Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Errors: 34
- Kernel Warnings: 25
- Boot result: PASS
- Errors: 1
1 10:01:36.362618 lava-dispatcher, installed at version: 2023.10
2 10:01:36.362867 start: 0 validate
3 10:01:36.363034 Start time: 2023-11-24 10:01:36.363025+00:00 (UTC)
4 10:01:36.363246 Using caching service: 'http://localhost/cache/?uri=%s'
5 10:01:36.363468 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-v4l2%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 10:01:36.630924 Using caching service: 'http://localhost/cache/?uri=%s'
7 10:01:36.631144 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 10:01:36.896153 Using caching service: 'http://localhost/cache/?uri=%s'
9 10:01:36.896340 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 10:01:37.161366 Using caching service: 'http://localhost/cache/?uri=%s'
11 10:01:37.161545 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 10:01:37.429918 validate duration: 1.07
14 10:01:37.430212 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 10:01:37.430310 start: 1.1 download-retry (timeout 00:10:00) [common]
16 10:01:37.430404 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 10:01:37.430537 Not decompressing ramdisk as can be used compressed.
18 10:01:37.430623 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-v4l2/20230623.0/arm64/rootfs.cpio.gz
19 10:01:37.430691 saving as /var/lib/lava/dispatcher/tmp/12073297/tftp-deploy-118urgzn/ramdisk/rootfs.cpio.gz
20 10:01:37.430755 total size: 26246609 (25 MB)
21 10:01:37.431933 progress 0 % (0 MB)
22 10:01:37.439017 progress 5 % (1 MB)
23 10:01:37.445894 progress 10 % (2 MB)
24 10:01:37.452721 progress 15 % (3 MB)
25 10:01:37.459675 progress 20 % (5 MB)
26 10:01:37.466546 progress 25 % (6 MB)
27 10:01:37.473400 progress 30 % (7 MB)
28 10:01:37.480360 progress 35 % (8 MB)
29 10:01:37.487295 progress 40 % (10 MB)
30 10:01:37.494251 progress 45 % (11 MB)
31 10:01:37.501287 progress 50 % (12 MB)
32 10:01:37.508739 progress 55 % (13 MB)
33 10:01:37.516490 progress 60 % (15 MB)
34 10:01:37.524061 progress 65 % (16 MB)
35 10:01:37.531951 progress 70 % (17 MB)
36 10:01:37.538989 progress 75 % (18 MB)
37 10:01:37.546216 progress 80 % (20 MB)
38 10:01:37.553167 progress 85 % (21 MB)
39 10:01:37.560260 progress 90 % (22 MB)
40 10:01:37.567139 progress 95 % (23 MB)
41 10:01:37.574226 progress 100 % (25 MB)
42 10:01:37.574475 25 MB downloaded in 0.14 s (174.16 MB/s)
43 10:01:37.574635 end: 1.1.1 http-download (duration 00:00:00) [common]
45 10:01:37.574928 end: 1.1 download-retry (duration 00:00:00) [common]
46 10:01:37.575047 start: 1.2 download-retry (timeout 00:10:00) [common]
47 10:01:37.575162 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 10:01:37.575346 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 10:01:37.575437 saving as /var/lib/lava/dispatcher/tmp/12073297/tftp-deploy-118urgzn/kernel/Image
50 10:01:37.575501 total size: 49107456 (46 MB)
51 10:01:37.575564 No compression specified
52 10:01:37.576662 progress 0 % (0 MB)
53 10:01:37.589930 progress 5 % (2 MB)
54 10:01:37.603341 progress 10 % (4 MB)
55 10:01:37.616159 progress 15 % (7 MB)
56 10:01:37.630088 progress 20 % (9 MB)
57 10:01:37.643325 progress 25 % (11 MB)
58 10:01:37.656383 progress 30 % (14 MB)
59 10:01:37.669415 progress 35 % (16 MB)
60 10:01:37.682406 progress 40 % (18 MB)
61 10:01:37.695396 progress 45 % (21 MB)
62 10:01:37.708410 progress 50 % (23 MB)
63 10:01:37.721476 progress 55 % (25 MB)
64 10:01:37.734485 progress 60 % (28 MB)
65 10:01:37.747500 progress 65 % (30 MB)
66 10:01:37.760652 progress 70 % (32 MB)
67 10:01:37.773466 progress 75 % (35 MB)
68 10:01:37.786441 progress 80 % (37 MB)
69 10:01:37.799467 progress 85 % (39 MB)
70 10:01:37.812531 progress 90 % (42 MB)
71 10:01:37.825450 progress 95 % (44 MB)
72 10:01:37.838610 progress 100 % (46 MB)
73 10:01:37.838864 46 MB downloaded in 0.26 s (177.83 MB/s)
74 10:01:37.839021 end: 1.2.1 http-download (duration 00:00:00) [common]
76 10:01:37.839255 end: 1.2 download-retry (duration 00:00:00) [common]
77 10:01:37.839347 start: 1.3 download-retry (timeout 00:10:00) [common]
78 10:01:37.839435 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 10:01:37.839575 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 10:01:37.839646 saving as /var/lib/lava/dispatcher/tmp/12073297/tftp-deploy-118urgzn/dtb/mt8192-asurada-spherion-r0.dtb
81 10:01:37.839723 total size: 47278 (0 MB)
82 10:01:37.839787 No compression specified
83 10:01:37.841027 progress 69 % (0 MB)
84 10:01:37.841307 progress 100 % (0 MB)
85 10:01:37.841466 0 MB downloaded in 0.00 s (25.92 MB/s)
86 10:01:37.841657 end: 1.3.1 http-download (duration 00:00:00) [common]
88 10:01:37.842066 end: 1.3 download-retry (duration 00:00:00) [common]
89 10:01:37.842155 start: 1.4 download-retry (timeout 00:10:00) [common]
90 10:01:37.842240 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 10:01:37.842364 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 10:01:37.842432 saving as /var/lib/lava/dispatcher/tmp/12073297/tftp-deploy-118urgzn/modules/modules.tar
93 10:01:37.842494 total size: 8622040 (8 MB)
94 10:01:37.842576 Using unxz to decompress xz
95 10:01:37.847093 progress 0 % (0 MB)
96 10:01:37.869260 progress 5 % (0 MB)
97 10:01:37.895394 progress 10 % (0 MB)
98 10:01:37.920773 progress 15 % (1 MB)
99 10:01:37.946361 progress 20 % (1 MB)
100 10:01:37.971022 progress 25 % (2 MB)
101 10:01:37.998172 progress 30 % (2 MB)
102 10:01:38.028550 progress 35 % (2 MB)
103 10:01:38.054987 progress 40 % (3 MB)
104 10:01:38.083714 progress 45 % (3 MB)
105 10:01:38.111380 progress 50 % (4 MB)
106 10:01:38.152674 progress 55 % (4 MB)
107 10:01:38.188870 progress 60 % (4 MB)
108 10:01:38.221614 progress 65 % (5 MB)
109 10:01:38.249635 progress 70 % (5 MB)
110 10:01:38.275684 progress 75 % (6 MB)
111 10:01:38.306414 progress 80 % (6 MB)
112 10:01:38.335421 progress 85 % (7 MB)
113 10:01:38.362482 progress 90 % (7 MB)
114 10:01:38.394926 progress 95 % (7 MB)
115 10:01:38.427781 progress 100 % (8 MB)
116 10:01:38.432915 8 MB downloaded in 0.59 s (13.93 MB/s)
117 10:01:38.433221 end: 1.4.1 http-download (duration 00:00:01) [common]
119 10:01:38.433664 end: 1.4 download-retry (duration 00:00:01) [common]
120 10:01:38.433766 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 10:01:38.433881 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 10:01:38.433968 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 10:01:38.434072 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 10:01:38.434327 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12073297/lava-overlay-n08cnt2z
125 10:01:38.434511 makedir: /var/lib/lava/dispatcher/tmp/12073297/lava-overlay-n08cnt2z/lava-12073297/bin
126 10:01:38.434661 makedir: /var/lib/lava/dispatcher/tmp/12073297/lava-overlay-n08cnt2z/lava-12073297/tests
127 10:01:38.434804 makedir: /var/lib/lava/dispatcher/tmp/12073297/lava-overlay-n08cnt2z/lava-12073297/results
128 10:01:38.434962 Creating /var/lib/lava/dispatcher/tmp/12073297/lava-overlay-n08cnt2z/lava-12073297/bin/lava-add-keys
129 10:01:38.435166 Creating /var/lib/lava/dispatcher/tmp/12073297/lava-overlay-n08cnt2z/lava-12073297/bin/lava-add-sources
130 10:01:38.435346 Creating /var/lib/lava/dispatcher/tmp/12073297/lava-overlay-n08cnt2z/lava-12073297/bin/lava-background-process-start
131 10:01:38.435528 Creating /var/lib/lava/dispatcher/tmp/12073297/lava-overlay-n08cnt2z/lava-12073297/bin/lava-background-process-stop
132 10:01:38.435695 Creating /var/lib/lava/dispatcher/tmp/12073297/lava-overlay-n08cnt2z/lava-12073297/bin/lava-common-functions
133 10:01:38.435871 Creating /var/lib/lava/dispatcher/tmp/12073297/lava-overlay-n08cnt2z/lava-12073297/bin/lava-echo-ipv4
134 10:01:38.436046 Creating /var/lib/lava/dispatcher/tmp/12073297/lava-overlay-n08cnt2z/lava-12073297/bin/lava-install-packages
135 10:01:38.436219 Creating /var/lib/lava/dispatcher/tmp/12073297/lava-overlay-n08cnt2z/lava-12073297/bin/lava-installed-packages
136 10:01:38.436395 Creating /var/lib/lava/dispatcher/tmp/12073297/lava-overlay-n08cnt2z/lava-12073297/bin/lava-os-build
137 10:01:38.436568 Creating /var/lib/lava/dispatcher/tmp/12073297/lava-overlay-n08cnt2z/lava-12073297/bin/lava-probe-channel
138 10:01:38.436741 Creating /var/lib/lava/dispatcher/tmp/12073297/lava-overlay-n08cnt2z/lava-12073297/bin/lava-probe-ip
139 10:01:38.436910 Creating /var/lib/lava/dispatcher/tmp/12073297/lava-overlay-n08cnt2z/lava-12073297/bin/lava-target-ip
140 10:01:38.437046 Creating /var/lib/lava/dispatcher/tmp/12073297/lava-overlay-n08cnt2z/lava-12073297/bin/lava-target-mac
141 10:01:38.437217 Creating /var/lib/lava/dispatcher/tmp/12073297/lava-overlay-n08cnt2z/lava-12073297/bin/lava-target-storage
142 10:01:38.437398 Creating /var/lib/lava/dispatcher/tmp/12073297/lava-overlay-n08cnt2z/lava-12073297/bin/lava-test-case
143 10:01:38.437571 Creating /var/lib/lava/dispatcher/tmp/12073297/lava-overlay-n08cnt2z/lava-12073297/bin/lava-test-event
144 10:01:38.437732 Creating /var/lib/lava/dispatcher/tmp/12073297/lava-overlay-n08cnt2z/lava-12073297/bin/lava-test-feedback
145 10:01:38.437876 Creating /var/lib/lava/dispatcher/tmp/12073297/lava-overlay-n08cnt2z/lava-12073297/bin/lava-test-raise
146 10:01:38.438047 Creating /var/lib/lava/dispatcher/tmp/12073297/lava-overlay-n08cnt2z/lava-12073297/bin/lava-test-reference
147 10:01:38.438199 Creating /var/lib/lava/dispatcher/tmp/12073297/lava-overlay-n08cnt2z/lava-12073297/bin/lava-test-runner
148 10:01:38.438336 Creating /var/lib/lava/dispatcher/tmp/12073297/lava-overlay-n08cnt2z/lava-12073297/bin/lava-test-set
149 10:01:38.438471 Creating /var/lib/lava/dispatcher/tmp/12073297/lava-overlay-n08cnt2z/lava-12073297/bin/lava-test-shell
150 10:01:38.438609 Updating /var/lib/lava/dispatcher/tmp/12073297/lava-overlay-n08cnt2z/lava-12073297/bin/lava-install-packages (oe)
151 10:01:38.438771 Updating /var/lib/lava/dispatcher/tmp/12073297/lava-overlay-n08cnt2z/lava-12073297/bin/lava-installed-packages (oe)
152 10:01:38.438907 Creating /var/lib/lava/dispatcher/tmp/12073297/lava-overlay-n08cnt2z/lava-12073297/environment
153 10:01:38.439014 LAVA metadata
154 10:01:38.439091 - LAVA_JOB_ID=12073297
155 10:01:38.439159 - LAVA_DISPATCHER_IP=192.168.201.1
156 10:01:38.439278 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 10:01:38.439348 skipped lava-vland-overlay
158 10:01:38.439427 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 10:01:38.439509 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 10:01:38.439579 skipped lava-multinode-overlay
161 10:01:38.439659 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 10:01:38.439745 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 10:01:38.439827 Loading test definitions
164 10:01:38.439923 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 10:01:38.439999 Using /lava-12073297 at stage 0
166 10:01:38.440319 uuid=12073297_1.5.2.3.1 testdef=None
167 10:01:38.440410 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 10:01:38.440500 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 10:01:38.441033 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 10:01:38.441261 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 10:01:38.441914 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 10:01:38.442184 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 10:01:38.442875 runner path: /var/lib/lava/dispatcher/tmp/12073297/lava-overlay-n08cnt2z/lava-12073297/0/tests/0_v4l2-compliance-uvc test_uuid 12073297_1.5.2.3.1
176 10:01:38.443074 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 10:01:38.443321 Creating lava-test-runner.conf files
179 10:01:38.443398 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12073297/lava-overlay-n08cnt2z/lava-12073297/0 for stage 0
180 10:01:38.443525 - 0_v4l2-compliance-uvc
181 10:01:38.443669 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 10:01:38.443797 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 10:01:38.452475 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 10:01:38.452650 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 10:01:38.452772 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 10:01:38.452901 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 10:01:38.453037 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 10:01:39.192627 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 10:01:39.193016 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 10:01:39.193142 extracting modules file /var/lib/lava/dispatcher/tmp/12073297/tftp-deploy-118urgzn/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12073297/extract-overlay-ramdisk-y64obwi1/ramdisk
191 10:01:39.437798 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 10:01:39.437977 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 10:01:39.438087 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12073297/compress-overlay-lnzbok58/overlay-1.5.2.4.tar.gz to ramdisk
194 10:01:39.438211 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12073297/compress-overlay-lnzbok58/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12073297/extract-overlay-ramdisk-y64obwi1/ramdisk
195 10:01:39.445296 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 10:01:39.445432 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 10:01:39.445529 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 10:01:39.445923 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 10:01:39.446022 Building ramdisk /var/lib/lava/dispatcher/tmp/12073297/extract-overlay-ramdisk-y64obwi1/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12073297/extract-overlay-ramdisk-y64obwi1/ramdisk
200 10:01:40.068708 >> 228427 blocks
201 10:01:44.141165 rename /var/lib/lava/dispatcher/tmp/12073297/extract-overlay-ramdisk-y64obwi1/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12073297/tftp-deploy-118urgzn/ramdisk/ramdisk.cpio.gz
202 10:01:44.141672 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 10:01:44.141867 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
204 10:01:44.142027 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
205 10:01:44.142205 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12073297/tftp-deploy-118urgzn/kernel/Image'
206 10:01:57.501163 Returned 0 in 13 seconds
207 10:01:57.601936 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12073297/tftp-deploy-118urgzn/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12073297/tftp-deploy-118urgzn/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12073297/tftp-deploy-118urgzn/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12073297/tftp-deploy-118urgzn/kernel/image.itb
208 10:01:58.238819 output: FIT description: Kernel Image image with one or more FDT blobs
209 10:01:58.239294 output: Created: Fri Nov 24 10:01:58 2023
210 10:01:58.239405 output: Image 0 (kernel-1)
211 10:01:58.239507 output: Description:
212 10:01:58.239606 output: Created: Fri Nov 24 10:01:58 2023
213 10:01:58.239704 output: Type: Kernel Image
214 10:01:58.239799 output: Compression: lzma compressed
215 10:01:58.239890 output: Data Size: 11047542 Bytes = 10788.62 KiB = 10.54 MiB
216 10:01:58.239979 output: Architecture: AArch64
217 10:01:58.240066 output: OS: Linux
218 10:01:58.240157 output: Load Address: 0x00000000
219 10:01:58.240246 output: Entry Point: 0x00000000
220 10:01:58.240336 output: Hash algo: crc32
221 10:01:58.240421 output: Hash value: 2edffaa3
222 10:01:58.240512 output: Image 1 (fdt-1)
223 10:01:58.240600 output: Description: mt8192-asurada-spherion-r0
224 10:01:58.240686 output: Created: Fri Nov 24 10:01:58 2023
225 10:01:58.240772 output: Type: Flat Device Tree
226 10:01:58.240858 output: Compression: uncompressed
227 10:01:58.240943 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 10:01:58.241044 output: Architecture: AArch64
229 10:01:58.241133 output: Hash algo: crc32
230 10:01:58.241219 output: Hash value: cc4352de
231 10:01:58.241305 output: Image 2 (ramdisk-1)
232 10:01:58.241391 output: Description: unavailable
233 10:01:58.241475 output: Created: Fri Nov 24 10:01:58 2023
234 10:01:58.241560 output: Type: RAMDisk Image
235 10:01:58.241657 output: Compression: Unknown Compression
236 10:01:58.241743 output: Data Size: 39357677 Bytes = 38435.23 KiB = 37.53 MiB
237 10:01:58.241829 output: Architecture: AArch64
238 10:01:58.241915 output: OS: Linux
239 10:01:58.242000 output: Load Address: unavailable
240 10:01:58.242088 output: Entry Point: unavailable
241 10:01:58.242177 output: Hash algo: crc32
242 10:01:58.242279 output: Hash value: 973b06a2
243 10:01:58.242372 output: Default Configuration: 'conf-1'
244 10:01:58.242459 output: Configuration 0 (conf-1)
245 10:01:58.242545 output: Description: mt8192-asurada-spherion-r0
246 10:01:58.242628 output: Kernel: kernel-1
247 10:01:58.242710 output: Init Ramdisk: ramdisk-1
248 10:01:58.242797 output: FDT: fdt-1
249 10:01:58.242884 output: Loadables: kernel-1
250 10:01:58.242969 output:
251 10:01:58.243246 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 10:01:58.243401 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 10:01:58.243557 end: 1.5 prepare-tftp-overlay (duration 00:00:20) [common]
254 10:01:58.243703 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:39) [common]
255 10:01:58.243823 No LXC device requested
256 10:01:58.243948 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 10:01:58.244075 start: 1.7 deploy-device-env (timeout 00:09:39) [common]
258 10:01:58.244196 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 10:01:58.244305 Checking files for TFTP limit of 4294967296 bytes.
260 10:01:58.245011 end: 1 tftp-deploy (duration 00:00:21) [common]
261 10:01:58.245163 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 10:01:58.245295 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 10:01:58.245471 substitutions:
264 10:01:58.245571 - {DTB}: 12073297/tftp-deploy-118urgzn/dtb/mt8192-asurada-spherion-r0.dtb
265 10:01:58.245676 - {INITRD}: 12073297/tftp-deploy-118urgzn/ramdisk/ramdisk.cpio.gz
266 10:01:58.245768 - {KERNEL}: 12073297/tftp-deploy-118urgzn/kernel/Image
267 10:01:58.245858 - {LAVA_MAC}: None
268 10:01:58.245948 - {PRESEED_CONFIG}: None
269 10:01:58.246039 - {PRESEED_LOCAL}: None
270 10:01:58.246128 - {RAMDISK}: 12073297/tftp-deploy-118urgzn/ramdisk/ramdisk.cpio.gz
271 10:01:58.246217 - {ROOT_PART}: None
272 10:01:58.246303 - {ROOT}: None
273 10:01:58.246390 - {SERVER_IP}: 192.168.201.1
274 10:01:58.246476 - {TEE}: None
275 10:01:58.246564 Parsed boot commands:
276 10:01:58.246650 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 10:01:58.246910 Parsed boot commands: tftpboot 192.168.201.1 12073297/tftp-deploy-118urgzn/kernel/image.itb 12073297/tftp-deploy-118urgzn/kernel/cmdline
278 10:01:58.247048 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 10:01:58.247179 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 10:01:58.247326 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 10:01:58.247457 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 10:01:58.247567 Not connected, no need to disconnect.
283 10:01:58.247681 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 10:01:58.247810 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 10:01:58.247913 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
286 10:01:58.252943 Setting prompt string to ['lava-test: # ']
287 10:01:58.253518 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 10:01:58.253710 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 10:01:58.253864 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 10:01:58.254000 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 10:01:58.254322 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
292 10:02:03.384673 >> Command sent successfully.
293 10:02:03.387182 Returned 0 in 5 seconds
294 10:02:03.487665 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 10:02:03.488056 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 10:02:03.488181 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 10:02:03.488269 Setting prompt string to 'Starting depthcharge on Spherion...'
299 10:02:03.488335 Changing prompt to 'Starting depthcharge on Spherion...'
300 10:02:03.488404 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 10:02:03.488741 [Enter `^Ec?' for help]
302 10:02:03.660507
303 10:02:03.660661
304 10:02:03.660735 F0: 102B 0000
305 10:02:03.660822
306 10:02:03.660899 F3: 1001 0000 [0200]
307 10:02:03.660989
308 10:02:03.663743 F3: 1001 0000
309 10:02:03.663863
310 10:02:03.663931 F7: 102D 0000
311 10:02:03.663992
312 10:02:03.667312 F1: 0000 0000
313 10:02:03.667398
314 10:02:03.667467 V0: 0000 0000 [0001]
315 10:02:03.667532
316 10:02:03.667590 00: 0007 8000
317 10:02:03.667652
318 10:02:03.670941 01: 0000 0000
319 10:02:03.671055
320 10:02:03.671144 BP: 0C00 0209 [0000]
321 10:02:03.671207
322 10:02:03.674779 G0: 1182 0000
323 10:02:03.674891
324 10:02:03.674985 EC: 0000 0021 [4000]
325 10:02:03.675074
326 10:02:03.678177 S7: 0000 0000 [0000]
327 10:02:03.678265
328 10:02:03.678331 CC: 0000 0000 [0001]
329 10:02:03.678412
330 10:02:03.681471 T0: 0000 0040 [010F]
331 10:02:03.681600
332 10:02:03.681687 Jump to BL
333 10:02:03.681780
334 10:02:03.707678
335 10:02:03.707820
336 10:02:03.707932
337 10:02:03.715118 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 10:02:03.718831 ARM64: Exception handlers installed.
339 10:02:03.722309 ARM64: Testing exception
340 10:02:03.726067 ARM64: Done test exception
341 10:02:03.732990 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 10:02:03.740491 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 10:02:03.747534 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 10:02:03.757943 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 10:02:03.764447 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 10:02:03.774862 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 10:02:03.785502 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 10:02:03.792157 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 10:02:03.810260 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 10:02:03.813406 WDT: Last reset was cold boot
351 10:02:03.816487 SPI1(PAD0) initialized at 2873684 Hz
352 10:02:03.819894 SPI5(PAD0) initialized at 992727 Hz
353 10:02:03.823376 VBOOT: Loading verstage.
354 10:02:03.829881 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 10:02:03.833548 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 10:02:03.836791 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 10:02:03.840077 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 10:02:03.847515 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 10:02:03.854420 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 10:02:03.865284 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
361 10:02:03.865408
362 10:02:03.865479
363 10:02:03.875875 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 10:02:03.878944 ARM64: Exception handlers installed.
365 10:02:03.882653 ARM64: Testing exception
366 10:02:03.882742 ARM64: Done test exception
367 10:02:03.885789 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 10:02:03.892223 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 10:02:03.906473 Probing TPM: . done!
370 10:02:03.906592 TPM ready after 0 ms
371 10:02:03.913822 Connected to device vid:did:rid of 1ae0:0028:00
372 10:02:03.920576 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 10:02:03.980037 Initialized TPM device CR50 revision 0
374 10:02:03.991881 tlcl_send_startup: Startup return code is 0
375 10:02:03.992006 TPM: setup succeeded
376 10:02:04.003060 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 10:02:04.011964 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 10:02:04.024918 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 10:02:04.033312 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 10:02:04.036721 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 10:02:04.040599 in-header: 03 07 00 00 08 00 00 00
382 10:02:04.044318 in-data: aa e4 47 04 13 02 00 00
383 10:02:04.047884 Chrome EC: UHEPI supported
384 10:02:04.055195 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 10:02:04.058955 in-header: 03 95 00 00 08 00 00 00
386 10:02:04.059068 in-data: 18 20 20 08 00 00 00 00
387 10:02:04.062686 Phase 1
388 10:02:04.065926 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 10:02:04.073520 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 10:02:04.076907 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 10:02:04.080657 Recovery requested (1009000e)
392 10:02:04.089065 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 10:02:04.094144 tlcl_extend: response is 0
394 10:02:04.104069 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 10:02:04.109627 tlcl_extend: response is 0
396 10:02:04.116511 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 10:02:04.136392 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 10:02:04.142984 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 10:02:04.143093
400 10:02:04.143161
401 10:02:04.152856 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 10:02:04.156702 ARM64: Exception handlers installed.
403 10:02:04.159938 ARM64: Testing exception
404 10:02:04.160027 ARM64: Done test exception
405 10:02:04.181849 pmic_efuse_setting: Set efuses in 11 msecs
406 10:02:04.185301 pmwrap_interface_init: Select PMIF_VLD_RDY
407 10:02:04.192295 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 10:02:04.195029 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 10:02:04.203143 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 10:02:04.206325 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 10:02:04.210437 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 10:02:04.213613 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 10:02:04.221950 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 10:02:04.225545 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 10:02:04.229268 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 10:02:04.232984 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 10:02:04.240458 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 10:02:04.244230 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 10:02:04.248027 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 10:02:04.255710 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 10:02:04.259374 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 10:02:04.266699 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 10:02:04.270638 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 10:02:04.278345 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 10:02:04.282293 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 10:02:04.290025 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 10:02:04.293627 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 10:02:04.300565 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 10:02:04.304218 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 10:02:04.312164 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 10:02:04.316354 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 10:02:04.323337 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 10:02:04.326957 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 10:02:04.330891 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 10:02:04.334574 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 10:02:04.341909 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 10:02:04.345706 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 10:02:04.352642 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 10:02:04.356211 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 10:02:04.359718 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 10:02:04.367655 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 10:02:04.371334 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 10:02:04.375247 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 10:02:04.383238 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 10:02:04.386822 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 10:02:04.390374 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 10:02:04.394392 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 10:02:04.398001 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 10:02:04.401758 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 10:02:04.408792 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 10:02:04.412961 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 10:02:04.416758 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 10:02:04.420424 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 10:02:04.423797 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 10:02:04.427856 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 10:02:04.431413 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 10:02:04.435467 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 10:02:04.445959 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 10:02:04.453485 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 10:02:04.457231 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 10:02:04.464370 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 10:02:04.475427 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 10:02:04.479135 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 10:02:04.483167 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 10:02:04.486900 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 10:02:04.495376 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde71, sec=0x39
467 10:02:04.499174 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 10:02:04.507765 [RTC]rtc_osc_init,62: osc32con val = 0xde71
469 10:02:04.511032 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 10:02:04.519203 [RTC]rtc_get_frequency_meter,154: input=15, output=758
471 10:02:04.529029 [RTC]rtc_get_frequency_meter,154: input=23, output=941
472 10:02:04.538228 [RTC]rtc_get_frequency_meter,154: input=19, output=850
473 10:02:04.548319 [RTC]rtc_get_frequency_meter,154: input=17, output=805
474 10:02:04.557376 [RTC]rtc_get_frequency_meter,154: input=16, output=781
475 10:02:04.567479 [RTC]rtc_get_frequency_meter,154: input=16, output=781
476 10:02:04.576564 [RTC]rtc_get_frequency_meter,154: input=17, output=805
477 10:02:04.580171 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
478 10:02:04.587478 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
479 10:02:04.591518 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 10:02:04.595077 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
481 10:02:04.598735 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 10:02:04.603112 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
483 10:02:04.606417 ADC[4]: Raw value=905834 ID=7
484 10:02:04.606511 ADC[3]: Raw value=213810 ID=1
485 10:02:04.610059 RAM Code: 0x71
486 10:02:04.613904 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 10:02:04.617617 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 10:02:04.629367 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 10:02:04.632472 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 10:02:04.636109 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 10:02:04.641174 in-header: 03 07 00 00 08 00 00 00
492 10:02:04.645014 in-data: aa e4 47 04 13 02 00 00
493 10:02:04.648520 Chrome EC: UHEPI supported
494 10:02:04.656564 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 10:02:04.659929 in-header: 03 95 00 00 08 00 00 00
496 10:02:04.660052 in-data: 18 20 20 08 00 00 00 00
497 10:02:04.663784 MRC: failed to locate region type 0.
498 10:02:04.671509 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 10:02:04.675207 DRAM-K: Running full calibration
500 10:02:04.682638 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 10:02:04.682750 header.status = 0x0
502 10:02:04.685895 header.version = 0x6 (expected: 0x6)
503 10:02:04.689275 header.size = 0xd00 (expected: 0xd00)
504 10:02:04.689369 header.flags = 0x0
505 10:02:04.700624 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 10:02:04.714985 read SPI 0x72590 0x1c583: 12497 us, 9290 KB/s, 74.320 Mbps
507 10:02:04.722821 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 10:02:04.722982 dram_init: ddr_geometry: 2
509 10:02:04.726551 [EMI] MDL number = 2
510 10:02:04.730322 [EMI] Get MDL freq = 0
511 10:02:04.730459 dram_init: ddr_type: 0
512 10:02:04.734551 is_discrete_lpddr4: 1
513 10:02:04.734682 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 10:02:04.734791
515 10:02:04.737617
516 10:02:04.737768 [Bian_co] ETT version 0.0.0.1
517 10:02:04.741587 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 10:02:04.745583
519 10:02:04.749176 dramc_set_vcore_voltage set vcore to 650000
520 10:02:04.749303 Read voltage for 800, 4
521 10:02:04.749405 Vio18 = 0
522 10:02:04.752622 Vcore = 650000
523 10:02:04.752733 Vdram = 0
524 10:02:04.752822 Vddq = 0
525 10:02:04.752909 Vmddr = 0
526 10:02:04.756641 dram_init: config_dvfs: 1
527 10:02:04.760628 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 10:02:04.767894 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 10:02:04.771430 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
530 10:02:04.775644 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
531 10:02:04.778645 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
532 10:02:04.781931 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
533 10:02:04.785511 MEM_TYPE=3, freq_sel=18
534 10:02:04.789033 sv_algorithm_assistance_LP4_1600
535 10:02:04.791956 ============ PULL DRAM RESETB DOWN ============
536 10:02:04.795746 ========== PULL DRAM RESETB DOWN end =========
537 10:02:04.799418 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 10:02:04.802705 ===================================
539 10:02:04.806952 LPDDR4 DRAM CONFIGURATION
540 10:02:04.810076 ===================================
541 10:02:04.810170 EX_ROW_EN[0] = 0x0
542 10:02:04.814094 EX_ROW_EN[1] = 0x0
543 10:02:04.814216 LP4Y_EN = 0x0
544 10:02:04.817324 WORK_FSP = 0x0
545 10:02:04.817419 WL = 0x2
546 10:02:04.821291 RL = 0x2
547 10:02:04.821384 BL = 0x2
548 10:02:04.823904 RPST = 0x0
549 10:02:04.823995 RD_PRE = 0x0
550 10:02:04.827279 WR_PRE = 0x1
551 10:02:04.827372 WR_PST = 0x0
552 10:02:04.830909 DBI_WR = 0x0
553 10:02:04.834056 DBI_RD = 0x0
554 10:02:04.834140 OTF = 0x1
555 10:02:04.837637 ===================================
556 10:02:04.841404 ===================================
557 10:02:04.841520 ANA top config
558 10:02:04.845152 ===================================
559 10:02:04.848815 DLL_ASYNC_EN = 0
560 10:02:04.851747 ALL_SLAVE_EN = 1
561 10:02:04.851846 NEW_RANK_MODE = 1
562 10:02:04.855280 DLL_IDLE_MODE = 1
563 10:02:04.858532 LP45_APHY_COMB_EN = 1
564 10:02:04.861926 TX_ODT_DIS = 1
565 10:02:04.862043 NEW_8X_MODE = 1
566 10:02:04.865884 ===================================
567 10:02:04.869431 ===================================
568 10:02:04.872865 data_rate = 1600
569 10:02:04.876461 CKR = 1
570 10:02:04.879584 DQ_P2S_RATIO = 8
571 10:02:04.882592 ===================================
572 10:02:04.886366 CA_P2S_RATIO = 8
573 10:02:04.886486 DQ_CA_OPEN = 0
574 10:02:04.889537 DQ_SEMI_OPEN = 0
575 10:02:04.892479 CA_SEMI_OPEN = 0
576 10:02:04.896254 CA_FULL_RATE = 0
577 10:02:04.899710 DQ_CKDIV4_EN = 1
578 10:02:04.902711 CA_CKDIV4_EN = 1
579 10:02:04.902806 CA_PREDIV_EN = 0
580 10:02:04.906127 PH8_DLY = 0
581 10:02:04.909212 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 10:02:04.912990 DQ_AAMCK_DIV = 4
583 10:02:04.916052 CA_AAMCK_DIV = 4
584 10:02:04.916141 CA_ADMCK_DIV = 4
585 10:02:04.919783 DQ_TRACK_CA_EN = 0
586 10:02:04.922730 CA_PICK = 800
587 10:02:04.926329 CA_MCKIO = 800
588 10:02:04.929853 MCKIO_SEMI = 0
589 10:02:04.933950 PLL_FREQ = 3068
590 10:02:04.934063 DQ_UI_PI_RATIO = 32
591 10:02:04.937735 CA_UI_PI_RATIO = 0
592 10:02:04.941204 ===================================
593 10:02:04.945186 ===================================
594 10:02:04.948390 memory_type:LPDDR4
595 10:02:04.948480 GP_NUM : 10
596 10:02:04.952231 SRAM_EN : 1
597 10:02:04.952319 MD32_EN : 0
598 10:02:04.956205 ===================================
599 10:02:04.959429 [ANA_INIT] >>>>>>>>>>>>>>
600 10:02:04.963787 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 10:02:04.963885 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 10:02:04.966617 ===================================
603 10:02:04.969993 data_rate = 1600,PCW = 0X7600
604 10:02:04.973437 ===================================
605 10:02:04.976782 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 10:02:04.983460 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 10:02:04.990113 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 10:02:04.993387 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 10:02:04.996532 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 10:02:05.000614 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 10:02:05.003370 [ANA_INIT] flow start
612 10:02:05.003458 [ANA_INIT] PLL >>>>>>>>
613 10:02:05.007005 [ANA_INIT] PLL <<<<<<<<
614 10:02:05.009935 [ANA_INIT] MIDPI >>>>>>>>
615 10:02:05.010023 [ANA_INIT] MIDPI <<<<<<<<
616 10:02:05.013156 [ANA_INIT] DLL >>>>>>>>
617 10:02:05.016336 [ANA_INIT] flow end
618 10:02:05.020093 ============ LP4 DIFF to SE enter ============
619 10:02:05.023140 ============ LP4 DIFF to SE exit ============
620 10:02:05.026372 [ANA_INIT] <<<<<<<<<<<<<
621 10:02:05.030076 [Flow] Enable top DCM control >>>>>
622 10:02:05.033145 [Flow] Enable top DCM control <<<<<
623 10:02:05.036604 Enable DLL master slave shuffle
624 10:02:05.039780 ==============================================================
625 10:02:05.043460 Gating Mode config
626 10:02:05.049696 ==============================================================
627 10:02:05.049787 Config description:
628 10:02:05.060060 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 10:02:05.066472 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 10:02:05.070203 SELPH_MODE 0: By rank 1: By Phase
631 10:02:05.076622 ==============================================================
632 10:02:05.080360 GAT_TRACK_EN = 1
633 10:02:05.083196 RX_GATING_MODE = 2
634 10:02:05.086550 RX_GATING_TRACK_MODE = 2
635 10:02:05.090341 SELPH_MODE = 1
636 10:02:05.093474 PICG_EARLY_EN = 1
637 10:02:05.093618 VALID_LAT_VALUE = 1
638 10:02:05.100417 ==============================================================
639 10:02:05.103363 Enter into Gating configuration >>>>
640 10:02:05.106854 Exit from Gating configuration <<<<
641 10:02:05.110231 Enter into DVFS_PRE_config >>>>>
642 10:02:05.120325 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 10:02:05.123414 Exit from DVFS_PRE_config <<<<<
644 10:02:05.126492 Enter into PICG configuration >>>>
645 10:02:05.130200 Exit from PICG configuration <<<<
646 10:02:05.133407 [RX_INPUT] configuration >>>>>
647 10:02:05.137175 [RX_INPUT] configuration <<<<<
648 10:02:05.140410 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 10:02:05.147045 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 10:02:05.153944 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 10:02:05.160300 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 10:02:05.167138 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 10:02:05.170293 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 10:02:05.177173 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 10:02:05.180278 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 10:02:05.183559 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 10:02:05.186777 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 10:02:05.193888 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 10:02:05.196850 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 10:02:05.200463 ===================================
661 10:02:05.203390 LPDDR4 DRAM CONFIGURATION
662 10:02:05.206622 ===================================
663 10:02:05.206711 EX_ROW_EN[0] = 0x0
664 10:02:05.210032 EX_ROW_EN[1] = 0x0
665 10:02:05.210120 LP4Y_EN = 0x0
666 10:02:05.213683 WORK_FSP = 0x0
667 10:02:05.213774 WL = 0x2
668 10:02:05.216974 RL = 0x2
669 10:02:05.217062 BL = 0x2
670 10:02:05.220306 RPST = 0x0
671 10:02:05.220425 RD_PRE = 0x0
672 10:02:05.223737 WR_PRE = 0x1
673 10:02:05.223823 WR_PST = 0x0
674 10:02:05.226803 DBI_WR = 0x0
675 10:02:05.226887 DBI_RD = 0x0
676 10:02:05.230324 OTF = 0x1
677 10:02:05.233612 ===================================
678 10:02:05.237460 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 10:02:05.240396 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 10:02:05.247057 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 10:02:05.250727 ===================================
682 10:02:05.250819 LPDDR4 DRAM CONFIGURATION
683 10:02:05.254107 ===================================
684 10:02:05.257567 EX_ROW_EN[0] = 0x10
685 10:02:05.257681 EX_ROW_EN[1] = 0x0
686 10:02:05.260815 LP4Y_EN = 0x0
687 10:02:05.260916 WORK_FSP = 0x0
688 10:02:05.263892 WL = 0x2
689 10:02:05.267150 RL = 0x2
690 10:02:05.267236 BL = 0x2
691 10:02:05.271023 RPST = 0x0
692 10:02:05.271108 RD_PRE = 0x0
693 10:02:05.274266 WR_PRE = 0x1
694 10:02:05.274352 WR_PST = 0x0
695 10:02:05.277483 DBI_WR = 0x0
696 10:02:05.277615 DBI_RD = 0x0
697 10:02:05.280925 OTF = 0x1
698 10:02:05.284603 ===================================
699 10:02:05.287787 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 10:02:05.293023 nWR fixed to 40
701 10:02:05.296259 [ModeRegInit_LP4] CH0 RK0
702 10:02:05.296347 [ModeRegInit_LP4] CH0 RK1
703 10:02:05.299592 [ModeRegInit_LP4] CH1 RK0
704 10:02:05.302825 [ModeRegInit_LP4] CH1 RK1
705 10:02:05.302941 match AC timing 13
706 10:02:05.309088 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 10:02:05.312831 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 10:02:05.316224 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 10:02:05.322877 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 10:02:05.326080 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 10:02:05.326168 [EMI DOE] emi_dcm 0
712 10:02:05.332717 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 10:02:05.332803 ==
714 10:02:05.336348 Dram Type= 6, Freq= 0, CH_0, rank 0
715 10:02:05.339376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 10:02:05.339465 ==
717 10:02:05.346375 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 10:02:05.352584 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 10:02:05.360306 [CA 0] Center 36 (6~67) winsize 62
720 10:02:05.363618 [CA 1] Center 36 (6~67) winsize 62
721 10:02:05.366739 [CA 2] Center 34 (4~65) winsize 62
722 10:02:05.370087 [CA 3] Center 34 (4~64) winsize 61
723 10:02:05.373353 [CA 4] Center 33 (2~64) winsize 63
724 10:02:05.376923 [CA 5] Center 32 (2~62) winsize 61
725 10:02:05.377014
726 10:02:05.380642 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 10:02:05.380735
728 10:02:05.383823 [CATrainingPosCal] consider 1 rank data
729 10:02:05.386890 u2DelayCellTimex100 = 270/100 ps
730 10:02:05.390157 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
731 10:02:05.393830 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
732 10:02:05.400363 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
733 10:02:05.403720 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
734 10:02:05.406815 CA4 delay=33 (2~64),Diff = 1 PI (7 cell)
735 10:02:05.410784 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
736 10:02:05.410871
737 10:02:05.414097 CA PerBit enable=1, Macro0, CA PI delay=32
738 10:02:05.414183
739 10:02:05.417036 [CBTSetCACLKResult] CA Dly = 32
740 10:02:05.417123 CS Dly: 4 (0~35)
741 10:02:05.417191 ==
742 10:02:05.420166 Dram Type= 6, Freq= 0, CH_0, rank 1
743 10:02:05.427040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 10:02:05.427129 ==
745 10:02:05.430825 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 10:02:05.437164 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 10:02:05.446261 [CA 0] Center 36 (6~67) winsize 62
748 10:02:05.450136 [CA 1] Center 36 (6~67) winsize 62
749 10:02:05.453294 [CA 2] Center 34 (4~64) winsize 61
750 10:02:05.456379 [CA 3] Center 33 (3~64) winsize 62
751 10:02:05.460030 [CA 4] Center 32 (2~63) winsize 62
752 10:02:05.463619 [CA 5] Center 32 (2~63) winsize 62
753 10:02:05.463705
754 10:02:05.466396 [CmdBusTrainingLP45] Vref(ca) range 1: 32
755 10:02:05.466487
756 10:02:05.470150 [CATrainingPosCal] consider 2 rank data
757 10:02:05.473261 u2DelayCellTimex100 = 270/100 ps
758 10:02:05.476771 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
759 10:02:05.480248 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
760 10:02:05.486620 CA2 delay=34 (4~64),Diff = 2 PI (14 cell)
761 10:02:05.489954 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
762 10:02:05.493334 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
763 10:02:05.496582 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
764 10:02:05.496667
765 10:02:05.500384 CA PerBit enable=1, Macro0, CA PI delay=32
766 10:02:05.500469
767 10:02:05.503389 [CBTSetCACLKResult] CA Dly = 32
768 10:02:05.503474 CS Dly: 5 (0~37)
769 10:02:05.503541
770 10:02:05.507286 ----->DramcWriteLeveling(PI) begin...
771 10:02:05.507375 ==
772 10:02:05.510489 Dram Type= 6, Freq= 0, CH_0, rank 0
773 10:02:05.514309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 10:02:05.517451 ==
775 10:02:05.517535 Write leveling (Byte 0): 33 => 33
776 10:02:05.521266 Write leveling (Byte 1): 31 => 31
777 10:02:05.524993 DramcWriteLeveling(PI) end<-----
778 10:02:05.525078
779 10:02:05.525144 ==
780 10:02:05.528697 Dram Type= 6, Freq= 0, CH_0, rank 0
781 10:02:05.531792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 10:02:05.531876 ==
783 10:02:05.535593 [Gating] SW mode calibration
784 10:02:05.542731 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 10:02:05.549536 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 10:02:05.552666 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 10:02:05.556445 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
788 10:02:05.563006 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
789 10:02:05.566174 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 10:02:05.569254 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 10:02:05.576394 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 10:02:05.579286 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 10:02:05.583004 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 10:02:05.586588 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 10:02:05.592774 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 10:02:05.596065 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 10:02:05.599779 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 10:02:05.606417 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 10:02:05.609728 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 10:02:05.613020 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 10:02:05.620029 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 10:02:05.623084 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 10:02:05.626885 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
804 10:02:05.633522 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
805 10:02:05.636744 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
806 10:02:05.639726 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 10:02:05.643473 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 10:02:05.649879 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 10:02:05.653020 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 10:02:05.656906 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 10:02:05.663413 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 10:02:05.666747 0 9 8 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
813 10:02:05.670452 0 9 12 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
814 10:02:05.676936 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 10:02:05.680064 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 10:02:05.683932 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 10:02:05.690501 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 10:02:05.693387 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 10:02:05.696899 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
820 10:02:05.703578 0 10 8 | B1->B0 | 3030 2828 | 0 0 | (0 1) (1 1)
821 10:02:05.706731 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 10:02:05.709851 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 10:02:05.716978 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 10:02:05.720008 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 10:02:05.723699 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 10:02:05.726771 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 10:02:05.733477 0 11 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
828 10:02:05.737019 0 11 8 | B1->B0 | 2d2d 4242 | 0 0 | (0 0) (1 1)
829 10:02:05.739855 0 11 12 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
830 10:02:05.746871 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 10:02:05.750463 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 10:02:05.753525 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 10:02:05.759995 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 10:02:05.763763 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 10:02:05.766824 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 10:02:05.773534 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
837 10:02:05.776744 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
838 10:02:05.780416 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 10:02:05.786862 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 10:02:05.790605 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 10:02:05.793885 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 10:02:05.796893 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 10:02:05.803525 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 10:02:05.806766 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 10:02:05.810236 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 10:02:05.817110 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 10:02:05.820255 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 10:02:05.823655 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 10:02:05.830785 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 10:02:05.833819 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 10:02:05.837004 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 10:02:05.844013 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
853 10:02:05.844100 Total UI for P1: 0, mck2ui 16
854 10:02:05.850412 best dqsien dly found for B0: ( 0, 14, 6)
855 10:02:05.853691 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
856 10:02:05.857155 Total UI for P1: 0, mck2ui 16
857 10:02:05.861192 best dqsien dly found for B1: ( 0, 14, 8)
858 10:02:05.865069 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
859 10:02:05.868294 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
860 10:02:05.868379
861 10:02:05.872089 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
862 10:02:05.875130 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
863 10:02:05.878234 [Gating] SW calibration Done
864 10:02:05.878319 ==
865 10:02:05.881775 Dram Type= 6, Freq= 0, CH_0, rank 0
866 10:02:05.885121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 10:02:05.885207 ==
868 10:02:05.885275 RX Vref Scan: 0
869 10:02:05.888060
870 10:02:05.888145 RX Vref 0 -> 0, step: 1
871 10:02:05.888213
872 10:02:05.891826 RX Delay -130 -> 252, step: 16
873 10:02:05.894919 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
874 10:02:05.898541 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
875 10:02:05.904990 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
876 10:02:05.908382 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
877 10:02:05.911281 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
878 10:02:05.915092 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
879 10:02:05.918274 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
880 10:02:05.924903 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
881 10:02:05.928331 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
882 10:02:05.931800 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
883 10:02:05.934960 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
884 10:02:05.938247 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
885 10:02:05.945189 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
886 10:02:05.948433 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
887 10:02:05.951736 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
888 10:02:05.955411 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
889 10:02:05.955495 ==
890 10:02:05.958433 Dram Type= 6, Freq= 0, CH_0, rank 0
891 10:02:05.965330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 10:02:05.965417 ==
893 10:02:05.965484 DQS Delay:
894 10:02:05.965547 DQS0 = 0, DQS1 = 0
895 10:02:05.968656 DQM Delay:
896 10:02:05.968740 DQM0 = 88, DQM1 = 82
897 10:02:05.971803 DQ Delay:
898 10:02:05.975147 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
899 10:02:05.975232 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
900 10:02:05.978880 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
901 10:02:05.981907 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
902 10:02:05.981993
903 10:02:05.985097
904 10:02:05.985179 ==
905 10:02:05.988775 Dram Type= 6, Freq= 0, CH_0, rank 0
906 10:02:05.992239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 10:02:05.992326 ==
908 10:02:05.992394
909 10:02:05.992455
910 10:02:05.995597 TX Vref Scan disable
911 10:02:05.995681 == TX Byte 0 ==
912 10:02:05.999020 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
913 10:02:06.005350 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
914 10:02:06.005436 == TX Byte 1 ==
915 10:02:06.008745 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
916 10:02:06.015744 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
917 10:02:06.015829 ==
918 10:02:06.018764 Dram Type= 6, Freq= 0, CH_0, rank 0
919 10:02:06.022392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 10:02:06.022478 ==
921 10:02:06.035720 TX Vref=22, minBit 4, minWin=27, winSum=447
922 10:02:06.038521 TX Vref=24, minBit 8, minWin=27, winSum=450
923 10:02:06.042236 TX Vref=26, minBit 0, minWin=28, winSum=454
924 10:02:06.045442 TX Vref=28, minBit 8, minWin=28, winSum=458
925 10:02:06.049113 TX Vref=30, minBit 5, minWin=28, winSum=457
926 10:02:06.052353 TX Vref=32, minBit 6, minWin=28, winSum=455
927 10:02:06.058633 [TxChooseVref] Worse bit 8, Min win 28, Win sum 458, Final Vref 28
928 10:02:06.058729
929 10:02:06.062280 Final TX Range 1 Vref 28
930 10:02:06.062401
931 10:02:06.062469 ==
932 10:02:06.065352 Dram Type= 6, Freq= 0, CH_0, rank 0
933 10:02:06.068607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 10:02:06.068723 ==
935 10:02:06.068793
936 10:02:06.072374
937 10:02:06.072459 TX Vref Scan disable
938 10:02:06.075464 == TX Byte 0 ==
939 10:02:06.078984 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
940 10:02:06.082421 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
941 10:02:06.085729 == TX Byte 1 ==
942 10:02:06.088591 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
943 10:02:06.092310 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
944 10:02:06.092397
945 10:02:06.095353 [DATLAT]
946 10:02:06.095438 Freq=800, CH0 RK0
947 10:02:06.095505
948 10:02:06.098754 DATLAT Default: 0xa
949 10:02:06.098838 0, 0xFFFF, sum = 0
950 10:02:06.102012 1, 0xFFFF, sum = 0
951 10:02:06.102101 2, 0xFFFF, sum = 0
952 10:02:06.105796 3, 0xFFFF, sum = 0
953 10:02:06.105882 4, 0xFFFF, sum = 0
954 10:02:06.108872 5, 0xFFFF, sum = 0
955 10:02:06.108958 6, 0xFFFF, sum = 0
956 10:02:06.111986 7, 0xFFFF, sum = 0
957 10:02:06.112072 8, 0xFFFF, sum = 0
958 10:02:06.115732 9, 0x0, sum = 1
959 10:02:06.115818 10, 0x0, sum = 2
960 10:02:06.118952 11, 0x0, sum = 3
961 10:02:06.119037 12, 0x0, sum = 4
962 10:02:06.122013 best_step = 10
963 10:02:06.122098
964 10:02:06.122165 ==
965 10:02:06.125391 Dram Type= 6, Freq= 0, CH_0, rank 0
966 10:02:06.128977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 10:02:06.129062 ==
968 10:02:06.132119 RX Vref Scan: 1
969 10:02:06.132230
970 10:02:06.132325 Set Vref Range= 32 -> 127
971 10:02:06.132403
972 10:02:06.135268 RX Vref 32 -> 127, step: 1
973 10:02:06.135353
974 10:02:06.138993 RX Delay -79 -> 252, step: 8
975 10:02:06.139078
976 10:02:06.141966 Set Vref, RX VrefLevel [Byte0]: 32
977 10:02:06.145457 [Byte1]: 32
978 10:02:06.145568
979 10:02:06.149139 Set Vref, RX VrefLevel [Byte0]: 33
980 10:02:06.152413 [Byte1]: 33
981 10:02:06.155673
982 10:02:06.155756 Set Vref, RX VrefLevel [Byte0]: 34
983 10:02:06.158840 [Byte1]: 34
984 10:02:06.163437
985 10:02:06.163547 Set Vref, RX VrefLevel [Byte0]: 35
986 10:02:06.166583 [Byte1]: 35
987 10:02:06.170875
988 10:02:06.170959 Set Vref, RX VrefLevel [Byte0]: 36
989 10:02:06.174042 [Byte1]: 36
990 10:02:06.178657
991 10:02:06.178744 Set Vref, RX VrefLevel [Byte0]: 37
992 10:02:06.181735 [Byte1]: 37
993 10:02:06.185751
994 10:02:06.185841 Set Vref, RX VrefLevel [Byte0]: 38
995 10:02:06.189523 [Byte1]: 38
996 10:02:06.193153
997 10:02:06.193239 Set Vref, RX VrefLevel [Byte0]: 39
998 10:02:06.196742 [Byte1]: 39
999 10:02:06.201311
1000 10:02:06.201396 Set Vref, RX VrefLevel [Byte0]: 40
1001 10:02:06.204380 [Byte1]: 40
1002 10:02:06.208696
1003 10:02:06.208780 Set Vref, RX VrefLevel [Byte0]: 41
1004 10:02:06.212189 [Byte1]: 41
1005 10:02:06.215966
1006 10:02:06.216049 Set Vref, RX VrefLevel [Byte0]: 42
1007 10:02:06.219085 [Byte1]: 42
1008 10:02:06.223276
1009 10:02:06.223361 Set Vref, RX VrefLevel [Byte0]: 43
1010 10:02:06.226769 [Byte1]: 43
1011 10:02:06.230940
1012 10:02:06.231028 Set Vref, RX VrefLevel [Byte0]: 44
1013 10:02:06.234634 [Byte1]: 44
1014 10:02:06.238472
1015 10:02:06.238556 Set Vref, RX VrefLevel [Byte0]: 45
1016 10:02:06.242405 [Byte1]: 45
1017 10:02:06.246510
1018 10:02:06.246594 Set Vref, RX VrefLevel [Byte0]: 46
1019 10:02:06.249596 [Byte1]: 46
1020 10:02:06.253870
1021 10:02:06.253953 Set Vref, RX VrefLevel [Byte0]: 47
1022 10:02:06.256809 [Byte1]: 47
1023 10:02:06.261389
1024 10:02:06.261472 Set Vref, RX VrefLevel [Byte0]: 48
1025 10:02:06.264603 [Byte1]: 48
1026 10:02:06.269053
1027 10:02:06.269134 Set Vref, RX VrefLevel [Byte0]: 49
1028 10:02:06.272253 [Byte1]: 49
1029 10:02:06.276628
1030 10:02:06.276710 Set Vref, RX VrefLevel [Byte0]: 50
1031 10:02:06.279788 [Byte1]: 50
1032 10:02:06.284053
1033 10:02:06.284136 Set Vref, RX VrefLevel [Byte0]: 51
1034 10:02:06.287403 [Byte1]: 51
1035 10:02:06.291222
1036 10:02:06.291304 Set Vref, RX VrefLevel [Byte0]: 52
1037 10:02:06.295006 [Byte1]: 52
1038 10:02:06.298857
1039 10:02:06.298941 Set Vref, RX VrefLevel [Byte0]: 53
1040 10:02:06.302669 [Byte1]: 53
1041 10:02:06.306861
1042 10:02:06.306943 Set Vref, RX VrefLevel [Byte0]: 54
1043 10:02:06.309862 [Byte1]: 54
1044 10:02:06.314312
1045 10:02:06.314395 Set Vref, RX VrefLevel [Byte0]: 55
1046 10:02:06.317650 [Byte1]: 55
1047 10:02:06.321418
1048 10:02:06.321501 Set Vref, RX VrefLevel [Byte0]: 56
1049 10:02:06.324795 [Byte1]: 56
1050 10:02:06.329323
1051 10:02:06.329407 Set Vref, RX VrefLevel [Byte0]: 57
1052 10:02:06.332770 [Byte1]: 57
1053 10:02:06.336534
1054 10:02:06.336619 Set Vref, RX VrefLevel [Byte0]: 58
1055 10:02:06.339946 [Byte1]: 58
1056 10:02:06.344340
1057 10:02:06.344425 Set Vref, RX VrefLevel [Byte0]: 59
1058 10:02:06.347638 [Byte1]: 59
1059 10:02:06.351919
1060 10:02:06.352004 Set Vref, RX VrefLevel [Byte0]: 60
1061 10:02:06.355351 [Byte1]: 60
1062 10:02:06.359505
1063 10:02:06.359593 Set Vref, RX VrefLevel [Byte0]: 61
1064 10:02:06.362470 [Byte1]: 61
1065 10:02:06.367174
1066 10:02:06.367258 Set Vref, RX VrefLevel [Byte0]: 62
1067 10:02:06.370407 [Byte1]: 62
1068 10:02:06.374738
1069 10:02:06.374820 Set Vref, RX VrefLevel [Byte0]: 63
1070 10:02:06.377875 [Byte1]: 63
1071 10:02:06.382178
1072 10:02:06.382294 Set Vref, RX VrefLevel [Byte0]: 64
1073 10:02:06.385476 [Byte1]: 64
1074 10:02:06.389940
1075 10:02:06.390022 Set Vref, RX VrefLevel [Byte0]: 65
1076 10:02:06.393127 [Byte1]: 65
1077 10:02:06.396752
1078 10:02:06.396834 Set Vref, RX VrefLevel [Byte0]: 66
1079 10:02:06.400374 [Byte1]: 66
1080 10:02:06.404921
1081 10:02:06.405003 Set Vref, RX VrefLevel [Byte0]: 67
1082 10:02:06.408248 [Byte1]: 67
1083 10:02:06.412167
1084 10:02:06.412249 Set Vref, RX VrefLevel [Byte0]: 68
1085 10:02:06.415847 [Byte1]: 68
1086 10:02:06.419739
1087 10:02:06.419823 Set Vref, RX VrefLevel [Byte0]: 69
1088 10:02:06.423444 [Byte1]: 69
1089 10:02:06.427460
1090 10:02:06.427542 Set Vref, RX VrefLevel [Byte0]: 70
1091 10:02:06.431021 [Byte1]: 70
1092 10:02:06.434800
1093 10:02:06.434882 Set Vref, RX VrefLevel [Byte0]: 71
1094 10:02:06.438123 [Byte1]: 71
1095 10:02:06.442493
1096 10:02:06.442575 Set Vref, RX VrefLevel [Byte0]: 72
1097 10:02:06.445829 [Byte1]: 72
1098 10:02:06.449802
1099 10:02:06.449884 Set Vref, RX VrefLevel [Byte0]: 73
1100 10:02:06.453570 [Byte1]: 73
1101 10:02:06.457568
1102 10:02:06.457691 Set Vref, RX VrefLevel [Byte0]: 74
1103 10:02:06.463980 [Byte1]: 74
1104 10:02:06.464065
1105 10:02:06.467385 Set Vref, RX VrefLevel [Byte0]: 75
1106 10:02:06.470422 [Byte1]: 75
1107 10:02:06.470504
1108 10:02:06.473996 Set Vref, RX VrefLevel [Byte0]: 76
1109 10:02:06.477131 [Byte1]: 76
1110 10:02:06.477213
1111 10:02:06.480456 Set Vref, RX VrefLevel [Byte0]: 77
1112 10:02:06.483754 [Byte1]: 77
1113 10:02:06.487585
1114 10:02:06.487668 Set Vref, RX VrefLevel [Byte0]: 78
1115 10:02:06.491099 [Byte1]: 78
1116 10:02:06.495021
1117 10:02:06.495104 Set Vref, RX VrefLevel [Byte0]: 79
1118 10:02:06.498907 [Byte1]: 79
1119 10:02:06.502663
1120 10:02:06.502744 Final RX Vref Byte 0 = 61 to rank0
1121 10:02:06.506351 Final RX Vref Byte 1 = 61 to rank0
1122 10:02:06.509501 Final RX Vref Byte 0 = 61 to rank1
1123 10:02:06.512681 Final RX Vref Byte 1 = 61 to rank1==
1124 10:02:06.516576 Dram Type= 6, Freq= 0, CH_0, rank 0
1125 10:02:06.522938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1126 10:02:06.523024 ==
1127 10:02:06.523089 DQS Delay:
1128 10:02:06.523149 DQS0 = 0, DQS1 = 0
1129 10:02:06.526104 DQM Delay:
1130 10:02:06.526186 DQM0 = 92, DQM1 = 85
1131 10:02:06.529585 DQ Delay:
1132 10:02:06.532692 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1133 10:02:06.536019 DQ4 =96, DQ5 =80, DQ6 =100, DQ7 =100
1134 10:02:06.539225 DQ8 =76, DQ9 =76, DQ10 =84, DQ11 =76
1135 10:02:06.543066 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =92
1136 10:02:06.543149
1137 10:02:06.543212
1138 10:02:06.549354 [DQSOSCAuto] RK0, (LSB)MR18= 0x4c42, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 390 ps
1139 10:02:06.552692 CH0 RK0: MR19=606, MR18=4C42
1140 10:02:06.559759 CH0_RK0: MR19=0x606, MR18=0x4C42, DQSOSC=390, MR23=63, INC=97, DEC=64
1141 10:02:06.559849
1142 10:02:06.562862 ----->DramcWriteLeveling(PI) begin...
1143 10:02:06.562946 ==
1144 10:02:06.566035 Dram Type= 6, Freq= 0, CH_0, rank 1
1145 10:02:06.569756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1146 10:02:06.569839 ==
1147 10:02:06.572878 Write leveling (Byte 0): 35 => 35
1148 10:02:06.575927 Write leveling (Byte 1): 31 => 31
1149 10:02:06.579838 DramcWriteLeveling(PI) end<-----
1150 10:02:06.579920
1151 10:02:06.579984 ==
1152 10:02:06.623741 Dram Type= 6, Freq= 0, CH_0, rank 1
1153 10:02:06.624036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1154 10:02:06.624110 ==
1155 10:02:06.624172 [Gating] SW mode calibration
1156 10:02:06.624232 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1157 10:02:06.624303 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1158 10:02:06.624811 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1159 10:02:06.625119 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1160 10:02:06.625568 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1161 10:02:06.625677 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 10:02:06.625987 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 10:02:06.636804 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 10:02:06.637080 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 10:02:06.640175 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 10:02:06.640259 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 10:02:06.647203 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 10:02:06.650278 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 10:02:06.653480 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 10:02:06.660448 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 10:02:06.663858 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 10:02:06.666979 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 10:02:06.673904 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 10:02:06.677080 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 10:02:06.680188 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1176 10:02:06.687255 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1177 10:02:06.690521 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 10:02:06.693803 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 10:02:06.696767 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 10:02:06.703661 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 10:02:06.707241 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 10:02:06.710397 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 10:02:06.717081 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 10:02:06.720737 0 9 8 | B1->B0 | 2e2e 2f2f | 1 0 | (1 1) (0 0)
1185 10:02:06.723518 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 10:02:06.730194 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1187 10:02:06.733458 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1188 10:02:06.736988 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1189 10:02:06.743554 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1190 10:02:06.746968 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1191 10:02:06.750192 0 10 4 | B1->B0 | 3333 3434 | 1 1 | (0 0) (1 1)
1192 10:02:06.754663 0 10 8 | B1->B0 | 2929 2a2a | 0 0 | (0 0) (1 0)
1193 10:02:06.761783 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1194 10:02:06.765992 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 10:02:06.769312 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 10:02:06.772743 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 10:02:06.776635 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 10:02:06.784171 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 10:02:06.787310 0 11 4 | B1->B0 | 2424 2626 | 0 0 | (0 0) (0 0)
1200 10:02:06.790728 0 11 8 | B1->B0 | 3e3e 3535 | 0 0 | (0 0) (0 0)
1201 10:02:06.793892 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 10:02:06.800280 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 10:02:06.804069 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1204 10:02:06.807243 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1205 10:02:06.814047 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1206 10:02:06.817012 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1207 10:02:06.820218 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1208 10:02:06.826972 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1209 10:02:06.830834 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 10:02:06.833836 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 10:02:06.840262 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 10:02:06.844007 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 10:02:06.847026 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 10:02:06.853790 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 10:02:06.857417 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 10:02:06.860262 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 10:02:06.863764 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 10:02:06.870332 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 10:02:06.873604 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 10:02:06.877168 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 10:02:06.883667 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 10:02:06.887409 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1223 10:02:06.890499 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1224 10:02:06.897558 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1225 10:02:06.900629 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1226 10:02:06.903974 Total UI for P1: 0, mck2ui 16
1227 10:02:06.907598 best dqsien dly found for B0: ( 0, 14, 6)
1228 10:02:06.910578 Total UI for P1: 0, mck2ui 16
1229 10:02:06.914072 best dqsien dly found for B1: ( 0, 14, 10)
1230 10:02:06.917184 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1231 10:02:06.920587 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1232 10:02:06.920683
1233 10:02:06.924090 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1234 10:02:06.927288 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1235 10:02:06.930811 [Gating] SW calibration Done
1236 10:02:06.930895 ==
1237 10:02:06.933931 Dram Type= 6, Freq= 0, CH_0, rank 1
1238 10:02:06.937180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1239 10:02:06.940346 ==
1240 10:02:06.940427 RX Vref Scan: 0
1241 10:02:06.940492
1242 10:02:06.943654 RX Vref 0 -> 0, step: 1
1243 10:02:06.943737
1244 10:02:06.947330 RX Delay -130 -> 252, step: 16
1245 10:02:06.951071 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1246 10:02:06.954078 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1247 10:02:06.957166 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1248 10:02:06.960898 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1249 10:02:06.967073 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1250 10:02:06.970553 iDelay=222, Bit 5, Center 93 (-18 ~ 205) 224
1251 10:02:06.973712 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1252 10:02:06.977416 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1253 10:02:06.980721 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1254 10:02:06.984190 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
1255 10:02:06.990458 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1256 10:02:06.993937 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1257 10:02:06.997209 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1258 10:02:07.000730 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1259 10:02:07.007429 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1260 10:02:07.010533 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1261 10:02:07.010618 ==
1262 10:02:07.014223 Dram Type= 6, Freq= 0, CH_0, rank 1
1263 10:02:07.017388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1264 10:02:07.017472 ==
1265 10:02:07.017538 DQS Delay:
1266 10:02:07.020473 DQS0 = 0, DQS1 = 0
1267 10:02:07.020556 DQM Delay:
1268 10:02:07.023672 DQM0 = 94, DQM1 = 85
1269 10:02:07.023755 DQ Delay:
1270 10:02:07.027367 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
1271 10:02:07.030902 DQ4 =93, DQ5 =93, DQ6 =93, DQ7 =101
1272 10:02:07.034249 DQ8 =77, DQ9 =69, DQ10 =85, DQ11 =77
1273 10:02:07.037352 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1274 10:02:07.037436
1275 10:02:07.037501
1276 10:02:07.037561 ==
1277 10:02:07.040997 Dram Type= 6, Freq= 0, CH_0, rank 1
1278 10:02:07.044186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1279 10:02:07.047377 ==
1280 10:02:07.047461
1281 10:02:07.047526
1282 10:02:07.047587 TX Vref Scan disable
1283 10:02:07.050641 == TX Byte 0 ==
1284 10:02:07.054516 Update DQ dly =586 (2 ,2, 10) DQ OEN =(1 ,7)
1285 10:02:07.057388 Update DQM dly =586 (2 ,2, 10) DQM OEN =(1 ,7)
1286 10:02:07.060924 == TX Byte 1 ==
1287 10:02:07.064133 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1288 10:02:07.067336 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1289 10:02:07.071147 ==
1290 10:02:07.071230 Dram Type= 6, Freq= 0, CH_0, rank 1
1291 10:02:07.077786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1292 10:02:07.077871 ==
1293 10:02:07.089992 TX Vref=22, minBit 8, minWin=27, winSum=446
1294 10:02:07.093038 TX Vref=24, minBit 9, minWin=27, winSum=450
1295 10:02:07.096787 TX Vref=26, minBit 1, minWin=28, winSum=454
1296 10:02:07.100072 TX Vref=28, minBit 4, minWin=28, winSum=456
1297 10:02:07.103207 TX Vref=30, minBit 1, minWin=28, winSum=453
1298 10:02:07.109867 TX Vref=32, minBit 1, minWin=28, winSum=452
1299 10:02:07.113563 [TxChooseVref] Worse bit 4, Min win 28, Win sum 456, Final Vref 28
1300 10:02:07.113672
1301 10:02:07.116661 Final TX Range 1 Vref 28
1302 10:02:07.116743
1303 10:02:07.116808 ==
1304 10:02:07.119995 Dram Type= 6, Freq= 0, CH_0, rank 1
1305 10:02:07.122948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1306 10:02:07.123034 ==
1307 10:02:07.126764
1308 10:02:07.126845
1309 10:02:07.126908 TX Vref Scan disable
1310 10:02:07.129929 == TX Byte 0 ==
1311 10:02:07.133318 Update DQ dly =586 (2 ,2, 10) DQ OEN =(1 ,7)
1312 10:02:07.136896 Update DQM dly =586 (2 ,2, 10) DQM OEN =(1 ,7)
1313 10:02:07.139630 == TX Byte 1 ==
1314 10:02:07.143170 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1315 10:02:07.149839 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1316 10:02:07.149926
1317 10:02:07.149998 [DATLAT]
1318 10:02:07.150066 Freq=800, CH0 RK1
1319 10:02:07.150126
1320 10:02:07.153528 DATLAT Default: 0xa
1321 10:02:07.153635 0, 0xFFFF, sum = 0
1322 10:02:07.156932 1, 0xFFFF, sum = 0
1323 10:02:07.157015 2, 0xFFFF, sum = 0
1324 10:02:07.159874 3, 0xFFFF, sum = 0
1325 10:02:07.159958 4, 0xFFFF, sum = 0
1326 10:02:07.162974 5, 0xFFFF, sum = 0
1327 10:02:07.166639 6, 0xFFFF, sum = 0
1328 10:02:07.166723 7, 0xFFFF, sum = 0
1329 10:02:07.170056 8, 0xFFFF, sum = 0
1330 10:02:07.170140 9, 0x0, sum = 1
1331 10:02:07.170207 10, 0x0, sum = 2
1332 10:02:07.173074 11, 0x0, sum = 3
1333 10:02:07.173157 12, 0x0, sum = 4
1334 10:02:07.176400 best_step = 10
1335 10:02:07.176482
1336 10:02:07.176549 ==
1337 10:02:07.180250 Dram Type= 6, Freq= 0, CH_0, rank 1
1338 10:02:07.183238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1339 10:02:07.183322 ==
1340 10:02:07.186399 RX Vref Scan: 0
1341 10:02:07.186485
1342 10:02:07.186550 RX Vref 0 -> 0, step: 1
1343 10:02:07.186610
1344 10:02:07.189549 RX Delay -79 -> 252, step: 8
1345 10:02:07.196687 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1346 10:02:07.199715 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1347 10:02:07.203780 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1348 10:02:07.206798 iDelay=209, Bit 3, Center 92 (-15 ~ 200) 216
1349 10:02:07.209873 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1350 10:02:07.216906 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1351 10:02:07.219996 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1352 10:02:07.223681 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1353 10:02:07.226792 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1354 10:02:07.230302 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1355 10:02:07.236407 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1356 10:02:07.239900 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1357 10:02:07.243474 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
1358 10:02:07.246383 iDelay=209, Bit 13, Center 88 (-15 ~ 192) 208
1359 10:02:07.250051 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1360 10:02:07.256787 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1361 10:02:07.256872 ==
1362 10:02:07.260427 Dram Type= 6, Freq= 0, CH_0, rank 1
1363 10:02:07.263308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1364 10:02:07.263394 ==
1365 10:02:07.263459 DQS Delay:
1366 10:02:07.267022 DQS0 = 0, DQS1 = 0
1367 10:02:07.267105 DQM Delay:
1368 10:02:07.270337 DQM0 = 92, DQM1 = 83
1369 10:02:07.270420 DQ Delay:
1370 10:02:07.273521 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =92
1371 10:02:07.276655 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1372 10:02:07.279656 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =76
1373 10:02:07.283074 DQ12 =88, DQ13 =88, DQ14 =92, DQ15 =92
1374 10:02:07.283156
1375 10:02:07.283220
1376 10:02:07.289743 [DQSOSCAuto] RK1, (LSB)MR18= 0x4415, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
1377 10:02:07.293473 CH0 RK1: MR19=606, MR18=4415
1378 10:02:07.299763 CH0_RK1: MR19=0x606, MR18=0x4415, DQSOSC=392, MR23=63, INC=96, DEC=64
1379 10:02:07.302902 [RxdqsGatingPostProcess] freq 800
1380 10:02:07.309920 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1381 10:02:07.313138 Pre-setting of DQS Precalculation
1382 10:02:07.316815 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1383 10:02:07.316892 ==
1384 10:02:07.320004 Dram Type= 6, Freq= 0, CH_1, rank 0
1385 10:02:07.323012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1386 10:02:07.323112 ==
1387 10:02:07.329954 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1388 10:02:07.336236 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1389 10:02:07.344662 [CA 0] Center 36 (6~67) winsize 62
1390 10:02:07.348063 [CA 1] Center 36 (6~67) winsize 62
1391 10:02:07.351613 [CA 2] Center 35 (5~65) winsize 61
1392 10:02:07.354976 [CA 3] Center 35 (5~65) winsize 61
1393 10:02:07.358429 [CA 4] Center 35 (5~65) winsize 61
1394 10:02:07.361808 [CA 5] Center 34 (4~65) winsize 62
1395 10:02:07.361927
1396 10:02:07.365225 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1397 10:02:07.365338
1398 10:02:07.368472 [CATrainingPosCal] consider 1 rank data
1399 10:02:07.371904 u2DelayCellTimex100 = 270/100 ps
1400 10:02:07.375198 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1401 10:02:07.379103 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1402 10:02:07.382361 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1403 10:02:07.385330 CA3 delay=35 (5~65),Diff = 1 PI (7 cell)
1404 10:02:07.392047 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1405 10:02:07.395518 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1406 10:02:07.395623
1407 10:02:07.398490 CA PerBit enable=1, Macro0, CA PI delay=34
1408 10:02:07.398567
1409 10:02:07.402305 [CBTSetCACLKResult] CA Dly = 34
1410 10:02:07.402403 CS Dly: 6 (0~37)
1411 10:02:07.402494 ==
1412 10:02:07.405147 Dram Type= 6, Freq= 0, CH_1, rank 1
1413 10:02:07.412092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1414 10:02:07.412193 ==
1415 10:02:07.415293 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1416 10:02:07.422517 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1417 10:02:07.431503 [CA 0] Center 36 (6~67) winsize 62
1418 10:02:07.435396 [CA 1] Center 37 (6~68) winsize 63
1419 10:02:07.439397 [CA 2] Center 35 (5~66) winsize 62
1420 10:02:07.443283 [CA 3] Center 35 (5~65) winsize 61
1421 10:02:07.447070 [CA 4] Center 35 (5~66) winsize 62
1422 10:02:07.447156 [CA 5] Center 35 (5~65) winsize 61
1423 10:02:07.447222
1424 10:02:07.450781 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1425 10:02:07.450868
1426 10:02:07.454415 [CATrainingPosCal] consider 2 rank data
1427 10:02:07.457660 u2DelayCellTimex100 = 270/100 ps
1428 10:02:07.460822 CA0 delay=36 (6~67),Diff = 1 PI (7 cell)
1429 10:02:07.463922 CA1 delay=36 (6~67),Diff = 1 PI (7 cell)
1430 10:02:07.470757 CA2 delay=35 (5~65),Diff = 0 PI (0 cell)
1431 10:02:07.474018 CA3 delay=35 (5~65),Diff = 0 PI (0 cell)
1432 10:02:07.477429 CA4 delay=35 (5~65),Diff = 0 PI (0 cell)
1433 10:02:07.480923 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
1434 10:02:07.481007
1435 10:02:07.484110 CA PerBit enable=1, Macro0, CA PI delay=35
1436 10:02:07.484211
1437 10:02:07.487405 [CBTSetCACLKResult] CA Dly = 35
1438 10:02:07.487488 CS Dly: 6 (0~38)
1439 10:02:07.487554
1440 10:02:07.490880 ----->DramcWriteLeveling(PI) begin...
1441 10:02:07.493784 ==
1442 10:02:07.497344 Dram Type= 6, Freq= 0, CH_1, rank 0
1443 10:02:07.500603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1444 10:02:07.500686 ==
1445 10:02:07.504230 Write leveling (Byte 0): 26 => 26
1446 10:02:07.507641 Write leveling (Byte 1): 27 => 27
1447 10:02:07.510436 DramcWriteLeveling(PI) end<-----
1448 10:02:07.510519
1449 10:02:07.510584 ==
1450 10:02:07.514084 Dram Type= 6, Freq= 0, CH_1, rank 0
1451 10:02:07.517228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1452 10:02:07.517311 ==
1453 10:02:07.521227 [Gating] SW mode calibration
1454 10:02:07.527622 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1455 10:02:07.530821 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1456 10:02:07.537846 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1457 10:02:07.541104 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1458 10:02:07.544371 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 10:02:07.550722 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 10:02:07.554045 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 10:02:07.557196 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 10:02:07.564023 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 10:02:07.567383 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 10:02:07.570595 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 10:02:07.577598 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 10:02:07.580828 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 10:02:07.583918 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 10:02:07.591122 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 10:02:07.594061 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 10:02:07.597558 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 10:02:07.600878 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 10:02:07.607654 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 10:02:07.610902 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1474 10:02:07.614190 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 10:02:07.620904 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 10:02:07.624395 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 10:02:07.627785 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 10:02:07.634435 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 10:02:07.637573 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 10:02:07.640820 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 10:02:07.647774 0 9 4 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
1482 10:02:07.651057 0 9 8 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
1483 10:02:07.654058 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 10:02:07.661062 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1485 10:02:07.664688 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1486 10:02:07.667913 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1487 10:02:07.674383 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1488 10:02:07.678066 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1489 10:02:07.681314 0 10 4 | B1->B0 | 3434 2f2f | 1 1 | (1 0) (1 1)
1490 10:02:07.684514 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1491 10:02:07.691341 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 10:02:07.694498 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 10:02:07.697763 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 10:02:07.704616 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 10:02:07.707724 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 10:02:07.711372 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 10:02:07.718141 0 11 4 | B1->B0 | 2828 3535 | 0 1 | (0 0) (0 0)
1498 10:02:07.721147 0 11 8 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1499 10:02:07.724648 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 10:02:07.731489 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 10:02:07.734774 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1502 10:02:07.737961 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1503 10:02:07.744502 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1504 10:02:07.748228 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1505 10:02:07.751536 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1506 10:02:07.754936 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 10:02:07.761455 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 10:02:07.765201 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 10:02:07.768235 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 10:02:07.774529 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 10:02:07.777829 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 10:02:07.781232 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 10:02:07.788204 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 10:02:07.791585 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 10:02:07.794929 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 10:02:07.801319 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 10:02:07.805089 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 10:02:07.808247 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 10:02:07.814625 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 10:02:07.818491 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1521 10:02:07.821609 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1522 10:02:07.824930 Total UI for P1: 0, mck2ui 16
1523 10:02:07.827958 best dqsien dly found for B0: ( 0, 14, 2)
1524 10:02:07.831291 Total UI for P1: 0, mck2ui 16
1525 10:02:07.834717 best dqsien dly found for B1: ( 0, 14, 2)
1526 10:02:07.837851 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1527 10:02:07.841756 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1528 10:02:07.841882
1529 10:02:07.844794 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1530 10:02:07.851465 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1531 10:02:07.851554 [Gating] SW calibration Done
1532 10:02:07.851622 ==
1533 10:02:07.854808 Dram Type= 6, Freq= 0, CH_1, rank 0
1534 10:02:07.861545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1535 10:02:07.861658 ==
1536 10:02:07.861754 RX Vref Scan: 0
1537 10:02:07.861845
1538 10:02:07.865042 RX Vref 0 -> 0, step: 1
1539 10:02:07.865164
1540 10:02:07.868328 RX Delay -130 -> 252, step: 16
1541 10:02:07.871527 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1542 10:02:07.874821 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1543 10:02:07.878097 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1544 10:02:07.881368 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1545 10:02:07.888319 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1546 10:02:07.891620 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1547 10:02:07.894909 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1548 10:02:07.897982 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1549 10:02:07.901959 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1550 10:02:07.907979 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1551 10:02:07.911600 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1552 10:02:07.914860 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1553 10:02:07.918767 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1554 10:02:07.921914 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1555 10:02:07.928403 iDelay=222, Bit 14, Center 101 (-2 ~ 205) 208
1556 10:02:07.931624 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1557 10:02:07.931712 ==
1558 10:02:07.935694 Dram Type= 6, Freq= 0, CH_1, rank 0
1559 10:02:07.938414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1560 10:02:07.938546 ==
1561 10:02:07.938626 DQS Delay:
1562 10:02:07.941538 DQS0 = 0, DQS1 = 0
1563 10:02:07.941668 DQM Delay:
1564 10:02:07.945250 DQM0 = 93, DQM1 = 90
1565 10:02:07.945362 DQ Delay:
1566 10:02:07.948367 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1567 10:02:07.952299 DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =93
1568 10:02:07.955442 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1569 10:02:07.958485 DQ12 =93, DQ13 =101, DQ14 =101, DQ15 =101
1570 10:02:07.958598
1571 10:02:07.958697
1572 10:02:07.958789 ==
1573 10:02:07.962223 Dram Type= 6, Freq= 0, CH_1, rank 0
1574 10:02:07.968883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1575 10:02:07.968993 ==
1576 10:02:07.969096
1577 10:02:07.969158
1578 10:02:07.969216 TX Vref Scan disable
1579 10:02:07.972012 == TX Byte 0 ==
1580 10:02:07.975421 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1581 10:02:07.978618 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1582 10:02:07.982348 == TX Byte 1 ==
1583 10:02:07.985285 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1584 10:02:07.988870 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1585 10:02:07.992219 ==
1586 10:02:07.995220 Dram Type= 6, Freq= 0, CH_1, rank 0
1587 10:02:07.999198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1588 10:02:07.999284 ==
1589 10:02:08.011223 TX Vref=22, minBit 1, minWin=26, winSum=436
1590 10:02:08.014238 TX Vref=24, minBit 0, minWin=26, winSum=438
1591 10:02:08.017811 TX Vref=26, minBit 0, minWin=27, winSum=442
1592 10:02:08.020721 TX Vref=28, minBit 3, minWin=26, winSum=445
1593 10:02:08.024376 TX Vref=30, minBit 1, minWin=27, winSum=447
1594 10:02:08.027595 TX Vref=32, minBit 0, minWin=27, winSum=442
1595 10:02:08.034462 [TxChooseVref] Worse bit 1, Min win 27, Win sum 447, Final Vref 30
1596 10:02:08.034551
1597 10:02:08.037590 Final TX Range 1 Vref 30
1598 10:02:08.037677
1599 10:02:08.037759 ==
1600 10:02:08.040807 Dram Type= 6, Freq= 0, CH_1, rank 0
1601 10:02:08.044079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1602 10:02:08.044164 ==
1603 10:02:08.044229
1604 10:02:08.047647
1605 10:02:08.047786 TX Vref Scan disable
1606 10:02:08.050650 == TX Byte 0 ==
1607 10:02:08.054387 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1608 10:02:08.061141 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1609 10:02:08.061244 == TX Byte 1 ==
1610 10:02:08.064311 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1611 10:02:08.070804 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1612 10:02:08.070903
1613 10:02:08.070970 [DATLAT]
1614 10:02:08.071031 Freq=800, CH1 RK0
1615 10:02:08.071091
1616 10:02:08.073995 DATLAT Default: 0xa
1617 10:02:08.074079 0, 0xFFFF, sum = 0
1618 10:02:08.077590 1, 0xFFFF, sum = 0
1619 10:02:08.077691 2, 0xFFFF, sum = 0
1620 10:02:08.080747 3, 0xFFFF, sum = 0
1621 10:02:08.080831 4, 0xFFFF, sum = 0
1622 10:02:08.084426 5, 0xFFFF, sum = 0
1623 10:02:08.087749 6, 0xFFFF, sum = 0
1624 10:02:08.087836 7, 0xFFFF, sum = 0
1625 10:02:08.090783 8, 0xFFFF, sum = 0
1626 10:02:08.090868 9, 0x0, sum = 1
1627 10:02:08.090939 10, 0x0, sum = 2
1628 10:02:08.093990 11, 0x0, sum = 3
1629 10:02:08.094112 12, 0x0, sum = 4
1630 10:02:08.097587 best_step = 10
1631 10:02:08.097685
1632 10:02:08.097751 ==
1633 10:02:08.101130 Dram Type= 6, Freq= 0, CH_1, rank 0
1634 10:02:08.104137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1635 10:02:08.104221 ==
1636 10:02:08.107744 RX Vref Scan: 1
1637 10:02:08.107827
1638 10:02:08.107892 Set Vref Range= 32 -> 127
1639 10:02:08.107953
1640 10:02:08.110920 RX Vref 32 -> 127, step: 1
1641 10:02:08.111108
1642 10:02:08.114712 RX Delay -79 -> 252, step: 8
1643 10:02:08.114795
1644 10:02:08.118062 Set Vref, RX VrefLevel [Byte0]: 32
1645 10:02:08.121212 [Byte1]: 32
1646 10:02:08.121299
1647 10:02:08.124242 Set Vref, RX VrefLevel [Byte0]: 33
1648 10:02:08.127776 [Byte1]: 33
1649 10:02:08.131181
1650 10:02:08.131348 Set Vref, RX VrefLevel [Byte0]: 34
1651 10:02:08.134891 [Byte1]: 34
1652 10:02:08.138633
1653 10:02:08.138753 Set Vref, RX VrefLevel [Byte0]: 35
1654 10:02:08.142004 [Byte1]: 35
1655 10:02:08.146287
1656 10:02:08.146454 Set Vref, RX VrefLevel [Byte0]: 36
1657 10:02:08.149747 [Byte1]: 36
1658 10:02:08.154098
1659 10:02:08.154246 Set Vref, RX VrefLevel [Byte0]: 37
1660 10:02:08.157229 [Byte1]: 37
1661 10:02:08.161689
1662 10:02:08.161805 Set Vref, RX VrefLevel [Byte0]: 38
1663 10:02:08.164662 [Byte1]: 38
1664 10:02:08.168722
1665 10:02:08.168813 Set Vref, RX VrefLevel [Byte0]: 39
1666 10:02:08.171947 [Byte1]: 39
1667 10:02:08.176405
1668 10:02:08.176489 Set Vref, RX VrefLevel [Byte0]: 40
1669 10:02:08.179643 [Byte1]: 40
1670 10:02:08.184154
1671 10:02:08.184244 Set Vref, RX VrefLevel [Byte0]: 41
1672 10:02:08.187061 [Byte1]: 41
1673 10:02:08.191341
1674 10:02:08.191428 Set Vref, RX VrefLevel [Byte0]: 42
1675 10:02:08.195223 [Byte1]: 42
1676 10:02:08.198861
1677 10:02:08.198945 Set Vref, RX VrefLevel [Byte0]: 43
1678 10:02:08.202114 [Byte1]: 43
1679 10:02:08.206441
1680 10:02:08.206526 Set Vref, RX VrefLevel [Byte0]: 44
1681 10:02:08.210316 [Byte1]: 44
1682 10:02:08.214244
1683 10:02:08.214329 Set Vref, RX VrefLevel [Byte0]: 45
1684 10:02:08.218026 [Byte1]: 45
1685 10:02:08.221798
1686 10:02:08.221881 Set Vref, RX VrefLevel [Byte0]: 46
1687 10:02:08.225246 [Byte1]: 46
1688 10:02:08.229532
1689 10:02:08.229685 Set Vref, RX VrefLevel [Byte0]: 47
1690 10:02:08.232861 [Byte1]: 47
1691 10:02:08.237222
1692 10:02:08.237382 Set Vref, RX VrefLevel [Byte0]: 48
1693 10:02:08.240136 [Byte1]: 48
1694 10:02:08.244197
1695 10:02:08.244287 Set Vref, RX VrefLevel [Byte0]: 49
1696 10:02:08.247759 [Byte1]: 49
1697 10:02:08.252114
1698 10:02:08.252206 Set Vref, RX VrefLevel [Byte0]: 50
1699 10:02:08.255360 [Byte1]: 50
1700 10:02:08.259384
1701 10:02:08.259477 Set Vref, RX VrefLevel [Byte0]: 51
1702 10:02:08.262583 [Byte1]: 51
1703 10:02:08.266901
1704 10:02:08.266995 Set Vref, RX VrefLevel [Byte0]: 52
1705 10:02:08.270070 [Byte1]: 52
1706 10:02:08.274304
1707 10:02:08.274394 Set Vref, RX VrefLevel [Byte0]: 53
1708 10:02:08.278093 [Byte1]: 53
1709 10:02:08.282518
1710 10:02:08.282645 Set Vref, RX VrefLevel [Byte0]: 54
1711 10:02:08.285644 [Byte1]: 54
1712 10:02:08.289783
1713 10:02:08.289892 Set Vref, RX VrefLevel [Byte0]: 55
1714 10:02:08.292802 [Byte1]: 55
1715 10:02:08.297233
1716 10:02:08.297338 Set Vref, RX VrefLevel [Byte0]: 56
1717 10:02:08.300817 [Byte1]: 56
1718 10:02:08.304675
1719 10:02:08.304764 Set Vref, RX VrefLevel [Byte0]: 57
1720 10:02:08.307681 [Byte1]: 57
1721 10:02:08.312321
1722 10:02:08.312439 Set Vref, RX VrefLevel [Byte0]: 58
1723 10:02:08.315537 [Byte1]: 58
1724 10:02:08.319544
1725 10:02:08.319654 Set Vref, RX VrefLevel [Byte0]: 59
1726 10:02:08.322833 [Byte1]: 59
1727 10:02:08.327330
1728 10:02:08.327419 Set Vref, RX VrefLevel [Byte0]: 60
1729 10:02:08.330946 [Byte1]: 60
1730 10:02:08.334906
1731 10:02:08.334998 Set Vref, RX VrefLevel [Byte0]: 61
1732 10:02:08.338162 [Byte1]: 61
1733 10:02:08.342777
1734 10:02:08.342895 Set Vref, RX VrefLevel [Byte0]: 62
1735 10:02:08.345942 [Byte1]: 62
1736 10:02:08.350356
1737 10:02:08.350442 Set Vref, RX VrefLevel [Byte0]: 63
1738 10:02:08.353371 [Byte1]: 63
1739 10:02:08.357515
1740 10:02:08.357628 Set Vref, RX VrefLevel [Byte0]: 64
1741 10:02:08.361144 [Byte1]: 64
1742 10:02:08.365065
1743 10:02:08.365156 Set Vref, RX VrefLevel [Byte0]: 65
1744 10:02:08.368703 [Byte1]: 65
1745 10:02:08.373045
1746 10:02:08.373158 Set Vref, RX VrefLevel [Byte0]: 66
1747 10:02:08.375662 [Byte1]: 66
1748 10:02:08.380200
1749 10:02:08.380319 Set Vref, RX VrefLevel [Byte0]: 67
1750 10:02:08.383262 [Byte1]: 67
1751 10:02:08.387585
1752 10:02:08.387697 Set Vref, RX VrefLevel [Byte0]: 68
1753 10:02:08.391445 [Byte1]: 68
1754 10:02:08.395355
1755 10:02:08.395512 Set Vref, RX VrefLevel [Byte0]: 69
1756 10:02:08.398424 [Byte1]: 69
1757 10:02:08.402680
1758 10:02:08.402775 Set Vref, RX VrefLevel [Byte0]: 70
1759 10:02:08.406134 [Byte1]: 70
1760 10:02:08.410411
1761 10:02:08.410506 Set Vref, RX VrefLevel [Byte0]: 71
1762 10:02:08.413617 [Byte1]: 71
1763 10:02:08.418089
1764 10:02:08.418178 Final RX Vref Byte 0 = 57 to rank0
1765 10:02:08.421261 Final RX Vref Byte 1 = 58 to rank0
1766 10:02:08.424986 Final RX Vref Byte 0 = 57 to rank1
1767 10:02:08.428138 Final RX Vref Byte 1 = 58 to rank1==
1768 10:02:08.431546 Dram Type= 6, Freq= 0, CH_1, rank 0
1769 10:02:08.434901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1770 10:02:08.438231 ==
1771 10:02:08.438318 DQS Delay:
1772 10:02:08.438384 DQS0 = 0, DQS1 = 0
1773 10:02:08.441248 DQM Delay:
1774 10:02:08.441358 DQM0 = 94, DQM1 = 89
1775 10:02:08.445049 DQ Delay:
1776 10:02:08.447939 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =92
1777 10:02:08.448031 DQ4 =92, DQ5 =108, DQ6 =104, DQ7 =92
1778 10:02:08.451701 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84
1779 10:02:08.458062 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1780 10:02:08.458167
1781 10:02:08.458234
1782 10:02:08.464884 [DQSOSCAuto] RK0, (LSB)MR18= 0x2d4a, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
1783 10:02:08.468130 CH1 RK0: MR19=606, MR18=2D4A
1784 10:02:08.474862 CH1_RK0: MR19=0x606, MR18=0x2D4A, DQSOSC=391, MR23=63, INC=96, DEC=64
1785 10:02:08.474951
1786 10:02:08.478131 ----->DramcWriteLeveling(PI) begin...
1787 10:02:08.478218 ==
1788 10:02:08.481553 Dram Type= 6, Freq= 0, CH_1, rank 1
1789 10:02:08.484678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1790 10:02:08.484765 ==
1791 10:02:08.488046 Write leveling (Byte 0): 25 => 25
1792 10:02:08.491695 Write leveling (Byte 1): 30 => 30
1793 10:02:08.495284 DramcWriteLeveling(PI) end<-----
1794 10:02:08.495372
1795 10:02:08.495438 ==
1796 10:02:08.498219 Dram Type= 6, Freq= 0, CH_1, rank 1
1797 10:02:08.501464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1798 10:02:08.501583 ==
1799 10:02:08.505150 [Gating] SW mode calibration
1800 10:02:08.511668 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1801 10:02:08.518525 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1802 10:02:08.521783 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1803 10:02:08.524963 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1804 10:02:08.531286 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1805 10:02:08.535048 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 10:02:08.538199 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 10:02:08.544782 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 10:02:08.547802 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 10:02:08.551669 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 10:02:08.557920 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 10:02:08.561128 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 10:02:08.564704 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 10:02:08.571334 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 10:02:08.574481 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 10:02:08.577752 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 10:02:08.581402 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 10:02:08.588012 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1818 10:02:08.591494 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1819 10:02:08.595085 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1820 10:02:08.601096 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1821 10:02:08.604793 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 10:02:08.607915 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 10:02:08.614811 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 10:02:08.617999 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 10:02:08.621239 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 10:02:08.627904 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 10:02:08.631068 0 9 4 | B1->B0 | 2a2a 2323 | 1 1 | (0 0) (1 1)
1828 10:02:08.635024 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1829 10:02:08.641416 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1830 10:02:08.644627 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1831 10:02:08.648404 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1832 10:02:08.655029 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1833 10:02:08.657849 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1834 10:02:08.661721 0 10 0 | B1->B0 | 3232 3434 | 1 1 | (1 0) (1 0)
1835 10:02:08.667987 0 10 4 | B1->B0 | 2727 3030 | 0 0 | (0 0) (0 1)
1836 10:02:08.671896 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1837 10:02:08.675057 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 10:02:08.678270 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 10:02:08.684601 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 10:02:08.688365 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 10:02:08.691583 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 10:02:08.698120 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 10:02:08.701363 0 11 4 | B1->B0 | 4040 2727 | 0 0 | (0 0) (0 0)
1844 10:02:08.704590 0 11 8 | B1->B0 | 4646 4141 | 0 0 | (0 0) (0 0)
1845 10:02:08.711442 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1846 10:02:08.714574 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1847 10:02:08.718275 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1848 10:02:08.724567 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1849 10:02:08.728491 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1850 10:02:08.731212 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1851 10:02:08.737992 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1852 10:02:08.741828 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1853 10:02:08.744667 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 10:02:08.751460 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 10:02:08.754827 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 10:02:08.758084 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 10:02:08.764445 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 10:02:08.768288 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 10:02:08.771719 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 10:02:08.774966 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 10:02:08.781223 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 10:02:08.785091 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 10:02:08.788524 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 10:02:08.794667 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 10:02:08.797850 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 10:02:08.801794 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 10:02:08.807738 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1868 10:02:08.811022 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1869 10:02:08.814592 Total UI for P1: 0, mck2ui 16
1870 10:02:08.818006 best dqsien dly found for B0: ( 0, 14, 4)
1871 10:02:08.821397 Total UI for P1: 0, mck2ui 16
1872 10:02:08.824911 best dqsien dly found for B1: ( 0, 14, 4)
1873 10:02:08.828254 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1874 10:02:08.831516 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1875 10:02:08.831642
1876 10:02:08.835118 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1877 10:02:08.838287 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1878 10:02:08.841550 [Gating] SW calibration Done
1879 10:02:08.841673 ==
1880 10:02:08.845166 Dram Type= 6, Freq= 0, CH_1, rank 1
1881 10:02:08.847943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1882 10:02:08.848033 ==
1883 10:02:08.851798 RX Vref Scan: 0
1884 10:02:08.851884
1885 10:02:08.854774 RX Vref 0 -> 0, step: 1
1886 10:02:08.854866
1887 10:02:08.854947 RX Delay -130 -> 252, step: 16
1888 10:02:08.861460 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1889 10:02:08.865014 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1890 10:02:08.868208 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1891 10:02:08.871475 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1892 10:02:08.874745 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1893 10:02:08.881739 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1894 10:02:08.884991 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1895 10:02:08.888089 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1896 10:02:08.891402 iDelay=222, Bit 8, Center 85 (-18 ~ 189) 208
1897 10:02:08.894626 iDelay=222, Bit 9, Center 85 (-18 ~ 189) 208
1898 10:02:08.901607 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1899 10:02:08.904854 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1900 10:02:08.908078 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1901 10:02:08.912018 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1902 10:02:08.915038 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1903 10:02:08.921355 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1904 10:02:08.921453 ==
1905 10:02:08.925188 Dram Type= 6, Freq= 0, CH_1, rank 1
1906 10:02:08.928191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1907 10:02:08.928280 ==
1908 10:02:08.928347 DQS Delay:
1909 10:02:08.931474 DQS0 = 0, DQS1 = 0
1910 10:02:08.931557 DQM Delay:
1911 10:02:08.934836 DQM0 = 93, DQM1 = 89
1912 10:02:08.934922 DQ Delay:
1913 10:02:08.938359 DQ0 =101, DQ1 =85, DQ2 =85, DQ3 =85
1914 10:02:08.941796 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1915 10:02:08.945195 DQ8 =85, DQ9 =85, DQ10 =85, DQ11 =85
1916 10:02:08.948686 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1917 10:02:08.948777
1918 10:02:08.948875
1919 10:02:08.948982 ==
1920 10:02:08.951318 Dram Type= 6, Freq= 0, CH_1, rank 1
1921 10:02:08.955076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1922 10:02:08.955188 ==
1923 10:02:08.958442
1924 10:02:08.958532
1925 10:02:08.958596 TX Vref Scan disable
1926 10:02:08.961531 == TX Byte 0 ==
1927 10:02:08.965153 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1928 10:02:08.968746 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1929 10:02:08.971884 == TX Byte 1 ==
1930 10:02:08.975299 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1931 10:02:08.978633 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1932 10:02:08.978787 ==
1933 10:02:08.981566 Dram Type= 6, Freq= 0, CH_1, rank 1
1934 10:02:08.988532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1935 10:02:08.988621 ==
1936 10:02:09.000938 TX Vref=22, minBit 0, minWin=27, winSum=442
1937 10:02:09.004089 TX Vref=24, minBit 0, minWin=27, winSum=445
1938 10:02:09.007244 TX Vref=26, minBit 0, minWin=27, winSum=447
1939 10:02:09.010444 TX Vref=28, minBit 0, minWin=27, winSum=446
1940 10:02:09.013804 TX Vref=30, minBit 0, minWin=27, winSum=449
1941 10:02:09.016991 TX Vref=32, minBit 0, minWin=27, winSum=449
1942 10:02:09.023859 [TxChooseVref] Worse bit 0, Min win 27, Win sum 449, Final Vref 30
1943 10:02:09.023964
1944 10:02:09.027330 Final TX Range 1 Vref 30
1945 10:02:09.027429
1946 10:02:09.027514 ==
1947 10:02:09.030253 Dram Type= 6, Freq= 0, CH_1, rank 1
1948 10:02:09.033548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1949 10:02:09.033679 ==
1950 10:02:09.033744
1951 10:02:09.037496
1952 10:02:09.037584 TX Vref Scan disable
1953 10:02:09.040714 == TX Byte 0 ==
1954 10:02:09.044094 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1955 10:02:09.047199 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1956 10:02:09.050414 == TX Byte 1 ==
1957 10:02:09.053853 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1958 10:02:09.057806 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1959 10:02:09.060786
1960 10:02:09.060877 [DATLAT]
1961 10:02:09.060952 Freq=800, CH1 RK1
1962 10:02:09.061022
1963 10:02:09.063775 DATLAT Default: 0xa
1964 10:02:09.063854 0, 0xFFFF, sum = 0
1965 10:02:09.067235 1, 0xFFFF, sum = 0
1966 10:02:09.067328 2, 0xFFFF, sum = 0
1967 10:02:09.070932 3, 0xFFFF, sum = 0
1968 10:02:09.071023 4, 0xFFFF, sum = 0
1969 10:02:09.074260 5, 0xFFFF, sum = 0
1970 10:02:09.074358 6, 0xFFFF, sum = 0
1971 10:02:09.077467 7, 0xFFFF, sum = 0
1972 10:02:09.077558 8, 0xFFFF, sum = 0
1973 10:02:09.080626 9, 0x0, sum = 1
1974 10:02:09.080710 10, 0x0, sum = 2
1975 10:02:09.084280 11, 0x0, sum = 3
1976 10:02:09.084365 12, 0x0, sum = 4
1977 10:02:09.087193 best_step = 10
1978 10:02:09.087279
1979 10:02:09.087353 ==
1980 10:02:09.090645 Dram Type= 6, Freq= 0, CH_1, rank 1
1981 10:02:09.093982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1982 10:02:09.094107 ==
1983 10:02:09.097155 RX Vref Scan: 0
1984 10:02:09.097248
1985 10:02:09.097350 RX Vref 0 -> 0, step: 1
1986 10:02:09.097460
1987 10:02:09.101080 RX Delay -63 -> 252, step: 8
1988 10:02:09.107429 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
1989 10:02:09.110729 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
1990 10:02:09.113802 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
1991 10:02:09.117782 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
1992 10:02:09.120961 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
1993 10:02:09.124102 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
1994 10:02:09.130845 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
1995 10:02:09.134079 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
1996 10:02:09.137918 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
1997 10:02:09.141081 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
1998 10:02:09.144291 iDelay=209, Bit 10, Center 92 (-15 ~ 200) 216
1999 10:02:09.147716 iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208
2000 10:02:09.154517 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2001 10:02:09.157713 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2002 10:02:09.160906 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2003 10:02:09.164783 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2004 10:02:09.164877 ==
2005 10:02:09.167919 Dram Type= 6, Freq= 0, CH_1, rank 1
2006 10:02:09.174264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2007 10:02:09.174383 ==
2008 10:02:09.174464 DQS Delay:
2009 10:02:09.174538 DQS0 = 0, DQS1 = 0
2010 10:02:09.177365 DQM Delay:
2011 10:02:09.177458 DQM0 = 97, DQM1 = 91
2012 10:02:09.181035 DQ Delay:
2013 10:02:09.184438 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2014 10:02:09.187814 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2015 10:02:09.190996 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =88
2016 10:02:09.194124 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2017 10:02:09.194210
2018 10:02:09.194295
2019 10:02:09.200841 [DQSOSCAuto] RK1, (LSB)MR18= 0x440e, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
2020 10:02:09.204308 CH1 RK1: MR19=606, MR18=440E
2021 10:02:09.210779 CH1_RK1: MR19=0x606, MR18=0x440E, DQSOSC=392, MR23=63, INC=96, DEC=64
2022 10:02:09.214561 [RxdqsGatingPostProcess] freq 800
2023 10:02:09.217668 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2024 10:02:09.220670 Pre-setting of DQS Precalculation
2025 10:02:09.227948 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2026 10:02:09.234064 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2027 10:02:09.240830 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2028 10:02:09.240935
2029 10:02:09.241022
2030 10:02:09.244702 [Calibration Summary] 1600 Mbps
2031 10:02:09.244785 CH 0, Rank 0
2032 10:02:09.248067 SW Impedance : PASS
2033 10:02:09.251221 DUTY Scan : NO K
2034 10:02:09.251309 ZQ Calibration : PASS
2035 10:02:09.254596 Jitter Meter : NO K
2036 10:02:09.257848 CBT Training : PASS
2037 10:02:09.257936 Write leveling : PASS
2038 10:02:09.261210 RX DQS gating : PASS
2039 10:02:09.264431 RX DQ/DQS(RDDQC) : PASS
2040 10:02:09.264523 TX DQ/DQS : PASS
2041 10:02:09.267536 RX DATLAT : PASS
2042 10:02:09.267624 RX DQ/DQS(Engine): PASS
2043 10:02:09.271279 TX OE : NO K
2044 10:02:09.271374 All Pass.
2045 10:02:09.271466
2046 10:02:09.274512 CH 0, Rank 1
2047 10:02:09.274595 SW Impedance : PASS
2048 10:02:09.277801 DUTY Scan : NO K
2049 10:02:09.281412 ZQ Calibration : PASS
2050 10:02:09.281535 Jitter Meter : NO K
2051 10:02:09.284760 CBT Training : PASS
2052 10:02:09.287922 Write leveling : PASS
2053 10:02:09.288010 RX DQS gating : PASS
2054 10:02:09.291514 RX DQ/DQS(RDDQC) : PASS
2055 10:02:09.294496 TX DQ/DQS : PASS
2056 10:02:09.294587 RX DATLAT : PASS
2057 10:02:09.297902 RX DQ/DQS(Engine): PASS
2058 10:02:09.301191 TX OE : NO K
2059 10:02:09.301279 All Pass.
2060 10:02:09.301381
2061 10:02:09.301483 CH 1, Rank 0
2062 10:02:09.304315 SW Impedance : PASS
2063 10:02:09.308211 DUTY Scan : NO K
2064 10:02:09.308300 ZQ Calibration : PASS
2065 10:02:09.311293 Jitter Meter : NO K
2066 10:02:09.311380 CBT Training : PASS
2067 10:02:09.314457 Write leveling : PASS
2068 10:02:09.318039 RX DQS gating : PASS
2069 10:02:09.318131 RX DQ/DQS(RDDQC) : PASS
2070 10:02:09.321319 TX DQ/DQS : PASS
2071 10:02:09.325067 RX DATLAT : PASS
2072 10:02:09.325155 RX DQ/DQS(Engine): PASS
2073 10:02:09.328103 TX OE : NO K
2074 10:02:09.328188 All Pass.
2075 10:02:09.328255
2076 10:02:09.331260 CH 1, Rank 1
2077 10:02:09.331393 SW Impedance : PASS
2078 10:02:09.334618 DUTY Scan : NO K
2079 10:02:09.337763 ZQ Calibration : PASS
2080 10:02:09.337856 Jitter Meter : NO K
2081 10:02:09.341330 CBT Training : PASS
2082 10:02:09.341422 Write leveling : PASS
2083 10:02:09.344770 RX DQS gating : PASS
2084 10:02:09.347971 RX DQ/DQS(RDDQC) : PASS
2085 10:02:09.348060 TX DQ/DQS : PASS
2086 10:02:09.351234 RX DATLAT : PASS
2087 10:02:09.354562 RX DQ/DQS(Engine): PASS
2088 10:02:09.354653 TX OE : NO K
2089 10:02:09.357852 All Pass.
2090 10:02:09.357937
2091 10:02:09.358027 DramC Write-DBI off
2092 10:02:09.361553 PER_BANK_REFRESH: Hybrid Mode
2093 10:02:09.361666 TX_TRACKING: ON
2094 10:02:09.364802 [GetDramInforAfterCalByMRR] Vendor 6.
2095 10:02:09.372066 [GetDramInforAfterCalByMRR] Revision 606.
2096 10:02:09.375107 [GetDramInforAfterCalByMRR] Revision 2 0.
2097 10:02:09.375196 MR0 0x3b3b
2098 10:02:09.375284 MR8 0x5151
2099 10:02:09.378530 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2100 10:02:09.378620
2101 10:02:09.381709 MR0 0x3b3b
2102 10:02:09.381797 MR8 0x5151
2103 10:02:09.384849 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2104 10:02:09.384931
2105 10:02:09.395038 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2106 10:02:09.398281 [FAST_K] Save calibration result to emmc
2107 10:02:09.402036 [FAST_K] Save calibration result to emmc
2108 10:02:09.405353 dram_init: config_dvfs: 1
2109 10:02:09.408537 dramc_set_vcore_voltage set vcore to 662500
2110 10:02:09.411838 Read voltage for 1200, 2
2111 10:02:09.411926 Vio18 = 0
2112 10:02:09.412011 Vcore = 662500
2113 10:02:09.414988 Vdram = 0
2114 10:02:09.415074 Vddq = 0
2115 10:02:09.415157 Vmddr = 0
2116 10:02:09.422208 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2117 10:02:09.425306 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2118 10:02:09.428381 MEM_TYPE=3, freq_sel=15
2119 10:02:09.431827 sv_algorithm_assistance_LP4_1600
2120 10:02:09.435392 ============ PULL DRAM RESETB DOWN ============
2121 10:02:09.438543 ========== PULL DRAM RESETB DOWN end =========
2122 10:02:09.445215 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2123 10:02:09.448282 ===================================
2124 10:02:09.448428 LPDDR4 DRAM CONFIGURATION
2125 10:02:09.451719 ===================================
2126 10:02:09.455154 EX_ROW_EN[0] = 0x0
2127 10:02:09.455249 EX_ROW_EN[1] = 0x0
2128 10:02:09.458628 LP4Y_EN = 0x0
2129 10:02:09.458714 WORK_FSP = 0x0
2130 10:02:09.461731 WL = 0x4
2131 10:02:09.465408 RL = 0x4
2132 10:02:09.465499 BL = 0x2
2133 10:02:09.468662 RPST = 0x0
2134 10:02:09.468751 RD_PRE = 0x0
2135 10:02:09.472034 WR_PRE = 0x1
2136 10:02:09.472150 WR_PST = 0x0
2137 10:02:09.475351 DBI_WR = 0x0
2138 10:02:09.475468 DBI_RD = 0x0
2139 10:02:09.478616 OTF = 0x1
2140 10:02:09.481787 ===================================
2141 10:02:09.485487 ===================================
2142 10:02:09.485626 ANA top config
2143 10:02:09.488745 ===================================
2144 10:02:09.491882 DLL_ASYNC_EN = 0
2145 10:02:09.495105 ALL_SLAVE_EN = 0
2146 10:02:09.495210 NEW_RANK_MODE = 1
2147 10:02:09.498966 DLL_IDLE_MODE = 1
2148 10:02:09.502200 LP45_APHY_COMB_EN = 1
2149 10:02:09.505391 TX_ODT_DIS = 1
2150 10:02:09.505523 NEW_8X_MODE = 1
2151 10:02:09.508902 ===================================
2152 10:02:09.512243 ===================================
2153 10:02:09.515388 data_rate = 2400
2154 10:02:09.518880 CKR = 1
2155 10:02:09.522206 DQ_P2S_RATIO = 8
2156 10:02:09.525273 ===================================
2157 10:02:09.529033 CA_P2S_RATIO = 8
2158 10:02:09.532181 DQ_CA_OPEN = 0
2159 10:02:09.532286 DQ_SEMI_OPEN = 0
2160 10:02:09.535677 CA_SEMI_OPEN = 0
2161 10:02:09.538734 CA_FULL_RATE = 0
2162 10:02:09.542085 DQ_CKDIV4_EN = 0
2163 10:02:09.545822 CA_CKDIV4_EN = 0
2164 10:02:09.548493 CA_PREDIV_EN = 0
2165 10:02:09.548598 PH8_DLY = 17
2166 10:02:09.551747 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2167 10:02:09.555710 DQ_AAMCK_DIV = 4
2168 10:02:09.558884 CA_AAMCK_DIV = 4
2169 10:02:09.562071 CA_ADMCK_DIV = 4
2170 10:02:09.565146 DQ_TRACK_CA_EN = 0
2171 10:02:09.565280 CA_PICK = 1200
2172 10:02:09.568888 CA_MCKIO = 1200
2173 10:02:09.572229 MCKIO_SEMI = 0
2174 10:02:09.575116 PLL_FREQ = 2366
2175 10:02:09.578662 DQ_UI_PI_RATIO = 32
2176 10:02:09.582000 CA_UI_PI_RATIO = 0
2177 10:02:09.585405 ===================================
2178 10:02:09.588770 ===================================
2179 10:02:09.588891 memory_type:LPDDR4
2180 10:02:09.592041 GP_NUM : 10
2181 10:02:09.595241 SRAM_EN : 1
2182 10:02:09.595364 MD32_EN : 0
2183 10:02:09.598450 ===================================
2184 10:02:09.602427 [ANA_INIT] >>>>>>>>>>>>>>
2185 10:02:09.605659 <<<<<< [CONFIGURE PHASE]: ANA_TX
2186 10:02:09.608782 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2187 10:02:09.612557 ===================================
2188 10:02:09.615486 data_rate = 2400,PCW = 0X5b00
2189 10:02:09.618651 ===================================
2190 10:02:09.621988 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2191 10:02:09.625132 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2192 10:02:09.632133 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2193 10:02:09.635146 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2194 10:02:09.638545 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2195 10:02:09.641847 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2196 10:02:09.645424 [ANA_INIT] flow start
2197 10:02:09.648505 [ANA_INIT] PLL >>>>>>>>
2198 10:02:09.648594 [ANA_INIT] PLL <<<<<<<<
2199 10:02:09.652448 [ANA_INIT] MIDPI >>>>>>>>
2200 10:02:09.655601 [ANA_INIT] MIDPI <<<<<<<<
2201 10:02:09.658847 [ANA_INIT] DLL >>>>>>>>
2202 10:02:09.658935 [ANA_INIT] DLL <<<<<<<<
2203 10:02:09.662086 [ANA_INIT] flow end
2204 10:02:09.665250 ============ LP4 DIFF to SE enter ============
2205 10:02:09.668399 ============ LP4 DIFF to SE exit ============
2206 10:02:09.671635 [ANA_INIT] <<<<<<<<<<<<<
2207 10:02:09.675590 [Flow] Enable top DCM control >>>>>
2208 10:02:09.678647 [Flow] Enable top DCM control <<<<<
2209 10:02:09.681725 Enable DLL master slave shuffle
2210 10:02:09.685113 ==============================================================
2211 10:02:09.688681 Gating Mode config
2212 10:02:09.695395 ==============================================================
2213 10:02:09.695538 Config description:
2214 10:02:09.705622 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2215 10:02:09.712145 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2216 10:02:09.715335 SELPH_MODE 0: By rank 1: By Phase
2217 10:02:09.722140 ==============================================================
2218 10:02:09.725403 GAT_TRACK_EN = 1
2219 10:02:09.728532 RX_GATING_MODE = 2
2220 10:02:09.732436 RX_GATING_TRACK_MODE = 2
2221 10:02:09.735472 SELPH_MODE = 1
2222 10:02:09.739267 PICG_EARLY_EN = 1
2223 10:02:09.742232 VALID_LAT_VALUE = 1
2224 10:02:09.745403 ==============================================================
2225 10:02:09.748727 Enter into Gating configuration >>>>
2226 10:02:09.752621 Exit from Gating configuration <<<<
2227 10:02:09.755773 Enter into DVFS_PRE_config >>>>>
2228 10:02:09.765882 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2229 10:02:09.769178 Exit from DVFS_PRE_config <<<<<
2230 10:02:09.772335 Enter into PICG configuration >>>>
2231 10:02:09.775619 Exit from PICG configuration <<<<
2232 10:02:09.778814 [RX_INPUT] configuration >>>>>
2233 10:02:09.782062 [RX_INPUT] configuration <<<<<
2234 10:02:09.789193 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2235 10:02:09.792115 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2236 10:02:09.798701 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2237 10:02:09.805895 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2238 10:02:09.812562 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2239 10:02:09.818818 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2240 10:02:09.822026 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2241 10:02:09.825292 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2242 10:02:09.828907 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2243 10:02:09.832135 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2244 10:02:09.839133 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2245 10:02:09.842005 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2246 10:02:09.845985 ===================================
2247 10:02:09.849175 LPDDR4 DRAM CONFIGURATION
2248 10:02:09.852403 ===================================
2249 10:02:09.852522 EX_ROW_EN[0] = 0x0
2250 10:02:09.855776 EX_ROW_EN[1] = 0x0
2251 10:02:09.855888 LP4Y_EN = 0x0
2252 10:02:09.859264 WORK_FSP = 0x0
2253 10:02:09.859385 WL = 0x4
2254 10:02:09.862169 RL = 0x4
2255 10:02:09.862264 BL = 0x2
2256 10:02:09.865565 RPST = 0x0
2257 10:02:09.865667 RD_PRE = 0x0
2258 10:02:09.869153 WR_PRE = 0x1
2259 10:02:09.869257 WR_PST = 0x0
2260 10:02:09.872340 DBI_WR = 0x0
2261 10:02:09.875683 DBI_RD = 0x0
2262 10:02:09.875777 OTF = 0x1
2263 10:02:09.878736 ===================================
2264 10:02:09.882566 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2265 10:02:09.885893 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2266 10:02:09.892404 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2267 10:02:09.895983 ===================================
2268 10:02:09.896115 LPDDR4 DRAM CONFIGURATION
2269 10:02:09.899046 ===================================
2270 10:02:09.902906 EX_ROW_EN[0] = 0x10
2271 10:02:09.906132 EX_ROW_EN[1] = 0x0
2272 10:02:09.906233 LP4Y_EN = 0x0
2273 10:02:09.909363 WORK_FSP = 0x0
2274 10:02:09.909477 WL = 0x4
2275 10:02:09.912513 RL = 0x4
2276 10:02:09.912622 BL = 0x2
2277 10:02:09.915919 RPST = 0x0
2278 10:02:09.916032 RD_PRE = 0x0
2279 10:02:09.919201 WR_PRE = 0x1
2280 10:02:09.919313 WR_PST = 0x0
2281 10:02:09.922514 DBI_WR = 0x0
2282 10:02:09.922624 DBI_RD = 0x0
2283 10:02:09.925807 OTF = 0x1
2284 10:02:09.929330 ===================================
2285 10:02:09.935788 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2286 10:02:09.935916 ==
2287 10:02:09.939253 Dram Type= 6, Freq= 0, CH_0, rank 0
2288 10:02:09.942780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2289 10:02:09.942911 ==
2290 10:02:09.946395 [Duty_Offset_Calibration]
2291 10:02:09.946487 B0:2 B1:1 CA:1
2292 10:02:09.946555
2293 10:02:09.949416 [DutyScan_Calibration_Flow] k_type=0
2294 10:02:09.959115
2295 10:02:09.959233 ==CLK 0==
2296 10:02:09.962634 Final CLK duty delay cell = 0
2297 10:02:09.965862 [0] MAX Duty = 5187%(X100), DQS PI = 24
2298 10:02:09.969695 [0] MIN Duty = 4844%(X100), DQS PI = 48
2299 10:02:09.969798 [0] AVG Duty = 5015%(X100)
2300 10:02:09.972437
2301 10:02:09.976061 CH0 CLK Duty spec in!! Max-Min= 343%
2302 10:02:09.979325 [DutyScan_Calibration_Flow] ====Done====
2303 10:02:09.979433
2304 10:02:09.982575 [DutyScan_Calibration_Flow] k_type=1
2305 10:02:09.997873
2306 10:02:09.998016 ==DQS 0 ==
2307 10:02:10.001510 Final DQS duty delay cell = -4
2308 10:02:10.004742 [-4] MAX Duty = 5124%(X100), DQS PI = 24
2309 10:02:10.008502 [-4] MIN Duty = 4782%(X100), DQS PI = 0
2310 10:02:10.011653 [-4] AVG Duty = 4953%(X100)
2311 10:02:10.011768
2312 10:02:10.011866 ==DQS 1 ==
2313 10:02:10.014955 Final DQS duty delay cell = 0
2314 10:02:10.018275 [0] MAX Duty = 5156%(X100), DQS PI = 0
2315 10:02:10.021381 [0] MIN Duty = 5031%(X100), DQS PI = 32
2316 10:02:10.024668 [0] AVG Duty = 5093%(X100)
2317 10:02:10.024779
2318 10:02:10.027980 CH0 DQS 0 Duty spec in!! Max-Min= 342%
2319 10:02:10.028105
2320 10:02:10.031257 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2321 10:02:10.035220 [DutyScan_Calibration_Flow] ====Done====
2322 10:02:10.035351
2323 10:02:10.038496 [DutyScan_Calibration_Flow] k_type=3
2324 10:02:10.054956
2325 10:02:10.055091 ==DQM 0 ==
2326 10:02:10.058102 Final DQM duty delay cell = 0
2327 10:02:10.061856 [0] MAX Duty = 5156%(X100), DQS PI = 28
2328 10:02:10.064853 [0] MIN Duty = 4907%(X100), DQS PI = 58
2329 10:02:10.064954 [0] AVG Duty = 5031%(X100)
2330 10:02:10.067872
2331 10:02:10.067965 ==DQM 1 ==
2332 10:02:10.071383 Final DQM duty delay cell = 0
2333 10:02:10.074642 [0] MAX Duty = 5093%(X100), DQS PI = 0
2334 10:02:10.078391 [0] MIN Duty = 5031%(X100), DQS PI = 36
2335 10:02:10.078476 [0] AVG Duty = 5062%(X100)
2336 10:02:10.078543
2337 10:02:10.084909 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2338 10:02:10.084994
2339 10:02:10.087998 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2340 10:02:10.091391 [DutyScan_Calibration_Flow] ====Done====
2341 10:02:10.091505
2342 10:02:10.094846 [DutyScan_Calibration_Flow] k_type=2
2343 10:02:10.111039
2344 10:02:10.111141 ==DQ 0 ==
2345 10:02:10.114671 Final DQ duty delay cell = 0
2346 10:02:10.117868 [0] MAX Duty = 5031%(X100), DQS PI = 26
2347 10:02:10.121024 [0] MIN Duty = 4906%(X100), DQS PI = 0
2348 10:02:10.121109 [0] AVG Duty = 4968%(X100)
2349 10:02:10.121174
2350 10:02:10.124847 ==DQ 1 ==
2351 10:02:10.128102 Final DQ duty delay cell = 0
2352 10:02:10.131338 [0] MAX Duty = 5093%(X100), DQS PI = 24
2353 10:02:10.134690 [0] MIN Duty = 4938%(X100), DQS PI = 36
2354 10:02:10.134807 [0] AVG Duty = 5015%(X100)
2355 10:02:10.134903
2356 10:02:10.138033 CH0 DQ 0 Duty spec in!! Max-Min= 125%
2357 10:02:10.138186
2358 10:02:10.141348 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2359 10:02:10.147835 [DutyScan_Calibration_Flow] ====Done====
2360 10:02:10.147975 ==
2361 10:02:10.151507 Dram Type= 6, Freq= 0, CH_1, rank 0
2362 10:02:10.154942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2363 10:02:10.155025 ==
2364 10:02:10.157936 [Duty_Offset_Calibration]
2365 10:02:10.158045 B0:1 B1:0 CA:0
2366 10:02:10.158144
2367 10:02:10.161630 [DutyScan_Calibration_Flow] k_type=0
2368 10:02:10.170741
2369 10:02:10.170828 ==CLK 0==
2370 10:02:10.173950 Final CLK duty delay cell = -4
2371 10:02:10.177160 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2372 10:02:10.180326 [-4] MIN Duty = 4875%(X100), DQS PI = 52
2373 10:02:10.183394 [-4] AVG Duty = 4953%(X100)
2374 10:02:10.183534
2375 10:02:10.186607 CH1 CLK Duty spec in!! Max-Min= 156%
2376 10:02:10.190256 [DutyScan_Calibration_Flow] ====Done====
2377 10:02:10.190371
2378 10:02:10.193697 [DutyScan_Calibration_Flow] k_type=1
2379 10:02:10.210143
2380 10:02:10.210244 ==DQS 0 ==
2381 10:02:10.213132 Final DQS duty delay cell = 0
2382 10:02:10.216579 [0] MAX Duty = 5094%(X100), DQS PI = 26
2383 10:02:10.220557 [0] MIN Duty = 4844%(X100), DQS PI = 0
2384 10:02:10.220644 [0] AVG Duty = 4969%(X100)
2385 10:02:10.220710
2386 10:02:10.223364 ==DQS 1 ==
2387 10:02:10.226947 Final DQS duty delay cell = 0
2388 10:02:10.230037 [0] MAX Duty = 5187%(X100), DQS PI = 18
2389 10:02:10.233818 [0] MIN Duty = 4969%(X100), DQS PI = 10
2390 10:02:10.233901 [0] AVG Duty = 5078%(X100)
2391 10:02:10.233965
2392 10:02:10.240347 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2393 10:02:10.240430
2394 10:02:10.243482 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2395 10:02:10.246761 [DutyScan_Calibration_Flow] ====Done====
2396 10:02:10.246844
2397 10:02:10.249915 [DutyScan_Calibration_Flow] k_type=3
2398 10:02:10.266627
2399 10:02:10.266715 ==DQM 0 ==
2400 10:02:10.269805 Final DQM duty delay cell = 0
2401 10:02:10.272983 [0] MAX Duty = 5156%(X100), DQS PI = 6
2402 10:02:10.276307 [0] MIN Duty = 5000%(X100), DQS PI = 62
2403 10:02:10.276388 [0] AVG Duty = 5078%(X100)
2404 10:02:10.280007
2405 10:02:10.280088 ==DQM 1 ==
2406 10:02:10.283305 Final DQM duty delay cell = 0
2407 10:02:10.287001 [0] MAX Duty = 5031%(X100), DQS PI = 16
2408 10:02:10.290227 [0] MIN Duty = 4907%(X100), DQS PI = 36
2409 10:02:10.290312 [0] AVG Duty = 4969%(X100)
2410 10:02:10.293426
2411 10:02:10.296556 CH1 DQM 0 Duty spec in!! Max-Min= 156%
2412 10:02:10.296672
2413 10:02:10.300271 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2414 10:02:10.303135 [DutyScan_Calibration_Flow] ====Done====
2415 10:02:10.303219
2416 10:02:10.306794 [DutyScan_Calibration_Flow] k_type=2
2417 10:02:10.322270
2418 10:02:10.322362 ==DQ 0 ==
2419 10:02:10.325454 Final DQ duty delay cell = -4
2420 10:02:10.328924 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2421 10:02:10.332191 [-4] MIN Duty = 4938%(X100), DQS PI = 0
2422 10:02:10.335523 [-4] AVG Duty = 5000%(X100)
2423 10:02:10.335609
2424 10:02:10.335678 ==DQ 1 ==
2425 10:02:10.339279 Final DQ duty delay cell = 0
2426 10:02:10.342285 [0] MAX Duty = 5125%(X100), DQS PI = 20
2427 10:02:10.345469 [0] MIN Duty = 4938%(X100), DQS PI = 34
2428 10:02:10.345551 [0] AVG Duty = 5031%(X100)
2429 10:02:10.349189
2430 10:02:10.352340 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2431 10:02:10.352421
2432 10:02:10.355429 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2433 10:02:10.359325 [DutyScan_Calibration_Flow] ====Done====
2434 10:02:10.362599 nWR fixed to 30
2435 10:02:10.362685 [ModeRegInit_LP4] CH0 RK0
2436 10:02:10.365744 [ModeRegInit_LP4] CH0 RK1
2437 10:02:10.368823 [ModeRegInit_LP4] CH1 RK0
2438 10:02:10.372278 [ModeRegInit_LP4] CH1 RK1
2439 10:02:10.372360 match AC timing 7
2440 10:02:10.375681 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2441 10:02:10.382201 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2442 10:02:10.385528 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2443 10:02:10.389357 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2444 10:02:10.396147 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2445 10:02:10.396235 ==
2446 10:02:10.399356 Dram Type= 6, Freq= 0, CH_0, rank 0
2447 10:02:10.402572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2448 10:02:10.402661 ==
2449 10:02:10.409479 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2450 10:02:10.412263 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2451 10:02:10.422596 [CA 0] Center 39 (8~70) winsize 63
2452 10:02:10.425823 [CA 1] Center 39 (8~70) winsize 63
2453 10:02:10.428979 [CA 2] Center 35 (5~66) winsize 62
2454 10:02:10.432707 [CA 3] Center 34 (4~65) winsize 62
2455 10:02:10.436007 [CA 4] Center 33 (3~64) winsize 62
2456 10:02:10.439206 [CA 5] Center 32 (3~62) winsize 60
2457 10:02:10.439288
2458 10:02:10.442709 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2459 10:02:10.442791
2460 10:02:10.445928 [CATrainingPosCal] consider 1 rank data
2461 10:02:10.449215 u2DelayCellTimex100 = 270/100 ps
2462 10:02:10.452658 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2463 10:02:10.455732 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2464 10:02:10.462706 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2465 10:02:10.466457 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2466 10:02:10.469532 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2467 10:02:10.472778 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2468 10:02:10.472889
2469 10:02:10.476094 CA PerBit enable=1, Macro0, CA PI delay=32
2470 10:02:10.476194
2471 10:02:10.479704 [CBTSetCACLKResult] CA Dly = 32
2472 10:02:10.479814 CS Dly: 6 (0~37)
2473 10:02:10.479911 ==
2474 10:02:10.482986 Dram Type= 6, Freq= 0, CH_0, rank 1
2475 10:02:10.489511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2476 10:02:10.489651 ==
2477 10:02:10.492651 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2478 10:02:10.499319 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2479 10:02:10.508333 [CA 0] Center 38 (8~69) winsize 62
2480 10:02:10.511436 [CA 1] Center 38 (8~69) winsize 62
2481 10:02:10.515074 [CA 2] Center 35 (5~66) winsize 62
2482 10:02:10.518070 [CA 3] Center 34 (4~65) winsize 62
2483 10:02:10.521835 [CA 4] Center 33 (3~64) winsize 62
2484 10:02:10.525060 [CA 5] Center 32 (2~62) winsize 61
2485 10:02:10.525142
2486 10:02:10.528921 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2487 10:02:10.529004
2488 10:02:10.531825 [CATrainingPosCal] consider 2 rank data
2489 10:02:10.535419 u2DelayCellTimex100 = 270/100 ps
2490 10:02:10.538533 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2491 10:02:10.541794 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2492 10:02:10.548200 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2493 10:02:10.551824 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2494 10:02:10.555365 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2495 10:02:10.558247 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2496 10:02:10.558332
2497 10:02:10.561544 CA PerBit enable=1, Macro0, CA PI delay=32
2498 10:02:10.561719
2499 10:02:10.565291 [CBTSetCACLKResult] CA Dly = 32
2500 10:02:10.565384 CS Dly: 6 (0~38)
2501 10:02:10.565468
2502 10:02:10.568803 ----->DramcWriteLeveling(PI) begin...
2503 10:02:10.571656 ==
2504 10:02:10.571740 Dram Type= 6, Freq= 0, CH_0, rank 0
2505 10:02:10.578718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2506 10:02:10.578804 ==
2507 10:02:10.581913 Write leveling (Byte 0): 32 => 32
2508 10:02:10.585198 Write leveling (Byte 1): 30 => 30
2509 10:02:10.585281 DramcWriteLeveling(PI) end<-----
2510 10:02:10.588339
2511 10:02:10.588421 ==
2512 10:02:10.592109 Dram Type= 6, Freq= 0, CH_0, rank 0
2513 10:02:10.595369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2514 10:02:10.595452 ==
2515 10:02:10.598252 [Gating] SW mode calibration
2516 10:02:10.605046 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2517 10:02:10.608636 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2518 10:02:10.615225 0 15 0 | B1->B0 | 2323 3434 | 1 1 | (0 0) (1 1)
2519 10:02:10.618818 0 15 4 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
2520 10:02:10.621928 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2521 10:02:10.628741 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2522 10:02:10.632063 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2523 10:02:10.635110 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2524 10:02:10.641976 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2525 10:02:10.645238 0 15 28 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
2526 10:02:10.648349 1 0 0 | B1->B0 | 2626 2323 | 1 0 | (1 0) (0 0)
2527 10:02:10.654966 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2528 10:02:10.658230 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2529 10:02:10.661907 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2530 10:02:10.668628 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2531 10:02:10.671836 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2532 10:02:10.674980 1 0 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
2533 10:02:10.678276 1 0 28 | B1->B0 | 2f2f 4646 | 0 0 | (0 0) (0 0)
2534 10:02:10.685298 1 1 0 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
2535 10:02:10.688719 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2536 10:02:10.692026 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2537 10:02:10.698695 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2538 10:02:10.701840 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2539 10:02:10.705735 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2540 10:02:10.711725 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2541 10:02:10.715031 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2542 10:02:10.718992 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2543 10:02:10.725749 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2544 10:02:10.728767 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 10:02:10.731691 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 10:02:10.738572 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 10:02:10.741832 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 10:02:10.745775 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 10:02:10.752117 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 10:02:10.755841 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 10:02:10.758941 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 10:02:10.762235 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 10:02:10.769200 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 10:02:10.772475 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 10:02:10.775503 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 10:02:10.782419 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 10:02:10.785685 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2558 10:02:10.789034 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2559 10:02:10.792474 Total UI for P1: 0, mck2ui 16
2560 10:02:10.795492 best dqsien dly found for B0: ( 1, 3, 28)
2561 10:02:10.802730 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2562 10:02:10.802840 Total UI for P1: 0, mck2ui 16
2563 10:02:10.806010 best dqsien dly found for B1: ( 1, 4, 0)
2564 10:02:10.812255 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2565 10:02:10.815519 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2566 10:02:10.815629
2567 10:02:10.819052 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2568 10:02:10.822694 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2569 10:02:10.825933 [Gating] SW calibration Done
2570 10:02:10.826022 ==
2571 10:02:10.829177 Dram Type= 6, Freq= 0, CH_0, rank 0
2572 10:02:10.832471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2573 10:02:10.832583 ==
2574 10:02:10.832680 RX Vref Scan: 0
2575 10:02:10.835499
2576 10:02:10.835599 RX Vref 0 -> 0, step: 1
2577 10:02:10.835665
2578 10:02:10.839218 RX Delay -40 -> 252, step: 8
2579 10:02:10.842215 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2580 10:02:10.846091 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2581 10:02:10.852383 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2582 10:02:10.855938 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2583 10:02:10.859113 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2584 10:02:10.862363 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2585 10:02:10.865740 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2586 10:02:10.872638 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2587 10:02:10.875887 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2588 10:02:10.879578 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2589 10:02:10.882858 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
2590 10:02:10.886095 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2591 10:02:10.889378 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2592 10:02:10.896276 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2593 10:02:10.899079 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2594 10:02:10.902854 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2595 10:02:10.902935 ==
2596 10:02:10.905748 Dram Type= 6, Freq= 0, CH_0, rank 0
2597 10:02:10.909428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2598 10:02:10.912473 ==
2599 10:02:10.912575 DQS Delay:
2600 10:02:10.912664 DQS0 = 0, DQS1 = 0
2601 10:02:10.916196 DQM Delay:
2602 10:02:10.916303 DQM0 = 121, DQM1 = 114
2603 10:02:10.919211 DQ Delay:
2604 10:02:10.922478 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2605 10:02:10.926474 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2606 10:02:10.929820 DQ8 =99, DQ9 =107, DQ10 =115, DQ11 =107
2607 10:02:10.932697 DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =119
2608 10:02:10.932798
2609 10:02:10.932900
2610 10:02:10.932988 ==
2611 10:02:10.936002 Dram Type= 6, Freq= 0, CH_0, rank 0
2612 10:02:10.939265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2613 10:02:10.939367 ==
2614 10:02:10.939460
2615 10:02:10.939546
2616 10:02:10.942880 TX Vref Scan disable
2617 10:02:10.946013 == TX Byte 0 ==
2618 10:02:10.949740 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2619 10:02:10.952831 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2620 10:02:10.955909 == TX Byte 1 ==
2621 10:02:10.959037 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2622 10:02:10.962401 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2623 10:02:10.962500 ==
2624 10:02:10.965801 Dram Type= 6, Freq= 0, CH_0, rank 0
2625 10:02:10.969545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2626 10:02:10.972184 ==
2627 10:02:10.983177 TX Vref=22, minBit 14, minWin=24, winSum=406
2628 10:02:10.986266 TX Vref=24, minBit 12, minWin=24, winSum=406
2629 10:02:10.989398 TX Vref=26, minBit 1, minWin=25, winSum=416
2630 10:02:10.992635 TX Vref=28, minBit 10, minWin=25, winSum=419
2631 10:02:10.996464 TX Vref=30, minBit 0, minWin=26, winSum=426
2632 10:02:11.002743 TX Vref=32, minBit 13, minWin=25, winSum=420
2633 10:02:11.006015 [TxChooseVref] Worse bit 0, Min win 26, Win sum 426, Final Vref 30
2634 10:02:11.006096
2635 10:02:11.009744 Final TX Range 1 Vref 30
2636 10:02:11.009821
2637 10:02:11.009903 ==
2638 10:02:11.012776 Dram Type= 6, Freq= 0, CH_0, rank 0
2639 10:02:11.016277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2640 10:02:11.016356 ==
2641 10:02:11.019093
2642 10:02:11.019192
2643 10:02:11.019286 TX Vref Scan disable
2644 10:02:11.022804 == TX Byte 0 ==
2645 10:02:11.026066 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2646 10:02:11.029345 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2647 10:02:11.033166 == TX Byte 1 ==
2648 10:02:11.036349 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2649 10:02:11.039697 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2650 10:02:11.042705
2651 10:02:11.042811 [DATLAT]
2652 10:02:11.042913 Freq=1200, CH0 RK0
2653 10:02:11.043003
2654 10:02:11.046532 DATLAT Default: 0xd
2655 10:02:11.046609 0, 0xFFFF, sum = 0
2656 10:02:11.049693 1, 0xFFFF, sum = 0
2657 10:02:11.049801 2, 0xFFFF, sum = 0
2658 10:02:11.052792 3, 0xFFFF, sum = 0
2659 10:02:11.056262 4, 0xFFFF, sum = 0
2660 10:02:11.056366 5, 0xFFFF, sum = 0
2661 10:02:11.059849 6, 0xFFFF, sum = 0
2662 10:02:11.059965 7, 0xFFFF, sum = 0
2663 10:02:11.062745 8, 0xFFFF, sum = 0
2664 10:02:11.062854 9, 0xFFFF, sum = 0
2665 10:02:11.066380 10, 0xFFFF, sum = 0
2666 10:02:11.066458 11, 0xFFFF, sum = 0
2667 10:02:11.070007 12, 0x0, sum = 1
2668 10:02:11.070083 13, 0x0, sum = 2
2669 10:02:11.072856 14, 0x0, sum = 3
2670 10:02:11.072932 15, 0x0, sum = 4
2671 10:02:11.072995 best_step = 13
2672 10:02:11.073097
2673 10:02:11.075998 ==
2674 10:02:11.079780 Dram Type= 6, Freq= 0, CH_0, rank 0
2675 10:02:11.082907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2676 10:02:11.082994 ==
2677 10:02:11.083062 RX Vref Scan: 1
2678 10:02:11.083123
2679 10:02:11.086377 Set Vref Range= 32 -> 127
2680 10:02:11.086453
2681 10:02:11.090105 RX Vref 32 -> 127, step: 1
2682 10:02:11.090203
2683 10:02:11.092991 RX Delay -13 -> 252, step: 4
2684 10:02:11.093088
2685 10:02:11.096107 Set Vref, RX VrefLevel [Byte0]: 32
2686 10:02:11.099930 [Byte1]: 32
2687 10:02:11.100004
2688 10:02:11.102986 Set Vref, RX VrefLevel [Byte0]: 33
2689 10:02:11.106127 [Byte1]: 33
2690 10:02:11.106199
2691 10:02:11.109822 Set Vref, RX VrefLevel [Byte0]: 34
2692 10:02:11.112919 [Byte1]: 34
2693 10:02:11.117329
2694 10:02:11.117408 Set Vref, RX VrefLevel [Byte0]: 35
2695 10:02:11.120629 [Byte1]: 35
2696 10:02:11.124965
2697 10:02:11.125038 Set Vref, RX VrefLevel [Byte0]: 36
2698 10:02:11.128122 [Byte1]: 36
2699 10:02:11.133059
2700 10:02:11.133157 Set Vref, RX VrefLevel [Byte0]: 37
2701 10:02:11.135923 [Byte1]: 37
2702 10:02:11.140662
2703 10:02:11.140763 Set Vref, RX VrefLevel [Byte0]: 38
2704 10:02:11.143937 [Byte1]: 38
2705 10:02:11.148737
2706 10:02:11.148845 Set Vref, RX VrefLevel [Byte0]: 39
2707 10:02:11.154742 [Byte1]: 39
2708 10:02:11.154862
2709 10:02:11.158567 Set Vref, RX VrefLevel [Byte0]: 40
2710 10:02:11.161750 [Byte1]: 40
2711 10:02:11.161830
2712 10:02:11.164889 Set Vref, RX VrefLevel [Byte0]: 41
2713 10:02:11.168781 [Byte1]: 41
2714 10:02:11.172281
2715 10:02:11.172394 Set Vref, RX VrefLevel [Byte0]: 42
2716 10:02:11.175805 [Byte1]: 42
2717 10:02:11.180450
2718 10:02:11.180557 Set Vref, RX VrefLevel [Byte0]: 43
2719 10:02:11.183701 [Byte1]: 43
2720 10:02:11.188420
2721 10:02:11.188520 Set Vref, RX VrefLevel [Byte0]: 44
2722 10:02:11.191590 [Byte1]: 44
2723 10:02:11.195871
2724 10:02:11.195981 Set Vref, RX VrefLevel [Byte0]: 45
2725 10:02:11.199432 [Byte1]: 45
2726 10:02:11.203959
2727 10:02:11.204036 Set Vref, RX VrefLevel [Byte0]: 46
2728 10:02:11.206945 [Byte1]: 46
2729 10:02:11.212066
2730 10:02:11.212166 Set Vref, RX VrefLevel [Byte0]: 47
2731 10:02:11.215319 [Byte1]: 47
2732 10:02:11.219846
2733 10:02:11.219958 Set Vref, RX VrefLevel [Byte0]: 48
2734 10:02:11.222991 [Byte1]: 48
2735 10:02:11.227612
2736 10:02:11.227686 Set Vref, RX VrefLevel [Byte0]: 49
2737 10:02:11.230704 [Byte1]: 49
2738 10:02:11.235260
2739 10:02:11.235367 Set Vref, RX VrefLevel [Byte0]: 50
2740 10:02:11.239071 [Byte1]: 50
2741 10:02:11.243168
2742 10:02:11.243271 Set Vref, RX VrefLevel [Byte0]: 51
2743 10:02:11.247113 [Byte1]: 51
2744 10:02:11.251065
2745 10:02:11.251167 Set Vref, RX VrefLevel [Byte0]: 52
2746 10:02:11.254679 [Byte1]: 52
2747 10:02:11.259234
2748 10:02:11.259339 Set Vref, RX VrefLevel [Byte0]: 53
2749 10:02:11.262647 [Byte1]: 53
2750 10:02:11.267160
2751 10:02:11.267263 Set Vref, RX VrefLevel [Byte0]: 54
2752 10:02:11.270459 [Byte1]: 54
2753 10:02:11.274940
2754 10:02:11.275050 Set Vref, RX VrefLevel [Byte0]: 55
2755 10:02:11.277992 [Byte1]: 55
2756 10:02:11.282824
2757 10:02:11.282925 Set Vref, RX VrefLevel [Byte0]: 56
2758 10:02:11.285917 [Byte1]: 56
2759 10:02:11.290914
2760 10:02:11.291019 Set Vref, RX VrefLevel [Byte0]: 57
2761 10:02:11.294452 [Byte1]: 57
2762 10:02:11.298840
2763 10:02:11.298921 Set Vref, RX VrefLevel [Byte0]: 58
2764 10:02:11.301796 [Byte1]: 58
2765 10:02:11.306247
2766 10:02:11.306342 Set Vref, RX VrefLevel [Byte0]: 59
2767 10:02:11.309828 [Byte1]: 59
2768 10:02:11.314074
2769 10:02:11.314181 Set Vref, RX VrefLevel [Byte0]: 60
2770 10:02:11.317674 [Byte1]: 60
2771 10:02:11.322238
2772 10:02:11.322347 Set Vref, RX VrefLevel [Byte0]: 61
2773 10:02:11.325347 [Byte1]: 61
2774 10:02:11.330573
2775 10:02:11.330691 Set Vref, RX VrefLevel [Byte0]: 62
2776 10:02:11.333427 [Byte1]: 62
2777 10:02:11.337950
2778 10:02:11.338059 Set Vref, RX VrefLevel [Byte0]: 63
2779 10:02:11.341135 [Byte1]: 63
2780 10:02:11.346348
2781 10:02:11.346433 Set Vref, RX VrefLevel [Byte0]: 64
2782 10:02:11.348913 [Byte1]: 64
2783 10:02:11.353851
2784 10:02:11.353940 Set Vref, RX VrefLevel [Byte0]: 65
2785 10:02:11.357064 [Byte1]: 65
2786 10:02:11.361538
2787 10:02:11.361684 Set Vref, RX VrefLevel [Byte0]: 66
2788 10:02:11.365147 [Byte1]: 66
2789 10:02:11.369364
2790 10:02:11.369474 Set Vref, RX VrefLevel [Byte0]: 67
2791 10:02:11.372930 [Byte1]: 67
2792 10:02:11.377222
2793 10:02:11.377327 Set Vref, RX VrefLevel [Byte0]: 68
2794 10:02:11.380812 [Byte1]: 68
2795 10:02:11.385430
2796 10:02:11.385538 Set Vref, RX VrefLevel [Byte0]: 69
2797 10:02:11.389025 [Byte1]: 69
2798 10:02:11.393431
2799 10:02:11.393549 Final RX Vref Byte 0 = 56 to rank0
2800 10:02:11.396777 Final RX Vref Byte 1 = 47 to rank0
2801 10:02:11.399858 Final RX Vref Byte 0 = 56 to rank1
2802 10:02:11.403185 Final RX Vref Byte 1 = 47 to rank1==
2803 10:02:11.406383 Dram Type= 6, Freq= 0, CH_0, rank 0
2804 10:02:11.413310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2805 10:02:11.413417 ==
2806 10:02:11.413520 DQS Delay:
2807 10:02:11.413649 DQS0 = 0, DQS1 = 0
2808 10:02:11.416724 DQM Delay:
2809 10:02:11.416805 DQM0 = 120, DQM1 = 111
2810 10:02:11.420077 DQ Delay:
2811 10:02:11.423078 DQ0 =120, DQ1 =122, DQ2 =120, DQ3 =118
2812 10:02:11.426973 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2813 10:02:11.429764 DQ8 =98, DQ9 =100, DQ10 =112, DQ11 =106
2814 10:02:11.433051 DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =118
2815 10:02:11.433152
2816 10:02:11.433278
2817 10:02:11.440062 [DQSOSCAuto] RK0, (LSB)MR18= 0x1610, (MSB)MR19= 0x404, tDQSOscB0 = 403 ps tDQSOscB1 = 401 ps
2818 10:02:11.443256 CH0 RK0: MR19=404, MR18=1610
2819 10:02:11.450160 CH0_RK0: MR19=0x404, MR18=0x1610, DQSOSC=401, MR23=63, INC=40, DEC=27
2820 10:02:11.450240
2821 10:02:11.453403 ----->DramcWriteLeveling(PI) begin...
2822 10:02:11.453478 ==
2823 10:02:11.456480 Dram Type= 6, Freq= 0, CH_0, rank 1
2824 10:02:11.460512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2825 10:02:11.463594 ==
2826 10:02:11.463668 Write leveling (Byte 0): 35 => 35
2827 10:02:11.466641 Write leveling (Byte 1): 28 => 28
2828 10:02:11.469889 DramcWriteLeveling(PI) end<-----
2829 10:02:11.470003
2830 10:02:11.470095 ==
2831 10:02:11.473737 Dram Type= 6, Freq= 0, CH_0, rank 1
2832 10:02:11.480114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2833 10:02:11.480200 ==
2834 10:02:11.480266 [Gating] SW mode calibration
2835 10:02:11.490114 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2836 10:02:11.493452 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2837 10:02:11.496581 0 15 0 | B1->B0 | 3131 2c2c | 0 1 | (0 0) (0 0)
2838 10:02:11.503220 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2839 10:02:11.507131 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2840 10:02:11.510440 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2841 10:02:11.516687 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2842 10:02:11.520449 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2843 10:02:11.523556 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2844 10:02:11.530588 0 15 28 | B1->B0 | 3030 2d2d | 0 0 | (1 0) (0 0)
2845 10:02:11.533426 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2846 10:02:11.536987 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2847 10:02:11.543402 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2848 10:02:11.546898 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2849 10:02:11.550019 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2850 10:02:11.556928 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2851 10:02:11.560590 1 0 24 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
2852 10:02:11.563736 1 0 28 | B1->B0 | 3838 3b3a | 1 1 | (0 0) (0 0)
2853 10:02:11.567066 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2854 10:02:11.573385 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2855 10:02:11.576727 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2856 10:02:11.580382 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2857 10:02:11.587074 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2858 10:02:11.590045 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2859 10:02:11.593909 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2860 10:02:11.599970 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2861 10:02:11.603513 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2862 10:02:11.606738 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2863 10:02:11.613448 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2864 10:02:11.616646 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2865 10:02:11.620502 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2866 10:02:11.627027 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 10:02:11.630137 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 10:02:11.633345 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 10:02:11.640189 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 10:02:11.643806 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 10:02:11.646799 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 10:02:11.653488 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 10:02:11.657028 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 10:02:11.660225 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 10:02:11.663715 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 10:02:11.670008 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2877 10:02:11.673933 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2878 10:02:11.677096 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2879 10:02:11.680339 Total UI for P1: 0, mck2ui 16
2880 10:02:11.684075 best dqsien dly found for B0: ( 1, 3, 30)
2881 10:02:11.687288 Total UI for P1: 0, mck2ui 16
2882 10:02:11.690387 best dqsien dly found for B1: ( 1, 3, 30)
2883 10:02:11.693733 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2884 10:02:11.697187 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2885 10:02:11.697297
2886 10:02:11.703607 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2887 10:02:11.707439 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2888 10:02:11.707541 [Gating] SW calibration Done
2889 10:02:11.710318 ==
2890 10:02:11.714134 Dram Type= 6, Freq= 0, CH_0, rank 1
2891 10:02:11.717029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2892 10:02:11.717124 ==
2893 10:02:11.717217 RX Vref Scan: 0
2894 10:02:11.717304
2895 10:02:11.720418 RX Vref 0 -> 0, step: 1
2896 10:02:11.720527
2897 10:02:11.724107 RX Delay -40 -> 252, step: 8
2898 10:02:11.727140 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2899 10:02:11.730470 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2900 10:02:11.734021 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2901 10:02:11.740419 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2902 10:02:11.743718 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2903 10:02:11.747527 iDelay=200, Bit 5, Center 119 (48 ~ 191) 144
2904 10:02:11.750598 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2905 10:02:11.753983 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2906 10:02:11.757472 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2907 10:02:11.764245 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2908 10:02:11.767121 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2909 10:02:11.770758 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2910 10:02:11.774032 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2911 10:02:11.780354 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2912 10:02:11.784330 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2913 10:02:11.787376 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2914 10:02:11.787461 ==
2915 10:02:11.790609 Dram Type= 6, Freq= 0, CH_0, rank 1
2916 10:02:11.793953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2917 10:02:11.794039 ==
2918 10:02:11.797161 DQS Delay:
2919 10:02:11.797268 DQS0 = 0, DQS1 = 0
2920 10:02:11.800331 DQM Delay:
2921 10:02:11.800438 DQM0 = 122, DQM1 = 112
2922 10:02:11.800530 DQ Delay:
2923 10:02:11.803897 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2924 10:02:11.807412 DQ4 =127, DQ5 =119, DQ6 =127, DQ7 =127
2925 10:02:11.813999 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =103
2926 10:02:11.817296 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =123
2927 10:02:11.817408
2928 10:02:11.817499
2929 10:02:11.817609 ==
2930 10:02:11.820628 Dram Type= 6, Freq= 0, CH_0, rank 1
2931 10:02:11.823701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2932 10:02:11.823790 ==
2933 10:02:11.823855
2934 10:02:11.823922
2935 10:02:11.827575 TX Vref Scan disable
2936 10:02:11.830535 == TX Byte 0 ==
2937 10:02:11.833843 Update DQ dly =855 (3 ,2, 23) DQ OEN =(2 ,7)
2938 10:02:11.837212 Update DQM dly =855 (3 ,2, 23) DQM OEN =(2 ,7)
2939 10:02:11.840547 == TX Byte 1 ==
2940 10:02:11.844154 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2941 10:02:11.847141 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2942 10:02:11.847224 ==
2943 10:02:11.850784 Dram Type= 6, Freq= 0, CH_0, rank 1
2944 10:02:11.854116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2945 10:02:11.854200 ==
2946 10:02:11.867266 TX Vref=22, minBit 1, minWin=25, winSum=414
2947 10:02:11.870860 TX Vref=24, minBit 10, minWin=25, winSum=417
2948 10:02:11.874328 TX Vref=26, minBit 0, minWin=26, winSum=422
2949 10:02:11.877450 TX Vref=28, minBit 5, minWin=25, winSum=425
2950 10:02:11.880867 TX Vref=30, minBit 5, minWin=25, winSum=422
2951 10:02:11.887788 TX Vref=32, minBit 5, minWin=25, winSum=422
2952 10:02:11.891251 [TxChooseVref] Worse bit 0, Min win 26, Win sum 422, Final Vref 26
2953 10:02:11.891336
2954 10:02:11.894350 Final TX Range 1 Vref 26
2955 10:02:11.894496
2956 10:02:11.894610 ==
2957 10:02:11.897893 Dram Type= 6, Freq= 0, CH_0, rank 1
2958 10:02:11.901080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2959 10:02:11.901270 ==
2960 10:02:11.901404
2961 10:02:11.904422
2962 10:02:11.904563 TX Vref Scan disable
2963 10:02:11.907703 == TX Byte 0 ==
2964 10:02:11.910891 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2965 10:02:11.914399 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2966 10:02:11.917935 == TX Byte 1 ==
2967 10:02:11.920870 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2968 10:02:11.924140 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2969 10:02:11.927345
2970 10:02:11.927450 [DATLAT]
2971 10:02:11.927544 Freq=1200, CH0 RK1
2972 10:02:11.927635
2973 10:02:11.931207 DATLAT Default: 0xd
2974 10:02:11.931305 0, 0xFFFF, sum = 0
2975 10:02:11.934430 1, 0xFFFF, sum = 0
2976 10:02:11.934559 2, 0xFFFF, sum = 0
2977 10:02:11.937546 3, 0xFFFF, sum = 0
2978 10:02:11.937730 4, 0xFFFF, sum = 0
2979 10:02:11.941026 5, 0xFFFF, sum = 0
2980 10:02:11.941163 6, 0xFFFF, sum = 0
2981 10:02:11.944556 7, 0xFFFF, sum = 0
2982 10:02:11.947804 8, 0xFFFF, sum = 0
2983 10:02:11.947950 9, 0xFFFF, sum = 0
2984 10:02:11.950907 10, 0xFFFF, sum = 0
2985 10:02:11.951067 11, 0xFFFF, sum = 0
2986 10:02:11.954608 12, 0x0, sum = 1
2987 10:02:11.954719 13, 0x0, sum = 2
2988 10:02:11.957379 14, 0x0, sum = 3
2989 10:02:11.957485 15, 0x0, sum = 4
2990 10:02:11.957587 best_step = 13
2991 10:02:11.957677
2992 10:02:11.961136 ==
2993 10:02:11.961235 Dram Type= 6, Freq= 0, CH_0, rank 1
2994 10:02:11.967895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2995 10:02:11.968005 ==
2996 10:02:11.968102 RX Vref Scan: 0
2997 10:02:11.968202
2998 10:02:11.971255 RX Vref 0 -> 0, step: 1
2999 10:02:11.971371
3000 10:02:11.974608 RX Delay -13 -> 252, step: 4
3001 10:02:11.978166 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
3002 10:02:11.981139 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3003 10:02:11.987763 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3004 10:02:11.991298 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3005 10:02:11.995019 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3006 10:02:11.998277 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3007 10:02:12.001404 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3008 10:02:12.007907 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3009 10:02:12.011601 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3010 10:02:12.014929 iDelay=195, Bit 9, Center 96 (31 ~ 162) 132
3011 10:02:12.017956 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3012 10:02:12.021238 iDelay=195, Bit 11, Center 100 (35 ~ 166) 132
3013 10:02:12.027881 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3014 10:02:12.031556 iDelay=195, Bit 13, Center 114 (51 ~ 178) 128
3015 10:02:12.034560 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3016 10:02:12.037923 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3017 10:02:12.038030 ==
3018 10:02:12.041725 Dram Type= 6, Freq= 0, CH_0, rank 1
3019 10:02:12.044936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3020 10:02:12.047926 ==
3021 10:02:12.048061 DQS Delay:
3022 10:02:12.048184 DQS0 = 0, DQS1 = 0
3023 10:02:12.051708 DQM Delay:
3024 10:02:12.051847 DQM0 = 121, DQM1 = 109
3025 10:02:12.055039 DQ Delay:
3026 10:02:12.057996 DQ0 =120, DQ1 =122, DQ2 =118, DQ3 =118
3027 10:02:12.061367 DQ4 =122, DQ5 =116, DQ6 =128, DQ7 =126
3028 10:02:12.065152 DQ8 =100, DQ9 =96, DQ10 =110, DQ11 =100
3029 10:02:12.068381 DQ12 =114, DQ13 =114, DQ14 =122, DQ15 =118
3030 10:02:12.068531
3031 10:02:12.068662
3032 10:02:12.075225 [DQSOSCAuto] RK1, (LSB)MR18= 0x11f2, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 403 ps
3033 10:02:12.078504 CH0 RK1: MR19=403, MR18=11F2
3034 10:02:12.084848 CH0_RK1: MR19=0x403, MR18=0x11F2, DQSOSC=403, MR23=63, INC=40, DEC=26
3035 10:02:12.088274 [RxdqsGatingPostProcess] freq 1200
3036 10:02:12.094969 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3037 10:02:12.095085 best DQS0 dly(2T, 0.5T) = (0, 11)
3038 10:02:12.098367 best DQS1 dly(2T, 0.5T) = (0, 12)
3039 10:02:12.101673 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3040 10:02:12.104964 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3041 10:02:12.108164 best DQS0 dly(2T, 0.5T) = (0, 11)
3042 10:02:12.111512 best DQS1 dly(2T, 0.5T) = (0, 11)
3043 10:02:12.115059 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3044 10:02:12.118458 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3045 10:02:12.121642 Pre-setting of DQS Precalculation
3046 10:02:12.124715 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3047 10:02:12.128625 ==
3048 10:02:12.128769 Dram Type= 6, Freq= 0, CH_1, rank 0
3049 10:02:12.134770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3050 10:02:12.134931 ==
3051 10:02:12.138616 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3052 10:02:12.144979 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3053 10:02:12.153921 [CA 0] Center 37 (7~68) winsize 62
3054 10:02:12.157765 [CA 1] Center 37 (7~68) winsize 62
3055 10:02:12.160964 [CA 2] Center 35 (5~65) winsize 61
3056 10:02:12.164193 [CA 3] Center 35 (5~65) winsize 61
3057 10:02:12.167273 [CA 4] Center 34 (4~64) winsize 61
3058 10:02:12.170647 [CA 5] Center 33 (3~63) winsize 61
3059 10:02:12.170794
3060 10:02:12.173968 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3061 10:02:12.174077
3062 10:02:12.177173 [CATrainingPosCal] consider 1 rank data
3063 10:02:12.181038 u2DelayCellTimex100 = 270/100 ps
3064 10:02:12.183962 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3065 10:02:12.187217 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3066 10:02:12.194331 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3067 10:02:12.197806 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
3068 10:02:12.200662 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3069 10:02:12.204140 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3070 10:02:12.204243
3071 10:02:12.207565 CA PerBit enable=1, Macro0, CA PI delay=33
3072 10:02:12.207648
3073 10:02:12.210917 [CBTSetCACLKResult] CA Dly = 33
3074 10:02:12.211001 CS Dly: 7 (0~38)
3075 10:02:12.211066 ==
3076 10:02:12.214259 Dram Type= 6, Freq= 0, CH_1, rank 1
3077 10:02:12.220852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3078 10:02:12.220940 ==
3079 10:02:12.224330 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3080 10:02:12.230839 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3081 10:02:12.239793 [CA 0] Center 37 (7~68) winsize 62
3082 10:02:12.243242 [CA 1] Center 37 (7~68) winsize 62
3083 10:02:12.246280 [CA 2] Center 35 (5~65) winsize 61
3084 10:02:12.249462 [CA 3] Center 34 (4~65) winsize 62
3085 10:02:12.253311 [CA 4] Center 34 (4~65) winsize 62
3086 10:02:12.256739 [CA 5] Center 33 (4~63) winsize 60
3087 10:02:12.256853
3088 10:02:12.259734 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3089 10:02:12.259854
3090 10:02:12.263320 [CATrainingPosCal] consider 2 rank data
3091 10:02:12.266392 u2DelayCellTimex100 = 270/100 ps
3092 10:02:12.270151 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3093 10:02:12.273476 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3094 10:02:12.276697 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3095 10:02:12.283083 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
3096 10:02:12.286394 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3097 10:02:12.289749 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3098 10:02:12.289836
3099 10:02:12.292987 CA PerBit enable=1, Macro0, CA PI delay=33
3100 10:02:12.293106
3101 10:02:12.296672 [CBTSetCACLKResult] CA Dly = 33
3102 10:02:12.296807 CS Dly: 8 (0~41)
3103 10:02:12.296877
3104 10:02:12.299986 ----->DramcWriteLeveling(PI) begin...
3105 10:02:12.300084 ==
3106 10:02:12.303244 Dram Type= 6, Freq= 0, CH_1, rank 0
3107 10:02:12.310001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3108 10:02:12.310089 ==
3109 10:02:12.313487 Write leveling (Byte 0): 24 => 24
3110 10:02:12.316587 Write leveling (Byte 1): 28 => 28
3111 10:02:12.316672 DramcWriteLeveling(PI) end<-----
3112 10:02:12.316739
3113 10:02:12.319895 ==
3114 10:02:12.323608 Dram Type= 6, Freq= 0, CH_1, rank 0
3115 10:02:12.326592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3116 10:02:12.326679 ==
3117 10:02:12.330348 [Gating] SW mode calibration
3118 10:02:12.337019 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3119 10:02:12.339820 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3120 10:02:12.346658 0 15 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
3121 10:02:12.350282 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3122 10:02:12.353205 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3123 10:02:12.359968 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3124 10:02:12.363212 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3125 10:02:12.366994 0 15 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3126 10:02:12.373101 0 15 24 | B1->B0 | 3232 2a2a | 0 0 | (0 0) (0 0)
3127 10:02:12.376579 0 15 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (1 0)
3128 10:02:12.379851 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3129 10:02:12.386861 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3130 10:02:12.390104 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3131 10:02:12.393140 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3132 10:02:12.396475 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3133 10:02:12.403546 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3134 10:02:12.406890 1 0 24 | B1->B0 | 2e2e 3c3c | 0 1 | (0 0) (0 0)
3135 10:02:12.410032 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3136 10:02:12.416485 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3137 10:02:12.420131 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3138 10:02:12.423566 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3139 10:02:12.430013 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3140 10:02:12.433684 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3141 10:02:12.436569 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3142 10:02:12.443287 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3143 10:02:12.447028 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3144 10:02:12.450064 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3145 10:02:12.456622 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3146 10:02:12.459927 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3147 10:02:12.463860 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 10:02:12.469976 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 10:02:12.473553 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 10:02:12.476997 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 10:02:12.480140 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 10:02:12.486886 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 10:02:12.489963 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 10:02:12.493565 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 10:02:12.500550 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 10:02:12.503803 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 10:02:12.507064 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 10:02:12.513437 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3159 10:02:12.516739 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3160 10:02:12.520365 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3161 10:02:12.523662 Total UI for P1: 0, mck2ui 16
3162 10:02:12.527021 best dqsien dly found for B0: ( 1, 3, 26)
3163 10:02:12.530516 Total UI for P1: 0, mck2ui 16
3164 10:02:12.533484 best dqsien dly found for B1: ( 1, 3, 26)
3165 10:02:12.539536 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3166 10:02:12.540353 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3167 10:02:12.540478
3168 10:02:12.546724 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3169 10:02:12.550086 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3170 10:02:12.550196 [Gating] SW calibration Done
3171 10:02:12.553376 ==
3172 10:02:12.553479 Dram Type= 6, Freq= 0, CH_1, rank 0
3173 10:02:12.559973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3174 10:02:12.560076 ==
3175 10:02:12.560179 RX Vref Scan: 0
3176 10:02:12.560267
3177 10:02:12.563554 RX Vref 0 -> 0, step: 1
3178 10:02:12.563656
3179 10:02:12.567122 RX Delay -40 -> 252, step: 8
3180 10:02:12.570368 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3181 10:02:12.573569 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3182 10:02:12.576715 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3183 10:02:12.583829 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3184 10:02:12.586733 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3185 10:02:12.590447 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3186 10:02:12.593953 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3187 10:02:12.597243 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3188 10:02:12.600341 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3189 10:02:12.607175 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3190 10:02:12.610742 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3191 10:02:12.613822 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3192 10:02:12.616950 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3193 10:02:12.624042 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3194 10:02:12.627232 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3195 10:02:12.630372 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3196 10:02:12.630483 ==
3197 10:02:12.633636 Dram Type= 6, Freq= 0, CH_1, rank 0
3198 10:02:12.637386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3199 10:02:12.637486 ==
3200 10:02:12.640511 DQS Delay:
3201 10:02:12.640616 DQS0 = 0, DQS1 = 0
3202 10:02:12.644100 DQM Delay:
3203 10:02:12.644201 DQM0 = 120, DQM1 = 116
3204 10:02:12.644301 DQ Delay:
3205 10:02:12.647092 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3206 10:02:12.650274 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =123
3207 10:02:12.657010 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3208 10:02:12.660376 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3209 10:02:12.660461
3210 10:02:12.660526
3211 10:02:12.660587 ==
3212 10:02:12.663630 Dram Type= 6, Freq= 0, CH_1, rank 0
3213 10:02:12.667267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3214 10:02:12.667381 ==
3215 10:02:12.667476
3216 10:02:12.667566
3217 10:02:12.670801 TX Vref Scan disable
3218 10:02:12.670911 == TX Byte 0 ==
3219 10:02:12.677179 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3220 10:02:12.680499 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3221 10:02:12.680617 == TX Byte 1 ==
3222 10:02:12.687550 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3223 10:02:12.690746 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3224 10:02:12.690851 ==
3225 10:02:12.693813 Dram Type= 6, Freq= 0, CH_1, rank 0
3226 10:02:12.697295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3227 10:02:12.697447 ==
3228 10:02:12.710198 TX Vref=22, minBit 9, minWin=24, winSum=410
3229 10:02:12.713279 TX Vref=24, minBit 7, minWin=25, winSum=415
3230 10:02:12.717113 TX Vref=26, minBit 10, minWin=25, winSum=424
3231 10:02:12.720063 TX Vref=28, minBit 1, minWin=26, winSum=426
3232 10:02:12.723530 TX Vref=30, minBit 9, minWin=26, winSum=428
3233 10:02:12.726932 TX Vref=32, minBit 9, minWin=26, winSum=430
3234 10:02:12.733472 [TxChooseVref] Worse bit 9, Min win 26, Win sum 430, Final Vref 32
3235 10:02:12.733621
3236 10:02:12.736724 Final TX Range 1 Vref 32
3237 10:02:12.736833
3238 10:02:12.736927 ==
3239 10:02:12.739961 Dram Type= 6, Freq= 0, CH_1, rank 0
3240 10:02:12.743340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3241 10:02:12.743441 ==
3242 10:02:12.743528
3243 10:02:12.747167
3244 10:02:12.747249 TX Vref Scan disable
3245 10:02:12.750288 == TX Byte 0 ==
3246 10:02:12.753703 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3247 10:02:12.757174 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3248 10:02:12.760163 == TX Byte 1 ==
3249 10:02:12.763415 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3250 10:02:12.766511 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3251 10:02:12.766621
3252 10:02:12.770261 [DATLAT]
3253 10:02:12.770370 Freq=1200, CH1 RK0
3254 10:02:12.770445
3255 10:02:12.773420 DATLAT Default: 0xd
3256 10:02:12.773514 0, 0xFFFF, sum = 0
3257 10:02:12.776833 1, 0xFFFF, sum = 0
3258 10:02:12.776953 2, 0xFFFF, sum = 0
3259 10:02:12.780047 3, 0xFFFF, sum = 0
3260 10:02:12.780153 4, 0xFFFF, sum = 0
3261 10:02:12.783634 5, 0xFFFF, sum = 0
3262 10:02:12.783748 6, 0xFFFF, sum = 0
3263 10:02:12.786463 7, 0xFFFF, sum = 0
3264 10:02:12.790276 8, 0xFFFF, sum = 0
3265 10:02:12.790370 9, 0xFFFF, sum = 0
3266 10:02:12.793524 10, 0xFFFF, sum = 0
3267 10:02:12.793636 11, 0xFFFF, sum = 0
3268 10:02:12.796764 12, 0x0, sum = 1
3269 10:02:12.796844 13, 0x0, sum = 2
3270 10:02:12.799909 14, 0x0, sum = 3
3271 10:02:12.800012 15, 0x0, sum = 4
3272 10:02:12.800109 best_step = 13
3273 10:02:12.800203
3274 10:02:12.803779 ==
3275 10:02:12.807001 Dram Type= 6, Freq= 0, CH_1, rank 0
3276 10:02:12.810134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3277 10:02:12.810220 ==
3278 10:02:12.810288 RX Vref Scan: 1
3279 10:02:12.810350
3280 10:02:12.813932 Set Vref Range= 32 -> 127
3281 10:02:12.814013
3282 10:02:12.817038 RX Vref 32 -> 127, step: 1
3283 10:02:12.817142
3284 10:02:12.820220 RX Delay -5 -> 252, step: 4
3285 10:02:12.820325
3286 10:02:12.823664 Set Vref, RX VrefLevel [Byte0]: 32
3287 10:02:12.826860 [Byte1]: 32
3288 10:02:12.826971
3289 10:02:12.830119 Set Vref, RX VrefLevel [Byte0]: 33
3290 10:02:12.833222 [Byte1]: 33
3291 10:02:12.833335
3292 10:02:12.836906 Set Vref, RX VrefLevel [Byte0]: 34
3293 10:02:12.839961 [Byte1]: 34
3294 10:02:12.843857
3295 10:02:12.843974 Set Vref, RX VrefLevel [Byte0]: 35
3296 10:02:12.847611 [Byte1]: 35
3297 10:02:12.851647
3298 10:02:12.851761 Set Vref, RX VrefLevel [Byte0]: 36
3299 10:02:12.855080 [Byte1]: 36
3300 10:02:12.859878
3301 10:02:12.859987 Set Vref, RX VrefLevel [Byte0]: 37
3302 10:02:12.863149 [Byte1]: 37
3303 10:02:12.867512
3304 10:02:12.867618 Set Vref, RX VrefLevel [Byte0]: 38
3305 10:02:12.871302 [Byte1]: 38
3306 10:02:12.875357
3307 10:02:12.875465 Set Vref, RX VrefLevel [Byte0]: 39
3308 10:02:12.878917 [Byte1]: 39
3309 10:02:12.883135
3310 10:02:12.883255 Set Vref, RX VrefLevel [Byte0]: 40
3311 10:02:12.886855 [Byte1]: 40
3312 10:02:12.891183
3313 10:02:12.891299 Set Vref, RX VrefLevel [Byte0]: 41
3314 10:02:12.894444 [Byte1]: 41
3315 10:02:12.898773
3316 10:02:12.898890 Set Vref, RX VrefLevel [Byte0]: 42
3317 10:02:12.902535 [Byte1]: 42
3318 10:02:12.907049
3319 10:02:12.907164 Set Vref, RX VrefLevel [Byte0]: 43
3320 10:02:12.910262 [Byte1]: 43
3321 10:02:12.914789
3322 10:02:12.914901 Set Vref, RX VrefLevel [Byte0]: 44
3323 10:02:12.917967 [Byte1]: 44
3324 10:02:12.922423
3325 10:02:12.922531 Set Vref, RX VrefLevel [Byte0]: 45
3326 10:02:12.925671 [Byte1]: 45
3327 10:02:12.930251
3328 10:02:12.930357 Set Vref, RX VrefLevel [Byte0]: 46
3329 10:02:12.933800 [Byte1]: 46
3330 10:02:12.938375
3331 10:02:12.938496 Set Vref, RX VrefLevel [Byte0]: 47
3332 10:02:12.941707 [Byte1]: 47
3333 10:02:12.946168
3334 10:02:12.946273 Set Vref, RX VrefLevel [Byte0]: 48
3335 10:02:12.949321 [Byte1]: 48
3336 10:02:12.953704
3337 10:02:12.953782 Set Vref, RX VrefLevel [Byte0]: 49
3338 10:02:12.957424 [Byte1]: 49
3339 10:02:12.962162
3340 10:02:12.962279 Set Vref, RX VrefLevel [Byte0]: 50
3341 10:02:12.964899 [Byte1]: 50
3342 10:02:12.969361
3343 10:02:12.969475 Set Vref, RX VrefLevel [Byte0]: 51
3344 10:02:12.973193 [Byte1]: 51
3345 10:02:12.977395
3346 10:02:12.977513 Set Vref, RX VrefLevel [Byte0]: 52
3347 10:02:12.981084 [Byte1]: 52
3348 10:02:12.985266
3349 10:02:12.985387 Set Vref, RX VrefLevel [Byte0]: 53
3350 10:02:12.988626 [Byte1]: 53
3351 10:02:12.993044
3352 10:02:12.993167 Set Vref, RX VrefLevel [Byte0]: 54
3353 10:02:12.996666 [Byte1]: 54
3354 10:02:13.001274
3355 10:02:13.001395 Set Vref, RX VrefLevel [Byte0]: 55
3356 10:02:13.004155 [Byte1]: 55
3357 10:02:13.009080
3358 10:02:13.009194 Set Vref, RX VrefLevel [Byte0]: 56
3359 10:02:13.012493 [Byte1]: 56
3360 10:02:13.016780
3361 10:02:13.016885 Set Vref, RX VrefLevel [Byte0]: 57
3362 10:02:13.019770 [Byte1]: 57
3363 10:02:13.024954
3364 10:02:13.025062 Set Vref, RX VrefLevel [Byte0]: 58
3365 10:02:13.027593 [Byte1]: 58
3366 10:02:13.032750
3367 10:02:13.032849 Set Vref, RX VrefLevel [Byte0]: 59
3368 10:02:13.035879 [Byte1]: 59
3369 10:02:13.040316
3370 10:02:13.040430 Set Vref, RX VrefLevel [Byte0]: 60
3371 10:02:13.043325 [Byte1]: 60
3372 10:02:13.047974
3373 10:02:13.048086 Set Vref, RX VrefLevel [Byte0]: 61
3374 10:02:13.051090 [Byte1]: 61
3375 10:02:13.056188
3376 10:02:13.056294 Set Vref, RX VrefLevel [Byte0]: 62
3377 10:02:13.059273 [Byte1]: 62
3378 10:02:13.063779
3379 10:02:13.063904 Set Vref, RX VrefLevel [Byte0]: 63
3380 10:02:13.067048 [Byte1]: 63
3381 10:02:13.071993
3382 10:02:13.072098 Set Vref, RX VrefLevel [Byte0]: 64
3383 10:02:13.074899 [Byte1]: 64
3384 10:02:13.079411
3385 10:02:13.079517 Set Vref, RX VrefLevel [Byte0]: 65
3386 10:02:13.083149 [Byte1]: 65
3387 10:02:13.087115
3388 10:02:13.087220 Set Vref, RX VrefLevel [Byte0]: 66
3389 10:02:13.090973 [Byte1]: 66
3390 10:02:13.095394
3391 10:02:13.095490 Set Vref, RX VrefLevel [Byte0]: 67
3392 10:02:13.098701 [Byte1]: 67
3393 10:02:13.103028
3394 10:02:13.103148 Set Vref, RX VrefLevel [Byte0]: 68
3395 10:02:13.106684 [Byte1]: 68
3396 10:02:13.110859
3397 10:02:13.110966 Set Vref, RX VrefLevel [Byte0]: 69
3398 10:02:13.114070 [Byte1]: 69
3399 10:02:13.118598
3400 10:02:13.118700 Final RX Vref Byte 0 = 54 to rank0
3401 10:02:13.122204 Final RX Vref Byte 1 = 48 to rank0
3402 10:02:13.125667 Final RX Vref Byte 0 = 54 to rank1
3403 10:02:13.129072 Final RX Vref Byte 1 = 48 to rank1==
3404 10:02:13.132101 Dram Type= 6, Freq= 0, CH_1, rank 0
3405 10:02:13.135547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3406 10:02:13.138744 ==
3407 10:02:13.138861 DQS Delay:
3408 10:02:13.138960 DQS0 = 0, DQS1 = 0
3409 10:02:13.141964 DQM Delay:
3410 10:02:13.142052 DQM0 = 120, DQM1 = 116
3411 10:02:13.145554 DQ Delay:
3412 10:02:13.148720 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =118
3413 10:02:13.152427 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =120
3414 10:02:13.155652 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =108
3415 10:02:13.158735 DQ12 =122, DQ13 =124, DQ14 =124, DQ15 =126
3416 10:02:13.158831
3417 10:02:13.158902
3418 10:02:13.165425 [DQSOSCAuto] RK0, (LSB)MR18= 0x215, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 409 ps
3419 10:02:13.168661 CH1 RK0: MR19=404, MR18=215
3420 10:02:13.175614 CH1_RK0: MR19=0x404, MR18=0x215, DQSOSC=401, MR23=63, INC=40, DEC=27
3421 10:02:13.175737
3422 10:02:13.178852 ----->DramcWriteLeveling(PI) begin...
3423 10:02:13.178956 ==
3424 10:02:13.182131 Dram Type= 6, Freq= 0, CH_1, rank 1
3425 10:02:13.185919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3426 10:02:13.186012 ==
3427 10:02:13.189134 Write leveling (Byte 0): 25 => 25
3428 10:02:13.192606 Write leveling (Byte 1): 30 => 30
3429 10:02:13.195622 DramcWriteLeveling(PI) end<-----
3430 10:02:13.195729
3431 10:02:13.195830 ==
3432 10:02:13.198798 Dram Type= 6, Freq= 0, CH_1, rank 1
3433 10:02:13.202453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3434 10:02:13.205352 ==
3435 10:02:13.205456 [Gating] SW mode calibration
3436 10:02:13.215386 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3437 10:02:13.219553 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3438 10:02:13.222673 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3439 10:02:13.228751 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3440 10:02:13.232490 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3441 10:02:13.235843 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3442 10:02:13.242193 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3443 10:02:13.245662 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3444 10:02:13.248897 0 15 24 | B1->B0 | 2d2d 3434 | 0 1 | (1 0) (1 0)
3445 10:02:13.255373 0 15 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 0)
3446 10:02:13.259019 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3447 10:02:13.262685 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3448 10:02:13.268974 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3449 10:02:13.272192 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3450 10:02:13.275526 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3451 10:02:13.278725 1 0 20 | B1->B0 | 2424 2323 | 1 0 | (0 0) (0 0)
3452 10:02:13.285807 1 0 24 | B1->B0 | 4242 2828 | 0 0 | (0 0) (0 0)
3453 10:02:13.288966 1 0 28 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
3454 10:02:13.292291 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3455 10:02:13.298564 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3456 10:02:13.302445 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3457 10:02:13.305711 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3458 10:02:13.311882 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3459 10:02:13.315224 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3460 10:02:13.318914 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3461 10:02:13.325568 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3462 10:02:13.328657 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3463 10:02:13.332692 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3464 10:02:13.338753 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3465 10:02:13.342265 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3466 10:02:13.345712 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 10:02:13.352082 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 10:02:13.355436 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 10:02:13.358735 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 10:02:13.365531 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 10:02:13.368877 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 10:02:13.372048 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 10:02:13.378757 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 10:02:13.382047 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 10:02:13.385505 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 10:02:13.392304 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3477 10:02:13.395590 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3478 10:02:13.398778 Total UI for P1: 0, mck2ui 16
3479 10:02:13.402003 best dqsien dly found for B1: ( 1, 3, 24)
3480 10:02:13.405187 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3481 10:02:13.408345 Total UI for P1: 0, mck2ui 16
3482 10:02:13.412068 best dqsien dly found for B0: ( 1, 3, 26)
3483 10:02:13.415177 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3484 10:02:13.418327 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3485 10:02:13.418402
3486 10:02:13.421568 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3487 10:02:13.428631 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3488 10:02:13.428737 [Gating] SW calibration Done
3489 10:02:13.428851 ==
3490 10:02:13.431814 Dram Type= 6, Freq= 0, CH_1, rank 1
3491 10:02:13.438800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3492 10:02:13.438907 ==
3493 10:02:13.439009 RX Vref Scan: 0
3494 10:02:13.439099
3495 10:02:13.441957 RX Vref 0 -> 0, step: 1
3496 10:02:13.442071
3497 10:02:13.445229 RX Delay -40 -> 252, step: 8
3498 10:02:13.448443 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3499 10:02:13.451526 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3500 10:02:13.455487 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3501 10:02:13.461706 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3502 10:02:13.465471 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3503 10:02:13.468497 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3504 10:02:13.471938 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3505 10:02:13.474910 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3506 10:02:13.481696 iDelay=200, Bit 8, Center 107 (40 ~ 175) 136
3507 10:02:13.484902 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3508 10:02:13.488164 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3509 10:02:13.491791 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3510 10:02:13.494850 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3511 10:02:13.501350 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3512 10:02:13.504538 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3513 10:02:13.507810 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
3514 10:02:13.507893 ==
3515 10:02:13.511340 Dram Type= 6, Freq= 0, CH_1, rank 1
3516 10:02:13.514667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3517 10:02:13.514749 ==
3518 10:02:13.517844 DQS Delay:
3519 10:02:13.517958 DQS0 = 0, DQS1 = 0
3520 10:02:13.521471 DQM Delay:
3521 10:02:13.521618 DQM0 = 119, DQM1 = 118
3522 10:02:13.524423 DQ Delay:
3523 10:02:13.527643 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =115
3524 10:02:13.531613 DQ4 =115, DQ5 =131, DQ6 =131, DQ7 =119
3525 10:02:13.534843 DQ8 =107, DQ9 =107, DQ10 =115, DQ11 =115
3526 10:02:13.537985 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =127
3527 10:02:13.538095
3528 10:02:13.538191
3529 10:02:13.538280 ==
3530 10:02:13.541012 Dram Type= 6, Freq= 0, CH_1, rank 1
3531 10:02:13.544888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3532 10:02:13.544972 ==
3533 10:02:13.545037
3534 10:02:13.545131
3535 10:02:13.547967 TX Vref Scan disable
3536 10:02:13.551154 == TX Byte 0 ==
3537 10:02:13.554464 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3538 10:02:13.557646 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3539 10:02:13.561002 == TX Byte 1 ==
3540 10:02:13.564734 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3541 10:02:13.567753 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3542 10:02:13.567860 ==
3543 10:02:13.570801 Dram Type= 6, Freq= 0, CH_1, rank 1
3544 10:02:13.577268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3545 10:02:13.577374 ==
3546 10:02:13.588254 TX Vref=22, minBit 9, minWin=25, winSum=419
3547 10:02:13.591429 TX Vref=24, minBit 10, minWin=25, winSum=423
3548 10:02:13.595051 TX Vref=26, minBit 2, minWin=26, winSum=433
3549 10:02:13.598202 TX Vref=28, minBit 10, minWin=26, winSum=435
3550 10:02:13.601305 TX Vref=30, minBit 9, minWin=26, winSum=436
3551 10:02:13.608352 TX Vref=32, minBit 9, minWin=26, winSum=436
3552 10:02:13.611463 [TxChooseVref] Worse bit 9, Min win 26, Win sum 436, Final Vref 30
3553 10:02:13.611573
3554 10:02:13.614634 Final TX Range 1 Vref 30
3555 10:02:13.614710
3556 10:02:13.614773 ==
3557 10:02:13.617963 Dram Type= 6, Freq= 0, CH_1, rank 1
3558 10:02:13.621034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3559 10:02:13.624454 ==
3560 10:02:13.624553
3561 10:02:13.624642
3562 10:02:13.624735 TX Vref Scan disable
3563 10:02:13.628295 == TX Byte 0 ==
3564 10:02:13.631463 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3565 10:02:13.638039 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3566 10:02:13.638126 == TX Byte 1 ==
3567 10:02:13.641421 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3568 10:02:13.647907 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3569 10:02:13.647987
3570 10:02:13.648050 [DATLAT]
3571 10:02:13.648116 Freq=1200, CH1 RK1
3572 10:02:13.648176
3573 10:02:13.651351 DATLAT Default: 0xd
3574 10:02:13.651456 0, 0xFFFF, sum = 0
3575 10:02:13.654448 1, 0xFFFF, sum = 0
3576 10:02:13.658125 2, 0xFFFF, sum = 0
3577 10:02:13.658209 3, 0xFFFF, sum = 0
3578 10:02:13.661307 4, 0xFFFF, sum = 0
3579 10:02:13.661407 5, 0xFFFF, sum = 0
3580 10:02:13.664500 6, 0xFFFF, sum = 0
3581 10:02:13.664598 7, 0xFFFF, sum = 0
3582 10:02:13.667822 8, 0xFFFF, sum = 0
3583 10:02:13.667922 9, 0xFFFF, sum = 0
3584 10:02:13.671308 10, 0xFFFF, sum = 0
3585 10:02:13.671413 11, 0xFFFF, sum = 0
3586 10:02:13.674225 12, 0x0, sum = 1
3587 10:02:13.674299 13, 0x0, sum = 2
3588 10:02:13.677978 14, 0x0, sum = 3
3589 10:02:13.678082 15, 0x0, sum = 4
3590 10:02:13.681149 best_step = 13
3591 10:02:13.681245
3592 10:02:13.681336 ==
3593 10:02:13.684380 Dram Type= 6, Freq= 0, CH_1, rank 1
3594 10:02:13.688005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3595 10:02:13.688086 ==
3596 10:02:13.688150 RX Vref Scan: 0
3597 10:02:13.691381
3598 10:02:13.691491 RX Vref 0 -> 0, step: 1
3599 10:02:13.691581
3600 10:02:13.694334 RX Delay -5 -> 252, step: 4
3601 10:02:13.697528 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3602 10:02:13.704089 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3603 10:02:13.707501 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3604 10:02:13.710651 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3605 10:02:13.714321 iDelay=195, Bit 4, Center 118 (59 ~ 178) 120
3606 10:02:13.717549 iDelay=195, Bit 5, Center 132 (71 ~ 194) 124
3607 10:02:13.723800 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3608 10:02:13.727695 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3609 10:02:13.730920 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3610 10:02:13.734225 iDelay=195, Bit 9, Center 106 (47 ~ 166) 120
3611 10:02:13.737384 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3612 10:02:13.744270 iDelay=195, Bit 11, Center 110 (51 ~ 170) 120
3613 10:02:13.747590 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3614 10:02:13.750611 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3615 10:02:13.753615 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3616 10:02:13.760226 iDelay=195, Bit 15, Center 126 (67 ~ 186) 120
3617 10:02:13.760306 ==
3618 10:02:13.763902 Dram Type= 6, Freq= 0, CH_1, rank 1
3619 10:02:13.767073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3620 10:02:13.767145 ==
3621 10:02:13.767213 DQS Delay:
3622 10:02:13.770712 DQS0 = 0, DQS1 = 0
3623 10:02:13.770816 DQM Delay:
3624 10:02:13.773702 DQM0 = 120, DQM1 = 117
3625 10:02:13.773777 DQ Delay:
3626 10:02:13.777135 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =118
3627 10:02:13.780728 DQ4 =118, DQ5 =132, DQ6 =130, DQ7 =120
3628 10:02:13.784014 DQ8 =106, DQ9 =106, DQ10 =116, DQ11 =110
3629 10:02:13.787469 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =126
3630 10:02:13.787543
3631 10:02:13.787614
3632 10:02:13.797605 [DQSOSCAuto] RK1, (LSB)MR18= 0x11ee, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 403 ps
3633 10:02:13.800630 CH1 RK1: MR19=403, MR18=11EE
3634 10:02:13.803756 CH1_RK1: MR19=0x403, MR18=0x11EE, DQSOSC=403, MR23=63, INC=40, DEC=26
3635 10:02:13.807518 [RxdqsGatingPostProcess] freq 1200
3636 10:02:13.813835 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3637 10:02:13.817267 best DQS0 dly(2T, 0.5T) = (0, 11)
3638 10:02:13.820470 best DQS1 dly(2T, 0.5T) = (0, 11)
3639 10:02:13.823544 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3640 10:02:13.826772 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3641 10:02:13.830118 best DQS0 dly(2T, 0.5T) = (0, 11)
3642 10:02:13.833882 best DQS1 dly(2T, 0.5T) = (0, 11)
3643 10:02:13.836589 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3644 10:02:13.840302 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3645 10:02:13.843593 Pre-setting of DQS Precalculation
3646 10:02:13.846658 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3647 10:02:13.853103 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3648 10:02:13.863526 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3649 10:02:13.863633
3650 10:02:13.863714
3651 10:02:13.863776 [Calibration Summary] 2400 Mbps
3652 10:02:13.866522 CH 0, Rank 0
3653 10:02:13.870213 SW Impedance : PASS
3654 10:02:13.870288 DUTY Scan : NO K
3655 10:02:13.873243 ZQ Calibration : PASS
3656 10:02:13.873316 Jitter Meter : NO K
3657 10:02:13.876344 CBT Training : PASS
3658 10:02:13.879940 Write leveling : PASS
3659 10:02:13.880014 RX DQS gating : PASS
3660 10:02:13.882833 RX DQ/DQS(RDDQC) : PASS
3661 10:02:13.886226 TX DQ/DQS : PASS
3662 10:02:13.886328 RX DATLAT : PASS
3663 10:02:13.890068 RX DQ/DQS(Engine): PASS
3664 10:02:13.892879 TX OE : NO K
3665 10:02:13.892976 All Pass.
3666 10:02:13.893040
3667 10:02:13.893099 CH 0, Rank 1
3668 10:02:13.896535 SW Impedance : PASS
3669 10:02:13.899924 DUTY Scan : NO K
3670 10:02:13.900004 ZQ Calibration : PASS
3671 10:02:13.902809 Jitter Meter : NO K
3672 10:02:13.906154 CBT Training : PASS
3673 10:02:13.906229 Write leveling : PASS
3674 10:02:13.909728 RX DQS gating : PASS
3675 10:02:13.912669 RX DQ/DQS(RDDQC) : PASS
3676 10:02:13.912751 TX DQ/DQS : PASS
3677 10:02:13.916162 RX DATLAT : PASS
3678 10:02:13.919336 RX DQ/DQS(Engine): PASS
3679 10:02:13.919412 TX OE : NO K
3680 10:02:13.919476 All Pass.
3681 10:02:13.922821
3682 10:02:13.922892 CH 1, Rank 0
3683 10:02:13.925918 SW Impedance : PASS
3684 10:02:13.926085 DUTY Scan : NO K
3685 10:02:13.929418 ZQ Calibration : PASS
3686 10:02:13.929505 Jitter Meter : NO K
3687 10:02:13.933159 CBT Training : PASS
3688 10:02:13.936346 Write leveling : PASS
3689 10:02:13.936429 RX DQS gating : PASS
3690 10:02:13.939563 RX DQ/DQS(RDDQC) : PASS
3691 10:02:13.942809 TX DQ/DQS : PASS
3692 10:02:13.942909 RX DATLAT : PASS
3693 10:02:13.945880 RX DQ/DQS(Engine): PASS
3694 10:02:13.949032 TX OE : NO K
3695 10:02:13.949113 All Pass.
3696 10:02:13.949177
3697 10:02:13.949266 CH 1, Rank 1
3698 10:02:13.952722 SW Impedance : PASS
3699 10:02:13.956069 DUTY Scan : NO K
3700 10:02:13.956151 ZQ Calibration : PASS
3701 10:02:13.959160 Jitter Meter : NO K
3702 10:02:13.962425 CBT Training : PASS
3703 10:02:13.962507 Write leveling : PASS
3704 10:02:13.965728 RX DQS gating : PASS
3705 10:02:13.969453 RX DQ/DQS(RDDQC) : PASS
3706 10:02:13.969536 TX DQ/DQS : PASS
3707 10:02:13.972443 RX DATLAT : PASS
3708 10:02:13.975652 RX DQ/DQS(Engine): PASS
3709 10:02:13.975768 TX OE : NO K
3710 10:02:13.975837 All Pass.
3711 10:02:13.979396
3712 10:02:13.979477 DramC Write-DBI off
3713 10:02:13.982719 PER_BANK_REFRESH: Hybrid Mode
3714 10:02:13.982800 TX_TRACKING: ON
3715 10:02:13.992729 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3716 10:02:13.995631 [FAST_K] Save calibration result to emmc
3717 10:02:13.998911 dramc_set_vcore_voltage set vcore to 650000
3718 10:02:14.002286 Read voltage for 600, 5
3719 10:02:14.002412 Vio18 = 0
3720 10:02:14.005455 Vcore = 650000
3721 10:02:14.005566 Vdram = 0
3722 10:02:14.005643 Vddq = 0
3723 10:02:14.005735 Vmddr = 0
3724 10:02:14.012464 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3725 10:02:14.019288 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3726 10:02:14.019383 MEM_TYPE=3, freq_sel=19
3727 10:02:14.022457 sv_algorithm_assistance_LP4_1600
3728 10:02:14.025889 ============ PULL DRAM RESETB DOWN ============
3729 10:02:14.032067 ========== PULL DRAM RESETB DOWN end =========
3730 10:02:14.035787 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3731 10:02:14.039219 ===================================
3732 10:02:14.042169 LPDDR4 DRAM CONFIGURATION
3733 10:02:14.045515 ===================================
3734 10:02:14.045620 EX_ROW_EN[0] = 0x0
3735 10:02:14.049332 EX_ROW_EN[1] = 0x0
3736 10:02:14.049437 LP4Y_EN = 0x0
3737 10:02:14.052256 WORK_FSP = 0x0
3738 10:02:14.052361 WL = 0x2
3739 10:02:14.055555 RL = 0x2
3740 10:02:14.055630 BL = 0x2
3741 10:02:14.059143 RPST = 0x0
3742 10:02:14.062218 RD_PRE = 0x0
3743 10:02:14.062290 WR_PRE = 0x1
3744 10:02:14.065474 WR_PST = 0x0
3745 10:02:14.065589 DBI_WR = 0x0
3746 10:02:14.068755 DBI_RD = 0x0
3747 10:02:14.068854 OTF = 0x1
3748 10:02:14.072442 ===================================
3749 10:02:14.075657 ===================================
3750 10:02:14.078810 ANA top config
3751 10:02:14.082451 ===================================
3752 10:02:14.082536 DLL_ASYNC_EN = 0
3753 10:02:14.085796 ALL_SLAVE_EN = 1
3754 10:02:14.088956 NEW_RANK_MODE = 1
3755 10:02:14.092176 DLL_IDLE_MODE = 1
3756 10:02:14.092260 LP45_APHY_COMB_EN = 1
3757 10:02:14.095323 TX_ODT_DIS = 1
3758 10:02:14.098670 NEW_8X_MODE = 1
3759 10:02:14.101711 ===================================
3760 10:02:14.105129 ===================================
3761 10:02:14.108603 data_rate = 1200
3762 10:02:14.111934 CKR = 1
3763 10:02:14.115550 DQ_P2S_RATIO = 8
3764 10:02:14.115637 ===================================
3765 10:02:14.118673 CA_P2S_RATIO = 8
3766 10:02:14.121974 DQ_CA_OPEN = 0
3767 10:02:14.125192 DQ_SEMI_OPEN = 0
3768 10:02:14.129057 CA_SEMI_OPEN = 0
3769 10:02:14.132276 CA_FULL_RATE = 0
3770 10:02:14.132360 DQ_CKDIV4_EN = 1
3771 10:02:14.135468 CA_CKDIV4_EN = 1
3772 10:02:14.138660 CA_PREDIV_EN = 0
3773 10:02:14.141978 PH8_DLY = 0
3774 10:02:14.145213 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3775 10:02:14.148971 DQ_AAMCK_DIV = 4
3776 10:02:14.149054 CA_AAMCK_DIV = 4
3777 10:02:14.152210 CA_ADMCK_DIV = 4
3778 10:02:14.155779 DQ_TRACK_CA_EN = 0
3779 10:02:14.158847 CA_PICK = 600
3780 10:02:14.161884 CA_MCKIO = 600
3781 10:02:14.165713 MCKIO_SEMI = 0
3782 10:02:14.168553 PLL_FREQ = 2288
3783 10:02:14.168654 DQ_UI_PI_RATIO = 32
3784 10:02:14.171950 CA_UI_PI_RATIO = 0
3785 10:02:14.175399 ===================================
3786 10:02:14.178886 ===================================
3787 10:02:14.182333 memory_type:LPDDR4
3788 10:02:14.185129 GP_NUM : 10
3789 10:02:14.185215 SRAM_EN : 1
3790 10:02:14.188870 MD32_EN : 0
3791 10:02:14.192186 ===================================
3792 10:02:14.192293 [ANA_INIT] >>>>>>>>>>>>>>
3793 10:02:14.195483 <<<<<< [CONFIGURE PHASE]: ANA_TX
3794 10:02:14.198642 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3795 10:02:14.201993 ===================================
3796 10:02:14.205234 data_rate = 1200,PCW = 0X5800
3797 10:02:14.208638 ===================================
3798 10:02:14.211722 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3799 10:02:14.218503 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3800 10:02:14.222082 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3801 10:02:14.228700 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3802 10:02:14.231880 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3803 10:02:14.234963 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3804 10:02:14.238196 [ANA_INIT] flow start
3805 10:02:14.238271 [ANA_INIT] PLL >>>>>>>>
3806 10:02:14.242106 [ANA_INIT] PLL <<<<<<<<
3807 10:02:14.245001 [ANA_INIT] MIDPI >>>>>>>>
3808 10:02:14.245105 [ANA_INIT] MIDPI <<<<<<<<
3809 10:02:14.248600 [ANA_INIT] DLL >>>>>>>>
3810 10:02:14.251954 [ANA_INIT] flow end
3811 10:02:14.255146 ============ LP4 DIFF to SE enter ============
3812 10:02:14.259188 ============ LP4 DIFF to SE exit ============
3813 10:02:14.262298 [ANA_INIT] <<<<<<<<<<<<<
3814 10:02:14.265467 [Flow] Enable top DCM control >>>>>
3815 10:02:14.268764 [Flow] Enable top DCM control <<<<<
3816 10:02:14.279606 Enable DLL master slave shuffle
3817 10:02:14.279701 ==============================================================
3818 10:02:14.279769 Gating Mode config
3819 10:02:14.282088 ==============================================================
3820 10:02:14.285448 Config description:
3821 10:02:14.295145 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3822 10:02:14.302038 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3823 10:02:14.305456 SELPH_MODE 0: By rank 1: By Phase
3824 10:02:14.311922 ==============================================================
3825 10:02:14.315025 GAT_TRACK_EN = 1
3826 10:02:14.318100 RX_GATING_MODE = 2
3827 10:02:14.321963 RX_GATING_TRACK_MODE = 2
3828 10:02:14.325163 SELPH_MODE = 1
3829 10:02:14.328337 PICG_EARLY_EN = 1
3830 10:02:14.331745 VALID_LAT_VALUE = 1
3831 10:02:14.334989 ==============================================================
3832 10:02:14.338249 Enter into Gating configuration >>>>
3833 10:02:14.341766 Exit from Gating configuration <<<<
3834 10:02:14.344906 Enter into DVFS_PRE_config >>>>>
3835 10:02:14.354770 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3836 10:02:14.358104 Exit from DVFS_PRE_config <<<<<
3837 10:02:14.361907 Enter into PICG configuration >>>>
3838 10:02:14.365096 Exit from PICG configuration <<<<
3839 10:02:14.368375 [RX_INPUT] configuration >>>>>
3840 10:02:14.371375 [RX_INPUT] configuration <<<<<
3841 10:02:14.378263 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3842 10:02:14.381468 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3843 10:02:14.388387 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3844 10:02:14.394730 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3845 10:02:14.401638 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3846 10:02:14.408349 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3847 10:02:14.411355 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3848 10:02:14.414656 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3849 10:02:14.418370 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3850 10:02:14.421857 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3851 10:02:14.428426 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3852 10:02:14.431685 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3853 10:02:14.435241 ===================================
3854 10:02:14.438304 LPDDR4 DRAM CONFIGURATION
3855 10:02:14.441457 ===================================
3856 10:02:14.441586 EX_ROW_EN[0] = 0x0
3857 10:02:14.445015 EX_ROW_EN[1] = 0x0
3858 10:02:14.445101 LP4Y_EN = 0x0
3859 10:02:14.447929 WORK_FSP = 0x0
3860 10:02:14.448022 WL = 0x2
3861 10:02:14.451325 RL = 0x2
3862 10:02:14.454324 BL = 0x2
3863 10:02:14.454433 RPST = 0x0
3864 10:02:14.458057 RD_PRE = 0x0
3865 10:02:14.458175 WR_PRE = 0x1
3866 10:02:14.461397 WR_PST = 0x0
3867 10:02:14.461512 DBI_WR = 0x0
3868 10:02:14.464555 DBI_RD = 0x0
3869 10:02:14.464660 OTF = 0x1
3870 10:02:14.467963 ===================================
3871 10:02:14.471035 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3872 10:02:14.477999 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3873 10:02:14.481542 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3874 10:02:14.484741 ===================================
3875 10:02:14.487754 LPDDR4 DRAM CONFIGURATION
3876 10:02:14.491526 ===================================
3877 10:02:14.491619 EX_ROW_EN[0] = 0x10
3878 10:02:14.494633 EX_ROW_EN[1] = 0x0
3879 10:02:14.494758 LP4Y_EN = 0x0
3880 10:02:14.497698 WORK_FSP = 0x0
3881 10:02:14.497802 WL = 0x2
3882 10:02:14.501507 RL = 0x2
3883 10:02:14.501626 BL = 0x2
3884 10:02:14.504556 RPST = 0x0
3885 10:02:14.504676 RD_PRE = 0x0
3886 10:02:14.507600 WR_PRE = 0x1
3887 10:02:14.511533 WR_PST = 0x0
3888 10:02:14.511662 DBI_WR = 0x0
3889 10:02:14.514607 DBI_RD = 0x0
3890 10:02:14.514710 OTF = 0x1
3891 10:02:14.517709 ===================================
3892 10:02:14.524567 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3893 10:02:14.528340 nWR fixed to 30
3894 10:02:14.531408 [ModeRegInit_LP4] CH0 RK0
3895 10:02:14.531510 [ModeRegInit_LP4] CH0 RK1
3896 10:02:14.534880 [ModeRegInit_LP4] CH1 RK0
3897 10:02:14.538083 [ModeRegInit_LP4] CH1 RK1
3898 10:02:14.538204 match AC timing 17
3899 10:02:14.544788 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3900 10:02:14.548201 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3901 10:02:14.551526 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3902 10:02:14.558125 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3903 10:02:14.560916 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3904 10:02:14.561029 ==
3905 10:02:14.564753 Dram Type= 6, Freq= 0, CH_0, rank 0
3906 10:02:14.567655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3907 10:02:14.567822 ==
3908 10:02:14.574767 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3909 10:02:14.581370 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3910 10:02:14.584939 [CA 0] Center 35 (5~66) winsize 62
3911 10:02:14.587764 [CA 1] Center 36 (5~67) winsize 63
3912 10:02:14.591026 [CA 2] Center 33 (3~64) winsize 62
3913 10:02:14.594817 [CA 3] Center 33 (2~64) winsize 63
3914 10:02:14.597875 [CA 4] Center 33 (2~64) winsize 63
3915 10:02:14.601721 [CA 5] Center 32 (2~63) winsize 62
3916 10:02:14.601815
3917 10:02:14.604835 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3918 10:02:14.604951
3919 10:02:14.607895 [CATrainingPosCal] consider 1 rank data
3920 10:02:14.611034 u2DelayCellTimex100 = 270/100 ps
3921 10:02:14.614234 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3922 10:02:14.618011 CA1 delay=36 (5~67),Diff = 4 PI (38 cell)
3923 10:02:14.621184 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3924 10:02:14.625054 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3925 10:02:14.628127 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3926 10:02:14.631346 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3927 10:02:14.634439
3928 10:02:14.637775 CA PerBit enable=1, Macro0, CA PI delay=32
3929 10:02:14.637886
3930 10:02:14.640848 [CBTSetCACLKResult] CA Dly = 32
3931 10:02:14.640934 CS Dly: 5 (0~36)
3932 10:02:14.641001 ==
3933 10:02:14.643867 Dram Type= 6, Freq= 0, CH_0, rank 1
3934 10:02:14.647559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3935 10:02:14.650703 ==
3936 10:02:14.653932 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3937 10:02:14.660995 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3938 10:02:14.663857 [CA 0] Center 35 (5~66) winsize 62
3939 10:02:14.667238 [CA 1] Center 35 (5~66) winsize 62
3940 10:02:14.670595 [CA 2] Center 34 (3~65) winsize 63
3941 10:02:14.673856 [CA 3] Center 33 (3~64) winsize 62
3942 10:02:14.677007 [CA 4] Center 33 (2~64) winsize 63
3943 10:02:14.680325 [CA 5] Center 32 (2~63) winsize 62
3944 10:02:14.680451
3945 10:02:14.683458 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3946 10:02:14.683570
3947 10:02:14.687246 [CATrainingPosCal] consider 2 rank data
3948 10:02:14.690298 u2DelayCellTimex100 = 270/100 ps
3949 10:02:14.693444 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3950 10:02:14.696851 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3951 10:02:14.700273 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3952 10:02:14.706732 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3953 10:02:14.710131 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3954 10:02:14.713643 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3955 10:02:14.713739
3956 10:02:14.716606 CA PerBit enable=1, Macro0, CA PI delay=32
3957 10:02:14.716703
3958 10:02:14.720362 [CBTSetCACLKResult] CA Dly = 32
3959 10:02:14.720453 CS Dly: 5 (0~36)
3960 10:02:14.720555
3961 10:02:14.723687 ----->DramcWriteLeveling(PI) begin...
3962 10:02:14.723792 ==
3963 10:02:14.726679 Dram Type= 6, Freq= 0, CH_0, rank 0
3964 10:02:14.733683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3965 10:02:14.733789 ==
3966 10:02:14.736801 Write leveling (Byte 0): 35 => 35
3967 10:02:14.739888 Write leveling (Byte 1): 31 => 31
3968 10:02:14.740003 DramcWriteLeveling(PI) end<-----
3969 10:02:14.743694
3970 10:02:14.743800 ==
3971 10:02:14.746620 Dram Type= 6, Freq= 0, CH_0, rank 0
3972 10:02:14.749851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3973 10:02:14.749956 ==
3974 10:02:14.753483 [Gating] SW mode calibration
3975 10:02:14.759876 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3976 10:02:14.763663 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3977 10:02:14.769864 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3978 10:02:14.772944 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3979 10:02:14.776599 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3980 10:02:14.782980 0 9 12 | B1->B0 | 3434 3333 | 1 0 | (1 0) (1 1)
3981 10:02:14.786675 0 9 16 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
3982 10:02:14.789762 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3983 10:02:14.796309 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3984 10:02:14.800045 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3985 10:02:14.803061 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3986 10:02:14.809764 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3987 10:02:14.812865 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3988 10:02:14.816212 0 10 12 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
3989 10:02:14.823068 0 10 16 | B1->B0 | 3232 4646 | 0 0 | (0 0) (0 0)
3990 10:02:14.826502 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3991 10:02:14.829823 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3992 10:02:14.836303 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3993 10:02:14.839597 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3994 10:02:14.842681 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3995 10:02:14.849761 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3996 10:02:14.852724 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3997 10:02:14.856268 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 10:02:14.863072 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 10:02:14.866169 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 10:02:14.869325 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 10:02:14.876201 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 10:02:14.879257 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 10:02:14.883093 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 10:02:14.885996 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 10:02:14.892847 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 10:02:14.896132 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 10:02:14.899456 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 10:02:14.906117 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 10:02:14.909309 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 10:02:14.912944 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 10:02:14.919393 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 10:02:14.922631 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4013 10:02:14.925904 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4014 10:02:14.929673 Total UI for P1: 0, mck2ui 16
4015 10:02:14.932369 best dqsien dly found for B0: ( 0, 13, 12)
4016 10:02:14.939035 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4017 10:02:14.939133 Total UI for P1: 0, mck2ui 16
4018 10:02:14.945738 best dqsien dly found for B1: ( 0, 13, 18)
4019 10:02:14.949462 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4020 10:02:14.952614 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4021 10:02:14.952709
4022 10:02:14.956156 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4023 10:02:14.959367 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4024 10:02:14.963081 [Gating] SW calibration Done
4025 10:02:14.963202 ==
4026 10:02:14.965833 Dram Type= 6, Freq= 0, CH_0, rank 0
4027 10:02:14.968925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4028 10:02:14.969022 ==
4029 10:02:14.972781 RX Vref Scan: 0
4030 10:02:14.972861
4031 10:02:14.972926 RX Vref 0 -> 0, step: 1
4032 10:02:14.975818
4033 10:02:14.975925 RX Delay -230 -> 252, step: 16
4034 10:02:14.982192 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4035 10:02:14.985879 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4036 10:02:14.988999 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4037 10:02:14.992083 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4038 10:02:14.995783 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4039 10:02:15.002578 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4040 10:02:15.005893 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4041 10:02:15.009112 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4042 10:02:15.012096 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4043 10:02:15.018996 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4044 10:02:15.022663 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4045 10:02:15.025925 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4046 10:02:15.028843 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4047 10:02:15.035603 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4048 10:02:15.038826 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4049 10:02:15.042484 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4050 10:02:15.042613 ==
4051 10:02:15.045573 Dram Type= 6, Freq= 0, CH_0, rank 0
4052 10:02:15.049170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4053 10:02:15.049303 ==
4054 10:02:15.052260 DQS Delay:
4055 10:02:15.052356 DQS0 = 0, DQS1 = 0
4056 10:02:15.055442 DQM Delay:
4057 10:02:15.055533 DQM0 = 52, DQM1 = 45
4058 10:02:15.055601 DQ Delay:
4059 10:02:15.059126 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4060 10:02:15.062005 DQ4 =49, DQ5 =49, DQ6 =57, DQ7 =57
4061 10:02:15.065472 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4062 10:02:15.068888 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =49
4063 10:02:15.068978
4064 10:02:15.069045
4065 10:02:15.072053 ==
4066 10:02:15.072164 Dram Type= 6, Freq= 0, CH_0, rank 0
4067 10:02:15.079079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4068 10:02:15.079200 ==
4069 10:02:15.079308
4070 10:02:15.079405
4071 10:02:15.082270 TX Vref Scan disable
4072 10:02:15.082379 == TX Byte 0 ==
4073 10:02:15.085509 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4074 10:02:15.092561 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4075 10:02:15.092660 == TX Byte 1 ==
4076 10:02:15.095495 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4077 10:02:15.102311 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4078 10:02:15.102421 ==
4079 10:02:15.105457 Dram Type= 6, Freq= 0, CH_0, rank 0
4080 10:02:15.108567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4081 10:02:15.108658 ==
4082 10:02:15.108725
4083 10:02:15.108787
4084 10:02:15.111973 TX Vref Scan disable
4085 10:02:15.115148 == TX Byte 0 ==
4086 10:02:15.119044 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4087 10:02:15.122167 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4088 10:02:15.125317 == TX Byte 1 ==
4089 10:02:15.128370 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4090 10:02:15.132074 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4091 10:02:15.132194
4092 10:02:15.135209 [DATLAT]
4093 10:02:15.135330 Freq=600, CH0 RK0
4094 10:02:15.135426
4095 10:02:15.138241 DATLAT Default: 0x9
4096 10:02:15.138322 0, 0xFFFF, sum = 0
4097 10:02:15.141948 1, 0xFFFF, sum = 0
4098 10:02:15.142074 2, 0xFFFF, sum = 0
4099 10:02:15.144919 3, 0xFFFF, sum = 0
4100 10:02:15.145057 4, 0xFFFF, sum = 0
4101 10:02:15.148521 5, 0xFFFF, sum = 0
4102 10:02:15.148611 6, 0xFFFF, sum = 0
4103 10:02:15.152013 7, 0xFFFF, sum = 0
4104 10:02:15.152127 8, 0x0, sum = 1
4105 10:02:15.155359 9, 0x0, sum = 2
4106 10:02:15.155470 10, 0x0, sum = 3
4107 10:02:15.158500 11, 0x0, sum = 4
4108 10:02:15.158613 best_step = 9
4109 10:02:15.158715
4110 10:02:15.158813 ==
4111 10:02:15.161808 Dram Type= 6, Freq= 0, CH_0, rank 0
4112 10:02:15.165217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4113 10:02:15.168292 ==
4114 10:02:15.168402 RX Vref Scan: 1
4115 10:02:15.168500
4116 10:02:15.171621 RX Vref 0 -> 0, step: 1
4117 10:02:15.171718
4118 10:02:15.175275 RX Delay -163 -> 252, step: 8
4119 10:02:15.175381
4120 10:02:15.178257 Set Vref, RX VrefLevel [Byte0]: 56
4121 10:02:15.181930 [Byte1]: 47
4122 10:02:15.182010
4123 10:02:15.184780 Final RX Vref Byte 0 = 56 to rank0
4124 10:02:15.187971 Final RX Vref Byte 1 = 47 to rank0
4125 10:02:15.191786 Final RX Vref Byte 0 = 56 to rank1
4126 10:02:15.194715 Final RX Vref Byte 1 = 47 to rank1==
4127 10:02:15.198127 Dram Type= 6, Freq= 0, CH_0, rank 0
4128 10:02:15.201263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4129 10:02:15.201351 ==
4130 10:02:15.204767 DQS Delay:
4131 10:02:15.204853 DQS0 = 0, DQS1 = 0
4132 10:02:15.204920 DQM Delay:
4133 10:02:15.207869 DQM0 = 53, DQM1 = 45
4134 10:02:15.207955 DQ Delay:
4135 10:02:15.211669 DQ0 =52, DQ1 =56, DQ2 =48, DQ3 =52
4136 10:02:15.214846 DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =60
4137 10:02:15.217963 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =40
4138 10:02:15.221102 DQ12 =48, DQ13 =48, DQ14 =56, DQ15 =52
4139 10:02:15.221187
4140 10:02:15.221255
4141 10:02:15.231228 [DQSOSCAuto] RK0, (LSB)MR18= 0x7366, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 388 ps
4142 10:02:15.231329 CH0 RK0: MR19=808, MR18=7366
4143 10:02:15.238012 CH0_RK0: MR19=0x808, MR18=0x7366, DQSOSC=388, MR23=63, INC=174, DEC=116
4144 10:02:15.238103
4145 10:02:15.241132 ----->DramcWriteLeveling(PI) begin...
4146 10:02:15.244285 ==
4147 10:02:15.244397 Dram Type= 6, Freq= 0, CH_0, rank 1
4148 10:02:15.250925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4149 10:02:15.251040 ==
4150 10:02:15.254217 Write leveling (Byte 0): 35 => 35
4151 10:02:15.257794 Write leveling (Byte 1): 29 => 29
4152 10:02:15.261467 DramcWriteLeveling(PI) end<-----
4153 10:02:15.261571
4154 10:02:15.261674 ==
4155 10:02:15.264343 Dram Type= 6, Freq= 0, CH_0, rank 1
4156 10:02:15.267413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4157 10:02:15.267495 ==
4158 10:02:15.270724 [Gating] SW mode calibration
4159 10:02:15.277537 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4160 10:02:15.284334 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4161 10:02:15.287300 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4162 10:02:15.291098 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4163 10:02:15.294287 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4164 10:02:15.300620 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4165 10:02:15.303832 0 9 16 | B1->B0 | 2424 2828 | 1 0 | (1 0) (0 0)
4166 10:02:15.307785 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4167 10:02:15.314147 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4168 10:02:15.317498 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4169 10:02:15.320519 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4170 10:02:15.327658 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4171 10:02:15.330780 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4172 10:02:15.333884 0 10 12 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
4173 10:02:15.340681 0 10 16 | B1->B0 | 3d3d 3f3f | 0 0 | (0 0) (0 0)
4174 10:02:15.343728 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4175 10:02:15.347476 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4176 10:02:15.353610 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4177 10:02:15.357243 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4178 10:02:15.360183 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4179 10:02:15.366964 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4180 10:02:15.370688 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4181 10:02:15.373727 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4182 10:02:15.380258 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 10:02:15.383780 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4184 10:02:15.387150 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 10:02:15.393802 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 10:02:15.396873 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 10:02:15.400041 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 10:02:15.407010 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 10:02:15.410590 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 10:02:15.413651 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 10:02:15.420712 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 10:02:15.423537 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 10:02:15.427041 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 10:02:15.433376 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 10:02:15.437031 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 10:02:15.440308 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4197 10:02:15.443367 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4198 10:02:15.450043 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4199 10:02:15.453938 Total UI for P1: 0, mck2ui 16
4200 10:02:15.456869 best dqsien dly found for B0: ( 0, 13, 14)
4201 10:02:15.459980 Total UI for P1: 0, mck2ui 16
4202 10:02:15.463099 best dqsien dly found for B1: ( 0, 13, 14)
4203 10:02:15.466660 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4204 10:02:15.469824 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4205 10:02:15.469935
4206 10:02:15.473243 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4207 10:02:15.476652 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4208 10:02:15.480148 [Gating] SW calibration Done
4209 10:02:15.480265 ==
4210 10:02:15.483351 Dram Type= 6, Freq= 0, CH_0, rank 1
4211 10:02:15.486286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4212 10:02:15.486407 ==
4213 10:02:15.489595 RX Vref Scan: 0
4214 10:02:15.489682
4215 10:02:15.493207 RX Vref 0 -> 0, step: 1
4216 10:02:15.493325
4217 10:02:15.493420 RX Delay -230 -> 252, step: 16
4218 10:02:15.500434 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4219 10:02:15.503486 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4220 10:02:15.506580 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4221 10:02:15.509759 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4222 10:02:15.516510 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4223 10:02:15.520106 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4224 10:02:15.523178 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4225 10:02:15.526333 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4226 10:02:15.529896 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4227 10:02:15.536467 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4228 10:02:15.540216 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4229 10:02:15.543157 iDelay=218, Bit 11, Center 41 (-102 ~ 185) 288
4230 10:02:15.546946 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4231 10:02:15.553511 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4232 10:02:15.556689 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4233 10:02:15.560373 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4234 10:02:15.560485 ==
4235 10:02:15.563491 Dram Type= 6, Freq= 0, CH_0, rank 1
4236 10:02:15.566534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4237 10:02:15.569602 ==
4238 10:02:15.569689 DQS Delay:
4239 10:02:15.569756 DQS0 = 0, DQS1 = 0
4240 10:02:15.573225 DQM Delay:
4241 10:02:15.573309 DQM0 = 52, DQM1 = 44
4242 10:02:15.576283 DQ Delay:
4243 10:02:15.576379 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4244 10:02:15.580118 DQ4 =57, DQ5 =49, DQ6 =57, DQ7 =57
4245 10:02:15.583189 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4246 10:02:15.586342 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4247 10:02:15.586425
4248 10:02:15.589982
4249 10:02:15.590085 ==
4250 10:02:15.592898 Dram Type= 6, Freq= 0, CH_0, rank 1
4251 10:02:15.596619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4252 10:02:15.596704 ==
4253 10:02:15.596771
4254 10:02:15.596834
4255 10:02:15.599782 TX Vref Scan disable
4256 10:02:15.599861 == TX Byte 0 ==
4257 10:02:15.606350 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4258 10:02:15.609527 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4259 10:02:15.609652 == TX Byte 1 ==
4260 10:02:15.616274 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4261 10:02:15.619275 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4262 10:02:15.619418 ==
4263 10:02:15.623063 Dram Type= 6, Freq= 0, CH_0, rank 1
4264 10:02:15.626174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4265 10:02:15.626306 ==
4266 10:02:15.626378
4267 10:02:15.626442
4268 10:02:15.629209 TX Vref Scan disable
4269 10:02:15.632503 == TX Byte 0 ==
4270 10:02:15.636024 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4271 10:02:15.642899 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4272 10:02:15.643066 == TX Byte 1 ==
4273 10:02:15.646109 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4274 10:02:15.652587 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4275 10:02:15.652673
4276 10:02:15.652740 [DATLAT]
4277 10:02:15.652802 Freq=600, CH0 RK1
4278 10:02:15.652862
4279 10:02:15.656105 DATLAT Default: 0x9
4280 10:02:15.656191 0, 0xFFFF, sum = 0
4281 10:02:15.659541 1, 0xFFFF, sum = 0
4282 10:02:15.659627 2, 0xFFFF, sum = 0
4283 10:02:15.662685 3, 0xFFFF, sum = 0
4284 10:02:15.665967 4, 0xFFFF, sum = 0
4285 10:02:15.666055 5, 0xFFFF, sum = 0
4286 10:02:15.669243 6, 0xFFFF, sum = 0
4287 10:02:15.669363 7, 0xFFFF, sum = 0
4288 10:02:15.672797 8, 0x0, sum = 1
4289 10:02:15.672910 9, 0x0, sum = 2
4290 10:02:15.673007 10, 0x0, sum = 3
4291 10:02:15.675785 11, 0x0, sum = 4
4292 10:02:15.675894 best_step = 9
4293 10:02:15.675991
4294 10:02:15.676098 ==
4295 10:02:15.679209 Dram Type= 6, Freq= 0, CH_0, rank 1
4296 10:02:15.685583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4297 10:02:15.685697 ==
4298 10:02:15.685799 RX Vref Scan: 0
4299 10:02:15.685890
4300 10:02:15.689247 RX Vref 0 -> 0, step: 1
4301 10:02:15.689335
4302 10:02:15.692962 RX Delay -163 -> 252, step: 8
4303 10:02:15.695884 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4304 10:02:15.702873 iDelay=205, Bit 1, Center 56 (-83 ~ 196) 280
4305 10:02:15.706027 iDelay=205, Bit 2, Center 52 (-91 ~ 196) 288
4306 10:02:15.709087 iDelay=205, Bit 3, Center 52 (-91 ~ 196) 288
4307 10:02:15.712647 iDelay=205, Bit 4, Center 56 (-83 ~ 196) 280
4308 10:02:15.715628 iDelay=205, Bit 5, Center 48 (-91 ~ 188) 280
4309 10:02:15.719430 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4310 10:02:15.726241 iDelay=205, Bit 7, Center 60 (-83 ~ 204) 288
4311 10:02:15.729321 iDelay=205, Bit 8, Center 36 (-107 ~ 180) 288
4312 10:02:15.732390 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4313 10:02:15.735703 iDelay=205, Bit 10, Center 48 (-91 ~ 188) 280
4314 10:02:15.742477 iDelay=205, Bit 11, Center 40 (-99 ~ 180) 280
4315 10:02:15.746126 iDelay=205, Bit 12, Center 52 (-83 ~ 188) 272
4316 10:02:15.749380 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4317 10:02:15.752719 iDelay=205, Bit 14, Center 56 (-83 ~ 196) 280
4318 10:02:15.755839 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4319 10:02:15.758906 ==
4320 10:02:15.759021 Dram Type= 6, Freq= 0, CH_0, rank 1
4321 10:02:15.765699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4322 10:02:15.765788 ==
4323 10:02:15.765868 DQS Delay:
4324 10:02:15.769403 DQS0 = 0, DQS1 = 0
4325 10:02:15.769508 DQM Delay:
4326 10:02:15.769634 DQM0 = 54, DQM1 = 46
4327 10:02:15.772731 DQ Delay:
4328 10:02:15.775976 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4329 10:02:15.778899 DQ4 =56, DQ5 =48, DQ6 =56, DQ7 =60
4330 10:02:15.782509 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4331 10:02:15.785969 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4332 10:02:15.786055
4333 10:02:15.786123
4334 10:02:15.792232 [DQSOSCAuto] RK1, (LSB)MR18= 0x6526, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 390 ps
4335 10:02:15.795589 CH0 RK1: MR19=808, MR18=6526
4336 10:02:15.802409 CH0_RK1: MR19=0x808, MR18=0x6526, DQSOSC=390, MR23=63, INC=172, DEC=114
4337 10:02:15.805816 [RxdqsGatingPostProcess] freq 600
4338 10:02:15.809280 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4339 10:02:15.812252 Pre-setting of DQS Precalculation
4340 10:02:15.819088 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4341 10:02:15.819185 ==
4342 10:02:15.822786 Dram Type= 6, Freq= 0, CH_1, rank 0
4343 10:02:15.825637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4344 10:02:15.825722 ==
4345 10:02:15.832739 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4346 10:02:15.838776 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4347 10:02:15.841974 [CA 0] Center 36 (5~67) winsize 63
4348 10:02:15.845819 [CA 1] Center 36 (5~67) winsize 63
4349 10:02:15.848978 [CA 2] Center 35 (4~66) winsize 63
4350 10:02:15.852042 [CA 3] Center 34 (4~65) winsize 62
4351 10:02:15.855728 [CA 4] Center 34 (4~65) winsize 62
4352 10:02:15.858912 [CA 5] Center 34 (3~65) winsize 63
4353 10:02:15.858997
4354 10:02:15.862056 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4355 10:02:15.862140
4356 10:02:15.865153 [CATrainingPosCal] consider 1 rank data
4357 10:02:15.868964 u2DelayCellTimex100 = 270/100 ps
4358 10:02:15.872188 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4359 10:02:15.875626 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4360 10:02:15.878785 CA2 delay=35 (4~66),Diff = 1 PI (9 cell)
4361 10:02:15.881864 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4362 10:02:15.885366 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4363 10:02:15.888406 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4364 10:02:15.888491
4365 10:02:15.895165 CA PerBit enable=1, Macro0, CA PI delay=34
4366 10:02:15.895289
4367 10:02:15.895368 [CBTSetCACLKResult] CA Dly = 34
4368 10:02:15.898515 CS Dly: 5 (0~36)
4369 10:02:15.898599 ==
4370 10:02:15.901905 Dram Type= 6, Freq= 0, CH_1, rank 1
4371 10:02:15.905443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4372 10:02:15.905537 ==
4373 10:02:15.912309 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4374 10:02:15.918244 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4375 10:02:15.922068 [CA 0] Center 36 (5~67) winsize 63
4376 10:02:15.924923 [CA 1] Center 36 (5~67) winsize 63
4377 10:02:15.928657 [CA 2] Center 34 (4~65) winsize 62
4378 10:02:15.931660 [CA 3] Center 34 (4~65) winsize 62
4379 10:02:15.935050 [CA 4] Center 35 (4~66) winsize 63
4380 10:02:15.938422 [CA 5] Center 34 (3~65) winsize 63
4381 10:02:15.938509
4382 10:02:15.941648 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4383 10:02:15.941734
4384 10:02:15.945337 [CATrainingPosCal] consider 2 rank data
4385 10:02:15.948588 u2DelayCellTimex100 = 270/100 ps
4386 10:02:15.951726 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4387 10:02:15.955540 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4388 10:02:15.958608 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4389 10:02:15.961825 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4390 10:02:15.964985 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4391 10:02:15.968797 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4392 10:02:15.968883
4393 10:02:15.975093 CA PerBit enable=1, Macro0, CA PI delay=34
4394 10:02:15.975182
4395 10:02:15.978153 [CBTSetCACLKResult] CA Dly = 34
4396 10:02:15.978239 CS Dly: 6 (0~38)
4397 10:02:15.978306
4398 10:02:15.981910 ----->DramcWriteLeveling(PI) begin...
4399 10:02:15.981997 ==
4400 10:02:15.984866 Dram Type= 6, Freq= 0, CH_1, rank 0
4401 10:02:15.988119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4402 10:02:15.988204 ==
4403 10:02:15.991524 Write leveling (Byte 0): 29 => 29
4404 10:02:15.995328 Write leveling (Byte 1): 29 => 29
4405 10:02:15.998513 DramcWriteLeveling(PI) end<-----
4406 10:02:15.998599
4407 10:02:15.998665 ==
4408 10:02:16.001669 Dram Type= 6, Freq= 0, CH_1, rank 0
4409 10:02:16.008302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4410 10:02:16.008390 ==
4411 10:02:16.008458 [Gating] SW mode calibration
4412 10:02:16.018109 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4413 10:02:16.021799 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4414 10:02:16.024879 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4415 10:02:16.031670 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4416 10:02:16.035150 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4417 10:02:16.038385 0 9 12 | B1->B0 | 3030 2f2f | 1 0 | (1 0) (0 0)
4418 10:02:16.044916 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4419 10:02:16.048309 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4420 10:02:16.051388 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4421 10:02:16.057820 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4422 10:02:16.061451 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4423 10:02:16.064704 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4424 10:02:16.071484 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4425 10:02:16.074648 0 10 12 | B1->B0 | 3030 3737 | 0 0 | (0 0) (0 0)
4426 10:02:16.077836 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4427 10:02:16.084714 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4428 10:02:16.087770 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4429 10:02:16.091033 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4430 10:02:16.098082 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4431 10:02:16.101177 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4432 10:02:16.104435 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4433 10:02:16.111403 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4434 10:02:16.114376 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4435 10:02:16.117927 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 10:02:16.124152 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 10:02:16.127589 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 10:02:16.130763 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 10:02:16.138038 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 10:02:16.141058 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 10:02:16.144236 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 10:02:16.147802 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 10:02:16.154529 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 10:02:16.158021 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 10:02:16.161197 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 10:02:16.167851 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 10:02:16.171227 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 10:02:16.174629 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 10:02:16.180889 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4450 10:02:16.184774 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4451 10:02:16.187852 Total UI for P1: 0, mck2ui 16
4452 10:02:16.190995 best dqsien dly found for B0: ( 0, 13, 12)
4453 10:02:16.194014 Total UI for P1: 0, mck2ui 16
4454 10:02:16.197788 best dqsien dly found for B1: ( 0, 13, 12)
4455 10:02:16.200966 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4456 10:02:16.204060 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4457 10:02:16.204153
4458 10:02:16.207388 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4459 10:02:16.211136 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4460 10:02:16.214334 [Gating] SW calibration Done
4461 10:02:16.214420 ==
4462 10:02:16.217355 Dram Type= 6, Freq= 0, CH_1, rank 0
4463 10:02:16.224139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4464 10:02:16.224252 ==
4465 10:02:16.224357 RX Vref Scan: 0
4466 10:02:16.224449
4467 10:02:16.227280 RX Vref 0 -> 0, step: 1
4468 10:02:16.227357
4469 10:02:16.230820 RX Delay -230 -> 252, step: 16
4470 10:02:16.233959 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4471 10:02:16.237546 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4472 10:02:16.240433 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4473 10:02:16.247087 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4474 10:02:16.250666 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4475 10:02:16.254176 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4476 10:02:16.257025 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4477 10:02:16.263888 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4478 10:02:16.267047 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4479 10:02:16.270572 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4480 10:02:16.273976 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4481 10:02:16.276912 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4482 10:02:16.283690 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4483 10:02:16.286883 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4484 10:02:16.290434 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4485 10:02:16.293797 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4486 10:02:16.296955 ==
4487 10:02:16.300248 Dram Type= 6, Freq= 0, CH_1, rank 0
4488 10:02:16.304081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4489 10:02:16.304198 ==
4490 10:02:16.304306 DQS Delay:
4491 10:02:16.306971 DQS0 = 0, DQS1 = 0
4492 10:02:16.307088 DQM Delay:
4493 10:02:16.310361 DQM0 = 49, DQM1 = 46
4494 10:02:16.310444 DQ Delay:
4495 10:02:16.314097 DQ0 =49, DQ1 =41, DQ2 =41, DQ3 =49
4496 10:02:16.317063 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4497 10:02:16.320349 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4498 10:02:16.323942 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4499 10:02:16.324057
4500 10:02:16.324157
4501 10:02:16.324228 ==
4502 10:02:16.327106 Dram Type= 6, Freq= 0, CH_1, rank 0
4503 10:02:16.330378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4504 10:02:16.330462 ==
4505 10:02:16.330526
4506 10:02:16.330607
4507 10:02:16.333526 TX Vref Scan disable
4508 10:02:16.337189 == TX Byte 0 ==
4509 10:02:16.340568 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4510 10:02:16.343492 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4511 10:02:16.347740 == TX Byte 1 ==
4512 10:02:16.350201 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4513 10:02:16.353540 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4514 10:02:16.353706 ==
4515 10:02:16.356660 Dram Type= 6, Freq= 0, CH_1, rank 0
4516 10:02:16.360068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4517 10:02:16.363275 ==
4518 10:02:16.363382
4519 10:02:16.363450
4520 10:02:16.363512 TX Vref Scan disable
4521 10:02:16.367306 == TX Byte 0 ==
4522 10:02:16.370559 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4523 10:02:16.377294 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4524 10:02:16.377434 == TX Byte 1 ==
4525 10:02:16.380479 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4526 10:02:16.387185 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4527 10:02:16.387301
4528 10:02:16.387373 [DATLAT]
4529 10:02:16.387437 Freq=600, CH1 RK0
4530 10:02:16.387527
4531 10:02:16.390217 DATLAT Default: 0x9
4532 10:02:16.390311 0, 0xFFFF, sum = 0
4533 10:02:16.393805 1, 0xFFFF, sum = 0
4534 10:02:16.396881 2, 0xFFFF, sum = 0
4535 10:02:16.396986 3, 0xFFFF, sum = 0
4536 10:02:16.400255 4, 0xFFFF, sum = 0
4537 10:02:16.400355 5, 0xFFFF, sum = 0
4538 10:02:16.403451 6, 0xFFFF, sum = 0
4539 10:02:16.403540 7, 0xFFFF, sum = 0
4540 10:02:16.407234 8, 0x0, sum = 1
4541 10:02:16.407328 9, 0x0, sum = 2
4542 10:02:16.407396 10, 0x0, sum = 3
4543 10:02:16.410408 11, 0x0, sum = 4
4544 10:02:16.410554 best_step = 9
4545 10:02:16.410659
4546 10:02:16.410766 ==
4547 10:02:16.413610 Dram Type= 6, Freq= 0, CH_1, rank 0
4548 10:02:16.420564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4549 10:02:16.420690 ==
4550 10:02:16.420762 RX Vref Scan: 1
4551 10:02:16.420841
4552 10:02:16.423844 RX Vref 0 -> 0, step: 1
4553 10:02:16.423964
4554 10:02:16.427077 RX Delay -163 -> 252, step: 8
4555 10:02:16.427199
4556 10:02:16.430036 Set Vref, RX VrefLevel [Byte0]: 54
4557 10:02:16.433874 [Byte1]: 48
4558 10:02:16.433984
4559 10:02:16.436945 Final RX Vref Byte 0 = 54 to rank0
4560 10:02:16.440132 Final RX Vref Byte 1 = 48 to rank0
4561 10:02:16.443943 Final RX Vref Byte 0 = 54 to rank1
4562 10:02:16.446820 Final RX Vref Byte 1 = 48 to rank1==
4563 10:02:16.450389 Dram Type= 6, Freq= 0, CH_1, rank 0
4564 10:02:16.453349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4565 10:02:16.453457 ==
4566 10:02:16.457069 DQS Delay:
4567 10:02:16.457179 DQS0 = 0, DQS1 = 0
4568 10:02:16.459916 DQM Delay:
4569 10:02:16.460023 DQM0 = 48, DQM1 = 46
4570 10:02:16.460123 DQ Delay:
4571 10:02:16.463585 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4572 10:02:16.466706 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4573 10:02:16.470268 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =40
4574 10:02:16.473240 DQ12 =56, DQ13 =52, DQ14 =52, DQ15 =56
4575 10:02:16.473358
4576 10:02:16.473471
4577 10:02:16.483509 [DQSOSCAuto] RK0, (LSB)MR18= 0x476d, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4578 10:02:16.486488 CH1 RK0: MR19=808, MR18=476D
4579 10:02:16.493354 CH1_RK0: MR19=0x808, MR18=0x476D, DQSOSC=389, MR23=63, INC=173, DEC=115
4580 10:02:16.493485
4581 10:02:16.496752 ----->DramcWriteLeveling(PI) begin...
4582 10:02:16.496862 ==
4583 10:02:16.499913 Dram Type= 6, Freq= 0, CH_1, rank 1
4584 10:02:16.503602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4585 10:02:16.503733 ==
4586 10:02:16.506723 Write leveling (Byte 0): 27 => 27
4587 10:02:16.509919 Write leveling (Byte 1): 32 => 32
4588 10:02:16.513107 DramcWriteLeveling(PI) end<-----
4589 10:02:16.513219
4590 10:02:16.513301 ==
4591 10:02:16.516627 Dram Type= 6, Freq= 0, CH_1, rank 1
4592 10:02:16.520133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4593 10:02:16.520228 ==
4594 10:02:16.523262 [Gating] SW mode calibration
4595 10:02:16.529668 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4596 10:02:16.536220 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4597 10:02:16.539696 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4598 10:02:16.543191 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4599 10:02:16.549602 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4600 10:02:16.553153 0 9 12 | B1->B0 | 3030 3131 | 0 0 | (0 0) (0 0)
4601 10:02:16.556514 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4602 10:02:16.562951 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4603 10:02:16.566491 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4604 10:02:16.569439 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4605 10:02:16.576346 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4606 10:02:16.579322 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4607 10:02:16.582952 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4608 10:02:16.586264 0 10 12 | B1->B0 | 3737 3131 | 0 0 | (0 0) (0 0)
4609 10:02:16.593096 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4610 10:02:16.596575 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4611 10:02:16.599600 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4612 10:02:16.606611 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4613 10:02:16.609550 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4614 10:02:16.612813 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4615 10:02:16.619794 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4616 10:02:16.622927 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4617 10:02:16.626002 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4618 10:02:16.632908 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 10:02:16.636514 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 10:02:16.639752 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 10:02:16.646350 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 10:02:16.649658 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 10:02:16.653374 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 10:02:16.659534 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 10:02:16.663307 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 10:02:16.666442 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 10:02:16.672945 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 10:02:16.676338 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 10:02:16.679889 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 10:02:16.686157 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 10:02:16.689237 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 10:02:16.692950 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4633 10:02:16.695972 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4634 10:02:16.699379 Total UI for P1: 0, mck2ui 16
4635 10:02:16.702917 best dqsien dly found for B0: ( 0, 13, 12)
4636 10:02:16.706344 Total UI for P1: 0, mck2ui 16
4637 10:02:16.709508 best dqsien dly found for B1: ( 0, 13, 12)
4638 10:02:16.712693 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4639 10:02:16.719729 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4640 10:02:16.719830
4641 10:02:16.722901 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4642 10:02:16.726062 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4643 10:02:16.729146 [Gating] SW calibration Done
4644 10:02:16.729228 ==
4645 10:02:16.732861 Dram Type= 6, Freq= 0, CH_1, rank 1
4646 10:02:16.736101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4647 10:02:16.736234 ==
4648 10:02:16.739274 RX Vref Scan: 0
4649 10:02:16.739384
4650 10:02:16.739453 RX Vref 0 -> 0, step: 1
4651 10:02:16.739515
4652 10:02:16.742408 RX Delay -230 -> 252, step: 16
4653 10:02:16.745897 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4654 10:02:16.752230 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4655 10:02:16.755705 iDelay=218, Bit 2, Center 41 (-102 ~ 185) 288
4656 10:02:16.759254 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4657 10:02:16.762200 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4658 10:02:16.768973 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4659 10:02:16.772059 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4660 10:02:16.775734 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4661 10:02:16.778736 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4662 10:02:16.782482 iDelay=218, Bit 9, Center 41 (-102 ~ 185) 288
4663 10:02:16.788839 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4664 10:02:16.791995 iDelay=218, Bit 11, Center 49 (-102 ~ 201) 304
4665 10:02:16.795247 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4666 10:02:16.798859 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4667 10:02:16.805631 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4668 10:02:16.808811 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4669 10:02:16.808904 ==
4670 10:02:16.812078 Dram Type= 6, Freq= 0, CH_1, rank 1
4671 10:02:16.815861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4672 10:02:16.815950 ==
4673 10:02:16.818934 DQS Delay:
4674 10:02:16.819010 DQS0 = 0, DQS1 = 0
4675 10:02:16.819078 DQM Delay:
4676 10:02:16.821977 DQM0 = 51, DQM1 = 49
4677 10:02:16.822057 DQ Delay:
4678 10:02:16.825646 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =49
4679 10:02:16.828755 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4680 10:02:16.831987 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =49
4681 10:02:16.835161 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4682 10:02:16.835255
4683 10:02:16.835320
4684 10:02:16.835381 ==
4685 10:02:16.838821 Dram Type= 6, Freq= 0, CH_1, rank 1
4686 10:02:16.845382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4687 10:02:16.845503 ==
4688 10:02:16.845626
4689 10:02:16.845702
4690 10:02:16.845763 TX Vref Scan disable
4691 10:02:16.849008 == TX Byte 0 ==
4692 10:02:16.852125 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4693 10:02:16.858620 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4694 10:02:16.858706 == TX Byte 1 ==
4695 10:02:16.862377 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4696 10:02:16.868635 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4697 10:02:16.868718 ==
4698 10:02:16.872423 Dram Type= 6, Freq= 0, CH_1, rank 1
4699 10:02:16.875751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4700 10:02:16.875839 ==
4701 10:02:16.875906
4702 10:02:16.875968
4703 10:02:16.878640 TX Vref Scan disable
4704 10:02:16.881904 == TX Byte 0 ==
4705 10:02:16.885488 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4706 10:02:16.889032 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4707 10:02:16.892122 == TX Byte 1 ==
4708 10:02:16.895334 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4709 10:02:16.898612 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4710 10:02:16.898692
4711 10:02:16.898758 [DATLAT]
4712 10:02:16.901962 Freq=600, CH1 RK1
4713 10:02:16.902054
4714 10:02:16.905683 DATLAT Default: 0x9
4715 10:02:16.905775 0, 0xFFFF, sum = 0
4716 10:02:16.909016 1, 0xFFFF, sum = 0
4717 10:02:16.909104 2, 0xFFFF, sum = 0
4718 10:02:16.911717 3, 0xFFFF, sum = 0
4719 10:02:16.911807 4, 0xFFFF, sum = 0
4720 10:02:16.915136 5, 0xFFFF, sum = 0
4721 10:02:16.915223 6, 0xFFFF, sum = 0
4722 10:02:16.918549 7, 0xFFFF, sum = 0
4723 10:02:16.918665 8, 0x0, sum = 1
4724 10:02:16.921616 9, 0x0, sum = 2
4725 10:02:16.921703 10, 0x0, sum = 3
4726 10:02:16.925712 11, 0x0, sum = 4
4727 10:02:16.925799 best_step = 9
4728 10:02:16.925866
4729 10:02:16.925928 ==
4730 10:02:16.928646 Dram Type= 6, Freq= 0, CH_1, rank 1
4731 10:02:16.932012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4732 10:02:16.932098 ==
4733 10:02:16.935132 RX Vref Scan: 0
4734 10:02:16.935217
4735 10:02:16.938140 RX Vref 0 -> 0, step: 1
4736 10:02:16.938225
4737 10:02:16.938293 RX Delay -163 -> 252, step: 8
4738 10:02:16.946240 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4739 10:02:16.949493 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4740 10:02:16.952520 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4741 10:02:16.956209 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4742 10:02:16.959386 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4743 10:02:16.966308 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4744 10:02:16.969397 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4745 10:02:16.973348 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4746 10:02:16.976219 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4747 10:02:16.979671 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4748 10:02:16.986543 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4749 10:02:16.989223 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4750 10:02:16.992489 iDelay=205, Bit 12, Center 56 (-91 ~ 204) 296
4751 10:02:16.995838 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4752 10:02:17.003286 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4753 10:02:17.006317 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4754 10:02:17.006407 ==
4755 10:02:17.009378 Dram Type= 6, Freq= 0, CH_1, rank 1
4756 10:02:17.013026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4757 10:02:17.013106 ==
4758 10:02:17.016047 DQS Delay:
4759 10:02:17.016132 DQS0 = 0, DQS1 = 0
4760 10:02:17.016203 DQM Delay:
4761 10:02:17.019126 DQM0 = 49, DQM1 = 46
4762 10:02:17.019208 DQ Delay:
4763 10:02:17.022760 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =44
4764 10:02:17.026198 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =48
4765 10:02:17.029473 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =40
4766 10:02:17.032367 DQ12 =56, DQ13 =52, DQ14 =52, DQ15 =52
4767 10:02:17.032470
4768 10:02:17.032571
4769 10:02:17.042709 [DQSOSCAuto] RK1, (LSB)MR18= 0x6a22, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 389 ps
4770 10:02:17.042830 CH1 RK1: MR19=808, MR18=6A22
4771 10:02:17.049379 CH1_RK1: MR19=0x808, MR18=0x6A22, DQSOSC=389, MR23=63, INC=173, DEC=115
4772 10:02:17.052419 [RxdqsGatingPostProcess] freq 600
4773 10:02:17.059085 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4774 10:02:17.062666 Pre-setting of DQS Precalculation
4775 10:02:17.065974 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4776 10:02:17.072514 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4777 10:02:17.082725 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4778 10:02:17.082814
4779 10:02:17.082882
4780 10:02:17.085925 [Calibration Summary] 1200 Mbps
4781 10:02:17.086010 CH 0, Rank 0
4782 10:02:17.089088 SW Impedance : PASS
4783 10:02:17.089202 DUTY Scan : NO K
4784 10:02:17.092332 ZQ Calibration : PASS
4785 10:02:17.092421 Jitter Meter : NO K
4786 10:02:17.095838 CBT Training : PASS
4787 10:02:17.099084 Write leveling : PASS
4788 10:02:17.099164 RX DQS gating : PASS
4789 10:02:17.102246 RX DQ/DQS(RDDQC) : PASS
4790 10:02:17.105420 TX DQ/DQS : PASS
4791 10:02:17.105506 RX DATLAT : PASS
4792 10:02:17.108962 RX DQ/DQS(Engine): PASS
4793 10:02:17.112327 TX OE : NO K
4794 10:02:17.112419 All Pass.
4795 10:02:17.112486
4796 10:02:17.112548 CH 0, Rank 1
4797 10:02:17.115710 SW Impedance : PASS
4798 10:02:17.118825 DUTY Scan : NO K
4799 10:02:17.118911 ZQ Calibration : PASS
4800 10:02:17.122528 Jitter Meter : NO K
4801 10:02:17.125400 CBT Training : PASS
4802 10:02:17.125513 Write leveling : PASS
4803 10:02:17.129106 RX DQS gating : PASS
4804 10:02:17.132342 RX DQ/DQS(RDDQC) : PASS
4805 10:02:17.132428 TX DQ/DQS : PASS
4806 10:02:17.135346 RX DATLAT : PASS
4807 10:02:17.138956 RX DQ/DQS(Engine): PASS
4808 10:02:17.139043 TX OE : NO K
4809 10:02:17.139110 All Pass.
4810 10:02:17.142031
4811 10:02:17.142117 CH 1, Rank 0
4812 10:02:17.145237 SW Impedance : PASS
4813 10:02:17.145322 DUTY Scan : NO K
4814 10:02:17.148850 ZQ Calibration : PASS
4815 10:02:17.148935 Jitter Meter : NO K
4816 10:02:17.152170 CBT Training : PASS
4817 10:02:17.155169 Write leveling : PASS
4818 10:02:17.155255 RX DQS gating : PASS
4819 10:02:17.158571 RX DQ/DQS(RDDQC) : PASS
4820 10:02:17.161765 TX DQ/DQS : PASS
4821 10:02:17.161851 RX DATLAT : PASS
4822 10:02:17.165498 RX DQ/DQS(Engine): PASS
4823 10:02:17.168834 TX OE : NO K
4824 10:02:17.168922 All Pass.
4825 10:02:17.168990
4826 10:02:17.169052 CH 1, Rank 1
4827 10:02:17.172397 SW Impedance : PASS
4828 10:02:17.175674 DUTY Scan : NO K
4829 10:02:17.175761 ZQ Calibration : PASS
4830 10:02:17.178769 Jitter Meter : NO K
4831 10:02:17.181948 CBT Training : PASS
4832 10:02:17.182034 Write leveling : PASS
4833 10:02:17.185764 RX DQS gating : PASS
4834 10:02:17.188836 RX DQ/DQS(RDDQC) : PASS
4835 10:02:17.188922 TX DQ/DQS : PASS
4836 10:02:17.192055 RX DATLAT : PASS
4837 10:02:17.192144 RX DQ/DQS(Engine): PASS
4838 10:02:17.195309 TX OE : NO K
4839 10:02:17.195395 All Pass.
4840 10:02:17.195463
4841 10:02:17.198699 DramC Write-DBI off
4842 10:02:17.201795 PER_BANK_REFRESH: Hybrid Mode
4843 10:02:17.201884 TX_TRACKING: ON
4844 10:02:17.211938 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4845 10:02:17.215681 [FAST_K] Save calibration result to emmc
4846 10:02:17.218570 dramc_set_vcore_voltage set vcore to 662500
4847 10:02:17.221686 Read voltage for 933, 3
4848 10:02:17.221776 Vio18 = 0
4849 10:02:17.225420 Vcore = 662500
4850 10:02:17.225532 Vdram = 0
4851 10:02:17.225627 Vddq = 0
4852 10:02:17.225692 Vmddr = 0
4853 10:02:17.231894 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4854 10:02:17.235227 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4855 10:02:17.238411 MEM_TYPE=3, freq_sel=17
4856 10:02:17.241964 sv_algorithm_assistance_LP4_1600
4857 10:02:17.245247 ============ PULL DRAM RESETB DOWN ============
4858 10:02:17.251874 ========== PULL DRAM RESETB DOWN end =========
4859 10:02:17.254779 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4860 10:02:17.258501 ===================================
4861 10:02:17.261520 LPDDR4 DRAM CONFIGURATION
4862 10:02:17.265343 ===================================
4863 10:02:17.265430 EX_ROW_EN[0] = 0x0
4864 10:02:17.268292 EX_ROW_EN[1] = 0x0
4865 10:02:17.268406 LP4Y_EN = 0x0
4866 10:02:17.271693 WORK_FSP = 0x0
4867 10:02:17.271779 WL = 0x3
4868 10:02:17.275123 RL = 0x3
4869 10:02:17.275213 BL = 0x2
4870 10:02:17.278373 RPST = 0x0
4871 10:02:17.278458 RD_PRE = 0x0
4872 10:02:17.281501 WR_PRE = 0x1
4873 10:02:17.281617 WR_PST = 0x0
4874 10:02:17.284796 DBI_WR = 0x0
4875 10:02:17.288255 DBI_RD = 0x0
4876 10:02:17.288341 OTF = 0x1
4877 10:02:17.291869 ===================================
4878 10:02:17.295025 ===================================
4879 10:02:17.295112 ANA top config
4880 10:02:17.298360 ===================================
4881 10:02:17.301397 DLL_ASYNC_EN = 0
4882 10:02:17.304934 ALL_SLAVE_EN = 1
4883 10:02:17.308044 NEW_RANK_MODE = 1
4884 10:02:17.311331 DLL_IDLE_MODE = 1
4885 10:02:17.311421 LP45_APHY_COMB_EN = 1
4886 10:02:17.314496 TX_ODT_DIS = 1
4887 10:02:17.318334 NEW_8X_MODE = 1
4888 10:02:17.321476 ===================================
4889 10:02:17.324493 ===================================
4890 10:02:17.328318 data_rate = 1866
4891 10:02:17.331548 CKR = 1
4892 10:02:17.331633 DQ_P2S_RATIO = 8
4893 10:02:17.334603 ===================================
4894 10:02:17.338394 CA_P2S_RATIO = 8
4895 10:02:17.341473 DQ_CA_OPEN = 0
4896 10:02:17.344483 DQ_SEMI_OPEN = 0
4897 10:02:17.348047 CA_SEMI_OPEN = 0
4898 10:02:17.351404 CA_FULL_RATE = 0
4899 10:02:17.351527 DQ_CKDIV4_EN = 1
4900 10:02:17.354418 CA_CKDIV4_EN = 1
4901 10:02:17.357773 CA_PREDIV_EN = 0
4902 10:02:17.360998 PH8_DLY = 0
4903 10:02:17.364840 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4904 10:02:17.367988 DQ_AAMCK_DIV = 4
4905 10:02:17.368075 CA_AAMCK_DIV = 4
4906 10:02:17.371235 CA_ADMCK_DIV = 4
4907 10:02:17.374216 DQ_TRACK_CA_EN = 0
4908 10:02:17.377931 CA_PICK = 933
4909 10:02:17.380884 CA_MCKIO = 933
4910 10:02:17.384646 MCKIO_SEMI = 0
4911 10:02:17.387472 PLL_FREQ = 3732
4912 10:02:17.387560 DQ_UI_PI_RATIO = 32
4913 10:02:17.391064 CA_UI_PI_RATIO = 0
4914 10:02:17.394120 ===================================
4915 10:02:17.397731 ===================================
4916 10:02:17.401301 memory_type:LPDDR4
4917 10:02:17.404736 GP_NUM : 10
4918 10:02:17.404830 SRAM_EN : 1
4919 10:02:17.407661 MD32_EN : 0
4920 10:02:17.410663 ===================================
4921 10:02:17.414410 [ANA_INIT] >>>>>>>>>>>>>>
4922 10:02:17.414497 <<<<<< [CONFIGURE PHASE]: ANA_TX
4923 10:02:17.417648 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4924 10:02:17.420714 ===================================
4925 10:02:17.424108 data_rate = 1866,PCW = 0X8f00
4926 10:02:17.427675 ===================================
4927 10:02:17.430923 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4928 10:02:17.437720 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4929 10:02:17.444050 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4930 10:02:17.447845 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4931 10:02:17.450903 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4932 10:02:17.453877 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4933 10:02:17.457755 [ANA_INIT] flow start
4934 10:02:17.457842 [ANA_INIT] PLL >>>>>>>>
4935 10:02:17.460909 [ANA_INIT] PLL <<<<<<<<
4936 10:02:17.464017 [ANA_INIT] MIDPI >>>>>>>>
4937 10:02:17.464103 [ANA_INIT] MIDPI <<<<<<<<
4938 10:02:17.467632 [ANA_INIT] DLL >>>>>>>>
4939 10:02:17.470568 [ANA_INIT] flow end
4940 10:02:17.473896 ============ LP4 DIFF to SE enter ============
4941 10:02:17.477307 ============ LP4 DIFF to SE exit ============
4942 10:02:17.480569 [ANA_INIT] <<<<<<<<<<<<<
4943 10:02:17.483945 [Flow] Enable top DCM control >>>>>
4944 10:02:17.487184 [Flow] Enable top DCM control <<<<<
4945 10:02:17.490497 Enable DLL master slave shuffle
4946 10:02:17.493737 ==============================================================
4947 10:02:17.497229 Gating Mode config
4948 10:02:17.503821 ==============================================================
4949 10:02:17.503937 Config description:
4950 10:02:17.513791 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4951 10:02:17.520818 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4952 10:02:17.523809 SELPH_MODE 0: By rank 1: By Phase
4953 10:02:17.530606 ==============================================================
4954 10:02:17.533647 GAT_TRACK_EN = 1
4955 10:02:17.536830 RX_GATING_MODE = 2
4956 10:02:17.540521 RX_GATING_TRACK_MODE = 2
4957 10:02:17.543713 SELPH_MODE = 1
4958 10:02:17.546945 PICG_EARLY_EN = 1
4959 10:02:17.549961 VALID_LAT_VALUE = 1
4960 10:02:17.553654 ==============================================================
4961 10:02:17.556699 Enter into Gating configuration >>>>
4962 10:02:17.559890 Exit from Gating configuration <<<<
4963 10:02:17.563622 Enter into DVFS_PRE_config >>>>>
4964 10:02:17.576785 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4965 10:02:17.579848 Exit from DVFS_PRE_config <<<<<
4966 10:02:17.583294 Enter into PICG configuration >>>>
4967 10:02:17.583412 Exit from PICG configuration <<<<
4968 10:02:17.586590 [RX_INPUT] configuration >>>>>
4969 10:02:17.590289 [RX_INPUT] configuration <<<<<
4970 10:02:17.596357 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4971 10:02:17.599815 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4972 10:02:17.606340 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4973 10:02:17.613350 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4974 10:02:17.619568 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4975 10:02:17.625967 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4976 10:02:17.629257 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4977 10:02:17.632528 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4978 10:02:17.639619 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4979 10:02:17.642778 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4980 10:02:17.646097 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4981 10:02:17.649045 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4982 10:02:17.652854 ===================================
4983 10:02:17.655867 LPDDR4 DRAM CONFIGURATION
4984 10:02:17.659116 ===================================
4985 10:02:17.662828 EX_ROW_EN[0] = 0x0
4986 10:02:17.662952 EX_ROW_EN[1] = 0x0
4987 10:02:17.666073 LP4Y_EN = 0x0
4988 10:02:17.666185 WORK_FSP = 0x0
4989 10:02:17.669119 WL = 0x3
4990 10:02:17.669232 RL = 0x3
4991 10:02:17.672207 BL = 0x2
4992 10:02:17.672316 RPST = 0x0
4993 10:02:17.675439 RD_PRE = 0x0
4994 10:02:17.675565 WR_PRE = 0x1
4995 10:02:17.679185 WR_PST = 0x0
4996 10:02:17.682349 DBI_WR = 0x0
4997 10:02:17.682468 DBI_RD = 0x0
4998 10:02:17.685615 OTF = 0x1
4999 10:02:17.688646 ===================================
5000 10:02:17.692209 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5001 10:02:17.695764 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5002 10:02:17.698648 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5003 10:02:17.702149 ===================================
5004 10:02:17.705609 LPDDR4 DRAM CONFIGURATION
5005 10:02:17.708687 ===================================
5006 10:02:17.712080 EX_ROW_EN[0] = 0x10
5007 10:02:17.712221 EX_ROW_EN[1] = 0x0
5008 10:02:17.715209 LP4Y_EN = 0x0
5009 10:02:17.715333 WORK_FSP = 0x0
5010 10:02:17.718839 WL = 0x3
5011 10:02:17.718955 RL = 0x3
5012 10:02:17.721940 BL = 0x2
5013 10:02:17.722032 RPST = 0x0
5014 10:02:17.725683 RD_PRE = 0x0
5015 10:02:17.725770 WR_PRE = 0x1
5016 10:02:17.728705 WR_PST = 0x0
5017 10:02:17.731849 DBI_WR = 0x0
5018 10:02:17.731939 DBI_RD = 0x0
5019 10:02:17.735533 OTF = 0x1
5020 10:02:17.738576 ===================================
5021 10:02:17.741760 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5022 10:02:17.746755 nWR fixed to 30
5023 10:02:17.750558 [ModeRegInit_LP4] CH0 RK0
5024 10:02:17.750674 [ModeRegInit_LP4] CH0 RK1
5025 10:02:17.753525 [ModeRegInit_LP4] CH1 RK0
5026 10:02:17.757158 [ModeRegInit_LP4] CH1 RK1
5027 10:02:17.757277 match AC timing 9
5028 10:02:17.763962 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5029 10:02:17.766853 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5030 10:02:17.770127 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5031 10:02:17.776764 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5032 10:02:17.779978 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5033 10:02:17.780097 ==
5034 10:02:17.783784 Dram Type= 6, Freq= 0, CH_0, rank 0
5035 10:02:17.786956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5036 10:02:17.787049 ==
5037 10:02:17.793554 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5038 10:02:17.800207 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5039 10:02:17.803883 [CA 0] Center 37 (6~68) winsize 63
5040 10:02:17.807077 [CA 1] Center 37 (7~68) winsize 62
5041 10:02:17.810710 [CA 2] Center 34 (4~65) winsize 62
5042 10:02:17.813686 [CA 3] Center 33 (3~64) winsize 62
5043 10:02:17.816888 [CA 4] Center 33 (3~64) winsize 62
5044 10:02:17.820178 [CA 5] Center 32 (2~62) winsize 61
5045 10:02:17.820296
5046 10:02:17.823884 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5047 10:02:17.824003
5048 10:02:17.827056 [CATrainingPosCal] consider 1 rank data
5049 10:02:17.830044 u2DelayCellTimex100 = 270/100 ps
5050 10:02:17.833848 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5051 10:02:17.836700 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5052 10:02:17.840263 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5053 10:02:17.843637 CA3 delay=33 (3~64),Diff = 1 PI (6 cell)
5054 10:02:17.846694 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5055 10:02:17.850376 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5056 10:02:17.853460
5057 10:02:17.856484 CA PerBit enable=1, Macro0, CA PI delay=32
5058 10:02:17.856624
5059 10:02:17.859840 [CBTSetCACLKResult] CA Dly = 32
5060 10:02:17.859994 CS Dly: 5 (0~36)
5061 10:02:17.860094 ==
5062 10:02:17.863078 Dram Type= 6, Freq= 0, CH_0, rank 1
5063 10:02:17.866587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5064 10:02:17.866712 ==
5065 10:02:17.873287 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5066 10:02:17.879706 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5067 10:02:17.883455 [CA 0] Center 37 (7~68) winsize 62
5068 10:02:17.886460 [CA 1] Center 37 (7~68) winsize 62
5069 10:02:17.889716 [CA 2] Center 34 (4~65) winsize 62
5070 10:02:17.892815 [CA 3] Center 34 (4~65) winsize 62
5071 10:02:17.896462 [CA 4] Center 32 (2~63) winsize 62
5072 10:02:17.899734 [CA 5] Center 32 (2~62) winsize 61
5073 10:02:17.899874
5074 10:02:17.902751 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5075 10:02:17.902888
5076 10:02:17.905952 [CATrainingPosCal] consider 2 rank data
5077 10:02:17.909601 u2DelayCellTimex100 = 270/100 ps
5078 10:02:17.912711 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5079 10:02:17.916034 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5080 10:02:17.919140 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5081 10:02:17.923098 CA3 delay=34 (4~64),Diff = 2 PI (12 cell)
5082 10:02:17.929238 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5083 10:02:17.932764 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5084 10:02:17.932913
5085 10:02:17.958621 CA PerBit enable=1, Macro0, CA PI delay=32
5086 10:02:17.958825
5087 10:02:17.958943 [CBTSetCACLKResult] CA Dly = 32
5088 10:02:17.959047 CS Dly: 5 (0~37)
5089 10:02:17.959157
5090 10:02:17.959262 ----->DramcWriteLeveling(PI) begin...
5091 10:02:17.959365 ==
5092 10:02:17.959470 Dram Type= 6, Freq= 0, CH_0, rank 0
5093 10:02:17.959568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5094 10:02:17.959672 ==
5095 10:02:17.959769 Write leveling (Byte 0): 31 => 31
5096 10:02:17.960077 Write leveling (Byte 1): 30 => 30
5097 10:02:17.960189 DramcWriteLeveling(PI) end<-----
5098 10:02:17.960289
5099 10:02:17.962932 ==
5100 10:02:17.965977 Dram Type= 6, Freq= 0, CH_0, rank 0
5101 10:02:17.969605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5102 10:02:17.969767 ==
5103 10:02:17.972674 [Gating] SW mode calibration
5104 10:02:17.979228 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5105 10:02:17.982644 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5106 10:02:17.988968 0 14 0 | B1->B0 | 2a2a 3434 | 1 1 | (1 1) (1 1)
5107 10:02:17.992536 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5108 10:02:17.995663 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5109 10:02:18.002371 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5110 10:02:18.005529 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5111 10:02:18.009321 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5112 10:02:18.016055 0 14 24 | B1->B0 | 3434 3131 | 1 0 | (1 1) (1 0)
5113 10:02:18.019060 0 14 28 | B1->B0 | 3434 2525 | 1 0 | (1 1) (1 0)
5114 10:02:18.022453 0 15 0 | B1->B0 | 3030 2323 | 1 0 | (1 1) (0 0)
5115 10:02:18.028849 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5116 10:02:18.032624 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5117 10:02:18.035685 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5118 10:02:18.042375 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5119 10:02:18.045796 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5120 10:02:18.049022 0 15 24 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
5121 10:02:18.055811 0 15 28 | B1->B0 | 2424 3c3c | 0 0 | (0 0) (0 0)
5122 10:02:18.059166 1 0 0 | B1->B0 | 3d3d 4646 | 0 0 | (1 1) (0 0)
5123 10:02:18.062388 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5124 10:02:18.065654 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5125 10:02:18.072408 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5126 10:02:18.075504 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5127 10:02:18.078864 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5128 10:02:18.085845 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5129 10:02:18.088875 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5130 10:02:18.092532 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5131 10:02:18.099175 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 10:02:18.102277 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 10:02:18.105675 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 10:02:18.112112 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 10:02:18.115643 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 10:02:18.118730 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 10:02:18.125589 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 10:02:18.128715 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 10:02:18.132633 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 10:02:18.138884 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 10:02:18.142108 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 10:02:18.145279 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 10:02:18.152230 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 10:02:18.155483 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 10:02:18.158590 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5146 10:02:18.165736 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5147 10:02:18.165897 Total UI for P1: 0, mck2ui 16
5148 10:02:18.168800 best dqsien dly found for B0: ( 1, 2, 28)
5149 10:02:18.175476 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5150 10:02:18.178787 Total UI for P1: 0, mck2ui 16
5151 10:02:18.181923 best dqsien dly found for B1: ( 1, 3, 0)
5152 10:02:18.185486 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5153 10:02:18.188539 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5154 10:02:18.188708
5155 10:02:18.192056 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5156 10:02:18.195327 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5157 10:02:18.198661 [Gating] SW calibration Done
5158 10:02:18.198805 ==
5159 10:02:18.202196 Dram Type= 6, Freq= 0, CH_0, rank 0
5160 10:02:18.205438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5161 10:02:18.205588 ==
5162 10:02:18.208696 RX Vref Scan: 0
5163 10:02:18.208811
5164 10:02:18.208906 RX Vref 0 -> 0, step: 1
5165 10:02:18.212356
5166 10:02:18.212492 RX Delay -80 -> 252, step: 8
5167 10:02:18.218890 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5168 10:02:18.222308 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5169 10:02:18.225573 iDelay=208, Bit 2, Center 103 (16 ~ 191) 176
5170 10:02:18.229035 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5171 10:02:18.232218 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5172 10:02:18.235594 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5173 10:02:18.242486 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5174 10:02:18.245655 iDelay=208, Bit 7, Center 111 (24 ~ 199) 176
5175 10:02:18.248683 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5176 10:02:18.252447 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5177 10:02:18.255522 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5178 10:02:18.258530 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5179 10:02:18.265280 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5180 10:02:18.268435 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5181 10:02:18.272218 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5182 10:02:18.275262 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5183 10:02:18.275388 ==
5184 10:02:18.278450 Dram Type= 6, Freq= 0, CH_0, rank 0
5185 10:02:18.282137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5186 10:02:18.285183 ==
5187 10:02:18.285292 DQS Delay:
5188 10:02:18.285396 DQS0 = 0, DQS1 = 0
5189 10:02:18.288611 DQM Delay:
5190 10:02:18.288707 DQM0 = 104, DQM1 = 94
5191 10:02:18.292134 DQ Delay:
5192 10:02:18.295054 DQ0 =107, DQ1 =107, DQ2 =103, DQ3 =99
5193 10:02:18.298434 DQ4 =107, DQ5 =91, DQ6 =111, DQ7 =111
5194 10:02:18.301779 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =91
5195 10:02:18.305016 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5196 10:02:18.305132
5197 10:02:18.305232
5198 10:02:18.305333 ==
5199 10:02:18.308256 Dram Type= 6, Freq= 0, CH_0, rank 0
5200 10:02:18.311621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5201 10:02:18.311765 ==
5202 10:02:18.311868
5203 10:02:18.311978
5204 10:02:18.314844 TX Vref Scan disable
5205 10:02:18.314970 == TX Byte 0 ==
5206 10:02:18.321611 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5207 10:02:18.324752 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5208 10:02:18.324905 == TX Byte 1 ==
5209 10:02:18.331524 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5210 10:02:18.335029 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5211 10:02:18.335139 ==
5212 10:02:18.338226 Dram Type= 6, Freq= 0, CH_0, rank 0
5213 10:02:18.341612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5214 10:02:18.341753 ==
5215 10:02:18.341859
5216 10:02:18.345032
5217 10:02:18.345179 TX Vref Scan disable
5218 10:02:18.348292 == TX Byte 0 ==
5219 10:02:18.351547 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5220 10:02:18.354695 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5221 10:02:18.357909 == TX Byte 1 ==
5222 10:02:18.361180 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5223 10:02:18.368216 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5224 10:02:18.368338
5225 10:02:18.368410 [DATLAT]
5226 10:02:18.368473 Freq=933, CH0 RK0
5227 10:02:18.368535
5228 10:02:18.371285 DATLAT Default: 0xd
5229 10:02:18.371374 0, 0xFFFF, sum = 0
5230 10:02:18.374466 1, 0xFFFF, sum = 0
5231 10:02:18.374555 2, 0xFFFF, sum = 0
5232 10:02:18.378255 3, 0xFFFF, sum = 0
5233 10:02:18.381275 4, 0xFFFF, sum = 0
5234 10:02:18.381366 5, 0xFFFF, sum = 0
5235 10:02:18.384403 6, 0xFFFF, sum = 0
5236 10:02:18.384494 7, 0xFFFF, sum = 0
5237 10:02:18.388148 8, 0xFFFF, sum = 0
5238 10:02:18.388269 9, 0xFFFF, sum = 0
5239 10:02:18.391222 10, 0x0, sum = 1
5240 10:02:18.391350 11, 0x0, sum = 2
5241 10:02:18.391455 12, 0x0, sum = 3
5242 10:02:18.394459 13, 0x0, sum = 4
5243 10:02:18.394576 best_step = 11
5244 10:02:18.394677
5245 10:02:18.398281 ==
5246 10:02:18.398404 Dram Type= 6, Freq= 0, CH_0, rank 0
5247 10:02:18.404630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5248 10:02:18.404752 ==
5249 10:02:18.404835 RX Vref Scan: 1
5250 10:02:18.404910
5251 10:02:18.408083 RX Vref 0 -> 0, step: 1
5252 10:02:18.408190
5253 10:02:18.411270 RX Delay -53 -> 252, step: 4
5254 10:02:18.411380
5255 10:02:18.414326 Set Vref, RX VrefLevel [Byte0]: 56
5256 10:02:18.417924 [Byte1]: 47
5257 10:02:18.418042
5258 10:02:18.420967 Final RX Vref Byte 0 = 56 to rank0
5259 10:02:18.424605 Final RX Vref Byte 1 = 47 to rank0
5260 10:02:18.427388 Final RX Vref Byte 0 = 56 to rank1
5261 10:02:18.430809 Final RX Vref Byte 1 = 47 to rank1==
5262 10:02:18.434134 Dram Type= 6, Freq= 0, CH_0, rank 0
5263 10:02:18.437772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5264 10:02:18.440857 ==
5265 10:02:18.440954 DQS Delay:
5266 10:02:18.441022 DQS0 = 0, DQS1 = 0
5267 10:02:18.444077 DQM Delay:
5268 10:02:18.444186 DQM0 = 104, DQM1 = 94
5269 10:02:18.447322 DQ Delay:
5270 10:02:18.450548 DQ0 =104, DQ1 =106, DQ2 =104, DQ3 =102
5271 10:02:18.454255 DQ4 =104, DQ5 =96, DQ6 =112, DQ7 =110
5272 10:02:18.457585 DQ8 =86, DQ9 =86, DQ10 =96, DQ11 =90
5273 10:02:18.460923 DQ12 =98, DQ13 =98, DQ14 =104, DQ15 =100
5274 10:02:18.461045
5275 10:02:18.461139
5276 10:02:18.467649 [DQSOSCAuto] RK0, (LSB)MR18= 0x332b, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 405 ps
5277 10:02:18.470776 CH0 RK0: MR19=505, MR18=332B
5278 10:02:18.477717 CH0_RK0: MR19=0x505, MR18=0x332B, DQSOSC=405, MR23=63, INC=66, DEC=44
5279 10:02:18.477859
5280 10:02:18.480720 ----->DramcWriteLeveling(PI) begin...
5281 10:02:18.480823 ==
5282 10:02:18.484010 Dram Type= 6, Freq= 0, CH_0, rank 1
5283 10:02:18.487789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5284 10:02:18.487895 ==
5285 10:02:18.490829 Write leveling (Byte 0): 31 => 31
5286 10:02:18.494115 Write leveling (Byte 1): 31 => 31
5287 10:02:18.497120 DramcWriteLeveling(PI) end<-----
5288 10:02:18.497229
5289 10:02:18.497350 ==
5290 10:02:18.500328 Dram Type= 6, Freq= 0, CH_0, rank 1
5291 10:02:18.504339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5292 10:02:18.504508 ==
5293 10:02:18.507387 [Gating] SW mode calibration
5294 10:02:18.513971 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5295 10:02:18.520770 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5296 10:02:18.523847 0 14 0 | B1->B0 | 3232 3232 | 1 0 | (1 1) (0 0)
5297 10:02:18.530841 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5298 10:02:18.533823 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5299 10:02:18.536887 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5300 10:02:18.543831 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5301 10:02:18.546839 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5302 10:02:18.550481 0 14 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (0 1)
5303 10:02:18.556924 0 14 28 | B1->B0 | 2626 2c2c | 0 0 | (0 0) (0 0)
5304 10:02:18.560150 0 15 0 | B1->B0 | 2525 2828 | 0 0 | (0 0) (0 0)
5305 10:02:18.563456 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5306 10:02:18.570760 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5307 10:02:18.573385 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5308 10:02:18.577268 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5309 10:02:18.583240 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5310 10:02:18.587015 0 15 24 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
5311 10:02:18.589985 0 15 28 | B1->B0 | 3e3e 3838 | 0 0 | (1 1) (0 0)
5312 10:02:18.593539 1 0 0 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
5313 10:02:18.600507 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5314 10:02:18.603558 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5315 10:02:18.606632 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5316 10:02:18.613507 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5317 10:02:18.616586 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5318 10:02:18.620074 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5319 10:02:18.626707 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5320 10:02:18.630462 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5321 10:02:18.633511 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 10:02:18.640412 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 10:02:18.643496 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 10:02:18.646562 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 10:02:18.653635 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 10:02:18.656791 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 10:02:18.659833 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 10:02:18.666662 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 10:02:18.670259 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 10:02:18.673486 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 10:02:18.679878 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 10:02:18.683149 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 10:02:18.686866 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 10:02:18.693432 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 10:02:18.696676 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5336 10:02:18.699754 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5337 10:02:18.703205 Total UI for P1: 0, mck2ui 16
5338 10:02:18.706716 best dqsien dly found for B0: ( 1, 2, 28)
5339 10:02:18.709716 Total UI for P1: 0, mck2ui 16
5340 10:02:18.713548 best dqsien dly found for B1: ( 1, 2, 28)
5341 10:02:18.716885 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5342 10:02:18.719935 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5343 10:02:18.720059
5344 10:02:18.723191 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5345 10:02:18.729487 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5346 10:02:18.729633 [Gating] SW calibration Done
5347 10:02:18.729737 ==
5348 10:02:18.733013 Dram Type= 6, Freq= 0, CH_0, rank 1
5349 10:02:18.739825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5350 10:02:18.739956 ==
5351 10:02:18.740056 RX Vref Scan: 0
5352 10:02:18.740149
5353 10:02:18.742736 RX Vref 0 -> 0, step: 1
5354 10:02:18.742857
5355 10:02:18.746451 RX Delay -80 -> 252, step: 8
5356 10:02:18.749636 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5357 10:02:18.753232 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5358 10:02:18.756324 iDelay=208, Bit 2, Center 107 (16 ~ 199) 184
5359 10:02:18.762640 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5360 10:02:18.766550 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5361 10:02:18.769572 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5362 10:02:18.772742 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5363 10:02:18.775879 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5364 10:02:18.782921 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5365 10:02:18.785959 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5366 10:02:18.789318 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5367 10:02:18.792689 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5368 10:02:18.796321 iDelay=208, Bit 12, Center 99 (16 ~ 183) 168
5369 10:02:18.799441 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5370 10:02:18.805691 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5371 10:02:18.809666 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5372 10:02:18.809769 ==
5373 10:02:18.812574 Dram Type= 6, Freq= 0, CH_0, rank 1
5374 10:02:18.815939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5375 10:02:18.816051 ==
5376 10:02:18.816155 DQS Delay:
5377 10:02:18.819347 DQS0 = 0, DQS1 = 0
5378 10:02:18.819426 DQM Delay:
5379 10:02:18.822289 DQM0 = 105, DQM1 = 94
5380 10:02:18.822408 DQ Delay:
5381 10:02:18.826042 DQ0 =107, DQ1 =107, DQ2 =107, DQ3 =103
5382 10:02:18.829467 DQ4 =107, DQ5 =95, DQ6 =107, DQ7 =111
5383 10:02:18.832448 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =87
5384 10:02:18.835536 DQ12 =99, DQ13 =99, DQ14 =103, DQ15 =99
5385 10:02:18.835620
5386 10:02:18.835686
5387 10:02:18.835760 ==
5388 10:02:18.838921 Dram Type= 6, Freq= 0, CH_0, rank 1
5389 10:02:18.845443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5390 10:02:18.845561 ==
5391 10:02:18.845671
5392 10:02:18.845735
5393 10:02:18.849145 TX Vref Scan disable
5394 10:02:18.849262 == TX Byte 0 ==
5395 10:02:18.852257 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5396 10:02:18.858916 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5397 10:02:18.859021 == TX Byte 1 ==
5398 10:02:18.862028 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5399 10:02:18.868896 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5400 10:02:18.869009 ==
5401 10:02:18.872159 Dram Type= 6, Freq= 0, CH_0, rank 1
5402 10:02:18.875267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5403 10:02:18.875346 ==
5404 10:02:18.875411
5405 10:02:18.875479
5406 10:02:18.879067 TX Vref Scan disable
5407 10:02:18.882190 == TX Byte 0 ==
5408 10:02:18.885785 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5409 10:02:18.888987 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5410 10:02:18.892141 == TX Byte 1 ==
5411 10:02:18.895302 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5412 10:02:18.898835 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5413 10:02:18.898920
5414 10:02:18.898985 [DATLAT]
5415 10:02:18.902460 Freq=933, CH0 RK1
5416 10:02:18.902541
5417 10:02:18.905132 DATLAT Default: 0xb
5418 10:02:18.905239 0, 0xFFFF, sum = 0
5419 10:02:18.908930 1, 0xFFFF, sum = 0
5420 10:02:18.909053 2, 0xFFFF, sum = 0
5421 10:02:18.911950 3, 0xFFFF, sum = 0
5422 10:02:18.912068 4, 0xFFFF, sum = 0
5423 10:02:18.915737 5, 0xFFFF, sum = 0
5424 10:02:18.915850 6, 0xFFFF, sum = 0
5425 10:02:18.918910 7, 0xFFFF, sum = 0
5426 10:02:18.919020 8, 0xFFFF, sum = 0
5427 10:02:18.922063 9, 0xFFFF, sum = 0
5428 10:02:18.922181 10, 0x0, sum = 1
5429 10:02:18.925241 11, 0x0, sum = 2
5430 10:02:18.925353 12, 0x0, sum = 3
5431 10:02:18.928837 13, 0x0, sum = 4
5432 10:02:18.928947 best_step = 11
5433 10:02:18.929052
5434 10:02:18.929149 ==
5435 10:02:18.932141 Dram Type= 6, Freq= 0, CH_0, rank 1
5436 10:02:18.935102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5437 10:02:18.935212 ==
5438 10:02:18.938556 RX Vref Scan: 0
5439 10:02:18.938677
5440 10:02:18.941835 RX Vref 0 -> 0, step: 1
5441 10:02:18.941950
5442 10:02:18.942060 RX Delay -45 -> 252, step: 4
5443 10:02:18.949782 iDelay=199, Bit 0, Center 102 (15 ~ 190) 176
5444 10:02:18.953167 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5445 10:02:18.956261 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5446 10:02:18.959877 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5447 10:02:18.963444 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5448 10:02:18.969536 iDelay=199, Bit 5, Center 100 (15 ~ 186) 172
5449 10:02:18.972762 iDelay=199, Bit 6, Center 110 (27 ~ 194) 168
5450 10:02:18.976029 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5451 10:02:18.979920 iDelay=199, Bit 8, Center 82 (-1 ~ 166) 168
5452 10:02:18.982957 iDelay=199, Bit 9, Center 82 (-1 ~ 166) 168
5453 10:02:18.989229 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5454 10:02:18.992968 iDelay=199, Bit 11, Center 88 (7 ~ 170) 164
5455 10:02:18.996081 iDelay=199, Bit 12, Center 100 (19 ~ 182) 164
5456 10:02:18.999846 iDelay=199, Bit 13, Center 98 (15 ~ 182) 168
5457 10:02:19.002925 iDelay=199, Bit 14, Center 102 (19 ~ 186) 168
5458 10:02:19.009641 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5459 10:02:19.009733 ==
5460 10:02:19.013230 Dram Type= 6, Freq= 0, CH_0, rank 1
5461 10:02:19.016041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5462 10:02:19.016158 ==
5463 10:02:19.016271 DQS Delay:
5464 10:02:19.019445 DQS0 = 0, DQS1 = 0
5465 10:02:19.019535 DQM Delay:
5466 10:02:19.022609 DQM0 = 105, DQM1 = 93
5467 10:02:19.022719 DQ Delay:
5468 10:02:19.026482 DQ0 =102, DQ1 =106, DQ2 =102, DQ3 =102
5469 10:02:19.029605 DQ4 =106, DQ5 =100, DQ6 =110, DQ7 =112
5470 10:02:19.032750 DQ8 =82, DQ9 =82, DQ10 =94, DQ11 =88
5471 10:02:19.036391 DQ12 =100, DQ13 =98, DQ14 =102, DQ15 =102
5472 10:02:19.036490
5473 10:02:19.036561
5474 10:02:19.046077 [DQSOSCAuto] RK1, (LSB)MR18= 0x2b04, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 408 ps
5475 10:02:19.049196 CH0 RK1: MR19=505, MR18=2B04
5476 10:02:19.053146 CH0_RK1: MR19=0x505, MR18=0x2B04, DQSOSC=408, MR23=63, INC=65, DEC=43
5477 10:02:19.055879 [RxdqsGatingPostProcess] freq 933
5478 10:02:19.062476 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5479 10:02:19.065936 best DQS0 dly(2T, 0.5T) = (0, 10)
5480 10:02:19.069315 best DQS1 dly(2T, 0.5T) = (0, 11)
5481 10:02:19.072637 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5482 10:02:19.075933 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5483 10:02:19.079444 best DQS0 dly(2T, 0.5T) = (0, 10)
5484 10:02:19.082634 best DQS1 dly(2T, 0.5T) = (0, 10)
5485 10:02:19.085911 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5486 10:02:19.089035 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5487 10:02:19.089153 Pre-setting of DQS Precalculation
5488 10:02:19.095585 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5489 10:02:19.095710 ==
5490 10:02:19.099449 Dram Type= 6, Freq= 0, CH_1, rank 0
5491 10:02:19.102611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5492 10:02:19.102718 ==
5493 10:02:19.108969 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5494 10:02:19.115621 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5495 10:02:19.118985 [CA 0] Center 36 (6~67) winsize 62
5496 10:02:19.122638 [CA 1] Center 36 (6~67) winsize 62
5497 10:02:19.125538 [CA 2] Center 34 (4~65) winsize 62
5498 10:02:19.128990 [CA 3] Center 34 (4~65) winsize 62
5499 10:02:19.132517 [CA 4] Center 34 (4~65) winsize 62
5500 10:02:19.135631 [CA 5] Center 33 (3~64) winsize 62
5501 10:02:19.135745
5502 10:02:19.139279 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5503 10:02:19.139390
5504 10:02:19.142398 [CATrainingPosCal] consider 1 rank data
5505 10:02:19.145458 u2DelayCellTimex100 = 270/100 ps
5506 10:02:19.149095 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5507 10:02:19.152320 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5508 10:02:19.155434 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5509 10:02:19.159126 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5510 10:02:19.162639 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5511 10:02:19.165461 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5512 10:02:19.165590
5513 10:02:19.172695 CA PerBit enable=1, Macro0, CA PI delay=33
5514 10:02:19.172815
5515 10:02:19.175676 [CBTSetCACLKResult] CA Dly = 33
5516 10:02:19.175790 CS Dly: 6 (0~37)
5517 10:02:19.175884 ==
5518 10:02:19.178610 Dram Type= 6, Freq= 0, CH_1, rank 1
5519 10:02:19.182302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5520 10:02:19.182385 ==
5521 10:02:19.188484 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5522 10:02:19.195175 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5523 10:02:19.198993 [CA 0] Center 36 (6~67) winsize 62
5524 10:02:19.201997 [CA 1] Center 37 (7~68) winsize 62
5525 10:02:19.205541 [CA 2] Center 35 (5~65) winsize 61
5526 10:02:19.208682 [CA 3] Center 34 (4~65) winsize 62
5527 10:02:19.211917 [CA 4] Center 34 (4~65) winsize 62
5528 10:02:19.215234 [CA 5] Center 33 (3~64) winsize 62
5529 10:02:19.215327
5530 10:02:19.218544 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5531 10:02:19.218634
5532 10:02:19.222063 [CATrainingPosCal] consider 2 rank data
5533 10:02:19.225162 u2DelayCellTimex100 = 270/100 ps
5534 10:02:19.228455 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5535 10:02:19.232279 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5536 10:02:19.235217 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5537 10:02:19.238832 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5538 10:02:19.241664 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5539 10:02:19.248447 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5540 10:02:19.248586
5541 10:02:19.251844 CA PerBit enable=1, Macro0, CA PI delay=33
5542 10:02:19.251942
5543 10:02:19.254976 [CBTSetCACLKResult] CA Dly = 33
5544 10:02:19.255100 CS Dly: 7 (0~40)
5545 10:02:19.255204
5546 10:02:19.258785 ----->DramcWriteLeveling(PI) begin...
5547 10:02:19.258899 ==
5548 10:02:19.261928 Dram Type= 6, Freq= 0, CH_1, rank 0
5549 10:02:19.268680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5550 10:02:19.268771 ==
5551 10:02:19.271927 Write leveling (Byte 0): 24 => 24
5552 10:02:19.272008 Write leveling (Byte 1): 27 => 27
5553 10:02:19.274848 DramcWriteLeveling(PI) end<-----
5554 10:02:19.274927
5555 10:02:19.274992 ==
5556 10:02:19.278693 Dram Type= 6, Freq= 0, CH_1, rank 0
5557 10:02:19.285532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5558 10:02:19.285643 ==
5559 10:02:19.288744 [Gating] SW mode calibration
5560 10:02:19.295298 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5561 10:02:19.298592 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5562 10:02:19.305372 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5563 10:02:19.308367 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5564 10:02:19.311526 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5565 10:02:19.318229 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5566 10:02:19.322032 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5567 10:02:19.325203 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5568 10:02:19.328554 0 14 24 | B1->B0 | 3232 2e2e | 1 0 | (1 1) (1 0)
5569 10:02:19.334882 0 14 28 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
5570 10:02:19.338482 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5571 10:02:19.341465 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5572 10:02:19.348170 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5573 10:02:19.351841 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5574 10:02:19.354866 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5575 10:02:19.361325 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5576 10:02:19.365052 0 15 24 | B1->B0 | 2323 3333 | 0 1 | (0 0) (0 0)
5577 10:02:19.368093 0 15 28 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5578 10:02:19.375024 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5579 10:02:19.378191 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5580 10:02:19.381972 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5581 10:02:19.388301 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5582 10:02:19.391446 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5583 10:02:19.395176 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5584 10:02:19.401903 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5585 10:02:19.405045 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 10:02:19.408152 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 10:02:19.414960 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 10:02:19.418668 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 10:02:19.421924 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 10:02:19.425119 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 10:02:19.431989 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 10:02:19.435197 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 10:02:19.438357 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 10:02:19.444845 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 10:02:19.448226 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 10:02:19.451747 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 10:02:19.458212 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 10:02:19.461342 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 10:02:19.464884 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 10:02:19.471744 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5601 10:02:19.474649 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5602 10:02:19.478585 Total UI for P1: 0, mck2ui 16
5603 10:02:19.481493 best dqsien dly found for B0: ( 1, 2, 26)
5604 10:02:19.484539 Total UI for P1: 0, mck2ui 16
5605 10:02:19.488029 best dqsien dly found for B1: ( 1, 2, 24)
5606 10:02:19.491296 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5607 10:02:19.494443 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5608 10:02:19.494562
5609 10:02:19.498087 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5610 10:02:19.501160 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5611 10:02:19.504259 [Gating] SW calibration Done
5612 10:02:19.504345 ==
5613 10:02:19.507651 Dram Type= 6, Freq= 0, CH_1, rank 0
5614 10:02:19.514518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5615 10:02:19.514635 ==
5616 10:02:19.514725 RX Vref Scan: 0
5617 10:02:19.514821
5618 10:02:19.517535 RX Vref 0 -> 0, step: 1
5619 10:02:19.517648
5620 10:02:19.521253 RX Delay -80 -> 252, step: 8
5621 10:02:19.524224 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5622 10:02:19.528002 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5623 10:02:19.531173 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5624 10:02:19.534313 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5625 10:02:19.538080 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5626 10:02:19.544333 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5627 10:02:19.548016 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5628 10:02:19.551075 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5629 10:02:19.554253 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5630 10:02:19.557583 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5631 10:02:19.560998 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5632 10:02:19.567845 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5633 10:02:19.570847 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5634 10:02:19.574175 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5635 10:02:19.577845 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5636 10:02:19.584185 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5637 10:02:19.584315 ==
5638 10:02:19.587232 Dram Type= 6, Freq= 0, CH_1, rank 0
5639 10:02:19.591030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5640 10:02:19.591148 ==
5641 10:02:19.591244 DQS Delay:
5642 10:02:19.594212 DQS0 = 0, DQS1 = 0
5643 10:02:19.594291 DQM Delay:
5644 10:02:19.597706 DQM0 = 103, DQM1 = 98
5645 10:02:19.597815 DQ Delay:
5646 10:02:19.600817 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =99
5647 10:02:19.604024 DQ4 =99, DQ5 =115, DQ6 =115, DQ7 =103
5648 10:02:19.607219 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5649 10:02:19.611012 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5650 10:02:19.611142
5651 10:02:19.611234
5652 10:02:19.611302 ==
5653 10:02:19.614166 Dram Type= 6, Freq= 0, CH_1, rank 0
5654 10:02:19.617239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5655 10:02:19.620543 ==
5656 10:02:19.620666
5657 10:02:19.620760
5658 10:02:19.620825 TX Vref Scan disable
5659 10:02:19.623918 == TX Byte 0 ==
5660 10:02:19.627781 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5661 10:02:19.630957 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5662 10:02:19.633882 == TX Byte 1 ==
5663 10:02:19.637150 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5664 10:02:19.640935 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5665 10:02:19.644038 ==
5666 10:02:19.647226 Dram Type= 6, Freq= 0, CH_1, rank 0
5667 10:02:19.650320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5668 10:02:19.650431 ==
5669 10:02:19.650527
5670 10:02:19.650615
5671 10:02:19.654087 TX Vref Scan disable
5672 10:02:19.654171 == TX Byte 0 ==
5673 10:02:19.660404 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5674 10:02:19.664251 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5675 10:02:19.664372 == TX Byte 1 ==
5676 10:02:19.670337 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5677 10:02:19.673834 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5678 10:02:19.673955
5679 10:02:19.674050 [DATLAT]
5680 10:02:19.677025 Freq=933, CH1 RK0
5681 10:02:19.677125
5682 10:02:19.677195 DATLAT Default: 0xd
5683 10:02:19.680571 0, 0xFFFF, sum = 0
5684 10:02:19.680687 1, 0xFFFF, sum = 0
5685 10:02:19.683723 2, 0xFFFF, sum = 0
5686 10:02:19.683810 3, 0xFFFF, sum = 0
5687 10:02:19.687345 4, 0xFFFF, sum = 0
5688 10:02:19.687430 5, 0xFFFF, sum = 0
5689 10:02:19.690387 6, 0xFFFF, sum = 0
5690 10:02:19.690467 7, 0xFFFF, sum = 0
5691 10:02:19.693836 8, 0xFFFF, sum = 0
5692 10:02:19.696842 9, 0xFFFF, sum = 0
5693 10:02:19.696933 10, 0x0, sum = 1
5694 10:02:19.697002 11, 0x0, sum = 2
5695 10:02:19.700625 12, 0x0, sum = 3
5696 10:02:19.700741 13, 0x0, sum = 4
5697 10:02:19.703621 best_step = 11
5698 10:02:19.703730
5699 10:02:19.703823 ==
5700 10:02:19.706836 Dram Type= 6, Freq= 0, CH_1, rank 0
5701 10:02:19.710542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5702 10:02:19.710665 ==
5703 10:02:19.713816 RX Vref Scan: 1
5704 10:02:19.713939
5705 10:02:19.714036 RX Vref 0 -> 0, step: 1
5706 10:02:19.714150
5707 10:02:19.716895 RX Delay -45 -> 252, step: 4
5708 10:02:19.717002
5709 10:02:19.720609 Set Vref, RX VrefLevel [Byte0]: 54
5710 10:02:19.723799 [Byte1]: 48
5711 10:02:19.727542
5712 10:02:19.727647 Final RX Vref Byte 0 = 54 to rank0
5713 10:02:19.730950 Final RX Vref Byte 1 = 48 to rank0
5714 10:02:19.734112 Final RX Vref Byte 0 = 54 to rank1
5715 10:02:19.737712 Final RX Vref Byte 1 = 48 to rank1==
5716 10:02:19.740854 Dram Type= 6, Freq= 0, CH_1, rank 0
5717 10:02:19.747482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5718 10:02:19.747601 ==
5719 10:02:19.747712 DQS Delay:
5720 10:02:19.747808 DQS0 = 0, DQS1 = 0
5721 10:02:19.751110 DQM Delay:
5722 10:02:19.751225 DQM0 = 103, DQM1 = 98
5723 10:02:19.754164 DQ Delay:
5724 10:02:19.757319 DQ0 =106, DQ1 =96, DQ2 =94, DQ3 =98
5725 10:02:19.760607 DQ4 =104, DQ5 =112, DQ6 =110, DQ7 =104
5726 10:02:19.764306 DQ8 =86, DQ9 =90, DQ10 =98, DQ11 =94
5727 10:02:19.767507 DQ12 =106, DQ13 =104, DQ14 =104, DQ15 =108
5728 10:02:19.767615
5729 10:02:19.767720
5730 10:02:19.773891 [DQSOSCAuto] RK0, (LSB)MR18= 0x1830, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 414 ps
5731 10:02:19.777650 CH1 RK0: MR19=505, MR18=1830
5732 10:02:19.784202 CH1_RK0: MR19=0x505, MR18=0x1830, DQSOSC=406, MR23=63, INC=65, DEC=43
5733 10:02:19.784330
5734 10:02:19.787614 ----->DramcWriteLeveling(PI) begin...
5735 10:02:19.787727 ==
5736 10:02:19.790912 Dram Type= 6, Freq= 0, CH_1, rank 1
5737 10:02:19.794456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5738 10:02:19.794575 ==
5739 10:02:19.797531 Write leveling (Byte 0): 25 => 25
5740 10:02:19.800568 Write leveling (Byte 1): 28 => 28
5741 10:02:19.803985 DramcWriteLeveling(PI) end<-----
5742 10:02:19.804118
5743 10:02:19.804217 ==
5744 10:02:19.807614 Dram Type= 6, Freq= 0, CH_1, rank 1
5745 10:02:19.810797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5746 10:02:19.813961 ==
5747 10:02:19.814072 [Gating] SW mode calibration
5748 10:02:19.824058 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5749 10:02:19.827206 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5750 10:02:19.830296 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5751 10:02:19.837206 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5752 10:02:19.840975 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5753 10:02:19.843960 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5754 10:02:19.850500 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5755 10:02:19.853656 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5756 10:02:19.857313 0 14 24 | B1->B0 | 2f2f 3434 | 0 0 | (1 0) (0 0)
5757 10:02:19.863876 0 14 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5758 10:02:19.867001 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5759 10:02:19.870515 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5760 10:02:19.876868 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5761 10:02:19.880233 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5762 10:02:19.883836 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5763 10:02:19.890362 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5764 10:02:19.893347 0 15 24 | B1->B0 | 3030 2a2a | 0 1 | (0 0) (0 0)
5765 10:02:19.896968 0 15 28 | B1->B0 | 4646 4343 | 0 0 | (0 0) (1 1)
5766 10:02:19.903624 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5767 10:02:19.907291 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5768 10:02:19.910359 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5769 10:02:19.917098 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5770 10:02:19.920322 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5771 10:02:19.923578 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5772 10:02:19.930373 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5773 10:02:19.933627 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5774 10:02:19.936685 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 10:02:19.943542 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 10:02:19.946739 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 10:02:19.949811 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 10:02:19.953631 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 10:02:19.959851 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 10:02:19.963574 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 10:02:19.966759 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 10:02:19.973298 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 10:02:19.976690 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 10:02:19.980015 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 10:02:19.986710 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 10:02:19.989809 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 10:02:19.992951 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 10:02:19.999670 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 10:02:20.003603 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5790 10:02:20.006455 Total UI for P1: 0, mck2ui 16
5791 10:02:20.009699 best dqsien dly found for B1: ( 1, 2, 26)
5792 10:02:20.013288 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5793 10:02:20.016670 Total UI for P1: 0, mck2ui 16
5794 10:02:20.019661 best dqsien dly found for B0: ( 1, 2, 28)
5795 10:02:20.023355 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5796 10:02:20.026696 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5797 10:02:20.026795
5798 10:02:20.033161 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5799 10:02:20.036265 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5800 10:02:20.036376 [Gating] SW calibration Done
5801 10:02:20.040104 ==
5802 10:02:20.043393 Dram Type= 6, Freq= 0, CH_1, rank 1
5803 10:02:20.046523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5804 10:02:20.046647 ==
5805 10:02:20.046746 RX Vref Scan: 0
5806 10:02:20.046841
5807 10:02:20.049846 RX Vref 0 -> 0, step: 1
5808 10:02:20.049955
5809 10:02:20.052954 RX Delay -80 -> 252, step: 8
5810 10:02:20.056623 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5811 10:02:20.059889 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5812 10:02:20.062839 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5813 10:02:20.069613 iDelay=208, Bit 3, Center 95 (8 ~ 183) 176
5814 10:02:20.072870 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5815 10:02:20.076755 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5816 10:02:20.079722 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5817 10:02:20.082797 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5818 10:02:20.086259 iDelay=208, Bit 8, Center 91 (0 ~ 183) 184
5819 10:02:20.092675 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5820 10:02:20.096321 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5821 10:02:20.099229 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5822 10:02:20.102750 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5823 10:02:20.106205 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5824 10:02:20.109315 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5825 10:02:20.116065 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5826 10:02:20.116157 ==
5827 10:02:20.119188 Dram Type= 6, Freq= 0, CH_1, rank 1
5828 10:02:20.123055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5829 10:02:20.123140 ==
5830 10:02:20.123204 DQS Delay:
5831 10:02:20.126311 DQS0 = 0, DQS1 = 0
5832 10:02:20.126387 DQM Delay:
5833 10:02:20.129289 DQM0 = 102, DQM1 = 98
5834 10:02:20.129367 DQ Delay:
5835 10:02:20.132914 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =95
5836 10:02:20.135929 DQ4 =95, DQ5 =115, DQ6 =115, DQ7 =99
5837 10:02:20.139428 DQ8 =91, DQ9 =91, DQ10 =99, DQ11 =91
5838 10:02:20.143025 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =107
5839 10:02:20.143124
5840 10:02:20.143197
5841 10:02:20.143258 ==
5842 10:02:20.146107 Dram Type= 6, Freq= 0, CH_1, rank 1
5843 10:02:20.152926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5844 10:02:20.153026 ==
5845 10:02:20.153099
5846 10:02:20.153163
5847 10:02:20.153223 TX Vref Scan disable
5848 10:02:20.156002 == TX Byte 0 ==
5849 10:02:20.159721 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5850 10:02:20.166086 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5851 10:02:20.166169 == TX Byte 1 ==
5852 10:02:20.169163 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5853 10:02:20.175897 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5854 10:02:20.175981 ==
5855 10:02:20.179718 Dram Type= 6, Freq= 0, CH_1, rank 1
5856 10:02:20.182716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5857 10:02:20.182797 ==
5858 10:02:20.182861
5859 10:02:20.182920
5860 10:02:20.185995 TX Vref Scan disable
5861 10:02:20.186066 == TX Byte 0 ==
5862 10:02:20.192714 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5863 10:02:20.196292 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5864 10:02:20.196384 == TX Byte 1 ==
5865 10:02:20.202679 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5866 10:02:20.206270 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5867 10:02:20.206382
5868 10:02:20.206452 [DATLAT]
5869 10:02:20.209212 Freq=933, CH1 RK1
5870 10:02:20.209301
5871 10:02:20.209371 DATLAT Default: 0xb
5872 10:02:20.212570 0, 0xFFFF, sum = 0
5873 10:02:20.212657 1, 0xFFFF, sum = 0
5874 10:02:20.216164 2, 0xFFFF, sum = 0
5875 10:02:20.216257 3, 0xFFFF, sum = 0
5876 10:02:20.219236 4, 0xFFFF, sum = 0
5877 10:02:20.222325 5, 0xFFFF, sum = 0
5878 10:02:20.222417 6, 0xFFFF, sum = 0
5879 10:02:20.226138 7, 0xFFFF, sum = 0
5880 10:02:20.226267 8, 0xFFFF, sum = 0
5881 10:02:20.229281 9, 0xFFFF, sum = 0
5882 10:02:20.229420 10, 0x0, sum = 1
5883 10:02:20.229535 11, 0x0, sum = 2
5884 10:02:20.232544 12, 0x0, sum = 3
5885 10:02:20.232669 13, 0x0, sum = 4
5886 10:02:20.235699 best_step = 11
5887 10:02:20.235824
5888 10:02:20.235933 ==
5889 10:02:20.239262 Dram Type= 6, Freq= 0, CH_1, rank 1
5890 10:02:20.242432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5891 10:02:20.242559 ==
5892 10:02:20.245821 RX Vref Scan: 0
5893 10:02:20.245913
5894 10:02:20.245980 RX Vref 0 -> 0, step: 1
5895 10:02:20.249133
5896 10:02:20.249265 RX Delay -45 -> 252, step: 4
5897 10:02:20.256432 iDelay=203, Bit 0, Center 110 (27 ~ 194) 168
5898 10:02:20.260026 iDelay=203, Bit 1, Center 100 (15 ~ 186) 172
5899 10:02:20.263159 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5900 10:02:20.266408 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5901 10:02:20.269915 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5902 10:02:20.276710 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5903 10:02:20.279756 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5904 10:02:20.283013 iDelay=203, Bit 7, Center 102 (19 ~ 186) 168
5905 10:02:20.286817 iDelay=203, Bit 8, Center 90 (7 ~ 174) 168
5906 10:02:20.289910 iDelay=203, Bit 9, Center 90 (7 ~ 174) 168
5907 10:02:20.296380 iDelay=203, Bit 10, Center 102 (19 ~ 186) 168
5908 10:02:20.299591 iDelay=203, Bit 11, Center 92 (7 ~ 178) 172
5909 10:02:20.303230 iDelay=203, Bit 12, Center 112 (27 ~ 198) 172
5910 10:02:20.306299 iDelay=203, Bit 13, Center 108 (27 ~ 190) 164
5911 10:02:20.310078 iDelay=203, Bit 14, Center 106 (27 ~ 186) 160
5912 10:02:20.316834 iDelay=203, Bit 15, Center 110 (27 ~ 194) 168
5913 10:02:20.316963 ==
5914 10:02:20.319850 Dram Type= 6, Freq= 0, CH_1, rank 1
5915 10:02:20.322906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5916 10:02:20.323013 ==
5917 10:02:20.323086 DQS Delay:
5918 10:02:20.326438 DQS0 = 0, DQS1 = 0
5919 10:02:20.326543 DQM Delay:
5920 10:02:20.329631 DQM0 = 104, DQM1 = 101
5921 10:02:20.329708 DQ Delay:
5922 10:02:20.333360 DQ0 =110, DQ1 =100, DQ2 =94, DQ3 =100
5923 10:02:20.336418 DQ4 =100, DQ5 =118, DQ6 =114, DQ7 =102
5924 10:02:20.339645 DQ8 =90, DQ9 =90, DQ10 =102, DQ11 =92
5925 10:02:20.342923 DQ12 =112, DQ13 =108, DQ14 =106, DQ15 =110
5926 10:02:20.343040
5927 10:02:20.343134
5928 10:02:20.352940 [DQSOSCAuto] RK1, (LSB)MR18= 0x2afd, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 408 ps
5929 10:02:20.356079 CH1 RK1: MR19=504, MR18=2AFD
5930 10:02:20.359347 CH1_RK1: MR19=0x504, MR18=0x2AFD, DQSOSC=408, MR23=63, INC=65, DEC=43
5931 10:02:20.362957 [RxdqsGatingPostProcess] freq 933
5932 10:02:20.369787 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5933 10:02:20.372864 best DQS0 dly(2T, 0.5T) = (0, 10)
5934 10:02:20.376357 best DQS1 dly(2T, 0.5T) = (0, 10)
5935 10:02:20.379770 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5936 10:02:20.382908 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5937 10:02:20.386032 best DQS0 dly(2T, 0.5T) = (0, 10)
5938 10:02:20.389700 best DQS1 dly(2T, 0.5T) = (0, 10)
5939 10:02:20.393208 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5940 10:02:20.396037 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5941 10:02:20.396129 Pre-setting of DQS Precalculation
5942 10:02:20.402839 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5943 10:02:20.409526 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5944 10:02:20.416365 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5945 10:02:20.416513
5946 10:02:20.416630
5947 10:02:20.419279 [Calibration Summary] 1866 Mbps
5948 10:02:20.422575 CH 0, Rank 0
5949 10:02:20.422689 SW Impedance : PASS
5950 10:02:20.426150 DUTY Scan : NO K
5951 10:02:20.429005 ZQ Calibration : PASS
5952 10:02:20.429142 Jitter Meter : NO K
5953 10:02:20.432792 CBT Training : PASS
5954 10:02:20.435880 Write leveling : PASS
5955 10:02:20.435965 RX DQS gating : PASS
5956 10:02:20.439008 RX DQ/DQS(RDDQC) : PASS
5957 10:02:20.439122 TX DQ/DQS : PASS
5958 10:02:20.442241 RX DATLAT : PASS
5959 10:02:20.445891 RX DQ/DQS(Engine): PASS
5960 10:02:20.446010 TX OE : NO K
5961 10:02:20.448926 All Pass.
5962 10:02:20.449019
5963 10:02:20.449107 CH 0, Rank 1
5964 10:02:20.452725 SW Impedance : PASS
5965 10:02:20.452835 DUTY Scan : NO K
5966 10:02:20.455904 ZQ Calibration : PASS
5967 10:02:20.459470 Jitter Meter : NO K
5968 10:02:20.459561 CBT Training : PASS
5969 10:02:20.462676 Write leveling : PASS
5970 10:02:20.465723 RX DQS gating : PASS
5971 10:02:20.465812 RX DQ/DQS(RDDQC) : PASS
5972 10:02:20.469037 TX DQ/DQS : PASS
5973 10:02:20.472664 RX DATLAT : PASS
5974 10:02:20.472753 RX DQ/DQS(Engine): PASS
5975 10:02:20.475729 TX OE : NO K
5976 10:02:20.475815 All Pass.
5977 10:02:20.475882
5978 10:02:20.478983 CH 1, Rank 0
5979 10:02:20.479096 SW Impedance : PASS
5980 10:02:20.482824 DUTY Scan : NO K
5981 10:02:20.482910 ZQ Calibration : PASS
5982 10:02:20.485942 Jitter Meter : NO K
5983 10:02:20.489020 CBT Training : PASS
5984 10:02:20.489106 Write leveling : PASS
5985 10:02:20.492612 RX DQS gating : PASS
5986 10:02:20.496198 RX DQ/DQS(RDDQC) : PASS
5987 10:02:20.496285 TX DQ/DQS : PASS
5988 10:02:20.499135 RX DATLAT : PASS
5989 10:02:20.502728 RX DQ/DQS(Engine): PASS
5990 10:02:20.502816 TX OE : NO K
5991 10:02:20.505572 All Pass.
5992 10:02:20.505666
5993 10:02:20.505734 CH 1, Rank 1
5994 10:02:20.508994 SW Impedance : PASS
5995 10:02:20.509107 DUTY Scan : NO K
5996 10:02:20.512726 ZQ Calibration : PASS
5997 10:02:20.515595 Jitter Meter : NO K
5998 10:02:20.515710 CBT Training : PASS
5999 10:02:20.518988 Write leveling : PASS
6000 10:02:20.522437 RX DQS gating : PASS
6001 10:02:20.522528 RX DQ/DQS(RDDQC) : PASS
6002 10:02:20.525950 TX DQ/DQS : PASS
6003 10:02:20.529448 RX DATLAT : PASS
6004 10:02:20.529564 RX DQ/DQS(Engine): PASS
6005 10:02:20.532226 TX OE : NO K
6006 10:02:20.532332 All Pass.
6007 10:02:20.532429
6008 10:02:20.535749 DramC Write-DBI off
6009 10:02:20.535834 PER_BANK_REFRESH: Hybrid Mode
6010 10:02:20.539220 TX_TRACKING: ON
6011 10:02:20.549023 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6012 10:02:20.552153 [FAST_K] Save calibration result to emmc
6013 10:02:20.556024 dramc_set_vcore_voltage set vcore to 650000
6014 10:02:20.559136 Read voltage for 400, 6
6015 10:02:20.559223 Vio18 = 0
6016 10:02:20.559289 Vcore = 650000
6017 10:02:20.562098 Vdram = 0
6018 10:02:20.562186 Vddq = 0
6019 10:02:20.562254 Vmddr = 0
6020 10:02:20.568831 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6021 10:02:20.572555 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6022 10:02:20.575607 MEM_TYPE=3, freq_sel=20
6023 10:02:20.578646 sv_algorithm_assistance_LP4_800
6024 10:02:20.581815 ============ PULL DRAM RESETB DOWN ============
6025 10:02:20.585645 ========== PULL DRAM RESETB DOWN end =========
6026 10:02:20.592031 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6027 10:02:20.595185 ===================================
6028 10:02:20.595269 LPDDR4 DRAM CONFIGURATION
6029 10:02:20.598991 ===================================
6030 10:02:20.602108 EX_ROW_EN[0] = 0x0
6031 10:02:20.605759 EX_ROW_EN[1] = 0x0
6032 10:02:20.605881 LP4Y_EN = 0x0
6033 10:02:20.608945 WORK_FSP = 0x0
6034 10:02:20.609059 WL = 0x2
6035 10:02:20.611921 RL = 0x2
6036 10:02:20.612004 BL = 0x2
6037 10:02:20.615301 RPST = 0x0
6038 10:02:20.615398 RD_PRE = 0x0
6039 10:02:20.618837 WR_PRE = 0x1
6040 10:02:20.618918 WR_PST = 0x0
6041 10:02:20.621891 DBI_WR = 0x0
6042 10:02:20.621970 DBI_RD = 0x0
6043 10:02:20.625069 OTF = 0x1
6044 10:02:20.628678 ===================================
6045 10:02:20.632234 ===================================
6046 10:02:20.632340 ANA top config
6047 10:02:20.635837 ===================================
6048 10:02:20.638799 DLL_ASYNC_EN = 0
6049 10:02:20.641908 ALL_SLAVE_EN = 1
6050 10:02:20.641994 NEW_RANK_MODE = 1
6051 10:02:20.645233 DLL_IDLE_MODE = 1
6052 10:02:20.648293 LP45_APHY_COMB_EN = 1
6053 10:02:20.651737 TX_ODT_DIS = 1
6054 10:02:20.654892 NEW_8X_MODE = 1
6055 10:02:20.658548 ===================================
6056 10:02:20.661444 ===================================
6057 10:02:20.661562 data_rate = 800
6058 10:02:20.664754 CKR = 1
6059 10:02:20.668102 DQ_P2S_RATIO = 4
6060 10:02:20.671552 ===================================
6061 10:02:20.674749 CA_P2S_RATIO = 4
6062 10:02:20.678448 DQ_CA_OPEN = 0
6063 10:02:20.681526 DQ_SEMI_OPEN = 1
6064 10:02:20.681644 CA_SEMI_OPEN = 1
6065 10:02:20.685288 CA_FULL_RATE = 0
6066 10:02:20.688338 DQ_CKDIV4_EN = 0
6067 10:02:20.691727 CA_CKDIV4_EN = 1
6068 10:02:20.695431 CA_PREDIV_EN = 0
6069 10:02:20.698547 PH8_DLY = 0
6070 10:02:20.698659 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6071 10:02:20.701706 DQ_AAMCK_DIV = 0
6072 10:02:20.704891 CA_AAMCK_DIV = 0
6073 10:02:20.708536 CA_ADMCK_DIV = 4
6074 10:02:20.711575 DQ_TRACK_CA_EN = 0
6075 10:02:20.715330 CA_PICK = 800
6076 10:02:20.715488 CA_MCKIO = 400
6077 10:02:20.718493 MCKIO_SEMI = 400
6078 10:02:20.721703 PLL_FREQ = 3016
6079 10:02:20.725203 DQ_UI_PI_RATIO = 32
6080 10:02:20.728315 CA_UI_PI_RATIO = 32
6081 10:02:20.731487 ===================================
6082 10:02:20.734690 ===================================
6083 10:02:20.738216 memory_type:LPDDR4
6084 10:02:20.738336 GP_NUM : 10
6085 10:02:20.741689 SRAM_EN : 1
6086 10:02:20.744871 MD32_EN : 0
6087 10:02:20.748149 ===================================
6088 10:02:20.748283 [ANA_INIT] >>>>>>>>>>>>>>
6089 10:02:20.751223 <<<<<< [CONFIGURE PHASE]: ANA_TX
6090 10:02:20.754858 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6091 10:02:20.757978 ===================================
6092 10:02:20.761463 data_rate = 800,PCW = 0X7400
6093 10:02:20.765596 ===================================
6094 10:02:20.768120 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6095 10:02:20.774597 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6096 10:02:20.784696 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6097 10:02:20.788127 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6098 10:02:20.791499 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6099 10:02:20.794580 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6100 10:02:20.797855 [ANA_INIT] flow start
6101 10:02:20.801388 [ANA_INIT] PLL >>>>>>>>
6102 10:02:20.801515 [ANA_INIT] PLL <<<<<<<<
6103 10:02:20.804490 [ANA_INIT] MIDPI >>>>>>>>
6104 10:02:20.807776 [ANA_INIT] MIDPI <<<<<<<<
6105 10:02:20.811623 [ANA_INIT] DLL >>>>>>>>
6106 10:02:20.811709 [ANA_INIT] flow end
6107 10:02:20.814792 ============ LP4 DIFF to SE enter ============
6108 10:02:20.821450 ============ LP4 DIFF to SE exit ============
6109 10:02:20.821557 [ANA_INIT] <<<<<<<<<<<<<
6110 10:02:20.824675 [Flow] Enable top DCM control >>>>>
6111 10:02:20.827682 [Flow] Enable top DCM control <<<<<
6112 10:02:20.831170 Enable DLL master slave shuffle
6113 10:02:20.838067 ==============================================================
6114 10:02:20.838165 Gating Mode config
6115 10:02:20.844971 ==============================================================
6116 10:02:20.847888 Config description:
6117 10:02:20.857820 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6118 10:02:20.864534 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6119 10:02:20.867721 SELPH_MODE 0: By rank 1: By Phase
6120 10:02:20.874500 ==============================================================
6121 10:02:20.874599 GAT_TRACK_EN = 0
6122 10:02:20.878369 RX_GATING_MODE = 2
6123 10:02:20.881523 RX_GATING_TRACK_MODE = 2
6124 10:02:20.884465 SELPH_MODE = 1
6125 10:02:20.888315 PICG_EARLY_EN = 1
6126 10:02:20.891363 VALID_LAT_VALUE = 1
6127 10:02:20.897742 ==============================================================
6128 10:02:20.901499 Enter into Gating configuration >>>>
6129 10:02:20.904197 Exit from Gating configuration <<<<
6130 10:02:20.907636 Enter into DVFS_PRE_config >>>>>
6131 10:02:20.917529 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6132 10:02:20.920784 Exit from DVFS_PRE_config <<<<<
6133 10:02:20.924353 Enter into PICG configuration >>>>
6134 10:02:20.927769 Exit from PICG configuration <<<<
6135 10:02:20.930843 [RX_INPUT] configuration >>>>>
6136 10:02:20.934203 [RX_INPUT] configuration <<<<<
6137 10:02:20.937327 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6138 10:02:20.944334 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6139 10:02:20.951156 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6140 10:02:20.954348 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6141 10:02:20.960578 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6142 10:02:20.967618 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6143 10:02:20.970672 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6144 10:02:20.976926 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6145 10:02:20.980679 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6146 10:02:20.983911 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6147 10:02:20.987091 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6148 10:02:20.993964 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6149 10:02:20.996941 ===================================
6150 10:02:20.997029 LPDDR4 DRAM CONFIGURATION
6151 10:02:21.000152 ===================================
6152 10:02:21.003493 EX_ROW_EN[0] = 0x0
6153 10:02:21.007079 EX_ROW_EN[1] = 0x0
6154 10:02:21.007166 LP4Y_EN = 0x0
6155 10:02:21.010192 WORK_FSP = 0x0
6156 10:02:21.010284 WL = 0x2
6157 10:02:21.013381 RL = 0x2
6158 10:02:21.013494 BL = 0x2
6159 10:02:21.017125 RPST = 0x0
6160 10:02:21.017213 RD_PRE = 0x0
6161 10:02:21.020323 WR_PRE = 0x1
6162 10:02:21.020443 WR_PST = 0x0
6163 10:02:21.023321 DBI_WR = 0x0
6164 10:02:21.023406 DBI_RD = 0x0
6165 10:02:21.027106 OTF = 0x1
6166 10:02:21.030193 ===================================
6167 10:02:21.033252 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6168 10:02:21.037004 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6169 10:02:21.043498 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6170 10:02:21.046537 ===================================
6171 10:02:21.046655 LPDDR4 DRAM CONFIGURATION
6172 10:02:21.049953 ===================================
6173 10:02:21.053140 EX_ROW_EN[0] = 0x10
6174 10:02:21.056498 EX_ROW_EN[1] = 0x0
6175 10:02:21.056579 LP4Y_EN = 0x0
6176 10:02:21.059742 WORK_FSP = 0x0
6177 10:02:21.059849 WL = 0x2
6178 10:02:21.063069 RL = 0x2
6179 10:02:21.063167 BL = 0x2
6180 10:02:21.066468 RPST = 0x0
6181 10:02:21.066550 RD_PRE = 0x0
6182 10:02:21.070547 WR_PRE = 0x1
6183 10:02:21.070669 WR_PST = 0x0
6184 10:02:21.073166 DBI_WR = 0x0
6185 10:02:21.073246 DBI_RD = 0x0
6186 10:02:21.076224 OTF = 0x1
6187 10:02:21.079997 ===================================
6188 10:02:21.086318 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6189 10:02:21.089670 nWR fixed to 30
6190 10:02:21.092842 [ModeRegInit_LP4] CH0 RK0
6191 10:02:21.092951 [ModeRegInit_LP4] CH0 RK1
6192 10:02:21.096620 [ModeRegInit_LP4] CH1 RK0
6193 10:02:21.099890 [ModeRegInit_LP4] CH1 RK1
6194 10:02:21.099972 match AC timing 19
6195 10:02:21.106100 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6196 10:02:21.109298 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6197 10:02:21.113063 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6198 10:02:21.119782 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6199 10:02:21.122983 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6200 10:02:21.123086 ==
6201 10:02:21.126141 Dram Type= 6, Freq= 0, CH_0, rank 0
6202 10:02:21.129782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6203 10:02:21.129878 ==
6204 10:02:21.135986 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6205 10:02:21.142483 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6206 10:02:21.146188 [CA 0] Center 36 (8~64) winsize 57
6207 10:02:21.149545 [CA 1] Center 36 (8~64) winsize 57
6208 10:02:21.149651 [CA 2] Center 36 (8~64) winsize 57
6209 10:02:21.152442 [CA 3] Center 36 (8~64) winsize 57
6210 10:02:21.156165 [CA 4] Center 36 (8~64) winsize 57
6211 10:02:21.159326 [CA 5] Center 36 (8~64) winsize 57
6212 10:02:21.159407
6213 10:02:21.162339 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6214 10:02:21.162420
6215 10:02:21.169458 [CATrainingPosCal] consider 1 rank data
6216 10:02:21.169584 u2DelayCellTimex100 = 270/100 ps
6217 10:02:21.172840 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6218 10:02:21.179221 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6219 10:02:21.182759 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6220 10:02:21.185959 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6221 10:02:21.189497 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6222 10:02:21.192316 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6223 10:02:21.192397
6224 10:02:21.195929 CA PerBit enable=1, Macro0, CA PI delay=36
6225 10:02:21.196019
6226 10:02:21.199428 [CBTSetCACLKResult] CA Dly = 36
6227 10:02:21.202853 CS Dly: 1 (0~32)
6228 10:02:21.202937 ==
6229 10:02:21.205914 Dram Type= 6, Freq= 0, CH_0, rank 1
6230 10:02:21.209168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6231 10:02:21.209280 ==
6232 10:02:21.212639 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6233 10:02:21.219506 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6234 10:02:21.222717 [CA 0] Center 36 (8~64) winsize 57
6235 10:02:21.225844 [CA 1] Center 36 (8~64) winsize 57
6236 10:02:21.229650 [CA 2] Center 36 (8~64) winsize 57
6237 10:02:21.233156 [CA 3] Center 36 (8~64) winsize 57
6238 10:02:21.236095 [CA 4] Center 36 (8~64) winsize 57
6239 10:02:21.239298 [CA 5] Center 36 (8~64) winsize 57
6240 10:02:21.239408
6241 10:02:21.242356 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6242 10:02:21.242468
6243 10:02:21.245512 [CATrainingPosCal] consider 2 rank data
6244 10:02:21.249294 u2DelayCellTimex100 = 270/100 ps
6245 10:02:21.252478 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6246 10:02:21.256044 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6247 10:02:21.259206 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6248 10:02:21.262237 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6249 10:02:21.269119 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 10:02:21.272279 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6251 10:02:21.272415
6252 10:02:21.275997 CA PerBit enable=1, Macro0, CA PI delay=36
6253 10:02:21.276134
6254 10:02:21.278765 [CBTSetCACLKResult] CA Dly = 36
6255 10:02:21.278872 CS Dly: 1 (0~32)
6256 10:02:21.278958
6257 10:02:21.282251 ----->DramcWriteLeveling(PI) begin...
6258 10:02:21.282351 ==
6259 10:02:21.285491 Dram Type= 6, Freq= 0, CH_0, rank 0
6260 10:02:21.292116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6261 10:02:21.292231 ==
6262 10:02:21.295263 Write leveling (Byte 0): 40 => 8
6263 10:02:21.295348 Write leveling (Byte 1): 40 => 8
6264 10:02:21.299181 DramcWriteLeveling(PI) end<-----
6265 10:02:21.299274
6266 10:02:21.302294 ==
6267 10:02:21.302396 Dram Type= 6, Freq= 0, CH_0, rank 0
6268 10:02:21.308459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6269 10:02:21.308543 ==
6270 10:02:21.312216 [Gating] SW mode calibration
6271 10:02:21.319036 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6272 10:02:21.322540 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6273 10:02:21.328582 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6274 10:02:21.332132 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6275 10:02:21.335800 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6276 10:02:21.342173 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6277 10:02:21.345471 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6278 10:02:21.348639 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6279 10:02:21.355526 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6280 10:02:21.358731 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6281 10:02:21.361720 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6282 10:02:21.365440 Total UI for P1: 0, mck2ui 16
6283 10:02:21.368636 best dqsien dly found for B0: ( 0, 14, 24)
6284 10:02:21.371894 Total UI for P1: 0, mck2ui 16
6285 10:02:21.375430 best dqsien dly found for B1: ( 0, 14, 24)
6286 10:02:21.378626 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6287 10:02:21.381818 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6288 10:02:21.381901
6289 10:02:21.385143 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6290 10:02:21.391535 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6291 10:02:21.391669 [Gating] SW calibration Done
6292 10:02:21.394932 ==
6293 10:02:21.395043 Dram Type= 6, Freq= 0, CH_0, rank 0
6294 10:02:21.401860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6295 10:02:21.401962 ==
6296 10:02:21.402052 RX Vref Scan: 0
6297 10:02:21.402116
6298 10:02:21.405062 RX Vref 0 -> 0, step: 1
6299 10:02:21.405181
6300 10:02:21.408241 RX Delay -410 -> 252, step: 16
6301 10:02:21.411861 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6302 10:02:21.415015 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6303 10:02:21.422003 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6304 10:02:21.425313 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6305 10:02:21.428012 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6306 10:02:21.431592 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6307 10:02:21.438763 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6308 10:02:21.441749 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6309 10:02:21.445155 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6310 10:02:21.448039 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6311 10:02:21.454734 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6312 10:02:21.458100 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6313 10:02:21.461387 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6314 10:02:21.465014 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6315 10:02:21.471242 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6316 10:02:21.474872 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6317 10:02:21.474988 ==
6318 10:02:21.477973 Dram Type= 6, Freq= 0, CH_0, rank 0
6319 10:02:21.481207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6320 10:02:21.481327 ==
6321 10:02:21.484983 DQS Delay:
6322 10:02:21.485097 DQS0 = 27, DQS1 = 35
6323 10:02:21.488161 DQM Delay:
6324 10:02:21.488282 DQM0 = 10, DQM1 = 11
6325 10:02:21.488376 DQ Delay:
6326 10:02:21.491268 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6327 10:02:21.494816 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6328 10:02:21.498175 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6329 10:02:21.501325 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6330 10:02:21.501413
6331 10:02:21.501484
6332 10:02:21.501545 ==
6333 10:02:21.504865 Dram Type= 6, Freq= 0, CH_0, rank 0
6334 10:02:21.511537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6335 10:02:21.511666 ==
6336 10:02:21.511790
6337 10:02:21.511881
6338 10:02:21.511972 TX Vref Scan disable
6339 10:02:21.514675 == TX Byte 0 ==
6340 10:02:21.517831 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6341 10:02:21.521561 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6342 10:02:21.524821 == TX Byte 1 ==
6343 10:02:21.527895 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6344 10:02:21.531152 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6345 10:02:21.531259 ==
6346 10:02:21.534205 Dram Type= 6, Freq= 0, CH_0, rank 0
6347 10:02:21.540839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6348 10:02:21.540963 ==
6349 10:02:21.541065
6350 10:02:21.541163
6351 10:02:21.541264 TX Vref Scan disable
6352 10:02:21.544760 == TX Byte 0 ==
6353 10:02:21.547836 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6354 10:02:21.551113 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6355 10:02:21.554687 == TX Byte 1 ==
6356 10:02:21.557510 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6357 10:02:21.561030 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6358 10:02:21.561140
6359 10:02:21.564464 [DATLAT]
6360 10:02:21.564570 Freq=400, CH0 RK0
6361 10:02:21.564666
6362 10:02:21.567620 DATLAT Default: 0xf
6363 10:02:21.567732 0, 0xFFFF, sum = 0
6364 10:02:21.571243 1, 0xFFFF, sum = 0
6365 10:02:21.571327 2, 0xFFFF, sum = 0
6366 10:02:21.574242 3, 0xFFFF, sum = 0
6367 10:02:21.574321 4, 0xFFFF, sum = 0
6368 10:02:21.577456 5, 0xFFFF, sum = 0
6369 10:02:21.577560 6, 0xFFFF, sum = 0
6370 10:02:21.580787 7, 0xFFFF, sum = 0
6371 10:02:21.580896 8, 0xFFFF, sum = 0
6372 10:02:21.584592 9, 0xFFFF, sum = 0
6373 10:02:21.587835 10, 0xFFFF, sum = 0
6374 10:02:21.587916 11, 0xFFFF, sum = 0
6375 10:02:21.590885 12, 0xFFFF, sum = 0
6376 10:02:21.590962 13, 0x0, sum = 1
6377 10:02:21.594445 14, 0x0, sum = 2
6378 10:02:21.594566 15, 0x0, sum = 3
6379 10:02:21.594667 16, 0x0, sum = 4
6380 10:02:21.597546 best_step = 14
6381 10:02:21.597639
6382 10:02:21.597714 ==
6383 10:02:21.601150 Dram Type= 6, Freq= 0, CH_0, rank 0
6384 10:02:21.604347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6385 10:02:21.604428 ==
6386 10:02:21.608100 RX Vref Scan: 1
6387 10:02:21.608179
6388 10:02:21.608247 RX Vref 0 -> 0, step: 1
6389 10:02:21.610841
6390 10:02:21.610941 RX Delay -311 -> 252, step: 8
6391 10:02:21.611013
6392 10:02:21.614133 Set Vref, RX VrefLevel [Byte0]: 56
6393 10:02:21.617335 [Byte1]: 47
6394 10:02:21.622829
6395 10:02:21.622914 Final RX Vref Byte 0 = 56 to rank0
6396 10:02:21.626203 Final RX Vref Byte 1 = 47 to rank0
6397 10:02:21.629282 Final RX Vref Byte 0 = 56 to rank1
6398 10:02:21.632345 Final RX Vref Byte 1 = 47 to rank1==
6399 10:02:21.636201 Dram Type= 6, Freq= 0, CH_0, rank 0
6400 10:02:21.642205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6401 10:02:21.642307 ==
6402 10:02:21.642382 DQS Delay:
6403 10:02:21.645766 DQS0 = 28, DQS1 = 36
6404 10:02:21.645883 DQM Delay:
6405 10:02:21.645988 DQM0 = 12, DQM1 = 13
6406 10:02:21.649287 DQ Delay:
6407 10:02:21.652270 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =8
6408 10:02:21.655577 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6409 10:02:21.655689 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
6410 10:02:21.659213 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =20
6411 10:02:21.662445
6412 10:02:21.662553
6413 10:02:21.669117 [DQSOSCAuto] RK0, (LSB)MR18= 0xcebb, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 384 ps
6414 10:02:21.672536 CH0 RK0: MR19=C0C, MR18=CEBB
6415 10:02:21.678899 CH0_RK0: MR19=0xC0C, MR18=0xCEBB, DQSOSC=384, MR23=63, INC=400, DEC=267
6416 10:02:21.679034 ==
6417 10:02:21.682101 Dram Type= 6, Freq= 0, CH_0, rank 1
6418 10:02:21.685700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6419 10:02:21.685817 ==
6420 10:02:21.688577 [Gating] SW mode calibration
6421 10:02:21.695157 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6422 10:02:21.702097 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6423 10:02:21.705558 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6424 10:02:21.708764 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6425 10:02:21.714987 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6426 10:02:21.718456 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6427 10:02:21.721669 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6428 10:02:21.728417 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6429 10:02:21.731937 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6430 10:02:21.735092 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6431 10:02:21.741948 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6432 10:02:21.742044 Total UI for P1: 0, mck2ui 16
6433 10:02:21.748092 best dqsien dly found for B0: ( 0, 14, 24)
6434 10:02:21.748195 Total UI for P1: 0, mck2ui 16
6435 10:02:21.755082 best dqsien dly found for B1: ( 0, 14, 24)
6436 10:02:21.758085 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6437 10:02:21.761278 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6438 10:02:21.761361
6439 10:02:21.765065 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6440 10:02:21.768309 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6441 10:02:21.771428 [Gating] SW calibration Done
6442 10:02:21.771550 ==
6443 10:02:21.774462 Dram Type= 6, Freq= 0, CH_0, rank 1
6444 10:02:21.778229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6445 10:02:21.778336 ==
6446 10:02:21.781119 RX Vref Scan: 0
6447 10:02:21.781222
6448 10:02:21.781319 RX Vref 0 -> 0, step: 1
6449 10:02:21.781410
6450 10:02:21.784839 RX Delay -410 -> 252, step: 16
6451 10:02:21.791523 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6452 10:02:21.794549 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6453 10:02:21.797527 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6454 10:02:21.800908 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6455 10:02:21.807689 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6456 10:02:21.811157 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6457 10:02:21.814243 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6458 10:02:21.818036 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6459 10:02:21.824183 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6460 10:02:21.827662 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6461 10:02:21.830996 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6462 10:02:21.834296 iDelay=230, Bit 11, Center -27 (-250 ~ 197) 448
6463 10:02:21.840964 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6464 10:02:21.844307 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6465 10:02:21.847286 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6466 10:02:21.850943 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6467 10:02:21.854050 ==
6468 10:02:21.854167 Dram Type= 6, Freq= 0, CH_0, rank 1
6469 10:02:21.860840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6470 10:02:21.860929 ==
6471 10:02:21.861002 DQS Delay:
6472 10:02:21.864649 DQS0 = 19, DQS1 = 35
6473 10:02:21.864757 DQM Delay:
6474 10:02:21.867937 DQM0 = 5, DQM1 = 12
6475 10:02:21.868051 DQ Delay:
6476 10:02:21.871045 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6477 10:02:21.874274 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6478 10:02:21.874377 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6479 10:02:21.877412 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6480 10:02:21.881012
6481 10:02:21.881126
6482 10:02:21.881227 ==
6483 10:02:21.884088 Dram Type= 6, Freq= 0, CH_0, rank 1
6484 10:02:21.887827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6485 10:02:21.887933 ==
6486 10:02:21.888028
6487 10:02:21.888118
6488 10:02:21.890843 TX Vref Scan disable
6489 10:02:21.890940 == TX Byte 0 ==
6490 10:02:21.894449 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6491 10:02:21.900928 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6492 10:02:21.901050 == TX Byte 1 ==
6493 10:02:21.903937 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6494 10:02:21.911048 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6495 10:02:21.911188 ==
6496 10:02:21.914558 Dram Type= 6, Freq= 0, CH_0, rank 1
6497 10:02:21.917623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6498 10:02:21.917723 ==
6499 10:02:21.917808
6500 10:02:21.917908
6501 10:02:21.921189 TX Vref Scan disable
6502 10:02:21.921306 == TX Byte 0 ==
6503 10:02:21.924364 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6504 10:02:21.930647 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6505 10:02:21.930779 == TX Byte 1 ==
6506 10:02:21.933934 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6507 10:02:21.940900 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6508 10:02:21.941013
6509 10:02:21.941115 [DATLAT]
6510 10:02:21.941205 Freq=400, CH0 RK1
6511 10:02:21.941302
6512 10:02:21.944308 DATLAT Default: 0xe
6513 10:02:21.947782 0, 0xFFFF, sum = 0
6514 10:02:21.947895 1, 0xFFFF, sum = 0
6515 10:02:21.950886 2, 0xFFFF, sum = 0
6516 10:02:21.950997 3, 0xFFFF, sum = 0
6517 10:02:21.954576 4, 0xFFFF, sum = 0
6518 10:02:21.954697 5, 0xFFFF, sum = 0
6519 10:02:21.957661 6, 0xFFFF, sum = 0
6520 10:02:21.957781 7, 0xFFFF, sum = 0
6521 10:02:21.960682 8, 0xFFFF, sum = 0
6522 10:02:21.960806 9, 0xFFFF, sum = 0
6523 10:02:21.963992 10, 0xFFFF, sum = 0
6524 10:02:21.964114 11, 0xFFFF, sum = 0
6525 10:02:21.967792 12, 0xFFFF, sum = 0
6526 10:02:21.967902 13, 0x0, sum = 1
6527 10:02:21.970858 14, 0x0, sum = 2
6528 10:02:21.970985 15, 0x0, sum = 3
6529 10:02:21.974175 16, 0x0, sum = 4
6530 10:02:21.974273 best_step = 14
6531 10:02:21.974360
6532 10:02:21.974444 ==
6533 10:02:21.977420 Dram Type= 6, Freq= 0, CH_0, rank 1
6534 10:02:21.981126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6535 10:02:21.984218 ==
6536 10:02:21.984301 RX Vref Scan: 0
6537 10:02:21.984388
6538 10:02:21.987682 RX Vref 0 -> 0, step: 1
6539 10:02:21.987761
6540 10:02:21.990799 RX Delay -311 -> 252, step: 8
6541 10:02:21.993882 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6542 10:02:22.000773 iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440
6543 10:02:22.004403 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6544 10:02:22.007462 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6545 10:02:22.010650 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6546 10:02:22.017922 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6547 10:02:22.020578 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6548 10:02:22.023791 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6549 10:02:22.027583 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6550 10:02:22.033774 iDelay=217, Bit 9, Center -36 (-255 ~ 184) 440
6551 10:02:22.037273 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6552 10:02:22.040871 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6553 10:02:22.044303 iDelay=217, Bit 12, Center -16 (-231 ~ 200) 432
6554 10:02:22.050470 iDelay=217, Bit 13, Center -16 (-231 ~ 200) 432
6555 10:02:22.054128 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6556 10:02:22.057324 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6557 10:02:22.057447 ==
6558 10:02:22.060347 Dram Type= 6, Freq= 0, CH_0, rank 1
6559 10:02:22.067036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6560 10:02:22.067187 ==
6561 10:02:22.067287 DQS Delay:
6562 10:02:22.070410 DQS0 = 24, DQS1 = 36
6563 10:02:22.070487 DQM Delay:
6564 10:02:22.070615 DQM0 = 8, DQM1 = 14
6565 10:02:22.073613 DQ Delay:
6566 10:02:22.077406 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6567 10:02:22.077528 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6568 10:02:22.080231 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6569 10:02:22.083734 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6570 10:02:22.083821
6571 10:02:22.083902
6572 10:02:22.093801 [DQSOSCAuto] RK1, (LSB)MR18= 0xbd5d, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 386 ps
6573 10:02:22.097021 CH0 RK1: MR19=C0C, MR18=BD5D
6574 10:02:22.103811 CH0_RK1: MR19=0xC0C, MR18=0xBD5D, DQSOSC=386, MR23=63, INC=396, DEC=264
6575 10:02:22.106832 [RxdqsGatingPostProcess] freq 400
6576 10:02:22.110684 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6577 10:02:22.113496 best DQS0 dly(2T, 0.5T) = (0, 10)
6578 10:02:22.117132 best DQS1 dly(2T, 0.5T) = (0, 10)
6579 10:02:22.120219 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6580 10:02:22.123535 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6581 10:02:22.127285 best DQS0 dly(2T, 0.5T) = (0, 10)
6582 10:02:22.130211 best DQS1 dly(2T, 0.5T) = (0, 10)
6583 10:02:22.133999 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6584 10:02:22.136708 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6585 10:02:22.140074 Pre-setting of DQS Precalculation
6586 10:02:22.143586 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6587 10:02:22.143707 ==
6588 10:02:22.146981 Dram Type= 6, Freq= 0, CH_1, rank 0
6589 10:02:22.150273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6590 10:02:22.153689 ==
6591 10:02:22.157010 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6592 10:02:22.163421 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6593 10:02:22.167154 [CA 0] Center 36 (8~64) winsize 57
6594 10:02:22.170316 [CA 1] Center 36 (8~64) winsize 57
6595 10:02:22.173703 [CA 2] Center 36 (8~64) winsize 57
6596 10:02:22.176815 [CA 3] Center 36 (8~64) winsize 57
6597 10:02:22.179900 [CA 4] Center 36 (8~64) winsize 57
6598 10:02:22.183054 [CA 5] Center 36 (8~64) winsize 57
6599 10:02:22.183175
6600 10:02:22.186337 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6601 10:02:22.186455
6602 10:02:22.189838 [CATrainingPosCal] consider 1 rank data
6603 10:02:22.193193 u2DelayCellTimex100 = 270/100 ps
6604 10:02:22.196843 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6605 10:02:22.199974 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6606 10:02:22.203277 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6607 10:02:22.206503 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6608 10:02:22.209607 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6609 10:02:22.213318 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6610 10:02:22.213436
6611 10:02:22.219585 CA PerBit enable=1, Macro0, CA PI delay=36
6612 10:02:22.219699
6613 10:02:22.219799 [CBTSetCACLKResult] CA Dly = 36
6614 10:02:22.222948 CS Dly: 1 (0~32)
6615 10:02:22.223056 ==
6616 10:02:22.226158 Dram Type= 6, Freq= 0, CH_1, rank 1
6617 10:02:22.229260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6618 10:02:22.229379 ==
6619 10:02:22.236335 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6620 10:02:22.242552 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6621 10:02:22.246143 [CA 0] Center 36 (8~64) winsize 57
6622 10:02:22.249501 [CA 1] Center 36 (8~64) winsize 57
6623 10:02:22.252539 [CA 2] Center 36 (8~64) winsize 57
6624 10:02:22.256032 [CA 3] Center 36 (8~64) winsize 57
6625 10:02:22.256141 [CA 4] Center 36 (8~64) winsize 57
6626 10:02:22.259096 [CA 5] Center 36 (8~64) winsize 57
6627 10:02:22.259205
6628 10:02:22.266313 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6629 10:02:22.266397
6630 10:02:22.269638 [CATrainingPosCal] consider 2 rank data
6631 10:02:22.272565 u2DelayCellTimex100 = 270/100 ps
6632 10:02:22.276273 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6633 10:02:22.279345 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6634 10:02:22.282648 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6635 10:02:22.285926 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6636 10:02:22.289605 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 10:02:22.292742 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6638 10:02:22.292830
6639 10:02:22.296252 CA PerBit enable=1, Macro0, CA PI delay=36
6640 10:02:22.296332
6641 10:02:22.299347 [CBTSetCACLKResult] CA Dly = 36
6642 10:02:22.302423 CS Dly: 1 (0~32)
6643 10:02:22.302511
6644 10:02:22.305964 ----->DramcWriteLeveling(PI) begin...
6645 10:02:22.306081 ==
6646 10:02:22.308986 Dram Type= 6, Freq= 0, CH_1, rank 0
6647 10:02:22.312424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6648 10:02:22.312541 ==
6649 10:02:22.315725 Write leveling (Byte 0): 40 => 8
6650 10:02:22.319035 Write leveling (Byte 1): 40 => 8
6651 10:02:22.322825 DramcWriteLeveling(PI) end<-----
6652 10:02:22.322909
6653 10:02:22.323018 ==
6654 10:02:22.326057 Dram Type= 6, Freq= 0, CH_1, rank 0
6655 10:02:22.329005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6656 10:02:22.329108 ==
6657 10:02:22.332527 [Gating] SW mode calibration
6658 10:02:22.338872 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6659 10:02:22.345832 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6660 10:02:22.349103 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6661 10:02:22.351973 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6662 10:02:22.359196 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6663 10:02:22.361995 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6664 10:02:22.365621 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6665 10:02:22.372719 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6666 10:02:22.375509 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6667 10:02:22.378668 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6668 10:02:22.385713 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6669 10:02:22.385805 Total UI for P1: 0, mck2ui 16
6670 10:02:22.392153 best dqsien dly found for B0: ( 0, 14, 24)
6671 10:02:22.392272 Total UI for P1: 0, mck2ui 16
6672 10:02:22.399082 best dqsien dly found for B1: ( 0, 14, 24)
6673 10:02:22.402044 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6674 10:02:22.405076 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6675 10:02:22.405193
6676 10:02:22.408646 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6677 10:02:22.411719 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6678 10:02:22.415423 [Gating] SW calibration Done
6679 10:02:22.415510 ==
6680 10:02:22.418415 Dram Type= 6, Freq= 0, CH_1, rank 0
6681 10:02:22.421967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6682 10:02:22.422056 ==
6683 10:02:22.425329 RX Vref Scan: 0
6684 10:02:22.425442
6685 10:02:22.425545 RX Vref 0 -> 0, step: 1
6686 10:02:22.428807
6687 10:02:22.428926 RX Delay -410 -> 252, step: 16
6688 10:02:22.435075 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6689 10:02:22.438716 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6690 10:02:22.441720 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6691 10:02:22.444862 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6692 10:02:22.451595 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6693 10:02:22.454754 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6694 10:02:22.458045 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6695 10:02:22.461715 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6696 10:02:22.468073 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6697 10:02:22.471655 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6698 10:02:22.475173 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6699 10:02:22.478287 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6700 10:02:22.484857 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6701 10:02:22.488474 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6702 10:02:22.491325 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6703 10:02:22.498357 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6704 10:02:22.498479 ==
6705 10:02:22.501462 Dram Type= 6, Freq= 0, CH_1, rank 0
6706 10:02:22.504788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6707 10:02:22.504885 ==
6708 10:02:22.505000 DQS Delay:
6709 10:02:22.508286 DQS0 = 27, DQS1 = 35
6710 10:02:22.508384 DQM Delay:
6711 10:02:22.511454 DQM0 = 11, DQM1 = 13
6712 10:02:22.511545 DQ Delay:
6713 10:02:22.514586 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6714 10:02:22.518279 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6715 10:02:22.521507 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6716 10:02:22.525199 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6717 10:02:22.525335
6718 10:02:22.525436
6719 10:02:22.525526 ==
6720 10:02:22.528226 Dram Type= 6, Freq= 0, CH_1, rank 0
6721 10:02:22.531357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6722 10:02:22.531467 ==
6723 10:02:22.531573
6724 10:02:22.531673
6725 10:02:22.534959 TX Vref Scan disable
6726 10:02:22.535072 == TX Byte 0 ==
6727 10:02:22.541150 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6728 10:02:22.544987 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6729 10:02:22.545096 == TX Byte 1 ==
6730 10:02:22.551073 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6731 10:02:22.554878 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6732 10:02:22.554974 ==
6733 10:02:22.557967 Dram Type= 6, Freq= 0, CH_1, rank 0
6734 10:02:22.561099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6735 10:02:22.561189 ==
6736 10:02:22.561274
6737 10:02:22.561353
6738 10:02:22.564806 TX Vref Scan disable
6739 10:02:22.564886 == TX Byte 0 ==
6740 10:02:22.571065 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6741 10:02:22.574666 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6742 10:02:22.574755 == TX Byte 1 ==
6743 10:02:22.580942 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6744 10:02:22.584802 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6745 10:02:22.584890
6746 10:02:22.584960 [DATLAT]
6747 10:02:22.587842 Freq=400, CH1 RK0
6748 10:02:22.587951
6749 10:02:22.588040 DATLAT Default: 0xf
6750 10:02:22.591062 0, 0xFFFF, sum = 0
6751 10:02:22.591147 1, 0xFFFF, sum = 0
6752 10:02:22.594617 2, 0xFFFF, sum = 0
6753 10:02:22.594706 3, 0xFFFF, sum = 0
6754 10:02:22.597733 4, 0xFFFF, sum = 0
6755 10:02:22.597842 5, 0xFFFF, sum = 0
6756 10:02:22.601211 6, 0xFFFF, sum = 0
6757 10:02:22.601297 7, 0xFFFF, sum = 0
6758 10:02:22.604774 8, 0xFFFF, sum = 0
6759 10:02:22.604858 9, 0xFFFF, sum = 0
6760 10:02:22.608289 10, 0xFFFF, sum = 0
6761 10:02:22.611136 11, 0xFFFF, sum = 0
6762 10:02:22.611231 12, 0xFFFF, sum = 0
6763 10:02:22.614595 13, 0x0, sum = 1
6764 10:02:22.614725 14, 0x0, sum = 2
6765 10:02:22.618038 15, 0x0, sum = 3
6766 10:02:22.618163 16, 0x0, sum = 4
6767 10:02:22.618267 best_step = 14
6768 10:02:22.618357
6769 10:02:22.621079 ==
6770 10:02:22.621193 Dram Type= 6, Freq= 0, CH_1, rank 0
6771 10:02:22.627374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6772 10:02:22.627501 ==
6773 10:02:22.627603 RX Vref Scan: 1
6774 10:02:22.627707
6775 10:02:22.631122 RX Vref 0 -> 0, step: 1
6776 10:02:22.631230
6777 10:02:22.634246 RX Delay -311 -> 252, step: 8
6778 10:02:22.634327
6779 10:02:22.637469 Set Vref, RX VrefLevel [Byte0]: 54
6780 10:02:22.641015 [Byte1]: 48
6781 10:02:22.644628
6782 10:02:22.644712 Final RX Vref Byte 0 = 54 to rank0
6783 10:02:22.647480 Final RX Vref Byte 1 = 48 to rank0
6784 10:02:22.650839 Final RX Vref Byte 0 = 54 to rank1
6785 10:02:22.654118 Final RX Vref Byte 1 = 48 to rank1==
6786 10:02:22.657924 Dram Type= 6, Freq= 0, CH_1, rank 0
6787 10:02:22.664223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6788 10:02:22.664349 ==
6789 10:02:22.664449 DQS Delay:
6790 10:02:22.667498 DQS0 = 24, DQS1 = 32
6791 10:02:22.667602 DQM Delay:
6792 10:02:22.667711 DQM0 = 6, DQM1 = 11
6793 10:02:22.670514 DQ Delay:
6794 10:02:22.674351 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =4
6795 10:02:22.674454 DQ4 =8, DQ5 =16, DQ6 =12, DQ7 =4
6796 10:02:22.677565 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6797 10:02:22.680518 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =24
6798 10:02:22.680628
6799 10:02:22.680722
6800 10:02:22.690631 [DQSOSCAuto] RK0, (LSB)MR18= 0x90c9, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6801 10:02:22.693686 CH1 RK0: MR19=C0C, MR18=90C9
6802 10:02:22.700424 CH1_RK0: MR19=0xC0C, MR18=0x90C9, DQSOSC=384, MR23=63, INC=400, DEC=267
6803 10:02:22.700545 ==
6804 10:02:22.703616 Dram Type= 6, Freq= 0, CH_1, rank 1
6805 10:02:22.706855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6806 10:02:22.706932 ==
6807 10:02:22.710679 [Gating] SW mode calibration
6808 10:02:22.717216 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6809 10:02:22.723579 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6810 10:02:22.726853 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6811 10:02:22.730018 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6812 10:02:22.733736 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6813 10:02:22.740612 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6814 10:02:22.743755 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6815 10:02:22.746827 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6816 10:02:22.753270 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6817 10:02:22.756839 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6818 10:02:22.759983 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6819 10:02:22.763203 Total UI for P1: 0, mck2ui 16
6820 10:02:22.766411 best dqsien dly found for B0: ( 0, 14, 24)
6821 10:02:22.769936 Total UI for P1: 0, mck2ui 16
6822 10:02:22.773167 best dqsien dly found for B1: ( 0, 14, 24)
6823 10:02:22.776566 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6824 10:02:22.783217 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6825 10:02:22.783351
6826 10:02:22.786811 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6827 10:02:22.789851 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6828 10:02:22.793025 [Gating] SW calibration Done
6829 10:02:22.793170 ==
6830 10:02:22.796518 Dram Type= 6, Freq= 0, CH_1, rank 1
6831 10:02:22.799931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6832 10:02:22.800064 ==
6833 10:02:22.803412 RX Vref Scan: 0
6834 10:02:22.803501
6835 10:02:22.803591 RX Vref 0 -> 0, step: 1
6836 10:02:22.803685
6837 10:02:22.806617 RX Delay -410 -> 252, step: 16
6838 10:02:22.809703 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6839 10:02:22.816482 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6840 10:02:22.819659 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6841 10:02:22.823137 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6842 10:02:22.826187 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6843 10:02:22.833428 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6844 10:02:22.836281 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6845 10:02:22.839672 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6846 10:02:22.843071 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6847 10:02:22.849773 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6848 10:02:22.852997 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6849 10:02:22.856551 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6850 10:02:22.859238 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6851 10:02:22.866005 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6852 10:02:22.869596 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6853 10:02:22.872867 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6854 10:02:22.872983 ==
6855 10:02:22.876049 Dram Type= 6, Freq= 0, CH_1, rank 1
6856 10:02:22.882771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6857 10:02:22.882890 ==
6858 10:02:22.882989 DQS Delay:
6859 10:02:22.886104 DQS0 = 35, DQS1 = 35
6860 10:02:22.886224 DQM Delay:
6861 10:02:22.886327 DQM0 = 17, DQM1 = 13
6862 10:02:22.889464 DQ Delay:
6863 10:02:22.892586 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6864 10:02:22.896229 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6865 10:02:22.899460 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6866 10:02:22.902436 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6867 10:02:22.902547
6868 10:02:22.902649
6869 10:02:22.902749 ==
6870 10:02:22.905951 Dram Type= 6, Freq= 0, CH_1, rank 1
6871 10:02:22.909351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6872 10:02:22.909464 ==
6873 10:02:22.909582
6874 10:02:22.909689
6875 10:02:22.912486 TX Vref Scan disable
6876 10:02:22.912615 == TX Byte 0 ==
6877 10:02:22.916272 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6878 10:02:22.922611 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6879 10:02:22.922738 == TX Byte 1 ==
6880 10:02:22.925651 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6881 10:02:22.932277 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6882 10:02:22.932406 ==
6883 10:02:22.936166 Dram Type= 6, Freq= 0, CH_1, rank 1
6884 10:02:22.939347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6885 10:02:22.939434 ==
6886 10:02:22.939534
6887 10:02:22.939647
6888 10:02:22.942666 TX Vref Scan disable
6889 10:02:22.942741 == TX Byte 0 ==
6890 10:02:22.949166 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6891 10:02:22.952699 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6892 10:02:22.952817 == TX Byte 1 ==
6893 10:02:22.955937 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6894 10:02:22.962713 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6895 10:02:22.962836
6896 10:02:22.962932 [DATLAT]
6897 10:02:22.965835 Freq=400, CH1 RK1
6898 10:02:22.965941
6899 10:02:22.966033 DATLAT Default: 0xe
6900 10:02:22.968918 0, 0xFFFF, sum = 0
6901 10:02:22.969030 1, 0xFFFF, sum = 0
6902 10:02:22.972152 2, 0xFFFF, sum = 0
6903 10:02:22.972256 3, 0xFFFF, sum = 0
6904 10:02:22.975776 4, 0xFFFF, sum = 0
6905 10:02:22.975887 5, 0xFFFF, sum = 0
6906 10:02:22.978848 6, 0xFFFF, sum = 0
6907 10:02:22.978949 7, 0xFFFF, sum = 0
6908 10:02:22.982233 8, 0xFFFF, sum = 0
6909 10:02:22.982343 9, 0xFFFF, sum = 0
6910 10:02:22.986098 10, 0xFFFF, sum = 0
6911 10:02:22.986214 11, 0xFFFF, sum = 0
6912 10:02:22.989027 12, 0xFFFF, sum = 0
6913 10:02:22.989138 13, 0x0, sum = 1
6914 10:02:22.992219 14, 0x0, sum = 2
6915 10:02:22.992329 15, 0x0, sum = 3
6916 10:02:22.995364 16, 0x0, sum = 4
6917 10:02:22.995480 best_step = 14
6918 10:02:22.995573
6919 10:02:22.995671 ==
6920 10:02:22.999276 Dram Type= 6, Freq= 0, CH_1, rank 1
6921 10:02:23.005702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6922 10:02:23.005817 ==
6923 10:02:23.005932 RX Vref Scan: 0
6924 10:02:23.006024
6925 10:02:23.008908 RX Vref 0 -> 0, step: 1
6926 10:02:23.009007
6927 10:02:23.012096 RX Delay -311 -> 252, step: 8
6928 10:02:23.018898 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6929 10:02:23.022037 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6930 10:02:23.025828 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6931 10:02:23.028908 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6932 10:02:23.035607 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6933 10:02:23.039099 iDelay=217, Bit 5, Center -4 (-223 ~ 216) 440
6934 10:02:23.042422 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6935 10:02:23.045550 iDelay=217, Bit 7, Center -16 (-239 ~ 208) 448
6936 10:02:23.048777 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6937 10:02:23.055581 iDelay=217, Bit 9, Center -28 (-247 ~ 192) 440
6938 10:02:23.058545 iDelay=217, Bit 10, Center -16 (-239 ~ 208) 448
6939 10:02:23.061991 iDelay=217, Bit 11, Center -24 (-247 ~ 200) 448
6940 10:02:23.068598 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6941 10:02:23.071926 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6942 10:02:23.075586 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6943 10:02:23.078751 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6944 10:02:23.078859 ==
6945 10:02:23.081794 Dram Type= 6, Freq= 0, CH_1, rank 1
6946 10:02:23.088428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6947 10:02:23.088543 ==
6948 10:02:23.088639 DQS Delay:
6949 10:02:23.091851 DQS0 = 28, DQS1 = 32
6950 10:02:23.091956 DQM Delay:
6951 10:02:23.095162 DQM0 = 11, DQM1 = 12
6952 10:02:23.095271 DQ Delay:
6953 10:02:23.098446 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
6954 10:02:23.101522 DQ4 =8, DQ5 =24, DQ6 =20, DQ7 =12
6955 10:02:23.105330 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6956 10:02:23.108417 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
6957 10:02:23.108526
6958 10:02:23.108627
6959 10:02:23.115186 [DQSOSCAuto] RK1, (LSB)MR18= 0xc053, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 386 ps
6960 10:02:23.118767 CH1 RK1: MR19=C0C, MR18=C053
6961 10:02:23.125215 CH1_RK1: MR19=0xC0C, MR18=0xC053, DQSOSC=386, MR23=63, INC=396, DEC=264
6962 10:02:23.128411 [RxdqsGatingPostProcess] freq 400
6963 10:02:23.131927 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6964 10:02:23.135062 best DQS0 dly(2T, 0.5T) = (0, 10)
6965 10:02:23.138415 best DQS1 dly(2T, 0.5T) = (0, 10)
6966 10:02:23.142140 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6967 10:02:23.145624 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6968 10:02:23.148619 best DQS0 dly(2T, 0.5T) = (0, 10)
6969 10:02:23.151924 best DQS1 dly(2T, 0.5T) = (0, 10)
6970 10:02:23.155777 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6971 10:02:23.158845 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6972 10:02:23.161922 Pre-setting of DQS Precalculation
6973 10:02:23.165729 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6974 10:02:23.172074 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6975 10:02:23.181993 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6976 10:02:23.182122
6977 10:02:23.182196
6978 10:02:23.185279 [Calibration Summary] 800 Mbps
6979 10:02:23.185366 CH 0, Rank 0
6980 10:02:23.188608 SW Impedance : PASS
6981 10:02:23.188694 DUTY Scan : NO K
6982 10:02:23.191665 ZQ Calibration : PASS
6983 10:02:23.194880 Jitter Meter : NO K
6984 10:02:23.194964 CBT Training : PASS
6985 10:02:23.198570 Write leveling : PASS
6986 10:02:23.198657 RX DQS gating : PASS
6987 10:02:23.201582 RX DQ/DQS(RDDQC) : PASS
6988 10:02:23.205072 TX DQ/DQS : PASS
6989 10:02:23.205158 RX DATLAT : PASS
6990 10:02:23.208354 RX DQ/DQS(Engine): PASS
6991 10:02:23.211514 TX OE : NO K
6992 10:02:23.211601 All Pass.
6993 10:02:23.211703
6994 10:02:23.211794 CH 0, Rank 1
6995 10:02:23.214710 SW Impedance : PASS
6996 10:02:23.217800 DUTY Scan : NO K
6997 10:02:23.217899 ZQ Calibration : PASS
6998 10:02:23.221542 Jitter Meter : NO K
6999 10:02:23.224653 CBT Training : PASS
7000 10:02:23.224839 Write leveling : NO K
7001 10:02:23.228067 RX DQS gating : PASS
7002 10:02:23.231466 RX DQ/DQS(RDDQC) : PASS
7003 10:02:23.231623 TX DQ/DQS : PASS
7004 10:02:23.234939 RX DATLAT : PASS
7005 10:02:23.238122 RX DQ/DQS(Engine): PASS
7006 10:02:23.238233 TX OE : NO K
7007 10:02:23.241121 All Pass.
7008 10:02:23.241228
7009 10:02:23.241336 CH 1, Rank 0
7010 10:02:23.244075 SW Impedance : PASS
7011 10:02:23.244197 DUTY Scan : NO K
7012 10:02:23.247571 ZQ Calibration : PASS
7013 10:02:23.251226 Jitter Meter : NO K
7014 10:02:23.251351 CBT Training : PASS
7015 10:02:23.254069 Write leveling : PASS
7016 10:02:23.257636 RX DQS gating : PASS
7017 10:02:23.257721 RX DQ/DQS(RDDQC) : PASS
7018 10:02:23.261130 TX DQ/DQS : PASS
7019 10:02:23.264298 RX DATLAT : PASS
7020 10:02:23.264379 RX DQ/DQS(Engine): PASS
7021 10:02:23.267428 TX OE : NO K
7022 10:02:23.267506 All Pass.
7023 10:02:23.267571
7024 10:02:23.271249 CH 1, Rank 1
7025 10:02:23.271369 SW Impedance : PASS
7026 10:02:23.274281 DUTY Scan : NO K
7027 10:02:23.274394 ZQ Calibration : PASS
7028 10:02:23.277215 Jitter Meter : NO K
7029 10:02:23.280789 CBT Training : PASS
7030 10:02:23.280873 Write leveling : NO K
7031 10:02:23.284246 RX DQS gating : PASS
7032 10:02:23.287519 RX DQ/DQS(RDDQC) : PASS
7033 10:02:23.287601 TX DQ/DQS : PASS
7034 10:02:23.290698 RX DATLAT : PASS
7035 10:02:23.293827 RX DQ/DQS(Engine): PASS
7036 10:02:23.293915 TX OE : NO K
7037 10:02:23.297640 All Pass.
7038 10:02:23.297721
7039 10:02:23.297794 DramC Write-DBI off
7040 10:02:23.300957 PER_BANK_REFRESH: Hybrid Mode
7041 10:02:23.303952 TX_TRACKING: ON
7042 10:02:23.310689 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7043 10:02:23.314242 [FAST_K] Save calibration result to emmc
7044 10:02:23.317196 dramc_set_vcore_voltage set vcore to 725000
7045 10:02:23.320605 Read voltage for 1600, 0
7046 10:02:23.320705 Vio18 = 0
7047 10:02:23.323919 Vcore = 725000
7048 10:02:23.324035 Vdram = 0
7049 10:02:23.324110 Vddq = 0
7050 10:02:23.327162 Vmddr = 0
7051 10:02:23.330846 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7052 10:02:23.337759 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7053 10:02:23.337859 MEM_TYPE=3, freq_sel=13
7054 10:02:23.340416 sv_algorithm_assistance_LP4_3733
7055 10:02:23.347452 ============ PULL DRAM RESETB DOWN ============
7056 10:02:23.350949 ========== PULL DRAM RESETB DOWN end =========
7057 10:02:23.353946 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7058 10:02:23.357477 ===================================
7059 10:02:23.360916 LPDDR4 DRAM CONFIGURATION
7060 10:02:23.363907 ===================================
7061 10:02:23.364022 EX_ROW_EN[0] = 0x0
7062 10:02:23.367156 EX_ROW_EN[1] = 0x0
7063 10:02:23.370651 LP4Y_EN = 0x0
7064 10:02:23.370735 WORK_FSP = 0x1
7065 10:02:23.373560 WL = 0x5
7066 10:02:23.373653 RL = 0x5
7067 10:02:23.377317 BL = 0x2
7068 10:02:23.377422 RPST = 0x0
7069 10:02:23.380508 RD_PRE = 0x0
7070 10:02:23.380586 WR_PRE = 0x1
7071 10:02:23.383982 WR_PST = 0x1
7072 10:02:23.384062 DBI_WR = 0x0
7073 10:02:23.386919 DBI_RD = 0x0
7074 10:02:23.387002 OTF = 0x1
7075 10:02:23.390697 ===================================
7076 10:02:23.393837 ===================================
7077 10:02:23.397139 ANA top config
7078 10:02:23.400204 ===================================
7079 10:02:23.400293 DLL_ASYNC_EN = 0
7080 10:02:23.404032 ALL_SLAVE_EN = 0
7081 10:02:23.407034 NEW_RANK_MODE = 1
7082 10:02:23.410329 DLL_IDLE_MODE = 1
7083 10:02:23.413505 LP45_APHY_COMB_EN = 1
7084 10:02:23.413619 TX_ODT_DIS = 0
7085 10:02:23.417251 NEW_8X_MODE = 1
7086 10:02:23.420464 ===================================
7087 10:02:23.423448 ===================================
7088 10:02:23.426846 data_rate = 3200
7089 10:02:23.430281 CKR = 1
7090 10:02:23.433920 DQ_P2S_RATIO = 8
7091 10:02:23.437057 ===================================
7092 10:02:23.437153 CA_P2S_RATIO = 8
7093 10:02:23.440140 DQ_CA_OPEN = 0
7094 10:02:23.443835 DQ_SEMI_OPEN = 0
7095 10:02:23.446904 CA_SEMI_OPEN = 0
7096 10:02:23.449911 CA_FULL_RATE = 0
7097 10:02:23.453590 DQ_CKDIV4_EN = 0
7098 10:02:23.453714 CA_CKDIV4_EN = 0
7099 10:02:23.457225 CA_PREDIV_EN = 0
7100 10:02:23.460112 PH8_DLY = 12
7101 10:02:23.463450 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7102 10:02:23.467559 DQ_AAMCK_DIV = 4
7103 10:02:23.470276 CA_AAMCK_DIV = 4
7104 10:02:23.470363 CA_ADMCK_DIV = 4
7105 10:02:23.473927 DQ_TRACK_CA_EN = 0
7106 10:02:23.476859 CA_PICK = 1600
7107 10:02:23.480505 CA_MCKIO = 1600
7108 10:02:23.483346 MCKIO_SEMI = 0
7109 10:02:23.486912 PLL_FREQ = 3068
7110 10:02:23.489873 DQ_UI_PI_RATIO = 32
7111 10:02:23.493594 CA_UI_PI_RATIO = 0
7112 10:02:23.493676 ===================================
7113 10:02:23.496625 ===================================
7114 10:02:23.500279 memory_type:LPDDR4
7115 10:02:23.503410 GP_NUM : 10
7116 10:02:23.503495 SRAM_EN : 1
7117 10:02:23.506727 MD32_EN : 0
7118 10:02:23.510475 ===================================
7119 10:02:23.513631 [ANA_INIT] >>>>>>>>>>>>>>
7120 10:02:23.516775 <<<<<< [CONFIGURE PHASE]: ANA_TX
7121 10:02:23.519943 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7122 10:02:23.523675 ===================================
7123 10:02:23.523760 data_rate = 3200,PCW = 0X7600
7124 10:02:23.526821 ===================================
7125 10:02:23.530029 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7126 10:02:23.536758 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7127 10:02:23.543515 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7128 10:02:23.546692 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7129 10:02:23.550260 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7130 10:02:23.553391 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7131 10:02:23.556552 [ANA_INIT] flow start
7132 10:02:23.560193 [ANA_INIT] PLL >>>>>>>>
7133 10:02:23.560277 [ANA_INIT] PLL <<<<<<<<
7134 10:02:23.563090 [ANA_INIT] MIDPI >>>>>>>>
7135 10:02:23.566792 [ANA_INIT] MIDPI <<<<<<<<
7136 10:02:23.566908 [ANA_INIT] DLL >>>>>>>>
7137 10:02:23.569797 [ANA_INIT] DLL <<<<<<<<
7138 10:02:23.573137 [ANA_INIT] flow end
7139 10:02:23.576671 ============ LP4 DIFF to SE enter ============
7140 10:02:23.579831 ============ LP4 DIFF to SE exit ============
7141 10:02:23.583492 [ANA_INIT] <<<<<<<<<<<<<
7142 10:02:23.586624 [Flow] Enable top DCM control >>>>>
7143 10:02:23.589639 [Flow] Enable top DCM control <<<<<
7144 10:02:23.593070 Enable DLL master slave shuffle
7145 10:02:23.596485 ==============================================================
7146 10:02:23.599821 Gating Mode config
7147 10:02:23.603485 ==============================================================
7148 10:02:23.606405 Config description:
7149 10:02:23.616349 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7150 10:02:23.622935 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7151 10:02:23.626619 SELPH_MODE 0: By rank 1: By Phase
7152 10:02:23.632887 ==============================================================
7153 10:02:23.636597 GAT_TRACK_EN = 1
7154 10:02:23.639801 RX_GATING_MODE = 2
7155 10:02:23.642786 RX_GATING_TRACK_MODE = 2
7156 10:02:23.646667 SELPH_MODE = 1
7157 10:02:23.649451 PICG_EARLY_EN = 1
7158 10:02:23.652864 VALID_LAT_VALUE = 1
7159 10:02:23.656201 ==============================================================
7160 10:02:23.659572 Enter into Gating configuration >>>>
7161 10:02:23.662896 Exit from Gating configuration <<<<
7162 10:02:23.665916 Enter into DVFS_PRE_config >>>>>
7163 10:02:23.675916 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7164 10:02:23.679491 Exit from DVFS_PRE_config <<<<<
7165 10:02:23.682884 Enter into PICG configuration >>>>
7166 10:02:23.686182 Exit from PICG configuration <<<<
7167 10:02:23.689802 [RX_INPUT] configuration >>>>>
7168 10:02:23.692849 [RX_INPUT] configuration <<<<<
7169 10:02:23.699642 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7170 10:02:23.702932 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7171 10:02:23.709358 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7172 10:02:23.715995 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7173 10:02:23.722747 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7174 10:02:23.729137 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7175 10:02:23.732441 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7176 10:02:23.736376 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7177 10:02:23.739453 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7178 10:02:23.745891 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7179 10:02:23.749766 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7180 10:02:23.752892 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7181 10:02:23.755899 ===================================
7182 10:02:23.759014 LPDDR4 DRAM CONFIGURATION
7183 10:02:23.762333 ===================================
7184 10:02:23.762443 EX_ROW_EN[0] = 0x0
7185 10:02:23.765888 EX_ROW_EN[1] = 0x0
7186 10:02:23.765993 LP4Y_EN = 0x0
7187 10:02:23.769029 WORK_FSP = 0x1
7188 10:02:23.772843 WL = 0x5
7189 10:02:23.772932 RL = 0x5
7190 10:02:23.775931 BL = 0x2
7191 10:02:23.776047 RPST = 0x0
7192 10:02:23.779332 RD_PRE = 0x0
7193 10:02:23.779443 WR_PRE = 0x1
7194 10:02:23.782559 WR_PST = 0x1
7195 10:02:23.782646 DBI_WR = 0x0
7196 10:02:23.785922 DBI_RD = 0x0
7197 10:02:23.786008 OTF = 0x1
7198 10:02:23.789166 ===================================
7199 10:02:23.792531 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7200 10:02:23.799121 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7201 10:02:23.802308 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7202 10:02:23.805812 ===================================
7203 10:02:23.808911 LPDDR4 DRAM CONFIGURATION
7204 10:02:23.812328 ===================================
7205 10:02:23.812414 EX_ROW_EN[0] = 0x10
7206 10:02:23.816010 EX_ROW_EN[1] = 0x0
7207 10:02:23.816103 LP4Y_EN = 0x0
7208 10:02:23.818842 WORK_FSP = 0x1
7209 10:02:23.818952 WL = 0x5
7210 10:02:23.822299 RL = 0x5
7211 10:02:23.822392 BL = 0x2
7212 10:02:23.826032 RPST = 0x0
7213 10:02:23.826122 RD_PRE = 0x0
7214 10:02:23.828832 WR_PRE = 0x1
7215 10:02:23.832176 WR_PST = 0x1
7216 10:02:23.832275 DBI_WR = 0x0
7217 10:02:23.835468 DBI_RD = 0x0
7218 10:02:23.835553 OTF = 0x1
7219 10:02:23.838664 ===================================
7220 10:02:23.845540 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7221 10:02:23.845659 ==
7222 10:02:23.848678 Dram Type= 6, Freq= 0, CH_0, rank 0
7223 10:02:23.852671 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7224 10:02:23.852770 ==
7225 10:02:23.855856 [Duty_Offset_Calibration]
7226 10:02:23.855934 B0:2 B1:1 CA:1
7227 10:02:23.858841
7228 10:02:23.861990 [DutyScan_Calibration_Flow] k_type=0
7229 10:02:23.870128
7230 10:02:23.870215 ==CLK 0==
7231 10:02:23.873846 Final CLK duty delay cell = 0
7232 10:02:23.877043 [0] MAX Duty = 5156%(X100), DQS PI = 22
7233 10:02:23.880421 [0] MIN Duty = 4907%(X100), DQS PI = 0
7234 10:02:23.880538 [0] AVG Duty = 5031%(X100)
7235 10:02:23.883520
7236 10:02:23.887158 CH0 CLK Duty spec in!! Max-Min= 249%
7237 10:02:23.890323 [DutyScan_Calibration_Flow] ====Done====
7238 10:02:23.890406
7239 10:02:23.893345 [DutyScan_Calibration_Flow] k_type=1
7240 10:02:23.909409
7241 10:02:23.909525 ==DQS 0 ==
7242 10:02:23.912939 Final DQS duty delay cell = -4
7243 10:02:23.916242 [-4] MAX Duty = 5125%(X100), DQS PI = 26
7244 10:02:23.919119 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7245 10:02:23.922556 [-4] AVG Duty = 4891%(X100)
7246 10:02:23.922652
7247 10:02:23.922720 ==DQS 1 ==
7248 10:02:23.926284 Final DQS duty delay cell = 0
7249 10:02:23.929317 [0] MAX Duty = 5187%(X100), DQS PI = 20
7250 10:02:23.932546 [0] MIN Duty = 5031%(X100), DQS PI = 52
7251 10:02:23.935969 [0] AVG Duty = 5109%(X100)
7252 10:02:23.936056
7253 10:02:23.939277 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7254 10:02:23.939357
7255 10:02:23.942881 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7256 10:02:23.946397 [DutyScan_Calibration_Flow] ====Done====
7257 10:02:23.946477
7258 10:02:23.949801 [DutyScan_Calibration_Flow] k_type=3
7259 10:02:23.966460
7260 10:02:23.966570 ==DQM 0 ==
7261 10:02:23.969599 Final DQM duty delay cell = 0
7262 10:02:23.972782 [0] MAX Duty = 5218%(X100), DQS PI = 34
7263 10:02:23.976035 [0] MIN Duty = 4907%(X100), DQS PI = 56
7264 10:02:23.979630 [0] AVG Duty = 5062%(X100)
7265 10:02:23.979716
7266 10:02:23.979781 ==DQM 1 ==
7267 10:02:23.982586 Final DQM duty delay cell = -4
7268 10:02:23.986315 [-4] MAX Duty = 5000%(X100), DQS PI = 62
7269 10:02:23.989486 [-4] MIN Duty = 4813%(X100), DQS PI = 50
7270 10:02:23.992831 [-4] AVG Duty = 4906%(X100)
7271 10:02:23.992937
7272 10:02:23.995774 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7273 10:02:23.995851
7274 10:02:23.999014 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7275 10:02:24.002763 [DutyScan_Calibration_Flow] ====Done====
7276 10:02:24.002844
7277 10:02:24.005859 [DutyScan_Calibration_Flow] k_type=2
7278 10:02:24.023774
7279 10:02:24.023903 ==DQ 0 ==
7280 10:02:24.026796 Final DQ duty delay cell = 0
7281 10:02:24.030615 [0] MAX Duty = 5062%(X100), DQS PI = 24
7282 10:02:24.033416 [0] MIN Duty = 4907%(X100), DQS PI = 0
7283 10:02:24.033501 [0] AVG Duty = 4984%(X100)
7284 10:02:24.033566
7285 10:02:24.036775 ==DQ 1 ==
7286 10:02:24.040443 Final DQ duty delay cell = 0
7287 10:02:24.043512 [0] MAX Duty = 5156%(X100), DQS PI = 22
7288 10:02:24.046707 [0] MIN Duty = 4938%(X100), DQS PI = 34
7289 10:02:24.046819 [0] AVG Duty = 5047%(X100)
7290 10:02:24.046915
7291 10:02:24.050273 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7292 10:02:24.053831
7293 10:02:24.056902 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7294 10:02:24.060098 [DutyScan_Calibration_Flow] ====Done====
7295 10:02:24.060255 ==
7296 10:02:24.063507 Dram Type= 6, Freq= 0, CH_1, rank 0
7297 10:02:24.067073 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7298 10:02:24.067201 ==
7299 10:02:24.069971 [Duty_Offset_Calibration]
7300 10:02:24.070081 B0:1 B1:0 CA:0
7301 10:02:24.070177
7302 10:02:24.073137 [DutyScan_Calibration_Flow] k_type=0
7303 10:02:24.083192
7304 10:02:24.083334 ==CLK 0==
7305 10:02:24.086289 Final CLK duty delay cell = -4
7306 10:02:24.089902 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7307 10:02:24.093431 [-4] MIN Duty = 4844%(X100), DQS PI = 2
7308 10:02:24.096608 [-4] AVG Duty = 4922%(X100)
7309 10:02:24.096726
7310 10:02:24.099701 CH1 CLK Duty spec in!! Max-Min= 156%
7311 10:02:24.102887 [DutyScan_Calibration_Flow] ====Done====
7312 10:02:24.103004
7313 10:02:24.106116 [DutyScan_Calibration_Flow] k_type=1
7314 10:02:24.123178
7315 10:02:24.123326 ==DQS 0 ==
7316 10:02:24.126292 Final DQS duty delay cell = 0
7317 10:02:24.130104 [0] MAX Duty = 5094%(X100), DQS PI = 28
7318 10:02:24.133268 [0] MIN Duty = 4844%(X100), DQS PI = 48
7319 10:02:24.133381 [0] AVG Duty = 4969%(X100)
7320 10:02:24.136732
7321 10:02:24.136842 ==DQS 1 ==
7322 10:02:24.139753 Final DQS duty delay cell = 0
7323 10:02:24.143052 [0] MAX Duty = 5281%(X100), DQS PI = 18
7324 10:02:24.146404 [0] MIN Duty = 4969%(X100), DQS PI = 6
7325 10:02:24.146518 [0] AVG Duty = 5125%(X100)
7326 10:02:24.149906
7327 10:02:24.152940 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7328 10:02:24.153061
7329 10:02:24.156644 CH1 DQS 1 Duty spec in!! Max-Min= 312%
7330 10:02:24.159789 [DutyScan_Calibration_Flow] ====Done====
7331 10:02:24.159901
7332 10:02:24.162930 [DutyScan_Calibration_Flow] k_type=3
7333 10:02:24.179950
7334 10:02:24.180085 ==DQM 0 ==
7335 10:02:24.183171 Final DQM duty delay cell = 0
7336 10:02:24.186833 [0] MAX Duty = 5218%(X100), DQS PI = 18
7337 10:02:24.189744 [0] MIN Duty = 4969%(X100), DQS PI = 48
7338 10:02:24.193165 [0] AVG Duty = 5093%(X100)
7339 10:02:24.193280
7340 10:02:24.193376 ==DQM 1 ==
7341 10:02:24.196323 Final DQM duty delay cell = 0
7342 10:02:24.199976 [0] MAX Duty = 5093%(X100), DQS PI = 16
7343 10:02:24.203659 [0] MIN Duty = 4907%(X100), DQS PI = 34
7344 10:02:24.206937 [0] AVG Duty = 5000%(X100)
7345 10:02:24.207053
7346 10:02:24.210172 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7347 10:02:24.210285
7348 10:02:24.213346 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7349 10:02:24.216756 [DutyScan_Calibration_Flow] ====Done====
7350 10:02:24.216879
7351 10:02:24.219877 [DutyScan_Calibration_Flow] k_type=2
7352 10:02:24.236394
7353 10:02:24.236546 ==DQ 0 ==
7354 10:02:24.239583 Final DQ duty delay cell = -4
7355 10:02:24.242698 [-4] MAX Duty = 5062%(X100), DQS PI = 12
7356 10:02:24.245838 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7357 10:02:24.249476 [-4] AVG Duty = 4968%(X100)
7358 10:02:24.249597
7359 10:02:24.249694 ==DQ 1 ==
7360 10:02:24.252602 Final DQ duty delay cell = 0
7361 10:02:24.256186 [0] MAX Duty = 5124%(X100), DQS PI = 16
7362 10:02:24.259235 [0] MIN Duty = 4969%(X100), DQS PI = 8
7363 10:02:24.262572 [0] AVG Duty = 5046%(X100)
7364 10:02:24.262684
7365 10:02:24.266038 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7366 10:02:24.266156
7367 10:02:24.269276 CH1 DQ 1 Duty spec in!! Max-Min= 155%
7368 10:02:24.272737 [DutyScan_Calibration_Flow] ====Done====
7369 10:02:24.275935 nWR fixed to 30
7370 10:02:24.279032 [ModeRegInit_LP4] CH0 RK0
7371 10:02:24.279124 [ModeRegInit_LP4] CH0 RK1
7372 10:02:24.282188 [ModeRegInit_LP4] CH1 RK0
7373 10:02:24.286105 [ModeRegInit_LP4] CH1 RK1
7374 10:02:24.286198 match AC timing 5
7375 10:02:24.292406 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7376 10:02:24.296129 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7377 10:02:24.299069 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7378 10:02:24.305997 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7379 10:02:24.309248 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7380 10:02:24.309365 [MiockJmeterHQA]
7381 10:02:24.309462
7382 10:02:24.312525 [DramcMiockJmeter] u1RxGatingPI = 0
7383 10:02:24.315744 0 : 4363, 4137
7384 10:02:24.315868 4 : 4363, 4137
7385 10:02:24.319023 8 : 4253, 4026
7386 10:02:24.319139 12 : 4252, 4027
7387 10:02:24.319238 16 : 4252, 4027
7388 10:02:24.321967 20 : 4255, 4029
7389 10:02:24.322085 24 : 4252, 4027
7390 10:02:24.325710 28 : 4363, 4137
7391 10:02:24.325831 32 : 4363, 4137
7392 10:02:24.328816 36 : 4252, 4027
7393 10:02:24.328939 40 : 4252, 4027
7394 10:02:24.332030 44 : 4252, 4026
7395 10:02:24.332147 48 : 4254, 4030
7396 10:02:24.332247 52 : 4253, 4029
7397 10:02:24.335535 56 : 4361, 4138
7398 10:02:24.335650 60 : 4250, 4026
7399 10:02:24.338957 64 : 4250, 4026
7400 10:02:24.339082 68 : 4250, 4027
7401 10:02:24.342123 72 : 4253, 4029
7402 10:02:24.342241 76 : 4249, 4027
7403 10:02:24.345797 80 : 4360, 4137
7404 10:02:24.345916 84 : 4361, 4137
7405 10:02:24.346017 88 : 4250, 219
7406 10:02:24.348999 92 : 4250, 0
7407 10:02:24.349116 96 : 4252, 0
7408 10:02:24.352169 100 : 4360, 0
7409 10:02:24.352262 104 : 4361, 0
7410 10:02:24.352331 108 : 4363, 0
7411 10:02:24.355401 112 : 4253, 0
7412 10:02:24.355493 116 : 4360, 0
7413 10:02:24.355569 120 : 4361, 0
7414 10:02:24.359140 124 : 4250, 0
7415 10:02:24.359222 128 : 4250, 0
7416 10:02:24.361987 132 : 4250, 0
7417 10:02:24.362075 136 : 4253, 0
7418 10:02:24.362141 140 : 4252, 0
7419 10:02:24.365442 144 : 4250, 0
7420 10:02:24.365561 148 : 4253, 0
7421 10:02:24.368987 152 : 4360, 0
7422 10:02:24.369072 156 : 4361, 0
7423 10:02:24.369146 160 : 4250, 0
7424 10:02:24.371813 164 : 4250, 0
7425 10:02:24.371911 168 : 4250, 0
7426 10:02:24.375494 172 : 4250, 0
7427 10:02:24.375579 176 : 4250, 0
7428 10:02:24.375653 180 : 4252, 0
7429 10:02:24.378848 184 : 4250, 0
7430 10:02:24.378938 188 : 4253, 0
7431 10:02:24.379005 192 : 4250, 0
7432 10:02:24.381991 196 : 4250, 0
7433 10:02:24.382073 200 : 4252, 0
7434 10:02:24.385598 204 : 4250, 1032
7435 10:02:24.385720 208 : 4250, 3884
7436 10:02:24.389017 212 : 4361, 4137
7437 10:02:24.389127 216 : 4360, 4138
7438 10:02:24.392114 220 : 4249, 4027
7439 10:02:24.392228 224 : 4250, 4026
7440 10:02:24.395162 228 : 4363, 4140
7441 10:02:24.395277 232 : 4250, 4027
7442 10:02:24.395377 236 : 4250, 4027
7443 10:02:24.399036 240 : 4250, 4026
7444 10:02:24.399152 244 : 4253, 4029
7445 10:02:24.402234 248 : 4250, 4027
7446 10:02:24.402351 252 : 4249, 4027
7447 10:02:24.405140 256 : 4360, 4137
7448 10:02:24.405250 260 : 4250, 4027
7449 10:02:24.408977 264 : 4250, 4026
7450 10:02:24.409089 268 : 4361, 4138
7451 10:02:24.412075 272 : 4250, 4027
7452 10:02:24.412194 276 : 4250, 4026
7453 10:02:24.415170 280 : 4363, 4140
7454 10:02:24.415288 284 : 4250, 4027
7455 10:02:24.415386 288 : 4250, 4027
7456 10:02:24.418642 292 : 4250, 4026
7457 10:02:24.418758 296 : 4253, 4029
7458 10:02:24.422005 300 : 4250, 4026
7459 10:02:24.422129 304 : 4250, 4027
7460 10:02:24.424898 308 : 4249, 4025
7461 10:02:24.425018 312 : 4253, 2200
7462 10:02:24.428414 316 : 4250, 20
7463 10:02:24.428536
7464 10:02:24.428633 MIOCK jitter meter ch=0
7465 10:02:24.431962
7466 10:02:24.432067 1T = (316-88) = 228 dly cells
7467 10:02:24.438672 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps
7468 10:02:24.438786 ==
7469 10:02:24.441538 Dram Type= 6, Freq= 0, CH_0, rank 0
7470 10:02:24.445120 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7471 10:02:24.445233 ==
7472 10:02:24.451419 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7473 10:02:24.455028 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7474 10:02:24.461275 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7475 10:02:24.464863 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7476 10:02:24.475466 [CA 0] Center 43 (13~74) winsize 62
7477 10:02:24.478359 [CA 1] Center 43 (13~74) winsize 62
7478 10:02:24.482004 [CA 2] Center 38 (9~68) winsize 60
7479 10:02:24.484824 [CA 3] Center 38 (8~68) winsize 61
7480 10:02:24.488397 [CA 4] Center 37 (7~67) winsize 61
7481 10:02:24.491890 [CA 5] Center 36 (7~65) winsize 59
7482 10:02:24.492008
7483 10:02:24.494979 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7484 10:02:24.495084
7485 10:02:24.498275 [CATrainingPosCal] consider 1 rank data
7486 10:02:24.502128 u2DelayCellTimex100 = 285/100 ps
7487 10:02:24.505305 CA0 delay=43 (13~74),Diff = 7 PI (23 cell)
7488 10:02:24.511647 CA1 delay=43 (13~74),Diff = 7 PI (23 cell)
7489 10:02:24.514842 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
7490 10:02:24.518450 CA3 delay=38 (8~68),Diff = 2 PI (6 cell)
7491 10:02:24.521612 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
7492 10:02:24.525010 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7493 10:02:24.525123
7494 10:02:24.528555 CA PerBit enable=1, Macro0, CA PI delay=36
7495 10:02:24.528673
7496 10:02:24.531614 [CBTSetCACLKResult] CA Dly = 36
7497 10:02:24.534788 CS Dly: 9 (0~40)
7498 10:02:24.538486 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7499 10:02:24.541413 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7500 10:02:24.541531 ==
7501 10:02:24.544936 Dram Type= 6, Freq= 0, CH_0, rank 1
7502 10:02:24.548460 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7503 10:02:24.548579 ==
7504 10:02:24.554962 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7505 10:02:24.558093 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7506 10:02:24.564949 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7507 10:02:24.568248 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7508 10:02:24.578231 [CA 0] Center 42 (12~73) winsize 62
7509 10:02:24.581778 [CA 1] Center 42 (12~73) winsize 62
7510 10:02:24.584813 [CA 2] Center 38 (8~68) winsize 61
7511 10:02:24.588433 [CA 3] Center 38 (8~68) winsize 61
7512 10:02:24.591426 [CA 4] Center 35 (6~65) winsize 60
7513 10:02:24.595169 [CA 5] Center 35 (5~65) winsize 61
7514 10:02:24.595249
7515 10:02:24.598640 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7516 10:02:24.598732
7517 10:02:24.601641 [CATrainingPosCal] consider 2 rank data
7518 10:02:24.604807 u2DelayCellTimex100 = 285/100 ps
7519 10:02:24.608454 CA0 delay=43 (13~73),Diff = 7 PI (23 cell)
7520 10:02:24.614854 CA1 delay=43 (13~73),Diff = 7 PI (23 cell)
7521 10:02:24.617965 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
7522 10:02:24.621659 CA3 delay=38 (8~68),Diff = 2 PI (6 cell)
7523 10:02:24.624879 CA4 delay=36 (7~65),Diff = 0 PI (0 cell)
7524 10:02:24.628326 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7525 10:02:24.628448
7526 10:02:24.631568 CA PerBit enable=1, Macro0, CA PI delay=36
7527 10:02:24.631688
7528 10:02:24.634533 [CBTSetCACLKResult] CA Dly = 36
7529 10:02:24.638285 CS Dly: 9 (0~41)
7530 10:02:24.641508 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7531 10:02:24.644799 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7532 10:02:24.644914
7533 10:02:24.647919 ----->DramcWriteLeveling(PI) begin...
7534 10:02:24.648032 ==
7535 10:02:24.651553 Dram Type= 6, Freq= 0, CH_0, rank 0
7536 10:02:24.654550 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7537 10:02:24.657916 ==
7538 10:02:24.658032 Write leveling (Byte 0): 34 => 34
7539 10:02:24.661443 Write leveling (Byte 1): 26 => 26
7540 10:02:24.664602 DramcWriteLeveling(PI) end<-----
7541 10:02:24.664710
7542 10:02:24.664803 ==
7543 10:02:24.667750 Dram Type= 6, Freq= 0, CH_0, rank 0
7544 10:02:24.674603 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7545 10:02:24.674725 ==
7546 10:02:24.677660 [Gating] SW mode calibration
7547 10:02:24.684545 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7548 10:02:24.688029 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7549 10:02:24.694538 1 4 0 | B1->B0 | 2323 2424 | 0 1 | (0 0) (1 1)
7550 10:02:24.697593 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7551 10:02:24.701244 1 4 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
7552 10:02:24.708023 1 4 12 | B1->B0 | 2323 3635 | 0 1 | (0 0) (1 1)
7553 10:02:24.710943 1 4 16 | B1->B0 | 2323 3838 | 0 1 | (0 0) (1 1)
7554 10:02:24.714617 1 4 20 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
7555 10:02:24.717965 1 4 24 | B1->B0 | 3434 3636 | 1 1 | (1 1) (0 0)
7556 10:02:24.724744 1 4 28 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7557 10:02:24.727871 1 5 0 | B1->B0 | 3434 3838 | 1 1 | (1 1) (0 0)
7558 10:02:24.730903 1 5 4 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7559 10:02:24.737471 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
7560 10:02:24.741303 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7561 10:02:24.744505 1 5 16 | B1->B0 | 3434 2625 | 1 1 | (1 0) (1 0)
7562 10:02:24.750687 1 5 20 | B1->B0 | 2323 2727 | 0 0 | (1 0) (0 0)
7563 10:02:24.754446 1 5 24 | B1->B0 | 2323 2e2d | 0 1 | (0 0) (0 0)
7564 10:02:24.757672 1 5 28 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (0 0)
7565 10:02:24.764308 1 6 0 | B1->B0 | 2323 2f2e | 0 1 | (0 0) (0 0)
7566 10:02:24.767886 1 6 4 | B1->B0 | 2323 2827 | 0 1 | (0 0) (0 0)
7567 10:02:24.770620 1 6 8 | B1->B0 | 2323 302f | 0 1 | (0 0) (0 0)
7568 10:02:24.777558 1 6 12 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
7569 10:02:24.780602 1 6 16 | B1->B0 | 2f2f 4645 | 0 1 | (0 0) (0 0)
7570 10:02:24.784410 1 6 20 | B1->B0 | 4646 4646 | 0 1 | (0 0) (0 0)
7571 10:02:24.790513 1 6 24 | B1->B0 | 4646 4645 | 0 1 | (0 0) (1 1)
7572 10:02:24.794219 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7573 10:02:24.797222 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7574 10:02:24.803830 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7575 10:02:24.807286 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7576 10:02:24.810508 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7577 10:02:24.817542 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7578 10:02:24.820934 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7579 10:02:24.824130 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7580 10:02:24.830586 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7581 10:02:24.834213 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7582 10:02:24.837235 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7583 10:02:24.843797 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7584 10:02:24.847618 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7585 10:02:24.850851 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7586 10:02:24.857159 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7587 10:02:24.860719 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7588 10:02:24.863867 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7589 10:02:24.866938 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7590 10:02:24.873825 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7591 10:02:24.876985 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7592 10:02:24.880586 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7593 10:02:24.887412 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7594 10:02:24.890531 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7595 10:02:24.893696 Total UI for P1: 0, mck2ui 16
7596 10:02:24.896934 best dqsien dly found for B0: ( 1, 9, 14)
7597 10:02:24.900185 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7598 10:02:24.903846 Total UI for P1: 0, mck2ui 16
7599 10:02:24.907061 best dqsien dly found for B1: ( 1, 9, 18)
7600 10:02:24.910396 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7601 10:02:24.913497 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7602 10:02:24.913637
7603 10:02:24.920246 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7604 10:02:24.923863 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7605 10:02:24.926670 [Gating] SW calibration Done
7606 10:02:24.926836 ==
7607 10:02:24.930118 Dram Type= 6, Freq= 0, CH_0, rank 0
7608 10:02:24.933490 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7609 10:02:24.933629 ==
7610 10:02:24.933798 RX Vref Scan: 0
7611 10:02:24.933894
7612 10:02:24.936954 RX Vref 0 -> 0, step: 1
7613 10:02:24.937066
7614 10:02:24.940462 RX Delay 0 -> 252, step: 8
7615 10:02:24.943510 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7616 10:02:24.947075 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7617 10:02:24.953522 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7618 10:02:24.956740 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
7619 10:02:24.959928 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7620 10:02:24.963430 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7621 10:02:24.966602 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7622 10:02:24.969906 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7623 10:02:24.976798 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7624 10:02:24.980309 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
7625 10:02:24.983437 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7626 10:02:24.987186 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7627 10:02:24.990527 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
7628 10:02:24.996881 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
7629 10:02:24.999948 iDelay=200, Bit 14, Center 143 (96 ~ 191) 96
7630 10:02:25.003230 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7631 10:02:25.003343 ==
7632 10:02:25.006463 Dram Type= 6, Freq= 0, CH_0, rank 0
7633 10:02:25.010108 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7634 10:02:25.013170 ==
7635 10:02:25.013284 DQS Delay:
7636 10:02:25.013381 DQS0 = 0, DQS1 = 0
7637 10:02:25.016456 DQM Delay:
7638 10:02:25.016574 DQM0 = 137, DQM1 = 131
7639 10:02:25.020220 DQ Delay:
7640 10:02:25.023280 DQ0 =135, DQ1 =143, DQ2 =131, DQ3 =135
7641 10:02:25.026879 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7642 10:02:25.029895 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =123
7643 10:02:25.033395 DQ12 =135, DQ13 =139, DQ14 =143, DQ15 =135
7644 10:02:25.033504
7645 10:02:25.033610
7646 10:02:25.033705 ==
7647 10:02:25.037012 Dram Type= 6, Freq= 0, CH_0, rank 0
7648 10:02:25.040069 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7649 10:02:25.040181 ==
7650 10:02:25.040280
7651 10:02:25.040373
7652 10:02:25.043282 TX Vref Scan disable
7653 10:02:25.046929 == TX Byte 0 ==
7654 10:02:25.050243 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7655 10:02:25.053179 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7656 10:02:25.056526 == TX Byte 1 ==
7657 10:02:25.059874 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7658 10:02:25.063557 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7659 10:02:25.063680 ==
7660 10:02:25.066626 Dram Type= 6, Freq= 0, CH_0, rank 0
7661 10:02:25.070071 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7662 10:02:25.073308 ==
7663 10:02:25.084514
7664 10:02:25.087648 TX Vref early break, caculate TX vref
7665 10:02:25.091136 TX Vref=16, minBit 0, minWin=23, winSum=381
7666 10:02:25.094347 TX Vref=18, minBit 0, minWin=24, winSum=392
7667 10:02:25.098044 TX Vref=20, minBit 7, minWin=24, winSum=404
7668 10:02:25.100758 TX Vref=22, minBit 0, minWin=24, winSum=410
7669 10:02:25.103933 TX Vref=24, minBit 7, minWin=25, winSum=422
7670 10:02:25.110598 TX Vref=26, minBit 1, minWin=26, winSum=429
7671 10:02:25.114496 TX Vref=28, minBit 1, minWin=25, winSum=422
7672 10:02:25.117669 TX Vref=30, minBit 6, minWin=24, winSum=412
7673 10:02:25.120828 TX Vref=32, minBit 6, minWin=24, winSum=406
7674 10:02:25.127843 [TxChooseVref] Worse bit 1, Min win 26, Win sum 429, Final Vref 26
7675 10:02:25.127974
7676 10:02:25.131000 Final TX Range 0 Vref 26
7677 10:02:25.131122
7678 10:02:25.131221 ==
7679 10:02:25.134054 Dram Type= 6, Freq= 0, CH_0, rank 0
7680 10:02:25.137139 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7681 10:02:25.137259 ==
7682 10:02:25.137359
7683 10:02:25.137466
7684 10:02:25.140977 TX Vref Scan disable
7685 10:02:25.143819 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
7686 10:02:25.147264 == TX Byte 0 ==
7687 10:02:25.150783 u2DelayCellOfst[0]=10 cells (3 PI)
7688 10:02:25.153963 u2DelayCellOfst[1]=13 cells (4 PI)
7689 10:02:25.157478 u2DelayCellOfst[2]=10 cells (3 PI)
7690 10:02:25.160558 u2DelayCellOfst[3]=10 cells (3 PI)
7691 10:02:25.163578 u2DelayCellOfst[4]=6 cells (2 PI)
7692 10:02:25.167223 u2DelayCellOfst[5]=0 cells (0 PI)
7693 10:02:25.167340 u2DelayCellOfst[6]=17 cells (5 PI)
7694 10:02:25.170575 u2DelayCellOfst[7]=17 cells (5 PI)
7695 10:02:25.176801 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7696 10:02:25.180736 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7697 10:02:25.180857 == TX Byte 1 ==
7698 10:02:25.183577 u2DelayCellOfst[8]=3 cells (1 PI)
7699 10:02:25.187122 u2DelayCellOfst[9]=0 cells (0 PI)
7700 10:02:25.190090 u2DelayCellOfst[10]=6 cells (2 PI)
7701 10:02:25.193922 u2DelayCellOfst[11]=6 cells (2 PI)
7702 10:02:25.197033 u2DelayCellOfst[12]=13 cells (4 PI)
7703 10:02:25.200166 u2DelayCellOfst[13]=13 cells (4 PI)
7704 10:02:25.203990 u2DelayCellOfst[14]=13 cells (4 PI)
7705 10:02:25.206746 u2DelayCellOfst[15]=10 cells (3 PI)
7706 10:02:25.210062 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7707 10:02:25.213709 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7708 10:02:25.216636 DramC Write-DBI on
7709 10:02:25.216754 ==
7710 10:02:25.220499 Dram Type= 6, Freq= 0, CH_0, rank 0
7711 10:02:25.223559 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7712 10:02:25.223681 ==
7713 10:02:25.223779
7714 10:02:25.226712
7715 10:02:25.226823 TX Vref Scan disable
7716 10:02:25.229893 == TX Byte 0 ==
7717 10:02:25.233178 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7718 10:02:25.236850 == TX Byte 1 ==
7719 10:02:25.239914 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
7720 10:02:25.240029 DramC Write-DBI off
7721 10:02:25.243136
7722 10:02:25.243248 [DATLAT]
7723 10:02:25.243345 Freq=1600, CH0 RK0
7724 10:02:25.243438
7725 10:02:25.246957 DATLAT Default: 0xf
7726 10:02:25.247068 0, 0xFFFF, sum = 0
7727 10:02:25.249950 1, 0xFFFF, sum = 0
7728 10:02:25.250065 2, 0xFFFF, sum = 0
7729 10:02:25.253463 3, 0xFFFF, sum = 0
7730 10:02:25.253588 4, 0xFFFF, sum = 0
7731 10:02:25.256724 5, 0xFFFF, sum = 0
7732 10:02:25.259941 6, 0xFFFF, sum = 0
7733 10:02:25.260067 7, 0xFFFF, sum = 0
7734 10:02:25.263238 8, 0xFFFF, sum = 0
7735 10:02:25.263360 9, 0xFFFF, sum = 0
7736 10:02:25.266770 10, 0xFFFF, sum = 0
7737 10:02:25.266888 11, 0xFFFF, sum = 0
7738 10:02:25.269811 12, 0xFFFF, sum = 0
7739 10:02:25.269930 13, 0xFFFF, sum = 0
7740 10:02:25.273606 14, 0x0, sum = 1
7741 10:02:25.273729 15, 0x0, sum = 2
7742 10:02:25.276732 16, 0x0, sum = 3
7743 10:02:25.276848 17, 0x0, sum = 4
7744 10:02:25.279774 best_step = 15
7745 10:02:25.279895
7746 10:02:25.279993 ==
7747 10:02:25.283596 Dram Type= 6, Freq= 0, CH_0, rank 0
7748 10:02:25.286454 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7749 10:02:25.286569 ==
7750 10:02:25.286666 RX Vref Scan: 1
7751 10:02:25.289752
7752 10:02:25.289867 Set Vref Range= 24 -> 127
7753 10:02:25.289964
7754 10:02:25.293175 RX Vref 24 -> 127, step: 1
7755 10:02:25.293293
7756 10:02:25.296210 RX Delay 27 -> 252, step: 4
7757 10:02:25.296326
7758 10:02:25.300080 Set Vref, RX VrefLevel [Byte0]: 24
7759 10:02:25.302988 [Byte1]: 24
7760 10:02:25.303119
7761 10:02:25.306689 Set Vref, RX VrefLevel [Byte0]: 25
7762 10:02:25.309761 [Byte1]: 25
7763 10:02:25.309881
7764 10:02:25.312881 Set Vref, RX VrefLevel [Byte0]: 26
7765 10:02:25.316329 [Byte1]: 26
7766 10:02:25.319812
7767 10:02:25.323179 Set Vref, RX VrefLevel [Byte0]: 27
7768 10:02:25.326840 [Byte1]: 27
7769 10:02:25.326966
7770 10:02:25.329944 Set Vref, RX VrefLevel [Byte0]: 28
7771 10:02:25.333024 [Byte1]: 28
7772 10:02:25.333135
7773 10:02:25.336788 Set Vref, RX VrefLevel [Byte0]: 29
7774 10:02:25.340024 [Byte1]: 29
7775 10:02:25.340140
7776 10:02:25.343220 Set Vref, RX VrefLevel [Byte0]: 30
7777 10:02:25.347047 [Byte1]: 30
7778 10:02:25.350261
7779 10:02:25.350377 Set Vref, RX VrefLevel [Byte0]: 31
7780 10:02:25.353442 [Byte1]: 31
7781 10:02:25.357923
7782 10:02:25.358041 Set Vref, RX VrefLevel [Byte0]: 32
7783 10:02:25.360811 [Byte1]: 32
7784 10:02:25.365533
7785 10:02:25.365656 Set Vref, RX VrefLevel [Byte0]: 33
7786 10:02:25.368454 [Byte1]: 33
7787 10:02:25.372991
7788 10:02:25.373108 Set Vref, RX VrefLevel [Byte0]: 34
7789 10:02:25.375840 [Byte1]: 34
7790 10:02:25.380275
7791 10:02:25.380383 Set Vref, RX VrefLevel [Byte0]: 35
7792 10:02:25.383438 [Byte1]: 35
7793 10:02:25.387817
7794 10:02:25.387934 Set Vref, RX VrefLevel [Byte0]: 36
7795 10:02:25.390935 [Byte1]: 36
7796 10:02:25.395204
7797 10:02:25.395323 Set Vref, RX VrefLevel [Byte0]: 37
7798 10:02:25.398718 [Byte1]: 37
7799 10:02:25.402860
7800 10:02:25.402971 Set Vref, RX VrefLevel [Byte0]: 38
7801 10:02:25.406533 [Byte1]: 38
7802 10:02:25.410721
7803 10:02:25.410837 Set Vref, RX VrefLevel [Byte0]: 39
7804 10:02:25.413541 [Byte1]: 39
7805 10:02:25.417860
7806 10:02:25.417995 Set Vref, RX VrefLevel [Byte0]: 40
7807 10:02:25.421049 [Byte1]: 40
7808 10:02:25.425664
7809 10:02:25.425794 Set Vref, RX VrefLevel [Byte0]: 41
7810 10:02:25.428831 [Byte1]: 41
7811 10:02:25.432954
7812 10:02:25.433085 Set Vref, RX VrefLevel [Byte0]: 42
7813 10:02:25.436467 [Byte1]: 42
7814 10:02:25.440813
7815 10:02:25.440934 Set Vref, RX VrefLevel [Byte0]: 43
7816 10:02:25.444056 [Byte1]: 43
7817 10:02:25.447816
7818 10:02:25.447934 Set Vref, RX VrefLevel [Byte0]: 44
7819 10:02:25.451615 [Byte1]: 44
7820 10:02:25.455509
7821 10:02:25.455618 Set Vref, RX VrefLevel [Byte0]: 45
7822 10:02:25.458740 [Byte1]: 45
7823 10:02:25.463085
7824 10:02:25.463199 Set Vref, RX VrefLevel [Byte0]: 46
7825 10:02:25.466310 [Byte1]: 46
7826 10:02:25.470745
7827 10:02:25.470854 Set Vref, RX VrefLevel [Byte0]: 47
7828 10:02:25.473784 [Byte1]: 47
7829 10:02:25.478658
7830 10:02:25.478784 Set Vref, RX VrefLevel [Byte0]: 48
7831 10:02:25.481673 [Byte1]: 48
7832 10:02:25.485832
7833 10:02:25.485950 Set Vref, RX VrefLevel [Byte0]: 49
7834 10:02:25.489241 [Byte1]: 49
7835 10:02:25.493474
7836 10:02:25.493601 Set Vref, RX VrefLevel [Byte0]: 50
7837 10:02:25.496680 [Byte1]: 50
7838 10:02:25.500884
7839 10:02:25.501000 Set Vref, RX VrefLevel [Byte0]: 51
7840 10:02:25.503922 [Byte1]: 51
7841 10:02:25.508691
7842 10:02:25.508822 Set Vref, RX VrefLevel [Byte0]: 52
7843 10:02:25.511626 [Byte1]: 52
7844 10:02:25.515865
7845 10:02:25.515985 Set Vref, RX VrefLevel [Byte0]: 53
7846 10:02:25.519545 [Byte1]: 53
7847 10:02:25.523497
7848 10:02:25.523618 Set Vref, RX VrefLevel [Byte0]: 54
7849 10:02:25.526538 [Byte1]: 54
7850 10:02:25.530858
7851 10:02:25.531002 Set Vref, RX VrefLevel [Byte0]: 55
7852 10:02:25.534116 [Byte1]: 55
7853 10:02:25.538272
7854 10:02:25.538369 Set Vref, RX VrefLevel [Byte0]: 56
7855 10:02:25.541669 [Byte1]: 56
7856 10:02:25.546018
7857 10:02:25.546133 Set Vref, RX VrefLevel [Byte0]: 57
7858 10:02:25.549299 [Byte1]: 57
7859 10:02:25.553610
7860 10:02:25.553710 Set Vref, RX VrefLevel [Byte0]: 58
7861 10:02:25.556743 [Byte1]: 58
7862 10:02:25.561131
7863 10:02:25.561264 Set Vref, RX VrefLevel [Byte0]: 59
7864 10:02:25.564208 [Byte1]: 59
7865 10:02:25.568802
7866 10:02:25.568932 Set Vref, RX VrefLevel [Byte0]: 60
7867 10:02:25.571883 [Byte1]: 60
7868 10:02:25.576478
7869 10:02:25.576605 Set Vref, RX VrefLevel [Byte0]: 61
7870 10:02:25.579341 [Byte1]: 61
7871 10:02:25.583567
7872 10:02:25.586889 Set Vref, RX VrefLevel [Byte0]: 62
7873 10:02:25.587017 [Byte1]: 62
7874 10:02:25.591409
7875 10:02:25.591530 Set Vref, RX VrefLevel [Byte0]: 63
7876 10:02:25.594572 [Byte1]: 63
7877 10:02:25.598966
7878 10:02:25.599052 Set Vref, RX VrefLevel [Byte0]: 64
7879 10:02:25.602126 [Byte1]: 64
7880 10:02:25.606100
7881 10:02:25.606192 Set Vref, RX VrefLevel [Byte0]: 65
7882 10:02:25.609555 [Byte1]: 65
7883 10:02:25.613720
7884 10:02:25.613814 Set Vref, RX VrefLevel [Byte0]: 66
7885 10:02:25.617260 [Byte1]: 66
7886 10:02:25.621428
7887 10:02:25.621554 Set Vref, RX VrefLevel [Byte0]: 67
7888 10:02:25.624448 [Byte1]: 67
7889 10:02:25.628921
7890 10:02:25.629016 Set Vref, RX VrefLevel [Byte0]: 68
7891 10:02:25.632218 [Byte1]: 68
7892 10:02:25.636481
7893 10:02:25.636577 Set Vref, RX VrefLevel [Byte0]: 69
7894 10:02:25.639682 [Byte1]: 69
7895 10:02:25.644169
7896 10:02:25.644260 Set Vref, RX VrefLevel [Byte0]: 70
7897 10:02:25.647341 [Byte1]: 70
7898 10:02:25.651337
7899 10:02:25.651455 Set Vref, RX VrefLevel [Byte0]: 71
7900 10:02:25.655089 [Byte1]: 71
7901 10:02:25.659158
7902 10:02:25.659279 Set Vref, RX VrefLevel [Byte0]: 72
7903 10:02:25.662327 [Byte1]: 72
7904 10:02:25.666848
7905 10:02:25.666966 Set Vref, RX VrefLevel [Byte0]: 73
7906 10:02:25.670041 [Byte1]: 73
7907 10:02:25.673866
7908 10:02:25.673985 Set Vref, RX VrefLevel [Byte0]: 74
7909 10:02:25.677584 [Byte1]: 74
7910 10:02:25.681348
7911 10:02:25.681453 Set Vref, RX VrefLevel [Byte0]: 75
7912 10:02:25.685048 [Byte1]: 75
7913 10:02:25.689043
7914 10:02:25.689154 Final RX Vref Byte 0 = 54 to rank0
7915 10:02:25.692520 Final RX Vref Byte 1 = 64 to rank0
7916 10:02:25.696003 Final RX Vref Byte 0 = 54 to rank1
7917 10:02:25.698953 Final RX Vref Byte 1 = 64 to rank1==
7918 10:02:25.702876 Dram Type= 6, Freq= 0, CH_0, rank 0
7919 10:02:25.708964 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7920 10:02:25.709066 ==
7921 10:02:25.709179 DQS Delay:
7922 10:02:25.709284 DQS0 = 0, DQS1 = 0
7923 10:02:25.712347 DQM Delay:
7924 10:02:25.712432 DQM0 = 133, DQM1 = 128
7925 10:02:25.715757 DQ Delay:
7926 10:02:25.719197 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =130
7927 10:02:25.722130 DQ4 =132, DQ5 =124, DQ6 =138, DQ7 =138
7928 10:02:25.725437 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =120
7929 10:02:25.728756 DQ12 =132, DQ13 =132, DQ14 =138, DQ15 =136
7930 10:02:25.728863
7931 10:02:25.728969
7932 10:02:25.729063
7933 10:02:25.732072 [DramC_TX_OE_Calibration] TA2
7934 10:02:25.735586 Original DQ_B0 (3 6) =30, OEN = 27
7935 10:02:25.738605 Original DQ_B1 (3 6) =30, OEN = 27
7936 10:02:25.742013 24, 0x0, End_B0=24 End_B1=24
7937 10:02:25.742110 25, 0x0, End_B0=25 End_B1=25
7938 10:02:25.745696 26, 0x0, End_B0=26 End_B1=26
7939 10:02:25.748801 27, 0x0, End_B0=27 End_B1=27
7940 10:02:25.751876 28, 0x0, End_B0=28 End_B1=28
7941 10:02:25.755604 29, 0x0, End_B0=29 End_B1=29
7942 10:02:25.755710 30, 0x0, End_B0=30 End_B1=30
7943 10:02:25.758928 31, 0x4141, End_B0=30 End_B1=30
7944 10:02:25.762206 Byte0 end_step=30 best_step=27
7945 10:02:25.765502 Byte1 end_step=30 best_step=27
7946 10:02:25.768901 Byte0 TX OE(2T, 0.5T) = (3, 3)
7947 10:02:25.772142 Byte1 TX OE(2T, 0.5T) = (3, 3)
7948 10:02:25.772265
7949 10:02:25.772370
7950 10:02:25.778470 [DQSOSCAuto] RK0, (LSB)MR18= 0x2420, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
7951 10:02:25.782139 CH0 RK0: MR19=303, MR18=2420
7952 10:02:25.788338 CH0_RK0: MR19=0x303, MR18=0x2420, DQSOSC=391, MR23=63, INC=24, DEC=16
7953 10:02:25.788459
7954 10:02:25.792289 ----->DramcWriteLeveling(PI) begin...
7955 10:02:25.792411 ==
7956 10:02:25.795389 Dram Type= 6, Freq= 0, CH_0, rank 1
7957 10:02:25.798362 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7958 10:02:25.798470 ==
7959 10:02:25.801749 Write leveling (Byte 0): 34 => 34
7960 10:02:25.804955 Write leveling (Byte 1): 27 => 27
7961 10:02:25.808509 DramcWriteLeveling(PI) end<-----
7962 10:02:25.808604
7963 10:02:25.808672 ==
7964 10:02:25.811659 Dram Type= 6, Freq= 0, CH_0, rank 1
7965 10:02:25.815423 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7966 10:02:25.815542 ==
7967 10:02:25.818437 [Gating] SW mode calibration
7968 10:02:25.825338 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7969 10:02:25.832064 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7970 10:02:25.834766 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7971 10:02:25.841914 1 4 4 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7972 10:02:25.845104 1 4 8 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
7973 10:02:25.848404 1 4 12 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
7974 10:02:25.851725 1 4 16 | B1->B0 | 2a2a 3635 | 1 1 | (0 0) (0 0)
7975 10:02:25.858139 1 4 20 | B1->B0 | 3434 3534 | 1 1 | (1 1) (1 1)
7976 10:02:25.861428 1 4 24 | B1->B0 | 3434 3838 | 1 0 | (1 1) (0 0)
7977 10:02:25.865088 1 4 28 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7978 10:02:25.871500 1 5 0 | B1->B0 | 3434 3635 | 1 1 | (1 1) (1 1)
7979 10:02:25.875348 1 5 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (1 1)
7980 10:02:25.878099 1 5 8 | B1->B0 | 3434 3635 | 1 1 | (1 1) (1 1)
7981 10:02:25.884726 1 5 12 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 1)
7982 10:02:25.887859 1 5 16 | B1->B0 | 2b2b 2828 | 0 0 | (0 0) (0 0)
7983 10:02:25.891491 1 5 20 | B1->B0 | 2323 2a29 | 0 1 | (0 0) (0 0)
7984 10:02:25.898306 1 5 24 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
7985 10:02:25.901542 1 5 28 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)
7986 10:02:25.904555 1 6 0 | B1->B0 | 2323 2e2d | 0 1 | (0 0) (1 1)
7987 10:02:25.911942 1 6 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7988 10:02:25.914571 1 6 8 | B1->B0 | 2323 2827 | 0 1 | (0 0) (0 0)
7989 10:02:25.917953 1 6 12 | B1->B0 | 2828 3a3a | 1 1 | (0 0) (0 0)
7990 10:02:25.924996 1 6 16 | B1->B0 | 3a3a 4645 | 0 1 | (0 0) (0 0)
7991 10:02:25.928046 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7992 10:02:25.931866 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7993 10:02:25.938166 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7994 10:02:25.941264 1 7 0 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7995 10:02:25.944954 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7996 10:02:25.951303 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7997 10:02:25.954772 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7998 10:02:25.958118 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7999 10:02:25.964470 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8000 10:02:25.967747 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8001 10:02:25.971480 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8002 10:02:25.977870 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8003 10:02:25.980925 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8004 10:02:25.984149 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8005 10:02:25.991189 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8006 10:02:25.994545 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8007 10:02:25.998098 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8008 10:02:26.001205 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8009 10:02:26.007542 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8010 10:02:26.011183 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8011 10:02:26.014329 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8012 10:02:26.020952 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8013 10:02:26.024402 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8014 10:02:26.027412 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8015 10:02:26.034292 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8016 10:02:26.037793 Total UI for P1: 0, mck2ui 16
8017 10:02:26.040997 best dqsien dly found for B0: ( 1, 9, 14)
8018 10:02:26.041109 Total UI for P1: 0, mck2ui 16
8019 10:02:26.047255 best dqsien dly found for B1: ( 1, 9, 14)
8020 10:02:26.051114 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8021 10:02:26.054009 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8022 10:02:26.054123
8023 10:02:26.057850 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8024 10:02:26.061118 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8025 10:02:26.064653 [Gating] SW calibration Done
8026 10:02:26.064748 ==
8027 10:02:26.067524 Dram Type= 6, Freq= 0, CH_0, rank 1
8028 10:02:26.071052 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8029 10:02:26.071139 ==
8030 10:02:26.074061 RX Vref Scan: 0
8031 10:02:26.074159
8032 10:02:26.074227 RX Vref 0 -> 0, step: 1
8033 10:02:26.074289
8034 10:02:26.077716 RX Delay 0 -> 252, step: 8
8035 10:02:26.081114 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8036 10:02:26.087368 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8037 10:02:26.091061 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8038 10:02:26.094084 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8039 10:02:26.097314 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8040 10:02:26.100941 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8041 10:02:26.107836 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8042 10:02:26.110544 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8043 10:02:26.113653 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8044 10:02:26.117478 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8045 10:02:26.120707 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8046 10:02:26.127634 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8047 10:02:26.130339 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8048 10:02:26.134408 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8049 10:02:26.137404 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8050 10:02:26.140420 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8051 10:02:26.144113 ==
8052 10:02:26.147500 Dram Type= 6, Freq= 0, CH_0, rank 1
8053 10:02:26.150708 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8054 10:02:26.150794 ==
8055 10:02:26.150860 DQS Delay:
8056 10:02:26.153925 DQS0 = 0, DQS1 = 0
8057 10:02:26.154009 DQM Delay:
8058 10:02:26.157607 DQM0 = 136, DQM1 = 130
8059 10:02:26.157718 DQ Delay:
8060 10:02:26.160528 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8061 10:02:26.163686 DQ4 =139, DQ5 =127, DQ6 =139, DQ7 =143
8062 10:02:26.167023 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8063 10:02:26.170850 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =139
8064 10:02:26.170962
8065 10:02:26.171056
8066 10:02:26.171148 ==
8067 10:02:26.173717 Dram Type= 6, Freq= 0, CH_0, rank 1
8068 10:02:26.180523 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8069 10:02:26.180649 ==
8070 10:02:26.180758
8071 10:02:26.180849
8072 10:02:26.183701 TX Vref Scan disable
8073 10:02:26.183809 == TX Byte 0 ==
8074 10:02:26.187364 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8075 10:02:26.194038 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8076 10:02:26.194141 == TX Byte 1 ==
8077 10:02:26.196758 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8078 10:02:26.203839 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8079 10:02:26.203976 ==
8080 10:02:26.206999 Dram Type= 6, Freq= 0, CH_0, rank 1
8081 10:02:26.210026 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8082 10:02:26.210108 ==
8083 10:02:26.222797
8084 10:02:26.226090 TX Vref early break, caculate TX vref
8085 10:02:26.229807 TX Vref=16, minBit 1, minWin=22, winSum=386
8086 10:02:26.232422 TX Vref=18, minBit 6, minWin=23, winSum=398
8087 10:02:26.236071 TX Vref=20, minBit 1, minWin=23, winSum=405
8088 10:02:26.239378 TX Vref=22, minBit 2, minWin=24, winSum=412
8089 10:02:26.242826 TX Vref=24, minBit 0, minWin=25, winSum=421
8090 10:02:26.249650 TX Vref=26, minBit 0, minWin=26, winSum=433
8091 10:02:26.252570 TX Vref=28, minBit 7, minWin=25, winSum=426
8092 10:02:26.256055 TX Vref=30, minBit 1, minWin=25, winSum=419
8093 10:02:26.258938 TX Vref=32, minBit 0, minWin=24, winSum=407
8094 10:02:26.265829 [TxChooseVref] Worse bit 0, Min win 26, Win sum 433, Final Vref 26
8095 10:02:26.265922
8096 10:02:26.269035 Final TX Range 0 Vref 26
8097 10:02:26.269113
8098 10:02:26.269176 ==
8099 10:02:26.272884 Dram Type= 6, Freq= 0, CH_0, rank 1
8100 10:02:26.276005 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8101 10:02:26.276118 ==
8102 10:02:26.276221
8103 10:02:26.276317
8104 10:02:26.279034 TX Vref Scan disable
8105 10:02:26.285472 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8106 10:02:26.285608 == TX Byte 0 ==
8107 10:02:26.289107 u2DelayCellOfst[0]=13 cells (4 PI)
8108 10:02:26.292202 u2DelayCellOfst[1]=17 cells (5 PI)
8109 10:02:26.295973 u2DelayCellOfst[2]=10 cells (3 PI)
8110 10:02:26.298954 u2DelayCellOfst[3]=6 cells (2 PI)
8111 10:02:26.302026 u2DelayCellOfst[4]=6 cells (2 PI)
8112 10:02:26.305628 u2DelayCellOfst[5]=0 cells (0 PI)
8113 10:02:26.305721 u2DelayCellOfst[6]=17 cells (5 PI)
8114 10:02:26.309168 u2DelayCellOfst[7]=17 cells (5 PI)
8115 10:02:26.315893 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8116 10:02:26.319207 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8117 10:02:26.319344 == TX Byte 1 ==
8118 10:02:26.322198 u2DelayCellOfst[8]=3 cells (1 PI)
8119 10:02:26.325430 u2DelayCellOfst[9]=0 cells (0 PI)
8120 10:02:26.328676 u2DelayCellOfst[10]=10 cells (3 PI)
8121 10:02:26.331939 u2DelayCellOfst[11]=3 cells (1 PI)
8122 10:02:26.335791 u2DelayCellOfst[12]=10 cells (3 PI)
8123 10:02:26.339029 u2DelayCellOfst[13]=13 cells (4 PI)
8124 10:02:26.342108 u2DelayCellOfst[14]=13 cells (4 PI)
8125 10:02:26.345304 u2DelayCellOfst[15]=10 cells (3 PI)
8126 10:02:26.348893 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8127 10:02:26.355417 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8128 10:02:26.355575 DramC Write-DBI on
8129 10:02:26.355705 ==
8130 10:02:26.358468 Dram Type= 6, Freq= 0, CH_0, rank 1
8131 10:02:26.362083 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8132 10:02:26.362190 ==
8133 10:02:26.364944
8134 10:02:26.365065
8135 10:02:26.365164 TX Vref Scan disable
8136 10:02:26.368288 == TX Byte 0 ==
8137 10:02:26.371830 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8138 10:02:26.375043 == TX Byte 1 ==
8139 10:02:26.378774 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8140 10:02:26.378930 DramC Write-DBI off
8141 10:02:26.381877
8142 10:02:26.381992 [DATLAT]
8143 10:02:26.382096 Freq=1600, CH0 RK1
8144 10:02:26.382195
8145 10:02:26.385318 DATLAT Default: 0xf
8146 10:02:26.385459 0, 0xFFFF, sum = 0
8147 10:02:26.388933 1, 0xFFFF, sum = 0
8148 10:02:26.389053 2, 0xFFFF, sum = 0
8149 10:02:26.391867 3, 0xFFFF, sum = 0
8150 10:02:26.394921 4, 0xFFFF, sum = 0
8151 10:02:26.395032 5, 0xFFFF, sum = 0
8152 10:02:26.398685 6, 0xFFFF, sum = 0
8153 10:02:26.398793 7, 0xFFFF, sum = 0
8154 10:02:26.401614 8, 0xFFFF, sum = 0
8155 10:02:26.401739 9, 0xFFFF, sum = 0
8156 10:02:26.405330 10, 0xFFFF, sum = 0
8157 10:02:26.405423 11, 0xFFFF, sum = 0
8158 10:02:26.408415 12, 0xFFFF, sum = 0
8159 10:02:26.408521 13, 0xFFFF, sum = 0
8160 10:02:26.412040 14, 0x0, sum = 1
8161 10:02:26.412123 15, 0x0, sum = 2
8162 10:02:26.414926 16, 0x0, sum = 3
8163 10:02:26.415020 17, 0x0, sum = 4
8164 10:02:26.418291 best_step = 15
8165 10:02:26.418416
8166 10:02:26.418512 ==
8167 10:02:26.421879 Dram Type= 6, Freq= 0, CH_0, rank 1
8168 10:02:26.425004 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8169 10:02:26.425124 ==
8170 10:02:26.425225 RX Vref Scan: 0
8171 10:02:26.428209
8172 10:02:26.428318 RX Vref 0 -> 0, step: 1
8173 10:02:26.428419
8174 10:02:26.431980 RX Delay 19 -> 252, step: 4
8175 10:02:26.435255 iDelay=191, Bit 0, Center 132 (79 ~ 186) 108
8176 10:02:26.441547 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8177 10:02:26.445162 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8178 10:02:26.448311 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8179 10:02:26.452132 iDelay=191, Bit 4, Center 136 (83 ~ 190) 108
8180 10:02:26.455119 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8181 10:02:26.458701 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8182 10:02:26.465177 iDelay=191, Bit 7, Center 142 (95 ~ 190) 96
8183 10:02:26.468242 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8184 10:02:26.471414 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8185 10:02:26.475004 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8186 10:02:26.481569 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8187 10:02:26.484798 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8188 10:02:26.488484 iDelay=191, Bit 13, Center 132 (83 ~ 182) 100
8189 10:02:26.491510 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8190 10:02:26.495217 iDelay=191, Bit 15, Center 134 (87 ~ 182) 96
8191 10:02:26.495319 ==
8192 10:02:26.498123 Dram Type= 6, Freq= 0, CH_0, rank 1
8193 10:02:26.504719 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8194 10:02:26.504856 ==
8195 10:02:26.504964 DQS Delay:
8196 10:02:26.508653 DQS0 = 0, DQS1 = 0
8197 10:02:26.508747 DQM Delay:
8198 10:02:26.511713 DQM0 = 134, DQM1 = 127
8199 10:02:26.511828 DQ Delay:
8200 10:02:26.515040 DQ0 =132, DQ1 =138, DQ2 =130, DQ3 =134
8201 10:02:26.518116 DQ4 =136, DQ5 =124, DQ6 =140, DQ7 =142
8202 10:02:26.521255 DQ8 =118, DQ9 =116, DQ10 =128, DQ11 =120
8203 10:02:26.524838 DQ12 =134, DQ13 =132, DQ14 =134, DQ15 =134
8204 10:02:26.524955
8205 10:02:26.525048
8206 10:02:26.525147
8207 10:02:26.528297 [DramC_TX_OE_Calibration] TA2
8208 10:02:26.531310 Original DQ_B0 (3 6) =30, OEN = 27
8209 10:02:26.534918 Original DQ_B1 (3 6) =30, OEN = 27
8210 10:02:26.538055 24, 0x0, End_B0=24 End_B1=24
8211 10:02:26.541302 25, 0x0, End_B0=25 End_B1=25
8212 10:02:26.541430 26, 0x0, End_B0=26 End_B1=26
8213 10:02:26.544509 27, 0x0, End_B0=27 End_B1=27
8214 10:02:26.548068 28, 0x0, End_B0=28 End_B1=28
8215 10:02:26.551784 29, 0x0, End_B0=29 End_B1=29
8216 10:02:26.551875 30, 0x0, End_B0=30 End_B1=30
8217 10:02:26.554646 31, 0x4141, End_B0=30 End_B1=30
8218 10:02:26.557677 Byte0 end_step=30 best_step=27
8219 10:02:26.561242 Byte1 end_step=30 best_step=27
8220 10:02:26.564440 Byte0 TX OE(2T, 0.5T) = (3, 3)
8221 10:02:26.567698 Byte1 TX OE(2T, 0.5T) = (3, 3)
8222 10:02:26.567813
8223 10:02:26.567928
8224 10:02:26.574582 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f07, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 394 ps
8225 10:02:26.577719 CH0 RK1: MR19=303, MR18=1F07
8226 10:02:26.584213 CH0_RK1: MR19=0x303, MR18=0x1F07, DQSOSC=394, MR23=63, INC=23, DEC=15
8227 10:02:26.587742 [RxdqsGatingPostProcess] freq 1600
8228 10:02:26.591168 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8229 10:02:26.594427 best DQS0 dly(2T, 0.5T) = (1, 1)
8230 10:02:26.597792 best DQS1 dly(2T, 0.5T) = (1, 1)
8231 10:02:26.601030 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8232 10:02:26.604478 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8233 10:02:26.607955 best DQS0 dly(2T, 0.5T) = (1, 1)
8234 10:02:26.610821 best DQS1 dly(2T, 0.5T) = (1, 1)
8235 10:02:26.614302 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8236 10:02:26.617589 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8237 10:02:26.620792 Pre-setting of DQS Precalculation
8238 10:02:26.624418 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8239 10:02:26.624534 ==
8240 10:02:26.627523 Dram Type= 6, Freq= 0, CH_1, rank 0
8241 10:02:26.631172 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8242 10:02:26.634267 ==
8243 10:02:26.637796 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8244 10:02:26.640712 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8245 10:02:26.647485 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8246 10:02:26.654464 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8247 10:02:26.661635 [CA 0] Center 42 (12~72) winsize 61
8248 10:02:26.664831 [CA 1] Center 42 (12~72) winsize 61
8249 10:02:26.667840 [CA 2] Center 38 (9~68) winsize 60
8250 10:02:26.671581 [CA 3] Center 38 (9~67) winsize 59
8251 10:02:26.674871 [CA 4] Center 38 (9~68) winsize 60
8252 10:02:26.677700 [CA 5] Center 37 (8~67) winsize 60
8253 10:02:26.677811
8254 10:02:26.681443 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8255 10:02:26.681555
8256 10:02:26.684703 [CATrainingPosCal] consider 1 rank data
8257 10:02:26.687885 u2DelayCellTimex100 = 285/100 ps
8258 10:02:26.690915 CA0 delay=42 (12~72),Diff = 5 PI (17 cell)
8259 10:02:26.697865 CA1 delay=42 (12~72),Diff = 5 PI (17 cell)
8260 10:02:26.701056 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8261 10:02:26.704582 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8262 10:02:26.707763 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8263 10:02:26.710752 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8264 10:02:26.710861
8265 10:02:26.714086 CA PerBit enable=1, Macro0, CA PI delay=37
8266 10:02:26.714167
8267 10:02:26.717799 [CBTSetCACLKResult] CA Dly = 37
8268 10:02:26.720779 CS Dly: 11 (0~42)
8269 10:02:26.723962 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8270 10:02:26.727344 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8271 10:02:26.727469 ==
8272 10:02:26.731031 Dram Type= 6, Freq= 0, CH_1, rank 1
8273 10:02:26.734044 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8274 10:02:26.737256 ==
8275 10:02:26.741010 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8276 10:02:26.743922 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8277 10:02:26.750972 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8278 10:02:26.754080 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8279 10:02:26.764341 [CA 0] Center 42 (12~72) winsize 61
8280 10:02:26.767544 [CA 1] Center 42 (12~72) winsize 61
8281 10:02:26.771243 [CA 2] Center 38 (9~68) winsize 60
8282 10:02:26.774304 [CA 3] Center 38 (8~68) winsize 61
8283 10:02:26.777721 [CA 4] Center 38 (8~69) winsize 62
8284 10:02:26.781142 [CA 5] Center 37 (7~67) winsize 61
8285 10:02:26.781264
8286 10:02:26.784365 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8287 10:02:26.784490
8288 10:02:26.787611 [CATrainingPosCal] consider 2 rank data
8289 10:02:26.791208 u2DelayCellTimex100 = 285/100 ps
8290 10:02:26.794255 CA0 delay=42 (12~72),Diff = 5 PI (17 cell)
8291 10:02:26.801050 CA1 delay=42 (12~72),Diff = 5 PI (17 cell)
8292 10:02:26.804243 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8293 10:02:26.807905 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8294 10:02:26.811028 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8295 10:02:26.814101 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8296 10:02:26.814182
8297 10:02:26.817897 CA PerBit enable=1, Macro0, CA PI delay=37
8298 10:02:26.818002
8299 10:02:26.821061 [CBTSetCACLKResult] CA Dly = 37
8300 10:02:26.824533 CS Dly: 12 (0~44)
8301 10:02:26.827487 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8302 10:02:26.831188 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8303 10:02:26.831270
8304 10:02:26.834124 ----->DramcWriteLeveling(PI) begin...
8305 10:02:26.834239 ==
8306 10:02:26.837831 Dram Type= 6, Freq= 0, CH_1, rank 0
8307 10:02:26.844238 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8308 10:02:26.844332 ==
8309 10:02:26.847561 Write leveling (Byte 0): 26 => 26
8310 10:02:26.847673 Write leveling (Byte 1): 29 => 29
8311 10:02:26.850776 DramcWriteLeveling(PI) end<-----
8312 10:02:26.850877
8313 10:02:26.850967 ==
8314 10:02:26.853783 Dram Type= 6, Freq= 0, CH_1, rank 0
8315 10:02:26.860652 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8316 10:02:26.860792 ==
8317 10:02:26.864251 [Gating] SW mode calibration
8318 10:02:26.870650 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8319 10:02:26.873959 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8320 10:02:26.881087 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8321 10:02:26.883943 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8322 10:02:26.887192 1 4 8 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
8323 10:02:26.893887 1 4 12 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
8324 10:02:26.897120 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8325 10:02:26.900309 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8326 10:02:26.907401 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8327 10:02:26.910442 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8328 10:02:26.913700 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8329 10:02:26.917233 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8330 10:02:26.923749 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8331 10:02:26.927390 1 5 12 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
8332 10:02:26.930673 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8333 10:02:26.936837 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8334 10:02:26.940461 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8335 10:02:26.943477 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8336 10:02:26.950431 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8337 10:02:26.954040 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8338 10:02:26.956972 1 6 8 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (0 0)
8339 10:02:26.963886 1 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8340 10:02:26.967108 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8341 10:02:26.970646 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8342 10:02:26.976819 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8343 10:02:26.980787 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8344 10:02:26.983837 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8345 10:02:26.989952 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8346 10:02:26.993729 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8347 10:02:26.996838 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8348 10:02:27.003496 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8349 10:02:27.006965 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8350 10:02:27.010415 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8351 10:02:27.017116 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8352 10:02:27.020588 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8353 10:02:27.023625 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8354 10:02:27.026962 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8355 10:02:27.033808 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8356 10:02:27.036887 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8357 10:02:27.040546 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8358 10:02:27.046920 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8359 10:02:27.049996 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8360 10:02:27.053780 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8361 10:02:27.060344 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8362 10:02:27.063603 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8363 10:02:27.066749 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8364 10:02:27.069999 Total UI for P1: 0, mck2ui 16
8365 10:02:27.073615 best dqsien dly found for B0: ( 1, 9, 8)
8366 10:02:27.080153 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8367 10:02:27.080248 Total UI for P1: 0, mck2ui 16
8368 10:02:27.087122 best dqsien dly found for B1: ( 1, 9, 12)
8369 10:02:27.090453 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8370 10:02:27.093384 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8371 10:02:27.093500
8372 10:02:27.096505 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8373 10:02:27.100323 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8374 10:02:27.103671 [Gating] SW calibration Done
8375 10:02:27.103756 ==
8376 10:02:27.106527 Dram Type= 6, Freq= 0, CH_1, rank 0
8377 10:02:27.109795 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8378 10:02:27.109882 ==
8379 10:02:27.113582 RX Vref Scan: 0
8380 10:02:27.113705
8381 10:02:27.113782 RX Vref 0 -> 0, step: 1
8382 10:02:27.116437
8383 10:02:27.116522 RX Delay 0 -> 252, step: 8
8384 10:02:27.120174 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8385 10:02:27.126325 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8386 10:02:27.130033 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8387 10:02:27.133145 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8388 10:02:27.137040 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8389 10:02:27.139841 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8390 10:02:27.146612 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8391 10:02:27.149755 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8392 10:02:27.152780 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8393 10:02:27.156571 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8394 10:02:27.159803 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8395 10:02:27.166453 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8396 10:02:27.169505 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8397 10:02:27.172887 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8398 10:02:27.176555 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8399 10:02:27.180132 iDelay=200, Bit 15, Center 143 (96 ~ 191) 96
8400 10:02:27.183313 ==
8401 10:02:27.183401 Dram Type= 6, Freq= 0, CH_1, rank 0
8402 10:02:27.189572 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8403 10:02:27.189705 ==
8404 10:02:27.189802 DQS Delay:
8405 10:02:27.193004 DQS0 = 0, DQS1 = 0
8406 10:02:27.193089 DQM Delay:
8407 10:02:27.196520 DQM0 = 136, DQM1 = 132
8408 10:02:27.196609 DQ Delay:
8409 10:02:27.199421 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8410 10:02:27.203215 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8411 10:02:27.206386 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8412 10:02:27.209656 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =143
8413 10:02:27.209745
8414 10:02:27.209814
8415 10:02:27.209882 ==
8416 10:02:27.212725 Dram Type= 6, Freq= 0, CH_1, rank 0
8417 10:02:27.219571 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8418 10:02:27.219698 ==
8419 10:02:27.219767
8420 10:02:27.219829
8421 10:02:27.219888 TX Vref Scan disable
8422 10:02:27.223264 == TX Byte 0 ==
8423 10:02:27.226417 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8424 10:02:27.233273 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8425 10:02:27.233372 == TX Byte 1 ==
8426 10:02:27.236274 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8427 10:02:27.242999 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8428 10:02:27.243102 ==
8429 10:02:27.246358 Dram Type= 6, Freq= 0, CH_1, rank 0
8430 10:02:27.249560 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8431 10:02:27.249673 ==
8432 10:02:27.262266
8433 10:02:27.265405 TX Vref early break, caculate TX vref
8434 10:02:27.268530 TX Vref=16, minBit 0, minWin=22, winSum=377
8435 10:02:27.271703 TX Vref=18, minBit 9, minWin=22, winSum=381
8436 10:02:27.275383 TX Vref=20, minBit 1, minWin=23, winSum=393
8437 10:02:27.278294 TX Vref=22, minBit 1, minWin=24, winSum=405
8438 10:02:27.281698 TX Vref=24, minBit 1, minWin=25, winSum=420
8439 10:02:27.288933 TX Vref=26, minBit 0, minWin=25, winSum=423
8440 10:02:27.291976 TX Vref=28, minBit 0, minWin=25, winSum=424
8441 10:02:27.294904 TX Vref=30, minBit 0, minWin=25, winSum=417
8442 10:02:27.298447 TX Vref=32, minBit 0, minWin=24, winSum=409
8443 10:02:27.302037 TX Vref=34, minBit 0, minWin=24, winSum=399
8444 10:02:27.308259 [TxChooseVref] Worse bit 0, Min win 25, Win sum 424, Final Vref 28
8445 10:02:27.308368
8446 10:02:27.312136 Final TX Range 0 Vref 28
8447 10:02:27.312232
8448 10:02:27.312329 ==
8449 10:02:27.315302 Dram Type= 6, Freq= 0, CH_1, rank 0
8450 10:02:27.318466 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8451 10:02:27.318577 ==
8452 10:02:27.318680
8453 10:02:27.318779
8454 10:02:27.321466 TX Vref Scan disable
8455 10:02:27.328710 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8456 10:02:27.328856 == TX Byte 0 ==
8457 10:02:27.331811 u2DelayCellOfst[0]=17 cells (5 PI)
8458 10:02:27.335126 u2DelayCellOfst[1]=10 cells (3 PI)
8459 10:02:27.338327 u2DelayCellOfst[2]=0 cells (0 PI)
8460 10:02:27.342114 u2DelayCellOfst[3]=6 cells (2 PI)
8461 10:02:27.344963 u2DelayCellOfst[4]=6 cells (2 PI)
8462 10:02:27.348528 u2DelayCellOfst[5]=17 cells (5 PI)
8463 10:02:27.348623 u2DelayCellOfst[6]=17 cells (5 PI)
8464 10:02:27.351576 u2DelayCellOfst[7]=6 cells (2 PI)
8465 10:02:27.358193 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8466 10:02:27.361929 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8467 10:02:27.362027 == TX Byte 1 ==
8468 10:02:27.364937 u2DelayCellOfst[8]=0 cells (0 PI)
8469 10:02:27.368749 u2DelayCellOfst[9]=6 cells (2 PI)
8470 10:02:27.371823 u2DelayCellOfst[10]=13 cells (4 PI)
8471 10:02:27.375050 u2DelayCellOfst[11]=6 cells (2 PI)
8472 10:02:27.378197 u2DelayCellOfst[12]=17 cells (5 PI)
8473 10:02:27.381838 u2DelayCellOfst[13]=17 cells (5 PI)
8474 10:02:27.385147 u2DelayCellOfst[14]=20 cells (6 PI)
8475 10:02:27.388815 u2DelayCellOfst[15]=17 cells (5 PI)
8476 10:02:27.391597 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8477 10:02:27.395333 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8478 10:02:27.398285 DramC Write-DBI on
8479 10:02:27.398408 ==
8480 10:02:27.401323 Dram Type= 6, Freq= 0, CH_1, rank 0
8481 10:02:27.405072 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8482 10:02:27.405159 ==
8483 10:02:27.405228
8484 10:02:27.407970
8485 10:02:27.408107 TX Vref Scan disable
8486 10:02:27.411603 == TX Byte 0 ==
8487 10:02:27.414564 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8488 10:02:27.418209 == TX Byte 1 ==
8489 10:02:27.421346 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8490 10:02:27.421472 DramC Write-DBI off
8491 10:02:27.421602
8492 10:02:27.424629 [DATLAT]
8493 10:02:27.424711 Freq=1600, CH1 RK0
8494 10:02:27.424787
8495 10:02:27.428270 DATLAT Default: 0xf
8496 10:02:27.428391 0, 0xFFFF, sum = 0
8497 10:02:27.431463 1, 0xFFFF, sum = 0
8498 10:02:27.431585 2, 0xFFFF, sum = 0
8499 10:02:27.434631 3, 0xFFFF, sum = 0
8500 10:02:27.434740 4, 0xFFFF, sum = 0
8501 10:02:27.438430 5, 0xFFFF, sum = 0
8502 10:02:27.438544 6, 0xFFFF, sum = 0
8503 10:02:27.441514 7, 0xFFFF, sum = 0
8504 10:02:27.444492 8, 0xFFFF, sum = 0
8505 10:02:27.444622 9, 0xFFFF, sum = 0
8506 10:02:27.448431 10, 0xFFFF, sum = 0
8507 10:02:27.448540 11, 0xFFFF, sum = 0
8508 10:02:27.451661 12, 0xFFFF, sum = 0
8509 10:02:27.451820 13, 0xFFFF, sum = 0
8510 10:02:27.454647 14, 0x0, sum = 1
8511 10:02:27.454769 15, 0x0, sum = 2
8512 10:02:27.458383 16, 0x0, sum = 3
8513 10:02:27.458501 17, 0x0, sum = 4
8514 10:02:27.458644 best_step = 15
8515 10:02:27.461268
8516 10:02:27.461386 ==
8517 10:02:27.464757 Dram Type= 6, Freq= 0, CH_1, rank 0
8518 10:02:27.467701 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8519 10:02:27.467815 ==
8520 10:02:27.467912 RX Vref Scan: 1
8521 10:02:27.468012
8522 10:02:27.471111 Set Vref Range= 24 -> 127
8523 10:02:27.471218
8524 10:02:27.474572 RX Vref 24 -> 127, step: 1
8525 10:02:27.474663
8526 10:02:27.478249 RX Delay 27 -> 252, step: 4
8527 10:02:27.478396
8528 10:02:27.481457 Set Vref, RX VrefLevel [Byte0]: 24
8529 10:02:27.484449 [Byte1]: 24
8530 10:02:27.484577
8531 10:02:27.487703 Set Vref, RX VrefLevel [Byte0]: 25
8532 10:02:27.491011 [Byte1]: 25
8533 10:02:27.491150
8534 10:02:27.494606 Set Vref, RX VrefLevel [Byte0]: 26
8535 10:02:27.497739 [Byte1]: 26
8536 10:02:27.501213
8537 10:02:27.501360 Set Vref, RX VrefLevel [Byte0]: 27
8538 10:02:27.504980 [Byte1]: 27
8539 10:02:27.508865
8540 10:02:27.509014 Set Vref, RX VrefLevel [Byte0]: 28
8541 10:02:27.511856 [Byte1]: 28
8542 10:02:27.516702
8543 10:02:27.516794 Set Vref, RX VrefLevel [Byte0]: 29
8544 10:02:27.519646 [Byte1]: 29
8545 10:02:27.523950
8546 10:02:27.524080 Set Vref, RX VrefLevel [Byte0]: 30
8547 10:02:27.527179 [Byte1]: 30
8548 10:02:27.531793
8549 10:02:27.531926 Set Vref, RX VrefLevel [Byte0]: 31
8550 10:02:27.534652 [Byte1]: 31
8551 10:02:27.538875
8552 10:02:27.539002 Set Vref, RX VrefLevel [Byte0]: 32
8553 10:02:27.542498 [Byte1]: 32
8554 10:02:27.546342
8555 10:02:27.546447 Set Vref, RX VrefLevel [Byte0]: 33
8556 10:02:27.549976 [Byte1]: 33
8557 10:02:27.554217
8558 10:02:27.554301 Set Vref, RX VrefLevel [Byte0]: 34
8559 10:02:27.557202 [Byte1]: 34
8560 10:02:27.561790
8561 10:02:27.561917 Set Vref, RX VrefLevel [Byte0]: 35
8562 10:02:27.564958 [Byte1]: 35
8563 10:02:27.568898
8564 10:02:27.568988 Set Vref, RX VrefLevel [Byte0]: 36
8565 10:02:27.572267 [Byte1]: 36
8566 10:02:27.576442
8567 10:02:27.576528 Set Vref, RX VrefLevel [Byte0]: 37
8568 10:02:27.579782 [Byte1]: 37
8569 10:02:27.584288
8570 10:02:27.584385 Set Vref, RX VrefLevel [Byte0]: 38
8571 10:02:27.587532 [Byte1]: 38
8572 10:02:27.591904
8573 10:02:27.592028 Set Vref, RX VrefLevel [Byte0]: 39
8574 10:02:27.594949 [Byte1]: 39
8575 10:02:27.599463
8576 10:02:27.599572 Set Vref, RX VrefLevel [Byte0]: 40
8577 10:02:27.602668 [Byte1]: 40
8578 10:02:27.607086
8579 10:02:27.607198 Set Vref, RX VrefLevel [Byte0]: 41
8580 10:02:27.610018 [Byte1]: 41
8581 10:02:27.614229
8582 10:02:27.614318 Set Vref, RX VrefLevel [Byte0]: 42
8583 10:02:27.617753 [Byte1]: 42
8584 10:02:27.621562
8585 10:02:27.621672 Set Vref, RX VrefLevel [Byte0]: 43
8586 10:02:27.624969 [Byte1]: 43
8587 10:02:27.629595
8588 10:02:27.629693 Set Vref, RX VrefLevel [Byte0]: 44
8589 10:02:27.632733 [Byte1]: 44
8590 10:02:27.636943
8591 10:02:27.637028 Set Vref, RX VrefLevel [Byte0]: 45
8592 10:02:27.640466 [Byte1]: 45
8593 10:02:27.644884
8594 10:02:27.644992 Set Vref, RX VrefLevel [Byte0]: 46
8595 10:02:27.647917 [Byte1]: 46
8596 10:02:27.651723
8597 10:02:27.651828 Set Vref, RX VrefLevel [Byte0]: 47
8598 10:02:27.655256 [Byte1]: 47
8599 10:02:27.659711
8600 10:02:27.659796 Set Vref, RX VrefLevel [Byte0]: 48
8601 10:02:27.662892 [Byte1]: 48
8602 10:02:27.667356
8603 10:02:27.667471 Set Vref, RX VrefLevel [Byte0]: 49
8604 10:02:27.670483 [Byte1]: 49
8605 10:02:27.674695
8606 10:02:27.674785 Set Vref, RX VrefLevel [Byte0]: 50
8607 10:02:27.678176 [Byte1]: 50
8608 10:02:27.682296
8609 10:02:27.682389 Set Vref, RX VrefLevel [Byte0]: 51
8610 10:02:27.685251 [Byte1]: 51
8611 10:02:27.689334
8612 10:02:27.689432 Set Vref, RX VrefLevel [Byte0]: 52
8613 10:02:27.692825 [Byte1]: 52
8614 10:02:27.697225
8615 10:02:27.697309 Set Vref, RX VrefLevel [Byte0]: 53
8616 10:02:27.700210 [Byte1]: 53
8617 10:02:27.704812
8618 10:02:27.704920 Set Vref, RX VrefLevel [Byte0]: 54
8619 10:02:27.708071 [Byte1]: 54
8620 10:02:27.712212
8621 10:02:27.712311 Set Vref, RX VrefLevel [Byte0]: 55
8622 10:02:27.716041 [Byte1]: 55
8623 10:02:27.719809
8624 10:02:27.719923 Set Vref, RX VrefLevel [Byte0]: 56
8625 10:02:27.722888 [Byte1]: 56
8626 10:02:27.727463
8627 10:02:27.727575 Set Vref, RX VrefLevel [Byte0]: 57
8628 10:02:27.730852 [Byte1]: 57
8629 10:02:27.734765
8630 10:02:27.734877 Set Vref, RX VrefLevel [Byte0]: 58
8631 10:02:27.738013 [Byte1]: 58
8632 10:02:27.742142
8633 10:02:27.742225 Set Vref, RX VrefLevel [Byte0]: 59
8634 10:02:27.745803 [Byte1]: 59
8635 10:02:27.749858
8636 10:02:27.749962 Set Vref, RX VrefLevel [Byte0]: 60
8637 10:02:27.753007 [Byte1]: 60
8638 10:02:27.757299
8639 10:02:27.757417 Set Vref, RX VrefLevel [Byte0]: 61
8640 10:02:27.760510 [Byte1]: 61
8641 10:02:27.764990
8642 10:02:27.765100 Set Vref, RX VrefLevel [Byte0]: 62
8643 10:02:27.768157 [Byte1]: 62
8644 10:02:27.772421
8645 10:02:27.772534 Set Vref, RX VrefLevel [Byte0]: 63
8646 10:02:27.775697 [Byte1]: 63
8647 10:02:27.779972
8648 10:02:27.780084 Set Vref, RX VrefLevel [Byte0]: 64
8649 10:02:27.782989 [Byte1]: 64
8650 10:02:27.787751
8651 10:02:27.787862 Set Vref, RX VrefLevel [Byte0]: 65
8652 10:02:27.790631 [Byte1]: 65
8653 10:02:27.794857
8654 10:02:27.794966 Set Vref, RX VrefLevel [Byte0]: 66
8655 10:02:27.798571 [Byte1]: 66
8656 10:02:27.802746
8657 10:02:27.802860 Set Vref, RX VrefLevel [Byte0]: 67
8658 10:02:27.805882 [Byte1]: 67
8659 10:02:27.810295
8660 10:02:27.810381 Set Vref, RX VrefLevel [Byte0]: 68
8661 10:02:27.813449 [Byte1]: 68
8662 10:02:27.817766
8663 10:02:27.817878 Set Vref, RX VrefLevel [Byte0]: 69
8664 10:02:27.821202 [Byte1]: 69
8665 10:02:27.824982
8666 10:02:27.825095 Set Vref, RX VrefLevel [Byte0]: 70
8667 10:02:27.828222 [Byte1]: 70
8668 10:02:27.832694
8669 10:02:27.832774 Set Vref, RX VrefLevel [Byte0]: 71
8670 10:02:27.836390 [Byte1]: 71
8671 10:02:27.840488
8672 10:02:27.840573 Set Vref, RX VrefLevel [Byte0]: 72
8673 10:02:27.843458 [Byte1]: 72
8674 10:02:27.847531
8675 10:02:27.847646 Set Vref, RX VrefLevel [Byte0]: 73
8676 10:02:27.851076 [Byte1]: 73
8677 10:02:27.855308
8678 10:02:27.855465 Set Vref, RX VrefLevel [Byte0]: 74
8679 10:02:27.858446 [Byte1]: 74
8680 10:02:27.863057
8681 10:02:27.863186 Set Vref, RX VrefLevel [Byte0]: 75
8682 10:02:27.866424 [Byte1]: 75
8683 10:02:27.870431
8684 10:02:27.870554 Set Vref, RX VrefLevel [Byte0]: 76
8685 10:02:27.873485 [Byte1]: 76
8686 10:02:27.877896
8687 10:02:27.878002 Set Vref, RX VrefLevel [Byte0]: 77
8688 10:02:27.881085 [Byte1]: 77
8689 10:02:27.885436
8690 10:02:27.885565 Set Vref, RX VrefLevel [Byte0]: 78
8691 10:02:27.888911 [Byte1]: 78
8692 10:02:27.893125
8693 10:02:27.893362 Set Vref, RX VrefLevel [Byte0]: 79
8694 10:02:27.896109 [Byte1]: 79
8695 10:02:27.900252
8696 10:02:27.900396 Final RX Vref Byte 0 = 56 to rank0
8697 10:02:27.903615 Final RX Vref Byte 1 = 56 to rank0
8698 10:02:27.907385 Final RX Vref Byte 0 = 56 to rank1
8699 10:02:27.910233 Final RX Vref Byte 1 = 56 to rank1==
8700 10:02:27.914009 Dram Type= 6, Freq= 0, CH_1, rank 0
8701 10:02:27.920517 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8702 10:02:27.920640 ==
8703 10:02:27.920749 DQS Delay:
8704 10:02:27.920840 DQS0 = 0, DQS1 = 0
8705 10:02:27.923681 DQM Delay:
8706 10:02:27.923819 DQM0 = 134, DQM1 = 131
8707 10:02:27.927044 DQ Delay:
8708 10:02:27.930609 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8709 10:02:27.933935 DQ4 =132, DQ5 =144, DQ6 =142, DQ7 =132
8710 10:02:27.936949 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =124
8711 10:02:27.940678 DQ12 =138, DQ13 =138, DQ14 =140, DQ15 =140
8712 10:02:27.940760
8713 10:02:27.940827
8714 10:02:27.940894
8715 10:02:27.943653 [DramC_TX_OE_Calibration] TA2
8716 10:02:27.947378 Original DQ_B0 (3 6) =30, OEN = 27
8717 10:02:27.950258 Original DQ_B1 (3 6) =30, OEN = 27
8718 10:02:27.954025 24, 0x0, End_B0=24 End_B1=24
8719 10:02:27.954156 25, 0x0, End_B0=25 End_B1=25
8720 10:02:27.956882 26, 0x0, End_B0=26 End_B1=26
8721 10:02:27.960730 27, 0x0, End_B0=27 End_B1=27
8722 10:02:27.963479 28, 0x0, End_B0=28 End_B1=28
8723 10:02:27.963606 29, 0x0, End_B0=29 End_B1=29
8724 10:02:27.967255 30, 0x0, End_B0=30 End_B1=30
8725 10:02:27.970302 31, 0x4141, End_B0=30 End_B1=30
8726 10:02:27.973746 Byte0 end_step=30 best_step=27
8727 10:02:27.977193 Byte1 end_step=30 best_step=27
8728 10:02:27.980105 Byte0 TX OE(2T, 0.5T) = (3, 3)
8729 10:02:27.980224 Byte1 TX OE(2T, 0.5T) = (3, 3)
8730 10:02:27.983934
8731 10:02:27.984026
8732 10:02:27.990130 [DQSOSCAuto] RK0, (LSB)MR18= 0x1523, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
8733 10:02:27.993355 CH1 RK0: MR19=303, MR18=1523
8734 10:02:28.000486 CH1_RK0: MR19=0x303, MR18=0x1523, DQSOSC=392, MR23=63, INC=24, DEC=16
8735 10:02:28.000615
8736 10:02:28.003360 ----->DramcWriteLeveling(PI) begin...
8737 10:02:28.003467 ==
8738 10:02:28.007043 Dram Type= 6, Freq= 0, CH_1, rank 1
8739 10:02:28.009977 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8740 10:02:28.010066 ==
8741 10:02:28.013749 Write leveling (Byte 0): 26 => 26
8742 10:02:28.016903 Write leveling (Byte 1): 29 => 29
8743 10:02:28.019885 DramcWriteLeveling(PI) end<-----
8744 10:02:28.020029
8745 10:02:28.020126 ==
8746 10:02:28.023767 Dram Type= 6, Freq= 0, CH_1, rank 1
8747 10:02:28.026726 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8748 10:02:28.026816 ==
8749 10:02:28.029925 [Gating] SW mode calibration
8750 10:02:28.036616 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8751 10:02:28.043678 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8752 10:02:28.046703 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8753 10:02:28.050366 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8754 10:02:28.056649 1 4 8 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
8755 10:02:28.059757 1 4 12 | B1->B0 | 3434 2d2d | 0 0 | (0 0) (0 0)
8756 10:02:28.063458 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8757 10:02:28.069920 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8758 10:02:28.073392 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8759 10:02:28.076544 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8760 10:02:28.083393 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8761 10:02:28.086844 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8762 10:02:28.089697 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8763 10:02:28.096503 1 5 12 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (1 0)
8764 10:02:28.099709 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
8765 10:02:28.103295 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8766 10:02:28.109957 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8767 10:02:28.112948 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8768 10:02:28.116784 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8769 10:02:28.122951 1 6 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8770 10:02:28.126647 1 6 8 | B1->B0 | 3838 2323 | 0 0 | (0 0) (0 0)
8771 10:02:28.129754 1 6 12 | B1->B0 | 4646 4242 | 0 0 | (0 0) (0 0)
8772 10:02:28.136561 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8773 10:02:28.139661 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8774 10:02:28.143312 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8775 10:02:28.146477 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8776 10:02:28.152796 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8777 10:02:28.156241 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8778 10:02:28.160006 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8779 10:02:28.166350 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8780 10:02:28.170115 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8781 10:02:28.173087 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8782 10:02:28.179991 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8783 10:02:28.182840 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8784 10:02:28.185942 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8785 10:02:28.192512 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8786 10:02:28.195905 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8787 10:02:28.199385 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8788 10:02:28.205675 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8789 10:02:28.209532 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8790 10:02:28.212251 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8791 10:02:28.218899 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8792 10:02:28.221994 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8793 10:02:28.225844 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8794 10:02:28.232565 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8795 10:02:28.235805 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8796 10:02:28.238898 Total UI for P1: 0, mck2ui 16
8797 10:02:28.242523 best dqsien dly found for B1: ( 1, 9, 8)
8798 10:02:28.245818 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8799 10:02:28.248902 Total UI for P1: 0, mck2ui 16
8800 10:02:28.252138 best dqsien dly found for B0: ( 1, 9, 12)
8801 10:02:28.255848 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8802 10:02:28.258940 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8803 10:02:28.259056
8804 10:02:28.265534 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8805 10:02:28.268713 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8806 10:02:28.272310 [Gating] SW calibration Done
8807 10:02:28.272415 ==
8808 10:02:28.275392 Dram Type= 6, Freq= 0, CH_1, rank 1
8809 10:02:28.279047 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8810 10:02:28.279162 ==
8811 10:02:28.279268 RX Vref Scan: 0
8812 10:02:28.279375
8813 10:02:28.282079 RX Vref 0 -> 0, step: 1
8814 10:02:28.282196
8815 10:02:28.285821 RX Delay 0 -> 252, step: 8
8816 10:02:28.288748 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8817 10:02:28.292243 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8818 10:02:28.295589 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8819 10:02:28.302116 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8820 10:02:28.305650 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8821 10:02:28.309120 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8822 10:02:28.312589 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8823 10:02:28.315406 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8824 10:02:28.322489 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8825 10:02:28.325345 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8826 10:02:28.328545 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8827 10:02:28.332253 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8828 10:02:28.335288 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8829 10:02:28.342287 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8830 10:02:28.345235 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8831 10:02:28.348762 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8832 10:02:28.348856 ==
8833 10:02:28.351754 Dram Type= 6, Freq= 0, CH_1, rank 1
8834 10:02:28.355135 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8835 10:02:28.359178 ==
8836 10:02:28.359315 DQS Delay:
8837 10:02:28.359413 DQS0 = 0, DQS1 = 0
8838 10:02:28.361935 DQM Delay:
8839 10:02:28.362035 DQM0 = 136, DQM1 = 133
8840 10:02:28.365063 DQ Delay:
8841 10:02:28.368298 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8842 10:02:28.371922 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8843 10:02:28.374970 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8844 10:02:28.378332 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8845 10:02:28.378463
8846 10:02:28.378559
8847 10:02:28.378642 ==
8848 10:02:28.381944 Dram Type= 6, Freq= 0, CH_1, rank 1
8849 10:02:28.384875 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8850 10:02:28.384967 ==
8851 10:02:28.388690
8852 10:02:28.388777
8853 10:02:28.388865 TX Vref Scan disable
8854 10:02:28.391905 == TX Byte 0 ==
8855 10:02:28.395537 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8856 10:02:28.398556 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8857 10:02:28.401783 == TX Byte 1 ==
8858 10:02:28.405063 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8859 10:02:28.408693 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8860 10:02:28.408786 ==
8861 10:02:28.411679 Dram Type= 6, Freq= 0, CH_1, rank 1
8862 10:02:28.418647 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8863 10:02:28.418733 ==
8864 10:02:28.429884
8865 10:02:28.433117 TX Vref early break, caculate TX vref
8866 10:02:28.436342 TX Vref=16, minBit 0, minWin=22, winSum=382
8867 10:02:28.439818 TX Vref=18, minBit 0, minWin=23, winSum=390
8868 10:02:28.443203 TX Vref=20, minBit 1, minWin=24, winSum=398
8869 10:02:28.446225 TX Vref=22, minBit 0, minWin=25, winSum=411
8870 10:02:28.449996 TX Vref=24, minBit 0, minWin=24, winSum=415
8871 10:02:28.456633 TX Vref=26, minBit 0, minWin=25, winSum=424
8872 10:02:28.459674 TX Vref=28, minBit 0, minWin=26, winSum=427
8873 10:02:28.462963 TX Vref=30, minBit 0, minWin=25, winSum=422
8874 10:02:28.466194 TX Vref=32, minBit 1, minWin=25, winSum=411
8875 10:02:28.469278 TX Vref=34, minBit 0, minWin=24, winSum=403
8876 10:02:28.476431 [TxChooseVref] Worse bit 0, Min win 26, Win sum 427, Final Vref 28
8877 10:02:28.476536
8878 10:02:28.479573 Final TX Range 0 Vref 28
8879 10:02:28.479653
8880 10:02:28.479739 ==
8881 10:02:28.482870 Dram Type= 6, Freq= 0, CH_1, rank 1
8882 10:02:28.486599 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8883 10:02:28.486705 ==
8884 10:02:28.486815
8885 10:02:28.486921
8886 10:02:28.489459 TX Vref Scan disable
8887 10:02:28.496445 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8888 10:02:28.496558 == TX Byte 0 ==
8889 10:02:28.499612 u2DelayCellOfst[0]=17 cells (5 PI)
8890 10:02:28.502650 u2DelayCellOfst[1]=10 cells (3 PI)
8891 10:02:28.506190 u2DelayCellOfst[2]=0 cells (0 PI)
8892 10:02:28.509433 u2DelayCellOfst[3]=6 cells (2 PI)
8893 10:02:28.513119 u2DelayCellOfst[4]=10 cells (3 PI)
8894 10:02:28.516185 u2DelayCellOfst[5]=17 cells (5 PI)
8895 10:02:28.519813 u2DelayCellOfst[6]=20 cells (6 PI)
8896 10:02:28.519920 u2DelayCellOfst[7]=6 cells (2 PI)
8897 10:02:28.526170 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8898 10:02:28.529479 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8899 10:02:28.529599 == TX Byte 1 ==
8900 10:02:28.532682 u2DelayCellOfst[8]=0 cells (0 PI)
8901 10:02:28.535970 u2DelayCellOfst[9]=3 cells (1 PI)
8902 10:02:28.539172 u2DelayCellOfst[10]=10 cells (3 PI)
8903 10:02:28.542938 u2DelayCellOfst[11]=6 cells (2 PI)
8904 10:02:28.546237 u2DelayCellOfst[12]=17 cells (5 PI)
8905 10:02:28.549402 u2DelayCellOfst[13]=17 cells (5 PI)
8906 10:02:28.553139 u2DelayCellOfst[14]=17 cells (5 PI)
8907 10:02:28.555855 u2DelayCellOfst[15]=17 cells (5 PI)
8908 10:02:28.559789 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8909 10:02:28.566416 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8910 10:02:28.566513 DramC Write-DBI on
8911 10:02:28.566610 ==
8912 10:02:28.569323 Dram Type= 6, Freq= 0, CH_1, rank 1
8913 10:02:28.573100 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8914 10:02:28.573207 ==
8915 10:02:28.576280
8916 10:02:28.576365
8917 10:02:28.576462 TX Vref Scan disable
8918 10:02:28.579490 == TX Byte 0 ==
8919 10:02:28.582496 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8920 10:02:28.586421 == TX Byte 1 ==
8921 10:02:28.589703 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8922 10:02:28.589814 DramC Write-DBI off
8923 10:02:28.589908
8924 10:02:28.592892 [DATLAT]
8925 10:02:28.592999 Freq=1600, CH1 RK1
8926 10:02:28.593091
8927 10:02:28.595851 DATLAT Default: 0xf
8928 10:02:28.595924 0, 0xFFFF, sum = 0
8929 10:02:28.599515 1, 0xFFFF, sum = 0
8930 10:02:28.599630 2, 0xFFFF, sum = 0
8931 10:02:28.602556 3, 0xFFFF, sum = 0
8932 10:02:28.602670 4, 0xFFFF, sum = 0
8933 10:02:28.605953 5, 0xFFFF, sum = 0
8934 10:02:28.609043 6, 0xFFFF, sum = 0
8935 10:02:28.609151 7, 0xFFFF, sum = 0
8936 10:02:28.612624 8, 0xFFFF, sum = 0
8937 10:02:28.612732 9, 0xFFFF, sum = 0
8938 10:02:28.616334 10, 0xFFFF, sum = 0
8939 10:02:28.616410 11, 0xFFFF, sum = 0
8940 10:02:28.619243 12, 0xFFFF, sum = 0
8941 10:02:28.619348 13, 0xFFFF, sum = 0
8942 10:02:28.622318 14, 0x0, sum = 1
8943 10:02:28.622427 15, 0x0, sum = 2
8944 10:02:28.626109 16, 0x0, sum = 3
8945 10:02:28.626219 17, 0x0, sum = 4
8946 10:02:28.629217 best_step = 15
8947 10:02:28.629305
8948 10:02:28.629371 ==
8949 10:02:28.632347 Dram Type= 6, Freq= 0, CH_1, rank 1
8950 10:02:28.636316 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8951 10:02:28.636403 ==
8952 10:02:28.636468 RX Vref Scan: 0
8953 10:02:28.636529
8954 10:02:28.639509 RX Vref 0 -> 0, step: 1
8955 10:02:28.639610
8956 10:02:28.642838 RX Delay 19 -> 252, step: 4
8957 10:02:28.645929 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8958 10:02:28.652366 iDelay=195, Bit 1, Center 128 (79 ~ 178) 100
8959 10:02:28.656353 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8960 10:02:28.659576 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8961 10:02:28.662749 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8962 10:02:28.665629 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8963 10:02:28.669317 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8964 10:02:28.675558 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
8965 10:02:28.678969 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8966 10:02:28.682224 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8967 10:02:28.685772 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
8968 10:02:28.688978 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8969 10:02:28.695960 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
8970 10:02:28.699152 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8971 10:02:28.702297 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8972 10:02:28.705916 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
8973 10:02:28.706004 ==
8974 10:02:28.709019 Dram Type= 6, Freq= 0, CH_1, rank 1
8975 10:02:28.715379 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8976 10:02:28.715464 ==
8977 10:02:28.715530 DQS Delay:
8978 10:02:28.718989 DQS0 = 0, DQS1 = 0
8979 10:02:28.719072 DQM Delay:
8980 10:02:28.721937 DQM0 = 134, DQM1 = 130
8981 10:02:28.722051 DQ Delay:
8982 10:02:28.725518 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =130
8983 10:02:28.728557 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
8984 10:02:28.732033 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =124
8985 10:02:28.735451 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =138
8986 10:02:28.735539
8987 10:02:28.735604
8988 10:02:28.735665
8989 10:02:28.738485 [DramC_TX_OE_Calibration] TA2
8990 10:02:28.741834 Original DQ_B0 (3 6) =30, OEN = 27
8991 10:02:28.745721 Original DQ_B1 (3 6) =30, OEN = 27
8992 10:02:28.748856 24, 0x0, End_B0=24 End_B1=24
8993 10:02:28.752078 25, 0x0, End_B0=25 End_B1=25
8994 10:02:28.752167 26, 0x0, End_B0=26 End_B1=26
8995 10:02:28.755309 27, 0x0, End_B0=27 End_B1=27
8996 10:02:28.758990 28, 0x0, End_B0=28 End_B1=28
8997 10:02:28.761783 29, 0x0, End_B0=29 End_B1=29
8998 10:02:28.761876 30, 0x0, End_B0=30 End_B1=30
8999 10:02:28.765573 31, 0x5151, End_B0=30 End_B1=30
9000 10:02:28.768788 Byte0 end_step=30 best_step=27
9001 10:02:28.771801 Byte1 end_step=30 best_step=27
9002 10:02:28.775508 Byte0 TX OE(2T, 0.5T) = (3, 3)
9003 10:02:28.778699 Byte1 TX OE(2T, 0.5T) = (3, 3)
9004 10:02:28.778793
9005 10:02:28.778860
9006 10:02:28.785543 [DQSOSCAuto] RK1, (LSB)MR18= 0x2107, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 393 ps
9007 10:02:28.788739 CH1 RK1: MR19=303, MR18=2107
9008 10:02:28.795218 CH1_RK1: MR19=0x303, MR18=0x2107, DQSOSC=393, MR23=63, INC=23, DEC=15
9009 10:02:28.798759 [RxdqsGatingPostProcess] freq 1600
9010 10:02:28.802017 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9011 10:02:28.805589 best DQS0 dly(2T, 0.5T) = (1, 1)
9012 10:02:28.808625 best DQS1 dly(2T, 0.5T) = (1, 1)
9013 10:02:28.811904 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9014 10:02:28.815390 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9015 10:02:28.818541 best DQS0 dly(2T, 0.5T) = (1, 1)
9016 10:02:28.822306 best DQS1 dly(2T, 0.5T) = (1, 1)
9017 10:02:28.825529 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9018 10:02:28.828606 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9019 10:02:28.831791 Pre-setting of DQS Precalculation
9020 10:02:28.834971 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9021 10:02:28.842121 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9022 10:02:28.848352 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9023 10:02:28.851643
9024 10:02:28.851729
9025 10:02:28.851795 [Calibration Summary] 3200 Mbps
9026 10:02:28.855463 CH 0, Rank 0
9027 10:02:28.855551 SW Impedance : PASS
9028 10:02:28.858517 DUTY Scan : NO K
9029 10:02:28.861767 ZQ Calibration : PASS
9030 10:02:28.861855 Jitter Meter : NO K
9031 10:02:28.864929 CBT Training : PASS
9032 10:02:28.868815 Write leveling : PASS
9033 10:02:28.868906 RX DQS gating : PASS
9034 10:02:28.871900 RX DQ/DQS(RDDQC) : PASS
9035 10:02:28.875246 TX DQ/DQS : PASS
9036 10:02:28.875336 RX DATLAT : PASS
9037 10:02:28.878401 RX DQ/DQS(Engine): PASS
9038 10:02:28.882230 TX OE : PASS
9039 10:02:28.882320 All Pass.
9040 10:02:28.882386
9041 10:02:28.882470 CH 0, Rank 1
9042 10:02:28.885672 SW Impedance : PASS
9043 10:02:28.888527 DUTY Scan : NO K
9044 10:02:28.888613 ZQ Calibration : PASS
9045 10:02:28.891693 Jitter Meter : NO K
9046 10:02:28.891780 CBT Training : PASS
9047 10:02:28.895544 Write leveling : PASS
9048 10:02:28.898775 RX DQS gating : PASS
9049 10:02:28.898896 RX DQ/DQS(RDDQC) : PASS
9050 10:02:28.901928 TX DQ/DQS : PASS
9051 10:02:28.905193 RX DATLAT : PASS
9052 10:02:28.905298 RX DQ/DQS(Engine): PASS
9053 10:02:28.908232 TX OE : PASS
9054 10:02:28.908308 All Pass.
9055 10:02:28.908371
9056 10:02:28.911897 CH 1, Rank 0
9057 10:02:28.911969 SW Impedance : PASS
9058 10:02:28.915369 DUTY Scan : NO K
9059 10:02:28.918201 ZQ Calibration : PASS
9060 10:02:28.918297 Jitter Meter : NO K
9061 10:02:28.921779 CBT Training : PASS
9062 10:02:28.924949 Write leveling : PASS
9063 10:02:28.925075 RX DQS gating : PASS
9064 10:02:28.928352 RX DQ/DQS(RDDQC) : PASS
9065 10:02:28.932016 TX DQ/DQS : PASS
9066 10:02:28.932110 RX DATLAT : PASS
9067 10:02:28.935050 RX DQ/DQS(Engine): PASS
9068 10:02:28.935178 TX OE : PASS
9069 10:02:28.938541 All Pass.
9070 10:02:28.938650
9071 10:02:28.938753 CH 1, Rank 1
9072 10:02:28.941750 SW Impedance : PASS
9073 10:02:28.941847 DUTY Scan : NO K
9074 10:02:28.944815 ZQ Calibration : PASS
9075 10:02:28.948659 Jitter Meter : NO K
9076 10:02:28.948772 CBT Training : PASS
9077 10:02:28.951708 Write leveling : PASS
9078 10:02:28.954581 RX DQS gating : PASS
9079 10:02:28.954672 RX DQ/DQS(RDDQC) : PASS
9080 10:02:28.958342 TX DQ/DQS : PASS
9081 10:02:28.961464 RX DATLAT : PASS
9082 10:02:28.961552 RX DQ/DQS(Engine): PASS
9083 10:02:28.964634 TX OE : PASS
9084 10:02:28.964727 All Pass.
9085 10:02:28.964820
9086 10:02:28.968224 DramC Write-DBI on
9087 10:02:28.971829 PER_BANK_REFRESH: Hybrid Mode
9088 10:02:28.971914 TX_TRACKING: ON
9089 10:02:28.981347 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9090 10:02:28.988189 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9091 10:02:28.994631 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9092 10:02:28.998443 [FAST_K] Save calibration result to emmc
9093 10:02:29.001446 sync common calibartion params.
9094 10:02:29.004521 sync cbt_mode0:1, 1:1
9095 10:02:29.007899 dram_init: ddr_geometry: 2
9096 10:02:29.007981 dram_init: ddr_geometry: 2
9097 10:02:29.011649 dram_init: ddr_geometry: 2
9098 10:02:29.014879 0:dram_rank_size:100000000
9099 10:02:29.018002 1:dram_rank_size:100000000
9100 10:02:29.021324 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9101 10:02:29.024486 DFS_SHUFFLE_HW_MODE: ON
9102 10:02:29.028273 dramc_set_vcore_voltage set vcore to 725000
9103 10:02:29.031020 Read voltage for 1600, 0
9104 10:02:29.031109 Vio18 = 0
9105 10:02:29.031182 Vcore = 725000
9106 10:02:29.034671 Vdram = 0
9107 10:02:29.034775 Vddq = 0
9108 10:02:29.034882 Vmddr = 0
9109 10:02:29.037887 switch to 3200 Mbps bootup
9110 10:02:29.040998 [DramcRunTimeConfig]
9111 10:02:29.041102 PHYPLL
9112 10:02:29.041209 DPM_CONTROL_AFTERK: ON
9113 10:02:29.044991 PER_BANK_REFRESH: ON
9114 10:02:29.048192 REFRESH_OVERHEAD_REDUCTION: ON
9115 10:02:29.048280 CMD_PICG_NEW_MODE: OFF
9116 10:02:29.051113 XRTWTW_NEW_MODE: ON
9117 10:02:29.051201 XRTRTR_NEW_MODE: ON
9118 10:02:29.054538 TX_TRACKING: ON
9119 10:02:29.054619 RDSEL_TRACKING: OFF
9120 10:02:29.058167 DQS Precalculation for DVFS: ON
9121 10:02:29.061518 RX_TRACKING: OFF
9122 10:02:29.061677 HW_GATING DBG: ON
9123 10:02:29.064563 ZQCS_ENABLE_LP4: ON
9124 10:02:29.064707 RX_PICG_NEW_MODE: ON
9125 10:02:29.067878 TX_PICG_NEW_MODE: ON
9126 10:02:29.071481 ENABLE_RX_DCM_DPHY: ON
9127 10:02:29.071627 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9128 10:02:29.074875 DUMMY_READ_FOR_TRACKING: OFF
9129 10:02:29.077852 !!! SPM_CONTROL_AFTERK: OFF
9130 10:02:29.081347 !!! SPM could not control APHY
9131 10:02:29.081488 IMPEDANCE_TRACKING: ON
9132 10:02:29.084415 TEMP_SENSOR: ON
9133 10:02:29.084502 HW_SAVE_FOR_SR: OFF
9134 10:02:29.087781 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9135 10:02:29.094751 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9136 10:02:29.094855 Read ODT Tracking: ON
9137 10:02:29.098045 Refresh Rate DeBounce: ON
9138 10:02:29.098125 DFS_NO_QUEUE_FLUSH: ON
9139 10:02:29.101199 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9140 10:02:29.104576 ENABLE_DFS_RUNTIME_MRW: OFF
9141 10:02:29.107669 DDR_RESERVE_NEW_MODE: ON
9142 10:02:29.107748 MR_CBT_SWITCH_FREQ: ON
9143 10:02:29.110834 =========================
9144 10:02:29.130257 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9145 10:02:29.133492 dram_init: ddr_geometry: 2
9146 10:02:29.151953 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9147 10:02:29.155178 dram_init: dram init end (result: 0)
9148 10:02:29.161995 DRAM-K: Full calibration passed in 24475 msecs
9149 10:02:29.165110 MRC: failed to locate region type 0.
9150 10:02:29.165229 DRAM rank0 size:0x100000000,
9151 10:02:29.168672 DRAM rank1 size=0x100000000
9152 10:02:29.178487 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9153 10:02:29.185213 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9154 10:02:29.191607 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9155 10:02:29.198329 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9156 10:02:29.201668 DRAM rank0 size:0x100000000,
9157 10:02:29.204988 DRAM rank1 size=0x100000000
9158 10:02:29.205109 CBMEM:
9159 10:02:29.208343 IMD: root @ 0xfffff000 254 entries.
9160 10:02:29.211993 IMD: root @ 0xffffec00 62 entries.
9161 10:02:29.215275 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9162 10:02:29.218424 WARNING: RO_VPD is uninitialized or empty.
9163 10:02:29.224785 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9164 10:02:29.231878 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9165 10:02:29.244530 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9166 10:02:29.255922 BS: romstage times (exec / console): total (unknown) / 24006 ms
9167 10:02:29.256041
9168 10:02:29.256116
9169 10:02:29.266360 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9170 10:02:29.269485 ARM64: Exception handlers installed.
9171 10:02:29.272759 ARM64: Testing exception
9172 10:02:29.272844 ARM64: Done test exception
9173 10:02:29.275927 Enumerating buses...
9174 10:02:29.279803 Show all devs... Before device enumeration.
9175 10:02:29.282954 Root Device: enabled 1
9176 10:02:29.286244 CPU_CLUSTER: 0: enabled 1
9177 10:02:29.286367 CPU: 00: enabled 1
9178 10:02:29.289352 Compare with tree...
9179 10:02:29.289444 Root Device: enabled 1
9180 10:02:29.293305 CPU_CLUSTER: 0: enabled 1
9181 10:02:29.296324 CPU: 00: enabled 1
9182 10:02:29.296430 Root Device scanning...
9183 10:02:29.299579 scan_static_bus for Root Device
9184 10:02:29.302601 CPU_CLUSTER: 0 enabled
9185 10:02:29.305936 scan_static_bus for Root Device done
9186 10:02:29.309282 scan_bus: bus Root Device finished in 8 msecs
9187 10:02:29.309386 done
9188 10:02:29.316254 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9189 10:02:29.319479 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9190 10:02:29.325856 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9191 10:02:29.329311 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9192 10:02:29.332357 Allocating resources...
9193 10:02:29.332470 Reading resources...
9194 10:02:29.339191 Root Device read_resources bus 0 link: 0
9195 10:02:29.339320 DRAM rank0 size:0x100000000,
9196 10:02:29.342306 DRAM rank1 size=0x100000000
9197 10:02:29.345537 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9198 10:02:29.349304 CPU: 00 missing read_resources
9199 10:02:29.352476 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9200 10:02:29.358890 Root Device read_resources bus 0 link: 0 done
9201 10:02:29.358985 Done reading resources.
9202 10:02:29.365712 Show resources in subtree (Root Device)...After reading.
9203 10:02:29.368817 Root Device child on link 0 CPU_CLUSTER: 0
9204 10:02:29.372028 CPU_CLUSTER: 0 child on link 0 CPU: 00
9205 10:02:29.382296 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9206 10:02:29.382412 CPU: 00
9207 10:02:29.385615 Root Device assign_resources, bus 0 link: 0
9208 10:02:29.388713 CPU_CLUSTER: 0 missing set_resources
9209 10:02:29.395249 Root Device assign_resources, bus 0 link: 0 done
9210 10:02:29.395399 Done setting resources.
9211 10:02:29.402053 Show resources in subtree (Root Device)...After assigning values.
9212 10:02:29.405182 Root Device child on link 0 CPU_CLUSTER: 0
9213 10:02:29.408898 CPU_CLUSTER: 0 child on link 0 CPU: 00
9214 10:02:29.418779 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9215 10:02:29.418909 CPU: 00
9216 10:02:29.422006 Done allocating resources.
9217 10:02:29.425204 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9218 10:02:29.428964 Enabling resources...
9219 10:02:29.429098 done.
9220 10:02:29.435254 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9221 10:02:29.435408 Initializing devices...
9222 10:02:29.438843 Root Device init
9223 10:02:29.438927 init hardware done!
9224 10:02:29.442042 0x00000018: ctrlr->caps
9225 10:02:29.445430 52.000 MHz: ctrlr->f_max
9226 10:02:29.445551 0.400 MHz: ctrlr->f_min
9227 10:02:29.448350 0x40ff8080: ctrlr->voltages
9228 10:02:29.448464 sclk: 390625
9229 10:02:29.452057 Bus Width = 1
9230 10:02:29.452166 sclk: 390625
9231 10:02:29.455209 Bus Width = 1
9232 10:02:29.455293 Early init status = 3
9233 10:02:29.461793 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9234 10:02:29.465049 in-header: 03 fc 00 00 01 00 00 00
9235 10:02:29.468866 in-data: 00
9236 10:02:29.472019 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9237 10:02:29.476137 in-header: 03 fd 00 00 00 00 00 00
9238 10:02:29.479538 in-data:
9239 10:02:29.482508 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9240 10:02:29.487100 in-header: 03 fc 00 00 01 00 00 00
9241 10:02:29.490843 in-data: 00
9242 10:02:29.493984 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9243 10:02:29.499691 in-header: 03 fd 00 00 00 00 00 00
9244 10:02:29.502963 in-data:
9245 10:02:29.506153 [SSUSB] Setting up USB HOST controller...
9246 10:02:29.509403 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9247 10:02:29.512640 [SSUSB] phy power-on done.
9248 10:02:29.516478 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9249 10:02:29.522458 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9250 10:02:29.526287 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9251 10:02:29.532764 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9252 10:02:29.539009 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9253 10:02:29.545978 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9254 10:02:29.552654 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9255 10:02:29.558931 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9256 10:02:29.562735 SPM: binary array size = 0x9dc
9257 10:02:29.566033 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9258 10:02:29.572668 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9259 10:02:29.579045 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9260 10:02:29.582424 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9261 10:02:29.585829 configure_display: Starting display init
9262 10:02:29.622421 anx7625_power_on_init: Init interface.
9263 10:02:29.626128 anx7625_disable_pd_protocol: Disabled PD feature.
9264 10:02:29.629115 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9265 10:02:29.657240 anx7625_start_dp_work: Secure OCM version=00
9266 10:02:29.660379 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9267 10:02:29.675365 sp_tx_get_edid_block: EDID Block = 1
9268 10:02:29.777966 Extracted contents:
9269 10:02:29.781169 header: 00 ff ff ff ff ff ff 00
9270 10:02:29.784161 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9271 10:02:29.787722 version: 01 04
9272 10:02:29.790845 basic params: 95 1f 11 78 0a
9273 10:02:29.794152 chroma info: 76 90 94 55 54 90 27 21 50 54
9274 10:02:29.797444 established: 00 00 00
9275 10:02:29.804002 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9276 10:02:29.807552 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9277 10:02:29.813916 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9278 10:02:29.820954 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9279 10:02:29.827294 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9280 10:02:29.830965 extensions: 00
9281 10:02:29.831072 checksum: fb
9282 10:02:29.831140
9283 10:02:29.834086 Manufacturer: IVO Model 57d Serial Number 0
9284 10:02:29.837425 Made week 0 of 2020
9285 10:02:29.837542 EDID version: 1.4
9286 10:02:29.840730 Digital display
9287 10:02:29.843957 6 bits per primary color channel
9288 10:02:29.844067 DisplayPort interface
9289 10:02:29.847153 Maximum image size: 31 cm x 17 cm
9290 10:02:29.850815 Gamma: 220%
9291 10:02:29.850922 Check DPMS levels
9292 10:02:29.853842 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9293 10:02:29.860284 First detailed timing is preferred timing
9294 10:02:29.860410 Established timings supported:
9295 10:02:29.863718 Standard timings supported:
9296 10:02:29.867008 Detailed timings
9297 10:02:29.870261 Hex of detail: 383680a07038204018303c0035ae10000019
9298 10:02:29.873502 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9299 10:02:29.880645 0780 0798 07c8 0820 hborder 0
9300 10:02:29.883768 0438 043b 0447 0458 vborder 0
9301 10:02:29.887098 -hsync -vsync
9302 10:02:29.887180 Did detailed timing
9303 10:02:29.893539 Hex of detail: 000000000000000000000000000000000000
9304 10:02:29.893666 Manufacturer-specified data, tag 0
9305 10:02:29.900732 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9306 10:02:29.904080 ASCII string: InfoVision
9307 10:02:29.907477 Hex of detail: 000000fe00523134304e574635205248200a
9308 10:02:29.910500 ASCII string: R140NWF5 RH
9309 10:02:29.910589 Checksum
9310 10:02:29.913720 Checksum: 0xfb (valid)
9311 10:02:29.916993 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9312 10:02:29.920177 DSI data_rate: 832800000 bps
9313 10:02:29.927152 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9314 10:02:29.931011 anx7625_parse_edid: pixelclock(138800).
9315 10:02:29.934006 hactive(1920), hsync(48), hfp(24), hbp(88)
9316 10:02:29.937182 vactive(1080), vsync(12), vfp(3), vbp(17)
9317 10:02:29.940782 anx7625_dsi_config: config dsi.
9318 10:02:29.946946 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9319 10:02:29.959630 anx7625_dsi_config: success to config DSI
9320 10:02:29.963330 anx7625_dp_start: MIPI phy setup OK.
9321 10:02:29.966694 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9322 10:02:29.969771 mtk_ddp_mode_set invalid vrefresh 60
9323 10:02:29.972931 main_disp_path_setup
9324 10:02:29.973027 ovl_layer_smi_id_en
9325 10:02:29.976527 ovl_layer_smi_id_en
9326 10:02:29.976639 ccorr_config
9327 10:02:29.976734 aal_config
9328 10:02:29.979437 gamma_config
9329 10:02:29.979556 postmask_config
9330 10:02:29.983242 dither_config
9331 10:02:29.986411 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9332 10:02:29.992855 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9333 10:02:29.996046 Root Device init finished in 554 msecs
9334 10:02:29.999684 CPU_CLUSTER: 0 init
9335 10:02:30.006111 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9336 10:02:30.009690 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9337 10:02:30.012829 APU_MBOX 0x190000b0 = 0x10001
9338 10:02:30.016133 APU_MBOX 0x190001b0 = 0x10001
9339 10:02:30.019731 APU_MBOX 0x190005b0 = 0x10001
9340 10:02:30.022804 APU_MBOX 0x190006b0 = 0x10001
9341 10:02:30.026017 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9342 10:02:30.038758 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9343 10:02:30.051104 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9344 10:02:30.057758 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9345 10:02:30.069618 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9346 10:02:30.078720 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9347 10:02:30.081733 CPU_CLUSTER: 0 init finished in 81 msecs
9348 10:02:30.085261 Devices initialized
9349 10:02:30.088256 Show all devs... After init.
9350 10:02:30.088378 Root Device: enabled 1
9351 10:02:30.091614 CPU_CLUSTER: 0: enabled 1
9352 10:02:30.095106 CPU: 00: enabled 1
9353 10:02:30.098145 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9354 10:02:30.101955 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9355 10:02:30.105180 ELOG: NV offset 0x57f000 size 0x1000
9356 10:02:30.111542 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9357 10:02:30.118258 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9358 10:02:30.121996 ELOG: Event(17) added with size 13 at 2023-11-24 10:00:19 UTC
9359 10:02:30.125153 out: cmd=0x121: 03 db 21 01 00 00 00 00
9360 10:02:30.128921 in-header: 03 c9 00 00 2c 00 00 00
9361 10:02:30.141817 in-data: 96 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9362 10:02:30.148802 ELOG: Event(A1) added with size 10 at 2023-11-24 10:00:19 UTC
9363 10:02:30.155215 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9364 10:02:30.162176 ELOG: Event(A0) added with size 9 at 2023-11-24 10:00:19 UTC
9365 10:02:30.165066 elog_add_boot_reason: Logged dev mode boot
9366 10:02:30.168613 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9367 10:02:30.172257 Finalize devices...
9368 10:02:30.172385 Devices finalized
9369 10:02:30.178870 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9370 10:02:30.181972 Writing coreboot table at 0xffe64000
9371 10:02:30.185248 0. 000000000010a000-0000000000113fff: RAMSTAGE
9372 10:02:30.188550 1. 0000000040000000-00000000400fffff: RAM
9373 10:02:30.191657 2. 0000000040100000-000000004032afff: RAMSTAGE
9374 10:02:30.198352 3. 000000004032b000-00000000545fffff: RAM
9375 10:02:30.201706 4. 0000000054600000-000000005465ffff: BL31
9376 10:02:30.205436 5. 0000000054660000-00000000ffe63fff: RAM
9377 10:02:30.211703 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9378 10:02:30.215333 7. 0000000100000000-000000023fffffff: RAM
9379 10:02:30.215455 Passing 5 GPIOs to payload:
9380 10:02:30.221769 NAME | PORT | POLARITY | VALUE
9381 10:02:30.224737 EC in RW | 0x000000aa | low | undefined
9382 10:02:30.231896 EC interrupt | 0x00000005 | low | undefined
9383 10:02:30.234964 TPM interrupt | 0x000000ab | high | undefined
9384 10:02:30.238343 SD card detect | 0x00000011 | high | undefined
9385 10:02:30.244682 speaker enable | 0x00000093 | high | undefined
9386 10:02:30.248361 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9387 10:02:30.251540 in-header: 03 f9 00 00 02 00 00 00
9388 10:02:30.251650 in-data: 02 00
9389 10:02:30.254721 ADC[4]: Raw value=904357 ID=7
9390 10:02:30.257838 ADC[3]: Raw value=213441 ID=1
9391 10:02:30.261767 RAM Code: 0x71
9392 10:02:30.261891 ADC[6]: Raw value=75701 ID=0
9393 10:02:30.265041 ADC[5]: Raw value=213072 ID=1
9394 10:02:30.265166 SKU Code: 0x1
9395 10:02:30.271862 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 2e6b
9396 10:02:30.274798 coreboot table: 964 bytes.
9397 10:02:30.278193 IMD ROOT 0. 0xfffff000 0x00001000
9398 10:02:30.281208 IMD SMALL 1. 0xffffe000 0x00001000
9399 10:02:30.284922 RO MCACHE 2. 0xffffc000 0x00001104
9400 10:02:30.288265 CONSOLE 3. 0xfff7c000 0x00080000
9401 10:02:30.291486 FMAP 4. 0xfff7b000 0x00000452
9402 10:02:30.294551 TIME STAMP 5. 0xfff7a000 0x00000910
9403 10:02:30.297733 VBOOT WORK 6. 0xfff66000 0x00014000
9404 10:02:30.301573 RAMOOPS 7. 0xffe66000 0x00100000
9405 10:02:30.304800 COREBOOT 8. 0xffe64000 0x00002000
9406 10:02:30.304909 IMD small region:
9407 10:02:30.308141 IMD ROOT 0. 0xffffec00 0x00000400
9408 10:02:30.311216 VPD 1. 0xffffeb80 0x0000006c
9409 10:02:30.315011 MMC STATUS 2. 0xffffeb60 0x00000004
9410 10:02:30.321407 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9411 10:02:30.324642 Probing TPM: done!
9412 10:02:30.327798 Connected to device vid:did:rid of 1ae0:0028:00
9413 10:02:30.337655 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9414 10:02:30.341196 Initialized TPM device CR50 revision 0
9415 10:02:30.345156 Checking cr50 for pending updates
9416 10:02:30.348475 Reading cr50 TPM mode
9417 10:02:30.358389 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9418 10:02:30.363956 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9419 10:02:30.403745 read SPI 0x3990ec 0x4f1b0: 34851 us, 9297 KB/s, 74.376 Mbps
9420 10:02:30.406962 Checking segment from ROM address 0x40100000
9421 10:02:30.410159 Checking segment from ROM address 0x4010001c
9422 10:02:30.417225 Loading segment from ROM address 0x40100000
9423 10:02:30.417370 code (compression=0)
9424 10:02:30.427228 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9425 10:02:30.433609 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9426 10:02:30.433767 it's not compressed!
9427 10:02:30.440560 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9428 10:02:30.444196 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9429 10:02:30.464291 Loading segment from ROM address 0x4010001c
9430 10:02:30.464470 Entry Point 0x80000000
9431 10:02:30.467630 Loaded segments
9432 10:02:30.470952 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9433 10:02:30.477531 Jumping to boot code at 0x80000000(0xffe64000)
9434 10:02:30.484603 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9435 10:02:30.491265 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9436 10:02:30.499035 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9437 10:02:30.502249 Checking segment from ROM address 0x40100000
9438 10:02:30.505390 Checking segment from ROM address 0x4010001c
9439 10:02:30.511808 Loading segment from ROM address 0x40100000
9440 10:02:30.511957 code (compression=1)
9441 10:02:30.518552 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9442 10:02:30.528642 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9443 10:02:30.528791 using LZMA
9444 10:02:30.537252 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9445 10:02:30.543768 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9446 10:02:30.546863 Loading segment from ROM address 0x4010001c
9447 10:02:30.547019 Entry Point 0x54601000
9448 10:02:30.550521 Loaded segments
9449 10:02:30.553584 NOTICE: MT8192 bl31_setup
9450 10:02:30.561188 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9451 10:02:30.564072 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9452 10:02:30.567520 WARNING: region 0:
9453 10:02:30.571370 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9454 10:02:30.571502 WARNING: region 1:
9455 10:02:30.577866 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9456 10:02:30.577962 WARNING: region 2:
9457 10:02:30.584293 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9458 10:02:30.587436 WARNING: region 3:
9459 10:02:30.591239 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9460 10:02:30.594233 WARNING: region 4:
9461 10:02:30.597945 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9462 10:02:30.601099 WARNING: region 5:
9463 10:02:30.604341 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9464 10:02:30.607714 WARNING: region 6:
9465 10:02:30.610953 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9466 10:02:30.611066 WARNING: region 7:
9467 10:02:30.617924 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9468 10:02:30.624221 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9469 10:02:30.627488 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9470 10:02:30.630886 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9471 10:02:30.637369 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9472 10:02:30.640897 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9473 10:02:30.644548 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9474 10:02:30.650977 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9475 10:02:30.654035 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9476 10:02:30.657651 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9477 10:02:30.664399 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9478 10:02:30.667381 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9479 10:02:30.671122 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9480 10:02:30.677669 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9481 10:02:30.680903 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9482 10:02:30.687839 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9483 10:02:30.691250 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9484 10:02:30.694452 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9485 10:02:30.701219 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9486 10:02:30.704205 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9487 10:02:30.707889 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9488 10:02:30.714277 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9489 10:02:30.717448 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9490 10:02:30.724432 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9491 10:02:30.727570 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9492 10:02:30.731052 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9493 10:02:30.737674 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9494 10:02:30.741088 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9495 10:02:30.747687 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9496 10:02:30.751310 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9497 10:02:30.754728 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9498 10:02:30.761104 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9499 10:02:30.764449 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9500 10:02:30.767991 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9501 10:02:30.774809 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9502 10:02:30.777869 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9503 10:02:30.781767 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9504 10:02:30.784866 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9505 10:02:30.791341 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9506 10:02:30.794562 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9507 10:02:30.797976 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9508 10:02:30.801290 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9509 10:02:30.804536 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9510 10:02:30.811282 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9511 10:02:30.814917 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9512 10:02:30.818028 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9513 10:02:30.824551 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9514 10:02:30.828360 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9515 10:02:30.831423 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9516 10:02:30.834622 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9517 10:02:30.841485 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9518 10:02:30.845017 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9519 10:02:30.851563 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9520 10:02:30.854633 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9521 10:02:30.861216 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9522 10:02:30.864842 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9523 10:02:30.870862 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9524 10:02:30.874478 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9525 10:02:30.877585 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9526 10:02:30.884458 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9527 10:02:30.887840 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9528 10:02:30.894696 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9529 10:02:30.897967 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9530 10:02:30.904429 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9531 10:02:30.907680 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9532 10:02:30.910881 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9533 10:02:30.918044 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9534 10:02:30.921099 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9535 10:02:30.928016 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9536 10:02:30.931278 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9537 10:02:30.937959 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9538 10:02:30.941288 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9539 10:02:30.944438 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9540 10:02:30.951199 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9541 10:02:30.954927 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9542 10:02:30.961255 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9543 10:02:30.964564 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9544 10:02:30.971413 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9545 10:02:30.974487 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9546 10:02:30.978109 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9547 10:02:30.984527 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9548 10:02:30.987816 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9549 10:02:30.994554 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9550 10:02:30.998080 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9551 10:02:31.004700 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9552 10:02:31.008079 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9553 10:02:31.011356 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9554 10:02:31.018003 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9555 10:02:31.021259 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9556 10:02:31.028181 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9557 10:02:31.031761 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9558 10:02:31.038342 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9559 10:02:31.041640 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9560 10:02:31.044929 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9561 10:02:31.051754 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9562 10:02:31.054678 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9563 10:02:31.061504 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9564 10:02:31.064800 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9565 10:02:31.067996 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9566 10:02:31.071613 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9567 10:02:31.078281 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9568 10:02:31.081808 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9569 10:02:31.085208 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9570 10:02:31.091597 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9571 10:02:31.095009 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9572 10:02:31.101661 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9573 10:02:31.105286 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9574 10:02:31.108229 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9575 10:02:31.115208 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9576 10:02:31.118397 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9577 10:02:31.121762 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9578 10:02:31.128889 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9579 10:02:31.132129 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9580 10:02:31.138830 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9581 10:02:31.141916 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9582 10:02:31.145247 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9583 10:02:31.152357 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9584 10:02:31.155658 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9585 10:02:31.158783 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9586 10:02:31.165484 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9587 10:02:31.168634 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9588 10:02:31.171835 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9589 10:02:31.175461 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9590 10:02:31.182383 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9591 10:02:31.185653 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9592 10:02:31.188449 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9593 10:02:31.195496 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9594 10:02:31.198720 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9595 10:02:31.202238 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9596 10:02:31.208999 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9597 10:02:31.212032 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9598 10:02:31.215233 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9599 10:02:31.222087 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9600 10:02:31.225678 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9601 10:02:31.232296 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9602 10:02:31.235519 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9603 10:02:31.238778 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9604 10:02:31.245432 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9605 10:02:31.249084 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9606 10:02:31.255656 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9607 10:02:31.258692 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9608 10:02:31.261913 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9609 10:02:31.269045 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9610 10:02:31.272421 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9611 10:02:31.279151 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9612 10:02:31.282360 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9613 10:02:31.285662 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9614 10:02:31.292271 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9615 10:02:31.295964 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9616 10:02:31.298795 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9617 10:02:31.306214 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9618 10:02:31.308864 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9619 10:02:31.315532 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9620 10:02:31.319099 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9621 10:02:31.322380 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9622 10:02:31.328866 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9623 10:02:31.332613 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9624 10:02:31.338792 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9625 10:02:31.342195 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9626 10:02:31.345491 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9627 10:02:31.352272 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9628 10:02:31.355930 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9629 10:02:31.359228 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9630 10:02:31.365675 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9631 10:02:31.368907 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9632 10:02:31.375505 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9633 10:02:31.379232 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9634 10:02:31.382185 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9635 10:02:31.388977 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9636 10:02:31.392219 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9637 10:02:31.398687 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9638 10:02:31.402652 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9639 10:02:31.405924 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9640 10:02:31.412393 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9641 10:02:31.415360 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9642 10:02:31.418644 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9643 10:02:31.425767 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9644 10:02:31.428640 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9645 10:02:31.435168 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9646 10:02:31.439158 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9647 10:02:31.442334 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9648 10:02:31.449058 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9649 10:02:31.452117 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9650 10:02:31.458876 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9651 10:02:31.462533 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9652 10:02:31.465473 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9653 10:02:31.471935 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9654 10:02:31.475331 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9655 10:02:31.478553 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9656 10:02:31.485818 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9657 10:02:31.488678 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9658 10:02:31.495184 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9659 10:02:31.498598 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9660 10:02:31.505496 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9661 10:02:31.508759 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9662 10:02:31.512015 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9663 10:02:31.518670 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9664 10:02:31.521665 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9665 10:02:31.528737 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9666 10:02:31.531885 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9667 10:02:31.538317 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9668 10:02:31.541983 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9669 10:02:31.544904 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9670 10:02:31.552090 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9671 10:02:31.555027 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9672 10:02:31.561648 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9673 10:02:31.564748 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9674 10:02:31.568552 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9675 10:02:31.574705 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9676 10:02:31.578633 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9677 10:02:31.585197 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9678 10:02:31.588233 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9679 10:02:31.595130 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9680 10:02:31.598312 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9681 10:02:31.601589 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9682 10:02:31.608040 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9683 10:02:31.611599 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9684 10:02:31.618079 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9685 10:02:31.621398 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9686 10:02:31.624970 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9687 10:02:31.631402 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9688 10:02:31.634666 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9689 10:02:31.641730 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9690 10:02:31.645156 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9691 10:02:31.647994 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9692 10:02:31.654893 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9693 10:02:31.657990 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9694 10:02:31.664964 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9695 10:02:31.667924 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9696 10:02:31.671464 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9697 10:02:31.678039 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9698 10:02:31.681699 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9699 10:02:31.684962 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9700 10:02:31.688145 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9701 10:02:31.694681 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9702 10:02:31.698338 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9703 10:02:31.701638 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9704 10:02:31.708104 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9705 10:02:31.710928 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9706 10:02:31.714604 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9707 10:02:31.720931 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9708 10:02:31.724707 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9709 10:02:31.730841 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9710 10:02:31.734660 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9711 10:02:31.737858 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9712 10:02:31.744316 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9713 10:02:31.747463 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9714 10:02:31.751150 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9715 10:02:31.757727 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9716 10:02:31.760692 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9717 10:02:31.764288 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9718 10:02:31.770953 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9719 10:02:31.774153 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9720 10:02:31.780936 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9721 10:02:31.784027 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9722 10:02:31.787364 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9723 10:02:31.793789 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9724 10:02:31.797146 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9725 10:02:31.803915 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9726 10:02:31.807126 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9727 10:02:31.810475 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9728 10:02:31.817365 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9729 10:02:31.820621 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9730 10:02:31.823705 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9731 10:02:31.830308 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9732 10:02:31.833957 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9733 10:02:31.837070 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9734 10:02:31.843768 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9735 10:02:31.847065 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9736 10:02:31.853509 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9737 10:02:31.856905 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9738 10:02:31.860183 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9739 10:02:31.863662 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9740 10:02:31.866689 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9741 10:02:31.873521 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9742 10:02:31.876666 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9743 10:02:31.880278 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9744 10:02:31.883234 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9745 10:02:31.890238 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9746 10:02:31.893489 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9747 10:02:31.896712 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9748 10:02:31.903269 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9749 10:02:31.906350 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9750 10:02:31.909979 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9751 10:02:31.916501 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9752 10:02:31.919515 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9753 10:02:31.922837 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9754 10:02:31.929865 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9755 10:02:31.932753 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9756 10:02:31.939831 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9757 10:02:31.942918 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9758 10:02:31.946139 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9759 10:02:31.952691 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9760 10:02:31.956407 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9761 10:02:31.962814 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9762 10:02:31.965858 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9763 10:02:31.972566 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9764 10:02:31.975775 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9765 10:02:31.979596 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9766 10:02:31.986089 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9767 10:02:31.989294 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9768 10:02:31.995922 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9769 10:02:31.999185 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9770 10:02:32.002356 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9771 10:02:32.009017 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9772 10:02:32.012677 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9773 10:02:32.019391 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9774 10:02:32.022382 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9775 10:02:32.026092 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9776 10:02:32.032454 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9777 10:02:32.035702 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9778 10:02:32.042278 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9779 10:02:32.045656 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9780 10:02:32.052154 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9781 10:02:32.055398 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9782 10:02:32.058758 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9783 10:02:32.065860 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9784 10:02:32.068869 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9785 10:02:32.075863 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9786 10:02:32.079099 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9787 10:02:32.082300 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9788 10:02:32.088649 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9789 10:02:32.092319 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9790 10:02:32.098677 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9791 10:02:32.102162 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9792 10:02:32.105899 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9793 10:02:32.112083 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9794 10:02:32.115781 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9795 10:02:32.122473 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9796 10:02:32.125820 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9797 10:02:32.128785 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9798 10:02:32.135481 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9799 10:02:32.138758 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9800 10:02:32.145849 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9801 10:02:32.148907 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9802 10:02:32.152301 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9803 10:02:32.158757 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9804 10:02:32.162498 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9805 10:02:32.168912 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9806 10:02:32.172483 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9807 10:02:32.175550 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9808 10:02:32.182381 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9809 10:02:32.185529 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9810 10:02:32.191956 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9811 10:02:32.195390 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9812 10:02:32.201924 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9813 10:02:32.205909 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9814 10:02:32.209040 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9815 10:02:32.215476 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9816 10:02:32.218522 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9817 10:02:32.225484 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9818 10:02:32.228410 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9819 10:02:32.232288 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9820 10:02:32.238495 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9821 10:02:32.241581 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9822 10:02:32.248379 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9823 10:02:32.251662 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9824 10:02:32.255574 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9825 10:02:32.261785 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9826 10:02:32.265149 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9827 10:02:32.271757 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9828 10:02:32.275504 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9829 10:02:32.281939 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9830 10:02:32.285218 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9831 10:02:32.288750 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9832 10:02:32.295258 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9833 10:02:32.298399 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9834 10:02:32.304782 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9835 10:02:32.308611 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9836 10:02:32.314860 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9837 10:02:32.318594 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9838 10:02:32.321759 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9839 10:02:32.328246 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9840 10:02:32.331664 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9841 10:02:32.338294 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9842 10:02:32.341464 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9843 10:02:32.348235 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9844 10:02:32.351635 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9845 10:02:32.354861 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9846 10:02:32.361600 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9847 10:02:32.364849 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9848 10:02:32.371714 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9849 10:02:32.374739 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9850 10:02:32.381398 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9851 10:02:32.384645 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9852 10:02:32.391320 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9853 10:02:32.394523 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9854 10:02:32.397743 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9855 10:02:32.405021 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9856 10:02:32.408267 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9857 10:02:32.414652 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9858 10:02:32.417782 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9859 10:02:32.424670 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9860 10:02:32.427789 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9861 10:02:32.430892 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9862 10:02:32.437850 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9863 10:02:32.440907 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9864 10:02:32.447531 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9865 10:02:32.451249 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9866 10:02:32.458066 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9867 10:02:32.461190 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9868 10:02:32.467770 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9869 10:02:32.471066 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9870 10:02:32.474236 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9871 10:02:32.480792 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9872 10:02:32.484551 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9873 10:02:32.490937 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9874 10:02:32.493891 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9875 10:02:32.501208 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9876 10:02:32.503954 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9877 10:02:32.511047 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9878 10:02:32.514330 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9879 10:02:32.520761 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9880 10:02:32.523912 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9881 10:02:32.527554 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9882 10:02:32.534035 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9883 10:02:32.537064 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9884 10:02:32.544095 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9885 10:02:32.547335 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9886 10:02:32.553919 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9887 10:02:32.557581 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9888 10:02:32.563545 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9889 10:02:32.567217 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9890 10:02:32.573743 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9891 10:02:32.576877 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9892 10:02:32.583940 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9893 10:02:32.587207 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9894 10:02:32.593703 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9895 10:02:32.596838 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9896 10:02:32.603528 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9897 10:02:32.607132 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9898 10:02:32.613534 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9899 10:02:32.617233 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9900 10:02:32.623571 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9901 10:02:32.626900 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9902 10:02:32.633724 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9903 10:02:32.633837 INFO: [APUAPC] vio 0
9904 10:02:32.640420 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9905 10:02:32.643623 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9906 10:02:32.646920 INFO: [APUAPC] D0_APC_0: 0x400510
9907 10:02:32.650169 INFO: [APUAPC] D0_APC_1: 0x0
9908 10:02:32.653326 INFO: [APUAPC] D0_APC_2: 0x1540
9909 10:02:32.657173 INFO: [APUAPC] D0_APC_3: 0x0
9910 10:02:32.660474 INFO: [APUAPC] D1_APC_0: 0xffffffff
9911 10:02:32.663389 INFO: [APUAPC] D1_APC_1: 0xffffffff
9912 10:02:32.667148 INFO: [APUAPC] D1_APC_2: 0x3fffff
9913 10:02:32.670161 INFO: [APUAPC] D1_APC_3: 0x0
9914 10:02:32.673620 INFO: [APUAPC] D2_APC_0: 0xffffffff
9915 10:02:32.676544 INFO: [APUAPC] D2_APC_1: 0xffffffff
9916 10:02:32.680040 INFO: [APUAPC] D2_APC_2: 0x3fffff
9917 10:02:32.683394 INFO: [APUAPC] D2_APC_3: 0x0
9918 10:02:32.687159 INFO: [APUAPC] D3_APC_0: 0xffffffff
9919 10:02:32.689893 INFO: [APUAPC] D3_APC_1: 0xffffffff
9920 10:02:32.693613 INFO: [APUAPC] D3_APC_2: 0x3fffff
9921 10:02:32.696663 INFO: [APUAPC] D3_APC_3: 0x0
9922 10:02:32.700617 INFO: [APUAPC] D4_APC_0: 0xffffffff
9923 10:02:32.703731 INFO: [APUAPC] D4_APC_1: 0xffffffff
9924 10:02:32.706966 INFO: [APUAPC] D4_APC_2: 0x3fffff
9925 10:02:32.707075 INFO: [APUAPC] D4_APC_3: 0x0
9926 10:02:32.710361 INFO: [APUAPC] D5_APC_0: 0xffffffff
9927 10:02:32.713429 INFO: [APUAPC] D5_APC_1: 0xffffffff
9928 10:02:32.717030 INFO: [APUAPC] D5_APC_2: 0x3fffff
9929 10:02:32.720421 INFO: [APUAPC] D5_APC_3: 0x0
9930 10:02:32.723560 INFO: [APUAPC] D6_APC_0: 0xffffffff
9931 10:02:32.727044 INFO: [APUAPC] D6_APC_1: 0xffffffff
9932 10:02:32.730204 INFO: [APUAPC] D6_APC_2: 0x3fffff
9933 10:02:32.733373 INFO: [APUAPC] D6_APC_3: 0x0
9934 10:02:32.736692 INFO: [APUAPC] D7_APC_0: 0xffffffff
9935 10:02:32.740501 INFO: [APUAPC] D7_APC_1: 0xffffffff
9936 10:02:32.743334 INFO: [APUAPC] D7_APC_2: 0x3fffff
9937 10:02:32.747159 INFO: [APUAPC] D7_APC_3: 0x0
9938 10:02:32.749795 INFO: [APUAPC] D8_APC_0: 0xffffffff
9939 10:02:32.753218 INFO: [APUAPC] D8_APC_1: 0xffffffff
9940 10:02:32.756785 INFO: [APUAPC] D8_APC_2: 0x3fffff
9941 10:02:32.760095 INFO: [APUAPC] D8_APC_3: 0x0
9942 10:02:32.763241 INFO: [APUAPC] D9_APC_0: 0xffffffff
9943 10:02:32.767008 INFO: [APUAPC] D9_APC_1: 0xffffffff
9944 10:02:32.770113 INFO: [APUAPC] D9_APC_2: 0x3fffff
9945 10:02:32.773419 INFO: [APUAPC] D9_APC_3: 0x0
9946 10:02:32.776630 INFO: [APUAPC] D10_APC_0: 0xffffffff
9947 10:02:32.780272 INFO: [APUAPC] D10_APC_1: 0xffffffff
9948 10:02:32.783208 INFO: [APUAPC] D10_APC_2: 0x3fffff
9949 10:02:32.786677 INFO: [APUAPC] D10_APC_3: 0x0
9950 10:02:32.790141 INFO: [APUAPC] D11_APC_0: 0xffffffff
9951 10:02:32.793458 INFO: [APUAPC] D11_APC_1: 0xffffffff
9952 10:02:32.796534 INFO: [APUAPC] D11_APC_2: 0x3fffff
9953 10:02:32.799930 INFO: [APUAPC] D11_APC_3: 0x0
9954 10:02:32.803263 INFO: [APUAPC] D12_APC_0: 0xffffffff
9955 10:02:32.806592 INFO: [APUAPC] D12_APC_1: 0xffffffff
9956 10:02:32.809713 INFO: [APUAPC] D12_APC_2: 0x3fffff
9957 10:02:32.813469 INFO: [APUAPC] D12_APC_3: 0x0
9958 10:02:32.816840 INFO: [APUAPC] D13_APC_0: 0xffffffff
9959 10:02:32.819938 INFO: [APUAPC] D13_APC_1: 0xffffffff
9960 10:02:32.823434 INFO: [APUAPC] D13_APC_2: 0x3fffff
9961 10:02:32.826456 INFO: [APUAPC] D13_APC_3: 0x0
9962 10:02:32.829721 INFO: [APUAPC] D14_APC_0: 0xffffffff
9963 10:02:32.833410 INFO: [APUAPC] D14_APC_1: 0xffffffff
9964 10:02:32.836204 INFO: [APUAPC] D14_APC_2: 0x3fffff
9965 10:02:32.840274 INFO: [APUAPC] D14_APC_3: 0x0
9966 10:02:32.843110 INFO: [APUAPC] D15_APC_0: 0xffffffff
9967 10:02:32.846168 INFO: [APUAPC] D15_APC_1: 0xffffffff
9968 10:02:32.849873 INFO: [APUAPC] D15_APC_2: 0x3fffff
9969 10:02:32.852814 INFO: [APUAPC] D15_APC_3: 0x0
9970 10:02:32.856071 INFO: [APUAPC] APC_CON: 0x4
9971 10:02:32.859677 INFO: [NOCDAPC] D0_APC_0: 0x0
9972 10:02:32.862700 INFO: [NOCDAPC] D0_APC_1: 0x0
9973 10:02:32.866352 INFO: [NOCDAPC] D1_APC_0: 0x0
9974 10:02:32.869411 INFO: [NOCDAPC] D1_APC_1: 0xfff
9975 10:02:32.869521 INFO: [NOCDAPC] D2_APC_0: 0x0
9976 10:02:32.873215 INFO: [NOCDAPC] D2_APC_1: 0xfff
9977 10:02:32.876397 INFO: [NOCDAPC] D3_APC_0: 0x0
9978 10:02:32.879653 INFO: [NOCDAPC] D3_APC_1: 0xfff
9979 10:02:32.882901 INFO: [NOCDAPC] D4_APC_0: 0x0
9980 10:02:32.886865 INFO: [NOCDAPC] D4_APC_1: 0xfff
9981 10:02:32.890012 INFO: [NOCDAPC] D5_APC_0: 0x0
9982 10:02:32.893083 INFO: [NOCDAPC] D5_APC_1: 0xfff
9983 10:02:32.896588 INFO: [NOCDAPC] D6_APC_0: 0x0
9984 10:02:32.899607 INFO: [NOCDAPC] D6_APC_1: 0xfff
9985 10:02:32.899712 INFO: [NOCDAPC] D7_APC_0: 0x0
9986 10:02:32.902922 INFO: [NOCDAPC] D7_APC_1: 0xfff
9987 10:02:32.906480 INFO: [NOCDAPC] D8_APC_0: 0x0
9988 10:02:32.909672 INFO: [NOCDAPC] D8_APC_1: 0xfff
9989 10:02:32.912922 INFO: [NOCDAPC] D9_APC_0: 0x0
9990 10:02:32.916590 INFO: [NOCDAPC] D9_APC_1: 0xfff
9991 10:02:32.919918 INFO: [NOCDAPC] D10_APC_0: 0x0
9992 10:02:32.923195 INFO: [NOCDAPC] D10_APC_1: 0xfff
9993 10:02:32.926247 INFO: [NOCDAPC] D11_APC_0: 0x0
9994 10:02:32.929435 INFO: [NOCDAPC] D11_APC_1: 0xfff
9995 10:02:32.933137 INFO: [NOCDAPC] D12_APC_0: 0x0
9996 10:02:32.936422 INFO: [NOCDAPC] D12_APC_1: 0xfff
9997 10:02:32.936509 INFO: [NOCDAPC] D13_APC_0: 0x0
9998 10:02:32.939772 INFO: [NOCDAPC] D13_APC_1: 0xfff
9999 10:02:32.942885 INFO: [NOCDAPC] D14_APC_0: 0x0
10000 10:02:32.946440 INFO: [NOCDAPC] D14_APC_1: 0xfff
10001 10:02:32.949447 INFO: [NOCDAPC] D15_APC_0: 0x0
10002 10:02:32.953299 INFO: [NOCDAPC] D15_APC_1: 0xfff
10003 10:02:32.956314 INFO: [NOCDAPC] APC_CON: 0x4
10004 10:02:32.959422 INFO: [APUAPC] set_apusys_apc done
10005 10:02:32.962976 INFO: [DEVAPC] devapc_init done
10006 10:02:32.966064 INFO: GICv3 without legacy support detected.
10007 10:02:32.969654 INFO: ARM GICv3 driver initialized in EL3
10008 10:02:32.976059 INFO: Maximum SPI INTID supported: 639
10009 10:02:32.979832 INFO: BL31: Initializing runtime services
10010 10:02:32.986278 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10011 10:02:32.986390 INFO: SPM: enable CPC mode
10012 10:02:32.992701 INFO: mcdi ready for mcusys-off-idle and system suspend
10013 10:02:32.995878 INFO: BL31: Preparing for EL3 exit to normal world
10014 10:02:32.999590 INFO: Entry point address = 0x80000000
10015 10:02:33.002751 INFO: SPSR = 0x8
10016 10:02:33.008476
10017 10:02:33.008587
10018 10:02:33.008684
10019 10:02:33.011908 Starting depthcharge on Spherion...
10020 10:02:33.012011
10021 10:02:33.012103 Wipe memory regions:
10022 10:02:33.012190
10023 10:02:33.013133 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10024 10:02:33.013280 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10025 10:02:33.013402 Setting prompt string to ['asurada:']
10026 10:02:33.013515 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10027 10:02:33.014798 [0x00000040000000, 0x00000054600000)
10028 10:02:33.137743
10029 10:02:33.137885 [0x00000054660000, 0x00000080000000)
10030 10:02:33.398078
10031 10:02:33.398216 [0x000000821a7280, 0x000000ffe64000)
10032 10:02:34.142821
10033 10:02:34.142996 [0x00000100000000, 0x00000240000000)
10034 10:02:36.033298
10035 10:02:36.036516 Initializing XHCI USB controller at 0x11200000.
10036 10:02:37.074147
10037 10:02:37.077861 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10038 10:02:37.077997
10039 10:02:37.078080
10040 10:02:37.078142
10041 10:02:37.078434 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10043 10:02:37.178788 asurada: tftpboot 192.168.201.1 12073297/tftp-deploy-118urgzn/kernel/image.itb 12073297/tftp-deploy-118urgzn/kernel/cmdline
10044 10:02:37.178978 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10045 10:02:37.179074 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10046 10:02:37.183239 tftpboot 192.168.201.1 12073297/tftp-deploy-118urgzn/kernel/image.ittp-deploy-118urgzn/kernel/cmdline
10047 10:02:37.183354
10048 10:02:37.183424 Waiting for link
10049 10:02:37.343563
10050 10:02:37.343715 R8152: Initializing
10051 10:02:37.343784
10052 10:02:37.347400 Version 9 (ocp_data = 6010)
10053 10:02:37.347511
10054 10:02:37.350461 R8152: Done initializing
10055 10:02:37.350565
10056 10:02:37.350641 Adding net device
10057 10:02:39.222980
10058 10:02:39.223120 done.
10059 10:02:39.223192
10060 10:02:39.223280 MAC: 00:e0:4c:78:7a:aa
10061 10:02:39.223346
10062 10:02:39.226165 Sending DHCP discover... done.
10063 10:02:39.226282
10064 10:02:39.229165 Waiting for reply... done.
10065 10:02:39.229306
10066 10:02:39.232423 Sending DHCP request... done.
10067 10:02:39.232579
10068 10:02:39.249515 Waiting for reply... done.
10069 10:02:39.249737
10070 10:02:39.249852 My ip is 192.168.201.12
10071 10:02:39.249952
10072 10:02:39.252612 The DHCP server ip is 192.168.201.1
10073 10:02:39.252745
10074 10:02:39.259342 TFTP server IP predefined by user: 192.168.201.1
10075 10:02:39.259514
10076 10:02:39.265903 Bootfile predefined by user: 12073297/tftp-deploy-118urgzn/kernel/image.itb
10077 10:02:39.266061
10078 10:02:39.266167 Sending tftp read request... done.
10079 10:02:39.269531
10080 10:02:39.273018 Waiting for the transfer...
10081 10:02:39.273169
10082 10:02:39.614192 00000000 ################################################################
10083 10:02:39.614375
10084 10:02:39.964102 00080000 ################################################################
10085 10:02:39.964286
10086 10:02:40.310995 00100000 ################################################################
10087 10:02:40.311183
10088 10:02:40.672485 00180000 ################################################################
10089 10:02:40.672670
10090 10:02:41.046948 00200000 ################################################################
10091 10:02:41.047116
10092 10:02:41.417393 00280000 ################################################################
10093 10:02:41.417611
10094 10:02:41.792928 00300000 ################################################################
10095 10:02:41.793072
10096 10:02:42.161449 00380000 ################################################################
10097 10:02:42.161660
10098 10:02:42.522427 00400000 ################################################################
10099 10:02:42.522599
10100 10:02:42.877891 00480000 ################################################################
10101 10:02:42.878067
10102 10:02:43.230268 00500000 ################################################################
10103 10:02:43.230425
10104 10:02:43.588993 00580000 ################################################################
10105 10:02:43.589159
10106 10:02:43.946221 00600000 ################################################################
10107 10:02:43.946414
10108 10:02:44.308579 00680000 ################################################################
10109 10:02:44.308746
10110 10:02:44.663414 00700000 ################################################################
10111 10:02:44.663594
10112 10:02:45.017723 00780000 ################################################################
10113 10:02:45.017914
10114 10:02:45.361826 00800000 ################################################################
10115 10:02:45.362001
10116 10:02:45.710093 00880000 ################################################################
10117 10:02:45.710271
10118 10:02:46.065151 00900000 ################################################################
10119 10:02:46.065290
10120 10:02:46.409567 00980000 ################################################################
10121 10:02:46.409716
10122 10:02:46.765163 00a00000 ################################################################
10123 10:02:46.765356
10124 10:02:47.119684 00a80000 ################################################################
10125 10:02:47.119827
10126 10:02:47.479329 00b00000 ################################################################
10127 10:02:47.479476
10128 10:02:47.825453 00b80000 ################################################################
10129 10:02:47.826245
10130 10:02:48.187055 00c00000 ################################################################
10131 10:02:48.187247
10132 10:02:48.541992 00c80000 ################################################################
10133 10:02:48.542130
10134 10:02:48.892015 00d00000 ################################################################
10135 10:02:48.892156
10136 10:02:49.250044 00d80000 ################################################################
10137 10:02:49.250189
10138 10:02:49.600576 00e00000 ################################################################
10139 10:02:49.600751
10140 10:02:49.953535 00e80000 ################################################################
10141 10:02:49.953699
10142 10:02:50.308139 00f00000 ################################################################
10143 10:02:50.308305
10144 10:02:50.645331 00f80000 ################################################################
10145 10:02:50.645498
10146 10:02:50.897077 01000000 ################################################################
10147 10:02:50.897232
10148 10:02:51.146879 01080000 ################################################################
10149 10:02:51.147034
10150 10:02:51.413269 01100000 ################################################################
10151 10:02:51.413423
10152 10:02:51.668830 01180000 ################################################################
10153 10:02:51.668999
10154 10:02:51.911616 01200000 ################################################################
10155 10:02:51.911780
10156 10:02:52.158859 01280000 ################################################################
10157 10:02:52.158998
10158 10:02:52.414433 01300000 ################################################################
10159 10:02:52.414609
10160 10:02:52.661995 01380000 ################################################################
10161 10:02:52.662177
10162 10:02:52.905228 01400000 ################################################################
10163 10:02:52.905376
10164 10:02:53.149336 01480000 ################################################################
10165 10:02:53.149513
10166 10:02:53.392287 01500000 ################################################################
10167 10:02:53.392428
10168 10:02:53.651436 01580000 ################################################################
10169 10:02:53.651586
10170 10:02:53.909550 01600000 ################################################################
10171 10:02:53.909742
10172 10:02:54.156519 01680000 ################################################################
10173 10:02:54.156652
10174 10:02:54.417925 01700000 ################################################################
10175 10:02:54.418092
10176 10:02:54.681460 01780000 ################################################################
10177 10:02:54.681646
10178 10:02:54.939233 01800000 ################################################################
10179 10:02:54.939454
10180 10:02:55.190944 01880000 ################################################################
10181 10:02:55.191106
10182 10:02:55.636828 01900000 ################################################################
10183 10:02:55.637017
10184 10:02:55.687164 01980000 ################################################################
10185 10:02:55.687347
10186 10:02:55.948947 01a00000 ################################################################
10187 10:02:55.949111
10188 10:02:56.214208 01a80000 ################################################################
10189 10:02:56.214387
10190 10:02:56.475233 01b00000 ################################################################
10191 10:02:56.475427
10192 10:02:56.738503 01b80000 ################################################################
10193 10:02:56.738637
10194 10:02:56.998514 01c00000 ################################################################
10195 10:02:56.998691
10196 10:02:57.260862 01c80000 ################################################################
10197 10:02:57.261004
10198 10:02:57.545668 01d00000 ################################################################
10199 10:02:57.545832
10200 10:02:57.803483 01d80000 ################################################################
10201 10:02:57.803623
10202 10:02:58.052221 01e00000 ################################################################
10203 10:02:58.052374
10204 10:02:58.329190 01e80000 ################################################################
10205 10:02:58.329325
10206 10:02:58.615916 01f00000 ################################################################
10207 10:02:58.616047
10208 10:02:58.886154 01f80000 ################################################################
10209 10:02:58.886294
10210 10:02:59.141771 02000000 ################################################################
10211 10:02:59.141907
10212 10:02:59.404990 02080000 ################################################################
10213 10:02:59.405131
10214 10:02:59.656154 02100000 ################################################################
10215 10:02:59.656288
10216 10:02:59.918618 02180000 ################################################################
10217 10:02:59.918749
10218 10:03:00.194820 02200000 ################################################################
10219 10:03:00.195015
10220 10:03:00.450510 02280000 ################################################################
10221 10:03:00.450714
10222 10:03:00.711200 02300000 ################################################################
10223 10:03:00.711347
10224 10:03:00.986981 02380000 ################################################################
10225 10:03:00.987109
10226 10:03:01.250786 02400000 ################################################################
10227 10:03:01.250925
10228 10:03:01.503657 02480000 ################################################################
10229 10:03:01.503800
10230 10:03:01.769366 02500000 ################################################################
10231 10:03:01.769509
10232 10:03:02.039218 02580000 ################################################################
10233 10:03:02.039401
10234 10:03:02.310713 02600000 ################################################################
10235 10:03:02.310857
10236 10:03:02.570892 02680000 ################################################################
10237 10:03:02.571021
10238 10:03:02.823030 02700000 ################################################################
10239 10:03:02.823160
10240 10:03:03.072022 02780000 ################################################################
10241 10:03:03.072155
10242 10:03:03.326430 02800000 ################################################################
10243 10:03:03.326561
10244 10:03:03.600768 02880000 ################################################################
10245 10:03:03.600937
10246 10:03:03.852395 02900000 ################################################################
10247 10:03:03.852543
10248 10:03:04.110005 02980000 ################################################################
10249 10:03:04.110139
10250 10:03:04.369977 02a00000 ################################################################
10251 10:03:04.370141
10252 10:03:04.623901 02a80000 ################################################################
10253 10:03:04.624058
10254 10:03:04.874599 02b00000 ################################################################
10255 10:03:04.874735
10256 10:03:05.123778 02b80000 ################################################################
10257 10:03:05.123954
10258 10:03:05.373573 02c00000 ################################################################
10259 10:03:05.373759
10260 10:03:05.623138 02c80000 ################################################################
10261 10:03:05.623286
10262 10:03:05.882748 02d00000 ################################################################
10263 10:03:05.882897
10264 10:03:06.145426 02d80000 ################################################################
10265 10:03:06.145607
10266 10:03:06.402296 02e00000 ################################################################
10267 10:03:06.402434
10268 10:03:06.665655 02e80000 ################################################################
10269 10:03:06.665815
10270 10:03:06.930972 02f00000 ################################################################
10271 10:03:06.931129
10272 10:03:07.194037 02f80000 ################################################################
10273 10:03:07.194188
10274 10:03:07.261454 03000000 ################ done.
10275 10:03:07.261603
10276 10:03:07.264480 The bootfile was 50454534 bytes long.
10277 10:03:07.264579
10278 10:03:07.268096 Sending tftp read request... done.
10279 10:03:07.268185
10280 10:03:07.268254 Waiting for the transfer...
10281 10:03:07.268323
10282 10:03:07.271180 00000000 # done.
10283 10:03:07.271275
10284 10:03:07.277490 Command line loaded dynamically from TFTP file: 12073297/tftp-deploy-118urgzn/kernel/cmdline
10285 10:03:07.277625
10286 10:03:07.290749 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10287 10:03:07.290875
10288 10:03:07.294514 Loading FIT.
10289 10:03:07.294603
10290 10:03:07.297754 Image ramdisk-1 has 39357677 bytes.
10291 10:03:07.297866
10292 10:03:07.300906 Image fdt-1 has 47278 bytes.
10293 10:03:07.300996
10294 10:03:07.301062 Image kernel-1 has 11047542 bytes.
10295 10:03:07.304424
10296 10:03:07.310922 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10297 10:03:07.311010
10298 10:03:07.327409 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10299 10:03:07.327512
10300 10:03:07.334537 Choosing best match conf-1 for compat google,spherion-rev2.
10301 10:03:07.338381
10302 10:03:07.342894 Connected to device vid:did:rid of 1ae0:0028:00
10303 10:03:07.351258
10304 10:03:07.354403 tpm_get_response: command 0x17b, return code 0x0
10305 10:03:07.354482
10306 10:03:07.357560 ec_init: CrosEC protocol v3 supported (256, 248)
10307 10:03:07.362067
10308 10:03:07.364992 tpm_cleanup: add release locality here.
10309 10:03:07.365100
10310 10:03:07.365200 Shutting down all USB controllers.
10311 10:03:07.368143
10312 10:03:07.368252 Removing current net device
10313 10:03:07.368349
10314 10:03:07.374903 Exiting depthcharge with code 4 at timestamp: 63664039
10315 10:03:07.375044
10316 10:03:07.378588 LZMA decompressing kernel-1 to 0x821a6718
10317 10:03:07.378721
10318 10:03:07.381659 LZMA decompressing kernel-1 to 0x40000000
10319 10:03:08.770623
10320 10:03:08.770767 jumping to kernel
10321 10:03:08.771291 end: 2.2.4 bootloader-commands (duration 00:00:36) [common]
10322 10:03:08.771395 start: 2.2.5 auto-login-action (timeout 00:03:49) [common]
10323 10:03:08.771473 Setting prompt string to ['Linux version [0-9]']
10324 10:03:08.771549 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10325 10:03:08.771628 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10326 10:03:08.852297
10327 10:03:08.856076 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10328 10:03:08.859543 start: 2.2.5.1 login-action (timeout 00:03:49) [common]
10329 10:03:08.859661 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10330 10:03:08.859753 Setting prompt string to []
10331 10:03:08.859834 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10332 10:03:08.859912 Using line separator: #'\n'#
10333 10:03:08.859973 No login prompt set.
10334 10:03:08.860050 Parsing kernel messages
10335 10:03:08.860105 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10336 10:03:08.860206 [login-action] Waiting for messages, (timeout 00:03:49)
10337 10:03:08.878994 [ 0.000000] Linux version 6.1.62-cip9 (KernelCI@build-j22848-arm64-gcc-10-defconfig-arm64-chromebook-6q8mw) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Nov 24 09:44:51 UTC 2023
10338 10:03:08.882179 [ 0.000000] random: crng init done
10339 10:03:08.889217 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10340 10:03:08.892465 [ 0.000000] efi: UEFI not found.
10341 10:03:08.898899 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10342 10:03:08.905431 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10343 10:03:08.915591 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10344 10:03:08.925267 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10345 10:03:08.932266 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10346 10:03:08.938518 [ 0.000000] printk: bootconsole [mtk8250] enabled
10347 10:03:08.944951 [ 0.000000] NUMA: No NUMA configuration found
10348 10:03:08.951713 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10349 10:03:08.955301 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10350 10:03:08.958566 [ 0.000000] Zone ranges:
10351 10:03:08.965394 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10352 10:03:08.968339 [ 0.000000] DMA32 empty
10353 10:03:08.975169 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10354 10:03:08.978574 [ 0.000000] Movable zone start for each node
10355 10:03:08.982020 [ 0.000000] Early memory node ranges
10356 10:03:08.988401 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10357 10:03:08.994939 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10358 10:03:09.001977 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10359 10:03:09.008425 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10360 10:03:09.011641 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10361 10:03:09.021082 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10362 10:03:09.077373 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10363 10:03:09.083956 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10364 10:03:09.090397 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10365 10:03:09.093715 [ 0.000000] psci: probing for conduit method from DT.
10366 10:03:09.100762 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10367 10:03:09.103985 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10368 10:03:09.110524 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10369 10:03:09.113559 [ 0.000000] psci: SMC Calling Convention v1.2
10370 10:03:09.119935 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10371 10:03:09.123239 [ 0.000000] Detected VIPT I-cache on CPU0
10372 10:03:09.130220 [ 0.000000] CPU features: detected: GIC system register CPU interface
10373 10:03:09.136912 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10374 10:03:09.143504 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10375 10:03:09.149824 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10376 10:03:09.156402 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10377 10:03:09.166731 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10378 10:03:09.169956 [ 0.000000] alternatives: applying boot alternatives
10379 10:03:09.176663 [ 0.000000] Fallback order for Node 0: 0
10380 10:03:09.183260 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10381 10:03:09.186698 [ 0.000000] Policy zone: Normal
10382 10:03:09.199787 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10383 10:03:09.209453 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10384 10:03:09.221475 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10385 10:03:09.232027 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10386 10:03:09.238539 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10387 10:03:09.241688 <6>[ 0.000000] software IO TLB: area num 8.
10388 10:03:09.298647 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10389 10:03:09.447621 <6>[ 0.000000] Memory: 7931184K/8385536K available (17984K kernel code, 4116K rwdata, 17312K rodata, 8384K init, 615K bss, 421584K reserved, 32768K cma-reserved)
10390 10:03:09.454309 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10391 10:03:09.461105 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10392 10:03:09.464408 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10393 10:03:09.471363 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10394 10:03:09.477749 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10395 10:03:09.480982 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10396 10:03:09.491261 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10397 10:03:09.497808 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10398 10:03:09.500980 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10399 10:03:09.508837 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10400 10:03:09.511783 <6>[ 0.000000] GICv3: 608 SPIs implemented
10401 10:03:09.519055 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10402 10:03:09.522310 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10403 10:03:09.525493 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10404 10:03:09.535327 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10405 10:03:09.545341 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10406 10:03:09.558558 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10407 10:03:09.565071 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10408 10:03:09.574583 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10409 10:03:09.587493 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10410 10:03:09.594434 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10411 10:03:09.600884 <6>[ 0.009232] Console: colour dummy device 80x25
10412 10:03:09.610493 <6>[ 0.013957] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10413 10:03:09.617414 <6>[ 0.024399] pid_max: default: 32768 minimum: 301
10414 10:03:09.620520 <6>[ 0.029302] LSM: Security Framework initializing
10415 10:03:09.627543 <6>[ 0.034239] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10416 10:03:09.637492 <6>[ 0.042100] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10417 10:03:09.643801 <6>[ 0.051561] cblist_init_generic: Setting adjustable number of callback queues.
10418 10:03:09.650184 <6>[ 0.059004] cblist_init_generic: Setting shift to 3 and lim to 1.
10419 10:03:09.660077 <6>[ 0.065343] cblist_init_generic: Setting adjustable number of callback queues.
10420 10:03:09.667167 <6>[ 0.072794] cblist_init_generic: Setting shift to 3 and lim to 1.
10421 10:03:09.670281 <6>[ 0.079193] rcu: Hierarchical SRCU implementation.
10422 10:03:09.677107 <6>[ 0.084239] rcu: Max phase no-delay instances is 1000.
10423 10:03:09.683838 <6>[ 0.091295] EFI services will not be available.
10424 10:03:09.686905 <6>[ 0.096247] smp: Bringing up secondary CPUs ...
10425 10:03:09.695196 <6>[ 0.101292] Detected VIPT I-cache on CPU1
10426 10:03:09.701459 <6>[ 0.101362] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10427 10:03:09.708610 <6>[ 0.101394] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10428 10:03:09.711825 <6>[ 0.101726] Detected VIPT I-cache on CPU2
10429 10:03:09.718271 <6>[ 0.101778] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10430 10:03:09.728636 <6>[ 0.101795] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10431 10:03:09.731617 <6>[ 0.102051] Detected VIPT I-cache on CPU3
10432 10:03:09.738503 <6>[ 0.102096] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10433 10:03:09.744720 <6>[ 0.102110] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10434 10:03:09.747929 <6>[ 0.102416] CPU features: detected: Spectre-v4
10435 10:03:09.754501 <6>[ 0.102424] CPU features: detected: Spectre-BHB
10436 10:03:09.757764 <6>[ 0.102428] Detected PIPT I-cache on CPU4
10437 10:03:09.764331 <6>[ 0.102485] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10438 10:03:09.771306 <6>[ 0.102502] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10439 10:03:09.777471 <6>[ 0.102797] Detected PIPT I-cache on CPU5
10440 10:03:09.784233 <6>[ 0.102861] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10441 10:03:09.791126 <6>[ 0.102878] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10442 10:03:09.794230 <6>[ 0.103159] Detected PIPT I-cache on CPU6
10443 10:03:09.800879 <6>[ 0.103224] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10444 10:03:09.807349 <6>[ 0.103240] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10445 10:03:09.814463 <6>[ 0.103538] Detected PIPT I-cache on CPU7
10446 10:03:09.820888 <6>[ 0.103605] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10447 10:03:09.827398 <6>[ 0.103621] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10448 10:03:09.831263 <6>[ 0.103669] smp: Brought up 1 node, 8 CPUs
10449 10:03:09.837695 <6>[ 0.244977] SMP: Total of 8 processors activated.
10450 10:03:09.840803 <6>[ 0.249928] CPU features: detected: 32-bit EL0 Support
10451 10:03:09.850692 <6>[ 0.255324] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10452 10:03:09.857654 <6>[ 0.264124] CPU features: detected: Common not Private translations
10453 10:03:09.863723 <6>[ 0.270600] CPU features: detected: CRC32 instructions
10454 10:03:09.867238 <6>[ 0.275951] CPU features: detected: RCpc load-acquire (LDAPR)
10455 10:03:09.873898 <6>[ 0.281911] CPU features: detected: LSE atomic instructions
10456 10:03:09.880301 <6>[ 0.287692] CPU features: detected: Privileged Access Never
10457 10:03:09.883577 <6>[ 0.293472] CPU features: detected: RAS Extension Support
10458 10:03:09.893567 <6>[ 0.299080] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10459 10:03:09.896869 <6>[ 0.306299] CPU: All CPU(s) started at EL2
10460 10:03:09.903700 <6>[ 0.310642] alternatives: applying system-wide alternatives
10461 10:03:09.912384 <6>[ 0.321344] devtmpfs: initialized
10462 10:03:09.924978 <6>[ 0.330191] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10463 10:03:09.934700 <6>[ 0.340151] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10464 10:03:09.941526 <6>[ 0.348361] pinctrl core: initialized pinctrl subsystem
10465 10:03:09.944456 <6>[ 0.355023] DMI not present or invalid.
10466 10:03:09.951704 <6>[ 0.359437] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10467 10:03:09.961059 <6>[ 0.366261] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10468 10:03:09.967718 <6>[ 0.373843] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10469 10:03:09.977773 <6>[ 0.382071] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10470 10:03:09.980995 <6>[ 0.390313] audit: initializing netlink subsys (disabled)
10471 10:03:09.991210 <5>[ 0.396002] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10472 10:03:09.997455 <6>[ 0.396700] thermal_sys: Registered thermal governor 'step_wise'
10473 10:03:10.004295 <6>[ 0.403967] thermal_sys: Registered thermal governor 'power_allocator'
10474 10:03:10.008071 <6>[ 0.410223] cpuidle: using governor menu
10475 10:03:10.014534 <6>[ 0.421182] NET: Registered PF_QIPCRTR protocol family
10476 10:03:10.020766 <6>[ 0.426665] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10477 10:03:10.024429 <6>[ 0.433772] ASID allocator initialised with 32768 entries
10478 10:03:10.031595 <6>[ 0.440333] Serial: AMBA PL011 UART driver
10479 10:03:10.040502 <4>[ 0.449119] Trying to register duplicate clock ID: 134
10480 10:03:10.094740 <6>[ 0.506651] KASLR enabled
10481 10:03:10.108852 <6>[ 0.514325] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10482 10:03:10.115862 <6>[ 0.521338] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10483 10:03:10.122096 <6>[ 0.527830] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10484 10:03:10.128681 <6>[ 0.534833] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10485 10:03:10.135282 <6>[ 0.541318] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10486 10:03:10.142141 <6>[ 0.548323] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10487 10:03:10.148561 <6>[ 0.554812] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10488 10:03:10.155093 <6>[ 0.561819] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10489 10:03:10.158937 <6>[ 0.569310] ACPI: Interpreter disabled.
10490 10:03:10.167206 <6>[ 0.575705] iommu: Default domain type: Translated
10491 10:03:10.173436 <6>[ 0.580818] iommu: DMA domain TLB invalidation policy: strict mode
10492 10:03:10.177328 <5>[ 0.587472] SCSI subsystem initialized
10493 10:03:10.183699 <6>[ 0.591635] usbcore: registered new interface driver usbfs
10494 10:03:10.190108 <6>[ 0.597365] usbcore: registered new interface driver hub
10495 10:03:10.193297 <6>[ 0.602915] usbcore: registered new device driver usb
10496 10:03:10.200372 <6>[ 0.609012] pps_core: LinuxPPS API ver. 1 registered
10497 10:03:10.210089 <6>[ 0.614207] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10498 10:03:10.213944 <6>[ 0.623555] PTP clock support registered
10499 10:03:10.217043 <6>[ 0.627796] EDAC MC: Ver: 3.0.0
10500 10:03:10.224612 <6>[ 0.632946] FPGA manager framework
10501 10:03:10.227821 <6>[ 0.636623] Advanced Linux Sound Architecture Driver Initialized.
10502 10:03:10.231376 <6>[ 0.643384] vgaarb: loaded
10503 10:03:10.238295 <6>[ 0.646549] clocksource: Switched to clocksource arch_sys_counter
10504 10:03:10.244988 <5>[ 0.652977] VFS: Disk quotas dquot_6.6.0
10505 10:03:10.251533 <6>[ 0.657161] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10506 10:03:10.254562 <6>[ 0.664347] pnp: PnP ACPI: disabled
10507 10:03:10.262772 <6>[ 0.671046] NET: Registered PF_INET protocol family
10508 10:03:10.272248 <6>[ 0.676638] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10509 10:03:10.283900 <6>[ 0.688941] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10510 10:03:10.293238 <6>[ 0.697757] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10511 10:03:10.300364 <6>[ 0.705729] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10512 10:03:10.306698 <6>[ 0.714430] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10513 10:03:10.318747 <6>[ 0.724170] TCP: Hash tables configured (established 65536 bind 65536)
10514 10:03:10.325201 <6>[ 0.731033] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10515 10:03:10.332237 <6>[ 0.738235] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10516 10:03:10.338700 <6>[ 0.745934] NET: Registered PF_UNIX/PF_LOCAL protocol family
10517 10:03:10.345257 <6>[ 0.752003] RPC: Registered named UNIX socket transport module.
10518 10:03:10.348874 <6>[ 0.758151] RPC: Registered udp transport module.
10519 10:03:10.355388 <6>[ 0.763082] RPC: Registered tcp transport module.
10520 10:03:10.362085 <6>[ 0.768015] RPC: Registered tcp NFSv4.1 backchannel transport module.
10521 10:03:10.365484 <6>[ 0.774679] PCI: CLS 0 bytes, default 64
10522 10:03:10.368625 <6>[ 0.779152] Unpacking initramfs...
10523 10:03:10.378703 <6>[ 0.782884] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10524 10:03:10.385060 <6>[ 0.791556] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10525 10:03:10.391529 <6>[ 0.800443] kvm [1]: IPA Size Limit: 40 bits
10526 10:03:10.395016 <6>[ 0.804972] kvm [1]: GICv3: no GICV resource entry
10527 10:03:10.401944 <6>[ 0.809994] kvm [1]: disabling GICv2 emulation
10528 10:03:10.408467 <6>[ 0.814678] kvm [1]: GIC system register CPU interface enabled
10529 10:03:10.411655 <6>[ 0.820850] kvm [1]: vgic interrupt IRQ18
10530 10:03:10.418635 <6>[ 0.826602] kvm [1]: VHE mode initialized successfully
10531 10:03:10.424839 <5>[ 0.832925] Initialise system trusted keyrings
10532 10:03:10.431213 <6>[ 0.837725] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10533 10:03:10.439001 <6>[ 0.847648] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10534 10:03:10.445483 <5>[ 0.854043] NFS: Registering the id_resolver key type
10535 10:03:10.448769 <5>[ 0.859352] Key type id_resolver registered
10536 10:03:10.455532 <5>[ 0.863764] Key type id_legacy registered
10537 10:03:10.462157 <6>[ 0.868040] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10538 10:03:10.468555 <6>[ 0.874962] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10539 10:03:10.475143 <6>[ 0.882664] 9p: Installing v9fs 9p2000 file system support
10540 10:03:10.511193 <5>[ 0.920074] Key type asymmetric registered
10541 10:03:10.514610 <5>[ 0.924403] Asymmetric key parser 'x509' registered
10542 10:03:10.524622 <6>[ 0.929540] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10543 10:03:10.527812 <6>[ 0.937153] io scheduler mq-deadline registered
10544 10:03:10.531469 <6>[ 0.941913] io scheduler kyber registered
10545 10:03:10.550416 <6>[ 0.959055] EINJ: ACPI disabled.
10546 10:03:10.583071 <4>[ 0.984783] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10547 10:03:10.592790 <4>[ 0.995401] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10548 10:03:10.607164 <6>[ 1.015937] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10549 10:03:10.615256 <6>[ 1.023841] printk: console [ttyS0] disabled
10550 10:03:10.643150 <6>[ 1.048484] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10551 10:03:10.649477 <6>[ 1.057956] printk: console [ttyS0] enabled
10552 10:03:10.653288 <6>[ 1.057956] printk: console [ttyS0] enabled
10553 10:03:10.659730 <6>[ 1.066853] printk: bootconsole [mtk8250] disabled
10554 10:03:10.662977 <6>[ 1.066853] printk: bootconsole [mtk8250] disabled
10555 10:03:10.669519 <6>[ 1.077843] SuperH (H)SCI(F) driver initialized
10556 10:03:10.672745 <6>[ 1.083123] msm_serial: driver initialized
10557 10:03:10.686635 <6>[ 1.092063] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10558 10:03:10.696686 <6>[ 1.100607] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10559 10:03:10.703635 <6>[ 1.109148] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10560 10:03:10.713342 <6>[ 1.117778] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10561 10:03:10.719634 <6>[ 1.126485] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10562 10:03:10.729705 <6>[ 1.135199] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10563 10:03:10.740246 <6>[ 1.143740] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10564 10:03:10.746795 <6>[ 1.152533] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10565 10:03:10.756576 <6>[ 1.161076] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10566 10:03:10.767586 <6>[ 1.176481] loop: module loaded
10567 10:03:10.774665 <6>[ 1.182440] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10568 10:03:10.796614 <4>[ 1.205479] mtk-pmic-keys: Failed to locate of_node [id: -1]
10569 10:03:10.803281 <6>[ 1.212223] megasas: 07.719.03.00-rc1
10570 10:03:10.813250 <6>[ 1.221756] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10571 10:03:10.821319 <6>[ 1.229921] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10572 10:03:10.838018 <6>[ 1.246551] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10573 10:03:10.893563 <6>[ 1.295816] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10574 10:03:11.968229 <6>[ 2.377156] Freeing initrd memory: 38432K
10575 10:03:11.978700 <6>[ 2.387639] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10576 10:03:11.989552 <6>[ 2.398437] tun: Universal TUN/TAP device driver, 1.6
10577 10:03:11.993312 <6>[ 2.404508] thunder_xcv, ver 1.0
10578 10:03:11.996462 <6>[ 2.408013] thunder_bgx, ver 1.0
10579 10:03:11.999623 <6>[ 2.411509] nicpf, ver 1.0
10580 10:03:12.010170 <6>[ 2.415513] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10581 10:03:12.013429 <6>[ 2.422989] hns3: Copyright (c) 2017 Huawei Corporation.
10582 10:03:12.019884 <6>[ 2.428579] hclge is initializing
10583 10:03:12.022850 <6>[ 2.432158] e1000: Intel(R) PRO/1000 Network Driver
10584 10:03:12.029582 <6>[ 2.437287] e1000: Copyright (c) 1999-2006 Intel Corporation.
10585 10:03:12.032858 <6>[ 2.443300] e1000e: Intel(R) PRO/1000 Network Driver
10586 10:03:12.039648 <6>[ 2.448516] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10587 10:03:12.046478 <6>[ 2.454700] igb: Intel(R) Gigabit Ethernet Network Driver
10588 10:03:12.052862 <6>[ 2.460350] igb: Copyright (c) 2007-2014 Intel Corporation.
10589 10:03:12.059479 <6>[ 2.466185] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10590 10:03:12.066362 <6>[ 2.472704] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10591 10:03:12.069353 <6>[ 2.479170] sky2: driver version 1.30
10592 10:03:12.075925 <6>[ 2.484165] VFIO - User Level meta-driver version: 0.3
10593 10:03:12.083909 <6>[ 2.492428] usbcore: registered new interface driver usb-storage
10594 10:03:12.090422 <6>[ 2.498875] usbcore: registered new device driver onboard-usb-hub
10595 10:03:12.099464 <6>[ 2.508024] mt6397-rtc mt6359-rtc: registered as rtc0
10596 10:03:12.109420 <6>[ 2.513492] mt6397-rtc mt6359-rtc: setting system clock to 2023-11-24T10:01:01 UTC (1700820061)
10597 10:03:12.112928 <6>[ 2.523056] i2c_dev: i2c /dev entries driver
10598 10:03:12.129168 <6>[ 2.534710] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10599 10:03:12.149071 <6>[ 2.557697] cpu cpu0: EM: created perf domain
10600 10:03:12.151854 <6>[ 2.562648] cpu cpu4: EM: created perf domain
10601 10:03:12.159207 <6>[ 2.568238] sdhci: Secure Digital Host Controller Interface driver
10602 10:03:12.165955 <6>[ 2.574671] sdhci: Copyright(c) Pierre Ossman
10603 10:03:12.172894 <6>[ 2.579630] Synopsys Designware Multimedia Card Interface Driver
10604 10:03:12.179679 <6>[ 2.586264] sdhci-pltfm: SDHCI platform and OF driver helper
10605 10:03:12.183004 <6>[ 2.586387] mmc0: CQHCI version 5.10
10606 10:03:12.189312 <6>[ 2.596356] ledtrig-cpu: registered to indicate activity on CPUs
10607 10:03:12.196093 <6>[ 2.603485] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10608 10:03:12.202589 <6>[ 2.610559] usbcore: registered new interface driver usbhid
10609 10:03:12.206308 <6>[ 2.616381] usbhid: USB HID core driver
10610 10:03:12.212587 <6>[ 2.620572] spi_master spi0: will run message pump with realtime priority
10611 10:03:12.255908 <6>[ 2.658240] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10612 10:03:12.274692 <6>[ 2.673512] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10613 10:03:12.281969 <6>[ 2.688389] cros-ec-spi spi0.0: Chrome EC device registered
10614 10:03:12.285283 <6>[ 2.694421] mmc0: Command Queue Engine enabled
10615 10:03:12.291867 <6>[ 2.699195] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10616 10:03:12.298383 <6>[ 2.706634] mmcblk0: mmc0:0001 DA4128 116 GiB
10617 10:03:12.308513 <6>[ 2.707421] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10618 10:03:12.311622 <6>[ 2.716589] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10619 10:03:12.318065 <6>[ 2.721737] NET: Registered PF_PACKET protocol family
10620 10:03:12.325065 <6>[ 2.727462] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10621 10:03:12.328244 <6>[ 2.731973] 9pnet: Installing 9P2000 support
10622 10:03:12.331603 <6>[ 2.737761] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10623 10:03:12.338538 <5>[ 2.741684] Key type dns_resolver registered
10624 10:03:12.344862 <6>[ 2.747461] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10625 10:03:12.348005 <6>[ 2.751892] registered taskstats version 1
10626 10:03:12.354397 <5>[ 2.762290] Loading compiled-in X.509 certificates
10627 10:03:12.382980 <4>[ 2.784815] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10628 10:03:12.392806 <4>[ 2.795543] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10629 10:03:12.399127 <3>[ 2.806071] debugfs: File 'uA_load' in directory '/' already present!
10630 10:03:12.405819 <3>[ 2.812770] debugfs: File 'min_uV' in directory '/' already present!
10631 10:03:12.412527 <3>[ 2.819433] debugfs: File 'max_uV' in directory '/' already present!
10632 10:03:12.419206 <3>[ 2.826047] debugfs: File 'constraint_flags' in directory '/' already present!
10633 10:03:12.430239 <3>[ 2.835772] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10634 10:03:12.439792 <6>[ 2.848614] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10635 10:03:12.446690 <6>[ 2.855613] xhci-mtk 11200000.usb: xHCI Host Controller
10636 10:03:12.453483 <6>[ 2.861118] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10637 10:03:12.463760 <6>[ 2.868961] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10638 10:03:12.470227 <6>[ 2.878373] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10639 10:03:12.476669 <6>[ 2.884453] xhci-mtk 11200000.usb: xHCI Host Controller
10640 10:03:12.483215 <6>[ 2.889931] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10641 10:03:12.489912 <6>[ 2.897576] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10642 10:03:12.496902 <6>[ 2.905223] hub 1-0:1.0: USB hub found
10643 10:03:12.499706 <6>[ 2.909230] hub 1-0:1.0: 1 port detected
10644 10:03:12.506330 <6>[ 2.913469] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10645 10:03:12.513105 <6>[ 2.922033] hub 2-0:1.0: USB hub found
10646 10:03:12.516130 <6>[ 2.926036] hub 2-0:1.0: 1 port detected
10647 10:03:12.524074 <6>[ 2.933103] mtk-msdc 11f70000.mmc: Got CD GPIO
10648 10:03:12.534945 <6>[ 2.940261] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10649 10:03:12.541120 <6>[ 2.948286] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10650 10:03:12.551551 <4>[ 2.956223] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10651 10:03:12.561368 <6>[ 2.965747] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10652 10:03:12.567907 <6>[ 2.973823] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10653 10:03:12.574440 <6>[ 2.981926] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10654 10:03:12.584813 <6>[ 2.989852] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10655 10:03:12.591333 <6>[ 2.997668] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10656 10:03:12.601404 <6>[ 3.005486] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10657 10:03:12.610716 <6>[ 3.016095] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10658 10:03:12.617643 <6>[ 3.024457] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10659 10:03:12.627339 <6>[ 3.032797] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10660 10:03:12.633935 <6>[ 3.041137] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10661 10:03:12.643690 <6>[ 3.049476] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10662 10:03:12.650646 <6>[ 3.057815] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10663 10:03:12.660647 <6>[ 3.066152] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10664 10:03:12.670654 <6>[ 3.074491] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10665 10:03:12.676856 <6>[ 3.082830] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10666 10:03:12.687128 <6>[ 3.091174] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10667 10:03:12.693744 <6>[ 3.099516] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10668 10:03:12.703990 <6>[ 3.107866] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10669 10:03:12.710300 <6>[ 3.116206] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10670 10:03:12.720397 <6>[ 3.124545] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10671 10:03:12.726548 <6>[ 3.132883] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10672 10:03:12.733480 <6>[ 3.141610] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10673 10:03:12.739934 <6>[ 3.148512] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10674 10:03:12.746974 <6>[ 3.155276] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10675 10:03:12.753234 <6>[ 3.162029] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10676 10:03:12.760177 <6>[ 3.168956] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10677 10:03:12.770421 <6>[ 3.175802] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10678 10:03:12.780046 <6>[ 3.184931] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10679 10:03:12.790388 <6>[ 3.194051] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10680 10:03:12.799888 <6>[ 3.203353] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10681 10:03:12.806744 <6>[ 3.212825] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10682 10:03:12.816907 <6>[ 3.222293] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10683 10:03:12.826772 <6>[ 3.231414] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10684 10:03:12.836214 <6>[ 3.240881] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10685 10:03:12.846530 <6>[ 3.250013] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10686 10:03:12.856486 <6>[ 3.259308] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10687 10:03:12.866051 <6>[ 3.269469] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10688 10:03:12.876372 <6>[ 3.281481] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10689 10:03:12.902083 <6>[ 3.311085] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10690 10:03:12.933766 <6>[ 3.342461] hub 2-1:1.0: USB hub found
10691 10:03:12.936782 <6>[ 3.346943] hub 2-1:1.0: 3 ports detected
10692 10:03:12.945162 <6>[ 3.354204] hub 2-1:1.0: USB hub found
10693 10:03:12.948330 <6>[ 3.358531] hub 2-1:1.0: 3 ports detected
10694 10:03:13.056981 <6>[ 3.462820] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10695 10:03:13.212140 <6>[ 3.620937] hub 1-1:1.0: USB hub found
10696 10:03:13.215367 <6>[ 3.625406] hub 1-1:1.0: 4 ports detected
10697 10:03:13.224486 <6>[ 3.633128] hub 1-1:1.0: USB hub found
10698 10:03:13.227729 <6>[ 3.637445] hub 1-1:1.0: 4 ports detected
10699 10:03:13.297425 <6>[ 3.702950] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10700 10:03:13.549201 <6>[ 3.954907] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10701 10:03:13.681855 <6>[ 4.090740] hub 1-1.4:1.0: USB hub found
10702 10:03:13.684836 <6>[ 4.095409] hub 1-1.4:1.0: 2 ports detected
10703 10:03:13.694461 <6>[ 4.103662] hub 1-1.4:1.0: USB hub found
10704 10:03:13.697781 <6>[ 4.108254] hub 1-1.4:1.0: 2 ports detected
10705 10:03:13.997182 <6>[ 4.402831] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10706 10:03:14.189205 <6>[ 4.594833] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10707 10:03:25.154260 <6>[ 15.567817] ALSA device list:
10708 10:03:25.160647 <6>[ 15.571115] No soundcards found.
10709 10:03:25.169012 <6>[ 15.579111] Freeing unused kernel memory: 8384K
10710 10:03:25.172198 <6>[ 15.584087] Run /init as init process
10711 10:03:25.222031 <6>[ 15.632510] NET: Registered PF_INET6 protocol family
10712 10:03:25.229144 <6>[ 15.639192] Segment Routing with IPv6
10713 10:03:25.232043 <6>[ 15.643150] In-situ OAM (IOAM) with IPv6
10714 10:03:25.266474 <30>[ 15.656722] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10715 10:03:25.269594 <30>[ 15.680518] systemd[1]: Detected architecture arm64.
10716 10:03:25.269710
10717 10:03:25.280409 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10718 10:03:25.280550
10719 10:03:25.288789 <30>[ 15.698876] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10720 10:03:25.449204 <30>[ 15.856376] systemd[1]: Queued start job for default target Graphical Interface.
10721 10:03:25.486561 <30>[ 15.891688] systemd[1]: Created slice system-getty.slice.
10722 10:03:25.488412 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10723 10:03:25.504562 <30>[ 15.915114] systemd[1]: Created slice system-modprobe.slice.
10724 10:03:25.511539 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10725 10:03:25.529693 <30>[ 15.939912] systemd[1]: Created slice system-serial\x2dgetty.slice.
10726 10:03:25.539921 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10727 10:03:25.553806 <30>[ 15.963949] systemd[1]: Created slice User and Session Slice.
10728 10:03:25.560222 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10729 10:03:25.580806 <30>[ 15.987400] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10730 10:03:25.590201 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10731 10:03:25.608170 <30>[ 16.015361] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10732 10:03:25.614612 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10733 10:03:25.639321 <30>[ 16.043241] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10734 10:03:25.646167 <30>[ 16.055559] systemd[1]: Reached target Local Encrypted Volumes.
10735 10:03:25.652625 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10736 10:03:25.668820 <30>[ 16.079332] systemd[1]: Reached target Paths.
10737 10:03:25.672585 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10738 10:03:25.688766 <30>[ 16.099023] systemd[1]: Reached target Remote File Systems.
10739 10:03:25.695570 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10740 10:03:25.713059 <30>[ 16.123197] systemd[1]: Reached target Slices.
10741 10:03:25.719472 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10742 10:03:25.732461 <30>[ 16.142876] systemd[1]: Reached target Swap.
10743 10:03:25.735648 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10744 10:03:25.756024 <30>[ 16.163303] systemd[1]: Listening on initctl Compatibility Named Pipe.
10745 10:03:25.763135 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10746 10:03:25.769859 <30>[ 16.178493] systemd[1]: Listening on Journal Audit Socket.
10747 10:03:25.776072 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10748 10:03:25.788671 <30>[ 16.199292] systemd[1]: Listening on Journal Socket (/dev/log).
10749 10:03:25.795506 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10750 10:03:25.814004 <30>[ 16.224070] systemd[1]: Listening on Journal Socket.
10751 10:03:25.820225 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10752 10:03:25.836378 <30>[ 16.243525] systemd[1]: Listening on Network Service Netlink Socket.
10753 10:03:25.843163 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10754 10:03:25.857882 <30>[ 16.268062] systemd[1]: Listening on udev Control Socket.
10755 10:03:25.864355 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10756 10:03:25.881855 <30>[ 16.291917] systemd[1]: Listening on udev Kernel Socket.
10757 10:03:25.888161 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10758 10:03:25.940647 <30>[ 16.351079] systemd[1]: Mounting Huge Pages File System...
10759 10:03:25.947104 Mounting [0;1;39mHuge Pages File System[0m...
10760 10:03:25.962676 <30>[ 16.372751] systemd[1]: Mounting POSIX Message Queue File System...
10761 10:03:25.968987 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10762 10:03:25.986686 <30>[ 16.396744] systemd[1]: Mounting Kernel Debug File System...
10763 10:03:25.992814 Mounting [0;1;39mKernel Debug File System[0m...
10764 10:03:26.011816 <30>[ 16.419122] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10765 10:03:26.023751 <30>[ 16.430707] systemd[1]: Starting Create list of static device nodes for the current kernel...
10766 10:03:26.030259 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10767 10:03:26.052803 <30>[ 16.463141] systemd[1]: Starting Load Kernel Module configfs...
10768 10:03:26.059639 Starting [0;1;39mLoad Kernel Module configfs[0m...
10769 10:03:26.076526 <30>[ 16.486796] systemd[1]: Starting Load Kernel Module drm...
10770 10:03:26.082970 Starting [0;1;39mLoad Kernel Module drm[0m...
10771 10:03:26.104038 <30>[ 16.511162] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10772 10:03:26.137113 <30>[ 16.547221] systemd[1]: Starting Journal Service...
10773 10:03:26.140264 Starting [0;1;39mJournal Service[0m...
10774 10:03:26.159739 <30>[ 16.569903] systemd[1]: Starting Load Kernel Modules...
10775 10:03:26.165846 Starting [0;1;39mLoad Kernel Modules[0m...
10776 10:03:26.185972 <30>[ 16.592881] systemd[1]: Starting Remount Root and Kernel File Systems...
10777 10:03:26.192198 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10778 10:03:26.208886 <30>[ 16.619274] systemd[1]: Starting Coldplug All udev Devices...
10779 10:03:26.215473 Starting [0;1;39mColdplug All udev Devices[0m...
10780 10:03:26.232140 <30>[ 16.642462] systemd[1]: Started Journal Service.
10781 10:03:26.238928 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10782 10:03:26.254781 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10783 10:03:26.278225 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10784 10:03:26.293303 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10785 10:03:26.313476 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10786 10:03:26.334685 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10787 10:03:26.358251 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10788 10:03:26.377694 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10789 10:03:26.397163 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10790 10:03:26.412364 See 'systemctl status systemd-remount-fs.service' for details.
10791 10:03:26.468764 Mounting [0;1;39mKernel Configuration File System[0m...
10792 10:03:26.489830 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10793 10:03:26.502474 <46>[ 16.909797] systemd-journald[179]: Received client request to flush runtime journal.
10794 10:03:26.513724 Starting [0;1;39mLoad/Save Random Seed[0m...
10795 10:03:26.534008 Starting [0;1;39mApply Kernel Variables[0m...
10796 10:03:26.554474 Starting [0;1;39mCreate System Users[0m...
10797 10:03:26.574119 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10798 10:03:26.593296 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10799 10:03:26.617467 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10800 10:03:26.630142 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10801 10:03:26.645080 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10802 10:03:26.661028 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10803 10:03:26.721005 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10804 10:03:26.742993 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10805 10:03:26.760580 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10806 10:03:26.776358 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10807 10:03:26.825100 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10808 10:03:26.849806 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10809 10:03:26.875405 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10810 10:03:26.897476 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10811 10:03:26.949995 Starting [0;1;39mNetwork Service[0m...
10812 10:03:26.975404 Starting [0;1;39mNetwork Time Synchronization[0m...
10813 10:03:26.991826 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10814 10:03:27.030332 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10815 10:03:27.061267 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m<6>[ 17.467970] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10816 10:03:27.061381 .
10817 10:03:27.071014 <6>[ 17.476216] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10818 10:03:27.078018 <6>[ 17.485263] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10819 10:03:27.085759 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10820 10:03:27.108222 <4>[ 17.515164] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10821 10:03:27.111400 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10822 10:03:27.127049 <4>[ 17.534123] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10823 10:03:27.141479 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10824 10:03:27.144591 <6>[ 17.555505] mc: Linux media interface: v0.10
10825 10:03:27.154633 <3>[ 17.561454] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10826 10:03:27.161531 <3>[ 17.570225] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10827 10:03:27.172093 [[0;32m OK [<3>[ 17.580113] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10828 10:03:27.185263 0m] Reached target [0;1;39mSyst<3>[ 17.590047] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10829 10:03:27.194904 em Time Set[0m.<6>[ 17.591866] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10830 10:03:27.201525 <6>[ 17.595049] videodev: Linux video capture interface: v2.00
10831 10:03:27.201672
10832 10:03:27.208552 <3>[ 17.599689] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10833 10:03:27.218015 <3>[ 17.599700] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10834 10:03:27.225131 <3>[ 17.599711] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10835 10:03:27.234864 <3>[ 17.599716] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10836 10:03:27.241806 <3>[ 17.607140] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10837 10:03:27.252136 <6>[ 17.612525] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10838 10:03:27.258564 <3>[ 17.617541] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10839 10:03:27.265176 <6>[ 17.617775] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10840 10:03:27.271695 <6>[ 17.617784] pci_bus 0000:00: root bus resource [bus 00-ff]
10841 10:03:27.278766 <6>[ 17.617790] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10842 10:03:27.288634 <6>[ 17.617795] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10843 10:03:27.294902 <6>[ 17.617828] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10844 10:03:27.301752 <6>[ 17.617849] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10845 10:03:27.308051 <6>[ 17.617927] pci 0000:00:00.0: supports D1 D2
10846 10:03:27.314680 <6>[ 17.617930] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10847 10:03:27.321359 <6>[ 17.620327] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10848 10:03:27.327567 <6>[ 17.622583] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10849 10:03:27.334177 <6>[ 17.622615] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10850 10:03:27.344212 <6>[ 17.622634] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10851 10:03:27.351638 <6>[ 17.622649] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10852 10:03:27.355446 <6>[ 17.622756] pci 0000:01:00.0: supports D1 D2
10853 10:03:27.362478 <6>[ 17.622758] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10854 10:03:27.368807 <6>[ 17.626841] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10855 10:03:27.375755 <6>[ 17.627595] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10856 10:03:27.385760 <3>[ 17.633427] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10857 10:03:27.392256 <6>[ 17.633522] usbcore: registered new interface driver r8152
10858 10:03:27.398670 <6>[ 17.641689] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10859 10:03:27.405728 <3>[ 17.649687] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10860 10:03:27.415424 <4>[ 17.652603] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10861 10:03:27.421911 <4>[ 17.652603] Fallback method does not support PEC.
10862 10:03:27.428437 <6>[ 17.657757] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10863 10:03:27.438434 <3>[ 17.669284] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10864 10:03:27.445372 <6>[ 17.674923] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10865 10:03:27.451697 <3>[ 17.681939] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10866 10:03:27.462080 <6>[ 17.682017] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10867 10:03:27.472220 <6>[ 17.687629] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10868 10:03:27.478625 <3>[ 17.694585] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10869 10:03:27.488375 <6>[ 17.704743] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10870 10:03:27.495002 <3>[ 17.710738] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10871 10:03:27.498105 <6>[ 17.711627] Bluetooth: Core ver 2.22
10872 10:03:27.504895 <6>[ 17.711704] NET: Registered PF_BLUETOOTH protocol family
10873 10:03:27.511916 <6>[ 17.711707] Bluetooth: HCI device and connection manager initialized
10874 10:03:27.518182 <6>[ 17.711722] Bluetooth: HCI socket layer initialized
10875 10:03:27.521411 <6>[ 17.711728] Bluetooth: L2CAP socket layer initialized
10876 10:03:27.528599 <6>[ 17.711745] Bluetooth: SCO socket layer initialized
10877 10:03:27.532047 <6>[ 17.718423] pci 0000:00:00.0: PCI bridge to [bus 01]
10878 10:03:27.539807 <3>[ 17.722733] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10879 10:03:27.549853 <3>[ 17.722738] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10880 10:03:27.556498 <6>[ 17.729830] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10881 10:03:27.563056 <6>[ 17.730148] usbcore: registered new interface driver cdc_ether
10882 10:03:27.569816 <3>[ 17.737890] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10883 10:03:27.577132 <6>[ 17.739000] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10884 10:03:27.583870 <6>[ 17.741902] remoteproc remoteproc0: scp is available
10885 10:03:27.586866 <6>[ 17.741949] remoteproc remoteproc0: powering up scp
10886 10:03:27.596886 <6>[ 17.741953] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10887 10:03:27.603752 <6>[ 17.741961] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10888 10:03:27.610459 <6>[ 17.744355] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10889 10:03:27.613510 <6>[ 17.746567] usbcore: registered new interface driver r8153_ecm
10890 10:03:27.623377 <3>[ 17.774249] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10891 10:03:27.633223 <3>[ 17.775164] power_supply sbs-5-000b: driver failed to report `capacity_level' property: -6
10892 10:03:27.637102 <6>[ 17.822511] usbcore: registered new interface driver btusb
10893 10:03:27.650321 <4>[ 17.823053] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10894 10:03:27.653280 <3>[ 17.823063] Bluetooth: hci0: Failed to load firmware file (-2)
10895 10:03:27.660125 <3>[ 17.823067] Bluetooth: hci0: Failed to set up firmware (-2)
10896 10:03:27.670307 <4>[ 17.823070] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10897 10:03:27.676602 <6>[ 17.841198] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10898 10:03:27.683338 <6>[ 17.850213] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10899 10:03:27.693289 <6>[ 17.867673] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10900 10:03:27.699494 <6>[ 17.867683] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10901 10:03:27.706457 <6>[ 17.869810] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10902 10:03:27.713152 <6>[ 17.878521] remoteproc remoteproc0: remote processor scp is now up
10903 10:03:27.719693 <6>[ 17.879194] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10904 10:03:27.733104 <6>[ 17.900495] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10905 10:03:27.739615 <6>[ 17.903988] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10906 10:03:27.742659 <6>[ 17.911427] usbcore: registered new interface driver uvcvideo
10907 10:03:27.752678 <4>[ 17.914000] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10908 10:03:27.762487 <4>[ 17.914006] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10909 10:03:27.769515 <6>[ 17.916241] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10910 10:03:27.775807 <5>[ 17.927629] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10911 10:03:27.785977 <6>[ 17.934963] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10912 10:03:27.792261 <5>[ 17.952172] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10913 10:03:27.802529 <3>[ 17.955493] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10914 10:03:27.809368 <3>[ 17.956287] power_supply sbs-5-000b: driver failed to report `current_now' property: -6
10915 10:03:27.819108 <4>[ 17.964420] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10916 10:03:27.822309 <6>[ 17.975039] r8152 2-1.3:1.0 eth0: v1.12.13
10917 10:03:27.832235 <3>[ 17.976939] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10918 10:03:27.835802 <6>[ 17.978468] cfg80211: failed to load regulatory.db
10919 10:03:27.845642 <3>[ 17.997156] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10920 10:03:27.851948 <6>[ 17.998373] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
10921 10:03:27.858767 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10922 10:03:27.884971 <3>[ 18.292134] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10923 10:03:27.906722 <6>[ 18.313196] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10924 10:03:27.909980 <6>[ 18.320765] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10925 10:03:27.919579 <3>[ 18.325171] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10926 10:03:27.926368 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10927 10:03:27.936830 <6>[ 18.347500] mt7921e 0000:01:00.0: ASIC revision: 79610010
10928 10:03:27.952549 <3>[ 18.359945] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10929 10:03:27.959296 Starting [0;1;39mNetwork Name Resolution[0m...
10930 10:03:27.982593 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10931 10:03:28.019790 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10932 10:03:28.042447 <4>[ 18.446093] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10933 10:03:28.141526 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10934 10:03:28.162563 <4>[ 18.566380] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10935 10:03:28.169219 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10936 10:03:28.188096 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10937 10:03:28.200489 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10938 10:03:28.219728 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10939 10:03:28.235894 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10940 10:03:28.248624 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10941 10:03:28.269338 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10942 10:03:28.283406 <4>[ 18.687403] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10943 10:03:28.289866 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10944 10:03:28.304968 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10945 10:03:28.324600 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10946 10:03:28.377542 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10947 10:03:28.408903 <4>[ 18.812826] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10948 10:03:28.420369 Starting [0;1;39mUser Login Management[0m...
10949 10:03:28.441519 Starting [0;1;39mPermit User Sessions[0m...
10950 10:03:28.460599 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10951 10:03:28.535527 <4>[ 18.939655] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10952 10:03:28.542024 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10953 10:03:28.560225 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10954 10:03:28.580358 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10955 10:03:28.646019 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10956 10:03:28.661128 <4>[ 19.065185] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10957 10:03:28.668305 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10958 10:03:28.685544 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10959 10:03:28.693751 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10960 10:03:28.708928 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10961 10:03:28.775106 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10962 10:03:28.784559 <4>[ 19.190209] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10963 10:03:28.816071 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10964 10:03:28.865468
10965 10:03:28.865717
10966 10:03:28.868583 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10967 10:03:28.868746
10968 10:03:28.872190 debian-bullseye-arm64 login: root (automatic login)
10969 10:03:28.872365
10970 10:03:28.872515
10971 10:03:28.888539 Linux debian-bullseye-arm64 6.1.62-cip9 #1 SMP PREEMPT Fri Nov 24 09:44:51 UTC 2023 aarch64
10972 10:03:28.888733
10973 10:03:28.895056 The programs included with the Debian GNU/Linux system are free software;
10974 10:03:28.901373 the exact distribution terms for each program are described in the
10975 10:03:28.911503 in<4>[ 19.315172] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10976 10:03:28.914890 dividual files in /usr/share/doc/*/copyright.
10977 10:03:28.915010
10978 10:03:28.921229 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10979 10:03:28.924349 permitted by applicable law.
10980 10:03:28.924981 Matched prompt #10: / #
10982 10:03:28.925303 Setting prompt string to ['/ #']
10983 10:03:28.925438 end: 2.2.5.1 login-action (duration 00:00:20) [common]
10985 10:03:28.925841 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
10986 10:03:28.925975 start: 2.2.6 expect-shell-connection (timeout 00:03:29) [common]
10987 10:03:28.926075 Setting prompt string to ['/ #']
10988 10:03:28.926174 Forcing a shell prompt, looking for ['/ #']
10990 10:03:28.976451 / #
10991 10:03:28.976650 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10992 10:03:28.976771 Waiting using forced prompt support (timeout 00:02:30)
10993 10:03:28.981701
10994 10:03:28.982041 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10995 10:03:28.982155 start: 2.2.7 export-device-env (timeout 00:03:29) [common]
10996 10:03:28.982259 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10997 10:03:28.982355 end: 2.2 depthcharge-retry (duration 00:01:31) [common]
10998 10:03:28.982455 end: 2 depthcharge-action (duration 00:01:31) [common]
10999 10:03:28.982548 start: 3 lava-test-retry (timeout 00:08:08) [common]
11000 10:03:28.982636 start: 3.1 lava-test-shell (timeout 00:08:08) [common]
11001 10:03:28.982712 Using namespace: common
11003 10:03:29.083026 / # #
11004 10:03:29.083200 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11005 10:03:29.083325 <4>[ 19.434892] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11006 10:03:29.088210 #
11007 10:03:29.088522 Using /lava-12073297
11009 10:03:29.188918 / # export SHELL=/bin/sh
11010 10:03:29.189117 <4>[ 19.555121] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11011 10:03:29.191929 export SHELL=/bin/sh<6>[ 19.599044] IPv6: ADDRCONF(NETDEV_CHANGE): enx00e04c787aaa: link becomes ready
11012 10:03:29.233758 <6>[ 19.607156] r8152 2-1.3:1.0 enx00e04c787aaa: carrier on
11013 10:03:29.234012
11015 10:03:29.334528 / # . /lava-12073297/environment
11016 10:03:29.334768 <3>[ 19.673266] mt7921e 0000:01:00.0: hardware init failed
11017 10:03:29.339680 . /lava-12073297/environment
11019 10:03:29.440186 / # /lava-12073297/bin/lava-test-runner /lava-12073297/0
11020 10:03:29.440345 Test shell timeout: 10s (minimum of the action and connection timeout)
11021 10:03:29.444780 /lava-12073297/bin/lava-test-runner /lava-12073297/0
11022 10:03:29.467081 + export TESTRUN_ID=0_v4l2-compliance-uvc
11023 10:03:29.470464 + cd /lava-12073297/0/tests/0_v4l2-compliance-uvc
11024 10:03:29.470569 + cat uuid
11025 10:03:29.474147 + UUID=12073297_1.5.2.3.1
11026 10:03:29.474256 + set +x
11027 10:03:29.480308 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-uvc 12073297_1.5.2.3.1>
11028 10:03:29.480643 Received signal: <STARTRUN> 0_v4l2-compliance-uvc 12073297_1.5.2.3.1
11029 10:03:29.480756 Starting test lava.0_v4l2-compliance-uvc (12073297_1.5.2.3.1)
11030 10:03:29.480885 Skipping test definition patterns.
11031 10:03:29.484089 + /usr/bin/v4l2-parser.sh -d uvcvideo
11032 10:03:29.490543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
11033 10:03:29.490658 device: /dev/video0
11034 10:03:29.490903 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
11036 10:03:35.985145 v4l2-compliance 1.25.0-1, 64 bits, 64-bit time_t
11037 10:03:35.996286 v4l2-compliance SHA: 16e70e28584c 2023-06-22 09:47:27
11038 10:03:36.004328
11039 10:03:36.018697 Compliance test for uvcvideo device /dev/video0:
11040 10:03:36.025412
11041 10:03:36.036886 Driver Info:
11042 10:03:36.050067 Driver name : uvcvideo
11043 10:03:36.066291 Card type : HD User Facing: HD User Facing
11044 10:03:36.076903 Bus info : usb-11200000.usb-1.4.1
11045 10:03:36.087198 Driver version : 6.1.62
11046 10:03:36.098464 Capabilities : 0x84a00001
11047 10:03:36.112984 Metadata Capture
11048 10:03:36.124851 Streaming
11049 10:03:36.136531 Extended Pix Format
11050 10:03:36.149551 Device Capabilities
11051 10:03:36.162620 Device Caps : 0x04200001
11052 10:03:36.176937 Streaming
11053 10:03:36.188048 Extended Pix Format
11054 10:03:36.199018 Media Driver Info:
11055 10:03:36.209663 Driver name : uvcvideo
11056 10:03:36.224717 Model : HD User Facing: HD User Facing
11057 10:03:36.235244 Serial : 200901010001
11058 10:03:36.249239 Bus info : usb-11200000.usb-1.4.1
11059 10:03:36.257345 Media version : 6.1.62
11060 10:03:36.272130 Hardware revision: 0x00009758 (38744)
11061 10:03:36.280043 Driver version : 6.1.62
11062 10:03:36.292444 Interface Info:
11063 10:03:36.307314 <LAVA_SIGNAL_TESTSET START Interface-Info>
11064 10:03:36.307400 ID : 0x03000002
11065 10:03:36.307642 Received signal: <TESTSET> START Interface-Info
11066 10:03:36.307713 Starting test_set Interface-Info
11067 10:03:36.319175 Type : V4L Video
11068 10:03:36.329757 Entity Info:
11069 10:03:36.337370 <LAVA_SIGNAL_TESTSET STOP>
11070 10:03:36.337653 Received signal: <TESTSET> STOP
11071 10:03:36.337763 Closing test_set Interface-Info
11072 10:03:36.346993 <LAVA_SIGNAL_TESTSET START Entity-Info>
11073 10:03:36.347116 ID : 0x00000001 (1)
11074 10:03:36.347381 Received signal: <TESTSET> START Entity-Info
11075 10:03:36.347479 Starting test_set Entity-Info
11076 10:03:36.361206 Name : HD User Facing: HD User Facing
11077 10:03:36.368250 Function : V4L2 I/O
11078 10:03:36.381714 Flags : default
11079 10:03:36.394283 Pad 0x01000007 : 0: Sink
11080 10:03:36.417480 Link 0x02000013: from remote pad 0x100000a of entity 'Realtek Extended Controls Unit' (Video Pixel Formatter): Data, Enabled, Immutable
11081 10:03:36.417573
11082 10:03:36.429291 Required ioctls:
11083 10:03:36.440355 <LAVA_SIGNAL_TESTSET STOP>
11084 10:03:36.440614 Received signal: <TESTSET> STOP
11085 10:03:36.440685 Closing test_set Entity-Info
11086 10:03:36.450732 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11087 10:03:36.451025 Received signal: <TESTSET> START Required-ioctls
11088 10:03:36.451095 Starting test_set Required-ioctls
11089 10:03:36.453937 test MC information (see 'Media Driver Info' above): OK
11090 10:03:36.484355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass>
11091 10:03:36.484650 Received signal: <TESTCASE> TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass
11093 10:03:36.487459 test VIDIOC_QUERYCAP: OK
11094 10:03:36.508373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11095 10:03:36.508652 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11097 10:03:36.511369 test invalid ioctls: OK
11098 10:03:36.535997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11099 10:03:36.536092
11100 10:03:36.536332 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11102 10:03:36.546439 Allow for multiple opens:
11103 10:03:36.554005 <LAVA_SIGNAL_TESTSET STOP>
11104 10:03:36.554279 Received signal: <TESTSET> STOP
11105 10:03:36.554350 Closing test_set Required-ioctls
11106 10:03:36.563533 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11107 10:03:36.563794 Received signal: <TESTSET> START Allow-for-multiple-opens
11108 10:03:36.563865 Starting test_set Allow-for-multiple-opens
11109 10:03:36.566947 test second /dev/video0 open: OK
11110 10:03:36.589097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video0-open RESULT=pass>
11111 10:03:36.589365 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video0-open RESULT=pass
11113 10:03:36.592092 test VIDIOC_QUERYCAP: OK
11114 10:03:36.613107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11115 10:03:36.613365 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11117 10:03:36.616089 test VIDIOC_G/S_PRIORITY: OK
11118 10:03:36.637824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11119 10:03:36.638100 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11121 10:03:36.640796 test for unlimited opens: OK
11122 10:03:36.663876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11123 10:03:36.664035
11124 10:03:36.664320 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11126 10:03:36.674191 Debug ioctls:
11127 10:03:36.685498 <LAVA_SIGNAL_TESTSET STOP>
11128 10:03:36.685860 Received signal: <TESTSET> STOP
11129 10:03:36.685939 Closing test_set Allow-for-multiple-opens
11130 10:03:36.696057 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11131 10:03:36.696445 Received signal: <TESTSET> START Debug-ioctls
11132 10:03:36.696529 Starting test_set Debug-ioctls
11133 10:03:36.698685 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11134 10:03:36.719996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11135 10:03:36.720328 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11137 10:03:36.726603 test VIDIOC_LOG_STATUS: OK (Not Supported)
11138 10:03:36.750154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11139 10:03:36.750299
11140 10:03:36.750584 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11142 10:03:36.761397 Input ioctls:
11143 10:03:36.768897 <LAVA_SIGNAL_TESTSET STOP>
11144 10:03:36.769190 Received signal: <TESTSET> STOP
11145 10:03:36.769290 Closing test_set Debug-ioctls
11146 10:03:36.778893 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11147 10:03:36.779225 Received signal: <TESTSET> START Input-ioctls
11148 10:03:36.779336 Starting test_set Input-ioctls
11149 10:03:36.782017 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11150 10:03:36.808063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11151 10:03:36.808369 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11153 10:03:36.811079 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11154 10:03:36.833799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11155 10:03:36.834067 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11157 10:03:36.840701 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11158 10:03:36.860916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11159 10:03:36.861191 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11161 10:03:36.867925 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11162 10:03:36.889640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11163 10:03:36.889903 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11165 10:03:36.892772 test VIDIOC_G/S/ENUMINPUT: OK
11166 10:03:36.916328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11167 10:03:36.916607 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11169 10:03:36.919554 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11170 10:03:36.940853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11171 10:03:36.941111 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11173 10:03:36.943729 Inputs: 1 Audio Inputs: 0 Tuners: 0
11174 10:03:36.951416
11175 10:03:36.969830 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11176 10:03:36.993671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11177 10:03:36.994008 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11179 10:03:37.000193 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11180 10:03:37.020570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11181 10:03:37.020833 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11183 10:03:37.026697 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11184 10:03:37.045736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11185 10:03:37.046009 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11187 10:03:37.051893 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11188 10:03:37.070870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11189 10:03:37.071164 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11191 10:03:37.076968 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11192 10:03:37.099587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11193 10:03:37.099866 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11195 10:03:37.104997
11196 10:03:37.123549 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11197 10:03:37.146031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11198 10:03:37.146311 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11200 10:03:37.152851 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11201 10:03:37.175902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11202 10:03:37.176197 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11204 10:03:37.178959 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11205 10:03:37.198093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11206 10:03:37.198392 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11208 10:03:37.201247 test VIDIOC_G/S_EDID: OK (Not Supported)
11209 10:03:37.223792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11210 10:03:37.223881
11211 10:03:37.224117 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11213 10:03:37.234101 Control ioctls (Input 0):
11214 10:03:37.242071 <LAVA_SIGNAL_TESTSET STOP>
11215 10:03:37.242324 Received signal: <TESTSET> STOP
11216 10:03:37.242399 Closing test_set Input-ioctls
11217 10:03:37.251467 <LAVA_SIGNAL_TESTSET START Control-ioctls-Input-0>
11218 10:03:37.251801 Received signal: <TESTSET> START Control-ioctls-Input-0
11219 10:03:37.251906 Starting test_set Control-ioctls-Input-0
11220 10:03:37.254495 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11221 10:03:37.284495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11222 10:03:37.284591 test VIDIOC_QUERYCTRL: OK
11223 10:03:37.284830 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11225 10:03:37.306010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11226 10:03:37.306266 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11228 10:03:37.309675 test VIDIOC_G/S_CTRL: OK
11229 10:03:37.332904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11230 10:03:37.333208 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11232 10:03:37.336570 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11233 10:03:37.358574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11234 10:03:37.358904 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11236 10:03:37.364925 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
11237 10:03:37.387312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass>
11238 10:03:37.387586 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass
11240 10:03:37.390603 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11241 10:03:37.413091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11242 10:03:37.413358 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11244 10:03:37.416391 Standard Controls: 16 Private Controls: 0
11245 10:03:37.427128
11246 10:03:37.437882 Format ioctls (Input 0):
11247 10:03:37.445418 <LAVA_SIGNAL_TESTSET STOP>
11248 10:03:37.445701 Received signal: <TESTSET> STOP
11249 10:03:37.445774 Closing test_set Control-ioctls-Input-0
11250 10:03:37.455656 <LAVA_SIGNAL_TESTSET START Format-ioctls-Input-0>
11251 10:03:37.455999 Received signal: <TESTSET> START Format-ioctls-Input-0
11252 10:03:37.456075 Starting test_set Format-ioctls-Input-0
11253 10:03:37.458675 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11254 10:03:37.482932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11255 10:03:37.483328 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11257 10:03:37.486020 test VIDIOC_G/S_PARM: OK
11258 10:03:37.505437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11259 10:03:37.505819 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11261 10:03:37.508496 test VIDIOC_G_FBUF: OK (Not Supported)
11262 10:03:37.530659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11263 10:03:37.530984 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11265 10:03:37.534468 test VIDIOC_G_FMT: OK
11266 10:03:37.575551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11267 10:03:37.575882 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11269 10:03:37.578565 test VIDIOC_TRY_FMT: OK
11270 10:03:37.600528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11271 10:03:37.600937 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11273 10:03:37.607370 warn: ../utils/v4l2-compliance/v4l2-test-formats.cpp(1046): Could not set fmt2
11274 10:03:37.610410 test VIDIOC_S_FMT: OK
11275 10:03:37.636210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass>
11276 10:03:37.636533 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass
11278 10:03:37.639394 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11279 10:03:37.663395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11280 10:03:37.663735 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11282 10:03:37.666667 test Cropping: OK (Not Supported)
11283 10:03:37.689355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11284 10:03:37.689692 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11286 10:03:37.693131 test Composing: OK (Not Supported)
11287 10:03:37.713438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11288 10:03:37.713734 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11290 10:03:37.716891 test Scaling: OK (Not Supported)
11291 10:03:37.743676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11292 10:03:37.743840
11293 10:03:37.744094 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11295 10:03:37.756498 Codec ioctls (Input 0):
11296 10:03:37.764550 <LAVA_SIGNAL_TESTSET STOP>
11297 10:03:37.764830 Received signal: <TESTSET> STOP
11298 10:03:37.764900 Closing test_set Format-ioctls-Input-0
11299 10:03:37.774783 <LAVA_SIGNAL_TESTSET START Codec-ioctls-Input-0>
11300 10:03:37.775064 Received signal: <TESTSET> START Codec-ioctls-Input-0
11301 10:03:37.775136 Starting test_set Codec-ioctls-Input-0
11302 10:03:37.778155 test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
11303 10:03:37.800551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11304 10:03:37.800828 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11306 10:03:37.807366 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11307 10:03:37.827203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11308 10:03:37.827536 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11310 10:03:37.833370 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11311 10:03:37.855682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11312 10:03:37.855808
11313 10:03:37.856094 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11315 10:03:37.866744 Buffer ioctls (Input 0):
11316 10:03:37.874564 <LAVA_SIGNAL_TESTSET STOP>
11317 10:03:37.874825 Received signal: <TESTSET> STOP
11318 10:03:37.874897 Closing test_set Codec-ioctls-Input-0
11319 10:03:37.884902 <LAVA_SIGNAL_TESTSET START Buffer-ioctls-Input-0>
11320 10:03:37.885163 Received signal: <TESTSET> START Buffer-ioctls-Input-0
11321 10:03:37.885238 Starting test_set Buffer-ioctls-Input-0
11322 10:03:37.888423 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11323 10:03:37.912506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11324 10:03:37.912615 test VIDIOC_EXPBUF: OK
11325 10:03:37.912858 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11327 10:03:37.937207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11328 10:03:37.937476 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11330 10:03:37.940446 test Requests: OK (Not Supported)
11331 10:03:37.970112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11332 10:03:37.970223
11333 10:03:37.970478 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11335 10:03:37.985030 Test input 0:
11336 10:03:37.994072
11337 10:03:38.004802 Streaming ioctls:
11338 10:03:38.015287 <LAVA_SIGNAL_TESTSET STOP>
11339 10:03:38.015579 Received signal: <TESTSET> STOP
11340 10:03:38.015653 Closing test_set Buffer-ioctls-Input-0
11341 10:03:38.025584 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11342 10:03:38.025846 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11343 10:03:38.025920 Starting test_set Streaming-ioctls_Test-input-0
11344 10:03:38.028760 test read/write: OK (Not Supported)
11345 10:03:38.053707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11346 10:03:38.053984 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11348 10:03:38.056857 test blocking wait: OK
11349 10:03:38.084413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=pass>
11350 10:03:38.084694 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=pass
11352 10:03:38.093916 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL
11353 10:03:38.097446 test MMAP (no poll): FAIL
11354 10:03:38.125451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-no-poll RESULT=fail>
11355 10:03:38.125720 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-no-poll RESULT=fail
11357 10:03:38.135761 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL
11358 10:03:38.142062 test MMAP (select): FAIL
11359 10:03:38.169106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11360 10:03:38.169381 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11362 10:03:38.179204 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL
11363 10:03:38.179301 test MMAP (epoll): FAIL
11364 10:03:38.206997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11365 10:03:38.207117
11366 10:03:38.207360 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11368 10:03:38.221669
11369 10:03:38.411663
11370 10:03:38.421488 test USERPTR (no poll): OK
11371 10:03:38.448414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-no-poll RESULT=pass>
11372 10:03:38.448530
11373 10:03:38.448800 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-no-poll RESULT=pass
11375 10:03:38.461728
11376 10:03:38.649439
11377 10:03:38.660835 test USERPTR (select): OK
11378 10:03:38.685665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=pass>
11379 10:03:38.685976 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=pass
11381 10:03:38.688697 test DMABUF: Cannot test, specify --expbuf-device
11382 10:03:38.697885
11383 10:03:38.720065 Total for uvcvideo device /dev/video0: 53, Succeeded: 50, Failed: 3, Warnings: 3
11384 10:03:38.725369 <LAVA_TEST_RUNNER EXIT>
11385 10:03:38.725635 ok: lava_test_shell seems to have completed
11386 10:03:38.725714 Marking unfinished test run as failed
11388 10:03:38.726671 Composing:
result: pass
set: Format-ioctls-Input-0
Cropping:
result: pass
set: Format-ioctls-Input-0
MC-information-see-Media-Driver-Info-above:
result: pass
set: Required-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-no-poll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls-Input-0
Scaling:
result: pass
set: Format-ioctls-Input-0
USERPTR-no-poll:
result: pass
set: Streaming-ioctls_Test-input-0
USERPTR-select:
result: pass
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls-Input-0
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls-Input-0
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls-Input-0
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_S_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: pass
set: Control-ioctls-Input-0
blocking-wait:
result: pass
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video0-open:
result: pass
set: Allow-for-multiple-opens
11389 10:03:38.726798 end: 3.1 lava-test-shell (duration 00:00:10) [common]
11390 10:03:38.726884 end: 3 lava-test-retry (duration 00:00:10) [common]
11391 10:03:38.726980 start: 4 finalize (timeout 00:07:59) [common]
11392 10:03:38.727073 start: 4.1 power-off (timeout 00:00:30) [common]
11393 10:03:38.727226 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11394 10:03:38.804854 >> Command sent successfully.
11395 10:03:38.807812 Returned 0 in 0 seconds
11396 10:03:38.908294 end: 4.1 power-off (duration 00:00:00) [common]
11398 10:03:38.908747 start: 4.2 read-feedback (timeout 00:07:59) [common]
11399 10:03:38.909086 Listened to connection for namespace 'common' for up to 1s
11400 10:03:39.909645 Finalising connection for namespace 'common'
11401 10:03:39.909822 Disconnecting from shell: Finalise
11402 10:03:39.909913 / #
11403 10:03:40.010233 end: 4.2 read-feedback (duration 00:00:01) [common]
11404 10:03:40.010438 end: 4 finalize (duration 00:00:01) [common]
11405 10:03:40.010587 Cleaning after the job
11406 10:03:40.010718 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12073297/tftp-deploy-118urgzn/ramdisk
11407 10:03:40.016284 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12073297/tftp-deploy-118urgzn/kernel
11408 10:03:40.032431 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12073297/tftp-deploy-118urgzn/dtb
11409 10:03:40.032634 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12073297/tftp-deploy-118urgzn/modules
11410 10:03:40.039882 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12073297
11411 10:03:40.110714 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12073297
11412 10:03:40.110892 Job finished correctly