Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Errors: 27
- Kernel Warnings: 19
- Boot result: PASS
- Errors: 1
1 09:58:36.231827 lava-dispatcher, installed at version: 2023.10
2 09:58:36.232044 start: 0 validate
3 09:58:36.232177 Start time: 2023-11-24 09:58:36.232170+00:00 (UTC)
4 09:58:36.232299 Using caching service: 'http://localhost/cache/?uri=%s'
5 09:58:36.232437 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 09:58:36.498890 Using caching service: 'http://localhost/cache/?uri=%s'
7 09:58:36.499070 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 09:58:59.001222 Using caching service: 'http://localhost/cache/?uri=%s'
9 09:58:59.002020 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 09:58:59.274628 Using caching service: 'http://localhost/cache/?uri=%s'
11 09:58:59.275378 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 09:59:04.548864 validate duration: 28.32
14 09:59:04.550310 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 09:59:04.550870 start: 1.1 download-retry (timeout 00:10:00) [common]
16 09:59:04.551432 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 09:59:04.552076 Not decompressing ramdisk as can be used compressed.
18 09:59:04.552543 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230623.0/arm64/rootfs.cpio.gz
19 09:59:04.552910 saving as /var/lib/lava/dispatcher/tmp/12073268/tftp-deploy-2obxkcdy/ramdisk/rootfs.cpio.gz
20 09:59:04.553300 total size: 8181372 (7 MB)
21 09:59:04.827503 progress 0 % (0 MB)
22 09:59:04.829826 progress 5 % (0 MB)
23 09:59:04.831887 progress 10 % (0 MB)
24 09:59:04.834159 progress 15 % (1 MB)
25 09:59:04.836222 progress 20 % (1 MB)
26 09:59:04.838534 progress 25 % (1 MB)
27 09:59:04.840622 progress 30 % (2 MB)
28 09:59:04.843007 progress 35 % (2 MB)
29 09:59:04.845199 progress 40 % (3 MB)
30 09:59:04.847582 progress 45 % (3 MB)
31 09:59:04.849763 progress 50 % (3 MB)
32 09:59:04.852007 progress 55 % (4 MB)
33 09:59:04.854146 progress 60 % (4 MB)
34 09:59:04.856371 progress 65 % (5 MB)
35 09:59:04.858467 progress 70 % (5 MB)
36 09:59:04.860709 progress 75 % (5 MB)
37 09:59:04.862805 progress 80 % (6 MB)
38 09:59:04.865010 progress 85 % (6 MB)
39 09:59:04.867105 progress 90 % (7 MB)
40 09:59:04.869314 progress 95 % (7 MB)
41 09:59:04.871401 progress 100 % (7 MB)
42 09:59:04.871603 7 MB downloaded in 0.32 s (24.51 MB/s)
43 09:59:04.871755 end: 1.1.1 http-download (duration 00:00:00) [common]
45 09:59:04.871996 end: 1.1 download-retry (duration 00:00:00) [common]
46 09:59:04.872081 start: 1.2 download-retry (timeout 00:10:00) [common]
47 09:59:04.872165 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 09:59:04.872309 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 09:59:04.872416 saving as /var/lib/lava/dispatcher/tmp/12073268/tftp-deploy-2obxkcdy/kernel/Image
50 09:59:04.872476 total size: 49107456 (46 MB)
51 09:59:04.872537 No compression specified
52 09:59:04.873682 progress 0 % (0 MB)
53 09:59:04.886319 progress 5 % (2 MB)
54 09:59:04.899242 progress 10 % (4 MB)
55 09:59:04.911974 progress 15 % (7 MB)
56 09:59:04.925001 progress 20 % (9 MB)
57 09:59:04.938020 progress 25 % (11 MB)
58 09:59:04.950934 progress 30 % (14 MB)
59 09:59:04.963844 progress 35 % (16 MB)
60 09:59:04.976662 progress 40 % (18 MB)
61 09:59:04.989709 progress 45 % (21 MB)
62 09:59:05.002691 progress 50 % (23 MB)
63 09:59:05.015763 progress 55 % (25 MB)
64 09:59:05.028905 progress 60 % (28 MB)
65 09:59:05.042083 progress 65 % (30 MB)
66 09:59:05.055432 progress 70 % (32 MB)
67 09:59:05.068489 progress 75 % (35 MB)
68 09:59:05.081396 progress 80 % (37 MB)
69 09:59:05.094276 progress 85 % (39 MB)
70 09:59:05.107493 progress 90 % (42 MB)
71 09:59:05.120523 progress 95 % (44 MB)
72 09:59:05.133127 progress 100 % (46 MB)
73 09:59:05.133373 46 MB downloaded in 0.26 s (179.51 MB/s)
74 09:59:05.133529 end: 1.2.1 http-download (duration 00:00:00) [common]
76 09:59:05.133770 end: 1.2 download-retry (duration 00:00:00) [common]
77 09:59:05.133868 start: 1.3 download-retry (timeout 00:09:59) [common]
78 09:59:05.133955 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 09:59:05.134098 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 09:59:05.134166 saving as /var/lib/lava/dispatcher/tmp/12073268/tftp-deploy-2obxkcdy/dtb/mt8192-asurada-spherion-r0.dtb
81 09:59:05.134225 total size: 47278 (0 MB)
82 09:59:05.134286 No compression specified
83 09:59:05.135403 progress 69 % (0 MB)
84 09:59:05.135677 progress 100 % (0 MB)
85 09:59:05.135837 0 MB downloaded in 0.00 s (28.02 MB/s)
86 09:59:05.135962 end: 1.3.1 http-download (duration 00:00:00) [common]
88 09:59:05.136182 end: 1.3 download-retry (duration 00:00:00) [common]
89 09:59:05.136270 start: 1.4 download-retry (timeout 00:09:59) [common]
90 09:59:05.136351 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 09:59:05.136465 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 09:59:05.136531 saving as /var/lib/lava/dispatcher/tmp/12073268/tftp-deploy-2obxkcdy/modules/modules.tar
93 09:59:05.136590 total size: 8622040 (8 MB)
94 09:59:05.136649 Using unxz to decompress xz
95 09:59:05.140876 progress 0 % (0 MB)
96 09:59:05.163378 progress 5 % (0 MB)
97 09:59:05.189309 progress 10 % (0 MB)
98 09:59:05.215648 progress 15 % (1 MB)
99 09:59:05.240556 progress 20 % (1 MB)
100 09:59:05.269117 progress 25 % (2 MB)
101 09:59:05.299673 progress 30 % (2 MB)
102 09:59:05.331557 progress 35 % (2 MB)
103 09:59:05.357645 progress 40 % (3 MB)
104 09:59:05.383989 progress 45 % (3 MB)
105 09:59:05.411652 progress 50 % (4 MB)
106 09:59:05.438107 progress 55 % (4 MB)
107 09:59:05.464032 progress 60 % (4 MB)
108 09:59:05.493648 progress 65 % (5 MB)
109 09:59:05.521169 progress 70 % (5 MB)
110 09:59:05.547121 progress 75 % (6 MB)
111 09:59:05.576225 progress 80 % (6 MB)
112 09:59:05.604184 progress 85 % (7 MB)
113 09:59:05.631671 progress 90 % (7 MB)
114 09:59:05.664265 progress 95 % (7 MB)
115 09:59:05.696641 progress 100 % (8 MB)
116 09:59:05.701804 8 MB downloaded in 0.57 s (14.55 MB/s)
117 09:59:05.702072 end: 1.4.1 http-download (duration 00:00:01) [common]
119 09:59:05.702343 end: 1.4 download-retry (duration 00:00:01) [common]
120 09:59:05.702440 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 09:59:05.702540 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 09:59:05.702627 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 09:59:05.702715 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 09:59:05.702950 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12073268/lava-overlay-lqs5rs1e
125 09:59:05.703090 makedir: /var/lib/lava/dispatcher/tmp/12073268/lava-overlay-lqs5rs1e/lava-12073268/bin
126 09:59:05.703201 makedir: /var/lib/lava/dispatcher/tmp/12073268/lava-overlay-lqs5rs1e/lava-12073268/tests
127 09:59:05.703305 makedir: /var/lib/lava/dispatcher/tmp/12073268/lava-overlay-lqs5rs1e/lava-12073268/results
128 09:59:05.703428 Creating /var/lib/lava/dispatcher/tmp/12073268/lava-overlay-lqs5rs1e/lava-12073268/bin/lava-add-keys
129 09:59:05.703585 Creating /var/lib/lava/dispatcher/tmp/12073268/lava-overlay-lqs5rs1e/lava-12073268/bin/lava-add-sources
130 09:59:05.703724 Creating /var/lib/lava/dispatcher/tmp/12073268/lava-overlay-lqs5rs1e/lava-12073268/bin/lava-background-process-start
131 09:59:05.703862 Creating /var/lib/lava/dispatcher/tmp/12073268/lava-overlay-lqs5rs1e/lava-12073268/bin/lava-background-process-stop
132 09:59:05.703994 Creating /var/lib/lava/dispatcher/tmp/12073268/lava-overlay-lqs5rs1e/lava-12073268/bin/lava-common-functions
133 09:59:05.704125 Creating /var/lib/lava/dispatcher/tmp/12073268/lava-overlay-lqs5rs1e/lava-12073268/bin/lava-echo-ipv4
134 09:59:05.704257 Creating /var/lib/lava/dispatcher/tmp/12073268/lava-overlay-lqs5rs1e/lava-12073268/bin/lava-install-packages
135 09:59:05.704388 Creating /var/lib/lava/dispatcher/tmp/12073268/lava-overlay-lqs5rs1e/lava-12073268/bin/lava-installed-packages
136 09:59:05.704518 Creating /var/lib/lava/dispatcher/tmp/12073268/lava-overlay-lqs5rs1e/lava-12073268/bin/lava-os-build
137 09:59:05.704648 Creating /var/lib/lava/dispatcher/tmp/12073268/lava-overlay-lqs5rs1e/lava-12073268/bin/lava-probe-channel
138 09:59:05.704778 Creating /var/lib/lava/dispatcher/tmp/12073268/lava-overlay-lqs5rs1e/lava-12073268/bin/lava-probe-ip
139 09:59:05.704908 Creating /var/lib/lava/dispatcher/tmp/12073268/lava-overlay-lqs5rs1e/lava-12073268/bin/lava-target-ip
140 09:59:05.705039 Creating /var/lib/lava/dispatcher/tmp/12073268/lava-overlay-lqs5rs1e/lava-12073268/bin/lava-target-mac
141 09:59:05.705168 Creating /var/lib/lava/dispatcher/tmp/12073268/lava-overlay-lqs5rs1e/lava-12073268/bin/lava-target-storage
142 09:59:05.705304 Creating /var/lib/lava/dispatcher/tmp/12073268/lava-overlay-lqs5rs1e/lava-12073268/bin/lava-test-case
143 09:59:05.705438 Creating /var/lib/lava/dispatcher/tmp/12073268/lava-overlay-lqs5rs1e/lava-12073268/bin/lava-test-event
144 09:59:05.705567 Creating /var/lib/lava/dispatcher/tmp/12073268/lava-overlay-lqs5rs1e/lava-12073268/bin/lava-test-feedback
145 09:59:05.705711 Creating /var/lib/lava/dispatcher/tmp/12073268/lava-overlay-lqs5rs1e/lava-12073268/bin/lava-test-raise
146 09:59:05.705843 Creating /var/lib/lava/dispatcher/tmp/12073268/lava-overlay-lqs5rs1e/lava-12073268/bin/lava-test-reference
147 09:59:05.705973 Creating /var/lib/lava/dispatcher/tmp/12073268/lava-overlay-lqs5rs1e/lava-12073268/bin/lava-test-runner
148 09:59:05.706103 Creating /var/lib/lava/dispatcher/tmp/12073268/lava-overlay-lqs5rs1e/lava-12073268/bin/lava-test-set
149 09:59:05.706236 Creating /var/lib/lava/dispatcher/tmp/12073268/lava-overlay-lqs5rs1e/lava-12073268/bin/lava-test-shell
150 09:59:05.706368 Updating /var/lib/lava/dispatcher/tmp/12073268/lava-overlay-lqs5rs1e/lava-12073268/bin/lava-install-packages (oe)
151 09:59:05.706526 Updating /var/lib/lava/dispatcher/tmp/12073268/lava-overlay-lqs5rs1e/lava-12073268/bin/lava-installed-packages (oe)
152 09:59:05.706652 Creating /var/lib/lava/dispatcher/tmp/12073268/lava-overlay-lqs5rs1e/lava-12073268/environment
153 09:59:05.706755 LAVA metadata
154 09:59:05.706830 - LAVA_JOB_ID=12073268
155 09:59:05.706897 - LAVA_DISPATCHER_IP=192.168.201.1
156 09:59:05.707005 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 09:59:05.707074 skipped lava-vland-overlay
158 09:59:05.707150 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 09:59:05.707238 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 09:59:05.707302 skipped lava-multinode-overlay
161 09:59:05.707378 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 09:59:05.707462 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 09:59:05.707537 Loading test definitions
164 09:59:05.707641 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 09:59:05.707718 Using /lava-12073268 at stage 0
166 09:59:05.708048 uuid=12073268_1.5.2.3.1 testdef=None
167 09:59:05.708139 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 09:59:05.708226 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 09:59:05.708783 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 09:59:05.709012 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 09:59:05.709699 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 09:59:05.710004 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 09:59:05.710647 runner path: /var/lib/lava/dispatcher/tmp/12073268/lava-overlay-lqs5rs1e/lava-12073268/0/tests/0_dmesg test_uuid 12073268_1.5.2.3.1
176 09:59:05.710816 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 09:59:05.711049 start: 1.5.2.3.5 inline-repo-action (timeout 00:09:59) [common]
179 09:59:05.711123 Using /lava-12073268 at stage 1
180 09:59:05.711438 uuid=12073268_1.5.2.3.5 testdef=None
181 09:59:05.711529 end: 1.5.2.3.5 inline-repo-action (duration 00:00:00) [common]
182 09:59:05.711615 start: 1.5.2.3.6 test-overlay (timeout 00:09:59) [common]
183 09:59:05.712162 end: 1.5.2.3.6 test-overlay (duration 00:00:00) [common]
185 09:59:05.712416 start: 1.5.2.3.7 test-install-overlay (timeout 00:09:59) [common]
186 09:59:05.713601 end: 1.5.2.3.7 test-install-overlay (duration 00:00:00) [common]
188 09:59:05.713842 start: 1.5.2.3.8 test-runscript-overlay (timeout 00:09:59) [common]
189 09:59:05.714497 runner path: /var/lib/lava/dispatcher/tmp/12073268/lava-overlay-lqs5rs1e/lava-12073268/1/tests/1_bootrr test_uuid 12073268_1.5.2.3.5
190 09:59:05.714656 end: 1.5.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
192 09:59:05.714868 Creating lava-test-runner.conf files
193 09:59:05.714933 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12073268/lava-overlay-lqs5rs1e/lava-12073268/0 for stage 0
194 09:59:05.715028 - 0_dmesg
195 09:59:05.715113 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12073268/lava-overlay-lqs5rs1e/lava-12073268/1 for stage 1
196 09:59:05.715207 - 1_bootrr
197 09:59:05.715303 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
198 09:59:05.715388 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
199 09:59:05.723644 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
200 09:59:05.723797 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
201 09:59:05.723891 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
202 09:59:05.723981 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
203 09:59:05.724072 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
204 09:59:05.983084 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:00) [common]
205 09:59:05.983493 start: 1.5.4 extract-modules (timeout 00:09:59) [common]
206 09:59:05.983616 extracting modules file /var/lib/lava/dispatcher/tmp/12073268/tftp-deploy-2obxkcdy/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12073268/extract-overlay-ramdisk-t36en566/ramdisk
207 09:59:06.221272 end: 1.5.4 extract-modules (duration 00:00:00) [common]
208 09:59:06.221450 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
209 09:59:06.221551 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12073268/compress-overlay-vp9aro2r/overlay-1.5.2.4.tar.gz to ramdisk
210 09:59:06.221744 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12073268/compress-overlay-vp9aro2r/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12073268/extract-overlay-ramdisk-t36en566/ramdisk
211 09:59:06.230269 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
212 09:59:06.230403 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
213 09:59:06.230494 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
214 09:59:06.230585 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
215 09:59:06.230667 Building ramdisk /var/lib/lava/dispatcher/tmp/12073268/extract-overlay-ramdisk-t36en566/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12073268/extract-overlay-ramdisk-t36en566/ramdisk
216 09:59:06.647767 >> 145311 blocks
217 09:59:09.108202 rename /var/lib/lava/dispatcher/tmp/12073268/extract-overlay-ramdisk-t36en566/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12073268/tftp-deploy-2obxkcdy/ramdisk/ramdisk.cpio.gz
218 09:59:09.108665 end: 1.5.7 compress-ramdisk (duration 00:00:03) [common]
219 09:59:09.108803 start: 1.5.8 prepare-kernel (timeout 00:09:55) [common]
220 09:59:09.108917 start: 1.5.8.1 prepare-fit (timeout 00:09:55) [common]
221 09:59:09.109034 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12073268/tftp-deploy-2obxkcdy/kernel/Image'
222 09:59:22.432080 Returned 0 in 13 seconds
223 09:59:22.532835 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12073268/tftp-deploy-2obxkcdy/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12073268/tftp-deploy-2obxkcdy/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12073268/tftp-deploy-2obxkcdy/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12073268/tftp-deploy-2obxkcdy/kernel/image.itb
224 09:59:22.957021 output: FIT description: Kernel Image image with one or more FDT blobs
225 09:59:22.957507 output: Created: Fri Nov 24 09:59:22 2023
226 09:59:22.957672 output: Image 0 (kernel-1)
227 09:59:22.957770 output: Description:
228 09:59:22.957863 output: Created: Fri Nov 24 09:59:22 2023
229 09:59:22.957956 output: Type: Kernel Image
230 09:59:22.958048 output: Compression: lzma compressed
231 09:59:22.958143 output: Data Size: 11047542 Bytes = 10788.62 KiB = 10.54 MiB
232 09:59:22.958239 output: Architecture: AArch64
233 09:59:22.958338 output: OS: Linux
234 09:59:22.958437 output: Load Address: 0x00000000
235 09:59:22.958534 output: Entry Point: 0x00000000
236 09:59:22.958630 output: Hash algo: crc32
237 09:59:22.958718 output: Hash value: 2edffaa3
238 09:59:22.958812 output: Image 1 (fdt-1)
239 09:59:22.958903 output: Description: mt8192-asurada-spherion-r0
240 09:59:22.958991 output: Created: Fri Nov 24 09:59:22 2023
241 09:59:22.959079 output: Type: Flat Device Tree
242 09:59:22.959167 output: Compression: uncompressed
243 09:59:22.959255 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
244 09:59:22.959343 output: Architecture: AArch64
245 09:59:22.959430 output: Hash algo: crc32
246 09:59:22.959517 output: Hash value: cc4352de
247 09:59:22.959605 output: Image 2 (ramdisk-1)
248 09:59:22.959691 output: Description: unavailable
249 09:59:22.959777 output: Created: Fri Nov 24 09:59:22 2023
250 09:59:22.959865 output: Type: RAMDisk Image
251 09:59:22.959951 output: Compression: Unknown Compression
252 09:59:22.960056 output: Data Size: 21400585 Bytes = 20899.01 KiB = 20.41 MiB
253 09:59:22.960177 output: Architecture: AArch64
254 09:59:22.960265 output: OS: Linux
255 09:59:22.960384 output: Load Address: unavailable
256 09:59:22.960504 output: Entry Point: unavailable
257 09:59:22.960593 output: Hash algo: crc32
258 09:59:22.960683 output: Hash value: f8e9ddc3
259 09:59:22.960774 output: Default Configuration: 'conf-1'
260 09:59:22.960865 output: Configuration 0 (conf-1)
261 09:59:22.960954 output: Description: mt8192-asurada-spherion-r0
262 09:59:22.961045 output: Kernel: kernel-1
263 09:59:22.961135 output: Init Ramdisk: ramdisk-1
264 09:59:22.961226 output: FDT: fdt-1
265 09:59:22.961316 output: Loadables: kernel-1
266 09:59:22.961407 output:
267 09:59:22.961718 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
268 09:59:22.961870 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
269 09:59:22.962037 end: 1.5 prepare-tftp-overlay (duration 00:00:17) [common]
270 09:59:22.962181 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:42) [common]
271 09:59:22.962301 No LXC device requested
272 09:59:22.962452 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
273 09:59:22.962596 start: 1.7 deploy-device-env (timeout 00:09:42) [common]
274 09:59:22.962715 end: 1.7 deploy-device-env (duration 00:00:00) [common]
275 09:59:22.962821 Checking files for TFTP limit of 4294967296 bytes.
276 09:59:22.963539 end: 1 tftp-deploy (duration 00:00:18) [common]
277 09:59:22.963684 start: 2 depthcharge-action (timeout 00:05:00) [common]
278 09:59:22.963809 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
279 09:59:22.963990 substitutions:
280 09:59:22.964093 - {DTB}: 12073268/tftp-deploy-2obxkcdy/dtb/mt8192-asurada-spherion-r0.dtb
281 09:59:22.964191 - {INITRD}: 12073268/tftp-deploy-2obxkcdy/ramdisk/ramdisk.cpio.gz
282 09:59:22.964285 - {KERNEL}: 12073268/tftp-deploy-2obxkcdy/kernel/Image
283 09:59:22.964378 - {LAVA_MAC}: None
284 09:59:22.964486 - {PRESEED_CONFIG}: None
285 09:59:22.964591 - {PRESEED_LOCAL}: None
286 09:59:22.964681 - {RAMDISK}: 12073268/tftp-deploy-2obxkcdy/ramdisk/ramdisk.cpio.gz
287 09:59:22.964771 - {ROOT_PART}: None
288 09:59:22.964861 - {ROOT}: None
289 09:59:22.964956 - {SERVER_IP}: 192.168.201.1
290 09:59:22.965044 - {TEE}: None
291 09:59:22.965132 Parsed boot commands:
292 09:59:22.965221 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
293 09:59:22.965478 Parsed boot commands: tftpboot 192.168.201.1 12073268/tftp-deploy-2obxkcdy/kernel/image.itb 12073268/tftp-deploy-2obxkcdy/kernel/cmdline
294 09:59:22.965659 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
295 09:59:22.965789 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
296 09:59:22.965927 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
297 09:59:22.966052 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
298 09:59:22.966167 Not connected, no need to disconnect.
299 09:59:22.966280 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
300 09:59:22.966402 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
301 09:59:22.966522 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
302 09:59:22.971622 Setting prompt string to ['lava-test: # ']
303 09:59:22.972193 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
304 09:59:22.972383 end: 2.2.1 reset-connection (duration 00:00:00) [common]
305 09:59:22.972531 start: 2.2.2 reset-device (timeout 00:05:00) [common]
306 09:59:22.972882 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
307 09:59:22.973193 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
308 09:59:28.110133 >> Command sent successfully.
309 09:59:28.113359 Returned 0 in 5 seconds
310 09:59:28.213868 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
312 09:59:28.214353 end: 2.2.2 reset-device (duration 00:00:05) [common]
313 09:59:28.214501 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
314 09:59:28.214663 Setting prompt string to 'Starting depthcharge on Spherion...'
315 09:59:28.214811 Changing prompt to 'Starting depthcharge on Spherion...'
316 09:59:28.214948 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
317 09:59:28.215350 [Enter `^Ec?' for help]
318 09:59:28.386431
319 09:59:28.386638
320 09:59:28.386744 F0: 102B 0000
321 09:59:28.386840
322 09:59:28.386931 F3: 1001 0000 [0200]
323 09:59:28.387023
324 09:59:28.390203 F3: 1001 0000
325 09:59:28.390356
326 09:59:28.390459 F7: 102D 0000
327 09:59:28.390552
328 09:59:28.390644 F1: 0000 0000
329 09:59:28.390734
330 09:59:28.393216 V0: 0000 0000 [0001]
331 09:59:28.393363
332 09:59:28.393463 00: 0007 8000
333 09:59:28.393562
334 09:59:28.397300 01: 0000 0000
335 09:59:28.397457
336 09:59:28.397557 BP: 0C00 0209 [0000]
337 09:59:28.397753
338 09:59:28.400987 G0: 1182 0000
339 09:59:28.401135
340 09:59:28.401241 EC: 0000 0021 [4000]
341 09:59:28.401336
342 09:59:28.404337 S7: 0000 0000 [0000]
343 09:59:28.404488
344 09:59:28.404621 CC: 0000 0000 [0001]
345 09:59:28.404744
346 09:59:28.408090 T0: 0000 0040 [010F]
347 09:59:28.408247
348 09:59:28.408348 Jump to BL
349 09:59:28.408442
350 09:59:28.433256
351 09:59:28.433476
352 09:59:28.433604
353 09:59:28.440359 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
354 09:59:28.444302 ARM64: Exception handlers installed.
355 09:59:28.447910 ARM64: Testing exception
356 09:59:28.451697 ARM64: Done test exception
357 09:59:28.458852 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
358 09:59:28.465687 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
359 09:59:28.473124 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
360 09:59:28.483769 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
361 09:59:28.490269 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
362 09:59:28.500605 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
363 09:59:28.511109 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
364 09:59:28.517669 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
365 09:59:28.536057 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
366 09:59:28.539561 WDT: Last reset was cold boot
367 09:59:28.542579 SPI1(PAD0) initialized at 2873684 Hz
368 09:59:28.546204 SPI5(PAD0) initialized at 992727 Hz
369 09:59:28.549074 VBOOT: Loading verstage.
370 09:59:28.556187 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
371 09:59:28.559321 FMAP: Found "FLASH" version 1.1 at 0x20000.
372 09:59:28.562530 FMAP: base = 0x0 size = 0x800000 #areas = 25
373 09:59:28.566205 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
374 09:59:28.573318 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
375 09:59:28.579956 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
376 09:59:28.591324 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
377 09:59:28.591515
378 09:59:28.591630
379 09:59:28.602041 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
380 09:59:28.605426 ARM64: Exception handlers installed.
381 09:59:28.605597 ARM64: Testing exception
382 09:59:28.608532 ARM64: Done test exception
383 09:59:28.611795 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
384 09:59:28.618992 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
385 09:59:28.632207 Probing TPM: . done!
386 09:59:28.632370 TPM ready after 0 ms
387 09:59:28.638622 Connected to device vid:did:rid of 1ae0:0028:00
388 09:59:28.645607 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
389 09:59:28.705756 Initialized TPM device CR50 revision 0
390 09:59:28.716699 tlcl_send_startup: Startup return code is 0
391 09:59:28.716906 TPM: setup succeeded
392 09:59:28.728381 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
393 09:59:28.737505 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
394 09:59:28.751032 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
395 09:59:28.758397 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
396 09:59:28.761847 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
397 09:59:28.765434 in-header: 03 07 00 00 08 00 00 00
398 09:59:28.769058 in-data: aa e4 47 04 13 02 00 00
399 09:59:28.772735 Chrome EC: UHEPI supported
400 09:59:28.779827 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
401 09:59:28.783585 in-header: 03 95 00 00 08 00 00 00
402 09:59:28.787101 in-data: 18 20 20 08 00 00 00 00
403 09:59:28.787271 Phase 1
404 09:59:28.790892 FMAP: area GBB found @ 3f5000 (12032 bytes)
405 09:59:28.798122 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
406 09:59:28.802116 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
407 09:59:28.806296 Recovery requested (1009000e)
408 09:59:28.816203 TPM: Extending digest for VBOOT: boot mode into PCR 0
409 09:59:28.819615 tlcl_extend: response is 0
410 09:59:28.831130 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
411 09:59:28.834563 tlcl_extend: response is 0
412 09:59:28.842061 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
413 09:59:28.861027 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
414 09:59:28.867845 BS: bootblock times (exec / console): total (unknown) / 148 ms
415 09:59:28.868042
416 09:59:28.868154
417 09:59:28.878183 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
418 09:59:28.881428 ARM64: Exception handlers installed.
419 09:59:28.884445 ARM64: Testing exception
420 09:59:28.884593 ARM64: Done test exception
421 09:59:28.906994 pmic_efuse_setting: Set efuses in 11 msecs
422 09:59:28.910168 pmwrap_interface_init: Select PMIF_VLD_RDY
423 09:59:28.916922 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
424 09:59:28.920265 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
425 09:59:28.927452 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
426 09:59:28.931383 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
427 09:59:28.935062 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
428 09:59:28.938623 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
429 09:59:28.946185 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
430 09:59:28.949857 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
431 09:59:28.953543 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
432 09:59:28.960492 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
433 09:59:28.964402 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
434 09:59:28.968243 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
435 09:59:28.971282 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
436 09:59:28.980015 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
437 09:59:28.983514 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
438 09:59:28.990903 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
439 09:59:28.994604 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
440 09:59:29.002371 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
441 09:59:29.005829 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
442 09:59:29.013126 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
443 09:59:29.016956 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
444 09:59:29.024941 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
445 09:59:29.031376 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
446 09:59:29.035189 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
447 09:59:29.039054 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
448 09:59:29.046609 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
449 09:59:29.050238 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
450 09:59:29.057515 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
451 09:59:29.061254 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
452 09:59:29.065035 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
453 09:59:29.072093 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
454 09:59:29.075783 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
455 09:59:29.079543 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
456 09:59:29.086604 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
457 09:59:29.090352 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
458 09:59:29.097953 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
459 09:59:29.102039 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
460 09:59:29.105685 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
461 09:59:29.109250 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
462 09:59:29.117122 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
463 09:59:29.120676 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
464 09:59:29.124004 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
465 09:59:29.128041 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
466 09:59:29.131268 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
467 09:59:29.135224 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
468 09:59:29.142783 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
469 09:59:29.146391 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
470 09:59:29.149905 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
471 09:59:29.153738 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
472 09:59:29.157279 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
473 09:59:29.160835 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
474 09:59:29.168255 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
475 09:59:29.179124 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
476 09:59:29.183079 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
477 09:59:29.190832 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
478 09:59:29.197790 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
479 09:59:29.205474 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
480 09:59:29.209118 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
481 09:59:29.212338 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
482 09:59:29.220126 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x39
483 09:59:29.224032 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
484 09:59:29.232377 [RTC]rtc_osc_init,62: osc32con val = 0xde70
485 09:59:29.235694 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
486 09:59:29.244755 [RTC]rtc_get_frequency_meter,154: input=15, output=758
487 09:59:29.254477 [RTC]rtc_get_frequency_meter,154: input=23, output=940
488 09:59:29.263326 [RTC]rtc_get_frequency_meter,154: input=19, output=850
489 09:59:29.273998 [RTC]rtc_get_frequency_meter,154: input=17, output=805
490 09:59:29.282777 [RTC]rtc_get_frequency_meter,154: input=16, output=781
491 09:59:29.292086 [RTC]rtc_get_frequency_meter,154: input=16, output=781
492 09:59:29.301939 [RTC]rtc_get_frequency_meter,154: input=17, output=803
493 09:59:29.305159 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
494 09:59:29.312513 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde71
495 09:59:29.316693 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
496 09:59:29.320108 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
497 09:59:29.323662 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
498 09:59:29.327040 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
499 09:59:29.331159 ADC[4]: Raw value=906573 ID=7
500 09:59:29.334845 ADC[3]: Raw value=213441 ID=1
501 09:59:29.335001 RAM Code: 0x71
502 09:59:29.338497 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
503 09:59:29.346166 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
504 09:59:29.353343 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
505 09:59:29.361041 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
506 09:59:29.361232 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
507 09:59:29.366122 in-header: 03 07 00 00 08 00 00 00
508 09:59:29.370115 in-data: aa e4 47 04 13 02 00 00
509 09:59:29.373348 Chrome EC: UHEPI supported
510 09:59:29.380419 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
511 09:59:29.383579 in-header: 03 95 00 00 08 00 00 00
512 09:59:29.387459 in-data: 18 20 20 08 00 00 00 00
513 09:59:29.391019 MRC: failed to locate region type 0.
514 09:59:29.394747 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
515 09:59:29.398902 DRAM-K: Running full calibration
516 09:59:29.405967 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
517 09:59:29.406158 header.status = 0x0
518 09:59:29.409181 header.version = 0x6 (expected: 0x6)
519 09:59:29.413211 header.size = 0xd00 (expected: 0xd00)
520 09:59:29.417083 header.flags = 0x0
521 09:59:29.420124 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
522 09:59:29.439820 read SPI 0x72590 0x1c583: 12501 us, 9287 KB/s, 74.296 Mbps
523 09:59:29.447612 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
524 09:59:29.447779 dram_init: ddr_geometry: 2
525 09:59:29.451687 [EMI] MDL number = 2
526 09:59:29.454929 [EMI] Get MDL freq = 0
527 09:59:29.455059 dram_init: ddr_type: 0
528 09:59:29.458708 is_discrete_lpddr4: 1
529 09:59:29.458825 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
530 09:59:29.458894
531 09:59:29.462783
532 09:59:29.462892 [Bian_co] ETT version 0.0.0.1
533 09:59:29.469591 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
534 09:59:29.469743
535 09:59:29.474127 dramc_set_vcore_voltage set vcore to 650000
536 09:59:29.474249 Read voltage for 800, 4
537 09:59:29.474321 Vio18 = 0
538 09:59:29.477568 Vcore = 650000
539 09:59:29.477686 Vdram = 0
540 09:59:29.477756 Vddq = 0
541 09:59:29.477818 Vmddr = 0
542 09:59:29.481654 dram_init: config_dvfs: 1
543 09:59:29.485329 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
544 09:59:29.492929 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
545 09:59:29.496376 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
546 09:59:29.500038 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
547 09:59:29.503550 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
548 09:59:29.507008 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
549 09:59:29.510330 MEM_TYPE=3, freq_sel=18
550 09:59:29.513977 sv_algorithm_assistance_LP4_1600
551 09:59:29.517064 ============ PULL DRAM RESETB DOWN ============
552 09:59:29.520654 ========== PULL DRAM RESETB DOWN end =========
553 09:59:29.524449 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
554 09:59:29.527899 ===================================
555 09:59:29.531846 LPDDR4 DRAM CONFIGURATION
556 09:59:29.535401 ===================================
557 09:59:29.535536 EX_ROW_EN[0] = 0x0
558 09:59:29.539336 EX_ROW_EN[1] = 0x0
559 09:59:29.539469 LP4Y_EN = 0x0
560 09:59:29.542585 WORK_FSP = 0x0
561 09:59:29.542697 WL = 0x2
562 09:59:29.546162 RL = 0x2
563 09:59:29.546272 BL = 0x2
564 09:59:29.549635 RPST = 0x0
565 09:59:29.549739 RD_PRE = 0x0
566 09:59:29.552731 WR_PRE = 0x1
567 09:59:29.552836 WR_PST = 0x0
568 09:59:29.556318 DBI_WR = 0x0
569 09:59:29.556422 DBI_RD = 0x0
570 09:59:29.559389 OTF = 0x1
571 09:59:29.563262 ===================================
572 09:59:29.566892 ===================================
573 09:59:29.567019 ANA top config
574 09:59:29.570706 ===================================
575 09:59:29.574620 DLL_ASYNC_EN = 0
576 09:59:29.574744 ALL_SLAVE_EN = 1
577 09:59:29.577199 NEW_RANK_MODE = 1
578 09:59:29.580801 DLL_IDLE_MODE = 1
579 09:59:29.584097 LP45_APHY_COMB_EN = 1
580 09:59:29.584211 TX_ODT_DIS = 1
581 09:59:29.587712 NEW_8X_MODE = 1
582 09:59:29.591692 ===================================
583 09:59:29.595527 ===================================
584 09:59:29.598711 data_rate = 1600
585 09:59:29.601488 CKR = 1
586 09:59:29.601612 DQ_P2S_RATIO = 8
587 09:59:29.605324 ===================================
588 09:59:29.608162 CA_P2S_RATIO = 8
589 09:59:29.611704 DQ_CA_OPEN = 0
590 09:59:29.614901 DQ_SEMI_OPEN = 0
591 09:59:29.618155 CA_SEMI_OPEN = 0
592 09:59:29.621443 CA_FULL_RATE = 0
593 09:59:29.621555 DQ_CKDIV4_EN = 1
594 09:59:29.624950 CA_CKDIV4_EN = 1
595 09:59:29.628232 CA_PREDIV_EN = 0
596 09:59:29.631348 PH8_DLY = 0
597 09:59:29.634693 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
598 09:59:29.638011 DQ_AAMCK_DIV = 4
599 09:59:29.638121 CA_AAMCK_DIV = 4
600 09:59:29.641670 CA_ADMCK_DIV = 4
601 09:59:29.645006 DQ_TRACK_CA_EN = 0
602 09:59:29.648461 CA_PICK = 800
603 09:59:29.651927 CA_MCKIO = 800
604 09:59:29.655414 MCKIO_SEMI = 0
605 09:59:29.655530 PLL_FREQ = 3068
606 09:59:29.659333 DQ_UI_PI_RATIO = 32
607 09:59:29.663167 CA_UI_PI_RATIO = 0
608 09:59:29.667284 ===================================
609 09:59:29.670852 ===================================
610 09:59:29.670975 memory_type:LPDDR4
611 09:59:29.674436 GP_NUM : 10
612 09:59:29.674540 SRAM_EN : 1
613 09:59:29.678671 MD32_EN : 0
614 09:59:29.682013 ===================================
615 09:59:29.682169 [ANA_INIT] >>>>>>>>>>>>>>
616 09:59:29.685549 <<<<<< [CONFIGURE PHASE]: ANA_TX
617 09:59:29.689879 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
618 09:59:29.693133 ===================================
619 09:59:29.696614 data_rate = 1600,PCW = 0X7600
620 09:59:29.699962 ===================================
621 09:59:29.702606 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
622 09:59:29.706178 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
623 09:59:29.713036 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
624 09:59:29.716272 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
625 09:59:29.719353 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
626 09:59:29.726465 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
627 09:59:29.726606 [ANA_INIT] flow start
628 09:59:29.729723 [ANA_INIT] PLL >>>>>>>>
629 09:59:29.729830 [ANA_INIT] PLL <<<<<<<<
630 09:59:29.732976 [ANA_INIT] MIDPI >>>>>>>>
631 09:59:29.736726 [ANA_INIT] MIDPI <<<<<<<<
632 09:59:29.739715 [ANA_INIT] DLL >>>>>>>>
633 09:59:29.739826 [ANA_INIT] flow end
634 09:59:29.743052 ============ LP4 DIFF to SE enter ============
635 09:59:29.749783 ============ LP4 DIFF to SE exit ============
636 09:59:29.749916 [ANA_INIT] <<<<<<<<<<<<<
637 09:59:29.753589 [Flow] Enable top DCM control >>>>>
638 09:59:29.756620 [Flow] Enable top DCM control <<<<<
639 09:59:29.759969 Enable DLL master slave shuffle
640 09:59:29.766654 ==============================================================
641 09:59:29.766789 Gating Mode config
642 09:59:29.773724 ==============================================================
643 09:59:29.776551 Config description:
644 09:59:29.783762 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
645 09:59:29.790527 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
646 09:59:29.796467 SELPH_MODE 0: By rank 1: By Phase
647 09:59:29.803377 ==============================================================
648 09:59:29.803520 GAT_TRACK_EN = 1
649 09:59:29.806596 RX_GATING_MODE = 2
650 09:59:29.810132 RX_GATING_TRACK_MODE = 2
651 09:59:29.813386 SELPH_MODE = 1
652 09:59:29.816938 PICG_EARLY_EN = 1
653 09:59:29.820032 VALID_LAT_VALUE = 1
654 09:59:29.826981 ==============================================================
655 09:59:29.829548 Enter into Gating configuration >>>>
656 09:59:29.833372 Exit from Gating configuration <<<<
657 09:59:29.836711 Enter into DVFS_PRE_config >>>>>
658 09:59:29.846729 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
659 09:59:29.849847 Exit from DVFS_PRE_config <<<<<
660 09:59:29.853411 Enter into PICG configuration >>>>
661 09:59:29.856659 Exit from PICG configuration <<<<
662 09:59:29.859667 [RX_INPUT] configuration >>>>>
663 09:59:29.859776 [RX_INPUT] configuration <<<<<
664 09:59:29.866930 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
665 09:59:29.872963 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
666 09:59:29.876680 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
667 09:59:29.883324 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
668 09:59:29.890618 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
669 09:59:29.896483 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
670 09:59:29.899987 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
671 09:59:29.903469 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
672 09:59:29.910392 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
673 09:59:29.913643 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
674 09:59:29.916723 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
675 09:59:29.920421 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
676 09:59:29.923974 ===================================
677 09:59:29.927101 LPDDR4 DRAM CONFIGURATION
678 09:59:29.930244 ===================================
679 09:59:29.933409 EX_ROW_EN[0] = 0x0
680 09:59:29.933545 EX_ROW_EN[1] = 0x0
681 09:59:29.936932 LP4Y_EN = 0x0
682 09:59:29.937037 WORK_FSP = 0x0
683 09:59:29.940838 WL = 0x2
684 09:59:29.940977 RL = 0x2
685 09:59:29.943869 BL = 0x2
686 09:59:29.943970 RPST = 0x0
687 09:59:29.947021 RD_PRE = 0x0
688 09:59:29.947122 WR_PRE = 0x1
689 09:59:29.950244 WR_PST = 0x0
690 09:59:29.950349 DBI_WR = 0x0
691 09:59:29.953522 DBI_RD = 0x0
692 09:59:29.953648 OTF = 0x1
693 09:59:29.956939 ===================================
694 09:59:29.960304 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
695 09:59:29.967227 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
696 09:59:29.970015 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
697 09:59:29.973560 ===================================
698 09:59:29.976886 LPDDR4 DRAM CONFIGURATION
699 09:59:29.980204 ===================================
700 09:59:29.980329 EX_ROW_EN[0] = 0x10
701 09:59:29.983869 EX_ROW_EN[1] = 0x0
702 09:59:29.986801 LP4Y_EN = 0x0
703 09:59:29.986956 WORK_FSP = 0x0
704 09:59:29.990384 WL = 0x2
705 09:59:29.990531 RL = 0x2
706 09:59:29.993640 BL = 0x2
707 09:59:29.993771 RPST = 0x0
708 09:59:29.996777 RD_PRE = 0x0
709 09:59:29.996923 WR_PRE = 0x1
710 09:59:30.000401 WR_PST = 0x0
711 09:59:30.000542 DBI_WR = 0x0
712 09:59:30.003699 DBI_RD = 0x0
713 09:59:30.003831 OTF = 0x1
714 09:59:30.006647 ===================================
715 09:59:30.013689 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
716 09:59:30.017448 nWR fixed to 40
717 09:59:30.020890 [ModeRegInit_LP4] CH0 RK0
718 09:59:30.021039 [ModeRegInit_LP4] CH0 RK1
719 09:59:30.024273 [ModeRegInit_LP4] CH1 RK0
720 09:59:30.027575 [ModeRegInit_LP4] CH1 RK1
721 09:59:30.027721 match AC timing 13
722 09:59:30.034167 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
723 09:59:30.037971 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
724 09:59:30.041061 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
725 09:59:30.048302 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
726 09:59:30.051150 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
727 09:59:30.051299 [EMI DOE] emi_dcm 0
728 09:59:30.057505 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
729 09:59:30.057657 ==
730 09:59:30.061498 Dram Type= 6, Freq= 0, CH_0, rank 0
731 09:59:30.064331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
732 09:59:30.064464 ==
733 09:59:30.071130 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
734 09:59:30.077337 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
735 09:59:30.084884 [CA 0] Center 36 (6~67) winsize 62
736 09:59:30.088603 [CA 1] Center 36 (6~67) winsize 62
737 09:59:30.091755 [CA 2] Center 34 (4~65) winsize 62
738 09:59:30.095512 [CA 3] Center 33 (3~64) winsize 62
739 09:59:30.098263 [CA 4] Center 33 (3~63) winsize 61
740 09:59:30.101851 [CA 5] Center 32 (3~62) winsize 60
741 09:59:30.101969
742 09:59:30.104956 [CmdBusTrainingLP45] Vref(ca) range 1: 32
743 09:59:30.105066
744 09:59:30.108519 [CATrainingPosCal] consider 1 rank data
745 09:59:30.111992 u2DelayCellTimex100 = 270/100 ps
746 09:59:30.115312 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
747 09:59:30.118326 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
748 09:59:30.125951 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
749 09:59:30.128720 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
750 09:59:30.132181 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
751 09:59:30.135640 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
752 09:59:30.135759
753 09:59:30.138948 CA PerBit enable=1, Macro0, CA PI delay=32
754 09:59:30.139067
755 09:59:30.141924 [CBTSetCACLKResult] CA Dly = 32
756 09:59:30.142038 CS Dly: 5 (0~36)
757 09:59:30.142137 ==
758 09:59:30.145358 Dram Type= 6, Freq= 0, CH_0, rank 1
759 09:59:30.152309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
760 09:59:30.152465 ==
761 09:59:30.155749 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
762 09:59:30.162281 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
763 09:59:30.171588 [CA 0] Center 36 (6~67) winsize 62
764 09:59:30.174640 [CA 1] Center 36 (6~67) winsize 62
765 09:59:30.177801 [CA 2] Center 34 (3~65) winsize 63
766 09:59:30.181351 [CA 3] Center 33 (3~64) winsize 62
767 09:59:30.184665 [CA 4] Center 32 (2~63) winsize 62
768 09:59:30.188212 [CA 5] Center 32 (2~63) winsize 62
769 09:59:30.188346
770 09:59:30.191346 [CmdBusTrainingLP45] Vref(ca) range 1: 34
771 09:59:30.191465
772 09:59:30.194923 [CATrainingPosCal] consider 2 rank data
773 09:59:30.197930 u2DelayCellTimex100 = 270/100 ps
774 09:59:30.201717 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
775 09:59:30.204670 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
776 09:59:30.211141 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
777 09:59:30.214615 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
778 09:59:30.218247 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
779 09:59:30.221242 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
780 09:59:30.221401
781 09:59:30.224580 CA PerBit enable=1, Macro0, CA PI delay=32
782 09:59:30.224701
783 09:59:30.228246 [CBTSetCACLKResult] CA Dly = 32
784 09:59:30.228377 CS Dly: 5 (0~37)
785 09:59:30.228463
786 09:59:30.231852 ----->DramcWriteLeveling(PI) begin...
787 09:59:30.231963 ==
788 09:59:30.235558 Dram Type= 6, Freq= 0, CH_0, rank 0
789 09:59:30.239640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
790 09:59:30.242706 ==
791 09:59:30.242829 Write leveling (Byte 0): 34 => 34
792 09:59:30.246582 Write leveling (Byte 1): 29 => 29
793 09:59:30.250665 DramcWriteLeveling(PI) end<-----
794 09:59:30.250827
795 09:59:30.250932 ==
796 09:59:30.253225 Dram Type= 6, Freq= 0, CH_0, rank 0
797 09:59:30.256820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
798 09:59:30.256977 ==
799 09:59:30.260066 [Gating] SW mode calibration
800 09:59:30.267539 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
801 09:59:30.273884 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
802 09:59:30.277616 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
803 09:59:30.281061 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
804 09:59:30.287219 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
805 09:59:30.290588 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
806 09:59:30.294111 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 09:59:30.297366 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 09:59:30.304271 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 09:59:30.308020 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 09:59:30.310840 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 09:59:30.317522 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 09:59:30.320595 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 09:59:30.324114 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
814 09:59:30.331384 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
815 09:59:30.334689 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 09:59:30.337383 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 09:59:30.344037 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 09:59:30.347483 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 09:59:30.350921 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
820 09:59:30.357415 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
821 09:59:30.360771 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 09:59:30.364167 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 09:59:30.370927 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 09:59:30.374466 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 09:59:30.377582 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 09:59:30.380745 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 09:59:30.387843 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 09:59:30.390852 0 9 8 | B1->B0 | 2323 2c2b | 0 1 | (0 0) (1 1)
829 09:59:30.394415 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
830 09:59:30.401073 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
831 09:59:30.404349 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
832 09:59:30.407903 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
833 09:59:30.414441 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
834 09:59:30.417699 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
835 09:59:30.421097 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (1 0)
836 09:59:30.427482 0 10 8 | B1->B0 | 2f2f 2626 | 1 0 | (1 0) (0 0)
837 09:59:30.431138 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
838 09:59:30.434444 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 09:59:30.441065 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 09:59:30.444481 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
841 09:59:30.447910 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
842 09:59:30.451290 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 09:59:30.458267 0 11 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
844 09:59:30.461118 0 11 8 | B1->B0 | 2e2e 403f | 0 1 | (0 0) (0 0)
845 09:59:30.464580 0 11 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
846 09:59:30.471137 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
847 09:59:30.474435 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
848 09:59:30.478278 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
849 09:59:30.484732 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
850 09:59:30.487796 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
851 09:59:30.491152 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
852 09:59:30.498457 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
853 09:59:30.501415 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
854 09:59:30.504831 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
855 09:59:30.511395 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
856 09:59:30.514830 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
857 09:59:30.517806 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
858 09:59:30.524657 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
859 09:59:30.527867 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
860 09:59:30.531256 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
861 09:59:30.538087 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
862 09:59:30.541394 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
863 09:59:30.544842 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
864 09:59:30.547907 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
865 09:59:30.554600 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
866 09:59:30.557945 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
867 09:59:30.561552 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
868 09:59:30.568301 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
869 09:59:30.571152 Total UI for P1: 0, mck2ui 16
870 09:59:30.574537 best dqsien dly found for B0: ( 0, 14, 4)
871 09:59:30.577944 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
872 09:59:30.581306 Total UI for P1: 0, mck2ui 16
873 09:59:30.584541 best dqsien dly found for B1: ( 0, 14, 8)
874 09:59:30.588715 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
875 09:59:30.591997 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
876 09:59:30.592145
877 09:59:30.595470 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
878 09:59:30.598734 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
879 09:59:30.601928 [Gating] SW calibration Done
880 09:59:30.602044 ==
881 09:59:30.605481 Dram Type= 6, Freq= 0, CH_0, rank 0
882 09:59:30.608474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
883 09:59:30.608618 ==
884 09:59:30.612389 RX Vref Scan: 0
885 09:59:30.612553
886 09:59:30.612655 RX Vref 0 -> 0, step: 1
887 09:59:30.612750
888 09:59:30.615375 RX Delay -130 -> 252, step: 16
889 09:59:30.622329 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
890 09:59:30.625510 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
891 09:59:30.628980 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
892 09:59:30.631986 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
893 09:59:30.635868 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
894 09:59:30.638644 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
895 09:59:30.645783 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
896 09:59:30.649177 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
897 09:59:30.652030 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
898 09:59:30.655857 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
899 09:59:30.658672 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
900 09:59:30.665347 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
901 09:59:30.668666 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
902 09:59:30.672379 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
903 09:59:30.676014 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
904 09:59:30.678583 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
905 09:59:30.682319 ==
906 09:59:30.685261 Dram Type= 6, Freq= 0, CH_0, rank 0
907 09:59:30.688864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
908 09:59:30.689015 ==
909 09:59:30.689121 DQS Delay:
910 09:59:30.692227 DQS0 = 0, DQS1 = 0
911 09:59:30.692375 DQM Delay:
912 09:59:30.695539 DQM0 = 88, DQM1 = 82
913 09:59:30.695681 DQ Delay:
914 09:59:30.699192 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
915 09:59:30.702147 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
916 09:59:30.705450 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
917 09:59:30.709157 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
918 09:59:30.709308
919 09:59:30.709411
920 09:59:30.709504 ==
921 09:59:30.712630 Dram Type= 6, Freq= 0, CH_0, rank 0
922 09:59:30.715857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
923 09:59:30.716001 ==
924 09:59:30.716101
925 09:59:30.716194
926 09:59:30.719705 TX Vref Scan disable
927 09:59:30.722726 == TX Byte 0 ==
928 09:59:30.726006 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
929 09:59:30.729477 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
930 09:59:30.729643 == TX Byte 1 ==
931 09:59:30.735598 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
932 09:59:30.739459 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
933 09:59:30.739614 ==
934 09:59:30.742471 Dram Type= 6, Freq= 0, CH_0, rank 0
935 09:59:30.746018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
936 09:59:30.746158 ==
937 09:59:30.760868 TX Vref=22, minBit 8, minWin=27, winSum=448
938 09:59:30.763924 TX Vref=24, minBit 8, minWin=27, winSum=450
939 09:59:30.767201 TX Vref=26, minBit 4, minWin=28, winSum=454
940 09:59:30.770675 TX Vref=28, minBit 5, minWin=28, winSum=457
941 09:59:30.773970 TX Vref=30, minBit 5, minWin=28, winSum=458
942 09:59:30.777117 TX Vref=32, minBit 10, minWin=27, winSum=451
943 09:59:30.783862 [TxChooseVref] Worse bit 5, Min win 28, Win sum 458, Final Vref 30
944 09:59:30.784024
945 09:59:30.787468 Final TX Range 1 Vref 30
946 09:59:30.787592
947 09:59:30.787660 ==
948 09:59:30.790418 Dram Type= 6, Freq= 0, CH_0, rank 0
949 09:59:30.793991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
950 09:59:30.794116 ==
951 09:59:30.794200
952 09:59:30.797463
953 09:59:30.797600 TX Vref Scan disable
954 09:59:30.800518 == TX Byte 0 ==
955 09:59:30.804700 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
956 09:59:30.807388 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
957 09:59:30.810536 == TX Byte 1 ==
958 09:59:30.813630 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
959 09:59:30.817289 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
960 09:59:30.820541
961 09:59:30.820659 [DATLAT]
962 09:59:30.820729 Freq=800, CH0 RK0
963 09:59:30.820791
964 09:59:30.823978 DATLAT Default: 0xa
965 09:59:30.824075 0, 0xFFFF, sum = 0
966 09:59:30.827344 1, 0xFFFF, sum = 0
967 09:59:30.827495 2, 0xFFFF, sum = 0
968 09:59:30.830745 3, 0xFFFF, sum = 0
969 09:59:30.830875 4, 0xFFFF, sum = 0
970 09:59:30.833872 5, 0xFFFF, sum = 0
971 09:59:30.834004 6, 0xFFFF, sum = 0
972 09:59:30.837430 7, 0xFFFF, sum = 0
973 09:59:30.840575 8, 0xFFFF, sum = 0
974 09:59:30.840716 9, 0x0, sum = 1
975 09:59:30.840819 10, 0x0, sum = 2
976 09:59:30.843957 11, 0x0, sum = 3
977 09:59:30.844097 12, 0x0, sum = 4
978 09:59:30.847010 best_step = 10
979 09:59:30.847139
980 09:59:30.847238 ==
981 09:59:30.851168 Dram Type= 6, Freq= 0, CH_0, rank 0
982 09:59:30.853816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
983 09:59:30.853952 ==
984 09:59:30.857046 RX Vref Scan: 1
985 09:59:30.857172
986 09:59:30.857271 Set Vref Range= 32 -> 127
987 09:59:30.857365
988 09:59:30.860848 RX Vref 32 -> 127, step: 1
989 09:59:30.860979
990 09:59:30.863963 RX Delay -79 -> 252, step: 8
991 09:59:30.864093
992 09:59:30.867373 Set Vref, RX VrefLevel [Byte0]: 32
993 09:59:30.870762 [Byte1]: 32
994 09:59:30.870913
995 09:59:30.874043 Set Vref, RX VrefLevel [Byte0]: 33
996 09:59:30.877305 [Byte1]: 33
997 09:59:30.880566
998 09:59:30.880688 Set Vref, RX VrefLevel [Byte0]: 34
999 09:59:30.884108 [Byte1]: 34
1000 09:59:30.888501
1001 09:59:30.888637 Set Vref, RX VrefLevel [Byte0]: 35
1002 09:59:30.891700 [Byte1]: 35
1003 09:59:30.896169
1004 09:59:30.896355 Set Vref, RX VrefLevel [Byte0]: 36
1005 09:59:30.899182 [Byte1]: 36
1006 09:59:30.903420
1007 09:59:30.903593 Set Vref, RX VrefLevel [Byte0]: 37
1008 09:59:30.906606 [Byte1]: 37
1009 09:59:30.911473
1010 09:59:30.911653 Set Vref, RX VrefLevel [Byte0]: 38
1011 09:59:30.914872 [Byte1]: 38
1012 09:59:30.918570
1013 09:59:30.918735 Set Vref, RX VrefLevel [Byte0]: 39
1014 09:59:30.922030 [Byte1]: 39
1015 09:59:30.926452
1016 09:59:30.926623 Set Vref, RX VrefLevel [Byte0]: 40
1017 09:59:30.929674 [Byte1]: 40
1018 09:59:30.933962
1019 09:59:30.934129 Set Vref, RX VrefLevel [Byte0]: 41
1020 09:59:30.937554 [Byte1]: 41
1021 09:59:30.941135
1022 09:59:30.941279 Set Vref, RX VrefLevel [Byte0]: 42
1023 09:59:30.944953 [Byte1]: 42
1024 09:59:30.948659
1025 09:59:30.948813 Set Vref, RX VrefLevel [Byte0]: 43
1026 09:59:30.951848 [Byte1]: 43
1027 09:59:30.956738
1028 09:59:30.956895 Set Vref, RX VrefLevel [Byte0]: 44
1029 09:59:30.960430 [Byte1]: 44
1030 09:59:30.963715
1031 09:59:30.963864 Set Vref, RX VrefLevel [Byte0]: 45
1032 09:59:30.967141 [Byte1]: 45
1033 09:59:30.971619
1034 09:59:30.971777 Set Vref, RX VrefLevel [Byte0]: 46
1035 09:59:30.974474 [Byte1]: 46
1036 09:59:30.979496
1037 09:59:30.979662 Set Vref, RX VrefLevel [Byte0]: 47
1038 09:59:30.982466 [Byte1]: 47
1039 09:59:30.986823
1040 09:59:30.986976 Set Vref, RX VrefLevel [Byte0]: 48
1041 09:59:30.990057 [Byte1]: 48
1042 09:59:30.994136
1043 09:59:30.994273 Set Vref, RX VrefLevel [Byte0]: 49
1044 09:59:30.997348 [Byte1]: 49
1045 09:59:31.001609
1046 09:59:31.001763 Set Vref, RX VrefLevel [Byte0]: 50
1047 09:59:31.004571 [Byte1]: 50
1048 09:59:31.009150
1049 09:59:31.009311 Set Vref, RX VrefLevel [Byte0]: 51
1050 09:59:31.012475 [Byte1]: 51
1051 09:59:31.016829
1052 09:59:31.016998 Set Vref, RX VrefLevel [Byte0]: 52
1053 09:59:31.020064 [Byte1]: 52
1054 09:59:31.024117
1055 09:59:31.024266 Set Vref, RX VrefLevel [Byte0]: 53
1056 09:59:31.027642 [Byte1]: 53
1057 09:59:31.031982
1058 09:59:31.032134 Set Vref, RX VrefLevel [Byte0]: 54
1059 09:59:31.035105 [Byte1]: 54
1060 09:59:31.039281
1061 09:59:31.039434 Set Vref, RX VrefLevel [Byte0]: 55
1062 09:59:31.042686 [Byte1]: 55
1063 09:59:31.047399
1064 09:59:31.047580 Set Vref, RX VrefLevel [Byte0]: 56
1065 09:59:31.049829 [Byte1]: 56
1066 09:59:31.054205
1067 09:59:31.054341 Set Vref, RX VrefLevel [Byte0]: 57
1068 09:59:31.057544 [Byte1]: 57
1069 09:59:31.061922
1070 09:59:31.062051 Set Vref, RX VrefLevel [Byte0]: 58
1071 09:59:31.065512 [Byte1]: 58
1072 09:59:31.069684
1073 09:59:31.069816 Set Vref, RX VrefLevel [Byte0]: 59
1074 09:59:31.072576 [Byte1]: 59
1075 09:59:31.076890
1076 09:59:31.077027 Set Vref, RX VrefLevel [Byte0]: 60
1077 09:59:31.080196 [Byte1]: 60
1078 09:59:31.084534
1079 09:59:31.084673 Set Vref, RX VrefLevel [Byte0]: 61
1080 09:59:31.087697 [Byte1]: 61
1081 09:59:31.092375
1082 09:59:31.092517 Set Vref, RX VrefLevel [Byte0]: 62
1083 09:59:31.095740 [Byte1]: 62
1084 09:59:31.099748
1085 09:59:31.099879 Set Vref, RX VrefLevel [Byte0]: 63
1086 09:59:31.103154 [Byte1]: 63
1087 09:59:31.107400
1088 09:59:31.107532 Set Vref, RX VrefLevel [Byte0]: 64
1089 09:59:31.110495 [Byte1]: 64
1090 09:59:31.115236
1091 09:59:31.115387 Set Vref, RX VrefLevel [Byte0]: 65
1092 09:59:31.118066 [Byte1]: 65
1093 09:59:31.122823
1094 09:59:31.122961 Set Vref, RX VrefLevel [Byte0]: 66
1095 09:59:31.125550 [Byte1]: 66
1096 09:59:31.129810
1097 09:59:31.129990 Set Vref, RX VrefLevel [Byte0]: 67
1098 09:59:31.133487 [Byte1]: 67
1099 09:59:31.137421
1100 09:59:31.137561 Set Vref, RX VrefLevel [Byte0]: 68
1101 09:59:31.141413 [Byte1]: 68
1102 09:59:31.145241
1103 09:59:31.145379 Set Vref, RX VrefLevel [Byte0]: 69
1104 09:59:31.148130 [Byte1]: 69
1105 09:59:31.152940
1106 09:59:31.153080 Set Vref, RX VrefLevel [Byte0]: 70
1107 09:59:31.155997 [Byte1]: 70
1108 09:59:31.159956
1109 09:59:31.160085 Set Vref, RX VrefLevel [Byte0]: 71
1110 09:59:31.163305 [Byte1]: 71
1111 09:59:31.167734
1112 09:59:31.167855 Set Vref, RX VrefLevel [Byte0]: 72
1113 09:59:31.170777 [Byte1]: 72
1114 09:59:31.175310
1115 09:59:31.175430 Set Vref, RX VrefLevel [Byte0]: 73
1116 09:59:31.178475 [Byte1]: 73
1117 09:59:31.182582
1118 09:59:31.182704 Set Vref, RX VrefLevel [Byte0]: 74
1119 09:59:31.189055 [Byte1]: 74
1120 09:59:31.189186
1121 09:59:31.192291 Set Vref, RX VrefLevel [Byte0]: 75
1122 09:59:31.195763 [Byte1]: 75
1123 09:59:31.195877
1124 09:59:31.199407 Set Vref, RX VrefLevel [Byte0]: 76
1125 09:59:31.202353 [Byte1]: 76
1126 09:59:31.202460
1127 09:59:31.205976 Set Vref, RX VrefLevel [Byte0]: 77
1128 09:59:31.209166 [Byte1]: 77
1129 09:59:31.213216
1130 09:59:31.213352 Set Vref, RX VrefLevel [Byte0]: 78
1131 09:59:31.216103 [Byte1]: 78
1132 09:59:31.220698
1133 09:59:31.220817 Set Vref, RX VrefLevel [Byte0]: 79
1134 09:59:31.223758 [Byte1]: 79
1135 09:59:31.228245
1136 09:59:31.228373 Set Vref, RX VrefLevel [Byte0]: 80
1137 09:59:31.231697 [Byte1]: 80
1138 09:59:31.235478
1139 09:59:31.235596 Final RX Vref Byte 0 = 55 to rank0
1140 09:59:31.238765 Final RX Vref Byte 1 = 60 to rank0
1141 09:59:31.242079 Final RX Vref Byte 0 = 55 to rank1
1142 09:59:31.245322 Final RX Vref Byte 1 = 60 to rank1==
1143 09:59:31.249506 Dram Type= 6, Freq= 0, CH_0, rank 0
1144 09:59:31.255148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1145 09:59:31.255284 ==
1146 09:59:31.255352 DQS Delay:
1147 09:59:31.259061 DQS0 = 0, DQS1 = 0
1148 09:59:31.259174 DQM Delay:
1149 09:59:31.259240 DQM0 = 91, DQM1 = 85
1150 09:59:31.262184 DQ Delay:
1151 09:59:31.265475 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1152 09:59:31.268841 DQ4 =92, DQ5 =80, DQ6 =96, DQ7 =100
1153 09:59:31.272031 DQ8 =76, DQ9 =76, DQ10 =84, DQ11 =76
1154 09:59:31.275183 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =92
1155 09:59:31.275295
1156 09:59:31.275362
1157 09:59:31.282730 [DQSOSCAuto] RK0, (LSB)MR18= 0x4c42, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 390 ps
1158 09:59:31.285217 CH0 RK0: MR19=606, MR18=4C42
1159 09:59:31.292132 CH0_RK0: MR19=0x606, MR18=0x4C42, DQSOSC=390, MR23=63, INC=97, DEC=64
1160 09:59:31.292283
1161 09:59:31.295605 ----->DramcWriteLeveling(PI) begin...
1162 09:59:31.295723 ==
1163 09:59:31.298936 Dram Type= 6, Freq= 0, CH_0, rank 1
1164 09:59:31.302098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1165 09:59:31.302224 ==
1166 09:59:31.305674 Write leveling (Byte 0): 33 => 33
1167 09:59:31.349338 Write leveling (Byte 1): 31 => 31
1168 09:59:31.349566 DramcWriteLeveling(PI) end<-----
1169 09:59:31.349702
1170 09:59:31.349793 ==
1171 09:59:31.350114 Dram Type= 6, Freq= 0, CH_0, rank 1
1172 09:59:31.350261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1173 09:59:31.350353 ==
1174 09:59:31.350442 [Gating] SW mode calibration
1175 09:59:31.350548 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1176 09:59:31.350671 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1177 09:59:31.350777 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1178 09:59:31.351105 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1179 09:59:31.351451 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1180 09:59:31.362366 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 09:59:31.362567 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 09:59:31.362671 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 09:59:31.365675 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 09:59:31.369200 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 09:59:31.375554 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 09:59:31.378904 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 09:59:31.382319 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 09:59:31.389166 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 09:59:31.391975 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 09:59:31.395347 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 09:59:31.401916 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 09:59:31.405392 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 09:59:31.408517 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 09:59:31.411993 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1195 09:59:31.418714 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1196 09:59:31.422116 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1197 09:59:31.425150 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 09:59:31.432104 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 09:59:31.435086 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 09:59:31.438821 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 09:59:31.445533 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 09:59:31.448431 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 09:59:31.452389 0 9 8 | B1->B0 | 3030 2b2b | 1 1 | (1 1) (1 1)
1204 09:59:31.458933 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1205 09:59:31.462158 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1206 09:59:31.466109 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1207 09:59:31.472186 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1208 09:59:31.475890 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1209 09:59:31.479079 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1210 09:59:31.483184 0 10 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1211 09:59:31.487357 0 10 8 | B1->B0 | 2828 2626 | 0 0 | (0 1) (0 0)
1212 09:59:31.494603 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1213 09:59:31.497704 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 09:59:31.501171 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 09:59:31.504631 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 09:59:31.511762 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 09:59:31.514643 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 09:59:31.517990 0 11 4 | B1->B0 | 2626 2727 | 1 1 | (0 0) (0 0)
1219 09:59:31.525307 0 11 8 | B1->B0 | 3b3b 3535 | 0 1 | (0 0) (0 0)
1220 09:59:31.528054 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1221 09:59:31.531681 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1222 09:59:31.538136 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1223 09:59:31.541200 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1224 09:59:31.544578 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1225 09:59:31.551455 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1226 09:59:31.554942 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1227 09:59:31.558203 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1228 09:59:31.561302 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1229 09:59:31.568319 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1230 09:59:31.571366 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1231 09:59:31.574702 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1232 09:59:31.581610 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1233 09:59:31.584521 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1234 09:59:31.587843 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1235 09:59:31.594710 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1236 09:59:31.598323 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1237 09:59:31.601378 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1238 09:59:31.608335 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1239 09:59:31.611478 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1240 09:59:31.614744 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1241 09:59:31.621557 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1242 09:59:31.624966 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1243 09:59:31.628302 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1244 09:59:31.635110 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1245 09:59:31.635241 Total UI for P1: 0, mck2ui 16
1246 09:59:31.638685 best dqsien dly found for B0: ( 0, 14, 6)
1247 09:59:31.641786 Total UI for P1: 0, mck2ui 16
1248 09:59:31.644710 best dqsien dly found for B1: ( 0, 14, 8)
1249 09:59:31.648312 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1250 09:59:31.655370 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1251 09:59:31.655494
1252 09:59:31.658120 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1253 09:59:31.661474 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1254 09:59:31.665061 [Gating] SW calibration Done
1255 09:59:31.665160 ==
1256 09:59:31.668552 Dram Type= 6, Freq= 0, CH_0, rank 1
1257 09:59:31.671664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1258 09:59:31.671766 ==
1259 09:59:31.671833 RX Vref Scan: 0
1260 09:59:31.671894
1261 09:59:31.674906 RX Vref 0 -> 0, step: 1
1262 09:59:31.674999
1263 09:59:31.678327 RX Delay -130 -> 252, step: 16
1264 09:59:31.681993 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1265 09:59:31.684822 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1266 09:59:31.691703 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1267 09:59:31.695284 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1268 09:59:31.698823 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1269 09:59:31.701855 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1270 09:59:31.705169 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1271 09:59:31.708738 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1272 09:59:31.715176 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1273 09:59:31.718336 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1274 09:59:31.722018 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1275 09:59:31.725316 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1276 09:59:31.728457 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1277 09:59:31.734960 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1278 09:59:31.738476 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1279 09:59:31.741857 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1280 09:59:31.741962 ==
1281 09:59:31.745489 Dram Type= 6, Freq= 0, CH_0, rank 1
1282 09:59:31.748505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1283 09:59:31.751893 ==
1284 09:59:31.752000 DQS Delay:
1285 09:59:31.752069 DQS0 = 0, DQS1 = 0
1286 09:59:31.755355 DQM Delay:
1287 09:59:31.755449 DQM0 = 91, DQM1 = 83
1288 09:59:31.758936 DQ Delay:
1289 09:59:31.759031 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
1290 09:59:31.762364 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =101
1291 09:59:31.765104 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
1292 09:59:31.768613 DQ12 =85, DQ13 =93, DQ14 =93, DQ15 =85
1293 09:59:31.768720
1294 09:59:31.772249
1295 09:59:31.772344 ==
1296 09:59:31.775250 Dram Type= 6, Freq= 0, CH_0, rank 1
1297 09:59:31.778536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1298 09:59:31.778638 ==
1299 09:59:31.778708
1300 09:59:31.778768
1301 09:59:31.781976 TX Vref Scan disable
1302 09:59:31.782070 == TX Byte 0 ==
1303 09:59:31.788671 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1304 09:59:31.792139 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1305 09:59:31.792250 == TX Byte 1 ==
1306 09:59:31.798802 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1307 09:59:31.802046 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1308 09:59:31.802157 ==
1309 09:59:31.805757 Dram Type= 6, Freq= 0, CH_0, rank 1
1310 09:59:31.808536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1311 09:59:31.808663 ==
1312 09:59:31.822279 TX Vref=22, minBit 10, minWin=27, winSum=449
1313 09:59:31.825656 TX Vref=24, minBit 13, minWin=27, winSum=452
1314 09:59:31.829028 TX Vref=26, minBit 4, minWin=28, winSum=456
1315 09:59:31.832536 TX Vref=28, minBit 4, minWin=28, winSum=454
1316 09:59:31.835489 TX Vref=30, minBit 4, minWin=28, winSum=459
1317 09:59:31.839322 TX Vref=32, minBit 4, minWin=28, winSum=457
1318 09:59:31.846060 [TxChooseVref] Worse bit 4, Min win 28, Win sum 459, Final Vref 30
1319 09:59:31.846191
1320 09:59:31.848874 Final TX Range 1 Vref 30
1321 09:59:31.848969
1322 09:59:31.849035 ==
1323 09:59:31.852244 Dram Type= 6, Freq= 0, CH_0, rank 1
1324 09:59:31.855941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1325 09:59:31.856059 ==
1326 09:59:31.856128
1327 09:59:31.856189
1328 09:59:31.859167 TX Vref Scan disable
1329 09:59:31.862615 == TX Byte 0 ==
1330 09:59:31.865994 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1331 09:59:31.869237 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1332 09:59:31.872699 == TX Byte 1 ==
1333 09:59:31.876073 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1334 09:59:31.879622 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1335 09:59:31.879737
1336 09:59:31.883311 [DATLAT]
1337 09:59:31.883414 Freq=800, CH0 RK1
1338 09:59:31.883482
1339 09:59:31.886097 DATLAT Default: 0xa
1340 09:59:31.886185 0, 0xFFFF, sum = 0
1341 09:59:31.889397 1, 0xFFFF, sum = 0
1342 09:59:31.889491 2, 0xFFFF, sum = 0
1343 09:59:31.892716 3, 0xFFFF, sum = 0
1344 09:59:31.892814 4, 0xFFFF, sum = 0
1345 09:59:31.896463 5, 0xFFFF, sum = 0
1346 09:59:31.896563 6, 0xFFFF, sum = 0
1347 09:59:31.899512 7, 0xFFFF, sum = 0
1348 09:59:31.899612 8, 0xFFFF, sum = 0
1349 09:59:31.903024 9, 0x0, sum = 1
1350 09:59:31.903125 10, 0x0, sum = 2
1351 09:59:31.906571 11, 0x0, sum = 3
1352 09:59:31.906670 12, 0x0, sum = 4
1353 09:59:31.909742 best_step = 10
1354 09:59:31.909834
1355 09:59:31.909900 ==
1356 09:59:31.912923 Dram Type= 6, Freq= 0, CH_0, rank 1
1357 09:59:31.916612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1358 09:59:31.916718 ==
1359 09:59:31.919315 RX Vref Scan: 0
1360 09:59:31.919404
1361 09:59:31.919469 RX Vref 0 -> 0, step: 1
1362 09:59:31.919529
1363 09:59:31.922921 RX Delay -79 -> 252, step: 8
1364 09:59:31.926354 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1365 09:59:31.933103 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1366 09:59:31.936640 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1367 09:59:31.939552 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1368 09:59:31.942894 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224
1369 09:59:31.946285 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1370 09:59:31.952883 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1371 09:59:31.956047 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1372 09:59:31.959354 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
1373 09:59:31.962928 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1374 09:59:31.966374 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1375 09:59:31.973034 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1376 09:59:31.976277 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1377 09:59:31.979797 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
1378 09:59:31.983091 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1379 09:59:31.986485 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1380 09:59:31.989672 ==
1381 09:59:31.992866 Dram Type= 6, Freq= 0, CH_0, rank 1
1382 09:59:31.996039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1383 09:59:31.996168 ==
1384 09:59:31.996241 DQS Delay:
1385 09:59:31.999280 DQS0 = 0, DQS1 = 0
1386 09:59:31.999393 DQM Delay:
1387 09:59:32.003344 DQM0 = 92, DQM1 = 82
1388 09:59:32.003470 DQ Delay:
1389 09:59:32.006201 DQ0 =92, DQ1 =92, DQ2 =88, DQ3 =88
1390 09:59:32.009398 DQ4 =96, DQ5 =80, DQ6 =100, DQ7 =100
1391 09:59:32.012916 DQ8 =72, DQ9 =68, DQ10 =84, DQ11 =76
1392 09:59:32.016164 DQ12 =84, DQ13 =92, DQ14 =92, DQ15 =88
1393 09:59:32.016276
1394 09:59:32.016341
1395 09:59:32.023074 [DQSOSCAuto] RK1, (LSB)MR18= 0x4011, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
1396 09:59:32.026252 CH0 RK1: MR19=606, MR18=4011
1397 09:59:32.032732 CH0_RK1: MR19=0x606, MR18=0x4011, DQSOSC=393, MR23=63, INC=95, DEC=63
1398 09:59:32.036485 [RxdqsGatingPostProcess] freq 800
1399 09:59:32.042609 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1400 09:59:32.042749 Pre-setting of DQS Precalculation
1401 09:59:32.049291 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1402 09:59:32.049433 ==
1403 09:59:32.053164 Dram Type= 6, Freq= 0, CH_1, rank 0
1404 09:59:32.056138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1405 09:59:32.056343 ==
1406 09:59:32.063194 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1407 09:59:32.069458 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1408 09:59:32.077408 [CA 0] Center 36 (6~67) winsize 62
1409 09:59:32.080532 [CA 1] Center 36 (6~67) winsize 62
1410 09:59:32.084094 [CA 2] Center 35 (5~66) winsize 62
1411 09:59:32.087509 [CA 3] Center 34 (4~65) winsize 62
1412 09:59:32.090882 [CA 4] Center 34 (4~65) winsize 62
1413 09:59:32.094268 [CA 5] Center 34 (4~65) winsize 62
1414 09:59:32.094417
1415 09:59:32.097645 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1416 09:59:32.097781
1417 09:59:32.101121 [CATrainingPosCal] consider 1 rank data
1418 09:59:32.104278 u2DelayCellTimex100 = 270/100 ps
1419 09:59:32.107805 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1420 09:59:32.110556 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1421 09:59:32.117157 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1422 09:59:32.120583 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1423 09:59:32.123688 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1424 09:59:32.127798 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1425 09:59:32.127938
1426 09:59:32.130640 CA PerBit enable=1, Macro0, CA PI delay=34
1427 09:59:32.130754
1428 09:59:32.134262 [CBTSetCACLKResult] CA Dly = 34
1429 09:59:32.134384 CS Dly: 6 (0~37)
1430 09:59:32.134465 ==
1431 09:59:32.137793 Dram Type= 6, Freq= 0, CH_1, rank 1
1432 09:59:32.144578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1433 09:59:32.144741 ==
1434 09:59:32.148391 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1435 09:59:32.155387 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1436 09:59:32.163660 [CA 0] Center 36 (6~67) winsize 62
1437 09:59:32.167500 [CA 1] Center 36 (6~67) winsize 62
1438 09:59:32.171197 [CA 2] Center 35 (4~66) winsize 63
1439 09:59:32.175429 [CA 3] Center 34 (4~65) winsize 62
1440 09:59:32.179159 [CA 4] Center 35 (4~66) winsize 63
1441 09:59:32.182261 [CA 5] Center 34 (4~65) winsize 62
1442 09:59:32.182382
1443 09:59:32.185180 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1444 09:59:32.185278
1445 09:59:32.188569 [CATrainingPosCal] consider 2 rank data
1446 09:59:32.191575 u2DelayCellTimex100 = 270/100 ps
1447 09:59:32.194838 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1448 09:59:32.198288 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1449 09:59:32.201718 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1450 09:59:32.204813 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1451 09:59:32.208474 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1452 09:59:32.211567 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1453 09:59:32.211675
1454 09:59:32.215173 CA PerBit enable=1, Macro0, CA PI delay=34
1455 09:59:32.218363
1456 09:59:32.218480 [CBTSetCACLKResult] CA Dly = 34
1457 09:59:32.222060 CS Dly: 7 (0~39)
1458 09:59:32.222164
1459 09:59:32.225474 ----->DramcWriteLeveling(PI) begin...
1460 09:59:32.225612 ==
1461 09:59:32.228697 Dram Type= 6, Freq= 0, CH_1, rank 0
1462 09:59:32.231819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1463 09:59:32.231921 ==
1464 09:59:32.235211 Write leveling (Byte 0): 26 => 26
1465 09:59:32.238375 Write leveling (Byte 1): 26 => 26
1466 09:59:32.241980 DramcWriteLeveling(PI) end<-----
1467 09:59:32.242107
1468 09:59:32.242191 ==
1469 09:59:32.245183 Dram Type= 6, Freq= 0, CH_1, rank 0
1470 09:59:32.248691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1471 09:59:32.248814 ==
1472 09:59:32.251615 [Gating] SW mode calibration
1473 09:59:32.258511 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1474 09:59:32.264982 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1475 09:59:32.268208 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1476 09:59:32.274819 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1477 09:59:32.278280 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 09:59:32.281730 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 09:59:32.285003 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 09:59:32.291885 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 09:59:32.295307 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 09:59:32.298814 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 09:59:32.305507 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 09:59:32.309006 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 09:59:32.311856 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 09:59:32.318308 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 09:59:32.321854 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 09:59:32.325082 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 09:59:32.331679 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 09:59:32.335096 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 09:59:32.338644 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1492 09:59:32.345221 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1493 09:59:32.348783 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 09:59:32.352115 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 09:59:32.358875 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 09:59:32.361937 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 09:59:32.365839 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 09:59:32.368525 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 09:59:32.375279 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 09:59:32.379177 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 1)
1501 09:59:32.382177 0 9 8 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
1502 09:59:32.389076 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1503 09:59:32.391874 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1504 09:59:32.395657 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1505 09:59:32.402228 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1506 09:59:32.405697 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1507 09:59:32.408788 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
1508 09:59:32.416019 0 10 4 | B1->B0 | 3232 2a2a | 0 0 | (0 0) (1 0)
1509 09:59:32.419092 0 10 8 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
1510 09:59:32.422167 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 09:59:32.428849 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 09:59:32.432361 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 09:59:32.435934 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 09:59:32.442272 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 09:59:32.445325 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 09:59:32.448874 0 11 4 | B1->B0 | 2b2b 3232 | 0 1 | (0 0) (0 0)
1517 09:59:32.452512 0 11 8 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
1518 09:59:32.458952 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1519 09:59:32.462416 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1520 09:59:32.465515 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1521 09:59:32.472451 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1522 09:59:32.475718 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1523 09:59:32.478833 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1524 09:59:32.485880 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1525 09:59:32.489381 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1526 09:59:32.492426 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1527 09:59:32.499009 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1528 09:59:32.502569 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1529 09:59:32.505566 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1530 09:59:32.513014 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1531 09:59:32.515936 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1532 09:59:32.519863 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1533 09:59:32.522882 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1534 09:59:32.529430 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1535 09:59:32.532785 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1536 09:59:32.536435 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1537 09:59:32.543174 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1538 09:59:32.545881 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1539 09:59:32.549930 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1540 09:59:32.556267 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1541 09:59:32.559592 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1542 09:59:32.563197 Total UI for P1: 0, mck2ui 16
1543 09:59:32.566420 best dqsien dly found for B0: ( 0, 14, 6)
1544 09:59:32.569444 Total UI for P1: 0, mck2ui 16
1545 09:59:32.573263 best dqsien dly found for B1: ( 0, 14, 6)
1546 09:59:32.576258 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1547 09:59:32.579708 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1548 09:59:32.579807
1549 09:59:32.583671 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1550 09:59:32.586503 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1551 09:59:32.589780 [Gating] SW calibration Done
1552 09:59:32.589876 ==
1553 09:59:32.593387 Dram Type= 6, Freq= 0, CH_1, rank 0
1554 09:59:32.596450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1555 09:59:32.596546 ==
1556 09:59:32.599838 RX Vref Scan: 0
1557 09:59:32.599955
1558 09:59:32.600038 RX Vref 0 -> 0, step: 1
1559 09:59:32.603439
1560 09:59:32.603530 RX Delay -130 -> 252, step: 16
1561 09:59:32.610182 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1562 09:59:32.612926 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1563 09:59:32.616309 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1564 09:59:32.619974 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1565 09:59:32.623251 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1566 09:59:32.626962 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1567 09:59:32.633519 iDelay=222, Bit 6, Center 109 (-2 ~ 221) 224
1568 09:59:32.636369 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1569 09:59:32.640043 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1570 09:59:32.643263 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1571 09:59:32.646657 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1572 09:59:32.653104 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1573 09:59:32.656684 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1574 09:59:32.660118 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1575 09:59:32.663508 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1576 09:59:32.670063 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1577 09:59:32.670185 ==
1578 09:59:32.672972 Dram Type= 6, Freq= 0, CH_1, rank 0
1579 09:59:32.676322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1580 09:59:32.676416 ==
1581 09:59:32.676482 DQS Delay:
1582 09:59:32.680317 DQS0 = 0, DQS1 = 0
1583 09:59:32.680408 DQM Delay:
1584 09:59:32.683477 DQM0 = 94, DQM1 = 89
1585 09:59:32.683568 DQ Delay:
1586 09:59:32.686443 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1587 09:59:32.689893 DQ4 =93, DQ5 =109, DQ6 =109, DQ7 =93
1588 09:59:32.693263 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1589 09:59:32.696428 DQ12 =93, DQ13 =101, DQ14 =93, DQ15 =101
1590 09:59:32.696522
1591 09:59:32.696589
1592 09:59:32.696649 ==
1593 09:59:32.699733 Dram Type= 6, Freq= 0, CH_1, rank 0
1594 09:59:32.703121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1595 09:59:32.703224 ==
1596 09:59:32.703293
1597 09:59:32.703354
1598 09:59:32.706457 TX Vref Scan disable
1599 09:59:32.710115 == TX Byte 0 ==
1600 09:59:32.713205 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1601 09:59:32.716775 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1602 09:59:32.719992 == TX Byte 1 ==
1603 09:59:32.724542 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1604 09:59:32.728050 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1605 09:59:32.728166 ==
1606 09:59:32.730999 Dram Type= 6, Freq= 0, CH_1, rank 0
1607 09:59:32.734205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1608 09:59:32.734294 ==
1609 09:59:32.748291 TX Vref=22, minBit 3, minWin=26, winSum=437
1610 09:59:32.751082 TX Vref=24, minBit 3, minWin=26, winSum=435
1611 09:59:32.754915 TX Vref=26, minBit 0, minWin=26, winSum=440
1612 09:59:32.757937 TX Vref=28, minBit 3, minWin=26, winSum=438
1613 09:59:32.761623 TX Vref=30, minBit 3, minWin=26, winSum=443
1614 09:59:32.764876 TX Vref=32, minBit 2, minWin=26, winSum=441
1615 09:59:32.771594 [TxChooseVref] Worse bit 3, Min win 26, Win sum 443, Final Vref 30
1616 09:59:32.771705
1617 09:59:32.774695 Final TX Range 1 Vref 30
1618 09:59:32.774780
1619 09:59:32.774844 ==
1620 09:59:32.778377 Dram Type= 6, Freq= 0, CH_1, rank 0
1621 09:59:32.781446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1622 09:59:32.781534 ==
1623 09:59:32.781634
1624 09:59:32.781693
1625 09:59:32.784897 TX Vref Scan disable
1626 09:59:32.788113 == TX Byte 0 ==
1627 09:59:32.791977 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1628 09:59:32.794730 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1629 09:59:32.798127 == TX Byte 1 ==
1630 09:59:32.801506 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1631 09:59:32.804944 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1632 09:59:32.805043
1633 09:59:32.808149 [DATLAT]
1634 09:59:32.808233 Freq=800, CH1 RK0
1635 09:59:32.808298
1636 09:59:32.811655 DATLAT Default: 0xa
1637 09:59:32.811740 0, 0xFFFF, sum = 0
1638 09:59:32.814732 1, 0xFFFF, sum = 0
1639 09:59:32.814817 2, 0xFFFF, sum = 0
1640 09:59:32.818310 3, 0xFFFF, sum = 0
1641 09:59:32.818431 4, 0xFFFF, sum = 0
1642 09:59:32.822017 5, 0xFFFF, sum = 0
1643 09:59:32.822131 6, 0xFFFF, sum = 0
1644 09:59:32.824938 7, 0xFFFF, sum = 0
1645 09:59:32.825048 8, 0xFFFF, sum = 0
1646 09:59:32.828545 9, 0x0, sum = 1
1647 09:59:32.828659 10, 0x0, sum = 2
1648 09:59:32.831702 11, 0x0, sum = 3
1649 09:59:32.831814 12, 0x0, sum = 4
1650 09:59:32.834904 best_step = 10
1651 09:59:32.835015
1652 09:59:32.835109 ==
1653 09:59:32.838663 Dram Type= 6, Freq= 0, CH_1, rank 0
1654 09:59:32.841826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1655 09:59:32.841944 ==
1656 09:59:32.845104 RX Vref Scan: 1
1657 09:59:32.845216
1658 09:59:32.845310 Set Vref Range= 32 -> 127
1659 09:59:32.845400
1660 09:59:32.848483 RX Vref 32 -> 127, step: 1
1661 09:59:32.848592
1662 09:59:32.851998 RX Delay -79 -> 252, step: 8
1663 09:59:32.852109
1664 09:59:32.855339 Set Vref, RX VrefLevel [Byte0]: 32
1665 09:59:32.858243 [Byte1]: 32
1666 09:59:32.858355
1667 09:59:32.862002 Set Vref, RX VrefLevel [Byte0]: 33
1668 09:59:32.864810 [Byte1]: 33
1669 09:59:32.864919
1670 09:59:32.868493 Set Vref, RX VrefLevel [Byte0]: 34
1671 09:59:32.871700 [Byte1]: 34
1672 09:59:32.875635
1673 09:59:32.875750 Set Vref, RX VrefLevel [Byte0]: 35
1674 09:59:32.879347 [Byte1]: 35
1675 09:59:32.883068
1676 09:59:32.883183 Set Vref, RX VrefLevel [Byte0]: 36
1677 09:59:32.886712 [Byte1]: 36
1678 09:59:32.890719
1679 09:59:32.890833 Set Vref, RX VrefLevel [Byte0]: 37
1680 09:59:32.894133 [Byte1]: 37
1681 09:59:32.898499
1682 09:59:32.898613 Set Vref, RX VrefLevel [Byte0]: 38
1683 09:59:32.901382 [Byte1]: 38
1684 09:59:32.906259
1685 09:59:32.906384 Set Vref, RX VrefLevel [Byte0]: 39
1686 09:59:32.909014 [Byte1]: 39
1687 09:59:32.913545
1688 09:59:32.913701 Set Vref, RX VrefLevel [Byte0]: 40
1689 09:59:32.916734 [Byte1]: 40
1690 09:59:32.920712
1691 09:59:32.920834 Set Vref, RX VrefLevel [Byte0]: 41
1692 09:59:32.924012 [Byte1]: 41
1693 09:59:32.928353
1694 09:59:32.928475 Set Vref, RX VrefLevel [Byte0]: 42
1695 09:59:32.931755 [Byte1]: 42
1696 09:59:32.935748
1697 09:59:32.935868 Set Vref, RX VrefLevel [Byte0]: 43
1698 09:59:32.939316 [Byte1]: 43
1699 09:59:32.943549
1700 09:59:32.943670 Set Vref, RX VrefLevel [Byte0]: 44
1701 09:59:32.947066 [Byte1]: 44
1702 09:59:32.951311
1703 09:59:32.951431 Set Vref, RX VrefLevel [Byte0]: 45
1704 09:59:32.954644 [Byte1]: 45
1705 09:59:32.958773
1706 09:59:32.958885 Set Vref, RX VrefLevel [Byte0]: 46
1707 09:59:32.961704 [Byte1]: 46
1708 09:59:32.965971
1709 09:59:32.966078 Set Vref, RX VrefLevel [Byte0]: 47
1710 09:59:32.969280 [Byte1]: 47
1711 09:59:32.973503
1712 09:59:32.973646 Set Vref, RX VrefLevel [Byte0]: 48
1713 09:59:32.977175 [Byte1]: 48
1714 09:59:32.982008
1715 09:59:32.982115 Set Vref, RX VrefLevel [Byte0]: 49
1716 09:59:32.984733 [Byte1]: 49
1717 09:59:32.988581
1718 09:59:32.988685 Set Vref, RX VrefLevel [Byte0]: 50
1719 09:59:32.992496 [Byte1]: 50
1720 09:59:32.996448
1721 09:59:32.996552 Set Vref, RX VrefLevel [Byte0]: 51
1722 09:59:32.999520 [Byte1]: 51
1723 09:59:33.003931
1724 09:59:33.004035 Set Vref, RX VrefLevel [Byte0]: 52
1725 09:59:33.007710 [Byte1]: 52
1726 09:59:33.011601
1727 09:59:33.011705 Set Vref, RX VrefLevel [Byte0]: 53
1728 09:59:33.014805 [Byte1]: 53
1729 09:59:33.018960
1730 09:59:33.019068 Set Vref, RX VrefLevel [Byte0]: 54
1731 09:59:33.022609 [Byte1]: 54
1732 09:59:33.026405
1733 09:59:33.026513 Set Vref, RX VrefLevel [Byte0]: 55
1734 09:59:33.029569 [Byte1]: 55
1735 09:59:33.033973
1736 09:59:33.034079 Set Vref, RX VrefLevel [Byte0]: 56
1737 09:59:33.037363 [Byte1]: 56
1738 09:59:33.041667
1739 09:59:33.041771 Set Vref, RX VrefLevel [Byte0]: 57
1740 09:59:33.044778 [Byte1]: 57
1741 09:59:33.049190
1742 09:59:33.049307 Set Vref, RX VrefLevel [Byte0]: 58
1743 09:59:33.052317 [Byte1]: 58
1744 09:59:33.056625
1745 09:59:33.056717 Set Vref, RX VrefLevel [Byte0]: 59
1746 09:59:33.059737 [Byte1]: 59
1747 09:59:33.064163
1748 09:59:33.064292 Set Vref, RX VrefLevel [Byte0]: 60
1749 09:59:33.067618 [Byte1]: 60
1750 09:59:33.071992
1751 09:59:33.072100 Set Vref, RX VrefLevel [Byte0]: 61
1752 09:59:33.074947 [Byte1]: 61
1753 09:59:33.079478
1754 09:59:33.079586 Set Vref, RX VrefLevel [Byte0]: 62
1755 09:59:33.082650 [Byte1]: 62
1756 09:59:33.087004
1757 09:59:33.087112 Set Vref, RX VrefLevel [Byte0]: 63
1758 09:59:33.090081 [Byte1]: 63
1759 09:59:33.094456
1760 09:59:33.094561 Set Vref, RX VrefLevel [Byte0]: 64
1761 09:59:33.098150 [Byte1]: 64
1762 09:59:33.102198
1763 09:59:33.102304 Set Vref, RX VrefLevel [Byte0]: 65
1764 09:59:33.105295 [Byte1]: 65
1765 09:59:33.109550
1766 09:59:33.109690 Set Vref, RX VrefLevel [Byte0]: 66
1767 09:59:33.113155 [Byte1]: 66
1768 09:59:33.116958
1769 09:59:33.117064 Set Vref, RX VrefLevel [Byte0]: 67
1770 09:59:33.120818 [Byte1]: 67
1771 09:59:33.124715
1772 09:59:33.124819 Set Vref, RX VrefLevel [Byte0]: 68
1773 09:59:33.127674 [Byte1]: 68
1774 09:59:33.132336
1775 09:59:33.132438 Set Vref, RX VrefLevel [Byte0]: 69
1776 09:59:33.135920 [Byte1]: 69
1777 09:59:33.139780
1778 09:59:33.139884 Set Vref, RX VrefLevel [Byte0]: 70
1779 09:59:33.143576 [Byte1]: 70
1780 09:59:33.147284
1781 09:59:33.147389 Set Vref, RX VrefLevel [Byte0]: 71
1782 09:59:33.150917 [Byte1]: 71
1783 09:59:33.154893
1784 09:59:33.154999 Set Vref, RX VrefLevel [Byte0]: 72
1785 09:59:33.157964 [Byte1]: 72
1786 09:59:33.162433
1787 09:59:33.162539 Set Vref, RX VrefLevel [Byte0]: 73
1788 09:59:33.165929 [Byte1]: 73
1789 09:59:33.170240
1790 09:59:33.170343 Set Vref, RX VrefLevel [Byte0]: 74
1791 09:59:33.173274 [Byte1]: 74
1792 09:59:33.177157
1793 09:59:33.177264 Final RX Vref Byte 0 = 55 to rank0
1794 09:59:33.180969 Final RX Vref Byte 1 = 57 to rank0
1795 09:59:33.184279 Final RX Vref Byte 0 = 55 to rank1
1796 09:59:33.188108 Final RX Vref Byte 1 = 57 to rank1==
1797 09:59:33.190895 Dram Type= 6, Freq= 0, CH_1, rank 0
1798 09:59:33.197557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1799 09:59:33.197707 ==
1800 09:59:33.197802 DQS Delay:
1801 09:59:33.197893 DQS0 = 0, DQS1 = 0
1802 09:59:33.200502 DQM Delay:
1803 09:59:33.200604 DQM0 = 95, DQM1 = 90
1804 09:59:33.204115 DQ Delay:
1805 09:59:33.207384 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =88
1806 09:59:33.211111 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =92
1807 09:59:33.211220 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =84
1808 09:59:33.217481 DQ12 =96, DQ13 =96, DQ14 =100, DQ15 =96
1809 09:59:33.217633
1810 09:59:33.217729
1811 09:59:33.224492 [DQSOSCAuto] RK0, (LSB)MR18= 0x2c49, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
1812 09:59:33.227478 CH1 RK0: MR19=606, MR18=2C49
1813 09:59:33.234233 CH1_RK0: MR19=0x606, MR18=0x2C49, DQSOSC=391, MR23=63, INC=96, DEC=64
1814 09:59:33.234348
1815 09:59:33.237836 ----->DramcWriteLeveling(PI) begin...
1816 09:59:33.237941 ==
1817 09:59:33.241126 Dram Type= 6, Freq= 0, CH_1, rank 1
1818 09:59:33.244069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1819 09:59:33.244172 ==
1820 09:59:33.247779 Write leveling (Byte 0): 25 => 25
1821 09:59:33.250940 Write leveling (Byte 1): 31 => 31
1822 09:59:33.254535 DramcWriteLeveling(PI) end<-----
1823 09:59:33.254642
1824 09:59:33.254735 ==
1825 09:59:33.257562 Dram Type= 6, Freq= 0, CH_1, rank 1
1826 09:59:33.261350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1827 09:59:33.261457 ==
1828 09:59:33.264626 [Gating] SW mode calibration
1829 09:59:33.271327 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1830 09:59:33.277625 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1831 09:59:33.280937 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1832 09:59:33.284235 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1833 09:59:33.290922 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 09:59:33.294585 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 09:59:33.297896 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 09:59:33.304242 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 09:59:33.307658 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 09:59:33.311332 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 09:59:33.317803 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 09:59:33.320969 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 09:59:33.324620 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 09:59:33.327784 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 09:59:33.334610 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 09:59:33.337749 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 09:59:33.340890 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 09:59:33.347911 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 09:59:33.351461 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1848 09:59:33.354560 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1849 09:59:33.360914 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 09:59:33.364175 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 09:59:33.367644 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 09:59:33.374414 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 09:59:33.377538 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 09:59:33.380615 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 09:59:33.387266 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 09:59:33.390992 0 9 4 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
1857 09:59:33.394298 0 9 8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
1858 09:59:33.400684 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1859 09:59:33.404427 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1860 09:59:33.407643 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1861 09:59:33.414211 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1862 09:59:33.417791 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1863 09:59:33.421294 0 10 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1864 09:59:33.427858 0 10 4 | B1->B0 | 2d2d 3232 | 0 0 | (0 1) (1 0)
1865 09:59:33.431207 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 09:59:33.434592 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 09:59:33.441027 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 09:59:33.443986 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 09:59:33.447690 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 09:59:33.450904 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 09:59:33.457845 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 09:59:33.460778 0 11 4 | B1->B0 | 3333 2929 | 0 1 | (0 0) (0 0)
1873 09:59:33.463982 0 11 8 | B1->B0 | 4646 4242 | 0 0 | (0 0) (0 0)
1874 09:59:33.470907 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1875 09:59:33.473907 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1876 09:59:33.477625 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1877 09:59:33.484019 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1878 09:59:33.487663 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1879 09:59:33.490606 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1880 09:59:33.497396 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1881 09:59:33.500884 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 09:59:33.504406 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 09:59:33.510572 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1884 09:59:33.513897 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1885 09:59:33.517365 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1886 09:59:33.524553 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1887 09:59:33.527489 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1888 09:59:33.530945 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1889 09:59:33.537701 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1890 09:59:33.541487 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1891 09:59:33.544296 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1892 09:59:33.547927 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1893 09:59:33.554079 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1894 09:59:33.557376 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1895 09:59:33.561208 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1896 09:59:33.567502 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1897 09:59:33.570947 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1898 09:59:33.574257 Total UI for P1: 0, mck2ui 16
1899 09:59:33.577470 best dqsien dly found for B0: ( 0, 14, 4)
1900 09:59:33.581150 Total UI for P1: 0, mck2ui 16
1901 09:59:33.584304 best dqsien dly found for B1: ( 0, 14, 4)
1902 09:59:33.587437 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1903 09:59:33.590993 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1904 09:59:33.591076
1905 09:59:33.594786 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1906 09:59:33.597668 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1907 09:59:33.601414 [Gating] SW calibration Done
1908 09:59:33.601496 ==
1909 09:59:33.604374 Dram Type= 6, Freq= 0, CH_1, rank 1
1910 09:59:33.607988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1911 09:59:33.608072 ==
1912 09:59:33.610811 RX Vref Scan: 0
1913 09:59:33.610892
1914 09:59:33.614589 RX Vref 0 -> 0, step: 1
1915 09:59:33.614672
1916 09:59:33.614737 RX Delay -130 -> 252, step: 16
1917 09:59:33.621148 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1918 09:59:33.624585 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1919 09:59:33.627774 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1920 09:59:33.631142 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1921 09:59:33.634656 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1922 09:59:33.641063 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1923 09:59:33.644338 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1924 09:59:33.647994 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1925 09:59:33.651200 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1926 09:59:33.654646 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1927 09:59:33.660929 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1928 09:59:33.664686 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1929 09:59:33.667642 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1930 09:59:33.671176 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1931 09:59:33.674428 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1932 09:59:33.680942 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1933 09:59:33.681027 ==
1934 09:59:33.684416 Dram Type= 6, Freq= 0, CH_1, rank 1
1935 09:59:33.687802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1936 09:59:33.687889 ==
1937 09:59:33.687956 DQS Delay:
1938 09:59:33.690793 DQS0 = 0, DQS1 = 0
1939 09:59:33.690875 DQM Delay:
1940 09:59:33.694400 DQM0 = 93, DQM1 = 89
1941 09:59:33.694482 DQ Delay:
1942 09:59:33.698322 DQ0 =101, DQ1 =85, DQ2 =85, DQ3 =85
1943 09:59:33.701201 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1944 09:59:33.704258 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =85
1945 09:59:33.708098 DQ12 =93, DQ13 =101, DQ14 =93, DQ15 =93
1946 09:59:33.708184
1947 09:59:33.708249
1948 09:59:33.708310 ==
1949 09:59:33.710962 Dram Type= 6, Freq= 0, CH_1, rank 1
1950 09:59:33.714293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1951 09:59:33.717426 ==
1952 09:59:33.717509
1953 09:59:33.717600
1954 09:59:33.717697 TX Vref Scan disable
1955 09:59:33.721005 == TX Byte 0 ==
1956 09:59:33.724183 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1957 09:59:33.727874 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1958 09:59:33.730974 == TX Byte 1 ==
1959 09:59:33.734298 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1960 09:59:33.737551 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1961 09:59:33.740973 ==
1962 09:59:33.741060 Dram Type= 6, Freq= 0, CH_1, rank 1
1963 09:59:33.747832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1964 09:59:33.747923 ==
1965 09:59:33.760159 TX Vref=22, minBit 3, minWin=25, winSum=436
1966 09:59:33.763668 TX Vref=24, minBit 1, minWin=26, winSum=437
1967 09:59:33.767224 TX Vref=26, minBit 1, minWin=26, winSum=440
1968 09:59:33.770375 TX Vref=28, minBit 2, minWin=26, winSum=439
1969 09:59:33.773556 TX Vref=30, minBit 0, minWin=26, winSum=440
1970 09:59:33.777294 TX Vref=32, minBit 0, minWin=26, winSum=442
1971 09:59:33.784204 [TxChooseVref] Worse bit 0, Min win 26, Win sum 442, Final Vref 32
1972 09:59:33.784303
1973 09:59:33.786937 Final TX Range 1 Vref 32
1974 09:59:33.787022
1975 09:59:33.787086 ==
1976 09:59:33.790344 Dram Type= 6, Freq= 0, CH_1, rank 1
1977 09:59:33.793843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1978 09:59:33.793928 ==
1979 09:59:33.793992
1980 09:59:33.794051
1981 09:59:33.796972 TX Vref Scan disable
1982 09:59:33.800328 == TX Byte 0 ==
1983 09:59:33.803609 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1984 09:59:33.806942 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1985 09:59:33.810460 == TX Byte 1 ==
1986 09:59:33.813461 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1987 09:59:33.817202 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1988 09:59:33.820682
1989 09:59:33.820768 [DATLAT]
1990 09:59:33.820834 Freq=800, CH1 RK1
1991 09:59:33.820894
1992 09:59:33.823638 DATLAT Default: 0xa
1993 09:59:33.823720 0, 0xFFFF, sum = 0
1994 09:59:33.827303 1, 0xFFFF, sum = 0
1995 09:59:33.827388 2, 0xFFFF, sum = 0
1996 09:59:33.830374 3, 0xFFFF, sum = 0
1997 09:59:33.830463 4, 0xFFFF, sum = 0
1998 09:59:33.833651 5, 0xFFFF, sum = 0
1999 09:59:33.833740 6, 0xFFFF, sum = 0
2000 09:59:33.837095 7, 0xFFFF, sum = 0
2001 09:59:33.840270 8, 0xFFFF, sum = 0
2002 09:59:33.840365 9, 0x0, sum = 1
2003 09:59:33.840432 10, 0x0, sum = 2
2004 09:59:33.843798 11, 0x0, sum = 3
2005 09:59:33.843887 12, 0x0, sum = 4
2006 09:59:33.847109 best_step = 10
2007 09:59:33.847198
2008 09:59:33.847263 ==
2009 09:59:33.850562 Dram Type= 6, Freq= 0, CH_1, rank 1
2010 09:59:33.853657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2011 09:59:33.853802 ==
2012 09:59:33.857143 RX Vref Scan: 0
2013 09:59:33.857234
2014 09:59:33.857300 RX Vref 0 -> 0, step: 1
2015 09:59:33.857360
2016 09:59:33.860691 RX Delay -79 -> 252, step: 8
2017 09:59:33.867388 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
2018 09:59:33.870610 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
2019 09:59:33.873703 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
2020 09:59:33.877072 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
2021 09:59:33.880410 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
2022 09:59:33.884087 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
2023 09:59:33.890472 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2024 09:59:33.893628 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
2025 09:59:33.897366 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2026 09:59:33.900868 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2027 09:59:33.903650 iDelay=209, Bit 10, Center 96 (-7 ~ 200) 208
2028 09:59:33.910573 iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208
2029 09:59:33.913815 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2030 09:59:33.917332 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2031 09:59:33.920434 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2032 09:59:33.923991 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2033 09:59:33.924132 ==
2034 09:59:33.927342 Dram Type= 6, Freq= 0, CH_1, rank 1
2035 09:59:33.933461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2036 09:59:33.933546 ==
2037 09:59:33.933650 DQS Delay:
2038 09:59:33.937058 DQS0 = 0, DQS1 = 0
2039 09:59:33.937139 DQM Delay:
2040 09:59:33.937202 DQM0 = 97, DQM1 = 91
2041 09:59:33.940684 DQ Delay:
2042 09:59:33.943882 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2043 09:59:33.947393 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2044 09:59:33.950557 DQ8 =80, DQ9 =80, DQ10 =96, DQ11 =88
2045 09:59:33.953671 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2046 09:59:33.953752
2047 09:59:33.953816
2048 09:59:33.960282 [DQSOSCAuto] RK1, (LSB)MR18= 0x440e, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
2049 09:59:33.964109 CH1 RK1: MR19=606, MR18=440E
2050 09:59:33.970967 CH1_RK1: MR19=0x606, MR18=0x440E, DQSOSC=392, MR23=63, INC=96, DEC=64
2051 09:59:33.974102 [RxdqsGatingPostProcess] freq 800
2052 09:59:33.977195 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2053 09:59:33.980695 Pre-setting of DQS Precalculation
2054 09:59:33.986952 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2055 09:59:33.993778 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2056 09:59:34.000966 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2057 09:59:34.001052
2058 09:59:34.001116
2059 09:59:34.004181 [Calibration Summary] 1600 Mbps
2060 09:59:34.004266 CH 0, Rank 0
2061 09:59:34.007473 SW Impedance : PASS
2062 09:59:34.010646 DUTY Scan : NO K
2063 09:59:34.010732 ZQ Calibration : PASS
2064 09:59:34.014491 Jitter Meter : NO K
2065 09:59:34.017663 CBT Training : PASS
2066 09:59:34.017745 Write leveling : PASS
2067 09:59:34.020562 RX DQS gating : PASS
2068 09:59:34.024145 RX DQ/DQS(RDDQC) : PASS
2069 09:59:34.024226 TX DQ/DQS : PASS
2070 09:59:34.027268 RX DATLAT : PASS
2071 09:59:34.030469 RX DQ/DQS(Engine): PASS
2072 09:59:34.030550 TX OE : NO K
2073 09:59:34.030614 All Pass.
2074 09:59:34.030673
2075 09:59:34.034108 CH 0, Rank 1
2076 09:59:34.034190 SW Impedance : PASS
2077 09:59:34.037439 DUTY Scan : NO K
2078 09:59:34.040809 ZQ Calibration : PASS
2079 09:59:34.040893 Jitter Meter : NO K
2080 09:59:34.044312 CBT Training : PASS
2081 09:59:34.047621 Write leveling : PASS
2082 09:59:34.047706 RX DQS gating : PASS
2083 09:59:34.050527 RX DQ/DQS(RDDQC) : PASS
2084 09:59:34.054102 TX DQ/DQS : PASS
2085 09:59:34.054218 RX DATLAT : PASS
2086 09:59:34.057307 RX DQ/DQS(Engine): PASS
2087 09:59:34.061203 TX OE : NO K
2088 09:59:34.061286 All Pass.
2089 09:59:34.061350
2090 09:59:34.061409 CH 1, Rank 0
2091 09:59:34.064395 SW Impedance : PASS
2092 09:59:34.067363 DUTY Scan : NO K
2093 09:59:34.067444 ZQ Calibration : PASS
2094 09:59:34.071318 Jitter Meter : NO K
2095 09:59:34.071400 CBT Training : PASS
2096 09:59:34.074057 Write leveling : PASS
2097 09:59:34.077345 RX DQS gating : PASS
2098 09:59:34.077449 RX DQ/DQS(RDDQC) : PASS
2099 09:59:34.080837 TX DQ/DQS : PASS
2100 09:59:34.084038 RX DATLAT : PASS
2101 09:59:34.084123 RX DQ/DQS(Engine): PASS
2102 09:59:34.087362 TX OE : NO K
2103 09:59:34.087446 All Pass.
2104 09:59:34.087511
2105 09:59:34.090773 CH 1, Rank 1
2106 09:59:34.090949 SW Impedance : PASS
2107 09:59:34.094171 DUTY Scan : NO K
2108 09:59:34.097521 ZQ Calibration : PASS
2109 09:59:34.097635 Jitter Meter : NO K
2110 09:59:34.101135 CBT Training : PASS
2111 09:59:34.104038 Write leveling : PASS
2112 09:59:34.104120 RX DQS gating : PASS
2113 09:59:34.107594 RX DQ/DQS(RDDQC) : PASS
2114 09:59:34.110960 TX DQ/DQS : PASS
2115 09:59:34.111041 RX DATLAT : PASS
2116 09:59:34.114155 RX DQ/DQS(Engine): PASS
2117 09:59:34.114258 TX OE : NO K
2118 09:59:34.117501 All Pass.
2119 09:59:34.117605
2120 09:59:34.117686 DramC Write-DBI off
2121 09:59:34.121212 PER_BANK_REFRESH: Hybrid Mode
2122 09:59:34.124222 TX_TRACKING: ON
2123 09:59:34.127873 [GetDramInforAfterCalByMRR] Vendor 6.
2124 09:59:34.131022 [GetDramInforAfterCalByMRR] Revision 606.
2125 09:59:34.134876 [GetDramInforAfterCalByMRR] Revision 2 0.
2126 09:59:34.134957 MR0 0x3b3b
2127 09:59:34.135022 MR8 0x5151
2128 09:59:34.140830 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2129 09:59:34.140911
2130 09:59:34.140974 MR0 0x3b3b
2131 09:59:34.141032 MR8 0x5151
2132 09:59:34.144424 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2133 09:59:34.144505
2134 09:59:34.154263 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2135 09:59:34.157826 [FAST_K] Save calibration result to emmc
2136 09:59:34.160955 [FAST_K] Save calibration result to emmc
2137 09:59:34.164288 dram_init: config_dvfs: 1
2138 09:59:34.167609 dramc_set_vcore_voltage set vcore to 662500
2139 09:59:34.171328 Read voltage for 1200, 2
2140 09:59:34.171436 Vio18 = 0
2141 09:59:34.171556 Vcore = 662500
2142 09:59:34.174354 Vdram = 0
2143 09:59:34.174435 Vddq = 0
2144 09:59:34.174500 Vmddr = 0
2145 09:59:34.181232 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2146 09:59:34.184118 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2147 09:59:34.187947 MEM_TYPE=3, freq_sel=15
2148 09:59:34.190948 sv_algorithm_assistance_LP4_1600
2149 09:59:34.194606 ============ PULL DRAM RESETB DOWN ============
2150 09:59:34.198072 ========== PULL DRAM RESETB DOWN end =========
2151 09:59:34.204871 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2152 09:59:34.207583 ===================================
2153 09:59:34.207666 LPDDR4 DRAM CONFIGURATION
2154 09:59:34.211020 ===================================
2155 09:59:34.214599 EX_ROW_EN[0] = 0x0
2156 09:59:34.217728 EX_ROW_EN[1] = 0x0
2157 09:59:34.217809 LP4Y_EN = 0x0
2158 09:59:34.220874 WORK_FSP = 0x0
2159 09:59:34.220955 WL = 0x4
2160 09:59:34.224673 RL = 0x4
2161 09:59:34.224754 BL = 0x2
2162 09:59:34.227896 RPST = 0x0
2163 09:59:34.227976 RD_PRE = 0x0
2164 09:59:34.230735 WR_PRE = 0x1
2165 09:59:34.230815 WR_PST = 0x0
2166 09:59:34.234198 DBI_WR = 0x0
2167 09:59:34.234279 DBI_RD = 0x0
2168 09:59:34.237724 OTF = 0x1
2169 09:59:34.240837 ===================================
2170 09:59:34.244621 ===================================
2171 09:59:34.244704 ANA top config
2172 09:59:34.247722 ===================================
2173 09:59:34.251392 DLL_ASYNC_EN = 0
2174 09:59:34.254377 ALL_SLAVE_EN = 0
2175 09:59:34.258203 NEW_RANK_MODE = 1
2176 09:59:34.258285 DLL_IDLE_MODE = 1
2177 09:59:34.261014 LP45_APHY_COMB_EN = 1
2178 09:59:34.264764 TX_ODT_DIS = 1
2179 09:59:34.267505 NEW_8X_MODE = 1
2180 09:59:34.271523 ===================================
2181 09:59:34.274740 ===================================
2182 09:59:34.274821 data_rate = 2400
2183 09:59:34.277850 CKR = 1
2184 09:59:34.280862 DQ_P2S_RATIO = 8
2185 09:59:34.284180 ===================================
2186 09:59:34.287805 CA_P2S_RATIO = 8
2187 09:59:34.290951 DQ_CA_OPEN = 0
2188 09:59:34.294706 DQ_SEMI_OPEN = 0
2189 09:59:34.294786 CA_SEMI_OPEN = 0
2190 09:59:34.298160 CA_FULL_RATE = 0
2191 09:59:34.301472 DQ_CKDIV4_EN = 0
2192 09:59:34.304331 CA_CKDIV4_EN = 0
2193 09:59:34.308395 CA_PREDIV_EN = 0
2194 09:59:34.311110 PH8_DLY = 17
2195 09:59:34.311190 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2196 09:59:34.314407 DQ_AAMCK_DIV = 4
2197 09:59:34.317852 CA_AAMCK_DIV = 4
2198 09:59:34.321052 CA_ADMCK_DIV = 4
2199 09:59:34.324544 DQ_TRACK_CA_EN = 0
2200 09:59:34.327998 CA_PICK = 1200
2201 09:59:34.328080 CA_MCKIO = 1200
2202 09:59:34.331722 MCKIO_SEMI = 0
2203 09:59:34.334294 PLL_FREQ = 2366
2204 09:59:34.337969 DQ_UI_PI_RATIO = 32
2205 09:59:34.341611 CA_UI_PI_RATIO = 0
2206 09:59:34.344555 ===================================
2207 09:59:34.348116 ===================================
2208 09:59:34.351456 memory_type:LPDDR4
2209 09:59:34.351539 GP_NUM : 10
2210 09:59:34.355094 SRAM_EN : 1
2211 09:59:34.355176 MD32_EN : 0
2212 09:59:34.358021 ===================================
2213 09:59:34.361115 [ANA_INIT] >>>>>>>>>>>>>>
2214 09:59:34.364487 <<<<<< [CONFIGURE PHASE]: ANA_TX
2215 09:59:34.368237 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2216 09:59:34.371204 ===================================
2217 09:59:34.374320 data_rate = 2400,PCW = 0X5b00
2218 09:59:34.377730 ===================================
2219 09:59:34.381455 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2220 09:59:34.387721 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2221 09:59:34.391061 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2222 09:59:34.398041 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2223 09:59:34.401006 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2224 09:59:34.404656 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2225 09:59:34.404744 [ANA_INIT] flow start
2226 09:59:34.407844 [ANA_INIT] PLL >>>>>>>>
2227 09:59:34.411459 [ANA_INIT] PLL <<<<<<<<
2228 09:59:34.411541 [ANA_INIT] MIDPI >>>>>>>>
2229 09:59:34.414381 [ANA_INIT] MIDPI <<<<<<<<
2230 09:59:34.418397 [ANA_INIT] DLL >>>>>>>>
2231 09:59:34.418480 [ANA_INIT] DLL <<<<<<<<
2232 09:59:34.421221 [ANA_INIT] flow end
2233 09:59:34.424577 ============ LP4 DIFF to SE enter ============
2234 09:59:34.428136 ============ LP4 DIFF to SE exit ============
2235 09:59:34.431415 [ANA_INIT] <<<<<<<<<<<<<
2236 09:59:34.434844 [Flow] Enable top DCM control >>>>>
2237 09:59:34.438070 [Flow] Enable top DCM control <<<<<
2238 09:59:34.441848 Enable DLL master slave shuffle
2239 09:59:34.444762 ==============================================================
2240 09:59:34.448797 Gating Mode config
2241 09:59:34.455335 ==============================================================
2242 09:59:34.455426 Config description:
2243 09:59:34.465248 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2244 09:59:34.471687 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2245 09:59:34.478353 SELPH_MODE 0: By rank 1: By Phase
2246 09:59:34.481725 ==============================================================
2247 09:59:34.484885 GAT_TRACK_EN = 1
2248 09:59:34.488633 RX_GATING_MODE = 2
2249 09:59:34.491427 RX_GATING_TRACK_MODE = 2
2250 09:59:34.495261 SELPH_MODE = 1
2251 09:59:34.498612 PICG_EARLY_EN = 1
2252 09:59:34.501949 VALID_LAT_VALUE = 1
2253 09:59:34.505123 ==============================================================
2254 09:59:34.508144 Enter into Gating configuration >>>>
2255 09:59:34.511589 Exit from Gating configuration <<<<
2256 09:59:34.515268 Enter into DVFS_PRE_config >>>>>
2257 09:59:34.528711 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2258 09:59:34.528814 Exit from DVFS_PRE_config <<<<<
2259 09:59:34.531804 Enter into PICG configuration >>>>
2260 09:59:34.535219 Exit from PICG configuration <<<<
2261 09:59:34.538291 [RX_INPUT] configuration >>>>>
2262 09:59:34.541558 [RX_INPUT] configuration <<<<<
2263 09:59:34.548290 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2264 09:59:34.552185 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2265 09:59:34.558195 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2266 09:59:34.565034 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2267 09:59:34.571719 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2268 09:59:34.578432 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2269 09:59:34.581700 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2270 09:59:34.585287 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2271 09:59:34.588358 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2272 09:59:34.595118 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2273 09:59:34.598596 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2274 09:59:34.601580 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2275 09:59:34.605130 ===================================
2276 09:59:34.608529 LPDDR4 DRAM CONFIGURATION
2277 09:59:34.611774 ===================================
2278 09:59:34.611860 EX_ROW_EN[0] = 0x0
2279 09:59:34.615212 EX_ROW_EN[1] = 0x0
2280 09:59:34.615301 LP4Y_EN = 0x0
2281 09:59:34.618934 WORK_FSP = 0x0
2282 09:59:34.621609 WL = 0x4
2283 09:59:34.621711 RL = 0x4
2284 09:59:34.625428 BL = 0x2
2285 09:59:34.625511 RPST = 0x0
2286 09:59:34.628333 RD_PRE = 0x0
2287 09:59:34.628414 WR_PRE = 0x1
2288 09:59:34.632054 WR_PST = 0x0
2289 09:59:34.632137 DBI_WR = 0x0
2290 09:59:34.634845 DBI_RD = 0x0
2291 09:59:34.634927 OTF = 0x1
2292 09:59:34.638634 ===================================
2293 09:59:34.641776 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2294 09:59:34.648259 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2295 09:59:34.651782 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2296 09:59:34.654831 ===================================
2297 09:59:34.658094 LPDDR4 DRAM CONFIGURATION
2298 09:59:34.661803 ===================================
2299 09:59:34.661913 EX_ROW_EN[0] = 0x10
2300 09:59:34.664758 EX_ROW_EN[1] = 0x0
2301 09:59:34.664847 LP4Y_EN = 0x0
2302 09:59:34.668506 WORK_FSP = 0x0
2303 09:59:34.668597 WL = 0x4
2304 09:59:34.671651 RL = 0x4
2305 09:59:34.671739 BL = 0x2
2306 09:59:34.675011 RPST = 0x0
2307 09:59:34.675102 RD_PRE = 0x0
2308 09:59:34.678394 WR_PRE = 0x1
2309 09:59:34.678488 WR_PST = 0x0
2310 09:59:34.681949 DBI_WR = 0x0
2311 09:59:34.682037 DBI_RD = 0x0
2312 09:59:34.685082 OTF = 0x1
2313 09:59:34.688612 ===================================
2314 09:59:34.695123 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2315 09:59:34.695221 ==
2316 09:59:34.698438 Dram Type= 6, Freq= 0, CH_0, rank 0
2317 09:59:34.701532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2318 09:59:34.701655 ==
2319 09:59:34.705186 [Duty_Offset_Calibration]
2320 09:59:34.705317 B0:2 B1:1 CA:1
2321 09:59:34.705411
2322 09:59:34.708289 [DutyScan_Calibration_Flow] k_type=0
2323 09:59:34.719144
2324 09:59:34.719276 ==CLK 0==
2325 09:59:34.722651 Final CLK duty delay cell = 0
2326 09:59:34.725547 [0] MAX Duty = 5187%(X100), DQS PI = 24
2327 09:59:34.729091 [0] MIN Duty = 4844%(X100), DQS PI = 48
2328 09:59:34.729189 [0] AVG Duty = 5015%(X100)
2329 09:59:34.732270
2330 09:59:34.736187 CH0 CLK Duty spec in!! Max-Min= 343%
2331 09:59:34.739171 [DutyScan_Calibration_Flow] ====Done====
2332 09:59:34.739262
2333 09:59:34.742267 [DutyScan_Calibration_Flow] k_type=1
2334 09:59:34.757756
2335 09:59:34.757932 ==DQS 0 ==
2336 09:59:34.761207 Final DQS duty delay cell = -4
2337 09:59:34.764200 [-4] MAX Duty = 5124%(X100), DQS PI = 24
2338 09:59:34.768080 [-4] MIN Duty = 4751%(X100), DQS PI = 0
2339 09:59:34.771308 [-4] AVG Duty = 4937%(X100)
2340 09:59:34.771397
2341 09:59:34.771462 ==DQS 1 ==
2342 09:59:34.774841 Final DQS duty delay cell = 0
2343 09:59:34.777873 [0] MAX Duty = 5156%(X100), DQS PI = 0
2344 09:59:34.781047 [0] MIN Duty = 5031%(X100), DQS PI = 34
2345 09:59:34.784273 [0] AVG Duty = 5093%(X100)
2346 09:59:34.784365
2347 09:59:34.787903 CH0 DQS 0 Duty spec in!! Max-Min= 373%
2348 09:59:34.788012
2349 09:59:34.791460 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2350 09:59:34.794706 [DutyScan_Calibration_Flow] ====Done====
2351 09:59:34.794796
2352 09:59:34.797760 [DutyScan_Calibration_Flow] k_type=3
2353 09:59:34.814323
2354 09:59:34.814466 ==DQM 0 ==
2355 09:59:34.817782 Final DQM duty delay cell = 0
2356 09:59:34.821780 [0] MAX Duty = 5156%(X100), DQS PI = 32
2357 09:59:34.825045 [0] MIN Duty = 4875%(X100), DQS PI = 58
2358 09:59:34.825141 [0] AVG Duty = 5015%(X100)
2359 09:59:34.827709
2360 09:59:34.827794 ==DQM 1 ==
2361 09:59:34.831201 Final DQM duty delay cell = 0
2362 09:59:34.834703 [0] MAX Duty = 5093%(X100), DQS PI = 0
2363 09:59:34.837851 [0] MIN Duty = 5031%(X100), DQS PI = 14
2364 09:59:34.837944 [0] AVG Duty = 5062%(X100)
2365 09:59:34.841099
2366 09:59:34.844557 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2367 09:59:34.844648
2368 09:59:34.847788 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2369 09:59:34.851315 [DutyScan_Calibration_Flow] ====Done====
2370 09:59:34.851417
2371 09:59:34.854439 [DutyScan_Calibration_Flow] k_type=2
2372 09:59:34.871014
2373 09:59:34.871166 ==DQ 0 ==
2374 09:59:34.874309 Final DQ duty delay cell = 0
2375 09:59:34.877652 [0] MAX Duty = 5062%(X100), DQS PI = 32
2376 09:59:34.880889 [0] MIN Duty = 4906%(X100), DQS PI = 0
2377 09:59:34.880976 [0] AVG Duty = 4984%(X100)
2378 09:59:34.881041
2379 09:59:34.884392 ==DQ 1 ==
2380 09:59:34.884480 Final DQ duty delay cell = 0
2381 09:59:34.891377 [0] MAX Duty = 5093%(X100), DQS PI = 24
2382 09:59:34.894801 [0] MIN Duty = 4938%(X100), DQS PI = 36
2383 09:59:34.894894 [0] AVG Duty = 5015%(X100)
2384 09:59:34.894958
2385 09:59:34.897872 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2386 09:59:34.897960
2387 09:59:34.901282 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2388 09:59:34.904390 [DutyScan_Calibration_Flow] ====Done====
2389 09:59:34.908072 ==
2390 09:59:34.910935 Dram Type= 6, Freq= 0, CH_1, rank 0
2391 09:59:34.914542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2392 09:59:34.914634 ==
2393 09:59:34.917779 [Duty_Offset_Calibration]
2394 09:59:34.917868 B0:1 B1:0 CA:0
2395 09:59:34.917933
2396 09:59:34.921413 [DutyScan_Calibration_Flow] k_type=0
2397 09:59:34.930312
2398 09:59:34.930445 ==CLK 0==
2399 09:59:34.933130 Final CLK duty delay cell = -4
2400 09:59:34.936689 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2401 09:59:34.939632 [-4] MIN Duty = 4875%(X100), DQS PI = 52
2402 09:59:34.943084 [-4] AVG Duty = 4953%(X100)
2403 09:59:34.943175
2404 09:59:34.946660 CH1 CLK Duty spec in!! Max-Min= 156%
2405 09:59:34.950155 [DutyScan_Calibration_Flow] ====Done====
2406 09:59:34.950245
2407 09:59:34.953571 [DutyScan_Calibration_Flow] k_type=1
2408 09:59:34.969975
2409 09:59:34.970127 ==DQS 0 ==
2410 09:59:34.973289 Final DQS duty delay cell = 0
2411 09:59:34.976513 [0] MAX Duty = 5094%(X100), DQS PI = 26
2412 09:59:34.980037 [0] MIN Duty = 4875%(X100), DQS PI = 0
2413 09:59:34.980129 [0] AVG Duty = 4984%(X100)
2414 09:59:34.983332
2415 09:59:34.983419 ==DQS 1 ==
2416 09:59:34.986389 Final DQS duty delay cell = 0
2417 09:59:34.989870 [0] MAX Duty = 5187%(X100), DQS PI = 20
2418 09:59:34.993065 [0] MIN Duty = 4938%(X100), DQS PI = 12
2419 09:59:34.993153 [0] AVG Duty = 5062%(X100)
2420 09:59:34.996748
2421 09:59:34.999912 CH1 DQS 0 Duty spec in!! Max-Min= 219%
2422 09:59:35.000006
2423 09:59:35.003279 CH1 DQS 1 Duty spec in!! Max-Min= 249%
2424 09:59:35.006401 [DutyScan_Calibration_Flow] ====Done====
2425 09:59:35.006499
2426 09:59:35.009735 [DutyScan_Calibration_Flow] k_type=3
2427 09:59:35.026416
2428 09:59:35.026569 ==DQM 0 ==
2429 09:59:35.029738 Final DQM duty delay cell = 0
2430 09:59:35.032897 [0] MAX Duty = 5156%(X100), DQS PI = 8
2431 09:59:35.036465 [0] MIN Duty = 5031%(X100), DQS PI = 0
2432 09:59:35.036561 [0] AVG Duty = 5093%(X100)
2433 09:59:35.039530
2434 09:59:35.039617 ==DQM 1 ==
2435 09:59:35.043102 Final DQM duty delay cell = 0
2436 09:59:35.046084 [0] MAX Duty = 5031%(X100), DQS PI = 16
2437 09:59:35.049744 [0] MIN Duty = 4907%(X100), DQS PI = 36
2438 09:59:35.049832 [0] AVG Duty = 4969%(X100)
2439 09:59:35.052803
2440 09:59:35.056396 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2441 09:59:35.056486
2442 09:59:35.059683 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2443 09:59:35.063513 [DutyScan_Calibration_Flow] ====Done====
2444 09:59:35.063601
2445 09:59:35.066441 [DutyScan_Calibration_Flow] k_type=2
2446 09:59:35.081909
2447 09:59:35.082083 ==DQ 0 ==
2448 09:59:35.085234 Final DQ duty delay cell = -4
2449 09:59:35.088764 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2450 09:59:35.091797 [-4] MIN Duty = 4938%(X100), DQS PI = 0
2451 09:59:35.095127 [-4] AVG Duty = 5000%(X100)
2452 09:59:35.095345
2453 09:59:35.095462 ==DQ 1 ==
2454 09:59:35.098609 Final DQ duty delay cell = 0
2455 09:59:35.102298 [0] MAX Duty = 5125%(X100), DQS PI = 20
2456 09:59:35.105308 [0] MIN Duty = 4938%(X100), DQS PI = 60
2457 09:59:35.105439 [0] AVG Duty = 5031%(X100)
2458 09:59:35.105541
2459 09:59:35.109180 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2460 09:59:35.111937
2461 09:59:35.115438 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2462 09:59:35.118901 [DutyScan_Calibration_Flow] ====Done====
2463 09:59:35.121936 nWR fixed to 30
2464 09:59:35.122041 [ModeRegInit_LP4] CH0 RK0
2465 09:59:35.125655 [ModeRegInit_LP4] CH0 RK1
2466 09:59:35.128757 [ModeRegInit_LP4] CH1 RK0
2467 09:59:35.128850 [ModeRegInit_LP4] CH1 RK1
2468 09:59:35.132315 match AC timing 7
2469 09:59:35.135725 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2470 09:59:35.139217 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2471 09:59:35.145822 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2472 09:59:35.149280 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2473 09:59:35.156206 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2474 09:59:35.156336 ==
2475 09:59:35.159151 Dram Type= 6, Freq= 0, CH_0, rank 0
2476 09:59:35.162524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2477 09:59:35.162617 ==
2478 09:59:35.169110 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2479 09:59:35.172301 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2480 09:59:35.182275 [CA 0] Center 39 (8~70) winsize 63
2481 09:59:35.185724 [CA 1] Center 39 (8~70) winsize 63
2482 09:59:35.188854 [CA 2] Center 35 (5~66) winsize 62
2483 09:59:35.192341 [CA 3] Center 34 (4~65) winsize 62
2484 09:59:35.195736 [CA 4] Center 33 (3~64) winsize 62
2485 09:59:35.198876 [CA 5] Center 32 (3~62) winsize 60
2486 09:59:35.198972
2487 09:59:35.202201 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2488 09:59:35.202294
2489 09:59:35.205981 [CATrainingPosCal] consider 1 rank data
2490 09:59:35.209319 u2DelayCellTimex100 = 270/100 ps
2491 09:59:35.212780 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2492 09:59:35.215694 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2493 09:59:35.222814 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2494 09:59:35.225516 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2495 09:59:35.229310 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2496 09:59:35.232155 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2497 09:59:35.232264
2498 09:59:35.235368 CA PerBit enable=1, Macro0, CA PI delay=32
2499 09:59:35.235461
2500 09:59:35.238844 [CBTSetCACLKResult] CA Dly = 32
2501 09:59:35.238935 CS Dly: 6 (0~37)
2502 09:59:35.239000 ==
2503 09:59:35.242264 Dram Type= 6, Freq= 0, CH_0, rank 1
2504 09:59:35.248709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2505 09:59:35.248852 ==
2506 09:59:35.252020 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2507 09:59:35.258989 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2508 09:59:35.268354 [CA 0] Center 38 (8~69) winsize 62
2509 09:59:35.271135 [CA 1] Center 38 (8~69) winsize 62
2510 09:59:35.274689 [CA 2] Center 35 (4~66) winsize 63
2511 09:59:35.278314 [CA 3] Center 34 (4~65) winsize 62
2512 09:59:35.281547 [CA 4] Center 33 (3~64) winsize 62
2513 09:59:35.285258 [CA 5] Center 32 (2~62) winsize 61
2514 09:59:35.285371
2515 09:59:35.288053 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2516 09:59:35.288141
2517 09:59:35.291704 [CATrainingPosCal] consider 2 rank data
2518 09:59:35.295207 u2DelayCellTimex100 = 270/100 ps
2519 09:59:35.297886 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2520 09:59:35.302092 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2521 09:59:35.305020 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2522 09:59:35.311605 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2523 09:59:35.315040 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2524 09:59:35.318169 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2525 09:59:35.318292
2526 09:59:35.321954 CA PerBit enable=1, Macro0, CA PI delay=32
2527 09:59:35.322060
2528 09:59:35.325220 [CBTSetCACLKResult] CA Dly = 32
2529 09:59:35.325312 CS Dly: 6 (0~38)
2530 09:59:35.325383
2531 09:59:35.328006 ----->DramcWriteLeveling(PI) begin...
2532 09:59:35.328096 ==
2533 09:59:35.331625 Dram Type= 6, Freq= 0, CH_0, rank 0
2534 09:59:35.338370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2535 09:59:35.338500 ==
2536 09:59:35.341506 Write leveling (Byte 0): 35 => 35
2537 09:59:35.345223 Write leveling (Byte 1): 29 => 29
2538 09:59:35.345331 DramcWriteLeveling(PI) end<-----
2539 09:59:35.345397
2540 09:59:35.348610 ==
2541 09:59:35.351648 Dram Type= 6, Freq= 0, CH_0, rank 0
2542 09:59:35.354712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2543 09:59:35.354819 ==
2544 09:59:35.358025 [Gating] SW mode calibration
2545 09:59:35.365224 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2546 09:59:35.368221 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2547 09:59:35.375306 0 15 0 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
2548 09:59:35.378249 0 15 4 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
2549 09:59:35.381567 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2550 09:59:35.388790 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2551 09:59:35.392197 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2552 09:59:35.395304 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2553 09:59:35.402122 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
2554 09:59:35.405732 0 15 28 | B1->B0 | 3434 2626 | 1 0 | (1 0) (0 1)
2555 09:59:35.408854 1 0 0 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
2556 09:59:35.412058 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2557 09:59:35.418435 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2558 09:59:35.422118 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2559 09:59:35.425286 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2560 09:59:35.431804 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2561 09:59:35.435273 1 0 24 | B1->B0 | 2323 302f | 0 1 | (0 0) (0 0)
2562 09:59:35.439200 1 0 28 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
2563 09:59:35.445194 1 1 0 | B1->B0 | 3838 4646 | 1 0 | (0 0) (0 0)
2564 09:59:35.449020 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2565 09:59:35.452164 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2566 09:59:35.458560 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2567 09:59:35.462331 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2568 09:59:35.465266 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2569 09:59:35.471951 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2570 09:59:35.475376 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2571 09:59:35.478662 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 09:59:35.485282 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 09:59:35.488701 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 09:59:35.492068 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2575 09:59:35.496014 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2576 09:59:35.502142 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2577 09:59:35.505188 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2578 09:59:35.508792 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2579 09:59:35.515438 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2580 09:59:35.518704 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2581 09:59:35.522425 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2582 09:59:35.529047 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2583 09:59:35.532051 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2584 09:59:35.535699 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2585 09:59:35.542179 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2586 09:59:35.545873 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2587 09:59:35.548911 Total UI for P1: 0, mck2ui 16
2588 09:59:35.552071 best dqsien dly found for B0: ( 1, 3, 24)
2589 09:59:35.555207 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2590 09:59:35.561921 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2591 09:59:35.562049 Total UI for P1: 0, mck2ui 16
2592 09:59:35.565683 best dqsien dly found for B1: ( 1, 3, 30)
2593 09:59:35.571947 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2594 09:59:35.575216 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2595 09:59:35.575327
2596 09:59:35.578736 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2597 09:59:35.582096 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2598 09:59:35.585527 [Gating] SW calibration Done
2599 09:59:35.585649 ==
2600 09:59:35.588678 Dram Type= 6, Freq= 0, CH_0, rank 0
2601 09:59:35.592394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2602 09:59:35.592518 ==
2603 09:59:35.595104 RX Vref Scan: 0
2604 09:59:35.595193
2605 09:59:35.595259 RX Vref 0 -> 0, step: 1
2606 09:59:35.595321
2607 09:59:35.598664 RX Delay -40 -> 252, step: 8
2608 09:59:35.602229 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2609 09:59:35.608816 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2610 09:59:35.611946 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2611 09:59:35.615240 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2612 09:59:35.618340 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2613 09:59:35.621812 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2614 09:59:35.624891 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2615 09:59:35.631976 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2616 09:59:35.635900 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2617 09:59:35.638841 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2618 09:59:35.642060 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2619 09:59:35.645305 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2620 09:59:35.651949 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2621 09:59:35.655196 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2622 09:59:35.658727 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2623 09:59:35.662769 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2624 09:59:35.662874 ==
2625 09:59:35.665320 Dram Type= 6, Freq= 0, CH_0, rank 0
2626 09:59:35.671963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2627 09:59:35.672087 ==
2628 09:59:35.672157 DQS Delay:
2629 09:59:35.672218 DQS0 = 0, DQS1 = 0
2630 09:59:35.675532 DQM Delay:
2631 09:59:35.675619 DQM0 = 121, DQM1 = 113
2632 09:59:35.679222 DQ Delay:
2633 09:59:35.682224 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2634 09:59:35.685602 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2635 09:59:35.688628 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2636 09:59:35.692254 DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =119
2637 09:59:35.692352
2638 09:59:35.692417
2639 09:59:35.692477 ==
2640 09:59:35.695520 Dram Type= 6, Freq= 0, CH_0, rank 0
2641 09:59:35.698975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2642 09:59:35.699078 ==
2643 09:59:35.699147
2644 09:59:35.702464
2645 09:59:35.702552 TX Vref Scan disable
2646 09:59:35.705681 == TX Byte 0 ==
2647 09:59:35.709240 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2648 09:59:35.712328 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2649 09:59:35.715486 == TX Byte 1 ==
2650 09:59:35.718715 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2651 09:59:35.722126 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2652 09:59:35.722234 ==
2653 09:59:35.725786 Dram Type= 6, Freq= 0, CH_0, rank 0
2654 09:59:35.732361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2655 09:59:35.732483 ==
2656 09:59:35.743025 TX Vref=22, minBit 0, minWin=24, winSum=398
2657 09:59:35.746372 TX Vref=24, minBit 4, minWin=24, winSum=403
2658 09:59:35.749717 TX Vref=26, minBit 1, minWin=25, winSum=415
2659 09:59:35.753088 TX Vref=28, minBit 7, minWin=25, winSum=415
2660 09:59:35.756190 TX Vref=30, minBit 4, minWin=25, winSum=417
2661 09:59:35.759896 TX Vref=32, minBit 1, minWin=25, winSum=414
2662 09:59:35.766451 [TxChooseVref] Worse bit 4, Min win 25, Win sum 417, Final Vref 30
2663 09:59:35.766593
2664 09:59:35.769457 Final TX Range 1 Vref 30
2665 09:59:35.769548
2666 09:59:35.769640 ==
2667 09:59:35.773101 Dram Type= 6, Freq= 0, CH_0, rank 0
2668 09:59:35.776882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2669 09:59:35.776998 ==
2670 09:59:35.777064
2671 09:59:35.779804
2672 09:59:35.779888 TX Vref Scan disable
2673 09:59:35.783005 == TX Byte 0 ==
2674 09:59:35.786088 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2675 09:59:35.789734 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2676 09:59:35.792908 == TX Byte 1 ==
2677 09:59:35.796424 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2678 09:59:35.799603 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2679 09:59:35.802947
2680 09:59:35.803042 [DATLAT]
2681 09:59:35.803108 Freq=1200, CH0 RK0
2682 09:59:35.803169
2683 09:59:35.806185 DATLAT Default: 0xd
2684 09:59:35.806271 0, 0xFFFF, sum = 0
2685 09:59:35.809892 1, 0xFFFF, sum = 0
2686 09:59:35.809993 2, 0xFFFF, sum = 0
2687 09:59:35.812669 3, 0xFFFF, sum = 0
2688 09:59:35.816357 4, 0xFFFF, sum = 0
2689 09:59:35.816461 5, 0xFFFF, sum = 0
2690 09:59:35.819460 6, 0xFFFF, sum = 0
2691 09:59:35.819550 7, 0xFFFF, sum = 0
2692 09:59:35.822865 8, 0xFFFF, sum = 0
2693 09:59:35.822966 9, 0xFFFF, sum = 0
2694 09:59:35.826145 10, 0xFFFF, sum = 0
2695 09:59:35.826238 11, 0xFFFF, sum = 0
2696 09:59:35.830138 12, 0x0, sum = 1
2697 09:59:35.830231 13, 0x0, sum = 2
2698 09:59:35.830299 14, 0x0, sum = 3
2699 09:59:35.832947 15, 0x0, sum = 4
2700 09:59:35.833033 best_step = 13
2701 09:59:35.833097
2702 09:59:35.836582 ==
2703 09:59:35.836670 Dram Type= 6, Freq= 0, CH_0, rank 0
2704 09:59:35.843472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2705 09:59:35.843586 ==
2706 09:59:35.843655 RX Vref Scan: 1
2707 09:59:35.843716
2708 09:59:35.846307 Set Vref Range= 32 -> 127
2709 09:59:35.846394
2710 09:59:35.849860 RX Vref 32 -> 127, step: 1
2711 09:59:35.849951
2712 09:59:35.853288 RX Delay -13 -> 252, step: 4
2713 09:59:35.853376
2714 09:59:35.856763 Set Vref, RX VrefLevel [Byte0]: 32
2715 09:59:35.860191 [Byte1]: 32
2716 09:59:35.860290
2717 09:59:35.863367 Set Vref, RX VrefLevel [Byte0]: 33
2718 09:59:35.866475 [Byte1]: 33
2719 09:59:35.866603
2720 09:59:35.869566 Set Vref, RX VrefLevel [Byte0]: 34
2721 09:59:35.872702 [Byte1]: 34
2722 09:59:35.877028
2723 09:59:35.877162 Set Vref, RX VrefLevel [Byte0]: 35
2724 09:59:35.880694 [Byte1]: 35
2725 09:59:35.884829
2726 09:59:35.884970 Set Vref, RX VrefLevel [Byte0]: 36
2727 09:59:35.888307 [Byte1]: 36
2728 09:59:35.892858
2729 09:59:35.892973 Set Vref, RX VrefLevel [Byte0]: 37
2730 09:59:35.896490 [Byte1]: 37
2731 09:59:35.900651
2732 09:59:35.900764 Set Vref, RX VrefLevel [Byte0]: 38
2733 09:59:35.904134 [Byte1]: 38
2734 09:59:35.908878
2735 09:59:35.909006 Set Vref, RX VrefLevel [Byte0]: 39
2736 09:59:35.911841 [Byte1]: 39
2737 09:59:35.916841
2738 09:59:35.916970 Set Vref, RX VrefLevel [Byte0]: 40
2739 09:59:35.919655 [Byte1]: 40
2740 09:59:35.924364
2741 09:59:35.924479 Set Vref, RX VrefLevel [Byte0]: 41
2742 09:59:35.927951 [Byte1]: 41
2743 09:59:35.932491
2744 09:59:35.932666 Set Vref, RX VrefLevel [Byte0]: 42
2745 09:59:35.935390 [Byte1]: 42
2746 09:59:35.940236
2747 09:59:35.940369 Set Vref, RX VrefLevel [Byte0]: 43
2748 09:59:35.943309 [Byte1]: 43
2749 09:59:35.948373
2750 09:59:35.948498 Set Vref, RX VrefLevel [Byte0]: 44
2751 09:59:35.951590 [Byte1]: 44
2752 09:59:35.956352
2753 09:59:35.956484 Set Vref, RX VrefLevel [Byte0]: 45
2754 09:59:35.959299 [Byte1]: 45
2755 09:59:35.963853
2756 09:59:35.963977 Set Vref, RX VrefLevel [Byte0]: 46
2757 09:59:35.967170 [Byte1]: 46
2758 09:59:35.971809
2759 09:59:35.971940 Set Vref, RX VrefLevel [Byte0]: 47
2760 09:59:35.975456 [Byte1]: 47
2761 09:59:35.980040
2762 09:59:35.980160 Set Vref, RX VrefLevel [Byte0]: 48
2763 09:59:35.983181 [Byte1]: 48
2764 09:59:35.987735
2765 09:59:35.987862 Set Vref, RX VrefLevel [Byte0]: 49
2766 09:59:35.991049 [Byte1]: 49
2767 09:59:35.995540
2768 09:59:35.995662 Set Vref, RX VrefLevel [Byte0]: 50
2769 09:59:35.998462 [Byte1]: 50
2770 09:59:36.003578
2771 09:59:36.003731 Set Vref, RX VrefLevel [Byte0]: 51
2772 09:59:36.006638 [Byte1]: 51
2773 09:59:36.011617
2774 09:59:36.011762 Set Vref, RX VrefLevel [Byte0]: 52
2775 09:59:36.014631 [Byte1]: 52
2776 09:59:36.019020
2777 09:59:36.019158 Set Vref, RX VrefLevel [Byte0]: 53
2778 09:59:36.022213 [Byte1]: 53
2779 09:59:36.026864
2780 09:59:36.027001 Set Vref, RX VrefLevel [Byte0]: 54
2781 09:59:36.030291 [Byte1]: 54
2782 09:59:36.034698
2783 09:59:36.034821 Set Vref, RX VrefLevel [Byte0]: 55
2784 09:59:36.038054 [Byte1]: 55
2785 09:59:36.042956
2786 09:59:36.043112 Set Vref, RX VrefLevel [Byte0]: 56
2787 09:59:36.046446 [Byte1]: 56
2788 09:59:36.050968
2789 09:59:36.051099 Set Vref, RX VrefLevel [Byte0]: 57
2790 09:59:36.054015 [Byte1]: 57
2791 09:59:36.058940
2792 09:59:36.059050 Set Vref, RX VrefLevel [Byte0]: 58
2793 09:59:36.062083 [Byte1]: 58
2794 09:59:36.066329
2795 09:59:36.066427 Set Vref, RX VrefLevel [Byte0]: 59
2796 09:59:36.069968 [Byte1]: 59
2797 09:59:36.074708
2798 09:59:36.074850 Set Vref, RX VrefLevel [Byte0]: 60
2799 09:59:36.077827 [Byte1]: 60
2800 09:59:36.082130
2801 09:59:36.082231 Set Vref, RX VrefLevel [Byte0]: 61
2802 09:59:36.085312 [Byte1]: 61
2803 09:59:36.090091
2804 09:59:36.090194 Set Vref, RX VrefLevel [Byte0]: 62
2805 09:59:36.093543 [Byte1]: 62
2806 09:59:36.097892
2807 09:59:36.097989 Set Vref, RX VrefLevel [Byte0]: 63
2808 09:59:36.101309 [Byte1]: 63
2809 09:59:36.106302
2810 09:59:36.106410 Set Vref, RX VrefLevel [Byte0]: 64
2811 09:59:36.109069 [Byte1]: 64
2812 09:59:36.113881
2813 09:59:36.113988 Set Vref, RX VrefLevel [Byte0]: 65
2814 09:59:36.117384 [Byte1]: 65
2815 09:59:36.121504
2816 09:59:36.121685 Set Vref, RX VrefLevel [Byte0]: 66
2817 09:59:36.125193 [Byte1]: 66
2818 09:59:36.129412
2819 09:59:36.129548 Set Vref, RX VrefLevel [Byte0]: 67
2820 09:59:36.133050 [Byte1]: 67
2821 09:59:36.137236
2822 09:59:36.137358 Set Vref, RX VrefLevel [Byte0]: 68
2823 09:59:36.140627 [Byte1]: 68
2824 09:59:36.145315
2825 09:59:36.145423 Set Vref, RX VrefLevel [Byte0]: 69
2826 09:59:36.148574 [Byte1]: 69
2827 09:59:36.153058
2828 09:59:36.153156 Final RX Vref Byte 0 = 53 to rank0
2829 09:59:36.156463 Final RX Vref Byte 1 = 46 to rank0
2830 09:59:36.160013 Final RX Vref Byte 0 = 53 to rank1
2831 09:59:36.163233 Final RX Vref Byte 1 = 46 to rank1==
2832 09:59:36.166783 Dram Type= 6, Freq= 0, CH_0, rank 0
2833 09:59:36.173549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2834 09:59:36.173717 ==
2835 09:59:36.173810 DQS Delay:
2836 09:59:36.173892 DQS0 = 0, DQS1 = 0
2837 09:59:36.177022 DQM Delay:
2838 09:59:36.177109 DQM0 = 120, DQM1 = 110
2839 09:59:36.179863 DQ Delay:
2840 09:59:36.183381 DQ0 =120, DQ1 =122, DQ2 =118, DQ3 =118
2841 09:59:36.186872 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =128
2842 09:59:36.190098 DQ8 =98, DQ9 =98, DQ10 =112, DQ11 =102
2843 09:59:36.193790 DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =118
2844 09:59:36.193885
2845 09:59:36.193951
2846 09:59:36.199969 [DQSOSCAuto] RK0, (LSB)MR18= 0x140d, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 402 ps
2847 09:59:36.203347 CH0 RK0: MR19=404, MR18=140D
2848 09:59:36.209863 CH0_RK0: MR19=0x404, MR18=0x140D, DQSOSC=402, MR23=63, INC=40, DEC=27
2849 09:59:36.209994
2850 09:59:36.213523 ----->DramcWriteLeveling(PI) begin...
2851 09:59:36.213641 ==
2852 09:59:36.217115 Dram Type= 6, Freq= 0, CH_0, rank 1
2853 09:59:36.219789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2854 09:59:36.223172 ==
2855 09:59:36.223304 Write leveling (Byte 0): 33 => 33
2856 09:59:36.226606 Write leveling (Byte 1): 27 => 27
2857 09:59:36.229804 DramcWriteLeveling(PI) end<-----
2858 09:59:36.229898
2859 09:59:36.229965 ==
2860 09:59:36.233525 Dram Type= 6, Freq= 0, CH_0, rank 1
2861 09:59:36.239906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2862 09:59:36.240021 ==
2863 09:59:36.240091 [Gating] SW mode calibration
2864 09:59:36.250148 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2865 09:59:36.253280 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2866 09:59:36.256520 0 15 0 | B1->B0 | 3333 3131 | 1 1 | (1 1) (0 0)
2867 09:59:36.263538 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2868 09:59:36.266841 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2869 09:59:36.269698 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2870 09:59:36.276728 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2871 09:59:36.280002 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2872 09:59:36.283941 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 0)
2873 09:59:36.289992 0 15 28 | B1->B0 | 2d2d 2b2b | 0 0 | (0 1) (0 1)
2874 09:59:36.293348 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2875 09:59:36.296841 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2876 09:59:36.303529 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2877 09:59:36.306595 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2878 09:59:36.310307 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2879 09:59:36.316631 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2880 09:59:36.320048 1 0 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
2881 09:59:36.323595 1 0 28 | B1->B0 | 3b3b 3b3b | 0 0 | (0 0) (0 0)
2882 09:59:36.326715 1 1 0 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
2883 09:59:36.333847 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2884 09:59:36.336741 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2885 09:59:36.340295 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2886 09:59:36.347000 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2887 09:59:36.350034 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2888 09:59:36.353765 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2889 09:59:36.360629 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2890 09:59:36.363503 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2891 09:59:36.367218 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 09:59:36.373742 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 09:59:36.377063 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 09:59:36.380242 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 09:59:36.386848 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2896 09:59:36.390354 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2897 09:59:36.393294 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2898 09:59:36.400185 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2899 09:59:36.403906 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2900 09:59:36.406955 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2901 09:59:36.410045 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2902 09:59:36.417171 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2903 09:59:36.420084 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2904 09:59:36.423778 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2905 09:59:36.430463 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2906 09:59:36.433441 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2907 09:59:36.437093 Total UI for P1: 0, mck2ui 16
2908 09:59:36.440806 best dqsien dly found for B0: ( 1, 3, 26)
2909 09:59:36.443731 Total UI for P1: 0, mck2ui 16
2910 09:59:36.447412 best dqsien dly found for B1: ( 1, 3, 26)
2911 09:59:36.450665 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2912 09:59:36.453851 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
2913 09:59:36.453945
2914 09:59:36.457211 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2915 09:59:36.460107 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
2916 09:59:36.463777 [Gating] SW calibration Done
2917 09:59:36.463877 ==
2918 09:59:36.466918 Dram Type= 6, Freq= 0, CH_0, rank 1
2919 09:59:36.470545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2920 09:59:36.474156 ==
2921 09:59:36.474256 RX Vref Scan: 0
2922 09:59:36.474344
2923 09:59:36.476908 RX Vref 0 -> 0, step: 1
2924 09:59:36.476994
2925 09:59:36.477079 RX Delay -40 -> 252, step: 8
2926 09:59:36.484220 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2927 09:59:36.487389 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2928 09:59:36.491131 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2929 09:59:36.493843 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2930 09:59:36.497171 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2931 09:59:36.503872 iDelay=200, Bit 5, Center 119 (48 ~ 191) 144
2932 09:59:36.507506 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
2933 09:59:36.510704 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2934 09:59:36.513841 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2935 09:59:36.517678 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2936 09:59:36.524299 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2937 09:59:36.527605 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2938 09:59:36.530636 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2939 09:59:36.534263 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2940 09:59:36.537254 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2941 09:59:36.543756 iDelay=200, Bit 15, Center 119 (56 ~ 183) 128
2942 09:59:36.543879 ==
2943 09:59:36.547218 Dram Type= 6, Freq= 0, CH_0, rank 1
2944 09:59:36.550332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2945 09:59:36.550430 ==
2946 09:59:36.550497 DQS Delay:
2947 09:59:36.554087 DQS0 = 0, DQS1 = 0
2948 09:59:36.554235 DQM Delay:
2949 09:59:36.557232 DQM0 = 122, DQM1 = 112
2950 09:59:36.557327 DQ Delay:
2951 09:59:36.560587 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2952 09:59:36.563972 DQ4 =127, DQ5 =119, DQ6 =131, DQ7 =127
2953 09:59:36.567162 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2954 09:59:36.570688 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =119
2955 09:59:36.570783
2956 09:59:36.570849
2957 09:59:36.573744 ==
2958 09:59:36.577346 Dram Type= 6, Freq= 0, CH_0, rank 1
2959 09:59:36.580341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2960 09:59:36.580433 ==
2961 09:59:36.580500
2962 09:59:36.580560
2963 09:59:36.583832 TX Vref Scan disable
2964 09:59:36.583998 == TX Byte 0 ==
2965 09:59:36.587420 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2966 09:59:36.594446 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2967 09:59:36.594558 == TX Byte 1 ==
2968 09:59:36.597063 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2969 09:59:36.603788 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2970 09:59:36.603899 ==
2971 09:59:36.607197 Dram Type= 6, Freq= 0, CH_0, rank 1
2972 09:59:36.610797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2973 09:59:36.610900 ==
2974 09:59:36.623220 TX Vref=22, minBit 1, minWin=25, winSum=414
2975 09:59:36.626314 TX Vref=24, minBit 3, minWin=25, winSum=419
2976 09:59:36.630026 TX Vref=26, minBit 0, minWin=26, winSum=422
2977 09:59:36.632996 TX Vref=28, minBit 1, minWin=26, winSum=427
2978 09:59:36.636631 TX Vref=30, minBit 3, minWin=26, winSum=430
2979 09:59:36.639588 TX Vref=32, minBit 5, minWin=25, winSum=425
2980 09:59:36.646378 [TxChooseVref] Worse bit 3, Min win 26, Win sum 430, Final Vref 30
2981 09:59:36.646502
2982 09:59:36.649491 Final TX Range 1 Vref 30
2983 09:59:36.649589
2984 09:59:36.649658 ==
2985 09:59:36.653243 Dram Type= 6, Freq= 0, CH_0, rank 1
2986 09:59:36.656777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2987 09:59:36.656880 ==
2988 09:59:36.656947
2989 09:59:36.659631
2990 09:59:36.659720 TX Vref Scan disable
2991 09:59:36.662926 == TX Byte 0 ==
2992 09:59:36.666435 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2993 09:59:36.670039 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2994 09:59:36.673131 == TX Byte 1 ==
2995 09:59:36.676780 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2996 09:59:36.679654 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2997 09:59:36.679749
2998 09:59:36.683264 [DATLAT]
2999 09:59:36.683354 Freq=1200, CH0 RK1
3000 09:59:36.683419
3001 09:59:36.686346 DATLAT Default: 0xd
3002 09:59:36.686432 0, 0xFFFF, sum = 0
3003 09:59:36.689848 1, 0xFFFF, sum = 0
3004 09:59:36.689937 2, 0xFFFF, sum = 0
3005 09:59:36.693067 3, 0xFFFF, sum = 0
3006 09:59:36.693154 4, 0xFFFF, sum = 0
3007 09:59:36.696346 5, 0xFFFF, sum = 0
3008 09:59:36.696437 6, 0xFFFF, sum = 0
3009 09:59:36.700182 7, 0xFFFF, sum = 0
3010 09:59:36.700315 8, 0xFFFF, sum = 0
3011 09:59:36.703550 9, 0xFFFF, sum = 0
3012 09:59:36.703641 10, 0xFFFF, sum = 0
3013 09:59:36.706808 11, 0xFFFF, sum = 0
3014 09:59:36.706895 12, 0x0, sum = 1
3015 09:59:36.709912 13, 0x0, sum = 2
3016 09:59:36.710003 14, 0x0, sum = 3
3017 09:59:36.713733 15, 0x0, sum = 4
3018 09:59:36.713821 best_step = 13
3019 09:59:36.713887
3020 09:59:36.713948 ==
3021 09:59:36.716636 Dram Type= 6, Freq= 0, CH_0, rank 1
3022 09:59:36.723254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3023 09:59:36.723363 ==
3024 09:59:36.723432 RX Vref Scan: 0
3025 09:59:36.723494
3026 09:59:36.726528 RX Vref 0 -> 0, step: 1
3027 09:59:36.726616
3028 09:59:36.729883 RX Delay -13 -> 252, step: 4
3029 09:59:36.733097 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3030 09:59:36.736595 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3031 09:59:36.743305 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3032 09:59:36.746525 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3033 09:59:36.750189 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3034 09:59:36.753370 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3035 09:59:36.757049 iDelay=195, Bit 6, Center 126 (63 ~ 190) 128
3036 09:59:36.760016 iDelay=195, Bit 7, Center 128 (63 ~ 194) 132
3037 09:59:36.767046 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3038 09:59:36.770202 iDelay=195, Bit 9, Center 96 (31 ~ 162) 132
3039 09:59:36.773528 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3040 09:59:36.776682 iDelay=195, Bit 11, Center 102 (39 ~ 166) 128
3041 09:59:36.780470 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3042 09:59:36.787064 iDelay=195, Bit 13, Center 116 (55 ~ 178) 124
3043 09:59:36.790003 iDelay=195, Bit 14, Center 120 (59 ~ 182) 124
3044 09:59:36.793546 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3045 09:59:36.793688 ==
3046 09:59:36.796643 Dram Type= 6, Freq= 0, CH_0, rank 1
3047 09:59:36.800172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3048 09:59:36.803301 ==
3049 09:59:36.803392 DQS Delay:
3050 09:59:36.803457 DQS0 = 0, DQS1 = 0
3051 09:59:36.807009 DQM Delay:
3052 09:59:36.807097 DQM0 = 121, DQM1 = 109
3053 09:59:36.810401 DQ Delay:
3054 09:59:36.813647 DQ0 =118, DQ1 =122, DQ2 =118, DQ3 =118
3055 09:59:36.816796 DQ4 =122, DQ5 =116, DQ6 =126, DQ7 =128
3056 09:59:36.820078 DQ8 =100, DQ9 =96, DQ10 =110, DQ11 =102
3057 09:59:36.823959 DQ12 =114, DQ13 =116, DQ14 =120, DQ15 =118
3058 09:59:36.824052
3059 09:59:36.824119
3060 09:59:36.829970 [DQSOSCAuto] RK1, (LSB)MR18= 0xff0, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 404 ps
3061 09:59:36.833976 CH0 RK1: MR19=403, MR18=FF0
3062 09:59:36.840197 CH0_RK1: MR19=0x403, MR18=0xFF0, DQSOSC=404, MR23=63, INC=40, DEC=26
3063 09:59:36.843691 [RxdqsGatingPostProcess] freq 1200
3064 09:59:36.846775 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3065 09:59:36.850001 best DQS0 dly(2T, 0.5T) = (0, 11)
3066 09:59:36.854255 best DQS1 dly(2T, 0.5T) = (0, 11)
3067 09:59:36.857095 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3068 09:59:36.860090 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3069 09:59:36.864031 best DQS0 dly(2T, 0.5T) = (0, 11)
3070 09:59:36.866688 best DQS1 dly(2T, 0.5T) = (0, 11)
3071 09:59:36.870039 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3072 09:59:36.873489 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3073 09:59:36.877131 Pre-setting of DQS Precalculation
3074 09:59:36.880289 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3075 09:59:36.883604 ==
3076 09:59:36.883697 Dram Type= 6, Freq= 0, CH_1, rank 0
3077 09:59:36.890352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3078 09:59:36.890469 ==
3079 09:59:36.893493 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3080 09:59:36.900121 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3081 09:59:36.909104 [CA 0] Center 37 (7~68) winsize 62
3082 09:59:36.912862 [CA 1] Center 37 (7~68) winsize 62
3083 09:59:36.916447 [CA 2] Center 35 (5~65) winsize 61
3084 09:59:36.919493 [CA 3] Center 34 (4~64) winsize 61
3085 09:59:36.922943 [CA 4] Center 34 (4~64) winsize 61
3086 09:59:36.926019 [CA 5] Center 33 (3~63) winsize 61
3087 09:59:36.926116
3088 09:59:36.929545 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3089 09:59:36.929700
3090 09:59:36.932623 [CATrainingPosCal] consider 1 rank data
3091 09:59:36.935745 u2DelayCellTimex100 = 270/100 ps
3092 09:59:36.939133 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3093 09:59:36.942779 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3094 09:59:36.945874 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3095 09:59:36.952492 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3096 09:59:36.956119 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3097 09:59:36.959325 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3098 09:59:36.959425
3099 09:59:36.962546 CA PerBit enable=1, Macro0, CA PI delay=33
3100 09:59:36.962633
3101 09:59:36.966033 [CBTSetCACLKResult] CA Dly = 33
3102 09:59:36.966121 CS Dly: 7 (0~38)
3103 09:59:36.966186 ==
3104 09:59:36.969454 Dram Type= 6, Freq= 0, CH_1, rank 1
3105 09:59:36.976189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3106 09:59:36.976323 ==
3107 09:59:36.979663 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3108 09:59:36.985941 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3109 09:59:36.994876 [CA 0] Center 37 (7~68) winsize 62
3110 09:59:36.998163 [CA 1] Center 37 (7~68) winsize 62
3111 09:59:37.001785 [CA 2] Center 35 (5~65) winsize 61
3112 09:59:37.004678 [CA 3] Center 34 (4~65) winsize 62
3113 09:59:37.008153 [CA 4] Center 35 (5~65) winsize 61
3114 09:59:37.011762 [CA 5] Center 34 (4~64) winsize 61
3115 09:59:37.011869
3116 09:59:37.014649 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3117 09:59:37.014734
3118 09:59:37.018484 [CATrainingPosCal] consider 2 rank data
3119 09:59:37.021438 u2DelayCellTimex100 = 270/100 ps
3120 09:59:37.024718 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3121 09:59:37.027927 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3122 09:59:37.034993 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3123 09:59:37.038042 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3124 09:59:37.041336 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3125 09:59:37.044946 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3126 09:59:37.045044
3127 09:59:37.047993 CA PerBit enable=1, Macro0, CA PI delay=33
3128 09:59:37.048080
3129 09:59:37.051870 [CBTSetCACLKResult] CA Dly = 33
3130 09:59:37.051959 CS Dly: 8 (0~40)
3131 09:59:37.052024
3132 09:59:37.054757 ----->DramcWriteLeveling(PI) begin...
3133 09:59:37.058033 ==
3134 09:59:37.058119 Dram Type= 6, Freq= 0, CH_1, rank 0
3135 09:59:37.064604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3136 09:59:37.064709 ==
3137 09:59:37.068509 Write leveling (Byte 0): 25 => 25
3138 09:59:37.071440 Write leveling (Byte 1): 27 => 27
3139 09:59:37.071554 DramcWriteLeveling(PI) end<-----
3140 09:59:37.074878
3141 09:59:37.074983 ==
3142 09:59:37.078111 Dram Type= 6, Freq= 0, CH_1, rank 0
3143 09:59:37.081507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3144 09:59:37.081623 ==
3145 09:59:37.084883 [Gating] SW mode calibration
3146 09:59:37.092057 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3147 09:59:37.095304 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3148 09:59:37.102030 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3149 09:59:37.104920 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3150 09:59:37.108622 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3151 09:59:37.115258 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3152 09:59:37.118326 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3153 09:59:37.122249 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3154 09:59:37.128894 0 15 24 | B1->B0 | 3434 2e2e | 1 0 | (0 1) (0 1)
3155 09:59:37.131522 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
3156 09:59:37.135058 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3157 09:59:37.141488 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3158 09:59:37.145029 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3159 09:59:37.148220 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3160 09:59:37.152318 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3161 09:59:37.158626 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3162 09:59:37.161783 1 0 24 | B1->B0 | 2e2e 3939 | 0 0 | (1 1) (0 0)
3163 09:59:37.165074 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3164 09:59:37.171754 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3165 09:59:37.174965 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3166 09:59:37.178629 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3167 09:59:37.185332 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3168 09:59:37.188911 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3169 09:59:37.191780 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3170 09:59:37.198215 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3171 09:59:37.201803 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3172 09:59:37.205243 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 09:59:37.212056 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 09:59:37.215573 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 09:59:37.219050 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 09:59:37.225666 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 09:59:37.228649 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3178 09:59:37.231975 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3179 09:59:37.235637 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3180 09:59:37.241965 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3181 09:59:37.245570 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3182 09:59:37.248503 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3183 09:59:37.255583 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3184 09:59:37.258836 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3185 09:59:37.261995 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3186 09:59:37.268726 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3187 09:59:37.272294 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3188 09:59:37.275081 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3189 09:59:37.278632 Total UI for P1: 0, mck2ui 16
3190 09:59:37.282471 best dqsien dly found for B0: ( 1, 3, 28)
3191 09:59:37.285029 Total UI for P1: 0, mck2ui 16
3192 09:59:37.288552 best dqsien dly found for B1: ( 1, 3, 26)
3193 09:59:37.292215 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3194 09:59:37.295499 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3195 09:59:37.295592
3196 09:59:37.302124 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3197 09:59:37.305366 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3198 09:59:37.305463 [Gating] SW calibration Done
3199 09:59:37.308463 ==
3200 09:59:37.308550 Dram Type= 6, Freq= 0, CH_1, rank 0
3201 09:59:37.315181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3202 09:59:37.315297 ==
3203 09:59:37.315363 RX Vref Scan: 0
3204 09:59:37.315462
3205 09:59:37.318427 RX Vref 0 -> 0, step: 1
3206 09:59:37.318509
3207 09:59:37.321978 RX Delay -40 -> 252, step: 8
3208 09:59:37.325314 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3209 09:59:37.328643 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3210 09:59:37.332122 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3211 09:59:37.338999 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3212 09:59:37.342362 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3213 09:59:37.345538 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3214 09:59:37.348656 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3215 09:59:37.352213 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3216 09:59:37.355350 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3217 09:59:37.361958 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3218 09:59:37.365404 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3219 09:59:37.368847 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3220 09:59:37.372022 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3221 09:59:37.379023 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3222 09:59:37.382442 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3223 09:59:37.385827 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3224 09:59:37.385933 ==
3225 09:59:37.389102 Dram Type= 6, Freq= 0, CH_1, rank 0
3226 09:59:37.392147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3227 09:59:37.392245 ==
3228 09:59:37.395334 DQS Delay:
3229 09:59:37.395426 DQS0 = 0, DQS1 = 0
3230 09:59:37.399283 DQM Delay:
3231 09:59:37.399377 DQM0 = 119, DQM1 = 116
3232 09:59:37.399444 DQ Delay:
3233 09:59:37.402509 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3234 09:59:37.405814 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =119
3235 09:59:37.412110 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3236 09:59:37.415957 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3237 09:59:37.416065
3238 09:59:37.416132
3239 09:59:37.416192 ==
3240 09:59:37.418749 Dram Type= 6, Freq= 0, CH_1, rank 0
3241 09:59:37.422487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3242 09:59:37.422585 ==
3243 09:59:37.422651
3244 09:59:37.422711
3245 09:59:37.425492 TX Vref Scan disable
3246 09:59:37.425593 == TX Byte 0 ==
3247 09:59:37.432116 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3248 09:59:37.436051 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3249 09:59:37.436168 == TX Byte 1 ==
3250 09:59:37.442207 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3251 09:59:37.445889 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3252 09:59:37.446002 ==
3253 09:59:37.449408 Dram Type= 6, Freq= 0, CH_1, rank 0
3254 09:59:37.452122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3255 09:59:37.452242 ==
3256 09:59:37.464851 TX Vref=22, minBit 9, minWin=24, winSum=411
3257 09:59:37.468855 TX Vref=24, minBit 9, minWin=24, winSum=413
3258 09:59:37.471845 TX Vref=26, minBit 1, minWin=26, winSum=427
3259 09:59:37.474945 TX Vref=28, minBit 1, minWin=26, winSum=425
3260 09:59:37.478363 TX Vref=30, minBit 2, minWin=26, winSum=431
3261 09:59:37.481534 TX Vref=32, minBit 10, minWin=25, winSum=431
3262 09:59:37.488389 [TxChooseVref] Worse bit 2, Min win 26, Win sum 431, Final Vref 30
3263 09:59:37.488538
3264 09:59:37.492055 Final TX Range 1 Vref 30
3265 09:59:37.492189
3266 09:59:37.492285 ==
3267 09:59:37.495000 Dram Type= 6, Freq= 0, CH_1, rank 0
3268 09:59:37.498519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3269 09:59:37.498624 ==
3270 09:59:37.498698
3271 09:59:37.502078
3272 09:59:37.502248 TX Vref Scan disable
3273 09:59:37.505236 == TX Byte 0 ==
3274 09:59:37.508620 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3275 09:59:37.511592 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3276 09:59:37.515375 == TX Byte 1 ==
3277 09:59:37.519001 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3278 09:59:37.522107 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3279 09:59:37.522207
3280 09:59:37.525241 [DATLAT]
3281 09:59:37.525337 Freq=1200, CH1 RK0
3282 09:59:37.525404
3283 09:59:37.529046 DATLAT Default: 0xd
3284 09:59:37.529146 0, 0xFFFF, sum = 0
3285 09:59:37.532052 1, 0xFFFF, sum = 0
3286 09:59:37.532154 2, 0xFFFF, sum = 0
3287 09:59:37.535557 3, 0xFFFF, sum = 0
3288 09:59:37.535689 4, 0xFFFF, sum = 0
3289 09:59:37.538614 5, 0xFFFF, sum = 0
3290 09:59:37.538731 6, 0xFFFF, sum = 0
3291 09:59:37.541815 7, 0xFFFF, sum = 0
3292 09:59:37.541938 8, 0xFFFF, sum = 0
3293 09:59:37.544981 9, 0xFFFF, sum = 0
3294 09:59:37.548589 10, 0xFFFF, sum = 0
3295 09:59:37.548692 11, 0xFFFF, sum = 0
3296 09:59:37.551695 12, 0x0, sum = 1
3297 09:59:37.551810 13, 0x0, sum = 2
3298 09:59:37.551916 14, 0x0, sum = 3
3299 09:59:37.555456 15, 0x0, sum = 4
3300 09:59:37.555571 best_step = 13
3301 09:59:37.555705
3302 09:59:37.555799 ==
3303 09:59:37.558306 Dram Type= 6, Freq= 0, CH_1, rank 0
3304 09:59:37.565403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3305 09:59:37.565572 ==
3306 09:59:37.565692 RX Vref Scan: 1
3307 09:59:37.565774
3308 09:59:37.568475 Set Vref Range= 32 -> 127
3309 09:59:37.568591
3310 09:59:37.571829 RX Vref 32 -> 127, step: 1
3311 09:59:37.571967
3312 09:59:37.572093 RX Delay -5 -> 252, step: 4
3313 09:59:37.575365
3314 09:59:37.575485 Set Vref, RX VrefLevel [Byte0]: 32
3315 09:59:37.578770 [Byte1]: 32
3316 09:59:37.582993
3317 09:59:37.583165 Set Vref, RX VrefLevel [Byte0]: 33
3318 09:59:37.586444 [Byte1]: 33
3319 09:59:37.590862
3320 09:59:37.591001 Set Vref, RX VrefLevel [Byte0]: 34
3321 09:59:37.594516 [Byte1]: 34
3322 09:59:37.598890
3323 09:59:37.599039 Set Vref, RX VrefLevel [Byte0]: 35
3324 09:59:37.602471 [Byte1]: 35
3325 09:59:37.606655
3326 09:59:37.606799 Set Vref, RX VrefLevel [Byte0]: 36
3327 09:59:37.609936 [Byte1]: 36
3328 09:59:37.614400
3329 09:59:37.614550 Set Vref, RX VrefLevel [Byte0]: 37
3330 09:59:37.617954 [Byte1]: 37
3331 09:59:37.622902
3332 09:59:37.623033 Set Vref, RX VrefLevel [Byte0]: 38
3333 09:59:37.625802 [Byte1]: 38
3334 09:59:37.630169
3335 09:59:37.630286 Set Vref, RX VrefLevel [Byte0]: 39
3336 09:59:37.634187 [Byte1]: 39
3337 09:59:37.637957
3338 09:59:37.638060 Set Vref, RX VrefLevel [Byte0]: 40
3339 09:59:37.641573 [Byte1]: 40
3340 09:59:37.646017
3341 09:59:37.646138 Set Vref, RX VrefLevel [Byte0]: 41
3342 09:59:37.649148 [Byte1]: 41
3343 09:59:37.653972
3344 09:59:37.654095 Set Vref, RX VrefLevel [Byte0]: 42
3345 09:59:37.657569 [Byte1]: 42
3346 09:59:37.661815
3347 09:59:37.661934 Set Vref, RX VrefLevel [Byte0]: 43
3348 09:59:37.665006 [Byte1]: 43
3349 09:59:37.669888
3350 09:59:37.670036 Set Vref, RX VrefLevel [Byte0]: 44
3351 09:59:37.672822 [Byte1]: 44
3352 09:59:37.677338
3353 09:59:37.677453 Set Vref, RX VrefLevel [Byte0]: 45
3354 09:59:37.680575 [Byte1]: 45
3355 09:59:37.685102
3356 09:59:37.685253 Set Vref, RX VrefLevel [Byte0]: 46
3357 09:59:37.688364 [Byte1]: 46
3358 09:59:37.693001
3359 09:59:37.693125 Set Vref, RX VrefLevel [Byte0]: 47
3360 09:59:37.696367 [Byte1]: 47
3361 09:59:37.701109
3362 09:59:37.701237 Set Vref, RX VrefLevel [Byte0]: 48
3363 09:59:37.704434 [Byte1]: 48
3364 09:59:37.709305
3365 09:59:37.709457 Set Vref, RX VrefLevel [Byte0]: 49
3366 09:59:37.712284 [Byte1]: 49
3367 09:59:37.716512
3368 09:59:37.716698 Set Vref, RX VrefLevel [Byte0]: 50
3369 09:59:37.719761 [Byte1]: 50
3370 09:59:37.724646
3371 09:59:37.724764 Set Vref, RX VrefLevel [Byte0]: 51
3372 09:59:37.727670 [Byte1]: 51
3373 09:59:37.732410
3374 09:59:37.732531 Set Vref, RX VrefLevel [Byte0]: 52
3375 09:59:37.735963 [Byte1]: 52
3376 09:59:37.740314
3377 09:59:37.740423 Set Vref, RX VrefLevel [Byte0]: 53
3378 09:59:37.743938 [Byte1]: 53
3379 09:59:37.748175
3380 09:59:37.748287 Set Vref, RX VrefLevel [Byte0]: 54
3381 09:59:37.751566 [Byte1]: 54
3382 09:59:37.756242
3383 09:59:37.756356 Set Vref, RX VrefLevel [Byte0]: 55
3384 09:59:37.759443 [Byte1]: 55
3385 09:59:37.764210
3386 09:59:37.764331 Set Vref, RX VrefLevel [Byte0]: 56
3387 09:59:37.767167 [Byte1]: 56
3388 09:59:37.771642
3389 09:59:37.771752 Set Vref, RX VrefLevel [Byte0]: 57
3390 09:59:37.774850 [Byte1]: 57
3391 09:59:37.779958
3392 09:59:37.780076 Set Vref, RX VrefLevel [Byte0]: 58
3393 09:59:37.782821 [Byte1]: 58
3394 09:59:37.787122
3395 09:59:37.787307 Set Vref, RX VrefLevel [Byte0]: 59
3396 09:59:37.790466 [Byte1]: 59
3397 09:59:37.795305
3398 09:59:37.795415 Set Vref, RX VrefLevel [Byte0]: 60
3399 09:59:37.798686 [Byte1]: 60
3400 09:59:37.802843
3401 09:59:37.802949 Set Vref, RX VrefLevel [Byte0]: 61
3402 09:59:37.806114 [Byte1]: 61
3403 09:59:37.811053
3404 09:59:37.811167 Set Vref, RX VrefLevel [Byte0]: 62
3405 09:59:37.814169 [Byte1]: 62
3406 09:59:37.818881
3407 09:59:37.819020 Set Vref, RX VrefLevel [Byte0]: 63
3408 09:59:37.821878 [Byte1]: 63
3409 09:59:37.826547
3410 09:59:37.826673 Set Vref, RX VrefLevel [Byte0]: 64
3411 09:59:37.829762 [Byte1]: 64
3412 09:59:37.834402
3413 09:59:37.834507 Set Vref, RX VrefLevel [Byte0]: 65
3414 09:59:37.838106 [Byte1]: 65
3415 09:59:37.842467
3416 09:59:37.842567 Set Vref, RX VrefLevel [Byte0]: 66
3417 09:59:37.845501 [Byte1]: 66
3418 09:59:37.850097
3419 09:59:37.850208 Set Vref, RX VrefLevel [Byte0]: 67
3420 09:59:37.853926 [Byte1]: 67
3421 09:59:37.858069
3422 09:59:37.858171 Set Vref, RX VrefLevel [Byte0]: 68
3423 09:59:37.861202 [Byte1]: 68
3424 09:59:37.866031
3425 09:59:37.866144 Final RX Vref Byte 0 = 56 to rank0
3426 09:59:37.869197 Final RX Vref Byte 1 = 49 to rank0
3427 09:59:37.872893 Final RX Vref Byte 0 = 56 to rank1
3428 09:59:37.875818 Final RX Vref Byte 1 = 49 to rank1==
3429 09:59:37.878872 Dram Type= 6, Freq= 0, CH_1, rank 0
3430 09:59:37.886094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3431 09:59:37.886217 ==
3432 09:59:37.886287 DQS Delay:
3433 09:59:37.886348 DQS0 = 0, DQS1 = 0
3434 09:59:37.889135 DQM Delay:
3435 09:59:37.889224 DQM0 = 120, DQM1 = 116
3436 09:59:37.892762 DQ Delay:
3437 09:59:37.895829 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =118
3438 09:59:37.899019 DQ4 =120, DQ5 =128, DQ6 =128, DQ7 =120
3439 09:59:37.902524 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =108
3440 09:59:37.905953 DQ12 =122, DQ13 =124, DQ14 =124, DQ15 =126
3441 09:59:37.906055
3442 09:59:37.906120
3443 09:59:37.912616 [DQSOSCAuto] RK0, (LSB)MR18= 0x13, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 410 ps
3444 09:59:37.915820 CH1 RK0: MR19=404, MR18=13
3445 09:59:37.922524 CH1_RK0: MR19=0x404, MR18=0x13, DQSOSC=402, MR23=63, INC=40, DEC=27
3446 09:59:37.922652
3447 09:59:37.925933 ----->DramcWriteLeveling(PI) begin...
3448 09:59:37.926026 ==
3449 09:59:37.929750 Dram Type= 6, Freq= 0, CH_1, rank 1
3450 09:59:37.932568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3451 09:59:37.932664 ==
3452 09:59:37.936198 Write leveling (Byte 0): 26 => 26
3453 09:59:37.939744 Write leveling (Byte 1): 28 => 28
3454 09:59:37.942859 DramcWriteLeveling(PI) end<-----
3455 09:59:37.943003
3456 09:59:37.943069 ==
3457 09:59:37.946543 Dram Type= 6, Freq= 0, CH_1, rank 1
3458 09:59:37.949499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3459 09:59:37.949667 ==
3460 09:59:37.953003 [Gating] SW mode calibration
3461 09:59:37.959221 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3462 09:59:37.966254 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3463 09:59:37.969193 0 15 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3464 09:59:37.975749 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3465 09:59:37.979572 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3466 09:59:37.983101 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3467 09:59:37.989816 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3468 09:59:37.993036 0 15 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3469 09:59:37.996096 0 15 24 | B1->B0 | 2d2d 3434 | 1 1 | (1 0) (1 1)
3470 09:59:37.999216 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3471 09:59:38.005955 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3472 09:59:38.009246 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3473 09:59:38.012788 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3474 09:59:38.019566 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3475 09:59:38.022848 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3476 09:59:38.026370 1 0 20 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
3477 09:59:38.032477 1 0 24 | B1->B0 | 3e3e 2e2e | 0 0 | (0 0) (0 0)
3478 09:59:38.035949 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3479 09:59:38.039670 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3480 09:59:38.046066 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3481 09:59:38.049322 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3482 09:59:38.052485 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3483 09:59:38.059275 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3484 09:59:38.062847 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3485 09:59:38.065894 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3486 09:59:38.072484 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3487 09:59:38.076195 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 09:59:38.079233 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 09:59:38.085598 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3490 09:59:38.089535 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3491 09:59:38.092416 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 09:59:38.099399 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3493 09:59:38.102435 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3494 09:59:38.106289 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3495 09:59:38.112446 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3496 09:59:38.115518 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3497 09:59:38.119228 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3498 09:59:38.125552 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3499 09:59:38.128739 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3500 09:59:38.132465 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3501 09:59:38.139086 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3502 09:59:38.141912 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3503 09:59:38.145140 Total UI for P1: 0, mck2ui 16
3504 09:59:38.148934 best dqsien dly found for B1: ( 1, 3, 22)
3505 09:59:38.152468 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3506 09:59:38.155567 Total UI for P1: 0, mck2ui 16
3507 09:59:38.158869 best dqsien dly found for B0: ( 1, 3, 26)
3508 09:59:38.162093 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3509 09:59:38.165554 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3510 09:59:38.165769
3511 09:59:38.169063 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3512 09:59:38.175844 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3513 09:59:38.175997 [Gating] SW calibration Done
3514 09:59:38.176131 ==
3515 09:59:38.178605 Dram Type= 6, Freq= 0, CH_1, rank 1
3516 09:59:38.185165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3517 09:59:38.185287 ==
3518 09:59:38.185355 RX Vref Scan: 0
3519 09:59:38.185415
3520 09:59:38.188790 RX Vref 0 -> 0, step: 1
3521 09:59:38.188912
3522 09:59:38.192503 RX Delay -40 -> 252, step: 8
3523 09:59:38.195561 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3524 09:59:38.198579 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3525 09:59:38.202181 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3526 09:59:38.208832 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3527 09:59:38.212066 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3528 09:59:38.214996 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3529 09:59:38.218714 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3530 09:59:38.221877 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3531 09:59:38.225303 iDelay=200, Bit 8, Center 107 (40 ~ 175) 136
3532 09:59:38.231993 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3533 09:59:38.235618 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3534 09:59:38.238684 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3535 09:59:38.241938 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3536 09:59:38.248409 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3537 09:59:38.251898 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3538 09:59:38.255394 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3539 09:59:38.255550 ==
3540 09:59:38.258757 Dram Type= 6, Freq= 0, CH_1, rank 1
3541 09:59:38.261883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3542 09:59:38.262008 ==
3543 09:59:38.265846 DQS Delay:
3544 09:59:38.265944 DQS0 = 0, DQS1 = 0
3545 09:59:38.266011 DQM Delay:
3546 09:59:38.268634 DQM0 = 120, DQM1 = 118
3547 09:59:38.268720 DQ Delay:
3548 09:59:38.272204 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3549 09:59:38.275658 DQ4 =115, DQ5 =131, DQ6 =131, DQ7 =123
3550 09:59:38.279155 DQ8 =107, DQ9 =107, DQ10 =115, DQ11 =115
3551 09:59:38.285374 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3552 09:59:38.285481
3553 09:59:38.285548
3554 09:59:38.285646 ==
3555 09:59:38.288878 Dram Type= 6, Freq= 0, CH_1, rank 1
3556 09:59:38.291968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3557 09:59:38.292074 ==
3558 09:59:38.292155
3559 09:59:38.292245
3560 09:59:38.295732 TX Vref Scan disable
3561 09:59:38.295825 == TX Byte 0 ==
3562 09:59:38.302339 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3563 09:59:38.305423 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3564 09:59:38.305552 == TX Byte 1 ==
3565 09:59:38.312215 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3566 09:59:38.315380 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3567 09:59:38.315498 ==
3568 09:59:38.318548 Dram Type= 6, Freq= 0, CH_1, rank 1
3569 09:59:38.322382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3570 09:59:38.322500 ==
3571 09:59:38.334550 TX Vref=22, minBit 10, minWin=25, winSum=420
3572 09:59:38.338084 TX Vref=24, minBit 2, minWin=26, winSum=422
3573 09:59:38.341843 TX Vref=26, minBit 2, minWin=26, winSum=425
3574 09:59:38.344580 TX Vref=28, minBit 9, minWin=26, winSum=434
3575 09:59:38.348024 TX Vref=30, minBit 9, minWin=26, winSum=434
3576 09:59:38.354870 TX Vref=32, minBit 9, minWin=26, winSum=434
3577 09:59:38.358067 [TxChooseVref] Worse bit 9, Min win 26, Win sum 434, Final Vref 28
3578 09:59:38.358177
3579 09:59:38.361507 Final TX Range 1 Vref 28
3580 09:59:38.361635
3581 09:59:38.361702 ==
3582 09:59:38.364405 Dram Type= 6, Freq= 0, CH_1, rank 1
3583 09:59:38.367673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3584 09:59:38.367786 ==
3585 09:59:38.371371
3586 09:59:38.371465
3587 09:59:38.371533 TX Vref Scan disable
3588 09:59:38.374556 == TX Byte 0 ==
3589 09:59:38.378140 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3590 09:59:38.381139 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3591 09:59:38.384704 == TX Byte 1 ==
3592 09:59:38.387898 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3593 09:59:38.391802 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3594 09:59:38.391933
3595 09:59:38.394714 [DATLAT]
3596 09:59:38.394825 Freq=1200, CH1 RK1
3597 09:59:38.394906
3598 09:59:38.398200 DATLAT Default: 0xd
3599 09:59:38.398310 0, 0xFFFF, sum = 0
3600 09:59:38.401343 1, 0xFFFF, sum = 0
3601 09:59:38.401436 2, 0xFFFF, sum = 0
3602 09:59:38.404550 3, 0xFFFF, sum = 0
3603 09:59:38.404643 4, 0xFFFF, sum = 0
3604 09:59:38.408254 5, 0xFFFF, sum = 0
3605 09:59:38.408350 6, 0xFFFF, sum = 0
3606 09:59:38.411206 7, 0xFFFF, sum = 0
3607 09:59:38.414735 8, 0xFFFF, sum = 0
3608 09:59:38.414839 9, 0xFFFF, sum = 0
3609 09:59:38.417611 10, 0xFFFF, sum = 0
3610 09:59:38.417721 11, 0xFFFF, sum = 0
3611 09:59:38.421248 12, 0x0, sum = 1
3612 09:59:38.421340 13, 0x0, sum = 2
3613 09:59:38.424505 14, 0x0, sum = 3
3614 09:59:38.424596 15, 0x0, sum = 4
3615 09:59:38.424663 best_step = 13
3616 09:59:38.424722
3617 09:59:38.427609 ==
3618 09:59:38.430923 Dram Type= 6, Freq= 0, CH_1, rank 1
3619 09:59:38.434798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3620 09:59:38.434896 ==
3621 09:59:38.434964 RX Vref Scan: 0
3622 09:59:38.435024
3623 09:59:38.438019 RX Vref 0 -> 0, step: 1
3624 09:59:38.438124
3625 09:59:38.441141 RX Delay -5 -> 252, step: 4
3626 09:59:38.444874 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3627 09:59:38.450660 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3628 09:59:38.454431 iDelay=195, Bit 2, Center 112 (51 ~ 174) 124
3629 09:59:38.457425 iDelay=195, Bit 3, Center 116 (59 ~ 174) 116
3630 09:59:38.460961 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3631 09:59:38.463976 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3632 09:59:38.467883 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3633 09:59:38.474009 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3634 09:59:38.477939 iDelay=195, Bit 8, Center 104 (43 ~ 166) 124
3635 09:59:38.481183 iDelay=195, Bit 9, Center 106 (47 ~ 166) 120
3636 09:59:38.484050 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3637 09:59:38.491310 iDelay=195, Bit 11, Center 112 (51 ~ 174) 124
3638 09:59:38.493963 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3639 09:59:38.497379 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3640 09:59:38.501113 iDelay=195, Bit 14, Center 122 (63 ~ 182) 120
3641 09:59:38.504383 iDelay=195, Bit 15, Center 126 (67 ~ 186) 120
3642 09:59:38.507313 ==
3643 09:59:38.507424 Dram Type= 6, Freq= 0, CH_1, rank 1
3644 09:59:38.514046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3645 09:59:38.514176 ==
3646 09:59:38.514245 DQS Delay:
3647 09:59:38.517204 DQS0 = 0, DQS1 = 0
3648 09:59:38.517302 DQM Delay:
3649 09:59:38.520873 DQM0 = 120, DQM1 = 117
3650 09:59:38.520975 DQ Delay:
3651 09:59:38.523899 DQ0 =122, DQ1 =116, DQ2 =112, DQ3 =116
3652 09:59:38.527290 DQ4 =116, DQ5 =130, DQ6 =130, DQ7 =120
3653 09:59:38.531071 DQ8 =104, DQ9 =106, DQ10 =116, DQ11 =112
3654 09:59:38.534231 DQ12 =126, DQ13 =124, DQ14 =122, DQ15 =126
3655 09:59:38.534337
3656 09:59:38.534427
3657 09:59:38.544465 [DQSOSCAuto] RK1, (LSB)MR18= 0xeec, (MSB)MR19= 0x403, tDQSOscB0 = 418 ps tDQSOscB1 = 404 ps
3658 09:59:38.544598 CH1 RK1: MR19=403, MR18=EEC
3659 09:59:38.550636 CH1_RK1: MR19=0x403, MR18=0xEEC, DQSOSC=404, MR23=63, INC=40, DEC=26
3660 09:59:38.553750 [RxdqsGatingPostProcess] freq 1200
3661 09:59:38.560905 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3662 09:59:38.563845 best DQS0 dly(2T, 0.5T) = (0, 11)
3663 09:59:38.567573 best DQS1 dly(2T, 0.5T) = (0, 11)
3664 09:59:38.570611 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3665 09:59:38.574054 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3666 09:59:38.577612 best DQS0 dly(2T, 0.5T) = (0, 11)
3667 09:59:38.577717 best DQS1 dly(2T, 0.5T) = (0, 11)
3668 09:59:38.580470 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3669 09:59:38.583574 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3670 09:59:38.587442 Pre-setting of DQS Precalculation
3671 09:59:38.593762 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3672 09:59:38.600210 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3673 09:59:38.607222 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3674 09:59:38.607342
3675 09:59:38.607417
3676 09:59:38.610736 [Calibration Summary] 2400 Mbps
3677 09:59:38.613795 CH 0, Rank 0
3678 09:59:38.613897 SW Impedance : PASS
3679 09:59:38.616854 DUTY Scan : NO K
3680 09:59:38.616930 ZQ Calibration : PASS
3681 09:59:38.620494 Jitter Meter : NO K
3682 09:59:38.623561 CBT Training : PASS
3683 09:59:38.623663 Write leveling : PASS
3684 09:59:38.627120 RX DQS gating : PASS
3685 09:59:38.630657 RX DQ/DQS(RDDQC) : PASS
3686 09:59:38.630768 TX DQ/DQS : PASS
3687 09:59:38.634056 RX DATLAT : PASS
3688 09:59:38.637135 RX DQ/DQS(Engine): PASS
3689 09:59:38.637237 TX OE : NO K
3690 09:59:38.640206 All Pass.
3691 09:59:38.640307
3692 09:59:38.640374 CH 0, Rank 1
3693 09:59:38.643987 SW Impedance : PASS
3694 09:59:38.644089 DUTY Scan : NO K
3695 09:59:38.647553 ZQ Calibration : PASS
3696 09:59:38.650654 Jitter Meter : NO K
3697 09:59:38.650768 CBT Training : PASS
3698 09:59:38.654170 Write leveling : PASS
3699 09:59:38.654268 RX DQS gating : PASS
3700 09:59:38.657052 RX DQ/DQS(RDDQC) : PASS
3701 09:59:38.660764 TX DQ/DQS : PASS
3702 09:59:38.660870 RX DATLAT : PASS
3703 09:59:38.663728 RX DQ/DQS(Engine): PASS
3704 09:59:38.667117 TX OE : NO K
3705 09:59:38.667223 All Pass.
3706 09:59:38.667290
3707 09:59:38.667350 CH 1, Rank 0
3708 09:59:38.670650 SW Impedance : PASS
3709 09:59:38.673633 DUTY Scan : NO K
3710 09:59:38.673731 ZQ Calibration : PASS
3711 09:59:38.677096 Jitter Meter : NO K
3712 09:59:38.680538 CBT Training : PASS
3713 09:59:38.680630 Write leveling : PASS
3714 09:59:38.683661 RX DQS gating : PASS
3715 09:59:38.686872 RX DQ/DQS(RDDQC) : PASS
3716 09:59:38.686962 TX DQ/DQS : PASS
3717 09:59:38.690447 RX DATLAT : PASS
3718 09:59:38.693399 RX DQ/DQS(Engine): PASS
3719 09:59:38.693486 TX OE : NO K
3720 09:59:38.696924 All Pass.
3721 09:59:38.697013
3722 09:59:38.697078 CH 1, Rank 1
3723 09:59:38.700198 SW Impedance : PASS
3724 09:59:38.700284 DUTY Scan : NO K
3725 09:59:38.703614 ZQ Calibration : PASS
3726 09:59:38.707026 Jitter Meter : NO K
3727 09:59:38.707119 CBT Training : PASS
3728 09:59:38.709965 Write leveling : PASS
3729 09:59:38.710053 RX DQS gating : PASS
3730 09:59:38.713818 RX DQ/DQS(RDDQC) : PASS
3731 09:59:38.717036 TX DQ/DQS : PASS
3732 09:59:38.717132 RX DATLAT : PASS
3733 09:59:38.720060 RX DQ/DQS(Engine): PASS
3734 09:59:38.723573 TX OE : NO K
3735 09:59:38.723670 All Pass.
3736 09:59:38.723758
3737 09:59:38.726826 DramC Write-DBI off
3738 09:59:38.726982 PER_BANK_REFRESH: Hybrid Mode
3739 09:59:38.730447 TX_TRACKING: ON
3740 09:59:38.740052 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3741 09:59:38.743412 [FAST_K] Save calibration result to emmc
3742 09:59:38.746558 dramc_set_vcore_voltage set vcore to 650000
3743 09:59:38.746668 Read voltage for 600, 5
3744 09:59:38.750208 Vio18 = 0
3745 09:59:38.750308 Vcore = 650000
3746 09:59:38.750396 Vdram = 0
3747 09:59:38.753372 Vddq = 0
3748 09:59:38.753465 Vmddr = 0
3749 09:59:38.756518 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3750 09:59:38.763290 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3751 09:59:38.766644 MEM_TYPE=3, freq_sel=19
3752 09:59:38.770328 sv_algorithm_assistance_LP4_1600
3753 09:59:38.773309 ============ PULL DRAM RESETB DOWN ============
3754 09:59:38.776649 ========== PULL DRAM RESETB DOWN end =========
3755 09:59:38.783570 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3756 09:59:38.786714 ===================================
3757 09:59:38.786891 LPDDR4 DRAM CONFIGURATION
3758 09:59:38.789847 ===================================
3759 09:59:38.793474 EX_ROW_EN[0] = 0x0
3760 09:59:38.793616 EX_ROW_EN[1] = 0x0
3761 09:59:38.796775 LP4Y_EN = 0x0
3762 09:59:38.796860 WORK_FSP = 0x0
3763 09:59:38.799675 WL = 0x2
3764 09:59:38.802924 RL = 0x2
3765 09:59:38.803016 BL = 0x2
3766 09:59:38.806380 RPST = 0x0
3767 09:59:38.806468 RD_PRE = 0x0
3768 09:59:38.809849 WR_PRE = 0x1
3769 09:59:38.809970 WR_PST = 0x0
3770 09:59:38.812951 DBI_WR = 0x0
3771 09:59:38.813133 DBI_RD = 0x0
3772 09:59:38.816806 OTF = 0x1
3773 09:59:38.819604 ===================================
3774 09:59:38.823417 ===================================
3775 09:59:38.823596 ANA top config
3776 09:59:38.826212 ===================================
3777 09:59:38.830148 DLL_ASYNC_EN = 0
3778 09:59:38.833466 ALL_SLAVE_EN = 1
3779 09:59:38.833694 NEW_RANK_MODE = 1
3780 09:59:38.836632 DLL_IDLE_MODE = 1
3781 09:59:38.839515 LP45_APHY_COMB_EN = 1
3782 09:59:38.842878 TX_ODT_DIS = 1
3783 09:59:38.843026 NEW_8X_MODE = 1
3784 09:59:38.846510 ===================================
3785 09:59:38.849435 ===================================
3786 09:59:38.852893 data_rate = 1200
3787 09:59:38.856704 CKR = 1
3788 09:59:38.859982 DQ_P2S_RATIO = 8
3789 09:59:38.863045 ===================================
3790 09:59:38.866163 CA_P2S_RATIO = 8
3791 09:59:38.869326 DQ_CA_OPEN = 0
3792 09:59:38.873105 DQ_SEMI_OPEN = 0
3793 09:59:38.873244 CA_SEMI_OPEN = 0
3794 09:59:38.876215 CA_FULL_RATE = 0
3795 09:59:38.879524 DQ_CKDIV4_EN = 1
3796 09:59:38.882715 CA_CKDIV4_EN = 1
3797 09:59:38.886162 CA_PREDIV_EN = 0
3798 09:59:38.886304 PH8_DLY = 0
3799 09:59:38.889750 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3800 09:59:38.892702 DQ_AAMCK_DIV = 4
3801 09:59:38.895972 CA_AAMCK_DIV = 4
3802 09:59:38.899506 CA_ADMCK_DIV = 4
3803 09:59:38.902753 DQ_TRACK_CA_EN = 0
3804 09:59:38.906164 CA_PICK = 600
3805 09:59:38.906262 CA_MCKIO = 600
3806 09:59:38.909184 MCKIO_SEMI = 0
3807 09:59:38.912958 PLL_FREQ = 2288
3808 09:59:38.916069 DQ_UI_PI_RATIO = 32
3809 09:59:38.919019 CA_UI_PI_RATIO = 0
3810 09:59:38.922637 ===================================
3811 09:59:38.926197 ===================================
3812 09:59:38.929461 memory_type:LPDDR4
3813 09:59:38.929652 GP_NUM : 10
3814 09:59:38.932596 SRAM_EN : 1
3815 09:59:38.932699 MD32_EN : 0
3816 09:59:38.936021 ===================================
3817 09:59:38.939207 [ANA_INIT] >>>>>>>>>>>>>>
3818 09:59:38.942442 <<<<<< [CONFIGURE PHASE]: ANA_TX
3819 09:59:38.946047 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3820 09:59:38.949123 ===================================
3821 09:59:38.952416 data_rate = 1200,PCW = 0X5800
3822 09:59:38.955802 ===================================
3823 09:59:38.958993 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3824 09:59:38.962346 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3825 09:59:38.969282 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3826 09:59:38.976065 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3827 09:59:38.979428 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3828 09:59:38.982442 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3829 09:59:38.982546 [ANA_INIT] flow start
3830 09:59:38.985772 [ANA_INIT] PLL >>>>>>>>
3831 09:59:38.989262 [ANA_INIT] PLL <<<<<<<<
3832 09:59:38.989367 [ANA_INIT] MIDPI >>>>>>>>
3833 09:59:38.992453 [ANA_INIT] MIDPI <<<<<<<<
3834 09:59:38.996062 [ANA_INIT] DLL >>>>>>>>
3835 09:59:38.996164 [ANA_INIT] flow end
3836 09:59:39.002612 ============ LP4 DIFF to SE enter ============
3837 09:59:39.005705 ============ LP4 DIFF to SE exit ============
3838 09:59:39.005808 [ANA_INIT] <<<<<<<<<<<<<
3839 09:59:39.008817 [Flow] Enable top DCM control >>>>>
3840 09:59:39.012161 [Flow] Enable top DCM control <<<<<
3841 09:59:39.015939 Enable DLL master slave shuffle
3842 09:59:39.022592 ==============================================================
3843 09:59:39.025408 Gating Mode config
3844 09:59:39.028700 ==============================================================
3845 09:59:39.032230 Config description:
3846 09:59:39.042163 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3847 09:59:39.048951 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3848 09:59:39.052738 SELPH_MODE 0: By rank 1: By Phase
3849 09:59:39.058860 ==============================================================
3850 09:59:39.062548 GAT_TRACK_EN = 1
3851 09:59:39.065909 RX_GATING_MODE = 2
3852 09:59:39.066014 RX_GATING_TRACK_MODE = 2
3853 09:59:39.069086 SELPH_MODE = 1
3854 09:59:39.072141 PICG_EARLY_EN = 1
3855 09:59:39.075475 VALID_LAT_VALUE = 1
3856 09:59:39.082434 ==============================================================
3857 09:59:39.085478 Enter into Gating configuration >>>>
3858 09:59:39.089048 Exit from Gating configuration <<<<
3859 09:59:39.092302 Enter into DVFS_PRE_config >>>>>
3860 09:59:39.102205 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3861 09:59:39.105846 Exit from DVFS_PRE_config <<<<<
3862 09:59:39.108703 Enter into PICG configuration >>>>
3863 09:59:39.111985 Exit from PICG configuration <<<<
3864 09:59:39.115421 [RX_INPUT] configuration >>>>>
3865 09:59:39.118922 [RX_INPUT] configuration <<<<<
3866 09:59:39.122301 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3867 09:59:39.129023 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3868 09:59:39.135466 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3869 09:59:39.142440 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3870 09:59:39.145161 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3871 09:59:39.152218 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3872 09:59:39.155850 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3873 09:59:39.162026 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3874 09:59:39.165233 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3875 09:59:39.168829 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3876 09:59:39.172072 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3877 09:59:39.178808 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3878 09:59:39.181767 ===================================
3879 09:59:39.181869 LPDDR4 DRAM CONFIGURATION
3880 09:59:39.185261 ===================================
3881 09:59:39.189027 EX_ROW_EN[0] = 0x0
3882 09:59:39.191830 EX_ROW_EN[1] = 0x0
3883 09:59:39.191922 LP4Y_EN = 0x0
3884 09:59:39.195212 WORK_FSP = 0x0
3885 09:59:39.195343 WL = 0x2
3886 09:59:39.198602 RL = 0x2
3887 09:59:39.198803 BL = 0x2
3888 09:59:39.202309 RPST = 0x0
3889 09:59:39.202473 RD_PRE = 0x0
3890 09:59:39.205432 WR_PRE = 0x1
3891 09:59:39.205565 WR_PST = 0x0
3892 09:59:39.208848 DBI_WR = 0x0
3893 09:59:39.208958 DBI_RD = 0x0
3894 09:59:39.212318 OTF = 0x1
3895 09:59:39.215174 ===================================
3896 09:59:39.218958 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3897 09:59:39.222028 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3898 09:59:39.228563 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3899 09:59:39.231813 ===================================
3900 09:59:39.231918 LPDDR4 DRAM CONFIGURATION
3901 09:59:39.235345 ===================================
3902 09:59:39.238882 EX_ROW_EN[0] = 0x10
3903 09:59:39.238976 EX_ROW_EN[1] = 0x0
3904 09:59:39.242041 LP4Y_EN = 0x0
3905 09:59:39.244907 WORK_FSP = 0x0
3906 09:59:39.244994 WL = 0x2
3907 09:59:39.248662 RL = 0x2
3908 09:59:39.248749 BL = 0x2
3909 09:59:39.251698 RPST = 0x0
3910 09:59:39.251785 RD_PRE = 0x0
3911 09:59:39.255360 WR_PRE = 0x1
3912 09:59:39.255448 WR_PST = 0x0
3913 09:59:39.258247 DBI_WR = 0x0
3914 09:59:39.258331 DBI_RD = 0x0
3915 09:59:39.261847 OTF = 0x1
3916 09:59:39.264947 ===================================
3917 09:59:39.271712 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3918 09:59:39.274813 nWR fixed to 30
3919 09:59:39.274917 [ModeRegInit_LP4] CH0 RK0
3920 09:59:39.278450 [ModeRegInit_LP4] CH0 RK1
3921 09:59:39.281499 [ModeRegInit_LP4] CH1 RK0
3922 09:59:39.284692 [ModeRegInit_LP4] CH1 RK1
3923 09:59:39.284784 match AC timing 17
3924 09:59:39.287815 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3925 09:59:39.294707 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3926 09:59:39.298342 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3927 09:59:39.301319 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3928 09:59:39.308005 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3929 09:59:39.308119 ==
3930 09:59:39.311253 Dram Type= 6, Freq= 0, CH_0, rank 0
3931 09:59:39.314469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3932 09:59:39.314569 ==
3933 09:59:39.321162 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3934 09:59:39.327666 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3935 09:59:39.331554 [CA 0] Center 36 (5~67) winsize 63
3936 09:59:39.334746 [CA 1] Center 36 (5~67) winsize 63
3937 09:59:39.337552 [CA 2] Center 34 (3~65) winsize 63
3938 09:59:39.340949 [CA 3] Center 33 (2~64) winsize 63
3939 09:59:39.344395 [CA 4] Center 33 (2~64) winsize 63
3940 09:59:39.348094 [CA 5] Center 32 (2~63) winsize 62
3941 09:59:39.348216
3942 09:59:39.351082 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3943 09:59:39.351198
3944 09:59:39.354889 [CATrainingPosCal] consider 1 rank data
3945 09:59:39.357920 u2DelayCellTimex100 = 270/100 ps
3946 09:59:39.360885 CA0 delay=36 (5~67),Diff = 4 PI (38 cell)
3947 09:59:39.364490 CA1 delay=36 (5~67),Diff = 4 PI (38 cell)
3948 09:59:39.367539 CA2 delay=34 (3~65),Diff = 2 PI (19 cell)
3949 09:59:39.371787 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3950 09:59:39.374395 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3951 09:59:39.377888 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3952 09:59:39.377985
3953 09:59:39.381192 CA PerBit enable=1, Macro0, CA PI delay=32
3954 09:59:39.384517
3955 09:59:39.384610 [CBTSetCACLKResult] CA Dly = 32
3956 09:59:39.387834 CS Dly: 4 (0~35)
3957 09:59:39.387924 ==
3958 09:59:39.391011 Dram Type= 6, Freq= 0, CH_0, rank 1
3959 09:59:39.394556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3960 09:59:39.394651 ==
3961 09:59:39.400754 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3962 09:59:39.407756 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3963 09:59:39.410792 [CA 0] Center 36 (5~67) winsize 63
3964 09:59:39.414343 [CA 1] Center 36 (5~67) winsize 63
3965 09:59:39.417481 [CA 2] Center 34 (3~65) winsize 63
3966 09:59:39.420758 [CA 3] Center 34 (3~65) winsize 63
3967 09:59:39.424183 [CA 4] Center 33 (2~64) winsize 63
3968 09:59:39.427722 [CA 5] Center 32 (2~63) winsize 62
3969 09:59:39.427823
3970 09:59:39.431382 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3971 09:59:39.431478
3972 09:59:39.434448 [CATrainingPosCal] consider 2 rank data
3973 09:59:39.437845 u2DelayCellTimex100 = 270/100 ps
3974 09:59:39.440950 CA0 delay=36 (5~67),Diff = 4 PI (38 cell)
3975 09:59:39.444185 CA1 delay=36 (5~67),Diff = 4 PI (38 cell)
3976 09:59:39.447451 CA2 delay=34 (3~65),Diff = 2 PI (19 cell)
3977 09:59:39.450787 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3978 09:59:39.454050 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3979 09:59:39.457255 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3980 09:59:39.461043
3981 09:59:39.463794 CA PerBit enable=1, Macro0, CA PI delay=32
3982 09:59:39.463894
3983 09:59:39.467327 [CBTSetCACLKResult] CA Dly = 32
3984 09:59:39.467443 CS Dly: 4 (0~36)
3985 09:59:39.467536
3986 09:59:39.470491 ----->DramcWriteLeveling(PI) begin...
3987 09:59:39.470595 ==
3988 09:59:39.474335 Dram Type= 6, Freq= 0, CH_0, rank 0
3989 09:59:39.477353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3990 09:59:39.480393 ==
3991 09:59:39.480487 Write leveling (Byte 0): 33 => 33
3992 09:59:39.484167 Write leveling (Byte 1): 33 => 33
3993 09:59:39.487481 DramcWriteLeveling(PI) end<-----
3994 09:59:39.487574
3995 09:59:39.487640 ==
3996 09:59:39.490345 Dram Type= 6, Freq= 0, CH_0, rank 0
3997 09:59:39.497163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3998 09:59:39.497333 ==
3999 09:59:39.500343 [Gating] SW mode calibration
4000 09:59:39.507130 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4001 09:59:39.510716 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4002 09:59:39.513701 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4003 09:59:39.520632 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4004 09:59:39.524179 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4005 09:59:39.527286 0 9 12 | B1->B0 | 3434 3030 | 1 1 | (1 0) (0 0)
4006 09:59:39.533809 0 9 16 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
4007 09:59:39.537374 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4008 09:59:39.540412 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4009 09:59:39.547204 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4010 09:59:39.550129 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4011 09:59:39.553754 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4012 09:59:39.560442 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4013 09:59:39.563596 0 10 12 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
4014 09:59:39.567034 0 10 16 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
4015 09:59:39.573608 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4016 09:59:39.577129 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4017 09:59:39.580273 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4018 09:59:39.587387 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4019 09:59:39.590308 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4020 09:59:39.593584 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4021 09:59:39.600464 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4022 09:59:39.603961 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4023 09:59:39.607290 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 09:59:39.610462 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 09:59:39.617071 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 09:59:39.620131 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 09:59:39.623812 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 09:59:39.630371 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 09:59:39.634025 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 09:59:39.637086 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 09:59:39.644009 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 09:59:39.647054 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4033 09:59:39.650198 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4034 09:59:39.657065 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 09:59:39.660277 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4036 09:59:39.663600 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4037 09:59:39.670152 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4038 09:59:39.673769 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4039 09:59:39.676862 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4040 09:59:39.680004 Total UI for P1: 0, mck2ui 16
4041 09:59:39.683769 best dqsien dly found for B0: ( 0, 13, 14)
4042 09:59:39.686678 Total UI for P1: 0, mck2ui 16
4043 09:59:39.690023 best dqsien dly found for B1: ( 0, 13, 16)
4044 09:59:39.693547 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4045 09:59:39.696620 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4046 09:59:39.696710
4047 09:59:39.703438 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4048 09:59:39.707050 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4049 09:59:39.710251 [Gating] SW calibration Done
4050 09:59:39.710354 ==
4051 09:59:39.713606 Dram Type= 6, Freq= 0, CH_0, rank 0
4052 09:59:39.716949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4053 09:59:39.717058 ==
4054 09:59:39.717127 RX Vref Scan: 0
4055 09:59:39.717188
4056 09:59:39.719957 RX Vref 0 -> 0, step: 1
4057 09:59:39.720044
4058 09:59:39.723648 RX Delay -230 -> 252, step: 16
4059 09:59:39.726813 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4060 09:59:39.729855 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4061 09:59:39.736906 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4062 09:59:39.739925 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4063 09:59:39.743168 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4064 09:59:39.746918 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4065 09:59:39.750037 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4066 09:59:39.756354 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4067 09:59:39.759799 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4068 09:59:39.763138 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4069 09:59:39.766664 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4070 09:59:39.773747 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4071 09:59:39.776566 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4072 09:59:39.779824 iDelay=218, Bit 13, Center 57 (-86 ~ 201) 288
4073 09:59:39.783218 iDelay=218, Bit 14, Center 65 (-86 ~ 217) 304
4074 09:59:39.790081 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4075 09:59:39.790191 ==
4076 09:59:39.793283 Dram Type= 6, Freq= 0, CH_0, rank 0
4077 09:59:39.796270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4078 09:59:39.796356 ==
4079 09:59:39.796422 DQS Delay:
4080 09:59:39.800030 DQS0 = 0, DQS1 = 0
4081 09:59:39.800116 DQM Delay:
4082 09:59:39.803193 DQM0 = 50, DQM1 = 47
4083 09:59:39.803278 DQ Delay:
4084 09:59:39.806704 DQ0 =41, DQ1 =57, DQ2 =41, DQ3 =41
4085 09:59:39.809984 DQ4 =49, DQ5 =41, DQ6 =65, DQ7 =65
4086 09:59:39.812988 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4087 09:59:39.816537 DQ12 =49, DQ13 =57, DQ14 =65, DQ15 =57
4088 09:59:39.816671
4089 09:59:39.816741
4090 09:59:39.816802 ==
4091 09:59:39.820315 Dram Type= 6, Freq= 0, CH_0, rank 0
4092 09:59:39.823218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4093 09:59:39.823353 ==
4094 09:59:39.823418
4095 09:59:39.823479
4096 09:59:39.827176 TX Vref Scan disable
4097 09:59:39.830091 == TX Byte 0 ==
4098 09:59:39.833329 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4099 09:59:39.836539 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4100 09:59:39.839970 == TX Byte 1 ==
4101 09:59:39.843578 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4102 09:59:39.846513 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4103 09:59:39.846609 ==
4104 09:59:39.850173 Dram Type= 6, Freq= 0, CH_0, rank 0
4105 09:59:39.856494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4106 09:59:39.856605 ==
4107 09:59:39.856671
4108 09:59:39.856731
4109 09:59:39.856787 TX Vref Scan disable
4110 09:59:39.860214 == TX Byte 0 ==
4111 09:59:39.863859 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4112 09:59:39.866941 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4113 09:59:39.870851 == TX Byte 1 ==
4114 09:59:39.874283 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4115 09:59:39.877067 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4116 09:59:39.880549
4117 09:59:39.880641 [DATLAT]
4118 09:59:39.880707 Freq=600, CH0 RK0
4119 09:59:39.880768
4120 09:59:39.884168 DATLAT Default: 0x9
4121 09:59:39.884252 0, 0xFFFF, sum = 0
4122 09:59:39.887263 1, 0xFFFF, sum = 0
4123 09:59:39.887349 2, 0xFFFF, sum = 0
4124 09:59:39.890462 3, 0xFFFF, sum = 0
4125 09:59:39.890550 4, 0xFFFF, sum = 0
4126 09:59:39.894187 5, 0xFFFF, sum = 0
4127 09:59:39.894274 6, 0xFFFF, sum = 0
4128 09:59:39.897227 7, 0xFFFF, sum = 0
4129 09:59:39.897314 8, 0x0, sum = 1
4130 09:59:39.900368 9, 0x0, sum = 2
4131 09:59:39.900454 10, 0x0, sum = 3
4132 09:59:39.904324 11, 0x0, sum = 4
4133 09:59:39.904410 best_step = 9
4134 09:59:39.904474
4135 09:59:39.904533 ==
4136 09:59:39.907519 Dram Type= 6, Freq= 0, CH_0, rank 0
4137 09:59:39.914200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4138 09:59:39.914306 ==
4139 09:59:39.914376 RX Vref Scan: 1
4140 09:59:39.914436
4141 09:59:39.917332 RX Vref 0 -> 0, step: 1
4142 09:59:39.917421
4143 09:59:39.920990 RX Delay -163 -> 252, step: 8
4144 09:59:39.921082
4145 09:59:39.924051 Set Vref, RX VrefLevel [Byte0]: 53
4146 09:59:39.927030 [Byte1]: 46
4147 09:59:39.927123
4148 09:59:39.930620 Final RX Vref Byte 0 = 53 to rank0
4149 09:59:39.933810 Final RX Vref Byte 1 = 46 to rank0
4150 09:59:39.937399 Final RX Vref Byte 0 = 53 to rank1
4151 09:59:39.940374 Final RX Vref Byte 1 = 46 to rank1==
4152 09:59:39.943882 Dram Type= 6, Freq= 0, CH_0, rank 0
4153 09:59:39.947296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4154 09:59:39.947483 ==
4155 09:59:39.950471 DQS Delay:
4156 09:59:39.950576 DQS0 = 0, DQS1 = 0
4157 09:59:39.950643 DQM Delay:
4158 09:59:39.954130 DQM0 = 52, DQM1 = 48
4159 09:59:39.954230 DQ Delay:
4160 09:59:39.957550 DQ0 =52, DQ1 =56, DQ2 =48, DQ3 =52
4161 09:59:39.960519 DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =56
4162 09:59:39.963850 DQ8 =36, DQ9 =40, DQ10 =48, DQ11 =40
4163 09:59:39.966860 DQ12 =52, DQ13 =52, DQ14 =60, DQ15 =56
4164 09:59:39.966977
4165 09:59:39.967045
4166 09:59:39.977145 [DQSOSCAuto] RK0, (LSB)MR18= 0x6e60, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 389 ps
4167 09:59:39.977267 CH0 RK0: MR19=808, MR18=6E60
4168 09:59:39.983956 CH0_RK0: MR19=0x808, MR18=0x6E60, DQSOSC=389, MR23=63, INC=173, DEC=115
4169 09:59:39.984067
4170 09:59:39.986950 ----->DramcWriteLeveling(PI) begin...
4171 09:59:39.987039 ==
4172 09:59:39.990421 Dram Type= 6, Freq= 0, CH_0, rank 1
4173 09:59:39.997011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4174 09:59:39.997122 ==
4175 09:59:40.000444 Write leveling (Byte 0): 34 => 34
4176 09:59:40.003634 Write leveling (Byte 1): 30 => 30
4177 09:59:40.003738 DramcWriteLeveling(PI) end<-----
4178 09:59:40.007471
4179 09:59:40.007561 ==
4180 09:59:40.010694 Dram Type= 6, Freq= 0, CH_0, rank 1
4181 09:59:40.013948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4182 09:59:40.014035 ==
4183 09:59:40.016923 [Gating] SW mode calibration
4184 09:59:40.023756 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4185 09:59:40.027208 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4186 09:59:40.034165 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4187 09:59:40.037197 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4188 09:59:40.040987 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4189 09:59:40.047102 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (0 0)
4190 09:59:40.050225 0 9 16 | B1->B0 | 2929 2525 | 0 0 | (0 0) (0 0)
4191 09:59:40.053696 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4192 09:59:40.060275 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4193 09:59:40.063372 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4194 09:59:40.066782 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4195 09:59:40.073388 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4196 09:59:40.077091 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4197 09:59:40.080269 0 10 12 | B1->B0 | 2525 2828 | 0 0 | (0 0) (0 0)
4198 09:59:40.086976 0 10 16 | B1->B0 | 4040 4040 | 0 0 | (0 0) (1 1)
4199 09:59:40.090543 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4200 09:59:40.093777 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4201 09:59:40.100153 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4202 09:59:40.103534 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4203 09:59:40.106308 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4204 09:59:40.113058 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4205 09:59:40.116649 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4206 09:59:40.119971 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4207 09:59:40.126301 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 09:59:40.129546 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 09:59:40.132963 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 09:59:40.139791 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 09:59:40.143034 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 09:59:40.146622 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 09:59:40.153409 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4214 09:59:40.156345 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4215 09:59:40.159564 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4216 09:59:40.166161 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4217 09:59:40.169843 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4218 09:59:40.173155 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4219 09:59:40.176009 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4220 09:59:40.182885 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4221 09:59:40.186174 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4222 09:59:40.189306 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4223 09:59:40.193239 Total UI for P1: 0, mck2ui 16
4224 09:59:40.196133 best dqsien dly found for B0: ( 0, 13, 14)
4225 09:59:40.199470 Total UI for P1: 0, mck2ui 16
4226 09:59:40.203016 best dqsien dly found for B1: ( 0, 13, 14)
4227 09:59:40.206129 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4228 09:59:40.212946 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4229 09:59:40.213055
4230 09:59:40.216263 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4231 09:59:40.219124 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4232 09:59:40.222965 [Gating] SW calibration Done
4233 09:59:40.223062 ==
4234 09:59:40.225872 Dram Type= 6, Freq= 0, CH_0, rank 1
4235 09:59:40.229339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4236 09:59:40.229460 ==
4237 09:59:40.232333 RX Vref Scan: 0
4238 09:59:40.232424
4239 09:59:40.232513 RX Vref 0 -> 0, step: 1
4240 09:59:40.232589
4241 09:59:40.235634 RX Delay -230 -> 252, step: 16
4242 09:59:40.239371 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4243 09:59:40.246240 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4244 09:59:40.249095 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4245 09:59:40.252480 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4246 09:59:40.256108 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4247 09:59:40.259091 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4248 09:59:40.266110 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4249 09:59:40.269379 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4250 09:59:40.272515 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4251 09:59:40.275633 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4252 09:59:40.278932 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4253 09:59:40.285473 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4254 09:59:40.289488 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4255 09:59:40.292729 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4256 09:59:40.295819 iDelay=218, Bit 14, Center 57 (-86 ~ 201) 288
4257 09:59:40.302581 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4258 09:59:40.302690 ==
4259 09:59:40.305720 Dram Type= 6, Freq= 0, CH_0, rank 1
4260 09:59:40.308957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4261 09:59:40.309045 ==
4262 09:59:40.309111 DQS Delay:
4263 09:59:40.312122 DQS0 = 0, DQS1 = 0
4264 09:59:40.312208 DQM Delay:
4265 09:59:40.315744 DQM0 = 53, DQM1 = 44
4266 09:59:40.315828 DQ Delay:
4267 09:59:40.318987 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4268 09:59:40.322077 DQ4 =57, DQ5 =41, DQ6 =65, DQ7 =65
4269 09:59:40.325748 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =33
4270 09:59:40.328900 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =49
4271 09:59:40.328991
4272 09:59:40.329056
4273 09:59:40.329116 ==
4274 09:59:40.332541 Dram Type= 6, Freq= 0, CH_0, rank 1
4275 09:59:40.335508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4276 09:59:40.339214 ==
4277 09:59:40.339307
4278 09:59:40.339372
4279 09:59:40.339431 TX Vref Scan disable
4280 09:59:40.342293 == TX Byte 0 ==
4281 09:59:40.345317 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4282 09:59:40.348706 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4283 09:59:40.351894 == TX Byte 1 ==
4284 09:59:40.355624 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4285 09:59:40.359001 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4286 09:59:40.361953 ==
4287 09:59:40.365138 Dram Type= 6, Freq= 0, CH_0, rank 1
4288 09:59:40.368788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4289 09:59:40.368879 ==
4290 09:59:40.368945
4291 09:59:40.369004
4292 09:59:40.371759 TX Vref Scan disable
4293 09:59:40.371843 == TX Byte 0 ==
4294 09:59:40.378545 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4295 09:59:40.381688 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4296 09:59:40.381805 == TX Byte 1 ==
4297 09:59:40.388610 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4298 09:59:40.391952 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4299 09:59:40.392056
4300 09:59:40.392122 [DATLAT]
4301 09:59:40.395523 Freq=600, CH0 RK1
4302 09:59:40.395613
4303 09:59:40.395678 DATLAT Default: 0x9
4304 09:59:40.398622 0, 0xFFFF, sum = 0
4305 09:59:40.398710 1, 0xFFFF, sum = 0
4306 09:59:40.401634 2, 0xFFFF, sum = 0
4307 09:59:40.405359 3, 0xFFFF, sum = 0
4308 09:59:40.405448 4, 0xFFFF, sum = 0
4309 09:59:40.408436 5, 0xFFFF, sum = 0
4310 09:59:40.408523 6, 0xFFFF, sum = 0
4311 09:59:40.411987 7, 0xFFFF, sum = 0
4312 09:59:40.412080 8, 0x0, sum = 1
4313 09:59:40.412149 9, 0x0, sum = 2
4314 09:59:40.414939 10, 0x0, sum = 3
4315 09:59:40.415025 11, 0x0, sum = 4
4316 09:59:40.418746 best_step = 9
4317 09:59:40.418835
4318 09:59:40.418899 ==
4319 09:59:40.421941 Dram Type= 6, Freq= 0, CH_0, rank 1
4320 09:59:40.425277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4321 09:59:40.425366 ==
4322 09:59:40.428099 RX Vref Scan: 0
4323 09:59:40.428181
4324 09:59:40.428244 RX Vref 0 -> 0, step: 1
4325 09:59:40.428304
4326 09:59:40.431413 RX Delay -163 -> 252, step: 8
4327 09:59:40.439432 iDelay=197, Bit 0, Center 52 (-91 ~ 196) 288
4328 09:59:40.442522 iDelay=197, Bit 1, Center 52 (-91 ~ 196) 288
4329 09:59:40.445542 iDelay=197, Bit 2, Center 48 (-99 ~ 196) 296
4330 09:59:40.449105 iDelay=197, Bit 3, Center 52 (-91 ~ 196) 288
4331 09:59:40.452262 iDelay=197, Bit 4, Center 56 (-83 ~ 196) 280
4332 09:59:40.458952 iDelay=197, Bit 5, Center 44 (-99 ~ 188) 288
4333 09:59:40.462639 iDelay=197, Bit 6, Center 56 (-83 ~ 196) 280
4334 09:59:40.465921 iDelay=197, Bit 7, Center 60 (-75 ~ 196) 272
4335 09:59:40.468758 iDelay=197, Bit 8, Center 40 (-99 ~ 180) 280
4336 09:59:40.472529 iDelay=197, Bit 9, Center 32 (-107 ~ 172) 280
4337 09:59:40.478852 iDelay=197, Bit 10, Center 48 (-91 ~ 188) 280
4338 09:59:40.482596 iDelay=197, Bit 11, Center 40 (-99 ~ 180) 280
4339 09:59:40.485502 iDelay=197, Bit 12, Center 52 (-83 ~ 188) 272
4340 09:59:40.488810 iDelay=197, Bit 13, Center 48 (-91 ~ 188) 280
4341 09:59:40.495484 iDelay=197, Bit 14, Center 56 (-83 ~ 196) 280
4342 09:59:40.498657 iDelay=197, Bit 15, Center 52 (-91 ~ 196) 288
4343 09:59:40.498754 ==
4344 09:59:40.502264 Dram Type= 6, Freq= 0, CH_0, rank 1
4345 09:59:40.505307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4346 09:59:40.505396 ==
4347 09:59:40.505461 DQS Delay:
4348 09:59:40.508957 DQS0 = 0, DQS1 = 0
4349 09:59:40.509040 DQM Delay:
4350 09:59:40.512090 DQM0 = 52, DQM1 = 46
4351 09:59:40.512172 DQ Delay:
4352 09:59:40.515121 DQ0 =52, DQ1 =52, DQ2 =48, DQ3 =52
4353 09:59:40.518506 DQ4 =56, DQ5 =44, DQ6 =56, DQ7 =60
4354 09:59:40.521964 DQ8 =40, DQ9 =32, DQ10 =48, DQ11 =40
4355 09:59:40.525446 DQ12 =52, DQ13 =48, DQ14 =56, DQ15 =52
4356 09:59:40.525565
4357 09:59:40.525678
4358 09:59:40.535090 [DQSOSCAuto] RK1, (LSB)MR18= 0x6425, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 391 ps
4359 09:59:40.535204 CH0 RK1: MR19=808, MR18=6425
4360 09:59:40.541804 CH0_RK1: MR19=0x808, MR18=0x6425, DQSOSC=391, MR23=63, INC=171, DEC=114
4361 09:59:40.544955 [RxdqsGatingPostProcess] freq 600
4362 09:59:40.552146 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4363 09:59:40.555180 Pre-setting of DQS Precalculation
4364 09:59:40.558232 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4365 09:59:40.558327 ==
4366 09:59:40.561950 Dram Type= 6, Freq= 0, CH_1, rank 0
4367 09:59:40.568333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4368 09:59:40.568435 ==
4369 09:59:40.572055 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4370 09:59:40.578561 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4371 09:59:40.582006 [CA 0] Center 35 (5~66) winsize 62
4372 09:59:40.585264 [CA 1] Center 36 (5~67) winsize 63
4373 09:59:40.588350 [CA 2] Center 34 (4~65) winsize 62
4374 09:59:40.591726 [CA 3] Center 34 (4~65) winsize 62
4375 09:59:40.595099 [CA 4] Center 34 (4~65) winsize 62
4376 09:59:40.598811 [CA 5] Center 33 (3~64) winsize 62
4377 09:59:40.598905
4378 09:59:40.602078 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4379 09:59:40.602164
4380 09:59:40.605030 [CATrainingPosCal] consider 1 rank data
4381 09:59:40.608707 u2DelayCellTimex100 = 270/100 ps
4382 09:59:40.611587 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4383 09:59:40.615161 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
4384 09:59:40.618260 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4385 09:59:40.625239 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4386 09:59:40.628302 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4387 09:59:40.631695 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4388 09:59:40.631790
4389 09:59:40.635011 CA PerBit enable=1, Macro0, CA PI delay=33
4390 09:59:40.635125
4391 09:59:40.638565 [CBTSetCACLKResult] CA Dly = 33
4392 09:59:40.638651 CS Dly: 6 (0~37)
4393 09:59:40.638714 ==
4394 09:59:40.641777 Dram Type= 6, Freq= 0, CH_1, rank 1
4395 09:59:40.648123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4396 09:59:40.648229 ==
4397 09:59:40.651316 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4398 09:59:40.658050 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4399 09:59:40.661363 [CA 0] Center 36 (5~67) winsize 63
4400 09:59:40.664641 [CA 1] Center 36 (5~67) winsize 63
4401 09:59:40.667801 [CA 2] Center 34 (4~65) winsize 62
4402 09:59:40.671601 [CA 3] Center 34 (4~65) winsize 62
4403 09:59:40.674590 [CA 4] Center 35 (4~66) winsize 63
4404 09:59:40.677855 [CA 5] Center 34 (3~65) winsize 63
4405 09:59:40.677943
4406 09:59:40.681489 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4407 09:59:40.681605
4408 09:59:40.684629 [CATrainingPosCal] consider 2 rank data
4409 09:59:40.688279 u2DelayCellTimex100 = 270/100 ps
4410 09:59:40.691538 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4411 09:59:40.697891 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
4412 09:59:40.701118 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4413 09:59:40.704777 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4414 09:59:40.707937 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4415 09:59:40.711350 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4416 09:59:40.711441
4417 09:59:40.714545 CA PerBit enable=1, Macro0, CA PI delay=33
4418 09:59:40.714632
4419 09:59:40.717875 [CBTSetCACLKResult] CA Dly = 33
4420 09:59:40.717965 CS Dly: 6 (0~38)
4421 09:59:40.721553
4422 09:59:40.724654 ----->DramcWriteLeveling(PI) begin...
4423 09:59:40.724747 ==
4424 09:59:40.727675 Dram Type= 6, Freq= 0, CH_1, rank 0
4425 09:59:40.731349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4426 09:59:40.731442 ==
4427 09:59:40.734341 Write leveling (Byte 0): 29 => 29
4428 09:59:40.737705 Write leveling (Byte 1): 32 => 32
4429 09:59:40.741006 DramcWriteLeveling(PI) end<-----
4430 09:59:40.741090
4431 09:59:40.741151 ==
4432 09:59:40.744579 Dram Type= 6, Freq= 0, CH_1, rank 0
4433 09:59:40.747783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4434 09:59:40.747874 ==
4435 09:59:40.751004 [Gating] SW mode calibration
4436 09:59:40.757645 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4437 09:59:40.764526 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4438 09:59:40.767369 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4439 09:59:40.770769 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4440 09:59:40.778002 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4441 09:59:40.780823 0 9 12 | B1->B0 | 3030 2f2f | 0 0 | (0 1) (1 1)
4442 09:59:40.784287 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4443 09:59:40.787482 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4444 09:59:40.794612 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4445 09:59:40.797597 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4446 09:59:40.801243 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4447 09:59:40.807866 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4448 09:59:40.811040 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4449 09:59:40.814621 0 10 12 | B1->B0 | 3333 3737 | 1 0 | (0 0) (1 1)
4450 09:59:40.821191 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4451 09:59:40.824261 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4452 09:59:40.827717 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4453 09:59:40.834333 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4454 09:59:40.837550 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4455 09:59:40.841057 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4456 09:59:40.847713 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4457 09:59:40.851296 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4458 09:59:40.854608 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 09:59:40.860941 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 09:59:40.864185 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 09:59:40.867903 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 09:59:40.875170 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 09:59:40.877778 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 09:59:40.880641 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 09:59:40.884446 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 09:59:40.891168 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 09:59:40.894182 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 09:59:40.897836 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 09:59:40.904449 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 09:59:40.907416 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 09:59:40.910934 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4472 09:59:40.917422 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4473 09:59:40.920638 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4474 09:59:40.923904 Total UI for P1: 0, mck2ui 16
4475 09:59:40.927541 best dqsien dly found for B0: ( 0, 13, 10)
4476 09:59:40.930670 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4477 09:59:40.934637 Total UI for P1: 0, mck2ui 16
4478 09:59:40.937428 best dqsien dly found for B1: ( 0, 13, 10)
4479 09:59:40.940565 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4480 09:59:40.944051 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4481 09:59:40.947865
4482 09:59:40.950893 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4483 09:59:40.954268 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4484 09:59:40.957515 [Gating] SW calibration Done
4485 09:59:40.957678 ==
4486 09:59:40.961037 Dram Type= 6, Freq= 0, CH_1, rank 0
4487 09:59:40.964136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4488 09:59:40.964222 ==
4489 09:59:40.964288 RX Vref Scan: 0
4490 09:59:40.964347
4491 09:59:40.967869 RX Vref 0 -> 0, step: 1
4492 09:59:40.967953
4493 09:59:40.971294 RX Delay -230 -> 252, step: 16
4494 09:59:40.974183 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4495 09:59:40.977377 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4496 09:59:40.984289 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4497 09:59:40.987394 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4498 09:59:40.990516 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4499 09:59:40.994395 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4500 09:59:41.000587 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4501 09:59:41.003798 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4502 09:59:41.007670 iDelay=218, Bit 8, Center 41 (-102 ~ 185) 288
4503 09:59:41.010572 iDelay=218, Bit 9, Center 41 (-102 ~ 185) 288
4504 09:59:41.014333 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4505 09:59:41.020341 iDelay=218, Bit 11, Center 49 (-102 ~ 201) 304
4506 09:59:41.023992 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4507 09:59:41.027334 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4508 09:59:41.030575 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4509 09:59:41.037209 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4510 09:59:41.037327 ==
4511 09:59:41.040573 Dram Type= 6, Freq= 0, CH_1, rank 0
4512 09:59:41.043748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4513 09:59:41.043841 ==
4514 09:59:41.043922 DQS Delay:
4515 09:59:41.047229 DQS0 = 0, DQS1 = 0
4516 09:59:41.047312 DQM Delay:
4517 09:59:41.050376 DQM0 = 52, DQM1 = 49
4518 09:59:41.050461 DQ Delay:
4519 09:59:41.053428 DQ0 =57, DQ1 =49, DQ2 =49, DQ3 =49
4520 09:59:41.056872 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4521 09:59:41.060387 DQ8 =41, DQ9 =41, DQ10 =49, DQ11 =49
4522 09:59:41.063631 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4523 09:59:41.063789
4524 09:59:41.063854
4525 09:59:41.063913 ==
4526 09:59:41.067006 Dram Type= 6, Freq= 0, CH_1, rank 0
4527 09:59:41.070218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4528 09:59:41.073716 ==
4529 09:59:41.073805
4530 09:59:41.073870
4531 09:59:41.073929 TX Vref Scan disable
4532 09:59:41.076592 == TX Byte 0 ==
4533 09:59:41.080401 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4534 09:59:41.083531 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4535 09:59:41.086604 == TX Byte 1 ==
4536 09:59:41.089882 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4537 09:59:41.093427 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4538 09:59:41.096538 ==
4539 09:59:41.099783 Dram Type= 6, Freq= 0, CH_1, rank 0
4540 09:59:41.103554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4541 09:59:41.103642 ==
4542 09:59:41.103707
4543 09:59:41.103767
4544 09:59:41.107096 TX Vref Scan disable
4545 09:59:41.107180 == TX Byte 0 ==
4546 09:59:41.113417 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4547 09:59:41.116386 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4548 09:59:41.116477 == TX Byte 1 ==
4549 09:59:41.123340 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4550 09:59:41.126502 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4551 09:59:41.126599
4552 09:59:41.126664 [DATLAT]
4553 09:59:41.130138 Freq=600, CH1 RK0
4554 09:59:41.130223
4555 09:59:41.130288 DATLAT Default: 0x9
4556 09:59:41.133211 0, 0xFFFF, sum = 0
4557 09:59:41.133332 1, 0xFFFF, sum = 0
4558 09:59:41.136303 2, 0xFFFF, sum = 0
4559 09:59:41.139592 3, 0xFFFF, sum = 0
4560 09:59:41.139680 4, 0xFFFF, sum = 0
4561 09:59:41.142865 5, 0xFFFF, sum = 0
4562 09:59:41.142954 6, 0xFFFF, sum = 0
4563 09:59:41.146945 7, 0xFFFF, sum = 0
4564 09:59:41.147031 8, 0x0, sum = 1
4565 09:59:41.149888 9, 0x0, sum = 2
4566 09:59:41.149974 10, 0x0, sum = 3
4567 09:59:41.150040 11, 0x0, sum = 4
4568 09:59:41.152801 best_step = 9
4569 09:59:41.152884
4570 09:59:41.152950 ==
4571 09:59:41.156467 Dram Type= 6, Freq= 0, CH_1, rank 0
4572 09:59:41.159383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4573 09:59:41.159475 ==
4574 09:59:41.162972 RX Vref Scan: 1
4575 09:59:41.163060
4576 09:59:41.163125 RX Vref 0 -> 0, step: 1
4577 09:59:41.163187
4578 09:59:41.166302 RX Delay -147 -> 252, step: 8
4579 09:59:41.166387
4580 09:59:41.169797 Set Vref, RX VrefLevel [Byte0]: 56
4581 09:59:41.172898 [Byte1]: 49
4582 09:59:41.176933
4583 09:59:41.177021 Final RX Vref Byte 0 = 56 to rank0
4584 09:59:41.180533 Final RX Vref Byte 1 = 49 to rank0
4585 09:59:41.183385 Final RX Vref Byte 0 = 56 to rank1
4586 09:59:41.186680 Final RX Vref Byte 1 = 49 to rank1==
4587 09:59:41.190022 Dram Type= 6, Freq= 0, CH_1, rank 0
4588 09:59:41.197002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4589 09:59:41.197117 ==
4590 09:59:41.197184 DQS Delay:
4591 09:59:41.200311 DQS0 = 0, DQS1 = 0
4592 09:59:41.200396 DQM Delay:
4593 09:59:41.200460 DQM0 = 48, DQM1 = 45
4594 09:59:41.203394 DQ Delay:
4595 09:59:41.206963 DQ0 =52, DQ1 =40, DQ2 =40, DQ3 =48
4596 09:59:41.209983 DQ4 =48, DQ5 =56, DQ6 =56, DQ7 =48
4597 09:59:41.213158 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =36
4598 09:59:41.216792 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =56
4599 09:59:41.216880
4600 09:59:41.216945
4601 09:59:41.223044 [DQSOSCAuto] RK0, (LSB)MR18= 0x4368, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
4602 09:59:41.226799 CH1 RK0: MR19=808, MR18=4368
4603 09:59:41.232957 CH1_RK0: MR19=0x808, MR18=0x4368, DQSOSC=390, MR23=63, INC=172, DEC=114
4604 09:59:41.233058
4605 09:59:41.236308 ----->DramcWriteLeveling(PI) begin...
4606 09:59:41.236396 ==
4607 09:59:41.239940 Dram Type= 6, Freq= 0, CH_1, rank 1
4608 09:59:41.242937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4609 09:59:41.243024 ==
4610 09:59:41.246142 Write leveling (Byte 0): 31 => 31
4611 09:59:41.249838 Write leveling (Byte 1): 30 => 30
4612 09:59:41.253406 DramcWriteLeveling(PI) end<-----
4613 09:59:41.253491
4614 09:59:41.253556 ==
4615 09:59:41.256368 Dram Type= 6, Freq= 0, CH_1, rank 1
4616 09:59:41.259940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4617 09:59:41.260028 ==
4618 09:59:41.262778 [Gating] SW mode calibration
4619 09:59:41.269458 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4620 09:59:41.276483 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4621 09:59:41.279480 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4622 09:59:41.285846 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4623 09:59:41.289334 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4624 09:59:41.293094 0 9 12 | B1->B0 | 2f2f 2f2f | 0 1 | (1 1) (1 1)
4625 09:59:41.299304 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4626 09:59:41.302682 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4627 09:59:41.306194 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4628 09:59:41.312697 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4629 09:59:41.315871 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4630 09:59:41.319022 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4631 09:59:41.326024 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4632 09:59:41.329539 0 10 12 | B1->B0 | 3c3c 3838 | 0 0 | (0 0) (0 0)
4633 09:59:41.332554 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4634 09:59:41.339671 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4635 09:59:41.342935 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4636 09:59:41.345793 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4637 09:59:41.352500 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4638 09:59:41.355780 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4639 09:59:41.359188 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4640 09:59:41.362156 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4641 09:59:41.369044 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 09:59:41.372231 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 09:59:41.376023 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 09:59:41.382045 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 09:59:41.385492 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 09:59:41.388781 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 09:59:41.395559 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 09:59:41.398807 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 09:59:41.402605 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 09:59:41.409150 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 09:59:41.412302 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4652 09:59:41.415781 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4653 09:59:41.422399 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4654 09:59:41.425909 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4655 09:59:41.428643 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4656 09:59:41.435576 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4657 09:59:41.435687 Total UI for P1: 0, mck2ui 16
4658 09:59:41.442018 best dqsien dly found for B1: ( 0, 13, 10)
4659 09:59:41.445231 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4660 09:59:41.448720 Total UI for P1: 0, mck2ui 16
4661 09:59:41.452357 best dqsien dly found for B0: ( 0, 13, 12)
4662 09:59:41.455315 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4663 09:59:41.458851 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4664 09:59:41.458942
4665 09:59:41.461874 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4666 09:59:41.465069 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4667 09:59:41.468483 [Gating] SW calibration Done
4668 09:59:41.468572 ==
4669 09:59:41.472211 Dram Type= 6, Freq= 0, CH_1, rank 1
4670 09:59:41.475240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4671 09:59:41.478590 ==
4672 09:59:41.478675 RX Vref Scan: 0
4673 09:59:41.478740
4674 09:59:41.482207 RX Vref 0 -> 0, step: 1
4675 09:59:41.482291
4676 09:59:41.485256 RX Delay -230 -> 252, step: 16
4677 09:59:41.488722 iDelay=218, Bit 0, Center 65 (-86 ~ 217) 304
4678 09:59:41.491817 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4679 09:59:41.495657 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4680 09:59:41.498428 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4681 09:59:41.505209 iDelay=218, Bit 4, Center 57 (-86 ~ 201) 288
4682 09:59:41.509325 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4683 09:59:41.512170 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4684 09:59:41.515234 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4685 09:59:41.518446 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4686 09:59:41.525221 iDelay=218, Bit 9, Center 41 (-118 ~ 201) 320
4687 09:59:41.529006 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4688 09:59:41.532051 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4689 09:59:41.535152 iDelay=218, Bit 12, Center 65 (-86 ~ 217) 304
4690 09:59:41.542032 iDelay=218, Bit 13, Center 65 (-86 ~ 217) 304
4691 09:59:41.545272 iDelay=218, Bit 14, Center 57 (-86 ~ 201) 288
4692 09:59:41.548477 iDelay=218, Bit 15, Center 65 (-86 ~ 217) 304
4693 09:59:41.548569 ==
4694 09:59:41.551806 Dram Type= 6, Freq= 0, CH_1, rank 1
4695 09:59:41.555368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4696 09:59:41.555458 ==
4697 09:59:41.558506 DQS Delay:
4698 09:59:41.558591 DQS0 = 0, DQS1 = 0
4699 09:59:41.561765 DQM Delay:
4700 09:59:41.561849 DQM0 = 53, DQM1 = 52
4701 09:59:41.561914 DQ Delay:
4702 09:59:41.565131 DQ0 =65, DQ1 =41, DQ2 =33, DQ3 =49
4703 09:59:41.568321 DQ4 =57, DQ5 =65, DQ6 =65, DQ7 =49
4704 09:59:41.571436 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =41
4705 09:59:41.575314 DQ12 =65, DQ13 =65, DQ14 =57, DQ15 =65
4706 09:59:41.575404
4707 09:59:41.578457
4708 09:59:41.578543 ==
4709 09:59:41.581777 Dram Type= 6, Freq= 0, CH_1, rank 1
4710 09:59:41.585004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4711 09:59:41.585101 ==
4712 09:59:41.585168
4713 09:59:41.585228
4714 09:59:41.588197 TX Vref Scan disable
4715 09:59:41.588316 == TX Byte 0 ==
4716 09:59:41.594987 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4717 09:59:41.598163 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4718 09:59:41.598258 == TX Byte 1 ==
4719 09:59:41.604840 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4720 09:59:41.608471 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4721 09:59:41.608592 ==
4722 09:59:41.611792 Dram Type= 6, Freq= 0, CH_1, rank 1
4723 09:59:41.614588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4724 09:59:41.614677 ==
4725 09:59:41.614744
4726 09:59:41.614804
4727 09:59:41.618334 TX Vref Scan disable
4728 09:59:41.621289 == TX Byte 0 ==
4729 09:59:41.624906 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4730 09:59:41.627909 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4731 09:59:41.631713 == TX Byte 1 ==
4732 09:59:41.634957 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4733 09:59:41.638029 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4734 09:59:41.638119
4735 09:59:41.641454 [DATLAT]
4736 09:59:41.641582 Freq=600, CH1 RK1
4737 09:59:41.641686
4738 09:59:41.645153 DATLAT Default: 0x9
4739 09:59:41.645236 0, 0xFFFF, sum = 0
4740 09:59:41.648049 1, 0xFFFF, sum = 0
4741 09:59:41.648134 2, 0xFFFF, sum = 0
4742 09:59:41.651346 3, 0xFFFF, sum = 0
4743 09:59:41.651477 4, 0xFFFF, sum = 0
4744 09:59:41.655103 5, 0xFFFF, sum = 0
4745 09:59:41.655224 6, 0xFFFF, sum = 0
4746 09:59:41.658038 7, 0xFFFF, sum = 0
4747 09:59:41.658129 8, 0x0, sum = 1
4748 09:59:41.661328 9, 0x0, sum = 2
4749 09:59:41.661414 10, 0x0, sum = 3
4750 09:59:41.664894 11, 0x0, sum = 4
4751 09:59:41.664982 best_step = 9
4752 09:59:41.665047
4753 09:59:41.665107 ==
4754 09:59:41.667963 Dram Type= 6, Freq= 0, CH_1, rank 1
4755 09:59:41.671189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4756 09:59:41.674648 ==
4757 09:59:41.674735 RX Vref Scan: 0
4758 09:59:41.674801
4759 09:59:41.678271 RX Vref 0 -> 0, step: 1
4760 09:59:41.678357
4761 09:59:41.681052 RX Delay -163 -> 252, step: 8
4762 09:59:41.684661 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4763 09:59:41.688036 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4764 09:59:41.694485 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4765 09:59:41.697727 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4766 09:59:41.701315 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288
4767 09:59:41.704638 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4768 09:59:41.707773 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4769 09:59:41.714720 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4770 09:59:41.717972 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4771 09:59:41.721131 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4772 09:59:41.724756 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4773 09:59:41.728051 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4774 09:59:41.734274 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4775 09:59:41.737967 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4776 09:59:41.741268 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4777 09:59:41.744277 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4778 09:59:41.744366 ==
4779 09:59:41.747476 Dram Type= 6, Freq= 0, CH_1, rank 1
4780 09:59:41.754370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4781 09:59:41.754473 ==
4782 09:59:41.754540 DQS Delay:
4783 09:59:41.757708 DQS0 = 0, DQS1 = 0
4784 09:59:41.757794 DQM Delay:
4785 09:59:41.757860 DQM0 = 48, DQM1 = 44
4786 09:59:41.760798 DQ Delay:
4787 09:59:41.764578 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4788 09:59:41.767369 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =48
4789 09:59:41.770965 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4790 09:59:41.774141 DQ12 =52, DQ13 =52, DQ14 =48, DQ15 =52
4791 09:59:41.774229
4792 09:59:41.774294
4793 09:59:41.781073 [DQSOSCAuto] RK1, (LSB)MR18= 0x6b23, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 389 ps
4794 09:59:41.784445 CH1 RK1: MR19=808, MR18=6B23
4795 09:59:41.790658 CH1_RK1: MR19=0x808, MR18=0x6B23, DQSOSC=389, MR23=63, INC=173, DEC=115
4796 09:59:41.794121 [RxdqsGatingPostProcess] freq 600
4797 09:59:41.797408 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4798 09:59:41.800633 Pre-setting of DQS Precalculation
4799 09:59:41.807105 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4800 09:59:41.814058 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4801 09:59:41.820399 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4802 09:59:41.820514
4803 09:59:41.820581
4804 09:59:41.823851 [Calibration Summary] 1200 Mbps
4805 09:59:41.826852 CH 0, Rank 0
4806 09:59:41.826939 SW Impedance : PASS
4807 09:59:41.830363 DUTY Scan : NO K
4808 09:59:41.830448 ZQ Calibration : PASS
4809 09:59:41.833528 Jitter Meter : NO K
4810 09:59:41.837095 CBT Training : PASS
4811 09:59:41.837185 Write leveling : PASS
4812 09:59:41.840193 RX DQS gating : PASS
4813 09:59:41.843464 RX DQ/DQS(RDDQC) : PASS
4814 09:59:41.843550 TX DQ/DQS : PASS
4815 09:59:41.846863 RX DATLAT : PASS
4816 09:59:41.850176 RX DQ/DQS(Engine): PASS
4817 09:59:41.850260 TX OE : NO K
4818 09:59:41.853770 All Pass.
4819 09:59:41.853852
4820 09:59:41.853918 CH 0, Rank 1
4821 09:59:41.856749 SW Impedance : PASS
4822 09:59:41.856832 DUTY Scan : NO K
4823 09:59:41.860433 ZQ Calibration : PASS
4824 09:59:41.863778 Jitter Meter : NO K
4825 09:59:41.863860 CBT Training : PASS
4826 09:59:41.866800 Write leveling : PASS
4827 09:59:41.870487 RX DQS gating : PASS
4828 09:59:41.870569 RX DQ/DQS(RDDQC) : PASS
4829 09:59:41.873626 TX DQ/DQS : PASS
4830 09:59:41.873709 RX DATLAT : PASS
4831 09:59:41.876982 RX DQ/DQS(Engine): PASS
4832 09:59:41.880054 TX OE : NO K
4833 09:59:41.880137 All Pass.
4834 09:59:41.880201
4835 09:59:41.880261 CH 1, Rank 0
4836 09:59:41.883458 SW Impedance : PASS
4837 09:59:41.886927 DUTY Scan : NO K
4838 09:59:41.887009 ZQ Calibration : PASS
4839 09:59:41.890248 Jitter Meter : NO K
4840 09:59:41.894117 CBT Training : PASS
4841 09:59:41.894200 Write leveling : PASS
4842 09:59:41.896727 RX DQS gating : PASS
4843 09:59:41.900344 RX DQ/DQS(RDDQC) : PASS
4844 09:59:41.900426 TX DQ/DQS : PASS
4845 09:59:41.903524 RX DATLAT : PASS
4846 09:59:41.906826 RX DQ/DQS(Engine): PASS
4847 09:59:41.906909 TX OE : NO K
4848 09:59:41.910373 All Pass.
4849 09:59:41.910454
4850 09:59:41.910518 CH 1, Rank 1
4851 09:59:41.913416 SW Impedance : PASS
4852 09:59:41.913498 DUTY Scan : NO K
4853 09:59:41.917160 ZQ Calibration : PASS
4854 09:59:41.920286 Jitter Meter : NO K
4855 09:59:41.920368 CBT Training : PASS
4856 09:59:41.923203 Write leveling : PASS
4857 09:59:41.926816 RX DQS gating : PASS
4858 09:59:41.926898 RX DQ/DQS(RDDQC) : PASS
4859 09:59:41.929805 TX DQ/DQS : PASS
4860 09:59:41.929887 RX DATLAT : PASS
4861 09:59:41.933444 RX DQ/DQS(Engine): PASS
4862 09:59:41.936646 TX OE : NO K
4863 09:59:41.936728 All Pass.
4864 09:59:41.936792
4865 09:59:41.939877 DramC Write-DBI off
4866 09:59:41.939958 PER_BANK_REFRESH: Hybrid Mode
4867 09:59:41.943249 TX_TRACKING: ON
4868 09:59:41.966179 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4869 09:59:41.966319 [FAST_K] Save calibration result to emmc
4870 09:59:41.966411 dramc_set_vcore_voltage set vcore to 662500
4871 09:59:41.966517 Read voltage for 933, 3
4872 09:59:41.966618 Vio18 = 0
4873 09:59:41.966678 Vcore = 662500
4874 09:59:41.966736 Vdram = 0
4875 09:59:41.966984 Vddq = 0
4876 09:59:41.967046 Vmddr = 0
4877 09:59:41.969984 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4878 09:59:41.976915 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4879 09:59:41.979714 MEM_TYPE=3, freq_sel=17
4880 09:59:41.983321 sv_algorithm_assistance_LP4_1600
4881 09:59:41.986385 ============ PULL DRAM RESETB DOWN ============
4882 09:59:41.990056 ========== PULL DRAM RESETB DOWN end =========
4883 09:59:41.996640 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4884 09:59:42.000071 ===================================
4885 09:59:42.000156 LPDDR4 DRAM CONFIGURATION
4886 09:59:42.003358 ===================================
4887 09:59:42.006531 EX_ROW_EN[0] = 0x0
4888 09:59:42.006615 EX_ROW_EN[1] = 0x0
4889 09:59:42.009618 LP4Y_EN = 0x0
4890 09:59:42.009714 WORK_FSP = 0x0
4891 09:59:42.013611 WL = 0x3
4892 09:59:42.013735 RL = 0x3
4893 09:59:42.016341 BL = 0x2
4894 09:59:42.020026 RPST = 0x0
4895 09:59:42.020109 RD_PRE = 0x0
4896 09:59:42.023579 WR_PRE = 0x1
4897 09:59:42.023661 WR_PST = 0x0
4898 09:59:42.026610 DBI_WR = 0x0
4899 09:59:42.026692 DBI_RD = 0x0
4900 09:59:42.029710 OTF = 0x1
4901 09:59:42.033182 ===================================
4902 09:59:42.036196 ===================================
4903 09:59:42.036279 ANA top config
4904 09:59:42.040286 ===================================
4905 09:59:42.043318 DLL_ASYNC_EN = 0
4906 09:59:42.046338 ALL_SLAVE_EN = 1
4907 09:59:42.046420 NEW_RANK_MODE = 1
4908 09:59:42.049573 DLL_IDLE_MODE = 1
4909 09:59:42.053157 LP45_APHY_COMB_EN = 1
4910 09:59:42.056189 TX_ODT_DIS = 1
4911 09:59:42.056272 NEW_8X_MODE = 1
4912 09:59:42.059660 ===================================
4913 09:59:42.063106 ===================================
4914 09:59:42.066283 data_rate = 1866
4915 09:59:42.069635 CKR = 1
4916 09:59:42.072923 DQ_P2S_RATIO = 8
4917 09:59:42.076296 ===================================
4918 09:59:42.079394 CA_P2S_RATIO = 8
4919 09:59:42.082986 DQ_CA_OPEN = 0
4920 09:59:42.083069 DQ_SEMI_OPEN = 0
4921 09:59:42.086306 CA_SEMI_OPEN = 0
4922 09:59:42.089514 CA_FULL_RATE = 0
4923 09:59:42.092685 DQ_CKDIV4_EN = 1
4924 09:59:42.095974 CA_CKDIV4_EN = 1
4925 09:59:42.099483 CA_PREDIV_EN = 0
4926 09:59:42.099569 PH8_DLY = 0
4927 09:59:42.103230 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4928 09:59:42.105950 DQ_AAMCK_DIV = 4
4929 09:59:42.109308 CA_AAMCK_DIV = 4
4930 09:59:42.112593 CA_ADMCK_DIV = 4
4931 09:59:42.116246 DQ_TRACK_CA_EN = 0
4932 09:59:42.119296 CA_PICK = 933
4933 09:59:42.119380 CA_MCKIO = 933
4934 09:59:42.123057 MCKIO_SEMI = 0
4935 09:59:42.126072 PLL_FREQ = 3732
4936 09:59:42.129327 DQ_UI_PI_RATIO = 32
4937 09:59:42.132917 CA_UI_PI_RATIO = 0
4938 09:59:42.135916 ===================================
4939 09:59:42.139471 ===================================
4940 09:59:42.139555 memory_type:LPDDR4
4941 09:59:42.142759 GP_NUM : 10
4942 09:59:42.145868 SRAM_EN : 1
4943 09:59:42.145950 MD32_EN : 0
4944 09:59:42.149799 ===================================
4945 09:59:42.152813 [ANA_INIT] >>>>>>>>>>>>>>
4946 09:59:42.155824 <<<<<< [CONFIGURE PHASE]: ANA_TX
4947 09:59:42.159382 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4948 09:59:42.162511 ===================================
4949 09:59:42.166240 data_rate = 1866,PCW = 0X8f00
4950 09:59:42.169184 ===================================
4951 09:59:42.172317 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4952 09:59:42.176159 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4953 09:59:42.182216 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4954 09:59:42.185808 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4955 09:59:42.192311 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4956 09:59:42.196063 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4957 09:59:42.196150 [ANA_INIT] flow start
4958 09:59:42.199359 [ANA_INIT] PLL >>>>>>>>
4959 09:59:42.202482 [ANA_INIT] PLL <<<<<<<<
4960 09:59:42.202564 [ANA_INIT] MIDPI >>>>>>>>
4961 09:59:42.205492 [ANA_INIT] MIDPI <<<<<<<<
4962 09:59:42.209087 [ANA_INIT] DLL >>>>>>>>
4963 09:59:42.209169 [ANA_INIT] flow end
4964 09:59:42.215535 ============ LP4 DIFF to SE enter ============
4965 09:59:42.218873 ============ LP4 DIFF to SE exit ============
4966 09:59:42.218955 [ANA_INIT] <<<<<<<<<<<<<
4967 09:59:42.222024 [Flow] Enable top DCM control >>>>>
4968 09:59:42.225156 [Flow] Enable top DCM control <<<<<
4969 09:59:42.228544 Enable DLL master slave shuffle
4970 09:59:42.235439 ==============================================================
4971 09:59:42.239094 Gating Mode config
4972 09:59:42.241791 ==============================================================
4973 09:59:42.245414 Config description:
4974 09:59:42.255292 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4975 09:59:42.261982 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4976 09:59:42.265105 SELPH_MODE 0: By rank 1: By Phase
4977 09:59:42.271875 ==============================================================
4978 09:59:42.274881 GAT_TRACK_EN = 1
4979 09:59:42.278779 RX_GATING_MODE = 2
4980 09:59:42.281907 RX_GATING_TRACK_MODE = 2
4981 09:59:42.282002 SELPH_MODE = 1
4982 09:59:42.284996 PICG_EARLY_EN = 1
4983 09:59:42.288303 VALID_LAT_VALUE = 1
4984 09:59:42.295746 ==============================================================
4985 09:59:42.298918 Enter into Gating configuration >>>>
4986 09:59:42.301838 Exit from Gating configuration <<<<
4987 09:59:42.305176 Enter into DVFS_PRE_config >>>>>
4988 09:59:42.315256 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4989 09:59:42.318458 Exit from DVFS_PRE_config <<<<<
4990 09:59:42.321737 Enter into PICG configuration >>>>
4991 09:59:42.325003 Exit from PICG configuration <<<<
4992 09:59:42.328177 [RX_INPUT] configuration >>>>>
4993 09:59:42.331789 [RX_INPUT] configuration <<<<<
4994 09:59:42.335257 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4995 09:59:42.341709 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4996 09:59:42.348190 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4997 09:59:42.355024 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4998 09:59:42.358383 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4999 09:59:42.364788 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5000 09:59:42.368895 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5001 09:59:42.375315 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5002 09:59:42.378392 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5003 09:59:42.381525 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5004 09:59:42.385416 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5005 09:59:42.391487 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5006 09:59:42.395283 ===================================
5007 09:59:42.395367 LPDDR4 DRAM CONFIGURATION
5008 09:59:42.398045 ===================================
5009 09:59:42.401545 EX_ROW_EN[0] = 0x0
5010 09:59:42.404875 EX_ROW_EN[1] = 0x0
5011 09:59:42.404960 LP4Y_EN = 0x0
5012 09:59:42.408310 WORK_FSP = 0x0
5013 09:59:42.408391 WL = 0x3
5014 09:59:42.411428 RL = 0x3
5015 09:59:42.411510 BL = 0x2
5016 09:59:42.415370 RPST = 0x0
5017 09:59:42.415452 RD_PRE = 0x0
5018 09:59:42.418092 WR_PRE = 0x1
5019 09:59:42.418173 WR_PST = 0x0
5020 09:59:42.421353 DBI_WR = 0x0
5021 09:59:42.421436 DBI_RD = 0x0
5022 09:59:42.425098 OTF = 0x1
5023 09:59:42.428035 ===================================
5024 09:59:42.431192 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5025 09:59:42.434781 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5026 09:59:42.441678 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5027 09:59:42.444671 ===================================
5028 09:59:42.444762 LPDDR4 DRAM CONFIGURATION
5029 09:59:42.447755 ===================================
5030 09:59:42.451715 EX_ROW_EN[0] = 0x10
5031 09:59:42.454483 EX_ROW_EN[1] = 0x0
5032 09:59:42.454556 LP4Y_EN = 0x0
5033 09:59:42.457995 WORK_FSP = 0x0
5034 09:59:42.458069 WL = 0x3
5035 09:59:42.461336 RL = 0x3
5036 09:59:42.461422 BL = 0x2
5037 09:59:42.464468 RPST = 0x0
5038 09:59:42.464540 RD_PRE = 0x0
5039 09:59:42.467802 WR_PRE = 0x1
5040 09:59:42.467882 WR_PST = 0x0
5041 09:59:42.471368 DBI_WR = 0x0
5042 09:59:42.471440 DBI_RD = 0x0
5043 09:59:42.474827 OTF = 0x1
5044 09:59:42.478015 ===================================
5045 09:59:42.484275 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5046 09:59:42.487856 nWR fixed to 30
5047 09:59:42.487944 [ModeRegInit_LP4] CH0 RK0
5048 09:59:42.491159 [ModeRegInit_LP4] CH0 RK1
5049 09:59:42.494224 [ModeRegInit_LP4] CH1 RK0
5050 09:59:42.497478 [ModeRegInit_LP4] CH1 RK1
5051 09:59:42.497612 match AC timing 9
5052 09:59:42.501193 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5053 09:59:42.508058 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5054 09:59:42.510994 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5055 09:59:42.517663 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5056 09:59:42.520715 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5057 09:59:42.520888 ==
5058 09:59:42.524101 Dram Type= 6, Freq= 0, CH_0, rank 0
5059 09:59:42.527587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5060 09:59:42.527671 ==
5061 09:59:42.534403 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5062 09:59:42.541054 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5063 09:59:42.544107 [CA 0] Center 37 (6~68) winsize 63
5064 09:59:42.547933 [CA 1] Center 37 (7~68) winsize 62
5065 09:59:42.551102 [CA 2] Center 34 (4~65) winsize 62
5066 09:59:42.554014 [CA 3] Center 34 (3~65) winsize 63
5067 09:59:42.557700 [CA 4] Center 33 (3~64) winsize 62
5068 09:59:42.560893 [CA 5] Center 32 (2~62) winsize 61
5069 09:59:42.560976
5070 09:59:42.564427 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5071 09:59:42.564512
5072 09:59:42.567922 [CATrainingPosCal] consider 1 rank data
5073 09:59:42.570859 u2DelayCellTimex100 = 270/100 ps
5074 09:59:42.574468 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5075 09:59:42.577847 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5076 09:59:42.580723 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5077 09:59:42.584151 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5078 09:59:42.587262 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5079 09:59:42.590813 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5080 09:59:42.590902
5081 09:59:42.597267 CA PerBit enable=1, Macro0, CA PI delay=32
5082 09:59:42.597434
5083 09:59:42.597519 [CBTSetCACLKResult] CA Dly = 32
5084 09:59:42.600930 CS Dly: 5 (0~36)
5085 09:59:42.601006 ==
5086 09:59:42.604295 Dram Type= 6, Freq= 0, CH_0, rank 1
5087 09:59:42.607420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5088 09:59:42.607504 ==
5089 09:59:42.614143 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5090 09:59:42.620401 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5091 09:59:42.623815 [CA 0] Center 37 (6~68) winsize 63
5092 09:59:42.627621 [CA 1] Center 37 (6~68) winsize 63
5093 09:59:42.630330 [CA 2] Center 34 (4~65) winsize 62
5094 09:59:42.633505 [CA 3] Center 34 (3~65) winsize 63
5095 09:59:42.637428 [CA 4] Center 32 (2~63) winsize 62
5096 09:59:42.640352 [CA 5] Center 32 (2~63) winsize 62
5097 09:59:42.640437
5098 09:59:42.643464 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5099 09:59:42.643547
5100 09:59:42.647121 [CATrainingPosCal] consider 2 rank data
5101 09:59:42.650308 u2DelayCellTimex100 = 270/100 ps
5102 09:59:42.653603 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5103 09:59:42.657224 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5104 09:59:42.660315 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5105 09:59:42.663966 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5106 09:59:42.666937 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5107 09:59:42.673288 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5108 09:59:42.673376
5109 09:59:42.676864 CA PerBit enable=1, Macro0, CA PI delay=32
5110 09:59:42.676948
5111 09:59:42.679970 [CBTSetCACLKResult] CA Dly = 32
5112 09:59:42.680053 CS Dly: 5 (0~37)
5113 09:59:42.680119
5114 09:59:42.683219 ----->DramcWriteLeveling(PI) begin...
5115 09:59:42.683303 ==
5116 09:59:42.686788 Dram Type= 6, Freq= 0, CH_0, rank 0
5117 09:59:42.689893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5118 09:59:42.693223 ==
5119 09:59:42.693349 Write leveling (Byte 0): 34 => 34
5120 09:59:42.696509 Write leveling (Byte 1): 30 => 30
5121 09:59:42.700169 DramcWriteLeveling(PI) end<-----
5122 09:59:42.700243
5123 09:59:42.700311 ==
5124 09:59:42.703451 Dram Type= 6, Freq= 0, CH_0, rank 0
5125 09:59:42.709974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5126 09:59:42.710067 ==
5127 09:59:42.710134 [Gating] SW mode calibration
5128 09:59:42.720110 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5129 09:59:42.723235 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5130 09:59:42.729770 0 14 0 | B1->B0 | 2b2b 3434 | 1 1 | (0 0) (1 1)
5131 09:59:42.733243 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5132 09:59:42.736175 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5133 09:59:42.743325 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5134 09:59:42.746118 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5135 09:59:42.749634 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5136 09:59:42.756627 0 14 24 | B1->B0 | 3434 3030 | 1 0 | (1 1) (1 0)
5137 09:59:42.759781 0 14 28 | B1->B0 | 3232 2525 | 0 0 | (0 1) (0 0)
5138 09:59:42.762762 0 15 0 | B1->B0 | 2b2b 2323 | 0 0 | (0 1) (0 0)
5139 09:59:42.769415 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5140 09:59:42.772495 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5141 09:59:42.776286 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5142 09:59:42.782805 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5143 09:59:42.786197 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5144 09:59:42.789105 0 15 24 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
5145 09:59:42.795873 0 15 28 | B1->B0 | 2c2c 4545 | 0 0 | (0 0) (0 0)
5146 09:59:42.799158 1 0 0 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
5147 09:59:42.802227 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5148 09:59:42.808898 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5149 09:59:42.812437 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5150 09:59:42.815401 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5151 09:59:42.822330 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5152 09:59:42.825800 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5153 09:59:42.828993 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5154 09:59:42.832530 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5155 09:59:42.839308 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 09:59:42.842225 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 09:59:42.845322 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5158 09:59:42.852582 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5159 09:59:42.855511 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5160 09:59:42.858613 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 09:59:42.865216 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 09:59:42.869202 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 09:59:42.872037 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 09:59:42.879389 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5165 09:59:42.882265 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5166 09:59:42.885309 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5167 09:59:42.892117 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5168 09:59:42.895715 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5169 09:59:42.898714 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5170 09:59:42.905323 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5171 09:59:42.905439 Total UI for P1: 0, mck2ui 16
5172 09:59:42.912426 best dqsien dly found for B0: ( 1, 2, 26)
5173 09:59:42.912507 Total UI for P1: 0, mck2ui 16
5174 09:59:42.915316 best dqsien dly found for B1: ( 1, 2, 30)
5175 09:59:42.921940 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5176 09:59:42.925759 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5177 09:59:42.925839
5178 09:59:42.928891 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5179 09:59:42.931990 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5180 09:59:42.935634 [Gating] SW calibration Done
5181 09:59:42.935708 ==
5182 09:59:42.938860 Dram Type= 6, Freq= 0, CH_0, rank 0
5183 09:59:42.942048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5184 09:59:42.942124 ==
5185 09:59:42.945561 RX Vref Scan: 0
5186 09:59:42.945683
5187 09:59:42.945744 RX Vref 0 -> 0, step: 1
5188 09:59:42.945801
5189 09:59:42.949147 RX Delay -80 -> 252, step: 8
5190 09:59:42.952576 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5191 09:59:42.958754 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5192 09:59:42.962391 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5193 09:59:42.965762 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5194 09:59:42.969145 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5195 09:59:42.972481 iDelay=208, Bit 5, Center 95 (8 ~ 183) 176
5196 09:59:42.975458 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5197 09:59:42.979186 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5198 09:59:42.985461 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5199 09:59:42.988826 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5200 09:59:42.992098 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5201 09:59:42.995567 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5202 09:59:42.998637 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5203 09:59:43.002479 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5204 09:59:43.009000 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5205 09:59:43.011955 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5206 09:59:43.012035 ==
5207 09:59:43.015745 Dram Type= 6, Freq= 0, CH_0, rank 0
5208 09:59:43.018550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5209 09:59:43.018649 ==
5210 09:59:43.022062 DQS Delay:
5211 09:59:43.022146 DQS0 = 0, DQS1 = 0
5212 09:59:43.022220 DQM Delay:
5213 09:59:43.025459 DQM0 = 104, DQM1 = 95
5214 09:59:43.025541 DQ Delay:
5215 09:59:43.028439 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5216 09:59:43.031719 DQ4 =107, DQ5 =95, DQ6 =111, DQ7 =111
5217 09:59:43.035427 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =91
5218 09:59:43.038567 DQ12 =99, DQ13 =103, DQ14 =103, DQ15 =99
5219 09:59:43.038651
5220 09:59:43.038714
5221 09:59:43.042293 ==
5222 09:59:43.045433 Dram Type= 6, Freq= 0, CH_0, rank 0
5223 09:59:43.048518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5224 09:59:43.048588 ==
5225 09:59:43.048648
5226 09:59:43.048704
5227 09:59:43.052091 TX Vref Scan disable
5228 09:59:43.052162 == TX Byte 0 ==
5229 09:59:43.055161 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5230 09:59:43.061896 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5231 09:59:43.061977 == TX Byte 1 ==
5232 09:59:43.065043 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5233 09:59:43.071717 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5234 09:59:43.071795 ==
5235 09:59:43.075251 Dram Type= 6, Freq= 0, CH_0, rank 0
5236 09:59:43.078673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5237 09:59:43.078745 ==
5238 09:59:43.078806
5239 09:59:43.078868
5240 09:59:43.082159 TX Vref Scan disable
5241 09:59:43.084941 == TX Byte 0 ==
5242 09:59:43.088576 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5243 09:59:43.092097 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5244 09:59:43.095232 == TX Byte 1 ==
5245 09:59:43.098278 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5246 09:59:43.101713 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5247 09:59:43.101784
5248 09:59:43.105287 [DATLAT]
5249 09:59:43.105361 Freq=933, CH0 RK0
5250 09:59:43.105421
5251 09:59:43.108438 DATLAT Default: 0xd
5252 09:59:43.108506 0, 0xFFFF, sum = 0
5253 09:59:43.111537 1, 0xFFFF, sum = 0
5254 09:59:43.111613 2, 0xFFFF, sum = 0
5255 09:59:43.115027 3, 0xFFFF, sum = 0
5256 09:59:43.115096 4, 0xFFFF, sum = 0
5257 09:59:43.118695 5, 0xFFFF, sum = 0
5258 09:59:43.118776 6, 0xFFFF, sum = 0
5259 09:59:43.121587 7, 0xFFFF, sum = 0
5260 09:59:43.121683 8, 0xFFFF, sum = 0
5261 09:59:43.124981 9, 0xFFFF, sum = 0
5262 09:59:43.125059 10, 0x0, sum = 1
5263 09:59:43.128418 11, 0x0, sum = 2
5264 09:59:43.128492 12, 0x0, sum = 3
5265 09:59:43.131828 13, 0x0, sum = 4
5266 09:59:43.131906 best_step = 11
5267 09:59:43.131966
5268 09:59:43.132023 ==
5269 09:59:43.135092 Dram Type= 6, Freq= 0, CH_0, rank 0
5270 09:59:43.138083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5271 09:59:43.141587 ==
5272 09:59:43.141676 RX Vref Scan: 1
5273 09:59:43.141737
5274 09:59:43.144937 RX Vref 0 -> 0, step: 1
5275 09:59:43.145006
5276 09:59:43.148211 RX Delay -45 -> 252, step: 4
5277 09:59:43.148280
5278 09:59:43.151486 Set Vref, RX VrefLevel [Byte0]: 53
5279 09:59:43.154914 [Byte1]: 46
5280 09:59:43.154984
5281 09:59:43.158001 Final RX Vref Byte 0 = 53 to rank0
5282 09:59:43.161129 Final RX Vref Byte 1 = 46 to rank0
5283 09:59:43.164633 Final RX Vref Byte 0 = 53 to rank1
5284 09:59:43.168007 Final RX Vref Byte 1 = 46 to rank1==
5285 09:59:43.171904 Dram Type= 6, Freq= 0, CH_0, rank 0
5286 09:59:43.175015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5287 09:59:43.175087 ==
5288 09:59:43.178121 DQS Delay:
5289 09:59:43.178194 DQS0 = 0, DQS1 = 0
5290 09:59:43.178260 DQM Delay:
5291 09:59:43.181318 DQM0 = 104, DQM1 = 94
5292 09:59:43.181403 DQ Delay:
5293 09:59:43.184340 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =102
5294 09:59:43.188125 DQ4 =104, DQ5 =96, DQ6 =112, DQ7 =112
5295 09:59:43.190987 DQ8 =84, DQ9 =86, DQ10 =96, DQ11 =88
5296 09:59:43.194510 DQ12 =98, DQ13 =98, DQ14 =106, DQ15 =102
5297 09:59:43.194592
5298 09:59:43.197511
5299 09:59:43.204147 [DQSOSCAuto] RK0, (LSB)MR18= 0x3027, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 406 ps
5300 09:59:43.207502 CH0 RK0: MR19=505, MR18=3027
5301 09:59:43.214295 CH0_RK0: MR19=0x505, MR18=0x3027, DQSOSC=406, MR23=63, INC=65, DEC=43
5302 09:59:43.214374
5303 09:59:43.217361 ----->DramcWriteLeveling(PI) begin...
5304 09:59:43.217439 ==
5305 09:59:43.220846 Dram Type= 6, Freq= 0, CH_0, rank 1
5306 09:59:43.224239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5307 09:59:43.224321 ==
5308 09:59:43.227629 Write leveling (Byte 0): 35 => 35
5309 09:59:43.230721 Write leveling (Byte 1): 29 => 29
5310 09:59:43.234435 DramcWriteLeveling(PI) end<-----
5311 09:59:43.234516
5312 09:59:43.234578 ==
5313 09:59:43.237642 Dram Type= 6, Freq= 0, CH_0, rank 1
5314 09:59:43.240659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5315 09:59:43.240737 ==
5316 09:59:43.243959 [Gating] SW mode calibration
5317 09:59:43.250637 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5318 09:59:43.257574 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5319 09:59:43.260429 0 14 0 | B1->B0 | 3333 3333 | 1 1 | (1 1) (1 1)
5320 09:59:43.263758 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5321 09:59:43.270769 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5322 09:59:43.273847 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5323 09:59:43.277135 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5324 09:59:43.284108 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5325 09:59:43.286990 0 14 24 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
5326 09:59:43.290510 0 14 28 | B1->B0 | 2828 2b2b | 0 1 | (0 1) (1 0)
5327 09:59:43.297365 0 15 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5328 09:59:43.300262 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5329 09:59:43.303890 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5330 09:59:43.310708 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5331 09:59:43.314068 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5332 09:59:43.317126 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5333 09:59:43.323620 0 15 24 | B1->B0 | 2525 2424 | 0 0 | (0 0) (0 0)
5334 09:59:43.327074 0 15 28 | B1->B0 | 3d3d 3130 | 0 1 | (0 0) (0 0)
5335 09:59:43.330228 1 0 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
5336 09:59:43.337341 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5337 09:59:43.340501 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5338 09:59:43.343560 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5339 09:59:43.347275 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5340 09:59:43.353651 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5341 09:59:43.357323 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5342 09:59:43.360319 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5343 09:59:43.367204 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5344 09:59:43.370645 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5345 09:59:43.373641 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5346 09:59:43.380463 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5347 09:59:43.384046 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5348 09:59:43.386984 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5349 09:59:43.393405 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5350 09:59:43.396840 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5351 09:59:43.400527 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5352 09:59:43.406911 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5353 09:59:43.410213 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5354 09:59:43.413603 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5355 09:59:43.420271 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5356 09:59:43.423849 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5357 09:59:43.426964 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5358 09:59:43.433526 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5359 09:59:43.433651 Total UI for P1: 0, mck2ui 16
5360 09:59:43.440141 best dqsien dly found for B0: ( 1, 2, 26)
5361 09:59:43.443468 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5362 09:59:43.446592 Total UI for P1: 0, mck2ui 16
5363 09:59:43.449621 best dqsien dly found for B1: ( 1, 2, 28)
5364 09:59:43.453260 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5365 09:59:43.456353 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5366 09:59:43.456434
5367 09:59:43.459982 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5368 09:59:43.463301 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5369 09:59:43.466500 [Gating] SW calibration Done
5370 09:59:43.466582 ==
5371 09:59:43.470153 Dram Type= 6, Freq= 0, CH_0, rank 1
5372 09:59:43.473312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5373 09:59:43.476176 ==
5374 09:59:43.476258 RX Vref Scan: 0
5375 09:59:43.476321
5376 09:59:43.479785 RX Vref 0 -> 0, step: 1
5377 09:59:43.479867
5378 09:59:43.482904 RX Delay -80 -> 252, step: 8
5379 09:59:43.486712 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5380 09:59:43.489707 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5381 09:59:43.492992 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5382 09:59:43.496705 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5383 09:59:43.499545 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5384 09:59:43.506241 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5385 09:59:43.509763 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5386 09:59:43.512747 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5387 09:59:43.516053 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5388 09:59:43.519891 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5389 09:59:43.522831 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5390 09:59:43.529464 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5391 09:59:43.532926 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5392 09:59:43.536589 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5393 09:59:43.539510 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5394 09:59:43.543030 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5395 09:59:43.543123 ==
5396 09:59:43.546720 Dram Type= 6, Freq= 0, CH_0, rank 1
5397 09:59:43.552780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5398 09:59:43.552879 ==
5399 09:59:43.552945 DQS Delay:
5400 09:59:43.556421 DQS0 = 0, DQS1 = 0
5401 09:59:43.556503 DQM Delay:
5402 09:59:43.559582 DQM0 = 104, DQM1 = 94
5403 09:59:43.559664 DQ Delay:
5404 09:59:43.562580 DQ0 =103, DQ1 =107, DQ2 =103, DQ3 =99
5405 09:59:43.566574 DQ4 =103, DQ5 =95, DQ6 =107, DQ7 =115
5406 09:59:43.569693 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =87
5407 09:59:43.572654 DQ12 =95, DQ13 =99, DQ14 =103, DQ15 =99
5408 09:59:43.572738
5409 09:59:43.572802
5410 09:59:43.572860 ==
5411 09:59:43.576289 Dram Type= 6, Freq= 0, CH_0, rank 1
5412 09:59:43.579483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5413 09:59:43.579566 ==
5414 09:59:43.579631
5415 09:59:43.579691
5416 09:59:43.582584 TX Vref Scan disable
5417 09:59:43.586035 == TX Byte 0 ==
5418 09:59:43.589604 Update DQ dly =719 (2 ,6, 15) DQ OEN =(2 ,3)
5419 09:59:43.592758 Update DQM dly =719 (2 ,6, 15) DQM OEN =(2 ,3)
5420 09:59:43.596148 == TX Byte 1 ==
5421 09:59:43.599588 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5422 09:59:43.602945 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5423 09:59:43.603047 ==
5424 09:59:43.606121 Dram Type= 6, Freq= 0, CH_0, rank 1
5425 09:59:43.612938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5426 09:59:43.613028 ==
5427 09:59:43.613094
5428 09:59:43.613153
5429 09:59:43.613210 TX Vref Scan disable
5430 09:59:43.616738 == TX Byte 0 ==
5431 09:59:43.620025 Update DQ dly =719 (2 ,6, 15) DQ OEN =(2 ,3)
5432 09:59:43.623431 Update DQM dly =719 (2 ,6, 15) DQM OEN =(2 ,3)
5433 09:59:43.626990 == TX Byte 1 ==
5434 09:59:43.630094 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5435 09:59:43.633209 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5436 09:59:43.636603
5437 09:59:43.636694 [DATLAT]
5438 09:59:43.636761 Freq=933, CH0 RK1
5439 09:59:43.636821
5440 09:59:43.640677 DATLAT Default: 0xb
5441 09:59:43.640766 0, 0xFFFF, sum = 0
5442 09:59:43.643555 1, 0xFFFF, sum = 0
5443 09:59:43.643642 2, 0xFFFF, sum = 0
5444 09:59:43.646570 3, 0xFFFF, sum = 0
5445 09:59:43.650045 4, 0xFFFF, sum = 0
5446 09:59:43.650149 5, 0xFFFF, sum = 0
5447 09:59:43.652982 6, 0xFFFF, sum = 0
5448 09:59:43.653069 7, 0xFFFF, sum = 0
5449 09:59:43.656206 8, 0xFFFF, sum = 0
5450 09:59:43.656290 9, 0xFFFF, sum = 0
5451 09:59:43.659958 10, 0x0, sum = 1
5452 09:59:43.660046 11, 0x0, sum = 2
5453 09:59:43.662945 12, 0x0, sum = 3
5454 09:59:43.663030 13, 0x0, sum = 4
5455 09:59:43.663095 best_step = 11
5456 09:59:43.663154
5457 09:59:43.666388 ==
5458 09:59:43.669506 Dram Type= 6, Freq= 0, CH_0, rank 1
5459 09:59:43.673158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5460 09:59:43.673245 ==
5461 09:59:43.673309 RX Vref Scan: 0
5462 09:59:43.673372
5463 09:59:43.676123 RX Vref 0 -> 0, step: 1
5464 09:59:43.676205
5465 09:59:43.679518 RX Delay -45 -> 252, step: 4
5466 09:59:43.683100 iDelay=199, Bit 0, Center 102 (15 ~ 190) 176
5467 09:59:43.689383 iDelay=199, Bit 1, Center 108 (23 ~ 194) 172
5468 09:59:43.692917 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5469 09:59:43.696353 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5470 09:59:43.699373 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5471 09:59:43.703167 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5472 09:59:43.709723 iDelay=199, Bit 6, Center 108 (23 ~ 194) 172
5473 09:59:43.712941 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5474 09:59:43.716596 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5475 09:59:43.719602 iDelay=199, Bit 9, Center 82 (-1 ~ 166) 168
5476 09:59:43.722986 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5477 09:59:43.726054 iDelay=199, Bit 11, Center 86 (3 ~ 170) 168
5478 09:59:43.732773 iDelay=199, Bit 12, Center 100 (19 ~ 182) 164
5479 09:59:43.736205 iDelay=199, Bit 13, Center 98 (15 ~ 182) 168
5480 09:59:43.739629 iDelay=199, Bit 14, Center 104 (23 ~ 186) 164
5481 09:59:43.743110 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5482 09:59:43.743194 ==
5483 09:59:43.746484 Dram Type= 6, Freq= 0, CH_0, rank 1
5484 09:59:43.752711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5485 09:59:43.752800 ==
5486 09:59:43.752866 DQS Delay:
5487 09:59:43.756025 DQS0 = 0, DQS1 = 0
5488 09:59:43.756106 DQM Delay:
5489 09:59:43.756168 DQM0 = 104, DQM1 = 93
5490 09:59:43.759419 DQ Delay:
5491 09:59:43.762467 DQ0 =102, DQ1 =108, DQ2 =102, DQ3 =102
5492 09:59:43.765734 DQ4 =106, DQ5 =98, DQ6 =108, DQ7 =112
5493 09:59:43.769323 DQ8 =84, DQ9 =82, DQ10 =94, DQ11 =86
5494 09:59:43.772959 DQ12 =100, DQ13 =98, DQ14 =104, DQ15 =102
5495 09:59:43.773038
5496 09:59:43.773104
5497 09:59:43.778957 [DQSOSCAuto] RK1, (LSB)MR18= 0x26ff, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 409 ps
5498 09:59:43.782717 CH0 RK1: MR19=504, MR18=26FF
5499 09:59:43.788967 CH0_RK1: MR19=0x504, MR18=0x26FF, DQSOSC=409, MR23=63, INC=64, DEC=43
5500 09:59:43.792608 [RxdqsGatingPostProcess] freq 933
5501 09:59:43.798962 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5502 09:59:43.802447 best DQS0 dly(2T, 0.5T) = (0, 10)
5503 09:59:43.805750 best DQS1 dly(2T, 0.5T) = (0, 10)
5504 09:59:43.809057 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5505 09:59:43.809135 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5506 09:59:43.812587 best DQS0 dly(2T, 0.5T) = (0, 10)
5507 09:59:43.815659 best DQS1 dly(2T, 0.5T) = (0, 10)
5508 09:59:43.819399 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5509 09:59:43.822331 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5510 09:59:43.825863 Pre-setting of DQS Precalculation
5511 09:59:43.832071 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5512 09:59:43.832157 ==
5513 09:59:43.835618 Dram Type= 6, Freq= 0, CH_1, rank 0
5514 09:59:43.839217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5515 09:59:43.839314 ==
5516 09:59:43.845304 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5517 09:59:43.849205 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5518 09:59:43.853312 [CA 0] Center 36 (6~67) winsize 62
5519 09:59:43.856747 [CA 1] Center 36 (6~67) winsize 62
5520 09:59:43.860259 [CA 2] Center 34 (4~65) winsize 62
5521 09:59:43.863104 [CA 3] Center 34 (4~64) winsize 61
5522 09:59:43.866491 [CA 4] Center 34 (4~65) winsize 62
5523 09:59:43.869763 [CA 5] Center 33 (3~64) winsize 62
5524 09:59:43.869847
5525 09:59:43.873078 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5526 09:59:43.873164
5527 09:59:43.876345 [CATrainingPosCal] consider 1 rank data
5528 09:59:43.879999 u2DelayCellTimex100 = 270/100 ps
5529 09:59:43.883011 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5530 09:59:43.886809 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5531 09:59:43.893476 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5532 09:59:43.896580 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5533 09:59:43.899709 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5534 09:59:43.903400 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5535 09:59:43.903479
5536 09:59:43.906428 CA PerBit enable=1, Macro0, CA PI delay=33
5537 09:59:43.906501
5538 09:59:43.909471 [CBTSetCACLKResult] CA Dly = 33
5539 09:59:43.909540 CS Dly: 7 (0~38)
5540 09:59:43.912869 ==
5541 09:59:43.912956 Dram Type= 6, Freq= 0, CH_1, rank 1
5542 09:59:43.920036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5543 09:59:43.920123 ==
5544 09:59:43.922849 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5545 09:59:43.929837 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5546 09:59:43.932971 [CA 0] Center 37 (6~68) winsize 63
5547 09:59:43.936450 [CA 1] Center 37 (7~68) winsize 62
5548 09:59:43.939873 [CA 2] Center 35 (4~66) winsize 63
5549 09:59:43.943416 [CA 3] Center 34 (4~65) winsize 62
5550 09:59:43.946495 [CA 4] Center 34 (4~65) winsize 62
5551 09:59:43.950074 [CA 5] Center 33 (3~64) winsize 62
5552 09:59:43.950161
5553 09:59:43.953021 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5554 09:59:43.953102
5555 09:59:43.956450 [CATrainingPosCal] consider 2 rank data
5556 09:59:43.959606 u2DelayCellTimex100 = 270/100 ps
5557 09:59:43.963396 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5558 09:59:43.966278 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5559 09:59:43.973010 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5560 09:59:43.976862 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5561 09:59:43.979679 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5562 09:59:43.983086 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5563 09:59:43.983173
5564 09:59:43.986389 CA PerBit enable=1, Macro0, CA PI delay=33
5565 09:59:43.986502
5566 09:59:43.989668 [CBTSetCACLKResult] CA Dly = 33
5567 09:59:43.989751 CS Dly: 8 (0~40)
5568 09:59:43.989815
5569 09:59:43.993291 ----->DramcWriteLeveling(PI) begin...
5570 09:59:43.996309 ==
5571 09:59:44.000043 Dram Type= 6, Freq= 0, CH_1, rank 0
5572 09:59:44.003141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5573 09:59:44.003226 ==
5574 09:59:44.006899 Write leveling (Byte 0): 25 => 25
5575 09:59:44.009840 Write leveling (Byte 1): 28 => 28
5576 09:59:44.012833 DramcWriteLeveling(PI) end<-----
5577 09:59:44.012916
5578 09:59:44.012997 ==
5579 09:59:44.016340 Dram Type= 6, Freq= 0, CH_1, rank 0
5580 09:59:44.019348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5581 09:59:44.019450 ==
5582 09:59:44.022774 [Gating] SW mode calibration
5583 09:59:44.029611 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5584 09:59:44.035952 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5585 09:59:44.039194 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5586 09:59:44.042852 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5587 09:59:44.049230 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5588 09:59:44.053148 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5589 09:59:44.056086 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5590 09:59:44.062467 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5591 09:59:44.065744 0 14 24 | B1->B0 | 3333 2e2e | 1 1 | (1 0) (1 0)
5592 09:59:44.069088 0 14 28 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (0 0)
5593 09:59:44.076154 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5594 09:59:44.078885 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5595 09:59:44.082798 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5596 09:59:44.085795 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5597 09:59:44.092488 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5598 09:59:44.096127 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5599 09:59:44.099333 0 15 24 | B1->B0 | 2727 3232 | 0 0 | (0 0) (0 0)
5600 09:59:44.106114 0 15 28 | B1->B0 | 4040 4646 | 0 0 | (1 1) (0 0)
5601 09:59:44.108981 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5602 09:59:44.112387 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5603 09:59:44.119425 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5604 09:59:44.122754 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5605 09:59:44.125944 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5606 09:59:44.132609 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5607 09:59:44.135835 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 09:59:44.139523 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 09:59:44.146366 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5610 09:59:44.149262 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 09:59:44.152601 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 09:59:44.159355 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 09:59:44.162926 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5614 09:59:44.166071 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5615 09:59:44.169326 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 09:59:44.175924 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 09:59:44.179087 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 09:59:44.182656 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 09:59:44.188995 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 09:59:44.192749 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 09:59:44.195749 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 09:59:44.202430 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 09:59:44.205552 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5624 09:59:44.209226 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5625 09:59:44.212101 Total UI for P1: 0, mck2ui 16
5626 09:59:44.215560 best dqsien dly found for B0: ( 1, 2, 24)
5627 09:59:44.218832 Total UI for P1: 0, mck2ui 16
5628 09:59:44.222121 best dqsien dly found for B1: ( 1, 2, 24)
5629 09:59:44.225572 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5630 09:59:44.228747 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5631 09:59:44.232376
5632 09:59:44.235554 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5633 09:59:44.238701 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5634 09:59:44.242123 [Gating] SW calibration Done
5635 09:59:44.242258 ==
5636 09:59:44.245652 Dram Type= 6, Freq= 0, CH_1, rank 0
5637 09:59:44.248739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5638 09:59:44.248845 ==
5639 09:59:44.248914 RX Vref Scan: 0
5640 09:59:44.248975
5641 09:59:44.252522 RX Vref 0 -> 0, step: 1
5642 09:59:44.252627
5643 09:59:44.255442 RX Delay -80 -> 252, step: 8
5644 09:59:44.258974 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5645 09:59:44.262475 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5646 09:59:44.265620 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5647 09:59:44.272179 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5648 09:59:44.275600 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5649 09:59:44.278603 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5650 09:59:44.282150 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5651 09:59:44.285265 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5652 09:59:44.292057 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5653 09:59:44.295111 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5654 09:59:44.299044 iDelay=208, Bit 10, Center 103 (16 ~ 191) 176
5655 09:59:44.302020 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5656 09:59:44.305120 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5657 09:59:44.309092 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5658 09:59:44.315193 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5659 09:59:44.318722 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5660 09:59:44.318859 ==
5661 09:59:44.322161 Dram Type= 6, Freq= 0, CH_1, rank 0
5662 09:59:44.325005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5663 09:59:44.325106 ==
5664 09:59:44.328835 DQS Delay:
5665 09:59:44.328949 DQS0 = 0, DQS1 = 0
5666 09:59:44.331545 DQM Delay:
5667 09:59:44.331672 DQM0 = 103, DQM1 = 99
5668 09:59:44.331771 DQ Delay:
5669 09:59:44.335063 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =103
5670 09:59:44.338487 DQ4 =99, DQ5 =115, DQ6 =111, DQ7 =103
5671 09:59:44.341810 DQ8 =87, DQ9 =87, DQ10 =103, DQ11 =91
5672 09:59:44.348221 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5673 09:59:44.348392
5674 09:59:44.348497
5675 09:59:44.348587 ==
5676 09:59:44.351890 Dram Type= 6, Freq= 0, CH_1, rank 0
5677 09:59:44.354845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5678 09:59:44.354929 ==
5679 09:59:44.355011
5680 09:59:44.355087
5681 09:59:44.358223 TX Vref Scan disable
5682 09:59:44.358337 == TX Byte 0 ==
5683 09:59:44.364777 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5684 09:59:44.367987 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5685 09:59:44.368117 == TX Byte 1 ==
5686 09:59:44.374587 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5687 09:59:44.378325 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5688 09:59:44.378440 ==
5689 09:59:44.381211 Dram Type= 6, Freq= 0, CH_1, rank 0
5690 09:59:44.384730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5691 09:59:44.384841 ==
5692 09:59:44.384933
5693 09:59:44.387914
5694 09:59:44.388006 TX Vref Scan disable
5695 09:59:44.391164 == TX Byte 0 ==
5696 09:59:44.394758 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5697 09:59:44.398208 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5698 09:59:44.401005 == TX Byte 1 ==
5699 09:59:44.404749 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5700 09:59:44.408094 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5701 09:59:44.411062
5702 09:59:44.411161 [DATLAT]
5703 09:59:44.411250 Freq=933, CH1 RK0
5704 09:59:44.411333
5705 09:59:44.415139 DATLAT Default: 0xd
5706 09:59:44.415236 0, 0xFFFF, sum = 0
5707 09:59:44.418221 1, 0xFFFF, sum = 0
5708 09:59:44.418314 2, 0xFFFF, sum = 0
5709 09:59:44.421181 3, 0xFFFF, sum = 0
5710 09:59:44.421274 4, 0xFFFF, sum = 0
5711 09:59:44.424697 5, 0xFFFF, sum = 0
5712 09:59:44.424800 6, 0xFFFF, sum = 0
5713 09:59:44.427801 7, 0xFFFF, sum = 0
5714 09:59:44.431539 8, 0xFFFF, sum = 0
5715 09:59:44.431639 9, 0xFFFF, sum = 0
5716 09:59:44.434254 10, 0x0, sum = 1
5717 09:59:44.434346 11, 0x0, sum = 2
5718 09:59:44.434435 12, 0x0, sum = 3
5719 09:59:44.437731 13, 0x0, sum = 4
5720 09:59:44.437822 best_step = 11
5721 09:59:44.437910
5722 09:59:44.437992 ==
5723 09:59:44.441338 Dram Type= 6, Freq= 0, CH_1, rank 0
5724 09:59:44.447971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5725 09:59:44.448096 ==
5726 09:59:44.448166 RX Vref Scan: 1
5727 09:59:44.448228
5728 09:59:44.451433 RX Vref 0 -> 0, step: 1
5729 09:59:44.451516
5730 09:59:44.454235 RX Delay -45 -> 252, step: 4
5731 09:59:44.454344
5732 09:59:44.457905 Set Vref, RX VrefLevel [Byte0]: 56
5733 09:59:44.460972 [Byte1]: 49
5734 09:59:44.461070
5735 09:59:44.464444 Final RX Vref Byte 0 = 56 to rank0
5736 09:59:44.467877 Final RX Vref Byte 1 = 49 to rank0
5737 09:59:44.471321 Final RX Vref Byte 0 = 56 to rank1
5738 09:59:44.474506 Final RX Vref Byte 1 = 49 to rank1==
5739 09:59:44.477656 Dram Type= 6, Freq= 0, CH_1, rank 0
5740 09:59:44.481321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5741 09:59:44.481440 ==
5742 09:59:44.484802 DQS Delay:
5743 09:59:44.484920 DQS0 = 0, DQS1 = 0
5744 09:59:44.487549 DQM Delay:
5745 09:59:44.487641 DQM0 = 104, DQM1 = 100
5746 09:59:44.487706 DQ Delay:
5747 09:59:44.491532 DQ0 =106, DQ1 =98, DQ2 =94, DQ3 =102
5748 09:59:44.494669 DQ4 =104, DQ5 =114, DQ6 =114, DQ7 =106
5749 09:59:44.497616 DQ8 =88, DQ9 =90, DQ10 =100, DQ11 =96
5750 09:59:44.504417 DQ12 =106, DQ13 =104, DQ14 =108, DQ15 =108
5751 09:59:44.504522
5752 09:59:44.504597
5753 09:59:44.511250 [DQSOSCAuto] RK0, (LSB)MR18= 0x162d, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 414 ps
5754 09:59:44.514624 CH1 RK0: MR19=505, MR18=162D
5755 09:59:44.520962 CH1_RK0: MR19=0x505, MR18=0x162D, DQSOSC=407, MR23=63, INC=65, DEC=43
5756 09:59:44.521105
5757 09:59:44.524102 ----->DramcWriteLeveling(PI) begin...
5758 09:59:44.524205 ==
5759 09:59:44.527312 Dram Type= 6, Freq= 0, CH_1, rank 1
5760 09:59:44.530733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5761 09:59:44.530846 ==
5762 09:59:44.533934 Write leveling (Byte 0): 28 => 28
5763 09:59:44.537426 Write leveling (Byte 1): 28 => 28
5764 09:59:44.541116 DramcWriteLeveling(PI) end<-----
5765 09:59:44.541238
5766 09:59:44.541392 ==
5767 09:59:44.544140 Dram Type= 6, Freq= 0, CH_1, rank 1
5768 09:59:44.547556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5769 09:59:44.547690 ==
5770 09:59:44.550817 [Gating] SW mode calibration
5771 09:59:44.557326 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5772 09:59:44.564137 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5773 09:59:44.567505 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5774 09:59:44.574437 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5775 09:59:44.577319 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5776 09:59:44.580841 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5777 09:59:44.583848 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5778 09:59:44.590525 0 14 20 | B1->B0 | 3333 3434 | 1 1 | (1 0) (1 1)
5779 09:59:44.593845 0 14 24 | B1->B0 | 2c2c 2f2f | 0 1 | (0 0) (1 0)
5780 09:59:44.597228 0 14 28 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5781 09:59:44.603846 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5782 09:59:44.607431 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5783 09:59:44.610579 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5784 09:59:44.617061 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5785 09:59:44.620658 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5786 09:59:44.624537 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5787 09:59:44.630959 0 15 24 | B1->B0 | 3535 2929 | 1 0 | (0 0) (0 0)
5788 09:59:44.634264 0 15 28 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
5789 09:59:44.637229 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5790 09:59:44.644226 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5791 09:59:44.646998 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5792 09:59:44.650620 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5793 09:59:44.657345 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5794 09:59:44.660722 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5795 09:59:44.663650 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5796 09:59:44.670851 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5797 09:59:44.673912 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5798 09:59:44.677004 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5799 09:59:44.683926 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5800 09:59:44.687421 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5801 09:59:44.690645 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5802 09:59:44.697044 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5803 09:59:44.700575 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5804 09:59:44.703681 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5805 09:59:44.707495 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5806 09:59:44.714060 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5807 09:59:44.717194 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 09:59:44.720288 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5809 09:59:44.727285 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5810 09:59:44.730139 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5811 09:59:44.733856 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5812 09:59:44.740129 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5813 09:59:44.743372 Total UI for P1: 0, mck2ui 16
5814 09:59:44.747342 best dqsien dly found for B0: ( 1, 2, 26)
5815 09:59:44.750458 Total UI for P1: 0, mck2ui 16
5816 09:59:44.753376 best dqsien dly found for B1: ( 1, 2, 26)
5817 09:59:44.756899 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5818 09:59:44.760005 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5819 09:59:44.760088
5820 09:59:44.763796 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5821 09:59:44.766811 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5822 09:59:44.770046 [Gating] SW calibration Done
5823 09:59:44.770133 ==
5824 09:59:44.773765 Dram Type= 6, Freq= 0, CH_1, rank 1
5825 09:59:44.777237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5826 09:59:44.777322 ==
5827 09:59:44.780208 RX Vref Scan: 0
5828 09:59:44.780314
5829 09:59:44.780406 RX Vref 0 -> 0, step: 1
5830 09:59:44.783250
5831 09:59:44.783322 RX Delay -80 -> 252, step: 8
5832 09:59:44.790377 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5833 09:59:44.793238 iDelay=208, Bit 1, Center 103 (16 ~ 191) 176
5834 09:59:44.796989 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5835 09:59:44.799758 iDelay=208, Bit 3, Center 99 (16 ~ 183) 168
5836 09:59:44.803199 iDelay=208, Bit 4, Center 99 (16 ~ 183) 168
5837 09:59:44.806846 iDelay=208, Bit 5, Center 119 (32 ~ 207) 176
5838 09:59:44.813481 iDelay=208, Bit 6, Center 119 (32 ~ 207) 176
5839 09:59:44.816435 iDelay=208, Bit 7, Center 103 (16 ~ 191) 176
5840 09:59:44.819961 iDelay=208, Bit 8, Center 91 (0 ~ 183) 184
5841 09:59:44.823145 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5842 09:59:44.826837 iDelay=208, Bit 10, Center 103 (16 ~ 191) 176
5843 09:59:44.832913 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5844 09:59:44.836427 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5845 09:59:44.839606 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5846 09:59:44.843418 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5847 09:59:44.846463 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5848 09:59:44.846563 ==
5849 09:59:44.849783 Dram Type= 6, Freq= 0, CH_1, rank 1
5850 09:59:44.856584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5851 09:59:44.856681 ==
5852 09:59:44.856768 DQS Delay:
5853 09:59:44.860078 DQS0 = 0, DQS1 = 0
5854 09:59:44.860166 DQM Delay:
5855 09:59:44.863065 DQM0 = 105, DQM1 = 99
5856 09:59:44.863155 DQ Delay:
5857 09:59:44.866396 DQ0 =107, DQ1 =103, DQ2 =91, DQ3 =99
5858 09:59:44.869561 DQ4 =99, DQ5 =119, DQ6 =119, DQ7 =103
5859 09:59:44.873215 DQ8 =91, DQ9 =91, DQ10 =103, DQ11 =91
5860 09:59:44.876412 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5861 09:59:44.876516
5862 09:59:44.876607
5863 09:59:44.876704 ==
5864 09:59:44.879550 Dram Type= 6, Freq= 0, CH_1, rank 1
5865 09:59:44.883174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5866 09:59:44.883281 ==
5867 09:59:44.886500
5868 09:59:44.886599
5869 09:59:44.886688 TX Vref Scan disable
5870 09:59:44.889396 == TX Byte 0 ==
5871 09:59:44.892849 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5872 09:59:44.896300 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5873 09:59:44.900193 == TX Byte 1 ==
5874 09:59:44.903154 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5875 09:59:44.906350 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5876 09:59:44.906441 ==
5877 09:59:44.909669 Dram Type= 6, Freq= 0, CH_1, rank 1
5878 09:59:44.916702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5879 09:59:44.916831 ==
5880 09:59:44.916929
5881 09:59:44.917020
5882 09:59:44.917119 TX Vref Scan disable
5883 09:59:44.920336 == TX Byte 0 ==
5884 09:59:44.923818 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5885 09:59:44.930666 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5886 09:59:44.930781 == TX Byte 1 ==
5887 09:59:44.933670 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5888 09:59:44.940362 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5889 09:59:44.940466
5890 09:59:44.940536 [DATLAT]
5891 09:59:44.940597 Freq=933, CH1 RK1
5892 09:59:44.940656
5893 09:59:44.943669 DATLAT Default: 0xb
5894 09:59:44.943763 0, 0xFFFF, sum = 0
5895 09:59:44.947228 1, 0xFFFF, sum = 0
5896 09:59:44.947322 2, 0xFFFF, sum = 0
5897 09:59:44.950505 3, 0xFFFF, sum = 0
5898 09:59:44.953795 4, 0xFFFF, sum = 0
5899 09:59:44.953883 5, 0xFFFF, sum = 0
5900 09:59:44.956805 6, 0xFFFF, sum = 0
5901 09:59:44.956918 7, 0xFFFF, sum = 0
5902 09:59:44.960064 8, 0xFFFF, sum = 0
5903 09:59:44.960165 9, 0xFFFF, sum = 0
5904 09:59:44.963729 10, 0x0, sum = 1
5905 09:59:44.963846 11, 0x0, sum = 2
5906 09:59:44.966703 12, 0x0, sum = 3
5907 09:59:44.966797 13, 0x0, sum = 4
5908 09:59:44.966862 best_step = 11
5909 09:59:44.966923
5910 09:59:44.970178 ==
5911 09:59:44.974077 Dram Type= 6, Freq= 0, CH_1, rank 1
5912 09:59:44.976981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5913 09:59:44.977095 ==
5914 09:59:44.977188 RX Vref Scan: 0
5915 09:59:44.977278
5916 09:59:44.980289 RX Vref 0 -> 0, step: 1
5917 09:59:44.980391
5918 09:59:44.984212 RX Delay -45 -> 252, step: 4
5919 09:59:44.986805 iDelay=203, Bit 0, Center 110 (27 ~ 194) 168
5920 09:59:44.993903 iDelay=203, Bit 1, Center 100 (15 ~ 186) 172
5921 09:59:44.997115 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5922 09:59:45.000023 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5923 09:59:45.003450 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5924 09:59:45.007330 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5925 09:59:45.013535 iDelay=203, Bit 6, Center 112 (27 ~ 198) 172
5926 09:59:45.017068 iDelay=203, Bit 7, Center 104 (19 ~ 190) 172
5927 09:59:45.020073 iDelay=203, Bit 8, Center 88 (3 ~ 174) 172
5928 09:59:45.023534 iDelay=203, Bit 9, Center 90 (3 ~ 178) 176
5929 09:59:45.027238 iDelay=203, Bit 10, Center 100 (15 ~ 186) 172
5930 09:59:45.029841 iDelay=203, Bit 11, Center 92 (7 ~ 178) 172
5931 09:59:45.036707 iDelay=203, Bit 12, Center 110 (23 ~ 198) 176
5932 09:59:45.039797 iDelay=203, Bit 13, Center 106 (23 ~ 190) 168
5933 09:59:45.043212 iDelay=203, Bit 14, Center 104 (23 ~ 186) 164
5934 09:59:45.046827 iDelay=203, Bit 15, Center 108 (23 ~ 194) 172
5935 09:59:45.046924 ==
5936 09:59:45.049958 Dram Type= 6, Freq= 0, CH_1, rank 1
5937 09:59:45.056739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5938 09:59:45.056853 ==
5939 09:59:45.056948 DQS Delay:
5940 09:59:45.059905 DQS0 = 0, DQS1 = 0
5941 09:59:45.060012 DQM Delay:
5942 09:59:45.060106 DQM0 = 104, DQM1 = 99
5943 09:59:45.063371 DQ Delay:
5944 09:59:45.066781 DQ0 =110, DQ1 =100, DQ2 =94, DQ3 =100
5945 09:59:45.069598 DQ4 =100, DQ5 =118, DQ6 =112, DQ7 =104
5946 09:59:45.073083 DQ8 =88, DQ9 =90, DQ10 =100, DQ11 =92
5947 09:59:45.076416 DQ12 =110, DQ13 =106, DQ14 =104, DQ15 =108
5948 09:59:45.076510
5949 09:59:45.076596
5950 09:59:45.086286 [DQSOSCAuto] RK1, (LSB)MR18= 0x2bff, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 408 ps
5951 09:59:45.086406 CH1 RK1: MR19=504, MR18=2BFF
5952 09:59:45.093309 CH1_RK1: MR19=0x504, MR18=0x2BFF, DQSOSC=408, MR23=63, INC=65, DEC=43
5953 09:59:45.096263 [RxdqsGatingPostProcess] freq 933
5954 09:59:45.102885 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5955 09:59:45.106589 best DQS0 dly(2T, 0.5T) = (0, 10)
5956 09:59:45.109822 best DQS1 dly(2T, 0.5T) = (0, 10)
5957 09:59:45.112998 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5958 09:59:45.116183 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5959 09:59:45.116277 best DQS0 dly(2T, 0.5T) = (0, 10)
5960 09:59:45.120193 best DQS1 dly(2T, 0.5T) = (0, 10)
5961 09:59:45.122805 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5962 09:59:45.126298 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5963 09:59:45.129510 Pre-setting of DQS Precalculation
5964 09:59:45.136530 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5965 09:59:45.143075 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5966 09:59:45.149455 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5967 09:59:45.149559
5968 09:59:45.149644
5969 09:59:45.152959 [Calibration Summary] 1866 Mbps
5970 09:59:45.153046 CH 0, Rank 0
5971 09:59:45.156023 SW Impedance : PASS
5972 09:59:45.159614 DUTY Scan : NO K
5973 09:59:45.159716 ZQ Calibration : PASS
5974 09:59:45.162641 Jitter Meter : NO K
5975 09:59:45.166213 CBT Training : PASS
5976 09:59:45.166307 Write leveling : PASS
5977 09:59:45.169531 RX DQS gating : PASS
5978 09:59:45.173149 RX DQ/DQS(RDDQC) : PASS
5979 09:59:45.173243 TX DQ/DQS : PASS
5980 09:59:45.176153 RX DATLAT : PASS
5981 09:59:45.179942 RX DQ/DQS(Engine): PASS
5982 09:59:45.180031 TX OE : NO K
5983 09:59:45.180099 All Pass.
5984 09:59:45.180161
5985 09:59:45.182791 CH 0, Rank 1
5986 09:59:45.182876 SW Impedance : PASS
5987 09:59:45.186395 DUTY Scan : NO K
5988 09:59:45.189267 ZQ Calibration : PASS
5989 09:59:45.189392 Jitter Meter : NO K
5990 09:59:45.192621 CBT Training : PASS
5991 09:59:45.195982 Write leveling : PASS
5992 09:59:45.196102 RX DQS gating : PASS
5993 09:59:45.199141 RX DQ/DQS(RDDQC) : PASS
5994 09:59:45.202581 TX DQ/DQS : PASS
5995 09:59:45.202676 RX DATLAT : PASS
5996 09:59:45.205946 RX DQ/DQS(Engine): PASS
5997 09:59:45.209607 TX OE : NO K
5998 09:59:45.209698 All Pass.
5999 09:59:45.209764
6000 09:59:45.209846 CH 1, Rank 0
6001 09:59:45.212671 SW Impedance : PASS
6002 09:59:45.216201 DUTY Scan : NO K
6003 09:59:45.216298 ZQ Calibration : PASS
6004 09:59:45.219252 Jitter Meter : NO K
6005 09:59:45.222728 CBT Training : PASS
6006 09:59:45.222852 Write leveling : PASS
6007 09:59:45.226134 RX DQS gating : PASS
6008 09:59:45.229399 RX DQ/DQS(RDDQC) : PASS
6009 09:59:45.229530 TX DQ/DQS : PASS
6010 09:59:45.232616 RX DATLAT : PASS
6011 09:59:45.232717 RX DQ/DQS(Engine): PASS
6012 09:59:45.236025 TX OE : NO K
6013 09:59:45.236121 All Pass.
6014 09:59:45.236190
6015 09:59:45.239164 CH 1, Rank 1
6016 09:59:45.239239 SW Impedance : PASS
6017 09:59:45.242216 DUTY Scan : NO K
6018 09:59:45.246115 ZQ Calibration : PASS
6019 09:59:45.246204 Jitter Meter : NO K
6020 09:59:45.249122 CBT Training : PASS
6021 09:59:45.252615 Write leveling : PASS
6022 09:59:45.252698 RX DQS gating : PASS
6023 09:59:45.255673 RX DQ/DQS(RDDQC) : PASS
6024 09:59:45.259349 TX DQ/DQS : PASS
6025 09:59:45.259461 RX DATLAT : PASS
6026 09:59:45.262731 RX DQ/DQS(Engine): PASS
6027 09:59:45.265674 TX OE : NO K
6028 09:59:45.265771 All Pass.
6029 09:59:45.265837
6030 09:59:45.268929 DramC Write-DBI off
6031 09:59:45.269048 PER_BANK_REFRESH: Hybrid Mode
6032 09:59:45.272183 TX_TRACKING: ON
6033 09:59:45.279026 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6034 09:59:45.285309 [FAST_K] Save calibration result to emmc
6035 09:59:45.288868 dramc_set_vcore_voltage set vcore to 650000
6036 09:59:45.288989 Read voltage for 400, 6
6037 09:59:45.291995 Vio18 = 0
6038 09:59:45.292101 Vcore = 650000
6039 09:59:45.292197 Vdram = 0
6040 09:59:45.295239 Vddq = 0
6041 09:59:45.295351 Vmddr = 0
6042 09:59:45.298649 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6043 09:59:45.305267 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6044 09:59:45.308858 MEM_TYPE=3, freq_sel=20
6045 09:59:45.311970 sv_algorithm_assistance_LP4_800
6046 09:59:45.315774 ============ PULL DRAM RESETB DOWN ============
6047 09:59:45.318651 ========== PULL DRAM RESETB DOWN end =========
6048 09:59:45.322110 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6049 09:59:45.325383 ===================================
6050 09:59:45.329006 LPDDR4 DRAM CONFIGURATION
6051 09:59:45.331966 ===================================
6052 09:59:45.335594 EX_ROW_EN[0] = 0x0
6053 09:59:45.335711 EX_ROW_EN[1] = 0x0
6054 09:59:45.338669 LP4Y_EN = 0x0
6055 09:59:45.338779 WORK_FSP = 0x0
6056 09:59:45.341833 WL = 0x2
6057 09:59:45.341917 RL = 0x2
6058 09:59:45.345499 BL = 0x2
6059 09:59:45.345622 RPST = 0x0
6060 09:59:45.348672 RD_PRE = 0x0
6061 09:59:45.351592 WR_PRE = 0x1
6062 09:59:45.351678 WR_PST = 0x0
6063 09:59:45.355300 DBI_WR = 0x0
6064 09:59:45.355381 DBI_RD = 0x0
6065 09:59:45.358399 OTF = 0x1
6066 09:59:45.362244 ===================================
6067 09:59:45.365072 ===================================
6068 09:59:45.365178 ANA top config
6069 09:59:45.368624 ===================================
6070 09:59:45.371593 DLL_ASYNC_EN = 0
6071 09:59:45.375336 ALL_SLAVE_EN = 1
6072 09:59:45.375420 NEW_RANK_MODE = 1
6073 09:59:45.378490 DLL_IDLE_MODE = 1
6074 09:59:45.381697 LP45_APHY_COMB_EN = 1
6075 09:59:45.385052 TX_ODT_DIS = 1
6076 09:59:45.385133 NEW_8X_MODE = 1
6077 09:59:45.388495 ===================================
6078 09:59:45.392045 ===================================
6079 09:59:45.394939 data_rate = 800
6080 09:59:45.398568 CKR = 1
6081 09:59:45.401512 DQ_P2S_RATIO = 4
6082 09:59:45.405061 ===================================
6083 09:59:45.408073 CA_P2S_RATIO = 4
6084 09:59:45.411899 DQ_CA_OPEN = 0
6085 09:59:45.411998 DQ_SEMI_OPEN = 1
6086 09:59:45.414850 CA_SEMI_OPEN = 1
6087 09:59:45.418534 CA_FULL_RATE = 0
6088 09:59:45.421521 DQ_CKDIV4_EN = 0
6089 09:59:45.425146 CA_CKDIV4_EN = 1
6090 09:59:45.428480 CA_PREDIV_EN = 0
6091 09:59:45.428614 PH8_DLY = 0
6092 09:59:45.431785 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6093 09:59:45.435128 DQ_AAMCK_DIV = 0
6094 09:59:45.438067 CA_AAMCK_DIV = 0
6095 09:59:45.442090 CA_ADMCK_DIV = 4
6096 09:59:45.444953 DQ_TRACK_CA_EN = 0
6097 09:59:45.445049 CA_PICK = 800
6098 09:59:45.448052 CA_MCKIO = 400
6099 09:59:45.452069 MCKIO_SEMI = 400
6100 09:59:45.455282 PLL_FREQ = 3016
6101 09:59:45.458324 DQ_UI_PI_RATIO = 32
6102 09:59:45.461371 CA_UI_PI_RATIO = 32
6103 09:59:45.464658 ===================================
6104 09:59:45.468500 ===================================
6105 09:59:45.471749 memory_type:LPDDR4
6106 09:59:45.471836 GP_NUM : 10
6107 09:59:45.474626 SRAM_EN : 1
6108 09:59:45.474707 MD32_EN : 0
6109 09:59:45.478228 ===================================
6110 09:59:45.481384 [ANA_INIT] >>>>>>>>>>>>>>
6111 09:59:45.484624 <<<<<< [CONFIGURE PHASE]: ANA_TX
6112 09:59:45.488340 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6113 09:59:45.491457 ===================================
6114 09:59:45.494369 data_rate = 800,PCW = 0X7400
6115 09:59:45.497961 ===================================
6116 09:59:45.501164 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6117 09:59:45.504691 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6118 09:59:45.518108 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6119 09:59:45.521051 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6120 09:59:45.524876 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6121 09:59:45.528250 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6122 09:59:45.531468 [ANA_INIT] flow start
6123 09:59:45.534203 [ANA_INIT] PLL >>>>>>>>
6124 09:59:45.534296 [ANA_INIT] PLL <<<<<<<<
6125 09:59:45.537848 [ANA_INIT] MIDPI >>>>>>>>
6126 09:59:45.540976 [ANA_INIT] MIDPI <<<<<<<<
6127 09:59:45.541079 [ANA_INIT] DLL >>>>>>>>
6128 09:59:45.544554 [ANA_INIT] flow end
6129 09:59:45.547810 ============ LP4 DIFF to SE enter ============
6130 09:59:45.551188 ============ LP4 DIFF to SE exit ============
6131 09:59:45.554823 [ANA_INIT] <<<<<<<<<<<<<
6132 09:59:45.557736 [Flow] Enable top DCM control >>>>>
6133 09:59:45.561674 [Flow] Enable top DCM control <<<<<
6134 09:59:45.564820 Enable DLL master slave shuffle
6135 09:59:45.571346 ==============================================================
6136 09:59:45.571444 Gating Mode config
6137 09:59:45.577969 ==============================================================
6138 09:59:45.578071 Config description:
6139 09:59:45.587944 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6140 09:59:45.594313 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6141 09:59:45.601358 SELPH_MODE 0: By rank 1: By Phase
6142 09:59:45.604318 ==============================================================
6143 09:59:45.608082 GAT_TRACK_EN = 0
6144 09:59:45.611133 RX_GATING_MODE = 2
6145 09:59:45.614527 RX_GATING_TRACK_MODE = 2
6146 09:59:45.617615 SELPH_MODE = 1
6147 09:59:45.621067 PICG_EARLY_EN = 1
6148 09:59:45.624378 VALID_LAT_VALUE = 1
6149 09:59:45.631038 ==============================================================
6150 09:59:45.634759 Enter into Gating configuration >>>>
6151 09:59:45.637724 Exit from Gating configuration <<<<
6152 09:59:45.640823 Enter into DVFS_PRE_config >>>>>
6153 09:59:45.651241 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6154 09:59:45.654394 Exit from DVFS_PRE_config <<<<<
6155 09:59:45.657514 Enter into PICG configuration >>>>
6156 09:59:45.660712 Exit from PICG configuration <<<<
6157 09:59:45.660815 [RX_INPUT] configuration >>>>>
6158 09:59:45.664002 [RX_INPUT] configuration <<<<<
6159 09:59:45.671054 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6160 09:59:45.677549 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6161 09:59:45.681082 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6162 09:59:45.687356 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6163 09:59:45.693929 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6164 09:59:45.700911 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6165 09:59:45.703962 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6166 09:59:45.707720 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6167 09:59:45.714030 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6168 09:59:45.717293 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6169 09:59:45.720707 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6170 09:59:45.727419 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6171 09:59:45.730536 ===================================
6172 09:59:45.730666 LPDDR4 DRAM CONFIGURATION
6173 09:59:45.733817 ===================================
6174 09:59:45.737094 EX_ROW_EN[0] = 0x0
6175 09:59:45.737176 EX_ROW_EN[1] = 0x0
6176 09:59:45.740760 LP4Y_EN = 0x0
6177 09:59:45.740868 WORK_FSP = 0x0
6178 09:59:45.744406 WL = 0x2
6179 09:59:45.744519 RL = 0x2
6180 09:59:45.747048 BL = 0x2
6181 09:59:45.747126 RPST = 0x0
6182 09:59:45.750784 RD_PRE = 0x0
6183 09:59:45.753775 WR_PRE = 0x1
6184 09:59:45.753863 WR_PST = 0x0
6185 09:59:45.757408 DBI_WR = 0x0
6186 09:59:45.757491 DBI_RD = 0x0
6187 09:59:45.761090 OTF = 0x1
6188 09:59:45.764236 ===================================
6189 09:59:45.767114 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6190 09:59:45.770495 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6191 09:59:45.774048 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6192 09:59:45.777323 ===================================
6193 09:59:45.780452 LPDDR4 DRAM CONFIGURATION
6194 09:59:45.784120 ===================================
6195 09:59:45.787035 EX_ROW_EN[0] = 0x10
6196 09:59:45.787145 EX_ROW_EN[1] = 0x0
6197 09:59:45.790872 LP4Y_EN = 0x0
6198 09:59:45.790955 WORK_FSP = 0x0
6199 09:59:45.793680 WL = 0x2
6200 09:59:45.793785 RL = 0x2
6201 09:59:45.797276 BL = 0x2
6202 09:59:45.797360 RPST = 0x0
6203 09:59:45.800948 RD_PRE = 0x0
6204 09:59:45.801055 WR_PRE = 0x1
6205 09:59:45.803881 WR_PST = 0x0
6206 09:59:45.803958 DBI_WR = 0x0
6207 09:59:45.807557 DBI_RD = 0x0
6208 09:59:45.807632 OTF = 0x1
6209 09:59:45.810676 ===================================
6210 09:59:45.817769 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6211 09:59:45.822092 nWR fixed to 30
6212 09:59:45.825200 [ModeRegInit_LP4] CH0 RK0
6213 09:59:45.825296 [ModeRegInit_LP4] CH0 RK1
6214 09:59:45.828369 [ModeRegInit_LP4] CH1 RK0
6215 09:59:45.831833 [ModeRegInit_LP4] CH1 RK1
6216 09:59:45.831945 match AC timing 19
6217 09:59:45.838330 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6218 09:59:45.841827 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6219 09:59:45.845238 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6220 09:59:45.851476 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6221 09:59:45.855112 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6222 09:59:45.855235 ==
6223 09:59:45.858107 Dram Type= 6, Freq= 0, CH_0, rank 0
6224 09:59:45.861588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6225 09:59:45.861681 ==
6226 09:59:45.868253 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6227 09:59:45.875350 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6228 09:59:45.878835 [CA 0] Center 36 (8~64) winsize 57
6229 09:59:45.881964 [CA 1] Center 36 (8~64) winsize 57
6230 09:59:45.885245 [CA 2] Center 36 (8~64) winsize 57
6231 09:59:45.888427 [CA 3] Center 36 (8~64) winsize 57
6232 09:59:45.888537 [CA 4] Center 36 (8~64) winsize 57
6233 09:59:45.892007 [CA 5] Center 36 (8~64) winsize 57
6234 09:59:45.892122
6235 09:59:45.898561 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6236 09:59:45.898668
6237 09:59:45.901404 [CATrainingPosCal] consider 1 rank data
6238 09:59:45.905488 u2DelayCellTimex100 = 270/100 ps
6239 09:59:45.908544 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6240 09:59:45.911408 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6241 09:59:45.914765 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6242 09:59:45.918507 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6243 09:59:45.921746 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6244 09:59:45.925138 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6245 09:59:45.925230
6246 09:59:45.928227 CA PerBit enable=1, Macro0, CA PI delay=36
6247 09:59:45.928319
6248 09:59:45.931840 [CBTSetCACLKResult] CA Dly = 36
6249 09:59:45.934710 CS Dly: 1 (0~32)
6250 09:59:45.934800 ==
6251 09:59:45.937903 Dram Type= 6, Freq= 0, CH_0, rank 1
6252 09:59:45.941771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6253 09:59:45.941861 ==
6254 09:59:45.948404 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6255 09:59:45.951513 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6256 09:59:45.954813 [CA 0] Center 36 (8~64) winsize 57
6257 09:59:45.958019 [CA 1] Center 36 (8~64) winsize 57
6258 09:59:45.961534 [CA 2] Center 36 (8~64) winsize 57
6259 09:59:45.964948 [CA 3] Center 36 (8~64) winsize 57
6260 09:59:45.968151 [CA 4] Center 36 (8~64) winsize 57
6261 09:59:45.971312 [CA 5] Center 36 (8~64) winsize 57
6262 09:59:45.971427
6263 09:59:45.974641 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6264 09:59:45.974749
6265 09:59:45.977880 [CATrainingPosCal] consider 2 rank data
6266 09:59:45.981386 u2DelayCellTimex100 = 270/100 ps
6267 09:59:45.984367 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6268 09:59:45.987650 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6269 09:59:45.994619 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6270 09:59:45.997664 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6271 09:59:46.001235 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6272 09:59:46.004084 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6273 09:59:46.004202
6274 09:59:46.007460 CA PerBit enable=1, Macro0, CA PI delay=36
6275 09:59:46.007564
6276 09:59:46.011082 [CBTSetCACLKResult] CA Dly = 36
6277 09:59:46.011185 CS Dly: 1 (0~32)
6278 09:59:46.011265
6279 09:59:46.017856 ----->DramcWriteLeveling(PI) begin...
6280 09:59:46.017948 ==
6281 09:59:46.021033 Dram Type= 6, Freq= 0, CH_0, rank 0
6282 09:59:46.024335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6283 09:59:46.024445 ==
6284 09:59:46.027434 Write leveling (Byte 0): 40 => 8
6285 09:59:46.031125 Write leveling (Byte 1): 40 => 8
6286 09:59:46.034323 DramcWriteLeveling(PI) end<-----
6287 09:59:46.034431
6288 09:59:46.034524 ==
6289 09:59:46.037371 Dram Type= 6, Freq= 0, CH_0, rank 0
6290 09:59:46.041141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6291 09:59:46.041252 ==
6292 09:59:46.044429 [Gating] SW mode calibration
6293 09:59:46.050684 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6294 09:59:46.057756 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6295 09:59:46.060661 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6296 09:59:46.064489 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6297 09:59:46.067563 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6298 09:59:46.074291 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6299 09:59:46.077382 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6300 09:59:46.080694 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6301 09:59:46.087726 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6302 09:59:46.090671 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6303 09:59:46.093965 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6304 09:59:46.097795 Total UI for P1: 0, mck2ui 16
6305 09:59:46.100725 best dqsien dly found for B0: ( 0, 14, 24)
6306 09:59:46.104455 Total UI for P1: 0, mck2ui 16
6307 09:59:46.107382 best dqsien dly found for B1: ( 0, 14, 24)
6308 09:59:46.110893 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6309 09:59:46.114088 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6310 09:59:46.114182
6311 09:59:46.120783 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6312 09:59:46.124324 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6313 09:59:46.127401 [Gating] SW calibration Done
6314 09:59:46.127524 ==
6315 09:59:46.130590 Dram Type= 6, Freq= 0, CH_0, rank 0
6316 09:59:46.133972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6317 09:59:46.134082 ==
6318 09:59:46.134179 RX Vref Scan: 0
6319 09:59:46.134268
6320 09:59:46.137628 RX Vref 0 -> 0, step: 1
6321 09:59:46.137732
6322 09:59:46.140719 RX Delay -410 -> 252, step: 16
6323 09:59:46.144593 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6324 09:59:46.147700 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6325 09:59:46.153954 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6326 09:59:46.157691 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6327 09:59:46.160792 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6328 09:59:46.163881 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6329 09:59:46.170739 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6330 09:59:46.174230 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6331 09:59:46.177403 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6332 09:59:46.180395 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6333 09:59:46.187271 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6334 09:59:46.190787 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6335 09:59:46.193834 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6336 09:59:46.200822 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6337 09:59:46.203907 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6338 09:59:46.207755 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6339 09:59:46.207870 ==
6340 09:59:46.210830 Dram Type= 6, Freq= 0, CH_0, rank 0
6341 09:59:46.213656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6342 09:59:46.213763 ==
6343 09:59:46.217156 DQS Delay:
6344 09:59:46.217264 DQS0 = 27, DQS1 = 35
6345 09:59:46.220288 DQM Delay:
6346 09:59:46.220394 DQM0 = 8, DQM1 = 11
6347 09:59:46.224105 DQ Delay:
6348 09:59:46.224225 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =0
6349 09:59:46.226996 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6350 09:59:46.230583 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6351 09:59:46.234058 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6352 09:59:46.234178
6353 09:59:46.234279
6354 09:59:46.234374 ==
6355 09:59:46.236924 Dram Type= 6, Freq= 0, CH_0, rank 0
6356 09:59:46.243566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6357 09:59:46.243697 ==
6358 09:59:46.243795
6359 09:59:46.243894
6360 09:59:46.243963 TX Vref Scan disable
6361 09:59:46.247203 == TX Byte 0 ==
6362 09:59:46.250552 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6363 09:59:46.253827 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6364 09:59:46.256857 == TX Byte 1 ==
6365 09:59:46.260210 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6366 09:59:46.263969 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6367 09:59:46.266873 ==
6368 09:59:46.266959 Dram Type= 6, Freq= 0, CH_0, rank 0
6369 09:59:46.273537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6370 09:59:46.273662 ==
6371 09:59:46.273737
6372 09:59:46.273798
6373 09:59:46.277239 TX Vref Scan disable
6374 09:59:46.277357 == TX Byte 0 ==
6375 09:59:46.280215 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6376 09:59:46.286526 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6377 09:59:46.286630 == TX Byte 1 ==
6378 09:59:46.289970 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6379 09:59:46.296942 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6380 09:59:46.297083
6381 09:59:46.297191 [DATLAT]
6382 09:59:46.297285 Freq=400, CH0 RK0
6383 09:59:46.297375
6384 09:59:46.300079 DATLAT Default: 0xf
6385 09:59:46.300155 0, 0xFFFF, sum = 0
6386 09:59:46.303083 1, 0xFFFF, sum = 0
6387 09:59:46.303172 2, 0xFFFF, sum = 0
6388 09:59:46.306419 3, 0xFFFF, sum = 0
6389 09:59:46.310363 4, 0xFFFF, sum = 0
6390 09:59:46.310454 5, 0xFFFF, sum = 0
6391 09:59:46.313387 6, 0xFFFF, sum = 0
6392 09:59:46.313464 7, 0xFFFF, sum = 0
6393 09:59:46.316687 8, 0xFFFF, sum = 0
6394 09:59:46.316797 9, 0xFFFF, sum = 0
6395 09:59:46.319751 10, 0xFFFF, sum = 0
6396 09:59:46.319860 11, 0xFFFF, sum = 0
6397 09:59:46.323244 12, 0xFFFF, sum = 0
6398 09:59:46.323372 13, 0x0, sum = 1
6399 09:59:46.326349 14, 0x0, sum = 2
6400 09:59:46.326446 15, 0x0, sum = 3
6401 09:59:46.329946 16, 0x0, sum = 4
6402 09:59:46.330065 best_step = 14
6403 09:59:46.330172
6404 09:59:46.330264 ==
6405 09:59:46.333587 Dram Type= 6, Freq= 0, CH_0, rank 0
6406 09:59:46.336316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6407 09:59:46.339678 ==
6408 09:59:46.339771 RX Vref Scan: 1
6409 09:59:46.339838
6410 09:59:46.343064 RX Vref 0 -> 0, step: 1
6411 09:59:46.343177
6412 09:59:46.346656 RX Delay -311 -> 252, step: 8
6413 09:59:46.346741
6414 09:59:46.349317 Set Vref, RX VrefLevel [Byte0]: 53
6415 09:59:46.349442 [Byte1]: 46
6416 09:59:46.355169
6417 09:59:46.355289 Final RX Vref Byte 0 = 53 to rank0
6418 09:59:46.358400 Final RX Vref Byte 1 = 46 to rank0
6419 09:59:46.361598 Final RX Vref Byte 0 = 53 to rank1
6420 09:59:46.365168 Final RX Vref Byte 1 = 46 to rank1==
6421 09:59:46.368518 Dram Type= 6, Freq= 0, CH_0, rank 0
6422 09:59:46.375393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6423 09:59:46.375501 ==
6424 09:59:46.375573 DQS Delay:
6425 09:59:46.378532 DQS0 = 28, DQS1 = 36
6426 09:59:46.378617 DQM Delay:
6427 09:59:46.378687 DQM0 = 11, DQM1 = 12
6428 09:59:46.381870 DQ Delay:
6429 09:59:46.384825 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6430 09:59:46.384934 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6431 09:59:46.388437 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6432 09:59:46.391353 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6433 09:59:46.391481
6434 09:59:46.395088
6435 09:59:46.401454 [DQSOSCAuto] RK0, (LSB)MR18= 0xceba, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 384 ps
6436 09:59:46.404898 CH0 RK0: MR19=C0C, MR18=CEBA
6437 09:59:46.411398 CH0_RK0: MR19=0xC0C, MR18=0xCEBA, DQSOSC=384, MR23=63, INC=400, DEC=267
6438 09:59:46.411530 ==
6439 09:59:46.415159 Dram Type= 6, Freq= 0, CH_0, rank 1
6440 09:59:46.418527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6441 09:59:46.418646 ==
6442 09:59:46.421595 [Gating] SW mode calibration
6443 09:59:46.427979 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6444 09:59:46.434611 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6445 09:59:46.438219 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6446 09:59:46.441287 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6447 09:59:46.448186 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6448 09:59:46.451873 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6449 09:59:46.454901 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6450 09:59:46.458183 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6451 09:59:46.464507 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6452 09:59:46.468054 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6453 09:59:46.474492 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6454 09:59:46.474628 Total UI for P1: 0, mck2ui 16
6455 09:59:46.478127 best dqsien dly found for B0: ( 0, 14, 24)
6456 09:59:46.481569 Total UI for P1: 0, mck2ui 16
6457 09:59:46.484748 best dqsien dly found for B1: ( 0, 14, 24)
6458 09:59:46.487881 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6459 09:59:46.494351 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6460 09:59:46.494453
6461 09:59:46.498011 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6462 09:59:46.500952 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6463 09:59:46.504649 [Gating] SW calibration Done
6464 09:59:46.504764 ==
6465 09:59:46.507951 Dram Type= 6, Freq= 0, CH_0, rank 1
6466 09:59:46.511050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6467 09:59:46.511135 ==
6468 09:59:46.514630 RX Vref Scan: 0
6469 09:59:46.514727
6470 09:59:46.514794 RX Vref 0 -> 0, step: 1
6471 09:59:46.514854
6472 09:59:46.517529 RX Delay -410 -> 252, step: 16
6473 09:59:46.520950 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6474 09:59:46.528123 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6475 09:59:46.531090 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6476 09:59:46.534322 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6477 09:59:46.537599 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6478 09:59:46.544631 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6479 09:59:46.547786 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6480 09:59:46.550766 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6481 09:59:46.554419 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6482 09:59:46.561092 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6483 09:59:46.564155 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6484 09:59:46.567396 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6485 09:59:46.570746 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6486 09:59:46.577431 iDelay=230, Bit 13, Center -11 (-234 ~ 213) 448
6487 09:59:46.580646 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6488 09:59:46.584003 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6489 09:59:46.584109 ==
6490 09:59:46.587340 Dram Type= 6, Freq= 0, CH_0, rank 1
6491 09:59:46.594057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6492 09:59:46.594167 ==
6493 09:59:46.594260 DQS Delay:
6494 09:59:46.594341 DQS0 = 27, DQS1 = 35
6495 09:59:46.597674 DQM Delay:
6496 09:59:46.597801 DQM0 = 13, DQM1 = 12
6497 09:59:46.601276 DQ Delay:
6498 09:59:46.604440 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6499 09:59:46.604557 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6500 09:59:46.607619 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6501 09:59:46.610799 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =16
6502 09:59:46.610925
6503 09:59:46.611025
6504 09:59:46.614121 ==
6505 09:59:46.617709 Dram Type= 6, Freq= 0, CH_0, rank 1
6506 09:59:46.620649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6507 09:59:46.620738 ==
6508 09:59:46.620824
6509 09:59:46.620903
6510 09:59:46.624264 TX Vref Scan disable
6511 09:59:46.624364 == TX Byte 0 ==
6512 09:59:46.627572 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6513 09:59:46.634191 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6514 09:59:46.634301 == TX Byte 1 ==
6515 09:59:46.637336 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6516 09:59:46.641128 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6517 09:59:46.644000 ==
6518 09:59:46.647179 Dram Type= 6, Freq= 0, CH_0, rank 1
6519 09:59:46.650993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6520 09:59:46.651114 ==
6521 09:59:46.651226
6522 09:59:46.651316
6523 09:59:46.653973 TX Vref Scan disable
6524 09:59:46.654051 == TX Byte 0 ==
6525 09:59:46.657537 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6526 09:59:46.663995 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6527 09:59:46.664107 == TX Byte 1 ==
6528 09:59:46.667660 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6529 09:59:46.673885 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6530 09:59:46.673996
6531 09:59:46.674066 [DATLAT]
6532 09:59:46.674127 Freq=400, CH0 RK1
6533 09:59:46.674187
6534 09:59:46.677187 DATLAT Default: 0xe
6535 09:59:46.677272 0, 0xFFFF, sum = 0
6536 09:59:46.680942 1, 0xFFFF, sum = 0
6537 09:59:46.681029 2, 0xFFFF, sum = 0
6538 09:59:46.683849 3, 0xFFFF, sum = 0
6539 09:59:46.687125 4, 0xFFFF, sum = 0
6540 09:59:46.687214 5, 0xFFFF, sum = 0
6541 09:59:46.690682 6, 0xFFFF, sum = 0
6542 09:59:46.690772 7, 0xFFFF, sum = 0
6543 09:59:46.694087 8, 0xFFFF, sum = 0
6544 09:59:46.694173 9, 0xFFFF, sum = 0
6545 09:59:46.697063 10, 0xFFFF, sum = 0
6546 09:59:46.697138 11, 0xFFFF, sum = 0
6547 09:59:46.700781 12, 0xFFFF, sum = 0
6548 09:59:46.700869 13, 0x0, sum = 1
6549 09:59:46.704189 14, 0x0, sum = 2
6550 09:59:46.704279 15, 0x0, sum = 3
6551 09:59:46.707476 16, 0x0, sum = 4
6552 09:59:46.707557 best_step = 14
6553 09:59:46.707629
6554 09:59:46.707690 ==
6555 09:59:46.710556 Dram Type= 6, Freq= 0, CH_0, rank 1
6556 09:59:46.713850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6557 09:59:46.713942 ==
6558 09:59:46.717041 RX Vref Scan: 0
6559 09:59:46.717120
6560 09:59:46.720380 RX Vref 0 -> 0, step: 1
6561 09:59:46.720492
6562 09:59:46.720591 RX Delay -311 -> 252, step: 8
6563 09:59:46.729004 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6564 09:59:46.732738 iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440
6565 09:59:46.735732 iDelay=217, Bit 2, Center -16 (-239 ~ 208) 448
6566 09:59:46.739133 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6567 09:59:46.745895 iDelay=217, Bit 4, Center -12 (-239 ~ 216) 456
6568 09:59:46.749425 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6569 09:59:46.752451 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6570 09:59:46.756146 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6571 09:59:46.762751 iDelay=217, Bit 8, Center -28 (-247 ~ 192) 440
6572 09:59:46.765653 iDelay=217, Bit 9, Center -36 (-255 ~ 184) 440
6573 09:59:46.769170 iDelay=217, Bit 10, Center -24 (-239 ~ 192) 432
6574 09:59:46.772841 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6575 09:59:46.779449 iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440
6576 09:59:46.782585 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6577 09:59:46.785806 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6578 09:59:46.792540 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6579 09:59:46.792657 ==
6580 09:59:46.795589 Dram Type= 6, Freq= 0, CH_0, rank 1
6581 09:59:46.799313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6582 09:59:46.799431 ==
6583 09:59:46.799537 DQS Delay:
6584 09:59:46.801976 DQS0 = 24, DQS1 = 36
6585 09:59:46.802080 DQM Delay:
6586 09:59:46.805830 DQM0 = 9, DQM1 = 13
6587 09:59:46.805913 DQ Delay:
6588 09:59:46.808879 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6589 09:59:46.812227 DQ4 =12, DQ5 =0, DQ6 =12, DQ7 =16
6590 09:59:46.815554 DQ8 =8, DQ9 =0, DQ10 =12, DQ11 =8
6591 09:59:46.819098 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6592 09:59:46.819209
6593 09:59:46.819316
6594 09:59:46.825929 [DQSOSCAuto] RK1, (LSB)MR18= 0xb555, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 387 ps
6595 09:59:46.829074 CH0 RK1: MR19=C0C, MR18=B555
6596 09:59:46.835946 CH0_RK1: MR19=0xC0C, MR18=0xB555, DQSOSC=387, MR23=63, INC=394, DEC=262
6597 09:59:46.839061 [RxdqsGatingPostProcess] freq 400
6598 09:59:46.845267 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6599 09:59:46.845395 best DQS0 dly(2T, 0.5T) = (0, 10)
6600 09:59:46.849130 best DQS1 dly(2T, 0.5T) = (0, 10)
6601 09:59:46.852141 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6602 09:59:46.855805 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6603 09:59:46.858584 best DQS0 dly(2T, 0.5T) = (0, 10)
6604 09:59:46.862082 best DQS1 dly(2T, 0.5T) = (0, 10)
6605 09:59:46.866109 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6606 09:59:46.869315 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6607 09:59:46.872273 Pre-setting of DQS Precalculation
6608 09:59:46.875442 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6609 09:59:46.878776 ==
6610 09:59:46.882462 Dram Type= 6, Freq= 0, CH_1, rank 0
6611 09:59:46.885625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6612 09:59:46.885722 ==
6613 09:59:46.888589 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6614 09:59:46.895490 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6615 09:59:46.898738 [CA 0] Center 36 (8~64) winsize 57
6616 09:59:46.901920 [CA 1] Center 36 (8~64) winsize 57
6617 09:59:46.905497 [CA 2] Center 36 (8~64) winsize 57
6618 09:59:46.908624 [CA 3] Center 36 (8~64) winsize 57
6619 09:59:46.911930 [CA 4] Center 36 (8~64) winsize 57
6620 09:59:46.915855 [CA 5] Center 36 (8~64) winsize 57
6621 09:59:46.915942
6622 09:59:46.919095 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6623 09:59:46.919175
6624 09:59:46.922081 [CATrainingPosCal] consider 1 rank data
6625 09:59:46.925121 u2DelayCellTimex100 = 270/100 ps
6626 09:59:46.928879 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6627 09:59:46.932318 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6628 09:59:46.934979 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6629 09:59:46.938318 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6630 09:59:46.941876 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6631 09:59:46.948410 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6632 09:59:46.948510
6633 09:59:46.951829 CA PerBit enable=1, Macro0, CA PI delay=36
6634 09:59:46.951913
6635 09:59:46.955285 [CBTSetCACLKResult] CA Dly = 36
6636 09:59:46.955366 CS Dly: 1 (0~32)
6637 09:59:46.955434 ==
6638 09:59:46.958402 Dram Type= 6, Freq= 0, CH_1, rank 1
6639 09:59:46.961667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6640 09:59:46.965062 ==
6641 09:59:46.968743 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6642 09:59:46.975601 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6643 09:59:46.978746 [CA 0] Center 36 (8~64) winsize 57
6644 09:59:46.981814 [CA 1] Center 36 (8~64) winsize 57
6645 09:59:46.984980 [CA 2] Center 36 (8~64) winsize 57
6646 09:59:46.988507 [CA 3] Center 36 (8~64) winsize 57
6647 09:59:46.991958 [CA 4] Center 36 (8~64) winsize 57
6648 09:59:46.995026 [CA 5] Center 36 (8~64) winsize 57
6649 09:59:46.995115
6650 09:59:46.998272 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6651 09:59:46.998386
6652 09:59:47.002203 [CATrainingPosCal] consider 2 rank data
6653 09:59:47.005222 u2DelayCellTimex100 = 270/100 ps
6654 09:59:47.008432 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6655 09:59:47.011793 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6656 09:59:47.015258 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6657 09:59:47.018688 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6658 09:59:47.021656 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6659 09:59:47.024863 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6660 09:59:47.024944
6661 09:59:47.028515 CA PerBit enable=1, Macro0, CA PI delay=36
6662 09:59:47.028598
6663 09:59:47.032302 [CBTSetCACLKResult] CA Dly = 36
6664 09:59:47.034863 CS Dly: 1 (0~32)
6665 09:59:47.034938
6666 09:59:47.038552 ----->DramcWriteLeveling(PI) begin...
6667 09:59:47.038639 ==
6668 09:59:47.041594 Dram Type= 6, Freq= 0, CH_1, rank 0
6669 09:59:47.044943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6670 09:59:47.045056 ==
6671 09:59:47.048424 Write leveling (Byte 0): 40 => 8
6672 09:59:47.051480 Write leveling (Byte 1): 40 => 8
6673 09:59:47.055038 DramcWriteLeveling(PI) end<-----
6674 09:59:47.055145
6675 09:59:47.055225 ==
6676 09:59:47.058599 Dram Type= 6, Freq= 0, CH_1, rank 0
6677 09:59:47.061833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6678 09:59:47.061917 ==
6679 09:59:47.065454 [Gating] SW mode calibration
6680 09:59:47.071732 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6681 09:59:47.078691 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6682 09:59:47.081795 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6683 09:59:47.085245 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6684 09:59:47.091941 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6685 09:59:47.095218 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6686 09:59:47.098554 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6687 09:59:47.105223 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6688 09:59:47.108595 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6689 09:59:47.111646 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6690 09:59:47.118897 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6691 09:59:47.119038 Total UI for P1: 0, mck2ui 16
6692 09:59:47.125162 best dqsien dly found for B0: ( 0, 14, 24)
6693 09:59:47.125278 Total UI for P1: 0, mck2ui 16
6694 09:59:47.132182 best dqsien dly found for B1: ( 0, 14, 24)
6695 09:59:47.135122 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6696 09:59:47.138281 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6697 09:59:47.138399
6698 09:59:47.141732 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6699 09:59:47.145418 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6700 09:59:47.148361 [Gating] SW calibration Done
6701 09:59:47.148481 ==
6702 09:59:47.151504 Dram Type= 6, Freq= 0, CH_1, rank 0
6703 09:59:47.154901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6704 09:59:47.155018 ==
6705 09:59:47.158676 RX Vref Scan: 0
6706 09:59:47.158773
6707 09:59:47.158868 RX Vref 0 -> 0, step: 1
6708 09:59:47.158961
6709 09:59:47.161518 RX Delay -410 -> 252, step: 16
6710 09:59:47.168246 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6711 09:59:47.171388 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6712 09:59:47.174511 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6713 09:59:47.178216 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6714 09:59:47.184437 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6715 09:59:47.188302 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6716 09:59:47.191210 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6717 09:59:47.194506 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6718 09:59:47.201022 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6719 09:59:47.204327 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6720 09:59:47.207715 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6721 09:59:47.210994 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6722 09:59:47.217907 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6723 09:59:47.220887 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6724 09:59:47.224213 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6725 09:59:47.230694 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6726 09:59:47.230788 ==
6727 09:59:47.234489 Dram Type= 6, Freq= 0, CH_1, rank 0
6728 09:59:47.237769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6729 09:59:47.237874 ==
6730 09:59:47.237969 DQS Delay:
6731 09:59:47.240870 DQS0 = 35, DQS1 = 35
6732 09:59:47.240964 DQM Delay:
6733 09:59:47.244429 DQM0 = 18, DQM1 = 13
6734 09:59:47.244526 DQ Delay:
6735 09:59:47.247674 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =16
6736 09:59:47.250975 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6737 09:59:47.253718 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6738 09:59:47.257404 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6739 09:59:47.257518
6740 09:59:47.257622
6741 09:59:47.257686 ==
6742 09:59:47.260634 Dram Type= 6, Freq= 0, CH_1, rank 0
6743 09:59:47.263984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6744 09:59:47.264064 ==
6745 09:59:47.264129
6746 09:59:47.264188
6747 09:59:47.267068 TX Vref Scan disable
6748 09:59:47.270619 == TX Byte 0 ==
6749 09:59:47.273658 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6750 09:59:47.277396 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6751 09:59:47.280293 == TX Byte 1 ==
6752 09:59:47.283849 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6753 09:59:47.287029 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6754 09:59:47.287114 ==
6755 09:59:47.290066 Dram Type= 6, Freq= 0, CH_1, rank 0
6756 09:59:47.293365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6757 09:59:47.293472 ==
6758 09:59:47.296625
6759 09:59:47.296741
6760 09:59:47.296839 TX Vref Scan disable
6761 09:59:47.300323 == TX Byte 0 ==
6762 09:59:47.303408 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6763 09:59:47.307466 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6764 09:59:47.310155 == TX Byte 1 ==
6765 09:59:47.313189 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6766 09:59:47.316358 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6767 09:59:47.316449
6768 09:59:47.316524 [DATLAT]
6769 09:59:47.319654 Freq=400, CH1 RK0
6770 09:59:47.319736
6771 09:59:47.323174 DATLAT Default: 0xf
6772 09:59:47.323284 0, 0xFFFF, sum = 0
6773 09:59:47.326524 1, 0xFFFF, sum = 0
6774 09:59:47.326603 2, 0xFFFF, sum = 0
6775 09:59:47.330239 3, 0xFFFF, sum = 0
6776 09:59:47.330324 4, 0xFFFF, sum = 0
6777 09:59:47.332968 5, 0xFFFF, sum = 0
6778 09:59:47.333040 6, 0xFFFF, sum = 0
6779 09:59:47.336417 7, 0xFFFF, sum = 0
6780 09:59:47.336487 8, 0xFFFF, sum = 0
6781 09:59:47.339935 9, 0xFFFF, sum = 0
6782 09:59:47.340012 10, 0xFFFF, sum = 0
6783 09:59:47.343418 11, 0xFFFF, sum = 0
6784 09:59:47.343494 12, 0xFFFF, sum = 0
6785 09:59:47.346245 13, 0x0, sum = 1
6786 09:59:47.346323 14, 0x0, sum = 2
6787 09:59:47.350087 15, 0x0, sum = 3
6788 09:59:47.350199 16, 0x0, sum = 4
6789 09:59:47.353176 best_step = 14
6790 09:59:47.353285
6791 09:59:47.353379 ==
6792 09:59:47.356871 Dram Type= 6, Freq= 0, CH_1, rank 0
6793 09:59:47.360105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6794 09:59:47.360206 ==
6795 09:59:47.363573 RX Vref Scan: 1
6796 09:59:47.363672
6797 09:59:47.363767 RX Vref 0 -> 0, step: 1
6798 09:59:47.363854
6799 09:59:47.366661 RX Delay -311 -> 252, step: 8
6800 09:59:47.366769
6801 09:59:47.369567 Set Vref, RX VrefLevel [Byte0]: 56
6802 09:59:47.373317 [Byte1]: 49
6803 09:59:47.377429
6804 09:59:47.377539 Final RX Vref Byte 0 = 56 to rank0
6805 09:59:47.380791 Final RX Vref Byte 1 = 49 to rank0
6806 09:59:47.383915 Final RX Vref Byte 0 = 56 to rank1
6807 09:59:47.387435 Final RX Vref Byte 1 = 49 to rank1==
6808 09:59:47.391074 Dram Type= 6, Freq= 0, CH_1, rank 0
6809 09:59:47.397447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6810 09:59:47.397554 ==
6811 09:59:47.397660 DQS Delay:
6812 09:59:47.400764 DQS0 = 28, DQS1 = 32
6813 09:59:47.400844 DQM Delay:
6814 09:59:47.400907 DQM0 = 9, DQM1 = 11
6815 09:59:47.404150 DQ Delay:
6816 09:59:47.407086 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6817 09:59:47.407189 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6818 09:59:47.410955 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6819 09:59:47.413831 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =24
6820 09:59:47.413907
6821 09:59:47.413968
6822 09:59:47.423963 [DQSOSCAuto] RK0, (LSB)MR18= 0x90c8, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 391 ps
6823 09:59:47.427363 CH1 RK0: MR19=C0C, MR18=90C8
6824 09:59:47.434018 CH1_RK0: MR19=0xC0C, MR18=0x90C8, DQSOSC=385, MR23=63, INC=398, DEC=265
6825 09:59:47.434140 ==
6826 09:59:47.437013 Dram Type= 6, Freq= 0, CH_1, rank 1
6827 09:59:47.440230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6828 09:59:47.440337 ==
6829 09:59:47.443746 [Gating] SW mode calibration
6830 09:59:47.450587 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6831 09:59:47.453608 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6832 09:59:47.460749 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6833 09:59:47.463669 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6834 09:59:47.466932 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6835 09:59:47.473678 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6836 09:59:47.477135 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6837 09:59:47.480682 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6838 09:59:47.487357 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6839 09:59:47.490522 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6840 09:59:47.494254 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6841 09:59:47.497225 Total UI for P1: 0, mck2ui 16
6842 09:59:47.500268 best dqsien dly found for B0: ( 0, 14, 24)
6843 09:59:47.503450 Total UI for P1: 0, mck2ui 16
6844 09:59:47.507334 best dqsien dly found for B1: ( 0, 14, 24)
6845 09:59:47.510212 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6846 09:59:47.513754 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6847 09:59:47.513839
6848 09:59:47.520272 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6849 09:59:47.523967 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6850 09:59:47.526713 [Gating] SW calibration Done
6851 09:59:47.526798 ==
6852 09:59:47.530086 Dram Type= 6, Freq= 0, CH_1, rank 1
6853 09:59:47.533403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6854 09:59:47.533490 ==
6855 09:59:47.533557 RX Vref Scan: 0
6856 09:59:47.533632
6857 09:59:47.536918 RX Vref 0 -> 0, step: 1
6858 09:59:47.537039
6859 09:59:47.540039 RX Delay -410 -> 252, step: 16
6860 09:59:47.543325 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6861 09:59:47.550347 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6862 09:59:47.553727 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6863 09:59:47.557055 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6864 09:59:47.560038 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6865 09:59:47.563531 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6866 09:59:47.570063 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6867 09:59:47.573761 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6868 09:59:47.576771 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6869 09:59:47.580480 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6870 09:59:47.586736 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6871 09:59:47.590075 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6872 09:59:47.593229 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6873 09:59:47.599986 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6874 09:59:47.603271 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6875 09:59:47.606874 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6876 09:59:47.606960 ==
6877 09:59:47.610082 Dram Type= 6, Freq= 0, CH_1, rank 1
6878 09:59:47.613298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6879 09:59:47.617201 ==
6880 09:59:47.617289 DQS Delay:
6881 09:59:47.617355 DQS0 = 35, DQS1 = 35
6882 09:59:47.620169 DQM Delay:
6883 09:59:47.620254 DQM0 = 18, DQM1 = 13
6884 09:59:47.623348 DQ Delay:
6885 09:59:47.623433 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6886 09:59:47.626397 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6887 09:59:47.630177 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6888 09:59:47.633276 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6889 09:59:47.633365
6890 09:59:47.633451
6891 09:59:47.636259 ==
6892 09:59:47.636344 Dram Type= 6, Freq= 0, CH_1, rank 1
6893 09:59:47.643310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6894 09:59:47.643413 ==
6895 09:59:47.643482
6896 09:59:47.643543
6897 09:59:47.646259 TX Vref Scan disable
6898 09:59:47.646344 == TX Byte 0 ==
6899 09:59:47.649485 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6900 09:59:47.656378 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6901 09:59:47.656470 == TX Byte 1 ==
6902 09:59:47.659815 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6903 09:59:47.662982 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6904 09:59:47.666214 ==
6905 09:59:47.669495 Dram Type= 6, Freq= 0, CH_1, rank 1
6906 09:59:47.673151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6907 09:59:47.673240 ==
6908 09:59:47.673322
6909 09:59:47.673385
6910 09:59:47.676441 TX Vref Scan disable
6911 09:59:47.676525 == TX Byte 0 ==
6912 09:59:47.679826 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6913 09:59:47.686371 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6914 09:59:47.686474 == TX Byte 1 ==
6915 09:59:47.689199 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6916 09:59:47.696157 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6917 09:59:47.696246
6918 09:59:47.696312 [DATLAT]
6919 09:59:47.696373 Freq=400, CH1 RK1
6920 09:59:47.696433
6921 09:59:47.699464 DATLAT Default: 0xe
6922 09:59:47.699548 0, 0xFFFF, sum = 0
6923 09:59:47.702914 1, 0xFFFF, sum = 0
6924 09:59:47.703000 2, 0xFFFF, sum = 0
6925 09:59:47.706432 3, 0xFFFF, sum = 0
6926 09:59:47.709475 4, 0xFFFF, sum = 0
6927 09:59:47.709561 5, 0xFFFF, sum = 0
6928 09:59:47.712693 6, 0xFFFF, sum = 0
6929 09:59:47.712778 7, 0xFFFF, sum = 0
6930 09:59:47.715798 8, 0xFFFF, sum = 0
6931 09:59:47.715882 9, 0xFFFF, sum = 0
6932 09:59:47.719559 10, 0xFFFF, sum = 0
6933 09:59:47.719644 11, 0xFFFF, sum = 0
6934 09:59:47.722732 12, 0xFFFF, sum = 0
6935 09:59:47.722814 13, 0x0, sum = 1
6936 09:59:47.725787 14, 0x0, sum = 2
6937 09:59:47.725886 15, 0x0, sum = 3
6938 09:59:47.729479 16, 0x0, sum = 4
6939 09:59:47.729594 best_step = 14
6940 09:59:47.729662
6941 09:59:47.729722 ==
6942 09:59:47.732898 Dram Type= 6, Freq= 0, CH_1, rank 1
6943 09:59:47.736336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6944 09:59:47.736425 ==
6945 09:59:47.739584 RX Vref Scan: 0
6946 09:59:47.739657
6947 09:59:47.742491 RX Vref 0 -> 0, step: 1
6948 09:59:47.742567
6949 09:59:47.742642 RX Delay -311 -> 252, step: 8
6950 09:59:47.751902 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6951 09:59:47.754685 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6952 09:59:47.758174 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6953 09:59:47.761257 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6954 09:59:47.768350 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6955 09:59:47.771536 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6956 09:59:47.775089 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6957 09:59:47.778210 iDelay=217, Bit 7, Center -16 (-239 ~ 208) 448
6958 09:59:47.784822 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6959 09:59:47.788239 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6960 09:59:47.791232 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
6961 09:59:47.794584 iDelay=217, Bit 11, Center -24 (-247 ~ 200) 448
6962 09:59:47.801417 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6963 09:59:47.804468 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6964 09:59:47.808349 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6965 09:59:47.814959 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6966 09:59:47.815062 ==
6967 09:59:47.818009 Dram Type= 6, Freq= 0, CH_1, rank 1
6968 09:59:47.821123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6969 09:59:47.821246 ==
6970 09:59:47.821343 DQS Delay:
6971 09:59:47.824947 DQS0 = 28, DQS1 = 36
6972 09:59:47.825029 DQM Delay:
6973 09:59:47.828047 DQM0 = 10, DQM1 = 15
6974 09:59:47.828130 DQ Delay:
6975 09:59:47.831240 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
6976 09:59:47.834287 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =12
6977 09:59:47.837864 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =12
6978 09:59:47.841105 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
6979 09:59:47.841190
6980 09:59:47.841256
6981 09:59:47.847818 [DQSOSCAuto] RK1, (LSB)MR18= 0xc458, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 385 ps
6982 09:59:47.850759 CH1 RK1: MR19=C0C, MR18=C458
6983 09:59:47.857806 CH1_RK1: MR19=0xC0C, MR18=0xC458, DQSOSC=385, MR23=63, INC=398, DEC=265
6984 09:59:47.860837 [RxdqsGatingPostProcess] freq 400
6985 09:59:47.867455 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6986 09:59:47.867560 best DQS0 dly(2T, 0.5T) = (0, 10)
6987 09:59:47.871074 best DQS1 dly(2T, 0.5T) = (0, 10)
6988 09:59:47.874456 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6989 09:59:47.877964 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6990 09:59:47.880994 best DQS0 dly(2T, 0.5T) = (0, 10)
6991 09:59:47.884617 best DQS1 dly(2T, 0.5T) = (0, 10)
6992 09:59:47.887504 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6993 09:59:47.891167 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6994 09:59:47.894548 Pre-setting of DQS Precalculation
6995 09:59:47.897848 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6996 09:59:47.907746 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6997 09:59:47.914084 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6998 09:59:47.914204
6999 09:59:47.914276
7000 09:59:47.917451 [Calibration Summary] 800 Mbps
7001 09:59:47.917555 CH 0, Rank 0
7002 09:59:47.920817 SW Impedance : PASS
7003 09:59:47.920927 DUTY Scan : NO K
7004 09:59:47.923964 ZQ Calibration : PASS
7005 09:59:47.927809 Jitter Meter : NO K
7006 09:59:47.927919 CBT Training : PASS
7007 09:59:47.930731 Write leveling : PASS
7008 09:59:47.934290 RX DQS gating : PASS
7009 09:59:47.934407 RX DQ/DQS(RDDQC) : PASS
7010 09:59:47.937522 TX DQ/DQS : PASS
7011 09:59:47.940601 RX DATLAT : PASS
7012 09:59:47.940714 RX DQ/DQS(Engine): PASS
7013 09:59:47.944218 TX OE : NO K
7014 09:59:47.944300 All Pass.
7015 09:59:47.944366
7016 09:59:47.947196 CH 0, Rank 1
7017 09:59:47.947273 SW Impedance : PASS
7018 09:59:47.951024 DUTY Scan : NO K
7019 09:59:47.954014 ZQ Calibration : PASS
7020 09:59:47.954093 Jitter Meter : NO K
7021 09:59:47.957313 CBT Training : PASS
7022 09:59:47.960864 Write leveling : NO K
7023 09:59:47.960943 RX DQS gating : PASS
7024 09:59:47.963909 RX DQ/DQS(RDDQC) : PASS
7025 09:59:47.967072 TX DQ/DQS : PASS
7026 09:59:47.967181 RX DATLAT : PASS
7027 09:59:47.970649 RX DQ/DQS(Engine): PASS
7028 09:59:47.970754 TX OE : NO K
7029 09:59:47.973742 All Pass.
7030 09:59:47.973833
7031 09:59:47.973900 CH 1, Rank 0
7032 09:59:47.977306 SW Impedance : PASS
7033 09:59:47.977391 DUTY Scan : NO K
7034 09:59:47.980313 ZQ Calibration : PASS
7035 09:59:47.984089 Jitter Meter : NO K
7036 09:59:47.984167 CBT Training : PASS
7037 09:59:47.987298 Write leveling : PASS
7038 09:59:47.990922 RX DQS gating : PASS
7039 09:59:47.991000 RX DQ/DQS(RDDQC) : PASS
7040 09:59:47.994129 TX DQ/DQS : PASS
7041 09:59:47.997484 RX DATLAT : PASS
7042 09:59:47.997568 RX DQ/DQS(Engine): PASS
7043 09:59:48.000975 TX OE : NO K
7044 09:59:48.001059 All Pass.
7045 09:59:48.001127
7046 09:59:48.004420 CH 1, Rank 1
7047 09:59:48.004499 SW Impedance : PASS
7048 09:59:48.007339 DUTY Scan : NO K
7049 09:59:48.010302 ZQ Calibration : PASS
7050 09:59:48.010386 Jitter Meter : NO K
7051 09:59:48.013876 CBT Training : PASS
7052 09:59:48.013955 Write leveling : NO K
7053 09:59:48.017325 RX DQS gating : PASS
7054 09:59:48.020767 RX DQ/DQS(RDDQC) : PASS
7055 09:59:48.020864 TX DQ/DQS : PASS
7056 09:59:48.024050 RX DATLAT : PASS
7057 09:59:48.026949 RX DQ/DQS(Engine): PASS
7058 09:59:48.027036 TX OE : NO K
7059 09:59:48.030420 All Pass.
7060 09:59:48.030499
7061 09:59:48.030565 DramC Write-DBI off
7062 09:59:48.033430 PER_BANK_REFRESH: Hybrid Mode
7063 09:59:48.036759 TX_TRACKING: ON
7064 09:59:48.043610 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7065 09:59:48.047153 [FAST_K] Save calibration result to emmc
7066 09:59:48.050435 dramc_set_vcore_voltage set vcore to 725000
7067 09:59:48.053433 Read voltage for 1600, 0
7068 09:59:48.053549 Vio18 = 0
7069 09:59:48.056766 Vcore = 725000
7070 09:59:48.056898 Vdram = 0
7071 09:59:48.056993 Vddq = 0
7072 09:59:48.060446 Vmddr = 0
7073 09:59:48.063711 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7074 09:59:48.070240 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7075 09:59:48.070361 MEM_TYPE=3, freq_sel=13
7076 09:59:48.073534 sv_algorithm_assistance_LP4_3733
7077 09:59:48.079995 ============ PULL DRAM RESETB DOWN ============
7078 09:59:48.083590 ========== PULL DRAM RESETB DOWN end =========
7079 09:59:48.087061 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7080 09:59:48.090281 ===================================
7081 09:59:48.093368 LPDDR4 DRAM CONFIGURATION
7082 09:59:48.096976 ===================================
7083 09:59:48.100066 EX_ROW_EN[0] = 0x0
7084 09:59:48.100156 EX_ROW_EN[1] = 0x0
7085 09:59:48.103219 LP4Y_EN = 0x0
7086 09:59:48.103313 WORK_FSP = 0x1
7087 09:59:48.107002 WL = 0x5
7088 09:59:48.107116 RL = 0x5
7089 09:59:48.109989 BL = 0x2
7090 09:59:48.110096 RPST = 0x0
7091 09:59:48.113366 RD_PRE = 0x0
7092 09:59:48.113467 WR_PRE = 0x1
7093 09:59:48.116371 WR_PST = 0x1
7094 09:59:48.116461 DBI_WR = 0x0
7095 09:59:48.120251 DBI_RD = 0x0
7096 09:59:48.120340 OTF = 0x1
7097 09:59:48.123275 ===================================
7098 09:59:48.126527 ===================================
7099 09:59:48.130135 ANA top config
7100 09:59:48.133092 ===================================
7101 09:59:48.136704 DLL_ASYNC_EN = 0
7102 09:59:48.136799 ALL_SLAVE_EN = 0
7103 09:59:48.139926 NEW_RANK_MODE = 1
7104 09:59:48.143231 DLL_IDLE_MODE = 1
7105 09:59:48.146572 LP45_APHY_COMB_EN = 1
7106 09:59:48.146656 TX_ODT_DIS = 0
7107 09:59:48.150071 NEW_8X_MODE = 1
7108 09:59:48.153095 ===================================
7109 09:59:48.156280 ===================================
7110 09:59:48.159761 data_rate = 3200
7111 09:59:48.162989 CKR = 1
7112 09:59:48.166471 DQ_P2S_RATIO = 8
7113 09:59:48.170524 ===================================
7114 09:59:48.170609 CA_P2S_RATIO = 8
7115 09:59:48.173758 DQ_CA_OPEN = 0
7116 09:59:48.176888 DQ_SEMI_OPEN = 0
7117 09:59:48.180061 CA_SEMI_OPEN = 0
7118 09:59:48.182971 CA_FULL_RATE = 0
7119 09:59:48.186632 DQ_CKDIV4_EN = 0
7120 09:59:48.186710 CA_CKDIV4_EN = 0
7121 09:59:48.190027 CA_PREDIV_EN = 0
7122 09:59:48.193589 PH8_DLY = 12
7123 09:59:48.196587 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7124 09:59:48.199789 DQ_AAMCK_DIV = 4
7125 09:59:48.203071 CA_AAMCK_DIV = 4
7126 09:59:48.206171 CA_ADMCK_DIV = 4
7127 09:59:48.206250 DQ_TRACK_CA_EN = 0
7128 09:59:48.209971 CA_PICK = 1600
7129 09:59:48.213023 CA_MCKIO = 1600
7130 09:59:48.216260 MCKIO_SEMI = 0
7131 09:59:48.219588 PLL_FREQ = 3068
7132 09:59:48.223022 DQ_UI_PI_RATIO = 32
7133 09:59:48.226409 CA_UI_PI_RATIO = 0
7134 09:59:48.229302 ===================================
7135 09:59:48.232634 ===================================
7136 09:59:48.232714 memory_type:LPDDR4
7137 09:59:48.235752 GP_NUM : 10
7138 09:59:48.239355 SRAM_EN : 1
7139 09:59:48.239440 MD32_EN : 0
7140 09:59:48.242675 ===================================
7141 09:59:48.245779 [ANA_INIT] >>>>>>>>>>>>>>
7142 09:59:48.249102 <<<<<< [CONFIGURE PHASE]: ANA_TX
7143 09:59:48.252840 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7144 09:59:48.255882 ===================================
7145 09:59:48.259820 data_rate = 3200,PCW = 0X7600
7146 09:59:48.262573 ===================================
7147 09:59:48.265760 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7148 09:59:48.268883 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7149 09:59:48.275680 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7150 09:59:48.278927 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7151 09:59:48.282062 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7152 09:59:48.289177 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7153 09:59:48.289294 [ANA_INIT] flow start
7154 09:59:48.292085 [ANA_INIT] PLL >>>>>>>>
7155 09:59:48.295578 [ANA_INIT] PLL <<<<<<<<
7156 09:59:48.295661 [ANA_INIT] MIDPI >>>>>>>>
7157 09:59:48.299316 [ANA_INIT] MIDPI <<<<<<<<
7158 09:59:48.301937 [ANA_INIT] DLL >>>>>>>>
7159 09:59:48.302019 [ANA_INIT] DLL <<<<<<<<
7160 09:59:48.305338 [ANA_INIT] flow end
7161 09:59:48.308843 ============ LP4 DIFF to SE enter ============
7162 09:59:48.312328 ============ LP4 DIFF to SE exit ============
7163 09:59:48.315367 [ANA_INIT] <<<<<<<<<<<<<
7164 09:59:48.318347 [Flow] Enable top DCM control >>>>>
7165 09:59:48.321618 [Flow] Enable top DCM control <<<<<
7166 09:59:48.325243 Enable DLL master slave shuffle
7167 09:59:48.331942 ==============================================================
7168 09:59:48.332056 Gating Mode config
7169 09:59:48.338096 ==============================================================
7170 09:59:48.341823 Config description:
7171 09:59:48.348101 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7172 09:59:48.354587 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7173 09:59:48.361307 SELPH_MODE 0: By rank 1: By Phase
7174 09:59:48.367954 ==============================================================
7175 09:59:48.368052 GAT_TRACK_EN = 1
7176 09:59:48.371436 RX_GATING_MODE = 2
7177 09:59:48.374714 RX_GATING_TRACK_MODE = 2
7178 09:59:48.377951 SELPH_MODE = 1
7179 09:59:48.381566 PICG_EARLY_EN = 1
7180 09:59:48.384880 VALID_LAT_VALUE = 1
7181 09:59:48.391320 ==============================================================
7182 09:59:48.394869 Enter into Gating configuration >>>>
7183 09:59:48.397946 Exit from Gating configuration <<<<
7184 09:59:48.401271 Enter into DVFS_PRE_config >>>>>
7185 09:59:48.411452 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7186 09:59:48.414403 Exit from DVFS_PRE_config <<<<<
7187 09:59:48.417836 Enter into PICG configuration >>>>
7188 09:59:48.420921 Exit from PICG configuration <<<<
7189 09:59:48.424565 [RX_INPUT] configuration >>>>>
7190 09:59:48.424672 [RX_INPUT] configuration <<<<<
7191 09:59:48.431388 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7192 09:59:48.437959 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7193 09:59:48.441134 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7194 09:59:48.447680 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7195 09:59:48.454141 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7196 09:59:48.461072 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7197 09:59:48.464225 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7198 09:59:48.467656 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7199 09:59:48.474419 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7200 09:59:48.477760 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7201 09:59:48.481456 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7202 09:59:48.487737 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7203 09:59:48.490773 ===================================
7204 09:59:48.490909 LPDDR4 DRAM CONFIGURATION
7205 09:59:48.494039 ===================================
7206 09:59:48.497921 EX_ROW_EN[0] = 0x0
7207 09:59:48.498019 EX_ROW_EN[1] = 0x0
7208 09:59:48.500989 LP4Y_EN = 0x0
7209 09:59:48.501085 WORK_FSP = 0x1
7210 09:59:48.504466 WL = 0x5
7211 09:59:48.504567 RL = 0x5
7212 09:59:48.507378 BL = 0x2
7213 09:59:48.511024 RPST = 0x0
7214 09:59:48.511104 RD_PRE = 0x0
7215 09:59:48.514095 WR_PRE = 0x1
7216 09:59:48.514172 WR_PST = 0x1
7217 09:59:48.517691 DBI_WR = 0x0
7218 09:59:48.517803 DBI_RD = 0x0
7219 09:59:48.520953 OTF = 0x1
7220 09:59:48.524245 ===================================
7221 09:59:48.527136 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7222 09:59:48.530862 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7223 09:59:48.534398 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7224 09:59:48.537458 ===================================
7225 09:59:48.540779 LPDDR4 DRAM CONFIGURATION
7226 09:59:48.544471 ===================================
7227 09:59:48.547761 EX_ROW_EN[0] = 0x10
7228 09:59:48.547841 EX_ROW_EN[1] = 0x0
7229 09:59:48.550817 LP4Y_EN = 0x0
7230 09:59:48.550901 WORK_FSP = 0x1
7231 09:59:48.554076 WL = 0x5
7232 09:59:48.554156 RL = 0x5
7233 09:59:48.557873 BL = 0x2
7234 09:59:48.557950 RPST = 0x0
7235 09:59:48.561004 RD_PRE = 0x0
7236 09:59:48.561083 WR_PRE = 0x1
7237 09:59:48.564013 WR_PST = 0x1
7238 09:59:48.567819 DBI_WR = 0x0
7239 09:59:48.567897 DBI_RD = 0x0
7240 09:59:48.570735 OTF = 0x1
7241 09:59:48.573682 ===================================
7242 09:59:48.576982 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7243 09:59:48.580364 ==
7244 09:59:48.580441 Dram Type= 6, Freq= 0, CH_0, rank 0
7245 09:59:48.586835 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7246 09:59:48.586920 ==
7247 09:59:48.590775 [Duty_Offset_Calibration]
7248 09:59:48.590851 B0:2 B1:1 CA:1
7249 09:59:48.590921
7250 09:59:48.593787 [DutyScan_Calibration_Flow] k_type=0
7251 09:59:48.603485
7252 09:59:48.603568 ==CLK 0==
7253 09:59:48.607213 Final CLK duty delay cell = 0
7254 09:59:48.610616 [0] MAX Duty = 5187%(X100), DQS PI = 22
7255 09:59:48.613462 [0] MIN Duty = 4907%(X100), DQS PI = 0
7256 09:59:48.613585 [0] AVG Duty = 5047%(X100)
7257 09:59:48.617005
7258 09:59:48.617081 CH0 CLK Duty spec in!! Max-Min= 280%
7259 09:59:48.623697 [DutyScan_Calibration_Flow] ====Done====
7260 09:59:48.623779
7261 09:59:48.626721 [DutyScan_Calibration_Flow] k_type=1
7262 09:59:48.642938
7263 09:59:48.643059 ==DQS 0 ==
7264 09:59:48.645936 Final DQS duty delay cell = -4
7265 09:59:48.649175 [-4] MAX Duty = 5156%(X100), DQS PI = 26
7266 09:59:48.652471 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7267 09:59:48.656201 [-4] AVG Duty = 4906%(X100)
7268 09:59:48.656279
7269 09:59:48.656351 ==DQS 1 ==
7270 09:59:48.659587 Final DQS duty delay cell = 0
7271 09:59:48.662591 [0] MAX Duty = 5187%(X100), DQS PI = 2
7272 09:59:48.665785 [0] MIN Duty = 5031%(X100), DQS PI = 52
7273 09:59:48.669200 [0] AVG Duty = 5109%(X100)
7274 09:59:48.669281
7275 09:59:48.672769 CH0 DQS 0 Duty spec in!! Max-Min= 499%
7276 09:59:48.672855
7277 09:59:48.675836 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7278 09:59:48.679352 [DutyScan_Calibration_Flow] ====Done====
7279 09:59:48.679457
7280 09:59:48.682527 [DutyScan_Calibration_Flow] k_type=3
7281 09:59:48.699299
7282 09:59:48.699386 ==DQM 0 ==
7283 09:59:48.702376 Final DQM duty delay cell = 0
7284 09:59:48.705869 [0] MAX Duty = 5187%(X100), DQS PI = 26
7285 09:59:48.709472 [0] MIN Duty = 4907%(X100), DQS PI = 54
7286 09:59:48.712877 [0] AVG Duty = 5047%(X100)
7287 09:59:48.712957
7288 09:59:48.713027 ==DQM 1 ==
7289 09:59:48.715478 Final DQM duty delay cell = -4
7290 09:59:48.718911 [-4] MAX Duty = 4969%(X100), DQS PI = 20
7291 09:59:48.722247 [-4] MIN Duty = 4813%(X100), DQS PI = 50
7292 09:59:48.725478 [-4] AVG Duty = 4891%(X100)
7293 09:59:48.725564
7294 09:59:48.729198 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7295 09:59:48.729277
7296 09:59:48.732467 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7297 09:59:48.735942 [DutyScan_Calibration_Flow] ====Done====
7298 09:59:48.736017
7299 09:59:48.738902 [DutyScan_Calibration_Flow] k_type=2
7300 09:59:48.757166
7301 09:59:48.757263 ==DQ 0 ==
7302 09:59:48.759895 Final DQ duty delay cell = 0
7303 09:59:48.763524 [0] MAX Duty = 5062%(X100), DQS PI = 26
7304 09:59:48.766898 [0] MIN Duty = 4907%(X100), DQS PI = 0
7305 09:59:48.766986 [0] AVG Duty = 4984%(X100)
7306 09:59:48.770092
7307 09:59:48.770165 ==DQ 1 ==
7308 09:59:48.772979 Final DQ duty delay cell = 0
7309 09:59:48.776767 [0] MAX Duty = 5125%(X100), DQS PI = 6
7310 09:59:48.780278 [0] MIN Duty = 4938%(X100), DQS PI = 34
7311 09:59:48.780358 [0] AVG Duty = 5031%(X100)
7312 09:59:48.780420
7313 09:59:48.783233 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7314 09:59:48.786414
7315 09:59:48.789673 CH0 DQ 1 Duty spec in!! Max-Min= 187%
7316 09:59:48.792938 [DutyScan_Calibration_Flow] ====Done====
7317 09:59:48.793020 ==
7318 09:59:48.796239 Dram Type= 6, Freq= 0, CH_1, rank 0
7319 09:59:48.799959 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7320 09:59:48.800067 ==
7321 09:59:48.802952 [Duty_Offset_Calibration]
7322 09:59:48.803033 B0:1 B1:0 CA:0
7323 09:59:48.803097
7324 09:59:48.806455 [DutyScan_Calibration_Flow] k_type=0
7325 09:59:48.816122
7326 09:59:48.816203 ==CLK 0==
7327 09:59:48.819202 Final CLK duty delay cell = -4
7328 09:59:48.823022 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7329 09:59:48.826534 [-4] MIN Duty = 4844%(X100), DQS PI = 2
7330 09:59:48.828965 [-4] AVG Duty = 4922%(X100)
7331 09:59:48.829046
7332 09:59:48.832918 CH1 CLK Duty spec in!! Max-Min= 156%
7333 09:59:48.836014 [DutyScan_Calibration_Flow] ====Done====
7334 09:59:48.836095
7335 09:59:48.839288 [DutyScan_Calibration_Flow] k_type=1
7336 09:59:48.856354
7337 09:59:48.856455 ==DQS 0 ==
7338 09:59:48.859284 Final DQS duty delay cell = 0
7339 09:59:48.862940 [0] MAX Duty = 5094%(X100), DQS PI = 16
7340 09:59:48.865962 [0] MIN Duty = 4844%(X100), DQS PI = 48
7341 09:59:48.866069 [0] AVG Duty = 4969%(X100)
7342 09:59:48.869775
7343 09:59:48.869857 ==DQS 1 ==
7344 09:59:48.872729 Final DQS duty delay cell = 0
7345 09:59:48.875973 [0] MAX Duty = 5249%(X100), DQS PI = 18
7346 09:59:48.879736 [0] MIN Duty = 4969%(X100), DQS PI = 6
7347 09:59:48.879819 [0] AVG Duty = 5109%(X100)
7348 09:59:48.882645
7349 09:59:48.885846 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7350 09:59:48.885927
7351 09:59:48.889511 CH1 DQS 1 Duty spec in!! Max-Min= 280%
7352 09:59:48.892968 [DutyScan_Calibration_Flow] ====Done====
7353 09:59:48.893095
7354 09:59:48.895791 [DutyScan_Calibration_Flow] k_type=3
7355 09:59:48.912841
7356 09:59:48.912934 ==DQM 0 ==
7357 09:59:48.916093 Final DQM duty delay cell = 0
7358 09:59:48.919790 [0] MAX Duty = 5187%(X100), DQS PI = 8
7359 09:59:48.922635 [0] MIN Duty = 4969%(X100), DQS PI = 48
7360 09:59:48.922716 [0] AVG Duty = 5078%(X100)
7361 09:59:48.925863
7362 09:59:48.925943 ==DQM 1 ==
7363 09:59:48.929255 Final DQM duty delay cell = 0
7364 09:59:48.932878 [0] MAX Duty = 5093%(X100), DQS PI = 16
7365 09:59:48.935961 [0] MIN Duty = 4907%(X100), DQS PI = 34
7366 09:59:48.939421 [0] AVG Duty = 5000%(X100)
7367 09:59:48.939502
7368 09:59:48.942615 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7369 09:59:48.942697
7370 09:59:48.946043 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7371 09:59:48.949471 [DutyScan_Calibration_Flow] ====Done====
7372 09:59:48.949556
7373 09:59:48.952499 [DutyScan_Calibration_Flow] k_type=2
7374 09:59:48.969116
7375 09:59:48.969245 ==DQ 0 ==
7376 09:59:48.971933 Final DQ duty delay cell = -4
7377 09:59:48.975744 [-4] MAX Duty = 5062%(X100), DQS PI = 12
7378 09:59:48.978918 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7379 09:59:48.981917 [-4] AVG Duty = 4968%(X100)
7380 09:59:48.981998
7381 09:59:48.982061 ==DQ 1 ==
7382 09:59:48.985291 Final DQ duty delay cell = 0
7383 09:59:48.988590 [0] MAX Duty = 5124%(X100), DQS PI = 16
7384 09:59:48.992407 [0] MIN Duty = 4938%(X100), DQS PI = 10
7385 09:59:48.995537 [0] AVG Duty = 5031%(X100)
7386 09:59:48.995679
7387 09:59:48.998669 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7388 09:59:48.998749
7389 09:59:49.002307 CH1 DQ 1 Duty spec in!! Max-Min= 186%
7390 09:59:49.005264 [DutyScan_Calibration_Flow] ====Done====
7391 09:59:49.008956 nWR fixed to 30
7392 09:59:49.012484 [ModeRegInit_LP4] CH0 RK0
7393 09:59:49.012568 [ModeRegInit_LP4] CH0 RK1
7394 09:59:49.015483 [ModeRegInit_LP4] CH1 RK0
7395 09:59:49.018484 [ModeRegInit_LP4] CH1 RK1
7396 09:59:49.018566 match AC timing 5
7397 09:59:49.025197 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7398 09:59:49.028635 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7399 09:59:49.031882 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7400 09:59:49.039003 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7401 09:59:49.041869 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7402 09:59:49.041957 [MiockJmeterHQA]
7403 09:59:49.042022
7404 09:59:49.045206 [DramcMiockJmeter] u1RxGatingPI = 0
7405 09:59:49.048853 0 : 4252, 4027
7406 09:59:49.048938 4 : 4252, 4027
7407 09:59:49.052059 8 : 4253, 4026
7408 09:59:49.052160 12 : 4253, 4026
7409 09:59:49.052288 16 : 4250, 4027
7410 09:59:49.055313 20 : 4363, 4137
7411 09:59:49.055401 24 : 4252, 4027
7412 09:59:49.058301 28 : 4363, 4138
7413 09:59:49.058385 32 : 4253, 4026
7414 09:59:49.061533 36 : 4252, 4027
7415 09:59:49.061658 40 : 4252, 4027
7416 09:59:49.065128 44 : 4257, 4031
7417 09:59:49.065211 48 : 4252, 4027
7418 09:59:49.065276 52 : 4363, 4137
7419 09:59:49.068406 56 : 4363, 4138
7420 09:59:49.068490 60 : 4250, 4027
7421 09:59:49.071864 64 : 4250, 4027
7422 09:59:49.071947 68 : 4250, 4027
7423 09:59:49.074722 72 : 4250, 4027
7424 09:59:49.074822 76 : 4252, 4029
7425 09:59:49.078465 80 : 4361, 4138
7426 09:59:49.078542 84 : 4250, 4026
7427 09:59:49.078607 88 : 4250, 173
7428 09:59:49.081692 92 : 4360, 0
7429 09:59:49.081776 96 : 4255, 0
7430 09:59:49.085272 100 : 4360, 0
7431 09:59:49.085373 104 : 4360, 0
7432 09:59:49.085464 108 : 4250, 0
7433 09:59:49.088452 112 : 4249, 0
7434 09:59:49.088537 116 : 4250, 0
7435 09:59:49.088603 120 : 4250, 0
7436 09:59:49.091654 124 : 4252, 0
7437 09:59:49.091738 128 : 4250, 0
7438 09:59:49.095135 132 : 4253, 0
7439 09:59:49.095218 136 : 4249, 0
7440 09:59:49.095285 140 : 4250, 0
7441 09:59:49.099131 144 : 4255, 0
7442 09:59:49.099215 148 : 4360, 0
7443 09:59:49.101455 152 : 4360, 0
7444 09:59:49.101597 156 : 4363, 0
7445 09:59:49.101709 160 : 4250, 0
7446 09:59:49.105102 164 : 4250, 0
7447 09:59:49.105215 168 : 4250, 0
7448 09:59:49.105312 172 : 4250, 0
7449 09:59:49.108289 176 : 4250, 0
7450 09:59:49.108402 180 : 4250, 0
7451 09:59:49.111941 184 : 4253, 0
7452 09:59:49.112015 188 : 4249, 0
7453 09:59:49.112100 192 : 4361, 0
7454 09:59:49.114952 196 : 4250, 0
7455 09:59:49.115043 200 : 4360, 0
7456 09:59:49.118110 204 : 4361, 853
7457 09:59:49.118206 208 : 4250, 3788
7458 09:59:49.121308 212 : 4250, 4026
7459 09:59:49.121421 216 : 4250, 4026
7460 09:59:49.125045 220 : 4249, 4027
7461 09:59:49.125137 224 : 4250, 4027
7462 09:59:49.125200 228 : 4250, 4027
7463 09:59:49.127866 232 : 4250, 4027
7464 09:59:49.127972 236 : 4360, 4138
7465 09:59:49.131539 240 : 4360, 4138
7466 09:59:49.131616 244 : 4250, 4026
7467 09:59:49.134671 248 : 4361, 4137
7468 09:59:49.134749 252 : 4361, 4137
7469 09:59:49.138345 256 : 4249, 4027
7470 09:59:49.138422 260 : 4249, 4027
7471 09:59:49.141311 264 : 4250, 4027
7472 09:59:49.141412 268 : 4250, 4026
7473 09:59:49.144778 272 : 4250, 4027
7474 09:59:49.144894 276 : 4250, 4027
7475 09:59:49.148222 280 : 4250, 4027
7476 09:59:49.148333 284 : 4250, 4026
7477 09:59:49.148448 288 : 4360, 4137
7478 09:59:49.151304 292 : 4360, 4138
7479 09:59:49.151389 296 : 4247, 4024
7480 09:59:49.155116 300 : 4360, 4138
7481 09:59:49.155199 304 : 4249, 4027
7482 09:59:49.158260 308 : 4250, 4019
7483 09:59:49.158339 312 : 4250, 2374
7484 09:59:49.161703 316 : 4253, 27
7485 09:59:49.161780
7486 09:59:49.161842 MIOCK jitter meter ch=0
7487 09:59:49.161982
7488 09:59:49.165005 1T = (316-88) = 228 dly cells
7489 09:59:49.171929 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps
7490 09:59:49.172057 ==
7491 09:59:49.174687 Dram Type= 6, Freq= 0, CH_0, rank 0
7492 09:59:49.178111 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7493 09:59:49.178188 ==
7494 09:59:49.185006 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7495 09:59:49.188322 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7496 09:59:49.191331 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7497 09:59:49.198053 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7498 09:59:49.208067 [CA 0] Center 42 (12~73) winsize 62
7499 09:59:49.211282 [CA 1] Center 42 (12~73) winsize 62
7500 09:59:49.214931 [CA 2] Center 38 (8~68) winsize 61
7501 09:59:49.217933 [CA 3] Center 37 (8~67) winsize 60
7502 09:59:49.221699 [CA 4] Center 36 (6~66) winsize 61
7503 09:59:49.224518 [CA 5] Center 35 (6~64) winsize 59
7504 09:59:49.224594
7505 09:59:49.228334 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7506 09:59:49.228410
7507 09:59:49.231597 [CATrainingPosCal] consider 1 rank data
7508 09:59:49.234895 u2DelayCellTimex100 = 285/100 ps
7509 09:59:49.237918 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7510 09:59:49.244445 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7511 09:59:49.248073 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7512 09:59:49.251121 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7513 09:59:49.255044 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7514 09:59:49.258215 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7515 09:59:49.258290
7516 09:59:49.261060 CA PerBit enable=1, Macro0, CA PI delay=35
7517 09:59:49.261132
7518 09:59:49.264905 [CBTSetCACLKResult] CA Dly = 35
7519 09:59:49.264985 CS Dly: 9 (0~40)
7520 09:59:49.271036 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7521 09:59:49.274736 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7522 09:59:49.274812 ==
7523 09:59:49.278047 Dram Type= 6, Freq= 0, CH_0, rank 1
7524 09:59:49.281507 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7525 09:59:49.281604 ==
7526 09:59:49.287782 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7527 09:59:49.291766 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7528 09:59:49.294993 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7529 09:59:49.301098 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7530 09:59:49.311220 [CA 0] Center 42 (12~73) winsize 62
7531 09:59:49.314466 [CA 1] Center 42 (12~73) winsize 62
7532 09:59:49.317872 [CA 2] Center 38 (8~68) winsize 61
7533 09:59:49.321003 [CA 3] Center 38 (8~68) winsize 61
7534 09:59:49.324521 [CA 4] Center 36 (6~66) winsize 61
7535 09:59:49.327720 [CA 5] Center 35 (5~65) winsize 61
7536 09:59:49.327806
7537 09:59:49.331104 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7538 09:59:49.331178
7539 09:59:49.334252 [CATrainingPosCal] consider 2 rank data
7540 09:59:49.337446 u2DelayCellTimex100 = 285/100 ps
7541 09:59:49.341185 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7542 09:59:49.347453 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7543 09:59:49.351260 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7544 09:59:49.354418 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7545 09:59:49.357500 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7546 09:59:49.361463 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7547 09:59:49.361559
7548 09:59:49.364489 CA PerBit enable=1, Macro0, CA PI delay=35
7549 09:59:49.364571
7550 09:59:49.367664 [CBTSetCACLKResult] CA Dly = 35
7551 09:59:49.370704 CS Dly: 10 (0~42)
7552 09:59:49.374019 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7553 09:59:49.377584 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7554 09:59:49.377682
7555 09:59:49.380649 ----->DramcWriteLeveling(PI) begin...
7556 09:59:49.380732 ==
7557 09:59:49.384285 Dram Type= 6, Freq= 0, CH_0, rank 0
7558 09:59:49.390669 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7559 09:59:49.390754 ==
7560 09:59:49.394208 Write leveling (Byte 0): 33 => 33
7561 09:59:49.394327 Write leveling (Byte 1): 27 => 27
7562 09:59:49.397169 DramcWriteLeveling(PI) end<-----
7563 09:59:49.397269
7564 09:59:49.397336 ==
7565 09:59:49.401245 Dram Type= 6, Freq= 0, CH_0, rank 0
7566 09:59:49.407341 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7567 09:59:49.407467 ==
7568 09:59:49.410800 [Gating] SW mode calibration
7569 09:59:49.417440 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7570 09:59:49.420779 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7571 09:59:49.427126 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7572 09:59:49.430791 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7573 09:59:49.433929 1 4 8 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
7574 09:59:49.440657 1 4 12 | B1->B0 | 2323 3737 | 0 0 | (0 0) (1 1)
7575 09:59:49.444163 1 4 16 | B1->B0 | 2323 3535 | 0 1 | (0 0) (1 1)
7576 09:59:49.447235 1 4 20 | B1->B0 | 3434 3635 | 0 1 | (0 0) (0 0)
7577 09:59:49.453825 1 4 24 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
7578 09:59:49.456974 1 4 28 | B1->B0 | 3434 3636 | 1 0 | (1 1) (1 1)
7579 09:59:49.460750 1 5 0 | B1->B0 | 3434 3535 | 1 0 | (1 1) (1 1)
7580 09:59:49.466893 1 5 4 | B1->B0 | 3434 3736 | 1 1 | (1 1) (1 1)
7581 09:59:49.470661 1 5 8 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7582 09:59:49.473453 1 5 12 | B1->B0 | 3434 2727 | 1 0 | (1 1) (0 0)
7583 09:59:49.477157 1 5 16 | B1->B0 | 3434 2929 | 1 0 | (0 1) (0 0)
7584 09:59:49.483880 1 5 20 | B1->B0 | 2929 2c2b | 0 1 | (1 0) (0 0)
7585 09:59:49.487138 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7586 09:59:49.490603 1 5 28 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
7587 09:59:49.497008 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7588 09:59:49.500122 1 6 4 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)
7589 09:59:49.503423 1 6 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (0 0)
7590 09:59:49.510457 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7591 09:59:49.513689 1 6 16 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)
7592 09:59:49.517139 1 6 20 | B1->B0 | 4545 4645 | 0 1 | (0 0) (0 0)
7593 09:59:49.523804 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7594 09:59:49.527175 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7595 09:59:49.530049 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7596 09:59:49.536944 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7597 09:59:49.540522 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7598 09:59:49.543358 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7599 09:59:49.550234 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7600 09:59:49.553444 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7601 09:59:49.556874 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7602 09:59:49.563851 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7603 09:59:49.566963 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7604 09:59:49.570173 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7605 09:59:49.574018 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7606 09:59:49.580546 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7607 09:59:49.583507 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7608 09:59:49.586932 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7609 09:59:49.593407 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7610 09:59:49.597141 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7611 09:59:49.600172 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7612 09:59:49.607137 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7613 09:59:49.610140 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7614 09:59:49.613834 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7615 09:59:49.619859 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7616 09:59:49.623310 Total UI for P1: 0, mck2ui 16
7617 09:59:49.626348 best dqsien dly found for B0: ( 1, 9, 10)
7618 09:59:49.630281 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7619 09:59:49.633420 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7620 09:59:49.636567 Total UI for P1: 0, mck2ui 16
7621 09:59:49.640370 best dqsien dly found for B1: ( 1, 9, 18)
7622 09:59:49.643378 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7623 09:59:49.646294 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7624 09:59:49.649715
7625 09:59:49.653292 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7626 09:59:49.656736 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7627 09:59:49.659990 [Gating] SW calibration Done
7628 09:59:49.660129 ==
7629 09:59:49.663136 Dram Type= 6, Freq= 0, CH_0, rank 0
7630 09:59:49.666212 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7631 09:59:49.666316 ==
7632 09:59:49.666412 RX Vref Scan: 0
7633 09:59:49.669798
7634 09:59:49.669924 RX Vref 0 -> 0, step: 1
7635 09:59:49.670028
7636 09:59:49.672814 RX Delay 0 -> 252, step: 8
7637 09:59:49.676195 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7638 09:59:49.679680 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7639 09:59:49.686229 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7640 09:59:49.689995 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
7641 09:59:49.692971 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7642 09:59:49.695960 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7643 09:59:49.699791 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
7644 09:59:49.705965 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7645 09:59:49.709281 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7646 09:59:49.712921 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
7647 09:59:49.716172 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7648 09:59:49.720116 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7649 09:59:49.726290 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7650 09:59:49.729572 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
7651 09:59:49.733015 iDelay=200, Bit 14, Center 143 (96 ~ 191) 96
7652 09:59:49.735922 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7653 09:59:49.736009 ==
7654 09:59:49.739919 Dram Type= 6, Freq= 0, CH_0, rank 0
7655 09:59:49.742861 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7656 09:59:49.746016 ==
7657 09:59:49.746086 DQS Delay:
7658 09:59:49.746153 DQS0 = 0, DQS1 = 0
7659 09:59:49.749672 DQM Delay:
7660 09:59:49.749743 DQM0 = 136, DQM1 = 130
7661 09:59:49.752707 DQ Delay:
7662 09:59:49.756382 DQ0 =135, DQ1 =143, DQ2 =131, DQ3 =135
7663 09:59:49.759915 DQ4 =139, DQ5 =123, DQ6 =143, DQ7 =143
7664 09:59:49.762540 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =123
7665 09:59:49.766389 DQ12 =131, DQ13 =139, DQ14 =143, DQ15 =135
7666 09:59:49.766480
7667 09:59:49.766545
7668 09:59:49.766606 ==
7669 09:59:49.769286 Dram Type= 6, Freq= 0, CH_0, rank 0
7670 09:59:49.772482 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7671 09:59:49.772584 ==
7672 09:59:49.772679
7673 09:59:49.776220
7674 09:59:49.776323 TX Vref Scan disable
7675 09:59:49.779441 == TX Byte 0 ==
7676 09:59:49.782714 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7677 09:59:49.786002 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7678 09:59:49.789137 == TX Byte 1 ==
7679 09:59:49.792748 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7680 09:59:49.796282 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7681 09:59:49.796371 ==
7682 09:59:49.799379 Dram Type= 6, Freq= 0, CH_0, rank 0
7683 09:59:49.806172 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7684 09:59:49.806273 ==
7685 09:59:49.816883
7686 09:59:49.820324 TX Vref early break, caculate TX vref
7687 09:59:49.823865 TX Vref=16, minBit 0, minWin=23, winSum=379
7688 09:59:49.827098 TX Vref=18, minBit 1, minWin=24, winSum=391
7689 09:59:49.830368 TX Vref=20, minBit 3, minWin=24, winSum=402
7690 09:59:49.833840 TX Vref=22, minBit 7, minWin=24, winSum=408
7691 09:59:49.837243 TX Vref=24, minBit 7, minWin=25, winSum=415
7692 09:59:49.843308 TX Vref=26, minBit 5, minWin=26, winSum=430
7693 09:59:49.847043 TX Vref=28, minBit 1, minWin=25, winSum=423
7694 09:59:49.850150 TX Vref=30, minBit 5, minWin=25, winSum=418
7695 09:59:49.853415 TX Vref=32, minBit 6, minWin=24, winSum=407
7696 09:59:49.860172 [TxChooseVref] Worse bit 5, Min win 26, Win sum 430, Final Vref 26
7697 09:59:49.860305
7698 09:59:49.863780 Final TX Range 0 Vref 26
7699 09:59:49.863892
7700 09:59:49.863990 ==
7701 09:59:49.866771 Dram Type= 6, Freq= 0, CH_0, rank 0
7702 09:59:49.870444 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7703 09:59:49.870563 ==
7704 09:59:49.870667
7705 09:59:49.870760
7706 09:59:49.873625 TX Vref Scan disable
7707 09:59:49.877499 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
7708 09:59:49.880438 == TX Byte 0 ==
7709 09:59:49.883848 u2DelayCellOfst[0]=13 cells (4 PI)
7710 09:59:49.886859 u2DelayCellOfst[1]=17 cells (5 PI)
7711 09:59:49.889870 u2DelayCellOfst[2]=10 cells (3 PI)
7712 09:59:49.893566 u2DelayCellOfst[3]=10 cells (3 PI)
7713 09:59:49.897056 u2DelayCellOfst[4]=10 cells (3 PI)
7714 09:59:49.897146 u2DelayCellOfst[5]=0 cells (0 PI)
7715 09:59:49.899794 u2DelayCellOfst[6]=17 cells (5 PI)
7716 09:59:49.903592 u2DelayCellOfst[7]=17 cells (5 PI)
7717 09:59:49.910357 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7718 09:59:49.913523 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7719 09:59:49.913619 == TX Byte 1 ==
7720 09:59:49.916682 u2DelayCellOfst[8]=0 cells (0 PI)
7721 09:59:49.920213 u2DelayCellOfst[9]=0 cells (0 PI)
7722 09:59:49.923455 u2DelayCellOfst[10]=6 cells (2 PI)
7723 09:59:49.927226 u2DelayCellOfst[11]=6 cells (2 PI)
7724 09:59:49.930156 u2DelayCellOfst[12]=10 cells (3 PI)
7725 09:59:49.933418 u2DelayCellOfst[13]=10 cells (3 PI)
7726 09:59:49.936493 u2DelayCellOfst[14]=13 cells (4 PI)
7727 09:59:49.939824 u2DelayCellOfst[15]=10 cells (3 PI)
7728 09:59:49.943483 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7729 09:59:49.946834 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7730 09:59:49.949943 DramC Write-DBI on
7731 09:59:49.950027 ==
7732 09:59:49.953394 Dram Type= 6, Freq= 0, CH_0, rank 0
7733 09:59:49.957047 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7734 09:59:49.957134 ==
7735 09:59:49.957199
7736 09:59:49.957260
7737 09:59:49.960211 TX Vref Scan disable
7738 09:59:49.963236 == TX Byte 0 ==
7739 09:59:49.966438 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
7740 09:59:49.970135 == TX Byte 1 ==
7741 09:59:49.972937 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7742 09:59:49.973034 DramC Write-DBI off
7743 09:59:49.973121
7744 09:59:49.976674 [DATLAT]
7745 09:59:49.976787 Freq=1600, CH0 RK0
7746 09:59:49.976889
7747 09:59:49.979983 DATLAT Default: 0xf
7748 09:59:49.980068 0, 0xFFFF, sum = 0
7749 09:59:49.983357 1, 0xFFFF, sum = 0
7750 09:59:49.983438 2, 0xFFFF, sum = 0
7751 09:59:49.986507 3, 0xFFFF, sum = 0
7752 09:59:49.986588 4, 0xFFFF, sum = 0
7753 09:59:49.989855 5, 0xFFFF, sum = 0
7754 09:59:49.989942 6, 0xFFFF, sum = 0
7755 09:59:49.993134 7, 0xFFFF, sum = 0
7756 09:59:49.993237 8, 0xFFFF, sum = 0
7757 09:59:49.996806 9, 0xFFFF, sum = 0
7758 09:59:50.000005 10, 0xFFFF, sum = 0
7759 09:59:50.000151 11, 0xFFFF, sum = 0
7760 09:59:50.003014 12, 0xFFFF, sum = 0
7761 09:59:50.003142 13, 0xFFFF, sum = 0
7762 09:59:50.006602 14, 0x0, sum = 1
7763 09:59:50.006689 15, 0x0, sum = 2
7764 09:59:50.009642 16, 0x0, sum = 3
7765 09:59:50.009725 17, 0x0, sum = 4
7766 09:59:50.009814 best_step = 15
7767 09:59:50.009892
7768 09:59:50.012785 ==
7769 09:59:50.016809 Dram Type= 6, Freq= 0, CH_0, rank 0
7770 09:59:50.019400 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7771 09:59:50.019479 ==
7772 09:59:50.019568 RX Vref Scan: 1
7773 09:59:50.019647
7774 09:59:50.023062 Set Vref Range= 24 -> 127
7775 09:59:50.023143
7776 09:59:50.026202 RX Vref 24 -> 127, step: 1
7777 09:59:50.026278
7778 09:59:50.029362 RX Delay 27 -> 252, step: 4
7779 09:59:50.029463
7780 09:59:50.033148 Set Vref, RX VrefLevel [Byte0]: 24
7781 09:59:50.036231 [Byte1]: 24
7782 09:59:50.036319
7783 09:59:50.039366 Set Vref, RX VrefLevel [Byte0]: 25
7784 09:59:50.042763 [Byte1]: 25
7785 09:59:50.042850
7786 09:59:50.046183 Set Vref, RX VrefLevel [Byte0]: 26
7787 09:59:50.049109 [Byte1]: 26
7788 09:59:50.052978
7789 09:59:50.053061 Set Vref, RX VrefLevel [Byte0]: 27
7790 09:59:50.056031 [Byte1]: 27
7791 09:59:50.060079
7792 09:59:50.060172 Set Vref, RX VrefLevel [Byte0]: 28
7793 09:59:50.063736 [Byte1]: 28
7794 09:59:50.067955
7795 09:59:50.068037 Set Vref, RX VrefLevel [Byte0]: 29
7796 09:59:50.070929 [Byte1]: 29
7797 09:59:50.075771
7798 09:59:50.075888 Set Vref, RX VrefLevel [Byte0]: 30
7799 09:59:50.078929 [Byte1]: 30
7800 09:59:50.082748
7801 09:59:50.082846 Set Vref, RX VrefLevel [Byte0]: 31
7802 09:59:50.086058 [Byte1]: 31
7803 09:59:50.090252
7804 09:59:50.090339 Set Vref, RX VrefLevel [Byte0]: 32
7805 09:59:50.093840 [Byte1]: 32
7806 09:59:50.097827
7807 09:59:50.097914 Set Vref, RX VrefLevel [Byte0]: 33
7808 09:59:50.101516 [Byte1]: 33
7809 09:59:50.105701
7810 09:59:50.105793 Set Vref, RX VrefLevel [Byte0]: 34
7811 09:59:50.117089 [Byte1]: 34
7812 09:59:50.117271
7813 09:59:50.117393 Set Vref, RX VrefLevel [Byte0]: 35
7814 09:59:50.117490 [Byte1]: 35
7815 09:59:50.120877
7816 09:59:50.120962 Set Vref, RX VrefLevel [Byte0]: 36
7817 09:59:50.123937 [Byte1]: 36
7818 09:59:50.128379
7819 09:59:50.128481 Set Vref, RX VrefLevel [Byte0]: 37
7820 09:59:50.131516 [Byte1]: 37
7821 09:59:50.135903
7822 09:59:50.136003 Set Vref, RX VrefLevel [Byte0]: 38
7823 09:59:50.139149 [Byte1]: 38
7824 09:59:50.142939
7825 09:59:50.143038 Set Vref, RX VrefLevel [Byte0]: 39
7826 09:59:50.146650 [Byte1]: 39
7827 09:59:50.150435
7828 09:59:50.150526 Set Vref, RX VrefLevel [Byte0]: 40
7829 09:59:50.154311 [Byte1]: 40
7830 09:59:50.158274
7831 09:59:50.158378 Set Vref, RX VrefLevel [Byte0]: 41
7832 09:59:50.161247 [Byte1]: 41
7833 09:59:50.166006
7834 09:59:50.166101 Set Vref, RX VrefLevel [Byte0]: 42
7835 09:59:50.168915 [Byte1]: 42
7836 09:59:50.173527
7837 09:59:50.173647 Set Vref, RX VrefLevel [Byte0]: 43
7838 09:59:50.176757 [Byte1]: 43
7839 09:59:50.180911
7840 09:59:50.180995 Set Vref, RX VrefLevel [Byte0]: 44
7841 09:59:50.183977 [Byte1]: 44
7842 09:59:50.188689
7843 09:59:50.188775 Set Vref, RX VrefLevel [Byte0]: 45
7844 09:59:50.191679 [Byte1]: 45
7845 09:59:50.195983
7846 09:59:50.196083 Set Vref, RX VrefLevel [Byte0]: 46
7847 09:59:50.199044 [Byte1]: 46
7848 09:59:50.203557
7849 09:59:50.203662 Set Vref, RX VrefLevel [Byte0]: 47
7850 09:59:50.206390 [Byte1]: 47
7851 09:59:50.211249
7852 09:59:50.211366 Set Vref, RX VrefLevel [Byte0]: 48
7853 09:59:50.214126 [Byte1]: 48
7854 09:59:50.218416
7855 09:59:50.218534 Set Vref, RX VrefLevel [Byte0]: 49
7856 09:59:50.221552 [Byte1]: 49
7857 09:59:50.225822
7858 09:59:50.225929 Set Vref, RX VrefLevel [Byte0]: 50
7859 09:59:50.229104 [Byte1]: 50
7860 09:59:50.233625
7861 09:59:50.233731 Set Vref, RX VrefLevel [Byte0]: 51
7862 09:59:50.236938 [Byte1]: 51
7863 09:59:50.241124
7864 09:59:50.241242 Set Vref, RX VrefLevel [Byte0]: 52
7865 09:59:50.244363 [Byte1]: 52
7866 09:59:50.248876
7867 09:59:50.249040 Set Vref, RX VrefLevel [Byte0]: 53
7868 09:59:50.251823 [Byte1]: 53
7869 09:59:50.256379
7870 09:59:50.256502 Set Vref, RX VrefLevel [Byte0]: 54
7871 09:59:50.259565 [Byte1]: 54
7872 09:59:50.263937
7873 09:59:50.264056 Set Vref, RX VrefLevel [Byte0]: 55
7874 09:59:50.267174 [Byte1]: 55
7875 09:59:50.271197
7876 09:59:50.271299 Set Vref, RX VrefLevel [Byte0]: 56
7877 09:59:50.274394 [Byte1]: 56
7878 09:59:50.278485
7879 09:59:50.278579 Set Vref, RX VrefLevel [Byte0]: 57
7880 09:59:50.282347 [Byte1]: 57
7881 09:59:50.286402
7882 09:59:50.286482 Set Vref, RX VrefLevel [Byte0]: 58
7883 09:59:50.289319 [Byte1]: 58
7884 09:59:50.293783
7885 09:59:50.293862 Set Vref, RX VrefLevel [Byte0]: 59
7886 09:59:50.297015 [Byte1]: 59
7887 09:59:50.301408
7888 09:59:50.301487 Set Vref, RX VrefLevel [Byte0]: 60
7889 09:59:50.304368 [Byte1]: 60
7890 09:59:50.308900
7891 09:59:50.308981 Set Vref, RX VrefLevel [Byte0]: 61
7892 09:59:50.312583 [Byte1]: 61
7893 09:59:50.316224
7894 09:59:50.316311 Set Vref, RX VrefLevel [Byte0]: 62
7895 09:59:50.319581 [Byte1]: 62
7896 09:59:50.323715
7897 09:59:50.323827 Set Vref, RX VrefLevel [Byte0]: 63
7898 09:59:50.327233 [Byte1]: 63
7899 09:59:50.331591
7900 09:59:50.331702 Set Vref, RX VrefLevel [Byte0]: 64
7901 09:59:50.334694 [Byte1]: 64
7902 09:59:50.339205
7903 09:59:50.339309 Set Vref, RX VrefLevel [Byte0]: 65
7904 09:59:50.342296 [Byte1]: 65
7905 09:59:50.347047
7906 09:59:50.347174 Set Vref, RX VrefLevel [Byte0]: 66
7907 09:59:50.350025 [Byte1]: 66
7908 09:59:50.354435
7909 09:59:50.354576 Set Vref, RX VrefLevel [Byte0]: 67
7910 09:59:50.357404 [Byte1]: 67
7911 09:59:50.361385
7912 09:59:50.361489 Set Vref, RX VrefLevel [Byte0]: 68
7913 09:59:50.364918 [Byte1]: 68
7914 09:59:50.369239
7915 09:59:50.369330 Set Vref, RX VrefLevel [Byte0]: 69
7916 09:59:50.372257 [Byte1]: 69
7917 09:59:50.376546
7918 09:59:50.376658 Set Vref, RX VrefLevel [Byte0]: 70
7919 09:59:50.379881 [Byte1]: 70
7920 09:59:50.384070
7921 09:59:50.384233 Set Vref, RX VrefLevel [Byte0]: 71
7922 09:59:50.387433 [Byte1]: 71
7923 09:59:50.391805
7924 09:59:50.391944 Set Vref, RX VrefLevel [Byte0]: 72
7925 09:59:50.395017 [Byte1]: 72
7926 09:59:50.399458
7927 09:59:50.399569 Final RX Vref Byte 0 = 59 to rank0
7928 09:59:50.402870 Final RX Vref Byte 1 = 63 to rank0
7929 09:59:50.405833 Final RX Vref Byte 0 = 59 to rank1
7930 09:59:50.409101 Final RX Vref Byte 1 = 63 to rank1==
7931 09:59:50.412767 Dram Type= 6, Freq= 0, CH_0, rank 0
7932 09:59:50.419640 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7933 09:59:50.419734 ==
7934 09:59:50.419802 DQS Delay:
7935 09:59:50.419872 DQS0 = 0, DQS1 = 0
7936 09:59:50.422485 DQM Delay:
7937 09:59:50.422559 DQM0 = 134, DQM1 = 128
7938 09:59:50.426080 DQ Delay:
7939 09:59:50.429178 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =132
7940 09:59:50.432560 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =140
7941 09:59:50.436136 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =120
7942 09:59:50.439058 DQ12 =132, DQ13 =132, DQ14 =140, DQ15 =136
7943 09:59:50.439141
7944 09:59:50.439205
7945 09:59:50.439265
7946 09:59:50.442396 [DramC_TX_OE_Calibration] TA2
7947 09:59:50.445589 Original DQ_B0 (3 6) =30, OEN = 27
7948 09:59:50.449225 Original DQ_B1 (3 6) =30, OEN = 27
7949 09:59:50.452431 24, 0x0, End_B0=24 End_B1=24
7950 09:59:50.452515 25, 0x0, End_B0=25 End_B1=25
7951 09:59:50.455695 26, 0x0, End_B0=26 End_B1=26
7952 09:59:50.459460 27, 0x0, End_B0=27 End_B1=27
7953 09:59:50.462508 28, 0x0, End_B0=28 End_B1=28
7954 09:59:50.462587 29, 0x0, End_B0=29 End_B1=29
7955 09:59:50.465790 30, 0x0, End_B0=30 End_B1=30
7956 09:59:50.469108 31, 0x4141, End_B0=30 End_B1=30
7957 09:59:50.472299 Byte0 end_step=30 best_step=27
7958 09:59:50.475587 Byte1 end_step=30 best_step=27
7959 09:59:50.479248 Byte0 TX OE(2T, 0.5T) = (3, 3)
7960 09:59:50.482018 Byte1 TX OE(2T, 0.5T) = (3, 3)
7961 09:59:50.482116
7962 09:59:50.482183
7963 09:59:50.489009 [DQSOSCAuto] RK0, (LSB)MR18= 0x2420, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
7964 09:59:50.492245 CH0 RK0: MR19=303, MR18=2420
7965 09:59:50.498892 CH0_RK0: MR19=0x303, MR18=0x2420, DQSOSC=391, MR23=63, INC=24, DEC=16
7966 09:59:50.499032
7967 09:59:50.501997 ----->DramcWriteLeveling(PI) begin...
7968 09:59:50.502127 ==
7969 09:59:50.505783 Dram Type= 6, Freq= 0, CH_0, rank 1
7970 09:59:50.508809 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7971 09:59:50.508946 ==
7972 09:59:50.512590 Write leveling (Byte 0): 34 => 34
7973 09:59:50.515956 Write leveling (Byte 1): 26 => 26
7974 09:59:50.518735 DramcWriteLeveling(PI) end<-----
7975 09:59:50.518863
7976 09:59:50.518958 ==
7977 09:59:50.522262 Dram Type= 6, Freq= 0, CH_0, rank 1
7978 09:59:50.525693 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7979 09:59:50.525792 ==
7980 09:59:50.528592 [Gating] SW mode calibration
7981 09:59:50.535252 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7982 09:59:50.542174 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7983 09:59:50.545567 1 4 0 | B1->B0 | 2323 2525 | 0 1 | (0 0) (1 1)
7984 09:59:50.548746 1 4 4 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
7985 09:59:50.555844 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7986 09:59:50.558953 1 4 12 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
7987 09:59:50.562189 1 4 16 | B1->B0 | 2f2f 3434 | 0 0 | (0 0) (0 0)
7988 09:59:50.568667 1 4 20 | B1->B0 | 3434 3e3d | 1 1 | (1 1) (0 0)
7989 09:59:50.572280 1 4 24 | B1->B0 | 3434 3a3a | 1 1 | (1 1) (0 0)
7990 09:59:50.575473 1 4 28 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
7991 09:59:50.581648 1 5 0 | B1->B0 | 3434 3838 | 1 0 | (1 1) (1 1)
7992 09:59:50.585247 1 5 4 | B1->B0 | 3434 3838 | 1 0 | (1 1) (0 0)
7993 09:59:50.588616 1 5 8 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7994 09:59:50.595213 1 5 12 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 1)
7995 09:59:50.598284 1 5 16 | B1->B0 | 3030 2525 | 0 0 | (0 1) (1 0)
7996 09:59:50.601730 1 5 20 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
7997 09:59:50.608638 1 5 24 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
7998 09:59:50.611892 1 5 28 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)
7999 09:59:50.614924 1 6 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8000 09:59:50.621780 1 6 4 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
8001 09:59:50.625462 1 6 8 | B1->B0 | 2323 2625 | 0 1 | (0 0) (1 1)
8002 09:59:50.628345 1 6 12 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (0 0)
8003 09:59:50.635539 1 6 16 | B1->B0 | 3d3d 4645 | 0 1 | (0 0) (0 0)
8004 09:59:50.638109 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8005 09:59:50.641836 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8006 09:59:50.648574 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8007 09:59:50.651870 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8008 09:59:50.654844 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8009 09:59:50.661458 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8010 09:59:50.665106 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8011 09:59:50.668301 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8012 09:59:50.671447 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8013 09:59:50.678103 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8014 09:59:50.681253 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8015 09:59:50.684854 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8016 09:59:50.691565 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8017 09:59:50.694552 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8018 09:59:50.698458 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8019 09:59:50.704530 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8020 09:59:50.708125 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8021 09:59:50.711653 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8022 09:59:50.717963 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8023 09:59:50.721667 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8024 09:59:50.724623 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8025 09:59:50.731778 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8026 09:59:50.734647 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8027 09:59:50.738285 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8028 09:59:50.744555 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8029 09:59:50.744682 Total UI for P1: 0, mck2ui 16
8030 09:59:50.751516 best dqsien dly found for B0: ( 1, 9, 14)
8031 09:59:50.751675 Total UI for P1: 0, mck2ui 16
8032 09:59:50.757763 best dqsien dly found for B1: ( 1, 9, 14)
8033 09:59:50.760811 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8034 09:59:50.764562 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8035 09:59:50.764685
8036 09:59:50.767562 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8037 09:59:50.770938 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8038 09:59:50.774232 [Gating] SW calibration Done
8039 09:59:50.774315 ==
8040 09:59:50.777798 Dram Type= 6, Freq= 0, CH_0, rank 1
8041 09:59:50.780918 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8042 09:59:50.781035 ==
8043 09:59:50.784087 RX Vref Scan: 0
8044 09:59:50.784168
8045 09:59:50.784269 RX Vref 0 -> 0, step: 1
8046 09:59:50.784359
8047 09:59:50.787470 RX Delay 0 -> 252, step: 8
8048 09:59:50.791043 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8049 09:59:50.797367 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8050 09:59:50.801004 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8051 09:59:50.804004 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8052 09:59:50.807408 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8053 09:59:50.810949 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8054 09:59:50.817293 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8055 09:59:50.820828 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8056 09:59:50.823848 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8057 09:59:50.827410 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8058 09:59:50.830589 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8059 09:59:50.837460 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8060 09:59:50.840543 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8061 09:59:50.843896 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8062 09:59:50.846982 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8063 09:59:50.853825 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8064 09:59:50.853919 ==
8065 09:59:50.856929 Dram Type= 6, Freq= 0, CH_0, rank 1
8066 09:59:50.860418 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8067 09:59:50.860526 ==
8068 09:59:50.860619 DQS Delay:
8069 09:59:50.863962 DQS0 = 0, DQS1 = 0
8070 09:59:50.864068 DQM Delay:
8071 09:59:50.867121 DQM0 = 137, DQM1 = 128
8072 09:59:50.867226 DQ Delay:
8073 09:59:50.870118 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8074 09:59:50.873480 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8075 09:59:50.877369 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8076 09:59:50.880177 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8077 09:59:50.880282
8078 09:59:50.880381
8079 09:59:50.883403 ==
8080 09:59:50.886682 Dram Type= 6, Freq= 0, CH_0, rank 1
8081 09:59:50.890100 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8082 09:59:50.890204 ==
8083 09:59:50.890299
8084 09:59:50.890391
8085 09:59:50.893615 TX Vref Scan disable
8086 09:59:50.893703 == TX Byte 0 ==
8087 09:59:50.900094 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8088 09:59:50.903420 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8089 09:59:50.903540 == TX Byte 1 ==
8090 09:59:50.910116 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8091 09:59:50.913330 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8092 09:59:50.913411 ==
8093 09:59:50.916625 Dram Type= 6, Freq= 0, CH_0, rank 1
8094 09:59:50.920191 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8095 09:59:50.920316 ==
8096 09:59:50.934360
8097 09:59:50.937466 TX Vref early break, caculate TX vref
8098 09:59:50.941127 TX Vref=16, minBit 1, minWin=23, winSum=385
8099 09:59:50.944046 TX Vref=18, minBit 0, minWin=24, winSum=399
8100 09:59:50.947846 TX Vref=20, minBit 1, minWin=24, winSum=408
8101 09:59:50.950938 TX Vref=22, minBit 1, minWin=24, winSum=410
8102 09:59:50.954163 TX Vref=24, minBit 0, minWin=25, winSum=424
8103 09:59:50.960849 TX Vref=26, minBit 1, minWin=25, winSum=426
8104 09:59:50.964382 TX Vref=28, minBit 1, minWin=25, winSum=422
8105 09:59:50.968020 TX Vref=30, minBit 4, minWin=25, winSum=419
8106 09:59:50.970996 TX Vref=32, minBit 0, minWin=25, winSum=409
8107 09:59:50.974296 TX Vref=34, minBit 1, minWin=24, winSum=403
8108 09:59:50.980743 [TxChooseVref] Worse bit 1, Min win 25, Win sum 426, Final Vref 26
8109 09:59:50.980840
8110 09:59:50.984624 Final TX Range 0 Vref 26
8111 09:59:50.984711
8112 09:59:50.984777 ==
8113 09:59:50.987493 Dram Type= 6, Freq= 0, CH_0, rank 1
8114 09:59:50.990754 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8115 09:59:50.990865 ==
8116 09:59:50.990960
8117 09:59:50.991050
8118 09:59:50.993965 TX Vref Scan disable
8119 09:59:51.000467 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8120 09:59:51.000596 == TX Byte 0 ==
8121 09:59:51.003708 u2DelayCellOfst[0]=10 cells (3 PI)
8122 09:59:51.007030 u2DelayCellOfst[1]=13 cells (4 PI)
8123 09:59:51.010827 u2DelayCellOfst[2]=6 cells (2 PI)
8124 09:59:51.014222 u2DelayCellOfst[3]=6 cells (2 PI)
8125 09:59:51.017177 u2DelayCellOfst[4]=3 cells (1 PI)
8126 09:59:51.020755 u2DelayCellOfst[5]=0 cells (0 PI)
8127 09:59:51.024548 u2DelayCellOfst[6]=10 cells (3 PI)
8128 09:59:51.024662 u2DelayCellOfst[7]=13 cells (4 PI)
8129 09:59:51.030704 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8130 09:59:51.033597 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8131 09:59:51.037389 == TX Byte 1 ==
8132 09:59:51.037508 u2DelayCellOfst[8]=3 cells (1 PI)
8133 09:59:51.040527 u2DelayCellOfst[9]=0 cells (0 PI)
8134 09:59:51.044161 u2DelayCellOfst[10]=10 cells (3 PI)
8135 09:59:51.047365 u2DelayCellOfst[11]=3 cells (1 PI)
8136 09:59:51.050361 u2DelayCellOfst[12]=10 cells (3 PI)
8137 09:59:51.053490 u2DelayCellOfst[13]=10 cells (3 PI)
8138 09:59:51.056860 u2DelayCellOfst[14]=17 cells (5 PI)
8139 09:59:51.060308 u2DelayCellOfst[15]=10 cells (3 PI)
8140 09:59:51.063679 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8141 09:59:51.070280 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8142 09:59:51.070432 DramC Write-DBI on
8143 09:59:51.070540 ==
8144 09:59:51.073761 Dram Type= 6, Freq= 0, CH_0, rank 1
8145 09:59:51.077125 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8146 09:59:51.080407 ==
8147 09:59:51.080503
8148 09:59:51.080571
8149 09:59:51.080633 TX Vref Scan disable
8150 09:59:51.083537 == TX Byte 0 ==
8151 09:59:51.087388 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8152 09:59:51.090365 == TX Byte 1 ==
8153 09:59:51.093569 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8154 09:59:51.096968 DramC Write-DBI off
8155 09:59:51.097055
8156 09:59:51.097122 [DATLAT]
8157 09:59:51.097202 Freq=1600, CH0 RK1
8158 09:59:51.097264
8159 09:59:51.100261 DATLAT Default: 0xf
8160 09:59:51.100372 0, 0xFFFF, sum = 0
8161 09:59:51.103981 1, 0xFFFF, sum = 0
8162 09:59:51.107241 2, 0xFFFF, sum = 0
8163 09:59:51.107329 3, 0xFFFF, sum = 0
8164 09:59:51.110341 4, 0xFFFF, sum = 0
8165 09:59:51.110427 5, 0xFFFF, sum = 0
8166 09:59:51.113539 6, 0xFFFF, sum = 0
8167 09:59:51.113631 7, 0xFFFF, sum = 0
8168 09:59:51.116705 8, 0xFFFF, sum = 0
8169 09:59:51.116793 9, 0xFFFF, sum = 0
8170 09:59:51.120301 10, 0xFFFF, sum = 0
8171 09:59:51.120417 11, 0xFFFF, sum = 0
8172 09:59:51.123822 12, 0xFFFF, sum = 0
8173 09:59:51.123910 13, 0xFFFF, sum = 0
8174 09:59:51.126751 14, 0x0, sum = 1
8175 09:59:51.126864 15, 0x0, sum = 2
8176 09:59:51.130798 16, 0x0, sum = 3
8177 09:59:51.130906 17, 0x0, sum = 4
8178 09:59:51.133386 best_step = 15
8179 09:59:51.133463
8180 09:59:51.133525 ==
8181 09:59:51.137153 Dram Type= 6, Freq= 0, CH_0, rank 1
8182 09:59:51.140533 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8183 09:59:51.140618 ==
8184 09:59:51.143634 RX Vref Scan: 0
8185 09:59:51.143729
8186 09:59:51.143834 RX Vref 0 -> 0, step: 1
8187 09:59:51.143927
8188 09:59:51.147215 RX Delay 19 -> 252, step: 4
8189 09:59:51.150144 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8190 09:59:51.156725 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8191 09:59:51.160302 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8192 09:59:51.163305 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8193 09:59:51.166716 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8194 09:59:51.170279 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8195 09:59:51.176870 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8196 09:59:51.180236 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8197 09:59:51.183850 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8198 09:59:51.187001 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8199 09:59:51.190316 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8200 09:59:51.196596 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8201 09:59:51.200502 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8202 09:59:51.203293 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8203 09:59:51.206989 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8204 09:59:51.210029 iDelay=191, Bit 15, Center 136 (87 ~ 186) 100
8205 09:59:51.213528 ==
8206 09:59:51.213636 Dram Type= 6, Freq= 0, CH_0, rank 1
8207 09:59:51.219933 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8208 09:59:51.220019 ==
8209 09:59:51.220087 DQS Delay:
8210 09:59:51.223311 DQS0 = 0, DQS1 = 0
8211 09:59:51.223389 DQM Delay:
8212 09:59:51.226926 DQM0 = 134, DQM1 = 127
8213 09:59:51.227003 DQ Delay:
8214 09:59:51.230140 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =134
8215 09:59:51.233108 DQ4 =136, DQ5 =124, DQ6 =140, DQ7 =140
8216 09:59:51.236943 DQ8 =118, DQ9 =116, DQ10 =128, DQ11 =118
8217 09:59:51.240081 DQ12 =134, DQ13 =134, DQ14 =134, DQ15 =136
8218 09:59:51.240166
8219 09:59:51.240233
8220 09:59:51.240293
8221 09:59:51.243136 [DramC_TX_OE_Calibration] TA2
8222 09:59:51.246636 Original DQ_B0 (3 6) =30, OEN = 27
8223 09:59:51.249910 Original DQ_B1 (3 6) =30, OEN = 27
8224 09:59:51.253330 24, 0x0, End_B0=24 End_B1=24
8225 09:59:51.256865 25, 0x0, End_B0=25 End_B1=25
8226 09:59:51.256954 26, 0x0, End_B0=26 End_B1=26
8227 09:59:51.259911 27, 0x0, End_B0=27 End_B1=27
8228 09:59:51.263329 28, 0x0, End_B0=28 End_B1=28
8229 09:59:51.266492 29, 0x0, End_B0=29 End_B1=29
8230 09:59:51.266572 30, 0x0, End_B0=30 End_B1=30
8231 09:59:51.269893 31, 0x4141, End_B0=30 End_B1=30
8232 09:59:51.273214 Byte0 end_step=30 best_step=27
8233 09:59:51.276172 Byte1 end_step=30 best_step=27
8234 09:59:51.279565 Byte0 TX OE(2T, 0.5T) = (3, 3)
8235 09:59:51.283307 Byte1 TX OE(2T, 0.5T) = (3, 3)
8236 09:59:51.283395
8237 09:59:51.283467
8238 09:59:51.289789 [DQSOSCAuto] RK1, (LSB)MR18= 0x2109, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
8239 09:59:51.292790 CH0 RK1: MR19=303, MR18=2109
8240 09:59:51.299289 CH0_RK1: MR19=0x303, MR18=0x2109, DQSOSC=393, MR23=63, INC=23, DEC=15
8241 09:59:51.303221 [RxdqsGatingPostProcess] freq 1600
8242 09:59:51.309450 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8243 09:59:51.309534 best DQS0 dly(2T, 0.5T) = (1, 1)
8244 09:59:51.313253 best DQS1 dly(2T, 0.5T) = (1, 1)
8245 09:59:51.316142 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8246 09:59:51.319256 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8247 09:59:51.322472 best DQS0 dly(2T, 0.5T) = (1, 1)
8248 09:59:51.326213 best DQS1 dly(2T, 0.5T) = (1, 1)
8249 09:59:51.329258 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8250 09:59:51.332585 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8251 09:59:51.335939 Pre-setting of DQS Precalculation
8252 09:59:51.338981 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8253 09:59:51.339064 ==
8254 09:59:51.343151 Dram Type= 6, Freq= 0, CH_1, rank 0
8255 09:59:51.349189 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8256 09:59:51.349272 ==
8257 09:59:51.352935 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8258 09:59:51.359044 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8259 09:59:51.362550 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8260 09:59:51.369339 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8261 09:59:51.377049 [CA 0] Center 42 (12~72) winsize 61
8262 09:59:51.380007 [CA 1] Center 42 (12~72) winsize 61
8263 09:59:51.383259 [CA 2] Center 39 (10~68) winsize 59
8264 09:59:51.387087 [CA 3] Center 38 (9~67) winsize 59
8265 09:59:51.390316 [CA 4] Center 38 (9~68) winsize 60
8266 09:59:51.393549 [CA 5] Center 37 (8~67) winsize 60
8267 09:59:51.393714
8268 09:59:51.396699 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8269 09:59:51.396835
8270 09:59:51.400096 [CATrainingPosCal] consider 1 rank data
8271 09:59:51.403251 u2DelayCellTimex100 = 285/100 ps
8272 09:59:51.406698 CA0 delay=42 (12~72),Diff = 5 PI (17 cell)
8273 09:59:51.413546 CA1 delay=42 (12~72),Diff = 5 PI (17 cell)
8274 09:59:51.416922 CA2 delay=39 (10~68),Diff = 2 PI (6 cell)
8275 09:59:51.419836 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8276 09:59:51.423129 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8277 09:59:51.426352 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8278 09:59:51.426467
8279 09:59:51.430326 CA PerBit enable=1, Macro0, CA PI delay=37
8280 09:59:51.430438
8281 09:59:51.433252 [CBTSetCACLKResult] CA Dly = 37
8282 09:59:51.437032 CS Dly: 10 (0~41)
8283 09:59:51.439943 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8284 09:59:51.443417 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8285 09:59:51.443524 ==
8286 09:59:51.446413 Dram Type= 6, Freq= 0, CH_1, rank 1
8287 09:59:51.449702 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8288 09:59:51.453265 ==
8289 09:59:51.456869 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8290 09:59:51.460205 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8291 09:59:51.466527 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8292 09:59:51.470069 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8293 09:59:51.480143 [CA 0] Center 42 (13~72) winsize 60
8294 09:59:51.483293 [CA 1] Center 42 (13~72) winsize 60
8295 09:59:51.487189 [CA 2] Center 39 (10~69) winsize 60
8296 09:59:51.489982 [CA 3] Center 38 (9~68) winsize 60
8297 09:59:51.493180 [CA 4] Center 39 (10~69) winsize 60
8298 09:59:51.496629 [CA 5] Center 38 (8~68) winsize 61
8299 09:59:51.496741
8300 09:59:51.499958 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8301 09:59:51.500064
8302 09:59:51.503618 [CATrainingPosCal] consider 2 rank data
8303 09:59:51.506982 u2DelayCellTimex100 = 285/100 ps
8304 09:59:51.513549 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8305 09:59:51.516871 CA1 delay=42 (13~72),Diff = 5 PI (17 cell)
8306 09:59:51.520066 CA2 delay=39 (10~68),Diff = 2 PI (6 cell)
8307 09:59:51.523225 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8308 09:59:51.526425 CA4 delay=39 (10~68),Diff = 2 PI (6 cell)
8309 09:59:51.529865 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8310 09:59:51.529951
8311 09:59:51.533478 CA PerBit enable=1, Macro0, CA PI delay=37
8312 09:59:51.533560
8313 09:59:51.536707 [CBTSetCACLKResult] CA Dly = 37
8314 09:59:51.539982 CS Dly: 11 (0~44)
8315 09:59:51.543763 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8316 09:59:51.546615 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8317 09:59:51.546724
8318 09:59:51.549549 ----->DramcWriteLeveling(PI) begin...
8319 09:59:51.549670 ==
8320 09:59:51.553106 Dram Type= 6, Freq= 0, CH_1, rank 0
8321 09:59:51.559847 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8322 09:59:51.559971 ==
8323 09:59:51.563126 Write leveling (Byte 0): 26 => 26
8324 09:59:51.563238 Write leveling (Byte 1): 27 => 27
8325 09:59:51.566546 DramcWriteLeveling(PI) end<-----
8326 09:59:51.566666
8327 09:59:51.569636 ==
8328 09:59:51.569748 Dram Type= 6, Freq= 0, CH_1, rank 0
8329 09:59:51.577103 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8330 09:59:51.577228 ==
8331 09:59:51.580323 [Gating] SW mode calibration
8332 09:59:51.586623 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8333 09:59:51.589691 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8334 09:59:51.596219 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8335 09:59:51.599876 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8336 09:59:51.603077 1 4 8 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
8337 09:59:51.609814 1 4 12 | B1->B0 | 302f 3434 | 1 1 | (0 0) (1 1)
8338 09:59:51.613148 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8339 09:59:51.616378 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8340 09:59:51.622763 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8341 09:59:51.626469 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8342 09:59:51.629391 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8343 09:59:51.636273 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8344 09:59:51.639410 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 0) (1 0)
8345 09:59:51.642631 1 5 12 | B1->B0 | 2525 2323 | 0 0 | (1 0) (1 0)
8346 09:59:51.649852 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8347 09:59:51.652927 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8348 09:59:51.655961 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8349 09:59:51.659528 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8350 09:59:51.665889 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8351 09:59:51.669737 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8352 09:59:51.672890 1 6 8 | B1->B0 | 2525 3e3e | 0 0 | (0 0) (0 0)
8353 09:59:51.679368 1 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8354 09:59:51.682652 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8355 09:59:51.685922 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8356 09:59:51.692908 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8357 09:59:51.696016 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8358 09:59:51.699309 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8359 09:59:51.705906 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8360 09:59:51.709256 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8361 09:59:51.713006 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8362 09:59:51.719378 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8363 09:59:51.722892 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8364 09:59:51.725952 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8365 09:59:51.732357 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8366 09:59:51.735787 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8367 09:59:51.739279 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8368 09:59:51.746107 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8369 09:59:51.748870 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8370 09:59:51.752228 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8371 09:59:51.759134 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8372 09:59:51.762506 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8373 09:59:51.765821 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8374 09:59:51.772825 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8375 09:59:51.775802 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8376 09:59:51.779117 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8377 09:59:51.785429 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8378 09:59:51.789143 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8379 09:59:51.792254 Total UI for P1: 0, mck2ui 16
8380 09:59:51.795535 best dqsien dly found for B0: ( 1, 9, 10)
8381 09:59:51.798575 Total UI for P1: 0, mck2ui 16
8382 09:59:51.802473 best dqsien dly found for B1: ( 1, 9, 10)
8383 09:59:51.805479 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8384 09:59:51.808616 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8385 09:59:51.808723
8386 09:59:51.812032 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8387 09:59:51.815614 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8388 09:59:51.818802 [Gating] SW calibration Done
8389 09:59:51.818882 ==
8390 09:59:51.821927 Dram Type= 6, Freq= 0, CH_1, rank 0
8391 09:59:51.825144 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8392 09:59:51.828797 ==
8393 09:59:51.828877 RX Vref Scan: 0
8394 09:59:51.828952
8395 09:59:51.832226 RX Vref 0 -> 0, step: 1
8396 09:59:51.832311
8397 09:59:51.832376 RX Delay 0 -> 252, step: 8
8398 09:59:51.838889 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8399 09:59:51.842223 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8400 09:59:51.845544 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8401 09:59:51.848942 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8402 09:59:51.852152 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8403 09:59:51.858913 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8404 09:59:51.862212 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8405 09:59:51.865548 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8406 09:59:51.868596 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8407 09:59:51.871841 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8408 09:59:51.878375 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8409 09:59:51.882067 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8410 09:59:51.885220 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8411 09:59:51.888269 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8412 09:59:51.891408 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8413 09:59:51.898776 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8414 09:59:51.898860 ==
8415 09:59:51.901500 Dram Type= 6, Freq= 0, CH_1, rank 0
8416 09:59:51.905120 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8417 09:59:51.905201 ==
8418 09:59:51.905265 DQS Delay:
8419 09:59:51.908097 DQS0 = 0, DQS1 = 0
8420 09:59:51.908177 DQM Delay:
8421 09:59:51.911700 DQM0 = 136, DQM1 = 132
8422 09:59:51.911780 DQ Delay:
8423 09:59:51.914999 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8424 09:59:51.918114 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8425 09:59:51.922102 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8426 09:59:51.924968 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =139
8427 09:59:51.928081
8428 09:59:51.928164
8429 09:59:51.928227 ==
8430 09:59:51.931726 Dram Type= 6, Freq= 0, CH_1, rank 0
8431 09:59:51.935077 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8432 09:59:51.935196 ==
8433 09:59:51.935309
8434 09:59:51.935418
8435 09:59:51.938785 TX Vref Scan disable
8436 09:59:51.938877 == TX Byte 0 ==
8437 09:59:51.941949 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8438 09:59:51.948981 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8439 09:59:51.949146 == TX Byte 1 ==
8440 09:59:51.954842 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8441 09:59:51.958355 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8442 09:59:51.958459 ==
8443 09:59:51.961735 Dram Type= 6, Freq= 0, CH_1, rank 0
8444 09:59:51.965013 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8445 09:59:51.965112 ==
8446 09:59:51.977819
8447 09:59:51.981001 TX Vref early break, caculate TX vref
8448 09:59:51.984419 TX Vref=16, minBit 1, minWin=22, winSum=383
8449 09:59:51.987650 TX Vref=18, minBit 0, minWin=23, winSum=385
8450 09:59:51.991041 TX Vref=20, minBit 1, minWin=23, winSum=395
8451 09:59:51.994704 TX Vref=22, minBit 6, minWin=23, winSum=404
8452 09:59:51.997612 TX Vref=24, minBit 0, minWin=25, winSum=417
8453 09:59:52.004365 TX Vref=26, minBit 1, minWin=25, winSum=426
8454 09:59:52.007524 TX Vref=28, minBit 0, minWin=25, winSum=428
8455 09:59:52.011262 TX Vref=30, minBit 0, minWin=25, winSum=417
8456 09:59:52.014332 TX Vref=32, minBit 6, minWin=24, winSum=411
8457 09:59:52.017377 TX Vref=34, minBit 2, minWin=24, winSum=399
8458 09:59:52.024153 [TxChooseVref] Worse bit 0, Min win 25, Win sum 428, Final Vref 28
8459 09:59:52.024233
8460 09:59:52.027366 Final TX Range 0 Vref 28
8461 09:59:52.027464
8462 09:59:52.027528 ==
8463 09:59:52.030622 Dram Type= 6, Freq= 0, CH_1, rank 0
8464 09:59:52.034183 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8465 09:59:52.034274 ==
8466 09:59:52.034352
8467 09:59:52.034419
8468 09:59:52.037361 TX Vref Scan disable
8469 09:59:52.044388 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8470 09:59:52.044503 == TX Byte 0 ==
8471 09:59:52.047323 u2DelayCellOfst[0]=17 cells (5 PI)
8472 09:59:52.050571 u2DelayCellOfst[1]=10 cells (3 PI)
8473 09:59:52.054128 u2DelayCellOfst[2]=0 cells (0 PI)
8474 09:59:52.057793 u2DelayCellOfst[3]=6 cells (2 PI)
8475 09:59:52.060751 u2DelayCellOfst[4]=10 cells (3 PI)
8476 09:59:52.063916 u2DelayCellOfst[5]=17 cells (5 PI)
8477 09:59:52.067654 u2DelayCellOfst[6]=17 cells (5 PI)
8478 09:59:52.067758 u2DelayCellOfst[7]=6 cells (2 PI)
8479 09:59:52.074270 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8480 09:59:52.077176 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8481 09:59:52.077290 == TX Byte 1 ==
8482 09:59:52.080599 u2DelayCellOfst[8]=0 cells (0 PI)
8483 09:59:52.084302 u2DelayCellOfst[9]=3 cells (1 PI)
8484 09:59:52.087149 u2DelayCellOfst[10]=10 cells (3 PI)
8485 09:59:52.090627 u2DelayCellOfst[11]=6 cells (2 PI)
8486 09:59:52.093891 u2DelayCellOfst[12]=17 cells (5 PI)
8487 09:59:52.097067 u2DelayCellOfst[13]=17 cells (5 PI)
8488 09:59:52.100331 u2DelayCellOfst[14]=17 cells (5 PI)
8489 09:59:52.103413 u2DelayCellOfst[15]=17 cells (5 PI)
8490 09:59:52.107169 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8491 09:59:52.114087 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8492 09:59:52.114167 DramC Write-DBI on
8493 09:59:52.114233 ==
8494 09:59:52.116817 Dram Type= 6, Freq= 0, CH_1, rank 0
8495 09:59:52.120197 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8496 09:59:52.123296 ==
8497 09:59:52.123429
8498 09:59:52.123520
8499 09:59:52.123616 TX Vref Scan disable
8500 09:59:52.126737 == TX Byte 0 ==
8501 09:59:52.130246 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8502 09:59:52.133916 == TX Byte 1 ==
8503 09:59:52.136699 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8504 09:59:52.140514 DramC Write-DBI off
8505 09:59:52.140627
8506 09:59:52.140726 [DATLAT]
8507 09:59:52.140827 Freq=1600, CH1 RK0
8508 09:59:52.140916
8509 09:59:52.143586 DATLAT Default: 0xf
8510 09:59:52.143692 0, 0xFFFF, sum = 0
8511 09:59:52.147142 1, 0xFFFF, sum = 0
8512 09:59:52.147254 2, 0xFFFF, sum = 0
8513 09:59:52.150362 3, 0xFFFF, sum = 0
8514 09:59:52.153714 4, 0xFFFF, sum = 0
8515 09:59:52.153803 5, 0xFFFF, sum = 0
8516 09:59:52.156776 6, 0xFFFF, sum = 0
8517 09:59:52.156890 7, 0xFFFF, sum = 0
8518 09:59:52.160300 8, 0xFFFF, sum = 0
8519 09:59:52.160405 9, 0xFFFF, sum = 0
8520 09:59:52.163354 10, 0xFFFF, sum = 0
8521 09:59:52.163461 11, 0xFFFF, sum = 0
8522 09:59:52.167026 12, 0xFFFF, sum = 0
8523 09:59:52.167107 13, 0xFFFF, sum = 0
8524 09:59:52.170085 14, 0x0, sum = 1
8525 09:59:52.170162 15, 0x0, sum = 2
8526 09:59:52.173585 16, 0x0, sum = 3
8527 09:59:52.173665 17, 0x0, sum = 4
8528 09:59:52.177040 best_step = 15
8529 09:59:52.177158
8530 09:59:52.177252 ==
8531 09:59:52.180313 Dram Type= 6, Freq= 0, CH_1, rank 0
8532 09:59:52.183716 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8533 09:59:52.183829 ==
8534 09:59:52.183925 RX Vref Scan: 1
8535 09:59:52.186999
8536 09:59:52.187077 Set Vref Range= 24 -> 127
8537 09:59:52.187170
8538 09:59:52.190190 RX Vref 24 -> 127, step: 1
8539 09:59:52.190291
8540 09:59:52.193525 RX Delay 27 -> 252, step: 4
8541 09:59:52.193622
8542 09:59:52.196424 Set Vref, RX VrefLevel [Byte0]: 24
8543 09:59:52.199886 [Byte1]: 24
8544 09:59:52.199997
8545 09:59:52.203508 Set Vref, RX VrefLevel [Byte0]: 25
8546 09:59:52.206673 [Byte1]: 25
8547 09:59:52.206753
8548 09:59:52.210059 Set Vref, RX VrefLevel [Byte0]: 26
8549 09:59:52.213293 [Byte1]: 26
8550 09:59:52.217346
8551 09:59:52.217454 Set Vref, RX VrefLevel [Byte0]: 27
8552 09:59:52.220378 [Byte1]: 27
8553 09:59:52.224882
8554 09:59:52.224988 Set Vref, RX VrefLevel [Byte0]: 28
8555 09:59:52.228012 [Byte1]: 28
8556 09:59:52.232269
8557 09:59:52.232352 Set Vref, RX VrefLevel [Byte0]: 29
8558 09:59:52.235690 [Byte1]: 29
8559 09:59:52.239826
8560 09:59:52.239931 Set Vref, RX VrefLevel [Byte0]: 30
8561 09:59:52.243001 [Byte1]: 30
8562 09:59:52.247417
8563 09:59:52.247528 Set Vref, RX VrefLevel [Byte0]: 31
8564 09:59:52.250727 [Byte1]: 31
8565 09:59:52.254894
8566 09:59:52.255004 Set Vref, RX VrefLevel [Byte0]: 32
8567 09:59:52.258416 [Byte1]: 32
8568 09:59:52.262200
8569 09:59:52.262307 Set Vref, RX VrefLevel [Byte0]: 33
8570 09:59:52.266058 [Byte1]: 33
8571 09:59:52.270302
8572 09:59:52.270409 Set Vref, RX VrefLevel [Byte0]: 34
8573 09:59:52.273067 [Byte1]: 34
8574 09:59:52.277559
8575 09:59:52.277651 Set Vref, RX VrefLevel [Byte0]: 35
8576 09:59:52.281262 [Byte1]: 35
8577 09:59:52.285463
8578 09:59:52.285564 Set Vref, RX VrefLevel [Byte0]: 36
8579 09:59:52.288198 [Byte1]: 36
8580 09:59:52.292261
8581 09:59:52.292366 Set Vref, RX VrefLevel [Byte0]: 37
8582 09:59:52.295959 [Byte1]: 37
8583 09:59:52.300046
8584 09:59:52.300151 Set Vref, RX VrefLevel [Byte0]: 38
8585 09:59:52.303360 [Byte1]: 38
8586 09:59:52.307710
8587 09:59:52.307791 Set Vref, RX VrefLevel [Byte0]: 39
8588 09:59:52.310879 [Byte1]: 39
8589 09:59:52.315304
8590 09:59:52.315407 Set Vref, RX VrefLevel [Byte0]: 40
8591 09:59:52.318487 [Byte1]: 40
8592 09:59:52.322743
8593 09:59:52.322818 Set Vref, RX VrefLevel [Byte0]: 41
8594 09:59:52.325979 [Byte1]: 41
8595 09:59:52.329901
8596 09:59:52.329976 Set Vref, RX VrefLevel [Byte0]: 42
8597 09:59:52.333643 [Byte1]: 42
8598 09:59:52.337426
8599 09:59:52.337528 Set Vref, RX VrefLevel [Byte0]: 43
8600 09:59:52.340880 [Byte1]: 43
8601 09:59:52.345213
8602 09:59:52.345340 Set Vref, RX VrefLevel [Byte0]: 44
8603 09:59:52.348516 [Byte1]: 44
8604 09:59:52.353011
8605 09:59:52.353085 Set Vref, RX VrefLevel [Byte0]: 45
8606 09:59:52.356038 [Byte1]: 45
8607 09:59:52.360293
8608 09:59:52.360397 Set Vref, RX VrefLevel [Byte0]: 46
8609 09:59:52.363771 [Byte1]: 46
8610 09:59:52.367759
8611 09:59:52.367864 Set Vref, RX VrefLevel [Byte0]: 47
8612 09:59:52.370857 [Byte1]: 47
8613 09:59:52.375184
8614 09:59:52.375290 Set Vref, RX VrefLevel [Byte0]: 48
8615 09:59:52.378365 [Byte1]: 48
8616 09:59:52.383282
8617 09:59:52.383473 Set Vref, RX VrefLevel [Byte0]: 49
8618 09:59:52.386094 [Byte1]: 49
8619 09:59:52.390299
8620 09:59:52.390402 Set Vref, RX VrefLevel [Byte0]: 50
8621 09:59:52.393850 [Byte1]: 50
8622 09:59:52.398234
8623 09:59:52.398336 Set Vref, RX VrefLevel [Byte0]: 51
8624 09:59:52.401564 [Byte1]: 51
8625 09:59:52.405751
8626 09:59:52.405833 Set Vref, RX VrefLevel [Byte0]: 52
8627 09:59:52.408657 [Byte1]: 52
8628 09:59:52.412692
8629 09:59:52.412794 Set Vref, RX VrefLevel [Byte0]: 53
8630 09:59:52.416390 [Byte1]: 53
8631 09:59:52.420275
8632 09:59:52.420404 Set Vref, RX VrefLevel [Byte0]: 54
8633 09:59:52.424217 [Byte1]: 54
8634 09:59:52.427796
8635 09:59:52.427914 Set Vref, RX VrefLevel [Byte0]: 55
8636 09:59:52.431865 [Byte1]: 55
8637 09:59:52.435751
8638 09:59:52.435847 Set Vref, RX VrefLevel [Byte0]: 56
8639 09:59:52.438874 [Byte1]: 56
8640 09:59:52.442898
8641 09:59:52.443001 Set Vref, RX VrefLevel [Byte0]: 57
8642 09:59:52.446930 [Byte1]: 57
8643 09:59:52.450388
8644 09:59:52.450487 Set Vref, RX VrefLevel [Byte0]: 58
8645 09:59:52.453809 [Byte1]: 58
8646 09:59:52.457891
8647 09:59:52.457996 Set Vref, RX VrefLevel [Byte0]: 59
8648 09:59:52.461852 [Byte1]: 59
8649 09:59:52.465692
8650 09:59:52.465795 Set Vref, RX VrefLevel [Byte0]: 60
8651 09:59:52.468797 [Byte1]: 60
8652 09:59:52.473205
8653 09:59:52.473311 Set Vref, RX VrefLevel [Byte0]: 61
8654 09:59:52.476761 [Byte1]: 61
8655 09:59:52.480938
8656 09:59:52.481028 Set Vref, RX VrefLevel [Byte0]: 62
8657 09:59:52.484503 [Byte1]: 62
8658 09:59:52.488150
8659 09:59:52.488253 Set Vref, RX VrefLevel [Byte0]: 63
8660 09:59:52.491819 [Byte1]: 63
8661 09:59:52.496005
8662 09:59:52.496118 Set Vref, RX VrefLevel [Byte0]: 64
8663 09:59:52.499288 [Byte1]: 64
8664 09:59:52.503309
8665 09:59:52.503417 Set Vref, RX VrefLevel [Byte0]: 65
8666 09:59:52.507292 [Byte1]: 65
8667 09:59:52.510782
8668 09:59:52.510859 Set Vref, RX VrefLevel [Byte0]: 66
8669 09:59:52.514159 [Byte1]: 66
8670 09:59:52.518754
8671 09:59:52.518837 Set Vref, RX VrefLevel [Byte0]: 67
8672 09:59:52.521551 [Byte1]: 67
8673 09:59:52.525725
8674 09:59:52.525831 Set Vref, RX VrefLevel [Byte0]: 68
8675 09:59:52.529460 [Byte1]: 68
8676 09:59:52.533327
8677 09:59:52.533429 Set Vref, RX VrefLevel [Byte0]: 69
8678 09:59:52.536912 [Byte1]: 69
8679 09:59:52.541207
8680 09:59:52.541311 Set Vref, RX VrefLevel [Byte0]: 70
8681 09:59:52.544395 [Byte1]: 70
8682 09:59:52.548958
8683 09:59:52.549065 Set Vref, RX VrefLevel [Byte0]: 71
8684 09:59:52.551820 [Byte1]: 71
8685 09:59:52.556029
8686 09:59:52.556143 Set Vref, RX VrefLevel [Byte0]: 72
8687 09:59:52.559249 [Byte1]: 72
8688 09:59:52.563789
8689 09:59:52.563863 Set Vref, RX VrefLevel [Byte0]: 73
8690 09:59:52.567079 [Byte1]: 73
8691 09:59:52.571253
8692 09:59:52.571334 Set Vref, RX VrefLevel [Byte0]: 74
8693 09:59:52.574231 [Byte1]: 74
8694 09:59:52.578667
8695 09:59:52.578775 Set Vref, RX VrefLevel [Byte0]: 75
8696 09:59:52.581794 [Byte1]: 75
8697 09:59:52.586095
8698 09:59:52.586214 Set Vref, RX VrefLevel [Byte0]: 76
8699 09:59:52.589878 [Byte1]: 76
8700 09:59:52.593880
8701 09:59:52.593994 Set Vref, RX VrefLevel [Byte0]: 77
8702 09:59:52.596926 [Byte1]: 77
8703 09:59:52.601510
8704 09:59:52.601630 Final RX Vref Byte 0 = 57 to rank0
8705 09:59:52.604559 Final RX Vref Byte 1 = 54 to rank0
8706 09:59:52.607919 Final RX Vref Byte 0 = 57 to rank1
8707 09:59:52.611706 Final RX Vref Byte 1 = 54 to rank1==
8708 09:59:52.614677 Dram Type= 6, Freq= 0, CH_1, rank 0
8709 09:59:52.621375 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8710 09:59:52.621482 ==
8711 09:59:52.621602 DQS Delay:
8712 09:59:52.624795 DQS0 = 0, DQS1 = 0
8713 09:59:52.624899 DQM Delay:
8714 09:59:52.624991 DQM0 = 134, DQM1 = 130
8715 09:59:52.628089 DQ Delay:
8716 09:59:52.631402 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8717 09:59:52.634402 DQ4 =134, DQ5 =144, DQ6 =144, DQ7 =134
8718 09:59:52.637555 DQ8 =116, DQ9 =120, DQ10 =132, DQ11 =124
8719 09:59:52.640796 DQ12 =138, DQ13 =136, DQ14 =140, DQ15 =140
8720 09:59:52.640897
8721 09:59:52.640992
8722 09:59:52.641081
8723 09:59:52.644216 [DramC_TX_OE_Calibration] TA2
8724 09:59:52.647612 Original DQ_B0 (3 6) =30, OEN = 27
8725 09:59:52.651164 Original DQ_B1 (3 6) =30, OEN = 27
8726 09:59:52.653956 24, 0x0, End_B0=24 End_B1=24
8727 09:59:52.654041 25, 0x0, End_B0=25 End_B1=25
8728 09:59:52.657421 26, 0x0, End_B0=26 End_B1=26
8729 09:59:52.660876 27, 0x0, End_B0=27 End_B1=27
8730 09:59:52.663956 28, 0x0, End_B0=28 End_B1=28
8731 09:59:52.667474 29, 0x0, End_B0=29 End_B1=29
8732 09:59:52.667547 30, 0x0, End_B0=30 End_B1=30
8733 09:59:52.671216 31, 0x4141, End_B0=30 End_B1=30
8734 09:59:52.674332 Byte0 end_step=30 best_step=27
8735 09:59:52.677951 Byte1 end_step=30 best_step=27
8736 09:59:52.681125 Byte0 TX OE(2T, 0.5T) = (3, 3)
8737 09:59:52.684194 Byte1 TX OE(2T, 0.5T) = (3, 3)
8738 09:59:52.684271
8739 09:59:52.684340
8740 09:59:52.691049 [DQSOSCAuto] RK0, (LSB)MR18= 0x1826, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
8741 09:59:52.694243 CH1 RK0: MR19=303, MR18=1826
8742 09:59:52.701104 CH1_RK0: MR19=0x303, MR18=0x1826, DQSOSC=390, MR23=63, INC=24, DEC=16
8743 09:59:52.701222
8744 09:59:52.704315 ----->DramcWriteLeveling(PI) begin...
8745 09:59:52.704434 ==
8746 09:59:52.707662 Dram Type= 6, Freq= 0, CH_1, rank 1
8747 09:59:52.710670 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8748 09:59:52.710745 ==
8749 09:59:52.714127 Write leveling (Byte 0): 25 => 25
8750 09:59:52.717542 Write leveling (Byte 1): 29 => 29
8751 09:59:52.720799 DramcWriteLeveling(PI) end<-----
8752 09:59:52.720870
8753 09:59:52.720935 ==
8754 09:59:52.724123 Dram Type= 6, Freq= 0, CH_1, rank 1
8755 09:59:52.727273 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8756 09:59:52.727352 ==
8757 09:59:52.730498 [Gating] SW mode calibration
8758 09:59:52.737151 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8759 09:59:52.743814 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8760 09:59:52.747743 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8761 09:59:52.753919 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8762 09:59:52.757270 1 4 8 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
8763 09:59:52.761118 1 4 12 | B1->B0 | 3333 2e2d | 1 1 | (1 1) (0 0)
8764 09:59:52.767318 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8765 09:59:52.770119 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8766 09:59:52.773722 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8767 09:59:52.776816 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8768 09:59:52.784177 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8769 09:59:52.786959 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8770 09:59:52.790288 1 5 8 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 1)
8771 09:59:52.796987 1 5 12 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 0)
8772 09:59:52.800244 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
8773 09:59:52.803461 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8774 09:59:52.810529 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8775 09:59:52.813875 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8776 09:59:52.816937 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8777 09:59:52.823827 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8778 09:59:52.826866 1 6 8 | B1->B0 | 2b2b 2323 | 1 0 | (0 0) (0 0)
8779 09:59:52.830035 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8780 09:59:52.836985 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8781 09:59:52.840131 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8782 09:59:52.843240 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8783 09:59:52.850081 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8784 09:59:52.853308 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8785 09:59:52.856736 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8786 09:59:52.863125 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8787 09:59:52.866847 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8788 09:59:52.870016 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8789 09:59:52.876500 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8790 09:59:52.879906 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8791 09:59:52.883363 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8792 09:59:52.889679 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8793 09:59:52.893259 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8794 09:59:52.896401 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8795 09:59:52.903182 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8796 09:59:52.906468 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8797 09:59:52.909955 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8798 09:59:52.916136 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8799 09:59:52.919798 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8800 09:59:52.923390 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8801 09:59:52.926300 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8802 09:59:52.933236 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8803 09:59:52.936923 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8804 09:59:52.940076 Total UI for P1: 0, mck2ui 16
8805 09:59:52.943181 best dqsien dly found for B1: ( 1, 9, 6)
8806 09:59:52.946305 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8807 09:59:52.952903 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8808 09:59:52.953008 Total UI for P1: 0, mck2ui 16
8809 09:59:52.959699 best dqsien dly found for B0: ( 1, 9, 14)
8810 09:59:52.962808 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8811 09:59:52.966424 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8812 09:59:52.966507
8813 09:59:52.969792 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8814 09:59:52.973130 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8815 09:59:52.976298 [Gating] SW calibration Done
8816 09:59:52.976405 ==
8817 09:59:52.979983 Dram Type= 6, Freq= 0, CH_1, rank 1
8818 09:59:52.983005 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8819 09:59:52.983108 ==
8820 09:59:52.986583 RX Vref Scan: 0
8821 09:59:52.986682
8822 09:59:52.986773 RX Vref 0 -> 0, step: 1
8823 09:59:52.986864
8824 09:59:52.989858 RX Delay 0 -> 252, step: 8
8825 09:59:52.993022 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8826 09:59:52.999481 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8827 09:59:53.003232 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8828 09:59:53.006485 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8829 09:59:53.009522 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8830 09:59:53.013481 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8831 09:59:53.019709 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8832 09:59:53.022916 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8833 09:59:53.026879 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8834 09:59:53.029846 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8835 09:59:53.032792 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8836 09:59:53.039457 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8837 09:59:53.043083 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8838 09:59:53.046264 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8839 09:59:53.049312 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8840 09:59:53.052822 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8841 09:59:53.055969 ==
8842 09:59:53.059041 Dram Type= 6, Freq= 0, CH_1, rank 1
8843 09:59:53.062518 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8844 09:59:53.062625 ==
8845 09:59:53.062722 DQS Delay:
8846 09:59:53.066342 DQS0 = 0, DQS1 = 0
8847 09:59:53.066448 DQM Delay:
8848 09:59:53.069078 DQM0 = 136, DQM1 = 133
8849 09:59:53.069177 DQ Delay:
8850 09:59:53.072768 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8851 09:59:53.075961 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8852 09:59:53.079509 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8853 09:59:53.082762 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8854 09:59:53.082843
8855 09:59:53.082908
8856 09:59:53.082973 ==
8857 09:59:53.085887 Dram Type= 6, Freq= 0, CH_1, rank 1
8858 09:59:53.092506 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8859 09:59:53.092611 ==
8860 09:59:53.092691
8861 09:59:53.092792
8862 09:59:53.092890 TX Vref Scan disable
8863 09:59:53.096438 == TX Byte 0 ==
8864 09:59:53.099554 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8865 09:59:53.106419 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8866 09:59:53.106512 == TX Byte 1 ==
8867 09:59:53.109450 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8868 09:59:53.116309 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8869 09:59:53.116411 ==
8870 09:59:53.119477 Dram Type= 6, Freq= 0, CH_1, rank 1
8871 09:59:53.122670 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8872 09:59:53.122775 ==
8873 09:59:53.136791
8874 09:59:53.139570 TX Vref early break, caculate TX vref
8875 09:59:53.142932 TX Vref=16, minBit 1, minWin=22, winSum=383
8876 09:59:53.146076 TX Vref=18, minBit 0, minWin=23, winSum=394
8877 09:59:53.149723 TX Vref=20, minBit 0, minWin=24, winSum=395
8878 09:59:53.152740 TX Vref=22, minBit 0, minWin=24, winSum=409
8879 09:59:53.156275 TX Vref=24, minBit 0, minWin=25, winSum=417
8880 09:59:53.163030 TX Vref=26, minBit 0, minWin=26, winSum=426
8881 09:59:53.165933 TX Vref=28, minBit 0, minWin=26, winSum=427
8882 09:59:53.169521 TX Vref=30, minBit 0, minWin=25, winSum=421
8883 09:59:53.173049 TX Vref=32, minBit 1, minWin=24, winSum=415
8884 09:59:53.176216 TX Vref=34, minBit 0, minWin=25, winSum=405
8885 09:59:53.179334 TX Vref=36, minBit 6, minWin=23, winSum=397
8886 09:59:53.186240 [TxChooseVref] Worse bit 0, Min win 26, Win sum 427, Final Vref 28
8887 09:59:53.186379
8888 09:59:53.189343 Final TX Range 0 Vref 28
8889 09:59:53.189451
8890 09:59:53.189543 ==
8891 09:59:53.192892 Dram Type= 6, Freq= 0, CH_1, rank 1
8892 09:59:53.196018 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8893 09:59:53.196140 ==
8894 09:59:53.196292
8895 09:59:53.196411
8896 09:59:53.199446 TX Vref Scan disable
8897 09:59:53.205920 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8898 09:59:53.206019 == TX Byte 0 ==
8899 09:59:53.209148 u2DelayCellOfst[0]=17 cells (5 PI)
8900 09:59:53.212600 u2DelayCellOfst[1]=13 cells (4 PI)
8901 09:59:53.216149 u2DelayCellOfst[2]=0 cells (0 PI)
8902 09:59:53.219520 u2DelayCellOfst[3]=6 cells (2 PI)
8903 09:59:53.222719 u2DelayCellOfst[4]=6 cells (2 PI)
8904 09:59:53.225901 u2DelayCellOfst[5]=20 cells (6 PI)
8905 09:59:53.229199 u2DelayCellOfst[6]=20 cells (6 PI)
8906 09:59:53.232908 u2DelayCellOfst[7]=6 cells (2 PI)
8907 09:59:53.235618 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8908 09:59:53.239350 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8909 09:59:53.242524 == TX Byte 1 ==
8910 09:59:53.246022 u2DelayCellOfst[8]=0 cells (0 PI)
8911 09:59:53.246103 u2DelayCellOfst[9]=3 cells (1 PI)
8912 09:59:53.249062 u2DelayCellOfst[10]=13 cells (4 PI)
8913 09:59:53.252334 u2DelayCellOfst[11]=6 cells (2 PI)
8914 09:59:53.255648 u2DelayCellOfst[12]=17 cells (5 PI)
8915 09:59:53.259103 u2DelayCellOfst[13]=13 cells (4 PI)
8916 09:59:53.262462 u2DelayCellOfst[14]=17 cells (5 PI)
8917 09:59:53.265488 u2DelayCellOfst[15]=17 cells (5 PI)
8918 09:59:53.269162 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8919 09:59:53.275384 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8920 09:59:53.275495 DramC Write-DBI on
8921 09:59:53.275588 ==
8922 09:59:53.278717 Dram Type= 6, Freq= 0, CH_1, rank 1
8923 09:59:53.285584 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8924 09:59:53.285668 ==
8925 09:59:53.285740
8926 09:59:53.285834
8927 09:59:53.285927 TX Vref Scan disable
8928 09:59:53.289210 == TX Byte 0 ==
8929 09:59:53.292604 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8930 09:59:53.296478 == TX Byte 1 ==
8931 09:59:53.299689 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8932 09:59:53.299776 DramC Write-DBI off
8933 09:59:53.302768
8934 09:59:53.302853 [DATLAT]
8935 09:59:53.302918 Freq=1600, CH1 RK1
8936 09:59:53.302979
8937 09:59:53.306356 DATLAT Default: 0xf
8938 09:59:53.306442 0, 0xFFFF, sum = 0
8939 09:59:53.309778 1, 0xFFFF, sum = 0
8940 09:59:53.309865 2, 0xFFFF, sum = 0
8941 09:59:53.312842 3, 0xFFFF, sum = 0
8942 09:59:53.312927 4, 0xFFFF, sum = 0
8943 09:59:53.316698 5, 0xFFFF, sum = 0
8944 09:59:53.316799 6, 0xFFFF, sum = 0
8945 09:59:53.319866 7, 0xFFFF, sum = 0
8946 09:59:53.322720 8, 0xFFFF, sum = 0
8947 09:59:53.322815 9, 0xFFFF, sum = 0
8948 09:59:53.326355 10, 0xFFFF, sum = 0
8949 09:59:53.326449 11, 0xFFFF, sum = 0
8950 09:59:53.329369 12, 0xFFFF, sum = 0
8951 09:59:53.329456 13, 0xFFFF, sum = 0
8952 09:59:53.333192 14, 0x0, sum = 1
8953 09:59:53.333297 15, 0x0, sum = 2
8954 09:59:53.336569 16, 0x0, sum = 3
8955 09:59:53.336669 17, 0x0, sum = 4
8956 09:59:53.339555 best_step = 15
8957 09:59:53.339637
8958 09:59:53.339701 ==
8959 09:59:53.342819 Dram Type= 6, Freq= 0, CH_1, rank 1
8960 09:59:53.345966 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8961 09:59:53.346066 ==
8962 09:59:53.346139 RX Vref Scan: 0
8963 09:59:53.346220
8964 09:59:53.349764 RX Vref 0 -> 0, step: 1
8965 09:59:53.349847
8966 09:59:53.353261 RX Delay 19 -> 252, step: 4
8967 09:59:53.356080 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8968 09:59:53.362524 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
8969 09:59:53.366228 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8970 09:59:53.369197 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8971 09:59:53.372951 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8972 09:59:53.375900 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8973 09:59:53.379351 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8974 09:59:53.386215 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
8975 09:59:53.389264 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8976 09:59:53.392418 iDelay=195, Bit 9, Center 120 (67 ~ 174) 108
8977 09:59:53.396279 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
8978 09:59:53.399294 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8979 09:59:53.406091 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
8980 09:59:53.409259 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8981 09:59:53.412678 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8982 09:59:53.416152 iDelay=195, Bit 15, Center 140 (87 ~ 194) 108
8983 09:59:53.416235 ==
8984 09:59:53.419758 Dram Type= 6, Freq= 0, CH_1, rank 1
8985 09:59:53.426065 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8986 09:59:53.426162 ==
8987 09:59:53.426232 DQS Delay:
8988 09:59:53.426293 DQS0 = 0, DQS1 = 0
8989 09:59:53.429184 DQM Delay:
8990 09:59:53.429282 DQM0 = 134, DQM1 = 130
8991 09:59:53.433029 DQ Delay:
8992 09:59:53.435861 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =130
8993 09:59:53.439166 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
8994 09:59:53.442916 DQ8 =116, DQ9 =120, DQ10 =132, DQ11 =124
8995 09:59:53.446168 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =140
8996 09:59:53.446290
8997 09:59:53.446388
8998 09:59:53.446502
8999 09:59:53.449488 [DramC_TX_OE_Calibration] TA2
9000 09:59:53.452403 Original DQ_B0 (3 6) =30, OEN = 27
9001 09:59:53.456203 Original DQ_B1 (3 6) =30, OEN = 27
9002 09:59:53.459573 24, 0x0, End_B0=24 End_B1=24
9003 09:59:53.459668 25, 0x0, End_B0=25 End_B1=25
9004 09:59:53.462792 26, 0x0, End_B0=26 End_B1=26
9005 09:59:53.465726 27, 0x0, End_B0=27 End_B1=27
9006 09:59:53.469465 28, 0x0, End_B0=28 End_B1=28
9007 09:59:53.472636 29, 0x0, End_B0=29 End_B1=29
9008 09:59:53.472722 30, 0x0, End_B0=30 End_B1=30
9009 09:59:53.475598 31, 0x4141, End_B0=30 End_B1=30
9010 09:59:53.479249 Byte0 end_step=30 best_step=27
9011 09:59:53.482264 Byte1 end_step=30 best_step=27
9012 09:59:53.486100 Byte0 TX OE(2T, 0.5T) = (3, 3)
9013 09:59:53.488816 Byte1 TX OE(2T, 0.5T) = (3, 3)
9014 09:59:53.488915
9015 09:59:53.488983
9016 09:59:53.495689 [DQSOSCAuto] RK1, (LSB)MR18= 0x2106, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 393 ps
9017 09:59:53.498887 CH1 RK1: MR19=303, MR18=2106
9018 09:59:53.505528 CH1_RK1: MR19=0x303, MR18=0x2106, DQSOSC=393, MR23=63, INC=23, DEC=15
9019 09:59:53.509141 [RxdqsGatingPostProcess] freq 1600
9020 09:59:53.512480 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9021 09:59:53.515841 best DQS0 dly(2T, 0.5T) = (1, 1)
9022 09:59:53.518831 best DQS1 dly(2T, 0.5T) = (1, 1)
9023 09:59:53.522414 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9024 09:59:53.525880 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9025 09:59:53.528928 best DQS0 dly(2T, 0.5T) = (1, 1)
9026 09:59:53.532024 best DQS1 dly(2T, 0.5T) = (1, 1)
9027 09:59:53.535361 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9028 09:59:53.538642 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9029 09:59:53.542510 Pre-setting of DQS Precalculation
9030 09:59:53.545813 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9031 09:59:53.552462 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9032 09:59:53.558676 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9033 09:59:53.558792
9034 09:59:53.562497
9035 09:59:53.562608 [Calibration Summary] 3200 Mbps
9036 09:59:53.565294 CH 0, Rank 0
9037 09:59:53.565407 SW Impedance : PASS
9038 09:59:53.568959 DUTY Scan : NO K
9039 09:59:53.571998 ZQ Calibration : PASS
9040 09:59:53.572090 Jitter Meter : NO K
9041 09:59:53.575765 CBT Training : PASS
9042 09:59:53.578886 Write leveling : PASS
9043 09:59:53.578980 RX DQS gating : PASS
9044 09:59:53.582057 RX DQ/DQS(RDDQC) : PASS
9045 09:59:53.585164 TX DQ/DQS : PASS
9046 09:59:53.585259 RX DATLAT : PASS
9047 09:59:53.588768 RX DQ/DQS(Engine): PASS
9048 09:59:53.591933 TX OE : PASS
9049 09:59:53.592028 All Pass.
9050 09:59:53.592097
9051 09:59:53.592159 CH 0, Rank 1
9052 09:59:53.595145 SW Impedance : PASS
9053 09:59:53.598985 DUTY Scan : NO K
9054 09:59:53.599086 ZQ Calibration : PASS
9055 09:59:53.602049 Jitter Meter : NO K
9056 09:59:53.602137 CBT Training : PASS
9057 09:59:53.605194 Write leveling : PASS
9058 09:59:53.608439 RX DQS gating : PASS
9059 09:59:53.608527 RX DQ/DQS(RDDQC) : PASS
9060 09:59:53.611841 TX DQ/DQS : PASS
9061 09:59:53.615778 RX DATLAT : PASS
9062 09:59:53.615873 RX DQ/DQS(Engine): PASS
9063 09:59:53.618539 TX OE : PASS
9064 09:59:53.618629 All Pass.
9065 09:59:53.618699
9066 09:59:53.622021 CH 1, Rank 0
9067 09:59:53.622125 SW Impedance : PASS
9068 09:59:53.625083 DUTY Scan : NO K
9069 09:59:53.628750 ZQ Calibration : PASS
9070 09:59:53.628844 Jitter Meter : NO K
9071 09:59:53.632294 CBT Training : PASS
9072 09:59:53.634988 Write leveling : PASS
9073 09:59:53.635084 RX DQS gating : PASS
9074 09:59:53.638296 RX DQ/DQS(RDDQC) : PASS
9075 09:59:53.641820 TX DQ/DQS : PASS
9076 09:59:53.641916 RX DATLAT : PASS
9077 09:59:53.644973 RX DQ/DQS(Engine): PASS
9078 09:59:53.648160 TX OE : PASS
9079 09:59:53.648252 All Pass.
9080 09:59:53.648323
9081 09:59:53.648391 CH 1, Rank 1
9082 09:59:53.651787 SW Impedance : PASS
9083 09:59:53.655055 DUTY Scan : NO K
9084 09:59:53.655143 ZQ Calibration : PASS
9085 09:59:53.658310 Jitter Meter : NO K
9086 09:59:53.658407 CBT Training : PASS
9087 09:59:53.662035 Write leveling : PASS
9088 09:59:53.665573 RX DQS gating : PASS
9089 09:59:53.665696 RX DQ/DQS(RDDQC) : PASS
9090 09:59:53.668472 TX DQ/DQS : PASS
9091 09:59:53.671679 RX DATLAT : PASS
9092 09:59:53.671774 RX DQ/DQS(Engine): PASS
9093 09:59:53.674810 TX OE : PASS
9094 09:59:53.674889 All Pass.
9095 09:59:53.674952
9096 09:59:53.678476 DramC Write-DBI on
9097 09:59:53.681897 PER_BANK_REFRESH: Hybrid Mode
9098 09:59:53.682000 TX_TRACKING: ON
9099 09:59:53.691410 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9100 09:59:53.698109 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9101 09:59:53.704824 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9102 09:59:53.708531 [FAST_K] Save calibration result to emmc
9103 09:59:53.711970 sync common calibartion params.
9104 09:59:53.714968 sync cbt_mode0:1, 1:1
9105 09:59:53.718092 dram_init: ddr_geometry: 2
9106 09:59:53.718193 dram_init: ddr_geometry: 2
9107 09:59:53.722283 dram_init: ddr_geometry: 2
9108 09:59:53.725062 0:dram_rank_size:100000000
9109 09:59:53.728522 1:dram_rank_size:100000000
9110 09:59:53.731551 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9111 09:59:53.734919 DFS_SHUFFLE_HW_MODE: ON
9112 09:59:53.738267 dramc_set_vcore_voltage set vcore to 725000
9113 09:59:53.741592 Read voltage for 1600, 0
9114 09:59:53.741714 Vio18 = 0
9115 09:59:53.741783 Vcore = 725000
9116 09:59:53.745398 Vdram = 0
9117 09:59:53.745494 Vddq = 0
9118 09:59:53.745561 Vmddr = 0
9119 09:59:53.748224 switch to 3200 Mbps bootup
9120 09:59:53.751683 [DramcRunTimeConfig]
9121 09:59:53.751780 PHYPLL
9122 09:59:53.751854 DPM_CONTROL_AFTERK: ON
9123 09:59:53.755145 PER_BANK_REFRESH: ON
9124 09:59:53.758371 REFRESH_OVERHEAD_REDUCTION: ON
9125 09:59:53.758487 CMD_PICG_NEW_MODE: OFF
9126 09:59:53.761788 XRTWTW_NEW_MODE: ON
9127 09:59:53.761875 XRTRTR_NEW_MODE: ON
9128 09:59:53.764952 TX_TRACKING: ON
9129 09:59:53.765032 RDSEL_TRACKING: OFF
9130 09:59:53.768060 DQS Precalculation for DVFS: ON
9131 09:59:53.771735 RX_TRACKING: OFF
9132 09:59:53.771856 HW_GATING DBG: ON
9133 09:59:53.775341 ZQCS_ENABLE_LP4: ON
9134 09:59:53.775460 RX_PICG_NEW_MODE: ON
9135 09:59:53.778327 TX_PICG_NEW_MODE: ON
9136 09:59:53.781233 ENABLE_RX_DCM_DPHY: ON
9137 09:59:53.781326 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9138 09:59:53.785009 DUMMY_READ_FOR_TRACKING: OFF
9139 09:59:53.788092 !!! SPM_CONTROL_AFTERK: OFF
9140 09:59:53.791180 !!! SPM could not control APHY
9141 09:59:53.791304 IMPEDANCE_TRACKING: ON
9142 09:59:53.795061 TEMP_SENSOR: ON
9143 09:59:53.795181 HW_SAVE_FOR_SR: OFF
9144 09:59:53.798221 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9145 09:59:53.801444 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9146 09:59:53.804519 Read ODT Tracking: ON
9147 09:59:53.808093 Refresh Rate DeBounce: ON
9148 09:59:53.808219 DFS_NO_QUEUE_FLUSH: ON
9149 09:59:53.811175 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9150 09:59:53.814591 ENABLE_DFS_RUNTIME_MRW: OFF
9151 09:59:53.818076 DDR_RESERVE_NEW_MODE: ON
9152 09:59:53.818193 MR_CBT_SWITCH_FREQ: ON
9153 09:59:53.821062 =========================
9154 09:59:53.840780 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9155 09:59:53.843707 dram_init: ddr_geometry: 2
9156 09:59:53.862281 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9157 09:59:53.865593 dram_init: dram init end (result: 0)
9158 09:59:53.872431 DRAM-K: Full calibration passed in 24461 msecs
9159 09:59:53.875427 MRC: failed to locate region type 0.
9160 09:59:53.875558 DRAM rank0 size:0x100000000,
9161 09:59:53.878622 DRAM rank1 size=0x100000000
9162 09:59:53.888452 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9163 09:59:53.895624 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9164 09:59:53.901801 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9165 09:59:53.908474 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9166 09:59:53.912220 DRAM rank0 size:0x100000000,
9167 09:59:53.915575 DRAM rank1 size=0x100000000
9168 09:59:53.915666 CBMEM:
9169 09:59:53.918759 IMD: root @ 0xfffff000 254 entries.
9170 09:59:53.921884 IMD: root @ 0xffffec00 62 entries.
9171 09:59:53.925247 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9172 09:59:53.928612 WARNING: RO_VPD is uninitialized or empty.
9173 09:59:53.934866 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9174 09:59:53.942262 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9175 09:59:53.955125 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9176 09:59:53.966222 BS: romstage times (exec / console): total (unknown) / 23993 ms
9177 09:59:53.966368
9178 09:59:53.966458
9179 09:59:53.976514 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9180 09:59:53.979435 ARM64: Exception handlers installed.
9181 09:59:53.982911 ARM64: Testing exception
9182 09:59:53.986209 ARM64: Done test exception
9183 09:59:53.986308 Enumerating buses...
9184 09:59:53.989797 Show all devs... Before device enumeration.
9185 09:59:53.992934 Root Device: enabled 1
9186 09:59:53.996362 CPU_CLUSTER: 0: enabled 1
9187 09:59:53.996454 CPU: 00: enabled 1
9188 09:59:53.999852 Compare with tree...
9189 09:59:53.999945 Root Device: enabled 1
9190 09:59:54.003050 CPU_CLUSTER: 0: enabled 1
9191 09:59:54.006317 CPU: 00: enabled 1
9192 09:59:54.006402 Root Device scanning...
9193 09:59:54.010030 scan_static_bus for Root Device
9194 09:59:54.013164 CPU_CLUSTER: 0 enabled
9195 09:59:54.016375 scan_static_bus for Root Device done
9196 09:59:54.019545 scan_bus: bus Root Device finished in 8 msecs
9197 09:59:54.019628 done
9198 09:59:54.026096 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9199 09:59:54.029568 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9200 09:59:54.036193 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9201 09:59:54.039352 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9202 09:59:54.042639 Allocating resources...
9203 09:59:54.046340 Reading resources...
9204 09:59:54.049411 Root Device read_resources bus 0 link: 0
9205 09:59:54.049497 DRAM rank0 size:0x100000000,
9206 09:59:54.052481 DRAM rank1 size=0x100000000
9207 09:59:54.056139 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9208 09:59:54.059663 CPU: 00 missing read_resources
9209 09:59:54.062806 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9210 09:59:54.069573 Root Device read_resources bus 0 link: 0 done
9211 09:59:54.069707 Done reading resources.
9212 09:59:54.075924 Show resources in subtree (Root Device)...After reading.
9213 09:59:54.079824 Root Device child on link 0 CPU_CLUSTER: 0
9214 09:59:54.082693 CPU_CLUSTER: 0 child on link 0 CPU: 00
9215 09:59:54.092872 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9216 09:59:54.092973 CPU: 00
9217 09:59:54.095945 Root Device assign_resources, bus 0 link: 0
9218 09:59:54.099384 CPU_CLUSTER: 0 missing set_resources
9219 09:59:54.102989 Root Device assign_resources, bus 0 link: 0 done
9220 09:59:54.106094 Done setting resources.
9221 09:59:54.112802 Show resources in subtree (Root Device)...After assigning values.
9222 09:59:54.116044 Root Device child on link 0 CPU_CLUSTER: 0
9223 09:59:54.119035 CPU_CLUSTER: 0 child on link 0 CPU: 00
9224 09:59:54.129236 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9225 09:59:54.129338 CPU: 00
9226 09:59:54.132423 Done allocating resources.
9227 09:59:54.135625 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9228 09:59:54.138877 Enabling resources...
9229 09:59:54.138958 done.
9230 09:59:54.146351 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9231 09:59:54.146481 Initializing devices...
9232 09:59:54.149222 Root Device init
9233 09:59:54.149301 init hardware done!
9234 09:59:54.152602 0x00000018: ctrlr->caps
9235 09:59:54.156390 52.000 MHz: ctrlr->f_max
9236 09:59:54.156489 0.400 MHz: ctrlr->f_min
9237 09:59:54.159345 0x40ff8080: ctrlr->voltages
9238 09:59:54.159462 sclk: 390625
9239 09:59:54.162903 Bus Width = 1
9240 09:59:54.163014 sclk: 390625
9241 09:59:54.163107 Bus Width = 1
9242 09:59:54.165862 Early init status = 3
9243 09:59:54.172716 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9244 09:59:54.175779 in-header: 03 fb 00 00 01 00 00 00
9245 09:59:54.175872 in-data: 01
9246 09:59:54.182255 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9247 09:59:54.185543 in-header: 03 fb 00 00 01 00 00 00
9248 09:59:54.185652 in-data: 01
9249 09:59:54.188739 [SSUSB] Setting up USB HOST controller...
9250 09:59:54.195537 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9251 09:59:54.195665 [SSUSB] phy power-on done.
9252 09:59:54.202665 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9253 09:59:54.205678 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9254 09:59:54.212659 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9255 09:59:54.219324 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9256 09:59:54.222769 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9257 09:59:54.229677 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9258 09:59:54.236590 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9259 09:59:54.243565 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9260 09:59:54.246811 SPM: binary array size = 0x9dc
9261 09:59:54.253701 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9262 09:59:54.256646 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9263 09:59:54.263544 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9264 09:59:54.270127 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9265 09:59:54.273137 configure_display: Starting display init
9266 09:59:54.307627 anx7625_power_on_init: Init interface.
9267 09:59:54.311136 anx7625_disable_pd_protocol: Disabled PD feature.
9268 09:59:54.314318 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9269 09:59:54.341857 anx7625_start_dp_work: Secure OCM version=00
9270 09:59:54.345793 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9271 09:59:54.360426 sp_tx_get_edid_block: EDID Block = 1
9272 09:59:54.462640 Extracted contents:
9273 09:59:54.466257 header: 00 ff ff ff ff ff ff 00
9274 09:59:54.469424 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9275 09:59:54.473593 version: 01 04
9276 09:59:54.476315 basic params: 95 1f 11 78 0a
9277 09:59:54.479654 chroma info: 76 90 94 55 54 90 27 21 50 54
9278 09:59:54.482800 established: 00 00 00
9279 09:59:54.486116 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9280 09:59:54.492978 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9281 09:59:54.499411 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9282 09:59:54.506234 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9283 09:59:54.512750 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9284 09:59:54.516095 extensions: 00
9285 09:59:54.516197 checksum: fb
9286 09:59:54.516312
9287 09:59:54.519377 Manufacturer: IVO Model 57d Serial Number 0
9288 09:59:54.522369 Made week 0 of 2020
9289 09:59:54.522462 EDID version: 1.4
9290 09:59:54.526499 Digital display
9291 09:59:54.529407 6 bits per primary color channel
9292 09:59:54.529523 DisplayPort interface
9293 09:59:54.532408 Maximum image size: 31 cm x 17 cm
9294 09:59:54.536256 Gamma: 220%
9295 09:59:54.536359 Check DPMS levels
9296 09:59:54.539129 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9297 09:59:54.542381 First detailed timing is preferred timing
9298 09:59:54.545858 Established timings supported:
9299 09:59:54.549331 Standard timings supported:
9300 09:59:54.549444 Detailed timings
9301 09:59:54.556093 Hex of detail: 383680a07038204018303c0035ae10000019
9302 09:59:54.559304 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9303 09:59:54.565504 0780 0798 07c8 0820 hborder 0
9304 09:59:54.568773 0438 043b 0447 0458 vborder 0
9305 09:59:54.572415 -hsync -vsync
9306 09:59:54.572506 Did detailed timing
9307 09:59:54.579052 Hex of detail: 000000000000000000000000000000000000
9308 09:59:54.579167 Manufacturer-specified data, tag 0
9309 09:59:54.585768 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9310 09:59:54.588805 ASCII string: InfoVision
9311 09:59:54.592126 Hex of detail: 000000fe00523134304e574635205248200a
9312 09:59:54.595472 ASCII string: R140NWF5 RH
9313 09:59:54.595563 Checksum
9314 09:59:54.595637 Checksum: 0xfb (valid)
9315 09:59:54.602220 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9316 09:59:54.605812 DSI data_rate: 832800000 bps
9317 09:59:54.609019 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9318 09:59:54.615614 anx7625_parse_edid: pixelclock(138800).
9319 09:59:54.618873 hactive(1920), hsync(48), hfp(24), hbp(88)
9320 09:59:54.622105 vactive(1080), vsync(12), vfp(3), vbp(17)
9321 09:59:54.625437 anx7625_dsi_config: config dsi.
9322 09:59:54.632662 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9323 09:59:54.644828 anx7625_dsi_config: success to config DSI
9324 09:59:54.648069 anx7625_dp_start: MIPI phy setup OK.
9325 09:59:54.651574 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9326 09:59:54.654499 mtk_ddp_mode_set invalid vrefresh 60
9327 09:59:54.658158 main_disp_path_setup
9328 09:59:54.658268 ovl_layer_smi_id_en
9329 09:59:54.661672 ovl_layer_smi_id_en
9330 09:59:54.661757 ccorr_config
9331 09:59:54.661822 aal_config
9332 09:59:54.664545 gamma_config
9333 09:59:54.664650 postmask_config
9334 09:59:54.667935 dither_config
9335 09:59:54.671582 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9336 09:59:54.677978 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9337 09:59:54.681262 Root Device init finished in 529 msecs
9338 09:59:54.684369 CPU_CLUSTER: 0 init
9339 09:59:54.691614 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9340 09:59:54.694461 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9341 09:59:54.697907 APU_MBOX 0x190000b0 = 0x10001
9342 09:59:54.701289 APU_MBOX 0x190001b0 = 0x10001
9343 09:59:54.704335 APU_MBOX 0x190005b0 = 0x10001
9344 09:59:54.708136 APU_MBOX 0x190006b0 = 0x10001
9345 09:59:54.711583 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9346 09:59:54.723595 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9347 09:59:54.736314 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9348 09:59:54.742638 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9349 09:59:54.754619 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9350 09:59:54.763816 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9351 09:59:54.766927 CPU_CLUSTER: 0 init finished in 81 msecs
9352 09:59:54.770226 Devices initialized
9353 09:59:54.773456 Show all devs... After init.
9354 09:59:54.773590 Root Device: enabled 1
9355 09:59:54.776974 CPU_CLUSTER: 0: enabled 1
9356 09:59:54.780033 CPU: 00: enabled 1
9357 09:59:54.783724 BS: BS_DEV_INIT run times (exec / console): 206 / 428 ms
9358 09:59:54.786688 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9359 09:59:54.791045 ELOG: NV offset 0x57f000 size 0x1000
9360 09:59:54.796643 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9361 09:59:54.803461 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9362 09:59:54.806730 ELOG: Event(17) added with size 13 at 2023-11-24 09:57:44 UTC
9363 09:59:54.810018 out: cmd=0x121: 03 db 21 01 00 00 00 00
9364 09:59:54.814150 in-header: 03 f2 00 00 2c 00 00 00
9365 09:59:54.826847 in-data: 6d 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9366 09:59:54.833702 ELOG: Event(A1) added with size 10 at 2023-11-24 09:57:44 UTC
9367 09:59:54.840794 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9368 09:59:54.847221 ELOG: Event(A0) added with size 9 at 2023-11-24 09:57:44 UTC
9369 09:59:54.850293 elog_add_boot_reason: Logged dev mode boot
9370 09:59:54.853860 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9371 09:59:54.857312 Finalize devices...
9372 09:59:54.857412 Devices finalized
9373 09:59:54.863801 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9374 09:59:54.867078 Writing coreboot table at 0xffe64000
9375 09:59:54.870653 0. 000000000010a000-0000000000113fff: RAMSTAGE
9376 09:59:54.874055 1. 0000000040000000-00000000400fffff: RAM
9377 09:59:54.877241 2. 0000000040100000-000000004032afff: RAMSTAGE
9378 09:59:54.883612 3. 000000004032b000-00000000545fffff: RAM
9379 09:59:54.887274 4. 0000000054600000-000000005465ffff: BL31
9380 09:59:54.890320 5. 0000000054660000-00000000ffe63fff: RAM
9381 09:59:54.893471 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9382 09:59:54.900598 7. 0000000100000000-000000023fffffff: RAM
9383 09:59:54.900697 Passing 5 GPIOs to payload:
9384 09:59:54.907266 NAME | PORT | POLARITY | VALUE
9385 09:59:54.910301 EC in RW | 0x000000aa | low | undefined
9386 09:59:54.917067 EC interrupt | 0x00000005 | low | undefined
9387 09:59:54.920180 TPM interrupt | 0x000000ab | high | undefined
9388 09:59:54.923401 SD card detect | 0x00000011 | high | undefined
9389 09:59:54.930351 speaker enable | 0x00000093 | high | undefined
9390 09:59:54.933669 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9391 09:59:54.936898 in-header: 03 f9 00 00 02 00 00 00
9392 09:59:54.936989 in-data: 02 00
9393 09:59:54.940340 ADC[4]: Raw value=903988 ID=7
9394 09:59:54.944021 ADC[3]: Raw value=213441 ID=1
9395 09:59:54.944114 RAM Code: 0x71
9396 09:59:54.946988 ADC[6]: Raw value=75701 ID=0
9397 09:59:54.950132 ADC[5]: Raw value=213810 ID=1
9398 09:59:54.950222 SKU Code: 0x1
9399 09:59:54.956566 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 2e6b
9400 09:59:54.960318 coreboot table: 964 bytes.
9401 09:59:54.963464 IMD ROOT 0. 0xfffff000 0x00001000
9402 09:59:54.966483 IMD SMALL 1. 0xffffe000 0x00001000
9403 09:59:54.970137 RO MCACHE 2. 0xffffc000 0x00001104
9404 09:59:54.973183 CONSOLE 3. 0xfff7c000 0x00080000
9405 09:59:54.976374 FMAP 4. 0xfff7b000 0x00000452
9406 09:59:54.979748 TIME STAMP 5. 0xfff7a000 0x00000910
9407 09:59:54.983666 VBOOT WORK 6. 0xfff66000 0x00014000
9408 09:59:54.986454 RAMOOPS 7. 0xffe66000 0x00100000
9409 09:59:54.990425 COREBOOT 8. 0xffe64000 0x00002000
9410 09:59:54.990524 IMD small region:
9411 09:59:54.993468 IMD ROOT 0. 0xffffec00 0x00000400
9412 09:59:54.996428 VPD 1. 0xffffeb80 0x0000006c
9413 09:59:55.000035 MMC STATUS 2. 0xffffeb60 0x00000004
9414 09:59:55.007005 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9415 09:59:55.007136 Probing TPM: done!
9416 09:59:55.013357 Connected to device vid:did:rid of 1ae0:0028:00
9417 09:59:55.020185 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9418 09:59:55.023784 Initialized TPM device CR50 revision 0
9419 09:59:55.027917 Checking cr50 for pending updates
9420 09:59:55.033049 Reading cr50 TPM mode
9421 09:59:55.041537 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9422 09:59:55.048546 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9423 09:59:55.088731 read SPI 0x3990ec 0x4f1b0: 34851 us, 9297 KB/s, 74.376 Mbps
9424 09:59:55.092001 Checking segment from ROM address 0x40100000
9425 09:59:55.095436 Checking segment from ROM address 0x4010001c
9426 09:59:55.102338 Loading segment from ROM address 0x40100000
9427 09:59:55.102468 code (compression=0)
9428 09:59:55.109193 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9429 09:59:55.118606 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9430 09:59:55.118738 it's not compressed!
9431 09:59:55.125703 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9432 09:59:55.128665 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9433 09:59:55.149414 Loading segment from ROM address 0x4010001c
9434 09:59:55.149588 Entry Point 0x80000000
9435 09:59:55.152307 Loaded segments
9436 09:59:55.155335 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9437 09:59:55.162391 Jumping to boot code at 0x80000000(0xffe64000)
9438 09:59:55.168902 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9439 09:59:55.175647 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9440 09:59:55.183305 read SPI 0x8eb68 0x74a8: 3222 us, 9268 KB/s, 74.144 Mbps
9441 09:59:55.186831 Checking segment from ROM address 0x40100000
9442 09:59:55.190024 Checking segment from ROM address 0x4010001c
9443 09:59:55.196434 Loading segment from ROM address 0x40100000
9444 09:59:55.196548 code (compression=1)
9445 09:59:55.203495 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9446 09:59:55.213214 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9447 09:59:55.213339 using LZMA
9448 09:59:55.221581 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9449 09:59:55.228278 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9450 09:59:55.232082 Loading segment from ROM address 0x4010001c
9451 09:59:55.232168 Entry Point 0x54601000
9452 09:59:55.235098 Loaded segments
9453 09:59:55.238750 NOTICE: MT8192 bl31_setup
9454 09:59:55.245346 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9455 09:59:55.248469 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9456 09:59:55.252402 WARNING: region 0:
9457 09:59:55.255200 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9458 09:59:55.255325 WARNING: region 1:
9459 09:59:55.262110 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9460 09:59:55.265414 WARNING: region 2:
9461 09:59:55.268506 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9462 09:59:55.272285 WARNING: region 3:
9463 09:59:55.275464 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9464 09:59:55.279081 WARNING: region 4:
9465 09:59:55.285796 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9466 09:59:55.285886 WARNING: region 5:
9467 09:59:55.288612 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9468 09:59:55.292404 WARNING: region 6:
9469 09:59:55.295286 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9470 09:59:55.295401 WARNING: region 7:
9471 09:59:55.302462 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9472 09:59:55.309065 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9473 09:59:55.312007 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9474 09:59:55.315828 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9475 09:59:55.321907 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9476 09:59:55.325491 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9477 09:59:55.329187 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9478 09:59:55.335475 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9479 09:59:55.339269 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9480 09:59:55.342589 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9481 09:59:55.348927 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9482 09:59:55.352128 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9483 09:59:55.359120 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9484 09:59:55.362749 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9485 09:59:55.365667 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9486 09:59:55.371926 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9487 09:59:55.375649 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9488 09:59:55.378950 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9489 09:59:55.385830 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9490 09:59:55.389001 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9491 09:59:55.395436 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9492 09:59:55.399246 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9493 09:59:55.402678 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9494 09:59:55.408708 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9495 09:59:55.412006 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9496 09:59:55.418961 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9497 09:59:55.422232 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9498 09:59:55.425496 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9499 09:59:55.432969 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9500 09:59:55.436076 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9501 09:59:55.439127 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9502 09:59:55.445755 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9503 09:59:55.449245 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9504 09:59:55.452525 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9505 09:59:55.458949 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9506 09:59:55.462174 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9507 09:59:55.466235 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9508 09:59:55.469014 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9509 09:59:55.475952 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9510 09:59:55.479336 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9511 09:59:55.482579 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9512 09:59:55.485500 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9513 09:59:55.492149 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9514 09:59:55.495687 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9515 09:59:55.499437 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9516 09:59:55.502291 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9517 09:59:55.509154 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9518 09:59:55.512443 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9519 09:59:55.515915 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9520 09:59:55.522907 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9521 09:59:55.526250 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9522 09:59:55.529500 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9523 09:59:55.536062 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9524 09:59:55.539308 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9525 09:59:55.546334 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9526 09:59:55.549381 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9527 09:59:55.552428 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9528 09:59:55.559271 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9529 09:59:55.562579 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9530 09:59:55.569470 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9531 09:59:55.572794 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9532 09:59:55.579229 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9533 09:59:55.582721 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9534 09:59:55.589519 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9535 09:59:55.592678 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9536 09:59:55.595931 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9537 09:59:55.602733 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9538 09:59:55.605835 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9539 09:59:55.612808 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9540 09:59:55.616113 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9541 09:59:55.622549 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9542 09:59:55.626334 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9543 09:59:55.629596 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9544 09:59:55.636237 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9545 09:59:55.639497 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9546 09:59:55.646258 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9547 09:59:55.649333 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9548 09:59:55.656481 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9549 09:59:55.659497 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9550 09:59:55.663021 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9551 09:59:55.669792 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9552 09:59:55.672853 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9553 09:59:55.679396 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9554 09:59:55.682682 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9555 09:59:55.689402 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9556 09:59:55.693265 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9557 09:59:55.696006 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9558 09:59:55.703309 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9559 09:59:55.706581 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9560 09:59:55.713208 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9561 09:59:55.716296 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9562 09:59:55.719527 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9563 09:59:55.726507 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9564 09:59:55.729836 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9565 09:59:55.736994 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9566 09:59:55.739650 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9567 09:59:55.746416 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9568 09:59:55.749525 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9569 09:59:55.753101 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9570 09:59:55.756201 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9571 09:59:55.762982 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9572 09:59:55.766706 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9573 09:59:55.769586 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9574 09:59:55.776269 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9575 09:59:55.779608 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9576 09:59:55.786542 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9577 09:59:55.789360 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9578 09:59:55.792736 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9579 09:59:55.799754 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9580 09:59:55.802883 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9581 09:59:55.809889 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9582 09:59:55.813503 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9583 09:59:55.816618 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9584 09:59:55.822915 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9585 09:59:55.826336 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9586 09:59:55.833080 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9587 09:59:55.836991 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9588 09:59:55.840176 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9589 09:59:55.843563 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9590 09:59:55.850287 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9591 09:59:55.853397 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9592 09:59:55.856695 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9593 09:59:55.860575 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9594 09:59:55.867286 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9595 09:59:55.870296 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9596 09:59:55.873733 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9597 09:59:55.880254 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9598 09:59:55.883752 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9599 09:59:55.886993 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9600 09:59:55.893820 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9601 09:59:55.897223 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9602 09:59:55.900575 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9603 09:59:55.907421 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9604 09:59:55.910777 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9605 09:59:55.917248 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9606 09:59:55.920593 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9607 09:59:55.923680 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9608 09:59:55.930457 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9609 09:59:55.933785 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9610 09:59:55.940669 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9611 09:59:55.943923 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9612 09:59:55.947519 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9613 09:59:55.953912 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9614 09:59:55.957400 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9615 09:59:55.960370 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9616 09:59:55.967327 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9617 09:59:55.970881 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9618 09:59:55.977321 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9619 09:59:55.980497 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9620 09:59:55.984225 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9621 09:59:55.991078 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9622 09:59:55.994033 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9623 09:59:55.997565 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9624 09:59:56.004152 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9625 09:59:56.007556 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9626 09:59:56.014074 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9627 09:59:56.017210 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9628 09:59:56.020559 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9629 09:59:56.027519 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9630 09:59:56.030582 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9631 09:59:56.037348 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9632 09:59:56.040795 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9633 09:59:56.044457 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9634 09:59:56.050769 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9635 09:59:56.053922 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9636 09:59:56.058046 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9637 09:59:56.064106 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9638 09:59:56.067479 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9639 09:59:56.074517 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9640 09:59:56.077428 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9641 09:59:56.080803 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9642 09:59:56.087191 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9643 09:59:56.090827 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9644 09:59:56.097511 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9645 09:59:56.100721 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9646 09:59:56.103800 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9647 09:59:56.110750 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9648 09:59:56.114416 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9649 09:59:56.120801 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9650 09:59:56.124226 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9651 09:59:56.127458 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9652 09:59:56.134059 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9653 09:59:56.137491 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9654 09:59:56.140800 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9655 09:59:56.146968 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9656 09:59:56.150444 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9657 09:59:56.157152 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9658 09:59:56.160335 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9659 09:59:56.163696 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9660 09:59:56.170557 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9661 09:59:56.174154 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9662 09:59:56.180910 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9663 09:59:56.183924 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9664 09:59:56.190222 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9665 09:59:56.194140 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9666 09:59:56.197308 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9667 09:59:56.204127 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9668 09:59:56.207367 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9669 09:59:56.213443 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9670 09:59:56.216671 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9671 09:59:56.220053 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9672 09:59:56.226753 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9673 09:59:56.230163 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9674 09:59:56.237101 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9675 09:59:56.240214 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9676 09:59:56.243537 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9677 09:59:56.250296 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9678 09:59:56.253951 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9679 09:59:56.260389 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9680 09:59:56.263933 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9681 09:59:56.270174 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9682 09:59:56.273665 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9683 09:59:56.277212 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9684 09:59:56.284108 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9685 09:59:56.287166 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9686 09:59:56.290424 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9687 09:59:56.297184 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9688 09:59:56.300541 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9689 09:59:56.307388 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9690 09:59:56.310594 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9691 09:59:56.317117 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9692 09:59:56.320363 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9693 09:59:56.323735 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9694 09:59:56.330657 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9695 09:59:56.333790 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9696 09:59:56.341095 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9697 09:59:56.344095 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9698 09:59:56.347057 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9699 09:59:56.353879 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9700 09:59:56.357092 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9701 09:59:56.360716 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9702 09:59:56.367525 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9703 09:59:56.370541 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9704 09:59:56.374169 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9705 09:59:56.377011 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9706 09:59:56.383688 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9707 09:59:56.387117 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9708 09:59:56.390411 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9709 09:59:56.397232 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9710 09:59:56.400446 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9711 09:59:56.403717 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9712 09:59:56.410568 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9713 09:59:56.414196 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9714 09:59:56.420935 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9715 09:59:56.424145 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9716 09:59:56.427386 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9717 09:59:56.434008 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9718 09:59:56.437342 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9719 09:59:56.440420 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9720 09:59:56.447113 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9721 09:59:56.450969 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9722 09:59:56.457084 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9723 09:59:56.460208 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9724 09:59:56.463946 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9725 09:59:56.470013 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9726 09:59:56.473986 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9727 09:59:56.477127 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9728 09:59:56.483757 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9729 09:59:56.486854 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9730 09:59:56.489980 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9731 09:59:56.497214 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9732 09:59:56.500238 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9733 09:59:56.507244 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9734 09:59:56.510483 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9735 09:59:56.513377 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9736 09:59:56.520062 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9737 09:59:56.523725 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9738 09:59:56.526723 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9739 09:59:56.533759 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9740 09:59:56.536664 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9741 09:59:56.539801 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9742 09:59:56.543597 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9743 09:59:56.550240 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9744 09:59:56.553211 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9745 09:59:56.556540 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9746 09:59:56.559798 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9747 09:59:56.566663 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9748 09:59:56.570115 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9749 09:59:56.573041 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9750 09:59:56.576578 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9751 09:59:56.583145 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9752 09:59:56.586675 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9753 09:59:56.589862 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9754 09:59:56.596655 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9755 09:59:56.600313 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9756 09:59:56.606760 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9757 09:59:56.609688 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9758 09:59:56.612888 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9759 09:59:56.619611 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9760 09:59:56.623202 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9761 09:59:56.629785 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9762 09:59:56.633127 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9763 09:59:56.636237 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9764 09:59:56.642831 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9765 09:59:56.646658 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9766 09:59:56.653034 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9767 09:59:56.656427 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9768 09:59:56.659698 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9769 09:59:56.666718 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9770 09:59:56.669536 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9771 09:59:56.676195 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9772 09:59:56.679967 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9773 09:59:56.682921 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9774 09:59:56.689469 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9775 09:59:56.692904 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9776 09:59:56.699800 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9777 09:59:56.702969 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9778 09:59:56.705777 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9779 09:59:56.712877 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9780 09:59:56.715876 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9781 09:59:56.722590 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9782 09:59:56.725857 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9783 09:59:56.732530 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9784 09:59:56.736124 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9785 09:59:56.739213 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9786 09:59:56.745771 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9787 09:59:56.748943 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9788 09:59:56.755680 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9789 09:59:56.759140 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9790 09:59:56.762360 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9791 09:59:56.769524 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9792 09:59:56.772512 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9793 09:59:56.779527 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9794 09:59:56.782642 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9795 09:59:56.785981 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9796 09:59:56.792836 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9797 09:59:56.795887 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9798 09:59:56.802122 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9799 09:59:56.805482 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9800 09:59:56.812170 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9801 09:59:56.815874 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9802 09:59:56.819304 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9803 09:59:56.825284 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9804 09:59:56.829312 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9805 09:59:56.835436 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9806 09:59:56.838846 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9807 09:59:56.842077 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9808 09:59:56.849225 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9809 09:59:56.852248 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9810 09:59:56.858914 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9811 09:59:56.862205 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9812 09:59:56.865274 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9813 09:59:56.872610 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9814 09:59:56.875534 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9815 09:59:56.881819 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9816 09:59:56.885177 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9817 09:59:56.888978 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9818 09:59:56.895856 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9819 09:59:56.898745 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9820 09:59:56.905473 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9821 09:59:56.908443 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9822 09:59:56.911891 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9823 09:59:56.918452 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9824 09:59:56.922272 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9825 09:59:56.928371 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9826 09:59:56.932000 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9827 09:59:56.935774 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9828 09:59:56.941862 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9829 09:59:56.945263 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9830 09:59:56.952001 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9831 09:59:56.955123 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9832 09:59:56.962083 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9833 09:59:56.965295 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9834 09:59:56.968443 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9835 09:59:56.975121 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9836 09:59:56.978704 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9837 09:59:56.985186 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9838 09:59:56.988511 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9839 09:59:56.995228 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9840 09:59:56.998355 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9841 09:59:57.001550 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9842 09:59:57.008635 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9843 09:59:57.011658 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9844 09:59:57.018302 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9845 09:59:57.021420 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9846 09:59:57.028246 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9847 09:59:57.031353 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9848 09:59:57.038288 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9849 09:59:57.042098 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9850 09:59:57.045166 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9851 09:59:57.051325 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9852 09:59:57.054848 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9853 09:59:57.061695 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9854 09:59:57.065095 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9855 09:59:57.071843 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9856 09:59:57.075096 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9857 09:59:57.078346 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9858 09:59:57.084545 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9859 09:59:57.087918 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9860 09:59:57.094651 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9861 09:59:57.098049 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9862 09:59:57.104457 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9863 09:59:57.108158 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9864 09:59:57.114395 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9865 09:59:57.117738 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9866 09:59:57.120858 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9867 09:59:57.128272 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9868 09:59:57.131188 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9869 09:59:57.137724 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9870 09:59:57.141121 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9871 09:59:57.148013 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9872 09:59:57.151169 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9873 09:59:57.154389 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9874 09:59:57.161037 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9875 09:59:57.164484 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9876 09:59:57.170973 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9877 09:59:57.174269 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9878 09:59:57.180910 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9879 09:59:57.184174 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9880 09:59:57.191005 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9881 09:59:57.194516 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9882 09:59:57.197361 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9883 09:59:57.204015 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9884 09:59:57.208115 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9885 09:59:57.214377 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9886 09:59:57.217782 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9887 09:59:57.224049 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9888 09:59:57.227812 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9889 09:59:57.234736 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9890 09:59:57.237742 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9891 09:59:57.244237 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9892 09:59:57.247500 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9893 09:59:57.254159 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9894 09:59:57.258058 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9895 09:59:57.264262 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9896 09:59:57.267255 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9897 09:59:57.274134 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9898 09:59:57.277353 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9899 09:59:57.284288 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9900 09:59:57.287696 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9901 09:59:57.293780 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9902 09:59:57.297491 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9903 09:59:57.303814 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9904 09:59:57.307111 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9905 09:59:57.314145 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9906 09:59:57.317152 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9907 09:59:57.321023 INFO: [APUAPC] vio 0
9908 09:59:57.324228 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9909 09:59:57.330511 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9910 09:59:57.333869 INFO: [APUAPC] D0_APC_0: 0x400510
9911 09:59:57.333984 INFO: [APUAPC] D0_APC_1: 0x0
9912 09:59:57.337405 INFO: [APUAPC] D0_APC_2: 0x1540
9913 09:59:57.340294 INFO: [APUAPC] D0_APC_3: 0x0
9914 09:59:57.344551 INFO: [APUAPC] D1_APC_0: 0xffffffff
9915 09:59:57.347537 INFO: [APUAPC] D1_APC_1: 0xffffffff
9916 09:59:57.350337 INFO: [APUAPC] D1_APC_2: 0x3fffff
9917 09:59:57.353838 INFO: [APUAPC] D1_APC_3: 0x0
9918 09:59:57.357436 INFO: [APUAPC] D2_APC_0: 0xffffffff
9919 09:59:57.360428 INFO: [APUAPC] D2_APC_1: 0xffffffff
9920 09:59:57.363918 INFO: [APUAPC] D2_APC_2: 0x3fffff
9921 09:59:57.367608 INFO: [APUAPC] D2_APC_3: 0x0
9922 09:59:57.370581 INFO: [APUAPC] D3_APC_0: 0xffffffff
9923 09:59:57.373821 INFO: [APUAPC] D3_APC_1: 0xffffffff
9924 09:59:57.376828 INFO: [APUAPC] D3_APC_2: 0x3fffff
9925 09:59:57.380654 INFO: [APUAPC] D3_APC_3: 0x0
9926 09:59:57.383878 INFO: [APUAPC] D4_APC_0: 0xffffffff
9927 09:59:57.387002 INFO: [APUAPC] D4_APC_1: 0xffffffff
9928 09:59:57.390321 INFO: [APUAPC] D4_APC_2: 0x3fffff
9929 09:59:57.393530 INFO: [APUAPC] D4_APC_3: 0x0
9930 09:59:57.397254 INFO: [APUAPC] D5_APC_0: 0xffffffff
9931 09:59:57.400093 INFO: [APUAPC] D5_APC_1: 0xffffffff
9932 09:59:57.403558 INFO: [APUAPC] D5_APC_2: 0x3fffff
9933 09:59:57.406737 INFO: [APUAPC] D5_APC_3: 0x0
9934 09:59:57.409928 INFO: [APUAPC] D6_APC_0: 0xffffffff
9935 09:59:57.413664 INFO: [APUAPC] D6_APC_1: 0xffffffff
9936 09:59:57.417097 INFO: [APUAPC] D6_APC_2: 0x3fffff
9937 09:59:57.420027 INFO: [APUAPC] D6_APC_3: 0x0
9938 09:59:57.423631 INFO: [APUAPC] D7_APC_0: 0xffffffff
9939 09:59:57.426761 INFO: [APUAPC] D7_APC_1: 0xffffffff
9940 09:59:57.429945 INFO: [APUAPC] D7_APC_2: 0x3fffff
9941 09:59:57.433604 INFO: [APUAPC] D7_APC_3: 0x0
9942 09:59:57.437009 INFO: [APUAPC] D8_APC_0: 0xffffffff
9943 09:59:57.440523 INFO: [APUAPC] D8_APC_1: 0xffffffff
9944 09:59:57.443316 INFO: [APUAPC] D8_APC_2: 0x3fffff
9945 09:59:57.446810 INFO: [APUAPC] D8_APC_3: 0x0
9946 09:59:57.449866 INFO: [APUAPC] D9_APC_0: 0xffffffff
9947 09:59:57.453435 INFO: [APUAPC] D9_APC_1: 0xffffffff
9948 09:59:57.456744 INFO: [APUAPC] D9_APC_2: 0x3fffff
9949 09:59:57.456903 INFO: [APUAPC] D9_APC_3: 0x0
9950 09:59:57.463027 INFO: [APUAPC] D10_APC_0: 0xffffffff
9951 09:59:57.466369 INFO: [APUAPC] D10_APC_1: 0xffffffff
9952 09:59:57.469917 INFO: [APUAPC] D10_APC_2: 0x3fffff
9953 09:59:57.470082 INFO: [APUAPC] D10_APC_3: 0x0
9954 09:59:57.476401 INFO: [APUAPC] D11_APC_0: 0xffffffff
9955 09:59:57.480195 INFO: [APUAPC] D11_APC_1: 0xffffffff
9956 09:59:57.483237 INFO: [APUAPC] D11_APC_2: 0x3fffff
9957 09:59:57.486843 INFO: [APUAPC] D11_APC_3: 0x0
9958 09:59:57.490248 INFO: [APUAPC] D12_APC_0: 0xffffffff
9959 09:59:57.493183 INFO: [APUAPC] D12_APC_1: 0xffffffff
9960 09:59:57.496500 INFO: [APUAPC] D12_APC_2: 0x3fffff
9961 09:59:57.496662 INFO: [APUAPC] D12_APC_3: 0x0
9962 09:59:57.503626 INFO: [APUAPC] D13_APC_0: 0xffffffff
9963 09:59:57.506509 INFO: [APUAPC] D13_APC_1: 0xffffffff
9964 09:59:57.510053 INFO: [APUAPC] D13_APC_2: 0x3fffff
9965 09:59:57.513353 INFO: [APUAPC] D13_APC_3: 0x0
9966 09:59:57.516469 INFO: [APUAPC] D14_APC_0: 0xffffffff
9967 09:59:57.519738 INFO: [APUAPC] D14_APC_1: 0xffffffff
9968 09:59:57.523089 INFO: [APUAPC] D14_APC_2: 0x3fffff
9969 09:59:57.526375 INFO: [APUAPC] D14_APC_3: 0x0
9970 09:59:57.529650 INFO: [APUAPC] D15_APC_0: 0xffffffff
9971 09:59:57.532949 INFO: [APUAPC] D15_APC_1: 0xffffffff
9972 09:59:57.536398 INFO: [APUAPC] D15_APC_2: 0x3fffff
9973 09:59:57.539558 INFO: [APUAPC] D15_APC_3: 0x0
9974 09:59:57.539696 INFO: [APUAPC] APC_CON: 0x4
9975 09:59:57.542862 INFO: [NOCDAPC] D0_APC_0: 0x0
9976 09:59:57.545993 INFO: [NOCDAPC] D0_APC_1: 0x0
9977 09:59:57.549291 INFO: [NOCDAPC] D1_APC_0: 0x0
9978 09:59:57.552833 INFO: [NOCDAPC] D1_APC_1: 0xfff
9979 09:59:57.556529 INFO: [NOCDAPC] D2_APC_0: 0x0
9980 09:59:57.559782 INFO: [NOCDAPC] D2_APC_1: 0xfff
9981 09:59:57.562604 INFO: [NOCDAPC] D3_APC_0: 0x0
9982 09:59:57.566048 INFO: [NOCDAPC] D3_APC_1: 0xfff
9983 09:59:57.569662 INFO: [NOCDAPC] D4_APC_0: 0x0
9984 09:59:57.569804 INFO: [NOCDAPC] D4_APC_1: 0xfff
9985 09:59:57.572561 INFO: [NOCDAPC] D5_APC_0: 0x0
9986 09:59:57.576186 INFO: [NOCDAPC] D5_APC_1: 0xfff
9987 09:59:57.579204 INFO: [NOCDAPC] D6_APC_0: 0x0
9988 09:59:57.582674 INFO: [NOCDAPC] D6_APC_1: 0xfff
9989 09:59:57.586072 INFO: [NOCDAPC] D7_APC_0: 0x0
9990 09:59:57.589558 INFO: [NOCDAPC] D7_APC_1: 0xfff
9991 09:59:57.592900 INFO: [NOCDAPC] D8_APC_0: 0x0
9992 09:59:57.595879 INFO: [NOCDAPC] D8_APC_1: 0xfff
9993 09:59:57.599749 INFO: [NOCDAPC] D9_APC_0: 0x0
9994 09:59:57.602822 INFO: [NOCDAPC] D9_APC_1: 0xfff
9995 09:59:57.603001 INFO: [NOCDAPC] D10_APC_0: 0x0
9996 09:59:57.605972 INFO: [NOCDAPC] D10_APC_1: 0xfff
9997 09:59:57.609726 INFO: [NOCDAPC] D11_APC_0: 0x0
9998 09:59:57.612739 INFO: [NOCDAPC] D11_APC_1: 0xfff
9999 09:59:57.616201 INFO: [NOCDAPC] D12_APC_0: 0x0
10000 09:59:57.619490 INFO: [NOCDAPC] D12_APC_1: 0xfff
10001 09:59:57.622734 INFO: [NOCDAPC] D13_APC_0: 0x0
10002 09:59:57.625835 INFO: [NOCDAPC] D13_APC_1: 0xfff
10003 09:59:57.629791 INFO: [NOCDAPC] D14_APC_0: 0x0
10004 09:59:57.632719 INFO: [NOCDAPC] D14_APC_1: 0xfff
10005 09:59:57.635805 INFO: [NOCDAPC] D15_APC_0: 0x0
10006 09:59:57.639479 INFO: [NOCDAPC] D15_APC_1: 0xfff
10007 09:59:57.642650 INFO: [NOCDAPC] APC_CON: 0x4
10008 09:59:57.645869 INFO: [APUAPC] set_apusys_apc done
10009 09:59:57.649160 INFO: [DEVAPC] devapc_init done
10010 09:59:57.652789 INFO: GICv3 without legacy support detected.
10011 09:59:57.655995 INFO: ARM GICv3 driver initialized in EL3
10012 09:59:57.659080 INFO: Maximum SPI INTID supported: 639
10013 09:59:57.662738 INFO: BL31: Initializing runtime services
10014 09:59:57.669131 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10015 09:59:57.672285 INFO: SPM: enable CPC mode
10016 09:59:57.676151 INFO: mcdi ready for mcusys-off-idle and system suspend
10017 09:59:57.682376 INFO: BL31: Preparing for EL3 exit to normal world
10018 09:59:57.685766 INFO: Entry point address = 0x80000000
10019 09:59:57.688617 INFO: SPSR = 0x8
10020 09:59:57.693775
10021 09:59:57.693889
10022 09:59:57.693981
10023 09:59:57.696591 Starting depthcharge on Spherion...
10024 09:59:57.696704
10025 09:59:57.696792 Wipe memory regions:
10026 09:59:57.696875
10027 09:59:57.697634 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10028 09:59:57.697746 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10029 09:59:57.697833 Setting prompt string to ['asurada:']
10030 09:59:57.697918 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10031 09:59:57.700214 [0x00000040000000, 0x00000054600000)
10032 09:59:57.822611
10033 09:59:57.822777 [0x00000054660000, 0x00000080000000)
10034 09:59:58.082892
10035 09:59:58.083037 [0x000000821a7280, 0x000000ffe64000)
10036 09:59:58.827285
10037 09:59:58.827431 [0x00000100000000, 0x00000240000000)
10038 10:00:00.717709
10039 10:00:00.720611 Initializing XHCI USB controller at 0x11200000.
10040 10:00:01.758421
10041 10:00:01.761359 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10042 10:00:01.761492
10043 10:00:01.761597
10044 10:00:01.761689
10045 10:00:01.762013 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10047 10:00:01.862422 asurada: tftpboot 192.168.201.1 12073268/tftp-deploy-2obxkcdy/kernel/image.itb 12073268/tftp-deploy-2obxkcdy/kernel/cmdline
10048 10:00:01.862633 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10049 10:00:01.862758 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10050 10:00:01.867578 tftpboot 192.168.201.1 12073268/tftp-deploy-2obxkcdy/kernel/image.ittp-deploy-2obxkcdy/kernel/cmdline
10051 10:00:01.867712
10052 10:00:01.867808 Waiting for link
10053 10:00:02.027526
10054 10:00:02.027723 R8152: Initializing
10055 10:00:02.027831
10056 10:00:02.031312 Version 9 (ocp_data = 6010)
10057 10:00:02.031426
10058 10:00:02.034460 R8152: Done initializing
10059 10:00:02.034554
10060 10:00:02.034661 Adding net device
10061 10:00:04.011718
10062 10:00:04.011912 done.
10063 10:00:04.012018
10064 10:00:04.012118 MAC: 00:e0:4c:78:7a:aa
10065 10:00:04.012221
10066 10:00:04.014849 Sending DHCP discover... done.
10067 10:00:04.014967
10068 10:00:04.018772 Waiting for reply... done.
10069 10:00:04.018918
10070 10:00:04.020851 Sending DHCP request... done.
10071 10:00:04.020973
10072 10:00:04.027173 Waiting for reply... done.
10073 10:00:04.027321
10074 10:00:04.027421 My ip is 192.168.201.12
10075 10:00:04.027517
10076 10:00:04.030293 The DHCP server ip is 192.168.201.1
10077 10:00:04.030417
10078 10:00:04.036974 TFTP server IP predefined by user: 192.168.201.1
10079 10:00:04.037096
10080 10:00:04.043289 Bootfile predefined by user: 12073268/tftp-deploy-2obxkcdy/kernel/image.itb
10081 10:00:04.043385
10082 10:00:04.046686 Sending tftp read request... done.
10083 10:00:04.046808
10084 10:00:04.049953 Waiting for the transfer...
10085 10:00:04.050078
10086 10:00:04.301323 00000000 ################################################################
10087 10:00:04.301521
10088 10:00:04.555714 00080000 ################################################################
10089 10:00:04.555919
10090 10:00:04.807650 00100000 ################################################################
10091 10:00:04.807846
10092 10:00:05.059825 00180000 ################################################################
10093 10:00:05.060016
10094 10:00:05.316064 00200000 ################################################################
10095 10:00:05.316234
10096 10:00:05.568250 00280000 ################################################################
10097 10:00:05.568433
10098 10:00:05.823738 00300000 ################################################################
10099 10:00:05.823918
10100 10:00:06.076656 00380000 ################################################################
10101 10:00:06.076851
10102 10:00:06.330177 00400000 ################################################################
10103 10:00:06.330379
10104 10:00:06.584421 00480000 ################################################################
10105 10:00:06.584666
10106 10:00:06.838293 00500000 ################################################################
10107 10:00:06.838482
10108 10:00:07.091822 00580000 ################################################################
10109 10:00:07.091965
10110 10:00:07.346836 00600000 ################################################################
10111 10:00:07.347035
10112 10:00:07.600836 00680000 ################################################################
10113 10:00:07.601067
10114 10:00:07.853864 00700000 ################################################################
10115 10:00:07.854068
10116 10:00:08.105774 00780000 ################################################################
10117 10:00:08.105933
10118 10:00:08.361346 00800000 ################################################################
10119 10:00:08.361535
10120 10:00:08.616621 00880000 ################################################################
10121 10:00:08.616817
10122 10:00:08.871096 00900000 ################################################################
10123 10:00:08.871293
10124 10:00:09.402349 00980000 ################################################################
10125 10:00:09.402526
10126 10:00:09.402649 00a00000 ################################################################
10127 10:00:09.402721
10128 10:00:09.618943 00a80000 ################################################################
10129 10:00:09.619112
10130 10:00:09.864807 00b00000 ################################################################
10131 10:00:09.864950
10132 10:00:10.112659 00b80000 ################################################################
10133 10:00:10.112832
10134 10:00:10.367330 00c00000 ################################################################
10135 10:00:10.367508
10136 10:00:10.610601 00c80000 ################################################################
10137 10:00:10.610814
10138 10:00:10.862179 00d00000 ################################################################
10139 10:00:10.862339
10140 10:00:11.123311 00d80000 ################################################################
10141 10:00:11.123485
10142 10:00:11.378151 00e00000 ################################################################
10143 10:00:11.378310
10144 10:00:11.633675 00e80000 ################################################################
10145 10:00:11.633809
10146 10:00:11.887993 00f00000 ################################################################
10147 10:00:11.888162
10148 10:00:12.133839 00f80000 ################################################################
10149 10:00:12.133994
10150 10:00:12.387954 01000000 ################################################################
10151 10:00:12.388095
10152 10:00:12.643910 01080000 ################################################################
10153 10:00:12.644095
10154 10:00:12.900160 01100000 ################################################################
10155 10:00:12.900299
10156 10:00:13.153389 01180000 ################################################################
10157 10:00:13.153582
10158 10:00:13.404891 01200000 ################################################################
10159 10:00:13.405071
10160 10:00:13.662116 01280000 ################################################################
10161 10:00:13.662299
10162 10:00:13.907764 01300000 ################################################################
10163 10:00:13.907927
10164 10:00:14.201633 01380000 ################################################################
10165 10:00:14.201880
10166 10:00:14.394910 01400000 ################################################################
10167 10:00:14.395046
10168 10:00:14.633788 01480000 ################################################################
10169 10:00:14.633926
10170 10:00:14.868667 01500000 ################################################################
10171 10:00:14.868848
10172 10:00:15.105769 01580000 ################################################################
10173 10:00:15.105942
10174 10:00:15.343640 01600000 ################################################################
10175 10:00:15.343846
10176 10:00:15.581381 01680000 ################################################################
10177 10:00:15.581544
10178 10:00:15.818127 01700000 ################################################################
10179 10:00:15.818275
10180 10:00:16.052071 01780000 ################################################################
10181 10:00:16.052206
10182 10:00:16.286639 01800000 ################################################################
10183 10:00:16.286788
10184 10:00:16.527472 01880000 ################################################################
10185 10:00:16.527611
10186 10:00:16.762946 01900000 ################################################################
10187 10:00:16.763089
10188 10:00:16.995976 01980000 ################################################################
10189 10:00:16.996150
10190 10:00:17.235061 01a00000 ################################################################
10191 10:00:17.235246
10192 10:00:17.473957 01a80000 ################################################################
10193 10:00:17.474096
10194 10:00:17.721104 01b00000 ################################################################
10195 10:00:17.721262
10196 10:00:17.975397 01b80000 ################################################################
10197 10:00:17.975575
10198 10:00:18.228714 01c00000 ################################################################
10199 10:00:18.228866
10200 10:00:18.486796 01c80000 ################################################################
10201 10:00:18.486946
10202 10:00:18.738200 01d00000 ################################################################
10203 10:00:18.738338
10204 10:00:19.151144 01d80000 ################################################################
10205 10:00:19.151343
10206 10:00:19.576046 01e00000 ################################################################
10207 10:00:19.576283
10208 10:00:19.587954 01e80000 ############################################################### done.
10209 10:00:19.588136
10210 10:00:19.588253 The bootfile was 32497442 bytes long.
10211 10:00:19.588359
10212 10:00:19.588459 Sending tftp read request... done.
10213 10:00:19.588556
10214 10:00:19.588650 Waiting for the transfer...
10215 10:00:19.588745
10216 10:00:19.588867 00000000 # done.
10217 10:00:19.588990
10218 10:00:19.589113 Command line loaded dynamically from TFTP file: 12073268/tftp-deploy-2obxkcdy/kernel/cmdline
10219 10:00:19.589220
10220 10:00:19.603409 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10221 10:00:19.603599
10222 10:00:19.603705 Loading FIT.
10223 10:00:19.603797
10224 10:00:19.606198 Image ramdisk-1 has 21400585 bytes.
10225 10:00:19.606320
10226 10:00:19.609778 Image fdt-1 has 47278 bytes.
10227 10:00:19.609967
10228 10:00:19.613101 Image kernel-1 has 11047542 bytes.
10229 10:00:19.613223
10230 10:00:19.619879 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10231 10:00:19.619996
10232 10:00:19.639940 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10233 10:00:19.640101
10234 10:00:19.642697 Choosing best match conf-1 for compat google,spherion-rev2.
10235 10:00:19.647952
10236 10:00:19.652618 Connected to device vid:did:rid of 1ae0:0028:00
10237 10:00:19.660742
10238 10:00:19.664167 tpm_get_response: command 0x17b, return code 0x0
10239 10:00:19.664272
10240 10:00:19.666940 ec_init: CrosEC protocol v3 supported (256, 248)
10241 10:00:19.671328
10242 10:00:19.674789 tpm_cleanup: add release locality here.
10243 10:00:19.674881
10244 10:00:19.674948 Shutting down all USB controllers.
10245 10:00:19.678183
10246 10:00:19.678288 Removing current net device
10247 10:00:19.678357
10248 10:00:19.684359 Exiting depthcharge with code 4 at timestamp: 51247722
10249 10:00:19.684454
10250 10:00:19.688403 LZMA decompressing kernel-1 to 0x821a6718
10251 10:00:19.688503
10252 10:00:19.691702 LZMA decompressing kernel-1 to 0x40000000
10253 10:00:21.080733
10254 10:00:21.080871 jumping to kernel
10255 10:00:21.081331 end: 2.2.4 bootloader-commands (duration 00:00:23) [common]
10256 10:00:21.081434 start: 2.2.5 auto-login-action (timeout 00:04:02) [common]
10257 10:00:21.081514 Setting prompt string to ['Linux version [0-9]']
10258 10:00:21.081592 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10259 10:00:21.081694 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10260 10:00:21.163434
10261 10:00:21.166810 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10262 10:00:21.170387 start: 2.2.5.1 login-action (timeout 00:04:02) [common]
10263 10:00:21.170491 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10264 10:00:21.170578 Setting prompt string to []
10265 10:00:21.170661 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10266 10:00:21.170739 Using line separator: #'\n'#
10267 10:00:21.170799 No login prompt set.
10268 10:00:21.170863 Parsing kernel messages
10269 10:00:21.170920 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10270 10:00:21.171024 [login-action] Waiting for messages, (timeout 00:04:02)
10271 10:00:21.190199 [ 0.000000] Linux version 6.1.62-cip9 (KernelCI@build-j22848-arm64-gcc-10-defconfig-arm64-chromebook-6q8mw) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Nov 24 09:44:51 UTC 2023
10272 10:00:21.193017 [ 0.000000] random: crng init done
10273 10:00:21.200050 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10274 10:00:21.202959 [ 0.000000] efi: UEFI not found.
10275 10:00:21.209376 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10276 10:00:21.215887 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10277 10:00:21.226349 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10278 10:00:21.236098 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10279 10:00:21.242318 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10280 10:00:21.249358 [ 0.000000] printk: bootconsole [mtk8250] enabled
10281 10:00:21.255992 [ 0.000000] NUMA: No NUMA configuration found
10282 10:00:21.262785 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10283 10:00:21.266128 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10284 10:00:21.269072 [ 0.000000] Zone ranges:
10285 10:00:21.275483 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10286 10:00:21.279083 [ 0.000000] DMA32 empty
10287 10:00:21.285538 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10288 10:00:21.288940 [ 0.000000] Movable zone start for each node
10289 10:00:21.292362 [ 0.000000] Early memory node ranges
10290 10:00:21.298834 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10291 10:00:21.305790 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10292 10:00:21.312034 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10293 10:00:21.319012 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10294 10:00:21.322355 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10295 10:00:21.332317 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10296 10:00:21.387552 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10297 10:00:21.394676 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10298 10:00:21.400813 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10299 10:00:21.404049 [ 0.000000] psci: probing for conduit method from DT.
10300 10:00:21.410972 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10301 10:00:21.414145 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10302 10:00:21.420771 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10303 10:00:21.424349 [ 0.000000] psci: SMC Calling Convention v1.2
10304 10:00:21.430610 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10305 10:00:21.434187 [ 0.000000] Detected VIPT I-cache on CPU0
10306 10:00:21.440671 [ 0.000000] CPU features: detected: GIC system register CPU interface
10307 10:00:21.447536 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10308 10:00:21.454240 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10309 10:00:21.460366 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10310 10:00:21.467081 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10311 10:00:21.473919 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10312 10:00:21.480626 [ 0.000000] alternatives: applying boot alternatives
10313 10:00:21.484142 [ 0.000000] Fallback order for Node 0: 0
10314 10:00:21.490634 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10315 10:00:21.494142 [ 0.000000] Policy zone: Normal
10316 10:00:21.510371 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10317 10:00:21.520226 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10318 10:00:21.531969 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10319 10:00:21.541665 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10320 10:00:21.548725 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10321 10:00:21.551550 <6>[ 0.000000] software IO TLB: area num 8.
10322 10:00:21.609278 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10323 10:00:21.758003 <6>[ 0.000000] Memory: 7948720K/8385536K available (17984K kernel code, 4116K rwdata, 17312K rodata, 8384K init, 615K bss, 404048K reserved, 32768K cma-reserved)
10324 10:00:21.765111 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10325 10:00:21.771243 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10326 10:00:21.775039 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10327 10:00:21.781651 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10328 10:00:21.787617 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10329 10:00:21.790938 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10330 10:00:21.801289 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10331 10:00:21.808171 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10332 10:00:21.811044 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10333 10:00:21.818910 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10334 10:00:21.822360 <6>[ 0.000000] GICv3: 608 SPIs implemented
10335 10:00:21.828891 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10336 10:00:21.832365 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10337 10:00:21.835998 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10338 10:00:21.845907 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10339 10:00:21.855742 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10340 10:00:21.869187 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10341 10:00:21.875762 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10342 10:00:21.884534 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10343 10:00:21.898029 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10344 10:00:21.904144 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10345 10:00:21.911130 <6>[ 0.009173] Console: colour dummy device 80x25
10346 10:00:21.920954 <6>[ 0.013897] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10347 10:00:21.927708 <6>[ 0.024339] pid_max: default: 32768 minimum: 301
10348 10:00:21.931155 <6>[ 0.029240] LSM: Security Framework initializing
10349 10:00:21.937946 <6>[ 0.034178] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10350 10:00:21.948031 <6>[ 0.041992] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10351 10:00:21.954356 <6>[ 0.051459] cblist_init_generic: Setting adjustable number of callback queues.
10352 10:00:21.961460 <6>[ 0.058902] cblist_init_generic: Setting shift to 3 and lim to 1.
10353 10:00:21.971235 <6>[ 0.065239] cblist_init_generic: Setting adjustable number of callback queues.
10354 10:00:21.974030 <6>[ 0.072712] cblist_init_generic: Setting shift to 3 and lim to 1.
10355 10:00:21.981162 <6>[ 0.079110] rcu: Hierarchical SRCU implementation.
10356 10:00:21.988071 <6>[ 0.084126] rcu: Max phase no-delay instances is 1000.
10357 10:00:21.994410 <6>[ 0.091147] EFI services will not be available.
10358 10:00:21.997891 <6>[ 0.096100] smp: Bringing up secondary CPUs ...
10359 10:00:22.005463 <6>[ 0.101146] Detected VIPT I-cache on CPU1
10360 10:00:22.012334 <6>[ 0.101217] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10361 10:00:22.018951 <6>[ 0.101248] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10362 10:00:22.022133 <6>[ 0.101582] Detected VIPT I-cache on CPU2
10363 10:00:22.032058 <6>[ 0.101631] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10364 10:00:22.038587 <6>[ 0.101647] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10365 10:00:22.041631 <6>[ 0.101907] Detected VIPT I-cache on CPU3
10366 10:00:22.048137 <6>[ 0.101952] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10367 10:00:22.055222 <6>[ 0.101965] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10368 10:00:22.058274 <6>[ 0.102268] CPU features: detected: Spectre-v4
10369 10:00:22.064721 <6>[ 0.102274] CPU features: detected: Spectre-BHB
10370 10:00:22.068237 <6>[ 0.102279] Detected PIPT I-cache on CPU4
10371 10:00:22.074705 <6>[ 0.102337] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10372 10:00:22.081785 <6>[ 0.102353] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10373 10:00:22.088113 <6>[ 0.102642] Detected PIPT I-cache on CPU5
10374 10:00:22.094623 <6>[ 0.102705] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10375 10:00:22.101517 <6>[ 0.102721] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10376 10:00:22.104999 <6>[ 0.103001] Detected PIPT I-cache on CPU6
10377 10:00:22.111731 <6>[ 0.103065] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10378 10:00:22.118104 <6>[ 0.103082] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10379 10:00:22.125020 <6>[ 0.103380] Detected PIPT I-cache on CPU7
10380 10:00:22.131609 <6>[ 0.103443] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10381 10:00:22.138414 <6>[ 0.103459] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10382 10:00:22.141210 <6>[ 0.103506] smp: Brought up 1 node, 8 CPUs
10383 10:00:22.148214 <6>[ 0.244953] SMP: Total of 8 processors activated.
10384 10:00:22.151653 <6>[ 0.249874] CPU features: detected: 32-bit EL0 Support
10385 10:00:22.160944 <6>[ 0.255237] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10386 10:00:22.167814 <6>[ 0.264038] CPU features: detected: Common not Private translations
10387 10:00:22.170989 <6>[ 0.270514] CPU features: detected: CRC32 instructions
10388 10:00:22.178250 <6>[ 0.275865] CPU features: detected: RCpc load-acquire (LDAPR)
10389 10:00:22.184456 <6>[ 0.281825] CPU features: detected: LSE atomic instructions
10390 10:00:22.191509 <6>[ 0.287606] CPU features: detected: Privileged Access Never
10391 10:00:22.194829 <6>[ 0.293386] CPU features: detected: RAS Extension Support
10392 10:00:22.204845 <6>[ 0.298995] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10393 10:00:22.207626 <6>[ 0.306258] CPU: All CPU(s) started at EL2
10394 10:00:22.214435 <6>[ 0.310601] alternatives: applying system-wide alternatives
10395 10:00:22.222794 <6>[ 0.321306] devtmpfs: initialized
10396 10:00:22.235172 <6>[ 0.330180] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10397 10:00:22.245480 <6>[ 0.340143] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10398 10:00:22.252186 <6>[ 0.348326] pinctrl core: initialized pinctrl subsystem
10399 10:00:22.255032 <6>[ 0.354982] DMI not present or invalid.
10400 10:00:22.261668 <6>[ 0.359399] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10401 10:00:22.271795 <6>[ 0.366273] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10402 10:00:22.278044 <6>[ 0.373855] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10403 10:00:22.288103 <6>[ 0.382077] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10404 10:00:22.291318 <6>[ 0.390321] audit: initializing netlink subsys (disabled)
10405 10:00:22.301118 <5>[ 0.396015] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10406 10:00:22.308263 <6>[ 0.396727] thermal_sys: Registered thermal governor 'step_wise'
10407 10:00:22.314732 <6>[ 0.403982] thermal_sys: Registered thermal governor 'power_allocator'
10408 10:00:22.317585 <6>[ 0.410238] cpuidle: using governor menu
10409 10:00:22.324398 <6>[ 0.421196] NET: Registered PF_QIPCRTR protocol family
10410 10:00:22.330853 <6>[ 0.426683] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10411 10:00:22.337309 <6>[ 0.433787] ASID allocator initialised with 32768 entries
10412 10:00:22.340654 <6>[ 0.440362] Serial: AMBA PL011 UART driver
10413 10:00:22.350821 <4>[ 0.449155] Trying to register duplicate clock ID: 134
10414 10:00:22.405163 <6>[ 0.506781] KASLR enabled
10415 10:00:22.419317 <6>[ 0.514466] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10416 10:00:22.426186 <6>[ 0.521479] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10417 10:00:22.433162 <6>[ 0.527970] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10418 10:00:22.439511 <6>[ 0.534976] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10419 10:00:22.445685 <6>[ 0.541465] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10420 10:00:22.452971 <6>[ 0.548471] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10421 10:00:22.459397 <6>[ 0.554957] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10422 10:00:22.465700 <6>[ 0.561963] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10423 10:00:22.468987 <6>[ 0.569460] ACPI: Interpreter disabled.
10424 10:00:22.477889 <6>[ 0.575808] iommu: Default domain type: Translated
10425 10:00:22.484280 <6>[ 0.580919] iommu: DMA domain TLB invalidation policy: strict mode
10426 10:00:22.487653 <5>[ 0.587571] SCSI subsystem initialized
10427 10:00:22.494245 <6>[ 0.591740] usbcore: registered new interface driver usbfs
10428 10:00:22.500945 <6>[ 0.597472] usbcore: registered new interface driver hub
10429 10:00:22.503750 <6>[ 0.603023] usbcore: registered new device driver usb
10430 10:00:22.510749 <6>[ 0.609114] pps_core: LinuxPPS API ver. 1 registered
10431 10:00:22.520615 <6>[ 0.614308] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10432 10:00:22.524438 <6>[ 0.623653] PTP clock support registered
10433 10:00:22.527759 <6>[ 0.627894] EDAC MC: Ver: 3.0.0
10434 10:00:22.535043 <6>[ 0.633058] FPGA manager framework
10435 10:00:22.541862 <6>[ 0.636738] Advanced Linux Sound Architecture Driver Initialized.
10436 10:00:22.544731 <6>[ 0.643506] vgaarb: loaded
10437 10:00:22.551458 <6>[ 0.646674] clocksource: Switched to clocksource arch_sys_counter
10438 10:00:22.555031 <5>[ 0.653103] VFS: Disk quotas dquot_6.6.0
10439 10:00:22.561318 <6>[ 0.657283] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10440 10:00:22.564747 <6>[ 0.664467] pnp: PnP ACPI: disabled
10441 10:00:22.573132 <6>[ 0.671090] NET: Registered PF_INET protocol family
10442 10:00:22.582687 <6>[ 0.676676] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10443 10:00:22.594464 <6>[ 0.688947] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10444 10:00:22.604109 <6>[ 0.697760] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10445 10:00:22.611001 <6>[ 0.705729] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10446 10:00:22.617439 <6>[ 0.714429] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10447 10:00:22.629407 <6>[ 0.724176] TCP: Hash tables configured (established 65536 bind 65536)
10448 10:00:22.635802 <6>[ 0.731038] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10449 10:00:22.642510 <6>[ 0.738237] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10450 10:00:22.649007 <6>[ 0.745939] NET: Registered PF_UNIX/PF_LOCAL protocol family
10451 10:00:22.655904 <6>[ 0.752112] RPC: Registered named UNIX socket transport module.
10452 10:00:22.658991 <6>[ 0.758265] RPC: Registered udp transport module.
10453 10:00:22.665918 <6>[ 0.763197] RPC: Registered tcp transport module.
10454 10:00:22.672280 <6>[ 0.768129] RPC: Registered tcp NFSv4.1 backchannel transport module.
10455 10:00:22.675779 <6>[ 0.774798] PCI: CLS 0 bytes, default 64
10456 10:00:22.679272 <6>[ 0.779184] Unpacking initramfs...
10457 10:00:22.700313 <6>[ 0.795320] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10458 10:00:22.710613 <6>[ 0.803981] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10459 10:00:22.713954 <6>[ 0.812835] kvm [1]: IPA Size Limit: 40 bits
10460 10:00:22.720266 <6>[ 0.817363] kvm [1]: GICv3: no GICV resource entry
10461 10:00:22.723939 <6>[ 0.822387] kvm [1]: disabling GICv2 emulation
10462 10:00:22.730240 <6>[ 0.827074] kvm [1]: GIC system register CPU interface enabled
10463 10:00:22.733779 <6>[ 0.833239] kvm [1]: vgic interrupt IRQ18
10464 10:00:22.740111 <6>[ 0.837598] kvm [1]: VHE mode initialized successfully
10465 10:00:22.746640 <5>[ 0.843870] Initialise system trusted keyrings
10466 10:00:22.753831 <6>[ 0.848660] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10467 10:00:22.760507 <6>[ 0.858607] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10468 10:00:22.766989 <5>[ 0.865000] NFS: Registering the id_resolver key type
10469 10:00:22.770439 <5>[ 0.870298] Key type id_resolver registered
10470 10:00:22.777150 <5>[ 0.874713] Key type id_legacy registered
10471 10:00:22.783821 <6>[ 0.878990] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10472 10:00:22.789939 <6>[ 0.885911] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10473 10:00:22.796958 <6>[ 0.893599] 9p: Installing v9fs 9p2000 file system support
10474 10:00:22.833770 <5>[ 0.931778] Key type asymmetric registered
10475 10:00:22.837263 <5>[ 0.936112] Asymmetric key parser 'x509' registered
10476 10:00:22.846569 <6>[ 0.941259] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10477 10:00:22.849969 <6>[ 0.948876] io scheduler mq-deadline registered
10478 10:00:22.853510 <6>[ 0.953653] io scheduler kyber registered
10479 10:00:22.872761 <6>[ 0.970806] EINJ: ACPI disabled.
10480 10:00:22.904848 <4>[ 0.996421] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10481 10:00:22.914793 <4>[ 1.007052] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10482 10:00:22.929807 <6>[ 1.027807] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10483 10:00:22.937432 <6>[ 1.035782] printk: console [ttyS0] disabled
10484 10:00:22.966041 <6>[ 1.060424] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10485 10:00:22.972256 <6>[ 1.069902] printk: console [ttyS0] enabled
10486 10:00:22.975763 <6>[ 1.069902] printk: console [ttyS0] enabled
10487 10:00:22.982046 <6>[ 1.078796] printk: bootconsole [mtk8250] disabled
10488 10:00:22.985313 <6>[ 1.078796] printk: bootconsole [mtk8250] disabled
10489 10:00:22.992303 <6>[ 1.090073] SuperH (H)SCI(F) driver initialized
10490 10:00:22.995162 <6>[ 1.095348] msm_serial: driver initialized
10491 10:00:23.009851 <6>[ 1.104325] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10492 10:00:23.019197 <6>[ 1.112873] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10493 10:00:23.025956 <6>[ 1.121416] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10494 10:00:23.035963 <6>[ 1.130045] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10495 10:00:23.042817 <6>[ 1.138753] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10496 10:00:23.052604 <6>[ 1.147474] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10497 10:00:23.062588 <6>[ 1.156016] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10498 10:00:23.069447 <6>[ 1.164836] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10499 10:00:23.079248 <6>[ 1.173381] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10500 10:00:23.091204 <6>[ 1.189048] loop: module loaded
10501 10:00:23.097289 <6>[ 1.195024] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10502 10:00:23.119858 <4>[ 1.218405] mtk-pmic-keys: Failed to locate of_node [id: -1]
10503 10:00:23.126920 <6>[ 1.225307] megasas: 07.719.03.00-rc1
10504 10:00:23.136461 <6>[ 1.234862] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10505 10:00:23.147895 <6>[ 1.246045] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10506 10:00:23.164646 <6>[ 1.262771] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10507 10:00:23.221356 <6>[ 1.313129] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10508 10:00:23.611108 <6>[ 1.709453] Freeing initrd memory: 20896K
10509 10:00:23.627064 <6>[ 1.725075] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10510 10:00:23.637456 <6>[ 1.735908] tun: Universal TUN/TAP device driver, 1.6
10511 10:00:23.640950 <6>[ 1.741975] thunder_xcv, ver 1.0
10512 10:00:23.644177 <6>[ 1.745475] thunder_bgx, ver 1.0
10513 10:00:23.647426 <6>[ 1.748970] nicpf, ver 1.0
10514 10:00:23.657864 <6>[ 1.752993] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10515 10:00:23.661451 <6>[ 1.760469] hns3: Copyright (c) 2017 Huawei Corporation.
10516 10:00:23.664688 <6>[ 1.766055] hclge is initializing
10517 10:00:23.671678 <6>[ 1.769633] e1000: Intel(R) PRO/1000 Network Driver
10518 10:00:23.677909 <6>[ 1.774762] e1000: Copyright (c) 1999-2006 Intel Corporation.
10519 10:00:23.680981 <6>[ 1.780775] e1000e: Intel(R) PRO/1000 Network Driver
10520 10:00:23.688129 <6>[ 1.785990] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10521 10:00:23.694442 <6>[ 1.792178] igb: Intel(R) Gigabit Ethernet Network Driver
10522 10:00:23.701141 <6>[ 1.797829] igb: Copyright (c) 2007-2014 Intel Corporation.
10523 10:00:23.707820 <6>[ 1.803664] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10524 10:00:23.714516 <6>[ 1.810182] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10525 10:00:23.718116 <6>[ 1.816647] sky2: driver version 1.30
10526 10:00:23.724334 <6>[ 1.821640] VFIO - User Level meta-driver version: 0.3
10527 10:00:23.732014 <6>[ 1.829868] usbcore: registered new interface driver usb-storage
10528 10:00:23.738318 <6>[ 1.836313] usbcore: registered new device driver onboard-usb-hub
10529 10:00:23.746904 <6>[ 1.845456] mt6397-rtc mt6359-rtc: registered as rtc0
10530 10:00:23.756931 <6>[ 1.850923] mt6397-rtc mt6359-rtc: setting system clock to 2023-11-24T09:58:13 UTC (1700819893)
10531 10:00:23.760311 <6>[ 1.860488] i2c_dev: i2c /dev entries driver
10532 10:00:23.776922 <6>[ 1.872152] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10533 10:00:23.797047 <6>[ 1.895149] cpu cpu0: EM: created perf domain
10534 10:00:23.800437 <6>[ 1.900059] cpu cpu4: EM: created perf domain
10535 10:00:23.807313 <6>[ 1.905635] sdhci: Secure Digital Host Controller Interface driver
10536 10:00:23.813901 <6>[ 1.912068] sdhci: Copyright(c) Pierre Ossman
10537 10:00:23.820706 <6>[ 1.917021] Synopsys Designware Multimedia Card Interface Driver
10538 10:00:23.827611 <6>[ 1.923674] sdhci-pltfm: SDHCI platform and OF driver helper
10539 10:00:23.830997 <6>[ 1.923780] mmc0: CQHCI version 5.10
10540 10:00:23.837355 <6>[ 1.933697] ledtrig-cpu: registered to indicate activity on CPUs
10541 10:00:23.844376 <6>[ 1.940629] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10542 10:00:23.850753 <6>[ 1.947688] usbcore: registered new interface driver usbhid
10543 10:00:23.854315 <6>[ 1.953511] usbhid: USB HID core driver
10544 10:00:23.860627 <6>[ 1.957707] spi_master spi0: will run message pump with realtime priority
10545 10:00:23.903369 <6>[ 1.994755] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10546 10:00:23.919125 <6>[ 2.010827] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10547 10:00:23.926722 <6>[ 2.024447] mmc0: Command Queue Engine enabled
10548 10:00:23.933339 <6>[ 2.029219] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10549 10:00:23.939512 <6>[ 2.036148] cros-ec-spi spi0.0: Chrome EC device registered
10550 10:00:23.943088 <6>[ 2.036472] mmcblk0: mmc0:0001 DA4128 116 GiB
10551 10:00:23.952941 <6>[ 2.051413] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10552 10:00:23.960736 <6>[ 2.058791] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10553 10:00:23.967164 <6>[ 2.064723] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10554 10:00:23.973457 <6>[ 2.070700] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10555 10:00:23.989229 <6>[ 2.084122] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10556 10:00:23.996802 <6>[ 2.094805] NET: Registered PF_PACKET protocol family
10557 10:00:23.999640 <6>[ 2.100194] 9pnet: Installing 9P2000 support
10558 10:00:24.006800 <5>[ 2.104758] Key type dns_resolver registered
10559 10:00:24.009462 <6>[ 2.109758] registered taskstats version 1
10560 10:00:24.016354 <5>[ 2.114146] Loading compiled-in X.509 certificates
10561 10:00:24.046714 <4>[ 2.138394] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10562 10:00:24.057109 <4>[ 2.149166] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10563 10:00:24.063515 <3>[ 2.159769] debugfs: File 'uA_load' in directory '/' already present!
10564 10:00:24.070520 <3>[ 2.166478] debugfs: File 'min_uV' in directory '/' already present!
10565 10:00:24.076930 <3>[ 2.173086] debugfs: File 'max_uV' in directory '/' already present!
10566 10:00:24.083785 <3>[ 2.179692] debugfs: File 'constraint_flags' in directory '/' already present!
10567 10:00:24.094615 <3>[ 2.189519] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10568 10:00:24.108660 <6>[ 2.207008] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10569 10:00:24.115482 <6>[ 2.213759] xhci-mtk 11200000.usb: xHCI Host Controller
10570 10:00:24.121927 <6>[ 2.219267] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10571 10:00:24.132430 <6>[ 2.227131] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10572 10:00:24.138950 <6>[ 2.236565] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10573 10:00:24.145408 <6>[ 2.242784] xhci-mtk 11200000.usb: xHCI Host Controller
10574 10:00:24.151977 <6>[ 2.248279] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10575 10:00:24.158921 <6>[ 2.255937] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10576 10:00:24.165148 <6>[ 2.263795] hub 1-0:1.0: USB hub found
10577 10:00:24.173133 <6>[ 2.267813] hub 1-0:1.0: 1 port detected
10578 10:00:24.178472 <6>[ 2.272128] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10579 10:00:24.181806 <6>[ 2.280952] hub 2-0:1.0: USB hub found
10580 10:00:24.185356 <6>[ 2.284975] hub 2-0:1.0: 1 port detected
10581 10:00:24.194382 <6>[ 2.293059] mtk-msdc 11f70000.mmc: Got CD GPIO
10582 10:00:24.207140 <6>[ 2.302057] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10583 10:00:24.214044 <6>[ 2.310092] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10584 10:00:24.223952 <4>[ 2.318017] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10585 10:00:24.233750 <6>[ 2.327589] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10586 10:00:24.240092 <6>[ 2.335667] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10587 10:00:24.247081 <6>[ 2.343684] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10588 10:00:24.256948 <6>[ 2.351597] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10589 10:00:24.263074 <6>[ 2.359415] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10590 10:00:24.272966 <6>[ 2.367230] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10591 10:00:24.283459 <6>[ 2.377607] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10592 10:00:24.290201 <6>[ 2.385967] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10593 10:00:24.299839 <6>[ 2.394318] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10594 10:00:24.306659 <6>[ 2.402656] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10595 10:00:24.316530 <6>[ 2.410999] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10596 10:00:24.323449 <6>[ 2.419338] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10597 10:00:24.333314 <6>[ 2.427676] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10598 10:00:24.340227 <6>[ 2.436015] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10599 10:00:24.350219 <6>[ 2.444353] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10600 10:00:24.356551 <6>[ 2.452692] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10601 10:00:24.366177 <6>[ 2.461031] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10602 10:00:24.373188 <6>[ 2.469370] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10603 10:00:24.383308 <6>[ 2.477709] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10604 10:00:24.389556 <6>[ 2.486048] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10605 10:00:24.399983 <6>[ 2.494386] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10606 10:00:24.406370 <6>[ 2.503028] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10607 10:00:24.413233 <6>[ 2.510174] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10608 10:00:24.419495 <6>[ 2.516939] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10609 10:00:24.426658 <6>[ 2.523700] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10610 10:00:24.433196 <6>[ 2.530630] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10611 10:00:24.442977 <6>[ 2.537486] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10612 10:00:24.452929 <6>[ 2.546613] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10613 10:00:24.462860 <6>[ 2.555732] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10614 10:00:24.472742 <6>[ 2.565027] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10615 10:00:24.479491 <6>[ 2.574497] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10616 10:00:24.489264 <6>[ 2.583966] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10617 10:00:24.498961 <6>[ 2.593087] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10618 10:00:24.509166 <6>[ 2.602554] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10619 10:00:24.518940 <6>[ 2.611672] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10620 10:00:24.529093 <6>[ 2.620965] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10621 10:00:24.538968 <6>[ 2.631126] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10622 10:00:24.548694 <6>[ 2.642728] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10623 10:00:24.595641 <6>[ 2.690944] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10624 10:00:24.750334 <6>[ 2.848854] hub 1-1:1.0: USB hub found
10625 10:00:24.753699 <6>[ 2.853393] hub 1-1:1.0: 4 ports detected
10626 10:00:24.763317 <6>[ 2.861737] hub 1-1:1.0: USB hub found
10627 10:00:24.766896 <6>[ 2.866072] hub 1-1:1.0: 4 ports detected
10628 10:00:24.875815 <6>[ 2.971271] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10629 10:00:24.902386 <6>[ 3.000947] hub 2-1:1.0: USB hub found
10630 10:00:24.906023 <6>[ 3.005442] hub 2-1:1.0: 3 ports detected
10631 10:00:24.915330 <6>[ 3.013588] hub 2-1:1.0: USB hub found
10632 10:00:24.918196 <6>[ 3.018146] hub 2-1:1.0: 3 ports detected
10633 10:00:25.091942 <6>[ 3.186989] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10634 10:00:25.224401 <6>[ 3.322880] hub 1-1.4:1.0: USB hub found
10635 10:00:25.227913 <6>[ 3.327549] hub 1-1.4:1.0: 2 ports detected
10636 10:00:25.237015 <6>[ 3.335732] hub 1-1.4:1.0: USB hub found
10637 10:00:25.240483 <6>[ 3.340329] hub 1-1.4:1.0: 2 ports detected
10638 10:00:25.304008 <6>[ 3.399196] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10639 10:00:25.535666 <6>[ 3.630986] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10640 10:00:25.727707 <6>[ 3.822985] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10641 10:00:36.824680 <6>[ 14.927969] ALSA device list:
10642 10:00:36.831699 <6>[ 14.931264] No soundcards found.
10643 10:00:36.839565 <6>[ 14.939191] Freeing unused kernel memory: 8384K
10644 10:00:36.842709 <6>[ 14.944177] Run /init as init process
10645 10:00:36.874715 Starting syslogd: OK
10646 10:00:36.879732 Starting klogd: OK
10647 10:00:36.888474 Running sysctl: OK
10648 10:00:36.898240 Populating /dev using udev: <30>[ 14.997065] udevd[185]: starting version 3.2.9
10649 10:00:36.905265 <27>[ 15.005110] udevd[185]: specified user 'tss' unknown
10650 10:00:36.912085 <27>[ 15.010583] udevd[185]: specified group 'tss' unknown
10651 10:00:36.915626 <30>[ 15.017105] udevd[186]: starting eudev-3.2.9
10652 10:00:37.070688 <6>[ 15.166884] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10653 10:00:37.086163 <6>[ 15.182477] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10654 10:00:37.098981 <6>[ 15.195319] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10655 10:00:37.122931 <6>[ 15.219235] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10656 10:00:37.129220 <6>[ 15.228976] mc: Linux media interface: v0.10
10657 10:00:37.137509 <6>[ 15.237121] remoteproc remoteproc0: scp is available
10658 10:00:37.143943 <6>[ 15.243227] remoteproc remoteproc0: powering up scp
10659 10:00:37.150916 <6>[ 15.245004] usbcore: registered new interface driver r8152
10660 10:00:37.157057 <6>[ 15.248525] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10661 10:00:37.163930 <6>[ 15.262659] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10662 10:00:37.170818 <3>[ 15.266478] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10663 10:00:37.180640 <4>[ 15.270291] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10664 10:00:37.187031 <3>[ 15.276580] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10665 10:00:37.194074 <3>[ 15.276584] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10666 10:00:37.203536 <3>[ 15.293361] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10667 10:00:37.210458 <6>[ 15.297145] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10668 10:00:37.216849 <4>[ 15.300211] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10669 10:00:37.226710 <3>[ 15.308235] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10670 10:00:37.233692 <6>[ 15.319090] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10671 10:00:37.243175 <3>[ 15.323154] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10672 10:00:37.250148 <3>[ 15.323168] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10673 10:00:37.256598 <3>[ 15.323181] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10674 10:00:37.266933 <3>[ 15.323491] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10675 10:00:37.273161 <6>[ 15.327971] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10676 10:00:37.279983 <6>[ 15.327977] pci_bus 0000:00: root bus resource [bus 00-ff]
10677 10:00:37.286959 <6>[ 15.327982] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10678 10:00:37.296798 <6>[ 15.327984] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10679 10:00:37.303984 <6>[ 15.328010] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10680 10:00:37.311063 <6>[ 15.328023] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10681 10:00:37.314576 <6>[ 15.328086] pci 0000:00:00.0: supports D1 D2
10682 10:00:37.320957 <6>[ 15.328087] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10683 10:00:37.331044 <6>[ 15.328980] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10684 10:00:37.334283 <6>[ 15.329070] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10685 10:00:37.344319 <6>[ 15.329095] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10686 10:00:37.351092 <6>[ 15.329110] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10687 10:00:37.357386 <6>[ 15.329125] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10688 10:00:37.363800 <6>[ 15.329232] pci 0000:01:00.0: supports D1 D2
10689 10:00:37.371090 <6>[ 15.329233] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10690 10:00:37.377913 <4>[ 15.332292] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10691 10:00:37.384650 <4>[ 15.332292] Fallback method does not support PEC.
10692 10:00:37.391044 <3>[ 15.338751] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10693 10:00:37.398086 <6>[ 15.342810] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10694 10:00:37.407935 <6>[ 15.342886] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10695 10:00:37.414839 <6>[ 15.342893] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10696 10:00:37.424413 <6>[ 15.342906] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10697 10:00:37.431361 <6>[ 15.342923] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10698 10:00:37.437727 <6>[ 15.342939] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10699 10:00:37.444708 <6>[ 15.342956] pci 0000:00:00.0: PCI bridge to [bus 01]
10700 10:00:37.451033 <6>[ 15.342964] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10701 10:00:37.457541 <6>[ 15.343179] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10702 10:00:37.467372 <6>[ 15.343276] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10703 10:00:37.477292 <6>[ 15.343628] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10704 10:00:37.484400 <6>[ 15.344855] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10705 10:00:37.490636 <6>[ 15.345230] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10706 10:00:37.497277 <4>[ 15.354567] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10707 10:00:37.506923 <3>[ 15.354744] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10708 10:00:37.513887 <4>[ 15.363279] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10709 10:00:37.524103 <3>[ 15.370920] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10710 10:00:37.530341 <3>[ 15.371118] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10711 10:00:37.540300 <3>[ 15.371126] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10712 10:00:37.547032 <3>[ 15.371129] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10713 10:00:37.556954 <3>[ 15.371140] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10714 10:00:37.563406 <3>[ 15.371145] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10715 10:00:37.570502 <3>[ 15.371187] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10716 10:00:37.577172 <6>[ 15.378652] videodev: Linux video capture interface: v2.00
10717 10:00:37.586512 <6>[ 15.393738] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10718 10:00:37.593736 <6>[ 15.393738] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10719 10:00:37.599829 <3>[ 15.417604] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10720 10:00:37.606640 <6>[ 15.419237] remoteproc remoteproc0: remote processor scp is now up
10721 10:00:37.616877 <6>[ 15.430104] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10722 10:00:37.623390 <6>[ 15.438978] r8152 2-1.3:1.0 eth0: v1.12.13
10723 10:00:37.626803 <6>[ 15.465712] usbcore: registered new interface driver cdc_ether
10724 10:00:37.633634 <6>[ 15.465756] Bluetooth: Core ver 2.22
10725 10:00:37.636309 <6>[ 15.465837] NET: Registered PF_BLUETOOTH protocol family
10726 10:00:37.643437 <6>[ 15.465839] Bluetooth: HCI device and connection manager initialized
10727 10:00:37.649598 <6>[ 15.465861] Bluetooth: HCI socket layer initialized
10728 10:00:37.653319 <6>[ 15.465866] Bluetooth: L2CAP socket layer initialized
10729 10:00:37.659635 <6>[ 15.465876] Bluetooth: SCO socket layer initialized
10730 10:00:37.666072 <6>[ 15.498605] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10731 10:00:37.672967 <5>[ 15.499090] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10732 10:00:37.682411 <6>[ 15.505414] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10733 10:00:37.689710 <6>[ 15.512227] usbcore: registered new interface driver r8153_ecm
10734 10:00:37.695739 <3>[ 15.520458] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10735 10:00:37.709309 <6>[ 15.521822] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10736 10:00:37.715666 <6>[ 15.522048] usbcore: registered new interface driver uvcvideo
10737 10:00:37.722661 <6>[ 15.522144] usbcore: registered new interface driver btusb
10738 10:00:37.728994 <5>[ 15.525246] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10739 10:00:37.735871 <4>[ 15.525387] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10740 10:00:37.742658 <6>[ 15.525396] cfg80211: failed to load regulatory.db
10741 10:00:37.752225 <4>[ 15.526545] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10742 10:00:37.758773 <3>[ 15.526567] Bluetooth: hci0: Failed to load firmware file (-2)
10743 10:00:37.765596 <3>[ 15.526574] Bluetooth: hci0: Failed to set up firmware (-2)
10744 10:00:37.775074 <4>[ 15.526580] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10745 10:00:37.782163 <6>[ 15.528719] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10746 10:00:37.789082 <6>[ 15.538350] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10747 10:00:37.799071 <6>[ 15.600538] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10748 10:00:37.805202 <6>[ 15.902394] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10749 10:00:37.827054 <6>[ 15.926869] mt7921e 0000:01:00.0: ASIC revision: 79610010
10750 10:00:37.933817 <4>[ 16.027305] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10751 10:00:37.933975 done
10752 10:00:37.956175 Saving random seed: OK
10753 10:00:37.971464 Starting network: OK
10754 10:00:38.008774 Starting dropbear sshd: <6>[ 16.108570] NET: Registered PF_INET6 protocol family
10755 10:00:38.015214 <6>[ 16.114764] Segment Routing with IPv6
10756 10:00:38.018850 <6>[ 16.118713] In-situ OAM (IOAM) with IPv6
10757 10:00:38.021745 OK
10758 10:00:38.031022 /bin/sh: can't access tty; job control turned off
10759 10:00:38.031379 Matched prompt #10: / #
10761 10:00:38.031596 Setting prompt string to ['/ #']
10762 10:00:38.031690 end: 2.2.5.1 login-action (duration 00:00:17) [common]
10764 10:00:38.031888 end: 2.2.5 auto-login-action (duration 00:00:17) [common]
10765 10:00:38.031979 start: 2.2.6 expect-shell-connection (timeout 00:03:45) [common]
10766 10:00:38.032051 Setting prompt string to ['/ #']
10767 10:00:38.032113 Forcing a shell prompt, looking for ['/ #']
10769 10:00:38.082335 / #
10770 10:00:38.082478 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10771 10:00:38.082561 Waiting using forced prompt support (timeout 00:02:30)
10772 10:00:38.082662 <4>[ 16.149225] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10773 10:00:38.087508
10774 10:00:38.087841 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10775 10:00:38.087980 start: 2.2.7 export-device-env (timeout 00:03:45) [common]
10776 10:00:38.088128 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10777 10:00:38.088269 end: 2.2 depthcharge-retry (duration 00:01:15) [common]
10778 10:00:38.088402 end: 2 depthcharge-action (duration 00:01:15) [common]
10779 10:00:38.088533 start: 3 lava-test-retry (timeout 00:01:00) [common]
10780 10:00:38.088665 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10781 10:00:38.088792 Using namespace: common
10783 10:00:38.189175 / # #
10784 10:00:38.189336 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10785 10:00:38.189471 #<4>[ 16.269451] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10786 10:00:38.193980
10787 10:00:38.194258 Using /lava-12073268
10789 10:00:38.294561 / # export SHELL=/bin/sh
10790 10:00:38.295980 export SHELL=/bin/sh<4>[ 16.389333] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10791 10:00:38.337659
10793 10:00:38.438277 / # . /lava-12073268/environment
10794 10:00:38.438525 . /lava-12073268/environment<4>[ 16.509730] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10795 10:00:38.443648
10797 10:00:38.544255 / # /lava-12073268/bin/lava-test-runner /lava-12073268/0
10798 10:00:38.544414 Test shell timeout: 10s (minimum of the action and connection timeout)
10799 10:00:38.544754 /lava-12073268/bin/lava-test-runner /lava-12073268/0<4>[ 16.629816] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10800 10:00:38.550409
10801 10:00:38.593640 + export 'TESTRUN_ID=0_dmesg'
10802 10:00:38.593768 +<8>[ 16.676687] <LAVA_SIGNAL_STARTRUN 0_dmesg 12073268_1.5.2.3.1>
10803 10:00:38.593839 cd /lava-12073268/0/tests/0_dmesg
10804 10:00:38.593901 + cat uuid
10805 10:00:38.593975 + UUID=12073268_1.5.2.3.1
10806 10:00:38.594049 + set +x
10807 10:00:38.594288 Received signal: <STARTRUN> 0_dmesg 12073268_1.5.2.3.1
10808 10:00:38.594361 Starting test lava.0_dmesg (12073268_1.5.2.3.1)
10809 10:00:38.594448 Skipping test definition patterns.
10810 10:00:38.594555 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
10811 10:00:38.598316 <8>[ 16.695573] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
10812 10:00:38.598586 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
10814 10:00:38.619357 <8>[ 16.715786] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
10815 10:00:38.619626 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
10817 10:00:38.644939 <8>[ 16.741672] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
10818 10:00:38.645224 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
10820 10:00:38.658353 <4>[ 16.750724] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10821 10:00:38.658496 + set +x
10822 10:00:38.664830 <8>[ 16.762198] <LAVA_SIGNAL_ENDRUN 0_dmesg 12073268_1.5.2.3.1>
10823 10:00:38.665098 Received signal: <ENDRUN> 0_dmesg 12073268_1.5.2.3.1
10824 10:00:38.665187 Ending use of test pattern.
10825 10:00:38.665255 Ending test lava.0_dmesg (12073268_1.5.2.3.1), duration 0.07
10827 10:00:38.668284 <LAVA_TEST_RUNNER EXIT>
10828 10:00:38.668563 ok: lava_test_shell seems to have completed
10829 10:00:38.668705 alert: pass
crit: pass
emerg: pass
10830 10:00:38.668832 end: 3.1 lava-test-shell (duration 00:00:01) [common]
10831 10:00:38.668964 end: 3 lava-test-retry (duration 00:00:01) [common]
10832 10:00:38.669090 start: 4 lava-test-retry (timeout 00:01:00) [common]
10833 10:00:38.669218 start: 4.1 lava-test-shell (timeout 00:01:00) [common]
10834 10:00:38.669323 Using namespace: common
10836 10:00:38.769698 / # #
10837 10:00:38.769856 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10838 10:00:38.770009 Using /lava-12073268
10840 10:00:38.870358 export SHELL=/bin/sh
10841 10:00:38.870600 #<4>[ 16.869489] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10842 10:00:38.870711
10844 10:00:38.971249 / # export SHELL=/bin/sh. /lava-12073268/environment
10845 10:00:38.971448
10846 10:00:38.971530 / # <4>[ 16.989874] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10848 10:00:39.072018 . /lava-12073268/environment/lava-12073268/bin/lava-test-runner /lava-12073268/1
10849 10:00:39.072213 Test shell timeout: 10s (minimum of the action and connection timeout)
10850 10:00:39.072371
10851 10:00:39.072458 / # <4>[ 17.109533] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10852 10:00:39.077369 /lava-12073268/bin/lava-test-runner /lava-12073268/1
10853 10:00:39.117671 + export 'TESTRUN_ID=1_bootrr'
10854 10:00:39.117827 <8>[ 17.203934] <LAVA_SIGNAL_STARTRUN 1_bootrr 12073268_1.5.2.3.5>
10855 10:00:39.117939 + cd /lava-12073268/1/tests/1_bootrr
10856 10:00:39.118043 + cat uuid
10857 10:00:39.118147 + UUID=12073268_1.5.2.3.5
10858 10:00:39.118250 + set +x
10859 10:00:39.118534 Received signal: <STARTRUN> 1_bootrr 12073268_1.5.2.3.5
10860 10:00:39.118633 Starting test lava.1_bootrr (12073268_1.5.2.3.5)
10861 10:00:39.118764 Skipping test definition patterns.
10862 10:00:39.121429 + export 'PATH=/opt/bootrr/libexec/bootrr/helpers:/lava-12073268/1/../bin:/sbin:/usr/sbin:/bin:/usr/bin'
10863 10:00:39.127850 + cd /opt/bootr<3>[ 17.227715] mt7921e 0000:01:00.0: hardware init failed
10864 10:00:39.131336 r/libexec/bootrr
10865 10:00:39.131454 + sh helpers/bootrr-auto
10866 10:00:39.142611 /lava-12073268/1/../bin/lava-test-case
10867 10:00:39.149085 <8>[ 17.247683] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=deferred-probe-empty RESULT=pass>
10868 10:00:39.149400 Received signal: <TESTCASE> TEST_CASE_ID=deferred-probe-empty RESULT=pass
10870 10:00:39.168219 /lava-12073268/1/../bin/lava-test-case
10871 10:00:39.174108 <8>[ 17.271677] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=all-cpus-are-online RESULT=pass>
10872 10:00:39.174406 Received signal: <TESTCASE> TEST_CASE_ID=all-cpus-are-online RESULT=pass
10874 10:00:39.179609 /usr/bin/tpm2_getcap
10875 10:00:39.214353 /lava-12073268/1/../bin/lava-test-case
10876 10:00:39.224218 <8>[ 17.320543] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm-chip-is-online RESULT=pass>
10877 10:00:39.224539 Received signal: <TESTCASE> TEST_CASE_ID=tpm-chip-is-online RESULT=pass
10879 10:00:39.241990 /lava-12073268/1/../bin/lava-test-case
10880 10:00:39.248383 <8>[ 17.345255] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass>
10881 10:00:39.248700 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass
10883 10:00:39.260382 /lava-12073268/1/../bin/lava-test-case
10884 10:00:39.267135 <8>[ 17.363480] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass>
10885 10:00:39.267433 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass
10887 10:00:39.278364 /lava-12073268/1/../bin/lava-test-case
10888 10:00:39.284807 <8>[ 17.381714] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass>
10889 10:00:39.285101 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass
10891 10:00:39.298630 /lava-12073268/1/../bin/lava-test-case
10892 10:00:39.305299 <8>[ 17.401650] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass>
10893 10:00:39.305601 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass
10895 10:00:39.320071 /lava-12073268/1/../bin/lava-test-case
10896 10:00:39.330198 <8>[ 17.425514] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass>
10897 10:00:39.330504 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass
10899 10:00:39.338702 /lava-12073268/1/../bin/lava-test-case
10900 10:00:39.344992 <8>[ 17.441926] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass>
10901 10:00:39.345292 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass
10903 10:00:39.357756 /lava-12073268/1/../bin/lava-test-case
10904 10:00:39.364082 <8>[ 17.461026] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass>
10905 10:00:39.364381 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass
10907 10:00:39.373004 /lava-12073268/1/../bin/lava-test-case
10908 10:00:39.379738 <8>[ 17.476898] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass>
10909 10:00:39.380037 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass
10911 10:00:39.392422 /lava-12073268/1/../bin/lava-test-case
10912 10:00:39.398951 <8>[ 17.496637] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass>
10913 10:00:39.399267 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass
10915 10:00:39.410912 /lava-12073268/1/../bin/lava-test-case
10916 10:00:39.417923 <8>[ 17.515293] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass>
10917 10:00:39.418225 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass
10919 10:00:39.431619 /lava-12073268/1/../bin/lava-test-case
10920 10:00:39.441453 <8>[ 17.538381] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass>
10921 10:00:39.441789 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass
10923 10:00:39.453096 /lava-12073268/1/../bin/lava-test-case
10924 10:00:39.459464 <8>[ 17.556921] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass>
10925 10:00:39.459743 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass
10927 10:00:39.469597 /lava-12073268/1/../bin/lava-test-case
10928 10:00:39.476020 <8>[ 17.573051] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass>
10929 10:00:39.476331 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass
10931 10:00:39.489421 /lava-12073268/1/../bin/lava-test-case
10932 10:00:39.495663 <8>[ 17.592042] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass>
10933 10:00:39.495969 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass
10935 10:00:39.504716 /lava-12073268/1/../bin/lava-test-case
10936 10:00:39.510987 <8>[ 17.608339] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass>
10937 10:00:39.511323 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass
10939 10:00:39.522606 /lava-12073268/1/../bin/lava-test-case
10940 10:00:39.531931 <8>[ 17.628473] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass>
10941 10:00:39.532252 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass
10943 10:00:39.539501 /lava-12073268/1/../bin/lava-test-case
10944 10:00:39.546474 <8>[ 17.644566] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass>
10945 10:00:39.546790 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass
10947 10:00:39.559671 /lava-12073268/1/../bin/lava-test-case
10948 10:00:39.565947 <8>[ 17.662918] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-probed RESULT=pass>
10949 10:00:39.566248 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-probed RESULT=pass
10951 10:00:39.576022 /lava-12073268/1/../bin/lava-test-case
10952 10:00:39.582445 <8>[ 17.680348] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass>
10953 10:00:39.582745 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass
10955 10:00:39.594928 /lava-12073268/1/../bin/lava-test-case
10956 10:00:39.601518 <8>[ 17.699934] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass>
10957 10:00:39.601852 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass
10959 10:00:39.611962 /lava-12073268/1/../bin/lava-test-case
10960 10:00:39.618368 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass
10962 10:00:39.621659 <8>[ 17.716644] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass>
10963 10:00:39.632120 /lava-12073268/1/../bin/lava-test-case
10964 10:00:39.639266 <8>[ 17.736544] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass>
10965 10:00:39.639566 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass
10967 10:00:39.651092 /lava-12073268/1/../bin/lava-test-case
10968 10:00:39.657414 <8>[ 17.754383] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass>
10969 10:00:39.657708 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass
10971 10:00:39.666594 /lava-12073268/1/../bin/lava-test-case
10972 10:00:39.672830 <8>[ 17.770031] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass>
10973 10:00:39.673094 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass
10975 10:00:39.684220 /lava-12073268/1/../bin/lava-test-case
10976 10:00:39.691254 <8>[ 17.789163] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass>
10977 10:00:39.691554 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass
10979 10:00:39.700260 /lava-12073268/1/../bin/lava-test-case
10980 10:00:39.710742 <8>[ 17.807635] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass>
10981 10:00:39.711045 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass
10983 10:00:39.723074 /lava-12073268/1/../bin/lava-test-case
10984 10:00:39.733596 <8>[ 17.830020] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass>
10985 10:00:39.733875 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass
10987 10:00:39.745077 /lava-12073268/1/../bin/lava-test-case
10988 10:00:39.751847 <8>[ 17.848959] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass>
10989 10:00:39.752163 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass
10991 10:00:39.763057 /lava-12073268/1/../bin/lava-test-case
10992 10:00:39.769490 <8>[ 17.866158] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass>
10993 10:00:39.769801 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass
10995 10:00:39.782985 /lava-12073268/1/../bin/lava-test-case
10996 10:00:39.789214 <8>[ 17.885325] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass>
10997 10:00:39.789512 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass
10999 10:00:39.798466 /lava-12073268/1/../bin/lava-test-case
11000 10:00:39.804820 <8>[ 17.902719] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass>
11001 10:00:39.805118 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass
11003 10:00:39.825999 /lava-12073268/1/../bin/lava-tes<8>[ 17.922094] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass>
11004 10:00:39.826145 t-case
11005 10:00:39.826438 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass
11007 10:00:39.835147 /lava-12073268/1/../bin/lava-test-case
11008 10:00:39.845673 <8>[ 17.942305] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass>
11009 10:00:39.845958 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass
11011 10:00:39.854124 /lava-12073268/1/../bin/lava-test-case
11012 10:00:39.860238 <8>[ 17.958495] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass>
11013 10:00:39.860558 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass
11015 10:00:39.873229 /lava-12073268/1/../bin/lava-test-case
11016 10:00:39.880205 <8>[ 17.976589] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass>
11017 10:00:39.880472 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass
11019 10:00:39.887890 /lava-12073268/1/../bin/lava-test-case
11020 10:00:39.894700 <8>[ 17.992014] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass>
11021 10:00:39.894998 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass
11023 10:00:39.906636 /lava-12073268/1/../bin/lava-test-case
11024 10:00:39.913072 <8>[ 18.009489] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass>
11025 10:00:39.913362 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass
11027 10:00:39.922057 /lava-12073268/1/../bin/lava-test-case
11028 10:00:39.928963 <8>[ 18.026488] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass>
11029 10:00:39.929251 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass
11031 10:00:39.941317 /lava-12073268/1/../bin/lava-test-case
11032 10:00:39.947734 <8>[ 18.044767] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass>
11033 10:00:39.948055 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass
11035 10:00:39.958372 /lava-12073268/1/../bin/lava-test-case
11036 10:00:39.964518 <8>[ 18.061025] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass>
11037 10:00:39.964834 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass
11039 10:00:39.977363 /lava-12073268/1/../bin/lava-test-case
11040 10:00:39.983846 <8>[ 18.081565] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-probed RESULT=pass>
11041 10:00:39.984144 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-probed RESULT=pass
11043 10:00:39.994236 /lava-12073268/1/../bin/lava-test-case
11044 10:00:40.000559 <8>[ 18.097775] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass>
11045 10:00:40.000857 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass
11047 10:00:40.012245 /lava-12073268/1/../bin/lava-test-case
11048 10:00:40.018608 <8>[ 18.115850] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass>
11049 10:00:40.018874 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass
11051 10:00:40.027726 /lava-12073268/1/../bin/lava-test-case
11052 10:00:40.034398 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass
11054 10:00:40.036957 <8>[ 18.132860] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass>
11055 10:00:40.046365 /lava-12073268/1/../bin/lava-test-case
11056 10:00:40.052970 <8>[ 18.149679] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-probed RESULT=pass>
11057 10:00:40.053233 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-probed RESULT=pass
11059 10:00:40.060693 /lava-12073268/1/../bin/lava-test-case
11060 10:00:40.070455 <8>[ 18.166046] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass>
11061 10:00:40.070723 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass
11063 10:00:40.080334 /lava-12073268/1/../bin/lava-test-case
11064 10:00:40.087039 <8>[ 18.184797] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass>
11065 10:00:40.087319 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass
11067 10:00:40.098925 /lava-12073268/1/../bin/lava-test-case
11068 10:00:40.105230 <8>[ 18.202820] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass>
11069 10:00:40.105484 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass
11071 10:00:40.114771 /lava-12073268/1/../bin/lava-test-case
11072 10:00:40.121869 <8>[ 18.219328] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass>
11073 10:00:40.122133 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass
11075 10:00:40.133128 /lava-12073268/1/../bin/lava-test-case
11076 10:00:40.139986 <8>[ 18.237246] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass>
11077 10:00:40.140271 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass
11079 10:00:40.148397 /lava-12073268/1/../bin/lava-test-case
11080 10:00:40.155262 <8>[ 18.252514] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass>
11081 10:00:40.155559 Received signal: <TESTCASE> TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass
11083 10:00:40.172382 /lava-12073268/1/../bin/lava-tes<8>[ 18.268801] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass>
11084 10:00:40.172516 t-case
11085 10:00:40.172790 Received signal: <TESTCASE> TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass
11087 10:00:40.184912 /lava-12073268/1/../bin/lava-test-case
11088 10:00:40.191865 <8>[ 18.289704] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass>
11089 10:00:40.192150 Received signal: <TESTCASE> TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass
11091 10:00:40.205075 /lava-12073268/1/../bin/lava-test-case
11092 10:00:40.214916 <8>[ 18.311188] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass>
11093 10:00:40.215207 Received signal: <TESTCASE> TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass
11095 10:00:40.227292 /lava-12073268/1/../bin/lava-test-case
11096 10:00:40.233979 <8>[ 18.330542] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass>
11097 10:00:40.234270 Received signal: <TESTCASE> TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass
11099 10:00:40.252779 /lava-12073268/1/../bin/lava-tes<8>[ 18.348642] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass>
11100 10:00:40.252875 t-case
11101 10:00:40.253118 Received signal: <TESTCASE> TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass
11103 10:00:40.268034 /lava-12073268/1/../bin/lava-tes<8>[ 18.364572] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-driver-present RESULT=pass>
11104 10:00:40.268149 t-case
11105 10:00:40.268440 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-driver-present RESULT=pass
11107 10:00:40.280647 /lava-12073268/1/../bin/lava-test-case
11108 10:00:40.287092 <8>[ 18.383248] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi1-probed RESULT=pass>
11109 10:00:40.287378 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi1-probed RESULT=pass
11111 10:00:40.298095 /lava-12073268/1/../bin/lava-test-case
11112 10:00:40.304280 <8>[ 18.402402] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi5-probed RESULT=pass>
11113 10:00:40.304569 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi5-probed RESULT=pass
11115 10:00:40.313298 /lava-12073268/1/../bin/lava-test-case
11116 10:00:40.320193 <8>[ 18.416929] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass>
11117 10:00:40.320481 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass
11119 10:00:40.332361 /lava-12073268/1/../bin/lava-test-case
11120 10:00:40.342550 <8>[ 18.438766] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-probed RESULT=pass>
11121 10:00:40.342850 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-probed RESULT=pass
11123 10:00:40.350136 /lava-12073268/1/../bin/lava-test-case
11124 10:00:40.360468 <8>[ 18.457185] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass>
11125 10:00:40.360761 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass
11127 10:00:40.372110 /lava-12073268/1/../bin/lava-test-case
11128 10:00:40.378388 <8>[ 18.475266] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-probed RESULT=pass>
11129 10:00:40.378649 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-probed RESULT=pass
11131 10:00:40.387705 /lava-12073268/1/../bin/lava-test-case
11132 10:00:40.394457 <8>[ 18.491709] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass>
11133 10:00:40.394708 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass
11135 10:00:40.405300 /lava-12073268/1/../bin/lava-test-case
11136 10:00:40.412131 <8>[ 18.509058] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass>
11137 10:00:40.412410 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass
11139 10:00:40.423123 /lava-12073268/1/../bin/lava-test-case
11140 10:00:40.430115 <8>[ 18.528648] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass>
11141 10:00:40.430374 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass
11143 10:00:40.442829 /lava-12073268/1/../bin/lava-test-case
11144 10:00:40.449694 <8>[ 18.545988] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass>
11145 10:00:40.449985 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass
11147 10:00:40.470429 /lava-12073268/1/../bin/lava-tes<8>[ 18.566291] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass>
11148 10:00:40.470523 t-case
11149 10:00:40.470763 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass
11151 10:00:40.480947 /lava-12073268/1/../bin/lava-test-case
11152 10:00:40.487560 <8>[ 18.584014] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass>
11153 10:00:40.487822 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass
11155 10:00:40.499681 /lava-12073268/1/../bin/lava-test-case
11156 10:00:40.506058 <8>[ 18.604972] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass>
11157 10:00:40.506323 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass
11159 10:00:40.517832 /lava-12073268/1/../bin/lava-test-case
11160 10:00:40.524797 <8>[ 18.622688] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass>
11161 10:00:40.525106 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass
11163 10:00:40.536810 /lava-12073268/1/../bin/lava-test-case
11164 10:00:40.543506 <8>[ 18.640506] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass>
11165 10:00:40.543778 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass
11167 10:00:40.554321 /lava-12073268/1/../bin/lava-test-case
11168 10:00:40.561183 <8>[ 18.659905] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass>
11169 10:00:40.561453 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass
11171 10:00:40.573773 /lava-12073268/1/../bin/lava-test-case
11172 10:00:40.580331 <8>[ 18.676950] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass>
11173 10:00:40.580591 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass
11175 10:00:40.595736 /lava-12073268/1/../bin/lava-test-case
11176 10:00:40.602318 <8>[ 18.698941] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass>
11177 10:00:40.602604 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass
11179 10:00:40.612326 /lava-12073268/1/../bin/lava-test-case
11180 10:00:40.619290 <8>[ 18.716801] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass>
11181 10:00:40.619554 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass
11183 10:00:40.638635 /lava-12073268/1/../bin/lava-tes<8>[ 18.734505] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass>
11184 10:00:40.638757 t-case
11185 10:00:40.639039 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass
11187 10:00:40.647837 /lava-12073268/1/../bin/lava-test-case
11188 10:00:40.654671 <8>[ 18.751906] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass>
11189 10:00:40.654958 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass
11191 10:00:40.667278 /lava-12073268/1/../bin/lava-test-case
11192 10:00:40.674114 <8>[ 18.770296] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass>
11193 10:00:40.674393 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass
11195 10:00:40.682963 /lava-12073268/1/../bin/lava-test-case
11196 10:00:40.689742 <8>[ 18.786660] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass>
11197 10:00:40.689992 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass
11199 10:00:40.700917 /lava-12073268/1/../bin/lava-test-case
11200 10:00:40.707711 <8>[ 18.804518] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-probed RESULT=pass>
11201 10:00:40.707996 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-probed RESULT=pass
11203 10:00:40.716964 /lava-12073268/1/../bin/lava-test-case
11204 10:00:40.723608 <8>[ 18.820338] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass>
11205 10:00:40.723865 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass
11207 10:00:40.735859 /lava-12073268/1/../bin/lava-test-case
11208 10:00:40.742305 <8>[ 18.840715] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-probed RESULT=pass>
11209 10:00:40.742595 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-probed RESULT=pass
11211 10:00:40.752385 /lava-12073268/1/../bin/lava-test-case
11212 10:00:40.759019 <8>[ 18.855666] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass>
11213 10:00:40.759301 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass
11215 10:00:40.772962 /lava-12073268/1/../bin/lava-test-case
11216 10:00:40.779126 <8>[ 18.876124] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass>
11217 10:00:40.779379 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass
11219 10:00:40.787946 /lava-12073268/1/../bin/lava-test-case
11220 10:00:40.794685 <8>[ 18.892579] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass>
11221 10:00:40.794943 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass
11223 10:00:40.809238 /lava-12073268/1/../bin/lava-test-case
11224 10:00:40.815253 <8>[ 18.911778] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-probed RESULT=pass>
11225 10:00:40.815509 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-probed RESULT=pass
11227 10:00:40.825916 /lava-12073268/1/../bin/lava-test-case
11228 10:00:40.832645 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass
11230 10:00:40.835845 <8>[ 18.931336] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass>
11231 10:00:40.846361 /lava-12073268/1/../bin/lava-test-case
11232 10:00:40.852522 <8>[ 18.949813] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass>
11233 10:00:40.852815 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass
11235 10:00:40.862895 /lava-12073268/1/../bin/lava-test-case
11236 10:00:40.869529 <8>[ 18.966158] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass>
11237 10:00:40.869821 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass
11239 10:00:40.889622 /lava-12073268/1/../bin/lava-tes<8>[ 18.985986] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass>
11240 10:00:40.889743 t-case
11241 10:00:40.890018 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass
11243 10:00:40.901555 /lava-12073268/1/../bin/lava-test-case
11244 10:00:40.907869 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass
11246 10:00:40.911072 <8>[ 19.006778] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass>
11247 10:00:40.918510 /lava-12073268/1/../bin/lava-test-case
11248 10:00:40.924764 <8>[ 19.022865] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass>
11249 10:00:40.925085 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass
11251 10:00:40.936921 /lava-12073268/1/../bin/lava-test-case
11252 10:00:40.943700 <8>[ 19.041496] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass>
11253 10:00:40.943974 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass
11255 10:00:40.952964 /lava-12073268/1/../bin/lava-test-case
11256 10:00:40.959881 <8>[ 19.057921] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-driver-present RESULT=pass>
11257 10:00:40.960169 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-driver-present RESULT=pass
11259 10:00:40.971984 /lava-12073268/1/../bin/lava-test-case
11260 10:00:40.978276 <8>[ 19.075753] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-probed RESULT=pass>
11261 10:00:40.978556 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-probed RESULT=pass
11263 10:00:40.986733 /lava-12073268/1/../bin/lava-test-case
11264 10:00:40.993671 <8>[ 19.091766] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-driver-present RESULT=pass>
11265 10:00:40.993927 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-driver-present RESULT=pass
11267 10:00:42.008357 /lava-12073268/1/../bin/lava-test-case
11268 10:00:42.015362 <8>[ 20.113053] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-probed RESULT=fail>
11269 10:00:42.015651 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-probed RESULT=fail
11271 10:00:42.024908 /lava-12073268/1/../bin/lava-test-case
11272 10:00:42.031793 <8>[ 20.128423] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-driver-present RESULT=pass>
11273 10:00:42.032073 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-driver-present RESULT=pass
11275 10:00:43.046067 /lava-12073268/1/../bin/lava-test-case
11276 10:00:43.051735 <8>[ 21.149555] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-probed RESULT=fail>
11277 10:00:43.052007 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-probed RESULT=fail
11279 10:00:43.070013 /lava-12073268/1/../bin/lava-tes<8>[ 21.166652] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass>
11280 10:00:43.070118 t-case
11281 10:00:43.070363 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass
11283 10:00:44.085062 /lava-12073268/1/../bin/lava-test-case
11284 10:00:44.091222 <8>[ 22.190456] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail>
11285 10:00:44.091521 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail
11287 10:00:44.101904 /lava-12073268/1/../bin/lava-test-case
11288 10:00:44.108352 <8>[ 22.205757] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass>
11289 10:00:44.108619 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass
11291 10:00:45.121002 /lava-12073268/1/../bin/lava-test-case
11292 10:00:45.127805 <8>[ 23.227057] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-probed RESULT=fail>
11293 10:00:45.128072 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-probed RESULT=fail
11295 10:00:45.145086 /lava-12073268/1/../bin/lava-tes<8>[ 23.241741] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-driver-present RESULT=pass>
11296 10:00:45.145182 t-case
11297 10:00:45.145421 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-driver-present RESULT=pass
11299 10:00:46.160781 /lava-12073268/1/../bin/lava-test-case
11300 10:00:46.167039 <8>[ 24.265319] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-3-probed RESULT=fail>
11301 10:00:46.167380 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-3-probed RESULT=fail
11303 10:00:46.176694 /lava-12073268/1/../bin/lava-test-case
11304 10:00:46.183154 <8>[ 24.280588] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass>
11305 10:00:46.183475 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass
11307 10:00:47.198452 /lava-12073268/1/../bin/lava-test-case
11308 10:00:47.204958 <8>[ 25.302378] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail>
11309 10:00:47.205236 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail
11311 10:00:47.214786 /lava-12073268/1/../bin/lava-test-case
11312 10:00:47.221833 <8>[ 25.320023] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass>
11313 10:00:47.222096 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass
11315 10:00:48.236849 /lava-12073268/1/../bin/lava-test-case
11316 10:00:48.243233 <8>[ 26.341126] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-probed RESULT=fail>
11317 10:00:48.243527 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-probed RESULT=fail
11319 10:00:48.261310 /lava-12073268/1/../bin/lava-tes<8>[ 26.358453] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-edp-driver-present RESULT=pass>
11320 10:00:48.261438 t-case
11321 10:00:48.261708 Received signal: <TESTCASE> TEST_CASE_ID=panel-edp-driver-present RESULT=pass
11323 10:00:48.269279 /lava-12073268/1/../bin/lava-test-case
11324 10:00:48.276004 <8>[ 26.373863] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass>
11325 10:00:48.276268 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass
11327 10:00:49.290659 /lava-12073268/1/../bin/lava-test-case
11328 10:00:49.297365 <8>[ 27.395241] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail>
11329 10:00:49.297650 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail
11331 10:00:49.316120 /lava-12073268/1/../bin/lava-tes<8>[ 27.413130] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass>
11332 10:00:49.316205 t-case
11333 10:00:49.316473 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass
11335 10:00:49.333824 /lava-12073268/1/../bin/lava-tes<8>[ 27.430487] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-probed RESULT=pass>
11336 10:00:49.333956 t-case
11337 10:00:49.334241 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-probed RESULT=pass
11339 10:00:49.342919 /lava-12073268/1/../bin/lava-test-case
11340 10:00:49.349639 <8>[ 27.446975] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass>
11341 10:00:49.349933 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass
11343 10:00:49.360586 /lava-12073268/1/../bin/lava-test-case
11344 10:00:49.367278 <8>[ 27.466647] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass>
11345 10:00:49.367574 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass
11347 10:00:49.379025 /lava-12073268/1/../bin/lava-test-case
11348 10:00:49.389266 <8>[ 27.486085] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass>
11349 10:00:49.389537 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass
11351 10:00:49.398585 /lava-12073268/1/../bin/lava-test-case
11352 10:00:49.405753 <8>[ 27.504509] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass>
11353 10:00:49.406019 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass
11355 10:00:49.415671 /lava-12073268/1/../bin/lava-test-case
11356 10:00:49.422366 <8>[ 27.520939] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass>
11357 10:00:49.422628 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass
11359 10:00:49.434655 /lava-12073268/1/../bin/lava-test-case
11360 10:00:49.441328 <8>[ 27.539430] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass>
11361 10:00:49.441595 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass
11363 10:00:49.452710 /lava-12073268/1/../bin/lava-test-case
11364 10:00:49.462444 <8>[ 27.559204] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass>
11365 10:00:49.462711 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass
11367 10:00:49.470110 /lava-12073268/1/../bin/lava-test-case
11368 10:00:49.476622 <8>[ 27.575076] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass>
11369 10:00:49.476882 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass
11371 10:00:49.486141 /lava-12073268/1/../bin/lava-test-case
11372 10:00:49.496245 <8>[ 27.594147] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass>
11373 10:00:49.496505 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass
11375 10:00:49.506544 /lava-12073268/1/../bin/lava-test-case
11376 10:00:49.512950 <8>[ 27.611170] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass>
11377 10:00:49.513220 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass
11379 10:00:49.524699 /lava-12073268/1/../bin/lava-test-case
11380 10:00:49.534274 <8>[ 27.632253] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass>
11381 10:00:49.534537 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass
11383 10:00:49.544414 /lava-12073268/1/../bin/lava-test-case
11384 10:00:49.551049 <8>[ 27.649116] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass>
11385 10:00:49.551317 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass
11387 10:00:49.564030 /lava-12073268/1/../bin/lava-test-case
11388 10:00:49.570347 <8>[ 27.668782] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass>
11389 10:00:49.570618 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass
11391 10:00:49.579869 /lava-12073268/1/../bin/lava-test-case
11392 10:00:49.586538 <8>[ 27.684540] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass>
11393 10:00:49.586800 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass
11395 10:00:49.599002 /lava-12073268/1/../bin/lava-test-case
11396 10:00:49.605370 <8>[ 27.703516] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass>
11397 10:00:49.605604 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass
11399 10:00:49.614386 /lava-12073268/1/../bin/lava-test-case
11400 10:00:49.623935 <8>[ 27.720988] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass>
11401 10:00:49.624209 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass
11403 10:00:49.634825 /lava-12073268/1/../bin/lava-test-case
11404 10:00:49.641053 <8>[ 27.739646] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-probed RESULT=pass>
11405 10:00:49.641316 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-probed RESULT=pass
11407 10:00:49.650066 /lava-12073268/1/../bin/lava-test-case
11408 10:00:49.656939 <8>[ 27.754039] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass>
11409 10:00:49.657202 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass
11411 10:00:50.672602 /lava-12073268/1/../bin/lava-test-case
11412 10:00:50.679344 <8>[ 28.779334] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-probed RESULT=fail>
11413 10:00:50.679619 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-probed RESULT=fail
11415 10:00:51.694528 /lava-12073268/1/../bin/lava-test-case
11416 10:00:51.701065 <8>[ 29.799218] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-7-probed RESULT=fail>
11417 10:00:51.701339 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-7-probed RESULT=fail
11419 10:00:51.711699 /lava-12073268/1/../bin/lava-test-case
11420 10:00:51.718135 <8>[ 29.816534] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-driver-present RESULT=pass>
11421 10:00:51.718397 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-driver-present RESULT=pass
11423 10:00:51.729621 /lava-12073268/1/../bin/lava-test-case
11424 10:00:51.736402 <8>[ 29.834370] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-probed RESULT=pass>
11425 10:00:51.736660 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-probed RESULT=pass
11427 10:00:51.743992 /lava-12073268/1/../bin/lava-test-case
11428 10:00:51.750877 <8>[ 29.850012] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass>
11429 10:00:51.751150 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass
11431 10:00:51.763639 /lava-12073268/1/../bin/lava-test-case
11432 10:00:51.770128 <8>[ 29.868461] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass>
11433 10:00:51.770428 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass
11435 10:00:51.778954 /lava-12073268/1/../bin/lava-test-case
11436 10:00:51.785725 <8>[ 29.884465] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-driver-present RESULT=pass>
11437 10:00:51.785981 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-driver-present RESULT=pass
11439 10:00:51.796945 /lava-12073268/1/../bin/lava-test-case
11440 10:00:51.803451 <8>[ 29.903543] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-probed RESULT=pass>
11441 10:00:51.803715 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-probed RESULT=pass
11443 10:00:51.813312 /lava-12073268/1/../bin/lava-test-case
11444 10:00:51.819846 <8>[ 29.918120] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass>
11445 10:00:51.820110 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass
11447 10:00:51.831958 /lava-12073268/1/../bin/lava-test-case
11448 10:00:51.837966 <8>[ 29.936375] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass>
11449 10:00:51.838255 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass
11451 10:00:51.847760 /lava-12073268/1/../bin/lava-test-case
11452 10:00:51.854459 <8>[ 29.951840] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass>
11453 10:00:51.854743 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass
11455 10:00:51.864361 /lava-12073268/1/../bin/lava-test-case
11456 10:00:51.870878 <8>[ 29.970257] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-probed RESULT=pass>
11457 10:00:51.871150 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-probed RESULT=pass
11459 10:00:51.880851 /lava-12073268/1/../bin/lava-test-case
11460 10:00:51.887201 <8>[ 29.985505] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass>
11461 10:00:51.887466 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass
11463 10:00:51.898319 /lava-12073268/1/../bin/lava-test-case
11464 10:00:51.904997 <8>[ 30.002940] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass>
11465 10:00:51.905292 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass
11467 10:00:51.922459 /lava-12073268/1/../bin/lava-tes<8>[ 30.019904] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass>
11468 10:00:51.922565 t-case
11469 10:00:51.922843 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass
11471 10:00:51.932124 /lava-12073268/1/../bin/lava-test-case
11472 10:00:51.938467 <8>[ 30.036349] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-probed RESULT=pass>
11473 10:00:51.938738 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-probed RESULT=pass
11475 10:00:51.947683 /lava-12073268/1/../bin/lava-test-case
11476 10:00:51.954433 <8>[ 30.052998] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass>
11477 10:00:51.954699 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass
11479 10:00:51.965210 /lava-12073268/1/../bin/lava-test-case
11480 10:00:51.971897 <8>[ 30.069745] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-probed RESULT=pass>
11481 10:00:51.972188 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-probed RESULT=pass
11483 10:00:51.979498 /lava-12073268/1/../bin/lava-test-case
11484 10:00:51.986120 <8>[ 30.084160] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-driver-present RESULT=pass>
11485 10:00:51.986374 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-driver-present RESULT=pass
11487 10:00:51.997740 /lava-12073268/1/../bin/lava-test-case
11488 10:00:52.004280 <8>[ 30.102402] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-probed RESULT=pass>
11489 10:00:52.004543 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-probed RESULT=pass
11491 10:00:52.011636 /lava-12073268/1/../bin/lava-test-case
11492 10:00:52.018621 <8>[ 30.117219] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass>
11493 10:00:52.018885 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass
11495 10:00:52.032809 /lava-12073268/1/../bin/lava-test-case
11496 10:00:52.039379 <8>[ 30.139105] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass>
11497 10:00:52.039683 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass
11499 10:00:53.051558 /lava-12073268/1/../bin/lava-test-case
11500 10:00:53.057791 <8>[ 31.156448] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail>
11501 10:00:53.058065 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail
11503 10:00:54.071017 /lava-12073268/1/../bin/lava-test-case
11504 10:00:54.078060 <8>[ 32.176732] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked>
11505 10:00:54.078336 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked
11506 10:00:54.078425 Bad test result: blocked
11507 10:00:54.087371 /lava-12073268/1/../bin/lava-test-case
11508 10:00:54.094003 <8>[ 32.192480] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-driver-present RESULT=pass>
11509 10:00:54.094260 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-driver-present RESULT=pass
11511 10:00:55.107189 /lava-12073268/1/../bin/lava-test-case
11512 10:00:55.113965 <8>[ 33.212908] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-probed RESULT=fail>
11513 10:00:55.114235 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-probed RESULT=fail
11515 10:00:55.125318 /lava-12073268/1/../bin/lava-test-case
11516 10:00:55.131994 <8>[ 33.229994] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo-driver-present RESULT=pass>
11517 10:00:55.132280 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo-driver-present RESULT=pass
11519 10:00:55.141758 /lava-12073268/1/../bin/lava-test-case
11520 10:00:55.148355 <8>[ 33.249583] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo0-probed RESULT=pass>
11521 10:00:55.148620 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo0-probed RESULT=pass
11523 10:00:55.160572 /lava-12073268/1/../bin/lava-test-case
11524 10:00:55.167131 <8>[ 33.266785] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo1-probed RESULT=pass>
11525 10:00:55.167399 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo1-probed RESULT=pass
11527 10:00:55.176335 /lava-12073268/1/../bin/lava-test-case
11528 10:00:55.182931 <8>[ 33.282046] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass>
11529 10:00:55.183196 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass
11531 10:00:55.194647 /lava-12073268/1/../bin/lava-test-case
11532 10:00:55.201129 <8>[ 33.299327] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-probed RESULT=pass>
11533 10:00:55.201401 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-probed RESULT=pass
11535 10:00:55.210856 /lava-12073268/1/../bin/lava-test-case
11536 10:00:55.217393 <8>[ 33.315257] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-driver-present RESULT=pass>
11537 10:00:55.217653 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-driver-present RESULT=pass
11539 10:00:56.231871 /lava-12073268/1/../bin/lava-test-case
11540 10:00:56.238377 <8>[ 34.338741] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-probed RESULT=fail>
11541 10:00:56.238647 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-probed RESULT=fail
11543 10:00:56.249174 /lava-12073268/1/../bin/lava-test-case
11544 10:00:56.255597 <8>[ 34.354292] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-driver-present RESULT=pass>
11545 10:00:56.255860 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-driver-present RESULT=pass
11547 10:00:57.268352 /lava-12073268/1/../bin/lava-test-case
11548 10:00:57.275186 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-probed RESULT=fail
11550 10:00:57.278174 <8>[ 35.376927] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-probed RESULT=fail>
11551 10:00:57.286912 /lava-12073268/1/../bin/lava-test-case
11552 10:00:57.293548 <8>[ 35.392589] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-driver-present RESULT=pass>
11553 10:00:57.293818 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-driver-present RESULT=pass
11555 10:00:58.307549 /lava-12073268/1/../bin/lava-test-case
11556 10:00:58.314223 <8>[ 36.413037] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-probed RESULT=fail>
11557 10:00:58.314533 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-probed RESULT=fail
11559 10:00:58.332037 /lava-12073268/1/../bin/lava-tes<8>[ 36.430115] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass>
11560 10:00:58.332133 t-case
11561 10:00:58.332375 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass
11563 10:00:59.343620 /lava-12073268/1/../bin/lava-test-case
11564 10:00:59.350260 <8>[ 37.449057] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail>
11565 10:00:59.350528 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail
11567 10:00:59.360206 /lava-12073268/1/../bin/lava-test-case
11568 10:00:59.366465 <8>[ 37.465782] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb-driver-present RESULT=pass>
11569 10:00:59.366740 Received signal: <TESTCASE> TEST_CASE_ID=btusb-driver-present RESULT=pass
11571 10:00:59.376184 /lava-12073268/1/../bin/lava-test-case
11572 10:00:59.386854 <8>[ 37.485803] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb0-probed RESULT=pass>
11573 10:00:59.387114 Received signal: <TESTCASE> TEST_CASE_ID=btusb0-probed RESULT=pass
11575 10:00:59.397015 /lava-12073268/1/../bin/lava-test-case
11576 10:00:59.403165 <8>[ 37.502565] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb1-probed RESULT=pass>
11577 10:00:59.403440 Received signal: <TESTCASE> TEST_CASE_ID=btusb1-probed RESULT=pass
11579 10:00:59.411519 /lava-12073268/1/../bin/lava-test-case
11580 10:00:59.417701 <8>[ 37.518069] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass>
11581 10:00:59.417965 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass
11583 10:00:59.429002 /lava-12073268/1/../bin/lava-test-case
11584 10:00:59.435951 <8>[ 37.536963] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-probed RESULT=pass>
11585 10:00:59.436225 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-probed RESULT=pass
11587 10:00:59.445689 /lava-12073268/1/../bin/lava-test-case
11588 10:00:59.452336 <8>[ 37.551297] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass>
11589 10:00:59.452609 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass
11591 10:00:59.463018 /lava-12073268/1/../bin/lava-test-case
11592 10:00:59.469348 <8>[ 37.568943] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-probed RESULT=pass>
11593 10:00:59.469616 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-probed RESULT=pass
11595 10:00:59.478615 /lava-12073268/1/../bin/lava-test-case
11596 10:00:59.484707 <8>[ 37.584826] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass>
11597 10:00:59.484964 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass
11599 10:00:59.497877 /lava-12073268/1/../bin/lava-test-case
11600 10:00:59.503919 <8>[ 37.603766] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass>
11601 10:00:59.504189 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass
11603 10:00:59.508609 + set +x
11604 10:00:59.511958 Received signal: <ENDRUN> 1_bootrr 12073268_1.5.2.3.5
11605 10:00:59.512066 Ending use of test pattern.
11606 10:00:59.512164 Ending test lava.1_bootrr (12073268_1.5.2.3.5), duration 20.39
11608 10:00:59.515476 <8>[ 37.614251] <LAVA_SIGNAL_ENDRUN 1_bootrr 12073268_1.5.2.3.5>
11609 10:00:59.518502 <LAVA_TEST_RUNNER EXIT>
11610 10:00:59.518751 ok: lava_test_shell seems to have completed
11611 10:00:59.519712 all-cpus-are-online: pass
anx7625-3-probed: fail
anx7625-7-probed: fail
anx7625-driver-present: pass
btusb-driver-present: pass
btusb0-probed: pass
btusb1-probed: pass
clk-mt8192-apmixedsys-probed: pass
clk-mt8192-aud-driver-present: pass
clk-mt8192-aud-probed: pass
clk-mt8192-cam-driver-present: pass
clk-mt8192-cam-probed: pass
clk-mt8192-cam_rawa-probed: pass
clk-mt8192-cam_rawb-probed: pass
clk-mt8192-cam_rawc-probed: pass
clk-mt8192-driver-present: pass
clk-mt8192-img-driver-present: pass
clk-mt8192-img-probed: pass
clk-mt8192-img2-probed: pass
clk-mt8192-imp_iic_wrap-driver-present: pass
clk-mt8192-imp_iic_wrap_e-probed: pass
clk-mt8192-imp_iic_wrap_n-probed: pass
clk-mt8192-imp_iic_wrap_s-probed: pass
clk-mt8192-imp_iic_wrap_ws-probed: pass
clk-mt8192-infracfg-probed: pass
clk-mt8192-ipe-driver-present: pass
clk-mt8192-ipe-probed: pass
clk-mt8192-mdp-driver-present: pass
clk-mt8192-mdp-probed: pass
clk-mt8192-mfg-driver-present: pass
clk-mt8192-mfg-probed: pass
clk-mt8192-mm-driver-present: pass
clk-mt8192-mm-probed: pass
clk-mt8192-msdc-driver-present: pass
clk-mt8192-msdc-probed: pass
clk-mt8192-pericfg-probed: pass
clk-mt8192-topckgen-probed: pass
clk-mt8192-vdec-driver-present: pass
clk-mt8192-vdec-probed: pass
clk-mt8192-vdec_soc-probed: pass
clk-mt8192-venc-driver-present: pass
clk-mt8192-venc-probed: pass
cros-ec-i2c-tunnel-driver-present: pass
cros-ec-i2c-tunnel-probed: pass
cros-ec-keyb-driver-present: pass
cros-ec-keyb-probed: pass
cros-ec-pwm-driver-present: pass
cros-ec-pwm-probed: pass
cros-ec-regulator-driver-present: pass
cros-ec-regulator0-probed: pass
cros-ec-regulator1-probed: pass
cros-ec-rpmsg-driver-present: pass
cros-ec-rpmsg-probed: pass
cros-ec-spi-driver-present: pass
cros-ec-spi-probed: pass
cros-ec-typec-driver-present: pass
cros-ec-typec-probed: pass
deferred-probe-empty: pass
dmic-codec-driver-present: pass
dmic-codec-probed: fail
elan_i2c-driver-present: pass
elan_i2c-probed: fail
elants_i2c-driver-present: pass
elants_i2c-probed: fail
i2c-mt65xx-driver-present: pass
i2c0-mt65xx-probed: pass
i2c1-mt65xx-probed: pass
i2c2-mt65xx-probed: pass
i2c3-mt65xx-probed: pass
i2c7-mt65xx-probed: pass
leds_pwm-driver-present: pass
leds_pwm-probed: pass
mediatek,efuse-driver-present: pass
mediatek,efuse-probed: pass
mediatek-disp-aal-driver-present: pass
mediatek-disp-aal-probed: pass
mediatek-disp-ccorr-driver-present: pass
mediatek-disp-ccorr-probed: pass
mediatek-disp-color-driver-present: pass
mediatek-disp-color-probed: pass
mediatek-disp-gamma-driver-present: pass
mediatek-disp-gamma-probed: pass
mediatek-disp-ovl-driver-present: pass
mediatek-disp-ovl0-probed: pass
mediatek-disp-ovl2l0-probed: pass
mediatek-disp-ovl2l2-probed: pass
mediatek-disp-pwm-driver-present: pass
mediatek-disp-pwm-probed: fail
mediatek-disp-rdma-driver-present: pass
mediatek-disp-rdma0-probed: pass
mediatek-disp-rdma4-probed: pass
mediatek-dpi-driver-present: pass
mediatek-dpi-probed: fail
mediatek-drm-driver-present: pass
mediatek-drm-probed: pass
mediatek-mipi-tx-driver-present: pass
mediatek-mipi-tx-probed: fail
mediatek-mutex-driver-present: pass
mediatek-mutex-probed: pass
mt-pmic-pwrap-driver-present: pass
mt-pmic-pwrap-probed: pass
mt6315-regulator-driver-present: pass
mt6315-regulator6-probed: pass
mt6315-regulator7-probed: pass
mt6577-uart-driver-present: pass
mt6577-uart-probed: pass
mt7921e-driver-present: pass
mt7921e-probed: pass
mt8192-audio-driver-present: pass
mt8192-audio-probed: pass
mt8192-pinctrl-driver-present: pass
mt8192-pinctrl-probed: pass
mt8192_mt6359-driver-present: pass
mt8192_mt6359-probed: fail
mtk-cpufreq-hw-driver-present: pass
mtk-cpufreq-hw-probed: pass
mtk-dsi-driver-present: pass
mtk-dsi-probed: fail
mtk-iommu-driver-present: pass
mtk-iommu-probed: pass
mtk-mmsys-driver-present: pass
mtk-mmsys-probed: pass
mtk-msdc-driver-present: pass
mtk-msdc-probed: pass
mtk-pcie-gen3-driver-present: pass
mtk-pcie-gen3-probed: pass
mtk-power-controller-driver-present: pass
mtk-power-controller-probed: pass
mtk-scp-driver-present: pass
mtk-scp-probed: pass
mtk-smi-common-driver-present: pass
mtk-smi-common-probed: pass
mtk-smi-larb-driver-present: pass
mtk-smi-larb0-probed: pass
mtk-smi-larb1-probed: pass
mtk-smi-larb11-probed: pass
mtk-smi-larb13-probed: pass
mtk-smi-larb14-probed: pass
mtk-smi-larb16-probed: pass
mtk-smi-larb17-probed: pass
mtk-smi-larb18-probed: pass
mtk-smi-larb19-probed: pass
mtk-smi-larb2-probed: pass
mtk-smi-larb20-probed: pass
mtk-smi-larb4-probed: pass
mtk-smi-larb5-probed: pass
mtk-smi-larb7-probed: pass
mtk-smi-larb9-probed: pass
mtk-spi-driver-present: pass
mtk-spi-nor-driver-present: pass
mtk-spi-nor-probed: pass
mtk-spi1-probed: pass
mtk-spi5-probed: pass
mtk-tphy-driver-present: pass
mtk-tphy-probed: pass
mtk-vcodec-dec-driver-present: fail
mtk-vcodec-enc-driver-present: pass
mtk-vcodec-enc-probed: pass
mtk-wdt-driver-present: pass
mtk-wdt-probed: pass
panel-edp-driver-present: pass
panel-simple-dp-aux-driver-present: pass
panel-simple-dp-aux-probed: fail
panfrost-driver-present: pass
panfrost-probed: fail
pwm-backlight-driver-present: pass
pwm-backlight-probed: fail
rt1015p-driver-present: pass
rt1015p-probed: fail
rt5682-driver-present: pass
rt5682-probed: fail
sbs-battery-driver-present: pass
sbs-battery-probed: pass
spmi-mtk-driver-present: pass
spmi-mtk-probed: pass
tpm-chip-is-online: pass
tpm_tis_spi-driver-present: pass
tpm_tis_spi-probed: pass
uvcvideo-driver-present: pass
uvcvideo0-probed: pass
uvcvideo1-probed: pass
xhci-mtk-driver-present: pass
xhci-mtk-probed: pass
11612 10:00:59.519858 end: 4.1 lava-test-shell (duration 00:00:21) [common]
11613 10:00:59.519943 end: 4 lava-test-retry (duration 00:00:21) [common]
11614 10:00:59.520028 start: 5 finalize (timeout 00:08:05) [common]
11615 10:00:59.520113 start: 5.1 power-off (timeout 00:00:30) [common]
11616 10:00:59.520293 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11617 10:00:59.596383 >> Command sent successfully.
11618 10:00:59.599363 Returned 0 in 0 seconds
11619 10:00:59.699741 end: 5.1 power-off (duration 00:00:00) [common]
11621 10:00:59.700079 start: 5.2 read-feedback (timeout 00:08:05) [common]
11622 10:00:59.700351 Listened to connection for namespace 'common' for up to 1s
11623 10:01:00.701263 Finalising connection for namespace 'common'
11624 10:01:00.701425 Disconnecting from shell: Finalise
11625 10:01:00.701500 / #
11626 10:01:00.801822 end: 5.2 read-feedback (duration 00:00:01) [common]
11627 10:01:00.801985 end: 5 finalize (duration 00:00:01) [common]
11628 10:01:00.802104 Cleaning after the job
11629 10:01:00.802254 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12073268/tftp-deploy-2obxkcdy/ramdisk
11630 10:01:00.805534 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12073268/tftp-deploy-2obxkcdy/kernel
11631 10:01:00.814695 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12073268/tftp-deploy-2obxkcdy/dtb
11632 10:01:00.814924 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12073268/tftp-deploy-2obxkcdy/modules
11633 10:01:00.822524 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12073268
11634 10:01:00.869675 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12073268
11635 10:01:00.869859 Job finished correctly