Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Errors: 39
- Kernel Warnings: 27
- Boot result: PASS
- Errors: 0
1 10:02:39.129142 lava-dispatcher, installed at version: 2023.10
2 10:02:39.129346 start: 0 validate
3 10:02:39.129476 Start time: 2023-11-24 10:02:39.129468+00:00 (UTC)
4 10:02:39.129595 Using caching service: 'http://localhost/cache/?uri=%s'
5 10:02:39.129726 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 10:02:39.391499 Using caching service: 'http://localhost/cache/?uri=%s'
7 10:02:39.392237 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 10:02:39.663336 Using caching service: 'http://localhost/cache/?uri=%s'
9 10:02:39.664159 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 10:02:39.937725 Using caching service: 'http://localhost/cache/?uri=%s'
11 10:02:39.938528 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 10:02:40.209309 Using caching service: 'http://localhost/cache/?uri=%s'
13 10:02:40.210047 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 10:02:40.479061 validate duration: 1.35
16 10:02:40.480301 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 10:02:40.480877 start: 1.1 download-retry (timeout 00:10:00) [common]
18 10:02:40.481398 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 10:02:40.482056 Not decompressing ramdisk as can be used compressed.
20 10:02:40.482608 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/initrd.cpio.gz
21 10:02:40.483049 saving as /var/lib/lava/dispatcher/tmp/12073344/tftp-deploy-x5o2dtz4/ramdisk/initrd.cpio.gz
22 10:02:40.483634 total size: 4665395 (4 MB)
23 10:02:40.489012 progress 0 % (0 MB)
24 10:02:40.497656 progress 5 % (0 MB)
25 10:02:40.504493 progress 10 % (0 MB)
26 10:02:40.509393 progress 15 % (0 MB)
27 10:02:40.513099 progress 20 % (0 MB)
28 10:02:40.516328 progress 25 % (1 MB)
29 10:02:40.519094 progress 30 % (1 MB)
30 10:02:40.521603 progress 35 % (1 MB)
31 10:02:40.523870 progress 40 % (1 MB)
32 10:02:40.526328 progress 45 % (2 MB)
33 10:02:40.528311 progress 50 % (2 MB)
34 10:02:40.530302 progress 55 % (2 MB)
35 10:02:40.532056 progress 60 % (2 MB)
36 10:02:40.533759 progress 65 % (2 MB)
37 10:02:40.535519 progress 70 % (3 MB)
38 10:02:40.537067 progress 75 % (3 MB)
39 10:02:40.538621 progress 80 % (3 MB)
40 10:02:40.540370 progress 85 % (3 MB)
41 10:02:40.541773 progress 90 % (4 MB)
42 10:02:40.543150 progress 95 % (4 MB)
43 10:02:40.544544 progress 100 % (4 MB)
44 10:02:40.544715 4 MB downloaded in 0.06 s (72.82 MB/s)
45 10:02:40.544883 end: 1.1.1 http-download (duration 00:00:00) [common]
47 10:02:40.545152 end: 1.1 download-retry (duration 00:00:00) [common]
48 10:02:40.545249 start: 1.2 download-retry (timeout 00:10:00) [common]
49 10:02:40.545341 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 10:02:40.545488 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 10:02:40.545570 saving as /var/lib/lava/dispatcher/tmp/12073344/tftp-deploy-x5o2dtz4/kernel/Image
52 10:02:40.545647 total size: 49107456 (46 MB)
53 10:02:40.545709 No compression specified
54 10:02:40.546824 progress 0 % (0 MB)
55 10:02:40.559303 progress 5 % (2 MB)
56 10:02:40.571779 progress 10 % (4 MB)
57 10:02:40.584415 progress 15 % (7 MB)
58 10:02:40.597202 progress 20 % (9 MB)
59 10:02:40.610227 progress 25 % (11 MB)
60 10:02:40.623312 progress 30 % (14 MB)
61 10:02:40.636092 progress 35 % (16 MB)
62 10:02:40.648778 progress 40 % (18 MB)
63 10:02:40.661468 progress 45 % (21 MB)
64 10:02:40.674113 progress 50 % (23 MB)
65 10:02:40.686752 progress 55 % (25 MB)
66 10:02:40.699536 progress 60 % (28 MB)
67 10:02:40.712379 progress 65 % (30 MB)
68 10:02:40.725244 progress 70 % (32 MB)
69 10:02:40.738002 progress 75 % (35 MB)
70 10:02:40.751000 progress 80 % (37 MB)
71 10:02:40.763699 progress 85 % (39 MB)
72 10:02:40.776325 progress 90 % (42 MB)
73 10:02:40.788800 progress 95 % (44 MB)
74 10:02:40.801553 progress 100 % (46 MB)
75 10:02:40.801769 46 MB downloaded in 0.26 s (182.86 MB/s)
76 10:02:40.801924 end: 1.2.1 http-download (duration 00:00:00) [common]
78 10:02:40.802154 end: 1.2 download-retry (duration 00:00:00) [common]
79 10:02:40.802245 start: 1.3 download-retry (timeout 00:10:00) [common]
80 10:02:40.802341 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 10:02:40.802478 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 10:02:40.802547 saving as /var/lib/lava/dispatcher/tmp/12073344/tftp-deploy-x5o2dtz4/dtb/mt8192-asurada-spherion-r0.dtb
83 10:02:40.802607 total size: 47278 (0 MB)
84 10:02:40.802667 No compression specified
85 10:02:40.803803 progress 69 % (0 MB)
86 10:02:40.804078 progress 100 % (0 MB)
87 10:02:40.804237 0 MB downloaded in 0.00 s (27.70 MB/s)
88 10:02:40.804358 end: 1.3.1 http-download (duration 00:00:00) [common]
90 10:02:40.804581 end: 1.3 download-retry (duration 00:00:00) [common]
91 10:02:40.804667 start: 1.4 download-retry (timeout 00:10:00) [common]
92 10:02:40.804749 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 10:02:40.804861 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/full.rootfs.tar.xz
94 10:02:40.804928 saving as /var/lib/lava/dispatcher/tmp/12073344/tftp-deploy-x5o2dtz4/nfsrootfs/full.rootfs.tar
95 10:02:40.804986 total size: 200813988 (191 MB)
96 10:02:40.805046 Using unxz to decompress xz
97 10:02:40.809105 progress 0 % (0 MB)
98 10:02:41.351408 progress 5 % (9 MB)
99 10:02:41.868778 progress 10 % (19 MB)
100 10:02:42.459615 progress 15 % (28 MB)
101 10:02:42.829835 progress 20 % (38 MB)
102 10:02:43.150067 progress 25 % (47 MB)
103 10:02:43.739275 progress 30 % (57 MB)
104 10:02:44.300587 progress 35 % (67 MB)
105 10:02:44.894144 progress 40 % (76 MB)
106 10:02:45.446108 progress 45 % (86 MB)
107 10:02:46.025504 progress 50 % (95 MB)
108 10:02:46.651540 progress 55 % (105 MB)
109 10:02:47.313858 progress 60 % (114 MB)
110 10:02:47.430866 progress 65 % (124 MB)
111 10:02:47.568532 progress 70 % (134 MB)
112 10:02:47.663594 progress 75 % (143 MB)
113 10:02:47.734123 progress 80 % (153 MB)
114 10:02:47.802676 progress 85 % (162 MB)
115 10:02:47.902370 progress 90 % (172 MB)
116 10:02:48.176645 progress 95 % (181 MB)
117 10:02:48.749159 progress 100 % (191 MB)
118 10:02:48.754284 191 MB downloaded in 7.95 s (24.09 MB/s)
119 10:02:48.754550 end: 1.4.1 http-download (duration 00:00:08) [common]
121 10:02:48.754809 end: 1.4 download-retry (duration 00:00:08) [common]
122 10:02:48.754898 start: 1.5 download-retry (timeout 00:09:52) [common]
123 10:02:48.754984 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 10:02:48.755143 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 10:02:48.755214 saving as /var/lib/lava/dispatcher/tmp/12073344/tftp-deploy-x5o2dtz4/modules/modules.tar
126 10:02:48.755275 total size: 8622040 (8 MB)
127 10:02:48.755338 Using unxz to decompress xz
128 10:02:48.759617 progress 0 % (0 MB)
129 10:02:48.780329 progress 5 % (0 MB)
130 10:02:48.803876 progress 10 % (0 MB)
131 10:02:48.827427 progress 15 % (1 MB)
132 10:02:48.850852 progress 20 % (1 MB)
133 10:02:48.874656 progress 25 % (2 MB)
134 10:02:48.899828 progress 30 % (2 MB)
135 10:02:48.925695 progress 35 % (2 MB)
136 10:02:48.948806 progress 40 % (3 MB)
137 10:02:48.972525 progress 45 % (3 MB)
138 10:02:48.997240 progress 50 % (4 MB)
139 10:02:49.021181 progress 55 % (4 MB)
140 10:02:49.045632 progress 60 % (4 MB)
141 10:02:49.072788 progress 65 % (5 MB)
142 10:02:49.098294 progress 70 % (5 MB)
143 10:02:49.121129 progress 75 % (6 MB)
144 10:02:49.148072 progress 80 % (6 MB)
145 10:02:49.173302 progress 85 % (7 MB)
146 10:02:49.197782 progress 90 % (7 MB)
147 10:02:49.227127 progress 95 % (7 MB)
148 10:02:49.256777 progress 100 % (8 MB)
149 10:02:49.261467 8 MB downloaded in 0.51 s (16.24 MB/s)
150 10:02:49.261718 end: 1.5.1 http-download (duration 00:00:01) [common]
152 10:02:49.261980 end: 1.5 download-retry (duration 00:00:01) [common]
153 10:02:49.262073 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 10:02:49.262171 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 10:02:52.832591 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12073344/extract-nfsrootfs-d95w75f3
156 10:02:52.832793 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 10:02:52.832893 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 10:02:52.833057 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12073344/lava-overlay-4qkh41we
159 10:02:52.833187 makedir: /var/lib/lava/dispatcher/tmp/12073344/lava-overlay-4qkh41we/lava-12073344/bin
160 10:02:52.833287 makedir: /var/lib/lava/dispatcher/tmp/12073344/lava-overlay-4qkh41we/lava-12073344/tests
161 10:02:52.833384 makedir: /var/lib/lava/dispatcher/tmp/12073344/lava-overlay-4qkh41we/lava-12073344/results
162 10:02:52.833483 Creating /var/lib/lava/dispatcher/tmp/12073344/lava-overlay-4qkh41we/lava-12073344/bin/lava-add-keys
163 10:02:52.833627 Creating /var/lib/lava/dispatcher/tmp/12073344/lava-overlay-4qkh41we/lava-12073344/bin/lava-add-sources
164 10:02:52.833757 Creating /var/lib/lava/dispatcher/tmp/12073344/lava-overlay-4qkh41we/lava-12073344/bin/lava-background-process-start
165 10:02:52.833882 Creating /var/lib/lava/dispatcher/tmp/12073344/lava-overlay-4qkh41we/lava-12073344/bin/lava-background-process-stop
166 10:02:52.834006 Creating /var/lib/lava/dispatcher/tmp/12073344/lava-overlay-4qkh41we/lava-12073344/bin/lava-common-functions
167 10:02:52.834129 Creating /var/lib/lava/dispatcher/tmp/12073344/lava-overlay-4qkh41we/lava-12073344/bin/lava-echo-ipv4
168 10:02:52.834258 Creating /var/lib/lava/dispatcher/tmp/12073344/lava-overlay-4qkh41we/lava-12073344/bin/lava-install-packages
169 10:02:52.834434 Creating /var/lib/lava/dispatcher/tmp/12073344/lava-overlay-4qkh41we/lava-12073344/bin/lava-installed-packages
170 10:02:52.834599 Creating /var/lib/lava/dispatcher/tmp/12073344/lava-overlay-4qkh41we/lava-12073344/bin/lava-os-build
171 10:02:52.834724 Creating /var/lib/lava/dispatcher/tmp/12073344/lava-overlay-4qkh41we/lava-12073344/bin/lava-probe-channel
172 10:02:52.834849 Creating /var/lib/lava/dispatcher/tmp/12073344/lava-overlay-4qkh41we/lava-12073344/bin/lava-probe-ip
173 10:02:52.834972 Creating /var/lib/lava/dispatcher/tmp/12073344/lava-overlay-4qkh41we/lava-12073344/bin/lava-target-ip
174 10:02:52.835101 Creating /var/lib/lava/dispatcher/tmp/12073344/lava-overlay-4qkh41we/lava-12073344/bin/lava-target-mac
175 10:02:52.835224 Creating /var/lib/lava/dispatcher/tmp/12073344/lava-overlay-4qkh41we/lava-12073344/bin/lava-target-storage
176 10:02:52.835350 Creating /var/lib/lava/dispatcher/tmp/12073344/lava-overlay-4qkh41we/lava-12073344/bin/lava-test-case
177 10:02:52.835482 Creating /var/lib/lava/dispatcher/tmp/12073344/lava-overlay-4qkh41we/lava-12073344/bin/lava-test-event
178 10:02:52.835606 Creating /var/lib/lava/dispatcher/tmp/12073344/lava-overlay-4qkh41we/lava-12073344/bin/lava-test-feedback
179 10:02:52.835736 Creating /var/lib/lava/dispatcher/tmp/12073344/lava-overlay-4qkh41we/lava-12073344/bin/lava-test-raise
180 10:02:52.835874 Creating /var/lib/lava/dispatcher/tmp/12073344/lava-overlay-4qkh41we/lava-12073344/bin/lava-test-reference
181 10:02:52.835999 Creating /var/lib/lava/dispatcher/tmp/12073344/lava-overlay-4qkh41we/lava-12073344/bin/lava-test-runner
182 10:02:52.836122 Creating /var/lib/lava/dispatcher/tmp/12073344/lava-overlay-4qkh41we/lava-12073344/bin/lava-test-set
183 10:02:52.836247 Creating /var/lib/lava/dispatcher/tmp/12073344/lava-overlay-4qkh41we/lava-12073344/bin/lava-test-shell
184 10:02:52.836371 Updating /var/lib/lava/dispatcher/tmp/12073344/lava-overlay-4qkh41we/lava-12073344/bin/lava-add-keys (debian)
185 10:02:52.836527 Updating /var/lib/lava/dispatcher/tmp/12073344/lava-overlay-4qkh41we/lava-12073344/bin/lava-add-sources (debian)
186 10:02:52.836666 Updating /var/lib/lava/dispatcher/tmp/12073344/lava-overlay-4qkh41we/lava-12073344/bin/lava-install-packages (debian)
187 10:02:52.836802 Updating /var/lib/lava/dispatcher/tmp/12073344/lava-overlay-4qkh41we/lava-12073344/bin/lava-installed-packages (debian)
188 10:02:52.836938 Updating /var/lib/lava/dispatcher/tmp/12073344/lava-overlay-4qkh41we/lava-12073344/bin/lava-os-build (debian)
189 10:02:52.837057 Creating /var/lib/lava/dispatcher/tmp/12073344/lava-overlay-4qkh41we/lava-12073344/environment
190 10:02:52.837151 LAVA metadata
191 10:02:52.837218 - LAVA_JOB_ID=12073344
192 10:02:52.837280 - LAVA_DISPATCHER_IP=192.168.201.1
193 10:02:52.837376 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
194 10:02:52.837441 skipped lava-vland-overlay
195 10:02:52.837513 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 10:02:52.837590 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
197 10:02:52.837648 skipped lava-multinode-overlay
198 10:02:52.837717 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 10:02:52.837792 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
200 10:02:52.837876 Loading test definitions
201 10:02:52.837962 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
202 10:02:52.838029 Using /lava-12073344 at stage 0
203 10:02:52.838461 uuid=12073344_1.6.2.3.1 testdef=None
204 10:02:52.838610 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 10:02:52.838714 start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
206 10:02:52.839169 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 10:02:52.839387 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
209 10:02:52.839938 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 10:02:52.840162 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
212 10:02:52.840697 runner path: /var/lib/lava/dispatcher/tmp/12073344/lava-overlay-4qkh41we/lava-12073344/0/tests/0_timesync-off test_uuid 12073344_1.6.2.3.1
213 10:02:52.840851 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 10:02:52.841072 start: 1.6.2.3.5 git-repo-action (timeout 00:09:48) [common]
216 10:02:52.841143 Using /lava-12073344 at stage 0
217 10:02:52.841236 Fetching tests from https://github.com/kernelci/test-definitions.git
218 10:02:52.841313 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/12073344/lava-overlay-4qkh41we/lava-12073344/0/tests/1_kselftest-arm64'
219 10:03:00.053836 Running '/usr/bin/git checkout kernelci.org
220 10:03:00.110085 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12073344/lava-overlay-4qkh41we/lava-12073344/0/tests/1_kselftest-arm64/automated/linux/kselftest/kselftest.yaml
221 10:03:00.110849 uuid=12073344_1.6.2.3.5 testdef=None
222 10:03:00.111006 end: 1.6.2.3.5 git-repo-action (duration 00:00:07) [common]
224 10:03:00.111261 start: 1.6.2.3.6 test-overlay (timeout 00:09:40) [common]
225 10:03:00.112001 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 10:03:00.112231 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:40) [common]
228 10:03:00.113189 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 10:03:00.113420 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:40) [common]
231 10:03:00.114447 runner path: /var/lib/lava/dispatcher/tmp/12073344/lava-overlay-4qkh41we/lava-12073344/0/tests/1_kselftest-arm64 test_uuid 12073344_1.6.2.3.5
232 10:03:00.114541 BOARD='mt8192-asurada-spherion-r0'
233 10:03:00.114604 BRANCH='cip'
234 10:03:00.114661 SKIPFILE='/dev/null'
235 10:03:00.114718 SKIP_INSTALL='True'
236 10:03:00.114772 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 10:03:00.114828 TST_CASENAME=''
238 10:03:00.114882 TST_CMDFILES='arm64'
239 10:03:00.115024 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 10:03:00.115223 Creating lava-test-runner.conf files
242 10:03:00.115286 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12073344/lava-overlay-4qkh41we/lava-12073344/0 for stage 0
243 10:03:00.115378 - 0_timesync-off
244 10:03:00.115445 - 1_kselftest-arm64
245 10:03:00.115539 end: 1.6.2.3 test-definition (duration 00:00:07) [common]
246 10:03:00.115637 start: 1.6.2.4 compress-overlay (timeout 00:09:40) [common]
247 10:03:07.514205 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 10:03:07.514406 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:33) [common]
249 10:03:07.514499 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 10:03:07.514599 end: 1.6.2 lava-overlay (duration 00:00:15) [common]
251 10:03:07.514692 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:33) [common]
252 10:03:07.633678 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 10:03:07.634071 start: 1.6.4 extract-modules (timeout 00:09:33) [common]
254 10:03:07.634184 extracting modules file /var/lib/lava/dispatcher/tmp/12073344/tftp-deploy-x5o2dtz4/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12073344/extract-nfsrootfs-d95w75f3
255 10:03:07.856498 extracting modules file /var/lib/lava/dispatcher/tmp/12073344/tftp-deploy-x5o2dtz4/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12073344/extract-overlay-ramdisk-2rfjeb_e/ramdisk
256 10:03:08.082934 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 10:03:08.083104 start: 1.6.5 apply-overlay-tftp (timeout 00:09:32) [common]
258 10:03:08.083200 [common] Applying overlay to NFS
259 10:03:08.083272 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12073344/compress-overlay-oew0b2j_/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12073344/extract-nfsrootfs-d95w75f3
260 10:03:09.002650 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 10:03:09.002818 start: 1.6.6 configure-preseed-file (timeout 00:09:31) [common]
262 10:03:09.002958 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 10:03:09.003050 start: 1.6.7 compress-ramdisk (timeout 00:09:31) [common]
264 10:03:09.003131 Building ramdisk /var/lib/lava/dispatcher/tmp/12073344/extract-overlay-ramdisk-2rfjeb_e/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12073344/extract-overlay-ramdisk-2rfjeb_e/ramdisk
265 10:03:09.320015 >> 119398 blocks
266 10:03:11.268401 rename /var/lib/lava/dispatcher/tmp/12073344/extract-overlay-ramdisk-2rfjeb_e/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12073344/tftp-deploy-x5o2dtz4/ramdisk/ramdisk.cpio.gz
267 10:03:11.268880 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 10:03:11.269058 start: 1.6.8 prepare-kernel (timeout 00:09:29) [common]
269 10:03:11.269199 start: 1.6.8.1 prepare-fit (timeout 00:09:29) [common]
270 10:03:11.269347 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12073344/tftp-deploy-x5o2dtz4/kernel/Image'
271 10:03:23.159275 Returned 0 in 11 seconds
272 10:03:23.260505 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12073344/tftp-deploy-x5o2dtz4/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12073344/tftp-deploy-x5o2dtz4/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12073344/tftp-deploy-x5o2dtz4/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12073344/tftp-deploy-x5o2dtz4/kernel/image.itb
273 10:03:23.626060 output: FIT description: Kernel Image image with one or more FDT blobs
274 10:03:23.626496 output: Created: Fri Nov 24 10:03:23 2023
275 10:03:23.626604 output: Image 0 (kernel-1)
276 10:03:23.626689 output: Description:
277 10:03:23.626771 output: Created: Fri Nov 24 10:03:23 2023
278 10:03:23.626851 output: Type: Kernel Image
279 10:03:23.626930 output: Compression: lzma compressed
280 10:03:23.627006 output: Data Size: 11047542 Bytes = 10788.62 KiB = 10.54 MiB
281 10:03:23.627102 output: Architecture: AArch64
282 10:03:23.627200 output: OS: Linux
283 10:03:23.627294 output: Load Address: 0x00000000
284 10:03:23.627389 output: Entry Point: 0x00000000
285 10:03:23.627479 output: Hash algo: crc32
286 10:03:23.627573 output: Hash value: 2edffaa3
287 10:03:23.627666 output: Image 1 (fdt-1)
288 10:03:23.627756 output: Description: mt8192-asurada-spherion-r0
289 10:03:23.627846 output: Created: Fri Nov 24 10:03:23 2023
290 10:03:23.627936 output: Type: Flat Device Tree
291 10:03:23.628025 output: Compression: uncompressed
292 10:03:23.628114 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 10:03:23.628207 output: Architecture: AArch64
294 10:03:23.628298 output: Hash algo: crc32
295 10:03:23.628387 output: Hash value: cc4352de
296 10:03:23.628476 output: Image 2 (ramdisk-1)
297 10:03:23.628564 output: Description: unavailable
298 10:03:23.628653 output: Created: Fri Nov 24 10:03:23 2023
299 10:03:23.628742 output: Type: RAMDisk Image
300 10:03:23.628832 output: Compression: Unknown Compression
301 10:03:23.628920 output: Data Size: 17791565 Bytes = 17374.58 KiB = 16.97 MiB
302 10:03:23.629031 output: Architecture: AArch64
303 10:03:23.629165 output: OS: Linux
304 10:03:23.629270 output: Load Address: unavailable
305 10:03:23.629361 output: Entry Point: unavailable
306 10:03:23.629450 output: Hash algo: crc32
307 10:03:23.629569 output: Hash value: 30b4effc
308 10:03:23.629680 output: Default Configuration: 'conf-1'
309 10:03:23.629848 output: Configuration 0 (conf-1)
310 10:03:23.629939 output: Description: mt8192-asurada-spherion-r0
311 10:03:23.630029 output: Kernel: kernel-1
312 10:03:23.630118 output: Init Ramdisk: ramdisk-1
313 10:03:23.630207 output: FDT: fdt-1
314 10:03:23.630338 output: Loadables: kernel-1
315 10:03:23.630428 output:
316 10:03:23.630680 end: 1.6.8.1 prepare-fit (duration 00:00:12) [common]
317 10:03:23.630824 end: 1.6.8 prepare-kernel (duration 00:00:12) [common]
318 10:03:23.630976 end: 1.6 prepare-tftp-overlay (duration 00:00:34) [common]
319 10:03:23.631108 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:17) [common]
320 10:03:23.631198 No LXC device requested
321 10:03:23.631297 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 10:03:23.631404 start: 1.8 deploy-device-env (timeout 00:09:17) [common]
323 10:03:23.631495 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 10:03:23.631580 Checking files for TFTP limit of 4294967296 bytes.
325 10:03:23.632217 end: 1 tftp-deploy (duration 00:00:43) [common]
326 10:03:23.632354 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 10:03:23.632486 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 10:03:23.632665 substitutions:
329 10:03:23.632762 - {DTB}: 12073344/tftp-deploy-x5o2dtz4/dtb/mt8192-asurada-spherion-r0.dtb
330 10:03:23.632844 - {INITRD}: 12073344/tftp-deploy-x5o2dtz4/ramdisk/ramdisk.cpio.gz
331 10:03:23.632923 - {KERNEL}: 12073344/tftp-deploy-x5o2dtz4/kernel/Image
332 10:03:23.632999 - {LAVA_MAC}: None
333 10:03:23.633074 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12073344/extract-nfsrootfs-d95w75f3
334 10:03:23.633151 - {NFS_SERVER_IP}: 192.168.201.1
335 10:03:23.633243 - {PRESEED_CONFIG}: None
336 10:03:23.633388 - {PRESEED_LOCAL}: None
337 10:03:23.633481 - {RAMDISK}: 12073344/tftp-deploy-x5o2dtz4/ramdisk/ramdisk.cpio.gz
338 10:03:23.633573 - {ROOT_PART}: None
339 10:03:23.633668 - {ROOT}: None
340 10:03:23.633763 - {SERVER_IP}: 192.168.201.1
341 10:03:23.633861 - {TEE}: None
342 10:03:23.633953 Parsed boot commands:
343 10:03:23.634043 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 10:03:23.634383 Parsed boot commands: tftpboot 192.168.201.1 12073344/tftp-deploy-x5o2dtz4/kernel/image.itb 12073344/tftp-deploy-x5o2dtz4/kernel/cmdline
345 10:03:23.634508 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 10:03:23.634639 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 10:03:23.634792 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 10:03:23.634921 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 10:03:23.635029 Not connected, no need to disconnect.
350 10:03:23.635144 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 10:03:23.635267 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 10:03:23.635370 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-2'
353 10:03:23.639511 Setting prompt string to ['lava-test: # ']
354 10:03:23.639951 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 10:03:23.640193 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 10:03:23.640321 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 10:03:23.640432 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 10:03:23.640751 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=reboot'
359 10:03:28.794671 >> Command sent successfully.
360 10:03:28.805116 Returned 0 in 5 seconds
361 10:03:28.906419 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 10:03:28.908038 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 10:03:28.908715 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 10:03:28.909351 Setting prompt string to 'Starting depthcharge on Spherion...'
366 10:03:28.909786 Changing prompt to 'Starting depthcharge on Spherion...'
367 10:03:28.910298 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 10:03:28.911664 [Enter `^Ec?' for help]
369 10:03:29.071459
370 10:03:29.072017
371 10:03:29.072485 F0: 102B 0000
372 10:03:29.072945
373 10:03:29.073364 F3: 1001 0000 [0200]
374 10:03:29.074454
375 10:03:29.074884 F3: 1001 0000
376 10:03:29.075329
377 10:03:29.075747 F7: 102D 0000
378 10:03:29.076155
379 10:03:29.077490 F1: 0000 0000
380 10:03:29.077945
381 10:03:29.078473 V0: 0000 0000 [0001]
382 10:03:29.078911
383 10:03:29.081289 00: 0007 8000
384 10:03:29.081842
385 10:03:29.082324 01: 0000 0000
386 10:03:29.082758
387 10:03:29.084050 BP: 0C00 0209 [0000]
388 10:03:29.084486
389 10:03:29.084930 G0: 1182 0000
390 10:03:29.085347
391 10:03:29.088074 EC: 0000 0021 [4000]
392 10:03:29.088730
393 10:03:29.089197 S7: 0000 0000 [0000]
394 10:03:29.089527
395 10:03:29.090801 CC: 0000 0000 [0001]
396 10:03:29.091223
397 10:03:29.091556 T0: 0000 0040 [010F]
398 10:03:29.091865
399 10:03:29.094792 Jump to BL
400 10:03:29.095301
401 10:03:29.118248
402 10:03:29.118797
403 10:03:29.119134
404 10:03:29.125190 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 10:03:29.128610 ARM64: Exception handlers installed.
406 10:03:29.132019 ARM64: Testing exception
407 10:03:29.135162 ARM64: Done test exception
408 10:03:29.142329 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 10:03:29.152801 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 10:03:29.158483 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 10:03:29.169960 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 10:03:29.175123 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 10:03:29.185945 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 10:03:29.196213 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 10:03:29.202843 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 10:03:29.220799 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 10:03:29.224153 WDT: Last reset was cold boot
418 10:03:29.227643 SPI1(PAD0) initialized at 2873684 Hz
419 10:03:29.230751 SPI5(PAD0) initialized at 992727 Hz
420 10:03:29.234078 VBOOT: Loading verstage.
421 10:03:29.240965 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 10:03:29.244342 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 10:03:29.246934 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 10:03:29.250438 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 10:03:29.258802 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 10:03:29.264600 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 10:03:29.275897 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 10:03:29.276456
429 10:03:29.276793
430 10:03:29.286132 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 10:03:29.289525 ARM64: Exception handlers installed.
432 10:03:29.292588 ARM64: Testing exception
433 10:03:29.293118 ARM64: Done test exception
434 10:03:29.300021 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 10:03:29.302660 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 10:03:29.316537 Probing TPM: . done!
437 10:03:29.317137 TPM ready after 0 ms
438 10:03:29.324770 Connected to device vid:did:rid of 1ae0:0028:00
439 10:03:29.330770 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
440 10:03:29.390397 Initialized TPM device CR50 revision 0
441 10:03:29.399721 tlcl_send_startup: Startup return code is 0
442 10:03:29.400232 TPM: setup succeeded
443 10:03:29.411555 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 10:03:29.420305 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 10:03:29.432358 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 10:03:29.442166 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 10:03:29.445302 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 10:03:29.451196 in-header: 03 07 00 00 08 00 00 00
449 10:03:29.454573 in-data: aa e4 47 04 13 02 00 00
450 10:03:29.458413 Chrome EC: UHEPI supported
451 10:03:29.465285 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 10:03:29.468922 in-header: 03 95 00 00 08 00 00 00
453 10:03:29.472189 in-data: 18 20 20 08 00 00 00 00
454 10:03:29.472625 Phase 1
455 10:03:29.475944 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 10:03:29.483216 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 10:03:29.486906 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 10:03:29.490709 Recovery requested (1009000e)
459 10:03:29.499741 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 10:03:29.505287 tlcl_extend: response is 0
461 10:03:29.514838 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 10:03:29.520347 tlcl_extend: response is 0
463 10:03:29.527057 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 10:03:29.547196 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
465 10:03:29.553483 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 10:03:29.553990
467 10:03:29.554367
468 10:03:29.564075 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 10:03:29.567269 ARM64: Exception handlers installed.
470 10:03:29.570189 ARM64: Testing exception
471 10:03:29.570664 ARM64: Done test exception
472 10:03:29.592683 pmic_efuse_setting: Set efuses in 11 msecs
473 10:03:29.595426 pmwrap_interface_init: Select PMIF_VLD_RDY
474 10:03:29.602217 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 10:03:29.605797 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 10:03:29.612581 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 10:03:29.616570 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 10:03:29.620498 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 10:03:29.624102 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 10:03:29.632262 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 10:03:29.635375 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 10:03:29.639142 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 10:03:29.646051 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 10:03:29.649870 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 10:03:29.653673 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 10:03:29.656870 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 10:03:29.664881 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 10:03:29.671791 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 10:03:29.675097 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 10:03:29.682710 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 10:03:29.686358 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 10:03:29.693366 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 10:03:29.697542 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 10:03:29.704484 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 10:03:29.708416 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 10:03:29.715956 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 10:03:29.719122 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 10:03:29.726985 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 10:03:29.730900 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 10:03:29.737732 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 10:03:29.740993 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 10:03:29.748546 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 10:03:29.752194 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 10:03:29.755855 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 10:03:29.763192 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 10:03:29.766305 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 10:03:29.770508 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 10:03:29.777695 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 10:03:29.781356 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 10:03:29.788684 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 10:03:29.792339 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 10:03:29.796111 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 10:03:29.799180 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 10:03:29.803279 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 10:03:29.810018 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 10:03:29.813829 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 10:03:29.817435 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 10:03:29.821423 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 10:03:29.825199 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 10:03:29.832446 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 10:03:29.836069 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 10:03:29.839867 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 10:03:29.843172 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 10:03:29.847067 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 10:03:29.854168 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 10:03:29.865408 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 10:03:29.869064 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 10:03:29.876708 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 10:03:29.883823 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 10:03:29.891150 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 10:03:29.894673 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 10:03:29.898199 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 10:03:29.905585 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x2
534 10:03:29.909050 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 10:03:29.918061 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
536 10:03:29.920933 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 10:03:29.930310 [RTC]rtc_get_frequency_meter,154: input=15, output=852
538 10:03:29.939710 [RTC]rtc_get_frequency_meter,154: input=7, output=724
539 10:03:29.948401 [RTC]rtc_get_frequency_meter,154: input=11, output=788
540 10:03:29.958420 [RTC]rtc_get_frequency_meter,154: input=13, output=820
541 10:03:29.968237 [RTC]rtc_get_frequency_meter,154: input=12, output=805
542 10:03:29.977674 [RTC]rtc_get_frequency_meter,154: input=11, output=789
543 10:03:29.987099 [RTC]rtc_get_frequency_meter,154: input=12, output=803
544 10:03:29.991030 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
545 10:03:29.994561 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
546 10:03:30.002245 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 10:03:30.005294 [RTC]rtc_boot_common,220: irqsta=1, bbpu=81, con=486
548 10:03:30.009007 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 10:03:30.012545 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 10:03:30.016994 ADC[4]: Raw value=903325 ID=7
551 10:03:30.017424 ADC[3]: Raw value=213916 ID=1
552 10:03:30.021000 RAM Code: 0x71
553 10:03:30.024497 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 10:03:30.027844 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 10:03:30.039714 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 10:03:30.043078 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 10:03:30.046716 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 10:03:30.050379 in-header: 03 07 00 00 08 00 00 00
559 10:03:30.054071 in-data: aa e4 47 04 13 02 00 00
560 10:03:30.057484 Chrome EC: UHEPI supported
561 10:03:30.064631 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 10:03:30.067866 in-header: 03 95 00 00 08 00 00 00
563 10:03:30.071901 in-data: 18 20 20 08 00 00 00 00
564 10:03:30.075857 MRC: failed to locate region type 0.
565 10:03:30.079099 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 10:03:30.082447 DRAM-K: Running full calibration
567 10:03:30.090247 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 10:03:30.090767 header.status = 0x0
569 10:03:30.093685 header.version = 0x6 (expected: 0x6)
570 10:03:30.097711 header.size = 0xd00 (expected: 0xd00)
571 10:03:30.100729 header.flags = 0x0
572 10:03:30.104460 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 10:03:30.125014 read SPI 0x72590 0x1c583: 12501 us, 9287 KB/s, 74.296 Mbps
574 10:03:30.131582 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 10:03:30.132013 dram_init: ddr_geometry: 2
576 10:03:30.135360 [EMI] MDL number = 2
577 10:03:30.139276 [EMI] Get MDL freq = 0
578 10:03:30.139772 dram_init: ddr_type: 0
579 10:03:30.142910 is_discrete_lpddr4: 1
580 10:03:30.146735 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 10:03:30.147339
582 10:03:30.147750
583 10:03:30.148068 [Bian_co] ETT version 0.0.0.1
584 10:03:30.153304 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 10:03:30.153857
586 10:03:30.157421 dramc_set_vcore_voltage set vcore to 650000
587 10:03:30.157989 Read voltage for 800, 4
588 10:03:30.161029 Vio18 = 0
589 10:03:30.161563 Vcore = 650000
590 10:03:30.161947 Vdram = 0
591 10:03:30.162333 Vddq = 0
592 10:03:30.164345 Vmddr = 0
593 10:03:30.164771 dram_init: config_dvfs: 1
594 10:03:30.171977 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 10:03:30.176129 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 10:03:30.179118 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
597 10:03:30.182795 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
598 10:03:30.189385 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
599 10:03:30.192273 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
600 10:03:30.192801 MEM_TYPE=3, freq_sel=18
601 10:03:30.195490 sv_algorithm_assistance_LP4_1600
602 10:03:30.198927 ============ PULL DRAM RESETB DOWN ============
603 10:03:30.206361 ========== PULL DRAM RESETB DOWN end =========
604 10:03:30.210418 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 10:03:30.213657 ===================================
606 10:03:30.214071 LPDDR4 DRAM CONFIGURATION
607 10:03:30.216997 ===================================
608 10:03:30.220758 EX_ROW_EN[0] = 0x0
609 10:03:30.223706 EX_ROW_EN[1] = 0x0
610 10:03:30.224122 LP4Y_EN = 0x0
611 10:03:30.227462 WORK_FSP = 0x0
612 10:03:30.228084 WL = 0x2
613 10:03:30.230662 RL = 0x2
614 10:03:30.231300 BL = 0x2
615 10:03:30.233541 RPST = 0x0
616 10:03:30.233965 RD_PRE = 0x0
617 10:03:30.236967 WR_PRE = 0x1
618 10:03:30.237390 WR_PST = 0x0
619 10:03:30.240831 DBI_WR = 0x0
620 10:03:30.241254 DBI_RD = 0x0
621 10:03:30.243833 OTF = 0x1
622 10:03:30.246913 ===================================
623 10:03:30.250179 ===================================
624 10:03:30.250658 ANA top config
625 10:03:30.254127 ===================================
626 10:03:30.257466 DLL_ASYNC_EN = 0
627 10:03:30.260420 ALL_SLAVE_EN = 1
628 10:03:30.260944 NEW_RANK_MODE = 1
629 10:03:30.264157 DLL_IDLE_MODE = 1
630 10:03:30.267201 LP45_APHY_COMB_EN = 1
631 10:03:30.270498 TX_ODT_DIS = 1
632 10:03:30.273798 NEW_8X_MODE = 1
633 10:03:30.277550 ===================================
634 10:03:30.280412 ===================================
635 10:03:30.280972 data_rate = 1600
636 10:03:30.284051 CKR = 1
637 10:03:30.286936 DQ_P2S_RATIO = 8
638 10:03:30.290733 ===================================
639 10:03:30.293938 CA_P2S_RATIO = 8
640 10:03:30.297649 DQ_CA_OPEN = 0
641 10:03:30.298303 DQ_SEMI_OPEN = 0
642 10:03:30.301202 CA_SEMI_OPEN = 0
643 10:03:30.304772 CA_FULL_RATE = 0
644 10:03:30.307557 DQ_CKDIV4_EN = 1
645 10:03:30.310984 CA_CKDIV4_EN = 1
646 10:03:30.314396 CA_PREDIV_EN = 0
647 10:03:30.314843 PH8_DLY = 0
648 10:03:30.317652 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 10:03:30.321043 DQ_AAMCK_DIV = 4
650 10:03:30.324139 CA_AAMCK_DIV = 4
651 10:03:30.327530 CA_ADMCK_DIV = 4
652 10:03:30.330731 DQ_TRACK_CA_EN = 0
653 10:03:30.331257 CA_PICK = 800
654 10:03:30.334299 CA_MCKIO = 800
655 10:03:30.337303 MCKIO_SEMI = 0
656 10:03:30.342178 PLL_FREQ = 3068
657 10:03:30.345528 DQ_UI_PI_RATIO = 32
658 10:03:30.346140 CA_UI_PI_RATIO = 0
659 10:03:30.349623 ===================================
660 10:03:30.352894 ===================================
661 10:03:30.356591 memory_type:LPDDR4
662 10:03:30.357100 GP_NUM : 10
663 10:03:30.360163 SRAM_EN : 1
664 10:03:30.360733 MD32_EN : 0
665 10:03:30.364111 ===================================
666 10:03:30.367852 [ANA_INIT] >>>>>>>>>>>>>>
667 10:03:30.371089 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 10:03:30.374690 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 10:03:30.378055 ===================================
670 10:03:30.378631 data_rate = 1600,PCW = 0X7600
671 10:03:30.381401 ===================================
672 10:03:30.388079 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 10:03:30.391577 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 10:03:30.398041 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 10:03:30.401616 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 10:03:30.404394 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 10:03:30.408148 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 10:03:30.411411 [ANA_INIT] flow start
679 10:03:30.414628 [ANA_INIT] PLL >>>>>>>>
680 10:03:30.415165 [ANA_INIT] PLL <<<<<<<<
681 10:03:30.418197 [ANA_INIT] MIDPI >>>>>>>>
682 10:03:30.420897 [ANA_INIT] MIDPI <<<<<<<<
683 10:03:30.421322 [ANA_INIT] DLL >>>>>>>>
684 10:03:30.424743 [ANA_INIT] flow end
685 10:03:30.427770 ============ LP4 DIFF to SE enter ============
686 10:03:30.431137 ============ LP4 DIFF to SE exit ============
687 10:03:30.434498 [ANA_INIT] <<<<<<<<<<<<<
688 10:03:30.437397 [Flow] Enable top DCM control >>>>>
689 10:03:30.440829 [Flow] Enable top DCM control <<<<<
690 10:03:30.444639 Enable DLL master slave shuffle
691 10:03:30.451362 ==============================================================
692 10:03:30.451852 Gating Mode config
693 10:03:30.457801 ==============================================================
694 10:03:30.461262 Config description:
695 10:03:30.467629 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 10:03:30.474366 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 10:03:30.481033 SELPH_MODE 0: By rank 1: By Phase
698 10:03:30.487679 ==============================================================
699 10:03:30.488202 GAT_TRACK_EN = 1
700 10:03:30.490836 RX_GATING_MODE = 2
701 10:03:30.493987 RX_GATING_TRACK_MODE = 2
702 10:03:30.497272 SELPH_MODE = 1
703 10:03:30.500484 PICG_EARLY_EN = 1
704 10:03:30.503917 VALID_LAT_VALUE = 1
705 10:03:30.510651 ==============================================================
706 10:03:30.514249 Enter into Gating configuration >>>>
707 10:03:30.517534 Exit from Gating configuration <<<<
708 10:03:30.520966 Enter into DVFS_PRE_config >>>>>
709 10:03:30.530774 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 10:03:30.533956 Exit from DVFS_PRE_config <<<<<
711 10:03:30.536921 Enter into PICG configuration >>>>
712 10:03:30.540420 Exit from PICG configuration <<<<
713 10:03:30.543720 [RX_INPUT] configuration >>>>>
714 10:03:30.544175 [RX_INPUT] configuration <<<<<
715 10:03:30.550619 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 10:03:30.557432 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 10:03:30.560503 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 10:03:30.567294 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 10:03:30.573744 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 10:03:30.581078 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 10:03:30.584008 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 10:03:30.587157 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 10:03:30.593936 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 10:03:30.597920 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 10:03:30.600592 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 10:03:30.606908 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 10:03:30.610613 ===================================
728 10:03:30.611208 LPDDR4 DRAM CONFIGURATION
729 10:03:30.613702 ===================================
730 10:03:30.617335 EX_ROW_EN[0] = 0x0
731 10:03:30.617887 EX_ROW_EN[1] = 0x0
732 10:03:30.620291 LP4Y_EN = 0x0
733 10:03:30.620747 WORK_FSP = 0x0
734 10:03:30.623353 WL = 0x2
735 10:03:30.623769 RL = 0x2
736 10:03:30.627392 BL = 0x2
737 10:03:30.630371 RPST = 0x0
738 10:03:30.630794 RD_PRE = 0x0
739 10:03:30.633228 WR_PRE = 0x1
740 10:03:30.633656 WR_PST = 0x0
741 10:03:30.636754 DBI_WR = 0x0
742 10:03:30.637167 DBI_RD = 0x0
743 10:03:30.640462 OTF = 0x1
744 10:03:30.643454 ===================================
745 10:03:30.647333 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 10:03:30.650497 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 10:03:30.653957 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 10:03:30.656973 ===================================
749 10:03:30.660185 LPDDR4 DRAM CONFIGURATION
750 10:03:30.663649 ===================================
751 10:03:30.666687 EX_ROW_EN[0] = 0x10
752 10:03:30.667151 EX_ROW_EN[1] = 0x0
753 10:03:30.670194 LP4Y_EN = 0x0
754 10:03:30.670645 WORK_FSP = 0x0
755 10:03:30.673897 WL = 0x2
756 10:03:30.674468 RL = 0x2
757 10:03:30.676885 BL = 0x2
758 10:03:30.677402 RPST = 0x0
759 10:03:30.679797 RD_PRE = 0x0
760 10:03:30.683246 WR_PRE = 0x1
761 10:03:30.683758 WR_PST = 0x0
762 10:03:30.686304 DBI_WR = 0x0
763 10:03:30.686721 DBI_RD = 0x0
764 10:03:30.690059 OTF = 0x1
765 10:03:30.693760 ===================================
766 10:03:30.696551 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 10:03:30.702345 nWR fixed to 40
768 10:03:30.705489 [ModeRegInit_LP4] CH0 RK0
769 10:03:30.705905 [ModeRegInit_LP4] CH0 RK1
770 10:03:30.708442 [ModeRegInit_LP4] CH1 RK0
771 10:03:30.712163 [ModeRegInit_LP4] CH1 RK1
772 10:03:30.712579 match AC timing 13
773 10:03:30.718581 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 10:03:30.721669 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 10:03:30.725166 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 10:03:30.731890 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 10:03:30.735196 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 10:03:30.735622 [EMI DOE] emi_dcm 0
779 10:03:30.741783 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 10:03:30.742200 ==
781 10:03:30.745362 Dram Type= 6, Freq= 0, CH_0, rank 0
782 10:03:30.748363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 10:03:30.748949 ==
784 10:03:30.754991 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 10:03:30.762045 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 10:03:30.769093 [CA 0] Center 37 (7~68) winsize 62
787 10:03:30.772701 [CA 1] Center 37 (7~68) winsize 62
788 10:03:30.776008 [CA 2] Center 34 (4~65) winsize 62
789 10:03:30.779358 [CA 3] Center 35 (4~66) winsize 63
790 10:03:30.782775 [CA 4] Center 33 (3~64) winsize 62
791 10:03:30.786164 [CA 5] Center 33 (3~64) winsize 62
792 10:03:30.786713
793 10:03:30.789264 [CmdBusTrainingLP45] Vref(ca) range 1: 32
794 10:03:30.789775
795 10:03:30.792449 [CATrainingPosCal] consider 1 rank data
796 10:03:30.795860 u2DelayCellTimex100 = 270/100 ps
797 10:03:30.799628 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
798 10:03:30.806133 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
799 10:03:30.808896 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
800 10:03:30.812494 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
801 10:03:30.815538 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
802 10:03:30.818716 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
803 10:03:30.819149
804 10:03:30.822486 CA PerBit enable=1, Macro0, CA PI delay=33
805 10:03:30.823005
806 10:03:30.825661 [CBTSetCACLKResult] CA Dly = 33
807 10:03:30.828560 CS Dly: 5 (0~36)
808 10:03:30.828986 ==
809 10:03:30.832726 Dram Type= 6, Freq= 0, CH_0, rank 1
810 10:03:30.835498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 10:03:30.835933 ==
812 10:03:30.841962 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 10:03:30.845381 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 10:03:30.855805 [CA 0] Center 38 (7~69) winsize 63
815 10:03:30.859291 [CA 1] Center 37 (7~68) winsize 62
816 10:03:30.862577 [CA 2] Center 35 (4~66) winsize 63
817 10:03:30.865642 [CA 3] Center 35 (4~66) winsize 63
818 10:03:30.868911 [CA 4] Center 34 (3~65) winsize 63
819 10:03:30.872046 [CA 5] Center 33 (3~64) winsize 62
820 10:03:30.872594
821 10:03:30.875700 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 10:03:30.876122
823 10:03:30.878987 [CATrainingPosCal] consider 2 rank data
824 10:03:30.881983 u2DelayCellTimex100 = 270/100 ps
825 10:03:30.885512 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
826 10:03:30.889221 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
827 10:03:30.895213 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
828 10:03:30.898604 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
829 10:03:30.902293 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
830 10:03:30.905740 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
831 10:03:30.906159
832 10:03:30.908627 CA PerBit enable=1, Macro0, CA PI delay=33
833 10:03:30.909050
834 10:03:30.911910 [CBTSetCACLKResult] CA Dly = 33
835 10:03:30.912331 CS Dly: 6 (0~38)
836 10:03:30.915083
837 10:03:30.918574 ----->DramcWriteLeveling(PI) begin...
838 10:03:30.919114 ==
839 10:03:30.922312 Dram Type= 6, Freq= 0, CH_0, rank 0
840 10:03:30.925744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 10:03:30.926306 ==
842 10:03:30.929336 Write leveling (Byte 0): 31 => 31
843 10:03:30.929755 Write leveling (Byte 1): 25 => 25
844 10:03:30.933205 DramcWriteLeveling(PI) end<-----
845 10:03:30.933629
846 10:03:30.933964 ==
847 10:03:30.936628 Dram Type= 6, Freq= 0, CH_0, rank 0
848 10:03:30.943149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 10:03:30.943576 ==
850 10:03:30.943914 [Gating] SW mode calibration
851 10:03:30.950731 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 10:03:30.957439 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 10:03:30.961602 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 10:03:30.967357 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
855 10:03:30.970511 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
856 10:03:30.974066 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
857 10:03:30.981317 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 10:03:30.984285 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 10:03:30.987837 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 10:03:30.991211 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 10:03:30.997618 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 10:03:31.000802 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 10:03:31.004135 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 10:03:31.010422 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 10:03:31.013789 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 10:03:31.017079 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 10:03:31.023719 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 10:03:31.027024 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 10:03:31.030349 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 10:03:31.036785 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
871 10:03:31.040041 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
872 10:03:31.043573 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 10:03:31.049965 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 10:03:31.053496 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 10:03:31.056767 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 10:03:31.063462 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 10:03:31.067169 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 10:03:31.070261 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 10:03:31.076820 0 9 8 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
880 10:03:31.079741 0 9 12 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
881 10:03:31.083437 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 10:03:31.089915 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 10:03:31.093226 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 10:03:31.096755 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 10:03:31.103315 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 10:03:31.106766 0 10 4 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
887 10:03:31.110340 0 10 8 | B1->B0 | 3131 2323 | 0 0 | (0 1) (0 0)
888 10:03:31.117013 0 10 12 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
889 10:03:31.120020 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 10:03:31.123240 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 10:03:31.126715 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 10:03:31.133464 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 10:03:31.136512 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 10:03:31.139942 0 11 4 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
895 10:03:31.147403 0 11 8 | B1->B0 | 2828 4242 | 0 0 | (0 0) (0 0)
896 10:03:31.150219 0 11 12 | B1->B0 | 3d3d 4646 | 1 0 | (0 0) (0 0)
897 10:03:31.153703 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 10:03:31.160006 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 10:03:31.163549 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 10:03:31.166725 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 10:03:31.173439 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 10:03:31.177135 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
903 10:03:31.180125 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 10:03:31.186487 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
905 10:03:31.190176 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 10:03:31.193552 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 10:03:31.200102 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 10:03:31.203452 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 10:03:31.206367 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 10:03:31.213510 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 10:03:31.216933 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 10:03:31.219832 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 10:03:31.226325 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 10:03:31.229860 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 10:03:31.233002 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 10:03:31.240556 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 10:03:31.242992 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 10:03:31.246156 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
919 10:03:31.252708 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
920 10:03:31.253133 Total UI for P1: 0, mck2ui 16
921 10:03:31.259314 best dqsien dly found for B0: ( 0, 14, 6)
922 10:03:31.262973 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
923 10:03:31.266438 Total UI for P1: 0, mck2ui 16
924 10:03:31.269573 best dqsien dly found for B1: ( 0, 14, 8)
925 10:03:31.272797 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
926 10:03:31.276455 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
927 10:03:31.277086
928 10:03:31.279613 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
929 10:03:31.282784 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
930 10:03:31.286161 [Gating] SW calibration Done
931 10:03:31.286614 ==
932 10:03:31.289200 Dram Type= 6, Freq= 0, CH_0, rank 0
933 10:03:31.293146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 10:03:31.293569 ==
935 10:03:31.296856 RX Vref Scan: 0
936 10:03:31.297479
937 10:03:31.298143 RX Vref 0 -> 0, step: 1
938 10:03:31.298765
939 10:03:31.300259 RX Delay -130 -> 252, step: 16
940 10:03:31.303639 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
941 10:03:31.310098 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
942 10:03:31.313254 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
943 10:03:31.316277 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
944 10:03:31.319849 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
945 10:03:31.323097 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
946 10:03:31.330220 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
947 10:03:31.333639 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
948 10:03:31.336705 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
949 10:03:31.339825 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
950 10:03:31.343041 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
951 10:03:31.349739 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
952 10:03:31.353055 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
953 10:03:31.356393 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
954 10:03:31.359834 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
955 10:03:31.366140 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
956 10:03:31.366673 ==
957 10:03:31.370201 Dram Type= 6, Freq= 0, CH_0, rank 0
958 10:03:31.373145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
959 10:03:31.373570 ==
960 10:03:31.373919 DQS Delay:
961 10:03:31.376395 DQS0 = 0, DQS1 = 0
962 10:03:31.376909 DQM Delay:
963 10:03:31.379916 DQM0 = 92, DQM1 = 76
964 10:03:31.380348 DQ Delay:
965 10:03:31.382988 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
966 10:03:31.386706 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
967 10:03:31.389558 DQ8 =69, DQ9 =53, DQ10 =77, DQ11 =69
968 10:03:31.392502 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
969 10:03:31.392986
970 10:03:31.393328
971 10:03:31.393634 ==
972 10:03:31.395942 Dram Type= 6, Freq= 0, CH_0, rank 0
973 10:03:31.399531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 10:03:31.400051 ==
975 10:03:31.403668
976 10:03:31.404202
977 10:03:31.404551 TX Vref Scan disable
978 10:03:31.406059 == TX Byte 0 ==
979 10:03:31.409363 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
980 10:03:31.412458 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
981 10:03:31.415739 == TX Byte 1 ==
982 10:03:31.419128 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
983 10:03:31.422717 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
984 10:03:31.423151 ==
985 10:03:31.425775 Dram Type= 6, Freq= 0, CH_0, rank 0
986 10:03:31.432060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 10:03:31.432562 ==
988 10:03:31.445806 TX Vref=22, minBit 0, minWin=27, winSum=439
989 10:03:31.448360 TX Vref=24, minBit 9, minWin=26, winSum=442
990 10:03:31.451982 TX Vref=26, minBit 1, minWin=27, winSum=446
991 10:03:31.455345 TX Vref=28, minBit 1, minWin=27, winSum=448
992 10:03:31.458368 TX Vref=30, minBit 1, minWin=27, winSum=451
993 10:03:31.464857 TX Vref=32, minBit 4, minWin=27, winSum=450
994 10:03:31.468239 [TxChooseVref] Worse bit 1, Min win 27, Win sum 451, Final Vref 30
995 10:03:31.468748
996 10:03:31.471743 Final TX Range 1 Vref 30
997 10:03:31.472252
998 10:03:31.472600 ==
999 10:03:31.474806 Dram Type= 6, Freq= 0, CH_0, rank 0
1000 10:03:31.478245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1001 10:03:31.478790 ==
1002 10:03:31.481677
1003 10:03:31.482229
1004 10:03:31.482785 TX Vref Scan disable
1005 10:03:31.484947 == TX Byte 0 ==
1006 10:03:31.488393 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1007 10:03:31.495273 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1008 10:03:31.495760 == TX Byte 1 ==
1009 10:03:31.498443 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1010 10:03:31.504924 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1011 10:03:31.505405
1012 10:03:31.505748 [DATLAT]
1013 10:03:31.506112 Freq=800, CH0 RK0
1014 10:03:31.506486
1015 10:03:31.508214 DATLAT Default: 0xa
1016 10:03:31.508633 0, 0xFFFF, sum = 0
1017 10:03:31.511816 1, 0xFFFF, sum = 0
1018 10:03:31.515254 2, 0xFFFF, sum = 0
1019 10:03:31.515883 3, 0xFFFF, sum = 0
1020 10:03:31.518468 4, 0xFFFF, sum = 0
1021 10:03:31.518910 5, 0xFFFF, sum = 0
1022 10:03:31.521856 6, 0xFFFF, sum = 0
1023 10:03:31.522328 7, 0xFFFF, sum = 0
1024 10:03:31.525048 8, 0xFFFF, sum = 0
1025 10:03:31.525599 9, 0x0, sum = 1
1026 10:03:31.528356 10, 0x0, sum = 2
1027 10:03:31.528814 11, 0x0, sum = 3
1028 10:03:31.529258 12, 0x0, sum = 4
1029 10:03:31.531173 best_step = 10
1030 10:03:31.531599
1031 10:03:31.532032 ==
1032 10:03:31.534679 Dram Type= 6, Freq= 0, CH_0, rank 0
1033 10:03:31.537820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1034 10:03:31.538241 ==
1035 10:03:31.541211 RX Vref Scan: 1
1036 10:03:31.541623
1037 10:03:31.544424 Set Vref Range= 32 -> 127
1038 10:03:31.544836
1039 10:03:31.545165 RX Vref 32 -> 127, step: 1
1040 10:03:31.545476
1041 10:03:31.547738 RX Delay -111 -> 252, step: 8
1042 10:03:31.548149
1043 10:03:31.551284 Set Vref, RX VrefLevel [Byte0]: 32
1044 10:03:31.554291 [Byte1]: 32
1045 10:03:31.557838
1046 10:03:31.558357 Set Vref, RX VrefLevel [Byte0]: 33
1047 10:03:31.561135 [Byte1]: 33
1048 10:03:31.565887
1049 10:03:31.566411 Set Vref, RX VrefLevel [Byte0]: 34
1050 10:03:31.568741 [Byte1]: 34
1051 10:03:31.573704
1052 10:03:31.574219 Set Vref, RX VrefLevel [Byte0]: 35
1053 10:03:31.576697 [Byte1]: 35
1054 10:03:31.580905
1055 10:03:31.581384 Set Vref, RX VrefLevel [Byte0]: 36
1056 10:03:31.584260 [Byte1]: 36
1057 10:03:31.589701
1058 10:03:31.590175 Set Vref, RX VrefLevel [Byte0]: 37
1059 10:03:31.592163 [Byte1]: 37
1060 10:03:31.597062
1061 10:03:31.597477 Set Vref, RX VrefLevel [Byte0]: 38
1062 10:03:31.600474 [Byte1]: 38
1063 10:03:31.603678
1064 10:03:31.604093 Set Vref, RX VrefLevel [Byte0]: 39
1065 10:03:31.607570 [Byte1]: 39
1066 10:03:31.612029
1067 10:03:31.612520 Set Vref, RX VrefLevel [Byte0]: 40
1068 10:03:31.614690 [Byte1]: 40
1069 10:03:31.619136
1070 10:03:31.619589 Set Vref, RX VrefLevel [Byte0]: 41
1071 10:03:31.623114 [Byte1]: 41
1072 10:03:31.626926
1073 10:03:31.627426 Set Vref, RX VrefLevel [Byte0]: 42
1074 10:03:31.633001 [Byte1]: 42
1075 10:03:31.633419
1076 10:03:31.636521 Set Vref, RX VrefLevel [Byte0]: 43
1077 10:03:31.640008 [Byte1]: 43
1078 10:03:31.640431
1079 10:03:31.642977 Set Vref, RX VrefLevel [Byte0]: 44
1080 10:03:31.646198 [Byte1]: 44
1081 10:03:31.650336
1082 10:03:31.650828 Set Vref, RX VrefLevel [Byte0]: 45
1083 10:03:31.653452 [Byte1]: 45
1084 10:03:31.657628
1085 10:03:31.658120 Set Vref, RX VrefLevel [Byte0]: 46
1086 10:03:31.661269 [Byte1]: 46
1087 10:03:31.665188
1088 10:03:31.665661 Set Vref, RX VrefLevel [Byte0]: 47
1089 10:03:31.668706 [Byte1]: 47
1090 10:03:31.672802
1091 10:03:31.673312 Set Vref, RX VrefLevel [Byte0]: 48
1092 10:03:31.676260 [Byte1]: 48
1093 10:03:31.680491
1094 10:03:31.680972 Set Vref, RX VrefLevel [Byte0]: 49
1095 10:03:31.683369 [Byte1]: 49
1096 10:03:31.687933
1097 10:03:31.688410 Set Vref, RX VrefLevel [Byte0]: 50
1098 10:03:31.691498 [Byte1]: 50
1099 10:03:31.695508
1100 10:03:31.695983 Set Vref, RX VrefLevel [Byte0]: 51
1101 10:03:31.699149 [Byte1]: 51
1102 10:03:31.703293
1103 10:03:31.703705 Set Vref, RX VrefLevel [Byte0]: 52
1104 10:03:31.706374 [Byte1]: 52
1105 10:03:31.710606
1106 10:03:31.711017 Set Vref, RX VrefLevel [Byte0]: 53
1107 10:03:31.714375 [Byte1]: 53
1108 10:03:31.718654
1109 10:03:31.719158 Set Vref, RX VrefLevel [Byte0]: 54
1110 10:03:31.722325 [Byte1]: 54
1111 10:03:31.725977
1112 10:03:31.726441 Set Vref, RX VrefLevel [Byte0]: 55
1113 10:03:31.729611 [Byte1]: 55
1114 10:03:31.733662
1115 10:03:31.734322 Set Vref, RX VrefLevel [Byte0]: 56
1116 10:03:31.737033 [Byte1]: 56
1117 10:03:31.741284
1118 10:03:31.741767 Set Vref, RX VrefLevel [Byte0]: 57
1119 10:03:31.744579 [Byte1]: 57
1120 10:03:31.748916
1121 10:03:31.749411 Set Vref, RX VrefLevel [Byte0]: 58
1122 10:03:31.752331 [Byte1]: 58
1123 10:03:31.757039
1124 10:03:31.757544 Set Vref, RX VrefLevel [Byte0]: 59
1125 10:03:31.760261 [Byte1]: 59
1126 10:03:31.764790
1127 10:03:31.765288 Set Vref, RX VrefLevel [Byte0]: 60
1128 10:03:31.767699 [Byte1]: 60
1129 10:03:31.772437
1130 10:03:31.772940 Set Vref, RX VrefLevel [Byte0]: 61
1131 10:03:31.775927 [Byte1]: 61
1132 10:03:31.779788
1133 10:03:31.780301 Set Vref, RX VrefLevel [Byte0]: 62
1134 10:03:31.782943 [Byte1]: 62
1135 10:03:31.787223
1136 10:03:31.787715 Set Vref, RX VrefLevel [Byte0]: 63
1137 10:03:31.790776 [Byte1]: 63
1138 10:03:31.795091
1139 10:03:31.795521 Set Vref, RX VrefLevel [Byte0]: 64
1140 10:03:31.798306 [Byte1]: 64
1141 10:03:31.802711
1142 10:03:31.803256 Set Vref, RX VrefLevel [Byte0]: 65
1143 10:03:31.806193 [Byte1]: 65
1144 10:03:31.810544
1145 10:03:31.811043 Set Vref, RX VrefLevel [Byte0]: 66
1146 10:03:31.813954 [Byte1]: 66
1147 10:03:31.818639
1148 10:03:31.819153 Set Vref, RX VrefLevel [Byte0]: 67
1149 10:03:31.821682 [Byte1]: 67
1150 10:03:31.825505
1151 10:03:31.825922 Set Vref, RX VrefLevel [Byte0]: 68
1152 10:03:31.829061 [Byte1]: 68
1153 10:03:31.833373
1154 10:03:31.833787 Set Vref, RX VrefLevel [Byte0]: 69
1155 10:03:31.836316 [Byte1]: 69
1156 10:03:31.840650
1157 10:03:31.841063 Set Vref, RX VrefLevel [Byte0]: 70
1158 10:03:31.844351 [Byte1]: 70
1159 10:03:31.848526
1160 10:03:31.849133 Set Vref, RX VrefLevel [Byte0]: 71
1161 10:03:31.851848 [Byte1]: 71
1162 10:03:31.856356
1163 10:03:31.856857 Set Vref, RX VrefLevel [Byte0]: 72
1164 10:03:31.859529 [Byte1]: 72
1165 10:03:31.864322
1166 10:03:31.864835 Set Vref, RX VrefLevel [Byte0]: 73
1167 10:03:31.867748 [Byte1]: 73
1168 10:03:31.871425
1169 10:03:31.871840 Final RX Vref Byte 0 = 58 to rank0
1170 10:03:31.874512 Final RX Vref Byte 1 = 56 to rank0
1171 10:03:31.878152 Final RX Vref Byte 0 = 58 to rank1
1172 10:03:31.881380 Final RX Vref Byte 1 = 56 to rank1==
1173 10:03:31.884891 Dram Type= 6, Freq= 0, CH_0, rank 0
1174 10:03:31.891544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1175 10:03:31.892070 ==
1176 10:03:31.892439 DQS Delay:
1177 10:03:31.894464 DQS0 = 0, DQS1 = 0
1178 10:03:31.895005 DQM Delay:
1179 10:03:31.895375 DQM0 = 88, DQM1 = 75
1180 10:03:31.897922 DQ Delay:
1181 10:03:31.901122 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1182 10:03:31.904537 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1183 10:03:31.907594 DQ8 =68, DQ9 =60, DQ10 =76, DQ11 =68
1184 10:03:31.911317 DQ12 =84, DQ13 =80, DQ14 =84, DQ15 =84
1185 10:03:31.911732
1186 10:03:31.912062
1187 10:03:31.917798 [DQSOSCAuto] RK0, (LSB)MR18= 0x2a24, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 399 ps
1188 10:03:31.921716 CH0 RK0: MR19=606, MR18=2A24
1189 10:03:31.927817 CH0_RK0: MR19=0x606, MR18=0x2A24, DQSOSC=399, MR23=63, INC=92, DEC=61
1190 10:03:31.928229
1191 10:03:31.931257 ----->DramcWriteLeveling(PI) begin...
1192 10:03:31.931760 ==
1193 10:03:31.934455 Dram Type= 6, Freq= 0, CH_0, rank 1
1194 10:03:31.937861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1195 10:03:31.938383 ==
1196 10:03:31.941126 Write leveling (Byte 0): 31 => 31
1197 10:03:31.944624 Write leveling (Byte 1): 26 => 26
1198 10:03:31.947523 DramcWriteLeveling(PI) end<-----
1199 10:03:31.947927
1200 10:03:31.948250 ==
1201 10:03:31.950740 Dram Type= 6, Freq= 0, CH_0, rank 1
1202 10:03:31.954720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1203 10:03:31.955200 ==
1204 10:03:31.957573 [Gating] SW mode calibration
1205 10:03:31.963983 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1206 10:03:31.970870 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1207 10:03:31.974245 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1208 10:03:31.977456 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1209 10:03:31.983962 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1210 10:03:32.028379 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 10:03:32.028907 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 10:03:32.029509 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 10:03:32.030522 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 10:03:32.031156 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 10:03:32.031730 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 10:03:32.032322 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 10:03:32.032920 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 10:03:32.033500 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 10:03:32.034012 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 10:03:32.058114 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 10:03:32.059181 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 10:03:32.059651 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 10:03:32.060007 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 10:03:32.060519 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1225 10:03:32.060877 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1226 10:03:32.062625 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 10:03:32.063042 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 10:03:32.065819 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 10:03:32.072286 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 10:03:32.076023 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 10:03:32.079424 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 10:03:32.085848 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1233 10:03:32.089426 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (0 0)
1234 10:03:32.092779 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1235 10:03:32.098790 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1236 10:03:32.102366 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1237 10:03:32.105300 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1238 10:03:32.112548 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1239 10:03:32.115393 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1240 10:03:32.119151 0 10 4 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
1241 10:03:32.125468 0 10 8 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
1242 10:03:32.128486 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 10:03:32.132109 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 10:03:32.138792 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 10:03:32.142064 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 10:03:32.145680 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 10:03:32.151671 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 10:03:32.155541 0 11 4 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
1249 10:03:32.158383 0 11 8 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
1250 10:03:32.165616 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1251 10:03:32.168820 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1252 10:03:32.172396 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1253 10:03:32.175923 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1254 10:03:32.180355 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1255 10:03:32.186947 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1256 10:03:32.190452 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1257 10:03:32.193958 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1258 10:03:32.198110 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1259 10:03:32.204941 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1260 10:03:32.208332 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1261 10:03:32.211643 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1262 10:03:32.217917 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1263 10:03:32.221471 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1264 10:03:32.224355 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1265 10:03:32.231316 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 10:03:32.234457 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 10:03:32.237636 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 10:03:32.244564 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 10:03:32.247851 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 10:03:32.250808 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 10:03:32.257499 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 10:03:32.260909 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 10:03:32.264139 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1274 10:03:32.267729 Total UI for P1: 0, mck2ui 16
1275 10:03:32.270756 best dqsien dly found for B0: ( 0, 14, 6)
1276 10:03:32.274397 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1277 10:03:32.277118 Total UI for P1: 0, mck2ui 16
1278 10:03:32.280868 best dqsien dly found for B1: ( 0, 14, 8)
1279 10:03:32.284246 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1280 10:03:32.290969 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1281 10:03:32.291475
1282 10:03:32.294318 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1283 10:03:32.297674 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1284 10:03:32.300710 [Gating] SW calibration Done
1285 10:03:32.301317 ==
1286 10:03:32.303895 Dram Type= 6, Freq= 0, CH_0, rank 1
1287 10:03:32.307110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1288 10:03:32.307531 ==
1289 10:03:32.307867 RX Vref Scan: 0
1290 10:03:32.308401
1291 10:03:32.310977 RX Vref 0 -> 0, step: 1
1292 10:03:32.311397
1293 10:03:32.314157 RX Delay -130 -> 252, step: 16
1294 10:03:32.317404 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1295 10:03:32.320923 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
1296 10:03:32.327228 iDelay=206, Bit 2, Center 85 (-18 ~ 189) 208
1297 10:03:32.330649 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1298 10:03:32.334055 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1299 10:03:32.336908 iDelay=206, Bit 5, Center 69 (-50 ~ 189) 240
1300 10:03:32.340372 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1301 10:03:32.347418 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1302 10:03:32.350820 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1303 10:03:32.353472 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1304 10:03:32.356866 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1305 10:03:32.360106 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1306 10:03:32.366990 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1307 10:03:32.370450 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1308 10:03:32.373916 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1309 10:03:32.377085 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1310 10:03:32.377501 ==
1311 10:03:32.380472 Dram Type= 6, Freq= 0, CH_0, rank 1
1312 10:03:32.387332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1313 10:03:32.387770 ==
1314 10:03:32.388125 DQS Delay:
1315 10:03:32.390044 DQS0 = 0, DQS1 = 0
1316 10:03:32.390629 DQM Delay:
1317 10:03:32.390971 DQM0 = 88, DQM1 = 77
1318 10:03:32.394100 DQ Delay:
1319 10:03:32.396917 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
1320 10:03:32.400428 DQ4 =93, DQ5 =69, DQ6 =93, DQ7 =93
1321 10:03:32.403347 DQ8 =69, DQ9 =61, DQ10 =69, DQ11 =69
1322 10:03:32.406758 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
1323 10:03:32.407332
1324 10:03:32.407673
1325 10:03:32.408083 ==
1326 10:03:32.409829 Dram Type= 6, Freq= 0, CH_0, rank 1
1327 10:03:32.413768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1328 10:03:32.414376 ==
1329 10:03:32.414722
1330 10:03:32.415030
1331 10:03:32.416474 TX Vref Scan disable
1332 10:03:32.419986 == TX Byte 0 ==
1333 10:03:32.423633 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1334 10:03:32.426916 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1335 10:03:32.427376 == TX Byte 1 ==
1336 10:03:32.433662 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1337 10:03:32.437086 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1338 10:03:32.437552 ==
1339 10:03:32.439849 Dram Type= 6, Freq= 0, CH_0, rank 1
1340 10:03:32.443670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1341 10:03:32.444118 ==
1342 10:03:32.458335 TX Vref=22, minBit 3, minWin=27, winSum=443
1343 10:03:32.461837 TX Vref=24, minBit 1, minWin=27, winSum=445
1344 10:03:32.464731 TX Vref=26, minBit 1, minWin=27, winSum=448
1345 10:03:32.468147 TX Vref=28, minBit 9, minWin=27, winSum=452
1346 10:03:32.471463 TX Vref=30, minBit 2, minWin=27, winSum=450
1347 10:03:32.478117 TX Vref=32, minBit 0, minWin=28, winSum=450
1348 10:03:32.481307 [TxChooseVref] Worse bit 0, Min win 28, Win sum 450, Final Vref 32
1349 10:03:32.481718
1350 10:03:32.484660 Final TX Range 1 Vref 32
1351 10:03:32.485142
1352 10:03:32.485465 ==
1353 10:03:32.487992 Dram Type= 6, Freq= 0, CH_0, rank 1
1354 10:03:32.491374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1355 10:03:32.494670 ==
1356 10:03:32.495082
1357 10:03:32.495404
1358 10:03:32.495703 TX Vref Scan disable
1359 10:03:32.497906 == TX Byte 0 ==
1360 10:03:32.501197 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1361 10:03:32.507966 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1362 10:03:32.508372 == TX Byte 1 ==
1363 10:03:32.511558 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1364 10:03:32.518420 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1365 10:03:32.518829
1366 10:03:32.519148 [DATLAT]
1367 10:03:32.519445 Freq=800, CH0 RK1
1368 10:03:32.519792
1369 10:03:32.521434 DATLAT Default: 0xa
1370 10:03:32.521857 0, 0xFFFF, sum = 0
1371 10:03:32.524702 1, 0xFFFF, sum = 0
1372 10:03:32.524993 2, 0xFFFF, sum = 0
1373 10:03:32.528099 3, 0xFFFF, sum = 0
1374 10:03:32.530840 4, 0xFFFF, sum = 0
1375 10:03:32.531147 5, 0xFFFF, sum = 0
1376 10:03:32.534328 6, 0xFFFF, sum = 0
1377 10:03:32.534620 7, 0xFFFF, sum = 0
1378 10:03:32.537837 8, 0xFFFF, sum = 0
1379 10:03:32.538128 9, 0x0, sum = 1
1380 10:03:32.538405 10, 0x0, sum = 2
1381 10:03:32.541017 11, 0x0, sum = 3
1382 10:03:32.541410 12, 0x0, sum = 4
1383 10:03:32.544056 best_step = 10
1384 10:03:32.544413
1385 10:03:32.544642 ==
1386 10:03:32.548083 Dram Type= 6, Freq= 0, CH_0, rank 1
1387 10:03:32.551215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1388 10:03:32.551502 ==
1389 10:03:32.554464 RX Vref Scan: 0
1390 10:03:32.554753
1391 10:03:32.554983 RX Vref 0 -> 0, step: 1
1392 10:03:32.558028
1393 10:03:32.558342 RX Delay -95 -> 252, step: 8
1394 10:03:32.564744 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1395 10:03:32.568134 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1396 10:03:32.571273 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1397 10:03:32.574453 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1398 10:03:32.578052 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1399 10:03:32.584543 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1400 10:03:32.588375 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1401 10:03:32.591595 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1402 10:03:32.594683 iDelay=209, Bit 8, Center 68 (-47 ~ 184) 232
1403 10:03:32.598480 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1404 10:03:32.604420 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1405 10:03:32.608387 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
1406 10:03:32.611052 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1407 10:03:32.614874 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1408 10:03:32.621603 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1409 10:03:32.624884 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1410 10:03:32.625385 ==
1411 10:03:32.627449 Dram Type= 6, Freq= 0, CH_0, rank 1
1412 10:03:32.631250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1413 10:03:32.631752 ==
1414 10:03:32.634651 DQS Delay:
1415 10:03:32.635156 DQS0 = 0, DQS1 = 0
1416 10:03:32.635478 DQM Delay:
1417 10:03:32.638417 DQM0 = 86, DQM1 = 77
1418 10:03:32.638926 DQ Delay:
1419 10:03:32.641126 DQ0 =84, DQ1 =88, DQ2 =80, DQ3 =80
1420 10:03:32.644245 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1421 10:03:32.647654 DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =72
1422 10:03:32.650901 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1423 10:03:32.651351
1424 10:03:32.651707
1425 10:03:32.661167 [DQSOSCAuto] RK1, (LSB)MR18= 0x2c28, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 398 ps
1426 10:03:32.661728 CH0 RK1: MR19=606, MR18=2C28
1427 10:03:32.667411 CH0_RK1: MR19=0x606, MR18=0x2C28, DQSOSC=398, MR23=63, INC=93, DEC=62
1428 10:03:32.670722 [RxdqsGatingPostProcess] freq 800
1429 10:03:32.677200 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1430 10:03:32.680791 Pre-setting of DQS Precalculation
1431 10:03:32.684082 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1432 10:03:32.684590 ==
1433 10:03:32.687546 Dram Type= 6, Freq= 0, CH_1, rank 0
1434 10:03:32.694140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1435 10:03:32.694733 ==
1436 10:03:32.697761 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1437 10:03:32.703708 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1438 10:03:32.713387 [CA 0] Center 37 (6~68) winsize 63
1439 10:03:32.716570 [CA 1] Center 37 (6~68) winsize 63
1440 10:03:32.720154 [CA 2] Center 34 (4~65) winsize 62
1441 10:03:32.722971 [CA 3] Center 34 (4~65) winsize 62
1442 10:03:32.726466 [CA 4] Center 34 (4~65) winsize 62
1443 10:03:32.729997 [CA 5] Center 34 (3~65) winsize 63
1444 10:03:32.730581
1445 10:03:32.732885 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1446 10:03:32.733335
1447 10:03:32.736438 [CATrainingPosCal] consider 1 rank data
1448 10:03:32.739548 u2DelayCellTimex100 = 270/100 ps
1449 10:03:32.743065 CA0 delay=37 (6~68),Diff = 3 PI (21 cell)
1450 10:03:32.749956 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1451 10:03:32.752639 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1452 10:03:32.756008 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1453 10:03:32.759586 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1454 10:03:32.762947 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1455 10:03:32.763490
1456 10:03:32.766025 CA PerBit enable=1, Macro0, CA PI delay=34
1457 10:03:32.766614
1458 10:03:32.769370 [CBTSetCACLKResult] CA Dly = 34
1459 10:03:32.772822 CS Dly: 4 (0~35)
1460 10:03:32.773268 ==
1461 10:03:32.776083 Dram Type= 6, Freq= 0, CH_1, rank 1
1462 10:03:32.779638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1463 10:03:32.780183 ==
1464 10:03:32.786006 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1465 10:03:32.789272 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1466 10:03:32.799914 [CA 0] Center 36 (6~67) winsize 62
1467 10:03:32.802785 [CA 1] Center 36 (6~67) winsize 62
1468 10:03:32.805829 [CA 2] Center 34 (4~65) winsize 62
1469 10:03:32.809399 [CA 3] Center 34 (3~65) winsize 63
1470 10:03:32.812568 [CA 4] Center 34 (3~65) winsize 63
1471 10:03:32.815821 [CA 5] Center 33 (3~64) winsize 62
1472 10:03:32.816378
1473 10:03:32.819529 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1474 10:03:32.819939
1475 10:03:32.822468 [CATrainingPosCal] consider 2 rank data
1476 10:03:32.826244 u2DelayCellTimex100 = 270/100 ps
1477 10:03:32.829211 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1478 10:03:32.832425 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1479 10:03:32.836197 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1480 10:03:32.840208 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1481 10:03:32.843415 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1482 10:03:32.850769 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1483 10:03:32.851370
1484 10:03:32.853996 CA PerBit enable=1, Macro0, CA PI delay=33
1485 10:03:32.854579
1486 10:03:32.854947 [CBTSetCACLKResult] CA Dly = 33
1487 10:03:32.857525 CS Dly: 5 (0~37)
1488 10:03:32.858051
1489 10:03:32.861332 ----->DramcWriteLeveling(PI) begin...
1490 10:03:32.862043 ==
1491 10:03:32.864861 Dram Type= 6, Freq= 0, CH_1, rank 0
1492 10:03:32.869057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1493 10:03:32.869685 ==
1494 10:03:32.872103 Write leveling (Byte 0): 25 => 25
1495 10:03:32.875164 Write leveling (Byte 1): 28 => 28
1496 10:03:32.878642 DramcWriteLeveling(PI) end<-----
1497 10:03:32.879150
1498 10:03:32.879484 ==
1499 10:03:32.881992 Dram Type= 6, Freq= 0, CH_1, rank 0
1500 10:03:32.885266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1501 10:03:32.885682 ==
1502 10:03:32.888487 [Gating] SW mode calibration
1503 10:03:32.895312 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1504 10:03:32.901962 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1505 10:03:32.904850 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1506 10:03:32.908763 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1507 10:03:32.914838 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 10:03:32.918768 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 10:03:32.921858 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 10:03:32.928219 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 10:03:32.931890 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 10:03:32.935230 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 10:03:32.941747 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 10:03:32.944737 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 10:03:32.948236 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 10:03:32.954939 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 10:03:32.958082 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 10:03:32.961452 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 10:03:32.968091 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 10:03:32.971096 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 10:03:32.974949 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 10:03:32.981110 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1523 10:03:32.984956 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1524 10:03:32.987902 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 10:03:32.994173 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 10:03:32.997655 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 10:03:33.001074 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 10:03:33.008066 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 10:03:33.011066 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 10:03:33.013928 0 9 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1531 10:03:33.021187 0 9 8 | B1->B0 | 3030 3434 | 0 0 | (0 0) (0 0)
1532 10:03:33.024240 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1533 10:03:33.027547 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1534 10:03:33.033779 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1535 10:03:33.036901 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1536 10:03:33.040166 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1537 10:03:33.047359 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1538 10:03:33.050192 0 10 4 | B1->B0 | 3333 2f2f | 1 1 | (1 1) (1 1)
1539 10:03:33.053656 0 10 8 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1540 10:03:33.060786 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 10:03:33.063656 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 10:03:33.067530 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 10:03:33.071052 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 10:03:33.077028 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 10:03:33.080578 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 10:03:33.084044 0 11 4 | B1->B0 | 2726 2c2c | 1 0 | (0 0) (0 0)
1547 10:03:33.090919 0 11 8 | B1->B0 | 3c3c 4444 | 0 0 | (0 0) (0 0)
1548 10:03:33.093260 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1549 10:03:33.096827 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1550 10:03:33.103322 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1551 10:03:33.106892 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1552 10:03:33.110477 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1553 10:03:33.116794 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1554 10:03:33.120287 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1555 10:03:33.123612 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1556 10:03:33.130127 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1557 10:03:33.133046 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1558 10:03:33.136484 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1559 10:03:33.143590 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1560 10:03:33.146434 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1561 10:03:33.149856 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1562 10:03:33.156441 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1563 10:03:33.159996 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 10:03:33.162796 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 10:03:33.169546 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 10:03:33.172918 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 10:03:33.176331 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 10:03:33.182852 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 10:03:33.186136 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 10:03:33.189500 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1571 10:03:33.196167 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1572 10:03:33.196595 Total UI for P1: 0, mck2ui 16
1573 10:03:33.202748 best dqsien dly found for B0: ( 0, 14, 4)
1574 10:03:33.206089 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1575 10:03:33.209240 Total UI for P1: 0, mck2ui 16
1576 10:03:33.212811 best dqsien dly found for B1: ( 0, 14, 6)
1577 10:03:33.216154 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1578 10:03:33.219624 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1579 10:03:33.220081
1580 10:03:33.223045 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1581 10:03:33.225798 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1582 10:03:33.229271 [Gating] SW calibration Done
1583 10:03:33.229720 ==
1584 10:03:33.232551 Dram Type= 6, Freq= 0, CH_1, rank 0
1585 10:03:33.235779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1586 10:03:33.239132 ==
1587 10:03:33.239539 RX Vref Scan: 0
1588 10:03:33.239865
1589 10:03:33.242135 RX Vref 0 -> 0, step: 1
1590 10:03:33.242587
1591 10:03:33.246187 RX Delay -130 -> 252, step: 16
1592 10:03:33.248788 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1593 10:03:33.252654 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1594 10:03:33.255615 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1595 10:03:33.258797 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1596 10:03:33.266089 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1597 10:03:33.269029 iDelay=222, Bit 5, Center 93 (-18 ~ 205) 224
1598 10:03:33.272872 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1599 10:03:33.275749 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1600 10:03:33.278934 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1601 10:03:33.282203 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1602 10:03:33.289059 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1603 10:03:33.292424 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1604 10:03:33.295715 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1605 10:03:33.299604 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1606 10:03:33.305886 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1607 10:03:33.309228 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1608 10:03:33.309739 ==
1609 10:03:33.312291 Dram Type= 6, Freq= 0, CH_1, rank 0
1610 10:03:33.315304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1611 10:03:33.315811 ==
1612 10:03:33.318910 DQS Delay:
1613 10:03:33.319317 DQS0 = 0, DQS1 = 0
1614 10:03:33.319641 DQM Delay:
1615 10:03:33.322394 DQM0 = 85, DQM1 = 79
1616 10:03:33.322899 DQ Delay:
1617 10:03:33.325605 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1618 10:03:33.329203 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =85
1619 10:03:33.332501 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1620 10:03:33.335182 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1621 10:03:33.335598
1622 10:03:33.335917
1623 10:03:33.336213 ==
1624 10:03:33.338775 Dram Type= 6, Freq= 0, CH_1, rank 0
1625 10:03:33.345797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1626 10:03:33.346355 ==
1627 10:03:33.346696
1628 10:03:33.346999
1629 10:03:33.347284 TX Vref Scan disable
1630 10:03:33.348913 == TX Byte 0 ==
1631 10:03:33.352778 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1632 10:03:33.358809 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1633 10:03:33.359467 == TX Byte 1 ==
1634 10:03:33.361999 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1635 10:03:33.368840 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1636 10:03:33.369295 ==
1637 10:03:33.372216 Dram Type= 6, Freq= 0, CH_1, rank 0
1638 10:03:33.375076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1639 10:03:33.375501 ==
1640 10:03:33.387933 TX Vref=22, minBit 3, minWin=26, winSum=439
1641 10:03:33.391116 TX Vref=24, minBit 3, minWin=27, winSum=446
1642 10:03:33.395025 TX Vref=26, minBit 2, minWin=27, winSum=449
1643 10:03:33.397885 TX Vref=28, minBit 5, minWin=27, winSum=455
1644 10:03:33.401559 TX Vref=30, minBit 5, minWin=27, winSum=455
1645 10:03:33.408223 TX Vref=32, minBit 6, minWin=27, winSum=454
1646 10:03:33.411517 [TxChooseVref] Worse bit 5, Min win 27, Win sum 455, Final Vref 28
1647 10:03:33.412024
1648 10:03:33.415111 Final TX Range 1 Vref 28
1649 10:03:33.415524
1650 10:03:33.415847 ==
1651 10:03:33.418715 Dram Type= 6, Freq= 0, CH_1, rank 0
1652 10:03:33.422059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1653 10:03:33.422628 ==
1654 10:03:33.422994
1655 10:03:33.423327
1656 10:03:33.424822 TX Vref Scan disable
1657 10:03:33.428396 == TX Byte 0 ==
1658 10:03:33.431779 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1659 10:03:33.435407 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1660 10:03:33.438714 == TX Byte 1 ==
1661 10:03:33.441778 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1662 10:03:33.445221 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1663 10:03:33.445648
1664 10:03:33.448236 [DATLAT]
1665 10:03:33.448643 Freq=800, CH1 RK0
1666 10:03:33.448967
1667 10:03:33.452077 DATLAT Default: 0xa
1668 10:03:33.452575 0, 0xFFFF, sum = 0
1669 10:03:33.455301 1, 0xFFFF, sum = 0
1670 10:03:33.455718 2, 0xFFFF, sum = 0
1671 10:03:33.458685 3, 0xFFFF, sum = 0
1672 10:03:33.459096 4, 0xFFFF, sum = 0
1673 10:03:33.461871 5, 0xFFFF, sum = 0
1674 10:03:33.462342 6, 0xFFFF, sum = 0
1675 10:03:33.464967 7, 0xFFFF, sum = 0
1676 10:03:33.465381 8, 0xFFFF, sum = 0
1677 10:03:33.468618 9, 0x0, sum = 1
1678 10:03:33.468988 10, 0x0, sum = 2
1679 10:03:33.471988 11, 0x0, sum = 3
1680 10:03:33.472400 12, 0x0, sum = 4
1681 10:03:33.475343 best_step = 10
1682 10:03:33.475750
1683 10:03:33.476074 ==
1684 10:03:33.478512 Dram Type= 6, Freq= 0, CH_1, rank 0
1685 10:03:33.481846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1686 10:03:33.482281 ==
1687 10:03:33.485293 RX Vref Scan: 1
1688 10:03:33.486031
1689 10:03:33.486431 Set Vref Range= 32 -> 127
1690 10:03:33.486749
1691 10:03:33.488392 RX Vref 32 -> 127, step: 1
1692 10:03:33.488798
1693 10:03:33.492041 RX Delay -95 -> 252, step: 8
1694 10:03:33.492497
1695 10:03:33.494805 Set Vref, RX VrefLevel [Byte0]: 32
1696 10:03:33.498133 [Byte1]: 32
1697 10:03:33.498735
1698 10:03:33.501691 Set Vref, RX VrefLevel [Byte0]: 33
1699 10:03:33.504777 [Byte1]: 33
1700 10:03:33.508747
1701 10:03:33.509251 Set Vref, RX VrefLevel [Byte0]: 34
1702 10:03:33.511789 [Byte1]: 34
1703 10:03:33.516063
1704 10:03:33.516567 Set Vref, RX VrefLevel [Byte0]: 35
1705 10:03:33.519110 [Byte1]: 35
1706 10:03:33.523514
1707 10:03:33.523921 Set Vref, RX VrefLevel [Byte0]: 36
1708 10:03:33.527150 [Byte1]: 36
1709 10:03:33.530989
1710 10:03:33.531393 Set Vref, RX VrefLevel [Byte0]: 37
1711 10:03:33.534497 [Byte1]: 37
1712 10:03:33.539169
1713 10:03:33.539699 Set Vref, RX VrefLevel [Byte0]: 38
1714 10:03:33.542183 [Byte1]: 38
1715 10:03:33.546075
1716 10:03:33.546601 Set Vref, RX VrefLevel [Byte0]: 39
1717 10:03:33.549465 [Byte1]: 39
1718 10:03:33.553664
1719 10:03:33.554185 Set Vref, RX VrefLevel [Byte0]: 40
1720 10:03:33.556859 [Byte1]: 40
1721 10:03:33.561693
1722 10:03:33.562208 Set Vref, RX VrefLevel [Byte0]: 41
1723 10:03:33.564738 [Byte1]: 41
1724 10:03:33.569203
1725 10:03:33.569699 Set Vref, RX VrefLevel [Byte0]: 42
1726 10:03:33.572275 [Byte1]: 42
1727 10:03:33.576737
1728 10:03:33.577250 Set Vref, RX VrefLevel [Byte0]: 43
1729 10:03:33.580471 [Byte1]: 43
1730 10:03:33.584283
1731 10:03:33.584782 Set Vref, RX VrefLevel [Byte0]: 44
1732 10:03:33.587544 [Byte1]: 44
1733 10:03:33.591837
1734 10:03:33.592329 Set Vref, RX VrefLevel [Byte0]: 45
1735 10:03:33.595156 [Byte1]: 45
1736 10:03:33.599337
1737 10:03:33.599743 Set Vref, RX VrefLevel [Byte0]: 46
1738 10:03:33.602563 [Byte1]: 46
1739 10:03:33.607013
1740 10:03:33.607579 Set Vref, RX VrefLevel [Byte0]: 47
1741 10:03:33.610174 [Byte1]: 47
1742 10:03:33.614489
1743 10:03:33.614918 Set Vref, RX VrefLevel [Byte0]: 48
1744 10:03:33.617701 [Byte1]: 48
1745 10:03:33.622495
1746 10:03:33.622985 Set Vref, RX VrefLevel [Byte0]: 49
1747 10:03:33.625393 [Byte1]: 49
1748 10:03:33.630158
1749 10:03:33.630733 Set Vref, RX VrefLevel [Byte0]: 50
1750 10:03:33.632729 [Byte1]: 50
1751 10:03:33.637946
1752 10:03:33.638495 Set Vref, RX VrefLevel [Byte0]: 51
1753 10:03:33.641306 [Byte1]: 51
1754 10:03:33.644900
1755 10:03:33.645306 Set Vref, RX VrefLevel [Byte0]: 52
1756 10:03:33.648105 [Byte1]: 52
1757 10:03:33.652864
1758 10:03:33.653328 Set Vref, RX VrefLevel [Byte0]: 53
1759 10:03:33.655933 [Byte1]: 53
1760 10:03:33.660659
1761 10:03:33.661163 Set Vref, RX VrefLevel [Byte0]: 54
1762 10:03:33.663573 [Byte1]: 54
1763 10:03:33.667609
1764 10:03:33.668017 Set Vref, RX VrefLevel [Byte0]: 55
1765 10:03:33.670937 [Byte1]: 55
1766 10:03:33.675415
1767 10:03:33.675916 Set Vref, RX VrefLevel [Byte0]: 56
1768 10:03:33.678883 [Byte1]: 56
1769 10:03:33.683219
1770 10:03:33.683723 Set Vref, RX VrefLevel [Byte0]: 57
1771 10:03:33.686629 [Byte1]: 57
1772 10:03:33.690605
1773 10:03:33.691129 Set Vref, RX VrefLevel [Byte0]: 58
1774 10:03:33.694027 [Byte1]: 58
1775 10:03:33.698626
1776 10:03:33.699124 Set Vref, RX VrefLevel [Byte0]: 59
1777 10:03:33.701899 [Byte1]: 59
1778 10:03:33.706105
1779 10:03:33.706558 Set Vref, RX VrefLevel [Byte0]: 60
1780 10:03:33.709042 [Byte1]: 60
1781 10:03:33.713545
1782 10:03:33.714056 Set Vref, RX VrefLevel [Byte0]: 61
1783 10:03:33.716915 [Byte1]: 61
1784 10:03:33.721354
1785 10:03:33.721861 Set Vref, RX VrefLevel [Byte0]: 62
1786 10:03:33.724274 [Byte1]: 62
1787 10:03:33.728770
1788 10:03:33.729275 Set Vref, RX VrefLevel [Byte0]: 63
1789 10:03:33.731778 [Byte1]: 63
1790 10:03:33.736338
1791 10:03:33.736906 Set Vref, RX VrefLevel [Byte0]: 64
1792 10:03:33.739497 [Byte1]: 64
1793 10:03:33.743676
1794 10:03:33.744084 Set Vref, RX VrefLevel [Byte0]: 65
1795 10:03:33.746964 [Byte1]: 65
1796 10:03:33.751486
1797 10:03:33.751915 Set Vref, RX VrefLevel [Byte0]: 66
1798 10:03:33.755352 [Byte1]: 66
1799 10:03:33.758733
1800 10:03:33.759140 Set Vref, RX VrefLevel [Byte0]: 67
1801 10:03:33.762127 [Byte1]: 67
1802 10:03:33.766687
1803 10:03:33.767200 Set Vref, RX VrefLevel [Byte0]: 68
1804 10:03:33.770319 [Byte1]: 68
1805 10:03:33.774505
1806 10:03:33.775054 Set Vref, RX VrefLevel [Byte0]: 69
1807 10:03:33.778044 [Byte1]: 69
1808 10:03:33.781966
1809 10:03:33.782580 Set Vref, RX VrefLevel [Byte0]: 70
1810 10:03:33.785263 [Byte1]: 70
1811 10:03:33.789397
1812 10:03:33.789961 Set Vref, RX VrefLevel [Byte0]: 71
1813 10:03:33.793175 [Byte1]: 71
1814 10:03:33.796871
1815 10:03:33.797330 Set Vref, RX VrefLevel [Byte0]: 72
1816 10:03:33.800711 [Byte1]: 72
1817 10:03:33.804749
1818 10:03:33.805297 Set Vref, RX VrefLevel [Byte0]: 73
1819 10:03:33.807626 [Byte1]: 73
1820 10:03:33.812105
1821 10:03:33.812613 Final RX Vref Byte 0 = 55 to rank0
1822 10:03:33.815559 Final RX Vref Byte 1 = 59 to rank0
1823 10:03:33.818907 Final RX Vref Byte 0 = 55 to rank1
1824 10:03:33.822286 Final RX Vref Byte 1 = 59 to rank1==
1825 10:03:33.825553 Dram Type= 6, Freq= 0, CH_1, rank 0
1826 10:03:33.831676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1827 10:03:33.832101 ==
1828 10:03:33.832451 DQS Delay:
1829 10:03:33.835328 DQS0 = 0, DQS1 = 0
1830 10:03:33.835743 DQM Delay:
1831 10:03:33.836077 DQM0 = 84, DQM1 = 80
1832 10:03:33.838308 DQ Delay:
1833 10:03:33.841984 DQ0 =92, DQ1 =80, DQ2 =72, DQ3 =84
1834 10:03:33.844725 DQ4 =80, DQ5 =92, DQ6 =96, DQ7 =80
1835 10:03:33.848776 DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =72
1836 10:03:33.851450 DQ12 =88, DQ13 =92, DQ14 =84, DQ15 =84
1837 10:03:33.851872
1838 10:03:33.852200
1839 10:03:33.858507 [DQSOSCAuto] RK0, (LSB)MR18= 0x1c2f, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 402 ps
1840 10:03:33.862018 CH1 RK0: MR19=606, MR18=1C2F
1841 10:03:33.868382 CH1_RK0: MR19=0x606, MR18=0x1C2F, DQSOSC=397, MR23=63, INC=93, DEC=62
1842 10:03:33.868902
1843 10:03:33.871948 ----->DramcWriteLeveling(PI) begin...
1844 10:03:33.872473 ==
1845 10:03:33.874507 Dram Type= 6, Freq= 0, CH_1, rank 1
1846 10:03:33.878050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1847 10:03:33.878600 ==
1848 10:03:33.881465 Write leveling (Byte 0): 28 => 28
1849 10:03:33.884465 Write leveling (Byte 1): 28 => 28
1850 10:03:33.887953 DramcWriteLeveling(PI) end<-----
1851 10:03:33.888494
1852 10:03:33.888830 ==
1853 10:03:33.891017 Dram Type= 6, Freq= 0, CH_1, rank 1
1854 10:03:33.894701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1855 10:03:33.897643 ==
1856 10:03:33.898055 [Gating] SW mode calibration
1857 10:03:33.904588 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1858 10:03:33.911137 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1859 10:03:33.914871 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1860 10:03:33.921152 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1861 10:03:33.924677 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 10:03:33.927760 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 10:03:33.934518 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 10:03:33.937603 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 10:03:33.941435 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 10:03:33.947515 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 10:03:33.950452 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 10:03:33.954130 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 10:03:33.960705 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 10:03:33.964404 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 10:03:33.967507 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 10:03:33.974373 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 10:03:33.977137 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 10:03:33.981675 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 10:03:33.987327 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1876 10:03:33.990795 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1877 10:03:33.993893 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1878 10:03:34.000948 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 10:03:34.004034 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 10:03:34.006957 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 10:03:34.014242 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 10:03:34.017514 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 10:03:34.020168 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 10:03:34.026651 0 9 4 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
1885 10:03:34.030305 0 9 8 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
1886 10:03:34.033586 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1887 10:03:34.039806 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1888 10:03:34.043582 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1889 10:03:34.046721 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1890 10:03:34.053809 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1891 10:03:34.056346 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1892 10:03:34.060267 0 10 4 | B1->B0 | 3434 2929 | 1 0 | (1 0) (0 0)
1893 10:03:34.066656 0 10 8 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
1894 10:03:34.070634 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 10:03:34.073626 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 10:03:34.076501 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 10:03:34.082958 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 10:03:34.086209 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 10:03:34.089875 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 10:03:34.096859 0 11 4 | B1->B0 | 2525 3d3d | 0 0 | (0 0) (0 0)
1901 10:03:34.099981 0 11 8 | B1->B0 | 3838 4646 | 1 0 | (0 0) (0 0)
1902 10:03:34.103580 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1903 10:03:34.109974 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1904 10:03:34.113291 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1905 10:03:34.116679 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1906 10:03:34.122832 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1907 10:03:34.126870 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1908 10:03:34.129729 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1909 10:03:34.136299 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1910 10:03:34.139716 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1911 10:03:34.142880 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1912 10:03:34.149229 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1913 10:03:34.152317 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1914 10:03:34.156031 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1915 10:03:34.162915 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1916 10:03:34.166088 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1917 10:03:34.169922 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1918 10:03:34.175917 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 10:03:34.179338 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 10:03:34.182899 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 10:03:34.189635 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 10:03:34.192809 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 10:03:34.196094 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1924 10:03:34.202650 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1925 10:03:34.203166 Total UI for P1: 0, mck2ui 16
1926 10:03:34.208736 best dqsien dly found for B0: ( 0, 14, 0)
1927 10:03:34.209153 Total UI for P1: 0, mck2ui 16
1928 10:03:34.212483 best dqsien dly found for B1: ( 0, 14, 2)
1929 10:03:34.219158 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1930 10:03:34.222671 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1931 10:03:34.223288
1932 10:03:34.226006 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1933 10:03:34.229302 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1934 10:03:34.232344 [Gating] SW calibration Done
1935 10:03:34.232761 ==
1936 10:03:34.235333 Dram Type= 6, Freq= 0, CH_1, rank 1
1937 10:03:34.238949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1938 10:03:34.239463 ==
1939 10:03:34.242572 RX Vref Scan: 0
1940 10:03:34.243085
1941 10:03:34.243419 RX Vref 0 -> 0, step: 1
1942 10:03:34.243731
1943 10:03:34.245442 RX Delay -130 -> 252, step: 16
1944 10:03:34.249152 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1945 10:03:34.255449 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1946 10:03:34.258706 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1947 10:03:34.261834 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1948 10:03:34.265166 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1949 10:03:34.268953 iDelay=206, Bit 5, Center 85 (-34 ~ 205) 240
1950 10:03:34.275519 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1951 10:03:34.278585 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1952 10:03:34.282098 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
1953 10:03:34.285330 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1954 10:03:34.288462 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1955 10:03:34.295187 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1956 10:03:34.298820 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1957 10:03:34.302174 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1958 10:03:34.305032 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1959 10:03:34.308350 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1960 10:03:34.312287 ==
1961 10:03:34.312805 Dram Type= 6, Freq= 0, CH_1, rank 1
1962 10:03:34.318384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1963 10:03:34.318843 ==
1964 10:03:34.319187 DQS Delay:
1965 10:03:34.321539 DQS0 = 0, DQS1 = 0
1966 10:03:34.321952 DQM Delay:
1967 10:03:34.325255 DQM0 = 83, DQM1 = 81
1968 10:03:34.325770 DQ Delay:
1969 10:03:34.328348 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1970 10:03:34.331875 DQ4 =85, DQ5 =85, DQ6 =85, DQ7 =85
1971 10:03:34.335006 DQ8 =77, DQ9 =69, DQ10 =85, DQ11 =77
1972 10:03:34.338481 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1973 10:03:34.338895
1974 10:03:34.339223
1975 10:03:34.339530 ==
1976 10:03:34.341757 Dram Type= 6, Freq= 0, CH_1, rank 1
1977 10:03:34.345299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1978 10:03:34.345824 ==
1979 10:03:34.346162
1980 10:03:34.346510
1981 10:03:34.348207 TX Vref Scan disable
1982 10:03:34.351727 == TX Byte 0 ==
1983 10:03:34.354694 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1984 10:03:34.358542 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1985 10:03:34.361472 == TX Byte 1 ==
1986 10:03:34.364850 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1987 10:03:34.368341 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1988 10:03:34.368855 ==
1989 10:03:34.371544 Dram Type= 6, Freq= 0, CH_1, rank 1
1990 10:03:34.378397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1991 10:03:34.378913 ==
1992 10:03:34.389701 TX Vref=22, minBit 6, minWin=27, winSum=448
1993 10:03:34.392787 TX Vref=24, minBit 6, minWin=27, winSum=452
1994 10:03:34.396382 TX Vref=26, minBit 0, minWin=28, winSum=453
1995 10:03:34.399405 TX Vref=28, minBit 0, minWin=28, winSum=455
1996 10:03:34.402699 TX Vref=30, minBit 5, minWin=27, winSum=455
1997 10:03:34.405784 TX Vref=32, minBit 1, minWin=27, winSum=454
1998 10:03:34.412482 [TxChooseVref] Worse bit 0, Min win 28, Win sum 455, Final Vref 28
1999 10:03:34.412901
2000 10:03:34.415897 Final TX Range 1 Vref 28
2001 10:03:34.416410
2002 10:03:34.416758 ==
2003 10:03:34.419411 Dram Type= 6, Freq= 0, CH_1, rank 1
2004 10:03:34.422406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2005 10:03:34.422924 ==
2006 10:03:34.425847
2007 10:03:34.426413
2008 10:03:34.426762 TX Vref Scan disable
2009 10:03:34.429327 == TX Byte 0 ==
2010 10:03:34.433148 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2011 10:03:34.435649 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2012 10:03:34.438908 == TX Byte 1 ==
2013 10:03:34.442859 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2014 10:03:34.449114 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2015 10:03:34.449631
2016 10:03:34.449961 [DATLAT]
2017 10:03:34.450302 Freq=800, CH1 RK1
2018 10:03:34.450616
2019 10:03:34.452648 DATLAT Default: 0xa
2020 10:03:34.453064 0, 0xFFFF, sum = 0
2021 10:03:34.455833 1, 0xFFFF, sum = 0
2022 10:03:34.456352 2, 0xFFFF, sum = 0
2023 10:03:34.459129 3, 0xFFFF, sum = 0
2024 10:03:34.459549 4, 0xFFFF, sum = 0
2025 10:03:34.462652 5, 0xFFFF, sum = 0
2026 10:03:34.465976 6, 0xFFFF, sum = 0
2027 10:03:34.466440 7, 0xFFFF, sum = 0
2028 10:03:34.468897 8, 0xFFFF, sum = 0
2029 10:03:34.469316 9, 0x0, sum = 1
2030 10:03:34.469651 10, 0x0, sum = 2
2031 10:03:34.473045 11, 0x0, sum = 3
2032 10:03:34.473465 12, 0x0, sum = 4
2033 10:03:34.475707 best_step = 10
2034 10:03:34.476219
2035 10:03:34.476681 ==
2036 10:03:34.479241 Dram Type= 6, Freq= 0, CH_1, rank 1
2037 10:03:34.482404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2038 10:03:34.482826 ==
2039 10:03:34.485908 RX Vref Scan: 0
2040 10:03:34.486472
2041 10:03:34.486814 RX Vref 0 -> 0, step: 1
2042 10:03:34.487126
2043 10:03:34.489163 RX Delay -95 -> 252, step: 8
2044 10:03:34.496362 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
2045 10:03:34.499525 iDelay=209, Bit 1, Center 80 (-39 ~ 200) 240
2046 10:03:34.502755 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
2047 10:03:34.506565 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
2048 10:03:34.509311 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
2049 10:03:34.515810 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
2050 10:03:34.518954 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
2051 10:03:34.522291 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
2052 10:03:34.526441 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
2053 10:03:34.529421 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2054 10:03:34.536021 iDelay=209, Bit 10, Center 84 (-31 ~ 200) 232
2055 10:03:34.539095 iDelay=209, Bit 11, Center 76 (-39 ~ 192) 232
2056 10:03:34.542392 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
2057 10:03:34.545624 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2058 10:03:34.552324 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2059 10:03:34.555436 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2060 10:03:34.555916 ==
2061 10:03:34.558948 Dram Type= 6, Freq= 0, CH_1, rank 1
2062 10:03:34.562009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2063 10:03:34.562473 ==
2064 10:03:34.562906 DQS Delay:
2065 10:03:34.565462 DQS0 = 0, DQS1 = 0
2066 10:03:34.565886 DQM Delay:
2067 10:03:34.569150 DQM0 = 86, DQM1 = 82
2068 10:03:34.569569 DQ Delay:
2069 10:03:34.572337 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
2070 10:03:34.575542 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =84
2071 10:03:34.578905 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =76
2072 10:03:34.582120 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
2073 10:03:34.582685
2074 10:03:34.583121
2075 10:03:34.591813 [DQSOSCAuto] RK1, (LSB)MR18= 0x1d37, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 402 ps
2076 10:03:34.592336 CH1 RK1: MR19=606, MR18=1D37
2077 10:03:34.598681 CH1_RK1: MR19=0x606, MR18=0x1D37, DQSOSC=395, MR23=63, INC=94, DEC=63
2078 10:03:34.601861 [RxdqsGatingPostProcess] freq 800
2079 10:03:34.608635 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2080 10:03:34.612166 Pre-setting of DQS Precalculation
2081 10:03:34.615038 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2082 10:03:34.621658 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2083 10:03:34.631714 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2084 10:03:34.632227
2085 10:03:34.632552
2086 10:03:34.635368 [Calibration Summary] 1600 Mbps
2087 10:03:34.635774 CH 0, Rank 0
2088 10:03:34.638703 SW Impedance : PASS
2089 10:03:34.639249 DUTY Scan : NO K
2090 10:03:34.641879 ZQ Calibration : PASS
2091 10:03:34.644913 Jitter Meter : NO K
2092 10:03:34.645471 CBT Training : PASS
2093 10:03:34.648329 Write leveling : PASS
2094 10:03:34.648742 RX DQS gating : PASS
2095 10:03:34.651760 RX DQ/DQS(RDDQC) : PASS
2096 10:03:34.654750 TX DQ/DQS : PASS
2097 10:03:34.655165 RX DATLAT : PASS
2098 10:03:34.658406 RX DQ/DQS(Engine): PASS
2099 10:03:34.661891 TX OE : NO K
2100 10:03:34.662444 All Pass.
2101 10:03:34.662775
2102 10:03:34.663077 CH 0, Rank 1
2103 10:03:34.665034 SW Impedance : PASS
2104 10:03:34.668567 DUTY Scan : NO K
2105 10:03:34.669074 ZQ Calibration : PASS
2106 10:03:34.672036 Jitter Meter : NO K
2107 10:03:34.675123 CBT Training : PASS
2108 10:03:34.675529 Write leveling : PASS
2109 10:03:34.678440 RX DQS gating : PASS
2110 10:03:34.681392 RX DQ/DQS(RDDQC) : PASS
2111 10:03:34.681803 TX DQ/DQS : PASS
2112 10:03:34.685144 RX DATLAT : PASS
2113 10:03:34.688147 RX DQ/DQS(Engine): PASS
2114 10:03:34.688654 TX OE : NO K
2115 10:03:34.688985 All Pass.
2116 10:03:34.689285
2117 10:03:34.692051 CH 1, Rank 0
2118 10:03:34.695546 SW Impedance : PASS
2119 10:03:34.696047 DUTY Scan : NO K
2120 10:03:34.698945 ZQ Calibration : PASS
2121 10:03:34.699451 Jitter Meter : NO K
2122 10:03:34.701685 CBT Training : PASS
2123 10:03:34.705309 Write leveling : PASS
2124 10:03:34.705771 RX DQS gating : PASS
2125 10:03:34.708546 RX DQ/DQS(RDDQC) : PASS
2126 10:03:34.711295 TX DQ/DQS : PASS
2127 10:03:34.711733 RX DATLAT : PASS
2128 10:03:34.715175 RX DQ/DQS(Engine): PASS
2129 10:03:34.718029 TX OE : NO K
2130 10:03:34.718461 All Pass.
2131 10:03:34.718783
2132 10:03:34.719085 CH 1, Rank 1
2133 10:03:34.721513 SW Impedance : PASS
2134 10:03:34.724890 DUTY Scan : NO K
2135 10:03:34.725305 ZQ Calibration : PASS
2136 10:03:34.728318 Jitter Meter : NO K
2137 10:03:34.731742 CBT Training : PASS
2138 10:03:34.732252 Write leveling : PASS
2139 10:03:34.735279 RX DQS gating : PASS
2140 10:03:34.738335 RX DQ/DQS(RDDQC) : PASS
2141 10:03:34.738837 TX DQ/DQS : PASS
2142 10:03:34.741545 RX DATLAT : PASS
2143 10:03:34.742296 RX DQ/DQS(Engine): PASS
2144 10:03:34.744361 TX OE : NO K
2145 10:03:34.744776 All Pass.
2146 10:03:34.745103
2147 10:03:34.747702 DramC Write-DBI off
2148 10:03:34.751126 PER_BANK_REFRESH: Hybrid Mode
2149 10:03:34.751532 TX_TRACKING: ON
2150 10:03:34.755165 [GetDramInforAfterCalByMRR] Vendor 6.
2151 10:03:34.757901 [GetDramInforAfterCalByMRR] Revision 606.
2152 10:03:34.764964 [GetDramInforAfterCalByMRR] Revision 2 0.
2153 10:03:34.765485 MR0 0x3b3b
2154 10:03:34.765816 MR8 0x5151
2155 10:03:34.768120 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2156 10:03:34.768531
2157 10:03:34.771770 MR0 0x3b3b
2158 10:03:34.772276 MR8 0x5151
2159 10:03:34.774746 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2160 10:03:34.775176
2161 10:03:34.784636 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2162 10:03:34.788465 [FAST_K] Save calibration result to emmc
2163 10:03:34.791404 [FAST_K] Save calibration result to emmc
2164 10:03:34.795079 dram_init: config_dvfs: 1
2165 10:03:34.797843 dramc_set_vcore_voltage set vcore to 662500
2166 10:03:34.798417 Read voltage for 1200, 2
2167 10:03:34.802051 Vio18 = 0
2168 10:03:34.802660 Vcore = 662500
2169 10:03:34.803025 Vdram = 0
2170 10:03:34.804588 Vddq = 0
2171 10:03:34.804994 Vmddr = 0
2172 10:03:34.807928 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2173 10:03:34.814558 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2174 10:03:34.818040 MEM_TYPE=3, freq_sel=15
2175 10:03:34.821250 sv_algorithm_assistance_LP4_1600
2176 10:03:34.824976 ============ PULL DRAM RESETB DOWN ============
2177 10:03:34.827529 ========== PULL DRAM RESETB DOWN end =========
2178 10:03:34.834343 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2179 10:03:34.837338 ===================================
2180 10:03:34.837833 LPDDR4 DRAM CONFIGURATION
2181 10:03:34.841013 ===================================
2182 10:03:34.844533 EX_ROW_EN[0] = 0x0
2183 10:03:34.847530 EX_ROW_EN[1] = 0x0
2184 10:03:34.847964 LP4Y_EN = 0x0
2185 10:03:34.850541 WORK_FSP = 0x0
2186 10:03:34.850971 WL = 0x4
2187 10:03:34.853946 RL = 0x4
2188 10:03:34.854418 BL = 0x2
2189 10:03:34.857212 RPST = 0x0
2190 10:03:34.857640 RD_PRE = 0x0
2191 10:03:34.860801 WR_PRE = 0x1
2192 10:03:34.861227 WR_PST = 0x0
2193 10:03:34.864407 DBI_WR = 0x0
2194 10:03:34.864930 DBI_RD = 0x0
2195 10:03:34.867124 OTF = 0x1
2196 10:03:34.870646 ===================================
2197 10:03:34.874357 ===================================
2198 10:03:34.874859 ANA top config
2199 10:03:34.877673 ===================================
2200 10:03:34.880694 DLL_ASYNC_EN = 0
2201 10:03:34.883819 ALL_SLAVE_EN = 0
2202 10:03:34.884233 NEW_RANK_MODE = 1
2203 10:03:34.887238 DLL_IDLE_MODE = 1
2204 10:03:34.891170 LP45_APHY_COMB_EN = 1
2205 10:03:34.894935 TX_ODT_DIS = 1
2206 10:03:34.897715 NEW_8X_MODE = 1
2207 10:03:34.900662 ===================================
2208 10:03:34.903909 ===================================
2209 10:03:34.904413 data_rate = 2400
2210 10:03:34.907565 CKR = 1
2211 10:03:34.910773 DQ_P2S_RATIO = 8
2212 10:03:34.915150 ===================================
2213 10:03:34.917866 CA_P2S_RATIO = 8
2214 10:03:34.920987 DQ_CA_OPEN = 0
2215 10:03:34.924217 DQ_SEMI_OPEN = 0
2216 10:03:34.924629 CA_SEMI_OPEN = 0
2217 10:03:34.927190 CA_FULL_RATE = 0
2218 10:03:34.930893 DQ_CKDIV4_EN = 0
2219 10:03:34.934299 CA_CKDIV4_EN = 0
2220 10:03:34.937570 CA_PREDIV_EN = 0
2221 10:03:34.940961 PH8_DLY = 17
2222 10:03:34.941469 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2223 10:03:34.944314 DQ_AAMCK_DIV = 4
2224 10:03:34.947546 CA_AAMCK_DIV = 4
2225 10:03:34.950591 CA_ADMCK_DIV = 4
2226 10:03:34.954142 DQ_TRACK_CA_EN = 0
2227 10:03:34.957399 CA_PICK = 1200
2228 10:03:34.960484 CA_MCKIO = 1200
2229 10:03:34.960920 MCKIO_SEMI = 0
2230 10:03:34.964340 PLL_FREQ = 2366
2231 10:03:34.966977 DQ_UI_PI_RATIO = 32
2232 10:03:34.970622 CA_UI_PI_RATIO = 0
2233 10:03:34.974127 ===================================
2234 10:03:34.977194 ===================================
2235 10:03:34.980747 memory_type:LPDDR4
2236 10:03:34.981181 GP_NUM : 10
2237 10:03:34.983932 SRAM_EN : 1
2238 10:03:34.986811 MD32_EN : 0
2239 10:03:34.990442 ===================================
2240 10:03:34.990857 [ANA_INIT] >>>>>>>>>>>>>>
2241 10:03:34.993744 <<<<<< [CONFIGURE PHASE]: ANA_TX
2242 10:03:34.997115 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2243 10:03:35.000252 ===================================
2244 10:03:35.004483 data_rate = 2400,PCW = 0X5b00
2245 10:03:35.006765 ===================================
2246 10:03:35.010475 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2247 10:03:35.017416 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2248 10:03:35.020216 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2249 10:03:35.027144 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2250 10:03:35.030420 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2251 10:03:35.034417 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2252 10:03:35.034990 [ANA_INIT] flow start
2253 10:03:35.036703 [ANA_INIT] PLL >>>>>>>>
2254 10:03:35.040249 [ANA_INIT] PLL <<<<<<<<
2255 10:03:35.040660 [ANA_INIT] MIDPI >>>>>>>>
2256 10:03:35.043597 [ANA_INIT] MIDPI <<<<<<<<
2257 10:03:35.047244 [ANA_INIT] DLL >>>>>>>>
2258 10:03:35.047655 [ANA_INIT] DLL <<<<<<<<
2259 10:03:35.050030 [ANA_INIT] flow end
2260 10:03:35.054035 ============ LP4 DIFF to SE enter ============
2261 10:03:35.060060 ============ LP4 DIFF to SE exit ============
2262 10:03:35.060556 [ANA_INIT] <<<<<<<<<<<<<
2263 10:03:35.063375 [Flow] Enable top DCM control >>>>>
2264 10:03:35.066739 [Flow] Enable top DCM control <<<<<
2265 10:03:35.069947 Enable DLL master slave shuffle
2266 10:03:35.076977 ==============================================================
2267 10:03:35.077487 Gating Mode config
2268 10:03:35.083698 ==============================================================
2269 10:03:35.087542 Config description:
2270 10:03:35.093276 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2271 10:03:35.099916 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2272 10:03:35.107195 SELPH_MODE 0: By rank 1: By Phase
2273 10:03:35.113219 ==============================================================
2274 10:03:35.113769 GAT_TRACK_EN = 1
2275 10:03:35.116481 RX_GATING_MODE = 2
2276 10:03:35.119895 RX_GATING_TRACK_MODE = 2
2277 10:03:35.123049 SELPH_MODE = 1
2278 10:03:35.126744 PICG_EARLY_EN = 1
2279 10:03:35.130051 VALID_LAT_VALUE = 1
2280 10:03:35.136342 ==============================================================
2281 10:03:35.140087 Enter into Gating configuration >>>>
2282 10:03:35.142867 Exit from Gating configuration <<<<
2283 10:03:35.146222 Enter into DVFS_PRE_config >>>>>
2284 10:03:35.156235 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2285 10:03:35.160170 Exit from DVFS_PRE_config <<<<<
2286 10:03:35.163174 Enter into PICG configuration >>>>
2287 10:03:35.166640 Exit from PICG configuration <<<<
2288 10:03:35.170115 [RX_INPUT] configuration >>>>>
2289 10:03:35.170735 [RX_INPUT] configuration <<<<<
2290 10:03:35.176426 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2291 10:03:35.183137 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2292 10:03:35.186674 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2293 10:03:35.193223 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2294 10:03:35.200121 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2295 10:03:35.206481 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2296 10:03:35.209529 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2297 10:03:35.213193 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2298 10:03:35.219497 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2299 10:03:35.223043 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2300 10:03:35.226349 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2301 10:03:35.232970 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2302 10:03:35.236490 ===================================
2303 10:03:35.237133 LPDDR4 DRAM CONFIGURATION
2304 10:03:35.239406 ===================================
2305 10:03:35.242789 EX_ROW_EN[0] = 0x0
2306 10:03:35.243239 EX_ROW_EN[1] = 0x0
2307 10:03:35.246068 LP4Y_EN = 0x0
2308 10:03:35.246625 WORK_FSP = 0x0
2309 10:03:35.249588 WL = 0x4
2310 10:03:35.250103 RL = 0x4
2311 10:03:35.253084 BL = 0x2
2312 10:03:35.256255 RPST = 0x0
2313 10:03:35.256708 RD_PRE = 0x0
2314 10:03:35.259718 WR_PRE = 0x1
2315 10:03:35.260127 WR_PST = 0x0
2316 10:03:35.262684 DBI_WR = 0x0
2317 10:03:35.263094 DBI_RD = 0x0
2318 10:03:35.266289 OTF = 0x1
2319 10:03:35.269460 ===================================
2320 10:03:35.273402 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2321 10:03:35.276303 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2322 10:03:35.279629 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2323 10:03:35.283056 ===================================
2324 10:03:35.286171 LPDDR4 DRAM CONFIGURATION
2325 10:03:35.289275 ===================================
2326 10:03:35.292912 EX_ROW_EN[0] = 0x10
2327 10:03:35.293418 EX_ROW_EN[1] = 0x0
2328 10:03:35.296042 LP4Y_EN = 0x0
2329 10:03:35.296453 WORK_FSP = 0x0
2330 10:03:35.299407 WL = 0x4
2331 10:03:35.299907 RL = 0x4
2332 10:03:35.302924 BL = 0x2
2333 10:03:35.306338 RPST = 0x0
2334 10:03:35.306846 RD_PRE = 0x0
2335 10:03:35.309385 WR_PRE = 0x1
2336 10:03:35.309796 WR_PST = 0x0
2337 10:03:35.312599 DBI_WR = 0x0
2338 10:03:35.313102 DBI_RD = 0x0
2339 10:03:35.315646 OTF = 0x1
2340 10:03:35.319805 ===================================
2341 10:03:35.322494 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2342 10:03:35.326068 ==
2343 10:03:35.329129 Dram Type= 6, Freq= 0, CH_0, rank 0
2344 10:03:35.332443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2345 10:03:35.332861 ==
2346 10:03:35.336055 [Duty_Offset_Calibration]
2347 10:03:35.336562 B0:2 B1:0 CA:4
2348 10:03:35.336894
2349 10:03:35.338814 [DutyScan_Calibration_Flow] k_type=0
2350 10:03:35.347668
2351 10:03:35.348170 ==CLK 0==
2352 10:03:35.351298 Final CLK duty delay cell = -4
2353 10:03:35.354224 [-4] MAX Duty = 5031%(X100), DQS PI = 18
2354 10:03:35.358027 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2355 10:03:35.360871 [-4] AVG Duty = 4937%(X100)
2356 10:03:35.361291
2357 10:03:35.364515 CH0 CLK Duty spec in!! Max-Min= 187%
2358 10:03:35.367881 [DutyScan_Calibration_Flow] ====Done====
2359 10:03:35.368405
2360 10:03:35.370548 [DutyScan_Calibration_Flow] k_type=1
2361 10:03:35.387144
2362 10:03:35.387549 ==DQS 0 ==
2363 10:03:35.390394 Final DQS duty delay cell = 0
2364 10:03:35.394239 [0] MAX Duty = 5156%(X100), DQS PI = 12
2365 10:03:35.398096 [0] MIN Duty = 5093%(X100), DQS PI = 44
2366 10:03:35.400990 [0] AVG Duty = 5124%(X100)
2367 10:03:35.401596
2368 10:03:35.401987 ==DQS 1 ==
2369 10:03:35.403897 Final DQS duty delay cell = 0
2370 10:03:35.407080 [0] MAX Duty = 5125%(X100), DQS PI = 50
2371 10:03:35.410714 [0] MIN Duty = 4969%(X100), DQS PI = 14
2372 10:03:35.413667 [0] AVG Duty = 5047%(X100)
2373 10:03:35.414200
2374 10:03:35.417413 CH0 DQS 0 Duty spec in!! Max-Min= 63%
2375 10:03:35.417915
2376 10:03:35.420747 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2377 10:03:35.424089 [DutyScan_Calibration_Flow] ====Done====
2378 10:03:35.424590
2379 10:03:35.427289 [DutyScan_Calibration_Flow] k_type=3
2380 10:03:35.443722
2381 10:03:35.444270 ==DQM 0 ==
2382 10:03:35.446823 Final DQM duty delay cell = 0
2383 10:03:35.450339 [0] MAX Duty = 5125%(X100), DQS PI = 20
2384 10:03:35.453510 [0] MIN Duty = 4844%(X100), DQS PI = 56
2385 10:03:35.457215 [0] AVG Duty = 4984%(X100)
2386 10:03:35.457775
2387 10:03:35.458138 ==DQM 1 ==
2388 10:03:35.460353 Final DQM duty delay cell = 0
2389 10:03:35.463938 [0] MAX Duty = 5000%(X100), DQS PI = 6
2390 10:03:35.467354 [0] MIN Duty = 4875%(X100), DQS PI = 18
2391 10:03:35.470625 [0] AVG Duty = 4937%(X100)
2392 10:03:35.471161
2393 10:03:35.473850 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2394 10:03:35.474483
2395 10:03:35.477476 CH0 DQM 1 Duty spec in!! Max-Min= 125%
2396 10:03:35.480988 [DutyScan_Calibration_Flow] ====Done====
2397 10:03:35.481529
2398 10:03:35.483661 [DutyScan_Calibration_Flow] k_type=2
2399 10:03:35.500375
2400 10:03:35.500914 ==DQ 0 ==
2401 10:03:35.503964 Final DQ duty delay cell = 0
2402 10:03:35.507217 [0] MAX Duty = 5125%(X100), DQS PI = 16
2403 10:03:35.510510 [0] MIN Duty = 4969%(X100), DQS PI = 52
2404 10:03:35.511046 [0] AVG Duty = 5047%(X100)
2405 10:03:35.513963
2406 10:03:35.514564 ==DQ 1 ==
2407 10:03:35.517255 Final DQ duty delay cell = 0
2408 10:03:35.520548 [0] MAX Duty = 5156%(X100), DQS PI = 6
2409 10:03:35.523470 [0] MIN Duty = 4907%(X100), DQS PI = 18
2410 10:03:35.524009 [0] AVG Duty = 5031%(X100)
2411 10:03:35.524369
2412 10:03:35.527226 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2413 10:03:35.530716
2414 10:03:35.534038 CH0 DQ 1 Duty spec in!! Max-Min= 249%
2415 10:03:35.537268 [DutyScan_Calibration_Flow] ====Done====
2416 10:03:35.537809 ==
2417 10:03:35.540861 Dram Type= 6, Freq= 0, CH_1, rank 0
2418 10:03:35.544077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2419 10:03:35.544536 ==
2420 10:03:35.546996 [Duty_Offset_Calibration]
2421 10:03:35.547444 B0:0 B1:-1 CA:3
2422 10:03:35.547797
2423 10:03:35.550292 [DutyScan_Calibration_Flow] k_type=0
2424 10:03:35.559315
2425 10:03:35.559982 ==CLK 0==
2426 10:03:35.562648 Final CLK duty delay cell = -4
2427 10:03:35.566306 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2428 10:03:35.569508 [-4] MIN Duty = 4876%(X100), DQS PI = 36
2429 10:03:35.572723 [-4] AVG Duty = 4938%(X100)
2430 10:03:35.573262
2431 10:03:35.575964 CH1 CLK Duty spec in!! Max-Min= 124%
2432 10:03:35.579900 [DutyScan_Calibration_Flow] ====Done====
2433 10:03:35.580452
2434 10:03:35.582858 [DutyScan_Calibration_Flow] k_type=1
2435 10:03:35.599107
2436 10:03:35.599876 ==DQS 0 ==
2437 10:03:35.602149 Final DQS duty delay cell = 0
2438 10:03:35.605517 [0] MAX Duty = 5187%(X100), DQS PI = 18
2439 10:03:35.608965 [0] MIN Duty = 4907%(X100), DQS PI = 38
2440 10:03:35.612381 [0] AVG Duty = 5047%(X100)
2441 10:03:35.612792
2442 10:03:35.613160 ==DQS 1 ==
2443 10:03:35.615705 Final DQS duty delay cell = 0
2444 10:03:35.618566 [0] MAX Duty = 5156%(X100), DQS PI = 8
2445 10:03:35.621808 [0] MIN Duty = 5031%(X100), DQS PI = 26
2446 10:03:35.625179 [0] AVG Duty = 5093%(X100)
2447 10:03:35.625595
2448 10:03:35.628623 CH1 DQS 0 Duty spec in!! Max-Min= 280%
2449 10:03:35.629363
2450 10:03:35.632008 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2451 10:03:35.635620 [DutyScan_Calibration_Flow] ====Done====
2452 10:03:35.636333
2453 10:03:35.638867 [DutyScan_Calibration_Flow] k_type=3
2454 10:03:35.655878
2455 10:03:35.656379 ==DQM 0 ==
2456 10:03:35.658669 Final DQM duty delay cell = 0
2457 10:03:35.662122 [0] MAX Duty = 5031%(X100), DQS PI = 26
2458 10:03:35.665101 [0] MIN Duty = 4813%(X100), DQS PI = 38
2459 10:03:35.669022 [0] AVG Duty = 4922%(X100)
2460 10:03:35.669439
2461 10:03:35.669770 ==DQM 1 ==
2462 10:03:35.672117 Final DQM duty delay cell = 0
2463 10:03:35.675515 [0] MAX Duty = 5000%(X100), DQS PI = 34
2464 10:03:35.678755 [0] MIN Duty = 4844%(X100), DQS PI = 0
2465 10:03:35.681970 [0] AVG Duty = 4922%(X100)
2466 10:03:35.682527
2467 10:03:35.685323 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2468 10:03:35.685741
2469 10:03:35.688624 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2470 10:03:35.692287 [DutyScan_Calibration_Flow] ====Done====
2471 10:03:35.692790
2472 10:03:35.695199 [DutyScan_Calibration_Flow] k_type=2
2473 10:03:35.711451
2474 10:03:35.711954 ==DQ 0 ==
2475 10:03:35.714827 Final DQ duty delay cell = -4
2476 10:03:35.718033 [-4] MAX Duty = 5000%(X100), DQS PI = 14
2477 10:03:35.720966 [-4] MIN Duty = 4844%(X100), DQS PI = 36
2478 10:03:35.724751 [-4] AVG Duty = 4922%(X100)
2479 10:03:35.725257
2480 10:03:35.725589 ==DQ 1 ==
2481 10:03:35.727808 Final DQ duty delay cell = 0
2482 10:03:35.730937 [0] MAX Duty = 5031%(X100), DQS PI = 32
2483 10:03:35.734342 [0] MIN Duty = 4844%(X100), DQS PI = 62
2484 10:03:35.737709 [0] AVG Duty = 4937%(X100)
2485 10:03:35.738219
2486 10:03:35.741261 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2487 10:03:35.741767
2488 10:03:35.744129 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2489 10:03:35.747470 [DutyScan_Calibration_Flow] ====Done====
2490 10:03:35.750627 nWR fixed to 30
2491 10:03:35.754483 [ModeRegInit_LP4] CH0 RK0
2492 10:03:35.754898 [ModeRegInit_LP4] CH0 RK1
2493 10:03:35.757414 [ModeRegInit_LP4] CH1 RK0
2494 10:03:35.761166 [ModeRegInit_LP4] CH1 RK1
2495 10:03:35.761583 match AC timing 7
2496 10:03:35.767362 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2497 10:03:35.770893 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2498 10:03:35.774144 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2499 10:03:35.781026 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2500 10:03:35.784234 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2501 10:03:35.784781 ==
2502 10:03:35.788113 Dram Type= 6, Freq= 0, CH_0, rank 0
2503 10:03:35.791235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2504 10:03:35.791784 ==
2505 10:03:35.797599 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2506 10:03:35.803931 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2507 10:03:35.811619 [CA 0] Center 39 (9~70) winsize 62
2508 10:03:35.815239 [CA 1] Center 39 (9~69) winsize 61
2509 10:03:35.818413 [CA 2] Center 35 (5~66) winsize 62
2510 10:03:35.821868 [CA 3] Center 35 (5~66) winsize 62
2511 10:03:35.824852 [CA 4] Center 33 (3~64) winsize 62
2512 10:03:35.828662 [CA 5] Center 33 (3~63) winsize 61
2513 10:03:35.829119
2514 10:03:35.831227 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2515 10:03:35.831684
2516 10:03:35.834777 [CATrainingPosCal] consider 1 rank data
2517 10:03:35.838104 u2DelayCellTimex100 = 270/100 ps
2518 10:03:35.841373 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2519 10:03:35.848232 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2520 10:03:35.851462 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2521 10:03:35.854365 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2522 10:03:35.857881 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2523 10:03:35.861292 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2524 10:03:35.861717
2525 10:03:35.864658 CA PerBit enable=1, Macro0, CA PI delay=33
2526 10:03:35.865167
2527 10:03:35.868064 [CBTSetCACLKResult] CA Dly = 33
2528 10:03:35.868571 CS Dly: 7 (0~38)
2529 10:03:35.870906 ==
2530 10:03:35.874244 Dram Type= 6, Freq= 0, CH_0, rank 1
2531 10:03:35.877349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2532 10:03:35.877767 ==
2533 10:03:35.881214 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2534 10:03:35.888119 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2535 10:03:35.898063 [CA 0] Center 39 (9~70) winsize 62
2536 10:03:35.900561 [CA 1] Center 39 (9~70) winsize 62
2537 10:03:35.903889 [CA 2] Center 35 (5~66) winsize 62
2538 10:03:35.907196 [CA 3] Center 35 (5~66) winsize 62
2539 10:03:35.910371 [CA 4] Center 34 (4~65) winsize 62
2540 10:03:35.914145 [CA 5] Center 33 (3~64) winsize 62
2541 10:03:35.914698
2542 10:03:35.917229 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2543 10:03:35.917648
2544 10:03:35.920306 [CATrainingPosCal] consider 2 rank data
2545 10:03:35.924147 u2DelayCellTimex100 = 270/100 ps
2546 10:03:35.926900 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2547 10:03:35.933744 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2548 10:03:35.937043 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2549 10:03:35.940860 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2550 10:03:35.943742 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2551 10:03:35.946989 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2552 10:03:35.947406
2553 10:03:35.950496 CA PerBit enable=1, Macro0, CA PI delay=33
2554 10:03:35.950911
2555 10:03:35.953641 [CBTSetCACLKResult] CA Dly = 33
2556 10:03:35.954055 CS Dly: 8 (0~41)
2557 10:03:35.957312
2558 10:03:35.959913 ----->DramcWriteLeveling(PI) begin...
2559 10:03:35.960342 ==
2560 10:03:35.963610 Dram Type= 6, Freq= 0, CH_0, rank 0
2561 10:03:35.967152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2562 10:03:35.967661 ==
2563 10:03:35.970222 Write leveling (Byte 0): 33 => 33
2564 10:03:35.973315 Write leveling (Byte 1): 27 => 27
2565 10:03:35.977129 DramcWriteLeveling(PI) end<-----
2566 10:03:35.977546
2567 10:03:35.977872 ==
2568 10:03:35.979977 Dram Type= 6, Freq= 0, CH_0, rank 0
2569 10:03:35.983171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2570 10:03:35.983698 ==
2571 10:03:35.986537 [Gating] SW mode calibration
2572 10:03:35.993291 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2573 10:03:36.000018 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2574 10:03:36.003479 0 15 0 | B1->B0 | 2322 3434 | 1 1 | (0 0) (1 1)
2575 10:03:36.006888 0 15 4 | B1->B0 | 2c2c 3434 | 1 1 | (0 0) (1 1)
2576 10:03:36.013571 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2577 10:03:36.016219 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2578 10:03:36.020065 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2579 10:03:36.026116 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2580 10:03:36.029714 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2581 10:03:36.033046 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
2582 10:03:36.039811 1 0 0 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
2583 10:03:36.043202 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2584 10:03:36.046108 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2585 10:03:36.053187 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2586 10:03:36.055687 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2587 10:03:36.059518 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2588 10:03:36.066463 1 0 24 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
2589 10:03:36.069589 1 0 28 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
2590 10:03:36.072736 1 1 0 | B1->B0 | 2c2c 4646 | 0 0 | (1 1) (0 0)
2591 10:03:36.079837 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2592 10:03:36.082720 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2593 10:03:36.086336 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2594 10:03:36.092649 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2595 10:03:36.095702 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2596 10:03:36.099119 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2597 10:03:36.105848 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2598 10:03:36.109031 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2599 10:03:36.112350 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2600 10:03:36.118998 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2601 10:03:36.122426 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2602 10:03:36.125723 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2603 10:03:36.132236 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2604 10:03:36.135653 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2605 10:03:36.138754 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2606 10:03:36.145304 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2607 10:03:36.149138 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2608 10:03:36.151939 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2609 10:03:36.159251 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2610 10:03:36.162187 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 10:03:36.165305 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 10:03:36.169337 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 10:03:36.175644 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2614 10:03:36.178764 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2615 10:03:36.181597 Total UI for P1: 0, mck2ui 16
2616 10:03:36.185438 best dqsien dly found for B0: ( 1, 3, 28)
2617 10:03:36.188475 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2618 10:03:36.194962 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2619 10:03:36.198488 Total UI for P1: 0, mck2ui 16
2620 10:03:36.202359 best dqsien dly found for B1: ( 1, 4, 2)
2621 10:03:36.205394 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2622 10:03:36.208727 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2623 10:03:36.209233
2624 10:03:36.211590 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2625 10:03:36.215052 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2626 10:03:36.218184 [Gating] SW calibration Done
2627 10:03:36.218627 ==
2628 10:03:36.221378 Dram Type= 6, Freq= 0, CH_0, rank 0
2629 10:03:36.224735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2630 10:03:36.225244 ==
2631 10:03:36.228391 RX Vref Scan: 0
2632 10:03:36.228905
2633 10:03:36.229240 RX Vref 0 -> 0, step: 1
2634 10:03:36.231243
2635 10:03:36.231656 RX Delay -40 -> 252, step: 8
2636 10:03:36.238789 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2637 10:03:36.241838 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2638 10:03:36.244665 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2639 10:03:36.247816 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2640 10:03:36.251297 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2641 10:03:36.258075 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2642 10:03:36.261673 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2643 10:03:36.264987 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2644 10:03:36.268125 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2645 10:03:36.271215 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2646 10:03:36.275057 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2647 10:03:36.281558 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2648 10:03:36.285112 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2649 10:03:36.288358 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2650 10:03:36.291121 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2651 10:03:36.297887 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2652 10:03:36.298496 ==
2653 10:03:36.301403 Dram Type= 6, Freq= 0, CH_0, rank 0
2654 10:03:36.304766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2655 10:03:36.305313 ==
2656 10:03:36.305685 DQS Delay:
2657 10:03:36.308237 DQS0 = 0, DQS1 = 0
2658 10:03:36.308782 DQM Delay:
2659 10:03:36.311606 DQM0 = 117, DQM1 = 107
2660 10:03:36.312214 DQ Delay:
2661 10:03:36.314652 DQ0 =115, DQ1 =119, DQ2 =119, DQ3 =111
2662 10:03:36.317970 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =123
2663 10:03:36.321620 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2664 10:03:36.324607 DQ12 =119, DQ13 =111, DQ14 =119, DQ15 =111
2665 10:03:36.325151
2666 10:03:36.325513
2667 10:03:36.325853 ==
2668 10:03:36.327890 Dram Type= 6, Freq= 0, CH_0, rank 0
2669 10:03:36.334597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2670 10:03:36.335132 ==
2671 10:03:36.335503
2672 10:03:36.335840
2673 10:03:36.337815 TX Vref Scan disable
2674 10:03:36.338436 == TX Byte 0 ==
2675 10:03:36.341433 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2676 10:03:36.347657 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2677 10:03:36.348068 == TX Byte 1 ==
2678 10:03:36.350614 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2679 10:03:36.358315 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2680 10:03:36.358946 ==
2681 10:03:36.361245 Dram Type= 6, Freq= 0, CH_0, rank 0
2682 10:03:36.364139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2683 10:03:36.364599 ==
2684 10:03:36.376938 TX Vref=22, minBit 4, minWin=25, winSum=411
2685 10:03:36.379904 TX Vref=24, minBit 10, minWin=25, winSum=418
2686 10:03:36.383631 TX Vref=26, minBit 13, minWin=25, winSum=424
2687 10:03:36.386606 TX Vref=28, minBit 4, minWin=26, winSum=427
2688 10:03:36.390393 TX Vref=30, minBit 5, minWin=26, winSum=430
2689 10:03:36.396649 TX Vref=32, minBit 4, minWin=26, winSum=427
2690 10:03:36.400034 [TxChooseVref] Worse bit 5, Min win 26, Win sum 430, Final Vref 30
2691 10:03:36.400599
2692 10:03:36.403073 Final TX Range 1 Vref 30
2693 10:03:36.403523
2694 10:03:36.403878 ==
2695 10:03:36.406858 Dram Type= 6, Freq= 0, CH_0, rank 0
2696 10:03:36.409430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2697 10:03:36.412887 ==
2698 10:03:36.413340
2699 10:03:36.413700
2700 10:03:36.414031 TX Vref Scan disable
2701 10:03:36.416354 == TX Byte 0 ==
2702 10:03:36.419961 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2703 10:03:36.426925 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2704 10:03:36.427473 == TX Byte 1 ==
2705 10:03:36.429962 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2706 10:03:36.436711 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2707 10:03:36.437264
2708 10:03:36.437624 [DATLAT]
2709 10:03:36.437959 Freq=1200, CH0 RK0
2710 10:03:36.438311
2711 10:03:36.439349 DATLAT Default: 0xd
2712 10:03:36.439798 0, 0xFFFF, sum = 0
2713 10:03:36.443427 1, 0xFFFF, sum = 0
2714 10:03:36.446235 2, 0xFFFF, sum = 0
2715 10:03:36.446749 3, 0xFFFF, sum = 0
2716 10:03:36.449562 4, 0xFFFF, sum = 0
2717 10:03:36.450139 5, 0xFFFF, sum = 0
2718 10:03:36.452866 6, 0xFFFF, sum = 0
2719 10:03:36.453423 7, 0xFFFF, sum = 0
2720 10:03:36.456667 8, 0xFFFF, sum = 0
2721 10:03:36.457125 9, 0xFFFF, sum = 0
2722 10:03:36.459700 10, 0xFFFF, sum = 0
2723 10:03:36.460159 11, 0xFFFF, sum = 0
2724 10:03:36.462790 12, 0x0, sum = 1
2725 10:03:36.463245 13, 0x0, sum = 2
2726 10:03:36.465795 14, 0x0, sum = 3
2727 10:03:36.466208 15, 0x0, sum = 4
2728 10:03:36.469550 best_step = 13
2729 10:03:36.469954
2730 10:03:36.470314 ==
2731 10:03:36.472674 Dram Type= 6, Freq= 0, CH_0, rank 0
2732 10:03:36.476307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2733 10:03:36.476821 ==
2734 10:03:36.477153 RX Vref Scan: 1
2735 10:03:36.479658
2736 10:03:36.480063 Set Vref Range= 32 -> 127
2737 10:03:36.480386
2738 10:03:36.482663 RX Vref 32 -> 127, step: 1
2739 10:03:36.483071
2740 10:03:36.485668 RX Delay -21 -> 252, step: 4
2741 10:03:36.486076
2742 10:03:36.489605 Set Vref, RX VrefLevel [Byte0]: 32
2743 10:03:36.492347 [Byte1]: 32
2744 10:03:36.492756
2745 10:03:36.495910 Set Vref, RX VrefLevel [Byte0]: 33
2746 10:03:36.498902 [Byte1]: 33
2747 10:03:36.503119
2748 10:03:36.503625 Set Vref, RX VrefLevel [Byte0]: 34
2749 10:03:36.506116 [Byte1]: 34
2750 10:03:36.510869
2751 10:03:36.511373 Set Vref, RX VrefLevel [Byte0]: 35
2752 10:03:36.513864 [Byte1]: 35
2753 10:03:36.518863
2754 10:03:36.519366 Set Vref, RX VrefLevel [Byte0]: 36
2755 10:03:36.522079 [Byte1]: 36
2756 10:03:36.526854
2757 10:03:36.527358 Set Vref, RX VrefLevel [Byte0]: 37
2758 10:03:36.530180 [Byte1]: 37
2759 10:03:36.534662
2760 10:03:36.535208 Set Vref, RX VrefLevel [Byte0]: 38
2761 10:03:36.538153 [Byte1]: 38
2762 10:03:36.542574
2763 10:03:36.543120 Set Vref, RX VrefLevel [Byte0]: 39
2764 10:03:36.545889 [Byte1]: 39
2765 10:03:36.551134
2766 10:03:36.551678 Set Vref, RX VrefLevel [Byte0]: 40
2767 10:03:36.553813 [Byte1]: 40
2768 10:03:36.558131
2769 10:03:36.558885 Set Vref, RX VrefLevel [Byte0]: 41
2770 10:03:36.561646 [Byte1]: 41
2771 10:03:36.566751
2772 10:03:36.567201 Set Vref, RX VrefLevel [Byte0]: 42
2773 10:03:36.569889 [Byte1]: 42
2774 10:03:36.574782
2775 10:03:36.575192 Set Vref, RX VrefLevel [Byte0]: 43
2776 10:03:36.577282 [Byte1]: 43
2777 10:03:36.582203
2778 10:03:36.582660 Set Vref, RX VrefLevel [Byte0]: 44
2779 10:03:36.585059 [Byte1]: 44
2780 10:03:36.590114
2781 10:03:36.590661 Set Vref, RX VrefLevel [Byte0]: 45
2782 10:03:36.593561 [Byte1]: 45
2783 10:03:36.598003
2784 10:03:36.601039 Set Vref, RX VrefLevel [Byte0]: 46
2785 10:03:36.601551 [Byte1]: 46
2786 10:03:36.605923
2787 10:03:36.606472 Set Vref, RX VrefLevel [Byte0]: 47
2788 10:03:36.608894 [Byte1]: 47
2789 10:03:36.613529
2790 10:03:36.613941 Set Vref, RX VrefLevel [Byte0]: 48
2791 10:03:36.617205 [Byte1]: 48
2792 10:03:36.622535
2793 10:03:36.623051 Set Vref, RX VrefLevel [Byte0]: 49
2794 10:03:36.624897 [Byte1]: 49
2795 10:03:36.630062
2796 10:03:36.630609 Set Vref, RX VrefLevel [Byte0]: 50
2797 10:03:36.633064 [Byte1]: 50
2798 10:03:36.637561
2799 10:03:36.638073 Set Vref, RX VrefLevel [Byte0]: 51
2800 10:03:36.640700 [Byte1]: 51
2801 10:03:36.645989
2802 10:03:36.646530 Set Vref, RX VrefLevel [Byte0]: 52
2803 10:03:36.649101 [Byte1]: 52
2804 10:03:36.653371
2805 10:03:36.653931 Set Vref, RX VrefLevel [Byte0]: 53
2806 10:03:36.656470 [Byte1]: 53
2807 10:03:36.661692
2808 10:03:36.662205 Set Vref, RX VrefLevel [Byte0]: 54
2809 10:03:36.664824 [Byte1]: 54
2810 10:03:36.669235
2811 10:03:36.669746 Set Vref, RX VrefLevel [Byte0]: 55
2812 10:03:36.672901 [Byte1]: 55
2813 10:03:36.677184
2814 10:03:36.677688 Set Vref, RX VrefLevel [Byte0]: 56
2815 10:03:36.680327 [Byte1]: 56
2816 10:03:36.685358
2817 10:03:36.685772 Set Vref, RX VrefLevel [Byte0]: 57
2818 10:03:36.688995 [Byte1]: 57
2819 10:03:36.693041
2820 10:03:36.693450 Set Vref, RX VrefLevel [Byte0]: 58
2821 10:03:36.697318 [Byte1]: 58
2822 10:03:36.701099
2823 10:03:36.701606 Set Vref, RX VrefLevel [Byte0]: 59
2824 10:03:36.704415 [Byte1]: 59
2825 10:03:36.708779
2826 10:03:36.709189 Set Vref, RX VrefLevel [Byte0]: 60
2827 10:03:36.712363 [Byte1]: 60
2828 10:03:36.716668
2829 10:03:36.717077 Set Vref, RX VrefLevel [Byte0]: 61
2830 10:03:36.719815 [Byte1]: 61
2831 10:03:36.724595
2832 10:03:36.725006 Set Vref, RX VrefLevel [Byte0]: 62
2833 10:03:36.727878 [Byte1]: 62
2834 10:03:36.732975
2835 10:03:36.733383 Set Vref, RX VrefLevel [Byte0]: 63
2836 10:03:36.736555 [Byte1]: 63
2837 10:03:36.740894
2838 10:03:36.741432 Set Vref, RX VrefLevel [Byte0]: 64
2839 10:03:36.743779 [Byte1]: 64
2840 10:03:36.748439
2841 10:03:36.748847 Set Vref, RX VrefLevel [Byte0]: 65
2842 10:03:36.752029 [Byte1]: 65
2843 10:03:36.756404
2844 10:03:36.756811 Set Vref, RX VrefLevel [Byte0]: 66
2845 10:03:36.760077 [Byte1]: 66
2846 10:03:36.764872
2847 10:03:36.765382 Set Vref, RX VrefLevel [Byte0]: 67
2848 10:03:36.767658 [Byte1]: 67
2849 10:03:36.772280
2850 10:03:36.772793 Set Vref, RX VrefLevel [Byte0]: 68
2851 10:03:36.776061 [Byte1]: 68
2852 10:03:36.780690
2853 10:03:36.781198 Set Vref, RX VrefLevel [Byte0]: 69
2854 10:03:36.783687 [Byte1]: 69
2855 10:03:36.788425
2856 10:03:36.788946 Final RX Vref Byte 0 = 54 to rank0
2857 10:03:36.791713 Final RX Vref Byte 1 = 58 to rank0
2858 10:03:36.795211 Final RX Vref Byte 0 = 54 to rank1
2859 10:03:36.798697 Final RX Vref Byte 1 = 58 to rank1==
2860 10:03:36.801525 Dram Type= 6, Freq= 0, CH_0, rank 0
2861 10:03:36.808212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2862 10:03:36.808729 ==
2863 10:03:36.809063 DQS Delay:
2864 10:03:36.809371 DQS0 = 0, DQS1 = 0
2865 10:03:36.811311 DQM Delay:
2866 10:03:36.811721 DQM0 = 117, DQM1 = 105
2867 10:03:36.815002 DQ Delay:
2868 10:03:36.818461 DQ0 =118, DQ1 =116, DQ2 =114, DQ3 =114
2869 10:03:36.821609 DQ4 =120, DQ5 =110, DQ6 =124, DQ7 =122
2870 10:03:36.825166 DQ8 =94, DQ9 =90, DQ10 =106, DQ11 =100
2871 10:03:36.827998 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =112
2872 10:03:36.828485
2873 10:03:36.828880
2874 10:03:36.834817 [DQSOSCAuto] RK0, (LSB)MR18= 0x500, (MSB)MR19= 0x404, tDQSOscB0 = 410 ps tDQSOscB1 = 408 ps
2875 10:03:36.838388 CH0 RK0: MR19=404, MR18=500
2876 10:03:36.844879 CH0_RK0: MR19=0x404, MR18=0x500, DQSOSC=408, MR23=63, INC=39, DEC=26
2877 10:03:36.845429
2878 10:03:36.848094 ----->DramcWriteLeveling(PI) begin...
2879 10:03:36.848551 ==
2880 10:03:36.851092 Dram Type= 6, Freq= 0, CH_0, rank 1
2881 10:03:36.854499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2882 10:03:36.857812 ==
2883 10:03:36.858371 Write leveling (Byte 0): 32 => 32
2884 10:03:36.860770 Write leveling (Byte 1): 26 => 26
2885 10:03:36.864660 DramcWriteLeveling(PI) end<-----
2886 10:03:36.865067
2887 10:03:36.865388 ==
2888 10:03:36.867808 Dram Type= 6, Freq= 0, CH_0, rank 1
2889 10:03:36.875119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2890 10:03:36.875669 ==
2891 10:03:36.876038 [Gating] SW mode calibration
2892 10:03:36.884616 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2893 10:03:36.887860 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2894 10:03:36.894935 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2895 10:03:36.897803 0 15 4 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
2896 10:03:36.901339 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2897 10:03:36.904334 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2898 10:03:36.911282 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2899 10:03:36.914750 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2900 10:03:36.917683 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2901 10:03:36.924224 0 15 28 | B1->B0 | 3434 2626 | 0 0 | (0 0) (0 0)
2902 10:03:36.927917 1 0 0 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)
2903 10:03:36.931121 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2904 10:03:36.937635 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2905 10:03:36.940951 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2906 10:03:36.944585 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2907 10:03:36.950703 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2908 10:03:36.953863 1 0 24 | B1->B0 | 2323 3838 | 0 1 | (0 0) (0 0)
2909 10:03:36.957282 1 0 28 | B1->B0 | 2828 4545 | 0 0 | (0 0) (0 0)
2910 10:03:36.963719 1 1 0 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
2911 10:03:36.967315 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2912 10:03:36.970187 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2913 10:03:36.977206 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2914 10:03:36.980316 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2915 10:03:36.983995 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2916 10:03:36.990450 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2917 10:03:36.994138 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2918 10:03:36.997024 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2919 10:03:37.003722 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2920 10:03:37.007002 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2921 10:03:37.010411 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2922 10:03:37.017408 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2923 10:03:37.020653 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2924 10:03:37.023670 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2925 10:03:37.030968 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2926 10:03:37.033701 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2927 10:03:37.036984 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 10:03:37.043571 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 10:03:37.046841 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 10:03:37.050199 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 10:03:37.056915 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2932 10:03:37.060399 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2933 10:03:37.063455 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
2934 10:03:37.067826 Total UI for P1: 0, mck2ui 16
2935 10:03:37.070377 best dqsien dly found for B0: ( 1, 3, 22)
2936 10:03:37.073771 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2937 10:03:37.079890 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2938 10:03:37.083570 Total UI for P1: 0, mck2ui 16
2939 10:03:37.087028 best dqsien dly found for B1: ( 1, 4, 0)
2940 10:03:37.090453 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
2941 10:03:37.093283 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2942 10:03:37.093737
2943 10:03:37.096715 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
2944 10:03:37.099896 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2945 10:03:37.103500 [Gating] SW calibration Done
2946 10:03:37.104051 ==
2947 10:03:37.106516 Dram Type= 6, Freq= 0, CH_0, rank 1
2948 10:03:37.109966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2949 10:03:37.110612 ==
2950 10:03:37.112905 RX Vref Scan: 0
2951 10:03:37.113359
2952 10:03:37.116821 RX Vref 0 -> 0, step: 1
2953 10:03:37.117334
2954 10:03:37.117664 RX Delay -40 -> 252, step: 8
2955 10:03:37.123082 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2956 10:03:37.126656 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2957 10:03:37.130166 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2958 10:03:37.133547 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2959 10:03:37.136513 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2960 10:03:37.143411 iDelay=200, Bit 5, Center 107 (40 ~ 175) 136
2961 10:03:37.146448 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2962 10:03:37.149913 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
2963 10:03:37.153393 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2964 10:03:37.156717 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2965 10:03:37.163379 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2966 10:03:37.166363 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2967 10:03:37.169597 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2968 10:03:37.172899 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2969 10:03:37.176409 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2970 10:03:37.183118 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2971 10:03:37.183658 ==
2972 10:03:37.186066 Dram Type= 6, Freq= 0, CH_0, rank 1
2973 10:03:37.189554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2974 10:03:37.190066 ==
2975 10:03:37.190462 DQS Delay:
2976 10:03:37.192559 DQS0 = 0, DQS1 = 0
2977 10:03:37.192970 DQM Delay:
2978 10:03:37.196301 DQM0 = 115, DQM1 = 109
2979 10:03:37.196813 DQ Delay:
2980 10:03:37.199632 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =111
2981 10:03:37.202195 DQ4 =119, DQ5 =107, DQ6 =127, DQ7 =119
2982 10:03:37.206216 DQ8 =99, DQ9 =91, DQ10 =111, DQ11 =103
2983 10:03:37.209132 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2984 10:03:37.209643
2985 10:03:37.209971
2986 10:03:37.212478 ==
2987 10:03:37.215693 Dram Type= 6, Freq= 0, CH_0, rank 1
2988 10:03:37.218753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2989 10:03:37.219168 ==
2990 10:03:37.219495
2991 10:03:37.219796
2992 10:03:37.222371 TX Vref Scan disable
2993 10:03:37.222912 == TX Byte 0 ==
2994 10:03:37.226134 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2995 10:03:37.232412 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2996 10:03:37.232924 == TX Byte 1 ==
2997 10:03:37.235666 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2998 10:03:37.242771 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2999 10:03:37.243287 ==
3000 10:03:37.245833 Dram Type= 6, Freq= 0, CH_0, rank 1
3001 10:03:37.249180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3002 10:03:37.249596 ==
3003 10:03:37.261879 TX Vref=22, minBit 4, minWin=24, winSum=412
3004 10:03:37.265245 TX Vref=24, minBit 14, minWin=25, winSum=419
3005 10:03:37.268587 TX Vref=26, minBit 5, minWin=25, winSum=421
3006 10:03:37.271802 TX Vref=28, minBit 0, minWin=26, winSum=423
3007 10:03:37.275190 TX Vref=30, minBit 4, minWin=26, winSum=429
3008 10:03:37.281535 TX Vref=32, minBit 8, minWin=26, winSum=429
3009 10:03:37.285136 [TxChooseVref] Worse bit 4, Min win 26, Win sum 429, Final Vref 30
3010 10:03:37.285595
3011 10:03:37.288482 Final TX Range 1 Vref 30
3012 10:03:37.289101
3013 10:03:37.289473 ==
3014 10:03:37.291720 Dram Type= 6, Freq= 0, CH_0, rank 1
3015 10:03:37.295160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3016 10:03:37.295633 ==
3017 10:03:37.298085
3018 10:03:37.298573
3019 10:03:37.298937 TX Vref Scan disable
3020 10:03:37.301450 == TX Byte 0 ==
3021 10:03:37.304901 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3022 10:03:37.311422 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3023 10:03:37.311939 == TX Byte 1 ==
3024 10:03:37.314752 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3025 10:03:37.321446 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3026 10:03:37.321963
3027 10:03:37.322351 [DATLAT]
3028 10:03:37.322763 Freq=1200, CH0 RK1
3029 10:03:37.323082
3030 10:03:37.324938 DATLAT Default: 0xd
3031 10:03:37.325352 0, 0xFFFF, sum = 0
3032 10:03:37.327765 1, 0xFFFF, sum = 0
3033 10:03:37.331039 2, 0xFFFF, sum = 0
3034 10:03:37.331562 3, 0xFFFF, sum = 0
3035 10:03:37.334820 4, 0xFFFF, sum = 0
3036 10:03:37.335358 5, 0xFFFF, sum = 0
3037 10:03:37.338046 6, 0xFFFF, sum = 0
3038 10:03:37.338522 7, 0xFFFF, sum = 0
3039 10:03:37.341446 8, 0xFFFF, sum = 0
3040 10:03:37.342013 9, 0xFFFF, sum = 0
3041 10:03:37.344680 10, 0xFFFF, sum = 0
3042 10:03:37.345107 11, 0xFFFF, sum = 0
3043 10:03:37.348241 12, 0x0, sum = 1
3044 10:03:37.348676 13, 0x0, sum = 2
3045 10:03:37.351577 14, 0x0, sum = 3
3046 10:03:37.352098 15, 0x0, sum = 4
3047 10:03:37.354758 best_step = 13
3048 10:03:37.355175
3049 10:03:37.355505 ==
3050 10:03:37.357900 Dram Type= 6, Freq= 0, CH_0, rank 1
3051 10:03:37.361228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3052 10:03:37.361747 ==
3053 10:03:37.362084 RX Vref Scan: 0
3054 10:03:37.364613
3055 10:03:37.365024 RX Vref 0 -> 0, step: 1
3056 10:03:37.365353
3057 10:03:37.367598 RX Delay -21 -> 252, step: 4
3058 10:03:37.374127 iDelay=195, Bit 0, Center 112 (47 ~ 178) 132
3059 10:03:37.378397 iDelay=195, Bit 1, Center 116 (47 ~ 186) 140
3060 10:03:37.381093 iDelay=195, Bit 2, Center 112 (47 ~ 178) 132
3061 10:03:37.384559 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3062 10:03:37.387791 iDelay=195, Bit 4, Center 118 (51 ~ 186) 136
3063 10:03:37.391098 iDelay=195, Bit 5, Center 110 (43 ~ 178) 136
3064 10:03:37.397860 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3065 10:03:37.401343 iDelay=195, Bit 7, Center 122 (55 ~ 190) 136
3066 10:03:37.404312 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3067 10:03:37.407718 iDelay=195, Bit 9, Center 92 (27 ~ 158) 132
3068 10:03:37.410888 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3069 10:03:37.418005 iDelay=195, Bit 11, Center 100 (31 ~ 170) 140
3070 10:03:37.421337 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3071 10:03:37.424380 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3072 10:03:37.427811 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3073 10:03:37.431075 iDelay=195, Bit 15, Center 112 (47 ~ 178) 132
3074 10:03:37.434486 ==
3075 10:03:37.437534 Dram Type= 6, Freq= 0, CH_0, rank 1
3076 10:03:37.440753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3077 10:03:37.441317 ==
3078 10:03:37.441686 DQS Delay:
3079 10:03:37.444065 DQS0 = 0, DQS1 = 0
3080 10:03:37.444522 DQM Delay:
3081 10:03:37.447775 DQM0 = 116, DQM1 = 106
3082 10:03:37.448331 DQ Delay:
3083 10:03:37.450856 DQ0 =112, DQ1 =116, DQ2 =112, DQ3 =112
3084 10:03:37.454075 DQ4 =118, DQ5 =110, DQ6 =126, DQ7 =122
3085 10:03:37.457365 DQ8 =96, DQ9 =92, DQ10 =110, DQ11 =100
3086 10:03:37.460907 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =112
3087 10:03:37.461431
3088 10:03:37.461774
3089 10:03:37.470749 [DQSOSCAuto] RK1, (LSB)MR18= 0x200, (MSB)MR19= 0x404, tDQSOscB0 = 410 ps tDQSOscB1 = 409 ps
3090 10:03:37.471263 CH0 RK1: MR19=404, MR18=200
3091 10:03:37.477953 CH0_RK1: MR19=0x404, MR18=0x200, DQSOSC=409, MR23=63, INC=39, DEC=26
3092 10:03:37.481115 [RxdqsGatingPostProcess] freq 1200
3093 10:03:37.487767 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3094 10:03:37.490632 best DQS0 dly(2T, 0.5T) = (0, 11)
3095 10:03:37.494184 best DQS1 dly(2T, 0.5T) = (0, 12)
3096 10:03:37.497591 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3097 10:03:37.500507 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3098 10:03:37.504095 best DQS0 dly(2T, 0.5T) = (0, 11)
3099 10:03:37.506815 best DQS1 dly(2T, 0.5T) = (0, 12)
3100 10:03:37.510657 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3101 10:03:37.511217 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3102 10:03:37.514023 Pre-setting of DQS Precalculation
3103 10:03:37.520919 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3104 10:03:37.521442 ==
3105 10:03:37.523904 Dram Type= 6, Freq= 0, CH_1, rank 0
3106 10:03:37.527411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3107 10:03:37.527875 ==
3108 10:03:37.533991 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3109 10:03:37.540558 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3110 10:03:37.548037 [CA 0] Center 38 (8~68) winsize 61
3111 10:03:37.551217 [CA 1] Center 37 (7~68) winsize 62
3112 10:03:37.554427 [CA 2] Center 35 (5~65) winsize 61
3113 10:03:37.557944 [CA 3] Center 34 (4~64) winsize 61
3114 10:03:37.560771 [CA 4] Center 34 (4~65) winsize 62
3115 10:03:37.564016 [CA 5] Center 33 (4~63) winsize 60
3116 10:03:37.564479
3117 10:03:37.567284 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3118 10:03:37.567803
3119 10:03:37.571089 [CATrainingPosCal] consider 1 rank data
3120 10:03:37.574241 u2DelayCellTimex100 = 270/100 ps
3121 10:03:37.577580 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3122 10:03:37.583852 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3123 10:03:37.587101 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3124 10:03:37.590672 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3125 10:03:37.594080 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3126 10:03:37.597388 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3127 10:03:37.597897
3128 10:03:37.600654 CA PerBit enable=1, Macro0, CA PI delay=33
3129 10:03:37.601167
3130 10:03:37.603840 [CBTSetCACLKResult] CA Dly = 33
3131 10:03:37.604292 CS Dly: 4 (0~35)
3132 10:03:37.607288 ==
3133 10:03:37.607807 Dram Type= 6, Freq= 0, CH_1, rank 1
3134 10:03:37.614423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3135 10:03:37.615023 ==
3136 10:03:37.617666 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3137 10:03:37.624185 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3138 10:03:37.633187 [CA 0] Center 37 (7~68) winsize 62
3139 10:03:37.636647 [CA 1] Center 38 (8~68) winsize 61
3140 10:03:37.639643 [CA 2] Center 35 (5~65) winsize 61
3141 10:03:37.643307 [CA 3] Center 33 (3~64) winsize 62
3142 10:03:37.646449 [CA 4] Center 34 (4~64) winsize 61
3143 10:03:37.650226 [CA 5] Center 33 (3~64) winsize 62
3144 10:03:37.650828
3145 10:03:37.653695 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3146 10:03:37.654287
3147 10:03:37.656848 [CATrainingPosCal] consider 2 rank data
3148 10:03:37.660274 u2DelayCellTimex100 = 270/100 ps
3149 10:03:37.663164 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3150 10:03:37.666463 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3151 10:03:37.673345 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3152 10:03:37.676616 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3153 10:03:37.680237 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3154 10:03:37.682946 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3155 10:03:37.683409
3156 10:03:37.686090 CA PerBit enable=1, Macro0, CA PI delay=33
3157 10:03:37.686550
3158 10:03:37.689731 [CBTSetCACLKResult] CA Dly = 33
3159 10:03:37.690242 CS Dly: 6 (0~39)
3160 10:03:37.690617
3161 10:03:37.693181 ----->DramcWriteLeveling(PI) begin...
3162 10:03:37.696603 ==
3163 10:03:37.699792 Dram Type= 6, Freq= 0, CH_1, rank 0
3164 10:03:37.703262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3165 10:03:37.703916 ==
3166 10:03:37.706397 Write leveling (Byte 0): 26 => 26
3167 10:03:37.709946 Write leveling (Byte 1): 26 => 26
3168 10:03:37.713254 DramcWriteLeveling(PI) end<-----
3169 10:03:37.713763
3170 10:03:37.714093 ==
3171 10:03:37.716386 Dram Type= 6, Freq= 0, CH_1, rank 0
3172 10:03:37.719628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3173 10:03:37.720146 ==
3174 10:03:37.723177 [Gating] SW mode calibration
3175 10:03:37.729632 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3176 10:03:37.736254 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3177 10:03:37.739766 0 15 0 | B1->B0 | 2d2d 3333 | 1 1 | (1 1) (1 1)
3178 10:03:37.743017 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3179 10:03:37.749213 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3180 10:03:37.753115 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3181 10:03:37.756039 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3182 10:03:37.762384 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3183 10:03:37.765656 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
3184 10:03:37.768853 0 15 28 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
3185 10:03:37.775945 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3186 10:03:37.779546 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3187 10:03:37.782517 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3188 10:03:37.788717 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3189 10:03:37.792285 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3190 10:03:37.795665 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3191 10:03:37.798645 1 0 24 | B1->B0 | 2424 2e2e | 0 0 | (0 0) (0 0)
3192 10:03:37.805382 1 0 28 | B1->B0 | 3e3e 4444 | 0 1 | (0 0) (0 0)
3193 10:03:37.808892 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3194 10:03:37.811991 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3195 10:03:37.818786 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3196 10:03:37.821889 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3197 10:03:37.825083 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3198 10:03:37.831880 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3199 10:03:37.835786 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3200 10:03:37.838452 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3201 10:03:37.845065 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3202 10:03:37.848322 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3203 10:03:37.851749 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3204 10:03:37.859019 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3205 10:03:37.862127 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3206 10:03:37.865148 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3207 10:03:37.871469 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3208 10:03:37.874702 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3209 10:03:37.878225 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 10:03:37.885235 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 10:03:37.887959 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 10:03:37.891543 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 10:03:37.898610 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 10:03:37.901397 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 10:03:37.904713 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3216 10:03:37.911419 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3217 10:03:37.914705 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3218 10:03:37.918192 Total UI for P1: 0, mck2ui 16
3219 10:03:37.921859 best dqsien dly found for B0: ( 1, 3, 26)
3220 10:03:37.924750 Total UI for P1: 0, mck2ui 16
3221 10:03:37.928098 best dqsien dly found for B1: ( 1, 3, 26)
3222 10:03:37.931147 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3223 10:03:37.935001 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3224 10:03:37.935527
3225 10:03:37.938109 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3226 10:03:37.941781 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3227 10:03:37.944660 [Gating] SW calibration Done
3228 10:03:37.945181 ==
3229 10:03:37.948553 Dram Type= 6, Freq= 0, CH_1, rank 0
3230 10:03:37.951642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3231 10:03:37.954679 ==
3232 10:03:37.955193 RX Vref Scan: 0
3233 10:03:37.955644
3234 10:03:37.957467 RX Vref 0 -> 0, step: 1
3235 10:03:37.957897
3236 10:03:37.961010 RX Delay -40 -> 252, step: 8
3237 10:03:37.964731 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3238 10:03:37.967486 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3239 10:03:37.970955 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3240 10:03:37.974463 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3241 10:03:37.981208 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3242 10:03:37.984699 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3243 10:03:37.987638 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3244 10:03:37.990726 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3245 10:03:37.994118 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3246 10:03:38.001237 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3247 10:03:38.004964 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3248 10:03:38.007679 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3249 10:03:38.011230 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3250 10:03:38.014529 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3251 10:03:38.020722 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3252 10:03:38.024374 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3253 10:03:38.024896 ==
3254 10:03:38.027831 Dram Type= 6, Freq= 0, CH_1, rank 0
3255 10:03:38.031169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3256 10:03:38.031710 ==
3257 10:03:38.034302 DQS Delay:
3258 10:03:38.034822 DQS0 = 0, DQS1 = 0
3259 10:03:38.035272 DQM Delay:
3260 10:03:38.037350 DQM0 = 115, DQM1 = 112
3261 10:03:38.037871 DQ Delay:
3262 10:03:38.041023 DQ0 =123, DQ1 =111, DQ2 =103, DQ3 =115
3263 10:03:38.044547 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3264 10:03:38.047430 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3265 10:03:38.054067 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3266 10:03:38.054621
3267 10:03:38.055072
3268 10:03:38.055494 ==
3269 10:03:38.057713 Dram Type= 6, Freq= 0, CH_1, rank 0
3270 10:03:38.060612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3271 10:03:38.061143 ==
3272 10:03:38.061589
3273 10:03:38.062010
3274 10:03:38.063947 TX Vref Scan disable
3275 10:03:38.064379 == TX Byte 0 ==
3276 10:03:38.070324 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3277 10:03:38.073683 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3278 10:03:38.074114 == TX Byte 1 ==
3279 10:03:38.080653 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3280 10:03:38.084035 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3281 10:03:38.084546 ==
3282 10:03:38.087274 Dram Type= 6, Freq= 0, CH_1, rank 0
3283 10:03:38.090213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3284 10:03:38.090673 ==
3285 10:03:38.103648 TX Vref=22, minBit 9, minWin=24, winSum=404
3286 10:03:38.106722 TX Vref=24, minBit 9, minWin=24, winSum=411
3287 10:03:38.109808 TX Vref=26, minBit 9, minWin=24, winSum=414
3288 10:03:38.113274 TX Vref=28, minBit 9, minWin=24, winSum=422
3289 10:03:38.116068 TX Vref=30, minBit 9, minWin=25, winSum=424
3290 10:03:38.123286 TX Vref=32, minBit 9, minWin=25, winSum=423
3291 10:03:38.126423 [TxChooseVref] Worse bit 9, Min win 25, Win sum 424, Final Vref 30
3292 10:03:38.126859
3293 10:03:38.129525 Final TX Range 1 Vref 30
3294 10:03:38.130031
3295 10:03:38.130408 ==
3296 10:03:38.132857 Dram Type= 6, Freq= 0, CH_1, rank 0
3297 10:03:38.136223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3298 10:03:38.136734 ==
3299 10:03:38.140048
3300 10:03:38.140556
3301 10:03:38.140892 TX Vref Scan disable
3302 10:03:38.142581 == TX Byte 0 ==
3303 10:03:38.146365 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3304 10:03:38.149756 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3305 10:03:38.152971 == TX Byte 1 ==
3306 10:03:38.156374 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3307 10:03:38.159232 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3308 10:03:38.162703
3309 10:03:38.163117 [DATLAT]
3310 10:03:38.163446 Freq=1200, CH1 RK0
3311 10:03:38.163761
3312 10:03:38.166216 DATLAT Default: 0xd
3313 10:03:38.166674 0, 0xFFFF, sum = 0
3314 10:03:38.169573 1, 0xFFFF, sum = 0
3315 10:03:38.170088 2, 0xFFFF, sum = 0
3316 10:03:38.172780 3, 0xFFFF, sum = 0
3317 10:03:38.175962 4, 0xFFFF, sum = 0
3318 10:03:38.176420 5, 0xFFFF, sum = 0
3319 10:03:38.179297 6, 0xFFFF, sum = 0
3320 10:03:38.179720 7, 0xFFFF, sum = 0
3321 10:03:38.182968 8, 0xFFFF, sum = 0
3322 10:03:38.183393 9, 0xFFFF, sum = 0
3323 10:03:38.185786 10, 0xFFFF, sum = 0
3324 10:03:38.186207 11, 0xFFFF, sum = 0
3325 10:03:38.188999 12, 0x0, sum = 1
3326 10:03:38.189513 13, 0x0, sum = 2
3327 10:03:38.192747 14, 0x0, sum = 3
3328 10:03:38.193265 15, 0x0, sum = 4
3329 10:03:38.195914 best_step = 13
3330 10:03:38.196364
3331 10:03:38.196689 ==
3332 10:03:38.199691 Dram Type= 6, Freq= 0, CH_1, rank 0
3333 10:03:38.202597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3334 10:03:38.203101 ==
3335 10:03:38.203436 RX Vref Scan: 1
3336 10:03:38.203745
3337 10:03:38.206107 Set Vref Range= 32 -> 127
3338 10:03:38.206551
3339 10:03:38.209319 RX Vref 32 -> 127, step: 1
3340 10:03:38.209825
3341 10:03:38.212677 RX Delay -13 -> 252, step: 4
3342 10:03:38.213092
3343 10:03:38.215880 Set Vref, RX VrefLevel [Byte0]: 32
3344 10:03:38.219312 [Byte1]: 32
3345 10:03:38.219736
3346 10:03:38.223095 Set Vref, RX VrefLevel [Byte0]: 33
3347 10:03:38.225973 [Byte1]: 33
3348 10:03:38.229714
3349 10:03:38.230233 Set Vref, RX VrefLevel [Byte0]: 34
3350 10:03:38.232314 [Byte1]: 34
3351 10:03:38.237236
3352 10:03:38.237758 Set Vref, RX VrefLevel [Byte0]: 35
3353 10:03:38.240500 [Byte1]: 35
3354 10:03:38.245127
3355 10:03:38.245645 Set Vref, RX VrefLevel [Byte0]: 36
3356 10:03:38.248357 [Byte1]: 36
3357 10:03:38.252787
3358 10:03:38.253307 Set Vref, RX VrefLevel [Byte0]: 37
3359 10:03:38.256504 [Byte1]: 37
3360 10:03:38.260755
3361 10:03:38.261264 Set Vref, RX VrefLevel [Byte0]: 38
3362 10:03:38.263998 [Byte1]: 38
3363 10:03:38.268202
3364 10:03:38.268707 Set Vref, RX VrefLevel [Byte0]: 39
3365 10:03:38.271586 [Byte1]: 39
3366 10:03:38.276230
3367 10:03:38.276562 Set Vref, RX VrefLevel [Byte0]: 40
3368 10:03:38.279815 [Byte1]: 40
3369 10:03:38.284285
3370 10:03:38.284590 Set Vref, RX VrefLevel [Byte0]: 41
3371 10:03:38.287327 [Byte1]: 41
3372 10:03:38.292248
3373 10:03:38.292576 Set Vref, RX VrefLevel [Byte0]: 42
3374 10:03:38.295503 [Byte1]: 42
3375 10:03:38.299690
3376 10:03:38.299988 Set Vref, RX VrefLevel [Byte0]: 43
3377 10:03:38.303284 [Byte1]: 43
3378 10:03:38.307744
3379 10:03:38.307962 Set Vref, RX VrefLevel [Byte0]: 44
3380 10:03:38.311130 [Byte1]: 44
3381 10:03:38.315481
3382 10:03:38.315843 Set Vref, RX VrefLevel [Byte0]: 45
3383 10:03:38.318827 [Byte1]: 45
3384 10:03:38.324138
3385 10:03:38.324636 Set Vref, RX VrefLevel [Byte0]: 46
3386 10:03:38.327093 [Byte1]: 46
3387 10:03:38.331531
3388 10:03:38.332030 Set Vref, RX VrefLevel [Byte0]: 47
3389 10:03:38.334875 [Byte1]: 47
3390 10:03:38.339305
3391 10:03:38.339816 Set Vref, RX VrefLevel [Byte0]: 48
3392 10:03:38.342723 [Byte1]: 48
3393 10:03:38.347163
3394 10:03:38.347629 Set Vref, RX VrefLevel [Byte0]: 49
3395 10:03:38.350422 [Byte1]: 49
3396 10:03:38.355218
3397 10:03:38.355715 Set Vref, RX VrefLevel [Byte0]: 50
3398 10:03:38.358775 [Byte1]: 50
3399 10:03:38.363120
3400 10:03:38.363619 Set Vref, RX VrefLevel [Byte0]: 51
3401 10:03:38.366320 [Byte1]: 51
3402 10:03:38.371362
3403 10:03:38.371863 Set Vref, RX VrefLevel [Byte0]: 52
3404 10:03:38.374045 [Byte1]: 52
3405 10:03:38.378954
3406 10:03:38.379455 Set Vref, RX VrefLevel [Byte0]: 53
3407 10:03:38.382642 [Byte1]: 53
3408 10:03:38.386857
3409 10:03:38.387404 Set Vref, RX VrefLevel [Byte0]: 54
3410 10:03:38.389986 [Byte1]: 54
3411 10:03:38.394871
3412 10:03:38.395427 Set Vref, RX VrefLevel [Byte0]: 55
3413 10:03:38.398137 [Byte1]: 55
3414 10:03:38.402618
3415 10:03:38.403183 Set Vref, RX VrefLevel [Byte0]: 56
3416 10:03:38.405783 [Byte1]: 56
3417 10:03:38.410460
3418 10:03:38.410979 Set Vref, RX VrefLevel [Byte0]: 57
3419 10:03:38.414394 [Byte1]: 57
3420 10:03:38.418103
3421 10:03:38.418646 Set Vref, RX VrefLevel [Byte0]: 58
3422 10:03:38.421357 [Byte1]: 58
3423 10:03:38.426386
3424 10:03:38.426883 Set Vref, RX VrefLevel [Byte0]: 59
3425 10:03:38.429098 [Byte1]: 59
3426 10:03:38.433764
3427 10:03:38.434166 Set Vref, RX VrefLevel [Byte0]: 60
3428 10:03:38.437455 [Byte1]: 60
3429 10:03:38.442136
3430 10:03:38.442680 Set Vref, RX VrefLevel [Byte0]: 61
3431 10:03:38.445116 [Byte1]: 61
3432 10:03:38.450391
3433 10:03:38.450884 Set Vref, RX VrefLevel [Byte0]: 62
3434 10:03:38.453367 [Byte1]: 62
3435 10:03:38.457265
3436 10:03:38.457676 Set Vref, RX VrefLevel [Byte0]: 63
3437 10:03:38.460743 [Byte1]: 63
3438 10:03:38.465491
3439 10:03:38.465986 Set Vref, RX VrefLevel [Byte0]: 64
3440 10:03:38.468805 [Byte1]: 64
3441 10:03:38.473780
3442 10:03:38.474333 Final RX Vref Byte 0 = 52 to rank0
3443 10:03:38.476832 Final RX Vref Byte 1 = 53 to rank0
3444 10:03:38.480383 Final RX Vref Byte 0 = 52 to rank1
3445 10:03:38.483416 Final RX Vref Byte 1 = 53 to rank1==
3446 10:03:38.487005 Dram Type= 6, Freq= 0, CH_1, rank 0
3447 10:03:38.493698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3448 10:03:38.494209 ==
3449 10:03:38.494593 DQS Delay:
3450 10:03:38.494899 DQS0 = 0, DQS1 = 0
3451 10:03:38.496791 DQM Delay:
3452 10:03:38.497286 DQM0 = 114, DQM1 = 113
3453 10:03:38.500423 DQ Delay:
3454 10:03:38.503759 DQ0 =118, DQ1 =112, DQ2 =106, DQ3 =114
3455 10:03:38.506740 DQ4 =110, DQ5 =122, DQ6 =126, DQ7 =110
3456 10:03:38.510196 DQ8 =98, DQ9 =102, DQ10 =114, DQ11 =106
3457 10:03:38.513146 DQ12 =122, DQ13 =120, DQ14 =120, DQ15 =122
3458 10:03:38.513607
3459 10:03:38.514113
3460 10:03:38.523839 [DQSOSCAuto] RK0, (LSB)MR18= 0xf400, (MSB)MR19= 0x304, tDQSOscB0 = 410 ps tDQSOscB1 = 415 ps
3461 10:03:38.524352 CH1 RK0: MR19=304, MR18=F400
3462 10:03:38.530413 CH1_RK0: MR19=0x304, MR18=0xF400, DQSOSC=410, MR23=63, INC=39, DEC=26
3463 10:03:38.530915
3464 10:03:38.533590 ----->DramcWriteLeveling(PI) begin...
3465 10:03:38.534097 ==
3466 10:03:38.536729 Dram Type= 6, Freq= 0, CH_1, rank 1
3467 10:03:38.543423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3468 10:03:38.543989 ==
3469 10:03:38.546654 Write leveling (Byte 0): 25 => 25
3470 10:03:38.547108 Write leveling (Byte 1): 27 => 27
3471 10:03:38.549381 DramcWriteLeveling(PI) end<-----
3472 10:03:38.549785
3473 10:03:38.550108 ==
3474 10:03:38.552909 Dram Type= 6, Freq= 0, CH_1, rank 1
3475 10:03:38.559389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3476 10:03:38.559884 ==
3477 10:03:38.563084 [Gating] SW mode calibration
3478 10:03:38.569512 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3479 10:03:38.573147 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3480 10:03:38.579351 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3481 10:03:38.582852 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3482 10:03:38.586759 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3483 10:03:38.593388 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3484 10:03:38.596536 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3485 10:03:38.599754 0 15 20 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
3486 10:03:38.606234 0 15 24 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 0)
3487 10:03:38.609717 0 15 28 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
3488 10:03:38.613152 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3489 10:03:38.619656 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3490 10:03:38.622757 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3491 10:03:38.626032 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3492 10:03:38.629332 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3493 10:03:38.636045 1 0 20 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
3494 10:03:38.639844 1 0 24 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
3495 10:03:38.643143 1 0 28 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
3496 10:03:38.649215 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3497 10:03:38.652773 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3498 10:03:38.655873 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3499 10:03:38.662291 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3500 10:03:38.665745 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3501 10:03:38.669339 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3502 10:03:38.675367 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3503 10:03:38.679443 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3504 10:03:38.682384 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3505 10:03:38.689274 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3506 10:03:38.692380 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3507 10:03:38.695234 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3508 10:03:38.701863 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3509 10:03:38.705383 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3510 10:03:38.708642 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3511 10:03:38.715326 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3512 10:03:38.719087 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3513 10:03:38.722195 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3514 10:03:38.728672 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3515 10:03:38.731704 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3516 10:03:38.735697 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3517 10:03:38.741820 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3518 10:03:38.745213 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3519 10:03:38.748820 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3520 10:03:38.755115 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3521 10:03:38.758125 Total UI for P1: 0, mck2ui 16
3522 10:03:38.761758 best dqsien dly found for B0: ( 1, 3, 26)
3523 10:03:38.762360 Total UI for P1: 0, mck2ui 16
3524 10:03:38.768219 best dqsien dly found for B1: ( 1, 3, 26)
3525 10:03:38.771663 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3526 10:03:38.774862 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3527 10:03:38.775400
3528 10:03:38.778626 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3529 10:03:38.780994 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3530 10:03:38.784714 [Gating] SW calibration Done
3531 10:03:38.785126 ==
3532 10:03:38.788641 Dram Type= 6, Freq= 0, CH_1, rank 1
3533 10:03:38.791770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3534 10:03:38.792278 ==
3535 10:03:38.794229 RX Vref Scan: 0
3536 10:03:38.794688
3537 10:03:38.797883 RX Vref 0 -> 0, step: 1
3538 10:03:38.798437
3539 10:03:38.798779 RX Delay -40 -> 252, step: 8
3540 10:03:38.804753 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3541 10:03:38.808048 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
3542 10:03:38.811319 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3543 10:03:38.814800 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3544 10:03:38.817989 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3545 10:03:38.824877 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3546 10:03:38.827439 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3547 10:03:38.830991 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3548 10:03:38.833985 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3549 10:03:38.837677 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3550 10:03:38.843759 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3551 10:03:38.847419 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3552 10:03:38.850557 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3553 10:03:38.853476 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3554 10:03:38.860129 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3555 10:03:38.863966 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3556 10:03:38.864378 ==
3557 10:03:38.867195 Dram Type= 6, Freq= 0, CH_1, rank 1
3558 10:03:38.870247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3559 10:03:38.870688 ==
3560 10:03:38.871017 DQS Delay:
3561 10:03:38.873530 DQS0 = 0, DQS1 = 0
3562 10:03:38.873940 DQM Delay:
3563 10:03:38.877076 DQM0 = 115, DQM1 = 111
3564 10:03:38.877587 DQ Delay:
3565 10:03:38.879832 DQ0 =119, DQ1 =115, DQ2 =103, DQ3 =111
3566 10:03:38.883124 DQ4 =115, DQ5 =127, DQ6 =119, DQ7 =115
3567 10:03:38.886744 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =107
3568 10:03:38.893372 DQ12 =123, DQ13 =119, DQ14 =115, DQ15 =119
3569 10:03:38.893911
3570 10:03:38.894394
3571 10:03:38.894716 ==
3572 10:03:38.896471 Dram Type= 6, Freq= 0, CH_1, rank 1
3573 10:03:38.899811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3574 10:03:38.900362 ==
3575 10:03:38.900698
3576 10:03:38.901005
3577 10:03:38.903236 TX Vref Scan disable
3578 10:03:38.903675 == TX Byte 0 ==
3579 10:03:38.910234 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3580 10:03:38.912785 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3581 10:03:38.913197 == TX Byte 1 ==
3582 10:03:38.920230 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3583 10:03:38.923157 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3584 10:03:38.923667 ==
3585 10:03:38.926061 Dram Type= 6, Freq= 0, CH_1, rank 1
3586 10:03:38.929505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3587 10:03:38.930014 ==
3588 10:03:38.942097 TX Vref=22, minBit 7, minWin=25, winSum=418
3589 10:03:38.945978 TX Vref=24, minBit 9, minWin=25, winSum=422
3590 10:03:38.949292 TX Vref=26, minBit 9, minWin=25, winSum=426
3591 10:03:38.952225 TX Vref=28, minBit 1, minWin=26, winSum=427
3592 10:03:38.956178 TX Vref=30, minBit 1, minWin=26, winSum=431
3593 10:03:38.962294 TX Vref=32, minBit 9, minWin=25, winSum=429
3594 10:03:38.965663 [TxChooseVref] Worse bit 1, Min win 26, Win sum 431, Final Vref 30
3595 10:03:38.966174
3596 10:03:38.969052 Final TX Range 1 Vref 30
3597 10:03:38.969558
3598 10:03:38.969886 ==
3599 10:03:38.972273 Dram Type= 6, Freq= 0, CH_1, rank 1
3600 10:03:38.975754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3601 10:03:38.979066 ==
3602 10:03:38.979572
3603 10:03:38.979901
3604 10:03:38.980205 TX Vref Scan disable
3605 10:03:38.981938 == TX Byte 0 ==
3606 10:03:38.985524 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3607 10:03:38.991781 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3608 10:03:38.992291 == TX Byte 1 ==
3609 10:03:38.995777 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3610 10:03:39.002219 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3611 10:03:39.002808
3612 10:03:39.003171 [DATLAT]
3613 10:03:39.003506 Freq=1200, CH1 RK1
3614 10:03:39.003833
3615 10:03:39.004990 DATLAT Default: 0xd
3616 10:03:39.008300 0, 0xFFFF, sum = 0
3617 10:03:39.008872 1, 0xFFFF, sum = 0
3618 10:03:39.011931 2, 0xFFFF, sum = 0
3619 10:03:39.012533 3, 0xFFFF, sum = 0
3620 10:03:39.014775 4, 0xFFFF, sum = 0
3621 10:03:39.015203 5, 0xFFFF, sum = 0
3622 10:03:39.018236 6, 0xFFFF, sum = 0
3623 10:03:39.018750 7, 0xFFFF, sum = 0
3624 10:03:39.021395 8, 0xFFFF, sum = 0
3625 10:03:39.021915 9, 0xFFFF, sum = 0
3626 10:03:39.024961 10, 0xFFFF, sum = 0
3627 10:03:39.025480 11, 0xFFFF, sum = 0
3628 10:03:39.028530 12, 0x0, sum = 1
3629 10:03:39.028961 13, 0x0, sum = 2
3630 10:03:39.031922 14, 0x0, sum = 3
3631 10:03:39.032450 15, 0x0, sum = 4
3632 10:03:39.035137 best_step = 13
3633 10:03:39.035671
3634 10:03:39.036108 ==
3635 10:03:39.037967 Dram Type= 6, Freq= 0, CH_1, rank 1
3636 10:03:39.041107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3637 10:03:39.041533 ==
3638 10:03:39.045211 RX Vref Scan: 0
3639 10:03:39.045912
3640 10:03:39.046457 RX Vref 0 -> 0, step: 1
3641 10:03:39.046875
3642 10:03:39.048312 RX Delay -13 -> 252, step: 4
3643 10:03:39.054499 iDelay=195, Bit 0, Center 116 (47 ~ 186) 140
3644 10:03:39.058033 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3645 10:03:39.061149 iDelay=195, Bit 2, Center 106 (39 ~ 174) 136
3646 10:03:39.064892 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3647 10:03:39.068228 iDelay=195, Bit 4, Center 116 (47 ~ 186) 140
3648 10:03:39.074605 iDelay=195, Bit 5, Center 124 (55 ~ 194) 140
3649 10:03:39.077418 iDelay=195, Bit 6, Center 122 (55 ~ 190) 136
3650 10:03:39.081070 iDelay=195, Bit 7, Center 110 (39 ~ 182) 144
3651 10:03:39.084432 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3652 10:03:39.087863 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3653 10:03:39.093993 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3654 10:03:39.097648 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3655 10:03:39.101075 iDelay=195, Bit 12, Center 120 (59 ~ 182) 124
3656 10:03:39.103995 iDelay=195, Bit 13, Center 120 (59 ~ 182) 124
3657 10:03:39.110688 iDelay=195, Bit 14, Center 118 (59 ~ 178) 120
3658 10:03:39.114296 iDelay=195, Bit 15, Center 122 (59 ~ 186) 128
3659 10:03:39.114818 ==
3660 10:03:39.117698 Dram Type= 6, Freq= 0, CH_1, rank 1
3661 10:03:39.120604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3662 10:03:39.121142 ==
3663 10:03:39.123740 DQS Delay:
3664 10:03:39.124259 DQS0 = 0, DQS1 = 0
3665 10:03:39.124701 DQM Delay:
3666 10:03:39.127126 DQM0 = 114, DQM1 = 112
3667 10:03:39.127647 DQ Delay:
3668 10:03:39.130389 DQ0 =116, DQ1 =112, DQ2 =106, DQ3 =112
3669 10:03:39.133589 DQ4 =116, DQ5 =124, DQ6 =122, DQ7 =110
3670 10:03:39.140162 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =106
3671 10:03:39.143636 DQ12 =120, DQ13 =120, DQ14 =118, DQ15 =122
3672 10:03:39.144174
3673 10:03:39.144607
3674 10:03:39.149786 [DQSOSCAuto] RK1, (LSB)MR18= 0xfb0c, (MSB)MR19= 0x304, tDQSOscB0 = 405 ps tDQSOscB1 = 412 ps
3675 10:03:39.153331 CH1 RK1: MR19=304, MR18=FB0C
3676 10:03:39.160222 CH1_RK1: MR19=0x304, MR18=0xFB0C, DQSOSC=405, MR23=63, INC=39, DEC=26
3677 10:03:39.163115 [RxdqsGatingPostProcess] freq 1200
3678 10:03:39.169563 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3679 10:03:39.170130 best DQS0 dly(2T, 0.5T) = (0, 11)
3680 10:03:39.173212 best DQS1 dly(2T, 0.5T) = (0, 11)
3681 10:03:39.176860 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3682 10:03:39.179525 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3683 10:03:39.182770 best DQS0 dly(2T, 0.5T) = (0, 11)
3684 10:03:39.186034 best DQS1 dly(2T, 0.5T) = (0, 11)
3685 10:03:39.189379 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3686 10:03:39.193373 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3687 10:03:39.196424 Pre-setting of DQS Precalculation
3688 10:03:39.202977 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3689 10:03:39.209932 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3690 10:03:39.215811 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3691 10:03:39.216316
3692 10:03:39.216644
3693 10:03:39.218920 [Calibration Summary] 2400 Mbps
3694 10:03:39.219329 CH 0, Rank 0
3695 10:03:39.222903 SW Impedance : PASS
3696 10:03:39.225660 DUTY Scan : NO K
3697 10:03:39.226160 ZQ Calibration : PASS
3698 10:03:39.229482 Jitter Meter : NO K
3699 10:03:39.232499 CBT Training : PASS
3700 10:03:39.233008 Write leveling : PASS
3701 10:03:39.235567 RX DQS gating : PASS
3702 10:03:39.238880 RX DQ/DQS(RDDQC) : PASS
3703 10:03:39.239438 TX DQ/DQS : PASS
3704 10:03:39.242009 RX DATLAT : PASS
3705 10:03:39.246067 RX DQ/DQS(Engine): PASS
3706 10:03:39.246616 TX OE : NO K
3707 10:03:39.248880 All Pass.
3708 10:03:39.249385
3709 10:03:39.249744 CH 0, Rank 1
3710 10:03:39.251838 SW Impedance : PASS
3711 10:03:39.252258 DUTY Scan : NO K
3712 10:03:39.255011 ZQ Calibration : PASS
3713 10:03:39.259442 Jitter Meter : NO K
3714 10:03:39.259973 CBT Training : PASS
3715 10:03:39.261891 Write leveling : PASS
3716 10:03:39.262341 RX DQS gating : PASS
3717 10:03:39.265126 RX DQ/DQS(RDDQC) : PASS
3718 10:03:39.268394 TX DQ/DQS : PASS
3719 10:03:39.268941 RX DATLAT : PASS
3720 10:03:39.272043 RX DQ/DQS(Engine): PASS
3721 10:03:39.274866 TX OE : NO K
3722 10:03:39.275281 All Pass.
3723 10:03:39.275605
3724 10:03:39.275920 CH 1, Rank 0
3725 10:03:39.278361 SW Impedance : PASS
3726 10:03:39.281363 DUTY Scan : NO K
3727 10:03:39.281774 ZQ Calibration : PASS
3728 10:03:39.284601 Jitter Meter : NO K
3729 10:03:39.288192 CBT Training : PASS
3730 10:03:39.288694 Write leveling : PASS
3731 10:03:39.291534 RX DQS gating : PASS
3732 10:03:39.294971 RX DQ/DQS(RDDQC) : PASS
3733 10:03:39.295381 TX DQ/DQS : PASS
3734 10:03:39.298089 RX DATLAT : PASS
3735 10:03:39.301411 RX DQ/DQS(Engine): PASS
3736 10:03:39.301914 TX OE : NO K
3737 10:03:39.304643 All Pass.
3738 10:03:39.305051
3739 10:03:39.305376 CH 1, Rank 1
3740 10:03:39.307610 SW Impedance : PASS
3741 10:03:39.308022 DUTY Scan : NO K
3742 10:03:39.311165 ZQ Calibration : PASS
3743 10:03:39.314970 Jitter Meter : NO K
3744 10:03:39.315472 CBT Training : PASS
3745 10:03:39.318320 Write leveling : PASS
3746 10:03:39.321053 RX DQS gating : PASS
3747 10:03:39.321579 RX DQ/DQS(RDDQC) : PASS
3748 10:03:39.324841 TX DQ/DQS : PASS
3749 10:03:39.327525 RX DATLAT : PASS
3750 10:03:39.328070 RX DQ/DQS(Engine): PASS
3751 10:03:39.331382 TX OE : NO K
3752 10:03:39.331927 All Pass.
3753 10:03:39.332291
3754 10:03:39.334303 DramC Write-DBI off
3755 10:03:39.337968 PER_BANK_REFRESH: Hybrid Mode
3756 10:03:39.338563 TX_TRACKING: ON
3757 10:03:39.347953 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3758 10:03:39.351172 [FAST_K] Save calibration result to emmc
3759 10:03:39.353943 dramc_set_vcore_voltage set vcore to 650000
3760 10:03:39.357496 Read voltage for 600, 5
3761 10:03:39.358038 Vio18 = 0
3762 10:03:39.358588 Vcore = 650000
3763 10:03:39.360371 Vdram = 0
3764 10:03:39.360821 Vddq = 0
3765 10:03:39.361181 Vmddr = 0
3766 10:03:39.367174 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3767 10:03:39.371077 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3768 10:03:39.373883 MEM_TYPE=3, freq_sel=19
3769 10:03:39.377010 sv_algorithm_assistance_LP4_1600
3770 10:03:39.380630 ============ PULL DRAM RESETB DOWN ============
3771 10:03:39.388979 ========== PULL DRAM RESETB DOWN end =========
3772 10:03:39.390057 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3773 10:03:39.393646 ===================================
3774 10:03:39.397098 LPDDR4 DRAM CONFIGURATION
3775 10:03:39.400509 ===================================
3776 10:03:39.401057 EX_ROW_EN[0] = 0x0
3777 10:03:39.403463 EX_ROW_EN[1] = 0x0
3778 10:03:39.404009 LP4Y_EN = 0x0
3779 10:03:39.406909 WORK_FSP = 0x0
3780 10:03:39.407453 WL = 0x2
3781 10:03:39.409760 RL = 0x2
3782 10:03:39.410213 BL = 0x2
3783 10:03:39.413359 RPST = 0x0
3784 10:03:39.413904 RD_PRE = 0x0
3785 10:03:39.416787 WR_PRE = 0x1
3786 10:03:39.420156 WR_PST = 0x0
3787 10:03:39.420698 DBI_WR = 0x0
3788 10:03:39.423428 DBI_RD = 0x0
3789 10:03:39.423972 OTF = 0x1
3790 10:03:39.426836 ===================================
3791 10:03:39.430399 ===================================
3792 10:03:39.432998 ANA top config
3793 10:03:39.436108 ===================================
3794 10:03:39.436565 DLL_ASYNC_EN = 0
3795 10:03:39.440063 ALL_SLAVE_EN = 1
3796 10:03:39.443591 NEW_RANK_MODE = 1
3797 10:03:39.446324 DLL_IDLE_MODE = 1
3798 10:03:39.446931 LP45_APHY_COMB_EN = 1
3799 10:03:39.449645 TX_ODT_DIS = 1
3800 10:03:39.452787 NEW_8X_MODE = 1
3801 10:03:39.455796 ===================================
3802 10:03:39.459389 ===================================
3803 10:03:39.462866 data_rate = 1200
3804 10:03:39.465860 CKR = 1
3805 10:03:39.469238 DQ_P2S_RATIO = 8
3806 10:03:39.473023 ===================================
3807 10:03:39.473570 CA_P2S_RATIO = 8
3808 10:03:39.475596 DQ_CA_OPEN = 0
3809 10:03:39.478746 DQ_SEMI_OPEN = 0
3810 10:03:39.482189 CA_SEMI_OPEN = 0
3811 10:03:39.485660 CA_FULL_RATE = 0
3812 10:03:39.489148 DQ_CKDIV4_EN = 1
3813 10:03:39.489672 CA_CKDIV4_EN = 1
3814 10:03:39.492070 CA_PREDIV_EN = 0
3815 10:03:39.495384 PH8_DLY = 0
3816 10:03:39.498874 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3817 10:03:39.502049 DQ_AAMCK_DIV = 4
3818 10:03:39.505642 CA_AAMCK_DIV = 4
3819 10:03:39.506193 CA_ADMCK_DIV = 4
3820 10:03:39.508591 DQ_TRACK_CA_EN = 0
3821 10:03:39.512247 CA_PICK = 600
3822 10:03:39.516054 CA_MCKIO = 600
3823 10:03:39.518281 MCKIO_SEMI = 0
3824 10:03:39.521412 PLL_FREQ = 2288
3825 10:03:39.525284 DQ_UI_PI_RATIO = 32
3826 10:03:39.528565 CA_UI_PI_RATIO = 0
3827 10:03:39.531874 ===================================
3828 10:03:39.535075 ===================================
3829 10:03:39.535627 memory_type:LPDDR4
3830 10:03:39.538888 GP_NUM : 10
3831 10:03:39.541989 SRAM_EN : 1
3832 10:03:39.542591 MD32_EN : 0
3833 10:03:39.545025 ===================================
3834 10:03:39.548223 [ANA_INIT] >>>>>>>>>>>>>>
3835 10:03:39.551935 <<<<<< [CONFIGURE PHASE]: ANA_TX
3836 10:03:39.555106 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3837 10:03:39.558606 ===================================
3838 10:03:39.561872 data_rate = 1200,PCW = 0X5800
3839 10:03:39.564474 ===================================
3840 10:03:39.568031 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3841 10:03:39.571140 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3842 10:03:39.578174 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3843 10:03:39.580972 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3844 10:03:39.584759 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3845 10:03:39.588173 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3846 10:03:39.591255 [ANA_INIT] flow start
3847 10:03:39.594461 [ANA_INIT] PLL >>>>>>>>
3848 10:03:39.594916 [ANA_INIT] PLL <<<<<<<<
3849 10:03:39.597923 [ANA_INIT] MIDPI >>>>>>>>
3850 10:03:39.601155 [ANA_INIT] MIDPI <<<<<<<<
3851 10:03:39.604297 [ANA_INIT] DLL >>>>>>>>
3852 10:03:39.604844 [ANA_INIT] flow end
3853 10:03:39.607625 ============ LP4 DIFF to SE enter ============
3854 10:03:39.614169 ============ LP4 DIFF to SE exit ============
3855 10:03:39.614770 [ANA_INIT] <<<<<<<<<<<<<
3856 10:03:39.617377 [Flow] Enable top DCM control >>>>>
3857 10:03:39.620668 [Flow] Enable top DCM control <<<<<
3858 10:03:39.623711 Enable DLL master slave shuffle
3859 10:03:39.630230 ==============================================================
3860 10:03:39.633687 Gating Mode config
3861 10:03:39.636994 ==============================================================
3862 10:03:39.640513 Config description:
3863 10:03:39.650247 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3864 10:03:39.656359 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3865 10:03:39.660031 SELPH_MODE 0: By rank 1: By Phase
3866 10:03:39.666922 ==============================================================
3867 10:03:39.670411 GAT_TRACK_EN = 1
3868 10:03:39.673481 RX_GATING_MODE = 2
3869 10:03:39.676366 RX_GATING_TRACK_MODE = 2
3870 10:03:39.676823 SELPH_MODE = 1
3871 10:03:39.679664 PICG_EARLY_EN = 1
3872 10:03:39.682995 VALID_LAT_VALUE = 1
3873 10:03:39.689662 ==============================================================
3874 10:03:39.692641 Enter into Gating configuration >>>>
3875 10:03:39.696400 Exit from Gating configuration <<<<
3876 10:03:39.699792 Enter into DVFS_PRE_config >>>>>
3877 10:03:39.709521 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3878 10:03:39.712543 Exit from DVFS_PRE_config <<<<<
3879 10:03:39.716213 Enter into PICG configuration >>>>
3880 10:03:39.719149 Exit from PICG configuration <<<<
3881 10:03:39.722699 [RX_INPUT] configuration >>>>>
3882 10:03:39.726247 [RX_INPUT] configuration <<<<<
3883 10:03:39.732487 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3884 10:03:39.736154 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3885 10:03:39.743059 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3886 10:03:39.749111 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3887 10:03:39.755379 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3888 10:03:39.761988 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3889 10:03:39.765089 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3890 10:03:39.769525 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3891 10:03:39.772024 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3892 10:03:39.778805 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3893 10:03:39.781625 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3894 10:03:39.785221 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3895 10:03:39.788565 ===================================
3896 10:03:39.792424 LPDDR4 DRAM CONFIGURATION
3897 10:03:39.795177 ===================================
3898 10:03:39.798143 EX_ROW_EN[0] = 0x0
3899 10:03:39.798748 EX_ROW_EN[1] = 0x0
3900 10:03:39.801924 LP4Y_EN = 0x0
3901 10:03:39.802522 WORK_FSP = 0x0
3902 10:03:39.804800 WL = 0x2
3903 10:03:39.805260 RL = 0x2
3904 10:03:39.808408 BL = 0x2
3905 10:03:39.808961 RPST = 0x0
3906 10:03:39.811608 RD_PRE = 0x0
3907 10:03:39.812013 WR_PRE = 0x1
3908 10:03:39.815011 WR_PST = 0x0
3909 10:03:39.815417 DBI_WR = 0x0
3910 10:03:39.817825 DBI_RD = 0x0
3911 10:03:39.818229 OTF = 0x1
3912 10:03:39.821397 ===================================
3913 10:03:39.828441 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3914 10:03:39.831797 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3915 10:03:39.834289 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3916 10:03:39.837699 ===================================
3917 10:03:39.840886 LPDDR4 DRAM CONFIGURATION
3918 10:03:39.844804 ===================================
3919 10:03:39.847569 EX_ROW_EN[0] = 0x10
3920 10:03:39.848075 EX_ROW_EN[1] = 0x0
3921 10:03:39.850570 LP4Y_EN = 0x0
3922 10:03:39.850976 WORK_FSP = 0x0
3923 10:03:39.854162 WL = 0x2
3924 10:03:39.854762 RL = 0x2
3925 10:03:39.857439 BL = 0x2
3926 10:03:39.857939 RPST = 0x0
3927 10:03:39.860777 RD_PRE = 0x0
3928 10:03:39.861183 WR_PRE = 0x1
3929 10:03:39.864394 WR_PST = 0x0
3930 10:03:39.864899 DBI_WR = 0x0
3931 10:03:39.866990 DBI_RD = 0x0
3932 10:03:39.867395 OTF = 0x1
3933 10:03:39.870839 ===================================
3934 10:03:39.877294 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3935 10:03:39.881964 nWR fixed to 30
3936 10:03:39.885525 [ModeRegInit_LP4] CH0 RK0
3937 10:03:39.886185 [ModeRegInit_LP4] CH0 RK1
3938 10:03:39.888626 [ModeRegInit_LP4] CH1 RK0
3939 10:03:39.891746 [ModeRegInit_LP4] CH1 RK1
3940 10:03:39.892151 match AC timing 17
3941 10:03:39.898804 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3942 10:03:39.902096 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3943 10:03:39.905395 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3944 10:03:39.911450 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3945 10:03:39.914759 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3946 10:03:39.915165 ==
3947 10:03:39.918320 Dram Type= 6, Freq= 0, CH_0, rank 0
3948 10:03:39.921727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3949 10:03:39.924548 ==
3950 10:03:39.928196 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3951 10:03:39.934862 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3952 10:03:39.938028 [CA 0] Center 36 (6~67) winsize 62
3953 10:03:39.941347 [CA 1] Center 36 (6~67) winsize 62
3954 10:03:39.944584 [CA 2] Center 34 (4~65) winsize 62
3955 10:03:39.947786 [CA 3] Center 34 (3~65) winsize 63
3956 10:03:39.951000 [CA 4] Center 33 (3~64) winsize 62
3957 10:03:39.954188 [CA 5] Center 33 (3~64) winsize 62
3958 10:03:39.954682
3959 10:03:39.957744 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3960 10:03:39.958149
3961 10:03:39.961126 [CATrainingPosCal] consider 1 rank data
3962 10:03:39.965017 u2DelayCellTimex100 = 270/100 ps
3963 10:03:39.967298 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3964 10:03:39.971084 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3965 10:03:39.977977 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3966 10:03:39.980467 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3967 10:03:39.983959 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3968 10:03:39.987446 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3969 10:03:39.987861
3970 10:03:39.990674 CA PerBit enable=1, Macro0, CA PI delay=33
3971 10:03:39.991100
3972 10:03:39.994022 [CBTSetCACLKResult] CA Dly = 33
3973 10:03:39.994606 CS Dly: 5 (0~36)
3974 10:03:39.997068 ==
3975 10:03:39.997563 Dram Type= 6, Freq= 0, CH_0, rank 1
3976 10:03:40.003998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3977 10:03:40.004507 ==
3978 10:03:40.006831 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3979 10:03:40.013305 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3980 10:03:40.017549 [CA 0] Center 36 (6~67) winsize 62
3981 10:03:40.020497 [CA 1] Center 36 (6~67) winsize 62
3982 10:03:40.024377 [CA 2] Center 34 (4~65) winsize 62
3983 10:03:40.027390 [CA 3] Center 34 (4~65) winsize 62
3984 10:03:40.030428 [CA 4] Center 34 (3~65) winsize 63
3985 10:03:40.033819 [CA 5] Center 33 (3~64) winsize 62
3986 10:03:40.034382
3987 10:03:40.036980 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3988 10:03:40.037391
3989 10:03:40.040479 [CATrainingPosCal] consider 2 rank data
3990 10:03:40.043527 u2DelayCellTimex100 = 270/100 ps
3991 10:03:40.047152 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3992 10:03:40.053367 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3993 10:03:40.056724 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3994 10:03:40.060366 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3995 10:03:40.063572 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3996 10:03:40.066746 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3997 10:03:40.067161
3998 10:03:40.070135 CA PerBit enable=1, Macro0, CA PI delay=33
3999 10:03:40.070605
4000 10:03:40.073466 [CBTSetCACLKResult] CA Dly = 33
4001 10:03:40.076473 CS Dly: 5 (0~37)
4002 10:03:40.076886
4003 10:03:40.079927 ----->DramcWriteLeveling(PI) begin...
4004 10:03:40.080356 ==
4005 10:03:40.083286 Dram Type= 6, Freq= 0, CH_0, rank 0
4006 10:03:40.086184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4007 10:03:40.086660 ==
4008 10:03:40.089741 Write leveling (Byte 0): 31 => 31
4009 10:03:40.093220 Write leveling (Byte 1): 28 => 28
4010 10:03:40.096182 DramcWriteLeveling(PI) end<-----
4011 10:03:40.096681
4012 10:03:40.097004 ==
4013 10:03:40.099787 Dram Type= 6, Freq= 0, CH_0, rank 0
4014 10:03:40.102893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4015 10:03:40.103305 ==
4016 10:03:40.106387 [Gating] SW mode calibration
4017 10:03:40.113143 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4018 10:03:40.119906 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4019 10:03:40.123023 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4020 10:03:40.125871 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4021 10:03:40.132745 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4022 10:03:40.136103 0 9 12 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
4023 10:03:40.139562 0 9 16 | B1->B0 | 2d2d 2525 | 0 0 | (0 1) (0 0)
4024 10:03:40.145984 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
4025 10:03:40.149571 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4026 10:03:40.152575 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4027 10:03:40.159213 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4028 10:03:40.162470 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4029 10:03:40.169075 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4030 10:03:40.172301 0 10 12 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (0 0)
4031 10:03:40.175772 0 10 16 | B1->B0 | 3a3a 4444 | 0 1 | (0 0) (0 0)
4032 10:03:40.182198 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4033 10:03:40.185198 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4034 10:03:40.188776 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4035 10:03:40.194927 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4036 10:03:40.198573 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4037 10:03:40.201989 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4038 10:03:40.208397 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4039 10:03:40.211729 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4040 10:03:40.215567 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4041 10:03:40.218464 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4042 10:03:40.225049 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4043 10:03:40.228746 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4044 10:03:40.231424 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4045 10:03:40.238193 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4046 10:03:40.241678 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4047 10:03:40.244553 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4048 10:03:40.251268 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4049 10:03:40.255628 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4050 10:03:40.260875 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4051 10:03:40.264543 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4052 10:03:40.268081 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 10:03:40.274718 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 10:03:40.278177 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4055 10:03:40.281331 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4056 10:03:40.283900 Total UI for P1: 0, mck2ui 16
4057 10:03:40.287380 best dqsien dly found for B0: ( 0, 13, 12)
4058 10:03:40.290978 Total UI for P1: 0, mck2ui 16
4059 10:03:40.294446 best dqsien dly found for B1: ( 0, 13, 14)
4060 10:03:40.297487 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4061 10:03:40.300692 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4062 10:03:40.301142
4063 10:03:40.304309 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4064 10:03:40.310658 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4065 10:03:40.311202 [Gating] SW calibration Done
4066 10:03:40.313973 ==
4067 10:03:40.317313 Dram Type= 6, Freq= 0, CH_0, rank 0
4068 10:03:40.320534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4069 10:03:40.320986 ==
4070 10:03:40.321347 RX Vref Scan: 0
4071 10:03:40.321684
4072 10:03:40.323878 RX Vref 0 -> 0, step: 1
4073 10:03:40.324329
4074 10:03:40.327479 RX Delay -230 -> 252, step: 16
4075 10:03:40.330352 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4076 10:03:40.333612 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4077 10:03:40.340387 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4078 10:03:40.343729 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4079 10:03:40.347230 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4080 10:03:40.350299 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4081 10:03:40.356824 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4082 10:03:40.359968 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4083 10:03:40.363158 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4084 10:03:40.366494 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4085 10:03:40.372784 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4086 10:03:40.375983 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4087 10:03:40.379567 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4088 10:03:40.382850 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4089 10:03:40.389163 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4090 10:03:40.392824 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4091 10:03:40.393467 ==
4092 10:03:40.396058 Dram Type= 6, Freq= 0, CH_0, rank 0
4093 10:03:40.399313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4094 10:03:40.399815 ==
4095 10:03:40.402760 DQS Delay:
4096 10:03:40.403262 DQS0 = 0, DQS1 = 0
4097 10:03:40.403590 DQM Delay:
4098 10:03:40.406401 DQM0 = 42, DQM1 = 33
4099 10:03:40.406902 DQ Delay:
4100 10:03:40.409494 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4101 10:03:40.412443 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4102 10:03:40.416409 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4103 10:03:40.419232 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4104 10:03:40.419689
4105 10:03:40.420014
4106 10:03:40.420469 ==
4107 10:03:40.422531 Dram Type= 6, Freq= 0, CH_0, rank 0
4108 10:03:40.428973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4109 10:03:40.429487 ==
4110 10:03:40.429820
4111 10:03:40.430122
4112 10:03:40.430474 TX Vref Scan disable
4113 10:03:40.432975 == TX Byte 0 ==
4114 10:03:40.436360 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4115 10:03:40.443187 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4116 10:03:40.443692 == TX Byte 1 ==
4117 10:03:40.446409 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4118 10:03:40.452415 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4119 10:03:40.452921 ==
4120 10:03:40.455848 Dram Type= 6, Freq= 0, CH_0, rank 0
4121 10:03:40.459161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4122 10:03:40.459683 ==
4123 10:03:40.460017
4124 10:03:40.460319
4125 10:03:40.462525 TX Vref Scan disable
4126 10:03:40.465975 == TX Byte 0 ==
4127 10:03:40.469265 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4128 10:03:40.472306 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4129 10:03:40.475574 == TX Byte 1 ==
4130 10:03:40.478946 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4131 10:03:40.482452 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4132 10:03:40.482865
4133 10:03:40.485359 [DATLAT]
4134 10:03:40.486083 Freq=600, CH0 RK0
4135 10:03:40.486564
4136 10:03:40.488575 DATLAT Default: 0x9
4137 10:03:40.488982 0, 0xFFFF, sum = 0
4138 10:03:40.492141 1, 0xFFFF, sum = 0
4139 10:03:40.492647 2, 0xFFFF, sum = 0
4140 10:03:40.495046 3, 0xFFFF, sum = 0
4141 10:03:40.495483 4, 0xFFFF, sum = 0
4142 10:03:40.498411 5, 0xFFFF, sum = 0
4143 10:03:40.498825 6, 0xFFFF, sum = 0
4144 10:03:40.501985 7, 0xFFFF, sum = 0
4145 10:03:40.502449 8, 0x0, sum = 1
4146 10:03:40.505226 9, 0x0, sum = 2
4147 10:03:40.505781 10, 0x0, sum = 3
4148 10:03:40.508676 11, 0x0, sum = 4
4149 10:03:40.509190 best_step = 9
4150 10:03:40.509514
4151 10:03:40.509815 ==
4152 10:03:40.511817 Dram Type= 6, Freq= 0, CH_0, rank 0
4153 10:03:40.514724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4154 10:03:40.518474 ==
4155 10:03:40.518980 RX Vref Scan: 1
4156 10:03:40.519310
4157 10:03:40.521599 RX Vref 0 -> 0, step: 1
4158 10:03:40.522106
4159 10:03:40.524686 RX Delay -195 -> 252, step: 8
4160 10:03:40.525091
4161 10:03:40.528176 Set Vref, RX VrefLevel [Byte0]: 54
4162 10:03:40.532011 [Byte1]: 58
4163 10:03:40.532530
4164 10:03:40.534932 Final RX Vref Byte 0 = 54 to rank0
4165 10:03:40.538171 Final RX Vref Byte 1 = 58 to rank0
4166 10:03:40.541579 Final RX Vref Byte 0 = 54 to rank1
4167 10:03:40.544568 Final RX Vref Byte 1 = 58 to rank1==
4168 10:03:40.548527 Dram Type= 6, Freq= 0, CH_0, rank 0
4169 10:03:40.551244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4170 10:03:40.551752 ==
4171 10:03:40.555194 DQS Delay:
4172 10:03:40.555698 DQS0 = 0, DQS1 = 0
4173 10:03:40.556025 DQM Delay:
4174 10:03:40.557810 DQM0 = 42, DQM1 = 32
4175 10:03:40.558218 DQ Delay:
4176 10:03:40.561598 DQ0 =44, DQ1 =44, DQ2 =36, DQ3 =36
4177 10:03:40.565113 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =48
4178 10:03:40.568464 DQ8 =24, DQ9 =16, DQ10 =32, DQ11 =28
4179 10:03:40.570977 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4180 10:03:40.571496
4181 10:03:40.571820
4182 10:03:40.581196 [DQSOSCAuto] RK0, (LSB)MR18= 0x4840, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 396 ps
4183 10:03:40.584820 CH0 RK0: MR19=808, MR18=4840
4184 10:03:40.587594 CH0_RK0: MR19=0x808, MR18=0x4840, DQSOSC=396, MR23=63, INC=167, DEC=111
4185 10:03:40.591174
4186 10:03:40.594504 ----->DramcWriteLeveling(PI) begin...
4187 10:03:40.595070 ==
4188 10:03:40.597798 Dram Type= 6, Freq= 0, CH_0, rank 1
4189 10:03:40.600858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4190 10:03:40.601411 ==
4191 10:03:40.603994 Write leveling (Byte 0): 35 => 35
4192 10:03:40.607124 Write leveling (Byte 1): 31 => 31
4193 10:03:40.610672 DramcWriteLeveling(PI) end<-----
4194 10:03:40.611239
4195 10:03:40.611596 ==
4196 10:03:40.613592 Dram Type= 6, Freq= 0, CH_0, rank 1
4197 10:03:40.617119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4198 10:03:40.617668 ==
4199 10:03:40.620868 [Gating] SW mode calibration
4200 10:03:40.627939 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4201 10:03:40.633494 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4202 10:03:40.637359 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4203 10:03:40.640252 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4204 10:03:40.646901 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4205 10:03:40.650293 0 9 12 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (1 0)
4206 10:03:40.653746 0 9 16 | B1->B0 | 2e2e 2525 | 0 0 | (1 1) (0 0)
4207 10:03:40.659857 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4208 10:03:40.663026 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4209 10:03:40.666505 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4210 10:03:40.673228 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4211 10:03:40.676701 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4212 10:03:40.679642 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4213 10:03:40.686243 0 10 12 | B1->B0 | 2525 3636 | 0 0 | (0 0) (1 1)
4214 10:03:40.689547 0 10 16 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
4215 10:03:40.693023 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4216 10:03:40.699906 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4217 10:03:40.703353 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4218 10:03:40.706485 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4219 10:03:40.713111 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4220 10:03:40.715900 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4221 10:03:40.718944 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4222 10:03:40.726193 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4223 10:03:40.729502 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4224 10:03:40.732796 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4225 10:03:40.739093 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4226 10:03:40.742226 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4227 10:03:40.745787 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4228 10:03:40.751975 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4229 10:03:40.755677 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4230 10:03:40.758735 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4231 10:03:40.765171 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4232 10:03:40.768938 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4233 10:03:40.771918 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4234 10:03:40.778573 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4235 10:03:40.781652 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4236 10:03:40.784811 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 10:03:40.791608 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4238 10:03:40.795221 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4239 10:03:40.798384 Total UI for P1: 0, mck2ui 16
4240 10:03:40.801811 best dqsien dly found for B0: ( 0, 13, 12)
4241 10:03:40.805175 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4242 10:03:40.808377 Total UI for P1: 0, mck2ui 16
4243 10:03:40.811907 best dqsien dly found for B1: ( 0, 13, 14)
4244 10:03:40.814619 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4245 10:03:40.818456 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4246 10:03:40.821858
4247 10:03:40.825340 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4248 10:03:40.828420 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4249 10:03:40.831500 [Gating] SW calibration Done
4250 10:03:40.832053 ==
4251 10:03:40.834563 Dram Type= 6, Freq= 0, CH_0, rank 1
4252 10:03:40.837874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4253 10:03:40.838520 ==
4254 10:03:40.838889 RX Vref Scan: 0
4255 10:03:40.841505
4256 10:03:40.841950 RX Vref 0 -> 0, step: 1
4257 10:03:40.842533
4258 10:03:40.844971 RX Delay -230 -> 252, step: 16
4259 10:03:40.847860 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4260 10:03:40.854708 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4261 10:03:40.857695 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4262 10:03:40.861076 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4263 10:03:40.864076 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4264 10:03:40.870952 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4265 10:03:40.874016 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4266 10:03:40.877749 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4267 10:03:40.881153 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4268 10:03:40.883787 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4269 10:03:40.890652 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4270 10:03:40.893740 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4271 10:03:40.897202 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4272 10:03:40.903733 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4273 10:03:40.906763 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4274 10:03:40.910087 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4275 10:03:40.910698 ==
4276 10:03:40.913888 Dram Type= 6, Freq= 0, CH_0, rank 1
4277 10:03:40.917309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4278 10:03:40.917862 ==
4279 10:03:40.920134 DQS Delay:
4280 10:03:40.920677 DQS0 = 0, DQS1 = 0
4281 10:03:40.923298 DQM Delay:
4282 10:03:40.923842 DQM0 = 42, DQM1 = 31
4283 10:03:40.924206 DQ Delay:
4284 10:03:40.926487 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4285 10:03:40.930045 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4286 10:03:40.933587 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4287 10:03:40.936671 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4288 10:03:40.937230
4289 10:03:40.937594
4290 10:03:40.940606 ==
4291 10:03:40.943184 Dram Type= 6, Freq= 0, CH_0, rank 1
4292 10:03:40.946863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4293 10:03:40.947328 ==
4294 10:03:40.947695
4295 10:03:40.948033
4296 10:03:40.949981 TX Vref Scan disable
4297 10:03:40.950581 == TX Byte 0 ==
4298 10:03:40.956274 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4299 10:03:40.959769 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4300 10:03:40.960233 == TX Byte 1 ==
4301 10:03:40.965938 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4302 10:03:40.969428 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4303 10:03:40.969974 ==
4304 10:03:40.972656 Dram Type= 6, Freq= 0, CH_0, rank 1
4305 10:03:40.976069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4306 10:03:40.976621 ==
4307 10:03:40.976989
4308 10:03:40.977328
4309 10:03:40.979474 TX Vref Scan disable
4310 10:03:40.982600 == TX Byte 0 ==
4311 10:03:40.985896 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4312 10:03:40.992795 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4313 10:03:40.993319 == TX Byte 1 ==
4314 10:03:40.995750 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4315 10:03:41.002216 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4316 10:03:41.002684
4317 10:03:41.003150 [DATLAT]
4318 10:03:41.003481 Freq=600, CH0 RK1
4319 10:03:41.003785
4320 10:03:41.005556 DATLAT Default: 0x9
4321 10:03:41.005971 0, 0xFFFF, sum = 0
4322 10:03:41.009367 1, 0xFFFF, sum = 0
4323 10:03:41.012261 2, 0xFFFF, sum = 0
4324 10:03:41.012681 3, 0xFFFF, sum = 0
4325 10:03:41.015967 4, 0xFFFF, sum = 0
4326 10:03:41.016477 5, 0xFFFF, sum = 0
4327 10:03:41.018865 6, 0xFFFF, sum = 0
4328 10:03:41.019286 7, 0xFFFF, sum = 0
4329 10:03:41.022156 8, 0x0, sum = 1
4330 10:03:41.022619 9, 0x0, sum = 2
4331 10:03:41.025814 10, 0x0, sum = 3
4332 10:03:41.026392 11, 0x0, sum = 4
4333 10:03:41.026745 best_step = 9
4334 10:03:41.027054
4335 10:03:41.029114 ==
4336 10:03:41.031811 Dram Type= 6, Freq= 0, CH_0, rank 1
4337 10:03:41.035715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4338 10:03:41.036242 ==
4339 10:03:41.036581 RX Vref Scan: 0
4340 10:03:41.036891
4341 10:03:41.038830 RX Vref 0 -> 0, step: 1
4342 10:03:41.039244
4343 10:03:41.041536 RX Delay -195 -> 252, step: 8
4344 10:03:41.048859 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4345 10:03:41.051934 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4346 10:03:41.055033 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4347 10:03:41.058314 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4348 10:03:41.065027 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4349 10:03:41.068495 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4350 10:03:41.071476 iDelay=205, Bit 6, Center 52 (-99 ~ 204) 304
4351 10:03:41.075494 iDelay=205, Bit 7, Center 44 (-107 ~ 196) 304
4352 10:03:41.078328 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4353 10:03:41.084437 iDelay=205, Bit 9, Center 16 (-139 ~ 172) 312
4354 10:03:41.088358 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4355 10:03:41.090946 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4356 10:03:41.094482 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4357 10:03:41.101129 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4358 10:03:41.104881 iDelay=205, Bit 14, Center 44 (-115 ~ 204) 320
4359 10:03:41.107660 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4360 10:03:41.108071 ==
4361 10:03:41.110785 Dram Type= 6, Freq= 0, CH_0, rank 1
4362 10:03:41.113951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4363 10:03:41.117518 ==
4364 10:03:41.118013 DQS Delay:
4365 10:03:41.118574 DQS0 = 0, DQS1 = 0
4366 10:03:41.120665 DQM Delay:
4367 10:03:41.121067 DQM0 = 40, DQM1 = 33
4368 10:03:41.123913 DQ Delay:
4369 10:03:41.127345 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =36
4370 10:03:41.130696 DQ4 =44, DQ5 =28, DQ6 =52, DQ7 =44
4371 10:03:41.131104 DQ8 =24, DQ9 =16, DQ10 =36, DQ11 =28
4372 10:03:41.137409 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4373 10:03:41.137908
4374 10:03:41.138227
4375 10:03:41.143689 [DQSOSCAuto] RK1, (LSB)MR18= 0x423e, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
4376 10:03:41.147543 CH0 RK1: MR19=808, MR18=423E
4377 10:03:41.153629 CH0_RK1: MR19=0x808, MR18=0x423E, DQSOSC=397, MR23=63, INC=166, DEC=110
4378 10:03:41.157409 [RxdqsGatingPostProcess] freq 600
4379 10:03:41.159995 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4380 10:03:41.163512 Pre-setting of DQS Precalculation
4381 10:03:41.170030 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4382 10:03:41.170589 ==
4383 10:03:41.173397 Dram Type= 6, Freq= 0, CH_1, rank 0
4384 10:03:41.176791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4385 10:03:41.177197 ==
4386 10:03:41.183089 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4387 10:03:41.189576 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4388 10:03:41.193744 [CA 0] Center 35 (5~66) winsize 62
4389 10:03:41.196757 [CA 1] Center 35 (5~66) winsize 62
4390 10:03:41.200236 [CA 2] Center 34 (4~65) winsize 62
4391 10:03:41.203453 [CA 3] Center 34 (3~65) winsize 63
4392 10:03:41.206056 [CA 4] Center 34 (3~65) winsize 63
4393 10:03:41.209816 [CA 5] Center 34 (3~65) winsize 63
4394 10:03:41.210367
4395 10:03:41.213079 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4396 10:03:41.213483
4397 10:03:41.216054 [CATrainingPosCal] consider 1 rank data
4398 10:03:41.219767 u2DelayCellTimex100 = 270/100 ps
4399 10:03:41.222612 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4400 10:03:41.226182 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4401 10:03:41.229103 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4402 10:03:41.232452 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
4403 10:03:41.235660 CA4 delay=34 (3~65),Diff = 0 PI (0 cell)
4404 10:03:41.238920 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4405 10:03:41.242161
4406 10:03:41.245714 CA PerBit enable=1, Macro0, CA PI delay=34
4407 10:03:41.246127
4408 10:03:41.248721 [CBTSetCACLKResult] CA Dly = 34
4409 10:03:41.249132 CS Dly: 5 (0~36)
4410 10:03:41.249461 ==
4411 10:03:41.253098 Dram Type= 6, Freq= 0, CH_1, rank 1
4412 10:03:41.255831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4413 10:03:41.259238 ==
4414 10:03:41.262217 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4415 10:03:41.268461 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4416 10:03:41.271748 [CA 0] Center 35 (5~66) winsize 62
4417 10:03:41.275035 [CA 1] Center 35 (5~66) winsize 62
4418 10:03:41.278284 [CA 2] Center 34 (4~65) winsize 62
4419 10:03:41.281453 [CA 3] Center 33 (3~64) winsize 62
4420 10:03:41.284811 [CA 4] Center 34 (4~65) winsize 62
4421 10:03:41.288105 [CA 5] Center 33 (3~64) winsize 62
4422 10:03:41.288509
4423 10:03:41.291559 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4424 10:03:41.291846
4425 10:03:41.295126 [CATrainingPosCal] consider 2 rank data
4426 10:03:41.298380 u2DelayCellTimex100 = 270/100 ps
4427 10:03:41.301601 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4428 10:03:41.304696 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4429 10:03:41.311145 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4430 10:03:41.314537 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4431 10:03:41.318119 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4432 10:03:41.321273 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4433 10:03:41.321674
4434 10:03:41.324242 CA PerBit enable=1, Macro0, CA PI delay=33
4435 10:03:41.324657
4436 10:03:41.327857 [CBTSetCACLKResult] CA Dly = 33
4437 10:03:41.328149 CS Dly: 5 (0~37)
4438 10:03:41.328389
4439 10:03:41.334182 ----->DramcWriteLeveling(PI) begin...
4440 10:03:41.334438 ==
4441 10:03:41.337849 Dram Type= 6, Freq= 0, CH_1, rank 0
4442 10:03:41.340758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4443 10:03:41.341171 ==
4444 10:03:41.344414 Write leveling (Byte 0): 28 => 28
4445 10:03:41.347301 Write leveling (Byte 1): 31 => 31
4446 10:03:41.350913 DramcWriteLeveling(PI) end<-----
4447 10:03:41.351203
4448 10:03:41.351433 ==
4449 10:03:41.353912 Dram Type= 6, Freq= 0, CH_1, rank 0
4450 10:03:41.357133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4451 10:03:41.357312 ==
4452 10:03:41.360668 [Gating] SW mode calibration
4453 10:03:41.367429 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4454 10:03:41.373540 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4455 10:03:41.377066 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4456 10:03:41.380218 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4457 10:03:41.386912 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4458 10:03:41.390383 0 9 12 | B1->B0 | 3030 3030 | 1 0 | (1 1) (0 1)
4459 10:03:41.393590 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4460 10:03:41.400000 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4461 10:03:41.403535 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4462 10:03:41.407093 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4463 10:03:41.413613 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4464 10:03:41.416560 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4465 10:03:41.420013 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4466 10:03:41.426620 0 10 12 | B1->B0 | 3434 3838 | 0 1 | (0 0) (0 0)
4467 10:03:41.429915 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4468 10:03:41.433986 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4469 10:03:41.439696 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4470 10:03:41.443236 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4471 10:03:41.446290 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4472 10:03:41.452834 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4473 10:03:41.456453 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4474 10:03:41.459726 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4475 10:03:41.466328 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4476 10:03:41.469492 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4477 10:03:41.472868 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4478 10:03:41.478851 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4479 10:03:41.482273 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4480 10:03:41.485662 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4481 10:03:41.492172 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 10:03:41.495795 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 10:03:41.498900 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4484 10:03:41.505331 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4485 10:03:41.508299 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4486 10:03:41.512161 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 10:03:41.518176 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 10:03:41.521517 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 10:03:41.524889 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 10:03:41.531993 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4491 10:03:41.535431 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4492 10:03:41.537995 Total UI for P1: 0, mck2ui 16
4493 10:03:41.541477 best dqsien dly found for B0: ( 0, 13, 12)
4494 10:03:41.545114 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4495 10:03:41.548449 Total UI for P1: 0, mck2ui 16
4496 10:03:41.551602 best dqsien dly found for B1: ( 0, 13, 14)
4497 10:03:41.554721 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4498 10:03:41.558815 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4499 10:03:41.562198
4500 10:03:41.565314 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4501 10:03:41.568300 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4502 10:03:41.571922 [Gating] SW calibration Done
4503 10:03:41.572429 ==
4504 10:03:41.575272 Dram Type= 6, Freq= 0, CH_1, rank 0
4505 10:03:41.578056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4506 10:03:41.578622 ==
4507 10:03:41.581455 RX Vref Scan: 0
4508 10:03:41.582017
4509 10:03:41.582420 RX Vref 0 -> 0, step: 1
4510 10:03:41.582753
4511 10:03:41.585063 RX Delay -230 -> 252, step: 16
4512 10:03:41.587900 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4513 10:03:41.594644 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4514 10:03:41.597861 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4515 10:03:41.601245 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4516 10:03:41.604313 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4517 10:03:41.611451 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4518 10:03:41.614821 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4519 10:03:41.618222 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4520 10:03:41.621149 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4521 10:03:41.624310 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4522 10:03:41.630732 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4523 10:03:41.634173 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4524 10:03:41.637764 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4525 10:03:41.640728 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4526 10:03:41.647367 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4527 10:03:41.650922 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4528 10:03:41.651472 ==
4529 10:03:41.654103 Dram Type= 6, Freq= 0, CH_1, rank 0
4530 10:03:41.657285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4531 10:03:41.657829 ==
4532 10:03:41.660549 DQS Delay:
4533 10:03:41.661010 DQS0 = 0, DQS1 = 0
4534 10:03:41.663540 DQM Delay:
4535 10:03:41.663992 DQM0 = 46, DQM1 = 39
4536 10:03:41.664353 DQ Delay:
4537 10:03:41.666797 DQ0 =57, DQ1 =41, DQ2 =33, DQ3 =41
4538 10:03:41.670713 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4539 10:03:41.673628 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4540 10:03:41.676986 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4541 10:03:41.677496
4542 10:03:41.677826
4543 10:03:41.680183 ==
4544 10:03:41.683697 Dram Type= 6, Freq= 0, CH_1, rank 0
4545 10:03:41.686857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4546 10:03:41.687274 ==
4547 10:03:41.687605
4548 10:03:41.687955
4549 10:03:41.690108 TX Vref Scan disable
4550 10:03:41.690554 == TX Byte 0 ==
4551 10:03:41.696343 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4552 10:03:41.700116 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4553 10:03:41.700655 == TX Byte 1 ==
4554 10:03:41.706463 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4555 10:03:41.709757 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4556 10:03:41.710310 ==
4557 10:03:41.713542 Dram Type= 6, Freq= 0, CH_1, rank 0
4558 10:03:41.716443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4559 10:03:41.717086 ==
4560 10:03:41.717438
4561 10:03:41.717749
4562 10:03:41.720111 TX Vref Scan disable
4563 10:03:41.722807 == TX Byte 0 ==
4564 10:03:41.726419 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4565 10:03:41.730183 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4566 10:03:41.732548 == TX Byte 1 ==
4567 10:03:41.736165 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4568 10:03:41.742595 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4569 10:03:41.743101
4570 10:03:41.743425 [DATLAT]
4571 10:03:41.743729 Freq=600, CH1 RK0
4572 10:03:41.744023
4573 10:03:41.745936 DATLAT Default: 0x9
4574 10:03:41.746664 0, 0xFFFF, sum = 0
4575 10:03:41.749733 1, 0xFFFF, sum = 0
4576 10:03:41.750240 2, 0xFFFF, sum = 0
4577 10:03:41.752786 3, 0xFFFF, sum = 0
4578 10:03:41.756005 4, 0xFFFF, sum = 0
4579 10:03:41.756423 5, 0xFFFF, sum = 0
4580 10:03:41.759446 6, 0xFFFF, sum = 0
4581 10:03:41.759958 7, 0xFFFF, sum = 0
4582 10:03:41.762322 8, 0x0, sum = 1
4583 10:03:41.762836 9, 0x0, sum = 2
4584 10:03:41.763171 10, 0x0, sum = 3
4585 10:03:41.765835 11, 0x0, sum = 4
4586 10:03:41.766281 best_step = 9
4587 10:03:41.766615
4588 10:03:41.768632 ==
4589 10:03:41.769043 Dram Type= 6, Freq= 0, CH_1, rank 0
4590 10:03:41.775708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4591 10:03:41.776220 ==
4592 10:03:41.776553 RX Vref Scan: 1
4593 10:03:41.776861
4594 10:03:41.778833 RX Vref 0 -> 0, step: 1
4595 10:03:41.779244
4596 10:03:41.782619 RX Delay -179 -> 252, step: 8
4597 10:03:41.783125
4598 10:03:41.785198 Set Vref, RX VrefLevel [Byte0]: 52
4599 10:03:41.788636 [Byte1]: 53
4600 10:03:41.789135
4601 10:03:41.791732 Final RX Vref Byte 0 = 52 to rank0
4602 10:03:41.795694 Final RX Vref Byte 1 = 53 to rank0
4603 10:03:41.798797 Final RX Vref Byte 0 = 52 to rank1
4604 10:03:41.802206 Final RX Vref Byte 1 = 53 to rank1==
4605 10:03:41.805335 Dram Type= 6, Freq= 0, CH_1, rank 0
4606 10:03:41.808400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4607 10:03:41.811901 ==
4608 10:03:41.812406 DQS Delay:
4609 10:03:41.812741 DQS0 = 0, DQS1 = 0
4610 10:03:41.814810 DQM Delay:
4611 10:03:41.815221 DQM0 = 41, DQM1 = 34
4612 10:03:41.818046 DQ Delay:
4613 10:03:41.821554 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4614 10:03:41.824884 DQ4 =36, DQ5 =48, DQ6 =52, DQ7 =36
4615 10:03:41.827930 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =28
4616 10:03:41.831511 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =40
4617 10:03:41.832017
4618 10:03:41.832346
4619 10:03:41.837859 [DQSOSCAuto] RK0, (LSB)MR18= 0x334c, (MSB)MR19= 0x808, tDQSOscB0 = 395 ps tDQSOscB1 = 400 ps
4620 10:03:41.840937 CH1 RK0: MR19=808, MR18=334C
4621 10:03:41.847935 CH1_RK0: MR19=0x808, MR18=0x334C, DQSOSC=395, MR23=63, INC=168, DEC=112
4622 10:03:41.848422
4623 10:03:41.851732 ----->DramcWriteLeveling(PI) begin...
4624 10:03:41.852240 ==
4625 10:03:41.854372 Dram Type= 6, Freq= 0, CH_1, rank 1
4626 10:03:41.857436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4627 10:03:41.857942 ==
4628 10:03:41.861272 Write leveling (Byte 0): 29 => 29
4629 10:03:41.864134 Write leveling (Byte 1): 28 => 28
4630 10:03:41.867235 DramcWriteLeveling(PI) end<-----
4631 10:03:41.867650
4632 10:03:41.867975 ==
4633 10:03:41.870425 Dram Type= 6, Freq= 0, CH_1, rank 1
4634 10:03:41.874079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4635 10:03:41.877434 ==
4636 10:03:41.877972 [Gating] SW mode calibration
4637 10:03:41.886917 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4638 10:03:41.890781 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4639 10:03:41.893966 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4640 10:03:41.900337 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4641 10:03:41.903876 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4642 10:03:41.907266 0 9 12 | B1->B0 | 3131 2f2f | 0 0 | (0 0) (1 1)
4643 10:03:41.913476 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4644 10:03:41.916770 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4645 10:03:41.920020 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4646 10:03:41.926512 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4647 10:03:41.929892 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4648 10:03:41.933299 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4649 10:03:41.939866 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4650 10:03:41.942712 0 10 12 | B1->B0 | 3131 3c3c | 1 1 | (0 0) (0 0)
4651 10:03:41.945963 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4652 10:03:41.952696 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4653 10:03:41.956019 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4654 10:03:41.959060 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4655 10:03:41.966066 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4656 10:03:41.969607 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4657 10:03:41.973142 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4658 10:03:41.979318 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4659 10:03:41.982575 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4660 10:03:41.986014 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4661 10:03:41.992365 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4662 10:03:41.995694 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4663 10:03:41.998941 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4664 10:03:42.005476 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4665 10:03:42.009004 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4666 10:03:42.012284 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4667 10:03:42.018828 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4668 10:03:42.022224 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4669 10:03:42.025700 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4670 10:03:42.032373 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4671 10:03:42.035624 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4672 10:03:42.038629 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4673 10:03:42.045330 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4674 10:03:42.048850 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4675 10:03:42.051797 Total UI for P1: 0, mck2ui 16
4676 10:03:42.055248 best dqsien dly found for B0: ( 0, 13, 10)
4677 10:03:42.058764 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4678 10:03:42.061525 Total UI for P1: 0, mck2ui 16
4679 10:03:42.064891 best dqsien dly found for B1: ( 0, 13, 12)
4680 10:03:42.068225 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4681 10:03:42.075208 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4682 10:03:42.075638
4683 10:03:42.078423 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4684 10:03:42.081516 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4685 10:03:42.084600 [Gating] SW calibration Done
4686 10:03:42.085013 ==
4687 10:03:42.088015 Dram Type= 6, Freq= 0, CH_1, rank 1
4688 10:03:42.091110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4689 10:03:42.091529 ==
4690 10:03:42.094656 RX Vref Scan: 0
4691 10:03:42.095071
4692 10:03:42.095400 RX Vref 0 -> 0, step: 1
4693 10:03:42.095708
4694 10:03:42.097981 RX Delay -230 -> 252, step: 16
4695 10:03:42.101092 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4696 10:03:42.107639 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4697 10:03:42.111600 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4698 10:03:42.114459 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4699 10:03:42.117823 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4700 10:03:42.124902 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4701 10:03:42.127909 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4702 10:03:42.130854 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4703 10:03:42.134195 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4704 10:03:42.137763 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4705 10:03:42.144527 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4706 10:03:42.147826 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4707 10:03:42.150963 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4708 10:03:42.154549 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4709 10:03:42.161068 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4710 10:03:42.164108 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4711 10:03:42.164675 ==
4712 10:03:42.167226 Dram Type= 6, Freq= 0, CH_1, rank 1
4713 10:03:42.170655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4714 10:03:42.171205 ==
4715 10:03:42.173615 DQS Delay:
4716 10:03:42.174159 DQS0 = 0, DQS1 = 0
4717 10:03:42.176904 DQM Delay:
4718 10:03:42.177516 DQM0 = 41, DQM1 = 38
4719 10:03:42.177902 DQ Delay:
4720 10:03:42.180177 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4721 10:03:42.183549 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =33
4722 10:03:42.186673 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4723 10:03:42.190149 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4724 10:03:42.190652
4725 10:03:42.193227
4726 10:03:42.193639 ==
4727 10:03:42.197222 Dram Type= 6, Freq= 0, CH_1, rank 1
4728 10:03:42.200169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4729 10:03:42.200645 ==
4730 10:03:42.201289
4731 10:03:42.201742
4732 10:03:42.203091 TX Vref Scan disable
4733 10:03:42.203523 == TX Byte 0 ==
4734 10:03:42.209826 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4735 10:03:42.213585 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4736 10:03:42.214004 == TX Byte 1 ==
4737 10:03:42.220064 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4738 10:03:42.222989 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4739 10:03:42.223404 ==
4740 10:03:42.226206 Dram Type= 6, Freq= 0, CH_1, rank 1
4741 10:03:42.229582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4742 10:03:42.230202 ==
4743 10:03:42.230601
4744 10:03:42.230922
4745 10:03:42.232757 TX Vref Scan disable
4746 10:03:42.236140 == TX Byte 0 ==
4747 10:03:42.239805 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4748 10:03:42.242778 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4749 10:03:42.246063 == TX Byte 1 ==
4750 10:03:42.249590 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4751 10:03:42.253231 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4752 10:03:42.256393
4753 10:03:42.256829 [DATLAT]
4754 10:03:42.257177 Freq=600, CH1 RK1
4755 10:03:42.257528
4756 10:03:42.260078 DATLAT Default: 0x9
4757 10:03:42.260581 0, 0xFFFF, sum = 0
4758 10:03:42.263040 1, 0xFFFF, sum = 0
4759 10:03:42.263551 2, 0xFFFF, sum = 0
4760 10:03:42.266248 3, 0xFFFF, sum = 0
4761 10:03:42.266728 4, 0xFFFF, sum = 0
4762 10:03:42.269544 5, 0xFFFF, sum = 0
4763 10:03:42.272710 6, 0xFFFF, sum = 0
4764 10:03:42.273281 7, 0xFFFF, sum = 0
4765 10:03:42.276207 8, 0x0, sum = 1
4766 10:03:42.276720 9, 0x0, sum = 2
4767 10:03:42.277059 10, 0x0, sum = 3
4768 10:03:42.279541 11, 0x0, sum = 4
4769 10:03:42.279961 best_step = 9
4770 10:03:42.280297
4771 10:03:42.280608 ==
4772 10:03:42.282712 Dram Type= 6, Freq= 0, CH_1, rank 1
4773 10:03:42.288948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4774 10:03:42.289491 ==
4775 10:03:42.289831 RX Vref Scan: 0
4776 10:03:42.290144
4777 10:03:42.292302 RX Vref 0 -> 0, step: 1
4778 10:03:42.292717
4779 10:03:42.296044 RX Delay -179 -> 252, step: 8
4780 10:03:42.298815 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4781 10:03:42.305630 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4782 10:03:42.308511 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4783 10:03:42.311956 iDelay=205, Bit 3, Center 36 (-123 ~ 196) 320
4784 10:03:42.315436 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4785 10:03:42.322231 iDelay=205, Bit 5, Center 44 (-115 ~ 204) 320
4786 10:03:42.325664 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4787 10:03:42.329189 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4788 10:03:42.332164 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4789 10:03:42.339180 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4790 10:03:42.341927 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4791 10:03:42.345217 iDelay=205, Bit 11, Center 28 (-131 ~ 188) 320
4792 10:03:42.348935 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4793 10:03:42.355145 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4794 10:03:42.358296 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4795 10:03:42.362295 iDelay=205, Bit 15, Center 44 (-115 ~ 204) 320
4796 10:03:42.362859 ==
4797 10:03:42.364874 Dram Type= 6, Freq= 0, CH_1, rank 1
4798 10:03:42.368103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4799 10:03:42.368559 ==
4800 10:03:42.371565 DQS Delay:
4801 10:03:42.372108 DQS0 = 0, DQS1 = 0
4802 10:03:42.375423 DQM Delay:
4803 10:03:42.375969 DQM0 = 37, DQM1 = 35
4804 10:03:42.377852 DQ Delay:
4805 10:03:42.378350 DQ0 =40, DQ1 =36, DQ2 =28, DQ3 =36
4806 10:03:42.381588 DQ4 =36, DQ5 =44, DQ6 =44, DQ7 =32
4807 10:03:42.384803 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28
4808 10:03:42.388516 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =44
4809 10:03:42.389067
4810 10:03:42.391630
4811 10:03:42.397865 [DQSOSCAuto] RK1, (LSB)MR18= 0x3054, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 400 ps
4812 10:03:42.401691 CH1 RK1: MR19=808, MR18=3054
4813 10:03:42.408344 CH1_RK1: MR19=0x808, MR18=0x3054, DQSOSC=393, MR23=63, INC=169, DEC=113
4814 10:03:42.410963 [RxdqsGatingPostProcess] freq 600
4815 10:03:42.414956 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4816 10:03:42.418053 Pre-setting of DQS Precalculation
4817 10:03:42.424804 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4818 10:03:42.430621 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4819 10:03:42.437855 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4820 10:03:42.438447
4821 10:03:42.438817
4822 10:03:42.441320 [Calibration Summary] 1200 Mbps
4823 10:03:42.441878 CH 0, Rank 0
4824 10:03:42.444777 SW Impedance : PASS
4825 10:03:42.447565 DUTY Scan : NO K
4826 10:03:42.448026 ZQ Calibration : PASS
4827 10:03:42.451158 Jitter Meter : NO K
4828 10:03:42.454405 CBT Training : PASS
4829 10:03:42.454950 Write leveling : PASS
4830 10:03:42.457309 RX DQS gating : PASS
4831 10:03:42.460696 RX DQ/DQS(RDDQC) : PASS
4832 10:03:42.461242 TX DQ/DQS : PASS
4833 10:03:42.464284 RX DATLAT : PASS
4834 10:03:42.464833 RX DQ/DQS(Engine): PASS
4835 10:03:42.467426 TX OE : NO K
4836 10:03:42.467905 All Pass.
4837 10:03:42.468276
4838 10:03:42.470871 CH 0, Rank 1
4839 10:03:42.471419 SW Impedance : PASS
4840 10:03:42.474152 DUTY Scan : NO K
4841 10:03:42.477290 ZQ Calibration : PASS
4842 10:03:42.477839 Jitter Meter : NO K
4843 10:03:42.480470 CBT Training : PASS
4844 10:03:42.483310 Write leveling : PASS
4845 10:03:42.483766 RX DQS gating : PASS
4846 10:03:42.486949 RX DQ/DQS(RDDQC) : PASS
4847 10:03:42.490791 TX DQ/DQS : PASS
4848 10:03:42.491255 RX DATLAT : PASS
4849 10:03:42.493323 RX DQ/DQS(Engine): PASS
4850 10:03:42.496579 TX OE : NO K
4851 10:03:42.497040 All Pass.
4852 10:03:42.497398
4853 10:03:42.497733 CH 1, Rank 0
4854 10:03:42.500252 SW Impedance : PASS
4855 10:03:42.503705 DUTY Scan : NO K
4856 10:03:42.504250 ZQ Calibration : PASS
4857 10:03:42.507175 Jitter Meter : NO K
4858 10:03:42.510367 CBT Training : PASS
4859 10:03:42.510910 Write leveling : PASS
4860 10:03:42.513488 RX DQS gating : PASS
4861 10:03:42.516770 RX DQ/DQS(RDDQC) : PASS
4862 10:03:42.517333 TX DQ/DQS : PASS
4863 10:03:42.519977 RX DATLAT : PASS
4864 10:03:42.522747 RX DQ/DQS(Engine): PASS
4865 10:03:42.523209 TX OE : NO K
4866 10:03:42.526359 All Pass.
4867 10:03:42.526848
4868 10:03:42.527222 CH 1, Rank 1
4869 10:03:42.529614 SW Impedance : PASS
4870 10:03:42.530070 DUTY Scan : NO K
4871 10:03:42.533229 ZQ Calibration : PASS
4872 10:03:42.536462 Jitter Meter : NO K
4873 10:03:42.536925 CBT Training : PASS
4874 10:03:42.539452 Write leveling : PASS
4875 10:03:42.542751 RX DQS gating : PASS
4876 10:03:42.543173 RX DQ/DQS(RDDQC) : PASS
4877 10:03:42.546120 TX DQ/DQS : PASS
4878 10:03:42.549195 RX DATLAT : PASS
4879 10:03:42.549689 RX DQ/DQS(Engine): PASS
4880 10:03:42.552466 TX OE : NO K
4881 10:03:42.552882 All Pass.
4882 10:03:42.553279
4883 10:03:42.555874 DramC Write-DBI off
4884 10:03:42.559383 PER_BANK_REFRESH: Hybrid Mode
4885 10:03:42.559902 TX_TRACKING: ON
4886 10:03:42.568961 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4887 10:03:42.572351 [FAST_K] Save calibration result to emmc
4888 10:03:42.575758 dramc_set_vcore_voltage set vcore to 662500
4889 10:03:42.578588 Read voltage for 933, 3
4890 10:03:42.579003 Vio18 = 0
4891 10:03:42.579336 Vcore = 662500
4892 10:03:42.582089 Vdram = 0
4893 10:03:42.582633 Vddq = 0
4894 10:03:42.582975 Vmddr = 0
4895 10:03:42.589084 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4896 10:03:42.592730 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4897 10:03:42.595419 MEM_TYPE=3, freq_sel=17
4898 10:03:42.599051 sv_algorithm_assistance_LP4_1600
4899 10:03:42.602344 ============ PULL DRAM RESETB DOWN ============
4900 10:03:42.605595 ========== PULL DRAM RESETB DOWN end =========
4901 10:03:42.611911 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4902 10:03:42.615490 ===================================
4903 10:03:42.618766 LPDDR4 DRAM CONFIGURATION
4904 10:03:42.622195 ===================================
4905 10:03:42.622748 EX_ROW_EN[0] = 0x0
4906 10:03:42.625011 EX_ROW_EN[1] = 0x0
4907 10:03:42.625427 LP4Y_EN = 0x0
4908 10:03:42.628303 WORK_FSP = 0x0
4909 10:03:42.628804 WL = 0x3
4910 10:03:42.631648 RL = 0x3
4911 10:03:42.632153 BL = 0x2
4912 10:03:42.634884 RPST = 0x0
4913 10:03:42.635301 RD_PRE = 0x0
4914 10:03:42.638410 WR_PRE = 0x1
4915 10:03:42.638910 WR_PST = 0x0
4916 10:03:42.642174 DBI_WR = 0x0
4917 10:03:42.644966 DBI_RD = 0x0
4918 10:03:42.645518 OTF = 0x1
4919 10:03:42.648161 ===================================
4920 10:03:42.651508 ===================================
4921 10:03:42.651953 ANA top config
4922 10:03:42.654676 ===================================
4923 10:03:42.658067 DLL_ASYNC_EN = 0
4924 10:03:42.660845 ALL_SLAVE_EN = 1
4925 10:03:42.664773 NEW_RANK_MODE = 1
4926 10:03:42.667848 DLL_IDLE_MODE = 1
4927 10:03:42.668313 LP45_APHY_COMB_EN = 1
4928 10:03:42.671290 TX_ODT_DIS = 1
4929 10:03:42.674650 NEW_8X_MODE = 1
4930 10:03:42.677926 ===================================
4931 10:03:42.681045 ===================================
4932 10:03:42.684692 data_rate = 1866
4933 10:03:42.687526 CKR = 1
4934 10:03:42.690845 DQ_P2S_RATIO = 8
4935 10:03:42.693950 ===================================
4936 10:03:42.694448 CA_P2S_RATIO = 8
4937 10:03:42.697411 DQ_CA_OPEN = 0
4938 10:03:42.700785 DQ_SEMI_OPEN = 0
4939 10:03:42.704028 CA_SEMI_OPEN = 0
4940 10:03:42.707465 CA_FULL_RATE = 0
4941 10:03:42.710539 DQ_CKDIV4_EN = 1
4942 10:03:42.711000 CA_CKDIV4_EN = 1
4943 10:03:42.713870 CA_PREDIV_EN = 0
4944 10:03:42.717663 PH8_DLY = 0
4945 10:03:42.720389 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4946 10:03:42.723506 DQ_AAMCK_DIV = 4
4947 10:03:42.726774 CA_AAMCK_DIV = 4
4948 10:03:42.727232 CA_ADMCK_DIV = 4
4949 10:03:42.730050 DQ_TRACK_CA_EN = 0
4950 10:03:42.733861 CA_PICK = 933
4951 10:03:42.736908 CA_MCKIO = 933
4952 10:03:42.740690 MCKIO_SEMI = 0
4953 10:03:42.743182 PLL_FREQ = 3732
4954 10:03:42.747054 DQ_UI_PI_RATIO = 32
4955 10:03:42.750045 CA_UI_PI_RATIO = 0
4956 10:03:42.753564 ===================================
4957 10:03:42.754114 ===================================
4958 10:03:42.756930 memory_type:LPDDR4
4959 10:03:42.760092 GP_NUM : 10
4960 10:03:42.760565 SRAM_EN : 1
4961 10:03:42.763087 MD32_EN : 0
4962 10:03:42.766448 ===================================
4963 10:03:42.769948 [ANA_INIT] >>>>>>>>>>>>>>
4964 10:03:42.772833 <<<<<< [CONFIGURE PHASE]: ANA_TX
4965 10:03:42.775994 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4966 10:03:42.779693 ===================================
4967 10:03:42.783784 data_rate = 1866,PCW = 0X8f00
4968 10:03:42.786088 ===================================
4969 10:03:42.789403 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4970 10:03:42.792856 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4971 10:03:42.799488 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4972 10:03:42.802645 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4973 10:03:42.806111 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4974 10:03:42.809369 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4975 10:03:42.812868 [ANA_INIT] flow start
4976 10:03:42.816229 [ANA_INIT] PLL >>>>>>>>
4977 10:03:42.816774 [ANA_INIT] PLL <<<<<<<<
4978 10:03:42.818880 [ANA_INIT] MIDPI >>>>>>>>
4979 10:03:42.822433 [ANA_INIT] MIDPI <<<<<<<<
4980 10:03:42.825680 [ANA_INIT] DLL >>>>>>>>
4981 10:03:42.826143 [ANA_INIT] flow end
4982 10:03:42.829613 ============ LP4 DIFF to SE enter ============
4983 10:03:42.835546 ============ LP4 DIFF to SE exit ============
4984 10:03:42.836100 [ANA_INIT] <<<<<<<<<<<<<
4985 10:03:42.838952 [Flow] Enable top DCM control >>>>>
4986 10:03:42.842216 [Flow] Enable top DCM control <<<<<
4987 10:03:42.845608 Enable DLL master slave shuffle
4988 10:03:42.852399 ==============================================================
4989 10:03:42.852941 Gating Mode config
4990 10:03:42.858934 ==============================================================
4991 10:03:42.861870 Config description:
4992 10:03:42.872035 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4993 10:03:42.878470 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4994 10:03:42.881976 SELPH_MODE 0: By rank 1: By Phase
4995 10:03:42.888046 ==============================================================
4996 10:03:42.891537 GAT_TRACK_EN = 1
4997 10:03:42.895100 RX_GATING_MODE = 2
4998 10:03:42.897976 RX_GATING_TRACK_MODE = 2
4999 10:03:42.901490 SELPH_MODE = 1
5000 10:03:42.902036 PICG_EARLY_EN = 1
5001 10:03:42.904453 VALID_LAT_VALUE = 1
5002 10:03:42.911250 ==============================================================
5003 10:03:42.914191 Enter into Gating configuration >>>>
5004 10:03:42.917883 Exit from Gating configuration <<<<
5005 10:03:42.921252 Enter into DVFS_PRE_config >>>>>
5006 10:03:42.930684 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5007 10:03:42.934364 Exit from DVFS_PRE_config <<<<<
5008 10:03:42.937248 Enter into PICG configuration >>>>
5009 10:03:42.940729 Exit from PICG configuration <<<<
5010 10:03:42.944266 [RX_INPUT] configuration >>>>>
5011 10:03:42.946945 [RX_INPUT] configuration <<<<<
5012 10:03:42.953919 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5013 10:03:42.957394 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5014 10:03:42.964275 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5015 10:03:42.970697 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5016 10:03:42.977237 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5017 10:03:42.983461 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5018 10:03:42.986800 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5019 10:03:42.990434 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5020 10:03:42.993270 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5021 10:03:43.000066 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5022 10:03:43.003721 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5023 10:03:43.007051 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5024 10:03:43.010018 ===================================
5025 10:03:43.013262 LPDDR4 DRAM CONFIGURATION
5026 10:03:43.016636 ===================================
5027 10:03:43.020128 EX_ROW_EN[0] = 0x0
5028 10:03:43.020679 EX_ROW_EN[1] = 0x0
5029 10:03:43.023165 LP4Y_EN = 0x0
5030 10:03:43.023712 WORK_FSP = 0x0
5031 10:03:43.026367 WL = 0x3
5032 10:03:43.026829 RL = 0x3
5033 10:03:43.029653 BL = 0x2
5034 10:03:43.030109 RPST = 0x0
5035 10:03:43.033068 RD_PRE = 0x0
5036 10:03:43.033619 WR_PRE = 0x1
5037 10:03:43.036143 WR_PST = 0x0
5038 10:03:43.036603 DBI_WR = 0x0
5039 10:03:43.039574 DBI_RD = 0x0
5040 10:03:43.040063 OTF = 0x1
5041 10:03:43.042747 ===================================
5042 10:03:43.046228 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5043 10:03:43.052948 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5044 10:03:43.056118 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5045 10:03:43.059194 ===================================
5046 10:03:43.062842 LPDDR4 DRAM CONFIGURATION
5047 10:03:43.065706 ===================================
5048 10:03:43.069104 EX_ROW_EN[0] = 0x10
5049 10:03:43.069564 EX_ROW_EN[1] = 0x0
5050 10:03:43.072152 LP4Y_EN = 0x0
5051 10:03:43.072567 WORK_FSP = 0x0
5052 10:03:43.075727 WL = 0x3
5053 10:03:43.076229 RL = 0x3
5054 10:03:43.079162 BL = 0x2
5055 10:03:43.079671 RPST = 0x0
5056 10:03:43.082411 RD_PRE = 0x0
5057 10:03:43.082918 WR_PRE = 0x1
5058 10:03:43.085663 WR_PST = 0x0
5059 10:03:43.086163 DBI_WR = 0x0
5060 10:03:43.088941 DBI_RD = 0x0
5061 10:03:43.089441 OTF = 0x1
5062 10:03:43.091955 ===================================
5063 10:03:43.098857 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5064 10:03:43.103916 nWR fixed to 30
5065 10:03:43.106986 [ModeRegInit_LP4] CH0 RK0
5066 10:03:43.107406 [ModeRegInit_LP4] CH0 RK1
5067 10:03:43.110438 [ModeRegInit_LP4] CH1 RK0
5068 10:03:43.114173 [ModeRegInit_LP4] CH1 RK1
5069 10:03:43.114721 match AC timing 9
5070 10:03:43.120066 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5071 10:03:43.123387 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5072 10:03:43.126416 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5073 10:03:43.133370 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5074 10:03:43.136749 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5075 10:03:43.137261 ==
5076 10:03:43.140446 Dram Type= 6, Freq= 0, CH_0, rank 0
5077 10:03:43.143016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5078 10:03:43.146125 ==
5079 10:03:43.149719 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5080 10:03:43.156197 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5081 10:03:43.159265 [CA 0] Center 37 (7~68) winsize 62
5082 10:03:43.163106 [CA 1] Center 37 (7~68) winsize 62
5083 10:03:43.165730 [CA 2] Center 34 (4~64) winsize 61
5084 10:03:43.169121 [CA 3] Center 34 (4~65) winsize 62
5085 10:03:43.173127 [CA 4] Center 33 (2~64) winsize 63
5086 10:03:43.175979 [CA 5] Center 32 (2~63) winsize 62
5087 10:03:43.176508
5088 10:03:43.178944 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5089 10:03:43.179455
5090 10:03:43.182184 [CATrainingPosCal] consider 1 rank data
5091 10:03:43.185706 u2DelayCellTimex100 = 270/100 ps
5092 10:03:43.189399 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5093 10:03:43.192178 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5094 10:03:43.199006 CA2 delay=34 (4~64),Diff = 2 PI (12 cell)
5095 10:03:43.202725 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5096 10:03:43.205700 CA4 delay=33 (2~64),Diff = 1 PI (6 cell)
5097 10:03:43.209053 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5098 10:03:43.209561
5099 10:03:43.212077 CA PerBit enable=1, Macro0, CA PI delay=32
5100 10:03:43.212585
5101 10:03:43.215524 [CBTSetCACLKResult] CA Dly = 32
5102 10:03:43.216029 CS Dly: 6 (0~37)
5103 10:03:43.218734 ==
5104 10:03:43.219152 Dram Type= 6, Freq= 0, CH_0, rank 1
5105 10:03:43.225626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5106 10:03:43.226196 ==
5107 10:03:43.228898 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5108 10:03:43.235184 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5109 10:03:43.238609 [CA 0] Center 38 (8~68) winsize 61
5110 10:03:43.242011 [CA 1] Center 37 (7~68) winsize 62
5111 10:03:43.245893 [CA 2] Center 34 (4~65) winsize 62
5112 10:03:43.248637 [CA 3] Center 34 (4~65) winsize 62
5113 10:03:43.251794 [CA 4] Center 33 (3~64) winsize 62
5114 10:03:43.255150 [CA 5] Center 32 (2~63) winsize 62
5115 10:03:43.255654
5116 10:03:43.258550 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5117 10:03:43.258964
5118 10:03:43.261946 [CATrainingPosCal] consider 2 rank data
5119 10:03:43.265331 u2DelayCellTimex100 = 270/100 ps
5120 10:03:43.268205 CA0 delay=38 (8~68),Diff = 6 PI (37 cell)
5121 10:03:43.275138 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5122 10:03:43.278163 CA2 delay=34 (4~64),Diff = 2 PI (12 cell)
5123 10:03:43.281906 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5124 10:03:43.285336 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5125 10:03:43.288304 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5126 10:03:43.288817
5127 10:03:43.291314 CA PerBit enable=1, Macro0, CA PI delay=32
5128 10:03:43.291732
5129 10:03:43.294493 [CBTSetCACLKResult] CA Dly = 32
5130 10:03:43.298057 CS Dly: 7 (0~39)
5131 10:03:43.298600
5132 10:03:43.301348 ----->DramcWriteLeveling(PI) begin...
5133 10:03:43.301771 ==
5134 10:03:43.304691 Dram Type= 6, Freq= 0, CH_0, rank 0
5135 10:03:43.308595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5136 10:03:43.309155 ==
5137 10:03:43.311043 Write leveling (Byte 0): 33 => 33
5138 10:03:43.314422 Write leveling (Byte 1): 25 => 25
5139 10:03:43.317571 DramcWriteLeveling(PI) end<-----
5140 10:03:43.317985
5141 10:03:43.318376 ==
5142 10:03:43.321203 Dram Type= 6, Freq= 0, CH_0, rank 0
5143 10:03:43.324634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5144 10:03:43.325145 ==
5145 10:03:43.327928 [Gating] SW mode calibration
5146 10:03:43.334038 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5147 10:03:43.340856 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5148 10:03:43.344096 0 14 0 | B1->B0 | 2424 3434 | 1 1 | (1 1) (1 1)
5149 10:03:43.350832 0 14 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
5150 10:03:43.354224 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5151 10:03:43.357145 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5152 10:03:43.364424 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5153 10:03:43.366860 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5154 10:03:43.370433 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
5155 10:03:43.377135 0 14 28 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
5156 10:03:43.380589 0 15 0 | B1->B0 | 2f2f 2424 | 1 0 | (1 1) (1 0)
5157 10:03:43.383650 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5158 10:03:43.390412 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5159 10:03:43.393850 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5160 10:03:43.397187 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5161 10:03:43.403995 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5162 10:03:43.406786 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5163 10:03:43.410122 0 15 28 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (0 0)
5164 10:03:43.416729 1 0 0 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
5165 10:03:43.419875 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5166 10:03:43.422943 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5167 10:03:43.429850 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5168 10:03:43.433228 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5169 10:03:43.436277 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5170 10:03:43.443040 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5171 10:03:43.446543 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5172 10:03:43.449624 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5173 10:03:43.455956 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5174 10:03:43.459392 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5175 10:03:43.462979 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5176 10:03:43.469150 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5177 10:03:43.472635 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5178 10:03:43.476002 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5179 10:03:43.482440 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5180 10:03:43.486423 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5181 10:03:43.489277 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5182 10:03:43.495354 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5183 10:03:43.498958 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 10:03:43.502012 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 10:03:43.508947 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 10:03:43.512255 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5187 10:03:43.515428 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5188 10:03:43.521820 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5189 10:03:43.522415 Total UI for P1: 0, mck2ui 16
5190 10:03:43.528148 best dqsien dly found for B0: ( 1, 2, 26)
5191 10:03:43.531910 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5192 10:03:43.535229 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5193 10:03:43.538483 Total UI for P1: 0, mck2ui 16
5194 10:03:43.541704 best dqsien dly found for B1: ( 1, 3, 2)
5195 10:03:43.544531 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5196 10:03:43.548109 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5197 10:03:43.548711
5198 10:03:43.554544 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5199 10:03:43.557908 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5200 10:03:43.561345 [Gating] SW calibration Done
5201 10:03:43.561891 ==
5202 10:03:43.564880 Dram Type= 6, Freq= 0, CH_0, rank 0
5203 10:03:43.567735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5204 10:03:43.568194 ==
5205 10:03:43.568558 RX Vref Scan: 0
5206 10:03:43.568890
5207 10:03:43.570849 RX Vref 0 -> 0, step: 1
5208 10:03:43.571304
5209 10:03:43.574464 RX Delay -80 -> 252, step: 8
5210 10:03:43.577479 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5211 10:03:43.580875 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5212 10:03:43.587311 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5213 10:03:43.591165 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5214 10:03:43.594115 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5215 10:03:43.597595 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5216 10:03:43.600453 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5217 10:03:43.604013 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5218 10:03:43.610325 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5219 10:03:43.613857 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5220 10:03:43.617399 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5221 10:03:43.620702 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5222 10:03:43.623784 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5223 10:03:43.630740 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5224 10:03:43.633682 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5225 10:03:43.636642 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5226 10:03:43.637102 ==
5227 10:03:43.640253 Dram Type= 6, Freq= 0, CH_0, rank 0
5228 10:03:43.643738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5229 10:03:43.644287 ==
5230 10:03:43.646849 DQS Delay:
5231 10:03:43.647393 DQS0 = 0, DQS1 = 0
5232 10:03:43.650429 DQM Delay:
5233 10:03:43.650975 DQM0 = 101, DQM1 = 88
5234 10:03:43.651337 DQ Delay:
5235 10:03:43.653592 DQ0 =103, DQ1 =103, DQ2 =95, DQ3 =95
5236 10:03:43.657005 DQ4 =103, DQ5 =87, DQ6 =111, DQ7 =111
5237 10:03:43.660197 DQ8 =83, DQ9 =75, DQ10 =87, DQ11 =83
5238 10:03:43.663723 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5239 10:03:43.666517
5240 10:03:43.667064
5241 10:03:43.667453 ==
5242 10:03:43.670217 Dram Type= 6, Freq= 0, CH_0, rank 0
5243 10:03:43.673395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5244 10:03:43.673964 ==
5245 10:03:43.674367
5246 10:03:43.674705
5247 10:03:43.677095 TX Vref Scan disable
5248 10:03:43.677639 == TX Byte 0 ==
5249 10:03:43.682728 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5250 10:03:43.686485 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5251 10:03:43.687030 == TX Byte 1 ==
5252 10:03:43.692932 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5253 10:03:43.696002 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5254 10:03:43.696457 ==
5255 10:03:43.699748 Dram Type= 6, Freq= 0, CH_0, rank 0
5256 10:03:43.702766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5257 10:03:43.703225 ==
5258 10:03:43.703585
5259 10:03:43.703917
5260 10:03:43.706821 TX Vref Scan disable
5261 10:03:43.709686 == TX Byte 0 ==
5262 10:03:43.713133 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5263 10:03:43.716449 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5264 10:03:43.718971 == TX Byte 1 ==
5265 10:03:43.722525 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5266 10:03:43.729141 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5267 10:03:43.729690
5268 10:03:43.730052 [DATLAT]
5269 10:03:43.730436 Freq=933, CH0 RK0
5270 10:03:43.730767
5271 10:03:43.732282 DATLAT Default: 0xd
5272 10:03:43.732733 0, 0xFFFF, sum = 0
5273 10:03:43.735660 1, 0xFFFF, sum = 0
5274 10:03:43.736212 2, 0xFFFF, sum = 0
5275 10:03:43.738938 3, 0xFFFF, sum = 0
5276 10:03:43.742640 4, 0xFFFF, sum = 0
5277 10:03:43.743192 5, 0xFFFF, sum = 0
5278 10:03:43.745547 6, 0xFFFF, sum = 0
5279 10:03:43.746094 7, 0xFFFF, sum = 0
5280 10:03:43.749163 8, 0xFFFF, sum = 0
5281 10:03:43.749715 9, 0xFFFF, sum = 0
5282 10:03:43.751949 10, 0x0, sum = 1
5283 10:03:43.752433 11, 0x0, sum = 2
5284 10:03:43.755666 12, 0x0, sum = 3
5285 10:03:43.756223 13, 0x0, sum = 4
5286 10:03:43.756592 best_step = 11
5287 10:03:43.759272
5288 10:03:43.759818 ==
5289 10:03:43.762168 Dram Type= 6, Freq= 0, CH_0, rank 0
5290 10:03:43.765492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5291 10:03:43.766041 ==
5292 10:03:43.766446 RX Vref Scan: 1
5293 10:03:43.766793
5294 10:03:43.768563 RX Vref 0 -> 0, step: 1
5295 10:03:43.769106
5296 10:03:43.772261 RX Delay -61 -> 252, step: 4
5297 10:03:43.772713
5298 10:03:43.775099 Set Vref, RX VrefLevel [Byte0]: 54
5299 10:03:43.778671 [Byte1]: 58
5300 10:03:43.781365
5301 10:03:43.781819 Final RX Vref Byte 0 = 54 to rank0
5302 10:03:43.785311 Final RX Vref Byte 1 = 58 to rank0
5303 10:03:43.788385 Final RX Vref Byte 0 = 54 to rank1
5304 10:03:43.792066 Final RX Vref Byte 1 = 58 to rank1==
5305 10:03:43.794925 Dram Type= 6, Freq= 0, CH_0, rank 0
5306 10:03:43.801304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5307 10:03:43.801762 ==
5308 10:03:43.802119 DQS Delay:
5309 10:03:43.802524 DQS0 = 0, DQS1 = 0
5310 10:03:43.804852 DQM Delay:
5311 10:03:43.805395 DQM0 = 98, DQM1 = 88
5312 10:03:43.808247 DQ Delay:
5313 10:03:43.811414 DQ0 =100, DQ1 =98, DQ2 =92, DQ3 =96
5314 10:03:43.814981 DQ4 =100, DQ5 =90, DQ6 =108, DQ7 =106
5315 10:03:43.818407 DQ8 =80, DQ9 =76, DQ10 =88, DQ11 =84
5316 10:03:43.821508 DQ12 =96, DQ13 =94, DQ14 =98, DQ15 =94
5317 10:03:43.822055
5318 10:03:43.822486
5319 10:03:43.828040 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e18, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 412 ps
5320 10:03:43.830973 CH0 RK0: MR19=505, MR18=1E18
5321 10:03:43.837589 CH0_RK0: MR19=0x505, MR18=0x1E18, DQSOSC=412, MR23=63, INC=63, DEC=42
5322 10:03:43.838124
5323 10:03:43.841182 ----->DramcWriteLeveling(PI) begin...
5324 10:03:43.841733 ==
5325 10:03:43.844819 Dram Type= 6, Freq= 0, CH_0, rank 1
5326 10:03:43.847646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5327 10:03:43.848196 ==
5328 10:03:43.851714 Write leveling (Byte 0): 34 => 34
5329 10:03:43.854571 Write leveling (Byte 1): 30 => 30
5330 10:03:43.857850 DramcWriteLeveling(PI) end<-----
5331 10:03:43.858434
5332 10:03:43.858798 ==
5333 10:03:43.861230 Dram Type= 6, Freq= 0, CH_0, rank 1
5334 10:03:43.864211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5335 10:03:43.867570 ==
5336 10:03:43.868117 [Gating] SW mode calibration
5337 10:03:43.877683 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5338 10:03:43.880760 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5339 10:03:43.884301 0 14 0 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
5340 10:03:43.890649 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5341 10:03:43.894087 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5342 10:03:43.896971 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5343 10:03:43.903429 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5344 10:03:43.907490 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5345 10:03:43.910380 0 14 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5346 10:03:43.917710 0 14 28 | B1->B0 | 3434 2828 | 0 0 | (0 0) (1 0)
5347 10:03:43.920603 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
5348 10:03:43.923722 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5349 10:03:43.929856 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5350 10:03:43.933456 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5351 10:03:43.937281 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5352 10:03:43.943587 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5353 10:03:43.946548 0 15 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5354 10:03:43.949804 0 15 28 | B1->B0 | 2d2c 4545 | 1 0 | (0 0) (0 0)
5355 10:03:43.956713 1 0 0 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
5356 10:03:43.960339 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5357 10:03:43.963402 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5358 10:03:43.970009 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5359 10:03:43.973133 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5360 10:03:43.976188 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5361 10:03:43.982930 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5362 10:03:43.986136 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5363 10:03:43.989237 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5364 10:03:43.996150 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5365 10:03:43.999472 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5366 10:03:44.002640 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5367 10:03:44.009456 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5368 10:03:44.013345 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5369 10:03:44.016240 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5370 10:03:44.022075 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5371 10:03:44.025484 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5372 10:03:44.028700 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5373 10:03:44.035760 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 10:03:44.038724 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 10:03:44.042368 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 10:03:44.049042 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 10:03:44.051988 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5378 10:03:44.055605 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5379 10:03:44.058659 Total UI for P1: 0, mck2ui 16
5380 10:03:44.061939 best dqsien dly found for B0: ( 1, 2, 24)
5381 10:03:44.068665 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5382 10:03:44.072130 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5383 10:03:44.075356 Total UI for P1: 0, mck2ui 16
5384 10:03:44.077965 best dqsien dly found for B1: ( 1, 3, 0)
5385 10:03:44.081704 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5386 10:03:44.084933 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5387 10:03:44.085433
5388 10:03:44.088231 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5389 10:03:44.095063 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5390 10:03:44.095567 [Gating] SW calibration Done
5391 10:03:44.095895 ==
5392 10:03:44.097903 Dram Type= 6, Freq= 0, CH_0, rank 1
5393 10:03:44.104259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5394 10:03:44.104670 ==
5395 10:03:44.104994 RX Vref Scan: 0
5396 10:03:44.105299
5397 10:03:44.108375 RX Vref 0 -> 0, step: 1
5398 10:03:44.108872
5399 10:03:44.111659 RX Delay -80 -> 252, step: 8
5400 10:03:44.114809 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5401 10:03:44.117895 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5402 10:03:44.121074 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5403 10:03:44.124555 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5404 10:03:44.130908 iDelay=200, Bit 4, Center 103 (8 ~ 199) 192
5405 10:03:44.134530 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5406 10:03:44.137766 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5407 10:03:44.141073 iDelay=200, Bit 7, Center 107 (16 ~ 199) 184
5408 10:03:44.144332 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5409 10:03:44.147278 iDelay=200, Bit 9, Center 79 (-8 ~ 167) 176
5410 10:03:44.154052 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5411 10:03:44.157713 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5412 10:03:44.160386 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5413 10:03:44.164494 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5414 10:03:44.167389 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5415 10:03:44.173797 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5416 10:03:44.174386 ==
5417 10:03:44.177155 Dram Type= 6, Freq= 0, CH_0, rank 1
5418 10:03:44.180503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5419 10:03:44.181069 ==
5420 10:03:44.181435 DQS Delay:
5421 10:03:44.183994 DQS0 = 0, DQS1 = 0
5422 10:03:44.184542 DQM Delay:
5423 10:03:44.187287 DQM0 = 98, DQM1 = 90
5424 10:03:44.187827 DQ Delay:
5425 10:03:44.189972 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =95
5426 10:03:44.193821 DQ4 =103, DQ5 =87, DQ6 =103, DQ7 =107
5427 10:03:44.197215 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =83
5428 10:03:44.200304 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =95
5429 10:03:44.200854
5430 10:03:44.201242
5431 10:03:44.201573 ==
5432 10:03:44.203745 Dram Type= 6, Freq= 0, CH_0, rank 1
5433 10:03:44.209876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5434 10:03:44.210526 ==
5435 10:03:44.210917
5436 10:03:44.211260
5437 10:03:44.211658 TX Vref Scan disable
5438 10:03:44.213152 == TX Byte 0 ==
5439 10:03:44.216684 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5440 10:03:44.222984 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5441 10:03:44.223680 == TX Byte 1 ==
5442 10:03:44.225925 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5443 10:03:44.233112 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5444 10:03:44.233660 ==
5445 10:03:44.236040 Dram Type= 6, Freq= 0, CH_0, rank 1
5446 10:03:44.239284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5447 10:03:44.239741 ==
5448 10:03:44.240102
5449 10:03:44.240437
5450 10:03:44.243166 TX Vref Scan disable
5451 10:03:44.246713 == TX Byte 0 ==
5452 10:03:44.249489 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5453 10:03:44.252838 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5454 10:03:44.255961 == TX Byte 1 ==
5455 10:03:44.259578 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5456 10:03:44.262719 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5457 10:03:44.263266
5458 10:03:44.263786 [DATLAT]
5459 10:03:44.266061 Freq=933, CH0 RK1
5460 10:03:44.266654
5461 10:03:44.269871 DATLAT Default: 0xb
5462 10:03:44.270388 0, 0xFFFF, sum = 0
5463 10:03:44.272267 1, 0xFFFF, sum = 0
5464 10:03:44.272726 2, 0xFFFF, sum = 0
5465 10:03:44.276234 3, 0xFFFF, sum = 0
5466 10:03:44.276783 4, 0xFFFF, sum = 0
5467 10:03:44.279232 5, 0xFFFF, sum = 0
5468 10:03:44.279695 6, 0xFFFF, sum = 0
5469 10:03:44.282422 7, 0xFFFF, sum = 0
5470 10:03:44.282934 8, 0xFFFF, sum = 0
5471 10:03:44.285625 9, 0xFFFF, sum = 0
5472 10:03:44.286041 10, 0x0, sum = 1
5473 10:03:44.289330 11, 0x0, sum = 2
5474 10:03:44.289841 12, 0x0, sum = 3
5475 10:03:44.291965 13, 0x0, sum = 4
5476 10:03:44.292474 best_step = 11
5477 10:03:44.292811
5478 10:03:44.293119 ==
5479 10:03:44.295193 Dram Type= 6, Freq= 0, CH_0, rank 1
5480 10:03:44.298642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5481 10:03:44.301769 ==
5482 10:03:44.302178 RX Vref Scan: 0
5483 10:03:44.302540
5484 10:03:44.304859 RX Vref 0 -> 0, step: 1
5485 10:03:44.305267
5486 10:03:44.308492 RX Delay -53 -> 252, step: 4
5487 10:03:44.311582 iDelay=195, Bit 0, Center 94 (7 ~ 182) 176
5488 10:03:44.315260 iDelay=195, Bit 1, Center 100 (11 ~ 190) 180
5489 10:03:44.318782 iDelay=195, Bit 2, Center 92 (3 ~ 182) 180
5490 10:03:44.325360 iDelay=195, Bit 3, Center 94 (3 ~ 186) 184
5491 10:03:44.328038 iDelay=195, Bit 4, Center 100 (11 ~ 190) 180
5492 10:03:44.331713 iDelay=195, Bit 5, Center 86 (-5 ~ 178) 184
5493 10:03:44.335122 iDelay=195, Bit 6, Center 104 (15 ~ 194) 180
5494 10:03:44.338168 iDelay=195, Bit 7, Center 104 (15 ~ 194) 180
5495 10:03:44.344764 iDelay=195, Bit 8, Center 80 (-5 ~ 166) 172
5496 10:03:44.347858 iDelay=195, Bit 9, Center 76 (-9 ~ 162) 172
5497 10:03:44.351913 iDelay=195, Bit 10, Center 90 (-1 ~ 182) 184
5498 10:03:44.354347 iDelay=195, Bit 11, Center 82 (-5 ~ 170) 176
5499 10:03:44.357696 iDelay=195, Bit 12, Center 96 (11 ~ 182) 172
5500 10:03:44.364087 iDelay=195, Bit 13, Center 94 (3 ~ 186) 184
5501 10:03:44.367685 iDelay=195, Bit 14, Center 100 (11 ~ 190) 180
5502 10:03:44.370973 iDelay=195, Bit 15, Center 98 (11 ~ 186) 176
5503 10:03:44.371525 ==
5504 10:03:44.374506 Dram Type= 6, Freq= 0, CH_0, rank 1
5505 10:03:44.377760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5506 10:03:44.378221 ==
5507 10:03:44.381326 DQS Delay:
5508 10:03:44.381865 DQS0 = 0, DQS1 = 0
5509 10:03:44.383871 DQM Delay:
5510 10:03:44.384325 DQM0 = 96, DQM1 = 89
5511 10:03:44.387317 DQ Delay:
5512 10:03:44.387858 DQ0 =94, DQ1 =100, DQ2 =92, DQ3 =94
5513 10:03:44.390511 DQ4 =100, DQ5 =86, DQ6 =104, DQ7 =104
5514 10:03:44.394045 DQ8 =80, DQ9 =76, DQ10 =90, DQ11 =82
5515 10:03:44.400420 DQ12 =96, DQ13 =94, DQ14 =100, DQ15 =98
5516 10:03:44.400833
5517 10:03:44.401160
5518 10:03:44.406716 [DQSOSCAuto] RK1, (LSB)MR18= 0x1410, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 415 ps
5519 10:03:44.410023 CH0 RK1: MR19=505, MR18=1410
5520 10:03:44.416951 CH0_RK1: MR19=0x505, MR18=0x1410, DQSOSC=415, MR23=63, INC=62, DEC=41
5521 10:03:44.420426 [RxdqsGatingPostProcess] freq 933
5522 10:03:44.423687 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5523 10:03:44.427088 best DQS0 dly(2T, 0.5T) = (0, 10)
5524 10:03:44.430181 best DQS1 dly(2T, 0.5T) = (0, 11)
5525 10:03:44.433251 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5526 10:03:44.436720 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5527 10:03:44.440122 best DQS0 dly(2T, 0.5T) = (0, 10)
5528 10:03:44.443476 best DQS1 dly(2T, 0.5T) = (0, 11)
5529 10:03:44.446857 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5530 10:03:44.449557 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5531 10:03:44.453387 Pre-setting of DQS Precalculation
5532 10:03:44.456484 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5533 10:03:44.459834 ==
5534 10:03:44.463192 Dram Type= 6, Freq= 0, CH_1, rank 0
5535 10:03:44.466533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5536 10:03:44.467050 ==
5537 10:03:44.472405 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5538 10:03:44.476114 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5539 10:03:44.479941 [CA 0] Center 36 (6~66) winsize 61
5540 10:03:44.484093 [CA 1] Center 36 (6~67) winsize 62
5541 10:03:44.487130 [CA 2] Center 34 (4~65) winsize 62
5542 10:03:44.490503 [CA 3] Center 34 (4~64) winsize 61
5543 10:03:44.493473 [CA 4] Center 34 (4~64) winsize 61
5544 10:03:44.496877 [CA 5] Center 33 (3~64) winsize 62
5545 10:03:44.497385
5546 10:03:44.499850 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5547 10:03:44.500262
5548 10:03:44.503168 [CATrainingPosCal] consider 1 rank data
5549 10:03:44.506287 u2DelayCellTimex100 = 270/100 ps
5550 10:03:44.510130 CA0 delay=36 (6~66),Diff = 3 PI (18 cell)
5551 10:03:44.516936 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5552 10:03:44.519454 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5553 10:03:44.522791 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5554 10:03:44.525860 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5555 10:03:44.529530 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5556 10:03:44.529939
5557 10:03:44.532963 CA PerBit enable=1, Macro0, CA PI delay=33
5558 10:03:44.533373
5559 10:03:44.536038 [CBTSetCACLKResult] CA Dly = 33
5560 10:03:44.539579 CS Dly: 5 (0~36)
5561 10:03:44.540083 ==
5562 10:03:44.542442 Dram Type= 6, Freq= 0, CH_1, rank 1
5563 10:03:44.546122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5564 10:03:44.546571 ==
5565 10:03:44.552798 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5566 10:03:44.555342 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5567 10:03:44.560035 [CA 0] Center 36 (6~67) winsize 62
5568 10:03:44.563362 [CA 1] Center 36 (6~67) winsize 62
5569 10:03:44.566870 [CA 2] Center 34 (4~65) winsize 62
5570 10:03:44.570067 [CA 3] Center 33 (3~64) winsize 62
5571 10:03:44.573357 [CA 4] Center 33 (3~64) winsize 62
5572 10:03:44.576950 [CA 5] Center 33 (3~64) winsize 62
5573 10:03:44.577453
5574 10:03:44.580031 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5575 10:03:44.580545
5576 10:03:44.582924 [CATrainingPosCal] consider 2 rank data
5577 10:03:44.586628 u2DelayCellTimex100 = 270/100 ps
5578 10:03:44.590172 CA0 delay=36 (6~66),Diff = 3 PI (18 cell)
5579 10:03:44.596089 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5580 10:03:44.599596 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5581 10:03:44.603325 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5582 10:03:44.605820 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5583 10:03:44.610047 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5584 10:03:44.610591
5585 10:03:44.612904 CA PerBit enable=1, Macro0, CA PI delay=33
5586 10:03:44.613410
5587 10:03:44.616384 [CBTSetCACLKResult] CA Dly = 33
5588 10:03:44.619129 CS Dly: 6 (0~38)
5589 10:03:44.619542
5590 10:03:44.622318 ----->DramcWriteLeveling(PI) begin...
5591 10:03:44.622739 ==
5592 10:03:44.626159 Dram Type= 6, Freq= 0, CH_1, rank 0
5593 10:03:44.629186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5594 10:03:44.629607 ==
5595 10:03:44.632718 Write leveling (Byte 0): 29 => 29
5596 10:03:44.635769 Write leveling (Byte 1): 29 => 29
5597 10:03:44.638864 DramcWriteLeveling(PI) end<-----
5598 10:03:44.639281
5599 10:03:44.639730 ==
5600 10:03:44.642514 Dram Type= 6, Freq= 0, CH_1, rank 0
5601 10:03:44.645957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5602 10:03:44.646571 ==
5603 10:03:44.649341 [Gating] SW mode calibration
5604 10:03:44.656109 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5605 10:03:44.662326 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5606 10:03:44.665419 0 14 0 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
5607 10:03:44.668495 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5608 10:03:44.675361 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5609 10:03:44.678688 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5610 10:03:44.682109 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5611 10:03:44.688465 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5612 10:03:44.692065 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
5613 10:03:44.694916 0 14 28 | B1->B0 | 2929 2424 | 0 0 | (1 0) (1 0)
5614 10:03:44.701690 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5615 10:03:44.704740 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5616 10:03:44.708452 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5617 10:03:44.714886 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5618 10:03:44.718186 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5619 10:03:44.721753 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5620 10:03:44.727701 0 15 24 | B1->B0 | 2525 2b2b | 0 0 | (0 0) (1 1)
5621 10:03:44.731116 0 15 28 | B1->B0 | 3838 3a3a | 1 0 | (0 0) (0 0)
5622 10:03:44.734638 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5623 10:03:44.740902 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5624 10:03:44.744216 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5625 10:03:44.751219 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5626 10:03:44.754467 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5627 10:03:44.757462 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5628 10:03:44.761310 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5629 10:03:44.767730 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5630 10:03:44.770908 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 10:03:44.774090 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 10:03:44.780863 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 10:03:44.783879 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 10:03:44.790388 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 10:03:44.793565 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 10:03:44.797167 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 10:03:44.803657 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5638 10:03:44.806705 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 10:03:44.810232 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 10:03:44.816804 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 10:03:44.820025 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 10:03:44.823459 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 10:03:44.829958 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 10:03:44.833509 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5645 10:03:44.836724 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5646 10:03:44.839861 Total UI for P1: 0, mck2ui 16
5647 10:03:44.843717 best dqsien dly found for B1: ( 1, 2, 26)
5648 10:03:44.846578 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5649 10:03:44.849980 Total UI for P1: 0, mck2ui 16
5650 10:03:44.853291 best dqsien dly found for B0: ( 1, 2, 26)
5651 10:03:44.859291 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5652 10:03:44.862946 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5653 10:03:44.863494
5654 10:03:44.866327 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5655 10:03:44.869489 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5656 10:03:44.873004 [Gating] SW calibration Done
5657 10:03:44.873432 ==
5658 10:03:44.876281 Dram Type= 6, Freq= 0, CH_1, rank 0
5659 10:03:44.879541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5660 10:03:44.880087 ==
5661 10:03:44.882822 RX Vref Scan: 0
5662 10:03:44.883363
5663 10:03:44.883728 RX Vref 0 -> 0, step: 1
5664 10:03:44.884064
5665 10:03:44.886202 RX Delay -80 -> 252, step: 8
5666 10:03:44.888916 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5667 10:03:44.895916 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5668 10:03:44.899043 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5669 10:03:44.902645 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5670 10:03:44.905415 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5671 10:03:44.908628 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5672 10:03:44.912689 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5673 10:03:44.918948 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5674 10:03:44.922576 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5675 10:03:44.925382 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5676 10:03:44.928519 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5677 10:03:44.932356 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5678 10:03:44.938448 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5679 10:03:44.941671 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5680 10:03:44.945416 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5681 10:03:44.948772 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5682 10:03:44.949311 ==
5683 10:03:44.951603 Dram Type= 6, Freq= 0, CH_1, rank 0
5684 10:03:44.958082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5685 10:03:44.958725 ==
5686 10:03:44.959096 DQS Delay:
5687 10:03:44.959435 DQS0 = 0, DQS1 = 0
5688 10:03:44.961531 DQM Delay:
5689 10:03:44.962067 DQM0 = 99, DQM1 = 96
5690 10:03:44.964445 DQ Delay:
5691 10:03:44.968321 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =99
5692 10:03:44.971032 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5693 10:03:44.974377 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =91
5694 10:03:44.978019 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5695 10:03:44.978623
5696 10:03:44.978995
5697 10:03:44.979333 ==
5698 10:03:44.981474 Dram Type= 6, Freq= 0, CH_1, rank 0
5699 10:03:44.984331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5700 10:03:44.984793 ==
5701 10:03:44.985160
5702 10:03:44.985499
5703 10:03:44.987974 TX Vref Scan disable
5704 10:03:44.991206 == TX Byte 0 ==
5705 10:03:44.994418 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5706 10:03:44.997672 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5707 10:03:45.000708 == TX Byte 1 ==
5708 10:03:45.004635 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5709 10:03:45.008037 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5710 10:03:45.008500 ==
5711 10:03:45.010967 Dram Type= 6, Freq= 0, CH_1, rank 0
5712 10:03:45.017348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5713 10:03:45.017902 ==
5714 10:03:45.018329
5715 10:03:45.018706
5716 10:03:45.019036 TX Vref Scan disable
5717 10:03:45.021334 == TX Byte 0 ==
5718 10:03:45.024788 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5719 10:03:45.031319 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5720 10:03:45.031852 == TX Byte 1 ==
5721 10:03:45.035005 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5722 10:03:45.040916 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5723 10:03:45.041451
5724 10:03:45.041813 [DATLAT]
5725 10:03:45.042144 Freq=933, CH1 RK0
5726 10:03:45.042569
5727 10:03:45.044972 DATLAT Default: 0xd
5728 10:03:45.047575 0, 0xFFFF, sum = 0
5729 10:03:45.048134 1, 0xFFFF, sum = 0
5730 10:03:45.050799 2, 0xFFFF, sum = 0
5731 10:03:45.051554 3, 0xFFFF, sum = 0
5732 10:03:45.054019 4, 0xFFFF, sum = 0
5733 10:03:45.054674 5, 0xFFFF, sum = 0
5734 10:03:45.057733 6, 0xFFFF, sum = 0
5735 10:03:45.058336 7, 0xFFFF, sum = 0
5736 10:03:45.061394 8, 0xFFFF, sum = 0
5737 10:03:45.061950 9, 0xFFFF, sum = 0
5738 10:03:45.063967 10, 0x0, sum = 1
5739 10:03:45.064444 11, 0x0, sum = 2
5740 10:03:45.067665 12, 0x0, sum = 3
5741 10:03:45.068217 13, 0x0, sum = 4
5742 10:03:45.070319 best_step = 11
5743 10:03:45.070777
5744 10:03:45.071139 ==
5745 10:03:45.074180 Dram Type= 6, Freq= 0, CH_1, rank 0
5746 10:03:45.077218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5747 10:03:45.077771 ==
5748 10:03:45.078140 RX Vref Scan: 1
5749 10:03:45.078677
5750 10:03:45.080650 RX Vref 0 -> 0, step: 1
5751 10:03:45.081199
5752 10:03:45.083591 RX Delay -53 -> 252, step: 4
5753 10:03:45.084047
5754 10:03:45.087223 Set Vref, RX VrefLevel [Byte0]: 52
5755 10:03:45.090603 [Byte1]: 53
5756 10:03:45.093947
5757 10:03:45.094542 Final RX Vref Byte 0 = 52 to rank0
5758 10:03:45.096918 Final RX Vref Byte 1 = 53 to rank0
5759 10:03:45.100733 Final RX Vref Byte 0 = 52 to rank1
5760 10:03:45.103720 Final RX Vref Byte 1 = 53 to rank1==
5761 10:03:45.107083 Dram Type= 6, Freq= 0, CH_1, rank 0
5762 10:03:45.113610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5763 10:03:45.114157 ==
5764 10:03:45.114646 DQS Delay:
5765 10:03:45.116847 DQS0 = 0, DQS1 = 0
5766 10:03:45.117318 DQM Delay:
5767 10:03:45.117678 DQM0 = 98, DQM1 = 94
5768 10:03:45.120481 DQ Delay:
5769 10:03:45.123085 DQ0 =104, DQ1 =92, DQ2 =88, DQ3 =98
5770 10:03:45.126583 DQ4 =96, DQ5 =106, DQ6 =108, DQ7 =94
5771 10:03:45.129993 DQ8 =82, DQ9 =84, DQ10 =92, DQ11 =88
5772 10:03:45.133469 DQ12 =102, DQ13 =102, DQ14 =102, DQ15 =104
5773 10:03:45.133968
5774 10:03:45.134370
5775 10:03:45.139757 [DQSOSCAuto] RK0, (LSB)MR18= 0xc1b, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 418 ps
5776 10:03:45.143027 CH1 RK0: MR19=505, MR18=C1B
5777 10:03:45.149857 CH1_RK0: MR19=0x505, MR18=0xC1B, DQSOSC=413, MR23=63, INC=63, DEC=42
5778 10:03:45.150468
5779 10:03:45.153393 ----->DramcWriteLeveling(PI) begin...
5780 10:03:45.153945 ==
5781 10:03:45.156107 Dram Type= 6, Freq= 0, CH_1, rank 1
5782 10:03:45.159886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5783 10:03:45.160433 ==
5784 10:03:45.162786 Write leveling (Byte 0): 25 => 25
5785 10:03:45.166179 Write leveling (Byte 1): 25 => 25
5786 10:03:45.169536 DramcWriteLeveling(PI) end<-----
5787 10:03:45.170161
5788 10:03:45.170750 ==
5789 10:03:45.172982 Dram Type= 6, Freq= 0, CH_1, rank 1
5790 10:03:45.179418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5791 10:03:45.179965 ==
5792 10:03:45.180325 [Gating] SW mode calibration
5793 10:03:45.189840 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5794 10:03:45.192619 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5795 10:03:45.199140 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5796 10:03:45.202718 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5797 10:03:45.206005 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5798 10:03:45.212589 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5799 10:03:45.215823 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5800 10:03:45.218754 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5801 10:03:45.224957 0 14 24 | B1->B0 | 3333 2f2f | 1 1 | (1 1) (1 0)
5802 10:03:45.228352 0 14 28 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
5803 10:03:45.231747 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5804 10:03:45.238360 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5805 10:03:45.241349 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5806 10:03:45.245082 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5807 10:03:45.251542 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5808 10:03:45.255152 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5809 10:03:45.258115 0 15 24 | B1->B0 | 2424 3636 | 0 0 | (0 0) (1 1)
5810 10:03:45.264921 0 15 28 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
5811 10:03:45.267659 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5812 10:03:45.271140 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5813 10:03:45.277606 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5814 10:03:45.281062 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5815 10:03:45.284738 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5816 10:03:45.291282 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5817 10:03:45.293852 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5818 10:03:45.297140 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5819 10:03:45.304052 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5820 10:03:45.307045 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5821 10:03:45.310500 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5822 10:03:45.317151 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5823 10:03:45.320451 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5824 10:03:45.323695 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5825 10:03:45.330505 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5826 10:03:45.333940 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5827 10:03:45.336860 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5828 10:03:45.343285 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5829 10:03:45.347021 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5830 10:03:45.349707 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5831 10:03:45.356462 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5832 10:03:45.359939 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5833 10:03:45.363053 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5834 10:03:45.369997 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5835 10:03:45.373381 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5836 10:03:45.376372 Total UI for P1: 0, mck2ui 16
5837 10:03:45.380090 best dqsien dly found for B0: ( 1, 2, 28)
5838 10:03:45.382990 Total UI for P1: 0, mck2ui 16
5839 10:03:45.386402 best dqsien dly found for B1: ( 1, 2, 28)
5840 10:03:45.389518 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5841 10:03:45.393256 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5842 10:03:45.393802
5843 10:03:45.396093 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5844 10:03:45.403117 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5845 10:03:45.403666 [Gating] SW calibration Done
5846 10:03:45.404030 ==
5847 10:03:45.406161 Dram Type= 6, Freq= 0, CH_1, rank 1
5848 10:03:45.412471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5849 10:03:45.413040 ==
5850 10:03:45.413412 RX Vref Scan: 0
5851 10:03:45.413756
5852 10:03:45.415648 RX Vref 0 -> 0, step: 1
5853 10:03:45.416192
5854 10:03:45.418872 RX Delay -80 -> 252, step: 8
5855 10:03:45.422123 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5856 10:03:45.425926 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5857 10:03:45.428920 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5858 10:03:45.435633 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5859 10:03:45.438957 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5860 10:03:45.442217 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5861 10:03:45.445678 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5862 10:03:45.449061 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5863 10:03:45.451623 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5864 10:03:45.458925 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5865 10:03:45.461835 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5866 10:03:45.464798 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5867 10:03:45.468303 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5868 10:03:45.471527 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5869 10:03:45.478174 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5870 10:03:45.481096 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5871 10:03:45.481569 ==
5872 10:03:45.484669 Dram Type= 6, Freq= 0, CH_1, rank 1
5873 10:03:45.488450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5874 10:03:45.488992 ==
5875 10:03:45.489464 DQS Delay:
5876 10:03:45.491398 DQS0 = 0, DQS1 = 0
5877 10:03:45.492019 DQM Delay:
5878 10:03:45.494529 DQM0 = 97, DQM1 = 94
5879 10:03:45.494939 DQ Delay:
5880 10:03:45.497747 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =95
5881 10:03:45.500946 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5882 10:03:45.504386 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5883 10:03:45.508073 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5884 10:03:45.508486
5885 10:03:45.508809
5886 10:03:45.509108 ==
5887 10:03:45.510964 Dram Type= 6, Freq= 0, CH_1, rank 1
5888 10:03:45.517637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5889 10:03:45.518509 ==
5890 10:03:45.519008
5891 10:03:45.519330
5892 10:03:45.519630 TX Vref Scan disable
5893 10:03:45.521393 == TX Byte 0 ==
5894 10:03:45.524780 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5895 10:03:45.531507 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5896 10:03:45.531963 == TX Byte 1 ==
5897 10:03:45.534541 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5898 10:03:45.541123 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5899 10:03:45.541536 ==
5900 10:03:45.544744 Dram Type= 6, Freq= 0, CH_1, rank 1
5901 10:03:45.548122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5902 10:03:45.548633 ==
5903 10:03:45.548962
5904 10:03:45.549266
5905 10:03:45.550987 TX Vref Scan disable
5906 10:03:45.551396 == TX Byte 0 ==
5907 10:03:45.558008 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5908 10:03:45.561145 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5909 10:03:45.564558 == TX Byte 1 ==
5910 10:03:45.567568 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5911 10:03:45.571082 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5912 10:03:45.571610
5913 10:03:45.571944 [DATLAT]
5914 10:03:45.573780 Freq=933, CH1 RK1
5915 10:03:45.574406
5916 10:03:45.577202 DATLAT Default: 0xb
5917 10:03:45.577612 0, 0xFFFF, sum = 0
5918 10:03:45.580507 1, 0xFFFF, sum = 0
5919 10:03:45.580922 2, 0xFFFF, sum = 0
5920 10:03:45.584110 3, 0xFFFF, sum = 0
5921 10:03:45.584620 4, 0xFFFF, sum = 0
5922 10:03:45.586986 5, 0xFFFF, sum = 0
5923 10:03:45.587406 6, 0xFFFF, sum = 0
5924 10:03:45.591192 7, 0xFFFF, sum = 0
5925 10:03:45.591720 8, 0xFFFF, sum = 0
5926 10:03:45.594290 9, 0xFFFF, sum = 0
5927 10:03:45.594814 10, 0x0, sum = 1
5928 10:03:45.596891 11, 0x0, sum = 2
5929 10:03:45.597308 12, 0x0, sum = 3
5930 10:03:45.600201 13, 0x0, sum = 4
5931 10:03:45.600621 best_step = 11
5932 10:03:45.600949
5933 10:03:45.601253 ==
5934 10:03:45.604441 Dram Type= 6, Freq= 0, CH_1, rank 1
5935 10:03:45.607197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5936 10:03:45.610532 ==
5937 10:03:45.611057 RX Vref Scan: 0
5938 10:03:45.611389
5939 10:03:45.613722 RX Vref 0 -> 0, step: 1
5940 10:03:45.614224
5941 10:03:45.617039 RX Delay -53 -> 252, step: 4
5942 10:03:45.620586 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5943 10:03:45.623450 iDelay=199, Bit 1, Center 94 (-1 ~ 190) 192
5944 10:03:45.630007 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5945 10:03:45.633825 iDelay=199, Bit 3, Center 94 (3 ~ 186) 184
5946 10:03:45.637262 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5947 10:03:45.639972 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5948 10:03:45.643456 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5949 10:03:45.646697 iDelay=199, Bit 7, Center 94 (-1 ~ 190) 192
5950 10:03:45.653270 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5951 10:03:45.656590 iDelay=199, Bit 9, Center 82 (-9 ~ 174) 184
5952 10:03:45.660213 iDelay=199, Bit 10, Center 92 (-1 ~ 186) 188
5953 10:03:45.662958 iDelay=199, Bit 11, Center 86 (-5 ~ 178) 184
5954 10:03:45.665915 iDelay=199, Bit 12, Center 102 (11 ~ 194) 184
5955 10:03:45.673115 iDelay=199, Bit 13, Center 102 (11 ~ 194) 184
5956 10:03:45.676142 iDelay=199, Bit 14, Center 100 (11 ~ 190) 180
5957 10:03:45.680324 iDelay=199, Bit 15, Center 102 (11 ~ 194) 184
5958 10:03:45.680829 ==
5959 10:03:45.682394 Dram Type= 6, Freq= 0, CH_1, rank 1
5960 10:03:45.686713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5961 10:03:45.689437 ==
5962 10:03:45.689938 DQS Delay:
5963 10:03:45.690303 DQS0 = 0, DQS1 = 0
5964 10:03:45.692845 DQM Delay:
5965 10:03:45.693255 DQM0 = 97, DQM1 = 93
5966 10:03:45.695879 DQ Delay:
5967 10:03:45.698823 DQ0 =102, DQ1 =94, DQ2 =88, DQ3 =94
5968 10:03:45.702491 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =94
5969 10:03:45.705810 DQ8 =80, DQ9 =82, DQ10 =92, DQ11 =86
5970 10:03:45.709128 DQ12 =102, DQ13 =102, DQ14 =100, DQ15 =102
5971 10:03:45.709633
5972 10:03:45.710010
5973 10:03:45.716295 [DQSOSCAuto] RK1, (LSB)MR18= 0xa20, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 418 ps
5974 10:03:45.719032 CH1 RK1: MR19=505, MR18=A20
5975 10:03:45.725470 CH1_RK1: MR19=0x505, MR18=0xA20, DQSOSC=411, MR23=63, INC=64, DEC=42
5976 10:03:45.729036 [RxdqsGatingPostProcess] freq 933
5977 10:03:45.731672 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5978 10:03:45.735822 best DQS0 dly(2T, 0.5T) = (0, 10)
5979 10:03:45.738523 best DQS1 dly(2T, 0.5T) = (0, 10)
5980 10:03:45.741640 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5981 10:03:45.744970 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5982 10:03:45.748424 best DQS0 dly(2T, 0.5T) = (0, 10)
5983 10:03:45.751599 best DQS1 dly(2T, 0.5T) = (0, 10)
5984 10:03:45.754850 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5985 10:03:45.757931 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5986 10:03:45.761845 Pre-setting of DQS Precalculation
5987 10:03:45.768539 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5988 10:03:45.774710 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5989 10:03:45.781706 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5990 10:03:45.782248
5991 10:03:45.782679
5992 10:03:45.784851 [Calibration Summary] 1866 Mbps
5993 10:03:45.785398 CH 0, Rank 0
5994 10:03:45.787752 SW Impedance : PASS
5995 10:03:45.791230 DUTY Scan : NO K
5996 10:03:45.791774 ZQ Calibration : PASS
5997 10:03:45.794952 Jitter Meter : NO K
5998 10:03:45.797707 CBT Training : PASS
5999 10:03:45.798162 Write leveling : PASS
6000 10:03:45.800886 RX DQS gating : PASS
6001 10:03:45.804367 RX DQ/DQS(RDDQC) : PASS
6002 10:03:45.804913 TX DQ/DQS : PASS
6003 10:03:45.807300 RX DATLAT : PASS
6004 10:03:45.810476 RX DQ/DQS(Engine): PASS
6005 10:03:45.810928 TX OE : NO K
6006 10:03:45.811294 All Pass.
6007 10:03:45.813945
6008 10:03:45.814399 CH 0, Rank 1
6009 10:03:45.817330 SW Impedance : PASS
6010 10:03:45.817845 DUTY Scan : NO K
6011 10:03:45.820445 ZQ Calibration : PASS
6012 10:03:45.823607 Jitter Meter : NO K
6013 10:03:45.824023 CBT Training : PASS
6014 10:03:45.826913 Write leveling : PASS
6015 10:03:45.827324 RX DQS gating : PASS
6016 10:03:45.830217 RX DQ/DQS(RDDQC) : PASS
6017 10:03:45.833374 TX DQ/DQS : PASS
6018 10:03:45.833783 RX DATLAT : PASS
6019 10:03:45.837062 RX DQ/DQS(Engine): PASS
6020 10:03:45.840309 TX OE : NO K
6021 10:03:45.840816 All Pass.
6022 10:03:45.841147
6023 10:03:45.841452 CH 1, Rank 0
6024 10:03:45.843076 SW Impedance : PASS
6025 10:03:45.847017 DUTY Scan : NO K
6026 10:03:45.847515 ZQ Calibration : PASS
6027 10:03:45.850133 Jitter Meter : NO K
6028 10:03:45.853662 CBT Training : PASS
6029 10:03:45.854158 Write leveling : PASS
6030 10:03:45.856650 RX DQS gating : PASS
6031 10:03:45.860557 RX DQ/DQS(RDDQC) : PASS
6032 10:03:45.861059 TX DQ/DQS : PASS
6033 10:03:45.863444 RX DATLAT : PASS
6034 10:03:45.866338 RX DQ/DQS(Engine): PASS
6035 10:03:45.866914 TX OE : NO K
6036 10:03:45.869875 All Pass.
6037 10:03:45.870419
6038 10:03:45.870757 CH 1, Rank 1
6039 10:03:45.873258 SW Impedance : PASS
6040 10:03:45.873668 DUTY Scan : NO K
6041 10:03:45.876417 ZQ Calibration : PASS
6042 10:03:45.880004 Jitter Meter : NO K
6043 10:03:45.880502 CBT Training : PASS
6044 10:03:45.882623 Write leveling : PASS
6045 10:03:45.886601 RX DQS gating : PASS
6046 10:03:45.887160 RX DQ/DQS(RDDQC) : PASS
6047 10:03:45.889564 TX DQ/DQS : PASS
6048 10:03:45.893115 RX DATLAT : PASS
6049 10:03:45.893532 RX DQ/DQS(Engine): PASS
6050 10:03:45.896278 TX OE : NO K
6051 10:03:45.896785 All Pass.
6052 10:03:45.897115
6053 10:03:45.899453 DramC Write-DBI off
6054 10:03:45.902728 PER_BANK_REFRESH: Hybrid Mode
6055 10:03:45.903138 TX_TRACKING: ON
6056 10:03:45.912290 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6057 10:03:45.916054 [FAST_K] Save calibration result to emmc
6058 10:03:45.919308 dramc_set_vcore_voltage set vcore to 650000
6059 10:03:45.922885 Read voltage for 400, 6
6060 10:03:45.923296 Vio18 = 0
6061 10:03:45.923629 Vcore = 650000
6062 10:03:45.925976 Vdram = 0
6063 10:03:45.926536 Vddq = 0
6064 10:03:45.926873 Vmddr = 0
6065 10:03:45.932187 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6066 10:03:45.935725 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6067 10:03:45.938738 MEM_TYPE=3, freq_sel=20
6068 10:03:45.942141 sv_algorithm_assistance_LP4_800
6069 10:03:45.945581 ============ PULL DRAM RESETB DOWN ============
6070 10:03:45.948971 ========== PULL DRAM RESETB DOWN end =========
6071 10:03:45.955448 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6072 10:03:45.958591 ===================================
6073 10:03:45.962162 LPDDR4 DRAM CONFIGURATION
6074 10:03:45.965708 ===================================
6075 10:03:45.966216 EX_ROW_EN[0] = 0x0
6076 10:03:45.968517 EX_ROW_EN[1] = 0x0
6077 10:03:45.969017 LP4Y_EN = 0x0
6078 10:03:45.971517 WORK_FSP = 0x0
6079 10:03:45.971928 WL = 0x2
6080 10:03:45.975133 RL = 0x2
6081 10:03:45.975720 BL = 0x2
6082 10:03:45.978235 RPST = 0x0
6083 10:03:45.978778 RD_PRE = 0x0
6084 10:03:45.981709 WR_PRE = 0x1
6085 10:03:45.985326 WR_PST = 0x0
6086 10:03:45.985832 DBI_WR = 0x0
6087 10:03:45.988734 DBI_RD = 0x0
6088 10:03:45.989233 OTF = 0x1
6089 10:03:45.991364 ===================================
6090 10:03:45.995126 ===================================
6091 10:03:45.998384 ANA top config
6092 10:03:45.998884 ===================================
6093 10:03:46.001280 DLL_ASYNC_EN = 0
6094 10:03:46.004777 ALL_SLAVE_EN = 1
6095 10:03:46.007418 NEW_RANK_MODE = 1
6096 10:03:46.011200 DLL_IDLE_MODE = 1
6097 10:03:46.011694 LP45_APHY_COMB_EN = 1
6098 10:03:46.014692 TX_ODT_DIS = 1
6099 10:03:46.017948 NEW_8X_MODE = 1
6100 10:03:46.021269 ===================================
6101 10:03:46.024687 ===================================
6102 10:03:46.027584 data_rate = 800
6103 10:03:46.030803 CKR = 1
6104 10:03:46.034328 DQ_P2S_RATIO = 4
6105 10:03:46.037784 ===================================
6106 10:03:46.038207 CA_P2S_RATIO = 4
6107 10:03:46.040868 DQ_CA_OPEN = 0
6108 10:03:46.044210 DQ_SEMI_OPEN = 1
6109 10:03:46.047869 CA_SEMI_OPEN = 1
6110 10:03:46.051091 CA_FULL_RATE = 0
6111 10:03:46.054435 DQ_CKDIV4_EN = 0
6112 10:03:46.054939 CA_CKDIV4_EN = 1
6113 10:03:46.057429 CA_PREDIV_EN = 0
6114 10:03:46.060465 PH8_DLY = 0
6115 10:03:46.064322 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6116 10:03:46.066975 DQ_AAMCK_DIV = 0
6117 10:03:46.070569 CA_AAMCK_DIV = 0
6118 10:03:46.071075 CA_ADMCK_DIV = 4
6119 10:03:46.073691 DQ_TRACK_CA_EN = 0
6120 10:03:46.077145 CA_PICK = 800
6121 10:03:46.080462 CA_MCKIO = 400
6122 10:03:46.083932 MCKIO_SEMI = 400
6123 10:03:46.087398 PLL_FREQ = 3016
6124 10:03:46.090349 DQ_UI_PI_RATIO = 32
6125 10:03:46.093745 CA_UI_PI_RATIO = 32
6126 10:03:46.097099 ===================================
6127 10:03:46.100290 ===================================
6128 10:03:46.100798 memory_type:LPDDR4
6129 10:03:46.103643 GP_NUM : 10
6130 10:03:46.107178 SRAM_EN : 1
6131 10:03:46.107685 MD32_EN : 0
6132 10:03:46.109771 ===================================
6133 10:03:46.113306 [ANA_INIT] >>>>>>>>>>>>>>
6134 10:03:46.116958 <<<<<< [CONFIGURE PHASE]: ANA_TX
6135 10:03:46.120158 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6136 10:03:46.122805 ===================================
6137 10:03:46.126897 data_rate = 800,PCW = 0X7400
6138 10:03:46.130213 ===================================
6139 10:03:46.133157 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6140 10:03:46.136476 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6141 10:03:46.149828 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6142 10:03:46.152855 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6143 10:03:46.156537 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6144 10:03:46.159496 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6145 10:03:46.162686 [ANA_INIT] flow start
6146 10:03:46.166415 [ANA_INIT] PLL >>>>>>>>
6147 10:03:46.166923 [ANA_INIT] PLL <<<<<<<<
6148 10:03:46.169794 [ANA_INIT] MIDPI >>>>>>>>
6149 10:03:46.172882 [ANA_INIT] MIDPI <<<<<<<<
6150 10:03:46.173397 [ANA_INIT] DLL >>>>>>>>
6151 10:03:46.175713 [ANA_INIT] flow end
6152 10:03:46.180015 ============ LP4 DIFF to SE enter ============
6153 10:03:46.186277 ============ LP4 DIFF to SE exit ============
6154 10:03:46.186791 [ANA_INIT] <<<<<<<<<<<<<
6155 10:03:46.188680 [Flow] Enable top DCM control >>>>>
6156 10:03:46.192505 [Flow] Enable top DCM control <<<<<
6157 10:03:46.195414 Enable DLL master slave shuffle
6158 10:03:46.201966 ==============================================================
6159 10:03:46.202497 Gating Mode config
6160 10:03:46.208594 ==============================================================
6161 10:03:46.211903 Config description:
6162 10:03:46.221564 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6163 10:03:46.228679 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6164 10:03:46.231819 SELPH_MODE 0: By rank 1: By Phase
6165 10:03:46.238640 ==============================================================
6166 10:03:46.241731 GAT_TRACK_EN = 0
6167 10:03:46.244799 RX_GATING_MODE = 2
6168 10:03:46.245325 RX_GATING_TRACK_MODE = 2
6169 10:03:46.248217 SELPH_MODE = 1
6170 10:03:46.251382 PICG_EARLY_EN = 1
6171 10:03:46.254705 VALID_LAT_VALUE = 1
6172 10:03:46.261629 ==============================================================
6173 10:03:46.264517 Enter into Gating configuration >>>>
6174 10:03:46.267544 Exit from Gating configuration <<<<
6175 10:03:46.270960 Enter into DVFS_PRE_config >>>>>
6176 10:03:46.280904 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6177 10:03:46.284604 Exit from DVFS_PRE_config <<<<<
6178 10:03:46.287899 Enter into PICG configuration >>>>
6179 10:03:46.291095 Exit from PICG configuration <<<<
6180 10:03:46.293901 [RX_INPUT] configuration >>>>>
6181 10:03:46.297621 [RX_INPUT] configuration <<<<<
6182 10:03:46.300953 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6183 10:03:46.307638 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6184 10:03:46.314059 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6185 10:03:46.320574 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6186 10:03:46.326924 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6187 10:03:46.333360 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6188 10:03:46.336975 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6189 10:03:46.340359 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6190 10:03:46.343271 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6191 10:03:46.350116 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6192 10:03:46.353899 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6193 10:03:46.356942 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6194 10:03:46.360032 ===================================
6195 10:03:46.363510 LPDDR4 DRAM CONFIGURATION
6196 10:03:46.366572 ===================================
6197 10:03:46.367120 EX_ROW_EN[0] = 0x0
6198 10:03:46.369879 EX_ROW_EN[1] = 0x0
6199 10:03:46.373425 LP4Y_EN = 0x0
6200 10:03:46.373984 WORK_FSP = 0x0
6201 10:03:46.376934 WL = 0x2
6202 10:03:46.377501 RL = 0x2
6203 10:03:46.379631 BL = 0x2
6204 10:03:46.380089 RPST = 0x0
6205 10:03:46.383193 RD_PRE = 0x0
6206 10:03:46.383695 WR_PRE = 0x1
6207 10:03:46.386403 WR_PST = 0x0
6208 10:03:46.386906 DBI_WR = 0x0
6209 10:03:46.390421 DBI_RD = 0x0
6210 10:03:46.390924 OTF = 0x1
6211 10:03:46.393256 ===================================
6212 10:03:46.396138 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6213 10:03:46.402973 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6214 10:03:46.406111 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6215 10:03:46.409814 ===================================
6216 10:03:46.412865 LPDDR4 DRAM CONFIGURATION
6217 10:03:46.415658 ===================================
6218 10:03:46.416082 EX_ROW_EN[0] = 0x10
6219 10:03:46.419089 EX_ROW_EN[1] = 0x0
6220 10:03:46.422538 LP4Y_EN = 0x0
6221 10:03:46.423053 WORK_FSP = 0x0
6222 10:03:46.425884 WL = 0x2
6223 10:03:46.426425 RL = 0x2
6224 10:03:46.429300 BL = 0x2
6225 10:03:46.429807 RPST = 0x0
6226 10:03:46.432169 RD_PRE = 0x0
6227 10:03:46.432689 WR_PRE = 0x1
6228 10:03:46.436431 WR_PST = 0x0
6229 10:03:46.437012 DBI_WR = 0x0
6230 10:03:46.439379 DBI_RD = 0x0
6231 10:03:46.439940 OTF = 0x1
6232 10:03:46.442327 ===================================
6233 10:03:46.448664 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6234 10:03:46.453725 nWR fixed to 30
6235 10:03:46.456839 [ModeRegInit_LP4] CH0 RK0
6236 10:03:46.457349 [ModeRegInit_LP4] CH0 RK1
6237 10:03:46.459568 [ModeRegInit_LP4] CH1 RK0
6238 10:03:46.463155 [ModeRegInit_LP4] CH1 RK1
6239 10:03:46.463662 match AC timing 19
6240 10:03:46.470506 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6241 10:03:46.473499 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6242 10:03:46.476410 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6243 10:03:46.483268 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6244 10:03:46.485968 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6245 10:03:46.486467 ==
6246 10:03:46.489271 Dram Type= 6, Freq= 0, CH_0, rank 0
6247 10:03:46.492736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6248 10:03:46.493290 ==
6249 10:03:46.499188 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6250 10:03:46.505646 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6251 10:03:46.509393 [CA 0] Center 36 (8~64) winsize 57
6252 10:03:46.512261 [CA 1] Center 36 (8~64) winsize 57
6253 10:03:46.515443 [CA 2] Center 36 (8~64) winsize 57
6254 10:03:46.518966 [CA 3] Center 36 (8~64) winsize 57
6255 10:03:46.522611 [CA 4] Center 36 (8~64) winsize 57
6256 10:03:46.525814 [CA 5] Center 36 (8~64) winsize 57
6257 10:03:46.526410
6258 10:03:46.529174 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6259 10:03:46.529721
6260 10:03:46.532361 [CATrainingPosCal] consider 1 rank data
6261 10:03:46.535374 u2DelayCellTimex100 = 270/100 ps
6262 10:03:46.538828 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6263 10:03:46.541857 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6264 10:03:46.545397 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6265 10:03:46.548708 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6266 10:03:46.551548 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6267 10:03:46.555096 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6268 10:03:46.555612
6269 10:03:46.561619 CA PerBit enable=1, Macro0, CA PI delay=36
6270 10:03:46.562220
6271 10:03:46.564893 [CBTSetCACLKResult] CA Dly = 36
6272 10:03:46.565589 CS Dly: 1 (0~32)
6273 10:03:46.566165 ==
6274 10:03:46.568205 Dram Type= 6, Freq= 0, CH_0, rank 1
6275 10:03:46.571421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6276 10:03:46.571835 ==
6277 10:03:46.577787 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6278 10:03:46.584308 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6279 10:03:46.587664 [CA 0] Center 36 (8~64) winsize 57
6280 10:03:46.591083 [CA 1] Center 36 (8~64) winsize 57
6281 10:03:46.594849 [CA 2] Center 36 (8~64) winsize 57
6282 10:03:46.598063 [CA 3] Center 36 (8~64) winsize 57
6283 10:03:46.600955 [CA 4] Center 36 (8~64) winsize 57
6284 10:03:46.604430 [CA 5] Center 36 (8~64) winsize 57
6285 10:03:46.604842
6286 10:03:46.608323 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6287 10:03:46.608829
6288 10:03:46.610815 [CATrainingPosCal] consider 2 rank data
6289 10:03:46.615019 u2DelayCellTimex100 = 270/100 ps
6290 10:03:46.617184 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6291 10:03:46.621040 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6292 10:03:46.624242 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6293 10:03:46.627606 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6294 10:03:46.630440 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6295 10:03:46.633732 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6296 10:03:46.634156
6297 10:03:46.640741 CA PerBit enable=1, Macro0, CA PI delay=36
6298 10:03:46.641259
6299 10:03:46.644263 [CBTSetCACLKResult] CA Dly = 36
6300 10:03:46.644821 CS Dly: 1 (0~32)
6301 10:03:46.645184
6302 10:03:46.646935 ----->DramcWriteLeveling(PI) begin...
6303 10:03:46.647389 ==
6304 10:03:46.650405 Dram Type= 6, Freq= 0, CH_0, rank 0
6305 10:03:46.653525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6306 10:03:46.653933 ==
6307 10:03:46.657128 Write leveling (Byte 0): 40 => 8
6308 10:03:46.660126 Write leveling (Byte 1): 40 => 8
6309 10:03:46.663736 DramcWriteLeveling(PI) end<-----
6310 10:03:46.664270
6311 10:03:46.664593 ==
6312 10:03:46.666746 Dram Type= 6, Freq= 0, CH_0, rank 0
6313 10:03:46.673717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6314 10:03:46.674338 ==
6315 10:03:46.674706 [Gating] SW mode calibration
6316 10:03:46.683455 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6317 10:03:46.686826 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6318 10:03:46.690395 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6319 10:03:46.696597 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6320 10:03:46.700096 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6321 10:03:46.706425 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6322 10:03:46.709619 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6323 10:03:46.712918 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6324 10:03:46.719827 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6325 10:03:46.722985 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6326 10:03:46.726164 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6327 10:03:46.729872 Total UI for P1: 0, mck2ui 16
6328 10:03:46.733150 best dqsien dly found for B0: ( 0, 14, 24)
6329 10:03:46.736166 Total UI for P1: 0, mck2ui 16
6330 10:03:46.739298 best dqsien dly found for B1: ( 0, 14, 24)
6331 10:03:46.742696 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6332 10:03:46.745764 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6333 10:03:46.746171
6334 10:03:46.753204 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6335 10:03:46.755529 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6336 10:03:46.759239 [Gating] SW calibration Done
6337 10:03:46.759744 ==
6338 10:03:46.762420 Dram Type= 6, Freq= 0, CH_0, rank 0
6339 10:03:46.765114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6340 10:03:46.765524 ==
6341 10:03:46.765847 RX Vref Scan: 0
6342 10:03:46.766147
6343 10:03:46.768589 RX Vref 0 -> 0, step: 1
6344 10:03:46.768995
6345 10:03:46.771829 RX Delay -410 -> 252, step: 16
6346 10:03:46.774845 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6347 10:03:46.781765 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6348 10:03:46.784930 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6349 10:03:46.788029 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6350 10:03:46.791277 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6351 10:03:46.798143 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6352 10:03:46.801384 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6353 10:03:46.804733 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6354 10:03:46.807608 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6355 10:03:46.814068 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6356 10:03:46.817485 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6357 10:03:46.820912 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6358 10:03:46.827668 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6359 10:03:46.830761 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6360 10:03:46.833866 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6361 10:03:46.836956 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6362 10:03:46.840446 ==
6363 10:03:46.843959 Dram Type= 6, Freq= 0, CH_0, rank 0
6364 10:03:46.846876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6365 10:03:46.847014 ==
6366 10:03:46.847099 DQS Delay:
6367 10:03:46.850430 DQS0 = 35, DQS1 = 59
6368 10:03:46.850562 DQM Delay:
6369 10:03:46.853667 DQM0 = 4, DQM1 = 18
6370 10:03:46.853860 DQ Delay:
6371 10:03:46.856765 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6372 10:03:46.860189 DQ4 =0, DQ5 =0, DQ6 =16, DQ7 =16
6373 10:03:46.863875 DQ8 =8, DQ9 =0, DQ10 =24, DQ11 =16
6374 10:03:46.866665 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6375 10:03:46.866873
6376 10:03:46.866983
6377 10:03:46.867081 ==
6378 10:03:46.870077 Dram Type= 6, Freq= 0, CH_0, rank 0
6379 10:03:46.873128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6380 10:03:46.873360 ==
6381 10:03:46.873521
6382 10:03:46.873648
6383 10:03:46.876426 TX Vref Scan disable
6384 10:03:46.876617 == TX Byte 0 ==
6385 10:03:46.882872 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6386 10:03:46.886545 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6387 10:03:46.886868 == TX Byte 1 ==
6388 10:03:46.893639 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6389 10:03:46.897033 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6390 10:03:46.897510 ==
6391 10:03:46.900144 Dram Type= 6, Freq= 0, CH_0, rank 0
6392 10:03:46.903383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6393 10:03:46.903952 ==
6394 10:03:46.904315
6395 10:03:46.904652
6396 10:03:46.906679 TX Vref Scan disable
6397 10:03:46.909682 == TX Byte 0 ==
6398 10:03:46.912829 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6399 10:03:46.916406 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6400 10:03:46.916964 == TX Byte 1 ==
6401 10:03:46.923170 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6402 10:03:46.926214 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6403 10:03:46.926665
6404 10:03:46.926990 [DATLAT]
6405 10:03:46.929930 Freq=400, CH0 RK0
6406 10:03:46.930505
6407 10:03:46.930879 DATLAT Default: 0xf
6408 10:03:46.932494 0, 0xFFFF, sum = 0
6409 10:03:46.932910 1, 0xFFFF, sum = 0
6410 10:03:46.936560 2, 0xFFFF, sum = 0
6411 10:03:46.940108 3, 0xFFFF, sum = 0
6412 10:03:46.940664 4, 0xFFFF, sum = 0
6413 10:03:46.943193 5, 0xFFFF, sum = 0
6414 10:03:46.943705 6, 0xFFFF, sum = 0
6415 10:03:46.946149 7, 0xFFFF, sum = 0
6416 10:03:46.946744 8, 0xFFFF, sum = 0
6417 10:03:46.949426 9, 0xFFFF, sum = 0
6418 10:03:46.949977 10, 0xFFFF, sum = 0
6419 10:03:46.952756 11, 0xFFFF, sum = 0
6420 10:03:46.953310 12, 0xFFFF, sum = 0
6421 10:03:46.956058 13, 0x0, sum = 1
6422 10:03:46.956616 14, 0x0, sum = 2
6423 10:03:46.959229 15, 0x0, sum = 3
6424 10:03:46.959787 16, 0x0, sum = 4
6425 10:03:46.962410 best_step = 14
6426 10:03:46.963032
6427 10:03:46.963403 ==
6428 10:03:46.966081 Dram Type= 6, Freq= 0, CH_0, rank 0
6429 10:03:46.968938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6430 10:03:46.969494 ==
6431 10:03:46.972548 RX Vref Scan: 1
6432 10:03:46.973133
6433 10:03:46.973497 RX Vref 0 -> 0, step: 1
6434 10:03:46.973835
6435 10:03:46.975747 RX Delay -359 -> 252, step: 8
6436 10:03:46.976199
6437 10:03:46.978943 Set Vref, RX VrefLevel [Byte0]: 54
6438 10:03:46.982054 [Byte1]: 58
6439 10:03:46.986924
6440 10:03:46.987449 Final RX Vref Byte 0 = 54 to rank0
6441 10:03:46.990197 Final RX Vref Byte 1 = 58 to rank0
6442 10:03:46.993645 Final RX Vref Byte 0 = 54 to rank1
6443 10:03:46.996430 Final RX Vref Byte 1 = 58 to rank1==
6444 10:03:46.999988 Dram Type= 6, Freq= 0, CH_0, rank 0
6445 10:03:47.006555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6446 10:03:47.007136 ==
6447 10:03:47.007646 DQS Delay:
6448 10:03:47.009657 DQS0 = 44, DQS1 = 60
6449 10:03:47.010083 DQM Delay:
6450 10:03:47.012629 DQM0 = 11, DQM1 = 17
6451 10:03:47.013112 DQ Delay:
6452 10:03:47.016367 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =4
6453 10:03:47.019584 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6454 10:03:47.022797 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =12
6455 10:03:47.026495 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6456 10:03:47.027092
6457 10:03:47.027426
6458 10:03:47.033162 [DQSOSCAuto] RK0, (LSB)MR18= 0x978a, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
6459 10:03:47.036127 CH0 RK0: MR19=C0C, MR18=978A
6460 10:03:47.042557 CH0_RK0: MR19=0xC0C, MR18=0x978A, DQSOSC=390, MR23=63, INC=388, DEC=258
6461 10:03:47.043073 ==
6462 10:03:47.046037 Dram Type= 6, Freq= 0, CH_0, rank 1
6463 10:03:47.049351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6464 10:03:47.049867 ==
6465 10:03:47.052914 [Gating] SW mode calibration
6466 10:03:47.059221 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6467 10:03:47.065934 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6468 10:03:47.069210 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6469 10:03:47.075861 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6470 10:03:47.078792 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6471 10:03:47.081989 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6472 10:03:47.085416 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6473 10:03:47.092716 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6474 10:03:47.095139 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6475 10:03:47.101854 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6476 10:03:47.105061 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6477 10:03:47.108294 Total UI for P1: 0, mck2ui 16
6478 10:03:47.111762 best dqsien dly found for B0: ( 0, 14, 24)
6479 10:03:47.114938 Total UI for P1: 0, mck2ui 16
6480 10:03:47.118689 best dqsien dly found for B1: ( 0, 14, 24)
6481 10:03:47.121311 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6482 10:03:47.124684 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6483 10:03:47.125233
6484 10:03:47.128824 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6485 10:03:47.131978 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6486 10:03:47.134799 [Gating] SW calibration Done
6487 10:03:47.135248 ==
6488 10:03:47.138234 Dram Type= 6, Freq= 0, CH_0, rank 1
6489 10:03:47.142189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6490 10:03:47.144993 ==
6491 10:03:47.145563 RX Vref Scan: 0
6492 10:03:47.145930
6493 10:03:47.147969 RX Vref 0 -> 0, step: 1
6494 10:03:47.148421
6495 10:03:47.151725 RX Delay -410 -> 252, step: 16
6496 10:03:47.154885 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6497 10:03:47.158151 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6498 10:03:47.160872 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6499 10:03:47.167921 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6500 10:03:47.171076 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6501 10:03:47.174484 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6502 10:03:47.177918 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6503 10:03:47.184213 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6504 10:03:47.187328 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6505 10:03:47.190660 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6506 10:03:47.196903 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6507 10:03:47.200303 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6508 10:03:47.204132 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6509 10:03:47.206759 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6510 10:03:47.213457 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6511 10:03:47.216557 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6512 10:03:47.216969 ==
6513 10:03:47.219989 Dram Type= 6, Freq= 0, CH_0, rank 1
6514 10:03:47.223983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6515 10:03:47.224526 ==
6516 10:03:47.226632 DQS Delay:
6517 10:03:47.227041 DQS0 = 35, DQS1 = 59
6518 10:03:47.229822 DQM Delay:
6519 10:03:47.230230 DQM0 = 7, DQM1 = 16
6520 10:03:47.230613 DQ Delay:
6521 10:03:47.233680 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6522 10:03:47.236761 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6523 10:03:47.240317 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6524 10:03:47.243502 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6525 10:03:47.243965
6526 10:03:47.244306
6527 10:03:47.244610 ==
6528 10:03:47.246625 Dram Type= 6, Freq= 0, CH_0, rank 1
6529 10:03:47.253616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6530 10:03:47.254125 ==
6531 10:03:47.254498
6532 10:03:47.254806
6533 10:03:47.255094 TX Vref Scan disable
6534 10:03:47.256669 == TX Byte 0 ==
6535 10:03:47.259774 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6536 10:03:47.262971 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6537 10:03:47.266698 == TX Byte 1 ==
6538 10:03:47.269871 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6539 10:03:47.273045 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6540 10:03:47.273550 ==
6541 10:03:47.276119 Dram Type= 6, Freq= 0, CH_0, rank 1
6542 10:03:47.282883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6543 10:03:47.283390 ==
6544 10:03:47.283719
6545 10:03:47.284023
6546 10:03:47.284311 TX Vref Scan disable
6547 10:03:47.286009 == TX Byte 0 ==
6548 10:03:47.289649 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6549 10:03:47.292805 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6550 10:03:47.296086 == TX Byte 1 ==
6551 10:03:47.299460 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6552 10:03:47.302631 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6553 10:03:47.303154
6554 10:03:47.306378 [DATLAT]
6555 10:03:47.306987 Freq=400, CH0 RK1
6556 10:03:47.307364
6557 10:03:47.309304 DATLAT Default: 0xe
6558 10:03:47.309805 0, 0xFFFF, sum = 0
6559 10:03:47.312332 1, 0xFFFF, sum = 0
6560 10:03:47.312767 2, 0xFFFF, sum = 0
6561 10:03:47.315989 3, 0xFFFF, sum = 0
6562 10:03:47.316424 4, 0xFFFF, sum = 0
6563 10:03:47.318994 5, 0xFFFF, sum = 0
6564 10:03:47.319413 6, 0xFFFF, sum = 0
6565 10:03:47.322362 7, 0xFFFF, sum = 0
6566 10:03:47.325797 8, 0xFFFF, sum = 0
6567 10:03:47.326213 9, 0xFFFF, sum = 0
6568 10:03:47.328608 10, 0xFFFF, sum = 0
6569 10:03:47.329027 11, 0xFFFF, sum = 0
6570 10:03:47.332125 12, 0xFFFF, sum = 0
6571 10:03:47.332539 13, 0x0, sum = 1
6572 10:03:47.335180 14, 0x0, sum = 2
6573 10:03:47.335600 15, 0x0, sum = 3
6574 10:03:47.338430 16, 0x0, sum = 4
6575 10:03:47.338849 best_step = 14
6576 10:03:47.339174
6577 10:03:47.339481 ==
6578 10:03:47.341947 Dram Type= 6, Freq= 0, CH_0, rank 1
6579 10:03:47.346052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6580 10:03:47.348436 ==
6581 10:03:47.348849 RX Vref Scan: 0
6582 10:03:47.349175
6583 10:03:47.352102 RX Vref 0 -> 0, step: 1
6584 10:03:47.352610
6585 10:03:47.354925 RX Delay -359 -> 252, step: 8
6586 10:03:47.361851 iDelay=217, Bit 0, Center -36 (-271 ~ 200) 472
6587 10:03:47.365120 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6588 10:03:47.368498 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6589 10:03:47.371501 iDelay=217, Bit 3, Center -36 (-271 ~ 200) 472
6590 10:03:47.378316 iDelay=217, Bit 4, Center -32 (-271 ~ 208) 480
6591 10:03:47.381778 iDelay=217, Bit 5, Center -44 (-279 ~ 192) 472
6592 10:03:47.385139 iDelay=217, Bit 6, Center -24 (-263 ~ 216) 480
6593 10:03:47.388068 iDelay=217, Bit 7, Center -28 (-263 ~ 208) 472
6594 10:03:47.395002 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6595 10:03:47.398540 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6596 10:03:47.401648 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6597 10:03:47.405058 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6598 10:03:47.411212 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6599 10:03:47.414708 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6600 10:03:47.417674 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6601 10:03:47.421186 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6602 10:03:47.425427 ==
6603 10:03:47.427606 Dram Type= 6, Freq= 0, CH_0, rank 1
6604 10:03:47.430809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6605 10:03:47.431226 ==
6606 10:03:47.431550 DQS Delay:
6607 10:03:47.434679 DQS0 = 44, DQS1 = 60
6608 10:03:47.435091 DQM Delay:
6609 10:03:47.437461 DQM0 = 10, DQM1 = 15
6610 10:03:47.437868 DQ Delay:
6611 10:03:47.440879 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6612 10:03:47.443808 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6613 10:03:47.447187 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6614 10:03:47.450598 DQ12 =20, DQ13 =24, DQ14 =24, DQ15 =24
6615 10:03:47.451012
6616 10:03:47.451335
6617 10:03:47.457276 [DQSOSCAuto] RK1, (LSB)MR18= 0x8781, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
6618 10:03:47.460398 CH0 RK1: MR19=C0C, MR18=8781
6619 10:03:47.467084 CH0_RK1: MR19=0xC0C, MR18=0x8781, DQSOSC=392, MR23=63, INC=384, DEC=256
6620 10:03:47.470364 [RxdqsGatingPostProcess] freq 400
6621 10:03:47.477080 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6622 10:03:47.480070 best DQS0 dly(2T, 0.5T) = (0, 10)
6623 10:03:47.480494 best DQS1 dly(2T, 0.5T) = (0, 10)
6624 10:03:47.483443 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6625 10:03:47.487239 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6626 10:03:47.490174 best DQS0 dly(2T, 0.5T) = (0, 10)
6627 10:03:47.493679 best DQS1 dly(2T, 0.5T) = (0, 10)
6628 10:03:47.497099 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6629 10:03:47.500154 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6630 10:03:47.503449 Pre-setting of DQS Precalculation
6631 10:03:47.510115 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6632 10:03:47.510721 ==
6633 10:03:47.512923 Dram Type= 6, Freq= 0, CH_1, rank 0
6634 10:03:47.516253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6635 10:03:47.516710 ==
6636 10:03:47.523320 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6637 10:03:47.529503 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6638 10:03:47.532841 [CA 0] Center 36 (8~64) winsize 57
6639 10:03:47.533345 [CA 1] Center 36 (8~64) winsize 57
6640 10:03:47.535997 [CA 2] Center 36 (8~64) winsize 57
6641 10:03:47.539529 [CA 3] Center 36 (8~64) winsize 57
6642 10:03:47.542638 [CA 4] Center 36 (8~64) winsize 57
6643 10:03:47.546113 [CA 5] Center 36 (8~64) winsize 57
6644 10:03:47.546557
6645 10:03:47.548970 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6646 10:03:47.549382
6647 10:03:47.555824 [CATrainingPosCal] consider 1 rank data
6648 10:03:47.556328 u2DelayCellTimex100 = 270/100 ps
6649 10:03:47.562687 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6650 10:03:47.566235 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6651 10:03:47.569466 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6652 10:03:47.572546 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6653 10:03:47.576055 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6654 10:03:47.578853 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6655 10:03:47.579267
6656 10:03:47.582623 CA PerBit enable=1, Macro0, CA PI delay=36
6657 10:03:47.583034
6658 10:03:47.585776 [CBTSetCACLKResult] CA Dly = 36
6659 10:03:47.589300 CS Dly: 1 (0~32)
6660 10:03:47.589802 ==
6661 10:03:47.592716 Dram Type= 6, Freq= 0, CH_1, rank 1
6662 10:03:47.595389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6663 10:03:47.595807 ==
6664 10:03:47.602856 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6665 10:03:47.605350 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6666 10:03:47.609025 [CA 0] Center 36 (8~64) winsize 57
6667 10:03:47.612302 [CA 1] Center 36 (8~64) winsize 57
6668 10:03:47.615200 [CA 2] Center 36 (8~64) winsize 57
6669 10:03:47.618349 [CA 3] Center 36 (8~64) winsize 57
6670 10:03:47.621842 [CA 4] Center 36 (8~64) winsize 57
6671 10:03:47.625008 [CA 5] Center 36 (8~64) winsize 57
6672 10:03:47.625542
6673 10:03:47.628404 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6674 10:03:47.628817
6675 10:03:47.631880 [CATrainingPosCal] consider 2 rank data
6676 10:03:47.634587 u2DelayCellTimex100 = 270/100 ps
6677 10:03:47.638006 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6678 10:03:47.644792 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6679 10:03:47.648180 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6680 10:03:47.650928 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6681 10:03:47.654610 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6682 10:03:47.658383 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6683 10:03:47.658798
6684 10:03:47.660807 CA PerBit enable=1, Macro0, CA PI delay=36
6685 10:03:47.661216
6686 10:03:47.664746 [CBTSetCACLKResult] CA Dly = 36
6687 10:03:47.667281 CS Dly: 1 (0~32)
6688 10:03:47.667784
6689 10:03:47.671069 ----->DramcWriteLeveling(PI) begin...
6690 10:03:47.671572 ==
6691 10:03:47.674399 Dram Type= 6, Freq= 0, CH_1, rank 0
6692 10:03:47.677719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6693 10:03:47.678228 ==
6694 10:03:47.680862 Write leveling (Byte 0): 40 => 8
6695 10:03:47.684481 Write leveling (Byte 1): 40 => 8
6696 10:03:47.687386 DramcWriteLeveling(PI) end<-----
6697 10:03:47.688112
6698 10:03:47.688710 ==
6699 10:03:47.690725 Dram Type= 6, Freq= 0, CH_1, rank 0
6700 10:03:47.694426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6701 10:03:47.694913 ==
6702 10:03:47.697233 [Gating] SW mode calibration
6703 10:03:47.703959 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6704 10:03:47.710557 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6705 10:03:47.713661 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6706 10:03:47.717032 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6707 10:03:47.723530 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6708 10:03:47.727860 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6709 10:03:47.730211 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6710 10:03:47.737721 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6711 10:03:47.740266 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6712 10:03:47.743523 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6713 10:03:47.750243 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6714 10:03:47.753934 Total UI for P1: 0, mck2ui 16
6715 10:03:47.757382 best dqsien dly found for B0: ( 0, 14, 24)
6716 10:03:47.757896 Total UI for P1: 0, mck2ui 16
6717 10:03:47.763466 best dqsien dly found for B1: ( 0, 14, 24)
6718 10:03:47.766940 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6719 10:03:47.770101 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6720 10:03:47.770651
6721 10:03:47.773335 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6722 10:03:47.777143 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6723 10:03:47.779508 [Gating] SW calibration Done
6724 10:03:47.779926 ==
6725 10:03:47.782982 Dram Type= 6, Freq= 0, CH_1, rank 0
6726 10:03:47.785918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6727 10:03:47.786386 ==
6728 10:03:47.789918 RX Vref Scan: 0
6729 10:03:47.790455
6730 10:03:47.793686 RX Vref 0 -> 0, step: 1
6731 10:03:47.794189
6732 10:03:47.794553 RX Delay -410 -> 252, step: 16
6733 10:03:47.800199 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6734 10:03:47.802803 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6735 10:03:47.806732 iDelay=230, Bit 2, Center -43 (-282 ~ 197) 480
6736 10:03:47.812694 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6737 10:03:47.816359 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6738 10:03:47.819026 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6739 10:03:47.822934 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6740 10:03:47.829442 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6741 10:03:47.832871 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6742 10:03:47.836018 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6743 10:03:47.838986 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6744 10:03:47.845618 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6745 10:03:47.849199 iDelay=230, Bit 12, Center -19 (-266 ~ 229) 496
6746 10:03:47.852220 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6747 10:03:47.858918 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6748 10:03:47.862340 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6749 10:03:47.862994 ==
6750 10:03:47.865397 Dram Type= 6, Freq= 0, CH_1, rank 0
6751 10:03:47.869013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6752 10:03:47.869564 ==
6753 10:03:47.872526 DQS Delay:
6754 10:03:47.872974 DQS0 = 43, DQS1 = 51
6755 10:03:47.873331 DQM Delay:
6756 10:03:47.874924 DQM0 = 13, DQM1 = 14
6757 10:03:47.875371 DQ Delay:
6758 10:03:47.878445 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6759 10:03:47.881790 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6760 10:03:47.885499 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6761 10:03:47.888693 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =16
6762 10:03:47.889194
6763 10:03:47.889520
6764 10:03:47.889904 ==
6765 10:03:47.891949 Dram Type= 6, Freq= 0, CH_1, rank 0
6766 10:03:47.895170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6767 10:03:47.898533 ==
6768 10:03:47.898936
6769 10:03:47.899256
6770 10:03:47.899557 TX Vref Scan disable
6771 10:03:47.902433 == TX Byte 0 ==
6772 10:03:47.904608 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6773 10:03:47.908128 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6774 10:03:47.911336 == TX Byte 1 ==
6775 10:03:47.914972 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6776 10:03:47.917810 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6777 10:03:47.918247 ==
6778 10:03:47.921603 Dram Type= 6, Freq= 0, CH_1, rank 0
6779 10:03:47.927603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6780 10:03:47.928021 ==
6781 10:03:47.928348
6782 10:03:47.928649
6783 10:03:47.928945 TX Vref Scan disable
6784 10:03:47.931037 == TX Byte 0 ==
6785 10:03:47.934501 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6786 10:03:47.937659 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6787 10:03:47.941133 == TX Byte 1 ==
6788 10:03:47.944328 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6789 10:03:47.947262 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6790 10:03:47.950912
6791 10:03:47.951412 [DATLAT]
6792 10:03:47.951744 Freq=400, CH1 RK0
6793 10:03:47.952056
6794 10:03:47.954390 DATLAT Default: 0xf
6795 10:03:47.954889 0, 0xFFFF, sum = 0
6796 10:03:47.957705 1, 0xFFFF, sum = 0
6797 10:03:47.958221 2, 0xFFFF, sum = 0
6798 10:03:47.961173 3, 0xFFFF, sum = 0
6799 10:03:47.963746 4, 0xFFFF, sum = 0
6800 10:03:47.964168 5, 0xFFFF, sum = 0
6801 10:03:47.967048 6, 0xFFFF, sum = 0
6802 10:03:47.967465 7, 0xFFFF, sum = 0
6803 10:03:47.970654 8, 0xFFFF, sum = 0
6804 10:03:47.971167 9, 0xFFFF, sum = 0
6805 10:03:47.973997 10, 0xFFFF, sum = 0
6806 10:03:47.974555 11, 0xFFFF, sum = 0
6807 10:03:47.977347 12, 0xFFFF, sum = 0
6808 10:03:47.977862 13, 0x0, sum = 1
6809 10:03:47.980801 14, 0x0, sum = 2
6810 10:03:47.981292 15, 0x0, sum = 3
6811 10:03:47.984299 16, 0x0, sum = 4
6812 10:03:47.984806 best_step = 14
6813 10:03:47.985129
6814 10:03:47.985426 ==
6815 10:03:47.987037 Dram Type= 6, Freq= 0, CH_1, rank 0
6816 10:03:47.990526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6817 10:03:47.994036 ==
6818 10:03:47.994575 RX Vref Scan: 1
6819 10:03:47.994902
6820 10:03:47.997340 RX Vref 0 -> 0, step: 1
6821 10:03:47.997884
6822 10:03:48.000208 RX Delay -343 -> 252, step: 8
6823 10:03:48.000746
6824 10:03:48.003557 Set Vref, RX VrefLevel [Byte0]: 52
6825 10:03:48.006686 [Byte1]: 53
6826 10:03:48.007193
6827 10:03:48.010605 Final RX Vref Byte 0 = 52 to rank0
6828 10:03:48.013191 Final RX Vref Byte 1 = 53 to rank0
6829 10:03:48.016733 Final RX Vref Byte 0 = 52 to rank1
6830 10:03:48.019758 Final RX Vref Byte 1 = 53 to rank1==
6831 10:03:48.022854 Dram Type= 6, Freq= 0, CH_1, rank 0
6832 10:03:48.026340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6833 10:03:48.029594 ==
6834 10:03:48.030090 DQS Delay:
6835 10:03:48.030467 DQS0 = 44, DQS1 = 52
6836 10:03:48.032909 DQM Delay:
6837 10:03:48.033313 DQM0 = 11, DQM1 = 9
6838 10:03:48.036232 DQ Delay:
6839 10:03:48.036636 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
6840 10:03:48.039568 DQ4 =4, DQ5 =20, DQ6 =24, DQ7 =4
6841 10:03:48.042788 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6842 10:03:48.046249 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6843 10:03:48.046854
6844 10:03:48.047185
6845 10:03:48.056054 [DQSOSCAuto] RK0, (LSB)MR18= 0x6a91, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 396 ps
6846 10:03:48.059102 CH1 RK0: MR19=C0C, MR18=6A91
6847 10:03:48.065879 CH1_RK0: MR19=0xC0C, MR18=0x6A91, DQSOSC=391, MR23=63, INC=386, DEC=257
6848 10:03:48.066444 ==
6849 10:03:48.069512 Dram Type= 6, Freq= 0, CH_1, rank 1
6850 10:03:48.072616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6851 10:03:48.073032 ==
6852 10:03:48.075626 [Gating] SW mode calibration
6853 10:03:48.082228 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6854 10:03:48.085700 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6855 10:03:48.092551 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6856 10:03:48.096077 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6857 10:03:48.098874 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6858 10:03:48.105643 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6859 10:03:48.109057 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6860 10:03:48.115191 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6861 10:03:48.118816 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6862 10:03:48.121531 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6863 10:03:48.128393 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6864 10:03:48.128897 Total UI for P1: 0, mck2ui 16
6865 10:03:48.131928 best dqsien dly found for B0: ( 0, 14, 24)
6866 10:03:48.134614 Total UI for P1: 0, mck2ui 16
6867 10:03:48.138119 best dqsien dly found for B1: ( 0, 14, 24)
6868 10:03:48.145107 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6869 10:03:48.147940 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6870 10:03:48.148355
6871 10:03:48.151752 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6872 10:03:48.154567 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6873 10:03:48.158180 [Gating] SW calibration Done
6874 10:03:48.158734 ==
6875 10:03:48.161533 Dram Type= 6, Freq= 0, CH_1, rank 1
6876 10:03:48.164384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6877 10:03:48.164942 ==
6878 10:03:48.167752 RX Vref Scan: 0
6879 10:03:48.168254
6880 10:03:48.168587 RX Vref 0 -> 0, step: 1
6881 10:03:48.168896
6882 10:03:48.171479 RX Delay -410 -> 252, step: 16
6883 10:03:48.177567 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6884 10:03:48.181832 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6885 10:03:48.184308 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6886 10:03:48.187250 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6887 10:03:48.194104 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6888 10:03:48.197592 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6889 10:03:48.200796 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6890 10:03:48.204275 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6891 10:03:48.210370 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6892 10:03:48.214026 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6893 10:03:48.217290 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6894 10:03:48.224019 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6895 10:03:48.226427 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6896 10:03:48.230211 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6897 10:03:48.233064 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6898 10:03:48.240514 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6899 10:03:48.241022 ==
6900 10:03:48.243676 Dram Type= 6, Freq= 0, CH_1, rank 1
6901 10:03:48.246679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6902 10:03:48.247090 ==
6903 10:03:48.247416 DQS Delay:
6904 10:03:48.250226 DQS0 = 43, DQS1 = 51
6905 10:03:48.250662 DQM Delay:
6906 10:03:48.253019 DQM0 = 9, DQM1 = 14
6907 10:03:48.253424 DQ Delay:
6908 10:03:48.257074 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =8
6909 10:03:48.259964 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6910 10:03:48.263773 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6911 10:03:48.266330 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6912 10:03:48.267038
6913 10:03:48.267402
6914 10:03:48.267708 ==
6915 10:03:48.269717 Dram Type= 6, Freq= 0, CH_1, rank 1
6916 10:03:48.273240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6917 10:03:48.273752 ==
6918 10:03:48.274080
6919 10:03:48.274442
6920 10:03:48.276469 TX Vref Scan disable
6921 10:03:48.279937 == TX Byte 0 ==
6922 10:03:48.282863 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6923 10:03:48.286463 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6924 10:03:48.289705 == TX Byte 1 ==
6925 10:03:48.293062 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6926 10:03:48.295932 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6927 10:03:48.296437 ==
6928 10:03:48.300053 Dram Type= 6, Freq= 0, CH_1, rank 1
6929 10:03:48.302526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6930 10:03:48.306142 ==
6931 10:03:48.306691
6932 10:03:48.307039
6933 10:03:48.307342 TX Vref Scan disable
6934 10:03:48.309329 == TX Byte 0 ==
6935 10:03:48.312367 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6936 10:03:48.315450 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6937 10:03:48.318713 == TX Byte 1 ==
6938 10:03:48.322623 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6939 10:03:48.325682 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6940 10:03:48.326097
6941 10:03:48.329706 [DATLAT]
6942 10:03:48.330208 Freq=400, CH1 RK1
6943 10:03:48.330600
6944 10:03:48.332163 DATLAT Default: 0xe
6945 10:03:48.332571 0, 0xFFFF, sum = 0
6946 10:03:48.335464 1, 0xFFFF, sum = 0
6947 10:03:48.335879 2, 0xFFFF, sum = 0
6948 10:03:48.338443 3, 0xFFFF, sum = 0
6949 10:03:48.338889 4, 0xFFFF, sum = 0
6950 10:03:48.342075 5, 0xFFFF, sum = 0
6951 10:03:48.342530 6, 0xFFFF, sum = 0
6952 10:03:48.345807 7, 0xFFFF, sum = 0
6953 10:03:48.346368 8, 0xFFFF, sum = 0
6954 10:03:48.348346 9, 0xFFFF, sum = 0
6955 10:03:48.348809 10, 0xFFFF, sum = 0
6956 10:03:48.351912 11, 0xFFFF, sum = 0
6957 10:03:48.355566 12, 0xFFFF, sum = 0
6958 10:03:48.356079 13, 0x0, sum = 1
6959 10:03:48.356414 14, 0x0, sum = 2
6960 10:03:48.358426 15, 0x0, sum = 3
6961 10:03:48.358848 16, 0x0, sum = 4
6962 10:03:48.362320 best_step = 14
6963 10:03:48.362821
6964 10:03:48.363149 ==
6965 10:03:48.365016 Dram Type= 6, Freq= 0, CH_1, rank 1
6966 10:03:48.368492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6967 10:03:48.368906 ==
6968 10:03:48.371389 RX Vref Scan: 0
6969 10:03:48.371801
6970 10:03:48.372130 RX Vref 0 -> 0, step: 1
6971 10:03:48.375003
6972 10:03:48.375416 RX Delay -343 -> 252, step: 8
6973 10:03:48.383230 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6974 10:03:48.386600 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6975 10:03:48.390199 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6976 10:03:48.396655 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6977 10:03:48.399791 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6978 10:03:48.402939 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6979 10:03:48.406522 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6980 10:03:48.413169 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6981 10:03:48.416635 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6982 10:03:48.419226 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6983 10:03:48.422619 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6984 10:03:48.429374 iDelay=217, Bit 11, Center -48 (-287 ~ 192) 480
6985 10:03:48.432911 iDelay=217, Bit 12, Center -32 (-271 ~ 208) 480
6986 10:03:48.436575 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6987 10:03:48.442087 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6988 10:03:48.446334 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6989 10:03:48.446955 ==
6990 10:03:48.449123 Dram Type= 6, Freq= 0, CH_1, rank 1
6991 10:03:48.452189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6992 10:03:48.452730 ==
6993 10:03:48.455519 DQS Delay:
6994 10:03:48.456022 DQS0 = 48, DQS1 = 52
6995 10:03:48.456350 DQM Delay:
6996 10:03:48.459127 DQM0 = 11, DQM1 = 10
6997 10:03:48.459542 DQ Delay:
6998 10:03:48.462512 DQ0 =12, DQ1 =8, DQ2 =0, DQ3 =8
6999 10:03:48.465445 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =8
7000 10:03:48.468796 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
7001 10:03:48.472070 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
7002 10:03:48.472579
7003 10:03:48.472913
7004 10:03:48.482184 [DQSOSCAuto] RK1, (LSB)MR18= 0x76ae, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 394 ps
7005 10:03:48.482809 CH1 RK1: MR19=C0C, MR18=76AE
7006 10:03:48.488432 CH1_RK1: MR19=0xC0C, MR18=0x76AE, DQSOSC=388, MR23=63, INC=392, DEC=261
7007 10:03:48.491720 [RxdqsGatingPostProcess] freq 400
7008 10:03:48.498647 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7009 10:03:48.502073 best DQS0 dly(2T, 0.5T) = (0, 10)
7010 10:03:48.504902 best DQS1 dly(2T, 0.5T) = (0, 10)
7011 10:03:48.508301 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7012 10:03:48.512002 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7013 10:03:48.515218 best DQS0 dly(2T, 0.5T) = (0, 10)
7014 10:03:48.518522 best DQS1 dly(2T, 0.5T) = (0, 10)
7015 10:03:48.521713 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7016 10:03:48.525024 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7017 10:03:48.525577 Pre-setting of DQS Precalculation
7018 10:03:48.530890 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7019 10:03:48.538189 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7020 10:03:48.544459 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7021 10:03:48.544966
7022 10:03:48.545293
7023 10:03:48.547947 [Calibration Summary] 800 Mbps
7024 10:03:48.550891 CH 0, Rank 0
7025 10:03:48.551306 SW Impedance : PASS
7026 10:03:48.554561 DUTY Scan : NO K
7027 10:03:48.557507 ZQ Calibration : PASS
7028 10:03:48.557926 Jitter Meter : NO K
7029 10:03:48.561143 CBT Training : PASS
7030 10:03:48.564772 Write leveling : PASS
7031 10:03:48.565288 RX DQS gating : PASS
7032 10:03:48.568151 RX DQ/DQS(RDDQC) : PASS
7033 10:03:48.570875 TX DQ/DQS : PASS
7034 10:03:48.571290 RX DATLAT : PASS
7035 10:03:48.574409 RX DQ/DQS(Engine): PASS
7036 10:03:48.574934 TX OE : NO K
7037 10:03:48.577416 All Pass.
7038 10:03:48.577912
7039 10:03:48.578245 CH 0, Rank 1
7040 10:03:48.580527 SW Impedance : PASS
7041 10:03:48.580936 DUTY Scan : NO K
7042 10:03:48.584178 ZQ Calibration : PASS
7043 10:03:48.587494 Jitter Meter : NO K
7044 10:03:48.587997 CBT Training : PASS
7045 10:03:48.590712 Write leveling : NO K
7046 10:03:48.594334 RX DQS gating : PASS
7047 10:03:48.594841 RX DQ/DQS(RDDQC) : PASS
7048 10:03:48.597630 TX DQ/DQS : PASS
7049 10:03:48.600577 RX DATLAT : PASS
7050 10:03:48.601082 RX DQ/DQS(Engine): PASS
7051 10:03:48.603964 TX OE : NO K
7052 10:03:48.604378 All Pass.
7053 10:03:48.604705
7054 10:03:48.607233 CH 1, Rank 0
7055 10:03:48.607738 SW Impedance : PASS
7056 10:03:48.610835 DUTY Scan : NO K
7057 10:03:48.613929 ZQ Calibration : PASS
7058 10:03:48.614494 Jitter Meter : NO K
7059 10:03:48.616905 CBT Training : PASS
7060 10:03:48.620155 Write leveling : PASS
7061 10:03:48.620583 RX DQS gating : PASS
7062 10:03:48.623579 RX DQ/DQS(RDDQC) : PASS
7063 10:03:48.626592 TX DQ/DQS : PASS
7064 10:03:48.627177 RX DATLAT : PASS
7065 10:03:48.630191 RX DQ/DQS(Engine): PASS
7066 10:03:48.633233 TX OE : NO K
7067 10:03:48.633739 All Pass.
7068 10:03:48.634065
7069 10:03:48.634573 CH 1, Rank 1
7070 10:03:48.636750 SW Impedance : PASS
7071 10:03:48.640579 DUTY Scan : NO K
7072 10:03:48.641218 ZQ Calibration : PASS
7073 10:03:48.643294 Jitter Meter : NO K
7074 10:03:48.647232 CBT Training : PASS
7075 10:03:48.647737 Write leveling : NO K
7076 10:03:48.649848 RX DQS gating : PASS
7077 10:03:48.650291 RX DQ/DQS(RDDQC) : PASS
7078 10:03:48.653921 TX DQ/DQS : PASS
7079 10:03:48.657243 RX DATLAT : PASS
7080 10:03:48.657755 RX DQ/DQS(Engine): PASS
7081 10:03:48.660025 TX OE : NO K
7082 10:03:48.660533 All Pass.
7083 10:03:48.660864
7084 10:03:48.663427 DramC Write-DBI off
7085 10:03:48.666321 PER_BANK_REFRESH: Hybrid Mode
7086 10:03:48.666734 TX_TRACKING: ON
7087 10:03:48.676604 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7088 10:03:48.679859 [FAST_K] Save calibration result to emmc
7089 10:03:48.683019 dramc_set_vcore_voltage set vcore to 725000
7090 10:03:48.686157 Read voltage for 1600, 0
7091 10:03:48.686700 Vio18 = 0
7092 10:03:48.689665 Vcore = 725000
7093 10:03:48.690164 Vdram = 0
7094 10:03:48.690560 Vddq = 0
7095 10:03:48.690871 Vmddr = 0
7096 10:03:48.695976 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7097 10:03:48.702639 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7098 10:03:48.703150 MEM_TYPE=3, freq_sel=13
7099 10:03:48.706565 sv_algorithm_assistance_LP4_3733
7100 10:03:48.712528 ============ PULL DRAM RESETB DOWN ============
7101 10:03:48.715779 ========== PULL DRAM RESETB DOWN end =========
7102 10:03:48.719027 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7103 10:03:48.722591 ===================================
7104 10:03:48.725519 LPDDR4 DRAM CONFIGURATION
7105 10:03:48.728970 ===================================
7106 10:03:48.729514 EX_ROW_EN[0] = 0x0
7107 10:03:48.732218 EX_ROW_EN[1] = 0x0
7108 10:03:48.735771 LP4Y_EN = 0x0
7109 10:03:48.736184 WORK_FSP = 0x1
7110 10:03:48.738778 WL = 0x5
7111 10:03:48.739187 RL = 0x5
7112 10:03:48.742114 BL = 0x2
7113 10:03:48.742569 RPST = 0x0
7114 10:03:48.745737 RD_PRE = 0x0
7115 10:03:48.746402 WR_PRE = 0x1
7116 10:03:48.748929 WR_PST = 0x1
7117 10:03:48.749476 DBI_WR = 0x0
7118 10:03:48.751852 DBI_RD = 0x0
7119 10:03:48.752260 OTF = 0x1
7120 10:03:48.755059 ===================================
7121 10:03:48.758779 ===================================
7122 10:03:48.761973 ANA top config
7123 10:03:48.764954 ===================================
7124 10:03:48.768237 DLL_ASYNC_EN = 0
7125 10:03:48.768644 ALL_SLAVE_EN = 0
7126 10:03:48.771722 NEW_RANK_MODE = 1
7127 10:03:48.774904 DLL_IDLE_MODE = 1
7128 10:03:48.778409 LP45_APHY_COMB_EN = 1
7129 10:03:48.778823 TX_ODT_DIS = 0
7130 10:03:48.781567 NEW_8X_MODE = 1
7131 10:03:48.785338 ===================================
7132 10:03:48.788173 ===================================
7133 10:03:48.791450 data_rate = 3200
7134 10:03:48.794518 CKR = 1
7135 10:03:48.798100 DQ_P2S_RATIO = 8
7136 10:03:48.802021 ===================================
7137 10:03:48.804535 CA_P2S_RATIO = 8
7138 10:03:48.807775 DQ_CA_OPEN = 0
7139 10:03:48.808276 DQ_SEMI_OPEN = 0
7140 10:03:48.810930 CA_SEMI_OPEN = 0
7141 10:03:48.814459 CA_FULL_RATE = 0
7142 10:03:48.817942 DQ_CKDIV4_EN = 0
7143 10:03:48.821489 CA_CKDIV4_EN = 0
7144 10:03:48.824276 CA_PREDIV_EN = 0
7145 10:03:48.824775 PH8_DLY = 12
7146 10:03:48.827983 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7147 10:03:48.831106 DQ_AAMCK_DIV = 4
7148 10:03:48.834360 CA_AAMCK_DIV = 4
7149 10:03:48.837334 CA_ADMCK_DIV = 4
7150 10:03:48.840931 DQ_TRACK_CA_EN = 0
7151 10:03:48.844386 CA_PICK = 1600
7152 10:03:48.844903 CA_MCKIO = 1600
7153 10:03:48.847417 MCKIO_SEMI = 0
7154 10:03:48.850584 PLL_FREQ = 3068
7155 10:03:48.853979 DQ_UI_PI_RATIO = 32
7156 10:03:48.857768 CA_UI_PI_RATIO = 0
7157 10:03:48.860238 ===================================
7158 10:03:48.863708 ===================================
7159 10:03:48.867204 memory_type:LPDDR4
7160 10:03:48.867613 GP_NUM : 10
7161 10:03:48.870378 SRAM_EN : 1
7162 10:03:48.870792 MD32_EN : 0
7163 10:03:48.873717 ===================================
7164 10:03:48.877017 [ANA_INIT] >>>>>>>>>>>>>>
7165 10:03:48.880636 <<<<<< [CONFIGURE PHASE]: ANA_TX
7166 10:03:48.883598 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7167 10:03:48.886946 ===================================
7168 10:03:48.890305 data_rate = 3200,PCW = 0X7600
7169 10:03:48.894284 ===================================
7170 10:03:48.896818 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7171 10:03:48.903483 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7172 10:03:48.906705 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7173 10:03:48.913328 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7174 10:03:48.916843 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7175 10:03:48.919708 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7176 10:03:48.920257 [ANA_INIT] flow start
7177 10:03:48.923519 [ANA_INIT] PLL >>>>>>>>
7178 10:03:48.926484 [ANA_INIT] PLL <<<<<<<<
7179 10:03:48.929826 [ANA_INIT] MIDPI >>>>>>>>
7180 10:03:48.930231 [ANA_INIT] MIDPI <<<<<<<<
7181 10:03:48.933613 [ANA_INIT] DLL >>>>>>>>
7182 10:03:48.936338 [ANA_INIT] DLL <<<<<<<<
7183 10:03:48.936853 [ANA_INIT] flow end
7184 10:03:48.940267 ============ LP4 DIFF to SE enter ============
7185 10:03:48.946347 ============ LP4 DIFF to SE exit ============
7186 10:03:48.946856 [ANA_INIT] <<<<<<<<<<<<<
7187 10:03:48.949609 [Flow] Enable top DCM control >>>>>
7188 10:03:48.953004 [Flow] Enable top DCM control <<<<<
7189 10:03:48.955972 Enable DLL master slave shuffle
7190 10:03:48.962628 ==============================================================
7191 10:03:48.963132 Gating Mode config
7192 10:03:48.969768 ==============================================================
7193 10:03:48.972827 Config description:
7194 10:03:48.982419 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7195 10:03:48.989507 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7196 10:03:48.992577 SELPH_MODE 0: By rank 1: By Phase
7197 10:03:48.999794 ==============================================================
7198 10:03:49.002809 GAT_TRACK_EN = 1
7199 10:03:49.005511 RX_GATING_MODE = 2
7200 10:03:49.009293 RX_GATING_TRACK_MODE = 2
7201 10:03:49.009834 SELPH_MODE = 1
7202 10:03:49.012263 PICG_EARLY_EN = 1
7203 10:03:49.015299 VALID_LAT_VALUE = 1
7204 10:03:49.022133 ==============================================================
7205 10:03:49.025354 Enter into Gating configuration >>>>
7206 10:03:49.028780 Exit from Gating configuration <<<<
7207 10:03:49.032236 Enter into DVFS_PRE_config >>>>>
7208 10:03:49.042695 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7209 10:03:49.045546 Exit from DVFS_PRE_config <<<<<
7210 10:03:49.048608 Enter into PICG configuration >>>>
7211 10:03:49.051673 Exit from PICG configuration <<<<
7212 10:03:49.055547 [RX_INPUT] configuration >>>>>
7213 10:03:49.058340 [RX_INPUT] configuration <<<<<
7214 10:03:49.062145 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7215 10:03:49.068672 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7216 10:03:49.074857 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7217 10:03:49.081522 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7218 10:03:49.088270 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7219 10:03:49.094938 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7220 10:03:49.098119 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7221 10:03:49.101411 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7222 10:03:49.105120 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7223 10:03:49.107906 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7224 10:03:49.115040 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7225 10:03:49.118338 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7226 10:03:49.121396 ===================================
7227 10:03:49.124522 LPDDR4 DRAM CONFIGURATION
7228 10:03:49.128176 ===================================
7229 10:03:49.128648 EX_ROW_EN[0] = 0x0
7230 10:03:49.131637 EX_ROW_EN[1] = 0x0
7231 10:03:49.132167 LP4Y_EN = 0x0
7232 10:03:49.134085 WORK_FSP = 0x1
7233 10:03:49.137677 WL = 0x5
7234 10:03:49.138607 RL = 0x5
7235 10:03:49.140881 BL = 0x2
7236 10:03:49.141426 RPST = 0x0
7237 10:03:49.144192 RD_PRE = 0x0
7238 10:03:49.144607 WR_PRE = 0x1
7239 10:03:49.147185 WR_PST = 0x1
7240 10:03:49.147596 DBI_WR = 0x0
7241 10:03:49.150789 DBI_RD = 0x0
7242 10:03:49.151348 OTF = 0x1
7243 10:03:49.154387 ===================================
7244 10:03:49.157580 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7245 10:03:49.163817 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7246 10:03:49.167092 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7247 10:03:49.170690 ===================================
7248 10:03:49.174222 LPDDR4 DRAM CONFIGURATION
7249 10:03:49.177254 ===================================
7250 10:03:49.177767 EX_ROW_EN[0] = 0x10
7251 10:03:49.180597 EX_ROW_EN[1] = 0x0
7252 10:03:49.184326 LP4Y_EN = 0x0
7253 10:03:49.184837 WORK_FSP = 0x1
7254 10:03:49.186631 WL = 0x5
7255 10:03:49.187038 RL = 0x5
7256 10:03:49.190620 BL = 0x2
7257 10:03:49.191127 RPST = 0x0
7258 10:03:49.193545 RD_PRE = 0x0
7259 10:03:49.194053 WR_PRE = 0x1
7260 10:03:49.197043 WR_PST = 0x1
7261 10:03:49.197551 DBI_WR = 0x0
7262 10:03:49.200409 DBI_RD = 0x0
7263 10:03:49.200925 OTF = 0x1
7264 10:03:49.203512 ===================================
7265 10:03:49.209711 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7266 10:03:49.210128 ==
7267 10:03:49.213550 Dram Type= 6, Freq= 0, CH_0, rank 0
7268 10:03:49.217142 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7269 10:03:49.219762 ==
7270 10:03:49.220206 [Duty_Offset_Calibration]
7271 10:03:49.223017 B0:2 B1:0 CA:4
7272 10:03:49.223535
7273 10:03:49.226134 [DutyScan_Calibration_Flow] k_type=0
7274 10:03:49.235197
7275 10:03:49.235711 ==CLK 0==
7276 10:03:49.237704 Final CLK duty delay cell = -4
7277 10:03:49.241632 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7278 10:03:49.244741 [-4] MIN Duty = 4844%(X100), DQS PI = 4
7279 10:03:49.247751 [-4] AVG Duty = 4937%(X100)
7280 10:03:49.248166
7281 10:03:49.251259 CH0 CLK Duty spec in!! Max-Min= 187%
7282 10:03:49.254468 [DutyScan_Calibration_Flow] ====Done====
7283 10:03:49.254970
7284 10:03:49.257663 [DutyScan_Calibration_Flow] k_type=1
7285 10:03:49.275019
7286 10:03:49.275539 ==DQS 0 ==
7287 10:03:49.278148 Final DQS duty delay cell = 0
7288 10:03:49.281191 [0] MAX Duty = 5218%(X100), DQS PI = 22
7289 10:03:49.284635 [0] MIN Duty = 5093%(X100), DQS PI = 6
7290 10:03:49.288154 [0] AVG Duty = 5155%(X100)
7291 10:03:49.288676
7292 10:03:49.289124 ==DQS 1 ==
7293 10:03:49.291471 Final DQS duty delay cell = 0
7294 10:03:49.294805 [0] MAX Duty = 5156%(X100), DQS PI = 2
7295 10:03:49.298714 [0] MIN Duty = 4969%(X100), DQS PI = 12
7296 10:03:49.301058 [0] AVG Duty = 5062%(X100)
7297 10:03:49.301486
7298 10:03:49.304571 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7299 10:03:49.305222
7300 10:03:49.307596 CH0 DQS 1 Duty spec in!! Max-Min= 187%
7301 10:03:49.311412 [DutyScan_Calibration_Flow] ====Done====
7302 10:03:49.311932
7303 10:03:49.314649 [DutyScan_Calibration_Flow] k_type=3
7304 10:03:49.331915
7305 10:03:49.332511 ==DQM 0 ==
7306 10:03:49.335130 Final DQM duty delay cell = 0
7307 10:03:49.338543 [0] MAX Duty = 5124%(X100), DQS PI = 22
7308 10:03:49.342232 [0] MIN Duty = 4875%(X100), DQS PI = 54
7309 10:03:49.345751 [0] AVG Duty = 4999%(X100)
7310 10:03:49.346306
7311 10:03:49.346761 ==DQM 1 ==
7312 10:03:49.348831 Final DQM duty delay cell = 0
7313 10:03:49.351764 [0] MAX Duty = 4969%(X100), DQS PI = 0
7314 10:03:49.355106 [0] MIN Duty = 4844%(X100), DQS PI = 14
7315 10:03:49.358863 [0] AVG Duty = 4906%(X100)
7316 10:03:49.359380
7317 10:03:49.361839 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7318 10:03:49.362413
7319 10:03:49.365407 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7320 10:03:49.368196 [DutyScan_Calibration_Flow] ====Done====
7321 10:03:49.368623
7322 10:03:49.371391 [DutyScan_Calibration_Flow] k_type=2
7323 10:03:49.389390
7324 10:03:49.389904 ==DQ 0 ==
7325 10:03:49.392608 Final DQ duty delay cell = 0
7326 10:03:49.395748 [0] MAX Duty = 5156%(X100), DQS PI = 22
7327 10:03:49.398904 [0] MIN Duty = 4938%(X100), DQS PI = 12
7328 10:03:49.402412 [0] AVG Duty = 5047%(X100)
7329 10:03:49.402933
7330 10:03:49.403377 ==DQ 1 ==
7331 10:03:49.405265 Final DQ duty delay cell = 0
7332 10:03:49.409272 [0] MAX Duty = 5218%(X100), DQS PI = 2
7333 10:03:49.412405 [0] MIN Duty = 4938%(X100), DQS PI = 12
7334 10:03:49.412949 [0] AVG Duty = 5078%(X100)
7335 10:03:49.415599
7336 10:03:49.418769 CH0 DQ 0 Duty spec in!! Max-Min= 218%
7337 10:03:49.419289
7338 10:03:49.422010 CH0 DQ 1 Duty spec in!! Max-Min= 280%
7339 10:03:49.425621 [DutyScan_Calibration_Flow] ====Done====
7340 10:03:49.426149 ==
7341 10:03:49.428986 Dram Type= 6, Freq= 0, CH_1, rank 0
7342 10:03:49.431917 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7343 10:03:49.432389 ==
7344 10:03:49.435621 [Duty_Offset_Calibration]
7345 10:03:49.436137 B0:0 B1:-1 CA:3
7346 10:03:49.436583
7347 10:03:49.438460 [DutyScan_Calibration_Flow] k_type=0
7348 10:03:49.449532
7349 10:03:49.450046 ==CLK 0==
7350 10:03:49.453173 Final CLK duty delay cell = 0
7351 10:03:49.456173 [0] MAX Duty = 5187%(X100), DQS PI = 4
7352 10:03:49.460064 [0] MIN Duty = 5000%(X100), DQS PI = 56
7353 10:03:49.460583 [0] AVG Duty = 5093%(X100)
7354 10:03:49.461023
7355 10:03:49.462989 CH1 CLK Duty spec in!! Max-Min= 187%
7356 10:03:49.469357 [DutyScan_Calibration_Flow] ====Done====
7357 10:03:49.469863
7358 10:03:49.473068 [DutyScan_Calibration_Flow] k_type=1
7359 10:03:49.488104
7360 10:03:49.488644 ==DQS 0 ==
7361 10:03:49.491257 Final DQS duty delay cell = 0
7362 10:03:49.494514 [0] MAX Duty = 5250%(X100), DQS PI = 28
7363 10:03:49.498030 [0] MIN Duty = 4938%(X100), DQS PI = 42
7364 10:03:49.501142 [0] AVG Duty = 5094%(X100)
7365 10:03:49.501447
7366 10:03:49.501626 ==DQS 1 ==
7367 10:03:49.504901 Final DQS duty delay cell = -4
7368 10:03:49.507749 [-4] MAX Duty = 5000%(X100), DQS PI = 28
7369 10:03:49.511169 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7370 10:03:49.514570 [-4] AVG Duty = 4922%(X100)
7371 10:03:49.514881
7372 10:03:49.517688 CH1 DQS 0 Duty spec in!! Max-Min= 312%
7373 10:03:49.517907
7374 10:03:49.520905 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7375 10:03:49.524025 [DutyScan_Calibration_Flow] ====Done====
7376 10:03:49.524339
7377 10:03:49.527513 [DutyScan_Calibration_Flow] k_type=3
7378 10:03:49.545441
7379 10:03:49.545856 ==DQM 0 ==
7380 10:03:49.548294 Final DQM duty delay cell = 0
7381 10:03:49.552335 [0] MAX Duty = 5062%(X100), DQS PI = 30
7382 10:03:49.555204 [0] MIN Duty = 4782%(X100), DQS PI = 40
7383 10:03:49.558716 [0] AVG Duty = 4922%(X100)
7384 10:03:49.559218
7385 10:03:49.559546 ==DQM 1 ==
7386 10:03:49.562324 Final DQM duty delay cell = 0
7387 10:03:49.565234 [0] MAX Duty = 5000%(X100), DQS PI = 32
7388 10:03:49.568502 [0] MIN Duty = 4813%(X100), DQS PI = 0
7389 10:03:49.572113 [0] AVG Duty = 4906%(X100)
7390 10:03:49.572613
7391 10:03:49.574897 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7392 10:03:49.575401
7393 10:03:49.578413 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7394 10:03:49.581721 [DutyScan_Calibration_Flow] ====Done====
7395 10:03:49.582227
7396 10:03:49.584856 [DutyScan_Calibration_Flow] k_type=2
7397 10:03:49.601906
7398 10:03:49.602484 ==DQ 0 ==
7399 10:03:49.604961 Final DQ duty delay cell = -4
7400 10:03:49.608833 [-4] MAX Duty = 4938%(X100), DQS PI = 14
7401 10:03:49.611690 [-4] MIN Duty = 4813%(X100), DQS PI = 38
7402 10:03:49.614823 [-4] AVG Duty = 4875%(X100)
7403 10:03:49.615372
7404 10:03:49.615729 ==DQ 1 ==
7405 10:03:49.618654 Final DQ duty delay cell = 0
7406 10:03:49.621319 [0] MAX Duty = 5031%(X100), DQS PI = 30
7407 10:03:49.624431 [0] MIN Duty = 4875%(X100), DQS PI = 0
7408 10:03:49.628054 [0] AVG Duty = 4953%(X100)
7409 10:03:49.628512
7410 10:03:49.630926 CH1 DQ 0 Duty spec in!! Max-Min= 125%
7411 10:03:49.631333
7412 10:03:49.634365 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7413 10:03:49.637933 [DutyScan_Calibration_Flow] ====Done====
7414 10:03:49.641009 nWR fixed to 30
7415 10:03:49.644114 [ModeRegInit_LP4] CH0 RK0
7416 10:03:49.644525 [ModeRegInit_LP4] CH0 RK1
7417 10:03:49.647544 [ModeRegInit_LP4] CH1 RK0
7418 10:03:49.651151 [ModeRegInit_LP4] CH1 RK1
7419 10:03:49.651580 match AC timing 5
7420 10:03:49.657305 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7421 10:03:49.660875 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7422 10:03:49.664480 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7423 10:03:49.670547 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7424 10:03:49.674064 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7425 10:03:49.677193 [MiockJmeterHQA]
7426 10:03:49.677602
7427 10:03:49.681125 [DramcMiockJmeter] u1RxGatingPI = 0
7428 10:03:49.681629 0 : 4253, 4027
7429 10:03:49.681987 4 : 4363, 4137
7430 10:03:49.683508 8 : 4252, 4027
7431 10:03:49.683926 12 : 4253, 4026
7432 10:03:49.687115 16 : 4252, 4027
7433 10:03:49.687531 20 : 4253, 4026
7434 10:03:49.690870 24 : 4255, 4030
7435 10:03:49.691378 28 : 4252, 4027
7436 10:03:49.691709 32 : 4252, 4027
7437 10:03:49.693675 36 : 4365, 4140
7438 10:03:49.694187 40 : 4253, 4026
7439 10:03:49.696646 44 : 4254, 4029
7440 10:03:49.697075 48 : 4253, 4026
7441 10:03:49.700188 52 : 4361, 4137
7442 10:03:49.700698 56 : 4250, 4027
7443 10:03:49.703707 60 : 4361, 4137
7444 10:03:49.704212 64 : 4252, 4027
7445 10:03:49.704545 68 : 4250, 4026
7446 10:03:49.707083 72 : 4250, 4026
7447 10:03:49.707501 76 : 4252, 4029
7448 10:03:49.710095 80 : 4361, 4137
7449 10:03:49.710662 84 : 4250, 4027
7450 10:03:49.713424 88 : 4360, 4137
7451 10:03:49.713928 92 : 4250, 4026
7452 10:03:49.716863 96 : 4250, 2952
7453 10:03:49.717373 100 : 4250, 0
7454 10:03:49.717706 104 : 4253, 0
7455 10:03:49.720606 108 : 4252, 0
7456 10:03:49.721117 112 : 4253, 0
7457 10:03:49.723318 116 : 4253, 0
7458 10:03:49.723736 120 : 4363, 0
7459 10:03:49.724070 124 : 4360, 0
7460 10:03:49.726530 128 : 4363, 0
7461 10:03:49.727037 132 : 4249, 0
7462 10:03:49.729968 136 : 4361, 0
7463 10:03:49.730574 140 : 4250, 0
7464 10:03:49.730921 144 : 4251, 0
7465 10:03:49.732871 148 : 4250, 0
7466 10:03:49.733493 152 : 4250, 0
7467 10:03:49.733841 156 : 4252, 0
7468 10:03:49.736403 160 : 4361, 0
7469 10:03:49.736911 164 : 4250, 0
7470 10:03:49.739322 168 : 4250, 0
7471 10:03:49.739739 172 : 4361, 0
7472 10:03:49.740074 176 : 4360, 0
7473 10:03:49.742635 180 : 4250, 0
7474 10:03:49.743050 184 : 4250, 0
7475 10:03:49.745951 188 : 4361, 0
7476 10:03:49.746592 192 : 4250, 0
7477 10:03:49.747152 196 : 4249, 0
7478 10:03:49.749334 200 : 4250, 0
7479 10:03:49.749916 204 : 4250, 0
7480 10:03:49.752604 208 : 4252, 0
7481 10:03:49.753033 212 : 4363, 0
7482 10:03:49.753469 216 : 4250, 0
7483 10:03:49.756018 220 : 4250, 561
7484 10:03:49.756548 224 : 4360, 4126
7485 10:03:49.759672 228 : 4361, 4137
7486 10:03:49.760195 232 : 4248, 4025
7487 10:03:49.762727 236 : 4361, 4138
7488 10:03:49.763160 240 : 4361, 4137
7489 10:03:49.766181 244 : 4250, 4027
7490 10:03:49.766737 248 : 4250, 4027
7491 10:03:49.768890 252 : 4252, 4029
7492 10:03:49.769319 256 : 4250, 4026
7493 10:03:49.772406 260 : 4250, 4026
7494 10:03:49.772840 264 : 4250, 4027
7495 10:03:49.773281 268 : 4252, 4030
7496 10:03:49.775661 272 : 4250, 4027
7497 10:03:49.776093 276 : 4361, 4137
7498 10:03:49.778793 280 : 4361, 4137
7499 10:03:49.779227 284 : 4250, 4027
7500 10:03:49.782600 288 : 4363, 4140
7501 10:03:49.783172 292 : 4361, 4137
7502 10:03:49.786914 296 : 4250, 4026
7503 10:03:49.787342 300 : 4250, 4027
7504 10:03:49.789250 304 : 4252, 4030
7505 10:03:49.789779 308 : 4250, 4026
7506 10:03:49.792739 312 : 4250, 4026
7507 10:03:49.793263 316 : 4250, 4027
7508 10:03:49.795926 320 : 4252, 4030
7509 10:03:49.796356 324 : 4250, 4027
7510 10:03:49.798476 328 : 4361, 4137
7511 10:03:49.798907 332 : 4361, 4076
7512 10:03:49.802443 336 : 4250, 1715
7513 10:03:49.802973
7514 10:03:49.803416 MIOCK jitter meter ch=0
7515 10:03:49.803831
7516 10:03:49.805457 1T = (336-100) = 236 dly cells
7517 10:03:49.811847 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7518 10:03:49.812475 ==
7519 10:03:49.815445 Dram Type= 6, Freq= 0, CH_0, rank 0
7520 10:03:49.819193 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7521 10:03:49.819747 ==
7522 10:03:49.825142 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7523 10:03:49.828489 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7524 10:03:49.831894 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7525 10:03:49.838056 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7526 10:03:49.848404 [CA 0] Center 44 (14~74) winsize 61
7527 10:03:49.851849 [CA 1] Center 43 (13~74) winsize 62
7528 10:03:49.854515 [CA 2] Center 39 (10~68) winsize 59
7529 10:03:49.857802 [CA 3] Center 38 (9~68) winsize 60
7530 10:03:49.861123 [CA 4] Center 36 (7~66) winsize 60
7531 10:03:49.864762 [CA 5] Center 36 (6~66) winsize 61
7532 10:03:49.865569
7533 10:03:49.867531 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7534 10:03:49.868203
7535 10:03:49.874354 [CATrainingPosCal] consider 1 rank data
7536 10:03:49.874861 u2DelayCellTimex100 = 275/100 ps
7537 10:03:49.880993 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7538 10:03:49.884582 CA1 delay=43 (13~74),Diff = 7 PI (24 cell)
7539 10:03:49.887228 CA2 delay=39 (10~68),Diff = 3 PI (10 cell)
7540 10:03:49.891851 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7541 10:03:49.893975 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7542 10:03:49.897461 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7543 10:03:49.897980
7544 10:03:49.900988 CA PerBit enable=1, Macro0, CA PI delay=36
7545 10:03:49.901569
7546 10:03:49.903933 [CBTSetCACLKResult] CA Dly = 36
7547 10:03:49.907168 CS Dly: 11 (0~42)
7548 10:03:49.910090 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7549 10:03:49.914026 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7550 10:03:49.914575 ==
7551 10:03:49.916791 Dram Type= 6, Freq= 0, CH_0, rank 1
7552 10:03:49.924088 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7553 10:03:49.924600 ==
7554 10:03:49.927158 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7555 10:03:49.933746 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7556 10:03:49.936850 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7557 10:03:49.943549 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7558 10:03:49.952172 [CA 0] Center 44 (14~75) winsize 62
7559 10:03:49.955344 [CA 1] Center 44 (14~74) winsize 61
7560 10:03:49.958585 [CA 2] Center 39 (10~69) winsize 60
7561 10:03:49.961944 [CA 3] Center 39 (10~68) winsize 59
7562 10:03:49.965283 [CA 4] Center 37 (7~67) winsize 61
7563 10:03:49.968670 [CA 5] Center 36 (6~66) winsize 61
7564 10:03:49.969219
7565 10:03:49.971979 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7566 10:03:49.972528
7567 10:03:49.978343 [CATrainingPosCal] consider 2 rank data
7568 10:03:49.978879 u2DelayCellTimex100 = 275/100 ps
7569 10:03:49.984533 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7570 10:03:49.988007 CA1 delay=44 (14~74),Diff = 8 PI (28 cell)
7571 10:03:49.991503 CA2 delay=39 (10~68),Diff = 3 PI (10 cell)
7572 10:03:49.994605 CA3 delay=39 (10~68),Diff = 3 PI (10 cell)
7573 10:03:49.998187 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7574 10:03:50.001533 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7575 10:03:50.002081
7576 10:03:50.004828 CA PerBit enable=1, Macro0, CA PI delay=36
7577 10:03:50.005334
7578 10:03:50.007679 [CBTSetCACLKResult] CA Dly = 36
7579 10:03:50.010892 CS Dly: 11 (0~43)
7580 10:03:50.014945 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7581 10:03:50.017712 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7582 10:03:50.018317
7583 10:03:50.020944 ----->DramcWriteLeveling(PI) begin...
7584 10:03:50.024106 ==
7585 10:03:50.027416 Dram Type= 6, Freq= 0, CH_0, rank 0
7586 10:03:50.030717 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7587 10:03:50.031218 ==
7588 10:03:50.034299 Write leveling (Byte 0): 34 => 34
7589 10:03:50.038043 Write leveling (Byte 1): 26 => 26
7590 10:03:50.040974 DramcWriteLeveling(PI) end<-----
7591 10:03:50.041474
7592 10:03:50.041802 ==
7593 10:03:50.044064 Dram Type= 6, Freq= 0, CH_0, rank 0
7594 10:03:50.047224 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7595 10:03:50.047641 ==
7596 10:03:50.050189 [Gating] SW mode calibration
7597 10:03:50.057289 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7598 10:03:50.064183 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7599 10:03:50.067161 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7600 10:03:50.070541 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7601 10:03:50.076820 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7602 10:03:50.080216 1 4 12 | B1->B0 | 2323 302f | 0 1 | (0 0) (0 0)
7603 10:03:50.083724 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7604 10:03:50.090652 1 4 20 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
7605 10:03:50.093808 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7606 10:03:50.096731 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7607 10:03:50.103369 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7608 10:03:50.106959 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7609 10:03:50.110341 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
7610 10:03:50.116485 1 5 12 | B1->B0 | 3434 2828 | 1 0 | (1 1) (1 0)
7611 10:03:50.119627 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7612 10:03:50.122894 1 5 20 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
7613 10:03:50.130397 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7614 10:03:50.132797 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7615 10:03:50.136099 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7616 10:03:50.143142 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7617 10:03:50.145870 1 6 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (0 0)
7618 10:03:50.148877 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7619 10:03:50.155609 1 6 16 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
7620 10:03:50.159235 1 6 20 | B1->B0 | 3736 4646 | 1 0 | (0 0) (0 0)
7621 10:03:50.162987 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7622 10:03:50.168828 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7623 10:03:50.172651 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7624 10:03:50.175503 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7625 10:03:50.182212 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7626 10:03:50.186024 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7627 10:03:50.189049 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7628 10:03:50.195495 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7629 10:03:50.198733 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7630 10:03:50.202074 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7631 10:03:50.208886 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7632 10:03:50.212539 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7633 10:03:50.214960 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7634 10:03:50.222247 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7635 10:03:50.225379 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7636 10:03:50.228547 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7637 10:03:50.235123 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7638 10:03:50.238354 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7639 10:03:50.241477 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7640 10:03:50.248228 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7641 10:03:50.251578 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7642 10:03:50.254733 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7643 10:03:50.261504 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7644 10:03:50.264304 Total UI for P1: 0, mck2ui 16
7645 10:03:50.267651 best dqsien dly found for B0: ( 1, 9, 8)
7646 10:03:50.271005 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7647 10:03:50.274623 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7648 10:03:50.280643 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7649 10:03:50.284180 Total UI for P1: 0, mck2ui 16
7650 10:03:50.287625 best dqsien dly found for B1: ( 1, 9, 20)
7651 10:03:50.291556 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
7652 10:03:50.294388 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7653 10:03:50.294946
7654 10:03:50.297678 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
7655 10:03:50.300196 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7656 10:03:50.304286 [Gating] SW calibration Done
7657 10:03:50.304787 ==
7658 10:03:50.306763 Dram Type= 6, Freq= 0, CH_0, rank 0
7659 10:03:50.310830 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7660 10:03:50.311378 ==
7661 10:03:50.313660 RX Vref Scan: 0
7662 10:03:50.314202
7663 10:03:50.317387 RX Vref 0 -> 0, step: 1
7664 10:03:50.317937
7665 10:03:50.318341 RX Delay 0 -> 252, step: 8
7666 10:03:50.323744 iDelay=192, Bit 0, Center 135 (80 ~ 191) 112
7667 10:03:50.327038 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7668 10:03:50.330418 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7669 10:03:50.333660 iDelay=192, Bit 3, Center 123 (72 ~ 175) 104
7670 10:03:50.336639 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7671 10:03:50.344119 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7672 10:03:50.347135 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7673 10:03:50.350372 iDelay=192, Bit 7, Center 135 (80 ~ 191) 112
7674 10:03:50.353394 iDelay=192, Bit 8, Center 115 (64 ~ 167) 104
7675 10:03:50.357180 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7676 10:03:50.363962 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7677 10:03:50.366650 iDelay=192, Bit 11, Center 119 (64 ~ 175) 112
7678 10:03:50.370591 iDelay=192, Bit 12, Center 131 (72 ~ 191) 120
7679 10:03:50.373327 iDelay=192, Bit 13, Center 131 (80 ~ 183) 104
7680 10:03:50.376579 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7681 10:03:50.383742 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7682 10:03:50.384250 ==
7683 10:03:50.386308 Dram Type= 6, Freq= 0, CH_0, rank 0
7684 10:03:50.389608 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7685 10:03:50.390021 ==
7686 10:03:50.390398 DQS Delay:
7687 10:03:50.392984 DQS0 = 0, DQS1 = 0
7688 10:03:50.393487 DQM Delay:
7689 10:03:50.396657 DQM0 = 131, DQM1 = 125
7690 10:03:50.397162 DQ Delay:
7691 10:03:50.399493 DQ0 =135, DQ1 =135, DQ2 =127, DQ3 =123
7692 10:03:50.402606 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =135
7693 10:03:50.406239 DQ8 =115, DQ9 =111, DQ10 =127, DQ11 =119
7694 10:03:50.412597 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7695 10:03:50.413103
7696 10:03:50.413433
7697 10:03:50.413735 ==
7698 10:03:50.416044 Dram Type= 6, Freq= 0, CH_0, rank 0
7699 10:03:50.419080 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7700 10:03:50.419586 ==
7701 10:03:50.419916
7702 10:03:50.420219
7703 10:03:50.422791 TX Vref Scan disable
7704 10:03:50.423203 == TX Byte 0 ==
7705 10:03:50.429033 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7706 10:03:50.432266 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7707 10:03:50.436022 == TX Byte 1 ==
7708 10:03:50.439201 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7709 10:03:50.442301 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7710 10:03:50.442713 ==
7711 10:03:50.445481 Dram Type= 6, Freq= 0, CH_0, rank 0
7712 10:03:50.449227 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7713 10:03:50.449732 ==
7714 10:03:50.465346
7715 10:03:50.468205 TX Vref early break, caculate TX vref
7716 10:03:50.471577 TX Vref=16, minBit 4, minWin=22, winSum=371
7717 10:03:50.474917 TX Vref=18, minBit 1, minWin=23, winSum=381
7718 10:03:50.477835 TX Vref=20, minBit 1, minWin=23, winSum=386
7719 10:03:50.481456 TX Vref=22, minBit 1, minWin=23, winSum=398
7720 10:03:50.484546 TX Vref=24, minBit 0, minWin=25, winSum=412
7721 10:03:50.491201 TX Vref=26, minBit 1, minWin=25, winSum=416
7722 10:03:50.494507 TX Vref=28, minBit 2, minWin=25, winSum=421
7723 10:03:50.498131 TX Vref=30, minBit 2, minWin=25, winSum=416
7724 10:03:50.501479 TX Vref=32, minBit 0, minWin=25, winSum=409
7725 10:03:50.504680 TX Vref=34, minBit 7, minWin=23, winSum=402
7726 10:03:50.508087 TX Vref=36, minBit 2, minWin=23, winSum=388
7727 10:03:50.514294 [TxChooseVref] Worse bit 2, Min win 25, Win sum 421, Final Vref 28
7728 10:03:50.514754
7729 10:03:50.517759 Final TX Range 0 Vref 28
7730 10:03:50.518292
7731 10:03:50.518667 ==
7732 10:03:50.521315 Dram Type= 6, Freq= 0, CH_0, rank 0
7733 10:03:50.524281 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7734 10:03:50.524847 ==
7735 10:03:50.527288
7736 10:03:50.527741
7737 10:03:50.528102 TX Vref Scan disable
7738 10:03:50.534377 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7739 10:03:50.534923 == TX Byte 0 ==
7740 10:03:50.537482 u2DelayCellOfst[0]=14 cells (4 PI)
7741 10:03:50.540643 u2DelayCellOfst[1]=17 cells (5 PI)
7742 10:03:50.544576 u2DelayCellOfst[2]=14 cells (4 PI)
7743 10:03:50.547475 u2DelayCellOfst[3]=14 cells (4 PI)
7744 10:03:50.550858 u2DelayCellOfst[4]=10 cells (3 PI)
7745 10:03:50.554556 u2DelayCellOfst[5]=0 cells (0 PI)
7746 10:03:50.557952 u2DelayCellOfst[6]=17 cells (5 PI)
7747 10:03:50.560585 u2DelayCellOfst[7]=17 cells (5 PI)
7748 10:03:50.564016 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7749 10:03:50.567465 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7750 10:03:50.570323 == TX Byte 1 ==
7751 10:03:50.574064 u2DelayCellOfst[8]=0 cells (0 PI)
7752 10:03:50.577260 u2DelayCellOfst[9]=0 cells (0 PI)
7753 10:03:50.580636 u2DelayCellOfst[10]=7 cells (2 PI)
7754 10:03:50.583353 u2DelayCellOfst[11]=3 cells (1 PI)
7755 10:03:50.587159 u2DelayCellOfst[12]=10 cells (3 PI)
7756 10:03:50.590354 u2DelayCellOfst[13]=10 cells (3 PI)
7757 10:03:50.593583 u2DelayCellOfst[14]=14 cells (4 PI)
7758 10:03:50.596937 u2DelayCellOfst[15]=10 cells (3 PI)
7759 10:03:50.600209 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7760 10:03:50.603431 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7761 10:03:50.607020 DramC Write-DBI on
7762 10:03:50.607573 ==
7763 10:03:50.609658 Dram Type= 6, Freq= 0, CH_0, rank 0
7764 10:03:50.613552 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7765 10:03:50.614111 ==
7766 10:03:50.614596
7767 10:03:50.614946
7768 10:03:50.616264 TX Vref Scan disable
7769 10:03:50.620336 == TX Byte 0 ==
7770 10:03:50.623410 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7771 10:03:50.623873 == TX Byte 1 ==
7772 10:03:50.629833 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7773 10:03:50.630291 DramC Write-DBI off
7774 10:03:50.630636
7775 10:03:50.630943 [DATLAT]
7776 10:03:50.633200 Freq=1600, CH0 RK0
7777 10:03:50.633719
7778 10:03:50.636365 DATLAT Default: 0xf
7779 10:03:50.636881 0, 0xFFFF, sum = 0
7780 10:03:50.640116 1, 0xFFFF, sum = 0
7781 10:03:50.640539 2, 0xFFFF, sum = 0
7782 10:03:50.642829 3, 0xFFFF, sum = 0
7783 10:03:50.643250 4, 0xFFFF, sum = 0
7784 10:03:50.646332 5, 0xFFFF, sum = 0
7785 10:03:50.646853 6, 0xFFFF, sum = 0
7786 10:03:50.649677 7, 0xFFFF, sum = 0
7787 10:03:50.650196 8, 0xFFFF, sum = 0
7788 10:03:50.653045 9, 0xFFFF, sum = 0
7789 10:03:50.653566 10, 0xFFFF, sum = 0
7790 10:03:50.655646 11, 0xFFFF, sum = 0
7791 10:03:50.656071 12, 0xFFFF, sum = 0
7792 10:03:50.659608 13, 0xFFFF, sum = 0
7793 10:03:50.662492 14, 0x0, sum = 1
7794 10:03:50.662917 15, 0x0, sum = 2
7795 10:03:50.663260 16, 0x0, sum = 3
7796 10:03:50.666072 17, 0x0, sum = 4
7797 10:03:50.666646 best_step = 15
7798 10:03:50.666989
7799 10:03:50.667298 ==
7800 10:03:50.669589 Dram Type= 6, Freq= 0, CH_0, rank 0
7801 10:03:50.676127 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7802 10:03:50.676646 ==
7803 10:03:50.676983 RX Vref Scan: 1
7804 10:03:50.677294
7805 10:03:50.678804 Set Vref Range= 24 -> 127
7806 10:03:50.679218
7807 10:03:50.682403 RX Vref 24 -> 127, step: 1
7808 10:03:50.682928
7809 10:03:50.685869 RX Delay 11 -> 252, step: 4
7810 10:03:50.686329
7811 10:03:50.688771 Set Vref, RX VrefLevel [Byte0]: 24
7812 10:03:50.692229 [Byte1]: 24
7813 10:03:50.692747
7814 10:03:50.695498 Set Vref, RX VrefLevel [Byte0]: 25
7815 10:03:50.698892 [Byte1]: 25
7816 10:03:50.699481
7817 10:03:50.701837 Set Vref, RX VrefLevel [Byte0]: 26
7818 10:03:50.705295 [Byte1]: 26
7819 10:03:50.708451
7820 10:03:50.708940 Set Vref, RX VrefLevel [Byte0]: 27
7821 10:03:50.712445 [Byte1]: 27
7822 10:03:50.716234
7823 10:03:50.716649 Set Vref, RX VrefLevel [Byte0]: 28
7824 10:03:50.719649 [Byte1]: 28
7825 10:03:50.723697
7826 10:03:50.724113 Set Vref, RX VrefLevel [Byte0]: 29
7827 10:03:50.727035 [Byte1]: 29
7828 10:03:50.731468
7829 10:03:50.731883 Set Vref, RX VrefLevel [Byte0]: 30
7830 10:03:50.734906 [Byte1]: 30
7831 10:03:50.739234
7832 10:03:50.739818 Set Vref, RX VrefLevel [Byte0]: 31
7833 10:03:50.742514 [Byte1]: 31
7834 10:03:50.746582
7835 10:03:50.747124 Set Vref, RX VrefLevel [Byte0]: 32
7836 10:03:50.750091 [Byte1]: 32
7837 10:03:50.754348
7838 10:03:50.754772 Set Vref, RX VrefLevel [Byte0]: 33
7839 10:03:50.757790 [Byte1]: 33
7840 10:03:50.762193
7841 10:03:50.762641 Set Vref, RX VrefLevel [Byte0]: 34
7842 10:03:50.765139 [Byte1]: 34
7843 10:03:50.770233
7844 10:03:50.770847 Set Vref, RX VrefLevel [Byte0]: 35
7845 10:03:50.772788 [Byte1]: 35
7846 10:03:50.777301
7847 10:03:50.777728 Set Vref, RX VrefLevel [Byte0]: 36
7848 10:03:50.780826 [Byte1]: 36
7849 10:03:50.784796
7850 10:03:50.785239 Set Vref, RX VrefLevel [Byte0]: 37
7851 10:03:50.788401 [Byte1]: 37
7852 10:03:50.792874
7853 10:03:50.793287 Set Vref, RX VrefLevel [Byte0]: 38
7854 10:03:50.795847 [Byte1]: 38
7855 10:03:50.800276
7856 10:03:50.800712 Set Vref, RX VrefLevel [Byte0]: 39
7857 10:03:50.803680 [Byte1]: 39
7858 10:03:50.807597
7859 10:03:50.808139 Set Vref, RX VrefLevel [Byte0]: 40
7860 10:03:50.811376 [Byte1]: 40
7861 10:03:50.815198
7862 10:03:50.815612 Set Vref, RX VrefLevel [Byte0]: 41
7863 10:03:50.818528 [Byte1]: 41
7864 10:03:50.823216
7865 10:03:50.823633 Set Vref, RX VrefLevel [Byte0]: 42
7866 10:03:50.826348 [Byte1]: 42
7867 10:03:50.830465
7868 10:03:50.830878 Set Vref, RX VrefLevel [Byte0]: 43
7869 10:03:50.833972 [Byte1]: 43
7870 10:03:50.838043
7871 10:03:50.838505 Set Vref, RX VrefLevel [Byte0]: 44
7872 10:03:50.841450 [Byte1]: 44
7873 10:03:50.846150
7874 10:03:50.846728 Set Vref, RX VrefLevel [Byte0]: 45
7875 10:03:50.849199 [Byte1]: 45
7876 10:03:50.853339
7877 10:03:50.853753 Set Vref, RX VrefLevel [Byte0]: 46
7878 10:03:50.856407 [Byte1]: 46
7879 10:03:50.860845
7880 10:03:50.861255 Set Vref, RX VrefLevel [Byte0]: 47
7881 10:03:50.864226 [Byte1]: 47
7882 10:03:50.869029
7883 10:03:50.869460 Set Vref, RX VrefLevel [Byte0]: 48
7884 10:03:50.872156 [Byte1]: 48
7885 10:03:50.876755
7886 10:03:50.877264 Set Vref, RX VrefLevel [Byte0]: 49
7887 10:03:50.879927 [Byte1]: 49
7888 10:03:50.883963
7889 10:03:50.884377 Set Vref, RX VrefLevel [Byte0]: 50
7890 10:03:50.887344 [Byte1]: 50
7891 10:03:50.891242
7892 10:03:50.891924 Set Vref, RX VrefLevel [Byte0]: 51
7893 10:03:50.894840 [Byte1]: 51
7894 10:03:50.899495
7895 10:03:50.900121 Set Vref, RX VrefLevel [Byte0]: 52
7896 10:03:50.902295 [Byte1]: 52
7897 10:03:50.906880
7898 10:03:50.907288 Set Vref, RX VrefLevel [Byte0]: 53
7899 10:03:50.909700 [Byte1]: 53
7900 10:03:50.914732
7901 10:03:50.915140 Set Vref, RX VrefLevel [Byte0]: 54
7902 10:03:50.917546 [Byte1]: 54
7903 10:03:50.921793
7904 10:03:50.922218 Set Vref, RX VrefLevel [Byte0]: 55
7905 10:03:50.925577 [Byte1]: 55
7906 10:03:50.929526
7907 10:03:50.930091 Set Vref, RX VrefLevel [Byte0]: 56
7908 10:03:50.933372 [Byte1]: 56
7909 10:03:50.937300
7910 10:03:50.937841 Set Vref, RX VrefLevel [Byte0]: 57
7911 10:03:50.940408 [Byte1]: 57
7912 10:03:50.944431
7913 10:03:50.944840 Set Vref, RX VrefLevel [Byte0]: 58
7914 10:03:50.948461 [Byte1]: 58
7915 10:03:50.952549
7916 10:03:50.953269 Set Vref, RX VrefLevel [Byte0]: 59
7917 10:03:50.955735 [Byte1]: 59
7918 10:03:50.959911
7919 10:03:50.960319 Set Vref, RX VrefLevel [Byte0]: 60
7920 10:03:50.963283 [Byte1]: 60
7921 10:03:50.967488
7922 10:03:50.967904 Set Vref, RX VrefLevel [Byte0]: 61
7923 10:03:50.971251 [Byte1]: 61
7924 10:03:50.974935
7925 10:03:50.975346 Set Vref, RX VrefLevel [Byte0]: 62
7926 10:03:50.978383 [Byte1]: 62
7927 10:03:50.983613
7928 10:03:50.984118 Set Vref, RX VrefLevel [Byte0]: 63
7929 10:03:50.986063 [Byte1]: 63
7930 10:03:50.990655
7931 10:03:50.991197 Set Vref, RX VrefLevel [Byte0]: 64
7932 10:03:50.993902 [Byte1]: 64
7933 10:03:50.998088
7934 10:03:50.998662 Set Vref, RX VrefLevel [Byte0]: 65
7935 10:03:51.001207 [Byte1]: 65
7936 10:03:51.005929
7937 10:03:51.006471 Set Vref, RX VrefLevel [Byte0]: 66
7938 10:03:51.009105 [Byte1]: 66
7939 10:03:51.013188
7940 10:03:51.013701 Set Vref, RX VrefLevel [Byte0]: 67
7941 10:03:51.016675 [Byte1]: 67
7942 10:03:51.021298
7943 10:03:51.021814 Set Vref, RX VrefLevel [Byte0]: 68
7944 10:03:51.024313 [Byte1]: 68
7945 10:03:51.028720
7946 10:03:51.029235 Set Vref, RX VrefLevel [Byte0]: 69
7947 10:03:51.032290 [Byte1]: 69
7948 10:03:51.036174
7949 10:03:51.036690 Set Vref, RX VrefLevel [Byte0]: 70
7950 10:03:51.039135 [Byte1]: 70
7951 10:03:51.043846
7952 10:03:51.044362 Set Vref, RX VrefLevel [Byte0]: 71
7953 10:03:51.046830 [Byte1]: 71
7954 10:03:51.051269
7955 10:03:51.051708 Set Vref, RX VrefLevel [Byte0]: 72
7956 10:03:51.054925 [Byte1]: 72
7957 10:03:51.059462
7958 10:03:51.059977 Set Vref, RX VrefLevel [Byte0]: 73
7959 10:03:51.062348 [Byte1]: 73
7960 10:03:51.066985
7961 10:03:51.067485 Set Vref, RX VrefLevel [Byte0]: 74
7962 10:03:51.070040 [Byte1]: 74
7963 10:03:51.074296
7964 10:03:51.074817 Final RX Vref Byte 0 = 53 to rank0
7965 10:03:51.077495 Final RX Vref Byte 1 = 62 to rank0
7966 10:03:51.080799 Final RX Vref Byte 0 = 53 to rank1
7967 10:03:51.084085 Final RX Vref Byte 1 = 62 to rank1==
7968 10:03:51.087218 Dram Type= 6, Freq= 0, CH_0, rank 0
7969 10:03:51.093954 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7970 10:03:51.094527 ==
7971 10:03:51.094973 DQS Delay:
7972 10:03:51.097269 DQS0 = 0, DQS1 = 0
7973 10:03:51.097694 DQM Delay:
7974 10:03:51.098130 DQM0 = 128, DQM1 = 124
7975 10:03:51.101015 DQ Delay:
7976 10:03:51.104476 DQ0 =128, DQ1 =132, DQ2 =124, DQ3 =124
7977 10:03:51.107466 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =132
7978 10:03:51.111285 DQ8 =114, DQ9 =112, DQ10 =126, DQ11 =120
7979 10:03:51.113699 DQ12 =130, DQ13 =130, DQ14 =132, DQ15 =128
7980 10:03:51.114223
7981 10:03:51.114692
7982 10:03:51.115101
7983 10:03:51.117039 [DramC_TX_OE_Calibration] TA2
7984 10:03:51.120675 Original DQ_B0 (3 6) =30, OEN = 27
7985 10:03:51.123643 Original DQ_B1 (3 6) =30, OEN = 27
7986 10:03:51.127212 24, 0x0, End_B0=24 End_B1=24
7987 10:03:51.130349 25, 0x0, End_B0=25 End_B1=25
7988 10:03:51.130878 26, 0x0, End_B0=26 End_B1=26
7989 10:03:51.133543 27, 0x0, End_B0=27 End_B1=27
7990 10:03:51.137045 28, 0x0, End_B0=28 End_B1=28
7991 10:03:51.140221 29, 0x0, End_B0=29 End_B1=29
7992 10:03:51.140841 30, 0x0, End_B0=30 End_B1=30
7993 10:03:51.143901 31, 0x4545, End_B0=30 End_B1=30
7994 10:03:51.146821 Byte0 end_step=30 best_step=27
7995 10:03:51.150614 Byte1 end_step=30 best_step=27
7996 10:03:51.153770 Byte0 TX OE(2T, 0.5T) = (3, 3)
7997 10:03:51.156760 Byte1 TX OE(2T, 0.5T) = (3, 3)
7998 10:03:51.157262
7999 10:03:51.157588
8000 10:03:51.163313 [DQSOSCAuto] RK0, (LSB)MR18= 0x1512, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 399 ps
8001 10:03:51.166450 CH0 RK0: MR19=303, MR18=1512
8002 10:03:51.173050 CH0_RK0: MR19=0x303, MR18=0x1512, DQSOSC=399, MR23=63, INC=23, DEC=15
8003 10:03:51.173540
8004 10:03:51.176661 ----->DramcWriteLeveling(PI) begin...
8005 10:03:51.177174 ==
8006 10:03:51.179551 Dram Type= 6, Freq= 0, CH_0, rank 1
8007 10:03:51.183208 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8008 10:03:51.183716 ==
8009 10:03:51.186241 Write leveling (Byte 0): 36 => 36
8010 10:03:51.189561 Write leveling (Byte 1): 26 => 26
8011 10:03:51.193373 DramcWriteLeveling(PI) end<-----
8012 10:03:51.193893
8013 10:03:51.194430 ==
8014 10:03:51.196549 Dram Type= 6, Freq= 0, CH_0, rank 1
8015 10:03:51.199696 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8016 10:03:51.202769 ==
8017 10:03:51.203297 [Gating] SW mode calibration
8018 10:03:51.212696 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8019 10:03:51.216141 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8020 10:03:51.219793 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8021 10:03:51.225487 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8022 10:03:51.229100 1 4 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
8023 10:03:51.235612 1 4 12 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
8024 10:03:51.238856 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8025 10:03:51.241832 1 4 20 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
8026 10:03:51.248887 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8027 10:03:51.252178 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8028 10:03:51.255835 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8029 10:03:51.261748 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8030 10:03:51.265452 1 5 8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
8031 10:03:51.268621 1 5 12 | B1->B0 | 3434 2626 | 1 0 | (1 0) (0 0)
8032 10:03:51.275170 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8033 10:03:51.278716 1 5 20 | B1->B0 | 2727 2323 | 1 0 | (1 0) (0 0)
8034 10:03:51.281723 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8035 10:03:51.288230 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8036 10:03:51.291695 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8037 10:03:51.295163 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8038 10:03:51.301404 1 6 8 | B1->B0 | 2323 3d3d | 0 0 | (0 0) (0 0)
8039 10:03:51.304795 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8040 10:03:51.308244 1 6 16 | B1->B0 | 3232 4646 | 1 0 | (0 0) (0 0)
8041 10:03:51.314808 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8042 10:03:51.317772 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8043 10:03:51.321716 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8044 10:03:51.327610 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8045 10:03:51.330977 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8046 10:03:51.334344 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8047 10:03:51.341009 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8048 10:03:51.344309 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8049 10:03:51.347354 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8050 10:03:51.353870 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8051 10:03:51.357934 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8052 10:03:51.360692 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8053 10:03:51.367156 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8054 10:03:51.370292 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8055 10:03:51.373634 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8056 10:03:51.380337 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8057 10:03:51.383683 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8058 10:03:51.386811 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8059 10:03:51.393835 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8060 10:03:51.396722 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8061 10:03:51.400073 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8062 10:03:51.407015 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8063 10:03:51.410366 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8064 10:03:51.413779 Total UI for P1: 0, mck2ui 16
8065 10:03:51.416698 best dqsien dly found for B0: ( 1, 9, 6)
8066 10:03:51.420304 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8067 10:03:51.426769 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8068 10:03:51.430010 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8069 10:03:51.432754 Total UI for P1: 0, mck2ui 16
8070 10:03:51.436566 best dqsien dly found for B1: ( 1, 9, 18)
8071 10:03:51.440206 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8072 10:03:51.442910 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8073 10:03:51.443322
8074 10:03:51.446185 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8075 10:03:51.450041 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8076 10:03:51.452663 [Gating] SW calibration Done
8077 10:03:51.453076 ==
8078 10:03:51.456704 Dram Type= 6, Freq= 0, CH_0, rank 1
8079 10:03:51.459571 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8080 10:03:51.462557 ==
8081 10:03:51.462968 RX Vref Scan: 0
8082 10:03:51.463294
8083 10:03:51.466119 RX Vref 0 -> 0, step: 1
8084 10:03:51.466567
8085 10:03:51.466899 RX Delay 0 -> 252, step: 8
8086 10:03:51.472805 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
8087 10:03:51.476149 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
8088 10:03:51.479245 iDelay=192, Bit 2, Center 131 (80 ~ 183) 104
8089 10:03:51.482555 iDelay=192, Bit 3, Center 127 (72 ~ 183) 112
8090 10:03:51.485908 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
8091 10:03:51.492539 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
8092 10:03:51.495870 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
8093 10:03:51.499226 iDelay=192, Bit 7, Center 135 (80 ~ 191) 112
8094 10:03:51.502834 iDelay=192, Bit 8, Center 119 (64 ~ 175) 112
8095 10:03:51.509031 iDelay=192, Bit 9, Center 115 (64 ~ 167) 104
8096 10:03:51.512314 iDelay=192, Bit 10, Center 131 (72 ~ 191) 120
8097 10:03:51.515937 iDelay=192, Bit 11, Center 123 (64 ~ 183) 120
8098 10:03:51.518928 iDelay=192, Bit 12, Center 135 (80 ~ 191) 112
8099 10:03:51.522556 iDelay=192, Bit 13, Center 135 (80 ~ 191) 112
8100 10:03:51.529186 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
8101 10:03:51.532238 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
8102 10:03:51.532693 ==
8103 10:03:51.535472 Dram Type= 6, Freq= 0, CH_0, rank 1
8104 10:03:51.538659 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8105 10:03:51.539210 ==
8106 10:03:51.542579 DQS Delay:
8107 10:03:51.543316 DQS0 = 0, DQS1 = 0
8108 10:03:51.543692 DQM Delay:
8109 10:03:51.545368 DQM0 = 131, DQM1 = 128
8110 10:03:51.545820 DQ Delay:
8111 10:03:51.548742 DQ0 =131, DQ1 =135, DQ2 =131, DQ3 =127
8112 10:03:51.551680 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =135
8113 10:03:51.558412 DQ8 =119, DQ9 =115, DQ10 =131, DQ11 =123
8114 10:03:51.562020 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8115 10:03:51.562584
8116 10:03:51.562922
8117 10:03:51.563228 ==
8118 10:03:51.565639 Dram Type= 6, Freq= 0, CH_0, rank 1
8119 10:03:51.568325 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8120 10:03:51.568833 ==
8121 10:03:51.569162
8122 10:03:51.569461
8123 10:03:51.571916 TX Vref Scan disable
8124 10:03:51.575193 == TX Byte 0 ==
8125 10:03:51.578420 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8126 10:03:51.581790 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8127 10:03:51.585875 == TX Byte 1 ==
8128 10:03:51.588509 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8129 10:03:51.591861 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8130 10:03:51.592271 ==
8131 10:03:51.594874 Dram Type= 6, Freq= 0, CH_0, rank 1
8132 10:03:51.597891 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8133 10:03:51.601810 ==
8134 10:03:51.613530
8135 10:03:51.616816 TX Vref early break, caculate TX vref
8136 10:03:51.620308 TX Vref=16, minBit 9, minWin=22, winSum=379
8137 10:03:51.623326 TX Vref=18, minBit 2, minWin=23, winSum=384
8138 10:03:51.626401 TX Vref=20, minBit 9, minWin=23, winSum=397
8139 10:03:51.630173 TX Vref=22, minBit 10, minWin=24, winSum=405
8140 10:03:51.633416 TX Vref=24, minBit 3, minWin=25, winSum=411
8141 10:03:51.640279 TX Vref=26, minBit 4, minWin=25, winSum=417
8142 10:03:51.643440 TX Vref=28, minBit 3, minWin=25, winSum=419
8143 10:03:51.646456 TX Vref=30, minBit 1, minWin=25, winSum=412
8144 10:03:51.649493 TX Vref=32, minBit 8, minWin=24, winSum=402
8145 10:03:51.653065 TX Vref=34, minBit 0, minWin=24, winSum=397
8146 10:03:51.659312 [TxChooseVref] Worse bit 3, Min win 25, Win sum 419, Final Vref 28
8147 10:03:51.659808
8148 10:03:51.662643 Final TX Range 0 Vref 28
8149 10:03:51.663051
8150 10:03:51.663373 ==
8151 10:03:51.666312 Dram Type= 6, Freq= 0, CH_0, rank 1
8152 10:03:51.669691 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8153 10:03:51.670196 ==
8154 10:03:51.670574
8155 10:03:51.670881
8156 10:03:51.672879 TX Vref Scan disable
8157 10:03:51.679290 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8158 10:03:51.679782 == TX Byte 0 ==
8159 10:03:51.682832 u2DelayCellOfst[0]=10 cells (3 PI)
8160 10:03:51.686155 u2DelayCellOfst[1]=14 cells (4 PI)
8161 10:03:51.689071 u2DelayCellOfst[2]=7 cells (2 PI)
8162 10:03:51.693173 u2DelayCellOfst[3]=10 cells (3 PI)
8163 10:03:51.695763 u2DelayCellOfst[4]=7 cells (2 PI)
8164 10:03:51.698974 u2DelayCellOfst[5]=0 cells (0 PI)
8165 10:03:51.702222 u2DelayCellOfst[6]=14 cells (4 PI)
8166 10:03:51.705794 u2DelayCellOfst[7]=14 cells (4 PI)
8167 10:03:51.709063 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8168 10:03:51.712214 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8169 10:03:51.715622 == TX Byte 1 ==
8170 10:03:51.718849 u2DelayCellOfst[8]=0 cells (0 PI)
8171 10:03:51.722697 u2DelayCellOfst[9]=0 cells (0 PI)
8172 10:03:51.725374 u2DelayCellOfst[10]=3 cells (1 PI)
8173 10:03:51.729055 u2DelayCellOfst[11]=3 cells (1 PI)
8174 10:03:51.731952 u2DelayCellOfst[12]=10 cells (3 PI)
8175 10:03:51.732364 u2DelayCellOfst[13]=10 cells (3 PI)
8176 10:03:51.735387 u2DelayCellOfst[14]=14 cells (4 PI)
8177 10:03:51.738484 u2DelayCellOfst[15]=10 cells (3 PI)
8178 10:03:51.744994 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8179 10:03:51.748249 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8180 10:03:51.751480 DramC Write-DBI on
8181 10:03:51.751889 ==
8182 10:03:51.754702 Dram Type= 6, Freq= 0, CH_0, rank 1
8183 10:03:51.758648 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8184 10:03:51.759153 ==
8185 10:03:51.759480
8186 10:03:51.759784
8187 10:03:51.761528 TX Vref Scan disable
8188 10:03:51.761934 == TX Byte 0 ==
8189 10:03:51.768495 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8190 10:03:51.768982 == TX Byte 1 ==
8191 10:03:51.771728 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8192 10:03:51.774511 DramC Write-DBI off
8193 10:03:51.774923
8194 10:03:51.775248 [DATLAT]
8195 10:03:51.778130 Freq=1600, CH0 RK1
8196 10:03:51.778688
8197 10:03:51.779021 DATLAT Default: 0xf
8198 10:03:51.781400 0, 0xFFFF, sum = 0
8199 10:03:51.784594 1, 0xFFFF, sum = 0
8200 10:03:51.785110 2, 0xFFFF, sum = 0
8201 10:03:51.787439 3, 0xFFFF, sum = 0
8202 10:03:51.787857 4, 0xFFFF, sum = 0
8203 10:03:51.791046 5, 0xFFFF, sum = 0
8204 10:03:51.791461 6, 0xFFFF, sum = 0
8205 10:03:51.794806 7, 0xFFFF, sum = 0
8206 10:03:51.795317 8, 0xFFFF, sum = 0
8207 10:03:51.798386 9, 0xFFFF, sum = 0
8208 10:03:51.798897 10, 0xFFFF, sum = 0
8209 10:03:51.801346 11, 0xFFFF, sum = 0
8210 10:03:51.801851 12, 0xFFFF, sum = 0
8211 10:03:51.804236 13, 0xFFFF, sum = 0
8212 10:03:51.804929 14, 0x0, sum = 1
8213 10:03:51.807508 15, 0x0, sum = 2
8214 10:03:51.807924 16, 0x0, sum = 3
8215 10:03:51.810818 17, 0x0, sum = 4
8216 10:03:51.811331 best_step = 15
8217 10:03:51.811661
8218 10:03:51.811963 ==
8219 10:03:51.814700 Dram Type= 6, Freq= 0, CH_0, rank 1
8220 10:03:51.820629 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8221 10:03:51.821047 ==
8222 10:03:51.821373 RX Vref Scan: 0
8223 10:03:51.821678
8224 10:03:51.823790 RX Vref 0 -> 0, step: 1
8225 10:03:51.824200
8226 10:03:51.827428 RX Delay 19 -> 252, step: 4
8227 10:03:51.830571 iDelay=187, Bit 0, Center 126 (79 ~ 174) 96
8228 10:03:51.833823 iDelay=187, Bit 1, Center 132 (79 ~ 186) 108
8229 10:03:51.837548 iDelay=187, Bit 2, Center 124 (71 ~ 178) 108
8230 10:03:51.843417 iDelay=187, Bit 3, Center 126 (75 ~ 178) 104
8231 10:03:51.847276 iDelay=187, Bit 4, Center 132 (83 ~ 182) 100
8232 10:03:51.850962 iDelay=187, Bit 5, Center 118 (63 ~ 174) 112
8233 10:03:51.853495 iDelay=187, Bit 6, Center 138 (91 ~ 186) 96
8234 10:03:51.857663 iDelay=187, Bit 7, Center 134 (83 ~ 186) 104
8235 10:03:51.863811 iDelay=187, Bit 8, Center 114 (63 ~ 166) 104
8236 10:03:51.866537 iDelay=187, Bit 9, Center 110 (59 ~ 162) 104
8237 10:03:51.870137 iDelay=187, Bit 10, Center 126 (71 ~ 182) 112
8238 10:03:51.873539 iDelay=187, Bit 11, Center 120 (67 ~ 174) 108
8239 10:03:51.880123 iDelay=187, Bit 12, Center 126 (75 ~ 178) 104
8240 10:03:51.883266 iDelay=187, Bit 13, Center 130 (79 ~ 182) 104
8241 10:03:51.886809 iDelay=187, Bit 14, Center 134 (83 ~ 186) 104
8242 10:03:51.890040 iDelay=187, Bit 15, Center 130 (75 ~ 186) 112
8243 10:03:51.890544 ==
8244 10:03:51.893090 Dram Type= 6, Freq= 0, CH_0, rank 1
8245 10:03:51.899747 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8246 10:03:51.900304 ==
8247 10:03:51.900671 DQS Delay:
8248 10:03:51.902944 DQS0 = 0, DQS1 = 0
8249 10:03:51.903416 DQM Delay:
8250 10:03:51.903780 DQM0 = 128, DQM1 = 123
8251 10:03:51.907154 DQ Delay:
8252 10:03:51.909756 DQ0 =126, DQ1 =132, DQ2 =124, DQ3 =126
8253 10:03:51.913458 DQ4 =132, DQ5 =118, DQ6 =138, DQ7 =134
8254 10:03:51.916704 DQ8 =114, DQ9 =110, DQ10 =126, DQ11 =120
8255 10:03:51.919542 DQ12 =126, DQ13 =130, DQ14 =134, DQ15 =130
8256 10:03:51.920090
8257 10:03:51.920452
8258 10:03:51.920785
8259 10:03:51.922962 [DramC_TX_OE_Calibration] TA2
8260 10:03:51.926226 Original DQ_B0 (3 6) =30, OEN = 27
8261 10:03:51.929324 Original DQ_B1 (3 6) =30, OEN = 27
8262 10:03:51.932508 24, 0x0, End_B0=24 End_B1=24
8263 10:03:51.935652 25, 0x0, End_B0=25 End_B1=25
8264 10:03:51.936118 26, 0x0, End_B0=26 End_B1=26
8265 10:03:51.938915 27, 0x0, End_B0=27 End_B1=27
8266 10:03:51.942293 28, 0x0, End_B0=28 End_B1=28
8267 10:03:51.945504 29, 0x0, End_B0=29 End_B1=29
8268 10:03:51.946059 30, 0x0, End_B0=30 End_B1=30
8269 10:03:51.948770 31, 0x4141, End_B0=30 End_B1=30
8270 10:03:51.952416 Byte0 end_step=30 best_step=27
8271 10:03:51.956645 Byte1 end_step=30 best_step=27
8272 10:03:51.958687 Byte0 TX OE(2T, 0.5T) = (3, 3)
8273 10:03:51.962548 Byte1 TX OE(2T, 0.5T) = (3, 3)
8274 10:03:51.963054
8275 10:03:51.963382
8276 10:03:51.969133 [DQSOSCAuto] RK1, (LSB)MR18= 0x1311, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 400 ps
8277 10:03:51.972390 CH0 RK1: MR19=303, MR18=1311
8278 10:03:51.979137 CH0_RK1: MR19=0x303, MR18=0x1311, DQSOSC=400, MR23=63, INC=23, DEC=15
8279 10:03:51.981999 [RxdqsGatingPostProcess] freq 1600
8280 10:03:51.988615 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8281 10:03:51.989190 best DQS0 dly(2T, 0.5T) = (1, 1)
8282 10:03:51.991921 best DQS1 dly(2T, 0.5T) = (1, 1)
8283 10:03:51.995341 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8284 10:03:51.998694 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8285 10:03:52.001924 best DQS0 dly(2T, 0.5T) = (1, 1)
8286 10:03:52.004679 best DQS1 dly(2T, 0.5T) = (1, 1)
8287 10:03:52.007986 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8288 10:03:52.011508 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8289 10:03:52.014767 Pre-setting of DQS Precalculation
8290 10:03:52.017845 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8291 10:03:52.020895 ==
8292 10:03:52.024314 Dram Type= 6, Freq= 0, CH_1, rank 0
8293 10:03:52.027598 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8294 10:03:52.028120 ==
8295 10:03:52.034371 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8296 10:03:52.037404 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8297 10:03:52.041137 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8298 10:03:52.047535 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8299 10:03:52.055908 [CA 0] Center 42 (13~72) winsize 60
8300 10:03:52.059010 [CA 1] Center 42 (12~72) winsize 61
8301 10:03:52.062755 [CA 2] Center 38 (9~67) winsize 59
8302 10:03:52.065710 [CA 3] Center 37 (8~67) winsize 60
8303 10:03:52.069269 [CA 4] Center 38 (8~68) winsize 61
8304 10:03:52.072289 [CA 5] Center 36 (7~66) winsize 60
8305 10:03:52.072701
8306 10:03:52.076118 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8307 10:03:52.076623
8308 10:03:52.079287 [CATrainingPosCal] consider 1 rank data
8309 10:03:52.082275 u2DelayCellTimex100 = 275/100 ps
8310 10:03:52.088693 CA0 delay=42 (13~72),Diff = 6 PI (21 cell)
8311 10:03:52.091998 CA1 delay=42 (12~72),Diff = 6 PI (21 cell)
8312 10:03:52.095812 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8313 10:03:52.098850 CA3 delay=37 (8~67),Diff = 1 PI (3 cell)
8314 10:03:52.102353 CA4 delay=38 (8~68),Diff = 2 PI (7 cell)
8315 10:03:52.105376 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8316 10:03:52.105887
8317 10:03:52.109139 CA PerBit enable=1, Macro0, CA PI delay=36
8318 10:03:52.109642
8319 10:03:52.111944 [CBTSetCACLKResult] CA Dly = 36
8320 10:03:52.115265 CS Dly: 8 (0~39)
8321 10:03:52.118532 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8322 10:03:52.121634 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8323 10:03:52.122115 ==
8324 10:03:52.125140 Dram Type= 6, Freq= 0, CH_1, rank 1
8325 10:03:52.131358 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8326 10:03:52.131805 ==
8327 10:03:52.134776 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8328 10:03:52.141431 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8329 10:03:52.145153 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8330 10:03:52.151419 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8331 10:03:52.158848 [CA 0] Center 42 (12~72) winsize 61
8332 10:03:52.162152 [CA 1] Center 42 (13~72) winsize 60
8333 10:03:52.165644 [CA 2] Center 38 (9~68) winsize 60
8334 10:03:52.168956 [CA 3] Center 37 (8~66) winsize 59
8335 10:03:52.172757 [CA 4] Center 38 (8~68) winsize 61
8336 10:03:52.175452 [CA 5] Center 37 (8~67) winsize 60
8337 10:03:52.175959
8338 10:03:52.178820 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8339 10:03:52.179231
8340 10:03:52.182902 [CATrainingPosCal] consider 2 rank data
8341 10:03:52.185727 u2DelayCellTimex100 = 275/100 ps
8342 10:03:52.192144 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8343 10:03:52.195305 CA1 delay=42 (13~72),Diff = 5 PI (17 cell)
8344 10:03:52.198779 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8345 10:03:52.202105 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8346 10:03:52.204978 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
8347 10:03:52.208412 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8348 10:03:52.208915
8349 10:03:52.212130 CA PerBit enable=1, Macro0, CA PI delay=37
8350 10:03:52.212636
8351 10:03:52.214781 [CBTSetCACLKResult] CA Dly = 37
8352 10:03:52.218586 CS Dly: 9 (0~42)
8353 10:03:52.221758 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8354 10:03:52.224783 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8355 10:03:52.225288
8356 10:03:52.228010 ----->DramcWriteLeveling(PI) begin...
8357 10:03:52.228539 ==
8358 10:03:52.231410 Dram Type= 6, Freq= 0, CH_1, rank 0
8359 10:03:52.237730 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8360 10:03:52.238141 ==
8361 10:03:52.241248 Write leveling (Byte 0): 25 => 25
8362 10:03:52.244175 Write leveling (Byte 1): 26 => 26
8363 10:03:52.247583 DramcWriteLeveling(PI) end<-----
8364 10:03:52.247989
8365 10:03:52.248312 ==
8366 10:03:52.251228 Dram Type= 6, Freq= 0, CH_1, rank 0
8367 10:03:52.254523 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8368 10:03:52.254934 ==
8369 10:03:52.257716 [Gating] SW mode calibration
8370 10:03:52.264206 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8371 10:03:52.270474 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8372 10:03:52.273989 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8373 10:03:52.277936 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8374 10:03:52.283886 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8375 10:03:52.286927 1 4 12 | B1->B0 | 2524 3434 | 1 0 | (0 0) (0 0)
8376 10:03:52.290598 1 4 16 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8377 10:03:52.296926 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8378 10:03:52.300438 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8379 10:03:52.303941 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8380 10:03:52.310184 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8381 10:03:52.313424 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8382 10:03:52.316914 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
8383 10:03:52.323930 1 5 12 | B1->B0 | 3434 2525 | 0 0 | (0 1) (1 0)
8384 10:03:52.326973 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8385 10:03:52.330548 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8386 10:03:52.336600 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8387 10:03:52.339816 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8388 10:03:52.343223 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8389 10:03:52.349848 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8390 10:03:52.353185 1 6 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8391 10:03:52.356279 1 6 12 | B1->B0 | 2727 3f3f | 0 0 | (0 0) (0 0)
8392 10:03:52.363251 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8393 10:03:52.366326 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8394 10:03:52.369890 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8395 10:03:52.376746 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8396 10:03:52.379321 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8397 10:03:52.383176 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8398 10:03:52.389794 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8399 10:03:52.392670 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8400 10:03:52.396225 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8401 10:03:52.403160 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 10:03:52.406380 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 10:03:52.409160 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 10:03:52.416197 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 10:03:52.419684 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8406 10:03:52.422985 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 10:03:52.428914 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 10:03:52.432235 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8409 10:03:52.435527 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8410 10:03:52.442228 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 10:03:52.445467 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8412 10:03:52.448183 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8413 10:03:52.455382 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8414 10:03:52.458420 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8415 10:03:52.462223 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8416 10:03:52.468151 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8417 10:03:52.468700 Total UI for P1: 0, mck2ui 16
8418 10:03:52.474870 best dqsien dly found for B0: ( 1, 9, 10)
8419 10:03:52.475291 Total UI for P1: 0, mck2ui 16
8420 10:03:52.481314 best dqsien dly found for B1: ( 1, 9, 12)
8421 10:03:52.484874 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8422 10:03:52.487608 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8423 10:03:52.488025
8424 10:03:52.491094 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8425 10:03:52.494684 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8426 10:03:52.497608 [Gating] SW calibration Done
8427 10:03:52.498107 ==
8428 10:03:52.501081 Dram Type= 6, Freq= 0, CH_1, rank 0
8429 10:03:52.504446 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8430 10:03:52.504959 ==
8431 10:03:52.508352 RX Vref Scan: 0
8432 10:03:52.508856
8433 10:03:52.511139 RX Vref 0 -> 0, step: 1
8434 10:03:52.511643
8435 10:03:52.511976 RX Delay 0 -> 252, step: 8
8436 10:03:52.517730 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8437 10:03:52.520967 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8438 10:03:52.523945 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8439 10:03:52.527560 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8440 10:03:52.530710 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8441 10:03:52.537557 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8442 10:03:52.540259 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8443 10:03:52.543397 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8444 10:03:52.547134 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8445 10:03:52.550067 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8446 10:03:52.557182 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8447 10:03:52.559920 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8448 10:03:52.563645 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8449 10:03:52.566675 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8450 10:03:52.573518 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8451 10:03:52.576298 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8452 10:03:52.576721 ==
8453 10:03:52.579846 Dram Type= 6, Freq= 0, CH_1, rank 0
8454 10:03:52.583073 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8455 10:03:52.583510 ==
8456 10:03:52.586128 DQS Delay:
8457 10:03:52.586587 DQS0 = 0, DQS1 = 0
8458 10:03:52.586921 DQM Delay:
8459 10:03:52.589795 DQM0 = 135, DQM1 = 131
8460 10:03:52.590407 DQ Delay:
8461 10:03:52.592796 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8462 10:03:52.596316 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =127
8463 10:03:52.603159 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =127
8464 10:03:52.606241 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =135
8465 10:03:52.606827
8466 10:03:52.607159
8467 10:03:52.607469 ==
8468 10:03:52.609343 Dram Type= 6, Freq= 0, CH_1, rank 0
8469 10:03:52.612711 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8470 10:03:52.613218 ==
8471 10:03:52.613552
8472 10:03:52.613855
8473 10:03:52.616048 TX Vref Scan disable
8474 10:03:52.619137 == TX Byte 0 ==
8475 10:03:52.622873 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8476 10:03:52.626068 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8477 10:03:52.629061 == TX Byte 1 ==
8478 10:03:52.632616 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8479 10:03:52.636136 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8480 10:03:52.636655 ==
8481 10:03:52.638661 Dram Type= 6, Freq= 0, CH_1, rank 0
8482 10:03:52.645285 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8483 10:03:52.645699 ==
8484 10:03:52.656414
8485 10:03:52.660262 TX Vref early break, caculate TX vref
8486 10:03:52.662942 TX Vref=16, minBit 8, minWin=21, winSum=367
8487 10:03:52.666478 TX Vref=18, minBit 9, minWin=22, winSum=375
8488 10:03:52.669841 TX Vref=20, minBit 8, minWin=23, winSum=388
8489 10:03:52.673283 TX Vref=22, minBit 8, minWin=23, winSum=393
8490 10:03:52.676654 TX Vref=24, minBit 1, minWin=24, winSum=404
8491 10:03:52.683196 TX Vref=26, minBit 1, minWin=25, winSum=415
8492 10:03:52.685948 TX Vref=28, minBit 8, minWin=25, winSum=422
8493 10:03:52.689045 TX Vref=30, minBit 0, minWin=26, winSum=423
8494 10:03:52.692613 TX Vref=32, minBit 11, minWin=24, winSum=405
8495 10:03:52.695910 TX Vref=34, minBit 0, minWin=23, winSum=398
8496 10:03:52.702844 [TxChooseVref] Worse bit 0, Min win 26, Win sum 423, Final Vref 30
8497 10:03:52.703400
8498 10:03:52.706034 Final TX Range 0 Vref 30
8499 10:03:52.706514
8500 10:03:52.706869 ==
8501 10:03:52.709625 Dram Type= 6, Freq= 0, CH_1, rank 0
8502 10:03:52.712446 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8503 10:03:52.713018 ==
8504 10:03:52.713382
8505 10:03:52.713716
8506 10:03:52.715618 TX Vref Scan disable
8507 10:03:52.722578 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8508 10:03:52.723124 == TX Byte 0 ==
8509 10:03:52.725925 u2DelayCellOfst[0]=14 cells (4 PI)
8510 10:03:52.729060 u2DelayCellOfst[1]=10 cells (3 PI)
8511 10:03:52.732554 u2DelayCellOfst[2]=0 cells (0 PI)
8512 10:03:52.735505 u2DelayCellOfst[3]=7 cells (2 PI)
8513 10:03:52.739414 u2DelayCellOfst[4]=10 cells (3 PI)
8514 10:03:52.742018 u2DelayCellOfst[5]=17 cells (5 PI)
8515 10:03:52.745004 u2DelayCellOfst[6]=17 cells (5 PI)
8516 10:03:52.748998 u2DelayCellOfst[7]=7 cells (2 PI)
8517 10:03:52.752510 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8518 10:03:52.754997 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8519 10:03:52.758288 == TX Byte 1 ==
8520 10:03:52.761626 u2DelayCellOfst[8]=0 cells (0 PI)
8521 10:03:52.765668 u2DelayCellOfst[9]=3 cells (1 PI)
8522 10:03:52.768554 u2DelayCellOfst[10]=10 cells (3 PI)
8523 10:03:52.769064 u2DelayCellOfst[11]=7 cells (2 PI)
8524 10:03:52.771549 u2DelayCellOfst[12]=14 cells (4 PI)
8525 10:03:52.775216 u2DelayCellOfst[13]=17 cells (5 PI)
8526 10:03:52.778598 u2DelayCellOfst[14]=17 cells (5 PI)
8527 10:03:52.782029 u2DelayCellOfst[15]=17 cells (5 PI)
8528 10:03:52.788740 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8529 10:03:52.791381 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8530 10:03:52.791794 DramC Write-DBI on
8531 10:03:52.794884 ==
8532 10:03:52.798429 Dram Type= 6, Freq= 0, CH_1, rank 0
8533 10:03:52.801670 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8534 10:03:52.802174 ==
8535 10:03:52.802580
8536 10:03:52.802888
8537 10:03:52.804753 TX Vref Scan disable
8538 10:03:52.805395 == TX Byte 0 ==
8539 10:03:52.811434 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8540 10:03:52.811936 == TX Byte 1 ==
8541 10:03:52.814219 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8542 10:03:52.818178 DramC Write-DBI off
8543 10:03:52.818719
8544 10:03:52.819050 [DATLAT]
8545 10:03:52.820902 Freq=1600, CH1 RK0
8546 10:03:52.821313
8547 10:03:52.821638 DATLAT Default: 0xf
8548 10:03:52.824360 0, 0xFFFF, sum = 0
8549 10:03:52.824871 1, 0xFFFF, sum = 0
8550 10:03:52.827316 2, 0xFFFF, sum = 0
8551 10:03:52.827734 3, 0xFFFF, sum = 0
8552 10:03:52.830917 4, 0xFFFF, sum = 0
8553 10:03:52.834383 5, 0xFFFF, sum = 0
8554 10:03:52.834889 6, 0xFFFF, sum = 0
8555 10:03:52.837497 7, 0xFFFF, sum = 0
8556 10:03:52.838005 8, 0xFFFF, sum = 0
8557 10:03:52.840880 9, 0xFFFF, sum = 0
8558 10:03:52.841395 10, 0xFFFF, sum = 0
8559 10:03:52.843854 11, 0xFFFF, sum = 0
8560 10:03:52.844270 12, 0xFFFF, sum = 0
8561 10:03:52.847794 13, 0xFFFF, sum = 0
8562 10:03:52.848307 14, 0x0, sum = 1
8563 10:03:52.850713 15, 0x0, sum = 2
8564 10:03:52.851129 16, 0x0, sum = 3
8565 10:03:52.854301 17, 0x0, sum = 4
8566 10:03:52.854724 best_step = 15
8567 10:03:52.855052
8568 10:03:52.855358 ==
8569 10:03:52.857497 Dram Type= 6, Freq= 0, CH_1, rank 0
8570 10:03:52.860514 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8571 10:03:52.863847 ==
8572 10:03:52.864359 RX Vref Scan: 1
8573 10:03:52.864691
8574 10:03:52.867409 Set Vref Range= 24 -> 127
8575 10:03:52.867911
8576 10:03:52.870778 RX Vref 24 -> 127, step: 1
8577 10:03:52.871188
8578 10:03:52.871511 RX Delay 19 -> 252, step: 4
8579 10:03:52.871817
8580 10:03:52.873676 Set Vref, RX VrefLevel [Byte0]: 24
8581 10:03:52.877462 [Byte1]: 24
8582 10:03:52.881458
8583 10:03:52.881957 Set Vref, RX VrefLevel [Byte0]: 25
8584 10:03:52.884659 [Byte1]: 25
8585 10:03:52.888643
8586 10:03:52.889150 Set Vref, RX VrefLevel [Byte0]: 26
8587 10:03:52.891804 [Byte1]: 26
8588 10:03:52.896097
8589 10:03:52.896602 Set Vref, RX VrefLevel [Byte0]: 27
8590 10:03:52.899623 [Byte1]: 27
8591 10:03:52.904021
8592 10:03:52.904433 Set Vref, RX VrefLevel [Byte0]: 28
8593 10:03:52.907459 [Byte1]: 28
8594 10:03:52.911448
8595 10:03:52.911946 Set Vref, RX VrefLevel [Byte0]: 29
8596 10:03:52.914653 [Byte1]: 29
8597 10:03:52.918748
8598 10:03:52.919154 Set Vref, RX VrefLevel [Byte0]: 30
8599 10:03:52.922549 [Byte1]: 30
8600 10:03:52.926560
8601 10:03:52.927067 Set Vref, RX VrefLevel [Byte0]: 31
8602 10:03:52.929658 [Byte1]: 31
8603 10:03:52.934177
8604 10:03:52.934632 Set Vref, RX VrefLevel [Byte0]: 32
8605 10:03:52.937703 [Byte1]: 32
8606 10:03:52.942473
8607 10:03:52.942975 Set Vref, RX VrefLevel [Byte0]: 33
8608 10:03:52.945359 [Byte1]: 33
8609 10:03:52.949491
8610 10:03:52.950013 Set Vref, RX VrefLevel [Byte0]: 34
8611 10:03:52.952685 [Byte1]: 34
8612 10:03:52.956924
8613 10:03:52.957463 Set Vref, RX VrefLevel [Byte0]: 35
8614 10:03:52.960190 [Byte1]: 35
8615 10:03:52.964805
8616 10:03:52.965350 Set Vref, RX VrefLevel [Byte0]: 36
8617 10:03:52.967960 [Byte1]: 36
8618 10:03:52.971745
8619 10:03:52.972307 Set Vref, RX VrefLevel [Byte0]: 37
8620 10:03:52.978452 [Byte1]: 37
8621 10:03:52.978957
8622 10:03:52.981557 Set Vref, RX VrefLevel [Byte0]: 38
8623 10:03:52.984927 [Byte1]: 38
8624 10:03:52.985334
8625 10:03:52.988228 Set Vref, RX VrefLevel [Byte0]: 39
8626 10:03:52.991660 [Byte1]: 39
8627 10:03:52.992072
8628 10:03:52.994397 Set Vref, RX VrefLevel [Byte0]: 40
8629 10:03:52.997980 [Byte1]: 40
8630 10:03:53.002470
8631 10:03:53.003086 Set Vref, RX VrefLevel [Byte0]: 41
8632 10:03:53.005794 [Byte1]: 41
8633 10:03:53.009929
8634 10:03:53.010480 Set Vref, RX VrefLevel [Byte0]: 42
8635 10:03:53.013185 [Byte1]: 42
8636 10:03:53.018326
8637 10:03:53.018834 Set Vref, RX VrefLevel [Byte0]: 43
8638 10:03:53.020588 [Byte1]: 43
8639 10:03:53.025117
8640 10:03:53.025618 Set Vref, RX VrefLevel [Byte0]: 44
8641 10:03:53.028519 [Byte1]: 44
8642 10:03:53.032381
8643 10:03:53.032915 Set Vref, RX VrefLevel [Byte0]: 45
8644 10:03:53.035908 [Byte1]: 45
8645 10:03:53.040405
8646 10:03:53.040987 Set Vref, RX VrefLevel [Byte0]: 46
8647 10:03:53.043351 [Byte1]: 46
8648 10:03:53.047818
8649 10:03:53.048325 Set Vref, RX VrefLevel [Byte0]: 47
8650 10:03:53.050656 [Byte1]: 47
8651 10:03:53.055256
8652 10:03:53.055788 Set Vref, RX VrefLevel [Byte0]: 48
8653 10:03:53.058538 [Byte1]: 48
8654 10:03:53.062568
8655 10:03:53.062979 Set Vref, RX VrefLevel [Byte0]: 49
8656 10:03:53.066095 [Byte1]: 49
8657 10:03:53.070497
8658 10:03:53.071001 Set Vref, RX VrefLevel [Byte0]: 50
8659 10:03:53.073576 [Byte1]: 50
8660 10:03:53.077759
8661 10:03:53.078165 Set Vref, RX VrefLevel [Byte0]: 51
8662 10:03:53.081264 [Byte1]: 51
8663 10:03:53.086076
8664 10:03:53.086629 Set Vref, RX VrefLevel [Byte0]: 52
8665 10:03:53.088763 [Byte1]: 52
8666 10:03:53.093429
8667 10:03:53.093835 Set Vref, RX VrefLevel [Byte0]: 53
8668 10:03:53.096783 [Byte1]: 53
8669 10:03:53.101319
8670 10:03:53.101818 Set Vref, RX VrefLevel [Byte0]: 54
8671 10:03:53.103969 [Byte1]: 54
8672 10:03:53.108210
8673 10:03:53.108714 Set Vref, RX VrefLevel [Byte0]: 55
8674 10:03:53.111775 [Byte1]: 55
8675 10:03:53.115864
8676 10:03:53.116315 Set Vref, RX VrefLevel [Byte0]: 56
8677 10:03:53.119341 [Byte1]: 56
8678 10:03:53.124565
8679 10:03:53.125110 Set Vref, RX VrefLevel [Byte0]: 57
8680 10:03:53.126391 [Byte1]: 57
8681 10:03:53.131221
8682 10:03:53.131765 Set Vref, RX VrefLevel [Byte0]: 58
8683 10:03:53.134178 [Byte1]: 58
8684 10:03:53.138963
8685 10:03:53.139511 Set Vref, RX VrefLevel [Byte0]: 59
8686 10:03:53.142077 [Byte1]: 59
8687 10:03:53.146138
8688 10:03:53.146640 Set Vref, RX VrefLevel [Byte0]: 60
8689 10:03:53.149157 [Byte1]: 60
8690 10:03:53.154185
8691 10:03:53.154749 Set Vref, RX VrefLevel [Byte0]: 61
8692 10:03:53.157145 [Byte1]: 61
8693 10:03:53.161105
8694 10:03:53.161629 Set Vref, RX VrefLevel [Byte0]: 62
8695 10:03:53.164301 [Byte1]: 62
8696 10:03:53.168545
8697 10:03:53.168950 Set Vref, RX VrefLevel [Byte0]: 63
8698 10:03:53.171760 [Byte1]: 63
8699 10:03:53.176592
8700 10:03:53.177001 Set Vref, RX VrefLevel [Byte0]: 64
8701 10:03:53.179368 [Byte1]: 64
8702 10:03:53.183959
8703 10:03:53.184364 Set Vref, RX VrefLevel [Byte0]: 65
8704 10:03:53.187177 [Byte1]: 65
8705 10:03:53.191242
8706 10:03:53.191706 Set Vref, RX VrefLevel [Byte0]: 66
8707 10:03:53.194471 [Byte1]: 66
8708 10:03:53.198848
8709 10:03:53.199259 Set Vref, RX VrefLevel [Byte0]: 67
8710 10:03:53.202141 [Byte1]: 67
8711 10:03:53.206590
8712 10:03:53.207100 Set Vref, RX VrefLevel [Byte0]: 68
8713 10:03:53.210170 [Byte1]: 68
8714 10:03:53.213956
8715 10:03:53.214404 Set Vref, RX VrefLevel [Byte0]: 69
8716 10:03:53.217202 [Byte1]: 69
8717 10:03:53.221878
8718 10:03:53.222443 Set Vref, RX VrefLevel [Byte0]: 70
8719 10:03:53.225021 [Byte1]: 70
8720 10:03:53.229117
8721 10:03:53.229526 Set Vref, RX VrefLevel [Byte0]: 71
8722 10:03:53.233120 [Byte1]: 71
8723 10:03:53.236867
8724 10:03:53.237365 Final RX Vref Byte 0 = 57 to rank0
8725 10:03:53.240683 Final RX Vref Byte 1 = 62 to rank0
8726 10:03:53.243694 Final RX Vref Byte 0 = 57 to rank1
8727 10:03:53.247051 Final RX Vref Byte 1 = 62 to rank1==
8728 10:03:53.249799 Dram Type= 6, Freq= 0, CH_1, rank 0
8729 10:03:53.256646 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8730 10:03:53.257060 ==
8731 10:03:53.257385 DQS Delay:
8732 10:03:53.260685 DQS0 = 0, DQS1 = 0
8733 10:03:53.261185 DQM Delay:
8734 10:03:53.261512 DQM0 = 132, DQM1 = 128
8735 10:03:53.262956 DQ Delay:
8736 10:03:53.266884 DQ0 =140, DQ1 =128, DQ2 =118, DQ3 =132
8737 10:03:53.270012 DQ4 =128, DQ5 =142, DQ6 =144, DQ7 =126
8738 10:03:53.273808 DQ8 =114, DQ9 =118, DQ10 =128, DQ11 =120
8739 10:03:53.276202 DQ12 =138, DQ13 =138, DQ14 =136, DQ15 =138
8740 10:03:53.276619
8741 10:03:53.276942
8742 10:03:53.277239
8743 10:03:53.279590 [DramC_TX_OE_Calibration] TA2
8744 10:03:53.283092 Original DQ_B0 (3 6) =30, OEN = 27
8745 10:03:53.286930 Original DQ_B1 (3 6) =30, OEN = 27
8746 10:03:53.289776 24, 0x0, End_B0=24 End_B1=24
8747 10:03:53.290195 25, 0x0, End_B0=25 End_B1=25
8748 10:03:53.292982 26, 0x0, End_B0=26 End_B1=26
8749 10:03:53.296451 27, 0x0, End_B0=27 End_B1=27
8750 10:03:53.300050 28, 0x0, End_B0=28 End_B1=28
8751 10:03:53.302913 29, 0x0, End_B0=29 End_B1=29
8752 10:03:53.303335 30, 0x0, End_B0=30 End_B1=30
8753 10:03:53.306216 31, 0x4141, End_B0=30 End_B1=30
8754 10:03:53.309543 Byte0 end_step=30 best_step=27
8755 10:03:53.312909 Byte1 end_step=30 best_step=27
8756 10:03:53.316418 Byte0 TX OE(2T, 0.5T) = (3, 3)
8757 10:03:53.319504 Byte1 TX OE(2T, 0.5T) = (3, 3)
8758 10:03:53.320007
8759 10:03:53.320335
8760 10:03:53.325734 [DQSOSCAuto] RK0, (LSB)MR18= 0xe18, (MSB)MR19= 0x303, tDQSOscB0 = 397 ps tDQSOscB1 = 402 ps
8761 10:03:53.329660 CH1 RK0: MR19=303, MR18=E18
8762 10:03:53.335960 CH1_RK0: MR19=0x303, MR18=0xE18, DQSOSC=397, MR23=63, INC=23, DEC=15
8763 10:03:53.336466
8764 10:03:53.339452 ----->DramcWriteLeveling(PI) begin...
8765 10:03:53.339965 ==
8766 10:03:53.342357 Dram Type= 6, Freq= 0, CH_1, rank 1
8767 10:03:53.345989 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8768 10:03:53.346467 ==
8769 10:03:53.349148 Write leveling (Byte 0): 24 => 24
8770 10:03:53.352479 Write leveling (Byte 1): 24 => 24
8771 10:03:53.355352 DramcWriteLeveling(PI) end<-----
8772 10:03:53.355760
8773 10:03:53.356080 ==
8774 10:03:53.358535 Dram Type= 6, Freq= 0, CH_1, rank 1
8775 10:03:53.361968 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8776 10:03:53.365535 ==
8777 10:03:53.366038 [Gating] SW mode calibration
8778 10:03:53.372449 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8779 10:03:53.378718 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8780 10:03:53.382126 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8781 10:03:53.388825 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8782 10:03:53.392035 1 4 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8783 10:03:53.395408 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8784 10:03:53.402404 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8785 10:03:53.405400 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8786 10:03:53.408369 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8787 10:03:53.415195 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8788 10:03:53.418393 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8789 10:03:53.421613 1 5 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8790 10:03:53.428344 1 5 8 | B1->B0 | 3434 2828 | 1 0 | (1 1) (1 0)
8791 10:03:53.431540 1 5 12 | B1->B0 | 3434 2323 | 0 0 | (1 0) (0 0)
8792 10:03:53.434612 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8793 10:03:53.441465 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8794 10:03:53.444788 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8795 10:03:53.447984 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8796 10:03:53.454826 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8797 10:03:53.457924 1 6 4 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
8798 10:03:53.461245 1 6 8 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8799 10:03:53.467964 1 6 12 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
8800 10:03:53.470962 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8801 10:03:53.474436 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8802 10:03:53.481199 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8803 10:03:53.484639 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8804 10:03:53.487181 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8805 10:03:53.493820 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8806 10:03:53.497406 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8807 10:03:53.500665 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8808 10:03:53.507352 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 10:03:53.510191 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8810 10:03:53.514181 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 10:03:53.520311 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8812 10:03:53.523784 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8813 10:03:53.527005 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8814 10:03:53.533409 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8815 10:03:53.537072 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8816 10:03:53.540144 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8817 10:03:53.546761 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8818 10:03:53.550182 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8819 10:03:53.552998 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8820 10:03:53.560141 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8821 10:03:53.563029 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8822 10:03:53.566838 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8823 10:03:53.569572 Total UI for P1: 0, mck2ui 16
8824 10:03:53.573074 best dqsien dly found for B0: ( 1, 9, 4)
8825 10:03:53.579888 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8826 10:03:53.582580 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8827 10:03:53.586420 Total UI for P1: 0, mck2ui 16
8828 10:03:53.589393 best dqsien dly found for B1: ( 1, 9, 10)
8829 10:03:53.593413 best DQS0 dly(MCK, UI, PI) = (1, 9, 4)
8830 10:03:53.596049 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8831 10:03:53.596506
8832 10:03:53.599050 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 4)
8833 10:03:53.606005 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8834 10:03:53.606601 [Gating] SW calibration Done
8835 10:03:53.606970 ==
8836 10:03:53.609414 Dram Type= 6, Freq= 0, CH_1, rank 1
8837 10:03:53.616127 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8838 10:03:53.616678 ==
8839 10:03:53.617042 RX Vref Scan: 0
8840 10:03:53.617378
8841 10:03:53.618536 RX Vref 0 -> 0, step: 1
8842 10:03:53.618993
8843 10:03:53.622218 RX Delay 0 -> 252, step: 8
8844 10:03:53.625559 iDelay=200, Bit 0, Center 143 (88 ~ 199) 112
8845 10:03:53.628991 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8846 10:03:53.632146 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8847 10:03:53.638913 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8848 10:03:53.642240 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8849 10:03:53.645453 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8850 10:03:53.648555 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8851 10:03:53.651704 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8852 10:03:53.658852 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8853 10:03:53.662019 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8854 10:03:53.665346 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8855 10:03:53.668315 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8856 10:03:53.672172 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8857 10:03:53.678368 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8858 10:03:53.681342 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8859 10:03:53.684757 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8860 10:03:53.685304 ==
8861 10:03:53.688494 Dram Type= 6, Freq= 0, CH_1, rank 1
8862 10:03:53.694372 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8863 10:03:53.694909 ==
8864 10:03:53.695273 DQS Delay:
8865 10:03:53.695614 DQS0 = 0, DQS1 = 0
8866 10:03:53.698177 DQM Delay:
8867 10:03:53.698770 DQM0 = 135, DQM1 = 131
8868 10:03:53.701218 DQ Delay:
8869 10:03:53.704702 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8870 10:03:53.707911 DQ4 =131, DQ5 =143, DQ6 =143, DQ7 =131
8871 10:03:53.710951 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =123
8872 10:03:53.714315 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =143
8873 10:03:53.714859
8874 10:03:53.715219
8875 10:03:53.715553 ==
8876 10:03:53.717603 Dram Type= 6, Freq= 0, CH_1, rank 1
8877 10:03:53.721125 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8878 10:03:53.724715 ==
8879 10:03:53.725263
8880 10:03:53.725626
8881 10:03:53.725956 TX Vref Scan disable
8882 10:03:53.727672 == TX Byte 0 ==
8883 10:03:53.730368 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8884 10:03:53.734295 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8885 10:03:53.737397 == TX Byte 1 ==
8886 10:03:53.740672 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8887 10:03:53.744293 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8888 10:03:53.746933 ==
8889 10:03:53.750379 Dram Type= 6, Freq= 0, CH_1, rank 1
8890 10:03:53.754484 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8891 10:03:53.755288 ==
8892 10:03:53.767889
8893 10:03:53.771496 TX Vref early break, caculate TX vref
8894 10:03:53.774438 TX Vref=16, minBit 9, minWin=22, winSum=380
8895 10:03:53.777775 TX Vref=18, minBit 9, minWin=23, winSum=387
8896 10:03:53.781076 TX Vref=20, minBit 9, minWin=23, winSum=396
8897 10:03:53.784170 TX Vref=22, minBit 9, minWin=24, winSum=408
8898 10:03:53.787689 TX Vref=24, minBit 0, minWin=25, winSum=410
8899 10:03:53.794365 TX Vref=26, minBit 1, minWin=25, winSum=415
8900 10:03:53.797770 TX Vref=28, minBit 1, minWin=25, winSum=421
8901 10:03:53.801048 TX Vref=30, minBit 8, minWin=25, winSum=420
8902 10:03:53.804674 TX Vref=32, minBit 15, minWin=24, winSum=411
8903 10:03:53.807724 TX Vref=34, minBit 0, minWin=24, winSum=405
8904 10:03:53.814206 TX Vref=36, minBit 0, minWin=24, winSum=400
8905 10:03:53.817382 TX Vref=38, minBit 0, minWin=23, winSum=388
8906 10:03:53.821172 [TxChooseVref] Worse bit 1, Min win 25, Win sum 421, Final Vref 28
8907 10:03:53.823931
8908 10:03:53.824468 Final TX Range 0 Vref 28
8909 10:03:53.824831
8910 10:03:53.825164 ==
8911 10:03:53.827189 Dram Type= 6, Freq= 0, CH_1, rank 1
8912 10:03:53.833590 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8913 10:03:53.834127 ==
8914 10:03:53.834518
8915 10:03:53.834854
8916 10:03:53.835172 TX Vref Scan disable
8917 10:03:53.840964 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8918 10:03:53.841493 == TX Byte 0 ==
8919 10:03:53.844373 u2DelayCellOfst[0]=14 cells (4 PI)
8920 10:03:53.847547 u2DelayCellOfst[1]=10 cells (3 PI)
8921 10:03:53.850918 u2DelayCellOfst[2]=0 cells (0 PI)
8922 10:03:53.854474 u2DelayCellOfst[3]=7 cells (2 PI)
8923 10:03:53.857232 u2DelayCellOfst[4]=7 cells (2 PI)
8924 10:03:53.861313 u2DelayCellOfst[5]=17 cells (5 PI)
8925 10:03:53.863757 u2DelayCellOfst[6]=14 cells (4 PI)
8926 10:03:53.867013 u2DelayCellOfst[7]=3 cells (1 PI)
8927 10:03:53.871039 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8928 10:03:53.874050 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8929 10:03:53.877549 == TX Byte 1 ==
8930 10:03:53.880700 u2DelayCellOfst[8]=0 cells (0 PI)
8931 10:03:53.884261 u2DelayCellOfst[9]=0 cells (0 PI)
8932 10:03:53.887151 u2DelayCellOfst[10]=10 cells (3 PI)
8933 10:03:53.890849 u2DelayCellOfst[11]=3 cells (1 PI)
8934 10:03:53.893619 u2DelayCellOfst[12]=10 cells (3 PI)
8935 10:03:53.897046 u2DelayCellOfst[13]=14 cells (4 PI)
8936 10:03:53.900643 u2DelayCellOfst[14]=17 cells (5 PI)
8937 10:03:53.901329 u2DelayCellOfst[15]=17 cells (5 PI)
8938 10:03:53.907238 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8939 10:03:53.910634 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8940 10:03:53.913882 DramC Write-DBI on
8941 10:03:53.914607 ==
8942 10:03:53.916645 Dram Type= 6, Freq= 0, CH_1, rank 1
8943 10:03:53.919796 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8944 10:03:53.920360 ==
8945 10:03:53.920888
8946 10:03:53.921216
8947 10:03:53.923797 TX Vref Scan disable
8948 10:03:53.924456 == TX Byte 0 ==
8949 10:03:53.929698 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8950 10:03:53.930206 == TX Byte 1 ==
8951 10:03:53.933310 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8952 10:03:53.936404 DramC Write-DBI off
8953 10:03:53.936818
8954 10:03:53.937340 [DATLAT]
8955 10:03:53.939738 Freq=1600, CH1 RK1
8956 10:03:53.940157
8957 10:03:53.940685 DATLAT Default: 0xf
8958 10:03:53.943097 0, 0xFFFF, sum = 0
8959 10:03:53.946889 1, 0xFFFF, sum = 0
8960 10:03:53.947464 2, 0xFFFF, sum = 0
8961 10:03:53.949484 3, 0xFFFF, sum = 0
8962 10:03:53.949898 4, 0xFFFF, sum = 0
8963 10:03:53.953637 5, 0xFFFF, sum = 0
8964 10:03:53.954055 6, 0xFFFF, sum = 0
8965 10:03:53.956073 7, 0xFFFF, sum = 0
8966 10:03:53.956574 8, 0xFFFF, sum = 0
8967 10:03:53.959309 9, 0xFFFF, sum = 0
8968 10:03:53.959725 10, 0xFFFF, sum = 0
8969 10:03:53.962918 11, 0xFFFF, sum = 0
8970 10:03:53.963428 12, 0xFFFF, sum = 0
8971 10:03:53.966340 13, 0xFFFF, sum = 0
8972 10:03:53.966757 14, 0x0, sum = 1
8973 10:03:53.969643 15, 0x0, sum = 2
8974 10:03:53.970056 16, 0x0, sum = 3
8975 10:03:53.973078 17, 0x0, sum = 4
8976 10:03:53.973492 best_step = 15
8977 10:03:53.973817
8978 10:03:53.974120 ==
8979 10:03:53.976187 Dram Type= 6, Freq= 0, CH_1, rank 1
8980 10:03:53.983155 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8981 10:03:53.983601 ==
8982 10:03:53.983932 RX Vref Scan: 0
8983 10:03:53.984237
8984 10:03:53.985830 RX Vref 0 -> 0, step: 1
8985 10:03:53.986235
8986 10:03:53.989256 RX Delay 19 -> 252, step: 4
8987 10:03:53.992332 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
8988 10:03:53.995665 iDelay=195, Bit 1, Center 128 (75 ~ 182) 108
8989 10:03:53.999252 iDelay=195, Bit 2, Center 120 (67 ~ 174) 108
8990 10:03:54.006055 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8991 10:03:54.008669 iDelay=195, Bit 4, Center 128 (71 ~ 186) 116
8992 10:03:54.012305 iDelay=195, Bit 5, Center 142 (91 ~ 194) 104
8993 10:03:54.015301 iDelay=195, Bit 6, Center 140 (87 ~ 194) 108
8994 10:03:54.021674 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8995 10:03:54.025448 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8996 10:03:54.028742 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8997 10:03:54.031872 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
8998 10:03:54.034876 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8999 10:03:54.041624 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
9000 10:03:54.045226 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
9001 10:03:54.048581 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
9002 10:03:54.051844 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
9003 10:03:54.052258 ==
9004 10:03:54.054915 Dram Type= 6, Freq= 0, CH_1, rank 1
9005 10:03:54.061088 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9006 10:03:54.061508 ==
9007 10:03:54.061839 DQS Delay:
9008 10:03:54.064565 DQS0 = 0, DQS1 = 0
9009 10:03:54.064977 DQM Delay:
9010 10:03:54.067527 DQM0 = 130, DQM1 = 128
9011 10:03:54.067942 DQ Delay:
9012 10:03:54.071078 DQ0 =134, DQ1 =128, DQ2 =120, DQ3 =128
9013 10:03:54.074316 DQ4 =128, DQ5 =142, DQ6 =140, DQ7 =126
9014 10:03:54.077371 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =120
9015 10:03:54.080793 DQ12 =136, DQ13 =136, DQ14 =132, DQ15 =136
9016 10:03:54.081295
9017 10:03:54.081628
9018 10:03:54.081933
9019 10:03:54.084258 [DramC_TX_OE_Calibration] TA2
9020 10:03:54.087737 Original DQ_B0 (3 6) =30, OEN = 27
9021 10:03:54.091133 Original DQ_B1 (3 6) =30, OEN = 27
9022 10:03:54.094015 24, 0x0, End_B0=24 End_B1=24
9023 10:03:54.097520 25, 0x0, End_B0=25 End_B1=25
9024 10:03:54.097941 26, 0x0, End_B0=26 End_B1=26
9025 10:03:54.101343 27, 0x0, End_B0=27 End_B1=27
9026 10:03:54.103784 28, 0x0, End_B0=28 End_B1=28
9027 10:03:54.107308 29, 0x0, End_B0=29 End_B1=29
9028 10:03:54.110305 30, 0x0, End_B0=30 End_B1=30
9029 10:03:54.110820 31, 0x4141, End_B0=30 End_B1=30
9030 10:03:54.113692 Byte0 end_step=30 best_step=27
9031 10:03:54.117480 Byte1 end_step=30 best_step=27
9032 10:03:54.120658 Byte0 TX OE(2T, 0.5T) = (3, 3)
9033 10:03:54.123667 Byte1 TX OE(2T, 0.5T) = (3, 3)
9034 10:03:54.124086
9035 10:03:54.124413
9036 10:03:54.130607 [DQSOSCAuto] RK1, (LSB)MR18= 0x111e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 401 ps
9037 10:03:54.133898 CH1 RK1: MR19=303, MR18=111E
9038 10:03:54.140945 CH1_RK1: MR19=0x303, MR18=0x111E, DQSOSC=394, MR23=63, INC=23, DEC=15
9039 10:03:54.143682 [RxdqsGatingPostProcess] freq 1600
9040 10:03:54.150334 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9041 10:03:54.153557 best DQS0 dly(2T, 0.5T) = (1, 1)
9042 10:03:54.154016 best DQS1 dly(2T, 0.5T) = (1, 1)
9043 10:03:54.156684 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9044 10:03:54.160127 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9045 10:03:54.163305 best DQS0 dly(2T, 0.5T) = (1, 1)
9046 10:03:54.166709 best DQS1 dly(2T, 0.5T) = (1, 1)
9047 10:03:54.170329 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9048 10:03:54.173397 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9049 10:03:54.176525 Pre-setting of DQS Precalculation
9050 10:03:54.183516 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9051 10:03:54.189878 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9052 10:03:54.196586 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9053 10:03:54.197142
9054 10:03:54.197506
9055 10:03:54.199785 [Calibration Summary] 3200 Mbps
9056 10:03:54.200242 CH 0, Rank 0
9057 10:03:54.202801 SW Impedance : PASS
9058 10:03:54.206418 DUTY Scan : NO K
9059 10:03:54.206932 ZQ Calibration : PASS
9060 10:03:54.209757 Jitter Meter : NO K
9061 10:03:54.212888 CBT Training : PASS
9062 10:03:54.213440 Write leveling : PASS
9063 10:03:54.216410 RX DQS gating : PASS
9064 10:03:54.219593 RX DQ/DQS(RDDQC) : PASS
9065 10:03:54.220067 TX DQ/DQS : PASS
9066 10:03:54.222533 RX DATLAT : PASS
9067 10:03:54.226007 RX DQ/DQS(Engine): PASS
9068 10:03:54.226614 TX OE : PASS
9069 10:03:54.226986 All Pass.
9070 10:03:54.227326
9071 10:03:54.229621 CH 0, Rank 1
9072 10:03:54.233044 SW Impedance : PASS
9073 10:03:54.233606 DUTY Scan : NO K
9074 10:03:54.235793 ZQ Calibration : PASS
9075 10:03:54.236354 Jitter Meter : NO K
9076 10:03:54.239115 CBT Training : PASS
9077 10:03:54.242744 Write leveling : PASS
9078 10:03:54.243298 RX DQS gating : PASS
9079 10:03:54.245781 RX DQ/DQS(RDDQC) : PASS
9080 10:03:54.248703 TX DQ/DQS : PASS
9081 10:03:54.249161 RX DATLAT : PASS
9082 10:03:54.252555 RX DQ/DQS(Engine): PASS
9083 10:03:54.255273 TX OE : PASS
9084 10:03:54.255724 All Pass.
9085 10:03:54.256052
9086 10:03:54.256428 CH 1, Rank 0
9087 10:03:54.258794 SW Impedance : PASS
9088 10:03:54.261681 DUTY Scan : NO K
9089 10:03:54.262094 ZQ Calibration : PASS
9090 10:03:54.265205 Jitter Meter : NO K
9091 10:03:54.268833 CBT Training : PASS
9092 10:03:54.269243 Write leveling : PASS
9093 10:03:54.271976 RX DQS gating : PASS
9094 10:03:54.275435 RX DQ/DQS(RDDQC) : PASS
9095 10:03:54.275844 TX DQ/DQS : PASS
9096 10:03:54.278377 RX DATLAT : PASS
9097 10:03:54.281540 RX DQ/DQS(Engine): PASS
9098 10:03:54.281951 TX OE : PASS
9099 10:03:54.285181 All Pass.
9100 10:03:54.285593
9101 10:03:54.285920 CH 1, Rank 1
9102 10:03:54.288490 SW Impedance : PASS
9103 10:03:54.288904 DUTY Scan : NO K
9104 10:03:54.291810 ZQ Calibration : PASS
9105 10:03:54.295552 Jitter Meter : NO K
9106 10:03:54.295967 CBT Training : PASS
9107 10:03:54.298425 Write leveling : PASS
9108 10:03:54.301448 RX DQS gating : PASS
9109 10:03:54.301856 RX DQ/DQS(RDDQC) : PASS
9110 10:03:54.304999 TX DQ/DQS : PASS
9111 10:03:54.308483 RX DATLAT : PASS
9112 10:03:54.309074 RX DQ/DQS(Engine): PASS
9113 10:03:54.311095 TX OE : PASS
9114 10:03:54.311506 All Pass.
9115 10:03:54.311829
9116 10:03:54.314462 DramC Write-DBI on
9117 10:03:54.317852 PER_BANK_REFRESH: Hybrid Mode
9118 10:03:54.318307 TX_TRACKING: ON
9119 10:03:54.327831 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9120 10:03:54.334444 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9121 10:03:54.341036 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9122 10:03:54.344610 [FAST_K] Save calibration result to emmc
9123 10:03:54.347508 sync common calibartion params.
9124 10:03:54.350800 sync cbt_mode0:1, 1:1
9125 10:03:54.354145 dram_init: ddr_geometry: 2
9126 10:03:54.354601 dram_init: ddr_geometry: 2
9127 10:03:54.357891 dram_init: ddr_geometry: 2
9128 10:03:54.361312 0:dram_rank_size:100000000
9129 10:03:54.364181 1:dram_rank_size:100000000
9130 10:03:54.367814 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9131 10:03:54.370486 DFS_SHUFFLE_HW_MODE: ON
9132 10:03:54.373866 dramc_set_vcore_voltage set vcore to 725000
9133 10:03:54.377755 Read voltage for 1600, 0
9134 10:03:54.378310 Vio18 = 0
9135 10:03:54.378655 Vcore = 725000
9136 10:03:54.380223 Vdram = 0
9137 10:03:54.380627 Vddq = 0
9138 10:03:54.380953 Vmddr = 0
9139 10:03:54.383762 switch to 3200 Mbps bootup
9140 10:03:54.387268 [DramcRunTimeConfig]
9141 10:03:54.387780 PHYPLL
9142 10:03:54.388212 DPM_CONTROL_AFTERK: ON
9143 10:03:54.390361 PER_BANK_REFRESH: ON
9144 10:03:54.394042 REFRESH_OVERHEAD_REDUCTION: ON
9145 10:03:54.394622 CMD_PICG_NEW_MODE: OFF
9146 10:03:54.397461 XRTWTW_NEW_MODE: ON
9147 10:03:54.400450 XRTRTR_NEW_MODE: ON
9148 10:03:54.400949 TX_TRACKING: ON
9149 10:03:54.403805 RDSEL_TRACKING: OFF
9150 10:03:54.404311 DQS Precalculation for DVFS: ON
9151 10:03:54.407768 RX_TRACKING: OFF
9152 10:03:54.408316 HW_GATING DBG: ON
9153 10:03:54.410303 ZQCS_ENABLE_LP4: ON
9154 10:03:54.413657 RX_PICG_NEW_MODE: ON
9155 10:03:54.414200 TX_PICG_NEW_MODE: ON
9156 10:03:54.417192 ENABLE_RX_DCM_DPHY: ON
9157 10:03:54.420059 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9158 10:03:54.420665 DUMMY_READ_FOR_TRACKING: OFF
9159 10:03:54.423807 !!! SPM_CONTROL_AFTERK: OFF
9160 10:03:54.427290 !!! SPM could not control APHY
9161 10:03:54.430097 IMPEDANCE_TRACKING: ON
9162 10:03:54.430755 TEMP_SENSOR: ON
9163 10:03:54.433087 HW_SAVE_FOR_SR: OFF
9164 10:03:54.436730 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9165 10:03:54.440142 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9166 10:03:54.440708 Read ODT Tracking: ON
9167 10:03:54.443175 Refresh Rate DeBounce: ON
9168 10:03:54.447166 DFS_NO_QUEUE_FLUSH: ON
9169 10:03:54.449728 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9170 10:03:54.450186 ENABLE_DFS_RUNTIME_MRW: OFF
9171 10:03:54.453212 DDR_RESERVE_NEW_MODE: ON
9172 10:03:54.456897 MR_CBT_SWITCH_FREQ: ON
9173 10:03:54.457442 =========================
9174 10:03:54.476428 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9175 10:03:54.480070 dram_init: ddr_geometry: 2
9176 10:03:54.498356 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9177 10:03:54.501431 dram_init: dram init end (result: 0)
9178 10:03:54.507737 DRAM-K: Full calibration passed in 24412 msecs
9179 10:03:54.511067 MRC: failed to locate region type 0.
9180 10:03:54.511620 DRAM rank0 size:0x100000000,
9181 10:03:54.514814 DRAM rank1 size=0x100000000
9182 10:03:54.524207 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9183 10:03:54.531093 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9184 10:03:54.538040 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9185 10:03:54.547314 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9186 10:03:54.547841 DRAM rank0 size:0x100000000,
9187 10:03:54.550865 DRAM rank1 size=0x100000000
9188 10:03:54.551323 CBMEM:
9189 10:03:54.554108 IMD: root @ 0xfffff000 254 entries.
9190 10:03:54.557908 IMD: root @ 0xffffec00 62 entries.
9191 10:03:54.561044 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9192 10:03:54.567730 WARNING: RO_VPD is uninitialized or empty.
9193 10:03:54.570454 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9194 10:03:54.578831 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9195 10:03:54.590928 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9196 10:03:54.602105 BS: romstage times (exec / console): total (unknown) / 23944 ms
9197 10:03:54.602788
9198 10:03:54.603162
9199 10:03:54.611925 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9200 10:03:54.615405 ARM64: Exception handlers installed.
9201 10:03:54.618835 ARM64: Testing exception
9202 10:03:54.622226 ARM64: Done test exception
9203 10:03:54.622876 Enumerating buses...
9204 10:03:54.625090 Show all devs... Before device enumeration.
9205 10:03:54.628253 Root Device: enabled 1
9206 10:03:54.632009 CPU_CLUSTER: 0: enabled 1
9207 10:03:54.632556 CPU: 00: enabled 1
9208 10:03:54.635213 Compare with tree...
9209 10:03:54.635764 Root Device: enabled 1
9210 10:03:54.639231 CPU_CLUSTER: 0: enabled 1
9211 10:03:54.641656 CPU: 00: enabled 1
9212 10:03:54.642111 Root Device scanning...
9213 10:03:54.645762 scan_static_bus for Root Device
9214 10:03:54.648673 CPU_CLUSTER: 0 enabled
9215 10:03:54.651826 scan_static_bus for Root Device done
9216 10:03:54.654779 scan_bus: bus Root Device finished in 8 msecs
9217 10:03:54.655238 done
9218 10:03:54.661784 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9219 10:03:54.665175 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9220 10:03:54.671339 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9221 10:03:54.674831 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9222 10:03:54.678072 Allocating resources...
9223 10:03:54.681309 Reading resources...
9224 10:03:54.684577 Root Device read_resources bus 0 link: 0
9225 10:03:54.687918 DRAM rank0 size:0x100000000,
9226 10:03:54.688370 DRAM rank1 size=0x100000000
9227 10:03:54.694541 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9228 10:03:54.695077 CPU: 00 missing read_resources
9229 10:03:54.700928 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9230 10:03:54.704288 Root Device read_resources bus 0 link: 0 done
9231 10:03:54.707771 Done reading resources.
9232 10:03:54.711131 Show resources in subtree (Root Device)...After reading.
9233 10:03:54.714437 Root Device child on link 0 CPU_CLUSTER: 0
9234 10:03:54.717461 CPU_CLUSTER: 0 child on link 0 CPU: 00
9235 10:03:54.727477 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9236 10:03:54.728051 CPU: 00
9237 10:03:54.734464 Root Device assign_resources, bus 0 link: 0
9238 10:03:54.737727 CPU_CLUSTER: 0 missing set_resources
9239 10:03:54.740599 Root Device assign_resources, bus 0 link: 0 done
9240 10:03:54.741150 Done setting resources.
9241 10:03:54.747081 Show resources in subtree (Root Device)...After assigning values.
9242 10:03:54.751731 Root Device child on link 0 CPU_CLUSTER: 0
9243 10:03:54.753658 CPU_CLUSTER: 0 child on link 0 CPU: 00
9244 10:03:54.763380 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9245 10:03:54.763924 CPU: 00
9246 10:03:54.766662 Done allocating resources.
9247 10:03:54.773260 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9248 10:03:54.773798 Enabling resources...
9249 10:03:54.776875 done.
9250 10:03:54.780117 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9251 10:03:54.783547 Initializing devices...
9252 10:03:54.784097 Root Device init
9253 10:03:54.787187 init hardware done!
9254 10:03:54.787733 0x00000018: ctrlr->caps
9255 10:03:54.790664 52.000 MHz: ctrlr->f_max
9256 10:03:54.793157 0.400 MHz: ctrlr->f_min
9257 10:03:54.793623 0x40ff8080: ctrlr->voltages
9258 10:03:54.796349 sclk: 390625
9259 10:03:54.796797 Bus Width = 1
9260 10:03:54.799782 sclk: 390625
9261 10:03:54.800235 Bus Width = 1
9262 10:03:54.803021 Early init status = 3
9263 10:03:54.806882 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9264 10:03:54.810411 in-header: 03 fc 00 00 01 00 00 00
9265 10:03:54.813099 in-data: 00
9266 10:03:54.816508 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9267 10:03:54.821970 in-header: 03 fd 00 00 00 00 00 00
9268 10:03:54.825137 in-data:
9269 10:03:54.828236 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9270 10:03:54.832894 in-header: 03 fc 00 00 01 00 00 00
9271 10:03:54.836153 in-data: 00
9272 10:03:54.839211 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9273 10:03:54.844939 in-header: 03 fd 00 00 00 00 00 00
9274 10:03:54.847832 in-data:
9275 10:03:54.851169 [SSUSB] Setting up USB HOST controller...
9276 10:03:54.854976 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9277 10:03:54.858020 [SSUSB] phy power-on done.
9278 10:03:54.861660 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9279 10:03:54.867521 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9280 10:03:54.870782 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9281 10:03:54.877463 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9282 10:03:54.884039 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9283 10:03:54.890873 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9284 10:03:54.897239 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9285 10:03:54.904633 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9286 10:03:54.907269 SPM: binary array size = 0x9dc
9287 10:03:54.910727 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9288 10:03:54.917081 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9289 10:03:54.923930 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9290 10:03:54.930639 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9291 10:03:54.934034 configure_display: Starting display init
9292 10:03:54.967695 anx7625_power_on_init: Init interface.
9293 10:03:54.972207 anx7625_disable_pd_protocol: Disabled PD feature.
9294 10:03:54.974375 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9295 10:03:55.002125 anx7625_start_dp_work: Secure OCM version=00
9296 10:03:55.005542 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9297 10:03:55.020950 sp_tx_get_edid_block: EDID Block = 1
9298 10:03:55.123334 Extracted contents:
9299 10:03:55.126347 header: 00 ff ff ff ff ff ff 00
9300 10:03:55.129548 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9301 10:03:55.132995 version: 01 04
9302 10:03:55.136349 basic params: 95 1f 11 78 0a
9303 10:03:55.139597 chroma info: 76 90 94 55 54 90 27 21 50 54
9304 10:03:55.142604 established: 00 00 00
9305 10:03:55.149953 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9306 10:03:55.155611 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9307 10:03:55.159464 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9308 10:03:55.165527 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9309 10:03:55.172332 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9310 10:03:55.176049 extensions: 00
9311 10:03:55.176593 checksum: fb
9312 10:03:55.176955
9313 10:03:55.179237 Manufacturer: IVO Model 57d Serial Number 0
9314 10:03:55.182212 Made week 0 of 2020
9315 10:03:55.185538 EDID version: 1.4
9316 10:03:55.185963 Digital display
9317 10:03:55.189178 6 bits per primary color channel
9318 10:03:55.189691 DisplayPort interface
9319 10:03:55.192216 Maximum image size: 31 cm x 17 cm
9320 10:03:55.195769 Gamma: 220%
9321 10:03:55.196276 Check DPMS levels
9322 10:03:55.198939 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9323 10:03:55.205719 First detailed timing is preferred timing
9324 10:03:55.206229 Established timings supported:
9325 10:03:55.209048 Standard timings supported:
9326 10:03:55.212262 Detailed timings
9327 10:03:55.215186 Hex of detail: 383680a07038204018303c0035ae10000019
9328 10:03:55.221781 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9329 10:03:55.225210 0780 0798 07c8 0820 hborder 0
9330 10:03:55.228361 0438 043b 0447 0458 vborder 0
9331 10:03:55.232146 -hsync -vsync
9332 10:03:55.232661 Did detailed timing
9333 10:03:55.238479 Hex of detail: 000000000000000000000000000000000000
9334 10:03:55.241650 Manufacturer-specified data, tag 0
9335 10:03:55.244801 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9336 10:03:55.248103 ASCII string: InfoVision
9337 10:03:55.251390 Hex of detail: 000000fe00523134304e574635205248200a
9338 10:03:55.254696 ASCII string: R140NWF5 RH
9339 10:03:55.255147 Checksum
9340 10:03:55.257964 Checksum: 0xfb (valid)
9341 10:03:55.261546 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9342 10:03:55.264892 DSI data_rate: 832800000 bps
9343 10:03:55.271195 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9344 10:03:55.274483 anx7625_parse_edid: pixelclock(138800).
9345 10:03:55.278159 hactive(1920), hsync(48), hfp(24), hbp(88)
9346 10:03:55.281142 vactive(1080), vsync(12), vfp(3), vbp(17)
9347 10:03:55.285181 anx7625_dsi_config: config dsi.
9348 10:03:55.291213 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9349 10:03:55.304738 anx7625_dsi_config: success to config DSI
9350 10:03:55.308464 anx7625_dp_start: MIPI phy setup OK.
9351 10:03:55.311688 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9352 10:03:55.315527 mtk_ddp_mode_set invalid vrefresh 60
9353 10:03:55.318514 main_disp_path_setup
9354 10:03:55.319057 ovl_layer_smi_id_en
9355 10:03:55.321265 ovl_layer_smi_id_en
9356 10:03:55.321722 ccorr_config
9357 10:03:55.322081 aal_config
9358 10:03:55.324676 gamma_config
9359 10:03:55.325227 postmask_config
9360 10:03:55.327954 dither_config
9361 10:03:55.331320 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9362 10:03:55.337345 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9363 10:03:55.340637 Root Device init finished in 553 msecs
9364 10:03:55.344045 CPU_CLUSTER: 0 init
9365 10:03:55.350645 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9366 10:03:55.357420 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9367 10:03:55.357712 APU_MBOX 0x190000b0 = 0x10001
9368 10:03:55.360381 APU_MBOX 0x190001b0 = 0x10001
9369 10:03:55.363348 APU_MBOX 0x190005b0 = 0x10001
9370 10:03:55.366549 APU_MBOX 0x190006b0 = 0x10001
9371 10:03:55.373645 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9372 10:03:55.383635 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9373 10:03:55.395813 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9374 10:03:55.402534 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9375 10:03:55.414592 read SPI 0x61c74 0xe8ef: 6411 us, 9301 KB/s, 74.408 Mbps
9376 10:03:55.423460 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9377 10:03:55.427101 CPU_CLUSTER: 0 init finished in 81 msecs
9378 10:03:55.430207 Devices initialized
9379 10:03:55.433301 Show all devs... After init.
9380 10:03:55.433579 Root Device: enabled 1
9381 10:03:55.436819 CPU_CLUSTER: 0: enabled 1
9382 10:03:55.440033 CPU: 00: enabled 1
9383 10:03:55.443451 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9384 10:03:55.446902 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9385 10:03:55.450306 ELOG: NV offset 0x57f000 size 0x1000
9386 10:03:55.457204 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9387 10:03:55.463331 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9388 10:03:55.466553 ELOG: Event(17) added with size 13 at 2023-11-24 10:03:57 UTC
9389 10:03:55.473759 out: cmd=0x121: 03 db 21 01 00 00 00 00
9390 10:03:55.476743 in-header: 03 3b 00 00 2c 00 00 00
9391 10:03:55.486750 in-data: 24 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9392 10:03:55.493645 ELOG: Event(A1) added with size 10 at 2023-11-24 10:03:57 UTC
9393 10:03:55.499876 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9394 10:03:55.506224 ELOG: Event(A0) added with size 9 at 2023-11-24 10:03:57 UTC
9395 10:03:55.509566 elog_add_boot_reason: Logged dev mode boot
9396 10:03:55.516347 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9397 10:03:55.516884 Finalize devices...
9398 10:03:55.519691 Devices finalized
9399 10:03:55.522548 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9400 10:03:55.526136 Writing coreboot table at 0xffe64000
9401 10:03:55.529442 0. 000000000010a000-0000000000113fff: RAMSTAGE
9402 10:03:55.536185 1. 0000000040000000-00000000400fffff: RAM
9403 10:03:55.539769 2. 0000000040100000-000000004032afff: RAMSTAGE
9404 10:03:55.542973 3. 000000004032b000-00000000545fffff: RAM
9405 10:03:55.546001 4. 0000000054600000-000000005465ffff: BL31
9406 10:03:55.549409 5. 0000000054660000-00000000ffe63fff: RAM
9407 10:03:55.555861 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9408 10:03:55.558832 7. 0000000100000000-000000023fffffff: RAM
9409 10:03:55.562305 Passing 5 GPIOs to payload:
9410 10:03:55.565669 NAME | PORT | POLARITY | VALUE
9411 10:03:55.572575 EC in RW | 0x000000aa | low | undefined
9412 10:03:55.575589 EC interrupt | 0x00000005 | low | undefined
9413 10:03:55.578928 TPM interrupt | 0x000000ab | high | undefined
9414 10:03:55.585623 SD card detect | 0x00000011 | high | undefined
9415 10:03:55.588910 speaker enable | 0x00000093 | high | undefined
9416 10:03:55.592020 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9417 10:03:55.596141 in-header: 03 f9 00 00 02 00 00 00
9418 10:03:55.599132 in-data: 02 00
9419 10:03:55.602522 ADC[4]: Raw value=902955 ID=7
9420 10:03:55.605982 ADC[3]: Raw value=213916 ID=1
9421 10:03:55.606565 RAM Code: 0x71
9422 10:03:55.609535 ADC[6]: Raw value=74630 ID=0
9423 10:03:55.612417 ADC[5]: Raw value=214285 ID=1
9424 10:03:55.612932 SKU Code: 0x1
9425 10:03:55.619098 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum db3
9426 10:03:55.619602 coreboot table: 964 bytes.
9427 10:03:55.622693 IMD ROOT 0. 0xfffff000 0x00001000
9428 10:03:55.625463 IMD SMALL 1. 0xffffe000 0x00001000
9429 10:03:55.628675 RO MCACHE 2. 0xffffc000 0x00001104
9430 10:03:55.632346 CONSOLE 3. 0xfff7c000 0x00080000
9431 10:03:55.635429 FMAP 4. 0xfff7b000 0x00000452
9432 10:03:55.638685 TIME STAMP 5. 0xfff7a000 0x00000910
9433 10:03:55.641898 VBOOT WORK 6. 0xfff66000 0x00014000
9434 10:03:55.645435 RAMOOPS 7. 0xffe66000 0x00100000
9435 10:03:55.649006 COREBOOT 8. 0xffe64000 0x00002000
9436 10:03:55.652033 IMD small region:
9437 10:03:55.655241 IMD ROOT 0. 0xffffec00 0x00000400
9438 10:03:55.658812 VPD 1. 0xffffeb80 0x0000006c
9439 10:03:55.661624 MMC STATUS 2. 0xffffeb60 0x00000004
9440 10:03:55.668391 BS: BS_WRITE_TABLES run times (exec / console): 2 / 137 ms
9441 10:03:55.668815 Probing TPM: done!
9442 10:03:55.675406 Connected to device vid:did:rid of 1ae0:0028:00
9443 10:03:55.682097 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
9444 10:03:55.685217 Initialized TPM device CR50 revision 0
9445 10:03:55.688598 Checking cr50 for pending updates
9446 10:03:55.694537 Reading cr50 TPM mode
9447 10:03:55.702739 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9448 10:03:55.709558 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9449 10:03:55.749902 read SPI 0x3990ec 0x4f1b0: 34846 us, 9298 KB/s, 74.384 Mbps
9450 10:03:55.753246 Checking segment from ROM address 0x40100000
9451 10:03:55.756139 Checking segment from ROM address 0x4010001c
9452 10:03:55.762897 Loading segment from ROM address 0x40100000
9453 10:03:55.763445 code (compression=0)
9454 10:03:55.772847 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9455 10:03:55.779082 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9456 10:03:55.779538 it's not compressed!
9457 10:03:55.786683 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9458 10:03:55.792202 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9459 10:03:55.810036 Loading segment from ROM address 0x4010001c
9460 10:03:55.810645 Entry Point 0x80000000
9461 10:03:55.813337 Loaded segments
9462 10:03:55.816378 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9463 10:03:55.823393 Jumping to boot code at 0x80000000(0xffe64000)
9464 10:03:55.829963 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9465 10:03:55.836581 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9466 10:03:55.844353 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9467 10:03:55.847519 Checking segment from ROM address 0x40100000
9468 10:03:55.850944 Checking segment from ROM address 0x4010001c
9469 10:03:55.857255 Loading segment from ROM address 0x40100000
9470 10:03:55.857769 code (compression=1)
9471 10:03:55.864318 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9472 10:03:55.874322 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9473 10:03:55.874879 using LZMA
9474 10:03:55.882882 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9475 10:03:55.889588 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9476 10:03:55.892396 Loading segment from ROM address 0x4010001c
9477 10:03:55.892856 Entry Point 0x54601000
9478 10:03:55.895899 Loaded segments
9479 10:03:55.898960 NOTICE: MT8192 bl31_setup
9480 10:03:55.907055 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9481 10:03:55.909363 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9482 10:03:55.913333 WARNING: region 0:
9483 10:03:55.916333 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9484 10:03:55.916873 WARNING: region 1:
9485 10:03:55.922849 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9486 10:03:55.926143 WARNING: region 2:
9487 10:03:55.929830 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9488 10:03:55.933052 WARNING: region 3:
9489 10:03:55.936165 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9490 10:03:55.939647 WARNING: region 4:
9491 10:03:55.946208 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9492 10:03:55.946802 WARNING: region 5:
9493 10:03:55.949739 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9494 10:03:55.952678 WARNING: region 6:
9495 10:03:55.956126 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9496 10:03:55.959738 WARNING: region 7:
9497 10:03:55.962789 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9498 10:03:55.969063 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9499 10:03:55.972546 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9500 10:03:55.976133 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9501 10:03:55.982416 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9502 10:03:55.986191 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9503 10:03:55.992396 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9504 10:03:55.995754 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9505 10:03:55.999929 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9506 10:03:56.005956 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9507 10:03:56.009662 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9508 10:03:56.012643 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9509 10:03:56.019229 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9510 10:03:56.022720 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9511 10:03:56.026201 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9512 10:03:56.032980 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9513 10:03:56.036262 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9514 10:03:56.042867 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9515 10:03:56.046112 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9516 10:03:56.049292 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9517 10:03:56.055831 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9518 10:03:56.058849 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9519 10:03:56.065263 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9520 10:03:56.068695 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9521 10:03:56.072653 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9522 10:03:56.078784 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9523 10:03:56.082411 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9524 10:03:56.089125 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9525 10:03:56.092335 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9526 10:03:56.095257 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9527 10:03:56.102069 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9528 10:03:56.105895 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9529 10:03:56.112313 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9530 10:03:56.115153 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9531 10:03:56.119191 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9532 10:03:56.122320 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9533 10:03:56.128569 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9534 10:03:56.132450 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9535 10:03:56.135903 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9536 10:03:56.138853 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9537 10:03:56.145525 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9538 10:03:56.148610 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9539 10:03:56.151923 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9540 10:03:56.155089 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9541 10:03:56.162172 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9542 10:03:56.165420 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9543 10:03:56.168304 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9544 10:03:56.171912 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9545 10:03:56.178757 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9546 10:03:56.181405 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9547 10:03:56.188586 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9548 10:03:56.191815 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9549 10:03:56.194836 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9550 10:03:56.201825 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9551 10:03:56.205060 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9552 10:03:56.211553 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9553 10:03:56.214942 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9554 10:03:56.221489 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9555 10:03:56.225234 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9556 10:03:56.228090 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9557 10:03:56.235044 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9558 10:03:56.238155 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9559 10:03:56.244941 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9560 10:03:56.248160 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9561 10:03:56.255266 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9562 10:03:56.257915 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9563 10:03:56.264504 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9564 10:03:56.267695 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9565 10:03:56.271534 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9566 10:03:56.278129 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9567 10:03:56.280710 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9568 10:03:56.287609 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9569 10:03:56.291150 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9570 10:03:56.297482 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9571 10:03:56.300626 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9572 10:03:56.304240 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9573 10:03:56.310974 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9574 10:03:56.314099 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9575 10:03:56.320869 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9576 10:03:56.324318 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9577 10:03:56.330667 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9578 10:03:56.333745 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9579 10:03:56.340666 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9580 10:03:56.344441 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9581 10:03:56.347400 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9582 10:03:56.354055 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9583 10:03:56.357030 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9584 10:03:56.363937 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9585 10:03:56.367189 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9586 10:03:56.374092 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9587 10:03:56.377152 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9588 10:03:56.380606 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9589 10:03:56.387345 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9590 10:03:56.390500 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9591 10:03:56.396815 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9592 10:03:56.400085 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9593 10:03:56.406752 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9594 10:03:56.410121 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9595 10:03:56.413575 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9596 10:03:56.420113 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9597 10:03:56.423629 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9598 10:03:56.426559 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9599 10:03:56.430178 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9600 10:03:56.437023 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9601 10:03:56.439986 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9602 10:03:56.446921 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9603 10:03:56.450201 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9604 10:03:56.453526 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9605 10:03:56.459894 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9606 10:03:56.463508 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9607 10:03:56.469833 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9608 10:03:56.473526 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9609 10:03:56.477019 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9610 10:03:56.483195 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9611 10:03:56.486659 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9612 10:03:56.493373 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9613 10:03:56.496608 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9614 10:03:56.499966 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9615 10:03:56.506759 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9616 10:03:56.510149 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9617 10:03:56.513363 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9618 10:03:56.516883 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9619 10:03:56.523227 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9620 10:03:56.526508 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9621 10:03:56.529971 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9622 10:03:56.537004 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9623 10:03:56.539828 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9624 10:03:56.542800 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9625 10:03:56.549868 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9626 10:03:56.552962 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9627 10:03:56.559856 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9628 10:03:56.563095 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9629 10:03:56.566736 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9630 10:03:56.573023 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9631 10:03:56.576387 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9632 10:03:56.579877 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9633 10:03:56.586378 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9634 10:03:56.589755 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9635 10:03:56.596275 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9636 10:03:56.599546 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9637 10:03:56.602697 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9638 10:03:56.609987 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9639 10:03:56.613006 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9640 10:03:56.619755 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9641 10:03:56.622831 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9642 10:03:56.626492 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9643 10:03:56.633164 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9644 10:03:56.636371 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9645 10:03:56.642897 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9646 10:03:56.646127 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9647 10:03:56.649009 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9648 10:03:56.656028 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9649 10:03:56.659178 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9650 10:03:56.665900 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9651 10:03:56.669714 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9652 10:03:56.672077 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9653 10:03:56.678956 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9654 10:03:56.682050 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9655 10:03:56.689030 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9656 10:03:56.692525 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9657 10:03:56.695291 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9658 10:03:56.702236 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9659 10:03:56.705077 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9660 10:03:56.712523 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9661 10:03:56.715126 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9662 10:03:56.719163 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9663 10:03:56.725589 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9664 10:03:56.729008 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9665 10:03:56.735255 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9666 10:03:56.738965 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9667 10:03:56.741754 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9668 10:03:56.748631 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9669 10:03:56.751952 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9670 10:03:56.755001 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9671 10:03:56.761729 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9672 10:03:56.764920 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9673 10:03:56.771599 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9674 10:03:56.774820 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9675 10:03:56.781236 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9676 10:03:56.784833 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9677 10:03:56.787726 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9678 10:03:56.794896 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9679 10:03:56.798059 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9680 10:03:56.804230 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9681 10:03:56.807840 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9682 10:03:56.811244 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9683 10:03:56.817982 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9684 10:03:56.820948 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9685 10:03:56.827648 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9686 10:03:56.830853 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9687 10:03:56.833814 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9688 10:03:56.841047 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9689 10:03:56.843726 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9690 10:03:56.850599 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9691 10:03:56.853614 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9692 10:03:56.860637 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9693 10:03:56.863494 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9694 10:03:56.867097 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9695 10:03:56.873261 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9696 10:03:56.877394 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9697 10:03:56.883277 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9698 10:03:56.886749 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9699 10:03:56.893322 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9700 10:03:56.896574 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9701 10:03:56.899906 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9702 10:03:56.906626 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9703 10:03:56.909473 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9704 10:03:56.916159 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9705 10:03:56.919492 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9706 10:03:56.926131 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9707 10:03:56.929272 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9708 10:03:56.933399 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9709 10:03:56.939619 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9710 10:03:56.943166 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9711 10:03:56.949403 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9712 10:03:56.952523 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9713 10:03:56.959334 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9714 10:03:56.962498 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9715 10:03:56.966086 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9716 10:03:56.972511 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9717 10:03:56.975755 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9718 10:03:56.982649 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9719 10:03:56.985546 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9720 10:03:56.992174 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9721 10:03:56.995030 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9722 10:03:56.998815 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9723 10:03:57.005068 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9724 10:03:57.008710 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9725 10:03:57.015399 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9726 10:03:57.018304 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9727 10:03:57.021973 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9728 10:03:57.028793 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9729 10:03:57.031627 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9730 10:03:57.035001 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9731 10:03:57.037788 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9732 10:03:57.044520 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9733 10:03:57.047851 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9734 10:03:57.051474 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9735 10:03:57.058091 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9736 10:03:57.061100 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9737 10:03:57.067806 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9738 10:03:57.070974 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9739 10:03:57.074493 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9740 10:03:57.081528 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9741 10:03:57.084167 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9742 10:03:57.087543 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9743 10:03:57.094415 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9744 10:03:57.097571 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9745 10:03:57.104569 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9746 10:03:57.107087 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9747 10:03:57.110624 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9748 10:03:57.117139 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9749 10:03:57.120536 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9750 10:03:57.123992 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9751 10:03:57.130615 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9752 10:03:57.134042 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9753 10:03:57.140086 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9754 10:03:57.144352 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9755 10:03:57.147266 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9756 10:03:57.153775 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9757 10:03:57.156766 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9758 10:03:57.160577 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9759 10:03:57.167205 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9760 10:03:57.170317 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9761 10:03:57.173284 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9762 10:03:57.180266 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9763 10:03:57.183759 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9764 10:03:57.190447 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9765 10:03:57.193743 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9766 10:03:57.196778 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9767 10:03:57.199814 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9768 10:03:57.206925 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9769 10:03:57.210506 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9770 10:03:57.213370 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9771 10:03:57.216989 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9772 10:03:57.223247 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9773 10:03:57.226196 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9774 10:03:57.229906 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9775 10:03:57.232878 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9776 10:03:57.240022 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9777 10:03:57.243020 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9778 10:03:57.246398 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9779 10:03:57.253041 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9780 10:03:57.256127 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9781 10:03:57.259553 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9782 10:03:57.265920 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9783 10:03:57.269215 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9784 10:03:57.276156 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9785 10:03:57.279475 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9786 10:03:57.285719 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9787 10:03:57.289648 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9788 10:03:57.292770 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9789 10:03:57.299284 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9790 10:03:57.302389 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9791 10:03:57.309407 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9792 10:03:57.312469 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9793 10:03:57.318886 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9794 10:03:57.322229 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9795 10:03:57.325211 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9796 10:03:57.332043 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9797 10:03:57.335057 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9798 10:03:57.341917 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9799 10:03:57.345174 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9800 10:03:57.348487 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9801 10:03:57.355433 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9802 10:03:57.359008 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9803 10:03:57.364629 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9804 10:03:57.368532 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9805 10:03:57.374942 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9806 10:03:57.378019 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9807 10:03:57.381300 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9808 10:03:57.387905 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9809 10:03:57.391519 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9810 10:03:57.398106 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9811 10:03:57.401388 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9812 10:03:57.404261 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9813 10:03:57.411087 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9814 10:03:57.414315 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9815 10:03:57.420767 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9816 10:03:57.423891 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9817 10:03:57.430720 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9818 10:03:57.434193 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9819 10:03:57.437540 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9820 10:03:57.444500 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9821 10:03:57.447252 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9822 10:03:57.453748 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9823 10:03:57.456938 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9824 10:03:57.463385 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9825 10:03:57.467120 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9826 10:03:57.470374 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9827 10:03:57.477055 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9828 10:03:57.480761 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9829 10:03:57.486817 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9830 10:03:57.489592 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9831 10:03:57.493115 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9832 10:03:57.500035 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9833 10:03:57.503198 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9834 10:03:57.509664 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9835 10:03:57.513178 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9836 10:03:57.516533 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9837 10:03:57.522780 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9838 10:03:57.525884 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9839 10:03:57.533017 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9840 10:03:57.535975 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9841 10:03:57.542495 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9842 10:03:57.545974 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9843 10:03:57.549178 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9844 10:03:57.555667 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9845 10:03:57.559055 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9846 10:03:57.565237 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9847 10:03:57.569079 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9848 10:03:57.575602 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9849 10:03:57.578926 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9850 10:03:57.582528 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9851 10:03:57.588980 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9852 10:03:57.592430 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9853 10:03:57.598506 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9854 10:03:57.602493 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9855 10:03:57.608621 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9856 10:03:57.611881 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9857 10:03:57.618691 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9858 10:03:57.622121 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9859 10:03:57.624682 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9860 10:03:57.631782 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9861 10:03:57.634517 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9862 10:03:57.641411 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9863 10:03:57.644341 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9864 10:03:57.651362 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9865 10:03:57.654830 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9866 10:03:57.661550 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9867 10:03:57.664157 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9868 10:03:57.667451 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9869 10:03:57.674018 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9870 10:03:57.677186 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9871 10:03:57.683994 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9872 10:03:57.687178 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9873 10:03:57.694127 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9874 10:03:57.697338 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9875 10:03:57.703890 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9876 10:03:57.707123 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9877 10:03:57.710942 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9878 10:03:57.717175 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9879 10:03:57.720599 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9880 10:03:57.727270 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9881 10:03:57.730366 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9882 10:03:57.737099 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9883 10:03:57.740506 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9884 10:03:57.746608 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9885 10:03:57.750285 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9886 10:03:57.753506 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9887 10:03:57.759688 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9888 10:03:57.763245 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9889 10:03:57.769850 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9890 10:03:57.773008 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9891 10:03:57.779685 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9892 10:03:57.782734 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9893 10:03:57.789919 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9894 10:03:57.792776 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9895 10:03:57.796648 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9896 10:03:57.802725 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9897 10:03:57.806314 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9898 10:03:57.812792 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9899 10:03:57.816284 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9900 10:03:57.819184 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9901 10:03:57.826067 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9902 10:03:57.829168 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9903 10:03:57.835650 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9904 10:03:57.838974 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9905 10:03:57.845385 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9906 10:03:57.849055 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9907 10:03:57.855322 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9908 10:03:57.858731 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9909 10:03:57.865850 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9910 10:03:57.869127 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9911 10:03:57.875132 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9912 10:03:57.878346 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9913 10:03:57.885084 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9914 10:03:57.888987 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9915 10:03:57.895035 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9916 10:03:57.898144 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9917 10:03:57.905283 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9918 10:03:57.908596 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9919 10:03:57.915234 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9920 10:03:57.918168 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9921 10:03:57.924656 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9922 10:03:57.928123 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9923 10:03:57.934648 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9924 10:03:57.937471 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9925 10:03:57.944331 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9926 10:03:57.947799 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9927 10:03:57.954509 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9928 10:03:57.960854 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9929 10:03:57.964402 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9930 10:03:57.970283 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9931 10:03:57.974235 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9932 10:03:57.976890 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9933 10:03:57.980221 INFO: [APUAPC] vio 0
9934 10:03:57.983810 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9935 10:03:57.990584 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9936 10:03:57.993904 INFO: [APUAPC] D0_APC_0: 0x400510
9937 10:03:57.996777 INFO: [APUAPC] D0_APC_1: 0x0
9938 10:03:58.000783 INFO: [APUAPC] D0_APC_2: 0x1540
9939 10:03:58.001373 INFO: [APUAPC] D0_APC_3: 0x0
9940 10:03:58.006640 INFO: [APUAPC] D1_APC_0: 0xffffffff
9941 10:03:58.009903 INFO: [APUAPC] D1_APC_1: 0xffffffff
9942 10:03:58.013674 INFO: [APUAPC] D1_APC_2: 0x3fffff
9943 10:03:58.014191 INFO: [APUAPC] D1_APC_3: 0x0
9944 10:03:58.016890 INFO: [APUAPC] D2_APC_0: 0xffffffff
9945 10:03:58.023878 INFO: [APUAPC] D2_APC_1: 0xffffffff
9946 10:03:58.024430 INFO: [APUAPC] D2_APC_2: 0x3fffff
9947 10:03:58.026468 INFO: [APUAPC] D2_APC_3: 0x0
9948 10:03:58.030043 INFO: [APUAPC] D3_APC_0: 0xffffffff
9949 10:03:58.033877 INFO: [APUAPC] D3_APC_1: 0xffffffff
9950 10:03:58.036990 INFO: [APUAPC] D3_APC_2: 0x3fffff
9951 10:03:58.040066 INFO: [APUAPC] D3_APC_3: 0x0
9952 10:03:58.043240 INFO: [APUAPC] D4_APC_0: 0xffffffff
9953 10:03:58.046414 INFO: [APUAPC] D4_APC_1: 0xffffffff
9954 10:03:58.049970 INFO: [APUAPC] D4_APC_2: 0x3fffff
9955 10:03:58.053787 INFO: [APUAPC] D4_APC_3: 0x0
9956 10:03:58.056257 INFO: [APUAPC] D5_APC_0: 0xffffffff
9957 10:03:58.059599 INFO: [APUAPC] D5_APC_1: 0xffffffff
9958 10:03:58.063769 INFO: [APUAPC] D5_APC_2: 0x3fffff
9959 10:03:58.066104 INFO: [APUAPC] D5_APC_3: 0x0
9960 10:03:58.069739 INFO: [APUAPC] D6_APC_0: 0xffffffff
9961 10:03:58.072535 INFO: [APUAPC] D6_APC_1: 0xffffffff
9962 10:03:58.076090 INFO: [APUAPC] D6_APC_2: 0x3fffff
9963 10:03:58.079141 INFO: [APUAPC] D6_APC_3: 0x0
9964 10:03:58.082772 INFO: [APUAPC] D7_APC_0: 0xffffffff
9965 10:03:58.086137 INFO: [APUAPC] D7_APC_1: 0xffffffff
9966 10:03:58.089371 INFO: [APUAPC] D7_APC_2: 0x3fffff
9967 10:03:58.092958 INFO: [APUAPC] D7_APC_3: 0x0
9968 10:03:58.096090 INFO: [APUAPC] D8_APC_0: 0xffffffff
9969 10:03:58.099524 INFO: [APUAPC] D8_APC_1: 0xffffffff
9970 10:03:58.102860 INFO: [APUAPC] D8_APC_2: 0x3fffff
9971 10:03:58.105967 INFO: [APUAPC] D8_APC_3: 0x0
9972 10:03:58.109234 INFO: [APUAPC] D9_APC_0: 0xffffffff
9973 10:03:58.112713 INFO: [APUAPC] D9_APC_1: 0xffffffff
9974 10:03:58.116000 INFO: [APUAPC] D9_APC_2: 0x3fffff
9975 10:03:58.119204 INFO: [APUAPC] D9_APC_3: 0x0
9976 10:03:58.122430 INFO: [APUAPC] D10_APC_0: 0xffffffff
9977 10:03:58.126007 INFO: [APUAPC] D10_APC_1: 0xffffffff
9978 10:03:58.129304 INFO: [APUAPC] D10_APC_2: 0x3fffff
9979 10:03:58.132036 INFO: [APUAPC] D10_APC_3: 0x0
9980 10:03:58.135504 INFO: [APUAPC] D11_APC_0: 0xffffffff
9981 10:03:58.139159 INFO: [APUAPC] D11_APC_1: 0xffffffff
9982 10:03:58.142153 INFO: [APUAPC] D11_APC_2: 0x3fffff
9983 10:03:58.145012 INFO: [APUAPC] D11_APC_3: 0x0
9984 10:03:58.148671 INFO: [APUAPC] D12_APC_0: 0xffffffff
9985 10:03:58.152381 INFO: [APUAPC] D12_APC_1: 0xffffffff
9986 10:03:58.155171 INFO: [APUAPC] D12_APC_2: 0x3fffff
9987 10:03:58.158847 INFO: [APUAPC] D12_APC_3: 0x0
9988 10:03:58.161579 INFO: [APUAPC] D13_APC_0: 0xffffffff
9989 10:03:58.164915 INFO: [APUAPC] D13_APC_1: 0xffffffff
9990 10:03:58.168520 INFO: [APUAPC] D13_APC_2: 0x3fffff
9991 10:03:58.171739 INFO: [APUAPC] D13_APC_3: 0x0
9992 10:03:58.175149 INFO: [APUAPC] D14_APC_0: 0xffffffff
9993 10:03:58.178044 INFO: [APUAPC] D14_APC_1: 0xffffffff
9994 10:03:58.181561 INFO: [APUAPC] D14_APC_2: 0x3fffff
9995 10:03:58.185067 INFO: [APUAPC] D14_APC_3: 0x0
9996 10:03:58.188487 INFO: [APUAPC] D15_APC_0: 0xffffffff
9997 10:03:58.191395 INFO: [APUAPC] D15_APC_1: 0xffffffff
9998 10:03:58.194318 INFO: [APUAPC] D15_APC_2: 0x3fffff
9999 10:03:58.198321 INFO: [APUAPC] D15_APC_3: 0x0
10000 10:03:58.201688 INFO: [APUAPC] APC_CON: 0x4
10001 10:03:58.204693 INFO: [NOCDAPC] D0_APC_0: 0x0
10002 10:03:58.207625 INFO: [NOCDAPC] D0_APC_1: 0x0
10003 10:03:58.210972 INFO: [NOCDAPC] D1_APC_0: 0x0
10004 10:03:58.214621 INFO: [NOCDAPC] D1_APC_1: 0xfff
10005 10:03:58.217798 INFO: [NOCDAPC] D2_APC_0: 0x0
10006 10:03:58.220674 INFO: [NOCDAPC] D2_APC_1: 0xfff
10007 10:03:58.224703 INFO: [NOCDAPC] D3_APC_0: 0x0
10008 10:03:58.227979 INFO: [NOCDAPC] D3_APC_1: 0xfff
10009 10:03:58.228528 INFO: [NOCDAPC] D4_APC_0: 0x0
10010 10:03:58.230970 INFO: [NOCDAPC] D4_APC_1: 0xfff
10011 10:03:58.234572 INFO: [NOCDAPC] D5_APC_0: 0x0
10012 10:03:58.237672 INFO: [NOCDAPC] D5_APC_1: 0xfff
10013 10:03:58.240855 INFO: [NOCDAPC] D6_APC_0: 0x0
10014 10:03:58.243917 INFO: [NOCDAPC] D6_APC_1: 0xfff
10015 10:03:58.247292 INFO: [NOCDAPC] D7_APC_0: 0x0
10016 10:03:58.250721 INFO: [NOCDAPC] D7_APC_1: 0xfff
10017 10:03:58.254397 INFO: [NOCDAPC] D8_APC_0: 0x0
10018 10:03:58.257015 INFO: [NOCDAPC] D8_APC_1: 0xfff
10019 10:03:58.260159 INFO: [NOCDAPC] D9_APC_0: 0x0
10020 10:03:58.260617 INFO: [NOCDAPC] D9_APC_1: 0xfff
10021 10:03:58.264338 INFO: [NOCDAPC] D10_APC_0: 0x0
10022 10:03:58.267419 INFO: [NOCDAPC] D10_APC_1: 0xfff
10023 10:03:58.270013 INFO: [NOCDAPC] D11_APC_0: 0x0
10024 10:03:58.273739 INFO: [NOCDAPC] D11_APC_1: 0xfff
10025 10:03:58.277477 INFO: [NOCDAPC] D12_APC_0: 0x0
10026 10:03:58.280000 INFO: [NOCDAPC] D12_APC_1: 0xfff
10027 10:03:58.284616 INFO: [NOCDAPC] D13_APC_0: 0x0
10028 10:03:58.286582 INFO: [NOCDAPC] D13_APC_1: 0xfff
10029 10:03:58.289994 INFO: [NOCDAPC] D14_APC_0: 0x0
10030 10:03:58.293612 INFO: [NOCDAPC] D14_APC_1: 0xfff
10031 10:03:58.296676 INFO: [NOCDAPC] D15_APC_0: 0x0
10032 10:03:58.299974 INFO: [NOCDAPC] D15_APC_1: 0xfff
10033 10:03:58.303700 INFO: [NOCDAPC] APC_CON: 0x4
10034 10:03:58.306397 INFO: [APUAPC] set_apusys_apc done
10035 10:03:58.309875 INFO: [DEVAPC] devapc_init done
10036 10:03:58.313239 INFO: GICv3 without legacy support detected.
10037 10:03:58.316572 INFO: ARM GICv3 driver initialized in EL3
10038 10:03:58.319567 INFO: Maximum SPI INTID supported: 639
10039 10:03:58.322816 INFO: BL31: Initializing runtime services
10040 10:03:58.329866 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10041 10:03:58.333421 INFO: SPM: enable CPC mode
10042 10:03:58.339466 INFO: mcdi ready for mcusys-off-idle and system suspend
10043 10:03:58.343011 INFO: BL31: Preparing for EL3 exit to normal world
10044 10:03:58.346899 INFO: Entry point address = 0x80000000
10045 10:03:58.349567 INFO: SPSR = 0x8
10046 10:03:58.354072
10047 10:03:58.354702
10048 10:03:58.355076
10049 10:03:58.357830 Starting depthcharge on Spherion...
10050 10:03:58.358471
10051 10:03:58.358852 Wipe memory regions:
10052 10:03:58.359193
10053 10:03:58.361915 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10054 10:03:58.362530 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10055 10:03:58.362988 Setting prompt string to ['asurada:']
10056 10:03:58.363468 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10057 10:03:58.364191 [0x00000040000000, 0x00000054600000)
10058 10:03:58.483443
10059 10:03:58.483987 [0x00000054660000, 0x00000080000000)
10060 10:03:58.743826
10061 10:03:58.744369 [0x000000821a7280, 0x000000ffe64000)
10062 10:03:59.488738
10063 10:03:59.489335 [0x00000100000000, 0x00000240000000)
10064 10:04:01.378957
10065 10:04:01.382380 Initializing XHCI USB controller at 0x11200000.
10066 10:04:02.419956
10067 10:04:02.423430 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10068 10:04:02.423993
10069 10:04:02.424360
10070 10:04:02.424699
10071 10:04:02.425522 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10073 10:04:02.526982 asurada: tftpboot 192.168.201.1 12073344/tftp-deploy-x5o2dtz4/kernel/image.itb 12073344/tftp-deploy-x5o2dtz4/kernel/cmdline
10074 10:04:02.527636 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10075 10:04:02.528103 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10076 10:04:02.532846 tftpboot 192.168.201.1 12073344/tftp-deploy-x5o2dtz4/kernel/image.itp-deploy-x5o2dtz4/kernel/cmdline
10077 10:04:02.533416
10078 10:04:02.533856 Waiting for link
10079 10:04:02.693698
10080 10:04:02.694283 R8152: Initializing
10081 10:04:02.694663
10082 10:04:02.696530 Version 6 (ocp_data = 5c30)
10083 10:04:02.696919
10084 10:04:02.699744 R8152: Done initializing
10085 10:04:02.700308
10086 10:04:02.700680 Adding net device
10087 10:04:04.661324
10088 10:04:04.661885 done.
10089 10:04:04.662299
10090 10:04:04.662651 MAC: 00:24:32:30:7c:7b
10091 10:04:04.662984
10092 10:04:04.664417 Sending DHCP discover... done.
10093 10:04:04.664895
10094 10:04:14.508092 Waiting for reply... R8152: Bulk read error 0xffffffbf
10095 10:04:14.508673
10096 10:04:14.510960 Receive failed.
10097 10:04:14.511420
10098 10:04:14.511787 done.
10099 10:04:14.512127
10100 10:04:14.514352 Sending DHCP request... done.
10101 10:04:14.514812
10102 10:04:14.521869 Waiting for reply... done.
10103 10:04:14.522442
10104 10:04:14.522790 My ip is 192.168.201.14
10105 10:04:14.523102
10106 10:04:14.525011 The DHCP server ip is 192.168.201.1
10107 10:04:14.525534
10108 10:04:14.531460 TFTP server IP predefined by user: 192.168.201.1
10109 10:04:14.532030
10110 10:04:14.538011 Bootfile predefined by user: 12073344/tftp-deploy-x5o2dtz4/kernel/image.itb
10111 10:04:14.538552
10112 10:04:14.541398 Sending tftp read request... done.
10113 10:04:14.541899
10114 10:04:14.548578 Waiting for the transfer...
10115 10:04:14.549140
10116 10:04:15.242134 00000000 ################################################################
10117 10:04:15.242712
10118 10:04:15.956912 00080000 ################################################################
10119 10:04:15.957420
10120 10:04:16.663731 00100000 ################################################################
10121 10:04:16.664289
10122 10:04:17.358541 00180000 ################################################################
10123 10:04:17.359044
10124 10:04:18.064806 00200000 ################################################################
10125 10:04:18.065334
10126 10:04:18.745508 00280000 ################################################################
10127 10:04:18.745642
10128 10:04:19.351400 00300000 ################################################################
10129 10:04:19.351537
10130 10:04:20.011426 00380000 ################################################################
10131 10:04:20.011938
10132 10:04:20.730029 00400000 ################################################################
10133 10:04:20.730601
10134 10:04:21.461673 00480000 ################################################################
10135 10:04:21.462186
10136 10:04:22.155138 00500000 ################################################################
10137 10:04:22.155669
10138 10:04:22.871488 00580000 ################################################################
10139 10:04:22.872239
10140 10:04:23.594986 00600000 ################################################################
10141 10:04:23.595497
10142 10:04:24.316480 00680000 ################################################################
10143 10:04:24.317067
10144 10:04:25.031237 00700000 ################################################################
10145 10:04:25.031753
10146 10:04:25.726899 00780000 ################################################################
10147 10:04:25.727375
10148 10:04:26.424794 00800000 ################################################################
10149 10:04:26.425294
10150 10:04:27.142760 00880000 ################################################################
10151 10:04:27.143273
10152 10:04:27.853189 00900000 ################################################################
10153 10:04:27.853747
10154 10:04:28.576472 00980000 ################################################################
10155 10:04:28.577191
10156 10:04:29.311685 00a00000 ################################################################
10157 10:04:29.312227
10158 10:04:29.963504 00a80000 ################################################################
10159 10:04:29.963634
10160 10:04:30.621686 00b00000 ################################################################
10161 10:04:30.622205
10162 10:04:31.289679 00b80000 ################################################################
10163 10:04:31.289815
10164 10:04:31.966772 00c00000 ################################################################
10165 10:04:31.967323
10166 10:04:32.668143 00c80000 ################################################################
10167 10:04:32.668715
10168 10:04:33.392029 00d00000 ################################################################
10169 10:04:33.392528
10170 10:04:34.116038 00d80000 ################################################################
10171 10:04:34.116535
10172 10:04:34.837332 00e00000 ################################################################
10173 10:04:34.837927
10174 10:04:35.548086 00e80000 ################################################################
10175 10:04:35.548220
10176 10:04:36.251626 00f00000 ################################################################
10177 10:04:36.252162
10178 10:04:36.979157 00f80000 ################################################################
10179 10:04:36.979694
10180 10:04:37.706064 01000000 ################################################################
10181 10:04:37.706620
10182 10:04:38.376112 01080000 ################################################################
10183 10:04:38.376617
10184 10:04:39.070738 01100000 ################################################################
10185 10:04:39.071230
10186 10:04:39.772314 01180000 ################################################################
10187 10:04:39.772900
10188 10:04:40.459347 01200000 ################################################################
10189 10:04:40.459934
10190 10:04:41.190230 01280000 ################################################################
10191 10:04:41.190800
10192 10:04:41.912259 01300000 ################################################################
10193 10:04:41.912765
10194 10:04:42.631518 01380000 ################################################################
10195 10:04:42.632029
10196 10:04:43.353793 01400000 ################################################################
10197 10:04:43.354382
10198 10:04:44.075031 01480000 ################################################################
10199 10:04:44.075546
10200 10:04:44.802852 01500000 ################################################################
10201 10:04:44.803348
10202 10:04:45.528077 01580000 ################################################################
10203 10:04:45.528583
10204 10:04:46.236508 01600000 ################################################################
10205 10:04:46.236642
10206 10:04:46.922690 01680000 ################################################################
10207 10:04:46.923219
10208 10:04:47.631956 01700000 ################################################################
10209 10:04:47.632735
10210 10:04:48.374039 01780000 ################################################################
10211 10:04:48.374607
10212 10:04:49.103806 01800000 ################################################################
10213 10:04:49.104332
10214 10:04:49.807601 01880000 ################################################################
10215 10:04:49.808148
10216 10:04:50.525161 01900000 ################################################################
10217 10:04:50.525683
10218 10:04:51.243794 01980000 ################################################################
10219 10:04:51.244335
10220 10:04:51.936684 01a00000 ################################################################
10221 10:04:51.937185
10222 10:04:52.661983 01a80000 ################################################################
10223 10:04:52.662550
10224 10:04:53.381561 01b00000 ################################################################
10225 10:04:53.382107
10226 10:04:53.457239 01b80000 ####### done.
10227 10:04:53.457794
10228 10:04:53.461522 The bootfile was 28888422 bytes long.
10229 10:04:53.462290
10230 10:04:53.464213 Sending tftp read request... done.
10231 10:04:53.464669
10232 10:04:53.468078 Waiting for the transfer...
10233 10:04:53.468562
10234 10:04:53.468931 00000000 # done.
10235 10:04:53.469283
10236 10:04:53.474867 Command line loaded dynamically from TFTP file: 12073344/tftp-deploy-x5o2dtz4/kernel/cmdline
10237 10:04:53.477826
10238 10:04:53.497620 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12073344/extract-nfsrootfs-d95w75f3,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10239 10:04:53.498131
10240 10:04:53.501432 Loading FIT.
10241 10:04:53.501951
10242 10:04:53.502353 Image ramdisk-1 has 17791565 bytes.
10243 10:04:53.504221
10244 10:04:53.504596 Image fdt-1 has 47278 bytes.
10245 10:04:53.504912
10246 10:04:53.507958 Image kernel-1 has 11047542 bytes.
10247 10:04:53.508372
10248 10:04:53.517702 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10249 10:04:53.518214
10250 10:04:53.534045 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10251 10:04:53.534701
10252 10:04:53.540498 Choosing best match conf-1 for compat google,spherion-rev2.
10253 10:04:53.544915
10254 10:04:53.548971 Connected to device vid:did:rid of 1ae0:0028:00
10255 10:04:53.555673
10256 10:04:53.558830 tpm_get_response: command 0x17b, return code 0x0
10257 10:04:53.559243
10258 10:04:53.562103 ec_init: CrosEC protocol v3 supported (256, 248)
10259 10:04:53.567522
10260 10:04:53.571015 tpm_cleanup: add release locality here.
10261 10:04:53.571530
10262 10:04:53.572007 Shutting down all USB controllers.
10263 10:04:53.574152
10264 10:04:53.574602 Removing current net device
10265 10:04:53.574950
10266 10:04:53.580824 Exiting depthcharge with code 4 at timestamp: 84458814
10267 10:04:53.581334
10268 10:04:53.583990 LZMA decompressing kernel-1 to 0x821a6718
10269 10:04:53.584402
10270 10:04:53.587110 LZMA decompressing kernel-1 to 0x40000000
10271 10:04:54.975814
10272 10:04:54.976351 jumping to kernel
10273 10:04:54.978635 end: 2.2.4 bootloader-commands (duration 00:00:57) [common]
10274 10:04:54.979155 start: 2.2.5 auto-login-action (timeout 00:03:29) [common]
10275 10:04:54.979565 Setting prompt string to ['Linux version [0-9]']
10276 10:04:54.979934 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10277 10:04:54.980312 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10278 10:04:55.057574
10279 10:04:55.060992 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10280 10:04:55.064698 start: 2.2.5.1 login-action (timeout 00:03:29) [common]
10281 10:04:55.065196 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10282 10:04:55.065589 Setting prompt string to []
10283 10:04:55.065993 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10284 10:04:55.066486 Using line separator: #'\n'#
10285 10:04:55.066848 No login prompt set.
10286 10:04:55.067214 Parsing kernel messages
10287 10:04:55.067529 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10288 10:04:55.068080 [login-action] Waiting for messages, (timeout 00:03:29)
10289 10:04:55.084130 [ 0.000000] Linux version 6.1.62-cip9 (KernelCI@build-j22848-arm64-gcc-10-defconfig-arm64-chromebook-6q8mw) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Nov 24 09:44:51 UTC 2023
10290 10:04:55.087152 [ 0.000000] random: crng init done
10291 10:04:55.094032 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10292 10:04:55.097165 [ 0.000000] efi: UEFI not found.
10293 10:04:55.103556 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10294 10:04:55.113245 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10295 10:04:55.123406 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10296 10:04:55.129729 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10297 10:04:55.136802 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10298 10:04:55.143129 [ 0.000000] printk: bootconsole [mtk8250] enabled
10299 10:04:55.149882 [ 0.000000] NUMA: No NUMA configuration found
10300 10:04:55.156187 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10301 10:04:55.163099 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10302 10:04:55.163634 [ 0.000000] Zone ranges:
10303 10:04:55.169178 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10304 10:04:55.172391 [ 0.000000] DMA32 empty
10305 10:04:55.179436 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10306 10:04:55.182890 [ 0.000000] Movable zone start for each node
10307 10:04:55.185955 [ 0.000000] Early memory node ranges
10308 10:04:55.192328 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10309 10:04:55.199664 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10310 10:04:55.205858 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10311 10:04:55.212046 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10312 10:04:55.218671 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10313 10:04:55.225179 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10314 10:04:55.281747 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10315 10:04:55.288391 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10316 10:04:55.295149 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10317 10:04:55.298663 [ 0.000000] psci: probing for conduit method from DT.
10318 10:04:55.305455 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10319 10:04:55.308155 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10320 10:04:55.314725 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10321 10:04:55.318064 [ 0.000000] psci: SMC Calling Convention v1.2
10322 10:04:55.324482 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10323 10:04:55.327991 [ 0.000000] Detected VIPT I-cache on CPU0
10324 10:04:55.335008 [ 0.000000] CPU features: detected: GIC system register CPU interface
10325 10:04:55.340896 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10326 10:04:55.347928 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10327 10:04:55.354182 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10328 10:04:55.364688 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10329 10:04:55.371211 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10330 10:04:55.374665 [ 0.000000] alternatives: applying boot alternatives
10331 10:04:55.381786 [ 0.000000] Fallback order for Node 0: 0
10332 10:04:55.387398 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10333 10:04:55.390612 [ 0.000000] Policy zone: Normal
10334 10:04:55.413702 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12073344/extract-nfsrootfs-d95w75f3,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10335 10:04:55.423469 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10336 10:04:55.434565 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10337 10:04:55.444663 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10338 10:04:55.451636 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10339 10:04:55.454649 <6>[ 0.000000] software IO TLB: area num 8.
10340 10:04:55.511997 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10341 10:04:55.660577 <6>[ 0.000000] Memory: 7952244K/8385536K available (17984K kernel code, 4116K rwdata, 17312K rodata, 8384K init, 615K bss, 400524K reserved, 32768K cma-reserved)
10342 10:04:55.666886 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10343 10:04:55.673410 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10344 10:04:55.676883 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10345 10:04:55.683229 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10346 10:04:55.690762 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10347 10:04:55.693195 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10348 10:04:55.703390 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10349 10:04:55.709762 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10350 10:04:55.716242 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10351 10:04:55.722481 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10352 10:04:55.725949 <6>[ 0.000000] GICv3: 608 SPIs implemented
10353 10:04:55.729666 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10354 10:04:55.736137 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10355 10:04:55.739172 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10356 10:04:55.746744 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10357 10:04:55.759207 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10358 10:04:55.772821 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10359 10:04:55.779047 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10360 10:04:55.786933 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10361 10:04:55.799824 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10362 10:04:55.806059 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10363 10:04:55.812963 <6>[ 0.009226] Console: colour dummy device 80x25
10364 10:04:55.823229 <6>[ 0.013979] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10365 10:04:55.829924 <6>[ 0.024485] pid_max: default: 32768 minimum: 301
10366 10:04:55.834211 <6>[ 0.029358] LSM: Security Framework initializing
10367 10:04:55.840095 <6>[ 0.034327] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10368 10:04:55.849919 <6>[ 0.042157] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10369 10:04:55.859670 <6>[ 0.051562] cblist_init_generic: Setting adjustable number of callback queues.
10370 10:04:55.862993 <6>[ 0.059003] cblist_init_generic: Setting shift to 3 and lim to 1.
10371 10:04:55.872730 <6>[ 0.065342] cblist_init_generic: Setting adjustable number of callback queues.
10372 10:04:55.879584 <6>[ 0.072768] cblist_init_generic: Setting shift to 3 and lim to 1.
10373 10:04:55.883058 <6>[ 0.079167] rcu: Hierarchical SRCU implementation.
10374 10:04:55.889376 <6>[ 0.084183] rcu: Max phase no-delay instances is 1000.
10375 10:04:55.895850 <6>[ 0.091203] EFI services will not be available.
10376 10:04:55.899279 <6>[ 0.096156] smp: Bringing up secondary CPUs ...
10377 10:04:55.908188 <6>[ 0.101231] Detected VIPT I-cache on CPU1
10378 10:04:55.914501 <6>[ 0.101301] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10379 10:04:55.921013 <6>[ 0.101334] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10380 10:04:55.924357 <6>[ 0.101672] Detected VIPT I-cache on CPU2
10381 10:04:55.934055 <6>[ 0.101723] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10382 10:04:55.940419 <6>[ 0.101741] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10383 10:04:55.944343 <6>[ 0.102002] Detected VIPT I-cache on CPU3
10384 10:04:55.950463 <6>[ 0.102052] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10385 10:04:55.957074 <6>[ 0.102066] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10386 10:04:55.963505 <6>[ 0.102368] CPU features: detected: Spectre-v4
10387 10:04:55.967213 <6>[ 0.102375] CPU features: detected: Spectre-BHB
10388 10:04:55.970326 <6>[ 0.102380] Detected PIPT I-cache on CPU4
10389 10:04:55.976674 <6>[ 0.102438] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10390 10:04:55.986246 <6>[ 0.102455] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10391 10:04:55.989626 <6>[ 0.102746] Detected PIPT I-cache on CPU5
10392 10:04:55.996915 <6>[ 0.102808] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10393 10:04:56.003300 <6>[ 0.102824] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10394 10:04:56.005938 <6>[ 0.103103] Detected PIPT I-cache on CPU6
10395 10:04:56.016675 <6>[ 0.103167] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10396 10:04:56.022628 <6>[ 0.103183] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10397 10:04:56.026029 <6>[ 0.103480] Detected PIPT I-cache on CPU7
10398 10:04:56.033178 <6>[ 0.103545] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10399 10:04:56.039922 <6>[ 0.103561] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10400 10:04:56.042663 <6>[ 0.103609] smp: Brought up 1 node, 8 CPUs
10401 10:04:56.049377 <6>[ 0.244895] SMP: Total of 8 processors activated.
10402 10:04:56.055307 <6>[ 0.249816] CPU features: detected: 32-bit EL0 Support
10403 10:04:56.063255 <6>[ 0.255212] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10404 10:04:56.068892 <6>[ 0.264013] CPU features: detected: Common not Private translations
10405 10:04:56.075197 <6>[ 0.270529] CPU features: detected: CRC32 instructions
10406 10:04:56.082132 <6>[ 0.275880] CPU features: detected: RCpc load-acquire (LDAPR)
10407 10:04:56.085984 <6>[ 0.281839] CPU features: detected: LSE atomic instructions
10408 10:04:56.091529 <6>[ 0.287621] CPU features: detected: Privileged Access Never
10409 10:04:56.098828 <6>[ 0.293400] CPU features: detected: RAS Extension Support
10410 10:04:56.105422 <6>[ 0.299009] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10411 10:04:56.108796 <6>[ 0.306227] CPU: All CPU(s) started at EL2
10412 10:04:56.115007 <6>[ 0.310543] alternatives: applying system-wide alternatives
10413 10:04:56.125177 <6>[ 0.321282] devtmpfs: initialized
10414 10:04:56.140901 <6>[ 0.330100] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10415 10:04:56.147135 <6>[ 0.340063] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10416 10:04:56.154021 <6>[ 0.348254] pinctrl core: initialized pinctrl subsystem
10417 10:04:56.157683 <6>[ 0.354922] DMI not present or invalid.
10418 10:04:56.164101 <6>[ 0.359335] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10419 10:04:56.173757 <6>[ 0.366213] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10420 10:04:56.179814 <6>[ 0.373798] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10421 10:04:56.190185 <6>[ 0.382020] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10422 10:04:56.193806 <6>[ 0.390261] audit: initializing netlink subsys (disabled)
10423 10:04:56.202977 <5>[ 0.395955] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10424 10:04:56.210290 <6>[ 0.396649] thermal_sys: Registered thermal governor 'step_wise'
10425 10:04:56.216581 <6>[ 0.403922] thermal_sys: Registered thermal governor 'power_allocator'
10426 10:04:56.220158 <6>[ 0.410180] cpuidle: using governor menu
10427 10:04:56.226319 <6>[ 0.421138] NET: Registered PF_QIPCRTR protocol family
10428 10:04:56.232913 <6>[ 0.426632] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10429 10:04:56.239820 <6>[ 0.433737] ASID allocator initialised with 32768 entries
10430 10:04:56.242810 <6>[ 0.440296] Serial: AMBA PL011 UART driver
10431 10:04:56.252936 <4>[ 0.449064] Trying to register duplicate clock ID: 134
10432 10:04:56.308665 <6>[ 0.506534] KASLR enabled
10433 10:04:56.321597 <6>[ 0.514189] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10434 10:04:56.328014 <6>[ 0.521203] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10435 10:04:56.334889 <6>[ 0.527694] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10436 10:04:56.341486 <6>[ 0.534700] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10437 10:04:56.347689 <6>[ 0.541187] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10438 10:04:56.354120 <6>[ 0.548189] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10439 10:04:56.361124 <6>[ 0.554677] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10440 10:04:56.367283 <6>[ 0.561682] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10441 10:04:56.371165 <6>[ 0.569173] ACPI: Interpreter disabled.
10442 10:04:56.379403 <6>[ 0.575570] iommu: Default domain type: Translated
10443 10:04:56.385868 <6>[ 0.580681] iommu: DMA domain TLB invalidation policy: strict mode
10444 10:04:56.390228 <5>[ 0.587332] SCSI subsystem initialized
10445 10:04:56.396185 <6>[ 0.591496] usbcore: registered new interface driver usbfs
10446 10:04:56.402940 <6>[ 0.597227] usbcore: registered new interface driver hub
10447 10:04:56.406438 <6>[ 0.602779] usbcore: registered new device driver usb
10448 10:04:56.413347 <6>[ 0.608875] pps_core: LinuxPPS API ver. 1 registered
10449 10:04:56.422914 <6>[ 0.614069] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10450 10:04:56.425928 <6>[ 0.623415] PTP clock support registered
10451 10:04:56.429618 <6>[ 0.627656] EDAC MC: Ver: 3.0.0
10452 10:04:56.437638 <6>[ 0.632812] FPGA manager framework
10453 10:04:56.443111 <6>[ 0.636489] Advanced Linux Sound Architecture Driver Initialized.
10454 10:04:56.446650 <6>[ 0.643259] vgaarb: loaded
10455 10:04:56.452949 <6>[ 0.646446] clocksource: Switched to clocksource arch_sys_counter
10456 10:04:56.456666 <5>[ 0.652877] VFS: Disk quotas dquot_6.6.0
10457 10:04:56.463174 <6>[ 0.657062] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10458 10:04:56.466652 <6>[ 0.664245] pnp: PnP ACPI: disabled
10459 10:04:56.475077 <6>[ 0.670863] NET: Registered PF_INET protocol family
10460 10:04:56.485016 <6>[ 0.676446] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10461 10:04:56.495872 <6>[ 0.688720] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10462 10:04:56.506054 <6>[ 0.697533] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10463 10:04:56.512795 <6>[ 0.705501] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10464 10:04:56.519525 <6>[ 0.714202] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10465 10:04:56.531633 <6>[ 0.723952] TCP: Hash tables configured (established 65536 bind 65536)
10466 10:04:56.537568 <6>[ 0.730808] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10467 10:04:56.545110 <6>[ 0.738006] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10468 10:04:56.551305 <6>[ 0.745702] NET: Registered PF_UNIX/PF_LOCAL protocol family
10469 10:04:56.557509 <6>[ 0.751868] RPC: Registered named UNIX socket transport module.
10470 10:04:56.560981 <6>[ 0.758020] RPC: Registered udp transport module.
10471 10:04:56.567582 <6>[ 0.762953] RPC: Registered tcp transport module.
10472 10:04:56.573823 <6>[ 0.767884] RPC: Registered tcp NFSv4.1 backchannel transport module.
10473 10:04:56.577558 <6>[ 0.774551] PCI: CLS 0 bytes, default 64
10474 10:04:56.580448 <6>[ 0.778966] Unpacking initramfs...
10475 10:04:56.590524 <6>[ 0.783183] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10476 10:04:56.600225 <6>[ 0.791817] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10477 10:04:56.603695 <6>[ 0.800658] kvm [1]: IPA Size Limit: 40 bits
10478 10:04:56.610339 <6>[ 0.805183] kvm [1]: GICv3: no GICV resource entry
10479 10:04:56.613649 <6>[ 0.810207] kvm [1]: disabling GICv2 emulation
10480 10:04:56.620400 <6>[ 0.814893] kvm [1]: GIC system register CPU interface enabled
10481 10:04:56.623781 <6>[ 0.821067] kvm [1]: vgic interrupt IRQ18
10482 10:04:56.630118 <6>[ 0.825428] kvm [1]: VHE mode initialized successfully
10483 10:04:56.637240 <5>[ 0.831956] Initialise system trusted keyrings
10484 10:04:56.643676 <6>[ 0.836750] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10485 10:04:56.650498 <6>[ 0.846784] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10486 10:04:56.657452 <5>[ 0.853184] NFS: Registering the id_resolver key type
10487 10:04:56.660511 <5>[ 0.858491] Key type id_resolver registered
10488 10:04:56.667084 <5>[ 0.862906] Key type id_legacy registered
10489 10:04:56.674046 <6>[ 0.867196] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10490 10:04:56.680390 <6>[ 0.874116] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10491 10:04:56.687090 <6>[ 0.881818] 9p: Installing v9fs 9p2000 file system support
10492 10:04:56.724173 <5>[ 0.919746] Key type asymmetric registered
10493 10:04:56.727446 <5>[ 0.924079] Asymmetric key parser 'x509' registered
10494 10:04:56.737349 <6>[ 0.929223] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10495 10:04:56.740717 <6>[ 0.936833] io scheduler mq-deadline registered
10496 10:04:56.743776 <6>[ 0.941594] io scheduler kyber registered
10497 10:04:56.763245 <6>[ 0.958811] EINJ: ACPI disabled.
10498 10:04:56.794968 <4>[ 0.984454] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10499 10:04:56.805157 <4>[ 0.995201] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10500 10:04:56.820123 <6>[ 1.016137] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10501 10:04:56.828053 <6>[ 1.024151] printk: console [ttyS0] disabled
10502 10:04:56.856287 <6>[ 1.048814] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10503 10:04:56.862577 <6>[ 1.058295] printk: console [ttyS0] enabled
10504 10:04:56.865841 <6>[ 1.058295] printk: console [ttyS0] enabled
10505 10:04:56.872832 <6>[ 1.067185] printk: bootconsole [mtk8250] disabled
10506 10:04:56.876110 <6>[ 1.067185] printk: bootconsole [mtk8250] disabled
10507 10:04:56.882105 <6>[ 1.078449] SuperH (H)SCI(F) driver initialized
10508 10:04:56.885812 <6>[ 1.083728] msm_serial: driver initialized
10509 10:04:56.900027 <6>[ 1.092729] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10510 10:04:56.909606 <6>[ 1.101276] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10511 10:04:56.916245 <6>[ 1.109819] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10512 10:04:56.926242 <6>[ 1.118452] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10513 10:04:56.936427 <6>[ 1.127160] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10514 10:04:56.943049 <6>[ 1.135873] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10515 10:04:56.952917 <6>[ 1.144417] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10516 10:04:56.959738 <6>[ 1.153222] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10517 10:04:56.969734 <6>[ 1.161769] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10518 10:04:56.981970 <6>[ 1.177334] loop: module loaded
10519 10:04:56.988249 <6>[ 1.183240] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10520 10:04:57.010742 <4>[ 1.206679] mtk-pmic-keys: Failed to locate of_node [id: -1]
10521 10:04:57.017802 <6>[ 1.213557] megasas: 07.719.03.00-rc1
10522 10:04:57.027360 <6>[ 1.223170] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10523 10:04:57.034199 <6>[ 1.229838] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10524 10:04:57.050858 <6>[ 1.246394] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10525 10:04:57.107135 <6>[ 1.296120] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10526 10:04:57.329949 <6>[ 1.526125] Freeing initrd memory: 17372K
10527 10:04:57.340567 <6>[ 1.536629] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10528 10:04:57.351420 <6>[ 1.547706] tun: Universal TUN/TAP device driver, 1.6
10529 10:04:57.355214 <6>[ 1.553795] thunder_xcv, ver 1.0
10530 10:04:57.358512 <6>[ 1.557298] thunder_bgx, ver 1.0
10531 10:04:57.361948 <6>[ 1.560796] nicpf, ver 1.0
10532 10:04:57.371757 <6>[ 1.564816] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10533 10:04:57.375453 <6>[ 1.572292] hns3: Copyright (c) 2017 Huawei Corporation.
10534 10:04:57.382309 <6>[ 1.577885] hclge is initializing
10535 10:04:57.385051 <6>[ 1.581469] e1000: Intel(R) PRO/1000 Network Driver
10536 10:04:57.392098 <6>[ 1.586598] e1000: Copyright (c) 1999-2006 Intel Corporation.
10537 10:04:57.395450 <6>[ 1.592611] e1000e: Intel(R) PRO/1000 Network Driver
10538 10:04:57.402492 <6>[ 1.597827] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10539 10:04:57.408980 <6>[ 1.604012] igb: Intel(R) Gigabit Ethernet Network Driver
10540 10:04:57.415595 <6>[ 1.609662] igb: Copyright (c) 2007-2014 Intel Corporation.
10541 10:04:57.422406 <6>[ 1.615499] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10542 10:04:57.428590 <6>[ 1.622018] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10543 10:04:57.432788 <6>[ 1.628487] sky2: driver version 1.30
10544 10:04:57.438508 <6>[ 1.633483] VFIO - User Level meta-driver version: 0.3
10545 10:04:57.446410 <6>[ 1.641707] usbcore: registered new interface driver usb-storage
10546 10:04:57.452615 <6>[ 1.648156] usbcore: registered new device driver onboard-usb-hub
10547 10:04:57.461458 <6>[ 1.657362] mt6397-rtc mt6359-rtc: registered as rtc0
10548 10:04:57.471503 <6>[ 1.662829] mt6397-rtc mt6359-rtc: setting system clock to 2023-11-24T10:04:59 UTC (1700820299)
10549 10:04:57.474893 <6>[ 1.672416] i2c_dev: i2c /dev entries driver
10550 10:04:57.491708 <6>[ 1.684256] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10551 10:04:57.511032 <6>[ 1.707274] cpu cpu0: EM: created perf domain
10552 10:04:57.514712 <6>[ 1.712198] cpu cpu4: EM: created perf domain
10553 10:04:57.521527 <6>[ 1.717817] sdhci: Secure Digital Host Controller Interface driver
10554 10:04:57.528543 <6>[ 1.724249] sdhci: Copyright(c) Pierre Ossman
10555 10:04:57.534930 <6>[ 1.729200] Synopsys Designware Multimedia Card Interface Driver
10556 10:04:57.541767 <6>[ 1.735831] sdhci-pltfm: SDHCI platform and OF driver helper
10557 10:04:57.545142 <6>[ 1.735881] mmc0: CQHCI version 5.10
10558 10:04:57.551894 <6>[ 1.745742] ledtrig-cpu: registered to indicate activity on CPUs
10559 10:04:57.558475 <6>[ 1.752649] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10560 10:04:57.565167 <6>[ 1.759701] usbcore: registered new interface driver usbhid
10561 10:04:57.568804 <6>[ 1.765526] usbhid: USB HID core driver
10562 10:04:57.575026 <6>[ 1.769723] spi_master spi0: will run message pump with realtime priority
10563 10:04:57.618600 <6>[ 1.808086] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10564 10:04:57.637168 <6>[ 1.823194] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10565 10:04:57.641355 <6>[ 1.836808] mmc0: Command Queue Engine enabled
10566 10:04:57.648009 <6>[ 1.841594] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10567 10:04:57.654089 <6>[ 1.848537] cros-ec-spi spi0.0: Chrome EC device registered
10568 10:04:57.657954 <6>[ 1.848918] mmcblk0: mmc0:0001 DA4128 116 GiB
10569 10:04:57.669370 <6>[ 1.865341] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10570 10:04:57.676686 <6>[ 1.872670] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10571 10:04:57.683157 <6>[ 1.878834] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10572 10:04:57.690101 <6>[ 1.884846] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10573 10:04:57.699469 <6>[ 1.884921] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10574 10:04:57.706440 <6>[ 1.901957] NET: Registered PF_PACKET protocol family
10575 10:04:57.709730 <6>[ 1.907417] 9pnet: Installing 9P2000 support
10576 10:04:57.716738 <5>[ 1.911987] Key type dns_resolver registered
10577 10:04:57.719874 <6>[ 1.916981] registered taskstats version 1
10578 10:04:57.726687 <5>[ 1.921363] Loading compiled-in X.509 certificates
10579 10:04:57.757301 <4>[ 1.946866] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10580 10:04:57.767534 <4>[ 1.957756] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10581 10:04:57.774304 <3>[ 1.968313] debugfs: File 'uA_load' in directory '/' already present!
10582 10:04:57.780974 <3>[ 1.975023] debugfs: File 'min_uV' in directory '/' already present!
10583 10:04:57.787048 <3>[ 1.981633] debugfs: File 'max_uV' in directory '/' already present!
10584 10:04:57.794044 <3>[ 1.988246] debugfs: File 'constraint_flags' in directory '/' already present!
10585 10:04:57.805403 <3>[ 1.998035] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10586 10:04:57.820837 <6>[ 2.016583] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10587 10:04:57.827954 <6>[ 2.023504] xhci-mtk 11200000.usb: xHCI Host Controller
10588 10:04:57.834288 <6>[ 2.029009] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10589 10:04:57.844466 <6>[ 2.036880] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10590 10:04:57.851058 <6>[ 2.046317] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10591 10:04:57.857517 <6>[ 2.052420] xhci-mtk 11200000.usb: xHCI Host Controller
10592 10:04:57.864736 <6>[ 2.057907] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10593 10:04:57.870675 <6>[ 2.065577] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10594 10:04:57.877564 <6>[ 2.073474] hub 1-0:1.0: USB hub found
10595 10:04:57.881683 <6>[ 2.077510] hub 1-0:1.0: 1 port detected
10596 10:04:57.890904 <6>[ 2.081828] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10597 10:04:57.893712 <6>[ 2.090631] hub 2-0:1.0: USB hub found
10598 10:04:57.897199 <6>[ 2.094659] hub 2-0:1.0: 1 port detected
10599 10:04:57.906239 <6>[ 2.102499] mtk-msdc 11f70000.mmc: Got CD GPIO
10600 10:04:57.917084 <6>[ 2.110094] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10601 10:04:57.924046 <6>[ 2.118142] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10602 10:04:57.934220 <4>[ 2.126074] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10603 10:04:57.943669 <6>[ 2.135649] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10604 10:04:57.950609 <6>[ 2.143733] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10605 10:04:57.956929 <6>[ 2.151753] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10606 10:04:57.966869 <6>[ 2.159670] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10607 10:04:57.973741 <6>[ 2.167487] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10608 10:04:57.983629 <6>[ 2.175304] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10609 10:04:57.993423 <6>[ 2.185639] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10610 10:04:58.000620 <6>[ 2.194009] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10611 10:04:58.010001 <6>[ 2.202352] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10612 10:04:58.016737 <6>[ 2.210696] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10613 10:04:58.026979 <6>[ 2.219035] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10614 10:04:58.033477 <6>[ 2.227374] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10615 10:04:58.043411 <6>[ 2.235714] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10616 10:04:58.050093 <6>[ 2.244051] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10617 10:04:58.059726 <6>[ 2.252396] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10618 10:04:58.066335 <6>[ 2.260735] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10619 10:04:58.076087 <6>[ 2.269074] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10620 10:04:58.086323 <6>[ 2.277412] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10621 10:04:58.092853 <6>[ 2.285750] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10622 10:04:58.102529 <6>[ 2.294087] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10623 10:04:58.109534 <6>[ 2.302426] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10624 10:04:58.115863 <6>[ 2.311137] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10625 10:04:58.122838 <6>[ 2.318316] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10626 10:04:58.129592 <6>[ 2.325094] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10627 10:04:58.136037 <6>[ 2.331857] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10628 10:04:58.146462 <6>[ 2.338788] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10629 10:04:58.152912 <6>[ 2.345631] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10630 10:04:58.162882 <6>[ 2.354757] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10631 10:04:58.172368 <6>[ 2.363876] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10632 10:04:58.182412 <6>[ 2.373169] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10633 10:04:58.192099 <6>[ 2.382641] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10634 10:04:58.199184 <6>[ 2.392109] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10635 10:04:58.208534 <6>[ 2.401229] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10636 10:04:58.218929 <6>[ 2.410701] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10637 10:04:58.228462 <6>[ 2.419820] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10638 10:04:58.238856 <6>[ 2.429114] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10639 10:04:58.248283 <6>[ 2.439274] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10640 10:04:58.255137 <6>[ 2.442748] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10641 10:04:58.264883 <6>[ 2.450716] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10642 10:04:58.271206 <6>[ 2.466096] Trying to probe devices needed for running init ...
10643 10:04:58.285701 <6>[ 2.481786] hub 2-1:1.0: USB hub found
10644 10:04:58.288752 <6>[ 2.486236] hub 2-1:1.0: 3 ports detected
10645 10:04:58.297556 <6>[ 2.493528] hub 2-1:1.0: USB hub found
10646 10:04:58.301016 <6>[ 2.497967] hub 2-1:1.0: 3 ports detected
10647 10:04:58.410045 <6>[ 2.602709] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10648 10:04:58.564996 <6>[ 2.760855] hub 1-1:1.0: USB hub found
10649 10:04:58.568028 <6>[ 2.765367] hub 1-1:1.0: 4 ports detected
10650 10:04:58.578349 <6>[ 2.774048] hub 1-1:1.0: USB hub found
10651 10:04:58.581703 <6>[ 2.778419] hub 1-1:1.0: 4 ports detected
10652 10:04:58.650323 <6>[ 2.843010] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10653 10:04:58.901953 <6>[ 3.094754] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10654 10:04:59.034347 <6>[ 3.230681] hub 1-1.4:1.0: USB hub found
10655 10:04:59.038112 <6>[ 3.235350] hub 1-1.4:1.0: 2 ports detected
10656 10:04:59.047922 <6>[ 3.243827] hub 1-1.4:1.0: USB hub found
10657 10:04:59.051406 <6>[ 3.248433] hub 1-1.4:1.0: 2 ports detected
10658 10:04:59.349974 <6>[ 3.542730] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10659 10:04:59.541788 <6>[ 3.734728] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10660 10:05:10.567137 <6>[ 14.767757] ALSA device list:
10661 10:05:10.573302 <6>[ 14.771047] No soundcards found.
10662 10:05:10.581621 <6>[ 14.778951] Freeing unused kernel memory: 8384K
10663 10:05:10.585016 <6>[ 14.783936] Run /init as init process
10664 10:05:10.595348 Loading, please wait...
10665 10:05:10.616019 Starting version 247.3-7+deb11u2
10666 10:05:10.812973 <6>[ 15.007513] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10667 10:05:10.827357 <6>[ 15.021677] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10668 10:05:10.834025 <6>[ 15.021719] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10669 10:05:10.844175 <6>[ 15.037856] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10670 10:05:10.852833 <6>[ 15.050085] usbcore: registered new interface driver r8152
10671 10:05:10.859244 <6>[ 15.056555] remoteproc remoteproc0: scp is available
10672 10:05:10.868987 <3>[ 15.061930] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10673 10:05:10.872041 <6>[ 15.062139] remoteproc remoteproc0: powering up scp
10674 10:05:10.882106 <3>[ 15.070105] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10675 10:05:10.888899 <4>[ 15.071821] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10676 10:05:10.892157 <6>[ 15.072153] mc: Linux media interface: v0.10
10677 10:05:10.899197 <4>[ 15.072853] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10678 10:05:10.908884 <6>[ 15.075315] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10679 10:05:10.915487 <3>[ 15.083308] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10680 10:05:10.922172 <6>[ 15.090625] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10681 10:05:10.932416 <3>[ 15.100026] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10682 10:05:10.938626 <3>[ 15.132672] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10683 10:05:10.945178 <3>[ 15.140753] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10684 10:05:10.955658 <6>[ 15.146283] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10685 10:05:10.962164 <3>[ 15.148845] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10686 10:05:10.967922 <3>[ 15.148851] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10687 10:05:10.977865 <3>[ 15.154579] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10688 10:05:10.984910 <6>[ 15.156297] videodev: Linux video capture interface: v2.00
10689 10:05:10.991954 <6>[ 15.157317] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10690 10:05:10.998087 <3>[ 15.164167] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10691 10:05:11.004736 <6>[ 15.171997] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10692 10:05:11.011449 <6>[ 15.172005] pci_bus 0000:00: root bus resource [bus 00-ff]
10693 10:05:11.017694 <6>[ 15.172013] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10694 10:05:11.027765 <6>[ 15.172019] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10695 10:05:11.034508 <6>[ 15.172056] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10696 10:05:11.041253 <6>[ 15.172079] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10697 10:05:11.048543 <6>[ 15.172177] pci 0000:00:00.0: supports D1 D2
10698 10:05:11.054781 <6>[ 15.172181] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10699 10:05:11.061536 <6>[ 15.175186] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10700 10:05:11.070936 <4>[ 15.177641] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10701 10:05:11.080892 <4>[ 15.177647] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10702 10:05:11.087462 <3>[ 15.180305] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10703 10:05:11.098851 <3>[ 15.180308] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10704 10:05:11.104859 <3>[ 15.180351] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10705 10:05:11.114939 <6>[ 15.181009] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10706 10:05:11.125102 <6>[ 15.181150] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10707 10:05:11.131254 <6>[ 15.181309] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10708 10:05:11.138412 <6>[ 15.186289] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10709 10:05:11.148683 <3>[ 15.193697] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10710 10:05:11.154880 <3>[ 15.193702] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10711 10:05:11.161700 <6>[ 15.201858] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10712 10:05:11.171567 <3>[ 15.208645] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10713 10:05:11.178662 <6>[ 15.209026] usbcore: registered new interface driver cdc_ether
10714 10:05:11.184364 <6>[ 15.214521] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10715 10:05:11.191086 <6>[ 15.214794] usbcore: registered new interface driver r8153_ecm
10716 10:05:11.197477 <3>[ 15.221514] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10717 10:05:11.207260 <3>[ 15.221579] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10718 10:05:11.210812 <6>[ 15.222587] r8152 2-1.3:1.0 eth0: v1.12.13
10719 10:05:11.217026 <6>[ 15.227751] r8152 2-1.3:1.0 enx002432307c7b: renamed from eth0
10720 10:05:11.223909 <6>[ 15.228180] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10721 10:05:11.230590 <6>[ 15.231466] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10722 10:05:11.240740 <6>[ 15.231516] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10723 10:05:11.243784 <6>[ 15.231721] pci 0000:01:00.0: supports D1 D2
10724 10:05:11.250780 <6>[ 15.231726] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10725 10:05:11.253838 <6>[ 15.232353] Bluetooth: Core ver 2.22
10726 10:05:11.260404 <6>[ 15.232397] NET: Registered PF_BLUETOOTH protocol family
10727 10:05:11.267231 <6>[ 15.232409] Bluetooth: HCI device and connection manager initialized
10728 10:05:11.273897 <6>[ 15.232429] Bluetooth: HCI socket layer initialized
10729 10:05:11.277059 <6>[ 15.232433] Bluetooth: L2CAP socket layer initialized
10730 10:05:11.283492 <6>[ 15.232442] Bluetooth: SCO socket layer initialized
10731 10:05:11.290559 <6>[ 15.238793] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10732 10:05:11.296670 <6>[ 15.242546] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10733 10:05:11.307135 <6>[ 15.242585] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10734 10:05:11.313205 <6>[ 15.242588] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10735 10:05:11.323138 <6>[ 15.242597] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10736 10:05:11.329718 <6>[ 15.242610] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10737 10:05:11.335787 <6>[ 15.242623] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10738 10:05:11.342607 <6>[ 15.242635] pci 0000:00:00.0: PCI bridge to [bus 01]
10739 10:05:11.349081 <6>[ 15.242640] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10740 10:05:11.356015 <6>[ 15.242771] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10741 10:05:11.362867 <6>[ 15.243216] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10742 10:05:11.368665 <6>[ 15.243609] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10743 10:05:11.375435 <6>[ 15.245694] remoteproc remoteproc0: remote processor scp is now up
10744 10:05:11.381891 <6>[ 15.250220] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10745 10:05:11.392414 <6>[ 15.252876] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10746 10:05:11.399035 <4>[ 15.262687] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10747 10:05:11.405467 <4>[ 15.262687] Fallback method does not support PEC.
10748 10:05:11.418416 <6>[ 15.266364] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10749 10:05:11.425481 <5>[ 15.288139] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10750 10:05:11.431378 <6>[ 15.291160] usbcore: registered new interface driver uvcvideo
10751 10:05:11.438449 <6>[ 15.291918] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10752 10:05:11.444868 <6>[ 15.307228] usbcore: registered new interface driver btusb
10753 10:05:11.451103 <3>[ 15.307598] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10754 10:05:11.461354 <4>[ 15.308032] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10755 10:05:11.468294 <3>[ 15.308041] Bluetooth: hci0: Failed to load firmware file (-2)
10756 10:05:11.474197 <3>[ 15.308044] Bluetooth: hci0: Failed to set up firmware (-2)
10757 10:05:11.484171 <4>[ 15.308047] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10758 10:05:11.490918 <5>[ 15.310048] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10759 10:05:11.500500 <4>[ 15.310099] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10760 10:05:11.503748 <6>[ 15.310104] cfg80211: failed to load regulatory.db
10761 10:05:11.513789 <3>[ 15.330153] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10762 10:05:11.520720 <6>[ 15.405829] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10763 10:05:11.526789 <6>[ 15.724315] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10764 10:05:11.553433 <6>[ 15.750622] mt7921e 0000:01:00.0: ASIC revision: 79610010
10765 10:05:11.659059 <4>[ 15.849799] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10766 10:05:11.674974 Begin: Loading essential drivers ... done.
10767 10:05:11.677685 Begin: Running /scripts/init-premount ... done.
10768 10:05:11.684540 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10769 10:05:11.694373 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10770 10:05:11.697977 Device /sys/class/net/enx002432307c7b found
10771 10:05:11.701426 done.
10772 10:05:11.736312 IP-Config: enx002432307c7b hardware address 00:24:32:30:7c:7b mtu 1500 DHCP
10773 10:05:11.777898 <4>[ 15.969070] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10774 10:05:11.896569 <4>[ 16.087762] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10775 10:05:12.012591 <4>[ 16.203541] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10776 10:05:12.128295 <4>[ 16.319472] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10777 10:05:12.244154 <4>[ 16.435383] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10778 10:05:12.360326 <4>[ 16.551350] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10779 10:05:12.476716 <4>[ 16.667303] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10780 10:05:12.592114 <4>[ 16.783315] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10781 10:05:12.708047 <4>[ 16.899256] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10782 10:05:12.726840 <6>[ 16.924550] r8152 2-1.3:1.0 enx002432307c7b: carrier on
10783 10:05:12.815653 <3>[ 17.013236] mt7921e 0000:01:00.0: hardware init failed
10784 10:05:12.965141 IP-Config: no response after 2 secs - giving up
10785 10:05:13.012129 IP-Config: enx002432307c7b hardware address 00:24:32:30:7c:7b mtu 1500 DHCP
10786 10:05:13.019231 IP-Config: enx002432307c7b complete (dhcp from 192.168.201.1):
10787 10:05:13.025920 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10788 10:05:13.032239 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10789 10:05:13.038888 host : mt8192-asurada-spherion-r0-cbg-2
10790 10:05:13.045208 domain : lava-rack
10791 10:05:13.048392 rootserver: 192.168.201.1 rootpath:
10792 10:05:13.051344 filename :
10793 10:05:13.108803 done.
10794 10:05:13.116981 Begin: Running /scripts/nfs-bottom ... done.
10795 10:05:13.131915 Begin: Running /scripts/init-bottom ... done.
10796 10:05:14.414379 <6>[ 18.612509] NET: Registered PF_INET6 protocol family
10797 10:05:14.421817 <6>[ 18.619642] Segment Routing with IPv6
10798 10:05:14.424745 <6>[ 18.623623] In-situ OAM (IOAM) with IPv6
10799 10:05:14.558397 <30>[ 18.736669] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10800 10:05:14.564754 <30>[ 18.761110] systemd[1]: Detected architecture arm64.
10801 10:05:14.586666
10802 10:05:14.589358 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10803 10:05:14.589793
10804 10:05:14.611680 <30>[ 18.809911] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10805 10:05:15.589291 <30>[ 19.784363] systemd[1]: Queued start job for default target Graphical Interface.
10806 10:05:15.630678 <30>[ 19.829025] systemd[1]: Created slice system-getty.slice.
10807 10:05:15.637286 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10808 10:05:15.653855 <30>[ 19.852097] systemd[1]: Created slice system-modprobe.slice.
10809 10:05:15.660268 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10810 10:05:15.678012 <30>[ 19.875969] systemd[1]: Created slice system-serial\x2dgetty.slice.
10811 10:05:15.688015 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10812 10:05:15.701299 <30>[ 19.899771] systemd[1]: Created slice User and Session Slice.
10813 10:05:15.708279 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10814 10:05:15.728887 <30>[ 19.923595] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10815 10:05:15.738635 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10816 10:05:15.756886 <30>[ 19.951477] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10817 10:05:15.763410 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10818 10:05:15.787679 <30>[ 19.978899] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10819 10:05:15.793986 <30>[ 19.991120] systemd[1]: Reached target Local Encrypted Volumes.
10820 10:05:15.800618 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10821 10:05:15.816859 <30>[ 20.014872] systemd[1]: Reached target Paths.
10822 10:05:15.823855 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10823 10:05:15.836741 <30>[ 20.034714] systemd[1]: Reached target Remote File Systems.
10824 10:05:15.843535 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10825 10:05:15.860299 <30>[ 20.058722] systemd[1]: Reached target Slices.
10826 10:05:15.866869 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10827 10:05:15.880830 <30>[ 20.078816] systemd[1]: Reached target Swap.
10828 10:05:15.883952 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10829 10:05:15.904476 <30>[ 20.099156] systemd[1]: Listening on initctl Compatibility Named Pipe.
10830 10:05:15.911079 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10831 10:05:15.917585 <30>[ 20.115468] systemd[1]: Listening on Journal Audit Socket.
10832 10:05:15.924126 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10833 10:05:15.942138 <30>[ 20.140251] systemd[1]: Listening on Journal Socket (/dev/log).
10834 10:05:15.949176 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10835 10:05:15.965110 <30>[ 20.163286] systemd[1]: Listening on Journal Socket.
10836 10:05:15.971753 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10837 10:05:15.989998 <30>[ 20.184432] systemd[1]: Listening on Network Service Netlink Socket.
10838 10:05:15.996231 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10839 10:05:16.011930 <30>[ 20.210272] systemd[1]: Listening on udev Control Socket.
10840 10:05:16.018389 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10841 10:05:16.032968 <30>[ 20.231156] systemd[1]: Listening on udev Kernel Socket.
10842 10:05:16.039567 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10843 10:05:16.096593 <30>[ 20.294874] systemd[1]: Mounting Huge Pages File System...
10844 10:05:16.103139 Mounting [0;1;39mHuge Pages File System[0m...
10845 10:05:16.120604 <30>[ 20.318758] systemd[1]: Mounting POSIX Message Queue File System...
10846 10:05:16.127674 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10847 10:05:16.180709 <30>[ 20.379169] systemd[1]: Mounting Kernel Debug File System...
10848 10:05:16.187210 Mounting [0;1;39mKernel Debug File System[0m...
10849 10:05:16.204514 <30>[ 20.399199] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10850 10:05:16.227397 <30>[ 20.422292] systemd[1]: Starting Create list of static device nodes for the current kernel...
10851 10:05:16.233790 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10852 10:05:16.257498 <30>[ 20.455619] systemd[1]: Starting Load Kernel Module configfs...
10853 10:05:16.263735 Starting [0;1;39mLoad Kernel Module configfs[0m...
10854 10:05:16.281423 <30>[ 20.479419] systemd[1]: Starting Load Kernel Module drm...
10855 10:05:16.287455 Starting [0;1;39mLoad Kernel Module drm[0m...
10856 10:05:16.305637 <30>[ 20.503359] systemd[1]: Starting Load Kernel Module fuse...
10857 10:05:16.311530 Starting [0;1;39mLoad Kernel Module fuse[0m...
10858 10:05:16.333133 <30>[ 20.528220] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10859 10:05:16.351166 <6>[ 20.549155] fuse: init (API version 7.37)
10860 10:05:16.373093 <30>[ 20.571280] systemd[1]: Starting Journal Service...
10861 10:05:16.376851 Starting [0;1;39mJournal Service[0m...
10862 10:05:16.402695 <30>[ 20.600157] systemd[1]: Starting Load Kernel Modules...
10863 10:05:16.408162 Starting [0;1;39mLoad Kernel Modules[0m...
10864 10:05:16.427406 <30>[ 20.622365] systemd[1]: Starting Remount Root and Kernel File Systems...
10865 10:05:16.434051 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10866 10:05:16.458532 <30>[ 20.656724] systemd[1]: Starting Coldplug All udev Devices...
10867 10:05:16.465163 Starting [0;1;39mColdplug All udev Devices[0m...
10868 10:05:16.486924 <30>[ 20.685129] systemd[1]: Mounted Huge Pages File System.
10869 10:05:16.493656 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10870 10:05:16.508544 <30>[ 20.707226] systemd[1]: Mounted POSIX Message Queue File System.
10871 10:05:16.515564 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10872 10:05:16.527485 <3>[ 20.722756] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10873 10:05:16.536877 <30>[ 20.735334] systemd[1]: Mounted Kernel Debug File System.
10874 10:05:16.543378 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10875 10:05:16.563025 <3>[ 20.757985] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10876 10:05:16.573500 <30>[ 20.768257] systemd[1]: Finished Create list of static device nodes for the current kernel.
10877 10:05:16.583113 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10878 10:05:16.599434 <30>[ 20.796661] systemd[1]: modprobe@configfs.service: Succeeded.
10879 10:05:16.608726 <3>[ 20.803027] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10880 10:05:16.615279 <30>[ 20.803663] systemd[1]: Finished Load Kernel Module configfs.
10881 10:05:16.621505 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10882 10:05:16.638591 <30>[ 20.835794] systemd[1]: modprobe@drm.service: Succeeded.
10883 10:05:16.648102 <3>[ 20.842359] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10884 10:05:16.655282 <30>[ 20.842684] systemd[1]: Finished Load Kernel Module drm.
10885 10:05:16.661442 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10886 10:05:16.677199 <30>[ 20.875391] systemd[1]: modprobe@fuse.service: Succeeded.
10887 10:05:16.686951 <3>[ 20.875985] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10888 10:05:16.693745 <30>[ 20.881763] systemd[1]: Finished Load Kernel Module fuse.
10889 10:05:16.697120 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10890 10:05:16.715676 <3>[ 20.910298] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10891 10:05:16.722809 <30>[ 20.921057] systemd[1]: Finished Load Kernel Modules.
10892 10:05:16.729389 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10893 10:05:16.745448 <3>[ 20.940160] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10894 10:05:16.755913 <30>[ 20.950769] systemd[1]: Finished Remount Root and Kernel File Systems.
10895 10:05:16.762675 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10896 10:05:16.775627 <3>[ 20.970072] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10897 10:05:16.804629 <3>[ 20.999604] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10898 10:05:16.811301 <30>[ 21.004788] systemd[1]: Mounting FUSE Control File System...
10899 10:05:16.817804 Mounting [0;1;39mFUSE Control File System[0m...
10900 10:05:16.834661 <3>[ 21.029473] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10901 10:05:16.848501 <30>[ 21.043197] systemd[1]: Mounting Kernel Configuration File System...
10902 10:05:16.851702 Mounting [0;1;39mKernel Configuration File System[0m...
10903 10:05:16.878873 <30>[ 21.073477] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10904 10:05:16.888548 <30>[ 21.082721] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10905 10:05:16.921398 <30>[ 21.119794] systemd[1]: Starting Load/Save Random Seed...
10906 10:05:16.928242 Starting [0;1;39mLoad/Save Random Seed[0m...
10907 10:05:16.943214 <30>[ 21.141352] systemd[1]: Starting Apply Kernel Variables...
10908 10:05:16.959665 <4>[ 21.141672] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10909 10:05:16.966794 <3>[ 21.162879] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10910 10:05:16.973575 Starting [0;1;39mApply Kernel Variables[0m...
10911 10:05:16.992572 <30>[ 21.190814] systemd[1]: Starting Create System Users...
10912 10:05:16.999454 Starting [0;1;39mCreate System Users[0m...
10913 10:05:17.014868 <30>[ 21.213379] systemd[1]: Started Journal Service.
10914 10:05:17.021413 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10915 10:05:17.046206 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10916 10:05:17.060683 See 'systemctl status systemd-udev-trigger.service' for details.
10917 10:05:17.077127 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10918 10:05:17.092572 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10919 10:05:17.113530 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10920 10:05:17.129081 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10921 10:05:17.145940 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10922 10:05:17.194058 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10923 10:05:17.215652 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10924 10:05:17.263441 <46>[ 21.458059] systemd-journald[291]: Received client request to flush runtime journal.
10925 10:05:18.233216 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10926 10:05:18.248604 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10927 10:05:18.263861 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10928 10:05:18.319494 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10929 10:05:18.713427 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10930 10:05:18.777017 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10931 10:05:18.839210 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10932 10:05:18.896265 Starting [0;1;39mNetwork Service[0m...
10933 10:05:19.196551 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10934 10:05:19.217284 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10935 10:05:19.271656 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10936 10:05:19.572864 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10937 10:05:19.591590 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10938 10:05:19.629489 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10939 10:05:19.650544 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10940 10:05:19.668378 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10941 10:05:19.698576 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10942 10:05:19.743885 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10943 10:05:19.796998 Starting [0;1;39mNetwork Name Resolution[0m...
10944 10:05:19.822972 Starting [0;1;39mNetwork Time Synchronization[0m...
10945 10:05:19.838818 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10946 10:05:19.900882 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10947 10:05:20.054543 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10948 10:05:20.072580 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10949 10:05:20.091585 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10950 10:05:20.104443 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10951 10:05:20.120073 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10952 10:05:20.154350 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10953 10:05:20.218142 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10954 10:05:20.261674 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10955 10:05:20.310061 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10956 10:05:20.324103 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10957 10:05:20.349915 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10958 10:05:20.363952 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10959 10:05:20.381718 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10960 10:05:20.428903 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10961 10:05:21.136424 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10962 10:05:21.593133 Starting [0;1;39mUser Login Management[0m...
10963 10:05:21.614301 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10964 10:05:21.638787 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10965 10:05:21.655967 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10966 10:05:21.700470 Starting [0;1;39mPermit User Sessions[0m...
10967 10:05:21.755782 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10968 10:05:21.770335 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10969 10:05:21.804206 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10970 10:05:21.856630 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10971 10:05:21.872689 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10972 10:05:21.930401 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10973 10:05:21.939156 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10974 10:05:21.957559 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10975 10:05:22.018908 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10976 10:05:22.070825 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10977 10:05:22.173622
10978 10:05:22.174122
10979 10:05:22.177419 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10980 10:05:22.177830
10981 10:05:22.180288 debian-bullseye-arm64 login: root (automatic login)
10982 10:05:22.180702
10983 10:05:22.181074
10984 10:05:22.608931 Linux debian-bullseye-arm64 6.1.62-cip9 #1 SMP PREEMPT Fri Nov 24 09:44:51 UTC 2023 aarch64
10985 10:05:22.609425
10986 10:05:22.615772 The programs included with the Debian GNU/Linux system are free software;
10987 10:05:22.622245 the exact distribution terms for each program are described in the
10988 10:05:22.625378 individual files in /usr/share/doc/*/copyright.
10989 10:05:22.625789
10990 10:05:22.632092 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10991 10:05:22.635112 permitted by applicable law.
10992 10:05:23.769134 Matched prompt #10: / #
10994 10:05:23.770446 Setting prompt string to ['/ #']
10995 10:05:23.770892 end: 2.2.5.1 login-action (duration 00:00:29) [common]
10997 10:05:23.771878 end: 2.2.5 auto-login-action (duration 00:00:29) [common]
10998 10:05:23.772322 start: 2.2.6 expect-shell-connection (timeout 00:03:00) [common]
10999 10:05:23.772666 Setting prompt string to ['/ #']
11000 10:05:23.772970 Forcing a shell prompt, looking for ['/ #']
11002 10:05:23.823872 / #
11003 10:05:23.824519 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11004 10:05:23.825125 Waiting using forced prompt support (timeout 00:02:30)
11005 10:05:23.830663
11006 10:05:23.831775 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11007 10:05:23.832479 start: 2.2.7 export-device-env (timeout 00:03:00) [common]
11009 10:05:23.933910 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12073344/extract-nfsrootfs-d95w75f3'
11010 10:05:23.940810 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12073344/extract-nfsrootfs-d95w75f3'
11012 10:05:24.042731 / # export NFS_SERVER_IP='192.168.201.1'
11013 10:05:24.049487 export NFS_SERVER_IP='192.168.201.1'
11014 10:05:24.050500 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11015 10:05:24.051045 end: 2.2 depthcharge-retry (duration 00:02:00) [common]
11016 10:05:24.051562 end: 2 depthcharge-action (duration 00:02:00) [common]
11017 10:05:24.052070 start: 3 lava-test-retry (timeout 00:07:16) [common]
11018 10:05:24.052543 start: 3.1 lava-test-shell (timeout 00:07:16) [common]
11019 10:05:24.052952 Using namespace: common
11021 10:05:24.154241 / # #
11022 10:05:24.154914 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11023 10:05:24.160387 #
11024 10:05:24.161235 Using /lava-12073344
11026 10:05:24.262664 / # export SHELL=/bin/bash
11027 10:05:24.269573 export SHELL=/bin/bash
11029 10:05:24.371333 / # . /lava-12073344/environment
11030 10:05:24.378342 . /lava-12073344/environment
11032 10:05:24.486792 / # /lava-12073344/bin/lava-test-runner /lava-12073344/0
11033 10:05:24.487434 Test shell timeout: 10s (minimum of the action and connection timeout)
11034 10:05:24.493068 /lava-12073344/bin/lava-test-runner /lava-12073344/0
11035 10:05:24.863989 + export TESTRUN_ID=0_timesync-off
11036 10:05:24.867086 + TESTRUN_ID=0_timesync-off
11037 10:05:24.869874 + cd /lava-12073344/0/tests/0_timesync-off
11038 10:05:24.873313 ++ cat uuid
11039 10:05:24.883764 + UUID=12073344_1.6.2.3.1
11040 10:05:24.884342 + set +x
11041 10:05:24.889831 <LAVA_SIGNAL_STARTRUN 0_timesync-off 12073344_1.6.2.3.1>
11042 10:05:24.890714 Received signal: <STARTRUN> 0_timesync-off 12073344_1.6.2.3.1
11043 10:05:24.891118 Starting test lava.0_timesync-off (12073344_1.6.2.3.1)
11044 10:05:24.891522 Skipping test definition patterns.
11045 10:05:24.893511 + systemctl stop systemd-timesyncd
11046 10:05:24.954719 + set +x
11047 10:05:24.957596 <LAVA_SIGNAL_ENDRUN 0_timesync-off 12073344_1.6.2.3.1>
11048 10:05:24.958354 Received signal: <ENDRUN> 0_timesync-off 12073344_1.6.2.3.1
11049 10:05:24.958935 Ending use of test pattern.
11050 10:05:24.959271 Ending test lava.0_timesync-off (12073344_1.6.2.3.1), duration 0.07
11052 10:05:25.063594 + export TESTRUN_ID=1_kselftest-arm64
11053 10:05:25.064136 + TESTRUN_ID=1_kselftest-arm64
11054 10:05:25.070363 + cd /lava-12073344/0/tests/1_kselftest-arm64
11055 10:05:25.070786 ++ cat uuid
11056 10:05:25.079808 + UUID=12073344_1.6.2.3.5
11057 10:05:25.080222 + set +x
11058 10:05:25.085681 <LAVA_SIGNAL_STARTRUN 1_kselftest-arm64 12073344_1.6.2.3.5>
11059 10:05:25.086383 Received signal: <STARTRUN> 1_kselftest-arm64 12073344_1.6.2.3.5
11060 10:05:25.086768 Starting test lava.1_kselftest-arm64 (12073344_1.6.2.3.5)
11061 10:05:25.087285 Skipping test definition patterns.
11062 10:05:25.089114 + cd ./automated/linux/kselftest/
11063 10:05:25.115539 + ./kselftest.sh -c arm64 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11064 10:05:25.174960 INFO: install_deps skipped
11065 10:05:25.326043 --2023-11-24 10:05:25-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11066 10:05:25.344413 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11067 10:05:25.477507 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11068 10:05:25.612052 HTTP request sent, awaiting response... 200 OK
11069 10:05:25.614044 Length: 2964448 (2.8M) [application/octet-stream]
11070 10:05:25.617741 Saving to: 'kselftest.tar.xz'
11071 10:05:25.618334
11072 10:05:25.618708
11073 10:05:25.876841 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11074 10:05:26.145889 kselftest.tar.xz 1%[ ] 47.81K 181KB/s
11075 10:05:26.593659 kselftest.tar.xz 7%[> ] 219.84K 413KB/s
11076 10:05:26.870226 kselftest.tar.xz 27%[====> ] 804.33K 820KB/s
11077 10:05:27.081585 kselftest.tar.xz 79%[==============> ] 2.24M 1.78MB/s
11078 10:05:27.087629 kselftest.tar.xz 100%[===================>] 2.83M 1.93MB/s
11079 10:05:27.094218 kselftest.tar.xz 100%[===================>] 2.83M 1.93MB/s in 1.5s
11080 10:05:27.094754
11081 10:05:27.346923 2023-11-24 10:05:27 (1.93 MB/s) - 'kselftest.tar.xz' saved [2964448/2964448]
11082 10:05:27.347311
11083 10:05:34.463289 skiplist:
11084 10:05:34.466510 ========================================
11085 10:05:34.470046 ========================================
11086 10:05:34.529319 arm64:tags_test
11087 10:05:34.532556 arm64:run_tags_test.sh
11088 10:05:34.532966 arm64:fake_sigreturn_bad_magic
11089 10:05:34.535933 arm64:fake_sigreturn_bad_size
11090 10:05:34.539227 arm64:fake_sigreturn_bad_size_for_magic0
11091 10:05:34.542523 arm64:fake_sigreturn_duplicated_fpsimd
11092 10:05:34.545612 arm64:fake_sigreturn_misaligned_sp
11093 10:05:34.549077 arm64:fake_sigreturn_missing_fpsimd
11094 10:05:34.553233 arm64:fake_sigreturn_sme_change_vl
11095 10:05:34.555578 arm64:fake_sigreturn_sve_change_vl
11096 10:05:34.558887 arm64:mangle_pstate_invalid_compat_toggle
11097 10:05:34.562142 arm64:mangle_pstate_invalid_daif_bits
11098 10:05:34.565674 arm64:mangle_pstate_invalid_mode_el1h
11099 10:05:34.568953 arm64:mangle_pstate_invalid_mode_el1t
11100 10:05:34.572595 arm64:mangle_pstate_invalid_mode_el2h
11101 10:05:34.575153 arm64:mangle_pstate_invalid_mode_el2t
11102 10:05:34.582005 arm64:mangle_pstate_invalid_mode_el3h
11103 10:05:34.585623 arm64:mangle_pstate_invalid_mode_el3t
11104 10:05:34.586038 arm64:sme_trap_no_sm
11105 10:05:34.588876 arm64:sme_trap_non_streaming
11106 10:05:34.589290 arm64:sme_trap_za
11107 10:05:34.591669 arm64:sme_vl
11108 10:05:34.592081 arm64:ssve_regs
11109 10:05:34.594609 arm64:sve_regs
11110 10:05:34.594690 arm64:sve_vl
11111 10:05:34.594754 arm64:za_no_regs
11112 10:05:34.598063 arm64:za_regs
11113 10:05:34.598144 arm64:pac
11114 10:05:34.601060 arm64:fp-stress
11115 10:05:34.601140 arm64:sve-ptrace
11116 10:05:34.604630 arm64:sve-probe-vls
11117 10:05:34.604710 arm64:vec-syscfg
11118 10:05:34.608294 arm64:za-fork
11119 10:05:34.608374 arm64:za-ptrace
11120 10:05:34.611032 arm64:check_buffer_fill
11121 10:05:34.611113 arm64:check_child_memory
11122 10:05:34.614572 arm64:check_gcr_el1_cswitch
11123 10:05:34.617914 arm64:check_ksm_options
11124 10:05:34.617999 arm64:check_mmap_options
11125 10:05:34.621534 arm64:check_prctl
11126 10:05:34.624959 arm64:check_tags_inclusion
11127 10:05:34.625374 arm64:check_user_mem
11128 10:05:34.628307 arm64:btitest
11129 10:05:34.628722 arm64:nobtitest
11130 10:05:34.629050 arm64:hwcap
11131 10:05:34.631738 arm64:ptrace
11132 10:05:34.632155 arm64:syscall-abi
11133 10:05:34.634668 arm64:tpidr2
11134 10:05:34.638151 ============== Tests to run ===============
11135 10:05:34.638606 arm64:tags_test
11136 10:05:34.641069 arm64:run_tags_test.sh
11137 10:05:34.644404 arm64:fake_sigreturn_bad_magic
11138 10:05:34.647631 arm64:fake_sigreturn_bad_size
11139 10:05:34.651157 arm64:fake_sigreturn_bad_size_for_magic0
11140 10:05:34.654770 arm64:fake_sigreturn_duplicated_fpsimd
11141 10:05:34.657934 arm64:fake_sigreturn_misaligned_sp
11142 10:05:34.661201 arm64:fake_sigreturn_missing_fpsimd
11143 10:05:34.664170 arm64:fake_sigreturn_sme_change_vl
11144 10:05:34.667584 arm64:fake_sigreturn_sve_change_vl
11145 10:05:34.670704 arm64:mangle_pstate_invalid_compat_toggle
11146 10:05:34.674169 arm64:mangle_pstate_invalid_daif_bits
11147 10:05:34.677369 arm64:mangle_pstate_invalid_mode_el1h
11148 10:05:34.680793 arm64:mangle_pstate_invalid_mode_el1t
11149 10:05:34.684130 arm64:mangle_pstate_invalid_mode_el2h
11150 10:05:34.687555 arm64:mangle_pstate_invalid_mode_el2t
11151 10:05:34.691098 arm64:mangle_pstate_invalid_mode_el3h
11152 10:05:34.694323 arm64:mangle_pstate_invalid_mode_el3t
11153 10:05:34.694736 arm64:sme_trap_no_sm
11154 10:05:34.697398 arm64:sme_trap_non_streaming
11155 10:05:34.700578 arm64:sme_trap_za
11156 10:05:34.700990 arm64:sme_vl
11157 10:05:34.704005 arm64:ssve_regs
11158 10:05:34.704413 arm64:sve_regs
11159 10:05:34.704733 arm64:sve_vl
11160 10:05:34.707407 arm64:za_no_regs
11161 10:05:34.707816 arm64:za_regs
11162 10:05:34.708136 arm64:pac
11163 10:05:34.710538 arm64:fp-stress
11164 10:05:34.710949 arm64:sve-ptrace
11165 10:05:34.713595 arm64:sve-probe-vls
11166 10:05:34.714003 arm64:vec-syscfg
11167 10:05:34.717231 arm64:za-fork
11168 10:05:34.717642 arm64:za-ptrace
11169 10:05:34.720221 arm64:check_buffer_fill
11170 10:05:34.723708 arm64:check_child_memory
11171 10:05:34.724119 arm64:check_gcr_el1_cswitch
11172 10:05:34.727051 arm64:check_ksm_options
11173 10:05:34.730177 arm64:check_mmap_options
11174 10:05:34.730608 arm64:check_prctl
11175 10:05:34.733566 arm64:check_tags_inclusion
11176 10:05:34.736994 arm64:check_user_mem
11177 10:05:34.737405 arm64:btitest
11178 10:05:34.737731 arm64:nobtitest
11179 10:05:34.740219 arm64:hwcap
11180 10:05:34.740632 arm64:ptrace
11181 10:05:34.743285 arm64:syscall-abi
11182 10:05:34.743692 arm64:tpidr2
11183 10:05:34.746532 ===========End Tests to run ===============
11184 10:05:34.750015 shardfile-arm64 pass
11185 10:05:35.098916 <12>[ 39.299592] kselftest: Running tests in arm64
11186 10:05:35.111213 TAP version 13
11187 10:05:35.126349 1..48
11188 10:05:35.146558 # selftests: arm64: tags_test
11189 10:05:35.617161 ok 1 selftests: arm64: tags_test
11190 10:05:35.637343 # selftests: arm64: run_tags_test.sh
11191 10:05:35.703859 # --------------------
11192 10:05:35.707397 # running tags test
11193 10:05:35.707817 # --------------------
11194 10:05:35.710652 # [PASS]
11195 10:05:35.713893 ok 2 selftests: arm64: run_tags_test.sh
11196 10:05:35.729282 # selftests: arm64: fake_sigreturn_bad_magic
11197 10:05:35.784064 # Registered handlers for all signals.
11198 10:05:35.784490 # Detected MINSTKSIGSZ:4720
11199 10:05:35.787486 # Testcase initialized.
11200 10:05:35.790535 # uc context validated.
11201 10:05:35.794084 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11202 10:05:35.797252 # Handled SIG_COPYCTX
11203 10:05:35.797694 # Available space:3568
11204 10:05:35.803916 # Using badly built context - ERR: BAD MAGIC !
11205 10:05:35.810583 # SIG_OK -- SP:0xFFFFCA9DB3A0 si_addr@:0xffffca9db3a0 si_code:2 token@:0xffffca9da140 offset:-4704
11206 10:05:35.814013 # ==>> completed. PASS(1)
11207 10:05:35.820689 # # FAKE_SIGRETURN_BAD_MAGIC :: Trigger a sigreturn with a sigframe with a bad magic
11208 10:05:35.826917 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFCA9DA140
11209 10:05:35.833703 ok 3 selftests: arm64: fake_sigreturn_bad_magic
11210 10:05:35.837487 # selftests: arm64: fake_sigreturn_bad_size
11211 10:05:35.886007 # Registered handlers for all signals.
11212 10:05:35.886595 # Detected MINSTKSIGSZ:4720
11213 10:05:35.889483 # Testcase initialized.
11214 10:05:35.892658 # uc context validated.
11215 10:05:35.895544 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11216 10:05:35.898716 # Handled SIG_COPYCTX
11217 10:05:35.899168 # Available space:3568
11218 10:05:35.902356 # uc context validated.
11219 10:05:35.909181 # Using badly built context - ERR: Bad size for esr_context
11220 10:05:35.915942 # SIG_OK -- SP:0xFFFFDBF6E3D0 si_addr@:0xffffdbf6e3d0 si_code:2 token@:0xffffdbf6d170 offset:-4704
11221 10:05:35.918962 # ==>> completed. PASS(1)
11222 10:05:35.925407 # # FAKE_SIGRETURN_BAD_SIZE :: Triggers a sigreturn with a overrun __reserved area
11223 10:05:35.932085 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFDBF6D170
11224 10:05:35.936024 ok 4 selftests: arm64: fake_sigreturn_bad_size
11225 10:05:35.942077 # selftests: arm64: fake_sigreturn_bad_size_for_magic0
11226 10:05:36.005045 # Registered handlers for all signals.
11227 10:05:36.005627 # Detected MINSTKSIGSZ:4720
11228 10:05:36.008026 # Testcase initialized.
11229 10:05:36.010976 # uc context validated.
11230 10:05:36.014912 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11231 10:05:36.018050 # Handled SIG_COPYCTX
11232 10:05:36.018693 # Available space:3568
11233 10:05:36.024792 # Using badly built context - ERR: Bad size for terminator
11234 10:05:36.034072 # SIG_OK -- SP:0xFFFFD94B7A30 si_addr@:0xffffd94b7a30 si_code:2 token@:0xffffd94b67d0 offset:-4704
11235 10:05:36.034688 # ==>> completed. PASS(1)
11236 10:05:36.044204 # # FAKE_SIGRETURN_BAD_SIZE_FOR_TERMINATOR :: Trigger a sigreturn using non-zero size terminator
11237 10:05:36.050744 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFD94B67D0
11238 10:05:36.054686 ok 5 selftests: arm64: fake_sigreturn_bad_size_for_magic0
11239 10:05:36.060564 # selftests: arm64: fake_sigreturn_duplicated_fpsimd
11240 10:05:36.116714 # Registered handlers for all signals.
11241 10:05:36.117280 # Detected MINSTKSIGSZ:4720
11242 10:05:36.119414 # Testcase initialized.
11243 10:05:36.122800 # uc context validated.
11244 10:05:36.126200 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11245 10:05:36.129044 # Handled SIG_COPYCTX
11246 10:05:36.129527 # Available space:3568
11247 10:05:36.135812 # Using badly built context - ERR: Multiple FPSIMD_MAGIC
11248 10:05:36.145871 # SIG_OK -- SP:0xFFFFE65C69F0 si_addr@:0xffffe65c69f0 si_code:2 token@:0xffffe65c5790 offset:-4704
11249 10:05:36.146335 # ==>> completed. PASS(1)
11250 10:05:36.155639 # # FAKE_SIGRETURN_DUPLICATED_FPSIMD :: Triggers a sigreturn including two fpsimd_context
11251 10:05:36.162458 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFE65C5790
11252 10:05:36.165434 ok 6 selftests: arm64: fake_sigreturn_duplicated_fpsimd
11253 10:05:36.168699 # selftests: arm64: fake_sigreturn_misaligned_sp
11254 10:05:36.199736 # Registered handlers for all signals.
11255 10:05:36.200228 # Detected MINSTKSIGSZ:4720
11256 10:05:36.203581 # Testcase initialized.
11257 10:05:36.206744 # uc context validated.
11258 10:05:36.210342 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11259 10:05:36.212999 # Handled SIG_COPYCTX
11260 10:05:36.219745 # SIG_OK -- SP:0xFFFFE09C75A3 si_addr@:0xffffe09c75a3 si_code:2 token@:0xffffe09c75a3 offset:0
11261 10:05:36.223442 # ==>> completed. PASS(1)
11262 10:05:36.229570 # # FAKE_SIGRETURN_MISALIGNED_SP :: Triggers a sigreturn with a misaligned sigframe
11263 10:05:36.236547 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFE09C75A3
11264 10:05:36.242549 ok 7 selftests: arm64: fake_sigreturn_misaligned_sp
11265 10:05:36.245952 # selftests: arm64: fake_sigreturn_missing_fpsimd
11266 10:05:36.305495 # Registered handlers for all signals.
11267 10:05:36.306043 # Detected MINSTKSIGSZ:4720
11268 10:05:36.309038 # Testcase initialized.
11269 10:05:36.311851 # uc context validated.
11270 10:05:36.315127 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11271 10:05:36.318596 # Handled SIG_COPYCTX
11272 10:05:36.321789 # Mangling template header. Spare space:4096
11273 10:05:36.325367 # Using badly built context - ERR: Missing FPSIMD
11274 10:05:36.334816 # SIG_OK -- SP:0xFFFFEE60CFF0 si_addr@:0xffffee60cff0 si_code:2 token@:0xffffee60bd90 offset:-4704
11275 10:05:36.337970 # ==>> completed. PASS(1)
11276 10:05:36.344419 # # FAKE_SIGRETURN_MISSING_FPSIMD :: Triggers a sigreturn with a missing fpsimd_context
11277 10:05:36.351107 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFEE60BD90
11278 10:05:36.354508 ok 8 selftests: arm64: fake_sigreturn_missing_fpsimd
11279 10:05:36.361085 # selftests: arm64: fake_sigreturn_sme_change_vl
11280 10:05:36.398170 # Registered handlers for all signals.
11281 10:05:36.398891 # Detected MINSTKSIGSZ:4720
11282 10:05:36.401569 # ==>> completed. SKIP.
11283 10:05:36.408571 # # FAKE_SIGRETURN_SSVE_CHANGE :: Attempt to change Streaming SVE VL
11284 10:05:36.411283 ok 9 selftests: arm64: fake_sigreturn_sme_change_vl # SKIP
11285 10:05:36.420250 # selftests: arm64: fake_sigreturn_sve_change_vl
11286 10:05:36.497677 # Registered handlers for all signals.
11287 10:05:36.498221 # Detected MINSTKSIGSZ:4720
11288 10:05:36.501190 # ==>> completed. SKIP.
11289 10:05:36.504420 # # FAKE_SIGRETURN_SVE_CHANGE :: Attempt to change SVE VL
11290 10:05:36.511037 ok 10 selftests: arm64: fake_sigreturn_sve_change_vl # SKIP
11291 10:05:36.521607 # selftests: arm64: mangle_pstate_invalid_compat_toggle
11292 10:05:36.600377 # Registered handlers for all signals.
11293 10:05:36.600924 # Detected MINSTKSIGSZ:4720
11294 10:05:36.603643 # Testcase initialized.
11295 10:05:36.606811 # uc context validated.
11296 10:05:36.607268 # Handled SIG_TRIG
11297 10:05:36.616528 # SIG_OK -- SP:0xFFFFC6948F60 si_addr@:0xffffc6948f60 si_code:2 token@:(nil) offset:-281474013368160
11298 10:05:36.619970 # ==>> completed. PASS(1)
11299 10:05:36.626367 # # MANGLE_PSTATE_INVALID_STATE_TOGGLE :: Mangling uc_mcontext with INVALID STATE_TOGGLE
11300 10:05:36.633027 ok 11 selftests: arm64: mangle_pstate_invalid_compat_toggle
11301 10:05:36.636479 # selftests: arm64: mangle_pstate_invalid_daif_bits
11302 10:05:36.684093 # Registered handlers for all signals.
11303 10:05:36.684689 # Detected MINSTKSIGSZ:4720
11304 10:05:36.687184 # Testcase initialized.
11305 10:05:36.690320 # uc context validated.
11306 10:05:36.690780 # Handled SIG_TRIG
11307 10:05:36.700261 # SIG_OK -- SP:0xFFFFD4F49720 si_addr@:0xffffd4f49720 si_code:2 token@:(nil) offset:-281474254542624
11308 10:05:36.703738 # ==>> completed. PASS(1)
11309 10:05:36.710371 # # MANGLE_PSTATE_INVALID_DAIF_BITS :: Mangling uc_mcontext with INVALID DAIF_BITS
11310 10:05:36.713343 ok 12 selftests: arm64: mangle_pstate_invalid_daif_bits
11311 10:05:36.719860 # selftests: arm64: mangle_pstate_invalid_mode_el1h
11312 10:05:36.773605 # Registered handlers for all signals.
11313 10:05:36.774221 # Detected MINSTKSIGSZ:4720
11314 10:05:36.776415 # Testcase initialized.
11315 10:05:36.779819 # uc context validated.
11316 10:05:36.780279 # Handled SIG_TRIG
11317 10:05:36.789725 # SIG_OK -- SP:0xFFFFCDC118B0 si_addr@:0xffffcdc118b0 si_code:2 token@:(nil) offset:-281474133727408
11318 10:05:36.793136 # ==>> completed. PASS(1)
11319 10:05:36.799730 # # MANGLE_PSTATE_INVALID_MODE_EL1h :: Mangling uc_mcontext INVALID MODE EL1h
11320 10:05:36.803546 ok 13 selftests: arm64: mangle_pstate_invalid_mode_el1h
11321 10:05:36.809233 # selftests: arm64: mangle_pstate_invalid_mode_el1t
11322 10:05:36.870853 # Registered handlers for all signals.
11323 10:05:36.871391 # Detected MINSTKSIGSZ:4720
11324 10:05:36.874293 # Testcase initialized.
11325 10:05:36.877850 # uc context validated.
11326 10:05:36.878518 # Handled SIG_TRIG
11327 10:05:36.887111 # SIG_OK -- SP:0xFFFFD8F76930 si_addr@:0xffffd8f76930 si_code:2 token@:(nil) offset:-281474321836336
11328 10:05:36.890539 # ==>> completed. PASS(1)
11329 10:05:36.897297 # # MANGLE_PSTATE_INVALID_MODE_EL1t :: Mangling uc_mcontext INVALID MODE EL1t
11330 10:05:36.900395 ok 14 selftests: arm64: mangle_pstate_invalid_mode_el1t
11331 10:05:36.906885 # selftests: arm64: mangle_pstate_invalid_mode_el2h
11332 10:05:36.974674 # Registered handlers for all signals.
11333 10:05:36.975238 # Detected MINSTKSIGSZ:4720
11334 10:05:36.977914 # Testcase initialized.
11335 10:05:36.980840 # uc context validated.
11336 10:05:36.981298 # Handled SIG_TRIG
11337 10:05:36.991172 # SIG_OK -- SP:0xFFFFCDA79300 si_addr@:0xffffcda79300 si_code:2 token@:(nil) offset:-281474132054784
11338 10:05:36.994056 # ==>> completed. PASS(1)
11339 10:05:37.000784 # # MANGLE_PSTATE_INVALID_MODE_EL2h :: Mangling uc_mcontext INVALID MODE EL2h
11340 10:05:37.004151 ok 15 selftests: arm64: mangle_pstate_invalid_mode_el2h
11341 10:05:37.010722 # selftests: arm64: mangle_pstate_invalid_mode_el2t
11342 10:05:37.069180 # Registered handlers for all signals.
11343 10:05:37.069645 # Detected MINSTKSIGSZ:4720
11344 10:05:37.072674 # Testcase initialized.
11345 10:05:37.075424 # uc context validated.
11346 10:05:37.075834 # Handled SIG_TRIG
11347 10:05:37.085133 # SIG_OK -- SP:0xFFFFC0C3D630 si_addr@:0xffffc0c3d630 si_code:2 token@:(nil) offset:-281473915803184
11348 10:05:37.088782 # ==>> completed. PASS(1)
11349 10:05:37.095383 # # MANGLE_PSTATE_INVALID_MODE_EL2t :: Mangling uc_mcontext INVALID MODE EL2t
11350 10:05:37.098638 ok 16 selftests: arm64: mangle_pstate_invalid_mode_el2t
11351 10:05:37.105328 # selftests: arm64: mangle_pstate_invalid_mode_el3h
11352 10:05:37.161601 # Registered handlers for all signals.
11353 10:05:37.162146 # Detected MINSTKSIGSZ:4720
11354 10:05:37.165212 # Testcase initialized.
11355 10:05:37.167744 # uc context validated.
11356 10:05:37.168197 # Handled SIG_TRIG
11357 10:05:37.177386 # SIG_OK -- SP:0xFFFFEE5855A0 si_addr@:0xffffee5855a0 si_code:2 token@:(nil) offset:-281474680509856
11358 10:05:37.181020 # ==>> completed. PASS(1)
11359 10:05:37.187447 # # MANGLE_PSTATE_INVALID_MODE_EL3h :: Mangling uc_mcontext INVALID MODE EL3h
11360 10:05:37.190742 ok 17 selftests: arm64: mangle_pstate_invalid_mode_el3h
11361 10:05:37.197313 # selftests: arm64: mangle_pstate_invalid_mode_el3t
11362 10:05:37.256038 # Registered handlers for all signals.
11363 10:05:37.256630 # Detected MINSTKSIGSZ:4720
11364 10:05:37.258888 # Testcase initialized.
11365 10:05:37.262222 # uc context validated.
11366 10:05:37.262828 # Handled SIG_TRIG
11367 10:05:37.272440 # SIG_OK -- SP:0xFFFFC20AB7D0 si_addr@:0xffffc20ab7d0 si_code:2 token@:(nil) offset:-281473937225680
11368 10:05:37.275140 # ==>> completed. PASS(1)
11369 10:05:37.281940 # # MANGLE_PSTATE_INVALID_MODE_EL3t :: Mangling uc_mcontext INVALID MODE EL3t
11370 10:05:37.285153 ok 18 selftests: arm64: mangle_pstate_invalid_mode_el3t
11371 10:05:37.288256 # selftests: arm64: sme_trap_no_sm
11372 10:05:37.361430 # Registered handlers for all signals.
11373 10:05:37.362000 # Detected MINSTKSIGSZ:4720
11374 10:05:37.364759 # ==>> completed. SKIP.
11375 10:05:37.374605 # # SME trap without SM :: Check that we get a SIGILL if we use streaming mode without enabling it
11376 10:05:37.377858 ok 19 selftests: arm64: sme_trap_no_sm # SKIP
11377 10:05:37.386232 # selftests: arm64: sme_trap_non_streaming
11378 10:05:37.458534 # Registered handlers for all signals.
11379 10:05:37.459118 # Detected MINSTKSIGSZ:4720
11380 10:05:37.461720 # ==>> completed. SKIP.
11381 10:05:37.471314 # # SME SM trap unsupported instruction :: Check that we get a SIGILL if we use an unsupported instruction in streaming mode
11382 10:05:37.478004 ok 20 selftests: arm64: sme_trap_non_streaming # SKIP
11383 10:05:37.481468 # selftests: arm64: sme_trap_za
11384 10:05:37.551135 # Registered handlers for all signals.
11385 10:05:37.551657 # Detected MINSTKSIGSZ:4720
11386 10:05:37.554242 # Testcase initialized.
11387 10:05:37.564655 # SIG_OK -- SP:0xFFFFD099AD20 si_addr@:0xaaaad01f2510 si_code:1 token@:(nil) offset:-187650612864272
11388 10:05:37.565132 # ==>> completed. PASS(1)
11389 10:05:37.573991 # # SME ZA trap :: Check that we get a SIGILL if we access ZA without enabling
11390 10:05:37.577207 ok 21 selftests: arm64: sme_trap_za
11391 10:05:37.577622 # selftests: arm64: sme_vl
11392 10:05:37.641659 # Registered handlers for all signals.
11393 10:05:37.642185 # Detected MINSTKSIGSZ:4720
11394 10:05:37.644713 # ==>> completed. SKIP.
11395 10:05:37.651453 # # SME VL :: Check that we get the right SME VL reported
11396 10:05:37.654856 ok 22 selftests: arm64: sme_vl # SKIP
11397 10:05:37.661914 # selftests: arm64: ssve_regs
11398 10:05:37.729472 # Registered handlers for all signals.
11399 10:05:37.729975 # Detected MINSTKSIGSZ:4720
11400 10:05:37.732537 # ==>> completed. SKIP.
11401 10:05:37.739096 # # Streaming SVE registers :: Check that we get the right Streaming SVE registers reported
11402 10:05:37.745667 ok 23 selftests: arm64: ssve_regs # SKIP
11403 10:05:37.749317 # selftests: arm64: sve_regs
11404 10:05:37.826196 # Registered handlers for all signals.
11405 10:05:37.826777 # Detected MINSTKSIGSZ:4720
11406 10:05:37.829137 # ==>> completed. SKIP.
11407 10:05:37.835588 # # SVE registers :: Check that we get the right SVE registers reported
11408 10:05:37.838596 ok 24 selftests: arm64: sve_regs # SKIP
11409 10:05:37.845519 # selftests: arm64: sve_vl
11410 10:05:37.919833 # Registered handlers for all signals.
11411 10:05:37.920410 # Detected MINSTKSIGSZ:4720
11412 10:05:37.922917 # ==>> completed. SKIP.
11413 10:05:37.929864 # # SVE VL :: Check that we get the right SVE VL reported
11414 10:05:37.933037 ok 25 selftests: arm64: sve_vl # SKIP
11415 10:05:37.939225 # selftests: arm64: za_no_regs
11416 10:05:37.997552 # Registered handlers for all signals.
11417 10:05:37.998056 # Detected MINSTKSIGSZ:4720
11418 10:05:38.000149 # ==>> completed. SKIP.
11419 10:05:38.006544 # # ZA registers - ZA disabled :: Check ZA context with ZA disabled
11420 10:05:38.009650 ok 26 selftests: arm64: za_no_regs # SKIP
11421 10:05:38.015174 # selftests: arm64: za_regs
11422 10:05:38.090147 # Registered handlers for all signals.
11423 10:05:38.090687 # Detected MINSTKSIGSZ:4720
11424 10:05:38.091795 # ==>> completed. SKIP.
11425 10:05:38.098409 # # ZA register :: Check that we get the right ZA registers reported
11426 10:05:38.101550 ok 27 selftests: arm64: za_regs # SKIP
11427 10:05:38.108880 # selftests: arm64: pac
11428 10:05:38.159312 # TAP version 13
11429 10:05:38.159814 # 1..7
11430 10:05:38.162084 # # Starting 7 tests from 1 test cases.
11431 10:05:38.165423 # # RUN global.corrupt_pac ...
11432 10:05:38.168799 # # SKIP PAUTH not enabled
11433 10:05:38.172418 # # OK global.corrupt_pac
11434 10:05:38.175496 # ok 1 # SKIP PAUTH not enabled
11435 10:05:38.182225 # # RUN global.pac_instructions_not_nop ...
11436 10:05:38.184940 # # SKIP PAUTH not enabled
11437 10:05:38.188563 # # OK global.pac_instructions_not_nop
11438 10:05:38.191472 # ok 2 # SKIP PAUTH not enabled
11439 10:05:38.198423 # # RUN global.pac_instructions_not_nop_generic ...
11440 10:05:38.201761 # # SKIP Generic PAUTH not enabled
11441 10:05:38.205286 # # OK global.pac_instructions_not_nop_generic
11442 10:05:38.211209 # ok 3 # SKIP Generic PAUTH not enabled
11443 10:05:38.214763 # # RUN global.single_thread_different_keys ...
11444 10:05:38.218012 # # SKIP PAUTH not enabled
11445 10:05:38.224577 # # OK global.single_thread_different_keys
11446 10:05:38.224989 # ok 4 # SKIP PAUTH not enabled
11447 10:05:38.231187 # # RUN global.exec_changed_keys ...
11448 10:05:38.234790 # # SKIP PAUTH not enabled
11449 10:05:38.237977 # # OK global.exec_changed_keys
11450 10:05:38.241826 # ok 5 # SKIP PAUTH not enabled
11451 10:05:38.244583 # # RUN global.context_switch_keep_keys ...
11452 10:05:38.247702 # # SKIP PAUTH not enabled
11453 10:05:38.254779 # # OK global.context_switch_keep_keys
11454 10:05:38.255287 # ok 6 # SKIP PAUTH not enabled
11455 10:05:38.261457 # # RUN global.context_switch_keep_keys_generic ...
11456 10:05:38.264169 # # SKIP Generic PAUTH not enabled
11457 10:05:38.270955 # # OK global.context_switch_keep_keys_generic
11458 10:05:38.274174 # ok 7 # SKIP Generic PAUTH not enabled
11459 10:05:38.277647 # # PASSED: 7 / 7 tests passed.
11460 10:05:38.280959 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:7 error:0
11461 10:05:38.284608 ok 28 selftests: arm64: pac
11462 10:05:38.287461 # selftests: arm64: fp-stress
11463 10:05:41.954794 <6>[ 46.158526] vpu: disabling
11464 10:05:41.957370 <6>[ 46.161572] vproc2: disabling
11465 10:05:41.960596 <6>[ 46.164845] vproc1: disabling
11466 10:05:41.964376 <6>[ 46.168116] vaud18: disabling
11467 10:05:41.970889 <6>[ 46.171536] vsram_others: disabling
11468 10:05:41.971436 <6>[ 46.175420] va09: disabling
11469 10:05:41.977966 <6>[ 46.178532] vsram_md: disabling
11470 10:05:41.978553 <6>[ 46.182021] Vgpu: disabling
11471 10:05:48.236526 # TAP version 13
11472 10:05:48.237073 # 1..16
11473 10:05:48.239696 # # 8 CPUs, 0 SVE VLs, 0 SME VLs
11474 10:05:48.243301 # # Will run for 10s
11475 10:05:48.246418 # # Started FPSIMD-0-0
11476 10:05:48.246869 # # Started FPSIMD-0-1
11477 10:05:48.249750 # # Started FPSIMD-1-0
11478 10:05:48.250201 # # Started FPSIMD-1-1
11479 10:05:48.252964 # # Started FPSIMD-2-0
11480 10:05:48.256491 # # Started FPSIMD-2-1
11481 10:05:48.256948 # # Started FPSIMD-3-0
11482 10:05:48.259849 # # Started FPSIMD-3-1
11483 10:05:48.263148 # # Started FPSIMD-4-0
11484 10:05:48.263557 # # Started FPSIMD-4-1
11485 10:05:48.265967 # # Started FPSIMD-5-0
11486 10:05:48.269267 # # Started FPSIMD-5-1
11487 10:05:48.269677 # # Started FPSIMD-6-0
11488 10:05:48.272719 # # Started FPSIMD-6-1
11489 10:05:48.273131 # # Started FPSIMD-7-0
11490 10:05:48.276071 # # Started FPSIMD-7-1
11491 10:05:48.279457 # # FPSIMD-1-1: Vector length: 128 bits
11492 10:05:48.282818 # # FPSIMD-1-1: PID: 1162
11493 10:05:48.285520 # # FPSIMD-1-0: Vector length: 128 bits
11494 10:05:48.289386 # # FPSIMD-1-0: PID: 1161
11495 10:05:48.292530 # # FPSIMD-0-0: Vector length: 128 bits
11496 10:05:48.292939 # # FPSIMD-0-0: PID: 1159
11497 10:05:48.299453 # # FPSIMD-2-0: Vector length: 128 bits
11498 10:05:48.299867 # # FPSIMD-2-0: PID: 1163
11499 10:05:48.302298 # # FPSIMD-0-1: Vector length: 128 bits
11500 10:05:48.305570 # # FPSIMD-0-1: PID: 1160
11501 10:05:48.309060 # # FPSIMD-2-1: Vector length: 128 bits
11502 10:05:48.312312 # # FPSIMD-2-1: PID: 1164
11503 10:05:48.315709 # # FPSIMD-4-1: Vector length: 128 bits
11504 10:05:48.318902 # # FPSIMD-4-1: PID: 1168
11505 10:05:48.322055 # # FPSIMD-4-0: Vector length: 128 bits
11506 10:05:48.322530 # # FPSIMD-4-0: PID: 1167
11507 10:05:48.326349 # # FPSIMD-6-1: Vector length: 128 bits
11508 10:05:48.328986 # # FPSIMD-6-1: PID: 1172
11509 10:05:48.332160 # # FPSIMD-5-0: Vector length: 128 bits
11510 10:05:48.335525 # # FPSIMD-5-0: PID: 1169
11511 10:05:48.338696 # # FPSIMD-3-1: Vector length: 128 bits
11512 10:05:48.342179 # # FPSIMD-3-1: PID: 1166
11513 10:05:48.345292 # # FPSIMD-6-0: Vector length: 128 bits
11514 10:05:48.348572 # # FPSIMD-6-0: PID: 1171
11515 10:05:48.351958 # # FPSIMD-7-1: Vector length: 128 bits
11516 10:05:48.352375 # # FPSIMD-7-1: PID: 1174
11517 10:05:48.355390 # # FPSIMD-7-0: Vector length: 128 bits
11518 10:05:48.358343 # # FPSIMD-7-0: PID: 1173
11519 10:05:48.361954 # # FPSIMD-3-0: Vector length: 128 bits
11520 10:05:48.365786 # # FPSIMD-3-0: PID: 1165
11521 10:05:48.368603 # # FPSIMD-5-1: Vector length: 128 bits
11522 10:05:48.371556 # # FPSIMD-5-1: PID: 1170
11523 10:05:48.371964 # # Finishing up...
11524 10:05:48.378185 # # FPSIMD-1-1: Terminated by signal 15, no error, iterations=1126893, signals=10
11525 10:05:48.387822 # # FPSIMD-2-0: Terminated by signal 15, no error, iterations=2008803, signals=10
11526 10:05:48.394999 # # FPSIMD-4-0: Terminated by signal 15, no error, iterations=1113337, signals=10
11527 10:05:48.401642 # # FPSIMD-5-0: Terminated by signal 15, no error, iterations=1326875, signals=10
11528 10:05:48.407843 # # FPSIMD-0-1: Terminated by signal 15, no error, iterations=1032358, signals=10
11529 10:05:48.414820 # # FPSIMD-2-1: Terminated by signal 15, no error, iterations=1402249, signals=10
11530 10:05:48.421238 # # FPSIMD-5-1: Terminated by signal 15, no error, iterations=1271905, signals=10
11531 10:05:48.424900 # ok 1 FPSIMD-0-0
11532 10:05:48.425306 # ok 2 FPSIMD-0-1
11533 10:05:48.428140 # ok 3 FPSIMD-1-0
11534 10:05:48.428545 # ok 4 FPSIMD-1-1
11535 10:05:48.431710 # ok 5 FPSIMD-2-0
11536 10:05:48.432119 # ok 6 FPSIMD-2-1
11537 10:05:48.434692 # ok 7 FPSIMD-3-0
11538 10:05:48.435201 # ok 8 FPSIMD-3-1
11539 10:05:48.437851 # ok 9 FPSIMD-4-0
11540 10:05:48.438451 # ok 10 FPSIMD-4-1
11541 10:05:48.441374 # ok 11 FPSIMD-5-0
11542 10:05:48.444221 # ok 12 FPSIMD-5-1
11543 10:05:48.444633 # ok 13 FPSIMD-6-0
11544 10:05:48.447834 # ok 14 FPSIMD-6-1
11545 10:05:48.448240 # ok 15 FPSIMD-7-0
11546 10:05:48.451161 # ok 16 FPSIMD-7-1
11547 10:05:48.457475 # # FPSIMD-3-0: Terminated by signal 15, no error, iterations=1338726, signals=9
11548 10:05:48.464397 # # FPSIMD-4-1: Terminated by signal 15, no error, iterations=915812, signals=10
11549 10:05:48.470867 # # FPSIMD-6-0: Terminated by signal 15, no error, iterations=1570467, signals=10
11550 10:05:48.477518 # # FPSIMD-1-0: Terminated by signal 15, no error, iterations=1098752, signals=10
11551 10:05:48.484226 # # FPSIMD-6-1: Terminated by signal 15, no error, iterations=1217426, signals=9
11552 10:05:48.493876 # # FPSIMD-7-1: Terminated by signal 15, no error, iterations=1736113, signals=10
11553 10:05:48.501061 # # FPSIMD-0-0: Terminated by signal 15, no error, iterations=1328694, signals=10
11554 10:05:48.507250 # # FPSIMD-7-0: Terminated by signal 15, no error, iterations=914817, signals=10
11555 10:05:48.513990 # # FPSIMD-3-1: Terminated by signal 15, no error, iterations=1089282, signals=9
11556 10:05:48.520526 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:0 error:0
11557 10:05:48.523701 ok 29 selftests: arm64: fp-stress
11558 10:05:48.524258 # selftests: arm64: sve-ptrace
11559 10:05:48.526654 # TAP version 13
11560 10:05:48.527105 # 1..4104
11561 10:05:48.530630 # ok 2 # SKIP SVE not available
11562 10:05:48.533705 # # Planned tests != run tests (4104 != 1)
11563 10:05:48.540163 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11564 10:05:48.543516 ok 30 selftests: arm64: sve-ptrace # SKIP
11565 10:05:48.546880 # selftests: arm64: sve-probe-vls
11566 10:05:48.547289 # TAP version 13
11567 10:05:48.549862 # 1..2
11568 10:05:48.550332 # ok 2 # SKIP SVE not available
11569 10:05:48.556387 # # Planned tests != run tests (2 != 1)
11570 10:05:48.559801 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11571 10:05:48.563118 ok 31 selftests: arm64: sve-probe-vls # SKIP
11572 10:05:48.566198 # selftests: arm64: vec-syscfg
11573 10:05:48.569793 # TAP version 13
11574 10:05:48.570203 # 1..20
11575 10:05:48.572917 # ok 1 # SKIP SVE not supported
11576 10:05:48.575977 # ok 2 # SKIP SVE not supported
11577 10:05:48.576455 # ok 3 # SKIP SVE not supported
11578 10:05:48.579416 # ok 4 # SKIP SVE not supported
11579 10:05:48.582713 # ok 5 # SKIP SVE not supported
11580 10:05:48.586083 # ok 6 # SKIP SVE not supported
11581 10:05:48.590011 # ok 7 # SKIP SVE not supported
11582 10:05:48.592996 # ok 8 # SKIP SVE not supported
11583 10:05:48.596179 # ok 9 # SKIP SVE not supported
11584 10:05:48.599215 # ok 10 # SKIP SVE not supported
11585 10:05:48.599627 # ok 11 # SKIP SME not supported
11586 10:05:48.603094 # ok 12 # SKIP SME not supported
11587 10:05:48.606663 # ok 13 # SKIP SME not supported
11588 10:05:48.609433 # ok 14 # SKIP SME not supported
11589 10:05:48.613000 # ok 15 # SKIP SME not supported
11590 10:05:48.616272 # ok 16 # SKIP SME not supported
11591 10:05:48.618961 # ok 17 # SKIP SME not supported
11592 10:05:48.622400 # ok 18 # SKIP SME not supported
11593 10:05:48.625781 # ok 19 # SKIP SME not supported
11594 10:05:48.626194 # ok 20 # SKIP SME not supported
11595 10:05:48.632375 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:20 error:0
11596 10:05:48.635991 ok 32 selftests: arm64: vec-syscfg
11597 10:05:48.638756 # selftests: arm64: za-fork
11598 10:05:48.639164 # TAP version 13
11599 10:05:48.639490 # 1..1
11600 10:05:48.642286 # # PID: 1249
11601 10:05:48.645317 # # SME support not present
11602 10:05:48.645727 # ok 0 skipped
11603 10:05:48.652246 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11604 10:05:48.652660 ok 33 selftests: arm64: za-fork
11605 10:05:48.655593 # selftests: arm64: za-ptrace
11606 10:05:48.713423 # TAP version 13
11607 10:05:48.713966 # 1..1
11608 10:05:48.716183 # ok 2 # SKIP SME not available
11609 10:05:48.722991 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11610 10:05:48.726144 ok 34 selftests: arm64: za-ptrace # SKIP
11611 10:05:48.744156 # selftests: arm64: check_buffer_fill
11612 10:05:48.789925 # # SKIP: MTE features unavailable
11613 10:05:48.797200 ok 35 selftests: arm64: check_buffer_fill # SKIP
11614 10:05:48.818618 # selftests: arm64: check_child_memory
11615 10:05:48.875967 # # SKIP: MTE features unavailable
11616 10:05:48.883937 ok 36 selftests: arm64: check_child_memory # SKIP
11617 10:05:48.902836 # selftests: arm64: check_gcr_el1_cswitch
11618 10:05:48.973061 # # SKIP: MTE features unavailable
11619 10:05:48.980621 ok 37 selftests: arm64: check_gcr_el1_cswitch # SKIP
11620 10:05:49.000091 # selftests: arm64: check_ksm_options
11621 10:05:49.050815 # # SKIP: MTE features unavailable
11622 10:05:49.058302 ok 38 selftests: arm64: check_ksm_options # SKIP
11623 10:05:49.079579 # selftests: arm64: check_mmap_options
11624 10:05:49.147977 # # SKIP: MTE features unavailable
11625 10:05:49.154859 ok 39 selftests: arm64: check_mmap_options # SKIP
11626 10:05:49.171527 # selftests: arm64: check_prctl
11627 10:05:49.233881 # TAP version 13
11628 10:05:49.234470 # 1..5
11629 10:05:49.237364 # ok 1 check_basic_read
11630 10:05:49.237999 # ok 2 NONE
11631 10:05:49.241300 # ok 3 # SKIP SYNC
11632 10:05:49.241860 # ok 4 # SKIP ASYNC
11633 10:05:49.243929 # ok 5 # SKIP SYNC+ASYNC
11634 10:05:49.247657 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:3 error:0
11635 10:05:49.250602 ok 40 selftests: arm64: check_prctl
11636 10:05:49.260627 # selftests: arm64: check_tags_inclusion
11637 10:05:49.329766 # # SKIP: MTE features unavailable
11638 10:05:49.336390 ok 41 selftests: arm64: check_tags_inclusion # SKIP
11639 10:05:49.352257 # selftests: arm64: check_user_mem
11640 10:05:49.427164 # # SKIP: MTE features unavailable
11641 10:05:49.434492 ok 42 selftests: arm64: check_user_mem # SKIP
11642 10:05:49.451357 # selftests: arm64: btitest
11643 10:05:49.516203 # TAP version 13
11644 10:05:49.516750 # 1..18
11645 10:05:49.520315 # # HWCAP_PACA not present
11646 10:05:49.522355 # # HWCAP2_BTI not present
11647 10:05:49.522813 # # Test binary built for BTI
11648 10:05:49.529493 # ok 1 nohint_func/call_using_br_x0 # SKIP
11649 10:05:49.532146 # ok 1 nohint_func/call_using_br_x16 # SKIP
11650 10:05:49.535420 # ok 1 nohint_func/call_using_blr # SKIP
11651 10:05:49.538657 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11652 10:05:49.542364 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11653 10:05:49.545494 # ok 1 bti_none_func/call_using_blr # SKIP
11654 10:05:49.551922 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11655 10:05:49.555135 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11656 10:05:49.558826 # ok 1 bti_c_func/call_using_blr # SKIP
11657 10:05:49.562074 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11658 10:05:49.565366 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11659 10:05:49.568352 # ok 1 bti_j_func/call_using_blr # SKIP
11660 10:05:49.572043 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11661 10:05:49.578744 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11662 10:05:49.581781 # ok 1 bti_jc_func/call_using_blr # SKIP
11663 10:05:49.584910 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11664 10:05:49.588516 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11665 10:05:49.592000 # ok 1 paciasp_func/call_using_blr # SKIP
11666 10:05:49.598244 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11667 10:05:49.601534 # # WARNING - EXPECTED TEST COUNT WRONG
11668 10:05:49.605252 ok 43 selftests: arm64: btitest
11669 10:05:49.608578 # selftests: arm64: nobtitest
11670 10:05:49.611542 # TAP version 13
11671 10:05:49.612032 # 1..18
11672 10:05:49.614630 # # HWCAP_PACA not present
11673 10:05:49.615081 # # HWCAP2_BTI not present
11674 10:05:49.618116 # # Test binary not built for BTI
11675 10:05:49.621508 # ok 1 nohint_func/call_using_br_x0 # SKIP
11676 10:05:49.627840 # ok 1 nohint_func/call_using_br_x16 # SKIP
11677 10:05:49.631782 # ok 1 nohint_func/call_using_blr # SKIP
11678 10:05:49.634893 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11679 10:05:49.637646 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11680 10:05:49.640917 # ok 1 bti_none_func/call_using_blr # SKIP
11681 10:05:49.644256 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11682 10:05:49.650885 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11683 10:05:49.654079 # ok 1 bti_c_func/call_using_blr # SKIP
11684 10:05:49.657814 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11685 10:05:49.660908 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11686 10:05:49.664750 # ok 1 bti_j_func/call_using_blr # SKIP
11687 10:05:49.667577 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11688 10:05:49.670496 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11689 10:05:49.673997 # ok 1 bti_jc_func/call_using_blr # SKIP
11690 10:05:49.680583 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11691 10:05:49.684274 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11692 10:05:49.687692 # ok 1 paciasp_func/call_using_blr # SKIP
11693 10:05:49.694118 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11694 10:05:49.697534 # # WARNING - EXPECTED TEST COUNT WRONG
11695 10:05:49.700353 ok 44 selftests: arm64: nobtitest
11696 10:05:49.700834 # selftests: arm64: hwcap
11697 10:05:49.704016 # TAP version 13
11698 10:05:49.704641 # 1..28
11699 10:05:49.707096 # ok 1 cpuinfo_match_RNG
11700 10:05:49.707549 # # SIGILL reported for RNG
11701 10:05:49.710582 # ok 2 # SKIP sigill_RNG
11702 10:05:49.713583 # ok 3 cpuinfo_match_SME
11703 10:05:49.713990 # ok 4 sigill_SME
11704 10:05:49.717288 # ok 5 cpuinfo_match_SVE
11705 10:05:49.717697 # ok 6 sigill_SVE
11706 10:05:49.720365 # ok 7 cpuinfo_match_SVE 2
11707 10:05:49.723890 # # SIGILL reported for SVE 2
11708 10:05:49.727192 # ok 8 # SKIP sigill_SVE 2
11709 10:05:49.727610 # ok 9 cpuinfo_match_SVE AES
11710 10:05:49.730076 # # SIGILL reported for SVE AES
11711 10:05:49.733270 # ok 10 # SKIP sigill_SVE AES
11712 10:05:49.736744 # ok 11 cpuinfo_match_SVE2 PMULL
11713 10:05:49.740231 # # SIGILL reported for SVE2 PMULL
11714 10:05:49.743577 # ok 12 # SKIP sigill_SVE2 PMULL
11715 10:05:49.747360 # ok 13 cpuinfo_match_SVE2 BITPERM
11716 10:05:49.750243 # # SIGILL reported for SVE2 BITPERM
11717 10:05:49.754219 # ok 14 # SKIP sigill_SVE2 BITPERM
11718 10:05:49.756752 # ok 15 cpuinfo_match_SVE2 SHA3
11719 10:05:49.760184 # # SIGILL reported for SVE2 SHA3
11720 10:05:49.760657 # ok 16 # SKIP sigill_SVE2 SHA3
11721 10:05:49.763778 # ok 17 cpuinfo_match_SVE2 SM4
11722 10:05:49.766883 # # SIGILL reported for SVE2 SM4
11723 10:05:49.770330 # ok 18 # SKIP sigill_SVE2 SM4
11724 10:05:49.773184 # ok 19 cpuinfo_match_SVE2 I8MM
11725 10:05:49.776443 # # SIGILL reported for SVE2 I8MM
11726 10:05:49.780026 # ok 20 # SKIP sigill_SVE2 I8MM
11727 10:05:49.783187 # ok 21 cpuinfo_match_SVE2 F32MM
11728 10:05:49.783645 # # SIGILL reported for SVE2 F32MM
11729 10:05:49.786794 # ok 22 # SKIP sigill_SVE2 F32MM
11730 10:05:49.789916 # ok 23 cpuinfo_match_SVE2 F64MM
11731 10:05:49.793552 # # SIGILL reported for SVE2 F64MM
11732 10:05:49.796889 # ok 24 # SKIP sigill_SVE2 F64MM
11733 10:05:49.800051 # ok 25 cpuinfo_match_SVE2 BF16
11734 10:05:49.803260 # # SIGILL reported for SVE2 BF16
11735 10:05:49.805953 # ok 26 # SKIP sigill_SVE2 BF16
11736 10:05:49.809627 # ok 27 cpuinfo_match_SVE2 EBF16
11737 10:05:49.812986 # ok 28 # SKIP sigill_SVE2 EBF16
11738 10:05:49.816336 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:12 error:0
11739 10:05:49.819611 ok 45 selftests: arm64: hwcap
11740 10:05:49.822421 # selftests: arm64: ptrace
11741 10:05:49.822841 # TAP version 13
11742 10:05:49.823169 # 1..7
11743 10:05:49.826027 # # Parent is 1491, child is 1492
11744 10:05:49.829309 # ok 1 read_tpidr_one
11745 10:05:49.832687 # ok 2 write_tpidr_one
11746 10:05:49.833102 # ok 3 verify_tpidr_one
11747 10:05:49.835790 # ok 4 count_tpidrs
11748 10:05:49.836203 # ok 5 tpidr2_write
11749 10:05:49.838944 # ok 6 tpidr2_read
11750 10:05:49.839355 # ok 7 write_tpidr_only
11751 10:05:49.846373 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
11752 10:05:49.848793 ok 46 selftests: arm64: ptrace
11753 10:05:49.852332 # selftests: arm64: syscall-abi
11754 10:05:49.895730 # TAP version 13
11755 10:05:49.896255 # 1..2
11756 10:05:49.899409 # ok 1 getpid() FPSIMD
11757 10:05:49.902599 # ok 2 sched_yield() FPSIMD
11758 10:05:49.905413 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:0 error:0
11759 10:05:49.908748 ok 47 selftests: arm64: syscall-abi
11760 10:05:49.919103 # selftests: arm64: tpidr2
11761 10:05:50.002858 # TAP version 13
11762 10:05:50.003419 # 1..5
11763 10:05:50.005196 # # PID: 1528
11764 10:05:50.005762 # # SME support not present
11765 10:05:50.008326 # ok 0 skipped, TPIDR2 not supported
11766 10:05:50.011957 # ok 1 skipped, TPIDR2 not supported
11767 10:05:50.015041 # ok 2 skipped, TPIDR2 not supported
11768 10:05:50.018223 # ok 3 skipped, TPIDR2 not supported
11769 10:05:50.021541 # ok 4 skipped, TPIDR2 not supported
11770 10:05:50.028003 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0
11771 10:05:50.031762 ok 48 selftests: arm64: tpidr2
11772 10:05:50.719213 arm64_tags_test pass
11773 10:05:50.722494 arm64_run_tags_test_sh pass
11774 10:05:50.725461 arm64_fake_sigreturn_bad_magic pass
11775 10:05:50.728404 arm64_fake_sigreturn_bad_size pass
11776 10:05:50.732340 arm64_fake_sigreturn_bad_size_for_magic0 pass
11777 10:05:50.735222 arm64_fake_sigreturn_duplicated_fpsimd pass
11778 10:05:50.738553 arm64_fake_sigreturn_misaligned_sp pass
11779 10:05:50.741919 arm64_fake_sigreturn_missing_fpsimd pass
11780 10:05:50.745592 arm64_fake_sigreturn_sme_change_vl skip
11781 10:05:50.751978 arm64_fake_sigreturn_sve_change_vl skip
11782 10:05:50.755215 arm64_mangle_pstate_invalid_compat_toggle pass
11783 10:05:50.758348 arm64_mangle_pstate_invalid_daif_bits pass
11784 10:05:50.761733 arm64_mangle_pstate_invalid_mode_el1h pass
11785 10:05:50.765106 arm64_mangle_pstate_invalid_mode_el1t pass
11786 10:05:50.768094 arm64_mangle_pstate_invalid_mode_el2h pass
11787 10:05:50.774840 arm64_mangle_pstate_invalid_mode_el2t pass
11788 10:05:50.778345 arm64_mangle_pstate_invalid_mode_el3h pass
11789 10:05:50.781815 arm64_mangle_pstate_invalid_mode_el3t pass
11790 10:05:50.784453 arm64_sme_trap_no_sm skip
11791 10:05:50.788368 arm64_sme_trap_non_streaming skip
11792 10:05:50.788916 arm64_sme_trap_za pass
11793 10:05:50.791532 arm64_sme_vl skip
11794 10:05:50.791984 arm64_ssve_regs skip
11795 10:05:50.794442 arm64_sve_regs skip
11796 10:05:50.794894 arm64_sve_vl skip
11797 10:05:50.798355 arm64_za_no_regs skip
11798 10:05:50.798911 arm64_za_regs skip
11799 10:05:50.801242 arm64_pac_pauth_not_enabled skip
11800 10:05:50.804691 arm64_pac_pauth_not_enabled skip
11801 10:05:50.807937 arm64_pac_generic_pauth_not_enabled skip
11802 10:05:50.811494 arm64_pac_pauth_not_enabled skip
11803 10:05:50.814219 arm64_pac_pauth_not_enabled skip
11804 10:05:50.817774 arm64_pac_pauth_not_enabled skip
11805 10:05:50.821332 arm64_pac_generic_pauth_not_enabled skip
11806 10:05:50.824763 arm64_pac pass
11807 10:05:50.825308 arm64_fp-stress_FPSIMD-0-0 pass
11808 10:05:50.827559 arm64_fp-stress_FPSIMD-0-1 pass
11809 10:05:50.831272 arm64_fp-stress_FPSIMD-1-0 pass
11810 10:05:50.834305 arm64_fp-stress_FPSIMD-1-1 pass
11811 10:05:50.837982 arm64_fp-stress_FPSIMD-2-0 pass
11812 10:05:50.840781 arm64_fp-stress_FPSIMD-2-1 pass
11813 10:05:50.844471 arm64_fp-stress_FPSIMD-3-0 pass
11814 10:05:50.845016 arm64_fp-stress_FPSIMD-3-1 pass
11815 10:05:50.847726 arm64_fp-stress_FPSIMD-4-0 pass
11816 10:05:50.851196 arm64_fp-stress_FPSIMD-4-1 pass
11817 10:05:50.854411 arm64_fp-stress_FPSIMD-5-0 pass
11818 10:05:50.857279 arm64_fp-stress_FPSIMD-5-1 pass
11819 10:05:50.860653 arm64_fp-stress_FPSIMD-6-0 pass
11820 10:05:50.863663 arm64_fp-stress_FPSIMD-6-1 pass
11821 10:05:50.866918 arm64_fp-stress_FPSIMD-7-0 pass
11822 10:05:50.867375 arm64_fp-stress_FPSIMD-7-1 pass
11823 10:05:50.870463 arm64_fp-stress pass
11824 10:05:50.873913 arm64_sve-ptrace_sve_not_available skip
11825 10:05:50.877290 arm64_sve-ptrace skip
11826 10:05:50.880846 arm64_sve-probe-vls_sve_not_available skip
11827 10:05:50.883788 arm64_sve-probe-vls skip
11828 10:05:50.887045 arm64_vec-syscfg_sve_not_supported skip
11829 10:05:50.890201 arm64_vec-syscfg_sve_not_supported skip
11830 10:05:50.893765 arm64_vec-syscfg_sve_not_supported skip
11831 10:05:50.897170 arm64_vec-syscfg_sve_not_supported skip
11832 10:05:50.900241 arm64_vec-syscfg_sve_not_supported skip
11833 10:05:50.903705 arm64_vec-syscfg_sve_not_supported skip
11834 10:05:50.907263 arm64_vec-syscfg_sve_not_supported skip
11835 10:05:50.910598 arm64_vec-syscfg_sve_not_supported skip
11836 10:05:50.913765 arm64_vec-syscfg_sve_not_supported skip
11837 10:05:50.916716 arm64_vec-syscfg_sve_not_supported skip
11838 10:05:50.920551 arm64_vec-syscfg_sme_not_supported skip
11839 10:05:50.924155 arm64_vec-syscfg_sme_not_supported skip
11840 10:05:50.926799 arm64_vec-syscfg_sme_not_supported skip
11841 10:05:50.933681 arm64_vec-syscfg_sme_not_supported skip
11842 10:05:50.937020 arm64_vec-syscfg_sme_not_supported skip
11843 10:05:50.940421 arm64_vec-syscfg_sme_not_supported skip
11844 10:05:50.942829 arm64_vec-syscfg_sme_not_supported skip
11845 10:05:50.946662 arm64_vec-syscfg_sme_not_supported skip
11846 10:05:50.950046 arm64_vec-syscfg_sme_not_supported skip
11847 10:05:50.953326 arm64_vec-syscfg_sme_not_supported skip
11848 10:05:50.956401 arm64_vec-syscfg pass
11849 10:05:50.956856 arm64_za-fork_skipped pass
11850 10:05:50.960029 arm64_za-fork pass
11851 10:05:50.963223 arm64_za-ptrace_sme_not_available skip
11852 10:05:50.966236 arm64_za-ptrace skip
11853 10:05:50.966749 arm64_check_buffer_fill skip
11854 10:05:50.969540 arm64_check_child_memory skip
11855 10:05:50.972886 arm64_check_gcr_el1_cswitch skip
11856 10:05:50.976270 arm64_check_ksm_options skip
11857 10:05:50.979217 arm64_check_mmap_options skip
11858 10:05:50.982517 arm64_check_prctl_check_basic_read pass
11859 10:05:50.982972 arm64_check_prctl_NONE pass
11860 10:05:50.986502 arm64_check_prctl_sync skip
11861 10:05:50.989425 arm64_check_prctl_async skip
11862 10:05:50.992818 arm64_check_prctl_sync_async skip
11863 10:05:50.995972 arm64_check_prctl pass
11864 10:05:50.996428 arm64_check_tags_inclusion skip
11865 10:05:50.998776 arm64_check_user_mem skip
11866 10:05:51.002436 arm64_btitest_nohint_func_call_using_br_x0 skip
11867 10:05:51.009396 arm64_btitest_nohint_func_call_using_br_x16 skip
11868 10:05:51.012619 arm64_btitest_nohint_func_call_using_blr skip
11869 10:05:51.015754 arm64_btitest_bti_none_func_call_using_br_x0 skip
11870 10:05:51.022808 arm64_btitest_bti_none_func_call_using_br_x16 skip
11871 10:05:51.025344 arm64_btitest_bti_none_func_call_using_blr skip
11872 10:05:51.028831 arm64_btitest_bti_c_func_call_using_br_x0 skip
11873 10:05:51.034976 arm64_btitest_bti_c_func_call_using_br_x16 skip
11874 10:05:51.038789 arm64_btitest_bti_c_func_call_using_blr skip
11875 10:05:51.041989 arm64_btitest_bti_j_func_call_using_br_x0 skip
11876 10:05:51.045512 arm64_btitest_bti_j_func_call_using_br_x16 skip
11877 10:05:51.051690 arm64_btitest_bti_j_func_call_using_blr skip
11878 10:05:51.054999 arm64_btitest_bti_jc_func_call_using_br_x0 skip
11879 10:05:51.058228 arm64_btitest_bti_jc_func_call_using_br_x16 skip
11880 10:05:51.061373 arm64_btitest_bti_jc_func_call_using_blr skip
11881 10:05:51.068033 arm64_btitest_paciasp_func_call_using_br_x0 skip
11882 10:05:51.071290 arm64_btitest_paciasp_func_call_using_br_x16 skip
11883 10:05:51.074617 arm64_btitest_paciasp_func_call_using_blr skip
11884 10:05:51.077876 arm64_btitest pass
11885 10:05:51.081287 arm64_nobtitest_nohint_func_call_using_br_x0 skip
11886 10:05:51.087988 arm64_nobtitest_nohint_func_call_using_br_x16 skip
11887 10:05:51.091188 arm64_nobtitest_nohint_func_call_using_blr skip
11888 10:05:51.094433 arm64_nobtitest_bti_none_func_call_using_br_x0 skip
11889 10:05:51.101329 arm64_nobtitest_bti_none_func_call_using_br_x16 skip
11890 10:05:51.104822 arm64_nobtitest_bti_none_func_call_using_blr skip
11891 10:05:51.108003 arm64_nobtitest_bti_c_func_call_using_br_x0 skip
11892 10:05:51.114109 arm64_nobtitest_bti_c_func_call_using_br_x16 skip
11893 10:05:51.118050 arm64_nobtitest_bti_c_func_call_using_blr skip
11894 10:05:51.121324 arm64_nobtitest_bti_j_func_call_using_br_x0 skip
11895 10:05:51.127381 arm64_nobtitest_bti_j_func_call_using_br_x16 skip
11896 10:05:51.130755 arm64_nobtitest_bti_j_func_call_using_blr skip
11897 10:05:51.134107 arm64_nobtitest_bti_jc_func_call_using_br_x0 skip
11898 10:05:51.140780 arm64_nobtitest_bti_jc_func_call_using_br_x16 skip
11899 10:05:51.143888 arm64_nobtitest_bti_jc_func_call_using_blr skip
11900 10:05:51.147489 arm64_nobtitest_paciasp_func_call_using_br_x0 skip
11901 10:05:51.153344 arm64_nobtitest_paciasp_func_call_using_br_x16 skip
11902 10:05:51.156868 arm64_nobtitest_paciasp_func_call_using_blr skip
11903 10:05:51.160538 arm64_nobtitest pass
11904 10:05:51.163826 arm64_hwcap_cpuinfo_match_RNG pass
11905 10:05:51.164236 arm64_hwcap_sigill_rng skip
11906 10:05:51.166546 arm64_hwcap_cpuinfo_match_SME pass
11907 10:05:51.169908 arm64_hwcap_sigill_SME pass
11908 10:05:51.173105 arm64_hwcap_cpuinfo_match_SVE pass
11909 10:05:51.176931 arm64_hwcap_sigill_SVE pass
11910 10:05:51.180055 arm64_hwcap_cpuinfo_match_SVE_2 pass
11911 10:05:51.183272 arm64_hwcap_sigill_sve_2 skip
11912 10:05:51.186680 arm64_hwcap_cpuinfo_match_SVE_AES pass
11913 10:05:51.187089 arm64_hwcap_sigill_sve_aes skip
11914 10:05:51.193338 arm64_hwcap_cpuinfo_match_SVE2_PMULL pass
11915 10:05:51.196290 arm64_hwcap_sigill_sve2_pmull skip
11916 10:05:51.200504 arm64_hwcap_cpuinfo_match_SVE2_BITPERM pass
11917 10:05:51.203056 arm64_hwcap_sigill_sve2_bitperm skip
11918 10:05:51.206453 arm64_hwcap_cpuinfo_match_SVE2_SHA3 pass
11919 10:05:51.209792 arm64_hwcap_sigill_sve2_sha3 skip
11920 10:05:51.213117 arm64_hwcap_cpuinfo_match_SVE2_SM4 pass
11921 10:05:51.216437 arm64_hwcap_sigill_sve2_sm4 skip
11922 10:05:51.220035 arm64_hwcap_cpuinfo_match_SVE2_I8MM pass
11923 10:05:51.223149 arm64_hwcap_sigill_sve2_i8mm skip
11924 10:05:51.226369 arm64_hwcap_cpuinfo_match_SVE2_F32MM pass
11925 10:05:51.229586 arm64_hwcap_sigill_sve2_f32mm skip
11926 10:05:51.232543 arm64_hwcap_cpuinfo_match_SVE2_F64MM pass
11927 10:05:51.236281 arm64_hwcap_sigill_sve2_f64mm skip
11928 10:05:51.239112 arm64_hwcap_cpuinfo_match_SVE2_BF16 pass
11929 10:05:51.242713 arm64_hwcap_sigill_sve2_bf16 skip
11930 10:05:51.246004 arm64_hwcap_cpuinfo_match_SVE2_EBF16 pass
11931 10:05:51.249125 arm64_hwcap_sigill_sve2_ebf16 skip
11932 10:05:51.252738 arm64_hwcap pass
11933 10:05:51.253255 arm64_ptrace_read_tpidr_one pass
11934 10:05:51.255643 arm64_ptrace_write_tpidr_one pass
11935 10:05:51.259077 arm64_ptrace_verify_tpidr_one pass
11936 10:05:51.262737 arm64_ptrace_count_tpidrs pass
11937 10:05:51.265521 arm64_ptrace_tpidr2_write pass
11938 10:05:51.268639 arm64_ptrace_tpidr2_read pass
11939 10:05:51.272343 arm64_ptrace_write_tpidr_only pass
11940 10:05:51.272804 arm64_ptrace pass
11941 10:05:51.275708 arm64_syscall-abi_getpid_FPSIMD pass
11942 10:05:51.278647 arm64_syscall-abi_sched_yield_FPSIMD pass
11943 10:05:51.282047 arm64_syscall-abi pass
11944 10:05:51.285524 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11945 10:05:51.292270 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11946 10:05:51.294965 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11947 10:05:51.298559 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11948 10:05:51.301811 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11949 10:05:51.305262 arm64_tpidr2 pass
11950 10:05:51.308839 + ../../utils/send-to-lava.sh ./output/result.txt
11951 10:05:51.314752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-arm64 RESULT=pass>
11952 10:05:51.315630 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-arm64 RESULT=pass
11954 10:05:51.321238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tags_test RESULT=pass>
11955 10:05:51.322100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tags_test RESULT=pass
11957 10:05:51.327809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass>
11958 10:05:51.328477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass
11960 10:05:51.403059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass>
11961 10:05:51.403911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass
11963 10:05:51.481661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass>
11964 10:05:51.482425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass
11966 10:05:51.564477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass>
11967 10:05:51.565269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass
11969 10:05:51.638798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass>
11970 10:05:51.639559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass
11972 10:05:51.713398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass>
11973 10:05:51.714153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass
11975 10:05:51.793179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass>
11976 10:05:51.793930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass
11978 10:05:51.870348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip>
11979 10:05:51.871092 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip
11981 10:05:51.950248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip>
11982 10:05:51.951071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip
11984 10:05:52.021799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass>
11985 10:05:52.022627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass
11987 10:05:52.093671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass>
11988 10:05:52.094485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass
11990 10:05:52.168930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass>
11991 10:05:52.169597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass
11993 10:05:52.244885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass>
11994 10:05:52.245666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass
11996 10:05:52.328534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass>
11997 10:05:52.329400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass
11999 10:05:52.401934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass>
12000 10:05:52.402654 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass
12002 10:05:52.481472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass>
12003 10:05:52.482233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass
12005 10:05:52.559021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass>
12006 10:05:52.559780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass
12008 10:05:52.631591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip>
12009 10:05:52.632279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip
12011 10:05:52.708184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip
12013 10:05:52.711238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip>
12014 10:05:52.785744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_za RESULT=pass>
12015 10:05:52.786434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_za RESULT=pass
12017 10:05:52.858227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_vl RESULT=skip>
12018 10:05:52.858946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_vl RESULT=skip
12020 10:05:52.931497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ssve_regs RESULT=skip>
12021 10:05:52.932259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ssve_regs RESULT=skip
12023 10:05:53.010685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_regs RESULT=skip>
12024 10:05:53.011440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_regs RESULT=skip
12026 10:05:53.087901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_vl RESULT=skip>
12027 10:05:53.088671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_vl RESULT=skip
12029 10:05:53.170698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_no_regs RESULT=skip>
12030 10:05:53.171456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_no_regs RESULT=skip
12032 10:05:53.251483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_regs RESULT=skip>
12033 10:05:53.252235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_regs RESULT=skip
12035 10:05:53.330639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
12037 10:05:53.333437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
12038 10:05:53.405741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
12040 10:05:53.408939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
12041 10:05:53.487011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_generic_pauth_not_enabled RESULT=skip>
12042 10:05:53.487763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_generic_pauth_not_enabled RESULT=skip
12044 10:05:53.560097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
12046 10:05:53.563114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
12047 10:05:53.633017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
12049 10:05:53.635476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
12050 10:05:53.712035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
12052 10:05:53.714847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
12053 10:05:53.801095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_generic_pauth_not_enabled RESULT=skip>
12054 10:05:53.801861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_generic_pauth_not_enabled RESULT=skip
12056 10:05:53.869062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac RESULT=pass>
12057 10:05:53.869842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac RESULT=pass
12059 10:05:53.950210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass>
12060 10:05:53.951039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass
12062 10:05:54.017714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass>
12063 10:05:54.017984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass
12065 10:05:54.078713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass>
12066 10:05:54.079090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass
12068 10:05:54.157706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass>
12069 10:05:54.158488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass
12071 10:05:54.235087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass>
12072 10:05:54.235838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass
12074 10:05:54.312541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass>
12075 10:05:54.313274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass
12077 10:05:54.393594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass>
12078 10:05:54.394363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass
12080 10:05:54.475486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass>
12081 10:05:54.476313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass
12083 10:05:54.549983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass>
12084 10:05:54.550834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass
12086 10:05:54.623858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass>
12087 10:05:54.624650 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass
12089 10:05:54.700706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass>
12090 10:05:54.701431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass
12092 10:05:54.777420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass>
12093 10:05:54.778142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass
12095 10:05:54.846640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass>
12096 10:05:54.847432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass
12098 10:05:54.917923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass>
12099 10:05:54.918848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass
12101 10:05:54.986542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass>
12102 10:05:54.986806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass
12104 10:05:55.055661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass>
12105 10:05:55.056128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass
12107 10:05:55.124825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress RESULT=pass>
12108 10:05:55.125592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress RESULT=pass
12110 10:05:55.209487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_sve_not_available RESULT=skip>
12111 10:05:55.209820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_sve_not_available RESULT=skip
12113 10:05:55.271247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace RESULT=skip>
12114 10:05:55.271515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace RESULT=skip
12116 10:05:55.336361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls_sve_not_available RESULT=skip>
12117 10:05:55.336674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls_sve_not_available RESULT=skip
12119 10:05:55.395735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip>
12120 10:05:55.396061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip
12122 10:05:55.459350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12123 10:05:55.459634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12125 10:05:55.526156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12126 10:05:55.526489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12128 10:05:55.592956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12129 10:05:55.593536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12131 10:05:55.666978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12132 10:05:55.667724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12134 10:05:55.742043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12135 10:05:55.742861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12137 10:05:55.817981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12138 10:05:55.818795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12140 10:05:55.892879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12141 10:05:55.893174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12143 10:05:55.965661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12144 10:05:55.966367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12146 10:05:56.042802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12147 10:05:56.043553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12149 10:05:56.117871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12150 10:05:56.118647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12152 10:05:56.194999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12153 10:05:56.195739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12155 10:05:56.273650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12156 10:05:56.274670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12158 10:05:56.343249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12159 10:05:56.343989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12161 10:05:56.422199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12162 10:05:56.422953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12164 10:05:56.494380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12165 10:05:56.494689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12167 10:05:56.568508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12168 10:05:56.569270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12170 10:05:56.642931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12171 10:05:56.643634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12173 10:05:56.717682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12174 10:05:56.718437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12176 10:05:56.793550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12177 10:05:56.794629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12179 10:05:56.874583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12180 10:05:56.875337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12182 10:05:56.952665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg RESULT=pass>
12183 10:05:56.953415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg RESULT=pass
12185 10:05:57.032594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass>
12186 10:05:57.033375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass
12188 10:05:57.099184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork RESULT=pass>
12189 10:05:57.099756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork RESULT=pass
12191 10:05:57.177363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_sme_not_available RESULT=skip>
12192 10:05:57.178155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_sme_not_available RESULT=skip
12194 10:05:57.251951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace RESULT=skip>
12195 10:05:57.252706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace RESULT=skip
12197 10:05:57.328867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip>
12198 10:05:57.329647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip
12200 10:05:57.411882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory RESULT=skip>
12201 10:05:57.412691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory RESULT=skip
12203 10:05:57.491064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip
12205 10:05:57.493526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip>
12206 10:05:57.573512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_ksm_options RESULT=skip>
12207 10:05:57.574380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_ksm_options RESULT=skip
12209 10:05:57.656023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options RESULT=skip>
12210 10:05:57.656846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options RESULT=skip
12212 10:05:57.736711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass>
12213 10:05:57.737464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass
12215 10:05:57.811341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass>
12216 10:05:57.812062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass
12218 10:05:57.892928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_sync RESULT=skip>
12219 10:05:57.893717 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_sync RESULT=skip
12221 10:05:57.972667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_async RESULT=skip>
12222 10:05:57.973412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_async RESULT=skip
12224 10:05:58.050978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_sync_async RESULT=skip
12226 10:05:58.053826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_sync_async RESULT=skip>
12227 10:05:58.132048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl RESULT=pass>
12228 10:05:58.132868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl RESULT=pass
12230 10:05:58.213192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip>
12231 10:05:58.214011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip
12233 10:05:58.294357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem RESULT=skip>
12234 10:05:58.295136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem RESULT=skip
12236 10:05:58.380916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip>
12237 10:05:58.381795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip
12239 10:05:58.460067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip>
12240 10:05:58.460796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip
12242 10:05:58.542503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip>
12243 10:05:58.543229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip
12245 10:05:58.622115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip>
12246 10:05:58.622906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip
12248 10:05:58.699062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip>
12249 10:05:58.699811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip
12251 10:05:58.778757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip>
12252 10:05:58.779673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip
12254 10:05:58.850244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip>
12255 10:05:58.850960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip
12257 10:05:58.935463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip>
12258 10:05:58.936232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip
12260 10:05:59.021297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip>
12261 10:05:59.022113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip
12263 10:05:59.104205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip>
12264 10:05:59.105183 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip
12266 10:05:59.181804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip>
12267 10:05:59.182591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip
12269 10:05:59.252063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip>
12270 10:05:59.252760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip
12272 10:05:59.326702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12273 10:05:59.327454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip
12275 10:05:59.406107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12276 10:05:59.406925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip
12278 10:05:59.489639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip>
12279 10:05:59.490418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip
12281 10:05:59.567034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip>
12282 10:05:59.567769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip
12284 10:05:59.642311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip>
12285 10:05:59.643113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip
12287 10:05:59.719819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip>
12288 10:05:59.720729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip
12290 10:05:59.794891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest RESULT=pass>
12291 10:05:59.795583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest RESULT=pass
12293 10:05:59.874483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip>
12294 10:05:59.875295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip
12296 10:05:59.951795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip>
12297 10:05:59.952540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip
12299 10:06:00.027917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip>
12300 10:06:00.028656 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip
12302 10:06:00.109036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip>
12303 10:06:00.109823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip
12305 10:06:00.188125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip>
12306 10:06:00.189063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip
12308 10:06:00.256010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip>
12309 10:06:00.256714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip
12311 10:06:00.322551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip>
12312 10:06:00.323261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip
12314 10:06:00.391934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip>
12315 10:06:00.392629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip
12317 10:06:00.467440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip>
12318 10:06:00.468133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip
12320 10:06:00.547757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip>
12321 10:06:00.548523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip
12323 10:06:00.624551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip>
12324 10:06:00.625236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip
12326 10:06:00.703720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip>
12327 10:06:00.704452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip
12329 10:06:00.780805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12330 10:06:00.781581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip
12332 10:06:00.860839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12333 10:06:00.861598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip
12335 10:06:00.941494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip>
12336 10:06:00.942324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip
12338 10:06:01.021771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip>
12339 10:06:01.022743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip
12341 10:06:01.097128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip>
12342 10:06:01.097854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip
12344 10:06:01.175907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip>
12345 10:06:01.176682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip
12347 10:06:01.253710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest RESULT=pass>
12348 10:06:01.254608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest RESULT=pass
12350 10:06:01.329808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass>
12351 10:06:01.330509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass
12353 10:06:01.408007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_rng RESULT=skip>
12354 10:06:01.408758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_rng RESULT=skip
12356 10:06:01.490469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass>
12357 10:06:01.491174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass
12359 10:06:01.564644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass>
12360 10:06:01.565405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass
12362 10:06:01.645384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass>
12363 10:06:01.646182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass
12365 10:06:01.720491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass>
12366 10:06:01.721222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass
12368 10:06:01.804680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass>
12369 10:06:01.805427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass
12371 10:06:01.881814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve_2 RESULT=skip>
12372 10:06:01.882608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve_2 RESULT=skip
12374 10:06:01.963770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass>
12375 10:06:01.964568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass
12377 10:06:02.033565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve_aes RESULT=skip>
12378 10:06:02.034354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve_aes RESULT=skip
12380 10:06:02.115359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass>
12381 10:06:02.116116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass
12383 10:06:02.192808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_pmull RESULT=skip>
12384 10:06:02.193539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_pmull RESULT=skip
12386 10:06:02.271696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass>
12387 10:06:02.272430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass
12389 10:06:02.349036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_bitperm RESULT=skip>
12390 10:06:02.349788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_bitperm RESULT=skip
12392 10:06:02.432820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass>
12393 10:06:02.433602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass
12395 10:06:02.504620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_sha3 RESULT=skip
12397 10:06:02.507439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_sha3 RESULT=skip>
12398 10:06:02.589710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass>
12399 10:06:02.590361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass
12401 10:06:02.658285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_sm4 RESULT=skip
12403 10:06:02.661136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_sm4 RESULT=skip>
12404 10:06:02.741725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass>
12405 10:06:02.742507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass
12407 10:06:02.813965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_i8mm RESULT=skip
12409 10:06:02.816828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_i8mm RESULT=skip>
12410 10:06:02.898764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass>
12411 10:06:02.899113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass
12413 10:06:02.965686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_f32mm RESULT=skip>
12414 10:06:02.966435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_f32mm RESULT=skip
12416 10:06:03.040591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass>
12417 10:06:03.041381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass
12419 10:06:03.115973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_f64mm RESULT=skip>
12420 10:06:03.116737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_f64mm RESULT=skip
12422 10:06:03.191191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass>
12423 10:06:03.191976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass
12425 10:06:03.266206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_bf16 RESULT=skip
12427 10:06:03.269697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_bf16 RESULT=skip>
12428 10:06:03.346743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass>
12429 10:06:03.347539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass
12431 10:06:03.427633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_ebf16 RESULT=skip>
12432 10:06:03.428418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_ebf16 RESULT=skip
12434 10:06:03.496397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap RESULT=pass>
12435 10:06:03.497294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap RESULT=pass
12437 10:06:03.575156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass
12439 10:06:03.577923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass>
12440 10:06:03.653511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass
12442 10:06:03.656594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass>
12443 10:06:03.733221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass>
12444 10:06:03.734030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass
12446 10:06:03.808418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass>
12447 10:06:03.809196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass
12449 10:06:03.880850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass>
12450 10:06:03.881649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass
12452 10:06:03.962413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass>
12453 10:06:03.963171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass
12455 10:06:04.042574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass>
12456 10:06:04.043306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass
12458 10:06:04.115772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace RESULT=pass>
12459 10:06:04.116542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace RESULT=pass
12461 10:06:04.198450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass>
12462 10:06:04.199228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass
12464 10:06:04.276278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass>
12465 10:06:04.277024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass
12467 10:06:04.352688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi RESULT=pass>
12468 10:06:04.353438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi RESULT=pass
12470 10:06:04.435645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12471 10:06:04.436361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12473 10:06:04.511768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12474 10:06:04.512526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12476 10:06:04.585030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12477 10:06:04.585823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12479 10:06:04.659573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12480 10:06:04.660279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12482 10:06:04.730652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12483 10:06:04.731395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12485 10:06:04.799779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2 RESULT=pass>
12486 10:06:04.800278 + set +x
12487 10:06:04.800865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2 RESULT=pass
12489 10:06:04.806077 <LAVA_SIGNAL_ENDRUN 1_kselftest-arm64 12073344_1.6.2.3.5>
12490 10:06:04.806773 Received signal: <ENDRUN> 1_kselftest-arm64 12073344_1.6.2.3.5
12491 10:06:04.807140 Ending use of test pattern.
12492 10:06:04.807446 Ending test lava.1_kselftest-arm64 (12073344_1.6.2.3.5), duration 39.72
12494 10:06:04.809349 <LAVA_TEST_RUNNER EXIT>
12495 10:06:04.810006 ok: lava_test_shell seems to have completed
12496 10:06:04.815015 arm64_btitest: pass
arm64_btitest_bti_c_func_call_using_blr: skip
arm64_btitest_bti_c_func_call_using_br_x0: skip
arm64_btitest_bti_c_func_call_using_br_x16: skip
arm64_btitest_bti_j_func_call_using_blr: skip
arm64_btitest_bti_j_func_call_using_br_x0: skip
arm64_btitest_bti_j_func_call_using_br_x16: skip
arm64_btitest_bti_jc_func_call_using_blr: skip
arm64_btitest_bti_jc_func_call_using_br_x0: skip
arm64_btitest_bti_jc_func_call_using_br_x16: skip
arm64_btitest_bti_none_func_call_using_blr: skip
arm64_btitest_bti_none_func_call_using_br_x0: skip
arm64_btitest_bti_none_func_call_using_br_x16: skip
arm64_btitest_nohint_func_call_using_blr: skip
arm64_btitest_nohint_func_call_using_br_x0: skip
arm64_btitest_nohint_func_call_using_br_x16: skip
arm64_btitest_paciasp_func_call_using_blr: skip
arm64_btitest_paciasp_func_call_using_br_x0: skip
arm64_btitest_paciasp_func_call_using_br_x16: skip
arm64_check_buffer_fill: skip
arm64_check_child_memory: skip
arm64_check_gcr_el1_cswitch: skip
arm64_check_ksm_options: skip
arm64_check_mmap_options: skip
arm64_check_prctl: pass
arm64_check_prctl_NONE: pass
arm64_check_prctl_async: skip
arm64_check_prctl_check_basic_read: pass
arm64_check_prctl_sync: skip
arm64_check_prctl_sync_async: skip
arm64_check_tags_inclusion: skip
arm64_check_user_mem: skip
arm64_fake_sigreturn_bad_magic: pass
arm64_fake_sigreturn_bad_size: pass
arm64_fake_sigreturn_bad_size_for_magic0: pass
arm64_fake_sigreturn_duplicated_fpsimd: pass
arm64_fake_sigreturn_misaligned_sp: pass
arm64_fake_sigreturn_missing_fpsimd: pass
arm64_fake_sigreturn_sme_change_vl: skip
arm64_fake_sigreturn_sve_change_vl: skip
arm64_fp-stress: pass
arm64_fp-stress_FPSIMD-0-0: pass
arm64_fp-stress_FPSIMD-0-1: pass
arm64_fp-stress_FPSIMD-1-0: pass
arm64_fp-stress_FPSIMD-1-1: pass
arm64_fp-stress_FPSIMD-2-0: pass
arm64_fp-stress_FPSIMD-2-1: pass
arm64_fp-stress_FPSIMD-3-0: pass
arm64_fp-stress_FPSIMD-3-1: pass
arm64_fp-stress_FPSIMD-4-0: pass
arm64_fp-stress_FPSIMD-4-1: pass
arm64_fp-stress_FPSIMD-5-0: pass
arm64_fp-stress_FPSIMD-5-1: pass
arm64_fp-stress_FPSIMD-6-0: pass
arm64_fp-stress_FPSIMD-6-1: pass
arm64_fp-stress_FPSIMD-7-0: pass
arm64_fp-stress_FPSIMD-7-1: pass
arm64_hwcap: pass
arm64_hwcap_cpuinfo_match_RNG: pass
arm64_hwcap_cpuinfo_match_SME: pass
arm64_hwcap_cpuinfo_match_SVE: pass
arm64_hwcap_cpuinfo_match_SVE2_BF16: pass
arm64_hwcap_cpuinfo_match_SVE2_BITPERM: pass
arm64_hwcap_cpuinfo_match_SVE2_EBF16: pass
arm64_hwcap_cpuinfo_match_SVE2_F32MM: pass
arm64_hwcap_cpuinfo_match_SVE2_F64MM: pass
arm64_hwcap_cpuinfo_match_SVE2_I8MM: pass
arm64_hwcap_cpuinfo_match_SVE2_PMULL: pass
arm64_hwcap_cpuinfo_match_SVE2_SHA3: pass
arm64_hwcap_cpuinfo_match_SVE2_SM4: pass
arm64_hwcap_cpuinfo_match_SVE_2: pass
arm64_hwcap_cpuinfo_match_SVE_AES: pass
arm64_hwcap_sigill_SME: pass
arm64_hwcap_sigill_SVE: pass
arm64_hwcap_sigill_rng: skip
arm64_hwcap_sigill_sve2_bf16: skip
arm64_hwcap_sigill_sve2_bitperm: skip
arm64_hwcap_sigill_sve2_ebf16: skip
arm64_hwcap_sigill_sve2_f32mm: skip
arm64_hwcap_sigill_sve2_f64mm: skip
arm64_hwcap_sigill_sve2_i8mm: skip
arm64_hwcap_sigill_sve2_pmull: skip
arm64_hwcap_sigill_sve2_sha3: skip
arm64_hwcap_sigill_sve2_sm4: skip
arm64_hwcap_sigill_sve_2: skip
arm64_hwcap_sigill_sve_aes: skip
arm64_mangle_pstate_invalid_compat_toggle: pass
arm64_mangle_pstate_invalid_daif_bits: pass
arm64_mangle_pstate_invalid_mode_el1h: pass
arm64_mangle_pstate_invalid_mode_el1t: pass
arm64_mangle_pstate_invalid_mode_el2h: pass
arm64_mangle_pstate_invalid_mode_el2t: pass
arm64_mangle_pstate_invalid_mode_el3h: pass
arm64_mangle_pstate_invalid_mode_el3t: pass
arm64_nobtitest: pass
arm64_nobtitest_bti_c_func_call_using_blr: skip
arm64_nobtitest_bti_c_func_call_using_br_x0: skip
arm64_nobtitest_bti_c_func_call_using_br_x16: skip
arm64_nobtitest_bti_j_func_call_using_blr: skip
arm64_nobtitest_bti_j_func_call_using_br_x0: skip
arm64_nobtitest_bti_j_func_call_using_br_x16: skip
arm64_nobtitest_bti_jc_func_call_using_blr: skip
arm64_nobtitest_bti_jc_func_call_using_br_x0: skip
arm64_nobtitest_bti_jc_func_call_using_br_x16: skip
arm64_nobtitest_bti_none_func_call_using_blr: skip
arm64_nobtitest_bti_none_func_call_using_br_x0: skip
arm64_nobtitest_bti_none_func_call_using_br_x16: skip
arm64_nobtitest_nohint_func_call_using_blr: skip
arm64_nobtitest_nohint_func_call_using_br_x0: skip
arm64_nobtitest_nohint_func_call_using_br_x16: skip
arm64_nobtitest_paciasp_func_call_using_blr: skip
arm64_nobtitest_paciasp_func_call_using_br_x0: skip
arm64_nobtitest_paciasp_func_call_using_br_x16: skip
arm64_pac: pass
arm64_pac_generic_pauth_not_enabled: skip
arm64_pac_pauth_not_enabled: skip
arm64_ptrace: pass
arm64_ptrace_count_tpidrs: pass
arm64_ptrace_read_tpidr_one: pass
arm64_ptrace_tpidr2_read: pass
arm64_ptrace_tpidr2_write: pass
arm64_ptrace_verify_tpidr_one: pass
arm64_ptrace_write_tpidr_one: pass
arm64_ptrace_write_tpidr_only: pass
arm64_run_tags_test_sh: pass
arm64_sme_trap_no_sm: skip
arm64_sme_trap_non_streaming: skip
arm64_sme_trap_za: pass
arm64_sme_vl: skip
arm64_ssve_regs: skip
arm64_sve-probe-vls: skip
arm64_sve-probe-vls_sve_not_available: skip
arm64_sve-ptrace: skip
arm64_sve-ptrace_sve_not_available: skip
arm64_sve_regs: skip
arm64_sve_vl: skip
arm64_syscall-abi: pass
arm64_syscall-abi_getpid_FPSIMD: pass
arm64_syscall-abi_sched_yield_FPSIMD: pass
arm64_tags_test: pass
arm64_tpidr2: pass
arm64_tpidr2_skipped_TPIDR2_not_supported: pass
arm64_vec-syscfg: pass
arm64_vec-syscfg_sme_not_supported: skip
arm64_vec-syscfg_sve_not_supported: skip
arm64_za-fork: pass
arm64_za-fork_skipped: pass
arm64_za-ptrace: skip
arm64_za-ptrace_sme_not_available: skip
arm64_za_no_regs: skip
arm64_za_regs: skip
shardfile-arm64: pass
12497 10:06:04.815745 end: 3.1 lava-test-shell (duration 00:00:41) [common]
12498 10:06:04.816199 end: 3 lava-test-retry (duration 00:00:41) [common]
12499 10:06:04.816857 start: 4 finalize (timeout 00:06:36) [common]
12500 10:06:04.817521 start: 4.1 power-off (timeout 00:00:30) [common]
12501 10:06:04.818920 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=off'
12502 10:06:04.940650 >> Command sent successfully.
12503 10:06:04.944653 Returned 0 in 0 seconds
12504 10:06:05.045549 end: 4.1 power-off (duration 00:00:00) [common]
12506 10:06:05.047360 start: 4.2 read-feedback (timeout 00:06:35) [common]
12507 10:06:05.048653 Listened to connection for namespace 'common' for up to 1s
12508 10:06:06.049358 Finalising connection for namespace 'common'
12509 10:06:06.050105 Disconnecting from shell: Finalise
12510 10:06:06.050636 / #
12511 10:06:06.151956 end: 4.2 read-feedback (duration 00:00:01) [common]
12512 10:06:06.152699 end: 4 finalize (duration 00:00:01) [common]
12513 10:06:06.153305 Cleaning after the job
12514 10:06:06.153857 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12073344/tftp-deploy-x5o2dtz4/ramdisk
12515 10:06:06.167725 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12073344/tftp-deploy-x5o2dtz4/kernel
12516 10:06:06.198223 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12073344/tftp-deploy-x5o2dtz4/dtb
12517 10:06:06.198529 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12073344/tftp-deploy-x5o2dtz4/nfsrootfs
12518 10:06:06.290546 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12073344/tftp-deploy-x5o2dtz4/modules
12519 10:06:06.297506 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12073344
12520 10:06:06.936623 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12073344
12521 10:06:06.936805 Job finished correctly