Boot log: mt8192-asurada-spherion-r0
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 22
- Kernel Errors: 27
- Errors: 1
1 23:02:41.857836 lava-dispatcher, installed at version: 2023.10
2 23:02:41.858040 start: 0 validate
3 23:02:41.858166 Start time: 2023-12-01 23:02:41.858158+00:00 (UTC)
4 23:02:41.858284 Using caching service: 'http://localhost/cache/?uri=%s'
5 23:02:41.858465 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 23:02:42.126514 Using caching service: 'http://localhost/cache/?uri=%s'
7 23:02:42.127267 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.64-cip10%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 23:03:04.915951 Using caching service: 'http://localhost/cache/?uri=%s'
9 23:03:04.916713 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.64-cip10%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 23:03:05.186211 Using caching service: 'http://localhost/cache/?uri=%s'
11 23:03:05.187055 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.64-cip10%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 23:03:08.454505 validate duration: 26.60
14 23:03:08.454778 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 23:03:08.454880 start: 1.1 download-retry (timeout 00:10:00) [common]
16 23:03:08.454967 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 23:03:08.455088 Not decompressing ramdisk as can be used compressed.
18 23:03:08.455175 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230623.0/arm64/rootfs.cpio.gz
19 23:03:08.455241 saving as /var/lib/lava/dispatcher/tmp/12154372/tftp-deploy-61zxytub/ramdisk/rootfs.cpio.gz
20 23:03:08.455307 total size: 8181372 (7 MB)
21 23:03:08.711884 progress 0 % (0 MB)
22 23:03:08.715399 progress 5 % (0 MB)
23 23:03:08.718621 progress 10 % (0 MB)
24 23:03:08.722004 progress 15 % (1 MB)
25 23:03:08.725468 progress 20 % (1 MB)
26 23:03:08.728982 progress 25 % (1 MB)
27 23:03:08.732594 progress 30 % (2 MB)
28 23:03:08.736123 progress 35 % (2 MB)
29 23:03:08.739471 progress 40 % (3 MB)
30 23:03:08.742948 progress 45 % (3 MB)
31 23:03:08.746170 progress 50 % (3 MB)
32 23:03:08.749765 progress 55 % (4 MB)
33 23:03:08.752916 progress 60 % (4 MB)
34 23:03:08.756393 progress 65 % (5 MB)
35 23:03:08.759751 progress 70 % (5 MB)
36 23:03:08.763236 progress 75 % (5 MB)
37 23:03:08.766583 progress 80 % (6 MB)
38 23:03:08.770007 progress 85 % (6 MB)
39 23:03:08.772185 progress 90 % (7 MB)
40 23:03:08.774409 progress 95 % (7 MB)
41 23:03:08.776552 progress 100 % (7 MB)
42 23:03:08.776749 7 MB downloaded in 0.32 s (24.27 MB/s)
43 23:03:08.776912 end: 1.1.1 http-download (duration 00:00:00) [common]
45 23:03:08.777156 end: 1.1 download-retry (duration 00:00:00) [common]
46 23:03:08.777244 start: 1.2 download-retry (timeout 00:10:00) [common]
47 23:03:08.777329 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 23:03:08.777464 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.64-cip10/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 23:03:08.777534 saving as /var/lib/lava/dispatcher/tmp/12154372/tftp-deploy-61zxytub/kernel/Image
50 23:03:08.777596 total size: 49172992 (46 MB)
51 23:03:08.777658 No compression specified
52 23:03:08.778763 progress 0 % (0 MB)
53 23:03:08.791199 progress 5 % (2 MB)
54 23:03:08.803683 progress 10 % (4 MB)
55 23:03:08.816071 progress 15 % (7 MB)
56 23:03:08.828441 progress 20 % (9 MB)
57 23:03:08.841040 progress 25 % (11 MB)
58 23:03:08.853467 progress 30 % (14 MB)
59 23:03:08.866200 progress 35 % (16 MB)
60 23:03:08.878722 progress 40 % (18 MB)
61 23:03:08.891167 progress 45 % (21 MB)
62 23:03:08.903722 progress 50 % (23 MB)
63 23:03:08.916159 progress 55 % (25 MB)
64 23:03:08.928593 progress 60 % (28 MB)
65 23:03:08.940993 progress 65 % (30 MB)
66 23:03:08.953308 progress 70 % (32 MB)
67 23:03:08.966238 progress 75 % (35 MB)
68 23:03:08.979022 progress 80 % (37 MB)
69 23:03:08.991519 progress 85 % (39 MB)
70 23:03:09.004139 progress 90 % (42 MB)
71 23:03:09.016454 progress 95 % (44 MB)
72 23:03:09.028769 progress 100 % (46 MB)
73 23:03:09.029014 46 MB downloaded in 0.25 s (186.52 MB/s)
74 23:03:09.029171 end: 1.2.1 http-download (duration 00:00:00) [common]
76 23:03:09.029411 end: 1.2 download-retry (duration 00:00:00) [common]
77 23:03:09.029501 start: 1.3 download-retry (timeout 00:09:59) [common]
78 23:03:09.029592 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 23:03:09.029732 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.64-cip10/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 23:03:09.029806 saving as /var/lib/lava/dispatcher/tmp/12154372/tftp-deploy-61zxytub/dtb/mt8192-asurada-spherion-r0.dtb
81 23:03:09.029869 total size: 47278 (0 MB)
82 23:03:09.029931 No compression specified
83 23:03:09.031067 progress 69 % (0 MB)
84 23:03:09.031382 progress 100 % (0 MB)
85 23:03:09.031538 0 MB downloaded in 0.00 s (27.05 MB/s)
86 23:03:09.031662 end: 1.3.1 http-download (duration 00:00:00) [common]
88 23:03:09.031886 end: 1.3 download-retry (duration 00:00:00) [common]
89 23:03:09.031975 start: 1.4 download-retry (timeout 00:09:59) [common]
90 23:03:09.032059 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 23:03:09.032169 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.64-cip10/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 23:03:09.032238 saving as /var/lib/lava/dispatcher/tmp/12154372/tftp-deploy-61zxytub/modules/modules.tar
93 23:03:09.032299 total size: 8616152 (8 MB)
94 23:03:09.032360 Using unxz to decompress xz
95 23:03:09.035991 progress 0 % (0 MB)
96 23:03:09.057459 progress 5 % (0 MB)
97 23:03:09.081326 progress 10 % (0 MB)
98 23:03:09.105218 progress 15 % (1 MB)
99 23:03:09.128908 progress 20 % (1 MB)
100 23:03:09.153466 progress 25 % (2 MB)
101 23:03:09.179552 progress 30 % (2 MB)
102 23:03:09.206482 progress 35 % (2 MB)
103 23:03:09.229950 progress 40 % (3 MB)
104 23:03:09.254520 progress 45 % (3 MB)
105 23:03:09.280051 progress 50 % (4 MB)
106 23:03:09.304758 progress 55 % (4 MB)
107 23:03:09.329526 progress 60 % (4 MB)
108 23:03:09.354932 progress 65 % (5 MB)
109 23:03:09.384196 progress 70 % (5 MB)
110 23:03:09.408324 progress 75 % (6 MB)
111 23:03:09.435121 progress 80 % (6 MB)
112 23:03:09.461002 progress 85 % (7 MB)
113 23:03:09.487391 progress 90 % (7 MB)
114 23:03:09.517171 progress 95 % (7 MB)
115 23:03:09.544661 progress 100 % (8 MB)
116 23:03:09.551075 8 MB downloaded in 0.52 s (15.84 MB/s)
117 23:03:09.551394 end: 1.4.1 http-download (duration 00:00:01) [common]
119 23:03:09.551782 end: 1.4 download-retry (duration 00:00:01) [common]
120 23:03:09.551910 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 23:03:09.552048 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 23:03:09.552166 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 23:03:09.552295 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 23:03:09.552584 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12154372/lava-overlay-vzn737s0
125 23:03:09.552764 makedir: /var/lib/lava/dispatcher/tmp/12154372/lava-overlay-vzn737s0/lava-12154372/bin
126 23:03:09.552906 makedir: /var/lib/lava/dispatcher/tmp/12154372/lava-overlay-vzn737s0/lava-12154372/tests
127 23:03:09.553041 makedir: /var/lib/lava/dispatcher/tmp/12154372/lava-overlay-vzn737s0/lava-12154372/results
128 23:03:09.553199 Creating /var/lib/lava/dispatcher/tmp/12154372/lava-overlay-vzn737s0/lava-12154372/bin/lava-add-keys
129 23:03:09.553397 Creating /var/lib/lava/dispatcher/tmp/12154372/lava-overlay-vzn737s0/lava-12154372/bin/lava-add-sources
130 23:03:09.553572 Creating /var/lib/lava/dispatcher/tmp/12154372/lava-overlay-vzn737s0/lava-12154372/bin/lava-background-process-start
131 23:03:09.553743 Creating /var/lib/lava/dispatcher/tmp/12154372/lava-overlay-vzn737s0/lava-12154372/bin/lava-background-process-stop
132 23:03:09.553911 Creating /var/lib/lava/dispatcher/tmp/12154372/lava-overlay-vzn737s0/lava-12154372/bin/lava-common-functions
133 23:03:09.554087 Creating /var/lib/lava/dispatcher/tmp/12154372/lava-overlay-vzn737s0/lava-12154372/bin/lava-echo-ipv4
134 23:03:09.554257 Creating /var/lib/lava/dispatcher/tmp/12154372/lava-overlay-vzn737s0/lava-12154372/bin/lava-install-packages
135 23:03:09.554464 Creating /var/lib/lava/dispatcher/tmp/12154372/lava-overlay-vzn737s0/lava-12154372/bin/lava-installed-packages
136 23:03:09.554641 Creating /var/lib/lava/dispatcher/tmp/12154372/lava-overlay-vzn737s0/lava-12154372/bin/lava-os-build
137 23:03:09.554808 Creating /var/lib/lava/dispatcher/tmp/12154372/lava-overlay-vzn737s0/lava-12154372/bin/lava-probe-channel
138 23:03:09.554976 Creating /var/lib/lava/dispatcher/tmp/12154372/lava-overlay-vzn737s0/lava-12154372/bin/lava-probe-ip
139 23:03:09.555153 Creating /var/lib/lava/dispatcher/tmp/12154372/lava-overlay-vzn737s0/lava-12154372/bin/lava-target-ip
140 23:03:09.555322 Creating /var/lib/lava/dispatcher/tmp/12154372/lava-overlay-vzn737s0/lava-12154372/bin/lava-target-mac
141 23:03:09.555485 Creating /var/lib/lava/dispatcher/tmp/12154372/lava-overlay-vzn737s0/lava-12154372/bin/lava-target-storage
142 23:03:09.555664 Creating /var/lib/lava/dispatcher/tmp/12154372/lava-overlay-vzn737s0/lava-12154372/bin/lava-test-case
143 23:03:09.555833 Creating /var/lib/lava/dispatcher/tmp/12154372/lava-overlay-vzn737s0/lava-12154372/bin/lava-test-event
144 23:03:09.556000 Creating /var/lib/lava/dispatcher/tmp/12154372/lava-overlay-vzn737s0/lava-12154372/bin/lava-test-feedback
145 23:03:09.556178 Creating /var/lib/lava/dispatcher/tmp/12154372/lava-overlay-vzn737s0/lava-12154372/bin/lava-test-raise
146 23:03:09.556346 Creating /var/lib/lava/dispatcher/tmp/12154372/lava-overlay-vzn737s0/lava-12154372/bin/lava-test-reference
147 23:03:09.556512 Creating /var/lib/lava/dispatcher/tmp/12154372/lava-overlay-vzn737s0/lava-12154372/bin/lava-test-runner
148 23:03:09.556685 Creating /var/lib/lava/dispatcher/tmp/12154372/lava-overlay-vzn737s0/lava-12154372/bin/lava-test-set
149 23:03:09.556849 Creating /var/lib/lava/dispatcher/tmp/12154372/lava-overlay-vzn737s0/lava-12154372/bin/lava-test-shell
150 23:03:09.557019 Updating /var/lib/lava/dispatcher/tmp/12154372/lava-overlay-vzn737s0/lava-12154372/bin/lava-install-packages (oe)
151 23:03:09.557214 Updating /var/lib/lava/dispatcher/tmp/12154372/lava-overlay-vzn737s0/lava-12154372/bin/lava-installed-packages (oe)
152 23:03:09.557382 Creating /var/lib/lava/dispatcher/tmp/12154372/lava-overlay-vzn737s0/lava-12154372/environment
153 23:03:09.557521 LAVA metadata
154 23:03:09.557626 - LAVA_JOB_ID=12154372
155 23:03:09.557718 - LAVA_DISPATCHER_IP=192.168.201.1
156 23:03:09.557860 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 23:03:09.557964 skipped lava-vland-overlay
158 23:03:09.558073 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 23:03:09.558194 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 23:03:09.558289 skipped lava-multinode-overlay
161 23:03:09.558436 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 23:03:09.558574 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 23:03:09.558680 Loading test definitions
164 23:03:09.558819 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 23:03:09.558930 Using /lava-12154372 at stage 0
166 23:03:09.559364 uuid=12154372_1.5.2.3.1 testdef=None
167 23:03:09.559494 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 23:03:09.559616 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 23:03:09.560345 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 23:03:09.560672 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 23:03:09.561598 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 23:03:09.561942 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 23:03:09.562845 runner path: /var/lib/lava/dispatcher/tmp/12154372/lava-overlay-vzn737s0/lava-12154372/0/tests/0_dmesg test_uuid 12154372_1.5.2.3.1
176 23:03:09.563049 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 23:03:09.563392 start: 1.5.2.3.5 inline-repo-action (timeout 00:09:59) [common]
179 23:03:09.563497 Using /lava-12154372 at stage 1
180 23:03:09.563897 uuid=12154372_1.5.2.3.5 testdef=None
181 23:03:09.564018 end: 1.5.2.3.5 inline-repo-action (duration 00:00:00) [common]
182 23:03:09.564138 start: 1.5.2.3.6 test-overlay (timeout 00:09:59) [common]
183 23:03:09.564811 end: 1.5.2.3.6 test-overlay (duration 00:00:00) [common]
185 23:03:09.565142 start: 1.5.2.3.7 test-install-overlay (timeout 00:09:59) [common]
186 23:03:09.566660 end: 1.5.2.3.7 test-install-overlay (duration 00:00:00) [common]
188 23:03:09.567007 start: 1.5.2.3.8 test-runscript-overlay (timeout 00:09:59) [common]
189 23:03:09.567887 runner path: /var/lib/lava/dispatcher/tmp/12154372/lava-overlay-vzn737s0/lava-12154372/1/tests/1_bootrr test_uuid 12154372_1.5.2.3.5
190 23:03:09.568083 end: 1.5.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
192 23:03:09.568403 Creating lava-test-runner.conf files
193 23:03:09.568500 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12154372/lava-overlay-vzn737s0/lava-12154372/0 for stage 0
194 23:03:09.568622 - 0_dmesg
195 23:03:09.568734 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12154372/lava-overlay-vzn737s0/lava-12154372/1 for stage 1
196 23:03:09.568858 - 1_bootrr
197 23:03:09.568998 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
198 23:03:09.569123 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
199 23:03:09.579936 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
200 23:03:09.580083 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
201 23:03:09.580204 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
202 23:03:09.580327 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
203 23:03:09.580459 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
204 23:03:09.814437 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:00) [common]
205 23:03:09.814817 start: 1.5.4 extract-modules (timeout 00:09:59) [common]
206 23:03:09.814927 extracting modules file /var/lib/lava/dispatcher/tmp/12154372/tftp-deploy-61zxytub/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12154372/extract-overlay-ramdisk-uah4lukz/ramdisk
207 23:03:10.016190 end: 1.5.4 extract-modules (duration 00:00:00) [common]
208 23:03:10.016363 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
209 23:03:10.016459 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12154372/compress-overlay-xdvd_9b6/overlay-1.5.2.4.tar.gz to ramdisk
210 23:03:10.016530 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12154372/compress-overlay-xdvd_9b6/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12154372/extract-overlay-ramdisk-uah4lukz/ramdisk
211 23:03:10.024490 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
212 23:03:10.024619 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
213 23:03:10.024704 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
214 23:03:10.024793 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
215 23:03:10.024876 Building ramdisk /var/lib/lava/dispatcher/tmp/12154372/extract-overlay-ramdisk-uah4lukz/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12154372/extract-overlay-ramdisk-uah4lukz/ramdisk
216 23:03:10.415372 >> 145322 blocks
217 23:03:12.689240 rename /var/lib/lava/dispatcher/tmp/12154372/extract-overlay-ramdisk-uah4lukz/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12154372/tftp-deploy-61zxytub/ramdisk/ramdisk.cpio.gz
218 23:03:12.689761 end: 1.5.7 compress-ramdisk (duration 00:00:03) [common]
219 23:03:12.689926 start: 1.5.8 prepare-kernel (timeout 00:09:56) [common]
220 23:03:12.690065 start: 1.5.8.1 prepare-fit (timeout 00:09:56) [common]
221 23:03:12.690220 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12154372/tftp-deploy-61zxytub/kernel/Image'
222 23:03:25.614872 Returned 0 in 12 seconds
223 23:03:25.715497 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12154372/tftp-deploy-61zxytub/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12154372/tftp-deploy-61zxytub/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12154372/tftp-deploy-61zxytub/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12154372/tftp-deploy-61zxytub/kernel/image.itb
224 23:03:26.682208 output: FIT description: Kernel Image image with one or more FDT blobs
225 23:03:26.682592 output: Created: Fri Dec 1 23:03:26 2023
226 23:03:26.682665 output: Image 0 (kernel-1)
227 23:03:26.682789 output: Description:
228 23:03:26.682880 output: Created: Fri Dec 1 23:03:26 2023
229 23:03:26.682971 output: Type: Kernel Image
230 23:03:26.683063 output: Compression: lzma compressed
231 23:03:26.683142 output: Data Size: 11043984 Bytes = 10785.14 KiB = 10.53 MiB
232 23:03:26.683215 output: Architecture: AArch64
233 23:03:26.683273 output: OS: Linux
234 23:03:26.683331 output: Load Address: 0x00000000
235 23:03:26.683389 output: Entry Point: 0x00000000
236 23:03:26.683443 output: Hash algo: crc32
237 23:03:26.683499 output: Hash value: 36c84243
238 23:03:26.683554 output: Image 1 (fdt-1)
239 23:03:26.683608 output: Description: mt8192-asurada-spherion-r0
240 23:03:26.683660 output: Created: Fri Dec 1 23:03:26 2023
241 23:03:26.683713 output: Type: Flat Device Tree
242 23:03:26.683766 output: Compression: uncompressed
243 23:03:26.683819 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
244 23:03:26.683872 output: Architecture: AArch64
245 23:03:26.683924 output: Hash algo: crc32
246 23:03:26.683977 output: Hash value: cc4352de
247 23:03:26.684030 output: Image 2 (ramdisk-1)
248 23:03:26.684082 output: Description: unavailable
249 23:03:26.684134 output: Created: Fri Dec 1 23:03:26 2023
250 23:03:26.684187 output: Type: RAMDisk Image
251 23:03:26.684240 output: Compression: Unknown Compression
252 23:03:26.684293 output: Data Size: 21394303 Bytes = 20892.87 KiB = 20.40 MiB
253 23:03:26.684345 output: Architecture: AArch64
254 23:03:26.684398 output: OS: Linux
255 23:03:26.684450 output: Load Address: unavailable
256 23:03:26.684503 output: Entry Point: unavailable
257 23:03:26.684556 output: Hash algo: crc32
258 23:03:26.684608 output: Hash value: 34e70a22
259 23:03:26.684660 output: Default Configuration: 'conf-1'
260 23:03:26.684713 output: Configuration 0 (conf-1)
261 23:03:26.684765 output: Description: mt8192-asurada-spherion-r0
262 23:03:26.684817 output: Kernel: kernel-1
263 23:03:26.684869 output: Init Ramdisk: ramdisk-1
264 23:03:26.684922 output: FDT: fdt-1
265 23:03:26.684974 output: Loadables: kernel-1
266 23:03:26.685026 output:
267 23:03:26.685207 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
268 23:03:26.685303 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
269 23:03:26.685410 end: 1.5 prepare-tftp-overlay (duration 00:00:17) [common]
270 23:03:26.685502 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:42) [common]
271 23:03:26.685582 No LXC device requested
272 23:03:26.685660 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
273 23:03:26.685744 start: 1.7 deploy-device-env (timeout 00:09:42) [common]
274 23:03:26.685822 end: 1.7 deploy-device-env (duration 00:00:00) [common]
275 23:03:26.685890 Checking files for TFTP limit of 4294967296 bytes.
276 23:03:26.686368 end: 1 tftp-deploy (duration 00:00:18) [common]
277 23:03:26.686508 start: 2 depthcharge-action (timeout 00:05:00) [common]
278 23:03:26.686598 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
279 23:03:26.686718 substitutions:
280 23:03:26.686784 - {DTB}: 12154372/tftp-deploy-61zxytub/dtb/mt8192-asurada-spherion-r0.dtb
281 23:03:26.686847 - {INITRD}: 12154372/tftp-deploy-61zxytub/ramdisk/ramdisk.cpio.gz
282 23:03:26.686906 - {KERNEL}: 12154372/tftp-deploy-61zxytub/kernel/Image
283 23:03:26.686963 - {LAVA_MAC}: None
284 23:03:26.687020 - {PRESEED_CONFIG}: None
285 23:03:26.687075 - {PRESEED_LOCAL}: None
286 23:03:26.687130 - {RAMDISK}: 12154372/tftp-deploy-61zxytub/ramdisk/ramdisk.cpio.gz
287 23:03:26.687185 - {ROOT_PART}: None
288 23:03:26.687239 - {ROOT}: None
289 23:03:26.687293 - {SERVER_IP}: 192.168.201.1
290 23:03:26.687347 - {TEE}: None
291 23:03:26.687399 Parsed boot commands:
292 23:03:26.687452 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
293 23:03:26.687623 Parsed boot commands: tftpboot 192.168.201.1 12154372/tftp-deploy-61zxytub/kernel/image.itb 12154372/tftp-deploy-61zxytub/kernel/cmdline
294 23:03:26.687712 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
295 23:03:26.687795 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
296 23:03:26.687888 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
297 23:03:26.687975 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
298 23:03:26.688045 Not connected, no need to disconnect.
299 23:03:26.688118 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
300 23:03:26.688197 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
301 23:03:26.688263 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-1'
302 23:03:26.691780 Setting prompt string to ['lava-test: # ']
303 23:03:26.692140 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
304 23:03:26.692263 end: 2.2.1 reset-connection (duration 00:00:00) [common]
305 23:03:26.692390 start: 2.2.2 reset-device (timeout 00:05:00) [common]
306 23:03:26.692658 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
307 23:03:26.692868 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=reboot'
308 23:03:31.830228 >> Command sent successfully.
309 23:03:31.840367 Returned 0 in 5 seconds
310 23:03:31.941448 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
312 23:03:31.942197 end: 2.2.2 reset-device (duration 00:00:05) [common]
313 23:03:31.942511 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
314 23:03:31.942773 Setting prompt string to 'Starting depthcharge on Spherion...'
315 23:03:31.942980 Changing prompt to 'Starting depthcharge on Spherion...'
316 23:03:31.943182 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
317 23:03:31.943896 [Enter `^Ec?' for help]
318 23:03:32.107953
319 23:03:32.108492
320 23:03:32.108857 F0: 102B 0000
321 23:03:32.109193
322 23:03:32.109513 F3: 1001 0000 [0200]
323 23:03:32.110906
324 23:03:32.111350 F3: 1001 0000
325 23:03:32.111703
326 23:03:32.112029 F7: 102D 0000
327 23:03:32.112341
328 23:03:32.114309 F1: 0000 0000
329 23:03:32.114777
330 23:03:32.115128 V0: 0000 0000 [0001]
331 23:03:32.115479
332 23:03:32.118061 00: 0007 8000
333 23:03:32.118663
334 23:03:32.119024 01: 0000 0000
335 23:03:32.119358
336 23:03:32.121309 BP: 0C00 0209 [0000]
337 23:03:32.121743
338 23:03:32.122087 G0: 1182 0000
339 23:03:32.122438
340 23:03:32.125225 EC: 0000 0021 [4000]
341 23:03:32.125770
342 23:03:32.126126 S7: 0000 0000 [0000]
343 23:03:32.126492
344 23:03:32.128306 CC: 0000 0000 [0001]
345 23:03:32.128740
346 23:03:32.129082 T0: 0000 0040 [010F]
347 23:03:32.129426
348 23:03:32.129740 Jump to BL
349 23:03:32.130047
350 23:03:32.154715
351 23:03:32.155213
352 23:03:32.155565
353 23:03:32.161904 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
354 23:03:32.165402 ARM64: Exception handlers installed.
355 23:03:32.168638 ARM64: Testing exception
356 23:03:32.172290 ARM64: Done test exception
357 23:03:32.178490 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
358 23:03:32.189546 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
359 23:03:32.195603 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
360 23:03:32.206033 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
361 23:03:32.212295 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
362 23:03:32.223032 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
363 23:03:32.233195 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
364 23:03:32.239855 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
365 23:03:32.258343 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
366 23:03:32.261882 WDT: Last reset was cold boot
367 23:03:32.264728 SPI1(PAD0) initialized at 2873684 Hz
368 23:03:32.267823 SPI5(PAD0) initialized at 992727 Hz
369 23:03:32.271626 VBOOT: Loading verstage.
370 23:03:32.277954 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
371 23:03:32.281788 FMAP: Found "FLASH" version 1.1 at 0x20000.
372 23:03:32.285160 FMAP: base = 0x0 size = 0x800000 #areas = 25
373 23:03:32.288048 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
374 23:03:32.296181 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
375 23:03:32.302174 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
376 23:03:32.313171 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
377 23:03:32.313604
378 23:03:32.313945
379 23:03:32.322731 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
380 23:03:32.326266 ARM64: Exception handlers installed.
381 23:03:32.329335 ARM64: Testing exception
382 23:03:32.329949 ARM64: Done test exception
383 23:03:32.336418 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
384 23:03:32.339493 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
385 23:03:32.353504 Probing TPM: . done!
386 23:03:32.353939 TPM ready after 0 ms
387 23:03:32.360827 Connected to device vid:did:rid of 1ae0:0028:00
388 23:03:32.368378 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
389 23:03:32.425031 Initialized TPM device CR50 revision 0
390 23:03:32.436483 tlcl_send_startup: Startup return code is 0
391 23:03:32.437002 TPM: setup succeeded
392 23:03:32.447857 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
393 23:03:32.456561 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
394 23:03:32.466688 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
395 23:03:32.476523 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
396 23:03:32.479942 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
397 23:03:32.486317 in-header: 03 07 00 00 08 00 00 00
398 23:03:32.489985 in-data: aa e4 47 04 13 02 00 00
399 23:03:32.493586 Chrome EC: UHEPI supported
400 23:03:32.501223 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
401 23:03:32.505477 in-header: 03 ad 00 00 08 00 00 00
402 23:03:32.508568 in-data: 00 20 20 08 00 00 00 00
403 23:03:32.509122 Phase 1
404 23:03:32.512295 FMAP: area GBB found @ 3f5000 (12032 bytes)
405 23:03:32.520070 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
406 23:03:32.523350 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
407 23:03:32.527539 Recovery requested (1009000e)
408 23:03:32.535865 TPM: Extending digest for VBOOT: boot mode into PCR 0
409 23:03:32.540990 tlcl_extend: response is 0
410 23:03:32.550562 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
411 23:03:32.556100 tlcl_extend: response is 0
412 23:03:32.563391 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
413 23:03:32.583676 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
414 23:03:32.591111 BS: bootblock times (exec / console): total (unknown) / 148 ms
415 23:03:32.591199
416 23:03:32.591268
417 23:03:32.600103 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
418 23:03:32.603720 ARM64: Exception handlers installed.
419 23:03:32.603806 ARM64: Testing exception
420 23:03:32.607039 ARM64: Done test exception
421 23:03:32.625376 pmic_efuse_setting: Set efuses in 11 msecs
422 23:03:32.634094 pmwrap_interface_init: Select PMIF_VLD_RDY
423 23:03:32.636982 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
424 23:03:32.644462 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
425 23:03:32.647535 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
426 23:03:32.650940 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
427 23:03:32.658069 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
428 23:03:32.662000 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
429 23:03:32.665516 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
430 23:03:32.672637 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
431 23:03:32.676325 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
432 23:03:32.679483 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
433 23:03:32.687249 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
434 23:03:32.690357 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
435 23:03:32.694189 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
436 23:03:32.700164 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
437 23:03:32.706980 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
438 23:03:32.710644 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
439 23:03:32.718140 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
440 23:03:32.722113 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
441 23:03:32.729949 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
442 23:03:32.736408 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
443 23:03:32.739772 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
444 23:03:32.747433 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
445 23:03:32.750423 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
446 23:03:32.756478 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
447 23:03:32.763236 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
448 23:03:32.766595 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
449 23:03:32.773712 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
450 23:03:32.777074 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
451 23:03:32.783892 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
452 23:03:32.786931 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
453 23:03:32.793655 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
454 23:03:32.797270 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
455 23:03:32.803797 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
456 23:03:32.807033 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
457 23:03:32.814184 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
458 23:03:32.817414 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
459 23:03:32.824429 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
460 23:03:32.827846 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
461 23:03:32.830752 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
462 23:03:32.838326 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
463 23:03:32.841620 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
464 23:03:32.845349 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
465 23:03:32.848814 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
466 23:03:32.855209 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
467 23:03:32.858831 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
468 23:03:32.861795 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
469 23:03:32.865369 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
470 23:03:32.872142 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
471 23:03:32.875649 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
472 23:03:32.878951 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
473 23:03:32.885287 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
474 23:03:32.892366 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
475 23:03:32.898765 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
476 23:03:32.905867 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
477 23:03:32.912028 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
478 23:03:32.921891 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
479 23:03:32.925356 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
480 23:03:32.932216 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
481 23:03:32.935099 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
482 23:03:32.941956 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x32
483 23:03:32.948540 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
484 23:03:32.952007 [RTC]rtc_osc_init,62: osc32con val = 0xde70
485 23:03:32.955425 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
486 23:03:32.966708 [RTC]rtc_get_frequency_meter,154: input=15, output=774
487 23:03:32.975925 [RTC]rtc_get_frequency_meter,154: input=23, output=956
488 23:03:32.985527 [RTC]rtc_get_frequency_meter,154: input=19, output=864
489 23:03:32.994780 [RTC]rtc_get_frequency_meter,154: input=17, output=818
490 23:03:33.005045 [RTC]rtc_get_frequency_meter,154: input=16, output=795
491 23:03:33.008573 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
492 23:03:33.012623 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
493 23:03:33.016113 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
494 23:03:33.020041 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
495 23:03:33.023447 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
496 23:03:33.027086 ADC[4]: Raw value=903245 ID=7
497 23:03:33.030293 ADC[3]: Raw value=213179 ID=1
498 23:03:33.034537 RAM Code: 0x71
499 23:03:33.037397 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
500 23:03:33.040455 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
501 23:03:33.050458 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
502 23:03:33.056968 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
503 23:03:33.060621 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
504 23:03:33.063933 in-header: 03 07 00 00 08 00 00 00
505 23:03:33.067053 in-data: aa e4 47 04 13 02 00 00
506 23:03:33.070573 Chrome EC: UHEPI supported
507 23:03:33.074250 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
508 23:03:33.079006 in-header: 03 ed 00 00 08 00 00 00
509 23:03:33.082840 in-data: 80 20 60 08 00 00 00 00
510 23:03:33.086778 MRC: failed to locate region type 0.
511 23:03:33.093958 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
512 23:03:33.097912 DRAM-K: Running full calibration
513 23:03:33.100949 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
514 23:03:33.103949 header.status = 0x0
515 23:03:33.107847 header.version = 0x6 (expected: 0x6)
516 23:03:33.110689 header.size = 0xd00 (expected: 0xd00)
517 23:03:33.111305 header.flags = 0x0
518 23:03:33.117389 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
519 23:03:33.136063 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
520 23:03:33.143051 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
521 23:03:33.146271 dram_init: ddr_geometry: 2
522 23:03:33.149513 [EMI] MDL number = 2
523 23:03:33.149990 [EMI] Get MDL freq = 0
524 23:03:33.152930 dram_init: ddr_type: 0
525 23:03:33.153440 is_discrete_lpddr4: 1
526 23:03:33.156226 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
527 23:03:33.156764
528 23:03:33.157236
529 23:03:33.159541 [Bian_co] ETT version 0.0.0.1
530 23:03:33.166619 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
531 23:03:33.167063
532 23:03:33.169496 dramc_set_vcore_voltage set vcore to 650000
533 23:03:33.169983 Read voltage for 800, 4
534 23:03:33.172831 Vio18 = 0
535 23:03:33.173265 Vcore = 650000
536 23:03:33.173614 Vdram = 0
537 23:03:33.176190 Vddq = 0
538 23:03:33.176649 Vmddr = 0
539 23:03:33.179639 dram_init: config_dvfs: 1
540 23:03:33.183456 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
541 23:03:33.189554 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
542 23:03:33.193063 [SwImpedanceCal] DRVP=9, DRVN=15, ODTN=9
543 23:03:33.196340 freq_region=0, Reg: DRVP=9, DRVN=15, ODTN=9
544 23:03:33.199496 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
545 23:03:33.202785 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
546 23:03:33.205842 MEM_TYPE=3, freq_sel=18
547 23:03:33.209312 sv_algorithm_assistance_LP4_1600
548 23:03:33.212772 ============ PULL DRAM RESETB DOWN ============
549 23:03:33.215878 ========== PULL DRAM RESETB DOWN end =========
550 23:03:33.222757 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
551 23:03:33.225839 ===================================
552 23:03:33.225943 LPDDR4 DRAM CONFIGURATION
553 23:03:33.229173 ===================================
554 23:03:33.232668 EX_ROW_EN[0] = 0x0
555 23:03:33.236373 EX_ROW_EN[1] = 0x0
556 23:03:33.236486 LP4Y_EN = 0x0
557 23:03:33.239350 WORK_FSP = 0x0
558 23:03:33.239460 WL = 0x2
559 23:03:33.242464 RL = 0x2
560 23:03:33.242565 BL = 0x2
561 23:03:33.246181 RPST = 0x0
562 23:03:33.246267 RD_PRE = 0x0
563 23:03:33.249590 WR_PRE = 0x1
564 23:03:33.249681 WR_PST = 0x0
565 23:03:33.253202 DBI_WR = 0x0
566 23:03:33.253300 DBI_RD = 0x0
567 23:03:33.256727 OTF = 0x1
568 23:03:33.259558 ===================================
569 23:03:33.262965 ===================================
570 23:03:33.263086 ANA top config
571 23:03:33.266711 ===================================
572 23:03:33.269727 DLL_ASYNC_EN = 0
573 23:03:33.272955 ALL_SLAVE_EN = 1
574 23:03:33.273137 NEW_RANK_MODE = 1
575 23:03:33.276726 DLL_IDLE_MODE = 1
576 23:03:33.280047 LP45_APHY_COMB_EN = 1
577 23:03:33.283302 TX_ODT_DIS = 1
578 23:03:33.283483 NEW_8X_MODE = 1
579 23:03:33.286446 ===================================
580 23:03:33.290190 ===================================
581 23:03:33.293149 data_rate = 1600
582 23:03:33.296681 CKR = 1
583 23:03:33.299645 DQ_P2S_RATIO = 8
584 23:03:33.303483 ===================================
585 23:03:33.306749 CA_P2S_RATIO = 8
586 23:03:33.310426 DQ_CA_OPEN = 0
587 23:03:33.310684 DQ_SEMI_OPEN = 0
588 23:03:33.313398 CA_SEMI_OPEN = 0
589 23:03:33.316403 CA_FULL_RATE = 0
590 23:03:33.320506 DQ_CKDIV4_EN = 1
591 23:03:33.324531 CA_CKDIV4_EN = 1
592 23:03:33.327303 CA_PREDIV_EN = 0
593 23:03:33.327552 PH8_DLY = 0
594 23:03:33.331019 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
595 23:03:33.334284 DQ_AAMCK_DIV = 4
596 23:03:33.338087 CA_AAMCK_DIV = 4
597 23:03:33.338441 CA_ADMCK_DIV = 4
598 23:03:33.342128 DQ_TRACK_CA_EN = 0
599 23:03:33.346231 CA_PICK = 800
600 23:03:33.349460 CA_MCKIO = 800
601 23:03:33.349711 MCKIO_SEMI = 0
602 23:03:33.352734 PLL_FREQ = 3068
603 23:03:33.356423 DQ_UI_PI_RATIO = 32
604 23:03:33.359987 CA_UI_PI_RATIO = 0
605 23:03:33.363513 ===================================
606 23:03:33.367037 ===================================
607 23:03:33.367300 memory_type:LPDDR4
608 23:03:33.371136 GP_NUM : 10
609 23:03:33.371416 SRAM_EN : 1
610 23:03:33.374559 MD32_EN : 0
611 23:03:33.378007 ===================================
612 23:03:33.378095 [ANA_INIT] >>>>>>>>>>>>>>
613 23:03:33.382078 <<<<<< [CONFIGURE PHASE]: ANA_TX
614 23:03:33.385561 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
615 23:03:33.389886 ===================================
616 23:03:33.393217 data_rate = 1600,PCW = 0X7600
617 23:03:33.396509 ===================================
618 23:03:33.400437 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
619 23:03:33.404447 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
620 23:03:33.411209 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
621 23:03:33.415179 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
622 23:03:33.418789 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
623 23:03:33.422696 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
624 23:03:33.422888 [ANA_INIT] flow start
625 23:03:33.426533 [ANA_INIT] PLL >>>>>>>>
626 23:03:33.426719 [ANA_INIT] PLL <<<<<<<<
627 23:03:33.429942 [ANA_INIT] MIDPI >>>>>>>>
628 23:03:33.433898 [ANA_INIT] MIDPI <<<<<<<<
629 23:03:33.434075 [ANA_INIT] DLL >>>>>>>>
630 23:03:33.437844 [ANA_INIT] flow end
631 23:03:33.441602 ============ LP4 DIFF to SE enter ============
632 23:03:33.445478 ============ LP4 DIFF to SE exit ============
633 23:03:33.449055 [ANA_INIT] <<<<<<<<<<<<<
634 23:03:33.449165 [Flow] Enable top DCM control >>>>>
635 23:03:33.452711 [Flow] Enable top DCM control <<<<<
636 23:03:33.455984 Enable DLL master slave shuffle
637 23:03:33.463092 ==============================================================
638 23:03:33.463201 Gating Mode config
639 23:03:33.470761 ==============================================================
640 23:03:33.470846 Config description:
641 23:03:33.482144 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
642 23:03:33.489726 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
643 23:03:33.493313 SELPH_MODE 0: By rank 1: By Phase
644 23:03:33.497243 ==============================================================
645 23:03:33.500857 GAT_TRACK_EN = 1
646 23:03:33.504594 RX_GATING_MODE = 2
647 23:03:33.508324 RX_GATING_TRACK_MODE = 2
648 23:03:33.511676 SELPH_MODE = 1
649 23:03:33.511868 PICG_EARLY_EN = 1
650 23:03:33.515595 VALID_LAT_VALUE = 1
651 23:03:33.523346 ==============================================================
652 23:03:33.527283 Enter into Gating configuration >>>>
653 23:03:33.527637 Exit from Gating configuration <<<<
654 23:03:33.530850 Enter into DVFS_PRE_config >>>>>
655 23:03:33.542341 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
656 23:03:33.546308 Exit from DVFS_PRE_config <<<<<
657 23:03:33.549614 Enter into PICG configuration >>>>
658 23:03:33.553343 Exit from PICG configuration <<<<
659 23:03:33.553765 [RX_INPUT] configuration >>>>>
660 23:03:33.556976 [RX_INPUT] configuration <<<<<
661 23:03:33.564615 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
662 23:03:33.568170 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
663 23:03:33.575743 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
664 23:03:33.579448 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
665 23:03:33.586898 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
666 23:03:33.594621 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
667 23:03:33.598362 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
668 23:03:33.601806 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
669 23:03:33.605949 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
670 23:03:33.609495 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
671 23:03:33.613396 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
672 23:03:33.616762 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
673 23:03:33.620476 ===================================
674 23:03:33.624319 LPDDR4 DRAM CONFIGURATION
675 23:03:33.628087 ===================================
676 23:03:33.628615 EX_ROW_EN[0] = 0x0
677 23:03:33.631997 EX_ROW_EN[1] = 0x0
678 23:03:33.632431 LP4Y_EN = 0x0
679 23:03:33.635474 WORK_FSP = 0x0
680 23:03:33.635997 WL = 0x2
681 23:03:33.639096 RL = 0x2
682 23:03:33.639529 BL = 0x2
683 23:03:33.643039 RPST = 0x0
684 23:03:33.643592 RD_PRE = 0x0
685 23:03:33.646737 WR_PRE = 0x1
686 23:03:33.647169 WR_PST = 0x0
687 23:03:33.649973 DBI_WR = 0x0
688 23:03:33.650454 DBI_RD = 0x0
689 23:03:33.653969 OTF = 0x1
690 23:03:33.654478 ===================================
691 23:03:33.657751 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
692 23:03:33.661322 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
693 23:03:33.669077 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
694 23:03:33.672448 ===================================
695 23:03:33.672885 LPDDR4 DRAM CONFIGURATION
696 23:03:33.675912 ===================================
697 23:03:33.679316 EX_ROW_EN[0] = 0x10
698 23:03:33.679849 EX_ROW_EN[1] = 0x0
699 23:03:33.682434 LP4Y_EN = 0x0
700 23:03:33.685643 WORK_FSP = 0x0
701 23:03:33.686133 WL = 0x2
702 23:03:33.689153 RL = 0x2
703 23:03:33.689680 BL = 0x2
704 23:03:33.692192 RPST = 0x0
705 23:03:33.692626 RD_PRE = 0x0
706 23:03:33.695918 WR_PRE = 0x1
707 23:03:33.696466 WR_PST = 0x0
708 23:03:33.699276 DBI_WR = 0x0
709 23:03:33.699715 DBI_RD = 0x0
710 23:03:33.702276 OTF = 0x1
711 23:03:33.705690 ===================================
712 23:03:33.709414 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
713 23:03:33.715172 nWR fixed to 40
714 23:03:33.717941 [ModeRegInit_LP4] CH0 RK0
715 23:03:33.718376 [ModeRegInit_LP4] CH0 RK1
716 23:03:33.721295 [ModeRegInit_LP4] CH1 RK0
717 23:03:33.725160 [ModeRegInit_LP4] CH1 RK1
718 23:03:33.725696 match AC timing 13
719 23:03:33.731322 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
720 23:03:33.734914 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
721 23:03:33.738551 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
722 23:03:33.744574 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
723 23:03:33.748109 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
724 23:03:33.748664 [EMI DOE] emi_dcm 0
725 23:03:33.754916 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
726 23:03:33.755448 ==
727 23:03:33.758566 Dram Type= 6, Freq= 0, CH_0, rank 0
728 23:03:33.761704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
729 23:03:33.762235 ==
730 23:03:33.768422 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
731 23:03:33.771418 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
732 23:03:33.782195 [CA 0] Center 38 (7~69) winsize 63
733 23:03:33.785509 [CA 1] Center 38 (7~69) winsize 63
734 23:03:33.789150 [CA 2] Center 35 (5~66) winsize 62
735 23:03:33.792209 [CA 3] Center 35 (5~66) winsize 62
736 23:03:33.795678 [CA 4] Center 34 (4~65) winsize 62
737 23:03:33.799056 [CA 5] Center 33 (3~64) winsize 62
738 23:03:33.799532
739 23:03:33.802632 [CmdBusTrainingLP45] Vref(ca) range 1: 34
740 23:03:33.803201
741 23:03:33.806087 [CATrainingPosCal] consider 1 rank data
742 23:03:33.809156 u2DelayCellTimex100 = 270/100 ps
743 23:03:33.812429 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
744 23:03:33.815969 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
745 23:03:33.822009 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
746 23:03:33.825712 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
747 23:03:33.828708 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
748 23:03:33.832842 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
749 23:03:33.833409
750 23:03:33.835838 CA PerBit enable=1, Macro0, CA PI delay=33
751 23:03:33.836408
752 23:03:33.838976 [CBTSetCACLKResult] CA Dly = 33
753 23:03:33.839474 CS Dly: 6 (0~37)
754 23:03:33.842486 ==
755 23:03:33.843053 Dram Type= 6, Freq= 0, CH_0, rank 1
756 23:03:33.848902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
757 23:03:33.849477 ==
758 23:03:33.851976 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
759 23:03:33.858934 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
760 23:03:33.868705 [CA 0] Center 38 (7~69) winsize 63
761 23:03:33.872247 [CA 1] Center 38 (7~69) winsize 63
762 23:03:33.875379 [CA 2] Center 36 (6~67) winsize 62
763 23:03:33.878832 [CA 3] Center 35 (5~66) winsize 62
764 23:03:33.882279 [CA 4] Center 35 (4~66) winsize 63
765 23:03:33.885561 [CA 5] Center 34 (4~65) winsize 62
766 23:03:33.886152
767 23:03:33.888696 [CmdBusTrainingLP45] Vref(ca) range 1: 34
768 23:03:33.889274
769 23:03:33.891799 [CATrainingPosCal] consider 2 rank data
770 23:03:33.895710 u2DelayCellTimex100 = 270/100 ps
771 23:03:33.898875 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
772 23:03:33.901779 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
773 23:03:33.908551 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
774 23:03:33.911872 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
775 23:03:33.915662 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
776 23:03:33.918609 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
777 23:03:33.919141
778 23:03:33.922166 CA PerBit enable=1, Macro0, CA PI delay=34
779 23:03:33.922694
780 23:03:33.925454 [CBTSetCACLKResult] CA Dly = 34
781 23:03:33.925932 CS Dly: 6 (0~38)
782 23:03:33.926318
783 23:03:33.928566 ----->DramcWriteLeveling(PI) begin...
784 23:03:33.932060 ==
785 23:03:33.935422 Dram Type= 6, Freq= 0, CH_0, rank 0
786 23:03:33.938831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
787 23:03:33.939474 ==
788 23:03:33.942188 Write leveling (Byte 0): 29 => 29
789 23:03:33.945383 Write leveling (Byte 1): 28 => 28
790 23:03:33.949231 DramcWriteLeveling(PI) end<-----
791 23:03:33.949820
792 23:03:33.950202 ==
793 23:03:33.952541 Dram Type= 6, Freq= 0, CH_0, rank 0
794 23:03:33.956184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
795 23:03:33.956771 ==
796 23:03:33.958769 [Gating] SW mode calibration
797 23:03:33.966132 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
798 23:03:33.968665 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
799 23:03:33.975990 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
800 23:03:33.980120 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
801 23:03:33.983549 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
802 23:03:33.986953 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 23:03:33.990461 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 23:03:33.997363 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 23:03:34.000828 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 23:03:34.004616 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 23:03:34.010906 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 23:03:34.014524 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 23:03:34.017525 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 23:03:34.024581 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 23:03:34.027351 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 23:03:34.031169 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 23:03:34.037839 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
814 23:03:34.041095 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
815 23:03:34.044305 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
816 23:03:34.048026 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
817 23:03:34.054556 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
818 23:03:34.057476 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 23:03:34.061143 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 23:03:34.067994 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 23:03:34.071345 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 23:03:34.074257 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 23:03:34.081069 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 23:03:34.084758 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 23:03:34.087933 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
826 23:03:34.094627 0 9 12 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
827 23:03:34.098067 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
828 23:03:34.101736 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
829 23:03:34.107932 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
830 23:03:34.111370 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
831 23:03:34.114802 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
832 23:03:34.118506 0 10 4 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0)
833 23:03:34.124855 0 10 8 | B1->B0 | 3232 2323 | 1 0 | (0 0) (0 0)
834 23:03:34.128268 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
835 23:03:34.131104 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
836 23:03:34.137929 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
837 23:03:34.141409 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
838 23:03:34.144808 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 23:03:34.151264 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 23:03:34.155130 0 11 4 | B1->B0 | 2323 3535 | 0 0 | (0 0) (1 1)
841 23:03:34.158127 0 11 8 | B1->B0 | 2929 4646 | 1 0 | (0 0) (0 0)
842 23:03:34.165069 0 11 12 | B1->B0 | 3e3e 4646 | 1 0 | (0 0) (0 0)
843 23:03:34.167753 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
844 23:03:34.171408 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
845 23:03:34.178101 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
846 23:03:34.181598 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
847 23:03:34.184721 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
848 23:03:34.191291 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
849 23:03:34.194903 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
850 23:03:34.197966 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 23:03:34.204667 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 23:03:34.208289 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
853 23:03:34.211429 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
854 23:03:34.214630 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
855 23:03:34.221731 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
856 23:03:34.224701 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
857 23:03:34.228626 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
858 23:03:34.234806 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
859 23:03:34.238479 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
860 23:03:34.241489 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
861 23:03:34.248431 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
862 23:03:34.251516 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
863 23:03:34.254871 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
864 23:03:34.262108 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
865 23:03:34.264816 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
866 23:03:34.268115 Total UI for P1: 0, mck2ui 16
867 23:03:34.271417 best dqsien dly found for B0: ( 0, 14, 4)
868 23:03:34.275035 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
869 23:03:34.278470 Total UI for P1: 0, mck2ui 16
870 23:03:34.281949 best dqsien dly found for B1: ( 0, 14, 8)
871 23:03:34.285379 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
872 23:03:34.288949 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
873 23:03:34.289527
874 23:03:34.291455 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
875 23:03:34.295190 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
876 23:03:34.298485 [Gating] SW calibration Done
877 23:03:34.298965 ==
878 23:03:34.302066 Dram Type= 6, Freq= 0, CH_0, rank 0
879 23:03:34.305546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
880 23:03:34.308890 ==
881 23:03:34.309468 RX Vref Scan: 0
882 23:03:34.309851
883 23:03:34.311708 RX Vref 0 -> 0, step: 1
884 23:03:34.312189
885 23:03:34.315558 RX Delay -130 -> 252, step: 16
886 23:03:34.318622 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
887 23:03:34.321927 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
888 23:03:34.325225 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
889 23:03:34.328678 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
890 23:03:34.335435 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
891 23:03:34.338530 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
892 23:03:34.342512 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
893 23:03:34.345285 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
894 23:03:34.349011 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
895 23:03:34.355301 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
896 23:03:34.358766 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
897 23:03:34.361973 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
898 23:03:34.365510 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
899 23:03:34.369211 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
900 23:03:34.375733 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
901 23:03:34.379271 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
902 23:03:34.379848 ==
903 23:03:34.382291 Dram Type= 6, Freq= 0, CH_0, rank 0
904 23:03:34.385610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
905 23:03:34.386196 ==
906 23:03:34.386646 DQS Delay:
907 23:03:34.388872 DQS0 = 0, DQS1 = 0
908 23:03:34.389453 DQM Delay:
909 23:03:34.392344 DQM0 = 89, DQM1 = 81
910 23:03:34.392923 DQ Delay:
911 23:03:34.395424 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
912 23:03:34.398841 DQ4 =85, DQ5 =77, DQ6 =101, DQ7 =101
913 23:03:34.402819 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
914 23:03:34.405663 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =93
915 23:03:34.406244
916 23:03:34.406712
917 23:03:34.407080 ==
918 23:03:34.408934 Dram Type= 6, Freq= 0, CH_0, rank 0
919 23:03:34.412208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 23:03:34.415611 ==
921 23:03:34.416188
922 23:03:34.416572
923 23:03:34.416924 TX Vref Scan disable
924 23:03:34.418922 == TX Byte 0 ==
925 23:03:34.422059 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
926 23:03:34.425581 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
927 23:03:34.429158 == TX Byte 1 ==
928 23:03:34.432310 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
929 23:03:34.435769 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
930 23:03:34.439316 ==
931 23:03:34.439899 Dram Type= 6, Freq= 0, CH_0, rank 0
932 23:03:34.445545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
933 23:03:34.446115 ==
934 23:03:34.458096 TX Vref=22, minBit 8, minWin=26, winSum=438
935 23:03:34.461144 TX Vref=24, minBit 6, minWin=27, winSum=440
936 23:03:34.464757 TX Vref=26, minBit 5, minWin=27, winSum=446
937 23:03:34.467629 TX Vref=28, minBit 6, minWin=27, winSum=451
938 23:03:34.471332 TX Vref=30, minBit 9, minWin=27, winSum=454
939 23:03:34.474716 TX Vref=32, minBit 9, minWin=27, winSum=452
940 23:03:34.481252 [TxChooseVref] Worse bit 9, Min win 27, Win sum 454, Final Vref 30
941 23:03:34.481835
942 23:03:34.484780 Final TX Range 1 Vref 30
943 23:03:34.485361
944 23:03:34.485745 ==
945 23:03:34.487664 Dram Type= 6, Freq= 0, CH_0, rank 0
946 23:03:34.491833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
947 23:03:34.492428 ==
948 23:03:34.492820
949 23:03:34.493171
950 23:03:34.494260 TX Vref Scan disable
951 23:03:34.497971 == TX Byte 0 ==
952 23:03:34.501239 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
953 23:03:34.505068 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
954 23:03:34.508056 == TX Byte 1 ==
955 23:03:34.511457 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
956 23:03:34.515125 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
957 23:03:34.515706
958 23:03:34.518083 [DATLAT]
959 23:03:34.518699 Freq=800, CH0 RK0
960 23:03:34.519088
961 23:03:34.521280 DATLAT Default: 0xa
962 23:03:34.521897 0, 0xFFFF, sum = 0
963 23:03:34.524833 1, 0xFFFF, sum = 0
964 23:03:34.525418 2, 0xFFFF, sum = 0
965 23:03:34.528077 3, 0xFFFF, sum = 0
966 23:03:34.528580 4, 0xFFFF, sum = 0
967 23:03:34.531204 5, 0xFFFF, sum = 0
968 23:03:34.531761 6, 0xFFFF, sum = 0
969 23:03:34.534550 7, 0xFFFF, sum = 0
970 23:03:34.535035 8, 0xFFFF, sum = 0
971 23:03:34.538159 9, 0x0, sum = 1
972 23:03:34.538704 10, 0x0, sum = 2
973 23:03:34.541600 11, 0x0, sum = 3
974 23:03:34.542218 12, 0x0, sum = 4
975 23:03:34.544489 best_step = 10
976 23:03:34.544965
977 23:03:34.545341 ==
978 23:03:34.548436 Dram Type= 6, Freq= 0, CH_0, rank 0
979 23:03:34.551224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
980 23:03:34.551710 ==
981 23:03:34.555069 RX Vref Scan: 1
982 23:03:34.555640
983 23:03:34.556026 Set Vref Range= 32 -> 127
984 23:03:34.556382
985 23:03:34.558112 RX Vref 32 -> 127, step: 1
986 23:03:34.558729
987 23:03:34.561307 RX Delay -79 -> 252, step: 8
988 23:03:34.561786
989 23:03:34.564607 Set Vref, RX VrefLevel [Byte0]: 32
990 23:03:34.567809 [Byte1]: 32
991 23:03:34.568287
992 23:03:34.571395 Set Vref, RX VrefLevel [Byte0]: 33
993 23:03:34.574977 [Byte1]: 33
994 23:03:34.575456
995 23:03:34.578230 Set Vref, RX VrefLevel [Byte0]: 34
996 23:03:34.581699 [Byte1]: 34
997 23:03:34.585559
998 23:03:34.586087 Set Vref, RX VrefLevel [Byte0]: 35
999 23:03:34.589133 [Byte1]: 35
1000 23:03:34.593059
1001 23:03:34.593586 Set Vref, RX VrefLevel [Byte0]: 36
1002 23:03:34.596397 [Byte1]: 36
1003 23:03:34.600125
1004 23:03:34.600583 Set Vref, RX VrefLevel [Byte0]: 37
1005 23:03:34.603907 [Byte1]: 37
1006 23:03:34.607974
1007 23:03:34.608513 Set Vref, RX VrefLevel [Byte0]: 38
1008 23:03:34.611769 [Byte1]: 38
1009 23:03:34.615542
1010 23:03:34.615984 Set Vref, RX VrefLevel [Byte0]: 39
1011 23:03:34.618895 [Byte1]: 39
1012 23:03:34.623173
1013 23:03:34.623601 Set Vref, RX VrefLevel [Byte0]: 40
1014 23:03:34.626216 [Byte1]: 40
1015 23:03:34.630868
1016 23:03:34.631396 Set Vref, RX VrefLevel [Byte0]: 41
1017 23:03:34.633736 [Byte1]: 41
1018 23:03:34.638466
1019 23:03:34.639002 Set Vref, RX VrefLevel [Byte0]: 42
1020 23:03:34.641715 [Byte1]: 42
1021 23:03:34.645694
1022 23:03:34.646183 Set Vref, RX VrefLevel [Byte0]: 43
1023 23:03:34.649205 [Byte1]: 43
1024 23:03:34.653832
1025 23:03:34.654282 Set Vref, RX VrefLevel [Byte0]: 44
1026 23:03:34.657286 [Byte1]: 44
1027 23:03:34.661110
1028 23:03:34.661538 Set Vref, RX VrefLevel [Byte0]: 45
1029 23:03:34.664683 [Byte1]: 45
1030 23:03:34.669186
1031 23:03:34.669613 Set Vref, RX VrefLevel [Byte0]: 46
1032 23:03:34.672421 [Byte1]: 46
1033 23:03:34.676068
1034 23:03:34.676655 Set Vref, RX VrefLevel [Byte0]: 47
1035 23:03:34.679054 [Byte1]: 47
1036 23:03:34.683216
1037 23:03:34.683642 Set Vref, RX VrefLevel [Byte0]: 48
1038 23:03:34.686965 [Byte1]: 48
1039 23:03:34.691162
1040 23:03:34.691703 Set Vref, RX VrefLevel [Byte0]: 49
1041 23:03:34.694420 [Byte1]: 49
1042 23:03:34.698834
1043 23:03:34.699377 Set Vref, RX VrefLevel [Byte0]: 50
1044 23:03:34.701780 [Byte1]: 50
1045 23:03:34.706089
1046 23:03:34.706676 Set Vref, RX VrefLevel [Byte0]: 51
1047 23:03:34.709203 [Byte1]: 51
1048 23:03:34.713842
1049 23:03:34.714358 Set Vref, RX VrefLevel [Byte0]: 52
1050 23:03:34.717229 [Byte1]: 52
1051 23:03:34.721293
1052 23:03:34.721828 Set Vref, RX VrefLevel [Byte0]: 53
1053 23:03:34.724312 [Byte1]: 53
1054 23:03:34.729116
1055 23:03:34.729635 Set Vref, RX VrefLevel [Byte0]: 54
1056 23:03:34.731918 [Byte1]: 54
1057 23:03:34.736230
1058 23:03:34.736772 Set Vref, RX VrefLevel [Byte0]: 55
1059 23:03:34.739226 [Byte1]: 55
1060 23:03:34.743799
1061 23:03:34.744226 Set Vref, RX VrefLevel [Byte0]: 56
1062 23:03:34.747077 [Byte1]: 56
1063 23:03:34.751203
1064 23:03:34.751750 Set Vref, RX VrefLevel [Byte0]: 57
1065 23:03:34.754683 [Byte1]: 57
1066 23:03:34.759313
1067 23:03:34.759853 Set Vref, RX VrefLevel [Byte0]: 58
1068 23:03:34.762414 [Byte1]: 58
1069 23:03:34.766790
1070 23:03:34.767348 Set Vref, RX VrefLevel [Byte0]: 59
1071 23:03:34.769756 [Byte1]: 59
1072 23:03:34.774426
1073 23:03:34.774997 Set Vref, RX VrefLevel [Byte0]: 60
1074 23:03:34.777153 [Byte1]: 60
1075 23:03:34.781773
1076 23:03:34.782340 Set Vref, RX VrefLevel [Byte0]: 61
1077 23:03:34.785099 [Byte1]: 61
1078 23:03:34.789502
1079 23:03:34.790060 Set Vref, RX VrefLevel [Byte0]: 62
1080 23:03:34.792948 [Byte1]: 62
1081 23:03:34.796978
1082 23:03:34.797538 Set Vref, RX VrefLevel [Byte0]: 63
1083 23:03:34.799825 [Byte1]: 63
1084 23:03:34.804261
1085 23:03:34.804821 Set Vref, RX VrefLevel [Byte0]: 64
1086 23:03:34.807518 [Byte1]: 64
1087 23:03:34.811705
1088 23:03:34.812258 Set Vref, RX VrefLevel [Byte0]: 65
1089 23:03:34.815269 [Byte1]: 65
1090 23:03:34.819620
1091 23:03:34.820180 Set Vref, RX VrefLevel [Byte0]: 66
1092 23:03:34.822348 [Byte1]: 66
1093 23:03:34.827084
1094 23:03:34.827552 Set Vref, RX VrefLevel [Byte0]: 67
1095 23:03:34.830430 [Byte1]: 67
1096 23:03:34.834211
1097 23:03:34.834725 Set Vref, RX VrefLevel [Byte0]: 68
1098 23:03:34.837690 [Byte1]: 68
1099 23:03:34.841918
1100 23:03:34.842562 Set Vref, RX VrefLevel [Byte0]: 69
1101 23:03:34.845210 [Byte1]: 69
1102 23:03:34.849290
1103 23:03:34.849779 Set Vref, RX VrefLevel [Byte0]: 70
1104 23:03:34.852762 [Byte1]: 70
1105 23:03:34.857033
1106 23:03:34.857598 Set Vref, RX VrefLevel [Byte0]: 71
1107 23:03:34.860592 [Byte1]: 71
1108 23:03:34.864713
1109 23:03:34.865276 Set Vref, RX VrefLevel [Byte0]: 72
1110 23:03:34.868028 [Byte1]: 72
1111 23:03:34.872414
1112 23:03:34.872979 Set Vref, RX VrefLevel [Byte0]: 73
1113 23:03:34.875136 [Byte1]: 73
1114 23:03:34.880044
1115 23:03:34.880603 Set Vref, RX VrefLevel [Byte0]: 74
1116 23:03:34.883515 [Byte1]: 74
1117 23:03:34.887423
1118 23:03:34.888121 Set Vref, RX VrefLevel [Byte0]: 75
1119 23:03:34.890428 [Byte1]: 75
1120 23:03:34.894840
1121 23:03:34.895397 Set Vref, RX VrefLevel [Byte0]: 76
1122 23:03:34.898466 [Byte1]: 76
1123 23:03:34.902372
1124 23:03:34.903004 Set Vref, RX VrefLevel [Byte0]: 77
1125 23:03:34.905750 [Byte1]: 77
1126 23:03:34.910176
1127 23:03:34.910785 Final RX Vref Byte 0 = 61 to rank0
1128 23:03:34.913393 Final RX Vref Byte 1 = 60 to rank0
1129 23:03:34.916774 Final RX Vref Byte 0 = 61 to rank1
1130 23:03:34.919904 Final RX Vref Byte 1 = 60 to rank1==
1131 23:03:34.923208 Dram Type= 6, Freq= 0, CH_0, rank 0
1132 23:03:34.926528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1133 23:03:34.930024 ==
1134 23:03:34.930822 DQS Delay:
1135 23:03:34.931222 DQS0 = 0, DQS1 = 0
1136 23:03:34.933523 DQM Delay:
1137 23:03:34.933993 DQM0 = 93, DQM1 = 83
1138 23:03:34.936752 DQ Delay:
1139 23:03:34.939816 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1140 23:03:34.943321 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1141 23:03:34.946501 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =80
1142 23:03:34.950368 DQ12 =88, DQ13 =88, DQ14 =92, DQ15 =92
1143 23:03:34.950981
1144 23:03:34.951365
1145 23:03:34.956698 [DQSOSCAuto] RK0, (LSB)MR18= 0x3f3b, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
1146 23:03:34.960376 CH0 RK0: MR19=606, MR18=3F3B
1147 23:03:34.966798 CH0_RK0: MR19=0x606, MR18=0x3F3B, DQSOSC=393, MR23=63, INC=95, DEC=63
1148 23:03:34.967359
1149 23:03:34.969945 ----->DramcWriteLeveling(PI) begin...
1150 23:03:34.970553 ==
1151 23:03:34.973797 Dram Type= 6, Freq= 0, CH_0, rank 1
1152 23:03:34.976491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1153 23:03:34.977056 ==
1154 23:03:34.979842 Write leveling (Byte 0): 30 => 30
1155 23:03:34.983573 Write leveling (Byte 1): 28 => 28
1156 23:03:34.986550 DramcWriteLeveling(PI) end<-----
1157 23:03:34.987112
1158 23:03:34.987492 ==
1159 23:03:34.990372 Dram Type= 6, Freq= 0, CH_0, rank 1
1160 23:03:34.993450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1161 23:03:34.994014 ==
1162 23:03:34.996668 [Gating] SW mode calibration
1163 23:03:35.003407 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1164 23:03:35.010076 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1165 23:03:35.013777 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1166 23:03:35.016602 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1167 23:03:35.023189 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 23:03:35.026758 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 23:03:35.029998 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 23:03:35.077864 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 23:03:35.078485 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 23:03:35.079221 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 23:03:35.079605 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 23:03:35.079959 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 23:03:35.080294 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 23:03:35.080625 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 23:03:35.080948 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 23:03:35.081268 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 23:03:35.081584 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 23:03:35.121286 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 23:03:35.121845 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 23:03:35.122606 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1183 23:03:35.123024 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 23:03:35.123477 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 23:03:35.123837 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 23:03:35.124220 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 23:03:35.124568 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 23:03:35.124977 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 23:03:35.125314 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 23:03:35.125637 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 23:03:35.147304 0 9 8 | B1->B0 | 2d2d 3333 | 0 0 | (0 0) (0 0)
1192 23:03:35.147906 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1193 23:03:35.148300 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1194 23:03:35.148999 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1195 23:03:35.149368 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1196 23:03:35.150869 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1197 23:03:35.154498 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1198 23:03:35.157837 0 10 4 | B1->B0 | 3131 2f2f | 1 0 | (1 0) (0 1)
1199 23:03:35.164785 0 10 8 | B1->B0 | 2f2f 2525 | 1 0 | (1 1) (0 0)
1200 23:03:35.167567 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 23:03:35.171056 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 23:03:35.174758 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 23:03:35.181338 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 23:03:35.184690 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 23:03:35.187669 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 23:03:35.194672 0 11 4 | B1->B0 | 2626 3030 | 0 1 | (0 0) (0 0)
1207 23:03:35.198006 0 11 8 | B1->B0 | 3838 4545 | 0 0 | (0 0) (0 0)
1208 23:03:35.201089 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1209 23:03:35.208109 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1210 23:03:35.211263 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1211 23:03:35.214766 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1212 23:03:35.222138 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1213 23:03:35.225131 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1214 23:03:35.229045 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1215 23:03:35.232875 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 23:03:35.236465 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 23:03:35.243490 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 23:03:35.246443 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 23:03:35.249974 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 23:03:35.253990 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 23:03:35.260918 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 23:03:35.264515 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1223 23:03:35.267360 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1224 23:03:35.273974 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1225 23:03:35.277584 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1226 23:03:35.280960 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1227 23:03:35.287820 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1228 23:03:35.290806 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1229 23:03:35.294087 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1230 23:03:35.297803 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1231 23:03:35.304375 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1232 23:03:35.307414 Total UI for P1: 0, mck2ui 16
1233 23:03:35.311213 best dqsien dly found for B0: ( 0, 14, 4)
1234 23:03:35.314565 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1235 23:03:35.317702 Total UI for P1: 0, mck2ui 16
1236 23:03:35.320838 best dqsien dly found for B1: ( 0, 14, 6)
1237 23:03:35.324591 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1238 23:03:35.327530 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1239 23:03:35.328014
1240 23:03:35.331212 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1241 23:03:35.334164 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1242 23:03:35.337684 [Gating] SW calibration Done
1243 23:03:35.338265 ==
1244 23:03:35.340935 Dram Type= 6, Freq= 0, CH_0, rank 1
1245 23:03:35.344278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1246 23:03:35.344758 ==
1247 23:03:35.347446 RX Vref Scan: 0
1248 23:03:35.347978
1249 23:03:35.350932 RX Vref 0 -> 0, step: 1
1250 23:03:35.351407
1251 23:03:35.351876 RX Delay -130 -> 252, step: 16
1252 23:03:35.358368 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1253 23:03:35.361375 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1254 23:03:35.364623 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1255 23:03:35.367719 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1256 23:03:35.371170 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1257 23:03:35.377596 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1258 23:03:35.381262 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1259 23:03:35.384323 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1260 23:03:35.388440 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1261 23:03:35.391522 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
1262 23:03:35.398541 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1263 23:03:35.401537 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1264 23:03:35.404419 iDelay=222, Bit 12, Center 85 (-18 ~ 189) 208
1265 23:03:35.407749 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1266 23:03:35.411190 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1267 23:03:35.418130 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
1268 23:03:35.418708 ==
1269 23:03:35.421748 Dram Type= 6, Freq= 0, CH_0, rank 1
1270 23:03:35.424740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1271 23:03:35.425301 ==
1272 23:03:35.425840 DQS Delay:
1273 23:03:35.428380 DQS0 = 0, DQS1 = 0
1274 23:03:35.428842 DQM Delay:
1275 23:03:35.431744 DQM0 = 91, DQM1 = 84
1276 23:03:35.432313 DQ Delay:
1277 23:03:35.434510 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =85
1278 23:03:35.438439 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =101
1279 23:03:35.441152 DQ8 =77, DQ9 =69, DQ10 =85, DQ11 =85
1280 23:03:35.444907 DQ12 =85, DQ13 =93, DQ14 =93, DQ15 =85
1281 23:03:35.445493
1282 23:03:35.445982
1283 23:03:35.446635 ==
1284 23:03:35.447821 Dram Type= 6, Freq= 0, CH_0, rank 1
1285 23:03:35.451600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1286 23:03:35.452105 ==
1287 23:03:35.452483
1288 23:03:35.454865
1289 23:03:35.455328 TX Vref Scan disable
1290 23:03:35.458202 == TX Byte 0 ==
1291 23:03:35.461253 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1292 23:03:35.464712 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1293 23:03:35.467783 == TX Byte 1 ==
1294 23:03:35.471245 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1295 23:03:35.474560 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1296 23:03:35.475153 ==
1297 23:03:35.478116 Dram Type= 6, Freq= 0, CH_0, rank 1
1298 23:03:35.484333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1299 23:03:35.484943 ==
1300 23:03:35.497005 TX Vref=22, minBit 8, minWin=27, winSum=446
1301 23:03:35.499905 TX Vref=24, minBit 3, minWin=27, winSum=447
1302 23:03:35.503272 TX Vref=26, minBit 8, minWin=27, winSum=451
1303 23:03:35.506415 TX Vref=28, minBit 8, minWin=27, winSum=454
1304 23:03:35.509762 TX Vref=30, minBit 4, minWin=28, winSum=455
1305 23:03:35.513569 TX Vref=32, minBit 8, minWin=27, winSum=457
1306 23:03:35.519975 [TxChooseVref] Worse bit 4, Min win 28, Win sum 455, Final Vref 30
1307 23:03:35.520421
1308 23:03:35.523147 Final TX Range 1 Vref 30
1309 23:03:35.523570
1310 23:03:35.523911 ==
1311 23:03:35.526571 Dram Type= 6, Freq= 0, CH_0, rank 1
1312 23:03:35.530009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1313 23:03:35.530659 ==
1314 23:03:35.531246
1315 23:03:35.531804
1316 23:03:35.532929 TX Vref Scan disable
1317 23:03:35.536496 == TX Byte 0 ==
1318 23:03:35.539711 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1319 23:03:35.543336 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1320 23:03:35.546705 == TX Byte 1 ==
1321 23:03:35.550380 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1322 23:03:35.553092 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1323 23:03:35.553445
1324 23:03:35.556138 [DATLAT]
1325 23:03:35.556218 Freq=800, CH0 RK1
1326 23:03:35.556282
1327 23:03:35.559535 DATLAT Default: 0xa
1328 23:03:35.559616 0, 0xFFFF, sum = 0
1329 23:03:35.563150 1, 0xFFFF, sum = 0
1330 23:03:35.563231 2, 0xFFFF, sum = 0
1331 23:03:35.566093 3, 0xFFFF, sum = 0
1332 23:03:35.566164 4, 0xFFFF, sum = 0
1333 23:03:35.569780 5, 0xFFFF, sum = 0
1334 23:03:35.569851 6, 0xFFFF, sum = 0
1335 23:03:35.572836 7, 0xFFFF, sum = 0
1336 23:03:35.572910 8, 0xFFFF, sum = 0
1337 23:03:35.575853 9, 0x0, sum = 1
1338 23:03:35.575924 10, 0x0, sum = 2
1339 23:03:35.579567 11, 0x0, sum = 3
1340 23:03:35.579645 12, 0x0, sum = 4
1341 23:03:35.583049 best_step = 10
1342 23:03:35.583116
1343 23:03:35.583180 ==
1344 23:03:35.586220 Dram Type= 6, Freq= 0, CH_0, rank 1
1345 23:03:35.589573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1346 23:03:35.589649 ==
1347 23:03:35.593041 RX Vref Scan: 0
1348 23:03:35.593110
1349 23:03:35.593170 RX Vref 0 -> 0, step: 1
1350 23:03:35.593236
1351 23:03:35.596402 RX Delay -79 -> 252, step: 8
1352 23:03:35.602913 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1353 23:03:35.606253 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1354 23:03:35.609479 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1355 23:03:35.612537 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1356 23:03:35.616083 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1357 23:03:35.622710 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1358 23:03:35.626571 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1359 23:03:35.629187 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1360 23:03:35.632765 iDelay=209, Bit 8, Center 76 (-23 ~ 176) 200
1361 23:03:35.636138 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1362 23:03:35.642855 iDelay=209, Bit 10, Center 80 (-23 ~ 184) 208
1363 23:03:35.646180 iDelay=209, Bit 11, Center 80 (-23 ~ 184) 208
1364 23:03:35.649384 iDelay=209, Bit 12, Center 88 (-15 ~ 192) 208
1365 23:03:35.652774 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1366 23:03:35.656154 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1367 23:03:35.662891 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1368 23:03:35.662971 ==
1369 23:03:35.666208 Dram Type= 6, Freq= 0, CH_0, rank 1
1370 23:03:35.669421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1371 23:03:35.669502 ==
1372 23:03:35.669565 DQS Delay:
1373 23:03:35.672656 DQS0 = 0, DQS1 = 0
1374 23:03:35.672735 DQM Delay:
1375 23:03:35.676412 DQM0 = 90, DQM1 = 83
1376 23:03:35.676492 DQ Delay:
1377 23:03:35.679621 DQ0 =88, DQ1 =92, DQ2 =88, DQ3 =84
1378 23:03:35.682999 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1379 23:03:35.686495 DQ8 =76, DQ9 =72, DQ10 =80, DQ11 =80
1380 23:03:35.689469 DQ12 =88, DQ13 =84, DQ14 =92, DQ15 =92
1381 23:03:35.689549
1382 23:03:35.689612
1383 23:03:35.696418 [DQSOSCAuto] RK1, (LSB)MR18= 0x441f, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 392 ps
1384 23:03:35.699622 CH0 RK1: MR19=606, MR18=441F
1385 23:03:35.706255 CH0_RK1: MR19=0x606, MR18=0x441F, DQSOSC=392, MR23=63, INC=96, DEC=64
1386 23:03:35.709480 [RxdqsGatingPostProcess] freq 800
1387 23:03:35.716526 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1388 23:03:35.716607 Pre-setting of DQS Precalculation
1389 23:03:35.723105 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1390 23:03:35.723186 ==
1391 23:03:35.726270 Dram Type= 6, Freq= 0, CH_1, rank 0
1392 23:03:35.729394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1393 23:03:35.729481 ==
1394 23:03:35.736261 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1395 23:03:35.742963 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1396 23:03:35.751127 [CA 0] Center 36 (6~67) winsize 62
1397 23:03:35.754595 [CA 1] Center 36 (6~67) winsize 62
1398 23:03:35.757822 [CA 2] Center 34 (4~65) winsize 62
1399 23:03:35.761081 [CA 3] Center 34 (3~65) winsize 63
1400 23:03:35.764666 [CA 4] Center 34 (4~65) winsize 62
1401 23:03:35.767890 [CA 5] Center 34 (3~65) winsize 63
1402 23:03:35.767972
1403 23:03:35.771236 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1404 23:03:35.771318
1405 23:03:35.774295 [CATrainingPosCal] consider 1 rank data
1406 23:03:35.777736 u2DelayCellTimex100 = 270/100 ps
1407 23:03:35.781317 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1408 23:03:35.784529 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1409 23:03:35.791174 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1410 23:03:35.794647 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1411 23:03:35.798058 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1412 23:03:35.801453 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1413 23:03:35.801535
1414 23:03:35.804444 CA PerBit enable=1, Macro0, CA PI delay=34
1415 23:03:35.804524
1416 23:03:35.807985 [CBTSetCACLKResult] CA Dly = 34
1417 23:03:35.808066 CS Dly: 5 (0~36)
1418 23:03:35.808130 ==
1419 23:03:35.811216 Dram Type= 6, Freq= 0, CH_1, rank 1
1420 23:03:35.818053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1421 23:03:35.818134 ==
1422 23:03:35.821145 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1423 23:03:35.827791 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1424 23:03:35.837774 [CA 0] Center 36 (6~67) winsize 62
1425 23:03:35.840253 [CA 1] Center 37 (6~68) winsize 63
1426 23:03:35.843806 [CA 2] Center 35 (4~66) winsize 63
1427 23:03:35.847317 [CA 3] Center 34 (4~65) winsize 62
1428 23:03:35.850538 [CA 4] Center 34 (4~65) winsize 62
1429 23:03:35.854148 [CA 5] Center 34 (4~64) winsize 61
1430 23:03:35.854232
1431 23:03:35.857021 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1432 23:03:35.857104
1433 23:03:35.860824 [CATrainingPosCal] consider 2 rank data
1434 23:03:35.863996 u2DelayCellTimex100 = 270/100 ps
1435 23:03:35.867067 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1436 23:03:35.870258 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1437 23:03:35.877179 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1438 23:03:35.880448 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1439 23:03:35.883842 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1440 23:03:35.887780 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1441 23:03:35.887864
1442 23:03:35.891441 CA PerBit enable=1, Macro0, CA PI delay=34
1443 23:03:35.891525
1444 23:03:35.895220 [CBTSetCACLKResult] CA Dly = 34
1445 23:03:35.895304 CS Dly: 5 (0~37)
1446 23:03:35.895370
1447 23:03:35.899212 ----->DramcWriteLeveling(PI) begin...
1448 23:03:35.899297 ==
1449 23:03:35.902375 Dram Type= 6, Freq= 0, CH_1, rank 0
1450 23:03:35.906027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1451 23:03:35.906110 ==
1452 23:03:35.909993 Write leveling (Byte 0): 27 => 27
1453 23:03:35.913720 Write leveling (Byte 1): 27 => 27
1454 23:03:35.917460 DramcWriteLeveling(PI) end<-----
1455 23:03:35.917543
1456 23:03:35.917610 ==
1457 23:03:35.921241 Dram Type= 6, Freq= 0, CH_1, rank 0
1458 23:03:35.924744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1459 23:03:35.924828 ==
1460 23:03:35.927888 [Gating] SW mode calibration
1461 23:03:35.934446 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1462 23:03:35.937698 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1463 23:03:35.944674 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1464 23:03:35.948205 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1465 23:03:35.950942 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 23:03:35.957790 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 23:03:35.961232 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 23:03:35.965017 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 23:03:35.967868 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 23:03:35.974392 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 23:03:35.977800 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 23:03:35.981339 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 23:03:35.988033 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 23:03:35.991666 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 23:03:35.994477 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 23:03:36.001583 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 23:03:36.004676 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 23:03:36.008342 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 23:03:36.014599 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1480 23:03:36.018148 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1481 23:03:36.021466 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1482 23:03:36.028180 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 23:03:36.031546 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 23:03:36.034723 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 23:03:36.037954 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 23:03:36.044807 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 23:03:36.048053 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 23:03:36.051778 0 9 4 | B1->B0 | 2424 2d2d | 0 0 | (0 0) (1 1)
1489 23:03:36.058039 0 9 8 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
1490 23:03:36.061197 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1491 23:03:36.064775 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1492 23:03:36.071422 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1493 23:03:36.074619 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1494 23:03:36.078484 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1495 23:03:36.084684 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1496 23:03:36.088281 0 10 4 | B1->B0 | 2f2f 2d2d | 1 0 | (1 0) (0 0)
1497 23:03:36.091661 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 23:03:36.098490 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 23:03:36.101330 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 23:03:36.104901 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 23:03:36.111819 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 23:03:36.115058 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 23:03:36.118425 0 11 0 | B1->B0 | 2323 2929 | 0 0 | (0 0) (1 1)
1504 23:03:36.121560 0 11 4 | B1->B0 | 2e2e 3939 | 0 0 | (1 1) (0 0)
1505 23:03:36.128470 0 11 8 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1506 23:03:36.131936 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1507 23:03:36.134963 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1508 23:03:36.141470 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1509 23:03:36.144990 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1510 23:03:36.148414 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1511 23:03:36.155268 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1512 23:03:36.158131 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1513 23:03:36.161562 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 23:03:36.168538 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 23:03:36.171374 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 23:03:36.174950 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 23:03:36.181475 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 23:03:36.184950 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 23:03:36.188086 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 23:03:36.194906 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1521 23:03:36.198270 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1522 23:03:36.201886 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1523 23:03:36.207995 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1524 23:03:36.211525 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1525 23:03:36.214955 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1526 23:03:36.221559 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1527 23:03:36.225412 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1528 23:03:36.228408 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1529 23:03:36.231845 Total UI for P1: 0, mck2ui 16
1530 23:03:36.234920 best dqsien dly found for B0: ( 0, 14, 2)
1531 23:03:36.238369 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1532 23:03:36.241587 Total UI for P1: 0, mck2ui 16
1533 23:03:36.244929 best dqsien dly found for B1: ( 0, 14, 4)
1534 23:03:36.248260 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1535 23:03:36.252005 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1536 23:03:36.252089
1537 23:03:36.258219 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1538 23:03:36.261553 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1539 23:03:36.261637 [Gating] SW calibration Done
1540 23:03:36.264983 ==
1541 23:03:36.265066 Dram Type= 6, Freq= 0, CH_1, rank 0
1542 23:03:36.271961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1543 23:03:36.272045 ==
1544 23:03:36.272111 RX Vref Scan: 0
1545 23:03:36.272173
1546 23:03:36.275465 RX Vref 0 -> 0, step: 1
1547 23:03:36.275549
1548 23:03:36.278415 RX Delay -130 -> 252, step: 16
1549 23:03:36.281990 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1550 23:03:36.285427 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1551 23:03:36.288431 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1552 23:03:36.295205 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1553 23:03:36.298410 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1554 23:03:36.301827 iDelay=222, Bit 5, Center 93 (-18 ~ 205) 224
1555 23:03:36.305055 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1556 23:03:36.308703 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1557 23:03:36.315498 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1558 23:03:36.318563 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1559 23:03:36.321951 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1560 23:03:36.325513 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1561 23:03:36.328852 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1562 23:03:36.335451 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1563 23:03:36.338719 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1564 23:03:36.342113 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1565 23:03:36.342194 ==
1566 23:03:36.345473 Dram Type= 6, Freq= 0, CH_1, rank 0
1567 23:03:36.348859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1568 23:03:36.348942 ==
1569 23:03:36.352124 DQS Delay:
1570 23:03:36.352206 DQS0 = 0, DQS1 = 0
1571 23:03:36.355537 DQM Delay:
1572 23:03:36.355618 DQM0 = 91, DQM1 = 80
1573 23:03:36.355684 DQ Delay:
1574 23:03:36.359172 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1575 23:03:36.362292 DQ4 =93, DQ5 =93, DQ6 =101, DQ7 =93
1576 23:03:36.365315 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1577 23:03:36.368688 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1578 23:03:36.368770
1579 23:03:36.368835
1580 23:03:36.368895 ==
1581 23:03:36.372351 Dram Type= 6, Freq= 0, CH_1, rank 0
1582 23:03:36.378645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1583 23:03:36.378728 ==
1584 23:03:36.378793
1585 23:03:36.378853
1586 23:03:36.378912 TX Vref Scan disable
1587 23:03:36.382699 == TX Byte 0 ==
1588 23:03:36.386058 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1589 23:03:36.389314 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1590 23:03:36.392905 == TX Byte 1 ==
1591 23:03:36.396264 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1592 23:03:36.400025 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1593 23:03:36.402670 ==
1594 23:03:36.406056 Dram Type= 6, Freq= 0, CH_1, rank 0
1595 23:03:36.409238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1596 23:03:36.409320 ==
1597 23:03:36.421976 TX Vref=22, minBit 8, minWin=27, winSum=448
1598 23:03:36.424701 TX Vref=24, minBit 10, minWin=27, winSum=454
1599 23:03:36.428041 TX Vref=26, minBit 10, minWin=27, winSum=454
1600 23:03:36.431592 TX Vref=28, minBit 15, minWin=27, winSum=458
1601 23:03:36.434991 TX Vref=30, minBit 9, minWin=27, winSum=457
1602 23:03:36.442067 TX Vref=32, minBit 12, minWin=27, winSum=457
1603 23:03:36.444761 [TxChooseVref] Worse bit 15, Min win 27, Win sum 458, Final Vref 28
1604 23:03:36.444844
1605 23:03:36.448503 Final TX Range 1 Vref 28
1606 23:03:36.448592
1607 23:03:36.448657 ==
1608 23:03:36.451747 Dram Type= 6, Freq= 0, CH_1, rank 0
1609 23:03:36.455020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1610 23:03:36.458189 ==
1611 23:03:36.458296
1612 23:03:36.458395
1613 23:03:36.458495 TX Vref Scan disable
1614 23:03:36.461780 == TX Byte 0 ==
1615 23:03:36.465457 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1616 23:03:36.468734 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1617 23:03:36.471980 == TX Byte 1 ==
1618 23:03:36.475322 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1619 23:03:36.478760 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1620 23:03:36.478842
1621 23:03:36.482128 [DATLAT]
1622 23:03:36.482210 Freq=800, CH1 RK0
1623 23:03:36.482275
1624 23:03:36.485418 DATLAT Default: 0xa
1625 23:03:36.485501 0, 0xFFFF, sum = 0
1626 23:03:36.488804 1, 0xFFFF, sum = 0
1627 23:03:36.488889 2, 0xFFFF, sum = 0
1628 23:03:36.492226 3, 0xFFFF, sum = 0
1629 23:03:36.492339 4, 0xFFFF, sum = 0
1630 23:03:36.496338 5, 0xFFFF, sum = 0
1631 23:03:36.496421 6, 0xFFFF, sum = 0
1632 23:03:36.498963 7, 0xFFFF, sum = 0
1633 23:03:36.499046 8, 0xFFFF, sum = 0
1634 23:03:36.501712 9, 0x0, sum = 1
1635 23:03:36.501795 10, 0x0, sum = 2
1636 23:03:36.505543 11, 0x0, sum = 3
1637 23:03:36.505626 12, 0x0, sum = 4
1638 23:03:36.508571 best_step = 10
1639 23:03:36.508652
1640 23:03:36.508717 ==
1641 23:03:36.512117 Dram Type= 6, Freq= 0, CH_1, rank 0
1642 23:03:36.515343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1643 23:03:36.515427 ==
1644 23:03:36.518626 RX Vref Scan: 1
1645 23:03:36.518708
1646 23:03:36.518773 Set Vref Range= 32 -> 127
1647 23:03:36.518833
1648 23:03:36.521923 RX Vref 32 -> 127, step: 1
1649 23:03:36.522005
1650 23:03:36.525642 RX Delay -95 -> 252, step: 8
1651 23:03:36.525724
1652 23:03:36.528679 Set Vref, RX VrefLevel [Byte0]: 32
1653 23:03:36.531885 [Byte1]: 32
1654 23:03:36.531968
1655 23:03:36.535521 Set Vref, RX VrefLevel [Byte0]: 33
1656 23:03:36.538854 [Byte1]: 33
1657 23:03:36.542287
1658 23:03:36.542418 Set Vref, RX VrefLevel [Byte0]: 34
1659 23:03:36.545416 [Byte1]: 34
1660 23:03:36.549633
1661 23:03:36.549715 Set Vref, RX VrefLevel [Byte0]: 35
1662 23:03:36.553493 [Byte1]: 35
1663 23:03:36.557446
1664 23:03:36.557527 Set Vref, RX VrefLevel [Byte0]: 36
1665 23:03:36.560679 [Byte1]: 36
1666 23:03:36.564921
1667 23:03:36.565002 Set Vref, RX VrefLevel [Byte0]: 37
1668 23:03:36.571255 [Byte1]: 37
1669 23:03:36.571339
1670 23:03:36.574406 Set Vref, RX VrefLevel [Byte0]: 38
1671 23:03:36.578106 [Byte1]: 38
1672 23:03:36.578187
1673 23:03:36.581601 Set Vref, RX VrefLevel [Byte0]: 39
1674 23:03:36.584871 [Byte1]: 39
1675 23:03:36.584948
1676 23:03:36.587993 Set Vref, RX VrefLevel [Byte0]: 40
1677 23:03:36.591414 [Byte1]: 40
1678 23:03:36.595225
1679 23:03:36.595308 Set Vref, RX VrefLevel [Byte0]: 41
1680 23:03:36.598396 [Byte1]: 41
1681 23:03:36.602671
1682 23:03:36.602748 Set Vref, RX VrefLevel [Byte0]: 42
1683 23:03:36.606093 [Byte1]: 42
1684 23:03:36.610421
1685 23:03:36.610502 Set Vref, RX VrefLevel [Byte0]: 43
1686 23:03:36.613693 [Byte1]: 43
1687 23:03:36.617865
1688 23:03:36.617947 Set Vref, RX VrefLevel [Byte0]: 44
1689 23:03:36.621169 [Byte1]: 44
1690 23:03:36.625535
1691 23:03:36.625617 Set Vref, RX VrefLevel [Byte0]: 45
1692 23:03:36.628745 [Byte1]: 45
1693 23:03:36.632985
1694 23:03:36.633071 Set Vref, RX VrefLevel [Byte0]: 46
1695 23:03:36.636522 [Byte1]: 46
1696 23:03:36.640740
1697 23:03:36.640823 Set Vref, RX VrefLevel [Byte0]: 47
1698 23:03:36.643970 [Byte1]: 47
1699 23:03:36.648171
1700 23:03:36.648254 Set Vref, RX VrefLevel [Byte0]: 48
1701 23:03:36.651983 [Byte1]: 48
1702 23:03:36.655957
1703 23:03:36.656041 Set Vref, RX VrefLevel [Byte0]: 49
1704 23:03:36.659397 [Byte1]: 49
1705 23:03:36.663800
1706 23:03:36.663880 Set Vref, RX VrefLevel [Byte0]: 50
1707 23:03:36.666875 [Byte1]: 50
1708 23:03:36.671111
1709 23:03:36.671194 Set Vref, RX VrefLevel [Byte0]: 51
1710 23:03:36.674788 [Byte1]: 51
1711 23:03:36.678661
1712 23:03:36.678744 Set Vref, RX VrefLevel [Byte0]: 52
1713 23:03:36.682182 [Byte1]: 52
1714 23:03:36.686538
1715 23:03:36.686620 Set Vref, RX VrefLevel [Byte0]: 53
1716 23:03:36.689689 [Byte1]: 53
1717 23:03:36.693811
1718 23:03:36.693893 Set Vref, RX VrefLevel [Byte0]: 54
1719 23:03:36.697196 [Byte1]: 54
1720 23:03:36.701797
1721 23:03:36.701880 Set Vref, RX VrefLevel [Byte0]: 55
1722 23:03:36.705233 [Byte1]: 55
1723 23:03:36.709133
1724 23:03:36.709216 Set Vref, RX VrefLevel [Byte0]: 56
1725 23:03:36.712667 [Byte1]: 56
1726 23:03:36.716894
1727 23:03:36.716977 Set Vref, RX VrefLevel [Byte0]: 57
1728 23:03:36.720127 [Byte1]: 57
1729 23:03:36.724510
1730 23:03:36.724593 Set Vref, RX VrefLevel [Byte0]: 58
1731 23:03:36.727810 [Byte1]: 58
1732 23:03:36.732510
1733 23:03:36.732593 Set Vref, RX VrefLevel [Byte0]: 59
1734 23:03:36.735364 [Byte1]: 59
1735 23:03:36.739824
1736 23:03:36.739903 Set Vref, RX VrefLevel [Byte0]: 60
1737 23:03:36.743075 [Byte1]: 60
1738 23:03:36.747239
1739 23:03:36.747347 Set Vref, RX VrefLevel [Byte0]: 61
1740 23:03:36.750969 [Byte1]: 61
1741 23:03:36.755101
1742 23:03:36.755174 Set Vref, RX VrefLevel [Byte0]: 62
1743 23:03:36.757995 [Byte1]: 62
1744 23:03:36.762628
1745 23:03:36.762704 Set Vref, RX VrefLevel [Byte0]: 63
1746 23:03:36.765724 [Byte1]: 63
1747 23:03:36.769743
1748 23:03:36.769843 Set Vref, RX VrefLevel [Byte0]: 64
1749 23:03:36.773368 [Byte1]: 64
1750 23:03:36.777444
1751 23:03:36.777542 Set Vref, RX VrefLevel [Byte0]: 65
1752 23:03:36.780671 [Byte1]: 65
1753 23:03:36.785040
1754 23:03:36.785116 Set Vref, RX VrefLevel [Byte0]: 66
1755 23:03:36.788633 [Byte1]: 66
1756 23:03:36.792933
1757 23:03:36.793007 Set Vref, RX VrefLevel [Byte0]: 67
1758 23:03:36.796082 [Byte1]: 67
1759 23:03:36.800957
1760 23:03:36.801031 Set Vref, RX VrefLevel [Byte0]: 68
1761 23:03:36.803682 [Byte1]: 68
1762 23:03:36.808019
1763 23:03:36.808090 Set Vref, RX VrefLevel [Byte0]: 69
1764 23:03:36.811169 [Byte1]: 69
1765 23:03:36.815714
1766 23:03:36.815788 Set Vref, RX VrefLevel [Byte0]: 70
1767 23:03:36.819148 [Byte1]: 70
1768 23:03:36.823146
1769 23:03:36.823221 Set Vref, RX VrefLevel [Byte0]: 71
1770 23:03:36.826401 [Byte1]: 71
1771 23:03:36.830724
1772 23:03:36.830870 Set Vref, RX VrefLevel [Byte0]: 72
1773 23:03:36.834183 [Byte1]: 72
1774 23:03:36.838239
1775 23:03:36.838341 Set Vref, RX VrefLevel [Byte0]: 73
1776 23:03:36.842132 [Byte1]: 73
1777 23:03:36.846170
1778 23:03:36.846280 Set Vref, RX VrefLevel [Byte0]: 74
1779 23:03:36.849701 [Byte1]: 74
1780 23:03:36.853627
1781 23:03:36.853725 Set Vref, RX VrefLevel [Byte0]: 75
1782 23:03:36.856677 [Byte1]: 75
1783 23:03:36.861054
1784 23:03:36.861154 Set Vref, RX VrefLevel [Byte0]: 76
1785 23:03:36.864946 [Byte1]: 76
1786 23:03:36.868563
1787 23:03:36.868640 Set Vref, RX VrefLevel [Byte0]: 77
1788 23:03:36.871969 [Byte1]: 77
1789 23:03:36.876440
1790 23:03:36.876510 Set Vref, RX VrefLevel [Byte0]: 78
1791 23:03:36.879563 [Byte1]: 78
1792 23:03:36.883863
1793 23:03:36.883937 Final RX Vref Byte 0 = 53 to rank0
1794 23:03:36.887187 Final RX Vref Byte 1 = 63 to rank0
1795 23:03:36.890479 Final RX Vref Byte 0 = 53 to rank1
1796 23:03:36.894192 Final RX Vref Byte 1 = 63 to rank1==
1797 23:03:36.897355 Dram Type= 6, Freq= 0, CH_1, rank 0
1798 23:03:36.904348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1799 23:03:36.904425 ==
1800 23:03:36.904489 DQS Delay:
1801 23:03:36.904551 DQS0 = 0, DQS1 = 0
1802 23:03:36.907767 DQM Delay:
1803 23:03:36.907839 DQM0 = 92, DQM1 = 83
1804 23:03:36.910480 DQ Delay:
1805 23:03:36.914073 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =88
1806 23:03:36.917363 DQ4 =92, DQ5 =104, DQ6 =100, DQ7 =88
1807 23:03:36.917435 DQ8 =72, DQ9 =72, DQ10 =88, DQ11 =80
1808 23:03:36.923816 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
1809 23:03:36.923897
1810 23:03:36.923960
1811 23:03:36.930967 [DQSOSCAuto] RK0, (LSB)MR18= 0x314e, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
1812 23:03:36.934107 CH1 RK0: MR19=606, MR18=314E
1813 23:03:36.941172 CH1_RK0: MR19=0x606, MR18=0x314E, DQSOSC=390, MR23=63, INC=97, DEC=64
1814 23:03:36.941247
1815 23:03:36.943879 ----->DramcWriteLeveling(PI) begin...
1816 23:03:36.943954 ==
1817 23:03:36.947597 Dram Type= 6, Freq= 0, CH_1, rank 1
1818 23:03:36.950562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1819 23:03:36.950639 ==
1820 23:03:36.954072 Write leveling (Byte 0): 25 => 25
1821 23:03:36.957403 Write leveling (Byte 1): 30 => 30
1822 23:03:36.960563 DramcWriteLeveling(PI) end<-----
1823 23:03:36.960639
1824 23:03:36.960702 ==
1825 23:03:36.963854 Dram Type= 6, Freq= 0, CH_1, rank 1
1826 23:03:36.967619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1827 23:03:36.967694 ==
1828 23:03:36.970711 [Gating] SW mode calibration
1829 23:03:36.977391 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1830 23:03:36.983920 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1831 23:03:36.987537 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1832 23:03:36.990934 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1833 23:03:36.997401 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1834 23:03:37.000830 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 23:03:37.004206 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 23:03:37.010796 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 23:03:37.014232 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 23:03:37.017687 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 23:03:37.023902 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 23:03:37.027376 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 23:03:37.030571 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 23:03:37.037514 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 23:03:37.040673 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 23:03:37.044226 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 23:03:37.047388 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 23:03:37.054059 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 23:03:37.057493 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 23:03:37.060706 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1849 23:03:37.067340 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 23:03:37.070917 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 23:03:37.074255 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 23:03:37.080878 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 23:03:37.084040 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 23:03:37.087324 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 23:03:37.094355 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 23:03:37.097423 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 23:03:37.101093 0 9 8 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
1858 23:03:37.107571 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1859 23:03:37.110959 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1860 23:03:37.114280 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1861 23:03:37.120612 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1862 23:03:37.124256 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1863 23:03:37.127560 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1864 23:03:37.130872 0 10 4 | B1->B0 | 2c2c 3030 | 0 0 | (0 0) (0 1)
1865 23:03:37.137819 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1866 23:03:37.141044 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 23:03:37.144114 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 23:03:37.150779 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 23:03:37.153971 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 23:03:37.157545 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 23:03:37.164334 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 23:03:37.167628 0 11 4 | B1->B0 | 3232 3232 | 0 0 | (1 1) (1 1)
1873 23:03:37.171017 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1874 23:03:37.177497 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1875 23:03:37.180793 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1876 23:03:37.184158 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1877 23:03:37.191070 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1878 23:03:37.194505 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1879 23:03:37.197554 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1880 23:03:37.204411 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1881 23:03:37.207657 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1882 23:03:37.211116 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 23:03:37.214504 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1884 23:03:37.221403 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1885 23:03:37.224346 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1886 23:03:37.227827 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1887 23:03:37.234279 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1888 23:03:37.237553 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1889 23:03:37.241233 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1890 23:03:37.247676 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1891 23:03:37.251145 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1892 23:03:37.254227 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1893 23:03:37.261174 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1894 23:03:37.264780 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1895 23:03:37.267864 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1896 23:03:37.274366 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1897 23:03:37.278061 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1898 23:03:37.281274 Total UI for P1: 0, mck2ui 16
1899 23:03:37.284678 best dqsien dly found for B0: ( 0, 14, 4)
1900 23:03:37.287934 Total UI for P1: 0, mck2ui 16
1901 23:03:37.291303 best dqsien dly found for B1: ( 0, 14, 4)
1902 23:03:37.294542 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1903 23:03:37.297937 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1904 23:03:37.298015
1905 23:03:37.301322 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1906 23:03:37.305085 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1907 23:03:37.308087 [Gating] SW calibration Done
1908 23:03:37.308158 ==
1909 23:03:37.311558 Dram Type= 6, Freq= 0, CH_1, rank 1
1910 23:03:37.314950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1911 23:03:37.315023 ==
1912 23:03:37.318221 RX Vref Scan: 0
1913 23:03:37.318294
1914 23:03:37.318354 RX Vref 0 -> 0, step: 1
1915 23:03:37.318455
1916 23:03:37.321255 RX Delay -130 -> 252, step: 16
1917 23:03:37.324690 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1918 23:03:37.331396 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1919 23:03:37.335036 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1920 23:03:37.338351 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1921 23:03:37.341637 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1922 23:03:37.344922 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1923 23:03:37.351396 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1924 23:03:37.354953 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1925 23:03:37.358414 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
1926 23:03:37.361631 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1927 23:03:37.364774 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1928 23:03:37.371619 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1929 23:03:37.375038 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1930 23:03:37.378487 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1931 23:03:37.381507 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1932 23:03:37.385238 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1933 23:03:37.388438 ==
1934 23:03:37.388510 Dram Type= 6, Freq= 0, CH_1, rank 1
1935 23:03:37.395012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1936 23:03:37.395094 ==
1937 23:03:37.395159 DQS Delay:
1938 23:03:37.398346 DQS0 = 0, DQS1 = 0
1939 23:03:37.398457 DQM Delay:
1940 23:03:37.401757 DQM0 = 89, DQM1 = 85
1941 23:03:37.401841 DQ Delay:
1942 23:03:37.404939 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1943 23:03:37.408299 DQ4 =93, DQ5 =93, DQ6 =93, DQ7 =85
1944 23:03:37.411715 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
1945 23:03:37.414957 DQ12 =93, DQ13 =93, DQ14 =85, DQ15 =93
1946 23:03:37.415041
1947 23:03:37.415107
1948 23:03:37.415170 ==
1949 23:03:37.418580 Dram Type= 6, Freq= 0, CH_1, rank 1
1950 23:03:37.421695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1951 23:03:37.421778 ==
1952 23:03:37.421844
1953 23:03:37.421903
1954 23:03:37.425160 TX Vref Scan disable
1955 23:03:37.425242 == TX Byte 0 ==
1956 23:03:37.431765 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1957 23:03:37.435483 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1958 23:03:37.435566 == TX Byte 1 ==
1959 23:03:37.441742 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1960 23:03:37.444934 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1961 23:03:37.445041 ==
1962 23:03:37.448410 Dram Type= 6, Freq= 0, CH_1, rank 1
1963 23:03:37.451804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1964 23:03:37.451904 ==
1965 23:03:37.466487 TX Vref=22, minBit 9, minWin=27, winSum=449
1966 23:03:37.469773 TX Vref=24, minBit 13, minWin=27, winSum=452
1967 23:03:37.472968 TX Vref=26, minBit 13, minWin=27, winSum=454
1968 23:03:37.476484 TX Vref=28, minBit 13, minWin=27, winSum=457
1969 23:03:37.480135 TX Vref=30, minBit 8, minWin=28, winSum=459
1970 23:03:37.486330 TX Vref=32, minBit 8, minWin=28, winSum=461
1971 23:03:37.489649 [TxChooseVref] Worse bit 8, Min win 28, Win sum 461, Final Vref 32
1972 23:03:37.489732
1973 23:03:37.492961 Final TX Range 1 Vref 32
1974 23:03:37.493044
1975 23:03:37.493109 ==
1976 23:03:37.496430 Dram Type= 6, Freq= 0, CH_1, rank 1
1977 23:03:37.499510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1978 23:03:37.499593 ==
1979 23:03:37.502910
1980 23:03:37.503018
1981 23:03:37.503111 TX Vref Scan disable
1982 23:03:37.506478 == TX Byte 0 ==
1983 23:03:37.509670 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1984 23:03:37.513015 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1985 23:03:37.516626 == TX Byte 1 ==
1986 23:03:37.519792 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1987 23:03:37.523552 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1988 23:03:37.526297
1989 23:03:37.526441 [DATLAT]
1990 23:03:37.526540 Freq=800, CH1 RK1
1991 23:03:37.526602
1992 23:03:37.529931 DATLAT Default: 0xa
1993 23:03:37.530048 0, 0xFFFF, sum = 0
1994 23:03:37.533161 1, 0xFFFF, sum = 0
1995 23:03:37.533271 2, 0xFFFF, sum = 0
1996 23:03:37.536980 3, 0xFFFF, sum = 0
1997 23:03:37.537064 4, 0xFFFF, sum = 0
1998 23:03:37.539951 5, 0xFFFF, sum = 0
1999 23:03:37.540067 6, 0xFFFF, sum = 0
2000 23:03:37.543220 7, 0xFFFF, sum = 0
2001 23:03:37.543304 8, 0xFFFF, sum = 0
2002 23:03:37.546539 9, 0x0, sum = 1
2003 23:03:37.546622 10, 0x0, sum = 2
2004 23:03:37.549832 11, 0x0, sum = 3
2005 23:03:37.549916 12, 0x0, sum = 4
2006 23:03:37.553261 best_step = 10
2007 23:03:37.553343
2008 23:03:37.553408 ==
2009 23:03:37.556413 Dram Type= 6, Freq= 0, CH_1, rank 1
2010 23:03:37.559834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2011 23:03:37.559917 ==
2012 23:03:37.563242 RX Vref Scan: 0
2013 23:03:37.563323
2014 23:03:37.563388 RX Vref 0 -> 0, step: 1
2015 23:03:37.563449
2016 23:03:37.566826 RX Delay -79 -> 252, step: 8
2017 23:03:37.573399 iDelay=209, Bit 0, Center 96 (-7 ~ 200) 208
2018 23:03:37.576838 iDelay=209, Bit 1, Center 88 (-15 ~ 192) 208
2019 23:03:37.579925 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
2020 23:03:37.583428 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2021 23:03:37.586574 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
2022 23:03:37.590176 iDelay=209, Bit 5, Center 108 (9 ~ 208) 200
2023 23:03:37.596517 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2024 23:03:37.599989 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2025 23:03:37.603243 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2026 23:03:37.607072 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
2027 23:03:37.610271 iDelay=209, Bit 10, Center 84 (-31 ~ 200) 232
2028 23:03:37.616847 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2029 23:03:37.620187 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2030 23:03:37.623451 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
2031 23:03:37.626755 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2032 23:03:37.633546 iDelay=209, Bit 15, Center 96 (-15 ~ 208) 224
2033 23:03:37.633629 ==
2034 23:03:37.636969 Dram Type= 6, Freq= 0, CH_1, rank 1
2035 23:03:37.640004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2036 23:03:37.640087 ==
2037 23:03:37.640153 DQS Delay:
2038 23:03:37.643689 DQS0 = 0, DQS1 = 0
2039 23:03:37.643779 DQM Delay:
2040 23:03:37.646607 DQM0 = 92, DQM1 = 84
2041 23:03:37.646714 DQ Delay:
2042 23:03:37.649952 DQ0 =96, DQ1 =88, DQ2 =80, DQ3 =88
2043 23:03:37.653621 DQ4 =92, DQ5 =108, DQ6 =96, DQ7 =88
2044 23:03:37.657068 DQ8 =68, DQ9 =76, DQ10 =84, DQ11 =80
2045 23:03:37.660233 DQ12 =92, DQ13 =92, DQ14 =88, DQ15 =96
2046 23:03:37.660325
2047 23:03:37.660426
2048 23:03:37.666572 [DQSOSCAuto] RK1, (LSB)MR18= 0x3a0f, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 395 ps
2049 23:03:37.670226 CH1 RK1: MR19=606, MR18=3A0F
2050 23:03:37.676878 CH1_RK1: MR19=0x606, MR18=0x3A0F, DQSOSC=395, MR23=63, INC=94, DEC=63
2051 23:03:37.680170 [RxdqsGatingPostProcess] freq 800
2052 23:03:37.686899 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2053 23:03:37.687009 Pre-setting of DQS Precalculation
2054 23:03:37.693669 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2055 23:03:37.700244 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2056 23:03:37.707032 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2057 23:03:37.707116
2058 23:03:37.707181
2059 23:03:37.710167 [Calibration Summary] 1600 Mbps
2060 23:03:37.713664 CH 0, Rank 0
2061 23:03:37.713747 SW Impedance : PASS
2062 23:03:37.717217 DUTY Scan : NO K
2063 23:03:37.717301 ZQ Calibration : PASS
2064 23:03:37.720196 Jitter Meter : NO K
2065 23:03:37.724145 CBT Training : PASS
2066 23:03:37.724227 Write leveling : PASS
2067 23:03:37.726991 RX DQS gating : PASS
2068 23:03:37.730448 RX DQ/DQS(RDDQC) : PASS
2069 23:03:37.730534 TX DQ/DQS : PASS
2070 23:03:37.734066 RX DATLAT : PASS
2071 23:03:37.737328 RX DQ/DQS(Engine): PASS
2072 23:03:37.737411 TX OE : NO K
2073 23:03:37.737477 All Pass.
2074 23:03:37.740776
2075 23:03:37.740857 CH 0, Rank 1
2076 23:03:37.743674 SW Impedance : PASS
2077 23:03:37.743757 DUTY Scan : NO K
2078 23:03:37.747300 ZQ Calibration : PASS
2079 23:03:37.747383 Jitter Meter : NO K
2080 23:03:37.750273 CBT Training : PASS
2081 23:03:37.753970 Write leveling : PASS
2082 23:03:37.754052 RX DQS gating : PASS
2083 23:03:37.757063 RX DQ/DQS(RDDQC) : PASS
2084 23:03:37.760865 TX DQ/DQS : PASS
2085 23:03:37.760960 RX DATLAT : PASS
2086 23:03:37.764192 RX DQ/DQS(Engine): PASS
2087 23:03:37.767473 TX OE : NO K
2088 23:03:37.767556 All Pass.
2089 23:03:37.767621
2090 23:03:37.767682 CH 1, Rank 0
2091 23:03:37.770525 SW Impedance : PASS
2092 23:03:37.773842 DUTY Scan : NO K
2093 23:03:37.773924 ZQ Calibration : PASS
2094 23:03:37.777373 Jitter Meter : NO K
2095 23:03:37.780582 CBT Training : PASS
2096 23:03:37.780665 Write leveling : PASS
2097 23:03:37.783711 RX DQS gating : PASS
2098 23:03:37.783794 RX DQ/DQS(RDDQC) : PASS
2099 23:03:37.787325 TX DQ/DQS : PASS
2100 23:03:37.790842 RX DATLAT : PASS
2101 23:03:37.790924 RX DQ/DQS(Engine): PASS
2102 23:03:37.794200 TX OE : NO K
2103 23:03:37.794282 All Pass.
2104 23:03:37.794392
2105 23:03:37.797626 CH 1, Rank 1
2106 23:03:37.797709 SW Impedance : PASS
2107 23:03:37.800657 DUTY Scan : NO K
2108 23:03:37.804136 ZQ Calibration : PASS
2109 23:03:37.804244 Jitter Meter : NO K
2110 23:03:37.807635 CBT Training : PASS
2111 23:03:37.810982 Write leveling : PASS
2112 23:03:37.811064 RX DQS gating : PASS
2113 23:03:37.813854 RX DQ/DQS(RDDQC) : PASS
2114 23:03:37.817395 TX DQ/DQS : PASS
2115 23:03:37.817492 RX DATLAT : PASS
2116 23:03:37.820833 RX DQ/DQS(Engine): PASS
2117 23:03:37.820915 TX OE : NO K
2118 23:03:37.824109 All Pass.
2119 23:03:37.824191
2120 23:03:37.824256 DramC Write-DBI off
2121 23:03:37.827341 PER_BANK_REFRESH: Hybrid Mode
2122 23:03:37.830870 TX_TRACKING: ON
2123 23:03:37.834279 [GetDramInforAfterCalByMRR] Vendor 6.
2124 23:03:37.837666 [GetDramInforAfterCalByMRR] Revision 606.
2125 23:03:37.841124 [GetDramInforAfterCalByMRR] Revision 2 0.
2126 23:03:37.841207 MR0 0x3b3b
2127 23:03:37.841273 MR8 0x5151
2128 23:03:37.847656 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2129 23:03:37.847738
2130 23:03:37.847804 MR0 0x3b3b
2131 23:03:37.847866 MR8 0x5151
2132 23:03:37.851158 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2133 23:03:37.851267
2134 23:03:37.861087 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2135 23:03:37.864469 [FAST_K] Save calibration result to emmc
2136 23:03:37.867649 [FAST_K] Save calibration result to emmc
2137 23:03:37.871158 dram_init: config_dvfs: 1
2138 23:03:37.874338 dramc_set_vcore_voltage set vcore to 662500
2139 23:03:37.877648 Read voltage for 1200, 2
2140 23:03:37.877731 Vio18 = 0
2141 23:03:37.877797 Vcore = 662500
2142 23:03:37.881043 Vdram = 0
2143 23:03:37.881126 Vddq = 0
2144 23:03:37.881192 Vmddr = 0
2145 23:03:37.887384 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2146 23:03:37.890953 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2147 23:03:37.894265 MEM_TYPE=3, freq_sel=15
2148 23:03:37.897502 sv_algorithm_assistance_LP4_1600
2149 23:03:37.900874 ============ PULL DRAM RESETB DOWN ============
2150 23:03:37.904362 ========== PULL DRAM RESETB DOWN end =========
2151 23:03:37.910924 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2152 23:03:37.914454 ===================================
2153 23:03:37.914538 LPDDR4 DRAM CONFIGURATION
2154 23:03:37.917516 ===================================
2155 23:03:37.921129 EX_ROW_EN[0] = 0x0
2156 23:03:37.924507 EX_ROW_EN[1] = 0x0
2157 23:03:37.924590 LP4Y_EN = 0x0
2158 23:03:37.927776 WORK_FSP = 0x0
2159 23:03:37.927858 WL = 0x4
2160 23:03:37.930856 RL = 0x4
2161 23:03:37.930939 BL = 0x2
2162 23:03:37.934554 RPST = 0x0
2163 23:03:37.934637 RD_PRE = 0x0
2164 23:03:37.937356 WR_PRE = 0x1
2165 23:03:37.937439 WR_PST = 0x0
2166 23:03:37.940675 DBI_WR = 0x0
2167 23:03:37.940759 DBI_RD = 0x0
2168 23:03:37.944388 OTF = 0x1
2169 23:03:37.947973 ===================================
2170 23:03:37.951016 ===================================
2171 23:03:37.951099 ANA top config
2172 23:03:37.954619 ===================================
2173 23:03:37.957661 DLL_ASYNC_EN = 0
2174 23:03:37.961275 ALL_SLAVE_EN = 0
2175 23:03:37.964492 NEW_RANK_MODE = 1
2176 23:03:37.964577 DLL_IDLE_MODE = 1
2177 23:03:37.967692 LP45_APHY_COMB_EN = 1
2178 23:03:37.971168 TX_ODT_DIS = 1
2179 23:03:37.974346 NEW_8X_MODE = 1
2180 23:03:37.977348 ===================================
2181 23:03:37.980853 ===================================
2182 23:03:37.984211 data_rate = 2400
2183 23:03:37.984295 CKR = 1
2184 23:03:37.987523 DQ_P2S_RATIO = 8
2185 23:03:37.990942 ===================================
2186 23:03:37.994229 CA_P2S_RATIO = 8
2187 23:03:37.997514 DQ_CA_OPEN = 0
2188 23:03:38.000848 DQ_SEMI_OPEN = 0
2189 23:03:38.000931 CA_SEMI_OPEN = 0
2190 23:03:38.004160 CA_FULL_RATE = 0
2191 23:03:38.007913 DQ_CKDIV4_EN = 0
2192 23:03:38.011054 CA_CKDIV4_EN = 0
2193 23:03:38.014102 CA_PREDIV_EN = 0
2194 23:03:38.017522 PH8_DLY = 17
2195 23:03:38.017605 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2196 23:03:38.021159 DQ_AAMCK_DIV = 4
2197 23:03:38.024428 CA_AAMCK_DIV = 4
2198 23:03:38.027924 CA_ADMCK_DIV = 4
2199 23:03:38.030994 DQ_TRACK_CA_EN = 0
2200 23:03:38.034294 CA_PICK = 1200
2201 23:03:38.038111 CA_MCKIO = 1200
2202 23:03:38.038195 MCKIO_SEMI = 0
2203 23:03:38.041181 PLL_FREQ = 2366
2204 23:03:38.044653 DQ_UI_PI_RATIO = 32
2205 23:03:38.048005 CA_UI_PI_RATIO = 0
2206 23:03:38.051335 ===================================
2207 23:03:38.054526 ===================================
2208 23:03:38.057611 memory_type:LPDDR4
2209 23:03:38.057694 GP_NUM : 10
2210 23:03:38.060840 SRAM_EN : 1
2211 23:03:38.060923 MD32_EN : 0
2212 23:03:38.064512 ===================================
2213 23:03:38.067469 [ANA_INIT] >>>>>>>>>>>>>>
2214 23:03:38.070801 <<<<<< [CONFIGURE PHASE]: ANA_TX
2215 23:03:38.074566 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2216 23:03:38.077846 ===================================
2217 23:03:38.081215 data_rate = 2400,PCW = 0X5b00
2218 23:03:38.084451 ===================================
2219 23:03:38.087573 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2220 23:03:38.091153 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2221 23:03:38.097951 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2222 23:03:38.104504 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2223 23:03:38.107870 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2224 23:03:38.111567 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2225 23:03:38.111651 [ANA_INIT] flow start
2226 23:03:38.114557 [ANA_INIT] PLL >>>>>>>>
2227 23:03:38.117969 [ANA_INIT] PLL <<<<<<<<
2228 23:03:38.118060 [ANA_INIT] MIDPI >>>>>>>>
2229 23:03:38.121196 [ANA_INIT] MIDPI <<<<<<<<
2230 23:03:38.124452 [ANA_INIT] DLL >>>>>>>>
2231 23:03:38.124535 [ANA_INIT] DLL <<<<<<<<
2232 23:03:38.127822 [ANA_INIT] flow end
2233 23:03:38.130992 ============ LP4 DIFF to SE enter ============
2234 23:03:38.134301 ============ LP4 DIFF to SE exit ============
2235 23:03:38.138139 [ANA_INIT] <<<<<<<<<<<<<
2236 23:03:38.141141 [Flow] Enable top DCM control >>>>>
2237 23:03:38.144401 [Flow] Enable top DCM control <<<<<
2238 23:03:38.148055 Enable DLL master slave shuffle
2239 23:03:38.154478 ==============================================================
2240 23:03:38.154563 Gating Mode config
2241 23:03:38.161366 ==============================================================
2242 23:03:38.161450 Config description:
2243 23:03:38.171334 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2244 23:03:38.177973 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2245 23:03:38.184700 SELPH_MODE 0: By rank 1: By Phase
2246 23:03:38.187833 ==============================================================
2247 23:03:38.191350 GAT_TRACK_EN = 1
2248 23:03:38.194508 RX_GATING_MODE = 2
2249 23:03:38.198059 RX_GATING_TRACK_MODE = 2
2250 23:03:38.201570 SELPH_MODE = 1
2251 23:03:38.204607 PICG_EARLY_EN = 1
2252 23:03:38.208082 VALID_LAT_VALUE = 1
2253 23:03:38.211409 ==============================================================
2254 23:03:38.214759 Enter into Gating configuration >>>>
2255 23:03:38.218001 Exit from Gating configuration <<<<
2256 23:03:38.221396 Enter into DVFS_PRE_config >>>>>
2257 23:03:38.234747 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2258 23:03:38.234840 Exit from DVFS_PRE_config <<<<<
2259 23:03:38.237959 Enter into PICG configuration >>>>
2260 23:03:38.241549 Exit from PICG configuration <<<<
2261 23:03:38.244790 [RX_INPUT] configuration >>>>>
2262 23:03:38.248233 [RX_INPUT] configuration <<<<<
2263 23:03:38.255028 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2264 23:03:38.258076 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2265 23:03:38.264992 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2266 23:03:38.271646 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2267 23:03:38.278230 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2268 23:03:38.285079 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2269 23:03:38.288242 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2270 23:03:38.291574 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2271 23:03:38.294912 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2272 23:03:38.301540 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2273 23:03:38.304800 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2274 23:03:38.308314 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2275 23:03:38.311533 ===================================
2276 23:03:38.314711 LPDDR4 DRAM CONFIGURATION
2277 23:03:38.318655 ===================================
2278 23:03:38.318724 EX_ROW_EN[0] = 0x0
2279 23:03:38.321567 EX_ROW_EN[1] = 0x0
2280 23:03:38.321634 LP4Y_EN = 0x0
2281 23:03:38.325446 WORK_FSP = 0x0
2282 23:03:38.325515 WL = 0x4
2283 23:03:38.328352 RL = 0x4
2284 23:03:38.328427 BL = 0x2
2285 23:03:38.331875 RPST = 0x0
2286 23:03:38.331952 RD_PRE = 0x0
2287 23:03:38.334921 WR_PRE = 0x1
2288 23:03:38.338664 WR_PST = 0x0
2289 23:03:38.338774 DBI_WR = 0x0
2290 23:03:38.341933 DBI_RD = 0x0
2291 23:03:38.342029 OTF = 0x1
2292 23:03:38.345200 ===================================
2293 23:03:38.348460 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2294 23:03:38.354895 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2295 23:03:38.358538 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2296 23:03:38.361568 ===================================
2297 23:03:38.365045 LPDDR4 DRAM CONFIGURATION
2298 23:03:38.368608 ===================================
2299 23:03:38.368705 EX_ROW_EN[0] = 0x10
2300 23:03:38.371574 EX_ROW_EN[1] = 0x0
2301 23:03:38.371642 LP4Y_EN = 0x0
2302 23:03:38.375279 WORK_FSP = 0x0
2303 23:03:38.375376 WL = 0x4
2304 23:03:38.378654 RL = 0x4
2305 23:03:38.378758 BL = 0x2
2306 23:03:38.381810 RPST = 0x0
2307 23:03:38.381895 RD_PRE = 0x0
2308 23:03:38.385196 WR_PRE = 0x1
2309 23:03:38.385338 WR_PST = 0x0
2310 23:03:38.388437 DBI_WR = 0x0
2311 23:03:38.388517 DBI_RD = 0x0
2312 23:03:38.391654 OTF = 0x1
2313 23:03:38.395201 ===================================
2314 23:03:38.401834 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2315 23:03:38.401915 ==
2316 23:03:38.405259 Dram Type= 6, Freq= 0, CH_0, rank 0
2317 23:03:38.408510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2318 23:03:38.408591 ==
2319 23:03:38.411923 [Duty_Offset_Calibration]
2320 23:03:38.412004 B0:2 B1:0 CA:1
2321 23:03:38.412067
2322 23:03:38.414998 [DutyScan_Calibration_Flow] k_type=0
2323 23:03:38.424958
2324 23:03:38.425055 ==CLK 0==
2325 23:03:38.428013 Final CLK duty delay cell = -4
2326 23:03:38.431343 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2327 23:03:38.435033 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2328 23:03:38.438211 [-4] AVG Duty = 4953%(X100)
2329 23:03:38.438313
2330 23:03:38.441276 CH0 CLK Duty spec in!! Max-Min= 156%
2331 23:03:38.444724 [DutyScan_Calibration_Flow] ====Done====
2332 23:03:38.444799
2333 23:03:38.448273 [DutyScan_Calibration_Flow] k_type=1
2334 23:03:38.463572
2335 23:03:38.463648 ==DQS 0 ==
2336 23:03:38.466982 Final DQS duty delay cell = 0
2337 23:03:38.470325 [0] MAX Duty = 5187%(X100), DQS PI = 30
2338 23:03:38.473619 [0] MIN Duty = 4938%(X100), DQS PI = 0
2339 23:03:38.473717 [0] AVG Duty = 5062%(X100)
2340 23:03:38.477145
2341 23:03:38.477249 ==DQS 1 ==
2342 23:03:38.480629 Final DQS duty delay cell = -4
2343 23:03:38.483991 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2344 23:03:38.487432 [-4] MIN Duty = 4938%(X100), DQS PI = 8
2345 23:03:38.490535 [-4] AVG Duty = 5031%(X100)
2346 23:03:38.490615
2347 23:03:38.493854 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2348 23:03:38.493953
2349 23:03:38.497095 CH0 DQS 1 Duty spec in!! Max-Min= 186%
2350 23:03:38.500611 [DutyScan_Calibration_Flow] ====Done====
2351 23:03:38.500708
2352 23:03:38.504027 [DutyScan_Calibration_Flow] k_type=3
2353 23:03:38.520614
2354 23:03:38.520711 ==DQM 0 ==
2355 23:03:38.523827 Final DQM duty delay cell = 0
2356 23:03:38.527124 [0] MAX Duty = 5062%(X100), DQS PI = 24
2357 23:03:38.530673 [0] MIN Duty = 4813%(X100), DQS PI = 2
2358 23:03:38.530743 [0] AVG Duty = 4937%(X100)
2359 23:03:38.533771
2360 23:03:38.533867 ==DQM 1 ==
2361 23:03:38.537113 Final DQM duty delay cell = 0
2362 23:03:38.540758 [0] MAX Duty = 5187%(X100), DQS PI = 46
2363 23:03:38.543782 [0] MIN Duty = 5000%(X100), DQS PI = 12
2364 23:03:38.543862 [0] AVG Duty = 5093%(X100)
2365 23:03:38.547016
2366 23:03:38.550653 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2367 23:03:38.550733
2368 23:03:38.553800 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2369 23:03:38.557206 [DutyScan_Calibration_Flow] ====Done====
2370 23:03:38.557286
2371 23:03:38.560333 [DutyScan_Calibration_Flow] k_type=2
2372 23:03:38.576027
2373 23:03:38.576107 ==DQ 0 ==
2374 23:03:38.579787 Final DQ duty delay cell = -4
2375 23:03:38.582730 [-4] MAX Duty = 5062%(X100), DQS PI = 34
2376 23:03:38.586075 [-4] MIN Duty = 4875%(X100), DQS PI = 14
2377 23:03:38.589199 [-4] AVG Duty = 4968%(X100)
2378 23:03:38.589278
2379 23:03:38.589341 ==DQ 1 ==
2380 23:03:38.592782 Final DQ duty delay cell = 0
2381 23:03:38.595954 [0] MAX Duty = 4938%(X100), DQS PI = 4
2382 23:03:38.599360 [0] MIN Duty = 4907%(X100), DQS PI = 0
2383 23:03:38.602630 [0] AVG Duty = 4922%(X100)
2384 23:03:38.602710
2385 23:03:38.606209 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2386 23:03:38.606288
2387 23:03:38.609478 CH0 DQ 1 Duty spec in!! Max-Min= 31%
2388 23:03:38.612997 [DutyScan_Calibration_Flow] ====Done====
2389 23:03:38.613077 ==
2390 23:03:38.616092 Dram Type= 6, Freq= 0, CH_1, rank 0
2391 23:03:38.619287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2392 23:03:38.619367 ==
2393 23:03:38.622615 [Duty_Offset_Calibration]
2394 23:03:38.622696 B0:0 B1:-1 CA:2
2395 23:03:38.622759
2396 23:03:38.626897 [DutyScan_Calibration_Flow] k_type=0
2397 23:03:38.636464
2398 23:03:38.636545 ==CLK 0==
2399 23:03:38.639492 Final CLK duty delay cell = 0
2400 23:03:38.643525 [0] MAX Duty = 5156%(X100), DQS PI = 14
2401 23:03:38.646346 [0] MIN Duty = 4969%(X100), DQS PI = 44
2402 23:03:38.646451 [0] AVG Duty = 5062%(X100)
2403 23:03:38.650272
2404 23:03:38.653137 CH1 CLK Duty spec in!! Max-Min= 187%
2405 23:03:38.656561 [DutyScan_Calibration_Flow] ====Done====
2406 23:03:38.656644
2407 23:03:38.659491 [DutyScan_Calibration_Flow] k_type=1
2408 23:03:38.675906
2409 23:03:38.675987 ==DQS 0 ==
2410 23:03:38.679074 Final DQS duty delay cell = 0
2411 23:03:38.683015 [0] MAX Duty = 5093%(X100), DQS PI = 24
2412 23:03:38.685608 [0] MIN Duty = 4969%(X100), DQS PI = 0
2413 23:03:38.685690 [0] AVG Duty = 5031%(X100)
2414 23:03:38.689492
2415 23:03:38.689573 ==DQS 1 ==
2416 23:03:38.692619 Final DQS duty delay cell = 0
2417 23:03:38.696017 [0] MAX Duty = 5156%(X100), DQS PI = 0
2418 23:03:38.699128 [0] MIN Duty = 4813%(X100), DQS PI = 36
2419 23:03:38.699211 [0] AVG Duty = 4984%(X100)
2420 23:03:38.699276
2421 23:03:38.705821 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2422 23:03:38.705904
2423 23:03:38.709501 CH1 DQS 1 Duty spec in!! Max-Min= 343%
2424 23:03:38.712872 [DutyScan_Calibration_Flow] ====Done====
2425 23:03:38.712954
2426 23:03:38.715725 [DutyScan_Calibration_Flow] k_type=3
2427 23:03:38.732982
2428 23:03:38.733067 ==DQM 0 ==
2429 23:03:38.736647 Final DQM duty delay cell = 4
2430 23:03:38.739942 [4] MAX Duty = 5124%(X100), DQS PI = 22
2431 23:03:38.743445 [4] MIN Duty = 4938%(X100), DQS PI = 48
2432 23:03:38.743529 [4] AVG Duty = 5031%(X100)
2433 23:03:38.746479
2434 23:03:38.746561 ==DQM 1 ==
2435 23:03:38.749683 Final DQM duty delay cell = 0
2436 23:03:38.753530 [0] MAX Duty = 5249%(X100), DQS PI = 0
2437 23:03:38.756627 [0] MIN Duty = 4875%(X100), DQS PI = 36
2438 23:03:38.756711 [0] AVG Duty = 5062%(X100)
2439 23:03:38.759812
2440 23:03:38.763321 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2441 23:03:38.763405
2442 23:03:38.766692 CH1 DQM 1 Duty spec in!! Max-Min= 374%
2443 23:03:38.770150 [DutyScan_Calibration_Flow] ====Done====
2444 23:03:38.770233
2445 23:03:38.773391 [DutyScan_Calibration_Flow] k_type=2
2446 23:03:38.789575
2447 23:03:38.789658 ==DQ 0 ==
2448 23:03:38.792988 Final DQ duty delay cell = 0
2449 23:03:38.796250 [0] MAX Duty = 5062%(X100), DQS PI = 20
2450 23:03:38.799711 [0] MIN Duty = 4938%(X100), DQS PI = 0
2451 23:03:38.799797 [0] AVG Duty = 5000%(X100)
2452 23:03:38.799882
2453 23:03:38.802918 ==DQ 1 ==
2454 23:03:38.806470 Final DQ duty delay cell = 0
2455 23:03:38.809652 [0] MAX Duty = 5031%(X100), DQS PI = 2
2456 23:03:38.813045 [0] MIN Duty = 4813%(X100), DQS PI = 34
2457 23:03:38.813131 [0] AVG Duty = 4922%(X100)
2458 23:03:38.813216
2459 23:03:38.816448 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2460 23:03:38.816534
2461 23:03:38.820025 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2462 23:03:38.826592 [DutyScan_Calibration_Flow] ====Done====
2463 23:03:38.829937 nWR fixed to 30
2464 23:03:38.830023 [ModeRegInit_LP4] CH0 RK0
2465 23:03:38.833361 [ModeRegInit_LP4] CH0 RK1
2466 23:03:38.836638 [ModeRegInit_LP4] CH1 RK0
2467 23:03:38.836725 [ModeRegInit_LP4] CH1 RK1
2468 23:03:38.839760 match AC timing 7
2469 23:03:38.843316 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2470 23:03:38.846536 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2471 23:03:38.853500 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2472 23:03:38.856487 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2473 23:03:38.863102 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2474 23:03:38.863188 ==
2475 23:03:38.866706 Dram Type= 6, Freq= 0, CH_0, rank 0
2476 23:03:38.870207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2477 23:03:38.870293 ==
2478 23:03:38.876451 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2479 23:03:38.879461 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2480 23:03:38.889562 [CA 0] Center 38 (7~69) winsize 63
2481 23:03:38.892763 [CA 1] Center 38 (7~69) winsize 63
2482 23:03:38.896407 [CA 2] Center 34 (4~65) winsize 62
2483 23:03:38.899689 [CA 3] Center 34 (4~65) winsize 62
2484 23:03:38.902709 [CA 4] Center 34 (4~64) winsize 61
2485 23:03:38.906189 [CA 5] Center 32 (2~63) winsize 62
2486 23:03:38.906275
2487 23:03:38.909541 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2488 23:03:38.909627
2489 23:03:38.912892 [CATrainingPosCal] consider 1 rank data
2490 23:03:38.915975 u2DelayCellTimex100 = 270/100 ps
2491 23:03:38.919350 CA0 delay=38 (7~69),Diff = 6 PI (28 cell)
2492 23:03:38.922819 CA1 delay=38 (7~69),Diff = 6 PI (28 cell)
2493 23:03:38.929444 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2494 23:03:38.932968 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2495 23:03:38.936183 CA4 delay=34 (4~64),Diff = 2 PI (9 cell)
2496 23:03:38.939418 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2497 23:03:38.939491
2498 23:03:38.942929 CA PerBit enable=1, Macro0, CA PI delay=32
2499 23:03:38.943005
2500 23:03:38.946321 [CBTSetCACLKResult] CA Dly = 32
2501 23:03:38.946433 CS Dly: 6 (0~37)
2502 23:03:38.946497 ==
2503 23:03:38.949780 Dram Type= 6, Freq= 0, CH_0, rank 1
2504 23:03:38.956271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2505 23:03:38.956349 ==
2506 23:03:38.959280 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2507 23:03:38.966240 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2508 23:03:38.975095 [CA 0] Center 38 (7~69) winsize 63
2509 23:03:38.978238 [CA 1] Center 38 (7~69) winsize 63
2510 23:03:38.981579 [CA 2] Center 35 (5~66) winsize 62
2511 23:03:38.985345 [CA 3] Center 35 (5~66) winsize 62
2512 23:03:38.988358 [CA 4] Center 34 (3~65) winsize 63
2513 23:03:38.991735 [CA 5] Center 33 (3~63) winsize 61
2514 23:03:38.991817
2515 23:03:38.995144 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2516 23:03:38.995222
2517 23:03:38.998204 [CATrainingPosCal] consider 2 rank data
2518 23:03:39.001907 u2DelayCellTimex100 = 270/100 ps
2519 23:03:39.004878 CA0 delay=38 (7~69),Diff = 5 PI (24 cell)
2520 23:03:39.008396 CA1 delay=38 (7~69),Diff = 5 PI (24 cell)
2521 23:03:39.015195 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
2522 23:03:39.018342 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2523 23:03:39.021568 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2524 23:03:39.024842 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2525 23:03:39.024913
2526 23:03:39.028337 CA PerBit enable=1, Macro0, CA PI delay=33
2527 23:03:39.028408
2528 23:03:39.031858 [CBTSetCACLKResult] CA Dly = 33
2529 23:03:39.031931 CS Dly: 7 (0~39)
2530 23:03:39.031992
2531 23:03:39.035172 ----->DramcWriteLeveling(PI) begin...
2532 23:03:39.038663 ==
2533 23:03:39.038739 Dram Type= 6, Freq= 0, CH_0, rank 0
2534 23:03:39.045288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2535 23:03:39.045358 ==
2536 23:03:39.048580 Write leveling (Byte 0): 33 => 33
2537 23:03:39.052069 Write leveling (Byte 1): 31 => 31
2538 23:03:39.052140 DramcWriteLeveling(PI) end<-----
2539 23:03:39.055126
2540 23:03:39.055191 ==
2541 23:03:39.058545 Dram Type= 6, Freq= 0, CH_0, rank 0
2542 23:03:39.061978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2543 23:03:39.062044 ==
2544 23:03:39.065331 [Gating] SW mode calibration
2545 23:03:39.072179 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2546 23:03:39.075075 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2547 23:03:39.082298 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2548 23:03:39.085001 0 15 4 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
2549 23:03:39.088814 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2550 23:03:39.095023 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2551 23:03:39.098700 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2552 23:03:39.101955 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2553 23:03:39.108859 0 15 24 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
2554 23:03:39.112304 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
2555 23:03:39.115342 1 0 0 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
2556 23:03:39.122053 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2557 23:03:39.125408 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2558 23:03:39.128833 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2559 23:03:39.135437 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2560 23:03:39.138654 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2561 23:03:39.141895 1 0 24 | B1->B0 | 2323 3838 | 0 1 | (0 0) (0 0)
2562 23:03:39.145255 1 0 28 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
2563 23:03:39.151929 1 1 0 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
2564 23:03:39.155321 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2565 23:03:39.158664 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2566 23:03:39.165687 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2567 23:03:39.168722 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2568 23:03:39.172116 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2569 23:03:39.179168 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2570 23:03:39.182374 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2571 23:03:39.185480 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2572 23:03:39.192265 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 23:03:39.195676 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 23:03:39.198862 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2575 23:03:39.205558 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2576 23:03:39.208866 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2577 23:03:39.211955 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2578 23:03:39.215564 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2579 23:03:39.222213 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2580 23:03:39.225407 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2581 23:03:39.229122 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2582 23:03:39.235979 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2583 23:03:39.238885 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2584 23:03:39.242229 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2585 23:03:39.248759 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2586 23:03:39.252748 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2587 23:03:39.255468 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2588 23:03:39.259409 Total UI for P1: 0, mck2ui 16
2589 23:03:39.262371 best dqsien dly found for B0: ( 1, 3, 28)
2590 23:03:39.269164 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2591 23:03:39.269248 Total UI for P1: 0, mck2ui 16
2592 23:03:39.272292 best dqsien dly found for B1: ( 1, 4, 0)
2593 23:03:39.279190 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2594 23:03:39.282396 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2595 23:03:39.282479
2596 23:03:39.285539 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2597 23:03:39.289161 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2598 23:03:39.292813 [Gating] SW calibration Done
2599 23:03:39.292896 ==
2600 23:03:39.295661 Dram Type= 6, Freq= 0, CH_0, rank 0
2601 23:03:39.299113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2602 23:03:39.299197 ==
2603 23:03:39.299264 RX Vref Scan: 0
2604 23:03:39.302556
2605 23:03:39.302646 RX Vref 0 -> 0, step: 1
2606 23:03:39.302714
2607 23:03:39.306037 RX Delay -40 -> 252, step: 8
2608 23:03:39.308961 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
2609 23:03:39.312275 iDelay=200, Bit 1, Center 123 (56 ~ 191) 136
2610 23:03:39.319152 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2611 23:03:39.322337 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2612 23:03:39.325767 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2613 23:03:39.329339 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2614 23:03:39.332461 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2615 23:03:39.339140 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2616 23:03:39.342077 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2617 23:03:39.345576 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
2618 23:03:39.349124 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2619 23:03:39.352447 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2620 23:03:39.359133 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2621 23:03:39.362458 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2622 23:03:39.365727 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2623 23:03:39.369101 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2624 23:03:39.369185 ==
2625 23:03:39.372629 Dram Type= 6, Freq= 0, CH_0, rank 0
2626 23:03:39.378994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2627 23:03:39.379078 ==
2628 23:03:39.379145 DQS Delay:
2629 23:03:39.379207 DQS0 = 0, DQS1 = 0
2630 23:03:39.382136 DQM Delay:
2631 23:03:39.382219 DQM0 = 122, DQM1 = 110
2632 23:03:39.385669 DQ Delay:
2633 23:03:39.388810 DQ0 =123, DQ1 =123, DQ2 =119, DQ3 =119
2634 23:03:39.392304 DQ4 =127, DQ5 =115, DQ6 =127, DQ7 =127
2635 23:03:39.395885 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107
2636 23:03:39.398899 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2637 23:03:39.398983
2638 23:03:39.399049
2639 23:03:39.399111 ==
2640 23:03:39.402496 Dram Type= 6, Freq= 0, CH_0, rank 0
2641 23:03:39.405834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2642 23:03:39.405918 ==
2643 23:03:39.405985
2644 23:03:39.406047
2645 23:03:39.409006 TX Vref Scan disable
2646 23:03:39.412592 == TX Byte 0 ==
2647 23:03:39.416048 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2648 23:03:39.419375 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2649 23:03:39.422673 == TX Byte 1 ==
2650 23:03:39.425794 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2651 23:03:39.429130 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2652 23:03:39.429214 ==
2653 23:03:39.432413 Dram Type= 6, Freq= 0, CH_0, rank 0
2654 23:03:39.438845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2655 23:03:39.438928 ==
2656 23:03:39.449124 TX Vref=22, minBit 0, minWin=23, winSum=400
2657 23:03:39.452824 TX Vref=24, minBit 3, minWin=24, winSum=400
2658 23:03:39.455869 TX Vref=26, minBit 1, minWin=24, winSum=410
2659 23:03:39.459709 TX Vref=28, minBit 0, minWin=25, winSum=416
2660 23:03:39.462816 TX Vref=30, minBit 1, minWin=25, winSum=413
2661 23:03:39.465972 TX Vref=32, minBit 1, minWin=24, winSum=411
2662 23:03:39.472929 [TxChooseVref] Worse bit 0, Min win 25, Win sum 416, Final Vref 28
2663 23:03:39.473013
2664 23:03:39.475906 Final TX Range 1 Vref 28
2665 23:03:39.475991
2666 23:03:39.476057 ==
2667 23:03:39.479294 Dram Type= 6, Freq= 0, CH_0, rank 0
2668 23:03:39.483105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2669 23:03:39.483189 ==
2670 23:03:39.483256
2671 23:03:39.483317
2672 23:03:39.486172 TX Vref Scan disable
2673 23:03:39.489159 == TX Byte 0 ==
2674 23:03:39.493178 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2675 23:03:39.495939 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2676 23:03:39.499725 == TX Byte 1 ==
2677 23:03:39.502706 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2678 23:03:39.506243 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2679 23:03:39.506327
2680 23:03:39.509493 [DATLAT]
2681 23:03:39.509576 Freq=1200, CH0 RK0
2682 23:03:39.509642
2683 23:03:39.512694 DATLAT Default: 0xd
2684 23:03:39.512778 0, 0xFFFF, sum = 0
2685 23:03:39.516028 1, 0xFFFF, sum = 0
2686 23:03:39.516113 2, 0xFFFF, sum = 0
2687 23:03:39.519632 3, 0xFFFF, sum = 0
2688 23:03:39.519717 4, 0xFFFF, sum = 0
2689 23:03:39.523168 5, 0xFFFF, sum = 0
2690 23:03:39.523253 6, 0xFFFF, sum = 0
2691 23:03:39.525930 7, 0xFFFF, sum = 0
2692 23:03:39.526015 8, 0xFFFF, sum = 0
2693 23:03:39.529615 9, 0xFFFF, sum = 0
2694 23:03:39.529700 10, 0xFFFF, sum = 0
2695 23:03:39.532816 11, 0xFFFF, sum = 0
2696 23:03:39.532937 12, 0x0, sum = 1
2697 23:03:39.535936 13, 0x0, sum = 2
2698 23:03:39.536021 14, 0x0, sum = 3
2699 23:03:39.539779 15, 0x0, sum = 4
2700 23:03:39.539863 best_step = 13
2701 23:03:39.539930
2702 23:03:39.539993 ==
2703 23:03:39.542592 Dram Type= 6, Freq= 0, CH_0, rank 0
2704 23:03:39.549244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2705 23:03:39.549328 ==
2706 23:03:39.549395 RX Vref Scan: 1
2707 23:03:39.549491
2708 23:03:39.552898 Set Vref Range= 32 -> 127
2709 23:03:39.552982
2710 23:03:39.555790 RX Vref 32 -> 127, step: 1
2711 23:03:39.555874
2712 23:03:39.559289 RX Delay -13 -> 252, step: 4
2713 23:03:39.559372
2714 23:03:39.562573 Set Vref, RX VrefLevel [Byte0]: 32
2715 23:03:39.566320 [Byte1]: 32
2716 23:03:39.566442
2717 23:03:39.569747 Set Vref, RX VrefLevel [Byte0]: 33
2718 23:03:39.573040 [Byte1]: 33
2719 23:03:39.573170
2720 23:03:39.576273 Set Vref, RX VrefLevel [Byte0]: 34
2721 23:03:39.579399 [Byte1]: 34
2722 23:03:39.583127
2723 23:03:39.583210 Set Vref, RX VrefLevel [Byte0]: 35
2724 23:03:39.586417 [Byte1]: 35
2725 23:03:39.591013
2726 23:03:39.591096 Set Vref, RX VrefLevel [Byte0]: 36
2727 23:03:39.594348 [Byte1]: 36
2728 23:03:39.598756
2729 23:03:39.598842 Set Vref, RX VrefLevel [Byte0]: 37
2730 23:03:39.602235 [Byte1]: 37
2731 23:03:39.607124
2732 23:03:39.607207 Set Vref, RX VrefLevel [Byte0]: 38
2733 23:03:39.610296 [Byte1]: 38
2734 23:03:39.614545
2735 23:03:39.614628 Set Vref, RX VrefLevel [Byte0]: 39
2736 23:03:39.617991 [Byte1]: 39
2737 23:03:39.622675
2738 23:03:39.622761 Set Vref, RX VrefLevel [Byte0]: 40
2739 23:03:39.626361 [Byte1]: 40
2740 23:03:39.630597
2741 23:03:39.630721 Set Vref, RX VrefLevel [Byte0]: 41
2742 23:03:39.633870 [Byte1]: 41
2743 23:03:39.638366
2744 23:03:39.638511 Set Vref, RX VrefLevel [Byte0]: 42
2745 23:03:39.641935 [Byte1]: 42
2746 23:03:39.646637
2747 23:03:39.646721 Set Vref, RX VrefLevel [Byte0]: 43
2748 23:03:39.649446 [Byte1]: 43
2749 23:03:39.654088
2750 23:03:39.654172 Set Vref, RX VrefLevel [Byte0]: 44
2751 23:03:39.657595 [Byte1]: 44
2752 23:03:39.662081
2753 23:03:39.662165 Set Vref, RX VrefLevel [Byte0]: 45
2754 23:03:39.665530 [Byte1]: 45
2755 23:03:39.670111
2756 23:03:39.670194 Set Vref, RX VrefLevel [Byte0]: 46
2757 23:03:39.673664 [Byte1]: 46
2758 23:03:39.677870
2759 23:03:39.677954 Set Vref, RX VrefLevel [Byte0]: 47
2760 23:03:39.681216 [Byte1]: 47
2761 23:03:39.685767
2762 23:03:39.685850 Set Vref, RX VrefLevel [Byte0]: 48
2763 23:03:39.689247 [Byte1]: 48
2764 23:03:39.693842
2765 23:03:39.693926 Set Vref, RX VrefLevel [Byte0]: 49
2766 23:03:39.696852 [Byte1]: 49
2767 23:03:39.701772
2768 23:03:39.701856 Set Vref, RX VrefLevel [Byte0]: 50
2769 23:03:39.704676 [Byte1]: 50
2770 23:03:39.709609
2771 23:03:39.709692 Set Vref, RX VrefLevel [Byte0]: 51
2772 23:03:39.712630 [Byte1]: 51
2773 23:03:39.717568
2774 23:03:39.717651 Set Vref, RX VrefLevel [Byte0]: 52
2775 23:03:39.721267 [Byte1]: 52
2776 23:03:39.725239
2777 23:03:39.725322 Set Vref, RX VrefLevel [Byte0]: 53
2778 23:03:39.728372 [Byte1]: 53
2779 23:03:39.733188
2780 23:03:39.733303 Set Vref, RX VrefLevel [Byte0]: 54
2781 23:03:39.736720 [Byte1]: 54
2782 23:03:39.740941
2783 23:03:39.741024 Set Vref, RX VrefLevel [Byte0]: 55
2784 23:03:39.744281 [Byte1]: 55
2785 23:03:39.748994
2786 23:03:39.749077 Set Vref, RX VrefLevel [Byte0]: 56
2787 23:03:39.752427 [Byte1]: 56
2788 23:03:39.757003
2789 23:03:39.757087 Set Vref, RX VrefLevel [Byte0]: 57
2790 23:03:39.760393 [Byte1]: 57
2791 23:03:39.764561
2792 23:03:39.764647 Set Vref, RX VrefLevel [Byte0]: 58
2793 23:03:39.768037 [Byte1]: 58
2794 23:03:39.772594
2795 23:03:39.772677 Set Vref, RX VrefLevel [Byte0]: 59
2796 23:03:39.776366 [Byte1]: 59
2797 23:03:39.780841
2798 23:03:39.780925 Set Vref, RX VrefLevel [Byte0]: 60
2799 23:03:39.783903 [Byte1]: 60
2800 23:03:39.788261
2801 23:03:39.788344 Set Vref, RX VrefLevel [Byte0]: 61
2802 23:03:39.791680 [Byte1]: 61
2803 23:03:39.796380
2804 23:03:39.796463 Set Vref, RX VrefLevel [Byte0]: 62
2805 23:03:39.799558 [Byte1]: 62
2806 23:03:39.804054
2807 23:03:39.804137 Set Vref, RX VrefLevel [Byte0]: 63
2808 23:03:39.807477 [Byte1]: 63
2809 23:03:39.812368
2810 23:03:39.812452 Set Vref, RX VrefLevel [Byte0]: 64
2811 23:03:39.815571 [Byte1]: 64
2812 23:03:39.819951
2813 23:03:39.820034 Set Vref, RX VrefLevel [Byte0]: 65
2814 23:03:39.823283 [Byte1]: 65
2815 23:03:39.827710
2816 23:03:39.827794 Set Vref, RX VrefLevel [Byte0]: 66
2817 23:03:39.830968 [Byte1]: 66
2818 23:03:39.835669
2819 23:03:39.835752 Set Vref, RX VrefLevel [Byte0]: 67
2820 23:03:39.838799 [Byte1]: 67
2821 23:03:39.843679
2822 23:03:39.843762 Set Vref, RX VrefLevel [Byte0]: 68
2823 23:03:39.846951 [Byte1]: 68
2824 23:03:39.851310
2825 23:03:39.851394 Set Vref, RX VrefLevel [Byte0]: 69
2826 23:03:39.855137 [Byte1]: 69
2827 23:03:39.859474
2828 23:03:39.859558 Set Vref, RX VrefLevel [Byte0]: 70
2829 23:03:39.862750 [Byte1]: 70
2830 23:03:39.867363
2831 23:03:39.867447 Final RX Vref Byte 0 = 59 to rank0
2832 23:03:39.870835 Final RX Vref Byte 1 = 49 to rank0
2833 23:03:39.873787 Final RX Vref Byte 0 = 59 to rank1
2834 23:03:39.877471 Final RX Vref Byte 1 = 49 to rank1==
2835 23:03:39.880885 Dram Type= 6, Freq= 0, CH_0, rank 0
2836 23:03:39.887327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2837 23:03:39.887411 ==
2838 23:03:39.887478 DQS Delay:
2839 23:03:39.887541 DQS0 = 0, DQS1 = 0
2840 23:03:39.890661 DQM Delay:
2841 23:03:39.890745 DQM0 = 122, DQM1 = 109
2842 23:03:39.893837 DQ Delay:
2843 23:03:39.897482 DQ0 =122, DQ1 =122, DQ2 =118, DQ3 =120
2844 23:03:39.900446 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128
2845 23:03:39.903984 DQ8 =100, DQ9 =94, DQ10 =110, DQ11 =106
2846 23:03:39.907173 DQ12 =116, DQ13 =110, DQ14 =122, DQ15 =116
2847 23:03:39.907256
2848 23:03:39.907323
2849 23:03:39.913877 [DQSOSCAuto] RK0, (LSB)MR18= 0xe0b, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 404 ps
2850 23:03:39.917202 CH0 RK0: MR19=404, MR18=E0B
2851 23:03:39.923712 CH0_RK0: MR19=0x404, MR18=0xE0B, DQSOSC=404, MR23=63, INC=40, DEC=26
2852 23:03:39.923796
2853 23:03:39.927003 ----->DramcWriteLeveling(PI) begin...
2854 23:03:39.927088 ==
2855 23:03:39.930415 Dram Type= 6, Freq= 0, CH_0, rank 1
2856 23:03:39.934715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2857 23:03:39.934799 ==
2858 23:03:39.937075 Write leveling (Byte 0): 35 => 35
2859 23:03:39.940576 Write leveling (Byte 1): 30 => 30
2860 23:03:39.944056 DramcWriteLeveling(PI) end<-----
2861 23:03:39.944129
2862 23:03:39.944211 ==
2863 23:03:39.947377 Dram Type= 6, Freq= 0, CH_0, rank 1
2864 23:03:39.950723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2865 23:03:39.953912 ==
2866 23:03:39.954016 [Gating] SW mode calibration
2867 23:03:39.963912 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2868 23:03:39.967377 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2869 23:03:39.970871 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2870 23:03:39.977550 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2871 23:03:39.980681 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2872 23:03:39.984255 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2873 23:03:39.990845 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2874 23:03:39.994246 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2875 23:03:39.997650 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2876 23:03:40.004273 0 15 28 | B1->B0 | 3030 2a2a | 0 1 | (0 0) (1 0)
2877 23:03:40.007773 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2878 23:03:40.011612 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2879 23:03:40.014555 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2880 23:03:40.021137 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2881 23:03:40.024568 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2882 23:03:40.028124 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2883 23:03:40.034240 1 0 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
2884 23:03:40.038034 1 0 28 | B1->B0 | 3939 4141 | 0 0 | (0 0) (0 0)
2885 23:03:40.041162 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2886 23:03:40.047617 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2887 23:03:40.051195 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2888 23:03:40.054227 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2889 23:03:40.061174 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2890 23:03:40.064724 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2891 23:03:40.067678 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2892 23:03:40.074228 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2893 23:03:40.077560 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
2894 23:03:40.081312 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 23:03:40.087920 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2896 23:03:40.091004 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2897 23:03:40.094769 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2898 23:03:40.097756 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2899 23:03:40.104337 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2900 23:03:40.107557 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2901 23:03:40.110981 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2902 23:03:40.117636 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2903 23:03:40.121263 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2904 23:03:40.124678 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2905 23:03:40.131139 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2906 23:03:40.134318 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2907 23:03:40.137808 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2908 23:03:40.144524 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2909 23:03:40.147900 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2910 23:03:40.151327 Total UI for P1: 0, mck2ui 16
2911 23:03:40.154882 best dqsien dly found for B0: ( 1, 3, 26)
2912 23:03:40.157975 Total UI for P1: 0, mck2ui 16
2913 23:03:40.161673 best dqsien dly found for B1: ( 1, 3, 28)
2914 23:03:40.165011 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2915 23:03:40.168347 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2916 23:03:40.168449
2917 23:03:40.171076 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2918 23:03:40.174819 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2919 23:03:40.177956 [Gating] SW calibration Done
2920 23:03:40.178054 ==
2921 23:03:40.181259 Dram Type= 6, Freq= 0, CH_0, rank 1
2922 23:03:40.184647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2923 23:03:40.184742 ==
2924 23:03:40.187902 RX Vref Scan: 0
2925 23:03:40.187996
2926 23:03:40.191716 RX Vref 0 -> 0, step: 1
2927 23:03:40.191785
2928 23:03:40.191846 RX Delay -40 -> 252, step: 8
2929 23:03:40.197796 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2930 23:03:40.201261 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2931 23:03:40.205110 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2932 23:03:40.208045 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2933 23:03:40.211071 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2934 23:03:40.217713 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2935 23:03:40.221326 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2936 23:03:40.224395 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2937 23:03:40.228041 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2938 23:03:40.231351 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2939 23:03:40.234869 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2940 23:03:40.241592 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2941 23:03:40.244489 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2942 23:03:40.248084 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2943 23:03:40.251528 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2944 23:03:40.258173 iDelay=200, Bit 15, Center 111 (48 ~ 175) 128
2945 23:03:40.258281 ==
2946 23:03:40.261387 Dram Type= 6, Freq= 0, CH_0, rank 1
2947 23:03:40.264630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2948 23:03:40.264736 ==
2949 23:03:40.264828 DQS Delay:
2950 23:03:40.268183 DQS0 = 0, DQS1 = 0
2951 23:03:40.268280 DQM Delay:
2952 23:03:40.271560 DQM0 = 120, DQM1 = 108
2953 23:03:40.271666 DQ Delay:
2954 23:03:40.274818 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2955 23:03:40.278537 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2956 23:03:40.281345 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
2957 23:03:40.284770 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2958 23:03:40.284874
2959 23:03:40.284963
2960 23:03:40.285055 ==
2961 23:03:40.288378 Dram Type= 6, Freq= 0, CH_0, rank 1
2962 23:03:40.294611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2963 23:03:40.294709 ==
2964 23:03:40.294799
2965 23:03:40.294895
2966 23:03:40.294982 TX Vref Scan disable
2967 23:03:40.298152 == TX Byte 0 ==
2968 23:03:40.301489 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2969 23:03:40.304771 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2970 23:03:40.308018 == TX Byte 1 ==
2971 23:03:40.311686 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2972 23:03:40.315290 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2973 23:03:40.318308 ==
2974 23:03:40.321743 Dram Type= 6, Freq= 0, CH_0, rank 1
2975 23:03:40.324910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2976 23:03:40.325014 ==
2977 23:03:40.336839 TX Vref=22, minBit 0, minWin=24, winSum=396
2978 23:03:40.339827 TX Vref=24, minBit 0, minWin=24, winSum=404
2979 23:03:40.342866 TX Vref=26, minBit 0, minWin=24, winSum=407
2980 23:03:40.346909 TX Vref=28, minBit 7, minWin=24, winSum=413
2981 23:03:40.349838 TX Vref=30, minBit 1, minWin=24, winSum=413
2982 23:03:40.353054 TX Vref=32, minBit 1, minWin=25, winSum=416
2983 23:03:40.359945 [TxChooseVref] Worse bit 1, Min win 25, Win sum 416, Final Vref 32
2984 23:03:40.360027
2985 23:03:40.363273 Final TX Range 1 Vref 32
2986 23:03:40.363344
2987 23:03:40.363413 ==
2988 23:03:40.366218 Dram Type= 6, Freq= 0, CH_0, rank 1
2989 23:03:40.370170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2990 23:03:40.370248 ==
2991 23:03:40.370338
2992 23:03:40.373085
2993 23:03:40.373156 TX Vref Scan disable
2994 23:03:40.376439 == TX Byte 0 ==
2995 23:03:40.379706 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2996 23:03:40.383235 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2997 23:03:40.386244 == TX Byte 1 ==
2998 23:03:40.389732 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2999 23:03:40.392943 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3000 23:03:40.393047
3001 23:03:40.396256 [DATLAT]
3002 23:03:40.396350 Freq=1200, CH0 RK1
3003 23:03:40.396448
3004 23:03:40.399651 DATLAT Default: 0xd
3005 23:03:40.399721 0, 0xFFFF, sum = 0
3006 23:03:40.403149 1, 0xFFFF, sum = 0
3007 23:03:40.403250 2, 0xFFFF, sum = 0
3008 23:03:40.406468 3, 0xFFFF, sum = 0
3009 23:03:40.406541 4, 0xFFFF, sum = 0
3010 23:03:40.409981 5, 0xFFFF, sum = 0
3011 23:03:40.410082 6, 0xFFFF, sum = 0
3012 23:03:40.413253 7, 0xFFFF, sum = 0
3013 23:03:40.416595 8, 0xFFFF, sum = 0
3014 23:03:40.416702 9, 0xFFFF, sum = 0
3015 23:03:40.419848 10, 0xFFFF, sum = 0
3016 23:03:40.419946 11, 0xFFFF, sum = 0
3017 23:03:40.423160 12, 0x0, sum = 1
3018 23:03:40.423243 13, 0x0, sum = 2
3019 23:03:40.423305 14, 0x0, sum = 3
3020 23:03:40.426330 15, 0x0, sum = 4
3021 23:03:40.426440 best_step = 13
3022 23:03:40.426529
3023 23:03:40.429959 ==
3024 23:03:40.430063 Dram Type= 6, Freq= 0, CH_0, rank 1
3025 23:03:40.436541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3026 23:03:40.436655 ==
3027 23:03:40.436759 RX Vref Scan: 0
3028 23:03:40.436859
3029 23:03:40.439809 RX Vref 0 -> 0, step: 1
3030 23:03:40.439911
3031 23:03:40.443364 RX Delay -21 -> 252, step: 4
3032 23:03:40.446827 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3033 23:03:40.449907 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3034 23:03:40.456444 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3035 23:03:40.460084 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3036 23:03:40.463213 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3037 23:03:40.466517 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3038 23:03:40.470000 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3039 23:03:40.476594 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
3040 23:03:40.479890 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3041 23:03:40.483117 iDelay=195, Bit 9, Center 94 (31 ~ 158) 128
3042 23:03:40.486933 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3043 23:03:40.490868 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3044 23:03:40.496422 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3045 23:03:40.499726 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3046 23:03:40.503480 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3047 23:03:40.506294 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3048 23:03:40.506432 ==
3049 23:03:40.510229 Dram Type= 6, Freq= 0, CH_0, rank 1
3050 23:03:40.516852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3051 23:03:40.516961 ==
3052 23:03:40.517063 DQS Delay:
3053 23:03:40.517171 DQS0 = 0, DQS1 = 0
3054 23:03:40.519823 DQM Delay:
3055 23:03:40.519928 DQM0 = 119, DQM1 = 107
3056 23:03:40.523042 DQ Delay:
3057 23:03:40.526785 DQ0 =118, DQ1 =122, DQ2 =118, DQ3 =112
3058 23:03:40.530075 DQ4 =122, DQ5 =114, DQ6 =126, DQ7 =124
3059 23:03:40.533153 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =106
3060 23:03:40.536517 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =114
3061 23:03:40.536627
3062 23:03:40.536730
3063 23:03:40.543642 [DQSOSCAuto] RK1, (LSB)MR18= 0xdf5, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 405 ps
3064 23:03:40.546957 CH0 RK1: MR19=403, MR18=DF5
3065 23:03:40.553568 CH0_RK1: MR19=0x403, MR18=0xDF5, DQSOSC=405, MR23=63, INC=39, DEC=26
3066 23:03:40.556562 [RxdqsGatingPostProcess] freq 1200
3067 23:03:40.563507 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3068 23:03:40.563587 best DQS0 dly(2T, 0.5T) = (0, 11)
3069 23:03:40.566802 best DQS1 dly(2T, 0.5T) = (0, 12)
3070 23:03:40.569987 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3071 23:03:40.573433 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3072 23:03:40.576876 best DQS0 dly(2T, 0.5T) = (0, 11)
3073 23:03:40.580399 best DQS1 dly(2T, 0.5T) = (0, 11)
3074 23:03:40.583456 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3075 23:03:40.586478 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3076 23:03:40.589826 Pre-setting of DQS Precalculation
3077 23:03:40.593860 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3078 23:03:40.597105 ==
3079 23:03:40.597207 Dram Type= 6, Freq= 0, CH_1, rank 0
3080 23:03:40.603437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3081 23:03:40.603515 ==
3082 23:03:40.607409 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3083 23:03:40.613442 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3084 23:03:40.622261 [CA 0] Center 37 (7~67) winsize 61
3085 23:03:40.625691 [CA 1] Center 37 (7~68) winsize 62
3086 23:03:40.628995 [CA 2] Center 34 (4~65) winsize 62
3087 23:03:40.632638 [CA 3] Center 33 (3~64) winsize 62
3088 23:03:40.635712 [CA 4] Center 33 (3~64) winsize 62
3089 23:03:40.639083 [CA 5] Center 33 (3~63) winsize 61
3090 23:03:40.639188
3091 23:03:40.642362 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3092 23:03:40.642484
3093 23:03:40.646053 [CATrainingPosCal] consider 1 rank data
3094 23:03:40.649132 u2DelayCellTimex100 = 270/100 ps
3095 23:03:40.652492 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3096 23:03:40.656192 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3097 23:03:40.659060 CA2 delay=34 (4~65),Diff = 1 PI (4 cell)
3098 23:03:40.665804 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3099 23:03:40.669250 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3100 23:03:40.672678 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3101 23:03:40.672778
3102 23:03:40.675745 CA PerBit enable=1, Macro0, CA PI delay=33
3103 23:03:40.675842
3104 23:03:40.679242 [CBTSetCACLKResult] CA Dly = 33
3105 23:03:40.679346 CS Dly: 5 (0~36)
3106 23:03:40.679436 ==
3107 23:03:40.682636 Dram Type= 6, Freq= 0, CH_1, rank 1
3108 23:03:40.689335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3109 23:03:40.689435 ==
3110 23:03:40.692700 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3111 23:03:40.699275 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3112 23:03:40.707906 [CA 0] Center 38 (8~68) winsize 61
3113 23:03:40.711741 [CA 1] Center 37 (7~68) winsize 62
3114 23:03:40.714888 [CA 2] Center 35 (4~66) winsize 63
3115 23:03:40.718151 [CA 3] Center 34 (4~65) winsize 62
3116 23:03:40.721332 [CA 4] Center 34 (4~64) winsize 61
3117 23:03:40.724831 [CA 5] Center 33 (3~64) winsize 62
3118 23:03:40.724903
3119 23:03:40.728053 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3120 23:03:40.728148
3121 23:03:40.731148 [CATrainingPosCal] consider 2 rank data
3122 23:03:40.734877 u2DelayCellTimex100 = 270/100 ps
3123 23:03:40.738178 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3124 23:03:40.741494 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3125 23:03:40.747831 CA2 delay=34 (4~65),Diff = 1 PI (4 cell)
3126 23:03:40.751256 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3127 23:03:40.754839 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3128 23:03:40.758121 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3129 23:03:40.758217
3130 23:03:40.761607 CA PerBit enable=1, Macro0, CA PI delay=33
3131 23:03:40.761682
3132 23:03:40.765340 [CBTSetCACLKResult] CA Dly = 33
3133 23:03:40.765437 CS Dly: 6 (0~38)
3134 23:03:40.765527
3135 23:03:40.768357 ----->DramcWriteLeveling(PI) begin...
3136 23:03:40.768464 ==
3137 23:03:40.771345 Dram Type= 6, Freq= 0, CH_1, rank 0
3138 23:03:40.778404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3139 23:03:40.778507 ==
3140 23:03:40.781406 Write leveling (Byte 0): 25 => 25
3141 23:03:40.785080 Write leveling (Byte 1): 28 => 28
3142 23:03:40.785186 DramcWriteLeveling(PI) end<-----
3143 23:03:40.785279
3144 23:03:40.788268 ==
3145 23:03:40.791568 Dram Type= 6, Freq= 0, CH_1, rank 0
3146 23:03:40.794942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3147 23:03:40.795042 ==
3148 23:03:40.798410 [Gating] SW mode calibration
3149 23:03:40.804671 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3150 23:03:40.808035 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3151 23:03:40.814960 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3152 23:03:40.818262 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3153 23:03:40.821799 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3154 23:03:40.828511 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3155 23:03:40.831701 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3156 23:03:40.835160 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3157 23:03:40.841587 0 15 24 | B1->B0 | 2727 2424 | 0 0 | (0 0) (1 0)
3158 23:03:40.845102 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3159 23:03:40.848309 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3160 23:03:40.854945 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3161 23:03:40.858495 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3162 23:03:40.861942 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3163 23:03:40.864942 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3164 23:03:40.871635 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3165 23:03:40.875149 1 0 24 | B1->B0 | 4040 4545 | 0 0 | (0 0) (0 0)
3166 23:03:40.878947 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3167 23:03:40.885236 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3168 23:03:40.888423 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3169 23:03:40.891864 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3170 23:03:40.898378 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3171 23:03:40.901968 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3172 23:03:40.905069 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3173 23:03:40.911565 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3174 23:03:40.915357 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3175 23:03:40.918325 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 23:03:40.925250 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 23:03:40.928510 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3178 23:03:40.931635 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3179 23:03:40.938596 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3180 23:03:40.942107 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3181 23:03:40.945063 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3182 23:03:40.949003 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3183 23:03:40.955638 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3184 23:03:40.958419 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3185 23:03:40.961781 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3186 23:03:40.968825 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3187 23:03:40.971866 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3188 23:03:40.975263 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3189 23:03:40.982105 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3190 23:03:40.985106 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3191 23:03:40.988654 Total UI for P1: 0, mck2ui 16
3192 23:03:40.992042 best dqsien dly found for B0: ( 1, 3, 22)
3193 23:03:40.995345 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3194 23:03:40.998483 Total UI for P1: 0, mck2ui 16
3195 23:03:41.002111 best dqsien dly found for B1: ( 1, 3, 24)
3196 23:03:41.005262 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3197 23:03:41.008832 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3198 23:03:41.008929
3199 23:03:41.012153 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3200 23:03:41.019102 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3201 23:03:41.019176 [Gating] SW calibration Done
3202 23:03:41.019238 ==
3203 23:03:41.022034 Dram Type= 6, Freq= 0, CH_1, rank 0
3204 23:03:41.028856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3205 23:03:41.028956 ==
3206 23:03:41.029051 RX Vref Scan: 0
3207 23:03:41.029143
3208 23:03:41.032383 RX Vref 0 -> 0, step: 1
3209 23:03:41.032453
3210 23:03:41.035487 RX Delay -40 -> 252, step: 8
3211 23:03:41.038513 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3212 23:03:41.042044 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3213 23:03:41.045298 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3214 23:03:41.052021 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3215 23:03:41.055431 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3216 23:03:41.059122 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3217 23:03:41.062251 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3218 23:03:41.065433 iDelay=200, Bit 7, Center 119 (56 ~ 183) 128
3219 23:03:41.068629 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3220 23:03:41.075335 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3221 23:03:41.079002 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3222 23:03:41.082282 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3223 23:03:41.085794 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3224 23:03:41.088732 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3225 23:03:41.095566 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3226 23:03:41.098801 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3227 23:03:41.098883 ==
3228 23:03:41.102221 Dram Type= 6, Freq= 0, CH_1, rank 0
3229 23:03:41.105711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3230 23:03:41.105793 ==
3231 23:03:41.108949 DQS Delay:
3232 23:03:41.109031 DQS0 = 0, DQS1 = 0
3233 23:03:41.109097 DQM Delay:
3234 23:03:41.112114 DQM0 = 119, DQM1 = 113
3235 23:03:41.112196 DQ Delay:
3236 23:03:41.115556 DQ0 =123, DQ1 =115, DQ2 =111, DQ3 =119
3237 23:03:41.119371 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =119
3238 23:03:41.122116 DQ8 =99, DQ9 =103, DQ10 =115, DQ11 =107
3239 23:03:41.128775 DQ12 =123, DQ13 =123, DQ14 =119, DQ15 =119
3240 23:03:41.128858
3241 23:03:41.128923
3242 23:03:41.128984 ==
3243 23:03:41.132277 Dram Type= 6, Freq= 0, CH_1, rank 0
3244 23:03:41.136053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3245 23:03:41.136137 ==
3246 23:03:41.136203
3247 23:03:41.136265
3248 23:03:41.138805 TX Vref Scan disable
3249 23:03:41.138887 == TX Byte 0 ==
3250 23:03:41.145782 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3251 23:03:41.149111 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3252 23:03:41.149194 == TX Byte 1 ==
3253 23:03:41.155966 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3254 23:03:41.159258 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3255 23:03:41.159341 ==
3256 23:03:41.162274 Dram Type= 6, Freq= 0, CH_1, rank 0
3257 23:03:41.165901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3258 23:03:41.165984 ==
3259 23:03:41.178286 TX Vref=22, minBit 8, minWin=24, winSum=402
3260 23:03:41.181313 TX Vref=24, minBit 1, minWin=24, winSum=404
3261 23:03:41.184771 TX Vref=26, minBit 1, minWin=25, winSum=407
3262 23:03:41.187962 TX Vref=28, minBit 8, minWin=25, winSum=413
3263 23:03:41.191640 TX Vref=30, minBit 8, minWin=25, winSum=421
3264 23:03:41.194647 TX Vref=32, minBit 9, minWin=25, winSum=421
3265 23:03:41.201411 [TxChooseVref] Worse bit 8, Min win 25, Win sum 421, Final Vref 30
3266 23:03:41.201495
3267 23:03:41.205032 Final TX Range 1 Vref 30
3268 23:03:41.205116
3269 23:03:41.205182 ==
3270 23:03:41.207993 Dram Type= 6, Freq= 0, CH_1, rank 0
3271 23:03:41.211635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3272 23:03:41.211718 ==
3273 23:03:41.211784
3274 23:03:41.211844
3275 23:03:41.214952 TX Vref Scan disable
3276 23:03:41.218347 == TX Byte 0 ==
3277 23:03:41.221835 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3278 23:03:41.225003 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3279 23:03:41.228518 == TX Byte 1 ==
3280 23:03:41.231765 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3281 23:03:41.234899 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3282 23:03:41.234982
3283 23:03:41.238228 [DATLAT]
3284 23:03:41.238310 Freq=1200, CH1 RK0
3285 23:03:41.238375
3286 23:03:41.241645 DATLAT Default: 0xd
3287 23:03:41.241728 0, 0xFFFF, sum = 0
3288 23:03:41.244912 1, 0xFFFF, sum = 0
3289 23:03:41.244995 2, 0xFFFF, sum = 0
3290 23:03:41.248384 3, 0xFFFF, sum = 0
3291 23:03:41.248484 4, 0xFFFF, sum = 0
3292 23:03:41.251638 5, 0xFFFF, sum = 0
3293 23:03:41.251723 6, 0xFFFF, sum = 0
3294 23:03:41.254816 7, 0xFFFF, sum = 0
3295 23:03:41.254911 8, 0xFFFF, sum = 0
3296 23:03:41.258270 9, 0xFFFF, sum = 0
3297 23:03:41.258354 10, 0xFFFF, sum = 0
3298 23:03:41.261535 11, 0xFFFF, sum = 0
3299 23:03:41.261618 12, 0x0, sum = 1
3300 23:03:41.265088 13, 0x0, sum = 2
3301 23:03:41.265172 14, 0x0, sum = 3
3302 23:03:41.268298 15, 0x0, sum = 4
3303 23:03:41.268382 best_step = 13
3304 23:03:41.268447
3305 23:03:41.268507 ==
3306 23:03:41.271730 Dram Type= 6, Freq= 0, CH_1, rank 0
3307 23:03:41.278061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3308 23:03:41.278144 ==
3309 23:03:41.278228 RX Vref Scan: 1
3310 23:03:41.278289
3311 23:03:41.281627 Set Vref Range= 32 -> 127
3312 23:03:41.281708
3313 23:03:41.284751 RX Vref 32 -> 127, step: 1
3314 23:03:41.284832
3315 23:03:41.288090 RX Delay -13 -> 252, step: 4
3316 23:03:41.288171
3317 23:03:41.291446 Set Vref, RX VrefLevel [Byte0]: 32
3318 23:03:41.294676 [Byte1]: 32
3319 23:03:41.294756
3320 23:03:41.298279 Set Vref, RX VrefLevel [Byte0]: 33
3321 23:03:41.301435 [Byte1]: 33
3322 23:03:41.301516
3323 23:03:41.304657 Set Vref, RX VrefLevel [Byte0]: 34
3324 23:03:41.308232 [Byte1]: 34
3325 23:03:41.311975
3326 23:03:41.312055 Set Vref, RX VrefLevel [Byte0]: 35
3327 23:03:41.315383 [Byte1]: 35
3328 23:03:41.320263
3329 23:03:41.320343 Set Vref, RX VrefLevel [Byte0]: 36
3330 23:03:41.323343 [Byte1]: 36
3331 23:03:41.327948
3332 23:03:41.328028 Set Vref, RX VrefLevel [Byte0]: 37
3333 23:03:41.331229 [Byte1]: 37
3334 23:03:41.335684
3335 23:03:41.335764 Set Vref, RX VrefLevel [Byte0]: 38
3336 23:03:41.338874 [Byte1]: 38
3337 23:03:41.343843
3338 23:03:41.343923 Set Vref, RX VrefLevel [Byte0]: 39
3339 23:03:41.347092 [Byte1]: 39
3340 23:03:41.351541
3341 23:03:41.351622 Set Vref, RX VrefLevel [Byte0]: 40
3342 23:03:41.354580 [Byte1]: 40
3343 23:03:41.359460
3344 23:03:41.359540 Set Vref, RX VrefLevel [Byte0]: 41
3345 23:03:41.362766 [Byte1]: 41
3346 23:03:41.367266
3347 23:03:41.367348 Set Vref, RX VrefLevel [Byte0]: 42
3348 23:03:41.370330 [Byte1]: 42
3349 23:03:41.375284
3350 23:03:41.375364 Set Vref, RX VrefLevel [Byte0]: 43
3351 23:03:41.378344 [Byte1]: 43
3352 23:03:41.382985
3353 23:03:41.383065 Set Vref, RX VrefLevel [Byte0]: 44
3354 23:03:41.386117 [Byte1]: 44
3355 23:03:41.391443
3356 23:03:41.391526 Set Vref, RX VrefLevel [Byte0]: 45
3357 23:03:41.394346 [Byte1]: 45
3358 23:03:41.399197
3359 23:03:41.399277 Set Vref, RX VrefLevel [Byte0]: 46
3360 23:03:41.401992 [Byte1]: 46
3361 23:03:41.406860
3362 23:03:41.406940 Set Vref, RX VrefLevel [Byte0]: 47
3363 23:03:41.410093 [Byte1]: 47
3364 23:03:41.414493
3365 23:03:41.414573 Set Vref, RX VrefLevel [Byte0]: 48
3366 23:03:41.417871 [Byte1]: 48
3367 23:03:41.422516
3368 23:03:41.422597 Set Vref, RX VrefLevel [Byte0]: 49
3369 23:03:41.426149 [Byte1]: 49
3370 23:03:41.430219
3371 23:03:41.430301 Set Vref, RX VrefLevel [Byte0]: 50
3372 23:03:41.433831 [Byte1]: 50
3373 23:03:41.438177
3374 23:03:41.438259 Set Vref, RX VrefLevel [Byte0]: 51
3375 23:03:41.441533 [Byte1]: 51
3376 23:03:41.445842
3377 23:03:41.445925 Set Vref, RX VrefLevel [Byte0]: 52
3378 23:03:41.449436 [Byte1]: 52
3379 23:03:41.453992
3380 23:03:41.454075 Set Vref, RX VrefLevel [Byte0]: 53
3381 23:03:41.457316 [Byte1]: 53
3382 23:03:41.461817
3383 23:03:41.461899 Set Vref, RX VrefLevel [Byte0]: 54
3384 23:03:41.465106 [Byte1]: 54
3385 23:03:41.469916
3386 23:03:41.469999 Set Vref, RX VrefLevel [Byte0]: 55
3387 23:03:41.473196 [Byte1]: 55
3388 23:03:41.477762
3389 23:03:41.477845 Set Vref, RX VrefLevel [Byte0]: 56
3390 23:03:41.480824 [Byte1]: 56
3391 23:03:41.485592
3392 23:03:41.485675 Set Vref, RX VrefLevel [Byte0]: 57
3393 23:03:41.488919 [Byte1]: 57
3394 23:03:41.493302
3395 23:03:41.493376 Set Vref, RX VrefLevel [Byte0]: 58
3396 23:03:41.496916 [Byte1]: 58
3397 23:03:41.501332
3398 23:03:41.501406 Set Vref, RX VrefLevel [Byte0]: 59
3399 23:03:41.504677 [Byte1]: 59
3400 23:03:41.509342
3401 23:03:41.509421 Set Vref, RX VrefLevel [Byte0]: 60
3402 23:03:41.512465 [Byte1]: 60
3403 23:03:41.516945
3404 23:03:41.517017 Set Vref, RX VrefLevel [Byte0]: 61
3405 23:03:41.520436 [Byte1]: 61
3406 23:03:41.524857
3407 23:03:41.524929 Set Vref, RX VrefLevel [Byte0]: 62
3408 23:03:41.528024 [Byte1]: 62
3409 23:03:41.533088
3410 23:03:41.533160 Set Vref, RX VrefLevel [Byte0]: 63
3411 23:03:41.535926 [Byte1]: 63
3412 23:03:41.540933
3413 23:03:41.541007 Set Vref, RX VrefLevel [Byte0]: 64
3414 23:03:41.543851 [Byte1]: 64
3415 23:03:41.548427
3416 23:03:41.548506 Set Vref, RX VrefLevel [Byte0]: 65
3417 23:03:41.551804 [Byte1]: 65
3418 23:03:41.556647
3419 23:03:41.556724 Set Vref, RX VrefLevel [Byte0]: 66
3420 23:03:41.559754 [Byte1]: 66
3421 23:03:41.564416
3422 23:03:41.564488 Set Vref, RX VrefLevel [Byte0]: 67
3423 23:03:41.567772 [Byte1]: 67
3424 23:03:41.572514
3425 23:03:41.572588 Set Vref, RX VrefLevel [Byte0]: 68
3426 23:03:41.575704 [Byte1]: 68
3427 23:03:41.580518
3428 23:03:41.580590 Final RX Vref Byte 0 = 50 to rank0
3429 23:03:41.583434 Final RX Vref Byte 1 = 52 to rank0
3430 23:03:41.586822 Final RX Vref Byte 0 = 50 to rank1
3431 23:03:41.590304 Final RX Vref Byte 1 = 52 to rank1==
3432 23:03:41.593431 Dram Type= 6, Freq= 0, CH_1, rank 0
3433 23:03:41.600479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3434 23:03:41.600555 ==
3435 23:03:41.600619 DQS Delay:
3436 23:03:41.600677 DQS0 = 0, DQS1 = 0
3437 23:03:41.603433 DQM Delay:
3438 23:03:41.603505 DQM0 = 119, DQM1 = 112
3439 23:03:41.606870 DQ Delay:
3440 23:03:41.609980 DQ0 =122, DQ1 =112, DQ2 =112, DQ3 =118
3441 23:03:41.613722 DQ4 =118, DQ5 =128, DQ6 =128, DQ7 =116
3442 23:03:41.617224 DQ8 =102, DQ9 =100, DQ10 =114, DQ11 =106
3443 23:03:41.620047 DQ12 =122, DQ13 =118, DQ14 =120, DQ15 =118
3444 23:03:41.620119
3445 23:03:41.620181
3446 23:03:41.626713 [DQSOSCAuto] RK0, (LSB)MR18= 0x215, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 409 ps
3447 23:03:41.630341 CH1 RK0: MR19=404, MR18=215
3448 23:03:41.637155 CH1_RK0: MR19=0x404, MR18=0x215, DQSOSC=401, MR23=63, INC=40, DEC=27
3449 23:03:41.637233
3450 23:03:41.640145 ----->DramcWriteLeveling(PI) begin...
3451 23:03:41.640219 ==
3452 23:03:41.643501 Dram Type= 6, Freq= 0, CH_1, rank 1
3453 23:03:41.647149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3454 23:03:41.647227 ==
3455 23:03:41.650476 Write leveling (Byte 0): 25 => 25
3456 23:03:41.653687 Write leveling (Byte 1): 29 => 29
3457 23:03:41.656874 DramcWriteLeveling(PI) end<-----
3458 23:03:41.656955
3459 23:03:41.657019 ==
3460 23:03:41.660443 Dram Type= 6, Freq= 0, CH_1, rank 1
3461 23:03:41.663496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3462 23:03:41.667012 ==
3463 23:03:41.667082 [Gating] SW mode calibration
3464 23:03:41.673869 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3465 23:03:41.680666 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3466 23:03:41.683655 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3467 23:03:41.690611 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3468 23:03:41.693655 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3469 23:03:41.697385 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3470 23:03:41.704172 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3471 23:03:41.707140 0 15 20 | B1->B0 | 3333 3434 | 1 1 | (1 0) (1 1)
3472 23:03:41.710706 0 15 24 | B1->B0 | 2828 3232 | 0 1 | (1 0) (1 0)
3473 23:03:41.717325 0 15 28 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
3474 23:03:41.720760 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3475 23:03:41.723829 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3476 23:03:41.727519 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3477 23:03:41.733858 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3478 23:03:41.737473 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3479 23:03:41.740685 1 0 20 | B1->B0 | 2929 2323 | 0 0 | (1 1) (0 0)
3480 23:03:41.747159 1 0 24 | B1->B0 | 4444 2b2b | 0 1 | (0 0) (0 0)
3481 23:03:41.750666 1 0 28 | B1->B0 | 4646 3f3f | 0 1 | (0 0) (0 0)
3482 23:03:41.753878 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3483 23:03:41.760510 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3484 23:03:41.764003 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3485 23:03:41.767277 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3486 23:03:41.773937 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3487 23:03:41.777208 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3488 23:03:41.780379 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3489 23:03:41.787364 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3490 23:03:41.790341 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3491 23:03:41.793748 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 23:03:41.800526 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3493 23:03:41.803813 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3494 23:03:41.807313 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3495 23:03:41.813973 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3496 23:03:41.817052 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3497 23:03:41.820721 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3498 23:03:41.824002 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3499 23:03:41.830939 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3500 23:03:41.834126 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3501 23:03:41.837090 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3502 23:03:41.844103 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3503 23:03:41.847359 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3504 23:03:41.850234 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3505 23:03:41.857092 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3506 23:03:41.860630 Total UI for P1: 0, mck2ui 16
3507 23:03:41.863767 best dqsien dly found for B0: ( 1, 3, 24)
3508 23:03:41.863850 Total UI for P1: 0, mck2ui 16
3509 23:03:41.870801 best dqsien dly found for B1: ( 1, 3, 24)
3510 23:03:41.873830 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3511 23:03:41.876959 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3512 23:03:41.877040
3513 23:03:41.880495 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3514 23:03:41.883943 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3515 23:03:41.887221 [Gating] SW calibration Done
3516 23:03:41.887339 ==
3517 23:03:41.890400 Dram Type= 6, Freq= 0, CH_1, rank 1
3518 23:03:41.894111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3519 23:03:41.894188 ==
3520 23:03:41.896893 RX Vref Scan: 0
3521 23:03:41.896970
3522 23:03:41.897034 RX Vref 0 -> 0, step: 1
3523 23:03:41.897092
3524 23:03:41.900439 RX Delay -40 -> 252, step: 8
3525 23:03:41.903748 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3526 23:03:41.910082 iDelay=200, Bit 1, Center 111 (48 ~ 175) 128
3527 23:03:41.913446 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3528 23:03:41.916904 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3529 23:03:41.920375 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
3530 23:03:41.923533 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3531 23:03:41.930166 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3532 23:03:41.933878 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3533 23:03:41.936787 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3534 23:03:41.940518 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3535 23:03:41.943307 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3536 23:03:41.950202 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3537 23:03:41.953358 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3538 23:03:41.956963 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3539 23:03:41.960015 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3540 23:03:41.966673 iDelay=200, Bit 15, Center 123 (48 ~ 199) 152
3541 23:03:41.966750 ==
3542 23:03:41.970134 Dram Type= 6, Freq= 0, CH_1, rank 1
3543 23:03:41.974141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3544 23:03:41.974218 ==
3545 23:03:41.974282 DQS Delay:
3546 23:03:41.976788 DQS0 = 0, DQS1 = 0
3547 23:03:41.976858 DQM Delay:
3548 23:03:41.979794 DQM0 = 120, DQM1 = 113
3549 23:03:41.979864 DQ Delay:
3550 23:03:41.983386 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =119
3551 23:03:41.986583 DQ4 =123, DQ5 =131, DQ6 =127, DQ7 =115
3552 23:03:41.990289 DQ8 =99, DQ9 =103, DQ10 =115, DQ11 =107
3553 23:03:41.993512 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =123
3554 23:03:41.993590
3555 23:03:41.993655
3556 23:03:41.993714 ==
3557 23:03:41.996721 Dram Type= 6, Freq= 0, CH_1, rank 1
3558 23:03:42.003316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3559 23:03:42.003388 ==
3560 23:03:42.003453
3561 23:03:42.003512
3562 23:03:42.003568 TX Vref Scan disable
3563 23:03:42.006851 == TX Byte 0 ==
3564 23:03:42.010397 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3565 23:03:42.013550 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3566 23:03:42.017106 == TX Byte 1 ==
3567 23:03:42.020613 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3568 23:03:42.027002 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3569 23:03:42.027074 ==
3570 23:03:42.030164 Dram Type= 6, Freq= 0, CH_1, rank 1
3571 23:03:42.033749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3572 23:03:42.033818 ==
3573 23:03:42.045138 TX Vref=22, minBit 8, minWin=25, winSum=414
3574 23:03:42.048253 TX Vref=24, minBit 1, minWin=25, winSum=418
3575 23:03:42.051797 TX Vref=26, minBit 11, minWin=25, winSum=422
3576 23:03:42.055250 TX Vref=28, minBit 0, minWin=26, winSum=425
3577 23:03:42.058175 TX Vref=30, minBit 1, minWin=26, winSum=428
3578 23:03:42.064872 TX Vref=32, minBit 1, minWin=26, winSum=426
3579 23:03:42.068242 [TxChooseVref] Worse bit 1, Min win 26, Win sum 428, Final Vref 30
3580 23:03:42.068313
3581 23:03:42.071638 Final TX Range 1 Vref 30
3582 23:03:42.071710
3583 23:03:42.071771 ==
3584 23:03:42.074991 Dram Type= 6, Freq= 0, CH_1, rank 1
3585 23:03:42.078225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3586 23:03:42.078293 ==
3587 23:03:42.081298
3588 23:03:42.081369
3589 23:03:42.081429 TX Vref Scan disable
3590 23:03:42.085221 == TX Byte 0 ==
3591 23:03:42.088287 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3592 23:03:42.094847 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3593 23:03:42.094923 == TX Byte 1 ==
3594 23:03:42.097930 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3595 23:03:42.104568 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3596 23:03:42.104644
3597 23:03:42.104707 [DATLAT]
3598 23:03:42.104765 Freq=1200, CH1 RK1
3599 23:03:42.104826
3600 23:03:42.108103 DATLAT Default: 0xd
3601 23:03:42.108171 0, 0xFFFF, sum = 0
3602 23:03:42.111803 1, 0xFFFF, sum = 0
3603 23:03:42.114678 2, 0xFFFF, sum = 0
3604 23:03:42.114753 3, 0xFFFF, sum = 0
3605 23:03:42.118088 4, 0xFFFF, sum = 0
3606 23:03:42.118163 5, 0xFFFF, sum = 0
3607 23:03:42.121292 6, 0xFFFF, sum = 0
3608 23:03:42.121368 7, 0xFFFF, sum = 0
3609 23:03:42.124495 8, 0xFFFF, sum = 0
3610 23:03:42.124570 9, 0xFFFF, sum = 0
3611 23:03:42.128028 10, 0xFFFF, sum = 0
3612 23:03:42.128100 11, 0xFFFF, sum = 0
3613 23:03:42.131652 12, 0x0, sum = 1
3614 23:03:42.131726 13, 0x0, sum = 2
3615 23:03:42.135095 14, 0x0, sum = 3
3616 23:03:42.135168 15, 0x0, sum = 4
3617 23:03:42.137801 best_step = 13
3618 23:03:42.137873
3619 23:03:42.137938 ==
3620 23:03:42.141129 Dram Type= 6, Freq= 0, CH_1, rank 1
3621 23:03:42.144362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3622 23:03:42.144436 ==
3623 23:03:42.144499 RX Vref Scan: 0
3624 23:03:42.147774
3625 23:03:42.147845 RX Vref 0 -> 0, step: 1
3626 23:03:42.147905
3627 23:03:42.150795 RX Delay -13 -> 252, step: 4
3628 23:03:42.154142 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3629 23:03:42.161078 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3630 23:03:42.164434 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3631 23:03:42.167656 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3632 23:03:42.171158 iDelay=195, Bit 4, Center 122 (63 ~ 182) 120
3633 23:03:42.174368 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3634 23:03:42.180803 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3635 23:03:42.184363 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3636 23:03:42.187538 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3637 23:03:42.190815 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3638 23:03:42.194015 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3639 23:03:42.200660 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3640 23:03:42.204027 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3641 23:03:42.207336 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3642 23:03:42.210863 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3643 23:03:42.217474 iDelay=195, Bit 15, Center 124 (59 ~ 190) 132
3644 23:03:42.217544 ==
3645 23:03:42.220724 Dram Type= 6, Freq= 0, CH_1, rank 1
3646 23:03:42.223855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3647 23:03:42.223928 ==
3648 23:03:42.224009 DQS Delay:
3649 23:03:42.227466 DQS0 = 0, DQS1 = 0
3650 23:03:42.227543 DQM Delay:
3651 23:03:42.230605 DQM0 = 119, DQM1 = 113
3652 23:03:42.230676 DQ Delay:
3653 23:03:42.233750 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =118
3654 23:03:42.237355 DQ4 =122, DQ5 =130, DQ6 =126, DQ7 =116
3655 23:03:42.240514 DQ8 =98, DQ9 =102, DQ10 =112, DQ11 =106
3656 23:03:42.243963 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =124
3657 23:03:42.244037
3658 23:03:42.244100
3659 23:03:42.253738 [DQSOSCAuto] RK1, (LSB)MR18= 0xbee, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 405 ps
3660 23:03:42.257056 CH1 RK1: MR19=403, MR18=BEE
3661 23:03:42.260594 CH1_RK1: MR19=0x403, MR18=0xBEE, DQSOSC=405, MR23=63, INC=39, DEC=26
3662 23:03:42.263913 [RxdqsGatingPostProcess] freq 1200
3663 23:03:42.270498 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3664 23:03:42.273770 best DQS0 dly(2T, 0.5T) = (0, 11)
3665 23:03:42.276988 best DQS1 dly(2T, 0.5T) = (0, 11)
3666 23:03:42.280473 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3667 23:03:42.283602 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3668 23:03:42.287221 best DQS0 dly(2T, 0.5T) = (0, 11)
3669 23:03:42.290210 best DQS1 dly(2T, 0.5T) = (0, 11)
3670 23:03:42.294019 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3671 23:03:42.296997 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3672 23:03:42.297071 Pre-setting of DQS Precalculation
3673 23:03:42.303432 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3674 23:03:42.310170 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3675 23:03:42.316847 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3676 23:03:42.316930
3677 23:03:42.316996
3678 23:03:42.320363 [Calibration Summary] 2400 Mbps
3679 23:03:42.323497 CH 0, Rank 0
3680 23:03:42.323580 SW Impedance : PASS
3681 23:03:42.327074 DUTY Scan : NO K
3682 23:03:42.330129 ZQ Calibration : PASS
3683 23:03:42.330211 Jitter Meter : NO K
3684 23:03:42.333829 CBT Training : PASS
3685 23:03:42.337120 Write leveling : PASS
3686 23:03:42.337202 RX DQS gating : PASS
3687 23:03:42.340266 RX DQ/DQS(RDDQC) : PASS
3688 23:03:42.343545 TX DQ/DQS : PASS
3689 23:03:42.343635 RX DATLAT : PASS
3690 23:03:42.346797 RX DQ/DQS(Engine): PASS
3691 23:03:42.346883 TX OE : NO K
3692 23:03:42.350159 All Pass.
3693 23:03:42.350269
3694 23:03:42.350373 CH 0, Rank 1
3695 23:03:42.354149 SW Impedance : PASS
3696 23:03:42.354260 DUTY Scan : NO K
3697 23:03:42.357219 ZQ Calibration : PASS
3698 23:03:42.360559 Jitter Meter : NO K
3699 23:03:42.360645 CBT Training : PASS
3700 23:03:42.363474 Write leveling : PASS
3701 23:03:42.366726 RX DQS gating : PASS
3702 23:03:42.366811 RX DQ/DQS(RDDQC) : PASS
3703 23:03:42.370197 TX DQ/DQS : PASS
3704 23:03:42.373335 RX DATLAT : PASS
3705 23:03:42.373421 RX DQ/DQS(Engine): PASS
3706 23:03:42.376866 TX OE : NO K
3707 23:03:42.376977 All Pass.
3708 23:03:42.377063
3709 23:03:42.380084 CH 1, Rank 0
3710 23:03:42.380170 SW Impedance : PASS
3711 23:03:42.383465 DUTY Scan : NO K
3712 23:03:42.386645 ZQ Calibration : PASS
3713 23:03:42.386755 Jitter Meter : NO K
3714 23:03:42.390084 CBT Training : PASS
3715 23:03:42.393609 Write leveling : PASS
3716 23:03:42.393695 RX DQS gating : PASS
3717 23:03:42.396796 RX DQ/DQS(RDDQC) : PASS
3718 23:03:42.396885 TX DQ/DQS : PASS
3719 23:03:42.400325 RX DATLAT : PASS
3720 23:03:42.403471 RX DQ/DQS(Engine): PASS
3721 23:03:42.403557 TX OE : NO K
3722 23:03:42.406938 All Pass.
3723 23:03:42.407023
3724 23:03:42.407108 CH 1, Rank 1
3725 23:03:42.410263 SW Impedance : PASS
3726 23:03:42.410373 DUTY Scan : NO K
3727 23:03:42.413380 ZQ Calibration : PASS
3728 23:03:42.416717 Jitter Meter : NO K
3729 23:03:42.416803 CBT Training : PASS
3730 23:03:42.420327 Write leveling : PASS
3731 23:03:42.423322 RX DQS gating : PASS
3732 23:03:42.423408 RX DQ/DQS(RDDQC) : PASS
3733 23:03:42.426670 TX DQ/DQS : PASS
3734 23:03:42.430001 RX DATLAT : PASS
3735 23:03:42.430094 RX DQ/DQS(Engine): PASS
3736 23:03:42.433503 TX OE : NO K
3737 23:03:42.433589 All Pass.
3738 23:03:42.433674
3739 23:03:42.436935 DramC Write-DBI off
3740 23:03:42.440030 PER_BANK_REFRESH: Hybrid Mode
3741 23:03:42.440136 TX_TRACKING: ON
3742 23:03:42.450054 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3743 23:03:42.453574 [FAST_K] Save calibration result to emmc
3744 23:03:42.456540 dramc_set_vcore_voltage set vcore to 650000
3745 23:03:42.460230 Read voltage for 600, 5
3746 23:03:42.460315 Vio18 = 0
3747 23:03:42.460402 Vcore = 650000
3748 23:03:42.463478 Vdram = 0
3749 23:03:42.463564 Vddq = 0
3750 23:03:42.463649 Vmddr = 0
3751 23:03:42.469969 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3752 23:03:42.473299 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3753 23:03:42.476838 MEM_TYPE=3, freq_sel=19
3754 23:03:42.479825 sv_algorithm_assistance_LP4_1600
3755 23:03:42.483265 ============ PULL DRAM RESETB DOWN ============
3756 23:03:42.486486 ========== PULL DRAM RESETB DOWN end =========
3757 23:03:42.493041 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3758 23:03:42.496631 ===================================
3759 23:03:42.496738 LPDDR4 DRAM CONFIGURATION
3760 23:03:42.499984 ===================================
3761 23:03:42.503451 EX_ROW_EN[0] = 0x0
3762 23:03:42.506296 EX_ROW_EN[1] = 0x0
3763 23:03:42.506388 LP4Y_EN = 0x0
3764 23:03:42.510112 WORK_FSP = 0x0
3765 23:03:42.510199 WL = 0x2
3766 23:03:42.513526 RL = 0x2
3767 23:03:42.513612 BL = 0x2
3768 23:03:42.516332 RPST = 0x0
3769 23:03:42.516418 RD_PRE = 0x0
3770 23:03:42.520358 WR_PRE = 0x1
3771 23:03:42.520449 WR_PST = 0x0
3772 23:03:42.523153 DBI_WR = 0x0
3773 23:03:42.523239 DBI_RD = 0x0
3774 23:03:42.526320 OTF = 0x1
3775 23:03:42.529554 ===================================
3776 23:03:42.533014 ===================================
3777 23:03:42.533100 ANA top config
3778 23:03:42.536101 ===================================
3779 23:03:42.539472 DLL_ASYNC_EN = 0
3780 23:03:42.542954 ALL_SLAVE_EN = 1
3781 23:03:42.546025 NEW_RANK_MODE = 1
3782 23:03:42.546129 DLL_IDLE_MODE = 1
3783 23:03:42.549424 LP45_APHY_COMB_EN = 1
3784 23:03:42.552714 TX_ODT_DIS = 1
3785 23:03:42.556215 NEW_8X_MODE = 1
3786 23:03:42.559379 ===================================
3787 23:03:42.562580 ===================================
3788 23:03:42.566193 data_rate = 1200
3789 23:03:42.566303 CKR = 1
3790 23:03:42.569578 DQ_P2S_RATIO = 8
3791 23:03:42.572548 ===================================
3792 23:03:42.576022 CA_P2S_RATIO = 8
3793 23:03:42.579515 DQ_CA_OPEN = 0
3794 23:03:42.582755 DQ_SEMI_OPEN = 0
3795 23:03:42.582841 CA_SEMI_OPEN = 0
3796 23:03:42.585985 CA_FULL_RATE = 0
3797 23:03:42.589649 DQ_CKDIV4_EN = 1
3798 23:03:42.592878 CA_CKDIV4_EN = 1
3799 23:03:42.596207 CA_PREDIV_EN = 0
3800 23:03:42.599846 PH8_DLY = 0
3801 23:03:42.599957 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3802 23:03:42.603284 DQ_AAMCK_DIV = 4
3803 23:03:42.606287 CA_AAMCK_DIV = 4
3804 23:03:42.609702 CA_ADMCK_DIV = 4
3805 23:03:42.612858 DQ_TRACK_CA_EN = 0
3806 23:03:42.616314 CA_PICK = 600
3807 23:03:42.616400 CA_MCKIO = 600
3808 23:03:42.619404 MCKIO_SEMI = 0
3809 23:03:42.623098 PLL_FREQ = 2288
3810 23:03:42.626420 DQ_UI_PI_RATIO = 32
3811 23:03:42.629838 CA_UI_PI_RATIO = 0
3812 23:03:42.633127 ===================================
3813 23:03:42.636383 ===================================
3814 23:03:42.639550 memory_type:LPDDR4
3815 23:03:42.639636 GP_NUM : 10
3816 23:03:42.643008 SRAM_EN : 1
3817 23:03:42.643094 MD32_EN : 0
3818 23:03:42.646582 ===================================
3819 23:03:42.649488 [ANA_INIT] >>>>>>>>>>>>>>
3820 23:03:42.652739 <<<<<< [CONFIGURE PHASE]: ANA_TX
3821 23:03:42.656378 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3822 23:03:42.659310 ===================================
3823 23:03:42.662868 data_rate = 1200,PCW = 0X5800
3824 23:03:42.666271 ===================================
3825 23:03:42.669583 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3826 23:03:42.672623 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3827 23:03:42.679697 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3828 23:03:42.685965 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3829 23:03:42.689311 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3830 23:03:42.692728 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3831 23:03:42.692812 [ANA_INIT] flow start
3832 23:03:42.696122 [ANA_INIT] PLL >>>>>>>>
3833 23:03:42.699513 [ANA_INIT] PLL <<<<<<<<
3834 23:03:42.699597 [ANA_INIT] MIDPI >>>>>>>>
3835 23:03:42.702872 [ANA_INIT] MIDPI <<<<<<<<
3836 23:03:42.706258 [ANA_INIT] DLL >>>>>>>>
3837 23:03:42.706341 [ANA_INIT] flow end
3838 23:03:42.709790 ============ LP4 DIFF to SE enter ============
3839 23:03:42.716070 ============ LP4 DIFF to SE exit ============
3840 23:03:42.716154 [ANA_INIT] <<<<<<<<<<<<<
3841 23:03:42.719477 [Flow] Enable top DCM control >>>>>
3842 23:03:42.722750 [Flow] Enable top DCM control <<<<<
3843 23:03:42.725968 Enable DLL master slave shuffle
3844 23:03:42.732859 ==============================================================
3845 23:03:42.732943 Gating Mode config
3846 23:03:42.739413 ==============================================================
3847 23:03:42.742608 Config description:
3848 23:03:42.752576 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3849 23:03:42.759419 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3850 23:03:42.762525 SELPH_MODE 0: By rank 1: By Phase
3851 23:03:42.769224 ==============================================================
3852 23:03:42.773007 GAT_TRACK_EN = 1
3853 23:03:42.775816 RX_GATING_MODE = 2
3854 23:03:42.775900 RX_GATING_TRACK_MODE = 2
3855 23:03:42.779327 SELPH_MODE = 1
3856 23:03:42.782720 PICG_EARLY_EN = 1
3857 23:03:42.786060 VALID_LAT_VALUE = 1
3858 23:03:42.792337 ==============================================================
3859 23:03:42.795632 Enter into Gating configuration >>>>
3860 23:03:42.798900 Exit from Gating configuration <<<<
3861 23:03:42.802513 Enter into DVFS_PRE_config >>>>>
3862 23:03:42.812480 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3863 23:03:42.815720 Exit from DVFS_PRE_config <<<<<
3864 23:03:42.819138 Enter into PICG configuration >>>>
3865 23:03:42.822419 Exit from PICG configuration <<<<
3866 23:03:42.825856 [RX_INPUT] configuration >>>>>
3867 23:03:42.829327 [RX_INPUT] configuration <<<<<
3868 23:03:42.832502 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3869 23:03:42.839358 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3870 23:03:42.845904 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3871 23:03:42.849122 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3872 23:03:42.855743 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3873 23:03:42.862665 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3874 23:03:42.865597 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3875 23:03:42.872480 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3876 23:03:42.875637 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3877 23:03:42.879388 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3878 23:03:42.882593 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3879 23:03:42.889109 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3880 23:03:42.892423 ===================================
3881 23:03:42.892509 LPDDR4 DRAM CONFIGURATION
3882 23:03:42.895847 ===================================
3883 23:03:42.899005 EX_ROW_EN[0] = 0x0
3884 23:03:42.902358 EX_ROW_EN[1] = 0x0
3885 23:03:42.902455 LP4Y_EN = 0x0
3886 23:03:42.905720 WORK_FSP = 0x0
3887 23:03:42.905804 WL = 0x2
3888 23:03:42.909055 RL = 0x2
3889 23:03:42.909140 BL = 0x2
3890 23:03:42.912250 RPST = 0x0
3891 23:03:42.912334 RD_PRE = 0x0
3892 23:03:42.915458 WR_PRE = 0x1
3893 23:03:42.915542 WR_PST = 0x0
3894 23:03:42.918694 DBI_WR = 0x0
3895 23:03:42.918778 DBI_RD = 0x0
3896 23:03:42.922527 OTF = 0x1
3897 23:03:42.925361 ===================================
3898 23:03:42.928820 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3899 23:03:42.931901 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3900 23:03:42.938752 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3901 23:03:42.942131 ===================================
3902 23:03:42.942217 LPDDR4 DRAM CONFIGURATION
3903 23:03:42.945448 ===================================
3904 23:03:42.948577 EX_ROW_EN[0] = 0x10
3905 23:03:42.948661 EX_ROW_EN[1] = 0x0
3906 23:03:42.952087 LP4Y_EN = 0x0
3907 23:03:42.955414 WORK_FSP = 0x0
3908 23:03:42.955498 WL = 0x2
3909 23:03:42.958707 RL = 0x2
3910 23:03:42.958792 BL = 0x2
3911 23:03:42.962124 RPST = 0x0
3912 23:03:42.962208 RD_PRE = 0x0
3913 23:03:42.965386 WR_PRE = 0x1
3914 23:03:42.965470 WR_PST = 0x0
3915 23:03:42.968700 DBI_WR = 0x0
3916 23:03:42.968784 DBI_RD = 0x0
3917 23:03:42.971866 OTF = 0x1
3918 23:03:42.975425 ===================================
3919 23:03:42.981961 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3920 23:03:42.985589 nWR fixed to 30
3921 23:03:42.985675 [ModeRegInit_LP4] CH0 RK0
3922 23:03:42.988502 [ModeRegInit_LP4] CH0 RK1
3923 23:03:42.991982 [ModeRegInit_LP4] CH1 RK0
3924 23:03:42.992066 [ModeRegInit_LP4] CH1 RK1
3925 23:03:42.995199 match AC timing 17
3926 23:03:42.998769 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3927 23:03:43.002281 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3928 23:03:43.008745 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3929 23:03:43.011987 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3930 23:03:43.018954 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3931 23:03:43.019041 ==
3932 23:03:43.022059 Dram Type= 6, Freq= 0, CH_0, rank 0
3933 23:03:43.025449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3934 23:03:43.025535 ==
3935 23:03:43.032066 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3936 23:03:43.035337 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3937 23:03:43.039578 [CA 0] Center 36 (5~67) winsize 63
3938 23:03:43.043073 [CA 1] Center 36 (6~67) winsize 62
3939 23:03:43.046590 [CA 2] Center 34 (4~65) winsize 62
3940 23:03:43.049431 [CA 3] Center 34 (3~65) winsize 63
3941 23:03:43.052915 [CA 4] Center 33 (3~64) winsize 62
3942 23:03:43.056265 [CA 5] Center 33 (2~64) winsize 63
3943 23:03:43.056350
3944 23:03:43.059983 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3945 23:03:43.060070
3946 23:03:43.062816 [CATrainingPosCal] consider 1 rank data
3947 23:03:43.065971 u2DelayCellTimex100 = 270/100 ps
3948 23:03:43.069265 CA0 delay=36 (5~67),Diff = 3 PI (28 cell)
3949 23:03:43.073071 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3950 23:03:43.079571 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3951 23:03:43.083112 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3952 23:03:43.086152 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3953 23:03:43.089659 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
3954 23:03:43.089744
3955 23:03:43.092580 CA PerBit enable=1, Macro0, CA PI delay=33
3956 23:03:43.092665
3957 23:03:43.096218 [CBTSetCACLKResult] CA Dly = 33
3958 23:03:43.096326 CS Dly: 5 (0~36)
3959 23:03:43.099410 ==
3960 23:03:43.099488 Dram Type= 6, Freq= 0, CH_0, rank 1
3961 23:03:43.105914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3962 23:03:43.106020 ==
3963 23:03:43.109952 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3964 23:03:43.116030 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3965 23:03:43.119897 [CA 0] Center 36 (6~67) winsize 62
3966 23:03:43.123206 [CA 1] Center 36 (6~67) winsize 62
3967 23:03:43.126309 [CA 2] Center 35 (5~65) winsize 61
3968 23:03:43.129721 [CA 3] Center 34 (4~65) winsize 62
3969 23:03:43.132937 [CA 4] Center 34 (3~65) winsize 63
3970 23:03:43.136448 [CA 5] Center 33 (3~64) winsize 62
3971 23:03:43.136542
3972 23:03:43.139679 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3973 23:03:43.139787
3974 23:03:43.142861 [CATrainingPosCal] consider 2 rank data
3975 23:03:43.146195 u2DelayCellTimex100 = 270/100 ps
3976 23:03:43.149405 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3977 23:03:43.156267 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3978 23:03:43.159330 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
3979 23:03:43.162756 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3980 23:03:43.166067 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3981 23:03:43.170744 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3982 23:03:43.170823
3983 23:03:43.172736 CA PerBit enable=1, Macro0, CA PI delay=33
3984 23:03:43.172805
3985 23:03:43.176540 [CBTSetCACLKResult] CA Dly = 33
3986 23:03:43.176643 CS Dly: 5 (0~37)
3987 23:03:43.179358
3988 23:03:43.182590 ----->DramcWriteLeveling(PI) begin...
3989 23:03:43.182696 ==
3990 23:03:43.186123 Dram Type= 6, Freq= 0, CH_0, rank 0
3991 23:03:43.189437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3992 23:03:43.189525 ==
3993 23:03:43.192662 Write leveling (Byte 0): 34 => 34
3994 23:03:43.195833 Write leveling (Byte 1): 31 => 31
3995 23:03:43.199116 DramcWriteLeveling(PI) end<-----
3996 23:03:43.199191
3997 23:03:43.199270 ==
3998 23:03:43.202825 Dram Type= 6, Freq= 0, CH_0, rank 0
3999 23:03:43.206044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4000 23:03:43.206142 ==
4001 23:03:43.209569 [Gating] SW mode calibration
4002 23:03:43.215972 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4003 23:03:43.222604 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4004 23:03:43.225744 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4005 23:03:43.229194 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4006 23:03:43.235679 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4007 23:03:43.239128 0 9 12 | B1->B0 | 3333 2c2c | 1 0 | (1 1) (0 1)
4008 23:03:43.242453 0 9 16 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
4009 23:03:43.248878 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4010 23:03:43.252750 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4011 23:03:43.256131 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4012 23:03:43.262307 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4013 23:03:43.265677 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4014 23:03:43.268739 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4015 23:03:43.275376 0 10 12 | B1->B0 | 2828 3939 | 0 1 | (0 0) (0 0)
4016 23:03:43.278984 0 10 16 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
4017 23:03:43.282051 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4018 23:03:43.285741 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4019 23:03:43.292133 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4020 23:03:43.295652 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4021 23:03:43.298966 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4022 23:03:43.305511 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4023 23:03:43.308812 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4024 23:03:43.312237 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4025 23:03:43.318912 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 23:03:43.322120 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 23:03:43.325682 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 23:03:43.332334 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 23:03:43.335426 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 23:03:43.338653 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 23:03:43.345818 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 23:03:43.348585 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4033 23:03:43.352091 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4034 23:03:43.358877 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 23:03:43.361931 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4036 23:03:43.365256 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4037 23:03:43.372043 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4038 23:03:43.375800 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4039 23:03:43.378803 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4040 23:03:43.382065 Total UI for P1: 0, mck2ui 16
4041 23:03:43.385120 best dqsien dly found for B0: ( 0, 13, 10)
4042 23:03:43.392075 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4043 23:03:43.395200 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4044 23:03:43.398665 Total UI for P1: 0, mck2ui 16
4045 23:03:43.401794 best dqsien dly found for B1: ( 0, 13, 18)
4046 23:03:43.405186 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4047 23:03:43.408671 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4048 23:03:43.408754
4049 23:03:43.411750 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4050 23:03:43.415165 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4051 23:03:43.418493 [Gating] SW calibration Done
4052 23:03:43.418576 ==
4053 23:03:43.421807 Dram Type= 6, Freq= 0, CH_0, rank 0
4054 23:03:43.424848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4055 23:03:43.428458 ==
4056 23:03:43.428541 RX Vref Scan: 0
4057 23:03:43.428607
4058 23:03:43.431658 RX Vref 0 -> 0, step: 1
4059 23:03:43.431740
4060 23:03:43.435165 RX Delay -230 -> 252, step: 16
4061 23:03:43.438229 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4062 23:03:43.441786 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4063 23:03:43.444950 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4064 23:03:43.448724 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4065 23:03:43.455020 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4066 23:03:43.458624 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4067 23:03:43.461924 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4068 23:03:43.465216 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4069 23:03:43.468614 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4070 23:03:43.475267 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4071 23:03:43.478351 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4072 23:03:43.481936 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4073 23:03:43.485103 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4074 23:03:43.491661 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4075 23:03:43.494970 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4076 23:03:43.498393 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4077 23:03:43.498477 ==
4078 23:03:43.501694 Dram Type= 6, Freq= 0, CH_0, rank 0
4079 23:03:43.504733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4080 23:03:43.508700 ==
4081 23:03:43.508783 DQS Delay:
4082 23:03:43.508849 DQS0 = 0, DQS1 = 0
4083 23:03:43.511911 DQM Delay:
4084 23:03:43.511995 DQM0 = 51, DQM1 = 40
4085 23:03:43.514893 DQ Delay:
4086 23:03:43.518109 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =49
4087 23:03:43.518193 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4088 23:03:43.521774 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =25
4089 23:03:43.524770 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =49
4090 23:03:43.524854
4091 23:03:43.528433
4092 23:03:43.528516 ==
4093 23:03:43.531612 Dram Type= 6, Freq= 0, CH_0, rank 0
4094 23:03:43.535154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4095 23:03:43.535238 ==
4096 23:03:43.535305
4097 23:03:43.535367
4098 23:03:43.538371 TX Vref Scan disable
4099 23:03:43.538494 == TX Byte 0 ==
4100 23:03:43.544887 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4101 23:03:43.548018 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4102 23:03:43.548102 == TX Byte 1 ==
4103 23:03:43.554847 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4104 23:03:43.558042 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4105 23:03:43.558129 ==
4106 23:03:43.561488 Dram Type= 6, Freq= 0, CH_0, rank 0
4107 23:03:43.565027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4108 23:03:43.565111 ==
4109 23:03:43.565177
4110 23:03:43.565240
4111 23:03:43.568301 TX Vref Scan disable
4112 23:03:43.571240 == TX Byte 0 ==
4113 23:03:43.574306 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4114 23:03:43.577779 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4115 23:03:43.581450 == TX Byte 1 ==
4116 23:03:43.584282 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4117 23:03:43.591014 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4118 23:03:43.591098
4119 23:03:43.591164 [DATLAT]
4120 23:03:43.591226 Freq=600, CH0 RK0
4121 23:03:43.591286
4122 23:03:43.594233 DATLAT Default: 0x9
4123 23:03:43.594317 0, 0xFFFF, sum = 0
4124 23:03:43.597865 1, 0xFFFF, sum = 0
4125 23:03:43.597949 2, 0xFFFF, sum = 0
4126 23:03:43.601031 3, 0xFFFF, sum = 0
4127 23:03:43.604302 4, 0xFFFF, sum = 0
4128 23:03:43.604387 5, 0xFFFF, sum = 0
4129 23:03:43.607710 6, 0xFFFF, sum = 0
4130 23:03:43.607794 7, 0xFFFF, sum = 0
4131 23:03:43.611221 8, 0x0, sum = 1
4132 23:03:43.611307 9, 0x0, sum = 2
4133 23:03:43.611375 10, 0x0, sum = 3
4134 23:03:43.614137 11, 0x0, sum = 4
4135 23:03:43.614222 best_step = 9
4136 23:03:43.614288
4137 23:03:43.614349 ==
4138 23:03:43.617616 Dram Type= 6, Freq= 0, CH_0, rank 0
4139 23:03:43.624402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4140 23:03:43.624485 ==
4141 23:03:43.624552 RX Vref Scan: 1
4142 23:03:43.624616
4143 23:03:43.627436 RX Vref 0 -> 0, step: 1
4144 23:03:43.627520
4145 23:03:43.630926 RX Delay -179 -> 252, step: 8
4146 23:03:43.631009
4147 23:03:43.634190 Set Vref, RX VrefLevel [Byte0]: 59
4148 23:03:43.637512 [Byte1]: 49
4149 23:03:43.637595
4150 23:03:43.640737 Final RX Vref Byte 0 = 59 to rank0
4151 23:03:43.644222 Final RX Vref Byte 1 = 49 to rank0
4152 23:03:43.647261 Final RX Vref Byte 0 = 59 to rank1
4153 23:03:43.650778 Final RX Vref Byte 1 = 49 to rank1==
4154 23:03:43.654121 Dram Type= 6, Freq= 0, CH_0, rank 0
4155 23:03:43.657667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4156 23:03:43.657755 ==
4157 23:03:43.660566 DQS Delay:
4158 23:03:43.660649 DQS0 = 0, DQS1 = 0
4159 23:03:43.663936 DQM Delay:
4160 23:03:43.664006 DQM0 = 50, DQM1 = 37
4161 23:03:43.664070 DQ Delay:
4162 23:03:43.667273 DQ0 =48, DQ1 =48, DQ2 =48, DQ3 =48
4163 23:03:43.670251 DQ4 =52, DQ5 =40, DQ6 =60, DQ7 =56
4164 23:03:43.673969 DQ8 =32, DQ9 =20, DQ10 =36, DQ11 =32
4165 23:03:43.677165 DQ12 =44, DQ13 =40, DQ14 =48, DQ15 =44
4166 23:03:43.677234
4167 23:03:43.677295
4168 23:03:43.687254 [DQSOSCAuto] RK0, (LSB)MR18= 0x5a54, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
4169 23:03:43.690299 CH0 RK0: MR19=808, MR18=5A54
4170 23:03:43.696860 CH0_RK0: MR19=0x808, MR18=0x5A54, DQSOSC=392, MR23=63, INC=170, DEC=113
4171 23:03:43.696930
4172 23:03:43.700566 ----->DramcWriteLeveling(PI) begin...
4173 23:03:43.700633 ==
4174 23:03:43.703864 Dram Type= 6, Freq= 0, CH_0, rank 1
4175 23:03:43.707057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4176 23:03:43.707123 ==
4177 23:03:43.710304 Write leveling (Byte 0): 34 => 34
4178 23:03:43.713512 Write leveling (Byte 1): 30 => 30
4179 23:03:43.716698 DramcWriteLeveling(PI) end<-----
4180 23:03:43.716764
4181 23:03:43.716823 ==
4182 23:03:43.720402 Dram Type= 6, Freq= 0, CH_0, rank 1
4183 23:03:43.723570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4184 23:03:43.723638 ==
4185 23:03:43.726480 [Gating] SW mode calibration
4186 23:03:43.733218 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4187 23:03:43.739928 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4188 23:03:43.743180 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4189 23:03:43.746624 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4190 23:03:43.753326 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4191 23:03:43.756438 0 9 12 | B1->B0 | 3333 3333 | 1 1 | (0 0) (0 0)
4192 23:03:43.760152 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4193 23:03:43.766248 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4194 23:03:43.769622 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4195 23:03:43.772915 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4196 23:03:43.779773 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4197 23:03:43.783226 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4198 23:03:43.786560 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4199 23:03:43.792864 0 10 12 | B1->B0 | 2d2d 3232 | 0 0 | (0 0) (0 0)
4200 23:03:43.796635 0 10 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
4201 23:03:43.799500 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4202 23:03:43.806170 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4203 23:03:43.809485 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4204 23:03:43.812980 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4205 23:03:43.819410 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4206 23:03:43.822754 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4207 23:03:43.826092 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4208 23:03:43.832605 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 23:03:43.836431 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 23:03:43.839677 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 23:03:43.842941 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 23:03:43.849742 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 23:03:43.852978 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4214 23:03:43.856581 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4215 23:03:43.863107 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4216 23:03:43.866587 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4217 23:03:43.869371 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4218 23:03:43.876363 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4219 23:03:43.879474 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4220 23:03:43.882945 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4221 23:03:43.889322 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4222 23:03:43.892748 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4223 23:03:43.896002 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4224 23:03:43.899214 Total UI for P1: 0, mck2ui 16
4225 23:03:43.902869 best dqsien dly found for B0: ( 0, 13, 10)
4226 23:03:43.909339 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4227 23:03:43.909422 Total UI for P1: 0, mck2ui 16
4228 23:03:43.915978 best dqsien dly found for B1: ( 0, 13, 12)
4229 23:03:43.919376 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4230 23:03:43.922717 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4231 23:03:43.922800
4232 23:03:43.925790 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4233 23:03:43.929065 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4234 23:03:43.932743 [Gating] SW calibration Done
4235 23:03:43.932826 ==
4236 23:03:43.935727 Dram Type= 6, Freq= 0, CH_0, rank 1
4237 23:03:43.939288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4238 23:03:43.939371 ==
4239 23:03:43.942685 RX Vref Scan: 0
4240 23:03:43.942768
4241 23:03:43.942834 RX Vref 0 -> 0, step: 1
4242 23:03:43.942896
4243 23:03:43.945788 RX Delay -230 -> 252, step: 16
4244 23:03:43.952474 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4245 23:03:43.956001 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4246 23:03:43.958769 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4247 23:03:43.962364 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4248 23:03:43.968705 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4249 23:03:43.972123 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4250 23:03:43.975388 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4251 23:03:43.978806 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4252 23:03:43.982036 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4253 23:03:43.988774 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4254 23:03:43.992094 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4255 23:03:43.995474 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4256 23:03:43.998885 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4257 23:03:44.005624 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4258 23:03:44.008820 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4259 23:03:44.012393 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4260 23:03:44.012476 ==
4261 23:03:44.015174 Dram Type= 6, Freq= 0, CH_0, rank 1
4262 23:03:44.019121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4263 23:03:44.022051 ==
4264 23:03:44.022134 DQS Delay:
4265 23:03:44.022200 DQS0 = 0, DQS1 = 0
4266 23:03:44.025325 DQM Delay:
4267 23:03:44.025408 DQM0 = 50, DQM1 = 43
4268 23:03:44.025474 DQ Delay:
4269 23:03:44.029334 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4270 23:03:44.032168 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4271 23:03:44.035560 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4272 23:03:44.038441 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4273 23:03:44.038563
4274 23:03:44.038656
4275 23:03:44.042173 ==
4276 23:03:44.045509 Dram Type= 6, Freq= 0, CH_0, rank 1
4277 23:03:44.048604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4278 23:03:44.048687 ==
4279 23:03:44.048753
4280 23:03:44.048813
4281 23:03:44.052172 TX Vref Scan disable
4282 23:03:44.052255 == TX Byte 0 ==
4283 23:03:44.058514 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4284 23:03:44.061739 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4285 23:03:44.061823 == TX Byte 1 ==
4286 23:03:44.068495 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4287 23:03:44.071762 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4288 23:03:44.071845 ==
4289 23:03:44.075220 Dram Type= 6, Freq= 0, CH_0, rank 1
4290 23:03:44.078625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4291 23:03:44.078709 ==
4292 23:03:44.078775
4293 23:03:44.078834
4294 23:03:44.081905 TX Vref Scan disable
4295 23:03:44.085323 == TX Byte 0 ==
4296 23:03:44.088976 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4297 23:03:44.092083 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4298 23:03:44.094965 == TX Byte 1 ==
4299 23:03:44.098259 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4300 23:03:44.101792 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4301 23:03:44.101874
4302 23:03:44.105180 [DATLAT]
4303 23:03:44.105263 Freq=600, CH0 RK1
4304 23:03:44.105329
4305 23:03:44.108452 DATLAT Default: 0x9
4306 23:03:44.108535 0, 0xFFFF, sum = 0
4307 23:03:44.111765 1, 0xFFFF, sum = 0
4308 23:03:44.111850 2, 0xFFFF, sum = 0
4309 23:03:44.115322 3, 0xFFFF, sum = 0
4310 23:03:44.115404 4, 0xFFFF, sum = 0
4311 23:03:44.118613 5, 0xFFFF, sum = 0
4312 23:03:44.118723 6, 0xFFFF, sum = 0
4313 23:03:44.121881 7, 0xFFFF, sum = 0
4314 23:03:44.121964 8, 0x0, sum = 1
4315 23:03:44.125097 9, 0x0, sum = 2
4316 23:03:44.125179 10, 0x0, sum = 3
4317 23:03:44.128599 11, 0x0, sum = 4
4318 23:03:44.128680 best_step = 9
4319 23:03:44.128744
4320 23:03:44.128804 ==
4321 23:03:44.131653 Dram Type= 6, Freq= 0, CH_0, rank 1
4322 23:03:44.135193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4323 23:03:44.138540 ==
4324 23:03:44.138620 RX Vref Scan: 0
4325 23:03:44.138684
4326 23:03:44.141524 RX Vref 0 -> 0, step: 1
4327 23:03:44.141605
4328 23:03:44.144794 RX Delay -163 -> 252, step: 8
4329 23:03:44.148641 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4330 23:03:44.151569 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4331 23:03:44.158255 iDelay=205, Bit 2, Center 48 (-99 ~ 196) 296
4332 23:03:44.161726 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4333 23:03:44.165269 iDelay=205, Bit 4, Center 52 (-91 ~ 196) 288
4334 23:03:44.168496 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4335 23:03:44.171594 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4336 23:03:44.178270 iDelay=205, Bit 7, Center 56 (-91 ~ 204) 296
4337 23:03:44.181432 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4338 23:03:44.184938 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4339 23:03:44.187913 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4340 23:03:44.194677 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4341 23:03:44.197835 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4342 23:03:44.201260 iDelay=205, Bit 13, Center 48 (-91 ~ 188) 280
4343 23:03:44.204594 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4344 23:03:44.208163 iDelay=205, Bit 15, Center 48 (-91 ~ 188) 280
4345 23:03:44.211279 ==
4346 23:03:44.211360 Dram Type= 6, Freq= 0, CH_0, rank 1
4347 23:03:44.217948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4348 23:03:44.218030 ==
4349 23:03:44.218094 DQS Delay:
4350 23:03:44.221652 DQS0 = 0, DQS1 = 0
4351 23:03:44.221734 DQM Delay:
4352 23:03:44.224884 DQM0 = 49, DQM1 = 41
4353 23:03:44.224965 DQ Delay:
4354 23:03:44.227788 DQ0 =48, DQ1 =48, DQ2 =48, DQ3 =44
4355 23:03:44.231625 DQ4 =52, DQ5 =40, DQ6 =56, DQ7 =56
4356 23:03:44.234841 DQ8 =32, DQ9 =28, DQ10 =40, DQ11 =32
4357 23:03:44.238007 DQ12 =48, DQ13 =48, DQ14 =52, DQ15 =48
4358 23:03:44.238089
4359 23:03:44.238154
4360 23:03:44.244430 [DQSOSCAuto] RK1, (LSB)MR18= 0x622e, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 391 ps
4361 23:03:44.247963 CH0 RK1: MR19=808, MR18=622E
4362 23:03:44.254264 CH0_RK1: MR19=0x808, MR18=0x622E, DQSOSC=391, MR23=63, INC=171, DEC=114
4363 23:03:44.257820 [RxdqsGatingPostProcess] freq 600
4364 23:03:44.264553 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4365 23:03:44.264634 Pre-setting of DQS Precalculation
4366 23:03:44.271410 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4367 23:03:44.271491 ==
4368 23:03:44.274358 Dram Type= 6, Freq= 0, CH_1, rank 0
4369 23:03:44.277881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4370 23:03:44.277965 ==
4371 23:03:44.284355 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4372 23:03:44.291353 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4373 23:03:44.294008 [CA 0] Center 35 (5~66) winsize 62
4374 23:03:44.297307 [CA 1] Center 35 (5~66) winsize 62
4375 23:03:44.300923 [CA 2] Center 34 (4~65) winsize 62
4376 23:03:44.304101 [CA 3] Center 33 (3~64) winsize 62
4377 23:03:44.307450 [CA 4] Center 34 (3~65) winsize 63
4378 23:03:44.311170 [CA 5] Center 33 (3~64) winsize 62
4379 23:03:44.311253
4380 23:03:44.314259 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4381 23:03:44.314367
4382 23:03:44.317581 [CATrainingPosCal] consider 1 rank data
4383 23:03:44.321001 u2DelayCellTimex100 = 270/100 ps
4384 23:03:44.324285 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4385 23:03:44.327539 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4386 23:03:44.330856 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4387 23:03:44.334248 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4388 23:03:44.337476 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4389 23:03:44.340804 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4390 23:03:44.340901
4391 23:03:44.347510 CA PerBit enable=1, Macro0, CA PI delay=33
4392 23:03:44.347595
4393 23:03:44.347661 [CBTSetCACLKResult] CA Dly = 33
4394 23:03:44.350919 CS Dly: 3 (0~34)
4395 23:03:44.351002 ==
4396 23:03:44.354542 Dram Type= 6, Freq= 0, CH_1, rank 1
4397 23:03:44.357408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4398 23:03:44.357492 ==
4399 23:03:44.363942 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4400 23:03:44.370293 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4401 23:03:44.373840 [CA 0] Center 35 (5~66) winsize 62
4402 23:03:44.377539 [CA 1] Center 35 (5~66) winsize 62
4403 23:03:44.380552 [CA 2] Center 34 (4~65) winsize 62
4404 23:03:44.383994 [CA 3] Center 34 (4~65) winsize 62
4405 23:03:44.387179 [CA 4] Center 34 (4~65) winsize 62
4406 23:03:44.390271 [CA 5] Center 33 (3~64) winsize 62
4407 23:03:44.390380
4408 23:03:44.394181 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4409 23:03:44.394290
4410 23:03:44.397098 [CATrainingPosCal] consider 2 rank data
4411 23:03:44.400504 u2DelayCellTimex100 = 270/100 ps
4412 23:03:44.403862 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4413 23:03:44.407140 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4414 23:03:44.410471 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4415 23:03:44.413591 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4416 23:03:44.417351 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4417 23:03:44.420668 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4418 23:03:44.423698
4419 23:03:44.427283 CA PerBit enable=1, Macro0, CA PI delay=33
4420 23:03:44.427367
4421 23:03:44.430582 [CBTSetCACLKResult] CA Dly = 33
4422 23:03:44.430667 CS Dly: 4 (0~36)
4423 23:03:44.430734
4424 23:03:44.433765 ----->DramcWriteLeveling(PI) begin...
4425 23:03:44.433849 ==
4426 23:03:44.437159 Dram Type= 6, Freq= 0, CH_1, rank 0
4427 23:03:44.440292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4428 23:03:44.443548 ==
4429 23:03:44.443632 Write leveling (Byte 0): 28 => 28
4430 23:03:44.447683 Write leveling (Byte 1): 27 => 27
4431 23:03:44.450658 DramcWriteLeveling(PI) end<-----
4432 23:03:44.450743
4433 23:03:44.450809 ==
4434 23:03:44.453907 Dram Type= 6, Freq= 0, CH_1, rank 0
4435 23:03:44.460277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4436 23:03:44.460361 ==
4437 23:03:44.460429 [Gating] SW mode calibration
4438 23:03:44.470137 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4439 23:03:44.473520 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4440 23:03:44.480245 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4441 23:03:44.483956 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4442 23:03:44.487154 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4443 23:03:44.490006 0 9 12 | B1->B0 | 2d2d 2e2e | 0 0 | (0 1) (0 0)
4444 23:03:44.496874 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4445 23:03:44.500011 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4446 23:03:44.503473 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4447 23:03:44.509990 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4448 23:03:44.513741 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4449 23:03:44.516609 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4450 23:03:44.523799 0 10 8 | B1->B0 | 2525 2626 | 0 0 | (0 0) (0 0)
4451 23:03:44.526719 0 10 12 | B1->B0 | 3737 3c3c | 0 1 | (0 0) (0 0)
4452 23:03:44.529912 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4453 23:03:44.536773 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4454 23:03:44.540384 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4455 23:03:44.543334 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4456 23:03:44.549756 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4457 23:03:44.553217 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4458 23:03:44.556876 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4459 23:03:44.563239 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4460 23:03:44.566478 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 23:03:44.569843 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 23:03:44.576711 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 23:03:44.579788 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 23:03:44.583132 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 23:03:44.589785 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 23:03:44.593064 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 23:03:44.596562 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 23:03:44.603348 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 23:03:44.606530 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 23:03:44.609887 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 23:03:44.616283 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4472 23:03:44.619853 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4473 23:03:44.623120 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4474 23:03:44.626331 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4475 23:03:44.632965 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4476 23:03:44.636179 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4477 23:03:44.639590 Total UI for P1: 0, mck2ui 16
4478 23:03:44.643015 best dqsien dly found for B0: ( 0, 13, 12)
4479 23:03:44.646570 Total UI for P1: 0, mck2ui 16
4480 23:03:44.649796 best dqsien dly found for B1: ( 0, 13, 12)
4481 23:03:44.652995 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4482 23:03:44.656612 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4483 23:03:44.656696
4484 23:03:44.659632 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4485 23:03:44.663151 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4486 23:03:44.666288 [Gating] SW calibration Done
4487 23:03:44.666371 ==
4488 23:03:44.670011 Dram Type= 6, Freq= 0, CH_1, rank 0
4489 23:03:44.676165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4490 23:03:44.676252 ==
4491 23:03:44.676320 RX Vref Scan: 0
4492 23:03:44.676382
4493 23:03:44.679795 RX Vref 0 -> 0, step: 1
4494 23:03:44.679879
4495 23:03:44.682930 RX Delay -230 -> 252, step: 16
4496 23:03:44.686054 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4497 23:03:44.689651 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4498 23:03:44.692799 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4499 23:03:44.699364 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4500 23:03:44.702993 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4501 23:03:44.706015 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4502 23:03:44.709361 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4503 23:03:44.716107 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4504 23:03:44.719405 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4505 23:03:44.722752 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4506 23:03:44.726079 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4507 23:03:44.729357 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4508 23:03:44.736420 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4509 23:03:44.739521 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4510 23:03:44.743336 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4511 23:03:44.746484 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4512 23:03:44.746593 ==
4513 23:03:44.749733 Dram Type= 6, Freq= 0, CH_1, rank 0
4514 23:03:44.756205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4515 23:03:44.756289 ==
4516 23:03:44.756357 DQS Delay:
4517 23:03:44.759553 DQS0 = 0, DQS1 = 0
4518 23:03:44.759663 DQM Delay:
4519 23:03:44.759758 DQM0 = 49, DQM1 = 44
4520 23:03:44.762781 DQ Delay:
4521 23:03:44.766072 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =49
4522 23:03:44.769304 DQ4 =49, DQ5 =49, DQ6 =57, DQ7 =49
4523 23:03:44.772917 DQ8 =25, DQ9 =33, DQ10 =41, DQ11 =33
4524 23:03:44.776255 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4525 23:03:44.776338
4526 23:03:44.776404
4527 23:03:44.776465 ==
4528 23:03:44.779464 Dram Type= 6, Freq= 0, CH_1, rank 0
4529 23:03:44.782910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4530 23:03:44.782994 ==
4531 23:03:44.783061
4532 23:03:44.783122
4533 23:03:44.786529 TX Vref Scan disable
4534 23:03:44.789653 == TX Byte 0 ==
4535 23:03:44.792824 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4536 23:03:44.796735 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4537 23:03:44.799295 == TX Byte 1 ==
4538 23:03:44.802679 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4539 23:03:44.806290 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4540 23:03:44.806374 ==
4541 23:03:44.809177 Dram Type= 6, Freq= 0, CH_1, rank 0
4542 23:03:44.812812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4543 23:03:44.812919 ==
4544 23:03:44.815919
4545 23:03:44.816003
4546 23:03:44.816070 TX Vref Scan disable
4547 23:03:44.819543 == TX Byte 0 ==
4548 23:03:44.822852 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4549 23:03:44.826311 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4550 23:03:44.829754 == TX Byte 1 ==
4551 23:03:44.833137 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4552 23:03:44.836446 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4553 23:03:44.839581
4554 23:03:44.839664 [DATLAT]
4555 23:03:44.839731 Freq=600, CH1 RK0
4556 23:03:44.839793
4557 23:03:44.843349 DATLAT Default: 0x9
4558 23:03:44.843433 0, 0xFFFF, sum = 0
4559 23:03:44.846535 1, 0xFFFF, sum = 0
4560 23:03:44.846620 2, 0xFFFF, sum = 0
4561 23:03:44.849610 3, 0xFFFF, sum = 0
4562 23:03:44.849694 4, 0xFFFF, sum = 0
4563 23:03:44.853181 5, 0xFFFF, sum = 0
4564 23:03:44.856424 6, 0xFFFF, sum = 0
4565 23:03:44.856509 7, 0xFFFF, sum = 0
4566 23:03:44.856577 8, 0x0, sum = 1
4567 23:03:44.859708 9, 0x0, sum = 2
4568 23:03:44.859793 10, 0x0, sum = 3
4569 23:03:44.863174 11, 0x0, sum = 4
4570 23:03:44.863262 best_step = 9
4571 23:03:44.863330
4572 23:03:44.863391 ==
4573 23:03:44.866158 Dram Type= 6, Freq= 0, CH_1, rank 0
4574 23:03:44.872967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4575 23:03:44.873051 ==
4576 23:03:44.873118 RX Vref Scan: 1
4577 23:03:44.873179
4578 23:03:44.876032 RX Vref 0 -> 0, step: 1
4579 23:03:44.876115
4580 23:03:44.879470 RX Delay -179 -> 252, step: 8
4581 23:03:44.879554
4582 23:03:44.882705 Set Vref, RX VrefLevel [Byte0]: 50
4583 23:03:44.886202 [Byte1]: 52
4584 23:03:44.886286
4585 23:03:44.889285 Final RX Vref Byte 0 = 50 to rank0
4586 23:03:44.892713 Final RX Vref Byte 1 = 52 to rank0
4587 23:03:44.896059 Final RX Vref Byte 0 = 50 to rank1
4588 23:03:44.899228 Final RX Vref Byte 1 = 52 to rank1==
4589 23:03:44.902645 Dram Type= 6, Freq= 0, CH_1, rank 0
4590 23:03:44.906317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4591 23:03:44.906459 ==
4592 23:03:44.909325 DQS Delay:
4593 23:03:44.909407 DQS0 = 0, DQS1 = 0
4594 23:03:44.912461 DQM Delay:
4595 23:03:44.912544 DQM0 = 49, DQM1 = 41
4596 23:03:44.912611 DQ Delay:
4597 23:03:44.915984 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4598 23:03:44.919450 DQ4 =52, DQ5 =60, DQ6 =60, DQ7 =44
4599 23:03:44.922720 DQ8 =28, DQ9 =28, DQ10 =44, DQ11 =32
4600 23:03:44.925979 DQ12 =52, DQ13 =48, DQ14 =48, DQ15 =48
4601 23:03:44.926063
4602 23:03:44.926129
4603 23:03:44.935839 [DQSOSCAuto] RK0, (LSB)MR18= 0x4a70, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4604 23:03:44.939389 CH1 RK0: MR19=808, MR18=4A70
4605 23:03:44.942494 CH1_RK0: MR19=0x808, MR18=0x4A70, DQSOSC=388, MR23=63, INC=174, DEC=116
4606 23:03:44.942578
4607 23:03:44.945965 ----->DramcWriteLeveling(PI) begin...
4608 23:03:44.949233 ==
4609 23:03:44.952415 Dram Type= 6, Freq= 0, CH_1, rank 1
4610 23:03:44.956017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4611 23:03:44.956101 ==
4612 23:03:44.959840 Write leveling (Byte 0): 31 => 31
4613 23:03:44.962859 Write leveling (Byte 1): 31 => 31
4614 23:03:44.965713 DramcWriteLeveling(PI) end<-----
4615 23:03:44.965796
4616 23:03:44.965863 ==
4617 23:03:44.969109 Dram Type= 6, Freq= 0, CH_1, rank 1
4618 23:03:44.972766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4619 23:03:44.972850 ==
4620 23:03:44.975754 [Gating] SW mode calibration
4621 23:03:44.982635 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4622 23:03:44.989330 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4623 23:03:44.992386 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4624 23:03:44.995721 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4625 23:03:45.002478 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4626 23:03:45.005483 0 9 12 | B1->B0 | 2d2d 3232 | 0 1 | (0 0) (1 0)
4627 23:03:45.009420 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4628 23:03:45.012463 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4629 23:03:45.018883 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4630 23:03:45.022330 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4631 23:03:45.025517 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4632 23:03:45.032349 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4633 23:03:45.035453 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4634 23:03:45.038946 0 10 12 | B1->B0 | 3b3b 3030 | 0 1 | (0 0) (0 0)
4635 23:03:45.045525 0 10 16 | B1->B0 | 4646 4444 | 0 1 | (0 0) (0 0)
4636 23:03:45.048949 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4637 23:03:45.052214 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4638 23:03:45.059258 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4639 23:03:45.062363 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4640 23:03:45.065969 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4641 23:03:45.072592 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4642 23:03:45.075859 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4643 23:03:45.079198 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 23:03:45.085597 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 23:03:45.089092 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 23:03:45.092067 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 23:03:45.098744 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 23:03:45.102536 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 23:03:45.105476 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 23:03:45.112257 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 23:03:45.115484 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4652 23:03:45.118751 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4653 23:03:45.122156 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4654 23:03:45.128687 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4655 23:03:45.132214 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4656 23:03:45.135309 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4657 23:03:45.142193 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4658 23:03:45.145335 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4659 23:03:45.148567 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4660 23:03:45.151816 Total UI for P1: 0, mck2ui 16
4661 23:03:45.155515 best dqsien dly found for B0: ( 0, 13, 12)
4662 23:03:45.158850 Total UI for P1: 0, mck2ui 16
4663 23:03:45.162053 best dqsien dly found for B1: ( 0, 13, 10)
4664 23:03:45.165359 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4665 23:03:45.168472 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4666 23:03:45.172027
4667 23:03:45.175274 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4668 23:03:45.178556 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4669 23:03:45.181840 [Gating] SW calibration Done
4670 23:03:45.181924 ==
4671 23:03:45.185287 Dram Type= 6, Freq= 0, CH_1, rank 1
4672 23:03:45.188884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4673 23:03:45.188967 ==
4674 23:03:45.189035 RX Vref Scan: 0
4675 23:03:45.189097
4676 23:03:45.192461 RX Vref 0 -> 0, step: 1
4677 23:03:45.192545
4678 23:03:45.195441 RX Delay -230 -> 252, step: 16
4679 23:03:45.198537 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4680 23:03:45.201768 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4681 23:03:45.208511 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4682 23:03:45.212030 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4683 23:03:45.215269 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4684 23:03:45.218747 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4685 23:03:45.225382 iDelay=218, Bit 6, Center 49 (-102 ~ 201) 304
4686 23:03:45.228776 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4687 23:03:45.232326 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4688 23:03:45.235579 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4689 23:03:45.238760 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4690 23:03:45.245440 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4691 23:03:45.248631 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4692 23:03:45.252209 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4693 23:03:45.255433 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4694 23:03:45.262200 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4695 23:03:45.262283 ==
4696 23:03:45.265299 Dram Type= 6, Freq= 0, CH_1, rank 1
4697 23:03:45.268709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4698 23:03:45.268793 ==
4699 23:03:45.268861 DQS Delay:
4700 23:03:45.271862 DQS0 = 0, DQS1 = 0
4701 23:03:45.271945 DQM Delay:
4702 23:03:45.275491 DQM0 = 50, DQM1 = 46
4703 23:03:45.275574 DQ Delay:
4704 23:03:45.279082 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4705 23:03:45.282089 DQ4 =49, DQ5 =65, DQ6 =49, DQ7 =49
4706 23:03:45.285348 DQ8 =25, DQ9 =33, DQ10 =49, DQ11 =41
4707 23:03:45.288623 DQ12 =57, DQ13 =49, DQ14 =57, DQ15 =57
4708 23:03:45.288706
4709 23:03:45.288772
4710 23:03:45.288833 ==
4711 23:03:45.292069 Dram Type= 6, Freq= 0, CH_1, rank 1
4712 23:03:45.295631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4713 23:03:45.295715 ==
4714 23:03:45.295782
4715 23:03:45.295844
4716 23:03:45.298800 TX Vref Scan disable
4717 23:03:45.302101 == TX Byte 0 ==
4718 23:03:45.305493 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4719 23:03:45.308779 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4720 23:03:45.312248 == TX Byte 1 ==
4721 23:03:45.315281 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4722 23:03:45.318489 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4723 23:03:45.318572 ==
4724 23:03:45.321959 Dram Type= 6, Freq= 0, CH_1, rank 1
4725 23:03:45.328534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4726 23:03:45.328619 ==
4727 23:03:45.328686
4728 23:03:45.328829
4729 23:03:45.328892 TX Vref Scan disable
4730 23:03:45.332999 == TX Byte 0 ==
4731 23:03:45.336065 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4732 23:03:45.339923 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4733 23:03:45.342566 == TX Byte 1 ==
4734 23:03:45.346143 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4735 23:03:45.352686 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4736 23:03:45.352770
4737 23:03:45.352836 [DATLAT]
4738 23:03:45.352898 Freq=600, CH1 RK1
4739 23:03:45.352958
4740 23:03:45.356235 DATLAT Default: 0x9
4741 23:03:45.356319 0, 0xFFFF, sum = 0
4742 23:03:45.359455 1, 0xFFFF, sum = 0
4743 23:03:45.359540 2, 0xFFFF, sum = 0
4744 23:03:45.362956 3, 0xFFFF, sum = 0
4745 23:03:45.363041 4, 0xFFFF, sum = 0
4746 23:03:45.366325 5, 0xFFFF, sum = 0
4747 23:03:45.369447 6, 0xFFFF, sum = 0
4748 23:03:45.369532 7, 0xFFFF, sum = 0
4749 23:03:45.369600 8, 0x0, sum = 1
4750 23:03:45.372807 9, 0x0, sum = 2
4751 23:03:45.372893 10, 0x0, sum = 3
4752 23:03:45.376005 11, 0x0, sum = 4
4753 23:03:45.376090 best_step = 9
4754 23:03:45.376156
4755 23:03:45.376218 ==
4756 23:03:45.379517 Dram Type= 6, Freq= 0, CH_1, rank 1
4757 23:03:45.385929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4758 23:03:45.386013 ==
4759 23:03:45.386079 RX Vref Scan: 0
4760 23:03:45.386142
4761 23:03:45.389478 RX Vref 0 -> 0, step: 1
4762 23:03:45.389562
4763 23:03:45.392860 RX Delay -179 -> 252, step: 8
4764 23:03:45.396307 iDelay=205, Bit 0, Center 52 (-83 ~ 188) 272
4765 23:03:45.403110 iDelay=205, Bit 1, Center 44 (-91 ~ 180) 272
4766 23:03:45.405931 iDelay=205, Bit 2, Center 40 (-99 ~ 180) 280
4767 23:03:45.409232 iDelay=205, Bit 3, Center 48 (-91 ~ 188) 280
4768 23:03:45.412581 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4769 23:03:45.416027 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4770 23:03:45.422855 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4771 23:03:45.426342 iDelay=205, Bit 7, Center 48 (-91 ~ 188) 280
4772 23:03:45.429246 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4773 23:03:45.432593 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4774 23:03:45.435758 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4775 23:03:45.442837 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4776 23:03:45.445840 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4777 23:03:45.449136 iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296
4778 23:03:45.452303 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4779 23:03:45.458916 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4780 23:03:45.458999 ==
4781 23:03:45.462175 Dram Type= 6, Freq= 0, CH_1, rank 1
4782 23:03:45.465461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4783 23:03:45.465564 ==
4784 23:03:45.465664 DQS Delay:
4785 23:03:45.469228 DQS0 = 0, DQS1 = 0
4786 23:03:45.469312 DQM Delay:
4787 23:03:45.472331 DQM0 = 49, DQM1 = 44
4788 23:03:45.472414 DQ Delay:
4789 23:03:45.475679 DQ0 =52, DQ1 =44, DQ2 =40, DQ3 =48
4790 23:03:45.479277 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4791 23:03:45.482705 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =40
4792 23:03:45.485746 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =56
4793 23:03:45.485829
4794 23:03:45.485896
4795 23:03:45.492194 [DQSOSCAuto] RK1, (LSB)MR18= 0x5b22, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
4796 23:03:45.495449 CH1 RK1: MR19=808, MR18=5B22
4797 23:03:45.502255 CH1_RK1: MR19=0x808, MR18=0x5B22, DQSOSC=392, MR23=63, INC=170, DEC=113
4798 23:03:45.505507 [RxdqsGatingPostProcess] freq 600
4799 23:03:45.512117 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4800 23:03:45.512230 Pre-setting of DQS Precalculation
4801 23:03:45.518929 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4802 23:03:45.525259 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4803 23:03:45.531977 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4804 23:03:45.532062
4805 23:03:45.532128
4806 23:03:45.535271 [Calibration Summary] 1200 Mbps
4807 23:03:45.539028 CH 0, Rank 0
4808 23:03:45.539111 SW Impedance : PASS
4809 23:03:45.541996 DUTY Scan : NO K
4810 23:03:45.545261 ZQ Calibration : PASS
4811 23:03:45.545344 Jitter Meter : NO K
4812 23:03:45.548574 CBT Training : PASS
4813 23:03:45.548657 Write leveling : PASS
4814 23:03:45.552213 RX DQS gating : PASS
4815 23:03:45.555436 RX DQ/DQS(RDDQC) : PASS
4816 23:03:45.555520 TX DQ/DQS : PASS
4817 23:03:45.558378 RX DATLAT : PASS
4818 23:03:45.561948 RX DQ/DQS(Engine): PASS
4819 23:03:45.562031 TX OE : NO K
4820 23:03:45.565046 All Pass.
4821 23:03:45.565130
4822 23:03:45.565197 CH 0, Rank 1
4823 23:03:45.568447 SW Impedance : PASS
4824 23:03:45.568531 DUTY Scan : NO K
4825 23:03:45.571737 ZQ Calibration : PASS
4826 23:03:45.575033 Jitter Meter : NO K
4827 23:03:45.575117 CBT Training : PASS
4828 23:03:45.578402 Write leveling : PASS
4829 23:03:45.581840 RX DQS gating : PASS
4830 23:03:45.581923 RX DQ/DQS(RDDQC) : PASS
4831 23:03:45.585451 TX DQ/DQS : PASS
4832 23:03:45.588600 RX DATLAT : PASS
4833 23:03:45.588683 RX DQ/DQS(Engine): PASS
4834 23:03:45.592177 TX OE : NO K
4835 23:03:45.592260 All Pass.
4836 23:03:45.592327
4837 23:03:45.595132 CH 1, Rank 0
4838 23:03:45.595232 SW Impedance : PASS
4839 23:03:45.598243 DUTY Scan : NO K
4840 23:03:45.602297 ZQ Calibration : PASS
4841 23:03:45.602381 Jitter Meter : NO K
4842 23:03:45.605052 CBT Training : PASS
4843 23:03:45.605135 Write leveling : PASS
4844 23:03:45.608539 RX DQS gating : PASS
4845 23:03:45.611885 RX DQ/DQS(RDDQC) : PASS
4846 23:03:45.611968 TX DQ/DQS : PASS
4847 23:03:45.614918 RX DATLAT : PASS
4848 23:03:45.618105 RX DQ/DQS(Engine): PASS
4849 23:03:45.618189 TX OE : NO K
4850 23:03:45.621511 All Pass.
4851 23:03:45.621594
4852 23:03:45.621660 CH 1, Rank 1
4853 23:03:45.625102 SW Impedance : PASS
4854 23:03:45.625186 DUTY Scan : NO K
4855 23:03:45.628121 ZQ Calibration : PASS
4856 23:03:45.631514 Jitter Meter : NO K
4857 23:03:45.631598 CBT Training : PASS
4858 23:03:45.635397 Write leveling : PASS
4859 23:03:45.638341 RX DQS gating : PASS
4860 23:03:45.638432 RX DQ/DQS(RDDQC) : PASS
4861 23:03:45.641733 TX DQ/DQS : PASS
4862 23:03:45.644730 RX DATLAT : PASS
4863 23:03:45.644814 RX DQ/DQS(Engine): PASS
4864 23:03:45.648143 TX OE : NO K
4865 23:03:45.648226 All Pass.
4866 23:03:45.648293
4867 23:03:45.651569 DramC Write-DBI off
4868 23:03:45.655023 PER_BANK_REFRESH: Hybrid Mode
4869 23:03:45.655106 TX_TRACKING: ON
4870 23:03:45.664828 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4871 23:03:45.668200 [FAST_K] Save calibration result to emmc
4872 23:03:45.671476 dramc_set_vcore_voltage set vcore to 662500
4873 23:03:45.671560 Read voltage for 933, 3
4874 23:03:45.674861 Vio18 = 0
4875 23:03:45.674945 Vcore = 662500
4876 23:03:45.675012 Vdram = 0
4877 23:03:45.678357 Vddq = 0
4878 23:03:45.678462 Vmddr = 0
4879 23:03:45.685031 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4880 23:03:45.688025 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4881 23:03:45.691547 MEM_TYPE=3, freq_sel=17
4882 23:03:45.694745 sv_algorithm_assistance_LP4_1600
4883 23:03:45.698111 ============ PULL DRAM RESETB DOWN ============
4884 23:03:45.701434 ========== PULL DRAM RESETB DOWN end =========
4885 23:03:45.708213 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4886 23:03:45.711386 ===================================
4887 23:03:45.711470 LPDDR4 DRAM CONFIGURATION
4888 23:03:45.714819 ===================================
4889 23:03:45.718229 EX_ROW_EN[0] = 0x0
4890 23:03:45.718331 EX_ROW_EN[1] = 0x0
4891 23:03:45.721337 LP4Y_EN = 0x0
4892 23:03:45.724741 WORK_FSP = 0x0
4893 23:03:45.724840 WL = 0x3
4894 23:03:45.728395 RL = 0x3
4895 23:03:45.728498 BL = 0x2
4896 23:03:45.731210 RPST = 0x0
4897 23:03:45.731305 RD_PRE = 0x0
4898 23:03:45.734339 WR_PRE = 0x1
4899 23:03:45.734473 WR_PST = 0x0
4900 23:03:45.738027 DBI_WR = 0x0
4901 23:03:45.738125 DBI_RD = 0x0
4902 23:03:45.741168 OTF = 0x1
4903 23:03:45.745013 ===================================
4904 23:03:45.748495 ===================================
4905 23:03:45.748595 ANA top config
4906 23:03:45.751345 ===================================
4907 23:03:45.754747 DLL_ASYNC_EN = 0
4908 23:03:45.758225 ALL_SLAVE_EN = 1
4909 23:03:45.758333 NEW_RANK_MODE = 1
4910 23:03:45.761502 DLL_IDLE_MODE = 1
4911 23:03:45.764634 LP45_APHY_COMB_EN = 1
4912 23:03:45.767964 TX_ODT_DIS = 1
4913 23:03:45.771251 NEW_8X_MODE = 1
4914 23:03:45.774577 ===================================
4915 23:03:45.778326 ===================================
4916 23:03:45.778431 data_rate = 1866
4917 23:03:45.781037 CKR = 1
4918 23:03:45.784270 DQ_P2S_RATIO = 8
4919 23:03:45.787795 ===================================
4920 23:03:45.791010 CA_P2S_RATIO = 8
4921 23:03:45.794107 DQ_CA_OPEN = 0
4922 23:03:45.797393 DQ_SEMI_OPEN = 0
4923 23:03:45.797489 CA_SEMI_OPEN = 0
4924 23:03:45.800763 CA_FULL_RATE = 0
4925 23:03:45.804038 DQ_CKDIV4_EN = 1
4926 23:03:45.807694 CA_CKDIV4_EN = 1
4927 23:03:45.810917 CA_PREDIV_EN = 0
4928 23:03:45.814055 PH8_DLY = 0
4929 23:03:45.814154 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4930 23:03:45.817395 DQ_AAMCK_DIV = 4
4931 23:03:45.820820 CA_AAMCK_DIV = 4
4932 23:03:45.824271 CA_ADMCK_DIV = 4
4933 23:03:45.827450 DQ_TRACK_CA_EN = 0
4934 23:03:45.831206 CA_PICK = 933
4935 23:03:45.834253 CA_MCKIO = 933
4936 23:03:45.834359 MCKIO_SEMI = 0
4937 23:03:45.837393 PLL_FREQ = 3732
4938 23:03:45.840991 DQ_UI_PI_RATIO = 32
4939 23:03:45.844502 CA_UI_PI_RATIO = 0
4940 23:03:45.847455 ===================================
4941 23:03:45.850641 ===================================
4942 23:03:45.854240 memory_type:LPDDR4
4943 23:03:45.854339 GP_NUM : 10
4944 23:03:45.857354 SRAM_EN : 1
4945 23:03:45.857460 MD32_EN : 0
4946 23:03:45.861170 ===================================
4947 23:03:45.864139 [ANA_INIT] >>>>>>>>>>>>>>
4948 23:03:45.867198 <<<<<< [CONFIGURE PHASE]: ANA_TX
4949 23:03:45.870737 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4950 23:03:45.873995 ===================================
4951 23:03:45.877336 data_rate = 1866,PCW = 0X8f00
4952 23:03:45.880574 ===================================
4953 23:03:45.884172 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4954 23:03:45.890736 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4955 23:03:45.894170 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4956 23:03:45.900486 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4957 23:03:45.904114 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4958 23:03:45.907209 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4959 23:03:45.907309 [ANA_INIT] flow start
4960 23:03:45.910642 [ANA_INIT] PLL >>>>>>>>
4961 23:03:45.914102 [ANA_INIT] PLL <<<<<<<<
4962 23:03:45.914198 [ANA_INIT] MIDPI >>>>>>>>
4963 23:03:45.917476 [ANA_INIT] MIDPI <<<<<<<<
4964 23:03:45.920439 [ANA_INIT] DLL >>>>>>>>
4965 23:03:45.920535 [ANA_INIT] flow end
4966 23:03:45.926938 ============ LP4 DIFF to SE enter ============
4967 23:03:45.930329 ============ LP4 DIFF to SE exit ============
4968 23:03:45.933816 [ANA_INIT] <<<<<<<<<<<<<
4969 23:03:45.937225 [Flow] Enable top DCM control >>>>>
4970 23:03:45.940533 [Flow] Enable top DCM control <<<<<
4971 23:03:45.940631 Enable DLL master slave shuffle
4972 23:03:45.947003 ==============================================================
4973 23:03:45.950509 Gating Mode config
4974 23:03:45.953620 ==============================================================
4975 23:03:45.956880 Config description:
4976 23:03:45.966753 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4977 23:03:45.973808 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4978 23:03:45.977132 SELPH_MODE 0: By rank 1: By Phase
4979 23:03:45.983564 ==============================================================
4980 23:03:45.987398 GAT_TRACK_EN = 1
4981 23:03:45.990568 RX_GATING_MODE = 2
4982 23:03:45.993569 RX_GATING_TRACK_MODE = 2
4983 23:03:45.993652 SELPH_MODE = 1
4984 23:03:45.997233 PICG_EARLY_EN = 1
4985 23:03:46.000170 VALID_LAT_VALUE = 1
4986 23:03:46.006859 ==============================================================
4987 23:03:46.010550 Enter into Gating configuration >>>>
4988 23:03:46.013713 Exit from Gating configuration <<<<
4989 23:03:46.016584 Enter into DVFS_PRE_config >>>>>
4990 23:03:46.026740 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4991 23:03:46.030168 Exit from DVFS_PRE_config <<<<<
4992 23:03:46.033452 Enter into PICG configuration >>>>
4993 23:03:46.036735 Exit from PICG configuration <<<<
4994 23:03:46.040471 [RX_INPUT] configuration >>>>>
4995 23:03:46.043407 [RX_INPUT] configuration <<<<<
4996 23:03:46.046676 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4997 23:03:46.053723 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4998 23:03:46.060383 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4999 23:03:46.066955 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5000 23:03:46.070098 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5001 23:03:46.076678 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5002 23:03:46.080030 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5003 23:03:46.086608 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5004 23:03:46.089792 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5005 23:03:46.093232 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5006 23:03:46.096698 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5007 23:03:46.103054 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5008 23:03:46.106768 ===================================
5009 23:03:46.109861 LPDDR4 DRAM CONFIGURATION
5010 23:03:46.113236 ===================================
5011 23:03:46.113318 EX_ROW_EN[0] = 0x0
5012 23:03:46.116841 EX_ROW_EN[1] = 0x0
5013 23:03:46.116923 LP4Y_EN = 0x0
5014 23:03:46.120004 WORK_FSP = 0x0
5015 23:03:46.120086 WL = 0x3
5016 23:03:46.122969 RL = 0x3
5017 23:03:46.123051 BL = 0x2
5018 23:03:46.126723 RPST = 0x0
5019 23:03:46.126804 RD_PRE = 0x0
5020 23:03:46.129909 WR_PRE = 0x1
5021 23:03:46.129991 WR_PST = 0x0
5022 23:03:46.133408 DBI_WR = 0x0
5023 23:03:46.133489 DBI_RD = 0x0
5024 23:03:46.136438 OTF = 0x1
5025 23:03:46.139896 ===================================
5026 23:03:46.143450 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5027 23:03:46.146486 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5028 23:03:46.153205 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5029 23:03:46.156355 ===================================
5030 23:03:46.156437 LPDDR4 DRAM CONFIGURATION
5031 23:03:46.159898 ===================================
5032 23:03:46.163129 EX_ROW_EN[0] = 0x10
5033 23:03:46.166756 EX_ROW_EN[1] = 0x0
5034 23:03:46.166838 LP4Y_EN = 0x0
5035 23:03:46.169950 WORK_FSP = 0x0
5036 23:03:46.170032 WL = 0x3
5037 23:03:46.173275 RL = 0x3
5038 23:03:46.173357 BL = 0x2
5039 23:03:46.176421 RPST = 0x0
5040 23:03:46.176503 RD_PRE = 0x0
5041 23:03:46.179899 WR_PRE = 0x1
5042 23:03:46.179982 WR_PST = 0x0
5043 23:03:46.183037 DBI_WR = 0x0
5044 23:03:46.183120 DBI_RD = 0x0
5045 23:03:46.186545 OTF = 0x1
5046 23:03:46.189705 ===================================
5047 23:03:46.196419 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5048 23:03:46.199799 nWR fixed to 30
5049 23:03:46.199882 [ModeRegInit_LP4] CH0 RK0
5050 23:03:46.203036 [ModeRegInit_LP4] CH0 RK1
5051 23:03:46.206255 [ModeRegInit_LP4] CH1 RK0
5052 23:03:46.209653 [ModeRegInit_LP4] CH1 RK1
5053 23:03:46.209735 match AC timing 9
5054 23:03:46.212944 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5055 23:03:46.219547 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5056 23:03:46.223104 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5057 23:03:46.229716 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5058 23:03:46.232842 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5059 23:03:46.232928 ==
5060 23:03:46.236350 Dram Type= 6, Freq= 0, CH_0, rank 0
5061 23:03:46.239944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5062 23:03:46.240028 ==
5063 23:03:46.246023 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5064 23:03:46.252981 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5065 23:03:46.256180 [CA 0] Center 37 (7~68) winsize 62
5066 23:03:46.259508 [CA 1] Center 38 (7~69) winsize 63
5067 23:03:46.262814 [CA 2] Center 35 (5~66) winsize 62
5068 23:03:46.266066 [CA 3] Center 34 (4~65) winsize 62
5069 23:03:46.269345 [CA 4] Center 34 (4~64) winsize 61
5070 23:03:46.272658 [CA 5] Center 33 (3~64) winsize 62
5071 23:03:46.272740
5072 23:03:46.275976 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5073 23:03:46.276059
5074 23:03:46.279531 [CATrainingPosCal] consider 1 rank data
5075 23:03:46.283060 u2DelayCellTimex100 = 270/100 ps
5076 23:03:46.285866 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5077 23:03:46.289455 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5078 23:03:46.292765 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5079 23:03:46.296046 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5080 23:03:46.299479 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5081 23:03:46.302931 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5082 23:03:46.303014
5083 23:03:46.306007 CA PerBit enable=1, Macro0, CA PI delay=33
5084 23:03:46.306115
5085 23:03:46.309304 [CBTSetCACLKResult] CA Dly = 33
5086 23:03:46.312478 CS Dly: 7 (0~38)
5087 23:03:46.312577 ==
5088 23:03:46.315913 Dram Type= 6, Freq= 0, CH_0, rank 1
5089 23:03:46.319149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5090 23:03:46.319233 ==
5091 23:03:46.325665 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5092 23:03:46.332390 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5093 23:03:46.335578 [CA 0] Center 38 (8~69) winsize 62
5094 23:03:46.339026 [CA 1] Center 38 (8~69) winsize 62
5095 23:03:46.342317 [CA 2] Center 36 (6~66) winsize 61
5096 23:03:46.345593 [CA 3] Center 35 (5~66) winsize 62
5097 23:03:46.348846 [CA 4] Center 34 (4~65) winsize 62
5098 23:03:46.352053 [CA 5] Center 34 (4~64) winsize 61
5099 23:03:46.352136
5100 23:03:46.355535 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5101 23:03:46.355618
5102 23:03:46.358793 [CATrainingPosCal] consider 2 rank data
5103 23:03:46.362368 u2DelayCellTimex100 = 270/100 ps
5104 23:03:46.365431 CA0 delay=38 (8~68),Diff = 4 PI (24 cell)
5105 23:03:46.368963 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5106 23:03:46.372073 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5107 23:03:46.375732 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5108 23:03:46.379002 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5109 23:03:46.382027 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5110 23:03:46.385582
5111 23:03:46.388956 CA PerBit enable=1, Macro0, CA PI delay=34
5112 23:03:46.389039
5113 23:03:46.392262 [CBTSetCACLKResult] CA Dly = 34
5114 23:03:46.392345 CS Dly: 7 (0~39)
5115 23:03:46.392411
5116 23:03:46.395282 ----->DramcWriteLeveling(PI) begin...
5117 23:03:46.395366 ==
5118 23:03:46.398551 Dram Type= 6, Freq= 0, CH_0, rank 0
5119 23:03:46.401951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5120 23:03:46.405138 ==
5121 23:03:46.405220 Write leveling (Byte 0): 33 => 33
5122 23:03:46.408590 Write leveling (Byte 1): 31 => 31
5123 23:03:46.411701 DramcWriteLeveling(PI) end<-----
5124 23:03:46.411804
5125 23:03:46.411874 ==
5126 23:03:46.415010 Dram Type= 6, Freq= 0, CH_0, rank 0
5127 23:03:46.421699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5128 23:03:46.421783 ==
5129 23:03:46.421849 [Gating] SW mode calibration
5130 23:03:46.431722 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5131 23:03:46.434986 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5132 23:03:46.441588 0 14 0 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
5133 23:03:46.444953 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5134 23:03:46.448271 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5135 23:03:46.454712 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5136 23:03:46.458104 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5137 23:03:46.461853 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5138 23:03:46.468281 0 14 24 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
5139 23:03:46.471882 0 14 28 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)
5140 23:03:46.474721 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5141 23:03:46.481462 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5142 23:03:46.484694 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5143 23:03:46.488035 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5144 23:03:46.494462 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5145 23:03:46.497912 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5146 23:03:46.501270 0 15 24 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
5147 23:03:46.504708 0 15 28 | B1->B0 | 2d2d 4444 | 0 0 | (1 1) (0 0)
5148 23:03:46.510915 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5149 23:03:46.514312 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5150 23:03:46.517772 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5151 23:03:46.524504 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5152 23:03:46.527639 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5153 23:03:46.530957 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5154 23:03:46.537680 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5155 23:03:46.541276 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5156 23:03:46.544408 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 23:03:46.550936 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5158 23:03:46.554572 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5159 23:03:46.557528 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5160 23:03:46.564529 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 23:03:46.567786 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 23:03:46.570957 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 23:03:46.577759 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 23:03:46.581333 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5165 23:03:46.584148 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5166 23:03:46.591041 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5167 23:03:46.594197 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5168 23:03:46.597791 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5169 23:03:46.604586 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5170 23:03:46.607449 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5171 23:03:46.611156 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5172 23:03:46.614143 Total UI for P1: 0, mck2ui 16
5173 23:03:46.617218 best dqsien dly found for B0: ( 1, 2, 24)
5174 23:03:46.620740 Total UI for P1: 0, mck2ui 16
5175 23:03:46.623955 best dqsien dly found for B1: ( 1, 2, 26)
5176 23:03:46.627618 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5177 23:03:46.630576 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5178 23:03:46.630660
5179 23:03:46.634072 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5180 23:03:46.640688 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5181 23:03:46.640771 [Gating] SW calibration Done
5182 23:03:46.640837 ==
5183 23:03:46.644252 Dram Type= 6, Freq= 0, CH_0, rank 0
5184 23:03:46.650782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5185 23:03:46.650868 ==
5186 23:03:46.650935 RX Vref Scan: 0
5187 23:03:46.650999
5188 23:03:46.654376 RX Vref 0 -> 0, step: 1
5189 23:03:46.654503
5190 23:03:46.657301 RX Delay -80 -> 252, step: 8
5191 23:03:46.660791 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5192 23:03:46.663866 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5193 23:03:46.667549 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5194 23:03:46.670981 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5195 23:03:46.677194 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5196 23:03:46.680950 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5197 23:03:46.684342 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5198 23:03:46.687512 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5199 23:03:46.690995 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5200 23:03:46.694017 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5201 23:03:46.700622 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5202 23:03:46.703688 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5203 23:03:46.707015 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5204 23:03:46.710581 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5205 23:03:46.713810 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5206 23:03:46.720446 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5207 23:03:46.720529 ==
5208 23:03:46.723686 Dram Type= 6, Freq= 0, CH_0, rank 0
5209 23:03:46.727190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5210 23:03:46.727273 ==
5211 23:03:46.727339 DQS Delay:
5212 23:03:46.730296 DQS0 = 0, DQS1 = 0
5213 23:03:46.730377 DQM Delay:
5214 23:03:46.733710 DQM0 = 105, DQM1 = 90
5215 23:03:46.733792 DQ Delay:
5216 23:03:46.737773 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5217 23:03:46.740709 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115
5218 23:03:46.744194 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5219 23:03:46.747141 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =99
5220 23:03:46.747227
5221 23:03:46.747291
5222 23:03:46.747351 ==
5223 23:03:46.750421 Dram Type= 6, Freq= 0, CH_0, rank 0
5224 23:03:46.753822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5225 23:03:46.753905 ==
5226 23:03:46.757292
5227 23:03:46.757373
5228 23:03:46.757439 TX Vref Scan disable
5229 23:03:46.760413 == TX Byte 0 ==
5230 23:03:46.763940 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5231 23:03:46.767001 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5232 23:03:46.770704 == TX Byte 1 ==
5233 23:03:46.774277 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5234 23:03:46.777144 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5235 23:03:46.777226 ==
5236 23:03:46.780164 Dram Type= 6, Freq= 0, CH_0, rank 0
5237 23:03:46.786815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5238 23:03:46.786898 ==
5239 23:03:46.786964
5240 23:03:46.787024
5241 23:03:46.787082 TX Vref Scan disable
5242 23:03:46.791141 == TX Byte 0 ==
5243 23:03:46.794722 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5244 23:03:46.801046 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5245 23:03:46.801132 == TX Byte 1 ==
5246 23:03:46.804394 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5247 23:03:46.808035 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5248 23:03:46.811294
5249 23:03:46.811376 [DATLAT]
5250 23:03:46.811476 Freq=933, CH0 RK0
5251 23:03:46.811571
5252 23:03:46.814421 DATLAT Default: 0xd
5253 23:03:46.814502 0, 0xFFFF, sum = 0
5254 23:03:46.817778 1, 0xFFFF, sum = 0
5255 23:03:46.817861 2, 0xFFFF, sum = 0
5256 23:03:46.821313 3, 0xFFFF, sum = 0
5257 23:03:46.821399 4, 0xFFFF, sum = 0
5258 23:03:46.825067 5, 0xFFFF, sum = 0
5259 23:03:46.825151 6, 0xFFFF, sum = 0
5260 23:03:46.828100 7, 0xFFFF, sum = 0
5261 23:03:46.831360 8, 0xFFFF, sum = 0
5262 23:03:46.831449 9, 0xFFFF, sum = 0
5263 23:03:46.834483 10, 0x0, sum = 1
5264 23:03:46.834567 11, 0x0, sum = 2
5265 23:03:46.834634 12, 0x0, sum = 3
5266 23:03:46.837750 13, 0x0, sum = 4
5267 23:03:46.837834 best_step = 11
5268 23:03:46.837901
5269 23:03:46.837962 ==
5270 23:03:46.841005 Dram Type= 6, Freq= 0, CH_0, rank 0
5271 23:03:46.848267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5272 23:03:46.848351 ==
5273 23:03:46.848417 RX Vref Scan: 1
5274 23:03:46.848479
5275 23:03:46.851093 RX Vref 0 -> 0, step: 1
5276 23:03:46.851176
5277 23:03:46.854295 RX Delay -53 -> 252, step: 4
5278 23:03:46.854424
5279 23:03:46.857945 Set Vref, RX VrefLevel [Byte0]: 59
5280 23:03:46.861495 [Byte1]: 49
5281 23:03:46.861578
5282 23:03:46.864735 Final RX Vref Byte 0 = 59 to rank0
5283 23:03:46.867900 Final RX Vref Byte 1 = 49 to rank0
5284 23:03:46.871376 Final RX Vref Byte 0 = 59 to rank1
5285 23:03:46.874366 Final RX Vref Byte 1 = 49 to rank1==
5286 23:03:46.877711 Dram Type= 6, Freq= 0, CH_0, rank 0
5287 23:03:46.881250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5288 23:03:46.881333 ==
5289 23:03:46.884487 DQS Delay:
5290 23:03:46.884569 DQS0 = 0, DQS1 = 0
5291 23:03:46.887585 DQM Delay:
5292 23:03:46.887668 DQM0 = 108, DQM1 = 92
5293 23:03:46.887734 DQ Delay:
5294 23:03:46.891464 DQ0 =106, DQ1 =108, DQ2 =104, DQ3 =106
5295 23:03:46.897852 DQ4 =108, DQ5 =100, DQ6 =118, DQ7 =114
5296 23:03:46.897941 DQ8 =84, DQ9 =78, DQ10 =92, DQ11 =90
5297 23:03:46.904193 DQ12 =98, DQ13 =94, DQ14 =102, DQ15 =98
5298 23:03:46.904276
5299 23:03:46.904342
5300 23:03:46.910872 [DQSOSCAuto] RK0, (LSB)MR18= 0x2824, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 409 ps
5301 23:03:46.914276 CH0 RK0: MR19=505, MR18=2824
5302 23:03:46.920872 CH0_RK0: MR19=0x505, MR18=0x2824, DQSOSC=409, MR23=63, INC=64, DEC=43
5303 23:03:46.920954
5304 23:03:46.924302 ----->DramcWriteLeveling(PI) begin...
5305 23:03:46.924386 ==
5306 23:03:46.927601 Dram Type= 6, Freq= 0, CH_0, rank 1
5307 23:03:46.930742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5308 23:03:46.930825 ==
5309 23:03:46.934344 Write leveling (Byte 0): 31 => 31
5310 23:03:46.937480 Write leveling (Byte 1): 29 => 29
5311 23:03:46.940885 DramcWriteLeveling(PI) end<-----
5312 23:03:46.940966
5313 23:03:46.941029 ==
5314 23:03:46.944363 Dram Type= 6, Freq= 0, CH_0, rank 1
5315 23:03:46.947701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5316 23:03:46.947783 ==
5317 23:03:46.950937 [Gating] SW mode calibration
5318 23:03:46.957385 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5319 23:03:46.964089 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5320 23:03:46.967699 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5321 23:03:46.970694 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5322 23:03:46.977562 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5323 23:03:46.980667 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5324 23:03:46.983886 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5325 23:03:46.990530 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5326 23:03:46.994030 0 14 24 | B1->B0 | 3434 3333 | 1 1 | (1 0) (1 1)
5327 23:03:46.997350 0 14 28 | B1->B0 | 2f2f 2525 | 0 0 | (0 0) (0 0)
5328 23:03:47.004040 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5329 23:03:47.007780 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5330 23:03:47.010713 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5331 23:03:47.017421 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5332 23:03:47.020740 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5333 23:03:47.024181 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5334 23:03:47.030574 0 15 24 | B1->B0 | 2424 2e2e | 0 0 | (0 0) (1 1)
5335 23:03:47.033701 0 15 28 | B1->B0 | 3b3b 4343 | 0 0 | (0 0) (0 0)
5336 23:03:47.037123 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5337 23:03:47.043963 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5338 23:03:47.047151 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5339 23:03:47.050513 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5340 23:03:47.057156 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5341 23:03:47.060824 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5342 23:03:47.063662 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5343 23:03:47.070683 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5344 23:03:47.074035 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5345 23:03:47.077456 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5346 23:03:47.084116 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5347 23:03:47.087032 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5348 23:03:47.090411 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5349 23:03:47.097001 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5350 23:03:47.100671 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5351 23:03:47.103731 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5352 23:03:47.107235 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5353 23:03:47.113946 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5354 23:03:47.117006 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5355 23:03:47.120468 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5356 23:03:47.127517 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5357 23:03:47.130682 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5358 23:03:47.133529 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5359 23:03:47.140131 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5360 23:03:47.143459 Total UI for P1: 0, mck2ui 16
5361 23:03:47.146933 best dqsien dly found for B0: ( 1, 2, 26)
5362 23:03:47.147017 Total UI for P1: 0, mck2ui 16
5363 23:03:47.153905 best dqsien dly found for B1: ( 1, 2, 24)
5364 23:03:47.157068 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5365 23:03:47.160320 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5366 23:03:47.160403
5367 23:03:47.163852 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5368 23:03:47.167018 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5369 23:03:47.170113 [Gating] SW calibration Done
5370 23:03:47.170221 ==
5371 23:03:47.173887 Dram Type= 6, Freq= 0, CH_0, rank 1
5372 23:03:47.176811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5373 23:03:47.176901 ==
5374 23:03:47.180141 RX Vref Scan: 0
5375 23:03:47.180223
5376 23:03:47.180290 RX Vref 0 -> 0, step: 1
5377 23:03:47.180351
5378 23:03:47.183802 RX Delay -80 -> 252, step: 8
5379 23:03:47.186703 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5380 23:03:47.193585 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5381 23:03:47.196548 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5382 23:03:47.200381 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5383 23:03:47.203436 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5384 23:03:47.206705 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5385 23:03:47.209855 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5386 23:03:47.216411 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5387 23:03:47.219872 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5388 23:03:47.223577 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5389 23:03:47.226484 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5390 23:03:47.229838 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5391 23:03:47.236466 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5392 23:03:47.240083 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5393 23:03:47.243248 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5394 23:03:47.246788 iDelay=208, Bit 15, Center 95 (8 ~ 183) 176
5395 23:03:47.246871 ==
5396 23:03:47.250763 Dram Type= 6, Freq= 0, CH_0, rank 1
5397 23:03:47.253737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5398 23:03:47.253831 ==
5399 23:03:47.256602 DQS Delay:
5400 23:03:47.256685 DQS0 = 0, DQS1 = 0
5401 23:03:47.260189 DQM Delay:
5402 23:03:47.260272 DQM0 = 105, DQM1 = 90
5403 23:03:47.260338 DQ Delay:
5404 23:03:47.263523 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5405 23:03:47.266628 DQ4 =107, DQ5 =99, DQ6 =115, DQ7 =111
5406 23:03:47.269966 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5407 23:03:47.273639 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =95
5408 23:03:47.273722
5409 23:03:47.277028
5410 23:03:47.277111 ==
5411 23:03:47.280020 Dram Type= 6, Freq= 0, CH_0, rank 1
5412 23:03:47.283299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5413 23:03:47.283383 ==
5414 23:03:47.283450
5415 23:03:47.283511
5416 23:03:47.286476 TX Vref Scan disable
5417 23:03:47.286560 == TX Byte 0 ==
5418 23:03:47.293105 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5419 23:03:47.296440 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5420 23:03:47.296524 == TX Byte 1 ==
5421 23:03:47.303085 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5422 23:03:47.307019 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5423 23:03:47.307102 ==
5424 23:03:47.310089 Dram Type= 6, Freq= 0, CH_0, rank 1
5425 23:03:47.313579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5426 23:03:47.313663 ==
5427 23:03:47.313731
5428 23:03:47.313794
5429 23:03:47.316560 TX Vref Scan disable
5430 23:03:47.320385 == TX Byte 0 ==
5431 23:03:47.323664 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5432 23:03:47.326900 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5433 23:03:47.329773 == TX Byte 1 ==
5434 23:03:47.333010 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5435 23:03:47.336730 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5436 23:03:47.336813
5437 23:03:47.339611 [DATLAT]
5438 23:03:47.339694 Freq=933, CH0 RK1
5439 23:03:47.339761
5440 23:03:47.343041 DATLAT Default: 0xb
5441 23:03:47.343125 0, 0xFFFF, sum = 0
5442 23:03:47.346482 1, 0xFFFF, sum = 0
5443 23:03:47.346601 2, 0xFFFF, sum = 0
5444 23:03:47.349775 3, 0xFFFF, sum = 0
5445 23:03:47.349860 4, 0xFFFF, sum = 0
5446 23:03:47.352902 5, 0xFFFF, sum = 0
5447 23:03:47.352987 6, 0xFFFF, sum = 0
5448 23:03:47.356233 7, 0xFFFF, sum = 0
5449 23:03:47.356318 8, 0xFFFF, sum = 0
5450 23:03:47.359787 9, 0xFFFF, sum = 0
5451 23:03:47.359871 10, 0x0, sum = 1
5452 23:03:47.362989 11, 0x0, sum = 2
5453 23:03:47.363073 12, 0x0, sum = 3
5454 23:03:47.366172 13, 0x0, sum = 4
5455 23:03:47.366256 best_step = 11
5456 23:03:47.366323
5457 23:03:47.366392 ==
5458 23:03:47.369409 Dram Type= 6, Freq= 0, CH_0, rank 1
5459 23:03:47.376036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5460 23:03:47.376120 ==
5461 23:03:47.376187 RX Vref Scan: 0
5462 23:03:47.376250
5463 23:03:47.379316 RX Vref 0 -> 0, step: 1
5464 23:03:47.379400
5465 23:03:47.382935 RX Delay -53 -> 252, step: 4
5466 23:03:47.386086 iDelay=199, Bit 0, Center 102 (15 ~ 190) 176
5467 23:03:47.389431 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5468 23:03:47.396035 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5469 23:03:47.399635 iDelay=199, Bit 3, Center 98 (15 ~ 182) 168
5470 23:03:47.402739 iDelay=199, Bit 4, Center 104 (19 ~ 190) 172
5471 23:03:47.405803 iDelay=199, Bit 5, Center 100 (15 ~ 186) 172
5472 23:03:47.409167 iDelay=199, Bit 6, Center 110 (23 ~ 198) 176
5473 23:03:47.415818 iDelay=199, Bit 7, Center 110 (23 ~ 198) 176
5474 23:03:47.418902 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5475 23:03:47.422207 iDelay=199, Bit 9, Center 78 (-5 ~ 162) 168
5476 23:03:47.425654 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5477 23:03:47.429168 iDelay=199, Bit 11, Center 92 (11 ~ 174) 164
5478 23:03:47.435506 iDelay=199, Bit 12, Center 98 (15 ~ 182) 168
5479 23:03:47.439153 iDelay=199, Bit 13, Center 96 (15 ~ 178) 164
5480 23:03:47.442158 iDelay=199, Bit 14, Center 100 (15 ~ 186) 172
5481 23:03:47.445516 iDelay=199, Bit 15, Center 100 (19 ~ 182) 164
5482 23:03:47.445593 ==
5483 23:03:47.449020 Dram Type= 6, Freq= 0, CH_0, rank 1
5484 23:03:47.452343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5485 23:03:47.455676 ==
5486 23:03:47.455778 DQS Delay:
5487 23:03:47.455869 DQS0 = 0, DQS1 = 0
5488 23:03:47.458826 DQM Delay:
5489 23:03:47.458932 DQM0 = 104, DQM1 = 92
5490 23:03:47.462091 DQ Delay:
5491 23:03:47.465528 DQ0 =102, DQ1 =106, DQ2 =102, DQ3 =98
5492 23:03:47.468849 DQ4 =104, DQ5 =100, DQ6 =110, DQ7 =110
5493 23:03:47.472267 DQ8 =84, DQ9 =78, DQ10 =94, DQ11 =92
5494 23:03:47.475618 DQ12 =98, DQ13 =96, DQ14 =100, DQ15 =100
5495 23:03:47.475717
5496 23:03:47.475817
5497 23:03:47.481955 [DQSOSCAuto] RK1, (LSB)MR18= 0x2606, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 409 ps
5498 23:03:47.485462 CH0 RK1: MR19=505, MR18=2606
5499 23:03:47.491691 CH0_RK1: MR19=0x505, MR18=0x2606, DQSOSC=409, MR23=63, INC=64, DEC=43
5500 23:03:47.495370 [RxdqsGatingPostProcess] freq 933
5501 23:03:47.501849 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5502 23:03:47.501958 best DQS0 dly(2T, 0.5T) = (0, 10)
5503 23:03:47.504939 best DQS1 dly(2T, 0.5T) = (0, 10)
5504 23:03:47.508380 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5505 23:03:47.512048 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5506 23:03:47.515180 best DQS0 dly(2T, 0.5T) = (0, 10)
5507 23:03:47.518813 best DQS1 dly(2T, 0.5T) = (0, 10)
5508 23:03:47.522234 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5509 23:03:47.525324 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5510 23:03:47.528438 Pre-setting of DQS Precalculation
5511 23:03:47.535379 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5512 23:03:47.535456 ==
5513 23:03:47.538520 Dram Type= 6, Freq= 0, CH_1, rank 0
5514 23:03:47.541905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5515 23:03:47.542011 ==
5516 23:03:47.545280 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5517 23:03:47.551585 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5518 23:03:47.555518 [CA 0] Center 37 (7~68) winsize 62
5519 23:03:47.559044 [CA 1] Center 37 (7~68) winsize 62
5520 23:03:47.562481 [CA 2] Center 35 (6~65) winsize 60
5521 23:03:47.565842 [CA 3] Center 34 (4~65) winsize 62
5522 23:03:47.569117 [CA 4] Center 35 (5~66) winsize 62
5523 23:03:47.572193 [CA 5] Center 34 (4~65) winsize 62
5524 23:03:47.572274
5525 23:03:47.575308 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5526 23:03:47.575392
5527 23:03:47.578965 [CATrainingPosCal] consider 1 rank data
5528 23:03:47.582073 u2DelayCellTimex100 = 270/100 ps
5529 23:03:47.585134 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5530 23:03:47.591864 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5531 23:03:47.595123 CA2 delay=35 (6~65),Diff = 1 PI (6 cell)
5532 23:03:47.598354 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5533 23:03:47.601784 CA4 delay=35 (5~66),Diff = 1 PI (6 cell)
5534 23:03:47.605130 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
5535 23:03:47.605229
5536 23:03:47.608408 CA PerBit enable=1, Macro0, CA PI delay=34
5537 23:03:47.608491
5538 23:03:47.611933 [CBTSetCACLKResult] CA Dly = 34
5539 23:03:47.615475 CS Dly: 6 (0~37)
5540 23:03:47.615557 ==
5541 23:03:47.618382 Dram Type= 6, Freq= 0, CH_1, rank 1
5542 23:03:47.621643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5543 23:03:47.621726 ==
5544 23:03:47.628301 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5545 23:03:47.631836 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5546 23:03:47.635747 [CA 0] Center 37 (7~68) winsize 62
5547 23:03:47.639101 [CA 1] Center 38 (8~69) winsize 62
5548 23:03:47.642343 [CA 2] Center 35 (5~66) winsize 62
5549 23:03:47.645945 [CA 3] Center 35 (5~65) winsize 61
5550 23:03:47.648671 [CA 4] Center 35 (5~65) winsize 61
5551 23:03:47.652394 [CA 5] Center 34 (4~65) winsize 62
5552 23:03:47.652476
5553 23:03:47.655529 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5554 23:03:47.655612
5555 23:03:47.659049 [CATrainingPosCal] consider 2 rank data
5556 23:03:47.662005 u2DelayCellTimex100 = 270/100 ps
5557 23:03:47.665384 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5558 23:03:47.672345 CA1 delay=38 (8~68),Diff = 4 PI (24 cell)
5559 23:03:47.675495 CA2 delay=35 (6~65),Diff = 1 PI (6 cell)
5560 23:03:47.678622 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5561 23:03:47.681834 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5562 23:03:47.685227 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
5563 23:03:47.685309
5564 23:03:47.688718 CA PerBit enable=1, Macro0, CA PI delay=34
5565 23:03:47.688801
5566 23:03:47.691776 [CBTSetCACLKResult] CA Dly = 34
5567 23:03:47.691859 CS Dly: 7 (0~39)
5568 23:03:47.691924
5569 23:03:47.695300 ----->DramcWriteLeveling(PI) begin...
5570 23:03:47.698340 ==
5571 23:03:47.701809 Dram Type= 6, Freq= 0, CH_1, rank 0
5572 23:03:47.705129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5573 23:03:47.705212 ==
5574 23:03:47.708659 Write leveling (Byte 0): 25 => 25
5575 23:03:47.711782 Write leveling (Byte 1): 30 => 30
5576 23:03:47.715421 DramcWriteLeveling(PI) end<-----
5577 23:03:47.715505
5578 23:03:47.715572 ==
5579 23:03:47.718822 Dram Type= 6, Freq= 0, CH_1, rank 0
5580 23:03:47.721858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5581 23:03:47.721943 ==
5582 23:03:47.725378 [Gating] SW mode calibration
5583 23:03:47.731746 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5584 23:03:47.738643 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5585 23:03:47.741741 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5586 23:03:47.745010 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5587 23:03:47.751897 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5588 23:03:47.755580 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5589 23:03:47.758544 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5590 23:03:47.761929 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5591 23:03:47.768333 0 14 24 | B1->B0 | 3232 2f2f | 0 0 | (0 0) (0 0)
5592 23:03:47.771854 0 14 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5593 23:03:47.775043 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5594 23:03:47.781845 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5595 23:03:47.785069 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5596 23:03:47.788443 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5597 23:03:47.794831 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5598 23:03:47.798314 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5599 23:03:47.801601 0 15 24 | B1->B0 | 2626 3131 | 0 0 | (0 0) (0 0)
5600 23:03:47.808293 0 15 28 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
5601 23:03:47.811847 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5602 23:03:47.815226 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5603 23:03:47.821816 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5604 23:03:47.825110 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5605 23:03:47.828370 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5606 23:03:47.834985 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5607 23:03:47.838660 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5608 23:03:47.841660 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 23:03:47.848690 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5610 23:03:47.851909 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 23:03:47.854984 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 23:03:47.858432 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 23:03:47.864975 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5614 23:03:47.868423 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5615 23:03:47.871901 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 23:03:47.878563 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 23:03:47.881631 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 23:03:47.885204 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 23:03:47.891710 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 23:03:47.895033 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 23:03:47.898255 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 23:03:47.904876 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 23:03:47.908199 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5624 23:03:47.911526 Total UI for P1: 0, mck2ui 16
5625 23:03:47.914916 best dqsien dly found for B0: ( 1, 2, 22)
5626 23:03:47.918057 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5627 23:03:47.921448 Total UI for P1: 0, mck2ui 16
5628 23:03:47.924810 best dqsien dly found for B1: ( 1, 2, 24)
5629 23:03:47.928039 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5630 23:03:47.931329 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5631 23:03:47.931412
5632 23:03:47.937885 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5633 23:03:47.941071 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5634 23:03:47.944676 [Gating] SW calibration Done
5635 23:03:47.944758 ==
5636 23:03:47.947743 Dram Type= 6, Freq= 0, CH_1, rank 0
5637 23:03:47.951555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5638 23:03:47.951639 ==
5639 23:03:47.951705 RX Vref Scan: 0
5640 23:03:47.951766
5641 23:03:47.954573 RX Vref 0 -> 0, step: 1
5642 23:03:47.954656
5643 23:03:47.957953 RX Delay -80 -> 252, step: 8
5644 23:03:47.961336 iDelay=208, Bit 0, Center 107 (24 ~ 191) 168
5645 23:03:47.964353 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5646 23:03:47.971061 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5647 23:03:47.974760 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5648 23:03:47.977747 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5649 23:03:47.981020 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5650 23:03:47.984352 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5651 23:03:47.987809 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5652 23:03:47.991002 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5653 23:03:47.997947 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5654 23:03:48.000912 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5655 23:03:48.004146 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5656 23:03:48.007623 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5657 23:03:48.011178 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5658 23:03:48.017601 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5659 23:03:48.021239 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5660 23:03:48.021328 ==
5661 23:03:48.024160 Dram Type= 6, Freq= 0, CH_1, rank 0
5662 23:03:48.027386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5663 23:03:48.027469 ==
5664 23:03:48.027536 DQS Delay:
5665 23:03:48.030927 DQS0 = 0, DQS1 = 0
5666 23:03:48.031009 DQM Delay:
5667 23:03:48.034238 DQM0 = 102, DQM1 = 95
5668 23:03:48.034320 DQ Delay:
5669 23:03:48.037440 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5670 23:03:48.041280 DQ4 =99, DQ5 =111, DQ6 =115, DQ7 =99
5671 23:03:48.044485 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =91
5672 23:03:48.047675 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =99
5673 23:03:48.047757
5674 23:03:48.047824
5675 23:03:48.047885 ==
5676 23:03:48.050966 Dram Type= 6, Freq= 0, CH_1, rank 0
5677 23:03:48.057385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5678 23:03:48.057469 ==
5679 23:03:48.057535
5680 23:03:48.057597
5681 23:03:48.057656 TX Vref Scan disable
5682 23:03:48.060969 == TX Byte 0 ==
5683 23:03:48.064273 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5684 23:03:48.067840 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5685 23:03:48.071130 == TX Byte 1 ==
5686 23:03:48.074654 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5687 23:03:48.077884 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5688 23:03:48.080987 ==
5689 23:03:48.084320 Dram Type= 6, Freq= 0, CH_1, rank 0
5690 23:03:48.087918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5691 23:03:48.088003 ==
5692 23:03:48.088069
5693 23:03:48.088129
5694 23:03:48.090977 TX Vref Scan disable
5695 23:03:48.091060 == TX Byte 0 ==
5696 23:03:48.097496 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5697 23:03:48.100881 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5698 23:03:48.100964 == TX Byte 1 ==
5699 23:03:48.107942 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5700 23:03:48.110936 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5701 23:03:48.111020
5702 23:03:48.111086 [DATLAT]
5703 23:03:48.114590 Freq=933, CH1 RK0
5704 23:03:48.114691
5705 23:03:48.114795 DATLAT Default: 0xd
5706 23:03:48.118128 0, 0xFFFF, sum = 0
5707 23:03:48.118213 1, 0xFFFF, sum = 0
5708 23:03:48.121326 2, 0xFFFF, sum = 0
5709 23:03:48.121411 3, 0xFFFF, sum = 0
5710 23:03:48.124228 4, 0xFFFF, sum = 0
5711 23:03:48.124313 5, 0xFFFF, sum = 0
5712 23:03:48.127698 6, 0xFFFF, sum = 0
5713 23:03:48.127783 7, 0xFFFF, sum = 0
5714 23:03:48.130941 8, 0xFFFF, sum = 0
5715 23:03:48.134157 9, 0xFFFF, sum = 0
5716 23:03:48.134241 10, 0x0, sum = 1
5717 23:03:48.134309 11, 0x0, sum = 2
5718 23:03:48.137648 12, 0x0, sum = 3
5719 23:03:48.137733 13, 0x0, sum = 4
5720 23:03:48.140836 best_step = 11
5721 23:03:48.140919
5722 23:03:48.140985 ==
5723 23:03:48.144132 Dram Type= 6, Freq= 0, CH_1, rank 0
5724 23:03:48.147566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5725 23:03:48.147650 ==
5726 23:03:48.151008 RX Vref Scan: 1
5727 23:03:48.151091
5728 23:03:48.151158 RX Vref 0 -> 0, step: 1
5729 23:03:48.151222
5730 23:03:48.154091 RX Delay -53 -> 252, step: 4
5731 23:03:48.154174
5732 23:03:48.157785 Set Vref, RX VrefLevel [Byte0]: 50
5733 23:03:48.160559 [Byte1]: 52
5734 23:03:48.164906
5735 23:03:48.164989 Final RX Vref Byte 0 = 50 to rank0
5736 23:03:48.168409 Final RX Vref Byte 1 = 52 to rank0
5737 23:03:48.171703 Final RX Vref Byte 0 = 50 to rank1
5738 23:03:48.174919 Final RX Vref Byte 1 = 52 to rank1==
5739 23:03:48.178102 Dram Type= 6, Freq= 0, CH_1, rank 0
5740 23:03:48.185021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5741 23:03:48.185105 ==
5742 23:03:48.185172 DQS Delay:
5743 23:03:48.185233 DQS0 = 0, DQS1 = 0
5744 23:03:48.188259 DQM Delay:
5745 23:03:48.188342 DQM0 = 105, DQM1 = 98
5746 23:03:48.191544 DQ Delay:
5747 23:03:48.194747 DQ0 =108, DQ1 =98, DQ2 =96, DQ3 =104
5748 23:03:48.198392 DQ4 =104, DQ5 =112, DQ6 =114, DQ7 =104
5749 23:03:48.201504 DQ8 =90, DQ9 =86, DQ10 =100, DQ11 =92
5750 23:03:48.205078 DQ12 =106, DQ13 =104, DQ14 =104, DQ15 =104
5751 23:03:48.205162
5752 23:03:48.205229
5753 23:03:48.211618 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d35, (MSB)MR19= 0x505, tDQSOscB0 = 405 ps tDQSOscB1 = 412 ps
5754 23:03:48.214951 CH1 RK0: MR19=505, MR18=1D35
5755 23:03:48.221584 CH1_RK0: MR19=0x505, MR18=0x1D35, DQSOSC=405, MR23=63, INC=66, DEC=44
5756 23:03:48.221694
5757 23:03:48.224786 ----->DramcWriteLeveling(PI) begin...
5758 23:03:48.224871 ==
5759 23:03:48.228441 Dram Type= 6, Freq= 0, CH_1, rank 1
5760 23:03:48.231526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5761 23:03:48.231611 ==
5762 23:03:48.235038 Write leveling (Byte 0): 25 => 25
5763 23:03:48.238313 Write leveling (Byte 1): 28 => 28
5764 23:03:48.241335 DramcWriteLeveling(PI) end<-----
5765 23:03:48.241418
5766 23:03:48.241484 ==
5767 23:03:48.244573 Dram Type= 6, Freq= 0, CH_1, rank 1
5768 23:03:48.251242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5769 23:03:48.251326 ==
5770 23:03:48.251392 [Gating] SW mode calibration
5771 23:03:48.261328 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5772 23:03:48.264565 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5773 23:03:48.268003 0 14 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5774 23:03:48.274699 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5775 23:03:48.277891 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5776 23:03:48.281146 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5777 23:03:48.287900 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5778 23:03:48.291444 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5779 23:03:48.294413 0 14 24 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 0)
5780 23:03:48.301066 0 14 28 | B1->B0 | 2525 2e2e | 0 0 | (0 0) (0 0)
5781 23:03:48.304721 0 15 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5782 23:03:48.307486 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5783 23:03:48.314275 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5784 23:03:48.317982 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5785 23:03:48.320947 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5786 23:03:48.327878 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5787 23:03:48.330937 0 15 24 | B1->B0 | 2e2e 2323 | 1 1 | (0 0) (0 0)
5788 23:03:48.334109 0 15 28 | B1->B0 | 4343 3737 | 0 0 | (0 0) (0 0)
5789 23:03:48.340983 1 0 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
5790 23:03:48.344323 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5791 23:03:48.347617 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5792 23:03:48.353761 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5793 23:03:48.357362 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5794 23:03:48.360754 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5795 23:03:48.367659 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5796 23:03:48.370661 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5797 23:03:48.373909 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5798 23:03:48.380730 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5799 23:03:48.383717 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5800 23:03:48.387539 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5801 23:03:48.393936 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5802 23:03:48.397136 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5803 23:03:48.400889 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5804 23:03:48.407231 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5805 23:03:48.410374 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5806 23:03:48.414049 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5807 23:03:48.420469 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 23:03:48.424721 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5809 23:03:48.427593 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5810 23:03:48.433395 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5811 23:03:48.436816 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5812 23:03:48.440453 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5813 23:03:48.443674 Total UI for P1: 0, mck2ui 16
5814 23:03:48.446772 best dqsien dly found for B0: ( 1, 2, 24)
5815 23:03:48.450111 Total UI for P1: 0, mck2ui 16
5816 23:03:48.453495 best dqsien dly found for B1: ( 1, 2, 24)
5817 23:03:48.456906 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5818 23:03:48.460440 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5819 23:03:48.460593
5820 23:03:48.463522 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5821 23:03:48.469984 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5822 23:03:48.470089 [Gating] SW calibration Done
5823 23:03:48.470186 ==
5824 23:03:48.473579 Dram Type= 6, Freq= 0, CH_1, rank 1
5825 23:03:48.480337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5826 23:03:48.480438 ==
5827 23:03:48.480529 RX Vref Scan: 0
5828 23:03:48.480617
5829 23:03:48.483570 RX Vref 0 -> 0, step: 1
5830 23:03:48.483644
5831 23:03:48.486963 RX Delay -80 -> 252, step: 8
5832 23:03:48.490272 iDelay=200, Bit 0, Center 107 (24 ~ 191) 168
5833 23:03:48.493617 iDelay=200, Bit 1, Center 95 (8 ~ 183) 176
5834 23:03:48.496578 iDelay=200, Bit 2, Center 87 (0 ~ 175) 176
5835 23:03:48.500072 iDelay=200, Bit 3, Center 99 (8 ~ 191) 184
5836 23:03:48.506848 iDelay=200, Bit 4, Center 103 (16 ~ 191) 176
5837 23:03:48.509937 iDelay=200, Bit 5, Center 111 (24 ~ 199) 176
5838 23:03:48.513517 iDelay=200, Bit 6, Center 111 (24 ~ 199) 176
5839 23:03:48.516589 iDelay=200, Bit 7, Center 99 (8 ~ 191) 184
5840 23:03:48.519890 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5841 23:03:48.523345 iDelay=200, Bit 9, Center 87 (0 ~ 175) 176
5842 23:03:48.529880 iDelay=200, Bit 10, Center 99 (8 ~ 191) 184
5843 23:03:48.533563 iDelay=200, Bit 11, Center 87 (-8 ~ 183) 192
5844 23:03:48.536630 iDelay=200, Bit 12, Center 103 (8 ~ 199) 192
5845 23:03:48.540410 iDelay=200, Bit 13, Center 103 (8 ~ 199) 192
5846 23:03:48.543193 iDelay=200, Bit 14, Center 103 (8 ~ 199) 192
5847 23:03:48.546701 iDelay=200, Bit 15, Center 103 (8 ~ 199) 192
5848 23:03:48.550082 ==
5849 23:03:48.553271 Dram Type= 6, Freq= 0, CH_1, rank 1
5850 23:03:48.556672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5851 23:03:48.556748 ==
5852 23:03:48.556817 DQS Delay:
5853 23:03:48.559806 DQS0 = 0, DQS1 = 0
5854 23:03:48.559882 DQM Delay:
5855 23:03:48.563133 DQM0 = 101, DQM1 = 96
5856 23:03:48.563230 DQ Delay:
5857 23:03:48.566510 DQ0 =107, DQ1 =95, DQ2 =87, DQ3 =99
5858 23:03:48.569840 DQ4 =103, DQ5 =111, DQ6 =111, DQ7 =99
5859 23:03:48.573133 DQ8 =83, DQ9 =87, DQ10 =99, DQ11 =87
5860 23:03:48.576520 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5861 23:03:48.576598
5862 23:03:48.576662
5863 23:03:48.576720 ==
5864 23:03:48.580072 Dram Type= 6, Freq= 0, CH_1, rank 1
5865 23:03:48.583407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5866 23:03:48.586764 ==
5867 23:03:48.586865
5868 23:03:48.586954
5869 23:03:48.587041 TX Vref Scan disable
5870 23:03:48.590277 == TX Byte 0 ==
5871 23:03:48.593243 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5872 23:03:48.596448 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5873 23:03:48.599962 == TX Byte 1 ==
5874 23:03:48.603427 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5875 23:03:48.607051 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5876 23:03:48.607128 ==
5877 23:03:48.610081 Dram Type= 6, Freq= 0, CH_1, rank 1
5878 23:03:48.616716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5879 23:03:48.616819 ==
5880 23:03:48.616916
5881 23:03:48.617004
5882 23:03:48.617093 TX Vref Scan disable
5883 23:03:48.620831 == TX Byte 0 ==
5884 23:03:48.624399 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5885 23:03:48.630655 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5886 23:03:48.630729 == TX Byte 1 ==
5887 23:03:48.634144 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5888 23:03:48.640506 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5889 23:03:48.640608
5890 23:03:48.640701 [DATLAT]
5891 23:03:48.640803 Freq=933, CH1 RK1
5892 23:03:48.640902
5893 23:03:48.644532 DATLAT Default: 0xb
5894 23:03:48.644630 0, 0xFFFF, sum = 0
5895 23:03:48.647506 1, 0xFFFF, sum = 0
5896 23:03:48.647589 2, 0xFFFF, sum = 0
5897 23:03:48.650668 3, 0xFFFF, sum = 0
5898 23:03:48.654043 4, 0xFFFF, sum = 0
5899 23:03:48.654118 5, 0xFFFF, sum = 0
5900 23:03:48.657753 6, 0xFFFF, sum = 0
5901 23:03:48.657858 7, 0xFFFF, sum = 0
5902 23:03:48.660707 8, 0xFFFF, sum = 0
5903 23:03:48.660806 9, 0xFFFF, sum = 0
5904 23:03:48.664307 10, 0x0, sum = 1
5905 23:03:48.664394 11, 0x0, sum = 2
5906 23:03:48.664464 12, 0x0, sum = 3
5907 23:03:48.667580 13, 0x0, sum = 4
5908 23:03:48.667660 best_step = 11
5909 23:03:48.667725
5910 23:03:48.667784 ==
5911 23:03:48.671066 Dram Type= 6, Freq= 0, CH_1, rank 1
5912 23:03:48.677569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5913 23:03:48.677673 ==
5914 23:03:48.677766 RX Vref Scan: 0
5915 23:03:48.677854
5916 23:03:48.681013 RX Vref 0 -> 0, step: 1
5917 23:03:48.681109
5918 23:03:48.684398 RX Delay -53 -> 252, step: 4
5919 23:03:48.687609 iDelay=199, Bit 0, Center 110 (35 ~ 186) 152
5920 23:03:48.694264 iDelay=199, Bit 1, Center 100 (23 ~ 178) 156
5921 23:03:48.697452 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5922 23:03:48.700756 iDelay=199, Bit 3, Center 102 (19 ~ 186) 168
5923 23:03:48.704529 iDelay=199, Bit 4, Center 106 (27 ~ 186) 160
5924 23:03:48.707374 iDelay=199, Bit 5, Center 114 (31 ~ 198) 168
5925 23:03:48.713956 iDelay=199, Bit 6, Center 112 (31 ~ 194) 164
5926 23:03:48.717384 iDelay=199, Bit 7, Center 102 (23 ~ 182) 160
5927 23:03:48.720753 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5928 23:03:48.723636 iDelay=199, Bit 9, Center 88 (3 ~ 174) 172
5929 23:03:48.727104 iDelay=199, Bit 10, Center 98 (15 ~ 182) 168
5930 23:03:48.730345 iDelay=199, Bit 11, Center 94 (11 ~ 178) 168
5931 23:03:48.737394 iDelay=199, Bit 12, Center 106 (19 ~ 194) 176
5932 23:03:48.740322 iDelay=199, Bit 13, Center 104 (19 ~ 190) 172
5933 23:03:48.744227 iDelay=199, Bit 14, Center 104 (19 ~ 190) 172
5934 23:03:48.746999 iDelay=199, Bit 15, Center 106 (19 ~ 194) 176
5935 23:03:48.747096 ==
5936 23:03:48.750527 Dram Type= 6, Freq= 0, CH_1, rank 1
5937 23:03:48.757152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5938 23:03:48.757225 ==
5939 23:03:48.757306 DQS Delay:
5940 23:03:48.760250 DQS0 = 0, DQS1 = 0
5941 23:03:48.760321 DQM Delay:
5942 23:03:48.760382 DQM0 = 105, DQM1 = 98
5943 23:03:48.764043 DQ Delay:
5944 23:03:48.767015 DQ0 =110, DQ1 =100, DQ2 =94, DQ3 =102
5945 23:03:48.770180 DQ4 =106, DQ5 =114, DQ6 =112, DQ7 =102
5946 23:03:48.773828 DQ8 =84, DQ9 =88, DQ10 =98, DQ11 =94
5947 23:03:48.777301 DQ12 =106, DQ13 =104, DQ14 =104, DQ15 =106
5948 23:03:48.777396
5949 23:03:48.777490
5950 23:03:48.784330 [DQSOSCAuto] RK1, (LSB)MR18= 0x2501, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 410 ps
5951 23:03:48.787329 CH1 RK1: MR19=505, MR18=2501
5952 23:03:48.793746 CH1_RK1: MR19=0x505, MR18=0x2501, DQSOSC=410, MR23=63, INC=64, DEC=42
5953 23:03:48.797366 [RxdqsGatingPostProcess] freq 933
5954 23:03:48.803890 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5955 23:03:48.807376 best DQS0 dly(2T, 0.5T) = (0, 10)
5956 23:03:48.807456 best DQS1 dly(2T, 0.5T) = (0, 10)
5957 23:03:48.810587 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5958 23:03:48.813742 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5959 23:03:48.816980 best DQS0 dly(2T, 0.5T) = (0, 10)
5960 23:03:48.820319 best DQS1 dly(2T, 0.5T) = (0, 10)
5961 23:03:48.823481 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5962 23:03:48.826809 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5963 23:03:48.830287 Pre-setting of DQS Precalculation
5964 23:03:48.836878 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5965 23:03:48.843269 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5966 23:03:48.850255 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5967 23:03:48.850333
5968 23:03:48.850437
5969 23:03:48.853203 [Calibration Summary] 1866 Mbps
5970 23:03:48.853299 CH 0, Rank 0
5971 23:03:48.856557 SW Impedance : PASS
5972 23:03:48.860210 DUTY Scan : NO K
5973 23:03:48.860308 ZQ Calibration : PASS
5974 23:03:48.863372 Jitter Meter : NO K
5975 23:03:48.866688 CBT Training : PASS
5976 23:03:48.866766 Write leveling : PASS
5977 23:03:48.869995 RX DQS gating : PASS
5978 23:03:48.873279 RX DQ/DQS(RDDQC) : PASS
5979 23:03:48.873379 TX DQ/DQS : PASS
5980 23:03:48.876471 RX DATLAT : PASS
5981 23:03:48.876570 RX DQ/DQS(Engine): PASS
5982 23:03:48.880171 TX OE : NO K
5983 23:03:48.880276 All Pass.
5984 23:03:48.880368
5985 23:03:48.883118 CH 0, Rank 1
5986 23:03:48.886591 SW Impedance : PASS
5987 23:03:48.886691 DUTY Scan : NO K
5988 23:03:48.889794 ZQ Calibration : PASS
5989 23:03:48.889898 Jitter Meter : NO K
5990 23:03:48.893162 CBT Training : PASS
5991 23:03:48.896474 Write leveling : PASS
5992 23:03:48.896550 RX DQS gating : PASS
5993 23:03:48.900279 RX DQ/DQS(RDDQC) : PASS
5994 23:03:48.903440 TX DQ/DQS : PASS
5995 23:03:48.903542 RX DATLAT : PASS
5996 23:03:48.906595 RX DQ/DQS(Engine): PASS
5997 23:03:48.910089 TX OE : NO K
5998 23:03:48.910169 All Pass.
5999 23:03:48.910234
6000 23:03:48.910294 CH 1, Rank 0
6001 23:03:48.913453 SW Impedance : PASS
6002 23:03:48.916774 DUTY Scan : NO K
6003 23:03:48.916872 ZQ Calibration : PASS
6004 23:03:48.920386 Jitter Meter : NO K
6005 23:03:48.923311 CBT Training : PASS
6006 23:03:48.923386 Write leveling : PASS
6007 23:03:48.926489 RX DQS gating : PASS
6008 23:03:48.926562 RX DQ/DQS(RDDQC) : PASS
6009 23:03:48.930263 TX DQ/DQS : PASS
6010 23:03:48.933146 RX DATLAT : PASS
6011 23:03:48.933218 RX DQ/DQS(Engine): PASS
6012 23:03:48.936592 TX OE : NO K
6013 23:03:48.936663 All Pass.
6014 23:03:48.936725
6015 23:03:48.939971 CH 1, Rank 1
6016 23:03:48.940041 SW Impedance : PASS
6017 23:03:48.943346 DUTY Scan : NO K
6018 23:03:48.946443 ZQ Calibration : PASS
6019 23:03:48.946518 Jitter Meter : NO K
6020 23:03:48.950146 CBT Training : PASS
6021 23:03:48.953327 Write leveling : PASS
6022 23:03:48.953433 RX DQS gating : PASS
6023 23:03:48.956730 RX DQ/DQS(RDDQC) : PASS
6024 23:03:48.959881 TX DQ/DQS : PASS
6025 23:03:48.959955 RX DATLAT : PASS
6026 23:03:48.963247 RX DQ/DQS(Engine): PASS
6027 23:03:48.963322 TX OE : NO K
6028 23:03:48.966875 All Pass.
6029 23:03:48.966951
6030 23:03:48.967016 DramC Write-DBI off
6031 23:03:48.970244 PER_BANK_REFRESH: Hybrid Mode
6032 23:03:48.973313 TX_TRACKING: ON
6033 23:03:48.980152 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6034 23:03:48.983424 [FAST_K] Save calibration result to emmc
6035 23:03:48.989807 dramc_set_vcore_voltage set vcore to 650000
6036 23:03:48.989911 Read voltage for 400, 6
6037 23:03:48.990007 Vio18 = 0
6038 23:03:48.993351 Vcore = 650000
6039 23:03:48.993423 Vdram = 0
6040 23:03:48.993490 Vddq = 0
6041 23:03:48.996769 Vmddr = 0
6042 23:03:49.000066 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6043 23:03:49.006377 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6044 23:03:49.006489 MEM_TYPE=3, freq_sel=20
6045 23:03:49.009751 sv_algorithm_assistance_LP4_800
6046 23:03:49.016308 ============ PULL DRAM RESETB DOWN ============
6047 23:03:49.020010 ========== PULL DRAM RESETB DOWN end =========
6048 23:03:49.023046 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6049 23:03:49.026318 ===================================
6050 23:03:49.030290 LPDDR4 DRAM CONFIGURATION
6051 23:03:49.033223 ===================================
6052 23:03:49.036705 EX_ROW_EN[0] = 0x0
6053 23:03:49.036781 EX_ROW_EN[1] = 0x0
6054 23:03:49.039894 LP4Y_EN = 0x0
6055 23:03:49.039966 WORK_FSP = 0x0
6056 23:03:49.042848 WL = 0x2
6057 23:03:49.042922 RL = 0x2
6058 23:03:49.046685 BL = 0x2
6059 23:03:49.046758 RPST = 0x0
6060 23:03:49.049566 RD_PRE = 0x0
6061 23:03:49.049639 WR_PRE = 0x1
6062 23:03:49.052865 WR_PST = 0x0
6063 23:03:49.052944 DBI_WR = 0x0
6064 23:03:49.056257 DBI_RD = 0x0
6065 23:03:49.056327 OTF = 0x1
6066 23:03:49.059536 ===================================
6067 23:03:49.063012 ===================================
6068 23:03:49.066473 ANA top config
6069 23:03:49.069845 ===================================
6070 23:03:49.073112 DLL_ASYNC_EN = 0
6071 23:03:49.073214 ALL_SLAVE_EN = 1
6072 23:03:49.076549 NEW_RANK_MODE = 1
6073 23:03:49.079944 DLL_IDLE_MODE = 1
6074 23:03:49.083280 LP45_APHY_COMB_EN = 1
6075 23:03:49.083350 TX_ODT_DIS = 1
6076 23:03:49.086934 NEW_8X_MODE = 1
6077 23:03:49.089740 ===================================
6078 23:03:49.093271 ===================================
6079 23:03:49.096649 data_rate = 800
6080 23:03:49.099556 CKR = 1
6081 23:03:49.102784 DQ_P2S_RATIO = 4
6082 23:03:49.106369 ===================================
6083 23:03:49.109712 CA_P2S_RATIO = 4
6084 23:03:49.109814 DQ_CA_OPEN = 0
6085 23:03:49.112904 DQ_SEMI_OPEN = 1
6086 23:03:49.116310 CA_SEMI_OPEN = 1
6087 23:03:49.119435 CA_FULL_RATE = 0
6088 23:03:49.123087 DQ_CKDIV4_EN = 0
6089 23:03:49.123165 CA_CKDIV4_EN = 1
6090 23:03:49.126577 CA_PREDIV_EN = 0
6091 23:03:49.129701 PH8_DLY = 0
6092 23:03:49.132867 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6093 23:03:49.136302 DQ_AAMCK_DIV = 0
6094 23:03:49.139807 CA_AAMCK_DIV = 0
6095 23:03:49.139889 CA_ADMCK_DIV = 4
6096 23:03:49.142823 DQ_TRACK_CA_EN = 0
6097 23:03:49.146187 CA_PICK = 800
6098 23:03:49.149570 CA_MCKIO = 400
6099 23:03:49.153295 MCKIO_SEMI = 400
6100 23:03:49.156432 PLL_FREQ = 3016
6101 23:03:49.159480 DQ_UI_PI_RATIO = 32
6102 23:03:49.163093 CA_UI_PI_RATIO = 32
6103 23:03:49.163179 ===================================
6104 23:03:49.166407 ===================================
6105 23:03:49.169899 memory_type:LPDDR4
6106 23:03:49.173704 GP_NUM : 10
6107 23:03:49.173786 SRAM_EN : 1
6108 23:03:49.176181 MD32_EN : 0
6109 23:03:49.179457 ===================================
6110 23:03:49.182912 [ANA_INIT] >>>>>>>>>>>>>>
6111 23:03:49.185994 <<<<<< [CONFIGURE PHASE]: ANA_TX
6112 23:03:49.189401 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6113 23:03:49.193297 ===================================
6114 23:03:49.193374 data_rate = 800,PCW = 0X7400
6115 23:03:49.196087 ===================================
6116 23:03:49.202529 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6117 23:03:49.205950 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6118 23:03:49.219097 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6119 23:03:49.222357 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6120 23:03:49.226088 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6121 23:03:49.229151 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6122 23:03:49.232561 [ANA_INIT] flow start
6123 23:03:49.232654 [ANA_INIT] PLL >>>>>>>>
6124 23:03:49.235765 [ANA_INIT] PLL <<<<<<<<
6125 23:03:49.238937 [ANA_INIT] MIDPI >>>>>>>>
6126 23:03:49.242472 [ANA_INIT] MIDPI <<<<<<<<
6127 23:03:49.242561 [ANA_INIT] DLL >>>>>>>>
6128 23:03:49.245804 [ANA_INIT] flow end
6129 23:03:49.248859 ============ LP4 DIFF to SE enter ============
6130 23:03:49.252492 ============ LP4 DIFF to SE exit ============
6131 23:03:49.255573 [ANA_INIT] <<<<<<<<<<<<<
6132 23:03:49.258916 [Flow] Enable top DCM control >>>>>
6133 23:03:49.262216 [Flow] Enable top DCM control <<<<<
6134 23:03:49.266099 Enable DLL master slave shuffle
6135 23:03:49.272325 ==============================================================
6136 23:03:49.272410 Gating Mode config
6137 23:03:49.279043 ==============================================================
6138 23:03:49.279150 Config description:
6139 23:03:49.288829 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6140 23:03:49.295595 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6141 23:03:49.302424 SELPH_MODE 0: By rank 1: By Phase
6142 23:03:49.305346 ==============================================================
6143 23:03:49.309019 GAT_TRACK_EN = 0
6144 23:03:49.312064 RX_GATING_MODE = 2
6145 23:03:49.315481 RX_GATING_TRACK_MODE = 2
6146 23:03:49.318631 SELPH_MODE = 1
6147 23:03:49.322058 PICG_EARLY_EN = 1
6148 23:03:49.325432 VALID_LAT_VALUE = 1
6149 23:03:49.328736 ==============================================================
6150 23:03:49.332082 Enter into Gating configuration >>>>
6151 23:03:49.335589 Exit from Gating configuration <<<<
6152 23:03:49.338852 Enter into DVFS_PRE_config >>>>>
6153 23:03:49.351933 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6154 23:03:49.355885 Exit from DVFS_PRE_config <<<<<
6155 23:03:49.358660 Enter into PICG configuration >>>>
6156 23:03:49.358744 Exit from PICG configuration <<<<
6157 23:03:49.361840 [RX_INPUT] configuration >>>>>
6158 23:03:49.365101 [RX_INPUT] configuration <<<<<
6159 23:03:49.372185 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6160 23:03:49.375225 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6161 23:03:49.381654 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6162 23:03:49.388469 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6163 23:03:49.394902 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6164 23:03:49.402009 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6165 23:03:49.405016 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6166 23:03:49.408733 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6167 23:03:49.411839 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6168 23:03:49.418287 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6169 23:03:49.421651 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6170 23:03:49.424947 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6171 23:03:49.428492 ===================================
6172 23:03:49.431743 LPDDR4 DRAM CONFIGURATION
6173 23:03:49.435107 ===================================
6174 23:03:49.438034 EX_ROW_EN[0] = 0x0
6175 23:03:49.438108 EX_ROW_EN[1] = 0x0
6176 23:03:49.441656 LP4Y_EN = 0x0
6177 23:03:49.441735 WORK_FSP = 0x0
6178 23:03:49.445059 WL = 0x2
6179 23:03:49.445133 RL = 0x2
6180 23:03:49.448650 BL = 0x2
6181 23:03:49.448730 RPST = 0x0
6182 23:03:49.451618 RD_PRE = 0x0
6183 23:03:49.451694 WR_PRE = 0x1
6184 23:03:49.455417 WR_PST = 0x0
6185 23:03:49.455491 DBI_WR = 0x0
6186 23:03:49.458033 DBI_RD = 0x0
6187 23:03:49.458108 OTF = 0x1
6188 23:03:49.462257 ===================================
6189 23:03:49.468056 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6190 23:03:49.471869 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6191 23:03:49.475294 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6192 23:03:49.478351 ===================================
6193 23:03:49.481606 LPDDR4 DRAM CONFIGURATION
6194 23:03:49.485049 ===================================
6195 23:03:49.485134 EX_ROW_EN[0] = 0x10
6196 23:03:49.488136 EX_ROW_EN[1] = 0x0
6197 23:03:49.491647 LP4Y_EN = 0x0
6198 23:03:49.491750 WORK_FSP = 0x0
6199 23:03:49.494829 WL = 0x2
6200 23:03:49.494971 RL = 0x2
6201 23:03:49.498200 BL = 0x2
6202 23:03:49.498329 RPST = 0x0
6203 23:03:49.501704 RD_PRE = 0x0
6204 23:03:49.501793 WR_PRE = 0x1
6205 23:03:49.505021 WR_PST = 0x0
6206 23:03:49.505104 DBI_WR = 0x0
6207 23:03:49.507915 DBI_RD = 0x0
6208 23:03:49.507999 OTF = 0x1
6209 23:03:49.511805 ===================================
6210 23:03:49.517947 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6211 23:03:49.522246 nWR fixed to 30
6212 23:03:49.525618 [ModeRegInit_LP4] CH0 RK0
6213 23:03:49.525705 [ModeRegInit_LP4] CH0 RK1
6214 23:03:49.528913 [ModeRegInit_LP4] CH1 RK0
6215 23:03:49.532411 [ModeRegInit_LP4] CH1 RK1
6216 23:03:49.532497 match AC timing 19
6217 23:03:49.538928 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6218 23:03:49.542618 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6219 23:03:49.545490 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6220 23:03:49.552340 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6221 23:03:49.555426 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6222 23:03:49.555508 ==
6223 23:03:49.558925 Dram Type= 6, Freq= 0, CH_0, rank 0
6224 23:03:49.562184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6225 23:03:49.562262 ==
6226 23:03:49.568688 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6227 23:03:49.575539 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6228 23:03:49.578822 [CA 0] Center 36 (8~64) winsize 57
6229 23:03:49.582243 [CA 1] Center 36 (8~64) winsize 57
6230 23:03:49.585893 [CA 2] Center 36 (8~64) winsize 57
6231 23:03:49.585971 [CA 3] Center 36 (8~64) winsize 57
6232 23:03:49.588957 [CA 4] Center 36 (8~64) winsize 57
6233 23:03:49.592241 [CA 5] Center 36 (8~64) winsize 57
6234 23:03:49.592319
6235 23:03:49.598783 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6236 23:03:49.598865
6237 23:03:49.602048 [CATrainingPosCal] consider 1 rank data
6238 23:03:49.605366 u2DelayCellTimex100 = 270/100 ps
6239 23:03:49.608558 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6240 23:03:49.612182 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6241 23:03:49.615532 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6242 23:03:49.619137 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6243 23:03:49.622252 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6244 23:03:49.625722 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6245 23:03:49.625796
6246 23:03:49.628996 CA PerBit enable=1, Macro0, CA PI delay=36
6247 23:03:49.629072
6248 23:03:49.632344 [CBTSetCACLKResult] CA Dly = 36
6249 23:03:49.635682 CS Dly: 1 (0~32)
6250 23:03:49.635760 ==
6251 23:03:49.638975 Dram Type= 6, Freq= 0, CH_0, rank 1
6252 23:03:49.642143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6253 23:03:49.642217 ==
6254 23:03:49.648437 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6255 23:03:49.651836 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6256 23:03:49.655469 [CA 0] Center 36 (8~64) winsize 57
6257 23:03:49.658517 [CA 1] Center 36 (8~64) winsize 57
6258 23:03:49.661638 [CA 2] Center 36 (8~64) winsize 57
6259 23:03:49.665344 [CA 3] Center 36 (8~64) winsize 57
6260 23:03:49.668744 [CA 4] Center 36 (8~64) winsize 57
6261 23:03:49.671872 [CA 5] Center 36 (8~64) winsize 57
6262 23:03:49.671949
6263 23:03:49.675447 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6264 23:03:49.675524
6265 23:03:49.678411 [CATrainingPosCal] consider 2 rank data
6266 23:03:49.681807 u2DelayCellTimex100 = 270/100 ps
6267 23:03:49.685520 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6268 23:03:49.688799 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6269 23:03:49.691981 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6270 23:03:49.698435 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6271 23:03:49.701960 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6272 23:03:49.705096 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6273 23:03:49.705193
6274 23:03:49.708513 CA PerBit enable=1, Macro0, CA PI delay=36
6275 23:03:49.708652
6276 23:03:49.712510 [CBTSetCACLKResult] CA Dly = 36
6277 23:03:49.712587 CS Dly: 1 (0~32)
6278 23:03:49.712649
6279 23:03:49.715292 ----->DramcWriteLeveling(PI) begin...
6280 23:03:49.715365 ==
6281 23:03:49.718549 Dram Type= 6, Freq= 0, CH_0, rank 0
6282 23:03:49.725453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6283 23:03:49.725533 ==
6284 23:03:49.728539 Write leveling (Byte 0): 40 => 8
6285 23:03:49.732140 Write leveling (Byte 1): 32 => 0
6286 23:03:49.732217 DramcWriteLeveling(PI) end<-----
6287 23:03:49.732280
6288 23:03:49.734957 ==
6289 23:03:49.738258 Dram Type= 6, Freq= 0, CH_0, rank 0
6290 23:03:49.741845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6291 23:03:49.741921 ==
6292 23:03:49.744854 [Gating] SW mode calibration
6293 23:03:49.751776 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6294 23:03:49.754887 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6295 23:03:49.761769 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6296 23:03:49.764930 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6297 23:03:49.768422 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6298 23:03:49.775066 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6299 23:03:49.777985 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6300 23:03:49.781544 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6301 23:03:49.788022 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6302 23:03:49.791428 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6303 23:03:49.795213 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6304 23:03:49.798189 Total UI for P1: 0, mck2ui 16
6305 23:03:49.801790 best dqsien dly found for B0: ( 0, 14, 24)
6306 23:03:49.804811 Total UI for P1: 0, mck2ui 16
6307 23:03:49.808226 best dqsien dly found for B1: ( 0, 14, 24)
6308 23:03:49.811553 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6309 23:03:49.815123 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6310 23:03:49.815205
6311 23:03:49.821725 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6312 23:03:49.824885 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6313 23:03:49.824967 [Gating] SW calibration Done
6314 23:03:49.828071 ==
6315 23:03:49.831583 Dram Type= 6, Freq= 0, CH_0, rank 0
6316 23:03:49.834871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6317 23:03:49.834988 ==
6318 23:03:49.835067 RX Vref Scan: 0
6319 23:03:49.835128
6320 23:03:49.838112 RX Vref 0 -> 0, step: 1
6321 23:03:49.838194
6322 23:03:49.841192 RX Delay -410 -> 252, step: 16
6323 23:03:49.844806 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6324 23:03:49.847888 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6325 23:03:49.854454 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6326 23:03:49.858015 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6327 23:03:49.861617 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6328 23:03:49.864771 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6329 23:03:49.871306 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6330 23:03:49.874556 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6331 23:03:49.878220 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6332 23:03:49.881387 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6333 23:03:49.888309 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6334 23:03:49.891112 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6335 23:03:49.894376 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6336 23:03:49.898011 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6337 23:03:49.904761 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6338 23:03:49.907943 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6339 23:03:49.908025 ==
6340 23:03:49.911249 Dram Type= 6, Freq= 0, CH_0, rank 0
6341 23:03:49.914336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6342 23:03:49.914468 ==
6343 23:03:49.918549 DQS Delay:
6344 23:03:49.918629 DQS0 = 27, DQS1 = 43
6345 23:03:49.921223 DQM Delay:
6346 23:03:49.921304 DQM0 = 12, DQM1 = 13
6347 23:03:49.921370 DQ Delay:
6348 23:03:49.924695 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6349 23:03:49.927841 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6350 23:03:49.931037 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6351 23:03:49.934595 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6352 23:03:49.934677
6353 23:03:49.934740
6354 23:03:49.934800 ==
6355 23:03:49.937691 Dram Type= 6, Freq= 0, CH_0, rank 0
6356 23:03:49.944524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6357 23:03:49.944607 ==
6358 23:03:49.944673
6359 23:03:49.944733
6360 23:03:49.944790 TX Vref Scan disable
6361 23:03:49.947670 == TX Byte 0 ==
6362 23:03:49.951386 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6363 23:03:49.954613 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6364 23:03:49.957682 == TX Byte 1 ==
6365 23:03:49.961270 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6366 23:03:49.964696 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6367 23:03:49.964778 ==
6368 23:03:49.968132 Dram Type= 6, Freq= 0, CH_0, rank 0
6369 23:03:49.974604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6370 23:03:49.974687 ==
6371 23:03:49.974755
6372 23:03:49.974816
6373 23:03:49.974922 TX Vref Scan disable
6374 23:03:49.977768 == TX Byte 0 ==
6375 23:03:49.981411 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6376 23:03:49.984606 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6377 23:03:49.987874 == TX Byte 1 ==
6378 23:03:49.991265 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6379 23:03:49.994504 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6380 23:03:49.994587
6381 23:03:49.997735 [DATLAT]
6382 23:03:49.997818 Freq=400, CH0 RK0
6383 23:03:49.997885
6384 23:03:50.001198 DATLAT Default: 0xf
6385 23:03:50.001281 0, 0xFFFF, sum = 0
6386 23:03:50.004354 1, 0xFFFF, sum = 0
6387 23:03:50.004439 2, 0xFFFF, sum = 0
6388 23:03:50.007961 3, 0xFFFF, sum = 0
6389 23:03:50.008046 4, 0xFFFF, sum = 0
6390 23:03:50.011252 5, 0xFFFF, sum = 0
6391 23:03:50.011338 6, 0xFFFF, sum = 0
6392 23:03:50.014934 7, 0xFFFF, sum = 0
6393 23:03:50.015019 8, 0xFFFF, sum = 0
6394 23:03:50.017920 9, 0xFFFF, sum = 0
6395 23:03:50.021063 10, 0xFFFF, sum = 0
6396 23:03:50.021149 11, 0xFFFF, sum = 0
6397 23:03:50.024392 12, 0xFFFF, sum = 0
6398 23:03:50.024477 13, 0x0, sum = 1
6399 23:03:50.027755 14, 0x0, sum = 2
6400 23:03:50.027840 15, 0x0, sum = 3
6401 23:03:50.031049 16, 0x0, sum = 4
6402 23:03:50.031171 best_step = 14
6403 23:03:50.031259
6404 23:03:50.031321 ==
6405 23:03:50.034618 Dram Type= 6, Freq= 0, CH_0, rank 0
6406 23:03:50.037851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6407 23:03:50.037961 ==
6408 23:03:50.041123 RX Vref Scan: 1
6409 23:03:50.041207
6410 23:03:50.044489 RX Vref 0 -> 0, step: 1
6411 23:03:50.044587
6412 23:03:50.044679 RX Delay -327 -> 252, step: 8
6413 23:03:50.044768
6414 23:03:50.047525 Set Vref, RX VrefLevel [Byte0]: 59
6415 23:03:50.051218 [Byte1]: 49
6416 23:03:50.056311
6417 23:03:50.056401 Final RX Vref Byte 0 = 59 to rank0
6418 23:03:50.059458 Final RX Vref Byte 1 = 49 to rank0
6419 23:03:50.063067 Final RX Vref Byte 0 = 59 to rank1
6420 23:03:50.066273 Final RX Vref Byte 1 = 49 to rank1==
6421 23:03:50.069591 Dram Type= 6, Freq= 0, CH_0, rank 0
6422 23:03:50.076488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6423 23:03:50.076589 ==
6424 23:03:50.076682 DQS Delay:
6425 23:03:50.076771 DQS0 = 28, DQS1 = 48
6426 23:03:50.079545 DQM Delay:
6427 23:03:50.079642 DQM0 = 12, DQM1 = 16
6428 23:03:50.082967 DQ Delay:
6429 23:03:50.086195 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6430 23:03:50.086295 DQ4 =12, DQ5 =0, DQ6 =24, DQ7 =20
6431 23:03:50.089688 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =12
6432 23:03:50.092983 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =24
6433 23:03:50.093088
6434 23:03:50.095975
6435 23:03:50.103075 [DQSOSCAuto] RK0, (LSB)MR18= 0xada5, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 388 ps
6436 23:03:50.105969 CH0 RK0: MR19=C0C, MR18=ADA5
6437 23:03:50.112684 CH0_RK0: MR19=0xC0C, MR18=0xADA5, DQSOSC=388, MR23=63, INC=392, DEC=261
6438 23:03:50.112759 ==
6439 23:03:50.116468 Dram Type= 6, Freq= 0, CH_0, rank 1
6440 23:03:50.119240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6441 23:03:50.119310 ==
6442 23:03:50.122550 [Gating] SW mode calibration
6443 23:03:50.129350 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6444 23:03:50.135792 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6445 23:03:50.139339 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6446 23:03:50.142369 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6447 23:03:50.149197 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6448 23:03:50.152409 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6449 23:03:50.155564 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6450 23:03:50.162244 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6451 23:03:50.165847 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6452 23:03:50.168974 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6453 23:03:50.175628 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6454 23:03:50.175735 Total UI for P1: 0, mck2ui 16
6455 23:03:50.179070 best dqsien dly found for B0: ( 0, 14, 24)
6456 23:03:50.182263 Total UI for P1: 0, mck2ui 16
6457 23:03:50.185517 best dqsien dly found for B1: ( 0, 14, 24)
6458 23:03:50.192242 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6459 23:03:50.195438 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6460 23:03:50.195542
6461 23:03:50.198701 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6462 23:03:50.202308 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6463 23:03:50.205337 [Gating] SW calibration Done
6464 23:03:50.205454 ==
6465 23:03:50.208864 Dram Type= 6, Freq= 0, CH_0, rank 1
6466 23:03:50.212124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6467 23:03:50.212226 ==
6468 23:03:50.215625 RX Vref Scan: 0
6469 23:03:50.215726
6470 23:03:50.215815 RX Vref 0 -> 0, step: 1
6471 23:03:50.215900
6472 23:03:50.218580 RX Delay -410 -> 252, step: 16
6473 23:03:50.225397 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6474 23:03:50.228744 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6475 23:03:50.231986 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6476 23:03:50.235151 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6477 23:03:50.238622 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6478 23:03:50.245153 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6479 23:03:50.248604 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6480 23:03:50.251987 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6481 23:03:50.255470 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6482 23:03:50.261802 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6483 23:03:50.265554 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6484 23:03:50.268366 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6485 23:03:50.272017 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6486 23:03:50.278446 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6487 23:03:50.282062 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6488 23:03:50.285314 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6489 23:03:50.285409 ==
6490 23:03:50.288530 Dram Type= 6, Freq= 0, CH_0, rank 1
6491 23:03:50.295204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6492 23:03:50.295304 ==
6493 23:03:50.295401 DQS Delay:
6494 23:03:50.298294 DQS0 = 27, DQS1 = 35
6495 23:03:50.298399 DQM Delay:
6496 23:03:50.298492 DQM0 = 10, DQM1 = 8
6497 23:03:50.301688 DQ Delay:
6498 23:03:50.305485 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6499 23:03:50.305560 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =16
6500 23:03:50.308509 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6501 23:03:50.311795 DQ12 =8, DQ13 =16, DQ14 =16, DQ15 =16
6502 23:03:50.311892
6503 23:03:50.311981
6504 23:03:50.315207 ==
6505 23:03:50.315311 Dram Type= 6, Freq= 0, CH_0, rank 1
6506 23:03:50.321615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6507 23:03:50.321713 ==
6508 23:03:50.321808
6509 23:03:50.321900
6510 23:03:50.324875 TX Vref Scan disable
6511 23:03:50.324968 == TX Byte 0 ==
6512 23:03:50.328224 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6513 23:03:50.331753 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6514 23:03:50.335174 == TX Byte 1 ==
6515 23:03:50.338892 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6516 23:03:50.341498 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6517 23:03:50.345051 ==
6518 23:03:50.348094 Dram Type= 6, Freq= 0, CH_0, rank 1
6519 23:03:50.351614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6520 23:03:50.351807 ==
6521 23:03:50.351936
6522 23:03:50.352058
6523 23:03:50.354997 TX Vref Scan disable
6524 23:03:50.355080 == TX Byte 0 ==
6525 23:03:50.358245 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6526 23:03:50.365106 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6527 23:03:50.365205 == TX Byte 1 ==
6528 23:03:50.368070 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6529 23:03:50.371610 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6530 23:03:50.374785
6531 23:03:50.374856 [DATLAT]
6532 23:03:50.374918 Freq=400, CH0 RK1
6533 23:03:50.374993
6534 23:03:50.378156 DATLAT Default: 0xe
6535 23:03:50.378249 0, 0xFFFF, sum = 0
6536 23:03:50.381670 1, 0xFFFF, sum = 0
6537 23:03:50.381813 2, 0xFFFF, sum = 0
6538 23:03:50.384904 3, 0xFFFF, sum = 0
6539 23:03:50.385002 4, 0xFFFF, sum = 0
6540 23:03:50.388193 5, 0xFFFF, sum = 0
6541 23:03:50.391228 6, 0xFFFF, sum = 0
6542 23:03:50.391329 7, 0xFFFF, sum = 0
6543 23:03:50.394725 8, 0xFFFF, sum = 0
6544 23:03:50.394803 9, 0xFFFF, sum = 0
6545 23:03:50.398317 10, 0xFFFF, sum = 0
6546 23:03:50.398451 11, 0xFFFF, sum = 0
6547 23:03:50.401415 12, 0xFFFF, sum = 0
6548 23:03:50.401512 13, 0x0, sum = 1
6549 23:03:50.404634 14, 0x0, sum = 2
6550 23:03:50.404737 15, 0x0, sum = 3
6551 23:03:50.408052 16, 0x0, sum = 4
6552 23:03:50.408152 best_step = 14
6553 23:03:50.408245
6554 23:03:50.408331 ==
6555 23:03:50.411598 Dram Type= 6, Freq= 0, CH_0, rank 1
6556 23:03:50.414745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6557 23:03:50.414844 ==
6558 23:03:50.418067 RX Vref Scan: 0
6559 23:03:50.418161
6560 23:03:50.421248 RX Vref 0 -> 0, step: 1
6561 23:03:50.421343
6562 23:03:50.421439 RX Delay -311 -> 252, step: 8
6563 23:03:50.430110 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6564 23:03:50.433581 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6565 23:03:50.436717 iDelay=217, Bit 2, Center -24 (-247 ~ 200) 448
6566 23:03:50.443374 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6567 23:03:50.446611 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6568 23:03:50.449812 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6569 23:03:50.453192 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6570 23:03:50.456425 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6571 23:03:50.463299 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6572 23:03:50.466484 iDelay=217, Bit 9, Center -40 (-263 ~ 184) 448
6573 23:03:50.469680 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6574 23:03:50.473174 iDelay=217, Bit 11, Center -36 (-263 ~ 192) 456
6575 23:03:50.479558 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6576 23:03:50.483045 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6577 23:03:50.486121 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6578 23:03:50.493001 iDelay=217, Bit 15, Center -20 (-239 ~ 200) 440
6579 23:03:50.493108 ==
6580 23:03:50.496277 Dram Type= 6, Freq= 0, CH_0, rank 1
6581 23:03:50.499496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6582 23:03:50.499597 ==
6583 23:03:50.499695 DQS Delay:
6584 23:03:50.502916 DQS0 = 28, DQS1 = 40
6585 23:03:50.503023 DQM Delay:
6586 23:03:50.506317 DQM0 = 10, DQM1 = 11
6587 23:03:50.506465 DQ Delay:
6588 23:03:50.509714 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =4
6589 23:03:50.513370 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6590 23:03:50.516634 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6591 23:03:50.519673 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =20
6592 23:03:50.519752
6593 23:03:50.519816
6594 23:03:50.526537 [DQSOSCAuto] RK1, (LSB)MR18= 0xbd6f, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 386 ps
6595 23:03:50.529851 CH0 RK1: MR19=C0C, MR18=BD6F
6596 23:03:50.536738 CH0_RK1: MR19=0xC0C, MR18=0xBD6F, DQSOSC=386, MR23=63, INC=396, DEC=264
6597 23:03:50.539804 [RxdqsGatingPostProcess] freq 400
6598 23:03:50.543090 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6599 23:03:50.546469 best DQS0 dly(2T, 0.5T) = (0, 10)
6600 23:03:50.549974 best DQS1 dly(2T, 0.5T) = (0, 10)
6601 23:03:50.553045 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6602 23:03:50.556213 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6603 23:03:50.559689 best DQS0 dly(2T, 0.5T) = (0, 10)
6604 23:03:50.563086 best DQS1 dly(2T, 0.5T) = (0, 10)
6605 23:03:50.566554 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6606 23:03:50.570109 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6607 23:03:50.573415 Pre-setting of DQS Precalculation
6608 23:03:50.576604 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6609 23:03:50.580015 ==
6610 23:03:50.582933 Dram Type= 6, Freq= 0, CH_1, rank 0
6611 23:03:50.586066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6612 23:03:50.586165 ==
6613 23:03:50.589789 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6614 23:03:50.596423 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6615 23:03:50.599798 [CA 0] Center 36 (8~64) winsize 57
6616 23:03:50.603224 [CA 1] Center 36 (8~64) winsize 57
6617 23:03:50.606559 [CA 2] Center 36 (8~64) winsize 57
6618 23:03:50.609501 [CA 3] Center 36 (8~64) winsize 57
6619 23:03:50.612910 [CA 4] Center 36 (8~64) winsize 57
6620 23:03:50.616206 [CA 5] Center 36 (8~64) winsize 57
6621 23:03:50.616301
6622 23:03:50.619716 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6623 23:03:50.619798
6624 23:03:50.622876 [CATrainingPosCal] consider 1 rank data
6625 23:03:50.626169 u2DelayCellTimex100 = 270/100 ps
6626 23:03:50.629709 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6627 23:03:50.633211 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6628 23:03:50.636379 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6629 23:03:50.639691 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6630 23:03:50.642891 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6631 23:03:50.649790 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6632 23:03:50.649873
6633 23:03:50.653090 CA PerBit enable=1, Macro0, CA PI delay=36
6634 23:03:50.653190
6635 23:03:50.656144 [CBTSetCACLKResult] CA Dly = 36
6636 23:03:50.656230 CS Dly: 1 (0~32)
6637 23:03:50.656316 ==
6638 23:03:50.659253 Dram Type= 6, Freq= 0, CH_1, rank 1
6639 23:03:50.662773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6640 23:03:50.665922 ==
6641 23:03:50.669316 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6642 23:03:50.676025 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6643 23:03:50.679587 [CA 0] Center 36 (8~64) winsize 57
6644 23:03:50.682645 [CA 1] Center 36 (8~64) winsize 57
6645 23:03:50.686298 [CA 2] Center 36 (8~64) winsize 57
6646 23:03:50.689544 [CA 3] Center 36 (8~64) winsize 57
6647 23:03:50.692573 [CA 4] Center 36 (8~64) winsize 57
6648 23:03:50.696013 [CA 5] Center 36 (8~64) winsize 57
6649 23:03:50.696100
6650 23:03:50.699208 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6651 23:03:50.699294
6652 23:03:50.702795 [CATrainingPosCal] consider 2 rank data
6653 23:03:50.706239 u2DelayCellTimex100 = 270/100 ps
6654 23:03:50.709681 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6655 23:03:50.712852 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6656 23:03:50.716280 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6657 23:03:50.719471 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6658 23:03:50.722807 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6659 23:03:50.725947 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6660 23:03:50.726033
6661 23:03:50.729996 CA PerBit enable=1, Macro0, CA PI delay=36
6662 23:03:50.730083
6663 23:03:50.732591 [CBTSetCACLKResult] CA Dly = 36
6664 23:03:50.735971 CS Dly: 1 (0~32)
6665 23:03:50.736057
6666 23:03:50.739276 ----->DramcWriteLeveling(PI) begin...
6667 23:03:50.739363 ==
6668 23:03:50.742759 Dram Type= 6, Freq= 0, CH_1, rank 0
6669 23:03:50.745977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6670 23:03:50.746064 ==
6671 23:03:50.749197 Write leveling (Byte 0): 40 => 8
6672 23:03:50.752586 Write leveling (Byte 1): 32 => 0
6673 23:03:50.756260 DramcWriteLeveling(PI) end<-----
6674 23:03:50.756346
6675 23:03:50.756432 ==
6676 23:03:50.759355 Dram Type= 6, Freq= 0, CH_1, rank 0
6677 23:03:50.763018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6678 23:03:50.763105 ==
6679 23:03:50.766015 [Gating] SW mode calibration
6680 23:03:50.772662 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6681 23:03:50.779330 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6682 23:03:50.782559 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6683 23:03:50.789077 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6684 23:03:50.792676 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6685 23:03:50.795919 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6686 23:03:50.799575 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6687 23:03:50.805903 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6688 23:03:50.809541 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6689 23:03:50.812803 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6690 23:03:50.819095 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6691 23:03:50.822355 Total UI for P1: 0, mck2ui 16
6692 23:03:50.825670 best dqsien dly found for B0: ( 0, 14, 24)
6693 23:03:50.828904 Total UI for P1: 0, mck2ui 16
6694 23:03:50.832505 best dqsien dly found for B1: ( 0, 14, 24)
6695 23:03:50.836042 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6696 23:03:50.838853 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6697 23:03:50.838940
6698 23:03:50.842416 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6699 23:03:50.845742 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6700 23:03:50.848765 [Gating] SW calibration Done
6701 23:03:50.848852 ==
6702 23:03:50.852204 Dram Type= 6, Freq= 0, CH_1, rank 0
6703 23:03:50.855624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6704 23:03:50.855722 ==
6705 23:03:50.859001 RX Vref Scan: 0
6706 23:03:50.859077
6707 23:03:50.862086 RX Vref 0 -> 0, step: 1
6708 23:03:50.862156
6709 23:03:50.862219 RX Delay -410 -> 252, step: 16
6710 23:03:50.868911 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6711 23:03:50.871990 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6712 23:03:50.875814 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6713 23:03:50.878846 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6714 23:03:50.885518 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6715 23:03:50.889134 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6716 23:03:50.892198 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6717 23:03:50.895858 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6718 23:03:50.902032 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6719 23:03:50.905267 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6720 23:03:50.908734 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6721 23:03:50.911945 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6722 23:03:50.918578 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6723 23:03:50.922035 iDelay=230, Bit 13, Center -11 (-250 ~ 229) 480
6724 23:03:50.925286 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6725 23:03:50.931730 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6726 23:03:50.931841 ==
6727 23:03:50.935207 Dram Type= 6, Freq= 0, CH_1, rank 0
6728 23:03:50.938690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6729 23:03:50.938773 ==
6730 23:03:50.938840 DQS Delay:
6731 23:03:50.941821 DQS0 = 27, DQS1 = 43
6732 23:03:50.941903 DQM Delay:
6733 23:03:50.945091 DQM0 = 9, DQM1 = 17
6734 23:03:50.945173 DQ Delay:
6735 23:03:50.948491 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6736 23:03:50.951708 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =0
6737 23:03:50.954861 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6738 23:03:50.958261 DQ12 =32, DQ13 =32, DQ14 =16, DQ15 =24
6739 23:03:50.958373
6740 23:03:50.958485
6741 23:03:50.958581 ==
6742 23:03:50.961913 Dram Type= 6, Freq= 0, CH_1, rank 0
6743 23:03:50.965496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6744 23:03:50.965588 ==
6745 23:03:50.965689
6746 23:03:50.965782
6747 23:03:50.968725 TX Vref Scan disable
6748 23:03:50.968808 == TX Byte 0 ==
6749 23:03:50.975397 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6750 23:03:50.978620 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6751 23:03:50.978720 == TX Byte 1 ==
6752 23:03:50.984904 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6753 23:03:50.988292 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6754 23:03:50.988399 ==
6755 23:03:50.991718 Dram Type= 6, Freq= 0, CH_1, rank 0
6756 23:03:50.994969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6757 23:03:50.995070 ==
6758 23:03:50.995160
6759 23:03:50.995248
6760 23:03:50.998570 TX Vref Scan disable
6761 23:03:50.998668 == TX Byte 0 ==
6762 23:03:51.004923 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6763 23:03:51.008582 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6764 23:03:51.008658 == TX Byte 1 ==
6765 23:03:51.015049 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6766 23:03:51.018225 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6767 23:03:51.018325
6768 23:03:51.018478 [DATLAT]
6769 23:03:51.021653 Freq=400, CH1 RK0
6770 23:03:51.021751
6771 23:03:51.021839 DATLAT Default: 0xf
6772 23:03:51.025029 0, 0xFFFF, sum = 0
6773 23:03:51.025127 1, 0xFFFF, sum = 0
6774 23:03:51.028200 2, 0xFFFF, sum = 0
6775 23:03:51.028277 3, 0xFFFF, sum = 0
6776 23:03:51.031962 4, 0xFFFF, sum = 0
6777 23:03:51.032038 5, 0xFFFF, sum = 0
6778 23:03:51.034912 6, 0xFFFF, sum = 0
6779 23:03:51.034985 7, 0xFFFF, sum = 0
6780 23:03:51.038489 8, 0xFFFF, sum = 0
6781 23:03:51.041666 9, 0xFFFF, sum = 0
6782 23:03:51.041767 10, 0xFFFF, sum = 0
6783 23:03:51.044829 11, 0xFFFF, sum = 0
6784 23:03:51.044902 12, 0xFFFF, sum = 0
6785 23:03:51.048443 13, 0x0, sum = 1
6786 23:03:51.048547 14, 0x0, sum = 2
6787 23:03:51.051825 15, 0x0, sum = 3
6788 23:03:51.051929 16, 0x0, sum = 4
6789 23:03:51.052025 best_step = 14
6790 23:03:51.052105
6791 23:03:51.055259 ==
6792 23:03:51.058455 Dram Type= 6, Freq= 0, CH_1, rank 0
6793 23:03:51.061632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6794 23:03:51.061737 ==
6795 23:03:51.061829 RX Vref Scan: 1
6796 23:03:51.061903
6797 23:03:51.065118 RX Vref 0 -> 0, step: 1
6798 23:03:51.065236
6799 23:03:51.068294 RX Delay -327 -> 252, step: 8
6800 23:03:51.068408
6801 23:03:51.071540 Set Vref, RX VrefLevel [Byte0]: 50
6802 23:03:51.074631 [Byte1]: 52
6803 23:03:51.078404
6804 23:03:51.078491 Final RX Vref Byte 0 = 50 to rank0
6805 23:03:51.082112 Final RX Vref Byte 1 = 52 to rank0
6806 23:03:51.085032 Final RX Vref Byte 0 = 50 to rank1
6807 23:03:51.088599 Final RX Vref Byte 1 = 52 to rank1==
6808 23:03:51.091592 Dram Type= 6, Freq= 0, CH_1, rank 0
6809 23:03:51.098559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6810 23:03:51.098681 ==
6811 23:03:51.098790 DQS Delay:
6812 23:03:51.102144 DQS0 = 32, DQS1 = 40
6813 23:03:51.102242 DQM Delay:
6814 23:03:51.102331 DQM0 = 12, DQM1 = 13
6815 23:03:51.105089 DQ Delay:
6816 23:03:51.108366 DQ0 =12, DQ1 =8, DQ2 =0, DQ3 =8
6817 23:03:51.108465 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6818 23:03:51.111974 DQ8 =4, DQ9 =0, DQ10 =20, DQ11 =8
6819 23:03:51.114831 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =20
6820 23:03:51.114905
6821 23:03:51.118313
6822 23:03:51.125098 [DQSOSCAuto] RK0, (LSB)MR18= 0x92cc, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6823 23:03:51.128492 CH1 RK0: MR19=C0C, MR18=92CC
6824 23:03:51.135350 CH1_RK0: MR19=0xC0C, MR18=0x92CC, DQSOSC=384, MR23=63, INC=400, DEC=267
6825 23:03:51.135455 ==
6826 23:03:51.138349 Dram Type= 6, Freq= 0, CH_1, rank 1
6827 23:03:51.141404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6828 23:03:51.141502 ==
6829 23:03:51.144967 [Gating] SW mode calibration
6830 23:03:51.151669 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6831 23:03:51.158238 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6832 23:03:51.161360 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6833 23:03:51.164734 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6834 23:03:51.168415 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6835 23:03:51.174774 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6836 23:03:51.178288 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6837 23:03:51.181568 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6838 23:03:51.188092 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6839 23:03:51.191334 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6840 23:03:51.194892 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6841 23:03:51.198218 Total UI for P1: 0, mck2ui 16
6842 23:03:51.201394 best dqsien dly found for B0: ( 0, 14, 24)
6843 23:03:51.204802 Total UI for P1: 0, mck2ui 16
6844 23:03:51.207994 best dqsien dly found for B1: ( 0, 14, 24)
6845 23:03:51.211261 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6846 23:03:51.214602 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6847 23:03:51.218122
6848 23:03:51.221224 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6849 23:03:51.224665 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6850 23:03:51.227873 [Gating] SW calibration Done
6851 23:03:51.227974 ==
6852 23:03:51.231486 Dram Type= 6, Freq= 0, CH_1, rank 1
6853 23:03:51.234539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6854 23:03:51.234645 ==
6855 23:03:51.234736 RX Vref Scan: 0
6856 23:03:51.234825
6857 23:03:51.238278 RX Vref 0 -> 0, step: 1
6858 23:03:51.238377
6859 23:03:51.241154 RX Delay -410 -> 252, step: 16
6860 23:03:51.244541 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6861 23:03:51.251480 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6862 23:03:51.254468 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6863 23:03:51.257855 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6864 23:03:51.261003 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6865 23:03:51.267986 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6866 23:03:51.271056 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6867 23:03:51.274139 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6868 23:03:51.277566 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6869 23:03:51.284172 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6870 23:03:51.287674 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6871 23:03:51.291171 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6872 23:03:51.293894 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6873 23:03:51.300768 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6874 23:03:51.303879 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6875 23:03:51.307297 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6876 23:03:51.307380 ==
6877 23:03:51.310423 Dram Type= 6, Freq= 0, CH_1, rank 1
6878 23:03:51.316923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6879 23:03:51.317027 ==
6880 23:03:51.317125 DQS Delay:
6881 23:03:51.320675 DQS0 = 35, DQS1 = 35
6882 23:03:51.320750 DQM Delay:
6883 23:03:51.323696 DQM0 = 17, DQM1 = 13
6884 23:03:51.323812 DQ Delay:
6885 23:03:51.326949 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6886 23:03:51.330481 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =16
6887 23:03:51.333664 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6888 23:03:51.337199 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6889 23:03:51.337300
6890 23:03:51.337391
6891 23:03:51.337527 ==
6892 23:03:51.340345 Dram Type= 6, Freq= 0, CH_1, rank 1
6893 23:03:51.343712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6894 23:03:51.343812 ==
6895 23:03:51.343903
6896 23:03:51.343995
6897 23:03:51.346912 TX Vref Scan disable
6898 23:03:51.347026 == TX Byte 0 ==
6899 23:03:51.353735 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6900 23:03:51.357022 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6901 23:03:51.357123 == TX Byte 1 ==
6902 23:03:51.360690 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6903 23:03:51.367347 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6904 23:03:51.367452 ==
6905 23:03:51.370504 Dram Type= 6, Freq= 0, CH_1, rank 1
6906 23:03:51.373583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6907 23:03:51.373689 ==
6908 23:03:51.373780
6909 23:03:51.373867
6910 23:03:51.376802 TX Vref Scan disable
6911 23:03:51.376910 == TX Byte 0 ==
6912 23:03:51.383995 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6913 23:03:51.387081 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6914 23:03:51.387184 == TX Byte 1 ==
6915 23:03:51.393506 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6916 23:03:51.396646 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6917 23:03:51.396747
6918 23:03:51.396849 [DATLAT]
6919 23:03:51.399763 Freq=400, CH1 RK1
6920 23:03:51.399856
6921 23:03:51.399947 DATLAT Default: 0xe
6922 23:03:51.403164 0, 0xFFFF, sum = 0
6923 23:03:51.403267 1, 0xFFFF, sum = 0
6924 23:03:51.406552 2, 0xFFFF, sum = 0
6925 23:03:51.406658 3, 0xFFFF, sum = 0
6926 23:03:51.409858 4, 0xFFFF, sum = 0
6927 23:03:51.409960 5, 0xFFFF, sum = 0
6928 23:03:51.413239 6, 0xFFFF, sum = 0
6929 23:03:51.413345 7, 0xFFFF, sum = 0
6930 23:03:51.417055 8, 0xFFFF, sum = 0
6931 23:03:51.417171 9, 0xFFFF, sum = 0
6932 23:03:51.419703 10, 0xFFFF, sum = 0
6933 23:03:51.423204 11, 0xFFFF, sum = 0
6934 23:03:51.423318 12, 0xFFFF, sum = 0
6935 23:03:51.426347 13, 0x0, sum = 1
6936 23:03:51.426465 14, 0x0, sum = 2
6937 23:03:51.426570 15, 0x0, sum = 3
6938 23:03:51.429819 16, 0x0, sum = 4
6939 23:03:51.429923 best_step = 14
6940 23:03:51.430014
6941 23:03:51.433097 ==
6942 23:03:51.433220 Dram Type= 6, Freq= 0, CH_1, rank 1
6943 23:03:51.439936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6944 23:03:51.440064 ==
6945 23:03:51.440175 RX Vref Scan: 0
6946 23:03:51.440267
6947 23:03:51.443059 RX Vref 0 -> 0, step: 1
6948 23:03:51.443157
6949 23:03:51.446250 RX Delay -311 -> 252, step: 8
6950 23:03:51.452844 iDelay=217, Bit 0, Center -16 (-231 ~ 200) 432
6951 23:03:51.456721 iDelay=217, Bit 1, Center -28 (-247 ~ 192) 440
6952 23:03:51.459598 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6953 23:03:51.463338 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6954 23:03:51.469541 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6955 23:03:51.472630 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6956 23:03:51.476215 iDelay=217, Bit 6, Center -16 (-239 ~ 208) 448
6957 23:03:51.479347 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
6958 23:03:51.486132 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6959 23:03:51.489229 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
6960 23:03:51.492687 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
6961 23:03:51.496251 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6962 23:03:51.502796 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
6963 23:03:51.505949 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6964 23:03:51.509466 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6965 23:03:51.516165 iDelay=217, Bit 15, Center -16 (-247 ~ 216) 464
6966 23:03:51.516266 ==
6967 23:03:51.519314 Dram Type= 6, Freq= 0, CH_1, rank 1
6968 23:03:51.522735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6969 23:03:51.522821 ==
6970 23:03:51.522891 DQS Delay:
6971 23:03:51.526095 DQS0 = 28, DQS1 = 36
6972 23:03:51.526199 DQM Delay:
6973 23:03:51.529325 DQM0 = 9, DQM1 = 11
6974 23:03:51.529425 DQ Delay:
6975 23:03:51.532469 DQ0 =12, DQ1 =0, DQ2 =0, DQ3 =8
6976 23:03:51.535717 DQ4 =12, DQ5 =20, DQ6 =12, DQ7 =8
6977 23:03:51.539386 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6978 23:03:51.542992 DQ12 =16, DQ13 =20, DQ14 =16, DQ15 =20
6979 23:03:51.543111
6980 23:03:51.543208
6981 23:03:51.549311 [DQSOSCAuto] RK1, (LSB)MR18= 0xaf56, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 388 ps
6982 23:03:51.552681 CH1 RK1: MR19=C0C, MR18=AF56
6983 23:03:51.559557 CH1_RK1: MR19=0xC0C, MR18=0xAF56, DQSOSC=388, MR23=63, INC=392, DEC=261
6984 23:03:51.562501 [RxdqsGatingPostProcess] freq 400
6985 23:03:51.566244 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6986 23:03:51.569416 best DQS0 dly(2T, 0.5T) = (0, 10)
6987 23:03:51.572609 best DQS1 dly(2T, 0.5T) = (0, 10)
6988 23:03:51.576060 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6989 23:03:51.579298 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6990 23:03:51.582903 best DQS0 dly(2T, 0.5T) = (0, 10)
6991 23:03:51.585953 best DQS1 dly(2T, 0.5T) = (0, 10)
6992 23:03:51.589071 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6993 23:03:51.592663 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6994 23:03:51.596118 Pre-setting of DQS Precalculation
6995 23:03:51.599236 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6996 23:03:51.609080 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6997 23:03:51.615963 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6998 23:03:51.616062
6999 23:03:51.616154
7000 23:03:51.619336 [Calibration Summary] 800 Mbps
7001 23:03:51.619433 CH 0, Rank 0
7002 23:03:51.622519 SW Impedance : PASS
7003 23:03:51.622605 DUTY Scan : NO K
7004 23:03:51.625804 ZQ Calibration : PASS
7005 23:03:51.629040 Jitter Meter : NO K
7006 23:03:51.629143 CBT Training : PASS
7007 23:03:51.632276 Write leveling : PASS
7008 23:03:51.635765 RX DQS gating : PASS
7009 23:03:51.635869 RX DQ/DQS(RDDQC) : PASS
7010 23:03:51.639398 TX DQ/DQS : PASS
7011 23:03:51.642537 RX DATLAT : PASS
7012 23:03:51.642612 RX DQ/DQS(Engine): PASS
7013 23:03:51.645987 TX OE : NO K
7014 23:03:51.646089 All Pass.
7015 23:03:51.646192
7016 23:03:51.648905 CH 0, Rank 1
7017 23:03:51.649002 SW Impedance : PASS
7018 23:03:51.652718 DUTY Scan : NO K
7019 23:03:51.655731 ZQ Calibration : PASS
7020 23:03:51.655835 Jitter Meter : NO K
7021 23:03:51.659134 CBT Training : PASS
7022 23:03:51.659237 Write leveling : NO K
7023 23:03:51.662514 RX DQS gating : PASS
7024 23:03:51.665751 RX DQ/DQS(RDDQC) : PASS
7025 23:03:51.665853 TX DQ/DQS : PASS
7026 23:03:51.669185 RX DATLAT : PASS
7027 23:03:51.672288 RX DQ/DQS(Engine): PASS
7028 23:03:51.672388 TX OE : NO K
7029 23:03:51.675988 All Pass.
7030 23:03:51.676090
7031 23:03:51.676181 CH 1, Rank 0
7032 23:03:51.679127 SW Impedance : PASS
7033 23:03:51.679231 DUTY Scan : NO K
7034 23:03:51.682471 ZQ Calibration : PASS
7035 23:03:51.685600 Jitter Meter : NO K
7036 23:03:51.685700 CBT Training : PASS
7037 23:03:51.689225 Write leveling : PASS
7038 23:03:51.692529 RX DQS gating : PASS
7039 23:03:51.692632 RX DQ/DQS(RDDQC) : PASS
7040 23:03:51.695768 TX DQ/DQS : PASS
7041 23:03:51.698806 RX DATLAT : PASS
7042 23:03:51.698879 RX DQ/DQS(Engine): PASS
7043 23:03:51.702071 TX OE : NO K
7044 23:03:51.702171 All Pass.
7045 23:03:51.702261
7046 23:03:51.705248 CH 1, Rank 1
7047 23:03:51.705350 SW Impedance : PASS
7048 23:03:51.708790 DUTY Scan : NO K
7049 23:03:51.708891 ZQ Calibration : PASS
7050 23:03:51.711929 Jitter Meter : NO K
7051 23:03:51.715604 CBT Training : PASS
7052 23:03:51.715705 Write leveling : NO K
7053 23:03:51.718644 RX DQS gating : PASS
7054 23:03:51.722151 RX DQ/DQS(RDDQC) : PASS
7055 23:03:51.722249 TX DQ/DQS : PASS
7056 23:03:51.725555 RX DATLAT : PASS
7057 23:03:51.728548 RX DQ/DQS(Engine): PASS
7058 23:03:51.728651 TX OE : NO K
7059 23:03:51.732127 All Pass.
7060 23:03:51.732226
7061 23:03:51.732319 DramC Write-DBI off
7062 23:03:51.735229 PER_BANK_REFRESH: Hybrid Mode
7063 23:03:51.735319 TX_TRACKING: ON
7064 23:03:51.745484 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7065 23:03:51.748586 [FAST_K] Save calibration result to emmc
7066 23:03:51.751890 dramc_set_vcore_voltage set vcore to 725000
7067 23:03:51.755425 Read voltage for 1600, 0
7068 23:03:51.755508 Vio18 = 0
7069 23:03:51.758568 Vcore = 725000
7070 23:03:51.758651 Vdram = 0
7071 23:03:51.758716 Vddq = 0
7072 23:03:51.761731 Vmddr = 0
7073 23:03:51.765113 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7074 23:03:51.771989 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7075 23:03:51.772072 MEM_TYPE=3, freq_sel=13
7076 23:03:51.775024 sv_algorithm_assistance_LP4_3733
7077 23:03:51.781681 ============ PULL DRAM RESETB DOWN ============
7078 23:03:51.785488 ========== PULL DRAM RESETB DOWN end =========
7079 23:03:51.788446 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7080 23:03:51.791827 ===================================
7081 23:03:51.795197 LPDDR4 DRAM CONFIGURATION
7082 23:03:51.798875 ===================================
7083 23:03:51.798957 EX_ROW_EN[0] = 0x0
7084 23:03:51.802230 EX_ROW_EN[1] = 0x0
7085 23:03:51.805309 LP4Y_EN = 0x0
7086 23:03:51.805391 WORK_FSP = 0x1
7087 23:03:51.808875 WL = 0x5
7088 23:03:51.808958 RL = 0x5
7089 23:03:51.811555 BL = 0x2
7090 23:03:51.811638 RPST = 0x0
7091 23:03:51.815063 RD_PRE = 0x0
7092 23:03:51.815146 WR_PRE = 0x1
7093 23:03:51.818354 WR_PST = 0x1
7094 23:03:51.818477 DBI_WR = 0x0
7095 23:03:51.821734 DBI_RD = 0x0
7096 23:03:51.821816 OTF = 0x1
7097 23:03:51.825089 ===================================
7098 23:03:51.828705 ===================================
7099 23:03:51.832138 ANA top config
7100 23:03:51.835119 ===================================
7101 23:03:51.835203 DLL_ASYNC_EN = 0
7102 23:03:51.838664 ALL_SLAVE_EN = 0
7103 23:03:51.841993 NEW_RANK_MODE = 1
7104 23:03:51.845140 DLL_IDLE_MODE = 1
7105 23:03:51.845223 LP45_APHY_COMB_EN = 1
7106 23:03:51.848559 TX_ODT_DIS = 0
7107 23:03:51.851822 NEW_8X_MODE = 1
7108 23:03:51.855057 ===================================
7109 23:03:51.858320 ===================================
7110 23:03:51.861761 data_rate = 3200
7111 23:03:51.865332 CKR = 1
7112 23:03:51.868516 DQ_P2S_RATIO = 8
7113 23:03:51.871961 ===================================
7114 23:03:51.872045 CA_P2S_RATIO = 8
7115 23:03:51.875535 DQ_CA_OPEN = 0
7116 23:03:51.878429 DQ_SEMI_OPEN = 0
7117 23:03:51.882074 CA_SEMI_OPEN = 0
7118 23:03:51.885263 CA_FULL_RATE = 0
7119 23:03:51.888539 DQ_CKDIV4_EN = 0
7120 23:03:51.888621 CA_CKDIV4_EN = 0
7121 23:03:51.891601 CA_PREDIV_EN = 0
7122 23:03:51.894996 PH8_DLY = 12
7123 23:03:51.898524 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7124 23:03:51.902007 DQ_AAMCK_DIV = 4
7125 23:03:51.905230 CA_AAMCK_DIV = 4
7126 23:03:51.905312 CA_ADMCK_DIV = 4
7127 23:03:51.908110 DQ_TRACK_CA_EN = 0
7128 23:03:51.912251 CA_PICK = 1600
7129 23:03:51.914704 CA_MCKIO = 1600
7130 23:03:51.918488 MCKIO_SEMI = 0
7131 23:03:51.921857 PLL_FREQ = 3068
7132 23:03:51.925008 DQ_UI_PI_RATIO = 32
7133 23:03:51.925090 CA_UI_PI_RATIO = 0
7134 23:03:51.928151 ===================================
7135 23:03:51.931567 ===================================
7136 23:03:51.934808 memory_type:LPDDR4
7137 23:03:51.938206 GP_NUM : 10
7138 23:03:51.938288 SRAM_EN : 1
7139 23:03:51.941485 MD32_EN : 0
7140 23:03:51.944721 ===================================
7141 23:03:51.948131 [ANA_INIT] >>>>>>>>>>>>>>
7142 23:03:51.951696 <<<<<< [CONFIGURE PHASE]: ANA_TX
7143 23:03:51.954972 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7144 23:03:51.958067 ===================================
7145 23:03:51.958149 data_rate = 3200,PCW = 0X7600
7146 23:03:51.961274 ===================================
7147 23:03:51.964661 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7148 23:03:51.971591 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7149 23:03:51.977993 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7150 23:03:51.981507 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7151 23:03:51.984478 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7152 23:03:51.987910 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7153 23:03:51.991371 [ANA_INIT] flow start
7154 23:03:51.994606 [ANA_INIT] PLL >>>>>>>>
7155 23:03:51.994693 [ANA_INIT] PLL <<<<<<<<
7156 23:03:51.998027 [ANA_INIT] MIDPI >>>>>>>>
7157 23:03:52.001480 [ANA_INIT] MIDPI <<<<<<<<
7158 23:03:52.001555 [ANA_INIT] DLL >>>>>>>>
7159 23:03:52.004365 [ANA_INIT] DLL <<<<<<<<
7160 23:03:52.007798 [ANA_INIT] flow end
7161 23:03:52.011139 ============ LP4 DIFF to SE enter ============
7162 23:03:52.014324 ============ LP4 DIFF to SE exit ============
7163 23:03:52.017981 [ANA_INIT] <<<<<<<<<<<<<
7164 23:03:52.021244 [Flow] Enable top DCM control >>>>>
7165 23:03:52.024520 [Flow] Enable top DCM control <<<<<
7166 23:03:52.027847 Enable DLL master slave shuffle
7167 23:03:52.031188 ==============================================================
7168 23:03:52.034373 Gating Mode config
7169 23:03:52.041030 ==============================================================
7170 23:03:52.041105 Config description:
7171 23:03:52.051118 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7172 23:03:52.057577 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7173 23:03:52.060874 SELPH_MODE 0: By rank 1: By Phase
7174 23:03:52.067796 ==============================================================
7175 23:03:52.070955 GAT_TRACK_EN = 1
7176 23:03:52.074628 RX_GATING_MODE = 2
7177 23:03:52.077515 RX_GATING_TRACK_MODE = 2
7178 23:03:52.080776 SELPH_MODE = 1
7179 23:03:52.084405 PICG_EARLY_EN = 1
7180 23:03:52.087548 VALID_LAT_VALUE = 1
7181 23:03:52.090869 ==============================================================
7182 23:03:52.093883 Enter into Gating configuration >>>>
7183 23:03:52.097350 Exit from Gating configuration <<<<
7184 23:03:52.100637 Enter into DVFS_PRE_config >>>>>
7185 23:03:52.114069 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7186 23:03:52.114153 Exit from DVFS_PRE_config <<<<<
7187 23:03:52.117354 Enter into PICG configuration >>>>
7188 23:03:52.120641 Exit from PICG configuration <<<<
7189 23:03:52.124193 [RX_INPUT] configuration >>>>>
7190 23:03:52.127181 [RX_INPUT] configuration <<<<<
7191 23:03:52.133821 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7192 23:03:52.137048 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7193 23:03:52.144010 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7194 23:03:52.150290 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7195 23:03:52.157373 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7196 23:03:52.163827 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7197 23:03:52.167187 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7198 23:03:52.170488 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7199 23:03:52.173631 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7200 23:03:52.180390 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7201 23:03:52.183798 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7202 23:03:52.186943 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7203 23:03:52.190342 ===================================
7204 23:03:52.193589 LPDDR4 DRAM CONFIGURATION
7205 23:03:52.197208 ===================================
7206 23:03:52.197290 EX_ROW_EN[0] = 0x0
7207 23:03:52.200158 EX_ROW_EN[1] = 0x0
7208 23:03:52.203738 LP4Y_EN = 0x0
7209 23:03:52.203820 WORK_FSP = 0x1
7210 23:03:52.206830 WL = 0x5
7211 23:03:52.206906 RL = 0x5
7212 23:03:52.210230 BL = 0x2
7213 23:03:52.210306 RPST = 0x0
7214 23:03:52.213738 RD_PRE = 0x0
7215 23:03:52.213815 WR_PRE = 0x1
7216 23:03:52.216750 WR_PST = 0x1
7217 23:03:52.216828 DBI_WR = 0x0
7218 23:03:52.220111 DBI_RD = 0x0
7219 23:03:52.220185 OTF = 0x1
7220 23:03:52.223917 ===================================
7221 23:03:52.226916 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7222 23:03:52.233447 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7223 23:03:52.237056 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7224 23:03:52.240264 ===================================
7225 23:03:52.243601 LPDDR4 DRAM CONFIGURATION
7226 23:03:52.247025 ===================================
7227 23:03:52.247108 EX_ROW_EN[0] = 0x10
7228 23:03:52.250143 EX_ROW_EN[1] = 0x0
7229 23:03:52.250225 LP4Y_EN = 0x0
7230 23:03:52.253209 WORK_FSP = 0x1
7231 23:03:52.256779 WL = 0x5
7232 23:03:52.256863 RL = 0x5
7233 23:03:52.259905 BL = 0x2
7234 23:03:52.259988 RPST = 0x0
7235 23:03:52.263248 RD_PRE = 0x0
7236 23:03:52.263331 WR_PRE = 0x1
7237 23:03:52.266751 WR_PST = 0x1
7238 23:03:52.266834 DBI_WR = 0x0
7239 23:03:52.270153 DBI_RD = 0x0
7240 23:03:52.270241 OTF = 0x1
7241 23:03:52.273371 ===================================
7242 23:03:52.280150 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7243 23:03:52.280233 ==
7244 23:03:52.283194 Dram Type= 6, Freq= 0, CH_0, rank 0
7245 23:03:52.286734 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7246 23:03:52.286818 ==
7247 23:03:52.289771 [Duty_Offset_Calibration]
7248 23:03:52.293369 B0:2 B1:0 CA:1
7249 23:03:52.293455
7250 23:03:52.296458 [DutyScan_Calibration_Flow] k_type=0
7251 23:03:52.304295
7252 23:03:52.304378 ==CLK 0==
7253 23:03:52.307581 Final CLK duty delay cell = -4
7254 23:03:52.311004 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7255 23:03:52.314091 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7256 23:03:52.317607 [-4] AVG Duty = 4906%(X100)
7257 23:03:52.317691
7258 23:03:52.320660 CH0 CLK Duty spec in!! Max-Min= 187%
7259 23:03:52.324016 [DutyScan_Calibration_Flow] ====Done====
7260 23:03:52.324100
7261 23:03:52.327811 [DutyScan_Calibration_Flow] k_type=1
7262 23:03:52.343813
7263 23:03:52.343897 ==DQS 0 ==
7264 23:03:52.346976 Final DQS duty delay cell = 0
7265 23:03:52.350219 [0] MAX Duty = 5249%(X100), DQS PI = 36
7266 23:03:52.353496 [0] MIN Duty = 4969%(X100), DQS PI = 2
7267 23:03:52.353581 [0] AVG Duty = 5109%(X100)
7268 23:03:52.357125
7269 23:03:52.357220 ==DQS 1 ==
7270 23:03:52.360732 Final DQS duty delay cell = -4
7271 23:03:52.363831 [-4] MAX Duty = 5125%(X100), DQS PI = 28
7272 23:03:52.367241 [-4] MIN Duty = 4875%(X100), DQS PI = 4
7273 23:03:52.370813 [-4] AVG Duty = 5000%(X100)
7274 23:03:52.370896
7275 23:03:52.373736 CH0 DQS 0 Duty spec in!! Max-Min= 280%
7276 23:03:52.373820
7277 23:03:52.377004 CH0 DQS 1 Duty spec in!! Max-Min= 250%
7278 23:03:52.380341 [DutyScan_Calibration_Flow] ====Done====
7279 23:03:52.380424
7280 23:03:52.383821 [DutyScan_Calibration_Flow] k_type=3
7281 23:03:52.401157
7282 23:03:52.401240 ==DQM 0 ==
7283 23:03:52.404382 Final DQM duty delay cell = 0
7284 23:03:52.407510 [0] MAX Duty = 5093%(X100), DQS PI = 26
7285 23:03:52.411335 [0] MIN Duty = 4813%(X100), DQS PI = 52
7286 23:03:52.414414 [0] AVG Duty = 4953%(X100)
7287 23:03:52.414511
7288 23:03:52.414577 ==DQM 1 ==
7289 23:03:52.417642 Final DQM duty delay cell = 0
7290 23:03:52.421068 [0] MAX Duty = 5249%(X100), DQS PI = 28
7291 23:03:52.424279 [0] MIN Duty = 5000%(X100), DQS PI = 20
7292 23:03:52.427870 [0] AVG Duty = 5124%(X100)
7293 23:03:52.427954
7294 23:03:52.431096 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7295 23:03:52.431179
7296 23:03:52.434638 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7297 23:03:52.437732 [DutyScan_Calibration_Flow] ====Done====
7298 23:03:52.437815
7299 23:03:52.440795 [DutyScan_Calibration_Flow] k_type=2
7300 23:03:52.458322
7301 23:03:52.458443 ==DQ 0 ==
7302 23:03:52.461534 Final DQ duty delay cell = 0
7303 23:03:52.464803 [0] MAX Duty = 5124%(X100), DQS PI = 34
7304 23:03:52.468360 [0] MIN Duty = 5000%(X100), DQS PI = 0
7305 23:03:52.468444 [0] AVG Duty = 5062%(X100)
7306 23:03:52.468511
7307 23:03:52.471537 ==DQ 1 ==
7308 23:03:52.474870 Final DQ duty delay cell = 0
7309 23:03:52.478308 [0] MAX Duty = 4969%(X100), DQS PI = 44
7310 23:03:52.481726 [0] MIN Duty = 4875%(X100), DQS PI = 10
7311 23:03:52.481808 [0] AVG Duty = 4922%(X100)
7312 23:03:52.481873
7313 23:03:52.484870 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7314 23:03:52.488336
7315 23:03:52.488417 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7316 23:03:52.494856 [DutyScan_Calibration_Flow] ====Done====
7317 23:03:52.494938 ==
7318 23:03:52.498258 Dram Type= 6, Freq= 0, CH_1, rank 0
7319 23:03:52.501557 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7320 23:03:52.501638 ==
7321 23:03:52.504967 [Duty_Offset_Calibration]
7322 23:03:52.505074 B0:0 B1:-1 CA:2
7323 23:03:52.505177
7324 23:03:52.508212 [DutyScan_Calibration_Flow] k_type=0
7325 23:03:52.518558
7326 23:03:52.518640 ==CLK 0==
7327 23:03:52.521932 Final CLK duty delay cell = 0
7328 23:03:52.525358 [0] MAX Duty = 5156%(X100), DQS PI = 10
7329 23:03:52.528587 [0] MIN Duty = 4906%(X100), DQS PI = 46
7330 23:03:52.528668 [0] AVG Duty = 5031%(X100)
7331 23:03:52.532005
7332 23:03:52.532086 CH1 CLK Duty spec in!! Max-Min= 250%
7333 23:03:52.538380 [DutyScan_Calibration_Flow] ====Done====
7334 23:03:52.538498
7335 23:03:52.541754 [DutyScan_Calibration_Flow] k_type=1
7336 23:03:52.558288
7337 23:03:52.558405 ==DQS 0 ==
7338 23:03:52.561876 Final DQS duty delay cell = 0
7339 23:03:52.564997 [0] MAX Duty = 5124%(X100), DQS PI = 26
7340 23:03:52.568149 [0] MIN Duty = 4969%(X100), DQS PI = 0
7341 23:03:52.568225 [0] AVG Duty = 5046%(X100)
7342 23:03:52.571305
7343 23:03:52.571389 ==DQS 1 ==
7344 23:03:52.575163 Final DQS duty delay cell = 0
7345 23:03:52.578250 [0] MAX Duty = 5187%(X100), DQS PI = 0
7346 23:03:52.581718 [0] MIN Duty = 4844%(X100), DQS PI = 32
7347 23:03:52.581800 [0] AVG Duty = 5015%(X100)
7348 23:03:52.584629
7349 23:03:52.587982 CH1 DQS 0 Duty spec in!! Max-Min= 155%
7350 23:03:52.588064
7351 23:03:52.591632 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7352 23:03:52.594647 [DutyScan_Calibration_Flow] ====Done====
7353 23:03:52.594728
7354 23:03:52.598022 [DutyScan_Calibration_Flow] k_type=3
7355 23:03:52.615673
7356 23:03:52.615755 ==DQM 0 ==
7357 23:03:52.619189 Final DQM duty delay cell = 4
7358 23:03:52.622593 [4] MAX Duty = 5125%(X100), DQS PI = 8
7359 23:03:52.625892 [4] MIN Duty = 5000%(X100), DQS PI = 32
7360 23:03:52.628921 [4] AVG Duty = 5062%(X100)
7361 23:03:52.629002
7362 23:03:52.629067 ==DQM 1 ==
7363 23:03:52.632224 Final DQM duty delay cell = 0
7364 23:03:52.635635 [0] MAX Duty = 5281%(X100), DQS PI = 58
7365 23:03:52.638760 [0] MIN Duty = 4876%(X100), DQS PI = 34
7366 23:03:52.638844 [0] AVG Duty = 5078%(X100)
7367 23:03:52.642331
7368 23:03:52.645782 CH1 DQM 0 Duty spec in!! Max-Min= 125%
7369 23:03:52.645866
7370 23:03:52.649066 CH1 DQM 1 Duty spec in!! Max-Min= 405%
7371 23:03:52.652293 [DutyScan_Calibration_Flow] ====Done====
7372 23:03:52.652377
7373 23:03:52.655468 [DutyScan_Calibration_Flow] k_type=2
7374 23:03:52.672668
7375 23:03:52.672752 ==DQ 0 ==
7376 23:03:52.675978 Final DQ duty delay cell = 0
7377 23:03:52.679345 [0] MAX Duty = 5062%(X100), DQS PI = 16
7378 23:03:52.682405 [0] MIN Duty = 4969%(X100), DQS PI = 46
7379 23:03:52.682530 [0] AVG Duty = 5015%(X100)
7380 23:03:52.685776
7381 23:03:52.685859 ==DQ 1 ==
7382 23:03:52.688981 Final DQ duty delay cell = 0
7383 23:03:52.692401 [0] MAX Duty = 5062%(X100), DQS PI = 2
7384 23:03:52.695869 [0] MIN Duty = 4813%(X100), DQS PI = 34
7385 23:03:52.695953 [0] AVG Duty = 4937%(X100)
7386 23:03:52.696020
7387 23:03:52.699040 CH1 DQ 0 Duty spec in!! Max-Min= 93%
7388 23:03:52.702380
7389 23:03:52.705766 CH1 DQ 1 Duty spec in!! Max-Min= 249%
7390 23:03:52.709198 [DutyScan_Calibration_Flow] ====Done====
7391 23:03:52.712367 nWR fixed to 30
7392 23:03:52.712451 [ModeRegInit_LP4] CH0 RK0
7393 23:03:52.715792 [ModeRegInit_LP4] CH0 RK1
7394 23:03:52.719202 [ModeRegInit_LP4] CH1 RK0
7395 23:03:52.719286 [ModeRegInit_LP4] CH1 RK1
7396 23:03:52.722375 match AC timing 5
7397 23:03:52.726128 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7398 23:03:52.728853 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7399 23:03:52.736094 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7400 23:03:52.738892 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7401 23:03:52.745411 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7402 23:03:52.745495 [MiockJmeterHQA]
7403 23:03:52.745562
7404 23:03:52.749336 [DramcMiockJmeter] u1RxGatingPI = 0
7405 23:03:52.752341 0 : 4252, 4027
7406 23:03:52.752426 4 : 4252, 4027
7407 23:03:52.752494 8 : 4252, 4027
7408 23:03:52.755776 12 : 4363, 4137
7409 23:03:52.755868 16 : 4252, 4027
7410 23:03:52.759077 20 : 4255, 4029
7411 23:03:52.759161 24 : 4252, 4027
7412 23:03:52.762143 28 : 4363, 4137
7413 23:03:52.762227 32 : 4252, 4027
7414 23:03:52.765631 36 : 4363, 4137
7415 23:03:52.765715 40 : 4252, 4027
7416 23:03:52.765782 44 : 4252, 4027
7417 23:03:52.769007 48 : 4253, 4026
7418 23:03:52.769093 52 : 4258, 4032
7419 23:03:52.772101 56 : 4363, 4137
7420 23:03:52.772186 60 : 4250, 4027
7421 23:03:52.775565 64 : 4363, 4138
7422 23:03:52.775650 68 : 4252, 4027
7423 23:03:52.779181 72 : 4250, 4027
7424 23:03:52.779266 76 : 4249, 4027
7425 23:03:52.779334 80 : 4361, 4137
7426 23:03:52.782280 84 : 4250, 4027
7427 23:03:52.782419 88 : 4360, 3872
7428 23:03:52.785735 92 : 4250, 0
7429 23:03:52.785819 96 : 4361, 0
7430 23:03:52.785886 100 : 4249, 0
7431 23:03:52.789128 104 : 4360, 0
7432 23:03:52.789212 108 : 4250, 0
7433 23:03:52.792432 112 : 4250, 0
7434 23:03:52.792517 116 : 4250, 0
7435 23:03:52.792596 120 : 4250, 0
7436 23:03:52.795429 124 : 4250, 0
7437 23:03:52.795514 128 : 4250, 0
7438 23:03:52.798580 132 : 4252, 0
7439 23:03:52.798664 136 : 4360, 0
7440 23:03:52.798732 140 : 4361, 0
7441 23:03:52.802060 144 : 4363, 0
7442 23:03:52.802173 148 : 4250, 0
7443 23:03:52.802273 152 : 4250, 0
7444 23:03:52.805412 156 : 4250, 0
7445 23:03:52.805497 160 : 4250, 0
7446 23:03:52.808791 164 : 4250, 0
7447 23:03:52.808875 168 : 4250, 0
7448 23:03:52.808943 172 : 4252, 0
7449 23:03:52.812093 176 : 4250, 0
7450 23:03:52.812177 180 : 4250, 0
7451 23:03:52.815218 184 : 4253, 0
7452 23:03:52.815303 188 : 4360, 0
7453 23:03:52.815371 192 : 4361, 0
7454 23:03:52.818615 196 : 4363, 0
7455 23:03:52.818700 200 : 4249, 12
7456 23:03:52.821860 204 : 4361, 2860
7457 23:03:52.821944 208 : 4250, 4027
7458 23:03:52.825583 212 : 4250, 4026
7459 23:03:52.825668 216 : 4253, 4029
7460 23:03:52.828624 220 : 4250, 4027
7461 23:03:52.828708 224 : 4250, 4026
7462 23:03:52.828776 228 : 4250, 4026
7463 23:03:52.831820 232 : 4250, 4027
7464 23:03:52.831905 236 : 4249, 4027
7465 23:03:52.835283 240 : 4360, 4137
7466 23:03:52.835367 244 : 4361, 4137
7467 23:03:52.838685 248 : 4247, 4025
7468 23:03:52.838769 252 : 4360, 4138
7469 23:03:52.841897 256 : 4360, 4137
7470 23:03:52.841982 260 : 4250, 4026
7471 23:03:52.845207 264 : 4250, 4027
7472 23:03:52.845292 268 : 4250, 4027
7473 23:03:52.848755 272 : 4249, 4027
7474 23:03:52.848840 276 : 4249, 4027
7475 23:03:52.848907 280 : 4250, 4027
7476 23:03:52.852115 284 : 4250, 4027
7477 23:03:52.852200 288 : 4249, 4027
7478 23:03:52.855343 292 : 4360, 4137
7479 23:03:52.855428 296 : 4361, 4138
7480 23:03:52.858604 300 : 4247, 4025
7481 23:03:52.858688 304 : 4360, 4138
7482 23:03:52.861920 308 : 4360, 4137
7483 23:03:52.862004 312 : 4250, 3849
7484 23:03:52.865455 316 : 4250, 1936
7485 23:03:52.865539
7486 23:03:52.865605 MIOCK jitter meter ch=0
7487 23:03:52.865667
7488 23:03:52.868930 1T = (316-92) = 224 dly cells
7489 23:03:52.875704 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7490 23:03:52.875793 ==
7491 23:03:52.878826 Dram Type= 6, Freq= 0, CH_0, rank 0
7492 23:03:52.882126 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7493 23:03:52.882237 ==
7494 23:03:52.888857 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7495 23:03:52.891756 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7496 23:03:52.895473 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7497 23:03:52.901742 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7498 23:03:52.911220 [CA 0] Center 42 (12~73) winsize 62
7499 23:03:52.914775 [CA 1] Center 42 (12~72) winsize 61
7500 23:03:52.917963 [CA 2] Center 37 (7~67) winsize 61
7501 23:03:52.921631 [CA 3] Center 37 (7~67) winsize 61
7502 23:03:52.924838 [CA 4] Center 36 (6~66) winsize 61
7503 23:03:52.928189 [CA 5] Center 35 (5~65) winsize 61
7504 23:03:52.928272
7505 23:03:52.931215 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7506 23:03:52.931299
7507 23:03:52.934644 [CATrainingPosCal] consider 1 rank data
7508 23:03:52.938025 u2DelayCellTimex100 = 290/100 ps
7509 23:03:52.941288 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7510 23:03:52.948017 CA1 delay=42 (12~72),Diff = 7 PI (23 cell)
7511 23:03:52.951286 CA2 delay=37 (7~67),Diff = 2 PI (6 cell)
7512 23:03:52.954537 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7513 23:03:52.957876 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7514 23:03:52.961383 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7515 23:03:52.961467
7516 23:03:52.964409 CA PerBit enable=1, Macro0, CA PI delay=35
7517 23:03:52.964493
7518 23:03:52.967763 [CBTSetCACLKResult] CA Dly = 35
7519 23:03:52.971428 CS Dly: 9 (0~40)
7520 23:03:52.974364 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7521 23:03:52.977949 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7522 23:03:52.978033 ==
7523 23:03:52.981325 Dram Type= 6, Freq= 0, CH_0, rank 1
7524 23:03:52.984241 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7525 23:03:52.987899 ==
7526 23:03:52.991278 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7527 23:03:52.994542 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7528 23:03:53.000856 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7529 23:03:53.004194 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7530 23:03:53.014705 [CA 0] Center 43 (13~73) winsize 61
7531 23:03:53.018093 [CA 1] Center 43 (13~73) winsize 61
7532 23:03:53.021466 [CA 2] Center 37 (8~67) winsize 60
7533 23:03:53.025033 [CA 3] Center 38 (8~68) winsize 61
7534 23:03:53.028253 [CA 4] Center 36 (6~66) winsize 61
7535 23:03:53.031310 [CA 5] Center 36 (6~66) winsize 61
7536 23:03:53.031397
7537 23:03:53.034299 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7538 23:03:53.034443
7539 23:03:53.037806 [CATrainingPosCal] consider 2 rank data
7540 23:03:53.041209 u2DelayCellTimex100 = 290/100 ps
7541 23:03:53.044322 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7542 23:03:53.051422 CA1 delay=42 (13~72),Diff = 7 PI (23 cell)
7543 23:03:53.054646 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7544 23:03:53.057993 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7545 23:03:53.061035 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7546 23:03:53.064591 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7547 23:03:53.064674
7548 23:03:53.067771 CA PerBit enable=1, Macro0, CA PI delay=35
7549 23:03:53.067855
7550 23:03:53.071331 [CBTSetCACLKResult] CA Dly = 35
7551 23:03:53.074772 CS Dly: 10 (0~43)
7552 23:03:53.077892 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7553 23:03:53.080927 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7554 23:03:53.081011
7555 23:03:53.084622 ----->DramcWriteLeveling(PI) begin...
7556 23:03:53.084707 ==
7557 23:03:53.087827 Dram Type= 6, Freq= 0, CH_0, rank 0
7558 23:03:53.094282 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7559 23:03:53.094366 ==
7560 23:03:53.097817 Write leveling (Byte 0): 35 => 35
7561 23:03:53.097901 Write leveling (Byte 1): 31 => 31
7562 23:03:53.100752 DramcWriteLeveling(PI) end<-----
7563 23:03:53.100835
7564 23:03:53.100901 ==
7565 23:03:53.104154 Dram Type= 6, Freq= 0, CH_0, rank 0
7566 23:03:53.110877 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7567 23:03:53.110961 ==
7568 23:03:53.114102 [Gating] SW mode calibration
7569 23:03:53.120758 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7570 23:03:53.124057 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7571 23:03:53.131011 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7572 23:03:53.133902 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7573 23:03:53.137503 1 4 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
7574 23:03:53.144626 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7575 23:03:53.147298 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7576 23:03:53.150809 1 4 20 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
7577 23:03:53.157375 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7578 23:03:53.160835 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7579 23:03:53.163970 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7580 23:03:53.167328 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7581 23:03:53.174030 1 5 8 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 0)
7582 23:03:53.177264 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7583 23:03:53.180582 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (0 0) (0 0)
7584 23:03:53.187463 1 5 20 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
7585 23:03:53.190787 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7586 23:03:53.193920 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7587 23:03:53.200849 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7588 23:03:53.204118 1 6 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7589 23:03:53.207386 1 6 8 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
7590 23:03:53.214222 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7591 23:03:53.217933 1 6 16 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
7592 23:03:53.221021 1 6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7593 23:03:53.227327 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7594 23:03:53.230553 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7595 23:03:53.233826 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7596 23:03:53.240517 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7597 23:03:53.244117 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7598 23:03:53.247553 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7599 23:03:53.253811 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7600 23:03:53.256982 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7601 23:03:53.260695 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7602 23:03:53.267252 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7603 23:03:53.270636 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7604 23:03:53.273830 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7605 23:03:53.280317 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7606 23:03:53.284149 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7607 23:03:53.287170 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7608 23:03:53.290477 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7609 23:03:53.296954 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7610 23:03:53.300687 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7611 23:03:53.303629 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7612 23:03:53.310575 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7613 23:03:53.313531 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7614 23:03:53.317367 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7615 23:03:53.323914 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7616 23:03:53.327228 Total UI for P1: 0, mck2ui 16
7617 23:03:53.330412 best dqsien dly found for B0: ( 1, 9, 10)
7618 23:03:53.334000 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7619 23:03:53.337219 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7620 23:03:53.340538 Total UI for P1: 0, mck2ui 16
7621 23:03:53.343658 best dqsien dly found for B1: ( 1, 9, 18)
7622 23:03:53.347182 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7623 23:03:53.350280 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7624 23:03:53.350364
7625 23:03:53.357106 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7626 23:03:53.360116 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7627 23:03:53.363880 [Gating] SW calibration Done
7628 23:03:53.363963 ==
7629 23:03:53.366977 Dram Type= 6, Freq= 0, CH_0, rank 0
7630 23:03:53.370277 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7631 23:03:53.370361 ==
7632 23:03:53.370463 RX Vref Scan: 0
7633 23:03:53.370526
7634 23:03:53.373468 RX Vref 0 -> 0, step: 1
7635 23:03:53.373577
7636 23:03:53.376843 RX Delay 0 -> 252, step: 8
7637 23:03:53.379973 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7638 23:03:53.383510 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7639 23:03:53.386683 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7640 23:03:53.393602 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7641 23:03:53.396667 iDelay=200, Bit 4, Center 143 (96 ~ 191) 96
7642 23:03:53.399891 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
7643 23:03:53.403248 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7644 23:03:53.406685 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7645 23:03:53.413192 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7646 23:03:53.416930 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7647 23:03:53.419922 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7648 23:03:53.423162 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
7649 23:03:53.426368 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7650 23:03:53.433039 iDelay=200, Bit 13, Center 127 (80 ~ 175) 96
7651 23:03:53.436449 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7652 23:03:53.439746 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7653 23:03:53.439828 ==
7654 23:03:53.443314 Dram Type= 6, Freq= 0, CH_0, rank 0
7655 23:03:53.446314 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7656 23:03:53.446439 ==
7657 23:03:53.449610 DQS Delay:
7658 23:03:53.449693 DQS0 = 0, DQS1 = 0
7659 23:03:53.453011 DQM Delay:
7660 23:03:53.453102 DQM0 = 138, DQM1 = 126
7661 23:03:53.456747 DQ Delay:
7662 23:03:53.459601 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
7663 23:03:53.462628 DQ4 =143, DQ5 =127, DQ6 =147, DQ7 =147
7664 23:03:53.466966 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =123
7665 23:03:53.469717 DQ12 =131, DQ13 =127, DQ14 =139, DQ15 =135
7666 23:03:53.469854
7667 23:03:53.469978
7668 23:03:53.470106 ==
7669 23:03:53.472783 Dram Type= 6, Freq= 0, CH_0, rank 0
7670 23:03:53.476046 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7671 23:03:53.476146 ==
7672 23:03:53.476226
7673 23:03:53.479213
7674 23:03:53.479310 TX Vref Scan disable
7675 23:03:53.482510 == TX Byte 0 ==
7676 23:03:53.485857 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7677 23:03:53.489267 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7678 23:03:53.492473 == TX Byte 1 ==
7679 23:03:53.496371 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7680 23:03:53.499371 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7681 23:03:53.499487 ==
7682 23:03:53.503167 Dram Type= 6, Freq= 0, CH_0, rank 0
7683 23:03:53.509788 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7684 23:03:53.509871 ==
7685 23:03:53.519736
7686 23:03:53.523612 TX Vref early break, caculate TX vref
7687 23:03:53.526818 TX Vref=16, minBit 4, minWin=23, winSum=378
7688 23:03:53.529909 TX Vref=18, minBit 6, minWin=23, winSum=384
7689 23:03:53.532977 TX Vref=20, minBit 12, minWin=23, winSum=397
7690 23:03:53.536271 TX Vref=22, minBit 1, minWin=25, winSum=410
7691 23:03:53.539704 TX Vref=24, minBit 5, minWin=25, winSum=418
7692 23:03:53.546264 TX Vref=26, minBit 12, minWin=25, winSum=425
7693 23:03:53.549657 TX Vref=28, minBit 2, minWin=25, winSum=428
7694 23:03:53.553126 TX Vref=30, minBit 2, minWin=25, winSum=413
7695 23:03:53.556662 TX Vref=32, minBit 1, minWin=24, winSum=404
7696 23:03:53.563097 [TxChooseVref] Worse bit 2, Min win 25, Win sum 428, Final Vref 28
7697 23:03:53.563181
7698 23:03:53.566652 Final TX Range 0 Vref 28
7699 23:03:53.566731
7700 23:03:53.566796 ==
7701 23:03:53.569656 Dram Type= 6, Freq= 0, CH_0, rank 0
7702 23:03:53.573339 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7703 23:03:53.573487 ==
7704 23:03:53.573595
7705 23:03:53.573679
7706 23:03:53.576435 TX Vref Scan disable
7707 23:03:53.579908 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7708 23:03:53.583050 == TX Byte 0 ==
7709 23:03:53.586565 u2DelayCellOfst[0]=13 cells (4 PI)
7710 23:03:53.589831 u2DelayCellOfst[1]=16 cells (5 PI)
7711 23:03:53.593174 u2DelayCellOfst[2]=10 cells (3 PI)
7712 23:03:53.596303 u2DelayCellOfst[3]=10 cells (3 PI)
7713 23:03:53.599668 u2DelayCellOfst[4]=10 cells (3 PI)
7714 23:03:53.599753 u2DelayCellOfst[5]=0 cells (0 PI)
7715 23:03:53.603187 u2DelayCellOfst[6]=16 cells (5 PI)
7716 23:03:53.606510 u2DelayCellOfst[7]=13 cells (4 PI)
7717 23:03:53.613090 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7718 23:03:53.616236 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7719 23:03:53.616347 == TX Byte 1 ==
7720 23:03:53.619847 u2DelayCellOfst[8]=0 cells (0 PI)
7721 23:03:53.623189 u2DelayCellOfst[9]=0 cells (0 PI)
7722 23:03:53.626499 u2DelayCellOfst[10]=6 cells (2 PI)
7723 23:03:53.629699 u2DelayCellOfst[11]=3 cells (1 PI)
7724 23:03:53.633138 u2DelayCellOfst[12]=13 cells (4 PI)
7725 23:03:53.636464 u2DelayCellOfst[13]=10 cells (3 PI)
7726 23:03:53.639801 u2DelayCellOfst[14]=13 cells (4 PI)
7727 23:03:53.643134 u2DelayCellOfst[15]=10 cells (3 PI)
7728 23:03:53.646146 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7729 23:03:53.650241 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7730 23:03:53.652890 DramC Write-DBI on
7731 23:03:53.652974 ==
7732 23:03:53.656401 Dram Type= 6, Freq= 0, CH_0, rank 0
7733 23:03:53.659644 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7734 23:03:53.659730 ==
7735 23:03:53.659796
7736 23:03:53.659860
7737 23:03:53.663266 TX Vref Scan disable
7738 23:03:53.666140 == TX Byte 0 ==
7739 23:03:53.669596 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7740 23:03:53.669697 == TX Byte 1 ==
7741 23:03:53.676464 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7742 23:03:53.676573 DramC Write-DBI off
7743 23:03:53.676670
7744 23:03:53.679769 [DATLAT]
7745 23:03:53.679841 Freq=1600, CH0 RK0
7746 23:03:53.679903
7747 23:03:53.683456 DATLAT Default: 0xf
7748 23:03:53.683526 0, 0xFFFF, sum = 0
7749 23:03:53.686110 1, 0xFFFF, sum = 0
7750 23:03:53.686226 2, 0xFFFF, sum = 0
7751 23:03:53.689360 3, 0xFFFF, sum = 0
7752 23:03:53.689445 4, 0xFFFF, sum = 0
7753 23:03:53.693052 5, 0xFFFF, sum = 0
7754 23:03:53.693163 6, 0xFFFF, sum = 0
7755 23:03:53.696473 7, 0xFFFF, sum = 0
7756 23:03:53.696592 8, 0xFFFF, sum = 0
7757 23:03:53.699641 9, 0xFFFF, sum = 0
7758 23:03:53.699720 10, 0xFFFF, sum = 0
7759 23:03:53.702777 11, 0xFFFF, sum = 0
7760 23:03:53.706127 12, 0xFFFF, sum = 0
7761 23:03:53.706201 13, 0xFFFF, sum = 0
7762 23:03:53.709616 14, 0x0, sum = 1
7763 23:03:53.709688 15, 0x0, sum = 2
7764 23:03:53.709750 16, 0x0, sum = 3
7765 23:03:53.713153 17, 0x0, sum = 4
7766 23:03:53.713238 best_step = 15
7767 23:03:53.713305
7768 23:03:53.713367 ==
7769 23:03:53.716586 Dram Type= 6, Freq= 0, CH_0, rank 0
7770 23:03:53.722746 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7771 23:03:53.722830 ==
7772 23:03:53.722896 RX Vref Scan: 1
7773 23:03:53.722958
7774 23:03:53.726299 Set Vref Range= 24 -> 127
7775 23:03:53.726446
7776 23:03:53.729484 RX Vref 24 -> 127, step: 1
7777 23:03:53.729568
7778 23:03:53.732794 RX Delay 19 -> 252, step: 4
7779 23:03:53.732878
7780 23:03:53.736093 Set Vref, RX VrefLevel [Byte0]: 24
7781 23:03:53.739298 [Byte1]: 24
7782 23:03:53.739381
7783 23:03:53.742788 Set Vref, RX VrefLevel [Byte0]: 25
7784 23:03:53.746029 [Byte1]: 25
7785 23:03:53.746113
7786 23:03:53.749345 Set Vref, RX VrefLevel [Byte0]: 26
7787 23:03:53.752746 [Byte1]: 26
7788 23:03:53.752830
7789 23:03:53.756274 Set Vref, RX VrefLevel [Byte0]: 27
7790 23:03:53.759525 [Byte1]: 27
7791 23:03:53.763169
7792 23:03:53.763252 Set Vref, RX VrefLevel [Byte0]: 28
7793 23:03:53.766807 [Byte1]: 28
7794 23:03:53.770966
7795 23:03:53.771049 Set Vref, RX VrefLevel [Byte0]: 29
7796 23:03:53.774173 [Byte1]: 29
7797 23:03:53.778331
7798 23:03:53.778436 Set Vref, RX VrefLevel [Byte0]: 30
7799 23:03:53.782122 [Byte1]: 30
7800 23:03:53.786126
7801 23:03:53.786209 Set Vref, RX VrefLevel [Byte0]: 31
7802 23:03:53.789353 [Byte1]: 31
7803 23:03:53.794016
7804 23:03:53.794099 Set Vref, RX VrefLevel [Byte0]: 32
7805 23:03:53.796955 [Byte1]: 32
7806 23:03:53.801372
7807 23:03:53.801455 Set Vref, RX VrefLevel [Byte0]: 33
7808 23:03:53.804679 [Byte1]: 33
7809 23:03:53.808915
7810 23:03:53.808998 Set Vref, RX VrefLevel [Byte0]: 34
7811 23:03:53.812100 [Byte1]: 34
7812 23:03:53.816160
7813 23:03:53.816243 Set Vref, RX VrefLevel [Byte0]: 35
7814 23:03:53.819576 [Byte1]: 35
7815 23:03:53.823983
7816 23:03:53.824066 Set Vref, RX VrefLevel [Byte0]: 36
7817 23:03:53.827075 [Byte1]: 36
7818 23:03:53.831628
7819 23:03:53.831710 Set Vref, RX VrefLevel [Byte0]: 37
7820 23:03:53.834936 [Byte1]: 37
7821 23:03:53.839098
7822 23:03:53.839181 Set Vref, RX VrefLevel [Byte0]: 38
7823 23:03:53.842418 [Byte1]: 38
7824 23:03:53.846669
7825 23:03:53.846752 Set Vref, RX VrefLevel [Byte0]: 39
7826 23:03:53.849712 [Byte1]: 39
7827 23:03:53.854028
7828 23:03:53.854127 Set Vref, RX VrefLevel [Byte0]: 40
7829 23:03:53.857459 [Byte1]: 40
7830 23:03:53.861910
7831 23:03:53.861985 Set Vref, RX VrefLevel [Byte0]: 41
7832 23:03:53.865378 [Byte1]: 41
7833 23:03:53.869149
7834 23:03:53.869229 Set Vref, RX VrefLevel [Byte0]: 42
7835 23:03:53.872776 [Byte1]: 42
7836 23:03:53.876750
7837 23:03:53.876849 Set Vref, RX VrefLevel [Byte0]: 43
7838 23:03:53.880136 [Byte1]: 43
7839 23:03:53.884627
7840 23:03:53.884709 Set Vref, RX VrefLevel [Byte0]: 44
7841 23:03:53.887608 [Byte1]: 44
7842 23:03:53.891896
7843 23:03:53.891978 Set Vref, RX VrefLevel [Byte0]: 45
7844 23:03:53.895764 [Byte1]: 45
7845 23:03:53.899492
7846 23:03:53.899574 Set Vref, RX VrefLevel [Byte0]: 46
7847 23:03:53.902872 [Byte1]: 46
7848 23:03:53.907423
7849 23:03:53.907505 Set Vref, RX VrefLevel [Byte0]: 47
7850 23:03:53.910740 [Byte1]: 47
7851 23:03:53.914793
7852 23:03:53.914875 Set Vref, RX VrefLevel [Byte0]: 48
7853 23:03:53.917873 [Byte1]: 48
7854 23:03:53.922403
7855 23:03:53.922485 Set Vref, RX VrefLevel [Byte0]: 49
7856 23:03:53.925660 [Byte1]: 49
7857 23:03:53.929748
7858 23:03:53.929830 Set Vref, RX VrefLevel [Byte0]: 50
7859 23:03:53.933292 [Byte1]: 50
7860 23:03:53.937380
7861 23:03:53.937489 Set Vref, RX VrefLevel [Byte0]: 51
7862 23:03:53.940649 [Byte1]: 51
7863 23:03:53.945503
7864 23:03:53.945602 Set Vref, RX VrefLevel [Byte0]: 52
7865 23:03:53.948159 [Byte1]: 52
7866 23:03:53.952873
7867 23:03:53.952955 Set Vref, RX VrefLevel [Byte0]: 53
7868 23:03:53.956077 [Byte1]: 53
7869 23:03:53.960122
7870 23:03:53.960220 Set Vref, RX VrefLevel [Byte0]: 54
7871 23:03:53.963641 [Byte1]: 54
7872 23:03:53.967624
7873 23:03:53.967706 Set Vref, RX VrefLevel [Byte0]: 55
7874 23:03:53.971066 [Byte1]: 55
7875 23:03:53.975263
7876 23:03:53.975344 Set Vref, RX VrefLevel [Byte0]: 56
7877 23:03:53.978433 [Byte1]: 56
7878 23:03:53.983135
7879 23:03:53.983217 Set Vref, RX VrefLevel [Byte0]: 57
7880 23:03:53.986075 [Byte1]: 57
7881 23:03:53.990668
7882 23:03:53.990777 Set Vref, RX VrefLevel [Byte0]: 58
7883 23:03:53.994091 [Byte1]: 58
7884 23:03:53.997835
7885 23:03:53.997917 Set Vref, RX VrefLevel [Byte0]: 59
7886 23:03:54.001716 [Byte1]: 59
7887 23:03:54.005405
7888 23:03:54.005502 Set Vref, RX VrefLevel [Byte0]: 60
7889 23:03:54.008772 [Byte1]: 60
7890 23:03:54.013134
7891 23:03:54.013253 Set Vref, RX VrefLevel [Byte0]: 61
7892 23:03:54.016696 [Byte1]: 61
7893 23:03:54.020709
7894 23:03:54.020807 Set Vref, RX VrefLevel [Byte0]: 62
7895 23:03:54.024081 [Byte1]: 62
7896 23:03:54.028210
7897 23:03:54.028292 Set Vref, RX VrefLevel [Byte0]: 63
7898 23:03:54.031552 [Byte1]: 63
7899 23:03:54.035907
7900 23:03:54.035989 Set Vref, RX VrefLevel [Byte0]: 64
7901 23:03:54.039094 [Byte1]: 64
7902 23:03:54.043488
7903 23:03:54.043570 Set Vref, RX VrefLevel [Byte0]: 65
7904 23:03:54.046749 [Byte1]: 65
7905 23:03:54.051000
7906 23:03:54.051082 Set Vref, RX VrefLevel [Byte0]: 66
7907 23:03:54.054654 [Byte1]: 66
7908 23:03:54.058488
7909 23:03:54.058598 Set Vref, RX VrefLevel [Byte0]: 67
7910 23:03:54.062112 [Byte1]: 67
7911 23:03:54.066785
7912 23:03:54.066882 Set Vref, RX VrefLevel [Byte0]: 68
7913 23:03:54.069622 [Byte1]: 68
7914 23:03:54.073684
7915 23:03:54.073766 Set Vref, RX VrefLevel [Byte0]: 69
7916 23:03:54.077108 [Byte1]: 69
7917 23:03:54.081581
7918 23:03:54.081663 Set Vref, RX VrefLevel [Byte0]: 70
7919 23:03:54.084681 [Byte1]: 70
7920 23:03:54.089163
7921 23:03:54.089245 Set Vref, RX VrefLevel [Byte0]: 71
7922 23:03:54.092709 [Byte1]: 71
7923 23:03:54.096436
7924 23:03:54.096517 Set Vref, RX VrefLevel [Byte0]: 72
7925 23:03:54.099913 [Byte1]: 72
7926 23:03:54.103856
7927 23:03:54.103938 Set Vref, RX VrefLevel [Byte0]: 73
7928 23:03:54.107360 [Byte1]: 73
7929 23:03:54.111942
7930 23:03:54.112023 Set Vref, RX VrefLevel [Byte0]: 74
7931 23:03:54.115042 [Byte1]: 74
7932 23:03:54.119287
7933 23:03:54.119364 Set Vref, RX VrefLevel [Byte0]: 75
7934 23:03:54.122867 [Byte1]: 75
7935 23:03:54.127508
7936 23:03:54.127609 Set Vref, RX VrefLevel [Byte0]: 76
7937 23:03:54.130144 [Byte1]: 76
7938 23:03:54.134201
7939 23:03:54.134286 Set Vref, RX VrefLevel [Byte0]: 77
7940 23:03:54.137801 [Byte1]: 77
7941 23:03:54.141985
7942 23:03:54.142075 Set Vref, RX VrefLevel [Byte0]: 78
7943 23:03:54.145261 [Byte1]: 78
7944 23:03:54.149514
7945 23:03:54.149592 Set Vref, RX VrefLevel [Byte0]: 79
7946 23:03:54.152964 [Byte1]: 79
7947 23:03:54.157165
7948 23:03:54.157265 Final RX Vref Byte 0 = 62 to rank0
7949 23:03:54.160326 Final RX Vref Byte 1 = 62 to rank0
7950 23:03:54.164324 Final RX Vref Byte 0 = 62 to rank1
7951 23:03:54.167418 Final RX Vref Byte 1 = 62 to rank1==
7952 23:03:54.170771 Dram Type= 6, Freq= 0, CH_0, rank 0
7953 23:03:54.177003 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7954 23:03:54.177081 ==
7955 23:03:54.177147 DQS Delay:
7956 23:03:54.177207 DQS0 = 0, DQS1 = 0
7957 23:03:54.180726 DQM Delay:
7958 23:03:54.180810 DQM0 = 136, DQM1 = 124
7959 23:03:54.183837 DQ Delay:
7960 23:03:54.186874 DQ0 =136, DQ1 =136, DQ2 =132, DQ3 =134
7961 23:03:54.190249 DQ4 =138, DQ5 =126, DQ6 =146, DQ7 =142
7962 23:03:54.193742 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =118
7963 23:03:54.197008 DQ12 =128, DQ13 =128, DQ14 =136, DQ15 =130
7964 23:03:54.197093
7965 23:03:54.197205
7966 23:03:54.197283
7967 23:03:54.200624 [DramC_TX_OE_Calibration] TA2
7968 23:03:54.204116 Original DQ_B0 (3 6) =30, OEN = 27
7969 23:03:54.207198 Original DQ_B1 (3 6) =30, OEN = 27
7970 23:03:54.210455 24, 0x0, End_B0=24 End_B1=24
7971 23:03:54.210540 25, 0x0, End_B0=25 End_B1=25
7972 23:03:54.213791 26, 0x0, End_B0=26 End_B1=26
7973 23:03:54.217023 27, 0x0, End_B0=27 End_B1=27
7974 23:03:54.220785 28, 0x0, End_B0=28 End_B1=28
7975 23:03:54.220872 29, 0x0, End_B0=29 End_B1=29
7976 23:03:54.223769 30, 0x0, End_B0=30 End_B1=30
7977 23:03:54.227196 31, 0x4545, End_B0=30 End_B1=30
7978 23:03:54.230524 Byte0 end_step=30 best_step=27
7979 23:03:54.233797 Byte1 end_step=30 best_step=27
7980 23:03:54.237269 Byte0 TX OE(2T, 0.5T) = (3, 3)
7981 23:03:54.237368 Byte1 TX OE(2T, 0.5T) = (3, 3)
7982 23:03:54.237453
7983 23:03:54.240321
7984 23:03:54.246900 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e1d, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
7985 23:03:54.250391 CH0 RK0: MR19=303, MR18=1E1D
7986 23:03:54.256757 CH0_RK0: MR19=0x303, MR18=0x1E1D, DQSOSC=394, MR23=63, INC=23, DEC=15
7987 23:03:54.256866
7988 23:03:54.260551 ----->DramcWriteLeveling(PI) begin...
7989 23:03:54.260658 ==
7990 23:03:54.263660 Dram Type= 6, Freq= 0, CH_0, rank 1
7991 23:03:54.266755 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7992 23:03:54.266831 ==
7993 23:03:54.270105 Write leveling (Byte 0): 39 => 39
7994 23:03:54.273554 Write leveling (Byte 1): 29 => 29
7995 23:03:54.277349 DramcWriteLeveling(PI) end<-----
7996 23:03:54.277450
7997 23:03:54.277542 ==
7998 23:03:54.280104 Dram Type= 6, Freq= 0, CH_0, rank 1
7999 23:03:54.283649 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8000 23:03:54.283746 ==
8001 23:03:54.286988 [Gating] SW mode calibration
8002 23:03:54.293734 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8003 23:03:54.300141 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8004 23:03:54.303270 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8005 23:03:54.306682 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8006 23:03:54.313442 1 4 8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
8007 23:03:54.316662 1 4 12 | B1->B0 | 2626 3333 | 1 1 | (1 1) (1 1)
8008 23:03:54.320086 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8009 23:03:54.327167 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8010 23:03:54.329854 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8011 23:03:54.333374 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8012 23:03:54.340080 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8013 23:03:54.343459 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8014 23:03:54.346782 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8015 23:03:54.353055 1 5 12 | B1->B0 | 3434 2b2b | 1 0 | (1 0) (0 0)
8016 23:03:54.356561 1 5 16 | B1->B0 | 2727 2323 | 0 0 | (1 0) (1 0)
8017 23:03:54.360082 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8018 23:03:54.366331 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8019 23:03:54.369809 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8020 23:03:54.373343 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8021 23:03:54.380098 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8022 23:03:54.383179 1 6 8 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
8023 23:03:54.386223 1 6 12 | B1->B0 | 3232 4646 | 0 0 | (0 0) (0 0)
8024 23:03:54.393165 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8025 23:03:54.396463 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8026 23:03:54.400068 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8027 23:03:54.406238 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8028 23:03:54.409531 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8029 23:03:54.412868 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8030 23:03:54.419460 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8031 23:03:54.422789 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8032 23:03:54.426183 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8033 23:03:54.429424 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8034 23:03:54.436092 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8035 23:03:54.439182 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8036 23:03:54.442554 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8037 23:03:54.449865 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8038 23:03:54.452948 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8039 23:03:54.455709 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8040 23:03:54.462703 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8041 23:03:54.465768 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8042 23:03:54.469360 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8043 23:03:54.475874 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8044 23:03:54.479282 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8045 23:03:54.482657 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8046 23:03:54.489322 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8047 23:03:54.492273 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8048 23:03:54.495576 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8049 23:03:54.499198 Total UI for P1: 0, mck2ui 16
8050 23:03:54.502429 best dqsien dly found for B0: ( 1, 9, 10)
8051 23:03:54.509049 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8052 23:03:54.509150 Total UI for P1: 0, mck2ui 16
8053 23:03:54.515821 best dqsien dly found for B1: ( 1, 9, 14)
8054 23:03:54.519169 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8055 23:03:54.522605 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8056 23:03:54.522677
8057 23:03:54.525930 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8058 23:03:54.529119 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8059 23:03:54.532401 [Gating] SW calibration Done
8060 23:03:54.532472 ==
8061 23:03:54.536129 Dram Type= 6, Freq= 0, CH_0, rank 1
8062 23:03:54.539351 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8063 23:03:54.539448 ==
8064 23:03:54.542336 RX Vref Scan: 0
8065 23:03:54.542458
8066 23:03:54.542519 RX Vref 0 -> 0, step: 1
8067 23:03:54.542597
8068 23:03:54.546059 RX Delay 0 -> 252, step: 8
8069 23:03:54.548819 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8070 23:03:54.555715 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8071 23:03:54.559092 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8072 23:03:54.562263 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8073 23:03:54.565576 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8074 23:03:54.568983 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8075 23:03:54.576052 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8076 23:03:54.578994 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8077 23:03:54.582038 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8078 23:03:54.585624 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8079 23:03:54.589013 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8080 23:03:54.595434 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8081 23:03:54.598696 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8082 23:03:54.602290 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8083 23:03:54.605246 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8084 23:03:54.608954 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8085 23:03:54.612103 ==
8086 23:03:54.615575 Dram Type= 6, Freq= 0, CH_0, rank 1
8087 23:03:54.619004 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8088 23:03:54.619110 ==
8089 23:03:54.619202 DQS Delay:
8090 23:03:54.622327 DQS0 = 0, DQS1 = 0
8091 23:03:54.622465 DQM Delay:
8092 23:03:54.625650 DQM0 = 136, DQM1 = 125
8093 23:03:54.625744 DQ Delay:
8094 23:03:54.628678 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =131
8095 23:03:54.632527 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8096 23:03:54.635433 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =123
8097 23:03:54.638801 DQ12 =127, DQ13 =135, DQ14 =135, DQ15 =131
8098 23:03:54.638887
8099 23:03:54.638975
8100 23:03:54.639064 ==
8101 23:03:54.642159 Dram Type= 6, Freq= 0, CH_0, rank 1
8102 23:03:54.648544 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8103 23:03:54.648644 ==
8104 23:03:54.648733
8105 23:03:54.648845
8106 23:03:54.648945 TX Vref Scan disable
8107 23:03:54.652223 == TX Byte 0 ==
8108 23:03:54.655693 Update DQ dly =995 (3 ,6, 35) DQ OEN =(3 ,3)
8109 23:03:54.659158 Update DQM dly =995 (3 ,6, 35) DQM OEN =(3 ,3)
8110 23:03:54.662208 == TX Byte 1 ==
8111 23:03:54.665775 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8112 23:03:54.672105 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8113 23:03:54.672206 ==
8114 23:03:54.675540 Dram Type= 6, Freq= 0, CH_0, rank 1
8115 23:03:54.678601 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8116 23:03:54.678676 ==
8117 23:03:54.692116
8118 23:03:54.695451 TX Vref early break, caculate TX vref
8119 23:03:54.698789 TX Vref=16, minBit 3, minWin=23, winSum=391
8120 23:03:54.702128 TX Vref=18, minBit 0, minWin=24, winSum=398
8121 23:03:54.705422 TX Vref=20, minBit 8, minWin=24, winSum=408
8122 23:03:54.709428 TX Vref=22, minBit 0, minWin=25, winSum=418
8123 23:03:54.712190 TX Vref=24, minBit 0, minWin=26, winSum=426
8124 23:03:54.718892 TX Vref=26, minBit 0, minWin=26, winSum=430
8125 23:03:54.722207 TX Vref=28, minBit 0, minWin=26, winSum=430
8126 23:03:54.725932 TX Vref=30, minBit 2, minWin=25, winSum=423
8127 23:03:54.729020 TX Vref=32, minBit 4, minWin=25, winSum=415
8128 23:03:54.732316 TX Vref=34, minBit 2, minWin=24, winSum=407
8129 23:03:54.738898 [TxChooseVref] Worse bit 0, Min win 26, Win sum 430, Final Vref 26
8130 23:03:54.739000
8131 23:03:54.742178 Final TX Range 0 Vref 26
8132 23:03:54.742286
8133 23:03:54.742380 ==
8134 23:03:54.745501 Dram Type= 6, Freq= 0, CH_0, rank 1
8135 23:03:54.748903 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8136 23:03:54.749002 ==
8137 23:03:54.749098
8138 23:03:54.749187
8139 23:03:54.752164 TX Vref Scan disable
8140 23:03:54.758661 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8141 23:03:54.758741 == TX Byte 0 ==
8142 23:03:54.761986 u2DelayCellOfst[0]=13 cells (4 PI)
8143 23:03:54.765550 u2DelayCellOfst[1]=20 cells (6 PI)
8144 23:03:54.768661 u2DelayCellOfst[2]=13 cells (4 PI)
8145 23:03:54.771826 u2DelayCellOfst[3]=13 cells (4 PI)
8146 23:03:54.775544 u2DelayCellOfst[4]=10 cells (3 PI)
8147 23:03:54.778587 u2DelayCellOfst[5]=0 cells (0 PI)
8148 23:03:54.782276 u2DelayCellOfst[6]=16 cells (5 PI)
8149 23:03:54.785135 u2DelayCellOfst[7]=20 cells (6 PI)
8150 23:03:54.788608 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8151 23:03:54.792290 Update DQM dly =995 (3 ,6, 35) DQM OEN =(3 ,3)
8152 23:03:54.795224 == TX Byte 1 ==
8153 23:03:54.795325 u2DelayCellOfst[8]=0 cells (0 PI)
8154 23:03:54.798686 u2DelayCellOfst[9]=3 cells (1 PI)
8155 23:03:54.802319 u2DelayCellOfst[10]=6 cells (2 PI)
8156 23:03:54.805228 u2DelayCellOfst[11]=3 cells (1 PI)
8157 23:03:54.808738 u2DelayCellOfst[12]=13 cells (4 PI)
8158 23:03:54.811997 u2DelayCellOfst[13]=13 cells (4 PI)
8159 23:03:54.814986 u2DelayCellOfst[14]=13 cells (4 PI)
8160 23:03:54.818601 u2DelayCellOfst[15]=10 cells (3 PI)
8161 23:03:54.821988 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8162 23:03:54.828255 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8163 23:03:54.828340 DramC Write-DBI on
8164 23:03:54.828406 ==
8165 23:03:54.832137 Dram Type= 6, Freq= 0, CH_0, rank 1
8166 23:03:54.835240 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8167 23:03:54.838258 ==
8168 23:03:54.838341
8169 23:03:54.838450
8170 23:03:54.838514 TX Vref Scan disable
8171 23:03:54.842091 == TX Byte 0 ==
8172 23:03:54.845303 Update DQM dly =738 (2 ,6, 34) DQM OEN =(3 ,3)
8173 23:03:54.848568 == TX Byte 1 ==
8174 23:03:54.851860 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8175 23:03:54.855130 DramC Write-DBI off
8176 23:03:54.855214
8177 23:03:54.855280 [DATLAT]
8178 23:03:54.855340 Freq=1600, CH0 RK1
8179 23:03:54.855399
8180 23:03:54.858559 DATLAT Default: 0xf
8181 23:03:54.858643 0, 0xFFFF, sum = 0
8182 23:03:54.861897 1, 0xFFFF, sum = 0
8183 23:03:54.865300 2, 0xFFFF, sum = 0
8184 23:03:54.865385 3, 0xFFFF, sum = 0
8185 23:03:54.868651 4, 0xFFFF, sum = 0
8186 23:03:54.868735 5, 0xFFFF, sum = 0
8187 23:03:54.871718 6, 0xFFFF, sum = 0
8188 23:03:54.871802 7, 0xFFFF, sum = 0
8189 23:03:54.875243 8, 0xFFFF, sum = 0
8190 23:03:54.875330 9, 0xFFFF, sum = 0
8191 23:03:54.878437 10, 0xFFFF, sum = 0
8192 23:03:54.878522 11, 0xFFFF, sum = 0
8193 23:03:54.881722 12, 0xFFFF, sum = 0
8194 23:03:54.881806 13, 0xFFFF, sum = 0
8195 23:03:54.885240 14, 0x0, sum = 1
8196 23:03:54.885325 15, 0x0, sum = 2
8197 23:03:54.888708 16, 0x0, sum = 3
8198 23:03:54.888792 17, 0x0, sum = 4
8199 23:03:54.891555 best_step = 15
8200 23:03:54.891638
8201 23:03:54.891703 ==
8202 23:03:54.895059 Dram Type= 6, Freq= 0, CH_0, rank 1
8203 23:03:54.898318 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8204 23:03:54.898410 ==
8205 23:03:54.901583 RX Vref Scan: 0
8206 23:03:54.901665
8207 23:03:54.901732 RX Vref 0 -> 0, step: 1
8208 23:03:54.901794
8209 23:03:54.905293 RX Delay 11 -> 252, step: 4
8210 23:03:54.908314 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8211 23:03:54.915461 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8212 23:03:54.918283 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8213 23:03:54.921763 iDelay=191, Bit 3, Center 128 (79 ~ 178) 100
8214 23:03:54.924899 iDelay=191, Bit 4, Center 134 (83 ~ 186) 104
8215 23:03:54.928198 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8216 23:03:54.935025 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8217 23:03:54.938216 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8218 23:03:54.941693 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8219 23:03:54.945040 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8220 23:03:54.948105 iDelay=191, Bit 10, Center 124 (75 ~ 174) 100
8221 23:03:54.954951 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8222 23:03:54.958503 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8223 23:03:54.961481 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8224 23:03:54.965295 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8225 23:03:54.968561 iDelay=191, Bit 15, Center 130 (79 ~ 182) 104
8226 23:03:54.971723 ==
8227 23:03:54.971806 Dram Type= 6, Freq= 0, CH_0, rank 1
8228 23:03:54.978209 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8229 23:03:54.978318 ==
8230 23:03:54.978466 DQS Delay:
8231 23:03:54.981681 DQS0 = 0, DQS1 = 0
8232 23:03:54.981763 DQM Delay:
8233 23:03:54.985092 DQM0 = 132, DQM1 = 123
8234 23:03:54.985169 DQ Delay:
8235 23:03:54.988423 DQ0 =132, DQ1 =136, DQ2 =130, DQ3 =128
8236 23:03:54.991643 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =138
8237 23:03:54.995071 DQ8 =116, DQ9 =110, DQ10 =124, DQ11 =120
8238 23:03:54.998273 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =130
8239 23:03:54.998391
8240 23:03:54.998460
8241 23:03:54.998522
8242 23:03:55.001745 [DramC_TX_OE_Calibration] TA2
8243 23:03:55.004957 Original DQ_B0 (3 6) =30, OEN = 27
8244 23:03:55.008468 Original DQ_B1 (3 6) =30, OEN = 27
8245 23:03:55.011678 24, 0x0, End_B0=24 End_B1=24
8246 23:03:55.014865 25, 0x0, End_B0=25 End_B1=25
8247 23:03:55.014943 26, 0x0, End_B0=26 End_B1=26
8248 23:03:55.018310 27, 0x0, End_B0=27 End_B1=27
8249 23:03:55.021503 28, 0x0, End_B0=28 End_B1=28
8250 23:03:55.025019 29, 0x0, End_B0=29 End_B1=29
8251 23:03:55.025120 30, 0x0, End_B0=30 End_B1=30
8252 23:03:55.028128 31, 0x4141, End_B0=30 End_B1=30
8253 23:03:55.031343 Byte0 end_step=30 best_step=27
8254 23:03:55.034669 Byte1 end_step=30 best_step=27
8255 23:03:55.037748 Byte0 TX OE(2T, 0.5T) = (3, 3)
8256 23:03:55.041249 Byte1 TX OE(2T, 0.5T) = (3, 3)
8257 23:03:55.041332
8258 23:03:55.041397
8259 23:03:55.048156 [DQSOSCAuto] RK1, (LSB)MR18= 0x2210, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 392 ps
8260 23:03:55.051467 CH0 RK1: MR19=303, MR18=2210
8261 23:03:55.057692 CH0_RK1: MR19=0x303, MR18=0x2210, DQSOSC=392, MR23=63, INC=24, DEC=16
8262 23:03:55.060940 [RxdqsGatingPostProcess] freq 1600
8263 23:03:55.067668 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8264 23:03:55.067752 best DQS0 dly(2T, 0.5T) = (1, 1)
8265 23:03:55.070979 best DQS1 dly(2T, 0.5T) = (1, 1)
8266 23:03:55.074201 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8267 23:03:55.077627 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8268 23:03:55.080788 best DQS0 dly(2T, 0.5T) = (1, 1)
8269 23:03:55.084429 best DQS1 dly(2T, 0.5T) = (1, 1)
8270 23:03:55.087697 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8271 23:03:55.091048 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8272 23:03:55.094096 Pre-setting of DQS Precalculation
8273 23:03:55.097375 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8274 23:03:55.097459 ==
8275 23:03:55.101078 Dram Type= 6, Freq= 0, CH_1, rank 0
8276 23:03:55.107639 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8277 23:03:55.107722 ==
8278 23:03:55.110891 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8279 23:03:55.117524 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8280 23:03:55.120887 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8281 23:03:55.127656 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8282 23:03:55.135291 [CA 0] Center 40 (11~70) winsize 60
8283 23:03:55.138302 [CA 1] Center 40 (10~70) winsize 61
8284 23:03:55.141836 [CA 2] Center 36 (7~66) winsize 60
8285 23:03:55.145082 [CA 3] Center 36 (7~66) winsize 60
8286 23:03:55.148374 [CA 4] Center 36 (6~67) winsize 62
8287 23:03:55.151891 [CA 5] Center 35 (6~65) winsize 60
8288 23:03:55.151974
8289 23:03:55.155010 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8290 23:03:55.155093
8291 23:03:55.158338 [CATrainingPosCal] consider 1 rank data
8292 23:03:55.161891 u2DelayCellTimex100 = 290/100 ps
8293 23:03:55.165191 CA0 delay=40 (11~70),Diff = 5 PI (16 cell)
8294 23:03:55.171831 CA1 delay=40 (10~70),Diff = 5 PI (16 cell)
8295 23:03:55.174901 CA2 delay=36 (7~66),Diff = 1 PI (3 cell)
8296 23:03:55.178247 CA3 delay=36 (7~66),Diff = 1 PI (3 cell)
8297 23:03:55.181726 CA4 delay=36 (6~67),Diff = 1 PI (3 cell)
8298 23:03:55.185125 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
8299 23:03:55.185211
8300 23:03:55.188073 CA PerBit enable=1, Macro0, CA PI delay=35
8301 23:03:55.188159
8302 23:03:55.191920 [CBTSetCACLKResult] CA Dly = 35
8303 23:03:55.194673 CS Dly: 9 (0~40)
8304 23:03:55.198009 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8305 23:03:55.201419 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8306 23:03:55.201505 ==
8307 23:03:55.204779 Dram Type= 6, Freq= 0, CH_1, rank 1
8308 23:03:55.207994 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8309 23:03:55.208103 ==
8310 23:03:55.214852 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8311 23:03:55.218043 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8312 23:03:55.224967 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8313 23:03:55.228056 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8314 23:03:55.238085 [CA 0] Center 42 (13~72) winsize 60
8315 23:03:55.241791 [CA 1] Center 42 (12~72) winsize 61
8316 23:03:55.244701 [CA 2] Center 38 (9~68) winsize 60
8317 23:03:55.248311 [CA 3] Center 37 (8~67) winsize 60
8318 23:03:55.251768 [CA 4] Center 38 (9~68) winsize 60
8319 23:03:55.254741 [CA 5] Center 37 (8~67) winsize 60
8320 23:03:55.254823
8321 23:03:55.257949 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8322 23:03:55.258031
8323 23:03:55.261486 [CATrainingPosCal] consider 2 rank data
8324 23:03:55.264978 u2DelayCellTimex100 = 290/100 ps
8325 23:03:55.268002 CA0 delay=41 (13~70),Diff = 5 PI (16 cell)
8326 23:03:55.275095 CA1 delay=41 (12~70),Diff = 5 PI (16 cell)
8327 23:03:55.277975 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8328 23:03:55.281290 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8329 23:03:55.284477 CA4 delay=38 (9~67),Diff = 2 PI (6 cell)
8330 23:03:55.288270 CA5 delay=36 (8~65),Diff = 0 PI (0 cell)
8331 23:03:55.288351
8332 23:03:55.291247 CA PerBit enable=1, Macro0, CA PI delay=36
8333 23:03:55.291328
8334 23:03:55.294453 [CBTSetCACLKResult] CA Dly = 36
8335 23:03:55.298081 CS Dly: 10 (0~42)
8336 23:03:55.301521 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8337 23:03:55.304882 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8338 23:03:55.304963
8339 23:03:55.308065 ----->DramcWriteLeveling(PI) begin...
8340 23:03:55.308147 ==
8341 23:03:55.311175 Dram Type= 6, Freq= 0, CH_1, rank 0
8342 23:03:55.314997 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8343 23:03:55.317944 ==
8344 23:03:55.318025 Write leveling (Byte 0): 25 => 25
8345 23:03:55.321420 Write leveling (Byte 1): 28 => 28
8346 23:03:55.324652 DramcWriteLeveling(PI) end<-----
8347 23:03:55.324733
8348 23:03:55.324799 ==
8349 23:03:55.327821 Dram Type= 6, Freq= 0, CH_1, rank 0
8350 23:03:55.334412 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8351 23:03:55.334508 ==
8352 23:03:55.334604 [Gating] SW mode calibration
8353 23:03:55.344944 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8354 23:03:55.347907 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8355 23:03:55.351388 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8356 23:03:55.358350 1 4 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
8357 23:03:55.361402 1 4 8 | B1->B0 | 2626 2a2a | 0 1 | (0 0) (1 1)
8358 23:03:55.364475 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8359 23:03:55.371364 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8360 23:03:55.374269 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8361 23:03:55.377687 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8362 23:03:55.384739 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8363 23:03:55.387620 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8364 23:03:55.391089 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8365 23:03:55.397608 1 5 8 | B1->B0 | 2e2e 2929 | 0 0 | (0 0) (1 0)
8366 23:03:55.401366 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8367 23:03:55.404318 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8368 23:03:55.410583 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8369 23:03:55.414169 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8370 23:03:55.417424 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8371 23:03:55.424451 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8372 23:03:55.427280 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8373 23:03:55.430854 1 6 8 | B1->B0 | 3434 3f3f | 0 0 | (0 0) (0 0)
8374 23:03:55.437288 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8375 23:03:55.440940 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8376 23:03:55.444209 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8377 23:03:55.450858 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8378 23:03:55.453979 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8379 23:03:55.457402 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8380 23:03:55.464192 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8381 23:03:55.467372 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8382 23:03:55.471006 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8383 23:03:55.477151 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8384 23:03:55.480537 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8385 23:03:55.483974 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8386 23:03:55.490730 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8387 23:03:55.493742 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8388 23:03:55.496888 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8389 23:03:55.503739 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8390 23:03:55.507120 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8391 23:03:55.510822 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8392 23:03:55.513772 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8393 23:03:55.520624 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8394 23:03:55.523812 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8395 23:03:55.527221 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 23:03:55.533630 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8397 23:03:55.536897 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8398 23:03:55.540260 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8399 23:03:55.543605 Total UI for P1: 0, mck2ui 16
8400 23:03:55.547469 best dqsien dly found for B0: ( 1, 9, 6)
8401 23:03:55.553982 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8402 23:03:55.554065 Total UI for P1: 0, mck2ui 16
8403 23:03:55.560321 best dqsien dly found for B1: ( 1, 9, 10)
8404 23:03:55.563661 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8405 23:03:55.567194 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8406 23:03:55.567277
8407 23:03:55.570808 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8408 23:03:55.573989 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8409 23:03:55.577088 [Gating] SW calibration Done
8410 23:03:55.577171 ==
8411 23:03:55.580718 Dram Type= 6, Freq= 0, CH_1, rank 0
8412 23:03:55.584012 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8413 23:03:55.584095 ==
8414 23:03:55.587051 RX Vref Scan: 0
8415 23:03:55.587134
8416 23:03:55.587200 RX Vref 0 -> 0, step: 1
8417 23:03:55.587262
8418 23:03:55.590705 RX Delay 0 -> 252, step: 8
8419 23:03:55.593623 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8420 23:03:55.600693 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8421 23:03:55.603605 iDelay=200, Bit 2, Center 127 (80 ~ 175) 96
8422 23:03:55.607382 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8423 23:03:55.610808 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8424 23:03:55.613696 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8425 23:03:55.616951 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8426 23:03:55.623702 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8427 23:03:55.626633 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8428 23:03:55.630098 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8429 23:03:55.633500 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8430 23:03:55.637219 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8431 23:03:55.643795 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8432 23:03:55.647108 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8433 23:03:55.650605 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8434 23:03:55.653652 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8435 23:03:55.653753 ==
8436 23:03:55.656842 Dram Type= 6, Freq= 0, CH_1, rank 0
8437 23:03:55.663812 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8438 23:03:55.663921 ==
8439 23:03:55.664025 DQS Delay:
8440 23:03:55.664125 DQS0 = 0, DQS1 = 0
8441 23:03:55.666906 DQM Delay:
8442 23:03:55.667005 DQM0 = 138, DQM1 = 131
8443 23:03:55.670369 DQ Delay:
8444 23:03:55.673563 DQ0 =143, DQ1 =135, DQ2 =127, DQ3 =139
8445 23:03:55.676883 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8446 23:03:55.680334 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =127
8447 23:03:55.683710 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =135
8448 23:03:55.683788
8449 23:03:55.683869
8450 23:03:55.683946 ==
8451 23:03:55.686815 Dram Type= 6, Freq= 0, CH_1, rank 0
8452 23:03:55.690172 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8453 23:03:55.693406 ==
8454 23:03:55.693515
8455 23:03:55.693619
8456 23:03:55.693720 TX Vref Scan disable
8457 23:03:55.696864 == TX Byte 0 ==
8458 23:03:55.700285 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8459 23:03:55.703929 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8460 23:03:55.706640 == TX Byte 1 ==
8461 23:03:55.709962 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8462 23:03:55.713374 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8463 23:03:55.713460 ==
8464 23:03:55.716658 Dram Type= 6, Freq= 0, CH_1, rank 0
8465 23:03:55.723201 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8466 23:03:55.723287 ==
8467 23:03:55.733682
8468 23:03:55.737656 TX Vref early break, caculate TX vref
8469 23:03:55.740592 TX Vref=16, minBit 10, minWin=21, winSum=371
8470 23:03:55.743689 TX Vref=18, minBit 10, minWin=22, winSum=380
8471 23:03:55.747145 TX Vref=20, minBit 10, minWin=23, winSum=393
8472 23:03:55.750782 TX Vref=22, minBit 10, minWin=23, winSum=400
8473 23:03:55.757389 TX Vref=24, minBit 10, minWin=24, winSum=408
8474 23:03:55.760425 TX Vref=26, minBit 10, minWin=25, winSum=418
8475 23:03:55.764016 TX Vref=28, minBit 15, minWin=24, winSum=414
8476 23:03:55.767349 TX Vref=30, minBit 9, minWin=23, winSum=405
8477 23:03:55.770491 TX Vref=32, minBit 9, minWin=23, winSum=393
8478 23:03:55.777095 [TxChooseVref] Worse bit 10, Min win 25, Win sum 418, Final Vref 26
8479 23:03:55.777196
8480 23:03:55.781447 Final TX Range 0 Vref 26
8481 23:03:55.781558
8482 23:03:55.781644 ==
8483 23:03:55.783849 Dram Type= 6, Freq= 0, CH_1, rank 0
8484 23:03:55.787130 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8485 23:03:55.787217 ==
8486 23:03:55.787304
8487 23:03:55.787385
8488 23:03:55.790448 TX Vref Scan disable
8489 23:03:55.797142 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8490 23:03:55.797225 == TX Byte 0 ==
8491 23:03:55.800585 u2DelayCellOfst[0]=16 cells (5 PI)
8492 23:03:55.804148 u2DelayCellOfst[1]=6 cells (2 PI)
8493 23:03:55.807310 u2DelayCellOfst[2]=0 cells (0 PI)
8494 23:03:55.810222 u2DelayCellOfst[3]=3 cells (1 PI)
8495 23:03:55.814116 u2DelayCellOfst[4]=6 cells (2 PI)
8496 23:03:55.817341 u2DelayCellOfst[5]=16 cells (5 PI)
8497 23:03:55.817451 u2DelayCellOfst[6]=16 cells (5 PI)
8498 23:03:55.820845 u2DelayCellOfst[7]=6 cells (2 PI)
8499 23:03:55.827117 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8500 23:03:55.830410 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8501 23:03:55.830505 == TX Byte 1 ==
8502 23:03:55.833980 u2DelayCellOfst[8]=0 cells (0 PI)
8503 23:03:55.837224 u2DelayCellOfst[9]=3 cells (1 PI)
8504 23:03:55.840310 u2DelayCellOfst[10]=10 cells (3 PI)
8505 23:03:55.843719 u2DelayCellOfst[11]=3 cells (1 PI)
8506 23:03:55.846937 u2DelayCellOfst[12]=13 cells (4 PI)
8507 23:03:55.850392 u2DelayCellOfst[13]=16 cells (5 PI)
8508 23:03:55.853939 u2DelayCellOfst[14]=20 cells (6 PI)
8509 23:03:55.856801 u2DelayCellOfst[15]=16 cells (5 PI)
8510 23:03:55.860719 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8511 23:03:55.863665 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8512 23:03:55.867059 DramC Write-DBI on
8513 23:03:55.867158 ==
8514 23:03:55.870190 Dram Type= 6, Freq= 0, CH_1, rank 0
8515 23:03:55.873470 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8516 23:03:55.873583 ==
8517 23:03:55.876867
8518 23:03:55.876963
8519 23:03:55.877063 TX Vref Scan disable
8520 23:03:55.880237 == TX Byte 0 ==
8521 23:03:55.883570 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8522 23:03:55.886656 == TX Byte 1 ==
8523 23:03:55.889997 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8524 23:03:55.890102 DramC Write-DBI off
8525 23:03:55.893439
8526 23:03:55.893542 [DATLAT]
8527 23:03:55.893634 Freq=1600, CH1 RK0
8528 23:03:55.893721
8529 23:03:55.896546 DATLAT Default: 0xf
8530 23:03:55.896622 0, 0xFFFF, sum = 0
8531 23:03:55.899864 1, 0xFFFF, sum = 0
8532 23:03:55.899936 2, 0xFFFF, sum = 0
8533 23:03:55.903327 3, 0xFFFF, sum = 0
8534 23:03:55.903398 4, 0xFFFF, sum = 0
8535 23:03:55.906762 5, 0xFFFF, sum = 0
8536 23:03:55.910079 6, 0xFFFF, sum = 0
8537 23:03:55.910150 7, 0xFFFF, sum = 0
8538 23:03:55.913327 8, 0xFFFF, sum = 0
8539 23:03:55.913425 9, 0xFFFF, sum = 0
8540 23:03:55.916607 10, 0xFFFF, sum = 0
8541 23:03:55.916704 11, 0xFFFF, sum = 0
8542 23:03:55.919748 12, 0xFFFF, sum = 0
8543 23:03:55.919853 13, 0xFFFF, sum = 0
8544 23:03:55.923390 14, 0x0, sum = 1
8545 23:03:55.923461 15, 0x0, sum = 2
8546 23:03:55.926704 16, 0x0, sum = 3
8547 23:03:55.926773 17, 0x0, sum = 4
8548 23:03:55.929900 best_step = 15
8549 23:03:55.929993
8550 23:03:55.930091 ==
8551 23:03:55.933472 Dram Type= 6, Freq= 0, CH_1, rank 0
8552 23:03:55.936883 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8553 23:03:55.936980 ==
8554 23:03:55.937079 RX Vref Scan: 1
8555 23:03:55.939824
8556 23:03:55.939900 Set Vref Range= 24 -> 127
8557 23:03:55.939992
8558 23:03:55.942923 RX Vref 24 -> 127, step: 1
8559 23:03:55.943029
8560 23:03:55.946305 RX Delay 19 -> 252, step: 4
8561 23:03:55.946435
8562 23:03:55.949603 Set Vref, RX VrefLevel [Byte0]: 24
8563 23:03:55.952755 [Byte1]: 24
8564 23:03:55.952860
8565 23:03:55.956590 Set Vref, RX VrefLevel [Byte0]: 25
8566 23:03:55.959538 [Byte1]: 25
8567 23:03:55.959641
8568 23:03:55.963120 Set Vref, RX VrefLevel [Byte0]: 26
8569 23:03:55.966052 [Byte1]: 26
8570 23:03:55.970146
8571 23:03:55.970243 Set Vref, RX VrefLevel [Byte0]: 27
8572 23:03:55.973484 [Byte1]: 27
8573 23:03:55.977687
8574 23:03:55.977792 Set Vref, RX VrefLevel [Byte0]: 28
8575 23:03:55.980970 [Byte1]: 28
8576 23:03:55.985710
8577 23:03:55.985816 Set Vref, RX VrefLevel [Byte0]: 29
8578 23:03:55.988911 [Byte1]: 29
8579 23:03:55.992816
8580 23:03:55.992912 Set Vref, RX VrefLevel [Byte0]: 30
8581 23:03:55.996170 [Byte1]: 30
8582 23:03:56.000389
8583 23:03:56.000485 Set Vref, RX VrefLevel [Byte0]: 31
8584 23:03:56.003863 [Byte1]: 31
8585 23:03:56.007924
8586 23:03:56.007992 Set Vref, RX VrefLevel [Byte0]: 32
8587 23:03:56.011437 [Byte1]: 32
8588 23:03:56.015726
8589 23:03:56.015797 Set Vref, RX VrefLevel [Byte0]: 33
8590 23:03:56.018668 [Byte1]: 33
8591 23:03:56.023163
8592 23:03:56.023231 Set Vref, RX VrefLevel [Byte0]: 34
8593 23:03:56.026347 [Byte1]: 34
8594 23:03:56.030653
8595 23:03:56.030749 Set Vref, RX VrefLevel [Byte0]: 35
8596 23:03:56.033916 [Byte1]: 35
8597 23:03:56.038472
8598 23:03:56.038544 Set Vref, RX VrefLevel [Byte0]: 36
8599 23:03:56.041547 [Byte1]: 36
8600 23:03:56.045714
8601 23:03:56.045813 Set Vref, RX VrefLevel [Byte0]: 37
8602 23:03:56.049165 [Byte1]: 37
8603 23:03:56.053233
8604 23:03:56.053336 Set Vref, RX VrefLevel [Byte0]: 38
8605 23:03:56.056647 [Byte1]: 38
8606 23:03:56.060893
8607 23:03:56.060997 Set Vref, RX VrefLevel [Byte0]: 39
8608 23:03:56.064166 [Byte1]: 39
8609 23:03:56.068434
8610 23:03:56.068538 Set Vref, RX VrefLevel [Byte0]: 40
8611 23:03:56.071684 [Byte1]: 40
8612 23:03:56.076061
8613 23:03:56.076164 Set Vref, RX VrefLevel [Byte0]: 41
8614 23:03:56.079496 [Byte1]: 41
8615 23:03:56.083654
8616 23:03:56.083757 Set Vref, RX VrefLevel [Byte0]: 42
8617 23:03:56.087065 [Byte1]: 42
8618 23:03:56.091298
8619 23:03:56.091398 Set Vref, RX VrefLevel [Byte0]: 43
8620 23:03:56.094638 [Byte1]: 43
8621 23:03:56.098805
8622 23:03:56.098903 Set Vref, RX VrefLevel [Byte0]: 44
8623 23:03:56.101973 [Byte1]: 44
8624 23:03:56.106456
8625 23:03:56.106526 Set Vref, RX VrefLevel [Byte0]: 45
8626 23:03:56.109885 [Byte1]: 45
8627 23:03:56.113950
8628 23:03:56.114047 Set Vref, RX VrefLevel [Byte0]: 46
8629 23:03:56.117186 [Byte1]: 46
8630 23:03:56.121452
8631 23:03:56.121547 Set Vref, RX VrefLevel [Byte0]: 47
8632 23:03:56.125056 [Byte1]: 47
8633 23:03:56.129085
8634 23:03:56.129184 Set Vref, RX VrefLevel [Byte0]: 48
8635 23:03:56.132654 [Byte1]: 48
8636 23:03:56.136893
8637 23:03:56.136988 Set Vref, RX VrefLevel [Byte0]: 49
8638 23:03:56.140009 [Byte1]: 49
8639 23:03:56.144134
8640 23:03:56.144239 Set Vref, RX VrefLevel [Byte0]: 50
8641 23:03:56.147568 [Byte1]: 50
8642 23:03:56.151974
8643 23:03:56.152057 Set Vref, RX VrefLevel [Byte0]: 51
8644 23:03:56.155034 [Byte1]: 51
8645 23:03:56.159392
8646 23:03:56.159498 Set Vref, RX VrefLevel [Byte0]: 52
8647 23:03:56.162634 [Byte1]: 52
8648 23:03:56.167013
8649 23:03:56.167095 Set Vref, RX VrefLevel [Byte0]: 53
8650 23:03:56.170706 [Byte1]: 53
8651 23:03:56.174750
8652 23:03:56.174833 Set Vref, RX VrefLevel [Byte0]: 54
8653 23:03:56.177858 [Byte1]: 54
8654 23:03:56.182310
8655 23:03:56.182453 Set Vref, RX VrefLevel [Byte0]: 55
8656 23:03:56.185481 [Byte1]: 55
8657 23:03:56.189530
8658 23:03:56.189612 Set Vref, RX VrefLevel [Byte0]: 56
8659 23:03:56.193019 [Byte1]: 56
8660 23:03:56.197192
8661 23:03:56.197274 Set Vref, RX VrefLevel [Byte0]: 57
8662 23:03:56.200643 [Byte1]: 57
8663 23:03:56.204970
8664 23:03:56.205052 Set Vref, RX VrefLevel [Byte0]: 58
8665 23:03:56.208036 [Byte1]: 58
8666 23:03:56.212822
8667 23:03:56.212905 Set Vref, RX VrefLevel [Byte0]: 59
8668 23:03:56.216043 [Byte1]: 59
8669 23:03:56.219714
8670 23:03:56.223623 Set Vref, RX VrefLevel [Byte0]: 60
8671 23:03:56.226321 [Byte1]: 60
8672 23:03:56.226409
8673 23:03:56.229873 Set Vref, RX VrefLevel [Byte0]: 61
8674 23:03:56.233137 [Byte1]: 61
8675 23:03:56.233220
8676 23:03:56.236669 Set Vref, RX VrefLevel [Byte0]: 62
8677 23:03:56.240062 [Byte1]: 62
8678 23:03:56.240145
8679 23:03:56.243152 Set Vref, RX VrefLevel [Byte0]: 63
8680 23:03:56.246480 [Byte1]: 63
8681 23:03:56.250112
8682 23:03:56.250195 Set Vref, RX VrefLevel [Byte0]: 64
8683 23:03:56.253457 [Byte1]: 64
8684 23:03:56.257816
8685 23:03:56.257898 Set Vref, RX VrefLevel [Byte0]: 65
8686 23:03:56.261331 [Byte1]: 65
8687 23:03:56.265864
8688 23:03:56.265947 Set Vref, RX VrefLevel [Byte0]: 66
8689 23:03:56.268653 [Byte1]: 66
8690 23:03:56.273134
8691 23:03:56.273216 Set Vref, RX VrefLevel [Byte0]: 67
8692 23:03:56.276430 [Byte1]: 67
8693 23:03:56.280716
8694 23:03:56.280841 Set Vref, RX VrefLevel [Byte0]: 68
8695 23:03:56.283977 [Byte1]: 68
8696 23:03:56.288078
8697 23:03:56.288186 Set Vref, RX VrefLevel [Byte0]: 69
8698 23:03:56.291848 [Byte1]: 69
8699 23:03:56.295714
8700 23:03:56.295789 Set Vref, RX VrefLevel [Byte0]: 70
8701 23:03:56.298774 [Byte1]: 70
8702 23:03:56.303455
8703 23:03:56.303529 Set Vref, RX VrefLevel [Byte0]: 71
8704 23:03:56.306481 [Byte1]: 71
8705 23:03:56.310880
8706 23:03:56.310949 Set Vref, RX VrefLevel [Byte0]: 72
8707 23:03:56.313991 [Byte1]: 72
8708 23:03:56.318649
8709 23:03:56.318731 Set Vref, RX VrefLevel [Byte0]: 73
8710 23:03:56.321737 [Byte1]: 73
8711 23:03:56.326074
8712 23:03:56.326156 Final RX Vref Byte 0 = 53 to rank0
8713 23:03:56.329450 Final RX Vref Byte 1 = 63 to rank0
8714 23:03:56.332733 Final RX Vref Byte 0 = 53 to rank1
8715 23:03:56.335991 Final RX Vref Byte 1 = 63 to rank1==
8716 23:03:56.339517 Dram Type= 6, Freq= 0, CH_1, rank 0
8717 23:03:56.346060 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8718 23:03:56.346143 ==
8719 23:03:56.346209 DQS Delay:
8720 23:03:56.346270 DQS0 = 0, DQS1 = 0
8721 23:03:56.349350 DQM Delay:
8722 23:03:56.349432 DQM0 = 133, DQM1 = 129
8723 23:03:56.353027 DQ Delay:
8724 23:03:56.355909 DQ0 =136, DQ1 =130, DQ2 =122, DQ3 =132
8725 23:03:56.359354 DQ4 =132, DQ5 =144, DQ6 =144, DQ7 =130
8726 23:03:56.362688 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =122
8727 23:03:56.366289 DQ12 =140, DQ13 =134, DQ14 =136, DQ15 =136
8728 23:03:56.366374
8729 23:03:56.366475
8730 23:03:56.366537
8731 23:03:56.369171 [DramC_TX_OE_Calibration] TA2
8732 23:03:56.372739 Original DQ_B0 (3 6) =30, OEN = 27
8733 23:03:56.376162 Original DQ_B1 (3 6) =30, OEN = 27
8734 23:03:56.379321 24, 0x0, End_B0=24 End_B1=24
8735 23:03:56.379434 25, 0x0, End_B0=25 End_B1=25
8736 23:03:56.382928 26, 0x0, End_B0=26 End_B1=26
8737 23:03:56.385666 27, 0x0, End_B0=27 End_B1=27
8738 23:03:56.389213 28, 0x0, End_B0=28 End_B1=28
8739 23:03:56.389300 29, 0x0, End_B0=29 End_B1=29
8740 23:03:56.392446 30, 0x0, End_B0=30 End_B1=30
8741 23:03:56.395858 31, 0x4141, End_B0=30 End_B1=30
8742 23:03:56.399348 Byte0 end_step=30 best_step=27
8743 23:03:56.402171 Byte1 end_step=30 best_step=27
8744 23:03:56.405913 Byte0 TX OE(2T, 0.5T) = (3, 3)
8745 23:03:56.406015 Byte1 TX OE(2T, 0.5T) = (3, 3)
8746 23:03:56.409124
8747 23:03:56.409210
8748 23:03:56.415896 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a28, (MSB)MR19= 0x303, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
8749 23:03:56.419229 CH1 RK0: MR19=303, MR18=1A28
8750 23:03:56.425843 CH1_RK0: MR19=0x303, MR18=0x1A28, DQSOSC=389, MR23=63, INC=24, DEC=16
8751 23:03:56.425928
8752 23:03:56.428893 ----->DramcWriteLeveling(PI) begin...
8753 23:03:56.428979 ==
8754 23:03:56.432444 Dram Type= 6, Freq= 0, CH_1, rank 1
8755 23:03:56.436033 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8756 23:03:56.436118 ==
8757 23:03:56.439010 Write leveling (Byte 0): 24 => 24
8758 23:03:56.442694 Write leveling (Byte 1): 29 => 29
8759 23:03:56.445907 DramcWriteLeveling(PI) end<-----
8760 23:03:56.445991
8761 23:03:56.446074 ==
8762 23:03:56.448803 Dram Type= 6, Freq= 0, CH_1, rank 1
8763 23:03:56.452082 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8764 23:03:56.452166 ==
8765 23:03:56.455703 [Gating] SW mode calibration
8766 23:03:56.462081 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8767 23:03:56.468989 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8768 23:03:56.472265 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8769 23:03:56.475424 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8770 23:03:56.481941 1 4 8 | B1->B0 | 3232 2323 | 1 0 | (1 1) (0 0)
8771 23:03:56.485750 1 4 12 | B1->B0 | 3434 2929 | 1 1 | (1 1) (1 1)
8772 23:03:56.488912 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8773 23:03:56.495369 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8774 23:03:56.499271 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8775 23:03:56.502347 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8776 23:03:56.508854 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8777 23:03:56.511989 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8778 23:03:56.515288 1 5 8 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 0)
8779 23:03:56.522204 1 5 12 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
8780 23:03:56.525604 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8781 23:03:56.528736 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8782 23:03:56.535015 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8783 23:03:56.538975 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8784 23:03:56.542212 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8785 23:03:56.548754 1 6 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8786 23:03:56.552549 1 6 8 | B1->B0 | 4444 2424 | 0 0 | (0 0) (0 0)
8787 23:03:56.555241 1 6 12 | B1->B0 | 4646 3737 | 0 1 | (0 0) (0 0)
8788 23:03:56.561890 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8789 23:03:56.565388 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8790 23:03:56.568822 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8791 23:03:56.574896 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8792 23:03:56.578717 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8793 23:03:56.581757 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8794 23:03:56.585371 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8795 23:03:56.591777 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8796 23:03:56.595215 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8797 23:03:56.598514 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8798 23:03:56.604889 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8799 23:03:56.608472 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8800 23:03:56.612063 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8801 23:03:56.618616 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8802 23:03:56.621819 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8803 23:03:56.624797 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8804 23:03:56.631729 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8805 23:03:56.635013 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8806 23:03:56.638134 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8807 23:03:56.644756 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 23:03:56.648002 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 23:03:56.651504 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8810 23:03:56.658159 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8811 23:03:56.661650 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8812 23:03:56.665252 Total UI for P1: 0, mck2ui 16
8813 23:03:56.668099 best dqsien dly found for B0: ( 1, 9, 8)
8814 23:03:56.671296 Total UI for P1: 0, mck2ui 16
8815 23:03:56.674631 best dqsien dly found for B1: ( 1, 9, 8)
8816 23:03:56.677958 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8817 23:03:56.681214 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8818 23:03:56.681323
8819 23:03:56.684417 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8820 23:03:56.688076 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8821 23:03:56.691776 [Gating] SW calibration Done
8822 23:03:56.691862 ==
8823 23:03:56.694687 Dram Type= 6, Freq= 0, CH_1, rank 1
8824 23:03:56.698152 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8825 23:03:56.698234 ==
8826 23:03:56.701349 RX Vref Scan: 0
8827 23:03:56.701457
8828 23:03:56.704608 RX Vref 0 -> 0, step: 1
8829 23:03:56.704715
8830 23:03:56.704809 RX Delay 0 -> 252, step: 8
8831 23:03:56.711624 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8832 23:03:56.714644 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8833 23:03:56.717826 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8834 23:03:56.721403 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8835 23:03:56.724545 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8836 23:03:56.730887 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8837 23:03:56.734325 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8838 23:03:56.737996 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
8839 23:03:56.740965 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8840 23:03:56.744460 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8841 23:03:56.748243 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8842 23:03:56.754410 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8843 23:03:56.757909 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8844 23:03:56.761172 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8845 23:03:56.764305 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8846 23:03:56.771463 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8847 23:03:56.771554 ==
8848 23:03:56.774721 Dram Type= 6, Freq= 0, CH_1, rank 1
8849 23:03:56.777838 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8850 23:03:56.777922 ==
8851 23:03:56.777996 DQS Delay:
8852 23:03:56.780990 DQS0 = 0, DQS1 = 0
8853 23:03:56.781065 DQM Delay:
8854 23:03:56.784485 DQM0 = 137, DQM1 = 131
8855 23:03:56.784560 DQ Delay:
8856 23:03:56.787728 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =135
8857 23:03:56.791127 DQ4 =135, DQ5 =147, DQ6 =143, DQ7 =139
8858 23:03:56.794736 DQ8 =115, DQ9 =119, DQ10 =135, DQ11 =127
8859 23:03:56.798269 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =143
8860 23:03:56.798354
8861 23:03:56.798443
8862 23:03:56.801036 ==
8863 23:03:56.804535 Dram Type= 6, Freq= 0, CH_1, rank 1
8864 23:03:56.807851 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8865 23:03:56.807936 ==
8866 23:03:56.808003
8867 23:03:56.808065
8868 23:03:56.810915 TX Vref Scan disable
8869 23:03:56.810999 == TX Byte 0 ==
8870 23:03:56.814405 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8871 23:03:56.820955 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8872 23:03:56.821066 == TX Byte 1 ==
8873 23:03:56.824204 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8874 23:03:56.831421 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8875 23:03:56.831518 ==
8876 23:03:56.834132 Dram Type= 6, Freq= 0, CH_1, rank 1
8877 23:03:56.837584 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8878 23:03:56.837660 ==
8879 23:03:56.850813
8880 23:03:56.853846 TX Vref early break, caculate TX vref
8881 23:03:56.857677 TX Vref=16, minBit 10, minWin=22, winSum=381
8882 23:03:56.860788 TX Vref=18, minBit 9, minWin=21, winSum=390
8883 23:03:56.863842 TX Vref=20, minBit 10, minWin=22, winSum=393
8884 23:03:56.867684 TX Vref=22, minBit 9, minWin=23, winSum=405
8885 23:03:56.870610 TX Vref=24, minBit 11, minWin=24, winSum=413
8886 23:03:56.877076 TX Vref=26, minBit 11, minWin=24, winSum=417
8887 23:03:56.880866 TX Vref=28, minBit 9, minWin=24, winSum=413
8888 23:03:56.883809 TX Vref=30, minBit 8, minWin=24, winSum=408
8889 23:03:56.887417 TX Vref=32, minBit 10, minWin=23, winSum=400
8890 23:03:56.890486 TX Vref=34, minBit 8, minWin=22, winSum=392
8891 23:03:56.897166 [TxChooseVref] Worse bit 11, Min win 24, Win sum 417, Final Vref 26
8892 23:03:56.897251
8893 23:03:56.900636 Final TX Range 0 Vref 26
8894 23:03:56.900720
8895 23:03:56.900787 ==
8896 23:03:56.903944 Dram Type= 6, Freq= 0, CH_1, rank 1
8897 23:03:56.907109 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8898 23:03:56.907194 ==
8899 23:03:56.907260
8900 23:03:56.907320
8901 23:03:56.910255 TX Vref Scan disable
8902 23:03:56.917444 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8903 23:03:56.917527 == TX Byte 0 ==
8904 23:03:56.920442 u2DelayCellOfst[0]=13 cells (4 PI)
8905 23:03:56.923981 u2DelayCellOfst[1]=10 cells (3 PI)
8906 23:03:56.927013 u2DelayCellOfst[2]=0 cells (0 PI)
8907 23:03:56.930340 u2DelayCellOfst[3]=3 cells (1 PI)
8908 23:03:56.933995 u2DelayCellOfst[4]=6 cells (2 PI)
8909 23:03:56.937075 u2DelayCellOfst[5]=16 cells (5 PI)
8910 23:03:56.940410 u2DelayCellOfst[6]=16 cells (5 PI)
8911 23:03:56.943693 u2DelayCellOfst[7]=3 cells (1 PI)
8912 23:03:56.947457 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8913 23:03:56.950496 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8914 23:03:56.953668 == TX Byte 1 ==
8915 23:03:56.956856 u2DelayCellOfst[8]=0 cells (0 PI)
8916 23:03:56.956939 u2DelayCellOfst[9]=3 cells (1 PI)
8917 23:03:56.960398 u2DelayCellOfst[10]=6 cells (2 PI)
8918 23:03:56.963674 u2DelayCellOfst[11]=3 cells (1 PI)
8919 23:03:56.966894 u2DelayCellOfst[12]=10 cells (3 PI)
8920 23:03:56.970558 u2DelayCellOfst[13]=16 cells (5 PI)
8921 23:03:56.973414 u2DelayCellOfst[14]=16 cells (5 PI)
8922 23:03:56.976665 u2DelayCellOfst[15]=16 cells (5 PI)
8923 23:03:56.980208 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8924 23:03:56.986645 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8925 23:03:56.986729 DramC Write-DBI on
8926 23:03:56.986794 ==
8927 23:03:56.990096 Dram Type= 6, Freq= 0, CH_1, rank 1
8928 23:03:56.997220 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8929 23:03:56.997302 ==
8930 23:03:56.997368
8931 23:03:56.997427
8932 23:03:56.997484 TX Vref Scan disable
8933 23:03:57.000567 == TX Byte 0 ==
8934 23:03:57.003956 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8935 23:03:57.007027 == TX Byte 1 ==
8936 23:03:57.010644 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8937 23:03:57.013656 DramC Write-DBI off
8938 23:03:57.013737
8939 23:03:57.013802 [DATLAT]
8940 23:03:57.013862 Freq=1600, CH1 RK1
8941 23:03:57.013921
8942 23:03:57.017087 DATLAT Default: 0xf
8943 23:03:57.017169 0, 0xFFFF, sum = 0
8944 23:03:57.020616 1, 0xFFFF, sum = 0
8945 23:03:57.023695 2, 0xFFFF, sum = 0
8946 23:03:57.023778 3, 0xFFFF, sum = 0
8947 23:03:57.026776 4, 0xFFFF, sum = 0
8948 23:03:57.026859 5, 0xFFFF, sum = 0
8949 23:03:57.030640 6, 0xFFFF, sum = 0
8950 23:03:57.030724 7, 0xFFFF, sum = 0
8951 23:03:57.033576 8, 0xFFFF, sum = 0
8952 23:03:57.033659 9, 0xFFFF, sum = 0
8953 23:03:57.037418 10, 0xFFFF, sum = 0
8954 23:03:57.037501 11, 0xFFFF, sum = 0
8955 23:03:57.040732 12, 0xFFFF, sum = 0
8956 23:03:57.040815 13, 0xFFFF, sum = 0
8957 23:03:57.044036 14, 0x0, sum = 1
8958 23:03:57.044120 15, 0x0, sum = 2
8959 23:03:57.047363 16, 0x0, sum = 3
8960 23:03:57.047447 17, 0x0, sum = 4
8961 23:03:57.050230 best_step = 15
8962 23:03:57.050313
8963 23:03:57.050377 ==
8964 23:03:57.053449 Dram Type= 6, Freq= 0, CH_1, rank 1
8965 23:03:57.057349 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8966 23:03:57.057432 ==
8967 23:03:57.057498 RX Vref Scan: 0
8968 23:03:57.060471
8969 23:03:57.060552 RX Vref 0 -> 0, step: 1
8970 23:03:57.060618
8971 23:03:57.063616 RX Delay 19 -> 252, step: 4
8972 23:03:57.067484 iDelay=195, Bit 0, Center 138 (95 ~ 182) 88
8973 23:03:57.073544 iDelay=195, Bit 1, Center 130 (87 ~ 174) 88
8974 23:03:57.076936 iDelay=195, Bit 2, Center 120 (75 ~ 166) 92
8975 23:03:57.080190 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8976 23:03:57.084198 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
8977 23:03:57.086720 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8978 23:03:57.090135 iDelay=195, Bit 6, Center 142 (95 ~ 190) 96
8979 23:03:57.097154 iDelay=195, Bit 7, Center 130 (83 ~ 178) 96
8980 23:03:57.100101 iDelay=195, Bit 8, Center 114 (67 ~ 162) 96
8981 23:03:57.103680 iDelay=195, Bit 9, Center 120 (71 ~ 170) 100
8982 23:03:57.106860 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
8983 23:03:57.110178 iDelay=195, Bit 11, Center 126 (75 ~ 178) 104
8984 23:03:57.116679 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
8985 23:03:57.120023 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8986 23:03:57.123744 iDelay=195, Bit 14, Center 138 (91 ~ 186) 96
8987 23:03:57.126846 iDelay=195, Bit 15, Center 140 (87 ~ 194) 108
8988 23:03:57.126929 ==
8989 23:03:57.130063 Dram Type= 6, Freq= 0, CH_1, rank 1
8990 23:03:57.133439 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8991 23:03:57.136743 ==
8992 23:03:57.136826 DQS Delay:
8993 23:03:57.136891 DQS0 = 0, DQS1 = 0
8994 23:03:57.140175 DQM Delay:
8995 23:03:57.140257 DQM0 = 133, DQM1 = 130
8996 23:03:57.143390 DQ Delay:
8997 23:03:57.146676 DQ0 =138, DQ1 =130, DQ2 =120, DQ3 =130
8998 23:03:57.150238 DQ4 =134, DQ5 =146, DQ6 =142, DQ7 =130
8999 23:03:57.153738 DQ8 =114, DQ9 =120, DQ10 =130, DQ11 =126
9000 23:03:57.156921 DQ12 =138, DQ13 =138, DQ14 =138, DQ15 =140
9001 23:03:57.157003
9002 23:03:57.157067
9003 23:03:57.157127
9004 23:03:57.160225 [DramC_TX_OE_Calibration] TA2
9005 23:03:57.163395 Original DQ_B0 (3 6) =30, OEN = 27
9006 23:03:57.166893 Original DQ_B1 (3 6) =30, OEN = 27
9007 23:03:57.170113 24, 0x0, End_B0=24 End_B1=24
9008 23:03:57.170197 25, 0x0, End_B0=25 End_B1=25
9009 23:03:57.173047 26, 0x0, End_B0=26 End_B1=26
9010 23:03:57.176963 27, 0x0, End_B0=27 End_B1=27
9011 23:03:57.179984 28, 0x0, End_B0=28 End_B1=28
9012 23:03:57.180068 29, 0x0, End_B0=29 End_B1=29
9013 23:03:57.183400 30, 0x0, End_B0=30 End_B1=30
9014 23:03:57.186526 31, 0x4141, End_B0=30 End_B1=30
9015 23:03:57.189658 Byte0 end_step=30 best_step=27
9016 23:03:57.193179 Byte1 end_step=30 best_step=27
9017 23:03:57.196158 Byte0 TX OE(2T, 0.5T) = (3, 3)
9018 23:03:57.199748 Byte1 TX OE(2T, 0.5T) = (3, 3)
9019 23:03:57.199830
9020 23:03:57.199896
9021 23:03:57.206272 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e08, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
9022 23:03:57.209547 CH1 RK1: MR19=303, MR18=1E08
9023 23:03:57.215977 CH1_RK1: MR19=0x303, MR18=0x1E08, DQSOSC=394, MR23=63, INC=23, DEC=15
9024 23:03:57.219442 [RxdqsGatingPostProcess] freq 1600
9025 23:03:57.222636 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9026 23:03:57.225934 best DQS0 dly(2T, 0.5T) = (1, 1)
9027 23:03:57.229719 best DQS1 dly(2T, 0.5T) = (1, 1)
9028 23:03:57.232728 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9029 23:03:57.236077 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9030 23:03:57.239182 best DQS0 dly(2T, 0.5T) = (1, 1)
9031 23:03:57.242845 best DQS1 dly(2T, 0.5T) = (1, 1)
9032 23:03:57.245974 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9033 23:03:57.249329 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9034 23:03:57.252977 Pre-setting of DQS Precalculation
9035 23:03:57.255844 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9036 23:03:57.262528 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9037 23:03:57.269390 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9038 23:03:57.272742
9039 23:03:57.272826
9040 23:03:57.272911 [Calibration Summary] 3200 Mbps
9041 23:03:57.276033 CH 0, Rank 0
9042 23:03:57.276118 SW Impedance : PASS
9043 23:03:57.279291 DUTY Scan : NO K
9044 23:03:57.282974 ZQ Calibration : PASS
9045 23:03:57.283076 Jitter Meter : NO K
9046 23:03:57.286024 CBT Training : PASS
9047 23:03:57.289522 Write leveling : PASS
9048 23:03:57.289605 RX DQS gating : PASS
9049 23:03:57.292553 RX DQ/DQS(RDDQC) : PASS
9050 23:03:57.296091 TX DQ/DQS : PASS
9051 23:03:57.296174 RX DATLAT : PASS
9052 23:03:57.299322 RX DQ/DQS(Engine): PASS
9053 23:03:57.302749 TX OE : PASS
9054 23:03:57.302833 All Pass.
9055 23:03:57.302898
9056 23:03:57.302973 CH 0, Rank 1
9057 23:03:57.305992 SW Impedance : PASS
9058 23:03:57.306074 DUTY Scan : NO K
9059 23:03:57.309274 ZQ Calibration : PASS
9060 23:03:57.312789 Jitter Meter : NO K
9061 23:03:57.312872 CBT Training : PASS
9062 23:03:57.316062 Write leveling : PASS
9063 23:03:57.319469 RX DQS gating : PASS
9064 23:03:57.319551 RX DQ/DQS(RDDQC) : PASS
9065 23:03:57.322582 TX DQ/DQS : PASS
9066 23:03:57.326204 RX DATLAT : PASS
9067 23:03:57.326286 RX DQ/DQS(Engine): PASS
9068 23:03:57.329319 TX OE : PASS
9069 23:03:57.329402 All Pass.
9070 23:03:57.329467
9071 23:03:57.332794 CH 1, Rank 0
9072 23:03:57.332878 SW Impedance : PASS
9073 23:03:57.335941 DUTY Scan : NO K
9074 23:03:57.339088 ZQ Calibration : PASS
9075 23:03:57.339173 Jitter Meter : NO K
9076 23:03:57.342714 CBT Training : PASS
9077 23:03:57.345987 Write leveling : PASS
9078 23:03:57.346071 RX DQS gating : PASS
9079 23:03:57.349109 RX DQ/DQS(RDDQC) : PASS
9080 23:03:57.352884 TX DQ/DQS : PASS
9081 23:03:57.352968 RX DATLAT : PASS
9082 23:03:57.355959 RX DQ/DQS(Engine): PASS
9083 23:03:57.356042 TX OE : PASS
9084 23:03:57.359204 All Pass.
9085 23:03:57.359287
9086 23:03:57.359353 CH 1, Rank 1
9087 23:03:57.362710 SW Impedance : PASS
9088 23:03:57.362793 DUTY Scan : NO K
9089 23:03:57.366062 ZQ Calibration : PASS
9090 23:03:57.369558 Jitter Meter : NO K
9091 23:03:57.369642 CBT Training : PASS
9092 23:03:57.372441 Write leveling : PASS
9093 23:03:57.376164 RX DQS gating : PASS
9094 23:03:57.376247 RX DQ/DQS(RDDQC) : PASS
9095 23:03:57.379198 TX DQ/DQS : PASS
9096 23:03:57.382700 RX DATLAT : PASS
9097 23:03:57.382783 RX DQ/DQS(Engine): PASS
9098 23:03:57.385970 TX OE : PASS
9099 23:03:57.386053 All Pass.
9100 23:03:57.386119
9101 23:03:57.389404 DramC Write-DBI on
9102 23:03:57.392724 PER_BANK_REFRESH: Hybrid Mode
9103 23:03:57.392808 TX_TRACKING: ON
9104 23:03:57.402547 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9105 23:03:57.409380 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9106 23:03:57.416289 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9107 23:03:57.419508 [FAST_K] Save calibration result to emmc
9108 23:03:57.422808 sync common calibartion params.
9109 23:03:57.426181 sync cbt_mode0:1, 1:1
9110 23:03:57.429309 dram_init: ddr_geometry: 2
9111 23:03:57.429392 dram_init: ddr_geometry: 2
9112 23:03:57.432404 dram_init: ddr_geometry: 2
9113 23:03:57.435853 0:dram_rank_size:100000000
9114 23:03:57.435938 1:dram_rank_size:100000000
9115 23:03:57.442542 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9116 23:03:57.445589 DFS_SHUFFLE_HW_MODE: ON
9117 23:03:57.448981 dramc_set_vcore_voltage set vcore to 725000
9118 23:03:57.452403 Read voltage for 1600, 0
9119 23:03:57.452490 Vio18 = 0
9120 23:03:57.452588 Vcore = 725000
9121 23:03:57.455880 Vdram = 0
9122 23:03:57.455962 Vddq = 0
9123 23:03:57.456028 Vmddr = 0
9124 23:03:57.458939 switch to 3200 Mbps bootup
9125 23:03:57.459021 [DramcRunTimeConfig]
9126 23:03:57.462659 PHYPLL
9127 23:03:57.462742 DPM_CONTROL_AFTERK: ON
9128 23:03:57.466015 PER_BANK_REFRESH: ON
9129 23:03:57.469465 REFRESH_OVERHEAD_REDUCTION: ON
9130 23:03:57.469548 CMD_PICG_NEW_MODE: OFF
9131 23:03:57.472231 XRTWTW_NEW_MODE: ON
9132 23:03:57.472340 XRTRTR_NEW_MODE: ON
9133 23:03:57.475745 TX_TRACKING: ON
9134 23:03:57.475829 RDSEL_TRACKING: OFF
9135 23:03:57.478991 DQS Precalculation for DVFS: ON
9136 23:03:57.482394 RX_TRACKING: OFF
9137 23:03:57.482490 HW_GATING DBG: ON
9138 23:03:57.485855 ZQCS_ENABLE_LP4: ON
9139 23:03:57.485937 RX_PICG_NEW_MODE: ON
9140 23:03:57.489169 TX_PICG_NEW_MODE: ON
9141 23:03:57.489251 ENABLE_RX_DCM_DPHY: ON
9142 23:03:57.492734 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9143 23:03:57.495959 DUMMY_READ_FOR_TRACKING: OFF
9144 23:03:57.498822 !!! SPM_CONTROL_AFTERK: OFF
9145 23:03:57.502273 !!! SPM could not control APHY
9146 23:03:57.502356 IMPEDANCE_TRACKING: ON
9147 23:03:57.505444 TEMP_SENSOR: ON
9148 23:03:57.505526 HW_SAVE_FOR_SR: OFF
9149 23:03:57.508797 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9150 23:03:57.512220 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9151 23:03:57.515699 Read ODT Tracking: ON
9152 23:03:57.519353 Refresh Rate DeBounce: ON
9153 23:03:57.519435 DFS_NO_QUEUE_FLUSH: ON
9154 23:03:57.522370 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9155 23:03:57.525373 ENABLE_DFS_RUNTIME_MRW: OFF
9156 23:03:57.528991 DDR_RESERVE_NEW_MODE: ON
9157 23:03:57.529073 MR_CBT_SWITCH_FREQ: ON
9158 23:03:57.532008 =========================
9159 23:03:57.551018 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9160 23:03:57.554133 dram_init: ddr_geometry: 2
9161 23:03:57.572698 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9162 23:03:57.575990 dram_init: dram init end (result: 0)
9163 23:03:57.583229 DRAM-K: Full calibration passed in 24475 msecs
9164 23:03:57.586073 MRC: failed to locate region type 0.
9165 23:03:57.586156 DRAM rank0 size:0x100000000,
9166 23:03:57.589398 DRAM rank1 size=0x100000000
9167 23:03:57.599561 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9168 23:03:57.606308 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9169 23:03:57.612738 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9170 23:03:57.619423 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9171 23:03:57.623179 DRAM rank0 size:0x100000000,
9172 23:03:57.626160 DRAM rank1 size=0x100000000
9173 23:03:57.626234 CBMEM:
9174 23:03:57.629497 IMD: root @ 0xfffff000 254 entries.
9175 23:03:57.632605 IMD: root @ 0xffffec00 62 entries.
9176 23:03:57.636110 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9177 23:03:57.639542 WARNING: RO_VPD is uninitialized or empty.
9178 23:03:57.645661 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9179 23:03:57.652807 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9180 23:03:57.665283 read SPI 0x42894 0xe01e: 6223 us, 9219 KB/s, 73.752 Mbps
9181 23:03:57.676656 BS: romstage times (exec / console): total (unknown) / 23978 ms
9182 23:03:57.676746
9183 23:03:57.676812
9184 23:03:57.686655 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9185 23:03:57.690012 ARM64: Exception handlers installed.
9186 23:03:57.693328 ARM64: Testing exception
9187 23:03:57.697075 ARM64: Done test exception
9188 23:03:57.697196 Enumerating buses...
9189 23:03:57.699784 Show all devs... Before device enumeration.
9190 23:03:57.703449 Root Device: enabled 1
9191 23:03:57.706939 CPU_CLUSTER: 0: enabled 1
9192 23:03:57.707023 CPU: 00: enabled 1
9193 23:03:57.710213 Compare with tree...
9194 23:03:57.710298 Root Device: enabled 1
9195 23:03:57.713316 CPU_CLUSTER: 0: enabled 1
9196 23:03:57.716956 CPU: 00: enabled 1
9197 23:03:57.717039 Root Device scanning...
9198 23:03:57.719683 scan_static_bus for Root Device
9199 23:03:57.723263 CPU_CLUSTER: 0 enabled
9200 23:03:57.726839 scan_static_bus for Root Device done
9201 23:03:57.729960 scan_bus: bus Root Device finished in 8 msecs
9202 23:03:57.730045 done
9203 23:03:57.736553 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9204 23:03:57.739899 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9205 23:03:57.746654 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9206 23:03:57.749803 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9207 23:03:57.753380 Allocating resources...
9208 23:03:57.756578 Reading resources...
9209 23:03:57.759536 Root Device read_resources bus 0 link: 0
9210 23:03:57.759620 DRAM rank0 size:0x100000000,
9211 23:03:57.762845 DRAM rank1 size=0x100000000
9212 23:03:57.766281 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9213 23:03:57.769349 CPU: 00 missing read_resources
9214 23:03:57.776312 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9215 23:03:57.779441 Root Device read_resources bus 0 link: 0 done
9216 23:03:57.779524 Done reading resources.
9217 23:03:57.786259 Show resources in subtree (Root Device)...After reading.
9218 23:03:57.789859 Root Device child on link 0 CPU_CLUSTER: 0
9219 23:03:57.793315 CPU_CLUSTER: 0 child on link 0 CPU: 00
9220 23:03:57.802720 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9221 23:03:57.802806 CPU: 00
9222 23:03:57.806449 Root Device assign_resources, bus 0 link: 0
9223 23:03:57.809436 CPU_CLUSTER: 0 missing set_resources
9224 23:03:57.816152 Root Device assign_resources, bus 0 link: 0 done
9225 23:03:57.816237 Done setting resources.
9226 23:03:57.822882 Show resources in subtree (Root Device)...After assigning values.
9227 23:03:57.826215 Root Device child on link 0 CPU_CLUSTER: 0
9228 23:03:57.829381 CPU_CLUSTER: 0 child on link 0 CPU: 00
9229 23:03:57.839640 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9230 23:03:57.839725 CPU: 00
9231 23:03:57.842691 Done allocating resources.
9232 23:03:57.845773 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9233 23:03:57.849273 Enabling resources...
9234 23:03:57.849355 done.
9235 23:03:57.855915 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9236 23:03:57.855999 Initializing devices...
9237 23:03:57.859455 Root Device init
9238 23:03:57.859539 init hardware done!
9239 23:03:57.862674 0x00000018: ctrlr->caps
9240 23:03:57.865704 52.000 MHz: ctrlr->f_max
9241 23:03:57.865801 0.400 MHz: ctrlr->f_min
9242 23:03:57.869323 0x40ff8080: ctrlr->voltages
9243 23:03:57.869409 sclk: 390625
9244 23:03:57.872766 Bus Width = 1
9245 23:03:57.872850 sclk: 390625
9246 23:03:57.876104 Bus Width = 1
9247 23:03:57.876188 Early init status = 3
9248 23:03:57.882435 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9249 23:03:57.885857 in-header: 03 fc 00 00 01 00 00 00
9250 23:03:57.885940 in-data: 00
9251 23:03:57.892463 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9252 23:03:57.895606 in-header: 03 fd 00 00 00 00 00 00
9253 23:03:57.899014 in-data:
9254 23:03:57.902046 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9255 23:03:57.905821 in-header: 03 fc 00 00 01 00 00 00
9256 23:03:57.908847 in-data: 00
9257 23:03:57.911985 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9258 23:03:57.917179 in-header: 03 fd 00 00 00 00 00 00
9259 23:03:57.920084 in-data:
9260 23:03:57.923809 [SSUSB] Setting up USB HOST controller...
9261 23:03:57.926675 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9262 23:03:57.930094 [SSUSB] phy power-on done.
9263 23:03:57.933774 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9264 23:03:57.940463 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9265 23:03:57.943702 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9266 23:03:57.950434 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9267 23:03:57.956635 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9268 23:03:57.963152 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9269 23:03:57.969578 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9270 23:03:57.976515 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9271 23:03:57.979950 SPM: binary array size = 0x9dc
9272 23:03:57.983014 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9273 23:03:57.989956 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9274 23:03:57.996435 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9275 23:03:58.002917 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9276 23:03:58.006162 configure_display: Starting display init
9277 23:03:58.040551 anx7625_power_on_init: Init interface.
9278 23:03:58.043422 anx7625_disable_pd_protocol: Disabled PD feature.
9279 23:03:58.046770 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9280 23:03:58.074701 anx7625_start_dp_work: Secure OCM version=00
9281 23:03:58.078159 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9282 23:03:58.092624 sp_tx_get_edid_block: EDID Block = 1
9283 23:03:58.195407 Extracted contents:
9284 23:03:58.198728 header: 00 ff ff ff ff ff ff 00
9285 23:03:58.202024 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9286 23:03:58.205181 version: 01 04
9287 23:03:58.208290 basic params: 95 1f 11 78 0a
9288 23:03:58.211567 chroma info: 76 90 94 55 54 90 27 21 50 54
9289 23:03:58.215693 established: 00 00 00
9290 23:03:58.222265 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9291 23:03:58.225334 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9292 23:03:58.231922 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9293 23:03:58.238306 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9294 23:03:58.245405 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9295 23:03:58.248238 extensions: 00
9296 23:03:58.248335 checksum: fb
9297 23:03:58.248400
9298 23:03:58.251649 Manufacturer: IVO Model 57d Serial Number 0
9299 23:03:58.254852 Made week 0 of 2020
9300 23:03:58.254933 EDID version: 1.4
9301 23:03:58.258849 Digital display
9302 23:03:58.261681 6 bits per primary color channel
9303 23:03:58.261764 DisplayPort interface
9304 23:03:58.264815 Maximum image size: 31 cm x 17 cm
9305 23:03:58.268366 Gamma: 220%
9306 23:03:58.268449 Check DPMS levels
9307 23:03:58.271699 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9308 23:03:58.275059 First detailed timing is preferred timing
9309 23:03:58.278143 Established timings supported:
9310 23:03:58.281686 Standard timings supported:
9311 23:03:58.281771 Detailed timings
9312 23:03:58.288130 Hex of detail: 383680a07038204018303c0035ae10000019
9313 23:03:58.291659 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9314 23:03:58.298049 0780 0798 07c8 0820 hborder 0
9315 23:03:58.301460 0438 043b 0447 0458 vborder 0
9316 23:03:58.304802 -hsync -vsync
9317 23:03:58.304931 Did detailed timing
9318 23:03:58.311356 Hex of detail: 000000000000000000000000000000000000
9319 23:03:58.311501 Manufacturer-specified data, tag 0
9320 23:03:58.317857 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9321 23:03:58.321248 ASCII string: InfoVision
9322 23:03:58.324909 Hex of detail: 000000fe00523134304e574635205248200a
9323 23:03:58.327967 ASCII string: R140NWF5 RH
9324 23:03:58.328244 Checksum
9325 23:03:58.331619 Checksum: 0xfb (valid)
9326 23:03:58.335145 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9327 23:03:58.338305 DSI data_rate: 832800000 bps
9328 23:03:58.344743 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9329 23:03:58.348209 anx7625_parse_edid: pixelclock(138800).
9330 23:03:58.351240 hactive(1920), hsync(48), hfp(24), hbp(88)
9331 23:03:58.355111 vactive(1080), vsync(12), vfp(3), vbp(17)
9332 23:03:58.358133 anx7625_dsi_config: config dsi.
9333 23:03:58.364600 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9334 23:03:58.378086 anx7625_dsi_config: success to config DSI
9335 23:03:58.381082 anx7625_dp_start: MIPI phy setup OK.
9336 23:03:58.384531 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9337 23:03:58.387692 mtk_ddp_mode_set invalid vrefresh 60
9338 23:03:58.391234 main_disp_path_setup
9339 23:03:58.391639 ovl_layer_smi_id_en
9340 23:03:58.394174 ovl_layer_smi_id_en
9341 23:03:58.394625 ccorr_config
9342 23:03:58.394951 aal_config
9343 23:03:58.397256 gamma_config
9344 23:03:58.397335 postmask_config
9345 23:03:58.400338 dither_config
9346 23:03:58.403627 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9347 23:03:58.410616 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9348 23:03:58.413865 Root Device init finished in 551 msecs
9349 23:03:58.416980 CPU_CLUSTER: 0 init
9350 23:03:58.423547 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9351 23:03:58.427084 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9352 23:03:58.430078 APU_MBOX 0x190000b0 = 0x10001
9353 23:03:58.433376 APU_MBOX 0x190001b0 = 0x10001
9354 23:03:58.437159 APU_MBOX 0x190005b0 = 0x10001
9355 23:03:58.440201 APU_MBOX 0x190006b0 = 0x10001
9356 23:03:58.443354 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9357 23:03:58.456157 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9358 23:03:58.468440 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9359 23:03:58.475515 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9360 23:03:58.487006 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9361 23:03:58.495799 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9362 23:03:58.499139 CPU_CLUSTER: 0 init finished in 81 msecs
9363 23:03:58.502645 Devices initialized
9364 23:03:58.506420 Show all devs... After init.
9365 23:03:58.506515 Root Device: enabled 1
9366 23:03:58.509177 CPU_CLUSTER: 0: enabled 1
9367 23:03:58.512991 CPU: 00: enabled 1
9368 23:03:58.515784 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9369 23:03:58.519387 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9370 23:03:58.522719 ELOG: NV offset 0x57f000 size 0x1000
9371 23:03:58.529230 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9372 23:03:58.535730 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9373 23:03:58.539108 ELOG: Event(17) added with size 13 at 2023-12-01 23:03:24 UTC
9374 23:03:58.542240 out: cmd=0x121: 03 db 21 01 00 00 00 00
9375 23:03:58.547322 in-header: 03 4f 00 00 2c 00 00 00
9376 23:03:58.560560 in-data: 10 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9377 23:03:58.567243 ELOG: Event(A1) added with size 10 at 2023-12-01 23:03:24 UTC
9378 23:03:58.573994 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9379 23:03:58.580293 ELOG: Event(A0) added with size 9 at 2023-12-01 23:03:24 UTC
9380 23:03:58.583725 elog_add_boot_reason: Logged dev mode boot
9381 23:03:58.587222 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9382 23:03:58.590803 Finalize devices...
9383 23:03:58.590886 Devices finalized
9384 23:03:58.596824 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9385 23:03:58.600228 Writing coreboot table at 0xffe64000
9386 23:03:58.603300 0. 000000000010a000-0000000000113fff: RAMSTAGE
9387 23:03:58.606565 1. 0000000040000000-00000000400fffff: RAM
9388 23:03:58.613491 2. 0000000040100000-000000004032afff: RAMSTAGE
9389 23:03:58.616463 3. 000000004032b000-00000000545fffff: RAM
9390 23:03:58.620246 4. 0000000054600000-000000005465ffff: BL31
9391 23:03:58.623079 5. 0000000054660000-00000000ffe63fff: RAM
9392 23:03:58.629854 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9393 23:03:58.633095 7. 0000000100000000-000000023fffffff: RAM
9394 23:03:58.636369 Passing 5 GPIOs to payload:
9395 23:03:58.639925 NAME | PORT | POLARITY | VALUE
9396 23:03:58.643056 EC in RW | 0x000000aa | low | undefined
9397 23:03:58.649745 EC interrupt | 0x00000005 | low | undefined
9398 23:03:58.652980 TPM interrupt | 0x000000ab | high | undefined
9399 23:03:58.659559 SD card detect | 0x00000011 | high | undefined
9400 23:03:58.662965 speaker enable | 0x00000093 | high | undefined
9401 23:03:58.666277 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9402 23:03:58.669650 in-header: 03 f9 00 00 02 00 00 00
9403 23:03:58.672774 in-data: 02 00
9404 23:03:58.672856 ADC[4]: Raw value=901401 ID=7
9405 23:03:58.676142 ADC[3]: Raw value=213179 ID=1
9406 23:03:58.679729 RAM Code: 0x71
9407 23:03:58.679812 ADC[6]: Raw value=74502 ID=0
9408 23:03:58.682956 ADC[5]: Raw value=212072 ID=1
9409 23:03:58.686284 SKU Code: 0x1
9410 23:03:58.689746 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 844e
9411 23:03:58.693194 coreboot table: 964 bytes.
9412 23:03:58.695954 IMD ROOT 0. 0xfffff000 0x00001000
9413 23:03:58.699350 IMD SMALL 1. 0xffffe000 0x00001000
9414 23:03:58.702522 RO MCACHE 2. 0xffffc000 0x00001104
9415 23:03:58.706292 CONSOLE 3. 0xfff7c000 0x00080000
9416 23:03:58.709373 FMAP 4. 0xfff7b000 0x00000452
9417 23:03:58.712866 TIME STAMP 5. 0xfff7a000 0x00000910
9418 23:03:58.716252 VBOOT WORK 6. 0xfff66000 0x00014000
9419 23:03:58.719186 RAMOOPS 7. 0xffe66000 0x00100000
9420 23:03:58.722369 COREBOOT 8. 0xffe64000 0x00002000
9421 23:03:58.722460 IMD small region:
9422 23:03:58.725967 IMD ROOT 0. 0xffffec00 0x00000400
9423 23:03:58.729313 VPD 1. 0xffffeb80 0x0000006c
9424 23:03:58.736045 MMC STATUS 2. 0xffffeb60 0x00000004
9425 23:03:58.739368 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9426 23:03:58.742624 Probing TPM: done!
9427 23:03:58.745963 Connected to device vid:did:rid of 1ae0:0028:00
9428 23:03:58.756039 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9429 23:03:58.759857 Initialized TPM device CR50 revision 0
9430 23:03:58.762831 Checking cr50 for pending updates
9431 23:03:58.766678 Reading cr50 TPM mode
9432 23:03:58.775080 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9433 23:03:58.782002 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9434 23:03:58.821877 read SPI 0x3990ec 0x4f1b0: 34846 us, 9298 KB/s, 74.384 Mbps
9435 23:03:58.825409 Checking segment from ROM address 0x40100000
9436 23:03:58.828772 Checking segment from ROM address 0x4010001c
9437 23:03:58.835309 Loading segment from ROM address 0x40100000
9438 23:03:58.835415 code (compression=0)
9439 23:03:58.845158 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9440 23:03:58.851968 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9441 23:03:58.852075 it's not compressed!
9442 23:03:58.858679 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9443 23:03:58.861838 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9444 23:03:58.882284 Loading segment from ROM address 0x4010001c
9445 23:03:58.882414 Entry Point 0x80000000
9446 23:03:58.885988 Loaded segments
9447 23:03:58.889129 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9448 23:03:58.896122 Jumping to boot code at 0x80000000(0xffe64000)
9449 23:03:58.902416 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9450 23:03:58.908729 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9451 23:03:58.916685 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9452 23:03:58.920181 Checking segment from ROM address 0x40100000
9453 23:03:58.923444 Checking segment from ROM address 0x4010001c
9454 23:03:58.930053 Loading segment from ROM address 0x40100000
9455 23:03:58.930152 code (compression=1)
9456 23:03:58.936625 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9457 23:03:58.946828 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9458 23:03:58.946903 using LZMA
9459 23:03:58.955419 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9460 23:03:58.962061 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9461 23:03:58.965798 Loading segment from ROM address 0x4010001c
9462 23:03:58.965902 Entry Point 0x54601000
9463 23:03:58.969203 Loaded segments
9464 23:03:58.971790 NOTICE: MT8192 bl31_setup
9465 23:03:58.978871 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9466 23:03:58.982079 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9467 23:03:58.985698 WARNING: region 0:
9468 23:03:58.989132 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9469 23:03:58.989204 WARNING: region 1:
9470 23:03:58.995437 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9471 23:03:58.998901 WARNING: region 2:
9472 23:03:59.002027 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9473 23:03:59.005690 WARNING: region 3:
9474 23:03:59.008919 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9475 23:03:59.012527 WARNING: region 4:
9476 23:03:59.018929 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9477 23:03:59.019017 WARNING: region 5:
9478 23:03:59.022314 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9479 23:03:59.025719 WARNING: region 6:
9480 23:03:59.028679 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9481 23:03:59.031923 WARNING: region 7:
9482 23:03:59.035523 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9483 23:03:59.042044 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9484 23:03:59.045432 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9485 23:03:59.049123 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9486 23:03:59.055739 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9487 23:03:59.058931 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9488 23:03:59.062152 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9489 23:03:59.068780 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9490 23:03:59.072106 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9491 23:03:59.078593 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9492 23:03:59.082346 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9493 23:03:59.085275 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9494 23:03:59.091917 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9495 23:03:59.095260 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9496 23:03:59.098836 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9497 23:03:59.105442 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9498 23:03:59.108875 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9499 23:03:59.115477 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9500 23:03:59.118841 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9501 23:03:59.121697 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9502 23:03:59.128317 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9503 23:03:59.131969 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9504 23:03:59.134836 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9505 23:03:59.141659 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9506 23:03:59.145225 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9507 23:03:59.151579 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9508 23:03:59.155052 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9509 23:03:59.161751 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9510 23:03:59.164831 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9511 23:03:59.168266 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9512 23:03:59.175034 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9513 23:03:59.178194 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9514 23:03:59.181729 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9515 23:03:59.188222 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9516 23:03:59.191519 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9517 23:03:59.195104 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9518 23:03:59.198521 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9519 23:03:59.205463 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9520 23:03:59.208742 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9521 23:03:59.211722 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9522 23:03:59.215106 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9523 23:03:59.221540 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9524 23:03:59.225248 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9525 23:03:59.228609 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9526 23:03:59.231998 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9527 23:03:59.238345 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9528 23:03:59.241644 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9529 23:03:59.244905 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9530 23:03:59.248820 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9531 23:03:59.254786 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9532 23:03:59.258235 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9533 23:03:59.265240 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9534 23:03:59.268305 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9535 23:03:59.275217 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9536 23:03:59.278320 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9537 23:03:59.281775 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9538 23:03:59.288412 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9539 23:03:59.291902 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9540 23:03:59.298613 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9541 23:03:59.301737 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9542 23:03:59.308329 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9543 23:03:59.311896 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9544 23:03:59.315118 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9545 23:03:59.321752 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9546 23:03:59.324982 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9547 23:03:59.331477 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9548 23:03:59.334715 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9549 23:03:59.341918 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9550 23:03:59.345462 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9551 23:03:59.351248 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9552 23:03:59.354668 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9553 23:03:59.358065 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9554 23:03:59.364870 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9555 23:03:59.368137 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9556 23:03:59.375243 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9557 23:03:59.378177 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9558 23:03:59.384663 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9559 23:03:59.388330 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9560 23:03:59.391419 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9561 23:03:59.398047 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9562 23:03:59.401417 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9563 23:03:59.408085 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9564 23:03:59.411570 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9565 23:03:59.418014 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9566 23:03:59.421356 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9567 23:03:59.425008 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9568 23:03:59.431297 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9569 23:03:59.434741 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9570 23:03:59.441607 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9571 23:03:59.444973 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9572 23:03:59.448066 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9573 23:03:59.455414 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9574 23:03:59.458329 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9575 23:03:59.465369 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9576 23:03:59.468669 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9577 23:03:59.475045 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9578 23:03:59.478701 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9579 23:03:59.481730 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9580 23:03:59.488681 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9581 23:03:59.491685 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9582 23:03:59.495218 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9583 23:03:59.498725 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9584 23:03:59.505032 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9585 23:03:59.508258 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9586 23:03:59.515232 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9587 23:03:59.518339 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9588 23:03:59.522237 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9589 23:03:59.528576 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9590 23:03:59.531877 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9591 23:03:59.538764 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9592 23:03:59.541849 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9593 23:03:59.545112 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9594 23:03:59.552101 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9595 23:03:59.555189 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9596 23:03:59.558860 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9597 23:03:59.565761 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9598 23:03:59.568875 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9599 23:03:59.572349 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9600 23:03:59.578726 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9601 23:03:59.582126 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9602 23:03:59.585312 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9603 23:03:59.591906 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9604 23:03:59.595668 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9605 23:03:59.598825 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9606 23:03:59.602103 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9607 23:03:59.608916 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9608 23:03:59.612199 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9609 23:03:59.615258 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9610 23:03:59.622037 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9611 23:03:59.625703 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9612 23:03:59.632518 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9613 23:03:59.635540 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9614 23:03:59.638862 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9615 23:03:59.645660 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9616 23:03:59.649059 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9617 23:03:59.652210 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9618 23:03:59.659197 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9619 23:03:59.662214 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9620 23:03:59.669143 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9621 23:03:59.672127 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9622 23:03:59.675424 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9623 23:03:59.682112 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9624 23:03:59.685435 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9625 23:03:59.692263 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9626 23:03:59.695465 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9627 23:03:59.698755 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9628 23:03:59.705506 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9629 23:03:59.709058 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9630 23:03:59.712187 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9631 23:03:59.719302 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9632 23:03:59.722207 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9633 23:03:59.729265 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9634 23:03:59.732723 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9635 23:03:59.735828 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9636 23:03:59.742302 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9637 23:03:59.745840 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9638 23:03:59.749080 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9639 23:03:59.755551 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9640 23:03:59.758971 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9641 23:03:59.765844 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9642 23:03:59.769013 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9643 23:03:59.772192 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9644 23:03:59.779212 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9645 23:03:59.782303 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9646 23:03:59.788838 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9647 23:03:59.792011 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9648 23:03:59.795740 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9649 23:03:59.802084 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9650 23:03:59.805183 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9651 23:03:59.812285 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9652 23:03:59.815230 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9653 23:03:59.818671 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9654 23:03:59.825424 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9655 23:03:59.828654 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9656 23:03:59.835202 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9657 23:03:59.838736 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9658 23:03:59.841997 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9659 23:03:59.848412 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9660 23:03:59.851830 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9661 23:03:59.858598 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9662 23:03:59.861838 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9663 23:03:59.865542 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9664 23:03:59.871534 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9665 23:03:59.874837 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9666 23:03:59.881374 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9667 23:03:59.884681 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9668 23:03:59.888661 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9669 23:03:59.895013 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9670 23:03:59.898263 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9671 23:03:59.904633 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9672 23:03:59.907997 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9673 23:03:59.911157 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9674 23:03:59.917930 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9675 23:03:59.921165 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9676 23:03:59.927762 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9677 23:03:59.931243 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9678 23:03:59.934824 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9679 23:03:59.941074 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9680 23:03:59.944481 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9681 23:03:59.951076 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9682 23:03:59.954893 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9683 23:03:59.961223 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9684 23:03:59.964445 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9685 23:03:59.967733 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9686 23:03:59.974418 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9687 23:03:59.977836 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9688 23:03:59.984633 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9689 23:03:59.987751 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9690 23:03:59.990872 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9691 23:03:59.997438 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9692 23:04:00.000847 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9693 23:04:00.007382 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9694 23:04:00.010980 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9695 23:04:00.017398 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9696 23:04:00.020502 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9697 23:04:00.024228 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9698 23:04:00.030358 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9699 23:04:00.033757 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9700 23:04:00.040393 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9701 23:04:00.043779 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9702 23:04:00.050367 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9703 23:04:00.053693 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9704 23:04:00.057019 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9705 23:04:00.063845 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9706 23:04:00.067197 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9707 23:04:00.073572 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9708 23:04:00.076839 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9709 23:04:00.083779 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9710 23:04:00.087112 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9711 23:04:00.090121 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9712 23:04:00.097049 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9713 23:04:00.100035 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9714 23:04:00.103433 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9715 23:04:00.106829 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9716 23:04:00.110259 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9717 23:04:00.116639 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9718 23:04:00.119842 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9719 23:04:00.126975 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9720 23:04:00.129874 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9721 23:04:00.133195 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9722 23:04:00.139830 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9723 23:04:00.143148 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9724 23:04:00.146277 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9725 23:04:00.152942 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9726 23:04:00.156589 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9727 23:04:00.163203 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9728 23:04:00.166102 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9729 23:04:00.169625 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9730 23:04:00.176392 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9731 23:04:00.179602 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9732 23:04:00.182914 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9733 23:04:00.189447 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9734 23:04:00.193268 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9735 23:04:00.199909 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9736 23:04:00.202829 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9737 23:04:00.206405 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9738 23:04:00.212912 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9739 23:04:00.215997 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9740 23:04:00.219334 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9741 23:04:00.226100 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9742 23:04:00.228979 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9743 23:04:00.232433 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9744 23:04:00.239133 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9745 23:04:00.242700 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9746 23:04:00.246049 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9747 23:04:00.252659 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9748 23:04:00.255545 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9749 23:04:00.262365 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9750 23:04:00.265671 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9751 23:04:00.269116 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9752 23:04:00.275950 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9753 23:04:00.279126 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9754 23:04:00.282302 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9755 23:04:00.285560 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9756 23:04:00.289180 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9757 23:04:00.295675 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9758 23:04:00.298918 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9759 23:04:00.302296 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9760 23:04:00.305670 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9761 23:04:00.312578 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9762 23:04:00.315348 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9763 23:04:00.318735 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9764 23:04:00.325437 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9765 23:04:00.328744 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9766 23:04:00.332053 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9767 23:04:00.338664 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9768 23:04:00.342220 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9769 23:04:00.348913 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9770 23:04:00.351802 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9771 23:04:00.358573 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9772 23:04:00.361832 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9773 23:04:00.365463 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9774 23:04:00.371854 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9775 23:04:00.374865 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9776 23:04:00.381962 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9777 23:04:00.384900 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9778 23:04:00.388400 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9779 23:04:00.394840 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9780 23:04:00.398095 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9781 23:04:00.404827 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9782 23:04:00.407994 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9783 23:04:00.411605 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9784 23:04:00.418307 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9785 23:04:00.421787 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9786 23:04:00.428387 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9787 23:04:00.431459 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9788 23:04:00.434766 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9789 23:04:00.441526 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9790 23:04:00.444610 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9791 23:04:00.451339 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9792 23:04:00.454829 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9793 23:04:00.458440 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9794 23:04:00.464653 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9795 23:04:00.468205 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9796 23:04:00.475041 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9797 23:04:00.477895 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9798 23:04:00.481426 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9799 23:04:00.487804 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9800 23:04:00.491375 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9801 23:04:00.498145 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9802 23:04:00.501483 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9803 23:04:00.508188 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9804 23:04:00.511529 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9805 23:04:00.514640 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9806 23:04:00.521313 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9807 23:04:00.524688 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9808 23:04:00.531532 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9809 23:04:00.534597 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9810 23:04:00.537796 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9811 23:04:00.544728 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9812 23:04:00.547883 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9813 23:04:00.554380 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9814 23:04:00.557926 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9815 23:04:00.560954 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9816 23:04:00.567638 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9817 23:04:00.571091 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9818 23:04:00.577611 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9819 23:04:00.581229 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9820 23:04:00.584331 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9821 23:04:00.590845 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9822 23:04:00.594269 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9823 23:04:00.601164 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9824 23:04:00.604577 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9825 23:04:00.610787 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9826 23:04:00.614442 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9827 23:04:00.617538 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9828 23:04:00.624477 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9829 23:04:00.627351 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9830 23:04:00.634200 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9831 23:04:00.637296 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9832 23:04:00.640727 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9833 23:04:00.647294 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9834 23:04:00.651112 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9835 23:04:00.657607 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9836 23:04:00.660792 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9837 23:04:00.663965 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9838 23:04:00.670932 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9839 23:04:00.674233 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9840 23:04:00.680460 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9841 23:04:00.683880 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9842 23:04:00.690766 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9843 23:04:00.694326 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9844 23:04:00.697629 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9845 23:04:00.704307 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9846 23:04:00.707178 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9847 23:04:00.713913 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9848 23:04:00.717187 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9849 23:04:00.723660 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9850 23:04:00.726751 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9851 23:04:00.733417 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9852 23:04:00.737027 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9853 23:04:00.740089 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9854 23:04:00.746920 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9855 23:04:00.750214 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9856 23:04:00.756984 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9857 23:04:00.760051 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9858 23:04:00.766687 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9859 23:04:00.770092 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9860 23:04:00.773591 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9861 23:04:00.780025 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9862 23:04:00.783058 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9863 23:04:00.790206 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9864 23:04:00.793380 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9865 23:04:00.800175 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9866 23:04:00.803262 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9867 23:04:00.809676 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9868 23:04:00.813114 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9869 23:04:00.816308 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9870 23:04:00.823098 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9871 23:04:00.826298 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9872 23:04:00.833292 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9873 23:04:00.836211 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9874 23:04:00.843180 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9875 23:04:00.846374 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9876 23:04:00.849689 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9877 23:04:00.856609 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9878 23:04:00.859514 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9879 23:04:00.866309 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9880 23:04:00.869818 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9881 23:04:00.876176 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9882 23:04:00.879419 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9883 23:04:00.886278 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9884 23:04:00.889488 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9885 23:04:00.892726 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9886 23:04:00.899299 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9887 23:04:00.902806 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9888 23:04:00.909400 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9889 23:04:00.912887 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9890 23:04:00.915922 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9891 23:04:00.922708 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9892 23:04:00.926012 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9893 23:04:00.932472 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9894 23:04:00.935931 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9895 23:04:00.942629 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9896 23:04:00.945799 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9897 23:04:00.952580 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9898 23:04:00.955831 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9899 23:04:00.962598 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9900 23:04:00.965570 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9901 23:04:00.972419 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9902 23:04:00.975618 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9903 23:04:00.982204 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9904 23:04:00.985921 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9905 23:04:00.992433 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9906 23:04:00.995476 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9907 23:04:01.002122 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9908 23:04:01.005506 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9909 23:04:01.011989 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9910 23:04:01.015515 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9911 23:04:01.022130 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9912 23:04:01.025590 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9913 23:04:01.032020 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9914 23:04:01.035813 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9915 23:04:01.042063 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9916 23:04:01.045417 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9917 23:04:01.051950 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9918 23:04:01.052033 INFO: [APUAPC] vio 0
9919 23:04:01.058572 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9920 23:04:01.062065 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9921 23:04:01.065367 INFO: [APUAPC] D0_APC_0: 0x400510
9922 23:04:01.068498 INFO: [APUAPC] D0_APC_1: 0x0
9923 23:04:01.071869 INFO: [APUAPC] D0_APC_2: 0x1540
9924 23:04:01.075112 INFO: [APUAPC] D0_APC_3: 0x0
9925 23:04:01.078488 INFO: [APUAPC] D1_APC_0: 0xffffffff
9926 23:04:01.081802 INFO: [APUAPC] D1_APC_1: 0xffffffff
9927 23:04:01.085233 INFO: [APUAPC] D1_APC_2: 0x3fffff
9928 23:04:01.088455 INFO: [APUAPC] D1_APC_3: 0x0
9929 23:04:01.091867 INFO: [APUAPC] D2_APC_0: 0xffffffff
9930 23:04:01.095173 INFO: [APUAPC] D2_APC_1: 0xffffffff
9931 23:04:01.098492 INFO: [APUAPC] D2_APC_2: 0x3fffff
9932 23:04:01.101802 INFO: [APUAPC] D2_APC_3: 0x0
9933 23:04:01.105315 INFO: [APUAPC] D3_APC_0: 0xffffffff
9934 23:04:01.108682 INFO: [APUAPC] D3_APC_1: 0xffffffff
9935 23:04:01.111946 INFO: [APUAPC] D3_APC_2: 0x3fffff
9936 23:04:01.114943 INFO: [APUAPC] D3_APC_3: 0x0
9937 23:04:01.118447 INFO: [APUAPC] D4_APC_0: 0xffffffff
9938 23:04:01.121661 INFO: [APUAPC] D4_APC_1: 0xffffffff
9939 23:04:01.125038 INFO: [APUAPC] D4_APC_2: 0x3fffff
9940 23:04:01.125120 INFO: [APUAPC] D4_APC_3: 0x0
9941 23:04:01.128223 INFO: [APUAPC] D5_APC_0: 0xffffffff
9942 23:04:01.135313 INFO: [APUAPC] D5_APC_1: 0xffffffff
9943 23:04:01.138288 INFO: [APUAPC] D5_APC_2: 0x3fffff
9944 23:04:01.138370 INFO: [APUAPC] D5_APC_3: 0x0
9945 23:04:01.141867 INFO: [APUAPC] D6_APC_0: 0xffffffff
9946 23:04:01.144871 INFO: [APUAPC] D6_APC_1: 0xffffffff
9947 23:04:01.148089 INFO: [APUAPC] D6_APC_2: 0x3fffff
9948 23:04:01.151444 INFO: [APUAPC] D6_APC_3: 0x0
9949 23:04:01.154835 INFO: [APUAPC] D7_APC_0: 0xffffffff
9950 23:04:01.158415 INFO: [APUAPC] D7_APC_1: 0xffffffff
9951 23:04:01.161560 INFO: [APUAPC] D7_APC_2: 0x3fffff
9952 23:04:01.164748 INFO: [APUAPC] D7_APC_3: 0x0
9953 23:04:01.168530 INFO: [APUAPC] D8_APC_0: 0xffffffff
9954 23:04:01.171528 INFO: [APUAPC] D8_APC_1: 0xffffffff
9955 23:04:01.174632 INFO: [APUAPC] D8_APC_2: 0x3fffff
9956 23:04:01.178058 INFO: [APUAPC] D8_APC_3: 0x0
9957 23:04:01.181593 INFO: [APUAPC] D9_APC_0: 0xffffffff
9958 23:04:01.184645 INFO: [APUAPC] D9_APC_1: 0xffffffff
9959 23:04:01.188200 INFO: [APUAPC] D9_APC_2: 0x3fffff
9960 23:04:01.191582 INFO: [APUAPC] D9_APC_3: 0x0
9961 23:04:01.194774 INFO: [APUAPC] D10_APC_0: 0xffffffff
9962 23:04:01.198248 INFO: [APUAPC] D10_APC_1: 0xffffffff
9963 23:04:01.201333 INFO: [APUAPC] D10_APC_2: 0x3fffff
9964 23:04:01.204780 INFO: [APUAPC] D10_APC_3: 0x0
9965 23:04:01.208150 INFO: [APUAPC] D11_APC_0: 0xffffffff
9966 23:04:01.211436 INFO: [APUAPC] D11_APC_1: 0xffffffff
9967 23:04:01.214663 INFO: [APUAPC] D11_APC_2: 0x3fffff
9968 23:04:01.217908 INFO: [APUAPC] D11_APC_3: 0x0
9969 23:04:01.221173 INFO: [APUAPC] D12_APC_0: 0xffffffff
9970 23:04:01.224535 INFO: [APUAPC] D12_APC_1: 0xffffffff
9971 23:04:01.227924 INFO: [APUAPC] D12_APC_2: 0x3fffff
9972 23:04:01.231139 INFO: [APUAPC] D12_APC_3: 0x0
9973 23:04:01.234294 INFO: [APUAPC] D13_APC_0: 0xffffffff
9974 23:04:01.237701 INFO: [APUAPC] D13_APC_1: 0xffffffff
9975 23:04:01.241066 INFO: [APUAPC] D13_APC_2: 0x3fffff
9976 23:04:01.244335 INFO: [APUAPC] D13_APC_3: 0x0
9977 23:04:01.248026 INFO: [APUAPC] D14_APC_0: 0xffffffff
9978 23:04:01.251269 INFO: [APUAPC] D14_APC_1: 0xffffffff
9979 23:04:01.254305 INFO: [APUAPC] D14_APC_2: 0x3fffff
9980 23:04:01.257632 INFO: [APUAPC] D14_APC_3: 0x0
9981 23:04:01.260778 INFO: [APUAPC] D15_APC_0: 0xffffffff
9982 23:04:01.264411 INFO: [APUAPC] D15_APC_1: 0xffffffff
9983 23:04:01.267615 INFO: [APUAPC] D15_APC_2: 0x3fffff
9984 23:04:01.270924 INFO: [APUAPC] D15_APC_3: 0x0
9985 23:04:01.274143 INFO: [APUAPC] APC_CON: 0x4
9986 23:04:01.277723 INFO: [NOCDAPC] D0_APC_0: 0x0
9987 23:04:01.280734 INFO: [NOCDAPC] D0_APC_1: 0x0
9988 23:04:01.283957 INFO: [NOCDAPC] D1_APC_0: 0x0
9989 23:04:01.287576 INFO: [NOCDAPC] D1_APC_1: 0xfff
9990 23:04:01.290623 INFO: [NOCDAPC] D2_APC_0: 0x0
9991 23:04:01.290706 INFO: [NOCDAPC] D2_APC_1: 0xfff
9992 23:04:01.294146 INFO: [NOCDAPC] D3_APC_0: 0x0
9993 23:04:01.297527 INFO: [NOCDAPC] D3_APC_1: 0xfff
9994 23:04:01.300619 INFO: [NOCDAPC] D4_APC_0: 0x0
9995 23:04:01.303862 INFO: [NOCDAPC] D4_APC_1: 0xfff
9996 23:04:01.307146 INFO: [NOCDAPC] D5_APC_0: 0x0
9997 23:04:01.310494 INFO: [NOCDAPC] D5_APC_1: 0xfff
9998 23:04:01.314396 INFO: [NOCDAPC] D6_APC_0: 0x0
9999 23:04:01.316917 INFO: [NOCDAPC] D6_APC_1: 0xfff
10000 23:04:01.320362 INFO: [NOCDAPC] D7_APC_0: 0x0
10001 23:04:01.323749 INFO: [NOCDAPC] D7_APC_1: 0xfff
10002 23:04:01.327371 INFO: [NOCDAPC] D8_APC_0: 0x0
10003 23:04:01.327476 INFO: [NOCDAPC] D8_APC_1: 0xfff
10004 23:04:01.330246 INFO: [NOCDAPC] D9_APC_0: 0x0
10005 23:04:01.333469 INFO: [NOCDAPC] D9_APC_1: 0xfff
10006 23:04:01.336751 INFO: [NOCDAPC] D10_APC_0: 0x0
10007 23:04:01.339735 INFO: [NOCDAPC] D10_APC_1: 0xfff
10008 23:04:01.343480 INFO: [NOCDAPC] D11_APC_0: 0x0
10009 23:04:01.346910 INFO: [NOCDAPC] D11_APC_1: 0xfff
10010 23:04:01.349826 INFO: [NOCDAPC] D12_APC_0: 0x0
10011 23:04:01.353189 INFO: [NOCDAPC] D12_APC_1: 0xfff
10012 23:04:01.356878 INFO: [NOCDAPC] D13_APC_0: 0x0
10013 23:04:01.360043 INFO: [NOCDAPC] D13_APC_1: 0xfff
10014 23:04:01.363328 INFO: [NOCDAPC] D14_APC_0: 0x0
10015 23:04:01.366337 INFO: [NOCDAPC] D14_APC_1: 0xfff
10016 23:04:01.369494 INFO: [NOCDAPC] D15_APC_0: 0x0
10017 23:04:01.373013 INFO: [NOCDAPC] D15_APC_1: 0xfff
10018 23:04:01.373115 INFO: [NOCDAPC] APC_CON: 0x4
10019 23:04:01.379845 INFO: [APUAPC] set_apusys_apc done
10020 23:04:01.379953 INFO: [DEVAPC] devapc_init done
10021 23:04:01.386318 INFO: GICv3 without legacy support detected.
10022 23:04:01.389522 INFO: ARM GICv3 driver initialized in EL3
10023 23:04:01.393086 INFO: Maximum SPI INTID supported: 639
10024 23:04:01.396679 INFO: BL31: Initializing runtime services
10025 23:04:01.402987 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10026 23:04:01.406062 INFO: SPM: enable CPC mode
10027 23:04:01.409538 INFO: mcdi ready for mcusys-off-idle and system suspend
10028 23:04:01.416148 INFO: BL31: Preparing for EL3 exit to normal world
10029 23:04:01.419508 INFO: Entry point address = 0x80000000
10030 23:04:01.419587 INFO: SPSR = 0x8
10031 23:04:01.426461
10032 23:04:01.426542
10033 23:04:01.426608
10034 23:04:01.430167 Starting depthcharge on Spherion...
10035 23:04:01.430270
10036 23:04:01.430362 Wipe memory regions:
10037 23:04:01.430439
10038 23:04:01.431088 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10039 23:04:01.431187 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10040 23:04:01.431279 Setting prompt string to ['asurada:']
10041 23:04:01.431390 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10042 23:04:01.433216 [0x00000040000000, 0x00000054600000)
10043 23:04:01.555700
10044 23:04:01.555833 [0x00000054660000, 0x00000080000000)
10045 23:04:01.816420
10046 23:04:01.816576 [0x000000821a7280, 0x000000ffe64000)
10047 23:04:02.561044
10048 23:04:02.561188 [0x00000100000000, 0x00000240000000)
10049 23:04:04.451668
10050 23:04:04.454696 Initializing XHCI USB controller at 0x11200000.
10051 23:04:05.492701
10052 23:04:05.495610 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10053 23:04:05.495692
10054 23:04:05.495772
10055 23:04:05.495863
10056 23:04:05.496172 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10058 23:04:05.596524 asurada: tftpboot 192.168.201.1 12154372/tftp-deploy-61zxytub/kernel/image.itb 12154372/tftp-deploy-61zxytub/kernel/cmdline
10059 23:04:05.596673 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10060 23:04:05.596788 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10061 23:04:05.601317 tftpboot 192.168.201.1 12154372/tftp-deploy-61zxytub/kernel/image.itbtp-deploy-61zxytub/kernel/cmdline
10062 23:04:05.601427
10063 23:04:05.601522 Waiting for link
10064 23:04:05.761734
10065 23:04:05.761869 R8152: Initializing
10066 23:04:05.761972
10067 23:04:05.765050 Version 9 (ocp_data = 6010)
10068 23:04:05.765152
10069 23:04:05.768275 R8152: Done initializing
10070 23:04:05.768377
10071 23:04:05.768470 Adding net device
10072 23:04:07.713852
10073 23:04:07.714027 done.
10074 23:04:07.714130
10075 23:04:07.714220 MAC: 00:e0:4c:72:2d:d6
10076 23:04:07.714318
10077 23:04:07.717169 Sending DHCP discover... done.
10078 23:04:07.717273
10079 23:04:18.087866 Waiting for reply... R8152: Bulk read error 0xffffffbf
10080 23:04:18.088521
10081 23:04:18.091177 Receive failed.
10082 23:04:18.091673
10083 23:04:18.092036 done.
10084 23:04:18.092367
10085 23:04:18.094271 Sending DHCP request... done.
10086 23:04:18.094762
10087 23:04:18.101532 Waiting for reply... done.
10088 23:04:18.102084
10089 23:04:18.102496 My ip is 192.168.201.21
10090 23:04:18.102966
10091 23:04:18.104994 The DHCP server ip is 192.168.201.1
10092 23:04:18.105457
10093 23:04:18.112173 TFTP server IP predefined by user: 192.168.201.1
10094 23:04:18.112738
10095 23:04:18.118601 Bootfile predefined by user: 12154372/tftp-deploy-61zxytub/kernel/image.itb
10096 23:04:18.119168
10097 23:04:18.119543 Sending tftp read request... done.
10098 23:04:18.121777
10099 23:04:18.126186 Waiting for the transfer...
10100 23:04:18.126685
10101 23:04:18.435447 00000000 ################################################################
10102 23:04:18.435596
10103 23:04:18.708237 00080000 ################################################################
10104 23:04:18.708378
10105 23:04:18.991484 00100000 ################################################################
10106 23:04:18.991616
10107 23:04:19.272455 00180000 ################################################################
10108 23:04:19.272619
10109 23:04:19.558928 00200000 ################################################################
10110 23:04:19.559078
10111 23:04:19.853883 00280000 ################################################################
10112 23:04:19.854048
10113 23:04:20.148359 00300000 ################################################################
10114 23:04:20.148484
10115 23:04:20.436909 00380000 ################################################################
10116 23:04:20.437069
10117 23:04:20.720826 00400000 ################################################################
10118 23:04:20.720961
10119 23:04:21.002757 00480000 ################################################################
10120 23:04:21.002890
10121 23:04:21.298886 00500000 ################################################################
10122 23:04:21.299022
10123 23:04:21.571732 00580000 ################################################################
10124 23:04:21.571869
10125 23:04:21.868033 00600000 ################################################################
10126 23:04:21.868208
10127 23:04:22.153291 00680000 ################################################################
10128 23:04:22.153422
10129 23:04:22.403171 00700000 ################################################################
10130 23:04:22.403301
10131 23:04:22.679714 00780000 ################################################################
10132 23:04:22.679850
10133 23:04:22.976520 00800000 ################################################################
10134 23:04:22.976660
10135 23:04:23.260168 00880000 ################################################################
10136 23:04:23.260331
10137 23:04:23.521548 00900000 ################################################################
10138 23:04:23.521702
10139 23:04:23.788052 00980000 ################################################################
10140 23:04:23.788188
10141 23:04:24.079022 00a00000 ################################################################
10142 23:04:24.079158
10143 23:04:24.376280 00a80000 ################################################################
10144 23:04:24.376418
10145 23:04:24.668951 00b00000 ################################################################
10146 23:04:24.669112
10147 23:04:24.964839 00b80000 ################################################################
10148 23:04:24.964988
10149 23:04:25.260371 00c00000 ################################################################
10150 23:04:25.260501
10151 23:04:25.552591 00c80000 ################################################################
10152 23:04:25.552730
10153 23:04:25.801727 00d00000 ################################################################
10154 23:04:25.801864
10155 23:04:26.090757 00d80000 ################################################################
10156 23:04:26.090895
10157 23:04:26.353990 00e00000 ################################################################
10158 23:04:26.354119
10159 23:04:26.606638 00e80000 ################################################################
10160 23:04:26.606795
10161 23:04:26.898203 00f00000 ################################################################
10162 23:04:26.898359
10163 23:04:27.185813 00f80000 ################################################################
10164 23:04:27.185949
10165 23:04:27.470565 01000000 ################################################################
10166 23:04:27.470702
10167 23:04:27.735963 01080000 ################################################################
10168 23:04:27.736112
10169 23:04:28.024251 01100000 ################################################################
10170 23:04:28.024397
10171 23:04:28.310798 01180000 ################################################################
10172 23:04:28.310949
10173 23:04:28.596910 01200000 ################################################################
10174 23:04:28.597054
10175 23:04:28.855114 01280000 ################################################################
10176 23:04:28.855258
10177 23:04:29.147982 01300000 ################################################################
10178 23:04:29.148121
10179 23:04:29.443342 01380000 ################################################################
10180 23:04:29.443482
10181 23:04:29.734945 01400000 ################################################################
10182 23:04:29.735093
10183 23:04:30.031556 01480000 ################################################################
10184 23:04:30.031694
10185 23:04:30.328655 01500000 ################################################################
10186 23:04:30.328840
10187 23:04:30.620259 01580000 ################################################################
10188 23:04:30.620398
10189 23:04:30.908623 01600000 ################################################################
10190 23:04:30.908770
10191 23:04:31.174654 01680000 ################################################################
10192 23:04:31.174789
10193 23:04:31.460698 01700000 ################################################################
10194 23:04:31.460843
10195 23:04:31.754810 01780000 ################################################################
10196 23:04:31.754954
10197 23:04:32.003444 01800000 ################################################################
10198 23:04:32.003582
10199 23:04:32.285606 01880000 ################################################################
10200 23:04:32.285744
10201 23:04:32.565561 01900000 ################################################################
10202 23:04:32.565696
10203 23:04:32.829068 01980000 ################################################################
10204 23:04:32.829205
10205 23:04:33.089879 01a00000 ################################################################
10206 23:04:33.090016
10207 23:04:33.363655 01a80000 ################################################################
10208 23:04:33.363795
10209 23:04:33.650229 01b00000 ################################################################
10210 23:04:33.650395
10211 23:04:33.937612 01b80000 ################################################################
10212 23:04:33.937756
10213 23:04:34.224841 01c00000 ################################################################
10214 23:04:34.224978
10215 23:04:34.503521 01c80000 ################################################################
10216 23:04:34.503684
10217 23:04:34.796305 01d00000 ################################################################
10218 23:04:34.796445
10219 23:04:35.090074 01d80000 ################################################################
10220 23:04:35.090215
10221 23:04:35.366811 01e00000 ################################################################
10222 23:04:35.366952
10223 23:04:35.624126 01e80000 ############################################################## done.
10224 23:04:35.624260
10225 23:04:35.627499 The bootfile was 32487598 bytes long.
10226 23:04:35.627673
10227 23:04:35.630700 Sending tftp read request... done.
10228 23:04:35.630798
10229 23:04:35.630868 Waiting for the transfer...
10230 23:04:35.630931
10231 23:04:35.634345 00000000 # done.
10232 23:04:35.634448
10233 23:04:35.641053 Command line loaded dynamically from TFTP file: 12154372/tftp-deploy-61zxytub/kernel/cmdline
10234 23:04:35.641234
10235 23:04:35.654551 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10236 23:04:35.654770
10237 23:04:35.657828 Loading FIT.
10238 23:04:35.658056
10239 23:04:35.661032 Image ramdisk-1 has 21394303 bytes.
10240 23:04:35.661265
10241 23:04:35.661396 Image fdt-1 has 47278 bytes.
10242 23:04:35.661514
10243 23:04:35.665189 Image kernel-1 has 11043984 bytes.
10244 23:04:35.665442
10245 23:04:35.674546 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10246 23:04:35.674870
10247 23:04:35.691028 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10248 23:04:35.691611
10249 23:04:35.698322 Choosing best match conf-1 for compat google,spherion-rev2.
10250 23:04:35.701654
10251 23:04:35.706556 Connected to device vid:did:rid of 1ae0:0028:00
10252 23:04:35.714617
10253 23:04:35.717613 tpm_get_response: command 0x17b, return code 0x0
10254 23:04:35.718107
10255 23:04:35.720966 ec_init: CrosEC protocol v3 supported (256, 248)
10256 23:04:35.725365
10257 23:04:35.729003 tpm_cleanup: add release locality here.
10258 23:04:35.729487
10259 23:04:35.729877 Shutting down all USB controllers.
10260 23:04:35.732056
10261 23:04:35.732524 Removing current net device
10262 23:04:35.732903
10263 23:04:35.738529 Exiting depthcharge with code 4 at timestamp: 63580177
10264 23:04:35.738994
10265 23:04:35.742055 LZMA decompressing kernel-1 to 0x821a6718
10266 23:04:35.742567
10267 23:04:35.745449 LZMA decompressing kernel-1 to 0x40000000
10268 23:04:37.139672
10269 23:04:37.140360 jumping to kernel
10270 23:04:37.143520 end: 2.2.4 bootloader-commands (duration 00:00:36) [common]
10271 23:04:37.144089 start: 2.2.5 auto-login-action (timeout 00:03:50) [common]
10272 23:04:37.144510 Setting prompt string to ['Linux version [0-9]']
10273 23:04:37.144894 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10274 23:04:37.145466 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10275 23:04:37.221620
10276 23:04:37.225057 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10277 23:04:37.228638 start: 2.2.5.1 login-action (timeout 00:03:49) [common]
10278 23:04:37.229135 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10279 23:04:37.229534 Setting prompt string to []
10280 23:04:37.229977 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10281 23:04:37.230406 Using line separator: #'\n'#
10282 23:04:37.230752 No login prompt set.
10283 23:04:37.231095 Parsing kernel messages
10284 23:04:37.231410 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10285 23:04:37.231975 [login-action] Waiting for messages, (timeout 00:03:49)
10286 23:04:37.248203 [ 0.000000] Linux version 6.1.64-cip10 (KernelCI@build-j31357-arm64-gcc-10-defconfig-arm64-chromebook-69txj) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Dec 1 22:47:09 UTC 2023
10287 23:04:37.251618 [ 0.000000] random: crng init done
10288 23:04:37.258366 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10289 23:04:37.258994 [ 0.000000] efi: UEFI not found.
10290 23:04:37.268420 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10291 23:04:37.274717 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10292 23:04:37.284541 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10293 23:04:37.294786 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10294 23:04:37.301330 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10295 23:04:37.304680 [ 0.000000] printk: bootconsole [mtk8250] enabled
10296 23:04:37.313589 [ 0.000000] NUMA: No NUMA configuration found
10297 23:04:37.320528 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10298 23:04:37.326681 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10299 23:04:37.327153 [ 0.000000] Zone ranges:
10300 23:04:37.333227 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10301 23:04:37.336719 [ 0.000000] DMA32 empty
10302 23:04:37.343743 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10303 23:04:37.346695 [ 0.000000] Movable zone start for each node
10304 23:04:37.350000 [ 0.000000] Early memory node ranges
10305 23:04:37.356680 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10306 23:04:37.363205 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10307 23:04:37.369933 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10308 23:04:37.376444 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10309 23:04:37.382991 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10310 23:04:37.389469 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10311 23:04:37.446210 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10312 23:04:37.452435 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10313 23:04:37.459699 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10314 23:04:37.462563 [ 0.000000] psci: probing for conduit method from DT.
10315 23:04:37.469344 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10316 23:04:37.472736 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10317 23:04:37.479358 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10318 23:04:37.482427 [ 0.000000] psci: SMC Calling Convention v1.2
10319 23:04:37.489733 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10320 23:04:37.492738 [ 0.000000] Detected VIPT I-cache on CPU0
10321 23:04:37.499287 [ 0.000000] CPU features: detected: GIC system register CPU interface
10322 23:04:37.505950 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10323 23:04:37.512441 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10324 23:04:37.518842 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10325 23:04:37.526098 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10326 23:04:37.532092 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10327 23:04:37.538875 [ 0.000000] alternatives: applying boot alternatives
10328 23:04:37.542442 [ 0.000000] Fallback order for Node 0: 0
10329 23:04:37.549137 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10330 23:04:37.552330 [ 0.000000] Policy zone: Normal
10331 23:04:37.569524 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10332 23:04:37.578555 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10333 23:04:37.590858 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10334 23:04:37.600516 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10335 23:04:37.606867 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10336 23:04:37.610162 <6>[ 0.000000] software IO TLB: area num 8.
10337 23:04:37.666927 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10338 23:04:37.815434 <6>[ 0.000000] Memory: 7948660K/8385536K available (17984K kernel code, 4116K rwdata, 17316K rodata, 8448K init, 615K bss, 404108K reserved, 32768K cma-reserved)
10339 23:04:37.822444 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10340 23:04:37.828775 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10341 23:04:37.831920 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10342 23:04:37.838796 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10343 23:04:37.845621 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10344 23:04:37.848509 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10345 23:04:37.858533 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10346 23:04:37.865360 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10347 23:04:37.871712 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10348 23:04:37.878403 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10349 23:04:37.881455 <6>[ 0.000000] GICv3: 608 SPIs implemented
10350 23:04:37.885025 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10351 23:04:37.891491 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10352 23:04:37.894760 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10353 23:04:37.901695 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10354 23:04:37.914716 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10355 23:04:37.927833 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10356 23:04:37.934256 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10357 23:04:37.942588 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10358 23:04:37.955515 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10359 23:04:37.962088 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10360 23:04:37.969182 <6>[ 0.009184] Console: colour dummy device 80x25
10361 23:04:37.978937 <6>[ 0.013904] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10362 23:04:37.982086 <6>[ 0.024345] pid_max: default: 32768 minimum: 301
10363 23:04:37.988883 <6>[ 0.029217] LSM: Security Framework initializing
10364 23:04:37.995861 <6>[ 0.034155] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10365 23:04:38.005844 <6>[ 0.042017] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10366 23:04:38.011999 <6>[ 0.051439] cblist_init_generic: Setting adjustable number of callback queues.
10367 23:04:38.018894 <6>[ 0.058881] cblist_init_generic: Setting shift to 3 and lim to 1.
10368 23:04:38.028776 <6>[ 0.065259] cblist_init_generic: Setting adjustable number of callback queues.
10369 23:04:38.035127 <6>[ 0.072686] cblist_init_generic: Setting shift to 3 and lim to 1.
10370 23:04:38.038440 <6>[ 0.079125] rcu: Hierarchical SRCU implementation.
10371 23:04:38.045063 <6>[ 0.084171] rcu: Max phase no-delay instances is 1000.
10372 23:04:38.051839 <6>[ 0.091227] EFI services will not be available.
10373 23:04:38.054860 <6>[ 0.096182] smp: Bringing up secondary CPUs ...
10374 23:04:38.063109 <6>[ 0.101235] Detected VIPT I-cache on CPU1
10375 23:04:38.070230 <6>[ 0.101303] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10376 23:04:38.076342 <6>[ 0.101332] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10377 23:04:38.079663 <6>[ 0.101664] Detected VIPT I-cache on CPU2
10378 23:04:38.086367 <6>[ 0.101714] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10379 23:04:38.092933 <6>[ 0.101730] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10380 23:04:38.099771 <6>[ 0.101988] Detected VIPT I-cache on CPU3
10381 23:04:38.106293 <6>[ 0.102034] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10382 23:04:38.113082 <6>[ 0.102048] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10383 23:04:38.115935 <6>[ 0.102352] CPU features: detected: Spectre-v4
10384 23:04:38.122813 <6>[ 0.102358] CPU features: detected: Spectre-BHB
10385 23:04:38.125937 <6>[ 0.102363] Detected PIPT I-cache on CPU4
10386 23:04:38.132293 <6>[ 0.102420] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10387 23:04:38.139275 <6>[ 0.102436] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10388 23:04:38.146150 <6>[ 0.102731] Detected PIPT I-cache on CPU5
10389 23:04:38.152414 <6>[ 0.102790] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10390 23:04:38.158800 <6>[ 0.102806] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10391 23:04:38.162356 <6>[ 0.103086] Detected PIPT I-cache on CPU6
10392 23:04:38.169090 <6>[ 0.103151] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10393 23:04:38.175489 <6>[ 0.103168] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10394 23:04:38.182366 <6>[ 0.103464] Detected PIPT I-cache on CPU7
10395 23:04:38.188607 <6>[ 0.103528] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10396 23:04:38.195604 <6>[ 0.103544] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10397 23:04:38.199602 <6>[ 0.103591] smp: Brought up 1 node, 8 CPUs
10398 23:04:38.205602 <6>[ 0.244980] SMP: Total of 8 processors activated.
10399 23:04:38.208824 <6>[ 0.249932] CPU features: detected: 32-bit EL0 Support
10400 23:04:38.218922 <6>[ 0.255296] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10401 23:04:38.225443 <6>[ 0.264151] CPU features: detected: Common not Private translations
10402 23:04:38.232053 <6>[ 0.270666] CPU features: detected: CRC32 instructions
10403 23:04:38.235416 <6>[ 0.276017] CPU features: detected: RCpc load-acquire (LDAPR)
10404 23:04:38.241937 <6>[ 0.281978] CPU features: detected: LSE atomic instructions
10405 23:04:38.248182 <6>[ 0.287759] CPU features: detected: Privileged Access Never
10406 23:04:38.255246 <6>[ 0.293539] CPU features: detected: RAS Extension Support
10407 23:04:38.261706 <6>[ 0.299147] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10408 23:04:38.265077 <6>[ 0.306368] CPU: All CPU(s) started at EL2
10409 23:04:38.271754 <6>[ 0.310684] alternatives: applying system-wide alternatives
10410 23:04:38.281121 <6>[ 0.321389] devtmpfs: initialized
10411 23:04:38.293042 <6>[ 0.330306] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10412 23:04:38.303270 <6>[ 0.340269] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10413 23:04:38.309917 <6>[ 0.348509] pinctrl core: initialized pinctrl subsystem
10414 23:04:38.313016 <6>[ 0.355180] DMI not present or invalid.
10415 23:04:38.319508 <6>[ 0.359589] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10416 23:04:38.329913 <6>[ 0.366403] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10417 23:04:38.336362 <6>[ 0.373989] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10418 23:04:38.346236 <6>[ 0.382217] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10419 23:04:38.349279 <6>[ 0.390460] audit: initializing netlink subsys (disabled)
10420 23:04:38.359278 <5>[ 0.396151] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10421 23:04:38.365994 <6>[ 0.396865] thermal_sys: Registered thermal governor 'step_wise'
10422 23:04:38.372523 <6>[ 0.404118] thermal_sys: Registered thermal governor 'power_allocator'
10423 23:04:38.375934 <6>[ 0.410374] cpuidle: using governor menu
10424 23:04:38.382979 <6>[ 0.421330] NET: Registered PF_QIPCRTR protocol family
10425 23:04:38.389197 <6>[ 0.426805] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10426 23:04:38.392705 <6>[ 0.433907] ASID allocator initialised with 32768 entries
10427 23:04:38.399971 <6>[ 0.440474] Serial: AMBA PL011 UART driver
10428 23:04:38.408789 <4>[ 0.449257] Trying to register duplicate clock ID: 134
10429 23:04:38.462867 <6>[ 0.506894] KASLR enabled
10430 23:04:38.477622 <6>[ 0.514606] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10431 23:04:38.484164 <6>[ 0.521618] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10432 23:04:38.490480 <6>[ 0.528108] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10433 23:04:38.497451 <6>[ 0.535114] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10434 23:04:38.503771 <6>[ 0.541603] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10435 23:04:38.510518 <6>[ 0.548610] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10436 23:04:38.516683 <6>[ 0.555096] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10437 23:04:38.524142 <6>[ 0.562099] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10438 23:04:38.527203 <6>[ 0.569612] ACPI: Interpreter disabled.
10439 23:04:38.535255 <6>[ 0.576018] iommu: Default domain type: Translated
10440 23:04:38.542228 <6>[ 0.581128] iommu: DMA domain TLB invalidation policy: strict mode
10441 23:04:38.545491 <5>[ 0.587785] SCSI subsystem initialized
10442 23:04:38.551934 <6>[ 0.591947] usbcore: registered new interface driver usbfs
10443 23:04:38.558464 <6>[ 0.597681] usbcore: registered new interface driver hub
10444 23:04:38.561920 <6>[ 0.603231] usbcore: registered new device driver usb
10445 23:04:38.568935 <6>[ 0.609330] pps_core: LinuxPPS API ver. 1 registered
10446 23:04:38.578426 <6>[ 0.614526] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10447 23:04:38.582544 <6>[ 0.623872] PTP clock support registered
10448 23:04:38.585278 <6>[ 0.628114] EDAC MC: Ver: 3.0.0
10449 23:04:38.592781 <6>[ 0.633273] FPGA manager framework
10450 23:04:38.596413 <6>[ 0.636951] Advanced Linux Sound Architecture Driver Initialized.
10451 23:04:38.600100 <6>[ 0.643725] vgaarb: loaded
10452 23:04:38.606184 <6>[ 0.646893] clocksource: Switched to clocksource arch_sys_counter
10453 23:04:38.612998 <5>[ 0.653340] VFS: Disk quotas dquot_6.6.0
10454 23:04:38.619646 <6>[ 0.657525] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10455 23:04:38.622952 <6>[ 0.664718] pnp: PnP ACPI: disabled
10456 23:04:38.631130 <6>[ 0.671431] NET: Registered PF_INET protocol family
10457 23:04:38.640636 <6>[ 0.677032] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10458 23:04:38.651964 <6>[ 0.689354] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10459 23:04:38.662287 <6>[ 0.698167] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10460 23:04:38.668943 <6>[ 0.706137] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10461 23:04:38.676155 <6>[ 0.714834] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10462 23:04:38.687355 <6>[ 0.724580] TCP: Hash tables configured (established 65536 bind 65536)
10463 23:04:38.694084 <6>[ 0.731444] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10464 23:04:38.700456 <6>[ 0.738643] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10465 23:04:38.707515 <6>[ 0.746345] NET: Registered PF_UNIX/PF_LOCAL protocol family
10466 23:04:38.714155 <6>[ 0.752515] RPC: Registered named UNIX socket transport module.
10467 23:04:38.716916 <6>[ 0.758670] RPC: Registered udp transport module.
10468 23:04:38.724424 <6>[ 0.763603] RPC: Registered tcp transport module.
10469 23:04:38.730233 <6>[ 0.768536] RPC: Registered tcp NFSv4.1 backchannel transport module.
10470 23:04:38.733726 <6>[ 0.775206] PCI: CLS 0 bytes, default 64
10471 23:04:38.736825 <6>[ 0.779611] Unpacking initramfs...
10472 23:04:38.761800 <6>[ 0.798992] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10473 23:04:38.771563 <6>[ 0.807666] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10474 23:04:38.774750 <6>[ 0.816523] kvm [1]: IPA Size Limit: 40 bits
10475 23:04:38.781601 <6>[ 0.821047] kvm [1]: GICv3: no GICV resource entry
10476 23:04:38.784906 <6>[ 0.826068] kvm [1]: disabling GICv2 emulation
10477 23:04:38.791358 <6>[ 0.830757] kvm [1]: GIC system register CPU interface enabled
10478 23:04:38.794658 <6>[ 0.836919] kvm [1]: vgic interrupt IRQ18
10479 23:04:38.801438 <6>[ 0.841270] kvm [1]: VHE mode initialized successfully
10480 23:04:38.807951 <5>[ 0.847686] Initialise system trusted keyrings
10481 23:04:38.814496 <6>[ 0.852511] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10482 23:04:38.822011 <6>[ 0.862540] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10483 23:04:38.828792 <5>[ 0.868931] NFS: Registering the id_resolver key type
10484 23:04:38.832086 <5>[ 0.874237] Key type id_resolver registered
10485 23:04:38.838248 <5>[ 0.878652] Key type id_legacy registered
10486 23:04:38.845155 <6>[ 0.882932] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10487 23:04:38.851744 <6>[ 0.889855] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10488 23:04:38.858199 <6>[ 0.897565] 9p: Installing v9fs 9p2000 file system support
10489 23:04:38.894306 <5>[ 0.934941] Key type asymmetric registered
10490 23:04:38.897950 <5>[ 0.939275] Asymmetric key parser 'x509' registered
10491 23:04:38.907239 <6>[ 0.944423] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10492 23:04:38.910536 <6>[ 0.952036] io scheduler mq-deadline registered
10493 23:04:38.914131 <6>[ 0.956812] io scheduler kyber registered
10494 23:04:38.933199 <6>[ 0.973864] EINJ: ACPI disabled.
10495 23:04:38.965653 <4>[ 0.999512] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10496 23:04:38.975115 <4>[ 1.010138] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10497 23:04:38.990579 <6>[ 1.031214] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10498 23:04:38.998733 <6>[ 1.039306] printk: console [ttyS0] disabled
10499 23:04:39.026970 <6>[ 1.063954] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10500 23:04:39.033486 <6>[ 1.073427] printk: console [ttyS0] enabled
10501 23:04:39.036568 <6>[ 1.073427] printk: console [ttyS0] enabled
10502 23:04:39.043193 <6>[ 1.082323] printk: bootconsole [mtk8250] disabled
10503 23:04:39.047235 <6>[ 1.082323] printk: bootconsole [mtk8250] disabled
10504 23:04:39.053305 <6>[ 1.093590] SuperH (H)SCI(F) driver initialized
10505 23:04:39.056321 <6>[ 1.098904] msm_serial: driver initialized
10506 23:04:39.070858 <6>[ 1.107957] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10507 23:04:39.080720 <6>[ 1.116513] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10508 23:04:39.087002 <6>[ 1.125058] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10509 23:04:39.097062 <6>[ 1.133686] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10510 23:04:39.107101 <6>[ 1.142393] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10511 23:04:39.113825 <6>[ 1.151114] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10512 23:04:39.123765 <6>[ 1.159655] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10513 23:04:39.130330 <6>[ 1.168456] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10514 23:04:39.140151 <6>[ 1.176999] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10515 23:04:39.152025 <6>[ 1.192633] loop: module loaded
10516 23:04:39.158365 <6>[ 1.198653] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10517 23:04:39.181703 <4>[ 1.222110] mtk-pmic-keys: Failed to locate of_node [id: -1]
10518 23:04:39.188840 <6>[ 1.229107] megasas: 07.719.03.00-rc1
10519 23:04:39.197651 <6>[ 1.238620] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10520 23:04:39.205643 <6>[ 1.246271] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10521 23:04:39.222441 <6>[ 1.262984] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10522 23:04:39.279255 <6>[ 1.313165] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10523 23:04:39.641335 <6>[ 1.682228] Freeing initrd memory: 20892K
10524 23:04:39.657665 <6>[ 1.697998] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10525 23:04:39.668645 <6>[ 1.708872] tun: Universal TUN/TAP device driver, 1.6
10526 23:04:39.671280 <6>[ 1.714938] thunder_xcv, ver 1.0
10527 23:04:39.674984 <6>[ 1.718432] thunder_bgx, ver 1.0
10528 23:04:39.678130 <6>[ 1.721930] nicpf, ver 1.0
10529 23:04:39.688655 <6>[ 1.725930] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10530 23:04:39.691990 <6>[ 1.733405] hns3: Copyright (c) 2017 Huawei Corporation.
10531 23:04:39.698473 <6>[ 1.738990] hclge is initializing
10532 23:04:39.702086 <6>[ 1.742566] e1000: Intel(R) PRO/1000 Network Driver
10533 23:04:39.708417 <6>[ 1.747695] e1000: Copyright (c) 1999-2006 Intel Corporation.
10534 23:04:39.711684 <6>[ 1.753707] e1000e: Intel(R) PRO/1000 Network Driver
10535 23:04:39.718458 <6>[ 1.758922] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10536 23:04:39.725392 <6>[ 1.765110] igb: Intel(R) Gigabit Ethernet Network Driver
10537 23:04:39.732110 <6>[ 1.770760] igb: Copyright (c) 2007-2014 Intel Corporation.
10538 23:04:39.738706 <6>[ 1.776594] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10539 23:04:39.741883 <6>[ 1.783112] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10540 23:04:39.748910 <6>[ 1.789572] sky2: driver version 1.30
10541 23:04:39.755380 <6>[ 1.794567] VFIO - User Level meta-driver version: 0.3
10542 23:04:39.762824 <6>[ 1.802811] usbcore: registered new interface driver usb-storage
10543 23:04:39.768714 <6>[ 1.809259] usbcore: registered new device driver onboard-usb-hub
10544 23:04:39.778072 <6>[ 1.818391] mt6397-rtc mt6359-rtc: registered as rtc0
10545 23:04:39.787852 <6>[ 1.823852] mt6397-rtc mt6359-rtc: setting system clock to 2023-12-01T23:04:06 UTC (1701471846)
10546 23:04:39.790868 <6>[ 1.833417] i2c_dev: i2c /dev entries driver
10547 23:04:39.807591 <6>[ 1.845108] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10548 23:04:39.827403 <6>[ 1.868078] cpu cpu0: EM: created perf domain
10549 23:04:39.830688 <6>[ 1.873034] cpu cpu4: EM: created perf domain
10550 23:04:39.837965 <6>[ 1.878590] sdhci: Secure Digital Host Controller Interface driver
10551 23:04:39.844572 <6>[ 1.885022] sdhci: Copyright(c) Pierre Ossman
10552 23:04:39.851081 <6>[ 1.889976] Synopsys Designware Multimedia Card Interface Driver
10553 23:04:39.857991 <6>[ 1.896608] sdhci-pltfm: SDHCI platform and OF driver helper
10554 23:04:39.861946 <6>[ 1.896641] mmc0: CQHCI version 5.10
10555 23:04:39.867977 <6>[ 1.906586] ledtrig-cpu: registered to indicate activity on CPUs
10556 23:04:39.875045 <6>[ 1.913651] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10557 23:04:39.881878 <6>[ 1.920711] usbcore: registered new interface driver usbhid
10558 23:04:39.885165 <6>[ 1.926533] usbhid: USB HID core driver
10559 23:04:39.891468 <6>[ 1.930736] spi_master spi0: will run message pump with realtime priority
10560 23:04:39.933754 <6>[ 1.967915] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10561 23:04:39.952205 <6>[ 1.982743] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10562 23:04:39.955486 <6>[ 1.998027] mmc0: Command Queue Engine enabled
10563 23:04:39.962375 <6>[ 1.998049] cros-ec-spi spi0.0: Chrome EC device registered
10564 23:04:39.969076 <6>[ 2.008624] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10565 23:04:39.975922 <6>[ 2.016227] mmcblk0: mmc0:0001 DA4128 116 GiB
10566 23:04:39.985337 <6>[ 2.026111] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10567 23:04:39.992782 <6>[ 2.033653] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10568 23:04:40.002705 <6>[ 2.037141] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10569 23:04:40.006311 <6>[ 2.039596] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10570 23:04:40.012876 <6>[ 2.049505] NET: Registered PF_PACKET protocol family
10571 23:04:40.019143 <6>[ 2.054063] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10572 23:04:40.022888 <6>[ 2.058792] 9pnet: Installing 9P2000 support
10573 23:04:40.029552 <5>[ 2.069817] Key type dns_resolver registered
10574 23:04:40.032937 <6>[ 2.074762] registered taskstats version 1
10575 23:04:40.039059 <5>[ 2.079150] Loading compiled-in X.509 certificates
10576 23:04:40.069589 <4>[ 2.103707] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10577 23:04:40.079578 <4>[ 2.114468] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10578 23:04:40.086159 <3>[ 2.125007] debugfs: File 'uA_load' in directory '/' already present!
10579 23:04:40.093268 <3>[ 2.131765] debugfs: File 'min_uV' in directory '/' already present!
10580 23:04:40.100071 <3>[ 2.138383] debugfs: File 'max_uV' in directory '/' already present!
10581 23:04:40.106434 <3>[ 2.144998] debugfs: File 'constraint_flags' in directory '/' already present!
10582 23:04:40.117377 <3>[ 2.154739] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10583 23:04:40.129678 <6>[ 2.170236] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10584 23:04:40.136712 <6>[ 2.177091] xhci-mtk 11200000.usb: xHCI Host Controller
10585 23:04:40.143264 <6>[ 2.182599] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10586 23:04:40.153418 <6>[ 2.190535] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10587 23:04:40.159994 <6>[ 2.199967] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10588 23:04:40.166725 <6>[ 2.206040] xhci-mtk 11200000.usb: xHCI Host Controller
10589 23:04:40.173325 <6>[ 2.211519] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10590 23:04:40.179828 <6>[ 2.219174] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10591 23:04:40.186124 <6>[ 2.227002] hub 1-0:1.0: USB hub found
10592 23:04:40.190083 <6>[ 2.231016] hub 1-0:1.0: 1 port detected
10593 23:04:40.196653 <6>[ 2.235290] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10594 23:04:40.203330 <6>[ 2.244004] hub 2-0:1.0: USB hub found
10595 23:04:40.206509 <6>[ 2.248024] hub 2-0:1.0: 1 port detected
10596 23:04:40.214288 <6>[ 2.255295] mtk-msdc 11f70000.mmc: Got CD GPIO
10597 23:04:40.231215 <6>[ 2.268723] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10598 23:04:40.237767 <6>[ 2.276769] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10599 23:04:40.247905 <4>[ 2.284674] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10600 23:04:40.258061 <6>[ 2.294215] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10601 23:04:40.264231 <6>[ 2.302293] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10602 23:04:40.271321 <6>[ 2.310302] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10603 23:04:40.281637 <6>[ 2.318226] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10604 23:04:40.288211 <6>[ 2.326043] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10605 23:04:40.298525 <6>[ 2.333860] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10606 23:04:40.307729 <6>[ 2.343957] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10607 23:04:40.314663 <6>[ 2.352326] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10608 23:04:40.324056 <6>[ 2.360676] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10609 23:04:40.330607 <6>[ 2.369016] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10610 23:04:40.340563 <6>[ 2.377354] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10611 23:04:40.347312 <6>[ 2.385693] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10612 23:04:40.357588 <6>[ 2.394032] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10613 23:04:40.363841 <6>[ 2.402370] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10614 23:04:40.374047 <6>[ 2.410709] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10615 23:04:40.380683 <6>[ 2.419048] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10616 23:04:40.390953 <6>[ 2.427389] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10617 23:04:40.397884 <6>[ 2.435727] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10618 23:04:40.406929 <6>[ 2.444065] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10619 23:04:40.413435 <6>[ 2.452403] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10620 23:04:40.423845 <6>[ 2.460743] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10621 23:04:40.430334 <6>[ 2.469462] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10622 23:04:40.436623 <6>[ 2.476632] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10623 23:04:40.443304 <6>[ 2.483393] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10624 23:04:40.449697 <6>[ 2.490154] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10625 23:04:40.456337 <6>[ 2.497088] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10626 23:04:40.466860 <6>[ 2.503944] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10627 23:04:40.476405 <6>[ 2.513076] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10628 23:04:40.486249 <6>[ 2.522195] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10629 23:04:40.496278 <6>[ 2.531489] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10630 23:04:40.506377 <6>[ 2.540960] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10631 23:04:40.512785 <6>[ 2.550429] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10632 23:04:40.522974 <6>[ 2.559550] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10633 23:04:40.532805 <6>[ 2.569017] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10634 23:04:40.542823 <6>[ 2.578135] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10635 23:04:40.552455 <6>[ 2.587428] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10636 23:04:40.562349 <6>[ 2.597589] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10637 23:04:40.572657 <6>[ 2.609177] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10638 23:04:40.609952 <6>[ 2.647158] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10639 23:04:40.764586 <6>[ 2.805088] hub 1-1:1.0: USB hub found
10640 23:04:40.767625 <6>[ 2.809603] hub 1-1:1.0: 4 ports detected
10641 23:04:40.777852 <6>[ 2.818343] hub 1-1:1.0: USB hub found
10642 23:04:40.780851 <6>[ 2.822687] hub 1-1:1.0: 4 ports detected
10643 23:04:40.889927 <6>[ 2.927498] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10644 23:04:40.916262 <6>[ 2.957052] hub 2-1:1.0: USB hub found
10645 23:04:40.919231 <6>[ 2.961548] hub 2-1:1.0: 3 ports detected
10646 23:04:40.928905 <6>[ 2.969267] hub 2-1:1.0: USB hub found
10647 23:04:40.931986 <6>[ 2.973771] hub 2-1:1.0: 3 ports detected
10648 23:04:41.105373 <6>[ 3.143194] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10649 23:04:41.238784 <6>[ 3.279182] hub 1-1.4:1.0: USB hub found
10650 23:04:41.241772 <6>[ 3.283862] hub 1-1.4:1.0: 2 ports detected
10651 23:04:41.250280 <6>[ 3.291433] hub 1-1.4:1.0: USB hub found
10652 23:04:41.253885 <6>[ 3.295979] hub 1-1.4:1.0: 2 ports detected
10653 23:04:41.322044 <6>[ 3.359388] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10654 23:04:41.549143 <6>[ 3.587194] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10655 23:04:41.741786 <6>[ 3.779193] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10656 23:04:52.850546 <6>[ 14.896101] ALSA device list:
10657 23:04:52.856992 <6>[ 14.899385] No soundcards found.
10658 23:04:52.864406 <6>[ 14.906682] Freeing unused kernel memory: 8448K
10659 23:04:52.868263 <6>[ 14.911710] Run /init as init process
10660 23:04:52.899895 Starting syslogd: OK
10661 23:04:52.903254 Starting klogd: OK
10662 23:04:52.909988 Running sysctl: OK
10663 23:04:52.916146 Populating /dev using udev: <30>[ 14.960154] udevd[195]: starting version 3.2.9
10664 23:04:52.926656 <27>[ 14.968798] udevd[195]: specified user 'tss' unknown
10665 23:04:52.933448 <27>[ 14.974249] udevd[195]: specified group 'tss' unknown
10666 23:04:52.937245 <30>[ 14.980507] udevd[196]: starting eudev-3.2.9
10667 23:04:52.957366 <27>[ 14.999327] udevd[196]: specified user 'tss' unknown
10668 23:04:52.963502 <27>[ 15.004666] udevd[196]: specified group 'tss' unknown
10669 23:04:53.053074 <6>[ 15.091985] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10670 23:04:53.070357 <6>[ 15.112577] remoteproc remoteproc0: scp is available
10671 23:04:53.076894 <6>[ 15.113341] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10672 23:04:53.083521 <6>[ 15.118088] remoteproc remoteproc0: powering up scp
10673 23:04:53.093345 <6>[ 15.125421] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10674 23:04:53.100127 <3>[ 15.126073] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10675 23:04:53.107280 <3>[ 15.126080] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10676 23:04:53.116989 <3>[ 15.126083] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10677 23:04:53.123446 <3>[ 15.126127] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10678 23:04:53.133412 <3>[ 15.126130] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10679 23:04:53.140225 <3>[ 15.126132] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10680 23:04:53.149526 <3>[ 15.126135] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10681 23:04:53.156208 <3>[ 15.126138] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10682 23:04:53.166467 <3>[ 15.126156] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10683 23:04:53.173048 <3>[ 15.126169] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10684 23:04:53.179991 <3>[ 15.126171] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10685 23:04:53.190053 <3>[ 15.126173] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10686 23:04:53.196734 <3>[ 15.126187] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10687 23:04:53.206613 <3>[ 15.126190] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10688 23:04:53.213688 <3>[ 15.126192] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10689 23:04:53.220823 <3>[ 15.126194] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10690 23:04:53.230639 <3>[ 15.126196] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10691 23:04:53.237225 <3>[ 15.126205] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10692 23:04:53.246913 <6>[ 15.130678] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10693 23:04:53.254314 <6>[ 15.139232] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10694 23:04:53.260632 <6>[ 15.147309] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10695 23:04:53.267094 <6>[ 15.163099] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10696 23:04:53.273677 <6>[ 15.179225] mc: Linux media interface: v0.10
10697 23:04:53.277004 <6>[ 15.180996] usbcore: registered new interface driver r8152
10698 23:04:53.283645 <6>[ 15.204468] videodev: Linux video capture interface: v2.00
10699 23:04:53.293616 <4>[ 15.209094] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10700 23:04:53.296934 <4>[ 15.209094] Fallback method does not support PEC.
10701 23:04:53.306856 <3>[ 15.226121] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10702 23:04:53.313505 <4>[ 15.237242] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10703 23:04:53.322855 <3>[ 15.266322] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10704 23:04:53.329809 <4>[ 15.269035] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10705 23:04:53.336104 <6>[ 15.280189] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10706 23:04:53.346103 <6>[ 15.288623] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10707 23:04:53.352901 <6>[ 15.288633] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10708 23:04:53.359256 <6>[ 15.293385] pci_bus 0000:00: root bus resource [bus 00-ff]
10709 23:04:53.366168 <6>[ 15.295199] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10710 23:04:53.373285 <6>[ 15.302034] remoteproc remoteproc0: remote processor scp is now up
10711 23:04:53.379707 <6>[ 15.303072] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10712 23:04:53.386168 <6>[ 15.307693] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10713 23:04:53.395811 <6>[ 15.307699] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10714 23:04:53.405725 <6>[ 15.317021] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10715 23:04:53.412101 <6>[ 15.319897] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10716 23:04:53.418681 <6>[ 15.319917] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10717 23:04:53.428937 <6>[ 15.326698] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10718 23:04:53.438916 <4>[ 15.328411] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10719 23:04:53.445589 <4>[ 15.328418] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10720 23:04:53.451816 <6>[ 15.331530] pci 0000:00:00.0: supports D1 D2
10721 23:04:53.458816 <6>[ 15.345533] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10722 23:04:53.465356 <6>[ 15.353924] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10723 23:04:53.472337 <6>[ 15.379116] r8152 2-1.3:1.0 eth0: v1.12.13
10724 23:04:53.478768 <6>[ 15.384796] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10725 23:04:53.488900 <6>[ 15.394340] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10726 23:04:53.494883 <6>[ 15.399707] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10727 23:04:53.498483 <6>[ 15.424242] Bluetooth: Core ver 2.22
10728 23:04:53.504947 <6>[ 15.427217] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10729 23:04:53.511293 <6>[ 15.427436] usbcore: registered new interface driver cdc_ether
10730 23:04:53.518132 <6>[ 15.434345] NET: Registered PF_BLUETOOTH protocol family
10731 23:04:53.524675 <6>[ 15.434456] usbcore: registered new interface driver r8153_ecm
10732 23:04:53.531519 <6>[ 15.444237] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10733 23:04:53.538106 <6>[ 15.452477] Bluetooth: HCI device and connection manager initialized
10734 23:04:53.541365 <6>[ 15.452487] Bluetooth: HCI socket layer initialized
10735 23:04:53.551263 <6>[ 15.452958] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10736 23:04:53.561379 <6>[ 15.453857] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10737 23:04:53.567916 <6>[ 15.453922] usbcore: registered new interface driver uvcvideo
10738 23:04:53.574668 <6>[ 15.458754] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10739 23:04:53.581236 <6>[ 15.466212] Bluetooth: L2CAP socket layer initialized
10740 23:04:53.584947 <6>[ 15.476385] pci 0000:01:00.0: supports D1 D2
10741 23:04:53.591322 <6>[ 15.485317] Bluetooth: SCO socket layer initialized
10742 23:04:53.597864 <6>[ 15.493391] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10743 23:04:53.604330 <6>[ 15.507240] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10744 23:04:53.610840 <6>[ 15.553489] usbcore: registered new interface driver btusb
10745 23:04:53.620519 <4>[ 15.554292] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10746 23:04:53.627124 <3>[ 15.554308] Bluetooth: hci0: Failed to load firmware file (-2)
10747 23:04:53.633727 <3>[ 15.554314] Bluetooth: hci0: Failed to set up firmware (-2)
10748 23:04:53.644431 <4>[ 15.554321] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10749 23:04:53.650056 <6>[ 15.575025] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10750 23:04:53.657286 <6>[ 15.696853] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10751 23:04:53.666557 <6>[ 15.704935] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10752 23:04:53.673594 <6>[ 15.712933] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10753 23:04:53.679707 <6>[ 15.720935] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10754 23:04:53.690143 <6>[ 15.728935] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10755 23:04:53.696703 <6>[ 15.736934] pci 0000:00:00.0: PCI bridge to [bus 01]
10756 23:04:53.703177 <6>[ 15.742151] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10757 23:04:53.709801 <6>[ 15.750224] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10758 23:04:53.716421 <6>[ 15.756948] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10759 23:04:53.722908 <6>[ 15.763520] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10760 23:04:53.745996 <5>[ 15.785110] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10761 23:04:53.765092 <5>[ 15.803626] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10762 23:04:53.771503 <4>[ 15.810540] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10763 23:04:53.777747 <6>[ 15.819461] cfg80211: failed to load regulatory.db
10764 23:04:53.814322 <6>[ 15.853312] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10765 23:04:53.820739 <6>[ 15.860848] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10766 23:04:53.844962 <6>[ 15.887114] mt7921e 0000:01:00.0: ASIC revision: 79610010
10767 23:04:53.946682 <4>[ 15.982340] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10768 23:04:53.961097 done
10769 23:04:53.964817 Saving random seed: OK
10770 23:04:53.980331 Starting network: OK
10771 23:04:54.007092 Starting dropbear sshd: <6>[ 16.048937] NET: Registered PF_INET6 protocol family
10772 23:04:54.010147 <6>[ 16.054753] Segment Routing with IPv6
10773 23:04:54.016610 <6>[ 16.058685] In-situ OAM (IOAM) with IPv6
10774 23:04:54.017170 OK
10775 23:04:54.028870 /bin/sh: can't access tty; job control turned off
10776 23:04:54.030135 Matched prompt #10: / #
10778 23:04:54.031286 Setting prompt string to ['/ #']
10779 23:04:54.031751 end: 2.2.5.1 login-action (duration 00:00:17) [common]
10781 23:04:54.032819 end: 2.2.5 auto-login-action (duration 00:00:17) [common]
10782 23:04:54.033291 start: 2.2.6 expect-shell-connection (timeout 00:03:33) [common]
10783 23:04:54.033669 Setting prompt string to ['/ #']
10784 23:04:54.034005 Forcing a shell prompt, looking for ['/ #']
10786 23:04:54.084983 / #
10787 23:04:54.085692 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10788 23:04:54.086319 Waiting using forced prompt support (timeout 00:02:30)
10789 23:04:54.086895 <4>[ 16.086932] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10790 23:04:54.091344
10791 23:04:54.092289 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10792 23:04:54.092891 start: 2.2.7 export-device-env (timeout 00:03:33) [common]
10793 23:04:54.093394 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10794 23:04:54.093870 end: 2.2 depthcharge-retry (duration 00:01:27) [common]
10795 23:04:54.094349 end: 2 depthcharge-action (duration 00:01:27) [common]
10796 23:04:54.094860 start: 3 lava-test-retry (timeout 00:01:00) [common]
10797 23:04:54.095341 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10798 23:04:54.095764 Using namespace: common
10800 23:04:54.196913 / # #
10801 23:04:54.197585 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10802 23:04:54.198214 <4>[ 16.194427] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10803 23:04:54.203848 #
10804 23:04:54.204718 Using /lava-12154372
10806 23:04:54.306041 / # export SHELL=/bin/sh
10807 23:04:54.306898 <4>[ 16.302494] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10808 23:04:54.312778 export SHELL=/bin/sh
10810 23:04:54.414446 / # . /lava-12154372/environment
10811 23:04:54.415324 <4>[ 16.414304] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10812 23:04:54.420803 . /lava-12154372/environment
10814 23:04:54.522498 / # /lava-12154372/bin/lava-test-runner /lava-12154372/0
10815 23:04:54.523130 Test shell timeout: 10s (minimum of the action and connection timeout)
10816 23:04:54.524877 /lava-12154372/bin/lava-test<4>[ 16.526440] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10817 23:04:54.528880 -runner /lava-12154372/0
10818 23:04:54.570923 + export 'TESTRU<8>[ 16.593375] <LAVA_SIGNAL_STARTRUN 0_dmesg 12154372_1.5.2.3.1>
10819 23:04:54.571551 N_ID=0_dmesg'
10820 23:04:54.571954 + cd /lava-12154372/0/tests/0_dmesg
10821 23:04:54.572327 + cat uuid
10822 23:04:54.572798 + UUID=12154372_1.5.2.3.1
10823 23:04:54.573141 + set +x
10824 23:04:54.573466 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
10825 23:04:54.574057 Received signal: <STARTRUN> 0_dmesg 12154372_1.5.2.3.1
10826 23:04:54.574465 Starting test lava.0_dmesg (12154372_1.5.2.3.1)
10827 23:04:54.574891 Skipping test definition patterns.
10828 23:04:54.575845 <8>[ 16.614440] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
10829 23:04:54.576492 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
10831 23:04:54.599261 <4>[ 16.634746] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10832 23:04:54.605591 <8>[ 16.639282] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
10833 23:04:54.606503 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
10835 23:04:54.627354 <8>[ 16.666330] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
10836 23:04:54.628166 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
10838 23:04:54.630374 + set +x
10839 23:04:54.633596 <8>[ 16.675677] <LAVA_SIGNAL_ENDRUN 0_dmesg 12154372_1.5.2.3.1>
10840 23:04:54.634467 Received signal: <ENDRUN> 0_dmesg 12154372_1.5.2.3.1
10841 23:04:54.634913 Ending use of test pattern.
10842 23:04:54.635271 Ending test lava.0_dmesg (12154372_1.5.2.3.1), duration 0.06
10844 23:04:54.637735 <LAVA_TEST_RUNNER EXIT>
10845 23:04:54.638477 ok: lava_test_shell seems to have completed
10846 23:04:54.639061 alert: pass
crit: pass
emerg: pass
10847 23:04:54.639507 end: 3.1 lava-test-shell (duration 00:00:01) [common]
10848 23:04:54.639972 end: 3 lava-test-retry (duration 00:00:01) [common]
10849 23:04:54.640439 start: 4 lava-test-retry (timeout 00:01:00) [common]
10850 23:04:54.640894 start: 4.1 lava-test-shell (timeout 00:01:00) [common]
10851 23:04:54.641257 Using namespace: common
10853 23:04:54.742561 / # #
10854 23:04:54.743210 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10855 23:04:54.743899 Using /lava-12154372
10857 23:04:54.845149 export SHELL=/bin/sh
10858 23:04:54.845953 #<4>[ 16.750236] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10859 23:04:54.846437
10860 23:04:54.846803 / # export SHELL=/bin/sh<4>[ 16.862165] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10862 23:04:54.948464 . /lava-12154372/environment
10863 23:04:54.949278
10864 23:04:54.949723 / # . /lava-12154372/environment<4>[ 16.974391] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10866 23:04:55.051393 /lava-12154372/bin/lava-test-runner /lava-12154372/1
10867 23:04:55.052087 Test shell timeout: 10s (minimum of the action and connection timeout)
10868 23:04:55.052930
10869 23:04:55.053336 / # /lava-12154372/bin/lava-test-runner /lava-12154372/1<3>[ 17.084143] mt7921e 0000:01:00.0: hardware init failed
10870 23:04:55.094956
10871 23:04:55.095512 + export 'TESTRUN_ID=1_bootrr'
10872 23:04:55.096195 <8>[ 17.121342] <LAVA_SIGNAL_STARTRUN 1_bootrr 12154372_1.5.2.3.5>
10873 23:04:55.096572 + cd /lava-12154372/1/tests/1_bootrr
10874 23:04:55.096920 + cat uuid
10875 23:04:55.097250 + UUID=12154372_1.5.2.3.5
10876 23:04:55.097578 + set +x
10877 23:04:55.097968 + export 'PATH=/opt/bootrr/libexec/bootrr/helpers:/lava-12154372/1/../bin:/sbin:/usr/sbin:/bin:/usr/bin'
10878 23:04:55.098584 Received signal: <STARTRUN> 1_bootrr 12154372_1.5.2.3.5
10879 23:04:55.098945 Starting test lava.1_bootrr (12154372_1.5.2.3.5)
10880 23:04:55.099354 Skipping test definition patterns.
10881 23:04:55.103294 <8>[ 17.143214] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=deferred-probe-empty RESULT=pass>
10882 23:04:55.104013 Received signal: <TESTCASE> TEST_CASE_ID=deferred-probe-empty RESULT=pass
10884 23:04:55.106560
10885 23:04:55.107118 + cd /opt/bootrr/libexec/bootrr
10886 23:04:55.110311 + sh helpers/bootrr-auto
10887 23:04:55.113247 /lava-12154372/1/../bin/lava-test-case
10888 23:04:55.123039 /lava-121543<8>[ 17.161200] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=all-cpus-are-online RESULT=pass>
10889 23:04:55.123613 72/1/../bin/lava-test-case
10890 23:04:55.124321 Received signal: <TESTCASE> TEST_CASE_ID=all-cpus-are-online RESULT=pass
10892 23:04:55.127277 /usr/bin/tpm2_getcap
10893 23:04:55.159527 /lava-12154372/1/../bin/lava-test-case
10894 23:04:55.166006 <8>[ 17.206398] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm-chip-is-online RESULT=pass>
10895 23:04:55.166874 Received signal: <TESTCASE> TEST_CASE_ID=tpm-chip-is-online RESULT=pass
10897 23:04:55.183281 /lava-12154372/1/../bin/lava-test-case
10898 23:04:55.190462 <8>[ 17.228784] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass>
10899 23:04:55.191350 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass
10901 23:04:55.201606 /lava-12154372/1/../bin/lava-test-case
10902 23:04:55.207870 <8>[ 17.247316] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass>
10903 23:04:55.208723 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass
10905 23:04:55.218988 /lava-12154372/1/../bin/lava-test-case
10906 23:04:55.225386 <8>[ 17.265337] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass>
10907 23:04:55.226232 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass
10909 23:04:55.237399 /lava-12154372/1/../bin/lava-test-case
10910 23:04:55.244462 <8>[ 17.282828] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass>
10911 23:04:55.245320 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass
10913 23:04:55.255713 /lava-12154372/1/../bin/lava-test-case
10914 23:04:55.262270 <8>[ 17.301182] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass>
10915 23:04:55.263166 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass
10917 23:04:55.271241 /lava-12154372/1/../bin/lava-test-case
10918 23:04:55.278000 <8>[ 17.316480] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass>
10919 23:04:55.278904 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass
10921 23:04:55.288929 /lava-12154372/1/../bin/lava-test-case
10922 23:04:55.294961 <8>[ 17.334277] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass>
10923 23:04:55.295742 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass
10925 23:04:55.304152 /lava-12154372/1/../bin/lava-test-case
10926 23:04:55.310755 <8>[ 17.349850] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass>
10927 23:04:55.311593 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass
10929 23:04:55.321459 /lava-12154372/1/../bin/lava-test-case
10930 23:04:55.328063 <8>[ 17.367069] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass>
10931 23:04:55.328907 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass
10933 23:04:55.339318 /lava-12154372/1/../bin/lava-test-case
10934 23:04:55.345367 <8>[ 17.384513] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass>
10935 23:04:55.346209 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass
10937 23:04:55.363379 /lava-12154372/1/../bin/lava-tes<8>[ 17.401553] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass>
10938 23:04:55.363952 t-case
10939 23:04:55.364596 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass
10941 23:04:55.374469 /lava-12154372/1/../bin/lava-test-case
10942 23:04:55.381015 <8>[ 17.419577] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass>
10943 23:04:55.381860 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass
10945 23:04:55.390639 /lava-12154372/1/../bin/lava-test-case
10946 23:04:55.397052 <8>[ 17.436833] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass>
10947 23:04:55.397896 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass
10949 23:04:55.414885 /lava-12154372/1/../bin/lava-tes<8>[ 17.452827] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass>
10950 23:04:55.415451 t-case
10951 23:04:55.416087 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass
10953 23:04:55.430422 /lava-12154372/1/../bin/lava-tes<8>[ 17.467650] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass>
10954 23:04:55.431028 t-case
10955 23:04:55.431727 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass
10957 23:04:55.449050 /lava-12154372/1/../bin/lava-tes<8>[ 17.486976] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass>
10958 23:04:55.449623 t-case
10959 23:04:55.450261 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass
10961 23:04:55.455681 /lava-12154372/1/../bin/lava-test-case
10962 23:04:55.462670 <8>[ 17.501907] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass>
10963 23:04:55.463508 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass
10965 23:04:55.477295 /lava-12154372/1/../bin/lava-tes<8>[ 17.518470] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-probed RESULT=pass>
10966 23:04:55.478313 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-probed RESULT=pass
10968 23:04:55.480154 t-case
10969 23:04:55.495424 /lava-12154372/1/../bin/lava-tes<8>[ 17.533566] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass>
10970 23:04:55.495900 t-case
10971 23:04:55.496523 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass
10973 23:04:55.507071 /lava-12154372/1/../bin/lava-test-case
10974 23:04:55.513813 <8>[ 17.552637] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass>
10975 23:04:55.514684 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass
10977 23:04:55.527704 /lava-12154372/1/../bin/lava-tes<8>[ 17.565717] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass>
10978 23:04:55.528276 t-case
10979 23:04:55.528905 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass
10981 23:04:55.540674 /lava-12154372/1/../bin/lava-test-case
10982 23:04:55.547457 <8>[ 17.586161] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass>
10983 23:04:55.548307 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass
10985 23:04:55.558802 /lava-12154372/1/../bin/lava-test-case
10986 23:04:55.565388 <8>[ 17.605178] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass>
10987 23:04:55.566230 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass
10989 23:04:55.574116 /lava-12154372/1/../bin/lava-test-case
10990 23:04:55.580097 <8>[ 17.620212] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass>
10991 23:04:55.580952 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass
10993 23:04:55.593112 /lava-12154372/1/../bin/lava-test-case
10994 23:04:55.599169 <8>[ 17.638524] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass>
10995 23:04:55.600015 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass
10997 23:04:55.615005 /lava-12154372/1/../bin/lava-tes<8>[ 17.653380] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass>
10998 23:04:55.615582 t-case
10999 23:04:55.616230 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass
11001 23:04:55.624118 /lava-12154372/1/../bin/lava-test-case
11002 23:04:55.630446 <8>[ 17.669973] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass>
11003 23:04:55.631500 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass
11005 23:04:55.641732 /lava-12154372/1/../bin/lava-test-case
11006 23:04:55.648255 <8>[ 17.686887] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass>
11007 23:04:55.649096 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass
11009 23:04:55.665013 /lava-12154372/1/../bin/lava-tes<8>[ 17.703362] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass>
11010 23:04:55.665578 t-case
11011 23:04:55.666206 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass
11013 23:04:55.683075 /lava-12154372/1/../bin/lava-tes<8>[ 17.720992] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass>
11014 23:04:55.683649 t-case
11015 23:04:55.684356 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass
11017 23:04:55.690608 /lava-12154372/1/../bin/lava-test-case
11018 23:04:55.697262 <8>[ 17.736157] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass>
11019 23:04:55.698107 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass
11021 23:04:55.714088 /lava-12154372/1/../bin/lava-tes<8>[ 17.752311] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass>
11022 23:04:55.714695 t-case
11023 23:04:55.715330 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass
11025 23:04:55.732056 /lava-12154372/1/../bin/lava-tes<8>[ 17.770037] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass>
11026 23:04:55.732625 t-case
11027 23:04:55.733347 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass
11029 23:04:55.746792 /lava-12154372/1/../bin/lava-tes<8>[ 17.785188] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass>
11030 23:04:55.747352 t-case
11031 23:04:55.747981 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass
11033 23:04:55.755680 /lava-12154372/1/../bin/lava-test-case
11034 23:04:55.766081 <8>[ 17.805112] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass>
11035 23:04:55.766964 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass
11037 23:04:55.781598 /lava-12154372/1/../bin/lava-tes<8>[ 17.819916] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass>
11038 23:04:55.782177 t-case
11039 23:04:55.782865 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass
11041 23:04:55.790647 /lava-12154372/1/../bin/lava-test-case
11042 23:04:55.796930 <8>[ 17.838100] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass>
11043 23:04:55.797748 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass
11045 23:04:55.807112 /lava-12154372/1/../bin/lava-test-case
11046 23:04:55.813637 <8>[ 17.852570] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass>
11047 23:04:55.814505 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass
11049 23:04:55.823827 /lava-12154372/1/../bin/lava-test-case
11050 23:04:55.830479 <8>[ 17.870249] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass>
11051 23:04:55.831322 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass
11053 23:04:55.838342 /lava-12154372/1/../bin/lava-test-case
11054 23:04:55.845186 <8>[ 17.884680] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass>
11055 23:04:55.846035 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass
11057 23:04:55.856216 /lava-12154372/1/../bin/lava-test-case
11058 23:04:55.862925 <8>[ 17.901997] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-probed RESULT=pass>
11059 23:04:55.863784 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-probed RESULT=pass
11061 23:04:55.879350 /lava-12154372/1/../bin/lava-tes<8>[ 17.917394] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass>
11062 23:04:55.879939 t-case
11063 23:04:55.880583 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass
11065 23:04:55.887380 /lava-12154372/1/../bin/lava-test-case
11066 23:04:55.894558 <8>[ 17.934504] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass>
11067 23:04:55.895411 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass
11069 23:04:55.910886 /lava-12154372/1/../bin/lava-tes<8>[ 17.948837] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass>
11070 23:04:55.911460 t-case
11071 23:04:55.912102 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass
11073 23:04:55.919780 /lava-12154372/1/../bin/lava-test-case
11074 23:04:55.926267 <8>[ 17.966099] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-probed RESULT=pass>
11075 23:04:55.927151 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-probed RESULT=pass
11077 23:04:55.941796 /lava-12154372/1/../bin/lava-tes<8>[ 17.979488] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass>
11078 23:04:55.942377 t-case
11079 23:04:55.943081 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass
11081 23:04:55.961304 /lava-12154372/1/../bin/lava-tes<8>[ 17.998956] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass>
11082 23:04:55.961876 t-case
11083 23:04:55.962525 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass
11085 23:04:55.969436 /lava-12154372/1/../bin/lava-test-case
11086 23:04:55.976085 <8>[ 18.016041] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass>
11087 23:04:55.976930 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass
11089 23:04:55.993095 /lava-12154372/1/../bin/lava-tes<8>[ 18.031212] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass>
11090 23:04:55.993654 t-case
11091 23:04:55.994295 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass
11093 23:04:56.002484 /lava-12154372/1/../bin/lava-test-case
11094 23:04:56.008179 <8>[ 18.048134] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass>
11095 23:04:56.009022 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass
11097 23:04:56.024276 /lava-12154372/1/../bin/lava-tes<8>[ 18.062391] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass>
11098 23:04:56.024860 t-case
11099 23:04:56.025508 Received signal: <TESTCASE> TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass
11101 23:04:56.034858 /lava-12154372/1/../bin/lava-test-case
11102 23:04:56.041636 <8>[ 18.081318] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass>
11103 23:04:56.042519 Received signal: <TESTCASE> TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass
11105 23:04:56.053048 /lava-12154372/1/../bin/lava-test-case
11106 23:04:56.059534 <8>[ 18.099126] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass>
11107 23:04:56.060374 Received signal: <TESTCASE> TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass
11109 23:04:56.069904 /lava-12154372/1/../bin/lava-test-case
11110 23:04:56.076561 <8>[ 18.116020] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass>
11111 23:04:56.077400 Received signal: <TESTCASE> TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass
11113 23:04:56.086201 /lava-12154372/1/../bin/lava-test-case
11114 23:04:56.093070 <8>[ 18.132003] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass>
11115 23:04:56.093922 Received signal: <TESTCASE> TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass
11117 23:04:56.103401 /lava-12154372/1/../bin/lava-test-case
11118 23:04:56.110293 <8>[ 18.149190] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass>
11119 23:04:56.111165 Received signal: <TESTCASE> TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass
11121 23:04:56.117562 /lava-12154372/1/../bin/lava-test-case
11122 23:04:56.127742 <8>[ 18.166813] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-driver-present RESULT=pass>
11123 23:04:56.128592 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-driver-present RESULT=pass
11125 23:04:56.134596 /lava-12154372/1/../bin/lava-test-case
11126 23:04:56.144683 <8>[ 18.184191] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi1-probed RESULT=pass>
11127 23:04:56.145524 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi1-probed RESULT=pass
11129 23:04:56.154049 /lava-12154372/1/../bin/lava-test-case
11130 23:04:56.160474 <8>[ 18.199761] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi5-probed RESULT=pass>
11131 23:04:56.161303 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi5-probed RESULT=pass
11133 23:04:56.175816 /lava-12154372/1/../bin/lava-tes<8>[ 18.213932] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass>
11134 23:04:56.176403 t-case
11135 23:04:56.177054 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass
11137 23:04:56.193097 /lava-12154372/1/../bin/lava-tes<8>[ 18.230957] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-probed RESULT=pass>
11138 23:04:56.193682 t-case
11139 23:04:56.194328 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-probed RESULT=pass
11141 23:04:56.208163 /lava-12154372/1/../bin/lava-tes<8>[ 18.246436] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass>
11142 23:04:56.208738 t-case
11143 23:04:56.209385 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass
11145 23:04:56.225027 /lava-12154372/1/../bin/lava-tes<8>[ 18.263325] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-probed RESULT=pass>
11146 23:04:56.225605 t-case
11147 23:04:56.226247 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-probed RESULT=pass
11149 23:04:56.241092 /lava-12154372/1/../bin/lava-tes<8>[ 18.279271] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass>
11150 23:04:56.241663 t-case
11151 23:04:56.242303 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass
11153 23:04:56.251901 /lava-12154372/1/../bin/lava-test-case
11154 23:04:56.258012 <8>[ 18.297232] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass>
11155 23:04:56.258998 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass
11157 23:04:56.267049 /lava-12154372/1/../bin/lava-test-case
11158 23:04:56.274093 <8>[ 18.313750] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass>
11159 23:04:56.274996 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass
11161 23:04:56.292562 /lava-12154372/1/../bin/lava-tes<8>[ 18.330685] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass>
11162 23:04:56.293139 t-case
11163 23:04:56.293861 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass
11165 23:04:56.304990 /lava-12154372/1/../bin/lava-test-case
11166 23:04:56.310906 <8>[ 18.351091] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass>
11167 23:04:56.311768 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass
11169 23:04:56.321911 /lava-12154372/1/../bin/lava-test-case
11170 23:04:56.328289 <8>[ 18.367826] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass>
11171 23:04:56.329162 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass
11173 23:04:56.338240 /lava-12154372/1/../bin/lava-test-case
11174 23:04:56.345018 <8>[ 18.383791] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass>
11175 23:04:56.345857 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass
11177 23:04:56.353515 /lava-12154372/1/../bin/lava-test-case
11178 23:04:56.360300 <8>[ 18.401024] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass>
11179 23:04:56.361138 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass
11181 23:04:56.379984 /lava-12154372/1/../bin/lava-tes<8>[ 18.418263] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass>
11182 23:04:56.380566 t-case
11183 23:04:56.381204 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass
11185 23:04:56.390324 /lava-12154372/1/../bin/lava-test-case
11186 23:04:56.397167 <8>[ 18.438011] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass>
11187 23:04:56.398044 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass
11189 23:04:56.408783 /lava-12154372/1/../bin/lava-test-case
11190 23:04:56.418905 <8>[ 18.457990] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass>
11191 23:04:56.419758 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass
11193 23:04:56.428355 /lava-12154372/1/../bin/lava-test-case
11194 23:04:56.435268 <8>[ 18.474164] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass>
11195 23:04:56.436360 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass
11197 23:04:56.454204 /lava-12154372/1/../bin/lava-tes<8>[ 18.492675] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass>
11198 23:04:56.454860 t-case
11199 23:04:56.455510 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass
11201 23:04:56.470850 /lava-12154372/1/../bin/lava-tes<8>[ 18.509041] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass>
11202 23:04:56.471427 t-case
11203 23:04:56.472072 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass
11205 23:04:56.481961 /lava-12154372/1/../bin/lava-test-case
11206 23:04:56.488511 <8>[ 18.528790] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass>
11207 23:04:56.489378 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass
11209 23:04:56.498132 /lava-12154372/1/../bin/lava-test-case
11210 23:04:56.504656 <8>[ 18.543857] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass>
11211 23:04:56.505489 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass
11213 23:04:56.512218 /lava-12154372/1/../bin/lava-test-case
11214 23:04:56.518764 <8>[ 18.558002] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass>
11215 23:04:56.519597 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass
11217 23:04:56.531584 /lava-12154372/1/../bin/lava-test-case
11218 23:04:56.537955 <8>[ 18.577641] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-probed RESULT=pass>
11219 23:04:56.538680 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-probed RESULT=pass
11221 23:04:56.545747 /lava-12154372/1/../bin/lava-test-case
11222 23:04:56.553735 <8>[ 18.591144] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass>
11223 23:04:56.554574 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass
11225 23:04:56.562271 /lava-12154372/1/../bin/lava-test-case
11226 23:04:56.568866 <8>[ 18.607905] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-probed RESULT=pass>
11227 23:04:56.569708 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-probed RESULT=pass
11229 23:04:56.576275 /lava-12154372/1/../bin/lava-test-case
11230 23:04:56.585916 <8>[ 18.623664] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass>
11231 23:04:56.586840 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass
11233 23:04:56.594095 /lava-12154372/1/../bin/lava-test-case
11234 23:04:56.600846 <8>[ 18.640863] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass>
11235 23:04:56.601686 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass
11237 23:04:56.609520 /lava-12154372/1/../bin/lava-test-case
11238 23:04:56.616255 <8>[ 18.655196] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass>
11239 23:04:56.617093 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass
11241 23:04:56.625771 /lava-12154372/1/../bin/lava-test-case
11242 23:04:56.635280 <8>[ 18.674773] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-probed RESULT=pass>
11243 23:04:56.636120 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-probed RESULT=pass
11245 23:04:56.642863 /lava-12154372/1/../bin/lava-test-case
11246 23:04:56.649560 <8>[ 18.688395] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass>
11247 23:04:56.650424 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass
11249 23:04:56.660037 /lava-12154372/1/../bin/lava-test-case
11250 23:04:56.666800 <8>[ 18.705954] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass>
11251 23:04:56.667639 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass
11253 23:04:56.674338 /lava-12154372/1/../bin/lava-test-case
11254 23:04:56.684217 <8>[ 18.721951] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass>
11255 23:04:56.685060 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass
11257 23:04:56.693725 /lava-12154372/1/../bin/lava-test-case
11258 23:04:56.699726 <8>[ 18.740509] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass>
11259 23:04:56.700511 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass
11261 23:04:56.710368 /lava-12154372/1/../bin/lava-test-case
11262 23:04:56.716996 <8>[ 18.756859] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass>
11263 23:04:56.717846 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass
11265 23:04:56.725506 /lava-12154372/1/../bin/lava-test-case
11266 23:04:56.732566 <8>[ 18.771079] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass>
11267 23:04:56.733421 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass
11269 23:04:56.741533 /lava-12154372/1/../bin/lava-test-case
11270 23:04:56.751599 <8>[ 18.790956] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass>
11271 23:04:56.752441 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass
11273 23:04:56.759358 /lava-12154372/1/../bin/lava-test-case
11274 23:04:56.765965 <8>[ 18.805978] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-driver-present RESULT=pass>
11275 23:04:56.766840 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-driver-present RESULT=pass
11277 23:04:56.775524 /lava-12154372/1/../bin/lava-test-case
11278 23:04:56.781992 <8>[ 18.822049] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-probed RESULT=pass>
11279 23:04:56.782866 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-probed RESULT=pass
11281 23:04:56.789692 /lava-12154372/1/../bin/lava-test-case
11282 23:04:56.796223 <8>[ 18.837267] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-driver-present RESULT=pass>
11283 23:04:56.797063 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-driver-present RESULT=pass
11285 23:04:57.814074 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-probed RESULT=fail
11287 23:04:57.816689 /lava-12154372/1/../bin/lava-tes<8>[ 19.855619] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-probed RESULT=fail>
11288 23:04:57.817260 t-case
11289 23:04:57.826604 /lava-12154372/1/../bin/lava-test-case
11290 23:04:57.833073 <8>[ 19.874425] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-driver-present RESULT=pass>
11291 23:04:57.833916 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-driver-present RESULT=pass
11293 23:04:58.853747 /lava-12154372/1/../bin/lava-tes<8>[ 20.892275] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-probed RESULT=fail>
11294 23:04:58.854332 t-case
11295 23:04:58.855049 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-probed RESULT=fail
11297 23:04:58.871372 /lava-12154372/1/../bin/lava-tes<8>[ 20.910309] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass>
11298 23:04:58.871539 t-case
11299 23:04:58.871798 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass
11301 23:04:59.891368 /lava-12154372/1/../bin/lava-tes<8>[ 21.930359] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail>
11302 23:04:59.892013 t-case
11303 23:04:59.892662 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail
11305 23:04:59.901860 /lava-12154372/1/../bin/lava-test-case
11306 23:04:59.907631 <8>[ 21.947537] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass>
11307 23:04:59.908490 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass
11309 23:05:00.923130 /lava-12154372/1/../bin/lava-tes<8>[ 22.965521] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-probed RESULT=fail>
11310 23:05:00.923975 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-probed RESULT=fail
11312 23:05:00.926181 t-case
11313 23:05:00.941667 /lava-12154372/1/../bin/lava-tes<8>[ 22.980465] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-driver-present RESULT=pass>
11314 23:05:00.942246 t-case
11315 23:05:00.942945 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-driver-present RESULT=pass
11317 23:05:01.958537 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-3-probed RESULT=fail
11319 23:05:01.961204 /lava-12154372/1/../bin/lava-tes<8>[ 24.000193] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-3-probed RESULT=fail>
11320 23:05:01.961776 t-case
11321 23:05:01.969931 /lava-12154372/1/../bin/lava-test-case
11322 23:05:01.976715 <8>[ 24.016702] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass>
11323 23:05:01.977559 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass
11325 23:05:02.996438 /lava-12154372/1/../bin/lava-tes<8>[ 25.035858] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail>
11326 23:05:02.997007 t-case
11327 23:05:02.997647 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail
11329 23:05:03.005805 /lava-12154372/1/../bin/lava-test-case
11330 23:05:03.012299 <8>[ 25.052938] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass>
11331 23:05:03.013215 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass
11333 23:05:04.032323 /lava-12154372/1/../bin/lava-tes<8>[ 26.072094] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-probed RESULT=fail>
11334 23:05:04.032894 t-case
11335 23:05:04.033523 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-probed RESULT=fail
11337 23:05:04.042173 /lava-12154372/1/../bin/lava-test-case
11338 23:05:04.048455 <8>[ 26.089043] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-edp-driver-present RESULT=pass>
11339 23:05:04.049284 Received signal: <TESTCASE> TEST_CASE_ID=panel-edp-driver-present RESULT=pass
11341 23:05:04.058063 /lava-12154372/1/../bin/lava-test-case
11342 23:05:04.064880 <8>[ 26.104410] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass>
11343 23:05:04.065712 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass
11345 23:05:05.078890 /lava-12154372/1/../bin/lava-test-case
11346 23:05:05.085244 <8>[ 27.126316] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail>
11347 23:05:05.086084 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail
11349 23:05:05.094801 /lava-12154372/1/../bin/lava-test-case
11350 23:05:05.101392 <8>[ 27.142003] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass>
11351 23:05:05.102227 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass
11353 23:05:05.112813 /lava-12154372/1/../bin/lava-test-case
11354 23:05:05.119398 <8>[ 27.159433] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-probed RESULT=pass>
11355 23:05:05.120232 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-probed RESULT=pass
11357 23:05:05.128521 /lava-12154372/1/../bin/lava-test-case
11358 23:05:05.135068 <8>[ 27.174719] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass>
11359 23:05:05.135920 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass
11361 23:05:05.155754 /lava-12154372/1/../bin/lava-tes<8>[ 27.194945] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass>
11362 23:05:05.156328 t-case
11363 23:05:05.156979 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass
11365 23:05:05.164495 /lava-12154372/1/../bin/lava-test-case
11366 23:05:05.170599 <8>[ 27.212087] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass>
11367 23:05:05.171404 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass
11369 23:05:05.189896 /lava-12154372/1/../bin/lava-tes<8>[ 27.229212] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass>
11370 23:05:05.190493 t-case
11371 23:05:05.191134 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass
11373 23:05:05.197847 /lava-12154372/1/../bin/lava-test-case
11374 23:05:05.203730 <8>[ 27.243872] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass>
11375 23:05:05.204546 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass
11377 23:05:05.224030 /lava-12154372/1/../bin/lava-tes<8>[ 27.263033] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass>
11378 23:05:05.224602 t-case
11379 23:05:05.225248 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass
11381 23:05:05.241633 /lava-12154372/1/../bin/lava-tes<8>[ 27.280740] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass>
11382 23:05:05.242231 t-case
11383 23:05:05.242912 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass
11385 23:05:05.257540 /lava-12154372/1/../bin/lava-tes<8>[ 27.296446] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass>
11386 23:05:05.258115 t-case
11387 23:05:05.258812 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass
11389 23:05:05.270151 /lava-12154372/1/../bin/lava-test-case
11390 23:05:05.276910 <8>[ 27.318027] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass>
11391 23:05:05.277779 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass
11393 23:05:05.285437 /lava-12154372/1/../bin/lava-test-case
11394 23:05:05.291584 <8>[ 27.332100] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass>
11395 23:05:05.292319 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass
11397 23:05:05.303823 /lava-12154372/1/../bin/lava-test-case
11398 23:05:05.310348 <8>[ 27.350361] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass>
11399 23:05:05.311268 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass
11401 23:05:05.325149 /lava-12154372/1/../bin/lava-tes<8>[ 27.364324] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass>
11402 23:05:05.325725 t-case
11403 23:05:05.326364 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass
11405 23:05:05.340577 /lava-12154372/1/../bin/lava-test-case
11406 23:05:05.346912 <8>[ 27.388710] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass>
11407 23:05:05.347761 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass
11409 23:05:05.356334 /lava-12154372/1/../bin/lava-test-case
11410 23:05:05.362836 <8>[ 27.402882] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass>
11411 23:05:05.363703 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass
11413 23:05:05.374992 /lava-12154372/1/../bin/lava-test-case
11414 23:05:05.381238 <8>[ 27.421587] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass>
11415 23:05:05.382077 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass
11417 23:05:05.389373 /lava-12154372/1/../bin/lava-test-case
11418 23:05:05.395487 <8>[ 27.435880] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass>
11419 23:05:05.396308 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass
11421 23:05:05.404980 /lava-12154372/1/../bin/lava-test-case
11422 23:05:05.415295 <8>[ 27.455579] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-probed RESULT=pass>
11423 23:05:05.416342 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-probed RESULT=pass
11425 23:05:05.422612 /lava-12154372/1/../bin/lava-test-case
11426 23:05:05.429006 <8>[ 27.469476] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass>
11427 23:05:05.429847 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass
11429 23:05:06.448615 /lava-12154372/1/../bin/lava-tes<8>[ 28.488760] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-probed RESULT=fail>
11430 23:05:06.449184 t-case
11431 23:05:06.449820 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-probed RESULT=fail
11433 23:05:07.462444 /lava-12154372/1/../bin/lava-test-case
11434 23:05:07.469077 <8>[ 29.510350] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-7-probed RESULT=fail>
11435 23:05:07.469931 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-7-probed RESULT=fail
11437 23:05:07.476897 /lava-12154372/1/../bin/lava-test-case
11438 23:05:07.484014 <8>[ 29.523841] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-driver-present RESULT=pass>
11439 23:05:07.484919 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-driver-present RESULT=pass
11441 23:05:07.502193 /lava-12154372/1/../bin/lava-tes<8>[ 29.541668] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-probed RESULT=pass>
11442 23:05:07.503083 t-case
11443 23:05:07.503762 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-probed RESULT=pass
11445 23:05:07.518344 /lava-12154372/1/../bin/lava-tes<8>[ 29.558323] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass>
11446 23:05:07.518971 t-case
11447 23:05:07.519622 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass
11449 23:05:07.537062 /lava-12154372/1/../bin/lava-tes<8>[ 29.576571] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass>
11450 23:05:07.537635 t-case
11451 23:05:07.538276 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass
11453 23:05:07.551990 /lava-12154372/1/../bin/lava-tes<8>[ 29.591570] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-driver-present RESULT=pass>
11454 23:05:07.552567 t-case
11455 23:05:07.553208 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-driver-present RESULT=pass
11457 23:05:07.563242 /lava-12154372/1/../bin/lava-test-case
11458 23:05:07.568940 <8>[ 29.609842] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-probed RESULT=pass>
11459 23:05:07.569786 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-probed RESULT=pass
11461 23:05:07.577578 /lava-12154372/1/../bin/lava-test-case
11462 23:05:07.584334 <8>[ 29.624663] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass>
11463 23:05:07.585159 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass
11465 23:05:07.602657 /lava-12154372/1/../bin/lava-tes<8>[ 29.642247] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass>
11466 23:05:07.603375 t-case
11467 23:05:07.604159 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass
11469 23:05:07.617347 /lava-12154372/1/../bin/lava-tes<8>[ 29.656687] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass>
11470 23:05:07.617925 t-case
11471 23:05:07.618568 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass
11473 23:05:07.632684 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-probed RESULT=pass
11475 23:05:07.635007 /lava-12154372/1/../bin/lava-tes<8>[ 29.674622] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-probed RESULT=pass>
11476 23:05:07.635478 t-case
11477 23:05:07.643691 /lava-12154372/1/../bin/lava-test-case
11478 23:05:07.649697 <8>[ 29.689970] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass>
11479 23:05:07.650527 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass
11481 23:05:07.668336 /lava-12154372/1/../bin/lava-tes<8>[ 29.707833] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass>
11482 23:05:07.668915 t-case
11483 23:05:07.669554 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass
11485 23:05:07.683090 /lava-12154372/1/../bin/lava-tes<8>[ 29.722308] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass>
11486 23:05:07.683712 t-case
11487 23:05:07.684365 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass
11489 23:05:07.694945 /lava-12154372/1/../bin/lava-tes<8>[ 29.737508] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-probed RESULT=pass>
11490 23:05:07.695791 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-probed RESULT=pass
11492 23:05:07.698247 t-case
11493 23:05:07.713278 /lava-12154372/1/../bin/lava-tes<8>[ 29.753029] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass>
11494 23:05:07.713853 t-case
11495 23:05:07.714524 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass
11497 23:05:07.726502 /lava-12154372/1/../bin/lava-tes<8>[ 29.769130] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-probed RESULT=pass>
11498 23:05:07.727331 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-probed RESULT=pass
11500 23:05:07.729702 t-case
11501 23:05:07.745754 /lava-12154372/1/../bin/lava-tes<8>[ 29.784836] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-driver-present RESULT=pass>
11502 23:05:07.746330 t-case
11503 23:05:07.747007 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-driver-present RESULT=pass
11505 23:05:07.753399 /lava-12154372/1/../bin/lava-test-case
11506 23:05:07.760197 <8>[ 29.800327] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-probed RESULT=pass>
11507 23:05:07.761036 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-probed RESULT=pass
11509 23:05:07.776282 /lava-12154372/1/../bin/lava-tes<8>[ 29.815909] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass>
11510 23:05:07.776849 t-case
11511 23:05:07.777475 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass
11513 23:05:07.794637 /lava-12154372/1/../bin/lava-tes<8>[ 29.833821] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass>
11514 23:05:07.795210 t-case
11515 23:05:07.795858 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass
11517 23:05:08.804890 /lava-12154372/1/../bin/lava-test-case
11518 23:05:08.811152 <8>[ 30.852747] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail>
11519 23:05:08.811996 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail
11521 23:05:09.828238 /lava-12154372/1/../bin/lava-tes<8>[ 31.868351] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked>
11522 23:05:09.828813 t-case
11523 23:05:09.829449 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked
11524 23:05:09.829903 Bad test result: blocked
11525 23:05:09.844321 /lava-12154372/1/../bin/lava-tes<8>[ 31.884301] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-driver-present RESULT=pass>
11526 23:05:09.844493 t-case
11527 23:05:09.844756 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-driver-present RESULT=pass
11529 23:05:10.862825 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-probed RESULT=fail
11531 23:05:10.865995 /lava-12154372/1/../bin/lava-tes<8>[ 32.905955] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-probed RESULT=fail>
11532 23:05:10.866603 t-case
11533 23:05:10.884419 /lava-12154372/1/../bin/lava-tes<8>[ 32.924282] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo-driver-present RESULT=pass>
11534 23:05:10.884999 t-case
11535 23:05:10.885641 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo-driver-present RESULT=pass
11537 23:05:10.895384 /lava-12154372/1/../bin/lava-test-case
11538 23:05:10.902280 <8>[ 32.942987] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo0-probed RESULT=pass>
11539 23:05:10.903157 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo0-probed RESULT=pass
11541 23:05:10.917765 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo1-probed RESULT=pass
11543 23:05:10.920921 /lava-12154372/1/../bin/lava-tes<8>[ 32.960883] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo1-probed RESULT=pass>
11544 23:05:10.921498 t-case
11545 23:05:10.935403 /lava-12154372/1/../bin/lava-tes<8>[ 32.975474] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass>
11546 23:05:10.935988 t-case
11547 23:05:10.936630 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass
11549 23:05:10.953213 /lava-12154372/1/../bin/lava-tes<8>[ 32.993125] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-probed RESULT=pass>
11550 23:05:10.953803 t-case
11551 23:05:10.954474 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-probed RESULT=pass
11553 23:05:10.961885 /lava-12154372/1/../bin/lava-test-case
11554 23:05:10.968836 <8>[ 33.009167] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-driver-present RESULT=pass>
11555 23:05:10.969676 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-driver-present RESULT=pass
11557 23:05:11.985192 /lava-12154372/1/../bin/lava-test-case
11558 23:05:11.992251 <8>[ 34.033754] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-probed RESULT=fail>
11559 23:05:11.993101 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-probed RESULT=fail
11561 23:05:12.001024 /lava-12154372/1/../bin/lava-test-case
11562 23:05:12.007773 <8>[ 34.048887] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-driver-present RESULT=pass>
11563 23:05:12.008611 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-driver-present RESULT=pass
11565 23:05:13.021423 /lava-12154372/1/../bin/lava-test-case
11566 23:05:13.027938 <8>[ 35.068753] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-probed RESULT=fail>
11567 23:05:13.028779 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-probed RESULT=fail
11569 23:05:13.043702 /lava-12154372/1/../bin/lava-tes<8>[ 35.084037] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-driver-present RESULT=pass>
11570 23:05:13.044277 t-case
11571 23:05:13.044918 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-driver-present RESULT=pass
11573 23:05:14.055538 /lava-12154372/1/../bin/lava-test-case
11574 23:05:14.061515 <8>[ 36.103592] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-probed RESULT=fail>
11575 23:05:14.062363 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-probed RESULT=fail
11577 23:05:14.070133 /lava-12154372/1/../bin/lava-test-case
11578 23:05:14.077250 <8>[ 36.117672] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass>
11579 23:05:14.078091 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass
11581 23:05:15.092937 /lava-12154372/1/../bin/lava-test-case
11582 23:05:15.099423 <8>[ 37.141763] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail>
11583 23:05:15.099717 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail
11585 23:05:15.108334 /lava-12154372/1/../bin/lava-test-case
11586 23:05:15.115079 <8>[ 37.156988] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb-driver-present RESULT=pass>
11587 23:05:15.115444 Received signal: <TESTCASE> TEST_CASE_ID=btusb-driver-present RESULT=pass
11589 23:05:15.129860 /lava-12154372/1/../bin/lava-test-case
11590 23:05:15.136791 <8>[ 37.178972] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb0-probed RESULT=pass>
11591 23:05:15.137217 Received signal: <TESTCASE> TEST_CASE_ID=btusb0-probed RESULT=pass
11593 23:05:15.146681 /lava-12154372/1/../bin/lava-test-case
11594 23:05:15.153557 <8>[ 37.194893] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb1-probed RESULT=pass>
11595 23:05:15.154199 Received signal: <TESTCASE> TEST_CASE_ID=btusb1-probed RESULT=pass
11597 23:05:15.167016 /lava-12154372/1/../bin/lava-tes<8>[ 37.207608] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass>
11598 23:05:15.167566 t-case
11599 23:05:15.168188 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass
11601 23:05:15.181026 /lava-12154372/1/../bin/lava-tes<8>[ 37.224471] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-probed RESULT=pass>
11602 23:05:15.181869 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-probed RESULT=pass
11604 23:05:15.184162 t-case
11605 23:05:15.198438 /lava-12154372/1/../bin/lava-tes<8>[ 37.239124] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass>
11606 23:05:15.199030 t-case
11607 23:05:15.199670 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass
11609 23:05:15.216687 /lava-12154372/1/../bin/lava-tes<8>[ 37.257031] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-probed RESULT=pass>
11610 23:05:15.217267 t-case
11611 23:05:15.217918 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-probed RESULT=pass
11613 23:05:15.231994 /lava-12154372/1/../bin/lava-tes<8>[ 37.272595] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass>
11614 23:05:15.232581 t-case
11615 23:05:15.233231 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass
11617 23:05:15.253285 /lava-12154372/1/../bin/lava-tes<8>[ 37.293979] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass>
11618 23:05:15.253858 t-case
11619 23:05:15.254721 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass
11621 23:05:15.256579 + set +x
11622 23:05:15.259863 <8>[ 37.304522] <LAVA_SIGNAL_ENDRUN 1_bootrr 12154372_1.5.2.3.5>
11623 23:05:15.260617 Received signal: <ENDRUN> 1_bootrr 12154372_1.5.2.3.5
11624 23:05:15.261082 Ending use of test pattern.
11625 23:05:15.261523 Ending test lava.1_bootrr (12154372_1.5.2.3.5), duration 20.16
11627 23:05:15.263801 <LAVA_TEST_RUNNER EXIT>
11628 23:05:15.264535 ok: lava_test_shell seems to have completed
11629 23:05:15.270145 all-cpus-are-online: pass
anx7625-3-probed: fail
anx7625-7-probed: fail
anx7625-driver-present: pass
btusb-driver-present: pass
btusb0-probed: pass
btusb1-probed: pass
clk-mt8192-apmixedsys-probed: pass
clk-mt8192-aud-driver-present: pass
clk-mt8192-aud-probed: pass
clk-mt8192-cam-driver-present: pass
clk-mt8192-cam-probed: pass
clk-mt8192-cam_rawa-probed: pass
clk-mt8192-cam_rawb-probed: pass
clk-mt8192-cam_rawc-probed: pass
clk-mt8192-driver-present: pass
clk-mt8192-img-driver-present: pass
clk-mt8192-img-probed: pass
clk-mt8192-img2-probed: pass
clk-mt8192-imp_iic_wrap-driver-present: pass
clk-mt8192-imp_iic_wrap_e-probed: pass
clk-mt8192-imp_iic_wrap_n-probed: pass
clk-mt8192-imp_iic_wrap_s-probed: pass
clk-mt8192-imp_iic_wrap_ws-probed: pass
clk-mt8192-infracfg-probed: pass
clk-mt8192-ipe-driver-present: pass
clk-mt8192-ipe-probed: pass
clk-mt8192-mdp-driver-present: pass
clk-mt8192-mdp-probed: pass
clk-mt8192-mfg-driver-present: pass
clk-mt8192-mfg-probed: pass
clk-mt8192-mm-driver-present: pass
clk-mt8192-mm-probed: pass
clk-mt8192-msdc-driver-present: pass
clk-mt8192-msdc-probed: pass
clk-mt8192-pericfg-probed: pass
clk-mt8192-topckgen-probed: pass
clk-mt8192-vdec-driver-present: pass
clk-mt8192-vdec-probed: pass
clk-mt8192-vdec_soc-probed: pass
clk-mt8192-venc-driver-present: pass
clk-mt8192-venc-probed: pass
cros-ec-i2c-tunnel-driver-present: pass
cros-ec-i2c-tunnel-probed: pass
cros-ec-keyb-driver-present: pass
cros-ec-keyb-probed: pass
cros-ec-pwm-driver-present: pass
cros-ec-pwm-probed: pass
cros-ec-regulator-driver-present: pass
cros-ec-regulator0-probed: pass
cros-ec-regulator1-probed: pass
cros-ec-rpmsg-driver-present: pass
cros-ec-rpmsg-probed: pass
cros-ec-spi-driver-present: pass
cros-ec-spi-probed: pass
cros-ec-typec-driver-present: pass
cros-ec-typec-probed: pass
deferred-probe-empty: pass
dmic-codec-driver-present: pass
dmic-codec-probed: fail
elan_i2c-driver-present: pass
elan_i2c-probed: fail
elants_i2c-driver-present: pass
elants_i2c-probed: fail
i2c-mt65xx-driver-present: pass
i2c0-mt65xx-probed: pass
i2c1-mt65xx-probed: pass
i2c2-mt65xx-probed: pass
i2c3-mt65xx-probed: pass
i2c7-mt65xx-probed: pass
leds_pwm-driver-present: pass
leds_pwm-probed: pass
mediatek,efuse-driver-present: pass
mediatek,efuse-probed: pass
mediatek-disp-aal-driver-present: pass
mediatek-disp-aal-probed: pass
mediatek-disp-ccorr-driver-present: pass
mediatek-disp-ccorr-probed: pass
mediatek-disp-color-driver-present: pass
mediatek-disp-color-probed: pass
mediatek-disp-gamma-driver-present: pass
mediatek-disp-gamma-probed: pass
mediatek-disp-ovl-driver-present: pass
mediatek-disp-ovl0-probed: pass
mediatek-disp-ovl2l0-probed: pass
mediatek-disp-ovl2l2-probed: pass
mediatek-disp-pwm-driver-present: pass
mediatek-disp-pwm-probed: fail
mediatek-disp-rdma-driver-present: pass
mediatek-disp-rdma0-probed: pass
mediatek-disp-rdma4-probed: pass
mediatek-dpi-driver-present: pass
mediatek-dpi-probed: fail
mediatek-drm-driver-present: pass
mediatek-drm-probed: pass
mediatek-mipi-tx-driver-present: pass
mediatek-mipi-tx-probed: fail
mediatek-mutex-driver-present: pass
mediatek-mutex-probed: pass
mt-pmic-pwrap-driver-present: pass
mt-pmic-pwrap-probed: pass
mt6315-regulator-driver-present: pass
mt6315-regulator6-probed: pass
mt6315-regulator7-probed: pass
mt6577-uart-driver-present: pass
mt6577-uart-probed: pass
mt7921e-driver-present: pass
mt7921e-probed: pass
mt8192-audio-driver-present: pass
mt8192-audio-probed: pass
mt8192-pinctrl-driver-present: pass
mt8192-pinctrl-probed: pass
mt8192_mt6359-driver-present: pass
mt8192_mt6359-probed: fail
mtk-cpufreq-hw-driver-present: pass
mtk-cpufreq-hw-probed: pass
mtk-dsi-driver-present: pass
mtk-dsi-probed: fail
mtk-iommu-driver-present: pass
mtk-iommu-probed: pass
mtk-mmsys-driver-present: pass
mtk-mmsys-probed: pass
mtk-msdc-driver-present: pass
mtk-msdc-probed: pass
mtk-pcie-gen3-driver-present: pass
mtk-pcie-gen3-probed: pass
mtk-power-controller-driver-present: pass
mtk-power-controller-probed: pass
mtk-scp-driver-present: pass
mtk-scp-probed: pass
mtk-smi-common-driver-present: pass
mtk-smi-common-probed: pass
mtk-smi-larb-driver-present: pass
mtk-smi-larb0-probed: pass
mtk-smi-larb1-probed: pass
mtk-smi-larb11-probed: pass
mtk-smi-larb13-probed: pass
mtk-smi-larb14-probed: pass
mtk-smi-larb16-probed: pass
mtk-smi-larb17-probed: pass
mtk-smi-larb18-probed: pass
mtk-smi-larb19-probed: pass
mtk-smi-larb2-probed: pass
mtk-smi-larb20-probed: pass
mtk-smi-larb4-probed: pass
mtk-smi-larb5-probed: pass
mtk-smi-larb7-probed: pass
mtk-smi-larb9-probed: pass
mtk-spi-driver-present: pass
mtk-spi-nor-driver-present: pass
mtk-spi-nor-probed: pass
mtk-spi1-probed: pass
mtk-spi5-probed: pass
mtk-tphy-driver-present: pass
mtk-tphy-probed: pass
mtk-vcodec-dec-driver-present: fail
mtk-vcodec-enc-driver-present: pass
mtk-vcodec-enc-probed: pass
mtk-wdt-driver-present: pass
mtk-wdt-probed: pass
panel-edp-driver-present: pass
panel-simple-dp-aux-driver-present: pass
panel-simple-dp-aux-probed: fail
panfrost-driver-present: pass
panfrost-probed: fail
pwm-backlight-driver-present: pass
pwm-backlight-probed: fail
rt1015p-driver-present: pass
rt1015p-probed: fail
rt5682-driver-present: pass
rt5682-probed: fail
sbs-battery-driver-present: pass
sbs-battery-probed: pass
spmi-mtk-driver-present: pass
spmi-mtk-probed: pass
tpm-chip-is-online: pass
tpm_tis_spi-driver-present: pass
tpm_tis_spi-probed: pass
uvcvideo-driver-present: pass
uvcvideo0-probed: pass
uvcvideo1-probed: pass
xhci-mtk-driver-present: pass
xhci-mtk-probed: pass
11630 23:05:15.271005 end: 4.1 lava-test-shell (duration 00:00:21) [common]
11631 23:05:15.271587 end: 4 lava-test-retry (duration 00:00:21) [common]
11632 23:05:15.272172 start: 5 finalize (timeout 00:07:53) [common]
11633 23:05:15.272752 start: 5.1 power-off (timeout 00:00:30) [common]
11634 23:05:15.273686 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
11635 23:05:15.357483 >> Command sent successfully.
11636 23:05:15.361596 Returned 0 in 0 seconds
11637 23:05:15.462591 end: 5.1 power-off (duration 00:00:00) [common]
11639 23:05:15.464281 start: 5.2 read-feedback (timeout 00:07:53) [common]
11640 23:05:15.465629 Listened to connection for namespace 'common' for up to 1s
11641 23:05:16.466338 Finalising connection for namespace 'common'
11642 23:05:16.467107 Disconnecting from shell: Finalise
11643 23:05:16.467633 / #
11644 23:05:16.568816 end: 5.2 read-feedback (duration 00:00:01) [common]
11645 23:05:16.569571 end: 5 finalize (duration 00:00:01) [common]
11646 23:05:16.570279 Cleaning after the job
11647 23:05:16.571018 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12154372/tftp-deploy-61zxytub/ramdisk
11648 23:05:16.582816 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12154372/tftp-deploy-61zxytub/kernel
11649 23:05:16.609581 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12154372/tftp-deploy-61zxytub/dtb
11650 23:05:16.610055 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12154372/tftp-deploy-61zxytub/modules
11651 23:05:16.621088 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12154372
11652 23:05:16.663918 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12154372
11653 23:05:16.664111 Job finished correctly