Boot log: mt8192-asurada-spherion-r0
- Boot result: FAIL
- Warnings: 1
- Kernel Warnings: 26
- Kernel Errors: 37
- Errors: 3
1 23:01:54.137935 lava-dispatcher, installed at version: 2023.10
2 23:01:54.138137 start: 0 validate
3 23:01:54.138271 Start time: 2023-12-01 23:01:54.138263+00:00 (UTC)
4 23:01:54.138389 Using caching service: 'http://localhost/cache/?uri=%s'
5 23:01:54.138522 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 23:01:54.406164 Using caching service: 'http://localhost/cache/?uri=%s'
7 23:01:54.406380 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.64-cip10%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 23:02:21.418524 Using caching service: 'http://localhost/cache/?uri=%s'
9 23:02:21.419277 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.64-cip10%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 23:02:21.689103 Using caching service: 'http://localhost/cache/?uri=%s'
11 23:02:21.689834 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 23:02:22.218384 Using caching service: 'http://localhost/cache/?uri=%s'
13 23:02:22.219118 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.64-cip10%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 23:02:25.230480 validate duration: 31.09
16 23:02:25.230738 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 23:02:25.230840 start: 1.1 download-retry (timeout 00:10:00) [common]
18 23:02:25.230929 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 23:02:25.231104 Not decompressing ramdisk as can be used compressed.
20 23:02:25.231250 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/initrd.cpio.gz
21 23:02:25.231334 saving as /var/lib/lava/dispatcher/tmp/12154420/tftp-deploy-1s1l4ozf/ramdisk/initrd.cpio.gz
22 23:02:25.231403 total size: 4665412 (4 MB)
23 23:02:25.496890 progress 0 % (0 MB)
24 23:02:25.498449 progress 5 % (0 MB)
25 23:02:25.499723 progress 10 % (0 MB)
26 23:02:25.501047 progress 15 % (0 MB)
27 23:02:25.502381 progress 20 % (0 MB)
28 23:02:25.503626 progress 25 % (1 MB)
29 23:02:25.505030 progress 30 % (1 MB)
30 23:02:25.506376 progress 35 % (1 MB)
31 23:02:25.507657 progress 40 % (1 MB)
32 23:02:25.509097 progress 45 % (2 MB)
33 23:02:25.510396 progress 50 % (2 MB)
34 23:02:25.511780 progress 55 % (2 MB)
35 23:02:25.513116 progress 60 % (2 MB)
36 23:02:25.514577 progress 65 % (2 MB)
37 23:02:25.515886 progress 70 % (3 MB)
38 23:02:25.517167 progress 75 % (3 MB)
39 23:02:25.518519 progress 80 % (3 MB)
40 23:02:25.519930 progress 85 % (3 MB)
41 23:02:25.521211 progress 90 % (4 MB)
42 23:02:25.522496 progress 95 % (4 MB)
43 23:02:25.523755 progress 100 % (4 MB)
44 23:02:25.523910 4 MB downloaded in 0.29 s (15.21 MB/s)
45 23:02:25.524069 end: 1.1.1 http-download (duration 00:00:00) [common]
47 23:02:25.524356 end: 1.1 download-retry (duration 00:00:00) [common]
48 23:02:25.524445 start: 1.2 download-retry (timeout 00:10:00) [common]
49 23:02:25.524530 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 23:02:25.524694 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.64-cip10/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 23:02:25.524829 saving as /var/lib/lava/dispatcher/tmp/12154420/tftp-deploy-1s1l4ozf/kernel/Image
52 23:02:25.524923 total size: 49172992 (46 MB)
53 23:02:25.525001 No compression specified
54 23:02:25.526183 progress 0 % (0 MB)
55 23:02:25.539628 progress 5 % (2 MB)
56 23:02:25.553178 progress 10 % (4 MB)
57 23:02:25.566429 progress 15 % (7 MB)
58 23:02:25.579938 progress 20 % (9 MB)
59 23:02:25.593134 progress 25 % (11 MB)
60 23:02:25.606047 progress 30 % (14 MB)
61 23:02:25.619076 progress 35 % (16 MB)
62 23:02:25.632135 progress 40 % (18 MB)
63 23:02:25.645230 progress 45 % (21 MB)
64 23:02:25.658259 progress 50 % (23 MB)
65 23:02:25.671333 progress 55 % (25 MB)
66 23:02:25.684358 progress 60 % (28 MB)
67 23:02:25.697289 progress 65 % (30 MB)
68 23:02:25.710341 progress 70 % (32 MB)
69 23:02:25.723249 progress 75 % (35 MB)
70 23:02:25.736057 progress 80 % (37 MB)
71 23:02:25.749110 progress 85 % (39 MB)
72 23:02:25.761939 progress 90 % (42 MB)
73 23:02:25.774901 progress 95 % (44 MB)
74 23:02:25.787477 progress 100 % (46 MB)
75 23:02:25.787712 46 MB downloaded in 0.26 s (178.45 MB/s)
76 23:02:25.787869 end: 1.2.1 http-download (duration 00:00:00) [common]
78 23:02:25.788100 end: 1.2 download-retry (duration 00:00:00) [common]
79 23:02:25.788211 start: 1.3 download-retry (timeout 00:09:59) [common]
80 23:02:25.788319 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 23:02:25.788461 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.64-cip10/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 23:02:25.788534 saving as /var/lib/lava/dispatcher/tmp/12154420/tftp-deploy-1s1l4ozf/dtb/mt8192-asurada-spherion-r0.dtb
83 23:02:25.788597 total size: 47278 (0 MB)
84 23:02:25.788658 No compression specified
85 23:02:25.789783 progress 69 % (0 MB)
86 23:02:25.790096 progress 100 % (0 MB)
87 23:02:25.790255 0 MB downloaded in 0.00 s (27.23 MB/s)
88 23:02:25.790380 end: 1.3.1 http-download (duration 00:00:00) [common]
90 23:02:25.790607 end: 1.3 download-retry (duration 00:00:00) [common]
91 23:02:25.790695 start: 1.4 download-retry (timeout 00:09:59) [common]
92 23:02:25.790778 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 23:02:25.790893 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/full.rootfs.tar.xz
94 23:02:25.790961 saving as /var/lib/lava/dispatcher/tmp/12154420/tftp-deploy-1s1l4ozf/nfsrootfs/full.rootfs.tar
95 23:02:25.791022 total size: 125290964 (119 MB)
96 23:02:25.791084 Using unxz to decompress xz
97 23:02:25.795260 progress 0 % (0 MB)
98 23:02:26.135630 progress 5 % (6 MB)
99 23:02:26.483632 progress 10 % (11 MB)
100 23:02:26.818667 progress 15 % (17 MB)
101 23:02:27.007225 progress 20 % (23 MB)
102 23:02:27.180592 progress 25 % (29 MB)
103 23:02:27.529827 progress 30 % (35 MB)
104 23:02:27.881966 progress 35 % (41 MB)
105 23:02:28.264566 progress 40 % (47 MB)
106 23:02:28.638440 progress 45 % (53 MB)
107 23:02:29.027420 progress 50 % (59 MB)
108 23:02:29.385072 progress 55 % (65 MB)
109 23:02:29.745641 progress 60 % (71 MB)
110 23:02:30.084387 progress 65 % (77 MB)
111 23:02:30.453367 progress 70 % (83 MB)
112 23:02:30.831293 progress 75 % (89 MB)
113 23:02:31.247163 progress 80 % (95 MB)
114 23:02:31.661831 progress 85 % (101 MB)
115 23:02:31.908913 progress 90 % (107 MB)
116 23:02:32.257726 progress 95 % (113 MB)
117 23:02:32.639702 progress 100 % (119 MB)
118 23:02:32.645600 119 MB downloaded in 6.85 s (17.43 MB/s)
119 23:02:32.645893 end: 1.4.1 http-download (duration 00:00:07) [common]
121 23:02:32.646225 end: 1.4 download-retry (duration 00:00:07) [common]
122 23:02:32.646319 start: 1.5 download-retry (timeout 00:09:53) [common]
123 23:02:32.646412 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 23:02:32.646578 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.64-cip10/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 23:02:32.646648 saving as /var/lib/lava/dispatcher/tmp/12154420/tftp-deploy-1s1l4ozf/modules/modules.tar
126 23:02:32.646710 total size: 8616152 (8 MB)
127 23:02:32.646775 Using unxz to decompress xz
128 23:02:32.915473 progress 0 % (0 MB)
129 23:02:32.936878 progress 5 % (0 MB)
130 23:02:32.960743 progress 10 % (0 MB)
131 23:02:32.985001 progress 15 % (1 MB)
132 23:02:33.009251 progress 20 % (1 MB)
133 23:02:33.033819 progress 25 % (2 MB)
134 23:02:33.060362 progress 30 % (2 MB)
135 23:02:33.087170 progress 35 % (2 MB)
136 23:02:33.111270 progress 40 % (3 MB)
137 23:02:33.136344 progress 45 % (3 MB)
138 23:02:33.162437 progress 50 % (4 MB)
139 23:02:33.187195 progress 55 % (4 MB)
140 23:02:33.212727 progress 60 % (4 MB)
141 23:02:33.238974 progress 65 % (5 MB)
142 23:02:33.267413 progress 70 % (5 MB)
143 23:02:33.291624 progress 75 % (6 MB)
144 23:02:33.319478 progress 80 % (6 MB)
145 23:02:33.346081 progress 85 % (7 MB)
146 23:02:33.372239 progress 90 % (7 MB)
147 23:02:33.402413 progress 95 % (7 MB)
148 23:02:33.431233 progress 100 % (8 MB)
149 23:02:33.437789 8 MB downloaded in 0.79 s (10.39 MB/s)
150 23:02:33.438101 end: 1.5.1 http-download (duration 00:00:01) [common]
152 23:02:33.438373 end: 1.5 download-retry (duration 00:00:01) [common]
153 23:02:33.438469 start: 1.6 prepare-tftp-overlay (timeout 00:09:52) [common]
154 23:02:33.438564 start: 1.6.1 extract-nfsrootfs (timeout 00:09:52) [common]
155 23:02:35.603310 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12154420/extract-nfsrootfs-aawdswdf
156 23:02:35.603526 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 23:02:35.603631 start: 1.6.2 lava-overlay (timeout 00:09:50) [common]
158 23:02:35.603793 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12154420/lava-overlay-xfjcp51v
159 23:02:35.603925 makedir: /var/lib/lava/dispatcher/tmp/12154420/lava-overlay-xfjcp51v/lava-12154420/bin
160 23:02:35.604029 makedir: /var/lib/lava/dispatcher/tmp/12154420/lava-overlay-xfjcp51v/lava-12154420/tests
161 23:02:35.604129 makedir: /var/lib/lava/dispatcher/tmp/12154420/lava-overlay-xfjcp51v/lava-12154420/results
162 23:02:35.604260 Creating /var/lib/lava/dispatcher/tmp/12154420/lava-overlay-xfjcp51v/lava-12154420/bin/lava-add-keys
163 23:02:35.604424 Creating /var/lib/lava/dispatcher/tmp/12154420/lava-overlay-xfjcp51v/lava-12154420/bin/lava-add-sources
164 23:02:35.604554 Creating /var/lib/lava/dispatcher/tmp/12154420/lava-overlay-xfjcp51v/lava-12154420/bin/lava-background-process-start
165 23:02:35.604683 Creating /var/lib/lava/dispatcher/tmp/12154420/lava-overlay-xfjcp51v/lava-12154420/bin/lava-background-process-stop
166 23:02:35.604811 Creating /var/lib/lava/dispatcher/tmp/12154420/lava-overlay-xfjcp51v/lava-12154420/bin/lava-common-functions
167 23:02:35.604936 Creating /var/lib/lava/dispatcher/tmp/12154420/lava-overlay-xfjcp51v/lava-12154420/bin/lava-echo-ipv4
168 23:02:35.605062 Creating /var/lib/lava/dispatcher/tmp/12154420/lava-overlay-xfjcp51v/lava-12154420/bin/lava-install-packages
169 23:02:35.605188 Creating /var/lib/lava/dispatcher/tmp/12154420/lava-overlay-xfjcp51v/lava-12154420/bin/lava-installed-packages
170 23:02:35.605313 Creating /var/lib/lava/dispatcher/tmp/12154420/lava-overlay-xfjcp51v/lava-12154420/bin/lava-os-build
171 23:02:35.605438 Creating /var/lib/lava/dispatcher/tmp/12154420/lava-overlay-xfjcp51v/lava-12154420/bin/lava-probe-channel
172 23:02:35.605564 Creating /var/lib/lava/dispatcher/tmp/12154420/lava-overlay-xfjcp51v/lava-12154420/bin/lava-probe-ip
173 23:02:35.605691 Creating /var/lib/lava/dispatcher/tmp/12154420/lava-overlay-xfjcp51v/lava-12154420/bin/lava-target-ip
174 23:02:35.605815 Creating /var/lib/lava/dispatcher/tmp/12154420/lava-overlay-xfjcp51v/lava-12154420/bin/lava-target-mac
175 23:02:35.605940 Creating /var/lib/lava/dispatcher/tmp/12154420/lava-overlay-xfjcp51v/lava-12154420/bin/lava-target-storage
176 23:02:35.606066 Creating /var/lib/lava/dispatcher/tmp/12154420/lava-overlay-xfjcp51v/lava-12154420/bin/lava-test-case
177 23:02:35.606195 Creating /var/lib/lava/dispatcher/tmp/12154420/lava-overlay-xfjcp51v/lava-12154420/bin/lava-test-event
178 23:02:35.606339 Creating /var/lib/lava/dispatcher/tmp/12154420/lava-overlay-xfjcp51v/lava-12154420/bin/lava-test-feedback
179 23:02:35.606468 Creating /var/lib/lava/dispatcher/tmp/12154420/lava-overlay-xfjcp51v/lava-12154420/bin/lava-test-raise
180 23:02:35.606594 Creating /var/lib/lava/dispatcher/tmp/12154420/lava-overlay-xfjcp51v/lava-12154420/bin/lava-test-reference
181 23:02:35.606720 Creating /var/lib/lava/dispatcher/tmp/12154420/lava-overlay-xfjcp51v/lava-12154420/bin/lava-test-runner
182 23:02:35.606846 Creating /var/lib/lava/dispatcher/tmp/12154420/lava-overlay-xfjcp51v/lava-12154420/bin/lava-test-set
183 23:02:35.606971 Creating /var/lib/lava/dispatcher/tmp/12154420/lava-overlay-xfjcp51v/lava-12154420/bin/lava-test-shell
184 23:02:35.607100 Updating /var/lib/lava/dispatcher/tmp/12154420/lava-overlay-xfjcp51v/lava-12154420/bin/lava-install-packages (oe)
185 23:02:35.607257 Updating /var/lib/lava/dispatcher/tmp/12154420/lava-overlay-xfjcp51v/lava-12154420/bin/lava-installed-packages (oe)
186 23:02:35.607382 Creating /var/lib/lava/dispatcher/tmp/12154420/lava-overlay-xfjcp51v/lava-12154420/environment
187 23:02:35.607479 LAVA metadata
188 23:02:35.607550 - LAVA_JOB_ID=12154420
189 23:02:35.607613 - LAVA_DISPATCHER_IP=192.168.201.1
190 23:02:35.607715 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:50) [common]
191 23:02:35.607782 skipped lava-vland-overlay
192 23:02:35.607856 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 23:02:35.607936 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:50) [common]
194 23:02:35.607997 skipped lava-multinode-overlay
195 23:02:35.608069 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 23:02:35.608148 start: 1.6.2.3 test-definition (timeout 00:09:50) [common]
197 23:02:35.608248 Loading test definitions
198 23:02:35.608355 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:50) [common]
199 23:02:35.608425 Using /lava-12154420 at stage 0
200 23:02:35.608739 uuid=12154420_1.6.2.3.1 testdef=None
201 23:02:35.608828 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 23:02:35.608915 start: 1.6.2.3.2 test-overlay (timeout 00:09:50) [common]
203 23:02:35.609431 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 23:02:35.609649 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:50) [common]
206 23:02:35.610290 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 23:02:35.610519 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:50) [common]
209 23:02:35.611137 runner path: /var/lib/lava/dispatcher/tmp/12154420/lava-overlay-xfjcp51v/lava-12154420/0/tests/0_dmesg test_uuid 12154420_1.6.2.3.1
210 23:02:35.611292 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 23:02:35.611514 start: 1.6.2.3.5 inline-repo-action (timeout 00:09:50) [common]
213 23:02:35.611585 Using /lava-12154420 at stage 1
214 23:02:35.611885 uuid=12154420_1.6.2.3.5 testdef=None
215 23:02:35.611974 end: 1.6.2.3.5 inline-repo-action (duration 00:00:00) [common]
216 23:02:35.612058 start: 1.6.2.3.6 test-overlay (timeout 00:09:50) [common]
217 23:02:35.612562 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
219 23:02:35.612775 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:50) [common]
220 23:02:35.613412 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
222 23:02:35.613636 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:50) [common]
223 23:02:35.614255 runner path: /var/lib/lava/dispatcher/tmp/12154420/lava-overlay-xfjcp51v/lava-12154420/1/tests/1_bootrr test_uuid 12154420_1.6.2.3.5
224 23:02:35.614406 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
226 23:02:35.614608 Creating lava-test-runner.conf files
227 23:02:35.614670 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12154420/lava-overlay-xfjcp51v/lava-12154420/0 for stage 0
228 23:02:35.614761 - 0_dmesg
229 23:02:35.614840 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12154420/lava-overlay-xfjcp51v/lava-12154420/1 for stage 1
230 23:02:35.614931 - 1_bootrr
231 23:02:35.615025 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
232 23:02:35.615110 start: 1.6.2.4 compress-overlay (timeout 00:09:50) [common]
233 23:02:35.622550 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
234 23:02:35.622683 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:50) [common]
235 23:02:35.622772 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
236 23:02:35.622859 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
237 23:02:35.622945 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:50) [common]
238 23:02:35.744474 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
239 23:02:35.744864 start: 1.6.4 extract-modules (timeout 00:09:49) [common]
240 23:02:35.744980 extracting modules file /var/lib/lava/dispatcher/tmp/12154420/tftp-deploy-1s1l4ozf/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12154420/extract-nfsrootfs-aawdswdf
241 23:02:35.969787 extracting modules file /var/lib/lava/dispatcher/tmp/12154420/tftp-deploy-1s1l4ozf/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12154420/extract-overlay-ramdisk-frywmg7m/ramdisk
242 23:02:36.200118 end: 1.6.4 extract-modules (duration 00:00:00) [common]
243 23:02:36.200377 start: 1.6.5 apply-overlay-tftp (timeout 00:09:49) [common]
244 23:02:36.200479 [common] Applying overlay to NFS
245 23:02:36.200548 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12154420/compress-overlay-hr5vv8q9/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12154420/extract-nfsrootfs-aawdswdf
246 23:02:36.208663 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
247 23:02:36.208806 start: 1.6.6 configure-preseed-file (timeout 00:09:49) [common]
248 23:02:36.208902 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
249 23:02:36.208993 start: 1.6.7 compress-ramdisk (timeout 00:09:49) [common]
250 23:02:36.209077 Building ramdisk /var/lib/lava/dispatcher/tmp/12154420/extract-overlay-ramdisk-frywmg7m/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12154420/extract-overlay-ramdisk-frywmg7m/ramdisk
251 23:02:36.539626 >> 119410 blocks
252 23:02:38.458633 rename /var/lib/lava/dispatcher/tmp/12154420/extract-overlay-ramdisk-frywmg7m/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12154420/tftp-deploy-1s1l4ozf/ramdisk/ramdisk.cpio.gz
253 23:02:38.459143 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
254 23:02:38.459307 start: 1.6.8 prepare-kernel (timeout 00:09:47) [common]
255 23:02:38.459422 start: 1.6.8.1 prepare-fit (timeout 00:09:47) [common]
256 23:02:38.459547 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12154420/tftp-deploy-1s1l4ozf/kernel/Image'
257 23:02:50.890952 Returned 0 in 12 seconds
258 23:02:50.991623 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12154420/tftp-deploy-1s1l4ozf/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12154420/tftp-deploy-1s1l4ozf/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12154420/tftp-deploy-1s1l4ozf/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12154420/tftp-deploy-1s1l4ozf/kernel/image.itb
259 23:02:51.352807 output: FIT description: Kernel Image image with one or more FDT blobs
260 23:02:51.353182 output: Created: Fri Dec 1 23:02:51 2023
261 23:02:51.353264 output: Image 0 (kernel-1)
262 23:02:51.353331 output: Description:
263 23:02:51.353393 output: Created: Fri Dec 1 23:02:51 2023
264 23:02:51.353454 output: Type: Kernel Image
265 23:02:51.353514 output: Compression: lzma compressed
266 23:02:51.353574 output: Data Size: 11043984 Bytes = 10785.14 KiB = 10.53 MiB
267 23:02:51.353632 output: Architecture: AArch64
268 23:02:51.353689 output: OS: Linux
269 23:02:51.353747 output: Load Address: 0x00000000
270 23:02:51.353804 output: Entry Point: 0x00000000
271 23:02:51.353859 output: Hash algo: crc32
272 23:02:51.353917 output: Hash value: 36c84243
273 23:02:51.354027 output: Image 1 (fdt-1)
274 23:02:51.354099 output: Description: mt8192-asurada-spherion-r0
275 23:02:51.354152 output: Created: Fri Dec 1 23:02:51 2023
276 23:02:51.354206 output: Type: Flat Device Tree
277 23:02:51.354259 output: Compression: uncompressed
278 23:02:51.354312 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
279 23:02:51.354365 output: Architecture: AArch64
280 23:02:51.354417 output: Hash algo: crc32
281 23:02:51.354470 output: Hash value: cc4352de
282 23:02:51.354571 output: Image 2 (ramdisk-1)
283 23:02:51.354637 output: Description: unavailable
284 23:02:51.354690 output: Created: Fri Dec 1 23:02:51 2023
285 23:02:51.354743 output: Type: RAMDisk Image
286 23:02:51.354796 output: Compression: Unknown Compression
287 23:02:51.354866 output: Data Size: 17798348 Bytes = 17381.20 KiB = 16.97 MiB
288 23:02:51.354949 output: Architecture: AArch64
289 23:02:51.355003 output: OS: Linux
290 23:02:51.355056 output: Load Address: unavailable
291 23:02:51.355109 output: Entry Point: unavailable
292 23:02:51.355162 output: Hash algo: crc32
293 23:02:51.355214 output: Hash value: 0e1b3b8c
294 23:02:51.355268 output: Default Configuration: 'conf-1'
295 23:02:51.355321 output: Configuration 0 (conf-1)
296 23:02:51.355374 output: Description: mt8192-asurada-spherion-r0
297 23:02:51.355426 output: Kernel: kernel-1
298 23:02:51.355479 output: Init Ramdisk: ramdisk-1
299 23:02:51.355532 output: FDT: fdt-1
300 23:02:51.355584 output: Loadables: kernel-1
301 23:02:51.355636 output:
302 23:02:51.355849 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
303 23:02:51.355949 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
304 23:02:51.356050 end: 1.6 prepare-tftp-overlay (duration 00:00:18) [common]
305 23:02:51.356142 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:34) [common]
306 23:02:51.356257 No LXC device requested
307 23:02:51.356337 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
308 23:02:51.356421 start: 1.8 deploy-device-env (timeout 00:09:34) [common]
309 23:02:51.356498 end: 1.8 deploy-device-env (duration 00:00:00) [common]
310 23:02:51.356569 Checking files for TFTP limit of 4294967296 bytes.
311 23:02:51.357086 end: 1 tftp-deploy (duration 00:00:26) [common]
312 23:02:51.357189 start: 2 depthcharge-action (timeout 00:05:00) [common]
313 23:02:51.357279 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
314 23:02:51.357405 substitutions:
315 23:02:51.357471 - {DTB}: 12154420/tftp-deploy-1s1l4ozf/dtb/mt8192-asurada-spherion-r0.dtb
316 23:02:51.357538 - {INITRD}: 12154420/tftp-deploy-1s1l4ozf/ramdisk/ramdisk.cpio.gz
317 23:02:51.357598 - {KERNEL}: 12154420/tftp-deploy-1s1l4ozf/kernel/Image
318 23:02:51.357656 - {LAVA_MAC}: None
319 23:02:51.357713 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12154420/extract-nfsrootfs-aawdswdf
320 23:02:51.357770 - {NFS_SERVER_IP}: 192.168.201.1
321 23:02:51.357825 - {PRESEED_CONFIG}: None
322 23:02:51.357880 - {PRESEED_LOCAL}: None
323 23:02:51.357935 - {RAMDISK}: 12154420/tftp-deploy-1s1l4ozf/ramdisk/ramdisk.cpio.gz
324 23:02:51.357990 - {ROOT_PART}: None
325 23:02:51.358045 - {ROOT}: None
326 23:02:51.358099 - {SERVER_IP}: 192.168.201.1
327 23:02:51.358153 - {TEE}: None
328 23:02:51.358207 Parsed boot commands:
329 23:02:51.358259 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
330 23:02:51.358441 Parsed boot commands: tftpboot 192.168.201.1 12154420/tftp-deploy-1s1l4ozf/kernel/image.itb 12154420/tftp-deploy-1s1l4ozf/kernel/cmdline
331 23:02:51.358529 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
332 23:02:51.358614 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
333 23:02:51.358709 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
334 23:02:51.358796 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
335 23:02:51.358866 Not connected, no need to disconnect.
336 23:02:51.358942 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
337 23:02:51.359030 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
338 23:02:51.359098 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
339 23:02:51.363179 Setting prompt string to ['lava-test: # ']
340 23:02:51.363618 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
341 23:02:51.363728 end: 2.2.1 reset-connection (duration 00:00:00) [common]
342 23:02:51.363823 start: 2.2.2 reset-device (timeout 00:05:00) [common]
343 23:02:51.363933 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
344 23:02:51.364194 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
345 23:02:56.499535 >> Command sent successfully.
346 23:02:56.502078 Returned 0 in 5 seconds
347 23:02:56.602501 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
349 23:02:56.602844 end: 2.2.2 reset-device (duration 00:00:05) [common]
350 23:02:56.602946 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
351 23:02:56.603036 Setting prompt string to 'Starting depthcharge on Spherion...'
352 23:02:56.603105 Changing prompt to 'Starting depthcharge on Spherion...'
353 23:02:56.603174 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
354 23:02:56.603457 [Enter `^Ec?' for help]
355 23:02:56.777985
356 23:02:56.778181
357 23:02:56.778261 F0: 102B 0000
358 23:02:56.778328
359 23:02:56.778391 F3: 1001 0000 [0200]
360 23:02:56.778451
361 23:02:56.781708 F3: 1001 0000
362 23:02:56.781860
363 23:02:56.781972 F7: 102D 0000
364 23:02:56.782072
365 23:02:56.782142 F1: 0000 0000
366 23:02:56.782203
367 23:02:56.785372 V0: 0000 0000 [0001]
368 23:02:56.785460
369 23:02:56.785527 00: 0007 8000
370 23:02:56.785595
371 23:02:56.789028 01: 0000 0000
372 23:02:56.789119
373 23:02:56.789186 BP: 0C00 0209 [0000]
374 23:02:56.789248
375 23:02:56.789308 G0: 1182 0000
376 23:02:56.792627
377 23:02:56.792716 EC: 0000 0021 [4000]
378 23:02:56.792791
379 23:02:56.796213 S7: 0000 0000 [0000]
380 23:02:56.796348
381 23:02:56.796418 CC: 0000 0000 [0001]
382 23:02:56.796481
383 23:02:56.800091 T0: 0000 0040 [010F]
384 23:02:56.800182
385 23:02:56.800293 Jump to BL
386 23:02:56.800356
387 23:02:56.824703
388 23:02:56.824860
389 23:02:56.824932
390 23:02:56.831964 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
391 23:02:56.835860 ARM64: Exception handlers installed.
392 23:02:56.839503 ARM64: Testing exception
393 23:02:56.843299 ARM64: Done test exception
394 23:02:56.850927 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
395 23:02:56.858052 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
396 23:02:56.864733 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
397 23:02:56.875015 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
398 23:02:56.882073 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
399 23:02:56.892057 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
400 23:02:56.903113 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
401 23:02:56.909472 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
402 23:02:56.927093 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
403 23:02:56.930859 WDT: Last reset was cold boot
404 23:02:56.934135 SPI1(PAD0) initialized at 2873684 Hz
405 23:02:56.937306 SPI5(PAD0) initialized at 992727 Hz
406 23:02:56.940850 VBOOT: Loading verstage.
407 23:02:56.947370 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
408 23:02:56.950497 FMAP: Found "FLASH" version 1.1 at 0x20000.
409 23:02:56.953718 FMAP: base = 0x0 size = 0x800000 #areas = 25
410 23:02:56.957163 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
411 23:02:56.964686 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
412 23:02:56.971218 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
413 23:02:56.982538 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
414 23:02:56.982674
415 23:02:56.982743
416 23:02:56.992430 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
417 23:02:56.995621 ARM64: Exception handlers installed.
418 23:02:56.998871 ARM64: Testing exception
419 23:02:56.998961 ARM64: Done test exception
420 23:02:57.006143 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
421 23:02:57.009273 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 23:02:57.023239 Probing TPM: . done!
423 23:02:57.023387 TPM ready after 0 ms
424 23:02:57.030258 Connected to device vid:did:rid of 1ae0:0028:00
425 23:02:57.077531 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
426 23:02:57.077691 Initialized TPM device CR50 revision 0
427 23:02:57.089048 tlcl_send_startup: Startup return code is 0
428 23:02:57.089193 TPM: setup succeeded
429 23:02:57.100072 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
430 23:02:57.109626 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
431 23:02:57.121569 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
432 23:02:57.130617 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
433 23:02:57.133183 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
434 23:02:57.137088 in-header: 03 07 00 00 08 00 00 00
435 23:02:57.140926 in-data: aa e4 47 04 13 02 00 00
436 23:02:57.144031 Chrome EC: UHEPI supported
437 23:02:57.151371 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
438 23:02:57.154685 in-header: 03 9d 00 00 08 00 00 00
439 23:02:57.158746 in-data: 10 20 20 08 00 00 00 00
440 23:02:57.158851 Phase 1
441 23:02:57.162192 FMAP: area GBB found @ 3f5000 (12032 bytes)
442 23:02:57.169411 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
443 23:02:57.177382 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
444 23:02:57.177516 Recovery requested (1009000e)
445 23:02:57.185734 TPM: Extending digest for VBOOT: boot mode into PCR 0
446 23:02:57.191131 tlcl_extend: response is 0
447 23:02:57.199442 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
448 23:02:57.205207 tlcl_extend: response is 0
449 23:02:57.212000 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
450 23:02:57.232817 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
451 23:02:57.239877 BS: bootblock times (exec / console): total (unknown) / 148 ms
452 23:02:57.240008
453 23:02:57.240077
454 23:02:57.250458 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
455 23:02:57.253956 ARM64: Exception handlers installed.
456 23:02:57.254060 ARM64: Testing exception
457 23:02:57.257555 ARM64: Done test exception
458 23:02:57.277658 pmic_efuse_setting: Set efuses in 11 msecs
459 23:02:57.281076 pmwrap_interface_init: Select PMIF_VLD_RDY
460 23:02:57.288540 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
461 23:02:57.292250 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
462 23:02:57.295907 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
463 23:02:57.303511 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
464 23:02:57.306755 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
465 23:02:57.310517 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
466 23:02:57.314279 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
467 23:02:57.321141 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
468 23:02:57.324475 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
469 23:02:57.331229 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
470 23:02:57.334776 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
471 23:02:57.337794 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
472 23:02:57.344588 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
473 23:02:57.351113 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
474 23:02:57.354625 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
475 23:02:57.361334 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
476 23:02:57.367719 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
477 23:02:57.371197 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
478 23:02:57.378355 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
479 23:02:57.386349 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
480 23:02:57.390000 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
481 23:02:57.393241 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
482 23:02:57.400159 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
483 23:02:57.406852 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
484 23:02:57.410937 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
485 23:02:57.417197 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
486 23:02:57.420311 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
487 23:02:57.427149 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
488 23:02:57.430415 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
489 23:02:57.437824 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
490 23:02:57.441414 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
491 23:02:57.444976 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
492 23:02:57.452445 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
493 23:02:57.455899 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
494 23:02:57.459515 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
495 23:02:57.466757 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
496 23:02:57.470924 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
497 23:02:57.477689 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
498 23:02:57.480694 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
499 23:02:57.484403 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
500 23:02:57.490776 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
501 23:02:57.493956 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
502 23:02:57.497620 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
503 23:02:57.504196 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
504 23:02:57.507587 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
505 23:02:57.510946 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
506 23:02:57.514473 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
507 23:02:57.520781 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
508 23:02:57.524226 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
509 23:02:57.527605 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
510 23:02:57.530979 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
511 23:02:57.540877 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
512 23:02:57.547606 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
513 23:02:57.554099 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
514 23:02:57.560913 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
515 23:02:57.570821 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
516 23:02:57.574296 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
517 23:02:57.577883 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
518 23:02:57.584416 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
519 23:02:57.590750 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x2f
520 23:02:57.597706 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
521 23:02:57.600594 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
522 23:02:57.603926 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
523 23:02:57.615345 [RTC]rtc_get_frequency_meter,154: input=15, output=794
524 23:02:57.618151 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
525 23:02:57.625040 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
526 23:02:57.628029 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
527 23:02:57.631440 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
528 23:02:57.634847 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
529 23:02:57.638324 ADC[4]: Raw value=895191 ID=7
530 23:02:57.641479 ADC[3]: Raw value=213440 ID=1
531 23:02:57.641576 RAM Code: 0x71
532 23:02:57.649253 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
533 23:02:57.653015 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
534 23:02:57.660212 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
535 23:02:57.667416 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
536 23:02:57.671251 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
537 23:02:57.675308 in-header: 03 07 00 00 08 00 00 00
538 23:02:57.678876 in-data: aa e4 47 04 13 02 00 00
539 23:02:57.678983 Chrome EC: UHEPI supported
540 23:02:57.685737 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
541 23:02:57.689994 in-header: 03 95 00 00 08 00 00 00
542 23:02:57.693746 in-data: 18 20 20 08 00 00 00 00
543 23:02:57.698046 MRC: failed to locate region type 0.
544 23:02:57.705202 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
545 23:02:57.708802 DRAM-K: Running full calibration
546 23:02:57.712447 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
547 23:02:57.715985 header.status = 0x0
548 23:02:57.719649 header.version = 0x6 (expected: 0x6)
549 23:02:57.723240 header.size = 0xd00 (expected: 0xd00)
550 23:02:57.723339 header.flags = 0x0
551 23:02:57.730601 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
552 23:02:57.747849 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
553 23:02:57.754249 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
554 23:02:57.758206 dram_init: ddr_geometry: 2
555 23:02:57.758312 [EMI] MDL number = 2
556 23:02:57.761166 [EMI] Get MDL freq = 0
557 23:02:57.765037 dram_init: ddr_type: 0
558 23:02:57.765126 is_discrete_lpddr4: 1
559 23:02:57.768418 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
560 23:02:57.768507
561 23:02:57.768572
562 23:02:57.772080 [Bian_co] ETT version 0.0.0.1
563 23:02:57.775896 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
564 23:02:57.775999
565 23:02:57.779484 dramc_set_vcore_voltage set vcore to 650000
566 23:02:57.782741 Read voltage for 800, 4
567 23:02:57.782836 Vio18 = 0
568 23:02:57.782903 Vcore = 650000
569 23:02:57.786621 Vdram = 0
570 23:02:57.786712 Vddq = 0
571 23:02:57.786778 Vmddr = 0
572 23:02:57.789776 dram_init: config_dvfs: 1
573 23:02:57.793257 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
574 23:02:57.800017 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
575 23:02:57.803623 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
576 23:02:57.806813 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
577 23:02:57.809814 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
578 23:02:57.816702 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
579 23:02:57.816814 MEM_TYPE=3, freq_sel=18
580 23:02:57.820031 sv_algorithm_assistance_LP4_1600
581 23:02:57.822953 ============ PULL DRAM RESETB DOWN ============
582 23:02:57.829897 ========== PULL DRAM RESETB DOWN end =========
583 23:02:57.833183 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
584 23:02:57.836500 ===================================
585 23:02:57.839690 LPDDR4 DRAM CONFIGURATION
586 23:02:57.842939 ===================================
587 23:02:57.843038 EX_ROW_EN[0] = 0x0
588 23:02:57.846734 EX_ROW_EN[1] = 0x0
589 23:02:57.846825 LP4Y_EN = 0x0
590 23:02:57.849833 WORK_FSP = 0x0
591 23:02:57.849923 WL = 0x2
592 23:02:57.853416 RL = 0x2
593 23:02:57.856597 BL = 0x2
594 23:02:57.856690 RPST = 0x0
595 23:02:57.859767 RD_PRE = 0x0
596 23:02:57.859854 WR_PRE = 0x1
597 23:02:57.863209 WR_PST = 0x0
598 23:02:57.863298 DBI_WR = 0x0
599 23:02:57.866753 DBI_RD = 0x0
600 23:02:57.866840 OTF = 0x1
601 23:02:57.869732 ===================================
602 23:02:57.872868 ===================================
603 23:02:57.876481 ANA top config
604 23:02:57.879482 ===================================
605 23:02:57.879574 DLL_ASYNC_EN = 0
606 23:02:57.884100 ALL_SLAVE_EN = 1
607 23:02:57.886532 NEW_RANK_MODE = 1
608 23:02:57.889642 DLL_IDLE_MODE = 1
609 23:02:57.889736 LP45_APHY_COMB_EN = 1
610 23:02:57.892936 TX_ODT_DIS = 1
611 23:02:57.896358 NEW_8X_MODE = 1
612 23:02:57.899659 ===================================
613 23:02:57.903004 ===================================
614 23:02:57.906298 data_rate = 1600
615 23:02:57.909870 CKR = 1
616 23:02:57.909965 DQ_P2S_RATIO = 8
617 23:02:57.912988 ===================================
618 23:02:57.916794 CA_P2S_RATIO = 8
619 23:02:57.919826 DQ_CA_OPEN = 0
620 23:02:57.922877 DQ_SEMI_OPEN = 0
621 23:02:57.926252 CA_SEMI_OPEN = 0
622 23:02:57.929506 CA_FULL_RATE = 0
623 23:02:57.929605 DQ_CKDIV4_EN = 1
624 23:02:57.933364 CA_CKDIV4_EN = 1
625 23:02:57.936186 CA_PREDIV_EN = 0
626 23:02:57.940137 PH8_DLY = 0
627 23:02:57.943090 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
628 23:02:57.943189 DQ_AAMCK_DIV = 4
629 23:02:57.946411 CA_AAMCK_DIV = 4
630 23:02:57.950212 CA_ADMCK_DIV = 4
631 23:02:57.953495 DQ_TRACK_CA_EN = 0
632 23:02:57.956885 CA_PICK = 800
633 23:02:57.959731 CA_MCKIO = 800
634 23:02:57.963729 MCKIO_SEMI = 0
635 23:02:57.963826 PLL_FREQ = 3068
636 23:02:57.966633 DQ_UI_PI_RATIO = 32
637 23:02:57.969728 CA_UI_PI_RATIO = 0
638 23:02:57.973361 ===================================
639 23:02:57.976624 ===================================
640 23:02:57.979880 memory_type:LPDDR4
641 23:02:57.979970 GP_NUM : 10
642 23:02:57.982999 SRAM_EN : 1
643 23:02:57.986607 MD32_EN : 0
644 23:02:57.989872 ===================================
645 23:02:57.989979 [ANA_INIT] >>>>>>>>>>>>>>
646 23:02:57.993172 <<<<<< [CONFIGURE PHASE]: ANA_TX
647 23:02:57.996464 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
648 23:02:57.999742 ===================================
649 23:02:58.003036 data_rate = 1600,PCW = 0X7600
650 23:02:58.006149 ===================================
651 23:02:58.009910 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
652 23:02:58.016527 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
653 23:02:58.019316 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
654 23:02:58.026188 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
655 23:02:58.029896 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
656 23:02:58.033711 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
657 23:02:58.033815 [ANA_INIT] flow start
658 23:02:58.037212 [ANA_INIT] PLL >>>>>>>>
659 23:02:58.041048 [ANA_INIT] PLL <<<<<<<<
660 23:02:58.041147 [ANA_INIT] MIDPI >>>>>>>>
661 23:02:58.044484 [ANA_INIT] MIDPI <<<<<<<<
662 23:02:58.044576 [ANA_INIT] DLL >>>>>>>>
663 23:02:58.048421 [ANA_INIT] flow end
664 23:02:58.052129 ============ LP4 DIFF to SE enter ============
665 23:02:58.055762 ============ LP4 DIFF to SE exit ============
666 23:02:58.059413 [ANA_INIT] <<<<<<<<<<<<<
667 23:02:58.063197 [Flow] Enable top DCM control >>>>>
668 23:02:58.066827 [Flow] Enable top DCM control <<<<<
669 23:02:58.066930 Enable DLL master slave shuffle
670 23:02:58.073629 ==============================================================
671 23:02:58.077126 Gating Mode config
672 23:02:58.080864 ==============================================================
673 23:02:58.083895 Config description:
674 23:02:58.093893 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
675 23:02:58.100556 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
676 23:02:58.103739 SELPH_MODE 0: By rank 1: By Phase
677 23:02:58.110497 ==============================================================
678 23:02:58.113776 GAT_TRACK_EN = 1
679 23:02:58.117082 RX_GATING_MODE = 2
680 23:02:58.117177 RX_GATING_TRACK_MODE = 2
681 23:02:58.120187 SELPH_MODE = 1
682 23:02:58.124151 PICG_EARLY_EN = 1
683 23:02:58.127445 VALID_LAT_VALUE = 1
684 23:02:58.134025 ==============================================================
685 23:02:58.137196 Enter into Gating configuration >>>>
686 23:02:58.140338 Exit from Gating configuration <<<<
687 23:02:58.144110 Enter into DVFS_PRE_config >>>>>
688 23:02:58.153610 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
689 23:02:58.156898 Exit from DVFS_PRE_config <<<<<
690 23:02:58.160415 Enter into PICG configuration >>>>
691 23:02:58.163717 Exit from PICG configuration <<<<
692 23:02:58.167145 [RX_INPUT] configuration >>>>>
693 23:02:58.170726 [RX_INPUT] configuration <<<<<
694 23:02:58.174236 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
695 23:02:58.180532 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
696 23:02:58.187350 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
697 23:02:58.191089 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
698 23:02:58.197503 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
699 23:02:58.204108 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
700 23:02:58.207274 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
701 23:02:58.210767 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
702 23:02:58.217239 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
703 23:02:58.220681 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
704 23:02:58.224068 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
705 23:02:58.227813 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
706 23:02:58.231575 ===================================
707 23:02:58.235096 LPDDR4 DRAM CONFIGURATION
708 23:02:58.238114 ===================================
709 23:02:58.242185 EX_ROW_EN[0] = 0x0
710 23:02:58.242291 EX_ROW_EN[1] = 0x0
711 23:02:58.246158 LP4Y_EN = 0x0
712 23:02:58.246256 WORK_FSP = 0x0
713 23:02:58.246346 WL = 0x2
714 23:02:58.248913 RL = 0x2
715 23:02:58.249004 BL = 0x2
716 23:02:58.252480 RPST = 0x0
717 23:02:58.252576 RD_PRE = 0x0
718 23:02:58.255944 WR_PRE = 0x1
719 23:02:58.259484 WR_PST = 0x0
720 23:02:58.259585 DBI_WR = 0x0
721 23:02:58.259674 DBI_RD = 0x0
722 23:02:58.263115 OTF = 0x1
723 23:02:58.266741 ===================================
724 23:02:58.270461 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
725 23:02:58.273625 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
726 23:02:58.277423 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 23:02:58.280892 ===================================
728 23:02:58.285165 LPDDR4 DRAM CONFIGURATION
729 23:02:58.288627 ===================================
730 23:02:58.288722 EX_ROW_EN[0] = 0x10
731 23:02:58.292199 EX_ROW_EN[1] = 0x0
732 23:02:58.292299 LP4Y_EN = 0x0
733 23:02:58.295736 WORK_FSP = 0x0
734 23:02:58.295825 WL = 0x2
735 23:02:58.299300 RL = 0x2
736 23:02:58.299392 BL = 0x2
737 23:02:58.303556 RPST = 0x0
738 23:02:58.303650 RD_PRE = 0x0
739 23:02:58.307454 WR_PRE = 0x1
740 23:02:58.307545 WR_PST = 0x0
741 23:02:58.307612 DBI_WR = 0x0
742 23:02:58.311109 DBI_RD = 0x0
743 23:02:58.311199 OTF = 0x1
744 23:02:58.314677 ===================================
745 23:02:58.321532 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
746 23:02:58.325632 nWR fixed to 40
747 23:02:58.329304 [ModeRegInit_LP4] CH0 RK0
748 23:02:58.329407 [ModeRegInit_LP4] CH0 RK1
749 23:02:58.333068 [ModeRegInit_LP4] CH1 RK0
750 23:02:58.336157 [ModeRegInit_LP4] CH1 RK1
751 23:02:58.336288 match AC timing 13
752 23:02:58.339871 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
753 23:02:58.343797 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
754 23:02:58.350963 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
755 23:02:58.354761 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
756 23:02:58.358533 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
757 23:02:58.361799 [EMI DOE] emi_dcm 0
758 23:02:58.365587 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
759 23:02:58.365689 ==
760 23:02:58.369379 Dram Type= 6, Freq= 0, CH_0, rank 0
761 23:02:58.373112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
762 23:02:58.373209 ==
763 23:02:58.376667 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
764 23:02:58.383746 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
765 23:02:58.393664 [CA 0] Center 38 (7~69) winsize 63
766 23:02:58.397020 [CA 1] Center 37 (7~68) winsize 62
767 23:02:58.400883 [CA 2] Center 35 (5~66) winsize 62
768 23:02:58.404874 [CA 3] Center 35 (5~66) winsize 62
769 23:02:58.408146 [CA 4] Center 34 (4~65) winsize 62
770 23:02:58.408318 [CA 5] Center 34 (4~64) winsize 61
771 23:02:58.412036
772 23:02:58.412154 [CmdBusTrainingLP45] Vref(ca) range 1: 32
773 23:02:58.415804
774 23:02:58.419508 [CATrainingPosCal] consider 1 rank data
775 23:02:58.419603 u2DelayCellTimex100 = 270/100 ps
776 23:02:58.422998 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
777 23:02:58.426905 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
778 23:02:58.430790 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
779 23:02:58.434021 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
780 23:02:58.437845 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
781 23:02:58.441271 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
782 23:02:58.441364
783 23:02:58.444963 CA PerBit enable=1, Macro0, CA PI delay=34
784 23:02:58.445055
785 23:02:58.448826 [CBTSetCACLKResult] CA Dly = 34
786 23:02:58.452088 CS Dly: 6 (0~37)
787 23:02:58.452214 ==
788 23:02:58.456100 Dram Type= 6, Freq= 0, CH_0, rank 1
789 23:02:58.459995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
790 23:02:58.460096 ==
791 23:02:58.463198 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
792 23:02:58.470385 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
793 23:02:58.479946 [CA 0] Center 38 (7~69) winsize 63
794 23:02:58.483493 [CA 1] Center 37 (7~68) winsize 62
795 23:02:58.487264 [CA 2] Center 35 (5~66) winsize 62
796 23:02:58.490920 [CA 3] Center 35 (5~66) winsize 62
797 23:02:58.495020 [CA 4] Center 34 (4~65) winsize 62
798 23:02:58.495119 [CA 5] Center 34 (4~65) winsize 62
799 23:02:58.495186
800 23:02:58.501985 [CmdBusTrainingLP45] Vref(ca) range 1: 32
801 23:02:58.502096
802 23:02:58.505850 [CATrainingPosCal] consider 2 rank data
803 23:02:58.505944 u2DelayCellTimex100 = 270/100 ps
804 23:02:58.509282 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
805 23:02:58.513363 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
806 23:02:58.516869 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
807 23:02:58.520637 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
808 23:02:58.524114 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
809 23:02:58.528113 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
810 23:02:58.528218
811 23:02:58.531421 CA PerBit enable=1, Macro0, CA PI delay=34
812 23:02:58.531544
813 23:02:58.535070 [CBTSetCACLKResult] CA Dly = 34
814 23:02:58.538312 CS Dly: 6 (0~37)
815 23:02:58.538403
816 23:02:58.541589 ----->DramcWriteLeveling(PI) begin...
817 23:02:58.541682 ==
818 23:02:58.544815 Dram Type= 6, Freq= 0, CH_0, rank 0
819 23:02:58.548007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
820 23:02:58.548097 ==
821 23:02:58.551213 Write leveling (Byte 0): 31 => 31
822 23:02:58.554606 Write leveling (Byte 1): 31 => 31
823 23:02:58.558248 DramcWriteLeveling(PI) end<-----
824 23:02:58.558340
825 23:02:58.558407 ==
826 23:02:58.561361 Dram Type= 6, Freq= 0, CH_0, rank 0
827 23:02:58.564965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
828 23:02:58.565051 ==
829 23:02:58.568142 [Gating] SW mode calibration
830 23:02:58.574627 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
831 23:02:58.581541 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
832 23:02:58.584874 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
833 23:02:58.588247 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
834 23:02:58.594820 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
835 23:02:58.597845 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
836 23:02:58.601248 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
837 23:02:58.608042 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
838 23:02:58.611318 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 23:02:58.615021 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 23:02:58.622059 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
841 23:02:58.626252 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
842 23:02:58.630129 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 23:02:58.633240 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 23:02:58.636777 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 23:02:58.644001 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
846 23:02:58.647180 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
847 23:02:58.650745 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
848 23:02:58.654422 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
849 23:02:58.660941 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
850 23:02:58.664530 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
851 23:02:58.667760 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
852 23:02:58.674085 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 23:02:58.677588 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 23:02:58.681011 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 23:02:58.687341 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 23:02:58.691033 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 23:02:58.694526 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 23:02:58.701069 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 23:02:58.704107 0 9 12 | B1->B0 | 2727 3131 | 1 1 | (1 1) (1 1)
860 23:02:58.707824 0 9 16 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
861 23:02:58.714220 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
862 23:02:58.717388 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
863 23:02:58.720801 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
864 23:02:58.724102 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
865 23:02:58.730803 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
866 23:02:58.734183 0 10 8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
867 23:02:58.737217 0 10 12 | B1->B0 | 2f2f 2727 | 0 0 | (0 0) (0 0)
868 23:02:58.744154 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 23:02:58.747344 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 23:02:58.750588 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 23:02:58.757462 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 23:02:58.760802 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 23:02:58.764085 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 23:02:58.770767 0 11 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
875 23:02:58.774117 0 11 12 | B1->B0 | 3131 4545 | 0 0 | (1 1) (0 0)
876 23:02:58.777085 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
877 23:02:58.784258 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
878 23:02:58.787255 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
879 23:02:58.790457 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
880 23:02:58.797125 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
881 23:02:58.800604 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
882 23:02:58.803793 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
883 23:02:58.810700 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
884 23:02:58.813888 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
885 23:02:58.817617 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
886 23:02:58.823771 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
887 23:02:58.827444 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
888 23:02:58.830457 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
889 23:02:58.834047 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
890 23:02:58.840321 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
891 23:02:58.843905 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
892 23:02:58.847358 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
893 23:02:58.853968 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
894 23:02:58.857654 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
895 23:02:58.860702 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
896 23:02:58.867144 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
897 23:02:58.870697 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
898 23:02:58.874238 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
899 23:02:58.880654 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
900 23:02:58.880760 Total UI for P1: 0, mck2ui 16
901 23:02:58.887256 best dqsien dly found for B0: ( 0, 14, 8)
902 23:02:58.890928 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
903 23:02:58.894262 Total UI for P1: 0, mck2ui 16
904 23:02:58.897484 best dqsien dly found for B1: ( 0, 14, 12)
905 23:02:58.900941 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
906 23:02:58.904167 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
907 23:02:58.904264
908 23:02:58.907743 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
909 23:02:58.911110 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
910 23:02:58.914132 [Gating] SW calibration Done
911 23:02:58.914221 ==
912 23:02:58.917519 Dram Type= 6, Freq= 0, CH_0, rank 0
913 23:02:58.920863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
914 23:02:58.920951 ==
915 23:02:58.924020 RX Vref Scan: 0
916 23:02:58.924104
917 23:02:58.927750 RX Vref 0 -> 0, step: 1
918 23:02:58.927836
919 23:02:58.927902 RX Delay -130 -> 252, step: 16
920 23:02:58.934034 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
921 23:02:58.937397 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
922 23:02:58.940979 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
923 23:02:58.944107 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
924 23:02:58.947164 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
925 23:02:58.953848 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
926 23:02:58.957616 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
927 23:02:58.960876 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
928 23:02:58.964176 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
929 23:02:58.967370 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
930 23:02:58.973961 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
931 23:02:58.977205 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
932 23:02:58.981010 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
933 23:02:58.984084 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
934 23:02:58.987144 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
935 23:02:58.994027 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
936 23:02:58.994140 ==
937 23:02:58.997277 Dram Type= 6, Freq= 0, CH_0, rank 0
938 23:02:59.000793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
939 23:02:59.000890 ==
940 23:02:59.000957 DQS Delay:
941 23:02:59.003861 DQS0 = 0, DQS1 = 0
942 23:02:59.003949 DQM Delay:
943 23:02:59.007300 DQM0 = 80, DQM1 = 69
944 23:02:59.007388 DQ Delay:
945 23:02:59.010995 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
946 23:02:59.014175 DQ4 =85, DQ5 =61, DQ6 =85, DQ7 =93
947 23:02:59.017498 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
948 23:02:59.020849 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
949 23:02:59.020944
950 23:02:59.021011
951 23:02:59.021077 ==
952 23:02:59.023875 Dram Type= 6, Freq= 0, CH_0, rank 0
953 23:02:59.028048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
954 23:02:59.028170 ==
955 23:02:59.028291
956 23:02:59.028354
957 23:02:59.031211 TX Vref Scan disable
958 23:02:59.034940 == TX Byte 0 ==
959 23:02:59.038121 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
960 23:02:59.041733 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
961 23:02:59.044616 == TX Byte 1 ==
962 23:02:59.048393 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
963 23:02:59.051257 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
964 23:02:59.051432 ==
965 23:02:59.054906 Dram Type= 6, Freq= 0, CH_0, rank 0
966 23:02:59.058199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 23:02:59.058317 ==
968 23:02:59.072514 TX Vref=22, minBit 11, minWin=26, winSum=435
969 23:02:59.075638 TX Vref=24, minBit 11, minWin=25, winSum=433
970 23:02:59.078791 TX Vref=26, minBit 8, minWin=27, winSum=442
971 23:02:59.082200 TX Vref=28, minBit 9, minWin=27, winSum=442
972 23:02:59.085861 TX Vref=30, minBit 10, minWin=26, winSum=440
973 23:02:59.092197 TX Vref=32, minBit 10, minWin=26, winSum=440
974 23:02:59.095804 [TxChooseVref] Worse bit 8, Min win 27, Win sum 442, Final Vref 26
975 23:02:59.095903
976 23:02:59.099025 Final TX Range 1 Vref 26
977 23:02:59.099138
978 23:02:59.099233 ==
979 23:02:59.102145 Dram Type= 6, Freq= 0, CH_0, rank 0
980 23:02:59.105580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
981 23:02:59.109003 ==
982 23:02:59.109094
983 23:02:59.109159
984 23:02:59.109219 TX Vref Scan disable
985 23:02:59.112657 == TX Byte 0 ==
986 23:02:59.115778 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
987 23:02:59.119235 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
988 23:02:59.122656 == TX Byte 1 ==
989 23:02:59.125799 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
990 23:02:59.129005 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
991 23:02:59.132320
992 23:02:59.132412 [DATLAT]
993 23:02:59.132477 Freq=800, CH0 RK0
994 23:02:59.132539
995 23:02:59.136080 DATLAT Default: 0xa
996 23:02:59.136195 0, 0xFFFF, sum = 0
997 23:02:59.139496 1, 0xFFFF, sum = 0
998 23:02:59.139589 2, 0xFFFF, sum = 0
999 23:02:59.142459 3, 0xFFFF, sum = 0
1000 23:02:59.142546 4, 0xFFFF, sum = 0
1001 23:02:59.146023 5, 0xFFFF, sum = 0
1002 23:02:59.149066 6, 0xFFFF, sum = 0
1003 23:02:59.149154 7, 0xFFFF, sum = 0
1004 23:02:59.152530 8, 0xFFFF, sum = 0
1005 23:02:59.152619 9, 0x0, sum = 1
1006 23:02:59.152686 10, 0x0, sum = 2
1007 23:02:59.155812 11, 0x0, sum = 3
1008 23:02:59.155925 12, 0x0, sum = 4
1009 23:02:59.159080 best_step = 10
1010 23:02:59.159168
1011 23:02:59.159235 ==
1012 23:02:59.162258 Dram Type= 6, Freq= 0, CH_0, rank 0
1013 23:02:59.165575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1014 23:02:59.165662 ==
1015 23:02:59.168960 RX Vref Scan: 1
1016 23:02:59.169045
1017 23:02:59.172654 Set Vref Range= 32 -> 127
1018 23:02:59.172740
1019 23:02:59.172807 RX Vref 32 -> 127, step: 1
1020 23:02:59.172868
1021 23:02:59.175332 RX Delay -111 -> 252, step: 8
1022 23:02:59.175417
1023 23:02:59.179038 Set Vref, RX VrefLevel [Byte0]: 32
1024 23:02:59.182393 [Byte1]: 32
1025 23:02:59.182511
1026 23:02:59.185458 Set Vref, RX VrefLevel [Byte0]: 33
1027 23:02:59.188895 [Byte1]: 33
1028 23:02:59.193226
1029 23:02:59.193323 Set Vref, RX VrefLevel [Byte0]: 34
1030 23:02:59.196565 [Byte1]: 34
1031 23:02:59.200862
1032 23:02:59.200953 Set Vref, RX VrefLevel [Byte0]: 35
1033 23:02:59.203897 [Byte1]: 35
1034 23:02:59.208299
1035 23:02:59.208390 Set Vref, RX VrefLevel [Byte0]: 36
1036 23:02:59.211768 [Byte1]: 36
1037 23:02:59.216160
1038 23:02:59.216271 Set Vref, RX VrefLevel [Byte0]: 37
1039 23:02:59.219078 [Byte1]: 37
1040 23:02:59.223780
1041 23:02:59.223872 Set Vref, RX VrefLevel [Byte0]: 38
1042 23:02:59.226823 [Byte1]: 38
1043 23:02:59.231009
1044 23:02:59.231098 Set Vref, RX VrefLevel [Byte0]: 39
1045 23:02:59.234608 [Byte1]: 39
1046 23:02:59.239385
1047 23:02:59.239511 Set Vref, RX VrefLevel [Byte0]: 40
1048 23:02:59.241904 [Byte1]: 40
1049 23:02:59.246197
1050 23:02:59.246302 Set Vref, RX VrefLevel [Byte0]: 41
1051 23:02:59.249752 [Byte1]: 41
1052 23:02:59.254655
1053 23:02:59.254781 Set Vref, RX VrefLevel [Byte0]: 42
1054 23:02:59.257518 [Byte1]: 42
1055 23:02:59.261814
1056 23:02:59.261924 Set Vref, RX VrefLevel [Byte0]: 43
1057 23:02:59.264877 [Byte1]: 43
1058 23:02:59.269771
1059 23:02:59.269869 Set Vref, RX VrefLevel [Byte0]: 44
1060 23:02:59.273017 [Byte1]: 44
1061 23:02:59.277367
1062 23:02:59.277497 Set Vref, RX VrefLevel [Byte0]: 45
1063 23:02:59.280557 [Byte1]: 45
1064 23:02:59.285368
1065 23:02:59.285471 Set Vref, RX VrefLevel [Byte0]: 46
1066 23:02:59.288416 [Byte1]: 46
1067 23:02:59.292985
1068 23:02:59.293083 Set Vref, RX VrefLevel [Byte0]: 47
1069 23:02:59.296063 [Byte1]: 47
1070 23:02:59.300814
1071 23:02:59.300910 Set Vref, RX VrefLevel [Byte0]: 48
1072 23:02:59.303773 [Byte1]: 48
1073 23:02:59.307968
1074 23:02:59.308061 Set Vref, RX VrefLevel [Byte0]: 49
1075 23:02:59.311327 [Byte1]: 49
1076 23:02:59.315038
1077 23:02:59.318990 Set Vref, RX VrefLevel [Byte0]: 50
1078 23:02:59.319085 [Byte1]: 50
1079 23:02:59.323238
1080 23:02:59.323325 Set Vref, RX VrefLevel [Byte0]: 51
1081 23:02:59.326414 [Byte1]: 51
1082 23:02:59.330399
1083 23:02:59.330487 Set Vref, RX VrefLevel [Byte0]: 52
1084 23:02:59.333855 [Byte1]: 52
1085 23:02:59.338037
1086 23:02:59.338129 Set Vref, RX VrefLevel [Byte0]: 53
1087 23:02:59.341645 [Byte1]: 53
1088 23:02:59.346279
1089 23:02:59.346368 Set Vref, RX VrefLevel [Byte0]: 54
1090 23:02:59.349179 [Byte1]: 54
1091 23:02:59.353440
1092 23:02:59.353532 Set Vref, RX VrefLevel [Byte0]: 55
1093 23:02:59.356810 [Byte1]: 55
1094 23:02:59.361091
1095 23:02:59.361186 Set Vref, RX VrefLevel [Byte0]: 56
1096 23:02:59.364738 [Byte1]: 56
1097 23:02:59.368964
1098 23:02:59.369079 Set Vref, RX VrefLevel [Byte0]: 57
1099 23:02:59.371973 [Byte1]: 57
1100 23:02:59.376716
1101 23:02:59.376810 Set Vref, RX VrefLevel [Byte0]: 58
1102 23:02:59.379944 [Byte1]: 58
1103 23:02:59.383955
1104 23:02:59.384073 Set Vref, RX VrefLevel [Byte0]: 59
1105 23:02:59.387352 [Byte1]: 59
1106 23:02:59.391688
1107 23:02:59.391823 Set Vref, RX VrefLevel [Byte0]: 60
1108 23:02:59.394984 [Byte1]: 60
1109 23:02:59.399241
1110 23:02:59.399332 Set Vref, RX VrefLevel [Byte0]: 61
1111 23:02:59.402986 [Byte1]: 61
1112 23:02:59.406990
1113 23:02:59.407082 Set Vref, RX VrefLevel [Byte0]: 62
1114 23:02:59.410477 [Byte1]: 62
1115 23:02:59.414628
1116 23:02:59.414723 Set Vref, RX VrefLevel [Byte0]: 63
1117 23:02:59.417810 [Byte1]: 63
1118 23:02:59.422310
1119 23:02:59.422401 Set Vref, RX VrefLevel [Byte0]: 64
1120 23:02:59.425485 [Byte1]: 64
1121 23:02:59.430330
1122 23:02:59.430422 Set Vref, RX VrefLevel [Byte0]: 65
1123 23:02:59.433450 [Byte1]: 65
1124 23:02:59.438131
1125 23:02:59.438230 Set Vref, RX VrefLevel [Byte0]: 66
1126 23:02:59.440847 [Byte1]: 66
1127 23:02:59.445080
1128 23:02:59.445175 Set Vref, RX VrefLevel [Byte0]: 67
1129 23:02:59.448389 [Byte1]: 67
1130 23:02:59.453171
1131 23:02:59.453267 Set Vref, RX VrefLevel [Byte0]: 68
1132 23:02:59.456089 [Byte1]: 68
1133 23:02:59.461169
1134 23:02:59.461269 Set Vref, RX VrefLevel [Byte0]: 69
1135 23:02:59.463860 [Byte1]: 69
1136 23:02:59.468053
1137 23:02:59.468172 Set Vref, RX VrefLevel [Byte0]: 70
1138 23:02:59.471557 [Byte1]: 70
1139 23:02:59.475720
1140 23:02:59.475813 Set Vref, RX VrefLevel [Byte0]: 71
1141 23:02:59.479395 [Byte1]: 71
1142 23:02:59.483335
1143 23:02:59.483433 Set Vref, RX VrefLevel [Byte0]: 72
1144 23:02:59.486960 [Byte1]: 72
1145 23:02:59.491368
1146 23:02:59.491470 Set Vref, RX VrefLevel [Byte0]: 73
1147 23:02:59.494414 [Byte1]: 73
1148 23:02:59.499024
1149 23:02:59.499122 Set Vref, RX VrefLevel [Byte0]: 74
1150 23:02:59.502286 [Byte1]: 74
1151 23:02:59.506495
1152 23:02:59.506590 Set Vref, RX VrefLevel [Byte0]: 75
1153 23:02:59.510015 [Byte1]: 75
1154 23:02:59.514427
1155 23:02:59.514525 Set Vref, RX VrefLevel [Byte0]: 76
1156 23:02:59.517525 [Byte1]: 76
1157 23:02:59.521744
1158 23:02:59.521843 Set Vref, RX VrefLevel [Byte0]: 77
1159 23:02:59.524897 [Byte1]: 77
1160 23:02:59.529491
1161 23:02:59.529587 Set Vref, RX VrefLevel [Byte0]: 78
1162 23:02:59.532719 [Byte1]: 78
1163 23:02:59.536918
1164 23:02:59.537021 Set Vref, RX VrefLevel [Byte0]: 79
1165 23:02:59.540563 [Byte1]: 79
1166 23:02:59.544569
1167 23:02:59.544692 Final RX Vref Byte 0 = 61 to rank0
1168 23:02:59.547968 Final RX Vref Byte 1 = 61 to rank0
1169 23:02:59.551147 Final RX Vref Byte 0 = 61 to rank1
1170 23:02:59.554536 Final RX Vref Byte 1 = 61 to rank1==
1171 23:02:59.558269 Dram Type= 6, Freq= 0, CH_0, rank 0
1172 23:02:59.564661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1173 23:02:59.564773 ==
1174 23:02:59.564865 DQS Delay:
1175 23:02:59.564947 DQS0 = 0, DQS1 = 0
1176 23:02:59.568478 DQM Delay:
1177 23:02:59.568566 DQM0 = 81, DQM1 = 68
1178 23:02:59.571375 DQ Delay:
1179 23:02:59.575026 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1180 23:02:59.575123 DQ4 =80, DQ5 =68, DQ6 =88, DQ7 =92
1181 23:02:59.577921 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1182 23:02:59.581435 DQ12 =76, DQ13 =72, DQ14 =76, DQ15 =76
1183 23:02:59.584392
1184 23:02:59.584485
1185 23:02:59.591210 [DQSOSCAuto] RK0, (LSB)MR18= 0x2928, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
1186 23:02:59.594744 CH0 RK0: MR19=606, MR18=2928
1187 23:02:59.601209 CH0_RK0: MR19=0x606, MR18=0x2928, DQSOSC=399, MR23=63, INC=92, DEC=61
1188 23:02:59.601321
1189 23:02:59.604552 ----->DramcWriteLeveling(PI) begin...
1190 23:02:59.604643 ==
1191 23:02:59.608284 Dram Type= 6, Freq= 0, CH_0, rank 1
1192 23:02:59.611113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1193 23:02:59.611201 ==
1194 23:02:59.614347 Write leveling (Byte 0): 33 => 33
1195 23:02:59.617975 Write leveling (Byte 1): 29 => 29
1196 23:02:59.620982 DramcWriteLeveling(PI) end<-----
1197 23:02:59.621074
1198 23:02:59.621160 ==
1199 23:02:59.624426 Dram Type= 6, Freq= 0, CH_0, rank 1
1200 23:02:59.628319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1201 23:02:59.628489 ==
1202 23:02:59.631380 [Gating] SW mode calibration
1203 23:02:59.637596 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1204 23:02:59.644654 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1205 23:02:59.647712 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1206 23:02:59.650938 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1207 23:02:59.657904 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1208 23:02:59.661062 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1209 23:02:59.664522 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 23:02:59.671279 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 23:02:59.674629 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 23:02:59.677973 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 23:02:59.684367 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 23:02:59.687728 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 23:02:59.690990 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 23:02:59.697773 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 23:02:59.701410 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 23:02:59.745200 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 23:02:59.745870 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 23:02:59.746150 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 23:02:59.746226 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 23:02:59.746331 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 23:02:59.746405 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1224 23:02:59.746483 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 23:02:59.746580 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 23:02:59.746651 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 23:02:59.746943 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 23:02:59.789214 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 23:02:59.789567 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 23:02:59.789653 0 9 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
1231 23:02:59.789737 0 9 8 | B1->B0 | 2424 2f2f | 1 1 | (1 1) (1 1)
1232 23:02:59.789849 0 9 12 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
1233 23:02:59.790354 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1234 23:02:59.790733 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1235 23:02:59.790835 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1236 23:02:59.791405 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1237 23:02:59.791685 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1238 23:02:59.797515 0 10 4 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
1239 23:02:59.801005 0 10 8 | B1->B0 | 2f2f 2727 | 0 0 | (0 1) (1 1)
1240 23:02:59.801100 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1241 23:02:59.807441 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 23:02:59.811104 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 23:02:59.813917 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 23:02:59.820743 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 23:02:59.823825 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 23:02:59.827470 0 11 4 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
1247 23:02:59.833965 0 11 8 | B1->B0 | 3030 3d3d | 0 0 | (0 0) (0 0)
1248 23:02:59.837589 0 11 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1249 23:02:59.840702 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1250 23:02:59.844168 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1251 23:02:59.850568 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1252 23:02:59.854273 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1253 23:02:59.858166 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1254 23:02:59.861646 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1255 23:02:59.869206 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1256 23:02:59.872593 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1257 23:02:59.876091 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1258 23:02:59.879686 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1259 23:02:59.886517 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1260 23:02:59.890049 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1261 23:02:59.893258 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1262 23:02:59.896748 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1263 23:02:59.903739 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1264 23:02:59.906647 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1265 23:02:59.910446 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 23:02:59.916597 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 23:02:59.919906 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 23:02:59.923321 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 23:02:59.929896 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 23:02:59.933243 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 23:02:59.936473 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1272 23:02:59.943135 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1273 23:02:59.946620 Total UI for P1: 0, mck2ui 16
1274 23:02:59.949963 best dqsien dly found for B0: ( 0, 14, 8)
1275 23:02:59.950045 Total UI for P1: 0, mck2ui 16
1276 23:02:59.956658 best dqsien dly found for B1: ( 0, 14, 8)
1277 23:02:59.960075 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1278 23:02:59.963253 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1279 23:02:59.963335
1280 23:02:59.966711 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1281 23:02:59.969788 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1282 23:02:59.973069 [Gating] SW calibration Done
1283 23:02:59.973151 ==
1284 23:02:59.976488 Dram Type= 6, Freq= 0, CH_0, rank 1
1285 23:02:59.980106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1286 23:02:59.980188 ==
1287 23:02:59.983258 RX Vref Scan: 0
1288 23:02:59.983339
1289 23:02:59.983402 RX Vref 0 -> 0, step: 1
1290 23:02:59.983462
1291 23:02:59.986914 RX Delay -130 -> 252, step: 16
1292 23:02:59.989606 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1293 23:02:59.996369 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1294 23:03:00.000098 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1295 23:03:00.003734 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1296 23:03:00.006358 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1297 23:03:00.010020 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1298 23:03:00.016613 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1299 23:03:00.019703 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1300 23:03:00.023103 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1301 23:03:00.026800 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1302 23:03:00.029818 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1303 23:03:00.036938 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1304 23:03:00.039885 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1305 23:03:00.043364 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1306 23:03:00.046738 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1307 23:03:00.050102 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1308 23:03:00.053705 ==
1309 23:03:00.053788 Dram Type= 6, Freq= 0, CH_0, rank 1
1310 23:03:00.059940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1311 23:03:00.060025 ==
1312 23:03:00.060130 DQS Delay:
1313 23:03:00.062933 DQS0 = 0, DQS1 = 0
1314 23:03:00.063014 DQM Delay:
1315 23:03:00.066454 DQM0 = 81, DQM1 = 71
1316 23:03:00.066535 DQ Delay:
1317 23:03:00.070506 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =77
1318 23:03:00.073126 DQ4 =77, DQ5 =69, DQ6 =93, DQ7 =93
1319 23:03:00.076143 DQ8 =69, DQ9 =53, DQ10 =69, DQ11 =69
1320 23:03:00.079926 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1321 23:03:00.080010
1322 23:03:00.080075
1323 23:03:00.080135 ==
1324 23:03:00.082976 Dram Type= 6, Freq= 0, CH_0, rank 1
1325 23:03:00.086442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1326 23:03:00.086526 ==
1327 23:03:00.086591
1328 23:03:00.086650
1329 23:03:00.089595 TX Vref Scan disable
1330 23:03:00.093295 == TX Byte 0 ==
1331 23:03:00.096694 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1332 23:03:00.099873 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1333 23:03:00.103209 == TX Byte 1 ==
1334 23:03:00.106717 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1335 23:03:00.109650 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1336 23:03:00.109733 ==
1337 23:03:00.113112 Dram Type= 6, Freq= 0, CH_0, rank 1
1338 23:03:00.116814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1339 23:03:00.116898 ==
1340 23:03:00.131269 TX Vref=22, minBit 0, minWin=27, winSum=437
1341 23:03:00.134610 TX Vref=24, minBit 1, minWin=27, winSum=440
1342 23:03:00.137961 TX Vref=26, minBit 2, minWin=27, winSum=445
1343 23:03:00.141547 TX Vref=28, minBit 1, minWin=27, winSum=445
1344 23:03:00.144585 TX Vref=30, minBit 1, minWin=27, winSum=444
1345 23:03:00.147872 TX Vref=32, minBit 1, minWin=27, winSum=442
1346 23:03:00.154501 [TxChooseVref] Worse bit 2, Min win 27, Win sum 445, Final Vref 26
1347 23:03:00.154604
1348 23:03:00.158348 Final TX Range 1 Vref 26
1349 23:03:00.158448
1350 23:03:00.158537 ==
1351 23:03:00.161343 Dram Type= 6, Freq= 0, CH_0, rank 1
1352 23:03:00.164555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1353 23:03:00.164642 ==
1354 23:03:00.164704
1355 23:03:00.167803
1356 23:03:00.167899 TX Vref Scan disable
1357 23:03:00.171457 == TX Byte 0 ==
1358 23:03:00.174678 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1359 23:03:00.178053 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1360 23:03:00.181246 == TX Byte 1 ==
1361 23:03:00.184890 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1362 23:03:00.187802 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1363 23:03:00.191471
1364 23:03:00.191540 [DATLAT]
1365 23:03:00.191600 Freq=800, CH0 RK1
1366 23:03:00.191658
1367 23:03:00.194522 DATLAT Default: 0xa
1368 23:03:00.194603 0, 0xFFFF, sum = 0
1369 23:03:00.197945 1, 0xFFFF, sum = 0
1370 23:03:00.198028 2, 0xFFFF, sum = 0
1371 23:03:00.201171 3, 0xFFFF, sum = 0
1372 23:03:00.201260 4, 0xFFFF, sum = 0
1373 23:03:00.204434 5, 0xFFFF, sum = 0
1374 23:03:00.204534 6, 0xFFFF, sum = 0
1375 23:03:00.208185 7, 0xFFFF, sum = 0
1376 23:03:00.211154 8, 0xFFFF, sum = 0
1377 23:03:00.211247 9, 0x0, sum = 1
1378 23:03:00.211316 10, 0x0, sum = 2
1379 23:03:00.214846 11, 0x0, sum = 3
1380 23:03:00.214946 12, 0x0, sum = 4
1381 23:03:00.218035 best_step = 10
1382 23:03:00.218114
1383 23:03:00.218177 ==
1384 23:03:00.221191 Dram Type= 6, Freq= 0, CH_0, rank 1
1385 23:03:00.224589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1386 23:03:00.224671 ==
1387 23:03:00.227548 RX Vref Scan: 0
1388 23:03:00.227628
1389 23:03:00.227691 RX Vref 0 -> 0, step: 1
1390 23:03:00.227751
1391 23:03:00.231170 RX Delay -111 -> 252, step: 8
1392 23:03:00.237663 iDelay=209, Bit 0, Center 76 (-39 ~ 192) 232
1393 23:03:00.241183 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1394 23:03:00.244335 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1395 23:03:00.247748 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1396 23:03:00.251088 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
1397 23:03:00.258146 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1398 23:03:00.261096 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
1399 23:03:00.264772 iDelay=209, Bit 7, Center 88 (-31 ~ 208) 240
1400 23:03:00.267782 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
1401 23:03:00.271070 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1402 23:03:00.278403 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1403 23:03:00.281494 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1404 23:03:00.285141 iDelay=209, Bit 12, Center 72 (-47 ~ 192) 240
1405 23:03:00.288012 iDelay=209, Bit 13, Center 72 (-47 ~ 192) 240
1406 23:03:00.291255 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1407 23:03:00.298587 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
1408 23:03:00.298670 ==
1409 23:03:00.301525 Dram Type= 6, Freq= 0, CH_0, rank 1
1410 23:03:00.304897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1411 23:03:00.304979 ==
1412 23:03:00.305044 DQS Delay:
1413 23:03:00.308032 DQS0 = 0, DQS1 = 0
1414 23:03:00.308114 DQM Delay:
1415 23:03:00.311485 DQM0 = 78, DQM1 = 70
1416 23:03:00.311566 DQ Delay:
1417 23:03:00.314696 DQ0 =76, DQ1 =84, DQ2 =76, DQ3 =72
1418 23:03:00.317926 DQ4 =80, DQ5 =64, DQ6 =88, DQ7 =88
1419 23:03:00.321593 DQ8 =64, DQ9 =56, DQ10 =72, DQ11 =64
1420 23:03:00.324848 DQ12 =72, DQ13 =72, DQ14 =80, DQ15 =80
1421 23:03:00.324924
1422 23:03:00.324988
1423 23:03:00.331512 [DQSOSCAuto] RK1, (LSB)MR18= 0x4d27, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 390 ps
1424 23:03:00.334753 CH0 RK1: MR19=606, MR18=4D27
1425 23:03:00.341351 CH0_RK1: MR19=0x606, MR18=0x4D27, DQSOSC=390, MR23=63, INC=97, DEC=64
1426 23:03:00.344419 [RxdqsGatingPostProcess] freq 800
1427 23:03:00.351019 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1428 23:03:00.354738 Pre-setting of DQS Precalculation
1429 23:03:00.357957 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1430 23:03:00.358035 ==
1431 23:03:00.361034 Dram Type= 6, Freq= 0, CH_1, rank 0
1432 23:03:00.364363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1433 23:03:00.364445 ==
1434 23:03:00.370978 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1435 23:03:00.378083 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1436 23:03:00.386133 [CA 0] Center 36 (7~66) winsize 60
1437 23:03:00.389758 [CA 1] Center 36 (6~67) winsize 62
1438 23:03:00.392708 [CA 2] Center 34 (4~64) winsize 61
1439 23:03:00.396191 [CA 3] Center 34 (4~64) winsize 61
1440 23:03:00.399725 [CA 4] Center 34 (4~65) winsize 62
1441 23:03:00.402897 [CA 5] Center 34 (4~64) winsize 61
1442 23:03:00.402986
1443 23:03:00.406114 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1444 23:03:00.406196
1445 23:03:00.409616 [CATrainingPosCal] consider 1 rank data
1446 23:03:00.413286 u2DelayCellTimex100 = 270/100 ps
1447 23:03:00.416454 CA0 delay=36 (7~66),Diff = 2 PI (14 cell)
1448 23:03:00.419808 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1449 23:03:00.426093 CA2 delay=34 (4~64),Diff = 0 PI (0 cell)
1450 23:03:00.429137 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1451 23:03:00.432708 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1452 23:03:00.435947 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1453 23:03:00.436031
1454 23:03:00.439382 CA PerBit enable=1, Macro0, CA PI delay=34
1455 23:03:00.439465
1456 23:03:00.442473 [CBTSetCACLKResult] CA Dly = 34
1457 23:03:00.442555 CS Dly: 5 (0~36)
1458 23:03:00.446012 ==
1459 23:03:00.449290 Dram Type= 6, Freq= 0, CH_1, rank 1
1460 23:03:00.452739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1461 23:03:00.452823 ==
1462 23:03:00.455992 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1463 23:03:00.462625 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1464 23:03:00.472796 [CA 0] Center 36 (6~67) winsize 62
1465 23:03:00.475632 [CA 1] Center 36 (6~67) winsize 62
1466 23:03:00.479268 [CA 2] Center 34 (4~65) winsize 62
1467 23:03:00.482038 [CA 3] Center 34 (4~64) winsize 61
1468 23:03:00.485756 [CA 4] Center 34 (4~65) winsize 62
1469 23:03:00.488702 [CA 5] Center 33 (3~64) winsize 62
1470 23:03:00.488785
1471 23:03:00.492205 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1472 23:03:00.492321
1473 23:03:00.495784 [CATrainingPosCal] consider 2 rank data
1474 23:03:00.499114 u2DelayCellTimex100 = 270/100 ps
1475 23:03:00.502153 CA0 delay=36 (7~66),Diff = 2 PI (14 cell)
1476 23:03:00.505561 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1477 23:03:00.512060 CA2 delay=34 (4~64),Diff = 0 PI (0 cell)
1478 23:03:00.515315 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1479 23:03:00.519492 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1480 23:03:00.523195 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1481 23:03:00.523283
1482 23:03:00.526405 CA PerBit enable=1, Macro0, CA PI delay=34
1483 23:03:00.526487
1484 23:03:00.529951 [CBTSetCACLKResult] CA Dly = 34
1485 23:03:00.530036 CS Dly: 6 (0~38)
1486 23:03:00.530101
1487 23:03:00.533650 ----->DramcWriteLeveling(PI) begin...
1488 23:03:00.533734 ==
1489 23:03:00.537260 Dram Type= 6, Freq= 0, CH_1, rank 0
1490 23:03:00.541077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1491 23:03:00.541164 ==
1492 23:03:00.544471 Write leveling (Byte 0): 30 => 30
1493 23:03:00.548113 Write leveling (Byte 1): 31 => 31
1494 23:03:00.552118 DramcWriteLeveling(PI) end<-----
1495 23:03:00.552228
1496 23:03:00.552310 ==
1497 23:03:00.555667 Dram Type= 6, Freq= 0, CH_1, rank 0
1498 23:03:00.558868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1499 23:03:00.558954 ==
1500 23:03:00.562551 [Gating] SW mode calibration
1501 23:03:00.569002 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1502 23:03:00.572672 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1503 23:03:00.578804 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1504 23:03:00.582063 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1505 23:03:00.585511 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1506 23:03:00.592070 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 23:03:00.595457 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 23:03:00.599283 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 23:03:00.605362 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 23:03:00.608717 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 23:03:00.611948 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 23:03:00.618729 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 23:03:00.622308 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 23:03:00.625326 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 23:03:00.632080 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 23:03:00.635445 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 23:03:00.638945 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 23:03:00.645729 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 23:03:00.649017 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 23:03:00.652393 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1521 23:03:00.659660 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1522 23:03:00.661979 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 23:03:00.665342 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 23:03:00.669108 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 23:03:00.675761 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 23:03:00.678762 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 23:03:00.681910 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 23:03:00.688956 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 23:03:00.692187 0 9 8 | B1->B0 | 2727 2929 | 0 1 | (0 0) (1 1)
1530 23:03:00.695549 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1531 23:03:00.701992 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1532 23:03:00.705604 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1533 23:03:00.708692 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1534 23:03:00.715528 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1535 23:03:00.718751 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1536 23:03:00.722039 0 10 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1537 23:03:00.728856 0 10 8 | B1->B0 | 2a2a 2d2d | 0 0 | (1 0) (1 1)
1538 23:03:00.731938 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 23:03:00.735371 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 23:03:00.742089 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 23:03:00.745612 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 23:03:00.748934 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 23:03:00.755685 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 23:03:00.758713 0 11 4 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
1545 23:03:00.762040 0 11 8 | B1->B0 | 3838 3737 | 1 0 | (0 0) (1 1)
1546 23:03:00.765540 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1547 23:03:00.772141 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1548 23:03:00.775801 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1549 23:03:00.778844 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1550 23:03:00.785370 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1551 23:03:00.789248 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1552 23:03:00.792156 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1553 23:03:00.799321 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1554 23:03:00.802230 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1555 23:03:00.805445 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1556 23:03:00.812112 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1557 23:03:00.815561 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1558 23:03:00.818880 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1559 23:03:00.825529 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1560 23:03:00.828766 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1561 23:03:00.832315 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1562 23:03:00.838822 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1563 23:03:00.842456 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 23:03:00.845607 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 23:03:00.848846 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 23:03:00.855718 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 23:03:00.858816 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 23:03:00.862111 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1569 23:03:00.868817 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1570 23:03:00.872066 Total UI for P1: 0, mck2ui 16
1571 23:03:00.875563 best dqsien dly found for B0: ( 0, 14, 4)
1572 23:03:00.879003 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1573 23:03:00.882111 Total UI for P1: 0, mck2ui 16
1574 23:03:00.885753 best dqsien dly found for B1: ( 0, 14, 6)
1575 23:03:00.888698 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1576 23:03:00.892016 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1577 23:03:00.892122
1578 23:03:00.895697 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1579 23:03:00.898866 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1580 23:03:00.902060 [Gating] SW calibration Done
1581 23:03:00.902169 ==
1582 23:03:00.905285 Dram Type= 6, Freq= 0, CH_1, rank 0
1583 23:03:00.908715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1584 23:03:00.912149 ==
1585 23:03:00.912266 RX Vref Scan: 0
1586 23:03:00.912362
1587 23:03:00.915567 RX Vref 0 -> 0, step: 1
1588 23:03:00.915672
1589 23:03:00.918659 RX Delay -130 -> 252, step: 16
1590 23:03:00.922257 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1591 23:03:00.925665 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1592 23:03:00.928512 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1593 23:03:00.931958 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1594 23:03:00.938675 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1595 23:03:00.942092 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1596 23:03:00.945245 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1597 23:03:00.948798 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1598 23:03:00.952215 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1599 23:03:00.958992 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1600 23:03:00.961975 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1601 23:03:00.965716 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1602 23:03:00.968418 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1603 23:03:00.971922 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1604 23:03:00.978752 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1605 23:03:00.981791 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1606 23:03:00.981894 ==
1607 23:03:00.985307 Dram Type= 6, Freq= 0, CH_1, rank 0
1608 23:03:00.988509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1609 23:03:00.988585 ==
1610 23:03:00.992456 DQS Delay:
1611 23:03:00.992529 DQS0 = 0, DQS1 = 0
1612 23:03:00.992589 DQM Delay:
1613 23:03:00.995355 DQM0 = 82, DQM1 = 70
1614 23:03:00.995451 DQ Delay:
1615 23:03:00.998698 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1616 23:03:01.002048 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =77
1617 23:03:01.005756 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
1618 23:03:01.008886 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1619 23:03:01.008958
1620 23:03:01.009018
1621 23:03:01.009075 ==
1622 23:03:01.011815 Dram Type= 6, Freq= 0, CH_1, rank 0
1623 23:03:01.015355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1624 23:03:01.018629 ==
1625 23:03:01.018728
1626 23:03:01.018825
1627 23:03:01.018912 TX Vref Scan disable
1628 23:03:01.021907 == TX Byte 0 ==
1629 23:03:01.025370 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1630 23:03:01.029156 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1631 23:03:01.032617 == TX Byte 1 ==
1632 23:03:01.035508 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1633 23:03:01.038969 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1634 23:03:01.042276 ==
1635 23:03:01.042364 Dram Type= 6, Freq= 0, CH_1, rank 0
1636 23:03:01.049005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1637 23:03:01.049085 ==
1638 23:03:01.060721 TX Vref=22, minBit 1, minWin=26, winSum=436
1639 23:03:01.064235 TX Vref=24, minBit 0, minWin=27, winSum=441
1640 23:03:01.067278 TX Vref=26, minBit 0, minWin=27, winSum=442
1641 23:03:01.070678 TX Vref=28, minBit 4, minWin=27, winSum=450
1642 23:03:01.074077 TX Vref=30, minBit 0, minWin=27, winSum=445
1643 23:03:01.080658 TX Vref=32, minBit 0, minWin=27, winSum=446
1644 23:03:01.084058 [TxChooseVref] Worse bit 4, Min win 27, Win sum 450, Final Vref 28
1645 23:03:01.084159
1646 23:03:01.087514 Final TX Range 1 Vref 28
1647 23:03:01.087597
1648 23:03:01.087666 ==
1649 23:03:01.090608 Dram Type= 6, Freq= 0, CH_1, rank 0
1650 23:03:01.093953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1651 23:03:01.094036 ==
1652 23:03:01.097064
1653 23:03:01.097145
1654 23:03:01.097209 TX Vref Scan disable
1655 23:03:01.101325 == TX Byte 0 ==
1656 23:03:01.104806 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1657 23:03:01.108111 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1658 23:03:01.111264 == TX Byte 1 ==
1659 23:03:01.115177 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1660 23:03:01.117891 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1661 23:03:01.117973
1662 23:03:01.121523 [DATLAT]
1663 23:03:01.121605 Freq=800, CH1 RK0
1664 23:03:01.121670
1665 23:03:01.124853 DATLAT Default: 0xa
1666 23:03:01.124935 0, 0xFFFF, sum = 0
1667 23:03:01.128106 1, 0xFFFF, sum = 0
1668 23:03:01.128189 2, 0xFFFF, sum = 0
1669 23:03:01.131309 3, 0xFFFF, sum = 0
1670 23:03:01.131392 4, 0xFFFF, sum = 0
1671 23:03:01.135053 5, 0xFFFF, sum = 0
1672 23:03:01.135136 6, 0xFFFF, sum = 0
1673 23:03:01.138131 7, 0xFFFF, sum = 0
1674 23:03:01.138215 8, 0xFFFF, sum = 0
1675 23:03:01.141611 9, 0x0, sum = 1
1676 23:03:01.141694 10, 0x0, sum = 2
1677 23:03:01.144833 11, 0x0, sum = 3
1678 23:03:01.144916 12, 0x0, sum = 4
1679 23:03:01.148111 best_step = 10
1680 23:03:01.148255
1681 23:03:01.148345 ==
1682 23:03:01.151330 Dram Type= 6, Freq= 0, CH_1, rank 0
1683 23:03:01.154749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1684 23:03:01.154849 ==
1685 23:03:01.154934 RX Vref Scan: 1
1686 23:03:01.158557
1687 23:03:01.158659 Set Vref Range= 32 -> 127
1688 23:03:01.158747
1689 23:03:01.161715 RX Vref 32 -> 127, step: 1
1690 23:03:01.161823
1691 23:03:01.164732 RX Delay -111 -> 252, step: 8
1692 23:03:01.164835
1693 23:03:01.168158 Set Vref, RX VrefLevel [Byte0]: 32
1694 23:03:01.171285 [Byte1]: 32
1695 23:03:01.171384
1696 23:03:01.174807 Set Vref, RX VrefLevel [Byte0]: 33
1697 23:03:01.178437 [Byte1]: 33
1698 23:03:01.178545
1699 23:03:01.181657 Set Vref, RX VrefLevel [Byte0]: 34
1700 23:03:01.184736 [Byte1]: 34
1701 23:03:01.188845
1702 23:03:01.188952 Set Vref, RX VrefLevel [Byte0]: 35
1703 23:03:01.192250 [Byte1]: 35
1704 23:03:01.196370
1705 23:03:01.196477 Set Vref, RX VrefLevel [Byte0]: 36
1706 23:03:01.199951 [Byte1]: 36
1707 23:03:01.204096
1708 23:03:01.204207 Set Vref, RX VrefLevel [Byte0]: 37
1709 23:03:01.207409 [Byte1]: 37
1710 23:03:01.211811
1711 23:03:01.211916 Set Vref, RX VrefLevel [Byte0]: 38
1712 23:03:01.214843 [Byte1]: 38
1713 23:03:01.219401
1714 23:03:01.219527 Set Vref, RX VrefLevel [Byte0]: 39
1715 23:03:01.222935 [Byte1]: 39
1716 23:03:01.226897
1717 23:03:01.227003 Set Vref, RX VrefLevel [Byte0]: 40
1718 23:03:01.230596 [Byte1]: 40
1719 23:03:01.234793
1720 23:03:01.234883 Set Vref, RX VrefLevel [Byte0]: 41
1721 23:03:01.238171 [Byte1]: 41
1722 23:03:01.242189
1723 23:03:01.242275 Set Vref, RX VrefLevel [Byte0]: 42
1724 23:03:01.245539 [Byte1]: 42
1725 23:03:01.249957
1726 23:03:01.250042 Set Vref, RX VrefLevel [Byte0]: 43
1727 23:03:01.253250 [Byte1]: 43
1728 23:03:01.257492
1729 23:03:01.257576 Set Vref, RX VrefLevel [Byte0]: 44
1730 23:03:01.260820 [Byte1]: 44
1731 23:03:01.265573
1732 23:03:01.265657 Set Vref, RX VrefLevel [Byte0]: 45
1733 23:03:01.268525 [Byte1]: 45
1734 23:03:01.273264
1735 23:03:01.273408 Set Vref, RX VrefLevel [Byte0]: 46
1736 23:03:01.276453 [Byte1]: 46
1737 23:03:01.280810
1738 23:03:01.280915 Set Vref, RX VrefLevel [Byte0]: 47
1739 23:03:01.283840 [Byte1]: 47
1740 23:03:01.288423
1741 23:03:01.288506 Set Vref, RX VrefLevel [Byte0]: 48
1742 23:03:01.291726 [Byte1]: 48
1743 23:03:01.296307
1744 23:03:01.296391 Set Vref, RX VrefLevel [Byte0]: 49
1745 23:03:01.299424 [Byte1]: 49
1746 23:03:01.303316
1747 23:03:01.303399 Set Vref, RX VrefLevel [Byte0]: 50
1748 23:03:01.307119 [Byte1]: 50
1749 23:03:01.311199
1750 23:03:01.311286 Set Vref, RX VrefLevel [Byte0]: 51
1751 23:03:01.314754 [Byte1]: 51
1752 23:03:01.318780
1753 23:03:01.318863 Set Vref, RX VrefLevel [Byte0]: 52
1754 23:03:01.322357 [Byte1]: 52
1755 23:03:01.326235
1756 23:03:01.326317 Set Vref, RX VrefLevel [Byte0]: 53
1757 23:03:01.329864 [Byte1]: 53
1758 23:03:01.333979
1759 23:03:01.334061 Set Vref, RX VrefLevel [Byte0]: 54
1760 23:03:01.337388 [Byte1]: 54
1761 23:03:01.341936
1762 23:03:01.342019 Set Vref, RX VrefLevel [Byte0]: 55
1763 23:03:01.345125 [Byte1]: 55
1764 23:03:01.349618
1765 23:03:01.349700 Set Vref, RX VrefLevel [Byte0]: 56
1766 23:03:01.352781 [Byte1]: 56
1767 23:03:01.356998
1768 23:03:01.357081 Set Vref, RX VrefLevel [Byte0]: 57
1769 23:03:01.360405 [Byte1]: 57
1770 23:03:01.364551
1771 23:03:01.364634 Set Vref, RX VrefLevel [Byte0]: 58
1772 23:03:01.368001 [Byte1]: 58
1773 23:03:01.372536
1774 23:03:01.372619 Set Vref, RX VrefLevel [Byte0]: 59
1775 23:03:01.375851 [Byte1]: 59
1776 23:03:01.379928
1777 23:03:01.380012 Set Vref, RX VrefLevel [Byte0]: 60
1778 23:03:01.383547 [Byte1]: 60
1779 23:03:01.387872
1780 23:03:01.387956 Set Vref, RX VrefLevel [Byte0]: 61
1781 23:03:01.390915 [Byte1]: 61
1782 23:03:01.395435
1783 23:03:01.395518 Set Vref, RX VrefLevel [Byte0]: 62
1784 23:03:01.399001 [Byte1]: 62
1785 23:03:01.402958
1786 23:03:01.403041 Set Vref, RX VrefLevel [Byte0]: 63
1787 23:03:01.406324 [Byte1]: 63
1788 23:03:01.411081
1789 23:03:01.411165 Set Vref, RX VrefLevel [Byte0]: 64
1790 23:03:01.414097 [Byte1]: 64
1791 23:03:01.418246
1792 23:03:01.418329 Set Vref, RX VrefLevel [Byte0]: 65
1793 23:03:01.421552 [Byte1]: 65
1794 23:03:01.426298
1795 23:03:01.426382 Set Vref, RX VrefLevel [Byte0]: 66
1796 23:03:01.429244 [Byte1]: 66
1797 23:03:01.433285
1798 23:03:01.433371 Set Vref, RX VrefLevel [Byte0]: 67
1799 23:03:01.437072 [Byte1]: 67
1800 23:03:01.441016
1801 23:03:01.441127 Set Vref, RX VrefLevel [Byte0]: 68
1802 23:03:01.444415 [Byte1]: 68
1803 23:03:01.449010
1804 23:03:01.449094 Set Vref, RX VrefLevel [Byte0]: 69
1805 23:03:01.452109 [Byte1]: 69
1806 23:03:01.456639
1807 23:03:01.456722 Set Vref, RX VrefLevel [Byte0]: 70
1808 23:03:01.460025 [Byte1]: 70
1809 23:03:01.464369
1810 23:03:01.464479 Set Vref, RX VrefLevel [Byte0]: 71
1811 23:03:01.467511 [Byte1]: 71
1812 23:03:01.471872
1813 23:03:01.471960 Set Vref, RX VrefLevel [Byte0]: 72
1814 23:03:01.474982 [Byte1]: 72
1815 23:03:01.479550
1816 23:03:01.479634 Set Vref, RX VrefLevel [Byte0]: 73
1817 23:03:01.482925 [Byte1]: 73
1818 23:03:01.487144
1819 23:03:01.487240 Set Vref, RX VrefLevel [Byte0]: 74
1820 23:03:01.490151 [Byte1]: 74
1821 23:03:01.494961
1822 23:03:01.495046 Final RX Vref Byte 0 = 61 to rank0
1823 23:03:01.498122 Final RX Vref Byte 1 = 57 to rank0
1824 23:03:01.501237 Final RX Vref Byte 0 = 61 to rank1
1825 23:03:01.504737 Final RX Vref Byte 1 = 57 to rank1==
1826 23:03:01.508134 Dram Type= 6, Freq= 0, CH_1, rank 0
1827 23:03:01.514501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1828 23:03:01.514587 ==
1829 23:03:01.514652 DQS Delay:
1830 23:03:01.514713 DQS0 = 0, DQS1 = 0
1831 23:03:01.518230 DQM Delay:
1832 23:03:01.518312 DQM0 = 81, DQM1 = 71
1833 23:03:01.521336 DQ Delay:
1834 23:03:01.524703 DQ0 =88, DQ1 =76, DQ2 =68, DQ3 =76
1835 23:03:01.524786 DQ4 =76, DQ5 =96, DQ6 =92, DQ7 =76
1836 23:03:01.528405 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =68
1837 23:03:01.531381 DQ12 =80, DQ13 =80, DQ14 =76, DQ15 =76
1838 23:03:01.534829
1839 23:03:01.534911
1840 23:03:01.541581 [DQSOSCAuto] RK0, (LSB)MR18= 0x111c, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 405 ps
1841 23:03:01.544913 CH1 RK0: MR19=606, MR18=111C
1842 23:03:01.551342 CH1_RK0: MR19=0x606, MR18=0x111C, DQSOSC=402, MR23=63, INC=91, DEC=60
1843 23:03:01.551428
1844 23:03:01.554755 ----->DramcWriteLeveling(PI) begin...
1845 23:03:01.554840 ==
1846 23:03:01.558105 Dram Type= 6, Freq= 0, CH_1, rank 1
1847 23:03:01.561533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1848 23:03:01.561617 ==
1849 23:03:01.565118 Write leveling (Byte 0): 27 => 27
1850 23:03:01.568264 Write leveling (Byte 1): 28 => 28
1851 23:03:01.571412 DramcWriteLeveling(PI) end<-----
1852 23:03:01.571494
1853 23:03:01.571559 ==
1854 23:03:01.574671 Dram Type= 6, Freq= 0, CH_1, rank 1
1855 23:03:01.578603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1856 23:03:01.578688 ==
1857 23:03:01.581704 [Gating] SW mode calibration
1858 23:03:01.588166 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1859 23:03:01.595324 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1860 23:03:01.598241 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1861 23:03:01.601995 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1862 23:03:01.608299 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1863 23:03:01.611909 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 23:03:01.615056 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 23:03:01.621566 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 23:03:01.625035 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 23:03:01.628423 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 23:03:01.632118 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 23:03:01.638298 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 23:03:01.641604 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 23:03:01.645161 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 23:03:01.651578 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 23:03:01.654783 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 23:03:01.658194 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 23:03:01.664987 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 23:03:01.668379 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 23:03:01.671609 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1878 23:03:01.677818 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 23:03:01.681262 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 23:03:01.684809 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 23:03:01.691855 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 23:03:01.694926 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 23:03:01.697902 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 23:03:01.704734 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 23:03:01.707940 0 9 4 | B1->B0 | 2323 2e2d | 0 1 | (0 0) (0 0)
1886 23:03:01.711202 0 9 8 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
1887 23:03:01.717898 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1888 23:03:01.721049 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1889 23:03:01.724737 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1890 23:03:01.731396 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1891 23:03:01.734320 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1892 23:03:01.738012 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1893 23:03:01.744180 0 10 4 | B1->B0 | 3333 2e2e | 1 0 | (1 0) (0 0)
1894 23:03:01.747763 0 10 8 | B1->B0 | 2525 2323 | 0 0 | (1 1) (0 0)
1895 23:03:01.750902 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 23:03:01.758070 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 23:03:01.761059 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 23:03:01.764141 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 23:03:01.771022 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 23:03:01.774536 0 11 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1901 23:03:01.778000 0 11 4 | B1->B0 | 2c2c 3636 | 0 0 | (1 1) (0 0)
1902 23:03:01.780922 0 11 8 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
1903 23:03:01.787884 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1904 23:03:01.790991 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1905 23:03:01.794237 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1906 23:03:01.801261 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1907 23:03:01.804401 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1908 23:03:01.807947 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1909 23:03:01.814233 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1910 23:03:01.817889 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1911 23:03:01.820817 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1912 23:03:01.827472 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1913 23:03:01.831286 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1914 23:03:01.834459 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1915 23:03:01.841022 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1916 23:03:01.844527 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1917 23:03:01.847410 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1918 23:03:01.854429 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 23:03:01.858145 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 23:03:01.861157 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 23:03:01.867477 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 23:03:01.871034 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 23:03:01.874234 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 23:03:01.880883 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1925 23:03:01.884034 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1926 23:03:01.887546 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1927 23:03:01.890994 Total UI for P1: 0, mck2ui 16
1928 23:03:01.894767 best dqsien dly found for B0: ( 0, 14, 2)
1929 23:03:01.897633 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1930 23:03:01.901005 Total UI for P1: 0, mck2ui 16
1931 23:03:01.904118 best dqsien dly found for B1: ( 0, 14, 6)
1932 23:03:01.907868 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1933 23:03:01.910965 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1934 23:03:01.914264
1935 23:03:01.917559 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1936 23:03:01.920663 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1937 23:03:01.923869 [Gating] SW calibration Done
1938 23:03:01.923941 ==
1939 23:03:01.927803 Dram Type= 6, Freq= 0, CH_1, rank 1
1940 23:03:01.930543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1941 23:03:01.930612 ==
1942 23:03:01.930672 RX Vref Scan: 0
1943 23:03:01.930739
1944 23:03:01.934187 RX Vref 0 -> 0, step: 1
1945 23:03:01.934265
1946 23:03:01.937358 RX Delay -130 -> 252, step: 16
1947 23:03:01.940939 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1948 23:03:01.944388 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1949 23:03:01.951350 iDelay=222, Bit 2, Center 61 (-66 ~ 189) 256
1950 23:03:01.954198 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1951 23:03:01.957534 iDelay=222, Bit 4, Center 69 (-50 ~ 189) 240
1952 23:03:01.961040 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1953 23:03:01.964125 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1954 23:03:01.967791 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1955 23:03:01.974496 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1956 23:03:01.977437 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1957 23:03:01.980775 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1958 23:03:01.984556 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1959 23:03:01.990815 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1960 23:03:01.994405 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1961 23:03:01.997476 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1962 23:03:02.000793 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1963 23:03:02.000876 ==
1964 23:03:02.004072 Dram Type= 6, Freq= 0, CH_1, rank 1
1965 23:03:02.007991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1966 23:03:02.011203 ==
1967 23:03:02.011285 DQS Delay:
1968 23:03:02.011349 DQS0 = 0, DQS1 = 0
1969 23:03:02.014471 DQM Delay:
1970 23:03:02.014552 DQM0 = 76, DQM1 = 71
1971 23:03:02.017523 DQ Delay:
1972 23:03:02.017604 DQ0 =77, DQ1 =69, DQ2 =61, DQ3 =77
1973 23:03:02.021102 DQ4 =69, DQ5 =85, DQ6 =93, DQ7 =77
1974 23:03:02.024187 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =61
1975 23:03:02.027749 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1976 23:03:02.027818
1977 23:03:02.027886
1978 23:03:02.031240 ==
1979 23:03:02.034495 Dram Type= 6, Freq= 0, CH_1, rank 1
1980 23:03:02.037716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1981 23:03:02.037801 ==
1982 23:03:02.037913
1983 23:03:02.037990
1984 23:03:02.041094 TX Vref Scan disable
1985 23:03:02.041170 == TX Byte 0 ==
1986 23:03:02.045019 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1987 23:03:02.051007 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1988 23:03:02.051092 == TX Byte 1 ==
1989 23:03:02.054947 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1990 23:03:02.060995 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1991 23:03:02.061091 ==
1992 23:03:02.064318 Dram Type= 6, Freq= 0, CH_1, rank 1
1993 23:03:02.067718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1994 23:03:02.067803 ==
1995 23:03:02.080766 TX Vref=22, minBit 0, minWin=28, winSum=451
1996 23:03:02.084561 TX Vref=24, minBit 1, minWin=28, winSum=454
1997 23:03:02.087512 TX Vref=26, minBit 1, minWin=28, winSum=457
1998 23:03:02.090798 TX Vref=28, minBit 0, minWin=28, winSum=457
1999 23:03:02.094363 TX Vref=30, minBit 5, minWin=27, winSum=460
2000 23:03:02.097644 TX Vref=32, minBit 5, minWin=27, winSum=457
2001 23:03:02.104309 [TxChooseVref] Worse bit 1, Min win 28, Win sum 457, Final Vref 26
2002 23:03:02.104396
2003 23:03:02.107539 Final TX Range 1 Vref 26
2004 23:03:02.107613
2005 23:03:02.107673 ==
2006 23:03:02.111268 Dram Type= 6, Freq= 0, CH_1, rank 1
2007 23:03:02.114168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2008 23:03:02.114243 ==
2009 23:03:02.114305
2010 23:03:02.117342
2011 23:03:02.117443 TX Vref Scan disable
2012 23:03:02.121108 == TX Byte 0 ==
2013 23:03:02.124111 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2014 23:03:02.127712 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2015 23:03:02.131190 == TX Byte 1 ==
2016 23:03:02.134191 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2017 23:03:02.137574 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2018 23:03:02.137674
2019 23:03:02.140947 [DATLAT]
2020 23:03:02.141026 Freq=800, CH1 RK1
2021 23:03:02.141095
2022 23:03:02.144363 DATLAT Default: 0xa
2023 23:03:02.144443 0, 0xFFFF, sum = 0
2024 23:03:02.148071 1, 0xFFFF, sum = 0
2025 23:03:02.148184 2, 0xFFFF, sum = 0
2026 23:03:02.150655 3, 0xFFFF, sum = 0
2027 23:03:02.150732 4, 0xFFFF, sum = 0
2028 23:03:02.154409 5, 0xFFFF, sum = 0
2029 23:03:02.154483 6, 0xFFFF, sum = 0
2030 23:03:02.157613 7, 0xFFFF, sum = 0
2031 23:03:02.160496 8, 0xFFFF, sum = 0
2032 23:03:02.160571 9, 0x0, sum = 1
2033 23:03:02.160633 10, 0x0, sum = 2
2034 23:03:02.163935 11, 0x0, sum = 3
2035 23:03:02.164012 12, 0x0, sum = 4
2036 23:03:02.167659 best_step = 10
2037 23:03:02.167733
2038 23:03:02.167795 ==
2039 23:03:02.170669 Dram Type= 6, Freq= 0, CH_1, rank 1
2040 23:03:02.174283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2041 23:03:02.174358 ==
2042 23:03:02.177899 RX Vref Scan: 0
2043 23:03:02.177998
2044 23:03:02.178093 RX Vref 0 -> 0, step: 1
2045 23:03:02.178181
2046 23:03:02.181280 RX Delay -111 -> 252, step: 8
2047 23:03:02.187378 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
2048 23:03:02.190753 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2049 23:03:02.193929 iDelay=209, Bit 2, Center 68 (-55 ~ 192) 248
2050 23:03:02.197341 iDelay=209, Bit 3, Center 76 (-47 ~ 200) 248
2051 23:03:02.200592 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
2052 23:03:02.207911 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2053 23:03:02.211000 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2054 23:03:02.214180 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2055 23:03:02.217261 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
2056 23:03:02.220786 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2057 23:03:02.227627 iDelay=209, Bit 10, Center 76 (-47 ~ 200) 248
2058 23:03:02.230867 iDelay=209, Bit 11, Center 72 (-47 ~ 192) 240
2059 23:03:02.234092 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2060 23:03:02.237781 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2061 23:03:02.240922 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
2062 23:03:02.247658 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2063 23:03:02.247798 ==
2064 23:03:02.250864 Dram Type= 6, Freq= 0, CH_1, rank 1
2065 23:03:02.254350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2066 23:03:02.254428 ==
2067 23:03:02.254490 DQS Delay:
2068 23:03:02.257755 DQS0 = 0, DQS1 = 0
2069 23:03:02.257837 DQM Delay:
2070 23:03:02.261089 DQM0 = 78, DQM1 = 74
2071 23:03:02.261173 DQ Delay:
2072 23:03:02.264151 DQ0 =80, DQ1 =72, DQ2 =68, DQ3 =76
2073 23:03:02.267848 DQ4 =76, DQ5 =88, DQ6 =92, DQ7 =76
2074 23:03:02.270832 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =72
2075 23:03:02.274003 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =80
2076 23:03:02.274126
2077 23:03:02.274195
2078 23:03:02.280943 [DQSOSCAuto] RK1, (LSB)MR18= 0x2038, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 401 ps
2079 23:03:02.283935 CH1 RK1: MR19=606, MR18=2038
2080 23:03:02.290508 CH1_RK1: MR19=0x606, MR18=0x2038, DQSOSC=395, MR23=63, INC=94, DEC=63
2081 23:03:02.294178 [RxdqsGatingPostProcess] freq 800
2082 23:03:02.300819 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2083 23:03:02.303836 Pre-setting of DQS Precalculation
2084 23:03:02.307547 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2085 23:03:02.314079 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2086 23:03:02.320614 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2087 23:03:02.320727
2088 23:03:02.324116
2089 23:03:02.324258 [Calibration Summary] 1600 Mbps
2090 23:03:02.327099 CH 0, Rank 0
2091 23:03:02.327211 SW Impedance : PASS
2092 23:03:02.330665 DUTY Scan : NO K
2093 23:03:02.333770 ZQ Calibration : PASS
2094 23:03:02.333852 Jitter Meter : NO K
2095 23:03:02.337084 CBT Training : PASS
2096 23:03:02.340741 Write leveling : PASS
2097 23:03:02.340832 RX DQS gating : PASS
2098 23:03:02.344177 RX DQ/DQS(RDDQC) : PASS
2099 23:03:02.347534 TX DQ/DQS : PASS
2100 23:03:02.347623 RX DATLAT : PASS
2101 23:03:02.350552 RX DQ/DQS(Engine): PASS
2102 23:03:02.350638 TX OE : NO K
2103 23:03:02.354260 All Pass.
2104 23:03:02.354346
2105 23:03:02.354411 CH 0, Rank 1
2106 23:03:02.357499 SW Impedance : PASS
2107 23:03:02.357584 DUTY Scan : NO K
2108 23:03:02.360534 ZQ Calibration : PASS
2109 23:03:02.363778 Jitter Meter : NO K
2110 23:03:02.363863 CBT Training : PASS
2111 23:03:02.367223 Write leveling : PASS
2112 23:03:02.370556 RX DQS gating : PASS
2113 23:03:02.370637 RX DQ/DQS(RDDQC) : PASS
2114 23:03:02.373920 TX DQ/DQS : PASS
2115 23:03:02.377365 RX DATLAT : PASS
2116 23:03:02.377446 RX DQ/DQS(Engine): PASS
2117 23:03:02.380635 TX OE : NO K
2118 23:03:02.380717 All Pass.
2119 23:03:02.380782
2120 23:03:02.384099 CH 1, Rank 0
2121 23:03:02.384231 SW Impedance : PASS
2122 23:03:02.387290 DUTY Scan : NO K
2123 23:03:02.390591 ZQ Calibration : PASS
2124 23:03:02.390681 Jitter Meter : NO K
2125 23:03:02.393992 CBT Training : PASS
2126 23:03:02.397373 Write leveling : PASS
2127 23:03:02.397455 RX DQS gating : PASS
2128 23:03:02.400635 RX DQ/DQS(RDDQC) : PASS
2129 23:03:02.400717 TX DQ/DQS : PASS
2130 23:03:02.404098 RX DATLAT : PASS
2131 23:03:02.407312 RX DQ/DQS(Engine): PASS
2132 23:03:02.407393 TX OE : NO K
2133 23:03:02.410624 All Pass.
2134 23:03:02.410738
2135 23:03:02.410802 CH 1, Rank 1
2136 23:03:02.414389 SW Impedance : PASS
2137 23:03:02.414500 DUTY Scan : NO K
2138 23:03:02.417333 ZQ Calibration : PASS
2139 23:03:02.420794 Jitter Meter : NO K
2140 23:03:02.420877 CBT Training : PASS
2141 23:03:02.424740 Write leveling : PASS
2142 23:03:02.427578 RX DQS gating : PASS
2143 23:03:02.427661 RX DQ/DQS(RDDQC) : PASS
2144 23:03:02.430752 TX DQ/DQS : PASS
2145 23:03:02.430834 RX DATLAT : PASS
2146 23:03:02.434354 RX DQ/DQS(Engine): PASS
2147 23:03:02.437643 TX OE : NO K
2148 23:03:02.437726 All Pass.
2149 23:03:02.437790
2150 23:03:02.440604 DramC Write-DBI off
2151 23:03:02.440687 PER_BANK_REFRESH: Hybrid Mode
2152 23:03:02.444300 TX_TRACKING: ON
2153 23:03:02.447375 [GetDramInforAfterCalByMRR] Vendor 6.
2154 23:03:02.450667 [GetDramInforAfterCalByMRR] Revision 606.
2155 23:03:02.454228 [GetDramInforAfterCalByMRR] Revision 2 0.
2156 23:03:02.454312 MR0 0x3b3b
2157 23:03:02.457328 MR8 0x5151
2158 23:03:02.460675 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2159 23:03:02.460758
2160 23:03:02.460822 MR0 0x3b3b
2161 23:03:02.464186 MR8 0x5151
2162 23:03:02.467571 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2163 23:03:02.467653
2164 23:03:02.474498 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2165 23:03:02.477261 [FAST_K] Save calibration result to emmc
2166 23:03:02.484205 [FAST_K] Save calibration result to emmc
2167 23:03:02.484295 dram_init: config_dvfs: 1
2168 23:03:02.487577 dramc_set_vcore_voltage set vcore to 662500
2169 23:03:02.490882 Read voltage for 1200, 2
2170 23:03:02.490964 Vio18 = 0
2171 23:03:02.494039 Vcore = 662500
2172 23:03:02.494136 Vdram = 0
2173 23:03:02.494200 Vddq = 0
2174 23:03:02.497517 Vmddr = 0
2175 23:03:02.501078 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2176 23:03:02.507537 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2177 23:03:02.507620 MEM_TYPE=3, freq_sel=15
2178 23:03:02.510978 sv_algorithm_assistance_LP4_1600
2179 23:03:02.517420 ============ PULL DRAM RESETB DOWN ============
2180 23:03:02.521122 ========== PULL DRAM RESETB DOWN end =========
2181 23:03:02.524001 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2182 23:03:02.527414 ===================================
2183 23:03:02.530548 LPDDR4 DRAM CONFIGURATION
2184 23:03:02.534510 ===================================
2185 23:03:02.534591 EX_ROW_EN[0] = 0x0
2186 23:03:02.537487 EX_ROW_EN[1] = 0x0
2187 23:03:02.540591 LP4Y_EN = 0x0
2188 23:03:02.540674 WORK_FSP = 0x0
2189 23:03:02.544177 WL = 0x4
2190 23:03:02.544300 RL = 0x4
2191 23:03:02.547339 BL = 0x2
2192 23:03:02.547419 RPST = 0x0
2193 23:03:02.550895 RD_PRE = 0x0
2194 23:03:02.550976 WR_PRE = 0x1
2195 23:03:02.554193 WR_PST = 0x0
2196 23:03:02.554275 DBI_WR = 0x0
2197 23:03:02.557316 DBI_RD = 0x0
2198 23:03:02.557397 OTF = 0x1
2199 23:03:02.560538 ===================================
2200 23:03:02.563987 ===================================
2201 23:03:02.567431 ANA top config
2202 23:03:02.570886 ===================================
2203 23:03:02.570969 DLL_ASYNC_EN = 0
2204 23:03:02.573870 ALL_SLAVE_EN = 0
2205 23:03:02.577384 NEW_RANK_MODE = 1
2206 23:03:02.580704 DLL_IDLE_MODE = 1
2207 23:03:02.580786 LP45_APHY_COMB_EN = 1
2208 23:03:02.584296 TX_ODT_DIS = 1
2209 23:03:02.587358 NEW_8X_MODE = 1
2210 23:03:02.590702 ===================================
2211 23:03:02.593959 ===================================
2212 23:03:02.597501 data_rate = 2400
2213 23:03:02.600677 CKR = 1
2214 23:03:02.603972 DQ_P2S_RATIO = 8
2215 23:03:02.607735 ===================================
2216 23:03:02.607826 CA_P2S_RATIO = 8
2217 23:03:02.610829 DQ_CA_OPEN = 0
2218 23:03:02.614108 DQ_SEMI_OPEN = 0
2219 23:03:02.617633 CA_SEMI_OPEN = 0
2220 23:03:02.620747 CA_FULL_RATE = 0
2221 23:03:02.620834 DQ_CKDIV4_EN = 0
2222 23:03:02.623855 CA_CKDIV4_EN = 0
2223 23:03:02.627428 CA_PREDIV_EN = 0
2224 23:03:02.630992 PH8_DLY = 17
2225 23:03:02.633990 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2226 23:03:02.637326 DQ_AAMCK_DIV = 4
2227 23:03:02.637407 CA_AAMCK_DIV = 4
2228 23:03:02.640851 CA_ADMCK_DIV = 4
2229 23:03:02.644333 DQ_TRACK_CA_EN = 0
2230 23:03:02.647587 CA_PICK = 1200
2231 23:03:02.650784 CA_MCKIO = 1200
2232 23:03:02.654471 MCKIO_SEMI = 0
2233 23:03:02.657801 PLL_FREQ = 2366
2234 23:03:02.661064 DQ_UI_PI_RATIO = 32
2235 23:03:02.661146 CA_UI_PI_RATIO = 0
2236 23:03:02.664024 ===================================
2237 23:03:02.667341 ===================================
2238 23:03:02.670768 memory_type:LPDDR4
2239 23:03:02.674133 GP_NUM : 10
2240 23:03:02.674215 SRAM_EN : 1
2241 23:03:02.677498 MD32_EN : 0
2242 23:03:02.681133 ===================================
2243 23:03:02.684052 [ANA_INIT] >>>>>>>>>>>>>>
2244 23:03:02.684148 <<<<<< [CONFIGURE PHASE]: ANA_TX
2245 23:03:02.687353 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2246 23:03:02.690722 ===================================
2247 23:03:02.694014 data_rate = 2400,PCW = 0X5b00
2248 23:03:02.697507 ===================================
2249 23:03:02.700994 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2250 23:03:02.707820 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2251 23:03:02.714531 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2252 23:03:02.717603 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2253 23:03:02.720846 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2254 23:03:02.724316 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2255 23:03:02.727575 [ANA_INIT] flow start
2256 23:03:02.727654 [ANA_INIT] PLL >>>>>>>>
2257 23:03:02.730766 [ANA_INIT] PLL <<<<<<<<
2258 23:03:02.734155 [ANA_INIT] MIDPI >>>>>>>>
2259 23:03:02.734267 [ANA_INIT] MIDPI <<<<<<<<
2260 23:03:02.737968 [ANA_INIT] DLL >>>>>>>>
2261 23:03:02.740953 [ANA_INIT] DLL <<<<<<<<
2262 23:03:02.741061 [ANA_INIT] flow end
2263 23:03:02.747663 ============ LP4 DIFF to SE enter ============
2264 23:03:02.750893 ============ LP4 DIFF to SE exit ============
2265 23:03:02.750997 [ANA_INIT] <<<<<<<<<<<<<
2266 23:03:02.754439 [Flow] Enable top DCM control >>>>>
2267 23:03:02.757716 [Flow] Enable top DCM control <<<<<
2268 23:03:02.760955 Enable DLL master slave shuffle
2269 23:03:02.767483 ==============================================================
2270 23:03:02.770576 Gating Mode config
2271 23:03:02.774185 ==============================================================
2272 23:03:02.777512 Config description:
2273 23:03:02.787462 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2274 23:03:02.794040 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2275 23:03:02.797134 SELPH_MODE 0: By rank 1: By Phase
2276 23:03:02.803990 ==============================================================
2277 23:03:02.807473 GAT_TRACK_EN = 1
2278 23:03:02.810308 RX_GATING_MODE = 2
2279 23:03:02.813757 RX_GATING_TRACK_MODE = 2
2280 23:03:02.817111 SELPH_MODE = 1
2281 23:03:02.817195 PICG_EARLY_EN = 1
2282 23:03:02.820607 VALID_LAT_VALUE = 1
2283 23:03:02.827421 ==============================================================
2284 23:03:02.830429 Enter into Gating configuration >>>>
2285 23:03:02.833560 Exit from Gating configuration <<<<
2286 23:03:02.837035 Enter into DVFS_PRE_config >>>>>
2287 23:03:02.846826 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2288 23:03:02.850345 Exit from DVFS_PRE_config <<<<<
2289 23:03:02.853529 Enter into PICG configuration >>>>
2290 23:03:02.857150 Exit from PICG configuration <<<<
2291 23:03:02.860328 [RX_INPUT] configuration >>>>>
2292 23:03:02.863660 [RX_INPUT] configuration <<<<<
2293 23:03:02.867387 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2294 23:03:02.873505 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2295 23:03:02.880086 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2296 23:03:02.886741 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2297 23:03:02.893987 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2298 23:03:02.896965 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2299 23:03:02.903502 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2300 23:03:02.906702 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2301 23:03:02.910239 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2302 23:03:02.913330 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2303 23:03:02.916920 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2304 23:03:02.923862 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2305 23:03:02.926828 ===================================
2306 23:03:02.930465 LPDDR4 DRAM CONFIGURATION
2307 23:03:02.933497 ===================================
2308 23:03:02.933579 EX_ROW_EN[0] = 0x0
2309 23:03:02.936967 EX_ROW_EN[1] = 0x0
2310 23:03:02.937047 LP4Y_EN = 0x0
2311 23:03:02.939954 WORK_FSP = 0x0
2312 23:03:02.940035 WL = 0x4
2313 23:03:02.943429 RL = 0x4
2314 23:03:02.943510 BL = 0x2
2315 23:03:02.946689 RPST = 0x0
2316 23:03:02.946776 RD_PRE = 0x0
2317 23:03:02.950349 WR_PRE = 0x1
2318 23:03:02.950429 WR_PST = 0x0
2319 23:03:02.953888 DBI_WR = 0x0
2320 23:03:02.953969 DBI_RD = 0x0
2321 23:03:02.956748 OTF = 0x1
2322 23:03:02.960071 ===================================
2323 23:03:02.963572 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2324 23:03:02.967159 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2325 23:03:02.974134 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2326 23:03:02.976818 ===================================
2327 23:03:02.976899 LPDDR4 DRAM CONFIGURATION
2328 23:03:02.980562 ===================================
2329 23:03:02.983658 EX_ROW_EN[0] = 0x10
2330 23:03:02.986771 EX_ROW_EN[1] = 0x0
2331 23:03:02.986851 LP4Y_EN = 0x0
2332 23:03:02.990229 WORK_FSP = 0x0
2333 23:03:02.990310 WL = 0x4
2334 23:03:02.993303 RL = 0x4
2335 23:03:02.993383 BL = 0x2
2336 23:03:02.996601 RPST = 0x0
2337 23:03:02.996681 RD_PRE = 0x0
2338 23:03:03.000209 WR_PRE = 0x1
2339 23:03:03.000291 WR_PST = 0x0
2340 23:03:03.003292 DBI_WR = 0x0
2341 23:03:03.003372 DBI_RD = 0x0
2342 23:03:03.007036 OTF = 0x1
2343 23:03:03.010314 ===================================
2344 23:03:03.017072 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2345 23:03:03.017154 ==
2346 23:03:03.020081 Dram Type= 6, Freq= 0, CH_0, rank 0
2347 23:03:03.023776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2348 23:03:03.023859 ==
2349 23:03:03.027083 [Duty_Offset_Calibration]
2350 23:03:03.027164 B0:2 B1:0 CA:3
2351 23:03:03.027227
2352 23:03:03.029932 [DutyScan_Calibration_Flow] k_type=0
2353 23:03:03.040050
2354 23:03:03.040163 ==CLK 0==
2355 23:03:03.043264 Final CLK duty delay cell = 0
2356 23:03:03.047159 [0] MAX Duty = 5031%(X100), DQS PI = 28
2357 23:03:03.050137 [0] MIN Duty = 4875%(X100), DQS PI = 58
2358 23:03:03.050212 [0] AVG Duty = 4953%(X100)
2359 23:03:03.053585
2360 23:03:03.056740 CH0 CLK Duty spec in!! Max-Min= 156%
2361 23:03:03.060028 [DutyScan_Calibration_Flow] ====Done====
2362 23:03:03.060125
2363 23:03:03.063730 [DutyScan_Calibration_Flow] k_type=1
2364 23:03:03.079039
2365 23:03:03.079137 ==DQS 0 ==
2366 23:03:03.082071 Final DQS duty delay cell = 0
2367 23:03:03.085452 [0] MAX Duty = 5093%(X100), DQS PI = 28
2368 23:03:03.088854 [0] MIN Duty = 4907%(X100), DQS PI = 2
2369 23:03:03.088962 [0] AVG Duty = 5000%(X100)
2370 23:03:03.091807
2371 23:03:03.091904 ==DQS 1 ==
2372 23:03:03.095527 Final DQS duty delay cell = -4
2373 23:03:03.098694 [-4] MAX Duty = 4969%(X100), DQS PI = 6
2374 23:03:03.102395 [-4] MIN Duty = 4875%(X100), DQS PI = 16
2375 23:03:03.105444 [-4] AVG Duty = 4922%(X100)
2376 23:03:03.105524
2377 23:03:03.108824 CH0 DQS 0 Duty spec in!! Max-Min= 186%
2378 23:03:03.108905
2379 23:03:03.112230 CH0 DQS 1 Duty spec in!! Max-Min= 94%
2380 23:03:03.115337 [DutyScan_Calibration_Flow] ====Done====
2381 23:03:03.115418
2382 23:03:03.118457 [DutyScan_Calibration_Flow] k_type=3
2383 23:03:03.136158
2384 23:03:03.136280 ==DQM 0 ==
2385 23:03:03.139257 Final DQM duty delay cell = 0
2386 23:03:03.142766 [0] MAX Duty = 5124%(X100), DQS PI = 28
2387 23:03:03.146270 [0] MIN Duty = 4876%(X100), DQS PI = 0
2388 23:03:03.146350 [0] AVG Duty = 5000%(X100)
2389 23:03:03.149154
2390 23:03:03.149268 ==DQM 1 ==
2391 23:03:03.152595 Final DQM duty delay cell = 4
2392 23:03:03.156313 [4] MAX Duty = 5124%(X100), DQS PI = 50
2393 23:03:03.159517 [4] MIN Duty = 5000%(X100), DQS PI = 30
2394 23:03:03.159600 [4] AVG Duty = 5062%(X100)
2395 23:03:03.162657
2396 23:03:03.166288 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2397 23:03:03.166371
2398 23:03:03.169706 CH0 DQM 1 Duty spec in!! Max-Min= 124%
2399 23:03:03.172922 [DutyScan_Calibration_Flow] ====Done====
2400 23:03:03.173004
2401 23:03:03.176048 [DutyScan_Calibration_Flow] k_type=2
2402 23:03:03.191040
2403 23:03:03.191140 ==DQ 0 ==
2404 23:03:03.194133 Final DQ duty delay cell = -4
2405 23:03:03.197575 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2406 23:03:03.201235 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2407 23:03:03.204430 [-4] AVG Duty = 4969%(X100)
2408 23:03:03.204507
2409 23:03:03.204569 ==DQ 1 ==
2410 23:03:03.207466 Final DQ duty delay cell = -4
2411 23:03:03.211328 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2412 23:03:03.214342 [-4] MIN Duty = 4876%(X100), DQS PI = 20
2413 23:03:03.217493 [-4] AVG Duty = 4938%(X100)
2414 23:03:03.217574
2415 23:03:03.221309 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2416 23:03:03.221390
2417 23:03:03.224526 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2418 23:03:03.228040 [DutyScan_Calibration_Flow] ====Done====
2419 23:03:03.228121 ==
2420 23:03:03.231076 Dram Type= 6, Freq= 0, CH_1, rank 0
2421 23:03:03.234217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2422 23:03:03.234300 ==
2423 23:03:03.237770 [Duty_Offset_Calibration]
2424 23:03:03.237855 B0:1 B1:-2 CA:0
2425 23:03:03.237920
2426 23:03:03.240726 [DutyScan_Calibration_Flow] k_type=0
2427 23:03:03.251388
2428 23:03:03.251474 ==CLK 0==
2429 23:03:03.255190 Final CLK duty delay cell = 0
2430 23:03:03.258033 [0] MAX Duty = 5031%(X100), DQS PI = 18
2431 23:03:03.261794 [0] MIN Duty = 4875%(X100), DQS PI = 58
2432 23:03:03.261877 [0] AVG Duty = 4953%(X100)
2433 23:03:03.265212
2434 23:03:03.268579 CH1 CLK Duty spec in!! Max-Min= 156%
2435 23:03:03.271400 [DutyScan_Calibration_Flow] ====Done====
2436 23:03:03.271482
2437 23:03:03.274760 [DutyScan_Calibration_Flow] k_type=1
2438 23:03:03.290310
2439 23:03:03.290416 ==DQS 0 ==
2440 23:03:03.293342 Final DQS duty delay cell = -4
2441 23:03:03.296636 [-4] MAX Duty = 5000%(X100), DQS PI = 24
2442 23:03:03.300492 [-4] MIN Duty = 4907%(X100), DQS PI = 2
2443 23:03:03.303729 [-4] AVG Duty = 4953%(X100)
2444 23:03:03.303811
2445 23:03:03.303876 ==DQS 1 ==
2446 23:03:03.306577 Final DQS duty delay cell = 0
2447 23:03:03.310121 [0] MAX Duty = 5093%(X100), DQS PI = 0
2448 23:03:03.313725 [0] MIN Duty = 4875%(X100), DQS PI = 26
2449 23:03:03.316942 [0] AVG Duty = 4984%(X100)
2450 23:03:03.317027
2451 23:03:03.320023 CH1 DQS 0 Duty spec in!! Max-Min= 93%
2452 23:03:03.320106
2453 23:03:03.323180 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2454 23:03:03.326525 [DutyScan_Calibration_Flow] ====Done====
2455 23:03:03.326609
2456 23:03:03.330262 [DutyScan_Calibration_Flow] k_type=3
2457 23:03:03.346779
2458 23:03:03.346937 ==DQM 0 ==
2459 23:03:03.349935 Final DQM duty delay cell = 0
2460 23:03:03.353157 [0] MAX Duty = 5000%(X100), DQS PI = 22
2461 23:03:03.356799 [0] MIN Duty = 4844%(X100), DQS PI = 56
2462 23:03:03.356900 [0] AVG Duty = 4922%(X100)
2463 23:03:03.359880
2464 23:03:03.359998 ==DQM 1 ==
2465 23:03:03.363244 Final DQM duty delay cell = 0
2466 23:03:03.366571 [0] MAX Duty = 5031%(X100), DQS PI = 36
2467 23:03:03.369930 [0] MIN Duty = 4907%(X100), DQS PI = 2
2468 23:03:03.370036 [0] AVG Duty = 4969%(X100)
2469 23:03:03.373033
2470 23:03:03.376697 CH1 DQM 0 Duty spec in!! Max-Min= 156%
2471 23:03:03.376791
2472 23:03:03.379928 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2473 23:03:03.383027 [DutyScan_Calibration_Flow] ====Done====
2474 23:03:03.383171
2475 23:03:03.386197 [DutyScan_Calibration_Flow] k_type=2
2476 23:03:03.402924
2477 23:03:03.403075 ==DQ 0 ==
2478 23:03:03.406173 Final DQ duty delay cell = 0
2479 23:03:03.409737 [0] MAX Duty = 5062%(X100), DQS PI = 12
2480 23:03:03.413091 [0] MIN Duty = 4938%(X100), DQS PI = 54
2481 23:03:03.413216 [0] AVG Duty = 5000%(X100)
2482 23:03:03.416298
2483 23:03:03.416390 ==DQ 1 ==
2484 23:03:03.419490 Final DQ duty delay cell = 0
2485 23:03:03.422707 [0] MAX Duty = 5093%(X100), DQS PI = 20
2486 23:03:03.426071 [0] MIN Duty = 4969%(X100), DQS PI = 26
2487 23:03:03.426162 [0] AVG Duty = 5031%(X100)
2488 23:03:03.426228
2489 23:03:03.429929 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2490 23:03:03.433109
2491 23:03:03.436386 CH1 DQ 1 Duty spec in!! Max-Min= 124%
2492 23:03:03.439965 [DutyScan_Calibration_Flow] ====Done====
2493 23:03:03.443014 nWR fixed to 30
2494 23:03:03.443101 [ModeRegInit_LP4] CH0 RK0
2495 23:03:03.446119 [ModeRegInit_LP4] CH0 RK1
2496 23:03:03.449740 [ModeRegInit_LP4] CH1 RK0
2497 23:03:03.449823 [ModeRegInit_LP4] CH1 RK1
2498 23:03:03.453088 match AC timing 7
2499 23:03:03.456123 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2500 23:03:03.459701 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2501 23:03:03.466328 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2502 23:03:03.469433 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2503 23:03:03.476083 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2504 23:03:03.476193 ==
2505 23:03:03.479494 Dram Type= 6, Freq= 0, CH_0, rank 0
2506 23:03:03.482928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2507 23:03:03.483012 ==
2508 23:03:03.489532 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2509 23:03:03.492870 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2510 23:03:03.503236 [CA 0] Center 40 (10~71) winsize 62
2511 23:03:03.506064 [CA 1] Center 39 (9~70) winsize 62
2512 23:03:03.509825 [CA 2] Center 36 (6~66) winsize 61
2513 23:03:03.513025 [CA 3] Center 35 (5~66) winsize 62
2514 23:03:03.516327 [CA 4] Center 34 (4~65) winsize 62
2515 23:03:03.520101 [CA 5] Center 33 (3~63) winsize 61
2516 23:03:03.520183
2517 23:03:03.522803 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2518 23:03:03.522884
2519 23:03:03.526375 [CATrainingPosCal] consider 1 rank data
2520 23:03:03.529473 u2DelayCellTimex100 = 270/100 ps
2521 23:03:03.533135 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2522 23:03:03.539449 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2523 23:03:03.542863 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2524 23:03:03.545970 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2525 23:03:03.549790 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2526 23:03:03.552847 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2527 23:03:03.552929
2528 23:03:03.556013 CA PerBit enable=1, Macro0, CA PI delay=33
2529 23:03:03.556095
2530 23:03:03.559318 [CBTSetCACLKResult] CA Dly = 33
2531 23:03:03.562896 CS Dly: 7 (0~38)
2532 23:03:03.562977 ==
2533 23:03:03.566059 Dram Type= 6, Freq= 0, CH_0, rank 1
2534 23:03:03.569584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2535 23:03:03.569667 ==
2536 23:03:03.575889 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2537 23:03:03.579230 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2538 23:03:03.589362 [CA 0] Center 40 (10~70) winsize 61
2539 23:03:03.592569 [CA 1] Center 39 (9~70) winsize 62
2540 23:03:03.596010 [CA 2] Center 35 (5~66) winsize 62
2541 23:03:03.599232 [CA 3] Center 35 (5~66) winsize 62
2542 23:03:03.602217 [CA 4] Center 34 (4~65) winsize 62
2543 23:03:03.605897 [CA 5] Center 33 (3~64) winsize 62
2544 23:03:03.605993
2545 23:03:03.609217 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2546 23:03:03.609299
2547 23:03:03.612654 [CATrainingPosCal] consider 2 rank data
2548 23:03:03.615891 u2DelayCellTimex100 = 270/100 ps
2549 23:03:03.619493 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2550 23:03:03.626059 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2551 23:03:03.629483 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2552 23:03:03.632439 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2553 23:03:03.636060 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2554 23:03:03.639135 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2555 23:03:03.639217
2556 23:03:03.642599 CA PerBit enable=1, Macro0, CA PI delay=33
2557 23:03:03.642681
2558 23:03:03.645620 [CBTSetCACLKResult] CA Dly = 33
2559 23:03:03.645703 CS Dly: 8 (0~40)
2560 23:03:03.649057
2561 23:03:03.652591 ----->DramcWriteLeveling(PI) begin...
2562 23:03:03.652675 ==
2563 23:03:03.656015 Dram Type= 6, Freq= 0, CH_0, rank 0
2564 23:03:03.659175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2565 23:03:03.659258 ==
2566 23:03:03.662495 Write leveling (Byte 0): 32 => 32
2567 23:03:03.665632 Write leveling (Byte 1): 30 => 30
2568 23:03:03.669293 DramcWriteLeveling(PI) end<-----
2569 23:03:03.669377
2570 23:03:03.669441 ==
2571 23:03:03.672633 Dram Type= 6, Freq= 0, CH_0, rank 0
2572 23:03:03.676085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2573 23:03:03.676168 ==
2574 23:03:03.679064 [Gating] SW mode calibration
2575 23:03:03.685605 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2576 23:03:03.692480 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2577 23:03:03.695651 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2578 23:03:03.699339 0 15 4 | B1->B0 | 2b2b 3434 | 1 1 | (0 0) (1 1)
2579 23:03:03.705869 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2580 23:03:03.709199 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2581 23:03:03.712157 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2582 23:03:03.715396 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2583 23:03:03.722727 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2584 23:03:03.725605 0 15 28 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
2585 23:03:03.728783 1 0 0 | B1->B0 | 3232 2d2d | 1 0 | (1 0) (0 1)
2586 23:03:03.735426 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2587 23:03:03.738879 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2588 23:03:03.742031 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2589 23:03:03.748773 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2590 23:03:03.752101 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2591 23:03:03.755703 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2592 23:03:03.761999 1 0 28 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
2593 23:03:03.765563 1 1 0 | B1->B0 | 2626 3333 | 0 1 | (0 0) (0 0)
2594 23:03:03.769107 1 1 4 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
2595 23:03:03.775562 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2596 23:03:03.778834 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2597 23:03:03.782138 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2598 23:03:03.788897 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2599 23:03:03.792166 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2600 23:03:03.795657 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2601 23:03:03.802287 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2602 23:03:03.805650 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2603 23:03:03.809466 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2604 23:03:03.815741 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2605 23:03:03.818776 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2606 23:03:03.822179 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2607 23:03:03.825310 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2608 23:03:03.832121 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2609 23:03:03.835615 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2610 23:03:03.839093 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 23:03:03.845733 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 23:03:03.848639 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 23:03:03.852007 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 23:03:03.859058 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 23:03:03.862460 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 23:03:03.865458 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 23:03:03.872024 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2618 23:03:03.875658 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2619 23:03:03.879076 Total UI for P1: 0, mck2ui 16
2620 23:03:03.882119 best dqsien dly found for B0: ( 1, 4, 0)
2621 23:03:03.885372 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2622 23:03:03.889319 Total UI for P1: 0, mck2ui 16
2623 23:03:03.892160 best dqsien dly found for B1: ( 1, 4, 2)
2624 23:03:03.895573 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2625 23:03:03.898670 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2626 23:03:03.898752
2627 23:03:03.902197 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2628 23:03:03.908908 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2629 23:03:03.908991 [Gating] SW calibration Done
2630 23:03:03.909057 ==
2631 23:03:03.912076 Dram Type= 6, Freq= 0, CH_0, rank 0
2632 23:03:03.918978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2633 23:03:03.919069 ==
2634 23:03:03.919135 RX Vref Scan: 0
2635 23:03:03.919195
2636 23:03:03.922354 RX Vref 0 -> 0, step: 1
2637 23:03:03.922435
2638 23:03:03.925339 RX Delay -40 -> 252, step: 8
2639 23:03:03.928827 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2640 23:03:03.932088 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
2641 23:03:03.935506 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2642 23:03:03.938853 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2643 23:03:03.945295 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2644 23:03:03.948585 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2645 23:03:03.952009 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2646 23:03:03.955281 iDelay=200, Bit 7, Center 119 (40 ~ 199) 160
2647 23:03:03.958630 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2648 23:03:03.965280 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2649 23:03:03.968627 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2650 23:03:03.971969 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2651 23:03:03.975737 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2652 23:03:03.978659 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2653 23:03:03.985401 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2654 23:03:03.988624 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2655 23:03:03.988708 ==
2656 23:03:03.992395 Dram Type= 6, Freq= 0, CH_0, rank 0
2657 23:03:03.995393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2658 23:03:03.995476 ==
2659 23:03:03.995540 DQS Delay:
2660 23:03:03.998961 DQS0 = 0, DQS1 = 0
2661 23:03:03.999044 DQM Delay:
2662 23:03:04.002410 DQM0 = 112, DQM1 = 102
2663 23:03:04.002492 DQ Delay:
2664 23:03:04.005460 DQ0 =111, DQ1 =111, DQ2 =115, DQ3 =107
2665 23:03:04.008816 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =119
2666 23:03:04.011797 DQ8 =91, DQ9 =87, DQ10 =103, DQ11 =95
2667 23:03:04.015330 DQ12 =107, DQ13 =107, DQ14 =115, DQ15 =111
2668 23:03:04.015416
2669 23:03:04.018556
2670 23:03:04.018638 ==
2671 23:03:04.022097 Dram Type= 6, Freq= 0, CH_0, rank 0
2672 23:03:04.025573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2673 23:03:04.025657 ==
2674 23:03:04.025721
2675 23:03:04.025781
2676 23:03:04.028978 TX Vref Scan disable
2677 23:03:04.029060 == TX Byte 0 ==
2678 23:03:04.032456 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2679 23:03:04.038726 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2680 23:03:04.038827 == TX Byte 1 ==
2681 23:03:04.042092 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2682 23:03:04.048565 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2683 23:03:04.048651 ==
2684 23:03:04.052149 Dram Type= 6, Freq= 0, CH_0, rank 0
2685 23:03:04.055692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2686 23:03:04.055775 ==
2687 23:03:04.068066 TX Vref=22, minBit 12, minWin=25, winSum=418
2688 23:03:04.071147 TX Vref=24, minBit 1, minWin=26, winSum=425
2689 23:03:04.074180 TX Vref=26, minBit 10, minWin=26, winSum=432
2690 23:03:04.077435 TX Vref=28, minBit 12, minWin=26, winSum=436
2691 23:03:04.081144 TX Vref=30, minBit 10, minWin=26, winSum=433
2692 23:03:04.087462 TX Vref=32, minBit 1, minWin=26, winSum=431
2693 23:03:04.091196 [TxChooseVref] Worse bit 12, Min win 26, Win sum 436, Final Vref 28
2694 23:03:04.091280
2695 23:03:04.093987 Final TX Range 1 Vref 28
2696 23:03:04.094070
2697 23:03:04.094135 ==
2698 23:03:04.097348 Dram Type= 6, Freq= 0, CH_0, rank 0
2699 23:03:04.100665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2700 23:03:04.104154 ==
2701 23:03:04.104262
2702 23:03:04.104327
2703 23:03:04.104388 TX Vref Scan disable
2704 23:03:04.107515 == TX Byte 0 ==
2705 23:03:04.111288 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2706 23:03:04.114297 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2707 23:03:04.117775 == TX Byte 1 ==
2708 23:03:04.120877 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2709 23:03:04.127889 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2710 23:03:04.127973
2711 23:03:04.128036 [DATLAT]
2712 23:03:04.128095 Freq=1200, CH0 RK0
2713 23:03:04.128153
2714 23:03:04.131087 DATLAT Default: 0xd
2715 23:03:04.131168 0, 0xFFFF, sum = 0
2716 23:03:04.134059 1, 0xFFFF, sum = 0
2717 23:03:04.137620 2, 0xFFFF, sum = 0
2718 23:03:04.137702 3, 0xFFFF, sum = 0
2719 23:03:04.141058 4, 0xFFFF, sum = 0
2720 23:03:04.141140 5, 0xFFFF, sum = 0
2721 23:03:04.144591 6, 0xFFFF, sum = 0
2722 23:03:04.144673 7, 0xFFFF, sum = 0
2723 23:03:04.147454 8, 0xFFFF, sum = 0
2724 23:03:04.147536 9, 0xFFFF, sum = 0
2725 23:03:04.150722 10, 0xFFFF, sum = 0
2726 23:03:04.150804 11, 0xFFFF, sum = 0
2727 23:03:04.154384 12, 0x0, sum = 1
2728 23:03:04.154466 13, 0x0, sum = 2
2729 23:03:04.157898 14, 0x0, sum = 3
2730 23:03:04.157981 15, 0x0, sum = 4
2731 23:03:04.158045 best_step = 13
2732 23:03:04.160878
2733 23:03:04.160958 ==
2734 23:03:04.164189 Dram Type= 6, Freq= 0, CH_0, rank 0
2735 23:03:04.167466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2736 23:03:04.167548 ==
2737 23:03:04.167611 RX Vref Scan: 1
2738 23:03:04.167671
2739 23:03:04.171031 Set Vref Range= 32 -> 127
2740 23:03:04.171112
2741 23:03:04.174027 RX Vref 32 -> 127, step: 1
2742 23:03:04.174108
2743 23:03:04.177410 RX Delay -37 -> 252, step: 4
2744 23:03:04.177491
2745 23:03:04.181004 Set Vref, RX VrefLevel [Byte0]: 32
2746 23:03:04.184060 [Byte1]: 32
2747 23:03:04.184183
2748 23:03:04.187841 Set Vref, RX VrefLevel [Byte0]: 33
2749 23:03:04.190971 [Byte1]: 33
2750 23:03:04.194900
2751 23:03:04.194981 Set Vref, RX VrefLevel [Byte0]: 34
2752 23:03:04.197945 [Byte1]: 34
2753 23:03:04.202479
2754 23:03:04.202559 Set Vref, RX VrefLevel [Byte0]: 35
2755 23:03:04.205739 [Byte1]: 35
2756 23:03:04.210573
2757 23:03:04.210654 Set Vref, RX VrefLevel [Byte0]: 36
2758 23:03:04.213689 [Byte1]: 36
2759 23:03:04.218262
2760 23:03:04.218348 Set Vref, RX VrefLevel [Byte0]: 37
2761 23:03:04.221796 [Byte1]: 37
2762 23:03:04.226624
2763 23:03:04.226706 Set Vref, RX VrefLevel [Byte0]: 38
2764 23:03:04.229656 [Byte1]: 38
2765 23:03:04.234213
2766 23:03:04.234294 Set Vref, RX VrefLevel [Byte0]: 39
2767 23:03:04.237527 [Byte1]: 39
2768 23:03:04.242575
2769 23:03:04.242658 Set Vref, RX VrefLevel [Byte0]: 40
2770 23:03:04.246183 [Byte1]: 40
2771 23:03:04.250281
2772 23:03:04.250389 Set Vref, RX VrefLevel [Byte0]: 41
2773 23:03:04.254079 [Byte1]: 41
2774 23:03:04.258408
2775 23:03:04.258489 Set Vref, RX VrefLevel [Byte0]: 42
2776 23:03:04.261968 [Byte1]: 42
2777 23:03:04.266448
2778 23:03:04.266580 Set Vref, RX VrefLevel [Byte0]: 43
2779 23:03:04.269921 [Byte1]: 43
2780 23:03:04.274451
2781 23:03:04.274532 Set Vref, RX VrefLevel [Byte0]: 44
2782 23:03:04.277682 [Byte1]: 44
2783 23:03:04.282927
2784 23:03:04.283008 Set Vref, RX VrefLevel [Byte0]: 45
2785 23:03:04.285650 [Byte1]: 45
2786 23:03:04.290605
2787 23:03:04.290686 Set Vref, RX VrefLevel [Byte0]: 46
2788 23:03:04.293516 [Byte1]: 46
2789 23:03:04.298234
2790 23:03:04.298314 Set Vref, RX VrefLevel [Byte0]: 47
2791 23:03:04.301607 [Byte1]: 47
2792 23:03:04.306266
2793 23:03:04.306346 Set Vref, RX VrefLevel [Byte0]: 48
2794 23:03:04.309899 [Byte1]: 48
2795 23:03:04.314271
2796 23:03:04.314351 Set Vref, RX VrefLevel [Byte0]: 49
2797 23:03:04.317577 [Byte1]: 49
2798 23:03:04.322509
2799 23:03:04.322598 Set Vref, RX VrefLevel [Byte0]: 50
2800 23:03:04.325921 [Byte1]: 50
2801 23:03:04.330452
2802 23:03:04.330536 Set Vref, RX VrefLevel [Byte0]: 51
2803 23:03:04.333532 [Byte1]: 51
2804 23:03:04.338301
2805 23:03:04.338381 Set Vref, RX VrefLevel [Byte0]: 52
2806 23:03:04.341744 [Byte1]: 52
2807 23:03:04.346274
2808 23:03:04.346359 Set Vref, RX VrefLevel [Byte0]: 53
2809 23:03:04.349692 [Byte1]: 53
2810 23:03:04.354515
2811 23:03:04.354603 Set Vref, RX VrefLevel [Byte0]: 54
2812 23:03:04.357741 [Byte1]: 54
2813 23:03:04.362116
2814 23:03:04.362197 Set Vref, RX VrefLevel [Byte0]: 55
2815 23:03:04.365437 [Byte1]: 55
2816 23:03:04.370647
2817 23:03:04.370733 Set Vref, RX VrefLevel [Byte0]: 56
2818 23:03:04.373914 [Byte1]: 56
2819 23:03:04.378369
2820 23:03:04.378454 Set Vref, RX VrefLevel [Byte0]: 57
2821 23:03:04.381766 [Byte1]: 57
2822 23:03:04.386497
2823 23:03:04.386584 Set Vref, RX VrefLevel [Byte0]: 58
2824 23:03:04.389740 [Byte1]: 58
2825 23:03:04.394543
2826 23:03:04.394628 Set Vref, RX VrefLevel [Byte0]: 59
2827 23:03:04.397525 [Byte1]: 59
2828 23:03:04.402395
2829 23:03:04.402481 Set Vref, RX VrefLevel [Byte0]: 60
2830 23:03:04.405786 [Byte1]: 60
2831 23:03:04.410503
2832 23:03:04.410588 Set Vref, RX VrefLevel [Byte0]: 61
2833 23:03:04.413801 [Byte1]: 61
2834 23:03:04.418127
2835 23:03:04.418212 Set Vref, RX VrefLevel [Byte0]: 62
2836 23:03:04.421767 [Byte1]: 62
2837 23:03:04.426337
2838 23:03:04.426422 Set Vref, RX VrefLevel [Byte0]: 63
2839 23:03:04.429327 [Byte1]: 63
2840 23:03:04.434425
2841 23:03:04.434510 Set Vref, RX VrefLevel [Byte0]: 64
2842 23:03:04.437563 [Byte1]: 64
2843 23:03:04.442661
2844 23:03:04.442768 Set Vref, RX VrefLevel [Byte0]: 65
2845 23:03:04.445960 [Byte1]: 65
2846 23:03:04.450353
2847 23:03:04.450443 Set Vref, RX VrefLevel [Byte0]: 66
2848 23:03:04.453853 [Byte1]: 66
2849 23:03:04.458426
2850 23:03:04.458510 Set Vref, RX VrefLevel [Byte0]: 67
2851 23:03:04.461518 [Byte1]: 67
2852 23:03:04.466232
2853 23:03:04.466331 Set Vref, RX VrefLevel [Byte0]: 68
2854 23:03:04.469537 [Byte1]: 68
2855 23:03:04.474218
2856 23:03:04.474303 Set Vref, RX VrefLevel [Byte0]: 69
2857 23:03:04.477702 [Byte1]: 69
2858 23:03:04.482423
2859 23:03:04.482508 Set Vref, RX VrefLevel [Byte0]: 70
2860 23:03:04.485508 [Byte1]: 70
2861 23:03:04.490395
2862 23:03:04.490482 Set Vref, RX VrefLevel [Byte0]: 71
2863 23:03:04.493868 [Byte1]: 71
2864 23:03:04.498233
2865 23:03:04.498316 Set Vref, RX VrefLevel [Byte0]: 72
2866 23:03:04.501940 [Byte1]: 72
2867 23:03:04.506199
2868 23:03:04.506281 Set Vref, RX VrefLevel [Byte0]: 73
2869 23:03:04.509444 [Byte1]: 73
2870 23:03:04.514403
2871 23:03:04.514485 Set Vref, RX VrefLevel [Byte0]: 74
2872 23:03:04.517945 [Byte1]: 74
2873 23:03:04.522382
2874 23:03:04.522464 Final RX Vref Byte 0 = 60 to rank0
2875 23:03:04.525836 Final RX Vref Byte 1 = 57 to rank0
2876 23:03:04.528964 Final RX Vref Byte 0 = 60 to rank1
2877 23:03:04.532451 Final RX Vref Byte 1 = 57 to rank1==
2878 23:03:04.535531 Dram Type= 6, Freq= 0, CH_0, rank 0
2879 23:03:04.542108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2880 23:03:04.542191 ==
2881 23:03:04.542256 DQS Delay:
2882 23:03:04.542316 DQS0 = 0, DQS1 = 0
2883 23:03:04.545696 DQM Delay:
2884 23:03:04.545780 DQM0 = 111, DQM1 = 102
2885 23:03:04.549322 DQ Delay:
2886 23:03:04.552493 DQ0 =112, DQ1 =110, DQ2 =110, DQ3 =108
2887 23:03:04.555525 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120
2888 23:03:04.559065 DQ8 =94, DQ9 =86, DQ10 =104, DQ11 =94
2889 23:03:04.562424 DQ12 =108, DQ13 =108, DQ14 =116, DQ15 =108
2890 23:03:04.562506
2891 23:03:04.562570
2892 23:03:04.569361 [DQSOSCAuto] RK0, (LSB)MR18= 0xff, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps
2893 23:03:04.572658 CH0 RK0: MR19=403, MR18=FF
2894 23:03:04.578997 CH0_RK0: MR19=0x403, MR18=0xFF, DQSOSC=410, MR23=63, INC=39, DEC=26
2895 23:03:04.579079
2896 23:03:04.582397 ----->DramcWriteLeveling(PI) begin...
2897 23:03:04.582481 ==
2898 23:03:04.585671 Dram Type= 6, Freq= 0, CH_0, rank 1
2899 23:03:04.588732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2900 23:03:04.588815 ==
2901 23:03:04.592185 Write leveling (Byte 0): 33 => 33
2902 23:03:04.595539 Write leveling (Byte 1): 30 => 30
2903 23:03:04.598755 DramcWriteLeveling(PI) end<-----
2904 23:03:04.598837
2905 23:03:04.598901 ==
2906 23:03:04.602286 Dram Type= 6, Freq= 0, CH_0, rank 1
2907 23:03:04.605418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2908 23:03:04.609083 ==
2909 23:03:04.609165 [Gating] SW mode calibration
2910 23:03:04.615426 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2911 23:03:04.622343 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2912 23:03:04.625316 0 15 0 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
2913 23:03:04.632090 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2914 23:03:04.635569 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2915 23:03:04.639019 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2916 23:03:04.645811 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2917 23:03:04.648857 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2918 23:03:04.651824 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2919 23:03:04.658752 0 15 28 | B1->B0 | 3434 2626 | 1 0 | (1 1) (1 0)
2920 23:03:04.662332 1 0 0 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
2921 23:03:04.664993 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2922 23:03:04.671712 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2923 23:03:04.674961 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2924 23:03:04.678285 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2925 23:03:04.685131 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2926 23:03:04.688586 1 0 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
2927 23:03:04.692121 1 0 28 | B1->B0 | 2525 4444 | 0 0 | (0 0) (0 0)
2928 23:03:04.698536 1 1 0 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
2929 23:03:04.701723 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2930 23:03:04.705021 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2931 23:03:04.708279 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2932 23:03:04.714973 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2933 23:03:04.718587 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2934 23:03:04.721957 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2935 23:03:04.728851 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2936 23:03:04.731776 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2937 23:03:04.735022 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2938 23:03:04.742143 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2939 23:03:04.745118 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2940 23:03:04.748360 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2941 23:03:04.755087 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2942 23:03:04.758275 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2943 23:03:04.761596 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2944 23:03:04.768140 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2945 23:03:04.771859 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2946 23:03:04.775247 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2947 23:03:04.782477 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2948 23:03:04.785428 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2949 23:03:04.788505 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2950 23:03:04.795184 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2951 23:03:04.798529 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2952 23:03:04.801849 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2953 23:03:04.804892 Total UI for P1: 0, mck2ui 16
2954 23:03:04.808129 best dqsien dly found for B0: ( 1, 3, 28)
2955 23:03:04.811759 Total UI for P1: 0, mck2ui 16
2956 23:03:04.815096 best dqsien dly found for B1: ( 1, 3, 28)
2957 23:03:04.818369 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2958 23:03:04.821469 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2959 23:03:04.821605
2960 23:03:04.825211 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2961 23:03:04.831505 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2962 23:03:04.831591 [Gating] SW calibration Done
2963 23:03:04.831657 ==
2964 23:03:04.834775 Dram Type= 6, Freq= 0, CH_0, rank 1
2965 23:03:04.841989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2966 23:03:04.842075 ==
2967 23:03:04.842140 RX Vref Scan: 0
2968 23:03:04.842200
2969 23:03:04.844845 RX Vref 0 -> 0, step: 1
2970 23:03:04.844928
2971 23:03:04.848516 RX Delay -40 -> 252, step: 8
2972 23:03:04.851597 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2973 23:03:04.854690 iDelay=200, Bit 1, Center 111 (32 ~ 191) 160
2974 23:03:04.858112 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2975 23:03:04.864602 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2976 23:03:04.868192 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2977 23:03:04.871516 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2978 23:03:04.875024 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2979 23:03:04.878227 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2980 23:03:04.881652 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2981 23:03:04.888007 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2982 23:03:04.891572 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2983 23:03:04.895123 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2984 23:03:04.898062 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2985 23:03:04.901801 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2986 23:03:04.908180 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2987 23:03:04.911573 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2988 23:03:04.911656 ==
2989 23:03:04.914942 Dram Type= 6, Freq= 0, CH_0, rank 1
2990 23:03:04.918380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2991 23:03:04.918463 ==
2992 23:03:04.921684 DQS Delay:
2993 23:03:04.921765 DQS0 = 0, DQS1 = 0
2994 23:03:04.921830 DQM Delay:
2995 23:03:04.924669 DQM0 = 112, DQM1 = 102
2996 23:03:04.924752 DQ Delay:
2997 23:03:04.928176 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
2998 23:03:04.931768 DQ4 =115, DQ5 =103, DQ6 =119, DQ7 =123
2999 23:03:04.934986 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
3000 23:03:04.938611 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =111
3001 23:03:04.941524
3002 23:03:04.941605
3003 23:03:04.941669 ==
3004 23:03:04.945203 Dram Type= 6, Freq= 0, CH_0, rank 1
3005 23:03:04.948023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3006 23:03:04.948107 ==
3007 23:03:04.948170
3008 23:03:04.948272
3009 23:03:04.951601 TX Vref Scan disable
3010 23:03:04.951682 == TX Byte 0 ==
3011 23:03:04.958249 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3012 23:03:04.961316 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3013 23:03:04.961398 == TX Byte 1 ==
3014 23:03:04.968094 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3015 23:03:04.971696 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3016 23:03:04.971779 ==
3017 23:03:04.974923 Dram Type= 6, Freq= 0, CH_0, rank 1
3018 23:03:04.978164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3019 23:03:04.978250 ==
3020 23:03:04.991337 TX Vref=22, minBit 1, minWin=26, winSum=428
3021 23:03:04.994295 TX Vref=24, minBit 1, minWin=26, winSum=431
3022 23:03:04.997306 TX Vref=26, minBit 11, minWin=26, winSum=435
3023 23:03:05.000745 TX Vref=28, minBit 10, minWin=26, winSum=438
3024 23:03:05.004133 TX Vref=30, minBit 8, minWin=26, winSum=436
3025 23:03:05.010830 TX Vref=32, minBit 8, minWin=26, winSum=440
3026 23:03:05.014468 [TxChooseVref] Worse bit 8, Min win 26, Win sum 440, Final Vref 32
3027 23:03:05.014551
3028 23:03:05.017531 Final TX Range 1 Vref 32
3029 23:03:05.017618
3030 23:03:05.017687 ==
3031 23:03:05.020927 Dram Type= 6, Freq= 0, CH_0, rank 1
3032 23:03:05.024081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3033 23:03:05.024189 ==
3034 23:03:05.024267
3035 23:03:05.027229
3036 23:03:05.027310 TX Vref Scan disable
3037 23:03:05.030976 == TX Byte 0 ==
3038 23:03:05.034059 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3039 23:03:05.037600 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3040 23:03:05.040654 == TX Byte 1 ==
3041 23:03:05.044040 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3042 23:03:05.047895 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3043 23:03:05.047977
3044 23:03:05.050697 [DATLAT]
3045 23:03:05.050779 Freq=1200, CH0 RK1
3046 23:03:05.050843
3047 23:03:05.054170 DATLAT Default: 0xd
3048 23:03:05.054251 0, 0xFFFF, sum = 0
3049 23:03:05.057426 1, 0xFFFF, sum = 0
3050 23:03:05.057508 2, 0xFFFF, sum = 0
3051 23:03:05.060531 3, 0xFFFF, sum = 0
3052 23:03:05.060613 4, 0xFFFF, sum = 0
3053 23:03:05.064015 5, 0xFFFF, sum = 0
3054 23:03:05.064100 6, 0xFFFF, sum = 0
3055 23:03:05.067184 7, 0xFFFF, sum = 0
3056 23:03:05.070692 8, 0xFFFF, sum = 0
3057 23:03:05.070775 9, 0xFFFF, sum = 0
3058 23:03:05.073985 10, 0xFFFF, sum = 0
3059 23:03:05.074067 11, 0xFFFF, sum = 0
3060 23:03:05.077205 12, 0x0, sum = 1
3061 23:03:05.077287 13, 0x0, sum = 2
3062 23:03:05.080457 14, 0x0, sum = 3
3063 23:03:05.080539 15, 0x0, sum = 4
3064 23:03:05.080604 best_step = 13
3065 23:03:05.080663
3066 23:03:05.084165 ==
3067 23:03:05.087626 Dram Type= 6, Freq= 0, CH_0, rank 1
3068 23:03:05.090760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3069 23:03:05.090842 ==
3070 23:03:05.090907 RX Vref Scan: 0
3071 23:03:05.090968
3072 23:03:05.094250 RX Vref 0 -> 0, step: 1
3073 23:03:05.094330
3074 23:03:05.097384 RX Delay -37 -> 252, step: 4
3075 23:03:05.101030 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3076 23:03:05.107207 iDelay=195, Bit 1, Center 110 (39 ~ 182) 144
3077 23:03:05.110324 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3078 23:03:05.113682 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3079 23:03:05.117213 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3080 23:03:05.120441 iDelay=195, Bit 5, Center 102 (35 ~ 170) 136
3081 23:03:05.127033 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3082 23:03:05.130337 iDelay=195, Bit 7, Center 118 (47 ~ 190) 144
3083 23:03:05.134269 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3084 23:03:05.137340 iDelay=195, Bit 9, Center 84 (15 ~ 154) 140
3085 23:03:05.140547 iDelay=195, Bit 10, Center 102 (35 ~ 170) 136
3086 23:03:05.144122 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3087 23:03:05.150820 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3088 23:03:05.154115 iDelay=195, Bit 13, Center 108 (39 ~ 178) 140
3089 23:03:05.157210 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3090 23:03:05.160751 iDelay=195, Bit 15, Center 110 (43 ~ 178) 136
3091 23:03:05.160833 ==
3092 23:03:05.163671 Dram Type= 6, Freq= 0, CH_0, rank 1
3093 23:03:05.170240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3094 23:03:05.170324 ==
3095 23:03:05.170390 DQS Delay:
3096 23:03:05.173643 DQS0 = 0, DQS1 = 0
3097 23:03:05.173726 DQM Delay:
3098 23:03:05.177276 DQM0 = 111, DQM1 = 101
3099 23:03:05.177358 DQ Delay:
3100 23:03:05.180475 DQ0 =108, DQ1 =110, DQ2 =110, DQ3 =108
3101 23:03:05.183666 DQ4 =112, DQ5 =102, DQ6 =120, DQ7 =118
3102 23:03:05.187206 DQ8 =90, DQ9 =84, DQ10 =102, DQ11 =94
3103 23:03:05.190461 DQ12 =110, DQ13 =108, DQ14 =116, DQ15 =110
3104 23:03:05.190544
3105 23:03:05.190608
3106 23:03:05.200882 [DQSOSCAuto] RK1, (LSB)MR18= 0x14fb, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 402 ps
3107 23:03:05.200967 CH0 RK1: MR19=403, MR18=14FB
3108 23:03:05.207041 CH0_RK1: MR19=0x403, MR18=0x14FB, DQSOSC=402, MR23=63, INC=40, DEC=27
3109 23:03:05.210555 [RxdqsGatingPostProcess] freq 1200
3110 23:03:05.217200 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3111 23:03:05.220920 best DQS0 dly(2T, 0.5T) = (0, 12)
3112 23:03:05.223651 best DQS1 dly(2T, 0.5T) = (0, 12)
3113 23:03:05.227656 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3114 23:03:05.227739 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3115 23:03:05.230403 best DQS0 dly(2T, 0.5T) = (0, 11)
3116 23:03:05.234052 best DQS1 dly(2T, 0.5T) = (0, 11)
3117 23:03:05.237140 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3118 23:03:05.240274 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3119 23:03:05.243818 Pre-setting of DQS Precalculation
3120 23:03:05.250348 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3121 23:03:05.250432 ==
3122 23:03:05.253998 Dram Type= 6, Freq= 0, CH_1, rank 0
3123 23:03:05.257012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3124 23:03:05.257095 ==
3125 23:03:05.263760 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3126 23:03:05.267188 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3127 23:03:05.276679 [CA 0] Center 37 (7~67) winsize 61
3128 23:03:05.279886 [CA 1] Center 37 (7~68) winsize 62
3129 23:03:05.283394 [CA 2] Center 34 (4~64) winsize 61
3130 23:03:05.286472 [CA 3] Center 33 (3~64) winsize 62
3131 23:03:05.290244 [CA 4] Center 34 (4~64) winsize 61
3132 23:03:05.293540 [CA 5] Center 33 (3~63) winsize 61
3133 23:03:05.293621
3134 23:03:05.296770 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3135 23:03:05.296852
3136 23:03:05.299908 [CATrainingPosCal] consider 1 rank data
3137 23:03:05.303552 u2DelayCellTimex100 = 270/100 ps
3138 23:03:05.306749 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3139 23:03:05.310406 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3140 23:03:05.316972 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3141 23:03:05.319966 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3142 23:03:05.323164 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3143 23:03:05.326615 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3144 23:03:05.326697
3145 23:03:05.329855 CA PerBit enable=1, Macro0, CA PI delay=33
3146 23:03:05.329938
3147 23:03:05.333143 [CBTSetCACLKResult] CA Dly = 33
3148 23:03:05.333226 CS Dly: 5 (0~36)
3149 23:03:05.336479 ==
3150 23:03:05.336562 Dram Type= 6, Freq= 0, CH_1, rank 1
3151 23:03:05.343131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3152 23:03:05.343215 ==
3153 23:03:05.346472 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3154 23:03:05.353111 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3155 23:03:05.362192 [CA 0] Center 37 (7~67) winsize 61
3156 23:03:05.365979 [CA 1] Center 37 (7~68) winsize 62
3157 23:03:05.368892 [CA 2] Center 34 (4~65) winsize 62
3158 23:03:05.372230 [CA 3] Center 33 (3~64) winsize 62
3159 23:03:05.375942 [CA 4] Center 34 (4~65) winsize 62
3160 23:03:05.379235 [CA 5] Center 33 (3~63) winsize 61
3161 23:03:05.379338
3162 23:03:05.382614 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3163 23:03:05.382713
3164 23:03:05.385694 [CATrainingPosCal] consider 2 rank data
3165 23:03:05.389376 u2DelayCellTimex100 = 270/100 ps
3166 23:03:05.392978 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3167 23:03:05.395702 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3168 23:03:05.402929 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3169 23:03:05.405629 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3170 23:03:05.408899 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3171 23:03:05.412463 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3172 23:03:05.412543
3173 23:03:05.415668 CA PerBit enable=1, Macro0, CA PI delay=33
3174 23:03:05.415770
3175 23:03:05.419462 [CBTSetCACLKResult] CA Dly = 33
3176 23:03:05.419544 CS Dly: 7 (0~40)
3177 23:03:05.419636
3178 23:03:05.422404 ----->DramcWriteLeveling(PI) begin...
3179 23:03:05.425587 ==
3180 23:03:05.425688 Dram Type= 6, Freq= 0, CH_1, rank 0
3181 23:03:05.432434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3182 23:03:05.432510 ==
3183 23:03:05.436118 Write leveling (Byte 0): 25 => 25
3184 23:03:05.439041 Write leveling (Byte 1): 28 => 28
3185 23:03:05.442620 DramcWriteLeveling(PI) end<-----
3186 23:03:05.442721
3187 23:03:05.442811 ==
3188 23:03:05.445509 Dram Type= 6, Freq= 0, CH_1, rank 0
3189 23:03:05.448933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3190 23:03:05.449037 ==
3191 23:03:05.452535 [Gating] SW mode calibration
3192 23:03:05.458793 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3193 23:03:05.462080 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3194 23:03:05.468929 0 15 0 | B1->B0 | 2f2f 2727 | 0 0 | (0 0) (0 0)
3195 23:03:05.472311 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3196 23:03:05.475619 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3197 23:03:05.482082 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3198 23:03:05.485631 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3199 23:03:05.488804 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3200 23:03:05.495326 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3201 23:03:05.499090 0 15 28 | B1->B0 | 2a2a 2d2d | 1 0 | (1 0) (0 0)
3202 23:03:05.502164 1 0 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3203 23:03:05.508802 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3204 23:03:05.512382 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3205 23:03:05.515737 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3206 23:03:05.522402 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3207 23:03:05.525627 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3208 23:03:05.529068 1 0 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3209 23:03:05.535502 1 0 28 | B1->B0 | 3e3e 3635 | 1 1 | (0 0) (0 0)
3210 23:03:05.538785 1 1 0 | B1->B0 | 4646 4343 | 0 0 | (0 0) (1 1)
3211 23:03:05.542058 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3212 23:03:05.548957 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3213 23:03:05.552409 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3214 23:03:05.555693 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3215 23:03:05.561995 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3216 23:03:05.565374 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3217 23:03:05.569248 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3218 23:03:05.571994 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3219 23:03:05.578599 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3220 23:03:05.581881 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3221 23:03:05.585489 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3222 23:03:05.592147 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3223 23:03:05.595475 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3224 23:03:05.598519 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3225 23:03:05.605275 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3226 23:03:05.608655 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3227 23:03:05.612225 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3228 23:03:05.618730 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3229 23:03:05.622010 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3230 23:03:05.625306 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3231 23:03:05.631850 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3232 23:03:05.635609 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3233 23:03:05.638757 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3234 23:03:05.645404 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3235 23:03:05.645490 Total UI for P1: 0, mck2ui 16
3236 23:03:05.652088 best dqsien dly found for B1: ( 1, 3, 30)
3237 23:03:05.655239 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3238 23:03:05.658363 Total UI for P1: 0, mck2ui 16
3239 23:03:05.661916 best dqsien dly found for B0: ( 1, 3, 30)
3240 23:03:05.665028 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3241 23:03:05.668630 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3242 23:03:05.668711
3243 23:03:05.671649 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3244 23:03:05.675091 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3245 23:03:05.678671 [Gating] SW calibration Done
3246 23:03:05.678753 ==
3247 23:03:05.681815 Dram Type= 6, Freq= 0, CH_1, rank 0
3248 23:03:05.685332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3249 23:03:05.685415 ==
3250 23:03:05.688452 RX Vref Scan: 0
3251 23:03:05.688533
3252 23:03:05.691739 RX Vref 0 -> 0, step: 1
3253 23:03:05.691820
3254 23:03:05.691885 RX Delay -40 -> 252, step: 8
3255 23:03:05.698360 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3256 23:03:05.701793 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3257 23:03:05.705379 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3258 23:03:05.708502 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3259 23:03:05.711919 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3260 23:03:05.718677 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3261 23:03:05.721723 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3262 23:03:05.725256 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3263 23:03:05.728769 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
3264 23:03:05.731812 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3265 23:03:05.738561 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3266 23:03:05.742091 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3267 23:03:05.745227 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3268 23:03:05.748662 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
3269 23:03:05.751730 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3270 23:03:05.758385 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3271 23:03:05.758468 ==
3272 23:03:05.761629 Dram Type= 6, Freq= 0, CH_1, rank 0
3273 23:03:05.765257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3274 23:03:05.765340 ==
3275 23:03:05.765406 DQS Delay:
3276 23:03:05.768515 DQS0 = 0, DQS1 = 0
3277 23:03:05.768597 DQM Delay:
3278 23:03:05.771860 DQM0 = 114, DQM1 = 104
3279 23:03:05.771941 DQ Delay:
3280 23:03:05.775634 DQ0 =115, DQ1 =111, DQ2 =103, DQ3 =115
3281 23:03:05.778460 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3282 23:03:05.781707 DQ8 =91, DQ9 =95, DQ10 =103, DQ11 =99
3283 23:03:05.785346 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =111
3284 23:03:05.785429
3285 23:03:05.785493
3286 23:03:05.785552 ==
3287 23:03:05.788303 Dram Type= 6, Freq= 0, CH_1, rank 0
3288 23:03:05.794849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3289 23:03:05.794933 ==
3290 23:03:05.794998
3291 23:03:05.795057
3292 23:03:05.795115 TX Vref Scan disable
3293 23:03:05.798846 == TX Byte 0 ==
3294 23:03:05.801913 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3295 23:03:05.808530 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3296 23:03:05.808612 == TX Byte 1 ==
3297 23:03:05.812144 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3298 23:03:05.819098 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3299 23:03:05.819183 ==
3300 23:03:05.822161 Dram Type= 6, Freq= 0, CH_1, rank 0
3301 23:03:05.825812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3302 23:03:05.825895 ==
3303 23:03:05.836513 TX Vref=22, minBit 10, minWin=24, winSum=408
3304 23:03:05.839817 TX Vref=24, minBit 10, minWin=24, winSum=410
3305 23:03:05.843270 TX Vref=26, minBit 10, minWin=24, winSum=417
3306 23:03:05.846613 TX Vref=28, minBit 9, minWin=25, winSum=423
3307 23:03:05.850152 TX Vref=30, minBit 9, minWin=25, winSum=425
3308 23:03:05.856710 TX Vref=32, minBit 9, minWin=24, winSum=418
3309 23:03:05.860229 [TxChooseVref] Worse bit 9, Min win 25, Win sum 425, Final Vref 30
3310 23:03:05.860325
3311 23:03:05.863366 Final TX Range 1 Vref 30
3312 23:03:05.863447
3313 23:03:05.863511 ==
3314 23:03:05.866854 Dram Type= 6, Freq= 0, CH_1, rank 0
3315 23:03:05.870240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3316 23:03:05.870323 ==
3317 23:03:05.870386
3318 23:03:05.874355
3319 23:03:05.874435 TX Vref Scan disable
3320 23:03:05.876721 == TX Byte 0 ==
3321 23:03:05.880325 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3322 23:03:05.883392 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3323 23:03:05.887202 == TX Byte 1 ==
3324 23:03:05.890203 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3325 23:03:05.893881 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3326 23:03:05.893972
3327 23:03:05.896842 [DATLAT]
3328 23:03:05.896966 Freq=1200, CH1 RK0
3329 23:03:05.897065
3330 23:03:05.900137 DATLAT Default: 0xd
3331 23:03:05.900291 0, 0xFFFF, sum = 0
3332 23:03:05.903200 1, 0xFFFF, sum = 0
3333 23:03:05.903284 2, 0xFFFF, sum = 0
3334 23:03:05.906934 3, 0xFFFF, sum = 0
3335 23:03:05.907047 4, 0xFFFF, sum = 0
3336 23:03:05.909922 5, 0xFFFF, sum = 0
3337 23:03:05.910035 6, 0xFFFF, sum = 0
3338 23:03:05.913172 7, 0xFFFF, sum = 0
3339 23:03:05.916691 8, 0xFFFF, sum = 0
3340 23:03:05.916842 9, 0xFFFF, sum = 0
3341 23:03:05.919861 10, 0xFFFF, sum = 0
3342 23:03:05.919976 11, 0xFFFF, sum = 0
3343 23:03:05.923620 12, 0x0, sum = 1
3344 23:03:05.923731 13, 0x0, sum = 2
3345 23:03:05.926367 14, 0x0, sum = 3
3346 23:03:05.926475 15, 0x0, sum = 4
3347 23:03:05.926572 best_step = 13
3348 23:03:05.926661
3349 23:03:05.929827 ==
3350 23:03:05.933521 Dram Type= 6, Freq= 0, CH_1, rank 0
3351 23:03:05.936957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3352 23:03:05.937071 ==
3353 23:03:05.937173 RX Vref Scan: 1
3354 23:03:05.937270
3355 23:03:05.940097 Set Vref Range= 32 -> 127
3356 23:03:05.940228
3357 23:03:05.943465 RX Vref 32 -> 127, step: 1
3358 23:03:05.943592
3359 23:03:05.946493 RX Delay -21 -> 252, step: 4
3360 23:03:05.946628
3361 23:03:05.950120 Set Vref, RX VrefLevel [Byte0]: 32
3362 23:03:05.953063 [Byte1]: 32
3363 23:03:05.953216
3364 23:03:05.956722 Set Vref, RX VrefLevel [Byte0]: 33
3365 23:03:05.960023 [Byte1]: 33
3366 23:03:05.960229
3367 23:03:05.963582 Set Vref, RX VrefLevel [Byte0]: 34
3368 23:03:05.966616 [Byte1]: 34
3369 23:03:05.970994
3370 23:03:05.971239 Set Vref, RX VrefLevel [Byte0]: 35
3371 23:03:05.974548 [Byte1]: 35
3372 23:03:05.979389
3373 23:03:05.979707 Set Vref, RX VrefLevel [Byte0]: 36
3374 23:03:05.982649 [Byte1]: 36
3375 23:03:05.987352
3376 23:03:05.987799 Set Vref, RX VrefLevel [Byte0]: 37
3377 23:03:05.990304 [Byte1]: 37
3378 23:03:05.995431
3379 23:03:05.995791 Set Vref, RX VrefLevel [Byte0]: 38
3380 23:03:05.998206 [Byte1]: 38
3381 23:03:06.003202
3382 23:03:06.003552 Set Vref, RX VrefLevel [Byte0]: 39
3383 23:03:06.006441 [Byte1]: 39
3384 23:03:06.010666
3385 23:03:06.011066 Set Vref, RX VrefLevel [Byte0]: 40
3386 23:03:06.013982 [Byte1]: 40
3387 23:03:06.018765
3388 23:03:06.019179 Set Vref, RX VrefLevel [Byte0]: 41
3389 23:03:06.022042 [Byte1]: 41
3390 23:03:06.026750
3391 23:03:06.027128 Set Vref, RX VrefLevel [Byte0]: 42
3392 23:03:06.029911 [Byte1]: 42
3393 23:03:06.035144
3394 23:03:06.035544 Set Vref, RX VrefLevel [Byte0]: 43
3395 23:03:06.038290 [Byte1]: 43
3396 23:03:06.042756
3397 23:03:06.043154 Set Vref, RX VrefLevel [Byte0]: 44
3398 23:03:06.046009 [Byte1]: 44
3399 23:03:06.050801
3400 23:03:06.051109 Set Vref, RX VrefLevel [Byte0]: 45
3401 23:03:06.053900 [Byte1]: 45
3402 23:03:06.058750
3403 23:03:06.059054 Set Vref, RX VrefLevel [Byte0]: 46
3404 23:03:06.061787 [Byte1]: 46
3405 23:03:06.066502
3406 23:03:06.066867 Set Vref, RX VrefLevel [Byte0]: 47
3407 23:03:06.069575 [Byte1]: 47
3408 23:03:06.074564
3409 23:03:06.074856 Set Vref, RX VrefLevel [Byte0]: 48
3410 23:03:06.077851 [Byte1]: 48
3411 23:03:06.082346
3412 23:03:06.082640 Set Vref, RX VrefLevel [Byte0]: 49
3413 23:03:06.085449 [Byte1]: 49
3414 23:03:06.090450
3415 23:03:06.090741 Set Vref, RX VrefLevel [Byte0]: 50
3416 23:03:06.093146 [Byte1]: 50
3417 23:03:06.098158
3418 23:03:06.098720 Set Vref, RX VrefLevel [Byte0]: 51
3419 23:03:06.104450 [Byte1]: 51
3420 23:03:06.104849
3421 23:03:06.107840 Set Vref, RX VrefLevel [Byte0]: 52
3422 23:03:06.111390 [Byte1]: 52
3423 23:03:06.111778
3424 23:03:06.114712 Set Vref, RX VrefLevel [Byte0]: 53
3425 23:03:06.118098 [Byte1]: 53
3426 23:03:06.122286
3427 23:03:06.122746 Set Vref, RX VrefLevel [Byte0]: 54
3428 23:03:06.124982 [Byte1]: 54
3429 23:03:06.129985
3430 23:03:06.130405 Set Vref, RX VrefLevel [Byte0]: 55
3431 23:03:06.132682 [Byte1]: 55
3432 23:03:06.137508
3433 23:03:06.137590 Set Vref, RX VrefLevel [Byte0]: 56
3434 23:03:06.141074 [Byte1]: 56
3435 23:03:06.145167
3436 23:03:06.145248 Set Vref, RX VrefLevel [Byte0]: 57
3437 23:03:06.148451 [Byte1]: 57
3438 23:03:06.153262
3439 23:03:06.153344 Set Vref, RX VrefLevel [Byte0]: 58
3440 23:03:06.156477 [Byte1]: 58
3441 23:03:06.161315
3442 23:03:06.161396 Set Vref, RX VrefLevel [Byte0]: 59
3443 23:03:06.164575 [Byte1]: 59
3444 23:03:06.169359
3445 23:03:06.169441 Set Vref, RX VrefLevel [Byte0]: 60
3446 23:03:06.172265 [Byte1]: 60
3447 23:03:06.176890
3448 23:03:06.176972 Set Vref, RX VrefLevel [Byte0]: 61
3449 23:03:06.180236 [Byte1]: 61
3450 23:03:06.184697
3451 23:03:06.184778 Set Vref, RX VrefLevel [Byte0]: 62
3452 23:03:06.188519 [Byte1]: 62
3453 23:03:06.192734
3454 23:03:06.192815 Set Vref, RX VrefLevel [Byte0]: 63
3455 23:03:06.196461 [Byte1]: 63
3456 23:03:06.200734
3457 23:03:06.200815 Set Vref, RX VrefLevel [Byte0]: 64
3458 23:03:06.204190 [Byte1]: 64
3459 23:03:06.209023
3460 23:03:06.209104 Set Vref, RX VrefLevel [Byte0]: 65
3461 23:03:06.212115 [Byte1]: 65
3462 23:03:06.216571
3463 23:03:06.216653 Set Vref, RX VrefLevel [Byte0]: 66
3464 23:03:06.219736 [Byte1]: 66
3465 23:03:06.224411
3466 23:03:06.224492 Set Vref, RX VrefLevel [Byte0]: 67
3467 23:03:06.227799 [Byte1]: 67
3468 23:03:06.232535
3469 23:03:06.232627 Set Vref, RX VrefLevel [Byte0]: 68
3470 23:03:06.235743 [Byte1]: 68
3471 23:03:06.240416
3472 23:03:06.240498 Set Vref, RX VrefLevel [Byte0]: 69
3473 23:03:06.243795 [Byte1]: 69
3474 23:03:06.248597
3475 23:03:06.248678 Final RX Vref Byte 0 = 56 to rank0
3476 23:03:06.252056 Final RX Vref Byte 1 = 56 to rank0
3477 23:03:06.255076 Final RX Vref Byte 0 = 56 to rank1
3478 23:03:06.258343 Final RX Vref Byte 1 = 56 to rank1==
3479 23:03:06.261553 Dram Type= 6, Freq= 0, CH_1, rank 0
3480 23:03:06.268441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3481 23:03:06.268523 ==
3482 23:03:06.268588 DQS Delay:
3483 23:03:06.268647 DQS0 = 0, DQS1 = 0
3484 23:03:06.271767 DQM Delay:
3485 23:03:06.271848 DQM0 = 114, DQM1 = 106
3486 23:03:06.274824 DQ Delay:
3487 23:03:06.278023 DQ0 =116, DQ1 =110, DQ2 =104, DQ3 =112
3488 23:03:06.281896 DQ4 =112, DQ5 =122, DQ6 =128, DQ7 =112
3489 23:03:06.284741 DQ8 =92, DQ9 =98, DQ10 =106, DQ11 =100
3490 23:03:06.287962 DQ12 =114, DQ13 =114, DQ14 =116, DQ15 =112
3491 23:03:06.288043
3492 23:03:06.288121
3493 23:03:06.294525 [DQSOSCAuto] RK0, (LSB)MR18= 0xf1f9, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 416 ps
3494 23:03:06.298061 CH1 RK0: MR19=303, MR18=F1F9
3495 23:03:06.304924 CH1_RK0: MR19=0x303, MR18=0xF1F9, DQSOSC=412, MR23=63, INC=38, DEC=25
3496 23:03:06.305028
3497 23:03:06.308086 ----->DramcWriteLeveling(PI) begin...
3498 23:03:06.308217 ==
3499 23:03:06.311547 Dram Type= 6, Freq= 0, CH_1, rank 1
3500 23:03:06.314807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3501 23:03:06.318206 ==
3502 23:03:06.318309 Write leveling (Byte 0): 24 => 24
3503 23:03:06.321438 Write leveling (Byte 1): 27 => 27
3504 23:03:06.324816 DramcWriteLeveling(PI) end<-----
3505 23:03:06.324919
3506 23:03:06.324985 ==
3507 23:03:06.328729 Dram Type= 6, Freq= 0, CH_1, rank 1
3508 23:03:06.335157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3509 23:03:06.335260 ==
3510 23:03:06.335353 [Gating] SW mode calibration
3511 23:03:06.345164 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3512 23:03:06.348443 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3513 23:03:06.351657 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3514 23:03:06.358385 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3515 23:03:06.361529 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3516 23:03:06.364698 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3517 23:03:06.371389 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3518 23:03:06.374800 0 15 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3519 23:03:06.378133 0 15 24 | B1->B0 | 3232 2424 | 0 0 | (0 1) (1 0)
3520 23:03:06.385022 0 15 28 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
3521 23:03:06.388198 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3522 23:03:06.391468 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3523 23:03:06.398132 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3524 23:03:06.401271 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3525 23:03:06.404810 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3526 23:03:06.411498 1 0 20 | B1->B0 | 2525 2d2d | 1 0 | (0 0) (0 0)
3527 23:03:06.414700 1 0 24 | B1->B0 | 2e2e 4646 | 0 0 | (0 0) (0 0)
3528 23:03:06.418279 1 0 28 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
3529 23:03:06.424585 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3530 23:03:06.427972 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3531 23:03:06.430992 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3532 23:03:06.437908 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3533 23:03:06.440923 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3534 23:03:06.444184 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3535 23:03:06.450919 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3536 23:03:06.454661 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3537 23:03:06.457790 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3538 23:03:06.464679 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3539 23:03:06.467569 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3540 23:03:06.471270 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3541 23:03:06.477602 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3542 23:03:06.480791 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3543 23:03:06.483976 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3544 23:03:06.490903 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3545 23:03:06.494272 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3546 23:03:06.497493 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3547 23:03:06.504040 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3548 23:03:06.507766 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3549 23:03:06.510747 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3550 23:03:06.513888 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3551 23:03:06.520721 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3552 23:03:06.523765 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3553 23:03:06.527394 Total UI for P1: 0, mck2ui 16
3554 23:03:06.530490 best dqsien dly found for B0: ( 1, 3, 22)
3555 23:03:06.533927 Total UI for P1: 0, mck2ui 16
3556 23:03:06.537050 best dqsien dly found for B1: ( 1, 3, 24)
3557 23:03:06.540735 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3558 23:03:06.543715 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3559 23:03:06.543814
3560 23:03:06.546765 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3561 23:03:06.553958 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3562 23:03:06.554061 [Gating] SW calibration Done
3563 23:03:06.554168 ==
3564 23:03:06.556848 Dram Type= 6, Freq= 0, CH_1, rank 1
3565 23:03:06.563555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3566 23:03:06.563653 ==
3567 23:03:06.563742 RX Vref Scan: 0
3568 23:03:06.563831
3569 23:03:06.566829 RX Vref 0 -> 0, step: 1
3570 23:03:06.566919
3571 23:03:06.570037 RX Delay -40 -> 252, step: 8
3572 23:03:06.573861 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3573 23:03:06.577193 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3574 23:03:06.580132 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3575 23:03:06.586758 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3576 23:03:06.590404 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3577 23:03:06.593547 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3578 23:03:06.596629 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3579 23:03:06.599853 iDelay=200, Bit 7, Center 107 (32 ~ 183) 152
3580 23:03:06.606460 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3581 23:03:06.610064 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3582 23:03:06.613168 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3583 23:03:06.616344 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3584 23:03:06.620086 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3585 23:03:06.626770 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3586 23:03:06.629518 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3587 23:03:06.633122 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
3588 23:03:06.633204 ==
3589 23:03:06.636222 Dram Type= 6, Freq= 0, CH_1, rank 1
3590 23:03:06.639730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3591 23:03:06.639813 ==
3592 23:03:06.642869 DQS Delay:
3593 23:03:06.642951 DQS0 = 0, DQS1 = 0
3594 23:03:06.646092 DQM Delay:
3595 23:03:06.646174 DQM0 = 110, DQM1 = 109
3596 23:03:06.649808 DQ Delay:
3597 23:03:06.653262 DQ0 =115, DQ1 =107, DQ2 =99, DQ3 =107
3598 23:03:06.656357 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =107
3599 23:03:06.659352 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3600 23:03:06.662778 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =115
3601 23:03:06.662860
3602 23:03:06.662925
3603 23:03:06.662985 ==
3604 23:03:06.666208 Dram Type= 6, Freq= 0, CH_1, rank 1
3605 23:03:06.669877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3606 23:03:06.669960 ==
3607 23:03:06.670025
3608 23:03:06.670084
3609 23:03:06.672726 TX Vref Scan disable
3610 23:03:06.676094 == TX Byte 0 ==
3611 23:03:06.679226 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3612 23:03:06.682456 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3613 23:03:06.685973 == TX Byte 1 ==
3614 23:03:06.689096 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3615 23:03:06.692336 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3616 23:03:06.692418 ==
3617 23:03:06.695740 Dram Type= 6, Freq= 0, CH_1, rank 1
3618 23:03:06.702581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3619 23:03:06.702663 ==
3620 23:03:06.712856 TX Vref=22, minBit 9, minWin=25, winSum=419
3621 23:03:06.716042 TX Vref=24, minBit 1, minWin=26, winSum=426
3622 23:03:06.719795 TX Vref=26, minBit 9, minWin=25, winSum=428
3623 23:03:06.722705 TX Vref=28, minBit 7, minWin=26, winSum=430
3624 23:03:06.726019 TX Vref=30, minBit 9, minWin=26, winSum=434
3625 23:03:06.729315 TX Vref=32, minBit 1, minWin=25, winSum=425
3626 23:03:06.736363 [TxChooseVref] Worse bit 9, Min win 26, Win sum 434, Final Vref 30
3627 23:03:06.736445
3628 23:03:06.739484 Final TX Range 1 Vref 30
3629 23:03:06.739567
3630 23:03:06.739631 ==
3631 23:03:06.742433 Dram Type= 6, Freq= 0, CH_1, rank 1
3632 23:03:06.746324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3633 23:03:06.746407 ==
3634 23:03:06.749482
3635 23:03:06.749579
3636 23:03:06.749646 TX Vref Scan disable
3637 23:03:06.752782 == TX Byte 0 ==
3638 23:03:06.755717 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3639 23:03:06.759328 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3640 23:03:06.762419 == TX Byte 1 ==
3641 23:03:06.765859 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3642 23:03:06.769004 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3643 23:03:06.772633
3644 23:03:06.772747 [DATLAT]
3645 23:03:06.772815 Freq=1200, CH1 RK1
3646 23:03:06.772876
3647 23:03:06.775644 DATLAT Default: 0xd
3648 23:03:06.775726 0, 0xFFFF, sum = 0
3649 23:03:06.779404 1, 0xFFFF, sum = 0
3650 23:03:06.779487 2, 0xFFFF, sum = 0
3651 23:03:06.782721 3, 0xFFFF, sum = 0
3652 23:03:06.785636 4, 0xFFFF, sum = 0
3653 23:03:06.785719 5, 0xFFFF, sum = 0
3654 23:03:06.788890 6, 0xFFFF, sum = 0
3655 23:03:06.788973 7, 0xFFFF, sum = 0
3656 23:03:06.792408 8, 0xFFFF, sum = 0
3657 23:03:06.792491 9, 0xFFFF, sum = 0
3658 23:03:06.796157 10, 0xFFFF, sum = 0
3659 23:03:06.796285 11, 0xFFFF, sum = 0
3660 23:03:06.799165 12, 0x0, sum = 1
3661 23:03:06.799283 13, 0x0, sum = 2
3662 23:03:06.802044 14, 0x0, sum = 3
3663 23:03:06.802147 15, 0x0, sum = 4
3664 23:03:06.805817 best_step = 13
3665 23:03:06.805928
3666 23:03:06.806021 ==
3667 23:03:06.808907 Dram Type= 6, Freq= 0, CH_1, rank 1
3668 23:03:06.812464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3669 23:03:06.812574 ==
3670 23:03:06.812666 RX Vref Scan: 0
3671 23:03:06.812756
3672 23:03:06.815736 RX Vref 0 -> 0, step: 1
3673 23:03:06.815839
3674 23:03:06.819056 RX Delay -21 -> 252, step: 4
3675 23:03:06.822002 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3676 23:03:06.829091 iDelay=195, Bit 1, Center 110 (43 ~ 178) 136
3677 23:03:06.832134 iDelay=195, Bit 2, Center 102 (35 ~ 170) 136
3678 23:03:06.835428 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3679 23:03:06.838691 iDelay=195, Bit 4, Center 110 (39 ~ 182) 144
3680 23:03:06.842133 iDelay=195, Bit 5, Center 120 (47 ~ 194) 148
3681 23:03:06.849152 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3682 23:03:06.852083 iDelay=195, Bit 7, Center 108 (39 ~ 178) 140
3683 23:03:06.855514 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3684 23:03:06.858298 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3685 23:03:06.862229 iDelay=195, Bit 10, Center 114 (47 ~ 182) 136
3686 23:03:06.868262 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3687 23:03:06.871794 iDelay=195, Bit 12, Center 120 (55 ~ 186) 132
3688 23:03:06.874906 iDelay=195, Bit 13, Center 116 (51 ~ 182) 132
3689 23:03:06.878465 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3690 23:03:06.884935 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3691 23:03:06.885011 ==
3692 23:03:06.888137 Dram Type= 6, Freq= 0, CH_1, rank 1
3693 23:03:06.891732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3694 23:03:06.891834 ==
3695 23:03:06.891928 DQS Delay:
3696 23:03:06.895218 DQS0 = 0, DQS1 = 0
3697 23:03:06.895316 DQM Delay:
3698 23:03:06.898593 DQM0 = 111, DQM1 = 111
3699 23:03:06.898695 DQ Delay:
3700 23:03:06.901875 DQ0 =114, DQ1 =110, DQ2 =102, DQ3 =108
3701 23:03:06.904680 DQ4 =110, DQ5 =120, DQ6 =122, DQ7 =108
3702 23:03:06.907969 DQ8 =96, DQ9 =102, DQ10 =114, DQ11 =104
3703 23:03:06.911750 DQ12 =120, DQ13 =116, DQ14 =118, DQ15 =118
3704 23:03:06.911848
3705 23:03:06.911941
3706 23:03:06.921370 [DQSOSCAuto] RK1, (LSB)MR18= 0xf807, (MSB)MR19= 0x304, tDQSOscB0 = 407 ps tDQSOscB1 = 413 ps
3707 23:03:06.924586 CH1 RK1: MR19=304, MR18=F807
3708 23:03:06.931388 CH1_RK1: MR19=0x304, MR18=0xF807, DQSOSC=407, MR23=63, INC=39, DEC=26
3709 23:03:06.934438 [RxdqsGatingPostProcess] freq 1200
3710 23:03:06.937727 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3711 23:03:06.941013 best DQS0 dly(2T, 0.5T) = (0, 11)
3712 23:03:06.944299 best DQS1 dly(2T, 0.5T) = (0, 11)
3713 23:03:06.947420 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3714 23:03:06.950953 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3715 23:03:06.954691 best DQS0 dly(2T, 0.5T) = (0, 11)
3716 23:03:06.957814 best DQS1 dly(2T, 0.5T) = (0, 11)
3717 23:03:06.961016 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3718 23:03:06.964319 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3719 23:03:06.967512 Pre-setting of DQS Precalculation
3720 23:03:06.971113 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3721 23:03:06.977638 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3722 23:03:06.987774 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3723 23:03:06.987878
3724 23:03:06.987972
3725 23:03:06.990744 [Calibration Summary] 2400 Mbps
3726 23:03:06.990845 CH 0, Rank 0
3727 23:03:06.993996 SW Impedance : PASS
3728 23:03:06.994096 DUTY Scan : NO K
3729 23:03:06.997788 ZQ Calibration : PASS
3730 23:03:06.997888 Jitter Meter : NO K
3731 23:03:07.000937 CBT Training : PASS
3732 23:03:07.004239 Write leveling : PASS
3733 23:03:07.004337 RX DQS gating : PASS
3734 23:03:07.007177 RX DQ/DQS(RDDQC) : PASS
3735 23:03:07.011000 TX DQ/DQS : PASS
3736 23:03:07.011106 RX DATLAT : PASS
3737 23:03:07.013869 RX DQ/DQS(Engine): PASS
3738 23:03:07.017359 TX OE : NO K
3739 23:03:07.017465 All Pass.
3740 23:03:07.017560
3741 23:03:07.017648 CH 0, Rank 1
3742 23:03:07.020701 SW Impedance : PASS
3743 23:03:07.024102 DUTY Scan : NO K
3744 23:03:07.024210 ZQ Calibration : PASS
3745 23:03:07.027080 Jitter Meter : NO K
3746 23:03:07.030658 CBT Training : PASS
3747 23:03:07.030762 Write leveling : PASS
3748 23:03:07.033679 RX DQS gating : PASS
3749 23:03:07.036949 RX DQ/DQS(RDDQC) : PASS
3750 23:03:07.037049 TX DQ/DQS : PASS
3751 23:03:07.040485 RX DATLAT : PASS
3752 23:03:07.043870 RX DQ/DQS(Engine): PASS
3753 23:03:07.043971 TX OE : NO K
3754 23:03:07.047121 All Pass.
3755 23:03:07.047221
3756 23:03:07.047311 CH 1, Rank 0
3757 23:03:07.050460 SW Impedance : PASS
3758 23:03:07.050560 DUTY Scan : NO K
3759 23:03:07.054005 ZQ Calibration : PASS
3760 23:03:07.056871 Jitter Meter : NO K
3761 23:03:07.056971 CBT Training : PASS
3762 23:03:07.060499 Write leveling : PASS
3763 23:03:07.063901 RX DQS gating : PASS
3764 23:03:07.063998 RX DQ/DQS(RDDQC) : PASS
3765 23:03:07.067105 TX DQ/DQS : PASS
3766 23:03:07.067203 RX DATLAT : PASS
3767 23:03:07.070419 RX DQ/DQS(Engine): PASS
3768 23:03:07.073649 TX OE : NO K
3769 23:03:07.073750 All Pass.
3770 23:03:07.073841
3771 23:03:07.073928 CH 1, Rank 1
3772 23:03:07.077074 SW Impedance : PASS
3773 23:03:07.080291 DUTY Scan : NO K
3774 23:03:07.080363 ZQ Calibration : PASS
3775 23:03:07.083553 Jitter Meter : NO K
3776 23:03:07.086683 CBT Training : PASS
3777 23:03:07.086783 Write leveling : PASS
3778 23:03:07.089941 RX DQS gating : PASS
3779 23:03:07.093123 RX DQ/DQS(RDDQC) : PASS
3780 23:03:07.093224 TX DQ/DQS : PASS
3781 23:03:07.096702 RX DATLAT : PASS
3782 23:03:07.099835 RX DQ/DQS(Engine): PASS
3783 23:03:07.099938 TX OE : NO K
3784 23:03:07.103029 All Pass.
3785 23:03:07.103129
3786 23:03:07.103218 DramC Write-DBI off
3787 23:03:07.106865 PER_BANK_REFRESH: Hybrid Mode
3788 23:03:07.106969 TX_TRACKING: ON
3789 23:03:07.116819 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3790 23:03:07.120131 [FAST_K] Save calibration result to emmc
3791 23:03:07.122840 dramc_set_vcore_voltage set vcore to 650000
3792 23:03:07.126585 Read voltage for 600, 5
3793 23:03:07.126687 Vio18 = 0
3794 23:03:07.129639 Vcore = 650000
3795 23:03:07.129739 Vdram = 0
3796 23:03:07.129827 Vddq = 0
3797 23:03:07.132818 Vmddr = 0
3798 23:03:07.136171 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3799 23:03:07.142545 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3800 23:03:07.142647 MEM_TYPE=3, freq_sel=19
3801 23:03:07.146118 sv_algorithm_assistance_LP4_1600
3802 23:03:07.152523 ============ PULL DRAM RESETB DOWN ============
3803 23:03:07.155908 ========== PULL DRAM RESETB DOWN end =========
3804 23:03:07.159209 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3805 23:03:07.162594 ===================================
3806 23:03:07.165699 LPDDR4 DRAM CONFIGURATION
3807 23:03:07.169093 ===================================
3808 23:03:07.172372 EX_ROW_EN[0] = 0x0
3809 23:03:07.172454 EX_ROW_EN[1] = 0x0
3810 23:03:07.175853 LP4Y_EN = 0x0
3811 23:03:07.175934 WORK_FSP = 0x0
3812 23:03:07.179150 WL = 0x2
3813 23:03:07.179247 RL = 0x2
3814 23:03:07.182739 BL = 0x2
3815 23:03:07.182820 RPST = 0x0
3816 23:03:07.185974 RD_PRE = 0x0
3817 23:03:07.186056 WR_PRE = 0x1
3818 23:03:07.189250 WR_PST = 0x0
3819 23:03:07.189332 DBI_WR = 0x0
3820 23:03:07.192575 DBI_RD = 0x0
3821 23:03:07.192656 OTF = 0x1
3822 23:03:07.195931 ===================================
3823 23:03:07.199013 ===================================
3824 23:03:07.202777 ANA top config
3825 23:03:07.205931 ===================================
3826 23:03:07.209014 DLL_ASYNC_EN = 0
3827 23:03:07.209096 ALL_SLAVE_EN = 1
3828 23:03:07.212493 NEW_RANK_MODE = 1
3829 23:03:07.215725 DLL_IDLE_MODE = 1
3830 23:03:07.219152 LP45_APHY_COMB_EN = 1
3831 23:03:07.219234 TX_ODT_DIS = 1
3832 23:03:07.222274 NEW_8X_MODE = 1
3833 23:03:07.225639 ===================================
3834 23:03:07.229100 ===================================
3835 23:03:07.232419 data_rate = 1200
3836 23:03:07.235527 CKR = 1
3837 23:03:07.239000 DQ_P2S_RATIO = 8
3838 23:03:07.241995 ===================================
3839 23:03:07.245442 CA_P2S_RATIO = 8
3840 23:03:07.245524 DQ_CA_OPEN = 0
3841 23:03:07.248617 DQ_SEMI_OPEN = 0
3842 23:03:07.251918 CA_SEMI_OPEN = 0
3843 23:03:07.255442 CA_FULL_RATE = 0
3844 23:03:07.258871 DQ_CKDIV4_EN = 1
3845 23:03:07.262079 CA_CKDIV4_EN = 1
3846 23:03:07.262161 CA_PREDIV_EN = 0
3847 23:03:07.265328 PH8_DLY = 0
3848 23:03:07.268546 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3849 23:03:07.271956 DQ_AAMCK_DIV = 4
3850 23:03:07.275093 CA_AAMCK_DIV = 4
3851 23:03:07.278707 CA_ADMCK_DIV = 4
3852 23:03:07.278789 DQ_TRACK_CA_EN = 0
3853 23:03:07.282118 CA_PICK = 600
3854 23:03:07.285192 CA_MCKIO = 600
3855 23:03:07.288523 MCKIO_SEMI = 0
3856 23:03:07.291541 PLL_FREQ = 2288
3857 23:03:07.295296 DQ_UI_PI_RATIO = 32
3858 23:03:07.298676 CA_UI_PI_RATIO = 0
3859 23:03:07.301813 ===================================
3860 23:03:07.304869 ===================================
3861 23:03:07.304951 memory_type:LPDDR4
3862 23:03:07.308534 GP_NUM : 10
3863 23:03:07.312006 SRAM_EN : 1
3864 23:03:07.312088 MD32_EN : 0
3865 23:03:07.314708 ===================================
3866 23:03:07.317960 [ANA_INIT] >>>>>>>>>>>>>>
3867 23:03:07.321362 <<<<<< [CONFIGURE PHASE]: ANA_TX
3868 23:03:07.324831 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3869 23:03:07.328066 ===================================
3870 23:03:07.331549 data_rate = 1200,PCW = 0X5800
3871 23:03:07.334750 ===================================
3872 23:03:07.338065 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3873 23:03:07.341229 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3874 23:03:07.347649 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3875 23:03:07.351311 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3876 23:03:07.357724 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3877 23:03:07.360935 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3878 23:03:07.361017 [ANA_INIT] flow start
3879 23:03:07.364361 [ANA_INIT] PLL >>>>>>>>
3880 23:03:07.367707 [ANA_INIT] PLL <<<<<<<<
3881 23:03:07.367789 [ANA_INIT] MIDPI >>>>>>>>
3882 23:03:07.371004 [ANA_INIT] MIDPI <<<<<<<<
3883 23:03:07.374045 [ANA_INIT] DLL >>>>>>>>
3884 23:03:07.374127 [ANA_INIT] flow end
3885 23:03:07.377486 ============ LP4 DIFF to SE enter ============
3886 23:03:07.384473 ============ LP4 DIFF to SE exit ============
3887 23:03:07.384557 [ANA_INIT] <<<<<<<<<<<<<
3888 23:03:07.387596 [Flow] Enable top DCM control >>>>>
3889 23:03:07.390497 [Flow] Enable top DCM control <<<<<
3890 23:03:07.394459 Enable DLL master slave shuffle
3891 23:03:07.400864 ==============================================================
3892 23:03:07.404119 Gating Mode config
3893 23:03:07.407199 ==============================================================
3894 23:03:07.410881 Config description:
3895 23:03:07.420725 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3896 23:03:07.427348 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3897 23:03:07.430553 SELPH_MODE 0: By rank 1: By Phase
3898 23:03:07.437184 ==============================================================
3899 23:03:07.440977 GAT_TRACK_EN = 1
3900 23:03:07.443990 RX_GATING_MODE = 2
3901 23:03:07.447064 RX_GATING_TRACK_MODE = 2
3902 23:03:07.447146 SELPH_MODE = 1
3903 23:03:07.450404 PICG_EARLY_EN = 1
3904 23:03:07.453540 VALID_LAT_VALUE = 1
3905 23:03:07.460482 ==============================================================
3906 23:03:07.463763 Enter into Gating configuration >>>>
3907 23:03:07.467320 Exit from Gating configuration <<<<
3908 23:03:07.470540 Enter into DVFS_PRE_config >>>>>
3909 23:03:07.480279 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3910 23:03:07.483617 Exit from DVFS_PRE_config <<<<<
3911 23:03:07.486952 Enter into PICG configuration >>>>
3912 23:03:07.490149 Exit from PICG configuration <<<<
3913 23:03:07.493673 [RX_INPUT] configuration >>>>>
3914 23:03:07.497061 [RX_INPUT] configuration <<<<<
3915 23:03:07.500250 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3916 23:03:07.506725 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3917 23:03:07.513458 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3918 23:03:07.520385 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3919 23:03:07.523443 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3920 23:03:07.530164 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3921 23:03:07.533833 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3922 23:03:07.540184 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3923 23:03:07.543253 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3924 23:03:07.546552 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3925 23:03:07.550035 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3926 23:03:07.556525 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3927 23:03:07.560143 ===================================
3928 23:03:07.563270 LPDDR4 DRAM CONFIGURATION
3929 23:03:07.566666 ===================================
3930 23:03:07.566751 EX_ROW_EN[0] = 0x0
3931 23:03:07.570034 EX_ROW_EN[1] = 0x0
3932 23:03:07.570118 LP4Y_EN = 0x0
3933 23:03:07.573137 WORK_FSP = 0x0
3934 23:03:07.573222 WL = 0x2
3935 23:03:07.576691 RL = 0x2
3936 23:03:07.576776 BL = 0x2
3937 23:03:07.579589 RPST = 0x0
3938 23:03:07.579698 RD_PRE = 0x0
3939 23:03:07.583015 WR_PRE = 0x1
3940 23:03:07.583151 WR_PST = 0x0
3941 23:03:07.586743 DBI_WR = 0x0
3942 23:03:07.586828 DBI_RD = 0x0
3943 23:03:07.589663 OTF = 0x1
3944 23:03:07.593350 ===================================
3945 23:03:07.596634 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3946 23:03:07.599529 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3947 23:03:07.606243 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3948 23:03:07.609640 ===================================
3949 23:03:07.609725 LPDDR4 DRAM CONFIGURATION
3950 23:03:07.612822 ===================================
3951 23:03:07.616359 EX_ROW_EN[0] = 0x10
3952 23:03:07.619847 EX_ROW_EN[1] = 0x0
3953 23:03:07.619931 LP4Y_EN = 0x0
3954 23:03:07.623198 WORK_FSP = 0x0
3955 23:03:07.623282 WL = 0x2
3956 23:03:07.626393 RL = 0x2
3957 23:03:07.626477 BL = 0x2
3958 23:03:07.629500 RPST = 0x0
3959 23:03:07.629585 RD_PRE = 0x0
3960 23:03:07.632892 WR_PRE = 0x1
3961 23:03:07.632977 WR_PST = 0x0
3962 23:03:07.636132 DBI_WR = 0x0
3963 23:03:07.636253 DBI_RD = 0x0
3964 23:03:07.639798 OTF = 0x1
3965 23:03:07.642982 ===================================
3966 23:03:07.649377 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3967 23:03:07.652760 nWR fixed to 30
3968 23:03:07.656158 [ModeRegInit_LP4] CH0 RK0
3969 23:03:07.656266 [ModeRegInit_LP4] CH0 RK1
3970 23:03:07.659429 [ModeRegInit_LP4] CH1 RK0
3971 23:03:07.662697 [ModeRegInit_LP4] CH1 RK1
3972 23:03:07.662781 match AC timing 17
3973 23:03:07.669443 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3974 23:03:07.672632 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3975 23:03:07.676072 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3976 23:03:07.682431 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3977 23:03:07.685674 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3978 23:03:07.685759 ==
3979 23:03:07.688969 Dram Type= 6, Freq= 0, CH_0, rank 0
3980 23:03:07.692239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3981 23:03:07.692336 ==
3982 23:03:07.699083 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3983 23:03:07.705732 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3984 23:03:07.709099 [CA 0] Center 37 (7~67) winsize 61
3985 23:03:07.712080 [CA 1] Center 37 (7~67) winsize 61
3986 23:03:07.715917 [CA 2] Center 35 (5~65) winsize 61
3987 23:03:07.718457 [CA 3] Center 35 (5~65) winsize 61
3988 23:03:07.722204 [CA 4] Center 34 (4~65) winsize 62
3989 23:03:07.725502 [CA 5] Center 34 (4~64) winsize 61
3990 23:03:07.725601
3991 23:03:07.728682 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3992 23:03:07.728763
3993 23:03:07.731943 [CATrainingPosCal] consider 1 rank data
3994 23:03:07.735116 u2DelayCellTimex100 = 270/100 ps
3995 23:03:07.739158 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3996 23:03:07.741756 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
3997 23:03:07.745042 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3998 23:03:07.748704 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3999 23:03:07.752046 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4000 23:03:07.758367 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4001 23:03:07.758449
4002 23:03:07.761916 CA PerBit enable=1, Macro0, CA PI delay=34
4003 23:03:07.761998
4004 23:03:07.765118 [CBTSetCACLKResult] CA Dly = 34
4005 23:03:07.765200 CS Dly: 5 (0~36)
4006 23:03:07.765264 ==
4007 23:03:07.768356 Dram Type= 6, Freq= 0, CH_0, rank 1
4008 23:03:07.771552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4009 23:03:07.775038 ==
4010 23:03:07.778551 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4011 23:03:07.784893 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4012 23:03:07.788509 [CA 0] Center 37 (7~67) winsize 61
4013 23:03:07.791778 [CA 1] Center 37 (7~67) winsize 61
4014 23:03:07.795031 [CA 2] Center 35 (5~65) winsize 61
4015 23:03:07.798616 [CA 3] Center 35 (5~65) winsize 61
4016 23:03:07.801778 [CA 4] Center 34 (4~65) winsize 62
4017 23:03:07.804858 [CA 5] Center 33 (3~64) winsize 62
4018 23:03:07.804940
4019 23:03:07.808491 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4020 23:03:07.808573
4021 23:03:07.811291 [CATrainingPosCal] consider 2 rank data
4022 23:03:07.814964 u2DelayCellTimex100 = 270/100 ps
4023 23:03:07.818250 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
4024 23:03:07.821684 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
4025 23:03:07.824948 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4026 23:03:07.831456 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
4027 23:03:07.834815 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4028 23:03:07.838053 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4029 23:03:07.838135
4030 23:03:07.841289 CA PerBit enable=1, Macro0, CA PI delay=34
4031 23:03:07.841371
4032 23:03:07.844702 [CBTSetCACLKResult] CA Dly = 34
4033 23:03:07.844784 CS Dly: 5 (0~37)
4034 23:03:07.844849
4035 23:03:07.848026 ----->DramcWriteLeveling(PI) begin...
4036 23:03:07.848109 ==
4037 23:03:07.851321 Dram Type= 6, Freq= 0, CH_0, rank 0
4038 23:03:07.857752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4039 23:03:07.857835 ==
4040 23:03:07.861158 Write leveling (Byte 0): 35 => 35
4041 23:03:07.864706 Write leveling (Byte 1): 31 => 31
4042 23:03:07.867692 DramcWriteLeveling(PI) end<-----
4043 23:03:07.867774
4044 23:03:07.867838 ==
4045 23:03:07.871057 Dram Type= 6, Freq= 0, CH_0, rank 0
4046 23:03:07.874709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4047 23:03:07.874791 ==
4048 23:03:07.877911 [Gating] SW mode calibration
4049 23:03:07.884443 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4050 23:03:07.887938 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4051 23:03:07.894255 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4052 23:03:07.898021 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4053 23:03:07.901535 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4054 23:03:07.907547 0 9 12 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
4055 23:03:07.911271 0 9 16 | B1->B0 | 3333 2c2c | 0 0 | (0 1) (1 1)
4056 23:03:07.914362 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4057 23:03:07.921013 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4058 23:03:07.924227 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4059 23:03:07.927462 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4060 23:03:07.934433 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4061 23:03:07.937363 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4062 23:03:07.940670 0 10 12 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
4063 23:03:07.947190 0 10 16 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
4064 23:03:07.951092 0 10 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4065 23:03:07.954393 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4066 23:03:07.960701 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4067 23:03:07.964268 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4068 23:03:07.967640 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4069 23:03:07.974396 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4070 23:03:07.977095 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4071 23:03:07.980162 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4072 23:03:07.986981 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 23:03:07.990285 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 23:03:07.993357 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4075 23:03:08.000400 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4076 23:03:08.003447 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4077 23:03:08.006555 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4078 23:03:08.013283 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4079 23:03:08.016639 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4080 23:03:08.019845 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4081 23:03:08.026916 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4082 23:03:08.030142 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4083 23:03:08.033374 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4084 23:03:08.040354 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4085 23:03:08.043177 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4086 23:03:08.046980 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4087 23:03:08.053298 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4088 23:03:08.053409 Total UI for P1: 0, mck2ui 16
4089 23:03:08.059815 best dqsien dly found for B0: ( 0, 13, 12)
4090 23:03:08.059962 Total UI for P1: 0, mck2ui 16
4091 23:03:08.063521 best dqsien dly found for B1: ( 0, 13, 14)
4092 23:03:08.069807 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4093 23:03:08.073567 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4094 23:03:08.073668
4095 23:03:08.076726 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4096 23:03:08.079972 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4097 23:03:08.082976 [Gating] SW calibration Done
4098 23:03:08.083072 ==
4099 23:03:08.086346 Dram Type= 6, Freq= 0, CH_0, rank 0
4100 23:03:08.089898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4101 23:03:08.089999 ==
4102 23:03:08.093454 RX Vref Scan: 0
4103 23:03:08.093554
4104 23:03:08.093643 RX Vref 0 -> 0, step: 1
4105 23:03:08.093730
4106 23:03:08.096478 RX Delay -230 -> 252, step: 16
4107 23:03:08.099686 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4108 23:03:08.106462 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4109 23:03:08.109771 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4110 23:03:08.113490 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4111 23:03:08.116337 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4112 23:03:08.122854 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4113 23:03:08.126209 iDelay=218, Bit 6, Center 41 (-134 ~ 217) 352
4114 23:03:08.130057 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4115 23:03:08.133286 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4116 23:03:08.136427 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4117 23:03:08.142889 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4118 23:03:08.146177 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4119 23:03:08.149569 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4120 23:03:08.153320 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4121 23:03:08.159651 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4122 23:03:08.163027 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4123 23:03:08.163124 ==
4124 23:03:08.166330 Dram Type= 6, Freq= 0, CH_0, rank 0
4125 23:03:08.169518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4126 23:03:08.169618 ==
4127 23:03:08.173268 DQS Delay:
4128 23:03:08.173369 DQS0 = 0, DQS1 = 0
4129 23:03:08.173458 DQM Delay:
4130 23:03:08.176416 DQM0 = 35, DQM1 = 31
4131 23:03:08.176488 DQ Delay:
4132 23:03:08.179601 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4133 23:03:08.182539 DQ4 =33, DQ5 =25, DQ6 =41, DQ7 =49
4134 23:03:08.186009 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =33
4135 23:03:08.189275 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4136 23:03:08.189375
4137 23:03:08.189464
4138 23:03:08.189550 ==
4139 23:03:08.192766 Dram Type= 6, Freq= 0, CH_0, rank 0
4140 23:03:08.199548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4141 23:03:08.199652 ==
4142 23:03:08.199744
4143 23:03:08.199830
4144 23:03:08.199918 TX Vref Scan disable
4145 23:03:08.203142 == TX Byte 0 ==
4146 23:03:08.206196 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4147 23:03:08.213487 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4148 23:03:08.213587 == TX Byte 1 ==
4149 23:03:08.216382 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4150 23:03:08.223039 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4151 23:03:08.223141 ==
4152 23:03:08.226441 Dram Type= 6, Freq= 0, CH_0, rank 0
4153 23:03:08.229465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4154 23:03:08.229539 ==
4155 23:03:08.229599
4156 23:03:08.229677
4157 23:03:08.233174 TX Vref Scan disable
4158 23:03:08.236604 == TX Byte 0 ==
4159 23:03:08.239342 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4160 23:03:08.243109 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4161 23:03:08.246092 == TX Byte 1 ==
4162 23:03:08.249407 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4163 23:03:08.252836 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4164 23:03:08.252938
4165 23:03:08.253027 [DATLAT]
4166 23:03:08.255815 Freq=600, CH0 RK0
4167 23:03:08.255919
4168 23:03:08.259759 DATLAT Default: 0x9
4169 23:03:08.259860 0, 0xFFFF, sum = 0
4170 23:03:08.262471 1, 0xFFFF, sum = 0
4171 23:03:08.262573 2, 0xFFFF, sum = 0
4172 23:03:08.265984 3, 0xFFFF, sum = 0
4173 23:03:08.266085 4, 0xFFFF, sum = 0
4174 23:03:08.269230 5, 0xFFFF, sum = 0
4175 23:03:08.269330 6, 0xFFFF, sum = 0
4176 23:03:08.272754 7, 0xFFFF, sum = 0
4177 23:03:08.272827 8, 0x0, sum = 1
4178 23:03:08.275920 9, 0x0, sum = 2
4179 23:03:08.276022 10, 0x0, sum = 3
4180 23:03:08.279304 11, 0x0, sum = 4
4181 23:03:08.279404 best_step = 9
4182 23:03:08.279491
4183 23:03:08.279579 ==
4184 23:03:08.282391 Dram Type= 6, Freq= 0, CH_0, rank 0
4185 23:03:08.285745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4186 23:03:08.285845 ==
4187 23:03:08.289146 RX Vref Scan: 1
4188 23:03:08.289241
4189 23:03:08.292478 RX Vref 0 -> 0, step: 1
4190 23:03:08.292583
4191 23:03:08.292674 RX Delay -195 -> 252, step: 8
4192 23:03:08.292764
4193 23:03:08.295786 Set Vref, RX VrefLevel [Byte0]: 60
4194 23:03:08.299241 [Byte1]: 57
4195 23:03:08.303793
4196 23:03:08.303895 Final RX Vref Byte 0 = 60 to rank0
4197 23:03:08.307076 Final RX Vref Byte 1 = 57 to rank0
4198 23:03:08.310302 Final RX Vref Byte 0 = 60 to rank1
4199 23:03:08.313725 Final RX Vref Byte 1 = 57 to rank1==
4200 23:03:08.316688 Dram Type= 6, Freq= 0, CH_0, rank 0
4201 23:03:08.323756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4202 23:03:08.323860 ==
4203 23:03:08.323953 DQS Delay:
4204 23:03:08.324040 DQS0 = 0, DQS1 = 0
4205 23:03:08.326919 DQM Delay:
4206 23:03:08.327019 DQM0 = 34, DQM1 = 27
4207 23:03:08.330356 DQ Delay:
4208 23:03:08.333609 DQ0 =36, DQ1 =36, DQ2 =32, DQ3 =32
4209 23:03:08.336876 DQ4 =32, DQ5 =20, DQ6 =40, DQ7 =48
4210 23:03:08.340038 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4211 23:03:08.343896 DQ12 =32, DQ13 =32, DQ14 =40, DQ15 =36
4212 23:03:08.343996
4213 23:03:08.344087
4214 23:03:08.349935 [DQSOSCAuto] RK0, (LSB)MR18= 0x3c3c, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 398 ps
4215 23:03:08.353755 CH0 RK0: MR19=808, MR18=3C3C
4216 23:03:08.359839 CH0_RK0: MR19=0x808, MR18=0x3C3C, DQSOSC=398, MR23=63, INC=165, DEC=110
4217 23:03:08.359940
4218 23:03:08.363498 ----->DramcWriteLeveling(PI) begin...
4219 23:03:08.363597 ==
4220 23:03:08.366638 Dram Type= 6, Freq= 0, CH_0, rank 1
4221 23:03:08.369821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4222 23:03:08.369921 ==
4223 23:03:08.373613 Write leveling (Byte 0): 36 => 36
4224 23:03:08.376735 Write leveling (Byte 1): 30 => 30
4225 23:03:08.379962 DramcWriteLeveling(PI) end<-----
4226 23:03:08.380063
4227 23:03:08.380155 ==
4228 23:03:08.383691 Dram Type= 6, Freq= 0, CH_0, rank 1
4229 23:03:08.386795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4230 23:03:08.386894 ==
4231 23:03:08.390031 [Gating] SW mode calibration
4232 23:03:08.396896 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4233 23:03:08.403225 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4234 23:03:08.406301 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4235 23:03:08.412960 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4236 23:03:08.416417 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4237 23:03:08.419873 0 9 12 | B1->B0 | 3434 2f2f | 0 1 | (0 0) (1 0)
4238 23:03:08.426438 0 9 16 | B1->B0 | 3030 2323 | 0 0 | (1 1) (0 0)
4239 23:03:08.429616 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4240 23:03:08.432877 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4241 23:03:08.439465 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4242 23:03:08.443018 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4243 23:03:08.446069 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4244 23:03:08.449531 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4245 23:03:08.456037 0 10 12 | B1->B0 | 2626 3434 | 0 1 | (0 0) (0 0)
4246 23:03:08.459476 0 10 16 | B1->B0 | 3a3a 4545 | 1 0 | (0 0) (0 0)
4247 23:03:08.463052 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4248 23:03:08.469504 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4249 23:03:08.472542 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4250 23:03:08.476268 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4251 23:03:08.482523 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4252 23:03:08.485932 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4253 23:03:08.489166 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4254 23:03:08.496293 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4255 23:03:08.499528 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 23:03:08.502647 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 23:03:08.509305 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 23:03:08.512374 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 23:03:08.515798 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 23:03:08.522349 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4261 23:03:08.525574 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4262 23:03:08.529016 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 23:03:08.535397 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 23:03:08.539251 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4265 23:03:08.541996 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4266 23:03:08.548486 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4267 23:03:08.552051 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4268 23:03:08.554996 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4269 23:03:08.561951 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4270 23:03:08.565247 Total UI for P1: 0, mck2ui 16
4271 23:03:08.568568 best dqsien dly found for B0: ( 0, 13, 10)
4272 23:03:08.571826 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4273 23:03:08.575395 Total UI for P1: 0, mck2ui 16
4274 23:03:08.578662 best dqsien dly found for B1: ( 0, 13, 14)
4275 23:03:08.581769 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4276 23:03:08.584892 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4277 23:03:08.584963
4278 23:03:08.588266 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4279 23:03:08.594725 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4280 23:03:08.594829 [Gating] SW calibration Done
4281 23:03:08.594927 ==
4282 23:03:08.598515 Dram Type= 6, Freq= 0, CH_0, rank 1
4283 23:03:08.604621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4284 23:03:08.604721 ==
4285 23:03:08.604813 RX Vref Scan: 0
4286 23:03:08.604900
4287 23:03:08.608063 RX Vref 0 -> 0, step: 1
4288 23:03:08.608185
4289 23:03:08.611203 RX Delay -230 -> 252, step: 16
4290 23:03:08.614954 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4291 23:03:08.617828 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4292 23:03:08.624851 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4293 23:03:08.627680 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4294 23:03:08.631342 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4295 23:03:08.634601 iDelay=218, Bit 5, Center 17 (-150 ~ 185) 336
4296 23:03:08.637899 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4297 23:03:08.644326 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4298 23:03:08.647394 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4299 23:03:08.650667 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4300 23:03:08.654642 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4301 23:03:08.661056 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4302 23:03:08.664325 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4303 23:03:08.667448 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4304 23:03:08.671092 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4305 23:03:08.677669 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4306 23:03:08.677760 ==
4307 23:03:08.680629 Dram Type= 6, Freq= 0, CH_0, rank 1
4308 23:03:08.683884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4309 23:03:08.683988 ==
4310 23:03:08.684079 DQS Delay:
4311 23:03:08.687143 DQS0 = 0, DQS1 = 0
4312 23:03:08.687246 DQM Delay:
4313 23:03:08.690860 DQM0 = 35, DQM1 = 28
4314 23:03:08.690964 DQ Delay:
4315 23:03:08.693802 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4316 23:03:08.697325 DQ4 =33, DQ5 =17, DQ6 =49, DQ7 =49
4317 23:03:08.700607 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4318 23:03:08.703705 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4319 23:03:08.703807
4320 23:03:08.703901
4321 23:03:08.703987 ==
4322 23:03:08.707497 Dram Type= 6, Freq= 0, CH_0, rank 1
4323 23:03:08.710500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4324 23:03:08.713557 ==
4325 23:03:08.713674
4326 23:03:08.713768
4327 23:03:08.713861 TX Vref Scan disable
4328 23:03:08.716823 == TX Byte 0 ==
4329 23:03:08.720427 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4330 23:03:08.723850 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4331 23:03:08.726947 == TX Byte 1 ==
4332 23:03:08.730286 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4333 23:03:08.733460 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4334 23:03:08.737214 ==
4335 23:03:08.740310 Dram Type= 6, Freq= 0, CH_0, rank 1
4336 23:03:08.743568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4337 23:03:08.743678 ==
4338 23:03:08.743770
4339 23:03:08.743870
4340 23:03:08.746674 TX Vref Scan disable
4341 23:03:08.749975 == TX Byte 0 ==
4342 23:03:08.753350 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4343 23:03:08.756664 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4344 23:03:08.759809 == TX Byte 1 ==
4345 23:03:08.763086 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4346 23:03:08.766800 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4347 23:03:08.766908
4348 23:03:08.767002 [DATLAT]
4349 23:03:08.769844 Freq=600, CH0 RK1
4350 23:03:08.769947
4351 23:03:08.773065 DATLAT Default: 0x9
4352 23:03:08.773166 0, 0xFFFF, sum = 0
4353 23:03:08.776224 1, 0xFFFF, sum = 0
4354 23:03:08.776340 2, 0xFFFF, sum = 0
4355 23:03:08.779875 3, 0xFFFF, sum = 0
4356 23:03:08.779978 4, 0xFFFF, sum = 0
4357 23:03:08.783262 5, 0xFFFF, sum = 0
4358 23:03:08.783361 6, 0xFFFF, sum = 0
4359 23:03:08.786655 7, 0xFFFF, sum = 0
4360 23:03:08.786757 8, 0x0, sum = 1
4361 23:03:08.789852 9, 0x0, sum = 2
4362 23:03:08.789955 10, 0x0, sum = 3
4363 23:03:08.790047 11, 0x0, sum = 4
4364 23:03:08.792711 best_step = 9
4365 23:03:08.792819
4366 23:03:08.792911 ==
4367 23:03:08.796635 Dram Type= 6, Freq= 0, CH_0, rank 1
4368 23:03:08.799426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4369 23:03:08.799561 ==
4370 23:03:08.802882 RX Vref Scan: 0
4371 23:03:08.802963
4372 23:03:08.806362 RX Vref 0 -> 0, step: 1
4373 23:03:08.806471
4374 23:03:08.806568 RX Delay -195 -> 252, step: 8
4375 23:03:08.813829 iDelay=205, Bit 0, Center 32 (-123 ~ 188) 312
4376 23:03:08.817467 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4377 23:03:08.820391 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4378 23:03:08.823694 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4379 23:03:08.830346 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4380 23:03:08.834037 iDelay=205, Bit 5, Center 24 (-131 ~ 180) 312
4381 23:03:08.837002 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4382 23:03:08.840320 iDelay=205, Bit 7, Center 40 (-115 ~ 196) 312
4383 23:03:08.847005 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4384 23:03:08.850381 iDelay=205, Bit 9, Center 12 (-147 ~ 172) 320
4385 23:03:08.853617 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4386 23:03:08.857297 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4387 23:03:08.860410 iDelay=205, Bit 12, Center 32 (-131 ~ 196) 328
4388 23:03:08.866778 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4389 23:03:08.870218 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4390 23:03:08.873778 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4391 23:03:08.873883 ==
4392 23:03:08.876849 Dram Type= 6, Freq= 0, CH_0, rank 1
4393 23:03:08.883503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4394 23:03:08.883605 ==
4395 23:03:08.883700 DQS Delay:
4396 23:03:08.883788 DQS0 = 0, DQS1 = 0
4397 23:03:08.886583 DQM Delay:
4398 23:03:08.886686 DQM0 = 33, DQM1 = 27
4399 23:03:08.890505 DQ Delay:
4400 23:03:08.893550 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =28
4401 23:03:08.896758 DQ4 =32, DQ5 =24, DQ6 =44, DQ7 =40
4402 23:03:08.896863 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4403 23:03:08.903107 DQ12 =32, DQ13 =36, DQ14 =36, DQ15 =36
4404 23:03:08.903215
4405 23:03:08.903305
4406 23:03:08.909959 [DQSOSCAuto] RK1, (LSB)MR18= 0x6e3e, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 389 ps
4407 23:03:08.913124 CH0 RK1: MR19=808, MR18=6E3E
4408 23:03:08.919868 CH0_RK1: MR19=0x808, MR18=0x6E3E, DQSOSC=389, MR23=63, INC=173, DEC=115
4409 23:03:08.923303 [RxdqsGatingPostProcess] freq 600
4410 23:03:08.926543 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4411 23:03:08.929959 Pre-setting of DQS Precalculation
4412 23:03:08.936374 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4413 23:03:08.936478 ==
4414 23:03:08.939820 Dram Type= 6, Freq= 0, CH_1, rank 0
4415 23:03:08.943458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4416 23:03:08.943564 ==
4417 23:03:08.949812 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4418 23:03:08.953242 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4419 23:03:08.957267 [CA 0] Center 36 (6~66) winsize 61
4420 23:03:08.961017 [CA 1] Center 36 (6~66) winsize 61
4421 23:03:08.964184 [CA 2] Center 34 (4~65) winsize 62
4422 23:03:08.967441 [CA 3] Center 34 (3~65) winsize 63
4423 23:03:08.971151 [CA 4] Center 34 (4~65) winsize 62
4424 23:03:08.974186 [CA 5] Center 33 (3~64) winsize 62
4425 23:03:08.974289
4426 23:03:08.977434 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4427 23:03:08.977532
4428 23:03:08.981102 [CATrainingPosCal] consider 1 rank data
4429 23:03:08.984374 u2DelayCellTimex100 = 270/100 ps
4430 23:03:08.987525 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4431 23:03:08.990779 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4432 23:03:08.997447 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4433 23:03:09.000961 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4434 23:03:09.004212 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4435 23:03:09.007348 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4436 23:03:09.007450
4437 23:03:09.010621 CA PerBit enable=1, Macro0, CA PI delay=33
4438 23:03:09.010723
4439 23:03:09.014325 [CBTSetCACLKResult] CA Dly = 33
4440 23:03:09.014427 CS Dly: 5 (0~36)
4441 23:03:09.017443 ==
4442 23:03:09.017522 Dram Type= 6, Freq= 0, CH_1, rank 1
4443 23:03:09.024298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4444 23:03:09.024402 ==
4445 23:03:09.027523 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4446 23:03:09.033827 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4447 23:03:09.037609 [CA 0] Center 36 (6~66) winsize 61
4448 23:03:09.041333 [CA 1] Center 35 (5~66) winsize 62
4449 23:03:09.044104 [CA 2] Center 34 (4~65) winsize 62
4450 23:03:09.047639 [CA 3] Center 34 (3~65) winsize 63
4451 23:03:09.051276 [CA 4] Center 34 (4~65) winsize 62
4452 23:03:09.054407 [CA 5] Center 33 (3~64) winsize 62
4453 23:03:09.054518
4454 23:03:09.057363 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4455 23:03:09.057469
4456 23:03:09.060838 [CATrainingPosCal] consider 2 rank data
4457 23:03:09.064045 u2DelayCellTimex100 = 270/100 ps
4458 23:03:09.067559 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4459 23:03:09.074067 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4460 23:03:09.077226 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4461 23:03:09.080826 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4462 23:03:09.083746 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4463 23:03:09.087260 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4464 23:03:09.087381
4465 23:03:09.090466 CA PerBit enable=1, Macro0, CA PI delay=33
4466 23:03:09.090557
4467 23:03:09.094087 [CBTSetCACLKResult] CA Dly = 33
4468 23:03:09.094180 CS Dly: 5 (0~37)
4469 23:03:09.097285
4470 23:03:09.100491 ----->DramcWriteLeveling(PI) begin...
4471 23:03:09.100589 ==
4472 23:03:09.104324 Dram Type= 6, Freq= 0, CH_1, rank 0
4473 23:03:09.107452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4474 23:03:09.107550 ==
4475 23:03:09.110581 Write leveling (Byte 0): 29 => 29
4476 23:03:09.113900 Write leveling (Byte 1): 32 => 32
4477 23:03:09.117064 DramcWriteLeveling(PI) end<-----
4478 23:03:09.117171
4479 23:03:09.117255 ==
4480 23:03:09.120786 Dram Type= 6, Freq= 0, CH_1, rank 0
4481 23:03:09.124095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4482 23:03:09.124210 ==
4483 23:03:09.127036 [Gating] SW mode calibration
4484 23:03:09.133462 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4485 23:03:09.140169 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4486 23:03:09.143972 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4487 23:03:09.147028 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4488 23:03:09.153540 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4489 23:03:09.157155 0 9 12 | B1->B0 | 3131 3131 | 1 1 | (1 0) (1 0)
4490 23:03:09.160345 0 9 16 | B1->B0 | 2a2a 2626 | 1 0 | (0 0) (0 0)
4491 23:03:09.166890 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4492 23:03:09.170213 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4493 23:03:09.173344 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4494 23:03:09.179986 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4495 23:03:09.183565 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4496 23:03:09.186574 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4497 23:03:09.193061 0 10 12 | B1->B0 | 2f2f 2727 | 0 0 | (0 0) (0 0)
4498 23:03:09.196521 0 10 16 | B1->B0 | 4545 4444 | 0 0 | (0 0) (0 0)
4499 23:03:09.199711 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4500 23:03:09.206836 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4501 23:03:09.209830 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4502 23:03:09.213094 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4503 23:03:09.216598 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4504 23:03:09.223677 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4505 23:03:09.226744 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4506 23:03:09.230084 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4507 23:03:09.236693 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4508 23:03:09.239589 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4509 23:03:09.243159 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 23:03:09.253998 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4511 23:03:09.254115 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4512 23:03:09.256546 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4513 23:03:09.262942 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4514 23:03:09.266051 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4515 23:03:09.269285 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4516 23:03:09.275987 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4517 23:03:09.279230 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4518 23:03:09.282714 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4519 23:03:09.289496 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4520 23:03:09.292550 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4521 23:03:09.295707 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4522 23:03:09.302656 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4523 23:03:09.305960 Total UI for P1: 0, mck2ui 16
4524 23:03:09.309417 best dqsien dly found for B0: ( 0, 13, 12)
4525 23:03:09.309503 Total UI for P1: 0, mck2ui 16
4526 23:03:09.316133 best dqsien dly found for B1: ( 0, 13, 14)
4527 23:03:09.319081 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4528 23:03:09.322783 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4529 23:03:09.322866
4530 23:03:09.325914 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4531 23:03:09.329172 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4532 23:03:09.332329 [Gating] SW calibration Done
4533 23:03:09.332412 ==
4534 23:03:09.336050 Dram Type= 6, Freq= 0, CH_1, rank 0
4535 23:03:09.339137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4536 23:03:09.339276 ==
4537 23:03:09.342293 RX Vref Scan: 0
4538 23:03:09.342401
4539 23:03:09.342494 RX Vref 0 -> 0, step: 1
4540 23:03:09.342583
4541 23:03:09.345880 RX Delay -230 -> 252, step: 16
4542 23:03:09.352225 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4543 23:03:09.355932 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4544 23:03:09.359518 iDelay=218, Bit 2, Center 25 (-150 ~ 201) 352
4545 23:03:09.362365 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4546 23:03:09.368972 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4547 23:03:09.372488 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4548 23:03:09.375609 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4549 23:03:09.379139 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4550 23:03:09.381896 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4551 23:03:09.388833 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4552 23:03:09.391902 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4553 23:03:09.395291 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4554 23:03:09.399080 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4555 23:03:09.405642 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4556 23:03:09.408543 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4557 23:03:09.411708 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4558 23:03:09.411781 ==
4559 23:03:09.415073 Dram Type= 6, Freq= 0, CH_1, rank 0
4560 23:03:09.418646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4561 23:03:09.421638 ==
4562 23:03:09.421716 DQS Delay:
4563 23:03:09.421779 DQS0 = 0, DQS1 = 0
4564 23:03:09.424969 DQM Delay:
4565 23:03:09.425049 DQM0 = 38, DQM1 = 28
4566 23:03:09.428601 DQ Delay:
4567 23:03:09.428683 DQ0 =49, DQ1 =33, DQ2 =25, DQ3 =33
4568 23:03:09.431727 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4569 23:03:09.435083 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4570 23:03:09.438251 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4571 23:03:09.441410
4572 23:03:09.441490
4573 23:03:09.441552 ==
4574 23:03:09.445115 Dram Type= 6, Freq= 0, CH_1, rank 0
4575 23:03:09.448236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4576 23:03:09.448331 ==
4577 23:03:09.448393
4578 23:03:09.448450
4579 23:03:09.451541 TX Vref Scan disable
4580 23:03:09.451621 == TX Byte 0 ==
4581 23:03:09.458530 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4582 23:03:09.461363 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4583 23:03:09.461493 == TX Byte 1 ==
4584 23:03:09.468173 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4585 23:03:09.471903 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4586 23:03:09.472087 ==
4587 23:03:09.474543 Dram Type= 6, Freq= 0, CH_1, rank 0
4588 23:03:09.478332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4589 23:03:09.478476 ==
4590 23:03:09.478603
4591 23:03:09.478722
4592 23:03:09.481356 TX Vref Scan disable
4593 23:03:09.484645 == TX Byte 0 ==
4594 23:03:09.487777 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4595 23:03:09.491661 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4596 23:03:09.495100 == TX Byte 1 ==
4597 23:03:09.498339 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4598 23:03:09.504584 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4599 23:03:09.504695
4600 23:03:09.504787 [DATLAT]
4601 23:03:09.504876 Freq=600, CH1 RK0
4602 23:03:09.504990
4603 23:03:09.508027 DATLAT Default: 0x9
4604 23:03:09.508134 0, 0xFFFF, sum = 0
4605 23:03:09.511101 1, 0xFFFF, sum = 0
4606 23:03:09.511183 2, 0xFFFF, sum = 0
4607 23:03:09.514491 3, 0xFFFF, sum = 0
4608 23:03:09.518339 4, 0xFFFF, sum = 0
4609 23:03:09.518448 5, 0xFFFF, sum = 0
4610 23:03:09.521448 6, 0xFFFF, sum = 0
4611 23:03:09.521549 7, 0xFFFF, sum = 0
4612 23:03:09.524950 8, 0x0, sum = 1
4613 23:03:09.525075 9, 0x0, sum = 2
4614 23:03:09.525190 10, 0x0, sum = 3
4615 23:03:09.528164 11, 0x0, sum = 4
4616 23:03:09.528288 best_step = 9
4617 23:03:09.528351
4618 23:03:09.528408 ==
4619 23:03:09.531075 Dram Type= 6, Freq= 0, CH_1, rank 0
4620 23:03:09.537596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4621 23:03:09.537722 ==
4622 23:03:09.537838 RX Vref Scan: 1
4623 23:03:09.537978
4624 23:03:09.540799 RX Vref 0 -> 0, step: 1
4625 23:03:09.540870
4626 23:03:09.544194 RX Delay -195 -> 252, step: 8
4627 23:03:09.544314
4628 23:03:09.547824 Set Vref, RX VrefLevel [Byte0]: 56
4629 23:03:09.550816 [Byte1]: 56
4630 23:03:09.550897
4631 23:03:09.554038 Final RX Vref Byte 0 = 56 to rank0
4632 23:03:09.557455 Final RX Vref Byte 1 = 56 to rank0
4633 23:03:09.561194 Final RX Vref Byte 0 = 56 to rank1
4634 23:03:09.564050 Final RX Vref Byte 1 = 56 to rank1==
4635 23:03:09.567576 Dram Type= 6, Freq= 0, CH_1, rank 0
4636 23:03:09.571037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4637 23:03:09.571119 ==
4638 23:03:09.574048 DQS Delay:
4639 23:03:09.574129 DQS0 = 0, DQS1 = 0
4640 23:03:09.577553 DQM Delay:
4641 23:03:09.577633 DQM0 = 39, DQM1 = 28
4642 23:03:09.577697 DQ Delay:
4643 23:03:09.580716 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =36
4644 23:03:09.584000 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =36
4645 23:03:09.587315 DQ8 =12, DQ9 =20, DQ10 =28, DQ11 =20
4646 23:03:09.590586 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4647 23:03:09.590667
4648 23:03:09.590729
4649 23:03:09.600557 [DQSOSCAuto] RK0, (LSB)MR18= 0x2634, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 402 ps
4650 23:03:09.603853 CH1 RK0: MR19=808, MR18=2634
4651 23:03:09.610721 CH1_RK0: MR19=0x808, MR18=0x2634, DQSOSC=400, MR23=63, INC=163, DEC=109
4652 23:03:09.610802
4653 23:03:09.614062 ----->DramcWriteLeveling(PI) begin...
4654 23:03:09.614143 ==
4655 23:03:09.617278 Dram Type= 6, Freq= 0, CH_1, rank 1
4656 23:03:09.620401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4657 23:03:09.620482 ==
4658 23:03:09.624152 Write leveling (Byte 0): 30 => 30
4659 23:03:09.627116 Write leveling (Byte 1): 30 => 30
4660 23:03:09.630619 DramcWriteLeveling(PI) end<-----
4661 23:03:09.630700
4662 23:03:09.630763 ==
4663 23:03:09.633785 Dram Type= 6, Freq= 0, CH_1, rank 1
4664 23:03:09.637309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4665 23:03:09.637390 ==
4666 23:03:09.640537 [Gating] SW mode calibration
4667 23:03:09.647184 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4668 23:03:09.653588 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4669 23:03:09.657464 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4670 23:03:09.660699 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4671 23:03:09.666993 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
4672 23:03:09.670637 0 9 12 | B1->B0 | 3131 2f2f | 1 1 | (1 1) (1 0)
4673 23:03:09.673678 0 9 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4674 23:03:09.680396 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4675 23:03:09.683753 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4676 23:03:09.687063 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4677 23:03:09.693449 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4678 23:03:09.696714 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4679 23:03:09.700557 0 10 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
4680 23:03:09.706924 0 10 12 | B1->B0 | 302f 3838 | 1 1 | (0 0) (1 1)
4681 23:03:09.710245 0 10 16 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
4682 23:03:09.713574 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4683 23:03:09.720223 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4684 23:03:09.723423 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4685 23:03:09.726670 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4686 23:03:09.733027 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4687 23:03:09.736789 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4688 23:03:09.739645 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4689 23:03:09.746355 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4690 23:03:09.749472 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4691 23:03:09.753387 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4692 23:03:09.756359 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4693 23:03:09.763305 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4694 23:03:09.766305 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4695 23:03:09.769765 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4696 23:03:09.776721 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4697 23:03:09.779564 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4698 23:03:09.783244 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4699 23:03:09.789591 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4700 23:03:09.793137 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4701 23:03:09.796329 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4702 23:03:09.802830 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4703 23:03:09.806647 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4704 23:03:09.809757 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4705 23:03:09.813104 Total UI for P1: 0, mck2ui 16
4706 23:03:09.816447 best dqsien dly found for B0: ( 0, 13, 10)
4707 23:03:09.822687 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4708 23:03:09.822768 Total UI for P1: 0, mck2ui 16
4709 23:03:09.829509 best dqsien dly found for B1: ( 0, 13, 12)
4710 23:03:09.832752 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4711 23:03:09.836162 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4712 23:03:09.836291
4713 23:03:09.839779 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4714 23:03:09.842677 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4715 23:03:09.846374 [Gating] SW calibration Done
4716 23:03:09.846455 ==
4717 23:03:09.849658 Dram Type= 6, Freq= 0, CH_1, rank 1
4718 23:03:09.852951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4719 23:03:09.853032 ==
4720 23:03:09.856037 RX Vref Scan: 0
4721 23:03:09.856142
4722 23:03:09.856263 RX Vref 0 -> 0, step: 1
4723 23:03:09.859687
4724 23:03:09.859767 RX Delay -230 -> 252, step: 16
4725 23:03:09.865760 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4726 23:03:09.869138 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4727 23:03:09.872423 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4728 23:03:09.875631 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4729 23:03:09.882195 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4730 23:03:09.885846 iDelay=218, Bit 5, Center 41 (-134 ~ 217) 352
4731 23:03:09.888809 iDelay=218, Bit 6, Center 41 (-134 ~ 217) 352
4732 23:03:09.891951 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4733 23:03:09.895699 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4734 23:03:09.901883 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4735 23:03:09.905416 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4736 23:03:09.908687 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4737 23:03:09.911862 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4738 23:03:09.918370 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4739 23:03:09.922319 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4740 23:03:09.925382 iDelay=218, Bit 15, Center 41 (-134 ~ 217) 352
4741 23:03:09.925461 ==
4742 23:03:09.928355 Dram Type= 6, Freq= 0, CH_1, rank 1
4743 23:03:09.934815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4744 23:03:09.934891 ==
4745 23:03:09.934958 DQS Delay:
4746 23:03:09.935021 DQS0 = 0, DQS1 = 0
4747 23:03:09.938229 DQM Delay:
4748 23:03:09.938300 DQM0 = 33, DQM1 = 30
4749 23:03:09.941777 DQ Delay:
4750 23:03:09.944906 DQ0 =33, DQ1 =33, DQ2 =17, DQ3 =33
4751 23:03:09.948070 DQ4 =33, DQ5 =41, DQ6 =41, DQ7 =33
4752 23:03:09.951834 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4753 23:03:09.955095 DQ12 =33, DQ13 =41, DQ14 =33, DQ15 =41
4754 23:03:09.955176
4755 23:03:09.955242
4756 23:03:09.955300 ==
4757 23:03:09.958252 Dram Type= 6, Freq= 0, CH_1, rank 1
4758 23:03:09.961456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4759 23:03:09.961528 ==
4760 23:03:09.961598
4761 23:03:09.961656
4762 23:03:09.964781 TX Vref Scan disable
4763 23:03:09.964854 == TX Byte 0 ==
4764 23:03:09.971527 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4765 23:03:09.974751 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4766 23:03:09.974827 == TX Byte 1 ==
4767 23:03:09.981616 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4768 23:03:09.984716 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4769 23:03:09.984791 ==
4770 23:03:09.988087 Dram Type= 6, Freq= 0, CH_1, rank 1
4771 23:03:09.991266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4772 23:03:09.991343 ==
4773 23:03:09.991406
4774 23:03:09.991470
4775 23:03:09.994440 TX Vref Scan disable
4776 23:03:09.998378 == TX Byte 0 ==
4777 23:03:10.001537 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4778 23:03:10.004648 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4779 23:03:10.008206 == TX Byte 1 ==
4780 23:03:10.011665 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4781 23:03:10.017987 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4782 23:03:10.018065
4783 23:03:10.018128 [DATLAT]
4784 23:03:10.018196 Freq=600, CH1 RK1
4785 23:03:10.018258
4786 23:03:10.021223 DATLAT Default: 0x9
4787 23:03:10.021310 0, 0xFFFF, sum = 0
4788 23:03:10.024586 1, 0xFFFF, sum = 0
4789 23:03:10.024669 2, 0xFFFF, sum = 0
4790 23:03:10.027965 3, 0xFFFF, sum = 0
4791 23:03:10.028048 4, 0xFFFF, sum = 0
4792 23:03:10.031310 5, 0xFFFF, sum = 0
4793 23:03:10.034636 6, 0xFFFF, sum = 0
4794 23:03:10.034718 7, 0xFFFF, sum = 0
4795 23:03:10.038231 8, 0x0, sum = 1
4796 23:03:10.038314 9, 0x0, sum = 2
4797 23:03:10.038379 10, 0x0, sum = 3
4798 23:03:10.041624 11, 0x0, sum = 4
4799 23:03:10.041701 best_step = 9
4800 23:03:10.041788
4801 23:03:10.041868 ==
4802 23:03:10.044886 Dram Type= 6, Freq= 0, CH_1, rank 1
4803 23:03:10.051025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4804 23:03:10.051104 ==
4805 23:03:10.051175 RX Vref Scan: 0
4806 23:03:10.051238
4807 23:03:10.054737 RX Vref 0 -> 0, step: 1
4808 23:03:10.054812
4809 23:03:10.057892 RX Delay -195 -> 252, step: 8
4810 23:03:10.061198 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4811 23:03:10.067687 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4812 23:03:10.071068 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4813 23:03:10.074883 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4814 23:03:10.077687 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4815 23:03:10.084446 iDelay=205, Bit 5, Center 44 (-115 ~ 204) 320
4816 23:03:10.087624 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4817 23:03:10.091397 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4818 23:03:10.094349 iDelay=205, Bit 8, Center 16 (-147 ~ 180) 328
4819 23:03:10.097654 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4820 23:03:10.104103 iDelay=205, Bit 10, Center 32 (-131 ~ 196) 328
4821 23:03:10.107415 iDelay=205, Bit 11, Center 24 (-139 ~ 188) 328
4822 23:03:10.110991 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4823 23:03:10.113905 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4824 23:03:10.120554 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4825 23:03:10.123830 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4826 23:03:10.123911 ==
4827 23:03:10.127074 Dram Type= 6, Freq= 0, CH_1, rank 1
4828 23:03:10.130643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4829 23:03:10.130718 ==
4830 23:03:10.134301 DQS Delay:
4831 23:03:10.134382 DQS0 = 0, DQS1 = 0
4832 23:03:10.134451 DQM Delay:
4833 23:03:10.137118 DQM0 = 35, DQM1 = 29
4834 23:03:10.137200 DQ Delay:
4835 23:03:10.140889 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4836 23:03:10.144190 DQ4 =32, DQ5 =44, DQ6 =48, DQ7 =32
4837 23:03:10.147403 DQ8 =16, DQ9 =20, DQ10 =32, DQ11 =24
4838 23:03:10.150456 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4839 23:03:10.150537
4840 23:03:10.150608
4841 23:03:10.160396 [DQSOSCAuto] RK1, (LSB)MR18= 0x3757, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 399 ps
4842 23:03:10.163820 CH1 RK1: MR19=808, MR18=3757
4843 23:03:10.167121 CH1_RK1: MR19=0x808, MR18=0x3757, DQSOSC=393, MR23=63, INC=169, DEC=113
4844 23:03:10.170184 [RxdqsGatingPostProcess] freq 600
4845 23:03:10.177283 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4846 23:03:10.180415 Pre-setting of DQS Precalculation
4847 23:03:10.183853 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4848 23:03:10.193752 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4849 23:03:10.200126 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4850 23:03:10.200213
4851 23:03:10.200310
4852 23:03:10.203258 [Calibration Summary] 1200 Mbps
4853 23:03:10.203338 CH 0, Rank 0
4854 23:03:10.207027 SW Impedance : PASS
4855 23:03:10.207108 DUTY Scan : NO K
4856 23:03:10.210557 ZQ Calibration : PASS
4857 23:03:10.213518 Jitter Meter : NO K
4858 23:03:10.213590 CBT Training : PASS
4859 23:03:10.216729 Write leveling : PASS
4860 23:03:10.220166 RX DQS gating : PASS
4861 23:03:10.220297 RX DQ/DQS(RDDQC) : PASS
4862 23:03:10.223573 TX DQ/DQS : PASS
4863 23:03:10.226818 RX DATLAT : PASS
4864 23:03:10.226920 RX DQ/DQS(Engine): PASS
4865 23:03:10.229973 TX OE : NO K
4866 23:03:10.230046 All Pass.
4867 23:03:10.230107
4868 23:03:10.233148 CH 0, Rank 1
4869 23:03:10.233220 SW Impedance : PASS
4870 23:03:10.237078 DUTY Scan : NO K
4871 23:03:10.239863 ZQ Calibration : PASS
4872 23:03:10.239935 Jitter Meter : NO K
4873 23:03:10.243051 CBT Training : PASS
4874 23:03:10.243122 Write leveling : PASS
4875 23:03:10.246658 RX DQS gating : PASS
4876 23:03:10.249722 RX DQ/DQS(RDDQC) : PASS
4877 23:03:10.249802 TX DQ/DQS : PASS
4878 23:03:10.253129 RX DATLAT : PASS
4879 23:03:10.256345 RX DQ/DQS(Engine): PASS
4880 23:03:10.256421 TX OE : NO K
4881 23:03:10.259630 All Pass.
4882 23:03:10.259703
4883 23:03:10.259769 CH 1, Rank 0
4884 23:03:10.263344 SW Impedance : PASS
4885 23:03:10.263412 DUTY Scan : NO K
4886 23:03:10.266277 ZQ Calibration : PASS
4887 23:03:10.269616 Jitter Meter : NO K
4888 23:03:10.269694 CBT Training : PASS
4889 23:03:10.272804 Write leveling : PASS
4890 23:03:10.276082 RX DQS gating : PASS
4891 23:03:10.276164 RX DQ/DQS(RDDQC) : PASS
4892 23:03:10.279489 TX DQ/DQS : PASS
4893 23:03:10.282620 RX DATLAT : PASS
4894 23:03:10.282691 RX DQ/DQS(Engine): PASS
4895 23:03:10.286292 TX OE : NO K
4896 23:03:10.286366 All Pass.
4897 23:03:10.286429
4898 23:03:10.289512 CH 1, Rank 1
4899 23:03:10.289586 SW Impedance : PASS
4900 23:03:10.292781 DUTY Scan : NO K
4901 23:03:10.296254 ZQ Calibration : PASS
4902 23:03:10.296336 Jitter Meter : NO K
4903 23:03:10.299384 CBT Training : PASS
4904 23:03:10.302826 Write leveling : PASS
4905 23:03:10.302904 RX DQS gating : PASS
4906 23:03:10.306250 RX DQ/DQS(RDDQC) : PASS
4907 23:03:10.306329 TX DQ/DQS : PASS
4908 23:03:10.309657 RX DATLAT : PASS
4909 23:03:10.312812 RX DQ/DQS(Engine): PASS
4910 23:03:10.312888 TX OE : NO K
4911 23:03:10.315950 All Pass.
4912 23:03:10.316022
4913 23:03:10.316087 DramC Write-DBI off
4914 23:03:10.319096 PER_BANK_REFRESH: Hybrid Mode
4915 23:03:10.322847 TX_TRACKING: ON
4916 23:03:10.329108 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4917 23:03:10.332490 [FAST_K] Save calibration result to emmc
4918 23:03:10.335839 dramc_set_vcore_voltage set vcore to 662500
4919 23:03:10.338978 Read voltage for 933, 3
4920 23:03:10.339065 Vio18 = 0
4921 23:03:10.342570 Vcore = 662500
4922 23:03:10.342643 Vdram = 0
4923 23:03:10.342704 Vddq = 0
4924 23:03:10.345659 Vmddr = 0
4925 23:03:10.348937 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4926 23:03:10.355945 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4927 23:03:10.356023 MEM_TYPE=3, freq_sel=17
4928 23:03:10.358825 sv_algorithm_assistance_LP4_1600
4929 23:03:10.365510 ============ PULL DRAM RESETB DOWN ============
4930 23:03:10.369409 ========== PULL DRAM RESETB DOWN end =========
4931 23:03:10.372278 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4932 23:03:10.375560 ===================================
4933 23:03:10.378712 LPDDR4 DRAM CONFIGURATION
4934 23:03:10.382209 ===================================
4935 23:03:10.385917 EX_ROW_EN[0] = 0x0
4936 23:03:10.385991 EX_ROW_EN[1] = 0x0
4937 23:03:10.389130 LP4Y_EN = 0x0
4938 23:03:10.389204 WORK_FSP = 0x0
4939 23:03:10.392077 WL = 0x3
4940 23:03:10.392151 RL = 0x3
4941 23:03:10.395741 BL = 0x2
4942 23:03:10.395818 RPST = 0x0
4943 23:03:10.398659 RD_PRE = 0x0
4944 23:03:10.398736 WR_PRE = 0x1
4945 23:03:10.402293 WR_PST = 0x0
4946 23:03:10.402366 DBI_WR = 0x0
4947 23:03:10.405628 DBI_RD = 0x0
4948 23:03:10.405702 OTF = 0x1
4949 23:03:10.408864 ===================================
4950 23:03:10.412298 ===================================
4951 23:03:10.415660 ANA top config
4952 23:03:10.418684 ===================================
4953 23:03:10.421979 DLL_ASYNC_EN = 0
4954 23:03:10.422056 ALL_SLAVE_EN = 1
4955 23:03:10.425408 NEW_RANK_MODE = 1
4956 23:03:10.429023 DLL_IDLE_MODE = 1
4957 23:03:10.432175 LP45_APHY_COMB_EN = 1
4958 23:03:10.432267 TX_ODT_DIS = 1
4959 23:03:10.435409 NEW_8X_MODE = 1
4960 23:03:10.438717 ===================================
4961 23:03:10.441968 ===================================
4962 23:03:10.445347 data_rate = 1866
4963 23:03:10.448958 CKR = 1
4964 23:03:10.451836 DQ_P2S_RATIO = 8
4965 23:03:10.455463 ===================================
4966 23:03:10.458621 CA_P2S_RATIO = 8
4967 23:03:10.458694 DQ_CA_OPEN = 0
4968 23:03:10.461966 DQ_SEMI_OPEN = 0
4969 23:03:10.465278 CA_SEMI_OPEN = 0
4970 23:03:10.469119 CA_FULL_RATE = 0
4971 23:03:10.472238 DQ_CKDIV4_EN = 1
4972 23:03:10.475372 CA_CKDIV4_EN = 1
4973 23:03:10.475459 CA_PREDIV_EN = 0
4974 23:03:10.478617 PH8_DLY = 0
4975 23:03:10.481571 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4976 23:03:10.484850 DQ_AAMCK_DIV = 4
4977 23:03:10.488478 CA_AAMCK_DIV = 4
4978 23:03:10.491661 CA_ADMCK_DIV = 4
4979 23:03:10.491743 DQ_TRACK_CA_EN = 0
4980 23:03:10.494901 CA_PICK = 933
4981 23:03:10.498783 CA_MCKIO = 933
4982 23:03:10.501552 MCKIO_SEMI = 0
4983 23:03:10.505156 PLL_FREQ = 3732
4984 23:03:10.508385 DQ_UI_PI_RATIO = 32
4985 23:03:10.511560 CA_UI_PI_RATIO = 0
4986 23:03:10.514989 ===================================
4987 23:03:10.518566 ===================================
4988 23:03:10.518647 memory_type:LPDDR4
4989 23:03:10.521526 GP_NUM : 10
4990 23:03:10.524914 SRAM_EN : 1
4991 23:03:10.524995 MD32_EN : 0
4992 23:03:10.527919 ===================================
4993 23:03:10.531364 [ANA_INIT] >>>>>>>>>>>>>>
4994 23:03:10.534946 <<<<<< [CONFIGURE PHASE]: ANA_TX
4995 23:03:10.538176 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4996 23:03:10.541407 ===================================
4997 23:03:10.544613 data_rate = 1866,PCW = 0X8f00
4998 23:03:10.548121 ===================================
4999 23:03:10.551386 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5000 23:03:10.554708 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5001 23:03:10.561522 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5002 23:03:10.564767 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5003 23:03:10.567931 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5004 23:03:10.571062 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5005 23:03:10.574427 [ANA_INIT] flow start
5006 23:03:10.577922 [ANA_INIT] PLL >>>>>>>>
5007 23:03:10.578003 [ANA_INIT] PLL <<<<<<<<
5008 23:03:10.581186 [ANA_INIT] MIDPI >>>>>>>>
5009 23:03:10.584806 [ANA_INIT] MIDPI <<<<<<<<
5010 23:03:10.584881 [ANA_INIT] DLL >>>>>>>>
5011 23:03:10.587955 [ANA_INIT] flow end
5012 23:03:10.591209 ============ LP4 DIFF to SE enter ============
5013 23:03:10.598011 ============ LP4 DIFF to SE exit ============
5014 23:03:10.598121 [ANA_INIT] <<<<<<<<<<<<<
5015 23:03:10.601041 [Flow] Enable top DCM control >>>>>
5016 23:03:10.604290 [Flow] Enable top DCM control <<<<<
5017 23:03:10.608050 Enable DLL master slave shuffle
5018 23:03:10.614665 ==============================================================
5019 23:03:10.614745 Gating Mode config
5020 23:03:10.620876 ==============================================================
5021 23:03:10.624518 Config description:
5022 23:03:10.630927 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5023 23:03:10.637450 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5024 23:03:10.644526 SELPH_MODE 0: By rank 1: By Phase
5025 23:03:10.650785 ==============================================================
5026 23:03:10.650862 GAT_TRACK_EN = 1
5027 23:03:10.654533 RX_GATING_MODE = 2
5028 23:03:10.658134 RX_GATING_TRACK_MODE = 2
5029 23:03:10.661233 SELPH_MODE = 1
5030 23:03:10.664494 PICG_EARLY_EN = 1
5031 23:03:10.667723 VALID_LAT_VALUE = 1
5032 23:03:10.674395 ==============================================================
5033 23:03:10.677731 Enter into Gating configuration >>>>
5034 23:03:10.680934 Exit from Gating configuration <<<<
5035 23:03:10.684552 Enter into DVFS_PRE_config >>>>>
5036 23:03:10.693997 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5037 23:03:10.697342 Exit from DVFS_PRE_config <<<<<
5038 23:03:10.700713 Enter into PICG configuration >>>>
5039 23:03:10.704122 Exit from PICG configuration <<<<
5040 23:03:10.707483 [RX_INPUT] configuration >>>>>
5041 23:03:10.710550 [RX_INPUT] configuration <<<<<
5042 23:03:10.713842 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5043 23:03:10.720345 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5044 23:03:10.727201 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5045 23:03:10.730386 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5046 23:03:10.736966 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5047 23:03:10.743533 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5048 23:03:10.746878 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5049 23:03:10.750237 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5050 23:03:10.756632 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5051 23:03:10.760127 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5052 23:03:10.763200 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5053 23:03:10.770321 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5054 23:03:10.773601 ===================================
5055 23:03:10.773697 LPDDR4 DRAM CONFIGURATION
5056 23:03:10.776924 ===================================
5057 23:03:10.779950 EX_ROW_EN[0] = 0x0
5058 23:03:10.783196 EX_ROW_EN[1] = 0x0
5059 23:03:10.783269 LP4Y_EN = 0x0
5060 23:03:10.786530 WORK_FSP = 0x0
5061 23:03:10.786607 WL = 0x3
5062 23:03:10.789670 RL = 0x3
5063 23:03:10.789742 BL = 0x2
5064 23:03:10.793368 RPST = 0x0
5065 23:03:10.793445 RD_PRE = 0x0
5066 23:03:10.796683 WR_PRE = 0x1
5067 23:03:10.796762 WR_PST = 0x0
5068 23:03:10.799742 DBI_WR = 0x0
5069 23:03:10.799822 DBI_RD = 0x0
5070 23:03:10.803517 OTF = 0x1
5071 23:03:10.806587 ===================================
5072 23:03:10.809543 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5073 23:03:10.813468 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5074 23:03:10.819647 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5075 23:03:10.822977 ===================================
5076 23:03:10.823053 LPDDR4 DRAM CONFIGURATION
5077 23:03:10.826003 ===================================
5078 23:03:10.829313 EX_ROW_EN[0] = 0x10
5079 23:03:10.832900 EX_ROW_EN[1] = 0x0
5080 23:03:10.832976 LP4Y_EN = 0x0
5081 23:03:10.836362 WORK_FSP = 0x0
5082 23:03:10.836439 WL = 0x3
5083 23:03:10.839582 RL = 0x3
5084 23:03:10.839668 BL = 0x2
5085 23:03:10.842899 RPST = 0x0
5086 23:03:10.842981 RD_PRE = 0x0
5087 23:03:10.846065 WR_PRE = 0x1
5088 23:03:10.846147 WR_PST = 0x0
5089 23:03:10.849209 DBI_WR = 0x0
5090 23:03:10.849291 DBI_RD = 0x0
5091 23:03:10.852394 OTF = 0x1
5092 23:03:10.855598 ===================================
5093 23:03:10.862749 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5094 23:03:10.865625 nWR fixed to 30
5095 23:03:10.869527 [ModeRegInit_LP4] CH0 RK0
5096 23:03:10.869609 [ModeRegInit_LP4] CH0 RK1
5097 23:03:10.872369 [ModeRegInit_LP4] CH1 RK0
5098 23:03:10.875461 [ModeRegInit_LP4] CH1 RK1
5099 23:03:10.875542 match AC timing 9
5100 23:03:10.882274 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5101 23:03:10.885499 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5102 23:03:10.888860 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5103 23:03:10.895595 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5104 23:03:10.898819 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5105 23:03:10.898936 ==
5106 23:03:10.902143 Dram Type= 6, Freq= 0, CH_0, rank 0
5107 23:03:10.905587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5108 23:03:10.905671 ==
5109 23:03:10.912168 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5110 23:03:10.918872 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5111 23:03:10.921862 [CA 0] Center 38 (8~69) winsize 62
5112 23:03:10.925024 [CA 1] Center 38 (7~69) winsize 63
5113 23:03:10.928487 [CA 2] Center 35 (5~66) winsize 62
5114 23:03:10.932135 [CA 3] Center 35 (5~66) winsize 62
5115 23:03:10.935196 [CA 4] Center 34 (4~65) winsize 62
5116 23:03:10.938516 [CA 5] Center 33 (3~64) winsize 62
5117 23:03:10.938599
5118 23:03:10.941617 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5119 23:03:10.941700
5120 23:03:10.945078 [CATrainingPosCal] consider 1 rank data
5121 23:03:10.948714 u2DelayCellTimex100 = 270/100 ps
5122 23:03:10.951406 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5123 23:03:10.955048 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5124 23:03:10.958301 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5125 23:03:10.961494 CA3 delay=35 (5~66),Diff = 2 PI (12 cell)
5126 23:03:10.965119 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5127 23:03:10.971720 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5128 23:03:10.971802
5129 23:03:10.974721 CA PerBit enable=1, Macro0, CA PI delay=33
5130 23:03:10.974803
5131 23:03:10.978426 [CBTSetCACLKResult] CA Dly = 33
5132 23:03:10.978535 CS Dly: 7 (0~38)
5133 23:03:10.978628 ==
5134 23:03:10.981696 Dram Type= 6, Freq= 0, CH_0, rank 1
5135 23:03:10.984532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5136 23:03:10.988326 ==
5137 23:03:10.991153 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5138 23:03:10.998122 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5139 23:03:11.001286 [CA 0] Center 38 (8~69) winsize 62
5140 23:03:11.004435 [CA 1] Center 38 (8~69) winsize 62
5141 23:03:11.008055 [CA 2] Center 35 (5~66) winsize 62
5142 23:03:11.011039 [CA 3] Center 35 (5~66) winsize 62
5143 23:03:11.014351 [CA 4] Center 34 (4~65) winsize 62
5144 23:03:11.017673 [CA 5] Center 33 (3~64) winsize 62
5145 23:03:11.017756
5146 23:03:11.020789 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5147 23:03:11.020889
5148 23:03:11.023944 [CATrainingPosCal] consider 2 rank data
5149 23:03:11.027704 u2DelayCellTimex100 = 270/100 ps
5150 23:03:11.030968 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5151 23:03:11.033964 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5152 23:03:11.040619 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5153 23:03:11.044107 CA3 delay=35 (5~66),Diff = 2 PI (12 cell)
5154 23:03:11.047541 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5155 23:03:11.050481 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5156 23:03:11.050565
5157 23:03:11.053914 CA PerBit enable=1, Macro0, CA PI delay=33
5158 23:03:11.053998
5159 23:03:11.057119 [CBTSetCACLKResult] CA Dly = 33
5160 23:03:11.057281 CS Dly: 7 (0~38)
5161 23:03:11.060464
5162 23:03:11.063760 ----->DramcWriteLeveling(PI) begin...
5163 23:03:11.063844 ==
5164 23:03:11.067052 Dram Type= 6, Freq= 0, CH_0, rank 0
5165 23:03:11.070582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5166 23:03:11.070693 ==
5167 23:03:11.074024 Write leveling (Byte 0): 31 => 31
5168 23:03:11.077243 Write leveling (Byte 1): 33 => 33
5169 23:03:11.080340 DramcWriteLeveling(PI) end<-----
5170 23:03:11.080424
5171 23:03:11.080490 ==
5172 23:03:11.083678 Dram Type= 6, Freq= 0, CH_0, rank 0
5173 23:03:11.087156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5174 23:03:11.087233 ==
5175 23:03:11.090052 [Gating] SW mode calibration
5176 23:03:11.097016 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5177 23:03:11.103542 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5178 23:03:11.106949 0 14 0 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (1 1)
5179 23:03:11.110117 0 14 4 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
5180 23:03:11.116493 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5181 23:03:11.119815 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5182 23:03:11.123329 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5183 23:03:11.129690 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5184 23:03:11.133239 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5185 23:03:11.136557 0 14 28 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
5186 23:03:11.143302 0 15 0 | B1->B0 | 3434 2626 | 0 0 | (0 0) (0 0)
5187 23:03:11.146431 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
5188 23:03:11.150135 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5189 23:03:11.156152 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5190 23:03:11.159660 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5191 23:03:11.163395 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5192 23:03:11.169415 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5193 23:03:11.173008 0 15 28 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
5194 23:03:11.176182 1 0 0 | B1->B0 | 2f2f 3b3b | 0 0 | (0 0) (0 0)
5195 23:03:11.182686 1 0 4 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
5196 23:03:11.186103 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5197 23:03:11.189108 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5198 23:03:11.195959 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5199 23:03:11.199122 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5200 23:03:11.202428 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5201 23:03:11.209324 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5202 23:03:11.212934 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5203 23:03:11.216115 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5204 23:03:11.222386 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5205 23:03:11.225867 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5206 23:03:11.229410 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5207 23:03:11.235712 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5208 23:03:11.239134 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5209 23:03:11.242490 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5210 23:03:11.248760 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5211 23:03:11.252262 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5212 23:03:11.255327 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5213 23:03:11.261998 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5214 23:03:11.265244 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5215 23:03:11.268410 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5216 23:03:11.274997 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5217 23:03:11.278501 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5218 23:03:11.281946 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5219 23:03:11.288496 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5220 23:03:11.288610 Total UI for P1: 0, mck2ui 16
5221 23:03:11.295438 best dqsien dly found for B0: ( 1, 2, 30)
5222 23:03:11.295547 Total UI for P1: 0, mck2ui 16
5223 23:03:11.298644 best dqsien dly found for B1: ( 1, 3, 2)
5224 23:03:11.305327 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5225 23:03:11.308150 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5226 23:03:11.308254
5227 23:03:11.311744 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5228 23:03:11.314874 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5229 23:03:11.318200 [Gating] SW calibration Done
5230 23:03:11.318282 ==
5231 23:03:11.321519 Dram Type= 6, Freq= 0, CH_0, rank 0
5232 23:03:11.324932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5233 23:03:11.325014 ==
5234 23:03:11.328396 RX Vref Scan: 0
5235 23:03:11.328477
5236 23:03:11.328540 RX Vref 0 -> 0, step: 1
5237 23:03:11.328599
5238 23:03:11.331419 RX Delay -80 -> 252, step: 8
5239 23:03:11.334721 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5240 23:03:11.338320 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5241 23:03:11.344542 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5242 23:03:11.347708 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5243 23:03:11.351015 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5244 23:03:11.354506 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5245 23:03:11.357882 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5246 23:03:11.364655 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5247 23:03:11.367935 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5248 23:03:11.371096 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5249 23:03:11.374384 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5250 23:03:11.377833 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5251 23:03:11.384189 iDelay=208, Bit 12, Center 87 (-16 ~ 191) 208
5252 23:03:11.387770 iDelay=208, Bit 13, Center 87 (-16 ~ 191) 208
5253 23:03:11.390995 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5254 23:03:11.394125 iDelay=208, Bit 15, Center 87 (-16 ~ 191) 208
5255 23:03:11.394199 ==
5256 23:03:11.397777 Dram Type= 6, Freq= 0, CH_0, rank 0
5257 23:03:11.404013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5258 23:03:11.404089 ==
5259 23:03:11.404152 DQS Delay:
5260 23:03:11.407687 DQS0 = 0, DQS1 = 0
5261 23:03:11.407758 DQM Delay:
5262 23:03:11.407818 DQM0 = 94, DQM1 = 82
5263 23:03:11.410874 DQ Delay:
5264 23:03:11.413944 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5265 23:03:11.417148 DQ4 =95, DQ5 =79, DQ6 =103, DQ7 =107
5266 23:03:11.420397 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =79
5267 23:03:11.423772 DQ12 =87, DQ13 =87, DQ14 =91, DQ15 =87
5268 23:03:11.423853
5269 23:03:11.423918
5270 23:03:11.423977 ==
5271 23:03:11.426914 Dram Type= 6, Freq= 0, CH_0, rank 0
5272 23:03:11.430566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5273 23:03:11.430677 ==
5274 23:03:11.430795
5275 23:03:11.430860
5276 23:03:11.434112 TX Vref Scan disable
5277 23:03:11.437139 == TX Byte 0 ==
5278 23:03:11.440491 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5279 23:03:11.443689 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5280 23:03:11.447168 == TX Byte 1 ==
5281 23:03:11.450254 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5282 23:03:11.453661 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5283 23:03:11.453743 ==
5284 23:03:11.456967 Dram Type= 6, Freq= 0, CH_0, rank 0
5285 23:03:11.460534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5286 23:03:11.460617 ==
5287 23:03:11.463419
5288 23:03:11.463501
5289 23:03:11.463566 TX Vref Scan disable
5290 23:03:11.467524 == TX Byte 0 ==
5291 23:03:11.470326 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5292 23:03:11.476675 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5293 23:03:11.476775 == TX Byte 1 ==
5294 23:03:11.480161 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5295 23:03:11.486604 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5296 23:03:11.486700
5297 23:03:11.486820 [DATLAT]
5298 23:03:11.486941 Freq=933, CH0 RK0
5299 23:03:11.487003
5300 23:03:11.490115 DATLAT Default: 0xd
5301 23:03:11.490234 0, 0xFFFF, sum = 0
5302 23:03:11.493401 1, 0xFFFF, sum = 0
5303 23:03:11.493494 2, 0xFFFF, sum = 0
5304 23:03:11.496768 3, 0xFFFF, sum = 0
5305 23:03:11.500483 4, 0xFFFF, sum = 0
5306 23:03:11.500565 5, 0xFFFF, sum = 0
5307 23:03:11.503514 6, 0xFFFF, sum = 0
5308 23:03:11.503595 7, 0xFFFF, sum = 0
5309 23:03:11.507021 8, 0xFFFF, sum = 0
5310 23:03:11.507108 9, 0xFFFF, sum = 0
5311 23:03:11.509908 10, 0x0, sum = 1
5312 23:03:11.510007 11, 0x0, sum = 2
5313 23:03:11.513399 12, 0x0, sum = 3
5314 23:03:11.513473 13, 0x0, sum = 4
5315 23:03:11.513598 best_step = 11
5316 23:03:11.513688
5317 23:03:11.516765 ==
5318 23:03:11.519940 Dram Type= 6, Freq= 0, CH_0, rank 0
5319 23:03:11.523515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5320 23:03:11.523624 ==
5321 23:03:11.523700 RX Vref Scan: 1
5322 23:03:11.523788
5323 23:03:11.526297 RX Vref 0 -> 0, step: 1
5324 23:03:11.526369
5325 23:03:11.529896 RX Delay -69 -> 252, step: 4
5326 23:03:11.529995
5327 23:03:11.533557 Set Vref, RX VrefLevel [Byte0]: 60
5328 23:03:11.536290 [Byte1]: 57
5329 23:03:11.536364
5330 23:03:11.539930 Final RX Vref Byte 0 = 60 to rank0
5331 23:03:11.542980 Final RX Vref Byte 1 = 57 to rank0
5332 23:03:11.546349 Final RX Vref Byte 0 = 60 to rank1
5333 23:03:11.549522 Final RX Vref Byte 1 = 57 to rank1==
5334 23:03:11.552783 Dram Type= 6, Freq= 0, CH_0, rank 0
5335 23:03:11.559622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5336 23:03:11.559732 ==
5337 23:03:11.559828 DQS Delay:
5338 23:03:11.559920 DQS0 = 0, DQS1 = 0
5339 23:03:11.563162 DQM Delay:
5340 23:03:11.563266 DQM0 = 95, DQM1 = 84
5341 23:03:11.566371 DQ Delay:
5342 23:03:11.569720 DQ0 =94, DQ1 =94, DQ2 =92, DQ3 =92
5343 23:03:11.572695 DQ4 =96, DQ5 =86, DQ6 =104, DQ7 =106
5344 23:03:11.576336 DQ8 =78, DQ9 =72, DQ10 =84, DQ11 =80
5345 23:03:11.579617 DQ12 =90, DQ13 =88, DQ14 =94, DQ15 =90
5346 23:03:11.579746
5347 23:03:11.579835
5348 23:03:11.585951 [DQSOSCAuto] RK0, (LSB)MR18= 0x1211, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 416 ps
5349 23:03:11.589134 CH0 RK0: MR19=505, MR18=1211
5350 23:03:11.596077 CH0_RK0: MR19=0x505, MR18=0x1211, DQSOSC=416, MR23=63, INC=62, DEC=41
5351 23:03:11.596188
5352 23:03:11.599403 ----->DramcWriteLeveling(PI) begin...
5353 23:03:11.599502 ==
5354 23:03:11.602747 Dram Type= 6, Freq= 0, CH_0, rank 1
5355 23:03:11.605908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5356 23:03:11.606040 ==
5357 23:03:11.609416 Write leveling (Byte 0): 31 => 31
5358 23:03:11.612653 Write leveling (Byte 1): 31 => 31
5359 23:03:11.616000 DramcWriteLeveling(PI) end<-----
5360 23:03:11.616074
5361 23:03:11.616135 ==
5362 23:03:11.619492 Dram Type= 6, Freq= 0, CH_0, rank 1
5363 23:03:11.622342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5364 23:03:11.622443 ==
5365 23:03:11.625906 [Gating] SW mode calibration
5366 23:03:11.632343 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5367 23:03:11.639466 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5368 23:03:11.642472 0 14 0 | B1->B0 | 2c2c 3434 | 1 1 | (1 1) (1 1)
5369 23:03:11.649054 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5370 23:03:11.652349 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5371 23:03:11.655855 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5372 23:03:11.662344 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5373 23:03:11.665490 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5374 23:03:11.669089 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5375 23:03:11.672410 0 14 28 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0)
5376 23:03:11.678924 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
5377 23:03:11.682522 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5378 23:03:11.685444 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5379 23:03:11.692424 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5380 23:03:11.695677 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5381 23:03:11.699098 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5382 23:03:11.705351 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5383 23:03:11.708895 0 15 28 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
5384 23:03:11.712530 1 0 0 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
5385 23:03:11.718690 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5386 23:03:11.721921 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5387 23:03:11.725590 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5388 23:03:11.732352 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5389 23:03:11.735479 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5390 23:03:11.738674 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5391 23:03:11.745029 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5392 23:03:11.748624 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5393 23:03:11.752225 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 23:03:11.758464 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 23:03:11.761951 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 23:03:11.765127 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5397 23:03:11.771760 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5398 23:03:11.775024 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5399 23:03:11.778248 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5400 23:03:11.785428 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5401 23:03:11.788206 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5402 23:03:11.791477 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5403 23:03:11.798298 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5404 23:03:11.801845 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5405 23:03:11.805087 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5406 23:03:11.811560 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5407 23:03:11.814852 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5408 23:03:11.818284 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5409 23:03:11.821762 Total UI for P1: 0, mck2ui 16
5410 23:03:11.824876 best dqsien dly found for B0: ( 1, 2, 28)
5411 23:03:11.828409 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5412 23:03:11.831416 Total UI for P1: 0, mck2ui 16
5413 23:03:11.834814 best dqsien dly found for B1: ( 1, 3, 0)
5414 23:03:11.841666 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5415 23:03:11.844819 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5416 23:03:11.844928
5417 23:03:11.848619 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5418 23:03:11.851128 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5419 23:03:11.854551 [Gating] SW calibration Done
5420 23:03:11.854650 ==
5421 23:03:11.858178 Dram Type= 6, Freq= 0, CH_0, rank 1
5422 23:03:11.861371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5423 23:03:11.861453 ==
5424 23:03:11.861522 RX Vref Scan: 0
5425 23:03:11.864523
5426 23:03:11.864604 RX Vref 0 -> 0, step: 1
5427 23:03:11.864668
5428 23:03:11.868025 RX Delay -80 -> 252, step: 8
5429 23:03:11.871318 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5430 23:03:11.875000 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5431 23:03:11.881704 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5432 23:03:11.884416 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5433 23:03:11.887990 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5434 23:03:11.891340 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5435 23:03:11.894582 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5436 23:03:11.901348 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5437 23:03:11.904478 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5438 23:03:11.907690 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5439 23:03:11.911271 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5440 23:03:11.914520 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5441 23:03:11.921029 iDelay=208, Bit 12, Center 87 (-16 ~ 191) 208
5442 23:03:11.924809 iDelay=208, Bit 13, Center 87 (-16 ~ 191) 208
5443 23:03:11.927660 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5444 23:03:11.930969 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5445 23:03:11.931050 ==
5446 23:03:11.934397 Dram Type= 6, Freq= 0, CH_0, rank 1
5447 23:03:11.938086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5448 23:03:11.941491 ==
5449 23:03:11.941572 DQS Delay:
5450 23:03:11.941636 DQS0 = 0, DQS1 = 0
5451 23:03:11.944580 DQM Delay:
5452 23:03:11.944661 DQM0 = 91, DQM1 = 82
5453 23:03:11.947956 DQ Delay:
5454 23:03:11.948036 DQ0 =91, DQ1 =91, DQ2 =87, DQ3 =87
5455 23:03:11.950873 DQ4 =91, DQ5 =79, DQ6 =103, DQ7 =103
5456 23:03:11.954681 DQ8 =75, DQ9 =67, DQ10 =83, DQ11 =75
5457 23:03:11.960702 DQ12 =87, DQ13 =87, DQ14 =91, DQ15 =91
5458 23:03:11.960786
5459 23:03:11.960850
5460 23:03:11.960911 ==
5461 23:03:11.964483 Dram Type= 6, Freq= 0, CH_0, rank 1
5462 23:03:11.967503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5463 23:03:11.967586 ==
5464 23:03:11.967651
5465 23:03:11.967710
5466 23:03:11.971000 TX Vref Scan disable
5467 23:03:11.971098 == TX Byte 0 ==
5468 23:03:11.977798 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5469 23:03:11.981233 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5470 23:03:11.981329 == TX Byte 1 ==
5471 23:03:11.987558 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5472 23:03:11.991035 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5473 23:03:11.991184 ==
5474 23:03:11.994004 Dram Type= 6, Freq= 0, CH_0, rank 1
5475 23:03:11.997210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5476 23:03:11.997339 ==
5477 23:03:11.997404
5478 23:03:11.997464
5479 23:03:12.000857 TX Vref Scan disable
5480 23:03:12.003765 == TX Byte 0 ==
5481 23:03:12.007398 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5482 23:03:12.010497 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5483 23:03:12.014206 == TX Byte 1 ==
5484 23:03:12.017677 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5485 23:03:12.020883 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5486 23:03:12.020961
5487 23:03:12.023980 [DATLAT]
5488 23:03:12.024053 Freq=933, CH0 RK1
5489 23:03:12.024130
5490 23:03:12.027086 DATLAT Default: 0xb
5491 23:03:12.027217 0, 0xFFFF, sum = 0
5492 23:03:12.030845 1, 0xFFFF, sum = 0
5493 23:03:12.030944 2, 0xFFFF, sum = 0
5494 23:03:12.033830 3, 0xFFFF, sum = 0
5495 23:03:12.033915 4, 0xFFFF, sum = 0
5496 23:03:12.037197 5, 0xFFFF, sum = 0
5497 23:03:12.037312 6, 0xFFFF, sum = 0
5498 23:03:12.040835 7, 0xFFFF, sum = 0
5499 23:03:12.040944 8, 0xFFFF, sum = 0
5500 23:03:12.043999 9, 0xFFFF, sum = 0
5501 23:03:12.044115 10, 0x0, sum = 1
5502 23:03:12.047293 11, 0x0, sum = 2
5503 23:03:12.047386 12, 0x0, sum = 3
5504 23:03:12.051037 13, 0x0, sum = 4
5505 23:03:12.051154 best_step = 11
5506 23:03:12.051257
5507 23:03:12.051348 ==
5508 23:03:12.053739 Dram Type= 6, Freq= 0, CH_0, rank 1
5509 23:03:12.060798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5510 23:03:12.060893 ==
5511 23:03:12.060959 RX Vref Scan: 0
5512 23:03:12.061040
5513 23:03:12.064051 RX Vref 0 -> 0, step: 1
5514 23:03:12.064134
5515 23:03:12.067447 RX Delay -77 -> 252, step: 4
5516 23:03:12.070599 iDelay=199, Bit 0, Center 90 (-5 ~ 186) 192
5517 23:03:12.073784 iDelay=199, Bit 1, Center 92 (-1 ~ 186) 188
5518 23:03:12.080503 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5519 23:03:12.083401 iDelay=199, Bit 3, Center 88 (-9 ~ 186) 196
5520 23:03:12.086876 iDelay=199, Bit 4, Center 90 (-5 ~ 186) 192
5521 23:03:12.090024 iDelay=199, Bit 5, Center 80 (-13 ~ 174) 188
5522 23:03:12.093648 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5523 23:03:12.100180 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5524 23:03:12.103423 iDelay=199, Bit 8, Center 78 (-13 ~ 170) 184
5525 23:03:12.107070 iDelay=199, Bit 9, Center 72 (-17 ~ 162) 180
5526 23:03:12.109935 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5527 23:03:12.113171 iDelay=199, Bit 11, Center 80 (-9 ~ 170) 180
5528 23:03:12.119990 iDelay=199, Bit 12, Center 88 (-5 ~ 182) 188
5529 23:03:12.123579 iDelay=199, Bit 13, Center 88 (-5 ~ 182) 188
5530 23:03:12.126629 iDelay=199, Bit 14, Center 92 (-1 ~ 186) 188
5531 23:03:12.129734 iDelay=199, Bit 15, Center 92 (-1 ~ 186) 188
5532 23:03:12.129818 ==
5533 23:03:12.133505 Dram Type= 6, Freq= 0, CH_0, rank 1
5534 23:03:12.140124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5535 23:03:12.140240 ==
5536 23:03:12.140308 DQS Delay:
5537 23:03:12.140369 DQS0 = 0, DQS1 = 0
5538 23:03:12.143225 DQM Delay:
5539 23:03:12.143333 DQM0 = 91, DQM1 = 84
5540 23:03:12.146343 DQ Delay:
5541 23:03:12.150088 DQ0 =90, DQ1 =92, DQ2 =88, DQ3 =88
5542 23:03:12.152947 DQ4 =90, DQ5 =80, DQ6 =104, DQ7 =102
5543 23:03:12.156373 DQ8 =78, DQ9 =72, DQ10 =86, DQ11 =80
5544 23:03:12.159474 DQ12 =88, DQ13 =88, DQ14 =92, DQ15 =92
5545 23:03:12.159552
5546 23:03:12.159616
5547 23:03:12.166477 [DQSOSCAuto] RK1, (LSB)MR18= 0x3012, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 406 ps
5548 23:03:12.169602 CH0 RK1: MR19=505, MR18=3012
5549 23:03:12.176567 CH0_RK1: MR19=0x505, MR18=0x3012, DQSOSC=406, MR23=63, INC=65, DEC=43
5550 23:03:12.179380 [RxdqsGatingPostProcess] freq 933
5551 23:03:12.182891 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5552 23:03:12.186302 best DQS0 dly(2T, 0.5T) = (0, 10)
5553 23:03:12.189488 best DQS1 dly(2T, 0.5T) = (0, 11)
5554 23:03:12.192532 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5555 23:03:12.196194 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5556 23:03:12.199525 best DQS0 dly(2T, 0.5T) = (0, 10)
5557 23:03:12.202924 best DQS1 dly(2T, 0.5T) = (0, 11)
5558 23:03:12.206342 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5559 23:03:12.209516 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5560 23:03:12.212828 Pre-setting of DQS Precalculation
5561 23:03:12.215839 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5562 23:03:12.215926 ==
5563 23:03:12.219414 Dram Type= 6, Freq= 0, CH_1, rank 0
5564 23:03:12.225922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5565 23:03:12.226006 ==
5566 23:03:12.229208 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5567 23:03:12.236039 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5568 23:03:12.238923 [CA 0] Center 37 (7~67) winsize 61
5569 23:03:12.242239 [CA 1] Center 37 (7~68) winsize 62
5570 23:03:12.245532 [CA 2] Center 34 (5~64) winsize 60
5571 23:03:12.248975 [CA 3] Center 34 (4~64) winsize 61
5572 23:03:12.252683 [CA 4] Center 34 (5~64) winsize 60
5573 23:03:12.255848 [CA 5] Center 34 (4~64) winsize 61
5574 23:03:12.255966
5575 23:03:12.259179 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5576 23:03:12.259268
5577 23:03:12.262297 [CATrainingPosCal] consider 1 rank data
5578 23:03:12.265346 u2DelayCellTimex100 = 270/100 ps
5579 23:03:12.268628 CA0 delay=37 (7~67),Diff = 3 PI (18 cell)
5580 23:03:12.275462 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5581 23:03:12.279005 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5582 23:03:12.282421 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
5583 23:03:12.285603 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5584 23:03:12.289118 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5585 23:03:12.289193
5586 23:03:12.292220 CA PerBit enable=1, Macro0, CA PI delay=34
5587 23:03:12.292309
5588 23:03:12.295186 [CBTSetCACLKResult] CA Dly = 34
5589 23:03:12.295358 CS Dly: 6 (0~37)
5590 23:03:12.298457 ==
5591 23:03:12.302037 Dram Type= 6, Freq= 0, CH_1, rank 1
5592 23:03:12.305406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5593 23:03:12.305489 ==
5594 23:03:12.308386 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5595 23:03:12.315344 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5596 23:03:12.319230 [CA 0] Center 37 (7~68) winsize 62
5597 23:03:12.322365 [CA 1] Center 37 (7~68) winsize 62
5598 23:03:12.325683 [CA 2] Center 35 (5~65) winsize 61
5599 23:03:12.329159 [CA 3] Center 34 (4~64) winsize 61
5600 23:03:12.332097 [CA 4] Center 35 (5~65) winsize 61
5601 23:03:12.335548 [CA 5] Center 34 (4~64) winsize 61
5602 23:03:12.335630
5603 23:03:12.338982 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5604 23:03:12.339065
5605 23:03:12.342516 [CATrainingPosCal] consider 2 rank data
5606 23:03:12.345579 u2DelayCellTimex100 = 270/100 ps
5607 23:03:12.348861 CA0 delay=37 (7~67),Diff = 3 PI (18 cell)
5608 23:03:12.355326 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5609 23:03:12.358612 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5610 23:03:12.362188 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
5611 23:03:12.365455 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5612 23:03:12.368658 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5613 23:03:12.368764
5614 23:03:12.371843 CA PerBit enable=1, Macro0, CA PI delay=34
5615 23:03:12.371949
5616 23:03:12.375222 [CBTSetCACLKResult] CA Dly = 34
5617 23:03:12.378496 CS Dly: 7 (0~39)
5618 23:03:12.378583
5619 23:03:12.382197 ----->DramcWriteLeveling(PI) begin...
5620 23:03:12.382283 ==
5621 23:03:12.385196 Dram Type= 6, Freq= 0, CH_1, rank 0
5622 23:03:12.388447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5623 23:03:12.388531 ==
5624 23:03:12.392272 Write leveling (Byte 0): 24 => 24
5625 23:03:12.394914 Write leveling (Byte 1): 29 => 29
5626 23:03:12.398324 DramcWriteLeveling(PI) end<-----
5627 23:03:12.398407
5628 23:03:12.398524 ==
5629 23:03:12.401873 Dram Type= 6, Freq= 0, CH_1, rank 0
5630 23:03:12.405099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5631 23:03:12.405184 ==
5632 23:03:12.408330 [Gating] SW mode calibration
5633 23:03:12.414959 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5634 23:03:12.421557 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5635 23:03:12.425085 0 14 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5636 23:03:12.428519 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5637 23:03:12.434880 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5638 23:03:12.438615 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5639 23:03:12.441657 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5640 23:03:12.448015 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5641 23:03:12.451583 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5642 23:03:12.454703 0 14 28 | B1->B0 | 3030 3030 | 0 0 | (1 1) (0 1)
5643 23:03:12.461578 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5644 23:03:12.464666 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5645 23:03:12.467759 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5646 23:03:12.474748 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5647 23:03:12.477627 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5648 23:03:12.481000 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5649 23:03:12.487657 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5650 23:03:12.491516 0 15 28 | B1->B0 | 3737 3838 | 1 0 | (0 0) (0 0)
5651 23:03:12.494733 1 0 0 | B1->B0 | 4040 4242 | 0 0 | (0 0) (0 0)
5652 23:03:12.500817 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5653 23:03:12.504550 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5654 23:03:12.507943 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5655 23:03:12.514172 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5656 23:03:12.517408 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5657 23:03:12.521168 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5658 23:03:12.527672 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5659 23:03:12.530768 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5660 23:03:12.534528 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5661 23:03:12.537822 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5662 23:03:12.544566 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5663 23:03:12.548025 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5664 23:03:12.550629 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5665 23:03:12.557567 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5666 23:03:12.561138 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5667 23:03:12.563794 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5668 23:03:12.571005 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5669 23:03:12.573765 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5670 23:03:12.577168 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5671 23:03:12.583667 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5672 23:03:12.587311 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5673 23:03:12.590504 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5674 23:03:12.597042 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5675 23:03:12.600187 Total UI for P1: 0, mck2ui 16
5676 23:03:12.604222 best dqsien dly found for B1: ( 1, 2, 26)
5677 23:03:12.607286 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5678 23:03:12.610702 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5679 23:03:12.613872 Total UI for P1: 0, mck2ui 16
5680 23:03:12.616705 best dqsien dly found for B0: ( 1, 2, 30)
5681 23:03:12.620333 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5682 23:03:12.623805 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5683 23:03:12.626855
5684 23:03:12.630298 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5685 23:03:12.633305 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5686 23:03:12.636698 [Gating] SW calibration Done
5687 23:03:12.636779 ==
5688 23:03:12.639844 Dram Type= 6, Freq= 0, CH_1, rank 0
5689 23:03:12.643507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5690 23:03:12.643616 ==
5691 23:03:12.643688 RX Vref Scan: 0
5692 23:03:12.646561
5693 23:03:12.646642 RX Vref 0 -> 0, step: 1
5694 23:03:12.646707
5695 23:03:12.649770 RX Delay -80 -> 252, step: 8
5696 23:03:12.653048 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5697 23:03:12.656911 iDelay=208, Bit 1, Center 87 (-16 ~ 191) 208
5698 23:03:12.662912 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5699 23:03:12.666383 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5700 23:03:12.669898 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5701 23:03:12.672751 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5702 23:03:12.676349 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5703 23:03:12.683449 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5704 23:03:12.686244 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5705 23:03:12.689701 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5706 23:03:12.692992 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5707 23:03:12.696372 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5708 23:03:12.699414 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5709 23:03:12.706489 iDelay=208, Bit 13, Center 95 (-8 ~ 199) 208
5710 23:03:12.709819 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5711 23:03:12.713176 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5712 23:03:12.713258 ==
5713 23:03:12.716443 Dram Type= 6, Freq= 0, CH_1, rank 0
5714 23:03:12.719425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5715 23:03:12.722888 ==
5716 23:03:12.722969 DQS Delay:
5717 23:03:12.723034 DQS0 = 0, DQS1 = 0
5718 23:03:12.726004 DQM Delay:
5719 23:03:12.726113 DQM0 = 93, DQM1 = 86
5720 23:03:12.726211 DQ Delay:
5721 23:03:12.729360 DQ0 =99, DQ1 =87, DQ2 =83, DQ3 =91
5722 23:03:12.732865 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5723 23:03:12.736502 DQ8 =75, DQ9 =79, DQ10 =87, DQ11 =83
5724 23:03:12.739627 DQ12 =91, DQ13 =95, DQ14 =91, DQ15 =91
5725 23:03:12.742844
5726 23:03:12.742924
5727 23:03:12.742987 ==
5728 23:03:12.746563 Dram Type= 6, Freq= 0, CH_1, rank 0
5729 23:03:12.749206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5730 23:03:12.749288 ==
5731 23:03:12.749352
5732 23:03:12.749410
5733 23:03:12.752805 TX Vref Scan disable
5734 23:03:12.752885 == TX Byte 0 ==
5735 23:03:12.759556 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5736 23:03:12.762428 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5737 23:03:12.762542 == TX Byte 1 ==
5738 23:03:12.769314 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5739 23:03:12.772350 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5740 23:03:12.772450 ==
5741 23:03:12.775522 Dram Type= 6, Freq= 0, CH_1, rank 0
5742 23:03:12.779068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5743 23:03:12.779170 ==
5744 23:03:12.779262
5745 23:03:12.779359
5746 23:03:12.782388 TX Vref Scan disable
5747 23:03:12.785465 == TX Byte 0 ==
5748 23:03:12.789038 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5749 23:03:12.792341 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5750 23:03:12.795466 == TX Byte 1 ==
5751 23:03:12.799037 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5752 23:03:12.801997 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5753 23:03:12.802103
5754 23:03:12.805501 [DATLAT]
5755 23:03:12.805607 Freq=933, CH1 RK0
5756 23:03:12.805704
5757 23:03:12.808767 DATLAT Default: 0xd
5758 23:03:12.808848 0, 0xFFFF, sum = 0
5759 23:03:12.812020 1, 0xFFFF, sum = 0
5760 23:03:12.812135 2, 0xFFFF, sum = 0
5761 23:03:12.815414 3, 0xFFFF, sum = 0
5762 23:03:12.815525 4, 0xFFFF, sum = 0
5763 23:03:12.819010 5, 0xFFFF, sum = 0
5764 23:03:12.819093 6, 0xFFFF, sum = 0
5765 23:03:12.822237 7, 0xFFFF, sum = 0
5766 23:03:12.822320 8, 0xFFFF, sum = 0
5767 23:03:12.825468 9, 0xFFFF, sum = 0
5768 23:03:12.825551 10, 0x0, sum = 1
5769 23:03:12.828566 11, 0x0, sum = 2
5770 23:03:12.828648 12, 0x0, sum = 3
5771 23:03:12.832373 13, 0x0, sum = 4
5772 23:03:12.832482 best_step = 11
5773 23:03:12.832573
5774 23:03:12.832661 ==
5775 23:03:12.835167 Dram Type= 6, Freq= 0, CH_1, rank 0
5776 23:03:12.842194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5777 23:03:12.842276 ==
5778 23:03:12.842341 RX Vref Scan: 1
5779 23:03:12.842401
5780 23:03:12.845366 RX Vref 0 -> 0, step: 1
5781 23:03:12.845472
5782 23:03:12.848480 RX Delay -69 -> 252, step: 4
5783 23:03:12.848561
5784 23:03:12.851902 Set Vref, RX VrefLevel [Byte0]: 56
5785 23:03:12.855349 [Byte1]: 56
5786 23:03:12.855430
5787 23:03:12.858504 Final RX Vref Byte 0 = 56 to rank0
5788 23:03:12.861733 Final RX Vref Byte 1 = 56 to rank0
5789 23:03:12.865135 Final RX Vref Byte 0 = 56 to rank1
5790 23:03:12.868498 Final RX Vref Byte 1 = 56 to rank1==
5791 23:03:12.871974 Dram Type= 6, Freq= 0, CH_1, rank 0
5792 23:03:12.875246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5793 23:03:12.875356 ==
5794 23:03:12.878687 DQS Delay:
5795 23:03:12.878793 DQS0 = 0, DQS1 = 0
5796 23:03:12.881426 DQM Delay:
5797 23:03:12.881507 DQM0 = 96, DQM1 = 89
5798 23:03:12.881571 DQ Delay:
5799 23:03:12.885055 DQ0 =102, DQ1 =92, DQ2 =84, DQ3 =94
5800 23:03:12.888505 DQ4 =92, DQ5 =106, DQ6 =108, DQ7 =94
5801 23:03:12.891393 DQ8 =76, DQ9 =80, DQ10 =88, DQ11 =82
5802 23:03:12.894965 DQ12 =100, DQ13 =94, DQ14 =98, DQ15 =94
5803 23:03:12.898025
5804 23:03:12.898109
5805 23:03:12.904780 [DQSOSCAuto] RK0, (LSB)MR18= 0x40c, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 420 ps
5806 23:03:12.908174 CH1 RK0: MR19=505, MR18=40C
5807 23:03:12.914687 CH1_RK0: MR19=0x505, MR18=0x40C, DQSOSC=418, MR23=63, INC=62, DEC=41
5808 23:03:12.914770
5809 23:03:12.918322 ----->DramcWriteLeveling(PI) begin...
5810 23:03:12.918405 ==
5811 23:03:12.921529 Dram Type= 6, Freq= 0, CH_1, rank 1
5812 23:03:12.924975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5813 23:03:12.925073 ==
5814 23:03:12.927850 Write leveling (Byte 0): 25 => 25
5815 23:03:12.931222 Write leveling (Byte 1): 28 => 28
5816 23:03:12.934804 DramcWriteLeveling(PI) end<-----
5817 23:03:12.934885
5818 23:03:12.934948 ==
5819 23:03:12.938096 Dram Type= 6, Freq= 0, CH_1, rank 1
5820 23:03:12.941416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5821 23:03:12.941497 ==
5822 23:03:12.944716 [Gating] SW mode calibration
5823 23:03:12.951463 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5824 23:03:12.958123 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5825 23:03:12.961225 0 14 0 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
5826 23:03:12.964408 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5827 23:03:12.971029 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5828 23:03:12.974245 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5829 23:03:12.978007 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5830 23:03:12.984502 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5831 23:03:12.987808 0 14 24 | B1->B0 | 3232 2f2f | 0 1 | (0 0) (1 0)
5832 23:03:12.991135 0 14 28 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
5833 23:03:12.997566 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5834 23:03:13.000688 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5835 23:03:13.004321 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5836 23:03:13.010820 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5837 23:03:13.013994 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5838 23:03:13.017148 0 15 20 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
5839 23:03:13.023778 0 15 24 | B1->B0 | 2323 3030 | 0 1 | (0 0) (0 0)
5840 23:03:13.027610 0 15 28 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
5841 23:03:13.030518 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5842 23:03:13.037082 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5843 23:03:13.040602 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5844 23:03:13.044135 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5845 23:03:13.050619 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5846 23:03:13.053885 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5847 23:03:13.057209 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5848 23:03:13.063424 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5849 23:03:13.066743 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5850 23:03:13.070073 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5851 23:03:13.076957 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5852 23:03:13.079988 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5853 23:03:13.083453 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5854 23:03:13.090167 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5855 23:03:13.093400 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5856 23:03:13.096444 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5857 23:03:13.102995 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5858 23:03:13.106388 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5859 23:03:13.109526 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5860 23:03:13.116067 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5861 23:03:13.119628 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5862 23:03:13.122621 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5863 23:03:13.129552 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5864 23:03:13.132673 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5865 23:03:13.135837 Total UI for P1: 0, mck2ui 16
5866 23:03:13.139306 best dqsien dly found for B0: ( 1, 2, 24)
5867 23:03:13.142552 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5868 23:03:13.145954 Total UI for P1: 0, mck2ui 16
5869 23:03:13.149430 best dqsien dly found for B1: ( 1, 2, 28)
5870 23:03:13.152733 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5871 23:03:13.156011 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5872 23:03:13.156124
5873 23:03:13.162261 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5874 23:03:13.165664 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5875 23:03:13.165774 [Gating] SW calibration Done
5876 23:03:13.169378 ==
5877 23:03:13.172400 Dram Type= 6, Freq= 0, CH_1, rank 1
5878 23:03:13.175862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5879 23:03:13.175976 ==
5880 23:03:13.176045 RX Vref Scan: 0
5881 23:03:13.176107
5882 23:03:13.178914 RX Vref 0 -> 0, step: 1
5883 23:03:13.178995
5884 23:03:13.182135 RX Delay -80 -> 252, step: 8
5885 23:03:13.185693 iDelay=208, Bit 0, Center 95 (-8 ~ 199) 208
5886 23:03:13.189034 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5887 23:03:13.195655 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5888 23:03:13.198896 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5889 23:03:13.202465 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5890 23:03:13.205493 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5891 23:03:13.208520 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5892 23:03:13.211891 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5893 23:03:13.218883 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5894 23:03:13.221907 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5895 23:03:13.225240 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5896 23:03:13.228316 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5897 23:03:13.231809 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5898 23:03:13.238326 iDelay=208, Bit 13, Center 95 (-8 ~ 199) 208
5899 23:03:13.241896 iDelay=208, Bit 14, Center 95 (-8 ~ 199) 208
5900 23:03:13.245001 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5901 23:03:13.245085 ==
5902 23:03:13.248301 Dram Type= 6, Freq= 0, CH_1, rank 1
5903 23:03:13.251968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5904 23:03:13.252079 ==
5905 23:03:13.255233 DQS Delay:
5906 23:03:13.255319 DQS0 = 0, DQS1 = 0
5907 23:03:13.255384 DQM Delay:
5908 23:03:13.258259 DQM0 = 93, DQM1 = 90
5909 23:03:13.258344 DQ Delay:
5910 23:03:13.261954 DQ0 =95, DQ1 =91, DQ2 =83, DQ3 =91
5911 23:03:13.264984 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5912 23:03:13.268317 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5913 23:03:13.272016 DQ12 =99, DQ13 =95, DQ14 =95, DQ15 =99
5914 23:03:13.272099
5915 23:03:13.272164
5916 23:03:13.272235 ==
5917 23:03:13.275578 Dram Type= 6, Freq= 0, CH_1, rank 1
5918 23:03:13.281562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5919 23:03:13.281645 ==
5920 23:03:13.281712
5921 23:03:13.281772
5922 23:03:13.284800 TX Vref Scan disable
5923 23:03:13.284882 == TX Byte 0 ==
5924 23:03:13.288191 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5925 23:03:13.295394 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5926 23:03:13.295478 == TX Byte 1 ==
5927 23:03:13.298199 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5928 23:03:13.305357 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5929 23:03:13.305439 ==
5930 23:03:13.308230 Dram Type= 6, Freq= 0, CH_1, rank 1
5931 23:03:13.311247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5932 23:03:13.311328 ==
5933 23:03:13.311391
5934 23:03:13.311451
5935 23:03:13.314455 TX Vref Scan disable
5936 23:03:13.317808 == TX Byte 0 ==
5937 23:03:13.321044 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5938 23:03:13.324890 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5939 23:03:13.327710 == TX Byte 1 ==
5940 23:03:13.330792 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5941 23:03:13.334448 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5942 23:03:13.334533
5943 23:03:13.337487 [DATLAT]
5944 23:03:13.337568 Freq=933, CH1 RK1
5945 23:03:13.337632
5946 23:03:13.341469 DATLAT Default: 0xb
5947 23:03:13.341549 0, 0xFFFF, sum = 0
5948 23:03:13.344298 1, 0xFFFF, sum = 0
5949 23:03:13.344380 2, 0xFFFF, sum = 0
5950 23:03:13.347599 3, 0xFFFF, sum = 0
5951 23:03:13.347681 4, 0xFFFF, sum = 0
5952 23:03:13.350947 5, 0xFFFF, sum = 0
5953 23:03:13.351030 6, 0xFFFF, sum = 0
5954 23:03:13.354235 7, 0xFFFF, sum = 0
5955 23:03:13.354317 8, 0xFFFF, sum = 0
5956 23:03:13.357893 9, 0xFFFF, sum = 0
5957 23:03:13.357975 10, 0x0, sum = 1
5958 23:03:13.360668 11, 0x0, sum = 2
5959 23:03:13.360751 12, 0x0, sum = 3
5960 23:03:13.364047 13, 0x0, sum = 4
5961 23:03:13.364130 best_step = 11
5962 23:03:13.364238
5963 23:03:13.364299 ==
5964 23:03:13.367484 Dram Type= 6, Freq= 0, CH_1, rank 1
5965 23:03:13.373941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5966 23:03:13.374024 ==
5967 23:03:13.374088 RX Vref Scan: 0
5968 23:03:13.374148
5969 23:03:13.377464 RX Vref 0 -> 0, step: 1
5970 23:03:13.377545
5971 23:03:13.380815 RX Delay -61 -> 252, step: 4
5972 23:03:13.384014 iDelay=203, Bit 0, Center 96 (-1 ~ 194) 196
5973 23:03:13.387202 iDelay=203, Bit 1, Center 86 (-9 ~ 182) 192
5974 23:03:13.394175 iDelay=203, Bit 2, Center 80 (-17 ~ 178) 196
5975 23:03:13.397208 iDelay=203, Bit 3, Center 88 (-9 ~ 186) 196
5976 23:03:13.400316 iDelay=203, Bit 4, Center 90 (-5 ~ 186) 192
5977 23:03:13.404066 iDelay=203, Bit 5, Center 102 (7 ~ 198) 192
5978 23:03:13.407273 iDelay=203, Bit 6, Center 104 (7 ~ 202) 196
5979 23:03:13.410603 iDelay=203, Bit 7, Center 88 (-9 ~ 186) 196
5980 23:03:13.416986 iDelay=203, Bit 8, Center 78 (-17 ~ 174) 192
5981 23:03:13.420192 iDelay=203, Bit 9, Center 80 (-13 ~ 174) 188
5982 23:03:13.423654 iDelay=203, Bit 10, Center 94 (-1 ~ 190) 192
5983 23:03:13.426780 iDelay=203, Bit 11, Center 82 (-13 ~ 178) 192
5984 23:03:13.433480 iDelay=203, Bit 12, Center 100 (7 ~ 194) 188
5985 23:03:13.436878 iDelay=203, Bit 13, Center 98 (7 ~ 190) 184
5986 23:03:13.440372 iDelay=203, Bit 14, Center 100 (7 ~ 194) 188
5987 23:03:13.443578 iDelay=203, Bit 15, Center 100 (7 ~ 194) 188
5988 23:03:13.443660 ==
5989 23:03:13.446982 Dram Type= 6, Freq= 0, CH_1, rank 1
5990 23:03:13.450212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5991 23:03:13.450294 ==
5992 23:03:13.453238 DQS Delay:
5993 23:03:13.453318 DQS0 = 0, DQS1 = 0
5994 23:03:13.456623 DQM Delay:
5995 23:03:13.456703 DQM0 = 91, DQM1 = 91
5996 23:03:13.456767 DQ Delay:
5997 23:03:13.459894 DQ0 =96, DQ1 =86, DQ2 =80, DQ3 =88
5998 23:03:13.463462 DQ4 =90, DQ5 =102, DQ6 =104, DQ7 =88
5999 23:03:13.466930 DQ8 =78, DQ9 =80, DQ10 =94, DQ11 =82
6000 23:03:13.473517 DQ12 =100, DQ13 =98, DQ14 =100, DQ15 =100
6001 23:03:13.473599
6002 23:03:13.473664
6003 23:03:13.480098 [DQSOSCAuto] RK1, (LSB)MR18= 0x1024, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 416 ps
6004 23:03:13.483256 CH1 RK1: MR19=505, MR18=1024
6005 23:03:13.490156 CH1_RK1: MR19=0x505, MR18=0x1024, DQSOSC=410, MR23=63, INC=64, DEC=42
6006 23:03:13.492931 [RxdqsGatingPostProcess] freq 933
6007 23:03:13.496650 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6008 23:03:13.500094 best DQS0 dly(2T, 0.5T) = (0, 10)
6009 23:03:13.502948 best DQS1 dly(2T, 0.5T) = (0, 10)
6010 23:03:13.506552 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6011 23:03:13.509657 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6012 23:03:13.513055 best DQS0 dly(2T, 0.5T) = (0, 10)
6013 23:03:13.516581 best DQS1 dly(2T, 0.5T) = (0, 10)
6014 23:03:13.519804 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6015 23:03:13.523083 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6016 23:03:13.526383 Pre-setting of DQS Precalculation
6017 23:03:13.529749 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6018 23:03:13.536593 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6019 23:03:13.546394 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6020 23:03:13.546476
6021 23:03:13.546540
6022 23:03:13.549730 [Calibration Summary] 1866 Mbps
6023 23:03:13.549813 CH 0, Rank 0
6024 23:03:13.552975 SW Impedance : PASS
6025 23:03:13.553057 DUTY Scan : NO K
6026 23:03:13.556612 ZQ Calibration : PASS
6027 23:03:13.559501 Jitter Meter : NO K
6028 23:03:13.559583 CBT Training : PASS
6029 23:03:13.563118 Write leveling : PASS
6030 23:03:13.566204 RX DQS gating : PASS
6031 23:03:13.566286 RX DQ/DQS(RDDQC) : PASS
6032 23:03:13.569901 TX DQ/DQS : PASS
6033 23:03:13.569983 RX DATLAT : PASS
6034 23:03:13.572683 RX DQ/DQS(Engine): PASS
6035 23:03:13.576370 TX OE : NO K
6036 23:03:13.576452 All Pass.
6037 23:03:13.576516
6038 23:03:13.576576 CH 0, Rank 1
6039 23:03:13.579347 SW Impedance : PASS
6040 23:03:13.583102 DUTY Scan : NO K
6041 23:03:13.583184 ZQ Calibration : PASS
6042 23:03:13.586188 Jitter Meter : NO K
6043 23:03:13.589399 CBT Training : PASS
6044 23:03:13.589555 Write leveling : PASS
6045 23:03:13.592588 RX DQS gating : PASS
6046 23:03:13.596111 RX DQ/DQS(RDDQC) : PASS
6047 23:03:13.596192 TX DQ/DQS : PASS
6048 23:03:13.599302 RX DATLAT : PASS
6049 23:03:13.602843 RX DQ/DQS(Engine): PASS
6050 23:03:13.602926 TX OE : NO K
6051 23:03:13.605992 All Pass.
6052 23:03:13.606074
6053 23:03:13.606139 CH 1, Rank 0
6054 23:03:13.609371 SW Impedance : PASS
6055 23:03:13.609453 DUTY Scan : NO K
6056 23:03:13.612707 ZQ Calibration : PASS
6057 23:03:13.615892 Jitter Meter : NO K
6058 23:03:13.615974 CBT Training : PASS
6059 23:03:13.619375 Write leveling : PASS
6060 23:03:13.619457 RX DQS gating : PASS
6061 23:03:13.622769 RX DQ/DQS(RDDQC) : PASS
6062 23:03:13.626157 TX DQ/DQS : PASS
6063 23:03:13.626240 RX DATLAT : PASS
6064 23:03:13.629332 RX DQ/DQS(Engine): PASS
6065 23:03:13.632421 TX OE : NO K
6066 23:03:13.632503 All Pass.
6067 23:03:13.632567
6068 23:03:13.632627 CH 1, Rank 1
6069 23:03:13.635778 SW Impedance : PASS
6070 23:03:13.639029 DUTY Scan : NO K
6071 23:03:13.639110 ZQ Calibration : PASS
6072 23:03:13.643098 Jitter Meter : NO K
6073 23:03:13.645923 CBT Training : PASS
6074 23:03:13.646005 Write leveling : PASS
6075 23:03:13.649138 RX DQS gating : PASS
6076 23:03:13.652353 RX DQ/DQS(RDDQC) : PASS
6077 23:03:13.652434 TX DQ/DQS : PASS
6078 23:03:13.655908 RX DATLAT : PASS
6079 23:03:13.659227 RX DQ/DQS(Engine): PASS
6080 23:03:13.659309 TX OE : NO K
6081 23:03:13.659374 All Pass.
6082 23:03:13.662562
6083 23:03:13.662643 DramC Write-DBI off
6084 23:03:13.665696 PER_BANK_REFRESH: Hybrid Mode
6085 23:03:13.665779 TX_TRACKING: ON
6086 23:03:13.675495 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6087 23:03:13.678845 [FAST_K] Save calibration result to emmc
6088 23:03:13.682401 dramc_set_vcore_voltage set vcore to 650000
6089 23:03:13.685423 Read voltage for 400, 6
6090 23:03:13.685505 Vio18 = 0
6091 23:03:13.688891 Vcore = 650000
6092 23:03:13.688983 Vdram = 0
6093 23:03:13.689060 Vddq = 0
6094 23:03:13.689122 Vmddr = 0
6095 23:03:13.695996 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6096 23:03:13.702305 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6097 23:03:13.702388 MEM_TYPE=3, freq_sel=20
6098 23:03:13.705587 sv_algorithm_assistance_LP4_800
6099 23:03:13.708879 ============ PULL DRAM RESETB DOWN ============
6100 23:03:13.715535 ========== PULL DRAM RESETB DOWN end =========
6101 23:03:13.719007 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6102 23:03:13.722215 ===================================
6103 23:03:13.725407 LPDDR4 DRAM CONFIGURATION
6104 23:03:13.728561 ===================================
6105 23:03:13.728643 EX_ROW_EN[0] = 0x0
6106 23:03:13.731813 EX_ROW_EN[1] = 0x0
6107 23:03:13.735512 LP4Y_EN = 0x0
6108 23:03:13.735594 WORK_FSP = 0x0
6109 23:03:13.738451 WL = 0x2
6110 23:03:13.738533 RL = 0x2
6111 23:03:13.741747 BL = 0x2
6112 23:03:13.741828 RPST = 0x0
6113 23:03:13.745540 RD_PRE = 0x0
6114 23:03:13.745643 WR_PRE = 0x1
6115 23:03:13.748323 WR_PST = 0x0
6116 23:03:13.748405 DBI_WR = 0x0
6117 23:03:13.751849 DBI_RD = 0x0
6118 23:03:13.751931 OTF = 0x1
6119 23:03:13.755418 ===================================
6120 23:03:13.758547 ===================================
6121 23:03:13.761828 ANA top config
6122 23:03:13.765143 ===================================
6123 23:03:13.765225 DLL_ASYNC_EN = 0
6124 23:03:13.768513 ALL_SLAVE_EN = 1
6125 23:03:13.771696 NEW_RANK_MODE = 1
6126 23:03:13.775572 DLL_IDLE_MODE = 1
6127 23:03:13.775654 LP45_APHY_COMB_EN = 1
6128 23:03:13.778606 TX_ODT_DIS = 1
6129 23:03:13.781499 NEW_8X_MODE = 1
6130 23:03:13.785099 ===================================
6131 23:03:13.788377 ===================================
6132 23:03:13.791584 data_rate = 800
6133 23:03:13.795340 CKR = 1
6134 23:03:13.798691 DQ_P2S_RATIO = 4
6135 23:03:13.802085 ===================================
6136 23:03:13.802168 CA_P2S_RATIO = 4
6137 23:03:13.804816 DQ_CA_OPEN = 0
6138 23:03:13.808466 DQ_SEMI_OPEN = 1
6139 23:03:13.811710 CA_SEMI_OPEN = 1
6140 23:03:13.815365 CA_FULL_RATE = 0
6141 23:03:13.818524 DQ_CKDIV4_EN = 0
6142 23:03:13.818607 CA_CKDIV4_EN = 1
6143 23:03:13.821622 CA_PREDIV_EN = 0
6144 23:03:13.825161 PH8_DLY = 0
6145 23:03:13.828181 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6146 23:03:13.831641 DQ_AAMCK_DIV = 0
6147 23:03:13.835314 CA_AAMCK_DIV = 0
6148 23:03:13.835396 CA_ADMCK_DIV = 4
6149 23:03:13.838037 DQ_TRACK_CA_EN = 0
6150 23:03:13.841731 CA_PICK = 800
6151 23:03:13.844503 CA_MCKIO = 400
6152 23:03:13.848310 MCKIO_SEMI = 400
6153 23:03:13.851785 PLL_FREQ = 3016
6154 23:03:13.854952 DQ_UI_PI_RATIO = 32
6155 23:03:13.855034 CA_UI_PI_RATIO = 32
6156 23:03:13.858273 ===================================
6157 23:03:13.861582 ===================================
6158 23:03:13.864737 memory_type:LPDDR4
6159 23:03:13.868073 GP_NUM : 10
6160 23:03:13.868155 SRAM_EN : 1
6161 23:03:13.871791 MD32_EN : 0
6162 23:03:13.874579 ===================================
6163 23:03:13.877820 [ANA_INIT] >>>>>>>>>>>>>>
6164 23:03:13.881225 <<<<<< [CONFIGURE PHASE]: ANA_TX
6165 23:03:13.884381 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6166 23:03:13.887710 ===================================
6167 23:03:13.887792 data_rate = 800,PCW = 0X7400
6168 23:03:13.891184 ===================================
6169 23:03:13.894321 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6170 23:03:13.900888 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6171 23:03:13.914250 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6172 23:03:13.917504 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6173 23:03:13.920655 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6174 23:03:13.923996 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6175 23:03:13.927476 [ANA_INIT] flow start
6176 23:03:13.927558 [ANA_INIT] PLL >>>>>>>>
6177 23:03:13.930928 [ANA_INIT] PLL <<<<<<<<
6178 23:03:13.934279 [ANA_INIT] MIDPI >>>>>>>>
6179 23:03:13.937311 [ANA_INIT] MIDPI <<<<<<<<
6180 23:03:13.937416 [ANA_INIT] DLL >>>>>>>>
6181 23:03:13.940523 [ANA_INIT] flow end
6182 23:03:13.944013 ============ LP4 DIFF to SE enter ============
6183 23:03:13.947180 ============ LP4 DIFF to SE exit ============
6184 23:03:13.950620 [ANA_INIT] <<<<<<<<<<<<<
6185 23:03:13.954063 [Flow] Enable top DCM control >>>>>
6186 23:03:13.957639 [Flow] Enable top DCM control <<<<<
6187 23:03:13.960781 Enable DLL master slave shuffle
6188 23:03:13.967267 ==============================================================
6189 23:03:13.967349 Gating Mode config
6190 23:03:13.974062 ==============================================================
6191 23:03:13.974145 Config description:
6192 23:03:13.983727 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6193 23:03:13.990376 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6194 23:03:13.996876 SELPH_MODE 0: By rank 1: By Phase
6195 23:03:14.000465 ==============================================================
6196 23:03:14.003681 GAT_TRACK_EN = 0
6197 23:03:14.006775 RX_GATING_MODE = 2
6198 23:03:14.010236 RX_GATING_TRACK_MODE = 2
6199 23:03:14.013790 SELPH_MODE = 1
6200 23:03:14.017130 PICG_EARLY_EN = 1
6201 23:03:14.020322 VALID_LAT_VALUE = 1
6202 23:03:14.023611 ==============================================================
6203 23:03:14.026841 Enter into Gating configuration >>>>
6204 23:03:14.030034 Exit from Gating configuration <<<<
6205 23:03:14.033737 Enter into DVFS_PRE_config >>>>>
6206 23:03:14.047129 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6207 23:03:14.050036 Exit from DVFS_PRE_config <<<<<
6208 23:03:14.053140 Enter into PICG configuration >>>>
6209 23:03:14.056741 Exit from PICG configuration <<<<
6210 23:03:14.056823 [RX_INPUT] configuration >>>>>
6211 23:03:14.060016 [RX_INPUT] configuration <<<<<
6212 23:03:14.066705 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6213 23:03:14.070073 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6214 23:03:14.076728 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6215 23:03:14.083189 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6216 23:03:14.090265 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6217 23:03:14.096821 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6218 23:03:14.100154 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6219 23:03:14.103368 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6220 23:03:14.106622 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6221 23:03:14.113476 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6222 23:03:14.116925 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6223 23:03:14.119751 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6224 23:03:14.122879 ===================================
6225 23:03:14.126285 LPDDR4 DRAM CONFIGURATION
6226 23:03:14.129820 ===================================
6227 23:03:14.133043 EX_ROW_EN[0] = 0x0
6228 23:03:14.133125 EX_ROW_EN[1] = 0x0
6229 23:03:14.136190 LP4Y_EN = 0x0
6230 23:03:14.136307 WORK_FSP = 0x0
6231 23:03:14.139754 WL = 0x2
6232 23:03:14.139835 RL = 0x2
6233 23:03:14.142868 BL = 0x2
6234 23:03:14.142949 RPST = 0x0
6235 23:03:14.146186 RD_PRE = 0x0
6236 23:03:14.146268 WR_PRE = 0x1
6237 23:03:14.149380 WR_PST = 0x0
6238 23:03:14.149462 DBI_WR = 0x0
6239 23:03:14.152937 DBI_RD = 0x0
6240 23:03:14.156233 OTF = 0x1
6241 23:03:14.159400 ===================================
6242 23:03:14.163069 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6243 23:03:14.166124 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6244 23:03:14.169642 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6245 23:03:14.172729 ===================================
6246 23:03:14.175761 LPDDR4 DRAM CONFIGURATION
6247 23:03:14.179125 ===================================
6248 23:03:14.182393 EX_ROW_EN[0] = 0x10
6249 23:03:14.182501 EX_ROW_EN[1] = 0x0
6250 23:03:14.185955 LP4Y_EN = 0x0
6251 23:03:14.186059 WORK_FSP = 0x0
6252 23:03:14.188969 WL = 0x2
6253 23:03:14.189051 RL = 0x2
6254 23:03:14.192758 BL = 0x2
6255 23:03:14.192897 RPST = 0x0
6256 23:03:14.196050 RD_PRE = 0x0
6257 23:03:14.196171 WR_PRE = 0x1
6258 23:03:14.199192 WR_PST = 0x0
6259 23:03:14.199274 DBI_WR = 0x0
6260 23:03:14.202492 DBI_RD = 0x0
6261 23:03:14.205390 OTF = 0x1
6262 23:03:14.209081 ===================================
6263 23:03:14.212119 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6264 23:03:14.217493 nWR fixed to 30
6265 23:03:14.220741 [ModeRegInit_LP4] CH0 RK0
6266 23:03:14.220850 [ModeRegInit_LP4] CH0 RK1
6267 23:03:14.223898 [ModeRegInit_LP4] CH1 RK0
6268 23:03:14.227216 [ModeRegInit_LP4] CH1 RK1
6269 23:03:14.227325 match AC timing 19
6270 23:03:14.233678 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6271 23:03:14.237145 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6272 23:03:14.240424 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6273 23:03:14.248974 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6274 23:03:14.250234 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6275 23:03:14.250316 ==
6276 23:03:14.253975 Dram Type= 6, Freq= 0, CH_0, rank 0
6277 23:03:14.256924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6278 23:03:14.257008 ==
6279 23:03:14.263936 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6280 23:03:14.270508 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6281 23:03:14.273552 [CA 0] Center 36 (8~64) winsize 57
6282 23:03:14.277438 [CA 1] Center 36 (8~64) winsize 57
6283 23:03:14.280636 [CA 2] Center 36 (8~64) winsize 57
6284 23:03:14.283617 [CA 3] Center 36 (8~64) winsize 57
6285 23:03:14.283699 [CA 4] Center 36 (8~64) winsize 57
6286 23:03:14.287543 [CA 5] Center 36 (8~64) winsize 57
6287 23:03:14.287625
6288 23:03:14.293600 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6289 23:03:14.293683
6290 23:03:14.297006 [CATrainingPosCal] consider 1 rank data
6291 23:03:14.300151 u2DelayCellTimex100 = 270/100 ps
6292 23:03:14.303858 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6293 23:03:14.307064 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6294 23:03:14.310389 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6295 23:03:14.313681 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6296 23:03:14.317346 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6297 23:03:14.320517 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6298 23:03:14.320598
6299 23:03:14.323402 CA PerBit enable=1, Macro0, CA PI delay=36
6300 23:03:14.323484
6301 23:03:14.326957 [CBTSetCACLKResult] CA Dly = 36
6302 23:03:14.330132 CS Dly: 1 (0~32)
6303 23:03:14.330214 ==
6304 23:03:14.333494 Dram Type= 6, Freq= 0, CH_0, rank 1
6305 23:03:14.337094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6306 23:03:14.337177 ==
6307 23:03:14.343259 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6308 23:03:14.350157 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6309 23:03:14.350239 [CA 0] Center 36 (8~64) winsize 57
6310 23:03:14.353529 [CA 1] Center 36 (8~64) winsize 57
6311 23:03:14.356576 [CA 2] Center 36 (8~64) winsize 57
6312 23:03:14.359844 [CA 3] Center 36 (8~64) winsize 57
6313 23:03:14.363355 [CA 4] Center 36 (8~64) winsize 57
6314 23:03:14.366422 [CA 5] Center 36 (8~64) winsize 57
6315 23:03:14.366504
6316 23:03:14.370069 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6317 23:03:14.370159
6318 23:03:14.373333 [CATrainingPosCal] consider 2 rank data
6319 23:03:14.376542 u2DelayCellTimex100 = 270/100 ps
6320 23:03:14.379730 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6321 23:03:14.383511 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6322 23:03:14.389706 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6323 23:03:14.393204 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6324 23:03:14.396630 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6325 23:03:14.399656 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6326 23:03:14.399737
6327 23:03:14.402926 CA PerBit enable=1, Macro0, CA PI delay=36
6328 23:03:14.403008
6329 23:03:14.406587 [CBTSetCACLKResult] CA Dly = 36
6330 23:03:14.406669 CS Dly: 1 (0~32)
6331 23:03:14.406733
6332 23:03:14.413369 ----->DramcWriteLeveling(PI) begin...
6333 23:03:14.413452 ==
6334 23:03:14.416170 Dram Type= 6, Freq= 0, CH_0, rank 0
6335 23:03:14.419973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6336 23:03:14.420055 ==
6337 23:03:14.423257 Write leveling (Byte 0): 40 => 8
6338 23:03:14.426500 Write leveling (Byte 1): 40 => 8
6339 23:03:14.429889 DramcWriteLeveling(PI) end<-----
6340 23:03:14.429971
6341 23:03:14.430035 ==
6342 23:03:14.433198 Dram Type= 6, Freq= 0, CH_0, rank 0
6343 23:03:14.436451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6344 23:03:14.436533 ==
6345 23:03:14.439887 [Gating] SW mode calibration
6346 23:03:14.446273 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6347 23:03:14.449499 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6348 23:03:14.456400 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6349 23:03:14.459621 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6350 23:03:14.463341 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6351 23:03:14.469578 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6352 23:03:14.473092 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6353 23:03:14.476245 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6354 23:03:14.482803 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6355 23:03:14.486189 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6356 23:03:14.490118 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6357 23:03:14.493047 Total UI for P1: 0, mck2ui 16
6358 23:03:14.496516 best dqsien dly found for B0: ( 0, 14, 24)
6359 23:03:14.499805 Total UI for P1: 0, mck2ui 16
6360 23:03:14.503013 best dqsien dly found for B1: ( 0, 14, 24)
6361 23:03:14.506043 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6362 23:03:14.509297 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6363 23:03:14.512678
6364 23:03:14.516377 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6365 23:03:14.519180 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6366 23:03:14.522682 [Gating] SW calibration Done
6367 23:03:14.522763 ==
6368 23:03:14.526203 Dram Type= 6, Freq= 0, CH_0, rank 0
6369 23:03:14.529149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6370 23:03:14.529231 ==
6371 23:03:14.529295 RX Vref Scan: 0
6372 23:03:14.532503
6373 23:03:14.532595 RX Vref 0 -> 0, step: 1
6374 23:03:14.532686
6375 23:03:14.535582 RX Delay -410 -> 252, step: 16
6376 23:03:14.539294 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6377 23:03:14.545497 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6378 23:03:14.549471 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6379 23:03:14.552495 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6380 23:03:14.555516 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6381 23:03:14.562005 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6382 23:03:14.565391 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6383 23:03:14.568941 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6384 23:03:14.572121 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6385 23:03:14.578757 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6386 23:03:14.582056 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6387 23:03:14.585413 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6388 23:03:14.591924 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6389 23:03:14.595437 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6390 23:03:14.598639 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6391 23:03:14.602050 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6392 23:03:14.602168 ==
6393 23:03:14.605289 Dram Type= 6, Freq= 0, CH_0, rank 0
6394 23:03:14.611659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6395 23:03:14.611788 ==
6396 23:03:14.611901 DQS Delay:
6397 23:03:14.614884 DQS0 = 59, DQS1 = 59
6398 23:03:14.614987 DQM Delay:
6399 23:03:14.618353 DQM0 = 18, DQM1 = 10
6400 23:03:14.618450 DQ Delay:
6401 23:03:14.621559 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6402 23:03:14.625182 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6403 23:03:14.628489 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6404 23:03:14.631636 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6405 23:03:14.631733
6406 23:03:14.631821
6407 23:03:14.631911 ==
6408 23:03:14.634758 Dram Type= 6, Freq= 0, CH_0, rank 0
6409 23:03:14.637997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6410 23:03:14.638080 ==
6411 23:03:14.638145
6412 23:03:14.638205
6413 23:03:14.641621 TX Vref Scan disable
6414 23:03:14.641703 == TX Byte 0 ==
6415 23:03:14.647893 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6416 23:03:14.651110 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6417 23:03:14.651193 == TX Byte 1 ==
6418 23:03:14.658072 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6419 23:03:14.661742 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6420 23:03:14.661826 ==
6421 23:03:14.664610 Dram Type= 6, Freq= 0, CH_0, rank 0
6422 23:03:14.667739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6423 23:03:14.667822 ==
6424 23:03:14.667887
6425 23:03:14.667947
6426 23:03:14.671185 TX Vref Scan disable
6427 23:03:14.671268 == TX Byte 0 ==
6428 23:03:14.677923 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6429 23:03:14.681030 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6430 23:03:14.681112 == TX Byte 1 ==
6431 23:03:14.687802 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6432 23:03:14.691139 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6433 23:03:14.691221
6434 23:03:14.691286 [DATLAT]
6435 23:03:14.694284 Freq=400, CH0 RK0
6436 23:03:14.694366
6437 23:03:14.694431 DATLAT Default: 0xf
6438 23:03:14.697636 0, 0xFFFF, sum = 0
6439 23:03:14.697720 1, 0xFFFF, sum = 0
6440 23:03:14.700960 2, 0xFFFF, sum = 0
6441 23:03:14.701043 3, 0xFFFF, sum = 0
6442 23:03:14.704647 4, 0xFFFF, sum = 0
6443 23:03:14.704730 5, 0xFFFF, sum = 0
6444 23:03:14.707375 6, 0xFFFF, sum = 0
6445 23:03:14.707466 7, 0xFFFF, sum = 0
6446 23:03:14.710968 8, 0xFFFF, sum = 0
6447 23:03:14.714193 9, 0xFFFF, sum = 0
6448 23:03:14.714275 10, 0xFFFF, sum = 0
6449 23:03:14.717328 11, 0xFFFF, sum = 0
6450 23:03:14.717411 12, 0xFFFF, sum = 0
6451 23:03:14.720529 13, 0x0, sum = 1
6452 23:03:14.720612 14, 0x0, sum = 2
6453 23:03:14.724213 15, 0x0, sum = 3
6454 23:03:14.724297 16, 0x0, sum = 4
6455 23:03:14.724363 best_step = 14
6456 23:03:14.727566
6457 23:03:14.727647 ==
6458 23:03:14.730467 Dram Type= 6, Freq= 0, CH_0, rank 0
6459 23:03:14.733942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6460 23:03:14.734024 ==
6461 23:03:14.734089 RX Vref Scan: 1
6462 23:03:14.734148
6463 23:03:14.737756 RX Vref 0 -> 0, step: 1
6464 23:03:14.737837
6465 23:03:14.740845 RX Delay -359 -> 252, step: 8
6466 23:03:14.740927
6467 23:03:14.744239 Set Vref, RX VrefLevel [Byte0]: 60
6468 23:03:14.747541 [Byte1]: 57
6469 23:03:14.751385
6470 23:03:14.751467 Final RX Vref Byte 0 = 60 to rank0
6471 23:03:14.754529 Final RX Vref Byte 1 = 57 to rank0
6472 23:03:14.758000 Final RX Vref Byte 0 = 60 to rank1
6473 23:03:14.761352 Final RX Vref Byte 1 = 57 to rank1==
6474 23:03:14.764403 Dram Type= 6, Freq= 0, CH_0, rank 0
6475 23:03:14.771270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6476 23:03:14.771353 ==
6477 23:03:14.771418 DQS Delay:
6478 23:03:14.774210 DQS0 = 60, DQS1 = 68
6479 23:03:14.774292 DQM Delay:
6480 23:03:14.774357 DQM0 = 15, DQM1 = 13
6481 23:03:14.777555 DQ Delay:
6482 23:03:14.781187 DQ0 =16, DQ1 =16, DQ2 =12, DQ3 =12
6483 23:03:14.784532 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6484 23:03:14.784615 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6485 23:03:14.791345 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =20
6486 23:03:14.791426
6487 23:03:14.791491
6488 23:03:14.797423 [DQSOSCAuto] RK0, (LSB)MR18= 0x817f, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6489 23:03:14.801414 CH0 RK0: MR19=C0C, MR18=817F
6490 23:03:14.807601 CH0_RK0: MR19=0xC0C, MR18=0x817F, DQSOSC=393, MR23=63, INC=382, DEC=254
6491 23:03:14.807688 ==
6492 23:03:14.810916 Dram Type= 6, Freq= 0, CH_0, rank 1
6493 23:03:14.814834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6494 23:03:14.814917 ==
6495 23:03:14.817487 [Gating] SW mode calibration
6496 23:03:14.824358 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6497 23:03:14.830495 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6498 23:03:14.834200 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6499 23:03:14.837233 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6500 23:03:14.844440 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6501 23:03:14.847382 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6502 23:03:14.850875 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6503 23:03:14.857339 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6504 23:03:14.860408 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6505 23:03:14.863791 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6506 23:03:14.870510 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6507 23:03:14.870595 Total UI for P1: 0, mck2ui 16
6508 23:03:14.877287 best dqsien dly found for B0: ( 0, 14, 24)
6509 23:03:14.877369 Total UI for P1: 0, mck2ui 16
6510 23:03:14.880537 best dqsien dly found for B1: ( 0, 14, 24)
6511 23:03:14.887022 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6512 23:03:14.890326 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6513 23:03:14.890408
6514 23:03:14.894082 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6515 23:03:14.896984 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6516 23:03:14.901011 [Gating] SW calibration Done
6517 23:03:14.901094 ==
6518 23:03:14.903672 Dram Type= 6, Freq= 0, CH_0, rank 1
6519 23:03:14.907581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6520 23:03:14.907664 ==
6521 23:03:14.910654 RX Vref Scan: 0
6522 23:03:14.910735
6523 23:03:14.910800 RX Vref 0 -> 0, step: 1
6524 23:03:14.910859
6525 23:03:14.913676 RX Delay -410 -> 252, step: 16
6526 23:03:14.917198 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6527 23:03:14.923787 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6528 23:03:14.927321 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6529 23:03:14.930156 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6530 23:03:14.933672 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6531 23:03:14.940390 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6532 23:03:14.943973 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6533 23:03:14.946927 iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528
6534 23:03:14.950257 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6535 23:03:14.957199 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6536 23:03:14.960503 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6537 23:03:14.963515 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6538 23:03:14.970388 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6539 23:03:14.973852 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6540 23:03:14.976785 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6541 23:03:14.979972 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6542 23:03:14.980054 ==
6543 23:03:14.983349 Dram Type= 6, Freq= 0, CH_0, rank 1
6544 23:03:14.990202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6545 23:03:14.990285 ==
6546 23:03:14.990349 DQS Delay:
6547 23:03:14.993460 DQS0 = 59, DQS1 = 59
6548 23:03:14.993542 DQM Delay:
6549 23:03:14.996668 DQM0 = 16, DQM1 = 10
6550 23:03:14.996749 DQ Delay:
6551 23:03:14.999935 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6552 23:03:15.003277 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6553 23:03:15.007034 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6554 23:03:15.010028 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6555 23:03:15.010110
6556 23:03:15.010174
6557 23:03:15.010234 ==
6558 23:03:15.013259 Dram Type= 6, Freq= 0, CH_0, rank 1
6559 23:03:15.016509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6560 23:03:15.016591 ==
6561 23:03:15.016655
6562 23:03:15.016714
6563 23:03:15.019628 TX Vref Scan disable
6564 23:03:15.019709 == TX Byte 0 ==
6565 23:03:15.026307 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6566 23:03:15.029735 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6567 23:03:15.029817 == TX Byte 1 ==
6568 23:03:15.036159 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6569 23:03:15.039661 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6570 23:03:15.039743 ==
6571 23:03:15.043152 Dram Type= 6, Freq= 0, CH_0, rank 1
6572 23:03:15.046421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6573 23:03:15.046504 ==
6574 23:03:15.046569
6575 23:03:15.046629
6576 23:03:15.049727 TX Vref Scan disable
6577 23:03:15.049811 == TX Byte 0 ==
6578 23:03:15.056470 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6579 23:03:15.059888 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6580 23:03:15.059970 == TX Byte 1 ==
6581 23:03:15.066111 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6582 23:03:15.069224 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6583 23:03:15.069306
6584 23:03:15.069371 [DATLAT]
6585 23:03:15.072676 Freq=400, CH0 RK1
6586 23:03:15.072758
6587 23:03:15.072822 DATLAT Default: 0xe
6588 23:03:15.076239 0, 0xFFFF, sum = 0
6589 23:03:15.076362 1, 0xFFFF, sum = 0
6590 23:03:15.079374 2, 0xFFFF, sum = 0
6591 23:03:15.079457 3, 0xFFFF, sum = 0
6592 23:03:15.082555 4, 0xFFFF, sum = 0
6593 23:03:15.082638 5, 0xFFFF, sum = 0
6594 23:03:15.086449 6, 0xFFFF, sum = 0
6595 23:03:15.086533 7, 0xFFFF, sum = 0
6596 23:03:15.089298 8, 0xFFFF, sum = 0
6597 23:03:15.089376 9, 0xFFFF, sum = 0
6598 23:03:15.092575 10, 0xFFFF, sum = 0
6599 23:03:15.095951 11, 0xFFFF, sum = 0
6600 23:03:15.096053 12, 0xFFFF, sum = 0
6601 23:03:15.099293 13, 0x0, sum = 1
6602 23:03:15.099368 14, 0x0, sum = 2
6603 23:03:15.102639 15, 0x0, sum = 3
6604 23:03:15.102723 16, 0x0, sum = 4
6605 23:03:15.102788 best_step = 14
6606 23:03:15.102848
6607 23:03:15.106128 ==
6608 23:03:15.109471 Dram Type= 6, Freq= 0, CH_0, rank 1
6609 23:03:15.112696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6610 23:03:15.112778 ==
6611 23:03:15.112842 RX Vref Scan: 0
6612 23:03:15.112901
6613 23:03:15.115799 RX Vref 0 -> 0, step: 1
6614 23:03:15.115879
6615 23:03:15.119063 RX Delay -359 -> 252, step: 8
6616 23:03:15.126194 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6617 23:03:15.129354 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6618 23:03:15.133109 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6619 23:03:15.136154 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6620 23:03:15.142485 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6621 23:03:15.146161 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6622 23:03:15.149539 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6623 23:03:15.152657 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6624 23:03:15.159212 iDelay=217, Bit 8, Center -60 (-311 ~ 192) 504
6625 23:03:15.162908 iDelay=217, Bit 9, Center -68 (-319 ~ 184) 504
6626 23:03:15.166914 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6627 23:03:15.172496 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6628 23:03:15.175837 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6629 23:03:15.179240 iDelay=217, Bit 13, Center -52 (-303 ~ 200) 504
6630 23:03:15.182431 iDelay=217, Bit 14, Center -44 (-295 ~ 208) 504
6631 23:03:15.188838 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
6632 23:03:15.188920 ==
6633 23:03:15.192619 Dram Type= 6, Freq= 0, CH_0, rank 1
6634 23:03:15.195737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6635 23:03:15.195819 ==
6636 23:03:15.195883 DQS Delay:
6637 23:03:15.198908 DQS0 = 60, DQS1 = 68
6638 23:03:15.198989 DQM Delay:
6639 23:03:15.202146 DQM0 = 11, DQM1 = 14
6640 23:03:15.202243 DQ Delay:
6641 23:03:15.205505 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6642 23:03:15.209258 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24
6643 23:03:15.212102 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6644 23:03:15.215423 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =20
6645 23:03:15.215504
6646 23:03:15.215587
6647 23:03:15.222230 [DQSOSCAuto] RK1, (LSB)MR18= 0xc77d, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 385 ps
6648 23:03:15.225593 CH0 RK1: MR19=C0C, MR18=C77D
6649 23:03:15.231933 CH0_RK1: MR19=0xC0C, MR18=0xC77D, DQSOSC=385, MR23=63, INC=398, DEC=265
6650 23:03:15.235448 [RxdqsGatingPostProcess] freq 400
6651 23:03:15.241680 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6652 23:03:15.245386 best DQS0 dly(2T, 0.5T) = (0, 10)
6653 23:03:15.245475 best DQS1 dly(2T, 0.5T) = (0, 10)
6654 23:03:15.248598 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6655 23:03:15.251810 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6656 23:03:15.254874 best DQS0 dly(2T, 0.5T) = (0, 10)
6657 23:03:15.258675 best DQS1 dly(2T, 0.5T) = (0, 10)
6658 23:03:15.261917 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6659 23:03:15.265206 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6660 23:03:15.268543 Pre-setting of DQS Precalculation
6661 23:03:15.275326 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6662 23:03:15.275434 ==
6663 23:03:15.278405 Dram Type= 6, Freq= 0, CH_1, rank 0
6664 23:03:15.281629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6665 23:03:15.281727 ==
6666 23:03:15.288483 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6667 23:03:15.291774 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6668 23:03:15.295048 [CA 0] Center 36 (8~64) winsize 57
6669 23:03:15.298677 [CA 1] Center 36 (8~64) winsize 57
6670 23:03:15.301896 [CA 2] Center 36 (8~64) winsize 57
6671 23:03:15.305199 [CA 3] Center 36 (8~64) winsize 57
6672 23:03:15.308319 [CA 4] Center 36 (8~64) winsize 57
6673 23:03:15.311504 [CA 5] Center 36 (8~64) winsize 57
6674 23:03:15.311593
6675 23:03:15.315349 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6676 23:03:15.315449
6677 23:03:15.318431 [CATrainingPosCal] consider 1 rank data
6678 23:03:15.321379 u2DelayCellTimex100 = 270/100 ps
6679 23:03:15.324833 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6680 23:03:15.328444 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6681 23:03:15.334588 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6682 23:03:15.337839 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6683 23:03:15.341001 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6684 23:03:15.344844 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6685 23:03:15.344919
6686 23:03:15.347998 CA PerBit enable=1, Macro0, CA PI delay=36
6687 23:03:15.348107
6688 23:03:15.351038 [CBTSetCACLKResult] CA Dly = 36
6689 23:03:15.351138 CS Dly: 1 (0~32)
6690 23:03:15.354395 ==
6691 23:03:15.358005 Dram Type= 6, Freq= 0, CH_1, rank 1
6692 23:03:15.360717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6693 23:03:15.360793 ==
6694 23:03:15.364447 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6695 23:03:15.370855 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6696 23:03:15.374286 [CA 0] Center 36 (8~64) winsize 57
6697 23:03:15.377212 [CA 1] Center 36 (8~64) winsize 57
6698 23:03:15.381106 [CA 2] Center 36 (8~64) winsize 57
6699 23:03:15.384332 [CA 3] Center 36 (8~64) winsize 57
6700 23:03:15.387055 [CA 4] Center 36 (8~64) winsize 57
6701 23:03:15.390497 [CA 5] Center 36 (8~64) winsize 57
6702 23:03:15.390597
6703 23:03:15.393752 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6704 23:03:15.393859
6705 23:03:15.397657 [CATrainingPosCal] consider 2 rank data
6706 23:03:15.400942 u2DelayCellTimex100 = 270/100 ps
6707 23:03:15.403795 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6708 23:03:15.407186 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6709 23:03:15.410648 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6710 23:03:15.417021 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6711 23:03:15.420358 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6712 23:03:15.423743 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6713 23:03:15.423847
6714 23:03:15.426873 CA PerBit enable=1, Macro0, CA PI delay=36
6715 23:03:15.426971
6716 23:03:15.430421 [CBTSetCACLKResult] CA Dly = 36
6717 23:03:15.430521 CS Dly: 1 (0~32)
6718 23:03:15.430620
6719 23:03:15.433539 ----->DramcWriteLeveling(PI) begin...
6720 23:03:15.433630 ==
6721 23:03:15.437175 Dram Type= 6, Freq= 0, CH_1, rank 0
6722 23:03:15.443306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6723 23:03:15.443409 ==
6724 23:03:15.446991 Write leveling (Byte 0): 40 => 8
6725 23:03:15.450019 Write leveling (Byte 1): 40 => 8
6726 23:03:15.450120 DramcWriteLeveling(PI) end<-----
6727 23:03:15.453539
6728 23:03:15.453625 ==
6729 23:03:15.456790 Dram Type= 6, Freq= 0, CH_1, rank 0
6730 23:03:15.460031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6731 23:03:15.460130 ==
6732 23:03:15.463280 [Gating] SW mode calibration
6733 23:03:15.469648 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6734 23:03:15.476468 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6735 23:03:15.479935 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6736 23:03:15.482905 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6737 23:03:15.486585 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6738 23:03:15.492725 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6739 23:03:15.496348 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6740 23:03:15.499510 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6741 23:03:15.506064 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6742 23:03:15.509565 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6743 23:03:15.512489 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6744 23:03:15.516238 Total UI for P1: 0, mck2ui 16
6745 23:03:15.519391 best dqsien dly found for B0: ( 0, 14, 24)
6746 23:03:15.522687 Total UI for P1: 0, mck2ui 16
6747 23:03:15.525716 best dqsien dly found for B1: ( 0, 14, 24)
6748 23:03:15.529223 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6749 23:03:15.535786 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6750 23:03:15.535867
6751 23:03:15.539038 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6752 23:03:15.542545 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6753 23:03:15.545995 [Gating] SW calibration Done
6754 23:03:15.546093 ==
6755 23:03:15.549225 Dram Type= 6, Freq= 0, CH_1, rank 0
6756 23:03:15.552563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6757 23:03:15.552644 ==
6758 23:03:15.555805 RX Vref Scan: 0
6759 23:03:15.555914
6760 23:03:15.556005 RX Vref 0 -> 0, step: 1
6761 23:03:15.556101
6762 23:03:15.559150 RX Delay -410 -> 252, step: 16
6763 23:03:15.562132 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6764 23:03:15.568761 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6765 23:03:15.572370 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6766 23:03:15.575647 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6767 23:03:15.578747 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6768 23:03:15.585405 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6769 23:03:15.589336 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6770 23:03:15.591965 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6771 23:03:15.595826 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6772 23:03:15.601923 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6773 23:03:15.605286 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6774 23:03:15.609144 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6775 23:03:15.615189 iDelay=230, Bit 12, Center -35 (-298 ~ 229) 528
6776 23:03:15.618889 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6777 23:03:15.621836 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6778 23:03:15.625140 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6779 23:03:15.625217 ==
6780 23:03:15.628744 Dram Type= 6, Freq= 0, CH_1, rank 0
6781 23:03:15.635266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6782 23:03:15.635369 ==
6783 23:03:15.635470 DQS Delay:
6784 23:03:15.638665 DQS0 = 51, DQS1 = 67
6785 23:03:15.638764 DQM Delay:
6786 23:03:15.641735 DQM0 = 12, DQM1 = 20
6787 23:03:15.641843 DQ Delay:
6788 23:03:15.645252 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6789 23:03:15.648484 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6790 23:03:15.648559 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6791 23:03:15.655634 DQ12 =32, DQ13 =32, DQ14 =24, DQ15 =32
6792 23:03:15.655710
6793 23:03:15.655772
6794 23:03:15.655844 ==
6795 23:03:15.658712 Dram Type= 6, Freq= 0, CH_1, rank 0
6796 23:03:15.661844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6797 23:03:15.661918 ==
6798 23:03:15.661981
6799 23:03:15.662039
6800 23:03:15.665062 TX Vref Scan disable
6801 23:03:15.665136 == TX Byte 0 ==
6802 23:03:15.668403 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6803 23:03:15.675069 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6804 23:03:15.675175 == TX Byte 1 ==
6805 23:03:15.678607 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6806 23:03:15.684834 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6807 23:03:15.684910 ==
6808 23:03:15.688322 Dram Type= 6, Freq= 0, CH_1, rank 0
6809 23:03:15.691549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6810 23:03:15.691650 ==
6811 23:03:15.691739
6812 23:03:15.691867
6813 23:03:15.694905 TX Vref Scan disable
6814 23:03:15.695001 == TX Byte 0 ==
6815 23:03:15.701424 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6816 23:03:15.705074 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6817 23:03:15.705176 == TX Byte 1 ==
6818 23:03:15.711607 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6819 23:03:15.714888 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6820 23:03:15.714997
6821 23:03:15.715088 [DATLAT]
6822 23:03:15.718011 Freq=400, CH1 RK0
6823 23:03:15.718120
6824 23:03:15.718210 DATLAT Default: 0xf
6825 23:03:15.721360 0, 0xFFFF, sum = 0
6826 23:03:15.721436 1, 0xFFFF, sum = 0
6827 23:03:15.724924 2, 0xFFFF, sum = 0
6828 23:03:15.725029 3, 0xFFFF, sum = 0
6829 23:03:15.728043 4, 0xFFFF, sum = 0
6830 23:03:15.728152 5, 0xFFFF, sum = 0
6831 23:03:15.731648 6, 0xFFFF, sum = 0
6832 23:03:15.731750 7, 0xFFFF, sum = 0
6833 23:03:15.734368 8, 0xFFFF, sum = 0
6834 23:03:15.734443 9, 0xFFFF, sum = 0
6835 23:03:15.737802 10, 0xFFFF, sum = 0
6836 23:03:15.737891 11, 0xFFFF, sum = 0
6837 23:03:15.741209 12, 0xFFFF, sum = 0
6838 23:03:15.741282 13, 0x0, sum = 1
6839 23:03:15.744939 14, 0x0, sum = 2
6840 23:03:15.745014 15, 0x0, sum = 3
6841 23:03:15.747773 16, 0x0, sum = 4
6842 23:03:15.747884 best_step = 14
6843 23:03:15.747973
6844 23:03:15.748059 ==
6845 23:03:15.751181 Dram Type= 6, Freq= 0, CH_1, rank 0
6846 23:03:15.758028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6847 23:03:15.758129 ==
6848 23:03:15.758231 RX Vref Scan: 1
6849 23:03:15.758320
6850 23:03:15.761035 RX Vref 0 -> 0, step: 1
6851 23:03:15.761133
6852 23:03:15.764360 RX Delay -375 -> 252, step: 8
6853 23:03:15.764468
6854 23:03:15.767773 Set Vref, RX VrefLevel [Byte0]: 56
6855 23:03:15.770958 [Byte1]: 56
6856 23:03:15.774791
6857 23:03:15.774891 Final RX Vref Byte 0 = 56 to rank0
6858 23:03:15.777722 Final RX Vref Byte 1 = 56 to rank0
6859 23:03:15.781419 Final RX Vref Byte 0 = 56 to rank1
6860 23:03:15.784528 Final RX Vref Byte 1 = 56 to rank1==
6861 23:03:15.787615 Dram Type= 6, Freq= 0, CH_1, rank 0
6862 23:03:15.794778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6863 23:03:15.794879 ==
6864 23:03:15.794974 DQS Delay:
6865 23:03:15.797675 DQS0 = 56, DQS1 = 68
6866 23:03:15.797748 DQM Delay:
6867 23:03:15.797823 DQM0 = 12, DQM1 = 13
6868 23:03:15.801331 DQ Delay:
6869 23:03:15.804608 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
6870 23:03:15.804687 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6871 23:03:15.808172 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6872 23:03:15.811200 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6873 23:03:15.811298
6874 23:03:15.811368
6875 23:03:15.820742 [DQSOSCAuto] RK0, (LSB)MR18= 0x586c, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 398 ps
6876 23:03:15.824165 CH1 RK0: MR19=C0C, MR18=586C
6877 23:03:15.831136 CH1_RK0: MR19=0xC0C, MR18=0x586C, DQSOSC=396, MR23=63, INC=376, DEC=251
6878 23:03:15.831240 ==
6879 23:03:15.834379 Dram Type= 6, Freq= 0, CH_1, rank 1
6880 23:03:15.837598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6881 23:03:15.837672 ==
6882 23:03:15.840978 [Gating] SW mode calibration
6883 23:03:15.847384 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6884 23:03:15.851157 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6885 23:03:15.857434 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6886 23:03:15.860673 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6887 23:03:15.864320 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6888 23:03:15.870821 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6889 23:03:15.874378 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6890 23:03:15.877782 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6891 23:03:15.884482 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6892 23:03:15.887574 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6893 23:03:15.890455 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6894 23:03:15.894098 Total UI for P1: 0, mck2ui 16
6895 23:03:15.897201 best dqsien dly found for B0: ( 0, 14, 24)
6896 23:03:15.900756 Total UI for P1: 0, mck2ui 16
6897 23:03:15.904077 best dqsien dly found for B1: ( 0, 14, 24)
6898 23:03:15.907094 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6899 23:03:15.910504 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6900 23:03:15.914199
6901 23:03:15.917291 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6902 23:03:15.920476 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6903 23:03:15.924060 [Gating] SW calibration Done
6904 23:03:15.924165 ==
6905 23:03:15.927423 Dram Type= 6, Freq= 0, CH_1, rank 1
6906 23:03:15.931176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6907 23:03:15.931277 ==
6908 23:03:15.931379 RX Vref Scan: 0
6909 23:03:15.933766
6910 23:03:15.933855 RX Vref 0 -> 0, step: 1
6911 23:03:15.933946
6912 23:03:15.936946 RX Delay -410 -> 252, step: 16
6913 23:03:15.940765 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6914 23:03:15.947386 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6915 23:03:15.950644 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6916 23:03:15.953795 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6917 23:03:15.957324 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6918 23:03:15.963667 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6919 23:03:15.967347 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6920 23:03:15.970563 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6921 23:03:15.973686 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6922 23:03:15.980046 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6923 23:03:15.983983 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6924 23:03:15.986692 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6925 23:03:15.990141 iDelay=230, Bit 12, Center -35 (-298 ~ 229) 528
6926 23:03:15.996799 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6927 23:03:16.000134 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6928 23:03:16.003378 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6929 23:03:16.003478 ==
6930 23:03:16.006706 Dram Type= 6, Freq= 0, CH_1, rank 1
6931 23:03:16.013833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6932 23:03:16.013938 ==
6933 23:03:16.014030 DQS Delay:
6934 23:03:16.017020 DQS0 = 59, DQS1 = 67
6935 23:03:16.017097 DQM Delay:
6936 23:03:16.017159 DQM0 = 19, DQM1 = 22
6937 23:03:16.020208 DQ Delay:
6938 23:03:16.023742 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6939 23:03:16.026950 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6940 23:03:16.027024 DQ8 =0, DQ9 =8, DQ10 =24, DQ11 =16
6941 23:03:16.030270 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =32
6942 23:03:16.033488
6943 23:03:16.033589
6944 23:03:16.033678 ==
6945 23:03:16.036678 Dram Type= 6, Freq= 0, CH_1, rank 1
6946 23:03:16.040330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6947 23:03:16.040403 ==
6948 23:03:16.040465
6949 23:03:16.040523
6950 23:03:16.043442 TX Vref Scan disable
6951 23:03:16.043518 == TX Byte 0 ==
6952 23:03:16.046694 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6953 23:03:16.053575 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6954 23:03:16.053650 == TX Byte 1 ==
6955 23:03:16.057177 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6956 23:03:16.063235 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6957 23:03:16.063340 ==
6958 23:03:16.066535 Dram Type= 6, Freq= 0, CH_1, rank 1
6959 23:03:16.069787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6960 23:03:16.069887 ==
6961 23:03:16.069979
6962 23:03:16.070066
6963 23:03:16.073289 TX Vref Scan disable
6964 23:03:16.073368 == TX Byte 0 ==
6965 23:03:16.076574 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6966 23:03:16.082998 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6967 23:03:16.083131 == TX Byte 1 ==
6968 23:03:16.086779 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6969 23:03:16.093008 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6970 23:03:16.093109
6971 23:03:16.093209 [DATLAT]
6972 23:03:16.093300 Freq=400, CH1 RK1
6973 23:03:16.096595
6974 23:03:16.096702 DATLAT Default: 0xe
6975 23:03:16.099895 0, 0xFFFF, sum = 0
6976 23:03:16.100006 1, 0xFFFF, sum = 0
6977 23:03:16.102938 2, 0xFFFF, sum = 0
6978 23:03:16.103040 3, 0xFFFF, sum = 0
6979 23:03:16.106373 4, 0xFFFF, sum = 0
6980 23:03:16.106483 5, 0xFFFF, sum = 0
6981 23:03:16.109578 6, 0xFFFF, sum = 0
6982 23:03:16.109653 7, 0xFFFF, sum = 0
6983 23:03:16.112871 8, 0xFFFF, sum = 0
6984 23:03:16.112958 9, 0xFFFF, sum = 0
6985 23:03:16.116442 10, 0xFFFF, sum = 0
6986 23:03:16.116525 11, 0xFFFF, sum = 0
6987 23:03:16.119618 12, 0xFFFF, sum = 0
6988 23:03:16.119726 13, 0x0, sum = 1
6989 23:03:16.122710 14, 0x0, sum = 2
6990 23:03:16.122808 15, 0x0, sum = 3
6991 23:03:16.126157 16, 0x0, sum = 4
6992 23:03:16.126279 best_step = 14
6993 23:03:16.126382
6994 23:03:16.126479 ==
6995 23:03:16.129352 Dram Type= 6, Freq= 0, CH_1, rank 1
6996 23:03:16.135913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6997 23:03:16.136006 ==
6998 23:03:16.136071 RX Vref Scan: 0
6999 23:03:16.136132
7000 23:03:16.139499 RX Vref 0 -> 0, step: 1
7001 23:03:16.139608
7002 23:03:16.142898 RX Delay -375 -> 252, step: 8
7003 23:03:16.149435 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
7004 23:03:16.152867 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
7005 23:03:16.156083 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
7006 23:03:16.159371 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
7007 23:03:16.165629 iDelay=217, Bit 4, Center -48 (-303 ~ 208) 512
7008 23:03:16.169266 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
7009 23:03:16.172483 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
7010 23:03:16.175476 iDelay=217, Bit 7, Center -52 (-303 ~ 200) 504
7011 23:03:16.182284 iDelay=217, Bit 8, Center -68 (-327 ~ 192) 520
7012 23:03:16.185550 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
7013 23:03:16.189025 iDelay=217, Bit 10, Center -52 (-311 ~ 208) 520
7014 23:03:16.195837 iDelay=217, Bit 11, Center -60 (-319 ~ 200) 520
7015 23:03:16.198819 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
7016 23:03:16.202323 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
7017 23:03:16.205447 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
7018 23:03:16.212536 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
7019 23:03:16.212638 ==
7020 23:03:16.215242 Dram Type= 6, Freq= 0, CH_1, rank 1
7021 23:03:16.218871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7022 23:03:16.218981 ==
7023 23:03:16.219073 DQS Delay:
7024 23:03:16.222094 DQS0 = 60, DQS1 = 68
7025 23:03:16.222203 DQM Delay:
7026 23:03:16.225350 DQM0 = 12, DQM1 = 13
7027 23:03:16.225425 DQ Delay:
7028 23:03:16.228829 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
7029 23:03:16.231881 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
7030 23:03:16.235203 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
7031 23:03:16.238434 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
7032 23:03:16.238534
7033 23:03:16.238634
7034 23:03:16.244931 [DQSOSCAuto] RK1, (LSB)MR18= 0x7dae, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 394 ps
7035 23:03:16.248143 CH1 RK1: MR19=C0C, MR18=7DAE
7036 23:03:16.254944 CH1_RK1: MR19=0xC0C, MR18=0x7DAE, DQSOSC=388, MR23=63, INC=392, DEC=261
7037 23:03:16.258339 [RxdqsGatingPostProcess] freq 400
7038 23:03:16.265531 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7039 23:03:16.268573 best DQS0 dly(2T, 0.5T) = (0, 10)
7040 23:03:16.268695 best DQS1 dly(2T, 0.5T) = (0, 10)
7041 23:03:16.271936 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7042 23:03:16.274829 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7043 23:03:16.278128 best DQS0 dly(2T, 0.5T) = (0, 10)
7044 23:03:16.281835 best DQS1 dly(2T, 0.5T) = (0, 10)
7045 23:03:16.284933 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7046 23:03:16.287985 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7047 23:03:16.291608 Pre-setting of DQS Precalculation
7048 23:03:16.298016 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7049 23:03:16.304838 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7050 23:03:16.311711 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7051 23:03:16.311793
7052 23:03:16.311928
7053 23:03:16.315003 [Calibration Summary] 800 Mbps
7054 23:03:16.315117 CH 0, Rank 0
7055 23:03:16.317645 SW Impedance : PASS
7056 23:03:16.321287 DUTY Scan : NO K
7057 23:03:16.321392 ZQ Calibration : PASS
7058 23:03:16.324484 Jitter Meter : NO K
7059 23:03:16.328360 CBT Training : PASS
7060 23:03:16.328436 Write leveling : PASS
7061 23:03:16.331033 RX DQS gating : PASS
7062 23:03:16.334317 RX DQ/DQS(RDDQC) : PASS
7063 23:03:16.334420 TX DQ/DQS : PASS
7064 23:03:16.337652 RX DATLAT : PASS
7065 23:03:16.341132 RX DQ/DQS(Engine): PASS
7066 23:03:16.341236 TX OE : NO K
7067 23:03:16.341336 All Pass.
7068 23:03:16.344365
7069 23:03:16.344436 CH 0, Rank 1
7070 23:03:16.347743 SW Impedance : PASS
7071 23:03:16.347859 DUTY Scan : NO K
7072 23:03:16.350898 ZQ Calibration : PASS
7073 23:03:16.350999 Jitter Meter : NO K
7074 23:03:16.354878 CBT Training : PASS
7075 23:03:16.357897 Write leveling : NO K
7076 23:03:16.357999 RX DQS gating : PASS
7077 23:03:16.361058 RX DQ/DQS(RDDQC) : PASS
7078 23:03:16.364568 TX DQ/DQS : PASS
7079 23:03:16.364652 RX DATLAT : PASS
7080 23:03:16.367682 RX DQ/DQS(Engine): PASS
7081 23:03:16.370928 TX OE : NO K
7082 23:03:16.371028 All Pass.
7083 23:03:16.371117
7084 23:03:16.371203 CH 1, Rank 0
7085 23:03:16.374004 SW Impedance : PASS
7086 23:03:16.377624 DUTY Scan : NO K
7087 23:03:16.377710 ZQ Calibration : PASS
7088 23:03:16.380774 Jitter Meter : NO K
7089 23:03:16.384382 CBT Training : PASS
7090 23:03:16.384458 Write leveling : PASS
7091 23:03:16.387323 RX DQS gating : PASS
7092 23:03:16.390748 RX DQ/DQS(RDDQC) : PASS
7093 23:03:16.390821 TX DQ/DQS : PASS
7094 23:03:16.394260 RX DATLAT : PASS
7095 23:03:16.397633 RX DQ/DQS(Engine): PASS
7096 23:03:16.397723 TX OE : NO K
7097 23:03:16.400602 All Pass.
7098 23:03:16.400673
7099 23:03:16.400734 CH 1, Rank 1
7100 23:03:16.404089 SW Impedance : PASS
7101 23:03:16.404186 DUTY Scan : NO K
7102 23:03:16.407344 ZQ Calibration : PASS
7103 23:03:16.410595 Jitter Meter : NO K
7104 23:03:16.410672 CBT Training : PASS
7105 23:03:16.413873 Write leveling : NO K
7106 23:03:16.413947 RX DQS gating : PASS
7107 23:03:16.417238 RX DQ/DQS(RDDQC) : PASS
7108 23:03:16.420465 TX DQ/DQS : PASS
7109 23:03:16.420539 RX DATLAT : PASS
7110 23:03:16.424335 RX DQ/DQS(Engine): PASS
7111 23:03:16.427092 TX OE : NO K
7112 23:03:16.427191 All Pass.
7113 23:03:16.427280
7114 23:03:16.430451 DramC Write-DBI off
7115 23:03:16.430563 PER_BANK_REFRESH: Hybrid Mode
7116 23:03:16.433733 TX_TRACKING: ON
7117 23:03:16.443635 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7118 23:03:16.447330 [FAST_K] Save calibration result to emmc
7119 23:03:16.450311 dramc_set_vcore_voltage set vcore to 725000
7120 23:03:16.450415 Read voltage for 1600, 0
7121 23:03:16.453502 Vio18 = 0
7122 23:03:16.453608 Vcore = 725000
7123 23:03:16.453699 Vdram = 0
7124 23:03:16.457078 Vddq = 0
7125 23:03:16.457151 Vmddr = 0
7126 23:03:16.463911 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7127 23:03:16.467083 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7128 23:03:16.470289 MEM_TYPE=3, freq_sel=13
7129 23:03:16.473616 sv_algorithm_assistance_LP4_3733
7130 23:03:16.476669 ============ PULL DRAM RESETB DOWN ============
7131 23:03:16.480358 ========== PULL DRAM RESETB DOWN end =========
7132 23:03:16.486573 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7133 23:03:16.490090 ===================================
7134 23:03:16.490167 LPDDR4 DRAM CONFIGURATION
7135 23:03:16.493228 ===================================
7136 23:03:16.496685 EX_ROW_EN[0] = 0x0
7137 23:03:16.500100 EX_ROW_EN[1] = 0x0
7138 23:03:16.500206 LP4Y_EN = 0x0
7139 23:03:16.503106 WORK_FSP = 0x1
7140 23:03:16.503204 WL = 0x5
7141 23:03:16.506575 RL = 0x5
7142 23:03:16.506688 BL = 0x2
7143 23:03:16.509713 RPST = 0x0
7144 23:03:16.509791 RD_PRE = 0x0
7145 23:03:16.513530 WR_PRE = 0x1
7146 23:03:16.513620 WR_PST = 0x1
7147 23:03:16.516619 DBI_WR = 0x0
7148 23:03:16.516693 DBI_RD = 0x0
7149 23:03:16.519674 OTF = 0x1
7150 23:03:16.523400 ===================================
7151 23:03:16.526599 ===================================
7152 23:03:16.526705 ANA top config
7153 23:03:16.529761 ===================================
7154 23:03:16.533021 DLL_ASYNC_EN = 0
7155 23:03:16.536570 ALL_SLAVE_EN = 0
7156 23:03:16.536669 NEW_RANK_MODE = 1
7157 23:03:16.539607 DLL_IDLE_MODE = 1
7158 23:03:16.542980 LP45_APHY_COMB_EN = 1
7159 23:03:16.546675 TX_ODT_DIS = 0
7160 23:03:16.549949 NEW_8X_MODE = 1
7161 23:03:16.553386 ===================================
7162 23:03:16.556621 ===================================
7163 23:03:16.556721 data_rate = 3200
7164 23:03:16.559576 CKR = 1
7165 23:03:16.563039 DQ_P2S_RATIO = 8
7166 23:03:16.566349 ===================================
7167 23:03:16.570029 CA_P2S_RATIO = 8
7168 23:03:16.572812 DQ_CA_OPEN = 0
7169 23:03:16.576495 DQ_SEMI_OPEN = 0
7170 23:03:16.576602 CA_SEMI_OPEN = 0
7171 23:03:16.579829 CA_FULL_RATE = 0
7172 23:03:16.583027 DQ_CKDIV4_EN = 0
7173 23:03:16.586170 CA_CKDIV4_EN = 0
7174 23:03:16.589474 CA_PREDIV_EN = 0
7175 23:03:16.592903 PH8_DLY = 12
7176 23:03:16.593006 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7177 23:03:16.596407 DQ_AAMCK_DIV = 4
7178 23:03:16.599655 CA_AAMCK_DIV = 4
7179 23:03:16.602977 CA_ADMCK_DIV = 4
7180 23:03:16.606263 DQ_TRACK_CA_EN = 0
7181 23:03:16.609393 CA_PICK = 1600
7182 23:03:16.612725 CA_MCKIO = 1600
7183 23:03:16.612827 MCKIO_SEMI = 0
7184 23:03:16.615892 PLL_FREQ = 3068
7185 23:03:16.619447 DQ_UI_PI_RATIO = 32
7186 23:03:16.622767 CA_UI_PI_RATIO = 0
7187 23:03:16.626174 ===================================
7188 23:03:16.629159 ===================================
7189 23:03:16.632945 memory_type:LPDDR4
7190 23:03:16.633044 GP_NUM : 10
7191 23:03:16.636012 SRAM_EN : 1
7192 23:03:16.639432 MD32_EN : 0
7193 23:03:16.642578 ===================================
7194 23:03:16.642652 [ANA_INIT] >>>>>>>>>>>>>>
7195 23:03:16.645680 <<<<<< [CONFIGURE PHASE]: ANA_TX
7196 23:03:16.648863 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7197 23:03:16.652872 ===================================
7198 23:03:16.655951 data_rate = 3200,PCW = 0X7600
7199 23:03:16.658824 ===================================
7200 23:03:16.662196 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7201 23:03:16.669369 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7202 23:03:16.672136 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7203 23:03:16.679084 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7204 23:03:16.681956 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7205 23:03:16.685541 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7206 23:03:16.688749 [ANA_INIT] flow start
7207 23:03:16.688826 [ANA_INIT] PLL >>>>>>>>
7208 23:03:16.691938 [ANA_INIT] PLL <<<<<<<<
7209 23:03:16.695242 [ANA_INIT] MIDPI >>>>>>>>
7210 23:03:16.695343 [ANA_INIT] MIDPI <<<<<<<<
7211 23:03:16.698523 [ANA_INIT] DLL >>>>>>>>
7212 23:03:16.701872 [ANA_INIT] DLL <<<<<<<<
7213 23:03:16.701952 [ANA_INIT] flow end
7214 23:03:16.708421 ============ LP4 DIFF to SE enter ============
7215 23:03:16.711698 ============ LP4 DIFF to SE exit ============
7216 23:03:16.711772 [ANA_INIT] <<<<<<<<<<<<<
7217 23:03:16.715526 [Flow] Enable top DCM control >>>>>
7218 23:03:16.718382 [Flow] Enable top DCM control <<<<<
7219 23:03:16.721818 Enable DLL master slave shuffle
7220 23:03:16.728340 ==============================================================
7221 23:03:16.732034 Gating Mode config
7222 23:03:16.734991 ==============================================================
7223 23:03:16.738704 Config description:
7224 23:03:16.748741 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7225 23:03:16.755184 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7226 23:03:16.758337 SELPH_MODE 0: By rank 1: By Phase
7227 23:03:16.764795 ==============================================================
7228 23:03:16.768552 GAT_TRACK_EN = 1
7229 23:03:16.771817 RX_GATING_MODE = 2
7230 23:03:16.771916 RX_GATING_TRACK_MODE = 2
7231 23:03:16.774951 SELPH_MODE = 1
7232 23:03:16.778251 PICG_EARLY_EN = 1
7233 23:03:16.781706 VALID_LAT_VALUE = 1
7234 23:03:16.788701 ==============================================================
7235 23:03:16.791460 Enter into Gating configuration >>>>
7236 23:03:16.794965 Exit from Gating configuration <<<<
7237 23:03:16.798033 Enter into DVFS_PRE_config >>>>>
7238 23:03:16.808260 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7239 23:03:16.811198 Exit from DVFS_PRE_config <<<<<
7240 23:03:16.815096 Enter into PICG configuration >>>>
7241 23:03:16.817989 Exit from PICG configuration <<<<
7242 23:03:16.821660 [RX_INPUT] configuration >>>>>
7243 23:03:16.825061 [RX_INPUT] configuration <<<<<
7244 23:03:16.828118 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7245 23:03:16.835049 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7246 23:03:16.841405 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7247 23:03:16.848234 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7248 23:03:16.851511 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7249 23:03:16.857775 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7250 23:03:16.861226 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7251 23:03:16.867957 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7252 23:03:16.871415 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7253 23:03:16.874557 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7254 23:03:16.877871 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7255 23:03:16.884575 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7256 23:03:16.887715 ===================================
7257 23:03:16.891056 LPDDR4 DRAM CONFIGURATION
7258 23:03:16.894311 ===================================
7259 23:03:16.894411 EX_ROW_EN[0] = 0x0
7260 23:03:16.897562 EX_ROW_EN[1] = 0x0
7261 23:03:16.897636 LP4Y_EN = 0x0
7262 23:03:16.900946 WORK_FSP = 0x1
7263 23:03:16.901043 WL = 0x5
7264 23:03:16.904378 RL = 0x5
7265 23:03:16.904486 BL = 0x2
7266 23:03:16.907498 RPST = 0x0
7267 23:03:16.907599 RD_PRE = 0x0
7268 23:03:16.910775 WR_PRE = 0x1
7269 23:03:16.910851 WR_PST = 0x1
7270 23:03:16.914138 DBI_WR = 0x0
7271 23:03:16.914212 DBI_RD = 0x0
7272 23:03:16.917345 OTF = 0x1
7273 23:03:16.921421 ===================================
7274 23:03:16.924297 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7275 23:03:16.927472 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7276 23:03:16.934299 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7277 23:03:16.937559 ===================================
7278 23:03:16.937661 LPDDR4 DRAM CONFIGURATION
7279 23:03:16.940843 ===================================
7280 23:03:16.944148 EX_ROW_EN[0] = 0x10
7281 23:03:16.947379 EX_ROW_EN[1] = 0x0
7282 23:03:16.947489 LP4Y_EN = 0x0
7283 23:03:16.950733 WORK_FSP = 0x1
7284 23:03:16.950809 WL = 0x5
7285 23:03:16.954175 RL = 0x5
7286 23:03:16.954249 BL = 0x2
7287 23:03:16.957480 RPST = 0x0
7288 23:03:16.957561 RD_PRE = 0x0
7289 23:03:16.960539 WR_PRE = 0x1
7290 23:03:16.960638 WR_PST = 0x1
7291 23:03:16.963904 DBI_WR = 0x0
7292 23:03:16.964011 DBI_RD = 0x0
7293 23:03:16.967716 OTF = 0x1
7294 23:03:16.970573 ===================================
7295 23:03:16.977199 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7296 23:03:16.977311 ==
7297 23:03:16.980658 Dram Type= 6, Freq= 0, CH_0, rank 0
7298 23:03:16.983672 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7299 23:03:16.983772 ==
7300 23:03:16.987401 [Duty_Offset_Calibration]
7301 23:03:16.987500 B0:2 B1:0 CA:3
7302 23:03:16.987589
7303 23:03:16.990156 [DutyScan_Calibration_Flow] k_type=0
7304 23:03:17.001305
7305 23:03:17.001383 ==CLK 0==
7306 23:03:17.004607 Final CLK duty delay cell = 0
7307 23:03:17.007968 [0] MAX Duty = 5031%(X100), DQS PI = 14
7308 23:03:17.011188 [0] MIN Duty = 4907%(X100), DQS PI = 6
7309 23:03:17.011289 [0] AVG Duty = 4969%(X100)
7310 23:03:17.014751
7311 23:03:17.017923 CH0 CLK Duty spec in!! Max-Min= 124%
7312 23:03:17.021458 [DutyScan_Calibration_Flow] ====Done====
7313 23:03:17.021559
7314 23:03:17.024359 [DutyScan_Calibration_Flow] k_type=1
7315 23:03:17.041189
7316 23:03:17.041291 ==DQS 0 ==
7317 23:03:17.044484 Final DQS duty delay cell = 0
7318 23:03:17.047876 [0] MAX Duty = 5094%(X100), DQS PI = 30
7319 23:03:17.051431 [0] MIN Duty = 4875%(X100), DQS PI = 48
7320 23:03:17.054526 [0] AVG Duty = 4984%(X100)
7321 23:03:17.054606
7322 23:03:17.054668 ==DQS 1 ==
7323 23:03:17.057987 Final DQS duty delay cell = 0
7324 23:03:17.061044 [0] MAX Duty = 5156%(X100), DQS PI = 32
7325 23:03:17.064532 [0] MIN Duty = 5062%(X100), DQS PI = 8
7326 23:03:17.067886 [0] AVG Duty = 5109%(X100)
7327 23:03:17.067990
7328 23:03:17.071338 CH0 DQS 0 Duty spec in!! Max-Min= 219%
7329 23:03:17.071430
7330 23:03:17.074578 CH0 DQS 1 Duty spec in!! Max-Min= 94%
7331 23:03:17.077865 [DutyScan_Calibration_Flow] ====Done====
7332 23:03:17.077967
7333 23:03:17.081083 [DutyScan_Calibration_Flow] k_type=3
7334 23:03:17.099128
7335 23:03:17.099229 ==DQM 0 ==
7336 23:03:17.102438 Final DQM duty delay cell = 0
7337 23:03:17.106184 [0] MAX Duty = 5187%(X100), DQS PI = 32
7338 23:03:17.109241 [0] MIN Duty = 4875%(X100), DQS PI = 0
7339 23:03:17.112488 [0] AVG Duty = 5031%(X100)
7340 23:03:17.112572
7341 23:03:17.112637 ==DQM 1 ==
7342 23:03:17.115861 Final DQM duty delay cell = 4
7343 23:03:17.119224 [4] MAX Duty = 5187%(X100), DQS PI = 62
7344 23:03:17.122424 [4] MIN Duty = 5000%(X100), DQS PI = 14
7345 23:03:17.125832 [4] AVG Duty = 5093%(X100)
7346 23:03:17.125937
7347 23:03:17.129363 CH0 DQM 0 Duty spec in!! Max-Min= 312%
7348 23:03:17.129458
7349 23:03:17.132625 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7350 23:03:17.135889 [DutyScan_Calibration_Flow] ====Done====
7351 23:03:17.135963
7352 23:03:17.139182 [DutyScan_Calibration_Flow] k_type=2
7353 23:03:17.155663
7354 23:03:17.155737 ==DQ 0 ==
7355 23:03:17.159283 Final DQ duty delay cell = -4
7356 23:03:17.162069 [-4] MAX Duty = 5000%(X100), DQS PI = 12
7357 23:03:17.165700 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7358 23:03:17.168940 [-4] AVG Duty = 4938%(X100)
7359 23:03:17.169044
7360 23:03:17.169135 ==DQ 1 ==
7361 23:03:17.171929 Final DQ duty delay cell = 0
7362 23:03:17.175292 [0] MAX Duty = 5156%(X100), DQS PI = 58
7363 23:03:17.178958 [0] MIN Duty = 5000%(X100), DQS PI = 16
7364 23:03:17.182001 [0] AVG Duty = 5078%(X100)
7365 23:03:17.182101
7366 23:03:17.185182 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7367 23:03:17.185252
7368 23:03:17.188790 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7369 23:03:17.192113 [DutyScan_Calibration_Flow] ====Done====
7370 23:03:17.192233 ==
7371 23:03:17.195032 Dram Type= 6, Freq= 0, CH_1, rank 0
7372 23:03:17.198745 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7373 23:03:17.198852 ==
7374 23:03:17.202041 [Duty_Offset_Calibration]
7375 23:03:17.202114 B0:1 B1:-2 CA:1
7376 23:03:17.202175
7377 23:03:17.205330 [DutyScan_Calibration_Flow] k_type=0
7378 23:03:17.216437
7379 23:03:17.216513 ==CLK 0==
7380 23:03:17.219228 Final CLK duty delay cell = 0
7381 23:03:17.222923 [0] MAX Duty = 5094%(X100), DQS PI = 22
7382 23:03:17.226215 [0] MIN Duty = 4844%(X100), DQS PI = 0
7383 23:03:17.226316 [0] AVG Duty = 4969%(X100)
7384 23:03:17.226406
7385 23:03:17.229374 CH1 CLK Duty spec in!! Max-Min= 250%
7386 23:03:17.236075 [DutyScan_Calibration_Flow] ====Done====
7387 23:03:17.236175
7388 23:03:17.239458 [DutyScan_Calibration_Flow] k_type=1
7389 23:03:17.255931
7390 23:03:17.256030 ==DQS 0 ==
7391 23:03:17.259058 Final DQS duty delay cell = 0
7392 23:03:17.262804 [0] MAX Duty = 5187%(X100), DQS PI = 24
7393 23:03:17.265908 [0] MIN Duty = 5062%(X100), DQS PI = 48
7394 23:03:17.269360 [0] AVG Duty = 5124%(X100)
7395 23:03:17.269433
7396 23:03:17.269495 ==DQS 1 ==
7397 23:03:17.272149 Final DQS duty delay cell = 0
7398 23:03:17.275469 [0] MAX Duty = 5093%(X100), DQS PI = 62
7399 23:03:17.278942 [0] MIN Duty = 4844%(X100), DQS PI = 26
7400 23:03:17.282246 [0] AVG Duty = 4968%(X100)
7401 23:03:17.282348
7402 23:03:17.285506 CH1 DQS 0 Duty spec in!! Max-Min= 125%
7403 23:03:17.285607
7404 23:03:17.289092 CH1 DQS 1 Duty spec in!! Max-Min= 249%
7405 23:03:17.292467 [DutyScan_Calibration_Flow] ====Done====
7406 23:03:17.292545
7407 23:03:17.295458 [DutyScan_Calibration_Flow] k_type=3
7408 23:03:17.312887
7409 23:03:17.312979 ==DQM 0 ==
7410 23:03:17.316024 Final DQM duty delay cell = 0
7411 23:03:17.319344 [0] MAX Duty = 5031%(X100), DQS PI = 24
7412 23:03:17.322602 [0] MIN Duty = 4813%(X100), DQS PI = 54
7413 23:03:17.325965 [0] AVG Duty = 4922%(X100)
7414 23:03:17.326046
7415 23:03:17.326110 ==DQM 1 ==
7416 23:03:17.329250 Final DQM duty delay cell = 0
7417 23:03:17.332581 [0] MAX Duty = 5062%(X100), DQS PI = 34
7418 23:03:17.335933 [0] MIN Duty = 4875%(X100), DQS PI = 24
7419 23:03:17.339560 [0] AVG Duty = 4968%(X100)
7420 23:03:17.339641
7421 23:03:17.342572 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7422 23:03:17.342647
7423 23:03:17.345992 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7424 23:03:17.349313 [DutyScan_Calibration_Flow] ====Done====
7425 23:03:17.349411
7426 23:03:17.352343 [DutyScan_Calibration_Flow] k_type=2
7427 23:03:17.369716
7428 23:03:17.369819 ==DQ 0 ==
7429 23:03:17.372811 Final DQ duty delay cell = 0
7430 23:03:17.376464 [0] MAX Duty = 5093%(X100), DQS PI = 22
7431 23:03:17.379782 [0] MIN Duty = 4907%(X100), DQS PI = 62
7432 23:03:17.379888 [0] AVG Duty = 5000%(X100)
7433 23:03:17.382768
7434 23:03:17.382875 ==DQ 1 ==
7435 23:03:17.386561 Final DQ duty delay cell = 0
7436 23:03:17.389837 [0] MAX Duty = 5125%(X100), DQS PI = 34
7437 23:03:17.392877 [0] MIN Duty = 4969%(X100), DQS PI = 24
7438 23:03:17.392982 [0] AVG Duty = 5047%(X100)
7439 23:03:17.393075
7440 23:03:17.399371 CH1 DQ 0 Duty spec in!! Max-Min= 186%
7441 23:03:17.399463
7442 23:03:17.402725 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7443 23:03:17.406376 [DutyScan_Calibration_Flow] ====Done====
7444 23:03:17.409540 nWR fixed to 30
7445 23:03:17.409643 [ModeRegInit_LP4] CH0 RK0
7446 23:03:17.412867 [ModeRegInit_LP4] CH0 RK1
7447 23:03:17.416218 [ModeRegInit_LP4] CH1 RK0
7448 23:03:17.419558 [ModeRegInit_LP4] CH1 RK1
7449 23:03:17.419636 match AC timing 5
7450 23:03:17.423069 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7451 23:03:17.429176 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7452 23:03:17.432468 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7453 23:03:17.439412 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7454 23:03:17.442341 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7455 23:03:17.442443 [MiockJmeterHQA]
7456 23:03:17.442536
7457 23:03:17.445826 [DramcMiockJmeter] u1RxGatingPI = 0
7458 23:03:17.449109 0 : 4363, 4137
7459 23:03:17.449189 4 : 4255, 4030
7460 23:03:17.452732 8 : 4252, 4027
7461 23:03:17.452807 12 : 4252, 4027
7462 23:03:17.452869 16 : 4253, 4027
7463 23:03:17.456017 20 : 4363, 4137
7464 23:03:17.456122 24 : 4363, 4138
7465 23:03:17.458931 28 : 4252, 4027
7466 23:03:17.459035 32 : 4252, 4027
7467 23:03:17.462444 36 : 4253, 4027
7468 23:03:17.462605 40 : 4252, 4027
7469 23:03:17.465461 44 : 4252, 4027
7470 23:03:17.465537 48 : 4363, 4137
7471 23:03:17.465600 52 : 4252, 4027
7472 23:03:17.468758 56 : 4252, 4029
7473 23:03:17.468826 60 : 4250, 4027
7474 23:03:17.472071 64 : 4250, 4027
7475 23:03:17.472169 68 : 4250, 4027
7476 23:03:17.475676 72 : 4361, 4137
7477 23:03:17.475748 76 : 4360, 4138
7478 23:03:17.479153 80 : 4255, 4029
7479 23:03:17.479235 84 : 4250, 4027
7480 23:03:17.479301 88 : 4250, 4027
7481 23:03:17.482473 92 : 4250, 4027
7482 23:03:17.482563 96 : 4250, 4027
7483 23:03:17.485814 100 : 4361, 4137
7484 23:03:17.485883 104 : 4250, 3793
7485 23:03:17.488765 108 : 4250, 13
7486 23:03:17.488837 112 : 4361, 0
7487 23:03:17.488898 116 : 4360, 0
7488 23:03:17.491950 120 : 4252, 0
7489 23:03:17.492020 124 : 4252, 0
7490 23:03:17.495587 128 : 4250, 0
7491 23:03:17.495665 132 : 4250, 0
7492 23:03:17.495728 136 : 4250, 0
7493 23:03:17.498869 140 : 4250, 0
7494 23:03:17.498947 144 : 4250, 0
7495 23:03:17.502178 148 : 4250, 0
7496 23:03:17.502247 152 : 4250, 0
7497 23:03:17.502314 156 : 4250, 0
7498 23:03:17.505332 160 : 4361, 0
7499 23:03:17.505401 164 : 4250, 0
7500 23:03:17.508840 168 : 4360, 0
7501 23:03:17.508922 172 : 4249, 0
7502 23:03:17.508985 176 : 4361, 0
7503 23:03:17.511956 180 : 4361, 0
7504 23:03:17.512030 184 : 4250, 0
7505 23:03:17.512092 188 : 4250, 0
7506 23:03:17.515329 192 : 4250, 0
7507 23:03:17.515396 196 : 4253, 0
7508 23:03:17.518389 200 : 4250, 0
7509 23:03:17.518462 204 : 4250, 0
7510 23:03:17.518522 208 : 4250, 0
7511 23:03:17.522194 212 : 4360, 0
7512 23:03:17.522261 216 : 4361, 0
7513 23:03:17.525280 220 : 4250, 0
7514 23:03:17.525346 224 : 4250, 0
7515 23:03:17.525405 228 : 4361, 0
7516 23:03:17.528504 232 : 4250, 0
7517 23:03:17.528574 236 : 4249, 895
7518 23:03:17.532179 240 : 4250, 4027
7519 23:03:17.532273 244 : 4250, 4027
7520 23:03:17.535200 248 : 4360, 4138
7521 23:03:17.535297 252 : 4250, 4027
7522 23:03:17.538618 256 : 4250, 4027
7523 23:03:17.538687 260 : 4361, 4137
7524 23:03:17.538746 264 : 4250, 4027
7525 23:03:17.541916 268 : 4250, 4027
7526 23:03:17.541990 272 : 4360, 4137
7527 23:03:17.545093 276 : 4250, 4027
7528 23:03:17.545179 280 : 4250, 4027
7529 23:03:17.548516 284 : 4250, 4027
7530 23:03:17.548628 288 : 4250, 4027
7531 23:03:17.551683 292 : 4250, 4027
7532 23:03:17.551771 296 : 4250, 4027
7533 23:03:17.554891 300 : 4360, 4138
7534 23:03:17.554979 304 : 4250, 4027
7535 23:03:17.558458 308 : 4250, 4026
7536 23:03:17.558533 312 : 4361, 4137
7537 23:03:17.561921 316 : 4250, 4027
7538 23:03:17.562008 320 : 4250, 4027
7539 23:03:17.564959 324 : 4360, 4137
7540 23:03:17.565077 328 : 4250, 4027
7541 23:03:17.565201 332 : 4250, 4027
7542 23:03:17.568088 336 : 4249, 4027
7543 23:03:17.568195 340 : 4250, 4027
7544 23:03:17.571861 344 : 4250, 4027
7545 23:03:17.571988 348 : 4250, 4027
7546 23:03:17.575052 352 : 4361, 4132
7547 23:03:17.575152 356 : 4250, 2924
7548 23:03:17.578556 360 : 4250, 2
7549 23:03:17.578658
7550 23:03:17.578746 MIOCK jitter meter ch=0
7551 23:03:17.578831
7552 23:03:17.581457 1T = (360-108) = 252 dly cells
7553 23:03:17.588429 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7554 23:03:17.588509 ==
7555 23:03:17.591691 Dram Type= 6, Freq= 0, CH_0, rank 0
7556 23:03:17.594915 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7557 23:03:17.595019 ==
7558 23:03:17.601401 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7559 23:03:17.604495 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7560 23:03:17.607816 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7561 23:03:17.614643 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7562 23:03:17.624703 [CA 0] Center 44 (14~75) winsize 62
7563 23:03:17.627870 [CA 1] Center 43 (13~74) winsize 62
7564 23:03:17.631141 [CA 2] Center 39 (10~69) winsize 60
7565 23:03:17.635121 [CA 3] Center 39 (10~68) winsize 59
7566 23:03:17.637744 [CA 4] Center 37 (8~67) winsize 60
7567 23:03:17.641556 [CA 5] Center 37 (7~67) winsize 61
7568 23:03:17.641649
7569 23:03:17.644817 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7570 23:03:17.644885
7571 23:03:17.647783 [CATrainingPosCal] consider 1 rank data
7572 23:03:17.651091 u2DelayCellTimex100 = 258/100 ps
7573 23:03:17.657627 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7574 23:03:17.660960 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7575 23:03:17.664373 CA2 delay=39 (10~69),Diff = 2 PI (7 cell)
7576 23:03:17.668033 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7577 23:03:17.671048 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7578 23:03:17.674464 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7579 23:03:17.674557
7580 23:03:17.677927 CA PerBit enable=1, Macro0, CA PI delay=37
7581 23:03:17.678028
7582 23:03:17.680930 [CBTSetCACLKResult] CA Dly = 37
7583 23:03:17.684835 CS Dly: 11 (0~42)
7584 23:03:17.687915 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7585 23:03:17.690911 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7586 23:03:17.690985 ==
7587 23:03:17.694597 Dram Type= 6, Freq= 0, CH_0, rank 1
7588 23:03:17.701037 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7589 23:03:17.701117 ==
7590 23:03:17.704445 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7591 23:03:17.707369 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7592 23:03:17.714123 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7593 23:03:17.720931 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7594 23:03:17.728666 [CA 0] Center 44 (13~75) winsize 63
7595 23:03:17.731669 [CA 1] Center 43 (13~74) winsize 62
7596 23:03:17.734922 [CA 2] Center 39 (10~69) winsize 60
7597 23:03:17.738114 [CA 3] Center 39 (10~68) winsize 59
7598 23:03:17.741490 [CA 4] Center 37 (8~67) winsize 60
7599 23:03:17.744722 [CA 5] Center 37 (8~66) winsize 59
7600 23:03:17.744794
7601 23:03:17.748300 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7602 23:03:17.748371
7603 23:03:17.755154 [CATrainingPosCal] consider 2 rank data
7604 23:03:17.755254 u2DelayCellTimex100 = 258/100 ps
7605 23:03:17.761391 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7606 23:03:17.764849 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7607 23:03:17.768106 CA2 delay=39 (10~69),Diff = 2 PI (7 cell)
7608 23:03:17.771471 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7609 23:03:17.774951 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7610 23:03:17.778194 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
7611 23:03:17.778300
7612 23:03:17.781188 CA PerBit enable=1, Macro0, CA PI delay=37
7613 23:03:17.781292
7614 23:03:17.784458 [CBTSetCACLKResult] CA Dly = 37
7615 23:03:17.788072 CS Dly: 11 (0~43)
7616 23:03:17.791030 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7617 23:03:17.794571 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7618 23:03:17.794642
7619 23:03:17.797820 ----->DramcWriteLeveling(PI) begin...
7620 23:03:17.797917 ==
7621 23:03:17.801057 Dram Type= 6, Freq= 0, CH_0, rank 0
7622 23:03:17.807732 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7623 23:03:17.807817 ==
7624 23:03:17.810962 Write leveling (Byte 0): 36 => 36
7625 23:03:17.814160 Write leveling (Byte 1): 27 => 27
7626 23:03:17.817394 DramcWriteLeveling(PI) end<-----
7627 23:03:17.817497
7628 23:03:17.817591 ==
7629 23:03:17.821233 Dram Type= 6, Freq= 0, CH_0, rank 0
7630 23:03:17.824390 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7631 23:03:17.824459 ==
7632 23:03:17.827468 [Gating] SW mode calibration
7633 23:03:17.833911 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7634 23:03:17.837697 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7635 23:03:17.844137 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7636 23:03:17.847458 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7637 23:03:17.850651 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7638 23:03:17.857499 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7639 23:03:17.860781 1 4 16 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
7640 23:03:17.863725 1 4 20 | B1->B0 | 2626 3333 | 0 1 | (0 0) (1 1)
7641 23:03:17.870855 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7642 23:03:17.873937 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7643 23:03:17.877137 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7644 23:03:17.883774 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7645 23:03:17.886949 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7646 23:03:17.890637 1 5 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
7647 23:03:17.897380 1 5 16 | B1->B0 | 3434 2c2c | 1 1 | (1 1) (1 0)
7648 23:03:17.900380 1 5 20 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 0)
7649 23:03:17.903650 1 5 24 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
7650 23:03:17.910480 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7651 23:03:17.913974 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7652 23:03:17.916843 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7653 23:03:17.924156 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7654 23:03:17.927122 1 6 12 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
7655 23:03:17.930582 1 6 16 | B1->B0 | 2323 4040 | 0 0 | (0 0) (0 0)
7656 23:03:17.937341 1 6 20 | B1->B0 | 2929 4646 | 1 0 | (0 0) (0 0)
7657 23:03:17.940189 1 6 24 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
7658 23:03:17.943334 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7659 23:03:17.950555 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7660 23:03:17.953658 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7661 23:03:17.956679 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7662 23:03:17.963531 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7663 23:03:17.966761 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7664 23:03:17.970452 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7665 23:03:17.976880 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7666 23:03:17.979935 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7667 23:03:17.983685 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7668 23:03:17.989937 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7669 23:03:17.993235 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7670 23:03:17.996362 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7671 23:03:18.003348 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7672 23:03:18.006394 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7673 23:03:18.009671 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7674 23:03:18.016616 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7675 23:03:18.019761 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7676 23:03:18.023057 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7677 23:03:18.029435 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7678 23:03:18.032994 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7679 23:03:18.036418 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7680 23:03:18.042763 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7681 23:03:18.042841 Total UI for P1: 0, mck2ui 16
7682 23:03:18.046599 best dqsien dly found for B0: ( 1, 9, 14)
7683 23:03:18.053288 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7684 23:03:18.056604 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7685 23:03:18.059632 Total UI for P1: 0, mck2ui 16
7686 23:03:18.062725 best dqsien dly found for B1: ( 1, 9, 24)
7687 23:03:18.066343 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7688 23:03:18.069664 best DQS1 dly(MCK, UI, PI) = (1, 9, 24)
7689 23:03:18.069739
7690 23:03:18.072738 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7691 23:03:18.079436 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 24)
7692 23:03:18.079513 [Gating] SW calibration Done
7693 23:03:18.079577 ==
7694 23:03:18.083080 Dram Type= 6, Freq= 0, CH_0, rank 0
7695 23:03:18.089633 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7696 23:03:18.089710 ==
7697 23:03:18.089781 RX Vref Scan: 0
7698 23:03:18.089845
7699 23:03:18.092827 RX Vref 0 -> 0, step: 1
7700 23:03:18.092899
7701 23:03:18.096219 RX Delay 0 -> 252, step: 8
7702 23:03:18.099710 iDelay=192, Bit 0, Center 127 (72 ~ 183) 112
7703 23:03:18.102795 iDelay=192, Bit 1, Center 131 (80 ~ 183) 104
7704 23:03:18.106027 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7705 23:03:18.109323 iDelay=192, Bit 3, Center 119 (64 ~ 175) 112
7706 23:03:18.116186 iDelay=192, Bit 4, Center 127 (72 ~ 183) 112
7707 23:03:18.119049 iDelay=192, Bit 5, Center 115 (64 ~ 167) 104
7708 23:03:18.122656 iDelay=192, Bit 6, Center 135 (80 ~ 191) 112
7709 23:03:18.125869 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7710 23:03:18.129101 iDelay=192, Bit 8, Center 115 (56 ~ 175) 120
7711 23:03:18.135804 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7712 23:03:18.139031 iDelay=192, Bit 10, Center 123 (64 ~ 183) 120
7713 23:03:18.142250 iDelay=192, Bit 11, Center 115 (56 ~ 175) 120
7714 23:03:18.145896 iDelay=192, Bit 12, Center 127 (72 ~ 183) 112
7715 23:03:18.152105 iDelay=192, Bit 13, Center 131 (72 ~ 191) 120
7716 23:03:18.155552 iDelay=192, Bit 14, Center 131 (72 ~ 191) 120
7717 23:03:18.158791 iDelay=192, Bit 15, Center 131 (72 ~ 191) 120
7718 23:03:18.158865 ==
7719 23:03:18.161977 Dram Type= 6, Freq= 0, CH_0, rank 0
7720 23:03:18.165302 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7721 23:03:18.165376 ==
7722 23:03:18.169226 DQS Delay:
7723 23:03:18.169309 DQS0 = 0, DQS1 = 0
7724 23:03:18.172135 DQM Delay:
7725 23:03:18.172236 DQM0 = 127, DQM1 = 123
7726 23:03:18.175735 DQ Delay:
7727 23:03:18.178828 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =119
7728 23:03:18.181850 DQ4 =127, DQ5 =115, DQ6 =135, DQ7 =139
7729 23:03:18.185309 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =115
7730 23:03:18.188851 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =131
7731 23:03:18.188929
7732 23:03:18.188993
7733 23:03:18.189062 ==
7734 23:03:18.192121 Dram Type= 6, Freq= 0, CH_0, rank 0
7735 23:03:18.195513 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7736 23:03:18.195625 ==
7737 23:03:18.195718
7738 23:03:18.195817
7739 23:03:18.198730 TX Vref Scan disable
7740 23:03:18.201820 == TX Byte 0 ==
7741 23:03:18.205572 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
7742 23:03:18.208518 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7743 23:03:18.212057 == TX Byte 1 ==
7744 23:03:18.215031 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7745 23:03:18.218755 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7746 23:03:18.218855 ==
7747 23:03:18.222045 Dram Type= 6, Freq= 0, CH_0, rank 0
7748 23:03:18.228396 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7749 23:03:18.228495 ==
7750 23:03:18.241346
7751 23:03:18.244161 TX Vref early break, caculate TX vref
7752 23:03:18.247651 TX Vref=16, minBit 8, minWin=21, winSum=362
7753 23:03:18.251067 TX Vref=18, minBit 11, minWin=21, winSum=372
7754 23:03:18.254254 TX Vref=20, minBit 8, minWin=23, winSum=384
7755 23:03:18.257669 TX Vref=22, minBit 8, minWin=23, winSum=390
7756 23:03:18.261051 TX Vref=24, minBit 8, minWin=23, winSum=403
7757 23:03:18.267839 TX Vref=26, minBit 8, minWin=24, winSum=408
7758 23:03:18.270734 TX Vref=28, minBit 8, minWin=23, winSum=405
7759 23:03:18.273924 TX Vref=30, minBit 8, minWin=23, winSum=398
7760 23:03:18.277174 TX Vref=32, minBit 9, minWin=22, winSum=390
7761 23:03:18.280528 TX Vref=34, minBit 8, minWin=21, winSum=385
7762 23:03:18.287267 [TxChooseVref] Worse bit 8, Min win 24, Win sum 408, Final Vref 26
7763 23:03:18.287361
7764 23:03:18.290711 Final TX Range 0 Vref 26
7765 23:03:18.290809
7766 23:03:18.290898 ==
7767 23:03:18.293878 Dram Type= 6, Freq= 0, CH_0, rank 0
7768 23:03:18.297480 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7769 23:03:18.297581 ==
7770 23:03:18.297673
7771 23:03:18.297760
7772 23:03:18.300804 TX Vref Scan disable
7773 23:03:18.307018 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7774 23:03:18.307168 == TX Byte 0 ==
7775 23:03:18.310477 u2DelayCellOfst[0]=11 cells (3 PI)
7776 23:03:18.313581 u2DelayCellOfst[1]=15 cells (4 PI)
7777 23:03:18.317068 u2DelayCellOfst[2]=7 cells (2 PI)
7778 23:03:18.320408 u2DelayCellOfst[3]=11 cells (3 PI)
7779 23:03:18.323630 u2DelayCellOfst[4]=3 cells (1 PI)
7780 23:03:18.327571 u2DelayCellOfst[5]=0 cells (0 PI)
7781 23:03:18.330626 u2DelayCellOfst[6]=18 cells (5 PI)
7782 23:03:18.333854 u2DelayCellOfst[7]=15 cells (4 PI)
7783 23:03:18.337318 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7784 23:03:18.340616 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7785 23:03:18.343900 == TX Byte 1 ==
7786 23:03:18.343995 u2DelayCellOfst[8]=0 cells (0 PI)
7787 23:03:18.347127 u2DelayCellOfst[9]=3 cells (1 PI)
7788 23:03:18.350428 u2DelayCellOfst[10]=11 cells (3 PI)
7789 23:03:18.353530 u2DelayCellOfst[11]=7 cells (2 PI)
7790 23:03:18.356935 u2DelayCellOfst[12]=15 cells (4 PI)
7791 23:03:18.360065 u2DelayCellOfst[13]=15 cells (4 PI)
7792 23:03:18.363783 u2DelayCellOfst[14]=18 cells (5 PI)
7793 23:03:18.366911 u2DelayCellOfst[15]=15 cells (4 PI)
7794 23:03:18.370142 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7795 23:03:18.376971 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7796 23:03:18.377049 DramC Write-DBI on
7797 23:03:18.377113 ==
7798 23:03:18.380326 Dram Type= 6, Freq= 0, CH_0, rank 0
7799 23:03:18.386382 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7800 23:03:18.386473 ==
7801 23:03:18.386537
7802 23:03:18.386597
7803 23:03:18.386660 TX Vref Scan disable
7804 23:03:18.390723 == TX Byte 0 ==
7805 23:03:18.394008 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7806 23:03:18.397074 == TX Byte 1 ==
7807 23:03:18.400349 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7808 23:03:18.404068 DramC Write-DBI off
7809 23:03:18.404158
7810 23:03:18.404248 [DATLAT]
7811 23:03:18.404312 Freq=1600, CH0 RK0
7812 23:03:18.404371
7813 23:03:18.407075 DATLAT Default: 0xf
7814 23:03:18.407158 0, 0xFFFF, sum = 0
7815 23:03:18.410670 1, 0xFFFF, sum = 0
7816 23:03:18.413507 2, 0xFFFF, sum = 0
7817 23:03:18.413614 3, 0xFFFF, sum = 0
7818 23:03:18.416820 4, 0xFFFF, sum = 0
7819 23:03:18.416928 5, 0xFFFF, sum = 0
7820 23:03:18.420517 6, 0xFFFF, sum = 0
7821 23:03:18.420596 7, 0xFFFF, sum = 0
7822 23:03:18.423864 8, 0xFFFF, sum = 0
7823 23:03:18.423963 9, 0xFFFF, sum = 0
7824 23:03:18.427055 10, 0xFFFF, sum = 0
7825 23:03:18.427150 11, 0xFFFF, sum = 0
7826 23:03:18.430306 12, 0xFFFF, sum = 0
7827 23:03:18.430373 13, 0xEFFF, sum = 0
7828 23:03:18.433779 14, 0x0, sum = 1
7829 23:03:18.433848 15, 0x0, sum = 2
7830 23:03:18.436796 16, 0x0, sum = 3
7831 23:03:18.436895 17, 0x0, sum = 4
7832 23:03:18.440162 best_step = 15
7833 23:03:18.440286
7834 23:03:18.440348 ==
7835 23:03:18.443780 Dram Type= 6, Freq= 0, CH_0, rank 0
7836 23:03:18.447128 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7837 23:03:18.447226 ==
7838 23:03:18.450238 RX Vref Scan: 1
7839 23:03:18.450333
7840 23:03:18.450421 Set Vref Range= 24 -> 127
7841 23:03:18.450506
7842 23:03:18.453430 RX Vref 24 -> 127, step: 1
7843 23:03:18.453520
7844 23:03:18.456634 RX Delay 11 -> 252, step: 4
7845 23:03:18.456736
7846 23:03:18.460634 Set Vref, RX VrefLevel [Byte0]: 24
7847 23:03:18.463190 [Byte1]: 24
7848 23:03:18.463289
7849 23:03:18.466820 Set Vref, RX VrefLevel [Byte0]: 25
7850 23:03:18.469714 [Byte1]: 25
7851 23:03:18.473158
7852 23:03:18.473261 Set Vref, RX VrefLevel [Byte0]: 26
7853 23:03:18.476745 [Byte1]: 26
7854 23:03:18.480833
7855 23:03:18.480995 Set Vref, RX VrefLevel [Byte0]: 27
7856 23:03:18.484386 [Byte1]: 27
7857 23:03:18.488533
7858 23:03:18.488621 Set Vref, RX VrefLevel [Byte0]: 28
7859 23:03:18.491787 [Byte1]: 28
7860 23:03:18.496116
7861 23:03:18.496257 Set Vref, RX VrefLevel [Byte0]: 29
7862 23:03:18.499414 [Byte1]: 29
7863 23:03:18.503676
7864 23:03:18.503753 Set Vref, RX VrefLevel [Byte0]: 30
7865 23:03:18.507034 [Byte1]: 30
7866 23:03:18.511553
7867 23:03:18.511630 Set Vref, RX VrefLevel [Byte0]: 31
7868 23:03:18.514620 [Byte1]: 31
7869 23:03:18.518749
7870 23:03:18.518836 Set Vref, RX VrefLevel [Byte0]: 32
7871 23:03:18.522131 [Byte1]: 32
7872 23:03:18.526642
7873 23:03:18.526719 Set Vref, RX VrefLevel [Byte0]: 33
7874 23:03:18.530048 [Byte1]: 33
7875 23:03:18.534348
7876 23:03:18.534421 Set Vref, RX VrefLevel [Byte0]: 34
7877 23:03:18.537767 [Byte1]: 34
7878 23:03:18.541897
7879 23:03:18.542002 Set Vref, RX VrefLevel [Byte0]: 35
7880 23:03:18.545021 [Byte1]: 35
7881 23:03:18.549546
7882 23:03:18.549621 Set Vref, RX VrefLevel [Byte0]: 36
7883 23:03:18.552763 [Byte1]: 36
7884 23:03:18.556980
7885 23:03:18.557079 Set Vref, RX VrefLevel [Byte0]: 37
7886 23:03:18.560120 [Byte1]: 37
7887 23:03:18.564445
7888 23:03:18.564522 Set Vref, RX VrefLevel [Byte0]: 38
7889 23:03:18.568050 [Byte1]: 38
7890 23:03:18.572414
7891 23:03:18.572493 Set Vref, RX VrefLevel [Byte0]: 39
7892 23:03:18.575533 [Byte1]: 39
7893 23:03:18.579897
7894 23:03:18.579978 Set Vref, RX VrefLevel [Byte0]: 40
7895 23:03:18.583015 [Byte1]: 40
7896 23:03:18.587954
7897 23:03:18.588064 Set Vref, RX VrefLevel [Byte0]: 41
7898 23:03:18.591051 [Byte1]: 41
7899 23:03:18.595291
7900 23:03:18.595438 Set Vref, RX VrefLevel [Byte0]: 42
7901 23:03:18.598684 [Byte1]: 42
7902 23:03:18.603072
7903 23:03:18.603169 Set Vref, RX VrefLevel [Byte0]: 43
7904 23:03:18.606291 [Byte1]: 43
7905 23:03:18.610615
7906 23:03:18.610772 Set Vref, RX VrefLevel [Byte0]: 44
7907 23:03:18.613783 [Byte1]: 44
7908 23:03:18.617783
7909 23:03:18.617881 Set Vref, RX VrefLevel [Byte0]: 45
7910 23:03:18.621208 [Byte1]: 45
7911 23:03:18.625601
7912 23:03:18.625710 Set Vref, RX VrefLevel [Byte0]: 46
7913 23:03:18.628625 [Byte1]: 46
7914 23:03:18.633153
7915 23:03:18.633226 Set Vref, RX VrefLevel [Byte0]: 47
7916 23:03:18.636368 [Byte1]: 47
7917 23:03:18.640897
7918 23:03:18.640983 Set Vref, RX VrefLevel [Byte0]: 48
7919 23:03:18.644152 [Byte1]: 48
7920 23:03:18.648508
7921 23:03:18.648593 Set Vref, RX VrefLevel [Byte0]: 49
7922 23:03:18.651789 [Byte1]: 49
7923 23:03:18.656059
7924 23:03:18.656168 Set Vref, RX VrefLevel [Byte0]: 50
7925 23:03:18.659279 [Byte1]: 50
7926 23:03:18.664076
7927 23:03:18.664183 Set Vref, RX VrefLevel [Byte0]: 51
7928 23:03:18.667096 [Byte1]: 51
7929 23:03:18.671127
7930 23:03:18.671214 Set Vref, RX VrefLevel [Byte0]: 52
7931 23:03:18.674331 [Byte1]: 52
7932 23:03:18.678811
7933 23:03:18.678918 Set Vref, RX VrefLevel [Byte0]: 53
7934 23:03:18.682429 [Byte1]: 53
7935 23:03:18.686351
7936 23:03:18.686428 Set Vref, RX VrefLevel [Byte0]: 54
7937 23:03:18.689885 [Byte1]: 54
7938 23:03:18.694169
7939 23:03:18.694265 Set Vref, RX VrefLevel [Byte0]: 55
7940 23:03:18.697263 [Byte1]: 55
7941 23:03:18.701631
7942 23:03:18.701740 Set Vref, RX VrefLevel [Byte0]: 56
7943 23:03:18.705041 [Byte1]: 56
7944 23:03:18.709633
7945 23:03:18.709743 Set Vref, RX VrefLevel [Byte0]: 57
7946 23:03:18.712527 [Byte1]: 57
7947 23:03:18.717012
7948 23:03:18.717111 Set Vref, RX VrefLevel [Byte0]: 58
7949 23:03:18.720187 [Byte1]: 58
7950 23:03:18.724461
7951 23:03:18.724534 Set Vref, RX VrefLevel [Byte0]: 59
7952 23:03:18.727591 [Byte1]: 59
7953 23:03:18.732458
7954 23:03:18.732530 Set Vref, RX VrefLevel [Byte0]: 60
7955 23:03:18.735231 [Byte1]: 60
7956 23:03:18.739483
7957 23:03:18.739553 Set Vref, RX VrefLevel [Byte0]: 61
7958 23:03:18.742972 [Byte1]: 61
7959 23:03:18.747841
7960 23:03:18.747949 Set Vref, RX VrefLevel [Byte0]: 62
7961 23:03:18.750794 [Byte1]: 62
7962 23:03:18.754737
7963 23:03:18.754836 Set Vref, RX VrefLevel [Byte0]: 63
7964 23:03:18.758368 [Byte1]: 63
7965 23:03:18.762491
7966 23:03:18.762598 Set Vref, RX VrefLevel [Byte0]: 64
7967 23:03:18.765726 [Byte1]: 64
7968 23:03:18.770620
7969 23:03:18.770718 Set Vref, RX VrefLevel [Byte0]: 65
7970 23:03:18.773367 [Byte1]: 65
7971 23:03:18.777848
7972 23:03:18.777948 Set Vref, RX VrefLevel [Byte0]: 66
7973 23:03:18.780951 [Byte1]: 66
7974 23:03:18.785340
7975 23:03:18.785415 Set Vref, RX VrefLevel [Byte0]: 67
7976 23:03:18.788993 [Byte1]: 67
7977 23:03:18.793065
7978 23:03:18.793143 Set Vref, RX VrefLevel [Byte0]: 68
7979 23:03:18.796150 [Byte1]: 68
7980 23:03:18.800749
7981 23:03:18.800821 Set Vref, RX VrefLevel [Byte0]: 69
7982 23:03:18.803760 [Byte1]: 69
7983 23:03:18.808086
7984 23:03:18.808187 Set Vref, RX VrefLevel [Byte0]: 70
7985 23:03:18.811460 [Byte1]: 70
7986 23:03:18.815871
7987 23:03:18.815978 Set Vref, RX VrefLevel [Byte0]: 71
7988 23:03:18.818953 [Byte1]: 71
7989 23:03:18.823587
7990 23:03:18.823697 Set Vref, RX VrefLevel [Byte0]: 72
7991 23:03:18.826882 [Byte1]: 72
7992 23:03:18.831273
7993 23:03:18.831346 Set Vref, RX VrefLevel [Byte0]: 73
7994 23:03:18.834529 [Byte1]: 73
7995 23:03:18.839053
7996 23:03:18.839128 Set Vref, RX VrefLevel [Byte0]: 74
7997 23:03:18.841969 [Byte1]: 74
7998 23:03:18.846491
7999 23:03:18.846594 Set Vref, RX VrefLevel [Byte0]: 75
8000 23:03:18.849618 [Byte1]: 75
8001 23:03:18.853967
8002 23:03:18.854065 Set Vref, RX VrefLevel [Byte0]: 76
8003 23:03:18.857073 [Byte1]: 76
8004 23:03:18.861547
8005 23:03:18.861644 Set Vref, RX VrefLevel [Byte0]: 77
8006 23:03:18.864930 [Byte1]: 77
8007 23:03:18.869030
8008 23:03:18.869139 Final RX Vref Byte 0 = 62 to rank0
8009 23:03:18.872305 Final RX Vref Byte 1 = 61 to rank0
8010 23:03:18.875800 Final RX Vref Byte 0 = 62 to rank1
8011 23:03:18.879093 Final RX Vref Byte 1 = 61 to rank1==
8012 23:03:18.882503 Dram Type= 6, Freq= 0, CH_0, rank 0
8013 23:03:18.889365 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8014 23:03:18.889460 ==
8015 23:03:18.889526 DQS Delay:
8016 23:03:18.889586 DQS0 = 0, DQS1 = 0
8017 23:03:18.892406 DQM Delay:
8018 23:03:18.892482 DQM0 = 126, DQM1 = 119
8019 23:03:18.896001 DQ Delay:
8020 23:03:18.899232 DQ0 =124, DQ1 =128, DQ2 =126, DQ3 =122
8021 23:03:18.902298 DQ4 =126, DQ5 =112, DQ6 =132, DQ7 =138
8022 23:03:18.905441 DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =114
8023 23:03:18.908797 DQ12 =124, DQ13 =124, DQ14 =130, DQ15 =126
8024 23:03:18.908906
8025 23:03:18.909000
8026 23:03:18.909129
8027 23:03:18.912223 [DramC_TX_OE_Calibration] TA2
8028 23:03:18.915734 Original DQ_B0 (3 6) =30, OEN = 27
8029 23:03:18.918833 Original DQ_B1 (3 6) =30, OEN = 27
8030 23:03:18.922197 24, 0x0, End_B0=24 End_B1=24
8031 23:03:18.922301 25, 0x0, End_B0=25 End_B1=25
8032 23:03:18.925338 26, 0x0, End_B0=26 End_B1=26
8033 23:03:18.929072 27, 0x0, End_B0=27 End_B1=27
8034 23:03:18.932383 28, 0x0, End_B0=28 End_B1=28
8035 23:03:18.935285 29, 0x0, End_B0=29 End_B1=29
8036 23:03:18.935360 30, 0x0, End_B0=30 End_B1=30
8037 23:03:18.938697 31, 0x4141, End_B0=30 End_B1=30
8038 23:03:18.942068 Byte0 end_step=30 best_step=27
8039 23:03:18.945285 Byte1 end_step=30 best_step=27
8040 23:03:18.948924 Byte0 TX OE(2T, 0.5T) = (3, 3)
8041 23:03:18.952199 Byte1 TX OE(2T, 0.5T) = (3, 3)
8042 23:03:18.952282
8043 23:03:18.952344
8044 23:03:18.958599 [DQSOSCAuto] RK0, (LSB)MR18= 0x1514, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
8045 23:03:18.961787 CH0 RK0: MR19=303, MR18=1514
8046 23:03:18.968448 CH0_RK0: MR19=0x303, MR18=0x1514, DQSOSC=399, MR23=63, INC=23, DEC=15
8047 23:03:18.968523
8048 23:03:18.971971 ----->DramcWriteLeveling(PI) begin...
8049 23:03:18.972046 ==
8050 23:03:18.975445 Dram Type= 6, Freq= 0, CH_0, rank 1
8051 23:03:18.978499 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8052 23:03:18.978599 ==
8053 23:03:18.981656 Write leveling (Byte 0): 33 => 33
8054 23:03:18.985350 Write leveling (Byte 1): 26 => 26
8055 23:03:18.988704 DramcWriteLeveling(PI) end<-----
8056 23:03:18.988776
8057 23:03:18.988841 ==
8058 23:03:18.991711 Dram Type= 6, Freq= 0, CH_0, rank 1
8059 23:03:18.995136 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8060 23:03:18.995244 ==
8061 23:03:18.998470 [Gating] SW mode calibration
8062 23:03:19.004767 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8063 23:03:19.011458 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8064 23:03:19.015010 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8065 23:03:19.021565 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8066 23:03:19.024746 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8067 23:03:19.027926 1 4 12 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (1 1)
8068 23:03:19.034382 1 4 16 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
8069 23:03:19.037983 1 4 20 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
8070 23:03:19.041449 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8071 23:03:19.047977 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8072 23:03:19.051235 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8073 23:03:19.054408 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8074 23:03:19.057828 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8075 23:03:19.064605 1 5 12 | B1->B0 | 3434 2929 | 1 0 | (1 1) (0 1)
8076 23:03:19.067705 1 5 16 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
8077 23:03:19.071146 1 5 20 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
8078 23:03:19.077750 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8079 23:03:19.081248 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8080 23:03:19.084607 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8081 23:03:19.090870 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8082 23:03:19.094147 1 6 8 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
8083 23:03:19.097569 1 6 12 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
8084 23:03:19.104457 1 6 16 | B1->B0 | 3030 4646 | 0 0 | (0 0) (0 0)
8085 23:03:19.107486 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8086 23:03:19.110973 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8087 23:03:19.117911 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8088 23:03:19.120657 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8089 23:03:19.123827 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8090 23:03:19.130643 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8091 23:03:19.134092 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8092 23:03:19.137657 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8093 23:03:19.144145 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8094 23:03:19.147373 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8095 23:03:19.150769 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8096 23:03:19.157275 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8097 23:03:19.160509 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8098 23:03:19.164346 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8099 23:03:19.170945 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8100 23:03:19.173872 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8101 23:03:19.177184 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8102 23:03:19.184016 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8103 23:03:19.187126 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8104 23:03:19.190782 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8105 23:03:19.197270 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8106 23:03:19.200663 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8107 23:03:19.203921 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8108 23:03:19.210801 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8109 23:03:19.210914 Total UI for P1: 0, mck2ui 16
8110 23:03:19.214538 best dqsien dly found for B0: ( 1, 9, 10)
8111 23:03:19.220685 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8112 23:03:19.223699 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8113 23:03:19.227179 Total UI for P1: 0, mck2ui 16
8114 23:03:19.230806 best dqsien dly found for B1: ( 1, 9, 16)
8115 23:03:19.233715 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8116 23:03:19.236933 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8117 23:03:19.237027
8118 23:03:19.240143 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8119 23:03:19.247259 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8120 23:03:19.247373 [Gating] SW calibration Done
8121 23:03:19.247469 ==
8122 23:03:19.250653 Dram Type= 6, Freq= 0, CH_0, rank 1
8123 23:03:19.256890 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8124 23:03:19.256974 ==
8125 23:03:19.257039 RX Vref Scan: 0
8126 23:03:19.257098
8127 23:03:19.260484 RX Vref 0 -> 0, step: 1
8128 23:03:19.260564
8129 23:03:19.263670 RX Delay 0 -> 252, step: 8
8130 23:03:19.266887 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8131 23:03:19.270218 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8132 23:03:19.273461 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8133 23:03:19.280042 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8134 23:03:19.283463 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8135 23:03:19.286619 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
8136 23:03:19.289783 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8137 23:03:19.293731 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8138 23:03:19.300119 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8139 23:03:19.303372 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8140 23:03:19.306215 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8141 23:03:19.309913 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8142 23:03:19.313406 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8143 23:03:19.319596 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8144 23:03:19.322881 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8145 23:03:19.326317 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8146 23:03:19.326429 ==
8147 23:03:19.329552 Dram Type= 6, Freq= 0, CH_0, rank 1
8148 23:03:19.333167 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8149 23:03:19.336008 ==
8150 23:03:19.336109 DQS Delay:
8151 23:03:19.336206 DQS0 = 0, DQS1 = 0
8152 23:03:19.339472 DQM Delay:
8153 23:03:19.339573 DQM0 = 128, DQM1 = 122
8154 23:03:19.342684 DQ Delay:
8155 23:03:19.346134 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
8156 23:03:19.349270 DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =139
8157 23:03:19.352811 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
8158 23:03:19.356382 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =127
8159 23:03:19.356456
8160 23:03:19.356520
8161 23:03:19.356595 ==
8162 23:03:19.359294 Dram Type= 6, Freq= 0, CH_0, rank 1
8163 23:03:19.362775 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8164 23:03:19.362889 ==
8165 23:03:19.366034
8166 23:03:19.366135
8167 23:03:19.366232 TX Vref Scan disable
8168 23:03:19.369356 == TX Byte 0 ==
8169 23:03:19.372850 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8170 23:03:19.376044 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8171 23:03:19.379149 == TX Byte 1 ==
8172 23:03:19.382322 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8173 23:03:19.385643 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8174 23:03:19.385751 ==
8175 23:03:19.388853 Dram Type= 6, Freq= 0, CH_0, rank 1
8176 23:03:19.395873 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8177 23:03:19.395982 ==
8178 23:03:19.408111
8179 23:03:19.411773 TX Vref early break, caculate TX vref
8180 23:03:19.415165 TX Vref=16, minBit 0, minWin=22, winSum=364
8181 23:03:19.418469 TX Vref=18, minBit 8, minWin=22, winSum=373
8182 23:03:19.421704 TX Vref=20, minBit 2, minWin=23, winSum=383
8183 23:03:19.424969 TX Vref=22, minBit 0, minWin=24, winSum=391
8184 23:03:19.428357 TX Vref=24, minBit 0, minWin=24, winSum=397
8185 23:03:19.435040 TX Vref=26, minBit 8, minWin=24, winSum=406
8186 23:03:19.438427 TX Vref=28, minBit 1, minWin=25, winSum=409
8187 23:03:19.441710 TX Vref=30, minBit 8, minWin=24, winSum=406
8188 23:03:19.444967 TX Vref=32, minBit 8, minWin=23, winSum=396
8189 23:03:19.448143 TX Vref=34, minBit 8, minWin=23, winSum=387
8190 23:03:19.454516 [TxChooseVref] Worse bit 1, Min win 25, Win sum 409, Final Vref 28
8191 23:03:19.454621
8192 23:03:19.457945 Final TX Range 0 Vref 28
8193 23:03:19.458018
8194 23:03:19.458085 ==
8195 23:03:19.461160 Dram Type= 6, Freq= 0, CH_0, rank 1
8196 23:03:19.464449 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8197 23:03:19.464524 ==
8198 23:03:19.464584
8199 23:03:19.464641
8200 23:03:19.467915 TX Vref Scan disable
8201 23:03:19.474548 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8202 23:03:19.474652 == TX Byte 0 ==
8203 23:03:19.477664 u2DelayCellOfst[0]=11 cells (3 PI)
8204 23:03:19.481170 u2DelayCellOfst[1]=18 cells (5 PI)
8205 23:03:19.484419 u2DelayCellOfst[2]=11 cells (3 PI)
8206 23:03:19.487553 u2DelayCellOfst[3]=11 cells (3 PI)
8207 23:03:19.491349 u2DelayCellOfst[4]=7 cells (2 PI)
8208 23:03:19.494686 u2DelayCellOfst[5]=0 cells (0 PI)
8209 23:03:19.497874 u2DelayCellOfst[6]=18 cells (5 PI)
8210 23:03:19.500949 u2DelayCellOfst[7]=18 cells (5 PI)
8211 23:03:19.504084 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8212 23:03:19.507356 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8213 23:03:19.510672 == TX Byte 1 ==
8214 23:03:19.514164 u2DelayCellOfst[8]=0 cells (0 PI)
8215 23:03:19.514268 u2DelayCellOfst[9]=3 cells (1 PI)
8216 23:03:19.517319 u2DelayCellOfst[10]=11 cells (3 PI)
8217 23:03:19.520602 u2DelayCellOfst[11]=3 cells (1 PI)
8218 23:03:19.523827 u2DelayCellOfst[12]=15 cells (4 PI)
8219 23:03:19.527099 u2DelayCellOfst[13]=11 cells (3 PI)
8220 23:03:19.530334 u2DelayCellOfst[14]=15 cells (4 PI)
8221 23:03:19.534133 u2DelayCellOfst[15]=15 cells (4 PI)
8222 23:03:19.540706 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8223 23:03:19.543741 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8224 23:03:19.543849 DramC Write-DBI on
8225 23:03:19.543941 ==
8226 23:03:19.546769 Dram Type= 6, Freq= 0, CH_0, rank 1
8227 23:03:19.554169 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8228 23:03:19.554276 ==
8229 23:03:19.554367
8230 23:03:19.554459
8231 23:03:19.554544 TX Vref Scan disable
8232 23:03:19.557688 == TX Byte 0 ==
8233 23:03:19.561294 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
8234 23:03:19.564668 == TX Byte 1 ==
8235 23:03:19.568033 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8236 23:03:19.571151 DramC Write-DBI off
8237 23:03:19.571253
8238 23:03:19.571347 [DATLAT]
8239 23:03:19.571435 Freq=1600, CH0 RK1
8240 23:03:19.571530
8241 23:03:19.574267 DATLAT Default: 0xf
8242 23:03:19.574363 0, 0xFFFF, sum = 0
8243 23:03:19.577807 1, 0xFFFF, sum = 0
8244 23:03:19.577914 2, 0xFFFF, sum = 0
8245 23:03:19.581067 3, 0xFFFF, sum = 0
8246 23:03:19.584328 4, 0xFFFF, sum = 0
8247 23:03:19.584416 5, 0xFFFF, sum = 0
8248 23:03:19.588101 6, 0xFFFF, sum = 0
8249 23:03:19.588233 7, 0xFFFF, sum = 0
8250 23:03:19.591285 8, 0xFFFF, sum = 0
8251 23:03:19.591389 9, 0xFFFF, sum = 0
8252 23:03:19.594357 10, 0xFFFF, sum = 0
8253 23:03:19.594464 11, 0xFFFF, sum = 0
8254 23:03:19.597639 12, 0xFFFF, sum = 0
8255 23:03:19.597737 13, 0xCFFF, sum = 0
8256 23:03:19.601459 14, 0x0, sum = 1
8257 23:03:19.601583 15, 0x0, sum = 2
8258 23:03:19.604360 16, 0x0, sum = 3
8259 23:03:19.604449 17, 0x0, sum = 4
8260 23:03:19.607604 best_step = 15
8261 23:03:19.607706
8262 23:03:19.607795 ==
8263 23:03:19.610820 Dram Type= 6, Freq= 0, CH_0, rank 1
8264 23:03:19.614066 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8265 23:03:19.614172 ==
8266 23:03:19.617482 RX Vref Scan: 0
8267 23:03:19.617577
8268 23:03:19.617674 RX Vref 0 -> 0, step: 1
8269 23:03:19.617762
8270 23:03:19.620996 RX Delay 3 -> 252, step: 4
8271 23:03:19.624550 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8272 23:03:19.630935 iDelay=191, Bit 1, Center 126 (71 ~ 182) 112
8273 23:03:19.634191 iDelay=191, Bit 2, Center 120 (67 ~ 174) 108
8274 23:03:19.637276 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8275 23:03:19.640608 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8276 23:03:19.643925 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8277 23:03:19.650531 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8278 23:03:19.654422 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8279 23:03:19.657642 iDelay=191, Bit 8, Center 110 (55 ~ 166) 112
8280 23:03:19.660492 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8281 23:03:19.664419 iDelay=191, Bit 10, Center 118 (63 ~ 174) 112
8282 23:03:19.670673 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8283 23:03:19.674159 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8284 23:03:19.677284 iDelay=191, Bit 13, Center 122 (67 ~ 178) 112
8285 23:03:19.680385 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8286 23:03:19.687051 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8287 23:03:19.687153 ==
8288 23:03:19.690473 Dram Type= 6, Freq= 0, CH_0, rank 1
8289 23:03:19.694183 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8290 23:03:19.694317 ==
8291 23:03:19.694442 DQS Delay:
8292 23:03:19.696938 DQS0 = 0, DQS1 = 0
8293 23:03:19.697048 DQM Delay:
8294 23:03:19.700510 DQM0 = 124, DQM1 = 117
8295 23:03:19.700593 DQ Delay:
8296 23:03:19.703867 DQ0 =124, DQ1 =126, DQ2 =120, DQ3 =122
8297 23:03:19.707355 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8298 23:03:19.710491 DQ8 =110, DQ9 =104, DQ10 =118, DQ11 =112
8299 23:03:19.713668 DQ12 =124, DQ13 =122, DQ14 =128, DQ15 =124
8300 23:03:19.713774
8301 23:03:19.713865
8302 23:03:19.713989
8303 23:03:19.716960 [DramC_TX_OE_Calibration] TA2
8304 23:03:19.720313 Original DQ_B0 (3 6) =30, OEN = 27
8305 23:03:19.723613 Original DQ_B1 (3 6) =30, OEN = 27
8306 23:03:19.726899 24, 0x0, End_B0=24 End_B1=24
8307 23:03:19.730712 25, 0x0, End_B0=25 End_B1=25
8308 23:03:19.730819 26, 0x0, End_B0=26 End_B1=26
8309 23:03:19.733607 27, 0x0, End_B0=27 End_B1=27
8310 23:03:19.737176 28, 0x0, End_B0=28 End_B1=28
8311 23:03:19.740474 29, 0x0, End_B0=29 End_B1=29
8312 23:03:19.743674 30, 0x0, End_B0=30 End_B1=30
8313 23:03:19.743776 31, 0x4141, End_B0=30 End_B1=30
8314 23:03:19.746858 Byte0 end_step=30 best_step=27
8315 23:03:19.750007 Byte1 end_step=30 best_step=27
8316 23:03:19.753768 Byte0 TX OE(2T, 0.5T) = (3, 3)
8317 23:03:19.756665 Byte1 TX OE(2T, 0.5T) = (3, 3)
8318 23:03:19.756768
8319 23:03:19.756862
8320 23:03:19.763793 [DQSOSCAuto] RK1, (LSB)MR18= 0x2310, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 392 ps
8321 23:03:19.766469 CH0 RK1: MR19=303, MR18=2310
8322 23:03:19.773183 CH0_RK1: MR19=0x303, MR18=0x2310, DQSOSC=392, MR23=63, INC=24, DEC=16
8323 23:03:19.777124 [RxdqsGatingPostProcess] freq 1600
8324 23:03:19.783162 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8325 23:03:19.786863 best DQS0 dly(2T, 0.5T) = (1, 1)
8326 23:03:19.786964 best DQS1 dly(2T, 0.5T) = (1, 1)
8327 23:03:19.790047 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8328 23:03:19.793424 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8329 23:03:19.796745 best DQS0 dly(2T, 0.5T) = (1, 1)
8330 23:03:19.799970 best DQS1 dly(2T, 0.5T) = (1, 1)
8331 23:03:19.803229 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8332 23:03:19.806549 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8333 23:03:19.809890 Pre-setting of DQS Precalculation
8334 23:03:19.812909 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8335 23:03:19.816469 ==
8336 23:03:19.820057 Dram Type= 6, Freq= 0, CH_1, rank 0
8337 23:03:19.822950 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8338 23:03:19.823052 ==
8339 23:03:19.826469 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8340 23:03:19.832908 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8341 23:03:19.836332 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8342 23:03:19.842871 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8343 23:03:19.851340 [CA 0] Center 41 (12~71) winsize 60
8344 23:03:19.854584 [CA 1] Center 42 (12~72) winsize 61
8345 23:03:19.858008 [CA 2] Center 37 (9~66) winsize 58
8346 23:03:19.860861 [CA 3] Center 36 (7~66) winsize 60
8347 23:03:19.864357 [CA 4] Center 37 (8~66) winsize 59
8348 23:03:19.867659 [CA 5] Center 36 (7~66) winsize 60
8349 23:03:19.867789
8350 23:03:19.870786 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8351 23:03:19.870890
8352 23:03:19.874018 [CATrainingPosCal] consider 1 rank data
8353 23:03:19.877619 u2DelayCellTimex100 = 258/100 ps
8354 23:03:19.884071 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8355 23:03:19.887245 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8356 23:03:19.890433 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8357 23:03:19.893896 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8358 23:03:19.897350 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8359 23:03:19.900640 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8360 23:03:19.900715
8361 23:03:19.903681 CA PerBit enable=1, Macro0, CA PI delay=36
8362 23:03:19.903783
8363 23:03:19.907383 [CBTSetCACLKResult] CA Dly = 36
8364 23:03:19.910354 CS Dly: 9 (0~40)
8365 23:03:19.913770 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8366 23:03:19.917048 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8367 23:03:19.917154 ==
8368 23:03:19.920441 Dram Type= 6, Freq= 0, CH_1, rank 1
8369 23:03:19.927081 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8370 23:03:19.927188 ==
8371 23:03:19.930185 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8372 23:03:19.936693 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8373 23:03:19.940402 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8374 23:03:19.946389 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8375 23:03:19.953975 [CA 0] Center 41 (12~71) winsize 60
8376 23:03:19.957210 [CA 1] Center 42 (12~72) winsize 61
8377 23:03:19.960522 [CA 2] Center 37 (8~67) winsize 60
8378 23:03:19.964144 [CA 3] Center 36 (7~66) winsize 60
8379 23:03:19.967230 [CA 4] Center 37 (8~67) winsize 60
8380 23:03:19.970745 [CA 5] Center 36 (6~66) winsize 61
8381 23:03:19.970850
8382 23:03:19.974183 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8383 23:03:19.974287
8384 23:03:19.977436 [CATrainingPosCal] consider 2 rank data
8385 23:03:19.980435 u2DelayCellTimex100 = 258/100 ps
8386 23:03:19.987276 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8387 23:03:19.990337 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8388 23:03:19.993852 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8389 23:03:19.996896 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8390 23:03:20.000230 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8391 23:03:20.003994 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8392 23:03:20.004088
8393 23:03:20.007318 CA PerBit enable=1, Macro0, CA PI delay=36
8394 23:03:20.007416
8395 23:03:20.010483 [CBTSetCACLKResult] CA Dly = 36
8396 23:03:20.013747 CS Dly: 10 (0~43)
8397 23:03:20.016927 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8398 23:03:20.020533 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8399 23:03:20.020633
8400 23:03:20.023448 ----->DramcWriteLeveling(PI) begin...
8401 23:03:20.023548 ==
8402 23:03:20.026926 Dram Type= 6, Freq= 0, CH_1, rank 0
8403 23:03:20.033754 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8404 23:03:20.033859 ==
8405 23:03:20.036863 Write leveling (Byte 0): 26 => 26
8406 23:03:20.040054 Write leveling (Byte 1): 27 => 27
8407 23:03:20.040160 DramcWriteLeveling(PI) end<-----
8408 23:03:20.040275
8409 23:03:20.043216 ==
8410 23:03:20.043312 Dram Type= 6, Freq= 0, CH_1, rank 0
8411 23:03:20.050146 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8412 23:03:20.050252 ==
8413 23:03:20.053369 [Gating] SW mode calibration
8414 23:03:20.060042 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8415 23:03:20.063685 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8416 23:03:20.069877 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8417 23:03:20.073566 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8418 23:03:20.078078 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8419 23:03:20.083174 1 4 12 | B1->B0 | 2323 2323 | 1 0 | (1 1) (0 0)
8420 23:03:20.087022 1 4 16 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
8421 23:03:20.089802 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8422 23:03:20.096433 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8423 23:03:20.099681 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8424 23:03:20.103255 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8425 23:03:20.109771 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8426 23:03:20.113099 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8427 23:03:20.116290 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8428 23:03:20.123204 1 5 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 0)
8429 23:03:20.126360 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8430 23:03:20.129875 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8431 23:03:20.136774 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8432 23:03:20.139790 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8433 23:03:20.142888 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8434 23:03:20.149341 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8435 23:03:20.153189 1 6 12 | B1->B0 | 2f2f 2a2a | 0 1 | (0 0) (0 0)
8436 23:03:20.156315 1 6 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8437 23:03:20.162837 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8438 23:03:20.165866 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8439 23:03:20.169223 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8440 23:03:20.176390 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8441 23:03:20.179379 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8442 23:03:20.182469 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8443 23:03:20.188899 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8444 23:03:20.192181 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8445 23:03:20.195617 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8446 23:03:20.199479 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8447 23:03:20.205739 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8448 23:03:20.208826 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8449 23:03:20.212535 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8450 23:03:20.219077 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8451 23:03:20.222340 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8452 23:03:20.225797 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8453 23:03:20.232061 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8454 23:03:20.235894 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8455 23:03:20.238856 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8456 23:03:20.245207 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8457 23:03:20.249010 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8458 23:03:20.252075 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8459 23:03:20.258997 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8460 23:03:20.262399 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8461 23:03:20.265043 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8462 23:03:20.268362 Total UI for P1: 0, mck2ui 16
8463 23:03:20.272121 best dqsien dly found for B0: ( 1, 9, 14)
8464 23:03:20.275166 Total UI for P1: 0, mck2ui 16
8465 23:03:20.278581 best dqsien dly found for B1: ( 1, 9, 16)
8466 23:03:20.281877 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8467 23:03:20.285042 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8468 23:03:20.285150
8469 23:03:20.292109 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8470 23:03:20.295029 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8471 23:03:20.298429 [Gating] SW calibration Done
8472 23:03:20.298530 ==
8473 23:03:20.301426 Dram Type= 6, Freq= 0, CH_1, rank 0
8474 23:03:20.305069 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8475 23:03:20.305147 ==
8476 23:03:20.305210 RX Vref Scan: 0
8477 23:03:20.308454
8478 23:03:20.308555 RX Vref 0 -> 0, step: 1
8479 23:03:20.308646
8480 23:03:20.311425 RX Delay 0 -> 252, step: 8
8481 23:03:20.315121 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8482 23:03:20.318446 iDelay=200, Bit 1, Center 127 (64 ~ 191) 128
8483 23:03:20.324667 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8484 23:03:20.328170 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8485 23:03:20.331366 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8486 23:03:20.334706 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8487 23:03:20.338583 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8488 23:03:20.344675 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8489 23:03:20.348135 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8490 23:03:20.351541 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8491 23:03:20.354904 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8492 23:03:20.358039 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8493 23:03:20.364538 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8494 23:03:20.367693 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8495 23:03:20.371398 iDelay=200, Bit 14, Center 131 (80 ~ 183) 104
8496 23:03:20.374744 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8497 23:03:20.374845 ==
8498 23:03:20.377894 Dram Type= 6, Freq= 0, CH_1, rank 0
8499 23:03:20.384379 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8500 23:03:20.384481 ==
8501 23:03:20.384567 DQS Delay:
8502 23:03:20.387597 DQS0 = 0, DQS1 = 0
8503 23:03:20.387695 DQM Delay:
8504 23:03:20.390836 DQM0 = 131, DQM1 = 125
8505 23:03:20.390931 DQ Delay:
8506 23:03:20.394071 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8507 23:03:20.397513 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =127
8508 23:03:20.400662 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
8509 23:03:20.404441 DQ12 =135, DQ13 =131, DQ14 =131, DQ15 =135
8510 23:03:20.404535
8511 23:03:20.404627
8512 23:03:20.404714 ==
8513 23:03:20.407894 Dram Type= 6, Freq= 0, CH_1, rank 0
8514 23:03:20.410988 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8515 23:03:20.414337 ==
8516 23:03:20.414439
8517 23:03:20.414539
8518 23:03:20.414628 TX Vref Scan disable
8519 23:03:20.417644 == TX Byte 0 ==
8520 23:03:20.421324 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8521 23:03:20.424412 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8522 23:03:20.427503 == TX Byte 1 ==
8523 23:03:20.431065 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8524 23:03:20.434153 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8525 23:03:20.437437 ==
8526 23:03:20.440595 Dram Type= 6, Freq= 0, CH_1, rank 0
8527 23:03:20.443802 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8528 23:03:20.443899 ==
8529 23:03:20.456022
8530 23:03:20.459679 TX Vref early break, caculate TX vref
8531 23:03:20.462824 TX Vref=16, minBit 11, minWin=21, winSum=364
8532 23:03:20.466141 TX Vref=18, minBit 11, minWin=22, winSum=377
8533 23:03:20.469533 TX Vref=20, minBit 10, minWin=23, winSum=386
8534 23:03:20.472889 TX Vref=22, minBit 1, minWin=24, winSum=398
8535 23:03:20.479298 TX Vref=24, minBit 13, minWin=24, winSum=407
8536 23:03:20.482465 TX Vref=26, minBit 13, minWin=24, winSum=411
8537 23:03:20.485834 TX Vref=28, minBit 5, minWin=25, winSum=420
8538 23:03:20.489443 TX Vref=30, minBit 0, minWin=25, winSum=419
8539 23:03:20.492729 TX Vref=32, minBit 0, minWin=24, winSum=412
8540 23:03:20.496109 TX Vref=34, minBit 0, minWin=24, winSum=398
8541 23:03:20.502589 [TxChooseVref] Worse bit 5, Min win 25, Win sum 420, Final Vref 28
8542 23:03:20.502701
8543 23:03:20.505754 Final TX Range 0 Vref 28
8544 23:03:20.505863
8545 23:03:20.505954 ==
8546 23:03:20.509060 Dram Type= 6, Freq= 0, CH_1, rank 0
8547 23:03:20.512178 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8548 23:03:20.512317 ==
8549 23:03:20.512399
8550 23:03:20.515640
8551 23:03:20.515737 TX Vref Scan disable
8552 23:03:20.522035 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8553 23:03:20.522138 == TX Byte 0 ==
8554 23:03:20.525474 u2DelayCellOfst[0]=18 cells (5 PI)
8555 23:03:20.528930 u2DelayCellOfst[1]=15 cells (4 PI)
8556 23:03:20.532287 u2DelayCellOfst[2]=0 cells (0 PI)
8557 23:03:20.535293 u2DelayCellOfst[3]=7 cells (2 PI)
8558 23:03:20.538491 u2DelayCellOfst[4]=7 cells (2 PI)
8559 23:03:20.542173 u2DelayCellOfst[5]=22 cells (6 PI)
8560 23:03:20.545463 u2DelayCellOfst[6]=18 cells (5 PI)
8561 23:03:20.548876 u2DelayCellOfst[7]=7 cells (2 PI)
8562 23:03:20.552319 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8563 23:03:20.555376 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8564 23:03:20.558590 == TX Byte 1 ==
8565 23:03:20.562005 u2DelayCellOfst[8]=0 cells (0 PI)
8566 23:03:20.565320 u2DelayCellOfst[9]=7 cells (2 PI)
8567 23:03:20.565404 u2DelayCellOfst[10]=11 cells (3 PI)
8568 23:03:20.568755 u2DelayCellOfst[11]=7 cells (2 PI)
8569 23:03:20.571932 u2DelayCellOfst[12]=15 cells (4 PI)
8570 23:03:20.575412 u2DelayCellOfst[13]=18 cells (5 PI)
8571 23:03:20.578711 u2DelayCellOfst[14]=18 cells (5 PI)
8572 23:03:20.581862 u2DelayCellOfst[15]=18 cells (5 PI)
8573 23:03:20.588608 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8574 23:03:20.591769 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8575 23:03:20.591873 DramC Write-DBI on
8576 23:03:20.591966 ==
8577 23:03:20.595118 Dram Type= 6, Freq= 0, CH_1, rank 0
8578 23:03:20.602026 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8579 23:03:20.602136 ==
8580 23:03:20.602231
8581 23:03:20.602318
8582 23:03:20.602415 TX Vref Scan disable
8583 23:03:20.605799 == TX Byte 0 ==
8584 23:03:20.609045 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8585 23:03:20.612809 == TX Byte 1 ==
8586 23:03:20.615681 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8587 23:03:20.619316 DramC Write-DBI off
8588 23:03:20.619424
8589 23:03:20.619524 [DATLAT]
8590 23:03:20.619658 Freq=1600, CH1 RK0
8591 23:03:20.619774
8592 23:03:20.622208 DATLAT Default: 0xf
8593 23:03:20.622322 0, 0xFFFF, sum = 0
8594 23:03:20.625746 1, 0xFFFF, sum = 0
8595 23:03:20.629110 2, 0xFFFF, sum = 0
8596 23:03:20.629234 3, 0xFFFF, sum = 0
8597 23:03:20.632424 4, 0xFFFF, sum = 0
8598 23:03:20.632535 5, 0xFFFF, sum = 0
8599 23:03:20.636052 6, 0xFFFF, sum = 0
8600 23:03:20.636164 7, 0xFFFF, sum = 0
8601 23:03:20.639255 8, 0xFFFF, sum = 0
8602 23:03:20.639355 9, 0xFFFF, sum = 0
8603 23:03:20.642369 10, 0xFFFF, sum = 0
8604 23:03:20.642465 11, 0xFFFF, sum = 0
8605 23:03:20.645487 12, 0xFFFF, sum = 0
8606 23:03:20.645559 13, 0x8FFF, sum = 0
8607 23:03:20.648910 14, 0x0, sum = 1
8608 23:03:20.648982 15, 0x0, sum = 2
8609 23:03:20.651951 16, 0x0, sum = 3
8610 23:03:20.652049 17, 0x0, sum = 4
8611 23:03:20.655419 best_step = 15
8612 23:03:20.655490
8613 23:03:20.655552 ==
8614 23:03:20.659339 Dram Type= 6, Freq= 0, CH_1, rank 0
8615 23:03:20.662151 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8616 23:03:20.662246 ==
8617 23:03:20.665730 RX Vref Scan: 1
8618 23:03:20.665832
8619 23:03:20.665923 Set Vref Range= 24 -> 127
8620 23:03:20.666010
8621 23:03:20.669050 RX Vref 24 -> 127, step: 1
8622 23:03:20.669120
8623 23:03:20.671900 RX Delay 11 -> 252, step: 4
8624 23:03:20.671995
8625 23:03:20.675643 Set Vref, RX VrefLevel [Byte0]: 24
8626 23:03:20.678534 [Byte1]: 24
8627 23:03:20.678626
8628 23:03:20.682079 Set Vref, RX VrefLevel [Byte0]: 25
8629 23:03:20.685397 [Byte1]: 25
8630 23:03:20.688528
8631 23:03:20.688601 Set Vref, RX VrefLevel [Byte0]: 26
8632 23:03:20.691926 [Byte1]: 26
8633 23:03:20.696173
8634 23:03:20.696286 Set Vref, RX VrefLevel [Byte0]: 27
8635 23:03:20.700063 [Byte1]: 27
8636 23:03:20.703681
8637 23:03:20.703749 Set Vref, RX VrefLevel [Byte0]: 28
8638 23:03:20.707627 [Byte1]: 28
8639 23:03:20.711308
8640 23:03:20.711406 Set Vref, RX VrefLevel [Byte0]: 29
8641 23:03:20.714521 [Byte1]: 29
8642 23:03:20.719240
8643 23:03:20.719338 Set Vref, RX VrefLevel [Byte0]: 30
8644 23:03:20.722552 [Byte1]: 30
8645 23:03:20.726641
8646 23:03:20.726713 Set Vref, RX VrefLevel [Byte0]: 31
8647 23:03:20.729833 [Byte1]: 31
8648 23:03:20.734587
8649 23:03:20.734658 Set Vref, RX VrefLevel [Byte0]: 32
8650 23:03:20.737390 [Byte1]: 32
8651 23:03:20.741808
8652 23:03:20.741881 Set Vref, RX VrefLevel [Byte0]: 33
8653 23:03:20.745462 [Byte1]: 33
8654 23:03:20.749598
8655 23:03:20.749666 Set Vref, RX VrefLevel [Byte0]: 34
8656 23:03:20.752990 [Byte1]: 34
8657 23:03:20.757291
8658 23:03:20.757355 Set Vref, RX VrefLevel [Byte0]: 35
8659 23:03:20.760456 [Byte1]: 35
8660 23:03:20.764642
8661 23:03:20.764706 Set Vref, RX VrefLevel [Byte0]: 36
8662 23:03:20.768394 [Byte1]: 36
8663 23:03:20.772461
8664 23:03:20.772529 Set Vref, RX VrefLevel [Byte0]: 37
8665 23:03:20.775788 [Byte1]: 37
8666 23:03:20.779778
8667 23:03:20.779851 Set Vref, RX VrefLevel [Byte0]: 38
8668 23:03:20.783490 [Byte1]: 38
8669 23:03:20.787427
8670 23:03:20.787552 Set Vref, RX VrefLevel [Byte0]: 39
8671 23:03:20.790813 [Byte1]: 39
8672 23:03:20.795123
8673 23:03:20.795217 Set Vref, RX VrefLevel [Byte0]: 40
8674 23:03:20.798502 [Byte1]: 40
8675 23:03:20.802791
8676 23:03:20.802893 Set Vref, RX VrefLevel [Byte0]: 41
8677 23:03:20.806383 [Byte1]: 41
8678 23:03:20.810347
8679 23:03:20.810445 Set Vref, RX VrefLevel [Byte0]: 42
8680 23:03:20.813545 [Byte1]: 42
8681 23:03:20.817837
8682 23:03:20.817932 Set Vref, RX VrefLevel [Byte0]: 43
8683 23:03:20.821527 [Byte1]: 43
8684 23:03:20.825354
8685 23:03:20.825425 Set Vref, RX VrefLevel [Byte0]: 44
8686 23:03:20.828981 [Byte1]: 44
8687 23:03:20.833381
8688 23:03:20.833450 Set Vref, RX VrefLevel [Byte0]: 45
8689 23:03:20.836923 [Byte1]: 45
8690 23:03:20.840909
8691 23:03:20.841002 Set Vref, RX VrefLevel [Byte0]: 46
8692 23:03:20.844342 [Byte1]: 46
8693 23:03:20.848535
8694 23:03:20.848629 Set Vref, RX VrefLevel [Byte0]: 47
8695 23:03:20.852094 [Byte1]: 47
8696 23:03:20.856152
8697 23:03:20.856284 Set Vref, RX VrefLevel [Byte0]: 48
8698 23:03:20.859394 [Byte1]: 48
8699 23:03:20.863603
8700 23:03:20.863697 Set Vref, RX VrefLevel [Byte0]: 49
8701 23:03:20.866848 [Byte1]: 49
8702 23:03:20.871376
8703 23:03:20.871467 Set Vref, RX VrefLevel [Byte0]: 50
8704 23:03:20.874580 [Byte1]: 50
8705 23:03:20.878757
8706 23:03:20.878870 Set Vref, RX VrefLevel [Byte0]: 51
8707 23:03:20.882416 [Byte1]: 51
8708 23:03:20.886641
8709 23:03:20.886742 Set Vref, RX VrefLevel [Byte0]: 52
8710 23:03:20.889683 [Byte1]: 52
8711 23:03:20.894527
8712 23:03:20.894605 Set Vref, RX VrefLevel [Byte0]: 53
8713 23:03:20.897554 [Byte1]: 53
8714 23:03:20.901803
8715 23:03:20.901922 Set Vref, RX VrefLevel [Byte0]: 54
8716 23:03:20.905068 [Byte1]: 54
8717 23:03:20.909767
8718 23:03:20.909877 Set Vref, RX VrefLevel [Byte0]: 55
8719 23:03:20.912594 [Byte1]: 55
8720 23:03:20.917014
8721 23:03:20.917117 Set Vref, RX VrefLevel [Byte0]: 56
8722 23:03:20.920599 [Byte1]: 56
8723 23:03:20.924392
8724 23:03:20.924467 Set Vref, RX VrefLevel [Byte0]: 57
8725 23:03:20.927908 [Byte1]: 57
8726 23:03:20.932187
8727 23:03:20.932296 Set Vref, RX VrefLevel [Byte0]: 58
8728 23:03:20.935335 [Byte1]: 58
8729 23:03:20.939959
8730 23:03:20.940062 Set Vref, RX VrefLevel [Byte0]: 59
8731 23:03:20.943238 [Byte1]: 59
8732 23:03:20.947395
8733 23:03:20.947494 Set Vref, RX VrefLevel [Byte0]: 60
8734 23:03:20.950581 [Byte1]: 60
8735 23:03:20.954981
8736 23:03:20.955081 Set Vref, RX VrefLevel [Byte0]: 61
8737 23:03:20.958162 [Byte1]: 61
8738 23:03:20.962939
8739 23:03:20.963048 Set Vref, RX VrefLevel [Byte0]: 62
8740 23:03:20.966070 [Byte1]: 62
8741 23:03:20.970561
8742 23:03:20.970665 Set Vref, RX VrefLevel [Byte0]: 63
8743 23:03:20.973784 [Byte1]: 63
8744 23:03:20.977734
8745 23:03:20.977834 Set Vref, RX VrefLevel [Byte0]: 64
8746 23:03:20.981190 [Byte1]: 64
8747 23:03:20.985594
8748 23:03:20.985695 Set Vref, RX VrefLevel [Byte0]: 65
8749 23:03:20.988746 [Byte1]: 65
8750 23:03:20.993014
8751 23:03:20.993113 Set Vref, RX VrefLevel [Byte0]: 66
8752 23:03:20.996459 [Byte1]: 66
8753 23:03:21.000631
8754 23:03:21.000734 Set Vref, RX VrefLevel [Byte0]: 67
8755 23:03:21.004043 [Byte1]: 67
8756 23:03:21.008756
8757 23:03:21.008856 Set Vref, RX VrefLevel [Byte0]: 68
8758 23:03:21.011769 [Byte1]: 68
8759 23:03:21.015734
8760 23:03:21.015834 Set Vref, RX VrefLevel [Byte0]: 69
8761 23:03:21.019749 [Byte1]: 69
8762 23:03:21.023615
8763 23:03:21.023725 Set Vref, RX VrefLevel [Byte0]: 70
8764 23:03:21.026885 [Byte1]: 70
8765 23:03:21.031236
8766 23:03:21.031335 Set Vref, RX VrefLevel [Byte0]: 71
8767 23:03:21.034665 [Byte1]: 71
8768 23:03:21.038840
8769 23:03:21.038957 Final RX Vref Byte 0 = 56 to rank0
8770 23:03:21.042029 Final RX Vref Byte 1 = 56 to rank0
8771 23:03:21.045447 Final RX Vref Byte 0 = 56 to rank1
8772 23:03:21.048965 Final RX Vref Byte 1 = 56 to rank1==
8773 23:03:21.052036 Dram Type= 6, Freq= 0, CH_1, rank 0
8774 23:03:21.058941 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8775 23:03:21.059052 ==
8776 23:03:21.059144 DQS Delay:
8777 23:03:21.059231 DQS0 = 0, DQS1 = 0
8778 23:03:21.062301 DQM Delay:
8779 23:03:21.062399 DQM0 = 131, DQM1 = 123
8780 23:03:21.065249 DQ Delay:
8781 23:03:21.068904 DQ0 =136, DQ1 =128, DQ2 =120, DQ3 =128
8782 23:03:21.072067 DQ4 =126, DQ5 =142, DQ6 =142, DQ7 =128
8783 23:03:21.075252 DQ8 =108, DQ9 =114, DQ10 =122, DQ11 =116
8784 23:03:21.078483 DQ12 =134, DQ13 =132, DQ14 =132, DQ15 =130
8785 23:03:21.078584
8786 23:03:21.078673
8787 23:03:21.078761
8788 23:03:21.081713 [DramC_TX_OE_Calibration] TA2
8789 23:03:21.085116 Original DQ_B0 (3 6) =30, OEN = 27
8790 23:03:21.088387 Original DQ_B1 (3 6) =30, OEN = 27
8791 23:03:21.092035 24, 0x0, End_B0=24 End_B1=24
8792 23:03:21.092135 25, 0x0, End_B0=25 End_B1=25
8793 23:03:21.095312 26, 0x0, End_B0=26 End_B1=26
8794 23:03:21.098698 27, 0x0, End_B0=27 End_B1=27
8795 23:03:21.101716 28, 0x0, End_B0=28 End_B1=28
8796 23:03:21.105544 29, 0x0, End_B0=29 End_B1=29
8797 23:03:21.105645 30, 0x0, End_B0=30 End_B1=30
8798 23:03:21.108444 31, 0x4141, End_B0=30 End_B1=30
8799 23:03:21.111695 Byte0 end_step=30 best_step=27
8800 23:03:21.115158 Byte1 end_step=30 best_step=27
8801 23:03:21.118422 Byte0 TX OE(2T, 0.5T) = (3, 3)
8802 23:03:21.121633 Byte1 TX OE(2T, 0.5T) = (3, 3)
8803 23:03:21.121731
8804 23:03:21.121819
8805 23:03:21.128768 [DQSOSCAuto] RK0, (LSB)MR18= 0x80d, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 405 ps
8806 23:03:21.131780 CH1 RK0: MR19=303, MR18=80D
8807 23:03:21.138042 CH1_RK0: MR19=0x303, MR18=0x80D, DQSOSC=403, MR23=63, INC=22, DEC=15
8808 23:03:21.138142
8809 23:03:21.141512 ----->DramcWriteLeveling(PI) begin...
8810 23:03:21.141592 ==
8811 23:03:21.144736 Dram Type= 6, Freq= 0, CH_1, rank 1
8812 23:03:21.148332 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8813 23:03:21.148407 ==
8814 23:03:21.151555 Write leveling (Byte 0): 23 => 23
8815 23:03:21.155106 Write leveling (Byte 1): 26 => 26
8816 23:03:21.158123 DramcWriteLeveling(PI) end<-----
8817 23:03:21.158233
8818 23:03:21.158324 ==
8819 23:03:21.161567 Dram Type= 6, Freq= 0, CH_1, rank 1
8820 23:03:21.164722 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8821 23:03:21.164822 ==
8822 23:03:21.167964 [Gating] SW mode calibration
8823 23:03:21.174766 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8824 23:03:21.181634 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8825 23:03:21.184684 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8826 23:03:21.188035 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8827 23:03:21.194369 1 4 8 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
8828 23:03:21.197663 1 4 12 | B1->B0 | 3130 3434 | 1 1 | (1 1) (1 1)
8829 23:03:21.200868 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8830 23:03:21.207653 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8831 23:03:21.210863 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8832 23:03:21.214485 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8833 23:03:21.221017 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8834 23:03:21.224034 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8835 23:03:21.227402 1 5 8 | B1->B0 | 3434 2727 | 1 0 | (1 1) (1 0)
8836 23:03:21.233983 1 5 12 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
8837 23:03:21.237210 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8838 23:03:21.241011 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8839 23:03:21.247852 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8840 23:03:21.250843 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8841 23:03:21.253986 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8842 23:03:21.260790 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8843 23:03:21.264084 1 6 8 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
8844 23:03:21.267520 1 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8845 23:03:21.273905 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8846 23:03:21.277648 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8847 23:03:21.280364 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8848 23:03:21.287135 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8849 23:03:21.290789 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8850 23:03:21.293822 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8851 23:03:21.300220 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8852 23:03:21.304234 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8853 23:03:21.306908 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8854 23:03:21.313727 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8855 23:03:21.316868 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8856 23:03:21.320120 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8857 23:03:21.326893 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8858 23:03:21.330148 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8859 23:03:21.333533 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8860 23:03:21.340357 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8861 23:03:21.343567 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8862 23:03:21.346834 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8863 23:03:21.353333 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8864 23:03:21.356772 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8865 23:03:21.359987 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8866 23:03:21.366696 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8867 23:03:21.369969 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8868 23:03:21.373454 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8869 23:03:21.376882 Total UI for P1: 0, mck2ui 16
8870 23:03:21.380029 best dqsien dly found for B0: ( 1, 9, 8)
8871 23:03:21.383524 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8872 23:03:21.386581 Total UI for P1: 0, mck2ui 16
8873 23:03:21.389750 best dqsien dly found for B1: ( 1, 9, 12)
8874 23:03:21.393264 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8875 23:03:21.399815 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8876 23:03:21.399949
8877 23:03:21.403213 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8878 23:03:21.406418 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8879 23:03:21.409744 [Gating] SW calibration Done
8880 23:03:21.409848 ==
8881 23:03:21.413068 Dram Type= 6, Freq= 0, CH_1, rank 1
8882 23:03:21.416754 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8883 23:03:21.416849 ==
8884 23:03:21.419653 RX Vref Scan: 0
8885 23:03:21.419751
8886 23:03:21.419839 RX Vref 0 -> 0, step: 1
8887 23:03:21.419971
8888 23:03:21.423644 RX Delay 0 -> 252, step: 8
8889 23:03:21.426890 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8890 23:03:21.429552 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8891 23:03:21.436474 iDelay=200, Bit 2, Center 115 (56 ~ 175) 120
8892 23:03:21.439669 iDelay=200, Bit 3, Center 127 (64 ~ 191) 128
8893 23:03:21.442820 iDelay=200, Bit 4, Center 123 (64 ~ 183) 120
8894 23:03:21.446153 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8895 23:03:21.449408 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8896 23:03:21.456436 iDelay=200, Bit 7, Center 127 (64 ~ 191) 128
8897 23:03:21.459336 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8898 23:03:21.463063 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8899 23:03:21.466369 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8900 23:03:21.469509 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8901 23:03:21.476352 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8902 23:03:21.479231 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8903 23:03:21.482879 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8904 23:03:21.486035 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8905 23:03:21.486110 ==
8906 23:03:21.489387 Dram Type= 6, Freq= 0, CH_1, rank 1
8907 23:03:21.495966 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8908 23:03:21.496066 ==
8909 23:03:21.496158 DQS Delay:
8910 23:03:21.499587 DQS0 = 0, DQS1 = 0
8911 23:03:21.499665 DQM Delay:
8912 23:03:21.502769 DQM0 = 128, DQM1 = 128
8913 23:03:21.502845 DQ Delay:
8914 23:03:21.506023 DQ0 =131, DQ1 =127, DQ2 =115, DQ3 =127
8915 23:03:21.509492 DQ4 =123, DQ5 =139, DQ6 =139, DQ7 =127
8916 23:03:21.513051 DQ8 =111, DQ9 =115, DQ10 =131, DQ11 =123
8917 23:03:21.516032 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =139
8918 23:03:21.516137
8919 23:03:21.516268
8920 23:03:21.516356 ==
8921 23:03:21.519210 Dram Type= 6, Freq= 0, CH_1, rank 1
8922 23:03:21.525672 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8923 23:03:21.525775 ==
8924 23:03:21.525870
8925 23:03:21.525955
8926 23:03:21.526042 TX Vref Scan disable
8927 23:03:21.529619 == TX Byte 0 ==
8928 23:03:21.532398 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8929 23:03:21.535635 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8930 23:03:21.539008 == TX Byte 1 ==
8931 23:03:21.542394 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8932 23:03:21.549061 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8933 23:03:21.549164 ==
8934 23:03:21.552365 Dram Type= 6, Freq= 0, CH_1, rank 1
8935 23:03:21.555318 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8936 23:03:21.555426 ==
8937 23:03:21.568140
8938 23:03:21.571340 TX Vref early break, caculate TX vref
8939 23:03:21.574851 TX Vref=16, minBit 0, minWin=22, winSum=380
8940 23:03:21.577951 TX Vref=18, minBit 0, minWin=22, winSum=391
8941 23:03:21.581559 TX Vref=20, minBit 0, minWin=24, winSum=399
8942 23:03:21.584773 TX Vref=22, minBit 0, minWin=24, winSum=405
8943 23:03:21.587771 TX Vref=24, minBit 5, minWin=24, winSum=418
8944 23:03:21.594531 TX Vref=26, minBit 0, minWin=25, winSum=424
8945 23:03:21.598294 TX Vref=28, minBit 0, minWin=25, winSum=422
8946 23:03:21.601339 TX Vref=30, minBit 5, minWin=24, winSum=418
8947 23:03:21.604750 TX Vref=32, minBit 1, minWin=24, winSum=414
8948 23:03:21.608000 TX Vref=34, minBit 5, minWin=22, winSum=401
8949 23:03:21.614240 [TxChooseVref] Worse bit 0, Min win 25, Win sum 424, Final Vref 26
8950 23:03:21.614346
8951 23:03:21.617537 Final TX Range 0 Vref 26
8952 23:03:21.617641
8953 23:03:21.617731 ==
8954 23:03:21.620885 Dram Type= 6, Freq= 0, CH_1, rank 1
8955 23:03:21.624333 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8956 23:03:21.624408 ==
8957 23:03:21.624472
8958 23:03:21.624567
8959 23:03:21.627412 TX Vref Scan disable
8960 23:03:21.633946 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8961 23:03:21.634050 == TX Byte 0 ==
8962 23:03:21.637653 u2DelayCellOfst[0]=18 cells (5 PI)
8963 23:03:21.640934 u2DelayCellOfst[1]=15 cells (4 PI)
8964 23:03:21.644003 u2DelayCellOfst[2]=0 cells (0 PI)
8965 23:03:21.647272 u2DelayCellOfst[3]=3 cells (1 PI)
8966 23:03:21.650469 u2DelayCellOfst[4]=7 cells (2 PI)
8967 23:03:21.653822 u2DelayCellOfst[5]=18 cells (5 PI)
8968 23:03:21.657481 u2DelayCellOfst[6]=18 cells (5 PI)
8969 23:03:21.660587 u2DelayCellOfst[7]=3 cells (1 PI)
8970 23:03:21.663864 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8971 23:03:21.667255 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8972 23:03:21.670913 == TX Byte 1 ==
8973 23:03:21.674028 u2DelayCellOfst[8]=0 cells (0 PI)
8974 23:03:21.674140 u2DelayCellOfst[9]=7 cells (2 PI)
8975 23:03:21.677307 u2DelayCellOfst[10]=15 cells (4 PI)
8976 23:03:21.680178 u2DelayCellOfst[11]=7 cells (2 PI)
8977 23:03:21.684091 u2DelayCellOfst[12]=15 cells (4 PI)
8978 23:03:21.687418 u2DelayCellOfst[13]=18 cells (5 PI)
8979 23:03:21.690118 u2DelayCellOfst[14]=18 cells (5 PI)
8980 23:03:21.693422 u2DelayCellOfst[15]=18 cells (5 PI)
8981 23:03:21.696722 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8982 23:03:21.703283 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8983 23:03:21.703387 DramC Write-DBI on
8984 23:03:21.703477 ==
8985 23:03:21.707006 Dram Type= 6, Freq= 0, CH_1, rank 1
8986 23:03:21.713644 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8987 23:03:21.713746 ==
8988 23:03:21.713837
8989 23:03:21.713926
8990 23:03:21.714012 TX Vref Scan disable
8991 23:03:21.717435 == TX Byte 0 ==
8992 23:03:21.720648 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8993 23:03:21.724182 == TX Byte 1 ==
8994 23:03:21.727012 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8995 23:03:21.730627 DramC Write-DBI off
8996 23:03:21.730739
8997 23:03:21.730828 [DATLAT]
8998 23:03:21.730916 Freq=1600, CH1 RK1
8999 23:03:21.731004
9000 23:03:21.733684 DATLAT Default: 0xf
9001 23:03:21.733782 0, 0xFFFF, sum = 0
9002 23:03:21.737437 1, 0xFFFF, sum = 0
9003 23:03:21.740297 2, 0xFFFF, sum = 0
9004 23:03:21.740384 3, 0xFFFF, sum = 0
9005 23:03:21.743564 4, 0xFFFF, sum = 0
9006 23:03:21.743704 5, 0xFFFF, sum = 0
9007 23:03:21.747279 6, 0xFFFF, sum = 0
9008 23:03:21.747390 7, 0xFFFF, sum = 0
9009 23:03:21.750739 8, 0xFFFF, sum = 0
9010 23:03:21.750843 9, 0xFFFF, sum = 0
9011 23:03:21.753915 10, 0xFFFF, sum = 0
9012 23:03:21.753988 11, 0xFFFF, sum = 0
9013 23:03:21.757035 12, 0xFFFF, sum = 0
9014 23:03:21.757109 13, 0x8FFF, sum = 0
9015 23:03:21.760440 14, 0x0, sum = 1
9016 23:03:21.760537 15, 0x0, sum = 2
9017 23:03:21.763666 16, 0x0, sum = 3
9018 23:03:21.763760 17, 0x0, sum = 4
9019 23:03:21.767224 best_step = 15
9020 23:03:21.767319
9021 23:03:21.767393 ==
9022 23:03:21.770478 Dram Type= 6, Freq= 0, CH_1, rank 1
9023 23:03:21.773779 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9024 23:03:21.773914 ==
9025 23:03:21.774020 RX Vref Scan: 0
9026 23:03:21.777303
9027 23:03:21.777404 RX Vref 0 -> 0, step: 1
9028 23:03:21.777493
9029 23:03:21.780377 RX Delay 3 -> 252, step: 4
9030 23:03:21.783913 iDelay=195, Bit 0, Center 132 (79 ~ 186) 108
9031 23:03:21.790677 iDelay=195, Bit 1, Center 126 (75 ~ 178) 104
9032 23:03:21.793708 iDelay=195, Bit 2, Center 114 (59 ~ 170) 112
9033 23:03:21.796856 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
9034 23:03:21.800439 iDelay=195, Bit 4, Center 124 (67 ~ 182) 116
9035 23:03:21.803651 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
9036 23:03:21.810316 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
9037 23:03:21.813784 iDelay=195, Bit 7, Center 124 (67 ~ 182) 116
9038 23:03:21.816966 iDelay=195, Bit 8, Center 110 (55 ~ 166) 112
9039 23:03:21.820393 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
9040 23:03:21.823630 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9041 23:03:21.830591 iDelay=195, Bit 11, Center 118 (63 ~ 174) 112
9042 23:03:21.833818 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
9043 23:03:21.836900 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
9044 23:03:21.839837 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
9045 23:03:21.846929 iDelay=195, Bit 15, Center 134 (79 ~ 190) 112
9046 23:03:21.847006 ==
9047 23:03:21.850149 Dram Type= 6, Freq= 0, CH_1, rank 1
9048 23:03:21.853269 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9049 23:03:21.853376 ==
9050 23:03:21.853468 DQS Delay:
9051 23:03:21.856897 DQS0 = 0, DQS1 = 0
9052 23:03:21.856995 DQM Delay:
9053 23:03:21.859988 DQM0 = 127, DQM1 = 124
9054 23:03:21.860086 DQ Delay:
9055 23:03:21.863028 DQ0 =132, DQ1 =126, DQ2 =114, DQ3 =124
9056 23:03:21.866347 DQ4 =124, DQ5 =138, DQ6 =138, DQ7 =124
9057 23:03:21.869646 DQ8 =110, DQ9 =112, DQ10 =128, DQ11 =118
9058 23:03:21.873431 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =134
9059 23:03:21.873533
9060 23:03:21.873624
9061 23:03:21.873718
9062 23:03:21.876220 [DramC_TX_OE_Calibration] TA2
9063 23:03:21.879902 Original DQ_B0 (3 6) =30, OEN = 27
9064 23:03:21.883007 Original DQ_B1 (3 6) =30, OEN = 27
9065 23:03:21.886520 24, 0x0, End_B0=24 End_B1=24
9066 23:03:21.889678 25, 0x0, End_B0=25 End_B1=25
9067 23:03:21.893360 26, 0x0, End_B0=26 End_B1=26
9068 23:03:21.893463 27, 0x0, End_B0=27 End_B1=27
9069 23:03:21.896315 28, 0x0, End_B0=28 End_B1=28
9070 23:03:21.899465 29, 0x0, End_B0=29 End_B1=29
9071 23:03:21.903437 30, 0x0, End_B0=30 End_B1=30
9072 23:03:21.903544 31, 0x4545, End_B0=30 End_B1=30
9073 23:03:21.906453 Byte0 end_step=30 best_step=27
9074 23:03:21.910035 Byte1 end_step=30 best_step=27
9075 23:03:21.912888 Byte0 TX OE(2T, 0.5T) = (3, 3)
9076 23:03:21.916117 Byte1 TX OE(2T, 0.5T) = (3, 3)
9077 23:03:21.916250
9078 23:03:21.916315
9079 23:03:21.922806 [DQSOSCAuto] RK1, (LSB)MR18= 0x121e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 400 ps
9080 23:03:21.926378 CH1 RK1: MR19=303, MR18=121E
9081 23:03:21.932709 CH1_RK1: MR19=0x303, MR18=0x121E, DQSOSC=394, MR23=63, INC=23, DEC=15
9082 23:03:21.936440 [RxdqsGatingPostProcess] freq 1600
9083 23:03:21.942978 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9084 23:03:21.946287 best DQS0 dly(2T, 0.5T) = (1, 1)
9085 23:03:21.946387 best DQS1 dly(2T, 0.5T) = (1, 1)
9086 23:03:21.949930 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9087 23:03:21.952694 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9088 23:03:21.956101 best DQS0 dly(2T, 0.5T) = (1, 1)
9089 23:03:21.959429 best DQS1 dly(2T, 0.5T) = (1, 1)
9090 23:03:21.962677 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9091 23:03:21.966062 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9092 23:03:21.969739 Pre-setting of DQS Precalculation
9093 23:03:21.973023 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9094 23:03:21.983052 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9095 23:03:21.989469 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9096 23:03:21.989573
9097 23:03:21.989666
9098 23:03:21.992690 [Calibration Summary] 3200 Mbps
9099 23:03:21.992762 CH 0, Rank 0
9100 23:03:21.995838 SW Impedance : PASS
9101 23:03:21.995950 DUTY Scan : NO K
9102 23:03:21.999590 ZQ Calibration : PASS
9103 23:03:22.002546 Jitter Meter : NO K
9104 23:03:22.002643 CBT Training : PASS
9105 23:03:22.006335 Write leveling : PASS
9106 23:03:22.009037 RX DQS gating : PASS
9107 23:03:22.009136 RX DQ/DQS(RDDQC) : PASS
9108 23:03:22.012747 TX DQ/DQS : PASS
9109 23:03:22.015843 RX DATLAT : PASS
9110 23:03:22.015948 RX DQ/DQS(Engine): PASS
9111 23:03:22.019107 TX OE : PASS
9112 23:03:22.019207 All Pass.
9113 23:03:22.019294
9114 23:03:22.022289 CH 0, Rank 1
9115 23:03:22.022393 SW Impedance : PASS
9116 23:03:22.025902 DUTY Scan : NO K
9117 23:03:22.028818 ZQ Calibration : PASS
9118 23:03:22.028925 Jitter Meter : NO K
9119 23:03:22.032745 CBT Training : PASS
9120 23:03:22.032851 Write leveling : PASS
9121 23:03:22.035783 RX DQS gating : PASS
9122 23:03:22.038791 RX DQ/DQS(RDDQC) : PASS
9123 23:03:22.038874 TX DQ/DQS : PASS
9124 23:03:22.042379 RX DATLAT : PASS
9125 23:03:22.045440 RX DQ/DQS(Engine): PASS
9126 23:03:22.045511 TX OE : PASS
9127 23:03:22.048917 All Pass.
9128 23:03:22.049018
9129 23:03:22.049146 CH 1, Rank 0
9130 23:03:22.052599 SW Impedance : PASS
9131 23:03:22.052673 DUTY Scan : NO K
9132 23:03:22.055861 ZQ Calibration : PASS
9133 23:03:22.059178 Jitter Meter : NO K
9134 23:03:22.059283 CBT Training : PASS
9135 23:03:22.062394 Write leveling : PASS
9136 23:03:22.065451 RX DQS gating : PASS
9137 23:03:22.065566 RX DQ/DQS(RDDQC) : PASS
9138 23:03:22.068585 TX DQ/DQS : PASS
9139 23:03:22.072323 RX DATLAT : PASS
9140 23:03:22.072404 RX DQ/DQS(Engine): PASS
9141 23:03:22.075473 TX OE : PASS
9142 23:03:22.075575 All Pass.
9143 23:03:22.075675
9144 23:03:22.078754 CH 1, Rank 1
9145 23:03:22.078863 SW Impedance : PASS
9146 23:03:22.082165 DUTY Scan : NO K
9147 23:03:22.085179 ZQ Calibration : PASS
9148 23:03:22.085283 Jitter Meter : NO K
9149 23:03:22.088848 CBT Training : PASS
9150 23:03:22.088925 Write leveling : PASS
9151 23:03:22.092031 RX DQS gating : PASS
9152 23:03:22.095187 RX DQ/DQS(RDDQC) : PASS
9153 23:03:22.095284 TX DQ/DQS : PASS
9154 23:03:22.098572 RX DATLAT : PASS
9155 23:03:22.101847 RX DQ/DQS(Engine): PASS
9156 23:03:22.101923 TX OE : PASS
9157 23:03:22.105614 All Pass.
9158 23:03:22.105693
9159 23:03:22.105783 DramC Write-DBI on
9160 23:03:22.108468 PER_BANK_REFRESH: Hybrid Mode
9161 23:03:22.111885 TX_TRACKING: ON
9162 23:03:22.118574 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9163 23:03:22.128542 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9164 23:03:22.135443 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9165 23:03:22.138109 [FAST_K] Save calibration result to emmc
9166 23:03:22.141675 sync common calibartion params.
9167 23:03:22.141800 sync cbt_mode0:1, 1:1
9168 23:03:22.144928 dram_init: ddr_geometry: 2
9169 23:03:22.148082 dram_init: ddr_geometry: 2
9170 23:03:22.151313 dram_init: ddr_geometry: 2
9171 23:03:22.151420 0:dram_rank_size:100000000
9172 23:03:22.155089 1:dram_rank_size:100000000
9173 23:03:22.161373 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9174 23:03:22.161456 DFS_SHUFFLE_HW_MODE: ON
9175 23:03:22.168230 dramc_set_vcore_voltage set vcore to 725000
9176 23:03:22.168358 Read voltage for 1600, 0
9177 23:03:22.171413 Vio18 = 0
9178 23:03:22.171534 Vcore = 725000
9179 23:03:22.171625 Vdram = 0
9180 23:03:22.174448 Vddq = 0
9181 23:03:22.174533 Vmddr = 0
9182 23:03:22.177817 switch to 3200 Mbps bootup
9183 23:03:22.177968 [DramcRunTimeConfig]
9184 23:03:22.178089 PHYPLL
9185 23:03:22.181435 DPM_CONTROL_AFTERK: ON
9186 23:03:22.184679 PER_BANK_REFRESH: ON
9187 23:03:22.184776 REFRESH_OVERHEAD_REDUCTION: ON
9188 23:03:22.188014 CMD_PICG_NEW_MODE: OFF
9189 23:03:22.191047 XRTWTW_NEW_MODE: ON
9190 23:03:22.191145 XRTRTR_NEW_MODE: ON
9191 23:03:22.191282 TX_TRACKING: ON
9192 23:03:22.194586 RDSEL_TRACKING: OFF
9193 23:03:22.197755 DQS Precalculation for DVFS: ON
9194 23:03:22.197866 RX_TRACKING: OFF
9195 23:03:22.201615 HW_GATING DBG: ON
9196 23:03:22.201691 ZQCS_ENABLE_LP4: ON
9197 23:03:22.204726 RX_PICG_NEW_MODE: ON
9198 23:03:22.207962 TX_PICG_NEW_MODE: ON
9199 23:03:22.208064 ENABLE_RX_DCM_DPHY: ON
9200 23:03:22.211166 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9201 23:03:22.214469 DUMMY_READ_FOR_TRACKING: OFF
9202 23:03:22.218057 !!! SPM_CONTROL_AFTERK: OFF
9203 23:03:22.218178 !!! SPM could not control APHY
9204 23:03:22.221302 IMPEDANCE_TRACKING: ON
9205 23:03:22.221411 TEMP_SENSOR: ON
9206 23:03:22.224505 HW_SAVE_FOR_SR: OFF
9207 23:03:22.228092 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9208 23:03:22.231344 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9209 23:03:22.234682 Read ODT Tracking: ON
9210 23:03:22.234790 Refresh Rate DeBounce: ON
9211 23:03:22.237809 DFS_NO_QUEUE_FLUSH: ON
9212 23:03:22.240820 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9213 23:03:22.244077 ENABLE_DFS_RUNTIME_MRW: OFF
9214 23:03:22.244175 DDR_RESERVE_NEW_MODE: ON
9215 23:03:22.247762 MR_CBT_SWITCH_FREQ: ON
9216 23:03:22.250890 =========================
9217 23:03:22.268601 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9218 23:03:22.271801 dram_init: ddr_geometry: 2
9219 23:03:22.290352 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9220 23:03:22.293880 dram_init: dram init end (result: 0)
9221 23:03:22.300128 DRAM-K: Full calibration passed in 24581 msecs
9222 23:03:22.303405 MRC: failed to locate region type 0.
9223 23:03:22.303505 DRAM rank0 size:0x100000000,
9224 23:03:22.306720 DRAM rank1 size=0x100000000
9225 23:03:22.316637 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9226 23:03:22.323546 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9227 23:03:22.329985 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9228 23:03:22.339736 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9229 23:03:22.339816 DRAM rank0 size:0x100000000,
9230 23:03:22.343410 DRAM rank1 size=0x100000000
9231 23:03:22.343511 CBMEM:
9232 23:03:22.346700 IMD: root @ 0xfffff000 254 entries.
9233 23:03:22.349883 IMD: root @ 0xffffec00 62 entries.
9234 23:03:22.352975 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9235 23:03:22.359820 WARNING: RO_VPD is uninitialized or empty.
9236 23:03:22.363063 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9237 23:03:22.370306 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9238 23:03:22.382968 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9239 23:03:22.394401 BS: romstage times (exec / console): total (unknown) / 24042 ms
9240 23:03:22.394483
9241 23:03:22.394548
9242 23:03:22.404415 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9243 23:03:22.407868 ARM64: Exception handlers installed.
9244 23:03:22.410917 ARM64: Testing exception
9245 23:03:22.414124 ARM64: Done test exception
9246 23:03:22.414199 Enumerating buses...
9247 23:03:22.418004 Show all devs... Before device enumeration.
9248 23:03:22.421191 Root Device: enabled 1
9249 23:03:22.424515 CPU_CLUSTER: 0: enabled 1
9250 23:03:22.424593 CPU: 00: enabled 1
9251 23:03:22.427582 Compare with tree...
9252 23:03:22.427659 Root Device: enabled 1
9253 23:03:22.430830 CPU_CLUSTER: 0: enabled 1
9254 23:03:22.434043 CPU: 00: enabled 1
9255 23:03:22.434124 Root Device scanning...
9256 23:03:22.437703 scan_static_bus for Root Device
9257 23:03:22.440926 CPU_CLUSTER: 0 enabled
9258 23:03:22.444362 scan_static_bus for Root Device done
9259 23:03:22.447407 scan_bus: bus Root Device finished in 8 msecs
9260 23:03:22.447485 done
9261 23:03:22.454147 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9262 23:03:22.457672 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9263 23:03:22.464276 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9264 23:03:22.467251 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9265 23:03:22.470914 Allocating resources...
9266 23:03:22.474195 Reading resources...
9267 23:03:22.477149 Root Device read_resources bus 0 link: 0
9268 23:03:22.477235 DRAM rank0 size:0x100000000,
9269 23:03:22.480974 DRAM rank1 size=0x100000000
9270 23:03:22.484291 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9271 23:03:22.487584 CPU: 00 missing read_resources
9272 23:03:22.494095 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9273 23:03:22.497499 Root Device read_resources bus 0 link: 0 done
9274 23:03:22.497573 Done reading resources.
9275 23:03:22.503918 Show resources in subtree (Root Device)...After reading.
9276 23:03:22.507145 Root Device child on link 0 CPU_CLUSTER: 0
9277 23:03:22.510689 CPU_CLUSTER: 0 child on link 0 CPU: 00
9278 23:03:22.520326 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9279 23:03:22.520407 CPU: 00
9280 23:03:22.523432 Root Device assign_resources, bus 0 link: 0
9281 23:03:22.527408 CPU_CLUSTER: 0 missing set_resources
9282 23:03:22.533754 Root Device assign_resources, bus 0 link: 0 done
9283 23:03:22.533835 Done setting resources.
9284 23:03:22.540152 Show resources in subtree (Root Device)...After assigning values.
9285 23:03:22.543275 Root Device child on link 0 CPU_CLUSTER: 0
9286 23:03:22.546495 CPU_CLUSTER: 0 child on link 0 CPU: 00
9287 23:03:22.556590 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9288 23:03:22.556670 CPU: 00
9289 23:03:22.559874 Done allocating resources.
9290 23:03:22.566333 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9291 23:03:22.566407 Enabling resources...
9292 23:03:22.566470 done.
9293 23:03:22.572955 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9294 23:03:22.573033 Initializing devices...
9295 23:03:22.576729 Root Device init
9296 23:03:22.579658 init hardware done!
9297 23:03:22.579728 0x00000018: ctrlr->caps
9298 23:03:22.582847 52.000 MHz: ctrlr->f_max
9299 23:03:22.586456 0.400 MHz: ctrlr->f_min
9300 23:03:22.586535 0x40ff8080: ctrlr->voltages
9301 23:03:22.589738 sclk: 390625
9302 23:03:22.589814 Bus Width = 1
9303 23:03:22.589876 sclk: 390625
9304 23:03:22.593013 Bus Width = 1
9305 23:03:22.593088 Early init status = 3
9306 23:03:22.599597 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9307 23:03:22.603479 in-header: 03 fc 00 00 01 00 00 00
9308 23:03:22.606496 in-data: 00
9309 23:03:22.609741 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9310 23:03:22.613475 in-header: 03 fd 00 00 00 00 00 00
9311 23:03:22.616791 in-data:
9312 23:03:22.619813 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9313 23:03:22.623680 in-header: 03 fc 00 00 01 00 00 00
9314 23:03:22.627025 in-data: 00
9315 23:03:22.630110 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9316 23:03:22.635949 in-header: 03 fd 00 00 00 00 00 00
9317 23:03:22.639148 in-data:
9318 23:03:22.642468 [SSUSB] Setting up USB HOST controller...
9319 23:03:22.645677 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9320 23:03:22.649082 [SSUSB] phy power-on done.
9321 23:03:22.652439 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9322 23:03:22.659042 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9323 23:03:22.662772 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9324 23:03:22.669625 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9325 23:03:22.675763 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9326 23:03:22.682090 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9327 23:03:22.688856 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9328 23:03:22.695984 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9329 23:03:22.699100 SPM: binary array size = 0x9dc
9330 23:03:22.702208 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9331 23:03:22.708972 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9332 23:03:22.715362 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9333 23:03:22.719050 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9334 23:03:22.725375 configure_display: Starting display init
9335 23:03:22.759293 anx7625_power_on_init: Init interface.
9336 23:03:22.762456 anx7625_disable_pd_protocol: Disabled PD feature.
9337 23:03:22.765581 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9338 23:03:22.793896 anx7625_start_dp_work: Secure OCM version=00
9339 23:03:22.797061 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9340 23:03:22.811752 sp_tx_get_edid_block: EDID Block = 1
9341 23:03:22.914250 Extracted contents:
9342 23:03:22.917832 header: 00 ff ff ff ff ff ff 00
9343 23:03:22.920609 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9344 23:03:22.924018 version: 01 04
9345 23:03:22.927321 basic params: 95 1f 11 78 0a
9346 23:03:22.930797 chroma info: 76 90 94 55 54 90 27 21 50 54
9347 23:03:22.934211 established: 00 00 00
9348 23:03:22.940375 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9349 23:03:22.944170 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9350 23:03:22.950571 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9351 23:03:22.957325 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9352 23:03:22.963714 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9353 23:03:22.966913 extensions: 00
9354 23:03:22.966987 checksum: fb
9355 23:03:22.967051
9356 23:03:22.970540 Manufacturer: IVO Model 57d Serial Number 0
9357 23:03:22.973729 Made week 0 of 2020
9358 23:03:22.973807 EDID version: 1.4
9359 23:03:22.977008 Digital display
9360 23:03:22.980367 6 bits per primary color channel
9361 23:03:22.980485 DisplayPort interface
9362 23:03:22.983650 Maximum image size: 31 cm x 17 cm
9363 23:03:22.987353 Gamma: 220%
9364 23:03:22.987426 Check DPMS levels
9365 23:03:22.990450 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9366 23:03:22.996988 First detailed timing is preferred timing
9367 23:03:22.997068 Established timings supported:
9368 23:03:23.000375 Standard timings supported:
9369 23:03:23.003567 Detailed timings
9370 23:03:23.007150 Hex of detail: 383680a07038204018303c0035ae10000019
9371 23:03:23.010103 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9372 23:03:23.016721 0780 0798 07c8 0820 hborder 0
9373 23:03:23.020108 0438 043b 0447 0458 vborder 0
9374 23:03:23.023421 -hsync -vsync
9375 23:03:23.023516 Did detailed timing
9376 23:03:23.030038 Hex of detail: 000000000000000000000000000000000000
9377 23:03:23.033178 Manufacturer-specified data, tag 0
9378 23:03:23.036566 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9379 23:03:23.039947 ASCII string: InfoVision
9380 23:03:23.043304 Hex of detail: 000000fe00523134304e574635205248200a
9381 23:03:23.046589 ASCII string: R140NWF5 RH
9382 23:03:23.046660 Checksum
9383 23:03:23.050000 Checksum: 0xfb (valid)
9384 23:03:23.053092 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9385 23:03:23.056731 DSI data_rate: 832800000 bps
9386 23:03:23.063060 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9387 23:03:23.066404 anx7625_parse_edid: pixelclock(138800).
9388 23:03:23.069516 hactive(1920), hsync(48), hfp(24), hbp(88)
9389 23:03:23.072678 vactive(1080), vsync(12), vfp(3), vbp(17)
9390 23:03:23.076439 anx7625_dsi_config: config dsi.
9391 23:03:23.082887 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9392 23:03:23.096035 anx7625_dsi_config: success to config DSI
9393 23:03:23.099763 anx7625_dp_start: MIPI phy setup OK.
9394 23:03:23.102826 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9395 23:03:23.106080 mtk_ddp_mode_set invalid vrefresh 60
9396 23:03:23.109957 main_disp_path_setup
9397 23:03:23.110059 ovl_layer_smi_id_en
9398 23:03:23.112549 ovl_layer_smi_id_en
9399 23:03:23.112656 ccorr_config
9400 23:03:23.112747 aal_config
9401 23:03:23.116652 gamma_config
9402 23:03:23.116727 postmask_config
9403 23:03:23.119839 dither_config
9404 23:03:23.122926 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9405 23:03:23.129287 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9406 23:03:23.133008 Root Device init finished in 552 msecs
9407 23:03:23.135747 CPU_CLUSTER: 0 init
9408 23:03:23.142424 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9409 23:03:23.145844 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9410 23:03:23.149376 APU_MBOX 0x190000b0 = 0x10001
9411 23:03:23.152702 APU_MBOX 0x190001b0 = 0x10001
9412 23:03:23.155837 APU_MBOX 0x190005b0 = 0x10001
9413 23:03:23.158953 APU_MBOX 0x190006b0 = 0x10001
9414 23:03:23.162301 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9415 23:03:23.175002 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9416 23:03:23.187687 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9417 23:03:23.193964 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9418 23:03:23.205698 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9419 23:03:23.215036 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9420 23:03:23.218157 CPU_CLUSTER: 0 init finished in 81 msecs
9421 23:03:23.221349 Devices initialized
9422 23:03:23.224761 Show all devs... After init.
9423 23:03:23.224864 Root Device: enabled 1
9424 23:03:23.228498 CPU_CLUSTER: 0: enabled 1
9425 23:03:23.231409 CPU: 00: enabled 1
9426 23:03:23.234868 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9427 23:03:23.238386 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9428 23:03:23.241653 ELOG: NV offset 0x57f000 size 0x1000
9429 23:03:23.248235 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9430 23:03:23.254945 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9431 23:03:23.258389 ELOG: Event(17) added with size 13 at 2023-12-01 23:03:25 UTC
9432 23:03:23.261373 out: cmd=0x121: 03 db 21 01 00 00 00 00
9433 23:03:23.265312 in-header: 03 52 00 00 2c 00 00 00
9434 23:03:23.278384 in-data: 0c 69 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9435 23:03:23.285167 ELOG: Event(A1) added with size 10 at 2023-12-01 23:03:25 UTC
9436 23:03:23.291638 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9437 23:03:23.298357 ELOG: Event(A0) added with size 9 at 2023-12-01 23:03:25 UTC
9438 23:03:23.301860 elog_add_boot_reason: Logged dev mode boot
9439 23:03:23.304775 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9440 23:03:23.308190 Finalize devices...
9441 23:03:23.308314 Devices finalized
9442 23:03:23.314694 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9443 23:03:23.317925 Writing coreboot table at 0xffe64000
9444 23:03:23.321837 0. 000000000010a000-0000000000113fff: RAMSTAGE
9445 23:03:23.324970 1. 0000000040000000-00000000400fffff: RAM
9446 23:03:23.331445 2. 0000000040100000-000000004032afff: RAMSTAGE
9447 23:03:23.334736 3. 000000004032b000-00000000545fffff: RAM
9448 23:03:23.338229 4. 0000000054600000-000000005465ffff: BL31
9449 23:03:23.341467 5. 0000000054660000-00000000ffe63fff: RAM
9450 23:03:23.348143 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9451 23:03:23.351448 7. 0000000100000000-000000023fffffff: RAM
9452 23:03:23.351546 Passing 5 GPIOs to payload:
9453 23:03:23.358148 NAME | PORT | POLARITY | VALUE
9454 23:03:23.361109 EC in RW | 0x000000aa | low | undefined
9455 23:03:23.368353 EC interrupt | 0x00000005 | low | undefined
9456 23:03:23.371368 TPM interrupt | 0x000000ab | high | undefined
9457 23:03:23.378046 SD card detect | 0x00000011 | high | undefined
9458 23:03:23.381213 speaker enable | 0x00000093 | high | undefined
9459 23:03:23.384316 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9460 23:03:23.388143 in-header: 03 f9 00 00 02 00 00 00
9461 23:03:23.391514 in-data: 02 00
9462 23:03:23.391626 ADC[4]: Raw value=894821 ID=7
9463 23:03:23.394766 ADC[3]: Raw value=213440 ID=1
9464 23:03:23.397919 RAM Code: 0x71
9465 23:03:23.397993 ADC[6]: Raw value=75092 ID=0
9466 23:03:23.401324 ADC[5]: Raw value=212330 ID=1
9467 23:03:23.404497 SKU Code: 0x1
9468 23:03:23.408118 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 59ba
9469 23:03:23.411300 coreboot table: 964 bytes.
9470 23:03:23.414862 IMD ROOT 0. 0xfffff000 0x00001000
9471 23:03:23.418342 IMD SMALL 1. 0xffffe000 0x00001000
9472 23:03:23.420960 RO MCACHE 2. 0xffffc000 0x00001104
9473 23:03:23.424192 CONSOLE 3. 0xfff7c000 0x00080000
9474 23:03:23.427564 FMAP 4. 0xfff7b000 0x00000452
9475 23:03:23.430657 TIME STAMP 5. 0xfff7a000 0x00000910
9476 23:03:23.434055 VBOOT WORK 6. 0xfff66000 0x00014000
9477 23:03:23.437654 RAMOOPS 7. 0xffe66000 0x00100000
9478 23:03:23.440720 COREBOOT 8. 0xffe64000 0x00002000
9479 23:03:23.440817 IMD small region:
9480 23:03:23.444389 IMD ROOT 0. 0xffffec00 0x00000400
9481 23:03:23.447261 VPD 1. 0xffffeb80 0x0000006c
9482 23:03:23.453854 MMC STATUS 2. 0xffffeb60 0x00000004
9483 23:03:23.457473 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9484 23:03:23.460615 Probing TPM: done!
9485 23:03:23.464091 Connected to device vid:did:rid of 1ae0:0028:00
9486 23:03:23.474320 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9487 23:03:23.477493 Initialized TPM device CR50 revision 0
9488 23:03:23.481191 Checking cr50 for pending updates
9489 23:03:23.484721 Reading cr50 TPM mode
9490 23:03:23.494156 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9491 23:03:23.500128 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9492 23:03:23.540131 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9493 23:03:23.543519 Checking segment from ROM address 0x40100000
9494 23:03:23.546826 Checking segment from ROM address 0x4010001c
9495 23:03:23.553455 Loading segment from ROM address 0x40100000
9496 23:03:23.553557 code (compression=0)
9497 23:03:23.563424 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9498 23:03:23.570350 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9499 23:03:23.570462 it's not compressed!
9500 23:03:23.577183 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9501 23:03:23.583492 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9502 23:03:23.600630 Loading segment from ROM address 0x4010001c
9503 23:03:23.600743 Entry Point 0x80000000
9504 23:03:23.604008 Loaded segments
9505 23:03:23.607426 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9506 23:03:23.613955 Jumping to boot code at 0x80000000(0xffe64000)
9507 23:03:23.620585 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9508 23:03:23.627446 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9509 23:03:23.635247 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9510 23:03:23.638735 Checking segment from ROM address 0x40100000
9511 23:03:23.641704 Checking segment from ROM address 0x4010001c
9512 23:03:23.648729 Loading segment from ROM address 0x40100000
9513 23:03:23.648804 code (compression=1)
9514 23:03:23.655166 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9515 23:03:23.665136 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9516 23:03:23.665232 using LZMA
9517 23:03:23.673336 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9518 23:03:23.680066 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9519 23:03:23.683549 Loading segment from ROM address 0x4010001c
9520 23:03:23.683694 Entry Point 0x54601000
9521 23:03:23.686821 Loaded segments
9522 23:03:23.689906 NOTICE: MT8192 bl31_setup
9523 23:03:23.696912 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9524 23:03:23.700999 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9525 23:03:23.703798 WARNING: region 0:
9526 23:03:23.707171 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9527 23:03:23.707248 WARNING: region 1:
9528 23:03:23.713664 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9529 23:03:23.716974 WARNING: region 2:
9530 23:03:23.720470 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9531 23:03:23.723456 WARNING: region 3:
9532 23:03:23.727139 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9533 23:03:23.730327 WARNING: region 4:
9534 23:03:23.737273 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9535 23:03:23.737365 WARNING: region 5:
9536 23:03:23.740522 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9537 23:03:23.743601 WARNING: region 6:
9538 23:03:23.747529 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9539 23:03:23.750529 WARNING: region 7:
9540 23:03:23.753930 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9541 23:03:23.760406 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9542 23:03:23.763962 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9543 23:03:23.767336 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9544 23:03:23.773875 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9545 23:03:23.777447 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9546 23:03:23.780184 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9547 23:03:23.787162 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9548 23:03:23.790759 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9549 23:03:23.794223 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9550 23:03:23.800715 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9551 23:03:23.803981 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9552 23:03:23.807183 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9553 23:03:23.814174 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9554 23:03:23.817610 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9555 23:03:23.823711 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9556 23:03:23.827213 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9557 23:03:23.830499 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9558 23:03:23.836959 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9559 23:03:23.840588 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9560 23:03:23.847090 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9561 23:03:23.850228 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9562 23:03:23.853411 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9563 23:03:23.860322 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9564 23:03:23.863695 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9565 23:03:23.870552 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9566 23:03:23.873889 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9567 23:03:23.876962 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9568 23:03:23.883673 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9569 23:03:23.887376 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9570 23:03:23.890286 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9571 23:03:23.897123 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9572 23:03:23.900791 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9573 23:03:23.906871 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9574 23:03:23.910613 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9575 23:03:23.913998 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9576 23:03:23.916988 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9577 23:03:23.920480 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9578 23:03:23.926980 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9579 23:03:23.930494 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9580 23:03:23.933972 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9581 23:03:23.937060 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9582 23:03:23.943792 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9583 23:03:23.947114 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9584 23:03:23.950510 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9585 23:03:23.956900 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9586 23:03:23.960538 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9587 23:03:23.963718 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9588 23:03:23.966936 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9589 23:03:23.973579 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9590 23:03:23.976869 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9591 23:03:23.983484 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9592 23:03:23.987117 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9593 23:03:23.990248 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9594 23:03:23.996862 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9595 23:03:24.000090 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9596 23:03:24.007035 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9597 23:03:24.010133 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9598 23:03:24.016966 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9599 23:03:24.020344 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9600 23:03:24.023607 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9601 23:03:24.030390 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9602 23:03:24.033612 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9603 23:03:24.040669 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9604 23:03:24.043730 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9605 23:03:24.050309 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9606 23:03:24.053879 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9607 23:03:24.056738 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9608 23:03:24.063702 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9609 23:03:24.067143 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9610 23:03:24.073440 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9611 23:03:24.076879 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9612 23:03:24.083463 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9613 23:03:24.086919 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9614 23:03:24.090632 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9615 23:03:24.097036 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9616 23:03:24.100453 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9617 23:03:24.107127 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9618 23:03:24.110242 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9619 23:03:24.116881 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9620 23:03:24.120629 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9621 23:03:24.126905 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9622 23:03:24.130111 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9623 23:03:24.133549 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9624 23:03:24.140681 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9625 23:03:24.144021 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9626 23:03:24.150134 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9627 23:03:24.153584 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9628 23:03:24.157339 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9629 23:03:24.163808 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9630 23:03:24.167388 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9631 23:03:24.173764 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9632 23:03:24.176891 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9633 23:03:24.183535 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9634 23:03:24.187333 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9635 23:03:24.194025 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9636 23:03:24.196999 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9637 23:03:24.199954 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9638 23:03:24.206891 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9639 23:03:24.210358 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9640 23:03:24.213504 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9641 23:03:24.216930 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9642 23:03:24.223491 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9643 23:03:24.226762 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9644 23:03:24.233202 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9645 23:03:24.236484 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9646 23:03:24.240144 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9647 23:03:24.246466 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9648 23:03:24.250065 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9649 23:03:24.256426 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9650 23:03:24.259733 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9651 23:03:24.263102 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9652 23:03:24.269857 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9653 23:03:24.273456 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9654 23:03:24.280132 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9655 23:03:24.283335 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9656 23:03:24.286511 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9657 23:03:24.289830 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9658 23:03:24.296749 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9659 23:03:24.299996 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9660 23:03:24.306217 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9661 23:03:24.309946 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9662 23:03:24.313436 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9663 23:03:24.316300 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9664 23:03:24.319915 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9665 23:03:24.326509 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9666 23:03:24.329711 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9667 23:03:24.336086 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9668 23:03:24.339935 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9669 23:03:24.343046 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9670 23:03:24.349645 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9671 23:03:24.353339 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9672 23:03:24.359546 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9673 23:03:24.363236 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9674 23:03:24.366223 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9675 23:03:24.373214 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9676 23:03:24.376276 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9677 23:03:24.382901 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9678 23:03:24.386559 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9679 23:03:24.389828 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9680 23:03:24.396224 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9681 23:03:24.399800 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9682 23:03:24.403075 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9683 23:03:24.409909 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9684 23:03:24.413096 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9685 23:03:24.419630 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9686 23:03:24.422968 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9687 23:03:24.426321 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9688 23:03:24.433193 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9689 23:03:24.436339 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9690 23:03:24.442950 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9691 23:03:24.446588 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9692 23:03:24.449457 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9693 23:03:24.456121 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9694 23:03:24.459727 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9695 23:03:24.463100 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9696 23:03:24.469604 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9697 23:03:24.472904 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9698 23:03:24.479531 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9699 23:03:24.483132 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9700 23:03:24.486168 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9701 23:03:24.492877 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9702 23:03:24.495986 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9703 23:03:24.502751 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9704 23:03:24.506061 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9705 23:03:24.509637 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9706 23:03:24.516105 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9707 23:03:24.519565 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9708 23:03:24.525986 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9709 23:03:24.529895 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9710 23:03:24.532692 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9711 23:03:24.539105 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9712 23:03:24.542280 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9713 23:03:24.545580 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9714 23:03:24.552504 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9715 23:03:24.555916 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9716 23:03:24.562230 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9717 23:03:24.565496 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9718 23:03:24.572065 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9719 23:03:24.575653 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9720 23:03:24.578805 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9721 23:03:24.585701 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9722 23:03:24.588771 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9723 23:03:24.592155 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9724 23:03:24.598882 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9725 23:03:24.601836 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9726 23:03:24.608736 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9727 23:03:24.611973 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9728 23:03:24.615385 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9729 23:03:24.621719 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9730 23:03:24.625134 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9731 23:03:24.631970 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9732 23:03:24.634900 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9733 23:03:24.641636 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9734 23:03:24.644969 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9735 23:03:24.648343 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9736 23:03:24.655211 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9737 23:03:24.658675 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9738 23:03:24.664882 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9739 23:03:24.668191 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9740 23:03:24.674666 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9741 23:03:24.677924 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9742 23:03:24.681642 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9743 23:03:24.688020 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9744 23:03:24.691277 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9745 23:03:24.697993 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9746 23:03:24.701105 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9747 23:03:24.708234 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9748 23:03:24.711133 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9749 23:03:24.714297 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9750 23:03:24.721110 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9751 23:03:24.724402 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9752 23:03:24.731076 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9753 23:03:24.734559 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9754 23:03:24.737667 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9755 23:03:24.744333 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9756 23:03:24.747489 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9757 23:03:24.754085 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9758 23:03:24.757252 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9759 23:03:24.763805 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9760 23:03:24.767026 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9761 23:03:24.770853 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9762 23:03:24.777051 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9763 23:03:24.780337 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9764 23:03:24.786850 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9765 23:03:24.790845 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9766 23:03:24.797226 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9767 23:03:24.800293 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9768 23:03:24.803597 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9769 23:03:24.810109 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9770 23:03:24.813963 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9771 23:03:24.817007 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9772 23:03:24.820251 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9773 23:03:24.826757 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9774 23:03:24.830214 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9775 23:03:24.833585 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9776 23:03:24.840120 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9777 23:03:24.843726 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9778 23:03:24.847066 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9779 23:03:24.853258 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9780 23:03:24.856704 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9781 23:03:24.860030 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9782 23:03:24.866938 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9783 23:03:24.870170 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9784 23:03:24.876533 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9785 23:03:24.880196 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9786 23:03:24.883429 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9787 23:03:24.889893 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9788 23:03:24.893143 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9789 23:03:24.896601 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9790 23:03:24.902928 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9791 23:03:24.906508 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9792 23:03:24.913065 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9793 23:03:24.916524 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9794 23:03:24.919829 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9795 23:03:24.926083 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9796 23:03:24.929488 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9797 23:03:24.932882 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9798 23:03:24.939598 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9799 23:03:24.942928 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9800 23:03:24.949112 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9801 23:03:24.952587 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9802 23:03:24.955755 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9803 23:03:24.962614 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9804 23:03:24.966167 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9805 23:03:24.969207 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9806 23:03:24.975981 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9807 23:03:24.978899 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9808 23:03:24.985654 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9809 23:03:24.989157 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9810 23:03:24.992420 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9811 23:03:24.995622 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9812 23:03:24.998874 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9813 23:03:25.005571 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9814 23:03:25.009080 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9815 23:03:25.012142 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9816 23:03:25.015370 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9817 23:03:25.021917 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9818 23:03:25.025333 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9819 23:03:25.029117 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9820 23:03:25.032212 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9821 23:03:25.038613 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9822 23:03:25.041517 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9823 23:03:25.048335 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9824 23:03:25.052006 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9825 23:03:25.055129 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9826 23:03:25.061758 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9827 23:03:25.064931 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9828 23:03:25.071841 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9829 23:03:25.076660 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9830 23:03:25.078390 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9831 23:03:25.085171 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9832 23:03:25.088100 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9833 23:03:25.094865 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9834 23:03:25.097971 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9835 23:03:25.104795 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9836 23:03:25.107968 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9837 23:03:25.112020 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9838 23:03:25.118341 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9839 23:03:25.121440 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9840 23:03:25.127868 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9841 23:03:25.131268 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9842 23:03:25.134404 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9843 23:03:25.141032 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9844 23:03:25.144989 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9845 23:03:25.151096 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9846 23:03:25.154859 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9847 23:03:25.157750 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9848 23:03:25.164599 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9849 23:03:25.167952 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9850 23:03:25.174663 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9851 23:03:25.177929 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9852 23:03:25.184166 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9853 23:03:25.187862 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9854 23:03:25.190933 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9855 23:03:25.197703 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9856 23:03:25.201040 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9857 23:03:25.207538 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9858 23:03:25.211191 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9859 23:03:25.214103 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9860 23:03:25.220901 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9861 23:03:25.224093 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9862 23:03:25.230884 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9863 23:03:25.234302 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9864 23:03:25.237484 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9865 23:03:25.244029 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9866 23:03:25.247475 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9867 23:03:25.253856 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9868 23:03:25.256952 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9869 23:03:25.263933 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9870 23:03:25.267196 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9871 23:03:25.270361 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9872 23:03:25.277219 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9873 23:03:25.280093 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9874 23:03:25.286770 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9875 23:03:25.290308 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9876 23:03:25.293346 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9877 23:03:25.300144 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9878 23:03:25.303409 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9879 23:03:25.309903 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9880 23:03:25.313122 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9881 23:03:25.316734 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9882 23:03:25.323504 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9883 23:03:25.326445 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9884 23:03:25.333479 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9885 23:03:25.336706 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9886 23:03:25.339554 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9887 23:03:25.346422 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9888 23:03:25.350058 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9889 23:03:25.356231 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9890 23:03:25.359905 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9891 23:03:25.366295 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9892 23:03:25.369814 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9893 23:03:25.372838 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9894 23:03:25.379666 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9895 23:03:25.383039 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9896 23:03:25.389631 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9897 23:03:25.392643 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9898 23:03:25.399445 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9899 23:03:25.402672 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9900 23:03:25.406020 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9901 23:03:25.412632 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9902 23:03:25.416385 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9903 23:03:25.422700 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9904 23:03:25.425794 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9905 23:03:25.432386 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9906 23:03:25.435867 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9907 23:03:25.442570 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9908 23:03:25.445470 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9909 23:03:25.448767 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9910 23:03:25.455760 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9911 23:03:25.459011 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9912 23:03:25.465737 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9913 23:03:25.468984 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9914 23:03:25.475452 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9915 23:03:25.479281 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9916 23:03:25.482347 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9917 23:03:25.488876 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9918 23:03:25.492517 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9919 23:03:25.498749 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9920 23:03:25.502292 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9921 23:03:25.508549 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9922 23:03:25.512350 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9923 23:03:25.518488 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9924 23:03:25.521940 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9925 23:03:25.525180 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9926 23:03:25.532264 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9927 23:03:25.535183 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9928 23:03:25.541821 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9929 23:03:25.545424 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9930 23:03:25.551909 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9931 23:03:25.555297 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9932 23:03:25.558442 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9933 23:03:25.565356 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9934 23:03:25.568565 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9935 23:03:25.575222 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9936 23:03:25.578583 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9937 23:03:25.585287 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9938 23:03:25.588266 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9939 23:03:25.595236 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9940 23:03:25.598247 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9941 23:03:25.601578 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9942 23:03:25.608067 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9943 23:03:25.611386 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9944 23:03:25.614869 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9945 23:03:25.621371 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9946 23:03:25.624809 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9947 23:03:25.631587 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9948 23:03:25.634916 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9949 23:03:25.641574 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9950 23:03:25.644591 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9951 23:03:25.651398 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9952 23:03:25.654578 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9953 23:03:25.661449 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9954 23:03:25.664404 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9955 23:03:25.671475 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9956 23:03:25.674720 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9957 23:03:25.681307 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9958 23:03:25.684583 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9959 23:03:25.691416 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9960 23:03:25.694613 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9961 23:03:25.701576 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9962 23:03:25.704775 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9963 23:03:25.711148 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9964 23:03:25.714357 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9965 23:03:25.721066 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9966 23:03:25.724546 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9967 23:03:25.731089 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9968 23:03:25.734293 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9969 23:03:25.740855 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9970 23:03:25.744280 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9971 23:03:25.750732 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9972 23:03:25.754024 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9973 23:03:25.760746 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9974 23:03:25.764332 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9975 23:03:25.767552 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9976 23:03:25.771124 INFO: [APUAPC] vio 0
9977 23:03:25.777849 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9978 23:03:25.780650 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9979 23:03:25.784193 INFO: [APUAPC] D0_APC_0: 0x400510
9980 23:03:25.787741 INFO: [APUAPC] D0_APC_1: 0x0
9981 23:03:25.790638 INFO: [APUAPC] D0_APC_2: 0x1540
9982 23:03:25.794048 INFO: [APUAPC] D0_APC_3: 0x0
9983 23:03:25.797277 INFO: [APUAPC] D1_APC_0: 0xffffffff
9984 23:03:25.800472 INFO: [APUAPC] D1_APC_1: 0xffffffff
9985 23:03:25.804102 INFO: [APUAPC] D1_APC_2: 0x3fffff
9986 23:03:25.807408 INFO: [APUAPC] D1_APC_3: 0x0
9987 23:03:25.810672 INFO: [APUAPC] D2_APC_0: 0xffffffff
9988 23:03:25.814070 INFO: [APUAPC] D2_APC_1: 0xffffffff
9989 23:03:25.817139 INFO: [APUAPC] D2_APC_2: 0x3fffff
9990 23:03:25.817220 INFO: [APUAPC] D2_APC_3: 0x0
9991 23:03:25.820615 INFO: [APUAPC] D3_APC_0: 0xffffffff
9992 23:03:25.827327 INFO: [APUAPC] D3_APC_1: 0xffffffff
9993 23:03:25.830595 INFO: [APUAPC] D3_APC_2: 0x3fffff
9994 23:03:25.830677 INFO: [APUAPC] D3_APC_3: 0x0
9995 23:03:25.833781 INFO: [APUAPC] D4_APC_0: 0xffffffff
9996 23:03:25.836813 INFO: [APUAPC] D4_APC_1: 0xffffffff
9997 23:03:25.840280 INFO: [APUAPC] D4_APC_2: 0x3fffff
9998 23:03:25.843507 INFO: [APUAPC] D4_APC_3: 0x0
9999 23:03:25.846817 INFO: [APUAPC] D5_APC_0: 0xffffffff
10000 23:03:25.850511 INFO: [APUAPC] D5_APC_1: 0xffffffff
10001 23:03:25.853443 INFO: [APUAPC] D5_APC_2: 0x3fffff
10002 23:03:25.857011 INFO: [APUAPC] D5_APC_3: 0x0
10003 23:03:25.860037 INFO: [APUAPC] D6_APC_0: 0xffffffff
10004 23:03:25.863448 INFO: [APUAPC] D6_APC_1: 0xffffffff
10005 23:03:25.866707 INFO: [APUAPC] D6_APC_2: 0x3fffff
10006 23:03:25.870288 INFO: [APUAPC] D6_APC_3: 0x0
10007 23:03:25.873921 INFO: [APUAPC] D7_APC_0: 0xffffffff
10008 23:03:25.876956 INFO: [APUAPC] D7_APC_1: 0xffffffff
10009 23:03:25.879923 INFO: [APUAPC] D7_APC_2: 0x3fffff
10010 23:03:25.883371 INFO: [APUAPC] D7_APC_3: 0x0
10011 23:03:25.886650 INFO: [APUAPC] D8_APC_0: 0xffffffff
10012 23:03:25.889901 INFO: [APUAPC] D8_APC_1: 0xffffffff
10013 23:03:25.893220 INFO: [APUAPC] D8_APC_2: 0x3fffff
10014 23:03:25.896681 INFO: [APUAPC] D8_APC_3: 0x0
10015 23:03:25.899589 INFO: [APUAPC] D9_APC_0: 0xffffffff
10016 23:03:25.903102 INFO: [APUAPC] D9_APC_1: 0xffffffff
10017 23:03:25.906379 INFO: [APUAPC] D9_APC_2: 0x3fffff
10018 23:03:25.909862 INFO: [APUAPC] D9_APC_3: 0x0
10019 23:03:25.913084 INFO: [APUAPC] D10_APC_0: 0xffffffff
10020 23:03:25.916225 INFO: [APUAPC] D10_APC_1: 0xffffffff
10021 23:03:25.919475 INFO: [APUAPC] D10_APC_2: 0x3fffff
10022 23:03:25.922773 INFO: [APUAPC] D10_APC_3: 0x0
10023 23:03:25.926402 INFO: [APUAPC] D11_APC_0: 0xffffffff
10024 23:03:25.929648 INFO: [APUAPC] D11_APC_1: 0xffffffff
10025 23:03:25.933127 INFO: [APUAPC] D11_APC_2: 0x3fffff
10026 23:03:25.935819 INFO: [APUAPC] D11_APC_3: 0x0
10027 23:03:25.939424 INFO: [APUAPC] D12_APC_0: 0xffffffff
10028 23:03:25.942687 INFO: [APUAPC] D12_APC_1: 0xffffffff
10029 23:03:25.945870 INFO: [APUAPC] D12_APC_2: 0x3fffff
10030 23:03:25.949419 INFO: [APUAPC] D12_APC_3: 0x0
10031 23:03:25.952970 INFO: [APUAPC] D13_APC_0: 0xffffffff
10032 23:03:25.955767 INFO: [APUAPC] D13_APC_1: 0xffffffff
10033 23:03:25.959028 INFO: [APUAPC] D13_APC_2: 0x3fffff
10034 23:03:25.962845 INFO: [APUAPC] D13_APC_3: 0x0
10035 23:03:25.965810 INFO: [APUAPC] D14_APC_0: 0xffffffff
10036 23:03:25.969191 INFO: [APUAPC] D14_APC_1: 0xffffffff
10037 23:03:25.972368 INFO: [APUAPC] D14_APC_2: 0x3fffff
10038 23:03:25.975733 INFO: [APUAPC] D14_APC_3: 0x0
10039 23:03:25.978786 INFO: [APUAPC] D15_APC_0: 0xffffffff
10040 23:03:25.982300 INFO: [APUAPC] D15_APC_1: 0xffffffff
10041 23:03:25.985532 INFO: [APUAPC] D15_APC_2: 0x3fffff
10042 23:03:25.989179 INFO: [APUAPC] D15_APC_3: 0x0
10043 23:03:25.992191 INFO: [APUAPC] APC_CON: 0x4
10044 23:03:25.995791 INFO: [NOCDAPC] D0_APC_0: 0x0
10045 23:03:25.998589 INFO: [NOCDAPC] D0_APC_1: 0x0
10046 23:03:26.001868 INFO: [NOCDAPC] D1_APC_0: 0x0
10047 23:03:26.005293 INFO: [NOCDAPC] D1_APC_1: 0xfff
10048 23:03:26.008888 INFO: [NOCDAPC] D2_APC_0: 0x0
10049 23:03:26.012042 INFO: [NOCDAPC] D2_APC_1: 0xfff
10050 23:03:26.012124 INFO: [NOCDAPC] D3_APC_0: 0x0
10051 23:03:26.015219 INFO: [NOCDAPC] D3_APC_1: 0xfff
10052 23:03:26.018961 INFO: [NOCDAPC] D4_APC_0: 0x0
10053 23:03:26.021689 INFO: [NOCDAPC] D4_APC_1: 0xfff
10054 23:03:26.025399 INFO: [NOCDAPC] D5_APC_0: 0x0
10055 23:03:26.028486 INFO: [NOCDAPC] D5_APC_1: 0xfff
10056 23:03:26.031776 INFO: [NOCDAPC] D6_APC_0: 0x0
10057 23:03:26.035053 INFO: [NOCDAPC] D6_APC_1: 0xfff
10058 23:03:26.038147 INFO: [NOCDAPC] D7_APC_0: 0x0
10059 23:03:26.041901 INFO: [NOCDAPC] D7_APC_1: 0xfff
10060 23:03:26.044704 INFO: [NOCDAPC] D8_APC_0: 0x0
10061 23:03:26.048163 INFO: [NOCDAPC] D8_APC_1: 0xfff
10062 23:03:26.048262 INFO: [NOCDAPC] D9_APC_0: 0x0
10063 23:03:26.051519 INFO: [NOCDAPC] D9_APC_1: 0xfff
10064 23:03:26.055069 INFO: [NOCDAPC] D10_APC_0: 0x0
10065 23:03:26.058375 INFO: [NOCDAPC] D10_APC_1: 0xfff
10066 23:03:26.061277 INFO: [NOCDAPC] D11_APC_0: 0x0
10067 23:03:26.065026 INFO: [NOCDAPC] D11_APC_1: 0xfff
10068 23:03:26.068427 INFO: [NOCDAPC] D12_APC_0: 0x0
10069 23:03:26.071520 INFO: [NOCDAPC] D12_APC_1: 0xfff
10070 23:03:26.074623 INFO: [NOCDAPC] D13_APC_0: 0x0
10071 23:03:26.078451 INFO: [NOCDAPC] D13_APC_1: 0xfff
10072 23:03:26.081283 INFO: [NOCDAPC] D14_APC_0: 0x0
10073 23:03:26.084887 INFO: [NOCDAPC] D14_APC_1: 0xfff
10074 23:03:26.088056 INFO: [NOCDAPC] D15_APC_0: 0x0
10075 23:03:26.091509 INFO: [NOCDAPC] D15_APC_1: 0xfff
10076 23:03:26.091614 INFO: [NOCDAPC] APC_CON: 0x4
10077 23:03:26.097859 INFO: [APUAPC] set_apusys_apc done
10078 23:03:26.097937 INFO: [DEVAPC] devapc_init done
10079 23:03:26.104510 INFO: GICv3 without legacy support detected.
10080 23:03:26.107733 INFO: ARM GICv3 driver initialized in EL3
10081 23:03:26.110869 INFO: Maximum SPI INTID supported: 639
10082 23:03:26.114572 INFO: BL31: Initializing runtime services
10083 23:03:26.121240 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10084 23:03:26.124759 INFO: SPM: enable CPC mode
10085 23:03:26.127854 INFO: mcdi ready for mcusys-off-idle and system suspend
10086 23:03:26.134034 INFO: BL31: Preparing for EL3 exit to normal world
10087 23:03:26.137471 INFO: Entry point address = 0x80000000
10088 23:03:26.140794 INFO: SPSR = 0x8
10089 23:03:26.144948
10090 23:03:26.145025
10091 23:03:26.145088
10092 23:03:26.148170 Starting depthcharge on Spherion...
10093 23:03:26.148277
10094 23:03:26.148366 Wipe memory regions:
10095 23:03:26.148449
10096 23:03:26.149109 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10097 23:03:26.149211 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10098 23:03:26.149547 Setting prompt string to ['asurada:']
10099 23:03:26.149659 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10100 23:03:26.151465 [0x00000040000000, 0x00000054600000)
10101 23:03:26.273926
10102 23:03:26.274062 [0x00000054660000, 0x00000080000000)
10103 23:03:26.534304
10104 23:03:26.534468 [0x000000821a7280, 0x000000ffe64000)
10105 23:03:27.278944
10106 23:03:27.279111 [0x00000100000000, 0x00000240000000)
10107 23:03:29.167677
10108 23:03:29.170935 Initializing XHCI USB controller at 0x11200000.
10109 23:03:30.209026
10110 23:03:30.212550 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10111 23:03:30.212770
10112 23:03:30.212960
10113 23:03:30.213143
10114 23:03:30.213613 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10116 23:03:30.314455 asurada: tftpboot 192.168.201.1 12154420/tftp-deploy-1s1l4ozf/kernel/image.itb 12154420/tftp-deploy-1s1l4ozf/kernel/cmdline
10117 23:03:30.315153 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10118 23:03:30.315758 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10119 23:03:30.320844 tftpboot 192.168.201.1 12154420/tftp-deploy-1s1l4ozf/kernel/image.ittp-deploy-1s1l4ozf/kernel/cmdline
10120 23:03:30.321391
10121 23:03:30.321908 Waiting for link
10122 23:03:30.480835
10123 23:03:30.481199 R8152: Initializing
10124 23:03:30.481481
10125 23:03:30.483380 Version 6 (ocp_data = 5c30)
10126 23:03:30.483677
10127 23:03:30.487020 R8152: Done initializing
10128 23:03:30.487288
10129 23:03:30.487556 Adding net device
10130 23:03:32.561772
10131 23:03:32.562305 done.
10132 23:03:32.562673
10133 23:03:32.563009 MAC: 00:24:32:30:78:ff
10134 23:03:32.563337
10135 23:03:32.564706 Sending DHCP discover... done.
10136 23:03:32.565166
10137 23:03:32.568256 Waiting for reply... done.
10138 23:03:32.568719
10139 23:03:32.571454 Sending DHCP request... done.
10140 23:03:32.572053
10141 23:03:32.576820 Waiting for reply... done.
10142 23:03:32.577318
10143 23:03:32.577686 My ip is 192.168.201.21
10144 23:03:32.578027
10145 23:03:32.580002 The DHCP server ip is 192.168.201.1
10146 23:03:32.580515
10147 23:03:32.586924 TFTP server IP predefined by user: 192.168.201.1
10148 23:03:32.587396
10149 23:03:32.593372 Bootfile predefined by user: 12154420/tftp-deploy-1s1l4ozf/kernel/image.itb
10150 23:03:32.593846
10151 23:03:32.594216 Sending tftp read request... done.
10152 23:03:32.597097
10153 23:03:32.603673 Waiting for the transfer...
10154 23:03:32.604396
10155 23:03:33.255405 00000000 ################################################################
10156 23:03:33.255946
10157 23:03:33.819913 00080000 ################################################################
10158 23:03:33.820057
10159 23:03:34.392007 00100000 ################################################################
10160 23:03:34.392368
10161 23:03:35.055501 00180000 ################################################################
10162 23:03:35.055866
10163 23:03:35.645436 00200000 ################################################################
10164 23:03:35.645591
10165 23:03:36.337960 00280000 ################################################################
10166 23:03:36.338544
10167 23:03:37.053019 00300000 ################################################################
10168 23:03:37.053633
10169 23:03:37.783730 00380000 ################################################################
10170 23:03:37.784303
10171 23:03:38.521224 00400000 ################################################################
10172 23:03:38.521869
10173 23:03:39.253731 00480000 ################################################################
10174 23:03:39.254331
10175 23:03:39.985890 00500000 ################################################################
10176 23:03:39.986492
10177 23:03:40.721854 00580000 ################################################################
10178 23:03:40.722416
10179 23:03:41.454784 00600000 ################################################################
10180 23:03:41.455361
10181 23:03:42.186920 00680000 ################################################################
10182 23:03:42.187531
10183 23:03:42.923631 00700000 ################################################################
10184 23:03:42.924269
10185 23:03:43.671382 00780000 ################################################################
10186 23:03:43.671937
10187 23:03:44.403959 00800000 ################################################################
10188 23:03:44.404650
10189 23:03:45.145030 00880000 ################################################################
10190 23:03:45.145638
10191 23:03:45.864560 00900000 ################################################################
10192 23:03:45.865238
10193 23:03:46.593644 00980000 ################################################################
10194 23:03:46.594232
10195 23:03:47.316221 00a00000 ################################################################
10196 23:03:47.316592
10197 23:03:48.014084 00a80000 ################################################################
10198 23:03:48.014605
10199 23:03:48.732659 00b00000 ################################################################
10200 23:03:48.733459
10201 23:03:49.337091 00b80000 ################################################################
10202 23:03:49.337300
10203 23:03:49.923934 00c00000 ################################################################
10204 23:03:49.924606
10205 23:03:50.642015 00c80000 ################################################################
10206 23:03:50.642627
10207 23:03:51.347373 00d00000 ################################################################
10208 23:03:51.347925
10209 23:03:52.022181 00d80000 ################################################################
10210 23:03:52.022319
10211 23:03:52.646168 00e00000 ################################################################
10212 23:03:52.646325
10213 23:03:53.259585 00e80000 ################################################################
10214 23:03:53.259751
10215 23:03:53.898919 00f00000 ################################################################
10216 23:03:53.899476
10217 23:03:54.605402 00f80000 ################################################################
10218 23:03:54.605944
10219 23:03:55.281293 01000000 ################################################################
10220 23:03:55.281807
10221 23:03:55.942284 01080000 ################################################################
10222 23:03:55.942835
10223 23:03:56.538281 01100000 ################################################################
10224 23:03:56.538426
10225 23:03:57.106872 01180000 ################################################################
10226 23:03:57.107055
10227 23:03:57.668648 01200000 ################################################################
10228 23:03:57.669153
10229 23:03:58.309009 01280000 ################################################################
10230 23:03:58.309168
10231 23:03:58.924748 01300000 ################################################################
10232 23:03:58.925296
10233 23:03:59.525766 01380000 ################################################################
10234 23:03:59.525904
10235 23:04:00.158306 01400000 ################################################################
10236 23:04:00.158837
10237 23:04:00.806795 01480000 ################################################################
10238 23:04:00.806931
10239 23:04:01.476439 01500000 ################################################################
10240 23:04:01.476943
10241 23:04:02.183631 01580000 ################################################################
10242 23:04:02.184279
10243 23:04:02.900707 01600000 ################################################################
10244 23:04:02.901217
10245 23:04:03.534181 01680000 ################################################################
10246 23:04:03.534700
10247 23:04:04.255849 01700000 ################################################################
10248 23:04:04.256445
10249 23:04:04.925157 01780000 ################################################################
10250 23:04:04.925338
10251 23:04:05.512520 01800000 ################################################################
10252 23:04:05.512692
10253 23:04:06.107903 01880000 ################################################################
10254 23:04:06.108053
10255 23:04:06.694440 01900000 ################################################################
10256 23:04:06.694959
10257 23:04:07.295762 01980000 ################################################################
10258 23:04:07.296447
10259 23:04:07.953345 01a00000 ################################################################
10260 23:04:07.953495
10261 23:04:08.567442 01a80000 ################################################################
10262 23:04:08.567593
10263 23:04:09.167996 01b00000 ################################################################
10264 23:04:09.168171
10265 23:04:09.229929 01b80000 ####### done.
10266 23:04:09.230067
10267 23:04:09.233334 The bootfile was 28891642 bytes long.
10268 23:04:09.233413
10269 23:04:09.236820 Sending tftp read request... done.
10270 23:04:09.236918
10271 23:04:09.237022 Waiting for the transfer...
10272 23:04:09.237093
10273 23:04:09.240087 00000000 # done.
10274 23:04:09.240193
10275 23:04:09.246896 Command line loaded dynamically from TFTP file: 12154420/tftp-deploy-1s1l4ozf/kernel/cmdline
10276 23:04:09.246999
10277 23:04:09.270024 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12154420/extract-nfsrootfs-aawdswdf,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10278 23:04:09.270143
10279 23:04:09.270246 Loading FIT.
10280 23:04:09.270330
10281 23:04:09.273252 Image ramdisk-1 has 17798348 bytes.
10282 23:04:09.273373
10283 23:04:09.276332 Image fdt-1 has 47278 bytes.
10284 23:04:09.276467
10285 23:04:09.279855 Image kernel-1 has 11043984 bytes.
10286 23:04:09.279977
10287 23:04:09.289722 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10288 23:04:09.289906
10289 23:04:09.306697 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10290 23:04:09.307279
10291 23:04:09.313352 Choosing best match conf-1 for compat google,spherion-rev2.
10292 23:04:09.313922
10293 23:04:09.320588 Connected to device vid:did:rid of 1ae0:0028:00
10294 23:04:09.327490
10295 23:04:09.330941 tpm_get_response: command 0x17b, return code 0x0
10296 23:04:09.331437
10297 23:04:09.334480 ec_init: CrosEC protocol v3 supported (256, 248)
10298 23:04:09.338384
10299 23:04:09.341764 tpm_cleanup: add release locality here.
10300 23:04:09.342307
10301 23:04:09.342744 Shutting down all USB controllers.
10302 23:04:09.344897
10303 23:04:09.345296 Removing current net device
10304 23:04:09.345724
10305 23:04:09.351788 Exiting depthcharge with code 4 at timestamp: 72523002
10306 23:04:09.352176
10307 23:04:09.355123 LZMA decompressing kernel-1 to 0x821a6718
10308 23:04:09.355623
10309 23:04:09.357987 LZMA decompressing kernel-1 to 0x40000000
10310 23:04:10.752479
10311 23:04:10.753047 jumping to kernel
10312 23:04:10.754784 end: 2.2.4 bootloader-commands (duration 00:00:45) [common]
10313 23:04:10.755321 start: 2.2.5 auto-login-action (timeout 00:03:41) [common]
10314 23:04:10.755868 Setting prompt string to ['Linux version [0-9]']
10315 23:04:10.756382 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10316 23:04:10.757023 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10317 23:04:10.834020
10318 23:04:10.837720 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10319 23:04:10.841290 start: 2.2.5.1 login-action (timeout 00:03:41) [common]
10320 23:04:10.841925 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10321 23:04:10.842340 Setting prompt string to []
10322 23:04:10.842818 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10323 23:04:10.843176 Using line separator: #'\n'#
10324 23:04:10.843497 No login prompt set.
10325 23:04:10.843808 Parsing kernel messages
10326 23:04:10.844292 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10327 23:04:10.845098 [login-action] Waiting for messages, (timeout 00:03:41)
10328 23:04:10.860433 [ 0.000000] Linux version 6.1.64-cip10 (KernelCI@build-j31357-arm64-gcc-10-defconfig-arm64-chromebook-69txj) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Dec 1 22:47:09 UTC 2023
10329 23:04:10.864188 [ 0.000000] random: crng init done
10330 23:04:10.870793 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10331 23:04:10.873816 [ 0.000000] efi: UEFI not found.
10332 23:04:10.880820 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10333 23:04:10.887130 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10334 23:04:10.897481 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10335 23:04:10.906904 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10336 23:04:10.913327 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10337 23:04:10.920400 [ 0.000000] printk: bootconsole [mtk8250] enabled
10338 23:04:10.926605 [ 0.000000] NUMA: No NUMA configuration found
10339 23:04:10.933811 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10340 23:04:10.937107 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10341 23:04:10.940139 [ 0.000000] Zone ranges:
10342 23:04:10.946527 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10343 23:04:10.950090 [ 0.000000] DMA32 empty
10344 23:04:10.956466 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10345 23:04:10.960513 [ 0.000000] Movable zone start for each node
10346 23:04:10.963555 [ 0.000000] Early memory node ranges
10347 23:04:10.969696 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10348 23:04:10.976480 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10349 23:04:10.983082 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10350 23:04:10.989747 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10351 23:04:10.992876 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10352 23:04:11.003013 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10353 23:04:11.058693 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10354 23:04:11.064922 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10355 23:04:11.071109 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10356 23:04:11.074579 [ 0.000000] psci: probing for conduit method from DT.
10357 23:04:11.081234 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10358 23:04:11.084924 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10359 23:04:11.091389 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10360 23:04:11.094464 [ 0.000000] psci: SMC Calling Convention v1.2
10361 23:04:11.100920 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10362 23:04:11.104090 [ 0.000000] Detected VIPT I-cache on CPU0
10363 23:04:11.110880 [ 0.000000] CPU features: detected: GIC system register CPU interface
10364 23:04:11.117407 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10365 23:04:11.124132 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10366 23:04:11.130556 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10367 23:04:11.140340 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10368 23:04:11.147103 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10369 23:04:11.150203 [ 0.000000] alternatives: applying boot alternatives
10370 23:04:11.157194 [ 0.000000] Fallback order for Node 0: 0
10371 23:04:11.164110 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10372 23:04:11.167035 [ 0.000000] Policy zone: Normal
10373 23:04:11.190535 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12154420/extract-nfsrootfs-aawdswdf,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10374 23:04:11.199855 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10375 23:04:11.211127 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10376 23:04:11.220609 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10377 23:04:11.227165 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10378 23:04:11.230505 <6>[ 0.000000] software IO TLB: area num 8.
10379 23:04:11.287270 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10380 23:04:11.437310 <6>[ 0.000000] Memory: 7952172K/8385536K available (17984K kernel code, 4116K rwdata, 17316K rodata, 8448K init, 615K bss, 400596K reserved, 32768K cma-reserved)
10381 23:04:11.444025 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10382 23:04:11.450450 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10383 23:04:11.453451 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10384 23:04:11.460271 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10385 23:04:11.466878 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10386 23:04:11.470242 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10387 23:04:11.480036 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10388 23:04:11.486922 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10389 23:04:11.493176 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10390 23:04:11.500170 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10391 23:04:11.503016 <6>[ 0.000000] GICv3: 608 SPIs implemented
10392 23:04:11.506304 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10393 23:04:11.512755 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10394 23:04:11.516185 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10395 23:04:11.522659 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10396 23:04:11.536099 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10397 23:04:11.549420 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10398 23:04:11.556016 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10399 23:04:11.563511 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10400 23:04:11.576881 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10401 23:04:11.583136 <6>[ 0.000001] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10402 23:04:11.590000 <6>[ 0.009169] Console: colour dummy device 80x25
10403 23:04:11.599971 <6>[ 0.013896] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10404 23:04:11.606834 <6>[ 0.024338] pid_max: default: 32768 minimum: 301
10405 23:04:11.609680 <6>[ 0.029239] LSM: Security Framework initializing
10406 23:04:11.616305 <6>[ 0.034177] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10407 23:04:11.626362 <6>[ 0.041992] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10408 23:04:11.632747 <6>[ 0.051401] cblist_init_generic: Setting adjustable number of callback queues.
10409 23:04:11.639709 <6>[ 0.058842] cblist_init_generic: Setting shift to 3 and lim to 1.
10410 23:04:11.649484 <6>[ 0.065219] cblist_init_generic: Setting adjustable number of callback queues.
10411 23:04:11.656301 <6>[ 0.072646] cblist_init_generic: Setting shift to 3 and lim to 1.
10412 23:04:11.659247 <6>[ 0.079046] rcu: Hierarchical SRCU implementation.
10413 23:04:11.666439 <6>[ 0.084061] rcu: Max phase no-delay instances is 1000.
10414 23:04:11.673412 <6>[ 0.091091] EFI services will not be available.
10415 23:04:11.676239 <6>[ 0.096048] smp: Bringing up secondary CPUs ...
10416 23:04:11.684443 <6>[ 0.101097] Detected VIPT I-cache on CPU1
10417 23:04:11.690658 <6>[ 0.101167] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10418 23:04:11.697546 <6>[ 0.101199] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10419 23:04:11.701054 <6>[ 0.101536] Detected VIPT I-cache on CPU2
10420 23:04:11.707315 <6>[ 0.101586] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10421 23:04:11.717259 <6>[ 0.101601] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10422 23:04:11.720818 <6>[ 0.101856] Detected VIPT I-cache on CPU3
10423 23:04:11.727290 <6>[ 0.101901] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10424 23:04:11.733721 <6>[ 0.101915] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10425 23:04:11.737666 <6>[ 0.102217] CPU features: detected: Spectre-v4
10426 23:04:11.743974 <6>[ 0.102224] CPU features: detected: Spectre-BHB
10427 23:04:11.747386 <6>[ 0.102229] Detected PIPT I-cache on CPU4
10428 23:04:11.753671 <6>[ 0.102286] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10429 23:04:11.760478 <6>[ 0.102303] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10430 23:04:11.767116 <6>[ 0.102594] Detected PIPT I-cache on CPU5
10431 23:04:11.773417 <6>[ 0.102655] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10432 23:04:11.780315 <6>[ 0.102671] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10433 23:04:11.783339 <6>[ 0.102953] Detected PIPT I-cache on CPU6
10434 23:04:11.790026 <6>[ 0.103017] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10435 23:04:11.799458 <6>[ 0.103034] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10436 23:04:11.803073 <6>[ 0.103333] Detected PIPT I-cache on CPU7
10437 23:04:11.809539 <6>[ 0.103396] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10438 23:04:11.816089 <6>[ 0.103413] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10439 23:04:11.819328 <6>[ 0.103460] smp: Brought up 1 node, 8 CPUs
10440 23:04:11.825836 <6>[ 0.244824] SMP: Total of 8 processors activated.
10441 23:04:11.829690 <6>[ 0.249745] CPU features: detected: 32-bit EL0 Support
10442 23:04:11.839202 <6>[ 0.255109] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10443 23:04:11.846116 <6>[ 0.263909] CPU features: detected: Common not Private translations
10444 23:04:11.852924 <6>[ 0.270384] CPU features: detected: CRC32 instructions
10445 23:04:11.855799 <6>[ 0.275736] CPU features: detected: RCpc load-acquire (LDAPR)
10446 23:04:11.862378 <6>[ 0.281733] CPU features: detected: LSE atomic instructions
10447 23:04:11.869150 <6>[ 0.287550] CPU features: detected: Privileged Access Never
10448 23:04:11.875687 <6>[ 0.293329] CPU features: detected: RAS Extension Support
10449 23:04:11.882092 <6>[ 0.298972] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10450 23:04:11.886049 <6>[ 0.306192] CPU: All CPU(s) started at EL2
10451 23:04:11.891915 <6>[ 0.310535] alternatives: applying system-wide alternatives
10452 23:04:11.902179 <6>[ 0.321268] devtmpfs: initialized
10453 23:04:11.914290 <6>[ 0.330248] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10454 23:04:11.924324 <6>[ 0.340210] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10455 23:04:11.930639 <6>[ 0.348440] pinctrl core: initialized pinctrl subsystem
10456 23:04:11.934056 <6>[ 0.355091] DMI not present or invalid.
10457 23:04:11.940957 <6>[ 0.359500] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10458 23:04:11.950897 <6>[ 0.366377] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10459 23:04:11.957203 <6>[ 0.373957] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10460 23:04:11.967151 <6>[ 0.382182] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10461 23:04:11.970541 <6>[ 0.390425] audit: initializing netlink subsys (disabled)
10462 23:04:11.980795 <5>[ 0.396116] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10463 23:04:11.987495 <6>[ 0.396819] thermal_sys: Registered thermal governor 'step_wise'
10464 23:04:11.993863 <6>[ 0.404085] thermal_sys: Registered thermal governor 'power_allocator'
10465 23:04:11.997320 <6>[ 0.410339] cpuidle: using governor menu
10466 23:04:12.004277 <6>[ 0.421298] NET: Registered PF_QIPCRTR protocol family
10467 23:04:12.010656 <6>[ 0.426783] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10468 23:04:12.013737 <6>[ 0.433884] ASID allocator initialised with 32768 entries
10469 23:04:12.020895 <6>[ 0.440442] Serial: AMBA PL011 UART driver
10470 23:04:12.029813 <4>[ 0.449143] Trying to register duplicate clock ID: 134
10471 23:04:12.086287 <6>[ 0.508718] KASLR enabled
10472 23:04:12.100762 <6>[ 0.516467] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10473 23:04:12.107285 <6>[ 0.523478] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10474 23:04:12.113702 <6>[ 0.529967] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10475 23:04:12.119975 <6>[ 0.536974] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10476 23:04:12.126856 <6>[ 0.543462] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10477 23:04:12.133136 <6>[ 0.550465] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10478 23:04:12.139794 <6>[ 0.556951] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10479 23:04:12.146333 <6>[ 0.563955] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10480 23:04:12.149752 <6>[ 0.571480] ACPI: Interpreter disabled.
10481 23:04:12.158639 <6>[ 0.577896] iommu: Default domain type: Translated
10482 23:04:12.165684 <6>[ 0.583009] iommu: DMA domain TLB invalidation policy: strict mode
10483 23:04:12.168494 <5>[ 0.589668] SCSI subsystem initialized
10484 23:04:12.175371 <6>[ 0.593829] usbcore: registered new interface driver usbfs
10485 23:04:12.182119 <6>[ 0.599564] usbcore: registered new interface driver hub
10486 23:04:12.184879 <6>[ 0.605116] usbcore: registered new device driver usb
10487 23:04:12.192286 <6>[ 0.611220] pps_core: LinuxPPS API ver. 1 registered
10488 23:04:12.202220 <6>[ 0.616413] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10489 23:04:12.205016 <6>[ 0.625760] PTP clock support registered
10490 23:04:12.208584 <6>[ 0.630001] EDAC MC: Ver: 3.0.0
10491 23:04:12.216174 <6>[ 0.635158] FPGA manager framework
10492 23:04:12.223125 <6>[ 0.638837] Advanced Linux Sound Architecture Driver Initialized.
10493 23:04:12.226211 <6>[ 0.645625] vgaarb: loaded
10494 23:04:12.232815 <6>[ 0.648784] clocksource: Switched to clocksource arch_sys_counter
10495 23:04:12.235933 <5>[ 0.655227] VFS: Disk quotas dquot_6.6.0
10496 23:04:12.242051 <6>[ 0.659413] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10497 23:04:12.245560 <6>[ 0.666599] pnp: PnP ACPI: disabled
10498 23:04:12.254060 <6>[ 0.673296] NET: Registered PF_INET protocol family
10499 23:04:12.263804 <6>[ 0.678890] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10500 23:04:12.275097 <6>[ 0.691231] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10501 23:04:12.285449 <6>[ 0.700044] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10502 23:04:12.291824 <6>[ 0.708014] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10503 23:04:12.298535 <6>[ 0.716712] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10504 23:04:12.310941 <6>[ 0.726466] TCP: Hash tables configured (established 65536 bind 65536)
10505 23:04:12.317747 <6>[ 0.733329] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10506 23:04:12.323988 <6>[ 0.740530] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10507 23:04:12.330448 <6>[ 0.748235] NET: Registered PF_UNIX/PF_LOCAL protocol family
10508 23:04:12.337352 <6>[ 0.754393] RPC: Registered named UNIX socket transport module.
10509 23:04:12.340391 <6>[ 0.760548] RPC: Registered udp transport module.
10510 23:04:12.346782 <6>[ 0.765480] RPC: Registered tcp transport module.
10511 23:04:12.353574 <6>[ 0.770412] RPC: Registered tcp NFSv4.1 backchannel transport module.
10512 23:04:12.357256 <6>[ 0.777078] PCI: CLS 0 bytes, default 64
10513 23:04:12.360250 <6>[ 0.781419] Unpacking initramfs...
10514 23:04:12.385364 <6>[ 0.800890] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10515 23:04:12.395021 <6>[ 0.809541] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10516 23:04:12.398193 <6>[ 0.818384] kvm [1]: IPA Size Limit: 40 bits
10517 23:04:12.404430 <6>[ 0.822911] kvm [1]: GICv3: no GICV resource entry
10518 23:04:12.407640 <6>[ 0.827934] kvm [1]: disabling GICv2 emulation
10519 23:04:12.414822 <6>[ 0.832619] kvm [1]: GIC system register CPU interface enabled
10520 23:04:12.418091 <6>[ 0.838790] kvm [1]: vgic interrupt IRQ18
10521 23:04:12.424537 <6>[ 0.843147] kvm [1]: VHE mode initialized successfully
10522 23:04:12.431495 <5>[ 0.849634] Initialise system trusted keyrings
10523 23:04:12.437812 <6>[ 0.854487] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10524 23:04:12.445231 <6>[ 0.864445] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10525 23:04:12.452001 <5>[ 0.870831] NFS: Registering the id_resolver key type
10526 23:04:12.454993 <5>[ 0.876137] Key type id_resolver registered
10527 23:04:12.461757 <5>[ 0.880552] Key type id_legacy registered
10528 23:04:12.468563 <6>[ 0.884830] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10529 23:04:12.475336 <6>[ 0.891753] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10530 23:04:12.481909 <6>[ 0.899498] 9p: Installing v9fs 9p2000 file system support
10531 23:04:12.517923 <5>[ 0.936943] Key type asymmetric registered
10532 23:04:12.521120 <5>[ 0.941277] Asymmetric key parser 'x509' registered
10533 23:04:12.531096 <6>[ 0.946424] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10534 23:04:12.534187 <6>[ 0.954039] io scheduler mq-deadline registered
10535 23:04:12.537275 <6>[ 0.958833] io scheduler kyber registered
10536 23:04:12.556574 <6>[ 0.975804] EINJ: ACPI disabled.
10537 23:04:12.588897 <4>[ 1.001375] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10538 23:04:12.598868 <4>[ 1.012018] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10539 23:04:12.613883 <6>[ 1.032944] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10540 23:04:12.621896 <6>[ 1.040944] printk: console [ttyS0] disabled
10541 23:04:12.649804 <6>[ 1.065589] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10542 23:04:12.657098 <6>[ 1.075064] printk: console [ttyS0] enabled
10543 23:04:12.659581 <6>[ 1.075064] printk: console [ttyS0] enabled
10544 23:04:12.665998 <6>[ 1.083957] printk: bootconsole [mtk8250] disabled
10545 23:04:12.669145 <6>[ 1.083957] printk: bootconsole [mtk8250] disabled
10546 23:04:12.676453 <6>[ 1.095237] SuperH (H)SCI(F) driver initialized
10547 23:04:12.679531 <6>[ 1.100530] msm_serial: driver initialized
10548 23:04:12.693446 <6>[ 1.109526] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10549 23:04:12.703558 <6>[ 1.118074] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10550 23:04:12.710286 <6>[ 1.126616] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10551 23:04:12.719937 <6>[ 1.135244] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10552 23:04:12.730097 <6>[ 1.143951] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10553 23:04:12.736624 <6>[ 1.152674] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10554 23:04:12.746468 <6>[ 1.161216] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10555 23:04:12.753212 <6>[ 1.170031] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10556 23:04:12.763264 <6>[ 1.178575] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10557 23:04:12.775571 <6>[ 1.194430] loop: module loaded
10558 23:04:12.781545 <6>[ 1.200413] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10559 23:04:12.804478 <4>[ 1.223936] mtk-pmic-keys: Failed to locate of_node [id: -1]
10560 23:04:12.811941 <6>[ 1.231094] megasas: 07.719.03.00-rc1
10561 23:04:12.822094 <6>[ 1.240927] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10562 23:04:12.829203 <6>[ 1.248180] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10563 23:04:12.846096 <6>[ 1.264981] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10564 23:04:12.902983 <6>[ 1.315043] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10565 23:04:13.101926 <6>[ 1.521060] Freeing initrd memory: 17380K
10566 23:04:13.112619 <6>[ 1.531363] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10567 23:04:13.123349 <6>[ 1.542469] tun: Universal TUN/TAP device driver, 1.6
10568 23:04:13.126748 <6>[ 1.548562] thunder_xcv, ver 1.0
10569 23:04:13.130634 <6>[ 1.552073] thunder_bgx, ver 1.0
10570 23:04:13.133217 <6>[ 1.555567] nicpf, ver 1.0
10571 23:04:13.144002 <6>[ 1.559599] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10572 23:04:13.147407 <6>[ 1.567075] hns3: Copyright (c) 2017 Huawei Corporation.
10573 23:04:13.150668 <6>[ 1.572666] hclge is initializing
10574 23:04:13.157232 <6>[ 1.576247] e1000: Intel(R) PRO/1000 Network Driver
10575 23:04:13.163471 <6>[ 1.581376] e1000: Copyright (c) 1999-2006 Intel Corporation.
10576 23:04:13.167181 <6>[ 1.587388] e1000e: Intel(R) PRO/1000 Network Driver
10577 23:04:13.174130 <6>[ 1.592604] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10578 23:04:13.180887 <6>[ 1.598791] igb: Intel(R) Gigabit Ethernet Network Driver
10579 23:04:13.187369 <6>[ 1.604441] igb: Copyright (c) 2007-2014 Intel Corporation.
10580 23:04:13.193698 <6>[ 1.610283] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10581 23:04:13.196748 <6>[ 1.616801] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10582 23:04:13.204436 <6>[ 1.623265] sky2: driver version 1.30
10583 23:04:13.210782 <6>[ 1.628270] VFIO - User Level meta-driver version: 0.3
10584 23:04:13.217869 <6>[ 1.636473] usbcore: registered new interface driver usb-storage
10585 23:04:13.224302 <6>[ 1.642934] usbcore: registered new device driver onboard-usb-hub
10586 23:04:13.232816 <6>[ 1.652112] mt6397-rtc mt6359-rtc: registered as rtc0
10587 23:04:13.242910 <6>[ 1.657573] mt6397-rtc mt6359-rtc: setting system clock to 2023-12-01T23:04:15 UTC (1701471855)
10588 23:04:13.246104 <6>[ 1.667145] i2c_dev: i2c /dev entries driver
10589 23:04:13.263092 <6>[ 1.678944] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10590 23:04:13.282584 <6>[ 1.701867] cpu cpu0: EM: created perf domain
10591 23:04:13.285909 <6>[ 1.706782] cpu cpu4: EM: created perf domain
10592 23:04:13.292931 <6>[ 1.712400] sdhci: Secure Digital Host Controller Interface driver
10593 23:04:13.299673 <6>[ 1.718832] sdhci: Copyright(c) Pierre Ossman
10594 23:04:13.306509 <6>[ 1.723780] Synopsys Designware Multimedia Card Interface Driver
10595 23:04:13.313038 <6>[ 1.730415] sdhci-pltfm: SDHCI platform and OF driver helper
10596 23:04:13.316498 <6>[ 1.730485] mmc0: CQHCI version 5.10
10597 23:04:13.323336 <6>[ 1.740367] ledtrig-cpu: registered to indicate activity on CPUs
10598 23:04:13.329610 <6>[ 1.747286] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10599 23:04:13.336590 <6>[ 1.754330] usbcore: registered new interface driver usbhid
10600 23:04:13.340115 <6>[ 1.760152] usbhid: USB HID core driver
10601 23:04:13.346463 <6>[ 1.764348] spi_master spi0: will run message pump with realtime priority
10602 23:04:13.390652 <6>[ 1.802765] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10603 23:04:13.409079 <6>[ 1.817822] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10604 23:04:13.412582 <6>[ 1.832016] mmc0: Command Queue Engine enabled
10605 23:04:13.418870 <6>[ 1.836817] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10606 23:04:13.425238 <6>[ 1.843542] cros-ec-spi spi0.0: Chrome EC device registered
10607 23:04:13.428762 <6>[ 1.844095] mmcblk0: mmc0:0001 DA4128 116 GiB
10608 23:04:13.443168 <6>[ 1.862095] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10609 23:04:13.450078 <6>[ 1.869355] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10610 23:04:13.460135 <6>[ 1.873529] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10611 23:04:13.463171 <6>[ 1.875274] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10612 23:04:13.469994 <6>[ 1.885110] NET: Registered PF_PACKET protocol family
10613 23:04:13.476349 <6>[ 1.889790] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10614 23:04:13.480590 <6>[ 1.894490] 9pnet: Installing 9P2000 support
10615 23:04:13.487000 <5>[ 1.905482] Key type dns_resolver registered
10616 23:04:13.490258 <6>[ 1.910432] registered taskstats version 1
10617 23:04:13.496709 <5>[ 1.914810] Loading compiled-in X.509 certificates
10618 23:04:13.525358 <4>[ 1.937552] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10619 23:04:13.534796 <4>[ 1.948477] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10620 23:04:13.541510 <3>[ 1.959025] debugfs: File 'uA_load' in directory '/' already present!
10621 23:04:13.548587 <3>[ 1.965783] debugfs: File 'min_uV' in directory '/' already present!
10622 23:04:13.554873 <3>[ 1.972417] debugfs: File 'max_uV' in directory '/' already present!
10623 23:04:13.561290 <3>[ 1.979054] debugfs: File 'constraint_flags' in directory '/' already present!
10624 23:04:13.572796 <3>[ 1.988941] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10625 23:04:13.582130 <6>[ 2.001356] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10626 23:04:13.588973 <6>[ 2.008148] xhci-mtk 11200000.usb: xHCI Host Controller
10627 23:04:13.595674 <6>[ 2.013681] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10628 23:04:13.605454 <6>[ 2.021521] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10629 23:04:13.612603 <6>[ 2.030947] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10630 23:04:13.619078 <6>[ 2.036988] xhci-mtk 11200000.usb: xHCI Host Controller
10631 23:04:13.625683 <6>[ 2.042463] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10632 23:04:13.632722 <6>[ 2.050109] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10633 23:04:13.639023 <6>[ 2.057786] hub 1-0:1.0: USB hub found
10634 23:04:13.642371 <6>[ 2.061797] hub 1-0:1.0: 1 port detected
10635 23:04:13.648984 <6>[ 2.066067] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10636 23:04:13.655430 <6>[ 2.074697] hub 2-0:1.0: USB hub found
10637 23:04:13.658574 <6>[ 2.078714] hub 2-0:1.0: 1 port detected
10638 23:04:13.667497 <6>[ 2.087171] mtk-msdc 11f70000.mmc: Got CD GPIO
10639 23:04:13.678010 <6>[ 2.093857] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10640 23:04:13.684283 <6>[ 2.101882] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10641 23:04:13.694399 <4>[ 2.109797] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10642 23:04:13.704345 <6>[ 2.119320] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10643 23:04:13.711046 <6>[ 2.127399] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10644 23:04:13.717804 <6>[ 2.135502] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10645 23:04:13.728081 <6>[ 2.143420] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10646 23:04:13.734449 <6>[ 2.151238] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10647 23:04:13.744524 <6>[ 2.159058] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10648 23:04:13.754431 <6>[ 2.169692] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10649 23:04:13.761096 <6>[ 2.178078] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10650 23:04:13.770698 <6>[ 2.186416] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10651 23:04:13.777850 <6>[ 2.194755] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10652 23:04:13.787590 <6>[ 2.203093] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10653 23:04:13.793728 <6>[ 2.211433] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10654 23:04:13.803986 <6>[ 2.219771] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10655 23:04:13.810371 <6>[ 2.228108] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10656 23:04:13.820425 <6>[ 2.236447] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10657 23:04:13.827224 <6>[ 2.244786] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10658 23:04:13.836983 <6>[ 2.253134] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10659 23:04:13.844002 <6>[ 2.261473] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10660 23:04:13.854135 <6>[ 2.269811] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10661 23:04:13.860301 <6>[ 2.278150] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10662 23:04:13.870784 <6>[ 2.286489] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10663 23:04:13.876914 <6>[ 2.295283] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10664 23:04:13.883888 <6>[ 2.302436] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10665 23:04:13.890427 <6>[ 2.309206] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10666 23:04:13.896850 <6>[ 2.315959] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10667 23:04:13.903651 <6>[ 2.322892] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10668 23:04:13.913523 <6>[ 2.329735] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10669 23:04:13.923932 <6>[ 2.338862] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10670 23:04:13.933367 <6>[ 2.347980] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10671 23:04:13.943449 <6>[ 2.357274] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10672 23:04:13.953049 <6>[ 2.366761] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10673 23:04:13.960185 <6>[ 2.376229] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10674 23:04:13.969796 <6>[ 2.385351] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10675 23:04:13.979998 <6>[ 2.394820] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10676 23:04:13.989862 <6>[ 2.403938] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10677 23:04:13.999979 <6>[ 2.413231] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10678 23:04:14.009297 <6>[ 2.423391] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10679 23:04:14.019055 <6>[ 2.435364] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10680 23:04:14.025737 <6>[ 2.445137] Trying to probe devices needed for running init ...
10681 23:04:14.049308 <6>[ 2.465317] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10682 23:04:14.078153 <6>[ 2.496913] hub 2-1:1.0: USB hub found
10683 23:04:14.081102 <6>[ 2.501449] hub 2-1:1.0: 3 ports detected
10684 23:04:14.089653 <6>[ 2.508816] hub 2-1:1.0: USB hub found
10685 23:04:14.092598 <6>[ 2.513246] hub 2-1:1.0: 3 ports detected
10686 23:04:14.201186 <6>[ 2.616994] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10687 23:04:14.355793 <6>[ 2.775167] hub 1-1:1.0: USB hub found
10688 23:04:14.359619 <6>[ 2.779636] hub 1-1:1.0: 4 ports detected
10689 23:04:14.368821 <6>[ 2.788128] hub 1-1:1.0: USB hub found
10690 23:04:14.371602 <6>[ 2.792467] hub 1-1:1.0: 4 ports detected
10691 23:04:14.433091 <6>[ 2.849375] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10692 23:04:14.692700 <6>[ 3.109100] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10693 23:04:14.825445 <6>[ 3.245007] hub 1-1.4:1.0: USB hub found
10694 23:04:14.829004 <6>[ 3.249696] hub 1-1.4:1.0: 2 ports detected
10695 23:04:14.839221 <6>[ 3.258571] hub 1-1.4:1.0: USB hub found
10696 23:04:14.842358 <6>[ 3.263175] hub 1-1.4:1.0: 2 ports detected
10697 23:04:15.140710 <6>[ 3.557084] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10698 23:04:15.333114 <6>[ 3.749086] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10699 23:04:26.310193 <6>[ 14.734078] ALSA device list:
10700 23:04:26.316808 <6>[ 14.737370] No soundcards found.
10701 23:04:26.324936 <6>[ 14.745386] Freeing unused kernel memory: 8448K
10702 23:04:26.327945 <6>[ 14.750351] Run /init as init process
10703 23:04:26.339031 Loading, please wait...
10704 23:04:26.360121 Starting version 247.3-7+deb11u2
10705 23:04:26.566614 <6>[ 14.983699] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10706 23:04:26.578103 <6>[ 14.998886] remoteproc remoteproc0: scp is available
10707 23:04:26.584862 <6>[ 15.004987] remoteproc remoteproc0: powering up scp
10708 23:04:26.591408 <6>[ 15.010153] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10709 23:04:26.598284 <6>[ 15.018625] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10710 23:04:26.608293 <3>[ 15.019157] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10711 23:04:26.614696 <6>[ 15.026387] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10712 23:04:26.618213 <6>[ 15.028527] mc: Linux media interface: v0.10
10713 23:04:26.627878 <3>[ 15.032485] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10714 23:04:26.634348 <6>[ 15.040340] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10715 23:04:26.644261 <3>[ 15.044646] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10716 23:04:26.650881 <6>[ 15.054027] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10717 23:04:26.657288 <6>[ 15.071675] videodev: Linux video capture interface: v2.00
10718 23:04:26.667642 <3>[ 15.079664] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10719 23:04:26.673972 <4>[ 15.091833] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10720 23:04:26.680848 <3>[ 15.092093] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10721 23:04:26.690791 <4>[ 15.100681] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10722 23:04:26.697274 <3>[ 15.107433] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10723 23:04:26.704017 <3>[ 15.107444] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10724 23:04:26.710816 <6>[ 15.113889] usbcore: registered new interface driver r8152
10725 23:04:26.720293 <6>[ 15.118532] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10726 23:04:26.727123 <3>[ 15.123683] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10727 23:04:26.736887 <4>[ 15.146421] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10728 23:04:26.740176 <4>[ 15.146421] Fallback method does not support PEC.
10729 23:04:26.750010 <6>[ 15.149519] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10730 23:04:26.757178 <6>[ 15.149530] remoteproc remoteproc0: remote processor scp is now up
10731 23:04:26.764326 <6>[ 15.149529] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10732 23:04:26.770785 <3>[ 15.153167] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10733 23:04:26.777396 <6>[ 15.155273] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10734 23:04:26.787421 <6>[ 15.156731] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10735 23:04:26.794061 <3>[ 15.184021] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10736 23:04:26.807729 <6>[ 15.185766] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10737 23:04:26.814424 <6>[ 15.186091] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10738 23:04:26.823940 <3>[ 15.188263] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10739 23:04:26.831298 <6>[ 15.197309] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10740 23:04:26.837337 <6>[ 15.202116] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10741 23:04:26.844172 <6>[ 15.202125] pci_bus 0000:00: root bus resource [bus 00-ff]
10742 23:04:26.850574 <6>[ 15.202132] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10743 23:04:26.860602 <6>[ 15.202134] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10744 23:04:26.867597 <6>[ 15.202164] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10745 23:04:26.873691 <6>[ 15.202177] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10746 23:04:26.877133 <6>[ 15.202239] pci 0000:00:00.0: supports D1 D2
10747 23:04:26.883689 <6>[ 15.202241] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10748 23:04:26.893692 <6>[ 15.203144] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10749 23:04:26.900245 <6>[ 15.203226] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10750 23:04:26.906782 <6>[ 15.203252] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10751 23:04:26.913134 <6>[ 15.203267] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10752 23:04:26.923291 <6>[ 15.203283] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10753 23:04:26.926831 <6>[ 15.203392] pci 0000:01:00.0: supports D1 D2
10754 23:04:26.933070 <6>[ 15.203393] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10755 23:04:26.939946 <3>[ 15.204563] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10756 23:04:26.950021 <3>[ 15.204567] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10757 23:04:26.959491 <3>[ 15.216700] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10758 23:04:26.966203 <6>[ 15.216989] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10759 23:04:26.973286 <6>[ 15.217012] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10760 23:04:26.983496 <6>[ 15.217015] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10761 23:04:26.989663 <6>[ 15.217023] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10762 23:04:26.996243 <6>[ 15.217035] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10763 23:04:27.006246 <6>[ 15.217048] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10764 23:04:27.009273 <6>[ 15.217060] pci 0000:00:00.0: PCI bridge to [bus 01]
10765 23:04:27.019132 <6>[ 15.217065] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10766 23:04:27.026062 <6>[ 15.217189] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10767 23:04:27.032507 <6>[ 15.217662] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10768 23:04:27.035931 <6>[ 15.217978] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10769 23:04:27.046111 <3>[ 15.221625] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10770 23:04:27.055825 <6>[ 15.223189] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10771 23:04:27.058900 <6>[ 15.242143] Bluetooth: Core ver 2.22
10772 23:04:27.065886 <3>[ 15.248795] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10773 23:04:27.075279 <3>[ 15.248804] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10774 23:04:27.082150 <6>[ 15.249094] usbcore: registered new interface driver cdc_ether
10775 23:04:27.085187 <6>[ 15.255997] NET: Registered PF_BLUETOOTH protocol family
10776 23:04:27.091786 <6>[ 15.257025] usbcore: registered new interface driver r8153_ecm
10777 23:04:27.098566 <5>[ 15.258859] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10778 23:04:27.108266 <3>[ 15.262812] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10779 23:04:27.115185 <3>[ 15.262818] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10780 23:04:27.121809 <6>[ 15.268665] Bluetooth: HCI device and connection manager initialized
10781 23:04:27.128652 <5>[ 15.270997] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10782 23:04:27.138285 <4>[ 15.271087] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10783 23:04:27.145184 <6>[ 15.271096] cfg80211: failed to load regulatory.db
10784 23:04:27.151160 <3>[ 15.275724] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10785 23:04:27.157662 <6>[ 15.276396] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10786 23:04:27.171021 <6>[ 15.281739] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10787 23:04:27.177994 <6>[ 15.281991] usbcore: registered new interface driver uvcvideo
10788 23:04:27.180980 <6>[ 15.285642] Bluetooth: HCI socket layer initialized
10789 23:04:27.190832 <4>[ 15.288074] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10790 23:04:27.200501 <4>[ 15.288086] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10791 23:04:27.207347 <6>[ 15.311333] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10792 23:04:27.210693 <6>[ 15.318971] Bluetooth: L2CAP socket layer initialized
10793 23:04:27.213941 <6>[ 15.357000] r8152 2-1.3:1.0 eth0: v1.12.13
10794 23:04:27.220468 <6>[ 15.359052] Bluetooth: SCO socket layer initialized
10795 23:04:27.227266 <6>[ 15.380588] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10796 23:04:27.233430 <6>[ 15.388148] r8152 2-1.3:1.0 enx0024323078ff: renamed from eth0
10797 23:04:27.240323 <6>[ 15.391248] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10798 23:04:27.247078 <6>[ 15.445079] usbcore: registered new interface driver btusb
10799 23:04:27.256520 <4>[ 15.446368] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10800 23:04:27.263743 <3>[ 15.446383] Bluetooth: hci0: Failed to load firmware file (-2)
10801 23:04:27.266661 <3>[ 15.446390] Bluetooth: hci0: Failed to set up firmware (-2)
10802 23:04:27.280257 <4>[ 15.446397] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10803 23:04:27.283019 <6>[ 15.471151] mt7921e 0000:01:00.0: ASIC revision: 79610010
10804 23:04:27.390396 <4>[ 15.804222] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10805 23:04:27.404730 Begin: Loading essential drivers ... done.
10806 23:04:27.411631 Begin: Running /scripts/init-premount ... done.
10807 23:04:27.418275 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10808 23:04:27.424817 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10809 23:04:27.431631 Device /sys/class/net/enx0024323078ff found
10810 23:04:27.432191 done.
10811 23:04:27.508803 <4>[ 15.923323] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10812 23:04:27.516286 IP-Config: enx0024323078ff hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10813 23:04:27.628077 <4>[ 16.042129] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10814 23:04:27.743822 <4>[ 16.158008] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10815 23:04:27.859500 <4>[ 16.273978] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10816 23:04:27.975857 <4>[ 16.389845] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10817 23:04:28.091349 <4>[ 16.505904] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10818 23:04:28.207517 <4>[ 16.621785] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10819 23:04:28.323621 <4>[ 16.737742] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10820 23:04:28.439542 <4>[ 16.853672] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10821 23:04:28.546781 <3>[ 16.967515] mt7921e 0000:01:00.0: hardware init failed
10822 23:04:28.584155 <6>[ 17.004948] r8152 2-1.3:1.0 enx0024323078ff: carrier on
10823 23:04:28.736579 IP-Config: no response after 2 secs - giving up
10824 23:04:28.779684 IP-Config: enx0024323078ff hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10825 23:04:28.786019 IP-Config: enx0024323078ff complete (dhcp from 192.168.201.1):
10826 23:04:28.792865 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10827 23:04:28.799538 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10828 23:04:28.805585 host : mt8192-asurada-spherion-r0-cbg-8
10829 23:04:28.812429 domain : lava-rack
10830 23:04:28.816352 rootserver: 192.168.201.1 rootpath:
10831 23:04:28.816910 filename :
10832 23:04:28.952535 done.
10833 23:04:28.960567 Begin: Running /scripts/nfs-bottom ... done.
10834 23:04:28.987398 Begin: Running /scripts/init-bottom ... done.
10835 23:04:30.267679 <6>[ 18.687890] NET: Registered PF_INET6 protocol family
10836 23:04:30.273761 <6>[ 18.694947] Segment Routing with IPv6
10837 23:04:30.276628 <6>[ 18.698930] In-situ OAM (IOAM) with IPv6
10838 23:04:30.409223 <30>[ 18.810692] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10839 23:04:30.416035 <30>[ 18.835223] systemd[1]: Detected architecture arm64.
10840 23:04:30.437129
10841 23:04:30.440325 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10842 23:04:30.440782
10843 23:04:30.459239 <30>[ 18.880439] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10844 23:04:31.461730 <30>[ 19.880064] systemd[1]: Queued start job for default target Graphical Interface.
10845 23:04:31.506346 <30>[ 19.927774] systemd[1]: Created slice system-getty.slice.
10846 23:04:31.512872 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10847 23:04:31.529486 <30>[ 19.950651] systemd[1]: Created slice system-modprobe.slice.
10848 23:04:31.535849 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10849 23:04:31.553108 <30>[ 19.974502] systemd[1]: Created slice system-serial\x2dgetty.slice.
10850 23:04:31.563156 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10851 23:04:31.576935 <30>[ 19.998261] systemd[1]: Created slice User and Session Slice.
10852 23:04:31.583240 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10853 23:04:31.603917 <30>[ 20.021966] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10854 23:04:31.613852 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10855 23:04:31.631174 <30>[ 20.049338] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10856 23:04:31.638191 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10857 23:04:31.659085 <30>[ 20.073578] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10858 23:04:31.665275 <30>[ 20.085760] systemd[1]: Reached target Local Encrypted Volumes.
10859 23:04:31.672630 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10860 23:04:31.688446 <30>[ 20.109297] systemd[1]: Reached target Paths.
10861 23:04:31.691495 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10862 23:04:31.707895 <30>[ 20.129101] systemd[1]: Reached target Remote File Systems.
10863 23:04:31.714376 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10864 23:04:31.732455 <30>[ 20.153442] systemd[1]: Reached target Slices.
10865 23:04:31.738623 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10866 23:04:31.751802 <30>[ 20.173136] systemd[1]: Reached target Swap.
10867 23:04:31.755131 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10868 23:04:31.775385 <30>[ 20.193587] systemd[1]: Listening on initctl Compatibility Named Pipe.
10869 23:04:31.782174 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10870 23:04:31.788888 <30>[ 20.210098] systemd[1]: Listening on Journal Audit Socket.
10871 23:04:31.795284 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10872 23:04:31.813031 <30>[ 20.234693] systemd[1]: Listening on Journal Socket (/dev/log).
10873 23:04:31.819641 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10874 23:04:31.836624 <30>[ 20.257789] systemd[1]: Listening on Journal Socket.
10875 23:04:31.843549 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10876 23:04:31.861179 <30>[ 20.278931] systemd[1]: Listening on Network Service Netlink Socket.
10877 23:04:31.867381 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10878 23:04:31.883070 <30>[ 20.304491] systemd[1]: Listening on udev Control Socket.
10879 23:04:31.889904 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10880 23:04:31.904883 <30>[ 20.325590] systemd[1]: Listening on udev Kernel Socket.
10881 23:04:31.910617 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10882 23:04:31.952008 <30>[ 20.373116] systemd[1]: Mounting Huge Pages File System...
10883 23:04:31.958206 Mounting [0;1;39mHuge Pages File System[0m...
10884 23:04:31.975852 <30>[ 20.397443] systemd[1]: Mounting POSIX Message Queue File System...
10885 23:04:31.982876 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10886 23:04:32.005828 <30>[ 20.427109] systemd[1]: Mounting Kernel Debug File System...
10887 23:04:32.012058 Mounting [0;1;39mKernel Debug File System[0m...
10888 23:04:32.031284 <30>[ 20.449383] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10889 23:04:32.043902 <30>[ 20.462182] systemd[1]: Starting Create list of static device nodes for the current kernel...
10890 23:04:32.050518 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10891 23:04:32.072502 <30>[ 20.493626] systemd[1]: Starting Load Kernel Module configfs...
10892 23:04:32.079035 Starting [0;1;39mLoad Kernel Module configfs[0m...
10893 23:04:32.096553 <30>[ 20.518176] systemd[1]: Starting Load Kernel Module drm...
10894 23:04:32.102754 Starting [0;1;39mLoad Kernel Module drm[0m...
10895 23:04:32.121244 <30>[ 20.542632] systemd[1]: Starting Load Kernel Module fuse...
10896 23:04:32.127427 Starting [0;1;39mLoad Kernel Module fuse[0m...
10897 23:04:32.168941 <30>[ 20.587093] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10898 23:04:32.175251 <6>[ 20.587290] fuse: init (API version 7.37)
10899 23:04:32.220625 <30>[ 20.642072] systemd[1]: Starting Journal Service...
10900 23:04:32.224449 Starting [0;1;39mJournal Service[0m...
10901 23:04:32.254103 <30>[ 20.675596] systemd[1]: Starting Load Kernel Modules...
10902 23:04:32.260448 Starting [0;1;39mLoad Kernel Modules[0m...
10903 23:04:32.281522 <30>[ 20.699938] systemd[1]: Starting Remount Root and Kernel File Systems...
10904 23:04:32.287770 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10905 23:04:32.307160 <30>[ 20.728728] systemd[1]: Starting Coldplug All udev Devices...
10906 23:04:32.313580 Starting [0;1;39mColdplug All udev Devices[0m...
10907 23:04:32.330450 <30>[ 20.752107] systemd[1]: Mounted Huge Pages File System.
10908 23:04:32.337340 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10909 23:04:32.352382 <30>[ 20.773799] systemd[1]: Mounted POSIX Message Queue File System.
10910 23:04:32.358796 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10911 23:04:32.377305 <3>[ 20.795165] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10912 23:04:32.383404 <30>[ 20.804537] systemd[1]: Mounted Kernel Debug File System.
10913 23:04:32.390051 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10914 23:04:32.407920 <30>[ 20.825700] systemd[1]: Finished Create list of static device nodes for the current kernel.
10915 23:04:32.418236 <3>[ 20.830359] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10916 23:04:32.424404 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10917 23:04:32.441657 <30>[ 20.862721] systemd[1]: modprobe@configfs.service: Succeeded.
10918 23:04:32.448347 <30>[ 20.869470] systemd[1]: Finished Load Kernel Module configfs.
10919 23:04:32.458559 [[0;32m OK [<3>[ 20.876283] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10920 23:04:32.464950 0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10921 23:04:32.480896 <30>[ 20.902080] systemd[1]: modprobe@drm.service: Succeeded.
10922 23:04:32.490824 <3>[ 20.907196] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10923 23:04:32.497663 <30>[ 20.908381] systemd[1]: Finished Load Kernel Module drm.
10924 23:04:32.500891 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10925 23:04:32.516987 <30>[ 20.938059] systemd[1]: modprobe@fuse.service: Succeeded.
10926 23:04:32.526863 <3>[ 20.940504] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10927 23:04:32.533397 <30>[ 20.944865] systemd[1]: Finished Load Kernel Module fuse.
10928 23:04:32.537053 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10929 23:04:32.555207 <3>[ 20.973488] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10930 23:04:32.561946 <30>[ 20.975896] systemd[1]: Finished Load Kernel Modules.
10931 23:04:32.568520 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10932 23:04:32.581315 <30>[ 21.002229] systemd[1]: Finished Remount Root and Kernel File Systems.
10933 23:04:32.591476 <3>[ 21.005087] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10934 23:04:32.597612 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10935 23:04:32.619893 <3>[ 21.037952] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10936 23:04:32.646931 <30>[ 21.068455] systemd[1]: Mounting FUSE Control File System...
10937 23:04:32.656564 <3>[ 21.069625] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10938 23:04:32.662994 Mounting [0;1;39mFUSE Control File System[0m...
10939 23:04:32.679523 <30>[ 21.099840] systemd[1]: Mounting Kernel Configuration File System...
10940 23:04:32.688986 <3>[ 21.105773] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10941 23:04:32.695897 Mounting [0;1;39mKernel Configuration File System[0m...
10942 23:04:32.724897 <30>[ 21.143335] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10943 23:04:32.735183 <30>[ 21.152555] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10944 23:04:32.772815 <30>[ 21.193602] systemd[1]: Starting Load/Save Random Seed...
10945 23:04:32.778915 Starting [0;1;39mLoad/Save Random Seed[0m...
10946 23:04:32.794786 <30>[ 21.216184] systemd[1]: Starting Apply Kernel Variables...
10947 23:04:32.801510 Starting [0;1;39mApply Kernel Variables[0m...
10948 23:04:32.820155 <30>[ 21.241740] systemd[1]: Starting Create System Users...
10949 23:04:32.840338 Starting [0;1;39mCreat<4>[ 21.250130] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10950 23:04:32.849940 e System Users[<3>[ 21.266502] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10951 23:04:32.850134 0m...
10952 23:04:32.865216 <30>[ 21.286983] systemd[1]: Started Journal Service.
10953 23:04:32.869015 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10954 23:04:32.891649 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10955 23:04:32.903376 See 'systemctl status systemd-udev-trigger.service' for details.
10956 23:04:32.920075 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10957 23:04:32.936276 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10958 23:04:32.953166 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10959 23:04:32.969651 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10960 23:04:33.029518 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10961 23:04:33.044491 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10962 23:04:33.063393 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10963 23:04:33.093255 <46>[ 21.511452] systemd-journald[298]: Received client request to flush runtime journal.
10964 23:04:34.498120 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10965 23:04:34.515964 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10966 23:04:34.527886 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10967 23:04:34.543968 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10968 23:04:34.587942 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10969 23:04:34.615228 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10970 23:04:34.805041 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10971 23:04:34.857168 Starting [0;1;39mNetwork Service[0m...
10972 23:04:35.039758 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10973 23:04:35.095550 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10974 23:04:35.119751 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10975 23:04:35.138374 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10976 23:04:35.447225 Starting [0;1;39mNetwork Time Synchronization[0m...
10977 23:04:35.467633 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10978 23:04:35.572866 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10979 23:04:35.599059 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10980 23:04:35.652630 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10981 23:04:35.716588 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10982 23:04:35.734328 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10983 23:04:35.803960 Starting [0;1;39mNetwork Name Resolution[0m...
10984 23:04:35.820147 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10985 23:04:35.836047 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10986 23:04:35.854676 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10987 23:04:35.866974 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10988 23:04:35.883309 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10989 23:04:36.570731 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10990 23:04:36.860781 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10991 23:04:36.913155 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10992 23:04:36.947710 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10993 23:04:36.959015 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10994 23:04:36.980381 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10995 23:04:36.994762 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10996 23:04:37.010724 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10997 23:04:37.051613 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10998 23:04:37.131220 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10999 23:04:37.251481 Starting [0;1;39mUser Login Management[0m...
11000 23:04:37.270193 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11001 23:04:37.675518 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
11002 23:04:37.691363 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
11003 23:04:37.710302 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
11004 23:04:37.755627 Starting [0;1;39mPermit User Sessions[0m...
11005 23:04:37.771274 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11006 23:04:37.804605 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
11007 23:04:37.822125 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11008 23:04:37.868017 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11009 23:04:37.888676 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11010 23:04:37.907500 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11011 23:04:37.923378 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11012 23:04:37.941673 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11013 23:04:37.959518 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11014 23:04:38.003487 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11015 23:04:38.051060 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11016 23:04:38.131586
11017 23:04:38.131741
11018 23:04:38.135127 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11019 23:04:38.135209
11020 23:04:38.138165 debian-bullseye-arm64 login: root (automatic login)
11021 23:04:38.138246
11022 23:04:38.138309
11023 23:04:38.505934 Linux debian-bullseye-arm64 6.1.64-cip10 #1 SMP PREEMPT Fri Dec 1 22:47:09 UTC 2023 aarch64
11024 23:04:38.506080
11025 23:04:38.512679 The programs included with the Debian GNU/Linux system are free software;
11026 23:04:38.519483 the exact distribution terms for each program are described in the
11027 23:04:38.522776 individual files in /usr/share/doc/*/copyright.
11028 23:04:38.522852
11029 23:04:38.529332 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11030 23:04:38.532700 permitted by applicable law.
11031 23:04:38.640038 Matched prompt #10: / #
11033 23:04:38.640340 Setting prompt string to ['/ #']
11034 23:04:38.640436 end: 2.2.5.1 login-action (duration 00:00:28) [common]
11036 23:04:38.640631 end: 2.2.5 auto-login-action (duration 00:00:28) [common]
11037 23:04:38.640717 start: 2.2.6 expect-shell-connection (timeout 00:03:13) [common]
11038 23:04:38.640785 Setting prompt string to ['/ #']
11039 23:04:38.640846 Forcing a shell prompt, looking for ['/ #']
11041 23:04:38.691078 / #
11042 23:04:38.691259 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11043 23:04:38.691343 Waiting using forced prompt support (timeout 00:02:30)
11044 23:04:38.696606
11045 23:04:38.696890 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11046 23:04:38.696985 start: 2.2.7 export-device-env (timeout 00:03:13) [common]
11048 23:04:38.797364 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12154420/extract-nfsrootfs-aawdswdf'
11049 23:04:38.802740 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12154420/extract-nfsrootfs-aawdswdf'
11051 23:04:38.903307 / # export NFS_SERVER_IP='192.168.201.1'
11052 23:04:38.908803 export NFS_SERVER_IP='192.168.201.1'
11053 23:04:38.909094 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11054 23:04:38.909187 end: 2.2 depthcharge-retry (duration 00:01:48) [common]
11055 23:04:38.909272 end: 2 depthcharge-action (duration 00:01:48) [common]
11056 23:04:38.909360 start: 3 lava-test-retry (timeout 00:01:00) [common]
11057 23:04:38.909444 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
11058 23:04:38.909518 Using namespace: common
11060 23:04:39.009886 / # #
11061 23:04:39.010068 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11062 23:04:39.015079 #
11063 23:04:39.015348 Using /lava-12154420
11065 23:04:39.115708 / # export SHELL=/bin/sh
11066 23:04:39.121568 export SHELL=/bin/sh
11068 23:04:39.222139 / # . /lava-12154420/environment
11069 23:04:39.228027 . /lava-12154420/environment
11071 23:04:39.334803 / # /lava-12154420/bin/lava-test-runner /lava-12154420/0
11072 23:04:39.335000 Test shell timeout: 10s (minimum of the action and connection timeout)
11073 23:04:39.340823 /lava-12154420/bin/lava-test-runner /lava-12154420/0
11074 23:04:39.624786 + export TESTRUN_ID=0_dmesg
11075 23:04:39.627844 + cd /lava-12154420/0/tests/0_dmesg
11076 23:04:39.631094 + cat uuid
11077 23:04:39.645853 + UUID=12154420_1.<8>[ 28.065131] <LAVA_SIGNAL_STARTRUN 0_dmesg 12154420_1.6.2.3.1>
11078 23:04:39.645949 6.2.3.1
11079 23:04:39.646015 + set +x
11080 23:04:39.646252 Received signal: <STARTRUN> 0_dmesg 12154420_1.6.2.3.1
11081 23:04:39.646325 Starting test lava.0_dmesg (12154420_1.6.2.3.1)
11082 23:04:39.646420 Skipping test definition patterns.
11083 23:04:39.652142 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
11084 23:04:39.758346 <8>[ 28.177784] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
11085 23:04:39.758669 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
11087 23:04:39.844959 <8>[ 28.264413] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
11088 23:04:39.845282 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
11090 23:04:39.933719 <8>[ 28.353155] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
11091 23:04:39.934029 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
11093 23:04:39.937144 + set +x
11094 23:04:39.940022 <8>[ 28.363086] <LAVA_SIGNAL_ENDRUN 0_dmesg 12154420_1.6.2.3.1>
11095 23:04:39.940275 Received signal: <ENDRUN> 0_dmesg 12154420_1.6.2.3.1
11096 23:04:39.940367 Ending use of test pattern.
11097 23:04:39.940431 Ending test lava.0_dmesg (12154420_1.6.2.3.1), duration 0.29
11099 23:04:39.949346 <LAVA_TEST_RUNNER EXIT>
11100 23:04:39.949597 ok: lava_test_shell seems to have completed
11101 23:04:39.949699 alert: pass
crit: pass
emerg: pass
11102 23:04:39.949784 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11103 23:04:39.949865 end: 3 lava-test-retry (duration 00:00:01) [common]
11104 23:04:39.949948 start: 4 lava-test-retry (timeout 00:01:00) [common]
11105 23:04:39.950027 start: 4.1 lava-test-shell (timeout 00:01:00) [common]
11106 23:04:39.950090 Using namespace: common
11108 23:04:40.050436 / # #
11109 23:04:40.050622 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11110 23:04:40.050744 Using /lava-12154420
11112 23:04:40.151100 export SHELL=/bin/sh
11113 23:04:40.151318 #
11115 23:04:40.251867 / # export SHELL=/bin/sh. /lava-12154420/environment
11116 23:04:40.252086
11118 23:04:40.352642 / # . /lava-12154420/environment/lava-12154420/bin/lava-test-runner /lava-12154420/1
11119 23:04:40.352811 Test shell timeout: 10s (minimum of the action and connection timeout)
11120 23:04:40.352958
11121 23:04:40.358052 / # /lava-12154420/bin/lava-test-runner /lava-12154420/1
11122 23:04:40.503993 + export TESTRUN_ID=1_bootrr
11123 23:04:40.507662 + cd /lava-12154420/1/tests/1_bootrr
11124 23:04:40.510649 + cat uuid
11125 23:04:40.527448 + UUID=12154420_<8>[ 28.946800] <LAVA_SIGNAL_STARTRUN 1_bootrr 12154420_1.6.2.3.5>
11126 23:04:40.527545 1.6.2.3.5
11127 23:04:40.527613 + set +x
11128 23:04:40.527852 Received signal: <STARTRUN> 1_bootrr 12154420_1.6.2.3.5
11129 23:04:40.527919 Starting test lava.1_bootrr (12154420_1.6.2.3.5)
11130 23:04:40.528000 Skipping test definition patterns.
11131 23:04:40.540243 + export PATH=/opt/bootrr/libexec/bootrr/helpers:/lava-12154420/1/../bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin
11132 23:04:40.543523 + cd /opt/bootrr/libexec/bootrr
11133 23:04:40.543610 + sh helpers/bootrr-auto
11134 23:04:40.625755 /lava-12154420/1/../bin/lava-test-case
11135 23:04:40.660985 <8>[ 29.080483] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=deferred-probe-empty RESULT=pass>
11136 23:04:40.661302 Received signal: <TESTCASE> TEST_CASE_ID=deferred-probe-empty RESULT=pass
11138 23:04:40.714641 /lava-12154420/1/../bin/lava-test-case
11139 23:04:40.746360 <8>[ 29.165996] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=all-cpus-are-online RESULT=pass>
11140 23:04:40.746671 Received signal: <TESTCASE> TEST_CASE_ID=all-cpus-are-online RESULT=pass
11142 23:04:40.776156 /lava-12154420/1/../bin/lava-test-case
11143 23:04:40.807784 <8>[ 29.227406] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm-chip-is-online RESULT=skip>
11144 23:04:40.808100 Received signal: <TESTCASE> TEST_CASE_ID=tpm-chip-is-online RESULT=skip
11146 23:04:40.872724 /lava-12154420/1/../bin/lava-test-case
11147 23:04:40.904803 <8>[ 29.324544] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass>
11148 23:04:40.905123 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass
11150 23:04:40.944645 /lava-12154420/1/../bin/lava-test-case
11151 23:04:40.976584 <8>[ 29.396272] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass>
11152 23:04:40.976894 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass
11154 23:04:41.021202 /lava-12154420/1/../bin/lava-test-case
11155 23:04:41.057896 <8>[ 29.477322] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass>
11156 23:04:41.058210 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass
11158 23:04:41.099031 /lava-12154420/1/../bin/lava-test-case
11159 23:04:41.133228 <8>[ 29.552926] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass>
11160 23:04:41.133543 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass
11162 23:04:41.177190 /lava-12154420/1/../bin/lava-test-case
11163 23:04:41.214535 <8>[ 29.634372] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass>
11164 23:04:41.214851 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass
11166 23:04:41.247630 /lava-12154420/1/../bin/lava-test-case
11167 23:04:41.277357 <8>[ 29.697194] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass>
11168 23:04:41.277689 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass
11170 23:04:41.312431 /lava-12154420/1/../bin/lava-test-case
11171 23:04:41.344074 <8>[ 29.763596] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass>
11172 23:04:41.344388 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass
11174 23:04:41.369461 /lava-12154420/1/../bin/lava-test-case
11175 23:04:41.404769 <8>[ 29.824725] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass>
11176 23:04:41.405073 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass
11178 23:04:41.450451 /lava-12154420/1/../bin/lava-test-case
11179 23:04:41.483085 <8>[ 29.902238] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass>
11180 23:04:41.483415 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass
11182 23:04:41.523571 /lava-12154420/1/../bin/lava-test-case
11183 23:04:41.558430 <8>[ 29.978167] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass>
11184 23:04:41.558728 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass
11186 23:04:41.608171 /lava-12154420/1/../bin/lava-test-case
11187 23:04:41.641458 <8>[ 30.060893] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass>
11188 23:04:41.641738 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass
11190 23:04:41.683182 /lava-12154420/1/../bin/lava-test-case
11191 23:04:41.717202 <8>[ 30.137138] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass>
11192 23:04:41.717460 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass
11194 23:04:41.746305 /lava-12154420/1/../bin/lava-test-case
11195 23:04:41.777439 <8>[ 30.197276] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass>
11196 23:04:41.777699 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass
11198 23:04:41.817372 /lava-12154420/1/../bin/lava-test-case
11199 23:04:41.850144 <8>[ 30.270109] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass>
11200 23:04:41.850409 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass
11202 23:04:41.873641 /lava-12154420/1/../bin/lava-test-case
11203 23:04:41.902123 <8>[ 30.322000] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass>
11204 23:04:41.902422 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass
11206 23:04:41.948146 /lava-12154420/1/../bin/lava-test-case
11207 23:04:41.980053 <8>[ 30.400088] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass>
11208 23:04:41.980348 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass
11210 23:04:42.008634 /lava-12154420/1/../bin/lava-test-case
11211 23:04:42.041124 <8>[ 30.460869] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass>
11212 23:04:42.041416 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass
11214 23:04:42.084606 /lava-12154420/1/../bin/lava-test-case
11215 23:04:42.116482 <8>[ 30.536506] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-probed RESULT=pass>
11216 23:04:42.116791 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-probed RESULT=pass
11218 23:04:42.139606 /lava-12154420/1/../bin/lava-test-case
11219 23:04:42.173397 <8>[ 30.593405] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass>
11220 23:04:42.173685 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass
11222 23:04:42.219612 /lava-12154420/1/../bin/lava-test-case
11223 23:04:42.252981 <8>[ 30.672580] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass>
11224 23:04:42.253279 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass
11226 23:04:42.282478 /lava-12154420/1/../bin/lava-test-case
11227 23:04:42.316549 <8>[ 30.736646] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass>
11228 23:04:42.316845 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass
11230 23:04:42.359051 /lava-12154420/1/../bin/lava-test-case
11231 23:04:42.391620 <8>[ 30.811617] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass>
11232 23:04:42.391883 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass
11234 23:04:42.436937 /lava-12154420/1/../bin/lava-test-case
11235 23:04:42.468968 <8>[ 30.888916] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass>
11236 23:04:42.469266 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass
11238 23:04:42.494654 /lava-12154420/1/../bin/lava-test-case
11239 23:04:42.526313 <8>[ 30.945964] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass>
11240 23:04:42.526577 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass
11242 23:04:42.568712 /lava-12154420/1/../bin/lava-test-case
11243 23:04:42.604830 <8>[ 31.024928] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass>
11244 23:04:42.605100 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass
11246 23:04:42.636400 /lava-12154420/1/../bin/lava-test-case
11247 23:04:42.669616 <8>[ 31.089806] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass>
11248 23:04:42.669888 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass
11250 23:04:42.709242 /lava-12154420/1/../bin/lava-test-case
11251 23:04:42.743840 <8>[ 31.164002] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass>
11252 23:04:42.744101 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass
11254 23:04:42.784952 /lava-12154420/1/../bin/lava-test-case
11255 23:04:42.816894 <8>[ 31.237021] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass>
11256 23:04:42.817157 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass
11258 23:04:42.856916 /lava-12154420/1/../bin/lava-test-case
11259 23:04:42.891369 <8>[ 31.311104] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass>
11260 23:04:42.891627 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass
11262 23:04:42.932951 /lava-12154420/1/../bin/lava-test-case
11263 23:04:42.966814 <8>[ 31.386563] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass>
11264 23:04:42.967074 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass
11266 23:04:43.001019 /lava-12154420/1/../bin/lava-test-case
11267 23:04:43.034930 <8>[ 31.455061] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass>
11268 23:04:43.035197 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass
11270 23:04:43.076118 /lava-12154420/1/../bin/lava-test-case
11271 23:04:43.112475 <8>[ 31.532659] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass>
11272 23:04:43.112740 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass
11274 23:04:43.155271 /lava-12154420/1/../bin/lava-test-case
11275 23:04:43.189451 <8>[ 31.609559] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass>
11276 23:04:43.189720 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass
11278 23:04:43.214153 /lava-12154420/1/../bin/lava-test-case
11279 23:04:43.245404 <8>[ 31.665238] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass>
11280 23:04:43.245679 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass
11282 23:04:43.284879 /lava-12154420/1/../bin/lava-test-case
11283 23:04:43.318453 <8>[ 31.738310] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass>
11284 23:04:43.318722 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass
11286 23:04:43.350771 /lava-12154420/1/../bin/lava-test-case
11287 23:04:43.384977 <8>[ 31.805017] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass>
11288 23:04:43.385236 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass
11290 23:04:43.429413 /lava-12154420/1/../bin/lava-test-case
11291 23:04:43.464189 <8>[ 31.884349] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass>
11292 23:04:43.464459 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass
11294 23:04:43.490450 /lava-12154420/1/../bin/lava-test-case
11295 23:04:43.524560 <8>[ 31.944154] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass>
11296 23:04:43.524843 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass
11298 23:04:43.567819 /lava-12154420/1/../bin/lava-test-case
11299 23:04:43.605386 <8>[ 32.025036] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass>
11300 23:04:43.605648 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass
11302 23:04:43.631822 /lava-12154420/1/../bin/lava-test-case
11303 23:04:43.664360 <8>[ 32.084007] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass>
11304 23:04:43.664622 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass
11306 23:04:43.710607 /lava-12154420/1/../bin/lava-test-case
11307 23:04:43.744950 <8>[ 32.164719] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-probed RESULT=pass>
11308 23:04:43.745225 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-probed RESULT=pass
11310 23:04:43.772843 /lava-12154420/1/../bin/lava-test-case
11311 23:04:43.804817 <8>[ 32.224513] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass>
11312 23:04:43.805077 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass
11314 23:04:43.848696 /lava-12154420/1/../bin/lava-test-case
11315 23:04:43.884909 <8>[ 32.304917] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass>
11316 23:04:43.885176 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass
11318 23:04:43.912696 /lava-12154420/1/../bin/lava-test-case
11319 23:04:43.944662 <8>[ 32.364608] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass>
11320 23:04:43.944920 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass
11322 23:04:43.986640 /lava-12154420/1/../bin/lava-test-case
11323 23:04:44.024006 <8>[ 32.444288] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-probed RESULT=pass>
11324 23:04:44.024292 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-probed RESULT=pass
11326 23:04:44.054830 /lava-12154420/1/../bin/lava-test-case
11327 23:04:44.085167 <8>[ 32.504875] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass>
11328 23:04:44.085427 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass
11330 23:04:44.125785 /lava-12154420/1/../bin/lava-test-case
11331 23:04:44.157985 <8>[ 32.577850] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass>
11332 23:04:44.158245 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass
11334 23:04:44.195960 /lava-12154420/1/../bin/lava-test-case
11335 23:04:44.230266 <8>[ 32.650352] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass>
11336 23:04:44.230529 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass
11338 23:04:44.255969 /lava-12154420/1/../bin/lava-test-case
11339 23:04:44.288169 <8>[ 32.708123] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass>
11340 23:04:44.288449 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass
11342 23:04:44.327568 /lava-12154420/1/../bin/lava-test-case
11343 23:04:44.361949 <8>[ 32.781458] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass>
11344 23:04:44.362212 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass
11346 23:04:44.391961 /lava-12154420/1/../bin/lava-test-case
11347 23:04:44.420804 <8>[ 32.840875] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass>
11348 23:04:44.421063 Received signal: <TESTCASE> TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass
11350 23:04:44.459794 /lava-12154420/1/../bin/lava-test-case
11351 23:04:44.495787 <8>[ 32.915863] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass>
11352 23:04:44.496049 Received signal: <TESTCASE> TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass
11354 23:04:44.535466 /lava-12154420/1/../bin/lava-test-case
11355 23:04:44.568208 <8>[ 32.988397] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass>
11356 23:04:44.568485 Received signal: <TESTCASE> TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass
11358 23:04:44.613304 /lava-12154420/1/../bin/lava-test-case
11359 23:04:44.646980 <8>[ 33.067145] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass>
11360 23:04:44.647242 Received signal: <TESTCASE> TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass
11362 23:04:44.685330 /lava-12154420/1/../bin/lava-test-case
11363 23:04:44.718968 <8>[ 33.139252] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass>
11364 23:04:44.719232 Received signal: <TESTCASE> TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass
11366 23:04:44.762803 /lava-12154420/1/../bin/lava-test-case
11367 23:04:44.796137 <8>[ 33.216109] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass>
11368 23:04:44.796443 Received signal: <TESTCASE> TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass
11370 23:04:44.820653 /lava-12154420/1/../bin/lava-test-case
11371 23:04:44.853310 <8>[ 33.273321] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-driver-present RESULT=pass>
11372 23:04:44.853577 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-driver-present RESULT=pass
11374 23:04:44.893162 /lava-12154420/1/../bin/lava-test-case
11375 23:04:44.924817 <8>[ 33.345116] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi1-probed RESULT=pass>
11376 23:04:44.925082 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi1-probed RESULT=pass
11378 23:04:44.962901 /lava-12154420/1/../bin/lava-test-case
11379 23:04:44.994202 <8>[ 33.414373] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi5-probed RESULT=pass>
11380 23:04:44.994462 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi5-probed RESULT=pass
11382 23:04:45.016644 /lava-12154420/1/../bin/lava-test-case
11383 23:04:45.045439 <8>[ 33.465636] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass>
11384 23:04:45.045701 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass
11386 23:04:45.090196 /lava-12154420/1/../bin/lava-test-case
11387 23:04:45.123047 <8>[ 33.543056] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-probed RESULT=pass>
11388 23:04:45.123312 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-probed RESULT=pass
11390 23:04:45.146036 /lava-12154420/1/../bin/lava-test-case
11391 23:04:45.175957 <8>[ 33.595953] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass>
11392 23:04:45.176239 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass
11394 23:04:45.215092 /lava-12154420/1/../bin/lava-test-case
11395 23:04:45.247074 <8>[ 33.667034] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-probed RESULT=pass>
11396 23:04:45.247334 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-probed RESULT=pass
11398 23:04:45.272392 /lava-12154420/1/../bin/lava-test-case
11399 23:04:45.304507 <8>[ 33.724689] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass>
11400 23:04:45.304766 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass
11402 23:04:45.341287 /lava-12154420/1/../bin/lava-test-case
11403 23:04:45.371782 <8>[ 33.792013] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass>
11404 23:04:45.372037 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass
11406 23:04:45.408514 /lava-12154420/1/../bin/lava-test-case
11407 23:04:45.439973 <8>[ 33.860051] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass>
11408 23:04:45.440259 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass
11410 23:04:45.484646 /lava-12154420/1/../bin/lava-test-case
11411 23:04:45.518742 <8>[ 33.938587] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass>
11412 23:04:45.519010 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass
11414 23:04:45.561113 /lava-12154420/1/../bin/lava-test-case
11415 23:04:45.590322 <8>[ 34.010452] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass>
11416 23:04:45.590578 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass
11418 23:04:45.628646 /lava-12154420/1/../bin/lava-test-case
11419 23:04:45.659435 <8>[ 34.079554] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass>
11420 23:04:45.659694 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass
11422 23:04:45.695623 /lava-12154420/1/../bin/lava-test-case
11423 23:04:45.726789 <8>[ 34.147076] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass>
11424 23:04:45.727049 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass
11426 23:04:45.763477 /lava-12154420/1/../bin/lava-test-case
11427 23:04:45.794189 <8>[ 34.214438] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass>
11428 23:04:45.794452 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass
11430 23:04:45.837467 /lava-12154420/1/../bin/lava-test-case
11431 23:04:45.863632 <8>[ 34.283974] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass>
11432 23:04:45.863917 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass
11434 23:04:45.901313 /lava-12154420/1/../bin/lava-test-case
11435 23:04:45.932860 <8>[ 34.353102] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass>
11436 23:04:45.933143 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass
11438 23:04:45.972041 /lava-12154420/1/../bin/lava-test-case
11439 23:04:46.004696 <8>[ 34.424969] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass>
11440 23:04:46.004963 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass
11442 23:04:46.044970 /lava-12154420/1/../bin/lava-test-case
11443 23:04:46.080182 <8>[ 34.500539] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass>
11444 23:04:46.080488 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass
11446 23:04:46.118452 /lava-12154420/1/../bin/lava-test-case
11447 23:04:46.146907 <8>[ 34.567223] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass>
11448 23:04:46.147169 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass
11450 23:04:46.189248 /lava-12154420/1/../bin/lava-test-case
11451 23:04:46.219038 <8>[ 34.639103] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass>
11452 23:04:46.219308 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass
11454 23:04:46.256479 /lava-12154420/1/../bin/lava-test-case
11455 23:04:46.287817 <8>[ 34.708059] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass>
11456 23:04:46.288081 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass
11458 23:04:46.326500 /lava-12154420/1/../bin/lava-test-case
11459 23:04:46.356522 <8>[ 34.776597] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass>
11460 23:04:46.356784 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass
11462 23:04:46.381525 /lava-12154420/1/../bin/lava-test-case
11463 23:04:46.414880 <8>[ 34.835197] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass>
11464 23:04:46.415148 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass
11466 23:04:46.456671 /lava-12154420/1/../bin/lava-test-case
11467 23:04:46.494500 <8>[ 34.914756] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-probed RESULT=pass>
11468 23:04:46.494770 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-probed RESULT=pass
11470 23:04:46.519260 /lava-12154420/1/../bin/lava-test-case
11471 23:04:46.551140 <8>[ 34.971271] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass>
11472 23:04:46.551403 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass
11474 23:04:46.590724 /lava-12154420/1/../bin/lava-test-case
11475 23:04:46.622217 <8>[ 35.042696] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-probed RESULT=pass>
11476 23:04:46.622493 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-probed RESULT=pass
11478 23:04:46.650148 /lava-12154420/1/../bin/lava-test-case
11479 23:04:46.684825 <8>[ 35.105030] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass>
11480 23:04:46.685085 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass
11482 23:04:46.724629 /lava-12154420/1/../bin/lava-test-case
11483 23:04:46.756517 <8>[ 35.176885] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass>
11484 23:04:46.756778 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass
11486 23:04:46.785420 /lava-12154420/1/../bin/lava-test-case
11487 23:04:46.818173 <8>[ 35.238439] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass>
11488 23:04:46.818435 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass
11490 23:04:46.857045 /lava-12154420/1/../bin/lava-test-case
11491 23:04:46.889078 <8>[ 35.309277] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-probed RESULT=pass>
11492 23:04:46.889347 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-probed RESULT=pass
11494 23:04:46.912469 /lava-12154420/1/../bin/lava-test-case
11495 23:04:46.942738 <8>[ 35.363398] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass>
11496 23:04:46.943015 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass
11498 23:04:46.981193 /lava-12154420/1/../bin/lava-test-case
11499 23:04:47.012076 <8>[ 35.432523] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass>
11500 23:04:47.012349 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass
11502 23:04:47.035657 /lava-12154420/1/../bin/lava-test-case
11503 23:04:47.066366 <8>[ 35.486755] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass>
11504 23:04:47.066629 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass
11506 23:04:47.103620 /lava-12154420/1/../bin/lava-test-case
11507 23:04:47.131023 <8>[ 35.551429] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass>
11508 23:04:47.131293 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass
11510 23:04:47.176836 /lava-12154420/1/../bin/lava-test-case
11511 23:04:47.208446 <8>[ 35.628973] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass>
11512 23:04:47.208711 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass
11514 23:04:47.233362 /lava-12154420/1/../bin/lava-test-case
11515 23:04:47.265115 <8>[ 35.685076] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass>
11516 23:04:47.265379 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass
11518 23:04:47.302915 /lava-12154420/1/../bin/lava-test-case
11519 23:04:47.337084 <8>[ 35.757332] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass>
11520 23:04:47.337354 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass
11522 23:04:47.362468 /lava-12154420/1/../bin/lava-test-case
11523 23:04:47.397417 <8>[ 35.817521] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-driver-present RESULT=pass>
11524 23:04:47.397681 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-driver-present RESULT=pass
11526 23:04:47.434042 /lava-12154420/1/../bin/lava-test-case
11527 23:04:47.465360 <8>[ 35.885925] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-probed RESULT=pass>
11528 23:04:47.465622 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-probed RESULT=pass
11530 23:04:47.496004 /lava-12154420/1/../bin/lava-test-case
11531 23:04:47.527932 <8>[ 35.948079] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-driver-present RESULT=pass>
11532 23:04:47.528212 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-driver-present RESULT=pass
11534 23:04:48.588434 /lava-12154420/1/../bin/lava-test-case
11535 23:04:48.622008 <8>[ 37.042453] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-probed RESULT=fail>
11536 23:04:48.622291 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-probed RESULT=fail
11538 23:04:48.648529 /lava-12154420/1/../bin/lava-test-case
11539 23:04:48.679686 <8>[ 37.100055] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-driver-present RESULT=pass>
11540 23:04:48.679940 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-driver-present RESULT=pass
11542 23:04:49.733344 /lava-12154420/1/../bin/lava-test-case
11543 23:04:49.767930 <8>[ 38.188522] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-probed RESULT=fail>
11544 23:04:49.768239 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-probed RESULT=fail
11546 23:04:49.788761 /lava-12154420/1/../bin/lava-test-case
11547 23:04:49.819086 <8>[ 38.240036] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass>
11548 23:04:49.819355 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass
11550 23:04:50.869263 /lava-12154420/1/../bin/lava-test-case
11551 23:04:50.903325 <8>[ 39.324283] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail>
11552 23:04:50.903603 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail
11554 23:04:50.927331 /lava-12154420/1/../bin/lava-test-case
11555 23:04:50.959182 <8>[ 39.379746] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass>
11556 23:04:50.959440 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass
11558 23:04:52.015563 /lava-12154420/1/../bin/lava-test-case
11559 23:04:52.049428 <8>[ 40.470389] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-probed RESULT=fail>
11560 23:04:52.049798 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-probed RESULT=fail
11562 23:04:52.072892 /lava-12154420/1/../bin/lava-test-case
11563 23:04:52.104035 <8>[ 40.525260] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-driver-present RESULT=pass>
11564 23:04:52.104416 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-driver-present RESULT=pass
11566 23:04:53.155908 /lava-12154420/1/../bin/lava-test-case
11567 23:04:53.192545 <8>[ 41.613526] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-3-probed RESULT=fail>
11568 23:04:53.192972 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-3-probed RESULT=fail
11570 23:04:53.215502 /lava-12154420/1/../bin/lava-test-case
11571 23:04:53.247250 <8>[ 41.668477] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass>
11572 23:04:53.247583 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass
11574 23:04:54.302103 /lava-12154420/1/../bin/lava-test-case
11575 23:04:54.331500 <8>[ 42.752700] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail>
11576 23:04:54.331825 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail
11578 23:04:54.358057 /lava-12154420/1/../bin/lava-test-case
11579 23:04:54.393513 <8>[ 42.814818] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass>
11580 23:04:54.393839 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass
11582 23:04:55.444299 /lava-12154420/1/../bin/lava-test-case
11583 23:04:55.478853 <8>[ 43.900042] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-probed RESULT=fail>
11584 23:04:55.479229 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-probed RESULT=fail
11586 23:04:55.501659 /lava-12154420/1/../bin/lava-test-case
11587 23:04:55.537358 <8>[ 43.958943] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-edp-driver-present RESULT=pass>
11588 23:04:55.537730 Received signal: <TESTCASE> TEST_CASE_ID=panel-edp-driver-present RESULT=pass
11590 23:04:55.564445 /lava-12154420/1/../bin/lava-test-case
11591 23:04:55.598967 <8>[ 44.020347] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass>
11592 23:04:55.599342 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass
11594 23:04:56.646769 /lava-12154420/1/../bin/lava-test-case
11595 23:04:56.678410 <8>[ 45.099853] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail>
11596 23:04:56.678796 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail
11598 23:04:56.703788 /lava-12154420/1/../bin/lava-test-case
11599 23:04:56.733419 <8>[ 45.154992] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass>
11600 23:04:56.733794 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass
11602 23:04:56.774887 /lava-12154420/1/../bin/lava-test-case
11603 23:04:56.809292 <8>[ 45.230532] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-probed RESULT=pass>
11604 23:04:56.809664 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-probed RESULT=pass
11606 23:04:56.833947 /lava-12154420/1/../bin/lava-test-case
11607 23:04:56.864121 <8>[ 45.285333] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass>
11608 23:04:56.864536 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass
11610 23:04:56.904729 /lava-12154420/1/../bin/lava-test-case
11611 23:04:56.938078 <8>[ 45.359686] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass>
11612 23:04:56.938478 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass
11614 23:04:56.981922 /lava-12154420/1/../bin/lava-test-case
11615 23:04:57.013083 <8>[ 45.434678] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass>
11616 23:04:57.013452 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass
11618 23:04:57.052080 /lava-12154420/1/../bin/lava-test-case
11619 23:04:57.083249 <8>[ 45.504904] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass>
11620 23:04:57.083621 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass
11622 23:04:57.110378 /lava-12154420/1/../bin/lava-test-case
11623 23:04:57.141721 <8>[ 45.562887] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass>
11624 23:04:57.142099 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass
11626 23:04:57.183026 /lava-12154420/1/../bin/lava-test-case
11627 23:04:57.216117 <8>[ 45.637428] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass>
11628 23:04:57.216545 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass
11630 23:04:57.252401 /lava-12154420/1/../bin/lava-test-case
11631 23:04:57.284087 <8>[ 45.705447] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass>
11632 23:04:57.284516 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass
11634 23:04:57.313706 /lava-12154420/1/../bin/lava-test-case
11635 23:04:57.343252 <8>[ 45.764763] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass>
11636 23:04:57.343627 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass
11638 23:04:57.385066 /lava-12154420/1/../bin/lava-test-case
11639 23:04:57.418321 <8>[ 45.839656] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass>
11640 23:04:57.418702 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass
11642 23:04:57.442958 /lava-12154420/1/../bin/lava-test-case
11643 23:04:57.474128 <8>[ 45.895817] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass>
11644 23:04:57.474504 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass
11646 23:04:57.517052 /lava-12154420/1/../bin/lava-test-case
11647 23:04:57.551109 <8>[ 45.972537] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass>
11648 23:04:57.551489 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass
11650 23:04:57.576936 /lava-12154420/1/../bin/lava-test-case
11651 23:04:57.610764 <8>[ 46.032332] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass>
11652 23:04:57.611138 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass
11654 23:04:57.655956 /lava-12154420/1/../bin/lava-test-case
11655 23:04:57.688221 <8>[ 46.109640] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass>
11656 23:04:57.688594 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass
11658 23:04:57.712689 /lava-12154420/1/../bin/lava-test-case
11659 23:04:57.732784 <6>[ 46.161021] vpu: disabling
11660 23:04:57.736113 <6>[ 46.164171] vproc2: disabling
11661 23:04:57.739470 <6>[ 46.167568] vproc1: disabling
11662 23:04:57.742884 <6>[ 46.170972] vaud18: disabling
11663 23:04:57.750118 <6>[ 46.174593] vsram_others: disabling
11664 23:04:57.752929 <6>[ 46.178680] va09: disabling
11665 23:04:57.756160 <6>[ 46.181957] vsram_md: disabling
11666 23:04:57.759678 <6>[ 46.185685] Vgpu: disabling
11667 23:04:57.769690 <8>[ 46.189216] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass>
11668 23:04:57.769999 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass
11670 23:04:57.810010 /lava-12154420/1/../bin/lava-test-case
11671 23:04:57.844823 <8>[ 46.266310] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass>
11672 23:04:57.845199 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass
11674 23:04:57.869851 /lava-12154420/1/../bin/lava-test-case
11675 23:04:57.900888 <8>[ 46.322457] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass>
11676 23:04:57.901191 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass
11678 23:04:57.939445 /lava-12154420/1/../bin/lava-test-case
11679 23:04:57.970710 <8>[ 46.392024] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-probed RESULT=pass>
11680 23:04:57.971037 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-probed RESULT=pass
11682 23:04:58.010701 /lava-12154420/1/../bin/lava-test-case
11683 23:04:58.046489 <8>[ 46.468305] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass>
11684 23:04:58.046921 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass
11686 23:04:59.100675 /lava-12154420/1/../bin/lava-test-case
11687 23:04:59.134618 <8>[ 47.556504] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-probed RESULT=fail>
11688 23:04:59.134984 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-probed RESULT=fail
11690 23:05:00.191909 /lava-12154420/1/../bin/lava-test-case
11691 23:05:00.231361 <8>[ 48.653145] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-7-probed RESULT=fail>
11692 23:05:00.231690 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-7-probed RESULT=fail
11694 23:05:00.258083 /lava-12154420/1/../bin/lava-test-case
11695 23:05:00.289201 <8>[ 48.711032] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-driver-present RESULT=pass>
11696 23:05:00.289525 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-driver-present RESULT=pass
11698 23:05:00.328915 /lava-12154420/1/../bin/lava-test-case
11699 23:05:00.364411 <8>[ 48.786363] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-probed RESULT=pass>
11700 23:05:00.364737 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-probed RESULT=pass
11702 23:05:00.390863 /lava-12154420/1/../bin/lava-test-case
11703 23:05:00.424682 <8>[ 48.846532] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass>
11704 23:05:00.425010 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass
11706 23:05:00.464881 /lava-12154420/1/../bin/lava-test-case
11707 23:05:00.498143 <8>[ 48.920206] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass>
11708 23:05:00.498468 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass
11710 23:05:00.529633 /lava-12154420/1/../bin/lava-test-case
11711 23:05:00.560445 <8>[ 48.982279] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-driver-present RESULT=pass>
11712 23:05:00.560780 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-driver-present RESULT=pass
11714 23:05:00.598859 /lava-12154420/1/../bin/lava-test-case
11715 23:05:00.630708 <8>[ 49.052273] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-probed RESULT=pass>
11716 23:05:00.630996 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-probed RESULT=pass
11718 23:05:00.654547 /lava-12154420/1/../bin/lava-test-case
11719 23:05:00.685479 <8>[ 49.107229] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass>
11720 23:05:00.685756 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass
11722 23:05:00.725698 /lava-12154420/1/../bin/lava-test-case
11723 23:05:00.760180 <8>[ 49.182024] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass>
11724 23:05:00.760523 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass
11726 23:05:00.786892 /lava-12154420/1/../bin/lava-test-case
11727 23:05:00.819029 <8>[ 49.240702] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass>
11728 23:05:00.819335 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass
11730 23:05:00.865073 /lava-12154420/1/../bin/lava-test-case
11731 23:05:00.898961 <8>[ 49.321143] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-probed RESULT=pass>
11732 23:05:00.899264 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-probed RESULT=pass
11734 23:05:00.926025 /lava-12154420/1/../bin/lava-test-case
11735 23:05:00.960438 <8>[ 49.382459] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass>
11736 23:05:00.960747 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass
11738 23:05:01.001630 /lava-12154420/1/../bin/lava-test-case
11739 23:05:01.031444 <8>[ 49.453409] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass>
11740 23:05:01.031805 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass
11742 23:05:01.055956 /lava-12154420/1/../bin/lava-test-case
11743 23:05:01.086609 <8>[ 49.508592] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass>
11744 23:05:01.086958 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass
11746 23:05:01.122967 /lava-12154420/1/../bin/lava-test-case
11747 23:05:01.153386 <8>[ 49.575514] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-probed RESULT=pass>
11748 23:05:01.153700 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-probed RESULT=pass
11750 23:05:01.181822 /lava-12154420/1/../bin/lava-test-case
11751 23:05:01.213474 <8>[ 49.635458] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass>
11752 23:05:01.213813 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass
11754 23:05:01.258148 /lava-12154420/1/../bin/lava-test-case
11755 23:05:01.291245 <8>[ 49.713390] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-probed RESULT=pass>
11756 23:05:01.291542 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-probed RESULT=pass
11758 23:05:01.317644 /lava-12154420/1/../bin/lava-test-case
11759 23:05:01.350226 <8>[ 49.772051] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-driver-present RESULT=pass>
11760 23:05:01.350533 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-driver-present RESULT=pass
11762 23:05:01.388033 /lava-12154420/1/../bin/lava-test-case
11763 23:05:01.421906 <8>[ 49.844093] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-probed RESULT=pass>
11764 23:05:01.422219 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-probed RESULT=pass
11766 23:05:01.446106 /lava-12154420/1/../bin/lava-test-case
11767 23:05:01.477461 <8>[ 49.899495] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass>
11768 23:05:01.477758 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass
11770 23:05:01.513851 /lava-12154420/1/../bin/lava-test-case
11771 23:05:01.543107 <8>[ 49.964792] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass>
11772 23:05:01.543427 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass
11774 23:05:02.584048 /lava-12154420/1/../bin/lava-test-case
11775 23:05:02.621320 <8>[ 51.043404] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail>
11776 23:05:02.621660 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail
11778 23:05:39.950274 Marking unfinished test run as failed
11781 23:05:39.951838 end: 4.1 lava-test-shell (duration 00:01:00) [common]
11783 23:05:39.952838 lava-test-retry failed: 1 of 5 attempts. 'lava-test-shell timed out after 60 seconds'
11785 23:05:39.953730 end: 4 lava-test-retry (duration 00:01:00) [common]
11787 23:05:39.954991 Cleaning after the job
11788 23:05:39.955497 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12154420/tftp-deploy-1s1l4ozf/ramdisk
11789 23:05:39.968325 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12154420/tftp-deploy-1s1l4ozf/kernel
11790 23:05:39.998547 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12154420/tftp-deploy-1s1l4ozf/dtb
11791 23:05:39.998837 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12154420/tftp-deploy-1s1l4ozf/nfsrootfs
11792 23:05:40.074787 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12154420/tftp-deploy-1s1l4ozf/modules
11793 23:05:40.082402 start: 5.1 power-off (timeout 00:00:30) [common]
11794 23:05:40.082590 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
11795 23:05:40.160437 >> Command sent successfully.
11796 23:05:40.165317 Returned 0 in 0 seconds
11797 23:05:40.265972 end: 5.1 power-off (duration 00:00:00) [common]
11799 23:05:40.266290 start: 5.2 read-feedback (timeout 00:10:00) [common]
11800 23:05:40.266557 Listened to connection for namespace 'common' for up to 1s
11801 23:05:41.267472 Finalising connection for namespace 'common'
11802 23:05:41.267639 Disconnecting from shell: Finalise
11803 23:05:41.367996 end: 5.2 read-feedback (duration 00:00:01) [common]
11804 23:05:41.368168 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12154420
11805 23:05:41.747721 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12154420
11806 23:05:41.747919 TestError: A test failed to run, look at the error message.