Boot log: mt8192-asurada-spherion-r0
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 19
- Kernel Errors: 34
- Errors: 0
1 23:08:19.457780 lava-dispatcher, installed at version: 2023.10
2 23:08:19.457983 start: 0 validate
3 23:08:19.458114 Start time: 2023-12-01 23:08:19.458106+00:00 (UTC)
4 23:08:19.458233 Using caching service: 'http://localhost/cache/?uri=%s'
5 23:08:19.458387 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-cros-ec%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 23:08:19.744151 Using caching service: 'http://localhost/cache/?uri=%s'
7 23:08:19.744931 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.64-cip10%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 23:08:20.009085 Using caching service: 'http://localhost/cache/?uri=%s'
9 23:08:20.009897 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.64-cip10%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 23:08:20.281333 Using caching service: 'http://localhost/cache/?uri=%s'
11 23:08:20.282087 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.64-cip10%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 23:08:20.551371 validate duration: 1.09
14 23:08:20.552789 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 23:08:20.553411 start: 1.1 download-retry (timeout 00:10:00) [common]
16 23:08:20.553938 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 23:08:20.554573 Not decompressing ramdisk as can be used compressed.
18 23:08:20.555057 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-cros-ec/20230623.0/arm64/rootfs.cpio.gz
19 23:08:20.555427 saving as /var/lib/lava/dispatcher/tmp/12154449/tftp-deploy-dwu5w1iq/ramdisk/rootfs.cpio.gz
20 23:08:20.555801 total size: 34390042 (32 MB)
21 23:08:20.561958 progress 0 % (0 MB)
22 23:08:20.590338 progress 5 % (1 MB)
23 23:08:20.603468 progress 10 % (3 MB)
24 23:08:20.613703 progress 15 % (4 MB)
25 23:08:20.622743 progress 20 % (6 MB)
26 23:08:20.631920 progress 25 % (8 MB)
27 23:08:20.641124 progress 30 % (9 MB)
28 23:08:20.650270 progress 35 % (11 MB)
29 23:08:20.659252 progress 40 % (13 MB)
30 23:08:20.668322 progress 45 % (14 MB)
31 23:08:20.677213 progress 50 % (16 MB)
32 23:08:20.686281 progress 55 % (18 MB)
33 23:08:20.695341 progress 60 % (19 MB)
34 23:08:20.704602 progress 65 % (21 MB)
35 23:08:20.713567 progress 70 % (22 MB)
36 23:08:20.722626 progress 75 % (24 MB)
37 23:08:20.731457 progress 80 % (26 MB)
38 23:08:20.740567 progress 85 % (27 MB)
39 23:08:20.749391 progress 90 % (29 MB)
40 23:08:20.758251 progress 95 % (31 MB)
41 23:08:20.766795 progress 100 % (32 MB)
42 23:08:20.766975 32 MB downloaded in 0.21 s (155.29 MB/s)
43 23:08:20.767134 end: 1.1.1 http-download (duration 00:00:00) [common]
45 23:08:20.767376 end: 1.1 download-retry (duration 00:00:00) [common]
46 23:08:20.767462 start: 1.2 download-retry (timeout 00:10:00) [common]
47 23:08:20.767547 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 23:08:20.767689 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.64-cip10/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 23:08:20.767758 saving as /var/lib/lava/dispatcher/tmp/12154449/tftp-deploy-dwu5w1iq/kernel/Image
50 23:08:20.767820 total size: 49172992 (46 MB)
51 23:08:20.767881 No compression specified
52 23:08:20.769075 progress 0 % (0 MB)
53 23:08:20.781936 progress 5 % (2 MB)
54 23:08:20.794746 progress 10 % (4 MB)
55 23:08:20.807768 progress 15 % (7 MB)
56 23:08:20.820667 progress 20 % (9 MB)
57 23:08:20.833299 progress 25 % (11 MB)
58 23:08:20.846343 progress 30 % (14 MB)
59 23:08:20.859228 progress 35 % (16 MB)
60 23:08:20.871899 progress 40 % (18 MB)
61 23:08:20.884522 progress 45 % (21 MB)
62 23:08:20.897276 progress 50 % (23 MB)
63 23:08:20.910173 progress 55 % (25 MB)
64 23:08:20.923070 progress 60 % (28 MB)
65 23:08:20.936094 progress 65 % (30 MB)
66 23:08:20.949040 progress 70 % (32 MB)
67 23:08:20.961804 progress 75 % (35 MB)
68 23:08:20.974736 progress 80 % (37 MB)
69 23:08:20.987326 progress 85 % (39 MB)
70 23:08:21.000020 progress 90 % (42 MB)
71 23:08:21.012427 progress 95 % (44 MB)
72 23:08:21.024973 progress 100 % (46 MB)
73 23:08:21.025178 46 MB downloaded in 0.26 s (182.22 MB/s)
74 23:08:21.025327 end: 1.2.1 http-download (duration 00:00:00) [common]
76 23:08:21.025559 end: 1.2 download-retry (duration 00:00:00) [common]
77 23:08:21.025649 start: 1.3 download-retry (timeout 00:10:00) [common]
78 23:08:21.025735 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 23:08:21.025874 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.64-cip10/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 23:08:21.025946 saving as /var/lib/lava/dispatcher/tmp/12154449/tftp-deploy-dwu5w1iq/dtb/mt8192-asurada-spherion-r0.dtb
81 23:08:21.026062 total size: 47278 (0 MB)
82 23:08:21.026138 No compression specified
83 23:08:21.027192 progress 69 % (0 MB)
84 23:08:21.027461 progress 100 % (0 MB)
85 23:08:21.027616 0 MB downloaded in 0.00 s (29.05 MB/s)
86 23:08:21.027737 end: 1.3.1 http-download (duration 00:00:00) [common]
88 23:08:21.027955 end: 1.3 download-retry (duration 00:00:00) [common]
89 23:08:21.028039 start: 1.4 download-retry (timeout 00:10:00) [common]
90 23:08:21.028121 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 23:08:21.028237 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.64-cip10/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 23:08:21.028307 saving as /var/lib/lava/dispatcher/tmp/12154449/tftp-deploy-dwu5w1iq/modules/modules.tar
93 23:08:21.028369 total size: 8616152 (8 MB)
94 23:08:21.028431 Using unxz to decompress xz
95 23:08:21.032810 progress 0 % (0 MB)
96 23:08:21.053877 progress 5 % (0 MB)
97 23:08:21.077484 progress 10 % (0 MB)
98 23:08:21.100823 progress 15 % (1 MB)
99 23:08:21.123937 progress 20 % (1 MB)
100 23:08:21.147831 progress 25 % (2 MB)
101 23:08:21.173186 progress 30 % (2 MB)
102 23:08:21.198898 progress 35 % (2 MB)
103 23:08:21.222607 progress 40 % (3 MB)
104 23:08:21.248470 progress 45 % (3 MB)
105 23:08:21.273310 progress 50 % (4 MB)
106 23:08:21.297367 progress 55 % (4 MB)
107 23:08:21.321479 progress 60 % (4 MB)
108 23:08:21.346357 progress 65 % (5 MB)
109 23:08:21.372488 progress 70 % (5 MB)
110 23:08:21.395648 progress 75 % (6 MB)
111 23:08:21.422105 progress 80 % (6 MB)
112 23:08:21.447191 progress 85 % (7 MB)
113 23:08:21.471488 progress 90 % (7 MB)
114 23:08:21.501103 progress 95 % (7 MB)
115 23:08:21.528832 progress 100 % (8 MB)
116 23:08:21.535019 8 MB downloaded in 0.51 s (16.22 MB/s)
117 23:08:21.535275 end: 1.4.1 http-download (duration 00:00:01) [common]
119 23:08:21.535545 end: 1.4 download-retry (duration 00:00:01) [common]
120 23:08:21.535639 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 23:08:21.535736 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 23:08:21.535819 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 23:08:21.535960 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 23:08:21.536240 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12154449/lava-overlay-2ex0dpl6
125 23:08:21.536375 makedir: /var/lib/lava/dispatcher/tmp/12154449/lava-overlay-2ex0dpl6/lava-12154449/bin
126 23:08:21.536483 makedir: /var/lib/lava/dispatcher/tmp/12154449/lava-overlay-2ex0dpl6/lava-12154449/tests
127 23:08:21.536628 makedir: /var/lib/lava/dispatcher/tmp/12154449/lava-overlay-2ex0dpl6/lava-12154449/results
128 23:08:21.536749 Creating /var/lib/lava/dispatcher/tmp/12154449/lava-overlay-2ex0dpl6/lava-12154449/bin/lava-add-keys
129 23:08:21.536899 Creating /var/lib/lava/dispatcher/tmp/12154449/lava-overlay-2ex0dpl6/lava-12154449/bin/lava-add-sources
130 23:08:21.537033 Creating /var/lib/lava/dispatcher/tmp/12154449/lava-overlay-2ex0dpl6/lava-12154449/bin/lava-background-process-start
131 23:08:21.537165 Creating /var/lib/lava/dispatcher/tmp/12154449/lava-overlay-2ex0dpl6/lava-12154449/bin/lava-background-process-stop
132 23:08:21.537293 Creating /var/lib/lava/dispatcher/tmp/12154449/lava-overlay-2ex0dpl6/lava-12154449/bin/lava-common-functions
133 23:08:21.537420 Creating /var/lib/lava/dispatcher/tmp/12154449/lava-overlay-2ex0dpl6/lava-12154449/bin/lava-echo-ipv4
134 23:08:21.537586 Creating /var/lib/lava/dispatcher/tmp/12154449/lava-overlay-2ex0dpl6/lava-12154449/bin/lava-install-packages
135 23:08:21.537714 Creating /var/lib/lava/dispatcher/tmp/12154449/lava-overlay-2ex0dpl6/lava-12154449/bin/lava-installed-packages
136 23:08:21.537838 Creating /var/lib/lava/dispatcher/tmp/12154449/lava-overlay-2ex0dpl6/lava-12154449/bin/lava-os-build
137 23:08:21.537963 Creating /var/lib/lava/dispatcher/tmp/12154449/lava-overlay-2ex0dpl6/lava-12154449/bin/lava-probe-channel
138 23:08:21.538088 Creating /var/lib/lava/dispatcher/tmp/12154449/lava-overlay-2ex0dpl6/lava-12154449/bin/lava-probe-ip
139 23:08:21.538214 Creating /var/lib/lava/dispatcher/tmp/12154449/lava-overlay-2ex0dpl6/lava-12154449/bin/lava-target-ip
140 23:08:21.538338 Creating /var/lib/lava/dispatcher/tmp/12154449/lava-overlay-2ex0dpl6/lava-12154449/bin/lava-target-mac
141 23:08:21.538477 Creating /var/lib/lava/dispatcher/tmp/12154449/lava-overlay-2ex0dpl6/lava-12154449/bin/lava-target-storage
142 23:08:21.538623 Creating /var/lib/lava/dispatcher/tmp/12154449/lava-overlay-2ex0dpl6/lava-12154449/bin/lava-test-case
143 23:08:21.538750 Creating /var/lib/lava/dispatcher/tmp/12154449/lava-overlay-2ex0dpl6/lava-12154449/bin/lava-test-event
144 23:08:21.538877 Creating /var/lib/lava/dispatcher/tmp/12154449/lava-overlay-2ex0dpl6/lava-12154449/bin/lava-test-feedback
145 23:08:21.539002 Creating /var/lib/lava/dispatcher/tmp/12154449/lava-overlay-2ex0dpl6/lava-12154449/bin/lava-test-raise
146 23:08:21.539127 Creating /var/lib/lava/dispatcher/tmp/12154449/lava-overlay-2ex0dpl6/lava-12154449/bin/lava-test-reference
147 23:08:21.539251 Creating /var/lib/lava/dispatcher/tmp/12154449/lava-overlay-2ex0dpl6/lava-12154449/bin/lava-test-runner
148 23:08:21.539376 Creating /var/lib/lava/dispatcher/tmp/12154449/lava-overlay-2ex0dpl6/lava-12154449/bin/lava-test-set
149 23:08:21.539502 Creating /var/lib/lava/dispatcher/tmp/12154449/lava-overlay-2ex0dpl6/lava-12154449/bin/lava-test-shell
150 23:08:21.539690 Updating /var/lib/lava/dispatcher/tmp/12154449/lava-overlay-2ex0dpl6/lava-12154449/bin/lava-install-packages (oe)
151 23:08:21.546640 Updating /var/lib/lava/dispatcher/tmp/12154449/lava-overlay-2ex0dpl6/lava-12154449/bin/lava-installed-packages (oe)
152 23:08:21.546789 Creating /var/lib/lava/dispatcher/tmp/12154449/lava-overlay-2ex0dpl6/lava-12154449/environment
153 23:08:21.546895 LAVA metadata
154 23:08:21.546974 - LAVA_JOB_ID=12154449
155 23:08:21.547047 - LAVA_DISPATCHER_IP=192.168.201.1
156 23:08:21.547153 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 23:08:21.547238 skipped lava-vland-overlay
158 23:08:21.547327 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 23:08:21.547467 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 23:08:21.547537 skipped lava-multinode-overlay
161 23:08:21.547610 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 23:08:21.547744 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 23:08:21.547882 Loading test definitions
164 23:08:21.547988 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 23:08:21.548063 Using /lava-12154449 at stage 0
166 23:08:21.548371 uuid=12154449_1.5.2.3.1 testdef=None
167 23:08:21.548459 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 23:08:21.548604 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 23:08:21.549122 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 23:08:21.549354 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 23:08:21.556398 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 23:08:21.556694 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 23:08:21.557274 runner path: /var/lib/lava/dispatcher/tmp/12154449/lava-overlay-2ex0dpl6/lava-12154449/0/tests/0_cros-ec test_uuid 12154449_1.5.2.3.1
176 23:08:21.557431 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 23:08:21.557635 Creating lava-test-runner.conf files
179 23:08:21.557703 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12154449/lava-overlay-2ex0dpl6/lava-12154449/0 for stage 0
180 23:08:21.557793 - 0_cros-ec
181 23:08:21.557892 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 23:08:21.557979 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 23:08:21.564765 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 23:08:21.564872 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 23:08:21.564959 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 23:08:21.565044 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 23:08:21.565136 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 23:08:22.546574 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 23:08:22.546965 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 23:08:22.547082 extracting modules file /var/lib/lava/dispatcher/tmp/12154449/tftp-deploy-dwu5w1iq/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12154449/extract-overlay-ramdisk-6cdltduv/ramdisk
191 23:08:22.781337 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 23:08:22.781508 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 23:08:22.781605 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12154449/compress-overlay-81lqb462/overlay-1.5.2.4.tar.gz to ramdisk
194 23:08:22.781682 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12154449/compress-overlay-81lqb462/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12154449/extract-overlay-ramdisk-6cdltduv/ramdisk
195 23:08:22.788395 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 23:08:22.788573 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 23:08:22.788669 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 23:08:22.788767 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 23:08:22.788844 Building ramdisk /var/lib/lava/dispatcher/tmp/12154449/extract-overlay-ramdisk-6cdltduv/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12154449/extract-overlay-ramdisk-6cdltduv/ramdisk
200 23:08:23.566353 >> 271079 blocks
201 23:08:28.177064 rename /var/lib/lava/dispatcher/tmp/12154449/extract-overlay-ramdisk-6cdltduv/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12154449/tftp-deploy-dwu5w1iq/ramdisk/ramdisk.cpio.gz
202 23:08:28.177501 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 23:08:28.177629 start: 1.5.8 prepare-kernel (timeout 00:09:52) [common]
204 23:08:28.177729 start: 1.5.8.1 prepare-fit (timeout 00:09:52) [common]
205 23:08:28.177834 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12154449/tftp-deploy-dwu5w1iq/kernel/Image'
206 23:08:40.127464 Returned 0 in 11 seconds
207 23:08:40.228432 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12154449/tftp-deploy-dwu5w1iq/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12154449/tftp-deploy-dwu5w1iq/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12154449/tftp-deploy-dwu5w1iq/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12154449/tftp-deploy-dwu5w1iq/kernel/image.itb
208 23:08:40.961822 output: FIT description: Kernel Image image with one or more FDT blobs
209 23:08:40.962203 output: Created: Fri Dec 1 23:08:40 2023
210 23:08:40.962281 output: Image 0 (kernel-1)
211 23:08:40.962348 output: Description:
212 23:08:40.962412 output: Created: Fri Dec 1 23:08:40 2023
213 23:08:40.962480 output: Type: Kernel Image
214 23:08:40.962540 output: Compression: lzma compressed
215 23:08:40.962600 output: Data Size: 11043984 Bytes = 10785.14 KiB = 10.53 MiB
216 23:08:40.962658 output: Architecture: AArch64
217 23:08:40.962715 output: OS: Linux
218 23:08:40.962770 output: Load Address: 0x00000000
219 23:08:40.962827 output: Entry Point: 0x00000000
220 23:08:40.962884 output: Hash algo: crc32
221 23:08:40.962939 output: Hash value: 36c84243
222 23:08:40.962996 output: Image 1 (fdt-1)
223 23:08:40.963051 output: Description: mt8192-asurada-spherion-r0
224 23:08:40.963105 output: Created: Fri Dec 1 23:08:40 2023
225 23:08:40.963158 output: Type: Flat Device Tree
226 23:08:40.963211 output: Compression: uncompressed
227 23:08:40.963264 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 23:08:40.963316 output: Architecture: AArch64
229 23:08:40.963369 output: Hash algo: crc32
230 23:08:40.963422 output: Hash value: cc4352de
231 23:08:40.963475 output: Image 2 (ramdisk-1)
232 23:08:40.963528 output: Description: unavailable
233 23:08:40.963581 output: Created: Fri Dec 1 23:08:40 2023
234 23:08:40.963660 output: Type: RAMDisk Image
235 23:08:40.963727 output: Compression: Unknown Compression
236 23:08:40.963780 output: Data Size: 47535571 Bytes = 46421.46 KiB = 45.33 MiB
237 23:08:40.963833 output: Architecture: AArch64
238 23:08:40.963886 output: OS: Linux
239 23:08:40.963939 output: Load Address: unavailable
240 23:08:40.963992 output: Entry Point: unavailable
241 23:08:40.964044 output: Hash algo: crc32
242 23:08:40.964097 output: Hash value: 73c1e4f0
243 23:08:40.964150 output: Default Configuration: 'conf-1'
244 23:08:40.964202 output: Configuration 0 (conf-1)
245 23:08:40.964255 output: Description: mt8192-asurada-spherion-r0
246 23:08:40.964329 output: Kernel: kernel-1
247 23:08:40.964396 output: Init Ramdisk: ramdisk-1
248 23:08:40.964449 output: FDT: fdt-1
249 23:08:40.964502 output: Loadables: kernel-1
250 23:08:40.964638 output:
251 23:08:40.964922 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
252 23:08:40.965023 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
253 23:08:40.965128 end: 1.5 prepare-tftp-overlay (duration 00:00:19) [common]
254 23:08:40.965222 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:40) [common]
255 23:08:40.965300 No LXC device requested
256 23:08:40.965385 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 23:08:40.965470 start: 1.7 deploy-device-env (timeout 00:09:40) [common]
258 23:08:40.965564 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 23:08:40.965653 Checking files for TFTP limit of 4294967296 bytes.
260 23:08:40.966152 end: 1 tftp-deploy (duration 00:00:20) [common]
261 23:08:40.966258 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 23:08:40.966347 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 23:08:40.966468 substitutions:
264 23:08:40.966534 - {DTB}: 12154449/tftp-deploy-dwu5w1iq/dtb/mt8192-asurada-spherion-r0.dtb
265 23:08:40.966598 - {INITRD}: 12154449/tftp-deploy-dwu5w1iq/ramdisk/ramdisk.cpio.gz
266 23:08:40.966658 - {KERNEL}: 12154449/tftp-deploy-dwu5w1iq/kernel/Image
267 23:08:40.966715 - {LAVA_MAC}: None
268 23:08:40.966772 - {PRESEED_CONFIG}: None
269 23:08:40.966827 - {PRESEED_LOCAL}: None
270 23:08:40.966883 - {RAMDISK}: 12154449/tftp-deploy-dwu5w1iq/ramdisk/ramdisk.cpio.gz
271 23:08:40.966938 - {ROOT_PART}: None
272 23:08:40.966993 - {ROOT}: None
273 23:08:40.967047 - {SERVER_IP}: 192.168.201.1
274 23:08:40.967101 - {TEE}: None
275 23:08:40.967155 Parsed boot commands:
276 23:08:40.967208 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 23:08:40.967389 Parsed boot commands: tftpboot 192.168.201.1 12154449/tftp-deploy-dwu5w1iq/kernel/image.itb 12154449/tftp-deploy-dwu5w1iq/kernel/cmdline
278 23:08:40.967477 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 23:08:40.967567 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 23:08:40.967661 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 23:08:40.967746 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 23:08:40.967819 Not connected, no need to disconnect.
283 23:08:40.967892 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 23:08:40.967971 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 23:08:40.968038 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
286 23:08:40.972093 Setting prompt string to ['lava-test: # ']
287 23:08:40.972441 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 23:08:40.972618 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 23:08:40.972718 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 23:08:40.972829 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 23:08:40.973109 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=reboot'
292 23:08:46.122059 >> Command sent successfully.
293 23:08:46.133681 Returned 0 in 5 seconds
294 23:08:46.234957 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 23:08:46.236620 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 23:08:46.237171 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 23:08:46.237646 Setting prompt string to 'Starting depthcharge on Spherion...'
299 23:08:46.238081 Changing prompt to 'Starting depthcharge on Spherion...'
300 23:08:46.238477 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 23:08:46.239882 [Enter `^Ec?' for help]
302 23:08:46.403696
303 23:08:46.404290
304 23:08:46.404734 F0: 102B 0000
305 23:08:46.405171
306 23:08:46.405531 F3: 1001 0000 [0200]
307 23:08:46.405871
308 23:08:46.406739 F3: 1001 0000
309 23:08:46.407223
310 23:08:46.407795 F7: 102D 0000
311 23:08:46.408228
312 23:08:46.410373 F1: 0000 0000
313 23:08:46.410852
314 23:08:46.411244 V0: 0000 0000 [0001]
315 23:08:46.411599
316 23:08:46.411935 00: 0007 8000
317 23:08:46.412291
318 23:08:46.414033 01: 0000 0000
319 23:08:46.414521
320 23:08:46.414920 BP: 0C00 0209 [0000]
321 23:08:46.415271
322 23:08:46.418194 G0: 1182 0000
323 23:08:46.418781
324 23:08:46.419166 EC: 0000 0021 [4000]
325 23:08:46.419520
326 23:08:46.422126 S7: 0000 0000 [0000]
327 23:08:46.422604
328 23:08:46.422983 CC: 0000 0000 [0001]
329 23:08:46.423339
330 23:08:46.425703 T0: 0000 0040 [010F]
331 23:08:46.426295
332 23:08:46.426684 Jump to BL
333 23:08:46.427042
334 23:08:46.450161
335 23:08:46.450752
336 23:08:46.451166
337 23:08:46.457612 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 23:08:46.461141 ARM64: Exception handlers installed.
339 23:08:46.465157 ARM64: Testing exception
340 23:08:46.468744 ARM64: Done test exception
341 23:08:46.475835 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 23:08:46.482769 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 23:08:46.490062 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 23:08:46.501485 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 23:08:46.507358 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 23:08:46.517915 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 23:08:46.528305 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 23:08:46.535331 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 23:08:46.553171 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 23:08:46.556467 WDT: Last reset was cold boot
351 23:08:46.559797 SPI1(PAD0) initialized at 2873684 Hz
352 23:08:46.563350 SPI5(PAD0) initialized at 992727 Hz
353 23:08:46.566575 VBOOT: Loading verstage.
354 23:08:46.572989 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 23:08:46.576048 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 23:08:46.580167 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 23:08:46.583016 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 23:08:46.590432 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 23:08:46.597224 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 23:08:46.608243 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 23:08:46.608882
362 23:08:46.609271
363 23:08:46.618325 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 23:08:46.621304 ARM64: Exception handlers installed.
365 23:08:46.624616 ARM64: Testing exception
366 23:08:46.625373 ARM64: Done test exception
367 23:08:46.631457 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 23:08:46.634744 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 23:08:46.649371 Probing TPM: . done!
370 23:08:46.649943 TPM ready after 0 ms
371 23:08:46.656608 Connected to device vid:did:rid of 1ae0:0028:00
372 23:08:46.663290 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
373 23:08:46.713467 Initialized TPM device CR50 revision 0
374 23:08:46.726373 tlcl_send_startup: Startup return code is 0
375 23:08:46.726947 TPM: setup succeeded
376 23:08:46.737439 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 23:08:46.746299 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 23:08:46.756055 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 23:08:46.765056 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 23:08:46.768145 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 23:08:46.771712 in-header: 03 07 00 00 08 00 00 00
382 23:08:46.774476 in-data: aa e4 47 04 13 02 00 00
383 23:08:46.777906 Chrome EC: UHEPI supported
384 23:08:46.784746 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 23:08:46.788837 in-header: 03 95 00 00 08 00 00 00
386 23:08:46.791860 in-data: 18 20 20 08 00 00 00 00
387 23:08:46.792337 Phase 1
388 23:08:46.795480 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 23:08:46.802640 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 23:08:46.806086 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 23:08:46.810203 Recovery requested (1009000e)
392 23:08:46.819738 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 23:08:46.825149 tlcl_extend: response is 0
394 23:08:46.833979 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 23:08:46.839869 tlcl_extend: response is 0
396 23:08:46.847067 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 23:08:46.867121 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
398 23:08:46.874255 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 23:08:46.875335
400 23:08:46.875735
401 23:08:46.885217 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 23:08:46.885796 ARM64: Exception handlers installed.
403 23:08:46.889015 ARM64: Testing exception
404 23:08:46.892381 ARM64: Done test exception
405 23:08:46.912418 pmic_efuse_setting: Set efuses in 11 msecs
406 23:08:46.915931 pmwrap_interface_init: Select PMIF_VLD_RDY
407 23:08:46.922120 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 23:08:46.925779 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 23:08:46.932294 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 23:08:46.935566 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 23:08:46.942047 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 23:08:46.945580 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 23:08:46.949109 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 23:08:46.955700 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 23:08:46.958809 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 23:08:46.965514 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 23:08:46.969092 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 23:08:46.972416 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 23:08:46.979230 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 23:08:46.985480 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 23:08:46.989495 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 23:08:46.996901 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 23:08:47.000975 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 23:08:47.007867 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 23:08:47.011537 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 23:08:47.019033 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 23:08:47.025805 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 23:08:47.029569 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 23:08:47.037083 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 23:08:47.040677 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 23:08:47.044327 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 23:08:47.051998 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 23:08:47.055486 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 23:08:47.062792 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 23:08:47.066847 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 23:08:47.070304 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 23:08:47.077560 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 23:08:47.081092 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 23:08:47.085264 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 23:08:47.091854 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 23:08:47.095356 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 23:08:47.102578 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 23:08:47.106496 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 23:08:47.109672 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 23:08:47.117101 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 23:08:47.121060 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 23:08:47.124353 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 23:08:47.127990 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 23:08:47.131465 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 23:08:47.139090 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 23:08:47.142626 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 23:08:47.146167 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 23:08:47.149546 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 23:08:47.153180 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 23:08:47.161067 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 23:08:47.164101 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 23:08:47.167933 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 23:08:47.175089 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 23:08:47.182216 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 23:08:47.189306 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 23:08:47.196583 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 23:08:47.204272 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 23:08:47.211528 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 23:08:47.215026 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 23:08:47.218230 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 23:08:47.225535 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
467 23:08:47.229466 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 23:08:47.237238 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 23:08:47.240574 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 23:08:47.250136 [RTC]rtc_get_frequency_meter,154: input=15, output=765
471 23:08:47.259524 [RTC]rtc_get_frequency_meter,154: input=23, output=949
472 23:08:47.268650 [RTC]rtc_get_frequency_meter,154: input=19, output=856
473 23:08:47.278688 [RTC]rtc_get_frequency_meter,154: input=17, output=810
474 23:08:47.287873 [RTC]rtc_get_frequency_meter,154: input=16, output=787
475 23:08:47.297469 [RTC]rtc_get_frequency_meter,154: input=16, output=788
476 23:08:47.307119 [RTC]rtc_get_frequency_meter,154: input=17, output=810
477 23:08:47.310389 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
478 23:08:47.317459 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
479 23:08:47.321188 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 23:08:47.324683 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 23:08:47.328357 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 23:08:47.332138 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 23:08:47.335800 ADC[4]: Raw value=670800 ID=5
484 23:08:47.339565 ADC[3]: Raw value=212549 ID=1
485 23:08:47.340153 RAM Code: 0x51
486 23:08:47.343347 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 23:08:47.350169 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 23:08:47.357386 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
489 23:08:47.364694 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
490 23:08:47.368347 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 23:08:47.371511 in-header: 03 07 00 00 08 00 00 00
492 23:08:47.375159 in-data: aa e4 47 04 13 02 00 00
493 23:08:47.375638 Chrome EC: UHEPI supported
494 23:08:47.382464 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 23:08:47.385687 in-header: 03 95 00 00 08 00 00 00
496 23:08:47.389430 in-data: 18 20 20 08 00 00 00 00
497 23:08:47.392652 MRC: failed to locate region type 0.
498 23:08:47.400250 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 23:08:47.403813 DRAM-K: Running full calibration
500 23:08:47.407843 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
501 23:08:47.411375 header.status = 0x0
502 23:08:47.415090 header.version = 0x6 (expected: 0x6)
503 23:08:47.418609 header.size = 0xd00 (expected: 0xd00)
504 23:08:47.419174 header.flags = 0x0
505 23:08:47.425911 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 23:08:47.443199 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
507 23:08:47.450445 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 23:08:47.454575 dram_init: ddr_geometry: 0
509 23:08:47.455142 [EMI] MDL number = 0
510 23:08:47.457847 [EMI] Get MDL freq = 0
511 23:08:47.458357 dram_init: ddr_type: 0
512 23:08:47.461319 is_discrete_lpddr4: 1
513 23:08:47.465037 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 23:08:47.465708
515 23:08:47.466096
516 23:08:47.468456 [Bian_co] ETT version 0.0.0.1
517 23:08:47.472091 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
518 23:08:47.472820
519 23:08:47.475991 dramc_set_vcore_voltage set vcore to 650000
520 23:08:47.479444 Read voltage for 800, 4
521 23:08:47.479991 Vio18 = 0
522 23:08:47.480385 Vcore = 650000
523 23:08:47.480804 Vdram = 0
524 23:08:47.483006 Vddq = 0
525 23:08:47.483481 Vmddr = 0
526 23:08:47.486395 dram_init: config_dvfs: 1
527 23:08:47.490205 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 23:08:47.493854 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 23:08:47.497275 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
530 23:08:47.504445 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
531 23:08:47.508826 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
532 23:08:47.511837 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
533 23:08:47.512412 MEM_TYPE=3, freq_sel=18
534 23:08:47.515739 sv_algorithm_assistance_LP4_1600
535 23:08:47.519455 ============ PULL DRAM RESETB DOWN ============
536 23:08:47.523215 ========== PULL DRAM RESETB DOWN end =========
537 23:08:47.530235 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 23:08:47.530804 ===================================
539 23:08:47.533812 LPDDR4 DRAM CONFIGURATION
540 23:08:47.537661 ===================================
541 23:08:47.540820 EX_ROW_EN[0] = 0x0
542 23:08:47.541370 EX_ROW_EN[1] = 0x0
543 23:08:47.544632 LP4Y_EN = 0x0
544 23:08:47.545111 WORK_FSP = 0x0
545 23:08:47.548434 WL = 0x2
546 23:08:47.549082 RL = 0x2
547 23:08:47.549598 BL = 0x2
548 23:08:47.552475 RPST = 0x0
549 23:08:47.553083 RD_PRE = 0x0
550 23:08:47.555818 WR_PRE = 0x1
551 23:08:47.556392 WR_PST = 0x0
552 23:08:47.559481 DBI_WR = 0x0
553 23:08:47.559987 DBI_RD = 0x0
554 23:08:47.563153 OTF = 0x1
555 23:08:47.566929 ===================================
556 23:08:47.570483 ===================================
557 23:08:47.571091 ANA top config
558 23:08:47.574175 ===================================
559 23:08:47.577878 DLL_ASYNC_EN = 0
560 23:08:47.578481 ALL_SLAVE_EN = 1
561 23:08:47.581100 NEW_RANK_MODE = 1
562 23:08:47.584390 DLL_IDLE_MODE = 1
563 23:08:47.587779 LP45_APHY_COMB_EN = 1
564 23:08:47.588253 TX_ODT_DIS = 1
565 23:08:47.591140 NEW_8X_MODE = 1
566 23:08:47.594573 ===================================
567 23:08:47.597511 ===================================
568 23:08:47.601644 data_rate = 1600
569 23:08:47.604848 CKR = 1
570 23:08:47.605384 DQ_P2S_RATIO = 8
571 23:08:47.608630 ===================================
572 23:08:47.612881 CA_P2S_RATIO = 8
573 23:08:47.616448 DQ_CA_OPEN = 0
574 23:08:47.620075 DQ_SEMI_OPEN = 0
575 23:08:47.620849 CA_SEMI_OPEN = 0
576 23:08:47.623245 CA_FULL_RATE = 0
577 23:08:47.626533 DQ_CKDIV4_EN = 1
578 23:08:47.630074 CA_CKDIV4_EN = 1
579 23:08:47.633134 CA_PREDIV_EN = 0
580 23:08:47.633615 PH8_DLY = 0
581 23:08:47.636577 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 23:08:47.639779 DQ_AAMCK_DIV = 4
583 23:08:47.643198 CA_AAMCK_DIV = 4
584 23:08:47.646905 CA_ADMCK_DIV = 4
585 23:08:47.650573 DQ_TRACK_CA_EN = 0
586 23:08:47.651142 CA_PICK = 800
587 23:08:47.654094 CA_MCKIO = 800
588 23:08:47.657714 MCKIO_SEMI = 0
589 23:08:47.661470 PLL_FREQ = 3068
590 23:08:47.662057 DQ_UI_PI_RATIO = 32
591 23:08:47.664441 CA_UI_PI_RATIO = 0
592 23:08:47.668210 ===================================
593 23:08:47.671776 ===================================
594 23:08:47.675398 memory_type:LPDDR4
595 23:08:47.676038 GP_NUM : 10
596 23:08:47.678704 SRAM_EN : 1
597 23:08:47.682542 MD32_EN : 0
598 23:08:47.683025 ===================================
599 23:08:47.685992 [ANA_INIT] >>>>>>>>>>>>>>
600 23:08:47.689719 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 23:08:47.693208 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 23:08:47.696755 ===================================
603 23:08:47.700741 data_rate = 1600,PCW = 0X7600
604 23:08:47.701310 ===================================
605 23:08:47.703859 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 23:08:47.711156 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 23:08:47.717637 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 23:08:47.721198 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 23:08:47.724592 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 23:08:47.728021 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 23:08:47.731453 [ANA_INIT] flow start
612 23:08:47.732021 [ANA_INIT] PLL >>>>>>>>
613 23:08:47.734469 [ANA_INIT] PLL <<<<<<<<
614 23:08:47.737888 [ANA_INIT] MIDPI >>>>>>>>
615 23:08:47.738472 [ANA_INIT] MIDPI <<<<<<<<
616 23:08:47.741190 [ANA_INIT] DLL >>>>>>>>
617 23:08:47.744639 [ANA_INIT] flow end
618 23:08:47.748221 ============ LP4 DIFF to SE enter ============
619 23:08:47.751153 ============ LP4 DIFF to SE exit ============
620 23:08:47.754728 [ANA_INIT] <<<<<<<<<<<<<
621 23:08:47.758101 [Flow] Enable top DCM control >>>>>
622 23:08:47.761072 [Flow] Enable top DCM control <<<<<
623 23:08:47.764378 Enable DLL master slave shuffle
624 23:08:47.767826 ==============================================================
625 23:08:47.771492 Gating Mode config
626 23:08:47.778130 ==============================================================
627 23:08:47.778701 Config description:
628 23:08:47.787966 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 23:08:47.795176 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 23:08:47.797960 SELPH_MODE 0: By rank 1: By Phase
631 23:08:47.804842 ==============================================================
632 23:08:47.807858 GAT_TRACK_EN = 1
633 23:08:47.811487 RX_GATING_MODE = 2
634 23:08:47.814486 RX_GATING_TRACK_MODE = 2
635 23:08:47.817674 SELPH_MODE = 1
636 23:08:47.821415 PICG_EARLY_EN = 1
637 23:08:47.824372 VALID_LAT_VALUE = 1
638 23:08:47.827884 ==============================================================
639 23:08:47.830856 Enter into Gating configuration >>>>
640 23:08:47.834270 Exit from Gating configuration <<<<
641 23:08:47.837724 Enter into DVFS_PRE_config >>>>>
642 23:08:47.851127 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 23:08:47.851742 Exit from DVFS_PRE_config <<<<<
644 23:08:47.854186 Enter into PICG configuration >>>>
645 23:08:47.857494 Exit from PICG configuration <<<<
646 23:08:47.860640 [RX_INPUT] configuration >>>>>
647 23:08:47.864767 [RX_INPUT] configuration <<<<<
648 23:08:47.871323 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 23:08:47.874460 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 23:08:47.881135 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 23:08:47.887702 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 23:08:47.894228 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 23:08:47.900892 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 23:08:47.904430 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 23:08:47.907497 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 23:08:47.910873 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 23:08:47.917199 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 23:08:47.920950 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 23:08:47.924138 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 23:08:47.927459 ===================================
661 23:08:47.930981 LPDDR4 DRAM CONFIGURATION
662 23:08:47.934216 ===================================
663 23:08:47.934792 EX_ROW_EN[0] = 0x0
664 23:08:47.937374 EX_ROW_EN[1] = 0x0
665 23:08:47.941112 LP4Y_EN = 0x0
666 23:08:47.941686 WORK_FSP = 0x0
667 23:08:47.944188 WL = 0x2
668 23:08:47.944847 RL = 0x2
669 23:08:47.947300 BL = 0x2
670 23:08:47.947873 RPST = 0x0
671 23:08:47.951047 RD_PRE = 0x0
672 23:08:47.951628 WR_PRE = 0x1
673 23:08:47.954536 WR_PST = 0x0
674 23:08:47.955106 DBI_WR = 0x0
675 23:08:47.957330 DBI_RD = 0x0
676 23:08:47.957807 OTF = 0x1
677 23:08:47.960585 ===================================
678 23:08:47.964391 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 23:08:47.971145 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 23:08:47.974194 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 23:08:47.977483 ===================================
682 23:08:47.980986 LPDDR4 DRAM CONFIGURATION
683 23:08:47.983914 ===================================
684 23:08:47.984396 EX_ROW_EN[0] = 0x10
685 23:08:47.987351 EX_ROW_EN[1] = 0x0
686 23:08:47.987829 LP4Y_EN = 0x0
687 23:08:47.990874 WORK_FSP = 0x0
688 23:08:47.991390 WL = 0x2
689 23:08:47.994279 RL = 0x2
690 23:08:47.994752 BL = 0x2
691 23:08:47.997343 RPST = 0x0
692 23:08:47.997813 RD_PRE = 0x0
693 23:08:48.000768 WR_PRE = 0x1
694 23:08:48.004232 WR_PST = 0x0
695 23:08:48.004840 DBI_WR = 0x0
696 23:08:48.007655 DBI_RD = 0x0
697 23:08:48.008224 OTF = 0x1
698 23:08:48.010798 ===================================
699 23:08:48.017401 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 23:08:48.021124 nWR fixed to 40
701 23:08:48.024500 [ModeRegInit_LP4] CH0 RK0
702 23:08:48.025101 [ModeRegInit_LP4] CH0 RK1
703 23:08:48.027557 [ModeRegInit_LP4] CH1 RK0
704 23:08:48.030987 [ModeRegInit_LP4] CH1 RK1
705 23:08:48.031562 match AC timing 12
706 23:08:48.037681 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
707 23:08:48.041248 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 23:08:48.044435 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 23:08:48.051058 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 23:08:48.054615 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 23:08:48.055184 [EMI DOE] emi_dcm 0
712 23:08:48.060912 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 23:08:48.061486 ==
714 23:08:48.064096 Dram Type= 6, Freq= 0, CH_0, rank 0
715 23:08:48.067829 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
716 23:08:48.068405 ==
717 23:08:48.074256 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 23:08:48.081001 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 23:08:48.088039 [CA 0] Center 37 (7~68) winsize 62
720 23:08:48.091316 [CA 1] Center 37 (6~68) winsize 63
721 23:08:48.094520 [CA 2] Center 35 (5~66) winsize 62
722 23:08:48.098353 [CA 3] Center 35 (5~66) winsize 62
723 23:08:48.101234 [CA 4] Center 34 (3~65) winsize 63
724 23:08:48.104976 [CA 5] Center 33 (3~64) winsize 62
725 23:08:48.105546
726 23:08:48.108466 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 23:08:48.109089
728 23:08:48.111836 [CATrainingPosCal] consider 1 rank data
729 23:08:48.115118 u2DelayCellTimex100 = 270/100 ps
730 23:08:48.118723 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
731 23:08:48.121644 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
732 23:08:48.128763 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
733 23:08:48.131838 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
734 23:08:48.135146 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
735 23:08:48.138280 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
736 23:08:48.138855
737 23:08:48.141484 CA PerBit enable=1, Macro0, CA PI delay=33
738 23:08:48.142058
739 23:08:48.144830 [CBTSetCACLKResult] CA Dly = 33
740 23:08:48.145350 CS Dly: 6 (0~37)
741 23:08:48.148147 ==
742 23:08:48.151708 Dram Type= 6, Freq= 0, CH_0, rank 1
743 23:08:48.154965 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
744 23:08:48.155541 ==
745 23:08:48.158223 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 23:08:48.165072 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 23:08:48.174399 [CA 0] Center 37 (7~68) winsize 62
748 23:08:48.177435 [CA 1] Center 37 (6~68) winsize 63
749 23:08:48.180897 [CA 2] Center 35 (4~66) winsize 63
750 23:08:48.184099 [CA 3] Center 35 (4~66) winsize 63
751 23:08:48.187664 [CA 4] Center 33 (3~64) winsize 62
752 23:08:48.190928 [CA 5] Center 33 (3~64) winsize 62
753 23:08:48.191514
754 23:08:48.194019 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 23:08:48.194498
756 23:08:48.197581 [CATrainingPosCal] consider 2 rank data
757 23:08:48.200701 u2DelayCellTimex100 = 270/100 ps
758 23:08:48.204387 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
759 23:08:48.207517 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
760 23:08:48.214257 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
761 23:08:48.217527 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
762 23:08:48.220696 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
763 23:08:48.224437 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
764 23:08:48.225054
765 23:08:48.227385 CA PerBit enable=1, Macro0, CA PI delay=33
766 23:08:48.227862
767 23:08:48.230706 [CBTSetCACLKResult] CA Dly = 33
768 23:08:48.231185 CS Dly: 6 (0~37)
769 23:08:48.231564
770 23:08:48.234045 ----->DramcWriteLeveling(PI) begin...
771 23:08:48.237158 ==
772 23:08:48.240829 Dram Type= 6, Freq= 0, CH_0, rank 0
773 23:08:48.243831 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
774 23:08:48.244398 ==
775 23:08:48.247472 Write leveling (Byte 0): 30 => 30
776 23:08:48.250819 Write leveling (Byte 1): 26 => 26
777 23:08:48.255082 DramcWriteLeveling(PI) end<-----
778 23:08:48.255646
779 23:08:48.256023 ==
780 23:08:48.258307 Dram Type= 6, Freq= 0, CH_0, rank 0
781 23:08:48.261832 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
782 23:08:48.262423 ==
783 23:08:48.265566 [Gating] SW mode calibration
784 23:08:48.269002 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 23:08:48.276117 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 23:08:48.279214 0 6 0 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
787 23:08:48.285933 0 6 4 | B1->B0 | 2c2c 2424 | 0 0 | (0 0) (0 0)
788 23:08:48.289218 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 23:08:48.292726 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 23:08:48.299702 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 23:08:48.302797 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 23:08:48.305883 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 23:08:48.309223 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 23:08:48.315961 0 7 0 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
795 23:08:48.319382 0 7 4 | B1->B0 | 3838 3f3f | 0 0 | (0 0) (0 0)
796 23:08:48.322676 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
797 23:08:48.329272 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
798 23:08:48.332784 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
799 23:08:48.336035 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
800 23:08:48.342827 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
801 23:08:48.345956 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
802 23:08:48.349337 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
803 23:08:48.355893 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
804 23:08:48.359288 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
805 23:08:48.362494 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
806 23:08:48.369358 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
807 23:08:48.372837 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
808 23:08:48.376054 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
809 23:08:48.382513 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
810 23:08:48.385732 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
811 23:08:48.389219 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
812 23:08:48.395620 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
813 23:08:48.398985 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
814 23:08:48.402379 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
815 23:08:48.409065 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
816 23:08:48.412481 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
817 23:08:48.415569 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
818 23:08:48.422355 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
819 23:08:48.425618 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
820 23:08:48.429059 Total UI for P1: 0, mck2ui 16
821 23:08:48.432330 best dqsien dly found for B0: ( 0, 10, 0)
822 23:08:48.435497 Total UI for P1: 0, mck2ui 16
823 23:08:48.438787 best dqsien dly found for B1: ( 0, 10, 0)
824 23:08:48.442263 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
825 23:08:48.445474 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
826 23:08:48.445953
827 23:08:48.448788 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
828 23:08:48.452330 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
829 23:08:48.455551 [Gating] SW calibration Done
830 23:08:48.456132 ==
831 23:08:48.459072 Dram Type= 6, Freq= 0, CH_0, rank 0
832 23:08:48.462279 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
833 23:08:48.462870 ==
834 23:08:48.465469 RX Vref Scan: 0
835 23:08:48.466053
836 23:08:48.468889 RX Vref 0 -> 0, step: 1
837 23:08:48.469475
838 23:08:48.469860 RX Delay -130 -> 252, step: 16
839 23:08:48.475566 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
840 23:08:48.479193 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
841 23:08:48.482157 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
842 23:08:48.485235 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
843 23:08:48.488354 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
844 23:08:48.495377 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
845 23:08:48.498708 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
846 23:08:48.502220 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
847 23:08:48.505113 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
848 23:08:48.509036 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
849 23:08:48.515369 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
850 23:08:48.518634 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
851 23:08:48.521764 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
852 23:08:48.525394 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
853 23:08:48.528433 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
854 23:08:48.535228 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
855 23:08:48.535801 ==
856 23:08:48.538687 Dram Type= 6, Freq= 0, CH_0, rank 0
857 23:08:48.541947 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
858 23:08:48.542432 ==
859 23:08:48.542857 DQS Delay:
860 23:08:48.545347 DQS0 = 0, DQS1 = 0
861 23:08:48.545828 DQM Delay:
862 23:08:48.548803 DQM0 = 84, DQM1 = 75
863 23:08:48.549375 DQ Delay:
864 23:08:48.552255 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77
865 23:08:48.555650 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
866 23:08:48.558773 DQ8 =69, DQ9 =53, DQ10 =69, DQ11 =69
867 23:08:48.562019 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
868 23:08:48.562605
869 23:08:48.563110
870 23:08:48.563580 ==
871 23:08:48.565125 Dram Type= 6, Freq= 0, CH_0, rank 0
872 23:08:48.568875 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
873 23:08:48.569467 ==
874 23:08:48.571960
875 23:08:48.572562
876 23:08:48.573063 TX Vref Scan disable
877 23:08:48.574991 == TX Byte 0 ==
878 23:08:48.578726 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
879 23:08:48.581830 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
880 23:08:48.585043 == TX Byte 1 ==
881 23:08:48.588220 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
882 23:08:48.591573 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
883 23:08:48.592063 ==
884 23:08:48.595210 Dram Type= 6, Freq= 0, CH_0, rank 0
885 23:08:48.601915 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
886 23:08:48.602508 ==
887 23:08:48.614401 TX Vref=22, minBit 2, minWin=27, winSum=438
888 23:08:48.617463 TX Vref=24, minBit 0, minWin=27, winSum=441
889 23:08:48.620834 TX Vref=26, minBit 3, minWin=27, winSum=447
890 23:08:48.624173 TX Vref=28, minBit 2, minWin=28, winSum=454
891 23:08:48.627463 TX Vref=30, minBit 0, minWin=28, winSum=456
892 23:08:48.631099 TX Vref=32, minBit 5, minWin=27, winSum=447
893 23:08:48.637813 [TxChooseVref] Worse bit 0, Min win 28, Win sum 456, Final Vref 30
894 23:08:48.638402
895 23:08:48.640847 Final TX Range 1 Vref 30
896 23:08:48.641339
897 23:08:48.641835 ==
898 23:08:48.644018 Dram Type= 6, Freq= 0, CH_0, rank 0
899 23:08:48.648257 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
900 23:08:48.648912 ==
901 23:08:48.649422
902 23:08:48.649892
903 23:08:48.651318 TX Vref Scan disable
904 23:08:48.654660 == TX Byte 0 ==
905 23:08:48.658635 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
906 23:08:48.661778 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
907 23:08:48.664744 == TX Byte 1 ==
908 23:08:48.668379 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
909 23:08:48.671576 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
910 23:08:48.672164
911 23:08:48.675147 [DATLAT]
912 23:08:48.675730 Freq=800, CH0 RK0
913 23:08:48.676232
914 23:08:48.678594 DATLAT Default: 0xa
915 23:08:48.679181 0, 0xFFFF, sum = 0
916 23:08:48.681691 1, 0xFFFF, sum = 0
917 23:08:48.682301 2, 0xFFFF, sum = 0
918 23:08:48.685126 3, 0xFFFF, sum = 0
919 23:08:48.685620 4, 0xFFFF, sum = 0
920 23:08:48.688019 5, 0xFFFF, sum = 0
921 23:08:48.688553 6, 0xFFFF, sum = 0
922 23:08:48.691601 7, 0xFFFF, sum = 0
923 23:08:48.692199 8, 0x0, sum = 1
924 23:08:48.694796 9, 0x0, sum = 2
925 23:08:48.695296 10, 0x0, sum = 3
926 23:08:48.698418 11, 0x0, sum = 4
927 23:08:48.699016 best_step = 9
928 23:08:48.699519
929 23:08:48.699989 ==
930 23:08:48.701713 Dram Type= 6, Freq= 0, CH_0, rank 0
931 23:08:48.704952 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
932 23:08:48.705543 ==
933 23:08:48.708274 RX Vref Scan: 1
934 23:08:48.708920
935 23:08:48.711512 Set Vref Range= 32 -> 127
936 23:08:48.712091
937 23:08:48.712706 RX Vref 32 -> 127, step: 1
938 23:08:48.713189
939 23:08:48.714496 RX Delay -111 -> 252, step: 8
940 23:08:48.714986
941 23:08:48.718083 Set Vref, RX VrefLevel [Byte0]: 32
942 23:08:48.721437 [Byte1]: 32
943 23:08:48.725348
944 23:08:48.725925 Set Vref, RX VrefLevel [Byte0]: 33
945 23:08:48.728436 [Byte1]: 33
946 23:08:48.732627
947 23:08:48.736215 Set Vref, RX VrefLevel [Byte0]: 34
948 23:08:48.736876 [Byte1]: 34
949 23:08:48.740860
950 23:08:48.741440 Set Vref, RX VrefLevel [Byte0]: 35
951 23:08:48.743629 [Byte1]: 35
952 23:08:48.748343
953 23:08:48.748969 Set Vref, RX VrefLevel [Byte0]: 36
954 23:08:48.751295 [Byte1]: 36
955 23:08:48.755788
956 23:08:48.756375 Set Vref, RX VrefLevel [Byte0]: 37
957 23:08:48.758860 [Byte1]: 37
958 23:08:48.763247
959 23:08:48.763833 Set Vref, RX VrefLevel [Byte0]: 38
960 23:08:48.766638 [Byte1]: 38
961 23:08:48.770721
962 23:08:48.771207 Set Vref, RX VrefLevel [Byte0]: 39
963 23:08:48.774433 [Byte1]: 39
964 23:08:48.778666
965 23:08:48.779258 Set Vref, RX VrefLevel [Byte0]: 40
966 23:08:48.781742 [Byte1]: 40
967 23:08:48.786314
968 23:08:48.787000 Set Vref, RX VrefLevel [Byte0]: 41
969 23:08:48.789279 [Byte1]: 41
970 23:08:48.793678
971 23:08:48.794161 Set Vref, RX VrefLevel [Byte0]: 42
972 23:08:48.797155 [Byte1]: 42
973 23:08:48.801636
974 23:08:48.802213 Set Vref, RX VrefLevel [Byte0]: 43
975 23:08:48.805061 [Byte1]: 43
976 23:08:48.809411
977 23:08:48.809992 Set Vref, RX VrefLevel [Byte0]: 44
978 23:08:48.812562 [Byte1]: 44
979 23:08:48.816864
980 23:08:48.817446 Set Vref, RX VrefLevel [Byte0]: 45
981 23:08:48.820048 [Byte1]: 45
982 23:08:48.824554
983 23:08:48.825145 Set Vref, RX VrefLevel [Byte0]: 46
984 23:08:48.828076 [Byte1]: 46
985 23:08:48.832255
986 23:08:48.832881 Set Vref, RX VrefLevel [Byte0]: 47
987 23:08:48.835358 [Byte1]: 47
988 23:08:48.839817
989 23:08:48.840390 Set Vref, RX VrefLevel [Byte0]: 48
990 23:08:48.843508 [Byte1]: 48
991 23:08:48.847726
992 23:08:48.848330 Set Vref, RX VrefLevel [Byte0]: 49
993 23:08:48.850695 [Byte1]: 49
994 23:08:48.855239
995 23:08:48.855841 Set Vref, RX VrefLevel [Byte0]: 50
996 23:08:48.858283 [Byte1]: 50
997 23:08:48.862725
998 23:08:48.863306 Set Vref, RX VrefLevel [Byte0]: 51
999 23:08:48.866268 [Byte1]: 51
1000 23:08:48.870531
1001 23:08:48.871118 Set Vref, RX VrefLevel [Byte0]: 52
1002 23:08:48.873372 [Byte1]: 52
1003 23:08:48.877989
1004 23:08:48.878578 Set Vref, RX VrefLevel [Byte0]: 53
1005 23:08:48.881143 [Byte1]: 53
1006 23:08:48.885409
1007 23:08:48.885892 Set Vref, RX VrefLevel [Byte0]: 54
1008 23:08:48.888689 [Byte1]: 54
1009 23:08:48.893193
1010 23:08:48.893777 Set Vref, RX VrefLevel [Byte0]: 55
1011 23:08:48.896603 [Byte1]: 55
1012 23:08:48.900962
1013 23:08:48.901450 Set Vref, RX VrefLevel [Byte0]: 56
1014 23:08:48.904002 [Byte1]: 56
1015 23:08:48.908269
1016 23:08:48.908807 Set Vref, RX VrefLevel [Byte0]: 57
1017 23:08:48.911596 [Byte1]: 57
1018 23:08:48.916768
1019 23:08:48.917344 Set Vref, RX VrefLevel [Byte0]: 58
1020 23:08:48.919762 [Byte1]: 58
1021 23:08:48.924037
1022 23:08:48.924641 Set Vref, RX VrefLevel [Byte0]: 59
1023 23:08:48.927737 [Byte1]: 59
1024 23:08:48.931981
1025 23:08:48.932606 Set Vref, RX VrefLevel [Byte0]: 60
1026 23:08:48.935397 [Byte1]: 60
1027 23:08:48.939603
1028 23:08:48.940153 Set Vref, RX VrefLevel [Byte0]: 61
1029 23:08:48.942631 [Byte1]: 61
1030 23:08:48.947567
1031 23:08:48.948145 Set Vref, RX VrefLevel [Byte0]: 62
1032 23:08:48.950721 [Byte1]: 62
1033 23:08:48.954433
1034 23:08:48.955022 Set Vref, RX VrefLevel [Byte0]: 63
1035 23:08:48.958152 [Byte1]: 63
1036 23:08:48.962290
1037 23:08:48.962869 Set Vref, RX VrefLevel [Byte0]: 64
1038 23:08:48.965241 [Byte1]: 64
1039 23:08:48.970126
1040 23:08:48.970697 Set Vref, RX VrefLevel [Byte0]: 65
1041 23:08:48.973123 [Byte1]: 65
1042 23:08:48.977460
1043 23:08:48.978029 Set Vref, RX VrefLevel [Byte0]: 66
1044 23:08:48.980679 [Byte1]: 66
1045 23:08:48.984972
1046 23:08:48.985615 Set Vref, RX VrefLevel [Byte0]: 67
1047 23:08:48.988217 [Byte1]: 67
1048 23:08:48.992567
1049 23:08:48.993187 Set Vref, RX VrefLevel [Byte0]: 68
1050 23:08:48.995698 [Byte1]: 68
1051 23:08:49.000004
1052 23:08:49.000469 Set Vref, RX VrefLevel [Byte0]: 69
1053 23:08:49.003420 [Byte1]: 69
1054 23:08:49.008022
1055 23:08:49.008626 Set Vref, RX VrefLevel [Byte0]: 70
1056 23:08:49.011247 [Byte1]: 70
1057 23:08:49.015602
1058 23:08:49.016157 Set Vref, RX VrefLevel [Byte0]: 71
1059 23:08:49.018996 [Byte1]: 71
1060 23:08:49.023369
1061 23:08:49.023924 Set Vref, RX VrefLevel [Byte0]: 72
1062 23:08:49.026522 [Byte1]: 72
1063 23:08:49.031210
1064 23:08:49.031765 Set Vref, RX VrefLevel [Byte0]: 73
1065 23:08:49.034252 [Byte1]: 73
1066 23:08:49.038830
1067 23:08:49.039386 Set Vref, RX VrefLevel [Byte0]: 74
1068 23:08:49.041793 [Byte1]: 74
1069 23:08:49.046314
1070 23:08:49.046872 Final RX Vref Byte 0 = 53 to rank0
1071 23:08:49.049650 Final RX Vref Byte 1 = 57 to rank0
1072 23:08:49.053020 Final RX Vref Byte 0 = 53 to rank1
1073 23:08:49.056209 Final RX Vref Byte 1 = 57 to rank1==
1074 23:08:49.060124 Dram Type= 6, Freq= 0, CH_0, rank 0
1075 23:08:49.066380 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1076 23:08:49.066940 ==
1077 23:08:49.067320 DQS Delay:
1078 23:08:49.067668 DQS0 = 0, DQS1 = 0
1079 23:08:49.069542 DQM Delay:
1080 23:08:49.070093 DQM0 = 83, DQM1 = 74
1081 23:08:49.072911 DQ Delay:
1082 23:08:49.075997 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1083 23:08:49.076599 DQ4 =88, DQ5 =72, DQ6 =92, DQ7 =92
1084 23:08:49.079690 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1085 23:08:49.086048 DQ12 =84, DQ13 =76, DQ14 =84, DQ15 =84
1086 23:08:49.086599
1087 23:08:49.086971
1088 23:08:49.092646 [DQSOSCAuto] RK0, (LSB)MR18= 0x3030, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 397 ps
1089 23:08:49.095585 CH0 RK0: MR19=606, MR18=3030
1090 23:08:49.102542 CH0_RK0: MR19=0x606, MR18=0x3030, DQSOSC=397, MR23=63, INC=93, DEC=62
1091 23:08:49.103106
1092 23:08:49.106079 ----->DramcWriteLeveling(PI) begin...
1093 23:08:49.106648 ==
1094 23:08:49.109142 Dram Type= 6, Freq= 0, CH_0, rank 1
1095 23:08:49.112897 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1096 23:08:49.113461 ==
1097 23:08:49.116171 Write leveling (Byte 0): 29 => 29
1098 23:08:49.119562 Write leveling (Byte 1): 26 => 26
1099 23:08:49.122544 DramcWriteLeveling(PI) end<-----
1100 23:08:49.123106
1101 23:08:49.123478 ==
1102 23:08:49.125811 Dram Type= 6, Freq= 0, CH_0, rank 1
1103 23:08:49.128956 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1104 23:08:49.129429 ==
1105 23:08:49.132305 [Gating] SW mode calibration
1106 23:08:49.139279 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1107 23:08:49.145803 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1108 23:08:49.149239 0 6 0 | B1->B0 | 3333 3333 | 0 0 | (0 1) (0 1)
1109 23:08:49.152740 0 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1110 23:08:49.159387 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1111 23:08:49.162768 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1112 23:08:49.165666 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1113 23:08:49.172851 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1114 23:08:49.175777 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1115 23:08:49.178986 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1116 23:08:49.185623 0 7 0 | B1->B0 | 2f2f 3333 | 0 1 | (0 0) (1 1)
1117 23:08:49.188741 0 7 4 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
1118 23:08:49.192435 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1119 23:08:49.198955 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1120 23:08:49.202483 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1121 23:08:49.205827 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1122 23:08:49.212581 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1123 23:08:49.215710 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1124 23:08:49.219094 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1125 23:08:49.225737 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1126 23:08:49.228910 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1127 23:08:49.232282 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1128 23:08:49.239138 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1129 23:08:49.242183 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1130 23:08:49.245853 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1131 23:08:49.248769 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1132 23:08:49.255648 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1133 23:08:49.258949 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1134 23:08:49.262450 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1135 23:08:49.268974 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1136 23:08:49.272163 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1137 23:08:49.275674 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1138 23:08:49.282595 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1139 23:08:49.285606 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1140 23:08:49.288694 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1141 23:08:49.295203 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1142 23:08:49.298496 0 10 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1143 23:08:49.302573 Total UI for P1: 0, mck2ui 16
1144 23:08:49.305735 best dqsien dly found for B0: ( 0, 10, 2)
1145 23:08:49.308751 Total UI for P1: 0, mck2ui 16
1146 23:08:49.312277 best dqsien dly found for B1: ( 0, 10, 2)
1147 23:08:49.315491 best DQS0 dly(MCK, UI, PI) = (0, 10, 2)
1148 23:08:49.319116 best DQS1 dly(MCK, UI, PI) = (0, 10, 2)
1149 23:08:49.319678
1150 23:08:49.322514 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 2)
1151 23:08:49.325800 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 2)
1152 23:08:49.328607 [Gating] SW calibration Done
1153 23:08:49.329077 ==
1154 23:08:49.372950 Dram Type= 6, Freq= 0, CH_0, rank 1
1155 23:08:49.373507 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1156 23:08:49.373885 ==
1157 23:08:49.374233 RX Vref Scan: 0
1158 23:08:49.374559
1159 23:08:49.374880 RX Vref 0 -> 0, step: 1
1160 23:08:49.375195
1161 23:08:49.375502 RX Delay -130 -> 252, step: 16
1162 23:08:49.376188 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1163 23:08:49.376572 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1164 23:08:49.376898 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1165 23:08:49.377206 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1166 23:08:49.377510 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1167 23:08:49.377812 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1168 23:08:49.378115 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1169 23:08:49.413169 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1170 23:08:49.413754 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1171 23:08:49.414178 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1172 23:08:49.415160 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1173 23:08:49.415577 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1174 23:08:49.415929 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1175 23:08:49.416261 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1176 23:08:49.416641 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1177 23:08:49.416975 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1178 23:08:49.417323 ==
1179 23:08:49.417652 Dram Type= 6, Freq= 0, CH_0, rank 1
1180 23:08:49.418031 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1181 23:08:49.418362 ==
1182 23:08:49.418670 DQS Delay:
1183 23:08:49.420872 DQS0 = 0, DQS1 = 0
1184 23:08:49.421366 DQM Delay:
1185 23:08:49.421742 DQM0 = 83, DQM1 = 72
1186 23:08:49.423883 DQ Delay:
1187 23:08:49.427538 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =69
1188 23:08:49.430841 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =101
1189 23:08:49.434291 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
1190 23:08:49.437662 DQ12 =85, DQ13 =77, DQ14 =85, DQ15 =77
1191 23:08:49.438216
1192 23:08:49.438585
1193 23:08:49.438922 ==
1194 23:08:49.440529 Dram Type= 6, Freq= 0, CH_0, rank 1
1195 23:08:49.444032 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1196 23:08:49.444638 ==
1197 23:08:49.445018
1198 23:08:49.445370
1199 23:08:49.447423 TX Vref Scan disable
1200 23:08:49.447974 == TX Byte 0 ==
1201 23:08:49.454396 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1202 23:08:49.457334 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1203 23:08:49.457795 == TX Byte 1 ==
1204 23:08:49.464333 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1205 23:08:49.467558 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1206 23:08:49.468115 ==
1207 23:08:49.470618 Dram Type= 6, Freq= 0, CH_0, rank 1
1208 23:08:49.473855 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1209 23:08:49.474500 ==
1210 23:08:49.488088 TX Vref=22, minBit 0, minWin=27, winSum=441
1211 23:08:49.491444 TX Vref=24, minBit 0, minWin=27, winSum=445
1212 23:08:49.495049 TX Vref=26, minBit 0, minWin=27, winSum=447
1213 23:08:49.498806 TX Vref=28, minBit 14, minWin=27, winSum=455
1214 23:08:49.502122 TX Vref=30, minBit 2, minWin=28, winSum=456
1215 23:08:49.505851 TX Vref=32, minBit 0, minWin=28, winSum=457
1216 23:08:49.513069 [TxChooseVref] Worse bit 0, Min win 28, Win sum 457, Final Vref 32
1217 23:08:49.513639
1218 23:08:49.514006 Final TX Range 1 Vref 32
1219 23:08:49.516176
1220 23:08:49.516806 ==
1221 23:08:49.519376 Dram Type= 6, Freq= 0, CH_0, rank 1
1222 23:08:49.523376 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1223 23:08:49.523941 ==
1224 23:08:49.524311
1225 23:08:49.524678
1226 23:08:49.527200 TX Vref Scan disable
1227 23:08:49.527660 == TX Byte 0 ==
1228 23:08:49.533969 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1229 23:08:49.536801 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1230 23:08:49.537264 == TX Byte 1 ==
1231 23:08:49.543502 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1232 23:08:49.547117 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1233 23:08:49.547681
1234 23:08:49.548049 [DATLAT]
1235 23:08:49.550317 Freq=800, CH0 RK1
1236 23:08:49.550878
1237 23:08:49.551249 DATLAT Default: 0x9
1238 23:08:49.553825 0, 0xFFFF, sum = 0
1239 23:08:49.554406 1, 0xFFFF, sum = 0
1240 23:08:49.556961 2, 0xFFFF, sum = 0
1241 23:08:49.557527 3, 0xFFFF, sum = 0
1242 23:08:49.560492 4, 0xFFFF, sum = 0
1243 23:08:49.561107 5, 0xFFFF, sum = 0
1244 23:08:49.563904 6, 0xFFFF, sum = 0
1245 23:08:49.564471 7, 0xFFFF, sum = 0
1246 23:08:49.567087 8, 0x0, sum = 1
1247 23:08:49.567653 9, 0x0, sum = 2
1248 23:08:49.570253 10, 0x0, sum = 3
1249 23:08:49.570825 11, 0x0, sum = 4
1250 23:08:49.573543 best_step = 9
1251 23:08:49.574104
1252 23:08:49.574546 ==
1253 23:08:49.576970 Dram Type= 6, Freq= 0, CH_0, rank 1
1254 23:08:49.580301 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1255 23:08:49.580911 ==
1256 23:08:49.581285 RX Vref Scan: 0
1257 23:08:49.583368
1258 23:08:49.583823 RX Vref 0 -> 0, step: 1
1259 23:08:49.584189
1260 23:08:49.586615 RX Delay -111 -> 252, step: 8
1261 23:08:49.590354 iDelay=217, Bit 0, Center 80 (-39 ~ 200) 240
1262 23:08:49.596726 iDelay=217, Bit 1, Center 88 (-31 ~ 208) 240
1263 23:08:49.600579 iDelay=217, Bit 2, Center 84 (-39 ~ 208) 248
1264 23:08:49.604165 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1265 23:08:49.607052 iDelay=217, Bit 4, Center 88 (-31 ~ 208) 240
1266 23:08:49.610275 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1267 23:08:49.616900 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1268 23:08:49.620391 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1269 23:08:49.624431 iDelay=217, Bit 8, Center 60 (-55 ~ 176) 232
1270 23:08:49.627055 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1271 23:08:49.630265 iDelay=217, Bit 10, Center 72 (-47 ~ 192) 240
1272 23:08:49.637150 iDelay=217, Bit 11, Center 64 (-47 ~ 176) 224
1273 23:08:49.640695 iDelay=217, Bit 12, Center 80 (-31 ~ 192) 224
1274 23:08:49.643610 iDelay=217, Bit 13, Center 80 (-39 ~ 200) 240
1275 23:08:49.646794 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1276 23:08:49.650339 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1277 23:08:49.653561 ==
1278 23:08:49.657032 Dram Type= 6, Freq= 0, CH_0, rank 1
1279 23:08:49.660727 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1280 23:08:49.661290 ==
1281 23:08:49.661661 DQS Delay:
1282 23:08:49.663874 DQS0 = 0, DQS1 = 0
1283 23:08:49.664436 DQM Delay:
1284 23:08:49.667016 DQM0 = 85, DQM1 = 73
1285 23:08:49.667578 DQ Delay:
1286 23:08:49.670435 DQ0 =80, DQ1 =88, DQ2 =84, DQ3 =80
1287 23:08:49.673737 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1288 23:08:49.677039 DQ8 =60, DQ9 =60, DQ10 =72, DQ11 =64
1289 23:08:49.680268 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =84
1290 23:08:49.680862
1291 23:08:49.681236
1292 23:08:49.686626 [DQSOSCAuto] RK1, (LSB)MR18= 0x4a4a, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
1293 23:08:49.690496 CH0 RK1: MR19=606, MR18=4A4A
1294 23:08:49.696983 CH0_RK1: MR19=0x606, MR18=0x4A4A, DQSOSC=391, MR23=63, INC=96, DEC=64
1295 23:08:49.700130 [RxdqsGatingPostProcess] freq 800
1296 23:08:49.703372 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1297 23:08:49.706710 Pre-setting of DQS Precalculation
1298 23:08:49.713070 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1299 23:08:49.713402 ==
1300 23:08:49.716557 Dram Type= 6, Freq= 0, CH_1, rank 0
1301 23:08:49.719891 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1302 23:08:49.720355 ==
1303 23:08:49.726935 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1304 23:08:49.733390 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1305 23:08:49.741106 [CA 0] Center 37 (6~68) winsize 63
1306 23:08:49.744058 [CA 1] Center 37 (6~68) winsize 63
1307 23:08:49.747630 [CA 2] Center 34 (4~65) winsize 62
1308 23:08:49.751025 [CA 3] Center 34 (4~65) winsize 62
1309 23:08:49.753954 [CA 4] Center 33 (3~64) winsize 62
1310 23:08:49.757611 [CA 5] Center 33 (3~64) winsize 62
1311 23:08:49.758139
1312 23:08:49.760852 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1313 23:08:49.761319
1314 23:08:49.764275 [CATrainingPosCal] consider 1 rank data
1315 23:08:49.767601 u2DelayCellTimex100 = 270/100 ps
1316 23:08:49.770928 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1317 23:08:49.774274 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1318 23:08:49.781176 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1319 23:08:49.784189 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1320 23:08:49.787805 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1321 23:08:49.790544 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1322 23:08:49.791055
1323 23:08:49.794075 CA PerBit enable=1, Macro0, CA PI delay=33
1324 23:08:49.794540
1325 23:08:49.797332 [CBTSetCACLKResult] CA Dly = 33
1326 23:08:49.797797 CS Dly: 4 (0~35)
1327 23:08:49.798169 ==
1328 23:08:49.800580 Dram Type= 6, Freq= 0, CH_1, rank 1
1329 23:08:49.807462 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1330 23:08:49.808052 ==
1331 23:08:49.810595 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1332 23:08:49.817595 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1333 23:08:49.826498 [CA 0] Center 36 (6~67) winsize 62
1334 23:08:49.830174 [CA 1] Center 37 (6~68) winsize 63
1335 23:08:49.833794 [CA 2] Center 34 (4~65) winsize 62
1336 23:08:49.836763 [CA 3] Center 34 (4~65) winsize 62
1337 23:08:49.839969 [CA 4] Center 33 (3~64) winsize 62
1338 23:08:49.843306 [CA 5] Center 33 (3~64) winsize 62
1339 23:08:49.843883
1340 23:08:49.846666 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1341 23:08:49.847129
1342 23:08:49.849667 [CATrainingPosCal] consider 2 rank data
1343 23:08:49.853685 u2DelayCellTimex100 = 270/100 ps
1344 23:08:49.856784 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1345 23:08:49.860174 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1346 23:08:49.866705 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1347 23:08:49.869693 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1348 23:08:49.873382 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1349 23:08:49.876766 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1350 23:08:49.877229
1351 23:08:49.880202 CA PerBit enable=1, Macro0, CA PI delay=33
1352 23:08:49.880792
1353 23:08:49.883469 [CBTSetCACLKResult] CA Dly = 33
1354 23:08:49.884031 CS Dly: 4 (0~36)
1355 23:08:49.884397
1356 23:08:49.886966 ----->DramcWriteLeveling(PI) begin...
1357 23:08:49.890052 ==
1358 23:08:49.890511 Dram Type= 6, Freq= 0, CH_1, rank 0
1359 23:08:49.896468 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1360 23:08:49.897061 ==
1361 23:08:49.900254 Write leveling (Byte 0): 24 => 24
1362 23:08:49.903430 Write leveling (Byte 1): 24 => 24
1363 23:08:49.906711 DramcWriteLeveling(PI) end<-----
1364 23:08:49.907272
1365 23:08:49.907638 ==
1366 23:08:49.909699 Dram Type= 6, Freq= 0, CH_1, rank 0
1367 23:08:49.913318 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1368 23:08:49.913886 ==
1369 23:08:49.916691 [Gating] SW mode calibration
1370 23:08:49.923300 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1371 23:08:49.926441 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1372 23:08:49.933418 0 6 0 | B1->B0 | 2f2f 2424 | 1 0 | (0 0) (0 0)
1373 23:08:49.936914 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1374 23:08:49.939885 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1375 23:08:49.946138 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1376 23:08:49.949874 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1377 23:08:49.953229 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1378 23:08:49.960111 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1379 23:08:49.963105 0 6 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1380 23:08:49.967009 0 7 0 | B1->B0 | 2727 4040 | 0 1 | (0 0) (0 0)
1381 23:08:49.973353 0 7 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1382 23:08:49.976487 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1383 23:08:49.980068 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1384 23:08:49.986689 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1385 23:08:49.989697 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1386 23:08:49.993331 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1387 23:08:50.000079 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1388 23:08:50.003507 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1389 23:08:50.006879 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1390 23:08:50.009755 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1391 23:08:50.016806 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1392 23:08:50.019631 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1393 23:08:50.022942 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1394 23:08:50.030197 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1395 23:08:50.033344 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1396 23:08:50.036681 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1397 23:08:50.043080 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1398 23:08:50.046485 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1399 23:08:50.049762 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1400 23:08:50.056357 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1401 23:08:50.060170 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1402 23:08:50.063168 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1403 23:08:50.069704 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1404 23:08:50.073537 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1405 23:08:50.076575 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1406 23:08:50.079810 Total UI for P1: 0, mck2ui 16
1407 23:08:50.083088 best dqsien dly found for B0: ( 0, 9, 30)
1408 23:08:50.086577 Total UI for P1: 0, mck2ui 16
1409 23:08:50.089703 best dqsien dly found for B1: ( 0, 9, 30)
1410 23:08:50.093307 best DQS0 dly(MCK, UI, PI) = (0, 9, 30)
1411 23:08:50.096471 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1412 23:08:50.096979
1413 23:08:50.100041 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 30)
1414 23:08:50.106632 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1415 23:08:50.107198 [Gating] SW calibration Done
1416 23:08:50.107568 ==
1417 23:08:50.110309 Dram Type= 6, Freq= 0, CH_1, rank 0
1418 23:08:50.116568 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1419 23:08:50.117181 ==
1420 23:08:50.117559 RX Vref Scan: 0
1421 23:08:50.117902
1422 23:08:50.120157 RX Vref 0 -> 0, step: 1
1423 23:08:50.120759
1424 23:08:50.123152 RX Delay -130 -> 252, step: 16
1425 23:08:50.126552 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1426 23:08:50.129808 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1427 23:08:50.133122 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1428 23:08:50.140105 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1429 23:08:50.142916 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1430 23:08:50.146408 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1431 23:08:50.150014 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1432 23:08:50.153024 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1433 23:08:50.160272 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1434 23:08:50.163898 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1435 23:08:50.167448 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1436 23:08:50.171119 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1437 23:08:50.174529 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1438 23:08:50.178069 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1439 23:08:50.181793 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1440 23:08:50.185423 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1441 23:08:50.188906 ==
1442 23:08:50.189386 Dram Type= 6, Freq= 0, CH_1, rank 0
1443 23:08:50.192710 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1444 23:08:50.196656 ==
1445 23:08:50.197119 DQS Delay:
1446 23:08:50.197548 DQS0 = 0, DQS1 = 0
1447 23:08:50.199545 DQM Delay:
1448 23:08:50.200002 DQM0 = 85, DQM1 = 75
1449 23:08:50.200374 DQ Delay:
1450 23:08:50.203391 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1451 23:08:50.206877 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =85
1452 23:08:50.210032 DQ8 =53, DQ9 =61, DQ10 =77, DQ11 =69
1453 23:08:50.213103 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1454 23:08:50.213562
1455 23:08:50.213930
1456 23:08:50.214267 ==
1457 23:08:50.216994 Dram Type= 6, Freq= 0, CH_1, rank 0
1458 23:08:50.223115 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1459 23:08:50.223662 ==
1460 23:08:50.224033
1461 23:08:50.224377
1462 23:08:50.226799 TX Vref Scan disable
1463 23:08:50.227360 == TX Byte 0 ==
1464 23:08:50.229819 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1465 23:08:50.236466 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1466 23:08:50.237091 == TX Byte 1 ==
1467 23:08:50.240176 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1468 23:08:50.246480 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1469 23:08:50.247045 ==
1470 23:08:50.249671 Dram Type= 6, Freq= 0, CH_1, rank 0
1471 23:08:50.253268 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1472 23:08:50.253829 ==
1473 23:08:50.265871 TX Vref=22, minBit 9, minWin=27, winSum=448
1474 23:08:50.269538 TX Vref=24, minBit 9, minWin=27, winSum=453
1475 23:08:50.273054 TX Vref=26, minBit 0, minWin=28, winSum=454
1476 23:08:50.276110 TX Vref=28, minBit 0, minWin=28, winSum=458
1477 23:08:50.279323 TX Vref=30, minBit 0, minWin=28, winSum=460
1478 23:08:50.285793 TX Vref=32, minBit 0, minWin=28, winSum=453
1479 23:08:50.289173 [TxChooseVref] Worse bit 0, Min win 28, Win sum 460, Final Vref 30
1480 23:08:50.289631
1481 23:08:50.292154 Final TX Range 1 Vref 30
1482 23:08:50.292662
1483 23:08:50.293036 ==
1484 23:08:50.295842 Dram Type= 6, Freq= 0, CH_1, rank 0
1485 23:08:50.299174 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1486 23:08:50.299636 ==
1487 23:08:50.302261
1488 23:08:50.302741
1489 23:08:50.303104 TX Vref Scan disable
1490 23:08:50.305344 == TX Byte 0 ==
1491 23:08:50.308861 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1492 23:08:50.316024 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1493 23:08:50.316639 == TX Byte 1 ==
1494 23:08:50.319077 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1495 23:08:50.325377 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1496 23:08:50.325839
1497 23:08:50.326203 [DATLAT]
1498 23:08:50.326547 Freq=800, CH1 RK0
1499 23:08:50.326876
1500 23:08:50.328966 DATLAT Default: 0xa
1501 23:08:50.329427 0, 0xFFFF, sum = 0
1502 23:08:50.332406 1, 0xFFFF, sum = 0
1503 23:08:50.335973 2, 0xFFFF, sum = 0
1504 23:08:50.336571 3, 0xFFFF, sum = 0
1505 23:08:50.338992 4, 0xFFFF, sum = 0
1506 23:08:50.339558 5, 0xFFFF, sum = 0
1507 23:08:50.342798 6, 0xFFFF, sum = 0
1508 23:08:50.343366 7, 0xFFFF, sum = 0
1509 23:08:50.345685 8, 0x0, sum = 1
1510 23:08:50.346212 9, 0x0, sum = 2
1511 23:08:50.346763 10, 0x0, sum = 3
1512 23:08:50.349307 11, 0x0, sum = 4
1513 23:08:50.349872 best_step = 9
1514 23:08:50.350241
1515 23:08:50.350583 ==
1516 23:08:50.352623 Dram Type= 6, Freq= 0, CH_1, rank 0
1517 23:08:50.359022 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1518 23:08:50.359583 ==
1519 23:08:50.359955 RX Vref Scan: 1
1520 23:08:50.360293
1521 23:08:50.362382 Set Vref Range= 32 -> 127
1522 23:08:50.362943
1523 23:08:50.365675 RX Vref 32 -> 127, step: 1
1524 23:08:50.366233
1525 23:08:50.369071 RX Delay -111 -> 252, step: 8
1526 23:08:50.369628
1527 23:08:50.372798 Set Vref, RX VrefLevel [Byte0]: 32
1528 23:08:50.375858 [Byte1]: 32
1529 23:08:50.376418
1530 23:08:50.378952 Set Vref, RX VrefLevel [Byte0]: 33
1531 23:08:50.382260 [Byte1]: 33
1532 23:08:50.382829
1533 23:08:50.385456 Set Vref, RX VrefLevel [Byte0]: 34
1534 23:08:50.389222 [Byte1]: 34
1535 23:08:50.389800
1536 23:08:50.392155 Set Vref, RX VrefLevel [Byte0]: 35
1537 23:08:50.396043 [Byte1]: 35
1538 23:08:50.399595
1539 23:08:50.400075 Set Vref, RX VrefLevel [Byte0]: 36
1540 23:08:50.403169 [Byte1]: 36
1541 23:08:50.407317
1542 23:08:50.407774 Set Vref, RX VrefLevel [Byte0]: 37
1543 23:08:50.410548 [Byte1]: 37
1544 23:08:50.414887
1545 23:08:50.415346 Set Vref, RX VrefLevel [Byte0]: 38
1546 23:08:50.418022 [Byte1]: 38
1547 23:08:50.422946
1548 23:08:50.423526 Set Vref, RX VrefLevel [Byte0]: 39
1549 23:08:50.426231 [Byte1]: 39
1550 23:08:50.430617
1551 23:08:50.431177 Set Vref, RX VrefLevel [Byte0]: 40
1552 23:08:50.433466 [Byte1]: 40
1553 23:08:50.437825
1554 23:08:50.441302 Set Vref, RX VrefLevel [Byte0]: 41
1555 23:08:50.441867 [Byte1]: 41
1556 23:08:50.445578
1557 23:08:50.446035 Set Vref, RX VrefLevel [Byte0]: 42
1558 23:08:50.448777 [Byte1]: 42
1559 23:08:50.453202
1560 23:08:50.453756 Set Vref, RX VrefLevel [Byte0]: 43
1561 23:08:50.456491 [Byte1]: 43
1562 23:08:50.460855
1563 23:08:50.461405 Set Vref, RX VrefLevel [Byte0]: 44
1564 23:08:50.463965 [Byte1]: 44
1565 23:08:50.468734
1566 23:08:50.469288 Set Vref, RX VrefLevel [Byte0]: 45
1567 23:08:50.471878 [Byte1]: 45
1568 23:08:50.476228
1569 23:08:50.476817 Set Vref, RX VrefLevel [Byte0]: 46
1570 23:08:50.479518 [Byte1]: 46
1571 23:08:50.483771
1572 23:08:50.484344 Set Vref, RX VrefLevel [Byte0]: 47
1573 23:08:50.487215 [Byte1]: 47
1574 23:08:50.492020
1575 23:08:50.492653 Set Vref, RX VrefLevel [Byte0]: 48
1576 23:08:50.495073 [Byte1]: 48
1577 23:08:50.499044
1578 23:08:50.499508 Set Vref, RX VrefLevel [Byte0]: 49
1579 23:08:50.502915 [Byte1]: 49
1580 23:08:50.507066
1581 23:08:50.507617 Set Vref, RX VrefLevel [Byte0]: 50
1582 23:08:50.510013 [Byte1]: 50
1583 23:08:50.514423
1584 23:08:50.514975 Set Vref, RX VrefLevel [Byte0]: 51
1585 23:08:50.517782 [Byte1]: 51
1586 23:08:50.521930
1587 23:08:50.522495 Set Vref, RX VrefLevel [Byte0]: 52
1588 23:08:50.525277 [Byte1]: 52
1589 23:08:50.529768
1590 23:08:50.530355 Set Vref, RX VrefLevel [Byte0]: 53
1591 23:08:50.532991 [Byte1]: 53
1592 23:08:50.537460
1593 23:08:50.538017 Set Vref, RX VrefLevel [Byte0]: 54
1594 23:08:50.540938 [Byte1]: 54
1595 23:08:50.544974
1596 23:08:50.545433 Set Vref, RX VrefLevel [Byte0]: 55
1597 23:08:50.548229 [Byte1]: 55
1598 23:08:50.553034
1599 23:08:50.553591 Set Vref, RX VrefLevel [Byte0]: 56
1600 23:08:50.556040 [Byte1]: 56
1601 23:08:50.560112
1602 23:08:50.560711 Set Vref, RX VrefLevel [Byte0]: 57
1603 23:08:50.563664 [Byte1]: 57
1604 23:08:50.568239
1605 23:08:50.568863 Set Vref, RX VrefLevel [Byte0]: 58
1606 23:08:50.571073 [Byte1]: 58
1607 23:08:50.576143
1608 23:08:50.576753 Set Vref, RX VrefLevel [Byte0]: 59
1609 23:08:50.579027 [Byte1]: 59
1610 23:08:50.583453
1611 23:08:50.584007 Set Vref, RX VrefLevel [Byte0]: 60
1612 23:08:50.587192 [Byte1]: 60
1613 23:08:50.590755
1614 23:08:50.591212 Set Vref, RX VrefLevel [Byte0]: 61
1615 23:08:50.594103 [Byte1]: 61
1616 23:08:50.598295
1617 23:08:50.598758 Set Vref, RX VrefLevel [Byte0]: 62
1618 23:08:50.601632 [Byte1]: 62
1619 23:08:50.606295
1620 23:08:50.606834 Set Vref, RX VrefLevel [Byte0]: 63
1621 23:08:50.609716 [Byte1]: 63
1622 23:08:50.613707
1623 23:08:50.614182 Set Vref, RX VrefLevel [Byte0]: 64
1624 23:08:50.617029 [Byte1]: 64
1625 23:08:50.621509
1626 23:08:50.622068 Set Vref, RX VrefLevel [Byte0]: 65
1627 23:08:50.624623 [Byte1]: 65
1628 23:08:50.629356
1629 23:08:50.629915 Set Vref, RX VrefLevel [Byte0]: 66
1630 23:08:50.632218 [Byte1]: 66
1631 23:08:50.636596
1632 23:08:50.637054 Set Vref, RX VrefLevel [Byte0]: 67
1633 23:08:50.639808 [Byte1]: 67
1634 23:08:50.644709
1635 23:08:50.645292 Set Vref, RX VrefLevel [Byte0]: 68
1636 23:08:50.647831 [Byte1]: 68
1637 23:08:50.652172
1638 23:08:50.652783 Set Vref, RX VrefLevel [Byte0]: 69
1639 23:08:50.655455 [Byte1]: 69
1640 23:08:50.660016
1641 23:08:50.660622 Set Vref, RX VrefLevel [Byte0]: 70
1642 23:08:50.663004 [Byte1]: 70
1643 23:08:50.667987
1644 23:08:50.668586 Set Vref, RX VrefLevel [Byte0]: 71
1645 23:08:50.670882 [Byte1]: 71
1646 23:08:50.675003
1647 23:08:50.675463 Set Vref, RX VrefLevel [Byte0]: 72
1648 23:08:50.678370 [Byte1]: 72
1649 23:08:50.682934
1650 23:08:50.683493 Set Vref, RX VrefLevel [Byte0]: 73
1651 23:08:50.685986 [Byte1]: 73
1652 23:08:50.690191
1653 23:08:50.690745 Set Vref, RX VrefLevel [Byte0]: 74
1654 23:08:50.693709 [Byte1]: 74
1655 23:08:50.697910
1656 23:08:50.698615 Set Vref, RX VrefLevel [Byte0]: 75
1657 23:08:50.701221 [Byte1]: 75
1658 23:08:50.705505
1659 23:08:50.705959 Set Vref, RX VrefLevel [Byte0]: 76
1660 23:08:50.708898 [Byte1]: 76
1661 23:08:50.713501
1662 23:08:50.714064 Set Vref, RX VrefLevel [Byte0]: 77
1663 23:08:50.716767 [Byte1]: 77
1664 23:08:50.720721
1665 23:08:50.721269 Set Vref, RX VrefLevel [Byte0]: 78
1666 23:08:50.724569 [Byte1]: 78
1667 23:08:50.729043
1668 23:08:50.729603 Final RX Vref Byte 0 = 61 to rank0
1669 23:08:50.731958 Final RX Vref Byte 1 = 55 to rank0
1670 23:08:50.735058 Final RX Vref Byte 0 = 61 to rank1
1671 23:08:50.738879 Final RX Vref Byte 1 = 55 to rank1==
1672 23:08:50.742264 Dram Type= 6, Freq= 0, CH_1, rank 0
1673 23:08:50.746001 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1674 23:08:50.746580 ==
1675 23:08:50.749225 DQS Delay:
1676 23:08:50.749682 DQS0 = 0, DQS1 = 0
1677 23:08:50.752427 DQM Delay:
1678 23:08:50.752926 DQM0 = 80, DQM1 = 75
1679 23:08:50.753297 DQ Delay:
1680 23:08:50.756173 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =80
1681 23:08:50.759329 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
1682 23:08:50.762434 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =68
1683 23:08:50.765929 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =84
1684 23:08:50.766489
1685 23:08:50.766863
1686 23:08:50.775893 [DQSOSCAuto] RK0, (LSB)MR18= 0x4d4d, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
1687 23:08:50.779357 CH1 RK0: MR19=606, MR18=4D4D
1688 23:08:50.783215 CH1_RK0: MR19=0x606, MR18=0x4D4D, DQSOSC=390, MR23=63, INC=97, DEC=64
1689 23:08:50.786078
1690 23:08:50.788882 ----->DramcWriteLeveling(PI) begin...
1691 23:08:50.789351 ==
1692 23:08:50.792201 Dram Type= 6, Freq= 0, CH_1, rank 1
1693 23:08:50.796110 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1694 23:08:50.796724 ==
1695 23:08:50.799107 Write leveling (Byte 0): 23 => 23
1696 23:08:50.802566 Write leveling (Byte 1): 23 => 23
1697 23:08:50.805963 DramcWriteLeveling(PI) end<-----
1698 23:08:50.806526
1699 23:08:50.806895 ==
1700 23:08:50.808995 Dram Type= 6, Freq= 0, CH_1, rank 1
1701 23:08:50.812119 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1702 23:08:50.812630 ==
1703 23:08:50.816015 [Gating] SW mode calibration
1704 23:08:50.822349 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1705 23:08:50.829252 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1706 23:08:50.832692 0 6 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1707 23:08:50.835783 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1708 23:08:50.842424 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1709 23:08:50.845670 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1710 23:08:50.848974 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1711 23:08:50.852234 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1712 23:08:50.859179 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1713 23:08:50.862248 0 6 28 | B1->B0 | 2525 2f2f | 0 0 | (0 0) (0 0)
1714 23:08:50.865417 0 7 0 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
1715 23:08:50.872756 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1716 23:08:50.875689 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1717 23:08:50.878874 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1718 23:08:50.885495 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1719 23:08:50.888800 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1720 23:08:50.892286 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1721 23:08:50.898511 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1722 23:08:50.902268 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1723 23:08:50.905254 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1724 23:08:50.912573 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1725 23:08:50.915444 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1726 23:08:50.918597 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1727 23:08:50.925851 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1728 23:08:50.928737 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1729 23:08:50.932192 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1730 23:08:50.939076 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1731 23:08:50.942429 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1732 23:08:50.945777 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1733 23:08:50.952077 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1734 23:08:50.955449 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1735 23:08:50.959102 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1736 23:08:50.965341 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1737 23:08:50.968847 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1738 23:08:50.972011 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1739 23:08:50.978505 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1740 23:08:50.979075 Total UI for P1: 0, mck2ui 16
1741 23:08:50.981789 best dqsien dly found for B0: ( 0, 9, 30)
1742 23:08:50.985424 Total UI for P1: 0, mck2ui 16
1743 23:08:50.988456 best dqsien dly found for B1: ( 0, 9, 30)
1744 23:08:50.991524 best DQS0 dly(MCK, UI, PI) = (0, 9, 30)
1745 23:08:50.998113 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1746 23:08:50.998663
1747 23:08:51.001544 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 30)
1748 23:08:51.005125 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1749 23:08:51.008353 [Gating] SW calibration Done
1750 23:08:51.008974 ==
1751 23:08:51.011726 Dram Type= 6, Freq= 0, CH_1, rank 1
1752 23:08:51.015058 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1753 23:08:51.015620 ==
1754 23:08:51.018602 RX Vref Scan: 0
1755 23:08:51.019167
1756 23:08:51.019539 RX Vref 0 -> 0, step: 1
1757 23:08:51.019885
1758 23:08:51.022043 RX Delay -130 -> 252, step: 16
1759 23:08:51.025250 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1760 23:08:51.031807 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1761 23:08:51.035171 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1762 23:08:51.038816 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1763 23:08:51.042193 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1764 23:08:51.045445 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1765 23:08:51.048577 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1766 23:08:51.056232 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1767 23:08:51.058730 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1768 23:08:51.061959 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1769 23:08:51.065348 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1770 23:08:51.068624 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1771 23:08:51.075331 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1772 23:08:51.078875 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1773 23:08:51.081943 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1774 23:08:51.085487 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1775 23:08:51.086052 ==
1776 23:08:51.089069 Dram Type= 6, Freq= 0, CH_1, rank 1
1777 23:08:51.095350 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1778 23:08:51.095915 ==
1779 23:08:51.096285 DQS Delay:
1780 23:08:51.098354 DQS0 = 0, DQS1 = 0
1781 23:08:51.098813 DQM Delay:
1782 23:08:51.099184 DQM0 = 85, DQM1 = 72
1783 23:08:51.101606 DQ Delay:
1784 23:08:51.104960 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1785 23:08:51.108736 DQ4 =85, DQ5 =101, DQ6 =85, DQ7 =85
1786 23:08:51.111893 DQ8 =53, DQ9 =61, DQ10 =69, DQ11 =61
1787 23:08:51.115005 DQ12 =85, DQ13 =85, DQ14 =77, DQ15 =85
1788 23:08:51.115464
1789 23:08:51.115921
1790 23:08:51.116270 ==
1791 23:08:51.118548 Dram Type= 6, Freq= 0, CH_1, rank 1
1792 23:08:51.121781 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1793 23:08:51.122341 ==
1794 23:08:51.122709
1795 23:08:51.123050
1796 23:08:51.125255 TX Vref Scan disable
1797 23:08:51.125713 == TX Byte 0 ==
1798 23:08:51.131934 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1799 23:08:51.135250 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1800 23:08:51.135804 == TX Byte 1 ==
1801 23:08:51.141877 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1802 23:08:51.145105 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1803 23:08:51.145602 ==
1804 23:08:51.148877 Dram Type= 6, Freq= 0, CH_1, rank 1
1805 23:08:51.151807 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1806 23:08:51.152366 ==
1807 23:08:51.165732 TX Vref=22, minBit 3, minWin=27, winSum=450
1808 23:08:51.169233 TX Vref=24, minBit 0, minWin=27, winSum=453
1809 23:08:51.172258 TX Vref=26, minBit 0, minWin=28, winSum=455
1810 23:08:51.175542 TX Vref=28, minBit 9, minWin=27, winSum=459
1811 23:08:51.178974 TX Vref=30, minBit 8, minWin=28, winSum=461
1812 23:08:51.185860 TX Vref=32, minBit 9, minWin=27, winSum=456
1813 23:08:51.189187 [TxChooseVref] Worse bit 8, Min win 28, Win sum 461, Final Vref 30
1814 23:08:51.189747
1815 23:08:51.192160 Final TX Range 1 Vref 30
1816 23:08:51.192661
1817 23:08:51.193035 ==
1818 23:08:51.195716 Dram Type= 6, Freq= 0, CH_1, rank 1
1819 23:08:51.198651 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1820 23:08:51.199115 ==
1821 23:08:51.201953
1822 23:08:51.202410
1823 23:08:51.202773 TX Vref Scan disable
1824 23:08:51.205355 == TX Byte 0 ==
1825 23:08:51.209350 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1826 23:08:51.212682 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1827 23:08:51.215904 == TX Byte 1 ==
1828 23:08:51.219241 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1829 23:08:51.222230 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1830 23:08:51.225571
1831 23:08:51.226030 [DATLAT]
1832 23:08:51.226416 Freq=800, CH1 RK1
1833 23:08:51.226776
1834 23:08:51.228813 DATLAT Default: 0x9
1835 23:08:51.229274 0, 0xFFFF, sum = 0
1836 23:08:51.232672 1, 0xFFFF, sum = 0
1837 23:08:51.233240 2, 0xFFFF, sum = 0
1838 23:08:51.235792 3, 0xFFFF, sum = 0
1839 23:08:51.236258 4, 0xFFFF, sum = 0
1840 23:08:51.238864 5, 0xFFFF, sum = 0
1841 23:08:51.239330 6, 0xFFFF, sum = 0
1842 23:08:51.242362 7, 0xFFFF, sum = 0
1843 23:08:51.242992 8, 0x0, sum = 1
1844 23:08:51.245416 9, 0x0, sum = 2
1845 23:08:51.245921 10, 0x0, sum = 3
1846 23:08:51.248846 11, 0x0, sum = 4
1847 23:08:51.249317 best_step = 9
1848 23:08:51.249688
1849 23:08:51.250027 ==
1850 23:08:51.252735 Dram Type= 6, Freq= 0, CH_1, rank 1
1851 23:08:51.258835 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1852 23:08:51.259397 ==
1853 23:08:51.259769 RX Vref Scan: 0
1854 23:08:51.260110
1855 23:08:51.262346 RX Vref 0 -> 0, step: 1
1856 23:08:51.262804
1857 23:08:51.265488 RX Delay -111 -> 252, step: 8
1858 23:08:51.268749 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
1859 23:08:51.272309 iDelay=209, Bit 1, Center 80 (-39 ~ 200) 240
1860 23:08:51.279072 iDelay=209, Bit 2, Center 72 (-47 ~ 192) 240
1861 23:08:51.282385 iDelay=209, Bit 3, Center 80 (-39 ~ 200) 240
1862 23:08:51.285767 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
1863 23:08:51.289130 iDelay=209, Bit 5, Center 92 (-23 ~ 208) 232
1864 23:08:51.291927 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1865 23:08:51.298421 iDelay=209, Bit 7, Center 80 (-39 ~ 200) 240
1866 23:08:51.301952 iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232
1867 23:08:51.305366 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
1868 23:08:51.308868 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1869 23:08:51.312055 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1870 23:08:51.318758 iDelay=209, Bit 12, Center 84 (-39 ~ 208) 248
1871 23:08:51.322000 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
1872 23:08:51.325414 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1873 23:08:51.328985 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1874 23:08:51.329728 ==
1875 23:08:51.332347 Dram Type= 6, Freq= 0, CH_1, rank 1
1876 23:08:51.335585 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1877 23:08:51.338969 ==
1878 23:08:51.339533 DQS Delay:
1879 23:08:51.339905 DQS0 = 0, DQS1 = 0
1880 23:08:51.342032 DQM Delay:
1881 23:08:51.342496 DQM0 = 82, DQM1 = 74
1882 23:08:51.342867 DQ Delay:
1883 23:08:51.345687 DQ0 =84, DQ1 =80, DQ2 =72, DQ3 =80
1884 23:08:51.348966 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =80
1885 23:08:51.352080 DQ8 =60, DQ9 =64, DQ10 =72, DQ11 =68
1886 23:08:51.355289 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =84
1887 23:08:51.355750
1888 23:08:51.356120
1889 23:08:51.365803 [DQSOSCAuto] RK1, (LSB)MR18= 0x3838, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
1890 23:08:51.368936 CH1 RK1: MR19=606, MR18=3838
1891 23:08:51.375806 CH1_RK1: MR19=0x606, MR18=0x3838, DQSOSC=395, MR23=63, INC=94, DEC=63
1892 23:08:51.376370 [RxdqsGatingPostProcess] freq 800
1893 23:08:51.382506 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1894 23:08:51.385364 Pre-setting of DQS Precalculation
1895 23:08:51.389072 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1896 23:08:51.399199 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1897 23:08:51.405466 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1898 23:08:51.405938
1899 23:08:51.406305
1900 23:08:51.408824 [Calibration Summary] 1600 Mbps
1901 23:08:51.409288 CH 0, Rank 0
1902 23:08:51.412278 SW Impedance : PASS
1903 23:08:51.412909 DUTY Scan : NO K
1904 23:08:51.415676 ZQ Calibration : PASS
1905 23:08:51.419199 Jitter Meter : NO K
1906 23:08:51.419763 CBT Training : PASS
1907 23:08:51.422279 Write leveling : PASS
1908 23:08:51.425611 RX DQS gating : PASS
1909 23:08:51.426177 RX DQ/DQS(RDDQC) : PASS
1910 23:08:51.429480 TX DQ/DQS : PASS
1911 23:08:51.432495 RX DATLAT : PASS
1912 23:08:51.433109 RX DQ/DQS(Engine): PASS
1913 23:08:51.435594 TX OE : NO K
1914 23:08:51.436075 All Pass.
1915 23:08:51.436448
1916 23:08:51.436853 CH 0, Rank 1
1917 23:08:51.438655 SW Impedance : PASS
1918 23:08:51.442255 DUTY Scan : NO K
1919 23:08:51.442825 ZQ Calibration : PASS
1920 23:08:51.445651 Jitter Meter : NO K
1921 23:08:51.448975 CBT Training : PASS
1922 23:08:51.449547 Write leveling : PASS
1923 23:08:51.452380 RX DQS gating : PASS
1924 23:08:51.455514 RX DQ/DQS(RDDQC) : PASS
1925 23:08:51.456129 TX DQ/DQS : PASS
1926 23:08:51.458978 RX DATLAT : PASS
1927 23:08:51.462233 RX DQ/DQS(Engine): PASS
1928 23:08:51.462812 TX OE : NO K
1929 23:08:51.465568 All Pass.
1930 23:08:51.466183
1931 23:08:51.466565 CH 1, Rank 0
1932 23:08:51.469021 SW Impedance : PASS
1933 23:08:51.469622 DUTY Scan : NO K
1934 23:08:51.472273 ZQ Calibration : PASS
1935 23:08:51.475988 Jitter Meter : NO K
1936 23:08:51.476615 CBT Training : PASS
1937 23:08:51.478578 Write leveling : PASS
1938 23:08:51.482128 RX DQS gating : PASS
1939 23:08:51.482694 RX DQ/DQS(RDDQC) : PASS
1940 23:08:51.485606 TX DQ/DQS : PASS
1941 23:08:51.486183 RX DATLAT : PASS
1942 23:08:51.489303 RX DQ/DQS(Engine): PASS
1943 23:08:51.491971 TX OE : NO K
1944 23:08:51.492468 All Pass.
1945 23:08:51.492907
1946 23:08:51.493259 CH 1, Rank 1
1947 23:08:51.495254 SW Impedance : PASS
1948 23:08:51.498876 DUTY Scan : NO K
1949 23:08:51.499345 ZQ Calibration : PASS
1950 23:08:51.501945 Jitter Meter : NO K
1951 23:08:51.505643 CBT Training : PASS
1952 23:08:51.506114 Write leveling : PASS
1953 23:08:51.508626 RX DQS gating : PASS
1954 23:08:51.512172 RX DQ/DQS(RDDQC) : PASS
1955 23:08:51.512683 TX DQ/DQS : PASS
1956 23:08:51.515413 RX DATLAT : PASS
1957 23:08:51.518725 RX DQ/DQS(Engine): PASS
1958 23:08:51.519192 TX OE : NO K
1959 23:08:51.519566 All Pass.
1960 23:08:51.522063
1961 23:08:51.522529 DramC Write-DBI off
1962 23:08:51.525242 PER_BANK_REFRESH: Hybrid Mode
1963 23:08:51.525712 TX_TRACKING: ON
1964 23:08:51.528676 [GetDramInforAfterCalByMRR] Vendor 6.
1965 23:08:51.532082 [GetDramInforAfterCalByMRR] Revision 606.
1966 23:08:51.539229 [GetDramInforAfterCalByMRR] Revision 2 0.
1967 23:08:51.539806 MR0 0x3939
1968 23:08:51.540183 MR8 0x1111
1969 23:08:51.542221 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
1970 23:08:51.542845
1971 23:08:51.545563 MR0 0x3939
1972 23:08:51.546126 MR8 0x1111
1973 23:08:51.548910 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
1974 23:08:51.549479
1975 23:08:51.559148 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
1976 23:08:51.562349 [FAST_K] Save calibration result to emmc
1977 23:08:51.565425 [FAST_K] Save calibration result to emmc
1978 23:08:51.568873 dram_init: config_dvfs: 1
1979 23:08:51.572209 dramc_set_vcore_voltage set vcore to 662500
1980 23:08:51.572898 Read voltage for 1200, 2
1981 23:08:51.575398 Vio18 = 0
1982 23:08:51.575982 Vcore = 662500
1983 23:08:51.576356 Vdram = 0
1984 23:08:51.578557 Vddq = 0
1985 23:08:51.579407 Vmddr = 0
1986 23:08:51.585366 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
1987 23:08:51.588344 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
1988 23:08:51.591919 MEM_TYPE=3, freq_sel=15
1989 23:08:51.595152 sv_algorithm_assistance_LP4_1600
1990 23:08:51.598444 ============ PULL DRAM RESETB DOWN ============
1991 23:08:51.601855 ========== PULL DRAM RESETB DOWN end =========
1992 23:08:51.608611 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
1993 23:08:51.611783 ===================================
1994 23:08:51.612251 LPDDR4 DRAM CONFIGURATION
1995 23:08:51.615495 ===================================
1996 23:08:51.619027 EX_ROW_EN[0] = 0x0
1997 23:08:51.619596 EX_ROW_EN[1] = 0x0
1998 23:08:51.622267 LP4Y_EN = 0x0
1999 23:08:51.622838 WORK_FSP = 0x0
2000 23:08:51.625359 WL = 0x4
2001 23:08:51.628563 RL = 0x4
2002 23:08:51.629039 BL = 0x2
2003 23:08:51.632066 RPST = 0x0
2004 23:08:51.632702 RD_PRE = 0x0
2005 23:08:51.635594 WR_PRE = 0x1
2006 23:08:51.636158 WR_PST = 0x0
2007 23:08:51.638847 DBI_WR = 0x0
2008 23:08:51.639417 DBI_RD = 0x0
2009 23:08:51.642037 OTF = 0x1
2010 23:08:51.645563 ===================================
2011 23:08:51.648866 ===================================
2012 23:08:51.649446 ANA top config
2013 23:08:51.651867 ===================================
2014 23:08:51.655887 DLL_ASYNC_EN = 0
2015 23:08:51.658700 ALL_SLAVE_EN = 0
2016 23:08:51.659267 NEW_RANK_MODE = 1
2017 23:08:51.662474 DLL_IDLE_MODE = 1
2018 23:08:51.665114 LP45_APHY_COMB_EN = 1
2019 23:08:51.668715 TX_ODT_DIS = 1
2020 23:08:51.669186 NEW_8X_MODE = 1
2021 23:08:51.672279 ===================================
2022 23:08:51.675445 ===================================
2023 23:08:51.678634 data_rate = 2400
2024 23:08:51.682438 CKR = 1
2025 23:08:51.685557 DQ_P2S_RATIO = 8
2026 23:08:51.688796 ===================================
2027 23:08:51.692699 CA_P2S_RATIO = 8
2028 23:08:51.695641 DQ_CA_OPEN = 0
2029 23:08:51.696109 DQ_SEMI_OPEN = 0
2030 23:08:51.698784 CA_SEMI_OPEN = 0
2031 23:08:51.701913 CA_FULL_RATE = 0
2032 23:08:51.705584 DQ_CKDIV4_EN = 0
2033 23:08:51.708842 CA_CKDIV4_EN = 0
2034 23:08:51.712161 CA_PREDIV_EN = 0
2035 23:08:51.712684 PH8_DLY = 17
2036 23:08:51.715536 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2037 23:08:51.718898 DQ_AAMCK_DIV = 4
2038 23:08:51.722088 CA_AAMCK_DIV = 4
2039 23:08:51.725166 CA_ADMCK_DIV = 4
2040 23:08:51.728588 DQ_TRACK_CA_EN = 0
2041 23:08:51.729061 CA_PICK = 1200
2042 23:08:51.732139 CA_MCKIO = 1200
2043 23:08:51.735230 MCKIO_SEMI = 0
2044 23:08:51.738872 PLL_FREQ = 2366
2045 23:08:51.742212 DQ_UI_PI_RATIO = 32
2046 23:08:51.745241 CA_UI_PI_RATIO = 0
2047 23:08:51.749099 ===================================
2048 23:08:51.752305 ===================================
2049 23:08:51.752982 memory_type:LPDDR4
2050 23:08:51.755448 GP_NUM : 10
2051 23:08:51.758658 SRAM_EN : 1
2052 23:08:51.759227 MD32_EN : 0
2053 23:08:51.762196 ===================================
2054 23:08:51.765213 [ANA_INIT] >>>>>>>>>>>>>>
2055 23:08:51.768638 <<<<<< [CONFIGURE PHASE]: ANA_TX
2056 23:08:51.771894 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2057 23:08:51.775077 ===================================
2058 23:08:51.778595 data_rate = 2400,PCW = 0X5b00
2059 23:08:51.781806 ===================================
2060 23:08:51.785153 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2061 23:08:51.788662 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2062 23:08:51.794789 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2063 23:08:51.801488 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2064 23:08:51.805217 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2065 23:08:51.808253 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2066 23:08:51.808883 [ANA_INIT] flow start
2067 23:08:51.811330 [ANA_INIT] PLL >>>>>>>>
2068 23:08:51.814897 [ANA_INIT] PLL <<<<<<<<
2069 23:08:51.815492 [ANA_INIT] MIDPI >>>>>>>>
2070 23:08:51.818371 [ANA_INIT] MIDPI <<<<<<<<
2071 23:08:51.821471 [ANA_INIT] DLL >>>>>>>>
2072 23:08:51.821942 [ANA_INIT] DLL <<<<<<<<
2073 23:08:51.824815 [ANA_INIT] flow end
2074 23:08:51.828436 ============ LP4 DIFF to SE enter ============
2075 23:08:51.831698 ============ LP4 DIFF to SE exit ============
2076 23:08:51.834867 [ANA_INIT] <<<<<<<<<<<<<
2077 23:08:51.838106 [Flow] Enable top DCM control >>>>>
2078 23:08:51.841587 [Flow] Enable top DCM control <<<<<
2079 23:08:51.844985 Enable DLL master slave shuffle
2080 23:08:51.851185 ==============================================================
2081 23:08:51.851741 Gating Mode config
2082 23:08:51.858399 ==============================================================
2083 23:08:51.858958 Config description:
2084 23:08:51.868158 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2085 23:08:51.874484 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2086 23:08:51.881693 SELPH_MODE 0: By rank 1: By Phase
2087 23:08:51.884746 ==============================================================
2088 23:08:51.888410 GAT_TRACK_EN = 1
2089 23:08:51.891522 RX_GATING_MODE = 2
2090 23:08:51.894470 RX_GATING_TRACK_MODE = 2
2091 23:08:51.898156 SELPH_MODE = 1
2092 23:08:51.901169 PICG_EARLY_EN = 1
2093 23:08:51.905134 VALID_LAT_VALUE = 1
2094 23:08:51.911607 ==============================================================
2095 23:08:51.914849 Enter into Gating configuration >>>>
2096 23:08:51.917971 Exit from Gating configuration <<<<
2097 23:08:51.918681 Enter into DVFS_PRE_config >>>>>
2098 23:08:51.931432 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2099 23:08:51.934528 Exit from DVFS_PRE_config <<<<<
2100 23:08:51.938024 Enter into PICG configuration >>>>
2101 23:08:51.941456 Exit from PICG configuration <<<<
2102 23:08:51.942021 [RX_INPUT] configuration >>>>>
2103 23:08:51.944441 [RX_INPUT] configuration <<<<<
2104 23:08:51.951551 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2105 23:08:51.955138 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2106 23:08:51.961237 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2107 23:08:51.968042 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2108 23:08:51.974353 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2109 23:08:51.981495 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2110 23:08:51.984568 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2111 23:08:51.987910 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2112 23:08:51.994001 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2113 23:08:51.997615 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2114 23:08:52.000955 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2115 23:08:52.004055 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2116 23:08:52.007752 ===================================
2117 23:08:52.011124 LPDDR4 DRAM CONFIGURATION
2118 23:08:52.014513 ===================================
2119 23:08:52.017569 EX_ROW_EN[0] = 0x0
2120 23:08:52.018041 EX_ROW_EN[1] = 0x0
2121 23:08:52.020936 LP4Y_EN = 0x0
2122 23:08:52.021423 WORK_FSP = 0x0
2123 23:08:52.024364 WL = 0x4
2124 23:08:52.024972 RL = 0x4
2125 23:08:52.027777 BL = 0x2
2126 23:08:52.028341 RPST = 0x0
2127 23:08:52.030880 RD_PRE = 0x0
2128 23:08:52.031441 WR_PRE = 0x1
2129 23:08:52.034297 WR_PST = 0x0
2130 23:08:52.034852 DBI_WR = 0x0
2131 23:08:52.037931 DBI_RD = 0x0
2132 23:08:52.041002 OTF = 0x1
2133 23:08:52.041474 ===================================
2134 23:08:52.047709 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2135 23:08:52.051150 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2136 23:08:52.054673 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2137 23:08:52.057703 ===================================
2138 23:08:52.061194 LPDDR4 DRAM CONFIGURATION
2139 23:08:52.064560 ===================================
2140 23:08:52.068219 EX_ROW_EN[0] = 0x10
2141 23:08:52.068856 EX_ROW_EN[1] = 0x0
2142 23:08:52.070656 LP4Y_EN = 0x0
2143 23:08:52.071122 WORK_FSP = 0x0
2144 23:08:52.074417 WL = 0x4
2145 23:08:52.074991 RL = 0x4
2146 23:08:52.077305 BL = 0x2
2147 23:08:52.077776 RPST = 0x0
2148 23:08:52.080980 RD_PRE = 0x0
2149 23:08:52.081539 WR_PRE = 0x1
2150 23:08:52.084702 WR_PST = 0x0
2151 23:08:52.085262 DBI_WR = 0x0
2152 23:08:52.087515 DBI_RD = 0x0
2153 23:08:52.088074 OTF = 0x1
2154 23:08:52.091229 ===================================
2155 23:08:52.097663 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2156 23:08:52.098220 ==
2157 23:08:52.100803 Dram Type= 6, Freq= 0, CH_0, rank 0
2158 23:08:52.107401 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2159 23:08:52.107869 ==
2160 23:08:52.108234 [Duty_Offset_Calibration]
2161 23:08:52.110578 B0:0 B1:2 CA:1
2162 23:08:52.111036
2163 23:08:52.114188 [DutyScan_Calibration_Flow] k_type=0
2164 23:08:52.122792
2165 23:08:52.123351 ==CLK 0==
2166 23:08:52.125995 Final CLK duty delay cell = 0
2167 23:08:52.129718 [0] MAX Duty = 5093%(X100), DQS PI = 12
2168 23:08:52.132680 [0] MIN Duty = 4938%(X100), DQS PI = 52
2169 23:08:52.133141 [0] AVG Duty = 5015%(X100)
2170 23:08:52.136131
2171 23:08:52.140019 CH0 CLK Duty spec in!! Max-Min= 155%
2172 23:08:52.142533 [DutyScan_Calibration_Flow] ====Done====
2173 23:08:52.143078
2174 23:08:52.146092 [DutyScan_Calibration_Flow] k_type=1
2175 23:08:52.162166
2176 23:08:52.162726 ==DQS 0 ==
2177 23:08:52.165457 Final DQS duty delay cell = 0
2178 23:08:52.168820 [0] MAX Duty = 5125%(X100), DQS PI = 30
2179 23:08:52.172148 [0] MIN Duty = 5031%(X100), DQS PI = 6
2180 23:08:52.172756 [0] AVG Duty = 5078%(X100)
2181 23:08:52.175414
2182 23:08:52.175872 ==DQS 1 ==
2183 23:08:52.178971 Final DQS duty delay cell = 0
2184 23:08:52.182131 [0] MAX Duty = 5031%(X100), DQS PI = 54
2185 23:08:52.185377 [0] MIN Duty = 4906%(X100), DQS PI = 14
2186 23:08:52.185935 [0] AVG Duty = 4968%(X100)
2187 23:08:52.188995
2188 23:08:52.192018 CH0 DQS 0 Duty spec in!! Max-Min= 94%
2189 23:08:52.192628
2190 23:08:52.195037 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2191 23:08:52.198337 [DutyScan_Calibration_Flow] ====Done====
2192 23:08:52.198798
2193 23:08:52.201818 [DutyScan_Calibration_Flow] k_type=3
2194 23:08:52.218204
2195 23:08:52.218675 ==DQM 0 ==
2196 23:08:52.221703 Final DQM duty delay cell = 0
2197 23:08:52.224792 [0] MAX Duty = 5124%(X100), DQS PI = 20
2198 23:08:52.228350 [0] MIN Duty = 4969%(X100), DQS PI = 38
2199 23:08:52.228606 [0] AVG Duty = 5046%(X100)
2200 23:08:52.231697
2201 23:08:52.232027 ==DQM 1 ==
2202 23:08:52.235165 Final DQM duty delay cell = 0
2203 23:08:52.238635 [0] MAX Duty = 5000%(X100), DQS PI = 56
2204 23:08:52.241527 [0] MIN Duty = 4813%(X100), DQS PI = 24
2205 23:08:52.244887 [0] AVG Duty = 4906%(X100)
2206 23:08:52.245219
2207 23:08:52.248133 CH0 DQM 0 Duty spec in!! Max-Min= 155%
2208 23:08:52.248377
2209 23:08:52.251681 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2210 23:08:52.254879 [DutyScan_Calibration_Flow] ====Done====
2211 23:08:52.255211
2212 23:08:52.258192 [DutyScan_Calibration_Flow] k_type=2
2213 23:08:52.273662
2214 23:08:52.274221 ==DQ 0 ==
2215 23:08:52.277170 Final DQ duty delay cell = -4
2216 23:08:52.279991 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2217 23:08:52.283715 [-4] MIN Duty = 4813%(X100), DQS PI = 8
2218 23:08:52.287003 [-4] AVG Duty = 4937%(X100)
2219 23:08:52.287567
2220 23:08:52.287941 ==DQ 1 ==
2221 23:08:52.290180 Final DQ duty delay cell = -4
2222 23:08:52.293939 [-4] MAX Duty = 5062%(X100), DQS PI = 6
2223 23:08:52.296924 [-4] MIN Duty = 4876%(X100), DQS PI = 62
2224 23:08:52.300104 [-4] AVG Duty = 4969%(X100)
2225 23:08:52.300737
2226 23:08:52.303379 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2227 23:08:52.303942
2228 23:08:52.306708 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2229 23:08:52.310057 [DutyScan_Calibration_Flow] ====Done====
2230 23:08:52.310617 ==
2231 23:08:52.313250 Dram Type= 6, Freq= 0, CH_1, rank 0
2232 23:08:52.316825 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2233 23:08:52.317388 ==
2234 23:08:52.319998 [Duty_Offset_Calibration]
2235 23:08:52.320629 B0:0 B1:4 CA:-5
2236 23:08:52.321044
2237 23:08:52.323526 [DutyScan_Calibration_Flow] k_type=0
2238 23:08:52.334050
2239 23:08:52.334609 ==CLK 0==
2240 23:08:52.337258 Final CLK duty delay cell = 0
2241 23:08:52.340973 [0] MAX Duty = 5094%(X100), DQS PI = 24
2242 23:08:52.343987 [0] MIN Duty = 4907%(X100), DQS PI = 2
2243 23:08:52.344582 [0] AVG Duty = 5000%(X100)
2244 23:08:52.347332
2245 23:08:52.350797 CH1 CLK Duty spec in!! Max-Min= 187%
2246 23:08:52.353891 [DutyScan_Calibration_Flow] ====Done====
2247 23:08:52.354354
2248 23:08:52.357325 [DutyScan_Calibration_Flow] k_type=1
2249 23:08:52.372901
2250 23:08:52.373458 ==DQS 0 ==
2251 23:08:52.375720 Final DQS duty delay cell = 0
2252 23:08:52.379127 [0] MAX Duty = 5125%(X100), DQS PI = 16
2253 23:08:52.382645 [0] MIN Duty = 4875%(X100), DQS PI = 40
2254 23:08:52.385697 [0] AVG Duty = 5000%(X100)
2255 23:08:52.386258
2256 23:08:52.386630 ==DQS 1 ==
2257 23:08:52.389249 Final DQS duty delay cell = -4
2258 23:08:52.392339 [-4] MAX Duty = 5000%(X100), DQS PI = 18
2259 23:08:52.395920 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2260 23:08:52.399280 [-4] AVG Duty = 4953%(X100)
2261 23:08:52.399851
2262 23:08:52.402607 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2263 23:08:52.403072
2264 23:08:52.406089 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2265 23:08:52.409342 [DutyScan_Calibration_Flow] ====Done====
2266 23:08:52.409812
2267 23:08:52.412766 [DutyScan_Calibration_Flow] k_type=3
2268 23:08:52.427631
2269 23:08:52.428198 ==DQM 0 ==
2270 23:08:52.431124 Final DQM duty delay cell = -4
2271 23:08:52.434555 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2272 23:08:52.437766 [-4] MIN Duty = 4844%(X100), DQS PI = 40
2273 23:08:52.441163 [-4] AVG Duty = 4953%(X100)
2274 23:08:52.441731
2275 23:08:52.442126 ==DQM 1 ==
2276 23:08:52.444437 Final DQM duty delay cell = -4
2277 23:08:52.447349 [-4] MAX Duty = 5062%(X100), DQS PI = 4
2278 23:08:52.451065 [-4] MIN Duty = 4907%(X100), DQS PI = 60
2279 23:08:52.454037 [-4] AVG Duty = 4984%(X100)
2280 23:08:52.454505
2281 23:08:52.457628 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2282 23:08:52.458197
2283 23:08:52.460782 CH1 DQM 1 Duty spec in!! Max-Min= 155%
2284 23:08:52.464123 [DutyScan_Calibration_Flow] ====Done====
2285 23:08:52.464750
2286 23:08:52.467446 [DutyScan_Calibration_Flow] k_type=2
2287 23:08:52.485012
2288 23:08:52.485593 ==DQ 0 ==
2289 23:08:52.488246 Final DQ duty delay cell = 0
2290 23:08:52.491496 [0] MAX Duty = 5062%(X100), DQS PI = 0
2291 23:08:52.494630 [0] MIN Duty = 4969%(X100), DQS PI = 44
2292 23:08:52.495104 [0] AVG Duty = 5015%(X100)
2293 23:08:52.495477
2294 23:08:52.498027 ==DQ 1 ==
2295 23:08:52.501471 Final DQ duty delay cell = 0
2296 23:08:52.504810 [0] MAX Duty = 5031%(X100), DQS PI = 8
2297 23:08:52.508078 [0] MIN Duty = 4875%(X100), DQS PI = 32
2298 23:08:52.508590 [0] AVG Duty = 4953%(X100)
2299 23:08:52.508972
2300 23:08:52.511283 CH1 DQ 0 Duty spec in!! Max-Min= 93%
2301 23:08:52.511751
2302 23:08:52.514787 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2303 23:08:52.521253 [DutyScan_Calibration_Flow] ====Done====
2304 23:08:52.524781 nWR fixed to 30
2305 23:08:52.525354 [ModeRegInit_LP4] CH0 RK0
2306 23:08:52.528309 [ModeRegInit_LP4] CH0 RK1
2307 23:08:52.531336 [ModeRegInit_LP4] CH1 RK0
2308 23:08:52.531920 [ModeRegInit_LP4] CH1 RK1
2309 23:08:52.534990 match AC timing 6
2310 23:08:52.538121 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2311 23:08:52.541388 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2312 23:08:52.548254 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2313 23:08:52.551254 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2314 23:08:52.557952 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2315 23:08:52.558525 ==
2316 23:08:52.561498 Dram Type= 6, Freq= 0, CH_0, rank 0
2317 23:08:52.564900 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2318 23:08:52.565474 ==
2319 23:08:52.571683 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2320 23:08:52.574745 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2321 23:08:52.584491 [CA 0] Center 39 (9~70) winsize 62
2322 23:08:52.587644 [CA 1] Center 39 (8~70) winsize 63
2323 23:08:52.591072 [CA 2] Center 36 (5~67) winsize 63
2324 23:08:52.594149 [CA 3] Center 35 (4~66) winsize 63
2325 23:08:52.597962 [CA 4] Center 34 (3~65) winsize 63
2326 23:08:52.601198 [CA 5] Center 33 (3~64) winsize 62
2327 23:08:52.601882
2328 23:08:52.604870 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2329 23:08:52.605444
2330 23:08:52.607924 [CATrainingPosCal] consider 1 rank data
2331 23:08:52.610757 u2DelayCellTimex100 = 270/100 ps
2332 23:08:52.614348 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2333 23:08:52.617322 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2334 23:08:52.624059 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2335 23:08:52.627630 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2336 23:08:52.630732 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
2337 23:08:52.634218 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2338 23:08:52.634788
2339 23:08:52.637613 CA PerBit enable=1, Macro0, CA PI delay=33
2340 23:08:52.638193
2341 23:08:52.640660 [CBTSetCACLKResult] CA Dly = 33
2342 23:08:52.641129 CS Dly: 7 (0~38)
2343 23:08:52.644339 ==
2344 23:08:52.644987 Dram Type= 6, Freq= 0, CH_0, rank 1
2345 23:08:52.651329 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2346 23:08:52.651897 ==
2347 23:08:52.654257 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2348 23:08:52.660638 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2349 23:08:52.669683 [CA 0] Center 39 (8~70) winsize 63
2350 23:08:52.673347 [CA 1] Center 39 (8~70) winsize 63
2351 23:08:52.676272 [CA 2] Center 36 (5~67) winsize 63
2352 23:08:52.679842 [CA 3] Center 35 (4~66) winsize 63
2353 23:08:52.682853 [CA 4] Center 33 (3~64) winsize 62
2354 23:08:52.686273 [CA 5] Center 34 (3~65) winsize 63
2355 23:08:52.686741
2356 23:08:52.689436 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2357 23:08:52.689984
2358 23:08:52.692807 [CATrainingPosCal] consider 2 rank data
2359 23:08:52.696416 u2DelayCellTimex100 = 270/100 ps
2360 23:08:52.699415 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2361 23:08:52.706179 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2362 23:08:52.709177 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2363 23:08:52.712915 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2364 23:08:52.716114 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2365 23:08:52.719447 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2366 23:08:52.720033
2367 23:08:52.722906 CA PerBit enable=1, Macro0, CA PI delay=33
2368 23:08:52.723488
2369 23:08:52.726007 [CBTSetCACLKResult] CA Dly = 33
2370 23:08:52.729163 CS Dly: 7 (0~39)
2371 23:08:52.729631
2372 23:08:52.732710 ----->DramcWriteLeveling(PI) begin...
2373 23:08:52.733294 ==
2374 23:08:52.736025 Dram Type= 6, Freq= 0, CH_0, rank 0
2375 23:08:52.739231 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2376 23:08:52.739705 ==
2377 23:08:52.742528 Write leveling (Byte 0): 28 => 28
2378 23:08:52.746084 Write leveling (Byte 1): 26 => 26
2379 23:08:52.749019 DramcWriteLeveling(PI) end<-----
2380 23:08:52.749483
2381 23:08:52.749854 ==
2382 23:08:52.753047 Dram Type= 6, Freq= 0, CH_0, rank 0
2383 23:08:52.756467 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2384 23:08:52.757078 ==
2385 23:08:52.759028 [Gating] SW mode calibration
2386 23:08:52.765880 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2387 23:08:52.772564 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2388 23:08:52.776100 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2389 23:08:52.779470 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2390 23:08:52.785814 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2391 23:08:52.789187 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2392 23:08:52.792424 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
2393 23:08:52.799163 0 11 20 | B1->B0 | 2e2e 2727 | 0 0 | (0 1) (0 0)
2394 23:08:52.802405 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2395 23:08:52.805905 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2396 23:08:52.812164 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2397 23:08:52.815663 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2398 23:08:52.819344 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2399 23:08:52.825436 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2400 23:08:52.828961 0 12 16 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
2401 23:08:52.832288 0 12 20 | B1->B0 | 3c3c 3f3f | 1 0 | (0 0) (0 0)
2402 23:08:52.838911 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2403 23:08:52.842398 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2404 23:08:52.845225 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2405 23:08:52.848808 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2406 23:08:52.855597 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2407 23:08:52.858628 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2408 23:08:52.862776 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2409 23:08:52.869074 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2410 23:08:52.872015 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2411 23:08:52.875610 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2412 23:08:52.882787 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2413 23:08:52.885339 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2414 23:08:52.888838 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2415 23:08:52.895304 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2416 23:08:52.899348 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2417 23:08:52.901856 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2418 23:08:52.908993 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2419 23:08:52.912583 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2420 23:08:52.915647 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2421 23:08:52.922477 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2422 23:08:52.925272 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2423 23:08:52.929085 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2424 23:08:52.935574 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2425 23:08:52.938856 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2426 23:08:52.942426 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2427 23:08:52.945651 Total UI for P1: 0, mck2ui 16
2428 23:08:52.948668 best dqsien dly found for B0: ( 0, 15, 18)
2429 23:08:52.952269 Total UI for P1: 0, mck2ui 16
2430 23:08:52.955508 best dqsien dly found for B1: ( 0, 15, 18)
2431 23:08:52.958791 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2432 23:08:52.962028 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2433 23:08:52.962591
2434 23:08:52.965459 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2435 23:08:52.971893 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
2436 23:08:52.972452 [Gating] SW calibration Done
2437 23:08:52.972867 ==
2438 23:08:52.975109 Dram Type= 6, Freq= 0, CH_0, rank 0
2439 23:08:52.982071 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2440 23:08:52.982631 ==
2441 23:08:52.983004 RX Vref Scan: 0
2442 23:08:52.983511
2443 23:08:52.985039 RX Vref 0 -> 0, step: 1
2444 23:08:52.985501
2445 23:08:52.988443 RX Delay -40 -> 252, step: 8
2446 23:08:52.992053 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2447 23:08:52.995395 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2448 23:08:52.998881 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2449 23:08:53.005307 iDelay=200, Bit 3, Center 111 (32 ~ 191) 160
2450 23:08:53.008591 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2451 23:08:53.011859 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2452 23:08:53.015291 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2453 23:08:53.018620 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2454 23:08:53.022075 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2455 23:08:53.029051 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2456 23:08:53.031998 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2457 23:08:53.035138 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2458 23:08:53.038745 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2459 23:08:53.041846 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2460 23:08:53.048642 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2461 23:08:53.052129 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
2462 23:08:53.052733 ==
2463 23:08:53.055348 Dram Type= 6, Freq= 0, CH_0, rank 0
2464 23:08:53.058811 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2465 23:08:53.059378 ==
2466 23:08:53.062178 DQS Delay:
2467 23:08:53.062738 DQS0 = 0, DQS1 = 0
2468 23:08:53.063112 DQM Delay:
2469 23:08:53.065029 DQM0 = 115, DQM1 = 105
2470 23:08:53.065492 DQ Delay:
2471 23:08:53.068903 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =111
2472 23:08:53.072052 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2473 23:08:53.075211 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =99
2474 23:08:53.081807 DQ12 =111, DQ13 =115, DQ14 =115, DQ15 =115
2475 23:08:53.082369
2476 23:08:53.082740
2477 23:08:53.083079 ==
2478 23:08:53.085192 Dram Type= 6, Freq= 0, CH_0, rank 0
2479 23:08:53.088554 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2480 23:08:53.089125 ==
2481 23:08:53.089503
2482 23:08:53.089889
2483 23:08:53.091741 TX Vref Scan disable
2484 23:08:53.092202 == TX Byte 0 ==
2485 23:08:53.098368 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2486 23:08:53.102235 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2487 23:08:53.102839 == TX Byte 1 ==
2488 23:08:53.108572 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2489 23:08:53.111998 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2490 23:08:53.112653 ==
2491 23:08:53.114969 Dram Type= 6, Freq= 0, CH_0, rank 0
2492 23:08:53.118572 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2493 23:08:53.119134 ==
2494 23:08:53.131130 TX Vref=22, minBit 12, minWin=24, winSum=412
2495 23:08:53.134755 TX Vref=24, minBit 10, minWin=25, winSum=420
2496 23:08:53.138158 TX Vref=26, minBit 10, minWin=25, winSum=429
2497 23:08:53.141244 TX Vref=28, minBit 8, minWin=26, winSum=432
2498 23:08:53.144491 TX Vref=30, minBit 10, minWin=26, winSum=432
2499 23:08:53.151082 TX Vref=32, minBit 8, minWin=26, winSum=433
2500 23:08:53.154691 [TxChooseVref] Worse bit 8, Min win 26, Win sum 433, Final Vref 32
2501 23:08:53.155261
2502 23:08:53.157868 Final TX Range 1 Vref 32
2503 23:08:53.158436
2504 23:08:53.158810 ==
2505 23:08:53.161475 Dram Type= 6, Freq= 0, CH_0, rank 0
2506 23:08:53.164463 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2507 23:08:53.167807 ==
2508 23:08:53.168367
2509 23:08:53.168804
2510 23:08:53.169153 TX Vref Scan disable
2511 23:08:53.171161 == TX Byte 0 ==
2512 23:08:53.174409 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2513 23:08:53.177916 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2514 23:08:53.181516 == TX Byte 1 ==
2515 23:08:53.184697 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2516 23:08:53.188138 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2517 23:08:53.191278
2518 23:08:53.191835 [DATLAT]
2519 23:08:53.192209 Freq=1200, CH0 RK0
2520 23:08:53.192633
2521 23:08:53.194668 DATLAT Default: 0xd
2522 23:08:53.195227 0, 0xFFFF, sum = 0
2523 23:08:53.197973 1, 0xFFFF, sum = 0
2524 23:08:53.198449 2, 0xFFFF, sum = 0
2525 23:08:53.201284 3, 0xFFFF, sum = 0
2526 23:08:53.201758 4, 0xFFFF, sum = 0
2527 23:08:53.204422 5, 0xFFFF, sum = 0
2528 23:08:53.204974 6, 0xFFFF, sum = 0
2529 23:08:53.207783 7, 0xFFFF, sum = 0
2530 23:08:53.211636 8, 0xFFFF, sum = 0
2531 23:08:53.212207 9, 0xFFFF, sum = 0
2532 23:08:53.214472 10, 0xFFFF, sum = 0
2533 23:08:53.215019 11, 0x0, sum = 1
2534 23:08:53.215575 12, 0x0, sum = 2
2535 23:08:53.218280 13, 0x0, sum = 3
2536 23:08:53.218841 14, 0x0, sum = 4
2537 23:08:53.221544 best_step = 12
2538 23:08:53.222152
2539 23:08:53.222528 ==
2540 23:08:53.224542 Dram Type= 6, Freq= 0, CH_0, rank 0
2541 23:08:53.228022 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2542 23:08:53.228647 ==
2543 23:08:53.231410 RX Vref Scan: 1
2544 23:08:53.231966
2545 23:08:53.232335 Set Vref Range= 32 -> 127
2546 23:08:53.234804
2547 23:08:53.235362 RX Vref 32 -> 127, step: 1
2548 23:08:53.235735
2549 23:08:53.238107 RX Delay -21 -> 252, step: 4
2550 23:08:53.238663
2551 23:08:53.241407 Set Vref, RX VrefLevel [Byte0]: 32
2552 23:08:53.244673 [Byte1]: 32
2553 23:08:53.248028
2554 23:08:53.248626 Set Vref, RX VrefLevel [Byte0]: 33
2555 23:08:53.251210 [Byte1]: 33
2556 23:08:53.255863
2557 23:08:53.256419 Set Vref, RX VrefLevel [Byte0]: 34
2558 23:08:53.258905 [Byte1]: 34
2559 23:08:53.263788
2560 23:08:53.264342 Set Vref, RX VrefLevel [Byte0]: 35
2561 23:08:53.267256 [Byte1]: 35
2562 23:08:53.271849
2563 23:08:53.272405 Set Vref, RX VrefLevel [Byte0]: 36
2564 23:08:53.274936 [Byte1]: 36
2565 23:08:53.279853
2566 23:08:53.280410 Set Vref, RX VrefLevel [Byte0]: 37
2567 23:08:53.283347 [Byte1]: 37
2568 23:08:53.287618
2569 23:08:53.288174 Set Vref, RX VrefLevel [Byte0]: 38
2570 23:08:53.291233 [Byte1]: 38
2571 23:08:53.295593
2572 23:08:53.296152 Set Vref, RX VrefLevel [Byte0]: 39
2573 23:08:53.298681 [Byte1]: 39
2574 23:08:53.303536
2575 23:08:53.304092 Set Vref, RX VrefLevel [Byte0]: 40
2576 23:08:53.306715 [Byte1]: 40
2577 23:08:53.311441
2578 23:08:53.312001 Set Vref, RX VrefLevel [Byte0]: 41
2579 23:08:53.314374 [Byte1]: 41
2580 23:08:53.319491
2581 23:08:53.320051 Set Vref, RX VrefLevel [Byte0]: 42
2582 23:08:53.322643 [Byte1]: 42
2583 23:08:53.327287
2584 23:08:53.327845 Set Vref, RX VrefLevel [Byte0]: 43
2585 23:08:53.330441 [Byte1]: 43
2586 23:08:53.335171
2587 23:08:53.335893 Set Vref, RX VrefLevel [Byte0]: 44
2588 23:08:53.338339 [Byte1]: 44
2589 23:08:53.343182
2590 23:08:53.343739 Set Vref, RX VrefLevel [Byte0]: 45
2591 23:08:53.346502 [Byte1]: 45
2592 23:08:53.351168
2593 23:08:53.351723 Set Vref, RX VrefLevel [Byte0]: 46
2594 23:08:53.354123 [Byte1]: 46
2595 23:08:53.358825
2596 23:08:53.359382 Set Vref, RX VrefLevel [Byte0]: 47
2597 23:08:53.362317 [Byte1]: 47
2598 23:08:53.366659
2599 23:08:53.367215 Set Vref, RX VrefLevel [Byte0]: 48
2600 23:08:53.370420 [Byte1]: 48
2601 23:08:53.375073
2602 23:08:53.375632 Set Vref, RX VrefLevel [Byte0]: 49
2603 23:08:53.377887 [Byte1]: 49
2604 23:08:53.383010
2605 23:08:53.383568 Set Vref, RX VrefLevel [Byte0]: 50
2606 23:08:53.385660 [Byte1]: 50
2607 23:08:53.390693
2608 23:08:53.391254 Set Vref, RX VrefLevel [Byte0]: 51
2609 23:08:53.393921 [Byte1]: 51
2610 23:08:53.398580
2611 23:08:53.399135 Set Vref, RX VrefLevel [Byte0]: 52
2612 23:08:53.401497 [Byte1]: 52
2613 23:08:53.406283
2614 23:08:53.406748 Set Vref, RX VrefLevel [Byte0]: 53
2615 23:08:53.409396 [Byte1]: 53
2616 23:08:53.414845
2617 23:08:53.415654 Set Vref, RX VrefLevel [Byte0]: 54
2618 23:08:53.417296 [Byte1]: 54
2619 23:08:53.422366
2620 23:08:53.422931 Set Vref, RX VrefLevel [Byte0]: 55
2621 23:08:53.425368 [Byte1]: 55
2622 23:08:53.430343
2623 23:08:53.430901 Set Vref, RX VrefLevel [Byte0]: 56
2624 23:08:53.433240 [Byte1]: 56
2625 23:08:53.438306
2626 23:08:53.438869 Set Vref, RX VrefLevel [Byte0]: 57
2627 23:08:53.441295 [Byte1]: 57
2628 23:08:53.446390
2629 23:08:53.446946 Set Vref, RX VrefLevel [Byte0]: 58
2630 23:08:53.449218 [Byte1]: 58
2631 23:08:53.453995
2632 23:08:53.454497 Set Vref, RX VrefLevel [Byte0]: 59
2633 23:08:53.457155 [Byte1]: 59
2634 23:08:53.461942
2635 23:08:53.462501 Set Vref, RX VrefLevel [Byte0]: 60
2636 23:08:53.465198 [Byte1]: 60
2637 23:08:53.469974
2638 23:08:53.470529 Set Vref, RX VrefLevel [Byte0]: 61
2639 23:08:53.473106 [Byte1]: 61
2640 23:08:53.477560
2641 23:08:53.478121 Set Vref, RX VrefLevel [Byte0]: 62
2642 23:08:53.481108 [Byte1]: 62
2643 23:08:53.485508
2644 23:08:53.486061 Set Vref, RX VrefLevel [Byte0]: 63
2645 23:08:53.489081 [Byte1]: 63
2646 23:08:53.494015
2647 23:08:53.494573 Set Vref, RX VrefLevel [Byte0]: 64
2648 23:08:53.496868 [Byte1]: 64
2649 23:08:53.501909
2650 23:08:53.502468 Set Vref, RX VrefLevel [Byte0]: 65
2651 23:08:53.504478 [Byte1]: 65
2652 23:08:53.509210
2653 23:08:53.509687 Set Vref, RX VrefLevel [Byte0]: 66
2654 23:08:53.512906 [Byte1]: 66
2655 23:08:53.517428
2656 23:08:53.517921 Final RX Vref Byte 0 = 47 to rank0
2657 23:08:53.520502 Final RX Vref Byte 1 = 48 to rank0
2658 23:08:53.523851 Final RX Vref Byte 0 = 47 to rank1
2659 23:08:53.527576 Final RX Vref Byte 1 = 48 to rank1==
2660 23:08:53.531080 Dram Type= 6, Freq= 0, CH_0, rank 0
2661 23:08:53.537543 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2662 23:08:53.538107 ==
2663 23:08:53.538501 DQS Delay:
2664 23:08:53.538847 DQS0 = 0, DQS1 = 0
2665 23:08:53.540696 DQM Delay:
2666 23:08:53.541164 DQM0 = 114, DQM1 = 105
2667 23:08:53.544357 DQ Delay:
2668 23:08:53.547533 DQ0 =110, DQ1 =114, DQ2 =112, DQ3 =108
2669 23:08:53.550818 DQ4 =118, DQ5 =108, DQ6 =124, DQ7 =120
2670 23:08:53.554298 DQ8 =94, DQ9 =86, DQ10 =106, DQ11 =96
2671 23:08:53.557454 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =116
2672 23:08:53.558017
2673 23:08:53.558389
2674 23:08:53.564203 [DQSOSCAuto] RK0, (LSB)MR18= 0x707, (MSB)MR19= 0x404, tDQSOscB0 = 407 ps tDQSOscB1 = 407 ps
2675 23:08:53.567533 CH0 RK0: MR19=404, MR18=707
2676 23:08:53.574182 CH0_RK0: MR19=0x404, MR18=0x707, DQSOSC=407, MR23=63, INC=39, DEC=26
2677 23:08:53.574747
2678 23:08:53.577428 ----->DramcWriteLeveling(PI) begin...
2679 23:08:53.577998 ==
2680 23:08:53.580495 Dram Type= 6, Freq= 0, CH_0, rank 1
2681 23:08:53.584124 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2682 23:08:53.584740 ==
2683 23:08:53.587461 Write leveling (Byte 0): 27 => 27
2684 23:08:53.590813 Write leveling (Byte 1): 24 => 24
2685 23:08:53.594735 DramcWriteLeveling(PI) end<-----
2686 23:08:53.595290
2687 23:08:53.595658 ==
2688 23:08:53.597287 Dram Type= 6, Freq= 0, CH_0, rank 1
2689 23:08:53.600786 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2690 23:08:53.603952 ==
2691 23:08:53.604433 [Gating] SW mode calibration
2692 23:08:53.610888 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2693 23:08:53.617103 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2694 23:08:53.621065 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2695 23:08:53.627931 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2696 23:08:53.630590 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2697 23:08:53.634083 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2698 23:08:53.640392 0 11 16 | B1->B0 | 3434 3333 | 1 1 | (1 0) (1 0)
2699 23:08:53.643976 0 11 20 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (0 0)
2700 23:08:53.647245 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2701 23:08:53.653645 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2702 23:08:53.657458 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2703 23:08:53.660953 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2704 23:08:53.667561 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2705 23:08:53.670704 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2706 23:08:53.673962 0 12 16 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
2707 23:08:53.677453 0 12 20 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
2708 23:08:53.684320 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2709 23:08:53.687141 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2710 23:08:53.691051 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2711 23:08:53.697278 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2712 23:08:53.700773 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2713 23:08:53.703982 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2714 23:08:53.710181 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2715 23:08:53.713426 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2716 23:08:53.717113 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2717 23:08:53.723588 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2718 23:08:53.726994 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2719 23:08:53.730167 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2720 23:08:53.736624 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2721 23:08:53.740168 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2722 23:08:53.743428 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2723 23:08:53.750202 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2724 23:08:53.753314 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2725 23:08:53.756812 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2726 23:08:53.763830 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2727 23:08:53.766910 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2728 23:08:53.770332 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2729 23:08:53.776822 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2730 23:08:53.780259 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2731 23:08:53.783900 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2732 23:08:53.790600 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2733 23:08:53.791159 Total UI for P1: 0, mck2ui 16
2734 23:08:53.793495 best dqsien dly found for B0: ( 0, 15, 18)
2735 23:08:53.796637 Total UI for P1: 0, mck2ui 16
2736 23:08:53.800275 best dqsien dly found for B1: ( 0, 15, 18)
2737 23:08:53.806717 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2738 23:08:53.810026 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2739 23:08:53.810487
2740 23:08:53.813468 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2741 23:08:53.817155 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
2742 23:08:53.820126 [Gating] SW calibration Done
2743 23:08:53.820718 ==
2744 23:08:53.823627 Dram Type= 6, Freq= 0, CH_0, rank 1
2745 23:08:53.826490 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2746 23:08:53.826953 ==
2747 23:08:53.830000 RX Vref Scan: 0
2748 23:08:53.830546
2749 23:08:53.830921 RX Vref 0 -> 0, step: 1
2750 23:08:53.831264
2751 23:08:53.833321 RX Delay -40 -> 252, step: 8
2752 23:08:53.836394 iDelay=200, Bit 0, Center 107 (32 ~ 183) 152
2753 23:08:53.843337 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2754 23:08:53.846940 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2755 23:08:53.849907 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2756 23:08:53.853443 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2757 23:08:53.857121 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2758 23:08:53.859963 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2759 23:08:53.866684 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2760 23:08:53.870415 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2761 23:08:53.873210 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2762 23:08:53.876862 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2763 23:08:53.880175 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2764 23:08:53.886765 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2765 23:08:53.889860 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2766 23:08:53.893499 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2767 23:08:53.896811 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2768 23:08:53.897367 ==
2769 23:08:53.899852 Dram Type= 6, Freq= 0, CH_0, rank 1
2770 23:08:53.906548 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2771 23:08:53.907118 ==
2772 23:08:53.907492 DQS Delay:
2773 23:08:53.909682 DQS0 = 0, DQS1 = 0
2774 23:08:53.910141 DQM Delay:
2775 23:08:53.910505 DQM0 = 114, DQM1 = 107
2776 23:08:53.913692 DQ Delay:
2777 23:08:53.916705 DQ0 =107, DQ1 =115, DQ2 =115, DQ3 =111
2778 23:08:53.919754 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2779 23:08:53.923186 DQ8 =91, DQ9 =95, DQ10 =111, DQ11 =99
2780 23:08:53.926602 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115
2781 23:08:53.927166
2782 23:08:53.927535
2783 23:08:53.927873 ==
2784 23:08:53.929635 Dram Type= 6, Freq= 0, CH_0, rank 1
2785 23:08:53.933327 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2786 23:08:53.936490 ==
2787 23:08:53.937081
2788 23:08:53.937446
2789 23:08:53.937782 TX Vref Scan disable
2790 23:08:53.940082 == TX Byte 0 ==
2791 23:08:53.943206 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2792 23:08:53.946647 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2793 23:08:53.949551 == TX Byte 1 ==
2794 23:08:53.953393 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2795 23:08:53.956655 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2796 23:08:53.957116 ==
2797 23:08:53.960074 Dram Type= 6, Freq= 0, CH_0, rank 1
2798 23:08:53.966362 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2799 23:08:53.966938 ==
2800 23:08:53.977280 TX Vref=22, minBit 8, minWin=24, winSum=412
2801 23:08:53.980707 TX Vref=24, minBit 8, minWin=25, winSum=419
2802 23:08:53.984058 TX Vref=26, minBit 8, minWin=25, winSum=426
2803 23:08:53.987434 TX Vref=28, minBit 8, minWin=26, winSum=429
2804 23:08:53.990289 TX Vref=30, minBit 8, minWin=26, winSum=432
2805 23:08:53.997200 TX Vref=32, minBit 8, minWin=25, winSum=430
2806 23:08:54.000190 [TxChooseVref] Worse bit 8, Min win 26, Win sum 432, Final Vref 30
2807 23:08:54.000717
2808 23:08:54.003859 Final TX Range 1 Vref 30
2809 23:08:54.004430
2810 23:08:54.005034 ==
2811 23:08:54.007264 Dram Type= 6, Freq= 0, CH_0, rank 1
2812 23:08:54.010251 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2813 23:08:54.010734 ==
2814 23:08:54.013671
2815 23:08:54.014263
2816 23:08:54.014752 TX Vref Scan disable
2817 23:08:54.017166 == TX Byte 0 ==
2818 23:08:54.020295 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2819 23:08:54.023903 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2820 23:08:54.027111 == TX Byte 1 ==
2821 23:08:54.030799 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
2822 23:08:54.033863 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
2823 23:08:54.037149
2824 23:08:54.037721 [DATLAT]
2825 23:08:54.038209 Freq=1200, CH0 RK1
2826 23:08:54.038663
2827 23:08:54.039925 DATLAT Default: 0xc
2828 23:08:54.040399 0, 0xFFFF, sum = 0
2829 23:08:54.043771 1, 0xFFFF, sum = 0
2830 23:08:54.047158 2, 0xFFFF, sum = 0
2831 23:08:54.047744 3, 0xFFFF, sum = 0
2832 23:08:54.050470 4, 0xFFFF, sum = 0
2833 23:08:54.051055 5, 0xFFFF, sum = 0
2834 23:08:54.053598 6, 0xFFFF, sum = 0
2835 23:08:54.054186 7, 0xFFFF, sum = 0
2836 23:08:54.056629 8, 0xFFFF, sum = 0
2837 23:08:54.057115 9, 0xFFFF, sum = 0
2838 23:08:54.060304 10, 0xFFFF, sum = 0
2839 23:08:54.060944 11, 0x0, sum = 1
2840 23:08:54.063825 12, 0x0, sum = 2
2841 23:08:54.064416 13, 0x0, sum = 3
2842 23:08:54.066599 14, 0x0, sum = 4
2843 23:08:54.067083 best_step = 12
2844 23:08:54.067563
2845 23:08:54.068021 ==
2846 23:08:54.070952 Dram Type= 6, Freq= 0, CH_0, rank 1
2847 23:08:54.073399 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2848 23:08:54.073879 ==
2849 23:08:54.077088 RX Vref Scan: 0
2850 23:08:54.077673
2851 23:08:54.080183 RX Vref 0 -> 0, step: 1
2852 23:08:54.080713
2853 23:08:54.081204 RX Delay -21 -> 252, step: 4
2854 23:08:54.087590 iDelay=195, Bit 0, Center 110 (39 ~ 182) 144
2855 23:08:54.090919 iDelay=195, Bit 1, Center 116 (43 ~ 190) 148
2856 23:08:54.094325 iDelay=195, Bit 2, Center 112 (43 ~ 182) 140
2857 23:08:54.097206 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
2858 23:08:54.100640 iDelay=195, Bit 4, Center 118 (47 ~ 190) 144
2859 23:08:54.107864 iDelay=195, Bit 5, Center 106 (35 ~ 178) 144
2860 23:08:54.111099 iDelay=195, Bit 6, Center 124 (55 ~ 194) 140
2861 23:08:54.114148 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
2862 23:08:54.117706 iDelay=195, Bit 8, Center 92 (31 ~ 154) 124
2863 23:08:54.120554 iDelay=195, Bit 9, Center 90 (27 ~ 154) 128
2864 23:08:54.127857 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
2865 23:08:54.130456 iDelay=195, Bit 11, Center 96 (35 ~ 158) 124
2866 23:08:54.134206 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
2867 23:08:54.137517 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
2868 23:08:54.140697 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
2869 23:08:54.147244 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
2870 23:08:54.147807 ==
2871 23:08:54.150903 Dram Type= 6, Freq= 0, CH_0, rank 1
2872 23:08:54.154106 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2873 23:08:54.154672 ==
2874 23:08:54.155049 DQS Delay:
2875 23:08:54.157003 DQS0 = 0, DQS1 = 0
2876 23:08:54.157469 DQM Delay:
2877 23:08:54.160784 DQM0 = 114, DQM1 = 105
2878 23:08:54.161350 DQ Delay:
2879 23:08:54.163894 DQ0 =110, DQ1 =116, DQ2 =112, DQ3 =108
2880 23:08:54.167369 DQ4 =118, DQ5 =106, DQ6 =124, DQ7 =122
2881 23:08:54.170837 DQ8 =92, DQ9 =90, DQ10 =110, DQ11 =96
2882 23:08:54.174045 DQ12 =112, DQ13 =112, DQ14 =116, DQ15 =114
2883 23:08:54.174611
2884 23:08:54.174983
2885 23:08:54.184045 [DQSOSCAuto] RK1, (LSB)MR18= 0xf0f, (MSB)MR19= 0x404, tDQSOscB0 = 404 ps tDQSOscB1 = 404 ps
2886 23:08:54.187182 CH0 RK1: MR19=404, MR18=F0F
2887 23:08:54.190497 CH0_RK1: MR19=0x404, MR18=0xF0F, DQSOSC=404, MR23=63, INC=40, DEC=26
2888 23:08:54.193675 [RxdqsGatingPostProcess] freq 1200
2889 23:08:54.200161 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2890 23:08:54.203528 Pre-setting of DQS Precalculation
2891 23:08:54.206788 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2892 23:08:54.210390 ==
2893 23:08:54.210966 Dram Type= 6, Freq= 0, CH_1, rank 0
2894 23:08:54.217199 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2895 23:08:54.217775 ==
2896 23:08:54.220180 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2897 23:08:54.226967 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2898 23:08:54.235965 [CA 0] Center 37 (7~68) winsize 62
2899 23:08:54.239673 [CA 1] Center 37 (7~68) winsize 62
2900 23:08:54.242616 [CA 2] Center 34 (4~65) winsize 62
2901 23:08:54.245797 [CA 3] Center 33 (3~64) winsize 62
2902 23:08:54.249335 [CA 4] Center 32 (1~63) winsize 63
2903 23:08:54.252855 [CA 5] Center 32 (1~63) winsize 63
2904 23:08:54.253423
2905 23:08:54.255975 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2906 23:08:54.256622
2907 23:08:54.259131 [CATrainingPosCal] consider 1 rank data
2908 23:08:54.262792 u2DelayCellTimex100 = 270/100 ps
2909 23:08:54.265956 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2910 23:08:54.269339 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2911 23:08:54.275940 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2912 23:08:54.279073 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2913 23:08:54.282360 CA4 delay=32 (1~63),Diff = 0 PI (0 cell)
2914 23:08:54.286083 CA5 delay=32 (1~63),Diff = 0 PI (0 cell)
2915 23:08:54.286644
2916 23:08:54.289224 CA PerBit enable=1, Macro0, CA PI delay=32
2917 23:08:54.289791
2918 23:08:54.292430 [CBTSetCACLKResult] CA Dly = 32
2919 23:08:54.293061 CS Dly: 6 (0~37)
2920 23:08:54.295893 ==
2921 23:08:54.296476 Dram Type= 6, Freq= 0, CH_1, rank 1
2922 23:08:54.302383 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2923 23:08:54.302991 ==
2924 23:08:54.305722 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2925 23:08:54.312399 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2926 23:08:54.321221 [CA 0] Center 37 (7~68) winsize 62
2927 23:08:54.324343 [CA 1] Center 37 (6~68) winsize 63
2928 23:08:54.327793 [CA 2] Center 34 (3~65) winsize 63
2929 23:08:54.331122 [CA 3] Center 33 (3~64) winsize 62
2930 23:08:54.334352 [CA 4] Center 32 (2~63) winsize 62
2931 23:08:54.337239 [CA 5] Center 32 (2~63) winsize 62
2932 23:08:54.337703
2933 23:08:54.341224 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2934 23:08:54.341790
2935 23:08:54.344694 [CATrainingPosCal] consider 2 rank data
2936 23:08:54.347528 u2DelayCellTimex100 = 270/100 ps
2937 23:08:54.350596 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2938 23:08:54.357370 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2939 23:08:54.360883 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2940 23:08:54.364159 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2941 23:08:54.367443 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2942 23:08:54.370886 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2943 23:08:54.371456
2944 23:08:54.374038 CA PerBit enable=1, Macro0, CA PI delay=32
2945 23:08:54.374610
2946 23:08:54.377780 [CBTSetCACLKResult] CA Dly = 32
2947 23:08:54.380483 CS Dly: 6 (0~38)
2948 23:08:54.381100
2949 23:08:54.384112 ----->DramcWriteLeveling(PI) begin...
2950 23:08:54.384796 ==
2951 23:08:54.387079 Dram Type= 6, Freq= 0, CH_1, rank 0
2952 23:08:54.390985 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2953 23:08:54.391556 ==
2954 23:08:54.394151 Write leveling (Byte 0): 22 => 22
2955 23:08:54.397197 Write leveling (Byte 1): 21 => 21
2956 23:08:54.400154 DramcWriteLeveling(PI) end<-----
2957 23:08:54.400783
2958 23:08:54.401184 ==
2959 23:08:54.403769 Dram Type= 6, Freq= 0, CH_1, rank 0
2960 23:08:54.407025 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2961 23:08:54.407494 ==
2962 23:08:54.410190 [Gating] SW mode calibration
2963 23:08:54.416865 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2964 23:08:54.423725 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2965 23:08:54.427082 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2966 23:08:54.430385 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2967 23:08:54.436878 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2968 23:08:54.440181 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2969 23:08:54.443690 0 11 16 | B1->B0 | 3232 2828 | 0 0 | (0 0) (0 1)
2970 23:08:54.450464 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2971 23:08:54.453674 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2972 23:08:54.456962 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2973 23:08:54.463648 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2974 23:08:54.467301 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2975 23:08:54.470160 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2976 23:08:54.476934 0 12 12 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
2977 23:08:54.480451 0 12 16 | B1->B0 | 3131 4444 | 0 0 | (0 0) (0 0)
2978 23:08:54.483564 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2979 23:08:54.490228 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2980 23:08:54.493464 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2981 23:08:54.496777 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2982 23:08:54.499802 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2983 23:08:54.506383 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2984 23:08:54.509815 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2985 23:08:54.513288 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2986 23:08:54.520324 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2987 23:08:54.523422 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2988 23:08:54.526376 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2989 23:08:54.533165 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2990 23:08:54.536251 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2991 23:08:54.540011 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2992 23:08:54.546698 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2993 23:08:54.549838 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2994 23:08:54.552980 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2995 23:08:54.559745 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2996 23:08:54.563451 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2997 23:08:54.566588 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2998 23:08:54.573029 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2999 23:08:54.576646 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3000 23:08:54.579691 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3001 23:08:54.586605 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3002 23:08:54.589517 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3003 23:08:54.592933 Total UI for P1: 0, mck2ui 16
3004 23:08:54.596082 best dqsien dly found for B0: ( 0, 15, 16)
3005 23:08:54.600372 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3006 23:08:54.602721 Total UI for P1: 0, mck2ui 16
3007 23:08:54.605992 best dqsien dly found for B1: ( 0, 15, 20)
3008 23:08:54.609456 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
3009 23:08:54.612638 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
3010 23:08:54.613102
3011 23:08:54.619605 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
3012 23:08:54.622880 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
3013 23:08:54.623359 [Gating] SW calibration Done
3014 23:08:54.626030 ==
3015 23:08:54.629282 Dram Type= 6, Freq= 0, CH_1, rank 0
3016 23:08:54.633038 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3017 23:08:54.633612 ==
3018 23:08:54.633992 RX Vref Scan: 0
3019 23:08:54.634338
3020 23:08:54.636210 RX Vref 0 -> 0, step: 1
3021 23:08:54.636711
3022 23:08:54.639686 RX Delay -40 -> 252, step: 8
3023 23:08:54.642985 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160
3024 23:08:54.646611 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3025 23:08:54.649922 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3026 23:08:54.656068 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3027 23:08:54.660173 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3028 23:08:54.663077 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3029 23:08:54.666482 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3030 23:08:54.669763 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3031 23:08:54.676670 iDelay=208, Bit 8, Center 87 (16 ~ 159) 144
3032 23:08:54.679968 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144
3033 23:08:54.683340 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3034 23:08:54.686219 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3035 23:08:54.690064 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3036 23:08:54.696646 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3037 23:08:54.699620 iDelay=208, Bit 14, Center 115 (48 ~ 183) 136
3038 23:08:54.703436 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3039 23:08:54.704005 ==
3040 23:08:54.706237 Dram Type= 6, Freq= 0, CH_1, rank 0
3041 23:08:54.709475 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3042 23:08:54.709939 ==
3043 23:08:54.713691 DQS Delay:
3044 23:08:54.714255 DQS0 = 0, DQS1 = 0
3045 23:08:54.714631 DQM Delay:
3046 23:08:54.716057 DQM0 = 116, DQM1 = 108
3047 23:08:54.716568 DQ Delay:
3048 23:08:54.719992 DQ0 =119, DQ1 =111, DQ2 =107, DQ3 =115
3049 23:08:54.722756 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3050 23:08:54.726330 DQ8 =87, DQ9 =95, DQ10 =111, DQ11 =99
3051 23:08:54.732953 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3052 23:08:54.733534
3053 23:08:54.734021
3054 23:08:54.734527 ==
3055 23:08:54.736325 Dram Type= 6, Freq= 0, CH_1, rank 0
3056 23:08:54.739947 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3057 23:08:54.740572 ==
3058 23:08:54.741072
3059 23:08:54.741525
3060 23:08:54.742854 TX Vref Scan disable
3061 23:08:54.743326 == TX Byte 0 ==
3062 23:08:54.749603 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3063 23:08:54.752901 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3064 23:08:54.753478 == TX Byte 1 ==
3065 23:08:54.759497 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3066 23:08:54.763065 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3067 23:08:54.763644 ==
3068 23:08:54.766722 Dram Type= 6, Freq= 0, CH_1, rank 0
3069 23:08:54.769659 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3070 23:08:54.770238 ==
3071 23:08:54.782209 TX Vref=22, minBit 9, minWin=25, winSum=418
3072 23:08:54.785446 TX Vref=24, minBit 9, minWin=25, winSum=420
3073 23:08:54.789110 TX Vref=26, minBit 0, minWin=26, winSum=433
3074 23:08:54.792070 TX Vref=28, minBit 9, minWin=25, winSum=430
3075 23:08:54.795477 TX Vref=30, minBit 8, minWin=26, winSum=436
3076 23:08:54.802036 TX Vref=32, minBit 9, minWin=26, winSum=433
3077 23:08:54.805531 [TxChooseVref] Worse bit 8, Min win 26, Win sum 436, Final Vref 30
3078 23:08:54.806118
3079 23:08:54.808934 Final TX Range 1 Vref 30
3080 23:08:54.809398
3081 23:08:54.809768 ==
3082 23:08:54.812205 Dram Type= 6, Freq= 0, CH_1, rank 0
3083 23:08:54.815860 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3084 23:08:54.816426 ==
3085 23:08:54.816865
3086 23:08:54.818941
3087 23:08:54.819508 TX Vref Scan disable
3088 23:08:54.821983 == TX Byte 0 ==
3089 23:08:54.825327 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3090 23:08:54.828834 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3091 23:08:54.832354 == TX Byte 1 ==
3092 23:08:54.835600 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3093 23:08:54.838960 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3094 23:08:54.839516
3095 23:08:54.841982 [DATLAT]
3096 23:08:54.842441 Freq=1200, CH1 RK0
3097 23:08:54.842809
3098 23:08:54.845283 DATLAT Default: 0xd
3099 23:08:54.845792 0, 0xFFFF, sum = 0
3100 23:08:54.848726 1, 0xFFFF, sum = 0
3101 23:08:54.849198 2, 0xFFFF, sum = 0
3102 23:08:54.852405 3, 0xFFFF, sum = 0
3103 23:08:54.853029 4, 0xFFFF, sum = 0
3104 23:08:54.855458 5, 0xFFFF, sum = 0
3105 23:08:54.856015 6, 0xFFFF, sum = 0
3106 23:08:54.859067 7, 0xFFFF, sum = 0
3107 23:08:54.859643 8, 0xFFFF, sum = 0
3108 23:08:54.862065 9, 0xFFFF, sum = 0
3109 23:08:54.865458 10, 0xFFFF, sum = 0
3110 23:08:54.866030 11, 0x0, sum = 1
3111 23:08:54.866411 12, 0x0, sum = 2
3112 23:08:54.868885 13, 0x0, sum = 3
3113 23:08:54.869494 14, 0x0, sum = 4
3114 23:08:54.872290 best_step = 12
3115 23:08:54.872916
3116 23:08:54.873287 ==
3117 23:08:54.875301 Dram Type= 6, Freq= 0, CH_1, rank 0
3118 23:08:54.878932 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3119 23:08:54.879546 ==
3120 23:08:54.882360 RX Vref Scan: 1
3121 23:08:54.882822
3122 23:08:54.883224 Set Vref Range= 32 -> 127
3123 23:08:54.883582
3124 23:08:54.885190 RX Vref 32 -> 127, step: 1
3125 23:08:54.885689
3126 23:08:54.888893 RX Delay -29 -> 252, step: 4
3127 23:08:54.889460
3128 23:08:54.892452 Set Vref, RX VrefLevel [Byte0]: 32
3129 23:08:54.895653 [Byte1]: 32
3130 23:08:54.896235
3131 23:08:54.898548 Set Vref, RX VrefLevel [Byte0]: 33
3132 23:08:54.901931 [Byte1]: 33
3133 23:08:54.906327
3134 23:08:54.906792 Set Vref, RX VrefLevel [Byte0]: 34
3135 23:08:54.910317 [Byte1]: 34
3136 23:08:54.914922
3137 23:08:54.915486 Set Vref, RX VrefLevel [Byte0]: 35
3138 23:08:54.917863 [Byte1]: 35
3139 23:08:54.922709
3140 23:08:54.923349 Set Vref, RX VrefLevel [Byte0]: 36
3141 23:08:54.925838 [Byte1]: 36
3142 23:08:54.930432
3143 23:08:54.930998 Set Vref, RX VrefLevel [Byte0]: 37
3144 23:08:54.933521 [Byte1]: 37
3145 23:08:54.938378
3146 23:08:54.938945 Set Vref, RX VrefLevel [Byte0]: 38
3147 23:08:54.941886 [Byte1]: 38
3148 23:08:54.946305
3149 23:08:54.946797 Set Vref, RX VrefLevel [Byte0]: 39
3150 23:08:54.949707 [Byte1]: 39
3151 23:08:54.954340
3152 23:08:54.954905 Set Vref, RX VrefLevel [Byte0]: 40
3153 23:08:54.957824 [Byte1]: 40
3154 23:08:54.962338
3155 23:08:54.962899 Set Vref, RX VrefLevel [Byte0]: 41
3156 23:08:54.965688 [Byte1]: 41
3157 23:08:54.970255
3158 23:08:54.970822 Set Vref, RX VrefLevel [Byte0]: 42
3159 23:08:54.973482 [Byte1]: 42
3160 23:08:54.978437
3161 23:08:54.979002 Set Vref, RX VrefLevel [Byte0]: 43
3162 23:08:54.981245 [Byte1]: 43
3163 23:08:54.986179
3164 23:08:54.986742 Set Vref, RX VrefLevel [Byte0]: 44
3165 23:08:54.989765 [Byte1]: 44
3166 23:08:54.994213
3167 23:08:54.994801 Set Vref, RX VrefLevel [Byte0]: 45
3168 23:08:54.997179 [Byte1]: 45
3169 23:08:55.001882
3170 23:08:55.002517 Set Vref, RX VrefLevel [Byte0]: 46
3171 23:08:55.005298 [Byte1]: 46
3172 23:08:55.009849
3173 23:08:55.010309 Set Vref, RX VrefLevel [Byte0]: 47
3174 23:08:55.013607 [Byte1]: 47
3175 23:08:55.018108
3176 23:08:55.018670 Set Vref, RX VrefLevel [Byte0]: 48
3177 23:08:55.021311 [Byte1]: 48
3178 23:08:55.026028
3179 23:08:55.026599 Set Vref, RX VrefLevel [Byte0]: 49
3180 23:08:55.028932 [Byte1]: 49
3181 23:08:55.034173
3182 23:08:55.034737 Set Vref, RX VrefLevel [Byte0]: 50
3183 23:08:55.037115 [Byte1]: 50
3184 23:08:55.041867
3185 23:08:55.042448 Set Vref, RX VrefLevel [Byte0]: 51
3186 23:08:55.045277 [Byte1]: 51
3187 23:08:55.049763
3188 23:08:55.050325 Set Vref, RX VrefLevel [Byte0]: 52
3189 23:08:55.052835 [Byte1]: 52
3190 23:08:55.058102
3191 23:08:55.058740 Set Vref, RX VrefLevel [Byte0]: 53
3192 23:08:55.064304 [Byte1]: 53
3193 23:08:55.064928
3194 23:08:55.067849 Set Vref, RX VrefLevel [Byte0]: 54
3195 23:08:55.070827 [Byte1]: 54
3196 23:08:55.071397
3197 23:08:55.074218 Set Vref, RX VrefLevel [Byte0]: 55
3198 23:08:55.077405 [Byte1]: 55
3199 23:08:55.081699
3200 23:08:55.082262 Set Vref, RX VrefLevel [Byte0]: 56
3201 23:08:55.085146 [Byte1]: 56
3202 23:08:55.089477
3203 23:08:55.090045 Set Vref, RX VrefLevel [Byte0]: 57
3204 23:08:55.093227 [Byte1]: 57
3205 23:08:55.097666
3206 23:08:55.098226 Set Vref, RX VrefLevel [Byte0]: 58
3207 23:08:55.100617 [Byte1]: 58
3208 23:08:55.105469
3209 23:08:55.106069 Set Vref, RX VrefLevel [Byte0]: 59
3210 23:08:55.108639 [Byte1]: 59
3211 23:08:55.113388
3212 23:08:55.113950 Set Vref, RX VrefLevel [Byte0]: 60
3213 23:08:55.116826 [Byte1]: 60
3214 23:08:55.121343
3215 23:08:55.122123 Set Vref, RX VrefLevel [Byte0]: 61
3216 23:08:55.124438 [Byte1]: 61
3217 23:08:55.129078
3218 23:08:55.129541 Set Vref, RX VrefLevel [Byte0]: 62
3219 23:08:55.132695 [Byte1]: 62
3220 23:08:55.137355
3221 23:08:55.137920 Set Vref, RX VrefLevel [Byte0]: 63
3222 23:08:55.140431 [Byte1]: 63
3223 23:08:55.145425
3224 23:08:55.145985 Set Vref, RX VrefLevel [Byte0]: 64
3225 23:08:55.148469 [Byte1]: 64
3226 23:08:55.153380
3227 23:08:55.153946 Set Vref, RX VrefLevel [Byte0]: 65
3228 23:08:55.156470 [Byte1]: 65
3229 23:08:55.161372
3230 23:08:55.161934 Set Vref, RX VrefLevel [Byte0]: 66
3231 23:08:55.164586 [Byte1]: 66
3232 23:08:55.169348
3233 23:08:55.169910 Set Vref, RX VrefLevel [Byte0]: 67
3234 23:08:55.172688 [Byte1]: 67
3235 23:08:55.177005
3236 23:08:55.177751 Final RX Vref Byte 0 = 55 to rank0
3237 23:08:55.180482 Final RX Vref Byte 1 = 48 to rank0
3238 23:08:55.183919 Final RX Vref Byte 0 = 55 to rank1
3239 23:08:55.187069 Final RX Vref Byte 1 = 48 to rank1==
3240 23:08:55.190693 Dram Type= 6, Freq= 0, CH_1, rank 0
3241 23:08:55.197406 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3242 23:08:55.197972 ==
3243 23:08:55.198347 DQS Delay:
3244 23:08:55.198690 DQS0 = 0, DQS1 = 0
3245 23:08:55.200276 DQM Delay:
3246 23:08:55.200793 DQM0 = 115, DQM1 = 105
3247 23:08:55.203685 DQ Delay:
3248 23:08:55.207088 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =114
3249 23:08:55.210145 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =114
3250 23:08:55.213708 DQ8 =86, DQ9 =94, DQ10 =108, DQ11 =98
3251 23:08:55.217497 DQ12 =112, DQ13 =116, DQ14 =116, DQ15 =114
3252 23:08:55.218068
3253 23:08:55.218433
3254 23:08:55.223929 [DQSOSCAuto] RK0, (LSB)MR18= 0x1919, (MSB)MR19= 0x404, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
3255 23:08:55.226775 CH1 RK0: MR19=404, MR18=1919
3256 23:08:55.233621 CH1_RK0: MR19=0x404, MR18=0x1919, DQSOSC=400, MR23=63, INC=40, DEC=27
3257 23:08:55.234132
3258 23:08:55.236853 ----->DramcWriteLeveling(PI) begin...
3259 23:08:55.237328 ==
3260 23:08:55.240312 Dram Type= 6, Freq= 0, CH_1, rank 1
3261 23:08:55.243978 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3262 23:08:55.246881 ==
3263 23:08:55.247346 Write leveling (Byte 0): 20 => 20
3264 23:08:55.250335 Write leveling (Byte 1): 24 => 24
3265 23:08:55.253694 DramcWriteLeveling(PI) end<-----
3266 23:08:55.254261
3267 23:08:55.254628 ==
3268 23:08:55.256689 Dram Type= 6, Freq= 0, CH_1, rank 1
3269 23:08:55.263837 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3270 23:08:55.264405 ==
3271 23:08:55.264852 [Gating] SW mode calibration
3272 23:08:55.273599 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3273 23:08:55.277639 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3274 23:08:55.280413 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3275 23:08:55.287099 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3276 23:08:55.290702 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3277 23:08:55.293585 0 11 12 | B1->B0 | 3434 2b2b | 1 1 | (1 1) (1 1)
3278 23:08:55.300080 0 11 16 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
3279 23:08:55.303408 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3280 23:08:55.306847 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3281 23:08:55.313564 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3282 23:08:55.317210 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3283 23:08:55.320324 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3284 23:08:55.326838 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3285 23:08:55.330388 0 12 12 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
3286 23:08:55.333422 0 12 16 | B1->B0 | 3737 4646 | 1 0 | (0 0) (0 0)
3287 23:08:55.340216 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3288 23:08:55.343797 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3289 23:08:55.346886 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3290 23:08:55.353447 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3291 23:08:55.357153 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3292 23:08:55.360134 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3293 23:08:55.363429 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3294 23:08:55.369994 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3295 23:08:55.373682 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3296 23:08:55.376910 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3297 23:08:55.383840 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3298 23:08:55.386992 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3299 23:08:55.390237 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3300 23:08:55.396887 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3301 23:08:55.400301 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3302 23:08:55.403529 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3303 23:08:55.410062 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3304 23:08:55.413348 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3305 23:08:55.416609 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3306 23:08:55.423596 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3307 23:08:55.426755 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3308 23:08:55.430314 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3309 23:08:55.437360 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3310 23:08:55.440366 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3311 23:08:55.443886 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3312 23:08:55.447052 Total UI for P1: 0, mck2ui 16
3313 23:08:55.450324 best dqsien dly found for B0: ( 0, 15, 14)
3314 23:08:55.453449 Total UI for P1: 0, mck2ui 16
3315 23:08:55.457123 best dqsien dly found for B1: ( 0, 15, 14)
3316 23:08:55.460548 best DQS0 dly(MCK, UI, PI) = (0, 15, 14)
3317 23:08:55.463843 best DQS1 dly(MCK, UI, PI) = (0, 15, 14)
3318 23:08:55.464398
3319 23:08:55.467402 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 14)
3320 23:08:55.473582 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 14)
3321 23:08:55.474145 [Gating] SW calibration Done
3322 23:08:55.474521 ==
3323 23:08:55.477219 Dram Type= 6, Freq= 0, CH_1, rank 1
3324 23:08:55.483579 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3325 23:08:55.484140 ==
3326 23:08:55.484561 RX Vref Scan: 0
3327 23:08:55.484922
3328 23:08:55.486958 RX Vref 0 -> 0, step: 1
3329 23:08:55.487523
3330 23:08:55.490179 RX Delay -40 -> 252, step: 8
3331 23:08:55.493475 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3332 23:08:55.496810 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3333 23:08:55.500083 iDelay=200, Bit 2, Center 107 (32 ~ 183) 152
3334 23:08:55.507017 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3335 23:08:55.510190 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3336 23:08:55.513598 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3337 23:08:55.517064 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3338 23:08:55.520456 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3339 23:08:55.523850 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
3340 23:08:55.530271 iDelay=200, Bit 9, Center 87 (16 ~ 159) 144
3341 23:08:55.533309 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3342 23:08:55.537011 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3343 23:08:55.540484 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3344 23:08:55.543583 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3345 23:08:55.550239 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3346 23:08:55.553698 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3347 23:08:55.554256 ==
3348 23:08:55.557152 Dram Type= 6, Freq= 0, CH_1, rank 1
3349 23:08:55.559966 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3350 23:08:55.560426 ==
3351 23:08:55.563536 DQS Delay:
3352 23:08:55.564089 DQS0 = 0, DQS1 = 0
3353 23:08:55.564456 DQM Delay:
3354 23:08:55.567127 DQM0 = 115, DQM1 = 104
3355 23:08:55.567684 DQ Delay:
3356 23:08:55.570489 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115
3357 23:08:55.573667 DQ4 =115, DQ5 =123, DQ6 =123, DQ7 =115
3358 23:08:55.577151 DQ8 =91, DQ9 =87, DQ10 =103, DQ11 =99
3359 23:08:55.584155 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =111
3360 23:08:55.584767
3361 23:08:55.585141
3362 23:08:55.585486 ==
3363 23:08:55.586962 Dram Type= 6, Freq= 0, CH_1, rank 1
3364 23:08:55.590345 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3365 23:08:55.590940 ==
3366 23:08:55.591347
3367 23:08:55.591696
3368 23:08:55.593862 TX Vref Scan disable
3369 23:08:55.594429 == TX Byte 0 ==
3370 23:08:55.600448 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3371 23:08:55.603567 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3372 23:08:55.604035 == TX Byte 1 ==
3373 23:08:55.609976 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3374 23:08:55.613480 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3375 23:08:55.613948 ==
3376 23:08:55.616810 Dram Type= 6, Freq= 0, CH_1, rank 1
3377 23:08:55.620608 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3378 23:08:55.621171 ==
3379 23:08:55.633087 TX Vref=22, minBit 8, minWin=25, winSum=417
3380 23:08:55.636493 TX Vref=24, minBit 9, minWin=25, winSum=425
3381 23:08:55.639608 TX Vref=26, minBit 3, minWin=26, winSum=429
3382 23:08:55.642964 TX Vref=28, minBit 8, minWin=26, winSum=429
3383 23:08:55.646450 TX Vref=30, minBit 8, minWin=26, winSum=430
3384 23:08:55.653192 TX Vref=32, minBit 13, minWin=26, winSum=431
3385 23:08:55.656570 [TxChooseVref] Worse bit 13, Min win 26, Win sum 431, Final Vref 32
3386 23:08:55.657152
3387 23:08:55.659612 Final TX Range 1 Vref 32
3388 23:08:55.660189
3389 23:08:55.660719 ==
3390 23:08:55.662726 Dram Type= 6, Freq= 0, CH_1, rank 1
3391 23:08:55.666424 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3392 23:08:55.670027 ==
3393 23:08:55.670604
3394 23:08:55.671093
3395 23:08:55.671552 TX Vref Scan disable
3396 23:08:55.672812 == TX Byte 0 ==
3397 23:08:55.676240 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3398 23:08:55.679736 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3399 23:08:55.683022 == TX Byte 1 ==
3400 23:08:55.686631 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3401 23:08:55.689853 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3402 23:08:55.693030
3403 23:08:55.693631 [DATLAT]
3404 23:08:55.694014 Freq=1200, CH1 RK1
3405 23:08:55.694370
3406 23:08:55.696248 DATLAT Default: 0xc
3407 23:08:55.696900 0, 0xFFFF, sum = 0
3408 23:08:55.699559 1, 0xFFFF, sum = 0
3409 23:08:55.700128 2, 0xFFFF, sum = 0
3410 23:08:55.702786 3, 0xFFFF, sum = 0
3411 23:08:55.706295 4, 0xFFFF, sum = 0
3412 23:08:55.706861 5, 0xFFFF, sum = 0
3413 23:08:55.709425 6, 0xFFFF, sum = 0
3414 23:08:55.709895 7, 0xFFFF, sum = 0
3415 23:08:55.712675 8, 0xFFFF, sum = 0
3416 23:08:55.713239 9, 0xFFFF, sum = 0
3417 23:08:55.716348 10, 0xFFFF, sum = 0
3418 23:08:55.716978 11, 0x0, sum = 1
3419 23:08:55.719180 12, 0x0, sum = 2
3420 23:08:55.719648 13, 0x0, sum = 3
3421 23:08:55.723183 14, 0x0, sum = 4
3422 23:08:55.723758 best_step = 12
3423 23:08:55.724134
3424 23:08:55.724473 ==
3425 23:08:55.725848 Dram Type= 6, Freq= 0, CH_1, rank 1
3426 23:08:55.729581 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3427 23:08:55.730047 ==
3428 23:08:55.732680 RX Vref Scan: 0
3429 23:08:55.733145
3430 23:08:55.735694 RX Vref 0 -> 0, step: 1
3431 23:08:55.736156
3432 23:08:55.736576 RX Delay -29 -> 252, step: 4
3433 23:08:55.743542 iDelay=199, Bit 0, Center 116 (47 ~ 186) 140
3434 23:08:55.746968 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3435 23:08:55.749937 iDelay=199, Bit 2, Center 108 (39 ~ 178) 140
3436 23:08:55.753185 iDelay=199, Bit 3, Center 112 (43 ~ 182) 140
3437 23:08:55.756424 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3438 23:08:55.763407 iDelay=199, Bit 5, Center 124 (51 ~ 198) 148
3439 23:08:55.766668 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
3440 23:08:55.770176 iDelay=199, Bit 7, Center 112 (43 ~ 182) 140
3441 23:08:55.773383 iDelay=199, Bit 8, Center 86 (19 ~ 154) 136
3442 23:08:55.776622 iDelay=199, Bit 9, Center 92 (27 ~ 158) 132
3443 23:08:55.783341 iDelay=199, Bit 10, Center 106 (39 ~ 174) 136
3444 23:08:55.786912 iDelay=199, Bit 11, Center 96 (31 ~ 162) 132
3445 23:08:55.789950 iDelay=199, Bit 12, Center 112 (43 ~ 182) 140
3446 23:08:55.793460 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
3447 23:08:55.796858 iDelay=199, Bit 14, Center 114 (47 ~ 182) 136
3448 23:08:55.803204 iDelay=199, Bit 15, Center 112 (47 ~ 178) 132
3449 23:08:55.803752 ==
3450 23:08:55.806439 Dram Type= 6, Freq= 0, CH_1, rank 1
3451 23:08:55.809836 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3452 23:08:55.810416 ==
3453 23:08:55.810799 DQS Delay:
3454 23:08:55.813330 DQS0 = 0, DQS1 = 0
3455 23:08:55.813897 DQM Delay:
3456 23:08:55.816960 DQM0 = 115, DQM1 = 103
3457 23:08:55.817526 DQ Delay:
3458 23:08:55.819731 DQ0 =116, DQ1 =110, DQ2 =108, DQ3 =112
3459 23:08:55.823131 DQ4 =116, DQ5 =124, DQ6 =122, DQ7 =112
3460 23:08:55.826641 DQ8 =86, DQ9 =92, DQ10 =106, DQ11 =96
3461 23:08:55.829903 DQ12 =112, DQ13 =112, DQ14 =114, DQ15 =112
3462 23:08:55.830370
3463 23:08:55.830734
3464 23:08:55.839832 [DQSOSCAuto] RK1, (LSB)MR18= 0x606, (MSB)MR19= 0x404, tDQSOscB0 = 407 ps tDQSOscB1 = 407 ps
3465 23:08:55.843435 CH1 RK1: MR19=404, MR18=606
3466 23:08:55.846691 CH1_RK1: MR19=0x404, MR18=0x606, DQSOSC=407, MR23=63, INC=39, DEC=26
3467 23:08:55.849805 [RxdqsGatingPostProcess] freq 1200
3468 23:08:55.856762 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3469 23:08:55.859953 Pre-setting of DQS Precalculation
3470 23:08:55.862918 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3471 23:08:55.872917 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3472 23:08:55.879747 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3473 23:08:55.880306
3474 23:08:55.880754
3475 23:08:55.883294 [Calibration Summary] 2400 Mbps
3476 23:08:55.883853 CH 0, Rank 0
3477 23:08:55.886815 SW Impedance : PASS
3478 23:08:55.887372 DUTY Scan : NO K
3479 23:08:55.889772 ZQ Calibration : PASS
3480 23:08:55.893189 Jitter Meter : NO K
3481 23:08:55.893743 CBT Training : PASS
3482 23:08:55.896590 Write leveling : PASS
3483 23:08:55.899899 RX DQS gating : PASS
3484 23:08:55.900450 RX DQ/DQS(RDDQC) : PASS
3485 23:08:55.902809 TX DQ/DQS : PASS
3486 23:08:55.906664 RX DATLAT : PASS
3487 23:08:55.907128 RX DQ/DQS(Engine): PASS
3488 23:08:55.909721 TX OE : NO K
3489 23:08:55.910186 All Pass.
3490 23:08:55.910554
3491 23:08:55.910897 CH 0, Rank 1
3492 23:08:55.913093 SW Impedance : PASS
3493 23:08:55.916664 DUTY Scan : NO K
3494 23:08:55.917213 ZQ Calibration : PASS
3495 23:08:55.919802 Jitter Meter : NO K
3496 23:08:55.922992 CBT Training : PASS
3497 23:08:55.923459 Write leveling : PASS
3498 23:08:55.926584 RX DQS gating : PASS
3499 23:08:55.929572 RX DQ/DQS(RDDQC) : PASS
3500 23:08:55.930182 TX DQ/DQS : PASS
3501 23:08:55.933087 RX DATLAT : PASS
3502 23:08:55.936396 RX DQ/DQS(Engine): PASS
3503 23:08:55.936997 TX OE : NO K
3504 23:08:55.939836 All Pass.
3505 23:08:55.940401
3506 23:08:55.940842 CH 1, Rank 0
3507 23:08:55.943051 SW Impedance : PASS
3508 23:08:55.943518 DUTY Scan : NO K
3509 23:08:55.946900 ZQ Calibration : PASS
3510 23:08:55.949497 Jitter Meter : NO K
3511 23:08:55.949985 CBT Training : PASS
3512 23:08:55.952921 Write leveling : PASS
3513 23:08:55.953410 RX DQS gating : PASS
3514 23:08:55.956571 RX DQ/DQS(RDDQC) : PASS
3515 23:08:55.959622 TX DQ/DQS : PASS
3516 23:08:55.960087 RX DATLAT : PASS
3517 23:08:55.962989 RX DQ/DQS(Engine): PASS
3518 23:08:55.966337 TX OE : NO K
3519 23:08:55.966804 All Pass.
3520 23:08:55.967171
3521 23:08:55.967569 CH 1, Rank 1
3522 23:08:55.969589 SW Impedance : PASS
3523 23:08:55.973005 DUTY Scan : NO K
3524 23:08:55.973468 ZQ Calibration : PASS
3525 23:08:55.976339 Jitter Meter : NO K
3526 23:08:55.979972 CBT Training : PASS
3527 23:08:55.980436 Write leveling : PASS
3528 23:08:55.983132 RX DQS gating : PASS
3529 23:08:55.986636 RX DQ/DQS(RDDQC) : PASS
3530 23:08:55.987202 TX DQ/DQS : PASS
3531 23:08:55.990225 RX DATLAT : PASS
3532 23:08:55.990794 RX DQ/DQS(Engine): PASS
3533 23:08:55.993132 TX OE : NO K
3534 23:08:55.993599 All Pass.
3535 23:08:55.993971
3536 23:08:55.996738 DramC Write-DBI off
3537 23:08:55.999882 PER_BANK_REFRESH: Hybrid Mode
3538 23:08:56.000450 TX_TRACKING: ON
3539 23:08:56.009761 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3540 23:08:56.012891 [FAST_K] Save calibration result to emmc
3541 23:08:56.016206 dramc_set_vcore_voltage set vcore to 650000
3542 23:08:56.019583 Read voltage for 600, 5
3543 23:08:56.020163 Vio18 = 0
3544 23:08:56.022732 Vcore = 650000
3545 23:08:56.023193 Vdram = 0
3546 23:08:56.023560 Vddq = 0
3547 23:08:56.023898 Vmddr = 0
3548 23:08:56.029752 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3549 23:08:56.036194 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3550 23:08:56.036720 MEM_TYPE=3, freq_sel=19
3551 23:08:56.040116 sv_algorithm_assistance_LP4_1600
3552 23:08:56.043171 ============ PULL DRAM RESETB DOWN ============
3553 23:08:56.049807 ========== PULL DRAM RESETB DOWN end =========
3554 23:08:56.052911 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3555 23:08:56.056618 ===================================
3556 23:08:56.061151 LPDDR4 DRAM CONFIGURATION
3557 23:08:56.062727 ===================================
3558 23:08:56.063204 EX_ROW_EN[0] = 0x0
3559 23:08:56.066329 EX_ROW_EN[1] = 0x0
3560 23:08:56.067020 LP4Y_EN = 0x0
3561 23:08:56.069604 WORK_FSP = 0x0
3562 23:08:56.070093 WL = 0x2
3563 23:08:56.072606 RL = 0x2
3564 23:08:56.073079 BL = 0x2
3565 23:08:56.076404 RPST = 0x0
3566 23:08:56.079194 RD_PRE = 0x0
3567 23:08:56.079672 WR_PRE = 0x1
3568 23:08:56.082678 WR_PST = 0x0
3569 23:08:56.083141 DBI_WR = 0x0
3570 23:08:56.086255 DBI_RD = 0x0
3571 23:08:56.087068 OTF = 0x1
3572 23:08:56.089249 ===================================
3573 23:08:56.092958 ===================================
3574 23:08:56.093526 ANA top config
3575 23:08:56.096316 ===================================
3576 23:08:56.099379 DLL_ASYNC_EN = 0
3577 23:08:56.102770 ALL_SLAVE_EN = 1
3578 23:08:56.106127 NEW_RANK_MODE = 1
3579 23:08:56.109193 DLL_IDLE_MODE = 1
3580 23:08:56.109660 LP45_APHY_COMB_EN = 1
3581 23:08:56.112739 TX_ODT_DIS = 1
3582 23:08:56.116186 NEW_8X_MODE = 1
3583 23:08:56.119457 ===================================
3584 23:08:56.122894 ===================================
3585 23:08:56.126038 data_rate = 1200
3586 23:08:56.129225 CKR = 1
3587 23:08:56.129793 DQ_P2S_RATIO = 8
3588 23:08:56.132415 ===================================
3589 23:08:56.136171 CA_P2S_RATIO = 8
3590 23:08:56.139545 DQ_CA_OPEN = 0
3591 23:08:56.142691 DQ_SEMI_OPEN = 0
3592 23:08:56.145905 CA_SEMI_OPEN = 0
3593 23:08:56.149219 CA_FULL_RATE = 0
3594 23:08:56.149687 DQ_CKDIV4_EN = 1
3595 23:08:56.152332 CA_CKDIV4_EN = 1
3596 23:08:56.155778 CA_PREDIV_EN = 0
3597 23:08:56.159371 PH8_DLY = 0
3598 23:08:56.162573 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3599 23:08:56.165804 DQ_AAMCK_DIV = 4
3600 23:08:56.166385 CA_AAMCK_DIV = 4
3601 23:08:56.169224 CA_ADMCK_DIV = 4
3602 23:08:56.172216 DQ_TRACK_CA_EN = 0
3603 23:08:56.175907 CA_PICK = 600
3604 23:08:56.178913 CA_MCKIO = 600
3605 23:08:56.182435 MCKIO_SEMI = 0
3606 23:08:56.185355 PLL_FREQ = 2288
3607 23:08:56.188891 DQ_UI_PI_RATIO = 32
3608 23:08:56.189453 CA_UI_PI_RATIO = 0
3609 23:08:56.191982 ===================================
3610 23:08:56.195646 ===================================
3611 23:08:56.198885 memory_type:LPDDR4
3612 23:08:56.201981 GP_NUM : 10
3613 23:08:56.202542 SRAM_EN : 1
3614 23:08:56.205186 MD32_EN : 0
3615 23:08:56.208710 ===================================
3616 23:08:56.211958 [ANA_INIT] >>>>>>>>>>>>>>
3617 23:08:56.215621 <<<<<< [CONFIGURE PHASE]: ANA_TX
3618 23:08:56.218571 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3619 23:08:56.222053 ===================================
3620 23:08:56.222615 data_rate = 1200,PCW = 0X5800
3621 23:08:56.225438 ===================================
3622 23:08:56.228845 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3623 23:08:56.235303 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3624 23:08:56.241933 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3625 23:08:56.245249 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3626 23:08:56.248236 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3627 23:08:56.251905 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3628 23:08:56.254888 [ANA_INIT] flow start
3629 23:08:56.255436 [ANA_INIT] PLL >>>>>>>>
3630 23:08:56.258157 [ANA_INIT] PLL <<<<<<<<
3631 23:08:56.261508 [ANA_INIT] MIDPI >>>>>>>>
3632 23:08:56.264825 [ANA_INIT] MIDPI <<<<<<<<
3633 23:08:56.265290 [ANA_INIT] DLL >>>>>>>>
3634 23:08:56.268463 [ANA_INIT] flow end
3635 23:08:56.271914 ============ LP4 DIFF to SE enter ============
3636 23:08:56.274770 ============ LP4 DIFF to SE exit ============
3637 23:08:56.278218 [ANA_INIT] <<<<<<<<<<<<<
3638 23:08:56.281535 [Flow] Enable top DCM control >>>>>
3639 23:08:56.284894 [Flow] Enable top DCM control <<<<<
3640 23:08:56.288237 Enable DLL master slave shuffle
3641 23:08:56.294652 ==============================================================
3642 23:08:56.295233 Gating Mode config
3643 23:08:56.301272 ==============================================================
3644 23:08:56.301835 Config description:
3645 23:08:56.311053 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3646 23:08:56.317810 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3647 23:08:56.324574 SELPH_MODE 0: By rank 1: By Phase
3648 23:08:56.328201 ==============================================================
3649 23:08:56.330935 GAT_TRACK_EN = 1
3650 23:08:56.334234 RX_GATING_MODE = 2
3651 23:08:56.337702 RX_GATING_TRACK_MODE = 2
3652 23:08:56.340769 SELPH_MODE = 1
3653 23:08:56.344114 PICG_EARLY_EN = 1
3654 23:08:56.347810 VALID_LAT_VALUE = 1
3655 23:08:56.353903 ==============================================================
3656 23:08:56.357207 Enter into Gating configuration >>>>
3657 23:08:56.360659 Exit from Gating configuration <<<<
3658 23:08:56.364053 Enter into DVFS_PRE_config >>>>>
3659 23:08:56.374407 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3660 23:08:56.377223 Exit from DVFS_PRE_config <<<<<
3661 23:08:56.380746 Enter into PICG configuration >>>>
3662 23:08:56.383749 Exit from PICG configuration <<<<
3663 23:08:56.387588 [RX_INPUT] configuration >>>>>
3664 23:08:56.388158 [RX_INPUT] configuration <<<<<
3665 23:08:56.394004 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3666 23:08:56.400663 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3667 23:08:56.403890 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3668 23:08:56.410673 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3669 23:08:56.417065 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3670 23:08:56.423729 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3671 23:08:56.427010 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3672 23:08:56.430236 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3673 23:08:56.437153 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3674 23:08:56.440390 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3675 23:08:56.443630 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3676 23:08:56.450205 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3677 23:08:56.453563 ===================================
3678 23:08:56.454087 LPDDR4 DRAM CONFIGURATION
3679 23:08:56.457111 ===================================
3680 23:08:56.460253 EX_ROW_EN[0] = 0x0
3681 23:08:56.460925 EX_ROW_EN[1] = 0x0
3682 23:08:56.463670 LP4Y_EN = 0x0
3683 23:08:56.464280 WORK_FSP = 0x0
3684 23:08:56.466894 WL = 0x2
3685 23:08:56.470123 RL = 0x2
3686 23:08:56.470584 BL = 0x2
3687 23:08:56.473356 RPST = 0x0
3688 23:08:56.473907 RD_PRE = 0x0
3689 23:08:56.477125 WR_PRE = 0x1
3690 23:08:56.477649 WR_PST = 0x0
3691 23:08:56.480245 DBI_WR = 0x0
3692 23:08:56.480901 DBI_RD = 0x0
3693 23:08:56.483764 OTF = 0x1
3694 23:08:56.486721 ===================================
3695 23:08:56.490326 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3696 23:08:56.493619 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3697 23:08:56.496865 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3698 23:08:56.500003 ===================================
3699 23:08:56.503394 LPDDR4 DRAM CONFIGURATION
3700 23:08:56.506571 ===================================
3701 23:08:56.509899 EX_ROW_EN[0] = 0x10
3702 23:08:56.510364 EX_ROW_EN[1] = 0x0
3703 23:08:56.513429 LP4Y_EN = 0x0
3704 23:08:56.513893 WORK_FSP = 0x0
3705 23:08:56.516726 WL = 0x2
3706 23:08:56.517187 RL = 0x2
3707 23:08:56.519697 BL = 0x2
3708 23:08:56.520252 RPST = 0x0
3709 23:08:56.523341 RD_PRE = 0x0
3710 23:08:56.526520 WR_PRE = 0x1
3711 23:08:56.526982 WR_PST = 0x0
3712 23:08:56.529653 DBI_WR = 0x0
3713 23:08:56.530116 DBI_RD = 0x0
3714 23:08:56.533433 OTF = 0x1
3715 23:08:56.536403 ===================================
3716 23:08:56.539599 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3717 23:08:56.544995 nWR fixed to 30
3718 23:08:56.548387 [ModeRegInit_LP4] CH0 RK0
3719 23:08:56.548974 [ModeRegInit_LP4] CH0 RK1
3720 23:08:56.551533 [ModeRegInit_LP4] CH1 RK0
3721 23:08:56.555334 [ModeRegInit_LP4] CH1 RK1
3722 23:08:56.555909 match AC timing 16
3723 23:08:56.561845 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3724 23:08:56.564951 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3725 23:08:56.568582 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3726 23:08:56.575503 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3727 23:08:56.578712 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3728 23:08:56.579277 ==
3729 23:08:56.581803 Dram Type= 6, Freq= 0, CH_0, rank 0
3730 23:08:56.585247 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3731 23:08:56.585811 ==
3732 23:08:56.592157 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3733 23:08:56.598207 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3734 23:08:56.601689 [CA 0] Center 35 (5~66) winsize 62
3735 23:08:56.604878 [CA 1] Center 35 (5~66) winsize 62
3736 23:08:56.608423 [CA 2] Center 34 (4~65) winsize 62
3737 23:08:56.611606 [CA 3] Center 34 (3~65) winsize 63
3738 23:08:56.615013 [CA 4] Center 33 (3~64) winsize 62
3739 23:08:56.617966 [CA 5] Center 33 (3~64) winsize 62
3740 23:08:56.618430
3741 23:08:56.621428 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3742 23:08:56.621984
3743 23:08:56.624940 [CATrainingPosCal] consider 1 rank data
3744 23:08:56.628170 u2DelayCellTimex100 = 270/100 ps
3745 23:08:56.631431 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3746 23:08:56.634568 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3747 23:08:56.637847 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3748 23:08:56.641652 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3749 23:08:56.644864 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3750 23:08:56.651167 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3751 23:08:56.651725
3752 23:08:56.654640 CA PerBit enable=1, Macro0, CA PI delay=33
3753 23:08:56.655213
3754 23:08:56.657747 [CBTSetCACLKResult] CA Dly = 33
3755 23:08:56.658319 CS Dly: 6 (0~37)
3756 23:08:56.658696 ==
3757 23:08:56.660911 Dram Type= 6, Freq= 0, CH_0, rank 1
3758 23:08:56.664157 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3759 23:08:56.667733 ==
3760 23:08:56.671184 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3761 23:08:56.677762 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
3762 23:08:56.681383 [CA 0] Center 35 (5~66) winsize 62
3763 23:08:56.684330 [CA 1] Center 35 (5~66) winsize 62
3764 23:08:56.687727 [CA 2] Center 34 (4~65) winsize 62
3765 23:08:56.691199 [CA 3] Center 34 (4~65) winsize 62
3766 23:08:56.694172 [CA 4] Center 33 (3~64) winsize 62
3767 23:08:56.698109 [CA 5] Center 33 (3~64) winsize 62
3768 23:08:56.698677
3769 23:08:56.700903 [CmdBusTrainingLP45] Vref(ca) range 1: 39
3770 23:08:56.701468
3771 23:08:56.704031 [CATrainingPosCal] consider 2 rank data
3772 23:08:56.707607 u2DelayCellTimex100 = 270/100 ps
3773 23:08:56.710770 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3774 23:08:56.714037 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3775 23:08:56.717207 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3776 23:08:56.720998 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3777 23:08:56.727536 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3778 23:08:56.730753 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3779 23:08:56.731224
3780 23:08:56.733969 CA PerBit enable=1, Macro0, CA PI delay=33
3781 23:08:56.734441
3782 23:08:56.737109 [CBTSetCACLKResult] CA Dly = 33
3783 23:08:56.737576 CS Dly: 6 (0~37)
3784 23:08:56.737950
3785 23:08:56.740809 ----->DramcWriteLeveling(PI) begin...
3786 23:08:56.741285 ==
3787 23:08:56.744057 Dram Type= 6, Freq= 0, CH_0, rank 0
3788 23:08:56.750679 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3789 23:08:56.751237 ==
3790 23:08:56.754174 Write leveling (Byte 0): 31 => 31
3791 23:08:56.757223 Write leveling (Byte 1): 29 => 29
3792 23:08:56.757694 DramcWriteLeveling(PI) end<-----
3793 23:08:56.758063
3794 23:08:56.760499 ==
3795 23:08:56.764250 Dram Type= 6, Freq= 0, CH_0, rank 0
3796 23:08:56.767379 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3797 23:08:56.767942 ==
3798 23:08:56.770617 [Gating] SW mode calibration
3799 23:08:56.777283 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3800 23:08:56.780743 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3801 23:08:56.787608 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3802 23:08:56.790406 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3803 23:08:56.793785 0 5 8 | B1->B0 | 3333 3030 | 1 0 | (0 1) (0 0)
3804 23:08:56.800728 0 5 12 | B1->B0 | 2727 2323 | 1 0 | (1 0) (0 0)
3805 23:08:56.803397 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3806 23:08:56.807189 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3807 23:08:56.813507 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3808 23:08:56.816661 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3809 23:08:56.820194 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3810 23:08:56.827093 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3811 23:08:56.830201 0 6 8 | B1->B0 | 2e2e 2e2e | 0 0 | (0 0) (0 0)
3812 23:08:56.833807 0 6 12 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
3813 23:08:56.840402 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3814 23:08:56.843326 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3815 23:08:56.846657 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3816 23:08:56.853204 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3817 23:08:56.856900 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3818 23:08:56.859931 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3819 23:08:56.866768 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3820 23:08:56.869935 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3821 23:08:56.873355 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3822 23:08:56.879755 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3823 23:08:56.883056 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3824 23:08:56.886342 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3825 23:08:56.893198 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3826 23:08:56.896349 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3827 23:08:56.900234 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3828 23:08:56.906275 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3829 23:08:56.909434 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3830 23:08:56.912619 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3831 23:08:56.919318 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3832 23:08:56.922492 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3833 23:08:56.926358 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3834 23:08:56.932787 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3835 23:08:56.935774 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3836 23:08:56.939111 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3837 23:08:56.942854 Total UI for P1: 0, mck2ui 16
3838 23:08:56.945674 best dqsien dly found for B0: ( 0, 9, 8)
3839 23:08:56.949015 Total UI for P1: 0, mck2ui 16
3840 23:08:56.952240 best dqsien dly found for B1: ( 0, 9, 10)
3841 23:08:56.956096 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
3842 23:08:56.959043 best DQS1 dly(MCK, UI, PI) = (0, 9, 10)
3843 23:08:56.959605
3844 23:08:56.962238 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
3845 23:08:56.969252 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10)
3846 23:08:56.969820 [Gating] SW calibration Done
3847 23:08:56.972275 ==
3848 23:08:56.972793 Dram Type= 6, Freq= 0, CH_0, rank 0
3849 23:08:56.978962 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3850 23:08:56.979530 ==
3851 23:08:56.979914 RX Vref Scan: 0
3852 23:08:56.980268
3853 23:08:56.982300 RX Vref 0 -> 0, step: 1
3854 23:08:56.982863
3855 23:08:56.985354 RX Delay -230 -> 252, step: 16
3856 23:08:56.989018 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
3857 23:08:56.992065 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
3858 23:08:56.998643 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
3859 23:08:57.002319 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
3860 23:08:57.005714 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
3861 23:08:57.008248 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
3862 23:08:57.015210 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3863 23:08:57.018363 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
3864 23:08:57.022205 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3865 23:08:57.024947 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
3866 23:08:57.028108 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
3867 23:08:57.034717 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3868 23:08:57.038212 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3869 23:08:57.041818 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3870 23:08:57.044853 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3871 23:08:57.051779 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3872 23:08:57.052397 ==
3873 23:08:57.054935 Dram Type= 6, Freq= 0, CH_0, rank 0
3874 23:08:57.058278 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3875 23:08:57.058843 ==
3876 23:08:57.059212 DQS Delay:
3877 23:08:57.061398 DQS0 = 0, DQS1 = 0
3878 23:08:57.061859 DQM Delay:
3879 23:08:57.064442 DQM0 = 38, DQM1 = 33
3880 23:08:57.064947 DQ Delay:
3881 23:08:57.068131 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
3882 23:08:57.071520 DQ4 =49, DQ5 =25, DQ6 =49, DQ7 =49
3883 23:08:57.074654 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
3884 23:08:57.078075 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3885 23:08:57.078643
3886 23:08:57.079015
3887 23:08:57.079358 ==
3888 23:08:57.080996 Dram Type= 6, Freq= 0, CH_0, rank 0
3889 23:08:57.084563 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3890 23:08:57.088099 ==
3891 23:08:57.088716
3892 23:08:57.089088
3893 23:08:57.089432 TX Vref Scan disable
3894 23:08:57.091013 == TX Byte 0 ==
3895 23:08:57.094611 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
3896 23:08:57.101047 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
3897 23:08:57.101601 == TX Byte 1 ==
3898 23:08:57.104157 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
3899 23:08:57.110595 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
3900 23:08:57.111127 ==
3901 23:08:57.113949 Dram Type= 6, Freq= 0, CH_0, rank 0
3902 23:08:57.117371 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3903 23:08:57.117843 ==
3904 23:08:57.118214
3905 23:08:57.118558
3906 23:08:57.120899 TX Vref Scan disable
3907 23:08:57.123997 == TX Byte 0 ==
3908 23:08:57.127339 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
3909 23:08:57.130904 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
3910 23:08:57.134081 == TX Byte 1 ==
3911 23:08:57.137012 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3912 23:08:57.140405 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3913 23:08:57.140911
3914 23:08:57.143610 [DATLAT]
3915 23:08:57.144092 Freq=600, CH0 RK0
3916 23:08:57.144688
3917 23:08:57.147037 DATLAT Default: 0x9
3918 23:08:57.147519 0, 0xFFFF, sum = 0
3919 23:08:57.150451 1, 0xFFFF, sum = 0
3920 23:08:57.150940 2, 0xFFFF, sum = 0
3921 23:08:57.153917 3, 0xFFFF, sum = 0
3922 23:08:57.154407 4, 0xFFFF, sum = 0
3923 23:08:57.157064 5, 0xFFFF, sum = 0
3924 23:08:57.157554 6, 0xFFFF, sum = 0
3925 23:08:57.160079 7, 0x0, sum = 1
3926 23:08:57.160608 8, 0x0, sum = 2
3927 23:08:57.163383 9, 0x0, sum = 3
3928 23:08:57.163874 10, 0x0, sum = 4
3929 23:08:57.164373 best_step = 8
3930 23:08:57.164878
3931 23:08:57.166811 ==
3932 23:08:57.170260 Dram Type= 6, Freq= 0, CH_0, rank 0
3933 23:08:57.173218 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3934 23:08:57.173643 ==
3935 23:08:57.174230 RX Vref Scan: 1
3936 23:08:57.174763
3937 23:08:57.176581 RX Vref 0 -> 0, step: 1
3938 23:08:57.177193
3939 23:08:57.180005 RX Delay -195 -> 252, step: 8
3940 23:08:57.180623
3941 23:08:57.183377 Set Vref, RX VrefLevel [Byte0]: 47
3942 23:08:57.186488 [Byte1]: 48
3943 23:08:57.186907
3944 23:08:57.189801 Final RX Vref Byte 0 = 47 to rank0
3945 23:08:57.193138 Final RX Vref Byte 1 = 48 to rank0
3946 23:08:57.196780 Final RX Vref Byte 0 = 47 to rank1
3947 23:08:57.199946 Final RX Vref Byte 1 = 48 to rank1==
3948 23:08:57.203377 Dram Type= 6, Freq= 0, CH_0, rank 0
3949 23:08:57.206506 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3950 23:08:57.209954 ==
3951 23:08:57.210379 DQS Delay:
3952 23:08:57.210737 DQS0 = 0, DQS1 = 0
3953 23:08:57.213132 DQM Delay:
3954 23:08:57.213554 DQM0 = 41, DQM1 = 30
3955 23:08:57.216372 DQ Delay:
3956 23:08:57.220071 DQ0 =40, DQ1 =40, DQ2 =40, DQ3 =36
3957 23:08:57.220656 DQ4 =40, DQ5 =32, DQ6 =48, DQ7 =52
3958 23:08:57.223289 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
3959 23:08:57.226248 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
3960 23:08:57.229667
3961 23:08:57.230091
3962 23:08:57.236286 [DQSOSCAuto] RK0, (LSB)MR18= 0x5b5b, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
3963 23:08:57.239709 CH0 RK0: MR19=808, MR18=5B5B
3964 23:08:57.246462 CH0_RK0: MR19=0x808, MR18=0x5B5B, DQSOSC=392, MR23=63, INC=170, DEC=113
3965 23:08:57.246993
3966 23:08:57.249705 ----->DramcWriteLeveling(PI) begin...
3967 23:08:57.250180 ==
3968 23:08:57.253132 Dram Type= 6, Freq= 0, CH_0, rank 1
3969 23:08:57.256468 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3970 23:08:57.256988 ==
3971 23:08:57.259952 Write leveling (Byte 0): 30 => 30
3972 23:08:57.263024 Write leveling (Byte 1): 29 => 29
3973 23:08:57.266357 DramcWriteLeveling(PI) end<-----
3974 23:08:57.266825
3975 23:08:57.267198 ==
3976 23:08:57.270022 Dram Type= 6, Freq= 0, CH_0, rank 1
3977 23:08:57.272928 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3978 23:08:57.273405 ==
3979 23:08:57.276204 [Gating] SW mode calibration
3980 23:08:57.283099 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3981 23:08:57.290028 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3982 23:08:57.292953 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3983 23:08:57.296311 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3984 23:08:57.303232 0 5 8 | B1->B0 | 3232 3030 | 0 0 | (0 0) (1 1)
3985 23:08:57.306300 0 5 12 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
3986 23:08:57.309480 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3987 23:08:57.316135 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3988 23:08:57.319487 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3989 23:08:57.322721 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3990 23:08:57.329467 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3991 23:08:57.332484 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3992 23:08:57.336068 0 6 8 | B1->B0 | 2929 3636 | 0 0 | (1 1) (0 0)
3993 23:08:57.342466 0 6 12 | B1->B0 | 4545 4545 | 0 0 | (0 0) (0 0)
3994 23:08:57.345749 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3995 23:08:57.348948 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3996 23:08:57.355517 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3997 23:08:57.358676 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3998 23:08:57.362067 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3999 23:08:57.368606 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4000 23:08:57.371742 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4001 23:08:57.375316 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 23:08:57.381989 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 23:08:57.385002 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 23:08:57.388470 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 23:08:57.395305 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 23:08:57.398409 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 23:08:57.401610 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 23:08:57.408207 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 23:08:57.411779 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 23:08:57.414716 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 23:08:57.421434 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 23:08:57.424626 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 23:08:57.428129 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 23:08:57.434787 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 23:08:57.438564 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 23:08:57.441335 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4017 23:08:57.444367 Total UI for P1: 0, mck2ui 16
4018 23:08:57.447914 best dqsien dly found for B1: ( 0, 9, 6)
4019 23:08:57.454730 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4020 23:08:57.454816 Total UI for P1: 0, mck2ui 16
4021 23:08:57.457766 best dqsien dly found for B0: ( 0, 9, 8)
4022 23:08:57.464896 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
4023 23:08:57.468200 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4024 23:08:57.468670
4025 23:08:57.471658 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
4026 23:08:57.474629 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4027 23:08:57.478245 [Gating] SW calibration Done
4028 23:08:57.478669 ==
4029 23:08:57.481296 Dram Type= 6, Freq= 0, CH_0, rank 1
4030 23:08:57.485067 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4031 23:08:57.485391 ==
4032 23:08:57.487930 RX Vref Scan: 0
4033 23:08:57.488249
4034 23:08:57.488446 RX Vref 0 -> 0, step: 1
4035 23:08:57.488637
4036 23:08:57.491564 RX Delay -230 -> 252, step: 16
4037 23:08:57.494873 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4038 23:08:57.501349 iDelay=218, Bit 1, Center 41 (-134 ~ 217) 352
4039 23:08:57.504803 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4040 23:08:57.507831 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4041 23:08:57.511132 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4042 23:08:57.514497 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4043 23:08:57.521783 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4044 23:08:57.524776 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4045 23:08:57.528324 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4046 23:08:57.531248 iDelay=218, Bit 9, Center 9 (-150 ~ 169) 320
4047 23:08:57.537900 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4048 23:08:57.541145 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4049 23:08:57.544619 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4050 23:08:57.547965 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4051 23:08:57.554189 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4052 23:08:57.557661 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4053 23:08:57.558132 ==
4054 23:08:57.561211 Dram Type= 6, Freq= 0, CH_0, rank 1
4055 23:08:57.564266 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4056 23:08:57.564771 ==
4057 23:08:57.567850 DQS Delay:
4058 23:08:57.568264 DQS0 = 0, DQS1 = 0
4059 23:08:57.568671 DQM Delay:
4060 23:08:57.571272 DQM0 = 40, DQM1 = 31
4061 23:08:57.571861 DQ Delay:
4062 23:08:57.574692 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4063 23:08:57.577936 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4064 23:08:57.581325 DQ8 =25, DQ9 =9, DQ10 =33, DQ11 =25
4065 23:08:57.584545 DQ12 =41, DQ13 =33, DQ14 =41, DQ15 =41
4066 23:08:57.585126
4067 23:08:57.585497
4068 23:08:57.585842 ==
4069 23:08:57.587814 Dram Type= 6, Freq= 0, CH_0, rank 1
4070 23:08:57.594236 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4071 23:08:57.594816 ==
4072 23:08:57.595198
4073 23:08:57.595544
4074 23:08:57.595876 TX Vref Scan disable
4075 23:08:57.597597 == TX Byte 0 ==
4076 23:08:57.601321 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4077 23:08:57.607708 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4078 23:08:57.608267 == TX Byte 1 ==
4079 23:08:57.611051 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4080 23:08:57.617493 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4081 23:08:57.617979 ==
4082 23:08:57.621074 Dram Type= 6, Freq= 0, CH_0, rank 1
4083 23:08:57.624193 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4084 23:08:57.624697 ==
4085 23:08:57.625073
4086 23:08:57.625417
4087 23:08:57.627605 TX Vref Scan disable
4088 23:08:57.631023 == TX Byte 0 ==
4089 23:08:57.634267 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4090 23:08:57.637644 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4091 23:08:57.640853 == TX Byte 1 ==
4092 23:08:57.644214 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4093 23:08:57.647687 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4094 23:08:57.648254
4095 23:08:57.648688 [DATLAT]
4096 23:08:57.650917 Freq=600, CH0 RK1
4097 23:08:57.651493
4098 23:08:57.654011 DATLAT Default: 0x8
4099 23:08:57.654481 0, 0xFFFF, sum = 0
4100 23:08:57.657637 1, 0xFFFF, sum = 0
4101 23:08:57.658184 2, 0xFFFF, sum = 0
4102 23:08:57.660865 3, 0xFFFF, sum = 0
4103 23:08:57.661443 4, 0xFFFF, sum = 0
4104 23:08:57.664357 5, 0xFFFF, sum = 0
4105 23:08:57.664980 6, 0xFFFF, sum = 0
4106 23:08:57.667232 7, 0x0, sum = 1
4107 23:08:57.667899 8, 0x0, sum = 2
4108 23:08:57.668303 9, 0x0, sum = 3
4109 23:08:57.670543 10, 0x0, sum = 4
4110 23:08:57.671017 best_step = 8
4111 23:08:57.671386
4112 23:08:57.671731 ==
4113 23:08:57.674347 Dram Type= 6, Freq= 0, CH_0, rank 1
4114 23:08:57.681009 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4115 23:08:57.681580 ==
4116 23:08:57.681957 RX Vref Scan: 0
4117 23:08:57.682308
4118 23:08:57.683692 RX Vref 0 -> 0, step: 1
4119 23:08:57.684162
4120 23:08:57.687261 RX Delay -195 -> 252, step: 8
4121 23:08:57.693806 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4122 23:08:57.697269 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4123 23:08:57.700592 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4124 23:08:57.703633 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4125 23:08:57.707021 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4126 23:08:57.713376 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4127 23:08:57.717146 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4128 23:08:57.720292 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4129 23:08:57.723505 iDelay=205, Bit 8, Center 24 (-123 ~ 172) 296
4130 23:08:57.730119 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4131 23:08:57.733366 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4132 23:08:57.736473 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4133 23:08:57.739771 iDelay=205, Bit 12, Center 36 (-115 ~ 188) 304
4134 23:08:57.746737 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4135 23:08:57.750353 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4136 23:08:57.753129 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4137 23:08:57.753593 ==
4138 23:08:57.756762 Dram Type= 6, Freq= 0, CH_0, rank 1
4139 23:08:57.759743 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4140 23:08:57.760300 ==
4141 23:08:57.762970 DQS Delay:
4142 23:08:57.763497 DQS0 = 0, DQS1 = 0
4143 23:08:57.766625 DQM Delay:
4144 23:08:57.767186 DQM0 = 41, DQM1 = 33
4145 23:08:57.767560 DQ Delay:
4146 23:08:57.769789 DQ0 =36, DQ1 =40, DQ2 =40, DQ3 =36
4147 23:08:57.773113 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4148 23:08:57.776335 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =24
4149 23:08:57.779650 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =44
4150 23:08:57.780197
4151 23:08:57.780627
4152 23:08:57.789314 [DQSOSCAuto] RK1, (LSB)MR18= 0x6868, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
4153 23:08:57.793084 CH0 RK1: MR19=808, MR18=6868
4154 23:08:57.799587 CH0_RK1: MR19=0x808, MR18=0x6868, DQSOSC=390, MR23=63, INC=172, DEC=114
4155 23:08:57.802815 [RxdqsGatingPostProcess] freq 600
4156 23:08:57.806079 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4157 23:08:57.809447 Pre-setting of DQS Precalculation
4158 23:08:57.812703 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4159 23:08:57.815974 ==
4160 23:08:57.819641 Dram Type= 6, Freq= 0, CH_1, rank 0
4161 23:08:57.822499 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4162 23:08:57.822975 ==
4163 23:08:57.826293 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4164 23:08:57.832550 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4165 23:08:57.837043 [CA 0] Center 35 (5~66) winsize 62
4166 23:08:57.840206 [CA 1] Center 35 (5~66) winsize 62
4167 23:08:57.843514 [CA 2] Center 33 (3~64) winsize 62
4168 23:08:57.846284 [CA 3] Center 33 (3~64) winsize 62
4169 23:08:57.849782 [CA 4] Center 33 (2~64) winsize 63
4170 23:08:57.853017 [CA 5] Center 33 (2~64) winsize 63
4171 23:08:57.853488
4172 23:08:57.856233 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4173 23:08:57.856733
4174 23:08:57.859945 [CATrainingPosCal] consider 1 rank data
4175 23:08:57.863310 u2DelayCellTimex100 = 270/100 ps
4176 23:08:57.866926 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4177 23:08:57.870156 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4178 23:08:57.876654 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4179 23:08:57.879675 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4180 23:08:57.883264 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
4181 23:08:57.886618 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4182 23:08:57.887196
4183 23:08:57.889553 CA PerBit enable=1, Macro0, CA PI delay=33
4184 23:08:57.890029
4185 23:08:57.893154 [CBTSetCACLKResult] CA Dly = 33
4186 23:08:57.893743 CS Dly: 3 (0~34)
4187 23:08:57.896092 ==
4188 23:08:57.899523 Dram Type= 6, Freq= 0, CH_1, rank 1
4189 23:08:57.902666 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4190 23:08:57.903141 ==
4191 23:08:57.906315 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4192 23:08:57.912812 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4193 23:08:57.916195 [CA 0] Center 35 (5~66) winsize 62
4194 23:08:57.919734 [CA 1] Center 34 (4~65) winsize 62
4195 23:08:57.922955 [CA 2] Center 33 (3~64) winsize 62
4196 23:08:57.926522 [CA 3] Center 33 (3~64) winsize 62
4197 23:08:57.929661 [CA 4] Center 32 (2~63) winsize 62
4198 23:08:57.933159 [CA 5] Center 32 (2~63) winsize 62
4199 23:08:57.933730
4200 23:08:57.936595 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4201 23:08:57.937147
4202 23:08:57.939537 [CATrainingPosCal] consider 2 rank data
4203 23:08:57.942987 u2DelayCellTimex100 = 270/100 ps
4204 23:08:57.946516 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4205 23:08:57.952967 CA1 delay=35 (5~65),Diff = 3 PI (28 cell)
4206 23:08:57.956133 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4207 23:08:57.959841 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4208 23:08:57.962829 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4209 23:08:57.965843 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4210 23:08:57.966310
4211 23:08:57.969099 CA PerBit enable=1, Macro0, CA PI delay=32
4212 23:08:57.969567
4213 23:08:57.972703 [CBTSetCACLKResult] CA Dly = 32
4214 23:08:57.976316 CS Dly: 4 (0~36)
4215 23:08:57.976923
4216 23:08:57.979344 ----->DramcWriteLeveling(PI) begin...
4217 23:08:57.979923 ==
4218 23:08:57.982614 Dram Type= 6, Freq= 0, CH_1, rank 0
4219 23:08:57.985819 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4220 23:08:57.986392 ==
4221 23:08:57.989102 Write leveling (Byte 0): 26 => 26
4222 23:08:57.992433 Write leveling (Byte 1): 26 => 26
4223 23:08:57.995857 DramcWriteLeveling(PI) end<-----
4224 23:08:57.996435
4225 23:08:57.996871 ==
4226 23:08:57.999062 Dram Type= 6, Freq= 0, CH_1, rank 0
4227 23:08:58.002647 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4228 23:08:58.003225 ==
4229 23:08:58.005376 [Gating] SW mode calibration
4230 23:08:58.012093 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4231 23:08:58.019032 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4232 23:08:58.022427 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4233 23:08:58.025336 0 5 4 | B1->B0 | 3434 3030 | 1 0 | (1 0) (1 1)
4234 23:08:58.032046 0 5 8 | B1->B0 | 3030 2b2b | 1 0 | (1 0) (0 0)
4235 23:08:58.035612 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4236 23:08:58.038433 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4237 23:08:58.045111 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4238 23:08:58.048378 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4239 23:08:58.051946 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4240 23:08:58.058906 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4241 23:08:58.061944 0 6 4 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
4242 23:08:58.065421 0 6 8 | B1->B0 | 3535 4343 | 0 0 | (0 0) (0 0)
4243 23:08:58.072048 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4244 23:08:58.075327 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4245 23:08:58.079211 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4246 23:08:58.085019 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4247 23:08:58.088593 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4248 23:08:58.091970 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4249 23:08:58.098684 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4250 23:08:58.101818 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4251 23:08:58.104796 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 23:08:58.111509 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 23:08:58.114953 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 23:08:58.118130 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 23:08:58.124866 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 23:08:58.128111 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 23:08:58.131587 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 23:08:58.138409 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 23:08:58.141367 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 23:08:58.144798 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4261 23:08:58.151372 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4262 23:08:58.154363 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 23:08:58.157807 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 23:08:58.164452 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4265 23:08:58.167862 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4266 23:08:58.171245 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4267 23:08:58.174443 Total UI for P1: 0, mck2ui 16
4268 23:08:58.177838 best dqsien dly found for B0: ( 0, 9, 4)
4269 23:08:58.181718 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4270 23:08:58.184128 Total UI for P1: 0, mck2ui 16
4271 23:08:58.187810 best dqsien dly found for B1: ( 0, 9, 8)
4272 23:08:58.191038 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
4273 23:08:58.197583 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4274 23:08:58.198160
4275 23:08:58.201051 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
4276 23:08:58.203983 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4277 23:08:58.207390 [Gating] SW calibration Done
4278 23:08:58.208020 ==
4279 23:08:58.210471 Dram Type= 6, Freq= 0, CH_1, rank 0
4280 23:08:58.214240 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4281 23:08:58.214874 ==
4282 23:08:58.217281 RX Vref Scan: 0
4283 23:08:58.217867
4284 23:08:58.218248 RX Vref 0 -> 0, step: 1
4285 23:08:58.218597
4286 23:08:58.220504 RX Delay -230 -> 252, step: 16
4287 23:08:58.223754 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4288 23:08:58.230593 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4289 23:08:58.234048 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4290 23:08:58.236997 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4291 23:08:58.240277 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4292 23:08:58.247054 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4293 23:08:58.250244 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4294 23:08:58.253631 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4295 23:08:58.257038 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4296 23:08:58.260184 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4297 23:08:58.266632 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4298 23:08:58.270370 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4299 23:08:58.273271 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4300 23:08:58.276742 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4301 23:08:58.283419 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4302 23:08:58.286805 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4303 23:08:58.287370 ==
4304 23:08:58.290266 Dram Type= 6, Freq= 0, CH_1, rank 0
4305 23:08:58.293577 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4306 23:08:58.294140 ==
4307 23:08:58.296571 DQS Delay:
4308 23:08:58.297047 DQS0 = 0, DQS1 = 0
4309 23:08:58.297420 DQM Delay:
4310 23:08:58.300446 DQM0 = 39, DQM1 = 32
4311 23:08:58.301069 DQ Delay:
4312 23:08:58.303217 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4313 23:08:58.306521 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4314 23:08:58.309629 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4315 23:08:58.312990 DQ12 =41, DQ13 =49, DQ14 =33, DQ15 =49
4316 23:08:58.313450
4317 23:08:58.313816
4318 23:08:58.314155 ==
4319 23:08:58.316351 Dram Type= 6, Freq= 0, CH_1, rank 0
4320 23:08:58.323064 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4321 23:08:58.323634 ==
4322 23:08:58.324009
4323 23:08:58.324353
4324 23:08:58.326346 TX Vref Scan disable
4325 23:08:58.326809 == TX Byte 0 ==
4326 23:08:58.329511 Update DQ dly =570 (2 ,1, 26) DQ OEN =(1 ,6)
4327 23:08:58.336463 Update DQM dly =570 (2 ,1, 26) DQM OEN =(1 ,6)
4328 23:08:58.337116 == TX Byte 1 ==
4329 23:08:58.339723 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4330 23:08:58.346255 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4331 23:08:58.346815 ==
4332 23:08:58.349187 Dram Type= 6, Freq= 0, CH_1, rank 0
4333 23:08:58.352587 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4334 23:08:58.353047 ==
4335 23:08:58.353454
4336 23:08:58.353801
4337 23:08:58.356002 TX Vref Scan disable
4338 23:08:58.359490 == TX Byte 0 ==
4339 23:08:58.362508 Update DQ dly =570 (2 ,1, 26) DQ OEN =(1 ,6)
4340 23:08:58.365695 Update DQM dly =570 (2 ,1, 26) DQM OEN =(1 ,6)
4341 23:08:58.369265 == TX Byte 1 ==
4342 23:08:58.372571 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4343 23:08:58.376056 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4344 23:08:58.376678
4345 23:08:58.379600 [DATLAT]
4346 23:08:58.380153 Freq=600, CH1 RK0
4347 23:08:58.380562
4348 23:08:58.382651 DATLAT Default: 0x9
4349 23:08:58.383202 0, 0xFFFF, sum = 0
4350 23:08:58.385951 1, 0xFFFF, sum = 0
4351 23:08:58.386514 2, 0xFFFF, sum = 0
4352 23:08:58.389299 3, 0xFFFF, sum = 0
4353 23:08:58.389862 4, 0xFFFF, sum = 0
4354 23:08:58.392444 5, 0xFFFF, sum = 0
4355 23:08:58.392964 6, 0xFFFF, sum = 0
4356 23:08:58.395893 7, 0x0, sum = 1
4357 23:08:58.396453 8, 0x0, sum = 2
4358 23:08:58.399244 9, 0x0, sum = 3
4359 23:08:58.399804 10, 0x0, sum = 4
4360 23:08:58.402479 best_step = 8
4361 23:08:58.403050
4362 23:08:58.403414 ==
4363 23:08:58.405740 Dram Type= 6, Freq= 0, CH_1, rank 0
4364 23:08:58.408687 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4365 23:08:58.409162 ==
4366 23:08:58.412314 RX Vref Scan: 1
4367 23:08:58.412939
4368 23:08:58.413311 RX Vref 0 -> 0, step: 1
4369 23:08:58.413649
4370 23:08:58.415196 RX Delay -195 -> 252, step: 8
4371 23:08:58.415652
4372 23:08:58.418850 Set Vref, RX VrefLevel [Byte0]: 55
4373 23:08:58.422154 [Byte1]: 48
4374 23:08:58.425972
4375 23:08:58.426543 Final RX Vref Byte 0 = 55 to rank0
4376 23:08:58.428824 Final RX Vref Byte 1 = 48 to rank0
4377 23:08:58.432568 Final RX Vref Byte 0 = 55 to rank1
4378 23:08:58.435867 Final RX Vref Byte 1 = 48 to rank1==
4379 23:08:58.438980 Dram Type= 6, Freq= 0, CH_1, rank 0
4380 23:08:58.445911 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4381 23:08:58.446475 ==
4382 23:08:58.446854 DQS Delay:
4383 23:08:58.447198 DQS0 = 0, DQS1 = 0
4384 23:08:58.448656 DQM Delay:
4385 23:08:58.449113 DQM0 = 38, DQM1 = 30
4386 23:08:58.452474 DQ Delay:
4387 23:08:58.455270 DQ0 =44, DQ1 =32, DQ2 =28, DQ3 =36
4388 23:08:58.458648 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4389 23:08:58.461887 DQ8 =12, DQ9 =20, DQ10 =32, DQ11 =24
4390 23:08:58.464991 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40
4391 23:08:58.465452
4392 23:08:58.465818
4393 23:08:58.471852 [DQSOSCAuto] RK0, (LSB)MR18= 0x7d7d, (MSB)MR19= 0x808, tDQSOscB0 = 386 ps tDQSOscB1 = 386 ps
4394 23:08:58.475407 CH1 RK0: MR19=808, MR18=7D7D
4395 23:08:58.481826 CH1_RK0: MR19=0x808, MR18=0x7D7D, DQSOSC=386, MR23=63, INC=176, DEC=117
4396 23:08:58.482384
4397 23:08:58.485471 ----->DramcWriteLeveling(PI) begin...
4398 23:08:58.486039 ==
4399 23:08:58.488413 Dram Type= 6, Freq= 0, CH_1, rank 1
4400 23:08:58.491936 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4401 23:08:58.492499 ==
4402 23:08:58.495143 Write leveling (Byte 0): 27 => 27
4403 23:08:58.498967 Write leveling (Byte 1): 27 => 27
4404 23:08:58.501782 DramcWriteLeveling(PI) end<-----
4405 23:08:58.502342
4406 23:08:58.502707 ==
4407 23:08:58.505064 Dram Type= 6, Freq= 0, CH_1, rank 1
4408 23:08:58.508555 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4409 23:08:58.511590 ==
4410 23:08:58.512049 [Gating] SW mode calibration
4411 23:08:58.518298 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4412 23:08:58.524997 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4413 23:08:58.527864 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4414 23:08:58.535136 0 5 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
4415 23:08:58.538034 0 5 8 | B1->B0 | 3030 2626 | 0 0 | (1 1) (0 0)
4416 23:08:58.541327 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4417 23:08:58.548439 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4418 23:08:58.551559 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4419 23:08:58.555093 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4420 23:08:58.561257 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4421 23:08:58.564703 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4422 23:08:58.567821 0 6 4 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
4423 23:08:58.574677 0 6 8 | B1->B0 | 3434 4545 | 0 0 | (1 1) (0 0)
4424 23:08:58.577884 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4425 23:08:58.581092 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4426 23:08:58.587854 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4427 23:08:58.591557 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4428 23:08:58.594473 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4429 23:08:58.601436 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4430 23:08:58.604790 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4431 23:08:58.607726 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 23:08:58.614176 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 23:08:58.617386 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 23:08:58.621107 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 23:08:58.624417 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 23:08:58.631401 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 23:08:58.633972 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 23:08:58.637661 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 23:08:58.644149 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 23:08:58.647661 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 23:08:58.650903 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 23:08:58.657237 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 23:08:58.660798 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 23:08:58.664209 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 23:08:58.670945 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 23:08:58.674133 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4447 23:08:58.677388 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4448 23:08:58.680381 Total UI for P1: 0, mck2ui 16
4449 23:08:58.683908 best dqsien dly found for B0: ( 0, 9, 4)
4450 23:08:58.687397 Total UI for P1: 0, mck2ui 16
4451 23:08:58.690230 best dqsien dly found for B1: ( 0, 9, 6)
4452 23:08:58.693842 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
4453 23:08:58.697245 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4454 23:08:58.697802
4455 23:08:58.703886 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
4456 23:08:58.707341 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4457 23:08:58.710131 [Gating] SW calibration Done
4458 23:08:58.710594 ==
4459 23:08:58.713587 Dram Type= 6, Freq= 0, CH_1, rank 1
4460 23:08:58.716954 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4461 23:08:58.717514 ==
4462 23:08:58.717889 RX Vref Scan: 0
4463 23:08:58.718234
4464 23:08:58.720300 RX Vref 0 -> 0, step: 1
4465 23:08:58.720801
4466 23:08:58.723637 RX Delay -230 -> 252, step: 16
4467 23:08:58.727074 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4468 23:08:58.730348 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4469 23:08:58.737065 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4470 23:08:58.740548 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4471 23:08:58.743524 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4472 23:08:58.746691 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4473 23:08:58.753272 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4474 23:08:58.756701 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4475 23:08:58.760197 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4476 23:08:58.763476 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4477 23:08:58.766665 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4478 23:08:58.773319 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4479 23:08:58.776639 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4480 23:08:58.779959 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4481 23:08:58.783174 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4482 23:08:58.790147 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4483 23:08:58.790774 ==
4484 23:08:58.793289 Dram Type= 6, Freq= 0, CH_1, rank 1
4485 23:08:58.796483 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4486 23:08:58.797095 ==
4487 23:08:58.797471 DQS Delay:
4488 23:08:58.799797 DQS0 = 0, DQS1 = 0
4489 23:08:58.800352 DQM Delay:
4490 23:08:58.803089 DQM0 = 39, DQM1 = 34
4491 23:08:58.803647 DQ Delay:
4492 23:08:58.806256 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4493 23:08:58.809663 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =33
4494 23:08:58.813048 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4495 23:08:58.816183 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41
4496 23:08:58.816801
4497 23:08:58.817171
4498 23:08:58.817518 ==
4499 23:08:58.819542 Dram Type= 6, Freq= 0, CH_1, rank 1
4500 23:08:58.826032 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4501 23:08:58.826598 ==
4502 23:08:58.826970
4503 23:08:58.827310
4504 23:08:58.827640 TX Vref Scan disable
4505 23:08:58.829329 == TX Byte 0 ==
4506 23:08:58.832722 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4507 23:08:58.839563 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4508 23:08:58.840124 == TX Byte 1 ==
4509 23:08:58.842886 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4510 23:08:58.849367 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4511 23:08:58.849842 ==
4512 23:08:58.852606 Dram Type= 6, Freq= 0, CH_1, rank 1
4513 23:08:58.856044 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4514 23:08:58.856684 ==
4515 23:08:58.857089
4516 23:08:58.857438
4517 23:08:58.859272 TX Vref Scan disable
4518 23:08:58.862804 == TX Byte 0 ==
4519 23:08:58.865845 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4520 23:08:58.869456 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4521 23:08:58.872585 == TX Byte 1 ==
4522 23:08:58.875936 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4523 23:08:58.879296 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4524 23:08:58.879854
4525 23:08:58.880225 [DATLAT]
4526 23:08:58.882453 Freq=600, CH1 RK1
4527 23:08:58.883013
4528 23:08:58.885960 DATLAT Default: 0x8
4529 23:08:58.886519 0, 0xFFFF, sum = 0
4530 23:08:58.889260 1, 0xFFFF, sum = 0
4531 23:08:58.889831 2, 0xFFFF, sum = 0
4532 23:08:58.892563 3, 0xFFFF, sum = 0
4533 23:08:58.893174 4, 0xFFFF, sum = 0
4534 23:08:58.895761 5, 0xFFFF, sum = 0
4535 23:08:58.896330 6, 0xFFFF, sum = 0
4536 23:08:58.899198 7, 0x0, sum = 1
4537 23:08:58.899786 8, 0x0, sum = 2
4538 23:08:58.902282 9, 0x0, sum = 3
4539 23:08:58.902846 10, 0x0, sum = 4
4540 23:08:58.903289 best_step = 8
4541 23:08:58.903823
4542 23:08:58.905269 ==
4543 23:08:58.905677 Dram Type= 6, Freq= 0, CH_1, rank 1
4544 23:08:58.912479 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4545 23:08:58.913103 ==
4546 23:08:58.913473 RX Vref Scan: 0
4547 23:08:58.913862
4548 23:08:58.915184 RX Vref 0 -> 0, step: 1
4549 23:08:58.915583
4550 23:08:58.918549 RX Delay -195 -> 252, step: 8
4551 23:08:58.922135 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4552 23:08:58.928751 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4553 23:08:58.931983 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4554 23:08:58.935332 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4555 23:08:58.938806 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4556 23:08:58.945295 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4557 23:08:58.948655 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4558 23:08:58.952278 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4559 23:08:58.955918 iDelay=205, Bit 8, Center 12 (-147 ~ 172) 320
4560 23:08:58.959103 iDelay=205, Bit 9, Center 12 (-147 ~ 172) 320
4561 23:08:58.965571 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4562 23:08:58.968821 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4563 23:08:58.972198 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4564 23:08:58.975333 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4565 23:08:58.982420 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4566 23:08:58.985418 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4567 23:08:58.985970 ==
4568 23:08:58.989063 Dram Type= 6, Freq= 0, CH_1, rank 1
4569 23:08:58.992068 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4570 23:08:58.992692 ==
4571 23:08:58.995252 DQS Delay:
4572 23:08:58.995811 DQS0 = 0, DQS1 = 0
4573 23:08:58.996180 DQM Delay:
4574 23:08:58.998365 DQM0 = 37, DQM1 = 29
4575 23:08:58.998830 DQ Delay:
4576 23:08:59.001866 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4577 23:08:59.005229 DQ4 =40, DQ5 =48, DQ6 =44, DQ7 =36
4578 23:08:59.008676 DQ8 =12, DQ9 =12, DQ10 =32, DQ11 =20
4579 23:08:59.011859 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40
4580 23:08:59.012417
4581 23:08:59.012852
4582 23:08:59.021908 [DQSOSCAuto] RK1, (LSB)MR18= 0x5555, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
4583 23:08:59.025529 CH1 RK1: MR19=808, MR18=5555
4584 23:08:59.028933 CH1_RK1: MR19=0x808, MR18=0x5555, DQSOSC=393, MR23=63, INC=169, DEC=113
4585 23:08:59.031609 [RxdqsGatingPostProcess] freq 600
4586 23:08:59.038128 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4587 23:08:59.041675 Pre-setting of DQS Precalculation
4588 23:08:59.045221 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4589 23:08:59.055140 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4590 23:08:59.061857 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4591 23:08:59.062418
4592 23:08:59.062787
4593 23:08:59.064622 [Calibration Summary] 1200 Mbps
4594 23:08:59.065089 CH 0, Rank 0
4595 23:08:59.068064 SW Impedance : PASS
4596 23:08:59.068576 DUTY Scan : NO K
4597 23:08:59.071617 ZQ Calibration : PASS
4598 23:08:59.075004 Jitter Meter : NO K
4599 23:08:59.075567 CBT Training : PASS
4600 23:08:59.078245 Write leveling : PASS
4601 23:08:59.081484 RX DQS gating : PASS
4602 23:08:59.082042 RX DQ/DQS(RDDQC) : PASS
4603 23:08:59.084756 TX DQ/DQS : PASS
4604 23:08:59.088356 RX DATLAT : PASS
4605 23:08:59.088948 RX DQ/DQS(Engine): PASS
4606 23:08:59.091237 TX OE : NO K
4607 23:08:59.091795 All Pass.
4608 23:08:59.092167
4609 23:08:59.094790 CH 0, Rank 1
4610 23:08:59.095347 SW Impedance : PASS
4611 23:08:59.097975 DUTY Scan : NO K
4612 23:08:59.101563 ZQ Calibration : PASS
4613 23:08:59.102125 Jitter Meter : NO K
4614 23:08:59.104163 CBT Training : PASS
4615 23:08:59.107585 Write leveling : PASS
4616 23:08:59.108049 RX DQS gating : PASS
4617 23:08:59.110907 RX DQ/DQS(RDDQC) : PASS
4618 23:08:59.111531 TX DQ/DQS : PASS
4619 23:08:59.114134 RX DATLAT : PASS
4620 23:08:59.117352 RX DQ/DQS(Engine): PASS
4621 23:08:59.117815 TX OE : NO K
4622 23:08:59.121133 All Pass.
4623 23:08:59.121595
4624 23:08:59.121961 CH 1, Rank 0
4625 23:08:59.124088 SW Impedance : PASS
4626 23:08:59.124582 DUTY Scan : NO K
4627 23:08:59.127531 ZQ Calibration : PASS
4628 23:08:59.130933 Jitter Meter : NO K
4629 23:08:59.131495 CBT Training : PASS
4630 23:08:59.133984 Write leveling : PASS
4631 23:08:59.137540 RX DQS gating : PASS
4632 23:08:59.138098 RX DQ/DQS(RDDQC) : PASS
4633 23:08:59.141176 TX DQ/DQS : PASS
4634 23:08:59.144266 RX DATLAT : PASS
4635 23:08:59.144877 RX DQ/DQS(Engine): PASS
4636 23:08:59.147169 TX OE : NO K
4637 23:08:59.147707 All Pass.
4638 23:08:59.148275
4639 23:08:59.150850 CH 1, Rank 1
4640 23:08:59.151400 SW Impedance : PASS
4641 23:08:59.153739 DUTY Scan : NO K
4642 23:08:59.157084 ZQ Calibration : PASS
4643 23:08:59.157547 Jitter Meter : NO K
4644 23:08:59.160555 CBT Training : PASS
4645 23:08:59.164088 Write leveling : PASS
4646 23:08:59.164692 RX DQS gating : PASS
4647 23:08:59.167247 RX DQ/DQS(RDDQC) : PASS
4648 23:08:59.170604 TX DQ/DQS : PASS
4649 23:08:59.171162 RX DATLAT : PASS
4650 23:08:59.173886 RX DQ/DQS(Engine): PASS
4651 23:08:59.174440 TX OE : NO K
4652 23:08:59.177183 All Pass.
4653 23:08:59.177737
4654 23:08:59.178107 DramC Write-DBI off
4655 23:08:59.180380 PER_BANK_REFRESH: Hybrid Mode
4656 23:08:59.183816 TX_TRACKING: ON
4657 23:08:59.190257 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4658 23:08:59.193493 [FAST_K] Save calibration result to emmc
4659 23:08:59.200217 dramc_set_vcore_voltage set vcore to 662500
4660 23:08:59.200822 Read voltage for 933, 3
4661 23:08:59.203437 Vio18 = 0
4662 23:08:59.203994 Vcore = 662500
4663 23:08:59.204368 Vdram = 0
4664 23:08:59.204782 Vddq = 0
4665 23:08:59.206826 Vmddr = 0
4666 23:08:59.209740 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4667 23:08:59.216612 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4668 23:08:59.220310 MEM_TYPE=3, freq_sel=17
4669 23:08:59.220921 sv_algorithm_assistance_LP4_1600
4670 23:08:59.226861 ============ PULL DRAM RESETB DOWN ============
4671 23:08:59.229838 ========== PULL DRAM RESETB DOWN end =========
4672 23:08:59.233365 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4673 23:08:59.236653 ===================================
4674 23:08:59.239935 LPDDR4 DRAM CONFIGURATION
4675 23:08:59.243039 ===================================
4676 23:08:59.246638 EX_ROW_EN[0] = 0x0
4677 23:08:59.247194 EX_ROW_EN[1] = 0x0
4678 23:08:59.249655 LP4Y_EN = 0x0
4679 23:08:59.250118 WORK_FSP = 0x0
4680 23:08:59.252801 WL = 0x3
4681 23:08:59.253265 RL = 0x3
4682 23:08:59.255944 BL = 0x2
4683 23:08:59.256620 RPST = 0x0
4684 23:08:59.259141 RD_PRE = 0x0
4685 23:08:59.262892 WR_PRE = 0x1
4686 23:08:59.263446 WR_PST = 0x0
4687 23:08:59.266172 DBI_WR = 0x0
4688 23:08:59.266637 DBI_RD = 0x0
4689 23:08:59.269271 OTF = 0x1
4690 23:08:59.272900 ===================================
4691 23:08:59.276360 ===================================
4692 23:08:59.276986 ANA top config
4693 23:08:59.279668 ===================================
4694 23:08:59.282636 DLL_ASYNC_EN = 0
4695 23:08:59.283104 ALL_SLAVE_EN = 1
4696 23:08:59.286677 NEW_RANK_MODE = 1
4697 23:08:59.289453 DLL_IDLE_MODE = 1
4698 23:08:59.292778 LP45_APHY_COMB_EN = 1
4699 23:08:59.296026 TX_ODT_DIS = 1
4700 23:08:59.296614 NEW_8X_MODE = 1
4701 23:08:59.299449 ===================================
4702 23:08:59.302738 ===================================
4703 23:08:59.306176 data_rate = 1866
4704 23:08:59.309359 CKR = 1
4705 23:08:59.313038 DQ_P2S_RATIO = 8
4706 23:08:59.315666 ===================================
4707 23:08:59.319316 CA_P2S_RATIO = 8
4708 23:08:59.322583 DQ_CA_OPEN = 0
4709 23:08:59.325359 DQ_SEMI_OPEN = 0
4710 23:08:59.325824 CA_SEMI_OPEN = 0
4711 23:08:59.328977 CA_FULL_RATE = 0
4712 23:08:59.331946 DQ_CKDIV4_EN = 1
4713 23:08:59.335524 CA_CKDIV4_EN = 1
4714 23:08:59.339029 CA_PREDIV_EN = 0
4715 23:08:59.341849 PH8_DLY = 0
4716 23:08:59.342312 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4717 23:08:59.345190 DQ_AAMCK_DIV = 4
4718 23:08:59.349041 CA_AAMCK_DIV = 4
4719 23:08:59.351795 CA_ADMCK_DIV = 4
4720 23:08:59.355073 DQ_TRACK_CA_EN = 0
4721 23:08:59.358571 CA_PICK = 933
4722 23:08:59.362207 CA_MCKIO = 933
4723 23:08:59.362784 MCKIO_SEMI = 0
4724 23:08:59.365004 PLL_FREQ = 3732
4725 23:08:59.368318 DQ_UI_PI_RATIO = 32
4726 23:08:59.371715 CA_UI_PI_RATIO = 0
4727 23:08:59.375077 ===================================
4728 23:08:59.378337 ===================================
4729 23:08:59.382055 memory_type:LPDDR4
4730 23:08:59.382611 GP_NUM : 10
4731 23:08:59.384930 SRAM_EN : 1
4732 23:08:59.388329 MD32_EN : 0
4733 23:08:59.391637 ===================================
4734 23:08:59.392196 [ANA_INIT] >>>>>>>>>>>>>>
4735 23:08:59.394850 <<<<<< [CONFIGURE PHASE]: ANA_TX
4736 23:08:59.398238 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4737 23:08:59.401206 ===================================
4738 23:08:59.405044 data_rate = 1866,PCW = 0X8f00
4739 23:08:59.408058 ===================================
4740 23:08:59.411452 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4741 23:08:59.417859 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4742 23:08:59.421320 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4743 23:08:59.428077 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4744 23:08:59.431312 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4745 23:08:59.434608 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4746 23:08:59.435256 [ANA_INIT] flow start
4747 23:08:59.437831 [ANA_INIT] PLL >>>>>>>>
4748 23:08:59.441142 [ANA_INIT] PLL <<<<<<<<
4749 23:08:59.444414 [ANA_INIT] MIDPI >>>>>>>>
4750 23:08:59.445049 [ANA_INIT] MIDPI <<<<<<<<
4751 23:08:59.447558 [ANA_INIT] DLL >>>>>>>>
4752 23:08:59.448016 [ANA_INIT] flow end
4753 23:08:59.454505 ============ LP4 DIFF to SE enter ============
4754 23:08:59.457581 ============ LP4 DIFF to SE exit ============
4755 23:08:59.460979 [ANA_INIT] <<<<<<<<<<<<<
4756 23:08:59.464353 [Flow] Enable top DCM control >>>>>
4757 23:08:59.467703 [Flow] Enable top DCM control <<<<<
4758 23:08:59.471033 Enable DLL master slave shuffle
4759 23:08:59.474599 ==============================================================
4760 23:08:59.477920 Gating Mode config
4761 23:08:59.481222 ==============================================================
4762 23:08:59.484175 Config description:
4763 23:08:59.494013 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4764 23:08:59.500921 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4765 23:08:59.504115 SELPH_MODE 0: By rank 1: By Phase
4766 23:08:59.510701 ==============================================================
4767 23:08:59.514334 GAT_TRACK_EN = 1
4768 23:08:59.517423 RX_GATING_MODE = 2
4769 23:08:59.520492 RX_GATING_TRACK_MODE = 2
4770 23:08:59.523966 SELPH_MODE = 1
4771 23:08:59.527281 PICG_EARLY_EN = 1
4772 23:08:59.527845 VALID_LAT_VALUE = 1
4773 23:08:59.533919 ==============================================================
4774 23:08:59.537158 Enter into Gating configuration >>>>
4775 23:08:59.540893 Exit from Gating configuration <<<<
4776 23:08:59.543900 Enter into DVFS_PRE_config >>>>>
4777 23:08:59.553749 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4778 23:08:59.557029 Exit from DVFS_PRE_config <<<<<
4779 23:08:59.560375 Enter into PICG configuration >>>>
4780 23:08:59.563864 Exit from PICG configuration <<<<
4781 23:08:59.567009 [RX_INPUT] configuration >>>>>
4782 23:08:59.570359 [RX_INPUT] configuration <<<<<
4783 23:08:59.576850 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4784 23:08:59.580639 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4785 23:08:59.587020 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4786 23:08:59.593686 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4787 23:08:59.600205 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4788 23:08:59.606855 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4789 23:08:59.610034 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4790 23:08:59.613327 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4791 23:08:59.617003 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4792 23:08:59.623398 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4793 23:08:59.626798 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4794 23:08:59.630300 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4795 23:08:59.633309 ===================================
4796 23:08:59.636597 LPDDR4 DRAM CONFIGURATION
4797 23:08:59.639962 ===================================
4798 23:08:59.640577 EX_ROW_EN[0] = 0x0
4799 23:08:59.643200 EX_ROW_EN[1] = 0x0
4800 23:08:59.646624 LP4Y_EN = 0x0
4801 23:08:59.647186 WORK_FSP = 0x0
4802 23:08:59.650038 WL = 0x3
4803 23:08:59.650744 RL = 0x3
4804 23:08:59.653255 BL = 0x2
4805 23:08:59.653715 RPST = 0x0
4806 23:08:59.656654 RD_PRE = 0x0
4807 23:08:59.657252 WR_PRE = 0x1
4808 23:08:59.659777 WR_PST = 0x0
4809 23:08:59.660334 DBI_WR = 0x0
4810 23:08:59.663337 DBI_RD = 0x0
4811 23:08:59.663894 OTF = 0x1
4812 23:08:59.666438 ===================================
4813 23:08:59.669530 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4814 23:08:59.676427 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4815 23:08:59.679700 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4816 23:08:59.683052 ===================================
4817 23:08:59.686585 LPDDR4 DRAM CONFIGURATION
4818 23:08:59.689929 ===================================
4819 23:08:59.690509 EX_ROW_EN[0] = 0x10
4820 23:08:59.692949 EX_ROW_EN[1] = 0x0
4821 23:08:59.696294 LP4Y_EN = 0x0
4822 23:08:59.696888 WORK_FSP = 0x0
4823 23:08:59.699301 WL = 0x3
4824 23:08:59.699856 RL = 0x3
4825 23:08:59.702703 BL = 0x2
4826 23:08:59.703162 RPST = 0x0
4827 23:08:59.706284 RD_PRE = 0x0
4828 23:08:59.706878 WR_PRE = 0x1
4829 23:08:59.709361 WR_PST = 0x0
4830 23:08:59.709816 DBI_WR = 0x0
4831 23:08:59.712655 DBI_RD = 0x0
4832 23:08:59.713115 OTF = 0x1
4833 23:08:59.716030 ===================================
4834 23:08:59.723123 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4835 23:08:59.726972 nWR fixed to 30
4836 23:08:59.730377 [ModeRegInit_LP4] CH0 RK0
4837 23:08:59.730977 [ModeRegInit_LP4] CH0 RK1
4838 23:08:59.733246 [ModeRegInit_LP4] CH1 RK0
4839 23:08:59.737093 [ModeRegInit_LP4] CH1 RK1
4840 23:08:59.737652 match AC timing 8
4841 23:08:59.743576 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4842 23:08:59.746958 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4843 23:08:59.750057 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4844 23:08:59.756845 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4845 23:08:59.759922 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4846 23:08:59.760483 ==
4847 23:08:59.763269 Dram Type= 6, Freq= 0, CH_0, rank 0
4848 23:08:59.766749 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4849 23:08:59.767313 ==
4850 23:08:59.773300 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4851 23:08:59.779780 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4852 23:08:59.783358 [CA 0] Center 38 (8~69) winsize 62
4853 23:08:59.786420 [CA 1] Center 38 (8~69) winsize 62
4854 23:08:59.789753 [CA 2] Center 36 (6~67) winsize 62
4855 23:08:59.792969 [CA 3] Center 36 (6~67) winsize 62
4856 23:08:59.796299 [CA 4] Center 34 (4~65) winsize 62
4857 23:08:59.800012 [CA 5] Center 34 (4~65) winsize 62
4858 23:08:59.800606
4859 23:08:59.803014 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4860 23:08:59.803573
4861 23:08:59.806181 [CATrainingPosCal] consider 1 rank data
4862 23:08:59.809256 u2DelayCellTimex100 = 270/100 ps
4863 23:08:59.812834 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4864 23:08:59.815978 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4865 23:08:59.819295 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4866 23:08:59.822583 CA3 delay=36 (6~67),Diff = 2 PI (12 cell)
4867 23:08:59.829286 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4868 23:08:59.832651 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4869 23:08:59.833208
4870 23:08:59.835884 CA PerBit enable=1, Macro0, CA PI delay=34
4871 23:08:59.836343
4872 23:08:59.839458 [CBTSetCACLKResult] CA Dly = 34
4873 23:08:59.840082 CS Dly: 7 (0~38)
4874 23:08:59.840460 ==
4875 23:08:59.842597 Dram Type= 6, Freq= 0, CH_0, rank 1
4876 23:08:59.845912 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4877 23:08:59.849149 ==
4878 23:08:59.852670 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4879 23:08:59.859144 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4880 23:08:59.862488 [CA 0] Center 38 (8~69) winsize 62
4881 23:08:59.865994 [CA 1] Center 38 (7~69) winsize 63
4882 23:08:59.868943 [CA 2] Center 36 (6~67) winsize 62
4883 23:08:59.872250 [CA 3] Center 35 (5~66) winsize 62
4884 23:08:59.875896 [CA 4] Center 34 (4~65) winsize 62
4885 23:08:59.878940 [CA 5] Center 34 (4~65) winsize 62
4886 23:08:59.879497
4887 23:08:59.882585 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4888 23:08:59.883149
4889 23:08:59.885750 [CATrainingPosCal] consider 2 rank data
4890 23:08:59.889120 u2DelayCellTimex100 = 270/100 ps
4891 23:08:59.892685 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4892 23:08:59.895850 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4893 23:08:59.902162 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4894 23:08:59.905460 CA3 delay=36 (6~66),Diff = 2 PI (12 cell)
4895 23:08:59.908888 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4896 23:08:59.911973 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4897 23:08:59.912432
4898 23:08:59.915143 CA PerBit enable=1, Macro0, CA PI delay=34
4899 23:08:59.915601
4900 23:08:59.918492 [CBTSetCACLKResult] CA Dly = 34
4901 23:08:59.918954 CS Dly: 7 (0~39)
4902 23:08:59.919321
4903 23:08:59.925146 ----->DramcWriteLeveling(PI) begin...
4904 23:08:59.925709 ==
4905 23:08:59.928132 Dram Type= 6, Freq= 0, CH_0, rank 0
4906 23:08:59.932017 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4907 23:08:59.932646 ==
4908 23:08:59.934891 Write leveling (Byte 0): 28 => 28
4909 23:08:59.938601 Write leveling (Byte 1): 28 => 28
4910 23:08:59.941605 DramcWriteLeveling(PI) end<-----
4911 23:08:59.942064
4912 23:08:59.942432 ==
4913 23:08:59.944733 Dram Type= 6, Freq= 0, CH_0, rank 0
4914 23:08:59.948347 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4915 23:08:59.948976 ==
4916 23:08:59.951633 [Gating] SW mode calibration
4917 23:08:59.958179 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4918 23:08:59.964823 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4919 23:08:59.968004 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4920 23:08:59.971612 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4921 23:08:59.978520 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4922 23:08:59.981473 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4923 23:08:59.984919 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4924 23:08:59.991696 0 10 20 | B1->B0 | 3434 3232 | 0 0 | (0 0) (0 1)
4925 23:08:59.994826 0 10 24 | B1->B0 | 2626 2323 | 0 0 | (0 0) (1 0)
4926 23:08:59.998210 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4927 23:09:00.004808 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4928 23:09:00.007972 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4929 23:09:00.011285 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4930 23:09:00.018100 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4931 23:09:00.021277 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4932 23:09:00.024920 0 11 20 | B1->B0 | 2525 2e2e | 0 0 | (0 0) (0 0)
4933 23:09:00.031268 0 11 24 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
4934 23:09:00.034175 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4935 23:09:00.037747 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4936 23:09:00.041105 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4937 23:09:00.047845 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4938 23:09:00.051377 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4939 23:09:00.054099 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4940 23:09:00.060821 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4941 23:09:00.064277 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4942 23:09:00.067934 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4943 23:09:00.074460 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4944 23:09:00.077642 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4945 23:09:00.080778 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4946 23:09:00.087815 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4947 23:09:00.090739 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4948 23:09:00.094024 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4949 23:09:00.101110 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4950 23:09:00.104148 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4951 23:09:00.107248 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4952 23:09:00.114015 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4953 23:09:00.117194 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4954 23:09:00.120874 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4955 23:09:00.127160 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4956 23:09:00.130425 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4957 23:09:00.133747 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4958 23:09:00.137099 Total UI for P1: 0, mck2ui 16
4959 23:09:00.140575 best dqsien dly found for B0: ( 0, 14, 20)
4960 23:09:00.143537 Total UI for P1: 0, mck2ui 16
4961 23:09:00.147064 best dqsien dly found for B1: ( 0, 14, 22)
4962 23:09:00.149993 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
4963 23:09:00.153140 best DQS1 dly(MCK, UI, PI) = (0, 14, 22)
4964 23:09:00.156782
4965 23:09:00.160449 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
4966 23:09:00.163476 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 22)
4967 23:09:00.167114 [Gating] SW calibration Done
4968 23:09:00.167672 ==
4969 23:09:00.170014 Dram Type= 6, Freq= 0, CH_0, rank 0
4970 23:09:00.173320 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4971 23:09:00.173892 ==
4972 23:09:00.174266 RX Vref Scan: 0
4973 23:09:00.176705
4974 23:09:00.177162 RX Vref 0 -> 0, step: 1
4975 23:09:00.177601
4976 23:09:00.179990 RX Delay -80 -> 252, step: 8
4977 23:09:00.183376 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
4978 23:09:00.186449 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
4979 23:09:00.193228 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
4980 23:09:00.196259 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
4981 23:09:00.200001 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
4982 23:09:00.203240 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
4983 23:09:00.206498 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
4984 23:09:00.209734 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
4985 23:09:00.216607 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
4986 23:09:00.220131 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
4987 23:09:00.222971 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
4988 23:09:00.226061 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
4989 23:09:00.229469 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
4990 23:09:00.236020 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
4991 23:09:00.239667 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
4992 23:09:00.242936 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
4993 23:09:00.243403 ==
4994 23:09:00.246027 Dram Type= 6, Freq= 0, CH_0, rank 0
4995 23:09:00.249406 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4996 23:09:00.249970 ==
4997 23:09:00.252560 DQS Delay:
4998 23:09:00.253037 DQS0 = 0, DQS1 = 0
4999 23:09:00.253484 DQM Delay:
5000 23:09:00.256038 DQM0 = 97, DQM1 = 89
5001 23:09:00.256503 DQ Delay:
5002 23:09:00.259165 DQ0 =91, DQ1 =95, DQ2 =95, DQ3 =91
5003 23:09:00.262735 DQ4 =103, DQ5 =91, DQ6 =107, DQ7 =107
5004 23:09:00.265654 DQ8 =79, DQ9 =71, DQ10 =87, DQ11 =83
5005 23:09:00.269268 DQ12 =95, DQ13 =99, DQ14 =99, DQ15 =99
5006 23:09:00.269829
5007 23:09:00.270198
5008 23:09:00.272741 ==
5009 23:09:00.273298 Dram Type= 6, Freq= 0, CH_0, rank 0
5010 23:09:00.278954 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5011 23:09:00.279501 ==
5012 23:09:00.279877
5013 23:09:00.280215
5014 23:09:00.282364 TX Vref Scan disable
5015 23:09:00.282823 == TX Byte 0 ==
5016 23:09:00.285642 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5017 23:09:00.292277 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5018 23:09:00.292966 == TX Byte 1 ==
5019 23:09:00.295767 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5020 23:09:00.302255 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5021 23:09:00.302841 ==
5022 23:09:00.305707 Dram Type= 6, Freq= 0, CH_0, rank 0
5023 23:09:00.308641 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5024 23:09:00.309106 ==
5025 23:09:00.309477
5026 23:09:00.309810
5027 23:09:00.312107 TX Vref Scan disable
5028 23:09:00.315555 == TX Byte 0 ==
5029 23:09:00.319218 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5030 23:09:00.321938 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5031 23:09:00.326488 == TX Byte 1 ==
5032 23:09:00.329047 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5033 23:09:00.332334 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5034 23:09:00.332941
5035 23:09:00.333439 [DATLAT]
5036 23:09:00.335535 Freq=933, CH0 RK0
5037 23:09:00.336109
5038 23:09:00.338992 DATLAT Default: 0xd
5039 23:09:00.339567 0, 0xFFFF, sum = 0
5040 23:09:00.342136 1, 0xFFFF, sum = 0
5041 23:09:00.342725 2, 0xFFFF, sum = 0
5042 23:09:00.345114 3, 0xFFFF, sum = 0
5043 23:09:00.345601 4, 0xFFFF, sum = 0
5044 23:09:00.348682 5, 0xFFFF, sum = 0
5045 23:09:00.349260 6, 0xFFFF, sum = 0
5046 23:09:00.351735 7, 0xFFFF, sum = 0
5047 23:09:00.352218 8, 0xFFFF, sum = 0
5048 23:09:00.355499 9, 0xFFFF, sum = 0
5049 23:09:00.355986 10, 0x0, sum = 1
5050 23:09:00.358643 11, 0x0, sum = 2
5051 23:09:00.359129 12, 0x0, sum = 3
5052 23:09:00.362197 13, 0x0, sum = 4
5053 23:09:00.362778 best_step = 11
5054 23:09:00.363272
5055 23:09:00.363731 ==
5056 23:09:00.365097 Dram Type= 6, Freq= 0, CH_0, rank 0
5057 23:09:00.368402 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5058 23:09:00.372001 ==
5059 23:09:00.372664 RX Vref Scan: 1
5060 23:09:00.373163
5061 23:09:00.375739 RX Vref 0 -> 0, step: 1
5062 23:09:00.376316
5063 23:09:00.378084 RX Delay -69 -> 252, step: 4
5064 23:09:00.378544
5065 23:09:00.382383 Set Vref, RX VrefLevel [Byte0]: 47
5066 23:09:00.384865 [Byte1]: 48
5067 23:09:00.385423
5068 23:09:00.388605 Final RX Vref Byte 0 = 47 to rank0
5069 23:09:00.391423 Final RX Vref Byte 1 = 48 to rank0
5070 23:09:00.394917 Final RX Vref Byte 0 = 47 to rank1
5071 23:09:00.398504 Final RX Vref Byte 1 = 48 to rank1==
5072 23:09:00.401469 Dram Type= 6, Freq= 0, CH_0, rank 0
5073 23:09:00.404921 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5074 23:09:00.405402 ==
5075 23:09:00.408664 DQS Delay:
5076 23:09:00.409230 DQS0 = 0, DQS1 = 0
5077 23:09:00.409721 DQM Delay:
5078 23:09:00.411474 DQM0 = 97, DQM1 = 87
5079 23:09:00.412125 DQ Delay:
5080 23:09:00.414730 DQ0 =94, DQ1 =100, DQ2 =96, DQ3 =94
5081 23:09:00.418103 DQ4 =100, DQ5 =90, DQ6 =104, DQ7 =104
5082 23:09:00.421406 DQ8 =78, DQ9 =72, DQ10 =88, DQ11 =80
5083 23:09:00.424609 DQ12 =94, DQ13 =94, DQ14 =98, DQ15 =96
5084 23:09:00.425073
5085 23:09:00.425440
5086 23:09:00.434691 [DQSOSCAuto] RK0, (LSB)MR18= 0x1c1c, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 412 ps
5087 23:09:00.438056 CH0 RK0: MR19=505, MR18=1C1C
5088 23:09:00.441696 CH0_RK0: MR19=0x505, MR18=0x1C1C, DQSOSC=412, MR23=63, INC=63, DEC=42
5089 23:09:00.442274
5090 23:09:00.444625 ----->DramcWriteLeveling(PI) begin...
5091 23:09:00.447568 ==
5092 23:09:00.451220 Dram Type= 6, Freq= 0, CH_0, rank 1
5093 23:09:00.454654 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5094 23:09:00.455154 ==
5095 23:09:00.457771 Write leveling (Byte 0): 29 => 29
5096 23:09:00.461097 Write leveling (Byte 1): 28 => 28
5097 23:09:00.464697 DramcWriteLeveling(PI) end<-----
5098 23:09:00.465281
5099 23:09:00.465776 ==
5100 23:09:00.467625 Dram Type= 6, Freq= 0, CH_0, rank 1
5101 23:09:00.471185 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5102 23:09:00.471747 ==
5103 23:09:00.474212 [Gating] SW mode calibration
5104 23:09:00.481225 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5105 23:09:00.488319 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5106 23:09:00.491196 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5107 23:09:00.494237 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5108 23:09:00.501091 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5109 23:09:00.504618 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5110 23:09:00.507647 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5111 23:09:00.514372 0 10 20 | B1->B0 | 3333 3030 | 0 0 | (0 1) (0 1)
5112 23:09:00.517436 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5113 23:09:00.521005 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5114 23:09:00.524192 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5115 23:09:00.531011 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5116 23:09:00.534028 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5117 23:09:00.537499 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5118 23:09:00.544589 0 11 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5119 23:09:00.547507 0 11 20 | B1->B0 | 2d2d 3232 | 0 0 | (0 0) (0 0)
5120 23:09:00.550975 0 11 24 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
5121 23:09:00.557105 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5122 23:09:00.560682 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5123 23:09:00.567239 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5124 23:09:00.570321 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5125 23:09:00.573912 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5126 23:09:00.580093 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5127 23:09:00.583469 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5128 23:09:00.587070 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5129 23:09:00.590286 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 23:09:00.597304 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 23:09:00.600491 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 23:09:00.603536 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 23:09:00.609934 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 23:09:00.613015 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 23:09:00.619956 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 23:09:00.622943 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 23:09:00.626501 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 23:09:00.629668 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 23:09:00.636138 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 23:09:00.639573 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 23:09:00.646037 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 23:09:00.649302 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 23:09:00.652910 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5144 23:09:00.655906 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5145 23:09:00.662731 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5146 23:09:00.666254 Total UI for P1: 0, mck2ui 16
5147 23:09:00.669303 best dqsien dly found for B0: ( 0, 14, 22)
5148 23:09:00.672699 Total UI for P1: 0, mck2ui 16
5149 23:09:00.676047 best dqsien dly found for B1: ( 0, 14, 22)
5150 23:09:00.679519 best DQS0 dly(MCK, UI, PI) = (0, 14, 22)
5151 23:09:00.682824 best DQS1 dly(MCK, UI, PI) = (0, 14, 22)
5152 23:09:00.683395
5153 23:09:00.685920 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 22)
5154 23:09:00.689151 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 22)
5155 23:09:00.692738 [Gating] SW calibration Done
5156 23:09:00.693302 ==
5157 23:09:00.696222 Dram Type= 6, Freq= 0, CH_0, rank 1
5158 23:09:00.699606 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5159 23:09:00.700166 ==
5160 23:09:00.702939 RX Vref Scan: 0
5161 23:09:00.703497
5162 23:09:00.705576 RX Vref 0 -> 0, step: 1
5163 23:09:00.706036
5164 23:09:00.706399 RX Delay -80 -> 252, step: 8
5165 23:09:00.712445 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5166 23:09:00.715695 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5167 23:09:00.719341 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5168 23:09:00.722750 iDelay=208, Bit 3, Center 91 (0 ~ 183) 184
5169 23:09:00.725711 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5170 23:09:00.728851 iDelay=208, Bit 5, Center 87 (-16 ~ 191) 208
5171 23:09:00.735501 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5172 23:09:00.738978 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5173 23:09:00.742159 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5174 23:09:00.745343 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5175 23:09:00.748574 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5176 23:09:00.755310 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5177 23:09:00.758453 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5178 23:09:00.762010 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5179 23:09:00.765117 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5180 23:09:00.768735 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5181 23:09:00.769296 ==
5182 23:09:00.771793 Dram Type= 6, Freq= 0, CH_0, rank 1
5183 23:09:00.778486 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5184 23:09:00.779065 ==
5185 23:09:00.779442 DQS Delay:
5186 23:09:00.781562 DQS0 = 0, DQS1 = 0
5187 23:09:00.782021 DQM Delay:
5188 23:09:00.784816 DQM0 = 98, DQM1 = 86
5189 23:09:00.785278 DQ Delay:
5190 23:09:00.787957 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =91
5191 23:09:00.791717 DQ4 =103, DQ5 =87, DQ6 =107, DQ7 =107
5192 23:09:00.795025 DQ8 =71, DQ9 =67, DQ10 =91, DQ11 =79
5193 23:09:00.798556 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5194 23:09:00.799114
5195 23:09:00.799482
5196 23:09:00.799821 ==
5197 23:09:00.801172 Dram Type= 6, Freq= 0, CH_0, rank 1
5198 23:09:00.805271 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5199 23:09:00.805836 ==
5200 23:09:00.806207
5201 23:09:00.806550
5202 23:09:00.808359 TX Vref Scan disable
5203 23:09:00.811533 == TX Byte 0 ==
5204 23:09:00.814945 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5205 23:09:00.818023 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5206 23:09:00.821471 == TX Byte 1 ==
5207 23:09:00.824677 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5208 23:09:00.828213 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5209 23:09:00.828834 ==
5210 23:09:00.831345 Dram Type= 6, Freq= 0, CH_0, rank 1
5211 23:09:00.837963 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5212 23:09:00.838530 ==
5213 23:09:00.838904
5214 23:09:00.839240
5215 23:09:00.839566 TX Vref Scan disable
5216 23:09:00.841458 == TX Byte 0 ==
5217 23:09:00.844972 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5218 23:09:00.851994 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5219 23:09:00.852599 == TX Byte 1 ==
5220 23:09:00.854947 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5221 23:09:00.861465 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5222 23:09:00.861930
5223 23:09:00.862296 [DATLAT]
5224 23:09:00.862636 Freq=933, CH0 RK1
5225 23:09:00.862966
5226 23:09:00.864797 DATLAT Default: 0xb
5227 23:09:00.865256 0, 0xFFFF, sum = 0
5228 23:09:00.868256 1, 0xFFFF, sum = 0
5229 23:09:00.871700 2, 0xFFFF, sum = 0
5230 23:09:00.872261 3, 0xFFFF, sum = 0
5231 23:09:00.874742 4, 0xFFFF, sum = 0
5232 23:09:00.875304 5, 0xFFFF, sum = 0
5233 23:09:00.878270 6, 0xFFFF, sum = 0
5234 23:09:00.878831 7, 0xFFFF, sum = 0
5235 23:09:00.881342 8, 0xFFFF, sum = 0
5236 23:09:00.881808 9, 0xFFFF, sum = 0
5237 23:09:00.884637 10, 0x0, sum = 1
5238 23:09:00.885147 11, 0x0, sum = 2
5239 23:09:00.888104 12, 0x0, sum = 3
5240 23:09:00.888716 13, 0x0, sum = 4
5241 23:09:00.889270 best_step = 11
5242 23:09:00.889748
5243 23:09:00.891119 ==
5244 23:09:00.894879 Dram Type= 6, Freq= 0, CH_0, rank 1
5245 23:09:00.898508 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5246 23:09:00.899068 ==
5247 23:09:00.899440 RX Vref Scan: 0
5248 23:09:00.899782
5249 23:09:00.901629 RX Vref 0 -> 0, step: 1
5250 23:09:00.902179
5251 23:09:00.904681 RX Delay -77 -> 252, step: 4
5252 23:09:00.907807 iDelay=199, Bit 0, Center 94 (3 ~ 186) 184
5253 23:09:00.914611 iDelay=199, Bit 1, Center 98 (3 ~ 194) 192
5254 23:09:00.917836 iDelay=199, Bit 2, Center 96 (3 ~ 190) 188
5255 23:09:00.921048 iDelay=199, Bit 3, Center 92 (3 ~ 182) 180
5256 23:09:00.924562 iDelay=199, Bit 4, Center 100 (7 ~ 194) 188
5257 23:09:00.928027 iDelay=199, Bit 5, Center 88 (-5 ~ 182) 188
5258 23:09:00.931232 iDelay=199, Bit 6, Center 104 (15 ~ 194) 180
5259 23:09:00.937801 iDelay=199, Bit 7, Center 108 (19 ~ 198) 180
5260 23:09:00.941122 iDelay=199, Bit 8, Center 76 (-13 ~ 166) 180
5261 23:09:00.944202 iDelay=199, Bit 9, Center 72 (-17 ~ 162) 180
5262 23:09:00.947951 iDelay=199, Bit 10, Center 88 (-5 ~ 182) 188
5263 23:09:00.951260 iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176
5264 23:09:00.958145 iDelay=199, Bit 12, Center 94 (7 ~ 182) 176
5265 23:09:00.960766 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5266 23:09:00.964221 iDelay=199, Bit 14, Center 94 (3 ~ 186) 184
5267 23:09:00.967766 iDelay=199, Bit 15, Center 94 (3 ~ 186) 184
5268 23:09:00.968349 ==
5269 23:09:00.970707 Dram Type= 6, Freq= 0, CH_0, rank 1
5270 23:09:00.974548 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5271 23:09:00.977606 ==
5272 23:09:00.978162 DQS Delay:
5273 23:09:00.978530 DQS0 = 0, DQS1 = 0
5274 23:09:00.980669 DQM Delay:
5275 23:09:00.981132 DQM0 = 97, DQM1 = 85
5276 23:09:00.984176 DQ Delay:
5277 23:09:00.984787 DQ0 =94, DQ1 =98, DQ2 =96, DQ3 =92
5278 23:09:00.990904 DQ4 =100, DQ5 =88, DQ6 =104, DQ7 =108
5279 23:09:00.994071 DQ8 =76, DQ9 =72, DQ10 =88, DQ11 =78
5280 23:09:00.997448 DQ12 =94, DQ13 =90, DQ14 =94, DQ15 =94
5281 23:09:00.998030
5282 23:09:00.998401
5283 23:09:01.003985 [DQSOSCAuto] RK1, (LSB)MR18= 0x2c2c, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 408 ps
5284 23:09:01.007451 CH0 RK1: MR19=505, MR18=2C2C
5285 23:09:01.013931 CH0_RK1: MR19=0x505, MR18=0x2C2C, DQSOSC=408, MR23=63, INC=65, DEC=43
5286 23:09:01.017184 [RxdqsGatingPostProcess] freq 933
5287 23:09:01.020467 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5288 23:09:01.023921 Pre-setting of DQS Precalculation
5289 23:09:01.030642 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5290 23:09:01.031205 ==
5291 23:09:01.033806 Dram Type= 6, Freq= 0, CH_1, rank 0
5292 23:09:01.037259 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5293 23:09:01.037719 ==
5294 23:09:01.043634 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5295 23:09:01.050136 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5296 23:09:01.053520 [CA 0] Center 37 (7~68) winsize 62
5297 23:09:01.056707 [CA 1] Center 37 (6~68) winsize 63
5298 23:09:01.060039 [CA 2] Center 34 (4~65) winsize 62
5299 23:09:01.065701 [CA 3] Center 34 (4~65) winsize 62
5300 23:09:01.066813 [CA 4] Center 33 (2~64) winsize 63
5301 23:09:01.067270 [CA 5] Center 33 (3~64) winsize 62
5302 23:09:01.070331
5303 23:09:01.073814 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5304 23:09:01.074370
5305 23:09:01.076654 [CATrainingPosCal] consider 1 rank data
5306 23:09:01.079855 u2DelayCellTimex100 = 270/100 ps
5307 23:09:01.083509 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5308 23:09:01.086899 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5309 23:09:01.090171 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5310 23:09:01.093437 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5311 23:09:01.096877 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
5312 23:09:01.100170 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5313 23:09:01.100752
5314 23:09:01.103179 CA PerBit enable=1, Macro0, CA PI delay=33
5315 23:09:01.103734
5316 23:09:01.106886 [CBTSetCACLKResult] CA Dly = 33
5317 23:09:01.110282 CS Dly: 5 (0~36)
5318 23:09:01.110847 ==
5319 23:09:01.113547 Dram Type= 6, Freq= 0, CH_1, rank 1
5320 23:09:01.116337 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5321 23:09:01.116853 ==
5322 23:09:01.123427 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5323 23:09:01.130140 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5324 23:09:01.133435 [CA 0] Center 37 (6~68) winsize 63
5325 23:09:01.136968 [CA 1] Center 37 (6~68) winsize 63
5326 23:09:01.139979 [CA 2] Center 34 (4~65) winsize 62
5327 23:09:01.143642 [CA 3] Center 33 (3~64) winsize 62
5328 23:09:01.146322 [CA 4] Center 32 (2~63) winsize 62
5329 23:09:01.150088 [CA 5] Center 32 (2~63) winsize 62
5330 23:09:01.150649
5331 23:09:01.152855 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5332 23:09:01.153323
5333 23:09:01.156652 [CATrainingPosCal] consider 2 rank data
5334 23:09:01.159858 u2DelayCellTimex100 = 270/100 ps
5335 23:09:01.163199 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5336 23:09:01.166279 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5337 23:09:01.169892 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5338 23:09:01.172985 CA3 delay=34 (4~64),Diff = 2 PI (12 cell)
5339 23:09:01.176405 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
5340 23:09:01.179777 CA5 delay=33 (3~63),Diff = 1 PI (6 cell)
5341 23:09:01.180332
5342 23:09:01.186356 CA PerBit enable=1, Macro0, CA PI delay=32
5343 23:09:01.186920
5344 23:09:01.187285 [CBTSetCACLKResult] CA Dly = 32
5345 23:09:01.189544 CS Dly: 6 (0~38)
5346 23:09:01.190100
5347 23:09:01.192897 ----->DramcWriteLeveling(PI) begin...
5348 23:09:01.193454 ==
5349 23:09:01.195969 Dram Type= 6, Freq= 0, CH_1, rank 0
5350 23:09:01.199617 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5351 23:09:01.200180 ==
5352 23:09:01.202955 Write leveling (Byte 0): 25 => 25
5353 23:09:01.206341 Write leveling (Byte 1): 28 => 28
5354 23:09:01.209463 DramcWriteLeveling(PI) end<-----
5355 23:09:01.210023
5356 23:09:01.210391 ==
5357 23:09:01.212829 Dram Type= 6, Freq= 0, CH_1, rank 0
5358 23:09:01.219353 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5359 23:09:01.219818 ==
5360 23:09:01.220187 [Gating] SW mode calibration
5361 23:09:01.229481 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5362 23:09:01.233246 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5363 23:09:01.236000 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5364 23:09:01.242938 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5365 23:09:01.245790 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5366 23:09:01.249121 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5367 23:09:01.256017 0 10 16 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
5368 23:09:01.259252 0 10 20 | B1->B0 | 3232 2525 | 0 0 | (0 1) (1 0)
5369 23:09:01.262481 0 10 24 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
5370 23:09:01.269268 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5371 23:09:01.272456 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5372 23:09:01.275877 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5373 23:09:01.282683 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5374 23:09:01.285737 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5375 23:09:01.289359 0 11 16 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
5376 23:09:01.295379 0 11 20 | B1->B0 | 2828 4141 | 0 1 | (0 0) (0 0)
5377 23:09:01.298916 0 11 24 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
5378 23:09:01.302072 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5379 23:09:01.308695 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5380 23:09:01.311981 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5381 23:09:01.315019 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5382 23:09:01.321795 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5383 23:09:01.325508 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5384 23:09:01.328634 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5385 23:09:01.335422 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 23:09:01.338604 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 23:09:01.342022 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 23:09:01.348122 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 23:09:01.351321 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 23:09:01.355341 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 23:09:01.362352 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 23:09:01.364766 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5393 23:09:01.368166 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 23:09:01.375201 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 23:09:01.378479 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 23:09:01.381176 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5397 23:09:01.388312 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5398 23:09:01.391398 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5399 23:09:01.395079 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5400 23:09:01.401340 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5401 23:09:01.401921 Total UI for P1: 0, mck2ui 16
5402 23:09:01.408208 best dqsien dly found for B0: ( 0, 14, 16)
5403 23:09:01.411451 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5404 23:09:01.414697 Total UI for P1: 0, mck2ui 16
5405 23:09:01.417754 best dqsien dly found for B1: ( 0, 14, 20)
5406 23:09:01.421386 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5407 23:09:01.424808 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5408 23:09:01.425287
5409 23:09:01.427760 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5410 23:09:01.431444 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5411 23:09:01.434543 [Gating] SW calibration Done
5412 23:09:01.435103 ==
5413 23:09:01.437990 Dram Type= 6, Freq= 0, CH_1, rank 0
5414 23:09:01.441369 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5415 23:09:01.444771 ==
5416 23:09:01.445361 RX Vref Scan: 0
5417 23:09:01.445733
5418 23:09:01.447659 RX Vref 0 -> 0, step: 1
5419 23:09:01.448221
5420 23:09:01.450924 RX Delay -80 -> 252, step: 8
5421 23:09:01.454519 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5422 23:09:01.457702 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5423 23:09:01.460942 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5424 23:09:01.464502 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5425 23:09:01.470672 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5426 23:09:01.474144 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5427 23:09:01.477134 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5428 23:09:01.481118 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5429 23:09:01.483663 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5430 23:09:01.486992 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5431 23:09:01.494154 iDelay=208, Bit 10, Center 87 (-16 ~ 191) 208
5432 23:09:01.497134 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5433 23:09:01.500314 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5434 23:09:01.503824 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5435 23:09:01.506863 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5436 23:09:01.513517 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5437 23:09:01.514077 ==
5438 23:09:01.516866 Dram Type= 6, Freq= 0, CH_1, rank 0
5439 23:09:01.519990 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5440 23:09:01.520450 ==
5441 23:09:01.520875 DQS Delay:
5442 23:09:01.523419 DQS0 = 0, DQS1 = 0
5443 23:09:01.523973 DQM Delay:
5444 23:09:01.527214 DQM0 = 94, DQM1 = 87
5445 23:09:01.527781 DQ Delay:
5446 23:09:01.530084 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5447 23:09:01.533256 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5448 23:09:01.537137 DQ8 =71, DQ9 =79, DQ10 =87, DQ11 =79
5449 23:09:01.540302 DQ12 =95, DQ13 =99, DQ14 =91, DQ15 =99
5450 23:09:01.540894
5451 23:09:01.541263
5452 23:09:01.541603 ==
5453 23:09:01.543686 Dram Type= 6, Freq= 0, CH_1, rank 0
5454 23:09:01.547098 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5455 23:09:01.547665 ==
5456 23:09:01.550177
5457 23:09:01.550632
5458 23:09:01.550993 TX Vref Scan disable
5459 23:09:01.553494 == TX Byte 0 ==
5460 23:09:01.556680 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5461 23:09:01.559931 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5462 23:09:01.563517 == TX Byte 1 ==
5463 23:09:01.567045 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5464 23:09:01.570011 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5465 23:09:01.570473 ==
5466 23:09:01.573313 Dram Type= 6, Freq= 0, CH_1, rank 0
5467 23:09:01.579826 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5468 23:09:01.580392 ==
5469 23:09:01.580828
5470 23:09:01.581174
5471 23:09:01.581502 TX Vref Scan disable
5472 23:09:01.584182 == TX Byte 0 ==
5473 23:09:01.587910 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5474 23:09:01.594431 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5475 23:09:01.595000 == TX Byte 1 ==
5476 23:09:01.597699 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5477 23:09:01.604351 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5478 23:09:01.604956
5479 23:09:01.605327 [DATLAT]
5480 23:09:01.605669 Freq=933, CH1 RK0
5481 23:09:01.606000
5482 23:09:01.607770 DATLAT Default: 0xd
5483 23:09:01.608328 0, 0xFFFF, sum = 0
5484 23:09:01.610760 1, 0xFFFF, sum = 0
5485 23:09:01.611229 2, 0xFFFF, sum = 0
5486 23:09:01.614135 3, 0xFFFF, sum = 0
5487 23:09:01.617408 4, 0xFFFF, sum = 0
5488 23:09:01.617875 5, 0xFFFF, sum = 0
5489 23:09:01.621088 6, 0xFFFF, sum = 0
5490 23:09:01.621660 7, 0xFFFF, sum = 0
5491 23:09:01.624016 8, 0xFFFF, sum = 0
5492 23:09:01.624484 9, 0xFFFF, sum = 0
5493 23:09:01.627520 10, 0x0, sum = 1
5494 23:09:01.628086 11, 0x0, sum = 2
5495 23:09:01.630726 12, 0x0, sum = 3
5496 23:09:01.631332 13, 0x0, sum = 4
5497 23:09:01.631743 best_step = 11
5498 23:09:01.632092
5499 23:09:01.634030 ==
5500 23:09:01.637192 Dram Type= 6, Freq= 0, CH_1, rank 0
5501 23:09:01.640464 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5502 23:09:01.640962 ==
5503 23:09:01.641328 RX Vref Scan: 1
5504 23:09:01.641863
5505 23:09:01.644019 RX Vref 0 -> 0, step: 1
5506 23:09:01.644632
5507 23:09:01.647306 RX Delay -69 -> 252, step: 4
5508 23:09:01.647766
5509 23:09:01.650926 Set Vref, RX VrefLevel [Byte0]: 55
5510 23:09:01.654063 [Byte1]: 48
5511 23:09:01.654639
5512 23:09:01.657471 Final RX Vref Byte 0 = 55 to rank0
5513 23:09:01.660805 Final RX Vref Byte 1 = 48 to rank0
5514 23:09:01.664042 Final RX Vref Byte 0 = 55 to rank1
5515 23:09:01.667335 Final RX Vref Byte 1 = 48 to rank1==
5516 23:09:01.670580 Dram Type= 6, Freq= 0, CH_1, rank 0
5517 23:09:01.673992 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5518 23:09:01.676823 ==
5519 23:09:01.677302 DQS Delay:
5520 23:09:01.677777 DQS0 = 0, DQS1 = 0
5521 23:09:01.680196 DQM Delay:
5522 23:09:01.680717 DQM0 = 94, DQM1 = 88
5523 23:09:01.683498 DQ Delay:
5524 23:09:01.686742 DQ0 =98, DQ1 =90, DQ2 =86, DQ3 =92
5525 23:09:01.690310 DQ4 =92, DQ5 =104, DQ6 =102, DQ7 =92
5526 23:09:01.690785 DQ8 =72, DQ9 =76, DQ10 =90, DQ11 =80
5527 23:09:01.696715 DQ12 =94, DQ13 =98, DQ14 =96, DQ15 =98
5528 23:09:01.697188
5529 23:09:01.697664
5530 23:09:01.703451 [DQSOSCAuto] RK0, (LSB)MR18= 0x3939, (MSB)MR19= 0x505, tDQSOscB0 = 404 ps tDQSOscB1 = 404 ps
5531 23:09:01.707117 CH1 RK0: MR19=505, MR18=3939
5532 23:09:01.713430 CH1_RK0: MR19=0x505, MR18=0x3939, DQSOSC=404, MR23=63, INC=66, DEC=44
5533 23:09:01.713986
5534 23:09:01.716905 ----->DramcWriteLeveling(PI) begin...
5535 23:09:01.717390 ==
5536 23:09:01.719966 Dram Type= 6, Freq= 0, CH_1, rank 1
5537 23:09:01.723447 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5538 23:09:01.723926 ==
5539 23:09:01.727045 Write leveling (Byte 0): 26 => 26
5540 23:09:01.730315 Write leveling (Byte 1): 25 => 25
5541 23:09:01.733474 DramcWriteLeveling(PI) end<-----
5542 23:09:01.734048
5543 23:09:01.734535 ==
5544 23:09:01.737168 Dram Type= 6, Freq= 0, CH_1, rank 1
5545 23:09:01.740265 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5546 23:09:01.740902 ==
5547 23:09:01.743712 [Gating] SW mode calibration
5548 23:09:01.749982 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5549 23:09:01.756548 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5550 23:09:01.759888 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5551 23:09:01.766555 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5552 23:09:01.770279 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5553 23:09:01.773270 0 10 12 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
5554 23:09:01.776497 0 10 16 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 0)
5555 23:09:01.783177 0 10 20 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)
5556 23:09:01.786791 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5557 23:09:01.789986 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5558 23:09:01.796781 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5559 23:09:01.799970 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5560 23:09:01.803249 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5561 23:09:01.809674 0 11 12 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
5562 23:09:01.813290 0 11 16 | B1->B0 | 2525 3939 | 0 0 | (0 0) (0 0)
5563 23:09:01.816304 0 11 20 | B1->B0 | 3333 4646 | 1 0 | (0 0) (0 0)
5564 23:09:01.823060 0 11 24 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5565 23:09:01.826410 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5566 23:09:01.829559 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5567 23:09:01.836126 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5568 23:09:01.839560 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5569 23:09:01.842718 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5570 23:09:01.849250 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5571 23:09:01.852837 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5572 23:09:01.855892 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5573 23:09:01.862495 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5574 23:09:01.865905 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5575 23:09:01.869238 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5576 23:09:01.875822 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5577 23:09:01.879330 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5578 23:09:01.882514 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5579 23:09:01.889270 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5580 23:09:01.892378 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5581 23:09:01.895668 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5582 23:09:01.902080 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 23:09:01.905825 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 23:09:01.908960 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 23:09:01.915214 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 23:09:01.918780 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 23:09:01.921832 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5588 23:09:01.925295 Total UI for P1: 0, mck2ui 16
5589 23:09:01.928681 best dqsien dly found for B0: ( 0, 14, 18)
5590 23:09:01.932063 Total UI for P1: 0, mck2ui 16
5591 23:09:01.935332 best dqsien dly found for B1: ( 0, 14, 18)
5592 23:09:01.938697 best DQS0 dly(MCK, UI, PI) = (0, 14, 18)
5593 23:09:01.942065 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5594 23:09:01.942625
5595 23:09:01.948179 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 18)
5596 23:09:01.951623 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5597 23:09:01.954976 [Gating] SW calibration Done
5598 23:09:01.955539 ==
5599 23:09:01.958101 Dram Type= 6, Freq= 0, CH_1, rank 1
5600 23:09:01.961511 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5601 23:09:01.961973 ==
5602 23:09:01.962338 RX Vref Scan: 0
5603 23:09:01.964837
5604 23:09:01.965292 RX Vref 0 -> 0, step: 1
5605 23:09:01.965656
5606 23:09:01.968429 RX Delay -80 -> 252, step: 8
5607 23:09:01.971488 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5608 23:09:01.974474 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5609 23:09:01.981134 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5610 23:09:01.984971 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5611 23:09:01.988179 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5612 23:09:01.991591 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5613 23:09:01.995014 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5614 23:09:01.998299 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5615 23:09:02.004291 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5616 23:09:02.007961 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5617 23:09:02.011384 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5618 23:09:02.014794 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5619 23:09:02.017653 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5620 23:09:02.024192 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5621 23:09:02.027766 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5622 23:09:02.030914 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5623 23:09:02.031377 ==
5624 23:09:02.034418 Dram Type= 6, Freq= 0, CH_1, rank 1
5625 23:09:02.037771 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5626 23:09:02.038334 ==
5627 23:09:02.040909 DQS Delay:
5628 23:09:02.041472 DQS0 = 0, DQS1 = 0
5629 23:09:02.044069 DQM Delay:
5630 23:09:02.044691 DQM0 = 94, DQM1 = 87
5631 23:09:02.045076 DQ Delay:
5632 23:09:02.047402 DQ0 =99, DQ1 =91, DQ2 =87, DQ3 =91
5633 23:09:02.050751 DQ4 =91, DQ5 =107, DQ6 =99, DQ7 =91
5634 23:09:02.053986 DQ8 =75, DQ9 =75, DQ10 =87, DQ11 =75
5635 23:09:02.057320 DQ12 =99, DQ13 =99, DQ14 =91, DQ15 =95
5636 23:09:02.057885
5637 23:09:02.058249
5638 23:09:02.060441 ==
5639 23:09:02.064096 Dram Type= 6, Freq= 0, CH_1, rank 1
5640 23:09:02.067277 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5641 23:09:02.067841 ==
5642 23:09:02.068210
5643 23:09:02.068599
5644 23:09:02.070523 TX Vref Scan disable
5645 23:09:02.070983 == TX Byte 0 ==
5646 23:09:02.073715 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5647 23:09:02.080888 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5648 23:09:02.081459 == TX Byte 1 ==
5649 23:09:02.083917 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5650 23:09:02.090426 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5651 23:09:02.090987 ==
5652 23:09:02.093802 Dram Type= 6, Freq= 0, CH_1, rank 1
5653 23:09:02.097468 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5654 23:09:02.098031 ==
5655 23:09:02.098402
5656 23:09:02.098740
5657 23:09:02.100487 TX Vref Scan disable
5658 23:09:02.104061 == TX Byte 0 ==
5659 23:09:02.106966 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5660 23:09:02.110768 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5661 23:09:02.113449 == TX Byte 1 ==
5662 23:09:02.116746 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5663 23:09:02.120005 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5664 23:09:02.120479
5665 23:09:02.123761 [DATLAT]
5666 23:09:02.124320 Freq=933, CH1 RK1
5667 23:09:02.124735
5668 23:09:02.126560 DATLAT Default: 0xb
5669 23:09:02.127025 0, 0xFFFF, sum = 0
5670 23:09:02.130715 1, 0xFFFF, sum = 0
5671 23:09:02.131284 2, 0xFFFF, sum = 0
5672 23:09:02.133210 3, 0xFFFF, sum = 0
5673 23:09:02.133677 4, 0xFFFF, sum = 0
5674 23:09:02.136950 5, 0xFFFF, sum = 0
5675 23:09:02.137520 6, 0xFFFF, sum = 0
5676 23:09:02.139721 7, 0xFFFF, sum = 0
5677 23:09:02.140188 8, 0xFFFF, sum = 0
5678 23:09:02.143196 9, 0xFFFF, sum = 0
5679 23:09:02.143802 10, 0x0, sum = 1
5680 23:09:02.146607 11, 0x0, sum = 2
5681 23:09:02.147078 12, 0x0, sum = 3
5682 23:09:02.149878 13, 0x0, sum = 4
5683 23:09:02.150448 best_step = 11
5684 23:09:02.150814
5685 23:09:02.151152 ==
5686 23:09:02.153051 Dram Type= 6, Freq= 0, CH_1, rank 1
5687 23:09:02.159758 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5688 23:09:02.160327 ==
5689 23:09:02.160743 RX Vref Scan: 0
5690 23:09:02.161086
5691 23:09:02.162867 RX Vref 0 -> 0, step: 1
5692 23:09:02.163326
5693 23:09:02.166251 RX Delay -69 -> 252, step: 4
5694 23:09:02.169367 iDelay=203, Bit 0, Center 98 (7 ~ 190) 184
5695 23:09:02.172705 iDelay=203, Bit 1, Center 92 (-1 ~ 186) 188
5696 23:09:02.179613 iDelay=203, Bit 2, Center 86 (-9 ~ 182) 192
5697 23:09:02.183296 iDelay=203, Bit 3, Center 92 (-1 ~ 186) 188
5698 23:09:02.186576 iDelay=203, Bit 4, Center 98 (3 ~ 194) 192
5699 23:09:02.189747 iDelay=203, Bit 5, Center 106 (11 ~ 202) 192
5700 23:09:02.193133 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5701 23:09:02.196372 iDelay=203, Bit 7, Center 96 (3 ~ 190) 188
5702 23:09:02.203125 iDelay=203, Bit 8, Center 74 (-17 ~ 166) 184
5703 23:09:02.206409 iDelay=203, Bit 9, Center 76 (-17 ~ 170) 188
5704 23:09:02.209465 iDelay=203, Bit 10, Center 86 (-5 ~ 178) 184
5705 23:09:02.213127 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5706 23:09:02.216135 iDelay=203, Bit 12, Center 96 (3 ~ 190) 188
5707 23:09:02.222963 iDelay=203, Bit 13, Center 98 (11 ~ 186) 176
5708 23:09:02.226377 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5709 23:09:02.229612 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5710 23:09:02.230173 ==
5711 23:09:02.233026 Dram Type= 6, Freq= 0, CH_1, rank 1
5712 23:09:02.236275 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5713 23:09:02.236882 ==
5714 23:09:02.239595 DQS Delay:
5715 23:09:02.240153 DQS0 = 0, DQS1 = 0
5716 23:09:02.240554 DQM Delay:
5717 23:09:02.242694 DQM0 = 96, DQM1 = 87
5718 23:09:02.243252 DQ Delay:
5719 23:09:02.245993 DQ0 =98, DQ1 =92, DQ2 =86, DQ3 =92
5720 23:09:02.249324 DQ4 =98, DQ5 =106, DQ6 =104, DQ7 =96
5721 23:09:02.252612 DQ8 =74, DQ9 =76, DQ10 =86, DQ11 =80
5722 23:09:02.256351 DQ12 =96, DQ13 =98, DQ14 =96, DQ15 =96
5723 23:09:02.256959
5724 23:09:02.257325
5725 23:09:02.265628 [DQSOSCAuto] RK1, (LSB)MR18= 0x2222, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 411 ps
5726 23:09:02.268913 CH1 RK1: MR19=505, MR18=2222
5727 23:09:02.275966 CH1_RK1: MR19=0x505, MR18=0x2222, DQSOSC=411, MR23=63, INC=64, DEC=42
5728 23:09:02.276592 [RxdqsGatingPostProcess] freq 933
5729 23:09:02.282616 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5730 23:09:02.285527 Pre-setting of DQS Precalculation
5731 23:09:02.289137 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5732 23:09:02.299057 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5733 23:09:02.305657 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5734 23:09:02.306220
5735 23:09:02.306593
5736 23:09:02.308755 [Calibration Summary] 1866 Mbps
5737 23:09:02.309213 CH 0, Rank 0
5738 23:09:02.312279 SW Impedance : PASS
5739 23:09:02.312890 DUTY Scan : NO K
5740 23:09:02.315772 ZQ Calibration : PASS
5741 23:09:02.318674 Jitter Meter : NO K
5742 23:09:02.319108 CBT Training : PASS
5743 23:09:02.322225 Write leveling : PASS
5744 23:09:02.325439 RX DQS gating : PASS
5745 23:09:02.325900 RX DQ/DQS(RDDQC) : PASS
5746 23:09:02.328755 TX DQ/DQS : PASS
5747 23:09:02.332070 RX DATLAT : PASS
5748 23:09:02.332668 RX DQ/DQS(Engine): PASS
5749 23:09:02.335366 TX OE : NO K
5750 23:09:02.335926 All Pass.
5751 23:09:02.336294
5752 23:09:02.338584 CH 0, Rank 1
5753 23:09:02.339041 SW Impedance : PASS
5754 23:09:02.341957 DUTY Scan : NO K
5755 23:09:02.345463 ZQ Calibration : PASS
5756 23:09:02.346022 Jitter Meter : NO K
5757 23:09:02.348548 CBT Training : PASS
5758 23:09:02.351747 Write leveling : PASS
5759 23:09:02.352208 RX DQS gating : PASS
5760 23:09:02.355239 RX DQ/DQS(RDDQC) : PASS
5761 23:09:02.358609 TX DQ/DQS : PASS
5762 23:09:02.359179 RX DATLAT : PASS
5763 23:09:02.361689 RX DQ/DQS(Engine): PASS
5764 23:09:02.362147 TX OE : NO K
5765 23:09:02.364975 All Pass.
5766 23:09:02.365528
5767 23:09:02.366059 CH 1, Rank 0
5768 23:09:02.368372 SW Impedance : PASS
5769 23:09:02.368913 DUTY Scan : NO K
5770 23:09:02.371917 ZQ Calibration : PASS
5771 23:09:02.375116 Jitter Meter : NO K
5772 23:09:02.375679 CBT Training : PASS
5773 23:09:02.378397 Write leveling : PASS
5774 23:09:02.381592 RX DQS gating : PASS
5775 23:09:02.382057 RX DQ/DQS(RDDQC) : PASS
5776 23:09:02.384957 TX DQ/DQS : PASS
5777 23:09:02.388136 RX DATLAT : PASS
5778 23:09:02.388737 RX DQ/DQS(Engine): PASS
5779 23:09:02.391792 TX OE : NO K
5780 23:09:02.392353 All Pass.
5781 23:09:02.392794
5782 23:09:02.395162 CH 1, Rank 1
5783 23:09:02.395720 SW Impedance : PASS
5784 23:09:02.398123 DUTY Scan : NO K
5785 23:09:02.401592 ZQ Calibration : PASS
5786 23:09:02.402151 Jitter Meter : NO K
5787 23:09:02.405029 CBT Training : PASS
5788 23:09:02.408264 Write leveling : PASS
5789 23:09:02.408884 RX DQS gating : PASS
5790 23:09:02.411516 RX DQ/DQS(RDDQC) : PASS
5791 23:09:02.414596 TX DQ/DQS : PASS
5792 23:09:02.415060 RX DATLAT : PASS
5793 23:09:02.417938 RX DQ/DQS(Engine): PASS
5794 23:09:02.418396 TX OE : NO K
5795 23:09:02.421281 All Pass.
5796 23:09:02.421735
5797 23:09:02.422097 DramC Write-DBI off
5798 23:09:02.425099 PER_BANK_REFRESH: Hybrid Mode
5799 23:09:02.427887 TX_TRACKING: ON
5800 23:09:02.435290 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5801 23:09:02.437971 [FAST_K] Save calibration result to emmc
5802 23:09:02.444814 dramc_set_vcore_voltage set vcore to 650000
5803 23:09:02.445374 Read voltage for 400, 6
5804 23:09:02.448027 Vio18 = 0
5805 23:09:02.448639 Vcore = 650000
5806 23:09:02.449018 Vdram = 0
5807 23:09:02.449362 Vddq = 0
5808 23:09:02.451042 Vmddr = 0
5809 23:09:02.454704 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5810 23:09:02.461340 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5811 23:09:02.464902 MEM_TYPE=3, freq_sel=20
5812 23:09:02.465466 sv_algorithm_assistance_LP4_800
5813 23:09:02.471209 ============ PULL DRAM RESETB DOWN ============
5814 23:09:02.474634 ========== PULL DRAM RESETB DOWN end =========
5815 23:09:02.477621 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5816 23:09:02.481021 ===================================
5817 23:09:02.484178 LPDDR4 DRAM CONFIGURATION
5818 23:09:02.487639 ===================================
5819 23:09:02.491179 EX_ROW_EN[0] = 0x0
5820 23:09:02.491758 EX_ROW_EN[1] = 0x0
5821 23:09:02.494353 LP4Y_EN = 0x0
5822 23:09:02.494829 WORK_FSP = 0x0
5823 23:09:02.497186 WL = 0x2
5824 23:09:02.497656 RL = 0x2
5825 23:09:02.500654 BL = 0x2
5826 23:09:02.501238 RPST = 0x0
5827 23:09:02.504453 RD_PRE = 0x0
5828 23:09:02.505069 WR_PRE = 0x1
5829 23:09:02.507382 WR_PST = 0x0
5830 23:09:02.507956 DBI_WR = 0x0
5831 23:09:02.510841 DBI_RD = 0x0
5832 23:09:02.513861 OTF = 0x1
5833 23:09:02.517217 ===================================
5834 23:09:02.520688 ===================================
5835 23:09:02.521289 ANA top config
5836 23:09:02.524077 ===================================
5837 23:09:02.527311 DLL_ASYNC_EN = 0
5838 23:09:02.530633 ALL_SLAVE_EN = 1
5839 23:09:02.531202 NEW_RANK_MODE = 1
5840 23:09:02.534140 DLL_IDLE_MODE = 1
5841 23:09:02.537222 LP45_APHY_COMB_EN = 1
5842 23:09:02.540643 TX_ODT_DIS = 1
5843 23:09:02.541128 NEW_8X_MODE = 1
5844 23:09:02.544139 ===================================
5845 23:09:02.547553 ===================================
5846 23:09:02.550514 data_rate = 800
5847 23:09:02.553896 CKR = 1
5848 23:09:02.557476 DQ_P2S_RATIO = 4
5849 23:09:02.560799 ===================================
5850 23:09:02.564370 CA_P2S_RATIO = 4
5851 23:09:02.567149 DQ_CA_OPEN = 0
5852 23:09:02.567615 DQ_SEMI_OPEN = 1
5853 23:09:02.570570 CA_SEMI_OPEN = 1
5854 23:09:02.573727 CA_FULL_RATE = 0
5855 23:09:02.576848 DQ_CKDIV4_EN = 0
5856 23:09:02.580249 CA_CKDIV4_EN = 1
5857 23:09:02.583814 CA_PREDIV_EN = 0
5858 23:09:02.584276 PH8_DLY = 0
5859 23:09:02.587027 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5860 23:09:02.590495 DQ_AAMCK_DIV = 0
5861 23:09:02.593496 CA_AAMCK_DIV = 0
5862 23:09:02.596898 CA_ADMCK_DIV = 4
5863 23:09:02.600430 DQ_TRACK_CA_EN = 0
5864 23:09:02.601033 CA_PICK = 800
5865 23:09:02.603620 CA_MCKIO = 400
5866 23:09:02.606780 MCKIO_SEMI = 400
5867 23:09:02.610262 PLL_FREQ = 3016
5868 23:09:02.613250 DQ_UI_PI_RATIO = 32
5869 23:09:02.616963 CA_UI_PI_RATIO = 32
5870 23:09:02.620031 ===================================
5871 23:09:02.623420 ===================================
5872 23:09:02.626666 memory_type:LPDDR4
5873 23:09:02.627124 GP_NUM : 10
5874 23:09:02.630144 SRAM_EN : 1
5875 23:09:02.630754 MD32_EN : 0
5876 23:09:02.633480 ===================================
5877 23:09:02.636797 [ANA_INIT] >>>>>>>>>>>>>>
5878 23:09:02.639724 <<<<<< [CONFIGURE PHASE]: ANA_TX
5879 23:09:02.643338 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5880 23:09:02.646743 ===================================
5881 23:09:02.649637 data_rate = 800,PCW = 0X7400
5882 23:09:02.652901 ===================================
5883 23:09:02.656052 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5884 23:09:02.663231 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5885 23:09:02.672987 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5886 23:09:02.675973 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5887 23:09:02.679881 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5888 23:09:02.682732 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5889 23:09:02.686402 [ANA_INIT] flow start
5890 23:09:02.689385 [ANA_INIT] PLL >>>>>>>>
5891 23:09:02.689844 [ANA_INIT] PLL <<<<<<<<
5892 23:09:02.692829 [ANA_INIT] MIDPI >>>>>>>>
5893 23:09:02.696167 [ANA_INIT] MIDPI <<<<<<<<
5894 23:09:02.699309 [ANA_INIT] DLL >>>>>>>>
5895 23:09:02.699768 [ANA_INIT] flow end
5896 23:09:02.702881 ============ LP4 DIFF to SE enter ============
5897 23:09:02.709492 ============ LP4 DIFF to SE exit ============
5898 23:09:02.710058 [ANA_INIT] <<<<<<<<<<<<<
5899 23:09:02.712834 [Flow] Enable top DCM control >>>>>
5900 23:09:02.716067 [Flow] Enable top DCM control <<<<<
5901 23:09:02.719280 Enable DLL master slave shuffle
5902 23:09:02.725852 ==============================================================
5903 23:09:02.726422 Gating Mode config
5904 23:09:02.733189 ==============================================================
5905 23:09:02.735944 Config description:
5906 23:09:02.743013 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5907 23:09:02.749370 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5908 23:09:02.756026 SELPH_MODE 0: By rank 1: By Phase
5909 23:09:02.762489 ==============================================================
5910 23:09:02.765714 GAT_TRACK_EN = 0
5911 23:09:02.766175 RX_GATING_MODE = 2
5912 23:09:02.769112 RX_GATING_TRACK_MODE = 2
5913 23:09:02.772473 SELPH_MODE = 1
5914 23:09:02.775730 PICG_EARLY_EN = 1
5915 23:09:02.779612 VALID_LAT_VALUE = 1
5916 23:09:02.785984 ==============================================================
5917 23:09:02.789496 Enter into Gating configuration >>>>
5918 23:09:02.792623 Exit from Gating configuration <<<<
5919 23:09:02.795762 Enter into DVFS_PRE_config >>>>>
5920 23:09:02.805604 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5921 23:09:02.808886 Exit from DVFS_PRE_config <<<<<
5922 23:09:02.812229 Enter into PICG configuration >>>>
5923 23:09:02.815718 Exit from PICG configuration <<<<
5924 23:09:02.818817 [RX_INPUT] configuration >>>>>
5925 23:09:02.822093 [RX_INPUT] configuration <<<<<
5926 23:09:02.825455 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5927 23:09:02.832057 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5928 23:09:02.838555 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5929 23:09:02.845427 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5930 23:09:02.848650 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5931 23:09:02.855817 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5932 23:09:02.858699 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5933 23:09:02.865192 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5934 23:09:02.868319 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5935 23:09:02.871614 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5936 23:09:02.875113 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5937 23:09:02.881485 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5938 23:09:02.885024 ===================================
5939 23:09:02.885492 LPDDR4 DRAM CONFIGURATION
5940 23:09:02.888662 ===================================
5941 23:09:02.892260 EX_ROW_EN[0] = 0x0
5942 23:09:02.895276 EX_ROW_EN[1] = 0x0
5943 23:09:02.895844 LP4Y_EN = 0x0
5944 23:09:02.898367 WORK_FSP = 0x0
5945 23:09:02.898836 WL = 0x2
5946 23:09:02.902060 RL = 0x2
5947 23:09:02.902639 BL = 0x2
5948 23:09:02.905484 RPST = 0x0
5949 23:09:02.906057 RD_PRE = 0x0
5950 23:09:02.908610 WR_PRE = 0x1
5951 23:09:02.909181 WR_PST = 0x0
5952 23:09:02.911932 DBI_WR = 0x0
5953 23:09:02.912552 DBI_RD = 0x0
5954 23:09:02.915036 OTF = 0x1
5955 23:09:02.918044 ===================================
5956 23:09:02.921404 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5957 23:09:02.925324 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5958 23:09:02.931533 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5959 23:09:02.934946 ===================================
5960 23:09:02.935506 LPDDR4 DRAM CONFIGURATION
5961 23:09:02.938424 ===================================
5962 23:09:02.941552 EX_ROW_EN[0] = 0x10
5963 23:09:02.944433 EX_ROW_EN[1] = 0x0
5964 23:09:02.944944 LP4Y_EN = 0x0
5965 23:09:02.948363 WORK_FSP = 0x0
5966 23:09:02.949142 WL = 0x2
5967 23:09:02.951216 RL = 0x2
5968 23:09:02.951810 BL = 0x2
5969 23:09:02.954523 RPST = 0x0
5970 23:09:02.955152 RD_PRE = 0x0
5971 23:09:02.958062 WR_PRE = 0x1
5972 23:09:02.958541 WR_PST = 0x0
5973 23:09:02.961325 DBI_WR = 0x0
5974 23:09:02.961786 DBI_RD = 0x0
5975 23:09:02.964596 OTF = 0x1
5976 23:09:02.967953 ===================================
5977 23:09:02.974359 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5978 23:09:02.977982 nWR fixed to 30
5979 23:09:02.978549 [ModeRegInit_LP4] CH0 RK0
5980 23:09:02.981050 [ModeRegInit_LP4] CH0 RK1
5981 23:09:02.984687 [ModeRegInit_LP4] CH1 RK0
5982 23:09:02.987833 [ModeRegInit_LP4] CH1 RK1
5983 23:09:02.988391 match AC timing 18
5984 23:09:02.994438 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
5985 23:09:02.997679 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5986 23:09:03.001277 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
5987 23:09:03.007538 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
5988 23:09:03.011401 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
5989 23:09:03.011971 ==
5990 23:09:03.014349 Dram Type= 6, Freq= 0, CH_0, rank 0
5991 23:09:03.017849 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
5992 23:09:03.018331 ==
5993 23:09:03.024653 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
5994 23:09:03.030797 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5995 23:09:03.034269 [CA 0] Center 36 (8~64) winsize 57
5996 23:09:03.034828 [CA 1] Center 36 (8~64) winsize 57
5997 23:09:03.037443 [CA 2] Center 36 (8~64) winsize 57
5998 23:09:03.040609 [CA 3] Center 36 (8~64) winsize 57
5999 23:09:03.044577 [CA 4] Center 36 (8~64) winsize 57
6000 23:09:03.047706 [CA 5] Center 36 (8~64) winsize 57
6001 23:09:03.048267
6002 23:09:03.050843 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6003 23:09:03.051402
6004 23:09:03.057418 [CATrainingPosCal] consider 1 rank data
6005 23:09:03.057990 u2DelayCellTimex100 = 270/100 ps
6006 23:09:03.064007 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6007 23:09:03.066961 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6008 23:09:03.070706 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6009 23:09:03.073443 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6010 23:09:03.077169 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6011 23:09:03.080248 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6012 23:09:03.080922
6013 23:09:03.083823 CA PerBit enable=1, Macro0, CA PI delay=36
6014 23:09:03.084398
6015 23:09:03.086812 [CBTSetCACLKResult] CA Dly = 36
6016 23:09:03.090201 CS Dly: 1 (0~32)
6017 23:09:03.090665 ==
6018 23:09:03.093705 Dram Type= 6, Freq= 0, CH_0, rank 1
6019 23:09:03.096781 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6020 23:09:03.097347 ==
6021 23:09:03.103625 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6022 23:09:03.106961 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6023 23:09:03.110043 [CA 0] Center 36 (8~64) winsize 57
6024 23:09:03.113226 [CA 1] Center 36 (8~64) winsize 57
6025 23:09:03.117062 [CA 2] Center 36 (8~64) winsize 57
6026 23:09:03.119786 [CA 3] Center 36 (8~64) winsize 57
6027 23:09:03.123604 [CA 4] Center 36 (8~64) winsize 57
6028 23:09:03.126829 [CA 5] Center 36 (8~64) winsize 57
6029 23:09:03.127290
6030 23:09:03.129871 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6031 23:09:03.130330
6032 23:09:03.133440 [CATrainingPosCal] consider 2 rank data
6033 23:09:03.136610 u2DelayCellTimex100 = 270/100 ps
6034 23:09:03.140222 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6035 23:09:03.143124 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6036 23:09:03.149774 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6037 23:09:03.152977 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6038 23:09:03.156094 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6039 23:09:03.160042 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6040 23:09:03.160668
6041 23:09:03.162828 CA PerBit enable=1, Macro0, CA PI delay=36
6042 23:09:03.163298
6043 23:09:03.166510 [CBTSetCACLKResult] CA Dly = 36
6044 23:09:03.166984 CS Dly: 1 (0~32)
6045 23:09:03.167468
6046 23:09:03.169700 ----->DramcWriteLeveling(PI) begin...
6047 23:09:03.172548 ==
6048 23:09:03.176230 Dram Type= 6, Freq= 0, CH_0, rank 0
6049 23:09:03.179904 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6050 23:09:03.180466 ==
6051 23:09:03.182975 Write leveling (Byte 0): 32 => 0
6052 23:09:03.186460 Write leveling (Byte 1): 32 => 0
6053 23:09:03.189361 DramcWriteLeveling(PI) end<-----
6054 23:09:03.189838
6055 23:09:03.190316 ==
6056 23:09:03.192713 Dram Type= 6, Freq= 0, CH_0, rank 0
6057 23:09:03.196281 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6058 23:09:03.196911 ==
6059 23:09:03.199183 [Gating] SW mode calibration
6060 23:09:03.206220 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6061 23:09:03.209158 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6062 23:09:03.215857 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6063 23:09:03.219158 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6064 23:09:03.222574 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6065 23:09:03.229264 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6066 23:09:03.232430 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6067 23:09:03.235736 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6068 23:09:03.242553 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6069 23:09:03.245868 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
6070 23:09:03.249438 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6071 23:09:03.252327 Total UI for P1: 0, mck2ui 16
6072 23:09:03.255924 best dqsien dly found for B0: ( 0, 10, 16)
6073 23:09:03.259094 Total UI for P1: 0, mck2ui 16
6074 23:09:03.262443 best dqsien dly found for B1: ( 0, 10, 24)
6075 23:09:03.265682 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6076 23:09:03.272187 best DQS1 dly(MCK, UI, PI) = (0, 10, 24)
6077 23:09:03.272791
6078 23:09:03.275585 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6079 23:09:03.278915 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24)
6080 23:09:03.281998 [Gating] SW calibration Done
6081 23:09:03.282585 ==
6082 23:09:03.286176 Dram Type= 6, Freq= 0, CH_0, rank 0
6083 23:09:03.289232 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6084 23:09:03.289711 ==
6085 23:09:03.292591 RX Vref Scan: 0
6086 23:09:03.293161
6087 23:09:03.293647 RX Vref 0 -> 0, step: 1
6088 23:09:03.294104
6089 23:09:03.295527 RX Delay -410 -> 252, step: 16
6090 23:09:03.298748 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6091 23:09:03.305725 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6092 23:09:03.308603 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6093 23:09:03.312042 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6094 23:09:03.315227 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6095 23:09:03.321757 iDelay=230, Bit 5, Center -51 (-298 ~ 197) 496
6096 23:09:03.325353 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6097 23:09:03.328435 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6098 23:09:03.331942 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6099 23:09:03.338790 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6100 23:09:03.341935 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6101 23:09:03.345192 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6102 23:09:03.351835 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6103 23:09:03.355338 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6104 23:09:03.358617 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6105 23:09:03.361810 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6106 23:09:03.362367 ==
6107 23:09:03.365289 Dram Type= 6, Freq= 0, CH_0, rank 0
6108 23:09:03.371747 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6109 23:09:03.372301 ==
6110 23:09:03.372780 DQS Delay:
6111 23:09:03.375408 DQS0 = 51, DQS1 = 59
6112 23:09:03.375967 DQM Delay:
6113 23:09:03.376339 DQM0 = 12, DQM1 = 16
6114 23:09:03.378354 DQ Delay:
6115 23:09:03.381587 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6116 23:09:03.385153 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6117 23:09:03.385732 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6118 23:09:03.388449 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6119 23:09:03.391774
6120 23:09:03.392327
6121 23:09:03.392743 ==
6122 23:09:03.395237 Dram Type= 6, Freq= 0, CH_0, rank 0
6123 23:09:03.398415 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6124 23:09:03.398878 ==
6125 23:09:03.399250
6126 23:09:03.399588
6127 23:09:03.402086 TX Vref Scan disable
6128 23:09:03.402648 == TX Byte 0 ==
6129 23:09:03.404883 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6130 23:09:03.411535 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6131 23:09:03.412103 == TX Byte 1 ==
6132 23:09:03.418250 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6133 23:09:03.421157 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6134 23:09:03.421623 ==
6135 23:09:03.424767 Dram Type= 6, Freq= 0, CH_0, rank 0
6136 23:09:03.427821 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6137 23:09:03.428283 ==
6138 23:09:03.428704
6139 23:09:03.429084
6140 23:09:03.431344 TX Vref Scan disable
6141 23:09:03.431802 == TX Byte 0 ==
6142 23:09:03.437680 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6143 23:09:03.441040 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6144 23:09:03.441500 == TX Byte 1 ==
6145 23:09:03.447867 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6146 23:09:03.450902 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6147 23:09:03.451361
6148 23:09:03.451725 [DATLAT]
6149 23:09:03.454858 Freq=400, CH0 RK0
6150 23:09:03.455419
6151 23:09:03.455787 DATLAT Default: 0xf
6152 23:09:03.457648 0, 0xFFFF, sum = 0
6153 23:09:03.458115 1, 0xFFFF, sum = 0
6154 23:09:03.461055 2, 0xFFFF, sum = 0
6155 23:09:03.461624 3, 0xFFFF, sum = 0
6156 23:09:03.464202 4, 0xFFFF, sum = 0
6157 23:09:03.467573 5, 0xFFFF, sum = 0
6158 23:09:03.468144 6, 0xFFFF, sum = 0
6159 23:09:03.470731 7, 0xFFFF, sum = 0
6160 23:09:03.471196 8, 0xFFFF, sum = 0
6161 23:09:03.473969 9, 0xFFFF, sum = 0
6162 23:09:03.474436 10, 0xFFFF, sum = 0
6163 23:09:03.477458 11, 0xFFFF, sum = 0
6164 23:09:03.477926 12, 0x0, sum = 1
6165 23:09:03.480832 13, 0x0, sum = 2
6166 23:09:03.481401 14, 0x0, sum = 3
6167 23:09:03.484364 15, 0x0, sum = 4
6168 23:09:03.484993 best_step = 13
6169 23:09:03.485366
6170 23:09:03.485707 ==
6171 23:09:03.487573 Dram Type= 6, Freq= 0, CH_0, rank 0
6172 23:09:03.490916 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6173 23:09:03.491495 ==
6174 23:09:03.493805 RX Vref Scan: 1
6175 23:09:03.494265
6176 23:09:03.497790 RX Vref 0 -> 0, step: 1
6177 23:09:03.498344
6178 23:09:03.498715 RX Delay -359 -> 252, step: 8
6179 23:09:03.500601
6180 23:09:03.501161 Set Vref, RX VrefLevel [Byte0]: 47
6181 23:09:03.504319 [Byte1]: 48
6182 23:09:03.509798
6183 23:09:03.510351 Final RX Vref Byte 0 = 47 to rank0
6184 23:09:03.513411 Final RX Vref Byte 1 = 48 to rank0
6185 23:09:03.516062 Final RX Vref Byte 0 = 47 to rank1
6186 23:09:03.519488 Final RX Vref Byte 1 = 48 to rank1==
6187 23:09:03.522905 Dram Type= 6, Freq= 0, CH_0, rank 0
6188 23:09:03.529603 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6189 23:09:03.530155 ==
6190 23:09:03.530525 DQS Delay:
6191 23:09:03.532919 DQS0 = 52, DQS1 = 68
6192 23:09:03.533483 DQM Delay:
6193 23:09:03.533852 DQM0 = 9, DQM1 = 16
6194 23:09:03.536684 DQ Delay:
6195 23:09:03.539259 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =4
6196 23:09:03.539718 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6197 23:09:03.542872 DQ8 =8, DQ9 =0, DQ10 =12, DQ11 =8
6198 23:09:03.545899 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =28
6199 23:09:03.546460
6200 23:09:03.549455
6201 23:09:03.555850 [DQSOSCAuto] RK0, (LSB)MR18= 0x9c9c, (MSB)MR19= 0xc0c, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
6202 23:09:03.559495 CH0 RK0: MR19=C0C, MR18=9C9C
6203 23:09:03.565980 CH0_RK0: MR19=0xC0C, MR18=0x9C9C, DQSOSC=390, MR23=63, INC=388, DEC=258
6204 23:09:03.566547 ==
6205 23:09:03.569570 Dram Type= 6, Freq= 0, CH_0, rank 1
6206 23:09:03.572192 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6207 23:09:03.572684 ==
6208 23:09:03.575536 [Gating] SW mode calibration
6209 23:09:03.582128 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6210 23:09:03.588932 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6211 23:09:03.592352 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6212 23:09:03.595952 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6213 23:09:03.602434 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6214 23:09:03.605328 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6215 23:09:03.609270 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6216 23:09:03.615518 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6217 23:09:03.618794 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6218 23:09:03.622128 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6219 23:09:03.628863 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6220 23:09:03.629443 Total UI for P1: 0, mck2ui 16
6221 23:09:03.632010 best dqsien dly found for B0: ( 0, 10, 16)
6222 23:09:03.635676 Total UI for P1: 0, mck2ui 16
6223 23:09:03.638751 best dqsien dly found for B1: ( 0, 10, 16)
6224 23:09:03.645510 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6225 23:09:03.648965 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6226 23:09:03.649529
6227 23:09:03.651612 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6228 23:09:03.655197 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6229 23:09:03.658816 [Gating] SW calibration Done
6230 23:09:03.659375 ==
6231 23:09:03.661903 Dram Type= 6, Freq= 0, CH_0, rank 1
6232 23:09:03.665281 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6233 23:09:03.665851 ==
6234 23:09:03.668808 RX Vref Scan: 0
6235 23:09:03.669368
6236 23:09:03.669761 RX Vref 0 -> 0, step: 1
6237 23:09:03.670133
6238 23:09:03.671676 RX Delay -410 -> 252, step: 16
6239 23:09:03.678161 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6240 23:09:03.681506 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6241 23:09:03.684818 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6242 23:09:03.688371 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6243 23:09:03.695151 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6244 23:09:03.698140 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6245 23:09:03.701840 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6246 23:09:03.704835 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6247 23:09:03.711689 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6248 23:09:03.715041 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6249 23:09:03.718311 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6250 23:09:03.721559 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6251 23:09:03.728164 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6252 23:09:03.731549 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6253 23:09:03.735014 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6254 23:09:03.738480 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6255 23:09:03.739045 ==
6256 23:09:03.741240 Dram Type= 6, Freq= 0, CH_0, rank 1
6257 23:09:03.748062 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6258 23:09:03.748558 ==
6259 23:09:03.748927 DQS Delay:
6260 23:09:03.751535 DQS0 = 43, DQS1 = 59
6261 23:09:03.751992 DQM Delay:
6262 23:09:03.755178 DQM0 = 7, DQM1 = 15
6263 23:09:03.755743 DQ Delay:
6264 23:09:03.758345 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6265 23:09:03.761515 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6266 23:09:03.761977 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6267 23:09:03.767804 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6268 23:09:03.768350
6269 23:09:03.768828
6270 23:09:03.769353 ==
6271 23:09:03.771110 Dram Type= 6, Freq= 0, CH_0, rank 1
6272 23:09:03.774582 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6273 23:09:03.775047 ==
6274 23:09:03.775408
6275 23:09:03.775742
6276 23:09:03.777706 TX Vref Scan disable
6277 23:09:03.778165 == TX Byte 0 ==
6278 23:09:03.784495 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6279 23:09:03.787860 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6280 23:09:03.788418 == TX Byte 1 ==
6281 23:09:03.791081 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6282 23:09:03.797811 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6283 23:09:03.798373 ==
6284 23:09:03.800637 Dram Type= 6, Freq= 0, CH_0, rank 1
6285 23:09:03.804405 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6286 23:09:03.805020 ==
6287 23:09:03.805393
6288 23:09:03.805735
6289 23:09:03.807380 TX Vref Scan disable
6290 23:09:03.807836 == TX Byte 0 ==
6291 23:09:03.814227 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6292 23:09:03.817566 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6293 23:09:03.818027 == TX Byte 1 ==
6294 23:09:03.823999 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6295 23:09:03.827486 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6296 23:09:03.827943
6297 23:09:03.828305 [DATLAT]
6298 23:09:03.830732 Freq=400, CH0 RK1
6299 23:09:03.831189
6300 23:09:03.831549 DATLAT Default: 0xd
6301 23:09:03.834215 0, 0xFFFF, sum = 0
6302 23:09:03.834681 1, 0xFFFF, sum = 0
6303 23:09:03.837611 2, 0xFFFF, sum = 0
6304 23:09:03.838071 3, 0xFFFF, sum = 0
6305 23:09:03.841003 4, 0xFFFF, sum = 0
6306 23:09:03.841562 5, 0xFFFF, sum = 0
6307 23:09:03.844334 6, 0xFFFF, sum = 0
6308 23:09:03.844944 7, 0xFFFF, sum = 0
6309 23:09:03.847348 8, 0xFFFF, sum = 0
6310 23:09:03.847916 9, 0xFFFF, sum = 0
6311 23:09:03.850533 10, 0xFFFF, sum = 0
6312 23:09:03.850995 11, 0xFFFF, sum = 0
6313 23:09:03.853898 12, 0x0, sum = 1
6314 23:09:03.854474 13, 0x0, sum = 2
6315 23:09:03.857329 14, 0x0, sum = 3
6316 23:09:03.857896 15, 0x0, sum = 4
6317 23:09:03.860903 best_step = 13
6318 23:09:03.861470
6319 23:09:03.861831 ==
6320 23:09:03.863899 Dram Type= 6, Freq= 0, CH_0, rank 1
6321 23:09:03.867086 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6322 23:09:03.867644 ==
6323 23:09:03.870266 RX Vref Scan: 0
6324 23:09:03.870719
6325 23:09:03.871081 RX Vref 0 -> 0, step: 1
6326 23:09:03.871417
6327 23:09:03.873774 RX Delay -359 -> 252, step: 8
6328 23:09:03.881985 iDelay=217, Bit 0, Center -48 (-295 ~ 200) 496
6329 23:09:03.885194 iDelay=217, Bit 1, Center -40 (-295 ~ 216) 512
6330 23:09:03.888916 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504
6331 23:09:03.892187 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6332 23:09:03.898544 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6333 23:09:03.902273 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6334 23:09:03.905297 iDelay=217, Bit 6, Center -32 (-279 ~ 216) 496
6335 23:09:03.908736 iDelay=217, Bit 7, Center -32 (-279 ~ 216) 496
6336 23:09:03.915423 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6337 23:09:03.918187 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6338 23:09:03.921699 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6339 23:09:03.928676 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6340 23:09:03.931815 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6341 23:09:03.935152 iDelay=217, Bit 13, Center -48 (-295 ~ 200) 496
6342 23:09:03.938452 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6343 23:09:03.944827 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6344 23:09:03.945364 ==
6345 23:09:03.948186 Dram Type= 6, Freq= 0, CH_0, rank 1
6346 23:09:03.951565 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6347 23:09:03.952128 ==
6348 23:09:03.952562 DQS Delay:
6349 23:09:03.955322 DQS0 = 52, DQS1 = 60
6350 23:09:03.955873 DQM Delay:
6351 23:09:03.958376 DQM0 = 10, DQM1 = 10
6352 23:09:03.959007 DQ Delay:
6353 23:09:03.961428 DQ0 =4, DQ1 =12, DQ2 =8, DQ3 =4
6354 23:09:03.965040 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6355 23:09:03.967913 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6356 23:09:03.971601 DQ12 =16, DQ13 =12, DQ14 =20, DQ15 =20
6357 23:09:03.972158
6358 23:09:03.972564
6359 23:09:03.977682 [DQSOSCAuto] RK1, (LSB)MR18= 0xc9c9, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 384 ps
6360 23:09:03.981243 CH0 RK1: MR19=C0C, MR18=C9C9
6361 23:09:03.987927 CH0_RK1: MR19=0xC0C, MR18=0xC9C9, DQSOSC=384, MR23=63, INC=400, DEC=267
6362 23:09:03.991170 [RxdqsGatingPostProcess] freq 400
6363 23:09:03.997860 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6364 23:09:04.001461 Pre-setting of DQS Precalculation
6365 23:09:04.004777 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6366 23:09:04.005332 ==
6367 23:09:04.007498 Dram Type= 6, Freq= 0, CH_1, rank 0
6368 23:09:04.011000 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6369 23:09:04.011460 ==
6370 23:09:04.017751 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6371 23:09:04.024196 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6372 23:09:04.027958 [CA 0] Center 36 (8~64) winsize 57
6373 23:09:04.030863 [CA 1] Center 36 (8~64) winsize 57
6374 23:09:04.034326 [CA 2] Center 36 (8~64) winsize 57
6375 23:09:04.037438 [CA 3] Center 36 (8~64) winsize 57
6376 23:09:04.040811 [CA 4] Center 36 (8~64) winsize 57
6377 23:09:04.044384 [CA 5] Center 36 (8~64) winsize 57
6378 23:09:04.044980
6379 23:09:04.047256 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6380 23:09:04.047710
6381 23:09:04.050886 [CATrainingPosCal] consider 1 rank data
6382 23:09:04.054108 u2DelayCellTimex100 = 270/100 ps
6383 23:09:04.057363 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6384 23:09:04.060687 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6385 23:09:04.064329 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6386 23:09:04.067472 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6387 23:09:04.070763 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6388 23:09:04.073767 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6389 23:09:04.074442
6390 23:09:04.077196 CA PerBit enable=1, Macro0, CA PI delay=36
6391 23:09:04.080402
6392 23:09:04.081039 [CBTSetCACLKResult] CA Dly = 36
6393 23:09:04.083865 CS Dly: 1 (0~32)
6394 23:09:04.084418 ==
6395 23:09:04.087102 Dram Type= 6, Freq= 0, CH_1, rank 1
6396 23:09:04.090325 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6397 23:09:04.090790 ==
6398 23:09:04.097038 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6399 23:09:04.103564 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6400 23:09:04.107366 [CA 0] Center 36 (8~64) winsize 57
6401 23:09:04.110066 [CA 1] Center 36 (8~64) winsize 57
6402 23:09:04.113255 [CA 2] Center 36 (8~64) winsize 57
6403 23:09:04.113722 [CA 3] Center 36 (8~64) winsize 57
6404 23:09:04.116829 [CA 4] Center 36 (8~64) winsize 57
6405 23:09:04.120638 [CA 5] Center 36 (8~64) winsize 57
6406 23:09:04.121205
6407 23:09:04.127070 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6408 23:09:04.127643
6409 23:09:04.129838 [CATrainingPosCal] consider 2 rank data
6410 23:09:04.133206 u2DelayCellTimex100 = 270/100 ps
6411 23:09:04.136916 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6412 23:09:04.140114 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6413 23:09:04.143222 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6414 23:09:04.146332 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6415 23:09:04.149995 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6416 23:09:04.153094 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6417 23:09:04.153563
6418 23:09:04.156808 CA PerBit enable=1, Macro0, CA PI delay=36
6419 23:09:04.157386
6420 23:09:04.160005 [CBTSetCACLKResult] CA Dly = 36
6421 23:09:04.163204 CS Dly: 1 (0~32)
6422 23:09:04.163777
6423 23:09:04.166327 ----->DramcWriteLeveling(PI) begin...
6424 23:09:04.166799 ==
6425 23:09:04.170221 Dram Type= 6, Freq= 0, CH_1, rank 0
6426 23:09:04.173190 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6427 23:09:04.173753 ==
6428 23:09:04.176272 Write leveling (Byte 0): 32 => 0
6429 23:09:04.179978 Write leveling (Byte 1): 32 => 0
6430 23:09:04.183292 DramcWriteLeveling(PI) end<-----
6431 23:09:04.183857
6432 23:09:04.184226 ==
6433 23:09:04.186188 Dram Type= 6, Freq= 0, CH_1, rank 0
6434 23:09:04.190185 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6435 23:09:04.190757 ==
6436 23:09:04.193143 [Gating] SW mode calibration
6437 23:09:04.199711 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6438 23:09:04.206054 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6439 23:09:04.209916 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6440 23:09:04.212843 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6441 23:09:04.219355 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6442 23:09:04.223084 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6443 23:09:04.226325 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6444 23:09:04.232989 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6445 23:09:04.236159 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6446 23:09:04.239572 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6447 23:09:04.245947 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6448 23:09:04.246520 Total UI for P1: 0, mck2ui 16
6449 23:09:04.252624 best dqsien dly found for B0: ( 0, 10, 16)
6450 23:09:04.253199 Total UI for P1: 0, mck2ui 16
6451 23:09:04.259461 best dqsien dly found for B1: ( 0, 10, 16)
6452 23:09:04.262789 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6453 23:09:04.266214 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6454 23:09:04.266782
6455 23:09:04.269259 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6456 23:09:04.272645 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6457 23:09:04.275775 [Gating] SW calibration Done
6458 23:09:04.276247 ==
6459 23:09:04.278786 Dram Type= 6, Freq= 0, CH_1, rank 0
6460 23:09:04.282374 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6461 23:09:04.282956 ==
6462 23:09:04.286032 RX Vref Scan: 0
6463 23:09:04.286590
6464 23:09:04.286955 RX Vref 0 -> 0, step: 1
6465 23:09:04.288988
6466 23:09:04.289443 RX Delay -410 -> 252, step: 16
6467 23:09:04.295683 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6468 23:09:04.299033 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6469 23:09:04.301942 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6470 23:09:04.305798 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6471 23:09:04.312130 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6472 23:09:04.315697 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6473 23:09:04.318771 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6474 23:09:04.322004 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6475 23:09:04.328947 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6476 23:09:04.332190 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6477 23:09:04.335559 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6478 23:09:04.338933 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6479 23:09:04.345423 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6480 23:09:04.348870 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6481 23:09:04.352070 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6482 23:09:04.358565 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6483 23:09:04.359153 ==
6484 23:09:04.361885 Dram Type= 6, Freq= 0, CH_1, rank 0
6485 23:09:04.365272 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6486 23:09:04.365844 ==
6487 23:09:04.366222 DQS Delay:
6488 23:09:04.368176 DQS0 = 43, DQS1 = 59
6489 23:09:04.368681 DQM Delay:
6490 23:09:04.371952 DQM0 = 6, DQM1 = 15
6491 23:09:04.372566 DQ Delay:
6492 23:09:04.375271 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6493 23:09:04.378518 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6494 23:09:04.381956 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6495 23:09:04.385097 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =32
6496 23:09:04.385564
6497 23:09:04.385931
6498 23:09:04.386276 ==
6499 23:09:04.388102 Dram Type= 6, Freq= 0, CH_1, rank 0
6500 23:09:04.391949 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6501 23:09:04.392589 ==
6502 23:09:04.392977
6503 23:09:04.393325
6504 23:09:04.394766 TX Vref Scan disable
6505 23:09:04.395235 == TX Byte 0 ==
6506 23:09:04.401682 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6507 23:09:04.405002 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6508 23:09:04.405577 == TX Byte 1 ==
6509 23:09:04.411879 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6510 23:09:04.415194 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6511 23:09:04.415766 ==
6512 23:09:04.418498 Dram Type= 6, Freq= 0, CH_1, rank 0
6513 23:09:04.421374 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6514 23:09:04.421847 ==
6515 23:09:04.424464
6516 23:09:04.424967
6517 23:09:04.425331 TX Vref Scan disable
6518 23:09:04.428288 == TX Byte 0 ==
6519 23:09:04.431697 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6520 23:09:04.434770 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6521 23:09:04.438175 == TX Byte 1 ==
6522 23:09:04.441526 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6523 23:09:04.444464 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6524 23:09:04.444957
6525 23:09:04.447981 [DATLAT]
6526 23:09:04.448651 Freq=400, CH1 RK0
6527 23:09:04.449221
6528 23:09:04.451222 DATLAT Default: 0xf
6529 23:09:04.451679 0, 0xFFFF, sum = 0
6530 23:09:04.454892 1, 0xFFFF, sum = 0
6531 23:09:04.455460 2, 0xFFFF, sum = 0
6532 23:09:04.457740 3, 0xFFFF, sum = 0
6533 23:09:04.458208 4, 0xFFFF, sum = 0
6534 23:09:04.461169 5, 0xFFFF, sum = 0
6535 23:09:04.461637 6, 0xFFFF, sum = 0
6536 23:09:04.464737 7, 0xFFFF, sum = 0
6537 23:09:04.465298 8, 0xFFFF, sum = 0
6538 23:09:04.467870 9, 0xFFFF, sum = 0
6539 23:09:04.468436 10, 0xFFFF, sum = 0
6540 23:09:04.471259 11, 0xFFFF, sum = 0
6541 23:09:04.471830 12, 0x0, sum = 1
6542 23:09:04.474350 13, 0x0, sum = 2
6543 23:09:04.474918 14, 0x0, sum = 3
6544 23:09:04.477757 15, 0x0, sum = 4
6545 23:09:04.478338 best_step = 13
6546 23:09:04.478711
6547 23:09:04.479053 ==
6548 23:09:04.481002 Dram Type= 6, Freq= 0, CH_1, rank 0
6549 23:09:04.488011 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6550 23:09:04.488627 ==
6551 23:09:04.489013 RX Vref Scan: 1
6552 23:09:04.489357
6553 23:09:04.490701 RX Vref 0 -> 0, step: 1
6554 23:09:04.491155
6555 23:09:04.494419 RX Delay -359 -> 252, step: 8
6556 23:09:04.494974
6557 23:09:04.497583 Set Vref, RX VrefLevel [Byte0]: 55
6558 23:09:04.500751 [Byte1]: 48
6559 23:09:04.504501
6560 23:09:04.505091 Final RX Vref Byte 0 = 55 to rank0
6561 23:09:04.507409 Final RX Vref Byte 1 = 48 to rank0
6562 23:09:04.510716 Final RX Vref Byte 0 = 55 to rank1
6563 23:09:04.514217 Final RX Vref Byte 1 = 48 to rank1==
6564 23:09:04.517465 Dram Type= 6, Freq= 0, CH_1, rank 0
6565 23:09:04.521034 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6566 23:09:04.523991 ==
6567 23:09:04.524449 DQS Delay:
6568 23:09:04.524871 DQS0 = 48, DQS1 = 64
6569 23:09:04.527621 DQM Delay:
6570 23:09:04.528178 DQM0 = 8, DQM1 = 16
6571 23:09:04.530767 DQ Delay:
6572 23:09:04.531225 DQ0 =12, DQ1 =0, DQ2 =0, DQ3 =8
6573 23:09:04.533855 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =4
6574 23:09:04.537515 DQ8 =0, DQ9 =8, DQ10 =20, DQ11 =8
6575 23:09:04.540501 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6576 23:09:04.540991
6577 23:09:04.541353
6578 23:09:04.550863 [DQSOSCAuto] RK0, (LSB)MR18= 0xcdcd, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 384 ps
6579 23:09:04.553653 CH1 RK0: MR19=C0C, MR18=CDCD
6580 23:09:04.560957 CH1_RK0: MR19=0xC0C, MR18=0xCDCD, DQSOSC=384, MR23=63, INC=400, DEC=267
6581 23:09:04.561516 ==
6582 23:09:04.563975 Dram Type= 6, Freq= 0, CH_1, rank 1
6583 23:09:04.566996 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6584 23:09:04.567458 ==
6585 23:09:04.570569 [Gating] SW mode calibration
6586 23:09:04.577195 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6587 23:09:04.580355 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6588 23:09:04.587574 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6589 23:09:04.590980 0 7 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
6590 23:09:04.593991 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6591 23:09:04.600583 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6592 23:09:04.603762 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6593 23:09:04.607252 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6594 23:09:04.613942 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6595 23:09:04.617435 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6596 23:09:04.620377 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6597 23:09:04.623442 Total UI for P1: 0, mck2ui 16
6598 23:09:04.627056 best dqsien dly found for B0: ( 0, 10, 16)
6599 23:09:04.630570 Total UI for P1: 0, mck2ui 16
6600 23:09:04.633430 best dqsien dly found for B1: ( 0, 10, 16)
6601 23:09:04.637097 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6602 23:09:04.640292 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6603 23:09:04.640906
6604 23:09:04.647064 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6605 23:09:04.650019 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6606 23:09:04.653268 [Gating] SW calibration Done
6607 23:09:04.653825 ==
6608 23:09:04.656682 Dram Type= 6, Freq= 0, CH_1, rank 1
6609 23:09:04.659979 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6610 23:09:04.660588 ==
6611 23:09:04.660971 RX Vref Scan: 0
6612 23:09:04.663199
6613 23:09:04.663751 RX Vref 0 -> 0, step: 1
6614 23:09:04.664119
6615 23:09:04.666500 RX Delay -410 -> 252, step: 16
6616 23:09:04.669789 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6617 23:09:04.676957 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6618 23:09:04.679740 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6619 23:09:04.683080 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6620 23:09:04.686554 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6621 23:09:04.693202 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6622 23:09:04.696661 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6623 23:09:04.699985 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6624 23:09:04.703127 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6625 23:09:04.709717 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6626 23:09:04.713231 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6627 23:09:04.716449 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6628 23:09:04.719770 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6629 23:09:04.725937 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6630 23:09:04.729918 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6631 23:09:04.733044 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6632 23:09:04.733606 ==
6633 23:09:04.736190 Dram Type= 6, Freq= 0, CH_1, rank 1
6634 23:09:04.742960 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6635 23:09:04.743524 ==
6636 23:09:04.743895 DQS Delay:
6637 23:09:04.746045 DQS0 = 43, DQS1 = 59
6638 23:09:04.746611 DQM Delay:
6639 23:09:04.746981 DQM0 = 9, DQM1 = 17
6640 23:09:04.749949 DQ Delay:
6641 23:09:04.752472 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6642 23:09:04.752974 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6643 23:09:04.756048 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6644 23:09:04.759236 DQ12 =32, DQ13 =32, DQ14 =24, DQ15 =24
6645 23:09:04.759800
6646 23:09:04.762842
6647 23:09:04.763398 ==
6648 23:09:04.765680 Dram Type= 6, Freq= 0, CH_1, rank 1
6649 23:09:04.769257 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6650 23:09:04.769819 ==
6651 23:09:04.770194
6652 23:09:04.770535
6653 23:09:04.772464 TX Vref Scan disable
6654 23:09:04.773075 == TX Byte 0 ==
6655 23:09:04.775605 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6656 23:09:04.782590 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6657 23:09:04.783220 == TX Byte 1 ==
6658 23:09:04.785686 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6659 23:09:04.792210 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6660 23:09:04.792714 ==
6661 23:09:04.795484 Dram Type= 6, Freq= 0, CH_1, rank 1
6662 23:09:04.799021 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6663 23:09:04.799493 ==
6664 23:09:04.799864
6665 23:09:04.800205
6666 23:09:04.802051 TX Vref Scan disable
6667 23:09:04.802532 == TX Byte 0 ==
6668 23:09:04.805790 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6669 23:09:04.812328 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6670 23:09:04.812931 == TX Byte 1 ==
6671 23:09:04.815809 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6672 23:09:04.822273 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6673 23:09:04.822820
6674 23:09:04.823189 [DATLAT]
6675 23:09:04.823666 Freq=400, CH1 RK1
6676 23:09:04.825490
6677 23:09:04.825954 DATLAT Default: 0xd
6678 23:09:04.829100 0, 0xFFFF, sum = 0
6679 23:09:04.829670 1, 0xFFFF, sum = 0
6680 23:09:04.831965 2, 0xFFFF, sum = 0
6681 23:09:04.832440 3, 0xFFFF, sum = 0
6682 23:09:04.835578 4, 0xFFFF, sum = 0
6683 23:09:04.836145 5, 0xFFFF, sum = 0
6684 23:09:04.839040 6, 0xFFFF, sum = 0
6685 23:09:04.839608 7, 0xFFFF, sum = 0
6686 23:09:04.842195 8, 0xFFFF, sum = 0
6687 23:09:04.842716 9, 0xFFFF, sum = 0
6688 23:09:04.845486 10, 0xFFFF, sum = 0
6689 23:09:04.846057 11, 0xFFFF, sum = 0
6690 23:09:04.848714 12, 0x0, sum = 1
6691 23:09:04.849280 13, 0x0, sum = 2
6692 23:09:04.851830 14, 0x0, sum = 3
6693 23:09:04.852603 15, 0x0, sum = 4
6694 23:09:04.855860 best_step = 13
6695 23:09:04.856421
6696 23:09:04.856855 ==
6697 23:09:04.858682 Dram Type= 6, Freq= 0, CH_1, rank 1
6698 23:09:04.862437 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6699 23:09:04.863001 ==
6700 23:09:04.863375 RX Vref Scan: 0
6701 23:09:04.865813
6702 23:09:04.866368 RX Vref 0 -> 0, step: 1
6703 23:09:04.866743
6704 23:09:04.868745 RX Delay -359 -> 252, step: 8
6705 23:09:04.876243 iDelay=225, Bit 0, Center -36 (-279 ~ 208) 488
6706 23:09:04.879531 iDelay=225, Bit 1, Center -44 (-287 ~ 200) 488
6707 23:09:04.882805 iDelay=225, Bit 2, Center -48 (-295 ~ 200) 496
6708 23:09:04.885977 iDelay=225, Bit 3, Center -44 (-287 ~ 200) 488
6709 23:09:04.892960 iDelay=225, Bit 4, Center -40 (-287 ~ 208) 496
6710 23:09:04.896265 iDelay=225, Bit 5, Center -24 (-271 ~ 224) 496
6711 23:09:04.899516 iDelay=225, Bit 6, Center -32 (-279 ~ 216) 496
6712 23:09:04.902878 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
6713 23:09:04.909298 iDelay=225, Bit 8, Center -64 (-311 ~ 184) 496
6714 23:09:04.912786 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
6715 23:09:04.916107 iDelay=225, Bit 10, Center -48 (-295 ~ 200) 496
6716 23:09:04.919554 iDelay=225, Bit 11, Center -56 (-303 ~ 192) 496
6717 23:09:04.925938 iDelay=225, Bit 12, Center -40 (-287 ~ 208) 496
6718 23:09:04.929491 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
6719 23:09:04.932448 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
6720 23:09:04.939697 iDelay=225, Bit 15, Center -40 (-287 ~ 208) 496
6721 23:09:04.940263 ==
6722 23:09:04.942597 Dram Type= 6, Freq= 0, CH_1, rank 1
6723 23:09:04.945971 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6724 23:09:04.946437 ==
6725 23:09:04.946816 DQS Delay:
6726 23:09:04.949434 DQS0 = 48, DQS1 = 64
6727 23:09:04.949995 DQM Delay:
6728 23:09:04.952729 DQM0 = 9, DQM1 = 16
6729 23:09:04.953290 DQ Delay:
6730 23:09:04.956105 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6731 23:09:04.959283 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6732 23:09:04.962821 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6733 23:09:04.965965 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6734 23:09:04.966522
6735 23:09:04.966897
6736 23:09:04.972743 [DQSOSCAuto] RK1, (LSB)MR18= 0xb2b2, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps
6737 23:09:04.976182 CH1 RK1: MR19=C0C, MR18=B2B2
6738 23:09:04.982103 CH1_RK1: MR19=0xC0C, MR18=0xB2B2, DQSOSC=387, MR23=63, INC=394, DEC=262
6739 23:09:04.985852 [RxdqsGatingPostProcess] freq 400
6740 23:09:04.992426 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6741 23:09:04.993051 Pre-setting of DQS Precalculation
6742 23:09:04.999031 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6743 23:09:05.005525 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6744 23:09:05.012496 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6745 23:09:05.013107
6746 23:09:05.013474
6747 23:09:05.015702 [Calibration Summary] 800 Mbps
6748 23:09:05.018917 CH 0, Rank 0
6749 23:09:05.019479 SW Impedance : PASS
6750 23:09:05.022177 DUTY Scan : NO K
6751 23:09:05.025132 ZQ Calibration : PASS
6752 23:09:05.025609 Jitter Meter : NO K
6753 23:09:05.028454 CBT Training : PASS
6754 23:09:05.032060 Write leveling : PASS
6755 23:09:05.032659 RX DQS gating : PASS
6756 23:09:05.035117 RX DQ/DQS(RDDQC) : PASS
6757 23:09:05.035575 TX DQ/DQS : PASS
6758 23:09:05.038389 RX DATLAT : PASS
6759 23:09:05.042097 RX DQ/DQS(Engine): PASS
6760 23:09:05.042659 TX OE : NO K
6761 23:09:05.045264 All Pass.
6762 23:09:05.045832
6763 23:09:05.046205 CH 0, Rank 1
6764 23:09:05.048480 SW Impedance : PASS
6765 23:09:05.049210 DUTY Scan : NO K
6766 23:09:05.051997 ZQ Calibration : PASS
6767 23:09:05.054978 Jitter Meter : NO K
6768 23:09:05.055451 CBT Training : PASS
6769 23:09:05.058684 Write leveling : NO K
6770 23:09:05.061578 RX DQS gating : PASS
6771 23:09:05.062141 RX DQ/DQS(RDDQC) : PASS
6772 23:09:05.065156 TX DQ/DQS : PASS
6773 23:09:05.068186 RX DATLAT : PASS
6774 23:09:05.068808 RX DQ/DQS(Engine): PASS
6775 23:09:05.071788 TX OE : NO K
6776 23:09:05.072347 All Pass.
6777 23:09:05.072758
6778 23:09:05.075329 CH 1, Rank 0
6779 23:09:05.075887 SW Impedance : PASS
6780 23:09:05.078267 DUTY Scan : NO K
6781 23:09:05.081533 ZQ Calibration : PASS
6782 23:09:05.082233 Jitter Meter : NO K
6783 23:09:05.084994 CBT Training : PASS
6784 23:09:05.088317 Write leveling : PASS
6785 23:09:05.088934 RX DQS gating : PASS
6786 23:09:05.091765 RX DQ/DQS(RDDQC) : PASS
6787 23:09:05.092321 TX DQ/DQS : PASS
6788 23:09:05.095088 RX DATLAT : PASS
6789 23:09:05.098258 RX DQ/DQS(Engine): PASS
6790 23:09:05.098819 TX OE : NO K
6791 23:09:05.101700 All Pass.
6792 23:09:05.102259
6793 23:09:05.102627 CH 1, Rank 1
6794 23:09:05.104605 SW Impedance : PASS
6795 23:09:05.105069 DUTY Scan : NO K
6796 23:09:05.108366 ZQ Calibration : PASS
6797 23:09:05.111390 Jitter Meter : NO K
6798 23:09:05.111950 CBT Training : PASS
6799 23:09:05.114876 Write leveling : NO K
6800 23:09:05.118194 RX DQS gating : PASS
6801 23:09:05.118811 RX DQ/DQS(RDDQC) : PASS
6802 23:09:05.121295 TX DQ/DQS : PASS
6803 23:09:05.124463 RX DATLAT : PASS
6804 23:09:05.124975 RX DQ/DQS(Engine): PASS
6805 23:09:05.128192 TX OE : NO K
6806 23:09:05.128944 All Pass.
6807 23:09:05.129383
6808 23:09:05.131101 DramC Write-DBI off
6809 23:09:05.134145 PER_BANK_REFRESH: Hybrid Mode
6810 23:09:05.134602 TX_TRACKING: ON
6811 23:09:05.144670 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6812 23:09:05.147887 [FAST_K] Save calibration result to emmc
6813 23:09:05.150989 dramc_set_vcore_voltage set vcore to 725000
6814 23:09:05.154216 Read voltage for 1600, 0
6815 23:09:05.154678 Vio18 = 0
6816 23:09:05.155041 Vcore = 725000
6817 23:09:05.157661 Vdram = 0
6818 23:09:05.158224 Vddq = 0
6819 23:09:05.158666 Vmddr = 0
6820 23:09:05.164308 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6821 23:09:05.167376 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6822 23:09:05.170748 MEM_TYPE=3, freq_sel=13
6823 23:09:05.174249 sv_algorithm_assistance_LP4_3733
6824 23:09:05.177692 ============ PULL DRAM RESETB DOWN ============
6825 23:09:05.184181 ========== PULL DRAM RESETB DOWN end =========
6826 23:09:05.187695 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6827 23:09:05.190959 ===================================
6828 23:09:05.194239 LPDDR4 DRAM CONFIGURATION
6829 23:09:05.197138 ===================================
6830 23:09:05.197603 EX_ROW_EN[0] = 0x0
6831 23:09:05.200746 EX_ROW_EN[1] = 0x0
6832 23:09:05.201306 LP4Y_EN = 0x0
6833 23:09:05.204085 WORK_FSP = 0x1
6834 23:09:05.204679 WL = 0x5
6835 23:09:05.207401 RL = 0x5
6836 23:09:05.207961 BL = 0x2
6837 23:09:05.211001 RPST = 0x0
6838 23:09:05.211563 RD_PRE = 0x0
6839 23:09:05.213927 WR_PRE = 0x1
6840 23:09:05.214485 WR_PST = 0x1
6841 23:09:05.217483 DBI_WR = 0x0
6842 23:09:05.220536 DBI_RD = 0x0
6843 23:09:05.221116 OTF = 0x1
6844 23:09:05.223681 ===================================
6845 23:09:05.226966 ===================================
6846 23:09:05.227428 ANA top config
6847 23:09:05.230554 ===================================
6848 23:09:05.234026 DLL_ASYNC_EN = 0
6849 23:09:05.237266 ALL_SLAVE_EN = 0
6850 23:09:05.240856 NEW_RANK_MODE = 1
6851 23:09:05.243867 DLL_IDLE_MODE = 1
6852 23:09:05.244430 LP45_APHY_COMB_EN = 1
6853 23:09:05.246746 TX_ODT_DIS = 0
6854 23:09:05.250064 NEW_8X_MODE = 1
6855 23:09:05.253513 ===================================
6856 23:09:05.256922 ===================================
6857 23:09:05.260423 data_rate = 3200
6858 23:09:05.263755 CKR = 1
6859 23:09:05.264317 DQ_P2S_RATIO = 8
6860 23:09:05.266887 ===================================
6861 23:09:05.270121 CA_P2S_RATIO = 8
6862 23:09:05.273760 DQ_CA_OPEN = 0
6863 23:09:05.276890 DQ_SEMI_OPEN = 0
6864 23:09:05.280094 CA_SEMI_OPEN = 0
6865 23:09:05.283450 CA_FULL_RATE = 0
6866 23:09:05.283955 DQ_CKDIV4_EN = 0
6867 23:09:05.286649 CA_CKDIV4_EN = 0
6868 23:09:05.289692 CA_PREDIV_EN = 0
6869 23:09:05.293256 PH8_DLY = 12
6870 23:09:05.296844 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6871 23:09:05.300191 DQ_AAMCK_DIV = 4
6872 23:09:05.300791 CA_AAMCK_DIV = 4
6873 23:09:05.303320 CA_ADMCK_DIV = 4
6874 23:09:05.306803 DQ_TRACK_CA_EN = 0
6875 23:09:05.309899 CA_PICK = 1600
6876 23:09:05.313001 CA_MCKIO = 1600
6877 23:09:05.316718 MCKIO_SEMI = 0
6878 23:09:05.320072 PLL_FREQ = 3068
6879 23:09:05.322944 DQ_UI_PI_RATIO = 32
6880 23:09:05.323403 CA_UI_PI_RATIO = 0
6881 23:09:05.326189 ===================================
6882 23:09:05.330025 ===================================
6883 23:09:05.333063 memory_type:LPDDR4
6884 23:09:05.336452 GP_NUM : 10
6885 23:09:05.337045 SRAM_EN : 1
6886 23:09:05.339730 MD32_EN : 0
6887 23:09:05.342935 ===================================
6888 23:09:05.346491 [ANA_INIT] >>>>>>>>>>>>>>
6889 23:09:05.349526 <<<<<< [CONFIGURE PHASE]: ANA_TX
6890 23:09:05.353284 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6891 23:09:05.356427 ===================================
6892 23:09:05.357043 data_rate = 3200,PCW = 0X7600
6893 23:09:05.359466 ===================================
6894 23:09:05.362880 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6895 23:09:05.369207 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6896 23:09:05.376145 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6897 23:09:05.379734 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6898 23:09:05.382699 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6899 23:09:05.385867 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6900 23:09:05.389026 [ANA_INIT] flow start
6901 23:09:05.392878 [ANA_INIT] PLL >>>>>>>>
6902 23:09:05.393439 [ANA_INIT] PLL <<<<<<<<
6903 23:09:05.396065 [ANA_INIT] MIDPI >>>>>>>>
6904 23:09:05.399111 [ANA_INIT] MIDPI <<<<<<<<
6905 23:09:05.399714 [ANA_INIT] DLL >>>>>>>>
6906 23:09:05.402597 [ANA_INIT] DLL <<<<<<<<
6907 23:09:05.405948 [ANA_INIT] flow end
6908 23:09:05.409063 ============ LP4 DIFF to SE enter ============
6909 23:09:05.412890 ============ LP4 DIFF to SE exit ============
6910 23:09:05.415913 [ANA_INIT] <<<<<<<<<<<<<
6911 23:09:05.419296 [Flow] Enable top DCM control >>>>>
6912 23:09:05.422138 [Flow] Enable top DCM control <<<<<
6913 23:09:05.425677 Enable DLL master slave shuffle
6914 23:09:05.429183 ==============================================================
6915 23:09:05.432602 Gating Mode config
6916 23:09:05.439207 ==============================================================
6917 23:09:05.439770 Config description:
6918 23:09:05.448889 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6919 23:09:05.455455 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6920 23:09:05.458941 SELPH_MODE 0: By rank 1: By Phase
6921 23:09:05.465515 ==============================================================
6922 23:09:05.468771 GAT_TRACK_EN = 1
6923 23:09:05.472034 RX_GATING_MODE = 2
6924 23:09:05.475479 RX_GATING_TRACK_MODE = 2
6925 23:09:05.478601 SELPH_MODE = 1
6926 23:09:05.481776 PICG_EARLY_EN = 1
6927 23:09:05.484971 VALID_LAT_VALUE = 1
6928 23:09:05.488866 ==============================================================
6929 23:09:05.491934 Enter into Gating configuration >>>>
6930 23:09:05.495372 Exit from Gating configuration <<<<
6931 23:09:05.498718 Enter into DVFS_PRE_config >>>>>
6932 23:09:05.511965 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6933 23:09:05.512601 Exit from DVFS_PRE_config <<<<<
6934 23:09:05.515226 Enter into PICG configuration >>>>
6935 23:09:05.518394 Exit from PICG configuration <<<<
6936 23:09:05.521695 [RX_INPUT] configuration >>>>>
6937 23:09:05.525333 [RX_INPUT] configuration <<<<<
6938 23:09:05.531894 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6939 23:09:05.535195 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6940 23:09:05.541493 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6941 23:09:05.548296 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6942 23:09:05.554994 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6943 23:09:05.561921 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6944 23:09:05.564916 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6945 23:09:05.568169 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6946 23:09:05.571294 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6947 23:09:05.577885 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6948 23:09:05.581113 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6949 23:09:05.584664 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6950 23:09:05.587969 ===================================
6951 23:09:05.591151 LPDDR4 DRAM CONFIGURATION
6952 23:09:05.594387 ===================================
6953 23:09:05.597596 EX_ROW_EN[0] = 0x0
6954 23:09:05.598062 EX_ROW_EN[1] = 0x0
6955 23:09:05.601096 LP4Y_EN = 0x0
6956 23:09:05.601556 WORK_FSP = 0x1
6957 23:09:05.604088 WL = 0x5
6958 23:09:05.604674 RL = 0x5
6959 23:09:05.607880 BL = 0x2
6960 23:09:05.608446 RPST = 0x0
6961 23:09:05.610779 RD_PRE = 0x0
6962 23:09:05.611240 WR_PRE = 0x1
6963 23:09:05.614037 WR_PST = 0x1
6964 23:09:05.614502 DBI_WR = 0x0
6965 23:09:05.617699 DBI_RD = 0x0
6966 23:09:05.618272 OTF = 0x1
6967 23:09:05.620905 ===================================
6968 23:09:05.627738 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6969 23:09:05.631080 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6970 23:09:05.633881 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6971 23:09:05.637222 ===================================
6972 23:09:05.640760 LPDDR4 DRAM CONFIGURATION
6973 23:09:05.644160 ===================================
6974 23:09:05.647146 EX_ROW_EN[0] = 0x10
6975 23:09:05.647629 EX_ROW_EN[1] = 0x0
6976 23:09:05.650736 LP4Y_EN = 0x0
6977 23:09:05.651301 WORK_FSP = 0x1
6978 23:09:05.654396 WL = 0x5
6979 23:09:05.654962 RL = 0x5
6980 23:09:05.657029 BL = 0x2
6981 23:09:05.657493 RPST = 0x0
6982 23:09:05.660739 RD_PRE = 0x0
6983 23:09:05.661386 WR_PRE = 0x1
6984 23:09:05.664026 WR_PST = 0x1
6985 23:09:05.664635 DBI_WR = 0x0
6986 23:09:05.667160 DBI_RD = 0x0
6987 23:09:05.667723 OTF = 0x1
6988 23:09:05.670458 ===================================
6989 23:09:05.677224 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6990 23:09:05.677795 ==
6991 23:09:05.680563 Dram Type= 6, Freq= 0, CH_0, rank 0
6992 23:09:05.687113 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
6993 23:09:05.687585 ==
6994 23:09:05.687955 [Duty_Offset_Calibration]
6995 23:09:05.690094 B0:0 B1:2 CA:1
6996 23:09:05.690553
6997 23:09:05.693259 [DutyScan_Calibration_Flow] k_type=0
6998 23:09:05.703374
6999 23:09:05.703948 ==CLK 0==
7000 23:09:05.706283 Final CLK duty delay cell = 0
7001 23:09:05.709480 [0] MAX Duty = 5187%(X100), DQS PI = 24
7002 23:09:05.712907 [0] MIN Duty = 4938%(X100), DQS PI = 38
7003 23:09:05.716141 [0] AVG Duty = 5062%(X100)
7004 23:09:05.716656
7005 23:09:05.719874 CH0 CLK Duty spec in!! Max-Min= 249%
7006 23:09:05.723125 [DutyScan_Calibration_Flow] ====Done====
7007 23:09:05.723628
7008 23:09:05.725920 [DutyScan_Calibration_Flow] k_type=1
7009 23:09:05.743432
7010 23:09:05.743998 ==DQS 0 ==
7011 23:09:05.746710 Final DQS duty delay cell = 0
7012 23:09:05.749662 [0] MAX Duty = 5156%(X100), DQS PI = 34
7013 23:09:05.752885 [0] MIN Duty = 5031%(X100), DQS PI = 8
7014 23:09:05.753351 [0] AVG Duty = 5093%(X100)
7015 23:09:05.756387
7016 23:09:05.757012 ==DQS 1 ==
7017 23:09:05.759736 Final DQS duty delay cell = 0
7018 23:09:05.762601 [0] MAX Duty = 5031%(X100), DQS PI = 0
7019 23:09:05.766484 [0] MIN Duty = 4876%(X100), DQS PI = 16
7020 23:09:05.769723 [0] AVG Duty = 4953%(X100)
7021 23:09:05.770295
7022 23:09:05.772903 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7023 23:09:05.773367
7024 23:09:05.775962 CH0 DQS 1 Duty spec in!! Max-Min= 155%
7025 23:09:05.779529 [DutyScan_Calibration_Flow] ====Done====
7026 23:09:05.780095
7027 23:09:05.783192 [DutyScan_Calibration_Flow] k_type=3
7028 23:09:05.800104
7029 23:09:05.800727 ==DQM 0 ==
7030 23:09:05.803562 Final DQM duty delay cell = 0
7031 23:09:05.806808 [0] MAX Duty = 5187%(X100), DQS PI = 24
7032 23:09:05.810085 [0] MIN Duty = 4907%(X100), DQS PI = 42
7033 23:09:05.813185 [0] AVG Duty = 5047%(X100)
7034 23:09:05.813664
7035 23:09:05.814031 ==DQM 1 ==
7036 23:09:05.816760 Final DQM duty delay cell = 0
7037 23:09:05.819817 [0] MAX Duty = 5031%(X100), DQS PI = 4
7038 23:09:05.823158 [0] MIN Duty = 4782%(X100), DQS PI = 14
7039 23:09:05.826330 [0] AVG Duty = 4906%(X100)
7040 23:09:05.826943
7041 23:09:05.830118 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7042 23:09:05.830676
7043 23:09:05.833260 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7044 23:09:05.836551 [DutyScan_Calibration_Flow] ====Done====
7045 23:09:05.837130
7046 23:09:05.839703 [DutyScan_Calibration_Flow] k_type=2
7047 23:09:05.856730
7048 23:09:05.857283 ==DQ 0 ==
7049 23:09:05.859735 Final DQ duty delay cell = 0
7050 23:09:05.862907 [0] MAX Duty = 5218%(X100), DQS PI = 18
7051 23:09:05.866098 [0] MIN Duty = 4938%(X100), DQS PI = 56
7052 23:09:05.866561 [0] AVG Duty = 5078%(X100)
7053 23:09:05.869378
7054 23:09:05.869847 ==DQ 1 ==
7055 23:09:05.873154 Final DQ duty delay cell = -4
7056 23:09:05.876549 [-4] MAX Duty = 5094%(X100), DQS PI = 4
7057 23:09:05.879628 [-4] MIN Duty = 4813%(X100), DQS PI = 36
7058 23:09:05.883033 [-4] AVG Duty = 4953%(X100)
7059 23:09:05.883511
7060 23:09:05.886008 CH0 DQ 0 Duty spec in!! Max-Min= 280%
7061 23:09:05.886493
7062 23:09:05.889230 CH0 DQ 1 Duty spec in!! Max-Min= 281%
7063 23:09:05.892841 [DutyScan_Calibration_Flow] ====Done====
7064 23:09:05.893308 ==
7065 23:09:05.896113 Dram Type= 6, Freq= 0, CH_1, rank 0
7066 23:09:05.899393 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7067 23:09:05.899958 ==
7068 23:09:05.902831 [Duty_Offset_Calibration]
7069 23:09:05.903390 B0:0 B1:4 CA:-5
7070 23:09:05.903767
7071 23:09:05.905494 [DutyScan_Calibration_Flow] k_type=0
7072 23:09:05.917066
7073 23:09:05.917625 ==CLK 0==
7074 23:09:05.920168 Final CLK duty delay cell = 0
7075 23:09:05.923408 [0] MAX Duty = 5156%(X100), DQS PI = 22
7076 23:09:05.926556 [0] MIN Duty = 4906%(X100), DQS PI = 50
7077 23:09:05.930286 [0] AVG Duty = 5031%(X100)
7078 23:09:05.930869
7079 23:09:05.933357 CH1 CLK Duty spec in!! Max-Min= 250%
7080 23:09:05.936714 [DutyScan_Calibration_Flow] ====Done====
7081 23:09:05.937242
7082 23:09:05.940236 [DutyScan_Calibration_Flow] k_type=1
7083 23:09:05.956309
7084 23:09:05.956988 ==DQS 0 ==
7085 23:09:05.959490 Final DQS duty delay cell = 0
7086 23:09:05.962422 [0] MAX Duty = 5187%(X100), DQS PI = 20
7087 23:09:05.966038 [0] MIN Duty = 4876%(X100), DQS PI = 42
7088 23:09:05.969064 [0] AVG Duty = 5031%(X100)
7089 23:09:05.969529
7090 23:09:05.969927 ==DQS 1 ==
7091 23:09:05.972902 Final DQS duty delay cell = -4
7092 23:09:05.976206 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7093 23:09:05.979155 [-4] MIN Duty = 4844%(X100), DQS PI = 56
7094 23:09:05.982564 [-4] AVG Duty = 4922%(X100)
7095 23:09:05.983199
7096 23:09:05.985672 CH1 DQS 0 Duty spec in!! Max-Min= 311%
7097 23:09:05.986176
7098 23:09:05.989324 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7099 23:09:05.992421 [DutyScan_Calibration_Flow] ====Done====
7100 23:09:05.993108
7101 23:09:05.995670 [DutyScan_Calibration_Flow] k_type=3
7102 23:09:06.011921
7103 23:09:06.012495 ==DQM 0 ==
7104 23:09:06.014960 Final DQM duty delay cell = -4
7105 23:09:06.018831 [-4] MAX Duty = 5062%(X100), DQS PI = 32
7106 23:09:06.021813 [-4] MIN Duty = 4813%(X100), DQS PI = 42
7107 23:09:06.024838 [-4] AVG Duty = 4937%(X100)
7108 23:09:06.025326
7109 23:09:06.025820 ==DQM 1 ==
7110 23:09:06.028024 Final DQM duty delay cell = -4
7111 23:09:06.031655 [-4] MAX Duty = 5093%(X100), DQS PI = 16
7112 23:09:06.034746 [-4] MIN Duty = 4907%(X100), DQS PI = 36
7113 23:09:06.037962 [-4] AVG Duty = 5000%(X100)
7114 23:09:06.038429
7115 23:09:06.041393 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7116 23:09:06.041958
7117 23:09:06.044902 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7118 23:09:06.048129 [DutyScan_Calibration_Flow] ====Done====
7119 23:09:06.048752
7120 23:09:06.050999 [DutyScan_Calibration_Flow] k_type=2
7121 23:09:06.069620
7122 23:09:06.070175 ==DQ 0 ==
7123 23:09:06.073920 Final DQ duty delay cell = 0
7124 23:09:06.075686 [0] MAX Duty = 5093%(X100), DQS PI = 20
7125 23:09:06.079473 [0] MIN Duty = 4969%(X100), DQS PI = 46
7126 23:09:06.080031 [0] AVG Duty = 5031%(X100)
7127 23:09:06.082832
7128 23:09:06.083397 ==DQ 1 ==
7129 23:09:06.085647 Final DQ duty delay cell = 0
7130 23:09:06.089039 [0] MAX Duty = 5031%(X100), DQS PI = 4
7131 23:09:06.092723 [0] MIN Duty = 4876%(X100), DQS PI = 28
7132 23:09:06.093292 [0] AVG Duty = 4953%(X100)
7133 23:09:06.095710
7134 23:09:06.099251 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7135 23:09:06.099821
7136 23:09:06.102497 CH1 DQ 1 Duty spec in!! Max-Min= 155%
7137 23:09:06.105251 [DutyScan_Calibration_Flow] ====Done====
7138 23:09:06.108690 nWR fixed to 30
7139 23:09:06.109253 [ModeRegInit_LP4] CH0 RK0
7140 23:09:06.112123 [ModeRegInit_LP4] CH0 RK1
7141 23:09:06.115933 [ModeRegInit_LP4] CH1 RK0
7142 23:09:06.118784 [ModeRegInit_LP4] CH1 RK1
7143 23:09:06.119341 match AC timing 4
7144 23:09:06.125381 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7145 23:09:06.128894 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7146 23:09:06.132005 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7147 23:09:06.138459 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7148 23:09:06.141923 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7149 23:09:06.142486 [MiockJmeterHQA]
7150 23:09:06.142862
7151 23:09:06.145337 [DramcMiockJmeter] u1RxGatingPI = 0
7152 23:09:06.148688 0 : 4366, 4137
7153 23:09:06.149256 4 : 4363, 4137
7154 23:09:06.151890 8 : 4253, 4026
7155 23:09:06.152366 12 : 4363, 4137
7156 23:09:06.152781 16 : 4252, 4027
7157 23:09:06.155316 20 : 4252, 4027
7158 23:09:06.155883 24 : 4252, 4027
7159 23:09:06.158513 28 : 4363, 4137
7160 23:09:06.159095 32 : 4365, 4140
7161 23:09:06.161724 36 : 4252, 4027
7162 23:09:06.162310 40 : 4253, 4026
7163 23:09:06.164820 44 : 4252, 4027
7164 23:09:06.165295 48 : 4252, 4027
7165 23:09:06.165676 52 : 4253, 4026
7166 23:09:06.168426 56 : 4363, 4138
7167 23:09:06.169024 60 : 4252, 4030
7168 23:09:06.171566 64 : 4250, 4027
7169 23:09:06.172133 68 : 4250, 4027
7170 23:09:06.175190 72 : 4250, 4026
7171 23:09:06.175764 76 : 4250, 4027
7172 23:09:06.178285 80 : 4361, 4138
7173 23:09:06.178854 84 : 4361, 4137
7174 23:09:06.179237 88 : 4250, 4027
7175 23:09:06.181308 92 : 4250, 4026
7176 23:09:06.181781 96 : 4250, 4027
7177 23:09:06.184893 100 : 4251, 2437
7178 23:09:06.185461 104 : 4250, 0
7179 23:09:06.188303 108 : 4251, 0
7180 23:09:06.188981 112 : 4250, 0
7181 23:09:06.189366 116 : 4250, 0
7182 23:09:06.191504 120 : 4253, 0
7183 23:09:06.192071 124 : 4250, 0
7184 23:09:06.194800 128 : 4252, 0
7185 23:09:06.195367 132 : 4361, 0
7186 23:09:06.195743 136 : 4361, 0
7187 23:09:06.198052 140 : 4250, 0
7188 23:09:06.198623 144 : 4250, 0
7189 23:09:06.201232 148 : 4360, 0
7190 23:09:06.201699 152 : 4361, 0
7191 23:09:06.202073 156 : 4252, 0
7192 23:09:06.204633 160 : 4253, 0
7193 23:09:06.205198 164 : 4250, 0
7194 23:09:06.205617 168 : 4252, 0
7195 23:09:06.208060 172 : 4253, 0
7196 23:09:06.208571 176 : 4250, 0
7197 23:09:06.211588 180 : 4250, 0
7198 23:09:06.212154 184 : 4360, 0
7199 23:09:06.212581 188 : 4250, 0
7200 23:09:06.214459 192 : 4361, 0
7201 23:09:06.215027 196 : 4252, 0
7202 23:09:06.218069 200 : 4360, 0
7203 23:09:06.218636 204 : 4250, 0
7204 23:09:06.219008 208 : 4252, 0
7205 23:09:06.220947 212 : 4253, 0
7206 23:09:06.221412 216 : 4250, 0
7207 23:09:06.224197 220 : 4252, 509
7208 23:09:06.224788 224 : 4250, 3968
7209 23:09:06.227480 228 : 4250, 4027
7210 23:09:06.227945 232 : 4250, 4027
7211 23:09:06.231282 236 : 4252, 4029
7212 23:09:06.231845 240 : 4250, 4027
7213 23:09:06.232219 244 : 4249, 4027
7214 23:09:06.234384 248 : 4360, 4137
7215 23:09:06.234970 252 : 4252, 4029
7216 23:09:06.237718 256 : 4250, 4027
7217 23:09:06.238188 260 : 4361, 4138
7218 23:09:06.240909 264 : 4251, 4027
7219 23:09:06.241480 268 : 4250, 4026
7220 23:09:06.244280 272 : 4361, 4137
7221 23:09:06.244898 276 : 4250, 4027
7222 23:09:06.247481 280 : 4250, 4027
7223 23:09:06.248051 284 : 4250, 4026
7224 23:09:06.251345 288 : 4250, 4026
7225 23:09:06.251917 292 : 4250, 4027
7226 23:09:06.254204 296 : 4249, 4027
7227 23:09:06.254770 300 : 4361, 4137
7228 23:09:06.255147 304 : 4250, 4027
7229 23:09:06.257171 308 : 4250, 4027
7230 23:09:06.257635 312 : 4361, 4138
7231 23:09:06.260867 316 : 4251, 4027
7232 23:09:06.261437 320 : 4250, 4026
7233 23:09:06.264244 324 : 4361, 4137
7234 23:09:06.264876 328 : 4250, 4027
7235 23:09:06.267648 332 : 4250, 4027
7236 23:09:06.268215 336 : 4251, 3914
7237 23:09:06.270511 340 : 4250, 2313
7238 23:09:06.270996 344 : 4250, 0
7239 23:09:06.271380
7240 23:09:06.273819 MIOCK jitter meter ch=0
7241 23:09:06.274281
7242 23:09:06.277301 1T = (344-104) = 240 dly cells
7243 23:09:06.280788 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 271/100 ps
7244 23:09:06.284027 ==
7245 23:09:06.284654 Dram Type= 6, Freq= 0, CH_0, rank 0
7246 23:09:06.290348 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7247 23:09:06.290813 ==
7248 23:09:06.293853 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7249 23:09:06.300475 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7250 23:09:06.303817 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7251 23:09:06.310284 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7252 23:09:06.318049 [CA 0] Center 42 (12~73) winsize 62
7253 23:09:06.321231 [CA 1] Center 42 (12~73) winsize 62
7254 23:09:06.324340 [CA 2] Center 39 (9~69) winsize 61
7255 23:09:06.327672 [CA 3] Center 38 (9~68) winsize 60
7256 23:09:06.331100 [CA 4] Center 37 (7~67) winsize 61
7257 23:09:06.334364 [CA 5] Center 36 (6~66) winsize 61
7258 23:09:06.334946
7259 23:09:06.337651 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7260 23:09:06.338115
7261 23:09:06.341175 [CATrainingPosCal] consider 1 rank data
7262 23:09:06.344352 u2DelayCellTimex100 = 271/100 ps
7263 23:09:06.347896 CA0 delay=42 (12~73),Diff = 6 PI (21 cell)
7264 23:09:06.354329 CA1 delay=42 (12~73),Diff = 6 PI (21 cell)
7265 23:09:06.357505 CA2 delay=39 (9~69),Diff = 3 PI (10 cell)
7266 23:09:06.360967 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7267 23:09:06.364252 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
7268 23:09:06.367584 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7269 23:09:06.368145
7270 23:09:06.370860 CA PerBit enable=1, Macro0, CA PI delay=36
7271 23:09:06.371426
7272 23:09:06.374131 [CBTSetCACLKResult] CA Dly = 36
7273 23:09:06.377464 CS Dly: 10 (0~41)
7274 23:09:06.380715 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7275 23:09:06.384007 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7276 23:09:06.384596 ==
7277 23:09:06.387509 Dram Type= 6, Freq= 0, CH_0, rank 1
7278 23:09:06.390556 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7279 23:09:06.394086 ==
7280 23:09:06.397151 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7281 23:09:06.401026 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7282 23:09:06.407578 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7283 23:09:06.413712 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7284 23:09:06.420655 [CA 0] Center 42 (12~73) winsize 62
7285 23:09:06.423924 [CA 1] Center 41 (11~72) winsize 62
7286 23:09:06.427274 [CA 2] Center 38 (8~68) winsize 61
7287 23:09:06.430514 [CA 3] Center 37 (7~67) winsize 61
7288 23:09:06.433936 [CA 4] Center 35 (5~65) winsize 61
7289 23:09:06.437137 [CA 5] Center 35 (5~66) winsize 62
7290 23:09:06.437600
7291 23:09:06.441106 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7292 23:09:06.441674
7293 23:09:06.443496 [CATrainingPosCal] consider 2 rank data
7294 23:09:06.446979 u2DelayCellTimex100 = 271/100 ps
7295 23:09:06.450388 CA0 delay=42 (12~73),Diff = 6 PI (21 cell)
7296 23:09:06.456788 CA1 delay=42 (12~72),Diff = 6 PI (21 cell)
7297 23:09:06.460323 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
7298 23:09:06.463259 CA3 delay=38 (9~67),Diff = 2 PI (7 cell)
7299 23:09:06.466879 CA4 delay=36 (7~65),Diff = 0 PI (0 cell)
7300 23:09:06.470296 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7301 23:09:06.470759
7302 23:09:06.473467 CA PerBit enable=1, Macro0, CA PI delay=36
7303 23:09:06.474030
7304 23:09:06.476600 [CBTSetCACLKResult] CA Dly = 36
7305 23:09:06.479826 CS Dly: 11 (0~43)
7306 23:09:06.483560 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7307 23:09:06.487162 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7308 23:09:06.487737
7309 23:09:06.490065 ----->DramcWriteLeveling(PI) begin...
7310 23:09:06.490542 ==
7311 23:09:06.493086 Dram Type= 6, Freq= 0, CH_0, rank 0
7312 23:09:06.499929 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7313 23:09:06.500486 ==
7314 23:09:06.503211 Write leveling (Byte 0): 29 => 29
7315 23:09:06.503861 Write leveling (Byte 1): 26 => 26
7316 23:09:06.506497 DramcWriteLeveling(PI) end<-----
7317 23:09:06.506950
7318 23:09:06.509659 ==
7319 23:09:06.512999 Dram Type= 6, Freq= 0, CH_0, rank 0
7320 23:09:06.516604 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7321 23:09:06.517167 ==
7322 23:09:06.519722 [Gating] SW mode calibration
7323 23:09:06.525792 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7324 23:09:06.529206 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7325 23:09:06.535962 0 12 0 | B1->B0 | 2323 2525 | 0 1 | (0 0) (1 1)
7326 23:09:06.539463 0 12 4 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
7327 23:09:06.542773 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7328 23:09:06.549298 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7329 23:09:06.552494 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7330 23:09:06.556324 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7331 23:09:06.562616 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7332 23:09:06.565839 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7333 23:09:06.568910 0 13 0 | B1->B0 | 3434 2d2d | 1 0 | (1 0) (1 0)
7334 23:09:06.575738 0 13 4 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
7335 23:09:06.578915 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7336 23:09:06.582045 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7337 23:09:06.588980 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7338 23:09:06.592237 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7339 23:09:06.595528 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7340 23:09:06.602141 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7341 23:09:06.605099 0 14 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (0 0)
7342 23:09:06.608770 0 14 4 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
7343 23:09:06.615175 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7344 23:09:06.618851 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7345 23:09:06.621655 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7346 23:09:06.628205 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7347 23:09:06.631919 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7348 23:09:06.635091 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7349 23:09:06.641977 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7350 23:09:06.645114 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7351 23:09:06.648483 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7352 23:09:06.654979 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7353 23:09:06.658054 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7354 23:09:06.661471 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7355 23:09:06.668213 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7356 23:09:06.671550 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7357 23:09:06.674986 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7358 23:09:06.681431 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7359 23:09:06.684677 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7360 23:09:06.688161 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7361 23:09:06.694230 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7362 23:09:06.698022 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7363 23:09:06.700780 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7364 23:09:06.707581 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7365 23:09:06.711190 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7366 23:09:06.714467 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7367 23:09:06.721341 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7368 23:09:06.721909 Total UI for P1: 0, mck2ui 16
7369 23:09:06.727397 best dqsien dly found for B0: ( 1, 1, 0)
7370 23:09:06.727884 Total UI for P1: 0, mck2ui 16
7371 23:09:06.734126 best dqsien dly found for B1: ( 1, 1, 2)
7372 23:09:06.737646 best DQS0 dly(MCK, UI, PI) = (1, 1, 0)
7373 23:09:06.740760 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
7374 23:09:06.741222
7375 23:09:06.744344 best DQS0 P1 dly(MCK, UI, PI) = (1, 5, 0)
7376 23:09:06.747561 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
7377 23:09:06.750771 [Gating] SW calibration Done
7378 23:09:06.751230 ==
7379 23:09:06.754005 Dram Type= 6, Freq= 0, CH_0, rank 0
7380 23:09:06.757126 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7381 23:09:06.757594 ==
7382 23:09:06.760682 RX Vref Scan: 0
7383 23:09:06.761240
7384 23:09:06.761607 RX Vref 0 -> 0, step: 1
7385 23:09:06.761953
7386 23:09:06.764398 RX Delay 0 -> 252, step: 8
7387 23:09:06.767432 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7388 23:09:06.770808 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7389 23:09:06.777361 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
7390 23:09:06.780730 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7391 23:09:06.783976 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7392 23:09:06.787062 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7393 23:09:06.790290 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7394 23:09:06.797092 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7395 23:09:06.800301 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
7396 23:09:06.803795 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7397 23:09:06.807069 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7398 23:09:06.813732 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7399 23:09:06.816796 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7400 23:09:06.819929 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7401 23:09:06.823435 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
7402 23:09:06.826807 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7403 23:09:06.830620 ==
7404 23:09:06.831183 Dram Type= 6, Freq= 0, CH_0, rank 0
7405 23:09:06.836676 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7406 23:09:06.837234 ==
7407 23:09:06.837790 DQS Delay:
7408 23:09:06.839996 DQS0 = 0, DQS1 = 0
7409 23:09:06.840590 DQM Delay:
7410 23:09:06.842960 DQM0 = 130, DQM1 = 124
7411 23:09:06.843438 DQ Delay:
7412 23:09:06.846332 DQ0 =127, DQ1 =131, DQ2 =123, DQ3 =127
7413 23:09:06.849717 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7414 23:09:06.853133 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
7415 23:09:06.856437 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7416 23:09:06.857051
7417 23:09:06.857481
7418 23:09:06.857832 ==
7419 23:09:06.859618 Dram Type= 6, Freq= 0, CH_0, rank 0
7420 23:09:06.866512 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7421 23:09:06.867099 ==
7422 23:09:06.867474
7423 23:09:06.867816
7424 23:09:06.868140 TX Vref Scan disable
7425 23:09:06.870284 == TX Byte 0 ==
7426 23:09:06.873196 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7427 23:09:06.879937 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7428 23:09:06.880501 == TX Byte 1 ==
7429 23:09:06.883231 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7430 23:09:06.889742 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7431 23:09:06.890299 ==
7432 23:09:06.893141 Dram Type= 6, Freq= 0, CH_0, rank 0
7433 23:09:06.896657 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7434 23:09:06.897218 ==
7435 23:09:06.909105
7436 23:09:06.912726 TX Vref early break, caculate TX vref
7437 23:09:06.915831 TX Vref=16, minBit 8, minWin=21, winSum=369
7438 23:09:06.919304 TX Vref=18, minBit 8, minWin=22, winSum=379
7439 23:09:06.922526 TX Vref=20, minBit 8, minWin=23, winSum=391
7440 23:09:06.925812 TX Vref=22, minBit 8, minWin=24, winSum=399
7441 23:09:06.929304 TX Vref=24, minBit 8, minWin=24, winSum=407
7442 23:09:06.935576 TX Vref=26, minBit 8, minWin=24, winSum=416
7443 23:09:06.939216 TX Vref=28, minBit 3, minWin=25, winSum=414
7444 23:09:06.942558 TX Vref=30, minBit 0, minWin=25, winSum=410
7445 23:09:06.945858 TX Vref=32, minBit 8, minWin=24, winSum=400
7446 23:09:06.948895 TX Vref=34, minBit 8, minWin=23, winSum=387
7447 23:09:06.955495 [TxChooseVref] Worse bit 3, Min win 25, Win sum 414, Final Vref 28
7448 23:09:06.956059
7449 23:09:06.959086 Final TX Range 0 Vref 28
7450 23:09:06.959644
7451 23:09:06.960027 ==
7452 23:09:06.962065 Dram Type= 6, Freq= 0, CH_0, rank 0
7453 23:09:06.965479 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7454 23:09:06.965946 ==
7455 23:09:06.966320
7456 23:09:06.966659
7457 23:09:06.968481 TX Vref Scan disable
7458 23:09:06.975373 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7459 23:09:06.975949 == TX Byte 0 ==
7460 23:09:06.978725 u2DelayCellOfst[0]=14 cells (4 PI)
7461 23:09:06.982082 u2DelayCellOfst[1]=18 cells (5 PI)
7462 23:09:06.984996 u2DelayCellOfst[2]=14 cells (4 PI)
7463 23:09:06.988661 u2DelayCellOfst[3]=10 cells (3 PI)
7464 23:09:06.991635 u2DelayCellOfst[4]=10 cells (3 PI)
7465 23:09:06.995217 u2DelayCellOfst[5]=0 cells (0 PI)
7466 23:09:06.998643 u2DelayCellOfst[6]=18 cells (5 PI)
7467 23:09:07.001845 u2DelayCellOfst[7]=18 cells (5 PI)
7468 23:09:07.005120 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7469 23:09:07.008613 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7470 23:09:07.011382 == TX Byte 1 ==
7471 23:09:07.014810 u2DelayCellOfst[8]=3 cells (1 PI)
7472 23:09:07.015291 u2DelayCellOfst[9]=0 cells (0 PI)
7473 23:09:07.018306 u2DelayCellOfst[10]=10 cells (3 PI)
7474 23:09:07.021430 u2DelayCellOfst[11]=7 cells (2 PI)
7475 23:09:07.024660 u2DelayCellOfst[12]=18 cells (5 PI)
7476 23:09:07.028379 u2DelayCellOfst[13]=14 cells (4 PI)
7477 23:09:07.031347 u2DelayCellOfst[14]=18 cells (5 PI)
7478 23:09:07.034998 u2DelayCellOfst[15]=14 cells (4 PI)
7479 23:09:07.038056 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
7480 23:09:07.044706 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7481 23:09:07.045171 DramC Write-DBI on
7482 23:09:07.045537 ==
7483 23:09:07.048026 Dram Type= 6, Freq= 0, CH_0, rank 0
7484 23:09:07.054836 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7485 23:09:07.055399 ==
7486 23:09:07.055771
7487 23:09:07.056107
7488 23:09:07.056430 TX Vref Scan disable
7489 23:09:07.058499 == TX Byte 0 ==
7490 23:09:07.061938 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7491 23:09:07.065033 == TX Byte 1 ==
7492 23:09:07.068686 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
7493 23:09:07.071890 DramC Write-DBI off
7494 23:09:07.072449
7495 23:09:07.072894 [DATLAT]
7496 23:09:07.073238 Freq=1600, CH0 RK0
7497 23:09:07.073571
7498 23:09:07.075111 DATLAT Default: 0xf
7499 23:09:07.075585 0, 0xFFFF, sum = 0
7500 23:09:07.078822 1, 0xFFFF, sum = 0
7501 23:09:07.082026 2, 0xFFFF, sum = 0
7502 23:09:07.082595 3, 0xFFFF, sum = 0
7503 23:09:07.085253 4, 0xFFFF, sum = 0
7504 23:09:07.085718 5, 0xFFFF, sum = 0
7505 23:09:07.088363 6, 0xFFFF, sum = 0
7506 23:09:07.088865 7, 0xFFFF, sum = 0
7507 23:09:07.091703 8, 0xFFFF, sum = 0
7508 23:09:07.092169 9, 0xFFFF, sum = 0
7509 23:09:07.094921 10, 0xFFFF, sum = 0
7510 23:09:07.095401 11, 0xFFFF, sum = 0
7511 23:09:07.098651 12, 0x8FFF, sum = 0
7512 23:09:07.099115 13, 0x0, sum = 1
7513 23:09:07.101472 14, 0x0, sum = 2
7514 23:09:07.101937 15, 0x0, sum = 3
7515 23:09:07.104850 16, 0x0, sum = 4
7516 23:09:07.105314 best_step = 14
7517 23:09:07.105768
7518 23:09:07.106232 ==
7519 23:09:07.108137 Dram Type= 6, Freq= 0, CH_0, rank 0
7520 23:09:07.111438 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7521 23:09:07.115008 ==
7522 23:09:07.115468 RX Vref Scan: 1
7523 23:09:07.115830
7524 23:09:07.118136 Set Vref Range= 24 -> 127
7525 23:09:07.118652
7526 23:09:07.121877 RX Vref 24 -> 127, step: 1
7527 23:09:07.122434
7528 23:09:07.122802 RX Delay 11 -> 252, step: 4
7529 23:09:07.123144
7530 23:09:07.124891 Set Vref, RX VrefLevel [Byte0]: 24
7531 23:09:07.128187 [Byte1]: 24
7532 23:09:07.132238
7533 23:09:07.132849 Set Vref, RX VrefLevel [Byte0]: 25
7534 23:09:07.135405 [Byte1]: 25
7535 23:09:07.139817
7536 23:09:07.140379 Set Vref, RX VrefLevel [Byte0]: 26
7537 23:09:07.142943 [Byte1]: 26
7538 23:09:07.147377
7539 23:09:07.147936 Set Vref, RX VrefLevel [Byte0]: 27
7540 23:09:07.150778 [Byte1]: 27
7541 23:09:07.154723
7542 23:09:07.155280 Set Vref, RX VrefLevel [Byte0]: 28
7543 23:09:07.158058 [Byte1]: 28
7544 23:09:07.162372
7545 23:09:07.162933 Set Vref, RX VrefLevel [Byte0]: 29
7546 23:09:07.165572 [Byte1]: 29
7547 23:09:07.170330
7548 23:09:07.170905 Set Vref, RX VrefLevel [Byte0]: 30
7549 23:09:07.173270 [Byte1]: 30
7550 23:09:07.177586
7551 23:09:07.178148 Set Vref, RX VrefLevel [Byte0]: 31
7552 23:09:07.180831 [Byte1]: 31
7553 23:09:07.185108
7554 23:09:07.185565 Set Vref, RX VrefLevel [Byte0]: 32
7555 23:09:07.188568 [Byte1]: 32
7556 23:09:07.192659
7557 23:09:07.193121 Set Vref, RX VrefLevel [Byte0]: 33
7558 23:09:07.196141 [Byte1]: 33
7559 23:09:07.200312
7560 23:09:07.200814 Set Vref, RX VrefLevel [Byte0]: 34
7561 23:09:07.203667 [Byte1]: 34
7562 23:09:07.208075
7563 23:09:07.208582 Set Vref, RX VrefLevel [Byte0]: 35
7564 23:09:07.211281 [Byte1]: 35
7565 23:09:07.215775
7566 23:09:07.216341 Set Vref, RX VrefLevel [Byte0]: 36
7567 23:09:07.219139 [Byte1]: 36
7568 23:09:07.223504
7569 23:09:07.224060 Set Vref, RX VrefLevel [Byte0]: 37
7570 23:09:07.226651 [Byte1]: 37
7571 23:09:07.230787
7572 23:09:07.231246 Set Vref, RX VrefLevel [Byte0]: 38
7573 23:09:07.234539 [Byte1]: 38
7574 23:09:07.238601
7575 23:09:07.239163 Set Vref, RX VrefLevel [Byte0]: 39
7576 23:09:07.242220 [Byte1]: 39
7577 23:09:07.246308
7578 23:09:07.246862 Set Vref, RX VrefLevel [Byte0]: 40
7579 23:09:07.249447 [Byte1]: 40
7580 23:09:07.253910
7581 23:09:07.254469 Set Vref, RX VrefLevel [Byte0]: 41
7582 23:09:07.257244 [Byte1]: 41
7583 23:09:07.261272
7584 23:09:07.261829 Set Vref, RX VrefLevel [Byte0]: 42
7585 23:09:07.264897 [Byte1]: 42
7586 23:09:07.269155
7587 23:09:07.269714 Set Vref, RX VrefLevel [Byte0]: 43
7588 23:09:07.272327 [Byte1]: 43
7589 23:09:07.276927
7590 23:09:07.277484 Set Vref, RX VrefLevel [Byte0]: 44
7591 23:09:07.279989 [Byte1]: 44
7592 23:09:07.284130
7593 23:09:07.284721 Set Vref, RX VrefLevel [Byte0]: 45
7594 23:09:07.287796 [Byte1]: 45
7595 23:09:07.291948
7596 23:09:07.292743 Set Vref, RX VrefLevel [Byte0]: 46
7597 23:09:07.294943 [Byte1]: 46
7598 23:09:07.299256
7599 23:09:07.299712 Set Vref, RX VrefLevel [Byte0]: 47
7600 23:09:07.302856 [Byte1]: 47
7601 23:09:07.307081
7602 23:09:07.307650 Set Vref, RX VrefLevel [Byte0]: 48
7603 23:09:07.310066 [Byte1]: 48
7604 23:09:07.314313
7605 23:09:07.314772 Set Vref, RX VrefLevel [Byte0]: 49
7606 23:09:07.318121 [Byte1]: 49
7607 23:09:07.322509
7608 23:09:07.323108 Set Vref, RX VrefLevel [Byte0]: 50
7609 23:09:07.325677 [Byte1]: 50
7610 23:09:07.329579
7611 23:09:07.330078 Set Vref, RX VrefLevel [Byte0]: 51
7612 23:09:07.333043 [Byte1]: 51
7613 23:09:07.337182
7614 23:09:07.337650 Set Vref, RX VrefLevel [Byte0]: 52
7615 23:09:07.340767 [Byte1]: 52
7616 23:09:07.345198
7617 23:09:07.345754 Set Vref, RX VrefLevel [Byte0]: 53
7618 23:09:07.348694 [Byte1]: 53
7619 23:09:07.352669
7620 23:09:07.353220 Set Vref, RX VrefLevel [Byte0]: 54
7621 23:09:07.355825 [Byte1]: 54
7622 23:09:07.360678
7623 23:09:07.361237 Set Vref, RX VrefLevel [Byte0]: 55
7624 23:09:07.364067 [Byte1]: 55
7625 23:09:07.368154
7626 23:09:07.368751 Set Vref, RX VrefLevel [Byte0]: 56
7627 23:09:07.371267 [Byte1]: 56
7628 23:09:07.375610
7629 23:09:07.376165 Set Vref, RX VrefLevel [Byte0]: 57
7630 23:09:07.378909 [Byte1]: 57
7631 23:09:07.383478
7632 23:09:07.384065 Set Vref, RX VrefLevel [Byte0]: 58
7633 23:09:07.386400 [Byte1]: 58
7634 23:09:07.390777
7635 23:09:07.391341 Set Vref, RX VrefLevel [Byte0]: 59
7636 23:09:07.394033 [Byte1]: 59
7637 23:09:07.398441
7638 23:09:07.399005 Set Vref, RX VrefLevel [Byte0]: 60
7639 23:09:07.401825 [Byte1]: 60
7640 23:09:07.406224
7641 23:09:07.406689 Set Vref, RX VrefLevel [Byte0]: 61
7642 23:09:07.409102 [Byte1]: 61
7643 23:09:07.413819
7644 23:09:07.414376 Set Vref, RX VrefLevel [Byte0]: 62
7645 23:09:07.416877 [Byte1]: 62
7646 23:09:07.421041
7647 23:09:07.421541 Set Vref, RX VrefLevel [Byte0]: 63
7648 23:09:07.424317 [Byte1]: 63
7649 23:09:07.428843
7650 23:09:07.429385 Set Vref, RX VrefLevel [Byte0]: 64
7651 23:09:07.431897 [Byte1]: 64
7652 23:09:07.436698
7653 23:09:07.437303 Set Vref, RX VrefLevel [Byte0]: 65
7654 23:09:07.439918 [Byte1]: 65
7655 23:09:07.444105
7656 23:09:07.444772 Set Vref, RX VrefLevel [Byte0]: 66
7657 23:09:07.447283 [Byte1]: 66
7658 23:09:07.451604
7659 23:09:07.452161 Set Vref, RX VrefLevel [Byte0]: 67
7660 23:09:07.455086 [Byte1]: 67
7661 23:09:07.459314
7662 23:09:07.459872 Set Vref, RX VrefLevel [Byte0]: 68
7663 23:09:07.462792 [Byte1]: 68
7664 23:09:07.467082
7665 23:09:07.467640 Set Vref, RX VrefLevel [Byte0]: 69
7666 23:09:07.470274 [Byte1]: 69
7667 23:09:07.474502
7668 23:09:07.475060 Set Vref, RX VrefLevel [Byte0]: 70
7669 23:09:07.477831 [Byte1]: 70
7670 23:09:07.482189
7671 23:09:07.482747 Set Vref, RX VrefLevel [Byte0]: 71
7672 23:09:07.485269 [Byte1]: 71
7673 23:09:07.489889
7674 23:09:07.490470 Final RX Vref Byte 0 = 53 to rank0
7675 23:09:07.493112 Final RX Vref Byte 1 = 57 to rank0
7676 23:09:07.496307 Final RX Vref Byte 0 = 53 to rank1
7677 23:09:07.500021 Final RX Vref Byte 1 = 57 to rank1==
7678 23:09:07.503025 Dram Type= 6, Freq= 0, CH_0, rank 0
7679 23:09:07.509496 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7680 23:09:07.510059 ==
7681 23:09:07.510429 DQS Delay:
7682 23:09:07.510770 DQS0 = 0, DQS1 = 0
7683 23:09:07.512713 DQM Delay:
7684 23:09:07.513170 DQM0 = 127, DQM1 = 121
7685 23:09:07.516274 DQ Delay:
7686 23:09:07.519869 DQ0 =124, DQ1 =128, DQ2 =124, DQ3 =122
7687 23:09:07.522450 DQ4 =130, DQ5 =116, DQ6 =138, DQ7 =134
7688 23:09:07.526277 DQ8 =110, DQ9 =106, DQ10 =122, DQ11 =112
7689 23:09:07.529104 DQ12 =126, DQ13 =126, DQ14 =136, DQ15 =134
7690 23:09:07.529627
7691 23:09:07.530051
7692 23:09:07.530551
7693 23:09:07.532731 [DramC_TX_OE_Calibration] TA2
7694 23:09:07.536022 Original DQ_B0 (3 6) =30, OEN = 27
7695 23:09:07.539336 Original DQ_B1 (3 6) =30, OEN = 27
7696 23:09:07.542949 24, 0x0, End_B0=24 End_B1=24
7697 23:09:07.543519 25, 0x0, End_B0=25 End_B1=25
7698 23:09:07.545839 26, 0x0, End_B0=26 End_B1=26
7699 23:09:07.549129 27, 0x0, End_B0=27 End_B1=27
7700 23:09:07.552948 28, 0x0, End_B0=28 End_B1=28
7701 23:09:07.556267 29, 0x0, End_B0=29 End_B1=29
7702 23:09:07.556880 30, 0x0, End_B0=30 End_B1=30
7703 23:09:07.559084 31, 0x4141, End_B0=30 End_B1=30
7704 23:09:07.562843 Byte0 end_step=30 best_step=27
7705 23:09:07.566183 Byte1 end_step=30 best_step=27
7706 23:09:07.569018 Byte0 TX OE(2T, 0.5T) = (3, 3)
7707 23:09:07.572389 Byte1 TX OE(2T, 0.5T) = (3, 3)
7708 23:09:07.572994
7709 23:09:07.573363
7710 23:09:07.579046 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f1f, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
7711 23:09:07.582506 CH0 RK0: MR19=303, MR18=1F1F
7712 23:09:07.589036 CH0_RK0: MR19=0x303, MR18=0x1F1F, DQSOSC=394, MR23=63, INC=23, DEC=15
7713 23:09:07.589601
7714 23:09:07.592671 ----->DramcWriteLeveling(PI) begin...
7715 23:09:07.593241 ==
7716 23:09:07.595420 Dram Type= 6, Freq= 0, CH_0, rank 1
7717 23:09:07.598645 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7718 23:09:07.599109 ==
7719 23:09:07.602251 Write leveling (Byte 0): 29 => 29
7720 23:09:07.605706 Write leveling (Byte 1): 26 => 26
7721 23:09:07.608989 DramcWriteLeveling(PI) end<-----
7722 23:09:07.609546
7723 23:09:07.609913 ==
7724 23:09:07.612171 Dram Type= 6, Freq= 0, CH_0, rank 1
7725 23:09:07.615557 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7726 23:09:07.616118 ==
7727 23:09:07.619110 [Gating] SW mode calibration
7728 23:09:07.625384 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7729 23:09:07.631855 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7730 23:09:07.634940 0 12 0 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
7731 23:09:07.641977 0 12 4 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
7732 23:09:07.645301 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7733 23:09:07.648869 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7734 23:09:07.655229 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7735 23:09:07.658524 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7736 23:09:07.661965 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7737 23:09:07.668606 0 12 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
7738 23:09:07.671661 0 13 0 | B1->B0 | 3434 2b2b | 1 1 | (1 1) (1 0)
7739 23:09:07.675176 0 13 4 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
7740 23:09:07.682192 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7741 23:09:07.685063 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7742 23:09:07.688338 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7743 23:09:07.694828 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7744 23:09:07.698114 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7745 23:09:07.701350 0 13 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7746 23:09:07.708218 0 14 0 | B1->B0 | 2323 4141 | 0 0 | (0 0) (0 0)
7747 23:09:07.711600 0 14 4 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
7748 23:09:07.715082 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7749 23:09:07.721577 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7750 23:09:07.724452 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7751 23:09:07.727749 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7752 23:09:07.731137 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7753 23:09:07.737846 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7754 23:09:07.741096 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7755 23:09:07.744786 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7756 23:09:07.751326 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7757 23:09:07.754769 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7758 23:09:07.757937 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7759 23:09:07.764683 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7760 23:09:07.768007 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7761 23:09:07.771505 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7762 23:09:07.777603 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7763 23:09:07.781078 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7764 23:09:07.784303 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7765 23:09:07.790986 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7766 23:09:07.794092 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7767 23:09:07.797432 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7768 23:09:07.804341 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7769 23:09:07.807943 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7770 23:09:07.810911 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7771 23:09:07.817317 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7772 23:09:07.817867 Total UI for P1: 0, mck2ui 16
7773 23:09:07.824287 best dqsien dly found for B0: ( 1, 0, 30)
7774 23:09:07.827248 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7775 23:09:07.830532 Total UI for P1: 0, mck2ui 16
7776 23:09:07.833889 best dqsien dly found for B1: ( 1, 1, 4)
7777 23:09:07.837025 best DQS0 dly(MCK, UI, PI) = (1, 0, 30)
7778 23:09:07.840328 best DQS1 dly(MCK, UI, PI) = (1, 1, 4)
7779 23:09:07.840814
7780 23:09:07.844219 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 30)
7781 23:09:07.847021 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 4)
7782 23:09:07.850659 [Gating] SW calibration Done
7783 23:09:07.851238 ==
7784 23:09:07.853702 Dram Type= 6, Freq= 0, CH_0, rank 1
7785 23:09:07.857143 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7786 23:09:07.860369 ==
7787 23:09:07.860854 RX Vref Scan: 0
7788 23:09:07.861223
7789 23:09:07.863796 RX Vref 0 -> 0, step: 1
7790 23:09:07.864354
7791 23:09:07.864767 RX Delay 0 -> 252, step: 8
7792 23:09:07.870281 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7793 23:09:07.873877 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7794 23:09:07.877176 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7795 23:09:07.880394 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7796 23:09:07.884070 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
7797 23:09:07.890551 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7798 23:09:07.893775 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7799 23:09:07.896820 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7800 23:09:07.899949 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7801 23:09:07.903491 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7802 23:09:07.910138 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7803 23:09:07.913223 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7804 23:09:07.916401 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7805 23:09:07.920185 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7806 23:09:07.926682 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7807 23:09:07.929835 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7808 23:09:07.930300 ==
7809 23:09:07.933218 Dram Type= 6, Freq= 0, CH_0, rank 1
7810 23:09:07.936160 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7811 23:09:07.936650 ==
7812 23:09:07.939929 DQS Delay:
7813 23:09:07.940484 DQS0 = 0, DQS1 = 0
7814 23:09:07.940912 DQM Delay:
7815 23:09:07.942804 DQM0 = 131, DQM1 = 124
7816 23:09:07.943388 DQ Delay:
7817 23:09:07.946181 DQ0 =127, DQ1 =135, DQ2 =131, DQ3 =127
7818 23:09:07.949484 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
7819 23:09:07.953196 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =119
7820 23:09:07.959866 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =131
7821 23:09:07.960436
7822 23:09:07.960851
7823 23:09:07.961189 ==
7824 23:09:07.963048 Dram Type= 6, Freq= 0, CH_0, rank 1
7825 23:09:07.966491 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7826 23:09:07.967054 ==
7827 23:09:07.967422
7828 23:09:07.967759
7829 23:09:07.969832 TX Vref Scan disable
7830 23:09:07.970389 == TX Byte 0 ==
7831 23:09:07.976286 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7832 23:09:07.979393 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7833 23:09:07.979952 == TX Byte 1 ==
7834 23:09:07.985964 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7835 23:09:07.989350 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7836 23:09:07.990066 ==
7837 23:09:07.993222 Dram Type= 6, Freq= 0, CH_0, rank 1
7838 23:09:07.995710 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7839 23:09:07.996187 ==
7840 23:09:08.010389
7841 23:09:08.013362 TX Vref early break, caculate TX vref
7842 23:09:08.016637 TX Vref=16, minBit 7, minWin=22, winSum=372
7843 23:09:08.020071 TX Vref=18, minBit 11, minWin=22, winSum=381
7844 23:09:08.023404 TX Vref=20, minBit 7, minWin=23, winSum=390
7845 23:09:08.026964 TX Vref=22, minBit 8, minWin=23, winSum=394
7846 23:09:08.029938 TX Vref=24, minBit 8, minWin=24, winSum=407
7847 23:09:08.036862 TX Vref=26, minBit 8, minWin=24, winSum=412
7848 23:09:08.040014 TX Vref=28, minBit 8, minWin=24, winSum=410
7849 23:09:08.043189 TX Vref=30, minBit 8, minWin=24, winSum=410
7850 23:09:08.046796 TX Vref=32, minBit 1, minWin=24, winSum=402
7851 23:09:08.049919 TX Vref=34, minBit 8, minWin=22, winSum=389
7852 23:09:08.056586 [TxChooseVref] Worse bit 8, Min win 24, Win sum 412, Final Vref 26
7853 23:09:08.057156
7854 23:09:08.060376 Final TX Range 0 Vref 26
7855 23:09:08.060981
7856 23:09:08.061348 ==
7857 23:09:08.063176 Dram Type= 6, Freq= 0, CH_0, rank 1
7858 23:09:08.066718 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7859 23:09:08.067284 ==
7860 23:09:08.067655
7861 23:09:08.067996
7862 23:09:08.069796 TX Vref Scan disable
7863 23:09:08.076409 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7864 23:09:08.077015 == TX Byte 0 ==
7865 23:09:08.079707 u2DelayCellOfst[0]=14 cells (4 PI)
7866 23:09:08.083032 u2DelayCellOfst[1]=18 cells (5 PI)
7867 23:09:08.086221 u2DelayCellOfst[2]=14 cells (4 PI)
7868 23:09:08.089682 u2DelayCellOfst[3]=14 cells (4 PI)
7869 23:09:08.092728 u2DelayCellOfst[4]=7 cells (2 PI)
7870 23:09:08.096448 u2DelayCellOfst[5]=0 cells (0 PI)
7871 23:09:08.099441 u2DelayCellOfst[6]=18 cells (5 PI)
7872 23:09:08.103002 u2DelayCellOfst[7]=18 cells (5 PI)
7873 23:09:08.105996 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7874 23:09:08.109518 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7875 23:09:08.112631 == TX Byte 1 ==
7876 23:09:08.116049 u2DelayCellOfst[8]=3 cells (1 PI)
7877 23:09:08.116655 u2DelayCellOfst[9]=0 cells (0 PI)
7878 23:09:08.119600 u2DelayCellOfst[10]=10 cells (3 PI)
7879 23:09:08.122791 u2DelayCellOfst[11]=3 cells (1 PI)
7880 23:09:08.126210 u2DelayCellOfst[12]=14 cells (4 PI)
7881 23:09:08.128987 u2DelayCellOfst[13]=14 cells (4 PI)
7882 23:09:08.132396 u2DelayCellOfst[14]=18 cells (5 PI)
7883 23:09:08.135820 u2DelayCellOfst[15]=14 cells (4 PI)
7884 23:09:08.142666 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
7885 23:09:08.145848 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7886 23:09:08.146433 DramC Write-DBI on
7887 23:09:08.146806 ==
7888 23:09:08.148846 Dram Type= 6, Freq= 0, CH_0, rank 1
7889 23:09:08.155574 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7890 23:09:08.156118 ==
7891 23:09:08.156489
7892 23:09:08.156894
7893 23:09:08.157219 TX Vref Scan disable
7894 23:09:08.159865 == TX Byte 0 ==
7895 23:09:08.163123 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7896 23:09:08.166396 == TX Byte 1 ==
7897 23:09:08.169425 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
7898 23:09:08.173084 DramC Write-DBI off
7899 23:09:08.173639
7900 23:09:08.173999 [DATLAT]
7901 23:09:08.174339 Freq=1600, CH0 RK1
7902 23:09:08.174671
7903 23:09:08.175902 DATLAT Default: 0xe
7904 23:09:08.179654 0, 0xFFFF, sum = 0
7905 23:09:08.180225 1, 0xFFFF, sum = 0
7906 23:09:08.183121 2, 0xFFFF, sum = 0
7907 23:09:08.183710 3, 0xFFFF, sum = 0
7908 23:09:08.185947 4, 0xFFFF, sum = 0
7909 23:09:08.186414 5, 0xFFFF, sum = 0
7910 23:09:08.189456 6, 0xFFFF, sum = 0
7911 23:09:08.190027 7, 0xFFFF, sum = 0
7912 23:09:08.193305 8, 0xFFFF, sum = 0
7913 23:09:08.193871 9, 0xFFFF, sum = 0
7914 23:09:08.196150 10, 0xFFFF, sum = 0
7915 23:09:08.196651 11, 0xFFFF, sum = 0
7916 23:09:08.199447 12, 0x8FFF, sum = 0
7917 23:09:08.199913 13, 0x0, sum = 1
7918 23:09:08.202730 14, 0x0, sum = 2
7919 23:09:08.203197 15, 0x0, sum = 3
7920 23:09:08.206144 16, 0x0, sum = 4
7921 23:09:08.206722 best_step = 14
7922 23:09:08.207095
7923 23:09:08.207435 ==
7924 23:09:08.209410 Dram Type= 6, Freq= 0, CH_0, rank 1
7925 23:09:08.212667 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7926 23:09:08.216089 ==
7927 23:09:08.216692 RX Vref Scan: 0
7928 23:09:08.217070
7929 23:09:08.219871 RX Vref 0 -> 0, step: 1
7930 23:09:08.220429
7931 23:09:08.222327 RX Delay 11 -> 252, step: 4
7932 23:09:08.225940 iDelay=195, Bit 0, Center 122 (67 ~ 178) 112
7933 23:09:08.228949 iDelay=195, Bit 1, Center 132 (79 ~ 186) 108
7934 23:09:08.232278 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
7935 23:09:08.239222 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
7936 23:09:08.242697 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
7937 23:09:08.245914 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
7938 23:09:08.249158 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
7939 23:09:08.252467 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
7940 23:09:08.259392 iDelay=195, Bit 8, Center 108 (55 ~ 162) 108
7941 23:09:08.262449 iDelay=195, Bit 9, Center 106 (51 ~ 162) 112
7942 23:09:08.265429 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
7943 23:09:08.268971 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
7944 23:09:08.272120 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
7945 23:09:08.279200 iDelay=195, Bit 13, Center 128 (75 ~ 182) 108
7946 23:09:08.282124 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
7947 23:09:08.285469 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
7948 23:09:08.286099 ==
7949 23:09:08.288677 Dram Type= 6, Freq= 0, CH_0, rank 1
7950 23:09:08.292098 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7951 23:09:08.295135 ==
7952 23:09:08.295665 DQS Delay:
7953 23:09:08.296033 DQS0 = 0, DQS1 = 0
7954 23:09:08.298383 DQM Delay:
7955 23:09:08.298845 DQM0 = 128, DQM1 = 120
7956 23:09:08.302055 DQ Delay:
7957 23:09:08.305463 DQ0 =122, DQ1 =132, DQ2 =126, DQ3 =124
7958 23:09:08.308743 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =138
7959 23:09:08.311916 DQ8 =108, DQ9 =106, DQ10 =122, DQ11 =112
7960 23:09:08.315187 DQ12 =126, DQ13 =128, DQ14 =132, DQ15 =130
7961 23:09:08.315752
7962 23:09:08.316120
7963 23:09:08.316456
7964 23:09:08.318628 [DramC_TX_OE_Calibration] TA2
7965 23:09:08.322201 Original DQ_B0 (3 6) =30, OEN = 27
7966 23:09:08.325129 Original DQ_B1 (3 6) =30, OEN = 27
7967 23:09:08.325593 24, 0x0, End_B0=24 End_B1=24
7968 23:09:08.328268 25, 0x0, End_B0=25 End_B1=25
7969 23:09:08.331589 26, 0x0, End_B0=26 End_B1=26
7970 23:09:08.335449 27, 0x0, End_B0=27 End_B1=27
7971 23:09:08.338429 28, 0x0, End_B0=28 End_B1=28
7972 23:09:08.339015 29, 0x0, End_B0=29 End_B1=29
7973 23:09:08.341376 30, 0x0, End_B0=30 End_B1=30
7974 23:09:08.345047 31, 0x4141, End_B0=30 End_B1=30
7975 23:09:08.348203 Byte0 end_step=30 best_step=27
7976 23:09:08.351774 Byte1 end_step=30 best_step=27
7977 23:09:08.354716 Byte0 TX OE(2T, 0.5T) = (3, 3)
7978 23:09:08.355257 Byte1 TX OE(2T, 0.5T) = (3, 3)
7979 23:09:08.358219
7980 23:09:08.358777
7981 23:09:08.364546 [DQSOSCAuto] RK1, (LSB)MR18= 0x2323, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
7982 23:09:08.368094 CH0 RK1: MR19=303, MR18=2323
7983 23:09:08.374552 CH0_RK1: MR19=0x303, MR18=0x2323, DQSOSC=392, MR23=63, INC=24, DEC=16
7984 23:09:08.378049 [RxdqsGatingPostProcess] freq 1600
7985 23:09:08.381060 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
7986 23:09:08.384711 Pre-setting of DQS Precalculation
7987 23:09:08.391262 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7988 23:09:08.391823 ==
7989 23:09:08.394411 Dram Type= 6, Freq= 0, CH_1, rank 0
7990 23:09:08.397580 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7991 23:09:08.398048 ==
7992 23:09:08.404433 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7993 23:09:08.407652 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
7994 23:09:08.411150 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
7995 23:09:08.417449 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7996 23:09:08.425719 [CA 0] Center 41 (11~71) winsize 61
7997 23:09:08.428987 [CA 1] Center 40 (10~70) winsize 61
7998 23:09:08.432386 [CA 2] Center 36 (7~66) winsize 60
7999 23:09:08.435604 [CA 3] Center 35 (6~65) winsize 60
8000 23:09:08.438712 [CA 4] Center 33 (3~63) winsize 61
8001 23:09:08.442169 [CA 5] Center 33 (4~63) winsize 60
8002 23:09:08.442633
8003 23:09:08.445526 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8004 23:09:08.446086
8005 23:09:08.449134 [CATrainingPosCal] consider 1 rank data
8006 23:09:08.452441 u2DelayCellTimex100 = 271/100 ps
8007 23:09:08.459010 CA0 delay=41 (11~71),Diff = 8 PI (28 cell)
8008 23:09:08.461880 CA1 delay=40 (10~70),Diff = 7 PI (25 cell)
8009 23:09:08.465462 CA2 delay=36 (7~66),Diff = 3 PI (10 cell)
8010 23:09:08.468681 CA3 delay=35 (6~65),Diff = 2 PI (7 cell)
8011 23:09:08.472130 CA4 delay=33 (3~63),Diff = 0 PI (0 cell)
8012 23:09:08.475210 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
8013 23:09:08.475672
8014 23:09:08.478724 CA PerBit enable=1, Macro0, CA PI delay=33
8015 23:09:08.479184
8016 23:09:08.482185 [CBTSetCACLKResult] CA Dly = 33
8017 23:09:08.485301 CS Dly: 8 (0~39)
8018 23:09:08.488836 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8019 23:09:08.491991 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8020 23:09:08.492567 ==
8021 23:09:08.495077 Dram Type= 6, Freq= 0, CH_1, rank 1
8022 23:09:08.498652 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8023 23:09:08.501702 ==
8024 23:09:08.504975 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8025 23:09:08.508202 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8026 23:09:08.515434 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8027 23:09:08.521907 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8028 23:09:08.528239 [CA 0] Center 41 (11~71) winsize 61
8029 23:09:08.531626 [CA 1] Center 41 (10~72) winsize 63
8030 23:09:08.534592 [CA 2] Center 36 (7~66) winsize 60
8031 23:09:08.538016 [CA 3] Center 36 (7~65) winsize 59
8032 23:09:08.541263 [CA 4] Center 34 (4~64) winsize 61
8033 23:09:08.544639 [CA 5] Center 34 (4~64) winsize 61
8034 23:09:08.545126
8035 23:09:08.548125 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8036 23:09:08.548731
8037 23:09:08.551413 [CATrainingPosCal] consider 2 rank data
8038 23:09:08.554513 u2DelayCellTimex100 = 271/100 ps
8039 23:09:08.558164 CA0 delay=41 (11~71),Diff = 8 PI (28 cell)
8040 23:09:08.564713 CA1 delay=40 (10~70),Diff = 7 PI (25 cell)
8041 23:09:08.568218 CA2 delay=36 (7~66),Diff = 3 PI (10 cell)
8042 23:09:08.571245 CA3 delay=36 (7~65),Diff = 3 PI (10 cell)
8043 23:09:08.574593 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
8044 23:09:08.577925 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
8045 23:09:08.578491
8046 23:09:08.581113 CA PerBit enable=1, Macro0, CA PI delay=33
8047 23:09:08.581577
8048 23:09:08.584881 [CBTSetCACLKResult] CA Dly = 33
8049 23:09:08.588170 CS Dly: 9 (0~41)
8050 23:09:08.591295 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8051 23:09:08.594783 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8052 23:09:08.595355
8053 23:09:08.598182 ----->DramcWriteLeveling(PI) begin...
8054 23:09:08.598792 ==
8055 23:09:08.600983 Dram Type= 6, Freq= 0, CH_1, rank 0
8056 23:09:08.607665 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8057 23:09:08.608229 ==
8058 23:09:08.611177 Write leveling (Byte 0): 22 => 22
8059 23:09:08.611638 Write leveling (Byte 1): 22 => 22
8060 23:09:08.614555 DramcWriteLeveling(PI) end<-----
8061 23:09:08.615242
8062 23:09:08.615619 ==
8063 23:09:08.617541 Dram Type= 6, Freq= 0, CH_1, rank 0
8064 23:09:08.624259 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8065 23:09:08.625011 ==
8066 23:09:08.627602 [Gating] SW mode calibration
8067 23:09:08.634201 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8068 23:09:08.637725 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8069 23:09:08.644302 0 12 0 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
8070 23:09:08.647743 0 12 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
8071 23:09:08.651024 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8072 23:09:08.657427 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8073 23:09:08.660954 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8074 23:09:08.664633 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8075 23:09:08.670730 0 12 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
8076 23:09:08.674158 0 12 28 | B1->B0 | 3434 2626 | 1 0 | (1 0) (1 0)
8077 23:09:08.677762 0 13 0 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
8078 23:09:08.684167 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8079 23:09:08.687044 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8080 23:09:08.690452 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8081 23:09:08.697275 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8082 23:09:08.700387 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8083 23:09:08.703814 0 13 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8084 23:09:08.710405 0 13 28 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
8085 23:09:08.713757 0 14 0 | B1->B0 | 2e2e 4646 | 0 0 | (0 0) (0 0)
8086 23:09:08.717140 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8087 23:09:08.723695 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8088 23:09:08.726699 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8089 23:09:08.730415 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8090 23:09:08.733641 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8091 23:09:08.740217 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8092 23:09:08.743324 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8093 23:09:08.747327 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8094 23:09:08.753350 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8095 23:09:08.756885 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8096 23:09:08.760384 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8097 23:09:08.766774 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8098 23:09:08.770051 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8099 23:09:08.773555 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8100 23:09:08.780024 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8101 23:09:08.783282 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8102 23:09:08.786315 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8103 23:09:08.792896 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8104 23:09:08.796467 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8105 23:09:08.800269 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8106 23:09:08.806860 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8107 23:09:08.809743 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8108 23:09:08.812955 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8109 23:09:08.819694 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8110 23:09:08.823003 Total UI for P1: 0, mck2ui 16
8111 23:09:08.826369 best dqsien dly found for B0: ( 1, 0, 26)
8112 23:09:08.829490 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8113 23:09:08.832712 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8114 23:09:08.836689 Total UI for P1: 0, mck2ui 16
8115 23:09:08.839665 best dqsien dly found for B1: ( 1, 1, 2)
8116 23:09:08.842781 best DQS0 dly(MCK, UI, PI) = (1, 0, 26)
8117 23:09:08.846064 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
8118 23:09:08.846532
8119 23:09:08.852679 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 26)
8120 23:09:08.855829 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
8121 23:09:08.859241 [Gating] SW calibration Done
8122 23:09:08.859806 ==
8123 23:09:08.862936 Dram Type= 6, Freq= 0, CH_1, rank 0
8124 23:09:08.866034 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8125 23:09:08.866605 ==
8126 23:09:08.866977 RX Vref Scan: 0
8127 23:09:08.867321
8128 23:09:08.869062 RX Vref 0 -> 0, step: 1
8129 23:09:08.869551
8130 23:09:08.872318 RX Delay 0 -> 252, step: 8
8131 23:09:08.875545 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8132 23:09:08.878871 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8133 23:09:08.885967 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8134 23:09:08.888998 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8135 23:09:08.892554 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8136 23:09:08.895717 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8137 23:09:08.898810 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8138 23:09:08.902112 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8139 23:09:08.908904 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8140 23:09:08.912378 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8141 23:09:08.915432 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8142 23:09:08.918935 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8143 23:09:08.925999 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8144 23:09:08.928805 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8145 23:09:08.932137 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8146 23:09:08.935405 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8147 23:09:08.935965 ==
8148 23:09:08.938528 Dram Type= 6, Freq= 0, CH_1, rank 0
8149 23:09:08.944933 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8150 23:09:08.945395 ==
8151 23:09:08.945760 DQS Delay:
8152 23:09:08.949026 DQS0 = 0, DQS1 = 0
8153 23:09:08.949584 DQM Delay:
8154 23:09:08.949949 DQM0 = 131, DQM1 = 126
8155 23:09:08.951688 DQ Delay:
8156 23:09:08.954845 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =127
8157 23:09:08.958515 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =127
8158 23:09:08.961687 DQ8 =107, DQ9 =115, DQ10 =127, DQ11 =115
8159 23:09:08.965183 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =135
8160 23:09:08.965747
8161 23:09:08.966116
8162 23:09:08.966456 ==
8163 23:09:08.968254 Dram Type= 6, Freq= 0, CH_1, rank 0
8164 23:09:08.971495 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8165 23:09:08.975210 ==
8166 23:09:08.975781
8167 23:09:08.976152
8168 23:09:08.976497 TX Vref Scan disable
8169 23:09:08.978330 == TX Byte 0 ==
8170 23:09:08.981794 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8171 23:09:08.984667 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8172 23:09:08.987995 == TX Byte 1 ==
8173 23:09:08.991313 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8174 23:09:08.998028 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8175 23:09:08.998672 ==
8176 23:09:09.001068 Dram Type= 6, Freq= 0, CH_1, rank 0
8177 23:09:09.004628 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8178 23:09:09.005114 ==
8179 23:09:09.017446
8180 23:09:09.020760 TX Vref early break, caculate TX vref
8181 23:09:09.024420 TX Vref=16, minBit 3, minWin=21, winSum=365
8182 23:09:09.027823 TX Vref=18, minBit 1, minWin=22, winSum=376
8183 23:09:09.030663 TX Vref=20, minBit 1, minWin=23, winSum=385
8184 23:09:09.034158 TX Vref=22, minBit 3, minWin=23, winSum=394
8185 23:09:09.037727 TX Vref=24, minBit 1, minWin=24, winSum=404
8186 23:09:09.044320 TX Vref=26, minBit 0, minWin=24, winSum=406
8187 23:09:09.047286 TX Vref=28, minBit 3, minWin=23, winSum=407
8188 23:09:09.050858 TX Vref=30, minBit 3, minWin=23, winSum=405
8189 23:09:09.054216 TX Vref=32, minBit 3, minWin=23, winSum=397
8190 23:09:09.057203 TX Vref=34, minBit 0, minWin=23, winSum=386
8191 23:09:09.060784 TX Vref=36, minBit 3, minWin=21, winSum=379
8192 23:09:09.067344 [TxChooseVref] Worse bit 0, Min win 24, Win sum 406, Final Vref 26
8193 23:09:09.067916
8194 23:09:09.070343 Final TX Range 0 Vref 26
8195 23:09:09.070913
8196 23:09:09.071285 ==
8197 23:09:09.073740 Dram Type= 6, Freq= 0, CH_1, rank 0
8198 23:09:09.077115 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8199 23:09:09.077683 ==
8200 23:09:09.078056
8201 23:09:09.080245
8202 23:09:09.080868 TX Vref Scan disable
8203 23:09:09.086973 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8204 23:09:09.087546 == TX Byte 0 ==
8205 23:09:09.090225 u2DelayCellOfst[0]=18 cells (5 PI)
8206 23:09:09.093661 u2DelayCellOfst[1]=14 cells (4 PI)
8207 23:09:09.096858 u2DelayCellOfst[2]=0 cells (0 PI)
8208 23:09:09.100351 u2DelayCellOfst[3]=7 cells (2 PI)
8209 23:09:09.103424 u2DelayCellOfst[4]=10 cells (3 PI)
8210 23:09:09.107046 u2DelayCellOfst[5]=18 cells (5 PI)
8211 23:09:09.110149 u2DelayCellOfst[6]=18 cells (5 PI)
8212 23:09:09.113659 u2DelayCellOfst[7]=7 cells (2 PI)
8213 23:09:09.116761 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8214 23:09:09.120048 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8215 23:09:09.123571 == TX Byte 1 ==
8216 23:09:09.126888 u2DelayCellOfst[8]=0 cells (0 PI)
8217 23:09:09.130301 u2DelayCellOfst[9]=7 cells (2 PI)
8218 23:09:09.130770 u2DelayCellOfst[10]=10 cells (3 PI)
8219 23:09:09.133197 u2DelayCellOfst[11]=3 cells (1 PI)
8220 23:09:09.136673 u2DelayCellOfst[12]=14 cells (4 PI)
8221 23:09:09.140051 u2DelayCellOfst[13]=21 cells (6 PI)
8222 23:09:09.143476 u2DelayCellOfst[14]=21 cells (6 PI)
8223 23:09:09.146229 u2DelayCellOfst[15]=18 cells (5 PI)
8224 23:09:09.153337 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8225 23:09:09.156422 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8226 23:09:09.157039 DramC Write-DBI on
8227 23:09:09.157415 ==
8228 23:09:09.159786 Dram Type= 6, Freq= 0, CH_1, rank 0
8229 23:09:09.166444 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8230 23:09:09.167004 ==
8231 23:09:09.167381
8232 23:09:09.167727
8233 23:09:09.169660 TX Vref Scan disable
8234 23:09:09.170126 == TX Byte 0 ==
8235 23:09:09.173049 Update DQM dly =718 (2 ,6, 14) DQM OEN =(3 ,3)
8236 23:09:09.176318 == TX Byte 1 ==
8237 23:09:09.179539 Update DQM dly =717 (2 ,6, 13) DQM OEN =(3 ,3)
8238 23:09:09.182913 DramC Write-DBI off
8239 23:09:09.183479
8240 23:09:09.183851 [DATLAT]
8241 23:09:09.186086 Freq=1600, CH1 RK0
8242 23:09:09.186555
8243 23:09:09.186923 DATLAT Default: 0xf
8244 23:09:09.189946 0, 0xFFFF, sum = 0
8245 23:09:09.190515 1, 0xFFFF, sum = 0
8246 23:09:09.193124 2, 0xFFFF, sum = 0
8247 23:09:09.193690 3, 0xFFFF, sum = 0
8248 23:09:09.196273 4, 0xFFFF, sum = 0
8249 23:09:09.196890 5, 0xFFFF, sum = 0
8250 23:09:09.199427 6, 0xFFFF, sum = 0
8251 23:09:09.199993 7, 0xFFFF, sum = 0
8252 23:09:09.202510 8, 0xFFFF, sum = 0
8253 23:09:09.202984 9, 0xFFFF, sum = 0
8254 23:09:09.206371 10, 0xFFFF, sum = 0
8255 23:09:09.209174 11, 0xFFFF, sum = 0
8256 23:09:09.209739 12, 0x8F7F, sum = 0
8257 23:09:09.212396 13, 0x0, sum = 1
8258 23:09:09.212924 14, 0x0, sum = 2
8259 23:09:09.213307 15, 0x0, sum = 3
8260 23:09:09.215752 16, 0x0, sum = 4
8261 23:09:09.216227 best_step = 14
8262 23:09:09.216643
8263 23:09:09.219371 ==
8264 23:09:09.222853 Dram Type= 6, Freq= 0, CH_1, rank 0
8265 23:09:09.225829 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8266 23:09:09.226395 ==
8267 23:09:09.226771 RX Vref Scan: 1
8268 23:09:09.227119
8269 23:09:09.228928 Set Vref Range= 24 -> 127
8270 23:09:09.229393
8271 23:09:09.232166 RX Vref 24 -> 127, step: 1
8272 23:09:09.232823
8273 23:09:09.235586 RX Delay 3 -> 252, step: 4
8274 23:09:09.236048
8275 23:09:09.239039 Set Vref, RX VrefLevel [Byte0]: 24
8276 23:09:09.242145 [Byte1]: 24
8277 23:09:09.242613
8278 23:09:09.245658 Set Vref, RX VrefLevel [Byte0]: 25
8279 23:09:09.248990 [Byte1]: 25
8280 23:09:09.249551
8281 23:09:09.252282 Set Vref, RX VrefLevel [Byte0]: 26
8282 23:09:09.255575 [Byte1]: 26
8283 23:09:09.258960
8284 23:09:09.259439 Set Vref, RX VrefLevel [Byte0]: 27
8285 23:09:09.262584 [Byte1]: 27
8286 23:09:09.267016
8287 23:09:09.267576 Set Vref, RX VrefLevel [Byte0]: 28
8288 23:09:09.270331 [Byte1]: 28
8289 23:09:09.274938
8290 23:09:09.275494 Set Vref, RX VrefLevel [Byte0]: 29
8291 23:09:09.277628 [Byte1]: 29
8292 23:09:09.282217
8293 23:09:09.282678 Set Vref, RX VrefLevel [Byte0]: 30
8294 23:09:09.285479 [Byte1]: 30
8295 23:09:09.289639
8296 23:09:09.290096 Set Vref, RX VrefLevel [Byte0]: 31
8297 23:09:09.293110 [Byte1]: 31
8298 23:09:09.297127
8299 23:09:09.297587 Set Vref, RX VrefLevel [Byte0]: 32
8300 23:09:09.300407 [Byte1]: 32
8301 23:09:09.305068
8302 23:09:09.305602 Set Vref, RX VrefLevel [Byte0]: 33
8303 23:09:09.307998 [Byte1]: 33
8304 23:09:09.312706
8305 23:09:09.313169 Set Vref, RX VrefLevel [Byte0]: 34
8306 23:09:09.315913 [Byte1]: 34
8307 23:09:09.320285
8308 23:09:09.320917 Set Vref, RX VrefLevel [Byte0]: 35
8309 23:09:09.323389 [Byte1]: 35
8310 23:09:09.327753
8311 23:09:09.328215 Set Vref, RX VrefLevel [Byte0]: 36
8312 23:09:09.331376 [Byte1]: 36
8313 23:09:09.335577
8314 23:09:09.336036 Set Vref, RX VrefLevel [Byte0]: 37
8315 23:09:09.339082 [Byte1]: 37
8316 23:09:09.343433
8317 23:09:09.343893 Set Vref, RX VrefLevel [Byte0]: 38
8318 23:09:09.346696 [Byte1]: 38
8319 23:09:09.351133
8320 23:09:09.351690 Set Vref, RX VrefLevel [Byte0]: 39
8321 23:09:09.354707 [Byte1]: 39
8322 23:09:09.358767
8323 23:09:09.359322 Set Vref, RX VrefLevel [Byte0]: 40
8324 23:09:09.362033 [Byte1]: 40
8325 23:09:09.366212
8326 23:09:09.366760 Set Vref, RX VrefLevel [Byte0]: 41
8327 23:09:09.369932 [Byte1]: 41
8328 23:09:09.374496
8329 23:09:09.375067 Set Vref, RX VrefLevel [Byte0]: 42
8330 23:09:09.377212 [Byte1]: 42
8331 23:09:09.381584
8332 23:09:09.382135 Set Vref, RX VrefLevel [Byte0]: 43
8333 23:09:09.384777 [Byte1]: 43
8334 23:09:09.389527
8335 23:09:09.390090 Set Vref, RX VrefLevel [Byte0]: 44
8336 23:09:09.392490 [Byte1]: 44
8337 23:09:09.396922
8338 23:09:09.397477 Set Vref, RX VrefLevel [Byte0]: 45
8339 23:09:09.400367 [Byte1]: 45
8340 23:09:09.404549
8341 23:09:09.405015 Set Vref, RX VrefLevel [Byte0]: 46
8342 23:09:09.408210 [Byte1]: 46
8343 23:09:09.412088
8344 23:09:09.412690 Set Vref, RX VrefLevel [Byte0]: 47
8345 23:09:09.415599 [Byte1]: 47
8346 23:09:09.420044
8347 23:09:09.420646 Set Vref, RX VrefLevel [Byte0]: 48
8348 23:09:09.423630 [Byte1]: 48
8349 23:09:09.427707
8350 23:09:09.428261 Set Vref, RX VrefLevel [Byte0]: 49
8351 23:09:09.430528 [Byte1]: 49
8352 23:09:09.434900
8353 23:09:09.435358 Set Vref, RX VrefLevel [Byte0]: 50
8354 23:09:09.438553 [Byte1]: 50
8355 23:09:09.442535
8356 23:09:09.442997 Set Vref, RX VrefLevel [Byte0]: 51
8357 23:09:09.446119 [Byte1]: 51
8358 23:09:09.450336
8359 23:09:09.450890 Set Vref, RX VrefLevel [Byte0]: 52
8360 23:09:09.456772 [Byte1]: 52
8361 23:09:09.457357
8362 23:09:09.459911 Set Vref, RX VrefLevel [Byte0]: 53
8363 23:09:09.463751 [Byte1]: 53
8364 23:09:09.464303
8365 23:09:09.466455 Set Vref, RX VrefLevel [Byte0]: 54
8366 23:09:09.470005 [Byte1]: 54
8367 23:09:09.473318
8368 23:09:09.473780 Set Vref, RX VrefLevel [Byte0]: 55
8369 23:09:09.476795 [Byte1]: 55
8370 23:09:09.481393
8371 23:09:09.481946 Set Vref, RX VrefLevel [Byte0]: 56
8372 23:09:09.484466 [Byte1]: 56
8373 23:09:09.488731
8374 23:09:09.489286 Set Vref, RX VrefLevel [Byte0]: 57
8375 23:09:09.492019 [Byte1]: 57
8376 23:09:09.496388
8377 23:09:09.496988 Set Vref, RX VrefLevel [Byte0]: 58
8378 23:09:09.499573 [Byte1]: 58
8379 23:09:09.503961
8380 23:09:09.504546 Set Vref, RX VrefLevel [Byte0]: 59
8381 23:09:09.507181 [Byte1]: 59
8382 23:09:09.511717
8383 23:09:09.512266 Set Vref, RX VrefLevel [Byte0]: 60
8384 23:09:09.514903 [Byte1]: 60
8385 23:09:09.519702
8386 23:09:09.520258 Set Vref, RX VrefLevel [Byte0]: 61
8387 23:09:09.522828 [Byte1]: 61
8388 23:09:09.527040
8389 23:09:09.527591 Set Vref, RX VrefLevel [Byte0]: 62
8390 23:09:09.529993 [Byte1]: 62
8391 23:09:09.534384
8392 23:09:09.534882 Set Vref, RX VrefLevel [Byte0]: 63
8393 23:09:09.538158 [Byte1]: 63
8394 23:09:09.542324
8395 23:09:09.542982 Set Vref, RX VrefLevel [Byte0]: 64
8396 23:09:09.545611 [Byte1]: 64
8397 23:09:09.550086
8398 23:09:09.550642 Set Vref, RX VrefLevel [Byte0]: 65
8399 23:09:09.553140 [Byte1]: 65
8400 23:09:09.557530
8401 23:09:09.557989 Set Vref, RX VrefLevel [Byte0]: 66
8402 23:09:09.560805 [Byte1]: 66
8403 23:09:09.565442
8404 23:09:09.565998 Set Vref, RX VrefLevel [Byte0]: 67
8405 23:09:09.568309 [Byte1]: 67
8406 23:09:09.572775
8407 23:09:09.573327 Set Vref, RX VrefLevel [Byte0]: 68
8408 23:09:09.576252 [Byte1]: 68
8409 23:09:09.580604
8410 23:09:09.581157 Set Vref, RX VrefLevel [Byte0]: 69
8411 23:09:09.583934 [Byte1]: 69
8412 23:09:09.588163
8413 23:09:09.588812 Set Vref, RX VrefLevel [Byte0]: 70
8414 23:09:09.591141 [Byte1]: 70
8415 23:09:09.595841
8416 23:09:09.596395 Set Vref, RX VrefLevel [Byte0]: 71
8417 23:09:09.599555 [Byte1]: 71
8418 23:09:09.603669
8419 23:09:09.604225 Set Vref, RX VrefLevel [Byte0]: 72
8420 23:09:09.606603 [Byte1]: 72
8421 23:09:09.611408
8422 23:09:09.611967 Set Vref, RX VrefLevel [Byte0]: 73
8423 23:09:09.614645 [Byte1]: 73
8424 23:09:09.618411
8425 23:09:09.618873 Set Vref, RX VrefLevel [Byte0]: 74
8426 23:09:09.622315 [Byte1]: 74
8427 23:09:09.626348
8428 23:09:09.626906 Set Vref, RX VrefLevel [Byte0]: 75
8429 23:09:09.629772 [Byte1]: 75
8430 23:09:09.633936
8431 23:09:09.634404 Final RX Vref Byte 0 = 61 to rank0
8432 23:09:09.637315 Final RX Vref Byte 1 = 54 to rank0
8433 23:09:09.640927 Final RX Vref Byte 0 = 61 to rank1
8434 23:09:09.643772 Final RX Vref Byte 1 = 54 to rank1==
8435 23:09:09.647216 Dram Type= 6, Freq= 0, CH_1, rank 0
8436 23:09:09.654334 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8437 23:09:09.654909 ==
8438 23:09:09.655285 DQS Delay:
8439 23:09:09.655628 DQS0 = 0, DQS1 = 0
8440 23:09:09.657117 DQM Delay:
8441 23:09:09.657582 DQM0 = 129, DQM1 = 123
8442 23:09:09.660670 DQ Delay:
8443 23:09:09.663890 DQ0 =132, DQ1 =124, DQ2 =116, DQ3 =126
8444 23:09:09.667189 DQ4 =130, DQ5 =140, DQ6 =138, DQ7 =126
8445 23:09:09.670889 DQ8 =104, DQ9 =114, DQ10 =124, DQ11 =114
8446 23:09:09.673734 DQ12 =130, DQ13 =134, DQ14 =132, DQ15 =132
8447 23:09:09.674294
8448 23:09:09.674666
8449 23:09:09.675007
8450 23:09:09.676835 [DramC_TX_OE_Calibration] TA2
8451 23:09:09.680819 Original DQ_B0 (3 6) =30, OEN = 27
8452 23:09:09.683566 Original DQ_B1 (3 6) =30, OEN = 27
8453 23:09:09.687306 24, 0x0, End_B0=24 End_B1=24
8454 23:09:09.687871 25, 0x0, End_B0=25 End_B1=25
8455 23:09:09.690067 26, 0x0, End_B0=26 End_B1=26
8456 23:09:09.693833 27, 0x0, End_B0=27 End_B1=27
8457 23:09:09.696957 28, 0x0, End_B0=28 End_B1=28
8458 23:09:09.700473 29, 0x0, End_B0=29 End_B1=29
8459 23:09:09.701138 30, 0x0, End_B0=30 End_B1=30
8460 23:09:09.703544 31, 0x4545, End_B0=30 End_B1=30
8461 23:09:09.706749 Byte0 end_step=30 best_step=27
8462 23:09:09.710289 Byte1 end_step=30 best_step=27
8463 23:09:09.713504 Byte0 TX OE(2T, 0.5T) = (3, 3)
8464 23:09:09.716736 Byte1 TX OE(2T, 0.5T) = (3, 3)
8465 23:09:09.717235
8466 23:09:09.717600
8467 23:09:09.723374 [DQSOSCAuto] RK0, (LSB)MR18= 0x2828, (MSB)MR19= 0x303, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
8468 23:09:09.726784 CH1 RK0: MR19=303, MR18=2828
8469 23:09:09.733090 CH1_RK0: MR19=0x303, MR18=0x2828, DQSOSC=389, MR23=63, INC=24, DEC=16
8470 23:09:09.733635
8471 23:09:09.736814 ----->DramcWriteLeveling(PI) begin...
8472 23:09:09.737383 ==
8473 23:09:09.740193 Dram Type= 6, Freq= 0, CH_1, rank 1
8474 23:09:09.742950 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8475 23:09:09.743511 ==
8476 23:09:09.746290 Write leveling (Byte 0): 23 => 23
8477 23:09:09.750059 Write leveling (Byte 1): 20 => 20
8478 23:09:09.753155 DramcWriteLeveling(PI) end<-----
8479 23:09:09.753715
8480 23:09:09.754086 ==
8481 23:09:09.756577 Dram Type= 6, Freq= 0, CH_1, rank 1
8482 23:09:09.759813 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8483 23:09:09.760372 ==
8484 23:09:09.762872 [Gating] SW mode calibration
8485 23:09:09.769738 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8486 23:09:09.776341 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8487 23:09:09.779739 0 12 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8488 23:09:09.786317 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8489 23:09:09.789475 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8490 23:09:09.793250 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8491 23:09:09.799712 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8492 23:09:09.802816 0 12 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8493 23:09:09.805864 0 12 24 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 1)
8494 23:09:09.812845 0 12 28 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
8495 23:09:09.816292 0 13 0 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
8496 23:09:09.819447 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8497 23:09:09.826106 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8498 23:09:09.829315 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8499 23:09:09.832418 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8500 23:09:09.838943 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8501 23:09:09.842627 0 13 24 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
8502 23:09:09.845728 0 13 28 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
8503 23:09:09.852621 0 14 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8504 23:09:09.855782 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8505 23:09:09.859121 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8506 23:09:09.865548 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8507 23:09:09.868876 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8508 23:09:09.872494 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8509 23:09:09.875902 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8510 23:09:09.882282 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8511 23:09:09.885475 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8512 23:09:09.892292 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8513 23:09:09.895308 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8514 23:09:09.898647 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8515 23:09:09.902332 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8516 23:09:09.908637 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8517 23:09:09.911853 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8518 23:09:09.915513 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8519 23:09:09.921837 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8520 23:09:09.925255 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8521 23:09:09.928600 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8522 23:09:09.935068 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8523 23:09:09.938127 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8524 23:09:09.941817 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8525 23:09:09.948171 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8526 23:09:09.951568 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8527 23:09:09.954863 Total UI for P1: 0, mck2ui 16
8528 23:09:09.958057 best dqsien dly found for B0: ( 1, 0, 24)
8529 23:09:09.961624 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8530 23:09:09.968551 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8531 23:09:09.971458 Total UI for P1: 0, mck2ui 16
8532 23:09:09.974794 best dqsien dly found for B1: ( 1, 0, 28)
8533 23:09:09.978194 best DQS0 dly(MCK, UI, PI) = (1, 0, 24)
8534 23:09:09.981481 best DQS1 dly(MCK, UI, PI) = (1, 0, 28)
8535 23:09:09.982039
8536 23:09:09.984988 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 24)
8537 23:09:09.988279 best DQS1 P1 dly(MCK, UI, PI) = (1, 4, 28)
8538 23:09:09.991252 [Gating] SW calibration Done
8539 23:09:09.991813 ==
8540 23:09:09.994556 Dram Type= 6, Freq= 0, CH_1, rank 1
8541 23:09:09.997968 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8542 23:09:09.998533 ==
8543 23:09:10.001261 RX Vref Scan: 0
8544 23:09:10.001817
8545 23:09:10.002184 RX Vref 0 -> 0, step: 1
8546 23:09:10.004537
8547 23:09:10.005091 RX Delay 0 -> 252, step: 8
8548 23:09:10.007877 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8549 23:09:10.014461 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120
8550 23:09:10.017899 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8551 23:09:10.021193 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8552 23:09:10.024612 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8553 23:09:10.027856 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8554 23:09:10.034392 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8555 23:09:10.037597 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8556 23:09:10.041089 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8557 23:09:10.044202 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8558 23:09:10.050903 iDelay=200, Bit 10, Center 127 (64 ~ 191) 128
8559 23:09:10.054475 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8560 23:09:10.057229 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8561 23:09:10.060657 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8562 23:09:10.064135 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8563 23:09:10.070784 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8564 23:09:10.071343 ==
8565 23:09:10.073939 Dram Type= 6, Freq= 0, CH_1, rank 1
8566 23:09:10.077380 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8567 23:09:10.077944 ==
8568 23:09:10.078312 DQS Delay:
8569 23:09:10.080668 DQS0 = 0, DQS1 = 0
8570 23:09:10.081224 DQM Delay:
8571 23:09:10.083992 DQM0 = 130, DQM1 = 125
8572 23:09:10.084602 DQ Delay:
8573 23:09:10.087262 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =127
8574 23:09:10.090545 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =127
8575 23:09:10.093601 DQ8 =107, DQ9 =115, DQ10 =127, DQ11 =115
8576 23:09:10.097424 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =131
8577 23:09:10.097988
8578 23:09:10.100748
8579 23:09:10.101295 ==
8580 23:09:10.104208 Dram Type= 6, Freq= 0, CH_1, rank 1
8581 23:09:10.107185 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8582 23:09:10.107768 ==
8583 23:09:10.108374
8584 23:09:10.108851
8585 23:09:10.110467 TX Vref Scan disable
8586 23:09:10.111123 == TX Byte 0 ==
8587 23:09:10.117264 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8588 23:09:10.120194 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8589 23:09:10.120788 == TX Byte 1 ==
8590 23:09:10.126901 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8591 23:09:10.129912 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8592 23:09:10.130375 ==
8593 23:09:10.133629 Dram Type= 6, Freq= 0, CH_1, rank 1
8594 23:09:10.136692 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8595 23:09:10.137155 ==
8596 23:09:10.150447
8597 23:09:10.153444 TX Vref early break, caculate TX vref
8598 23:09:10.157480 TX Vref=16, minBit 5, minWin=21, winSum=379
8599 23:09:10.160209 TX Vref=18, minBit 0, minWin=23, winSum=391
8600 23:09:10.163548 TX Vref=20, minBit 0, minWin=22, winSum=393
8601 23:09:10.166735 TX Vref=22, minBit 0, minWin=24, winSum=407
8602 23:09:10.169982 TX Vref=24, minBit 0, minWin=24, winSum=415
8603 23:09:10.177045 TX Vref=26, minBit 0, minWin=25, winSum=420
8604 23:09:10.180013 TX Vref=28, minBit 0, minWin=23, winSum=417
8605 23:09:10.183544 TX Vref=30, minBit 0, minWin=24, winSum=415
8606 23:09:10.186845 TX Vref=32, minBit 0, minWin=24, winSum=407
8607 23:09:10.189721 TX Vref=34, minBit 0, minWin=23, winSum=398
8608 23:09:10.196825 [TxChooseVref] Worse bit 0, Min win 25, Win sum 420, Final Vref 26
8609 23:09:10.197402
8610 23:09:10.199989 Final TX Range 0 Vref 26
8611 23:09:10.200590
8612 23:09:10.201086 ==
8613 23:09:10.203593 Dram Type= 6, Freq= 0, CH_1, rank 1
8614 23:09:10.206561 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8615 23:09:10.207136 ==
8616 23:09:10.207631
8617 23:09:10.208094
8618 23:09:10.209713 TX Vref Scan disable
8619 23:09:10.216606 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8620 23:09:10.217159 == TX Byte 0 ==
8621 23:09:10.219811 u2DelayCellOfst[0]=18 cells (5 PI)
8622 23:09:10.223251 u2DelayCellOfst[1]=10 cells (3 PI)
8623 23:09:10.226587 u2DelayCellOfst[2]=0 cells (0 PI)
8624 23:09:10.229777 u2DelayCellOfst[3]=10 cells (3 PI)
8625 23:09:10.232847 u2DelayCellOfst[4]=10 cells (3 PI)
8626 23:09:10.236284 u2DelayCellOfst[5]=21 cells (6 PI)
8627 23:09:10.239616 u2DelayCellOfst[6]=18 cells (5 PI)
8628 23:09:10.243107 u2DelayCellOfst[7]=7 cells (2 PI)
8629 23:09:10.246375 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8630 23:09:10.249598 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8631 23:09:10.252961 == TX Byte 1 ==
8632 23:09:10.253520 u2DelayCellOfst[8]=0 cells (0 PI)
8633 23:09:10.256557 u2DelayCellOfst[9]=3 cells (1 PI)
8634 23:09:10.259656 u2DelayCellOfst[10]=10 cells (3 PI)
8635 23:09:10.262900 u2DelayCellOfst[11]=3 cells (1 PI)
8636 23:09:10.265942 u2DelayCellOfst[12]=14 cells (4 PI)
8637 23:09:10.269488 u2DelayCellOfst[13]=18 cells (5 PI)
8638 23:09:10.272699 u2DelayCellOfst[14]=18 cells (5 PI)
8639 23:09:10.275943 u2DelayCellOfst[15]=14 cells (4 PI)
8640 23:09:10.279288 Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3)
8641 23:09:10.285823 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8642 23:09:10.286392 DramC Write-DBI on
8643 23:09:10.286763 ==
8644 23:09:10.289329 Dram Type= 6, Freq= 0, CH_1, rank 1
8645 23:09:10.295513 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8646 23:09:10.296061 ==
8647 23:09:10.296429
8648 23:09:10.296807
8649 23:09:10.297134 TX Vref Scan disable
8650 23:09:10.299806 == TX Byte 0 ==
8651 23:09:10.303075 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
8652 23:09:10.306377 == TX Byte 1 ==
8653 23:09:10.309493 Update DQM dly =715 (2 ,6, 11) DQM OEN =(3 ,3)
8654 23:09:10.312851 DramC Write-DBI off
8655 23:09:10.313309
8656 23:09:10.313672 [DATLAT]
8657 23:09:10.314010 Freq=1600, CH1 RK1
8658 23:09:10.314343
8659 23:09:10.316050 DATLAT Default: 0xe
8660 23:09:10.316541 0, 0xFFFF, sum = 0
8661 23:09:10.319470 1, 0xFFFF, sum = 0
8662 23:09:10.322790 2, 0xFFFF, sum = 0
8663 23:09:10.323370 3, 0xFFFF, sum = 0
8664 23:09:10.326299 4, 0xFFFF, sum = 0
8665 23:09:10.326871 5, 0xFFFF, sum = 0
8666 23:09:10.329040 6, 0xFFFF, sum = 0
8667 23:09:10.329511 7, 0xFFFF, sum = 0
8668 23:09:10.332564 8, 0xFFFF, sum = 0
8669 23:09:10.333091 9, 0xFFFF, sum = 0
8670 23:09:10.335726 10, 0xFFFF, sum = 0
8671 23:09:10.336386 11, 0xFFFF, sum = 0
8672 23:09:10.339197 12, 0xF7F, sum = 0
8673 23:09:10.339668 13, 0x0, sum = 1
8674 23:09:10.342498 14, 0x0, sum = 2
8675 23:09:10.342974 15, 0x0, sum = 3
8676 23:09:10.345734 16, 0x0, sum = 4
8677 23:09:10.346209 best_step = 14
8678 23:09:10.346585
8679 23:09:10.346933 ==
8680 23:09:10.349023 Dram Type= 6, Freq= 0, CH_1, rank 1
8681 23:09:10.352640 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8682 23:09:10.355794 ==
8683 23:09:10.356365 RX Vref Scan: 0
8684 23:09:10.356782
8685 23:09:10.359071 RX Vref 0 -> 0, step: 1
8686 23:09:10.359641
8687 23:09:10.362724 RX Delay 3 -> 252, step: 4
8688 23:09:10.365502 iDelay=195, Bit 0, Center 128 (75 ~ 182) 108
8689 23:09:10.369055 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
8690 23:09:10.372279 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
8691 23:09:10.379079 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8692 23:09:10.382360 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8693 23:09:10.385762 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8694 23:09:10.389246 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
8695 23:09:10.392265 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8696 23:09:10.398910 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
8697 23:09:10.402253 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8698 23:09:10.405318 iDelay=195, Bit 10, Center 124 (67 ~ 182) 116
8699 23:09:10.408671 iDelay=195, Bit 11, Center 112 (55 ~ 170) 116
8700 23:09:10.411797 iDelay=195, Bit 12, Center 130 (71 ~ 190) 120
8701 23:09:10.418823 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8702 23:09:10.422276 iDelay=195, Bit 14, Center 132 (75 ~ 190) 116
8703 23:09:10.425063 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8704 23:09:10.425526 ==
8705 23:09:10.429165 Dram Type= 6, Freq= 0, CH_1, rank 1
8706 23:09:10.432019 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8707 23:09:10.432770 ==
8708 23:09:10.434834 DQS Delay:
8709 23:09:10.435310 DQS0 = 0, DQS1 = 0
8710 23:09:10.438993 DQM Delay:
8711 23:09:10.439568 DQM0 = 127, DQM1 = 122
8712 23:09:10.441665 DQ Delay:
8713 23:09:10.445170 DQ0 =128, DQ1 =124, DQ2 =116, DQ3 =124
8714 23:09:10.448354 DQ4 =126, DQ5 =138, DQ6 =136, DQ7 =126
8715 23:09:10.451638 DQ8 =106, DQ9 =110, DQ10 =124, DQ11 =112
8716 23:09:10.455171 DQ12 =130, DQ13 =132, DQ14 =132, DQ15 =132
8717 23:09:10.455748
8718 23:09:10.456244
8719 23:09:10.456798
8720 23:09:10.458320 [DramC_TX_OE_Calibration] TA2
8721 23:09:10.461440 Original DQ_B0 (3 6) =30, OEN = 27
8722 23:09:10.465013 Original DQ_B1 (3 6) =30, OEN = 27
8723 23:09:10.465479 24, 0x0, End_B0=24 End_B1=24
8724 23:09:10.468277 25, 0x0, End_B0=25 End_B1=25
8725 23:09:10.471717 26, 0x0, End_B0=26 End_B1=26
8726 23:09:10.474817 27, 0x0, End_B0=27 End_B1=27
8727 23:09:10.478482 28, 0x0, End_B0=28 End_B1=28
8728 23:09:10.479050 29, 0x0, End_B0=29 End_B1=29
8729 23:09:10.481446 30, 0x0, End_B0=30 End_B1=30
8730 23:09:10.485036 31, 0x4141, End_B0=30 End_B1=30
8731 23:09:10.488062 Byte0 end_step=30 best_step=27
8732 23:09:10.491377 Byte1 end_step=30 best_step=27
8733 23:09:10.494765 Byte0 TX OE(2T, 0.5T) = (3, 3)
8734 23:09:10.495325 Byte1 TX OE(2T, 0.5T) = (3, 3)
8735 23:09:10.495701
8736 23:09:10.498360
8737 23:09:10.504956 [DQSOSCAuto] RK1, (LSB)MR18= 0x1a1a, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
8738 23:09:10.507931 CH1 RK1: MR19=303, MR18=1A1A
8739 23:09:10.514706 CH1_RK1: MR19=0x303, MR18=0x1A1A, DQSOSC=396, MR23=63, INC=23, DEC=15
8740 23:09:10.518254 [RxdqsGatingPostProcess] freq 1600
8741 23:09:10.521074 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8742 23:09:10.524658 Pre-setting of DQS Precalculation
8743 23:09:10.531243 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8744 23:09:10.537951 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8745 23:09:10.544702 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8746 23:09:10.545265
8747 23:09:10.545633
8748 23:09:10.547763 [Calibration Summary] 3200 Mbps
8749 23:09:10.548321 CH 0, Rank 0
8750 23:09:10.551039 SW Impedance : PASS
8751 23:09:10.554200 DUTY Scan : NO K
8752 23:09:10.554765 ZQ Calibration : PASS
8753 23:09:10.557400 Jitter Meter : NO K
8754 23:09:10.560984 CBT Training : PASS
8755 23:09:10.561542 Write leveling : PASS
8756 23:09:10.563843 RX DQS gating : PASS
8757 23:09:10.567459 RX DQ/DQS(RDDQC) : PASS
8758 23:09:10.568018 TX DQ/DQS : PASS
8759 23:09:10.570917 RX DATLAT : PASS
8760 23:09:10.574015 RX DQ/DQS(Engine): PASS
8761 23:09:10.574575 TX OE : PASS
8762 23:09:10.574952 All Pass.
8763 23:09:10.577426
8764 23:09:10.577979 CH 0, Rank 1
8765 23:09:10.580844 SW Impedance : PASS
8766 23:09:10.581403 DUTY Scan : NO K
8767 23:09:10.584005 ZQ Calibration : PASS
8768 23:09:10.584615 Jitter Meter : NO K
8769 23:09:10.587427 CBT Training : PASS
8770 23:09:10.590661 Write leveling : PASS
8771 23:09:10.591221 RX DQS gating : PASS
8772 23:09:10.594112 RX DQ/DQS(RDDQC) : PASS
8773 23:09:10.597149 TX DQ/DQS : PASS
8774 23:09:10.597710 RX DATLAT : PASS
8775 23:09:10.600780 RX DQ/DQS(Engine): PASS
8776 23:09:10.603922 TX OE : PASS
8777 23:09:10.604482 All Pass.
8778 23:09:10.604912
8779 23:09:10.605255 CH 1, Rank 0
8780 23:09:10.606777 SW Impedance : PASS
8781 23:09:10.610301 DUTY Scan : NO K
8782 23:09:10.610765 ZQ Calibration : PASS
8783 23:09:10.614245 Jitter Meter : NO K
8784 23:09:10.617042 CBT Training : PASS
8785 23:09:10.617505 Write leveling : PASS
8786 23:09:10.620644 RX DQS gating : PASS
8787 23:09:10.623890 RX DQ/DQS(RDDQC) : PASS
8788 23:09:10.624445 TX DQ/DQS : PASS
8789 23:09:10.627200 RX DATLAT : PASS
8790 23:09:10.630605 RX DQ/DQS(Engine): PASS
8791 23:09:10.631170 TX OE : PASS
8792 23:09:10.631543 All Pass.
8793 23:09:10.631886
8794 23:09:10.633858 CH 1, Rank 1
8795 23:09:10.637066 SW Impedance : PASS
8796 23:09:10.637523 DUTY Scan : NO K
8797 23:09:10.640801 ZQ Calibration : PASS
8798 23:09:10.641393 Jitter Meter : NO K
8799 23:09:10.643568 CBT Training : PASS
8800 23:09:10.647043 Write leveling : PASS
8801 23:09:10.647605 RX DQS gating : PASS
8802 23:09:10.650517 RX DQ/DQS(RDDQC) : PASS
8803 23:09:10.653546 TX DQ/DQS : PASS
8804 23:09:10.654007 RX DATLAT : PASS
8805 23:09:10.657069 RX DQ/DQS(Engine): PASS
8806 23:09:10.660604 TX OE : PASS
8807 23:09:10.661174 All Pass.
8808 23:09:10.661541
8809 23:09:10.663417 DramC Write-DBI on
8810 23:09:10.663870 PER_BANK_REFRESH: Hybrid Mode
8811 23:09:10.666726 TX_TRACKING: ON
8812 23:09:10.673347 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8813 23:09:10.683662 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8814 23:09:10.690047 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8815 23:09:10.693078 [FAST_K] Save calibration result to emmc
8816 23:09:10.696800 sync common calibartion params.
8817 23:09:10.700385 sync cbt_mode0:0, 1:0
8818 23:09:10.701109 dram_init: ddr_geometry: 0
8819 23:09:10.703335 dram_init: ddr_geometry: 0
8820 23:09:10.706606 dram_init: ddr_geometry: 0
8821 23:09:10.710190 0:dram_rank_size:80000000
8822 23:09:10.710760 1:dram_rank_size:80000000
8823 23:09:10.716313 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8824 23:09:10.719949 DFS_SHUFFLE_HW_MODE: ON
8825 23:09:10.723187 dramc_set_vcore_voltage set vcore to 725000
8826 23:09:10.723748 Read voltage for 1600, 0
8827 23:09:10.726713 Vio18 = 0
8828 23:09:10.727277 Vcore = 725000
8829 23:09:10.727649 Vdram = 0
8830 23:09:10.729469 Vddq = 0
8831 23:09:10.729930 Vmddr = 0
8832 23:09:10.733177 switch to 3200 Mbps bootup
8833 23:09:10.733742 [DramcRunTimeConfig]
8834 23:09:10.734115 PHYPLL
8835 23:09:10.736232 DPM_CONTROL_AFTERK: ON
8836 23:09:10.739758 PER_BANK_REFRESH: ON
8837 23:09:10.740320 REFRESH_OVERHEAD_REDUCTION: ON
8838 23:09:10.743207 CMD_PICG_NEW_MODE: OFF
8839 23:09:10.746226 XRTWTW_NEW_MODE: ON
8840 23:09:10.746683 XRTRTR_NEW_MODE: ON
8841 23:09:10.749870 TX_TRACKING: ON
8842 23:09:10.750331 RDSEL_TRACKING: OFF
8843 23:09:10.753178 DQS Precalculation for DVFS: ON
8844 23:09:10.753743 RX_TRACKING: OFF
8845 23:09:10.756565 HW_GATING DBG: ON
8846 23:09:10.759773 ZQCS_ENABLE_LP4: ON
8847 23:09:10.760329 RX_PICG_NEW_MODE: ON
8848 23:09:10.763049 TX_PICG_NEW_MODE: ON
8849 23:09:10.763606 ENABLE_RX_DCM_DPHY: ON
8850 23:09:10.766244 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8851 23:09:10.769344 DUMMY_READ_FOR_TRACKING: OFF
8852 23:09:10.772838 !!! SPM_CONTROL_AFTERK: OFF
8853 23:09:10.775881 !!! SPM could not control APHY
8854 23:09:10.776440 IMPEDANCE_TRACKING: ON
8855 23:09:10.779554 TEMP_SENSOR: ON
8856 23:09:10.780191 HW_SAVE_FOR_SR: OFF
8857 23:09:10.783024 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8858 23:09:10.785985 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8859 23:09:10.789237 Read ODT Tracking: ON
8860 23:09:10.792624 Refresh Rate DeBounce: ON
8861 23:09:10.793262 DFS_NO_QUEUE_FLUSH: ON
8862 23:09:10.795990 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8863 23:09:10.799245 ENABLE_DFS_RUNTIME_MRW: OFF
8864 23:09:10.802705 DDR_RESERVE_NEW_MODE: ON
8865 23:09:10.803267 MR_CBT_SWITCH_FREQ: ON
8866 23:09:10.805713 =========================
8867 23:09:10.824571 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8868 23:09:10.827362 dram_init: ddr_geometry: 0
8869 23:09:10.845463 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8870 23:09:10.848644 dram_init: dram init end (result: 0)
8871 23:09:10.855510 DRAM-K: Full calibration passed in 23441 msecs
8872 23:09:10.858688 MRC: failed to locate region type 0.
8873 23:09:10.859246 DRAM rank0 size:0x80000000,
8874 23:09:10.861816 DRAM rank1 size=0x80000000
8875 23:09:10.871776 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8876 23:09:10.878538 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8877 23:09:10.885173 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8878 23:09:10.891786 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8879 23:09:10.895017 DRAM rank0 size:0x80000000,
8880 23:09:10.898250 DRAM rank1 size=0x80000000
8881 23:09:10.898812 CBMEM:
8882 23:09:10.901699 IMD: root @ 0xfffff000 254 entries.
8883 23:09:10.904967 IMD: root @ 0xffffec00 62 entries.
8884 23:09:10.908264 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8885 23:09:10.911765 WARNING: RO_VPD is uninitialized or empty.
8886 23:09:10.918109 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8887 23:09:10.924902 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8888 23:09:10.937587 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
8889 23:09:10.949229 BS: romstage times (exec / console): total (unknown) / 22975 ms
8890 23:09:10.949786
8891 23:09:10.950154
8892 23:09:10.959318 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8893 23:09:10.962585 ARM64: Exception handlers installed.
8894 23:09:10.965946 ARM64: Testing exception
8895 23:09:10.969117 ARM64: Done test exception
8896 23:09:10.969673 Enumerating buses...
8897 23:09:10.972682 Show all devs... Before device enumeration.
8898 23:09:10.975739 Root Device: enabled 1
8899 23:09:10.979013 CPU_CLUSTER: 0: enabled 1
8900 23:09:10.979574 CPU: 00: enabled 1
8901 23:09:10.982352 Compare with tree...
8902 23:09:10.982924 Root Device: enabled 1
8903 23:09:10.985573 CPU_CLUSTER: 0: enabled 1
8904 23:09:10.989343 CPU: 00: enabled 1
8905 23:09:10.989904 Root Device scanning...
8906 23:09:10.992321 scan_static_bus for Root Device
8907 23:09:10.995647 CPU_CLUSTER: 0 enabled
8908 23:09:10.998909 scan_static_bus for Root Device done
8909 23:09:11.002510 scan_bus: bus Root Device finished in 8 msecs
8910 23:09:11.003079 done
8911 23:09:11.009012 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8912 23:09:11.012197 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8913 23:09:11.019046 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8914 23:09:11.022336 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8915 23:09:11.025504 Allocating resources...
8916 23:09:11.028618 Reading resources...
8917 23:09:11.032416 Root Device read_resources bus 0 link: 0
8918 23:09:11.033051 DRAM rank0 size:0x80000000,
8919 23:09:11.035169 DRAM rank1 size=0x80000000
8920 23:09:11.038986 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8921 23:09:11.042369 CPU: 00 missing read_resources
8922 23:09:11.045063 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8923 23:09:11.051673 Root Device read_resources bus 0 link: 0 done
8924 23:09:11.052212 Done reading resources.
8925 23:09:11.058241 Show resources in subtree (Root Device)...After reading.
8926 23:09:11.061601 Root Device child on link 0 CPU_CLUSTER: 0
8927 23:09:11.065199 CPU_CLUSTER: 0 child on link 0 CPU: 00
8928 23:09:11.076068 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8929 23:09:11.076646 CPU: 00
8930 23:09:11.078090 Root Device assign_resources, bus 0 link: 0
8931 23:09:11.081679 CPU_CLUSTER: 0 missing set_resources
8932 23:09:11.088177 Root Device assign_resources, bus 0 link: 0 done
8933 23:09:11.088767 Done setting resources.
8934 23:09:11.095303 Show resources in subtree (Root Device)...After assigning values.
8935 23:09:11.098541 Root Device child on link 0 CPU_CLUSTER: 0
8936 23:09:11.101671 CPU_CLUSTER: 0 child on link 0 CPU: 00
8937 23:09:11.111503 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8938 23:09:11.112065 CPU: 00
8939 23:09:11.114733 Done allocating resources.
8940 23:09:11.118269 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
8941 23:09:11.121216 Enabling resources...
8942 23:09:11.121679 done.
8943 23:09:11.128033 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
8944 23:09:11.128652 Initializing devices...
8945 23:09:11.131231 Root Device init
8946 23:09:11.131794 init hardware done!
8947 23:09:11.134528 0x00000018: ctrlr->caps
8948 23:09:11.137643 52.000 MHz: ctrlr->f_max
8949 23:09:11.138114 0.400 MHz: ctrlr->f_min
8950 23:09:11.141102 0x40ff8080: ctrlr->voltages
8951 23:09:11.144222 sclk: 390625
8952 23:09:11.144701 Bus Width = 1
8953 23:09:11.145067 sclk: 390625
8954 23:09:11.147844 Bus Width = 1
8955 23:09:11.148412 Early init status = 3
8956 23:09:11.154027 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
8957 23:09:11.157701 in-header: 03 fc 00 00 01 00 00 00
8958 23:09:11.158429 in-data: 00
8959 23:09:11.164239 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
8960 23:09:11.168388 in-header: 03 fd 00 00 00 00 00 00
8961 23:09:11.171179 in-data:
8962 23:09:11.174529 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
8963 23:09:11.179055 in-header: 03 fc 00 00 01 00 00 00
8964 23:09:11.182247 in-data: 00
8965 23:09:11.184909 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
8966 23:09:11.190776 in-header: 03 fd 00 00 00 00 00 00
8967 23:09:11.194395 in-data:
8968 23:09:11.197563 [SSUSB] Setting up USB HOST controller...
8969 23:09:11.201021 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
8970 23:09:11.204369 [SSUSB] phy power-on done.
8971 23:09:11.207580 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
8972 23:09:11.214244 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
8973 23:09:11.217205 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
8974 23:09:11.223999 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
8975 23:09:11.230387 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
8976 23:09:11.237084 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
8977 23:09:11.244109 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
8978 23:09:11.250584 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
8979 23:09:11.254083 SPM: binary array size = 0x9dc
8980 23:09:11.257259 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
8981 23:09:11.263774 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
8982 23:09:11.270554 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
8983 23:09:11.277167 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
8984 23:09:11.280113 configure_display: Starting display init
8985 23:09:11.314101 anx7625_power_on_init: Init interface.
8986 23:09:11.317380 anx7625_disable_pd_protocol: Disabled PD feature.
8987 23:09:11.320868 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
8988 23:09:11.348562 anx7625_start_dp_work: Secure OCM version=00
8989 23:09:11.351888 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
8990 23:09:11.366509 sp_tx_get_edid_block: EDID Block = 1
8991 23:09:11.469245 Extracted contents:
8992 23:09:11.472672 header: 00 ff ff ff ff ff ff 00
8993 23:09:11.475607 serial number: 26 cf 7d 05 00 00 00 00 00 1e
8994 23:09:11.479395 version: 01 04
8995 23:09:11.482027 basic params: 95 1f 11 78 0a
8996 23:09:11.485876 chroma info: 76 90 94 55 54 90 27 21 50 54
8997 23:09:11.489200 established: 00 00 00
8998 23:09:11.495513 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
8999 23:09:11.502300 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9000 23:09:11.505214 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9001 23:09:11.511873 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9002 23:09:11.518557 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9003 23:09:11.522096 extensions: 00
9004 23:09:11.522552 checksum: fb
9005 23:09:11.522913
9006 23:09:11.528640 Manufacturer: IVO Model 57d Serial Number 0
9007 23:09:11.529195 Made week 0 of 2020
9008 23:09:11.531661 EDID version: 1.4
9009 23:09:11.532222 Digital display
9010 23:09:11.535007 6 bits per primary color channel
9011 23:09:11.535478 DisplayPort interface
9012 23:09:11.538382 Maximum image size: 31 cm x 17 cm
9013 23:09:11.541445 Gamma: 220%
9014 23:09:11.541901 Check DPMS levels
9015 23:09:11.548303 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9016 23:09:11.551466 First detailed timing is preferred timing
9017 23:09:11.552036 Established timings supported:
9018 23:09:11.554780 Standard timings supported:
9019 23:09:11.557858 Detailed timings
9020 23:09:11.561385 Hex of detail: 383680a07038204018303c0035ae10000019
9021 23:09:11.568097 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9022 23:09:11.571687 0780 0798 07c8 0820 hborder 0
9023 23:09:11.574827 0438 043b 0447 0458 vborder 0
9024 23:09:11.577732 -hsync -vsync
9025 23:09:11.578192 Did detailed timing
9026 23:09:11.584817 Hex of detail: 000000000000000000000000000000000000
9027 23:09:11.587945 Manufacturer-specified data, tag 0
9028 23:09:11.591338 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9029 23:09:11.594214 ASCII string: InfoVision
9030 23:09:11.598108 Hex of detail: 000000fe00523134304e574635205248200a
9031 23:09:11.601256 ASCII string: R140NWF5 RH
9032 23:09:11.601969 Checksum
9033 23:09:11.604299 Checksum: 0xfb (valid)
9034 23:09:11.607757 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9035 23:09:11.611319 DSI data_rate: 832800000 bps
9036 23:09:11.617854 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9037 23:09:11.621005 anx7625_parse_edid: pixelclock(138800).
9038 23:09:11.624321 hactive(1920), hsync(48), hfp(24), hbp(88)
9039 23:09:11.627690 vactive(1080), vsync(12), vfp(3), vbp(17)
9040 23:09:11.630819 anx7625_dsi_config: config dsi.
9041 23:09:11.637226 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9042 23:09:11.651165 anx7625_dsi_config: success to config DSI
9043 23:09:11.654413 anx7625_dp_start: MIPI phy setup OK.
9044 23:09:11.657878 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9045 23:09:11.661284 mtk_ddp_mode_set invalid vrefresh 60
9046 23:09:11.664104 main_disp_path_setup
9047 23:09:11.664718 ovl_layer_smi_id_en
9048 23:09:11.667780 ovl_layer_smi_id_en
9049 23:09:11.668357 ccorr_config
9050 23:09:11.668763 aal_config
9051 23:09:11.671024 gamma_config
9052 23:09:11.671587 postmask_config
9053 23:09:11.674408 dither_config
9054 23:09:11.677435 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9055 23:09:11.684039 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9056 23:09:11.687901 Root Device init finished in 553 msecs
9057 23:09:11.690739 CPU_CLUSTER: 0 init
9058 23:09:11.697188 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9059 23:09:11.703760 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9060 23:09:11.704334 APU_MBOX 0x190000b0 = 0x10001
9061 23:09:11.707175 APU_MBOX 0x190001b0 = 0x10001
9062 23:09:11.710850 APU_MBOX 0x190005b0 = 0x10001
9063 23:09:11.714219 APU_MBOX 0x190006b0 = 0x10001
9064 23:09:11.719888 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9065 23:09:11.730458 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9066 23:09:11.742844 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9067 23:09:11.749108 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9068 23:09:11.760742 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9069 23:09:11.769758 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9070 23:09:11.773022 CPU_CLUSTER: 0 init finished in 81 msecs
9071 23:09:11.776620 Devices initialized
9072 23:09:11.779672 Show all devs... After init.
9073 23:09:11.780140 Root Device: enabled 1
9074 23:09:11.783088 CPU_CLUSTER: 0: enabled 1
9075 23:09:11.786617 CPU: 00: enabled 1
9076 23:09:11.789915 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9077 23:09:11.793467 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9078 23:09:11.796163 ELOG: NV offset 0x57f000 size 0x1000
9079 23:09:11.803240 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9080 23:09:11.809605 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9081 23:09:11.813279 ELOG: Event(17) added with size 13 at 2023-12-01 23:09:11 UTC
9082 23:09:11.816347 out: cmd=0x121: 03 db 21 01 00 00 00 00
9083 23:09:11.821061 in-header: 03 de 00 00 2c 00 00 00
9084 23:09:11.834519 in-data: 85 64 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9085 23:09:11.841249 ELOG: Event(A1) added with size 10 at 2023-12-01 23:09:11 UTC
9086 23:09:11.847898 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9087 23:09:11.854515 ELOG: Event(A0) added with size 9 at 2023-12-01 23:09:11 UTC
9088 23:09:11.857981 elog_add_boot_reason: Logged dev mode boot
9089 23:09:11.861419 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9090 23:09:11.864490 Finalize devices...
9091 23:09:11.865109 Devices finalized
9092 23:09:11.871636 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9093 23:09:11.874667 Writing coreboot table at 0xffe64000
9094 23:09:11.877767 0. 000000000010a000-0000000000113fff: RAMSTAGE
9095 23:09:11.881066 1. 0000000040000000-00000000400fffff: RAM
9096 23:09:11.884411 2. 0000000040100000-000000004032afff: RAMSTAGE
9097 23:09:11.891221 3. 000000004032b000-00000000545fffff: RAM
9098 23:09:11.894817 4. 0000000054600000-000000005465ffff: BL31
9099 23:09:11.897891 5. 0000000054660000-00000000ffe63fff: RAM
9100 23:09:11.901188 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9101 23:09:11.907883 7. 0000000100000000-000000013fffffff: RAM
9102 23:09:11.908457 Passing 5 GPIOs to payload:
9103 23:09:11.914598 NAME | PORT | POLARITY | VALUE
9104 23:09:11.917683 EC in RW | 0x000000aa | low | undefined
9105 23:09:11.924363 EC interrupt | 0x00000005 | low | undefined
9106 23:09:11.927658 TPM interrupt | 0x000000ab | high | undefined
9107 23:09:11.930857 SD card detect | 0x00000011 | high | undefined
9108 23:09:11.937420 speaker enable | 0x00000093 | high | undefined
9109 23:09:11.940403 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9110 23:09:11.944077 in-header: 03 f8 00 00 02 00 00 00
9111 23:09:11.944589 in-data: 03 00
9112 23:09:11.948072 ADC[4]: Raw value=668590 ID=5
9113 23:09:11.950838 ADC[3]: Raw value=212549 ID=1
9114 23:09:11.951409 RAM Code: 0x51
9115 23:09:11.953790 ADC[6]: Raw value=74778 ID=0
9116 23:09:11.957597 ADC[5]: Raw value=211444 ID=1
9117 23:09:11.958202 SKU Code: 0x1
9118 23:09:11.964294 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 8b6a
9119 23:09:11.967389 coreboot table: 964 bytes.
9120 23:09:11.970530 IMD ROOT 0. 0xfffff000 0x00001000
9121 23:09:11.973944 IMD SMALL 1. 0xffffe000 0x00001000
9122 23:09:11.977337 RO MCACHE 2. 0xffffc000 0x00001104
9123 23:09:11.980357 CONSOLE 3. 0xfff7c000 0x00080000
9124 23:09:11.983610 FMAP 4. 0xfff7b000 0x00000452
9125 23:09:11.986843 TIME STAMP 5. 0xfff7a000 0x00000910
9126 23:09:11.990166 VBOOT WORK 6. 0xfff66000 0x00014000
9127 23:09:11.993710 RAMOOPS 7. 0xffe66000 0x00100000
9128 23:09:11.996886 COREBOOT 8. 0xffe64000 0x00002000
9129 23:09:11.997461 IMD small region:
9130 23:09:12.000321 IMD ROOT 0. 0xffffec00 0x00000400
9131 23:09:12.003750 VPD 1. 0xffffeb80 0x0000006c
9132 23:09:12.007025 MMC STATUS 2. 0xffffeb60 0x00000004
9133 23:09:12.013452 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9134 23:09:12.016686 Probing TPM: done!
9135 23:09:12.019892 Connected to device vid:did:rid of 1ae0:0028:00
9136 23:09:12.030252 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
9137 23:09:12.033443 Initialized TPM device CR50 revision 0
9138 23:09:12.037138 Checking cr50 for pending updates
9139 23:09:12.040490 Reading cr50 TPM mode
9140 23:09:12.049484 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9141 23:09:12.055964 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9142 23:09:12.095873 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9143 23:09:12.099324 Checking segment from ROM address 0x40100000
9144 23:09:12.103082 Checking segment from ROM address 0x4010001c
9145 23:09:12.109257 Loading segment from ROM address 0x40100000
9146 23:09:12.109814 code (compression=0)
9147 23:09:12.118889 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9148 23:09:12.125936 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9149 23:09:12.126518 it's not compressed!
9150 23:09:12.132892 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9151 23:09:12.138763 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9152 23:09:12.156367 Loading segment from ROM address 0x4010001c
9153 23:09:12.156978 Entry Point 0x80000000
9154 23:09:12.159815 Loaded segments
9155 23:09:12.163126 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9156 23:09:12.169744 Jumping to boot code at 0x80000000(0xffe64000)
9157 23:09:12.176285 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9158 23:09:12.183097 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9159 23:09:12.190865 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9160 23:09:12.194288 Checking segment from ROM address 0x40100000
9161 23:09:12.197236 Checking segment from ROM address 0x4010001c
9162 23:09:12.204025 Loading segment from ROM address 0x40100000
9163 23:09:12.204663 code (compression=1)
9164 23:09:12.210906 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9165 23:09:12.220567 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9166 23:09:12.221131 using LZMA
9167 23:09:12.229325 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9168 23:09:12.235961 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9169 23:09:12.239156 Loading segment from ROM address 0x4010001c
9170 23:09:12.239633 Entry Point 0x54601000
9171 23:09:12.242739 Loaded segments
9172 23:09:12.245721 NOTICE: MT8192 bl31_setup
9173 23:09:12.252964 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9174 23:09:12.256036 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9175 23:09:12.259452 WARNING: region 0:
9176 23:09:12.262873 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9177 23:09:12.263450 WARNING: region 1:
9178 23:09:12.269330 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9179 23:09:12.272950 WARNING: region 2:
9180 23:09:12.276247 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9181 23:09:12.279396 WARNING: region 3:
9182 23:09:12.282392 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9183 23:09:12.285887 WARNING: region 4:
9184 23:09:12.292553 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9185 23:09:12.293137 WARNING: region 5:
9186 23:09:12.296242 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9187 23:09:12.299159 WARNING: region 6:
9188 23:09:12.302432 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9189 23:09:12.305671 WARNING: region 7:
9190 23:09:12.309454 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9191 23:09:12.315842 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9192 23:09:12.319186 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9193 23:09:12.322599 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9194 23:09:12.329185 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9195 23:09:12.332457 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9196 23:09:12.336126 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9197 23:09:12.342368 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9198 23:09:12.345688 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9199 23:09:12.352449 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9200 23:09:12.355750 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9201 23:09:12.358917 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9202 23:09:12.365952 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9203 23:09:12.369127 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9204 23:09:12.372370 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9205 23:09:12.378991 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9206 23:09:12.382268 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9207 23:09:12.389381 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9208 23:09:12.392356 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9209 23:09:12.395520 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9210 23:09:12.402397 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9211 23:09:12.405417 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9212 23:09:12.408823 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9213 23:09:12.415692 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9214 23:09:12.418624 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9215 23:09:12.425351 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9216 23:09:12.428833 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9217 23:09:12.432112 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9218 23:09:12.438884 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9219 23:09:12.442535 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9220 23:09:12.448989 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9221 23:09:12.452210 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9222 23:09:12.456152 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9223 23:09:12.462539 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9224 23:09:12.465739 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9225 23:09:12.469044 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9226 23:09:12.472230 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9227 23:09:12.479068 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9228 23:09:12.482327 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9229 23:09:12.485560 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9230 23:09:12.489107 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9231 23:09:12.495453 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9232 23:09:12.498993 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9233 23:09:12.502451 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9234 23:09:12.505609 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9235 23:09:12.512175 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9236 23:09:12.516068 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9237 23:09:12.519057 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9238 23:09:12.522359 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9239 23:09:12.529079 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9240 23:09:12.532117 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9241 23:09:12.538734 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9242 23:09:12.541859 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9243 23:09:12.548695 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9244 23:09:12.552313 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9245 23:09:12.555174 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9246 23:09:12.561888 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9247 23:09:12.565437 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9248 23:09:12.571871 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9249 23:09:12.575554 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9250 23:09:12.581712 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9251 23:09:12.585031 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9252 23:09:12.592157 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9253 23:09:12.595500 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9254 23:09:12.598712 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9255 23:09:12.605403 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9256 23:09:12.608460 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9257 23:09:12.615568 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9258 23:09:12.618701 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9259 23:09:12.624857 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9260 23:09:12.628717 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9261 23:09:12.631946 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9262 23:09:12.638477 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9263 23:09:12.641758 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9264 23:09:12.648697 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9265 23:09:12.651522 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9266 23:09:12.658255 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9267 23:09:12.661816 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9268 23:09:12.668883 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9269 23:09:12.671974 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9270 23:09:12.675076 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9271 23:09:12.681355 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9272 23:09:12.685118 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9273 23:09:12.691695 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9274 23:09:12.695002 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9275 23:09:12.701587 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9276 23:09:12.705111 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9277 23:09:12.708605 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9278 23:09:12.715041 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9279 23:09:12.718573 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9280 23:09:12.724653 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9281 23:09:12.728054 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9282 23:09:12.735468 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9283 23:09:12.737976 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9284 23:09:12.741237 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9285 23:09:12.747975 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9286 23:09:12.751357 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9287 23:09:12.758272 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9288 23:09:12.761429 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9289 23:09:12.764687 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9290 23:09:12.768061 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9291 23:09:12.774773 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9292 23:09:12.777909 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9293 23:09:12.781000 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9294 23:09:12.787983 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9295 23:09:12.791144 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9296 23:09:12.797906 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9297 23:09:12.801203 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9298 23:09:12.804676 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9299 23:09:12.811317 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9300 23:09:12.814692 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9301 23:09:12.821203 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9302 23:09:12.824580 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9303 23:09:12.827945 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9304 23:09:12.834207 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9305 23:09:12.837670 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9306 23:09:12.844380 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9307 23:09:12.847734 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9308 23:09:12.850878 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9309 23:09:12.857783 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9310 23:09:12.861108 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9311 23:09:12.864482 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9312 23:09:12.868137 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9313 23:09:12.870919 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9314 23:09:12.877761 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9315 23:09:12.881021 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9316 23:09:12.887609 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9317 23:09:12.890874 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9318 23:09:12.894400 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9319 23:09:12.901261 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9320 23:09:12.904329 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9321 23:09:12.907728 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9322 23:09:12.914778 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9323 23:09:12.917970 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9324 23:09:12.923979 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9325 23:09:12.927763 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9326 23:09:12.930981 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9327 23:09:12.937481 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9328 23:09:12.941110 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9329 23:09:12.947542 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9330 23:09:12.950928 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9331 23:09:12.954429 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9332 23:09:12.960632 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9333 23:09:12.964071 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9334 23:09:12.970612 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9335 23:09:12.974243 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9336 23:09:12.977308 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9337 23:09:12.984029 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9338 23:09:12.986938 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9339 23:09:12.990546 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9340 23:09:12.997344 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9341 23:09:13.000452 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9342 23:09:13.006948 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9343 23:09:13.010445 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9344 23:09:13.013830 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9345 23:09:13.020348 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9346 23:09:13.023871 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9347 23:09:13.030830 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9348 23:09:13.033768 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9349 23:09:13.037297 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9350 23:09:13.044095 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9351 23:09:13.047097 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9352 23:09:13.053634 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9353 23:09:13.057178 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9354 23:09:13.060690 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9355 23:09:13.066742 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9356 23:09:13.070181 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9357 23:09:13.076572 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9358 23:09:13.080277 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9359 23:09:13.083145 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9360 23:09:13.090194 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9361 23:09:13.093316 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9362 23:09:13.100057 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9363 23:09:13.103005 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9364 23:09:13.106349 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9365 23:09:13.113116 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9366 23:09:13.116408 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9367 23:09:13.123180 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9368 23:09:13.126241 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9369 23:09:13.129303 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9370 23:09:13.136331 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9371 23:09:13.139325 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9372 23:09:13.146313 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9373 23:09:13.149485 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9374 23:09:13.152812 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9375 23:09:13.159264 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9376 23:09:13.162875 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9377 23:09:13.166309 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9378 23:09:13.173052 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9379 23:09:13.176150 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9380 23:09:13.182456 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9381 23:09:13.185872 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9382 23:09:13.192446 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9383 23:09:13.196197 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9384 23:09:13.199063 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9385 23:09:13.205908 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9386 23:09:13.209009 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9387 23:09:13.215917 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9388 23:09:13.219249 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9389 23:09:13.225563 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9390 23:09:13.229063 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9391 23:09:13.232068 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9392 23:09:13.238692 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9393 23:09:13.242065 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9394 23:09:13.248657 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9395 23:09:13.251949 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9396 23:09:13.258591 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9397 23:09:13.262015 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9398 23:09:13.265471 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9399 23:09:13.272044 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9400 23:09:13.275189 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9401 23:09:13.281766 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9402 23:09:13.284831 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9403 23:09:13.291694 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9404 23:09:13.295202 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9405 23:09:13.297890 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9406 23:09:13.304778 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9407 23:09:13.308115 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9408 23:09:13.314536 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9409 23:09:13.318053 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9410 23:09:13.324586 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9411 23:09:13.327798 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9412 23:09:13.331363 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9413 23:09:13.337624 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9414 23:09:13.340652 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9415 23:09:13.347468 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9416 23:09:13.350641 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9417 23:09:13.357542 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9418 23:09:13.360886 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9419 23:09:13.364011 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9420 23:09:13.370590 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9421 23:09:13.373716 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9422 23:09:13.377467 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9423 23:09:13.380909 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9424 23:09:13.384306 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9425 23:09:13.390872 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9426 23:09:13.394014 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9427 23:09:13.400434 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9428 23:09:13.403858 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9429 23:09:13.407285 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9430 23:09:13.413681 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9431 23:09:13.416714 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9432 23:09:13.423321 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9433 23:09:13.426625 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9434 23:09:13.429959 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9435 23:09:13.436483 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9436 23:09:13.439866 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9437 23:09:13.442896 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9438 23:09:13.449619 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9439 23:09:13.453286 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9440 23:09:13.456447 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9441 23:09:13.463356 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9442 23:09:13.466401 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9443 23:09:13.473170 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9444 23:09:13.476748 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9445 23:09:13.479776 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9446 23:09:13.486064 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9447 23:09:13.489886 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9448 23:09:13.496075 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9449 23:09:13.499455 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9450 23:09:13.502856 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9451 23:09:13.509133 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9452 23:09:13.512992 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9453 23:09:13.516061 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9454 23:09:13.522737 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9455 23:09:13.525719 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9456 23:09:13.529113 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9457 23:09:13.535640 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9458 23:09:13.539041 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9459 23:09:13.542315 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9460 23:09:13.548916 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9461 23:09:13.551950 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9462 23:09:13.555588 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9463 23:09:13.559463 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9464 23:09:13.565493 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9465 23:09:13.568756 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9466 23:09:13.572107 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9467 23:09:13.575517 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9468 23:09:13.582225 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9469 23:09:13.585188 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9470 23:09:13.588793 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9471 23:09:13.595445 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9472 23:09:13.598396 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9473 23:09:13.601950 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9474 23:09:13.608674 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9475 23:09:13.611831 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9476 23:09:13.618502 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9477 23:09:13.621403 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9478 23:09:13.625396 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9479 23:09:13.631540 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9480 23:09:13.635183 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9481 23:09:13.641420 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9482 23:09:13.644623 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9483 23:09:13.648196 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9484 23:09:13.654338 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9485 23:09:13.658328 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9486 23:09:13.664400 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9487 23:09:13.667951 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9488 23:09:13.671346 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9489 23:09:13.678189 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9490 23:09:13.681050 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9491 23:09:13.687790 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9492 23:09:13.691043 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9493 23:09:13.697930 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9494 23:09:13.701116 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9495 23:09:13.704647 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9496 23:09:13.710944 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9497 23:09:13.714323 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9498 23:09:13.721034 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9499 23:09:13.723959 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9500 23:09:13.727796 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9501 23:09:13.734348 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9502 23:09:13.737260 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9503 23:09:13.743696 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9504 23:09:13.747500 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9505 23:09:13.751093 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9506 23:09:13.757070 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9507 23:09:13.760447 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9508 23:09:13.767242 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9509 23:09:13.770763 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9510 23:09:13.777564 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9511 23:09:13.780110 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9512 23:09:13.783843 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9513 23:09:13.790551 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9514 23:09:13.793854 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9515 23:09:13.800353 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9516 23:09:13.803515 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9517 23:09:13.807462 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9518 23:09:13.813194 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9519 23:09:13.816490 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9520 23:09:13.823431 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9521 23:09:13.826597 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9522 23:09:13.833232 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9523 23:09:13.836385 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9524 23:09:13.839684 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9525 23:09:13.846597 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9526 23:09:13.849655 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9527 23:09:13.856458 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9528 23:09:13.859605 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9529 23:09:13.863066 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9530 23:09:13.870066 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9531 23:09:13.873097 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9532 23:09:13.879865 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9533 23:09:13.883063 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9534 23:09:13.886328 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9535 23:09:13.892907 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9536 23:09:13.896178 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9537 23:09:13.902948 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9538 23:09:13.905771 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9539 23:09:13.912420 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9540 23:09:13.915664 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9541 23:09:13.919033 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9542 23:09:13.926045 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9543 23:09:13.928865 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9544 23:09:13.935796 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9545 23:09:13.939071 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9546 23:09:13.945281 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9547 23:09:13.948767 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9548 23:09:13.952233 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9549 23:09:13.958783 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9550 23:09:13.962193 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9551 23:09:13.969062 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9552 23:09:13.972234 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9553 23:09:13.978959 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9554 23:09:13.981818 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9555 23:09:13.985567 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9556 23:09:13.992145 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9557 23:09:13.995463 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9558 23:09:14.001951 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9559 23:09:14.004988 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9560 23:09:14.011724 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9561 23:09:14.015003 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9562 23:09:14.021632 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9563 23:09:14.024909 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9564 23:09:14.027944 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9565 23:09:14.035089 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9566 23:09:14.038327 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9567 23:09:14.044607 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9568 23:09:14.048127 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9569 23:09:14.054529 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9570 23:09:14.057994 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9571 23:09:14.064718 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9572 23:09:14.068306 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9573 23:09:14.071570 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9574 23:09:14.077476 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9575 23:09:14.080889 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9576 23:09:14.087631 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9577 23:09:14.091058 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9578 23:09:14.097520 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9579 23:09:14.100930 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9580 23:09:14.107431 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9581 23:09:14.110835 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9582 23:09:14.113972 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9583 23:09:14.121192 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9584 23:09:14.123972 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9585 23:09:14.130582 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9586 23:09:14.133635 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9587 23:09:14.140835 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9588 23:09:14.143574 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9589 23:09:14.150289 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9590 23:09:14.153637 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9591 23:09:14.156819 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9592 23:09:14.163750 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9593 23:09:14.166968 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9594 23:09:14.173448 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9595 23:09:14.176639 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9596 23:09:14.183623 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9597 23:09:14.186471 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9598 23:09:14.189917 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9599 23:09:14.196756 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9600 23:09:14.199694 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9601 23:09:14.206551 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9602 23:09:14.209703 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9603 23:09:14.216989 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9604 23:09:14.219827 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9605 23:09:14.226557 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9606 23:09:14.229437 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9607 23:09:14.236019 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9608 23:09:14.239335 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9609 23:09:14.246383 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9610 23:09:14.249533 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9611 23:09:14.256004 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9612 23:09:14.259218 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9613 23:09:14.265952 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9614 23:09:14.269086 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9615 23:09:14.275799 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9616 23:09:14.279236 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9617 23:09:14.285693 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9618 23:09:14.289225 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9619 23:09:14.296016 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9620 23:09:14.298802 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9621 23:09:14.305451 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9622 23:09:14.308799 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9623 23:09:14.315709 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9624 23:09:14.318962 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9625 23:09:14.325469 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9626 23:09:14.326037 INFO: [APUAPC] vio 0
9627 23:09:14.332318 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9628 23:09:14.335805 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9629 23:09:14.339128 INFO: [APUAPC] D0_APC_0: 0x400510
9630 23:09:14.342485 INFO: [APUAPC] D0_APC_1: 0x0
9631 23:09:14.345267 INFO: [APUAPC] D0_APC_2: 0x1540
9632 23:09:14.349091 INFO: [APUAPC] D0_APC_3: 0x0
9633 23:09:14.352791 INFO: [APUAPC] D1_APC_0: 0xffffffff
9634 23:09:14.355875 INFO: [APUAPC] D1_APC_1: 0xffffffff
9635 23:09:14.358947 INFO: [APUAPC] D1_APC_2: 0x3fffff
9636 23:09:14.362308 INFO: [APUAPC] D1_APC_3: 0x0
9637 23:09:14.365599 INFO: [APUAPC] D2_APC_0: 0xffffffff
9638 23:09:14.369203 INFO: [APUAPC] D2_APC_1: 0xffffffff
9639 23:09:14.372312 INFO: [APUAPC] D2_APC_2: 0x3fffff
9640 23:09:14.375612 INFO: [APUAPC] D2_APC_3: 0x0
9641 23:09:14.378521 INFO: [APUAPC] D3_APC_0: 0xffffffff
9642 23:09:14.381880 INFO: [APUAPC] D3_APC_1: 0xffffffff
9643 23:09:14.385061 INFO: [APUAPC] D3_APC_2: 0x3fffff
9644 23:09:14.388712 INFO: [APUAPC] D3_APC_3: 0x0
9645 23:09:14.391947 INFO: [APUAPC] D4_APC_0: 0xffffffff
9646 23:09:14.394887 INFO: [APUAPC] D4_APC_1: 0xffffffff
9647 23:09:14.398911 INFO: [APUAPC] D4_APC_2: 0x3fffff
9648 23:09:14.401720 INFO: [APUAPC] D4_APC_3: 0x0
9649 23:09:14.405237 INFO: [APUAPC] D5_APC_0: 0xffffffff
9650 23:09:14.408243 INFO: [APUAPC] D5_APC_1: 0xffffffff
9651 23:09:14.411671 INFO: [APUAPC] D5_APC_2: 0x3fffff
9652 23:09:14.415082 INFO: [APUAPC] D5_APC_3: 0x0
9653 23:09:14.418172 INFO: [APUAPC] D6_APC_0: 0xffffffff
9654 23:09:14.421543 INFO: [APUAPC] D6_APC_1: 0xffffffff
9655 23:09:14.424670 INFO: [APUAPC] D6_APC_2: 0x3fffff
9656 23:09:14.425241 INFO: [APUAPC] D6_APC_3: 0x0
9657 23:09:14.431602 INFO: [APUAPC] D7_APC_0: 0xffffffff
9658 23:09:14.434453 INFO: [APUAPC] D7_APC_1: 0xffffffff
9659 23:09:14.438129 INFO: [APUAPC] D7_APC_2: 0x3fffff
9660 23:09:14.438700 INFO: [APUAPC] D7_APC_3: 0x0
9661 23:09:14.441073 INFO: [APUAPC] D8_APC_0: 0xffffffff
9662 23:09:14.448024 INFO: [APUAPC] D8_APC_1: 0xffffffff
9663 23:09:14.451539 INFO: [APUAPC] D8_APC_2: 0x3fffff
9664 23:09:14.452149 INFO: [APUAPC] D8_APC_3: 0x0
9665 23:09:14.454362 INFO: [APUAPC] D9_APC_0: 0xffffffff
9666 23:09:14.457607 INFO: [APUAPC] D9_APC_1: 0xffffffff
9667 23:09:14.461395 INFO: [APUAPC] D9_APC_2: 0x3fffff
9668 23:09:14.464677 INFO: [APUAPC] D9_APC_3: 0x0
9669 23:09:14.467718 INFO: [APUAPC] D10_APC_0: 0xffffffff
9670 23:09:14.470837 INFO: [APUAPC] D10_APC_1: 0xffffffff
9671 23:09:14.474487 INFO: [APUAPC] D10_APC_2: 0x3fffff
9672 23:09:14.477268 INFO: [APUAPC] D10_APC_3: 0x0
9673 23:09:14.480747 INFO: [APUAPC] D11_APC_0: 0xffffffff
9674 23:09:14.487571 INFO: [APUAPC] D11_APC_1: 0xffffffff
9675 23:09:14.490804 INFO: [APUAPC] D11_APC_2: 0x3fffff
9676 23:09:14.491364 INFO: [APUAPC] D11_APC_3: 0x0
9677 23:09:14.497469 INFO: [APUAPC] D12_APC_0: 0xffffffff
9678 23:09:14.501439 INFO: [APUAPC] D12_APC_1: 0xffffffff
9679 23:09:14.504118 INFO: [APUAPC] D12_APC_2: 0x3fffff
9680 23:09:14.504744 INFO: [APUAPC] D12_APC_3: 0x0
9681 23:09:14.510624 INFO: [APUAPC] D13_APC_0: 0xffffffff
9682 23:09:14.513794 INFO: [APUAPC] D13_APC_1: 0xffffffff
9683 23:09:14.517365 INFO: [APUAPC] D13_APC_2: 0x3fffff
9684 23:09:14.517945 INFO: [APUAPC] D13_APC_3: 0x0
9685 23:09:14.523783 INFO: [APUAPC] D14_APC_0: 0xffffffff
9686 23:09:14.527083 INFO: [APUAPC] D14_APC_1: 0xffffffff
9687 23:09:14.530750 INFO: [APUAPC] D14_APC_2: 0x3fffff
9688 23:09:14.533541 INFO: [APUAPC] D14_APC_3: 0x0
9689 23:09:14.536885 INFO: [APUAPC] D15_APC_0: 0xffffffff
9690 23:09:14.540325 INFO: [APUAPC] D15_APC_1: 0xffffffff
9691 23:09:14.543487 INFO: [APUAPC] D15_APC_2: 0x3fffff
9692 23:09:14.546934 INFO: [APUAPC] D15_APC_3: 0x0
9693 23:09:14.547486 INFO: [APUAPC] APC_CON: 0x4
9694 23:09:14.549942 INFO: [NOCDAPC] D0_APC_0: 0x0
9695 23:09:14.553190 INFO: [NOCDAPC] D0_APC_1: 0x0
9696 23:09:14.556616 INFO: [NOCDAPC] D1_APC_0: 0x0
9697 23:09:14.560410 INFO: [NOCDAPC] D1_APC_1: 0xfff
9698 23:09:14.563780 INFO: [NOCDAPC] D2_APC_0: 0x0
9699 23:09:14.566897 INFO: [NOCDAPC] D2_APC_1: 0xfff
9700 23:09:14.570028 INFO: [NOCDAPC] D3_APC_0: 0x0
9701 23:09:14.573445 INFO: [NOCDAPC] D3_APC_1: 0xfff
9702 23:09:14.576567 INFO: [NOCDAPC] D4_APC_0: 0x0
9703 23:09:14.580045 INFO: [NOCDAPC] D4_APC_1: 0xfff
9704 23:09:14.580646 INFO: [NOCDAPC] D5_APC_0: 0x0
9705 23:09:14.583350 INFO: [NOCDAPC] D5_APC_1: 0xfff
9706 23:09:14.586184 INFO: [NOCDAPC] D6_APC_0: 0x0
9707 23:09:14.589777 INFO: [NOCDAPC] D6_APC_1: 0xfff
9708 23:09:14.593177 INFO: [NOCDAPC] D7_APC_0: 0x0
9709 23:09:14.596488 INFO: [NOCDAPC] D7_APC_1: 0xfff
9710 23:09:14.599667 INFO: [NOCDAPC] D8_APC_0: 0x0
9711 23:09:14.603145 INFO: [NOCDAPC] D8_APC_1: 0xfff
9712 23:09:14.606043 INFO: [NOCDAPC] D9_APC_0: 0x0
9713 23:09:14.609470 INFO: [NOCDAPC] D9_APC_1: 0xfff
9714 23:09:14.612885 INFO: [NOCDAPC] D10_APC_0: 0x0
9715 23:09:14.616255 INFO: [NOCDAPC] D10_APC_1: 0xfff
9716 23:09:14.616878 INFO: [NOCDAPC] D11_APC_0: 0x0
9717 23:09:14.619492 INFO: [NOCDAPC] D11_APC_1: 0xfff
9718 23:09:14.622676 INFO: [NOCDAPC] D12_APC_0: 0x0
9719 23:09:14.625957 INFO: [NOCDAPC] D12_APC_1: 0xfff
9720 23:09:14.629690 INFO: [NOCDAPC] D13_APC_0: 0x0
9721 23:09:14.632370 INFO: [NOCDAPC] D13_APC_1: 0xfff
9722 23:09:14.635751 INFO: [NOCDAPC] D14_APC_0: 0x0
9723 23:09:14.639083 INFO: [NOCDAPC] D14_APC_1: 0xfff
9724 23:09:14.642501 INFO: [NOCDAPC] D15_APC_0: 0x0
9725 23:09:14.645714 INFO: [NOCDAPC] D15_APC_1: 0xfff
9726 23:09:14.649316 INFO: [NOCDAPC] APC_CON: 0x4
9727 23:09:14.652301 INFO: [APUAPC] set_apusys_apc done
9728 23:09:14.656057 INFO: [DEVAPC] devapc_init done
9729 23:09:14.658977 INFO: GICv3 without legacy support detected.
9730 23:09:14.662416 INFO: ARM GICv3 driver initialized in EL3
9731 23:09:14.665726 INFO: Maximum SPI INTID supported: 639
9732 23:09:14.672187 INFO: BL31: Initializing runtime services
9733 23:09:14.675344 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9734 23:09:14.678837 INFO: SPM: enable CPC mode
9735 23:09:14.685480 INFO: mcdi ready for mcusys-off-idle and system suspend
9736 23:09:14.688570 INFO: BL31: Preparing for EL3 exit to normal world
9737 23:09:14.691933 INFO: Entry point address = 0x80000000
9738 23:09:14.695216 INFO: SPSR = 0x8
9739 23:09:14.700563
9740 23:09:14.701224
9741 23:09:14.701605
9742 23:09:14.704371 Starting depthcharge on Spherion...
9743 23:09:14.705006
9744 23:09:14.705389 Wipe memory regions:
9745 23:09:14.705739
9746 23:09:14.708430 end: 2.2.3 depthcharge-start (duration 00:00:28) [common]
9747 23:09:14.709051 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
9748 23:09:14.709508 Setting prompt string to ['asurada:']
9749 23:09:14.709946 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
9750 23:09:14.710665 [0x00000040000000, 0x00000054600000)
9751 23:09:14.829753
9752 23:09:14.830400 [0x00000054660000, 0x00000080000000)
9753 23:09:15.089878
9754 23:09:15.090446 [0x000000821a7280, 0x000000ffe64000)
9755 23:09:15.834878
9756 23:09:15.835446 [0x00000100000000, 0x00000140000000)
9757 23:09:16.216009
9758 23:09:16.219139 Initializing XHCI USB controller at 0x11200000.
9759 23:09:17.256623
9760 23:09:17.259686 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9761 23:09:17.260154
9762 23:09:17.260565
9763 23:09:17.261042
9764 23:09:17.261903 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9766 23:09:17.363137 asurada: tftpboot 192.168.201.1 12154449/tftp-deploy-dwu5w1iq/kernel/image.itb 12154449/tftp-deploy-dwu5w1iq/kernel/cmdline
9767 23:09:17.363815 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9768 23:09:17.364258 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:24)
9769 23:09:17.368481 tftpboot 192.168.201.1 12154449/tftp-deploy-dwu5w1iq/kernel/image.itp-deploy-dwu5w1iq/kernel/cmdline
9770 23:09:17.369009
9771 23:09:17.369383 Waiting for link
9772 23:09:17.529416
9773 23:09:17.529993 R8152: Initializing
9774 23:09:17.530374
9775 23:09:17.532648 Version 9 (ocp_data = 6010)
9776 23:09:17.533227
9777 23:09:17.535736 R8152: Done initializing
9778 23:09:17.536324
9779 23:09:17.536751 Adding net device
9780 23:09:19.418964
9781 23:09:19.419584 done.
9782 23:09:19.419976
9783 23:09:19.420339 MAC: 00:e0:4c:68:03:bd
9784 23:09:19.420825
9785 23:09:19.421851 Sending DHCP discover... done.
9786 23:09:19.422337
9787 23:09:19.425144 Waiting for reply... done.
9788 23:09:19.425610
9789 23:09:19.428589 Sending DHCP request... done.
9790 23:09:19.429057
9791 23:09:19.431769 Waiting for reply... done.
9792 23:09:19.432234
9793 23:09:19.432658 My ip is 192.168.201.16
9794 23:09:19.433016
9795 23:09:19.435005 The DHCP server ip is 192.168.201.1
9796 23:09:19.435473
9797 23:09:19.441943 TFTP server IP predefined by user: 192.168.201.1
9798 23:09:19.442526
9799 23:09:19.448434 Bootfile predefined by user: 12154449/tftp-deploy-dwu5w1iq/kernel/image.itb
9800 23:09:19.448928
9801 23:09:19.449298 Sending tftp read request... done.
9802 23:09:19.449645
9803 23:09:19.458332 Waiting for the transfer...
9804 23:09:19.458793
9805 23:09:19.864274 00000000 ################################################################
9806 23:09:19.864826
9807 23:09:20.284875 00080000 ################################################################
9808 23:09:20.285369
9809 23:09:20.669148 00100000 ################################################################
9810 23:09:20.669647
9811 23:09:21.047006 00180000 ################################################################
9812 23:09:21.047496
9813 23:09:21.464294 00200000 ################################################################
9814 23:09:21.464903
9815 23:09:21.850193 00280000 ################################################################
9816 23:09:21.850326
9817 23:09:22.152952 00300000 ################################################################
9818 23:09:22.153086
9819 23:09:22.457250 00380000 ################################################################
9820 23:09:22.457389
9821 23:09:22.762180 00400000 ################################################################
9822 23:09:22.762344
9823 23:09:23.065800 00480000 ################################################################
9824 23:09:23.065932
9825 23:09:23.366367 00500000 ################################################################
9826 23:09:23.366496
9827 23:09:23.668302 00580000 ################################################################
9828 23:09:23.668463
9829 23:09:23.969281 00600000 ################################################################
9830 23:09:23.969414
9831 23:09:24.271473 00680000 ################################################################
9832 23:09:24.271633
9833 23:09:24.573349 00700000 ################################################################
9834 23:09:24.573484
9835 23:09:24.873264 00780000 ################################################################
9836 23:09:24.873426
9837 23:09:25.175283 00800000 ################################################################
9838 23:09:25.175416
9839 23:09:25.478250 00880000 ################################################################
9840 23:09:25.478409
9841 23:09:25.764442 00900000 ################################################################
9842 23:09:25.764640
9843 23:09:26.052725 00980000 ################################################################
9844 23:09:26.052857
9845 23:09:26.344142 00a00000 ################################################################
9846 23:09:26.344298
9847 23:09:26.633094 00a80000 ################################################################
9848 23:09:26.633225
9849 23:09:26.920360 00b00000 ################################################################
9850 23:09:26.920494
9851 23:09:27.203759 00b80000 ################################################################
9852 23:09:27.203891
9853 23:09:27.492219 00c00000 ################################################################
9854 23:09:27.492351
9855 23:09:27.755590 00c80000 ################################################################
9856 23:09:27.755721
9857 23:09:28.011695 00d00000 ################################################################
9858 23:09:28.011832
9859 23:09:28.294210 00d80000 ################################################################
9860 23:09:28.294341
9861 23:09:28.587949 00e00000 ################################################################
9862 23:09:28.588082
9863 23:09:28.889154 00e80000 ################################################################
9864 23:09:28.889288
9865 23:09:29.166938 00f00000 ################################################################
9866 23:09:29.167072
9867 23:09:29.437417 00f80000 ################################################################
9868 23:09:29.437549
9869 23:09:29.704646 01000000 ################################################################
9870 23:09:29.704777
9871 23:09:29.961608 01080000 ################################################################
9872 23:09:29.961739
9873 23:09:30.240631 01100000 ################################################################
9874 23:09:30.240764
9875 23:09:30.518713 01180000 ################################################################
9876 23:09:30.518845
9877 23:09:30.810541 01200000 ################################################################
9878 23:09:30.810672
9879 23:09:31.091310 01280000 ################################################################
9880 23:09:31.091466
9881 23:09:31.379041 01300000 ################################################################
9882 23:09:31.379171
9883 23:09:31.669643 01380000 ################################################################
9884 23:09:31.669797
9885 23:09:31.939891 01400000 ################################################################
9886 23:09:31.940018
9887 23:09:32.209343 01480000 ################################################################
9888 23:09:32.209474
9889 23:09:32.484395 01500000 ################################################################
9890 23:09:32.484557
9891 23:09:32.777729 01580000 ################################################################
9892 23:09:32.777884
9893 23:09:33.069258 01600000 ################################################################
9894 23:09:33.069388
9895 23:09:33.347822 01680000 ################################################################
9896 23:09:33.347960
9897 23:09:33.601221 01700000 ################################################################
9898 23:09:33.601351
9899 23:09:33.852908 01780000 ################################################################
9900 23:09:33.853043
9901 23:09:34.142982 01800000 ################################################################
9902 23:09:34.143113
9903 23:09:34.417984 01880000 ################################################################
9904 23:09:34.418115
9905 23:09:34.706133 01900000 ################################################################
9906 23:09:34.706266
9907 23:09:34.987392 01980000 ################################################################
9908 23:09:34.987550
9909 23:09:35.281176 01a00000 ################################################################
9910 23:09:35.281304
9911 23:09:35.573515 01a80000 ################################################################
9912 23:09:35.573671
9913 23:09:35.861804 01b00000 ################################################################
9914 23:09:35.861932
9915 23:09:36.121298 01b80000 ################################################################
9916 23:09:36.121456
9917 23:09:36.374411 01c00000 ################################################################
9918 23:09:36.374546
9919 23:09:36.642352 01c80000 ################################################################
9920 23:09:36.642480
9921 23:09:36.937326 01d00000 ################################################################
9922 23:09:36.937453
9923 23:09:37.216490 01d80000 ################################################################
9924 23:09:37.216663
9925 23:09:37.507268 01e00000 ################################################################
9926 23:09:37.507398
9927 23:09:37.804255 01e80000 ################################################################
9928 23:09:37.804387
9929 23:09:38.074487 01f00000 ################################################################
9930 23:09:38.074616
9931 23:09:38.332771 01f80000 ################################################################
9932 23:09:38.332900
9933 23:09:38.625606 02000000 ################################################################
9934 23:09:38.625741
9935 23:09:38.916160 02080000 ################################################################
9936 23:09:38.916296
9937 23:09:39.180904 02100000 ################################################################
9938 23:09:39.181037
9939 23:09:39.458195 02180000 ################################################################
9940 23:09:39.458329
9941 23:09:39.733023 02200000 ################################################################
9942 23:09:39.733161
9943 23:09:40.034794 02280000 ################################################################
9944 23:09:40.034952
9945 23:09:40.335090 02300000 ################################################################
9946 23:09:40.335253
9947 23:09:40.636266 02380000 ################################################################
9948 23:09:40.636426
9949 23:09:40.936770 02400000 ################################################################
9950 23:09:40.936897
9951 23:09:41.237285 02480000 ################################################################
9952 23:09:41.237444
9953 23:09:41.539292 02500000 ################################################################
9954 23:09:41.539444
9955 23:09:41.894781 02580000 ################################################################
9956 23:09:41.895283
9957 23:09:42.279326 02600000 ################################################################
9958 23:09:42.279984
9959 23:09:42.661255 02680000 ################################################################
9960 23:09:42.661938
9961 23:09:43.058506 02700000 ################################################################
9962 23:09:43.058998
9963 23:09:43.413788 02780000 ################################################################
9964 23:09:43.413923
9965 23:09:43.741073 02800000 ################################################################
9966 23:09:43.741205
9967 23:09:44.081967 02880000 ################################################################
9968 23:09:44.082472
9969 23:09:44.504202 02900000 ################################################################
9970 23:09:44.504763
9971 23:09:44.815638 02980000 ################################################################
9972 23:09:44.815775
9973 23:09:45.118390 02a00000 ################################################################
9974 23:09:45.118527
9975 23:09:45.418417 02a80000 ################################################################
9976 23:09:45.418570
9977 23:09:45.719079 02b00000 ################################################################
9978 23:09:45.719233
9979 23:09:46.013908 02b80000 ################################################################
9980 23:09:46.014038
9981 23:09:46.311579 02c00000 ################################################################
9982 23:09:46.311710
9983 23:09:46.612384 02c80000 ################################################################
9984 23:09:46.612586
9985 23:09:46.912201 02d00000 ################################################################
9986 23:09:46.912341
9987 23:09:47.291808 02d80000 ################################################################
9988 23:09:47.292429
9989 23:09:47.712799 02e00000 ################################################################
9990 23:09:47.713438
9991 23:09:48.102405 02e80000 ################################################################
9992 23:09:48.102553
9993 23:09:48.405564 02f00000 ################################################################
9994 23:09:48.405703
9995 23:09:48.708468 02f80000 ################################################################
9996 23:09:48.708616
9997 23:09:49.011078 03000000 ################################################################
9998 23:09:49.011216
9999 23:09:49.315028 03080000 ################################################################
10000 23:09:49.315165
10001 23:09:49.687724 03100000 ################################################################
10002 23:09:49.688223
10003 23:09:50.076317 03180000 ################################################################
10004 23:09:50.076917
10005 23:09:50.481445 03200000 ################################################################
10006 23:09:50.481955
10007 23:09:50.862511 03280000 ################################################################
10008 23:09:50.863158
10009 23:09:51.249359 03300000 ################################################################
10010 23:09:51.249875
10011 23:09:51.631904 03380000 ################################################################
10012 23:09:51.632620
10013 23:09:52.027383 03400000 ################################################################
10014 23:09:52.027903
10015 23:09:52.380145 03480000 ################################################################
10016 23:09:52.380461
10017 23:09:52.759141 03500000 ################################################################
10018 23:09:52.759650
10019 23:09:53.154637 03580000 ################################################################
10020 23:09:53.155138
10021 23:09:53.531903 03600000 ################################################################
10022 23:09:53.532417
10023 23:09:53.910732 03680000 ################################################################
10024 23:09:53.910875
10025 23:09:54.213124 03700000 ################################################################
10026 23:09:54.213265
10027 23:09:54.463150 03780000 ##################################################### done.
10028 23:09:54.463283
10029 23:09:54.466545 The bootfile was 58628866 bytes long.
10030 23:09:54.466636
10031 23:09:54.469902 Sending tftp read request... done.
10032 23:09:54.469989
10033 23:09:54.470058 Waiting for the transfer...
10034 23:09:54.470124
10035 23:09:54.473224 00000000 # done.
10036 23:09:54.473320
10037 23:09:54.479990 Command line loaded dynamically from TFTP file: 12154449/tftp-deploy-dwu5w1iq/kernel/cmdline
10038 23:09:54.480176
10039 23:09:54.493280 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10040 23:09:54.493796
10041 23:09:54.496612 Loading FIT.
10042 23:09:54.497047
10043 23:09:54.499808 Image ramdisk-1 has 47535571 bytes.
10044 23:09:54.500230
10045 23:09:54.503255 Image fdt-1 has 47278 bytes.
10046 23:09:54.503677
10047 23:09:54.504015 Image kernel-1 has 11043984 bytes.
10048 23:09:54.506333
10049 23:09:54.512964 Compat preference: google,spherion-rev3-sku1 google,spherion-rev3 google,spherion-sku1 google,spherion
10050 23:09:54.513390
10051 23:09:54.529719 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 (match) google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10052 23:09:54.533217
10053 23:09:54.536122 Choosing best match conf-1 for compat google,spherion-rev3.
10054 23:09:54.540785
10055 23:09:54.545521 Connected to device vid:did:rid of 1ae0:0028:00
10056 23:09:54.552095
10057 23:09:54.555910 tpm_get_response: command 0x17b, return code 0x0
10058 23:09:54.556464
10059 23:09:54.558869 ec_init: CrosEC protocol v3 supported (256, 248)
10060 23:09:54.563297
10061 23:09:54.566516 tpm_cleanup: add release locality here.
10062 23:09:54.567049
10063 23:09:54.567388 Shutting down all USB controllers.
10064 23:09:54.569597
10065 23:09:54.569987 Removing current net device
10066 23:09:54.570308
10067 23:09:54.576620 Exiting depthcharge with code 4 at timestamp: 68122815
10068 23:09:54.577154
10069 23:09:54.579337 LZMA decompressing kernel-1 to 0x821a6718
10070 23:09:54.579807
10071 23:09:54.583152 LZMA decompressing kernel-1 to 0x40000000
10072 23:09:55.975948
10073 23:09:55.976540 jumping to kernel
10074 23:09:55.978704 end: 2.2.4 bootloader-commands (duration 00:00:41) [common]
10075 23:09:55.979259 start: 2.2.5 auto-login-action (timeout 00:03:45) [common]
10076 23:09:55.979680 Setting prompt string to ['Linux version [0-9]']
10077 23:09:55.980054 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10078 23:09:55.980436 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10079 23:09:56.026049
10080 23:09:56.029380 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10081 23:09:56.033259 start: 2.2.5.1 login-action (timeout 00:03:45) [common]
10082 23:09:56.033827 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10083 23:09:56.034222 Setting prompt string to []
10084 23:09:56.034651 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10085 23:09:56.035067 Using line separator: #'\n'#
10086 23:09:56.035406 No login prompt set.
10087 23:09:56.035756 Parsing kernel messages
10088 23:09:56.036068 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10089 23:09:56.036676 [login-action] Waiting for messages, (timeout 00:03:45)
10090 23:09:56.052429 [ 0.000000] Linux version 6.1.64-cip10 (KernelCI@build-j31357-arm64-gcc-10-defconfig-arm64-chromebook-69txj) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Dec 1 22:47:09 UTC 2023
10091 23:09:56.056142 [ 0.000000] random: crng init done
10092 23:09:56.062420 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10093 23:09:56.066021 [ 0.000000] efi: UEFI not found.
10094 23:09:56.072446 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10095 23:09:56.078875 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10096 23:09:56.089092 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10097 23:09:56.099018 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10098 23:09:56.105506 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10099 23:09:56.111817 [ 0.000000] printk: bootconsole [mtk8250] enabled
10100 23:09:56.118540 [ 0.000000] NUMA: No NUMA configuration found
10101 23:09:56.124922 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10102 23:09:56.128109 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d4a00-0x13f7d6fff]
10103 23:09:56.131749 [ 0.000000] Zone ranges:
10104 23:09:56.138376 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10105 23:09:56.141400 [ 0.000000] DMA32 empty
10106 23:09:56.148175 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10107 23:09:56.151312 [ 0.000000] Movable zone start for each node
10108 23:09:56.155142 [ 0.000000] Early memory node ranges
10109 23:09:56.161485 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10110 23:09:56.167960 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10111 23:09:56.174565 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10112 23:09:56.180867 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10113 23:09:56.187603 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10114 23:09:56.194101 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10115 23:09:56.223811 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10116 23:09:56.230448 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10117 23:09:56.237452 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10118 23:09:56.240639 [ 0.000000] psci: probing for conduit method from DT.
10119 23:09:56.247130 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10120 23:09:56.250556 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10121 23:09:56.257126 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10122 23:09:56.260447 [ 0.000000] psci: SMC Calling Convention v1.2
10123 23:09:56.267200 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10124 23:09:56.270464 [ 0.000000] Detected VIPT I-cache on CPU0
10125 23:09:56.277131 [ 0.000000] CPU features: detected: GIC system register CPU interface
10126 23:09:56.283543 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10127 23:09:56.290348 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10128 23:09:56.297147 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10129 23:09:56.306545 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10130 23:09:56.313198 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10131 23:09:56.316493 [ 0.000000] alternatives: applying boot alternatives
10132 23:09:56.322862 [ 0.000000] Fallback order for Node 0: 0
10133 23:09:56.329852 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10134 23:09:56.333411 [ 0.000000] Policy zone: Normal
10135 23:09:56.346408 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10136 23:09:56.356432 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10137 23:09:56.367027 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10138 23:09:56.376908 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10139 23:09:56.383439 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10140 23:09:56.386907 <6>[ 0.000000] software IO TLB: area num 8.
10141 23:09:56.443576 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10142 23:09:56.523515 <6>[ 0.000000] Memory: 3808720K/4191232K available (17984K kernel code, 4116K rwdata, 17316K rodata, 8448K init, 615K bss, 349744K reserved, 32768K cma-reserved)
10143 23:09:56.529998 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10144 23:09:56.536888 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10145 23:09:56.540073 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10146 23:09:56.546677 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10147 23:09:56.553401 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10148 23:09:56.556693 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10149 23:09:56.566248 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10150 23:09:56.572766 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10151 23:09:56.579695 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10152 23:09:56.585880 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10153 23:09:56.589583 <6>[ 0.000000] GICv3: 608 SPIs implemented
10154 23:09:56.592879 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10155 23:09:56.599386 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10156 23:09:56.602652 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10157 23:09:56.608986 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10158 23:09:56.622480 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10159 23:09:56.635286 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10160 23:09:56.641876 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10161 23:09:56.650209 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10162 23:09:56.663609 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10163 23:09:56.670126 <6>[ 0.000001] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10164 23:09:56.676581 <6>[ 0.009176] Console: colour dummy device 80x25
10165 23:09:56.686585 <6>[ 0.013931] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10166 23:09:56.693177 <6>[ 0.024437] pid_max: default: 32768 minimum: 301
10167 23:09:56.696579 <6>[ 0.029308] LSM: Security Framework initializing
10168 23:09:56.702746 <6>[ 0.034223] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10169 23:09:56.713041 <6>[ 0.041870] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10170 23:09:56.719463 <6>[ 0.051110] cblist_init_generic: Setting adjustable number of callback queues.
10171 23:09:56.726263 <6>[ 0.058596] cblist_init_generic: Setting shift to 3 and lim to 1.
10172 23:09:56.736424 <6>[ 0.064934] cblist_init_generic: Setting adjustable number of callback queues.
10173 23:09:56.742802 <6>[ 0.072361] cblist_init_generic: Setting shift to 3 and lim to 1.
10174 23:09:56.746165 <6>[ 0.078760] rcu: Hierarchical SRCU implementation.
10175 23:09:56.752815 <6>[ 0.083776] rcu: Max phase no-delay instances is 1000.
10176 23:09:56.759533 <6>[ 0.090804] EFI services will not be available.
10177 23:09:56.762533 <6>[ 0.095792] smp: Bringing up secondary CPUs ...
10178 23:09:56.770913 <6>[ 0.100874] Detected VIPT I-cache on CPU1
10179 23:09:56.777229 <6>[ 0.100942] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10180 23:09:56.784139 <6>[ 0.100970] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10181 23:09:56.787470 <6>[ 0.101308] Detected VIPT I-cache on CPU2
10182 23:09:56.793847 <6>[ 0.101361] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10183 23:09:56.803706 <6>[ 0.101377] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10184 23:09:56.807119 <6>[ 0.101635] Detected VIPT I-cache on CPU3
10185 23:09:56.813595 <6>[ 0.101681] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10186 23:09:56.820218 <6>[ 0.101695] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10187 23:09:56.823494 <6>[ 0.101998] CPU features: detected: Spectre-v4
10188 23:09:56.830080 <6>[ 0.102005] CPU features: detected: Spectre-BHB
10189 23:09:56.833168 <6>[ 0.102009] Detected PIPT I-cache on CPU4
10190 23:09:56.840289 <6>[ 0.102066] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10191 23:09:56.846783 <6>[ 0.102083] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10192 23:09:56.853448 <6>[ 0.102373] Detected PIPT I-cache on CPU5
10193 23:09:56.860074 <6>[ 0.102434] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10194 23:09:56.866581 <6>[ 0.102450] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10195 23:09:56.869878 <6>[ 0.102729] Detected PIPT I-cache on CPU6
10196 23:09:56.876660 <6>[ 0.102790] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10197 23:09:56.883034 <6>[ 0.102807] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10198 23:09:56.889716 <6>[ 0.103106] Detected PIPT I-cache on CPU7
10199 23:09:56.896455 <6>[ 0.103170] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10200 23:09:56.902721 <6>[ 0.103186] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10201 23:09:56.906007 <6>[ 0.103233] smp: Brought up 1 node, 8 CPUs
10202 23:09:56.912786 <6>[ 0.244543] SMP: Total of 8 processors activated.
10203 23:09:56.915956 <6>[ 0.249494] CPU features: detected: 32-bit EL0 Support
10204 23:09:56.926054 <6>[ 0.254858] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10205 23:09:56.932563 <6>[ 0.263658] CPU features: detected: Common not Private translations
10206 23:09:56.939257 <6>[ 0.270134] CPU features: detected: CRC32 instructions
10207 23:09:56.942681 <6>[ 0.275485] CPU features: detected: RCpc load-acquire (LDAPR)
10208 23:09:56.949386 <6>[ 0.281445] CPU features: detected: LSE atomic instructions
10209 23:09:56.955356 <6>[ 0.287262] CPU features: detected: Privileged Access Never
10210 23:09:56.961994 <6>[ 0.293043] CPU features: detected: RAS Extension Support
10211 23:09:56.968862 <6>[ 0.298686] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10212 23:09:56.972022 <6>[ 0.305905] CPU: All CPU(s) started at EL2
10213 23:09:56.978495 <6>[ 0.310223] alternatives: applying system-wide alternatives
10214 23:09:56.987449 <6>[ 0.320162] devtmpfs: initialized
10215 23:09:57.002618 <6>[ 0.328361] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10216 23:09:57.008959 <6>[ 0.338320] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10217 23:09:57.015524 <6>[ 0.346574] pinctrl core: initialized pinctrl subsystem
10218 23:09:57.018954 <6>[ 0.353223] DMI not present or invalid.
10219 23:09:57.025616 <6>[ 0.357629] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10220 23:09:57.035698 <6>[ 0.364480] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
10221 23:09:57.041972 <6>[ 0.371927] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10222 23:09:57.051714 <6>[ 0.380017] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10223 23:09:57.055006 <6>[ 0.388173] audit: initializing netlink subsys (disabled)
10224 23:09:57.065010 <5>[ 0.393858] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10225 23:09:57.071429 <6>[ 0.394539] thermal_sys: Registered thermal governor 'step_wise'
10226 23:09:57.078284 <6>[ 0.401823] thermal_sys: Registered thermal governor 'power_allocator'
10227 23:09:57.081300 <6>[ 0.408073] cpuidle: using governor menu
10228 23:09:57.088133 <6>[ 0.419029] NET: Registered PF_QIPCRTR protocol family
10229 23:09:57.094770 <6>[ 0.424497] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10230 23:09:57.098182 <6>[ 0.431598] ASID allocator initialised with 32768 entries
10231 23:09:57.105237 <6>[ 0.438137] Serial: AMBA PL011 UART driver
10232 23:09:57.114023 <4>[ 0.446873] Trying to register duplicate clock ID: 134
10233 23:09:57.168549 <6>[ 0.504417] KASLR enabled
10234 23:09:57.183099 <6>[ 0.512104] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10235 23:09:57.189966 <6>[ 0.519118] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10236 23:09:57.196188 <6>[ 0.525610] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10237 23:09:57.202745 <6>[ 0.532614] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10238 23:09:57.209244 <6>[ 0.539103] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10239 23:09:57.215992 <6>[ 0.546104] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10240 23:09:57.222625 <6>[ 0.552592] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10241 23:09:57.229058 <6>[ 0.559598] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10242 23:09:57.232364 <6>[ 0.567102] ACPI: Interpreter disabled.
10243 23:09:57.240720 <6>[ 0.573504] iommu: Default domain type: Translated
10244 23:09:57.247681 <6>[ 0.578615] iommu: DMA domain TLB invalidation policy: strict mode
10245 23:09:57.250822 <5>[ 0.585274] SCSI subsystem initialized
10246 23:09:57.257437 <6>[ 0.589436] usbcore: registered new interface driver usbfs
10247 23:09:57.263725 <6>[ 0.595169] usbcore: registered new interface driver hub
10248 23:09:57.267316 <6>[ 0.600721] usbcore: registered new device driver usb
10249 23:09:57.274427 <6>[ 0.606820] pps_core: LinuxPPS API ver. 1 registered
10250 23:09:57.284198 <6>[ 0.612014] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10251 23:09:57.287574 <6>[ 0.621361] PTP clock support registered
10252 23:09:57.290472 <6>[ 0.625603] EDAC MC: Ver: 3.0.0
10253 23:09:57.298351 <6>[ 0.630757] FPGA manager framework
10254 23:09:57.304879 <6>[ 0.634437] Advanced Linux Sound Architecture Driver Initialized.
10255 23:09:57.307923 <6>[ 0.641203] vgaarb: loaded
10256 23:09:57.311542 <6>[ 0.644362] clocksource: Switched to clocksource arch_sys_counter
10257 23:09:57.318296 <5>[ 0.650803] VFS: Disk quotas dquot_6.6.0
10258 23:09:57.324899 <6>[ 0.654988] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10259 23:09:57.328083 <6>[ 0.662177] pnp: PnP ACPI: disabled
10260 23:09:57.336216 <6>[ 0.668820] NET: Registered PF_INET protocol family
10261 23:09:57.342905 <6>[ 0.674197] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
10262 23:09:57.354874 <6>[ 0.684192] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
10263 23:09:57.364683 <6>[ 0.692982] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10264 23:09:57.371487 <6>[ 0.700947] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
10265 23:09:57.377818 <6>[ 0.709350] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
10266 23:09:57.388696 <6>[ 0.718007] TCP: Hash tables configured (established 32768 bind 32768)
10267 23:09:57.395386 <6>[ 0.724866] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
10268 23:09:57.401868 <6>[ 0.731886] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
10269 23:09:57.408467 <6>[ 0.739409] NET: Registered PF_UNIX/PF_LOCAL protocol family
10270 23:09:57.415096 <6>[ 0.745496] RPC: Registered named UNIX socket transport module.
10271 23:09:57.418663 <6>[ 0.751649] RPC: Registered udp transport module.
10272 23:09:57.425308 <6>[ 0.756584] RPC: Registered tcp transport module.
10273 23:09:57.431886 <6>[ 0.761515] RPC: Registered tcp NFSv4.1 backchannel transport module.
10274 23:09:57.435109 <6>[ 0.768182] PCI: CLS 0 bytes, default 64
10275 23:09:57.438342 <6>[ 0.772596] Unpacking initramfs...
10276 23:09:57.448345 <6>[ 0.776283] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10277 23:09:57.454853 <6>[ 0.784925] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10278 23:09:57.461235 <6>[ 0.793768] kvm [1]: IPA Size Limit: 40 bits
10279 23:09:57.464907 <6>[ 0.798296] kvm [1]: GICv3: no GICV resource entry
10280 23:09:57.471284 <6>[ 0.803318] kvm [1]: disabling GICv2 emulation
10281 23:09:57.478063 <6>[ 0.808006] kvm [1]: GIC system register CPU interface enabled
10282 23:09:57.481233 <6>[ 0.814176] kvm [1]: vgic interrupt IRQ18
10283 23:09:57.487928 <6>[ 0.818543] kvm [1]: VHE mode initialized successfully
10284 23:09:57.491319 <5>[ 0.825009] Initialise system trusted keyrings
10285 23:09:57.497861 <6>[ 0.829836] workingset: timestamp_bits=42 max_order=20 bucket_order=0
10286 23:09:57.507334 <6>[ 0.840062] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10287 23:09:57.514091 <5>[ 0.846413] NFS: Registering the id_resolver key type
10288 23:09:57.517249 <5>[ 0.851710] Key type id_resolver registered
10289 23:09:57.524090 <5>[ 0.856126] Key type id_legacy registered
10290 23:09:57.530786 <6>[ 0.860406] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10291 23:09:57.537036 <6>[ 0.867329] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10292 23:09:57.543694 <6>[ 0.875048] 9p: Installing v9fs 9p2000 file system support
10293 23:09:57.580084 <5>[ 0.912762] Key type asymmetric registered
10294 23:09:57.583497 <5>[ 0.917096] Asymmetric key parser 'x509' registered
10295 23:09:57.593778 <6>[ 0.922261] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10296 23:09:57.596909 <6>[ 0.929875] io scheduler mq-deadline registered
10297 23:09:57.599790 <6>[ 0.934635] io scheduler kyber registered
10298 23:09:57.618952 <6>[ 0.951615] EINJ: ACPI disabled.
10299 23:09:57.651360 <4>[ 0.977076] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10300 23:09:57.661076 <4>[ 0.987706] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10301 23:09:57.676033 <6>[ 1.008421] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10302 23:09:57.683966 <6>[ 1.016435] printk: console [ttyS0] disabled
10303 23:09:57.711545 <6>[ 1.041075] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10304 23:09:57.718602 <6>[ 1.050549] printk: console [ttyS0] enabled
10305 23:09:57.721608 <6>[ 1.050549] printk: console [ttyS0] enabled
10306 23:09:57.728279 <6>[ 1.059445] printk: bootconsole [mtk8250] disabled
10307 23:09:57.731662 <6>[ 1.059445] printk: bootconsole [mtk8250] disabled
10308 23:09:57.738106 <6>[ 1.070692] SuperH (H)SCI(F) driver initialized
10309 23:09:57.741443 <6>[ 1.075968] msm_serial: driver initialized
10310 23:09:57.755491 <6>[ 1.084924] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10311 23:09:57.765362 <6>[ 1.093472] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10312 23:09:57.772009 <6>[ 1.102014] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10313 23:09:57.781939 <6>[ 1.110644] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10314 23:09:57.792087 <6>[ 1.119357] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10315 23:09:57.798435 <6>[ 1.128079] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10316 23:09:57.808608 <6>[ 1.136619] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10317 23:09:57.814956 <6>[ 1.145420] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10318 23:09:57.824890 <6>[ 1.153963] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10319 23:09:57.836812 <6>[ 1.169695] loop: module loaded
10320 23:09:57.843350 <6>[ 1.175693] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10321 23:09:57.865533 <4>[ 1.198378] mtk-pmic-keys: Failed to locate of_node [id: -1]
10322 23:09:57.872594 <6>[ 1.205211] megasas: 07.719.03.00-rc1
10323 23:09:57.881922 <6>[ 1.214682] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10324 23:09:57.891334 <6>[ 1.223751] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10325 23:09:57.907602 <6>[ 1.240345] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10326 23:09:57.963922 <6>[ 1.289909] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10327 23:09:59.471310 <6>[ 2.804008] Freeing initrd memory: 46420K
10328 23:09:59.481293 <6>[ 2.814249] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10329 23:09:59.492143 <6>[ 2.824884] tun: Universal TUN/TAP device driver, 1.6
10330 23:09:59.495406 <6>[ 2.830937] thunder_xcv, ver 1.0
10331 23:09:59.498716 <6>[ 2.834441] thunder_bgx, ver 1.0
10332 23:09:59.501661 <6>[ 2.837938] nicpf, ver 1.0
10333 23:09:59.512185 <6>[ 2.841947] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10334 23:09:59.515521 <6>[ 2.849423] hns3: Copyright (c) 2017 Huawei Corporation.
10335 23:09:59.522396 <6>[ 2.855012] hclge is initializing
10336 23:09:59.525809 <6>[ 2.858592] e1000: Intel(R) PRO/1000 Network Driver
10337 23:09:59.532361 <6>[ 2.863721] e1000: Copyright (c) 1999-2006 Intel Corporation.
10338 23:09:59.535940 <6>[ 2.869732] e1000e: Intel(R) PRO/1000 Network Driver
10339 23:09:59.542433 <6>[ 2.874947] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10340 23:09:59.549018 <6>[ 2.881131] igb: Intel(R) Gigabit Ethernet Network Driver
10341 23:09:59.555340 <6>[ 2.886781] igb: Copyright (c) 2007-2014 Intel Corporation.
10342 23:09:59.562218 <6>[ 2.892616] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10343 23:09:59.568670 <6>[ 2.899134] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10344 23:09:59.572086 <6>[ 2.905598] sky2: driver version 1.30
10345 23:09:59.578482 <6>[ 2.910578] VFIO - User Level meta-driver version: 0.3
10346 23:09:59.586379 <6>[ 2.918802] usbcore: registered new interface driver usb-storage
10347 23:09:59.592680 <6>[ 2.925248] usbcore: registered new device driver onboard-usb-hub
10348 23:09:59.601514 <6>[ 2.934374] mt6397-rtc mt6359-rtc: registered as rtc0
10349 23:09:59.611412 <6>[ 2.939842] mt6397-rtc mt6359-rtc: setting system clock to 2023-12-01T23:09:59 UTC (1701472199)
10350 23:09:59.614518 <6>[ 2.949397] i2c_dev: i2c /dev entries driver
10351 23:09:59.631493 <6>[ 2.961044] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10352 23:09:59.651098 <6>[ 2.984014] cpu cpu0: EM: created perf domain
10353 23:09:59.654419 <6>[ 2.988918] cpu cpu4: EM: created perf domain
10354 23:09:59.661511 <6>[ 2.994414] sdhci: Secure Digital Host Controller Interface driver
10355 23:09:59.668030 <6>[ 3.000847] sdhci: Copyright(c) Pierre Ossman
10356 23:09:59.675017 <6>[ 3.005751] Synopsys Designware Multimedia Card Interface Driver
10357 23:09:59.681881 <6>[ 3.012337] sdhci-pltfm: SDHCI platform and OF driver helper
10358 23:09:59.684681 <6>[ 3.012493] mmc0: CQHCI version 5.10
10359 23:09:59.691173 <6>[ 3.022394] ledtrig-cpu: registered to indicate activity on CPUs
10360 23:09:59.697915 <6>[ 3.029409] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10361 23:09:59.704345 <6>[ 3.036432] usbcore: registered new interface driver usbhid
10362 23:09:59.707736 <6>[ 3.042253] usbhid: USB HID core driver
10363 23:09:59.714080 <6>[ 3.046449] spi_master spi0: will run message pump with realtime priority
10364 23:09:59.761028 <6>[ 3.087305] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10365 23:09:59.779262 <6>[ 3.102394] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10366 23:09:59.782924 <6>[ 3.115998] mmc0: Command Queue Engine enabled
10367 23:09:59.789415 <6>[ 3.120801] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10368 23:09:59.796164 <6>[ 3.128076] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10369 23:09:59.799518 <6>[ 3.133109] cros-ec-spi spi0.0: Chrome EC device registered
10370 23:09:59.806044 <6>[ 3.136875] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10371 23:09:59.813370 <6>[ 3.146513] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10372 23:09:59.820579 <6>[ 3.152606] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10373 23:09:59.826882 <6>[ 3.158522] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10374 23:09:59.843774 <6>[ 3.173323] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10375 23:09:59.850761 <6>[ 3.183677] NET: Registered PF_PACKET protocol family
10376 23:09:59.857434 <6>[ 3.189074] 9pnet: Installing 9P2000 support
10377 23:09:59.860689 <5>[ 3.193638] Key type dns_resolver registered
10378 23:09:59.864076 <6>[ 3.198604] registered taskstats version 1
10379 23:09:59.870322 <5>[ 3.202989] Loading compiled-in X.509 certificates
10380 23:09:59.900058 <4>[ 3.226116] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10381 23:09:59.909909 <4>[ 3.236838] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10382 23:09:59.916410 <3>[ 3.247416] debugfs: File 'uA_load' in directory '/' already present!
10383 23:09:59.923049 <3>[ 3.254122] debugfs: File 'min_uV' in directory '/' already present!
10384 23:09:59.930113 <3>[ 3.260732] debugfs: File 'max_uV' in directory '/' already present!
10385 23:09:59.936623 <3>[ 3.267338] debugfs: File 'constraint_flags' in directory '/' already present!
10386 23:09:59.947074 <3>[ 3.276688] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10387 23:09:59.956240 <6>[ 3.289041] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10388 23:09:59.962959 <6>[ 3.295795] xhci-mtk 11200000.usb: xHCI Host Controller
10389 23:09:59.969237 <6>[ 3.301297] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10390 23:09:59.979562 <6>[ 3.309139] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10391 23:09:59.986228 <6>[ 3.318558] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10392 23:09:59.992788 <6>[ 3.324624] xhci-mtk 11200000.usb: xHCI Host Controller
10393 23:09:59.999371 <6>[ 3.330098] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10394 23:10:00.006254 <6>[ 3.337748] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10395 23:10:00.012260 <6>[ 3.345548] hub 1-0:1.0: USB hub found
10396 23:10:00.015803 <6>[ 3.349568] hub 1-0:1.0: 1 port detected
10397 23:10:00.025679 <6>[ 3.353841] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10398 23:10:00.029124 <6>[ 3.362559] hub 2-0:1.0: USB hub found
10399 23:10:00.031993 <6>[ 3.366577] hub 2-0:1.0: 1 port detected
10400 23:10:00.041057 <6>[ 3.373985] mtk-msdc 11f70000.mmc: Got CD GPIO
10401 23:10:00.057185 <6>[ 3.386364] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10402 23:10:00.063494 <6>[ 3.394398] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10403 23:10:00.073250 <4>[ 3.402370] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10404 23:10:00.083313 <6>[ 3.411899] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10405 23:10:00.089820 <6>[ 3.419999] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10406 23:10:00.096410 <6>[ 3.428016] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10407 23:10:00.106496 <6>[ 3.435940] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10408 23:10:00.112758 <6>[ 3.443758] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10409 23:10:00.122871 <6>[ 3.451585] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10410 23:10:00.133048 <6>[ 3.461797] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10411 23:10:00.139398 <6>[ 3.470174] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10412 23:10:00.149698 <6>[ 3.478517] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10413 23:10:00.156042 <6>[ 3.486866] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10414 23:10:00.166044 <6>[ 3.495205] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10415 23:10:00.172732 <6>[ 3.503555] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10416 23:10:00.182622 <6>[ 3.511895] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10417 23:10:00.192194 <6>[ 3.520244] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10418 23:10:00.199223 <6>[ 3.528583] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10419 23:10:00.208853 <6>[ 3.536930] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10420 23:10:00.215221 <6>[ 3.545272] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10421 23:10:00.225648 <6>[ 3.553611] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10422 23:10:00.232050 <6>[ 3.561951] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10423 23:10:00.241945 <6>[ 3.570289] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10424 23:10:00.248474 <6>[ 3.578627] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10425 23:10:00.254996 <6>[ 3.587337] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10426 23:10:00.261802 <6>[ 3.594442] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10427 23:10:00.268621 <6>[ 3.601187] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10428 23:10:00.278377 <6>[ 3.607922] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10429 23:10:00.284931 <6>[ 3.614849] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10430 23:10:00.291438 <6>[ 3.621689] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10431 23:10:00.301216 <6>[ 3.630815] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10432 23:10:00.310978 <6>[ 3.639933] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10433 23:10:00.321214 <6>[ 3.649245] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10434 23:10:00.331050 <6>[ 3.658721] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10435 23:10:00.341168 <6>[ 3.668187] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10436 23:10:00.347848 <6>[ 3.677306] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10437 23:10:00.357579 <6>[ 3.686773] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10438 23:10:00.367286 <6>[ 3.695890] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10439 23:10:00.377354 <6>[ 3.705183] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10440 23:10:00.387224 <6>[ 3.715343] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10441 23:10:00.397388 <6>[ 3.726879] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10442 23:10:00.422712 <6>[ 3.752657] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10443 23:10:00.450592 <6>[ 3.783377] hub 2-1:1.0: USB hub found
10444 23:10:00.453674 <6>[ 3.787798] hub 2-1:1.0: 3 ports detected
10445 23:10:00.461796 <6>[ 3.794577] hub 2-1:1.0: USB hub found
10446 23:10:00.464925 <6>[ 3.799037] hub 2-1:1.0: 3 ports detected
10447 23:10:00.574793 <6>[ 3.904649] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10448 23:10:00.729471 <6>[ 4.062513] hub 1-1:1.0: USB hub found
10449 23:10:00.732703 <6>[ 4.066976] hub 1-1:1.0: 4 ports detected
10450 23:10:00.742317 <6>[ 4.075296] hub 1-1:1.0: USB hub found
10451 23:10:00.745572 <6>[ 4.079829] hub 1-1:1.0: 4 ports detected
10452 23:10:00.814734 <6>[ 4.144701] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10453 23:10:01.067105 <6>[ 4.396736] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10454 23:10:01.199671 <6>[ 4.532510] hub 1-1.4:1.0: USB hub found
10455 23:10:01.202616 <6>[ 4.537169] hub 1-1.4:1.0: 2 ports detected
10456 23:10:01.212500 <6>[ 4.545200] hub 1-1.4:1.0: USB hub found
10457 23:10:01.215304 <6>[ 4.549802] hub 1-1.4:1.0: 2 ports detected
10458 23:10:01.510809 <6>[ 4.840642] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10459 23:10:01.702821 <6>[ 5.032644] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10460 23:10:12.675923 <6>[ 16.013556] ALSA device list:
10461 23:10:12.682475 <6>[ 16.016848] No soundcards found.
10462 23:10:12.689908 <6>[ 16.023981] Freeing unused kernel memory: 8448K
10463 23:10:12.692751 <6>[ 16.029019] Run /init as init process
10464 23:10:12.740758 <6>[ 16.075080] NET: Registered PF_INET6 protocol family
10465 23:10:12.747289 <6>[ 16.081219] Segment Routing with IPv6
10466 23:10:12.750558 <6>[ 16.085154] In-situ OAM (IOAM) with IPv6
10467 23:10:12.786444 <30>[ 16.101095] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10468 23:10:12.789714 <30>[ 16.125001] systemd[1]: Detected architecture arm64.
10469 23:10:12.793104
10470 23:10:12.796301 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10471 23:10:12.796932
10472 23:10:12.810520 <30>[ 16.144832] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10473 23:10:12.931240 <30>[ 16.262264] systemd[1]: Queued start job for default target Graphical Interface.
10474 23:10:12.958519 <30>[ 16.293042] systemd[1]: Created slice system-getty.slice.
10475 23:10:12.965121 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10476 23:10:12.982594 <30>[ 16.316803] systemd[1]: Created slice system-modprobe.slice.
10477 23:10:12.989028 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10478 23:10:13.007013 <30>[ 16.341166] systemd[1]: Created slice system-serial\x2dgetty.slice.
10479 23:10:13.017010 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10480 23:10:13.030483 <30>[ 16.364976] systemd[1]: Created slice User and Session Slice.
10481 23:10:13.037040 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10482 23:10:13.058455 <30>[ 16.389409] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10483 23:10:13.068120 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10484 23:10:13.086063 <30>[ 16.417073] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10485 23:10:13.092473 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10486 23:10:13.112657 <30>[ 16.440615] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10487 23:10:13.119440 <30>[ 16.452707] systemd[1]: Reached target Local Encrypted Volumes.
10488 23:10:13.125862 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10489 23:10:13.142580 <30>[ 16.477066] systemd[1]: Reached target Paths.
10490 23:10:13.145935 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10491 23:10:13.162389 <30>[ 16.496617] systemd[1]: Reached target Remote File Systems.
10492 23:10:13.168481 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10493 23:10:13.182459 <30>[ 16.516604] systemd[1]: Reached target Slices.
10494 23:10:13.185325 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10495 23:10:13.202278 <30>[ 16.536644] systemd[1]: Reached target Swap.
10496 23:10:13.205540 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10497 23:10:13.225960 <30>[ 16.557086] systemd[1]: Listening on initctl Compatibility Named Pipe.
10498 23:10:13.232605 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10499 23:10:13.247943 <30>[ 16.581938] systemd[1]: Listening on Journal Audit Socket.
10500 23:10:13.253893 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10501 23:10:13.271050 <30>[ 16.605642] systemd[1]: Listening on Journal Socket (/dev/log).
10502 23:10:13.277513 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10503 23:10:13.295404 <30>[ 16.629731] systemd[1]: Listening on Journal Socket.
10504 23:10:13.301551 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10505 23:10:13.318337 <30>[ 16.649306] systemd[1]: Listening on Network Service Netlink Socket.
10506 23:10:13.324855 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10507 23:10:13.339292 <30>[ 16.673719] systemd[1]: Listening on udev Control Socket.
10508 23:10:13.345877 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10509 23:10:13.363174 <30>[ 16.697571] systemd[1]: Listening on udev Kernel Socket.
10510 23:10:13.369827 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10511 23:10:13.422444 <30>[ 16.756842] systemd[1]: Mounting Huge Pages File System...
10512 23:10:13.429180 Mounting [0;1;39mHuge Pages File System[0m...
10513 23:10:13.445880 <30>[ 16.780570] systemd[1]: Mounting POSIX Message Queue File System...
10514 23:10:13.452392 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10515 23:10:13.490297 <30>[ 16.824665] systemd[1]: Mounting Kernel Debug File System...
10516 23:10:13.496764 Mounting [0;1;39mKernel Debug File System[0m...
10517 23:10:13.513728 <30>[ 16.845031] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10518 23:10:13.526809 <30>[ 16.857927] systemd[1]: Starting Create list of static device nodes for the current kernel...
10519 23:10:13.533389 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10520 23:10:13.554347 <30>[ 16.888930] systemd[1]: Starting Load Kernel Module configfs...
10521 23:10:13.560954 Starting [0;1;39mLoad Kernel Module configfs[0m...
10522 23:10:13.578473 <30>[ 16.912743] systemd[1]: Starting Load Kernel Module drm...
10523 23:10:13.584940 Starting [0;1;39mLoad Kernel Module drm[0m...
10524 23:10:13.601682 <30>[ 16.932817] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10525 23:10:13.615529 <30>[ 16.950021] systemd[1]: Starting Journal Service...
10526 23:10:13.618555 Starting [0;1;39mJournal Service[0m...
10527 23:10:13.635813 <30>[ 16.970356] systemd[1]: Starting Load Kernel Modules...
10528 23:10:13.642242 Starting [0;1;39mLoad Kernel Modules[0m...
10529 23:10:13.660837 <30>[ 16.992044] systemd[1]: Starting Remount Root and Kernel File Systems...
10530 23:10:13.667597 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10531 23:10:13.686182 <30>[ 17.020624] systemd[1]: Starting Coldplug All udev Devices...
10532 23:10:13.692763 Starting [0;1;39mColdplug All udev Devices[0m...
10533 23:10:13.708901 <30>[ 17.043169] systemd[1]: Started Journal Service.
10534 23:10:13.715542 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10535 23:10:13.732062 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10536 23:10:13.746511 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10537 23:10:13.762453 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10538 23:10:13.782403 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10539 23:10:13.800882 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10540 23:10:13.820724 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10541 23:10:13.840121 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10542 23:10:13.860194 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10543 23:10:13.874420 See 'systemctl status systemd-remount-fs.service' for details.
10544 23:10:13.914978 Mounting [0;1;39mKernel Configuration File System[0m...
10545 23:10:13.932389 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10546 23:10:13.942273 <46>[ 17.273365] systemd-journald[185]: Received client request to flush runtime journal.
10547 23:10:13.949476 Starting [0;1;39mLoad/Save Random Seed[0m...
10548 23:10:13.964699 Starting [0;1;39mApply Kernel Variables[0m...
10549 23:10:13.984956 Starting [0;1;39mCreate System Users[0m...
10550 23:10:14.001191 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10551 23:10:14.019576 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10552 23:10:14.043355 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10553 23:10:14.056089 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10554 23:10:14.072079 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10555 23:10:14.087049 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10556 23:10:14.139542 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10557 23:10:14.162208 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10558 23:10:14.178407 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10559 23:10:14.194383 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10560 23:10:14.234571 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10561 23:10:14.264673 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10562 23:10:14.282915 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10563 23:10:14.302423 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10564 23:10:14.334590 Starting [0;1;39mNetwork Service[0m...
10565 23:10:14.353334 Starting [0;1;39mNetwork Time Synchronization[0m...
10566 23:10:14.371937 <6>[ 17.703273] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10567 23:10:14.381917 <6>[ 17.712212] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10568 23:10:14.391970 <6>[ 17.721738] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10569 23:10:14.395300 <6>[ 17.721996] usbcore: registered new interface driver r8152
10570 23:10:14.413145 <4>[ 17.744112] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10571 23:10:14.422964 <4>[ 17.754413] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10572 23:10:14.426301 <6>[ 17.760519] mc: Linux media interface: v0.10
10573 23:10:14.433188 <6>[ 17.766500] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10574 23:10:14.446143 Starting [0;1;39mUpdat<3>[ 17.776014] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10575 23:10:14.452709 e UTMP about Sys<6>[ 17.776839] remoteproc remoteproc0: scp is available
10576 23:10:14.462572 tem Boot/Shutdow<3>[ 17.784983] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10577 23:10:14.463117 n[0m...
10578 23:10:14.465916 <6>[ 17.791496] remoteproc remoteproc0: powering up scp
10579 23:10:14.475913 <3>[ 17.800953] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10580 23:10:14.482477 <6>[ 17.806908] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10581 23:10:14.492609 <6>[ 17.809932] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10582 23:10:14.495911 <6>[ 17.811849] videodev: Linux video capture interface: v2.00
10583 23:10:14.506032 <3>[ 17.815566] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10584 23:10:14.509253 <6>[ 17.823421] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10585 23:10:14.519714 <6>[ 17.823628] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10586 23:10:14.525984 <3>[ 17.831059] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10587 23:10:14.536262 <4>[ 17.833032] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10588 23:10:14.539220 <4>[ 17.833032] Fallback method does not support PEC.
10589 23:10:14.549738 <3>[ 17.850269] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10590 23:10:14.555721 <3>[ 17.850542] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10591 23:10:14.562859 <6>[ 17.853918] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10592 23:10:14.569837 <6>[ 17.853943] pci_bus 0000:00: root bus resource [bus 00-ff]
10593 23:10:14.576310 <6>[ 17.853949] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10594 23:10:14.586500 <6>[ 17.853954] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10595 23:10:14.593079 <6>[ 17.854028] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10596 23:10:14.599588 <6>[ 17.854099] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10597 23:10:14.602770 <6>[ 17.854377] pci 0000:00:00.0: supports D1 D2
10598 23:10:14.613066 <6>[ 17.854380] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10599 23:10:14.620041 <6>[ 17.856182] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10600 23:10:14.627031 <6>[ 17.856326] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10601 23:10:14.633974 <6>[ 17.856380] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10602 23:10:14.640574 <6>[ 17.856411] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10603 23:10:14.647774 <6>[ 17.856430] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10604 23:10:14.651255 <6>[ 17.856548] pci 0000:01:00.0: supports D1 D2
10605 23:10:14.660845 <6>[ 17.856552] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10606 23:10:14.667710 <6>[ 17.869062] r8152 2-1.3:1.0: load rtl8153b-2 v1 10/23/19 successfully
10607 23:10:14.675217 <6>[ 17.869290] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10608 23:10:14.681471 <6>[ 17.869305] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10609 23:10:14.688418 <6>[ 17.869308] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10610 23:10:14.698703 <6>[ 17.869316] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10611 23:10:14.705446 <6>[ 17.869328] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10612 23:10:14.712373 <6>[ 17.869341] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10613 23:10:14.719134 <6>[ 17.869352] pci 0000:00:00.0: PCI bridge to [bus 01]
10614 23:10:14.725803 <6>[ 17.869357] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10615 23:10:14.732554 <6>[ 17.869472] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10616 23:10:14.739131 <6>[ 17.870211] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10617 23:10:14.745508 <6>[ 17.870346] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10618 23:10:14.755986 <6>[ 17.879057] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10619 23:10:14.762751 <3>[ 17.879396] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10620 23:10:14.772864 <6>[ 17.896912] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10621 23:10:14.780287 <3>[ 17.903111] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10622 23:10:14.790166 <6>[ 17.909113] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10623 23:10:14.797214 <3>[ 17.909712] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10624 23:10:14.806932 <3>[ 17.915982] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10625 23:10:14.813848 <3>[ 17.920485] power_supply sbs-5-000b: driver failed to report `capacity' property: -6
10626 23:10:14.817408 <6>[ 17.940223] Bluetooth: Core ver 2.22
10627 23:10:14.824060 <6>[ 17.940292] usbcore: registered new interface driver cdc_ether
10628 23:10:14.833868 <3>[ 17.944131] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10629 23:10:14.837156 <6>[ 17.944350] r8152 2-1.3:1.0 eth0: v1.12.13
10630 23:10:14.844014 <5>[ 17.946169] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10631 23:10:14.850344 <6>[ 17.951010] NET: Registered PF_BLUETOOTH protocol family
10632 23:10:14.856982 <6>[ 17.951399] usbcore: registered new interface driver r8153_ecm
10633 23:10:14.863484 <5>[ 17.957520] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10634 23:10:14.873246 <4>[ 17.957555] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10635 23:10:14.876483 <6>[ 17.957559] cfg80211: failed to load regulatory.db
10636 23:10:14.883564 <3>[ 17.959225] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10637 23:10:14.893183 <6>[ 17.962385] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10638 23:10:14.896307 <6>[ 17.964095] r8152 2-1.3:1.0 enx00e04c6803bd: renamed from eth0
10639 23:10:14.903320 <6>[ 17.965479] Bluetooth: HCI device and connection manager initialized
10640 23:10:14.913178 <6>[ 17.965485] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10641 23:10:14.919694 <6>[ 17.965490] remoteproc remoteproc0: remote processor scp is now up
10642 23:10:14.929535 <3>[ 17.972526] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10643 23:10:14.936365 <3>[ 17.972948] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10644 23:10:14.945904 <3>[ 17.973218] power_supply sbs-5-000b: driver failed to report `voltage_now' property: -6
10645 23:10:14.949032 <6>[ 17.980422] Bluetooth: HCI socket layer initialized
10646 23:10:14.959106 <6>[ 17.981611] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10647 23:10:14.965752 <6>[ 17.982697] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10648 23:10:14.976056 <3>[ 17.987914] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10649 23:10:14.982062 <3>[ 17.990105] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10650 23:10:14.992344 <3>[ 17.991043] power_supply sbs-5-000b: driver failed to report `health' property: -6
10651 23:10:14.995536 <6>[ 17.992407] Bluetooth: L2CAP socket layer initialized
10652 23:10:15.002000 <6>[ 17.993189] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10653 23:10:15.015392 <6>[ 17.994277] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10654 23:10:15.021922 <6>[ 17.994402] usbcore: registered new interface driver uvcvideo
10655 23:10:15.028790 <3>[ 17.999270] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10656 23:10:15.035094 <6>[ 18.005962] Bluetooth: SCO socket layer initialized
10657 23:10:15.041709 <3>[ 18.012822] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10658 23:10:15.051597 <3>[ 18.013030] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10659 23:10:15.058115 <6>[ 18.021379] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10660 23:10:15.064865 <3>[ 18.028889] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10661 23:10:15.075085 <3>[ 18.032765] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10662 23:10:15.084399 <3>[ 18.054653] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10663 23:10:15.091278 <3>[ 18.058069] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10664 23:10:15.101145 <3>[ 18.058084] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10665 23:10:15.104344 <6>[ 18.072760] usbcore: registered new interface driver btusb
10666 23:10:15.117565 <4>[ 18.073532] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10667 23:10:15.120976 <3>[ 18.073537] Bluetooth: hci0: Failed to load firmware file (-2)
10668 23:10:15.127359 <3>[ 18.073539] Bluetooth: hci0: Failed to set up firmware (-2)
10669 23:10:15.137379 <4>[ 18.073540] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10670 23:10:15.143706 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10671 23:10:15.164780 <6>[ 18.496145] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10672 23:10:15.171714 <6>[ 18.503615] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10673 23:10:15.177880 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10674 23:10:15.193906 <6>[ 18.528483] mt7921e 0000:01:00.0: ASIC revision: 79610010
10675 23:10:15.235048 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10676 23:10:15.259452 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10677 23:10:15.293371 <4>[ 18.621402] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10678 23:10:15.379263 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10679 23:10:15.398670 <4>[ 18.726680] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10680 23:10:15.405201 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10681 23:10:15.418247 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10682 23:10:15.438543 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10683 23:10:15.461381 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10684 23:10:15.505478 Startin<4>[ 18.834583] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10685 23:10:15.512143 g [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10686 23:10:15.533445 Starting [0;1;39mNetwork Name Resolution[0m...
10687 23:10:15.554524 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10688 23:10:15.570909 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10689 23:10:15.589834 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10690 23:10:15.615709 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.<4>[ 18.942931] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10691 23:10:15.616287
10692 23:10:15.634589 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10693 23:10:15.654144 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10694 23:10:15.666091 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10695 23:10:15.682641 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10696 23:10:15.726837 <4>[ 19.054894] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10697 23:10:15.733157 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10698 23:10:15.768461 Starting [0;1;39mUser Login Management[0m...
10699 23:10:15.785577 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10700 23:10:15.804337 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10701 23:10:15.833142 [[0;32m OK [0m] Started [0;<4>[ 19.160608] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10702 23:10:15.836393 1;39mLoad/Save RF Kill Switch Status[0m.
10703 23:10:15.851605 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10704 23:10:15.869320 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10705 23:10:15.914740 Starting [0;1;39mPermit User Sessions[0m...
10706 23:10:15.942692 [[0;32m OK [0m] Finished [0;1;39mPermit Use<4>[ 19.270989] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10707 23:10:15.945638 r Sessions[0m.
10708 23:10:15.963357 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10709 23:10:16.007448 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10710 23:10:16.054893 <4>[ 19.382915] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10711 23:10:16.063443 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10712 23:10:16.079651 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10713 23:10:16.095079 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10714 23:10:16.110807 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10715 23:10:16.162810 <4>[ 19.491007] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10716 23:10:16.169436 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10717 23:10:16.207514 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10718 23:10:16.243207 <6>[ 19.574515] IPv6: ADDRCONF(NETDEV_CHANGE): enx00e04c6803bd: link becomes ready
10719 23:10:16.249573 <6>[ 19.582462] r8152 2-1.3:1.0 enx00e04c6803bd: carrier on
10720 23:10:16.250135
10721 23:10:16.250594
10722 23:10:16.256303 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10723 23:10:16.256956
10724 23:10:16.259443 debian-bullseye-arm64 login: root (automatic login)
10725 23:10:16.260003
10726 23:10:16.260371
10727 23:10:16.275203 Linux debian-bul<4>[ 19.604260] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10728 23:10:16.281956 lseye-arm64 6.1.64-cip10 #1 SMP PREEMPT Fri Dec 1 22:47:09 UTC 2023 aarch64
10729 23:10:16.282522
10730 23:10:16.288470 The programs included with the Debian GNU/Linux system are free software;
10731 23:10:16.295258 the exact distribution terms for each program are described in the
10732 23:10:16.301833 individual files in /usr/share/doc/*/copyright.
10733 23:10:16.302389
10734 23:10:16.305125 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10735 23:10:16.308239 permitted by applicable law.
10736 23:10:16.309987 Matched prompt #10: / #
10738 23:10:16.311087 Setting prompt string to ['/ #']
10739 23:10:16.311585 end: 2.2.5.1 login-action (duration 00:00:20) [common]
10741 23:10:16.312681 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
10742 23:10:16.313167 start: 2.2.6 expect-shell-connection (timeout 00:03:25) [common]
10743 23:10:16.313571 Setting prompt string to ['/ #']
10744 23:10:16.314125 Forcing a shell prompt, looking for ['/ #']
10746 23:10:16.365032 / #
10747 23:10:16.365893 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10748 23:10:16.366389 Waiting using forced prompt support (timeout 00:02:30)
10749 23:10:16.371513
10750 23:10:16.372451 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10751 23:10:16.373025 start: 2.2.7 export-device-env (timeout 00:03:25) [common]
10752 23:10:16.373534 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10753 23:10:16.374001 end: 2.2 depthcharge-retry (duration 00:01:35) [common]
10754 23:10:16.374478 end: 2 depthcharge-action (duration 00:01:35) [common]
10755 23:10:16.374972 start: 3 lava-test-retry (timeout 00:05:00) [common]
10756 23:10:16.375441 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
10757 23:10:16.375851 Using namespace: common
10759 23:10:16.477313 / # #
10760 23:10:16.478125 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
10761 23:10:16.478749 <3>[ 19.713244] mt7921e 0000:01:00.0: hardware init failed
10762 23:10:16.483803 #
10763 23:10:16.484690 Using /lava-12154449
10765 23:10:16.586110 / # export SHELL=/bin/sh
10766 23:10:16.592770 export SHELL=/bin/sh
10768 23:10:16.694729 / # . /lava-12154449/environment
10769 23:10:16.701335 . /lava-12154449/environment
10771 23:10:16.803113 / # /lava-12154449/bin/lava-test-runner /lava-12154449/0
10772 23:10:16.803833 Test shell timeout: 10s (minimum of the action and connection timeout)
10773 23:10:16.809627 /lava-12154449/bin/lava-test-runner /lava-12154449/0
10774 23:10:16.826044 + export TESTRUN_ID=0_cros-ec
10775 23:10:16.832584 +<8>[ 20.166104] <LAVA_SIGNAL_STARTRUN 0_cros-ec 12154449_1.5.2.3.1>
10776 23:10:16.833350 Received signal: <STARTRUN> 0_cros-ec 12154449_1.5.2.3.1
10777 23:10:16.833756 Starting test lava.0_cros-ec (12154449_1.5.2.3.1)
10778 23:10:16.834206 Skipping test definition patterns.
10779 23:10:16.836013 cd /lava-12154449/0/tests/0_cros-ec
10780 23:10:16.839449 + cat uuid
10781 23:10:16.840035 + UUID=12154449_1.5.2.3.1
10782 23:10:16.840412 + set +x
10783 23:10:16.845934 + python3 -m cros.runners.lava_runner -v
10784 23:10:17.123342 test_cros_ec_accel_iio_abi (cros.tests.cros_ec_accel.TestCrosECAccel)
10785 23:10:17.129978 Checks the cros-ec accelerometer IIO ABI. ... skipped 'No cros-ec-accel found'
10786 23:10:17.133473
10787 23:10:17.136940 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip
10789 23:10:17.140067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip>
10790 23:10:17.146369 test_cros_e<8>[ 20.478763] <LAVA_SIGNAL_ENDRUN 0_cros-ec 12154449_1.5.2.3.1>
10791 23:10:17.147215 Received signal: <ENDRUN> 0_cros-ec 12154449_1.5.2.3.1
10792 23:10:17.147670 Ending use of test pattern.
10793 23:10:17.148021 Ending test lava.0_cros-ec (12154449_1.5.2.3.1), duration 0.31
10795 23:10:17.149663 c_accel_iio_data_is_valid (cros.tests.cros_ec_accel.TestCrosECAccel)
10796 23:10:17.159871 Validates accelerometer data by computing the magnitude. If the ... skipped 'No accelerometer found'
10797 23:10:17.160441
10798 23:10:17.165878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=skip>
10799 23:10:17.166702 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=skip
10801 23:10:17.172887 test_cros_ec_gyro_iio_abi (cros.tests.cros_ec_gyro.TestCrosECGyro)
10802 23:10:17.179397 Checks the cros-ec gyroscope IIO ABI. ... skipped 'No cros-ec-gyro found'
10803 23:10:17.179960
10804 23:10:17.185806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip>
10805 23:10:17.186540 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip
10807 23:10:17.193002 test_cros_ec_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
10808 23:10:17.199587 Checks the standard ABI for the main Embedded Controller. ... ok
10809 23:10:17.200146
10810 23:10:17.202650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_abi RESULT=pass>
10811 23:10:17.203493 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_abi RESULT=pass
10813 23:10:17.209220 test_cros_ec_chardev (cros.tests.cros_ec_mcu.TestCrosECMCU)
10814 23:10:17.215895 Checks the main Embedded controller character device. ... ok
10815 23:10:17.216458
10816 23:10:17.219130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_chardev RESULT=pass>
10817 23:10:17.219975 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_chardev RESULT=pass
10819 23:10:17.225685 test_cros_ec_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
10820 23:10:17.232311 Checks basic comunication with the main Embedded controller. ... ok
10821 23:10:17.232916
10822 23:10:17.238839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_hello RESULT=pass>
10823 23:10:17.239683 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_hello RESULT=pass
10825 23:10:17.242207 test_cros_fp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
10826 23:10:17.248908 Checks the standard ABI for the Fingerprint EC. ... skipped 'MCU cros_fp not supported'
10827 23:10:17.251918
10828 23:10:17.255560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_abi RESULT=skip>
10829 23:10:17.256419 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_abi RESULT=skip
10831 23:10:17.262481 test_cros_fp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
10832 23:10:17.268453 Checks basic comunication with the fingerprint controller. ... skipped 'MCU cros_fp not found'
10833 23:10:17.269067
10834 23:10:17.275088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_hello RESULT=skip>
10835 23:10:17.275928 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_hello RESULT=skip
10837 23:10:17.281557 test_cros_fp_reboot (cros.tests.cros_ec_mcu.TestCrosECMCU)
10838 23:10:17.288840 Test reboot command on Fingerprint MCU. ... skipped 'MCU cros_fp not found'
10839 23:10:17.289516
10840 23:10:17.294767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_reboot RESULT=skip>
10841 23:10:17.295615 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_reboot RESULT=skip
10843 23:10:17.298386 test_cros_pd_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
10844 23:10:17.308204 Checks the standard ABI for the Power Delivery EC. ... skipped 'MCU cros_pd not supported'
10845 23:10:17.308811
10846 23:10:17.311463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_abi RESULT=skip>
10847 23:10:17.312307 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_abi RESULT=skip
10849 23:10:17.317981 test_cros_pd_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
10850 23:10:17.328128 Checks basic comunication with the power delivery controller. ... skipped 'MCU cros_pd not found'
10851 23:10:17.328736
10852 23:10:17.331174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_hello RESULT=skip>
10853 23:10:17.332023 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_hello RESULT=skip
10855 23:10:17.337853 test_cros_tp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
10856 23:10:17.344224 Checks the standard ABI for the Touchpad EC. ... skipped 'MCU cros_tp not supported'
10857 23:10:17.344967
10858 23:10:17.351039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_abi RESULT=skip>
10859 23:10:17.351881 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_abi RESULT=skip
10861 23:10:17.354297 test_cros_tp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
10862 23:10:17.364166 Checks basic comunication with the touchpad controller. ... skipped 'MCU cros_tp not found'
10863 23:10:17.364781
10864 23:10:17.370757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_hello RESULT=skip>
10865 23:10:17.371499 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_hello RESULT=skip
10867 23:10:17.374183 test_cros_ec_pwm_backlight (cros.tests.cros_ec_pwm.TestCrosECPWM)
10868 23:10:17.383960 Check that the backlight is connected to a pwm of the EC and that ... skipped 'No backlight pwm found'
10869 23:10:17.384574
10870 23:10:17.390548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip>
10871 23:10:17.391438 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip
10873 23:10:17.397130 test_cros_ec_battery_abi (cros.tests.cros_ec_power.TestCrosECPower)
10874 23:10:17.403867 Check the cros battery ABI. ... skipped 'No BAT found'
10875 23:10:17.404419
10876 23:10:17.410265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip>
10877 23:10:17.411087 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip
10879 23:10:17.417121 test_cros_ec_usbpd_charger_abi (cros.tests.cros_ec_power.TestCrosECPower)
10880 23:10:17.423494 Check the cros USBPD charger ABI. ... skipped 'No CROS_USBPD_CHARGER found'
10881 23:10:17.424061
10882 23:10:17.430493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip>
10883 23:10:17.431339 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip
10885 23:10:17.433434 test_cros_ec_rtc_abi (cros.tests.cros_ec_rtc.TestCrosECRTC)
10886 23:10:17.440206 Check the cros RTC ABI. ... skipped 'EC_FEATURE_RTC not supported, skipping'
10887 23:10:17.440802
10888 23:10:17.446819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip>
10889 23:10:17.447673 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip
10891 23:10:17.453091 test_cros_ec_extcon_usbc_abi (cros.tests.cros_ec_extcon.TestCrosECextcon)
10892 23:10:17.459870 Checks the cros-ec extcon ABI. ... skipped 'No extcon device found'
10893 23:10:17.460442
10894 23:10:17.466503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip>
10895 23:10:17.467102
10896 23:10:17.467751 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip
10898 23:10:17.472929 ----------------------------------------------------------------------
10899 23:10:17.476287 Ran 18 tests in 0.005s
10900 23:10:17.476891
10901 23:10:17.477266 OK (skipped=15)
10902 23:10:17.479496 + set +x
10903 23:10:17.479963 <LAVA_TEST_RUNNER EXIT>
10904 23:10:17.480635 ok: lava_test_shell seems to have completed
10905 23:10:17.481603 test_cros_ec_abi: pass
test_cros_ec_accel_iio_abi: skip
test_cros_ec_accel_iio_data_is_valid: skip
test_cros_ec_battery_abi: skip
test_cros_ec_chardev: pass
test_cros_ec_extcon_usbc_abi: skip
test_cros_ec_gyro_iio_abi: skip
test_cros_ec_hello: pass
test_cros_ec_pwm_backlight: skip
test_cros_ec_rtc_abi: skip
test_cros_ec_usbpd_charger_abi: skip
test_cros_fp_abi: skip
test_cros_fp_hello: skip
test_cros_fp_reboot: skip
test_cros_pd_abi: skip
test_cros_pd_hello: skip
test_cros_tp_abi: skip
test_cros_tp_hello: skip
10906 23:10:17.482090 end: 3.1 lava-test-shell (duration 00:00:01) [common]
10907 23:10:17.482558 end: 3 lava-test-retry (duration 00:00:01) [common]
10908 23:10:17.483027 start: 4 finalize (timeout 00:08:03) [common]
10909 23:10:17.483509 start: 4.1 power-off (timeout 00:00:30) [common]
10910 23:10:17.484634 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=off'
10911 23:10:17.604306 >> Command sent successfully.
10912 23:10:17.608627 Returned 0 in 0 seconds
10913 23:10:17.709581 end: 4.1 power-off (duration 00:00:00) [common]
10915 23:10:17.711229 start: 4.2 read-feedback (timeout 00:08:03) [common]
10916 23:10:17.712654 Listened to connection for namespace 'common' for up to 1s
10917 23:10:18.713179 Finalising connection for namespace 'common'
10918 23:10:18.713880 Disconnecting from shell: Finalise
10919 23:10:18.714290 / #
10920 23:10:18.815309 end: 4.2 read-feedback (duration 00:00:01) [common]
10921 23:10:18.816070 end: 4 finalize (duration 00:00:01) [common]
10922 23:10:18.816743 Cleaning after the job
10923 23:10:18.817283 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12154449/tftp-deploy-dwu5w1iq/ramdisk
10924 23:10:18.849054 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12154449/tftp-deploy-dwu5w1iq/kernel
10925 23:10:18.866563 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12154449/tftp-deploy-dwu5w1iq/dtb
10926 23:10:18.866838 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12154449/tftp-deploy-dwu5w1iq/modules
10927 23:10:18.876929 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12154449
10928 23:10:18.996063 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12154449
10929 23:10:18.996243 Job finished correctly