Boot log: mt8192-asurada-spherion-r0
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 21
- Kernel Errors: 33
- Errors: 0
1 23:07:51.840744 lava-dispatcher, installed at version: 2023.10
2 23:07:51.840960 start: 0 validate
3 23:07:51.841095 Start time: 2023-12-01 23:07:51.841086+00:00 (UTC)
4 23:07:51.841215 Using caching service: 'http://localhost/cache/?uri=%s'
5 23:07:51.841350 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-igt%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 23:07:52.109135 Using caching service: 'http://localhost/cache/?uri=%s'
7 23:07:52.109310 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.64-cip10%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 23:07:52.366876 Using caching service: 'http://localhost/cache/?uri=%s'
9 23:07:52.367055 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.64-cip10%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 23:07:52.632138 Using caching service: 'http://localhost/cache/?uri=%s'
11 23:07:52.632325 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.64-cip10%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 23:07:52.891484 validate duration: 1.05
14 23:07:52.891877 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 23:07:52.891990 start: 1.1 download-retry (timeout 00:10:00) [common]
16 23:07:52.892110 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 23:07:52.892230 Not decompressing ramdisk as can be used compressed.
18 23:07:52.892321 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-igt/20230623.0/arm64/rootfs.cpio.gz
19 23:07:52.892388 saving as /var/lib/lava/dispatcher/tmp/12154438/tftp-deploy-d_6wcibw/ramdisk/rootfs.cpio.gz
20 23:07:52.892453 total size: 43284872 (41 MB)
21 23:07:52.893529 progress 0 % (0 MB)
22 23:07:52.905917 progress 5 % (2 MB)
23 23:07:52.918098 progress 10 % (4 MB)
24 23:07:52.930852 progress 15 % (6 MB)
25 23:07:52.943496 progress 20 % (8 MB)
26 23:07:52.956653 progress 25 % (10 MB)
27 23:07:52.969265 progress 30 % (12 MB)
28 23:07:52.981445 progress 35 % (14 MB)
29 23:07:52.993039 progress 40 % (16 MB)
30 23:07:53.004681 progress 45 % (18 MB)
31 23:07:53.016244 progress 50 % (20 MB)
32 23:07:53.027700 progress 55 % (22 MB)
33 23:07:53.039271 progress 60 % (24 MB)
34 23:07:53.050722 progress 65 % (26 MB)
35 23:07:53.062183 progress 70 % (28 MB)
36 23:07:53.073603 progress 75 % (30 MB)
37 23:07:53.085091 progress 80 % (33 MB)
38 23:07:53.096533 progress 85 % (35 MB)
39 23:07:53.108056 progress 90 % (37 MB)
40 23:07:53.119316 progress 95 % (39 MB)
41 23:07:53.130513 progress 100 % (41 MB)
42 23:07:53.130775 41 MB downloaded in 0.24 s (173.21 MB/s)
43 23:07:53.130950 end: 1.1.1 http-download (duration 00:00:00) [common]
45 23:07:53.131197 end: 1.1 download-retry (duration 00:00:00) [common]
46 23:07:53.131284 start: 1.2 download-retry (timeout 00:10:00) [common]
47 23:07:53.131409 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 23:07:53.131539 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.64-cip10/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 23:07:53.131609 saving as /var/lib/lava/dispatcher/tmp/12154438/tftp-deploy-d_6wcibw/kernel/Image
50 23:07:53.131708 total size: 49172992 (46 MB)
51 23:07:53.131801 No compression specified
52 23:07:53.132963 progress 0 % (0 MB)
53 23:07:53.147841 progress 5 % (2 MB)
54 23:07:53.160675 progress 10 % (4 MB)
55 23:07:53.173420 progress 15 % (7 MB)
56 23:07:53.186584 progress 20 % (9 MB)
57 23:07:53.200076 progress 25 % (11 MB)
58 23:07:53.212995 progress 30 % (14 MB)
59 23:07:53.226031 progress 35 % (16 MB)
60 23:07:53.238980 progress 40 % (18 MB)
61 23:07:53.251940 progress 45 % (21 MB)
62 23:07:53.264921 progress 50 % (23 MB)
63 23:07:53.277738 progress 55 % (25 MB)
64 23:07:53.290771 progress 60 % (28 MB)
65 23:07:53.303660 progress 65 % (30 MB)
66 23:07:53.316528 progress 70 % (32 MB)
67 23:07:53.330016 progress 75 % (35 MB)
68 23:07:53.343423 progress 80 % (37 MB)
69 23:07:53.356700 progress 85 % (39 MB)
70 23:07:53.369566 progress 90 % (42 MB)
71 23:07:53.382457 progress 95 % (44 MB)
72 23:07:53.395566 progress 100 % (46 MB)
73 23:07:53.395819 46 MB downloaded in 0.26 s (177.56 MB/s)
74 23:07:53.395968 end: 1.2.1 http-download (duration 00:00:00) [common]
76 23:07:53.396201 end: 1.2 download-retry (duration 00:00:00) [common]
77 23:07:53.396293 start: 1.3 download-retry (timeout 00:09:59) [common]
78 23:07:53.396378 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 23:07:53.396510 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.64-cip10/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 23:07:53.396584 saving as /var/lib/lava/dispatcher/tmp/12154438/tftp-deploy-d_6wcibw/dtb/mt8192-asurada-spherion-r0.dtb
81 23:07:53.396646 total size: 47278 (0 MB)
82 23:07:53.396709 No compression specified
83 23:07:53.397864 progress 69 % (0 MB)
84 23:07:53.398138 progress 100 % (0 MB)
85 23:07:53.398374 0 MB downloaded in 0.00 s (26.14 MB/s)
86 23:07:53.398501 end: 1.3.1 http-download (duration 00:00:00) [common]
88 23:07:53.398726 end: 1.3 download-retry (duration 00:00:00) [common]
89 23:07:53.398811 start: 1.4 download-retry (timeout 00:09:59) [common]
90 23:07:53.398898 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 23:07:53.399015 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.64-cip10/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 23:07:53.399083 saving as /var/lib/lava/dispatcher/tmp/12154438/tftp-deploy-d_6wcibw/modules/modules.tar
93 23:07:53.399144 total size: 8616152 (8 MB)
94 23:07:53.399206 Using unxz to decompress xz
95 23:07:53.403383 progress 0 % (0 MB)
96 23:07:53.424761 progress 5 % (0 MB)
97 23:07:53.449080 progress 10 % (0 MB)
98 23:07:53.473258 progress 15 % (1 MB)
99 23:07:53.497428 progress 20 % (1 MB)
100 23:07:53.522785 progress 25 % (2 MB)
101 23:07:53.548973 progress 30 % (2 MB)
102 23:07:53.576501 progress 35 % (2 MB)
103 23:07:53.600798 progress 40 % (3 MB)
104 23:07:53.626084 progress 45 % (3 MB)
105 23:07:53.653793 progress 50 % (4 MB)
106 23:07:53.680420 progress 55 % (4 MB)
107 23:07:53.707536 progress 60 % (4 MB)
108 23:07:53.736170 progress 65 % (5 MB)
109 23:07:53.765176 progress 70 % (5 MB)
110 23:07:53.790733 progress 75 % (6 MB)
111 23:07:53.820141 progress 80 % (6 MB)
112 23:07:53.848362 progress 85 % (7 MB)
113 23:07:53.875307 progress 90 % (7 MB)
114 23:07:53.907042 progress 95 % (7 MB)
115 23:07:53.937418 progress 100 % (8 MB)
116 23:07:53.944281 8 MB downloaded in 0.55 s (15.07 MB/s)
117 23:07:53.944538 end: 1.4.1 http-download (duration 00:00:01) [common]
119 23:07:53.944807 end: 1.4 download-retry (duration 00:00:01) [common]
120 23:07:53.944900 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 23:07:53.944995 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 23:07:53.945078 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 23:07:53.945162 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 23:07:53.945397 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12154438/lava-overlay-n8dc13xv
125 23:07:53.945536 makedir: /var/lib/lava/dispatcher/tmp/12154438/lava-overlay-n8dc13xv/lava-12154438/bin
126 23:07:53.945688 makedir: /var/lib/lava/dispatcher/tmp/12154438/lava-overlay-n8dc13xv/lava-12154438/tests
127 23:07:53.945790 makedir: /var/lib/lava/dispatcher/tmp/12154438/lava-overlay-n8dc13xv/lava-12154438/results
128 23:07:53.945911 Creating /var/lib/lava/dispatcher/tmp/12154438/lava-overlay-n8dc13xv/lava-12154438/bin/lava-add-keys
129 23:07:53.946067 Creating /var/lib/lava/dispatcher/tmp/12154438/lava-overlay-n8dc13xv/lava-12154438/bin/lava-add-sources
130 23:07:53.946206 Creating /var/lib/lava/dispatcher/tmp/12154438/lava-overlay-n8dc13xv/lava-12154438/bin/lava-background-process-start
131 23:07:53.946342 Creating /var/lib/lava/dispatcher/tmp/12154438/lava-overlay-n8dc13xv/lava-12154438/bin/lava-background-process-stop
132 23:07:53.946473 Creating /var/lib/lava/dispatcher/tmp/12154438/lava-overlay-n8dc13xv/lava-12154438/bin/lava-common-functions
133 23:07:53.946603 Creating /var/lib/lava/dispatcher/tmp/12154438/lava-overlay-n8dc13xv/lava-12154438/bin/lava-echo-ipv4
134 23:07:53.946733 Creating /var/lib/lava/dispatcher/tmp/12154438/lava-overlay-n8dc13xv/lava-12154438/bin/lava-install-packages
135 23:07:53.946863 Creating /var/lib/lava/dispatcher/tmp/12154438/lava-overlay-n8dc13xv/lava-12154438/bin/lava-installed-packages
136 23:07:53.946991 Creating /var/lib/lava/dispatcher/tmp/12154438/lava-overlay-n8dc13xv/lava-12154438/bin/lava-os-build
137 23:07:53.947120 Creating /var/lib/lava/dispatcher/tmp/12154438/lava-overlay-n8dc13xv/lava-12154438/bin/lava-probe-channel
138 23:07:53.947248 Creating /var/lib/lava/dispatcher/tmp/12154438/lava-overlay-n8dc13xv/lava-12154438/bin/lava-probe-ip
139 23:07:53.947381 Creating /var/lib/lava/dispatcher/tmp/12154438/lava-overlay-n8dc13xv/lava-12154438/bin/lava-target-ip
140 23:07:53.947509 Creating /var/lib/lava/dispatcher/tmp/12154438/lava-overlay-n8dc13xv/lava-12154438/bin/lava-target-mac
141 23:07:53.947639 Creating /var/lib/lava/dispatcher/tmp/12154438/lava-overlay-n8dc13xv/lava-12154438/bin/lava-target-storage
142 23:07:53.947772 Creating /var/lib/lava/dispatcher/tmp/12154438/lava-overlay-n8dc13xv/lava-12154438/bin/lava-test-case
143 23:07:53.947904 Creating /var/lib/lava/dispatcher/tmp/12154438/lava-overlay-n8dc13xv/lava-12154438/bin/lava-test-event
144 23:07:53.948032 Creating /var/lib/lava/dispatcher/tmp/12154438/lava-overlay-n8dc13xv/lava-12154438/bin/lava-test-feedback
145 23:07:53.948190 Creating /var/lib/lava/dispatcher/tmp/12154438/lava-overlay-n8dc13xv/lava-12154438/bin/lava-test-raise
146 23:07:53.948320 Creating /var/lib/lava/dispatcher/tmp/12154438/lava-overlay-n8dc13xv/lava-12154438/bin/lava-test-reference
147 23:07:53.948449 Creating /var/lib/lava/dispatcher/tmp/12154438/lava-overlay-n8dc13xv/lava-12154438/bin/lava-test-runner
148 23:07:53.948578 Creating /var/lib/lava/dispatcher/tmp/12154438/lava-overlay-n8dc13xv/lava-12154438/bin/lava-test-set
149 23:07:53.948709 Creating /var/lib/lava/dispatcher/tmp/12154438/lava-overlay-n8dc13xv/lava-12154438/bin/lava-test-shell
150 23:07:53.948880 Updating /var/lib/lava/dispatcher/tmp/12154438/lava-overlay-n8dc13xv/lava-12154438/bin/lava-install-packages (oe)
151 23:07:53.949037 Updating /var/lib/lava/dispatcher/tmp/12154438/lava-overlay-n8dc13xv/lava-12154438/bin/lava-installed-packages (oe)
152 23:07:53.949163 Creating /var/lib/lava/dispatcher/tmp/12154438/lava-overlay-n8dc13xv/lava-12154438/environment
153 23:07:53.949297 LAVA metadata
154 23:07:53.949373 - LAVA_JOB_ID=12154438
155 23:07:53.949439 - LAVA_DISPATCHER_IP=192.168.201.1
156 23:07:53.949542 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 23:07:53.949650 skipped lava-vland-overlay
158 23:07:53.949728 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 23:07:53.949810 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 23:07:53.949878 skipped lava-multinode-overlay
161 23:07:53.949951 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 23:07:53.950037 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 23:07:53.950122 Loading test definitions
164 23:07:53.950212 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 23:07:53.950288 Using /lava-12154438 at stage 0
166 23:07:53.950609 uuid=12154438_1.5.2.3.1 testdef=None
167 23:07:53.950697 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 23:07:53.950783 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 23:07:53.951310 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 23:07:53.951536 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 23:07:53.952159 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 23:07:53.952389 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 23:07:53.953026 runner path: /var/lib/lava/dispatcher/tmp/12154438/lava-overlay-n8dc13xv/lava-12154438/0/tests/0_igt-gpu-panfrost test_uuid 12154438_1.5.2.3.1
176 23:07:53.953186 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 23:07:53.953394 Creating lava-test-runner.conf files
179 23:07:53.953457 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12154438/lava-overlay-n8dc13xv/lava-12154438/0 for stage 0
180 23:07:53.953549 - 0_igt-gpu-panfrost
181 23:07:53.953690 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 23:07:53.953773 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 23:07:53.960911 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 23:07:53.961034 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 23:07:53.961163 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 23:07:53.961249 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 23:07:53.961340 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 23:07:55.398839 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 23:07:55.399312 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
190 23:07:55.399483 extracting modules file /var/lib/lava/dispatcher/tmp/12154438/tftp-deploy-d_6wcibw/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12154438/extract-overlay-ramdisk-tlnyfaij/ramdisk
191 23:07:55.641406 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 23:07:55.641586 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 23:07:55.641733 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12154438/compress-overlay-uqiaxq6e/overlay-1.5.2.4.tar.gz to ramdisk
194 23:07:55.641807 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12154438/compress-overlay-uqiaxq6e/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12154438/extract-overlay-ramdisk-tlnyfaij/ramdisk
195 23:07:55.648483 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 23:07:55.648598 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 23:07:55.648691 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 23:07:55.648784 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 23:07:55.648895 Building ramdisk /var/lib/lava/dispatcher/tmp/12154438/extract-overlay-ramdisk-tlnyfaij/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12154438/extract-overlay-ramdisk-tlnyfaij/ramdisk
200 23:07:56.705390 >> 369988 blocks
201 23:08:02.486297 rename /var/lib/lava/dispatcher/tmp/12154438/extract-overlay-ramdisk-tlnyfaij/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12154438/tftp-deploy-d_6wcibw/ramdisk/ramdisk.cpio.gz
202 23:08:02.486733 end: 1.5.7 compress-ramdisk (duration 00:00:07) [common]
203 23:08:02.486857 start: 1.5.8 prepare-kernel (timeout 00:09:50) [common]
204 23:08:02.486958 start: 1.5.8.1 prepare-fit (timeout 00:09:50) [common]
205 23:08:02.487065 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12154438/tftp-deploy-d_6wcibw/kernel/Image'
206 23:08:14.477428 Returned 0 in 11 seconds
207 23:08:14.578087 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12154438/tftp-deploy-d_6wcibw/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12154438/tftp-deploy-d_6wcibw/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12154438/tftp-deploy-d_6wcibw/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12154438/tftp-deploy-d_6wcibw/kernel/image.itb
208 23:08:15.405410 output: FIT description: Kernel Image image with one or more FDT blobs
209 23:08:15.405828 output: Created: Fri Dec 1 23:08:15 2023
210 23:08:15.405905 output: Image 0 (kernel-1)
211 23:08:15.405970 output: Description:
212 23:08:15.406034 output: Created: Fri Dec 1 23:08:15 2023
213 23:08:15.406098 output: Type: Kernel Image
214 23:08:15.406158 output: Compression: lzma compressed
215 23:08:15.406214 output: Data Size: 11043984 Bytes = 10785.14 KiB = 10.53 MiB
216 23:08:15.406267 output: Architecture: AArch64
217 23:08:15.406322 output: OS: Linux
218 23:08:15.406375 output: Load Address: 0x00000000
219 23:08:15.406428 output: Entry Point: 0x00000000
220 23:08:15.406483 output: Hash algo: crc32
221 23:08:15.406538 output: Hash value: 36c84243
222 23:08:15.406592 output: Image 1 (fdt-1)
223 23:08:15.406645 output: Description: mt8192-asurada-spherion-r0
224 23:08:15.406696 output: Created: Fri Dec 1 23:08:15 2023
225 23:08:15.406747 output: Type: Flat Device Tree
226 23:08:15.406798 output: Compression: uncompressed
227 23:08:15.406850 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 23:08:15.406901 output: Architecture: AArch64
229 23:08:15.406952 output: Hash algo: crc32
230 23:08:15.407003 output: Hash value: cc4352de
231 23:08:15.407055 output: Image 2 (ramdisk-1)
232 23:08:15.407105 output: Description: unavailable
233 23:08:15.407156 output: Created: Fri Dec 1 23:08:15 2023
234 23:08:15.407207 output: Type: RAMDisk Image
235 23:08:15.407259 output: Compression: Unknown Compression
236 23:08:15.407310 output: Data Size: 56430018 Bytes = 55107.44 KiB = 53.82 MiB
237 23:08:15.407361 output: Architecture: AArch64
238 23:08:15.407412 output: OS: Linux
239 23:08:15.407463 output: Load Address: unavailable
240 23:08:15.407514 output: Entry Point: unavailable
241 23:08:15.407565 output: Hash algo: crc32
242 23:08:15.407615 output: Hash value: 39a0c060
243 23:08:15.407666 output: Default Configuration: 'conf-1'
244 23:08:15.407717 output: Configuration 0 (conf-1)
245 23:08:15.407767 output: Description: mt8192-asurada-spherion-r0
246 23:08:15.407818 output: Kernel: kernel-1
247 23:08:15.407869 output: Init Ramdisk: ramdisk-1
248 23:08:15.407920 output: FDT: fdt-1
249 23:08:15.407970 output: Loadables: kernel-1
250 23:08:15.408020 output:
251 23:08:15.408215 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
252 23:08:15.408312 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
253 23:08:15.408411 end: 1.5 prepare-tftp-overlay (duration 00:00:21) [common]
254 23:08:15.408499 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:37) [common]
255 23:08:15.408575 No LXC device requested
256 23:08:15.408651 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 23:08:15.408734 start: 1.7 deploy-device-env (timeout 00:09:37) [common]
258 23:08:15.408809 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 23:08:15.408875 Checking files for TFTP limit of 4294967296 bytes.
260 23:08:15.409371 end: 1 tftp-deploy (duration 00:00:23) [common]
261 23:08:15.409477 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 23:08:15.409567 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 23:08:15.409727 substitutions:
264 23:08:15.409791 - {DTB}: 12154438/tftp-deploy-d_6wcibw/dtb/mt8192-asurada-spherion-r0.dtb
265 23:08:15.409855 - {INITRD}: 12154438/tftp-deploy-d_6wcibw/ramdisk/ramdisk.cpio.gz
266 23:08:15.409912 - {KERNEL}: 12154438/tftp-deploy-d_6wcibw/kernel/Image
267 23:08:15.409967 - {LAVA_MAC}: None
268 23:08:15.410021 - {PRESEED_CONFIG}: None
269 23:08:15.410076 - {PRESEED_LOCAL}: None
270 23:08:15.410129 - {RAMDISK}: 12154438/tftp-deploy-d_6wcibw/ramdisk/ramdisk.cpio.gz
271 23:08:15.410183 - {ROOT_PART}: None
272 23:08:15.410236 - {ROOT}: None
273 23:08:15.410305 - {SERVER_IP}: 192.168.201.1
274 23:08:15.410370 - {TEE}: None
275 23:08:15.410422 Parsed boot commands:
276 23:08:15.410476 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 23:08:15.410654 Parsed boot commands: tftpboot 192.168.201.1 12154438/tftp-deploy-d_6wcibw/kernel/image.itb 12154438/tftp-deploy-d_6wcibw/kernel/cmdline
278 23:08:15.410740 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 23:08:15.410822 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 23:08:15.410912 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 23:08:15.410995 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 23:08:15.411064 Not connected, no need to disconnect.
283 23:08:15.411183 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 23:08:15.411273 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 23:08:15.411349 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
286 23:08:15.415532 Setting prompt string to ['lava-test: # ']
287 23:08:15.415922 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 23:08:15.416050 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 23:08:15.416174 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 23:08:15.416294 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 23:08:15.416526 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
292 23:08:20.569974 >> Command sent successfully.
293 23:08:20.580851 Returned 0 in 5 seconds
294 23:08:20.682368 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 23:08:20.684041 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 23:08:20.684583 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 23:08:20.685148 Setting prompt string to 'Starting depthcharge on Spherion...'
299 23:08:20.685703 Changing prompt to 'Starting depthcharge on Spherion...'
300 23:08:20.686108 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 23:08:20.687457 [Enter `^Ec?' for help]
302 23:08:20.846946
303 23:08:20.847516
304 23:08:20.847898 F0: 102B 0000
305 23:08:20.848287
306 23:08:20.848632 F3: 1001 0000 [0200]
307 23:08:20.848955
308 23:08:20.849763 F3: 1001 0000
309 23:08:20.850229
310 23:08:20.850605 F7: 102D 0000
311 23:08:20.850957
312 23:08:20.853680 F1: 0000 0000
313 23:08:20.854182
314 23:08:20.854533 V0: 0000 0000 [0001]
315 23:08:20.854863
316 23:08:20.856735 00: 0007 8000
317 23:08:20.857324
318 23:08:20.857762 01: 0000 0000
319 23:08:20.858131
320 23:08:20.858470 BP: 0C00 0209 [0000]
321 23:08:20.859974
322 23:08:20.860399 G0: 1182 0000
323 23:08:20.860742
324 23:08:20.861057 EC: 0000 0021 [4000]
325 23:08:20.863540
326 23:08:20.863963 S7: 0000 0000 [0000]
327 23:08:20.864303
328 23:08:20.864619 CC: 0000 0000 [0001]
329 23:08:20.867060
330 23:08:20.867486 T0: 0000 0040 [010F]
331 23:08:20.867826
332 23:08:20.868143 Jump to BL
333 23:08:20.868445
334 23:08:20.893390
335 23:08:20.893932
336 23:08:20.894273
337 23:08:20.901107 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 23:08:20.905141 ARM64: Exception handlers installed.
339 23:08:20.908172 ARM64: Testing exception
340 23:08:20.911334 ARM64: Done test exception
341 23:08:20.918120 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 23:08:20.928275 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 23:08:20.934422 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 23:08:20.944847 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 23:08:20.951493 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 23:08:20.958193 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 23:08:20.970836 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 23:08:20.977517 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 23:08:20.996228 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 23:08:20.999179 WDT: Last reset was cold boot
351 23:08:21.002608 SPI1(PAD0) initialized at 2873684 Hz
352 23:08:21.006074 SPI5(PAD0) initialized at 992727 Hz
353 23:08:21.009015 VBOOT: Loading verstage.
354 23:08:21.016024 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 23:08:21.020280 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 23:08:21.023170 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 23:08:21.026631 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 23:08:21.033466 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 23:08:21.040079 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 23:08:21.051533 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 23:08:21.051654
362 23:08:21.051746
363 23:08:21.061433 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 23:08:21.064690 ARM64: Exception handlers installed.
365 23:08:21.064783 ARM64: Testing exception
366 23:08:21.068228 ARM64: Done test exception
367 23:08:21.071575 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 23:08:21.078262 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 23:08:21.092143 Probing TPM: . done!
370 23:08:21.092226 TPM ready after 0 ms
371 23:08:21.098548 Connected to device vid:did:rid of 1ae0:0028:00
372 23:08:21.105492 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 23:08:21.164723 Initialized TPM device CR50 revision 0
374 23:08:21.176675 tlcl_send_startup: Startup return code is 0
375 23:08:21.176878 TPM: setup succeeded
376 23:08:21.188034 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 23:08:21.197134 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 23:08:21.210950 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 23:08:21.218238 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 23:08:21.221525 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 23:08:21.225423 in-header: 03 07 00 00 08 00 00 00
382 23:08:21.228862 in-data: aa e4 47 04 13 02 00 00
383 23:08:21.232897 Chrome EC: UHEPI supported
384 23:08:21.239981 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 23:08:21.243895 in-header: 03 95 00 00 08 00 00 00
386 23:08:21.247797 in-data: 18 20 20 08 00 00 00 00
387 23:08:21.248270 Phase 1
388 23:08:21.251392 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 23:08:21.255098 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 23:08:21.262085 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 23:08:21.265362 Recovery requested (1009000e)
392 23:08:21.273781 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 23:08:21.279052 tlcl_extend: response is 0
394 23:08:21.288984 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 23:08:21.292752 tlcl_extend: response is 0
396 23:08:21.299229 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 23:08:21.319878 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
398 23:08:21.326321 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 23:08:21.326908
400 23:08:21.327436
401 23:08:21.336893 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 23:08:21.339842 ARM64: Exception handlers installed.
403 23:08:21.343289 ARM64: Testing exception
404 23:08:21.343760 ARM64: Done test exception
405 23:08:21.365898 pmic_efuse_setting: Set efuses in 11 msecs
406 23:08:21.368748 pmwrap_interface_init: Select PMIF_VLD_RDY
407 23:08:21.375544 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 23:08:21.378630 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 23:08:21.386206 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 23:08:21.389740 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 23:08:21.393548 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 23:08:21.400500 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 23:08:21.404442 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 23:08:21.407759 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 23:08:21.411378 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 23:08:21.418650 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 23:08:21.422976 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 23:08:21.426047 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 23:08:21.429563 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 23:08:21.437303 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 23:08:21.444732 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 23:08:21.448371 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 23:08:21.456082 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 23:08:21.459772 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 23:08:21.467344 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 23:08:21.471456 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 23:08:21.478708 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 23:08:21.482211 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 23:08:21.490133 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 23:08:21.493812 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 23:08:21.497491 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 23:08:21.504752 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 23:08:21.508397 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 23:08:21.515390 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 23:08:21.519525 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 23:08:21.522948 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 23:08:21.530308 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 23:08:21.533766 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 23:08:21.537706 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 23:08:21.544908 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 23:08:21.548357 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 23:08:21.556102 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 23:08:21.559145 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 23:08:21.563583 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 23:08:21.567182 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 23:08:21.574761 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 23:08:21.578379 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 23:08:21.581855 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 23:08:21.585511 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 23:08:21.589231 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 23:08:21.597246 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 23:08:21.600983 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 23:08:21.604341 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 23:08:21.608133 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 23:08:21.611571 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 23:08:21.615252 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 23:08:21.618955 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 23:08:21.626962 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 23:08:21.638254 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 23:08:21.642012 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 23:08:21.649294 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 23:08:21.656880 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 23:08:21.664127 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 23:08:21.667860 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 23:08:21.671437 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 23:08:21.678845 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x29
467 23:08:21.682146 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 23:08:21.689783 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 23:08:21.693117 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 23:08:21.703068 [RTC]rtc_get_frequency_meter,154: input=15, output=759
471 23:08:21.712178 [RTC]rtc_get_frequency_meter,154: input=23, output=943
472 23:08:21.722203 [RTC]rtc_get_frequency_meter,154: input=19, output=850
473 23:08:21.731292 [RTC]rtc_get_frequency_meter,154: input=17, output=803
474 23:08:21.740279 [RTC]rtc_get_frequency_meter,154: input=16, output=783
475 23:08:21.750240 [RTC]rtc_get_frequency_meter,154: input=16, output=781
476 23:08:21.760010 [RTC]rtc_get_frequency_meter,154: input=17, output=803
477 23:08:21.763403 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
478 23:08:21.767050 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde71
479 23:08:21.771362 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 23:08:21.778336 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
481 23:08:21.782464 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 23:08:21.785566 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
483 23:08:21.789499 ADC[4]: Raw value=906573 ID=7
484 23:08:21.789610 ADC[3]: Raw value=213810 ID=1
485 23:08:21.793319 RAM Code: 0x71
486 23:08:21.796913 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 23:08:21.800868 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 23:08:21.812534 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 23:08:21.816016 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 23:08:21.819199 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 23:08:21.823325 in-header: 03 07 00 00 08 00 00 00
492 23:08:21.826769 in-data: aa e4 47 04 13 02 00 00
493 23:08:21.830376 Chrome EC: UHEPI supported
494 23:08:21.837724 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 23:08:21.841412 in-header: 03 95 00 00 08 00 00 00
496 23:08:21.845262 in-data: 18 20 20 08 00 00 00 00
497 23:08:21.845345 MRC: failed to locate region type 0.
498 23:08:21.853276 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 23:08:21.856420 DRAM-K: Running full calibration
500 23:08:21.863712 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 23:08:21.863797 header.status = 0x0
502 23:08:21.867893 header.version = 0x6 (expected: 0x6)
503 23:08:21.871591 header.size = 0xd00 (expected: 0xd00)
504 23:08:21.871675 header.flags = 0x0
505 23:08:21.878534 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 23:08:21.897208 read SPI 0x72590 0x1c583: 12497 us, 9290 KB/s, 74.320 Mbps
507 23:08:21.905003 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 23:08:21.905088 dram_init: ddr_geometry: 2
509 23:08:21.909414 [EMI] MDL number = 2
510 23:08:21.910007 [EMI] Get MDL freq = 0
511 23:08:21.913244 dram_init: ddr_type: 0
512 23:08:21.913877 is_discrete_lpddr4: 1
513 23:08:21.917173 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 23:08:21.917654
515 23:08:21.918041
516 23:08:21.921322 [Bian_co] ETT version 0.0.0.1
517 23:08:21.924772 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 23:08:21.925275
519 23:08:21.928822 dramc_set_vcore_voltage set vcore to 650000
520 23:08:21.932744 Read voltage for 800, 4
521 23:08:21.933247 Vio18 = 0
522 23:08:21.933634 Vcore = 650000
523 23:08:21.936016 Vdram = 0
524 23:08:21.936435 Vddq = 0
525 23:08:21.936819 Vmddr = 0
526 23:08:21.940310 dram_init: config_dvfs: 1
527 23:08:21.943752 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 23:08:21.950973 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 23:08:21.954790 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
530 23:08:21.958191 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
531 23:08:21.962532 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
532 23:08:21.966410 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
533 23:08:21.966846 MEM_TYPE=3, freq_sel=18
534 23:08:21.969879 sv_algorithm_assistance_LP4_1600
535 23:08:21.973918 ============ PULL DRAM RESETB DOWN ============
536 23:08:21.976552 ========== PULL DRAM RESETB DOWN end =========
537 23:08:21.983458 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 23:08:21.986555 ===================================
539 23:08:21.987004 LPDDR4 DRAM CONFIGURATION
540 23:08:21.990376 ===================================
541 23:08:21.994206 EX_ROW_EN[0] = 0x0
542 23:08:21.994627 EX_ROW_EN[1] = 0x0
543 23:08:21.997678 LP4Y_EN = 0x0
544 23:08:21.998103 WORK_FSP = 0x0
545 23:08:22.001571 WL = 0x2
546 23:08:22.002028 RL = 0x2
547 23:08:22.005086 BL = 0x2
548 23:08:22.005506 RPST = 0x0
549 23:08:22.008913 RD_PRE = 0x0
550 23:08:22.009338 WR_PRE = 0x1
551 23:08:22.012744 WR_PST = 0x0
552 23:08:22.013440 DBI_WR = 0x0
553 23:08:22.016005 DBI_RD = 0x0
554 23:08:22.016455 OTF = 0x1
555 23:08:22.019217 ===================================
556 23:08:22.022639 ===================================
557 23:08:22.023061 ANA top config
558 23:08:22.025806 ===================================
559 23:08:22.029759 DLL_ASYNC_EN = 0
560 23:08:22.032429 ALL_SLAVE_EN = 1
561 23:08:22.036332 NEW_RANK_MODE = 1
562 23:08:22.039177 DLL_IDLE_MODE = 1
563 23:08:22.039596 LP45_APHY_COMB_EN = 1
564 23:08:22.042659 TX_ODT_DIS = 1
565 23:08:22.046244 NEW_8X_MODE = 1
566 23:08:22.049726 ===================================
567 23:08:22.053370 ===================================
568 23:08:22.053847 data_rate = 1600
569 23:08:22.056661 CKR = 1
570 23:08:22.060197 DQ_P2S_RATIO = 8
571 23:08:22.063955 ===================================
572 23:08:22.066926 CA_P2S_RATIO = 8
573 23:08:22.070153 DQ_CA_OPEN = 0
574 23:08:22.073371 DQ_SEMI_OPEN = 0
575 23:08:22.073838 CA_SEMI_OPEN = 0
576 23:08:22.076855 CA_FULL_RATE = 0
577 23:08:22.080210 DQ_CKDIV4_EN = 1
578 23:08:22.083158 CA_CKDIV4_EN = 1
579 23:08:22.086806 CA_PREDIV_EN = 0
580 23:08:22.090426 PH8_DLY = 0
581 23:08:22.090853 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 23:08:22.093862 DQ_AAMCK_DIV = 4
583 23:08:22.096980 CA_AAMCK_DIV = 4
584 23:08:22.100239 CA_ADMCK_DIV = 4
585 23:08:22.103992 DQ_TRACK_CA_EN = 0
586 23:08:22.107101 CA_PICK = 800
587 23:08:22.107525 CA_MCKIO = 800
588 23:08:22.110257 MCKIO_SEMI = 0
589 23:08:22.114018 PLL_FREQ = 3068
590 23:08:22.117806 DQ_UI_PI_RATIO = 32
591 23:08:22.122288 CA_UI_PI_RATIO = 0
592 23:08:22.122735 ===================================
593 23:08:22.125162 ===================================
594 23:08:22.129232 memory_type:LPDDR4
595 23:08:22.129366 GP_NUM : 10
596 23:08:22.133081 SRAM_EN : 1
597 23:08:22.136288 MD32_EN : 0
598 23:08:22.136370 ===================================
599 23:08:22.140072 [ANA_INIT] >>>>>>>>>>>>>>
600 23:08:22.144266 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 23:08:22.148000 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 23:08:22.150993 ===================================
603 23:08:22.151078 data_rate = 1600,PCW = 0X7600
604 23:08:22.154735 ===================================
605 23:08:22.157834 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 23:08:22.164260 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 23:08:22.171254 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 23:08:22.174335 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 23:08:22.177492 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 23:08:22.181217 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 23:08:22.184456 [ANA_INIT] flow start
612 23:08:22.187355 [ANA_INIT] PLL >>>>>>>>
613 23:08:22.187436 [ANA_INIT] PLL <<<<<<<<
614 23:08:22.190723 [ANA_INIT] MIDPI >>>>>>>>
615 23:08:22.193884 [ANA_INIT] MIDPI <<<<<<<<
616 23:08:22.193967 [ANA_INIT] DLL >>>>>>>>
617 23:08:22.197428 [ANA_INIT] flow end
618 23:08:22.201012 ============ LP4 DIFF to SE enter ============
619 23:08:22.204314 ============ LP4 DIFF to SE exit ============
620 23:08:22.207417 [ANA_INIT] <<<<<<<<<<<<<
621 23:08:22.210588 [Flow] Enable top DCM control >>>>>
622 23:08:22.213878 [Flow] Enable top DCM control <<<<<
623 23:08:22.217355 Enable DLL master slave shuffle
624 23:08:22.224146 ==============================================================
625 23:08:22.224229 Gating Mode config
626 23:08:22.230824 ==============================================================
627 23:08:22.230908 Config description:
628 23:08:22.241038 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 23:08:22.247487 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 23:08:22.254409 SELPH_MODE 0: By rank 1: By Phase
631 23:08:22.257413 ==============================================================
632 23:08:22.261095 GAT_TRACK_EN = 1
633 23:08:22.264194 RX_GATING_MODE = 2
634 23:08:22.267412 RX_GATING_TRACK_MODE = 2
635 23:08:22.271170 SELPH_MODE = 1
636 23:08:22.274601 PICG_EARLY_EN = 1
637 23:08:22.277580 VALID_LAT_VALUE = 1
638 23:08:22.281427 ==============================================================
639 23:08:22.284487 Enter into Gating configuration >>>>
640 23:08:22.287886 Exit from Gating configuration <<<<
641 23:08:22.290742 Enter into DVFS_PRE_config >>>>>
642 23:08:22.304529 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 23:08:22.304618 Exit from DVFS_PRE_config <<<<<
644 23:08:22.307581 Enter into PICG configuration >>>>
645 23:08:22.311066 Exit from PICG configuration <<<<
646 23:08:22.314446 [RX_INPUT] configuration >>>>>
647 23:08:22.318120 [RX_INPUT] configuration <<<<<
648 23:08:22.325142 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 23:08:22.328434 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 23:08:22.334846 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 23:08:22.341874 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 23:08:22.348464 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 23:08:22.354970 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 23:08:22.358374 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 23:08:22.361537 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 23:08:22.365029 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 23:08:22.371471 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 23:08:22.374955 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 23:08:22.378114 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 23:08:22.381214 ===================================
661 23:08:22.384317 LPDDR4 DRAM CONFIGURATION
662 23:08:22.387728 ===================================
663 23:08:22.387824 EX_ROW_EN[0] = 0x0
664 23:08:22.391538 EX_ROW_EN[1] = 0x0
665 23:08:22.394541 LP4Y_EN = 0x0
666 23:08:22.394644 WORK_FSP = 0x0
667 23:08:22.397863 WL = 0x2
668 23:08:22.397974 RL = 0x2
669 23:08:22.400913 BL = 0x2
670 23:08:22.401024 RPST = 0x0
671 23:08:22.404513 RD_PRE = 0x0
672 23:08:22.404635 WR_PRE = 0x1
673 23:08:22.407792 WR_PST = 0x0
674 23:08:22.407928 DBI_WR = 0x0
675 23:08:22.411395 DBI_RD = 0x0
676 23:08:22.411547 OTF = 0x1
677 23:08:22.414305 ===================================
678 23:08:22.418002 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 23:08:22.424895 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 23:08:22.427938 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 23:08:22.431164 ===================================
682 23:08:22.434718 LPDDR4 DRAM CONFIGURATION
683 23:08:22.438350 ===================================
684 23:08:22.438752 EX_ROW_EN[0] = 0x10
685 23:08:22.441484 EX_ROW_EN[1] = 0x0
686 23:08:22.441940 LP4Y_EN = 0x0
687 23:08:22.444670 WORK_FSP = 0x0
688 23:08:22.445090 WL = 0x2
689 23:08:22.448118 RL = 0x2
690 23:08:22.448540 BL = 0x2
691 23:08:22.451617 RPST = 0x0
692 23:08:22.452045 RD_PRE = 0x0
693 23:08:22.455147 WR_PRE = 0x1
694 23:08:22.455572 WR_PST = 0x0
695 23:08:22.458655 DBI_WR = 0x0
696 23:08:22.461361 DBI_RD = 0x0
697 23:08:22.461968 OTF = 0x1
698 23:08:22.465147 ===================================
699 23:08:22.471499 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 23:08:22.475108 nWR fixed to 40
701 23:08:22.478446 [ModeRegInit_LP4] CH0 RK0
702 23:08:22.478870 [ModeRegInit_LP4] CH0 RK1
703 23:08:22.481766 [ModeRegInit_LP4] CH1 RK0
704 23:08:22.485214 [ModeRegInit_LP4] CH1 RK1
705 23:08:22.485885 match AC timing 13
706 23:08:22.491753 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 23:08:22.494840 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 23:08:22.498356 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 23:08:22.505079 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 23:08:22.508593 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 23:08:22.509022 [EMI DOE] emi_dcm 0
712 23:08:22.515141 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 23:08:22.515570 ==
714 23:08:22.518775 Dram Type= 6, Freq= 0, CH_0, rank 0
715 23:08:22.521750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 23:08:22.522182 ==
717 23:08:22.528400 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 23:08:22.534863 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 23:08:22.542347 [CA 0] Center 36 (6~67) winsize 62
720 23:08:22.545675 [CA 1] Center 36 (6~67) winsize 62
721 23:08:22.548887 [CA 2] Center 34 (4~65) winsize 62
722 23:08:22.552022 [CA 3] Center 33 (3~64) winsize 62
723 23:08:22.555478 [CA 4] Center 33 (3~63) winsize 61
724 23:08:22.558924 [CA 5] Center 32 (2~62) winsize 61
725 23:08:22.559352
726 23:08:22.562161 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 23:08:22.562589
728 23:08:22.565844 [CATrainingPosCal] consider 1 rank data
729 23:08:22.568811 u2DelayCellTimex100 = 270/100 ps
730 23:08:22.571742 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
731 23:08:22.578171 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
732 23:08:22.582282 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
733 23:08:22.585407 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
734 23:08:22.588955 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
735 23:08:22.592569 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
736 23:08:22.593101
737 23:08:22.595551 CA PerBit enable=1, Macro0, CA PI delay=32
738 23:08:22.595972
739 23:08:22.599058 [CBTSetCACLKResult] CA Dly = 32
740 23:08:22.599559 CS Dly: 4 (0~35)
741 23:08:22.602815 ==
742 23:08:22.603341 Dram Type= 6, Freq= 0, CH_0, rank 1
743 23:08:22.609396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 23:08:22.610049 ==
745 23:08:22.612792 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 23:08:22.619221 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 23:08:22.628916 [CA 0] Center 36 (6~67) winsize 62
748 23:08:22.631894 [CA 1] Center 36 (6~67) winsize 62
749 23:08:22.635268 [CA 2] Center 34 (4~65) winsize 62
750 23:08:22.638622 [CA 3] Center 33 (3~64) winsize 62
751 23:08:22.642039 [CA 4] Center 33 (2~64) winsize 63
752 23:08:22.645302 [CA 5] Center 32 (2~63) winsize 62
753 23:08:22.645825
754 23:08:22.648382 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 23:08:22.649038
756 23:08:22.651911 [CATrainingPosCal] consider 2 rank data
757 23:08:22.654963 u2DelayCellTimex100 = 270/100 ps
758 23:08:22.658209 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
759 23:08:22.662021 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
760 23:08:22.668512 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
761 23:08:22.671881 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
762 23:08:22.674792 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
763 23:08:22.678676 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
764 23:08:22.679098
765 23:08:22.681689 CA PerBit enable=1, Macro0, CA PI delay=32
766 23:08:22.682110
767 23:08:22.685350 [CBTSetCACLKResult] CA Dly = 32
768 23:08:22.685828 CS Dly: 5 (0~37)
769 23:08:22.686197
770 23:08:22.688975 ----->DramcWriteLeveling(PI) begin...
771 23:08:22.691900 ==
772 23:08:22.692321 Dram Type= 6, Freq= 0, CH_0, rank 0
773 23:08:22.699655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 23:08:22.700082 ==
775 23:08:22.700418 Write leveling (Byte 0): 32 => 32
776 23:08:22.703975 Write leveling (Byte 1): 31 => 31
777 23:08:22.707626 DramcWriteLeveling(PI) end<-----
778 23:08:22.708043
779 23:08:22.708469 ==
780 23:08:22.711111 Dram Type= 6, Freq= 0, CH_0, rank 0
781 23:08:22.714101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 23:08:22.714525 ==
783 23:08:22.717569 [Gating] SW mode calibration
784 23:08:22.725135 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 23:08:22.728557 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 23:08:22.735315 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 23:08:22.738561 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
788 23:08:22.742472 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
789 23:08:22.748813 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
790 23:08:22.752521 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 23:08:22.755757 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 23:08:22.762255 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 23:08:22.765464 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 23:08:22.768774 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 23:08:22.775556 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 23:08:22.778506 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 23:08:22.782229 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 23:08:22.785377 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 23:08:22.792180 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 23:08:22.795331 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 23:08:22.798474 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 23:08:22.805069 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
803 23:08:22.808516 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
804 23:08:22.811879 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
805 23:08:22.818621 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 23:08:22.822063 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 23:08:22.825218 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 23:08:22.831962 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 23:08:22.835360 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 23:08:22.838425 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 23:08:22.845380 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 23:08:22.849296 0 9 8 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
813 23:08:22.852166 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
814 23:08:22.855557 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 23:08:22.862140 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 23:08:22.865391 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 23:08:22.869113 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 23:08:22.875560 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 23:08:22.878778 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
820 23:08:22.882373 0 10 8 | B1->B0 | 3030 2828 | 0 0 | (0 0) (0 0)
821 23:08:22.889104 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
822 23:08:22.892184 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 23:08:22.895428 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 23:08:22.901960 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 23:08:22.905602 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 23:08:22.909152 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 23:08:22.915634 0 11 4 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
828 23:08:22.918646 0 11 8 | B1->B0 | 2e2e 3a39 | 1 1 | (1 1) (0 0)
829 23:08:22.922552 0 11 12 | B1->B0 | 4141 4646 | 1 0 | (0 0) (0 0)
830 23:08:22.928935 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 23:08:22.932606 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 23:08:22.935507 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 23:08:22.938838 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 23:08:22.945598 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 23:08:22.949056 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 23:08:22.952489 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
837 23:08:22.959820 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
838 23:08:22.962775 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 23:08:22.966273 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 23:08:22.973114 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 23:08:22.976290 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 23:08:22.979709 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 23:08:22.986218 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 23:08:22.989183 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 23:08:22.992666 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 23:08:22.999985 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 23:08:23.003062 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 23:08:23.006137 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 23:08:23.012965 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 23:08:23.016512 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 23:08:23.019999 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 23:08:23.023460 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
853 23:08:23.029964 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
854 23:08:23.033108 Total UI for P1: 0, mck2ui 16
855 23:08:23.036414 best dqsien dly found for B0: ( 0, 14, 8)
856 23:08:23.036879 Total UI for P1: 0, mck2ui 16
857 23:08:23.042801 best dqsien dly found for B1: ( 0, 14, 8)
858 23:08:23.046737 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
859 23:08:23.050494 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
860 23:08:23.050914
861 23:08:23.053481 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
862 23:08:23.056741 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
863 23:08:23.060360 [Gating] SW calibration Done
864 23:08:23.060793 ==
865 23:08:23.063997 Dram Type= 6, Freq= 0, CH_0, rank 0
866 23:08:23.067300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 23:08:23.067737 ==
868 23:08:23.068180 RX Vref Scan: 0
869 23:08:23.068597
870 23:08:23.070379 RX Vref 0 -> 0, step: 1
871 23:08:23.070814
872 23:08:23.073965 RX Delay -130 -> 252, step: 16
873 23:08:23.077016 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
874 23:08:23.080398 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
875 23:08:23.087038 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
876 23:08:23.090607 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
877 23:08:23.094081 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
878 23:08:23.097482 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
879 23:08:23.100492 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
880 23:08:23.103759 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
881 23:08:23.110808 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
882 23:08:23.114183 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
883 23:08:23.117363 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
884 23:08:23.120408 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
885 23:08:23.123967 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
886 23:08:23.131364 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
887 23:08:23.134096 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
888 23:08:23.137666 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
889 23:08:23.138089 ==
890 23:08:23.141093 Dram Type= 6, Freq= 0, CH_0, rank 0
891 23:08:23.143876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 23:08:23.144348 ==
893 23:08:23.147632 DQS Delay:
894 23:08:23.148049 DQS0 = 0, DQS1 = 0
895 23:08:23.150720 DQM Delay:
896 23:08:23.151142 DQM0 = 88, DQM1 = 80
897 23:08:23.151481 DQ Delay:
898 23:08:23.154468 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
899 23:08:23.157304 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
900 23:08:23.160892 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
901 23:08:23.164500 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
902 23:08:23.165094
903 23:08:23.165451
904 23:08:23.167420 ==
905 23:08:23.167969 Dram Type= 6, Freq= 0, CH_0, rank 0
906 23:08:23.174241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 23:08:23.174688 ==
908 23:08:23.175025
909 23:08:23.175338
910 23:08:23.178106 TX Vref Scan disable
911 23:08:23.178529 == TX Byte 0 ==
912 23:08:23.180836 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
913 23:08:23.187443 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
914 23:08:23.187865 == TX Byte 1 ==
915 23:08:23.190782 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
916 23:08:23.197361 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
917 23:08:23.197835 ==
918 23:08:23.201025 Dram Type= 6, Freq= 0, CH_0, rank 0
919 23:08:23.204392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 23:08:23.204815 ==
921 23:08:23.217324 TX Vref=22, minBit 8, minWin=27, winSum=446
922 23:08:23.220462 TX Vref=24, minBit 10, minWin=27, winSum=448
923 23:08:23.224070 TX Vref=26, minBit 0, minWin=28, winSum=455
924 23:08:23.227031 TX Vref=28, minBit 7, minWin=28, winSum=457
925 23:08:23.230113 TX Vref=30, minBit 5, minWin=28, winSum=458
926 23:08:23.237242 TX Vref=32, minBit 12, minWin=27, winSum=457
927 23:08:23.240493 [TxChooseVref] Worse bit 5, Min win 28, Win sum 458, Final Vref 30
928 23:08:23.240913
929 23:08:23.244545 Final TX Range 1 Vref 30
930 23:08:23.245071
931 23:08:23.245412 ==
932 23:08:23.247307 Dram Type= 6, Freq= 0, CH_0, rank 0
933 23:08:23.250428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 23:08:23.250850 ==
935 23:08:23.253909
936 23:08:23.254436
937 23:08:23.254890 TX Vref Scan disable
938 23:08:23.257378 == TX Byte 0 ==
939 23:08:23.260662 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
940 23:08:23.264313 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
941 23:08:23.267139 == TX Byte 1 ==
942 23:08:23.270418 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
943 23:08:23.273966 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
944 23:08:23.277854
945 23:08:23.278268 [DATLAT]
946 23:08:23.278599 Freq=800, CH0 RK0
947 23:08:23.278910
948 23:08:23.280443 DATLAT Default: 0xa
949 23:08:23.280858 0, 0xFFFF, sum = 0
950 23:08:23.284184 1, 0xFFFF, sum = 0
951 23:08:23.284608 2, 0xFFFF, sum = 0
952 23:08:23.287951 3, 0xFFFF, sum = 0
953 23:08:23.288375 4, 0xFFFF, sum = 0
954 23:08:23.290778 5, 0xFFFF, sum = 0
955 23:08:23.291198 6, 0xFFFF, sum = 0
956 23:08:23.293871 7, 0xFFFF, sum = 0
957 23:08:23.297476 8, 0xFFFF, sum = 0
958 23:08:23.297960 9, 0x0, sum = 1
959 23:08:23.298302 10, 0x0, sum = 2
960 23:08:23.300483 11, 0x0, sum = 3
961 23:08:23.300903 12, 0x0, sum = 4
962 23:08:23.304311 best_step = 10
963 23:08:23.304727
964 23:08:23.305058 ==
965 23:08:23.307381 Dram Type= 6, Freq= 0, CH_0, rank 0
966 23:08:23.311035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 23:08:23.311560 ==
968 23:08:23.314031 RX Vref Scan: 1
969 23:08:23.314446
970 23:08:23.314824 Set Vref Range= 32 -> 127
971 23:08:23.315138
972 23:08:23.317975 RX Vref 32 -> 127, step: 1
973 23:08:23.318395
974 23:08:23.320743 RX Delay -95 -> 252, step: 8
975 23:08:23.321161
976 23:08:23.324020 Set Vref, RX VrefLevel [Byte0]: 32
977 23:08:23.327596 [Byte1]: 32
978 23:08:23.328016
979 23:08:23.330421 Set Vref, RX VrefLevel [Byte0]: 33
980 23:08:23.334157 [Byte1]: 33
981 23:08:23.337444
982 23:08:23.337916 Set Vref, RX VrefLevel [Byte0]: 34
983 23:08:23.340842 [Byte1]: 34
984 23:08:23.345489
985 23:08:23.345982 Set Vref, RX VrefLevel [Byte0]: 35
986 23:08:23.348243 [Byte1]: 35
987 23:08:23.352301
988 23:08:23.352383 Set Vref, RX VrefLevel [Byte0]: 36
989 23:08:23.356161 [Byte1]: 36
990 23:08:23.360311
991 23:08:23.360406 Set Vref, RX VrefLevel [Byte0]: 37
992 23:08:23.363935 [Byte1]: 37
993 23:08:23.368110
994 23:08:23.368234 Set Vref, RX VrefLevel [Byte0]: 38
995 23:08:23.371373 [Byte1]: 38
996 23:08:23.375796
997 23:08:23.375904 Set Vref, RX VrefLevel [Byte0]: 39
998 23:08:23.379470 [Byte1]: 39
999 23:08:23.383389
1000 23:08:23.383476 Set Vref, RX VrefLevel [Byte0]: 40
1001 23:08:23.386407 [Byte1]: 40
1002 23:08:23.390648
1003 23:08:23.390742 Set Vref, RX VrefLevel [Byte0]: 41
1004 23:08:23.393953 [Byte1]: 41
1005 23:08:23.397955
1006 23:08:23.398057 Set Vref, RX VrefLevel [Byte0]: 42
1007 23:08:23.401820 [Byte1]: 42
1008 23:08:23.405920
1009 23:08:23.406122 Set Vref, RX VrefLevel [Byte0]: 43
1010 23:08:23.409083 [Byte1]: 43
1011 23:08:23.413435
1012 23:08:23.413678 Set Vref, RX VrefLevel [Byte0]: 44
1013 23:08:23.417187 [Byte1]: 44
1014 23:08:23.421345
1015 23:08:23.421639 Set Vref, RX VrefLevel [Byte0]: 45
1016 23:08:23.424250 [Byte1]: 45
1017 23:08:23.428728
1018 23:08:23.429017 Set Vref, RX VrefLevel [Byte0]: 46
1019 23:08:23.432265 [Byte1]: 46
1020 23:08:23.436236
1021 23:08:23.436574 Set Vref, RX VrefLevel [Byte0]: 47
1022 23:08:23.440027 [Byte1]: 47
1023 23:08:23.444033
1024 23:08:23.444506 Set Vref, RX VrefLevel [Byte0]: 48
1025 23:08:23.447380 [Byte1]: 48
1026 23:08:23.452246
1027 23:08:23.452808 Set Vref, RX VrefLevel [Byte0]: 49
1028 23:08:23.454951 [Byte1]: 49
1029 23:08:23.458978
1030 23:08:23.459429 Set Vref, RX VrefLevel [Byte0]: 50
1031 23:08:23.462570 [Byte1]: 50
1032 23:08:23.466910
1033 23:08:23.467477 Set Vref, RX VrefLevel [Byte0]: 51
1034 23:08:23.470201 [Byte1]: 51
1035 23:08:23.474526
1036 23:08:23.474978 Set Vref, RX VrefLevel [Byte0]: 52
1037 23:08:23.477793 [Byte1]: 52
1038 23:08:23.482553
1039 23:08:23.483100 Set Vref, RX VrefLevel [Byte0]: 53
1040 23:08:23.485652 [Byte1]: 53
1041 23:08:23.489949
1042 23:08:23.490405 Set Vref, RX VrefLevel [Byte0]: 54
1043 23:08:23.492976 [Byte1]: 54
1044 23:08:23.496883
1045 23:08:23.497334 Set Vref, RX VrefLevel [Byte0]: 55
1046 23:08:23.500803 [Byte1]: 55
1047 23:08:23.504777
1048 23:08:23.505239 Set Vref, RX VrefLevel [Byte0]: 56
1049 23:08:23.508146 [Byte1]: 56
1050 23:08:23.512809
1051 23:08:23.513381 Set Vref, RX VrefLevel [Byte0]: 57
1052 23:08:23.516053 [Byte1]: 57
1053 23:08:23.520325
1054 23:08:23.520872 Set Vref, RX VrefLevel [Byte0]: 58
1055 23:08:23.524098 [Byte1]: 58
1056 23:08:23.527914
1057 23:08:23.528384 Set Vref, RX VrefLevel [Byte0]: 59
1058 23:08:23.530890 [Byte1]: 59
1059 23:08:23.535214
1060 23:08:23.535823 Set Vref, RX VrefLevel [Byte0]: 60
1061 23:08:23.538875 [Byte1]: 60
1062 23:08:23.542595
1063 23:08:23.543102 Set Vref, RX VrefLevel [Byte0]: 61
1064 23:08:23.546157 [Byte1]: 61
1065 23:08:23.550750
1066 23:08:23.551202 Set Vref, RX VrefLevel [Byte0]: 62
1067 23:08:23.553707 [Byte1]: 62
1068 23:08:23.557963
1069 23:08:23.558417 Set Vref, RX VrefLevel [Byte0]: 63
1070 23:08:23.561563 [Byte1]: 63
1071 23:08:23.565685
1072 23:08:23.566230 Set Vref, RX VrefLevel [Byte0]: 64
1073 23:08:23.569322 [Byte1]: 64
1074 23:08:23.573228
1075 23:08:23.573739 Set Vref, RX VrefLevel [Byte0]: 65
1076 23:08:23.576585 [Byte1]: 65
1077 23:08:23.580537
1078 23:08:23.581087 Set Vref, RX VrefLevel [Byte0]: 66
1079 23:08:23.584138 [Byte1]: 66
1080 23:08:23.588692
1081 23:08:23.589177 Set Vref, RX VrefLevel [Byte0]: 67
1082 23:08:23.591565 [Byte1]: 67
1083 23:08:23.596180
1084 23:08:23.596725 Set Vref, RX VrefLevel [Byte0]: 68
1085 23:08:23.599913 [Byte1]: 68
1086 23:08:23.603955
1087 23:08:23.604503 Set Vref, RX VrefLevel [Byte0]: 69
1088 23:08:23.606913 [Byte1]: 69
1089 23:08:23.611312
1090 23:08:23.611763 Set Vref, RX VrefLevel [Byte0]: 70
1091 23:08:23.614242 [Byte1]: 70
1092 23:08:23.618826
1093 23:08:23.619366 Set Vref, RX VrefLevel [Byte0]: 71
1094 23:08:23.622158 [Byte1]: 71
1095 23:08:23.626569
1096 23:08:23.627116 Set Vref, RX VrefLevel [Byte0]: 72
1097 23:08:23.629673 [Byte1]: 72
1098 23:08:23.633793
1099 23:08:23.634247 Set Vref, RX VrefLevel [Byte0]: 73
1100 23:08:23.637142 [Byte1]: 73
1101 23:08:23.642126
1102 23:08:23.642682 Set Vref, RX VrefLevel [Byte0]: 74
1103 23:08:23.645041 [Byte1]: 74
1104 23:08:23.649065
1105 23:08:23.649634 Set Vref, RX VrefLevel [Byte0]: 75
1106 23:08:23.652451 [Byte1]: 75
1107 23:08:23.656789
1108 23:08:23.657333 Set Vref, RX VrefLevel [Byte0]: 76
1109 23:08:23.660558 [Byte1]: 76
1110 23:08:23.664950
1111 23:08:23.665507 Set Vref, RX VrefLevel [Byte0]: 77
1112 23:08:23.667567 [Byte1]: 77
1113 23:08:23.672144
1114 23:08:23.672777 Final RX Vref Byte 0 = 59 to rank0
1115 23:08:23.675454 Final RX Vref Byte 1 = 55 to rank0
1116 23:08:23.678916 Final RX Vref Byte 0 = 59 to rank1
1117 23:08:23.681982 Final RX Vref Byte 1 = 55 to rank1==
1118 23:08:23.685336 Dram Type= 6, Freq= 0, CH_0, rank 0
1119 23:08:23.688872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1120 23:08:23.691863 ==
1121 23:08:23.692335 DQS Delay:
1122 23:08:23.692695 DQS0 = 0, DQS1 = 0
1123 23:08:23.695396 DQM Delay:
1124 23:08:23.695848 DQM0 = 92, DQM1 = 85
1125 23:08:23.699312 DQ Delay:
1126 23:08:23.699946 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1127 23:08:23.702141 DQ4 =96, DQ5 =80, DQ6 =100, DQ7 =100
1128 23:08:23.705772 DQ8 =72, DQ9 =76, DQ10 =88, DQ11 =76
1129 23:08:23.708788 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92
1130 23:08:23.709431
1131 23:08:23.712665
1132 23:08:23.719405 [DQSOSCAuto] RK0, (LSB)MR18= 0x483f, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
1133 23:08:23.722766 CH0 RK0: MR19=606, MR18=483F
1134 23:08:23.728866 CH0_RK0: MR19=0x606, MR18=0x483F, DQSOSC=391, MR23=63, INC=96, DEC=64
1135 23:08:23.729325
1136 23:08:23.732284 ----->DramcWriteLeveling(PI) begin...
1137 23:08:23.732859 ==
1138 23:08:23.735751 Dram Type= 6, Freq= 0, CH_0, rank 1
1139 23:08:23.739594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1140 23:08:23.740151 ==
1141 23:08:23.742572 Write leveling (Byte 0): 33 => 33
1142 23:08:23.745797 Write leveling (Byte 1): 31 => 31
1143 23:08:23.749291 DramcWriteLeveling(PI) end<-----
1144 23:08:23.749870
1145 23:08:23.750233 ==
1146 23:08:23.752423 Dram Type= 6, Freq= 0, CH_0, rank 1
1147 23:08:23.755931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1148 23:08:23.756534 ==
1149 23:08:23.759643 [Gating] SW mode calibration
1150 23:08:23.765938 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1151 23:08:23.810511 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1152 23:08:23.811095 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1153 23:08:23.811834 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1154 23:08:23.812234 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1155 23:08:23.812572 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 23:08:23.812898 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 23:08:23.813216 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 23:08:23.813524 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 23:08:23.813874 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 23:08:23.814182 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 23:08:23.853942 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 23:08:23.854610 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 23:08:23.854935 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 23:08:23.855175 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 23:08:23.855395 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 23:08:23.855711 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 23:08:23.856087 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 23:08:23.856374 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 23:08:23.856598 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 23:08:23.856943 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 23:08:23.879655 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1172 23:08:23.879911 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 23:08:23.880298 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 23:08:23.880444 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 23:08:23.880575 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 23:08:23.883443 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 23:08:23.886514 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 23:08:23.889849 0 9 8 | B1->B0 | 2f2f 2828 | 0 0 | (0 0) (1 1)
1179 23:08:23.893454 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 23:08:23.896742 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 23:08:23.903174 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 23:08:23.906448 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 23:08:23.909807 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 23:08:23.916249 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 23:08:23.920022 0 10 4 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
1186 23:08:23.923448 0 10 8 | B1->B0 | 2929 2b2b | 0 0 | (0 0) (0 1)
1187 23:08:23.929702 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 23:08:23.933366 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 23:08:23.936742 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 23:08:23.941068 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 23:08:23.945572 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 23:08:23.952424 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 23:08:23.956297 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 23:08:23.959168 0 11 8 | B1->B0 | 4141 3b3b | 0 1 | (0 0) (0 0)
1195 23:08:23.962722 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 23:08:23.969930 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 23:08:23.973555 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 23:08:23.977150 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 23:08:23.983753 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 23:08:23.987000 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 23:08:23.990073 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 23:08:23.996679 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1203 23:08:23.999998 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 23:08:24.003537 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 23:08:24.006534 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 23:08:24.013632 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 23:08:24.017012 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 23:08:24.020033 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 23:08:24.026667 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 23:08:24.030244 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 23:08:24.033565 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 23:08:24.040245 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 23:08:24.043328 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 23:08:24.047277 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 23:08:24.053549 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 23:08:24.056450 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 23:08:24.059947 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 23:08:24.066749 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1219 23:08:24.070396 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1220 23:08:24.073226 Total UI for P1: 0, mck2ui 16
1221 23:08:24.076769 best dqsien dly found for B0: ( 0, 14, 8)
1222 23:08:24.079937 Total UI for P1: 0, mck2ui 16
1223 23:08:24.083565 best dqsien dly found for B1: ( 0, 14, 8)
1224 23:08:24.086448 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1225 23:08:24.090072 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1226 23:08:24.090652
1227 23:08:24.093135 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1228 23:08:24.097059 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1229 23:08:24.100459 [Gating] SW calibration Done
1230 23:08:24.100975 ==
1231 23:08:24.103601 Dram Type= 6, Freq= 0, CH_0, rank 1
1232 23:08:24.107395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1233 23:08:24.107919 ==
1234 23:08:24.110171 RX Vref Scan: 0
1235 23:08:24.110586
1236 23:08:24.110914 RX Vref 0 -> 0, step: 1
1237 23:08:24.113474
1238 23:08:24.114080 RX Delay -130 -> 252, step: 16
1239 23:08:24.120460 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1240 23:08:24.124126 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1241 23:08:24.127302 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1242 23:08:24.129890 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1243 23:08:24.133694 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1244 23:08:24.140328 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1245 23:08:24.143346 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1246 23:08:24.146722 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1247 23:08:24.150146 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1248 23:08:24.153346 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1249 23:08:24.159966 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1250 23:08:24.163634 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1251 23:08:24.167395 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1252 23:08:24.170279 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1253 23:08:24.173869 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1254 23:08:24.180611 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1255 23:08:24.181035 ==
1256 23:08:24.183587 Dram Type= 6, Freq= 0, CH_0, rank 1
1257 23:08:24.187004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1258 23:08:24.187591 ==
1259 23:08:24.188095 DQS Delay:
1260 23:08:24.190021 DQS0 = 0, DQS1 = 0
1261 23:08:24.190583 DQM Delay:
1262 23:08:24.193401 DQM0 = 91, DQM1 = 82
1263 23:08:24.193912 DQ Delay:
1264 23:08:24.197089 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
1265 23:08:24.200645 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =101
1266 23:08:24.203622 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
1267 23:08:24.206842 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
1268 23:08:24.207312
1269 23:08:24.207761
1270 23:08:24.208252 ==
1271 23:08:24.210194 Dram Type= 6, Freq= 0, CH_0, rank 1
1272 23:08:24.213906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1273 23:08:24.214332 ==
1274 23:08:24.214665
1275 23:08:24.214974
1276 23:08:24.217674 TX Vref Scan disable
1277 23:08:24.220655 == TX Byte 0 ==
1278 23:08:24.224007 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1279 23:08:24.226854 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1280 23:08:24.230397 == TX Byte 1 ==
1281 23:08:24.234246 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1282 23:08:24.237125 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1283 23:08:24.237743 ==
1284 23:08:24.240376 Dram Type= 6, Freq= 0, CH_0, rank 1
1285 23:08:24.246679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1286 23:08:24.247135 ==
1287 23:08:24.258720 TX Vref=22, minBit 12, minWin=27, winSum=450
1288 23:08:24.262091 TX Vref=24, minBit 13, minWin=27, winSum=451
1289 23:08:24.265360 TX Vref=26, minBit 1, minWin=28, winSum=455
1290 23:08:24.269101 TX Vref=28, minBit 5, minWin=28, winSum=456
1291 23:08:24.272220 TX Vref=30, minBit 7, minWin=28, winSum=460
1292 23:08:24.278793 TX Vref=32, minBit 2, minWin=28, winSum=456
1293 23:08:24.281898 [TxChooseVref] Worse bit 7, Min win 28, Win sum 460, Final Vref 30
1294 23:08:24.282307
1295 23:08:24.285902 Final TX Range 1 Vref 30
1296 23:08:24.286310
1297 23:08:24.286628 ==
1298 23:08:24.288851 Dram Type= 6, Freq= 0, CH_0, rank 1
1299 23:08:24.292204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1300 23:08:24.292616 ==
1301 23:08:24.292939
1302 23:08:24.293240
1303 23:08:24.295816 TX Vref Scan disable
1304 23:08:24.298644 == TX Byte 0 ==
1305 23:08:24.302199 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1306 23:08:24.305396 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1307 23:08:24.309086 == TX Byte 1 ==
1308 23:08:24.312258 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1309 23:08:24.315648 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1310 23:08:24.318595
1311 23:08:24.319003 [DATLAT]
1312 23:08:24.319329 Freq=800, CH0 RK1
1313 23:08:24.319632
1314 23:08:24.322165 DATLAT Default: 0xa
1315 23:08:24.322656 0, 0xFFFF, sum = 0
1316 23:08:24.325286 1, 0xFFFF, sum = 0
1317 23:08:24.325736 2, 0xFFFF, sum = 0
1318 23:08:24.329216 3, 0xFFFF, sum = 0
1319 23:08:24.329820 4, 0xFFFF, sum = 0
1320 23:08:24.332254 5, 0xFFFF, sum = 0
1321 23:08:24.335363 6, 0xFFFF, sum = 0
1322 23:08:24.335882 7, 0xFFFF, sum = 0
1323 23:08:24.339084 8, 0xFFFF, sum = 0
1324 23:08:24.339500 9, 0x0, sum = 1
1325 23:08:24.339831 10, 0x0, sum = 2
1326 23:08:24.342126 11, 0x0, sum = 3
1327 23:08:24.342544 12, 0x0, sum = 4
1328 23:08:24.345243 best_step = 10
1329 23:08:24.345687
1330 23:08:24.346014 ==
1331 23:08:24.349112 Dram Type= 6, Freq= 0, CH_0, rank 1
1332 23:08:24.351864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1333 23:08:24.352275 ==
1334 23:08:24.355308 RX Vref Scan: 0
1335 23:08:24.355712
1336 23:08:24.356029 RX Vref 0 -> 0, step: 1
1337 23:08:24.356338
1338 23:08:24.358938 RX Delay -79 -> 252, step: 8
1339 23:08:24.365226 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1340 23:08:24.368938 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1341 23:08:24.372182 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1342 23:08:24.375260 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1343 23:08:24.378912 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1344 23:08:24.385770 iDelay=209, Bit 5, Center 88 (-23 ~ 200) 224
1345 23:08:24.388333 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1346 23:08:24.391860 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1347 23:08:24.394785 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1348 23:08:24.398245 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
1349 23:08:24.404879 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1350 23:08:24.408576 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1351 23:08:24.411539 iDelay=209, Bit 12, Center 88 (-15 ~ 192) 208
1352 23:08:24.415115 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
1353 23:08:24.418479 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1354 23:08:24.425005 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1355 23:08:24.425157 ==
1356 23:08:24.428569 Dram Type= 6, Freq= 0, CH_0, rank 1
1357 23:08:24.431472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1358 23:08:24.431552 ==
1359 23:08:24.431617 DQS Delay:
1360 23:08:24.434671 DQS0 = 0, DQS1 = 0
1361 23:08:24.434751 DQM Delay:
1362 23:08:24.438100 DQM0 = 93, DQM1 = 83
1363 23:08:24.438194 DQ Delay:
1364 23:08:24.441636 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1365 23:08:24.445511 DQ4 =92, DQ5 =88, DQ6 =100, DQ7 =100
1366 23:08:24.448455 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =76
1367 23:08:24.452051 DQ12 =88, DQ13 =88, DQ14 =92, DQ15 =92
1368 23:08:24.452150
1369 23:08:24.452229
1370 23:08:24.458670 [DQSOSCAuto] RK1, (LSB)MR18= 0x4112, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
1371 23:08:24.461628 CH0 RK1: MR19=606, MR18=4112
1372 23:08:24.468776 CH0_RK1: MR19=0x606, MR18=0x4112, DQSOSC=393, MR23=63, INC=95, DEC=63
1373 23:08:24.471790 [RxdqsGatingPostProcess] freq 800
1374 23:08:24.479076 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1375 23:08:24.479313 Pre-setting of DQS Precalculation
1376 23:08:24.485397 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1377 23:08:24.485658 ==
1378 23:08:24.489161 Dram Type= 6, Freq= 0, CH_1, rank 0
1379 23:08:24.492152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1380 23:08:24.492448 ==
1381 23:08:24.499332 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1382 23:08:24.505895 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1383 23:08:24.514067 [CA 0] Center 36 (6~67) winsize 62
1384 23:08:24.516962 [CA 1] Center 36 (6~67) winsize 62
1385 23:08:24.520664 [CA 2] Center 35 (5~66) winsize 62
1386 23:08:24.524072 [CA 3] Center 34 (4~65) winsize 62
1387 23:08:24.527559 [CA 4] Center 35 (5~65) winsize 61
1388 23:08:24.530415 [CA 5] Center 34 (4~65) winsize 62
1389 23:08:24.530843
1390 23:08:24.533847 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1391 23:08:24.534277
1392 23:08:24.537536 [CATrainingPosCal] consider 1 rank data
1393 23:08:24.540442 u2DelayCellTimex100 = 270/100 ps
1394 23:08:24.544133 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1395 23:08:24.547200 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1396 23:08:24.554021 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1397 23:08:24.557292 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1398 23:08:24.560501 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1399 23:08:24.564387 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1400 23:08:24.564921
1401 23:08:24.567213 CA PerBit enable=1, Macro0, CA PI delay=34
1402 23:08:24.567795
1403 23:08:24.570443 [CBTSetCACLKResult] CA Dly = 34
1404 23:08:24.570912 CS Dly: 6 (0~37)
1405 23:08:24.571323 ==
1406 23:08:24.574250 Dram Type= 6, Freq= 0, CH_1, rank 1
1407 23:08:24.580772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1408 23:08:24.581199 ==
1409 23:08:24.584580 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1410 23:08:24.590584 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1411 23:08:24.600295 [CA 0] Center 36 (6~67) winsize 62
1412 23:08:24.604283 [CA 1] Center 37 (6~68) winsize 63
1413 23:08:24.607800 [CA 2] Center 35 (5~66) winsize 62
1414 23:08:24.611494 [CA 3] Center 35 (5~65) winsize 61
1415 23:08:24.615652 [CA 4] Center 35 (5~66) winsize 62
1416 23:08:24.616166 [CA 5] Center 34 (4~65) winsize 62
1417 23:08:24.616506
1418 23:08:24.619256 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1419 23:08:24.622700
1420 23:08:24.623119 [CATrainingPosCal] consider 2 rank data
1421 23:08:24.626944 u2DelayCellTimex100 = 270/100 ps
1422 23:08:24.630401 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1423 23:08:24.633955 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1424 23:08:24.637960 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1425 23:08:24.640911 CA3 delay=35 (5~65),Diff = 1 PI (7 cell)
1426 23:08:24.644803 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1427 23:08:24.647986 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1428 23:08:24.648829
1429 23:08:24.654389 CA PerBit enable=1, Macro0, CA PI delay=34
1430 23:08:24.654873
1431 23:08:24.657782 [CBTSetCACLKResult] CA Dly = 34
1432 23:08:24.658204 CS Dly: 6 (0~38)
1433 23:08:24.658786
1434 23:08:24.661642 ----->DramcWriteLeveling(PI) begin...
1435 23:08:24.662063 ==
1436 23:08:24.664531 Dram Type= 6, Freq= 0, CH_1, rank 0
1437 23:08:24.668130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1438 23:08:24.668646 ==
1439 23:08:24.671200 Write leveling (Byte 0): 27 => 27
1440 23:08:24.674518 Write leveling (Byte 1): 27 => 27
1441 23:08:24.677666 DramcWriteLeveling(PI) end<-----
1442 23:08:24.678087
1443 23:08:24.678515 ==
1444 23:08:24.681480 Dram Type= 6, Freq= 0, CH_1, rank 0
1445 23:08:24.685221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1446 23:08:24.687969 ==
1447 23:08:24.688399 [Gating] SW mode calibration
1448 23:08:24.698010 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1449 23:08:24.701899 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1450 23:08:24.704644 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1451 23:08:24.710809 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1452 23:08:24.714295 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 23:08:24.717648 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 23:08:24.724622 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 23:08:24.727967 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 23:08:24.731093 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 23:08:24.738172 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 23:08:24.741660 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 23:08:24.744822 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 23:08:24.748221 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 23:08:24.754825 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 23:08:24.757787 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 23:08:24.761305 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 23:08:24.768292 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 23:08:24.771437 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 23:08:24.774650 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1467 23:08:24.781677 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1468 23:08:24.784530 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 23:08:24.788197 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 23:08:24.794650 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 23:08:24.798402 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 23:08:24.801511 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 23:08:24.808478 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 23:08:24.811487 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 23:08:24.815173 0 9 4 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
1476 23:08:24.818784 0 9 8 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
1477 23:08:24.825204 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 23:08:24.828351 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 23:08:24.831434 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 23:08:24.838344 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 23:08:24.841834 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 23:08:24.845230 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 23:08:24.851801 0 10 4 | B1->B0 | 3030 2a2a | 1 1 | (1 0) (1 0)
1484 23:08:24.855166 0 10 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1485 23:08:24.858125 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 23:08:24.865309 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 23:08:24.868466 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 23:08:24.871733 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 23:08:24.878758 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 23:08:24.881434 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 23:08:24.885320 0 11 4 | B1->B0 | 2727 3535 | 0 1 | (0 0) (0 0)
1492 23:08:24.892284 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 23:08:24.895342 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 23:08:24.898678 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 23:08:24.902325 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 23:08:24.908350 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 23:08:24.911952 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 23:08:24.915596 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1499 23:08:24.922292 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1500 23:08:24.925621 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 23:08:24.928949 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 23:08:24.935438 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 23:08:24.938813 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 23:08:24.942448 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 23:08:24.948717 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 23:08:24.952360 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 23:08:24.955783 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 23:08:24.962210 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 23:08:24.965386 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 23:08:24.968988 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 23:08:24.975675 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 23:08:24.979083 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 23:08:24.982106 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 23:08:24.985543 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1515 23:08:24.992251 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1516 23:08:24.995725 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1517 23:08:24.998708 Total UI for P1: 0, mck2ui 16
1518 23:08:25.002121 best dqsien dly found for B0: ( 0, 14, 2)
1519 23:08:25.005917 Total UI for P1: 0, mck2ui 16
1520 23:08:25.008769 best dqsien dly found for B1: ( 0, 14, 4)
1521 23:08:25.012261 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1522 23:08:25.015466 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1523 23:08:25.015885
1524 23:08:25.018811 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1525 23:08:25.022180 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1526 23:08:25.025410 [Gating] SW calibration Done
1527 23:08:25.025877 ==
1528 23:08:25.029148 Dram Type= 6, Freq= 0, CH_1, rank 0
1529 23:08:25.032300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1530 23:08:25.032724 ==
1531 23:08:25.035873 RX Vref Scan: 0
1532 23:08:25.036292
1533 23:08:25.039012 RX Vref 0 -> 0, step: 1
1534 23:08:25.039430
1535 23:08:25.042670 RX Delay -130 -> 252, step: 16
1536 23:08:25.045301 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1537 23:08:25.048806 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1538 23:08:25.052591 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1539 23:08:25.055832 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1540 23:08:25.059227 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1541 23:08:25.065659 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1542 23:08:25.069231 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1543 23:08:25.072191 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1544 23:08:25.076050 iDelay=222, Bit 8, Center 85 (-18 ~ 189) 208
1545 23:08:25.079374 iDelay=222, Bit 9, Center 85 (-18 ~ 189) 208
1546 23:08:25.085691 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1547 23:08:25.088905 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1548 23:08:25.092681 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1549 23:08:25.095846 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1550 23:08:25.098707 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1551 23:08:25.105774 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1552 23:08:25.106071 ==
1553 23:08:25.108840 Dram Type= 6, Freq= 0, CH_1, rank 0
1554 23:08:25.112432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1555 23:08:25.112730 ==
1556 23:08:25.112965 DQS Delay:
1557 23:08:25.115914 DQS0 = 0, DQS1 = 0
1558 23:08:25.116211 DQM Delay:
1559 23:08:25.119013 DQM0 = 94, DQM1 = 90
1560 23:08:25.119308 DQ Delay:
1561 23:08:25.122310 DQ0 =93, DQ1 =85, DQ2 =85, DQ3 =93
1562 23:08:25.125689 DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =93
1563 23:08:25.128873 DQ8 =85, DQ9 =85, DQ10 =85, DQ11 =85
1564 23:08:25.132501 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =101
1565 23:08:25.132801
1566 23:08:25.133036
1567 23:08:25.133255 ==
1568 23:08:25.135808 Dram Type= 6, Freq= 0, CH_1, rank 0
1569 23:08:25.139067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1570 23:08:25.142587 ==
1571 23:08:25.142884
1572 23:08:25.143120
1573 23:08:25.143343 TX Vref Scan disable
1574 23:08:25.145512 == TX Byte 0 ==
1575 23:08:25.149481 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1576 23:08:25.152682 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1577 23:08:25.155853 == TX Byte 1 ==
1578 23:08:25.159000 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1579 23:08:25.162203 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1580 23:08:25.162509 ==
1581 23:08:25.166173 Dram Type= 6, Freq= 0, CH_1, rank 0
1582 23:08:25.172900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1583 23:08:25.173198 ==
1584 23:08:25.185359 TX Vref=22, minBit 0, minWin=26, winSum=432
1585 23:08:25.188446 TX Vref=24, minBit 1, minWin=27, winSum=443
1586 23:08:25.191892 TX Vref=26, minBit 3, minWin=26, winSum=443
1587 23:08:25.195398 TX Vref=28, minBit 1, minWin=27, winSum=448
1588 23:08:25.198462 TX Vref=30, minBit 1, minWin=27, winSum=449
1589 23:08:25.202214 TX Vref=32, minBit 0, minWin=27, winSum=445
1590 23:08:25.208733 [TxChooseVref] Worse bit 1, Min win 27, Win sum 449, Final Vref 30
1591 23:08:25.209034
1592 23:08:25.211654 Final TX Range 1 Vref 30
1593 23:08:25.211954
1594 23:08:25.212188 ==
1595 23:08:25.215310 Dram Type= 6, Freq= 0, CH_1, rank 0
1596 23:08:25.218274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1597 23:08:25.218499 ==
1598 23:08:25.218678
1599 23:08:25.218844
1600 23:08:25.221714 TX Vref Scan disable
1601 23:08:25.225240 == TX Byte 0 ==
1602 23:08:25.228502 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1603 23:08:25.231946 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1604 23:08:25.235575 == TX Byte 1 ==
1605 23:08:25.238343 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1606 23:08:25.241629 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1607 23:08:25.241857
1608 23:08:25.242037 [DATLAT]
1609 23:08:25.245396 Freq=800, CH1 RK0
1610 23:08:25.245643
1611 23:08:25.248670 DATLAT Default: 0xa
1612 23:08:25.248893 0, 0xFFFF, sum = 0
1613 23:08:25.251950 1, 0xFFFF, sum = 0
1614 23:08:25.252176 2, 0xFFFF, sum = 0
1615 23:08:25.255309 3, 0xFFFF, sum = 0
1616 23:08:25.255536 4, 0xFFFF, sum = 0
1617 23:08:25.258751 5, 0xFFFF, sum = 0
1618 23:08:25.258978 6, 0xFFFF, sum = 0
1619 23:08:25.261654 7, 0xFFFF, sum = 0
1620 23:08:25.261883 8, 0xFFFF, sum = 0
1621 23:08:25.265483 9, 0x0, sum = 1
1622 23:08:25.265759 10, 0x0, sum = 2
1623 23:08:25.268913 11, 0x0, sum = 3
1624 23:08:25.269190 12, 0x0, sum = 4
1625 23:08:25.269413 best_step = 10
1626 23:08:25.269650
1627 23:08:25.272121 ==
1628 23:08:25.275212 Dram Type= 6, Freq= 0, CH_1, rank 0
1629 23:08:25.278481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1630 23:08:25.278835 ==
1631 23:08:25.279117 RX Vref Scan: 1
1632 23:08:25.279384
1633 23:08:25.281763 Set Vref Range= 32 -> 127
1634 23:08:25.282119
1635 23:08:25.285422 RX Vref 32 -> 127, step: 1
1636 23:08:25.285826
1637 23:08:25.288907 RX Delay -63 -> 252, step: 8
1638 23:08:25.289261
1639 23:08:25.292223 Set Vref, RX VrefLevel [Byte0]: 32
1640 23:08:25.295532 [Byte1]: 32
1641 23:08:25.295891
1642 23:08:25.298776 Set Vref, RX VrefLevel [Byte0]: 33
1643 23:08:25.302219 [Byte1]: 33
1644 23:08:25.302621
1645 23:08:25.305322 Set Vref, RX VrefLevel [Byte0]: 34
1646 23:08:25.308831 [Byte1]: 34
1647 23:08:25.309185
1648 23:08:25.311881 Set Vref, RX VrefLevel [Byte0]: 35
1649 23:08:25.315527 [Byte1]: 35
1650 23:08:25.319026
1651 23:08:25.319379 Set Vref, RX VrefLevel [Byte0]: 36
1652 23:08:25.322739 [Byte1]: 36
1653 23:08:25.326809
1654 23:08:25.327162 Set Vref, RX VrefLevel [Byte0]: 37
1655 23:08:25.329802 [Byte1]: 37
1656 23:08:25.334180
1657 23:08:25.334532 Set Vref, RX VrefLevel [Byte0]: 38
1658 23:08:25.337665 [Byte1]: 38
1659 23:08:25.342008
1660 23:08:25.342358 Set Vref, RX VrefLevel [Byte0]: 39
1661 23:08:25.344923 [Byte1]: 39
1662 23:08:25.349645
1663 23:08:25.350001 Set Vref, RX VrefLevel [Byte0]: 40
1664 23:08:25.352624 [Byte1]: 40
1665 23:08:25.356923
1666 23:08:25.357277 Set Vref, RX VrefLevel [Byte0]: 41
1667 23:08:25.360664 [Byte1]: 41
1668 23:08:25.364449
1669 23:08:25.364806 Set Vref, RX VrefLevel [Byte0]: 42
1670 23:08:25.367532 [Byte1]: 42
1671 23:08:25.371838
1672 23:08:25.372194 Set Vref, RX VrefLevel [Byte0]: 43
1673 23:08:25.375158 [Byte1]: 43
1674 23:08:25.378915
1675 23:08:25.379171 Set Vref, RX VrefLevel [Byte0]: 44
1676 23:08:25.382851 [Byte1]: 44
1677 23:08:25.386422
1678 23:08:25.386638 Set Vref, RX VrefLevel [Byte0]: 45
1679 23:08:25.389787 [Byte1]: 45
1680 23:08:25.393987
1681 23:08:25.394186 Set Vref, RX VrefLevel [Byte0]: 46
1682 23:08:25.397349 [Byte1]: 46
1683 23:08:25.401766
1684 23:08:25.401930 Set Vref, RX VrefLevel [Byte0]: 47
1685 23:08:25.404863 [Byte1]: 47
1686 23:08:25.409281
1687 23:08:25.409443 Set Vref, RX VrefLevel [Byte0]: 48
1688 23:08:25.412186 [Byte1]: 48
1689 23:08:25.416550
1690 23:08:25.416711 Set Vref, RX VrefLevel [Byte0]: 49
1691 23:08:25.419908 [Byte1]: 49
1692 23:08:25.424388
1693 23:08:25.424623 Set Vref, RX VrefLevel [Byte0]: 50
1694 23:08:25.427119 [Byte1]: 50
1695 23:08:25.431270
1696 23:08:25.431479 Set Vref, RX VrefLevel [Byte0]: 51
1697 23:08:25.434854 [Byte1]: 51
1698 23:08:25.438921
1699 23:08:25.439101 Set Vref, RX VrefLevel [Byte0]: 52
1700 23:08:25.442307 [Byte1]: 52
1701 23:08:25.446536
1702 23:08:25.446701 Set Vref, RX VrefLevel [Byte0]: 53
1703 23:08:25.449807 [Byte1]: 53
1704 23:08:25.453819
1705 23:08:25.453900 Set Vref, RX VrefLevel [Byte0]: 54
1706 23:08:25.457508 [Byte1]: 54
1707 23:08:25.461464
1708 23:08:25.461544 Set Vref, RX VrefLevel [Byte0]: 55
1709 23:08:25.464521 [Byte1]: 55
1710 23:08:25.468864
1711 23:08:25.468945 Set Vref, RX VrefLevel [Byte0]: 56
1712 23:08:25.472438 [Byte1]: 56
1713 23:08:25.476244
1714 23:08:25.476325 Set Vref, RX VrefLevel [Byte0]: 57
1715 23:08:25.480144 [Byte1]: 57
1716 23:08:25.484144
1717 23:08:25.484225 Set Vref, RX VrefLevel [Byte0]: 58
1718 23:08:25.486888 [Byte1]: 58
1719 23:08:25.491279
1720 23:08:25.491359 Set Vref, RX VrefLevel [Byte0]: 59
1721 23:08:25.494766 [Byte1]: 59
1722 23:08:25.498709
1723 23:08:25.498789 Set Vref, RX VrefLevel [Byte0]: 60
1724 23:08:25.502358 [Byte1]: 60
1725 23:08:25.506848
1726 23:08:25.506929 Set Vref, RX VrefLevel [Byte0]: 61
1727 23:08:25.509423 [Byte1]: 61
1728 23:08:25.514097
1729 23:08:25.514177 Set Vref, RX VrefLevel [Byte0]: 62
1730 23:08:25.516916 [Byte1]: 62
1731 23:08:25.521184
1732 23:08:25.521264 Set Vref, RX VrefLevel [Byte0]: 63
1733 23:08:25.524585 [Byte1]: 63
1734 23:08:25.529344
1735 23:08:25.529424 Set Vref, RX VrefLevel [Byte0]: 64
1736 23:08:25.532077 [Byte1]: 64
1737 23:08:25.536324
1738 23:08:25.536414 Set Vref, RX VrefLevel [Byte0]: 65
1739 23:08:25.539758 [Byte1]: 65
1740 23:08:25.543970
1741 23:08:25.544051 Set Vref, RX VrefLevel [Byte0]: 66
1742 23:08:25.547392 [Byte1]: 66
1743 23:08:25.551304
1744 23:08:25.551384 Set Vref, RX VrefLevel [Byte0]: 67
1745 23:08:25.554519 [Byte1]: 67
1746 23:08:25.558684
1747 23:08:25.558765 Set Vref, RX VrefLevel [Byte0]: 68
1748 23:08:25.562301 [Byte1]: 68
1749 23:08:25.566647
1750 23:08:25.566730 Set Vref, RX VrefLevel [Byte0]: 69
1751 23:08:25.569536 [Byte1]: 69
1752 23:08:25.573913
1753 23:08:25.573993 Set Vref, RX VrefLevel [Byte0]: 70
1754 23:08:25.577435 [Byte1]: 70
1755 23:08:25.581390
1756 23:08:25.581496 Set Vref, RX VrefLevel [Byte0]: 71
1757 23:08:25.585616 [Byte1]: 71
1758 23:08:25.589424
1759 23:08:25.589922 Final RX Vref Byte 0 = 57 to rank0
1760 23:08:25.592366 Final RX Vref Byte 1 = 60 to rank0
1761 23:08:25.595961 Final RX Vref Byte 0 = 57 to rank1
1762 23:08:25.599531 Final RX Vref Byte 1 = 60 to rank1==
1763 23:08:25.602644 Dram Type= 6, Freq= 0, CH_1, rank 0
1764 23:08:25.606212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1765 23:08:25.609187 ==
1766 23:08:25.609642 DQS Delay:
1767 23:08:25.609986 DQS0 = 0, DQS1 = 0
1768 23:08:25.612539 DQM Delay:
1769 23:08:25.612949 DQM0 = 95, DQM1 = 89
1770 23:08:25.616270 DQ Delay:
1771 23:08:25.619423 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =92
1772 23:08:25.622729 DQ4 =92, DQ5 =108, DQ6 =108, DQ7 =92
1773 23:08:25.623148 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84
1774 23:08:25.629231 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1775 23:08:25.629715
1776 23:08:25.630056
1777 23:08:25.636206 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f4c, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
1778 23:08:25.639442 CH1 RK0: MR19=606, MR18=2F4C
1779 23:08:25.646388 CH1_RK0: MR19=0x606, MR18=0x2F4C, DQSOSC=390, MR23=63, INC=97, DEC=64
1780 23:08:25.646810
1781 23:08:25.649696 ----->DramcWriteLeveling(PI) begin...
1782 23:08:25.650121 ==
1783 23:08:25.653030 Dram Type= 6, Freq= 0, CH_1, rank 1
1784 23:08:25.656369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1785 23:08:25.656860 ==
1786 23:08:25.659795 Write leveling (Byte 0): 30 => 30
1787 23:08:25.663072 Write leveling (Byte 1): 30 => 30
1788 23:08:25.666460 DramcWriteLeveling(PI) end<-----
1789 23:08:25.666887
1790 23:08:25.667221 ==
1791 23:08:25.670042 Dram Type= 6, Freq= 0, CH_1, rank 1
1792 23:08:25.672940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1793 23:08:25.673359 ==
1794 23:08:25.676732 [Gating] SW mode calibration
1795 23:08:25.683058 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1796 23:08:25.689894 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1797 23:08:25.693601 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1798 23:08:25.696494 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1799 23:08:25.700334 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1800 23:08:25.706778 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1801 23:08:25.710105 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1802 23:08:25.713297 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1803 23:08:25.720070 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1804 23:08:25.723157 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1805 23:08:25.726513 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 23:08:25.733159 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 23:08:25.736275 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 23:08:25.739848 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 23:08:25.746472 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 23:08:25.749791 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 23:08:25.752992 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 23:08:25.759662 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 23:08:25.763094 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 23:08:25.766275 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1815 23:08:25.772957 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 23:08:25.776730 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 23:08:25.780266 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 23:08:25.787068 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 23:08:25.789778 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 23:08:25.793122 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 23:08:25.796570 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 23:08:25.803125 0 9 4 | B1->B0 | 2c2c 2323 | 1 0 | (1 1) (0 0)
1823 23:08:25.806779 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1824 23:08:25.809876 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1825 23:08:25.817101 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1826 23:08:25.819910 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1827 23:08:25.823488 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1828 23:08:25.830012 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1829 23:08:25.833846 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
1830 23:08:25.837159 0 10 4 | B1->B0 | 2c2c 3333 | 0 0 | (1 0) (0 1)
1831 23:08:25.843383 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1832 23:08:25.846931 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 23:08:25.849947 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 23:08:25.856581 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 23:08:25.860074 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 23:08:25.863289 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 23:08:25.869738 0 11 0 | B1->B0 | 2424 2323 | 1 0 | (0 0) (0 0)
1838 23:08:25.873415 0 11 4 | B1->B0 | 3737 2424 | 1 0 | (0 0) (0 0)
1839 23:08:25.876881 0 11 8 | B1->B0 | 4646 4141 | 0 0 | (0 0) (0 0)
1840 23:08:25.879961 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1841 23:08:25.886749 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1842 23:08:25.889684 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1843 23:08:25.893485 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1844 23:08:25.900134 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1845 23:08:25.903236 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1846 23:08:25.906538 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1847 23:08:25.913393 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1848 23:08:25.916641 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1849 23:08:25.920233 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1850 23:08:25.926918 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1851 23:08:25.930068 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1852 23:08:25.933777 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1853 23:08:25.940053 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 23:08:25.943989 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 23:08:25.946727 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 23:08:25.953930 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 23:08:25.957105 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 23:08:25.960288 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 23:08:25.966526 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 23:08:25.970270 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 23:08:25.973112 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1862 23:08:25.976498 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1863 23:08:25.983295 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1864 23:08:25.986923 Total UI for P1: 0, mck2ui 16
1865 23:08:25.989896 best dqsien dly found for B0: ( 0, 14, 4)
1866 23:08:25.993296 Total UI for P1: 0, mck2ui 16
1867 23:08:25.996816 best dqsien dly found for B1: ( 0, 14, 2)
1868 23:08:26.000075 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1869 23:08:26.003766 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1870 23:08:26.004181
1871 23:08:26.006774 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1872 23:08:26.009860 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1873 23:08:26.012830 [Gating] SW calibration Done
1874 23:08:26.012911 ==
1875 23:08:26.016165 Dram Type= 6, Freq= 0, CH_1, rank 1
1876 23:08:26.019686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1877 23:08:26.019767 ==
1878 23:08:26.022931 RX Vref Scan: 0
1879 23:08:26.023013
1880 23:08:26.023076 RX Vref 0 -> 0, step: 1
1881 23:08:26.026807
1882 23:08:26.026888 RX Delay -130 -> 252, step: 16
1883 23:08:26.032854 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1884 23:08:26.036399 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1885 23:08:26.039417 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1886 23:08:26.042782 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1887 23:08:26.046357 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1888 23:08:26.049427 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1889 23:08:26.056580 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1890 23:08:26.059679 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1891 23:08:26.063263 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1892 23:08:26.066225 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1893 23:08:26.069811 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1894 23:08:26.076473 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1895 23:08:26.079970 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1896 23:08:26.083179 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1897 23:08:26.086549 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1898 23:08:26.089929 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1899 23:08:26.093147 ==
1900 23:08:26.096261 Dram Type= 6, Freq= 0, CH_1, rank 1
1901 23:08:26.100014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1902 23:08:26.100095 ==
1903 23:08:26.100160 DQS Delay:
1904 23:08:26.102974 DQS0 = 0, DQS1 = 0
1905 23:08:26.103054 DQM Delay:
1906 23:08:26.106027 DQM0 = 92, DQM1 = 88
1907 23:08:26.106108 DQ Delay:
1908 23:08:26.109777 DQ0 =93, DQ1 =93, DQ2 =77, DQ3 =85
1909 23:08:26.113124 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1910 23:08:26.116338 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =77
1911 23:08:26.119770 DQ12 =93, DQ13 =101, DQ14 =93, DQ15 =93
1912 23:08:26.119851
1913 23:08:26.119915
1914 23:08:26.119974 ==
1915 23:08:26.123071 Dram Type= 6, Freq= 0, CH_1, rank 1
1916 23:08:26.126738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1917 23:08:26.126819 ==
1918 23:08:26.126884
1919 23:08:26.126944
1920 23:08:26.129552 TX Vref Scan disable
1921 23:08:26.132946 == TX Byte 0 ==
1922 23:08:26.136384 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1923 23:08:26.140012 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1924 23:08:26.142958 == TX Byte 1 ==
1925 23:08:26.146396 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1926 23:08:26.149961 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1927 23:08:26.150043 ==
1928 23:08:26.152981 Dram Type= 6, Freq= 0, CH_1, rank 1
1929 23:08:26.156412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1930 23:08:26.159642 ==
1931 23:08:26.170952 TX Vref=22, minBit 3, minWin=26, winSum=441
1932 23:08:26.174371 TX Vref=24, minBit 2, minWin=27, winSum=450
1933 23:08:26.177276 TX Vref=26, minBit 0, minWin=27, winSum=447
1934 23:08:26.180913 TX Vref=28, minBit 2, minWin=27, winSum=451
1935 23:08:26.184105 TX Vref=30, minBit 0, minWin=27, winSum=449
1936 23:08:26.190508 TX Vref=32, minBit 0, minWin=27, winSum=450
1937 23:08:26.194240 [TxChooseVref] Worse bit 2, Min win 27, Win sum 451, Final Vref 28
1938 23:08:26.194322
1939 23:08:26.197568 Final TX Range 1 Vref 28
1940 23:08:26.197690
1941 23:08:26.197754 ==
1942 23:08:26.200850 Dram Type= 6, Freq= 0, CH_1, rank 1
1943 23:08:26.204043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1944 23:08:26.204124 ==
1945 23:08:26.207733
1946 23:08:26.207813
1947 23:08:26.207876 TX Vref Scan disable
1948 23:08:26.210972 == TX Byte 0 ==
1949 23:08:26.214560 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1950 23:08:26.217593 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1951 23:08:26.221040 == TX Byte 1 ==
1952 23:08:26.223963 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1953 23:08:26.230693 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1954 23:08:26.230773
1955 23:08:26.230837 [DATLAT]
1956 23:08:26.230896 Freq=800, CH1 RK1
1957 23:08:26.230954
1958 23:08:26.234087 DATLAT Default: 0xa
1959 23:08:26.234167 0, 0xFFFF, sum = 0
1960 23:08:26.238113 1, 0xFFFF, sum = 0
1961 23:08:26.238195 2, 0xFFFF, sum = 0
1962 23:08:26.241042 3, 0xFFFF, sum = 0
1963 23:08:26.241123 4, 0xFFFF, sum = 0
1964 23:08:26.244074 5, 0xFFFF, sum = 0
1965 23:08:26.244156 6, 0xFFFF, sum = 0
1966 23:08:26.247434 7, 0xFFFF, sum = 0
1967 23:08:26.250808 8, 0xFFFF, sum = 0
1968 23:08:26.250891 9, 0x0, sum = 1
1969 23:08:26.250957 10, 0x0, sum = 2
1970 23:08:26.254371 11, 0x0, sum = 3
1971 23:08:26.254454 12, 0x0, sum = 4
1972 23:08:26.258281 best_step = 10
1973 23:08:26.258361
1974 23:08:26.258423 ==
1975 23:08:26.261018 Dram Type= 6, Freq= 0, CH_1, rank 1
1976 23:08:26.264685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1977 23:08:26.264767 ==
1978 23:08:26.267973 RX Vref Scan: 0
1979 23:08:26.268056
1980 23:08:26.268119 RX Vref 0 -> 0, step: 1
1981 23:08:26.268179
1982 23:08:26.271213 RX Delay -79 -> 252, step: 8
1983 23:08:26.277710 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
1984 23:08:26.280828 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
1985 23:08:26.284409 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
1986 23:08:26.287440 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
1987 23:08:26.291579 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
1988 23:08:26.295003 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
1989 23:08:26.301280 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
1990 23:08:26.304946 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
1991 23:08:26.308336 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
1992 23:08:26.311715 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
1993 23:08:26.315038 iDelay=209, Bit 10, Center 88 (-15 ~ 192) 208
1994 23:08:26.321851 iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208
1995 23:08:26.324876 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
1996 23:08:26.328463 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
1997 23:08:26.331680 iDelay=209, Bit 14, Center 92 (-7 ~ 192) 200
1998 23:08:26.334985 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
1999 23:08:26.335446 ==
2000 23:08:26.338319 Dram Type= 6, Freq= 0, CH_1, rank 1
2001 23:08:26.344598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2002 23:08:26.345016 ==
2003 23:08:26.345344 DQS Delay:
2004 23:08:26.348006 DQS0 = 0, DQS1 = 0
2005 23:08:26.348538 DQM Delay:
2006 23:08:26.351212 DQM0 = 97, DQM1 = 90
2007 23:08:26.351626 DQ Delay:
2008 23:08:26.354852 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2009 23:08:26.358396 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2010 23:08:26.361222 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =88
2011 23:08:26.364747 DQ12 =100, DQ13 =96, DQ14 =92, DQ15 =96
2012 23:08:26.365162
2013 23:08:26.365489
2014 23:08:26.371538 [DQSOSCAuto] RK1, (LSB)MR18= 0x430b, (MSB)MR19= 0x606, tDQSOscB0 = 407 ps tDQSOscB1 = 393 ps
2015 23:08:26.374497 CH1 RK1: MR19=606, MR18=430B
2016 23:08:26.381235 CH1_RK1: MR19=0x606, MR18=0x430B, DQSOSC=393, MR23=63, INC=95, DEC=63
2017 23:08:26.384577 [RxdqsGatingPostProcess] freq 800
2018 23:08:26.388047 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2019 23:08:26.391292 Pre-setting of DQS Precalculation
2020 23:08:26.397705 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2021 23:08:26.404963 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2022 23:08:26.411389 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2023 23:08:26.411809
2024 23:08:26.412137
2025 23:08:26.414810 [Calibration Summary] 1600 Mbps
2026 23:08:26.415221 CH 0, Rank 0
2027 23:08:26.418302 SW Impedance : PASS
2028 23:08:26.421767 DUTY Scan : NO K
2029 23:08:26.422183 ZQ Calibration : PASS
2030 23:08:26.425027 Jitter Meter : NO K
2031 23:08:26.428012 CBT Training : PASS
2032 23:08:26.428425 Write leveling : PASS
2033 23:08:26.431740 RX DQS gating : PASS
2034 23:08:26.434420 RX DQ/DQS(RDDQC) : PASS
2035 23:08:26.434833 TX DQ/DQS : PASS
2036 23:08:26.437717 RX DATLAT : PASS
2037 23:08:26.441309 RX DQ/DQS(Engine): PASS
2038 23:08:26.441758 TX OE : NO K
2039 23:08:26.444449 All Pass.
2040 23:08:26.444857
2041 23:08:26.445182 CH 0, Rank 1
2042 23:08:26.448001 SW Impedance : PASS
2043 23:08:26.448563 DUTY Scan : NO K
2044 23:08:26.451894 ZQ Calibration : PASS
2045 23:08:26.454485 Jitter Meter : NO K
2046 23:08:26.454902 CBT Training : PASS
2047 23:08:26.458142 Write leveling : PASS
2048 23:08:26.458656 RX DQS gating : PASS
2049 23:08:26.461619 RX DQ/DQS(RDDQC) : PASS
2050 23:08:26.465073 TX DQ/DQS : PASS
2051 23:08:26.465737 RX DATLAT : PASS
2052 23:08:26.468131 RX DQ/DQS(Engine): PASS
2053 23:08:26.472113 TX OE : NO K
2054 23:08:26.472827 All Pass.
2055 23:08:26.473355
2056 23:08:26.473760 CH 1, Rank 0
2057 23:08:26.474691 SW Impedance : PASS
2058 23:08:26.477973 DUTY Scan : NO K
2059 23:08:26.478503 ZQ Calibration : PASS
2060 23:08:26.481479 Jitter Meter : NO K
2061 23:08:26.484997 CBT Training : PASS
2062 23:08:26.485561 Write leveling : PASS
2063 23:08:26.487998 RX DQS gating : PASS
2064 23:08:26.491545 RX DQ/DQS(RDDQC) : PASS
2065 23:08:26.492163 TX DQ/DQS : PASS
2066 23:08:26.494441 RX DATLAT : PASS
2067 23:08:26.498805 RX DQ/DQS(Engine): PASS
2068 23:08:26.499265 TX OE : NO K
2069 23:08:26.499629 All Pass.
2070 23:08:26.501644
2071 23:08:26.502103 CH 1, Rank 1
2072 23:08:26.504662 SW Impedance : PASS
2073 23:08:26.505220 DUTY Scan : NO K
2074 23:08:26.508304 ZQ Calibration : PASS
2075 23:08:26.509008 Jitter Meter : NO K
2076 23:08:26.511687 CBT Training : PASS
2077 23:08:26.514510 Write leveling : PASS
2078 23:08:26.514967 RX DQS gating : PASS
2079 23:08:26.518231 RX DQ/DQS(RDDQC) : PASS
2080 23:08:26.521871 TX DQ/DQS : PASS
2081 23:08:26.522434 RX DATLAT : PASS
2082 23:08:26.524734 RX DQ/DQS(Engine): PASS
2083 23:08:26.528410 TX OE : NO K
2084 23:08:26.528973 All Pass.
2085 23:08:26.529339
2086 23:08:26.531199 DramC Write-DBI off
2087 23:08:26.531653 PER_BANK_REFRESH: Hybrid Mode
2088 23:08:26.534719 TX_TRACKING: ON
2089 23:08:26.538301 [GetDramInforAfterCalByMRR] Vendor 6.
2090 23:08:26.541088 [GetDramInforAfterCalByMRR] Revision 606.
2091 23:08:26.545047 [GetDramInforAfterCalByMRR] Revision 2 0.
2092 23:08:26.545506 MR0 0x3b3b
2093 23:08:26.547697 MR8 0x5151
2094 23:08:26.551142 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2095 23:08:26.551555
2096 23:08:26.551880 MR0 0x3b3b
2097 23:08:26.552207 MR8 0x5151
2098 23:08:26.558170 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2099 23:08:26.558713
2100 23:08:26.564576 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2101 23:08:26.567945 [FAST_K] Save calibration result to emmc
2102 23:08:26.571286 [FAST_K] Save calibration result to emmc
2103 23:08:26.575124 dram_init: config_dvfs: 1
2104 23:08:26.577692 dramc_set_vcore_voltage set vcore to 662500
2105 23:08:26.581296 Read voltage for 1200, 2
2106 23:08:26.581885 Vio18 = 0
2107 23:08:26.584324 Vcore = 662500
2108 23:08:26.584861 Vdram = 0
2109 23:08:26.585377 Vddq = 0
2110 23:08:26.585898 Vmddr = 0
2111 23:08:26.591383 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2112 23:08:26.598215 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2113 23:08:26.598638 MEM_TYPE=3, freq_sel=15
2114 23:08:26.601476 sv_algorithm_assistance_LP4_1600
2115 23:08:26.604729 ============ PULL DRAM RESETB DOWN ============
2116 23:08:26.610989 ========== PULL DRAM RESETB DOWN end =========
2117 23:08:26.614459 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2118 23:08:26.617637 ===================================
2119 23:08:26.620995 LPDDR4 DRAM CONFIGURATION
2120 23:08:26.624291 ===================================
2121 23:08:26.624372 EX_ROW_EN[0] = 0x0
2122 23:08:26.627923 EX_ROW_EN[1] = 0x0
2123 23:08:26.628003 LP4Y_EN = 0x0
2124 23:08:26.631250 WORK_FSP = 0x0
2125 23:08:26.631331 WL = 0x4
2126 23:08:26.634291 RL = 0x4
2127 23:08:26.634372 BL = 0x2
2128 23:08:26.637525 RPST = 0x0
2129 23:08:26.637644 RD_PRE = 0x0
2130 23:08:26.641249 WR_PRE = 0x1
2131 23:08:26.641329 WR_PST = 0x0
2132 23:08:26.644332 DBI_WR = 0x0
2133 23:08:26.647834 DBI_RD = 0x0
2134 23:08:26.647914 OTF = 0x1
2135 23:08:26.650867 ===================================
2136 23:08:26.654300 ===================================
2137 23:08:26.654381 ANA top config
2138 23:08:26.658010 ===================================
2139 23:08:26.660737 DLL_ASYNC_EN = 0
2140 23:08:26.664821 ALL_SLAVE_EN = 0
2141 23:08:26.667572 NEW_RANK_MODE = 1
2142 23:08:26.671322 DLL_IDLE_MODE = 1
2143 23:08:26.671404 LP45_APHY_COMB_EN = 1
2144 23:08:26.674584 TX_ODT_DIS = 1
2145 23:08:26.677556 NEW_8X_MODE = 1
2146 23:08:26.681221 ===================================
2147 23:08:26.684384 ===================================
2148 23:08:26.687611 data_rate = 2400
2149 23:08:26.691090 CKR = 1
2150 23:08:26.691170 DQ_P2S_RATIO = 8
2151 23:08:26.694232 ===================================
2152 23:08:26.697765 CA_P2S_RATIO = 8
2153 23:08:26.700702 DQ_CA_OPEN = 0
2154 23:08:26.704174 DQ_SEMI_OPEN = 0
2155 23:08:26.707556 CA_SEMI_OPEN = 0
2156 23:08:26.710667 CA_FULL_RATE = 0
2157 23:08:26.710748 DQ_CKDIV4_EN = 0
2158 23:08:26.714605 CA_CKDIV4_EN = 0
2159 23:08:26.718004 CA_PREDIV_EN = 0
2160 23:08:26.721088 PH8_DLY = 17
2161 23:08:26.724663 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2162 23:08:26.724770 DQ_AAMCK_DIV = 4
2163 23:08:26.727520 CA_AAMCK_DIV = 4
2164 23:08:26.731054 CA_ADMCK_DIV = 4
2165 23:08:26.734923 DQ_TRACK_CA_EN = 0
2166 23:08:26.738184 CA_PICK = 1200
2167 23:08:26.741199 CA_MCKIO = 1200
2168 23:08:26.744803 MCKIO_SEMI = 0
2169 23:08:26.744875 PLL_FREQ = 2366
2170 23:08:26.747758 DQ_UI_PI_RATIO = 32
2171 23:08:26.751053 CA_UI_PI_RATIO = 0
2172 23:08:26.754678 ===================================
2173 23:08:26.757805 ===================================
2174 23:08:26.761360 memory_type:LPDDR4
2175 23:08:26.761470 GP_NUM : 10
2176 23:08:26.764755 SRAM_EN : 1
2177 23:08:26.768013 MD32_EN : 0
2178 23:08:26.771016 ===================================
2179 23:08:26.771097 [ANA_INIT] >>>>>>>>>>>>>>
2180 23:08:26.774551 <<<<<< [CONFIGURE PHASE]: ANA_TX
2181 23:08:26.778315 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2182 23:08:26.781457 ===================================
2183 23:08:26.785156 data_rate = 2400,PCW = 0X5b00
2184 23:08:26.787928 ===================================
2185 23:08:26.791264 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2186 23:08:26.798067 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2187 23:08:26.801499 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2188 23:08:26.808210 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2189 23:08:26.812210 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2190 23:08:26.815329 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2191 23:08:26.815521 [ANA_INIT] flow start
2192 23:08:26.818110 [ANA_INIT] PLL >>>>>>>>
2193 23:08:26.821789 [ANA_INIT] PLL <<<<<<<<
2194 23:08:26.821982 [ANA_INIT] MIDPI >>>>>>>>
2195 23:08:26.824955 [ANA_INIT] MIDPI <<<<<<<<
2196 23:08:26.828524 [ANA_INIT] DLL >>>>>>>>
2197 23:08:26.828777 [ANA_INIT] DLL <<<<<<<<
2198 23:08:26.831913 [ANA_INIT] flow end
2199 23:08:26.835018 ============ LP4 DIFF to SE enter ============
2200 23:08:26.841832 ============ LP4 DIFF to SE exit ============
2201 23:08:26.842100 [ANA_INIT] <<<<<<<<<<<<<
2202 23:08:26.845716 [Flow] Enable top DCM control >>>>>
2203 23:08:26.848735 [Flow] Enable top DCM control <<<<<
2204 23:08:26.852157 Enable DLL master slave shuffle
2205 23:08:26.858614 ==============================================================
2206 23:08:26.859077 Gating Mode config
2207 23:08:26.865311 ==============================================================
2208 23:08:26.865789 Config description:
2209 23:08:26.875537 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2210 23:08:26.882119 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2211 23:08:26.888654 SELPH_MODE 0: By rank 1: By Phase
2212 23:08:26.891801 ==============================================================
2213 23:08:26.895126 GAT_TRACK_EN = 1
2214 23:08:26.898747 RX_GATING_MODE = 2
2215 23:08:26.902282 RX_GATING_TRACK_MODE = 2
2216 23:08:26.905142 SELPH_MODE = 1
2217 23:08:26.908469 PICG_EARLY_EN = 1
2218 23:08:26.911931 VALID_LAT_VALUE = 1
2219 23:08:26.918669 ==============================================================
2220 23:08:26.921987 Enter into Gating configuration >>>>
2221 23:08:26.925245 Exit from Gating configuration <<<<
2222 23:08:26.925722 Enter into DVFS_PRE_config >>>>>
2223 23:08:26.938338 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2224 23:08:26.941827 Exit from DVFS_PRE_config <<<<<
2225 23:08:26.945148 Enter into PICG configuration >>>>
2226 23:08:26.948436 Exit from PICG configuration <<<<
2227 23:08:26.948543 [RX_INPUT] configuration >>>>>
2228 23:08:26.951984 [RX_INPUT] configuration <<<<<
2229 23:08:26.958525 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2230 23:08:26.961856 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2231 23:08:26.968766 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2232 23:08:26.975084 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2233 23:08:26.981897 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2234 23:08:26.988691 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2235 23:08:26.991851 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2236 23:08:26.995121 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2237 23:08:26.998609 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2238 23:08:27.004837 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2239 23:08:27.008216 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2240 23:08:27.011381 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2241 23:08:27.014825 ===================================
2242 23:08:27.018332 LPDDR4 DRAM CONFIGURATION
2243 23:08:27.021750 ===================================
2244 23:08:27.024945 EX_ROW_EN[0] = 0x0
2245 23:08:27.025061 EX_ROW_EN[1] = 0x0
2246 23:08:27.028115 LP4Y_EN = 0x0
2247 23:08:27.028195 WORK_FSP = 0x0
2248 23:08:27.031926 WL = 0x4
2249 23:08:27.032005 RL = 0x4
2250 23:08:27.035097 BL = 0x2
2251 23:08:27.035177 RPST = 0x0
2252 23:08:27.038479 RD_PRE = 0x0
2253 23:08:27.038559 WR_PRE = 0x1
2254 23:08:27.041564 WR_PST = 0x0
2255 23:08:27.041681 DBI_WR = 0x0
2256 23:08:27.045124 DBI_RD = 0x0
2257 23:08:27.045244 OTF = 0x1
2258 23:08:27.048151 ===================================
2259 23:08:27.055218 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2260 23:08:27.058137 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2261 23:08:27.061795 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2262 23:08:27.064813 ===================================
2263 23:08:27.068460 LPDDR4 DRAM CONFIGURATION
2264 23:08:27.072162 ===================================
2265 23:08:27.072243 EX_ROW_EN[0] = 0x10
2266 23:08:27.074888 EX_ROW_EN[1] = 0x0
2267 23:08:27.078317 LP4Y_EN = 0x0
2268 23:08:27.078397 WORK_FSP = 0x0
2269 23:08:27.081818 WL = 0x4
2270 23:08:27.081897 RL = 0x4
2271 23:08:27.085075 BL = 0x2
2272 23:08:27.085180 RPST = 0x0
2273 23:08:27.088141 RD_PRE = 0x0
2274 23:08:27.088221 WR_PRE = 0x1
2275 23:08:27.091731 WR_PST = 0x0
2276 23:08:27.091811 DBI_WR = 0x0
2277 23:08:27.094811 DBI_RD = 0x0
2278 23:08:27.094891 OTF = 0x1
2279 23:08:27.098201 ===================================
2280 23:08:27.104740 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2281 23:08:27.104820 ==
2282 23:08:27.108488 Dram Type= 6, Freq= 0, CH_0, rank 0
2283 23:08:27.111719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2284 23:08:27.111801 ==
2285 23:08:27.115318 [Duty_Offset_Calibration]
2286 23:08:27.118267 B0:2 B1:1 CA:1
2287 23:08:27.118347
2288 23:08:27.121903 [DutyScan_Calibration_Flow] k_type=0
2289 23:08:27.129891
2290 23:08:27.129974 ==CLK 0==
2291 23:08:27.133500 Final CLK duty delay cell = 0
2292 23:08:27.136483 [0] MAX Duty = 5218%(X100), DQS PI = 24
2293 23:08:27.139813 [0] MIN Duty = 4875%(X100), DQS PI = 0
2294 23:08:27.139898 [0] AVG Duty = 5046%(X100)
2295 23:08:27.143314
2296 23:08:27.146516 CH0 CLK Duty spec in!! Max-Min= 343%
2297 23:08:27.149563 [DutyScan_Calibration_Flow] ====Done====
2298 23:08:27.149674
2299 23:08:27.152757 [DutyScan_Calibration_Flow] k_type=1
2300 23:08:27.168236
2301 23:08:27.168326 ==DQS 0 ==
2302 23:08:27.171358 Final DQS duty delay cell = -4
2303 23:08:27.174905 [-4] MAX Duty = 5124%(X100), DQS PI = 24
2304 23:08:27.178529 [-4] MIN Duty = 4782%(X100), DQS PI = 0
2305 23:08:27.181527 [-4] AVG Duty = 4953%(X100)
2306 23:08:27.181662
2307 23:08:27.181727 ==DQS 1 ==
2308 23:08:27.184917 Final DQS duty delay cell = 0
2309 23:08:27.188666 [0] MAX Duty = 5187%(X100), DQS PI = 62
2310 23:08:27.191933 [0] MIN Duty = 5000%(X100), DQS PI = 34
2311 23:08:27.195258 [0] AVG Duty = 5093%(X100)
2312 23:08:27.195339
2313 23:08:27.198131 CH0 DQS 0 Duty spec in!! Max-Min= 342%
2314 23:08:27.198211
2315 23:08:27.201916 CH0 DQS 1 Duty spec in!! Max-Min= 187%
2316 23:08:27.205002 [DutyScan_Calibration_Flow] ====Done====
2317 23:08:27.205082
2318 23:08:27.208221 [DutyScan_Calibration_Flow] k_type=3
2319 23:08:27.225416
2320 23:08:27.225521 ==DQM 0 ==
2321 23:08:27.228685 Final DQM duty delay cell = 0
2322 23:08:27.231968 [0] MAX Duty = 5156%(X100), DQS PI = 30
2323 23:08:27.235456 [0] MIN Duty = 4906%(X100), DQS PI = 58
2324 23:08:27.238307 [0] AVG Duty = 5031%(X100)
2325 23:08:27.238386
2326 23:08:27.238449 ==DQM 1 ==
2327 23:08:27.241923 Final DQM duty delay cell = 0
2328 23:08:27.244859 [0] MAX Duty = 5093%(X100), DQS PI = 0
2329 23:08:27.248515 [0] MIN Duty = 5031%(X100), DQS PI = 18
2330 23:08:27.251895 [0] AVG Duty = 5062%(X100)
2331 23:08:27.251974
2332 23:08:27.255408 CH0 DQM 0 Duty spec in!! Max-Min= 250%
2333 23:08:27.255488
2334 23:08:27.258294 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2335 23:08:27.261532 [DutyScan_Calibration_Flow] ====Done====
2336 23:08:27.261620
2337 23:08:27.264980 [DutyScan_Calibration_Flow] k_type=2
2338 23:08:27.281449
2339 23:08:27.281566 ==DQ 0 ==
2340 23:08:27.284677 Final DQ duty delay cell = 0
2341 23:08:27.288249 [0] MAX Duty = 5062%(X100), DQS PI = 32
2342 23:08:27.291790 [0] MIN Duty = 4906%(X100), DQS PI = 0
2343 23:08:27.291873 [0] AVG Duty = 4984%(X100)
2344 23:08:27.291937
2345 23:08:27.294908 ==DQ 1 ==
2346 23:08:27.298297 Final DQ duty delay cell = 0
2347 23:08:27.301609 [0] MAX Duty = 5093%(X100), DQS PI = 24
2348 23:08:27.305234 [0] MIN Duty = 4938%(X100), DQS PI = 36
2349 23:08:27.305305 [0] AVG Duty = 5015%(X100)
2350 23:08:27.305365
2351 23:08:27.308156 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2352 23:08:27.308238
2353 23:08:27.311529 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2354 23:08:27.318290 [DutyScan_Calibration_Flow] ====Done====
2355 23:08:27.318371 ==
2356 23:08:27.321744 Dram Type= 6, Freq= 0, CH_1, rank 0
2357 23:08:27.324975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2358 23:08:27.325056 ==
2359 23:08:27.328497 [Duty_Offset_Calibration]
2360 23:08:27.328578 B0:1 B1:0 CA:0
2361 23:08:27.328643
2362 23:08:27.331808 [DutyScan_Calibration_Flow] k_type=0
2363 23:08:27.340438
2364 23:08:27.340518 ==CLK 0==
2365 23:08:27.344231 Final CLK duty delay cell = -4
2366 23:08:27.347129 [-4] MAX Duty = 5000%(X100), DQS PI = 8
2367 23:08:27.350507 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2368 23:08:27.354217 [-4] AVG Duty = 4953%(X100)
2369 23:08:27.354298
2370 23:08:27.357065 CH1 CLK Duty spec in!! Max-Min= 93%
2371 23:08:27.360608 [DutyScan_Calibration_Flow] ====Done====
2372 23:08:27.360689
2373 23:08:27.363717 [DutyScan_Calibration_Flow] k_type=1
2374 23:08:27.380279
2375 23:08:27.380365 ==DQS 0 ==
2376 23:08:27.383460 Final DQS duty delay cell = 0
2377 23:08:27.386830 [0] MAX Duty = 5062%(X100), DQS PI = 56
2378 23:08:27.390146 [0] MIN Duty = 4875%(X100), DQS PI = 32
2379 23:08:27.390227 [0] AVG Duty = 4968%(X100)
2380 23:08:27.394048
2381 23:08:27.394128 ==DQS 1 ==
2382 23:08:27.397162 Final DQS duty delay cell = 0
2383 23:08:27.400297 [0] MAX Duty = 5187%(X100), DQS PI = 52
2384 23:08:27.404037 [0] MIN Duty = 4938%(X100), DQS PI = 42
2385 23:08:27.404118 [0] AVG Duty = 5062%(X100)
2386 23:08:27.404182
2387 23:08:27.410335 CH1 DQS 0 Duty spec in!! Max-Min= 187%
2388 23:08:27.410417
2389 23:08:27.413701 CH1 DQS 1 Duty spec in!! Max-Min= 249%
2390 23:08:27.417429 [DutyScan_Calibration_Flow] ====Done====
2391 23:08:27.417535
2392 23:08:27.420720 [DutyScan_Calibration_Flow] k_type=3
2393 23:08:27.437075
2394 23:08:27.437156 ==DQM 0 ==
2395 23:08:27.439974 Final DQM duty delay cell = 0
2396 23:08:27.443544 [0] MAX Duty = 5156%(X100), DQS PI = 38
2397 23:08:27.447223 [0] MIN Duty = 5031%(X100), DQS PI = 14
2398 23:08:27.447304 [0] AVG Duty = 5093%(X100)
2399 23:08:27.450354
2400 23:08:27.450432 ==DQM 1 ==
2401 23:08:27.453768 Final DQM duty delay cell = 0
2402 23:08:27.456780 [0] MAX Duty = 5062%(X100), DQS PI = 12
2403 23:08:27.460408 [0] MIN Duty = 4875%(X100), DQS PI = 4
2404 23:08:27.460488 [0] AVG Duty = 4968%(X100)
2405 23:08:27.460552
2406 23:08:27.466798 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2407 23:08:27.466879
2408 23:08:27.470203 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2409 23:08:27.473584 [DutyScan_Calibration_Flow] ====Done====
2410 23:08:27.473695
2411 23:08:27.476767 [DutyScan_Calibration_Flow] k_type=2
2412 23:08:27.492696
2413 23:08:27.492860 ==DQ 0 ==
2414 23:08:27.496282 Final DQ duty delay cell = -4
2415 23:08:27.499413 [-4] MAX Duty = 5062%(X100), DQS PI = 22
2416 23:08:27.502738 [-4] MIN Duty = 4938%(X100), DQS PI = 4
2417 23:08:27.506014 [-4] AVG Duty = 5000%(X100)
2418 23:08:27.506124
2419 23:08:27.506217 ==DQ 1 ==
2420 23:08:27.509402 Final DQ duty delay cell = 0
2421 23:08:27.512687 [0] MAX Duty = 5093%(X100), DQS PI = 10
2422 23:08:27.516522 [0] MIN Duty = 4938%(X100), DQS PI = 2
2423 23:08:27.516654 [0] AVG Duty = 5015%(X100)
2424 23:08:27.516759
2425 23:08:27.519423 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2426 23:08:27.523332
2427 23:08:27.526388 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2428 23:08:27.529513 [DutyScan_Calibration_Flow] ====Done====
2429 23:08:27.532792 nWR fixed to 30
2430 23:08:27.532993 [ModeRegInit_LP4] CH0 RK0
2431 23:08:27.536036 [ModeRegInit_LP4] CH0 RK1
2432 23:08:27.539507 [ModeRegInit_LP4] CH1 RK0
2433 23:08:27.539916 [ModeRegInit_LP4] CH1 RK1
2434 23:08:27.543381 match AC timing 7
2435 23:08:27.546681 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2436 23:08:27.549803 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2437 23:08:27.556891 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2438 23:08:27.559936 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2439 23:08:27.566546 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2440 23:08:27.566958 ==
2441 23:08:27.569842 Dram Type= 6, Freq= 0, CH_0, rank 0
2442 23:08:27.573123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2443 23:08:27.573540 ==
2444 23:08:27.580061 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2445 23:08:27.583107 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2446 23:08:27.593750 [CA 0] Center 39 (8~70) winsize 63
2447 23:08:27.597177 [CA 1] Center 39 (8~70) winsize 63
2448 23:08:27.600137 [CA 2] Center 35 (5~66) winsize 62
2449 23:08:27.603133 [CA 3] Center 34 (4~65) winsize 62
2450 23:08:27.606507 [CA 4] Center 33 (3~64) winsize 62
2451 23:08:27.609689 [CA 5] Center 32 (3~62) winsize 60
2452 23:08:27.610271
2453 23:08:27.613717 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2454 23:08:27.614344
2455 23:08:27.616401 [CATrainingPosCal] consider 1 rank data
2456 23:08:27.620235 u2DelayCellTimex100 = 270/100 ps
2457 23:08:27.623398 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2458 23:08:27.627008 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2459 23:08:27.633567 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2460 23:08:27.636526 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2461 23:08:27.639892 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2462 23:08:27.643390 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2463 23:08:27.643974
2464 23:08:27.646859 CA PerBit enable=1, Macro0, CA PI delay=32
2465 23:08:27.647273
2466 23:08:27.649852 [CBTSetCACLKResult] CA Dly = 32
2467 23:08:27.650267 CS Dly: 6 (0~37)
2468 23:08:27.650603 ==
2469 23:08:27.653498 Dram Type= 6, Freq= 0, CH_0, rank 1
2470 23:08:27.660282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2471 23:08:27.660701 ==
2472 23:08:27.663722 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2473 23:08:27.670142 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2474 23:08:27.678770 [CA 0] Center 38 (8~69) winsize 62
2475 23:08:27.682166 [CA 1] Center 38 (8~69) winsize 62
2476 23:08:27.685705 [CA 2] Center 35 (4~66) winsize 63
2477 23:08:27.688643 [CA 3] Center 34 (4~65) winsize 62
2478 23:08:27.692560 [CA 4] Center 33 (3~64) winsize 62
2479 23:08:27.695837 [CA 5] Center 32 (3~62) winsize 60
2480 23:08:27.696266
2481 23:08:27.699002 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2482 23:08:27.699500
2483 23:08:27.702045 [CATrainingPosCal] consider 2 rank data
2484 23:08:27.705699 u2DelayCellTimex100 = 270/100 ps
2485 23:08:27.709180 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2486 23:08:27.712783 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2487 23:08:27.719395 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2488 23:08:27.722723 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2489 23:08:27.725505 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2490 23:08:27.728687 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2491 23:08:27.729105
2492 23:08:27.732714 CA PerBit enable=1, Macro0, CA PI delay=32
2493 23:08:27.733194
2494 23:08:27.735637 [CBTSetCACLKResult] CA Dly = 32
2495 23:08:27.736050 CS Dly: 6 (0~38)
2496 23:08:27.736407
2497 23:08:27.739128 ----->DramcWriteLeveling(PI) begin...
2498 23:08:27.739580 ==
2499 23:08:27.742401 Dram Type= 6, Freq= 0, CH_0, rank 0
2500 23:08:27.749283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2501 23:08:27.749817 ==
2502 23:08:27.752656 Write leveling (Byte 0): 34 => 34
2503 23:08:27.756126 Write leveling (Byte 1): 29 => 29
2504 23:08:27.756541 DramcWriteLeveling(PI) end<-----
2505 23:08:27.756874
2506 23:08:27.759463 ==
2507 23:08:27.762413 Dram Type= 6, Freq= 0, CH_0, rank 0
2508 23:08:27.766724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2509 23:08:27.767218 ==
2510 23:08:27.769309 [Gating] SW mode calibration
2511 23:08:27.776408 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2512 23:08:27.779355 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2513 23:08:27.785643 0 15 0 | B1->B0 | 2323 3333 | 0 0 | (0 0) (1 1)
2514 23:08:27.789243 0 15 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
2515 23:08:27.792874 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2516 23:08:27.799420 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2517 23:08:27.802736 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2518 23:08:27.806302 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2519 23:08:27.812794 0 15 24 | B1->B0 | 3434 3131 | 1 1 | (1 1) (0 0)
2520 23:08:27.816687 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 0)
2521 23:08:27.819239 1 0 0 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
2522 23:08:27.826161 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2523 23:08:27.829801 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2524 23:08:27.833295 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2525 23:08:27.836633 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2526 23:08:27.842964 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2527 23:08:27.846194 1 0 24 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
2528 23:08:27.849783 1 0 28 | B1->B0 | 2d2d 4545 | 0 0 | (0 0) (0 0)
2529 23:08:27.856250 1 1 0 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
2530 23:08:27.859489 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2531 23:08:27.862876 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2532 23:08:27.869619 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2533 23:08:27.872536 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2534 23:08:27.876331 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2535 23:08:27.882795 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2536 23:08:27.886224 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2537 23:08:27.889861 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2538 23:08:27.896207 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2539 23:08:27.899378 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2540 23:08:27.902943 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2541 23:08:27.908942 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2542 23:08:27.912279 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2543 23:08:27.915431 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2544 23:08:27.922808 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 23:08:27.925731 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 23:08:27.929013 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 23:08:27.932749 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 23:08:27.939052 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 23:08:27.942477 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 23:08:27.945563 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 23:08:27.952274 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 23:08:27.956054 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2553 23:08:27.959199 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2554 23:08:27.962248 Total UI for P1: 0, mck2ui 16
2555 23:08:27.965800 best dqsien dly found for B0: ( 1, 3, 28)
2556 23:08:27.972762 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2557 23:08:27.972855 Total UI for P1: 0, mck2ui 16
2558 23:08:27.979573 best dqsien dly found for B1: ( 1, 4, 0)
2559 23:08:27.982610 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2560 23:08:27.986006 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2561 23:08:27.986096
2562 23:08:27.989582 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2563 23:08:27.992362 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2564 23:08:27.995767 [Gating] SW calibration Done
2565 23:08:27.995865 ==
2566 23:08:27.999275 Dram Type= 6, Freq= 0, CH_0, rank 0
2567 23:08:28.002893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2568 23:08:28.002975 ==
2569 23:08:28.005744 RX Vref Scan: 0
2570 23:08:28.005824
2571 23:08:28.005888 RX Vref 0 -> 0, step: 1
2572 23:08:28.005949
2573 23:08:28.009213 RX Delay -40 -> 252, step: 8
2574 23:08:28.012818 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2575 23:08:28.019125 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2576 23:08:28.022800 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2577 23:08:28.025518 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2578 23:08:28.029248 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2579 23:08:28.032937 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2580 23:08:28.036071 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2581 23:08:28.042893 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2582 23:08:28.045735 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2583 23:08:28.049421 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2584 23:08:28.052493 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
2585 23:08:28.056224 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2586 23:08:28.062276 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2587 23:08:28.065997 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2588 23:08:28.069222 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2589 23:08:28.072419 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2590 23:08:28.072501 ==
2591 23:08:28.075878 Dram Type= 6, Freq= 0, CH_0, rank 0
2592 23:08:28.082627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2593 23:08:28.082708 ==
2594 23:08:28.082773 DQS Delay:
2595 23:08:28.082834 DQS0 = 0, DQS1 = 0
2596 23:08:28.085801 DQM Delay:
2597 23:08:28.085880 DQM0 = 121, DQM1 = 114
2598 23:08:28.089471 DQ Delay:
2599 23:08:28.092583 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2600 23:08:28.096366 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2601 23:08:28.099450 DQ8 =99, DQ9 =107, DQ10 =115, DQ11 =107
2602 23:08:28.102526 DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =119
2603 23:08:28.102632
2604 23:08:28.102723
2605 23:08:28.102811 ==
2606 23:08:28.105811 Dram Type= 6, Freq= 0, CH_0, rank 0
2607 23:08:28.109230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2608 23:08:28.109311 ==
2609 23:08:28.112727
2610 23:08:28.112807
2611 23:08:28.112871 TX Vref Scan disable
2612 23:08:28.115674 == TX Byte 0 ==
2613 23:08:28.119193 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2614 23:08:28.122890 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2615 23:08:28.125892 == TX Byte 1 ==
2616 23:08:28.129123 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2617 23:08:28.132480 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2618 23:08:28.132561 ==
2619 23:08:28.136073 Dram Type= 6, Freq= 0, CH_0, rank 0
2620 23:08:28.142791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2621 23:08:28.142872 ==
2622 23:08:28.153521 TX Vref=22, minBit 10, minWin=24, winSum=403
2623 23:08:28.156613 TX Vref=24, minBit 0, minWin=25, winSum=411
2624 23:08:28.159949 TX Vref=26, minBit 13, minWin=25, winSum=417
2625 23:08:28.163412 TX Vref=28, minBit 0, minWin=26, winSum=420
2626 23:08:28.166743 TX Vref=30, minBit 0, minWin=26, winSum=421
2627 23:08:28.173403 TX Vref=32, minBit 13, minWin=25, winSum=419
2628 23:08:28.176581 [TxChooseVref] Worse bit 0, Min win 26, Win sum 421, Final Vref 30
2629 23:08:28.176663
2630 23:08:28.180163 Final TX Range 1 Vref 30
2631 23:08:28.180244
2632 23:08:28.180308 ==
2633 23:08:28.183258 Dram Type= 6, Freq= 0, CH_0, rank 0
2634 23:08:28.186761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2635 23:08:28.186843 ==
2636 23:08:28.189839
2637 23:08:28.189918
2638 23:08:28.189982 TX Vref Scan disable
2639 23:08:28.193210 == TX Byte 0 ==
2640 23:08:28.197045 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2641 23:08:28.203253 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2642 23:08:28.203333 == TX Byte 1 ==
2643 23:08:28.206558 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2644 23:08:28.213406 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2645 23:08:28.213487
2646 23:08:28.213549 [DATLAT]
2647 23:08:28.213655 Freq=1200, CH0 RK0
2648 23:08:28.213715
2649 23:08:28.216593 DATLAT Default: 0xd
2650 23:08:28.216672 0, 0xFFFF, sum = 0
2651 23:08:28.220525 1, 0xFFFF, sum = 0
2652 23:08:28.220606 2, 0xFFFF, sum = 0
2653 23:08:28.223551 3, 0xFFFF, sum = 0
2654 23:08:28.223631 4, 0xFFFF, sum = 0
2655 23:08:28.226592 5, 0xFFFF, sum = 0
2656 23:08:28.229845 6, 0xFFFF, sum = 0
2657 23:08:28.229927 7, 0xFFFF, sum = 0
2658 23:08:28.233558 8, 0xFFFF, sum = 0
2659 23:08:28.233657 9, 0xFFFF, sum = 0
2660 23:08:28.236746 10, 0xFFFF, sum = 0
2661 23:08:28.236860 11, 0xFFFF, sum = 0
2662 23:08:28.240481 12, 0x0, sum = 1
2663 23:08:28.240653 13, 0x0, sum = 2
2664 23:08:28.243454 14, 0x0, sum = 3
2665 23:08:28.243630 15, 0x0, sum = 4
2666 23:08:28.243723 best_step = 13
2667 23:08:28.246946
2668 23:08:28.247124 ==
2669 23:08:28.250573 Dram Type= 6, Freq= 0, CH_0, rank 0
2670 23:08:28.253944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2671 23:08:28.254362 ==
2672 23:08:28.254692 RX Vref Scan: 1
2673 23:08:28.254998
2674 23:08:28.257101 Set Vref Range= 32 -> 127
2675 23:08:28.257517
2676 23:08:28.260034 RX Vref 32 -> 127, step: 1
2677 23:08:28.260448
2678 23:08:28.263912 RX Delay -13 -> 252, step: 4
2679 23:08:28.264326
2680 23:08:28.267034 Set Vref, RX VrefLevel [Byte0]: 32
2681 23:08:28.270243 [Byte1]: 32
2682 23:08:28.270662
2683 23:08:28.273615 Set Vref, RX VrefLevel [Byte0]: 33
2684 23:08:28.276749 [Byte1]: 33
2685 23:08:28.280250
2686 23:08:28.280661 Set Vref, RX VrefLevel [Byte0]: 34
2687 23:08:28.283732 [Byte1]: 34
2688 23:08:28.287929
2689 23:08:28.288340 Set Vref, RX VrefLevel [Byte0]: 35
2690 23:08:28.291543 [Byte1]: 35
2691 23:08:28.296245
2692 23:08:28.296657 Set Vref, RX VrefLevel [Byte0]: 36
2693 23:08:28.299447 [Byte1]: 36
2694 23:08:28.304671
2695 23:08:28.305184 Set Vref, RX VrefLevel [Byte0]: 37
2696 23:08:28.307332 [Byte1]: 37
2697 23:08:28.311909
2698 23:08:28.312317 Set Vref, RX VrefLevel [Byte0]: 38
2699 23:08:28.314946 [Byte1]: 38
2700 23:08:28.319880
2701 23:08:28.320384 Set Vref, RX VrefLevel [Byte0]: 39
2702 23:08:28.322941 [Byte1]: 39
2703 23:08:28.328355
2704 23:08:28.328931 Set Vref, RX VrefLevel [Byte0]: 40
2705 23:08:28.330971 [Byte1]: 40
2706 23:08:28.335196
2707 23:08:28.335649 Set Vref, RX VrefLevel [Byte0]: 41
2708 23:08:28.338800 [Byte1]: 41
2709 23:08:28.343363
2710 23:08:28.343443 Set Vref, RX VrefLevel [Byte0]: 42
2711 23:08:28.345986 [Byte1]: 42
2712 23:08:28.350764
2713 23:08:28.350848 Set Vref, RX VrefLevel [Byte0]: 43
2714 23:08:28.354332 [Byte1]: 43
2715 23:08:28.358551
2716 23:08:28.358630 Set Vref, RX VrefLevel [Byte0]: 44
2717 23:08:28.365419 [Byte1]: 44
2718 23:08:28.365499
2719 23:08:28.368684 Set Vref, RX VrefLevel [Byte0]: 45
2720 23:08:28.371676 [Byte1]: 45
2721 23:08:28.371756
2722 23:08:28.375455 Set Vref, RX VrefLevel [Byte0]: 46
2723 23:08:28.378420 [Byte1]: 46
2724 23:08:28.382280
2725 23:08:28.382359 Set Vref, RX VrefLevel [Byte0]: 47
2726 23:08:28.385462 [Byte1]: 47
2727 23:08:28.390091
2728 23:08:28.390170 Set Vref, RX VrefLevel [Byte0]: 48
2729 23:08:28.393687 [Byte1]: 48
2730 23:08:28.398119
2731 23:08:28.398198 Set Vref, RX VrefLevel [Byte0]: 49
2732 23:08:28.401534 [Byte1]: 49
2733 23:08:28.406321
2734 23:08:28.406400 Set Vref, RX VrefLevel [Byte0]: 50
2735 23:08:28.409470 [Byte1]: 50
2736 23:08:28.414066
2737 23:08:28.414145 Set Vref, RX VrefLevel [Byte0]: 51
2738 23:08:28.417139 [Byte1]: 51
2739 23:08:28.421973
2740 23:08:28.422052 Set Vref, RX VrefLevel [Byte0]: 52
2741 23:08:28.425335 [Byte1]: 52
2742 23:08:28.429820
2743 23:08:28.429899 Set Vref, RX VrefLevel [Byte0]: 53
2744 23:08:28.433286 [Byte1]: 53
2745 23:08:28.437865
2746 23:08:28.437945 Set Vref, RX VrefLevel [Byte0]: 54
2747 23:08:28.440933 [Byte1]: 54
2748 23:08:28.445609
2749 23:08:28.445702 Set Vref, RX VrefLevel [Byte0]: 55
2750 23:08:28.449145 [Byte1]: 55
2751 23:08:28.453543
2752 23:08:28.453660 Set Vref, RX VrefLevel [Byte0]: 56
2753 23:08:28.456556 [Byte1]: 56
2754 23:08:28.461154
2755 23:08:28.461234 Set Vref, RX VrefLevel [Byte0]: 57
2756 23:08:28.464587 [Byte1]: 57
2757 23:08:28.469284
2758 23:08:28.469364 Set Vref, RX VrefLevel [Byte0]: 58
2759 23:08:28.472482 [Byte1]: 58
2760 23:08:28.477210
2761 23:08:28.477293 Set Vref, RX VrefLevel [Byte0]: 59
2762 23:08:28.480539 [Byte1]: 59
2763 23:08:28.485368
2764 23:08:28.485448 Set Vref, RX VrefLevel [Byte0]: 60
2765 23:08:28.488035 [Byte1]: 60
2766 23:08:28.493120
2767 23:08:28.493199 Set Vref, RX VrefLevel [Byte0]: 61
2768 23:08:28.496135 [Byte1]: 61
2769 23:08:28.500823
2770 23:08:28.500902 Set Vref, RX VrefLevel [Byte0]: 62
2771 23:08:28.503836 [Byte1]: 62
2772 23:08:28.508717
2773 23:08:28.508796 Set Vref, RX VrefLevel [Byte0]: 63
2774 23:08:28.512257 [Byte1]: 63
2775 23:08:28.516414
2776 23:08:28.516493 Set Vref, RX VrefLevel [Byte0]: 64
2777 23:08:28.520014 [Byte1]: 64
2778 23:08:28.524828
2779 23:08:28.524908 Set Vref, RX VrefLevel [Byte0]: 65
2780 23:08:28.527809 [Byte1]: 65
2781 23:08:28.532584
2782 23:08:28.532663 Set Vref, RX VrefLevel [Byte0]: 66
2783 23:08:28.535484 [Byte1]: 66
2784 23:08:28.540236
2785 23:08:28.540320 Set Vref, RX VrefLevel [Byte0]: 67
2786 23:08:28.544009 [Byte1]: 67
2787 23:08:28.548006
2788 23:08:28.548085 Set Vref, RX VrefLevel [Byte0]: 68
2789 23:08:28.551580 [Byte1]: 68
2790 23:08:28.556412
2791 23:08:28.556492 Set Vref, RX VrefLevel [Byte0]: 69
2792 23:08:28.559231 [Byte1]: 69
2793 23:08:28.563985
2794 23:08:28.564065 Final RX Vref Byte 0 = 53 to rank0
2795 23:08:28.566877 Final RX Vref Byte 1 = 46 to rank0
2796 23:08:28.570298 Final RX Vref Byte 0 = 53 to rank1
2797 23:08:28.573735 Final RX Vref Byte 1 = 46 to rank1==
2798 23:08:28.577088 Dram Type= 6, Freq= 0, CH_0, rank 0
2799 23:08:28.584063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2800 23:08:28.584143 ==
2801 23:08:28.584207 DQS Delay:
2802 23:08:28.584265 DQS0 = 0, DQS1 = 0
2803 23:08:28.586915 DQM Delay:
2804 23:08:28.586993 DQM0 = 121, DQM1 = 110
2805 23:08:28.590323 DQ Delay:
2806 23:08:28.593813 DQ0 =120, DQ1 =122, DQ2 =118, DQ3 =118
2807 23:08:28.597341 DQ4 =124, DQ5 =112, DQ6 =126, DQ7 =128
2808 23:08:28.600568 DQ8 =96, DQ9 =100, DQ10 =112, DQ11 =102
2809 23:08:28.603685 DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =118
2810 23:08:28.603788
2811 23:08:28.603879
2812 23:08:28.613881 [DQSOSCAuto] RK0, (LSB)MR18= 0x140e, (MSB)MR19= 0x404, tDQSOscB0 = 404 ps tDQSOscB1 = 402 ps
2813 23:08:28.613965 CH0 RK0: MR19=404, MR18=140E
2814 23:08:28.620580 CH0_RK0: MR19=0x404, MR18=0x140E, DQSOSC=402, MR23=63, INC=40, DEC=27
2815 23:08:28.620670
2816 23:08:28.623549 ----->DramcWriteLeveling(PI) begin...
2817 23:08:28.623620 ==
2818 23:08:28.627269 Dram Type= 6, Freq= 0, CH_0, rank 1
2819 23:08:28.630344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2820 23:08:28.633770 ==
2821 23:08:28.633849 Write leveling (Byte 0): 32 => 32
2822 23:08:28.637000 Write leveling (Byte 1): 30 => 30
2823 23:08:28.640483 DramcWriteLeveling(PI) end<-----
2824 23:08:28.640561
2825 23:08:28.640623 ==
2826 23:08:28.643684 Dram Type= 6, Freq= 0, CH_0, rank 1
2827 23:08:28.650519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2828 23:08:28.650624 ==
2829 23:08:28.650689 [Gating] SW mode calibration
2830 23:08:28.660634 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2831 23:08:28.664309 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2832 23:08:28.667330 0 15 0 | B1->B0 | 3434 3232 | 0 0 | (0 0) (0 0)
2833 23:08:28.674036 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2834 23:08:28.677114 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2835 23:08:28.680805 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2836 23:08:28.687691 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2837 23:08:28.690989 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2838 23:08:28.694178 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2839 23:08:28.700539 0 15 28 | B1->B0 | 3232 2e2e | 0 1 | (0 1) (1 0)
2840 23:08:28.704264 1 0 0 | B1->B0 | 2323 2424 | 0 0 | (1 0) (0 0)
2841 23:08:28.707355 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2842 23:08:28.714222 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2843 23:08:28.717330 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2844 23:08:28.720872 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2845 23:08:28.727333 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2846 23:08:28.730572 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2847 23:08:28.733849 1 0 28 | B1->B0 | 3c3c 3c3c | 0 0 | (0 0) (0 0)
2848 23:08:28.740870 1 1 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
2849 23:08:28.743918 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2850 23:08:28.747349 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2851 23:08:28.750764 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2852 23:08:28.757312 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2853 23:08:28.760898 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2854 23:08:28.764416 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2855 23:08:28.770631 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2856 23:08:28.774000 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2857 23:08:28.777756 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2858 23:08:28.783760 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2859 23:08:28.787157 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2860 23:08:28.790553 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2861 23:08:28.797461 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2862 23:08:28.801061 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2863 23:08:28.803723 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2864 23:08:28.810741 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2865 23:08:28.814394 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2866 23:08:28.817129 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 23:08:28.824362 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 23:08:28.827247 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 23:08:28.830412 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 23:08:28.837495 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 23:08:28.840497 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2872 23:08:28.843794 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2873 23:08:28.851198 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2874 23:08:28.851726 Total UI for P1: 0, mck2ui 16
2875 23:08:28.854619 best dqsien dly found for B0: ( 1, 3, 30)
2876 23:08:28.857811 Total UI for P1: 0, mck2ui 16
2877 23:08:28.861259 best dqsien dly found for B1: ( 1, 3, 30)
2878 23:08:28.864184 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2879 23:08:28.868063 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2880 23:08:28.871596
2881 23:08:28.874512 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2882 23:08:28.877876 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2883 23:08:28.881277 [Gating] SW calibration Done
2884 23:08:28.881722 ==
2885 23:08:28.884463 Dram Type= 6, Freq= 0, CH_0, rank 1
2886 23:08:28.888234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2887 23:08:28.888799 ==
2888 23:08:28.889170 RX Vref Scan: 0
2889 23:08:28.889513
2890 23:08:28.891168 RX Vref 0 -> 0, step: 1
2891 23:08:28.891639
2892 23:08:28.894521 RX Delay -40 -> 252, step: 8
2893 23:08:28.897775 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2894 23:08:28.901216 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2895 23:08:28.908104 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2896 23:08:28.911403 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2897 23:08:28.914660 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2898 23:08:28.917918 iDelay=200, Bit 5, Center 119 (48 ~ 191) 144
2899 23:08:28.921452 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
2900 23:08:28.924732 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2901 23:08:28.931171 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2902 23:08:28.934466 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2903 23:08:28.937734 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2904 23:08:28.940964 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2905 23:08:28.944701 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2906 23:08:28.950975 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2907 23:08:28.954563 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2908 23:08:28.957402 iDelay=200, Bit 15, Center 119 (56 ~ 183) 128
2909 23:08:28.957503 ==
2910 23:08:28.961127 Dram Type= 6, Freq= 0, CH_0, rank 1
2911 23:08:28.964232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2912 23:08:28.964352 ==
2913 23:08:28.967693 DQS Delay:
2914 23:08:28.967803 DQS0 = 0, DQS1 = 0
2915 23:08:28.971025 DQM Delay:
2916 23:08:28.971134 DQM0 = 121, DQM1 = 112
2917 23:08:28.974459 DQ Delay:
2918 23:08:28.977731 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2919 23:08:28.980849 DQ4 =127, DQ5 =119, DQ6 =123, DQ7 =127
2920 23:08:28.984258 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2921 23:08:28.987499 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =119
2922 23:08:28.987623
2923 23:08:28.987717
2924 23:08:28.987798 ==
2925 23:08:28.991462 Dram Type= 6, Freq= 0, CH_0, rank 1
2926 23:08:28.994208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2927 23:08:28.994323 ==
2928 23:08:28.994427
2929 23:08:28.994512
2930 23:08:28.997378 TX Vref Scan disable
2931 23:08:29.001185 == TX Byte 0 ==
2932 23:08:29.004211 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2933 23:08:29.007807 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2934 23:08:29.011226 == TX Byte 1 ==
2935 23:08:29.014348 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2936 23:08:29.018100 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2937 23:08:29.018183 ==
2938 23:08:29.021204 Dram Type= 6, Freq= 0, CH_0, rank 1
2939 23:08:29.024226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2940 23:08:29.024310 ==
2941 23:08:29.037456 TX Vref=22, minBit 12, minWin=24, winSum=413
2942 23:08:29.040681 TX Vref=24, minBit 1, minWin=25, winSum=412
2943 23:08:29.044290 TX Vref=26, minBit 3, minWin=25, winSum=418
2944 23:08:29.047967 TX Vref=28, minBit 4, minWin=25, winSum=420
2945 23:08:29.050773 TX Vref=30, minBit 12, minWin=25, winSum=424
2946 23:08:29.058056 TX Vref=32, minBit 10, minWin=25, winSum=420
2947 23:08:29.061235 [TxChooseVref] Worse bit 12, Min win 25, Win sum 424, Final Vref 30
2948 23:08:29.061343
2949 23:08:29.064216 Final TX Range 1 Vref 30
2950 23:08:29.064328
2951 23:08:29.064424 ==
2952 23:08:29.067737 Dram Type= 6, Freq= 0, CH_0, rank 1
2953 23:08:29.071623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2954 23:08:29.071741 ==
2955 23:08:29.074368
2956 23:08:29.074450
2957 23:08:29.074515 TX Vref Scan disable
2958 23:08:29.078218 == TX Byte 0 ==
2959 23:08:29.081711 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2960 23:08:29.084611 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2961 23:08:29.087985 == TX Byte 1 ==
2962 23:08:29.091424 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2963 23:08:29.094796 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2964 23:08:29.094877
2965 23:08:29.098094 [DATLAT]
2966 23:08:29.098173 Freq=1200, CH0 RK1
2967 23:08:29.098238
2968 23:08:29.101549 DATLAT Default: 0xd
2969 23:08:29.101670 0, 0xFFFF, sum = 0
2970 23:08:29.104910 1, 0xFFFF, sum = 0
2971 23:08:29.104992 2, 0xFFFF, sum = 0
2972 23:08:29.107844 3, 0xFFFF, sum = 0
2973 23:08:29.107927 4, 0xFFFF, sum = 0
2974 23:08:29.111323 5, 0xFFFF, sum = 0
2975 23:08:29.111411 6, 0xFFFF, sum = 0
2976 23:08:29.114527 7, 0xFFFF, sum = 0
2977 23:08:29.114622 8, 0xFFFF, sum = 0
2978 23:08:29.118044 9, 0xFFFF, sum = 0
2979 23:08:29.121765 10, 0xFFFF, sum = 0
2980 23:08:29.121932 11, 0xFFFF, sum = 0
2981 23:08:29.125121 12, 0x0, sum = 1
2982 23:08:29.125250 13, 0x0, sum = 2
2983 23:08:29.128429 14, 0x0, sum = 3
2984 23:08:29.128625 15, 0x0, sum = 4
2985 23:08:29.128740 best_step = 13
2986 23:08:29.128839
2987 23:08:29.131233 ==
2988 23:08:29.131363 Dram Type= 6, Freq= 0, CH_0, rank 1
2989 23:08:29.138468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2990 23:08:29.138670 ==
2991 23:08:29.138792 RX Vref Scan: 0
2992 23:08:29.138922
2993 23:08:29.141495 RX Vref 0 -> 0, step: 1
2994 23:08:29.141741
2995 23:08:29.145171 RX Delay -13 -> 252, step: 4
2996 23:08:29.148325 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
2997 23:08:29.151879 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
2998 23:08:29.158472 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
2999 23:08:29.161993 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3000 23:08:29.164943 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3001 23:08:29.168366 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3002 23:08:29.172092 iDelay=195, Bit 6, Center 126 (63 ~ 190) 128
3003 23:08:29.178363 iDelay=195, Bit 7, Center 128 (63 ~ 194) 132
3004 23:08:29.181957 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3005 23:08:29.185514 iDelay=195, Bit 9, Center 96 (31 ~ 162) 132
3006 23:08:29.188697 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3007 23:08:29.192138 iDelay=195, Bit 11, Center 102 (39 ~ 166) 128
3008 23:08:29.198691 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3009 23:08:29.201915 iDelay=195, Bit 13, Center 116 (55 ~ 178) 124
3010 23:08:29.205219 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3011 23:08:29.208295 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3012 23:08:29.208769 ==
3013 23:08:29.212011 Dram Type= 6, Freq= 0, CH_0, rank 1
3014 23:08:29.218351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3015 23:08:29.218772 ==
3016 23:08:29.219102 DQS Delay:
3017 23:08:29.219408 DQS0 = 0, DQS1 = 0
3018 23:08:29.222132 DQM Delay:
3019 23:08:29.222544 DQM0 = 121, DQM1 = 109
3020 23:08:29.225020 DQ Delay:
3021 23:08:29.228846 DQ0 =118, DQ1 =122, DQ2 =118, DQ3 =118
3022 23:08:29.232124 DQ4 =122, DQ5 =116, DQ6 =126, DQ7 =128
3023 23:08:29.235241 DQ8 =100, DQ9 =96, DQ10 =110, DQ11 =102
3024 23:08:29.238382 DQ12 =114, DQ13 =116, DQ14 =122, DQ15 =118
3025 23:08:29.238796
3026 23:08:29.239184
3027 23:08:29.245626 [DQSOSCAuto] RK1, (LSB)MR18= 0xbed, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 405 ps
3028 23:08:29.248909 CH0 RK1: MR19=403, MR18=BED
3029 23:08:29.255538 CH0_RK1: MR19=0x403, MR18=0xBED, DQSOSC=405, MR23=63, INC=39, DEC=26
3030 23:08:29.258332 [RxdqsGatingPostProcess] freq 1200
3031 23:08:29.265336 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3032 23:08:29.265957 best DQS0 dly(2T, 0.5T) = (0, 11)
3033 23:08:29.268480 best DQS1 dly(2T, 0.5T) = (0, 12)
3034 23:08:29.272097 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3035 23:08:29.275264 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3036 23:08:29.278938 best DQS0 dly(2T, 0.5T) = (0, 11)
3037 23:08:29.281992 best DQS1 dly(2T, 0.5T) = (0, 11)
3038 23:08:29.285562 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3039 23:08:29.288466 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3040 23:08:29.292639 Pre-setting of DQS Precalculation
3041 23:08:29.295444 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3042 23:08:29.298636 ==
3043 23:08:29.302286 Dram Type= 6, Freq= 0, CH_1, rank 0
3044 23:08:29.305103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3045 23:08:29.305556 ==
3046 23:08:29.308992 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3047 23:08:29.315247 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3048 23:08:29.324655 [CA 0] Center 37 (7~68) winsize 62
3049 23:08:29.327546 [CA 1] Center 37 (7~68) winsize 62
3050 23:08:29.330952 [CA 2] Center 35 (5~65) winsize 61
3051 23:08:29.334295 [CA 3] Center 34 (4~64) winsize 61
3052 23:08:29.337678 [CA 4] Center 34 (4~64) winsize 61
3053 23:08:29.341225 [CA 5] Center 33 (3~63) winsize 61
3054 23:08:29.341707
3055 23:08:29.344337 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3056 23:08:29.344752
3057 23:08:29.347385 [CATrainingPosCal] consider 1 rank data
3058 23:08:29.351172 u2DelayCellTimex100 = 270/100 ps
3059 23:08:29.354218 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3060 23:08:29.357461 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3061 23:08:29.364341 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3062 23:08:29.367825 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3063 23:08:29.371239 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3064 23:08:29.374153 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3065 23:08:29.374570
3066 23:08:29.377543 CA PerBit enable=1, Macro0, CA PI delay=33
3067 23:08:29.378030
3068 23:08:29.381564 [CBTSetCACLKResult] CA Dly = 33
3069 23:08:29.382034 CS Dly: 7 (0~38)
3070 23:08:29.382375 ==
3071 23:08:29.384391 Dram Type= 6, Freq= 0, CH_1, rank 1
3072 23:08:29.390814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3073 23:08:29.391234 ==
3074 23:08:29.394310 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3075 23:08:29.400759 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3076 23:08:29.409725 [CA 0] Center 37 (7~68) winsize 62
3077 23:08:29.413101 [CA 1] Center 37 (7~68) winsize 62
3078 23:08:29.416167 [CA 2] Center 35 (5~65) winsize 61
3079 23:08:29.419659 [CA 3] Center 34 (4~65) winsize 62
3080 23:08:29.423207 [CA 4] Center 34 (4~65) winsize 62
3081 23:08:29.426011 [CA 5] Center 34 (4~64) winsize 61
3082 23:08:29.426091
3083 23:08:29.429833 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3084 23:08:29.429914
3085 23:08:29.432611 [CATrainingPosCal] consider 2 rank data
3086 23:08:29.436514 u2DelayCellTimex100 = 270/100 ps
3087 23:08:29.439831 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3088 23:08:29.442919 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3089 23:08:29.449517 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3090 23:08:29.453133 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3091 23:08:29.456443 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3092 23:08:29.459485 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3093 23:08:29.459565
3094 23:08:29.462988 CA PerBit enable=1, Macro0, CA PI delay=33
3095 23:08:29.463069
3096 23:08:29.466368 [CBTSetCACLKResult] CA Dly = 33
3097 23:08:29.466449 CS Dly: 8 (0~41)
3098 23:08:29.466514
3099 23:08:29.469480 ----->DramcWriteLeveling(PI) begin...
3100 23:08:29.472823 ==
3101 23:08:29.472903 Dram Type= 6, Freq= 0, CH_1, rank 0
3102 23:08:29.479880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3103 23:08:29.479965 ==
3104 23:08:29.482962 Write leveling (Byte 0): 24 => 24
3105 23:08:29.486355 Write leveling (Byte 1): 26 => 26
3106 23:08:29.489394 DramcWriteLeveling(PI) end<-----
3107 23:08:29.489473
3108 23:08:29.489538 ==
3109 23:08:29.493048 Dram Type= 6, Freq= 0, CH_1, rank 0
3110 23:08:29.496770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3111 23:08:29.496850 ==
3112 23:08:29.499643 [Gating] SW mode calibration
3113 23:08:29.506288 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3114 23:08:29.509801 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3115 23:08:29.516174 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3116 23:08:29.520131 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3117 23:08:29.523098 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3118 23:08:29.529768 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3119 23:08:29.533338 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3120 23:08:29.536083 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3121 23:08:29.543213 0 15 24 | B1->B0 | 3131 2929 | 0 0 | (0 0) (0 0)
3122 23:08:29.546256 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
3123 23:08:29.549424 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3124 23:08:29.556675 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3125 23:08:29.560163 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3126 23:08:29.563342 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3127 23:08:29.569580 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3128 23:08:29.573527 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3129 23:08:29.576759 1 0 24 | B1->B0 | 3030 4141 | 1 0 | (0 0) (0 0)
3130 23:08:29.580086 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3131 23:08:29.586423 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3132 23:08:29.589820 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3133 23:08:29.593155 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3134 23:08:29.600120 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3135 23:08:29.603136 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3136 23:08:29.606467 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3137 23:08:29.613927 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3138 23:08:29.616535 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3139 23:08:29.620251 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3140 23:08:29.626640 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3141 23:08:29.630009 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3142 23:08:29.633473 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3143 23:08:29.640177 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3144 23:08:29.643990 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3145 23:08:29.646870 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3146 23:08:29.653048 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3147 23:08:29.657028 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 23:08:29.660085 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 23:08:29.666934 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 23:08:29.669912 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 23:08:29.672919 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 23:08:29.676732 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 23:08:29.683310 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3154 23:08:29.686669 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3155 23:08:29.689963 Total UI for P1: 0, mck2ui 16
3156 23:08:29.693240 best dqsien dly found for B1: ( 1, 3, 24)
3157 23:08:29.696737 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3158 23:08:29.699836 Total UI for P1: 0, mck2ui 16
3159 23:08:29.703220 best dqsien dly found for B0: ( 1, 3, 26)
3160 23:08:29.706390 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3161 23:08:29.709734 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3162 23:08:29.709816
3163 23:08:29.716667 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3164 23:08:29.719848 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3165 23:08:29.723179 [Gating] SW calibration Done
3166 23:08:29.723260 ==
3167 23:08:29.726362 Dram Type= 6, Freq= 0, CH_1, rank 0
3168 23:08:29.729862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3169 23:08:29.729944 ==
3170 23:08:29.730009 RX Vref Scan: 0
3171 23:08:29.730070
3172 23:08:29.733263 RX Vref 0 -> 0, step: 1
3173 23:08:29.733344
3174 23:08:29.736523 RX Delay -40 -> 252, step: 8
3175 23:08:29.739757 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3176 23:08:29.743187 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3177 23:08:29.749735 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3178 23:08:29.753115 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3179 23:08:29.757003 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3180 23:08:29.760138 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3181 23:08:29.763115 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3182 23:08:29.766833 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3183 23:08:29.774172 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3184 23:08:29.776866 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3185 23:08:29.780505 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3186 23:08:29.783547 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3187 23:08:29.787142 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3188 23:08:29.793625 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3189 23:08:29.797164 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3190 23:08:29.800460 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3191 23:08:29.800661 ==
3192 23:08:29.803896 Dram Type= 6, Freq= 0, CH_1, rank 0
3193 23:08:29.807315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3194 23:08:29.807574 ==
3195 23:08:29.810192 DQS Delay:
3196 23:08:29.810371 DQS0 = 0, DQS1 = 0
3197 23:08:29.813975 DQM Delay:
3198 23:08:29.814263 DQM0 = 119, DQM1 = 116
3199 23:08:29.814440 DQ Delay:
3200 23:08:29.817397 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3201 23:08:29.824244 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =119
3202 23:08:29.827222 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3203 23:08:29.830836 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3204 23:08:29.831223
3205 23:08:29.831526
3206 23:08:29.831809 ==
3207 23:08:29.833720 Dram Type= 6, Freq= 0, CH_1, rank 0
3208 23:08:29.837478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3209 23:08:29.838044 ==
3210 23:08:29.838450
3211 23:08:29.838795
3212 23:08:29.840804 TX Vref Scan disable
3213 23:08:29.844011 == TX Byte 0 ==
3214 23:08:29.847469 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3215 23:08:29.850883 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3216 23:08:29.854253 == TX Byte 1 ==
3217 23:08:29.857970 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3218 23:08:29.861477 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3219 23:08:29.862089 ==
3220 23:08:29.863837 Dram Type= 6, Freq= 0, CH_1, rank 0
3221 23:08:29.867724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3222 23:08:29.868237 ==
3223 23:08:29.880503 TX Vref=22, minBit 11, minWin=24, winSum=406
3224 23:08:29.884299 TX Vref=24, minBit 3, minWin=25, winSum=413
3225 23:08:29.887918 TX Vref=26, minBit 1, minWin=25, winSum=419
3226 23:08:29.890581 TX Vref=28, minBit 1, minWin=26, winSum=425
3227 23:08:29.893653 TX Vref=30, minBit 10, minWin=25, winSum=428
3228 23:08:29.897506 TX Vref=32, minBit 9, minWin=26, winSum=429
3229 23:08:29.904283 [TxChooseVref] Worse bit 9, Min win 26, Win sum 429, Final Vref 32
3230 23:08:29.904831
3231 23:08:29.907564 Final TX Range 1 Vref 32
3232 23:08:29.908026
3233 23:08:29.908385 ==
3234 23:08:29.910679 Dram Type= 6, Freq= 0, CH_1, rank 0
3235 23:08:29.914283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3236 23:08:29.914740 ==
3237 23:08:29.915100
3238 23:08:29.915437
3239 23:08:29.917314 TX Vref Scan disable
3240 23:08:29.921064 == TX Byte 0 ==
3241 23:08:29.924386 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3242 23:08:29.927127 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3243 23:08:29.930983 == TX Byte 1 ==
3244 23:08:29.933981 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3245 23:08:29.937491 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3246 23:08:29.937999
3247 23:08:29.940758 [DATLAT]
3248 23:08:29.941222 Freq=1200, CH1 RK0
3249 23:08:29.941647
3250 23:08:29.944409 DATLAT Default: 0xd
3251 23:08:29.944895 0, 0xFFFF, sum = 0
3252 23:08:29.947549 1, 0xFFFF, sum = 0
3253 23:08:29.947971 2, 0xFFFF, sum = 0
3254 23:08:29.951068 3, 0xFFFF, sum = 0
3255 23:08:29.951491 4, 0xFFFF, sum = 0
3256 23:08:29.954007 5, 0xFFFF, sum = 0
3257 23:08:29.954448 6, 0xFFFF, sum = 0
3258 23:08:29.957055 7, 0xFFFF, sum = 0
3259 23:08:29.957476 8, 0xFFFF, sum = 0
3260 23:08:29.960691 9, 0xFFFF, sum = 0
3261 23:08:29.961121 10, 0xFFFF, sum = 0
3262 23:08:29.963792 11, 0xFFFF, sum = 0
3263 23:08:29.964224 12, 0x0, sum = 1
3264 23:08:29.967371 13, 0x0, sum = 2
3265 23:08:29.967792 14, 0x0, sum = 3
3266 23:08:29.970811 15, 0x0, sum = 4
3267 23:08:29.971300 best_step = 13
3268 23:08:29.971642
3269 23:08:29.971950 ==
3270 23:08:29.973866 Dram Type= 6, Freq= 0, CH_1, rank 0
3271 23:08:29.980508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3272 23:08:29.980941 ==
3273 23:08:29.981274 RX Vref Scan: 1
3274 23:08:29.981652
3275 23:08:29.984128 Set Vref Range= 32 -> 127
3276 23:08:29.984537
3277 23:08:29.987426 RX Vref 32 -> 127, step: 1
3278 23:08:29.987838
3279 23:08:29.990692 RX Delay -5 -> 252, step: 4
3280 23:08:29.991104
3281 23:08:29.991430 Set Vref, RX VrefLevel [Byte0]: 32
3282 23:08:29.994033 [Byte1]: 32
3283 23:08:29.998802
3284 23:08:29.999211 Set Vref, RX VrefLevel [Byte0]: 33
3285 23:08:30.001935 [Byte1]: 33
3286 23:08:30.006486
3287 23:08:30.006895 Set Vref, RX VrefLevel [Byte0]: 34
3288 23:08:30.009971 [Byte1]: 34
3289 23:08:30.014057
3290 23:08:30.014513 Set Vref, RX VrefLevel [Byte0]: 35
3291 23:08:30.017664 [Byte1]: 35
3292 23:08:30.022174
3293 23:08:30.022583 Set Vref, RX VrefLevel [Byte0]: 36
3294 23:08:30.025340 [Byte1]: 36
3295 23:08:30.030262
3296 23:08:30.030668 Set Vref, RX VrefLevel [Byte0]: 37
3297 23:08:30.033809 [Byte1]: 37
3298 23:08:30.037797
3299 23:08:30.038206 Set Vref, RX VrefLevel [Byte0]: 38
3300 23:08:30.040759 [Byte1]: 38
3301 23:08:30.045707
3302 23:08:30.046120 Set Vref, RX VrefLevel [Byte0]: 39
3303 23:08:30.049176 [Byte1]: 39
3304 23:08:30.053190
3305 23:08:30.053408 Set Vref, RX VrefLevel [Byte0]: 40
3306 23:08:30.057013 [Byte1]: 40
3307 23:08:30.060957
3308 23:08:30.061195 Set Vref, RX VrefLevel [Byte0]: 41
3309 23:08:30.064637 [Byte1]: 41
3310 23:08:30.069294
3311 23:08:30.069513 Set Vref, RX VrefLevel [Byte0]: 42
3312 23:08:30.072128 [Byte1]: 42
3313 23:08:30.076854
3314 23:08:30.077071 Set Vref, RX VrefLevel [Byte0]: 43
3315 23:08:30.080497 [Byte1]: 43
3316 23:08:30.084462
3317 23:08:30.084679 Set Vref, RX VrefLevel [Byte0]: 44
3318 23:08:30.087983 [Byte1]: 44
3319 23:08:30.092877
3320 23:08:30.093219 Set Vref, RX VrefLevel [Byte0]: 45
3321 23:08:30.095885 [Byte1]: 45
3322 23:08:30.100738
3323 23:08:30.101145 Set Vref, RX VrefLevel [Byte0]: 46
3324 23:08:30.103790 [Byte1]: 46
3325 23:08:30.108779
3326 23:08:30.109182 Set Vref, RX VrefLevel [Byte0]: 47
3327 23:08:30.111568 [Byte1]: 47
3328 23:08:30.116094
3329 23:08:30.116500 Set Vref, RX VrefLevel [Byte0]: 48
3330 23:08:30.119818 [Byte1]: 48
3331 23:08:30.123902
3332 23:08:30.124327 Set Vref, RX VrefLevel [Byte0]: 49
3333 23:08:30.127263 [Byte1]: 49
3334 23:08:30.131756
3335 23:08:30.132164 Set Vref, RX VrefLevel [Byte0]: 50
3336 23:08:30.135175 [Byte1]: 50
3337 23:08:30.140355
3338 23:08:30.140761 Set Vref, RX VrefLevel [Byte0]: 51
3339 23:08:30.143176 [Byte1]: 51
3340 23:08:30.148054
3341 23:08:30.148508 Set Vref, RX VrefLevel [Byte0]: 52
3342 23:08:30.151146 [Byte1]: 52
3343 23:08:30.155380
3344 23:08:30.155786 Set Vref, RX VrefLevel [Byte0]: 53
3345 23:08:30.159002 [Byte1]: 53
3346 23:08:30.162993
3347 23:08:30.163072 Set Vref, RX VrefLevel [Byte0]: 54
3348 23:08:30.166416 [Byte1]: 54
3349 23:08:30.171403
3350 23:08:30.171488 Set Vref, RX VrefLevel [Byte0]: 55
3351 23:08:30.174550 [Byte1]: 55
3352 23:08:30.179179
3353 23:08:30.179334 Set Vref, RX VrefLevel [Byte0]: 56
3354 23:08:30.182520 [Byte1]: 56
3355 23:08:30.186594
3356 23:08:30.186701 Set Vref, RX VrefLevel [Byte0]: 57
3357 23:08:30.189785 [Byte1]: 57
3358 23:08:30.195079
3359 23:08:30.195275 Set Vref, RX VrefLevel [Byte0]: 58
3360 23:08:30.197973 [Byte1]: 58
3361 23:08:30.202292
3362 23:08:30.202554 Set Vref, RX VrefLevel [Byte0]: 59
3363 23:08:30.205758 [Byte1]: 59
3364 23:08:30.210217
3365 23:08:30.210297 Set Vref, RX VrefLevel [Byte0]: 60
3366 23:08:30.213526 [Byte1]: 60
3367 23:08:30.217910
3368 23:08:30.217989 Set Vref, RX VrefLevel [Byte0]: 61
3369 23:08:30.221944 [Byte1]: 61
3370 23:08:30.226305
3371 23:08:30.226810 Set Vref, RX VrefLevel [Byte0]: 62
3372 23:08:30.229475 [Byte1]: 62
3373 23:08:30.234168
3374 23:08:30.234572 Set Vref, RX VrefLevel [Byte0]: 63
3375 23:08:30.237924 [Byte1]: 63
3376 23:08:30.241882
3377 23:08:30.242290 Set Vref, RX VrefLevel [Byte0]: 64
3378 23:08:30.245316 [Byte1]: 64
3379 23:08:30.249860
3380 23:08:30.250403 Set Vref, RX VrefLevel [Byte0]: 65
3381 23:08:30.253190 [Byte1]: 65
3382 23:08:30.258061
3383 23:08:30.258617 Set Vref, RX VrefLevel [Byte0]: 66
3384 23:08:30.261185 [Byte1]: 66
3385 23:08:30.265996
3386 23:08:30.266447 Set Vref, RX VrefLevel [Byte0]: 67
3387 23:08:30.268664 [Byte1]: 67
3388 23:08:30.273217
3389 23:08:30.273718 Set Vref, RX VrefLevel [Byte0]: 68
3390 23:08:30.276734 [Byte1]: 68
3391 23:08:30.280972
3392 23:08:30.281427 Final RX Vref Byte 0 = 54 to rank0
3393 23:08:30.284930 Final RX Vref Byte 1 = 52 to rank0
3394 23:08:30.288211 Final RX Vref Byte 0 = 54 to rank1
3395 23:08:30.291253 Final RX Vref Byte 1 = 52 to rank1==
3396 23:08:30.294940 Dram Type= 6, Freq= 0, CH_1, rank 0
3397 23:08:30.301700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3398 23:08:30.302165 ==
3399 23:08:30.302536 DQS Delay:
3400 23:08:30.302942 DQS0 = 0, DQS1 = 0
3401 23:08:30.304387 DQM Delay:
3402 23:08:30.304840 DQM0 = 120, DQM1 = 117
3403 23:08:30.308160 DQ Delay:
3404 23:08:30.311302 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =116
3405 23:08:30.314515 DQ4 =120, DQ5 =128, DQ6 =128, DQ7 =120
3406 23:08:30.317805 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =112
3407 23:08:30.321706 DQ12 =124, DQ13 =124, DQ14 =124, DQ15 =126
3408 23:08:30.322242
3409 23:08:30.322580
3410 23:08:30.328287 [DQSOSCAuto] RK0, (LSB)MR18= 0x115, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 409 ps
3411 23:08:30.332227 CH1 RK0: MR19=404, MR18=115
3412 23:08:30.338047 CH1_RK0: MR19=0x404, MR18=0x115, DQSOSC=401, MR23=63, INC=40, DEC=27
3413 23:08:30.338603
3414 23:08:30.341682 ----->DramcWriteLeveling(PI) begin...
3415 23:08:30.342149 ==
3416 23:08:30.344933 Dram Type= 6, Freq= 0, CH_1, rank 1
3417 23:08:30.348522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3418 23:08:30.349084 ==
3419 23:08:30.351418 Write leveling (Byte 0): 25 => 25
3420 23:08:30.354911 Write leveling (Byte 1): 28 => 28
3421 23:08:30.357879 DramcWriteLeveling(PI) end<-----
3422 23:08:30.358339
3423 23:08:30.358701 ==
3424 23:08:30.361898 Dram Type= 6, Freq= 0, CH_1, rank 1
3425 23:08:30.368462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3426 23:08:30.369013 ==
3427 23:08:30.369409 [Gating] SW mode calibration
3428 23:08:30.378227 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3429 23:08:30.381886 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3430 23:08:30.384324 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3431 23:08:30.391040 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3432 23:08:30.395000 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3433 23:08:30.397901 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3434 23:08:30.404681 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3435 23:08:30.407986 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3436 23:08:30.411833 0 15 24 | B1->B0 | 2c2c 3333 | 0 0 | (1 1) (0 0)
3437 23:08:30.418076 0 15 28 | B1->B0 | 2323 2323 | 0 1 | (1 0) (1 0)
3438 23:08:30.421507 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3439 23:08:30.424453 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3440 23:08:30.431406 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3441 23:08:30.434604 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3442 23:08:30.438258 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3443 23:08:30.444737 1 0 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3444 23:08:30.447892 1 0 24 | B1->B0 | 3f3f 3131 | 0 1 | (0 0) (0 0)
3445 23:08:30.451066 1 0 28 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
3446 23:08:30.457968 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3447 23:08:30.461418 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3448 23:08:30.464857 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3449 23:08:30.468041 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3450 23:08:30.474619 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3451 23:08:30.478160 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3452 23:08:30.481544 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3453 23:08:30.487919 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3454 23:08:30.491241 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3455 23:08:30.494574 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3456 23:08:30.500981 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3457 23:08:30.504604 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3458 23:08:30.508016 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3459 23:08:30.514568 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3460 23:08:30.517743 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3461 23:08:30.521163 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3462 23:08:30.527911 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3463 23:08:30.530669 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3464 23:08:30.534241 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3465 23:08:30.540984 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3466 23:08:30.544158 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 23:08:30.547340 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3468 23:08:30.553944 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3469 23:08:30.557280 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3470 23:08:30.560903 Total UI for P1: 0, mck2ui 16
3471 23:08:30.564088 best dqsien dly found for B1: ( 1, 3, 22)
3472 23:08:30.567565 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3473 23:08:30.570831 Total UI for P1: 0, mck2ui 16
3474 23:08:30.574115 best dqsien dly found for B0: ( 1, 3, 28)
3475 23:08:30.577251 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3476 23:08:30.580874 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3477 23:08:30.581285
3478 23:08:30.587348 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3479 23:08:30.590291 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3480 23:08:30.590701 [Gating] SW calibration Done
3481 23:08:30.593757 ==
3482 23:08:30.597075 Dram Type= 6, Freq= 0, CH_1, rank 1
3483 23:08:30.600355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3484 23:08:30.600769 ==
3485 23:08:30.601170 RX Vref Scan: 0
3486 23:08:30.601487
3487 23:08:30.603911 RX Vref 0 -> 0, step: 1
3488 23:08:30.604268
3489 23:08:30.606924 RX Delay -40 -> 252, step: 8
3490 23:08:30.610186 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3491 23:08:30.613695 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3492 23:08:30.620270 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3493 23:08:30.623462 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3494 23:08:30.626790 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3495 23:08:30.630149 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3496 23:08:30.633342 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3497 23:08:30.639400 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3498 23:08:30.642742 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3499 23:08:30.646419 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3500 23:08:30.649512 iDelay=200, Bit 10, Center 119 (48 ~ 191) 144
3501 23:08:30.653300 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3502 23:08:30.659868 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3503 23:08:30.663245 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3504 23:08:30.666426 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3505 23:08:30.670093 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3506 23:08:30.670504 ==
3507 23:08:30.673290 Dram Type= 6, Freq= 0, CH_1, rank 1
3508 23:08:30.680201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3509 23:08:30.680701 ==
3510 23:08:30.681035 DQS Delay:
3511 23:08:30.681343 DQS0 = 0, DQS1 = 0
3512 23:08:30.682906 DQM Delay:
3513 23:08:30.683316 DQM0 = 120, DQM1 = 118
3514 23:08:30.686933 DQ Delay:
3515 23:08:30.689662 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3516 23:08:30.693073 DQ4 =119, DQ5 =131, DQ6 =131, DQ7 =119
3517 23:08:30.696946 DQ8 =103, DQ9 =107, DQ10 =119, DQ11 =115
3518 23:08:30.699694 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3519 23:08:30.700222
3520 23:08:30.700569
3521 23:08:30.700878 ==
3522 23:08:30.703305 Dram Type= 6, Freq= 0, CH_1, rank 1
3523 23:08:30.706294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3524 23:08:30.709917 ==
3525 23:08:30.710350
3526 23:08:30.710730
3527 23:08:30.711166 TX Vref Scan disable
3528 23:08:30.712881 == TX Byte 0 ==
3529 23:08:30.716255 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3530 23:08:30.719763 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3531 23:08:30.723246 == TX Byte 1 ==
3532 23:08:30.726114 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3533 23:08:30.729652 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3534 23:08:30.730081 ==
3535 23:08:30.732890 Dram Type= 6, Freq= 0, CH_1, rank 1
3536 23:08:30.739853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3537 23:08:30.740268 ==
3538 23:08:30.750371 TX Vref=22, minBit 9, minWin=25, winSum=416
3539 23:08:30.753534 TX Vref=24, minBit 9, minWin=25, winSum=424
3540 23:08:30.756854 TX Vref=26, minBit 10, minWin=25, winSum=423
3541 23:08:30.760649 TX Vref=28, minBit 2, minWin=26, winSum=432
3542 23:08:30.763362 TX Vref=30, minBit 1, minWin=26, winSum=429
3543 23:08:30.770409 TX Vref=32, minBit 9, minWin=26, winSum=433
3544 23:08:30.773704 [TxChooseVref] Worse bit 9, Min win 26, Win sum 433, Final Vref 32
3545 23:08:30.774131
3546 23:08:30.776628 Final TX Range 1 Vref 32
3547 23:08:30.777051
3548 23:08:30.777484 ==
3549 23:08:30.780315 Dram Type= 6, Freq= 0, CH_1, rank 1
3550 23:08:30.783869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3551 23:08:30.784302 ==
3552 23:08:30.787034
3553 23:08:30.787450
3554 23:08:30.787782 TX Vref Scan disable
3555 23:08:30.790458 == TX Byte 0 ==
3556 23:08:30.793410 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3557 23:08:30.800455 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3558 23:08:30.800978 == TX Byte 1 ==
3559 23:08:30.803818 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3560 23:08:30.810246 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3561 23:08:30.810805
3562 23:08:30.811192 [DATLAT]
3563 23:08:30.811662 Freq=1200, CH1 RK1
3564 23:08:30.812117
3565 23:08:30.813642 DATLAT Default: 0xd
3566 23:08:30.814117 0, 0xFFFF, sum = 0
3567 23:08:30.816799 1, 0xFFFF, sum = 0
3568 23:08:30.820352 2, 0xFFFF, sum = 0
3569 23:08:30.820937 3, 0xFFFF, sum = 0
3570 23:08:30.824062 4, 0xFFFF, sum = 0
3571 23:08:30.824655 5, 0xFFFF, sum = 0
3572 23:08:30.827012 6, 0xFFFF, sum = 0
3573 23:08:30.827674 7, 0xFFFF, sum = 0
3574 23:08:30.830315 8, 0xFFFF, sum = 0
3575 23:08:30.830895 9, 0xFFFF, sum = 0
3576 23:08:30.833885 10, 0xFFFF, sum = 0
3577 23:08:30.834465 11, 0xFFFF, sum = 0
3578 23:08:30.836832 12, 0x0, sum = 1
3579 23:08:30.837407 13, 0x0, sum = 2
3580 23:08:30.840306 14, 0x0, sum = 3
3581 23:08:30.840851 15, 0x0, sum = 4
3582 23:08:30.843619 best_step = 13
3583 23:08:30.844169
3584 23:08:30.844654 ==
3585 23:08:30.846446 Dram Type= 6, Freq= 0, CH_1, rank 1
3586 23:08:30.850358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3587 23:08:30.850949 ==
3588 23:08:30.851322 RX Vref Scan: 0
3589 23:08:30.852984
3590 23:08:30.853430 RX Vref 0 -> 0, step: 1
3591 23:08:30.853894
3592 23:08:30.856451 RX Delay -5 -> 252, step: 4
3593 23:08:30.860186 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3594 23:08:30.866626 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3595 23:08:30.869619 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3596 23:08:30.873380 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3597 23:08:30.876430 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3598 23:08:30.879677 iDelay=195, Bit 5, Center 132 (71 ~ 194) 124
3599 23:08:30.886037 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3600 23:08:30.889833 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3601 23:08:30.893126 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3602 23:08:30.896278 iDelay=195, Bit 9, Center 108 (47 ~ 170) 124
3603 23:08:30.899617 iDelay=195, Bit 10, Center 120 (59 ~ 182) 124
3604 23:08:30.906246 iDelay=195, Bit 11, Center 112 (51 ~ 174) 124
3605 23:08:30.909861 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3606 23:08:30.913026 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3607 23:08:30.916878 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3608 23:08:30.919922 iDelay=195, Bit 15, Center 128 (67 ~ 190) 124
3609 23:08:30.923402 ==
3610 23:08:30.927056 Dram Type= 6, Freq= 0, CH_1, rank 1
3611 23:08:30.929922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3612 23:08:30.930479 ==
3613 23:08:30.930844 DQS Delay:
3614 23:08:30.933282 DQS0 = 0, DQS1 = 0
3615 23:08:30.933888 DQM Delay:
3616 23:08:30.936982 DQM0 = 120, DQM1 = 118
3617 23:08:30.937539 DQ Delay:
3618 23:08:30.939476 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =118
3619 23:08:30.942988 DQ4 =116, DQ5 =132, DQ6 =130, DQ7 =120
3620 23:08:30.946519 DQ8 =106, DQ9 =108, DQ10 =120, DQ11 =112
3621 23:08:30.949660 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =128
3622 23:08:30.950110
3623 23:08:30.950473
3624 23:08:30.959683 [DQSOSCAuto] RK1, (LSB)MR18= 0xfec, (MSB)MR19= 0x403, tDQSOscB0 = 418 ps tDQSOscB1 = 404 ps
3625 23:08:30.960202 CH1 RK1: MR19=403, MR18=FEC
3626 23:08:30.966392 CH1_RK1: MR19=0x403, MR18=0xFEC, DQSOSC=404, MR23=63, INC=40, DEC=26
3627 23:08:30.969663 [RxdqsGatingPostProcess] freq 1200
3628 23:08:30.976883 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3629 23:08:30.979954 best DQS0 dly(2T, 0.5T) = (0, 11)
3630 23:08:30.982866 best DQS1 dly(2T, 0.5T) = (0, 11)
3631 23:08:30.986333 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3632 23:08:30.990114 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3633 23:08:30.993077 best DQS0 dly(2T, 0.5T) = (0, 11)
3634 23:08:30.996580 best DQS1 dly(2T, 0.5T) = (0, 11)
3635 23:08:30.997159 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3636 23:08:30.999507 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3637 23:08:31.002667 Pre-setting of DQS Precalculation
3638 23:08:31.009657 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3639 23:08:31.016630 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3640 23:08:31.023159 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3641 23:08:31.023717
3642 23:08:31.024081
3643 23:08:31.026500 [Calibration Summary] 2400 Mbps
3644 23:08:31.029653 CH 0, Rank 0
3645 23:08:31.030221 SW Impedance : PASS
3646 23:08:31.032954 DUTY Scan : NO K
3647 23:08:31.036148 ZQ Calibration : PASS
3648 23:08:31.036604 Jitter Meter : NO K
3649 23:08:31.039566 CBT Training : PASS
3650 23:08:31.040110 Write leveling : PASS
3651 23:08:31.043126 RX DQS gating : PASS
3652 23:08:31.046583 RX DQ/DQS(RDDQC) : PASS
3653 23:08:31.047145 TX DQ/DQS : PASS
3654 23:08:31.049420 RX DATLAT : PASS
3655 23:08:31.052925 RX DQ/DQS(Engine): PASS
3656 23:08:31.053381 TX OE : NO K
3657 23:08:31.055912 All Pass.
3658 23:08:31.056367
3659 23:08:31.056696 CH 0, Rank 1
3660 23:08:31.059635 SW Impedance : PASS
3661 23:08:31.060116 DUTY Scan : NO K
3662 23:08:31.062637 ZQ Calibration : PASS
3663 23:08:31.066080 Jitter Meter : NO K
3664 23:08:31.066493 CBT Training : PASS
3665 23:08:31.069642 Write leveling : PASS
3666 23:08:31.072457 RX DQS gating : PASS
3667 23:08:31.072869 RX DQ/DQS(RDDQC) : PASS
3668 23:08:31.076067 TX DQ/DQS : PASS
3669 23:08:31.079451 RX DATLAT : PASS
3670 23:08:31.079862 RX DQ/DQS(Engine): PASS
3671 23:08:31.082993 TX OE : NO K
3672 23:08:31.083500 All Pass.
3673 23:08:31.083988
3674 23:08:31.084309 CH 1, Rank 0
3675 23:08:31.085956 SW Impedance : PASS
3676 23:08:31.089452 DUTY Scan : NO K
3677 23:08:31.089917 ZQ Calibration : PASS
3678 23:08:31.092672 Jitter Meter : NO K
3679 23:08:31.095886 CBT Training : PASS
3680 23:08:31.096296 Write leveling : PASS
3681 23:08:31.099805 RX DQS gating : PASS
3682 23:08:31.102343 RX DQ/DQS(RDDQC) : PASS
3683 23:08:31.102758 TX DQ/DQS : PASS
3684 23:08:31.105954 RX DATLAT : PASS
3685 23:08:31.109754 RX DQ/DQS(Engine): PASS
3686 23:08:31.110271 TX OE : NO K
3687 23:08:31.112411 All Pass.
3688 23:08:31.112821
3689 23:08:31.113147 CH 1, Rank 1
3690 23:08:31.116253 SW Impedance : PASS
3691 23:08:31.116767 DUTY Scan : NO K
3692 23:08:31.119499 ZQ Calibration : PASS
3693 23:08:31.122668 Jitter Meter : NO K
3694 23:08:31.123202 CBT Training : PASS
3695 23:08:31.126015 Write leveling : PASS
3696 23:08:31.129147 RX DQS gating : PASS
3697 23:08:31.129763 RX DQ/DQS(RDDQC) : PASS
3698 23:08:31.132921 TX DQ/DQS : PASS
3699 23:08:31.135431 RX DATLAT : PASS
3700 23:08:31.135846 RX DQ/DQS(Engine): PASS
3701 23:08:31.139138 TX OE : NO K
3702 23:08:31.139574 All Pass.
3703 23:08:31.139903
3704 23:08:31.142553 DramC Write-DBI off
3705 23:08:31.145894 PER_BANK_REFRESH: Hybrid Mode
3706 23:08:31.146307 TX_TRACKING: ON
3707 23:08:31.155975 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3708 23:08:31.159513 [FAST_K] Save calibration result to emmc
3709 23:08:31.162325 dramc_set_vcore_voltage set vcore to 650000
3710 23:08:31.166136 Read voltage for 600, 5
3711 23:08:31.166650 Vio18 = 0
3712 23:08:31.166984 Vcore = 650000
3713 23:08:31.168717 Vdram = 0
3714 23:08:31.169147 Vddq = 0
3715 23:08:31.169479 Vmddr = 0
3716 23:08:31.175153 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3717 23:08:31.178826 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3718 23:08:31.182170 MEM_TYPE=3, freq_sel=19
3719 23:08:31.185614 sv_algorithm_assistance_LP4_1600
3720 23:08:31.188844 ============ PULL DRAM RESETB DOWN ============
3721 23:08:31.192277 ========== PULL DRAM RESETB DOWN end =========
3722 23:08:31.199066 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3723 23:08:31.201771 ===================================
3724 23:08:31.202227 LPDDR4 DRAM CONFIGURATION
3725 23:08:31.205391 ===================================
3726 23:08:31.208336 EX_ROW_EN[0] = 0x0
3727 23:08:31.212362 EX_ROW_EN[1] = 0x0
3728 23:08:31.212873 LP4Y_EN = 0x0
3729 23:08:31.215959 WORK_FSP = 0x0
3730 23:08:31.216489 WL = 0x2
3731 23:08:31.218522 RL = 0x2
3732 23:08:31.218937 BL = 0x2
3733 23:08:31.222337 RPST = 0x0
3734 23:08:31.222853 RD_PRE = 0x0
3735 23:08:31.225500 WR_PRE = 0x1
3736 23:08:31.225953 WR_PST = 0x0
3737 23:08:31.228788 DBI_WR = 0x0
3738 23:08:31.229307 DBI_RD = 0x0
3739 23:08:31.232591 OTF = 0x1
3740 23:08:31.235511 ===================================
3741 23:08:31.238707 ===================================
3742 23:08:31.239228 ANA top config
3743 23:08:31.241923 ===================================
3744 23:08:31.245045 DLL_ASYNC_EN = 0
3745 23:08:31.248728 ALL_SLAVE_EN = 1
3746 23:08:31.249245 NEW_RANK_MODE = 1
3747 23:08:31.251760 DLL_IDLE_MODE = 1
3748 23:08:31.255484 LP45_APHY_COMB_EN = 1
3749 23:08:31.259108 TX_ODT_DIS = 1
3750 23:08:31.262163 NEW_8X_MODE = 1
3751 23:08:31.265200 ===================================
3752 23:08:31.268544 ===================================
3753 23:08:31.269072 data_rate = 1200
3754 23:08:31.271760 CKR = 1
3755 23:08:31.274984 DQ_P2S_RATIO = 8
3756 23:08:31.278789 ===================================
3757 23:08:31.281738 CA_P2S_RATIO = 8
3758 23:08:31.285387 DQ_CA_OPEN = 0
3759 23:08:31.288695 DQ_SEMI_OPEN = 0
3760 23:08:31.289187 CA_SEMI_OPEN = 0
3761 23:08:31.292154 CA_FULL_RATE = 0
3762 23:08:31.294822 DQ_CKDIV4_EN = 1
3763 23:08:31.298425 CA_CKDIV4_EN = 1
3764 23:08:31.301999 CA_PREDIV_EN = 0
3765 23:08:31.304891 PH8_DLY = 0
3766 23:08:31.305334 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3767 23:08:31.308335 DQ_AAMCK_DIV = 4
3768 23:08:31.311866 CA_AAMCK_DIV = 4
3769 23:08:31.315384 CA_ADMCK_DIV = 4
3770 23:08:31.318175 DQ_TRACK_CA_EN = 0
3771 23:08:31.321693 CA_PICK = 600
3772 23:08:31.325219 CA_MCKIO = 600
3773 23:08:31.325879 MCKIO_SEMI = 0
3774 23:08:31.328226 PLL_FREQ = 2288
3775 23:08:31.331915 DQ_UI_PI_RATIO = 32
3776 23:08:31.334893 CA_UI_PI_RATIO = 0
3777 23:08:31.338313 ===================================
3778 23:08:31.341624 ===================================
3779 23:08:31.345128 memory_type:LPDDR4
3780 23:08:31.345748 GP_NUM : 10
3781 23:08:31.347797 SRAM_EN : 1
3782 23:08:31.351350 MD32_EN : 0
3783 23:08:31.351806 ===================================
3784 23:08:31.355085 [ANA_INIT] >>>>>>>>>>>>>>
3785 23:08:31.357938 <<<<<< [CONFIGURE PHASE]: ANA_TX
3786 23:08:31.361431 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3787 23:08:31.365366 ===================================
3788 23:08:31.368157 data_rate = 1200,PCW = 0X5800
3789 23:08:31.371631 ===================================
3790 23:08:31.374704 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3791 23:08:31.381622 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3792 23:08:31.384560 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3793 23:08:31.391252 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3794 23:08:31.394422 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3795 23:08:31.397688 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3796 23:08:31.398146 [ANA_INIT] flow start
3797 23:08:31.401467 [ANA_INIT] PLL >>>>>>>>
3798 23:08:31.404871 [ANA_INIT] PLL <<<<<<<<
3799 23:08:31.405322 [ANA_INIT] MIDPI >>>>>>>>
3800 23:08:31.408167 [ANA_INIT] MIDPI <<<<<<<<
3801 23:08:31.411465 [ANA_INIT] DLL >>>>>>>>
3802 23:08:31.411922 [ANA_INIT] flow end
3803 23:08:31.418100 ============ LP4 DIFF to SE enter ============
3804 23:08:31.422051 ============ LP4 DIFF to SE exit ============
3805 23:08:31.424805 [ANA_INIT] <<<<<<<<<<<<<
3806 23:08:31.428645 [Flow] Enable top DCM control >>>>>
3807 23:08:31.429197 [Flow] Enable top DCM control <<<<<
3808 23:08:31.432103 Enable DLL master slave shuffle
3809 23:08:31.438369 ==============================================================
3810 23:08:31.441236 Gating Mode config
3811 23:08:31.444782 ==============================================================
3812 23:08:31.448375 Config description:
3813 23:08:31.458609 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3814 23:08:31.465295 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3815 23:08:31.467975 SELPH_MODE 0: By rank 1: By Phase
3816 23:08:31.474757 ==============================================================
3817 23:08:31.477865 GAT_TRACK_EN = 1
3818 23:08:31.481508 RX_GATING_MODE = 2
3819 23:08:31.482001 RX_GATING_TRACK_MODE = 2
3820 23:08:31.484558 SELPH_MODE = 1
3821 23:08:31.488045 PICG_EARLY_EN = 1
3822 23:08:31.491296 VALID_LAT_VALUE = 1
3823 23:08:31.497889 ==============================================================
3824 23:08:31.501325 Enter into Gating configuration >>>>
3825 23:08:31.504415 Exit from Gating configuration <<<<
3826 23:08:31.507972 Enter into DVFS_PRE_config >>>>>
3827 23:08:31.517985 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3828 23:08:31.520758 Exit from DVFS_PRE_config <<<<<
3829 23:08:31.524810 Enter into PICG configuration >>>>
3830 23:08:31.527825 Exit from PICG configuration <<<<
3831 23:08:31.530988 [RX_INPUT] configuration >>>>>
3832 23:08:31.534405 [RX_INPUT] configuration <<<<<
3833 23:08:31.537571 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3834 23:08:31.543977 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3835 23:08:31.550534 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3836 23:08:31.557651 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3837 23:08:31.561209 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3838 23:08:31.567345 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3839 23:08:31.570939 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3840 23:08:31.577338 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3841 23:08:31.580557 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3842 23:08:31.583776 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3843 23:08:31.587348 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3844 23:08:31.593732 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3845 23:08:31.597049 ===================================
3846 23:08:31.600688 LPDDR4 DRAM CONFIGURATION
3847 23:08:31.603910 ===================================
3848 23:08:31.604209 EX_ROW_EN[0] = 0x0
3849 23:08:31.607225 EX_ROW_EN[1] = 0x0
3850 23:08:31.607521 LP4Y_EN = 0x0
3851 23:08:31.610411 WORK_FSP = 0x0
3852 23:08:31.610645 WL = 0x2
3853 23:08:31.614044 RL = 0x2
3854 23:08:31.614224 BL = 0x2
3855 23:08:31.616887 RPST = 0x0
3856 23:08:31.617066 RD_PRE = 0x0
3857 23:08:31.620175 WR_PRE = 0x1
3858 23:08:31.620262 WR_PST = 0x0
3859 23:08:31.623527 DBI_WR = 0x0
3860 23:08:31.623614 DBI_RD = 0x0
3861 23:08:31.626991 OTF = 0x1
3862 23:08:31.630302 ===================================
3863 23:08:31.633705 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3864 23:08:31.636838 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3865 23:08:31.643578 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3866 23:08:31.646563 ===================================
3867 23:08:31.646649 LPDDR4 DRAM CONFIGURATION
3868 23:08:31.649815 ===================================
3869 23:08:31.653247 EX_ROW_EN[0] = 0x10
3870 23:08:31.657152 EX_ROW_EN[1] = 0x0
3871 23:08:31.657239 LP4Y_EN = 0x0
3872 23:08:31.659913 WORK_FSP = 0x0
3873 23:08:31.659995 WL = 0x2
3874 23:08:31.663116 RL = 0x2
3875 23:08:31.663227 BL = 0x2
3876 23:08:31.666836 RPST = 0x0
3877 23:08:31.666927 RD_PRE = 0x0
3878 23:08:31.670231 WR_PRE = 0x1
3879 23:08:31.670358 WR_PST = 0x0
3880 23:08:31.673438 DBI_WR = 0x0
3881 23:08:31.673552 DBI_RD = 0x0
3882 23:08:31.676806 OTF = 0x1
3883 23:08:31.679986 ===================================
3884 23:08:31.686423 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3885 23:08:31.689925 nWR fixed to 30
3886 23:08:31.693109 [ModeRegInit_LP4] CH0 RK0
3887 23:08:31.693238 [ModeRegInit_LP4] CH0 RK1
3888 23:08:31.696740 [ModeRegInit_LP4] CH1 RK0
3889 23:08:31.699847 [ModeRegInit_LP4] CH1 RK1
3890 23:08:31.699930 match AC timing 17
3891 23:08:31.706715 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3892 23:08:31.709834 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3893 23:08:31.713292 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3894 23:08:31.719496 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3895 23:08:31.723226 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3896 23:08:31.723317 ==
3897 23:08:31.726095 Dram Type= 6, Freq= 0, CH_0, rank 0
3898 23:08:31.729813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3899 23:08:31.729902 ==
3900 23:08:31.736284 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3901 23:08:31.743355 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3902 23:08:31.746127 [CA 0] Center 35 (5~66) winsize 62
3903 23:08:31.749958 [CA 1] Center 35 (5~66) winsize 62
3904 23:08:31.752509 [CA 2] Center 33 (3~64) winsize 62
3905 23:08:31.756023 [CA 3] Center 33 (2~64) winsize 63
3906 23:08:31.759207 [CA 4] Center 33 (2~64) winsize 63
3907 23:08:31.762373 [CA 5] Center 32 (2~63) winsize 62
3908 23:08:31.762460
3909 23:08:31.765795 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3910 23:08:31.765880
3911 23:08:31.769270 [CATrainingPosCal] consider 1 rank data
3912 23:08:31.772421 u2DelayCellTimex100 = 270/100 ps
3913 23:08:31.775803 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3914 23:08:31.779588 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3915 23:08:31.782562 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3916 23:08:31.786022 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3917 23:08:31.789057 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3918 23:08:31.795676 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3919 23:08:31.795759
3920 23:08:31.798883 CA PerBit enable=1, Macro0, CA PI delay=32
3921 23:08:31.798967
3922 23:08:31.802290 [CBTSetCACLKResult] CA Dly = 32
3923 23:08:31.802402 CS Dly: 5 (0~36)
3924 23:08:31.802495 ==
3925 23:08:31.805619 Dram Type= 6, Freq= 0, CH_0, rank 1
3926 23:08:31.809272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3927 23:08:31.809380 ==
3928 23:08:31.815627 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3929 23:08:31.822580 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3930 23:08:31.825752 [CA 0] Center 36 (5~67) winsize 63
3931 23:08:31.828809 [CA 1] Center 36 (5~67) winsize 63
3932 23:08:31.832204 [CA 2] Center 34 (3~65) winsize 63
3933 23:08:31.836034 [CA 3] Center 33 (3~64) winsize 62
3934 23:08:31.839386 [CA 4] Center 33 (2~64) winsize 63
3935 23:08:31.842726 [CA 5] Center 32 (2~63) winsize 62
3936 23:08:31.843179
3937 23:08:31.845919 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3938 23:08:31.846351
3939 23:08:31.849024 [CATrainingPosCal] consider 2 rank data
3940 23:08:31.852459 u2DelayCellTimex100 = 270/100 ps
3941 23:08:31.855736 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3942 23:08:31.859245 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3943 23:08:31.862814 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3944 23:08:31.866071 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3945 23:08:31.872463 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3946 23:08:31.876142 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3947 23:08:31.876553
3948 23:08:31.878992 CA PerBit enable=1, Macro0, CA PI delay=32
3949 23:08:31.879404
3950 23:08:31.882198 [CBTSetCACLKResult] CA Dly = 32
3951 23:08:31.882719 CS Dly: 5 (0~36)
3952 23:08:31.883064
3953 23:08:31.885640 ----->DramcWriteLeveling(PI) begin...
3954 23:08:31.886057 ==
3955 23:08:31.888788 Dram Type= 6, Freq= 0, CH_0, rank 0
3956 23:08:31.896030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3957 23:08:31.896444 ==
3958 23:08:31.898952 Write leveling (Byte 0): 34 => 34
3959 23:08:31.902511 Write leveling (Byte 1): 31 => 31
3960 23:08:31.902925 DramcWriteLeveling(PI) end<-----
3961 23:08:31.903315
3962 23:08:31.905966 ==
3963 23:08:31.909063 Dram Type= 6, Freq= 0, CH_0, rank 0
3964 23:08:31.912572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3965 23:08:31.913000 ==
3966 23:08:31.915527 [Gating] SW mode calibration
3967 23:08:31.921865 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3968 23:08:31.925687 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3969 23:08:31.931864 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3970 23:08:31.935439 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3971 23:08:31.938417 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3972 23:08:31.945270 0 9 12 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
3973 23:08:31.948568 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
3974 23:08:31.951929 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3975 23:08:31.958990 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3976 23:08:31.962429 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3977 23:08:31.965372 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3978 23:08:31.971888 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3979 23:08:31.975179 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3980 23:08:31.978434 0 10 12 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
3981 23:08:31.985044 0 10 16 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
3982 23:08:31.988195 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3983 23:08:31.991797 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3984 23:08:31.998965 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3985 23:08:32.001648 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3986 23:08:32.004877 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3987 23:08:32.012145 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3988 23:08:32.015397 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
3989 23:08:32.018304 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3990 23:08:32.021704 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3991 23:08:32.028360 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3992 23:08:32.031757 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3993 23:08:32.035032 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3994 23:08:32.041375 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 23:08:32.044905 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 23:08:32.048084 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 23:08:32.054800 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 23:08:32.058267 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 23:08:32.061537 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 23:08:32.067776 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 23:08:32.071427 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 23:08:32.074253 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 23:08:32.081294 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 23:08:32.084441 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4005 23:08:32.087673 Total UI for P1: 0, mck2ui 16
4006 23:08:32.091107 best dqsien dly found for B0: ( 0, 13, 10)
4007 23:08:32.094245 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4008 23:08:32.097900 Total UI for P1: 0, mck2ui 16
4009 23:08:32.101226 best dqsien dly found for B1: ( 0, 13, 14)
4010 23:08:32.104181 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4011 23:08:32.107624 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4012 23:08:32.107705
4013 23:08:32.114241 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4014 23:08:32.117935 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4015 23:08:32.118017 [Gating] SW calibration Done
4016 23:08:32.120989 ==
4017 23:08:32.124222 Dram Type= 6, Freq= 0, CH_0, rank 0
4018 23:08:32.127580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4019 23:08:32.127662 ==
4020 23:08:32.127726 RX Vref Scan: 0
4021 23:08:32.127786
4022 23:08:32.131068 RX Vref 0 -> 0, step: 1
4023 23:08:32.131154
4024 23:08:32.134289 RX Delay -230 -> 252, step: 16
4025 23:08:32.137881 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4026 23:08:32.141137 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4027 23:08:32.147417 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4028 23:08:32.151043 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4029 23:08:32.154751 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4030 23:08:32.157595 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4031 23:08:32.164365 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4032 23:08:32.168071 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4033 23:08:32.170765 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4034 23:08:32.174441 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4035 23:08:32.177714 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4036 23:08:32.184572 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4037 23:08:32.188139 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4038 23:08:32.190988 iDelay=218, Bit 13, Center 57 (-86 ~ 201) 288
4039 23:08:32.194295 iDelay=218, Bit 14, Center 65 (-86 ~ 217) 304
4040 23:08:32.201076 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4041 23:08:32.201707 ==
4042 23:08:32.204583 Dram Type= 6, Freq= 0, CH_0, rank 0
4043 23:08:32.207884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4044 23:08:32.208336 ==
4045 23:08:32.208698 DQS Delay:
4046 23:08:32.211683 DQS0 = 0, DQS1 = 0
4047 23:08:32.212346 DQM Delay:
4048 23:08:32.214384 DQM0 = 54, DQM1 = 48
4049 23:08:32.214838 DQ Delay:
4050 23:08:32.217965 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4051 23:08:32.221067 DQ4 =57, DQ5 =41, DQ6 =65, DQ7 =65
4052 23:08:32.224823 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4053 23:08:32.228214 DQ12 =49, DQ13 =57, DQ14 =65, DQ15 =57
4054 23:08:32.228779
4055 23:08:32.229144
4056 23:08:32.229478 ==
4057 23:08:32.230861 Dram Type= 6, Freq= 0, CH_0, rank 0
4058 23:08:32.234210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4059 23:08:32.234671 ==
4060 23:08:32.235035
4061 23:08:32.237751
4062 23:08:32.238436 TX Vref Scan disable
4063 23:08:32.241285 == TX Byte 0 ==
4064 23:08:32.244024 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4065 23:08:32.247660 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4066 23:08:32.251316 == TX Byte 1 ==
4067 23:08:32.254234 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4068 23:08:32.257510 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4069 23:08:32.258019 ==
4070 23:08:32.260707 Dram Type= 6, Freq= 0, CH_0, rank 0
4071 23:08:32.267550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4072 23:08:32.268106 ==
4073 23:08:32.268471
4074 23:08:32.268806
4075 23:08:32.269130 TX Vref Scan disable
4076 23:08:32.271761 == TX Byte 0 ==
4077 23:08:32.275261 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4078 23:08:32.282185 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4079 23:08:32.282729 == TX Byte 1 ==
4080 23:08:32.285739 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4081 23:08:32.291444 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4082 23:08:32.291906
4083 23:08:32.292270 [DATLAT]
4084 23:08:32.292606 Freq=600, CH0 RK0
4085 23:08:32.292932
4086 23:08:32.295148 DATLAT Default: 0x9
4087 23:08:32.295601 0, 0xFFFF, sum = 0
4088 23:08:32.298830 1, 0xFFFF, sum = 0
4089 23:08:32.301645 2, 0xFFFF, sum = 0
4090 23:08:32.302232 3, 0xFFFF, sum = 0
4091 23:08:32.304599 4, 0xFFFF, sum = 0
4092 23:08:32.305063 5, 0xFFFF, sum = 0
4093 23:08:32.307907 6, 0xFFFF, sum = 0
4094 23:08:32.308367 7, 0xFFFF, sum = 0
4095 23:08:32.311233 8, 0x0, sum = 1
4096 23:08:32.311695 9, 0x0, sum = 2
4097 23:08:32.312066 10, 0x0, sum = 3
4098 23:08:32.314922 11, 0x0, sum = 4
4099 23:08:32.315396 best_step = 9
4100 23:08:32.315758
4101 23:08:32.316156 ==
4102 23:08:32.318263 Dram Type= 6, Freq= 0, CH_0, rank 0
4103 23:08:32.324793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4104 23:08:32.325311 ==
4105 23:08:32.325702 RX Vref Scan: 1
4106 23:08:32.326022
4107 23:08:32.328360 RX Vref 0 -> 0, step: 1
4108 23:08:32.328884
4109 23:08:32.331305 RX Delay -163 -> 252, step: 8
4110 23:08:32.331717
4111 23:08:32.334577 Set Vref, RX VrefLevel [Byte0]: 53
4112 23:08:32.338043 [Byte1]: 46
4113 23:08:32.338457
4114 23:08:32.341395 Final RX Vref Byte 0 = 53 to rank0
4115 23:08:32.344615 Final RX Vref Byte 1 = 46 to rank0
4116 23:08:32.347634 Final RX Vref Byte 0 = 53 to rank1
4117 23:08:32.350998 Final RX Vref Byte 1 = 46 to rank1==
4118 23:08:32.354803 Dram Type= 6, Freq= 0, CH_0, rank 0
4119 23:08:32.358710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4120 23:08:32.359225 ==
4121 23:08:32.361417 DQS Delay:
4122 23:08:32.361989 DQS0 = 0, DQS1 = 0
4123 23:08:32.364511 DQM Delay:
4124 23:08:32.364920 DQM0 = 53, DQM1 = 47
4125 23:08:32.365246 DQ Delay:
4126 23:08:32.368191 DQ0 =52, DQ1 =56, DQ2 =48, DQ3 =52
4127 23:08:32.370911 DQ4 =56, DQ5 =44, DQ6 =60, DQ7 =56
4128 23:08:32.374216 DQ8 =36, DQ9 =36, DQ10 =52, DQ11 =40
4129 23:08:32.377763 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =56
4130 23:08:32.378289
4131 23:08:32.378621
4132 23:08:32.387771 [DQSOSCAuto] RK0, (LSB)MR18= 0x6d61, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 389 ps
4133 23:08:32.390982 CH0 RK0: MR19=808, MR18=6D61
4134 23:08:32.398040 CH0_RK0: MR19=0x808, MR18=0x6D61, DQSOSC=389, MR23=63, INC=173, DEC=115
4135 23:08:32.398560
4136 23:08:32.401483 ----->DramcWriteLeveling(PI) begin...
4137 23:08:32.402069 ==
4138 23:08:32.404109 Dram Type= 6, Freq= 0, CH_0, rank 1
4139 23:08:32.407543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4140 23:08:32.407959 ==
4141 23:08:32.410900 Write leveling (Byte 0): 36 => 36
4142 23:08:32.414229 Write leveling (Byte 1): 30 => 30
4143 23:08:32.417704 DramcWriteLeveling(PI) end<-----
4144 23:08:32.418184
4145 23:08:32.418515 ==
4146 23:08:32.420739 Dram Type= 6, Freq= 0, CH_0, rank 1
4147 23:08:32.424259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4148 23:08:32.424675 ==
4149 23:08:32.427637 [Gating] SW mode calibration
4150 23:08:32.434073 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4151 23:08:32.441226 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4152 23:08:32.443945 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4153 23:08:32.447260 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4154 23:08:32.453920 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4155 23:08:32.457492 0 9 12 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
4156 23:08:32.460902 0 9 16 | B1->B0 | 2e2e 2a2a | 0 0 | (1 1) (0 0)
4157 23:08:32.467495 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4158 23:08:32.470288 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4159 23:08:32.473701 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4160 23:08:32.480792 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4161 23:08:32.483785 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4162 23:08:32.487010 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4163 23:08:32.493438 0 10 12 | B1->B0 | 2c2c 2525 | 1 1 | (0 0) (0 0)
4164 23:08:32.497267 0 10 16 | B1->B0 | 3c3c 4343 | 0 0 | (0 0) (0 0)
4165 23:08:32.500406 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4166 23:08:32.506959 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4167 23:08:32.510231 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4168 23:08:32.513707 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4169 23:08:32.520575 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4170 23:08:32.524010 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4171 23:08:32.527051 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4172 23:08:32.533975 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4173 23:08:32.536986 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4174 23:08:32.540176 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4175 23:08:32.543618 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4176 23:08:32.550551 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4177 23:08:32.553356 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4178 23:08:32.557446 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4179 23:08:32.563896 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4180 23:08:32.567001 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4181 23:08:32.570623 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 23:08:32.577246 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 23:08:32.580593 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4184 23:08:32.584091 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 23:08:32.590275 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 23:08:32.593431 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 23:08:32.596918 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4188 23:08:32.603967 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4189 23:08:32.604574 Total UI for P1: 0, mck2ui 16
4190 23:08:32.610223 best dqsien dly found for B0: ( 0, 13, 12)
4191 23:08:32.610642 Total UI for P1: 0, mck2ui 16
4192 23:08:32.616779 best dqsien dly found for B1: ( 0, 13, 14)
4193 23:08:32.620216 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4194 23:08:32.623891 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4195 23:08:32.624408
4196 23:08:32.626733 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4197 23:08:32.630518 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4198 23:08:32.633955 [Gating] SW calibration Done
4199 23:08:32.634504 ==
4200 23:08:32.637025 Dram Type= 6, Freq= 0, CH_0, rank 1
4201 23:08:32.640880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4202 23:08:32.641398 ==
4203 23:08:32.643544 RX Vref Scan: 0
4204 23:08:32.643956
4205 23:08:32.644285 RX Vref 0 -> 0, step: 1
4206 23:08:32.644592
4207 23:08:32.646805 RX Delay -230 -> 252, step: 16
4208 23:08:32.653620 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4209 23:08:32.656534 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4210 23:08:32.660085 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4211 23:08:32.663518 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4212 23:08:32.667165 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4213 23:08:32.672985 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4214 23:08:32.676128 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4215 23:08:32.679536 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4216 23:08:32.683212 iDelay=218, Bit 8, Center 41 (-102 ~ 185) 288
4217 23:08:32.686369 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4218 23:08:32.693038 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4219 23:08:32.696724 iDelay=218, Bit 11, Center 41 (-102 ~ 185) 288
4220 23:08:32.699679 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4221 23:08:32.703286 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4222 23:08:32.709418 iDelay=218, Bit 14, Center 57 (-86 ~ 201) 288
4223 23:08:32.713008 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4224 23:08:32.713247 ==
4225 23:08:32.716314 Dram Type= 6, Freq= 0, CH_0, rank 1
4226 23:08:32.719577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4227 23:08:32.719812 ==
4228 23:08:32.723142 DQS Delay:
4229 23:08:32.723398 DQS0 = 0, DQS1 = 0
4230 23:08:32.723552 DQM Delay:
4231 23:08:32.726236 DQM0 = 54, DQM1 = 46
4232 23:08:32.726541 DQ Delay:
4233 23:08:32.729964 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4234 23:08:32.733385 DQ4 =57, DQ5 =49, DQ6 =65, DQ7 =65
4235 23:08:32.736501 DQ8 =41, DQ9 =33, DQ10 =49, DQ11 =41
4236 23:08:32.739690 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =49
4237 23:08:32.740081
4238 23:08:32.740316
4239 23:08:32.740535 ==
4240 23:08:32.742787 Dram Type= 6, Freq= 0, CH_0, rank 1
4241 23:08:32.749702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4242 23:08:32.750167 ==
4243 23:08:32.750532
4244 23:08:32.750869
4245 23:08:32.751194 TX Vref Scan disable
4246 23:08:32.753749 == TX Byte 0 ==
4247 23:08:32.757475 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
4248 23:08:32.763472 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
4249 23:08:32.764082 == TX Byte 1 ==
4250 23:08:32.767134 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4251 23:08:32.774037 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4252 23:08:32.774603 ==
4253 23:08:32.776875 Dram Type= 6, Freq= 0, CH_0, rank 1
4254 23:08:32.779971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4255 23:08:32.780436 ==
4256 23:08:32.780802
4257 23:08:32.781136
4258 23:08:32.783169 TX Vref Scan disable
4259 23:08:32.786544 == TX Byte 0 ==
4260 23:08:32.790188 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4261 23:08:32.793464 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4262 23:08:32.796632 == TX Byte 1 ==
4263 23:08:32.799732 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4264 23:08:32.803835 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4265 23:08:32.804594
4266 23:08:32.804987 [DATLAT]
4267 23:08:32.806364 Freq=600, CH0 RK1
4268 23:08:32.806823
4269 23:08:32.809711 DATLAT Default: 0x9
4270 23:08:32.810163 0, 0xFFFF, sum = 0
4271 23:08:32.813260 1, 0xFFFF, sum = 0
4272 23:08:32.813729 2, 0xFFFF, sum = 0
4273 23:08:32.816649 3, 0xFFFF, sum = 0
4274 23:08:32.817065 4, 0xFFFF, sum = 0
4275 23:08:32.819927 5, 0xFFFF, sum = 0
4276 23:08:32.820344 6, 0xFFFF, sum = 0
4277 23:08:32.823153 7, 0xFFFF, sum = 0
4278 23:08:32.823595 8, 0x0, sum = 1
4279 23:08:32.826683 9, 0x0, sum = 2
4280 23:08:32.827099 10, 0x0, sum = 3
4281 23:08:32.827432 11, 0x0, sum = 4
4282 23:08:32.830060 best_step = 9
4283 23:08:32.830574
4284 23:08:32.830906 ==
4285 23:08:32.833049 Dram Type= 6, Freq= 0, CH_0, rank 1
4286 23:08:32.836426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4287 23:08:32.836842 ==
4288 23:08:32.839650 RX Vref Scan: 0
4289 23:08:32.840063
4290 23:08:32.840393 RX Vref 0 -> 0, step: 1
4291 23:08:32.842984
4292 23:08:32.843417 RX Delay -163 -> 252, step: 8
4293 23:08:32.850635 iDelay=197, Bit 0, Center 52 (-91 ~ 196) 288
4294 23:08:32.853900 iDelay=197, Bit 1, Center 52 (-91 ~ 196) 288
4295 23:08:32.857035 iDelay=197, Bit 2, Center 52 (-91 ~ 196) 288
4296 23:08:32.860775 iDelay=197, Bit 3, Center 52 (-91 ~ 196) 288
4297 23:08:32.863566 iDelay=197, Bit 4, Center 52 (-91 ~ 196) 288
4298 23:08:32.870931 iDelay=197, Bit 5, Center 44 (-99 ~ 188) 288
4299 23:08:32.873472 iDelay=197, Bit 6, Center 56 (-83 ~ 196) 280
4300 23:08:32.877311 iDelay=197, Bit 7, Center 56 (-83 ~ 196) 280
4301 23:08:32.880238 iDelay=197, Bit 8, Center 40 (-99 ~ 180) 280
4302 23:08:32.883453 iDelay=197, Bit 9, Center 32 (-107 ~ 172) 280
4303 23:08:32.889907 iDelay=197, Bit 10, Center 48 (-91 ~ 188) 280
4304 23:08:32.893505 iDelay=197, Bit 11, Center 40 (-99 ~ 180) 280
4305 23:08:32.896747 iDelay=197, Bit 12, Center 52 (-83 ~ 188) 272
4306 23:08:32.899993 iDelay=197, Bit 13, Center 52 (-83 ~ 188) 272
4307 23:08:32.906996 iDelay=197, Bit 14, Center 56 (-83 ~ 196) 280
4308 23:08:32.910250 iDelay=197, Bit 15, Center 52 (-91 ~ 196) 288
4309 23:08:32.910332 ==
4310 23:08:32.913246 Dram Type= 6, Freq= 0, CH_0, rank 1
4311 23:08:32.916566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4312 23:08:32.916648 ==
4313 23:08:32.916712 DQS Delay:
4314 23:08:32.919996 DQS0 = 0, DQS1 = 0
4315 23:08:32.920077 DQM Delay:
4316 23:08:32.923140 DQM0 = 52, DQM1 = 46
4317 23:08:32.923220 DQ Delay:
4318 23:08:32.926424 DQ0 =52, DQ1 =52, DQ2 =52, DQ3 =52
4319 23:08:32.930043 DQ4 =52, DQ5 =44, DQ6 =56, DQ7 =56
4320 23:08:32.933403 DQ8 =40, DQ9 =32, DQ10 =48, DQ11 =40
4321 23:08:32.936661 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4322 23:08:32.936741
4323 23:08:32.936805
4324 23:08:32.946279 [DQSOSCAuto] RK1, (LSB)MR18= 0x6728, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 390 ps
4325 23:08:32.946365 CH0 RK1: MR19=808, MR18=6728
4326 23:08:32.953217 CH0_RK1: MR19=0x808, MR18=0x6728, DQSOSC=390, MR23=63, INC=172, DEC=114
4327 23:08:32.956783 [RxdqsGatingPostProcess] freq 600
4328 23:08:32.962751 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4329 23:08:32.966479 Pre-setting of DQS Precalculation
4330 23:08:32.969368 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4331 23:08:32.969451 ==
4332 23:08:32.973056 Dram Type= 6, Freq= 0, CH_1, rank 0
4333 23:08:32.976185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4334 23:08:32.979662 ==
4335 23:08:32.982571 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4336 23:08:32.989530 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4337 23:08:32.992556 [CA 0] Center 35 (5~66) winsize 62
4338 23:08:32.996242 [CA 1] Center 36 (5~67) winsize 63
4339 23:08:32.999454 [CA 2] Center 34 (4~65) winsize 62
4340 23:08:33.003053 [CA 3] Center 34 (4~65) winsize 62
4341 23:08:33.006074 [CA 4] Center 34 (4~65) winsize 62
4342 23:08:33.009474 [CA 5] Center 34 (4~64) winsize 61
4343 23:08:33.009555
4344 23:08:33.012746 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4345 23:08:33.012826
4346 23:08:33.016462 [CATrainingPosCal] consider 1 rank data
4347 23:08:33.019670 u2DelayCellTimex100 = 270/100 ps
4348 23:08:33.022346 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4349 23:08:33.026090 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4350 23:08:33.029358 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4351 23:08:33.036019 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4352 23:08:33.039149 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4353 23:08:33.042019 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4354 23:08:33.042119
4355 23:08:33.045501 CA PerBit enable=1, Macro0, CA PI delay=34
4356 23:08:33.045657
4357 23:08:33.048802 [CBTSetCACLKResult] CA Dly = 34
4358 23:08:33.048909 CS Dly: 6 (0~37)
4359 23:08:33.048995 ==
4360 23:08:33.052115 Dram Type= 6, Freq= 0, CH_1, rank 1
4361 23:08:33.059299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4362 23:08:33.059404 ==
4363 23:08:33.062167 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4364 23:08:33.069101 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4365 23:08:33.072278 [CA 0] Center 36 (5~67) winsize 63
4366 23:08:33.075821 [CA 1] Center 36 (5~67) winsize 63
4367 23:08:33.078655 [CA 2] Center 35 (4~66) winsize 63
4368 23:08:33.082257 [CA 3] Center 34 (4~65) winsize 62
4369 23:08:33.085318 [CA 4] Center 34 (4~65) winsize 62
4370 23:08:33.088842 [CA 5] Center 34 (3~65) winsize 63
4371 23:08:33.088944
4372 23:08:33.092513 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4373 23:08:33.092613
4374 23:08:33.096060 [CATrainingPosCal] consider 2 rank data
4375 23:08:33.098613 u2DelayCellTimex100 = 270/100 ps
4376 23:08:33.101929 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4377 23:08:33.105810 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4378 23:08:33.112548 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4379 23:08:33.115950 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4380 23:08:33.118730 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4381 23:08:33.122036 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4382 23:08:33.122142
4383 23:08:33.125384 CA PerBit enable=1, Macro0, CA PI delay=34
4384 23:08:33.125508
4385 23:08:33.128580 [CBTSetCACLKResult] CA Dly = 34
4386 23:08:33.128689 CS Dly: 6 (0~37)
4387 23:08:33.128793
4388 23:08:33.132455 ----->DramcWriteLeveling(PI) begin...
4389 23:08:33.135447 ==
4390 23:08:33.135562 Dram Type= 6, Freq= 0, CH_1, rank 0
4391 23:08:33.142482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4392 23:08:33.142596 ==
4393 23:08:33.145753 Write leveling (Byte 0): 32 => 32
4394 23:08:33.148954 Write leveling (Byte 1): 32 => 32
4395 23:08:33.152070 DramcWriteLeveling(PI) end<-----
4396 23:08:33.152172
4397 23:08:33.152272 ==
4398 23:08:33.155475 Dram Type= 6, Freq= 0, CH_1, rank 0
4399 23:08:33.159040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4400 23:08:33.159153 ==
4401 23:08:33.161971 [Gating] SW mode calibration
4402 23:08:33.168769 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4403 23:08:33.172482 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4404 23:08:33.178691 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4405 23:08:33.182434 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4406 23:08:33.185252 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4407 23:08:33.191910 0 9 12 | B1->B0 | 3030 2c2c | 0 1 | (0 1) (1 0)
4408 23:08:33.195601 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4409 23:08:33.198519 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4410 23:08:33.205331 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4411 23:08:33.208908 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4412 23:08:33.211809 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4413 23:08:33.218893 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4414 23:08:33.221761 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4415 23:08:33.225399 0 10 12 | B1->B0 | 3434 3838 | 0 0 | (0 0) (0 0)
4416 23:08:33.231825 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4417 23:08:33.235185 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4418 23:08:33.238856 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4419 23:08:33.245215 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4420 23:08:33.248715 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4421 23:08:33.251713 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4422 23:08:33.258522 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4423 23:08:33.261910 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4424 23:08:33.264953 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4425 23:08:33.271852 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4426 23:08:33.275430 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4427 23:08:33.278384 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4428 23:08:33.285312 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4429 23:08:33.288740 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 23:08:33.291563 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 23:08:33.298854 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 23:08:33.302057 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 23:08:33.305378 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 23:08:33.308811 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 23:08:33.315246 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 23:08:33.318544 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 23:08:33.321592 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 23:08:33.328579 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 23:08:33.331540 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4440 23:08:33.334990 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4441 23:08:33.338019 Total UI for P1: 0, mck2ui 16
4442 23:08:33.341329 best dqsien dly found for B0: ( 0, 13, 12)
4443 23:08:33.345244 Total UI for P1: 0, mck2ui 16
4444 23:08:33.348167 best dqsien dly found for B1: ( 0, 13, 12)
4445 23:08:33.351380 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4446 23:08:33.354755 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4447 23:08:33.354854
4448 23:08:33.361679 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4449 23:08:33.365234 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4450 23:08:33.368588 [Gating] SW calibration Done
4451 23:08:33.368671 ==
4452 23:08:33.371409 Dram Type= 6, Freq= 0, CH_1, rank 0
4453 23:08:33.375331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4454 23:08:33.375413 ==
4455 23:08:33.375478 RX Vref Scan: 0
4456 23:08:33.375538
4457 23:08:33.378248 RX Vref 0 -> 0, step: 1
4458 23:08:33.378329
4459 23:08:33.381492 RX Delay -230 -> 252, step: 16
4460 23:08:33.385065 iDelay=218, Bit 0, Center 65 (-86 ~ 217) 304
4461 23:08:33.387853 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4462 23:08:33.394530 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4463 23:08:33.398213 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4464 23:08:33.401286 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4465 23:08:33.404993 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4466 23:08:33.411135 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4467 23:08:33.414744 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4468 23:08:33.417911 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4469 23:08:33.421395 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4470 23:08:33.424641 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4471 23:08:33.431529 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4472 23:08:33.434416 iDelay=218, Bit 12, Center 65 (-86 ~ 217) 304
4473 23:08:33.438180 iDelay=218, Bit 13, Center 57 (-86 ~ 201) 288
4474 23:08:33.441236 iDelay=218, Bit 14, Center 57 (-86 ~ 201) 288
4475 23:08:33.447745 iDelay=218, Bit 15, Center 65 (-86 ~ 217) 304
4476 23:08:33.447825 ==
4477 23:08:33.451364 Dram Type= 6, Freq= 0, CH_1, rank 0
4478 23:08:33.454198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4479 23:08:33.454280 ==
4480 23:08:33.454345 DQS Delay:
4481 23:08:33.457762 DQS0 = 0, DQS1 = 0
4482 23:08:33.457843 DQM Delay:
4483 23:08:33.460846 DQM0 = 53, DQM1 = 50
4484 23:08:33.460925 DQ Delay:
4485 23:08:33.464155 DQ0 =65, DQ1 =41, DQ2 =41, DQ3 =49
4486 23:08:33.467784 DQ4 =49, DQ5 =65, DQ6 =65, DQ7 =49
4487 23:08:33.471032 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4488 23:08:33.474270 DQ12 =65, DQ13 =57, DQ14 =57, DQ15 =65
4489 23:08:33.474352
4490 23:08:33.474417
4491 23:08:33.474477 ==
4492 23:08:33.477630 Dram Type= 6, Freq= 0, CH_1, rank 0
4493 23:08:33.481113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4494 23:08:33.481195 ==
4495 23:08:33.481260
4496 23:08:33.484354
4497 23:08:33.484433 TX Vref Scan disable
4498 23:08:33.487607 == TX Byte 0 ==
4499 23:08:33.490955 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4500 23:08:33.494503 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4501 23:08:33.497516 == TX Byte 1 ==
4502 23:08:33.500664 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4503 23:08:33.504150 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4504 23:08:33.504231 ==
4505 23:08:33.507513 Dram Type= 6, Freq= 0, CH_1, rank 0
4506 23:08:33.513779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4507 23:08:33.513861 ==
4508 23:08:33.513926
4509 23:08:33.513984
4510 23:08:33.514041 TX Vref Scan disable
4511 23:08:33.518439 == TX Byte 0 ==
4512 23:08:33.522034 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4513 23:08:33.528956 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4514 23:08:33.529037 == TX Byte 1 ==
4515 23:08:33.531606 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4516 23:08:33.538431 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4517 23:08:33.538512
4518 23:08:33.538576 [DATLAT]
4519 23:08:33.538635 Freq=600, CH1 RK0
4520 23:08:33.538692
4521 23:08:33.541513 DATLAT Default: 0x9
4522 23:08:33.541632 0, 0xFFFF, sum = 0
4523 23:08:33.544873 1, 0xFFFF, sum = 0
4524 23:08:33.544955 2, 0xFFFF, sum = 0
4525 23:08:33.548581 3, 0xFFFF, sum = 0
4526 23:08:33.551440 4, 0xFFFF, sum = 0
4527 23:08:33.551523 5, 0xFFFF, sum = 0
4528 23:08:33.555140 6, 0xFFFF, sum = 0
4529 23:08:33.555222 7, 0xFFFF, sum = 0
4530 23:08:33.558300 8, 0x0, sum = 1
4531 23:08:33.558382 9, 0x0, sum = 2
4532 23:08:33.558447 10, 0x0, sum = 3
4533 23:08:33.561873 11, 0x0, sum = 4
4534 23:08:33.561955 best_step = 9
4535 23:08:33.562019
4536 23:08:33.562079 ==
4537 23:08:33.565332 Dram Type= 6, Freq= 0, CH_1, rank 0
4538 23:08:33.571642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4539 23:08:33.571724 ==
4540 23:08:33.571788 RX Vref Scan: 1
4541 23:08:33.571848
4542 23:08:33.575395 RX Vref 0 -> 0, step: 1
4543 23:08:33.575475
4544 23:08:33.578066 RX Delay -163 -> 252, step: 8
4545 23:08:33.578146
4546 23:08:33.581473 Set Vref, RX VrefLevel [Byte0]: 54
4547 23:08:33.585011 [Byte1]: 52
4548 23:08:33.585092
4549 23:08:33.588344 Final RX Vref Byte 0 = 54 to rank0
4550 23:08:33.591590 Final RX Vref Byte 1 = 52 to rank0
4551 23:08:33.594682 Final RX Vref Byte 0 = 54 to rank1
4552 23:08:33.597872 Final RX Vref Byte 1 = 52 to rank1==
4553 23:08:33.601357 Dram Type= 6, Freq= 0, CH_1, rank 0
4554 23:08:33.604512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4555 23:08:33.604595 ==
4556 23:08:33.607824 DQS Delay:
4557 23:08:33.607904 DQS0 = 0, DQS1 = 0
4558 23:08:33.611512 DQM Delay:
4559 23:08:33.611591 DQM0 = 48, DQM1 = 47
4560 23:08:33.611655 DQ Delay:
4561 23:08:33.614460 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =44
4562 23:08:33.617918 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4563 23:08:33.621473 DQ8 =36, DQ9 =36, DQ10 =44, DQ11 =36
4564 23:08:33.624499 DQ12 =56, DQ13 =52, DQ14 =56, DQ15 =60
4565 23:08:33.624580
4566 23:08:33.624643
4567 23:08:33.634664 [DQSOSCAuto] RK0, (LSB)MR18= 0x4b71, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4568 23:08:33.638015 CH1 RK0: MR19=808, MR18=4B71
4569 23:08:33.641301 CH1_RK0: MR19=0x808, MR18=0x4B71, DQSOSC=388, MR23=63, INC=174, DEC=116
4570 23:08:33.645217
4571 23:08:33.648013 ----->DramcWriteLeveling(PI) begin...
4572 23:08:33.648097 ==
4573 23:08:33.651159 Dram Type= 6, Freq= 0, CH_1, rank 1
4574 23:08:33.654742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4575 23:08:33.654824 ==
4576 23:08:33.657736 Write leveling (Byte 0): 31 => 31
4577 23:08:33.661463 Write leveling (Byte 1): 29 => 29
4578 23:08:33.664443 DramcWriteLeveling(PI) end<-----
4579 23:08:33.664524
4580 23:08:33.664587 ==
4581 23:08:33.667890 Dram Type= 6, Freq= 0, CH_1, rank 1
4582 23:08:33.671351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4583 23:08:33.671432 ==
4584 23:08:33.674248 [Gating] SW mode calibration
4585 23:08:33.681470 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4586 23:08:33.687779 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4587 23:08:33.690736 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4588 23:08:33.694306 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4589 23:08:33.701252 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4590 23:08:33.704231 0 9 12 | B1->B0 | 2d2d 2d2d | 0 1 | (0 0) (1 1)
4591 23:08:33.707580 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4592 23:08:33.714171 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4593 23:08:33.717313 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4594 23:08:33.720566 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4595 23:08:33.727441 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4596 23:08:33.730615 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4597 23:08:33.734286 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4598 23:08:33.740633 0 10 12 | B1->B0 | 3939 3434 | 0 0 | (0 0) (0 0)
4599 23:08:33.743786 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4600 23:08:33.747271 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4601 23:08:33.750941 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4602 23:08:33.757388 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4603 23:08:33.760554 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4604 23:08:33.764049 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4605 23:08:33.770745 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4606 23:08:33.774317 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4607 23:08:33.777265 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4608 23:08:33.784039 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4609 23:08:33.787011 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4610 23:08:33.790741 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4611 23:08:33.797145 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4612 23:08:33.800002 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4613 23:08:33.803653 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4614 23:08:33.810299 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4615 23:08:33.813380 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4616 23:08:33.816907 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 23:08:33.823268 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4618 23:08:33.827229 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 23:08:33.830404 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 23:08:33.836996 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 23:08:33.839876 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 23:08:33.843427 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4623 23:08:33.846571 Total UI for P1: 0, mck2ui 16
4624 23:08:33.849891 best dqsien dly found for B0: ( 0, 13, 10)
4625 23:08:33.853307 Total UI for P1: 0, mck2ui 16
4626 23:08:33.856668 best dqsien dly found for B1: ( 0, 13, 10)
4627 23:08:33.861030 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4628 23:08:33.863445 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4629 23:08:33.863526
4630 23:08:33.870326 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4631 23:08:33.873370 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4632 23:08:33.876568 [Gating] SW calibration Done
4633 23:08:33.876642 ==
4634 23:08:33.880181 Dram Type= 6, Freq= 0, CH_1, rank 1
4635 23:08:33.883537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4636 23:08:33.883617 ==
4637 23:08:33.883680 RX Vref Scan: 0
4638 23:08:33.883739
4639 23:08:33.886647 RX Vref 0 -> 0, step: 1
4640 23:08:33.886727
4641 23:08:33.890025 RX Delay -230 -> 252, step: 16
4642 23:08:33.893485 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4643 23:08:33.896533 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4644 23:08:33.902966 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4645 23:08:33.906476 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4646 23:08:33.909738 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4647 23:08:33.912767 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4648 23:08:33.920480 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4649 23:08:33.923584 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4650 23:08:33.926757 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4651 23:08:33.930292 iDelay=218, Bit 9, Center 41 (-118 ~ 201) 320
4652 23:08:33.933233 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4653 23:08:33.940029 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4654 23:08:33.943174 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4655 23:08:33.946368 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4656 23:08:33.949580 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4657 23:08:33.956303 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4658 23:08:33.956384 ==
4659 23:08:33.959599 Dram Type= 6, Freq= 0, CH_1, rank 1
4660 23:08:33.963296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4661 23:08:33.963377 ==
4662 23:08:33.963441 DQS Delay:
4663 23:08:33.966200 DQS0 = 0, DQS1 = 0
4664 23:08:33.966278 DQM Delay:
4665 23:08:33.969547 DQM0 = 48, DQM1 = 48
4666 23:08:33.969648 DQ Delay:
4667 23:08:33.972916 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =49
4668 23:08:33.976368 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4669 23:08:33.980108 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =41
4670 23:08:33.983328 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4671 23:08:33.983408
4672 23:08:33.983471
4673 23:08:33.983529 ==
4674 23:08:33.986287 Dram Type= 6, Freq= 0, CH_1, rank 1
4675 23:08:33.989523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4676 23:08:33.993200 ==
4677 23:08:33.993278
4678 23:08:33.993341
4679 23:08:33.993399 TX Vref Scan disable
4680 23:08:33.996279 == TX Byte 0 ==
4681 23:08:33.999339 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4682 23:08:34.003074 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4683 23:08:34.005946 == TX Byte 1 ==
4684 23:08:34.009420 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4685 23:08:34.012524 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4686 23:08:34.015813 ==
4687 23:08:34.019699 Dram Type= 6, Freq= 0, CH_1, rank 1
4688 23:08:34.022901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4689 23:08:34.023049 ==
4690 23:08:34.023145
4691 23:08:34.023232
4692 23:08:34.026169 TX Vref Scan disable
4693 23:08:34.026340 == TX Byte 0 ==
4694 23:08:34.032685 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4695 23:08:34.035818 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4696 23:08:34.035898 == TX Byte 1 ==
4697 23:08:34.042331 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4698 23:08:34.045525 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4699 23:08:34.045638
4700 23:08:34.045702 [DATLAT]
4701 23:08:34.048724 Freq=600, CH1 RK1
4702 23:08:34.048804
4703 23:08:34.048873 DATLAT Default: 0x9
4704 23:08:34.052574 0, 0xFFFF, sum = 0
4705 23:08:34.052655 1, 0xFFFF, sum = 0
4706 23:08:34.055446 2, 0xFFFF, sum = 0
4707 23:08:34.059084 3, 0xFFFF, sum = 0
4708 23:08:34.059165 4, 0xFFFF, sum = 0
4709 23:08:34.062481 5, 0xFFFF, sum = 0
4710 23:08:34.062562 6, 0xFFFF, sum = 0
4711 23:08:34.065504 7, 0xFFFF, sum = 0
4712 23:08:34.065590 8, 0x0, sum = 1
4713 23:08:34.065656 9, 0x0, sum = 2
4714 23:08:34.069175 10, 0x0, sum = 3
4715 23:08:34.069256 11, 0x0, sum = 4
4716 23:08:34.072045 best_step = 9
4717 23:08:34.072124
4718 23:08:34.072187 ==
4719 23:08:34.075358 Dram Type= 6, Freq= 0, CH_1, rank 1
4720 23:08:34.079458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4721 23:08:34.079538 ==
4722 23:08:34.082640 RX Vref Scan: 0
4723 23:08:34.082719
4724 23:08:34.082780 RX Vref 0 -> 0, step: 1
4725 23:08:34.082838
4726 23:08:34.085358 RX Delay -163 -> 252, step: 8
4727 23:08:34.092846 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4728 23:08:34.095898 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4729 23:08:34.099213 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4730 23:08:34.102618 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4731 23:08:34.109482 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4732 23:08:34.112649 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4733 23:08:34.115852 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4734 23:08:34.119329 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4735 23:08:34.122478 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4736 23:08:34.129300 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4737 23:08:34.132456 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4738 23:08:34.135885 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4739 23:08:34.138971 iDelay=205, Bit 12, Center 56 (-91 ~ 204) 296
4740 23:08:34.142473 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4741 23:08:34.149253 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4742 23:08:34.152279 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4743 23:08:34.152359 ==
4744 23:08:34.156148 Dram Type= 6, Freq= 0, CH_1, rank 1
4745 23:08:34.159147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4746 23:08:34.159232 ==
4747 23:08:34.162540 DQS Delay:
4748 23:08:34.162657 DQS0 = 0, DQS1 = 0
4749 23:08:34.162749 DQM Delay:
4750 23:08:34.165433 DQM0 = 49, DQM1 = 46
4751 23:08:34.165542 DQ Delay:
4752 23:08:34.168723 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4753 23:08:34.172254 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =48
4754 23:08:34.176207 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4755 23:08:34.179037 DQ12 =56, DQ13 =52, DQ14 =52, DQ15 =56
4756 23:08:34.179122
4757 23:08:34.179189
4758 23:08:34.189214 [DQSOSCAuto] RK1, (LSB)MR18= 0x6921, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 390 ps
4759 23:08:34.192412 CH1 RK1: MR19=808, MR18=6921
4760 23:08:34.196139 CH1_RK1: MR19=0x808, MR18=0x6921, DQSOSC=390, MR23=63, INC=172, DEC=114
4761 23:08:34.199146 [RxdqsGatingPostProcess] freq 600
4762 23:08:34.206143 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4763 23:08:34.209452 Pre-setting of DQS Precalculation
4764 23:08:34.212339 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4765 23:08:34.219067 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4766 23:08:34.229282 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4767 23:08:34.229573
4768 23:08:34.229844
4769 23:08:34.232761 [Calibration Summary] 1200 Mbps
4770 23:08:34.233134 CH 0, Rank 0
4771 23:08:34.236426 SW Impedance : PASS
4772 23:08:34.236838 DUTY Scan : NO K
4773 23:08:34.239493 ZQ Calibration : PASS
4774 23:08:34.239900 Jitter Meter : NO K
4775 23:08:34.243008 CBT Training : PASS
4776 23:08:34.246075 Write leveling : PASS
4777 23:08:34.246483 RX DQS gating : PASS
4778 23:08:34.249153 RX DQ/DQS(RDDQC) : PASS
4779 23:08:34.252542 TX DQ/DQS : PASS
4780 23:08:34.252949 RX DATLAT : PASS
4781 23:08:34.256607 RX DQ/DQS(Engine): PASS
4782 23:08:34.259561 TX OE : NO K
4783 23:08:34.260067 All Pass.
4784 23:08:34.260398
4785 23:08:34.260703 CH 0, Rank 1
4786 23:08:34.262697 SW Impedance : PASS
4787 23:08:34.266511 DUTY Scan : NO K
4788 23:08:34.266924 ZQ Calibration : PASS
4789 23:08:34.269357 Jitter Meter : NO K
4790 23:08:34.273011 CBT Training : PASS
4791 23:08:34.273523 Write leveling : PASS
4792 23:08:34.276069 RX DQS gating : PASS
4793 23:08:34.279245 RX DQ/DQS(RDDQC) : PASS
4794 23:08:34.279763 TX DQ/DQS : PASS
4795 23:08:34.282722 RX DATLAT : PASS
4796 23:08:34.285756 RX DQ/DQS(Engine): PASS
4797 23:08:34.286270 TX OE : NO K
4798 23:08:34.286605 All Pass.
4799 23:08:34.289503
4800 23:08:34.290059 CH 1, Rank 0
4801 23:08:34.292796 SW Impedance : PASS
4802 23:08:34.293305 DUTY Scan : NO K
4803 23:08:34.295560 ZQ Calibration : PASS
4804 23:08:34.298978 Jitter Meter : NO K
4805 23:08:34.299389 CBT Training : PASS
4806 23:08:34.302430 Write leveling : PASS
4807 23:08:34.302838 RX DQS gating : PASS
4808 23:08:34.305803 RX DQ/DQS(RDDQC) : PASS
4809 23:08:34.309132 TX DQ/DQS : PASS
4810 23:08:34.309543 RX DATLAT : PASS
4811 23:08:34.312121 RX DQ/DQS(Engine): PASS
4812 23:08:34.315965 TX OE : NO K
4813 23:08:34.316377 All Pass.
4814 23:08:34.316704
4815 23:08:34.317009 CH 1, Rank 1
4816 23:08:34.319218 SW Impedance : PASS
4817 23:08:34.322499 DUTY Scan : NO K
4818 23:08:34.322962 ZQ Calibration : PASS
4819 23:08:34.325796 Jitter Meter : NO K
4820 23:08:34.329291 CBT Training : PASS
4821 23:08:34.329748 Write leveling : PASS
4822 23:08:34.332506 RX DQS gating : PASS
4823 23:08:34.335757 RX DQ/DQS(RDDQC) : PASS
4824 23:08:34.336175 TX DQ/DQS : PASS
4825 23:08:34.339274 RX DATLAT : PASS
4826 23:08:34.339681 RX DQ/DQS(Engine): PASS
4827 23:08:34.342724 TX OE : NO K
4828 23:08:34.343139 All Pass.
4829 23:08:34.343466
4830 23:08:34.345540 DramC Write-DBI off
4831 23:08:34.348859 PER_BANK_REFRESH: Hybrid Mode
4832 23:08:34.349335 TX_TRACKING: ON
4833 23:08:34.358451 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4834 23:08:34.361786 [FAST_K] Save calibration result to emmc
4835 23:08:34.365004 dramc_set_vcore_voltage set vcore to 662500
4836 23:08:34.368523 Read voltage for 933, 3
4837 23:08:34.368602 Vio18 = 0
4838 23:08:34.372131 Vcore = 662500
4839 23:08:34.372210 Vdram = 0
4840 23:08:34.372273 Vddq = 0
4841 23:08:34.372333 Vmddr = 0
4842 23:08:34.378391 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4843 23:08:34.385563 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4844 23:08:34.385682 MEM_TYPE=3, freq_sel=17
4845 23:08:34.388529 sv_algorithm_assistance_LP4_1600
4846 23:08:34.391425 ============ PULL DRAM RESETB DOWN ============
4847 23:08:34.398386 ========== PULL DRAM RESETB DOWN end =========
4848 23:08:34.401850 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4849 23:08:34.405331 ===================================
4850 23:08:34.408157 LPDDR4 DRAM CONFIGURATION
4851 23:08:34.411487 ===================================
4852 23:08:34.411563 EX_ROW_EN[0] = 0x0
4853 23:08:34.414519 EX_ROW_EN[1] = 0x0
4854 23:08:34.414587 LP4Y_EN = 0x0
4855 23:08:34.417835 WORK_FSP = 0x0
4856 23:08:34.417922 WL = 0x3
4857 23:08:34.421339 RL = 0x3
4858 23:08:34.424334 BL = 0x2
4859 23:08:34.424409 RPST = 0x0
4860 23:08:34.427834 RD_PRE = 0x0
4861 23:08:34.427907 WR_PRE = 0x1
4862 23:08:34.431352 WR_PST = 0x0
4863 23:08:34.431421 DBI_WR = 0x0
4864 23:08:34.434433 DBI_RD = 0x0
4865 23:08:34.434528 OTF = 0x1
4866 23:08:34.437882 ===================================
4867 23:08:34.441440 ===================================
4868 23:08:34.445002 ANA top config
4869 23:08:34.448015 ===================================
4870 23:08:34.448116 DLL_ASYNC_EN = 0
4871 23:08:34.451116 ALL_SLAVE_EN = 1
4872 23:08:34.454620 NEW_RANK_MODE = 1
4873 23:08:34.457512 DLL_IDLE_MODE = 1
4874 23:08:34.457656 LP45_APHY_COMB_EN = 1
4875 23:08:34.461092 TX_ODT_DIS = 1
4876 23:08:34.464595 NEW_8X_MODE = 1
4877 23:08:34.467780 ===================================
4878 23:08:34.471219 ===================================
4879 23:08:34.474723 data_rate = 1866
4880 23:08:34.477825 CKR = 1
4881 23:08:34.477933 DQ_P2S_RATIO = 8
4882 23:08:34.481158 ===================================
4883 23:08:34.484665 CA_P2S_RATIO = 8
4884 23:08:34.487729 DQ_CA_OPEN = 0
4885 23:08:34.491270 DQ_SEMI_OPEN = 0
4886 23:08:34.494381 CA_SEMI_OPEN = 0
4887 23:08:34.497645 CA_FULL_RATE = 0
4888 23:08:34.497734 DQ_CKDIV4_EN = 1
4889 23:08:34.501176 CA_CKDIV4_EN = 1
4890 23:08:34.504251 CA_PREDIV_EN = 0
4891 23:08:34.507606 PH8_DLY = 0
4892 23:08:34.511233 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4893 23:08:34.514260 DQ_AAMCK_DIV = 4
4894 23:08:34.514340 CA_AAMCK_DIV = 4
4895 23:08:34.517887 CA_ADMCK_DIV = 4
4896 23:08:34.520866 DQ_TRACK_CA_EN = 0
4897 23:08:34.524316 CA_PICK = 933
4898 23:08:34.528337 CA_MCKIO = 933
4899 23:08:34.531184 MCKIO_SEMI = 0
4900 23:08:34.534624 PLL_FREQ = 3732
4901 23:08:34.534713 DQ_UI_PI_RATIO = 32
4902 23:08:34.537466 CA_UI_PI_RATIO = 0
4903 23:08:34.540864 ===================================
4904 23:08:34.544163 ===================================
4905 23:08:34.547857 memory_type:LPDDR4
4906 23:08:34.550903 GP_NUM : 10
4907 23:08:34.550988 SRAM_EN : 1
4908 23:08:34.554039 MD32_EN : 0
4909 23:08:34.557520 ===================================
4910 23:08:34.561085 [ANA_INIT] >>>>>>>>>>>>>>
4911 23:08:34.561178 <<<<<< [CONFIGURE PHASE]: ANA_TX
4912 23:08:34.564451 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4913 23:08:34.567896 ===================================
4914 23:08:34.570923 data_rate = 1866,PCW = 0X8f00
4915 23:08:34.574499 ===================================
4916 23:08:34.577770 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4917 23:08:34.584390 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4918 23:08:34.591276 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4919 23:08:34.594396 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4920 23:08:34.597516 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4921 23:08:34.600929 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4922 23:08:34.604222 [ANA_INIT] flow start
4923 23:08:34.604302 [ANA_INIT] PLL >>>>>>>>
4924 23:08:34.607266 [ANA_INIT] PLL <<<<<<<<
4925 23:08:34.610631 [ANA_INIT] MIDPI >>>>>>>>
4926 23:08:34.610745 [ANA_INIT] MIDPI <<<<<<<<
4927 23:08:34.614283 [ANA_INIT] DLL >>>>>>>>
4928 23:08:34.617620 [ANA_INIT] flow end
4929 23:08:34.620913 ============ LP4 DIFF to SE enter ============
4930 23:08:34.624090 ============ LP4 DIFF to SE exit ============
4931 23:08:34.627592 [ANA_INIT] <<<<<<<<<<<<<
4932 23:08:34.630759 [Flow] Enable top DCM control >>>>>
4933 23:08:34.634227 [Flow] Enable top DCM control <<<<<
4934 23:08:34.637247 Enable DLL master slave shuffle
4935 23:08:34.640910 ==============================================================
4936 23:08:34.643909 Gating Mode config
4937 23:08:34.650766 ==============================================================
4938 23:08:34.650869 Config description:
4939 23:08:34.661152 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4940 23:08:34.667251 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4941 23:08:34.674315 SELPH_MODE 0: By rank 1: By Phase
4942 23:08:34.677118 ==============================================================
4943 23:08:34.680733 GAT_TRACK_EN = 1
4944 23:08:34.683909 RX_GATING_MODE = 2
4945 23:08:34.687566 RX_GATING_TRACK_MODE = 2
4946 23:08:34.690773 SELPH_MODE = 1
4947 23:08:34.693581 PICG_EARLY_EN = 1
4948 23:08:34.697043 VALID_LAT_VALUE = 1
4949 23:08:34.700771 ==============================================================
4950 23:08:34.703719 Enter into Gating configuration >>>>
4951 23:08:34.707104 Exit from Gating configuration <<<<
4952 23:08:34.710264 Enter into DVFS_PRE_config >>>>>
4953 23:08:34.723713 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4954 23:08:34.723804 Exit from DVFS_PRE_config <<<<<
4955 23:08:34.726880 Enter into PICG configuration >>>>
4956 23:08:34.730656 Exit from PICG configuration <<<<
4957 23:08:34.733595 [RX_INPUT] configuration >>>>>
4958 23:08:34.737224 [RX_INPUT] configuration <<<<<
4959 23:08:34.743962 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4960 23:08:34.747052 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4961 23:08:34.753710 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4962 23:08:34.760187 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4963 23:08:34.767169 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4964 23:08:34.773293 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4965 23:08:34.776996 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4966 23:08:34.780159 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4967 23:08:34.783485 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4968 23:08:34.790177 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4969 23:08:34.793585 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4970 23:08:34.796866 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4971 23:08:34.800387 ===================================
4972 23:08:34.803447 LPDDR4 DRAM CONFIGURATION
4973 23:08:34.807313 ===================================
4974 23:08:34.807394 EX_ROW_EN[0] = 0x0
4975 23:08:34.809855 EX_ROW_EN[1] = 0x0
4976 23:08:34.813285 LP4Y_EN = 0x0
4977 23:08:34.813411 WORK_FSP = 0x0
4978 23:08:34.817246 WL = 0x3
4979 23:08:34.817351 RL = 0x3
4980 23:08:34.820033 BL = 0x2
4981 23:08:34.820112 RPST = 0x0
4982 23:08:34.823821 RD_PRE = 0x0
4983 23:08:34.823901 WR_PRE = 0x1
4984 23:08:34.826660 WR_PST = 0x0
4985 23:08:34.826739 DBI_WR = 0x0
4986 23:08:34.830052 DBI_RD = 0x0
4987 23:08:34.830181 OTF = 0x1
4988 23:08:34.833392 ===================================
4989 23:08:34.836825 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4990 23:08:34.843666 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4991 23:08:34.846785 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4992 23:08:34.850492 ===================================
4993 23:08:34.853559 LPDDR4 DRAM CONFIGURATION
4994 23:08:34.856738 ===================================
4995 23:08:34.856859 EX_ROW_EN[0] = 0x10
4996 23:08:34.860200 EX_ROW_EN[1] = 0x0
4997 23:08:34.860306 LP4Y_EN = 0x0
4998 23:08:34.863186 WORK_FSP = 0x0
4999 23:08:34.866617 WL = 0x3
5000 23:08:34.866697 RL = 0x3
5001 23:08:34.869811 BL = 0x2
5002 23:08:34.869895 RPST = 0x0
5003 23:08:34.873500 RD_PRE = 0x0
5004 23:08:34.873636 WR_PRE = 0x1
5005 23:08:34.876499 WR_PST = 0x0
5006 23:08:34.876603 DBI_WR = 0x0
5007 23:08:34.880472 DBI_RD = 0x0
5008 23:08:34.880577 OTF = 0x1
5009 23:08:34.883113 ===================================
5010 23:08:34.889572 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5011 23:08:34.894004 nWR fixed to 30
5012 23:08:34.897117 [ModeRegInit_LP4] CH0 RK0
5013 23:08:34.897225 [ModeRegInit_LP4] CH0 RK1
5014 23:08:34.900760 [ModeRegInit_LP4] CH1 RK0
5015 23:08:34.903679 [ModeRegInit_LP4] CH1 RK1
5016 23:08:34.903783 match AC timing 9
5017 23:08:34.910699 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5018 23:08:34.913670 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5019 23:08:34.916920 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5020 23:08:34.923673 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5021 23:08:34.926943 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5022 23:08:34.927016 ==
5023 23:08:34.930151 Dram Type= 6, Freq= 0, CH_0, rank 0
5024 23:08:34.933765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5025 23:08:34.933841 ==
5026 23:08:34.940160 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5027 23:08:34.946912 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5028 23:08:34.949937 [CA 0] Center 37 (7~68) winsize 62
5029 23:08:34.953705 [CA 1] Center 37 (7~68) winsize 62
5030 23:08:34.957176 [CA 2] Center 34 (4~65) winsize 62
5031 23:08:34.960259 [CA 3] Center 33 (3~64) winsize 62
5032 23:08:34.963340 [CA 4] Center 33 (3~64) winsize 62
5033 23:08:34.966660 [CA 5] Center 32 (2~62) winsize 61
5034 23:08:34.966735
5035 23:08:34.970349 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5036 23:08:34.970419
5037 23:08:34.973270 [CATrainingPosCal] consider 1 rank data
5038 23:08:34.977466 u2DelayCellTimex100 = 270/100 ps
5039 23:08:34.980198 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5040 23:08:34.983413 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5041 23:08:34.986824 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5042 23:08:34.990328 CA3 delay=33 (3~64),Diff = 1 PI (6 cell)
5043 23:08:34.993183 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5044 23:08:34.999925 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5045 23:08:35.000010
5046 23:08:35.003532 CA PerBit enable=1, Macro0, CA PI delay=32
5047 23:08:35.003638
5048 23:08:35.006963 [CBTSetCACLKResult] CA Dly = 32
5049 23:08:35.007043 CS Dly: 5 (0~36)
5050 23:08:35.007113 ==
5051 23:08:35.009770 Dram Type= 6, Freq= 0, CH_0, rank 1
5052 23:08:35.013381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5053 23:08:35.016919 ==
5054 23:08:35.020147 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5055 23:08:35.026740 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5056 23:08:35.030209 [CA 0] Center 37 (6~68) winsize 63
5057 23:08:35.033420 [CA 1] Center 37 (6~68) winsize 63
5058 23:08:35.036458 [CA 2] Center 34 (4~65) winsize 62
5059 23:08:35.039655 [CA 3] Center 34 (3~65) winsize 63
5060 23:08:35.043253 [CA 4] Center 33 (3~63) winsize 61
5061 23:08:35.046352 [CA 5] Center 32 (2~63) winsize 62
5062 23:08:35.046454
5063 23:08:35.049162 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5064 23:08:35.049271
5065 23:08:35.053245 [CATrainingPosCal] consider 2 rank data
5066 23:08:35.056518 u2DelayCellTimex100 = 270/100 ps
5067 23:08:35.060025 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5068 23:08:35.062949 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5069 23:08:35.066381 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5070 23:08:35.069395 CA3 delay=33 (3~64),Diff = 1 PI (6 cell)
5071 23:08:35.075984 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5072 23:08:35.079597 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5073 23:08:35.079680
5074 23:08:35.082795 CA PerBit enable=1, Macro0, CA PI delay=32
5075 23:08:35.082876
5076 23:08:35.086229 [CBTSetCACLKResult] CA Dly = 32
5077 23:08:35.086332 CS Dly: 5 (0~37)
5078 23:08:35.086398
5079 23:08:35.089264 ----->DramcWriteLeveling(PI) begin...
5080 23:08:35.089367 ==
5081 23:08:35.092967 Dram Type= 6, Freq= 0, CH_0, rank 0
5082 23:08:35.099558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5083 23:08:35.099643 ==
5084 23:08:35.102980 Write leveling (Byte 0): 33 => 33
5085 23:08:35.106465 Write leveling (Byte 1): 29 => 29
5086 23:08:35.106579 DramcWriteLeveling(PI) end<-----
5087 23:08:35.106673
5088 23:08:35.109202 ==
5089 23:08:35.112535 Dram Type= 6, Freq= 0, CH_0, rank 0
5090 23:08:35.116410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5091 23:08:35.116525 ==
5092 23:08:35.119732 [Gating] SW mode calibration
5093 23:08:35.126179 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5094 23:08:35.129104 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5095 23:08:35.135840 0 14 0 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
5096 23:08:35.139516 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5097 23:08:35.142459 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5098 23:08:35.149310 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5099 23:08:35.152347 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5100 23:08:35.155780 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5101 23:08:35.162442 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5102 23:08:35.165771 0 14 28 | B1->B0 | 3434 2525 | 1 0 | (1 0) (1 0)
5103 23:08:35.168951 0 15 0 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
5104 23:08:35.175689 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5105 23:08:35.178980 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5106 23:08:35.182281 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5107 23:08:35.188700 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5108 23:08:35.192158 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5109 23:08:35.195647 0 15 24 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
5110 23:08:35.201991 0 15 28 | B1->B0 | 2323 3e3e | 0 1 | (0 0) (0 0)
5111 23:08:35.205571 1 0 0 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
5112 23:08:35.208559 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5113 23:08:35.215408 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5114 23:08:35.218680 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5115 23:08:35.221949 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5116 23:08:35.228555 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5117 23:08:35.232186 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5118 23:08:35.235997 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5119 23:08:35.241832 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5120 23:08:35.246153 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5121 23:08:35.248530 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5122 23:08:35.252232 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5123 23:08:35.258609 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5124 23:08:35.261831 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5125 23:08:35.265475 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5126 23:08:35.272019 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 23:08:35.275091 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 23:08:35.278181 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 23:08:35.285303 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 23:08:35.288381 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 23:08:35.291818 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 23:08:35.298232 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 23:08:35.302059 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5134 23:08:35.305185 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5135 23:08:35.308885 Total UI for P1: 0, mck2ui 16
5136 23:08:35.311505 best dqsien dly found for B0: ( 1, 2, 24)
5137 23:08:35.318432 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5138 23:08:35.321545 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5139 23:08:35.325412 Total UI for P1: 0, mck2ui 16
5140 23:08:35.328689 best dqsien dly found for B1: ( 1, 2, 30)
5141 23:08:35.331869 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5142 23:08:35.334763 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5143 23:08:35.334832
5144 23:08:35.338730 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5145 23:08:35.341601 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5146 23:08:35.345163 [Gating] SW calibration Done
5147 23:08:35.345242 ==
5148 23:08:35.348583 Dram Type= 6, Freq= 0, CH_0, rank 0
5149 23:08:35.351480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5150 23:08:35.355337 ==
5151 23:08:35.355418 RX Vref Scan: 0
5152 23:08:35.355496
5153 23:08:35.358825 RX Vref 0 -> 0, step: 1
5154 23:08:35.358904
5155 23:08:35.358970 RX Delay -80 -> 252, step: 8
5156 23:08:35.365103 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5157 23:08:35.368438 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5158 23:08:35.371850 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5159 23:08:35.375390 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5160 23:08:35.378855 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5161 23:08:35.382026 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5162 23:08:35.388176 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5163 23:08:35.391797 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5164 23:08:35.395231 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5165 23:08:35.398265 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5166 23:08:35.401786 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5167 23:08:35.408736 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5168 23:08:35.411549 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5169 23:08:35.414746 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5170 23:08:35.418567 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5171 23:08:35.421920 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5172 23:08:35.422002 ==
5173 23:08:35.424877 Dram Type= 6, Freq= 0, CH_0, rank 0
5174 23:08:35.431899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5175 23:08:35.431981 ==
5176 23:08:35.432046 DQS Delay:
5177 23:08:35.432144 DQS0 = 0, DQS1 = 0
5178 23:08:35.434639 DQM Delay:
5179 23:08:35.434720 DQM0 = 103, DQM1 = 94
5180 23:08:35.438113 DQ Delay:
5181 23:08:35.441527 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5182 23:08:35.444715 DQ4 =107, DQ5 =91, DQ6 =111, DQ7 =111
5183 23:08:35.448126 DQ8 =87, DQ9 =83, DQ10 =95, DQ11 =91
5184 23:08:35.451374 DQ12 =99, DQ13 =103, DQ14 =99, DQ15 =99
5185 23:08:35.451490
5186 23:08:35.451557
5187 23:08:35.451617 ==
5188 23:08:35.454920 Dram Type= 6, Freq= 0, CH_0, rank 0
5189 23:08:35.457887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5190 23:08:35.457990 ==
5191 23:08:35.458088
5192 23:08:35.458179
5193 23:08:35.461553 TX Vref Scan disable
5194 23:08:35.465115 == TX Byte 0 ==
5195 23:08:35.468183 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5196 23:08:35.471478 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5197 23:08:35.475207 == TX Byte 1 ==
5198 23:08:35.478386 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5199 23:08:35.481921 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5200 23:08:35.482002 ==
5201 23:08:35.484682 Dram Type= 6, Freq= 0, CH_0, rank 0
5202 23:08:35.488326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5203 23:08:35.488407 ==
5204 23:08:35.491648
5205 23:08:35.491728
5206 23:08:35.491792 TX Vref Scan disable
5207 23:08:35.494771 == TX Byte 0 ==
5208 23:08:35.498396 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5209 23:08:35.501971 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5210 23:08:35.504992 == TX Byte 1 ==
5211 23:08:35.508503 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5212 23:08:35.515061 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5213 23:08:35.515143
5214 23:08:35.515206 [DATLAT]
5215 23:08:35.515267 Freq=933, CH0 RK0
5216 23:08:35.515327
5217 23:08:35.518331 DATLAT Default: 0xd
5218 23:08:35.518411 0, 0xFFFF, sum = 0
5219 23:08:35.521846 1, 0xFFFF, sum = 0
5220 23:08:35.521961 2, 0xFFFF, sum = 0
5221 23:08:35.524734 3, 0xFFFF, sum = 0
5222 23:08:35.524816 4, 0xFFFF, sum = 0
5223 23:08:35.528233 5, 0xFFFF, sum = 0
5224 23:08:35.531650 6, 0xFFFF, sum = 0
5225 23:08:35.531732 7, 0xFFFF, sum = 0
5226 23:08:35.534856 8, 0xFFFF, sum = 0
5227 23:08:35.534939 9, 0xFFFF, sum = 0
5228 23:08:35.538412 10, 0x0, sum = 1
5229 23:08:35.538494 11, 0x0, sum = 2
5230 23:08:35.538558 12, 0x0, sum = 3
5231 23:08:35.541379 13, 0x0, sum = 4
5232 23:08:35.541461 best_step = 11
5233 23:08:35.541525
5234 23:08:35.544757 ==
5235 23:08:35.547738 Dram Type= 6, Freq= 0, CH_0, rank 0
5236 23:08:35.551339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5237 23:08:35.551421 ==
5238 23:08:35.551486 RX Vref Scan: 1
5239 23:08:35.551545
5240 23:08:35.554541 RX Vref 0 -> 0, step: 1
5241 23:08:35.554622
5242 23:08:35.557890 RX Delay -53 -> 252, step: 4
5243 23:08:35.557970
5244 23:08:35.561040 Set Vref, RX VrefLevel [Byte0]: 53
5245 23:08:35.564571 [Byte1]: 46
5246 23:08:35.564652
5247 23:08:35.568107 Final RX Vref Byte 0 = 53 to rank0
5248 23:08:35.571152 Final RX Vref Byte 1 = 46 to rank0
5249 23:08:35.574694 Final RX Vref Byte 0 = 53 to rank1
5250 23:08:35.577788 Final RX Vref Byte 1 = 46 to rank1==
5251 23:08:35.581155 Dram Type= 6, Freq= 0, CH_0, rank 0
5252 23:08:35.584541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5253 23:08:35.584623 ==
5254 23:08:35.587944 DQS Delay:
5255 23:08:35.588029 DQS0 = 0, DQS1 = 0
5256 23:08:35.591235 DQM Delay:
5257 23:08:35.591327 DQM0 = 104, DQM1 = 94
5258 23:08:35.591401 DQ Delay:
5259 23:08:35.597916 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =102
5260 23:08:35.601335 DQ4 =104, DQ5 =96, DQ6 =112, DQ7 =110
5261 23:08:35.604322 DQ8 =84, DQ9 =86, DQ10 =96, DQ11 =88
5262 23:08:35.607583 DQ12 =98, DQ13 =98, DQ14 =108, DQ15 =100
5263 23:08:35.607687
5264 23:08:35.607777
5265 23:08:35.614363 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e25, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 407 ps
5266 23:08:35.617864 CH0 RK0: MR19=505, MR18=2E25
5267 23:08:35.624508 CH0_RK0: MR19=0x505, MR18=0x2E25, DQSOSC=407, MR23=63, INC=65, DEC=43
5268 23:08:35.624590
5269 23:08:35.627737 ----->DramcWriteLeveling(PI) begin...
5270 23:08:35.627819 ==
5271 23:08:35.630963 Dram Type= 6, Freq= 0, CH_0, rank 1
5272 23:08:35.634129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5273 23:08:35.634210 ==
5274 23:08:35.637460 Write leveling (Byte 0): 33 => 33
5275 23:08:35.640690 Write leveling (Byte 1): 27 => 27
5276 23:08:35.643964 DramcWriteLeveling(PI) end<-----
5277 23:08:35.644044
5278 23:08:35.644109 ==
5279 23:08:35.647285 Dram Type= 6, Freq= 0, CH_0, rank 1
5280 23:08:35.650427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5281 23:08:35.654230 ==
5282 23:08:35.654315 [Gating] SW mode calibration
5283 23:08:35.660895 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5284 23:08:35.667525 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5285 23:08:35.670746 0 14 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (0 0)
5286 23:08:35.677376 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5287 23:08:35.680383 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5288 23:08:35.683880 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5289 23:08:35.690242 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5290 23:08:35.693751 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5291 23:08:35.697339 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5292 23:08:35.703968 0 14 28 | B1->B0 | 2c2c 2d2d | 1 0 | (1 1) (0 0)
5293 23:08:35.706787 0 15 0 | B1->B0 | 2424 2828 | 1 0 | (1 0) (1 0)
5294 23:08:35.710152 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5295 23:08:35.717066 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5296 23:08:35.719998 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5297 23:08:35.723823 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5298 23:08:35.730358 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5299 23:08:35.733311 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5300 23:08:35.737023 0 15 28 | B1->B0 | 3b3b 3a3a | 0 1 | (0 0) (0 0)
5301 23:08:35.743638 1 0 0 | B1->B0 | 4646 4040 | 0 1 | (0 0) (0 0)
5302 23:08:35.746741 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5303 23:08:35.750688 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5304 23:08:35.756754 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5305 23:08:35.760190 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5306 23:08:35.763615 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5307 23:08:35.766623 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5308 23:08:35.773351 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5309 23:08:35.776598 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5310 23:08:35.779701 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5311 23:08:35.786629 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5312 23:08:35.790151 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5313 23:08:35.793151 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5314 23:08:35.799658 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5315 23:08:35.803010 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5316 23:08:35.806558 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5317 23:08:35.813033 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5318 23:08:35.817104 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5319 23:08:35.819940 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5320 23:08:35.826724 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 23:08:35.829608 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 23:08:35.833439 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 23:08:35.839968 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5324 23:08:35.843013 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5325 23:08:35.846724 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5326 23:08:35.849898 Total UI for P1: 0, mck2ui 16
5327 23:08:35.852895 best dqsien dly found for B1: ( 1, 2, 26)
5328 23:08:35.860195 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5329 23:08:35.860286 Total UI for P1: 0, mck2ui 16
5330 23:08:35.866563 best dqsien dly found for B0: ( 1, 2, 28)
5331 23:08:35.869590 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5332 23:08:35.873062 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5333 23:08:35.873180
5334 23:08:35.876199 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5335 23:08:35.879596 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5336 23:08:35.883015 [Gating] SW calibration Done
5337 23:08:35.883095 ==
5338 23:08:35.886008 Dram Type= 6, Freq= 0, CH_0, rank 1
5339 23:08:35.889851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5340 23:08:35.889930 ==
5341 23:08:35.892770 RX Vref Scan: 0
5342 23:08:35.892848
5343 23:08:35.892910 RX Vref 0 -> 0, step: 1
5344 23:08:35.892969
5345 23:08:35.896306 RX Delay -80 -> 252, step: 8
5346 23:08:35.899569 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5347 23:08:35.906066 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5348 23:08:35.909470 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5349 23:08:35.912698 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5350 23:08:35.916410 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5351 23:08:35.919968 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5352 23:08:35.922885 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5353 23:08:35.929840 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5354 23:08:35.933184 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5355 23:08:35.936272 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5356 23:08:35.939202 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5357 23:08:35.942601 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5358 23:08:35.946159 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5359 23:08:35.952908 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5360 23:08:35.956261 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5361 23:08:35.959455 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5362 23:08:35.959536 ==
5363 23:08:35.962977 Dram Type= 6, Freq= 0, CH_0, rank 1
5364 23:08:35.965918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5365 23:08:35.966000 ==
5366 23:08:35.969448 DQS Delay:
5367 23:08:35.969528 DQS0 = 0, DQS1 = 0
5368 23:08:35.969616 DQM Delay:
5369 23:08:35.972468 DQM0 = 105, DQM1 = 93
5370 23:08:35.972548 DQ Delay:
5371 23:08:35.976235 DQ0 =103, DQ1 =107, DQ2 =103, DQ3 =99
5372 23:08:35.979315 DQ4 =107, DQ5 =95, DQ6 =111, DQ7 =115
5373 23:08:35.982786 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =87
5374 23:08:35.985865 DQ12 =95, DQ13 =99, DQ14 =99, DQ15 =99
5375 23:08:35.985945
5376 23:08:35.989310
5377 23:08:35.989390 ==
5378 23:08:35.992226 Dram Type= 6, Freq= 0, CH_0, rank 1
5379 23:08:35.995844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5380 23:08:35.995950 ==
5381 23:08:35.996049
5382 23:08:35.996144
5383 23:08:35.999281 TX Vref Scan disable
5384 23:08:35.999363 == TX Byte 0 ==
5385 23:08:36.005888 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5386 23:08:36.008880 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5387 23:08:36.008992 == TX Byte 1 ==
5388 23:08:36.015556 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5389 23:08:36.019585 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5390 23:08:36.019667 ==
5391 23:08:36.023065 Dram Type= 6, Freq= 0, CH_0, rank 1
5392 23:08:36.026119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5393 23:08:36.026201 ==
5394 23:08:36.026275
5395 23:08:36.026372
5396 23:08:36.029428 TX Vref Scan disable
5397 23:08:36.032740 == TX Byte 0 ==
5398 23:08:36.036198 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5399 23:08:36.039080 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5400 23:08:36.042302 == TX Byte 1 ==
5401 23:08:36.045838 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5402 23:08:36.048948 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5403 23:08:36.049028
5404 23:08:36.052593 [DATLAT]
5405 23:08:36.052673 Freq=933, CH0 RK1
5406 23:08:36.052738
5407 23:08:36.055904 DATLAT Default: 0xb
5408 23:08:36.055988 0, 0xFFFF, sum = 0
5409 23:08:36.058969 1, 0xFFFF, sum = 0
5410 23:08:36.059057 2, 0xFFFF, sum = 0
5411 23:08:36.062759 3, 0xFFFF, sum = 0
5412 23:08:36.062931 4, 0xFFFF, sum = 0
5413 23:08:36.065641 5, 0xFFFF, sum = 0
5414 23:08:36.065775 6, 0xFFFF, sum = 0
5415 23:08:36.069285 7, 0xFFFF, sum = 0
5416 23:08:36.069465 8, 0xFFFF, sum = 0
5417 23:08:36.072576 9, 0xFFFF, sum = 0
5418 23:08:36.072761 10, 0x0, sum = 1
5419 23:08:36.075294 11, 0x0, sum = 2
5420 23:08:36.075450 12, 0x0, sum = 3
5421 23:08:36.079464 13, 0x0, sum = 4
5422 23:08:36.079895 best_step = 11
5423 23:08:36.080324
5424 23:08:36.080731 ==
5425 23:08:36.082813 Dram Type= 6, Freq= 0, CH_0, rank 1
5426 23:08:36.089474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5427 23:08:36.090023 ==
5428 23:08:36.090460 RX Vref Scan: 0
5429 23:08:36.090869
5430 23:08:36.092206 RX Vref 0 -> 0, step: 1
5431 23:08:36.092631
5432 23:08:36.095990 RX Delay -45 -> 252, step: 4
5433 23:08:36.099313 iDelay=199, Bit 0, Center 100 (11 ~ 190) 180
5434 23:08:36.102610 iDelay=199, Bit 1, Center 108 (23 ~ 194) 172
5435 23:08:36.108733 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5436 23:08:36.112604 iDelay=199, Bit 3, Center 100 (11 ~ 190) 180
5437 23:08:36.115434 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5438 23:08:36.118902 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5439 23:08:36.122366 iDelay=199, Bit 6, Center 112 (31 ~ 194) 164
5440 23:08:36.128577 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5441 23:08:36.132387 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5442 23:08:36.135381 iDelay=199, Bit 9, Center 82 (-1 ~ 166) 168
5443 23:08:36.138771 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5444 23:08:36.141951 iDelay=199, Bit 11, Center 88 (7 ~ 170) 164
5445 23:08:36.145771 iDelay=199, Bit 12, Center 100 (19 ~ 182) 164
5446 23:08:36.151987 iDelay=199, Bit 13, Center 100 (19 ~ 182) 164
5447 23:08:36.155273 iDelay=199, Bit 14, Center 102 (19 ~ 186) 168
5448 23:08:36.158630 iDelay=199, Bit 15, Center 100 (15 ~ 186) 172
5449 23:08:36.159092 ==
5450 23:08:36.162377 Dram Type= 6, Freq= 0, CH_0, rank 1
5451 23:08:36.165513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5452 23:08:36.168896 ==
5453 23:08:36.169473 DQS Delay:
5454 23:08:36.169887 DQS0 = 0, DQS1 = 0
5455 23:08:36.171958 DQM Delay:
5456 23:08:36.172371 DQM0 = 104, DQM1 = 94
5457 23:08:36.175640 DQ Delay:
5458 23:08:36.179228 DQ0 =100, DQ1 =108, DQ2 =102, DQ3 =100
5459 23:08:36.181976 DQ4 =106, DQ5 =98, DQ6 =112, DQ7 =112
5460 23:08:36.185405 DQ8 =86, DQ9 =82, DQ10 =94, DQ11 =88
5461 23:08:36.188752 DQ12 =100, DQ13 =100, DQ14 =102, DQ15 =100
5462 23:08:36.189170
5463 23:08:36.189505
5464 23:08:36.195754 [DQSOSCAuto] RK1, (LSB)MR18= 0x2700, (MSB)MR19= 0x505, tDQSOscB0 = 422 ps tDQSOscB1 = 409 ps
5465 23:08:36.198609 CH0 RK1: MR19=505, MR18=2700
5466 23:08:36.205157 CH0_RK1: MR19=0x505, MR18=0x2700, DQSOSC=409, MR23=63, INC=64, DEC=43
5467 23:08:36.208488 [RxdqsGatingPostProcess] freq 933
5468 23:08:36.212218 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5469 23:08:36.215504 best DQS0 dly(2T, 0.5T) = (0, 10)
5470 23:08:36.218906 best DQS1 dly(2T, 0.5T) = (0, 10)
5471 23:08:36.221942 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5472 23:08:36.225310 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5473 23:08:36.228740 best DQS0 dly(2T, 0.5T) = (0, 10)
5474 23:08:36.232107 best DQS1 dly(2T, 0.5T) = (0, 10)
5475 23:08:36.235161 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5476 23:08:36.238758 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5477 23:08:36.241858 Pre-setting of DQS Precalculation
5478 23:08:36.245378 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5479 23:08:36.248339 ==
5480 23:08:36.248750 Dram Type= 6, Freq= 0, CH_1, rank 0
5481 23:08:36.255157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5482 23:08:36.255575 ==
5483 23:08:36.258675 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5484 23:08:36.265188 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5485 23:08:36.268680 [CA 0] Center 36 (6~67) winsize 62
5486 23:08:36.271812 [CA 1] Center 37 (7~67) winsize 61
5487 23:08:36.275455 [CA 2] Center 34 (4~65) winsize 62
5488 23:08:36.279059 [CA 3] Center 34 (4~65) winsize 62
5489 23:08:36.281893 [CA 4] Center 34 (4~65) winsize 62
5490 23:08:36.285407 [CA 5] Center 33 (3~64) winsize 62
5491 23:08:36.285862
5492 23:08:36.288589 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5493 23:08:36.289004
5494 23:08:36.292146 [CATrainingPosCal] consider 1 rank data
5495 23:08:36.295206 u2DelayCellTimex100 = 270/100 ps
5496 23:08:36.298481 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5497 23:08:36.305896 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5498 23:08:36.308561 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5499 23:08:36.312112 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5500 23:08:36.315000 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5501 23:08:36.318607 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5502 23:08:36.319024
5503 23:08:36.321712 CA PerBit enable=1, Macro0, CA PI delay=33
5504 23:08:36.322128
5505 23:08:36.324875 [CBTSetCACLKResult] CA Dly = 33
5506 23:08:36.325228 CS Dly: 6 (0~37)
5507 23:08:36.328623 ==
5508 23:08:36.332268 Dram Type= 6, Freq= 0, CH_1, rank 1
5509 23:08:36.335214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5510 23:08:36.335631 ==
5511 23:08:36.338125 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5512 23:08:36.345199 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5513 23:08:36.348695 [CA 0] Center 36 (6~67) winsize 62
5514 23:08:36.352012 [CA 1] Center 37 (6~68) winsize 63
5515 23:08:36.355455 [CA 2] Center 35 (5~66) winsize 62
5516 23:08:36.358586 [CA 3] Center 34 (4~65) winsize 62
5517 23:08:36.361870 [CA 4] Center 34 (4~65) winsize 62
5518 23:08:36.365237 [CA 5] Center 34 (4~64) winsize 61
5519 23:08:36.365688
5520 23:08:36.368411 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5521 23:08:36.369008
5522 23:08:36.371614 [CATrainingPosCal] consider 2 rank data
5523 23:08:36.375135 u2DelayCellTimex100 = 270/100 ps
5524 23:08:36.378692 CA0 delay=36 (6~67),Diff = 2 PI (12 cell)
5525 23:08:36.382029 CA1 delay=37 (7~67),Diff = 3 PI (18 cell)
5526 23:08:36.388231 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5527 23:08:36.391760 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5528 23:08:36.395355 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5529 23:08:36.398393 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5530 23:08:36.398813
5531 23:08:36.401662 CA PerBit enable=1, Macro0, CA PI delay=34
5532 23:08:36.402090
5533 23:08:36.405475 [CBTSetCACLKResult] CA Dly = 34
5534 23:08:36.405946 CS Dly: 7 (0~40)
5535 23:08:36.406289
5536 23:08:36.408890 ----->DramcWriteLeveling(PI) begin...
5537 23:08:36.411920 ==
5538 23:08:36.415331 Dram Type= 6, Freq= 0, CH_1, rank 0
5539 23:08:36.418182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5540 23:08:36.418741 ==
5541 23:08:36.421656 Write leveling (Byte 0): 26 => 26
5542 23:08:36.424971 Write leveling (Byte 1): 28 => 28
5543 23:08:36.427961 DramcWriteLeveling(PI) end<-----
5544 23:08:36.428368
5545 23:08:36.428736 ==
5546 23:08:36.431293 Dram Type= 6, Freq= 0, CH_1, rank 0
5547 23:08:36.434630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5548 23:08:36.435131 ==
5549 23:08:36.438286 [Gating] SW mode calibration
5550 23:08:36.444769 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5551 23:08:36.451632 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5552 23:08:36.454855 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5553 23:08:36.457724 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5554 23:08:36.464101 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5555 23:08:36.467716 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5556 23:08:36.471253 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5557 23:08:36.477897 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5558 23:08:36.480928 0 14 24 | B1->B0 | 3434 2e2e | 1 1 | (1 0) (1 0)
5559 23:08:36.484594 0 14 28 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5560 23:08:36.490972 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5561 23:08:36.494174 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5562 23:08:36.497844 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5563 23:08:36.504096 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5564 23:08:36.507382 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5565 23:08:36.511029 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5566 23:08:36.517520 0 15 24 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
5567 23:08:36.520629 0 15 28 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
5568 23:08:36.524037 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5569 23:08:36.530253 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5570 23:08:36.533733 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5571 23:08:36.536638 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5572 23:08:36.543636 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5573 23:08:36.546774 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5574 23:08:36.550375 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5575 23:08:36.557333 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5576 23:08:36.560133 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5577 23:08:36.563220 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5578 23:08:36.570154 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5579 23:08:36.573530 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5580 23:08:36.576777 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5581 23:08:36.583085 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5582 23:08:36.586808 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 23:08:36.589782 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 23:08:36.596371 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 23:08:36.599754 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 23:08:36.602745 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 23:08:36.609693 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 23:08:36.612581 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 23:08:36.616131 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5590 23:08:36.622799 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5591 23:08:36.625952 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5592 23:08:36.628863 Total UI for P1: 0, mck2ui 16
5593 23:08:36.632415 best dqsien dly found for B0: ( 1, 2, 24)
5594 23:08:36.635728 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5595 23:08:36.638853 Total UI for P1: 0, mck2ui 16
5596 23:08:36.642286 best dqsien dly found for B1: ( 1, 2, 24)
5597 23:08:36.645688 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5598 23:08:36.648849 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5599 23:08:36.648929
5600 23:08:36.652016 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5601 23:08:36.659110 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5602 23:08:36.659192 [Gating] SW calibration Done
5603 23:08:36.659256 ==
5604 23:08:36.661983 Dram Type= 6, Freq= 0, CH_1, rank 0
5605 23:08:36.668525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5606 23:08:36.668635 ==
5607 23:08:36.668727 RX Vref Scan: 0
5608 23:08:36.668815
5609 23:08:36.672286 RX Vref 0 -> 0, step: 1
5610 23:08:36.672376
5611 23:08:36.675202 RX Delay -80 -> 252, step: 8
5612 23:08:36.678555 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5613 23:08:36.682111 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5614 23:08:36.685078 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5615 23:08:36.692080 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5616 23:08:36.695585 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5617 23:08:36.698328 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5618 23:08:36.701525 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5619 23:08:36.705221 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5620 23:08:36.708599 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5621 23:08:36.712443 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5622 23:08:36.718749 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5623 23:08:36.722264 iDelay=208, Bit 11, Center 95 (8 ~ 183) 176
5624 23:08:36.725427 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5625 23:08:36.728694 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5626 23:08:36.731849 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5627 23:08:36.738553 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5628 23:08:36.738723 ==
5629 23:08:36.741781 Dram Type= 6, Freq= 0, CH_1, rank 0
5630 23:08:36.745207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5631 23:08:36.745281 ==
5632 23:08:36.745343 DQS Delay:
5633 23:08:36.748410 DQS0 = 0, DQS1 = 0
5634 23:08:36.748483 DQM Delay:
5635 23:08:36.751742 DQM0 = 103, DQM1 = 98
5636 23:08:36.751850 DQ Delay:
5637 23:08:36.754968 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5638 23:08:36.758380 DQ4 =99, DQ5 =115, DQ6 =115, DQ7 =103
5639 23:08:36.761822 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =95
5640 23:08:36.764965 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5641 23:08:36.765045
5642 23:08:36.765108
5643 23:08:36.765166 ==
5644 23:08:36.768203 Dram Type= 6, Freq= 0, CH_1, rank 0
5645 23:08:36.775467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5646 23:08:36.775636 ==
5647 23:08:36.775722
5648 23:08:36.775801
5649 23:08:36.775874 TX Vref Scan disable
5650 23:08:36.778920 == TX Byte 0 ==
5651 23:08:36.781908 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5652 23:08:36.785237 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5653 23:08:36.788698 == TX Byte 1 ==
5654 23:08:36.792254 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5655 23:08:36.799083 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5656 23:08:36.799271 ==
5657 23:08:36.801940 Dram Type= 6, Freq= 0, CH_1, rank 0
5658 23:08:36.805546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5659 23:08:36.805736 ==
5660 23:08:36.805872
5661 23:08:36.805998
5662 23:08:36.809015 TX Vref Scan disable
5663 23:08:36.809208 == TX Byte 0 ==
5664 23:08:36.815128 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5665 23:08:36.818860 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5666 23:08:36.819151 == TX Byte 1 ==
5667 23:08:36.825653 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5668 23:08:36.829080 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5669 23:08:36.829490
5670 23:08:36.829872 [DATLAT]
5671 23:08:36.832128 Freq=933, CH1 RK0
5672 23:08:36.832704
5673 23:08:36.833057 DATLAT Default: 0xd
5674 23:08:36.835669 0, 0xFFFF, sum = 0
5675 23:08:36.836221 1, 0xFFFF, sum = 0
5676 23:08:36.838689 2, 0xFFFF, sum = 0
5677 23:08:36.839102 3, 0xFFFF, sum = 0
5678 23:08:36.842618 4, 0xFFFF, sum = 0
5679 23:08:36.843079 5, 0xFFFF, sum = 0
5680 23:08:36.845515 6, 0xFFFF, sum = 0
5681 23:08:36.846225 7, 0xFFFF, sum = 0
5682 23:08:36.849245 8, 0xFFFF, sum = 0
5683 23:08:36.852653 9, 0xFFFF, sum = 0
5684 23:08:36.853089 10, 0x0, sum = 1
5685 23:08:36.853428 11, 0x0, sum = 2
5686 23:08:36.855279 12, 0x0, sum = 3
5687 23:08:36.855695 13, 0x0, sum = 4
5688 23:08:36.859006 best_step = 11
5689 23:08:36.859415
5690 23:08:36.859739 ==
5691 23:08:36.862238 Dram Type= 6, Freq= 0, CH_1, rank 0
5692 23:08:36.865343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5693 23:08:36.865787 ==
5694 23:08:36.868888 RX Vref Scan: 1
5695 23:08:36.869298
5696 23:08:36.869669 RX Vref 0 -> 0, step: 1
5697 23:08:36.869986
5698 23:08:36.872250 RX Delay -45 -> 252, step: 4
5699 23:08:36.872737
5700 23:08:36.875493 Set Vref, RX VrefLevel [Byte0]: 54
5701 23:08:36.879093 [Byte1]: 52
5702 23:08:36.882668
5703 23:08:36.883182 Final RX Vref Byte 0 = 54 to rank0
5704 23:08:36.886285 Final RX Vref Byte 1 = 52 to rank0
5705 23:08:36.889841 Final RX Vref Byte 0 = 54 to rank1
5706 23:08:36.892749 Final RX Vref Byte 1 = 52 to rank1==
5707 23:08:36.896238 Dram Type= 6, Freq= 0, CH_1, rank 0
5708 23:08:36.902601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5709 23:08:36.903037 ==
5710 23:08:36.903372 DQS Delay:
5711 23:08:36.906051 DQS0 = 0, DQS1 = 0
5712 23:08:36.906464 DQM Delay:
5713 23:08:36.906796 DQM0 = 103, DQM1 = 98
5714 23:08:36.909273 DQ Delay:
5715 23:08:36.913261 DQ0 =106, DQ1 =98, DQ2 =94, DQ3 =102
5716 23:08:36.915887 DQ4 =102, DQ5 =112, DQ6 =110, DQ7 =102
5717 23:08:36.919286 DQ8 =88, DQ9 =90, DQ10 =98, DQ11 =92
5718 23:08:36.922542 DQ12 =104, DQ13 =102, DQ14 =106, DQ15 =106
5719 23:08:36.923031
5720 23:08:36.923366
5721 23:08:36.928949 [DQSOSCAuto] RK0, (LSB)MR18= 0x162e, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 414 ps
5722 23:08:36.932735 CH1 RK0: MR19=505, MR18=162E
5723 23:08:36.939414 CH1_RK0: MR19=0x505, MR18=0x162E, DQSOSC=407, MR23=63, INC=65, DEC=43
5724 23:08:36.939832
5725 23:08:36.942447 ----->DramcWriteLeveling(PI) begin...
5726 23:08:36.942866 ==
5727 23:08:36.945890 Dram Type= 6, Freq= 0, CH_1, rank 1
5728 23:08:36.949151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5729 23:08:36.952723 ==
5730 23:08:36.953134 Write leveling (Byte 0): 26 => 26
5731 23:08:36.955609 Write leveling (Byte 1): 28 => 28
5732 23:08:36.958993 DramcWriteLeveling(PI) end<-----
5733 23:08:36.959406
5734 23:08:36.959730 ==
5735 23:08:36.962506 Dram Type= 6, Freq= 0, CH_1, rank 1
5736 23:08:36.969355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5737 23:08:36.969809 ==
5738 23:08:36.970140 [Gating] SW mode calibration
5739 23:08:36.978751 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5740 23:08:36.982077 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5741 23:08:36.988808 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5742 23:08:36.991913 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5743 23:08:36.995241 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5744 23:08:37.002086 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5745 23:08:37.005450 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5746 23:08:37.008577 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5747 23:08:37.014998 0 14 24 | B1->B0 | 2f2f 3131 | 0 0 | (0 1) (1 0)
5748 23:08:37.018676 0 14 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5749 23:08:37.021845 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5750 23:08:37.028138 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5751 23:08:37.031628 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5752 23:08:37.034974 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5753 23:08:37.038082 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5754 23:08:37.045042 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5755 23:08:37.048039 0 15 24 | B1->B0 | 3939 2d2d | 1 1 | (0 0) (0 0)
5756 23:08:37.051431 0 15 28 | B1->B0 | 4646 4242 | 0 0 | (0 0) (0 0)
5757 23:08:37.058109 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5758 23:08:37.061723 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5759 23:08:37.064531 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5760 23:08:37.071600 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5761 23:08:37.075103 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5762 23:08:37.077979 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5763 23:08:37.084856 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5764 23:08:37.087841 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5765 23:08:37.091219 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5766 23:08:37.098299 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5767 23:08:37.101662 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5768 23:08:37.104678 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5769 23:08:37.111618 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5770 23:08:37.115003 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5771 23:08:37.117899 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5772 23:08:37.124488 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5773 23:08:37.128004 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5774 23:08:37.130924 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 23:08:37.137684 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 23:08:37.141125 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 23:08:37.144388 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 23:08:37.151383 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 23:08:37.154316 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5780 23:08:37.157423 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5781 23:08:37.161253 Total UI for P1: 0, mck2ui 16
5782 23:08:37.164136 best dqsien dly found for B0: ( 1, 2, 24)
5783 23:08:37.167887 Total UI for P1: 0, mck2ui 16
5784 23:08:37.170796 best dqsien dly found for B1: ( 1, 2, 24)
5785 23:08:37.174289 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5786 23:08:37.177214 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5787 23:08:37.177688
5788 23:08:37.183873 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5789 23:08:37.187582 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5790 23:08:37.188006 [Gating] SW calibration Done
5791 23:08:37.190849 ==
5792 23:08:37.194041 Dram Type= 6, Freq= 0, CH_1, rank 1
5793 23:08:37.197238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5794 23:08:37.197692 ==
5795 23:08:37.198029 RX Vref Scan: 0
5796 23:08:37.198335
5797 23:08:37.200848 RX Vref 0 -> 0, step: 1
5798 23:08:37.201253
5799 23:08:37.203762 RX Delay -80 -> 252, step: 8
5800 23:08:37.207473 iDelay=208, Bit 0, Center 111 (24 ~ 199) 176
5801 23:08:37.210509 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5802 23:08:37.214293 iDelay=208, Bit 2, Center 95 (8 ~ 183) 176
5803 23:08:37.220749 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5804 23:08:37.224093 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5805 23:08:37.227292 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5806 23:08:37.230553 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5807 23:08:37.233793 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5808 23:08:37.237364 iDelay=208, Bit 8, Center 91 (0 ~ 183) 184
5809 23:08:37.244068 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5810 23:08:37.246854 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5811 23:08:37.250781 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5812 23:08:37.253484 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5813 23:08:37.257124 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5814 23:08:37.263826 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5815 23:08:37.267173 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5816 23:08:37.267596 ==
5817 23:08:37.270247 Dram Type= 6, Freq= 0, CH_1, rank 1
5818 23:08:37.273522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5819 23:08:37.273980 ==
5820 23:08:37.274319 DQS Delay:
5821 23:08:37.276599 DQS0 = 0, DQS1 = 0
5822 23:08:37.277019 DQM Delay:
5823 23:08:37.280503 DQM0 = 103, DQM1 = 99
5824 23:08:37.280918 DQ Delay:
5825 23:08:37.283324 DQ0 =111, DQ1 =99, DQ2 =95, DQ3 =99
5826 23:08:37.286572 DQ4 =95, DQ5 =115, DQ6 =111, DQ7 =99
5827 23:08:37.290000 DQ8 =91, DQ9 =91, DQ10 =99, DQ11 =91
5828 23:08:37.293670 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5829 23:08:37.294107
5830 23:08:37.294543
5831 23:08:37.296696 ==
5832 23:08:37.297126 Dram Type= 6, Freq= 0, CH_1, rank 1
5833 23:08:37.303657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5834 23:08:37.304248 ==
5835 23:08:37.304590
5836 23:08:37.304892
5837 23:08:37.306674 TX Vref Scan disable
5838 23:08:37.307085 == TX Byte 0 ==
5839 23:08:37.309742 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5840 23:08:37.316490 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5841 23:08:37.316905 == TX Byte 1 ==
5842 23:08:37.320398 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5843 23:08:37.326540 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5844 23:08:37.326950 ==
5845 23:08:37.330191 Dram Type= 6, Freq= 0, CH_1, rank 1
5846 23:08:37.333304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5847 23:08:37.333796 ==
5848 23:08:37.334133
5849 23:08:37.334439
5850 23:08:37.336610 TX Vref Scan disable
5851 23:08:37.340079 == TX Byte 0 ==
5852 23:08:37.343181 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5853 23:08:37.346644 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5854 23:08:37.349780 == TX Byte 1 ==
5855 23:08:37.353961 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5856 23:08:37.356853 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5857 23:08:37.357267
5858 23:08:37.357640 [DATLAT]
5859 23:08:37.360113 Freq=933, CH1 RK1
5860 23:08:37.360684
5861 23:08:37.361267 DATLAT Default: 0xb
5862 23:08:37.363091 0, 0xFFFF, sum = 0
5863 23:08:37.366611 1, 0xFFFF, sum = 0
5864 23:08:37.367131 2, 0xFFFF, sum = 0
5865 23:08:37.370195 3, 0xFFFF, sum = 0
5866 23:08:37.370640 4, 0xFFFF, sum = 0
5867 23:08:37.373347 5, 0xFFFF, sum = 0
5868 23:08:37.373890 6, 0xFFFF, sum = 0
5869 23:08:37.376631 7, 0xFFFF, sum = 0
5870 23:08:37.377190 8, 0xFFFF, sum = 0
5871 23:08:37.380394 9, 0xFFFF, sum = 0
5872 23:08:37.380947 10, 0x0, sum = 1
5873 23:08:37.383217 11, 0x0, sum = 2
5874 23:08:37.383814 12, 0x0, sum = 3
5875 23:08:37.386769 13, 0x0, sum = 4
5876 23:08:37.387207 best_step = 11
5877 23:08:37.387646
5878 23:08:37.388063 ==
5879 23:08:37.389936 Dram Type= 6, Freq= 0, CH_1, rank 1
5880 23:08:37.393301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5881 23:08:37.393780 ==
5882 23:08:37.396756 RX Vref Scan: 0
5883 23:08:37.397191
5884 23:08:37.399684 RX Vref 0 -> 0, step: 1
5885 23:08:37.400118
5886 23:08:37.400557 RX Delay -45 -> 252, step: 4
5887 23:08:37.407645 iDelay=203, Bit 0, Center 110 (27 ~ 194) 168
5888 23:08:37.410963 iDelay=203, Bit 1, Center 100 (15 ~ 186) 172
5889 23:08:37.414138 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5890 23:08:37.417610 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5891 23:08:37.420667 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5892 23:08:37.427341 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5893 23:08:37.430689 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5894 23:08:37.434178 iDelay=203, Bit 7, Center 102 (19 ~ 186) 168
5895 23:08:37.437455 iDelay=203, Bit 8, Center 92 (11 ~ 174) 164
5896 23:08:37.440665 iDelay=203, Bit 9, Center 90 (3 ~ 178) 176
5897 23:08:37.447067 iDelay=203, Bit 10, Center 100 (15 ~ 186) 172
5898 23:08:37.450925 iDelay=203, Bit 11, Center 94 (11 ~ 178) 168
5899 23:08:37.453756 iDelay=203, Bit 12, Center 108 (19 ~ 198) 180
5900 23:08:37.457065 iDelay=203, Bit 13, Center 104 (19 ~ 190) 172
5901 23:08:37.460181 iDelay=203, Bit 14, Center 106 (27 ~ 186) 160
5902 23:08:37.466827 iDelay=203, Bit 15, Center 106 (19 ~ 194) 176
5903 23:08:37.467275 ==
5904 23:08:37.470174 Dram Type= 6, Freq= 0, CH_1, rank 1
5905 23:08:37.473758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5906 23:08:37.474471 ==
5907 23:08:37.475209 DQS Delay:
5908 23:08:37.477119 DQS0 = 0, DQS1 = 0
5909 23:08:37.477720 DQM Delay:
5910 23:08:37.480198 DQM0 = 104, DQM1 = 100
5911 23:08:37.480804 DQ Delay:
5912 23:08:37.483603 DQ0 =110, DQ1 =100, DQ2 =94, DQ3 =100
5913 23:08:37.486689 DQ4 =100, DQ5 =118, DQ6 =114, DQ7 =102
5914 23:08:37.490378 DQ8 =92, DQ9 =90, DQ10 =100, DQ11 =94
5915 23:08:37.493387 DQ12 =108, DQ13 =104, DQ14 =106, DQ15 =106
5916 23:08:37.494098
5917 23:08:37.496580
5918 23:08:37.503211 [DQSOSCAuto] RK1, (LSB)MR18= 0x2d01, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 407 ps
5919 23:08:37.506833 CH1 RK1: MR19=505, MR18=2D01
5920 23:08:37.513072 CH1_RK1: MR19=0x505, MR18=0x2D01, DQSOSC=407, MR23=63, INC=65, DEC=43
5921 23:08:37.513365 [RxdqsGatingPostProcess] freq 933
5922 23:08:37.519707 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5923 23:08:37.523128 best DQS0 dly(2T, 0.5T) = (0, 10)
5924 23:08:37.526456 best DQS1 dly(2T, 0.5T) = (0, 10)
5925 23:08:37.529717 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5926 23:08:37.532972 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5927 23:08:37.536721 best DQS0 dly(2T, 0.5T) = (0, 10)
5928 23:08:37.539708 best DQS1 dly(2T, 0.5T) = (0, 10)
5929 23:08:37.543204 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5930 23:08:37.546272 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5931 23:08:37.549907 Pre-setting of DQS Precalculation
5932 23:08:37.553297 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5933 23:08:37.559854 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5934 23:08:37.566448 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5935 23:08:37.569628
5936 23:08:37.569919
5937 23:08:37.570149 [Calibration Summary] 1866 Mbps
5938 23:08:37.573223 CH 0, Rank 0
5939 23:08:37.573514 SW Impedance : PASS
5940 23:08:37.576248 DUTY Scan : NO K
5941 23:08:37.579491 ZQ Calibration : PASS
5942 23:08:37.580004 Jitter Meter : NO K
5943 23:08:37.583248 CBT Training : PASS
5944 23:08:37.586229 Write leveling : PASS
5945 23:08:37.586580 RX DQS gating : PASS
5946 23:08:37.589819 RX DQ/DQS(RDDQC) : PASS
5947 23:08:37.592985 TX DQ/DQS : PASS
5948 23:08:37.593065 RX DATLAT : PASS
5949 23:08:37.596257 RX DQ/DQS(Engine): PASS
5950 23:08:37.599667 TX OE : NO K
5951 23:08:37.599748 All Pass.
5952 23:08:37.599811
5953 23:08:37.599870 CH 0, Rank 1
5954 23:08:37.602892 SW Impedance : PASS
5955 23:08:37.606464 DUTY Scan : NO K
5956 23:08:37.606546 ZQ Calibration : PASS
5957 23:08:37.609555 Jitter Meter : NO K
5958 23:08:37.612614 CBT Training : PASS
5959 23:08:37.612718 Write leveling : PASS
5960 23:08:37.616169 RX DQS gating : PASS
5961 23:08:37.616250 RX DQ/DQS(RDDQC) : PASS
5962 23:08:37.619298 TX DQ/DQS : PASS
5963 23:08:37.622590 RX DATLAT : PASS
5964 23:08:37.622677 RX DQ/DQS(Engine): PASS
5965 23:08:37.626105 TX OE : NO K
5966 23:08:37.626206 All Pass.
5967 23:08:37.626317
5968 23:08:37.629389 CH 1, Rank 0
5969 23:08:37.629505 SW Impedance : PASS
5970 23:08:37.632700 DUTY Scan : NO K
5971 23:08:37.636262 ZQ Calibration : PASS
5972 23:08:37.636390 Jitter Meter : NO K
5973 23:08:37.639345 CBT Training : PASS
5974 23:08:37.642513 Write leveling : PASS
5975 23:08:37.642652 RX DQS gating : PASS
5976 23:08:37.645915 RX DQ/DQS(RDDQC) : PASS
5977 23:08:37.649008 TX DQ/DQS : PASS
5978 23:08:37.649136 RX DATLAT : PASS
5979 23:08:37.652549 RX DQ/DQS(Engine): PASS
5980 23:08:37.655570 TX OE : NO K
5981 23:08:37.655773 All Pass.
5982 23:08:37.655964
5983 23:08:37.656158 CH 1, Rank 1
5984 23:08:37.659304 SW Impedance : PASS
5985 23:08:37.662831 DUTY Scan : NO K
5986 23:08:37.663051 ZQ Calibration : PASS
5987 23:08:37.666077 Jitter Meter : NO K
5988 23:08:37.669660 CBT Training : PASS
5989 23:08:37.669885 Write leveling : PASS
5990 23:08:37.672460 RX DQS gating : PASS
5991 23:08:37.672707 RX DQ/DQS(RDDQC) : PASS
5992 23:08:37.676309 TX DQ/DQS : PASS
5993 23:08:37.679240 RX DATLAT : PASS
5994 23:08:37.679681 RX DQ/DQS(Engine): PASS
5995 23:08:37.682387 TX OE : NO K
5996 23:08:37.682837 All Pass.
5997 23:08:37.683338
5998 23:08:37.686066 DramC Write-DBI off
5999 23:08:37.689326 PER_BANK_REFRESH: Hybrid Mode
6000 23:08:37.689909 TX_TRACKING: ON
6001 23:08:37.699212 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6002 23:08:37.702386 [FAST_K] Save calibration result to emmc
6003 23:08:37.705869 dramc_set_vcore_voltage set vcore to 650000
6004 23:08:37.708964 Read voltage for 400, 6
6005 23:08:37.709377 Vio18 = 0
6006 23:08:37.709745 Vcore = 650000
6007 23:08:37.712771 Vdram = 0
6008 23:08:37.713180 Vddq = 0
6009 23:08:37.713503 Vmddr = 0
6010 23:08:37.719631 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6011 23:08:37.722378 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6012 23:08:37.725474 MEM_TYPE=3, freq_sel=20
6013 23:08:37.729064 sv_algorithm_assistance_LP4_800
6014 23:08:37.732518 ============ PULL DRAM RESETB DOWN ============
6015 23:08:37.738741 ========== PULL DRAM RESETB DOWN end =========
6016 23:08:37.742306 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6017 23:08:37.745230 ===================================
6018 23:08:37.748454 LPDDR4 DRAM CONFIGURATION
6019 23:08:37.752027 ===================================
6020 23:08:37.752110 EX_ROW_EN[0] = 0x0
6021 23:08:37.755283 EX_ROW_EN[1] = 0x0
6022 23:08:37.755370 LP4Y_EN = 0x0
6023 23:08:37.758354 WORK_FSP = 0x0
6024 23:08:37.758439 WL = 0x2
6025 23:08:37.761991 RL = 0x2
6026 23:08:37.762070 BL = 0x2
6027 23:08:37.765065 RPST = 0x0
6028 23:08:37.765136 RD_PRE = 0x0
6029 23:08:37.768695 WR_PRE = 0x1
6030 23:08:37.768790 WR_PST = 0x0
6031 23:08:37.771611 DBI_WR = 0x0
6032 23:08:37.775395 DBI_RD = 0x0
6033 23:08:37.775477 OTF = 0x1
6034 23:08:37.778915 ===================================
6035 23:08:37.781800 ===================================
6036 23:08:37.781883 ANA top config
6037 23:08:37.784922 ===================================
6038 23:08:37.788317 DLL_ASYNC_EN = 0
6039 23:08:37.792135 ALL_SLAVE_EN = 1
6040 23:08:37.795364 NEW_RANK_MODE = 1
6041 23:08:37.798715 DLL_IDLE_MODE = 1
6042 23:08:37.798797 LP45_APHY_COMB_EN = 1
6043 23:08:37.801684 TX_ODT_DIS = 1
6044 23:08:37.805381 NEW_8X_MODE = 1
6045 23:08:37.808245 ===================================
6046 23:08:37.811430 ===================================
6047 23:08:37.815173 data_rate = 800
6048 23:08:37.818001 CKR = 1
6049 23:08:37.818081 DQ_P2S_RATIO = 4
6050 23:08:37.822013 ===================================
6051 23:08:37.824975 CA_P2S_RATIO = 4
6052 23:08:37.828274 DQ_CA_OPEN = 0
6053 23:08:37.831448 DQ_SEMI_OPEN = 1
6054 23:08:37.834472 CA_SEMI_OPEN = 1
6055 23:08:37.837930 CA_FULL_RATE = 0
6056 23:08:37.838011 DQ_CKDIV4_EN = 0
6057 23:08:37.841071 CA_CKDIV4_EN = 1
6058 23:08:37.844816 CA_PREDIV_EN = 0
6059 23:08:37.847966 PH8_DLY = 0
6060 23:08:37.851695 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6061 23:08:37.854494 DQ_AAMCK_DIV = 0
6062 23:08:37.854574 CA_AAMCK_DIV = 0
6063 23:08:37.858090 CA_ADMCK_DIV = 4
6064 23:08:37.861495 DQ_TRACK_CA_EN = 0
6065 23:08:37.864501 CA_PICK = 800
6066 23:08:37.867809 CA_MCKIO = 400
6067 23:08:37.871325 MCKIO_SEMI = 400
6068 23:08:37.874358 PLL_FREQ = 3016
6069 23:08:37.874439 DQ_UI_PI_RATIO = 32
6070 23:08:37.877933 CA_UI_PI_RATIO = 32
6071 23:08:37.881214 ===================================
6072 23:08:37.884778 ===================================
6073 23:08:37.888238 memory_type:LPDDR4
6074 23:08:37.891113 GP_NUM : 10
6075 23:08:37.891211 SRAM_EN : 1
6076 23:08:37.894561 MD32_EN : 0
6077 23:08:37.897943 ===================================
6078 23:08:37.901094 [ANA_INIT] >>>>>>>>>>>>>>
6079 23:08:37.901175 <<<<<< [CONFIGURE PHASE]: ANA_TX
6080 23:08:37.904257 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6081 23:08:37.907907 ===================================
6082 23:08:37.910994 data_rate = 800,PCW = 0X7400
6083 23:08:37.914220 ===================================
6084 23:08:37.918017 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6085 23:08:37.924419 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6086 23:08:37.934358 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6087 23:08:37.941159 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6088 23:08:37.944117 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6089 23:08:37.947939 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6090 23:08:37.948021 [ANA_INIT] flow start
6091 23:08:37.951419 [ANA_INIT] PLL >>>>>>>>
6092 23:08:37.954120 [ANA_INIT] PLL <<<<<<<<
6093 23:08:37.957892 [ANA_INIT] MIDPI >>>>>>>>
6094 23:08:37.957974 [ANA_INIT] MIDPI <<<<<<<<
6095 23:08:37.960906 [ANA_INIT] DLL >>>>>>>>
6096 23:08:37.960988 [ANA_INIT] flow end
6097 23:08:37.967752 ============ LP4 DIFF to SE enter ============
6098 23:08:37.970898 ============ LP4 DIFF to SE exit ============
6099 23:08:37.973962 [ANA_INIT] <<<<<<<<<<<<<
6100 23:08:37.977695 [Flow] Enable top DCM control >>>>>
6101 23:08:37.981065 [Flow] Enable top DCM control <<<<<
6102 23:08:37.984280 Enable DLL master slave shuffle
6103 23:08:37.987455 ==============================================================
6104 23:08:37.990985 Gating Mode config
6105 23:08:37.994422 ==============================================================
6106 23:08:37.997743 Config description:
6107 23:08:38.007409 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6108 23:08:38.014942 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6109 23:08:38.017751 SELPH_MODE 0: By rank 1: By Phase
6110 23:08:38.024399 ==============================================================
6111 23:08:38.027691 GAT_TRACK_EN = 0
6112 23:08:38.030884 RX_GATING_MODE = 2
6113 23:08:38.034353 RX_GATING_TRACK_MODE = 2
6114 23:08:38.037872 SELPH_MODE = 1
6115 23:08:38.041066 PICG_EARLY_EN = 1
6116 23:08:38.041478 VALID_LAT_VALUE = 1
6117 23:08:38.047886 ==============================================================
6118 23:08:38.051021 Enter into Gating configuration >>>>
6119 23:08:38.053963 Exit from Gating configuration <<<<
6120 23:08:38.057493 Enter into DVFS_PRE_config >>>>>
6121 23:08:38.067331 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6122 23:08:38.071098 Exit from DVFS_PRE_config <<<<<
6123 23:08:38.074168 Enter into PICG configuration >>>>
6124 23:08:38.077456 Exit from PICG configuration <<<<
6125 23:08:38.080579 [RX_INPUT] configuration >>>>>
6126 23:08:38.083901 [RX_INPUT] configuration <<<<<
6127 23:08:38.087274 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6128 23:08:38.093893 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6129 23:08:38.101072 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6130 23:08:38.107639 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6131 23:08:38.114042 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6132 23:08:38.120665 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6133 23:08:38.123720 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6134 23:08:38.127422 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6135 23:08:38.130614 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6136 23:08:38.136993 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6137 23:08:38.140342 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6138 23:08:38.143879 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6139 23:08:38.147569 ===================================
6140 23:08:38.150418 LPDDR4 DRAM CONFIGURATION
6141 23:08:38.153510 ===================================
6142 23:08:38.154222 EX_ROW_EN[0] = 0x0
6143 23:08:38.157274 EX_ROW_EN[1] = 0x0
6144 23:08:38.157725 LP4Y_EN = 0x0
6145 23:08:38.160659 WORK_FSP = 0x0
6146 23:08:38.160954 WL = 0x2
6147 23:08:38.164418 RL = 0x2
6148 23:08:38.166811 BL = 0x2
6149 23:08:38.167120 RPST = 0x0
6150 23:08:38.170588 RD_PRE = 0x0
6151 23:08:38.170895 WR_PRE = 0x1
6152 23:08:38.173434 WR_PST = 0x0
6153 23:08:38.173721 DBI_WR = 0x0
6154 23:08:38.177228 DBI_RD = 0x0
6155 23:08:38.177482 OTF = 0x1
6156 23:08:38.179971 ===================================
6157 23:08:38.183481 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6158 23:08:38.190644 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6159 23:08:38.193725 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6160 23:08:38.196857 ===================================
6161 23:08:38.199965 LPDDR4 DRAM CONFIGURATION
6162 23:08:38.203619 ===================================
6163 23:08:38.203775 EX_ROW_EN[0] = 0x10
6164 23:08:38.206392 EX_ROW_EN[1] = 0x0
6165 23:08:38.206535 LP4Y_EN = 0x0
6166 23:08:38.209944 WORK_FSP = 0x0
6167 23:08:38.210070 WL = 0x2
6168 23:08:38.213478 RL = 0x2
6169 23:08:38.213602 BL = 0x2
6170 23:08:38.216457 RPST = 0x0
6171 23:08:38.216588 RD_PRE = 0x0
6172 23:08:38.219879 WR_PRE = 0x1
6173 23:08:38.219996 WR_PST = 0x0
6174 23:08:38.223570 DBI_WR = 0x0
6175 23:08:38.226374 DBI_RD = 0x0
6176 23:08:38.226493 OTF = 0x1
6177 23:08:38.230011 ===================================
6178 23:08:38.236401 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6179 23:08:38.239894 nWR fixed to 30
6180 23:08:38.243500 [ModeRegInit_LP4] CH0 RK0
6181 23:08:38.243639 [ModeRegInit_LP4] CH0 RK1
6182 23:08:38.246383 [ModeRegInit_LP4] CH1 RK0
6183 23:08:38.250180 [ModeRegInit_LP4] CH1 RK1
6184 23:08:38.250282 match AC timing 19
6185 23:08:38.256629 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6186 23:08:38.259677 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6187 23:08:38.263199 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6188 23:08:38.269907 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6189 23:08:38.273565 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6190 23:08:38.273675 ==
6191 23:08:38.276372 Dram Type= 6, Freq= 0, CH_0, rank 0
6192 23:08:38.279751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6193 23:08:38.279837 ==
6194 23:08:38.286128 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6195 23:08:38.293039 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6196 23:08:38.296262 [CA 0] Center 36 (8~64) winsize 57
6197 23:08:38.299763 [CA 1] Center 36 (8~64) winsize 57
6198 23:08:38.302767 [CA 2] Center 36 (8~64) winsize 57
6199 23:08:38.306163 [CA 3] Center 36 (8~64) winsize 57
6200 23:08:38.309303 [CA 4] Center 36 (8~64) winsize 57
6201 23:08:38.309422 [CA 5] Center 36 (8~64) winsize 57
6202 23:08:38.309519
6203 23:08:38.316106 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6204 23:08:38.316221
6205 23:08:38.319484 [CATrainingPosCal] consider 1 rank data
6206 23:08:38.322895 u2DelayCellTimex100 = 270/100 ps
6207 23:08:38.326266 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6208 23:08:38.329338 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6209 23:08:38.332685 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6210 23:08:38.336081 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6211 23:08:38.339610 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6212 23:08:38.342541 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6213 23:08:38.342651
6214 23:08:38.346213 CA PerBit enable=1, Macro0, CA PI delay=36
6215 23:08:38.346296
6216 23:08:38.349380 [CBTSetCACLKResult] CA Dly = 36
6217 23:08:38.353066 CS Dly: 1 (0~32)
6218 23:08:38.353152 ==
6219 23:08:38.356274 Dram Type= 6, Freq= 0, CH_0, rank 1
6220 23:08:38.359464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6221 23:08:38.359583 ==
6222 23:08:38.366092 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6223 23:08:38.373090 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6224 23:08:38.373183 [CA 0] Center 36 (8~64) winsize 57
6225 23:08:38.375932 [CA 1] Center 36 (8~64) winsize 57
6226 23:08:38.379168 [CA 2] Center 36 (8~64) winsize 57
6227 23:08:38.382777 [CA 3] Center 36 (8~64) winsize 57
6228 23:08:38.385654 [CA 4] Center 36 (8~64) winsize 57
6229 23:08:38.389030 [CA 5] Center 36 (8~64) winsize 57
6230 23:08:38.389119
6231 23:08:38.392720 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6232 23:08:38.392821
6233 23:08:38.395716 [CATrainingPosCal] consider 2 rank data
6234 23:08:38.399042 u2DelayCellTimex100 = 270/100 ps
6235 23:08:38.402416 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6236 23:08:38.406034 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6237 23:08:38.412533 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6238 23:08:38.415534 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6239 23:08:38.418970 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6240 23:08:38.422176 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6241 23:08:38.422253
6242 23:08:38.425516 CA PerBit enable=1, Macro0, CA PI delay=36
6243 23:08:38.425636
6244 23:08:38.428721 [CBTSetCACLKResult] CA Dly = 36
6245 23:08:38.428796 CS Dly: 1 (0~32)
6246 23:08:38.428873
6247 23:08:38.435696 ----->DramcWriteLeveling(PI) begin...
6248 23:08:38.435788 ==
6249 23:08:38.438693 Dram Type= 6, Freq= 0, CH_0, rank 0
6250 23:08:38.442201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6251 23:08:38.442314 ==
6252 23:08:38.445244 Write leveling (Byte 0): 40 => 8
6253 23:08:38.448498 Write leveling (Byte 1): 40 => 8
6254 23:08:38.452192 DramcWriteLeveling(PI) end<-----
6255 23:08:38.452286
6256 23:08:38.452351 ==
6257 23:08:38.455581 Dram Type= 6, Freq= 0, CH_0, rank 0
6258 23:08:38.458681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6259 23:08:38.458764 ==
6260 23:08:38.462173 [Gating] SW mode calibration
6261 23:08:38.468898 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6262 23:08:38.475366 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6263 23:08:38.478518 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6264 23:08:38.481833 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6265 23:08:38.488974 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6266 23:08:38.491760 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6267 23:08:38.495182 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6268 23:08:38.498710 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6269 23:08:38.505510 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6270 23:08:38.508902 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6271 23:08:38.512357 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6272 23:08:38.515226 Total UI for P1: 0, mck2ui 16
6273 23:08:38.519048 best dqsien dly found for B0: ( 0, 14, 24)
6274 23:08:38.521974 Total UI for P1: 0, mck2ui 16
6275 23:08:38.525414 best dqsien dly found for B1: ( 0, 14, 24)
6276 23:08:38.528404 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6277 23:08:38.531673 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6278 23:08:38.535343
6279 23:08:38.538796 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6280 23:08:38.542040 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6281 23:08:38.545718 [Gating] SW calibration Done
6282 23:08:38.545799 ==
6283 23:08:38.548698 Dram Type= 6, Freq= 0, CH_0, rank 0
6284 23:08:38.552148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6285 23:08:38.552233 ==
6286 23:08:38.552298 RX Vref Scan: 0
6287 23:08:38.552359
6288 23:08:38.555499 RX Vref 0 -> 0, step: 1
6289 23:08:38.555580
6290 23:08:38.559060 RX Delay -410 -> 252, step: 16
6291 23:08:38.561616 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6292 23:08:38.568449 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6293 23:08:38.572434 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6294 23:08:38.575564 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6295 23:08:38.578403 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6296 23:08:38.585103 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6297 23:08:38.588442 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6298 23:08:38.592261 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6299 23:08:38.595388 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6300 23:08:38.602116 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6301 23:08:38.605249 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6302 23:08:38.608396 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6303 23:08:38.611825 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6304 23:08:38.618768 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6305 23:08:38.621962 iDelay=230, Bit 14, Center -11 (-250 ~ 229) 480
6306 23:08:38.625430 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6307 23:08:38.625512 ==
6308 23:08:38.628849 Dram Type= 6, Freq= 0, CH_0, rank 0
6309 23:08:38.632244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6310 23:08:38.632325 ==
6311 23:08:38.635247 DQS Delay:
6312 23:08:38.635327 DQS0 = 27, DQS1 = 35
6313 23:08:38.638682 DQM Delay:
6314 23:08:38.638762 DQM0 = 11, DQM1 = 12
6315 23:08:38.641721 DQ Delay:
6316 23:08:38.641802 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6317 23:08:38.645425 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24
6318 23:08:38.648589 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6319 23:08:38.652034 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6320 23:08:38.652114
6321 23:08:38.652177
6322 23:08:38.652237 ==
6323 23:08:38.655038 Dram Type= 6, Freq= 0, CH_0, rank 0
6324 23:08:38.661960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6325 23:08:38.662041 ==
6326 23:08:38.662105
6327 23:08:38.662164
6328 23:08:38.662221 TX Vref Scan disable
6329 23:08:38.664890 == TX Byte 0 ==
6330 23:08:38.668413 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6331 23:08:38.671528 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6332 23:08:38.675085 == TX Byte 1 ==
6333 23:08:38.678174 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6334 23:08:38.681505 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6335 23:08:38.685081 ==
6336 23:08:38.687930 Dram Type= 6, Freq= 0, CH_0, rank 0
6337 23:08:38.691581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6338 23:08:38.691665 ==
6339 23:08:38.691729
6340 23:08:38.691788
6341 23:08:38.695099 TX Vref Scan disable
6342 23:08:38.695180 == TX Byte 0 ==
6343 23:08:38.698115 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6344 23:08:38.705103 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6345 23:08:38.705185 == TX Byte 1 ==
6346 23:08:38.708424 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6347 23:08:38.711360 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6348 23:08:38.714754
6349 23:08:38.714834 [DATLAT]
6350 23:08:38.714898 Freq=400, CH0 RK0
6351 23:08:38.714959
6352 23:08:38.717961 DATLAT Default: 0xf
6353 23:08:38.718044 0, 0xFFFF, sum = 0
6354 23:08:38.721431 1, 0xFFFF, sum = 0
6355 23:08:38.721512 2, 0xFFFF, sum = 0
6356 23:08:38.724828 3, 0xFFFF, sum = 0
6357 23:08:38.724911 4, 0xFFFF, sum = 0
6358 23:08:38.728139 5, 0xFFFF, sum = 0
6359 23:08:38.728247 6, 0xFFFF, sum = 0
6360 23:08:38.732042 7, 0xFFFF, sum = 0
6361 23:08:38.734769 8, 0xFFFF, sum = 0
6362 23:08:38.734877 9, 0xFFFF, sum = 0
6363 23:08:38.738135 10, 0xFFFF, sum = 0
6364 23:08:38.738237 11, 0xFFFF, sum = 0
6365 23:08:38.741589 12, 0xFFFF, sum = 0
6366 23:08:38.741692 13, 0x0, sum = 1
6367 23:08:38.744806 14, 0x0, sum = 2
6368 23:08:38.744912 15, 0x0, sum = 3
6369 23:08:38.747959 16, 0x0, sum = 4
6370 23:08:38.748065 best_step = 14
6371 23:08:38.748156
6372 23:08:38.748252 ==
6373 23:08:38.751579 Dram Type= 6, Freq= 0, CH_0, rank 0
6374 23:08:38.754598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6375 23:08:38.754700 ==
6376 23:08:38.758041 RX Vref Scan: 1
6377 23:08:38.758147
6378 23:08:38.760982 RX Vref 0 -> 0, step: 1
6379 23:08:38.761088
6380 23:08:38.761181 RX Delay -311 -> 252, step: 8
6381 23:08:38.764498
6382 23:08:38.764602 Set Vref, RX VrefLevel [Byte0]: 53
6383 23:08:38.767700 [Byte1]: 46
6384 23:08:38.773350
6385 23:08:38.773454 Final RX Vref Byte 0 = 53 to rank0
6386 23:08:38.776614 Final RX Vref Byte 1 = 46 to rank0
6387 23:08:38.780321 Final RX Vref Byte 0 = 53 to rank1
6388 23:08:38.783120 Final RX Vref Byte 1 = 46 to rank1==
6389 23:08:38.786586 Dram Type= 6, Freq= 0, CH_0, rank 0
6390 23:08:38.793232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6391 23:08:38.793339 ==
6392 23:08:38.793430 DQS Delay:
6393 23:08:38.796355 DQS0 = 28, DQS1 = 36
6394 23:08:38.796459 DQM Delay:
6395 23:08:38.796550 DQM0 = 11, DQM1 = 13
6396 23:08:38.800135 DQ Delay:
6397 23:08:38.803319 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6398 23:08:38.806150 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6399 23:08:38.806254 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
6400 23:08:38.809754 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =20
6401 23:08:38.812970
6402 23:08:38.813076
6403 23:08:38.819753 [DQSOSCAuto] RK0, (LSB)MR18= 0xc7b3, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 385 ps
6404 23:08:38.823228 CH0 RK0: MR19=C0C, MR18=C7B3
6405 23:08:38.829723 CH0_RK0: MR19=0xC0C, MR18=0xC7B3, DQSOSC=385, MR23=63, INC=398, DEC=265
6406 23:08:38.829829 ==
6407 23:08:38.832829 Dram Type= 6, Freq= 0, CH_0, rank 1
6408 23:08:38.836389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6409 23:08:38.836496 ==
6410 23:08:38.839539 [Gating] SW mode calibration
6411 23:08:38.846169 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6412 23:08:38.852810 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6413 23:08:38.856416 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6414 23:08:38.859679 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6415 23:08:38.866237 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6416 23:08:38.869768 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6417 23:08:38.873207 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6418 23:08:38.876111 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6419 23:08:38.883110 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6420 23:08:38.886060 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6421 23:08:38.889368 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6422 23:08:38.893040 Total UI for P1: 0, mck2ui 16
6423 23:08:38.896489 best dqsien dly found for B0: ( 0, 14, 24)
6424 23:08:38.899270 Total UI for P1: 0, mck2ui 16
6425 23:08:38.902714 best dqsien dly found for B1: ( 0, 14, 24)
6426 23:08:38.906516 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6427 23:08:38.909629 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6428 23:08:38.913083
6429 23:08:38.916178 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6430 23:08:38.919761 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6431 23:08:38.922560 [Gating] SW calibration Done
6432 23:08:38.922669 ==
6433 23:08:38.926357 Dram Type= 6, Freq= 0, CH_0, rank 1
6434 23:08:38.929371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6435 23:08:38.929475 ==
6436 23:08:38.929565 RX Vref Scan: 0
6437 23:08:38.932866
6438 23:08:38.932969 RX Vref 0 -> 0, step: 1
6439 23:08:38.933054
6440 23:08:38.935795 RX Delay -410 -> 252, step: 16
6441 23:08:38.939271 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6442 23:08:38.945841 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6443 23:08:38.949345 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6444 23:08:38.952952 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6445 23:08:38.955794 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6446 23:08:38.962575 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6447 23:08:38.965872 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6448 23:08:38.968965 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6449 23:08:38.972635 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6450 23:08:38.979087 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6451 23:08:38.982301 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6452 23:08:38.985593 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6453 23:08:38.989196 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6454 23:08:38.996075 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6455 23:08:38.999133 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6456 23:08:39.002211 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6457 23:08:39.002315 ==
6458 23:08:39.005602 Dram Type= 6, Freq= 0, CH_0, rank 1
6459 23:08:39.009199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6460 23:08:39.012224 ==
6461 23:08:39.012333 DQS Delay:
6462 23:08:39.012429 DQS0 = 27, DQS1 = 35
6463 23:08:39.015715 DQM Delay:
6464 23:08:39.015820 DQM0 = 12, DQM1 = 11
6465 23:08:39.018891 DQ Delay:
6466 23:08:39.018993 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6467 23:08:39.022020 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6468 23:08:39.025464 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6469 23:08:39.029135 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6470 23:08:39.029241
6471 23:08:39.029337
6472 23:08:39.032146 ==
6473 23:08:39.035922 Dram Type= 6, Freq= 0, CH_0, rank 1
6474 23:08:39.038751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6475 23:08:39.038853 ==
6476 23:08:39.038943
6477 23:08:39.039030
6478 23:08:39.041902 TX Vref Scan disable
6479 23:08:39.042007 == TX Byte 0 ==
6480 23:08:39.045662 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6481 23:08:39.052219 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6482 23:08:39.052328 == TX Byte 1 ==
6483 23:08:39.056066 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6484 23:08:39.062506 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6485 23:08:39.062622 ==
6486 23:08:39.065125 Dram Type= 6, Freq= 0, CH_0, rank 1
6487 23:08:39.068969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6488 23:08:39.069078 ==
6489 23:08:39.069173
6490 23:08:39.069257
6491 23:08:39.071735 TX Vref Scan disable
6492 23:08:39.071841 == TX Byte 0 ==
6493 23:08:39.075483 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6494 23:08:39.081550 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6495 23:08:39.081693 == TX Byte 1 ==
6496 23:08:39.085282 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6497 23:08:39.091674 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6498 23:08:39.091779
6499 23:08:39.091873 [DATLAT]
6500 23:08:39.091957 Freq=400, CH0 RK1
6501 23:08:39.092039
6502 23:08:39.095204 DATLAT Default: 0xe
6503 23:08:39.095314 0, 0xFFFF, sum = 0
6504 23:08:39.098780 1, 0xFFFF, sum = 0
6505 23:08:39.098884 2, 0xFFFF, sum = 0
6506 23:08:39.101908 3, 0xFFFF, sum = 0
6507 23:08:39.105228 4, 0xFFFF, sum = 0
6508 23:08:39.105336 5, 0xFFFF, sum = 0
6509 23:08:39.108573 6, 0xFFFF, sum = 0
6510 23:08:39.108699 7, 0xFFFF, sum = 0
6511 23:08:39.112019 8, 0xFFFF, sum = 0
6512 23:08:39.112127 9, 0xFFFF, sum = 0
6513 23:08:39.115191 10, 0xFFFF, sum = 0
6514 23:08:39.115299 11, 0xFFFF, sum = 0
6515 23:08:39.118433 12, 0xFFFF, sum = 0
6516 23:08:39.118538 13, 0x0, sum = 1
6517 23:08:39.121867 14, 0x0, sum = 2
6518 23:08:39.121983 15, 0x0, sum = 3
6519 23:08:39.124938 16, 0x0, sum = 4
6520 23:08:39.125041 best_step = 14
6521 23:08:39.125135
6522 23:08:39.125227 ==
6523 23:08:39.128328 Dram Type= 6, Freq= 0, CH_0, rank 1
6524 23:08:39.131692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6525 23:08:39.134790 ==
6526 23:08:39.134896 RX Vref Scan: 0
6527 23:08:39.134984
6528 23:08:39.138242 RX Vref 0 -> 0, step: 1
6529 23:08:39.138344
6530 23:08:39.141890 RX Delay -311 -> 252, step: 8
6531 23:08:39.144860 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6532 23:08:39.151459 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6533 23:08:39.155010 iDelay=217, Bit 2, Center -16 (-239 ~ 208) 448
6534 23:08:39.157998 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6535 23:08:39.161691 iDelay=217, Bit 4, Center -12 (-239 ~ 216) 456
6536 23:08:39.168187 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6537 23:08:39.171155 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6538 23:08:39.174573 iDelay=217, Bit 7, Center -4 (-223 ~ 216) 440
6539 23:08:39.177685 iDelay=217, Bit 8, Center -32 (-247 ~ 184) 432
6540 23:08:39.184735 iDelay=217, Bit 9, Center -36 (-255 ~ 184) 440
6541 23:08:39.187940 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6542 23:08:39.191395 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6543 23:08:39.197881 iDelay=217, Bit 12, Center -16 (-231 ~ 200) 432
6544 23:08:39.200800 iDelay=217, Bit 13, Center -16 (-231 ~ 200) 432
6545 23:08:39.204307 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6546 23:08:39.207714 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6547 23:08:39.207820 ==
6548 23:08:39.211392 Dram Type= 6, Freq= 0, CH_0, rank 1
6549 23:08:39.217618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6550 23:08:39.217742 ==
6551 23:08:39.217834 DQS Delay:
6552 23:08:39.221447 DQS0 = 24, DQS1 = 36
6553 23:08:39.221552 DQM Delay:
6554 23:08:39.221688 DQM0 = 9, DQM1 = 14
6555 23:08:39.224321 DQ Delay:
6556 23:08:39.227459 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6557 23:08:39.230996 DQ4 =12, DQ5 =0, DQ6 =12, DQ7 =20
6558 23:08:39.231102 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6559 23:08:39.234420 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6560 23:08:39.234523
6561 23:08:39.237680
6562 23:08:39.244269 [DQSOSCAuto] RK1, (LSB)MR18= 0xb555, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 387 ps
6563 23:08:39.247426 CH0 RK1: MR19=C0C, MR18=B555
6564 23:08:39.254585 CH0_RK1: MR19=0xC0C, MR18=0xB555, DQSOSC=387, MR23=63, INC=394, DEC=262
6565 23:08:39.257556 [RxdqsGatingPostProcess] freq 400
6566 23:08:39.261052 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6567 23:08:39.264159 best DQS0 dly(2T, 0.5T) = (0, 10)
6568 23:08:39.267574 best DQS1 dly(2T, 0.5T) = (0, 10)
6569 23:08:39.270926 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6570 23:08:39.274593 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6571 23:08:39.277696 best DQS0 dly(2T, 0.5T) = (0, 10)
6572 23:08:39.280979 best DQS1 dly(2T, 0.5T) = (0, 10)
6573 23:08:39.283937 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6574 23:08:39.287712 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6575 23:08:39.291173 Pre-setting of DQS Precalculation
6576 23:08:39.294050 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6577 23:08:39.294155 ==
6578 23:08:39.297804 Dram Type= 6, Freq= 0, CH_1, rank 0
6579 23:08:39.304212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6580 23:08:39.304318 ==
6581 23:08:39.307197 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6582 23:08:39.314333 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6583 23:08:39.317226 [CA 0] Center 36 (8~64) winsize 57
6584 23:08:39.320566 [CA 1] Center 36 (8~64) winsize 57
6585 23:08:39.324214 [CA 2] Center 36 (8~64) winsize 57
6586 23:08:39.327259 [CA 3] Center 36 (8~64) winsize 57
6587 23:08:39.330493 [CA 4] Center 36 (8~64) winsize 57
6588 23:08:39.333747 [CA 5] Center 36 (8~64) winsize 57
6589 23:08:39.333851
6590 23:08:39.337538 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6591 23:08:39.337683
6592 23:08:39.340968 [CATrainingPosCal] consider 1 rank data
6593 23:08:39.343980 u2DelayCellTimex100 = 270/100 ps
6594 23:08:39.347576 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6595 23:08:39.351133 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6596 23:08:39.354324 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6597 23:08:39.357426 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6598 23:08:39.360975 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6599 23:08:39.364128 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6600 23:08:39.364234
6601 23:08:39.370885 CA PerBit enable=1, Macro0, CA PI delay=36
6602 23:08:39.370997
6603 23:08:39.371095 [CBTSetCACLKResult] CA Dly = 36
6604 23:08:39.373911 CS Dly: 1 (0~32)
6605 23:08:39.374015 ==
6606 23:08:39.377048 Dram Type= 6, Freq= 0, CH_1, rank 1
6607 23:08:39.380389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6608 23:08:39.380500 ==
6609 23:08:39.386886 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6610 23:08:39.394236 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6611 23:08:39.396962 [CA 0] Center 36 (8~64) winsize 57
6612 23:08:39.400545 [CA 1] Center 36 (8~64) winsize 57
6613 23:08:39.404140 [CA 2] Center 36 (8~64) winsize 57
6614 23:08:39.404245 [CA 3] Center 36 (8~64) winsize 57
6615 23:08:39.407252 [CA 4] Center 36 (8~64) winsize 57
6616 23:08:39.410697 [CA 5] Center 36 (8~64) winsize 57
6617 23:08:39.410799
6618 23:08:39.413898 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6619 23:08:39.417208
6620 23:08:39.420256 [CATrainingPosCal] consider 2 rank data
6621 23:08:39.420362 u2DelayCellTimex100 = 270/100 ps
6622 23:08:39.427215 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6623 23:08:39.430255 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6624 23:08:39.433928 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6625 23:08:39.437126 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6626 23:08:39.440679 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6627 23:08:39.443885 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6628 23:08:39.443991
6629 23:08:39.447090 CA PerBit enable=1, Macro0, CA PI delay=36
6630 23:08:39.447199
6631 23:08:39.450146 [CBTSetCACLKResult] CA Dly = 36
6632 23:08:39.453351 CS Dly: 1 (0~32)
6633 23:08:39.453456
6634 23:08:39.456890 ----->DramcWriteLeveling(PI) begin...
6635 23:08:39.456993 ==
6636 23:08:39.460396 Dram Type= 6, Freq= 0, CH_1, rank 0
6637 23:08:39.463375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6638 23:08:39.463483 ==
6639 23:08:39.467021 Write leveling (Byte 0): 40 => 8
6640 23:08:39.470536 Write leveling (Byte 1): 40 => 8
6641 23:08:39.473555 DramcWriteLeveling(PI) end<-----
6642 23:08:39.473696
6643 23:08:39.473786 ==
6644 23:08:39.476890 Dram Type= 6, Freq= 0, CH_1, rank 0
6645 23:08:39.480198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6646 23:08:39.480309 ==
6647 23:08:39.483710 [Gating] SW mode calibration
6648 23:08:39.490361 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6649 23:08:39.496856 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6650 23:08:39.499868 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6651 23:08:39.503535 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6652 23:08:39.509998 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6653 23:08:39.513478 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6654 23:08:39.517146 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6655 23:08:39.523630 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6656 23:08:39.527369 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6657 23:08:39.530416 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6658 23:08:39.537233 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6659 23:08:39.537312 Total UI for P1: 0, mck2ui 16
6660 23:08:39.539955 best dqsien dly found for B0: ( 0, 14, 24)
6661 23:08:39.543434 Total UI for P1: 0, mck2ui 16
6662 23:08:39.546595 best dqsien dly found for B1: ( 0, 14, 24)
6663 23:08:39.553424 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6664 23:08:39.556913 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6665 23:08:39.557017
6666 23:08:39.560020 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6667 23:08:39.563357 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6668 23:08:39.566834 [Gating] SW calibration Done
6669 23:08:39.566916 ==
6670 23:08:39.570212 Dram Type= 6, Freq= 0, CH_1, rank 0
6671 23:08:39.573454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6672 23:08:39.573554 ==
6673 23:08:39.577043 RX Vref Scan: 0
6674 23:08:39.577138
6675 23:08:39.577227 RX Vref 0 -> 0, step: 1
6676 23:08:39.577318
6677 23:08:39.580020 RX Delay -410 -> 252, step: 16
6678 23:08:39.583749 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6679 23:08:39.590385 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6680 23:08:39.593452 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6681 23:08:39.597305 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6682 23:08:39.600480 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6683 23:08:39.606621 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6684 23:08:39.610121 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6685 23:08:39.613098 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6686 23:08:39.616679 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6687 23:08:39.622953 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6688 23:08:39.626318 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6689 23:08:39.629772 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6690 23:08:39.633264 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6691 23:08:39.639939 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6692 23:08:39.643274 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6693 23:08:39.646303 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6694 23:08:39.646384 ==
6695 23:08:39.650035 Dram Type= 6, Freq= 0, CH_1, rank 0
6696 23:08:39.656615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6697 23:08:39.656696 ==
6698 23:08:39.656760 DQS Delay:
6699 23:08:39.659521 DQS0 = 35, DQS1 = 35
6700 23:08:39.659601 DQM Delay:
6701 23:08:39.663051 DQM0 = 17, DQM1 = 13
6702 23:08:39.663132 DQ Delay:
6703 23:08:39.666202 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =16
6704 23:08:39.669397 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6705 23:08:39.672808 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6706 23:08:39.676321 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6707 23:08:39.676402
6708 23:08:39.676466
6709 23:08:39.676526 ==
6710 23:08:39.679167 Dram Type= 6, Freq= 0, CH_1, rank 0
6711 23:08:39.682724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6712 23:08:39.682806 ==
6713 23:08:39.682870
6714 23:08:39.682928
6715 23:08:39.685754 TX Vref Scan disable
6716 23:08:39.685834 == TX Byte 0 ==
6717 23:08:39.692382 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6718 23:08:39.695855 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6719 23:08:39.695937 == TX Byte 1 ==
6720 23:08:39.702371 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6721 23:08:39.706328 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6722 23:08:39.706412 ==
6723 23:08:39.708858 Dram Type= 6, Freq= 0, CH_1, rank 0
6724 23:08:39.712412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6725 23:08:39.712499 ==
6726 23:08:39.712564
6727 23:08:39.712624
6728 23:08:39.715883 TX Vref Scan disable
6729 23:08:39.715964 == TX Byte 0 ==
6730 23:08:39.722427 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6731 23:08:39.725823 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6732 23:08:39.725903 == TX Byte 1 ==
6733 23:08:39.732599 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6734 23:08:39.735858 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6735 23:08:39.735936
6736 23:08:39.736000 [DATLAT]
6737 23:08:39.739250 Freq=400, CH1 RK0
6738 23:08:39.739358
6739 23:08:39.739451 DATLAT Default: 0xf
6740 23:08:39.742100 0, 0xFFFF, sum = 0
6741 23:08:39.742187 1, 0xFFFF, sum = 0
6742 23:08:39.745476 2, 0xFFFF, sum = 0
6743 23:08:39.745571 3, 0xFFFF, sum = 0
6744 23:08:39.749214 4, 0xFFFF, sum = 0
6745 23:08:39.749310 5, 0xFFFF, sum = 0
6746 23:08:39.752174 6, 0xFFFF, sum = 0
6747 23:08:39.752255 7, 0xFFFF, sum = 0
6748 23:08:39.755695 8, 0xFFFF, sum = 0
6749 23:08:39.755778 9, 0xFFFF, sum = 0
6750 23:08:39.759150 10, 0xFFFF, sum = 0
6751 23:08:39.759233 11, 0xFFFF, sum = 0
6752 23:08:39.762766 12, 0xFFFF, sum = 0
6753 23:08:39.765732 13, 0x0, sum = 1
6754 23:08:39.765830 14, 0x0, sum = 2
6755 23:08:39.765897 15, 0x0, sum = 3
6756 23:08:39.769063 16, 0x0, sum = 4
6757 23:08:39.769144 best_step = 14
6758 23:08:39.769207
6759 23:08:39.769266 ==
6760 23:08:39.771999 Dram Type= 6, Freq= 0, CH_1, rank 0
6761 23:08:39.778717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6762 23:08:39.778800 ==
6763 23:08:39.778864 RX Vref Scan: 1
6764 23:08:39.778923
6765 23:08:39.782539 RX Vref 0 -> 0, step: 1
6766 23:08:39.782619
6767 23:08:39.785703 RX Delay -311 -> 252, step: 8
6768 23:08:39.785784
6769 23:08:39.789197 Set Vref, RX VrefLevel [Byte0]: 54
6770 23:08:39.792080 [Byte1]: 52
6771 23:08:39.795242
6772 23:08:39.795322 Final RX Vref Byte 0 = 54 to rank0
6773 23:08:39.798752 Final RX Vref Byte 1 = 52 to rank0
6774 23:08:39.802267 Final RX Vref Byte 0 = 54 to rank1
6775 23:08:39.805529 Final RX Vref Byte 1 = 52 to rank1==
6776 23:08:39.808573 Dram Type= 6, Freq= 0, CH_1, rank 0
6777 23:08:39.814989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6778 23:08:39.815072 ==
6779 23:08:39.815136 DQS Delay:
6780 23:08:39.818551 DQS0 = 28, DQS1 = 32
6781 23:08:39.818655 DQM Delay:
6782 23:08:39.818737 DQM0 = 9, DQM1 = 11
6783 23:08:39.821614 DQ Delay:
6784 23:08:39.825381 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6785 23:08:39.825462 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6786 23:08:39.828835 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6787 23:08:39.831837 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =24
6788 23:08:39.831918
6789 23:08:39.831984
6790 23:08:39.842000 [DQSOSCAuto] RK0, (LSB)MR18= 0x8ec7, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 392 ps
6791 23:08:39.844960 CH1 RK0: MR19=C0C, MR18=8EC7
6792 23:08:39.852180 CH1_RK0: MR19=0xC0C, MR18=0x8EC7, DQSOSC=385, MR23=63, INC=398, DEC=265
6793 23:08:39.852262 ==
6794 23:08:39.855376 Dram Type= 6, Freq= 0, CH_1, rank 1
6795 23:08:39.858557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6796 23:08:39.858631 ==
6797 23:08:39.861541 [Gating] SW mode calibration
6798 23:08:39.868340 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6799 23:08:39.871835 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6800 23:08:39.878309 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6801 23:08:39.881565 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6802 23:08:39.884818 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6803 23:08:39.891767 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6804 23:08:39.894826 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6805 23:08:39.898760 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6806 23:08:39.905388 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6807 23:08:39.908245 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6808 23:08:39.911610 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6809 23:08:39.915115 Total UI for P1: 0, mck2ui 16
6810 23:08:39.918666 best dqsien dly found for B0: ( 0, 14, 24)
6811 23:08:39.921417 Total UI for P1: 0, mck2ui 16
6812 23:08:39.924998 best dqsien dly found for B1: ( 0, 14, 24)
6813 23:08:39.928027 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6814 23:08:39.931495 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6815 23:08:39.931577
6816 23:08:39.937933 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6817 23:08:39.941286 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6818 23:08:39.945078 [Gating] SW calibration Done
6819 23:08:39.945160 ==
6820 23:08:39.947846 Dram Type= 6, Freq= 0, CH_1, rank 1
6821 23:08:39.951290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6822 23:08:39.951373 ==
6823 23:08:39.951437 RX Vref Scan: 0
6824 23:08:39.951498
6825 23:08:39.954948 RX Vref 0 -> 0, step: 1
6826 23:08:39.955028
6827 23:08:39.958231 RX Delay -410 -> 252, step: 16
6828 23:08:39.961459 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6829 23:08:39.968231 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6830 23:08:39.971529 iDelay=230, Bit 2, Center -27 (-250 ~ 197) 448
6831 23:08:39.974536 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6832 23:08:39.977947 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6833 23:08:39.984436 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6834 23:08:39.987877 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6835 23:08:39.991445 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6836 23:08:39.994422 iDelay=230, Bit 8, Center -27 (-250 ~ 197) 448
6837 23:08:40.000922 iDelay=230, Bit 9, Center -27 (-250 ~ 197) 448
6838 23:08:40.004255 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6839 23:08:40.007803 iDelay=230, Bit 11, Center -19 (-250 ~ 213) 464
6840 23:08:40.011196 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6841 23:08:40.017477 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6842 23:08:40.021014 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6843 23:08:40.024265 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6844 23:08:40.024341 ==
6845 23:08:40.027288 Dram Type= 6, Freq= 0, CH_1, rank 1
6846 23:08:40.034137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6847 23:08:40.034222 ==
6848 23:08:40.034288 DQS Delay:
6849 23:08:40.037692 DQS0 = 27, DQS1 = 27
6850 23:08:40.037773 DQM Delay:
6851 23:08:40.037838 DQM0 = 11, DQM1 = 8
6852 23:08:40.040969 DQ Delay:
6853 23:08:40.041038 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6854 23:08:40.044179 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6855 23:08:40.047492 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6856 23:08:40.050919 DQ12 =16, DQ13 =8, DQ14 =8, DQ15 =16
6857 23:08:40.050989
6858 23:08:40.051050
6859 23:08:40.051108 ==
6860 23:08:40.053612 Dram Type= 6, Freq= 0, CH_1, rank 1
6861 23:08:40.060619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6862 23:08:40.060701 ==
6863 23:08:40.060764
6864 23:08:40.060823
6865 23:08:40.060879 TX Vref Scan disable
6866 23:08:40.063837 == TX Byte 0 ==
6867 23:08:40.067280 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6868 23:08:40.070290 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6869 23:08:40.073731 == TX Byte 1 ==
6870 23:08:40.077444 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6871 23:08:40.080437 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6872 23:08:40.084065 ==
6873 23:08:40.084145 Dram Type= 6, Freq= 0, CH_1, rank 1
6874 23:08:40.090180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6875 23:08:40.090261 ==
6876 23:08:40.090325
6877 23:08:40.090384
6878 23:08:40.093763 TX Vref Scan disable
6879 23:08:40.093844 == TX Byte 0 ==
6880 23:08:40.097512 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6881 23:08:40.100876 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6882 23:08:40.103556 == TX Byte 1 ==
6883 23:08:40.106975 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6884 23:08:40.110697 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6885 23:08:40.110780
6886 23:08:40.114056 [DATLAT]
6887 23:08:40.114136 Freq=400, CH1 RK1
6888 23:08:40.114200
6889 23:08:40.117326 DATLAT Default: 0xe
6890 23:08:40.117406 0, 0xFFFF, sum = 0
6891 23:08:40.120574 1, 0xFFFF, sum = 0
6892 23:08:40.120656 2, 0xFFFF, sum = 0
6893 23:08:40.123808 3, 0xFFFF, sum = 0
6894 23:08:40.123890 4, 0xFFFF, sum = 0
6895 23:08:40.126882 5, 0xFFFF, sum = 0
6896 23:08:40.126963 6, 0xFFFF, sum = 0
6897 23:08:40.130628 7, 0xFFFF, sum = 0
6898 23:08:40.133496 8, 0xFFFF, sum = 0
6899 23:08:40.133640 9, 0xFFFF, sum = 0
6900 23:08:40.136917 10, 0xFFFF, sum = 0
6901 23:08:40.137022 11, 0xFFFF, sum = 0
6902 23:08:40.140246 12, 0xFFFF, sum = 0
6903 23:08:40.140356 13, 0x0, sum = 1
6904 23:08:40.143287 14, 0x0, sum = 2
6905 23:08:40.143365 15, 0x0, sum = 3
6906 23:08:40.146558 16, 0x0, sum = 4
6907 23:08:40.146635 best_step = 14
6908 23:08:40.146698
6909 23:08:40.146756 ==
6910 23:08:40.150278 Dram Type= 6, Freq= 0, CH_1, rank 1
6911 23:08:40.153502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6912 23:08:40.153642 ==
6913 23:08:40.156910 RX Vref Scan: 0
6914 23:08:40.157016
6915 23:08:40.159951 RX Vref 0 -> 0, step: 1
6916 23:08:40.160053
6917 23:08:40.160145 RX Delay -295 -> 252, step: 8
6918 23:08:40.168863 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6919 23:08:40.172103 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6920 23:08:40.175473 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6921 23:08:40.178305 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6922 23:08:40.184933 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6923 23:08:40.188424 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6924 23:08:40.191599 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6925 23:08:40.195258 iDelay=217, Bit 7, Center -16 (-239 ~ 208) 448
6926 23:08:40.201766 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6927 23:08:40.205112 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6928 23:08:40.208713 iDelay=217, Bit 10, Center -16 (-239 ~ 208) 448
6929 23:08:40.212240 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6930 23:08:40.218795 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6931 23:08:40.221764 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6932 23:08:40.225434 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6933 23:08:40.231680 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6934 23:08:40.231784 ==
6935 23:08:40.234957 Dram Type= 6, Freq= 0, CH_1, rank 1
6936 23:08:40.238544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6937 23:08:40.238642 ==
6938 23:08:40.238735 DQS Delay:
6939 23:08:40.242189 DQS0 = 28, DQS1 = 32
6940 23:08:40.242260 DQM Delay:
6941 23:08:40.245105 DQM0 = 11, DQM1 = 11
6942 23:08:40.245200 DQ Delay:
6943 23:08:40.248936 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
6944 23:08:40.252008 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =12
6945 23:08:40.254798 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6946 23:08:40.258147 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
6947 23:08:40.258247
6948 23:08:40.258336
6949 23:08:40.264708 [DQSOSCAuto] RK1, (LSB)MR18= 0xc052, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 386 ps
6950 23:08:40.268086 CH1 RK1: MR19=C0C, MR18=C052
6951 23:08:40.274765 CH1_RK1: MR19=0xC0C, MR18=0xC052, DQSOSC=386, MR23=63, INC=396, DEC=264
6952 23:08:40.278547 [RxdqsGatingPostProcess] freq 400
6953 23:08:40.281734 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6954 23:08:40.285246 best DQS0 dly(2T, 0.5T) = (0, 10)
6955 23:08:40.288256 best DQS1 dly(2T, 0.5T) = (0, 10)
6956 23:08:40.291925 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6957 23:08:40.294849 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6958 23:08:40.298235 best DQS0 dly(2T, 0.5T) = (0, 10)
6959 23:08:40.301324 best DQS1 dly(2T, 0.5T) = (0, 10)
6960 23:08:40.305161 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6961 23:08:40.308464 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6962 23:08:40.311760 Pre-setting of DQS Precalculation
6963 23:08:40.314883 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6964 23:08:40.324846 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6965 23:08:40.331392 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6966 23:08:40.331468
6967 23:08:40.331530
6968 23:08:40.334923 [Calibration Summary] 800 Mbps
6969 23:08:40.335004 CH 0, Rank 0
6970 23:08:40.338055 SW Impedance : PASS
6971 23:08:40.338136 DUTY Scan : NO K
6972 23:08:40.342085 ZQ Calibration : PASS
6973 23:08:40.345066 Jitter Meter : NO K
6974 23:08:40.345145 CBT Training : PASS
6975 23:08:40.348186 Write leveling : PASS
6976 23:08:40.351374 RX DQS gating : PASS
6977 23:08:40.351454 RX DQ/DQS(RDDQC) : PASS
6978 23:08:40.354904 TX DQ/DQS : PASS
6979 23:08:40.358097 RX DATLAT : PASS
6980 23:08:40.358177 RX DQ/DQS(Engine): PASS
6981 23:08:40.361816 TX OE : NO K
6982 23:08:40.361897 All Pass.
6983 23:08:40.361960
6984 23:08:40.364525 CH 0, Rank 1
6985 23:08:40.364605 SW Impedance : PASS
6986 23:08:40.367839 DUTY Scan : NO K
6987 23:08:40.371214 ZQ Calibration : PASS
6988 23:08:40.371295 Jitter Meter : NO K
6989 23:08:40.374641 CBT Training : PASS
6990 23:08:40.374744 Write leveling : NO K
6991 23:08:40.378200 RX DQS gating : PASS
6992 23:08:40.381473 RX DQ/DQS(RDDQC) : PASS
6993 23:08:40.381604 TX DQ/DQS : PASS
6994 23:08:40.384782 RX DATLAT : PASS
6995 23:08:40.387808 RX DQ/DQS(Engine): PASS
6996 23:08:40.387997 TX OE : NO K
6997 23:08:40.391055 All Pass.
6998 23:08:40.391201
6999 23:08:40.391300 CH 1, Rank 0
7000 23:08:40.394302 SW Impedance : PASS
7001 23:08:40.394391 DUTY Scan : NO K
7002 23:08:40.397720 ZQ Calibration : PASS
7003 23:08:40.401336 Jitter Meter : NO K
7004 23:08:40.401442 CBT Training : PASS
7005 23:08:40.404329 Write leveling : PASS
7006 23:08:40.408059 RX DQS gating : PASS
7007 23:08:40.408140 RX DQ/DQS(RDDQC) : PASS
7008 23:08:40.411236 TX DQ/DQS : PASS
7009 23:08:40.414442 RX DATLAT : PASS
7010 23:08:40.414522 RX DQ/DQS(Engine): PASS
7011 23:08:40.417543 TX OE : NO K
7012 23:08:40.417647 All Pass.
7013 23:08:40.417712
7014 23:08:40.420995 CH 1, Rank 1
7015 23:08:40.421076 SW Impedance : PASS
7016 23:08:40.424532 DUTY Scan : NO K
7017 23:08:40.427753 ZQ Calibration : PASS
7018 23:08:40.427833 Jitter Meter : NO K
7019 23:08:40.430542 CBT Training : PASS
7020 23:08:40.434139 Write leveling : NO K
7021 23:08:40.434220 RX DQS gating : PASS
7022 23:08:40.437081 RX DQ/DQS(RDDQC) : PASS
7023 23:08:40.440811 TX DQ/DQS : PASS
7024 23:08:40.440894 RX DATLAT : PASS
7025 23:08:40.444164 RX DQ/DQS(Engine): PASS
7026 23:08:40.444245 TX OE : NO K
7027 23:08:40.447114 All Pass.
7028 23:08:40.447199
7029 23:08:40.447263 DramC Write-DBI off
7030 23:08:40.450730 PER_BANK_REFRESH: Hybrid Mode
7031 23:08:40.454255 TX_TRACKING: ON
7032 23:08:40.460127 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7033 23:08:40.463750 [FAST_K] Save calibration result to emmc
7034 23:08:40.470539 dramc_set_vcore_voltage set vcore to 725000
7035 23:08:40.470619 Read voltage for 1600, 0
7036 23:08:40.473963 Vio18 = 0
7037 23:08:40.474043 Vcore = 725000
7038 23:08:40.474108 Vdram = 0
7039 23:08:40.474167 Vddq = 0
7040 23:08:40.476929 Vmddr = 0
7041 23:08:40.480593 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7042 23:08:40.487405 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7043 23:08:40.490383 MEM_TYPE=3, freq_sel=13
7044 23:08:40.490463 sv_algorithm_assistance_LP4_3733
7045 23:08:40.496567 ============ PULL DRAM RESETB DOWN ============
7046 23:08:40.499942 ========== PULL DRAM RESETB DOWN end =========
7047 23:08:40.503439 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7048 23:08:40.506329 ===================================
7049 23:08:40.509867 LPDDR4 DRAM CONFIGURATION
7050 23:08:40.513390 ===================================
7051 23:08:40.516294 EX_ROW_EN[0] = 0x0
7052 23:08:40.516420 EX_ROW_EN[1] = 0x0
7053 23:08:40.519679 LP4Y_EN = 0x0
7054 23:08:40.519760 WORK_FSP = 0x1
7055 23:08:40.523169 WL = 0x5
7056 23:08:40.523249 RL = 0x5
7057 23:08:40.526270 BL = 0x2
7058 23:08:40.526352 RPST = 0x0
7059 23:08:40.529713 RD_PRE = 0x0
7060 23:08:40.533020 WR_PRE = 0x1
7061 23:08:40.533101 WR_PST = 0x1
7062 23:08:40.536792 DBI_WR = 0x0
7063 23:08:40.536872 DBI_RD = 0x0
7064 23:08:40.539581 OTF = 0x1
7065 23:08:40.542970 ===================================
7066 23:08:40.546214 ===================================
7067 23:08:40.546294 ANA top config
7068 23:08:40.549764 ===================================
7069 23:08:40.552727 DLL_ASYNC_EN = 0
7070 23:08:40.555920 ALL_SLAVE_EN = 0
7071 23:08:40.556001 NEW_RANK_MODE = 1
7072 23:08:40.559133 DLL_IDLE_MODE = 1
7073 23:08:40.562757 LP45_APHY_COMB_EN = 1
7074 23:08:40.565943 TX_ODT_DIS = 0
7075 23:08:40.566024 NEW_8X_MODE = 1
7076 23:08:40.569667 ===================================
7077 23:08:40.572309 ===================================
7078 23:08:40.575915 data_rate = 3200
7079 23:08:40.579293 CKR = 1
7080 23:08:40.582227 DQ_P2S_RATIO = 8
7081 23:08:40.585904 ===================================
7082 23:08:40.588808 CA_P2S_RATIO = 8
7083 23:08:40.592553 DQ_CA_OPEN = 0
7084 23:08:40.595536 DQ_SEMI_OPEN = 0
7085 23:08:40.595620 CA_SEMI_OPEN = 0
7086 23:08:40.599075 CA_FULL_RATE = 0
7087 23:08:40.602587 DQ_CKDIV4_EN = 0
7088 23:08:40.605546 CA_CKDIV4_EN = 0
7089 23:08:40.608874 CA_PREDIV_EN = 0
7090 23:08:40.612269 PH8_DLY = 12
7091 23:08:40.612351 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7092 23:08:40.615827 DQ_AAMCK_DIV = 4
7093 23:08:40.618825 CA_AAMCK_DIV = 4
7094 23:08:40.622299 CA_ADMCK_DIV = 4
7095 23:08:40.625567 DQ_TRACK_CA_EN = 0
7096 23:08:40.628998 CA_PICK = 1600
7097 23:08:40.631879 CA_MCKIO = 1600
7098 23:08:40.631961 MCKIO_SEMI = 0
7099 23:08:40.635492 PLL_FREQ = 3068
7100 23:08:40.638678 DQ_UI_PI_RATIO = 32
7101 23:08:40.642260 CA_UI_PI_RATIO = 0
7102 23:08:40.645458 ===================================
7103 23:08:40.648883 ===================================
7104 23:08:40.652295 memory_type:LPDDR4
7105 23:08:40.652377 GP_NUM : 10
7106 23:08:40.655555 SRAM_EN : 1
7107 23:08:40.655636 MD32_EN : 0
7108 23:08:40.658896 ===================================
7109 23:08:40.662492 [ANA_INIT] >>>>>>>>>>>>>>
7110 23:08:40.665280 <<<<<< [CONFIGURE PHASE]: ANA_TX
7111 23:08:40.668915 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7112 23:08:40.672366 ===================================
7113 23:08:40.675274 data_rate = 3200,PCW = 0X7600
7114 23:08:40.678853 ===================================
7115 23:08:40.681785 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7116 23:08:40.688614 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7117 23:08:40.691870 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7118 23:08:40.698823 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7119 23:08:40.702491 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7120 23:08:40.705530 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7121 23:08:40.705656 [ANA_INIT] flow start
7122 23:08:40.708608 [ANA_INIT] PLL >>>>>>>>
7123 23:08:40.712023 [ANA_INIT] PLL <<<<<<<<
7124 23:08:40.712105 [ANA_INIT] MIDPI >>>>>>>>
7125 23:08:40.715335 [ANA_INIT] MIDPI <<<<<<<<
7126 23:08:40.718298 [ANA_INIT] DLL >>>>>>>>
7127 23:08:40.721749 [ANA_INIT] DLL <<<<<<<<
7128 23:08:40.721830 [ANA_INIT] flow end
7129 23:08:40.725295 ============ LP4 DIFF to SE enter ============
7130 23:08:40.731896 ============ LP4 DIFF to SE exit ============
7131 23:08:40.731979 [ANA_INIT] <<<<<<<<<<<<<
7132 23:08:40.735016 [Flow] Enable top DCM control >>>>>
7133 23:08:40.738549 [Flow] Enable top DCM control <<<<<
7134 23:08:40.741773 Enable DLL master slave shuffle
7135 23:08:40.748477 ==============================================================
7136 23:08:40.748558 Gating Mode config
7137 23:08:40.755090 ==============================================================
7138 23:08:40.758271 Config description:
7139 23:08:40.764825 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7140 23:08:40.771921 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7141 23:08:40.778576 SELPH_MODE 0: By rank 1: By Phase
7142 23:08:40.785034 ==============================================================
7143 23:08:40.785146 GAT_TRACK_EN = 1
7144 23:08:40.788691 RX_GATING_MODE = 2
7145 23:08:40.791575 RX_GATING_TRACK_MODE = 2
7146 23:08:40.795376 SELPH_MODE = 1
7147 23:08:40.798318 PICG_EARLY_EN = 1
7148 23:08:40.801548 VALID_LAT_VALUE = 1
7149 23:08:40.808330 ==============================================================
7150 23:08:40.811654 Enter into Gating configuration >>>>
7151 23:08:40.815072 Exit from Gating configuration <<<<
7152 23:08:40.818391 Enter into DVFS_PRE_config >>>>>
7153 23:08:40.828638 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7154 23:08:40.831322 Exit from DVFS_PRE_config <<<<<
7155 23:08:40.834952 Enter into PICG configuration >>>>
7156 23:08:40.837997 Exit from PICG configuration <<<<
7157 23:08:40.841331 [RX_INPUT] configuration >>>>>
7158 23:08:40.841438 [RX_INPUT] configuration <<<<<
7159 23:08:40.848043 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7160 23:08:40.854701 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7161 23:08:40.858059 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7162 23:08:40.864666 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7163 23:08:40.871219 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7164 23:08:40.878093 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7165 23:08:40.881450 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7166 23:08:40.884920 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7167 23:08:40.891181 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7168 23:08:40.894613 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7169 23:08:40.898237 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7170 23:08:40.904945 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7171 23:08:40.907941 ===================================
7172 23:08:40.908023 LPDDR4 DRAM CONFIGURATION
7173 23:08:40.911296 ===================================
7174 23:08:40.914910 EX_ROW_EN[0] = 0x0
7175 23:08:40.914992 EX_ROW_EN[1] = 0x0
7176 23:08:40.918178 LP4Y_EN = 0x0
7177 23:08:40.918258 WORK_FSP = 0x1
7178 23:08:40.921350 WL = 0x5
7179 23:08:40.921429 RL = 0x5
7180 23:08:40.924568 BL = 0x2
7181 23:08:40.924649 RPST = 0x0
7182 23:08:40.928047 RD_PRE = 0x0
7183 23:08:40.931185 WR_PRE = 0x1
7184 23:08:40.931331 WR_PST = 0x1
7185 23:08:40.934498 DBI_WR = 0x0
7186 23:08:40.934599 DBI_RD = 0x0
7187 23:08:40.937873 OTF = 0x1
7188 23:08:40.940900 ===================================
7189 23:08:40.944590 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7190 23:08:40.947696 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7191 23:08:40.951238 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7192 23:08:40.954338 ===================================
7193 23:08:40.957453 LPDDR4 DRAM CONFIGURATION
7194 23:08:40.961713 ===================================
7195 23:08:40.964531 EX_ROW_EN[0] = 0x10
7196 23:08:40.964612 EX_ROW_EN[1] = 0x0
7197 23:08:40.968153 LP4Y_EN = 0x0
7198 23:08:40.968235 WORK_FSP = 0x1
7199 23:08:40.971274 WL = 0x5
7200 23:08:40.971355 RL = 0x5
7201 23:08:40.974161 BL = 0x2
7202 23:08:40.974242 RPST = 0x0
7203 23:08:40.977825 RD_PRE = 0x0
7204 23:08:40.977907 WR_PRE = 0x1
7205 23:08:40.981297 WR_PST = 0x1
7206 23:08:40.984516 DBI_WR = 0x0
7207 23:08:40.984596 DBI_RD = 0x0
7208 23:08:40.988167 OTF = 0x1
7209 23:08:40.990778 ===================================
7210 23:08:40.994267 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7211 23:08:40.994349 ==
7212 23:08:40.997997 Dram Type= 6, Freq= 0, CH_0, rank 0
7213 23:08:41.004335 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7214 23:08:41.004417 ==
7215 23:08:41.004482 [Duty_Offset_Calibration]
7216 23:08:41.007541 B0:2 B1:1 CA:1
7217 23:08:41.007622
7218 23:08:41.011181 [DutyScan_Calibration_Flow] k_type=0
7219 23:08:41.020610
7220 23:08:41.020720 ==CLK 0==
7221 23:08:41.024050 Final CLK duty delay cell = 0
7222 23:08:41.027091 [0] MAX Duty = 5156%(X100), DQS PI = 22
7223 23:08:41.030556 [0] MIN Duty = 4907%(X100), DQS PI = 0
7224 23:08:41.030636 [0] AVG Duty = 5031%(X100)
7225 23:08:41.033794
7226 23:08:41.037231 CH0 CLK Duty spec in!! Max-Min= 249%
7227 23:08:41.040731 [DutyScan_Calibration_Flow] ====Done====
7228 23:08:41.040811
7229 23:08:41.043801 [DutyScan_Calibration_Flow] k_type=1
7230 23:08:41.060080
7231 23:08:41.060163 ==DQS 0 ==
7232 23:08:41.063069 Final DQS duty delay cell = -4
7233 23:08:41.066404 [-4] MAX Duty = 5125%(X100), DQS PI = 24
7234 23:08:41.069635 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7235 23:08:41.072906 [-4] AVG Duty = 4891%(X100)
7236 23:08:41.072985
7237 23:08:41.073048 ==DQS 1 ==
7238 23:08:41.076565 Final DQS duty delay cell = 0
7239 23:08:41.079374 [0] MAX Duty = 5187%(X100), DQS PI = 20
7240 23:08:41.082921 [0] MIN Duty = 5031%(X100), DQS PI = 32
7241 23:08:41.086077 [0] AVG Duty = 5109%(X100)
7242 23:08:41.086157
7243 23:08:41.089730 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7244 23:08:41.089809
7245 23:08:41.092755 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7246 23:08:41.096279 [DutyScan_Calibration_Flow] ====Done====
7247 23:08:41.096358
7248 23:08:41.099373 [DutyScan_Calibration_Flow] k_type=3
7249 23:08:41.116360
7250 23:08:41.116444 ==DQM 0 ==
7251 23:08:41.119856 Final DQM duty delay cell = 0
7252 23:08:41.123190 [0] MAX Duty = 5187%(X100), DQS PI = 32
7253 23:08:41.126169 [0] MIN Duty = 4844%(X100), DQS PI = 60
7254 23:08:41.129744 [0] AVG Duty = 5015%(X100)
7255 23:08:41.129850
7256 23:08:41.129949 ==DQM 1 ==
7257 23:08:41.132714 Final DQM duty delay cell = -4
7258 23:08:41.136244 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7259 23:08:41.139686 [-4] MIN Duty = 4813%(X100), DQS PI = 34
7260 23:08:41.143295 [-4] AVG Duty = 4906%(X100)
7261 23:08:41.143381
7262 23:08:41.146238 CH0 DQM 0 Duty spec in!! Max-Min= 343%
7263 23:08:41.146312
7264 23:08:41.149467 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7265 23:08:41.153306 [DutyScan_Calibration_Flow] ====Done====
7266 23:08:41.153386
7267 23:08:41.156537 [DutyScan_Calibration_Flow] k_type=2
7268 23:08:41.173858
7269 23:08:41.173965 ==DQ 0 ==
7270 23:08:41.177201 Final DQ duty delay cell = 0
7271 23:08:41.181097 [0] MAX Duty = 5062%(X100), DQS PI = 26
7272 23:08:41.183668 [0] MIN Duty = 4907%(X100), DQS PI = 0
7273 23:08:41.183774 [0] AVG Duty = 4984%(X100)
7274 23:08:41.187386
7275 23:08:41.187467 ==DQ 1 ==
7276 23:08:41.190150 Final DQ duty delay cell = 0
7277 23:08:41.193950 [0] MAX Duty = 5125%(X100), DQS PI = 6
7278 23:08:41.197017 [0] MIN Duty = 4907%(X100), DQS PI = 34
7279 23:08:41.197098 [0] AVG Duty = 5016%(X100)
7280 23:08:41.197163
7281 23:08:41.200512 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7282 23:08:41.203738
7283 23:08:41.207247 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7284 23:08:41.210149 [DutyScan_Calibration_Flow] ====Done====
7285 23:08:41.210232 ==
7286 23:08:41.213927 Dram Type= 6, Freq= 0, CH_1, rank 0
7287 23:08:41.216834 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7288 23:08:41.216921 ==
7289 23:08:41.220623 [Duty_Offset_Calibration]
7290 23:08:41.220730 B0:1 B1:0 CA:0
7291 23:08:41.220826
7292 23:08:41.223476 [DutyScan_Calibration_Flow] k_type=0
7293 23:08:41.233532
7294 23:08:41.233654 ==CLK 0==
7295 23:08:41.236608 Final CLK duty delay cell = -4
7296 23:08:41.239876 [-4] MAX Duty = 4969%(X100), DQS PI = 22
7297 23:08:41.242976 [-4] MIN Duty = 4844%(X100), DQS PI = 50
7298 23:08:41.246299 [-4] AVG Duty = 4906%(X100)
7299 23:08:41.246383
7300 23:08:41.250076 CH1 CLK Duty spec in!! Max-Min= 125%
7301 23:08:41.253001 [DutyScan_Calibration_Flow] ====Done====
7302 23:08:41.253082
7303 23:08:41.256620 [DutyScan_Calibration_Flow] k_type=1
7304 23:08:41.273458
7305 23:08:41.273570 ==DQS 0 ==
7306 23:08:41.276633 Final DQS duty delay cell = 0
7307 23:08:41.280325 [0] MAX Duty = 5094%(X100), DQS PI = 16
7308 23:08:41.283315 [0] MIN Duty = 4844%(X100), DQS PI = 48
7309 23:08:41.286342 [0] AVG Duty = 4969%(X100)
7310 23:08:41.286423
7311 23:08:41.286486 ==DQS 1 ==
7312 23:08:41.289796 Final DQS duty delay cell = 0
7313 23:08:41.293384 [0] MAX Duty = 5249%(X100), DQS PI = 16
7314 23:08:41.296593 [0] MIN Duty = 4969%(X100), DQS PI = 6
7315 23:08:41.299868 [0] AVG Duty = 5109%(X100)
7316 23:08:41.299947
7317 23:08:41.303029 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7318 23:08:41.303113
7319 23:08:41.306543 CH1 DQS 1 Duty spec in!! Max-Min= 280%
7320 23:08:41.309899 [DutyScan_Calibration_Flow] ====Done====
7321 23:08:41.309979
7322 23:08:41.313412 [DutyScan_Calibration_Flow] k_type=3
7323 23:08:41.329943
7324 23:08:41.330024 ==DQM 0 ==
7325 23:08:41.333820 Final DQM duty delay cell = 0
7326 23:08:41.337179 [0] MAX Duty = 5187%(X100), DQS PI = 8
7327 23:08:41.339998 [0] MIN Duty = 4969%(X100), DQS PI = 48
7328 23:08:41.340079 [0] AVG Duty = 5078%(X100)
7329 23:08:41.343652
7330 23:08:41.343732 ==DQM 1 ==
7331 23:08:41.347485 Final DQM duty delay cell = 0
7332 23:08:41.350043 [0] MAX Duty = 5093%(X100), DQS PI = 16
7333 23:08:41.353895 [0] MIN Duty = 4907%(X100), DQS PI = 50
7334 23:08:41.353975 [0] AVG Duty = 5000%(X100)
7335 23:08:41.356812
7336 23:08:41.360102 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7337 23:08:41.360182
7338 23:08:41.363807 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7339 23:08:41.366731 [DutyScan_Calibration_Flow] ====Done====
7340 23:08:41.366811
7341 23:08:41.370372 [DutyScan_Calibration_Flow] k_type=2
7342 23:08:41.386491
7343 23:08:41.386571 ==DQ 0 ==
7344 23:08:41.389526 Final DQ duty delay cell = -4
7345 23:08:41.392776 [-4] MAX Duty = 5062%(X100), DQS PI = 12
7346 23:08:41.396138 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7347 23:08:41.399758 [-4] AVG Duty = 4968%(X100)
7348 23:08:41.399951
7349 23:08:41.400061 ==DQ 1 ==
7350 23:08:41.403030 Final DQ duty delay cell = 0
7351 23:08:41.405905 [0] MAX Duty = 5124%(X100), DQS PI = 16
7352 23:08:41.409824 [0] MIN Duty = 4938%(X100), DQS PI = 8
7353 23:08:41.412719 [0] AVG Duty = 5031%(X100)
7354 23:08:41.412827
7355 23:08:41.416171 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7356 23:08:41.416282
7357 23:08:41.419343 CH1 DQ 1 Duty spec in!! Max-Min= 186%
7358 23:08:41.423018 [DutyScan_Calibration_Flow] ====Done====
7359 23:08:41.426120 nWR fixed to 30
7360 23:08:41.429725 [ModeRegInit_LP4] CH0 RK0
7361 23:08:41.429806 [ModeRegInit_LP4] CH0 RK1
7362 23:08:41.432606 [ModeRegInit_LP4] CH1 RK0
7363 23:08:41.436074 [ModeRegInit_LP4] CH1 RK1
7364 23:08:41.436180 match AC timing 5
7365 23:08:41.442977 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7366 23:08:41.446091 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7367 23:08:41.449699 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7368 23:08:41.455916 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7369 23:08:41.458992 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7370 23:08:41.459112 [MiockJmeterHQA]
7371 23:08:41.459208
7372 23:08:41.462811 [DramcMiockJmeter] u1RxGatingPI = 0
7373 23:08:41.465906 0 : 4363, 4137
7374 23:08:41.465989 4 : 4257, 4030
7375 23:08:41.469537 8 : 4365, 4140
7376 23:08:41.469640 12 : 4363, 4137
7377 23:08:41.469708 16 : 4253, 4026
7378 23:08:41.472386 20 : 4253, 4026
7379 23:08:41.472468 24 : 4252, 4027
7380 23:08:41.475899 28 : 4252, 4027
7381 23:08:41.475981 32 : 4253, 4026
7382 23:08:41.479504 36 : 4254, 4029
7383 23:08:41.479586 40 : 4363, 4137
7384 23:08:41.482527 44 : 4253, 4027
7385 23:08:41.482609 48 : 4252, 4027
7386 23:08:41.482674 52 : 4252, 4027
7387 23:08:41.485833 56 : 4254, 4029
7388 23:08:41.485919 60 : 4250, 4027
7389 23:08:41.489316 64 : 4361, 4137
7390 23:08:41.489397 68 : 4361, 4138
7391 23:08:41.492765 72 : 4250, 4026
7392 23:08:41.492848 76 : 4250, 4027
7393 23:08:41.492914 80 : 4250, 4027
7394 23:08:41.496383 84 : 4252, 4029
7395 23:08:41.496465 88 : 4252, 133
7396 23:08:41.499470 92 : 4250, 0
7397 23:08:41.499553 96 : 4250, 0
7398 23:08:41.499618 100 : 4253, 0
7399 23:08:41.502805 104 : 4252, 0
7400 23:08:41.502887 108 : 4250, 0
7401 23:08:41.506323 112 : 4250, 0
7402 23:08:41.506405 116 : 4252, 0
7403 23:08:41.506470 120 : 4250, 0
7404 23:08:41.509372 124 : 4250, 0
7405 23:08:41.509454 128 : 4252, 0
7406 23:08:41.512336 132 : 4360, 0
7407 23:08:41.512411 136 : 4361, 0
7408 23:08:41.512474 140 : 4363, 0
7409 23:08:41.515685 144 : 4249, 0
7410 23:08:41.515767 148 : 4250, 0
7411 23:08:41.515878 152 : 4250, 0
7412 23:08:41.519199 156 : 4250, 0
7413 23:08:41.519281 160 : 4250, 0
7414 23:08:41.522754 164 : 4250, 0
7415 23:08:41.522835 168 : 4252, 0
7416 23:08:41.522900 172 : 4250, 0
7417 23:08:41.526092 176 : 4250, 0
7418 23:08:41.526174 180 : 4252, 0
7419 23:08:41.528991 184 : 4360, 0
7420 23:08:41.529071 188 : 4361, 0
7421 23:08:41.529135 192 : 4363, 0
7422 23:08:41.532162 196 : 4249, 0
7423 23:08:41.532243 200 : 4250, 0
7424 23:08:41.535576 204 : 4250, 1266
7425 23:08:41.535658 208 : 4250, 3988
7426 23:08:41.539530 212 : 4361, 4137
7427 23:08:41.539612 216 : 4250, 4027
7428 23:08:41.542755 220 : 4361, 4138
7429 23:08:41.542836 224 : 4361, 4137
7430 23:08:41.542901 228 : 4250, 4026
7431 23:08:41.545753 232 : 4250, 4027
7432 23:08:41.545835 236 : 4363, 4140
7433 23:08:41.549179 240 : 4250, 4027
7434 23:08:41.549259 244 : 4250, 4026
7435 23:08:41.552099 248 : 4250, 4027
7436 23:08:41.552180 252 : 4252, 4030
7437 23:08:41.555417 256 : 4250, 4027
7438 23:08:41.555518 260 : 4250, 4026
7439 23:08:41.559211 264 : 4361, 4137
7440 23:08:41.559292 268 : 4250, 4027
7441 23:08:41.562162 272 : 4250, 4027
7442 23:08:41.562243 276 : 4360, 4137
7443 23:08:41.565847 280 : 4250, 4026
7444 23:08:41.565929 284 : 4252, 4027
7445 23:08:41.565994 288 : 4363, 4140
7446 23:08:41.569240 292 : 4250, 4027
7447 23:08:41.569321 296 : 4250, 4026
7448 23:08:41.572435 300 : 4250, 4027
7449 23:08:41.572516 304 : 4252, 4030
7450 23:08:41.575965 308 : 4250, 3923
7451 23:08:41.576046 312 : 4250, 1858
7452 23:08:41.576111
7453 23:08:41.578824 MIOCK jitter meter ch=0
7454 23:08:41.578904
7455 23:08:41.582421 1T = (312-88) = 224 dly cells
7456 23:08:41.588676 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7457 23:08:41.588757 ==
7458 23:08:41.592430 Dram Type= 6, Freq= 0, CH_0, rank 0
7459 23:08:41.595393 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7460 23:08:41.595473 ==
7461 23:08:41.598863 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7462 23:08:41.606061 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7463 23:08:41.608684 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7464 23:08:41.615283 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7465 23:08:41.623851 [CA 0] Center 42 (12~73) winsize 62
7466 23:08:41.626970 [CA 1] Center 43 (12~74) winsize 63
7467 23:08:41.630447 [CA 2] Center 37 (8~67) winsize 60
7468 23:08:41.633821 [CA 3] Center 37 (7~67) winsize 61
7469 23:08:41.637006 [CA 4] Center 36 (6~66) winsize 61
7470 23:08:41.640824 [CA 5] Center 35 (6~64) winsize 59
7471 23:08:41.640904
7472 23:08:41.643876 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7473 23:08:41.643948
7474 23:08:41.647645 [CATrainingPosCal] consider 1 rank data
7475 23:08:41.650875 u2DelayCellTimex100 = 290/100 ps
7476 23:08:41.654467 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7477 23:08:41.660633 CA1 delay=43 (12~74),Diff = 8 PI (26 cell)
7478 23:08:41.663962 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7479 23:08:41.667321 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7480 23:08:41.670427 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7481 23:08:41.673820 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7482 23:08:41.673900
7483 23:08:41.677597 CA PerBit enable=1, Macro0, CA PI delay=35
7484 23:08:41.677677
7485 23:08:41.680490 [CBTSetCACLKResult] CA Dly = 35
7486 23:08:41.680569 CS Dly: 9 (0~40)
7487 23:08:41.687114 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7488 23:08:41.690552 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7489 23:08:41.690632 ==
7490 23:08:41.693974 Dram Type= 6, Freq= 0, CH_0, rank 1
7491 23:08:41.697057 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7492 23:08:41.697138 ==
7493 23:08:41.704002 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7494 23:08:41.707399 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7495 23:08:41.713493 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7496 23:08:41.717111 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7497 23:08:41.727413 [CA 0] Center 42 (12~73) winsize 62
7498 23:08:41.730748 [CA 1] Center 42 (12~73) winsize 62
7499 23:08:41.733528 [CA 2] Center 38 (8~68) winsize 61
7500 23:08:41.737035 [CA 3] Center 37 (8~67) winsize 60
7501 23:08:41.740682 [CA 4] Center 36 (6~66) winsize 61
7502 23:08:41.743508 [CA 5] Center 35 (5~65) winsize 61
7503 23:08:41.743588
7504 23:08:41.746914 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7505 23:08:41.746994
7506 23:08:41.750552 [CATrainingPosCal] consider 2 rank data
7507 23:08:41.753489 u2DelayCellTimex100 = 290/100 ps
7508 23:08:41.756990 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7509 23:08:41.763337 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7510 23:08:41.767088 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7511 23:08:41.770323 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7512 23:08:41.773830 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7513 23:08:41.777083 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7514 23:08:41.777163
7515 23:08:41.780182 CA PerBit enable=1, Macro0, CA PI delay=35
7516 23:08:41.780262
7517 23:08:41.783818 [CBTSetCACLKResult] CA Dly = 35
7518 23:08:41.787016 CS Dly: 10 (0~42)
7519 23:08:41.790231 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7520 23:08:41.793537 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7521 23:08:41.793654
7522 23:08:41.796772 ----->DramcWriteLeveling(PI) begin...
7523 23:08:41.796868 ==
7524 23:08:41.800019 Dram Type= 6, Freq= 0, CH_0, rank 0
7525 23:08:41.806541 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7526 23:08:41.806623 ==
7527 23:08:41.809868 Write leveling (Byte 0): 34 => 34
7528 23:08:41.809949 Write leveling (Byte 1): 29 => 29
7529 23:08:41.813485 DramcWriteLeveling(PI) end<-----
7530 23:08:41.813584
7531 23:08:41.813707 ==
7532 23:08:41.816453 Dram Type= 6, Freq= 0, CH_0, rank 0
7533 23:08:41.823595 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7534 23:08:41.823679 ==
7535 23:08:41.826334 [Gating] SW mode calibration
7536 23:08:41.833201 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7537 23:08:41.836661 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7538 23:08:41.843035 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7539 23:08:41.846619 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7540 23:08:41.850147 1 4 8 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
7541 23:08:41.856624 1 4 12 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
7542 23:08:41.859740 1 4 16 | B1->B0 | 2626 3535 | 0 1 | (0 0) (1 1)
7543 23:08:41.863128 1 4 20 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
7544 23:08:41.869420 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7545 23:08:41.873125 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7546 23:08:41.876216 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7547 23:08:41.883141 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7548 23:08:41.886434 1 5 8 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7549 23:08:41.889519 1 5 12 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
7550 23:08:41.893075 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7551 23:08:41.899538 1 5 20 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
7552 23:08:41.903264 1 5 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7553 23:08:41.906208 1 5 28 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
7554 23:08:41.913329 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7555 23:08:41.916030 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7556 23:08:41.919745 1 6 8 | B1->B0 | 2323 3737 | 0 1 | (0 0) (0 0)
7557 23:08:41.926226 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7558 23:08:41.929985 1 6 16 | B1->B0 | 2e2e 4646 | 0 1 | (0 0) (0 0)
7559 23:08:41.932887 1 6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7560 23:08:41.939997 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7561 23:08:41.943031 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7562 23:08:41.946314 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7563 23:08:41.952651 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7564 23:08:41.956110 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7565 23:08:41.959513 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7566 23:08:41.965844 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7567 23:08:41.969379 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7568 23:08:41.973119 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7569 23:08:41.979564 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7570 23:08:41.982473 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7571 23:08:41.986094 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7572 23:08:41.992231 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7573 23:08:41.995700 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7574 23:08:41.998934 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7575 23:08:42.005940 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7576 23:08:42.009106 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7577 23:08:42.012612 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7578 23:08:42.019135 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7579 23:08:42.022593 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7580 23:08:42.025858 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7581 23:08:42.032268 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7582 23:08:42.036037 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7583 23:08:42.038657 Total UI for P1: 0, mck2ui 16
7584 23:08:42.042317 best dqsien dly found for B0: ( 1, 9, 12)
7585 23:08:42.045493 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7586 23:08:42.049131 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7587 23:08:42.052158 Total UI for P1: 0, mck2ui 16
7588 23:08:42.055731 best dqsien dly found for B1: ( 1, 9, 20)
7589 23:08:42.058789 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7590 23:08:42.065506 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7591 23:08:42.065647
7592 23:08:42.068830 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7593 23:08:42.072294 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7594 23:08:42.075283 [Gating] SW calibration Done
7595 23:08:42.075363 ==
7596 23:08:42.078882 Dram Type= 6, Freq= 0, CH_0, rank 0
7597 23:08:42.082036 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7598 23:08:42.082116 ==
7599 23:08:42.085616 RX Vref Scan: 0
7600 23:08:42.085709
7601 23:08:42.085773 RX Vref 0 -> 0, step: 1
7602 23:08:42.085832
7603 23:08:42.088962 RX Delay 0 -> 252, step: 8
7604 23:08:42.091983 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7605 23:08:42.095631 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7606 23:08:42.102119 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7607 23:08:42.105528 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7608 23:08:42.108595 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7609 23:08:42.112283 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7610 23:08:42.115415 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7611 23:08:42.121833 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7612 23:08:42.125135 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7613 23:08:42.128851 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
7614 23:08:42.131993 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7615 23:08:42.135038 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7616 23:08:42.142193 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
7617 23:08:42.145425 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
7618 23:08:42.148698 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7619 23:08:42.152207 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7620 23:08:42.152286 ==
7621 23:08:42.155297 Dram Type= 6, Freq= 0, CH_0, rank 0
7622 23:08:42.161931 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7623 23:08:42.162011 ==
7624 23:08:42.162075 DQS Delay:
7625 23:08:42.162133 DQS0 = 0, DQS1 = 0
7626 23:08:42.165257 DQM Delay:
7627 23:08:42.165336 DQM0 = 137, DQM1 = 131
7628 23:08:42.168390 DQ Delay:
7629 23:08:42.171863 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =131
7630 23:08:42.175290 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7631 23:08:42.178778 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =123
7632 23:08:42.182165 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =135
7633 23:08:42.182245
7634 23:08:42.182307
7635 23:08:42.182366 ==
7636 23:08:42.184859 Dram Type= 6, Freq= 0, CH_0, rank 0
7637 23:08:42.188308 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7638 23:08:42.191928 ==
7639 23:08:42.192007
7640 23:08:42.192068
7641 23:08:42.192126 TX Vref Scan disable
7642 23:08:42.194960 == TX Byte 0 ==
7643 23:08:42.198501 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7644 23:08:42.201685 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7645 23:08:42.204846 == TX Byte 1 ==
7646 23:08:42.208599 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7647 23:08:42.211671 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7648 23:08:42.211751 ==
7649 23:08:42.215187 Dram Type= 6, Freq= 0, CH_0, rank 0
7650 23:08:42.221848 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7651 23:08:42.221929 ==
7652 23:08:42.233936
7653 23:08:42.237418 TX Vref early break, caculate TX vref
7654 23:08:42.240683 TX Vref=16, minBit 0, minWin=22, winSum=379
7655 23:08:42.244000 TX Vref=18, minBit 1, minWin=23, winSum=388
7656 23:08:42.247193 TX Vref=20, minBit 1, minWin=24, winSum=400
7657 23:08:42.251072 TX Vref=22, minBit 7, minWin=24, winSum=407
7658 23:08:42.253994 TX Vref=24, minBit 1, minWin=25, winSum=420
7659 23:08:42.260422 TX Vref=26, minBit 7, minWin=25, winSum=426
7660 23:08:42.263747 TX Vref=28, minBit 1, minWin=25, winSum=427
7661 23:08:42.267618 TX Vref=30, minBit 6, minWin=24, winSum=415
7662 23:08:42.270186 TX Vref=32, minBit 6, minWin=24, winSum=409
7663 23:08:42.273681 TX Vref=34, minBit 1, minWin=23, winSum=396
7664 23:08:42.280279 [TxChooseVref] Worse bit 1, Min win 25, Win sum 427, Final Vref 28
7665 23:08:42.280360
7666 23:08:42.283598 Final TX Range 0 Vref 28
7667 23:08:42.283678
7668 23:08:42.283741 ==
7669 23:08:42.286903 Dram Type= 6, Freq= 0, CH_0, rank 0
7670 23:08:42.290340 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7671 23:08:42.290421 ==
7672 23:08:42.290485
7673 23:08:42.290544
7674 23:08:42.293573 TX Vref Scan disable
7675 23:08:42.300785 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7676 23:08:42.300866 == TX Byte 0 ==
7677 23:08:42.303688 u2DelayCellOfst[0]=13 cells (4 PI)
7678 23:08:42.306951 u2DelayCellOfst[1]=13 cells (4 PI)
7679 23:08:42.310401 u2DelayCellOfst[2]=10 cells (3 PI)
7680 23:08:42.313714 u2DelayCellOfst[3]=10 cells (3 PI)
7681 23:08:42.317102 u2DelayCellOfst[4]=6 cells (2 PI)
7682 23:08:42.320212 u2DelayCellOfst[5]=0 cells (0 PI)
7683 23:08:42.323495 u2DelayCellOfst[6]=16 cells (5 PI)
7684 23:08:42.327070 u2DelayCellOfst[7]=16 cells (5 PI)
7685 23:08:42.330124 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7686 23:08:42.333902 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7687 23:08:42.336920 == TX Byte 1 ==
7688 23:08:42.336999 u2DelayCellOfst[8]=0 cells (0 PI)
7689 23:08:42.340419 u2DelayCellOfst[9]=3 cells (1 PI)
7690 23:08:42.343653 u2DelayCellOfst[10]=6 cells (2 PI)
7691 23:08:42.346919 u2DelayCellOfst[11]=6 cells (2 PI)
7692 23:08:42.350284 u2DelayCellOfst[12]=13 cells (4 PI)
7693 23:08:42.353839 u2DelayCellOfst[13]=10 cells (3 PI)
7694 23:08:42.356738 u2DelayCellOfst[14]=13 cells (4 PI)
7695 23:08:42.360266 u2DelayCellOfst[15]=10 cells (3 PI)
7696 23:08:42.363241 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7697 23:08:42.370089 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7698 23:08:42.370170 DramC Write-DBI on
7699 23:08:42.370234 ==
7700 23:08:42.373316 Dram Type= 6, Freq= 0, CH_0, rank 0
7701 23:08:42.376442 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7702 23:08:42.379974 ==
7703 23:08:42.380054
7704 23:08:42.380117
7705 23:08:42.380175 TX Vref Scan disable
7706 23:08:42.383390 == TX Byte 0 ==
7707 23:08:42.386670 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7708 23:08:42.390420 == TX Byte 1 ==
7709 23:08:42.393582 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7710 23:08:42.396965 DramC Write-DBI off
7711 23:08:42.397060
7712 23:08:42.397150 [DATLAT]
7713 23:08:42.397227 Freq=1600, CH0 RK0
7714 23:08:42.397285
7715 23:08:42.399991 DATLAT Default: 0xf
7716 23:08:42.400114 0, 0xFFFF, sum = 0
7717 23:08:42.403277 1, 0xFFFF, sum = 0
7718 23:08:42.406698 2, 0xFFFF, sum = 0
7719 23:08:42.406779 3, 0xFFFF, sum = 0
7720 23:08:42.410095 4, 0xFFFF, sum = 0
7721 23:08:42.410177 5, 0xFFFF, sum = 0
7722 23:08:42.413438 6, 0xFFFF, sum = 0
7723 23:08:42.413550 7, 0xFFFF, sum = 0
7724 23:08:42.416608 8, 0xFFFF, sum = 0
7725 23:08:42.416692 9, 0xFFFF, sum = 0
7726 23:08:42.420225 10, 0xFFFF, sum = 0
7727 23:08:42.420334 11, 0xFFFF, sum = 0
7728 23:08:42.423398 12, 0xFFFF, sum = 0
7729 23:08:42.423479 13, 0xFFFF, sum = 0
7730 23:08:42.426229 14, 0x0, sum = 1
7731 23:08:42.426312 15, 0x0, sum = 2
7732 23:08:42.430006 16, 0x0, sum = 3
7733 23:08:42.430102 17, 0x0, sum = 4
7734 23:08:42.433212 best_step = 15
7735 23:08:42.433293
7736 23:08:42.433363 ==
7737 23:08:42.436249 Dram Type= 6, Freq= 0, CH_0, rank 0
7738 23:08:42.440066 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7739 23:08:42.440148 ==
7740 23:08:42.442988 RX Vref Scan: 1
7741 23:08:42.443068
7742 23:08:42.443139 Set Vref Range= 24 -> 127
7743 23:08:42.443201
7744 23:08:42.446355 RX Vref 24 -> 127, step: 1
7745 23:08:42.446437
7746 23:08:42.449914 RX Delay 27 -> 252, step: 4
7747 23:08:42.449995
7748 23:08:42.453341 Set Vref, RX VrefLevel [Byte0]: 24
7749 23:08:42.456709 [Byte1]: 24
7750 23:08:42.456789
7751 23:08:42.459667 Set Vref, RX VrefLevel [Byte0]: 25
7752 23:08:42.463405 [Byte1]: 25
7753 23:08:42.463486
7754 23:08:42.466557 Set Vref, RX VrefLevel [Byte0]: 26
7755 23:08:42.470080 [Byte1]: 26
7756 23:08:42.473387
7757 23:08:42.473468 Set Vref, RX VrefLevel [Byte0]: 27
7758 23:08:42.477184 [Byte1]: 27
7759 23:08:42.481002
7760 23:08:42.481111 Set Vref, RX VrefLevel [Byte0]: 28
7761 23:08:42.484462 [Byte1]: 28
7762 23:08:42.488389
7763 23:08:42.488469 Set Vref, RX VrefLevel [Byte0]: 29
7764 23:08:42.491973 [Byte1]: 29
7765 23:08:42.496332
7766 23:08:42.496412 Set Vref, RX VrefLevel [Byte0]: 30
7767 23:08:42.499448 [Byte1]: 30
7768 23:08:42.503901
7769 23:08:42.503980 Set Vref, RX VrefLevel [Byte0]: 31
7770 23:08:42.507069 [Byte1]: 31
7771 23:08:42.511524
7772 23:08:42.511604 Set Vref, RX VrefLevel [Byte0]: 32
7773 23:08:42.514265 [Byte1]: 32
7774 23:08:42.518912
7775 23:08:42.518993 Set Vref, RX VrefLevel [Byte0]: 33
7776 23:08:42.521981 [Byte1]: 33
7777 23:08:42.526470
7778 23:08:42.526549 Set Vref, RX VrefLevel [Byte0]: 34
7779 23:08:42.529841 [Byte1]: 34
7780 23:08:42.534025
7781 23:08:42.534104 Set Vref, RX VrefLevel [Byte0]: 35
7782 23:08:42.537404 [Byte1]: 35
7783 23:08:42.541311
7784 23:08:42.541390 Set Vref, RX VrefLevel [Byte0]: 36
7785 23:08:42.545034 [Byte1]: 36
7786 23:08:42.548734
7787 23:08:42.548813 Set Vref, RX VrefLevel [Byte0]: 37
7788 23:08:42.552203 [Byte1]: 37
7789 23:08:42.556325
7790 23:08:42.556403 Set Vref, RX VrefLevel [Byte0]: 38
7791 23:08:42.559519 [Byte1]: 38
7792 23:08:42.564006
7793 23:08:42.564112 Set Vref, RX VrefLevel [Byte0]: 39
7794 23:08:42.567651 [Byte1]: 39
7795 23:08:42.571370
7796 23:08:42.571449 Set Vref, RX VrefLevel [Byte0]: 40
7797 23:08:42.574814 [Byte1]: 40
7798 23:08:42.578853
7799 23:08:42.578932 Set Vref, RX VrefLevel [Byte0]: 41
7800 23:08:42.582271 [Byte1]: 41
7801 23:08:42.586915
7802 23:08:42.586994 Set Vref, RX VrefLevel [Byte0]: 42
7803 23:08:42.589584 [Byte1]: 42
7804 23:08:42.594397
7805 23:08:42.594476 Set Vref, RX VrefLevel [Byte0]: 43
7806 23:08:42.597372 [Byte1]: 43
7807 23:08:42.601542
7808 23:08:42.601670 Set Vref, RX VrefLevel [Byte0]: 44
7809 23:08:42.604826 [Byte1]: 44
7810 23:08:42.609261
7811 23:08:42.609341 Set Vref, RX VrefLevel [Byte0]: 45
7812 23:08:42.612602 [Byte1]: 45
7813 23:08:42.617253
7814 23:08:42.617361 Set Vref, RX VrefLevel [Byte0]: 46
7815 23:08:42.619833 [Byte1]: 46
7816 23:08:42.624197
7817 23:08:42.624276 Set Vref, RX VrefLevel [Byte0]: 47
7818 23:08:42.627388 [Byte1]: 47
7819 23:08:42.631585
7820 23:08:42.631670 Set Vref, RX VrefLevel [Byte0]: 48
7821 23:08:42.635379 [Byte1]: 48
7822 23:08:42.639415
7823 23:08:42.639494 Set Vref, RX VrefLevel [Byte0]: 49
7824 23:08:42.642858 [Byte1]: 49
7825 23:08:42.646924
7826 23:08:42.647003 Set Vref, RX VrefLevel [Byte0]: 50
7827 23:08:42.649984 [Byte1]: 50
7828 23:08:42.654885
7829 23:08:42.654963 Set Vref, RX VrefLevel [Byte0]: 51
7830 23:08:42.657528 [Byte1]: 51
7831 23:08:42.662189
7832 23:08:42.662267 Set Vref, RX VrefLevel [Byte0]: 52
7833 23:08:42.665468 [Byte1]: 52
7834 23:08:42.669546
7835 23:08:42.669668 Set Vref, RX VrefLevel [Byte0]: 53
7836 23:08:42.673091 [Byte1]: 53
7837 23:08:42.677211
7838 23:08:42.677294 Set Vref, RX VrefLevel [Byte0]: 54
7839 23:08:42.680370 [Byte1]: 54
7840 23:08:42.684242
7841 23:08:42.684320 Set Vref, RX VrefLevel [Byte0]: 55
7842 23:08:42.688068 [Byte1]: 55
7843 23:08:42.692002
7844 23:08:42.692080 Set Vref, RX VrefLevel [Byte0]: 56
7845 23:08:42.695458 [Byte1]: 56
7846 23:08:42.699722
7847 23:08:42.699801 Set Vref, RX VrefLevel [Byte0]: 57
7848 23:08:42.702768 [Byte1]: 57
7849 23:08:42.707331
7850 23:08:42.707410 Set Vref, RX VrefLevel [Byte0]: 58
7851 23:08:42.710145 [Byte1]: 58
7852 23:08:42.714600
7853 23:08:42.714705 Set Vref, RX VrefLevel [Byte0]: 59
7854 23:08:42.717548 [Byte1]: 59
7855 23:08:42.722274
7856 23:08:42.722354 Set Vref, RX VrefLevel [Byte0]: 60
7857 23:08:42.725523 [Byte1]: 60
7858 23:08:42.729451
7859 23:08:42.729557 Set Vref, RX VrefLevel [Byte0]: 61
7860 23:08:42.733349 [Byte1]: 61
7861 23:08:42.737422
7862 23:08:42.737528 Set Vref, RX VrefLevel [Byte0]: 62
7863 23:08:42.740364 [Byte1]: 62
7864 23:08:42.744856
7865 23:08:42.744935 Set Vref, RX VrefLevel [Byte0]: 63
7866 23:08:42.747931 [Byte1]: 63
7867 23:08:42.752336
7868 23:08:42.752416 Set Vref, RX VrefLevel [Byte0]: 64
7869 23:08:42.755268 [Byte1]: 64
7870 23:08:42.759601
7871 23:08:42.759679 Set Vref, RX VrefLevel [Byte0]: 65
7872 23:08:42.763212 [Byte1]: 65
7873 23:08:42.767320
7874 23:08:42.767401 Set Vref, RX VrefLevel [Byte0]: 66
7875 23:08:42.770663 [Byte1]: 66
7876 23:08:42.774889
7877 23:08:42.774967 Set Vref, RX VrefLevel [Byte0]: 67
7878 23:08:42.778465 [Byte1]: 67
7879 23:08:42.782520
7880 23:08:42.782599 Set Vref, RX VrefLevel [Byte0]: 68
7881 23:08:42.785749 [Byte1]: 68
7882 23:08:42.790153
7883 23:08:42.790232 Set Vref, RX VrefLevel [Byte0]: 69
7884 23:08:42.793492 [Byte1]: 69
7885 23:08:42.797464
7886 23:08:42.797569 Set Vref, RX VrefLevel [Byte0]: 70
7887 23:08:42.800531 [Byte1]: 70
7888 23:08:42.804886
7889 23:08:42.804965 Set Vref, RX VrefLevel [Byte0]: 71
7890 23:08:42.808641 [Byte1]: 71
7891 23:08:42.812555
7892 23:08:42.812635 Set Vref, RX VrefLevel [Byte0]: 72
7893 23:08:42.815708 [Byte1]: 72
7894 23:08:42.820184
7895 23:08:42.820268 Final RX Vref Byte 0 = 58 to rank0
7896 23:08:42.823101 Final RX Vref Byte 1 = 62 to rank0
7897 23:08:42.826457 Final RX Vref Byte 0 = 58 to rank1
7898 23:08:42.830010 Final RX Vref Byte 1 = 62 to rank1==
7899 23:08:42.833181 Dram Type= 6, Freq= 0, CH_0, rank 0
7900 23:08:42.840227 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7901 23:08:42.840308 ==
7902 23:08:42.840372 DQS Delay:
7903 23:08:42.840431 DQS0 = 0, DQS1 = 0
7904 23:08:42.843537 DQM Delay:
7905 23:08:42.843616 DQM0 = 135, DQM1 = 127
7906 23:08:42.846766 DQ Delay:
7907 23:08:42.849862 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =134
7908 23:08:42.853405 DQ4 =134, DQ5 =124, DQ6 =142, DQ7 =140
7909 23:08:42.856241 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =120
7910 23:08:42.859638 DQ12 =132, DQ13 =132, DQ14 =138, DQ15 =136
7911 23:08:42.859718
7912 23:08:42.859781
7913 23:08:42.859839
7914 23:08:42.863376 [DramC_TX_OE_Calibration] TA2
7915 23:08:42.866200 Original DQ_B0 (3 6) =30, OEN = 27
7916 23:08:42.869495 Original DQ_B1 (3 6) =30, OEN = 27
7917 23:08:42.872998 24, 0x0, End_B0=24 End_B1=24
7918 23:08:42.873078 25, 0x0, End_B0=25 End_B1=25
7919 23:08:42.876509 26, 0x0, End_B0=26 End_B1=26
7920 23:08:42.879937 27, 0x0, End_B0=27 End_B1=27
7921 23:08:42.883045 28, 0x0, End_B0=28 End_B1=28
7922 23:08:42.886577 29, 0x0, End_B0=29 End_B1=29
7923 23:08:42.886658 30, 0x0, End_B0=30 End_B1=30
7924 23:08:42.889537 31, 0x4141, End_B0=30 End_B1=30
7925 23:08:42.893223 Byte0 end_step=30 best_step=27
7926 23:08:42.896739 Byte1 end_step=30 best_step=27
7927 23:08:42.899860 Byte0 TX OE(2T, 0.5T) = (3, 3)
7928 23:08:42.899939 Byte1 TX OE(2T, 0.5T) = (3, 3)
7929 23:08:42.903358
7930 23:08:42.903437
7931 23:08:42.910018 [DQSOSCAuto] RK0, (LSB)MR18= 0x241f, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 391 ps
7932 23:08:42.913160 CH0 RK0: MR19=303, MR18=241F
7933 23:08:42.919561 CH0_RK0: MR19=0x303, MR18=0x241F, DQSOSC=391, MR23=63, INC=24, DEC=16
7934 23:08:42.919646
7935 23:08:42.922785 ----->DramcWriteLeveling(PI) begin...
7936 23:08:42.922866 ==
7937 23:08:42.926317 Dram Type= 6, Freq= 0, CH_0, rank 1
7938 23:08:42.929829 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7939 23:08:42.929910 ==
7940 23:08:42.932792 Write leveling (Byte 0): 35 => 35
7941 23:08:42.936422 Write leveling (Byte 1): 24 => 24
7942 23:08:42.939736 DramcWriteLeveling(PI) end<-----
7943 23:08:42.939815
7944 23:08:42.939908 ==
7945 23:08:42.942719 Dram Type= 6, Freq= 0, CH_0, rank 1
7946 23:08:42.946120 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7947 23:08:42.946224 ==
7948 23:08:42.949731 [Gating] SW mode calibration
7949 23:08:42.955863 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7950 23:08:42.962526 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7951 23:08:42.965793 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7952 23:08:42.969389 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7953 23:08:42.976411 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7954 23:08:42.979075 1 4 12 | B1->B0 | 2323 2828 | 0 1 | (0 0) (1 1)
7955 23:08:42.982452 1 4 16 | B1->B0 | 2c2c 3434 | 1 1 | (1 1) (1 1)
7956 23:08:42.989098 1 4 20 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
7957 23:08:42.992891 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7958 23:08:42.996104 1 4 28 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7959 23:08:43.002602 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7960 23:08:43.005988 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7961 23:08:43.009548 1 5 8 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
7962 23:08:43.015474 1 5 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
7963 23:08:43.019232 1 5 16 | B1->B0 | 2b2b 2726 | 0 1 | (1 0) (0 0)
7964 23:08:43.022637 1 5 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7965 23:08:43.028968 1 5 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7966 23:08:43.032265 1 5 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7967 23:08:43.035687 1 6 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7968 23:08:43.042044 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7969 23:08:43.045380 1 6 8 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
7970 23:08:43.048931 1 6 12 | B1->B0 | 2424 3636 | 0 0 | (0 0) (0 0)
7971 23:08:43.055200 1 6 16 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
7972 23:08:43.058654 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7973 23:08:43.061949 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7974 23:08:43.068803 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7975 23:08:43.072052 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7976 23:08:43.075278 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7977 23:08:43.082079 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7978 23:08:43.085349 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7979 23:08:43.088261 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
7980 23:08:43.095201 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7981 23:08:43.098457 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7982 23:08:43.101503 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7983 23:08:43.108386 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7984 23:08:43.112000 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7985 23:08:43.115116 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7986 23:08:43.121715 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7987 23:08:43.124924 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7988 23:08:43.128080 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7989 23:08:43.135042 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7990 23:08:43.138688 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7991 23:08:43.141785 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7992 23:08:43.148198 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7993 23:08:43.151795 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7994 23:08:43.155216 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7995 23:08:43.161244 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7996 23:08:43.164647 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7997 23:08:43.168172 Total UI for P1: 0, mck2ui 16
7998 23:08:43.171410 best dqsien dly found for B0: ( 1, 9, 14)
7999 23:08:43.175111 Total UI for P1: 0, mck2ui 16
8000 23:08:43.178089 best dqsien dly found for B1: ( 1, 9, 14)
8001 23:08:43.181401 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8002 23:08:43.184910 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8003 23:08:43.184989
8004 23:08:43.187648 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8005 23:08:43.191190 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8006 23:08:43.194537 [Gating] SW calibration Done
8007 23:08:43.194616 ==
8008 23:08:43.197592 Dram Type= 6, Freq= 0, CH_0, rank 1
8009 23:08:43.200974 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8010 23:08:43.204985 ==
8011 23:08:43.205065 RX Vref Scan: 0
8012 23:08:43.205130
8013 23:08:43.207640 RX Vref 0 -> 0, step: 1
8014 23:08:43.207719
8015 23:08:43.207782 RX Delay 0 -> 252, step: 8
8016 23:08:43.214175 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8017 23:08:43.217736 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8018 23:08:43.220923 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8019 23:08:43.224532 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8020 23:08:43.227523 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8021 23:08:43.234205 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8022 23:08:43.237490 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8023 23:08:43.241145 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8024 23:08:43.243999 iDelay=200, Bit 8, Center 123 (72 ~ 175) 104
8025 23:08:43.247656 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8026 23:08:43.254355 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8027 23:08:43.257506 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8028 23:08:43.261055 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8029 23:08:43.264163 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8030 23:08:43.267344 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8031 23:08:43.274540 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8032 23:08:43.274621 ==
8033 23:08:43.279100 Dram Type= 6, Freq= 0, CH_0, rank 1
8034 23:08:43.281063 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8035 23:08:43.281143 ==
8036 23:08:43.281206 DQS Delay:
8037 23:08:43.284142 DQS0 = 0, DQS1 = 0
8038 23:08:43.284221 DQM Delay:
8039 23:08:43.287359 DQM0 = 136, DQM1 = 130
8040 23:08:43.287437 DQ Delay:
8041 23:08:43.290616 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8042 23:08:43.294205 DQ4 =139, DQ5 =127, DQ6 =139, DQ7 =143
8043 23:08:43.297609 DQ8 =123, DQ9 =119, DQ10 =127, DQ11 =123
8044 23:08:43.300639 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =139
8045 23:08:43.304306
8046 23:08:43.304384
8047 23:08:43.304446 ==
8048 23:08:43.307459 Dram Type= 6, Freq= 0, CH_0, rank 1
8049 23:08:43.310772 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8050 23:08:43.310855 ==
8051 23:08:43.310918
8052 23:08:43.310977
8053 23:08:43.314110 TX Vref Scan disable
8054 23:08:43.314189 == TX Byte 0 ==
8055 23:08:43.320354 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8056 23:08:43.324090 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8057 23:08:43.324170 == TX Byte 1 ==
8058 23:08:43.330786 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8059 23:08:43.333794 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8060 23:08:43.333873 ==
8061 23:08:43.337230 Dram Type= 6, Freq= 0, CH_0, rank 1
8062 23:08:43.340513 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8063 23:08:43.340593 ==
8064 23:08:43.355566
8065 23:08:43.359088 TX Vref early break, caculate TX vref
8066 23:08:43.361950 TX Vref=16, minBit 1, minWin=23, winSum=387
8067 23:08:43.365356 TX Vref=18, minBit 0, minWin=24, winSum=394
8068 23:08:43.368660 TX Vref=20, minBit 1, minWin=23, winSum=405
8069 23:08:43.372222 TX Vref=22, minBit 1, minWin=24, winSum=410
8070 23:08:43.375350 TX Vref=24, minBit 1, minWin=25, winSum=418
8071 23:08:43.382246 TX Vref=26, minBit 1, minWin=25, winSum=426
8072 23:08:43.385213 TX Vref=28, minBit 4, minWin=25, winSum=425
8073 23:08:43.389108 TX Vref=30, minBit 0, minWin=25, winSum=419
8074 23:08:43.392439 TX Vref=32, minBit 0, minWin=25, winSum=411
8075 23:08:43.395269 TX Vref=34, minBit 1, minWin=23, winSum=403
8076 23:08:43.401813 [TxChooseVref] Worse bit 1, Min win 25, Win sum 426, Final Vref 26
8077 23:08:43.401892
8078 23:08:43.405535 Final TX Range 0 Vref 26
8079 23:08:43.405633
8080 23:08:43.405697 ==
8081 23:08:43.408707 Dram Type= 6, Freq= 0, CH_0, rank 1
8082 23:08:43.411937 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8083 23:08:43.412017 ==
8084 23:08:43.412080
8085 23:08:43.412139
8086 23:08:43.415397 TX Vref Scan disable
8087 23:08:43.422455 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8088 23:08:43.422537 == TX Byte 0 ==
8089 23:08:43.425495 u2DelayCellOfst[0]=13 cells (4 PI)
8090 23:08:43.428754 u2DelayCellOfst[1]=13 cells (4 PI)
8091 23:08:43.431995 u2DelayCellOfst[2]=10 cells (3 PI)
8092 23:08:43.435244 u2DelayCellOfst[3]=10 cells (3 PI)
8093 23:08:43.438638 u2DelayCellOfst[4]=6 cells (2 PI)
8094 23:08:43.442289 u2DelayCellOfst[5]=0 cells (0 PI)
8095 23:08:43.445650 u2DelayCellOfst[6]=16 cells (5 PI)
8096 23:08:43.445731 u2DelayCellOfst[7]=16 cells (5 PI)
8097 23:08:43.452133 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8098 23:08:43.455427 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8099 23:08:43.455508 == TX Byte 1 ==
8100 23:08:43.458683 u2DelayCellOfst[8]=3 cells (1 PI)
8101 23:08:43.462115 u2DelayCellOfst[9]=0 cells (0 PI)
8102 23:08:43.464963 u2DelayCellOfst[10]=6 cells (2 PI)
8103 23:08:43.468958 u2DelayCellOfst[11]=6 cells (2 PI)
8104 23:08:43.471890 u2DelayCellOfst[12]=10 cells (3 PI)
8105 23:08:43.475399 u2DelayCellOfst[13]=10 cells (3 PI)
8106 23:08:43.478572 u2DelayCellOfst[14]=13 cells (4 PI)
8107 23:08:43.482066 u2DelayCellOfst[15]=10 cells (3 PI)
8108 23:08:43.485102 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8109 23:08:43.491960 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8110 23:08:43.492041 DramC Write-DBI on
8111 23:08:43.492105 ==
8112 23:08:43.495236 Dram Type= 6, Freq= 0, CH_0, rank 1
8113 23:08:43.498571 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8114 23:08:43.501912 ==
8115 23:08:43.502018
8116 23:08:43.502108
8117 23:08:43.502197 TX Vref Scan disable
8118 23:08:43.505178 == TX Byte 0 ==
8119 23:08:43.508162 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8120 23:08:43.512362 == TX Byte 1 ==
8121 23:08:43.515158 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
8122 23:08:43.519135 DramC Write-DBI off
8123 23:08:43.519219
8124 23:08:43.519303 [DATLAT]
8125 23:08:43.519383 Freq=1600, CH0 RK1
8126 23:08:43.519461
8127 23:08:43.521742 DATLAT Default: 0xf
8128 23:08:43.521825 0, 0xFFFF, sum = 0
8129 23:08:43.525026 1, 0xFFFF, sum = 0
8130 23:08:43.525126 2, 0xFFFF, sum = 0
8131 23:08:43.528490 3, 0xFFFF, sum = 0
8132 23:08:43.531938 4, 0xFFFF, sum = 0
8133 23:08:43.532023 5, 0xFFFF, sum = 0
8134 23:08:43.535399 6, 0xFFFF, sum = 0
8135 23:08:43.535483 7, 0xFFFF, sum = 0
8136 23:08:43.538395 8, 0xFFFF, sum = 0
8137 23:08:43.538501 9, 0xFFFF, sum = 0
8138 23:08:43.541866 10, 0xFFFF, sum = 0
8139 23:08:43.541949 11, 0xFFFF, sum = 0
8140 23:08:43.544985 12, 0xFFFF, sum = 0
8141 23:08:43.545069 13, 0xFFFF, sum = 0
8142 23:08:43.548447 14, 0x0, sum = 1
8143 23:08:43.548531 15, 0x0, sum = 2
8144 23:08:43.551146 16, 0x0, sum = 3
8145 23:08:43.551231 17, 0x0, sum = 4
8146 23:08:43.554682 best_step = 15
8147 23:08:43.554764
8148 23:08:43.554849 ==
8149 23:08:43.558374 Dram Type= 6, Freq= 0, CH_0, rank 1
8150 23:08:43.561546 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8151 23:08:43.561669 ==
8152 23:08:43.564687 RX Vref Scan: 0
8153 23:08:43.564769
8154 23:08:43.564854 RX Vref 0 -> 0, step: 1
8155 23:08:43.564934
8156 23:08:43.568299 RX Delay 19 -> 252, step: 4
8157 23:08:43.571224 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8158 23:08:43.577795 iDelay=191, Bit 1, Center 136 (91 ~ 182) 92
8159 23:08:43.581374 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8160 23:08:43.584824 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8161 23:08:43.587927 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8162 23:08:43.591525 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8163 23:08:43.598022 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
8164 23:08:43.600908 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8165 23:08:43.604426 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8166 23:08:43.607718 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8167 23:08:43.610729 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8168 23:08:43.617914 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8169 23:08:43.620951 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8170 23:08:43.624613 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8171 23:08:43.628153 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8172 23:08:43.634514 iDelay=191, Bit 15, Center 136 (87 ~ 186) 100
8173 23:08:43.634597 ==
8174 23:08:43.638026 Dram Type= 6, Freq= 0, CH_0, rank 1
8175 23:08:43.640873 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8176 23:08:43.640955 ==
8177 23:08:43.641039 DQS Delay:
8178 23:08:43.644525 DQS0 = 0, DQS1 = 0
8179 23:08:43.644612 DQM Delay:
8180 23:08:43.648018 DQM0 = 134, DQM1 = 127
8181 23:08:43.648101 DQ Delay:
8182 23:08:43.651471 DQ0 =134, DQ1 =136, DQ2 =130, DQ3 =134
8183 23:08:43.654326 DQ4 =136, DQ5 =124, DQ6 =138, DQ7 =140
8184 23:08:43.658027 DQ8 =118, DQ9 =116, DQ10 =128, DQ11 =118
8185 23:08:43.661051 DQ12 =134, DQ13 =134, DQ14 =134, DQ15 =136
8186 23:08:43.661134
8187 23:08:43.661217
8188 23:08:43.661297
8189 23:08:43.664550 [DramC_TX_OE_Calibration] TA2
8190 23:08:43.667670 Original DQ_B0 (3 6) =30, OEN = 27
8191 23:08:43.671101 Original DQ_B1 (3 6) =30, OEN = 27
8192 23:08:43.674688 24, 0x0, End_B0=24 End_B1=24
8193 23:08:43.677817 25, 0x0, End_B0=25 End_B1=25
8194 23:08:43.677901 26, 0x0, End_B0=26 End_B1=26
8195 23:08:43.680932 27, 0x0, End_B0=27 End_B1=27
8196 23:08:43.684385 28, 0x0, End_B0=28 End_B1=28
8197 23:08:43.687531 29, 0x0, End_B0=29 End_B1=29
8198 23:08:43.690862 30, 0x0, End_B0=30 End_B1=30
8199 23:08:43.690946 31, 0x5151, End_B0=30 End_B1=30
8200 23:08:43.694545 Byte0 end_step=30 best_step=27
8201 23:08:43.697856 Byte1 end_step=30 best_step=27
8202 23:08:43.700823 Byte0 TX OE(2T, 0.5T) = (3, 3)
8203 23:08:43.704575 Byte1 TX OE(2T, 0.5T) = (3, 3)
8204 23:08:43.704658
8205 23:08:43.704742
8206 23:08:43.711345 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f07, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 394 ps
8207 23:08:43.713897 CH0 RK1: MR19=303, MR18=1F07
8208 23:08:43.720695 CH0_RK1: MR19=0x303, MR18=0x1F07, DQSOSC=394, MR23=63, INC=23, DEC=15
8209 23:08:43.724090 [RxdqsGatingPostProcess] freq 1600
8210 23:08:43.730723 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8211 23:08:43.730805 best DQS0 dly(2T, 0.5T) = (1, 1)
8212 23:08:43.733969 best DQS1 dly(2T, 0.5T) = (1, 1)
8213 23:08:43.737197 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8214 23:08:43.740782 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8215 23:08:43.743889 best DQS0 dly(2T, 0.5T) = (1, 1)
8216 23:08:43.747571 best DQS1 dly(2T, 0.5T) = (1, 1)
8217 23:08:43.750596 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8218 23:08:43.754012 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8219 23:08:43.757140 Pre-setting of DQS Precalculation
8220 23:08:43.761040 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8221 23:08:43.761120 ==
8222 23:08:43.764048 Dram Type= 6, Freq= 0, CH_1, rank 0
8223 23:08:43.770654 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8224 23:08:43.770738 ==
8225 23:08:43.774246 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8226 23:08:43.780680 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8227 23:08:43.783770 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8228 23:08:43.790400 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8229 23:08:43.798040 [CA 0] Center 41 (12~71) winsize 60
8230 23:08:43.801835 [CA 1] Center 41 (12~71) winsize 60
8231 23:08:43.804878 [CA 2] Center 38 (9~68) winsize 60
8232 23:08:43.808208 [CA 3] Center 37 (8~66) winsize 59
8233 23:08:43.811458 [CA 4] Center 37 (8~67) winsize 60
8234 23:08:43.815039 [CA 5] Center 36 (7~66) winsize 60
8235 23:08:43.815122
8236 23:08:43.818019 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8237 23:08:43.818102
8238 23:08:43.821499 [CATrainingPosCal] consider 1 rank data
8239 23:08:43.824923 u2DelayCellTimex100 = 290/100 ps
8240 23:08:43.827978 CA0 delay=41 (12~71),Diff = 5 PI (16 cell)
8241 23:08:43.834801 CA1 delay=41 (12~71),Diff = 5 PI (16 cell)
8242 23:08:43.838065 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
8243 23:08:43.841221 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8244 23:08:43.844723 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8245 23:08:43.847988 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8246 23:08:43.848070
8247 23:08:43.851131 CA PerBit enable=1, Macro0, CA PI delay=36
8248 23:08:43.851214
8249 23:08:43.854854 [CBTSetCACLKResult] CA Dly = 36
8250 23:08:43.858047 CS Dly: 11 (0~42)
8251 23:08:43.861315 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8252 23:08:43.864527 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8253 23:08:43.864609 ==
8254 23:08:43.868031 Dram Type= 6, Freq= 0, CH_1, rank 1
8255 23:08:43.871520 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8256 23:08:43.874393 ==
8257 23:08:43.877860 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8258 23:08:43.881467 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8259 23:08:43.888292 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8260 23:08:43.891520 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8261 23:08:43.901253 [CA 0] Center 42 (12~72) winsize 61
8262 23:08:43.904818 [CA 1] Center 41 (12~71) winsize 60
8263 23:08:43.908384 [CA 2] Center 38 (9~68) winsize 60
8264 23:08:43.911753 [CA 3] Center 37 (8~67) winsize 60
8265 23:08:43.914990 [CA 4] Center 38 (9~68) winsize 60
8266 23:08:43.918103 [CA 5] Center 37 (8~67) winsize 60
8267 23:08:43.918185
8268 23:08:43.921486 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8269 23:08:43.921567
8270 23:08:43.924975 [CATrainingPosCal] consider 2 rank data
8271 23:08:43.927728 u2DelayCellTimex100 = 290/100 ps
8272 23:08:43.931437 CA0 delay=41 (12~71),Diff = 4 PI (13 cell)
8273 23:08:43.937855 CA1 delay=41 (12~71),Diff = 4 PI (13 cell)
8274 23:08:43.941515 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8275 23:08:43.945232 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8276 23:08:43.947812 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8277 23:08:43.951044 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8278 23:08:43.951125
8279 23:08:43.954426 CA PerBit enable=1, Macro0, CA PI delay=37
8280 23:08:43.954507
8281 23:08:43.958231 [CBTSetCACLKResult] CA Dly = 37
8282 23:08:43.961275 CS Dly: 12 (0~44)
8283 23:08:43.965199 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8284 23:08:43.967812 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8285 23:08:43.967893
8286 23:08:43.971246 ----->DramcWriteLeveling(PI) begin...
8287 23:08:43.971328 ==
8288 23:08:43.974778 Dram Type= 6, Freq= 0, CH_1, rank 0
8289 23:08:43.977510 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8290 23:08:43.981216 ==
8291 23:08:43.981297 Write leveling (Byte 0): 25 => 25
8292 23:08:43.984508 Write leveling (Byte 1): 27 => 27
8293 23:08:43.987618 DramcWriteLeveling(PI) end<-----
8294 23:08:43.987697
8295 23:08:43.987759 ==
8296 23:08:43.991036 Dram Type= 6, Freq= 0, CH_1, rank 0
8297 23:08:43.997585 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8298 23:08:43.997683 ==
8299 23:08:43.997745 [Gating] SW mode calibration
8300 23:08:44.007507 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8301 23:08:44.011275 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8302 23:08:44.017418 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8303 23:08:44.021179 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8304 23:08:44.024392 1 4 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (1 1)
8305 23:08:44.030710 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8306 23:08:44.034478 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8307 23:08:44.037491 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8308 23:08:44.040800 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8309 23:08:44.047416 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8310 23:08:44.050957 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8311 23:08:44.054011 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8312 23:08:44.060768 1 5 8 | B1->B0 | 3434 2b2b | 1 0 | (1 0) (0 0)
8313 23:08:44.063939 1 5 12 | B1->B0 | 2525 2323 | 0 0 | (1 0) (1 0)
8314 23:08:44.067703 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8315 23:08:44.073772 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8316 23:08:44.077379 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8317 23:08:44.080388 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8318 23:08:44.086955 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8319 23:08:44.090166 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8320 23:08:44.093409 1 6 8 | B1->B0 | 2323 3636 | 0 1 | (0 0) (0 0)
8321 23:08:44.100075 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8322 23:08:44.104091 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8323 23:08:44.107393 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8324 23:08:44.113858 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8325 23:08:44.116843 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8326 23:08:44.120006 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8327 23:08:44.127192 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8328 23:08:44.130010 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8329 23:08:44.133846 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8330 23:08:44.140239 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8331 23:08:44.143318 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8332 23:08:44.146573 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8333 23:08:44.153463 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8334 23:08:44.156830 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8335 23:08:44.160106 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8336 23:08:44.166413 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8337 23:08:44.169802 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8338 23:08:44.173338 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8339 23:08:44.179726 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8340 23:08:44.183371 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8341 23:08:44.186912 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8342 23:08:44.193511 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8343 23:08:44.196312 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8344 23:08:44.199742 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8345 23:08:44.206365 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8346 23:08:44.209953 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8347 23:08:44.212970 Total UI for P1: 0, mck2ui 16
8348 23:08:44.216436 best dqsien dly found for B0: ( 1, 9, 10)
8349 23:08:44.220030 Total UI for P1: 0, mck2ui 16
8350 23:08:44.223026 best dqsien dly found for B1: ( 1, 9, 10)
8351 23:08:44.226199 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8352 23:08:44.229758 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8353 23:08:44.229841
8354 23:08:44.233293 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8355 23:08:44.236040 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8356 23:08:44.239655 [Gating] SW calibration Done
8357 23:08:44.239738 ==
8358 23:08:44.242968 Dram Type= 6, Freq= 0, CH_1, rank 0
8359 23:08:44.246608 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8360 23:08:44.246691 ==
8361 23:08:44.249407 RX Vref Scan: 0
8362 23:08:44.249490
8363 23:08:44.253091 RX Vref 0 -> 0, step: 1
8364 23:08:44.253174
8365 23:08:44.253259 RX Delay 0 -> 252, step: 8
8366 23:08:44.259612 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8367 23:08:44.262859 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8368 23:08:44.266400 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8369 23:08:44.269476 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8370 23:08:44.272964 iDelay=200, Bit 4, Center 135 (88 ~ 183) 96
8371 23:08:44.279561 iDelay=200, Bit 5, Center 151 (104 ~ 199) 96
8372 23:08:44.282775 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8373 23:08:44.286250 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8374 23:08:44.289513 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8375 23:08:44.292772 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8376 23:08:44.299903 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8377 23:08:44.302862 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8378 23:08:44.305839 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8379 23:08:44.309183 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8380 23:08:44.313215 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8381 23:08:44.319662 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8382 23:08:44.319746 ==
8383 23:08:44.322572 Dram Type= 6, Freq= 0, CH_1, rank 0
8384 23:08:44.326285 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8385 23:08:44.326368 ==
8386 23:08:44.326453 DQS Delay:
8387 23:08:44.329262 DQS0 = 0, DQS1 = 0
8388 23:08:44.329345 DQM Delay:
8389 23:08:44.332727 DQM0 = 137, DQM1 = 132
8390 23:08:44.332812 DQ Delay:
8391 23:08:44.336303 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8392 23:08:44.339402 DQ4 =135, DQ5 =151, DQ6 =147, DQ7 =135
8393 23:08:44.342688 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8394 23:08:44.346033 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =139
8395 23:08:44.346116
8396 23:08:44.346200
8397 23:08:44.349410 ==
8398 23:08:44.352297 Dram Type= 6, Freq= 0, CH_1, rank 0
8399 23:08:44.356052 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8400 23:08:44.356134 ==
8401 23:08:44.356219
8402 23:08:44.356298
8403 23:08:44.359338 TX Vref Scan disable
8404 23:08:44.359444 == TX Byte 0 ==
8405 23:08:44.362438 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8406 23:08:44.368792 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8407 23:08:44.368875 == TX Byte 1 ==
8408 23:08:44.375524 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8409 23:08:44.378932 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8410 23:08:44.379015 ==
8411 23:08:44.382270 Dram Type= 6, Freq= 0, CH_1, rank 0
8412 23:08:44.385744 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8413 23:08:44.385827 ==
8414 23:08:44.398650
8415 23:08:44.401773 TX Vref early break, caculate TX vref
8416 23:08:44.405325 TX Vref=16, minBit 1, minWin=22, winSum=380
8417 23:08:44.408552 TX Vref=18, minBit 0, minWin=23, winSum=384
8418 23:08:44.411769 TX Vref=20, minBit 5, minWin=23, winSum=396
8419 23:08:44.414891 TX Vref=22, minBit 1, minWin=24, winSum=405
8420 23:08:44.418095 TX Vref=24, minBit 0, minWin=25, winSum=416
8421 23:08:44.425010 TX Vref=26, minBit 1, minWin=25, winSum=428
8422 23:08:44.428291 TX Vref=28, minBit 0, minWin=25, winSum=427
8423 23:08:44.431786 TX Vref=30, minBit 0, minWin=25, winSum=419
8424 23:08:44.434879 TX Vref=32, minBit 0, minWin=24, winSum=416
8425 23:08:44.438324 TX Vref=34, minBit 0, minWin=24, winSum=405
8426 23:08:44.444973 [TxChooseVref] Worse bit 1, Min win 25, Win sum 428, Final Vref 26
8427 23:08:44.445056
8428 23:08:44.448523 Final TX Range 0 Vref 26
8429 23:08:44.448606
8430 23:08:44.448690 ==
8431 23:08:44.451289 Dram Type= 6, Freq= 0, CH_1, rank 0
8432 23:08:44.454803 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8433 23:08:44.454886 ==
8434 23:08:44.454970
8435 23:08:44.455050
8436 23:08:44.458061 TX Vref Scan disable
8437 23:08:44.464802 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8438 23:08:44.464886 == TX Byte 0 ==
8439 23:08:44.467858 u2DelayCellOfst[0]=16 cells (5 PI)
8440 23:08:44.471212 u2DelayCellOfst[1]=10 cells (3 PI)
8441 23:08:44.475106 u2DelayCellOfst[2]=0 cells (0 PI)
8442 23:08:44.478012 u2DelayCellOfst[3]=6 cells (2 PI)
8443 23:08:44.481493 u2DelayCellOfst[4]=6 cells (2 PI)
8444 23:08:44.484639 u2DelayCellOfst[5]=16 cells (5 PI)
8445 23:08:44.487724 u2DelayCellOfst[6]=16 cells (5 PI)
8446 23:08:44.491161 u2DelayCellOfst[7]=3 cells (1 PI)
8447 23:08:44.494711 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8448 23:08:44.497738 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8449 23:08:44.500717 == TX Byte 1 ==
8450 23:08:44.504419 u2DelayCellOfst[8]=0 cells (0 PI)
8451 23:08:44.504521 u2DelayCellOfst[9]=3 cells (1 PI)
8452 23:08:44.507753 u2DelayCellOfst[10]=13 cells (4 PI)
8453 23:08:44.510978 u2DelayCellOfst[11]=3 cells (1 PI)
8454 23:08:44.514647 u2DelayCellOfst[12]=16 cells (5 PI)
8455 23:08:44.517513 u2DelayCellOfst[13]=16 cells (5 PI)
8456 23:08:44.520888 u2DelayCellOfst[14]=16 cells (5 PI)
8457 23:08:44.524394 u2DelayCellOfst[15]=16 cells (5 PI)
8458 23:08:44.527517 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8459 23:08:44.534384 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8460 23:08:44.534468 DramC Write-DBI on
8461 23:08:44.534553 ==
8462 23:08:44.537861 Dram Type= 6, Freq= 0, CH_1, rank 0
8463 23:08:44.544293 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8464 23:08:44.544377 ==
8465 23:08:44.544462
8466 23:08:44.544543
8467 23:08:44.544622 TX Vref Scan disable
8468 23:08:44.547778 == TX Byte 0 ==
8469 23:08:44.551272 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8470 23:08:44.554249 == TX Byte 1 ==
8471 23:08:44.557636 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8472 23:08:44.561052 DramC Write-DBI off
8473 23:08:44.561135
8474 23:08:44.561218 [DATLAT]
8475 23:08:44.561298 Freq=1600, CH1 RK0
8476 23:08:44.561375
8477 23:08:44.564660 DATLAT Default: 0xf
8478 23:08:44.564743 0, 0xFFFF, sum = 0
8479 23:08:44.567839 1, 0xFFFF, sum = 0
8480 23:08:44.567922 2, 0xFFFF, sum = 0
8481 23:08:44.571500 3, 0xFFFF, sum = 0
8482 23:08:44.571584 4, 0xFFFF, sum = 0
8483 23:08:44.574488 5, 0xFFFF, sum = 0
8484 23:08:44.577870 6, 0xFFFF, sum = 0
8485 23:08:44.577955 7, 0xFFFF, sum = 0
8486 23:08:44.581442 8, 0xFFFF, sum = 0
8487 23:08:44.581552 9, 0xFFFF, sum = 0
8488 23:08:44.584441 10, 0xFFFF, sum = 0
8489 23:08:44.584525 11, 0xFFFF, sum = 0
8490 23:08:44.587955 12, 0xFFFF, sum = 0
8491 23:08:44.588039 13, 0xFFFF, sum = 0
8492 23:08:44.591362 14, 0x0, sum = 1
8493 23:08:44.591445 15, 0x0, sum = 2
8494 23:08:44.594655 16, 0x0, sum = 3
8495 23:08:44.594744 17, 0x0, sum = 4
8496 23:08:44.597893 best_step = 15
8497 23:08:44.597975
8498 23:08:44.598060 ==
8499 23:08:44.601184 Dram Type= 6, Freq= 0, CH_1, rank 0
8500 23:08:44.604801 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8501 23:08:44.604885 ==
8502 23:08:44.604970 RX Vref Scan: 1
8503 23:08:44.605049
8504 23:08:44.607765 Set Vref Range= 24 -> 127
8505 23:08:44.607872
8506 23:08:44.611699 RX Vref 24 -> 127, step: 1
8507 23:08:44.611782
8508 23:08:44.614700 RX Delay 27 -> 252, step: 4
8509 23:08:44.614783
8510 23:08:44.618186 Set Vref, RX VrefLevel [Byte0]: 24
8511 23:08:44.621558 [Byte1]: 24
8512 23:08:44.621681
8513 23:08:44.624566 Set Vref, RX VrefLevel [Byte0]: 25
8514 23:08:44.627701 [Byte1]: 25
8515 23:08:44.627814
8516 23:08:44.631055 Set Vref, RX VrefLevel [Byte0]: 26
8517 23:08:44.634414 [Byte1]: 26
8518 23:08:44.638098
8519 23:08:44.638180 Set Vref, RX VrefLevel [Byte0]: 27
8520 23:08:44.641292 [Byte1]: 27
8521 23:08:44.645289
8522 23:08:44.645372 Set Vref, RX VrefLevel [Byte0]: 28
8523 23:08:44.649102 [Byte1]: 28
8524 23:08:44.653187
8525 23:08:44.653270 Set Vref, RX VrefLevel [Byte0]: 29
8526 23:08:44.656325 [Byte1]: 29
8527 23:08:44.660647
8528 23:08:44.660730 Set Vref, RX VrefLevel [Byte0]: 30
8529 23:08:44.663960 [Byte1]: 30
8530 23:08:44.668149
8531 23:08:44.668231 Set Vref, RX VrefLevel [Byte0]: 31
8532 23:08:44.671203 [Byte1]: 31
8533 23:08:44.675612
8534 23:08:44.675694 Set Vref, RX VrefLevel [Byte0]: 32
8535 23:08:44.679310 [Byte1]: 32
8536 23:08:44.683328
8537 23:08:44.683409 Set Vref, RX VrefLevel [Byte0]: 33
8538 23:08:44.686329 [Byte1]: 33
8539 23:08:44.690569
8540 23:08:44.690684 Set Vref, RX VrefLevel [Byte0]: 34
8541 23:08:44.694048 [Byte1]: 34
8542 23:08:44.697911
8543 23:08:44.701284 Set Vref, RX VrefLevel [Byte0]: 35
8544 23:08:44.705143 [Byte1]: 35
8545 23:08:44.705227
8546 23:08:44.708147 Set Vref, RX VrefLevel [Byte0]: 36
8547 23:08:44.711531 [Byte1]: 36
8548 23:08:44.711613
8549 23:08:44.714771 Set Vref, RX VrefLevel [Byte0]: 37
8550 23:08:44.717938 [Byte1]: 37
8551 23:08:44.718021
8552 23:08:44.721542 Set Vref, RX VrefLevel [Byte0]: 38
8553 23:08:44.724539 [Byte1]: 38
8554 23:08:44.728563
8555 23:08:44.728646 Set Vref, RX VrefLevel [Byte0]: 39
8556 23:08:44.731841 [Byte1]: 39
8557 23:08:44.736307
8558 23:08:44.736389 Set Vref, RX VrefLevel [Byte0]: 40
8559 23:08:44.739007 [Byte1]: 40
8560 23:08:44.743470
8561 23:08:44.743552 Set Vref, RX VrefLevel [Byte0]: 41
8562 23:08:44.746705 [Byte1]: 41
8563 23:08:44.751088
8564 23:08:44.751170 Set Vref, RX VrefLevel [Byte0]: 42
8565 23:08:44.754825 [Byte1]: 42
8566 23:08:44.758606
8567 23:08:44.758688 Set Vref, RX VrefLevel [Byte0]: 43
8568 23:08:44.761984 [Byte1]: 43
8569 23:08:44.766617
8570 23:08:44.766699 Set Vref, RX VrefLevel [Byte0]: 44
8571 23:08:44.769504 [Byte1]: 44
8572 23:08:44.773748
8573 23:08:44.773830 Set Vref, RX VrefLevel [Byte0]: 45
8574 23:08:44.776806 [Byte1]: 45
8575 23:08:44.781191
8576 23:08:44.781273 Set Vref, RX VrefLevel [Byte0]: 46
8577 23:08:44.784496 [Byte1]: 46
8578 23:08:44.788430
8579 23:08:44.788512 Set Vref, RX VrefLevel [Byte0]: 47
8580 23:08:44.791984 [Byte1]: 47
8581 23:08:44.796375
8582 23:08:44.796462 Set Vref, RX VrefLevel [Byte0]: 48
8583 23:08:44.799718 [Byte1]: 48
8584 23:08:44.803996
8585 23:08:44.804079 Set Vref, RX VrefLevel [Byte0]: 49
8586 23:08:44.807218 [Byte1]: 49
8587 23:08:44.811287
8588 23:08:44.811370 Set Vref, RX VrefLevel [Byte0]: 50
8589 23:08:44.814509 [Byte1]: 50
8590 23:08:44.818738
8591 23:08:44.818824 Set Vref, RX VrefLevel [Byte0]: 51
8592 23:08:44.821956 [Byte1]: 51
8593 23:08:44.826217
8594 23:08:44.826300 Set Vref, RX VrefLevel [Byte0]: 52
8595 23:08:44.829552 [Byte1]: 52
8596 23:08:44.833879
8597 23:08:44.833962 Set Vref, RX VrefLevel [Byte0]: 53
8598 23:08:44.837531 [Byte1]: 53
8599 23:08:44.841711
8600 23:08:44.841793 Set Vref, RX VrefLevel [Byte0]: 54
8601 23:08:44.844705 [Byte1]: 54
8602 23:08:44.848969
8603 23:08:44.849051 Set Vref, RX VrefLevel [Byte0]: 55
8604 23:08:44.852440 [Byte1]: 55
8605 23:08:44.856248
8606 23:08:44.856330 Set Vref, RX VrefLevel [Byte0]: 56
8607 23:08:44.859643 [Byte1]: 56
8608 23:08:44.863843
8609 23:08:44.863925 Set Vref, RX VrefLevel [Byte0]: 57
8610 23:08:44.867171 [Byte1]: 57
8611 23:08:44.871652
8612 23:08:44.871734 Set Vref, RX VrefLevel [Byte0]: 58
8613 23:08:44.875065 [Byte1]: 58
8614 23:08:44.879111
8615 23:08:44.879194 Set Vref, RX VrefLevel [Byte0]: 59
8616 23:08:44.882505 [Byte1]: 59
8617 23:08:44.886626
8618 23:08:44.886709 Set Vref, RX VrefLevel [Byte0]: 60
8619 23:08:44.890142 [Byte1]: 60
8620 23:08:44.894233
8621 23:08:44.894315 Set Vref, RX VrefLevel [Byte0]: 61
8622 23:08:44.897513 [Byte1]: 61
8623 23:08:44.902042
8624 23:08:44.902125 Set Vref, RX VrefLevel [Byte0]: 62
8625 23:08:44.904906 [Byte1]: 62
8626 23:08:44.909244
8627 23:08:44.909326 Set Vref, RX VrefLevel [Byte0]: 63
8628 23:08:44.912532 [Byte1]: 63
8629 23:08:44.916871
8630 23:08:44.916954 Set Vref, RX VrefLevel [Byte0]: 64
8631 23:08:44.919776 [Byte1]: 64
8632 23:08:44.924063
8633 23:08:44.924145 Set Vref, RX VrefLevel [Byte0]: 65
8634 23:08:44.927332 [Byte1]: 65
8635 23:08:44.932092
8636 23:08:44.932175 Set Vref, RX VrefLevel [Byte0]: 66
8637 23:08:44.934989 [Byte1]: 66
8638 23:08:44.939111
8639 23:08:44.939193 Set Vref, RX VrefLevel [Byte0]: 67
8640 23:08:44.942442 [Byte1]: 67
8641 23:08:44.946815
8642 23:08:44.946897 Set Vref, RX VrefLevel [Byte0]: 68
8643 23:08:44.950293 [Byte1]: 68
8644 23:08:44.954220
8645 23:08:44.954307 Set Vref, RX VrefLevel [Byte0]: 69
8646 23:08:44.957880 [Byte1]: 69
8647 23:08:44.962332
8648 23:08:44.962415 Set Vref, RX VrefLevel [Byte0]: 70
8649 23:08:44.965685 [Byte1]: 70
8650 23:08:44.969709
8651 23:08:44.969791 Set Vref, RX VrefLevel [Byte0]: 71
8652 23:08:44.972817 [Byte1]: 71
8653 23:08:44.977007
8654 23:08:44.977088 Set Vref, RX VrefLevel [Byte0]: 72
8655 23:08:44.980180 [Byte1]: 72
8656 23:08:44.984422
8657 23:08:44.984504 Set Vref, RX VrefLevel [Byte0]: 73
8658 23:08:44.988337 [Byte1]: 73
8659 23:08:44.992154
8660 23:08:44.992251 Set Vref, RX VrefLevel [Byte0]: 74
8661 23:08:44.995334 [Byte1]: 74
8662 23:08:44.999461
8663 23:08:44.999542 Set Vref, RX VrefLevel [Byte0]: 75
8664 23:08:45.002983 [Byte1]: 75
8665 23:08:45.006848
8666 23:08:45.006930 Set Vref, RX VrefLevel [Byte0]: 76
8667 23:08:45.010321 [Byte1]: 76
8668 23:08:45.014450
8669 23:08:45.014532 Final RX Vref Byte 0 = 58 to rank0
8670 23:08:45.017776 Final RX Vref Byte 1 = 56 to rank0
8671 23:08:45.021308 Final RX Vref Byte 0 = 58 to rank1
8672 23:08:45.025048 Final RX Vref Byte 1 = 56 to rank1==
8673 23:08:45.027958 Dram Type= 6, Freq= 0, CH_1, rank 0
8674 23:08:45.034482 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8675 23:08:45.034566 ==
8676 23:08:45.034651 DQS Delay:
8677 23:08:45.034732 DQS0 = 0, DQS1 = 0
8678 23:08:45.038074 DQM Delay:
8679 23:08:45.038157 DQM0 = 134, DQM1 = 131
8680 23:08:45.041147 DQ Delay:
8681 23:08:45.044471 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8682 23:08:45.047800 DQ4 =134, DQ5 =144, DQ6 =144, DQ7 =132
8683 23:08:45.050815 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =124
8684 23:08:45.054594 DQ12 =138, DQ13 =140, DQ14 =140, DQ15 =140
8685 23:08:45.054677
8686 23:08:45.054761
8687 23:08:45.054840
8688 23:08:45.057394 [DramC_TX_OE_Calibration] TA2
8689 23:08:45.060993 Original DQ_B0 (3 6) =30, OEN = 27
8690 23:08:45.064524 Original DQ_B1 (3 6) =30, OEN = 27
8691 23:08:45.067510 24, 0x0, End_B0=24 End_B1=24
8692 23:08:45.067595 25, 0x0, End_B0=25 End_B1=25
8693 23:08:45.071080 26, 0x0, End_B0=26 End_B1=26
8694 23:08:45.074023 27, 0x0, End_B0=27 End_B1=27
8695 23:08:45.077582 28, 0x0, End_B0=28 End_B1=28
8696 23:08:45.081214 29, 0x0, End_B0=29 End_B1=29
8697 23:08:45.081298 30, 0x0, End_B0=30 End_B1=30
8698 23:08:45.084204 31, 0x4141, End_B0=30 End_B1=30
8699 23:08:45.087649 Byte0 end_step=30 best_step=27
8700 23:08:45.090919 Byte1 end_step=30 best_step=27
8701 23:08:45.094132 Byte0 TX OE(2T, 0.5T) = (3, 3)
8702 23:08:45.097480 Byte1 TX OE(2T, 0.5T) = (3, 3)
8703 23:08:45.097564
8704 23:08:45.097687
8705 23:08:45.103974 [DQSOSCAuto] RK0, (LSB)MR18= 0x1624, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
8706 23:08:45.107226 CH1 RK0: MR19=303, MR18=1624
8707 23:08:45.114070 CH1_RK0: MR19=0x303, MR18=0x1624, DQSOSC=391, MR23=63, INC=24, DEC=16
8708 23:08:45.114153
8709 23:08:45.117009 ----->DramcWriteLeveling(PI) begin...
8710 23:08:45.117093 ==
8711 23:08:45.120895 Dram Type= 6, Freq= 0, CH_1, rank 1
8712 23:08:45.124169 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8713 23:08:45.124253 ==
8714 23:08:45.127292 Write leveling (Byte 0): 26 => 26
8715 23:08:45.130661 Write leveling (Byte 1): 28 => 28
8716 23:08:45.133882 DramcWriteLeveling(PI) end<-----
8717 23:08:45.133965
8718 23:08:45.134051 ==
8719 23:08:45.137487 Dram Type= 6, Freq= 0, CH_1, rank 1
8720 23:08:45.140405 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8721 23:08:45.140489 ==
8722 23:08:45.143889 [Gating] SW mode calibration
8723 23:08:45.151023 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8724 23:08:45.157131 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8725 23:08:45.160885 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8726 23:08:45.164145 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8727 23:08:45.170320 1 4 8 | B1->B0 | 2b2b 2322 | 0 1 | (0 0) (0 0)
8728 23:08:45.173898 1 4 12 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
8729 23:08:45.177461 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8730 23:08:45.183686 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8731 23:08:45.187284 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8732 23:08:45.190479 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8733 23:08:45.197003 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8734 23:08:45.200690 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8735 23:08:45.203521 1 5 8 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
8736 23:08:45.210003 1 5 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 0)
8737 23:08:45.213805 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8738 23:08:45.217364 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8739 23:08:45.223516 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8740 23:08:45.226631 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8741 23:08:45.229897 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8742 23:08:45.237194 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8743 23:08:45.240046 1 6 8 | B1->B0 | 3030 2323 | 0 0 | (1 1) (0 0)
8744 23:08:45.243817 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8745 23:08:45.250100 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8746 23:08:45.253193 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8747 23:08:45.256816 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8748 23:08:45.263393 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8749 23:08:45.267192 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8750 23:08:45.270058 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8751 23:08:45.276707 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8752 23:08:45.280049 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8753 23:08:45.283712 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8754 23:08:45.290702 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8755 23:08:45.293270 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8756 23:08:45.296851 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8757 23:08:45.303420 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8758 23:08:45.306655 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8759 23:08:45.309882 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8760 23:08:45.313150 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8761 23:08:45.319980 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8762 23:08:45.323174 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8763 23:08:45.326663 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8764 23:08:45.333520 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8765 23:08:45.336354 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8766 23:08:45.339902 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8767 23:08:45.346863 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8768 23:08:45.349998 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8769 23:08:45.353445 Total UI for P1: 0, mck2ui 16
8770 23:08:45.356669 best dqsien dly found for B1: ( 1, 9, 6)
8771 23:08:45.360230 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8772 23:08:45.363416 Total UI for P1: 0, mck2ui 16
8773 23:08:45.367249 best dqsien dly found for B0: ( 1, 9, 12)
8774 23:08:45.370007 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8775 23:08:45.373361 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8776 23:08:45.373441
8777 23:08:45.376813 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8778 23:08:45.383546 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8779 23:08:45.383630 [Gating] SW calibration Done
8780 23:08:45.386890 ==
8781 23:08:45.386973 Dram Type= 6, Freq= 0, CH_1, rank 1
8782 23:08:45.393487 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8783 23:08:45.393571 ==
8784 23:08:45.393697 RX Vref Scan: 0
8785 23:08:45.393776
8786 23:08:45.396679 RX Vref 0 -> 0, step: 1
8787 23:08:45.396760
8788 23:08:45.399734 RX Delay 0 -> 252, step: 8
8789 23:08:45.403199 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8790 23:08:45.406947 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8791 23:08:45.409791 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8792 23:08:45.416882 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8793 23:08:45.419491 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8794 23:08:45.423110 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8795 23:08:45.426342 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8796 23:08:45.429584 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8797 23:08:45.436356 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8798 23:08:45.439450 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8799 23:08:45.442817 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8800 23:08:45.446362 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8801 23:08:45.449450 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8802 23:08:45.455951 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8803 23:08:45.459219 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8804 23:08:45.462552 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8805 23:08:45.462633 ==
8806 23:08:45.466093 Dram Type= 6, Freq= 0, CH_1, rank 1
8807 23:08:45.469696 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8808 23:08:45.473167 ==
8809 23:08:45.473246 DQS Delay:
8810 23:08:45.473309 DQS0 = 0, DQS1 = 0
8811 23:08:45.475952 DQM Delay:
8812 23:08:45.476032 DQM0 = 136, DQM1 = 133
8813 23:08:45.479199 DQ Delay:
8814 23:08:45.482639 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8815 23:08:45.485969 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8816 23:08:45.489907 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8817 23:08:45.492588 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8818 23:08:45.492668
8819 23:08:45.492749
8820 23:08:45.492820 ==
8821 23:08:45.495868 Dram Type= 6, Freq= 0, CH_1, rank 1
8822 23:08:45.499148 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8823 23:08:45.499229 ==
8824 23:08:45.499292
8825 23:08:45.502635
8826 23:08:45.502714 TX Vref Scan disable
8827 23:08:45.506021 == TX Byte 0 ==
8828 23:08:45.509313 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8829 23:08:45.512927 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8830 23:08:45.516134 == TX Byte 1 ==
8831 23:08:45.519285 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8832 23:08:45.522219 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8833 23:08:45.522328 ==
8834 23:08:45.525621 Dram Type= 6, Freq= 0, CH_1, rank 1
8835 23:08:45.532231 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8836 23:08:45.532365 ==
8837 23:08:45.545070
8838 23:08:45.548469 TX Vref early break, caculate TX vref
8839 23:08:45.551666 TX Vref=16, minBit 0, minWin=22, winSum=385
8840 23:08:45.555725 TX Vref=18, minBit 6, minWin=23, winSum=391
8841 23:08:45.558527 TX Vref=20, minBit 0, minWin=24, winSum=403
8842 23:08:45.561533 TX Vref=22, minBit 0, minWin=24, winSum=407
8843 23:08:45.564530 TX Vref=24, minBit 0, minWin=25, winSum=417
8844 23:08:45.571640 TX Vref=26, minBit 0, minWin=25, winSum=426
8845 23:08:45.574788 TX Vref=28, minBit 0, minWin=25, winSum=425
8846 23:08:45.577853 TX Vref=30, minBit 0, minWin=25, winSum=423
8847 23:08:45.581551 TX Vref=32, minBit 0, minWin=25, winSum=414
8848 23:08:45.585310 TX Vref=34, minBit 0, minWin=24, winSum=407
8849 23:08:45.588173 TX Vref=36, minBit 1, minWin=23, winSum=399
8850 23:08:45.594800 [TxChooseVref] Worse bit 0, Min win 25, Win sum 426, Final Vref 26
8851 23:08:45.594915
8852 23:08:45.597838 Final TX Range 0 Vref 26
8853 23:08:45.597940
8854 23:08:45.598029 ==
8855 23:08:45.601245 Dram Type= 6, Freq= 0, CH_1, rank 1
8856 23:08:45.604487 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8857 23:08:45.604594 ==
8858 23:08:45.604686
8859 23:08:45.604774
8860 23:08:45.607879 TX Vref Scan disable
8861 23:08:45.614679 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8862 23:08:45.614764 == TX Byte 0 ==
8863 23:08:45.617856 u2DelayCellOfst[0]=16 cells (5 PI)
8864 23:08:45.621339 u2DelayCellOfst[1]=10 cells (3 PI)
8865 23:08:45.624324 u2DelayCellOfst[2]=0 cells (0 PI)
8866 23:08:45.627538 u2DelayCellOfst[3]=6 cells (2 PI)
8867 23:08:45.631038 u2DelayCellOfst[4]=6 cells (2 PI)
8868 23:08:45.634632 u2DelayCellOfst[5]=16 cells (5 PI)
8869 23:08:45.637704 u2DelayCellOfst[6]=16 cells (5 PI)
8870 23:08:45.641471 u2DelayCellOfst[7]=3 cells (1 PI)
8871 23:08:45.644376 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8872 23:08:45.647625 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8873 23:08:45.651253 == TX Byte 1 ==
8874 23:08:45.654062 u2DelayCellOfst[8]=0 cells (0 PI)
8875 23:08:45.657489 u2DelayCellOfst[9]=3 cells (1 PI)
8876 23:08:45.657570 u2DelayCellOfst[10]=10 cells (3 PI)
8877 23:08:45.660671 u2DelayCellOfst[11]=3 cells (1 PI)
8878 23:08:45.664062 u2DelayCellOfst[12]=13 cells (4 PI)
8879 23:08:45.667288 u2DelayCellOfst[13]=16 cells (5 PI)
8880 23:08:45.670940 u2DelayCellOfst[14]=13 cells (4 PI)
8881 23:08:45.674045 u2DelayCellOfst[15]=16 cells (5 PI)
8882 23:08:45.680613 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8883 23:08:45.684272 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8884 23:08:45.684353 DramC Write-DBI on
8885 23:08:45.684418 ==
8886 23:08:45.687284 Dram Type= 6, Freq= 0, CH_1, rank 1
8887 23:08:45.693858 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8888 23:08:45.693939 ==
8889 23:08:45.694004
8890 23:08:45.694063
8891 23:08:45.694119 TX Vref Scan disable
8892 23:08:45.697966 == TX Byte 0 ==
8893 23:08:45.701674 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8894 23:08:45.704654 == TX Byte 1 ==
8895 23:08:45.708410 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8896 23:08:45.711441 DramC Write-DBI off
8897 23:08:45.711522
8898 23:08:45.711586 [DATLAT]
8899 23:08:45.711648 Freq=1600, CH1 RK1
8900 23:08:45.711706
8901 23:08:45.714860 DATLAT Default: 0xf
8902 23:08:45.714941 0, 0xFFFF, sum = 0
8903 23:08:45.718357 1, 0xFFFF, sum = 0
8904 23:08:45.718438 2, 0xFFFF, sum = 0
8905 23:08:45.721485 3, 0xFFFF, sum = 0
8906 23:08:45.724696 4, 0xFFFF, sum = 0
8907 23:08:45.724779 5, 0xFFFF, sum = 0
8908 23:08:45.727954 6, 0xFFFF, sum = 0
8909 23:08:45.728036 7, 0xFFFF, sum = 0
8910 23:08:45.731452 8, 0xFFFF, sum = 0
8911 23:08:45.731535 9, 0xFFFF, sum = 0
8912 23:08:45.734775 10, 0xFFFF, sum = 0
8913 23:08:45.734857 11, 0xFFFF, sum = 0
8914 23:08:45.738192 12, 0xFFFF, sum = 0
8915 23:08:45.738275 13, 0xFFFF, sum = 0
8916 23:08:45.741634 14, 0x0, sum = 1
8917 23:08:45.741716 15, 0x0, sum = 2
8918 23:08:45.744529 16, 0x0, sum = 3
8919 23:08:45.744611 17, 0x0, sum = 4
8920 23:08:45.748014 best_step = 15
8921 23:08:45.748094
8922 23:08:45.748158 ==
8923 23:08:45.751453 Dram Type= 6, Freq= 0, CH_1, rank 1
8924 23:08:45.754799 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8925 23:08:45.754881 ==
8926 23:08:45.754945 RX Vref Scan: 0
8927 23:08:45.758560
8928 23:08:45.758640 RX Vref 0 -> 0, step: 1
8929 23:08:45.758704
8930 23:08:45.761599 RX Delay 19 -> 252, step: 4
8931 23:08:45.764638 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8932 23:08:45.772116 iDelay=195, Bit 1, Center 132 (83 ~ 182) 100
8933 23:08:45.774465 iDelay=195, Bit 2, Center 124 (75 ~ 174) 100
8934 23:08:45.778035 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8935 23:08:45.781070 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8936 23:08:45.784736 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8937 23:08:45.787712 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8938 23:08:45.794935 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
8939 23:08:45.798017 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8940 23:08:45.801031 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8941 23:08:45.804467 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
8942 23:08:45.807686 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8943 23:08:45.814522 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
8944 23:08:45.818130 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8945 23:08:45.821326 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8946 23:08:45.824195 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
8947 23:08:45.824287 ==
8948 23:08:45.827991 Dram Type= 6, Freq= 0, CH_1, rank 1
8949 23:08:45.834289 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8950 23:08:45.834371 ==
8951 23:08:45.834435 DQS Delay:
8952 23:08:45.837522 DQS0 = 0, DQS1 = 0
8953 23:08:45.837642 DQM Delay:
8954 23:08:45.840857 DQM0 = 134, DQM1 = 130
8955 23:08:45.840938 DQ Delay:
8956 23:08:45.844223 DQ0 =138, DQ1 =132, DQ2 =124, DQ3 =130
8957 23:08:45.847841 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
8958 23:08:45.851049 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =124
8959 23:08:45.854290 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =140
8960 23:08:45.854371
8961 23:08:45.854435
8962 23:08:45.854494
8963 23:08:45.857807 [DramC_TX_OE_Calibration] TA2
8964 23:08:45.861251 Original DQ_B0 (3 6) =30, OEN = 27
8965 23:08:45.863975 Original DQ_B1 (3 6) =30, OEN = 27
8966 23:08:45.867532 24, 0x0, End_B0=24 End_B1=24
8967 23:08:45.867630 25, 0x0, End_B0=25 End_B1=25
8968 23:08:45.871086 26, 0x0, End_B0=26 End_B1=26
8969 23:08:45.874517 27, 0x0, End_B0=27 End_B1=27
8970 23:08:45.877560 28, 0x0, End_B0=28 End_B1=28
8971 23:08:45.881009 29, 0x0, End_B0=29 End_B1=29
8972 23:08:45.881091 30, 0x0, End_B0=30 End_B1=30
8973 23:08:45.884651 31, 0x4141, End_B0=30 End_B1=30
8974 23:08:45.887605 Byte0 end_step=30 best_step=27
8975 23:08:45.891107 Byte1 end_step=30 best_step=27
8976 23:08:45.894050 Byte0 TX OE(2T, 0.5T) = (3, 3)
8977 23:08:45.897694 Byte1 TX OE(2T, 0.5T) = (3, 3)
8978 23:08:45.897775
8979 23:08:45.897838
8980 23:08:45.904356 [DQSOSCAuto] RK1, (LSB)MR18= 0x2006, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 393 ps
8981 23:08:45.907324 CH1 RK1: MR19=303, MR18=2006
8982 23:08:45.913931 CH1_RK1: MR19=0x303, MR18=0x2006, DQSOSC=393, MR23=63, INC=23, DEC=15
8983 23:08:45.917140 [RxdqsGatingPostProcess] freq 1600
8984 23:08:45.920638 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8985 23:08:45.924101 best DQS0 dly(2T, 0.5T) = (1, 1)
8986 23:08:45.927200 best DQS1 dly(2T, 0.5T) = (1, 1)
8987 23:08:45.931093 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8988 23:08:45.933924 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8989 23:08:45.937141 best DQS0 dly(2T, 0.5T) = (1, 1)
8990 23:08:45.940550 best DQS1 dly(2T, 0.5T) = (1, 1)
8991 23:08:45.944020 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8992 23:08:45.947467 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8993 23:08:45.950285 Pre-setting of DQS Precalculation
8994 23:08:45.953856 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8995 23:08:45.960316 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8996 23:08:45.970355 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8997 23:08:45.970435
8998 23:08:45.970499
8999 23:08:45.974043 [Calibration Summary] 3200 Mbps
9000 23:08:45.974123 CH 0, Rank 0
9001 23:08:45.977107 SW Impedance : PASS
9002 23:08:45.977188 DUTY Scan : NO K
9003 23:08:45.980390 ZQ Calibration : PASS
9004 23:08:45.980470 Jitter Meter : NO K
9005 23:08:45.983890 CBT Training : PASS
9006 23:08:45.987241 Write leveling : PASS
9007 23:08:45.987329 RX DQS gating : PASS
9008 23:08:45.990178 RX DQ/DQS(RDDQC) : PASS
9009 23:08:45.993707 TX DQ/DQS : PASS
9010 23:08:45.993788 RX DATLAT : PASS
9011 23:08:45.997183 RX DQ/DQS(Engine): PASS
9012 23:08:46.000915 TX OE : PASS
9013 23:08:46.000996 All Pass.
9014 23:08:46.001059
9015 23:08:46.001118 CH 0, Rank 1
9016 23:08:46.003487 SW Impedance : PASS
9017 23:08:46.007500 DUTY Scan : NO K
9018 23:08:46.007581 ZQ Calibration : PASS
9019 23:08:46.010458 Jitter Meter : NO K
9020 23:08:46.013420 CBT Training : PASS
9021 23:08:46.013501 Write leveling : PASS
9022 23:08:46.016868 RX DQS gating : PASS
9023 23:08:46.020244 RX DQ/DQS(RDDQC) : PASS
9024 23:08:46.020325 TX DQ/DQS : PASS
9025 23:08:46.023979 RX DATLAT : PASS
9026 23:08:46.024060 RX DQ/DQS(Engine): PASS
9027 23:08:46.026896 TX OE : PASS
9028 23:08:46.026977 All Pass.
9029 23:08:46.027040
9030 23:08:46.029908 CH 1, Rank 0
9031 23:08:46.033528 SW Impedance : PASS
9032 23:08:46.033661 DUTY Scan : NO K
9033 23:08:46.037049 ZQ Calibration : PASS
9034 23:08:46.037130 Jitter Meter : NO K
9035 23:08:46.040472 CBT Training : PASS
9036 23:08:46.043561 Write leveling : PASS
9037 23:08:46.043641 RX DQS gating : PASS
9038 23:08:46.046671 RX DQ/DQS(RDDQC) : PASS
9039 23:08:46.049986 TX DQ/DQS : PASS
9040 23:08:46.050066 RX DATLAT : PASS
9041 23:08:46.053405 RX DQ/DQS(Engine): PASS
9042 23:08:46.057059 TX OE : PASS
9043 23:08:46.057139 All Pass.
9044 23:08:46.057202
9045 23:08:46.057261 CH 1, Rank 1
9046 23:08:46.060535 SW Impedance : PASS
9047 23:08:46.063525 DUTY Scan : NO K
9048 23:08:46.063605 ZQ Calibration : PASS
9049 23:08:46.066575 Jitter Meter : NO K
9050 23:08:46.070266 CBT Training : PASS
9051 23:08:46.070346 Write leveling : PASS
9052 23:08:46.073492 RX DQS gating : PASS
9053 23:08:46.073641 RX DQ/DQS(RDDQC) : PASS
9054 23:08:46.077336 TX DQ/DQS : PASS
9055 23:08:46.080382 RX DATLAT : PASS
9056 23:08:46.080461 RX DQ/DQS(Engine): PASS
9057 23:08:46.083871 TX OE : PASS
9058 23:08:46.083951 All Pass.
9059 23:08:46.084014
9060 23:08:46.087208 DramC Write-DBI on
9061 23:08:46.090090 PER_BANK_REFRESH: Hybrid Mode
9062 23:08:46.090170 TX_TRACKING: ON
9063 23:08:46.099861 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9064 23:08:46.106692 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9065 23:08:46.113494 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9066 23:08:46.119818 [FAST_K] Save calibration result to emmc
9067 23:08:46.119899 sync common calibartion params.
9068 23:08:46.123178 sync cbt_mode0:1, 1:1
9069 23:08:46.126804 dram_init: ddr_geometry: 2
9070 23:08:46.126884 dram_init: ddr_geometry: 2
9071 23:08:46.129752 dram_init: ddr_geometry: 2
9072 23:08:46.133487 0:dram_rank_size:100000000
9073 23:08:46.136488 1:dram_rank_size:100000000
9074 23:08:46.139877 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9075 23:08:46.142915 DFS_SHUFFLE_HW_MODE: ON
9076 23:08:46.146164 dramc_set_vcore_voltage set vcore to 725000
9077 23:08:46.149866 Read voltage for 1600, 0
9078 23:08:46.149947 Vio18 = 0
9079 23:08:46.153411 Vcore = 725000
9080 23:08:46.153491 Vdram = 0
9081 23:08:46.153555 Vddq = 0
9082 23:08:46.153626 Vmddr = 0
9083 23:08:46.156523 switch to 3200 Mbps bootup
9084 23:08:46.159821 [DramcRunTimeConfig]
9085 23:08:46.159903 PHYPLL
9086 23:08:46.163279 DPM_CONTROL_AFTERK: ON
9087 23:08:46.163359 PER_BANK_REFRESH: ON
9088 23:08:46.166259 REFRESH_OVERHEAD_REDUCTION: ON
9089 23:08:46.169744 CMD_PICG_NEW_MODE: OFF
9090 23:08:46.169824 XRTWTW_NEW_MODE: ON
9091 23:08:46.172812 XRTRTR_NEW_MODE: ON
9092 23:08:46.172892 TX_TRACKING: ON
9093 23:08:46.176482 RDSEL_TRACKING: OFF
9094 23:08:46.176561 DQS Precalculation for DVFS: ON
9095 23:08:46.179631 RX_TRACKING: OFF
9096 23:08:46.179710 HW_GATING DBG: ON
9097 23:08:46.183074 ZQCS_ENABLE_LP4: ON
9098 23:08:46.186479 RX_PICG_NEW_MODE: ON
9099 23:08:46.186559 TX_PICG_NEW_MODE: ON
9100 23:08:46.189769 ENABLE_RX_DCM_DPHY: ON
9101 23:08:46.192653 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9102 23:08:46.192733 DUMMY_READ_FOR_TRACKING: OFF
9103 23:08:46.196210 !!! SPM_CONTROL_AFTERK: OFF
9104 23:08:46.199865 !!! SPM could not control APHY
9105 23:08:46.202787 IMPEDANCE_TRACKING: ON
9106 23:08:46.202866 TEMP_SENSOR: ON
9107 23:08:46.206166 HW_SAVE_FOR_SR: OFF
9108 23:08:46.206246 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9109 23:08:46.212837 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9110 23:08:46.212923 Read ODT Tracking: ON
9111 23:08:46.216376 Refresh Rate DeBounce: ON
9112 23:08:46.219498 DFS_NO_QUEUE_FLUSH: ON
9113 23:08:46.223169 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9114 23:08:46.223252 ENABLE_DFS_RUNTIME_MRW: OFF
9115 23:08:46.226202 DDR_RESERVE_NEW_MODE: ON
9116 23:08:46.229742 MR_CBT_SWITCH_FREQ: ON
9117 23:08:46.229823 =========================
9118 23:08:46.249627 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9119 23:08:46.252238 dram_init: ddr_geometry: 2
9120 23:08:46.270687 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9121 23:08:46.274153 dram_init: dram init end (result: 0)
9122 23:08:46.280544 DRAM-K: Full calibration passed in 24412 msecs
9123 23:08:46.284139 MRC: failed to locate region type 0.
9124 23:08:46.284221 DRAM rank0 size:0x100000000,
9125 23:08:46.287288 DRAM rank1 size=0x100000000
9126 23:08:46.296985 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9127 23:08:46.303730 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9128 23:08:46.310809 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9129 23:08:46.317249 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9130 23:08:46.320640 DRAM rank0 size:0x100000000,
9131 23:08:46.323822 DRAM rank1 size=0x100000000
9132 23:08:46.323908 CBMEM:
9133 23:08:46.327412 IMD: root @ 0xfffff000 254 entries.
9134 23:08:46.330569 IMD: root @ 0xffffec00 62 entries.
9135 23:08:46.333568 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9136 23:08:46.337463 WARNING: RO_VPD is uninitialized or empty.
9137 23:08:46.343667 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9138 23:08:46.350752 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9139 23:08:46.363567 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9140 23:08:46.375380 BS: romstage times (exec / console): total (unknown) / 23952 ms
9141 23:08:46.375476
9142 23:08:46.375542
9143 23:08:46.385015 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9144 23:08:46.387918 ARM64: Exception handlers installed.
9145 23:08:46.391642 ARM64: Testing exception
9146 23:08:46.394690 ARM64: Done test exception
9147 23:08:46.394770 Enumerating buses...
9148 23:08:46.398233 Show all devs... Before device enumeration.
9149 23:08:46.401680 Root Device: enabled 1
9150 23:08:46.404436 CPU_CLUSTER: 0: enabled 1
9151 23:08:46.404516 CPU: 00: enabled 1
9152 23:08:46.408034 Compare with tree...
9153 23:08:46.408116 Root Device: enabled 1
9154 23:08:46.411827 CPU_CLUSTER: 0: enabled 1
9155 23:08:46.415149 CPU: 00: enabled 1
9156 23:08:46.415231 Root Device scanning...
9157 23:08:46.417890 scan_static_bus for Root Device
9158 23:08:46.421195 CPU_CLUSTER: 0 enabled
9159 23:08:46.424774 scan_static_bus for Root Device done
9160 23:08:46.428256 scan_bus: bus Root Device finished in 8 msecs
9161 23:08:46.428338 done
9162 23:08:46.434655 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9163 23:08:46.438089 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9164 23:08:46.444574 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9165 23:08:46.447678 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9166 23:08:46.451098 Allocating resources...
9167 23:08:46.453960 Reading resources...
9168 23:08:46.457368 Root Device read_resources bus 0 link: 0
9169 23:08:46.460661 DRAM rank0 size:0x100000000,
9170 23:08:46.460742 DRAM rank1 size=0x100000000
9171 23:08:46.463894 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9172 23:08:46.467889 CPU: 00 missing read_resources
9173 23:08:46.474199 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9174 23:08:46.477491 Root Device read_resources bus 0 link: 0 done
9175 23:08:46.477573 Done reading resources.
9176 23:08:46.484394 Show resources in subtree (Root Device)...After reading.
9177 23:08:46.487428 Root Device child on link 0 CPU_CLUSTER: 0
9178 23:08:46.490835 CPU_CLUSTER: 0 child on link 0 CPU: 00
9179 23:08:46.500646 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9180 23:08:46.500729 CPU: 00
9181 23:08:46.504013 Root Device assign_resources, bus 0 link: 0
9182 23:08:46.507552 CPU_CLUSTER: 0 missing set_resources
9183 23:08:46.513972 Root Device assign_resources, bus 0 link: 0 done
9184 23:08:46.514053 Done setting resources.
9185 23:08:46.520683 Show resources in subtree (Root Device)...After assigning values.
9186 23:08:46.523757 Root Device child on link 0 CPU_CLUSTER: 0
9187 23:08:46.527509 CPU_CLUSTER: 0 child on link 0 CPU: 00
9188 23:08:46.537165 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9189 23:08:46.537248 CPU: 00
9190 23:08:46.540672 Done allocating resources.
9191 23:08:46.547272 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9192 23:08:46.547355 Enabling resources...
9193 23:08:46.547420 done.
9194 23:08:46.553503 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9195 23:08:46.553630 Initializing devices...
9196 23:08:46.556698 Root Device init
9197 23:08:46.556779 init hardware done!
9198 23:08:46.560427 0x00000018: ctrlr->caps
9199 23:08:46.563394 52.000 MHz: ctrlr->f_max
9200 23:08:46.563480 0.400 MHz: ctrlr->f_min
9201 23:08:46.566644 0x40ff8080: ctrlr->voltages
9202 23:08:46.569991 sclk: 390625
9203 23:08:46.570084 Bus Width = 1
9204 23:08:46.570150 sclk: 390625
9205 23:08:46.573625 Bus Width = 1
9206 23:08:46.573716 Early init status = 3
9207 23:08:46.580179 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9208 23:08:46.583696 in-header: 03 fc 00 00 01 00 00 00
9209 23:08:46.586885 in-data: 00
9210 23:08:46.590197 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9211 23:08:46.593894 in-header: 03 fd 00 00 00 00 00 00
9212 23:08:46.597566 in-data:
9213 23:08:46.600126 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9214 23:08:46.604265 in-header: 03 fc 00 00 01 00 00 00
9215 23:08:46.607761 in-data: 00
9216 23:08:46.611064 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9217 23:08:46.616517 in-header: 03 fd 00 00 00 00 00 00
9218 23:08:46.619835 in-data:
9219 23:08:46.623249 [SSUSB] Setting up USB HOST controller...
9220 23:08:46.626476 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9221 23:08:46.629909 [SSUSB] phy power-on done.
9222 23:08:46.633378 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9223 23:08:46.640094 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9224 23:08:46.642916 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9225 23:08:46.650026 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9226 23:08:46.656393 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9227 23:08:46.662927 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9228 23:08:46.669582 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9229 23:08:46.676258 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9230 23:08:46.679758 SPM: binary array size = 0x9dc
9231 23:08:46.683181 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9232 23:08:46.689376 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9233 23:08:46.696585 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9234 23:08:46.702631 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9235 23:08:46.705623 configure_display: Starting display init
9236 23:08:46.739562 anx7625_power_on_init: Init interface.
9237 23:08:46.743167 anx7625_disable_pd_protocol: Disabled PD feature.
9238 23:08:46.746682 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9239 23:08:46.774050 anx7625_start_dp_work: Secure OCM version=00
9240 23:08:46.777539 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9241 23:08:46.792571 sp_tx_get_edid_block: EDID Block = 1
9242 23:08:46.894968 Extracted contents:
9243 23:08:46.898791 header: 00 ff ff ff ff ff ff 00
9244 23:08:46.901329 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9245 23:08:46.905097 version: 01 04
9246 23:08:46.907973 basic params: 95 1f 11 78 0a
9247 23:08:46.911476 chroma info: 76 90 94 55 54 90 27 21 50 54
9248 23:08:46.914650 established: 00 00 00
9249 23:08:46.921707 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9250 23:08:46.924701 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9251 23:08:46.931376 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9252 23:08:46.938317 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9253 23:08:46.944358 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9254 23:08:46.948190 extensions: 00
9255 23:08:46.948270 checksum: fb
9256 23:08:46.948332
9257 23:08:46.951387 Manufacturer: IVO Model 57d Serial Number 0
9258 23:08:46.954484 Made week 0 of 2020
9259 23:08:46.954563 EDID version: 1.4
9260 23:08:46.957717 Digital display
9261 23:08:46.961086 6 bits per primary color channel
9262 23:08:46.961167 DisplayPort interface
9263 23:08:46.964854 Maximum image size: 31 cm x 17 cm
9264 23:08:46.968433 Gamma: 220%
9265 23:08:46.968512 Check DPMS levels
9266 23:08:46.971292 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9267 23:08:46.977469 First detailed timing is preferred timing
9268 23:08:46.977566 Established timings supported:
9269 23:08:46.981059 Standard timings supported:
9270 23:08:46.984214 Detailed timings
9271 23:08:46.987565 Hex of detail: 383680a07038204018303c0035ae10000019
9272 23:08:46.991142 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9273 23:08:46.997452 0780 0798 07c8 0820 hborder 0
9274 23:08:47.000842 0438 043b 0447 0458 vborder 0
9275 23:08:47.004507 -hsync -vsync
9276 23:08:47.004588 Did detailed timing
9277 23:08:47.010852 Hex of detail: 000000000000000000000000000000000000
9278 23:08:47.010932 Manufacturer-specified data, tag 0
9279 23:08:47.017481 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9280 23:08:47.020775 ASCII string: InfoVision
9281 23:08:47.024138 Hex of detail: 000000fe00523134304e574635205248200a
9282 23:08:47.027598 ASCII string: R140NWF5 RH
9283 23:08:47.027680 Checksum
9284 23:08:47.030967 Checksum: 0xfb (valid)
9285 23:08:47.034672 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9286 23:08:47.037292 DSI data_rate: 832800000 bps
9287 23:08:47.044628 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9288 23:08:47.047437 anx7625_parse_edid: pixelclock(138800).
9289 23:08:47.051065 hactive(1920), hsync(48), hfp(24), hbp(88)
9290 23:08:47.053945 vactive(1080), vsync(12), vfp(3), vbp(17)
9291 23:08:47.057435 anx7625_dsi_config: config dsi.
9292 23:08:47.064085 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9293 23:08:47.076953 anx7625_dsi_config: success to config DSI
9294 23:08:47.080365 anx7625_dp_start: MIPI phy setup OK.
9295 23:08:47.083679 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9296 23:08:47.087142 mtk_ddp_mode_set invalid vrefresh 60
9297 23:08:47.090287 main_disp_path_setup
9298 23:08:47.090406 ovl_layer_smi_id_en
9299 23:08:47.093467 ovl_layer_smi_id_en
9300 23:08:47.093548 ccorr_config
9301 23:08:47.093623 aal_config
9302 23:08:47.096729 gamma_config
9303 23:08:47.096809 postmask_config
9304 23:08:47.099939 dither_config
9305 23:08:47.103106 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9306 23:08:47.109775 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9307 23:08:47.113449 Root Device init finished in 553 msecs
9308 23:08:47.116606 CPU_CLUSTER: 0 init
9309 23:08:47.123579 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9310 23:08:47.126448 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9311 23:08:47.130442 APU_MBOX 0x190000b0 = 0x10001
9312 23:08:47.133456 APU_MBOX 0x190001b0 = 0x10001
9313 23:08:47.136513 APU_MBOX 0x190005b0 = 0x10001
9314 23:08:47.140169 APU_MBOX 0x190006b0 = 0x10001
9315 23:08:47.143132 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9316 23:08:47.155974 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9317 23:08:47.168690 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9318 23:08:47.175036 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9319 23:08:47.186512 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9320 23:08:47.195665 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9321 23:08:47.199059 CPU_CLUSTER: 0 init finished in 81 msecs
9322 23:08:47.202027 Devices initialized
9323 23:08:47.205570 Show all devs... After init.
9324 23:08:47.205683 Root Device: enabled 1
9325 23:08:47.208776 CPU_CLUSTER: 0: enabled 1
9326 23:08:47.212535 CPU: 00: enabled 1
9327 23:08:47.215554 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9328 23:08:47.218978 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9329 23:08:47.222297 ELOG: NV offset 0x57f000 size 0x1000
9330 23:08:47.229258 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9331 23:08:47.235258 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9332 23:08:47.238665 ELOG: Event(17) added with size 13 at 2023-12-01 23:06:33 UTC
9333 23:08:47.242230 out: cmd=0x121: 03 db 21 01 00 00 00 00
9334 23:08:47.245778 in-header: 03 09 00 00 2c 00 00 00
9335 23:08:47.259128 in-data: 56 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9336 23:08:47.266290 ELOG: Event(A1) added with size 10 at 2023-12-01 23:06:33 UTC
9337 23:08:47.272813 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9338 23:08:47.276257 ELOG: Event(A0) added with size 9 at 2023-12-01 23:06:33 UTC
9339 23:08:47.282702 elog_add_boot_reason: Logged dev mode boot
9340 23:08:47.286302 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9341 23:08:47.289376 Finalize devices...
9342 23:08:47.289457 Devices finalized
9343 23:08:47.296325 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9344 23:08:47.299267 Writing coreboot table at 0xffe64000
9345 23:08:47.302670 0. 000000000010a000-0000000000113fff: RAMSTAGE
9346 23:08:47.306357 1. 0000000040000000-00000000400fffff: RAM
9347 23:08:47.309855 2. 0000000040100000-000000004032afff: RAMSTAGE
9348 23:08:47.312682 3. 000000004032b000-00000000545fffff: RAM
9349 23:08:47.319232 4. 0000000054600000-000000005465ffff: BL31
9350 23:08:47.322676 5. 0000000054660000-00000000ffe63fff: RAM
9351 23:08:47.326106 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9352 23:08:47.332884 7. 0000000100000000-000000023fffffff: RAM
9353 23:08:47.332969 Passing 5 GPIOs to payload:
9354 23:08:47.339577 NAME | PORT | POLARITY | VALUE
9355 23:08:47.342658 EC in RW | 0x000000aa | low | undefined
9356 23:08:47.346267 EC interrupt | 0x00000005 | low | undefined
9357 23:08:47.353139 TPM interrupt | 0x000000ab | high | undefined
9358 23:08:47.356143 SD card detect | 0x00000011 | high | undefined
9359 23:08:47.362869 speaker enable | 0x00000093 | high | undefined
9360 23:08:47.366378 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9361 23:08:47.369260 in-header: 03 f9 00 00 02 00 00 00
9362 23:08:47.369343 in-data: 02 00
9363 23:08:47.372602 ADC[4]: Raw value=904357 ID=7
9364 23:08:47.376381 ADC[3]: Raw value=213441 ID=1
9365 23:08:47.376463 RAM Code: 0x71
9366 23:08:47.379474 ADC[6]: Raw value=75701 ID=0
9367 23:08:47.382657 ADC[5]: Raw value=213072 ID=1
9368 23:08:47.382738 SKU Code: 0x1
9369 23:08:47.389048 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum dbc0
9370 23:08:47.392788 coreboot table: 964 bytes.
9371 23:08:47.395651 IMD ROOT 0. 0xfffff000 0x00001000
9372 23:08:47.399595 IMD SMALL 1. 0xffffe000 0x00001000
9373 23:08:47.402468 RO MCACHE 2. 0xffffc000 0x00001104
9374 23:08:47.405991 CONSOLE 3. 0xfff7c000 0x00080000
9375 23:08:47.409174 FMAP 4. 0xfff7b000 0x00000452
9376 23:08:47.412743 TIME STAMP 5. 0xfff7a000 0x00000910
9377 23:08:47.415738 VBOOT WORK 6. 0xfff66000 0x00014000
9378 23:08:47.419226 RAMOOPS 7. 0xffe66000 0x00100000
9379 23:08:47.422851 COREBOOT 8. 0xffe64000 0x00002000
9380 23:08:47.422933 IMD small region:
9381 23:08:47.425810 IMD ROOT 0. 0xffffec00 0x00000400
9382 23:08:47.429339 VPD 1. 0xffffeb80 0x0000006c
9383 23:08:47.432749 MMC STATUS 2. 0xffffeb60 0x00000004
9384 23:08:47.438887 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9385 23:08:47.438972 Probing TPM: done!
9386 23:08:47.446013 Connected to device vid:did:rid of 1ae0:0028:00
9387 23:08:47.452378 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9388 23:08:47.455702 Initialized TPM device CR50 revision 0
9389 23:08:47.459991 Checking cr50 for pending updates
9390 23:08:47.465230 Reading cr50 TPM mode
9391 23:08:47.474208 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9392 23:08:47.480603 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9393 23:08:47.521050 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9394 23:08:47.523861 Checking segment from ROM address 0x40100000
9395 23:08:47.527326 Checking segment from ROM address 0x4010001c
9396 23:08:47.533934 Loading segment from ROM address 0x40100000
9397 23:08:47.534019 code (compression=0)
9398 23:08:47.544361 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9399 23:08:47.550892 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9400 23:08:47.550980 it's not compressed!
9401 23:08:47.557487 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9402 23:08:47.561012 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9403 23:08:47.581395 Loading segment from ROM address 0x4010001c
9404 23:08:47.581490 Entry Point 0x80000000
9405 23:08:47.584510 Loaded segments
9406 23:08:47.587826 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9407 23:08:47.594580 Jumping to boot code at 0x80000000(0xffe64000)
9408 23:08:47.601550 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9409 23:08:47.608046 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9410 23:08:47.616020 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9411 23:08:47.619328 Checking segment from ROM address 0x40100000
9412 23:08:47.622496 Checking segment from ROM address 0x4010001c
9413 23:08:47.629275 Loading segment from ROM address 0x40100000
9414 23:08:47.629382 code (compression=1)
9415 23:08:47.635735 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9416 23:08:47.645657 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9417 23:08:47.645756 using LZMA
9418 23:08:47.654542 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9419 23:08:47.660622 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9420 23:08:47.664217 Loading segment from ROM address 0x4010001c
9421 23:08:47.664299 Entry Point 0x54601000
9422 23:08:47.667815 Loaded segments
9423 23:08:47.670514 NOTICE: MT8192 bl31_setup
9424 23:08:47.677500 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9425 23:08:47.680970 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9426 23:08:47.684233 WARNING: region 0:
9427 23:08:47.687575 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9428 23:08:47.687656 WARNING: region 1:
9429 23:08:47.694188 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9430 23:08:47.697942 WARNING: region 2:
9431 23:08:47.701068 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9432 23:08:47.704493 WARNING: region 3:
9433 23:08:47.707614 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9434 23:08:47.710955 WARNING: region 4:
9435 23:08:47.714202 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9436 23:08:47.718016 WARNING: region 5:
9437 23:08:47.721210 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9438 23:08:47.724646 WARNING: region 6:
9439 23:08:47.727594 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9440 23:08:47.727676 WARNING: region 7:
9441 23:08:47.734601 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9442 23:08:47.741488 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9443 23:08:47.744563 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9444 23:08:47.748180 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9445 23:08:47.754747 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9446 23:08:47.758027 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9447 23:08:47.761028 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9448 23:08:47.767635 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9449 23:08:47.771258 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9450 23:08:47.775147 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9451 23:08:47.781365 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9452 23:08:47.784957 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9453 23:08:47.787874 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9454 23:08:47.794897 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9455 23:08:47.798311 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9456 23:08:47.804973 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9457 23:08:47.808230 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9458 23:08:47.811291 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9459 23:08:47.818222 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9460 23:08:47.821538 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9461 23:08:47.825183 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9462 23:08:47.831869 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9463 23:08:47.834816 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9464 23:08:47.841560 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9465 23:08:47.844788 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9466 23:08:47.848669 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9467 23:08:47.855036 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9468 23:08:47.858525 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9469 23:08:47.862060 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9470 23:08:47.868320 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9471 23:08:47.871731 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9472 23:08:47.878491 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9473 23:08:47.881618 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9474 23:08:47.885431 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9475 23:08:47.891914 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9476 23:08:47.895410 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9477 23:08:47.898851 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9478 23:08:47.901885 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9479 23:08:47.905558 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9480 23:08:47.912102 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9481 23:08:47.915420 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9482 23:08:47.918662 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9483 23:08:47.922085 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9484 23:08:47.928688 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9485 23:08:47.932158 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9486 23:08:47.935680 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9487 23:08:47.938761 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9488 23:08:47.945534 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9489 23:08:47.948989 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9490 23:08:47.952442 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9491 23:08:47.958813 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9492 23:08:47.962022 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9493 23:08:47.969121 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9494 23:08:47.972309 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9495 23:08:47.976001 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9496 23:08:47.982439 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9497 23:08:47.985771 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9498 23:08:47.992873 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9499 23:08:47.995508 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9500 23:08:48.002532 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9501 23:08:48.005470 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9502 23:08:48.008973 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9503 23:08:48.015922 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9504 23:08:48.018899 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9505 23:08:48.026249 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9506 23:08:48.029014 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9507 23:08:48.036195 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9508 23:08:48.039030 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9509 23:08:48.042675 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9510 23:08:48.049393 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9511 23:08:48.052528 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9512 23:08:48.059216 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9513 23:08:48.062525 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9514 23:08:48.069477 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9515 23:08:48.072975 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9516 23:08:48.075979 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9517 23:08:48.082720 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9518 23:08:48.085902 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9519 23:08:48.092578 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9520 23:08:48.096296 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9521 23:08:48.102692 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9522 23:08:48.106269 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9523 23:08:48.109682 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9524 23:08:48.116062 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9525 23:08:48.119418 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9526 23:08:48.125733 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9527 23:08:48.129156 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9528 23:08:48.135745 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9529 23:08:48.139458 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9530 23:08:48.142404 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9531 23:08:48.149243 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9532 23:08:48.152627 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9533 23:08:48.159723 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9534 23:08:48.162641 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9535 23:08:48.169329 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9536 23:08:48.172371 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9537 23:08:48.176249 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9538 23:08:48.182557 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9539 23:08:48.185997 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9540 23:08:48.189158 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9541 23:08:48.192319 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9542 23:08:48.199506 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9543 23:08:48.202690 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9544 23:08:48.209609 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9545 23:08:48.212803 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9546 23:08:48.215825 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9547 23:08:48.222488 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9548 23:08:48.226027 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9549 23:08:48.229270 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9550 23:08:48.236015 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9551 23:08:48.239441 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9552 23:08:48.246154 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9553 23:08:48.249329 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9554 23:08:48.253003 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9555 23:08:48.259232 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9556 23:08:48.262691 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9557 23:08:48.269863 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9558 23:08:48.272675 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9559 23:08:48.278404 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9560 23:08:48.279414 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9561 23:08:48.285950 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9562 23:08:48.289347 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9563 23:08:48.292885 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9564 23:08:48.296381 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9565 23:08:48.302568 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9566 23:08:48.306177 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9567 23:08:48.309312 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9568 23:08:48.316464 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9569 23:08:48.319645 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9570 23:08:48.326305 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9571 23:08:48.330003 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9572 23:08:48.332855 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9573 23:08:48.339463 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9574 23:08:48.342864 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9575 23:08:48.349512 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9576 23:08:48.353001 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9577 23:08:48.356179 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9578 23:08:48.363158 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9579 23:08:48.366404 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9580 23:08:48.370025 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9581 23:08:48.376247 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9582 23:08:48.379944 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9583 23:08:48.386471 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9584 23:08:48.389517 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9585 23:08:48.392889 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9586 23:08:48.400086 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9587 23:08:48.403226 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9588 23:08:48.406991 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9589 23:08:48.413215 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9590 23:08:48.416746 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9591 23:08:48.423461 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9592 23:08:48.426671 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9593 23:08:48.430262 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9594 23:08:48.436667 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9595 23:08:48.440303 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9596 23:08:48.446755 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9597 23:08:48.449658 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9598 23:08:48.453599 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9599 23:08:48.460041 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9600 23:08:48.463425 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9601 23:08:48.466568 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9602 23:08:48.473524 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9603 23:08:48.476959 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9604 23:08:48.483407 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9605 23:08:48.486626 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9606 23:08:48.489982 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9607 23:08:48.496330 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9608 23:08:48.499462 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9609 23:08:48.506369 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9610 23:08:48.509671 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9611 23:08:48.513442 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9612 23:08:48.519703 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9613 23:08:48.522935 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9614 23:08:48.526283 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9615 23:08:48.533052 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9616 23:08:48.536617 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9617 23:08:48.543363 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9618 23:08:48.546047 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9619 23:08:48.549595 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9620 23:08:48.556264 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9621 23:08:48.559744 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9622 23:08:48.566439 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9623 23:08:48.570004 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9624 23:08:48.573018 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9625 23:08:48.579448 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9626 23:08:48.582895 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9627 23:08:48.589391 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9628 23:08:48.593029 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9629 23:08:48.596659 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9630 23:08:48.602948 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9631 23:08:48.606048 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9632 23:08:48.613024 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9633 23:08:48.616138 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9634 23:08:48.622480 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9635 23:08:48.626030 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9636 23:08:48.629172 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9637 23:08:48.635798 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9638 23:08:48.639004 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9639 23:08:48.645775 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9640 23:08:48.648836 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9641 23:08:48.652550 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9642 23:08:48.659237 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9643 23:08:48.662708 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9644 23:08:48.668958 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9645 23:08:48.672549 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9646 23:08:48.675585 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9647 23:08:48.682568 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9648 23:08:48.685967 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9649 23:08:48.692412 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9650 23:08:48.695544 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9651 23:08:48.702524 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9652 23:08:48.705434 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9653 23:08:48.709130 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9654 23:08:48.715641 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9655 23:08:48.718723 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9656 23:08:48.725401 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9657 23:08:48.728618 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9658 23:08:48.732175 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9659 23:08:48.738831 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9660 23:08:48.742043 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9661 23:08:48.748635 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9662 23:08:48.752334 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9663 23:08:48.756016 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9664 23:08:48.762501 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9665 23:08:48.765298 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9666 23:08:48.771907 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9667 23:08:48.775269 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9668 23:08:48.782252 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9669 23:08:48.785561 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9670 23:08:48.788823 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9671 23:08:48.795705 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9672 23:08:48.798607 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9673 23:08:48.802675 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9674 23:08:48.805472 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9675 23:08:48.811984 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9676 23:08:48.815500 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9677 23:08:48.818420 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9678 23:08:48.825472 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9679 23:08:48.828548 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9680 23:08:48.832140 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9681 23:08:48.838530 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9682 23:08:48.841427 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9683 23:08:48.848559 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9684 23:08:48.851772 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9685 23:08:48.854859 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9686 23:08:48.861780 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9687 23:08:48.865291 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9688 23:08:48.868209 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9689 23:08:48.874875 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9690 23:08:48.878448 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9691 23:08:48.881509 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9692 23:08:48.888234 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9693 23:08:48.891531 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9694 23:08:48.898373 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9695 23:08:48.901494 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9696 23:08:48.905287 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9697 23:08:48.911325 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9698 23:08:48.915146 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9699 23:08:48.918462 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9700 23:08:48.924558 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9701 23:08:48.928182 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9702 23:08:48.931072 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9703 23:08:48.937807 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9704 23:08:48.941420 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9705 23:08:48.944882 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9706 23:08:48.951372 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9707 23:08:48.954532 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9708 23:08:48.961069 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9709 23:08:48.964271 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9710 23:08:48.967489 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9711 23:08:48.974365 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9712 23:08:48.977856 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9713 23:08:48.981368 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9714 23:08:48.984131 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9715 23:08:48.988123 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9716 23:08:48.994311 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9717 23:08:48.997681 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9718 23:08:49.000976 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9719 23:08:49.004532 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9720 23:08:49.011006 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9721 23:08:49.014650 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9722 23:08:49.017609 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9723 23:08:49.024384 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9724 23:08:49.027696 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9725 23:08:49.031018 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9726 23:08:49.037172 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9727 23:08:49.040855 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9728 23:08:49.048003 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9729 23:08:49.050441 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9730 23:08:49.057261 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9731 23:08:49.061200 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9732 23:08:49.063882 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9733 23:08:49.070674 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9734 23:08:49.074094 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9735 23:08:49.080510 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9736 23:08:49.084227 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9737 23:08:49.087359 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9738 23:08:49.093522 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9739 23:08:49.097008 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9740 23:08:49.103848 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9741 23:08:49.107383 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9742 23:08:49.110105 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9743 23:08:49.116488 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9744 23:08:49.120077 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9745 23:08:49.126738 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9746 23:08:49.130314 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9747 23:08:49.136873 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9748 23:08:49.140270 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9749 23:08:49.143060 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9750 23:08:49.150381 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9751 23:08:49.153340 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9752 23:08:49.159881 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9753 23:08:49.163338 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9754 23:08:49.166822 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9755 23:08:49.173049 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9756 23:08:49.176699 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9757 23:08:49.183221 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9758 23:08:49.186346 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9759 23:08:49.190053 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9760 23:08:49.196223 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9761 23:08:49.199865 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9762 23:08:49.206507 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9763 23:08:49.210171 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9764 23:08:49.212610 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9765 23:08:49.219458 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9766 23:08:49.222959 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9767 23:08:49.229399 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9768 23:08:49.232848 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9769 23:08:49.239358 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9770 23:08:49.242720 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9771 23:08:49.246709 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9772 23:08:49.253086 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9773 23:08:49.256093 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9774 23:08:49.262675 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9775 23:08:49.266173 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9776 23:08:49.269260 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9777 23:08:49.275734 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9778 23:08:49.279327 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9779 23:08:49.285860 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9780 23:08:49.288948 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9781 23:08:49.292753 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9782 23:08:49.299530 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9783 23:08:49.302436 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9784 23:08:49.309481 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9785 23:08:49.312491 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9786 23:08:49.319466 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9787 23:08:49.322519 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9788 23:08:49.326122 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9789 23:08:49.332247 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9790 23:08:49.335996 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9791 23:08:49.342450 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9792 23:08:49.346055 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9793 23:08:49.349132 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9794 23:08:49.355694 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9795 23:08:49.359297 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9796 23:08:49.365698 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9797 23:08:49.369334 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9798 23:08:49.372201 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9799 23:08:49.379404 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9800 23:08:49.382571 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9801 23:08:49.389303 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9802 23:08:49.392145 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9803 23:08:49.398558 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9804 23:08:49.402319 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9805 23:08:49.405320 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9806 23:08:49.412185 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9807 23:08:49.415792 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9808 23:08:49.422146 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9809 23:08:49.425765 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9810 23:08:49.431998 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9811 23:08:49.435435 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9812 23:08:49.438442 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9813 23:08:49.445411 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9814 23:08:49.448440 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9815 23:08:49.455220 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9816 23:08:49.458594 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9817 23:08:49.465075 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9818 23:08:49.468658 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9819 23:08:49.472230 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9820 23:08:49.478700 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9821 23:08:49.481735 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9822 23:08:49.488699 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9823 23:08:49.491729 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9824 23:08:49.498586 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9825 23:08:49.501600 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9826 23:08:49.508549 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9827 23:08:49.511538 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9828 23:08:49.514790 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9829 23:08:49.521755 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9830 23:08:49.524934 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9831 23:08:49.531701 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9832 23:08:49.534954 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9833 23:08:49.541522 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9834 23:08:49.544777 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9835 23:08:49.548105 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9836 23:08:49.554531 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9837 23:08:49.558071 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9838 23:08:49.564511 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9839 23:08:49.567686 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9840 23:08:49.574869 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9841 23:08:49.578036 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9842 23:08:49.584575 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9843 23:08:49.588204 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9844 23:08:49.591182 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9845 23:08:49.597963 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9846 23:08:49.601132 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9847 23:08:49.607717 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9848 23:08:49.611130 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9849 23:08:49.617787 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9850 23:08:49.621172 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9851 23:08:49.627833 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9852 23:08:49.631468 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9853 23:08:49.638037 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9854 23:08:49.641489 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9855 23:08:49.647522 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9856 23:08:49.651156 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9857 23:08:49.654877 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9858 23:08:49.660730 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9859 23:08:49.664227 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9860 23:08:49.671029 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9861 23:08:49.674239 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9862 23:08:49.680495 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9863 23:08:49.683911 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9864 23:08:49.690995 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9865 23:08:49.693949 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9866 23:08:49.700688 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9867 23:08:49.704529 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9868 23:08:49.711031 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9869 23:08:49.714313 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9870 23:08:49.720825 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9871 23:08:49.724310 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9872 23:08:49.730587 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9873 23:08:49.734198 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9874 23:08:49.740274 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9875 23:08:49.744328 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9876 23:08:49.750833 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9877 23:08:49.750915 INFO: [APUAPC] vio 0
9878 23:08:49.757196 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9879 23:08:49.760780 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9880 23:08:49.764105 INFO: [APUAPC] D0_APC_0: 0x400510
9881 23:08:49.767411 INFO: [APUAPC] D0_APC_1: 0x0
9882 23:08:49.771019 INFO: [APUAPC] D0_APC_2: 0x1540
9883 23:08:49.773989 INFO: [APUAPC] D0_APC_3: 0x0
9884 23:08:49.777623 INFO: [APUAPC] D1_APC_0: 0xffffffff
9885 23:08:49.780757 INFO: [APUAPC] D1_APC_1: 0xffffffff
9886 23:08:49.783987 INFO: [APUAPC] D1_APC_2: 0x3fffff
9887 23:08:49.787619 INFO: [APUAPC] D1_APC_3: 0x0
9888 23:08:49.790644 INFO: [APUAPC] D2_APC_0: 0xffffffff
9889 23:08:49.794181 INFO: [APUAPC] D2_APC_1: 0xffffffff
9890 23:08:49.797286 INFO: [APUAPC] D2_APC_2: 0x3fffff
9891 23:08:49.801442 INFO: [APUAPC] D2_APC_3: 0x0
9892 23:08:49.803593 INFO: [APUAPC] D3_APC_0: 0xffffffff
9893 23:08:49.807306 INFO: [APUAPC] D3_APC_1: 0xffffffff
9894 23:08:49.810379 INFO: [APUAPC] D3_APC_2: 0x3fffff
9895 23:08:49.814312 INFO: [APUAPC] D3_APC_3: 0x0
9896 23:08:49.817301 INFO: [APUAPC] D4_APC_0: 0xffffffff
9897 23:08:49.820398 INFO: [APUAPC] D4_APC_1: 0xffffffff
9898 23:08:49.824035 INFO: [APUAPC] D4_APC_2: 0x3fffff
9899 23:08:49.824116 INFO: [APUAPC] D4_APC_3: 0x0
9900 23:08:49.830204 INFO: [APUAPC] D5_APC_0: 0xffffffff
9901 23:08:49.833411 INFO: [APUAPC] D5_APC_1: 0xffffffff
9902 23:08:49.837252 INFO: [APUAPC] D5_APC_2: 0x3fffff
9903 23:08:49.837333 INFO: [APUAPC] D5_APC_3: 0x0
9904 23:08:49.840192 INFO: [APUAPC] D6_APC_0: 0xffffffff
9905 23:08:49.843603 INFO: [APUAPC] D6_APC_1: 0xffffffff
9906 23:08:49.847122 INFO: [APUAPC] D6_APC_2: 0x3fffff
9907 23:08:49.850143 INFO: [APUAPC] D6_APC_3: 0x0
9908 23:08:49.853401 INFO: [APUAPC] D7_APC_0: 0xffffffff
9909 23:08:49.856721 INFO: [APUAPC] D7_APC_1: 0xffffffff
9910 23:08:49.859905 INFO: [APUAPC] D7_APC_2: 0x3fffff
9911 23:08:49.863384 INFO: [APUAPC] D7_APC_3: 0x0
9912 23:08:49.867046 INFO: [APUAPC] D8_APC_0: 0xffffffff
9913 23:08:49.869994 INFO: [APUAPC] D8_APC_1: 0xffffffff
9914 23:08:49.873753 INFO: [APUAPC] D8_APC_2: 0x3fffff
9915 23:08:49.876614 INFO: [APUAPC] D8_APC_3: 0x0
9916 23:08:49.880064 INFO: [APUAPC] D9_APC_0: 0xffffffff
9917 23:08:49.883200 INFO: [APUAPC] D9_APC_1: 0xffffffff
9918 23:08:49.886642 INFO: [APUAPC] D9_APC_2: 0x3fffff
9919 23:08:49.890426 INFO: [APUAPC] D9_APC_3: 0x0
9920 23:08:49.893345 INFO: [APUAPC] D10_APC_0: 0xffffffff
9921 23:08:49.896941 INFO: [APUAPC] D10_APC_1: 0xffffffff
9922 23:08:49.900150 INFO: [APUAPC] D10_APC_2: 0x3fffff
9923 23:08:49.903569 INFO: [APUAPC] D10_APC_3: 0x0
9924 23:08:49.906968 INFO: [APUAPC] D11_APC_0: 0xffffffff
9925 23:08:49.909841 INFO: [APUAPC] D11_APC_1: 0xffffffff
9926 23:08:49.913232 INFO: [APUAPC] D11_APC_2: 0x3fffff
9927 23:08:49.917128 INFO: [APUAPC] D11_APC_3: 0x0
9928 23:08:49.919970 INFO: [APUAPC] D12_APC_0: 0xffffffff
9929 23:08:49.923557 INFO: [APUAPC] D12_APC_1: 0xffffffff
9930 23:08:49.926429 INFO: [APUAPC] D12_APC_2: 0x3fffff
9931 23:08:49.930374 INFO: [APUAPC] D12_APC_3: 0x0
9932 23:08:49.933069 INFO: [APUAPC] D13_APC_0: 0xffffffff
9933 23:08:49.936466 INFO: [APUAPC] D13_APC_1: 0xffffffff
9934 23:08:49.940039 INFO: [APUAPC] D13_APC_2: 0x3fffff
9935 23:08:49.943195 INFO: [APUAPC] D13_APC_3: 0x0
9936 23:08:49.946740 INFO: [APUAPC] D14_APC_0: 0xffffffff
9937 23:08:49.949868 INFO: [APUAPC] D14_APC_1: 0xffffffff
9938 23:08:49.953326 INFO: [APUAPC] D14_APC_2: 0x3fffff
9939 23:08:49.956199 INFO: [APUAPC] D14_APC_3: 0x0
9940 23:08:49.959908 INFO: [APUAPC] D15_APC_0: 0xffffffff
9941 23:08:49.963483 INFO: [APUAPC] D15_APC_1: 0xffffffff
9942 23:08:49.966782 INFO: [APUAPC] D15_APC_2: 0x3fffff
9943 23:08:49.969512 INFO: [APUAPC] D15_APC_3: 0x0
9944 23:08:49.973170 INFO: [APUAPC] APC_CON: 0x4
9945 23:08:49.976386 INFO: [NOCDAPC] D0_APC_0: 0x0
9946 23:08:49.979967 INFO: [NOCDAPC] D0_APC_1: 0x0
9947 23:08:49.983212 INFO: [NOCDAPC] D1_APC_0: 0x0
9948 23:08:49.986334 INFO: [NOCDAPC] D1_APC_1: 0xfff
9949 23:08:49.986414 INFO: [NOCDAPC] D2_APC_0: 0x0
9950 23:08:49.989908 INFO: [NOCDAPC] D2_APC_1: 0xfff
9951 23:08:49.992975 INFO: [NOCDAPC] D3_APC_0: 0x0
9952 23:08:49.996396 INFO: [NOCDAPC] D3_APC_1: 0xfff
9953 23:08:49.999384 INFO: [NOCDAPC] D4_APC_0: 0x0
9954 23:08:50.003115 INFO: [NOCDAPC] D4_APC_1: 0xfff
9955 23:08:50.006179 INFO: [NOCDAPC] D5_APC_0: 0x0
9956 23:08:50.009938 INFO: [NOCDAPC] D5_APC_1: 0xfff
9957 23:08:50.013272 INFO: [NOCDAPC] D6_APC_0: 0x0
9958 23:08:50.016215 INFO: [NOCDAPC] D6_APC_1: 0xfff
9959 23:08:50.019703 INFO: [NOCDAPC] D7_APC_0: 0x0
9960 23:08:50.022838 INFO: [NOCDAPC] D7_APC_1: 0xfff
9961 23:08:50.022918 INFO: [NOCDAPC] D8_APC_0: 0x0
9962 23:08:50.026180 INFO: [NOCDAPC] D8_APC_1: 0xfff
9963 23:08:50.029426 INFO: [NOCDAPC] D9_APC_0: 0x0
9964 23:08:50.033094 INFO: [NOCDAPC] D9_APC_1: 0xfff
9965 23:08:50.036029 INFO: [NOCDAPC] D10_APC_0: 0x0
9966 23:08:50.039335 INFO: [NOCDAPC] D10_APC_1: 0xfff
9967 23:08:50.042537 INFO: [NOCDAPC] D11_APC_0: 0x0
9968 23:08:50.046090 INFO: [NOCDAPC] D11_APC_1: 0xfff
9969 23:08:50.049334 INFO: [NOCDAPC] D12_APC_0: 0x0
9970 23:08:50.053048 INFO: [NOCDAPC] D12_APC_1: 0xfff
9971 23:08:50.056044 INFO: [NOCDAPC] D13_APC_0: 0x0
9972 23:08:50.059213 INFO: [NOCDAPC] D13_APC_1: 0xfff
9973 23:08:50.062973 INFO: [NOCDAPC] D14_APC_0: 0x0
9974 23:08:50.066072 INFO: [NOCDAPC] D14_APC_1: 0xfff
9975 23:08:50.066152 INFO: [NOCDAPC] D15_APC_0: 0x0
9976 23:08:50.069569 INFO: [NOCDAPC] D15_APC_1: 0xfff
9977 23:08:50.072841 INFO: [NOCDAPC] APC_CON: 0x4
9978 23:08:50.075722 INFO: [APUAPC] set_apusys_apc done
9979 23:08:50.079010 INFO: [DEVAPC] devapc_init done
9980 23:08:50.082603 INFO: GICv3 without legacy support detected.
9981 23:08:50.089172 INFO: ARM GICv3 driver initialized in EL3
9982 23:08:50.092516 INFO: Maximum SPI INTID supported: 639
9983 23:08:50.095888 INFO: BL31: Initializing runtime services
9984 23:08:50.102646 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9985 23:08:50.106043 INFO: SPM: enable CPC mode
9986 23:08:50.109468 INFO: mcdi ready for mcusys-off-idle and system suspend
9987 23:08:50.115943 INFO: BL31: Preparing for EL3 exit to normal world
9988 23:08:50.119069 INFO: Entry point address = 0x80000000
9989 23:08:50.119150 INFO: SPSR = 0x8
9990 23:08:50.125387
9991 23:08:50.125467
9992 23:08:50.125530
9993 23:08:50.128962 Starting depthcharge on Spherion...
9994 23:08:50.129042
9995 23:08:50.129106 Wipe memory regions:
9996 23:08:50.129165
9997 23:08:50.129885 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
9998 23:08:50.129982 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
9999 23:08:50.130063 Setting prompt string to ['asurada:']
10000 23:08:50.130141 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10001 23:08:50.132212 [0x00000040000000, 0x00000054600000)
10002 23:08:50.254504
10003 23:08:50.254631 [0x00000054660000, 0x00000080000000)
10004 23:08:50.514886
10005 23:08:50.515033 [0x000000821a7280, 0x000000ffe64000)
10006 23:08:51.260089
10007 23:08:51.260244 [0x00000100000000, 0x00000240000000)
10008 23:08:53.150010
10009 23:08:53.152814 Initializing XHCI USB controller at 0x11200000.
10010 23:08:54.192013
10011 23:08:54.195877 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10012 23:08:54.195985
10013 23:08:54.196051
10014 23:08:54.196112
10015 23:08:54.196392 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10017 23:08:54.296773 asurada: tftpboot 192.168.201.1 12154438/tftp-deploy-d_6wcibw/kernel/image.itb 12154438/tftp-deploy-d_6wcibw/kernel/cmdline
10018 23:08:54.296996 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10019 23:08:54.297108 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10020 23:08:54.301498 tftpboot 192.168.201.1 12154438/tftp-deploy-d_6wcibw/kernel/image.ittp-deploy-d_6wcibw/kernel/cmdline
10021 23:08:54.301618
10022 23:08:54.301684 Waiting for link
10023 23:08:54.462424
10024 23:08:54.462560 R8152: Initializing
10025 23:08:54.462630
10026 23:08:54.465213 Version 9 (ocp_data = 6010)
10027 23:08:54.465300
10028 23:08:54.468982 R8152: Done initializing
10029 23:08:54.469070
10030 23:08:54.469135 Adding net device
10031 23:08:56.413525
10032 23:08:56.413714 done.
10033 23:08:56.413800
10034 23:08:56.413875 MAC: 00:e0:4c:78:7a:aa
10035 23:08:56.413935
10036 23:08:56.417052 Sending DHCP discover... done.
10037 23:08:56.417143
10038 23:09:08.630311 Waiting for reply... done.
10039 23:09:08.630468
10040 23:09:08.630551 Sending DHCP request... done.
10041 23:09:08.633308
10042 23:09:08.633428 Waiting for reply... done.
10043 23:09:08.633496
10044 23:09:08.636593 My ip is 192.168.201.12
10045 23:09:08.636675
10046 23:09:08.640145 The DHCP server ip is 192.168.201.1
10047 23:09:08.640229
10048 23:09:08.643831 TFTP server IP predefined by user: 192.168.201.1
10049 23:09:08.643917
10050 23:09:08.650109 Bootfile predefined by user: 12154438/tftp-deploy-d_6wcibw/kernel/image.itb
10051 23:09:08.650204
10052 23:09:08.653889 Sending tftp read request... done.
10053 23:09:08.653999
10054 23:09:08.656346 Waiting for the transfer...
10055 23:09:08.656469
10056 23:09:08.919766 00000000 ################################################################
10057 23:09:08.919922
10058 23:09:09.190854 00080000 ################################################################
10059 23:09:09.191007
10060 23:09:09.454584 00100000 ################################################################
10061 23:09:09.454774
10062 23:09:09.730041 00180000 ################################################################
10063 23:09:09.730194
10064 23:09:10.013444 00200000 ################################################################
10065 23:09:10.013620
10066 23:09:10.286823 00280000 ################################################################
10067 23:09:10.287015
10068 23:09:10.554097 00300000 ################################################################
10069 23:09:10.554245
10070 23:09:10.822653 00380000 ################################################################
10071 23:09:10.822803
10072 23:09:11.113935 00400000 ################################################################
10073 23:09:11.114081
10074 23:09:11.379318 00480000 ################################################################
10075 23:09:11.379471
10076 23:09:11.649529 00500000 ################################################################
10077 23:09:11.649705
10078 23:09:11.944252 00580000 ################################################################
10079 23:09:11.944405
10080 23:09:12.239105 00600000 ################################################################
10081 23:09:12.239251
10082 23:09:12.535314 00680000 ################################################################
10083 23:09:12.535463
10084 23:09:12.789038 00700000 ################################################################
10085 23:09:12.789187
10086 23:09:13.080278 00780000 ################################################################
10087 23:09:13.080451
10088 23:09:13.347550 00800000 ################################################################
10089 23:09:13.347723
10090 23:09:13.609714 00880000 ################################################################
10091 23:09:13.609851
10092 23:09:13.868387 00900000 ################################################################
10093 23:09:13.868532
10094 23:09:14.131189 00980000 ################################################################
10095 23:09:14.131324
10096 23:09:14.388448 00a00000 ################################################################
10097 23:09:14.388585
10098 23:09:14.642929 00a80000 ################################################################
10099 23:09:14.643061
10100 23:09:14.898576 00b00000 ################################################################
10101 23:09:14.898733
10102 23:09:15.167230 00b80000 ################################################################
10103 23:09:15.167368
10104 23:09:15.430829 00c00000 ################################################################
10105 23:09:15.430978
10106 23:09:15.729249 00c80000 ################################################################
10107 23:09:15.729427
10108 23:09:16.058285 00d00000 ################################################################
10109 23:09:16.058741
10110 23:09:16.441361 00d80000 ################################################################
10111 23:09:16.441878
10112 23:09:16.819913 00e00000 ################################################################
10113 23:09:16.820509
10114 23:09:17.203285 00e80000 ################################################################
10115 23:09:17.203766
10116 23:09:17.595366 00f00000 ################################################################
10117 23:09:17.595887
10118 23:09:17.959092 00f80000 ################################################################
10119 23:09:17.959593
10120 23:09:18.320827 01000000 ################################################################
10121 23:09:18.321370
10122 23:09:18.676977 01080000 ################################################################
10123 23:09:18.677131
10124 23:09:18.938454 01100000 ################################################################
10125 23:09:18.938596
10126 23:09:19.207840 01180000 ################################################################
10127 23:09:19.207986
10128 23:09:19.457975 01200000 ################################################################
10129 23:09:19.458146
10130 23:09:19.705098 01280000 ################################################################
10131 23:09:19.705256
10132 23:09:19.950533 01300000 ################################################################
10133 23:09:19.950697
10134 23:09:20.200343 01380000 ################################################################
10135 23:09:20.200487
10136 23:09:20.456089 01400000 ################################################################
10137 23:09:20.456297
10138 23:09:20.706535 01480000 ################################################################
10139 23:09:20.706683
10140 23:09:20.955193 01500000 ################################################################
10141 23:09:20.955348
10142 23:09:21.201738 01580000 ################################################################
10143 23:09:21.201880
10144 23:09:21.447188 01600000 ################################################################
10145 23:09:21.447344
10146 23:09:21.693053 01680000 ################################################################
10147 23:09:21.693186
10148 23:09:21.940219 01700000 ################################################################
10149 23:09:21.940419
10150 23:09:22.191844 01780000 ################################################################
10151 23:09:22.191977
10152 23:09:22.437862 01800000 ################################################################
10153 23:09:22.438003
10154 23:09:22.699418 01880000 ################################################################
10155 23:09:22.699579
10156 23:09:22.949424 01900000 ################################################################
10157 23:09:22.949605
10158 23:09:23.198311 01980000 ################################################################
10159 23:09:23.198468
10160 23:09:23.447820 01a00000 ################################################################
10161 23:09:23.447963
10162 23:09:23.695119 01a80000 ################################################################
10163 23:09:23.695267
10164 23:09:23.947038 01b00000 ################################################################
10165 23:09:23.947178
10166 23:09:24.204432 01b80000 ################################################################
10167 23:09:24.204596
10168 23:09:24.465500 01c00000 ################################################################
10169 23:09:24.465684
10170 23:09:24.727153 01c80000 ################################################################
10171 23:09:24.727308
10172 23:09:24.972934 01d00000 ################################################################
10173 23:09:24.973060
10174 23:09:25.237835 01d80000 ################################################################
10175 23:09:25.237981
10176 23:09:25.487779 01e00000 ################################################################
10177 23:09:25.487945
10178 23:09:25.734016 01e80000 ################################################################
10179 23:09:25.734154
10180 23:09:25.983059 01f00000 ################################################################
10181 23:09:25.983235
10182 23:09:26.228808 01f80000 ################################################################
10183 23:09:26.228958
10184 23:09:26.485244 02000000 ################################################################
10185 23:09:26.485386
10186 23:09:26.750731 02080000 ################################################################
10187 23:09:26.750881
10188 23:09:27.011681 02100000 ################################################################
10189 23:09:27.011838
10190 23:09:27.266383 02180000 ################################################################
10191 23:09:27.266523
10192 23:09:27.525881 02200000 ################################################################
10193 23:09:27.526005
10194 23:09:27.781901 02280000 ################################################################
10195 23:09:27.782058
10196 23:09:28.029462 02300000 ################################################################
10197 23:09:28.029659
10198 23:09:28.279952 02380000 ################################################################
10199 23:09:28.280094
10200 23:09:28.530405 02400000 ################################################################
10201 23:09:28.530538
10202 23:09:28.774752 02480000 ################################################################
10203 23:09:28.774883
10204 23:09:29.023960 02500000 ################################################################
10205 23:09:29.024096
10206 23:09:29.285108 02580000 ################################################################
10207 23:09:29.285243
10208 23:09:29.544374 02600000 ################################################################
10209 23:09:29.544504
10210 23:09:29.789214 02680000 ################################################################
10211 23:09:29.789359
10212 23:09:30.034540 02700000 ################################################################
10213 23:09:30.034682
10214 23:09:30.281234 02780000 ################################################################
10215 23:09:30.281418
10216 23:09:30.525923 02800000 ################################################################
10217 23:09:30.526080
10218 23:09:30.769414 02880000 ################################################################
10219 23:09:30.769609
10220 23:09:31.016229 02900000 ################################################################
10221 23:09:31.016387
10222 23:09:31.269648 02980000 ################################################################
10223 23:09:31.269781
10224 23:09:31.514516 02a00000 ################################################################
10225 23:09:31.514667
10226 23:09:31.763552 02a80000 ################################################################
10227 23:09:31.763714
10228 23:09:32.012865 02b00000 ################################################################
10229 23:09:32.013043
10230 23:09:32.259154 02b80000 ################################################################
10231 23:09:32.259309
10232 23:09:32.511381 02c00000 ################################################################
10233 23:09:32.511581
10234 23:09:32.763030 02c80000 ################################################################
10235 23:09:32.763163
10236 23:09:33.023209 02d00000 ################################################################
10237 23:09:33.023342
10238 23:09:33.270674 02d80000 ################################################################
10239 23:09:33.270812
10240 23:09:33.517337 02e00000 ################################################################
10241 23:09:33.517476
10242 23:09:33.766005 02e80000 ################################################################
10243 23:09:33.766137
10244 23:09:34.010775 02f00000 ################################################################
10245 23:09:34.010911
10246 23:09:34.259184 02f80000 ################################################################
10247 23:09:34.259321
10248 23:09:34.508377 03000000 ################################################################
10249 23:09:34.508545
10250 23:09:34.752619 03080000 ################################################################
10251 23:09:34.752754
10252 23:09:35.002702 03100000 ################################################################
10253 23:09:35.002852
10254 23:09:35.254204 03180000 ################################################################
10255 23:09:35.254346
10256 23:09:35.502813 03200000 ################################################################
10257 23:09:35.502941
10258 23:09:35.752233 03280000 ################################################################
10259 23:09:35.752379
10260 23:09:35.999191 03300000 ################################################################
10261 23:09:35.999323
10262 23:09:36.250143 03380000 ################################################################
10263 23:09:36.250283
10264 23:09:36.494864 03400000 ################################################################
10265 23:09:36.494993
10266 23:09:36.739298 03480000 ################################################################
10267 23:09:36.739455
10268 23:09:36.983175 03500000 ################################################################
10269 23:09:36.983325
10270 23:09:37.231309 03580000 ################################################################
10271 23:09:37.231461
10272 23:09:37.477940 03600000 ################################################################
10273 23:09:37.478081
10274 23:09:37.732760 03680000 ################################################################
10275 23:09:37.732894
10276 23:09:37.978373 03700000 ################################################################
10277 23:09:37.978513
10278 23:09:38.221887 03780000 ################################################################
10279 23:09:38.222051
10280 23:09:38.475494 03800000 ################################################################
10281 23:09:38.475628
10282 23:09:38.723338 03880000 ################################################################
10283 23:09:38.723471
10284 23:09:38.980160 03900000 ################################################################
10285 23:09:38.980317
10286 23:09:39.231385 03980000 ################################################################
10287 23:09:39.231520
10288 23:09:39.480835 03a00000 ################################################################
10289 23:09:39.480974
10290 23:09:39.728270 03a80000 ################################################################
10291 23:09:39.728431
10292 23:09:39.977019 03b00000 ################################################################
10293 23:09:39.977194
10294 23:09:40.227448 03b80000 ################################################################
10295 23:09:40.227596
10296 23:09:40.477916 03c00000 ################################################################
10297 23:09:40.478078
10298 23:09:40.721836 03c80000 ################################################################
10299 23:09:40.721994
10300 23:09:40.967167 03d00000 ################################################################
10301 23:09:40.967331
10302 23:09:41.214721 03d80000 ################################################################
10303 23:09:41.214851
10304 23:09:41.460129 03e00000 ################################################################
10305 23:09:41.460298
10306 23:09:41.707530 03e80000 ################################################################
10307 23:09:41.707695
10308 23:09:41.959530 03f00000 ################################################################
10309 23:09:41.959696
10310 23:09:42.206040 03f80000 ################################################################
10311 23:09:42.206183
10312 23:09:42.398891 04000000 ################################################### done.
10313 23:09:42.399061
10314 23:09:42.402184 The bootfile was 67523314 bytes long.
10315 23:09:42.402291
10316 23:09:42.405560 Sending tftp read request... done.
10317 23:09:42.405664
10318 23:09:42.408579 Waiting for the transfer...
10319 23:09:42.408686
10320 23:09:42.411879 00000000 # done.
10321 23:09:42.412031
10322 23:09:42.418724 Command line loaded dynamically from TFTP file: 12154438/tftp-deploy-d_6wcibw/kernel/cmdline
10323 23:09:42.418835
10324 23:09:42.431769 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10325 23:09:42.431892
10326 23:09:42.431986 Loading FIT.
10327 23:09:42.432080
10328 23:09:42.435094 Image ramdisk-1 has 56430018 bytes.
10329 23:09:42.435192
10330 23:09:42.438336 Image fdt-1 has 47278 bytes.
10331 23:09:42.438417
10332 23:09:42.441878 Image kernel-1 has 11043984 bytes.
10333 23:09:42.441949
10334 23:09:42.451674 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10335 23:09:42.451775
10336 23:09:42.468723 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10337 23:09:42.468822
10338 23:09:42.474717 Choosing best match conf-1 for compat google,spherion-rev2.
10339 23:09:42.474806
10340 23:09:42.482485 Connected to device vid:did:rid of 1ae0:0028:00
10341 23:09:42.490673
10342 23:09:42.494457 tpm_get_response: command 0x17b, return code 0x0
10343 23:09:42.494532
10344 23:09:42.497841 ec_init: CrosEC protocol v3 supported (256, 248)
10345 23:09:42.502102
10346 23:09:42.505726 tpm_cleanup: add release locality here.
10347 23:09:42.505833
10348 23:09:42.505924 Shutting down all USB controllers.
10349 23:09:42.506022
10350 23:09:42.508643 Removing current net device
10351 23:09:42.508738
10352 23:09:42.515531 Exiting depthcharge with code 4 at timestamp: 81618580
10353 23:09:42.515629
10354 23:09:42.518659 LZMA decompressing kernel-1 to 0x821a6718
10355 23:09:42.518730
10356 23:09:42.521993 LZMA decompressing kernel-1 to 0x40000000
10357 23:09:43.915344
10358 23:09:43.915513 jumping to kernel
10359 23:09:43.916569 end: 2.2.4 bootloader-commands (duration 00:00:54) [common]
10360 23:09:43.916708 start: 2.2.5 auto-login-action (timeout 00:03:31) [common]
10361 23:09:43.916815 Setting prompt string to ['Linux version [0-9]']
10362 23:09:43.916924 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10363 23:09:43.917022 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10364 23:09:43.997222
10365 23:09:44.000224 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10366 23:09:44.004202 start: 2.2.5.1 login-action (timeout 00:03:31) [common]
10367 23:09:44.004287 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10368 23:09:44.004359 Setting prompt string to []
10369 23:09:44.004440 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10370 23:09:44.004514 Using line separator: #'\n'#
10371 23:09:44.004573 No login prompt set.
10372 23:09:44.004635 Parsing kernel messages
10373 23:09:44.004690 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10374 23:09:44.004795 [login-action] Waiting for messages, (timeout 00:03:31)
10375 23:09:44.023590 [ 0.000000] Linux version 6.1.64-cip10 (KernelCI@build-j31357-arm64-gcc-10-defconfig-arm64-chromebook-69txj) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Dec 1 22:47:09 UTC 2023
10376 23:09:44.027348 [ 0.000000] random: crng init done
10377 23:09:44.033781 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10378 23:09:44.033873 [ 0.000000] efi: UEFI not found.
10379 23:09:44.043761 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10380 23:09:44.050386 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10381 23:09:44.060433 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10382 23:09:44.070325 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10383 23:09:44.077008 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10384 23:09:44.080812 [ 0.000000] printk: bootconsole [mtk8250] enabled
10385 23:09:44.089043 [ 0.000000] NUMA: No NUMA configuration found
10386 23:09:44.095944 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10387 23:09:44.102192 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10388 23:09:44.102279 [ 0.000000] Zone ranges:
10389 23:09:44.109430 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10390 23:09:44.112583 [ 0.000000] DMA32 empty
10391 23:09:44.118824 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10392 23:09:44.122106 [ 0.000000] Movable zone start for each node
10393 23:09:44.125633 [ 0.000000] Early memory node ranges
10394 23:09:44.132240 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10395 23:09:44.138910 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10396 23:09:44.145504 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10397 23:09:44.152239 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10398 23:09:44.159065 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10399 23:09:44.165250 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10400 23:09:44.222285 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10401 23:09:44.228212 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10402 23:09:44.234925 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10403 23:09:44.238237 [ 0.000000] psci: probing for conduit method from DT.
10404 23:09:44.245396 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10405 23:09:44.248338 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10406 23:09:44.254668 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10407 23:09:44.258096 [ 0.000000] psci: SMC Calling Convention v1.2
10408 23:09:44.264611 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10409 23:09:44.268458 [ 0.000000] Detected VIPT I-cache on CPU0
10410 23:09:44.274506 [ 0.000000] CPU features: detected: GIC system register CPU interface
10411 23:09:44.281388 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10412 23:09:44.288088 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10413 23:09:44.294958 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10414 23:09:44.300971 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10415 23:09:44.311325 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10416 23:09:44.314669 [ 0.000000] alternatives: applying boot alternatives
10417 23:09:44.321238 [ 0.000000] Fallback order for Node 0: 0
10418 23:09:44.328245 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10419 23:09:44.328351 [ 0.000000] Policy zone: Normal
10420 23:09:44.344487 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10421 23:09:44.354350 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10422 23:09:44.366107 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10423 23:09:44.375897 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10424 23:09:44.383057 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10425 23:09:44.386227 <6>[ 0.000000] software IO TLB: area num 8.
10426 23:09:44.442872 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10427 23:09:44.592073 <6>[ 0.000000] Memory: 7914448K/8385536K available (17984K kernel code, 4116K rwdata, 17316K rodata, 8448K init, 615K bss, 438320K reserved, 32768K cma-reserved)
10428 23:09:44.598699 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10429 23:09:44.605562 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10430 23:09:44.608380 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10431 23:09:44.614928 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10432 23:09:44.621610 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10433 23:09:44.624775 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10434 23:09:44.635277 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10435 23:09:44.641660 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10436 23:09:44.648407 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10437 23:09:44.654833 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10438 23:09:44.657899 <6>[ 0.000000] GICv3: 608 SPIs implemented
10439 23:09:44.661414 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10440 23:09:44.668418 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10441 23:09:44.671592 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10442 23:09:44.678081 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10443 23:09:44.691087 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10444 23:09:44.701451 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10445 23:09:44.710956 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10446 23:09:44.718746 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10447 23:09:44.732017 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10448 23:09:44.738685 <6>[ 0.000001] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10449 23:09:44.745525 <6>[ 0.009235] Console: colour dummy device 80x25
10450 23:09:44.755209 <6>[ 0.013963] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10451 23:09:44.758692 <6>[ 0.024405] pid_max: default: 32768 minimum: 301
10452 23:09:44.765020 <6>[ 0.029307] LSM: Security Framework initializing
10453 23:09:44.772423 <6>[ 0.034206] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10454 23:09:44.782301 <6>[ 0.042019] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10455 23:09:44.788300 <6>[ 0.051386] cblist_init_generic: Setting adjustable number of callback queues.
10456 23:09:44.795008 <6>[ 0.058874] cblist_init_generic: Setting shift to 3 and lim to 1.
10457 23:09:44.801640 <6>[ 0.065212] cblist_init_generic: Setting adjustable number of callback queues.
10458 23:09:44.808372 <6>[ 0.072639] cblist_init_generic: Setting shift to 3 and lim to 1.
10459 23:09:44.814870 <6>[ 0.079079] rcu: Hierarchical SRCU implementation.
10460 23:09:44.821248 <6>[ 0.084125] rcu: Max phase no-delay instances is 1000.
10461 23:09:44.828251 <6>[ 0.091187] EFI services will not be available.
10462 23:09:44.831080 <6>[ 0.096145] smp: Bringing up secondary CPUs ...
10463 23:09:44.839265 <6>[ 0.101188] Detected VIPT I-cache on CPU1
10464 23:09:44.845952 <6>[ 0.101245] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10465 23:09:44.852196 <6>[ 0.101270] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10466 23:09:44.855460 <6>[ 0.101588] Detected VIPT I-cache on CPU2
10467 23:09:44.862881 <6>[ 0.101636] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10468 23:09:44.869075 <6>[ 0.101652] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10469 23:09:44.875544 <6>[ 0.101909] Detected VIPT I-cache on CPU3
10470 23:09:44.882197 <6>[ 0.101956] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10471 23:09:44.889041 <6>[ 0.101970] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10472 23:09:44.892316 <6>[ 0.102276] CPU features: detected: Spectre-v4
10473 23:09:44.899138 <6>[ 0.102282] CPU features: detected: Spectre-BHB
10474 23:09:44.902396 <6>[ 0.102287] Detected PIPT I-cache on CPU4
10475 23:09:44.908994 <6>[ 0.102343] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10476 23:09:44.915384 <6>[ 0.102360] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10477 23:09:44.922401 <6>[ 0.102651] Detected PIPT I-cache on CPU5
10478 23:09:44.929077 <6>[ 0.102713] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10479 23:09:44.935378 <6>[ 0.102730] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10480 23:09:44.938833 <6>[ 0.103010] Detected PIPT I-cache on CPU6
10481 23:09:44.945132 <6>[ 0.103074] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10482 23:09:44.952330 <6>[ 0.103090] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10483 23:09:44.958980 <6>[ 0.103387] Detected PIPT I-cache on CPU7
10484 23:09:44.965609 <6>[ 0.103452] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10485 23:09:44.971727 <6>[ 0.103468] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10486 23:09:44.974978 <6>[ 0.103515] smp: Brought up 1 node, 8 CPUs
10487 23:09:44.981744 <6>[ 0.244821] SMP: Total of 8 processors activated.
10488 23:09:44.985054 <6>[ 0.249742] CPU features: detected: 32-bit EL0 Support
10489 23:09:44.995188 <6>[ 0.255106] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10490 23:09:45.001801 <6>[ 0.263961] CPU features: detected: Common not Private translations
10491 23:09:45.005459 <6>[ 0.270437] CPU features: detected: CRC32 instructions
10492 23:09:45.011587 <6>[ 0.275822] CPU features: detected: RCpc load-acquire (LDAPR)
10493 23:09:45.018186 <6>[ 0.281782] CPU features: detected: LSE atomic instructions
10494 23:09:45.025166 <6>[ 0.287563] CPU features: detected: Privileged Access Never
10495 23:09:45.028859 <6>[ 0.293343] CPU features: detected: RAS Extension Support
10496 23:09:45.038146 <6>[ 0.298952] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10497 23:09:45.041749 <6>[ 0.306215] CPU: All CPU(s) started at EL2
10498 23:09:45.048318 <6>[ 0.310531] alternatives: applying system-wide alternatives
10499 23:09:45.056836 <6>[ 0.321184] devtmpfs: initialized
10500 23:09:45.069100 <6>[ 0.330104] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10501 23:09:45.079031 <6>[ 0.340067] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10502 23:09:45.085925 <6>[ 0.348298] pinctrl core: initialized pinctrl subsystem
10503 23:09:45.088981 <6>[ 0.354981] DMI not present or invalid.
10504 23:09:45.095988 <6>[ 0.359389] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10505 23:09:45.105881 <6>[ 0.366253] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10506 23:09:45.112639 <6>[ 0.373840] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10507 23:09:45.122634 <6>[ 0.382068] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10508 23:09:45.125463 <6>[ 0.390309] audit: initializing netlink subsys (disabled)
10509 23:09:45.135536 <5>[ 0.396000] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10510 23:09:45.142179 <6>[ 0.396708] thermal_sys: Registered thermal governor 'step_wise'
10511 23:09:45.148901 <6>[ 0.403968] thermal_sys: Registered thermal governor 'power_allocator'
10512 23:09:45.152356 <6>[ 0.410224] cpuidle: using governor menu
10513 23:09:45.159145 <6>[ 0.421180] NET: Registered PF_QIPCRTR protocol family
10514 23:09:45.165467 <6>[ 0.426652] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10515 23:09:45.168559 <6>[ 0.433755] ASID allocator initialised with 32768 entries
10516 23:09:45.176395 <6>[ 0.440328] Serial: AMBA PL011 UART driver
10517 23:09:45.185319 <4>[ 0.449124] Trying to register duplicate clock ID: 134
10518 23:09:45.239110 <6>[ 0.506758] KASLR enabled
10519 23:09:45.253345 <6>[ 0.514465] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10520 23:09:45.260136 <6>[ 0.521478] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10521 23:09:45.266677 <6>[ 0.527966] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10522 23:09:45.273386 <6>[ 0.534969] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10523 23:09:45.280288 <6>[ 0.541457] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10524 23:09:45.286519 <6>[ 0.548459] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10525 23:09:45.293088 <6>[ 0.554947] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10526 23:09:45.300067 <6>[ 0.561952] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10527 23:09:45.303294 <6>[ 0.569470] ACPI: Interpreter disabled.
10528 23:09:45.311752 <6>[ 0.575883] iommu: Default domain type: Translated
10529 23:09:45.318099 <6>[ 0.580996] iommu: DMA domain TLB invalidation policy: strict mode
10530 23:09:45.321510 <5>[ 0.587657] SCSI subsystem initialized
10531 23:09:45.328241 <6>[ 0.591818] usbcore: registered new interface driver usbfs
10532 23:09:45.334760 <6>[ 0.597551] usbcore: registered new interface driver hub
10533 23:09:45.338261 <6>[ 0.603102] usbcore: registered new device driver usb
10534 23:09:45.344866 <6>[ 0.609203] pps_core: LinuxPPS API ver. 1 registered
10535 23:09:45.354831 <6>[ 0.614398] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10536 23:09:45.358066 <6>[ 0.623745] PTP clock support registered
10537 23:09:45.361414 <6>[ 0.627985] EDAC MC: Ver: 3.0.0
10538 23:09:45.368485 <6>[ 0.633147] FPGA manager framework
10539 23:09:45.375250 <6>[ 0.636829] Advanced Linux Sound Architecture Driver Initialized.
10540 23:09:45.378794 <6>[ 0.643613] vgaarb: loaded
10541 23:09:45.385161 <6>[ 0.646768] clocksource: Switched to clocksource arch_sys_counter
10542 23:09:45.388479 <5>[ 0.653205] VFS: Disk quotas dquot_6.6.0
10543 23:09:45.395459 <6>[ 0.657392] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10544 23:09:45.398027 <6>[ 0.664580] pnp: PnP ACPI: disabled
10545 23:09:45.406899 <6>[ 0.671219] NET: Registered PF_INET protocol family
10546 23:09:45.416917 <6>[ 0.676814] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10547 23:09:45.428350 <6>[ 0.689113] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10548 23:09:45.438493 <6>[ 0.697927] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10549 23:09:45.445003 <6>[ 0.705901] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10550 23:09:45.451324 <6>[ 0.714600] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10551 23:09:45.463070 <6>[ 0.724356] TCP: Hash tables configured (established 65536 bind 65536)
10552 23:09:45.469773 <6>[ 0.731221] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10553 23:09:45.476490 <6>[ 0.738420] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10554 23:09:45.483094 <6>[ 0.746121] NET: Registered PF_UNIX/PF_LOCAL protocol family
10555 23:09:45.489720 <6>[ 0.752275] RPC: Registered named UNIX socket transport module.
10556 23:09:45.492861 <6>[ 0.758428] RPC: Registered udp transport module.
10557 23:09:45.499632 <6>[ 0.763360] RPC: Registered tcp transport module.
10558 23:09:45.506224 <6>[ 0.768292] RPC: Registered tcp NFSv4.1 backchannel transport module.
10559 23:09:45.509607 <6>[ 0.774958] PCI: CLS 0 bytes, default 64
10560 23:09:45.512844 <6>[ 0.779289] Unpacking initramfs...
10561 23:09:45.537554 <6>[ 0.798876] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10562 23:09:45.547484 <6>[ 0.807539] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10563 23:09:45.550974 <6>[ 0.816395] kvm [1]: IPA Size Limit: 40 bits
10564 23:09:45.558014 <6>[ 0.820926] kvm [1]: GICv3: no GICV resource entry
10565 23:09:45.561001 <6>[ 0.825948] kvm [1]: disabling GICv2 emulation
10566 23:09:45.567499 <6>[ 0.830633] kvm [1]: GIC system register CPU interface enabled
10567 23:09:45.571112 <6>[ 0.836790] kvm [1]: vgic interrupt IRQ18
10568 23:09:45.578110 <6>[ 0.841143] kvm [1]: VHE mode initialized successfully
10569 23:09:45.584893 <5>[ 0.847616] Initialise system trusted keyrings
10570 23:09:45.590651 <6>[ 0.852456] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10571 23:09:45.598226 <6>[ 0.862432] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10572 23:09:45.604512 <5>[ 0.868825] NFS: Registering the id_resolver key type
10573 23:09:45.607986 <5>[ 0.874128] Key type id_resolver registered
10574 23:09:45.614807 <5>[ 0.878543] Key type id_legacy registered
10575 23:09:45.621506 <6>[ 0.882822] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10576 23:09:45.627879 <6>[ 0.889744] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10577 23:09:45.634371 <6>[ 0.897452] 9p: Installing v9fs 9p2000 file system support
10578 23:09:45.670515 <5>[ 0.934564] Key type asymmetric registered
10579 23:09:45.673323 <5>[ 0.938894] Asymmetric key parser 'x509' registered
10580 23:09:45.683703 <6>[ 0.944037] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10581 23:09:45.687054 <6>[ 0.951658] io scheduler mq-deadline registered
10582 23:09:45.689905 <6>[ 0.956438] io scheduler kyber registered
10583 23:09:45.708692 <6>[ 0.973428] EINJ: ACPI disabled.
10584 23:09:45.741053 <4>[ 0.998916] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10585 23:09:45.750839 <4>[ 1.009565] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10586 23:09:45.766272 <6>[ 1.030332] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10587 23:09:45.773670 <6>[ 1.038361] printk: console [ttyS0] disabled
10588 23:09:45.801803 <6>[ 1.063005] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10589 23:09:45.808475 <6>[ 1.072499] printk: console [ttyS0] enabled
10590 23:09:45.812219 <6>[ 1.072499] printk: console [ttyS0] enabled
10591 23:09:45.818546 <6>[ 1.081394] printk: bootconsole [mtk8250] disabled
10592 23:09:45.822319 <6>[ 1.081394] printk: bootconsole [mtk8250] disabled
10593 23:09:45.828691 <6>[ 1.092655] SuperH (H)SCI(F) driver initialized
10594 23:09:45.832094 <6>[ 1.097973] msm_serial: driver initialized
10595 23:09:45.845958 <6>[ 1.106952] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10596 23:09:45.855915 <6>[ 1.115507] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10597 23:09:45.862321 <6>[ 1.124049] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10598 23:09:45.872623 <6>[ 1.132677] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10599 23:09:45.879174 <6>[ 1.141384] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10600 23:09:45.889338 <6>[ 1.150107] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10601 23:09:45.899144 <6>[ 1.158650] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10602 23:09:45.905745 <6>[ 1.167453] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10603 23:09:45.915333 <6>[ 1.175995] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10604 23:09:45.927233 <6>[ 1.191572] loop: module loaded
10605 23:09:45.933923 <6>[ 1.197562] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10606 23:09:45.956768 <4>[ 1.220967] mtk-pmic-keys: Failed to locate of_node [id: -1]
10607 23:09:45.963494 <6>[ 1.228023] megasas: 07.719.03.00-rc1
10608 23:09:45.973236 <6>[ 1.237829] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10609 23:09:45.981987 <6>[ 1.246165] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10610 23:09:45.998929 <6>[ 1.263013] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10611 23:09:46.055749 <6>[ 1.313497] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10612 23:09:47.919896 <6>[ 3.184745] Freeing initrd memory: 55104K
10613 23:09:47.930615 <6>[ 3.195165] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10614 23:09:47.941372 <6>[ 3.206159] tun: Universal TUN/TAP device driver, 1.6
10615 23:09:47.944747 <6>[ 3.212240] thunder_xcv, ver 1.0
10616 23:09:47.948319 <6>[ 3.215747] thunder_bgx, ver 1.0
10617 23:09:47.951331 <6>[ 3.219241] nicpf, ver 1.0
10618 23:09:47.962460 <6>[ 3.223267] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10619 23:09:47.965337 <6>[ 3.230743] hns3: Copyright (c) 2017 Huawei Corporation.
10620 23:09:47.971774 <6>[ 3.236330] hclge is initializing
10621 23:09:47.975140 <6>[ 3.239912] e1000: Intel(R) PRO/1000 Network Driver
10622 23:09:47.981966 <6>[ 3.245042] e1000: Copyright (c) 1999-2006 Intel Corporation.
10623 23:09:47.984998 <6>[ 3.251055] e1000e: Intel(R) PRO/1000 Network Driver
10624 23:09:47.991617 <6>[ 3.256269] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10625 23:09:47.998458 <6>[ 3.262453] igb: Intel(R) Gigabit Ethernet Network Driver
10626 23:09:48.004834 <6>[ 3.268103] igb: Copyright (c) 2007-2014 Intel Corporation.
10627 23:09:48.011606 <6>[ 3.273942] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10628 23:09:48.018537 <6>[ 3.280459] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10629 23:09:48.021473 <6>[ 3.286927] sky2: driver version 1.30
10630 23:09:48.028134 <6>[ 3.291926] VFIO - User Level meta-driver version: 0.3
10631 23:09:48.035691 <6>[ 3.300170] usbcore: registered new interface driver usb-storage
10632 23:09:48.042369 <6>[ 3.306621] usbcore: registered new device driver onboard-usb-hub
10633 23:09:48.051431 <6>[ 3.315806] mt6397-rtc mt6359-rtc: registered as rtc0
10634 23:09:48.061153 <6>[ 3.321271] mt6397-rtc mt6359-rtc: setting system clock to 2023-12-01T23:07:34 UTC (1701472054)
10635 23:09:48.064480 <6>[ 3.330849] i2c_dev: i2c /dev entries driver
10636 23:09:48.081049 <6>[ 3.342631] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10637 23:09:48.101040 <6>[ 3.365630] cpu cpu0: EM: created perf domain
10638 23:09:48.104479 <6>[ 3.370549] cpu cpu4: EM: created perf domain
10639 23:09:48.111859 <6>[ 3.376177] sdhci: Secure Digital Host Controller Interface driver
10640 23:09:48.118351 <6>[ 3.382610] sdhci: Copyright(c) Pierre Ossman
10641 23:09:48.125214 <6>[ 3.387570] Synopsys Designware Multimedia Card Interface Driver
10642 23:09:48.131620 <6>[ 3.394199] sdhci-pltfm: SDHCI platform and OF driver helper
10643 23:09:48.134674 <6>[ 3.394237] mmc0: CQHCI version 5.10
10644 23:09:48.141253 <6>[ 3.404573] ledtrig-cpu: registered to indicate activity on CPUs
10645 23:09:48.148419 <6>[ 3.411622] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10646 23:09:48.154827 <6>[ 3.418675] usbcore: registered new interface driver usbhid
10647 23:09:48.158305 <6>[ 3.424497] usbhid: USB HID core driver
10648 23:09:48.164824 <6>[ 3.428703] spi_master spi0: will run message pump with realtime priority
10649 23:09:48.209028 <6>[ 3.467007] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10650 23:09:48.227929 <6>[ 3.482730] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10651 23:09:48.231191 <6>[ 3.496276] mmc0: Command Queue Engine enabled
10652 23:09:48.238253 <6>[ 3.501069] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10653 23:09:48.244977 <6>[ 3.508383] mmcblk0: mmc0:0001 DA4128 116 GiB
10654 23:09:48.248036 <6>[ 3.513328] cros-ec-spi spi0.0: Chrome EC device registered
10655 23:09:48.254499 <6>[ 3.517012] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10656 23:09:48.262176 <6>[ 3.526838] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10657 23:09:48.268906 <6>[ 3.532970] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10658 23:09:48.275466 <6>[ 3.538927] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10659 23:09:48.293758 <6>[ 3.554920] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10660 23:09:48.301304 <6>[ 3.565576] NET: Registered PF_PACKET protocol family
10661 23:09:48.304344 <6>[ 3.570987] 9pnet: Installing 9P2000 support
10662 23:09:48.311048 <5>[ 3.575555] Key type dns_resolver registered
10663 23:09:48.314487 <6>[ 3.580547] registered taskstats version 1
10664 23:09:48.320712 <5>[ 3.584937] Loading compiled-in X.509 certificates
10665 23:09:48.349759 <4>[ 3.607914] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10666 23:09:48.359636 <4>[ 3.618603] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10667 23:09:48.366419 <3>[ 3.629183] debugfs: File 'uA_load' in directory '/' already present!
10668 23:09:48.373038 <3>[ 3.635890] debugfs: File 'min_uV' in directory '/' already present!
10669 23:09:48.380077 <3>[ 3.642498] debugfs: File 'max_uV' in directory '/' already present!
10670 23:09:48.386144 <3>[ 3.649105] debugfs: File 'constraint_flags' in directory '/' already present!
10671 23:09:48.397037 <3>[ 3.658633] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10672 23:09:48.406710 <6>[ 3.671607] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10673 23:09:48.413503 <6>[ 3.678379] xhci-mtk 11200000.usb: xHCI Host Controller
10674 23:09:48.420770 <6>[ 3.683898] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10675 23:09:48.430295 <6>[ 3.691743] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10676 23:09:48.436821 <6>[ 3.701166] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10677 23:09:48.443772 <6>[ 3.707229] xhci-mtk 11200000.usb: xHCI Host Controller
10678 23:09:48.450491 <6>[ 3.712707] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10679 23:09:48.456703 <6>[ 3.720352] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10680 23:09:48.463560 <6>[ 3.728187] hub 1-0:1.0: USB hub found
10681 23:09:48.466795 <6>[ 3.732229] hub 1-0:1.0: 1 port detected
10682 23:09:48.476847 <6>[ 3.736504] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10683 23:09:48.479998 <6>[ 3.745245] hub 2-0:1.0: USB hub found
10684 23:09:48.483263 <6>[ 3.749263] hub 2-0:1.0: 1 port detected
10685 23:09:48.492444 <6>[ 3.756958] mtk-msdc 11f70000.mmc: Got CD GPIO
10686 23:09:48.503021 <6>[ 3.764643] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10687 23:09:48.510329 <6>[ 3.772670] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10688 23:09:48.519671 <4>[ 3.780584] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10689 23:09:48.529915 <6>[ 3.790109] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10690 23:09:48.536416 <6>[ 3.798185] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10691 23:09:48.543340 <6>[ 3.806204] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10692 23:09:48.553148 <6>[ 3.814129] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10693 23:09:48.560005 <6>[ 3.821947] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10694 23:09:48.570104 <6>[ 3.829764] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10695 23:09:48.579639 <6>[ 3.840195] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10696 23:09:48.586240 <6>[ 3.848554] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10697 23:09:48.596147 <6>[ 3.856908] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10698 23:09:48.603078 <6>[ 3.865248] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10699 23:09:48.612737 <6>[ 3.873587] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10700 23:09:48.619466 <6>[ 3.881926] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10701 23:09:48.629541 <6>[ 3.890265] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10702 23:09:48.636484 <6>[ 3.898604] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10703 23:09:48.645944 <6>[ 3.906943] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10704 23:09:48.652908 <6>[ 3.915281] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10705 23:09:48.662423 <6>[ 3.923620] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10706 23:09:48.669137 <6>[ 3.931971] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10707 23:09:48.678731 <6>[ 3.940310] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10708 23:09:48.688971 <6>[ 3.948648] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10709 23:09:48.695522 <6>[ 3.956986] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10710 23:09:48.702102 <6>[ 3.965707] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10711 23:09:48.708903 <6>[ 3.972589] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10712 23:09:48.715381 <6>[ 3.979347] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10713 23:09:48.722255 <6>[ 3.986108] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10714 23:09:48.728818 <6>[ 3.993062] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10715 23:09:48.738896 <6>[ 3.999916] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10716 23:09:48.749072 <6>[ 4.009043] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10717 23:09:48.758899 <6>[ 4.018163] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10718 23:09:48.769212 <6>[ 4.027456] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10719 23:09:48.775638 <6>[ 4.036928] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10720 23:09:48.785425 <6>[ 4.046396] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10721 23:09:48.794927 <6>[ 4.055516] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10722 23:09:48.805185 <6>[ 4.064985] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10723 23:09:48.815565 <6>[ 4.074102] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10724 23:09:48.825102 <6>[ 4.083396] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10725 23:09:48.834857 <6>[ 4.093556] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10726 23:09:48.844848 <6>[ 4.105043] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10727 23:09:48.893789 <6>[ 4.155034] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10728 23:09:49.048131 <6>[ 4.313064] hub 1-1:1.0: USB hub found
10729 23:09:49.051677 <6>[ 4.317589] hub 1-1:1.0: 4 ports detected
10730 23:09:49.061136 <6>[ 4.325971] hub 1-1:1.0: USB hub found
10731 23:09:49.064436 <6>[ 4.330282] hub 1-1:1.0: 4 ports detected
10732 23:09:49.173908 <6>[ 4.435396] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10733 23:09:49.199838 <6>[ 4.464768] hub 2-1:1.0: USB hub found
10734 23:09:49.203111 <6>[ 4.469251] hub 2-1:1.0: 3 ports detected
10735 23:09:49.212915 <6>[ 4.477428] hub 2-1:1.0: USB hub found
10736 23:09:49.216054 <6>[ 4.481899] hub 2-1:1.0: 3 ports detected
10737 23:09:49.389783 <6>[ 4.651078] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10738 23:09:49.522233 <6>[ 4.786903] hub 1-1.4:1.0: USB hub found
10739 23:09:49.525480 <6>[ 4.791572] hub 1-1.4:1.0: 2 ports detected
10740 23:09:49.535127 <6>[ 4.799950] hub 1-1.4:1.0: USB hub found
10741 23:09:49.539007 <6>[ 4.804556] hub 1-1.4:1.0: 2 ports detected
10742 23:09:49.601755 <6>[ 4.863201] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10743 23:09:49.837507 <6>[ 5.099081] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10744 23:09:50.029353 <6>[ 5.291065] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10745 23:10:01.131044 <6>[ 16.400067] ALSA device list:
10746 23:10:01.137209 <6>[ 16.403350] No soundcards found.
10747 23:10:01.145386 <6>[ 16.411362] Freeing unused kernel memory: 8448K
10748 23:10:01.148802 <6>[ 16.416391] Run /init as init process
10749 23:10:01.197734 <6>[ 16.463934] NET: Registered PF_INET6 protocol family
10750 23:10:01.205023 <6>[ 16.470251] Segment Routing with IPv6
10751 23:10:01.208010 <6>[ 16.474224] In-situ OAM (IOAM) with IPv6
10752 23:10:01.242266 <30>[ 16.488617] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10753 23:10:01.245310 <30>[ 16.512588] systemd[1]: Detected architecture arm64.
10754 23:10:01.248828
10755 23:10:01.252553 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10756 23:10:01.252654
10757 23:10:01.265262 <30>[ 16.531114] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10758 23:10:01.443150 <30>[ 16.706220] systemd[1]: Queued start job for default target Graphical Interface.
10759 23:10:01.481554 <30>[ 16.747855] systemd[1]: Created slice system-getty.slice.
10760 23:10:01.488180 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10761 23:10:01.505326 <30>[ 16.771623] systemd[1]: Created slice system-modprobe.slice.
10762 23:10:01.512341 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10763 23:10:01.530450 <30>[ 16.796396] systemd[1]: Created slice system-serial\x2dgetty.slice.
10764 23:10:01.540575 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10765 23:10:01.553440 <30>[ 16.819332] systemd[1]: Created slice User and Session Slice.
10766 23:10:01.559951 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10767 23:10:01.580613 <30>[ 16.843597] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10768 23:10:01.590722 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10769 23:10:01.608716 <30>[ 16.871542] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10770 23:10:01.615965 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10771 23:10:01.635963 <30>[ 16.895108] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10772 23:10:01.642469 <30>[ 16.907275] systemd[1]: Reached target Local Encrypted Volumes.
10773 23:10:01.648747 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10774 23:10:01.665258 <30>[ 16.931484] systemd[1]: Reached target Paths.
10775 23:10:01.669072 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10776 23:10:01.684641 <30>[ 16.951056] systemd[1]: Reached target Remote File Systems.
10777 23:10:01.691866 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10778 23:10:01.709065 <30>[ 16.975435] systemd[1]: Reached target Slices.
10779 23:10:01.715662 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10780 23:10:01.728746 <30>[ 16.995071] systemd[1]: Reached target Swap.
10781 23:10:01.732044 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10782 23:10:01.752714 <30>[ 17.015516] systemd[1]: Listening on initctl Compatibility Named Pipe.
10783 23:10:01.759048 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10784 23:10:01.765619 <30>[ 17.030659] systemd[1]: Listening on Journal Audit Socket.
10785 23:10:01.772517 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10786 23:10:01.785403 <30>[ 17.051520] systemd[1]: Listening on Journal Socket (/dev/log).
10787 23:10:01.792023 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10788 23:10:01.810341 <30>[ 17.076276] systemd[1]: Listening on Journal Socket.
10789 23:10:01.816626 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10790 23:10:01.829406 <30>[ 17.095628] systemd[1]: Listening on udev Control Socket.
10791 23:10:01.836252 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10792 23:10:01.854274 <30>[ 17.120083] systemd[1]: Listening on udev Kernel Socket.
10793 23:10:01.860542 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10794 23:10:01.913255 <30>[ 17.179333] systemd[1]: Mounting Huge Pages File System...
10795 23:10:01.919710 Mounting [0;1;39mHuge Pages File System[0m...
10796 23:10:01.936998 <30>[ 17.203173] systemd[1]: Mounting POSIX Message Queue File System...
10797 23:10:01.943713 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10798 23:10:01.977006 <30>[ 17.243081] systemd[1]: Mounting Kernel Debug File System...
10799 23:10:01.983505 Mounting [0;1;39mKernel Debug File System[0m...
10800 23:10:02.000555 <30>[ 17.263465] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10801 23:10:02.014171 <30>[ 17.276475] systemd[1]: Starting Create list of static device nodes for the current kernel...
10802 23:10:02.020305 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10803 23:10:02.041382 <30>[ 17.307529] systemd[1]: Starting Load Kernel Module configfs...
10804 23:10:02.047893 Starting [0;1;39mLoad Kernel Module configfs[0m...
10805 23:10:02.064861 <30>[ 17.330964] systemd[1]: Starting Load Kernel Module drm...
10806 23:10:02.071138 Starting [0;1;39mLoad Kernel Module drm[0m...
10807 23:10:02.088081 <30>[ 17.351118] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10808 23:10:02.121245 <30>[ 17.387533] systemd[1]: Starting Journal Service...
10809 23:10:02.124642 Starting [0;1;39mJournal Service[0m...
10810 23:10:02.143575 <30>[ 17.409892] systemd[1]: Starting Load Kernel Modules...
10811 23:10:02.150622 Starting [0;1;39mLoad Kernel Modules[0m...
10812 23:10:02.170835 <30>[ 17.433854] systemd[1]: Starting Remount Root and Kernel File Systems...
10813 23:10:02.177765 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10814 23:10:02.196308 <30>[ 17.462267] systemd[1]: Starting Coldplug All udev Devices...
10815 23:10:02.202436 Starting [0;1;39mColdplug All udev Devices[0m...
10816 23:10:02.221651 <30>[ 17.487876] systemd[1]: Started Journal Service.
10817 23:10:02.228169 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10818 23:10:02.242970 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10819 23:10:02.261862 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10820 23:10:02.278028 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10821 23:10:02.297476 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10822 23:10:02.318782 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10823 23:10:02.334951 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10824 23:10:02.359037 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10825 23:10:02.379161 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10826 23:10:02.393067 See 'systemctl status systemd-remount-fs.service' for details.
10827 23:10:02.437979 Mounting [0;1;39mKernel Configuration File System[0m...
10828 23:10:02.459898 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10829 23:10:02.473562 <46>[ 17.736576] systemd-journald[183]: Received client request to flush runtime journal.
10830 23:10:02.485201 Starting [0;1;39mLoad/Save Random Seed[0m...
10831 23:10:02.505879 Starting [0;1;39mApply Kernel Variables[0m...
10832 23:10:02.529913 Starting [0;1;39mCreate System Users[0m...
10833 23:10:02.554516 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10834 23:10:02.573907 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10835 23:10:02.596805 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10836 23:10:02.610342 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10837 23:10:02.626629 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10838 23:10:02.642288 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10839 23:10:02.681186 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10840 23:10:02.703720 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10841 23:10:02.717269 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10842 23:10:02.733237 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10843 23:10:02.781835 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10844 23:10:02.805494 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10845 23:10:02.827327 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10846 23:10:02.847386 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10847 23:10:02.907005 Starting [0;1;39mNetwork Time Synchronization[0m...
10848 23:10:02.938075 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10849 23:10:02.984082 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m<6>[ 18.246662] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10850 23:10:02.984184 .
10851 23:10:03.010096 <3>[ 18.272951] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10852 23:10:03.019697 <3>[ 18.282299] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10853 23:10:03.026806 <3>[ 18.290724] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10854 23:10:03.033128 <6>[ 18.293325] remoteproc remoteproc0: scp is available
10855 23:10:03.039871 <3>[ 18.304538] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10856 23:10:03.046681 <6>[ 18.304840] remoteproc remoteproc0: powering up scp
10857 23:10:03.053413 <6>[ 18.306273] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10858 23:10:03.062870 <6>[ 18.307343] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10859 23:10:03.073170 <6>[ 18.307357] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10860 23:10:03.079878 <3>[ 18.313033] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10861 23:10:03.089458 <6>[ 18.318970] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10862 23:10:03.096610 <4>[ 18.319843] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10863 23:10:03.102784 <4>[ 18.320104] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10864 23:10:03.109513 <3>[ 18.325498] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10865 23:10:03.116413 <6>[ 18.334288] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10866 23:10:03.126309 <3>[ 18.343045] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10867 23:10:03.129133 <6>[ 18.378737] mc: Linux media interface: v0.10
10868 23:10:03.135766 <3>[ 18.382120] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10869 23:10:03.145732 <3>[ 18.384825] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10870 23:10:03.153109 <6>[ 18.391671] usbcore: registered new interface driver r8152
10871 23:10:03.158757 <3>[ 18.398158] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10872 23:10:03.165222 <6>[ 18.398194] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10873 23:10:03.176018 <4>[ 18.421148] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10874 23:10:03.182571 <4>[ 18.421148] Fallback method does not support PEC.
10875 23:10:03.188832 <3>[ 18.422403] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10876 23:10:03.196010 <6>[ 18.434319] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10877 23:10:03.202783 <3>[ 18.438117] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10878 23:10:03.213035 <6>[ 18.440312] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10879 23:10:03.219932 <6>[ 18.452658] pci_bus 0000:00: root bus resource [bus 00-ff]
10880 23:10:03.226639 <3>[ 18.460531] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10881 23:10:03.236159 <3>[ 18.460571] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10882 23:10:03.243434 <3>[ 18.460579] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10883 23:10:03.250365 <3>[ 18.460595] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10884 23:10:03.260517 <6>[ 18.467543] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10885 23:10:03.270703 <6>[ 18.467622] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10886 23:10:03.280528 <6>[ 18.467631] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10887 23:10:03.283626 <6>[ 18.467678] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10888 23:10:03.293780 <6>[ 18.467699] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10889 23:10:03.296989 <6>[ 18.467787] pci 0000:00:00.0: supports D1 D2
10890 23:10:03.303495 <6>[ 18.467791] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10891 23:10:03.313887 <6>[ 18.474538] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10892 23:10:03.319996 <6>[ 18.474663] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10893 23:10:03.327093 <6>[ 18.474689] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10894 23:10:03.334536 <6>[ 18.474707] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10895 23:10:03.341122 <6>[ 18.474722] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10896 23:10:03.344116 <6>[ 18.474861] pci 0000:01:00.0: supports D1 D2
10897 23:10:03.354232 <6>[ 18.474863] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10898 23:10:03.361269 <3>[ 18.475680] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10899 23:10:03.367475 <6>[ 18.476481] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10900 23:10:03.377955 <3>[ 18.476497] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10901 23:10:03.387219 <6>[ 18.486445] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10902 23:10:03.394087 <6>[ 18.487202] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10903 23:10:03.400503 <6>[ 18.487242] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10904 23:10:03.410732 <6>[ 18.487247] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10905 23:10:03.418197 <6>[ 18.487256] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10906 23:10:03.424901 <6>[ 18.487269] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10907 23:10:03.432374 <6>[ 18.487282] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10908 23:10:03.438543 <6>[ 18.487294] pci 0000:00:00.0: PCI bridge to [bus 01]
10909 23:10:03.445207 <6>[ 18.487299] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10910 23:10:03.451805 <6>[ 18.489236] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10911 23:10:03.461981 <6>[ 18.490667] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10912 23:10:03.469276 <3>[ 18.492472] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10913 23:10:03.478797 <3>[ 18.520533] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10914 23:10:03.484925 <3>[ 18.521344] power_supply sbs-5-000b: driver failed to report `temp' property: -6
10915 23:10:03.491792 <6>[ 18.523322] remoteproc remoteproc0: remote processor scp is now up
10916 23:10:03.498479 <6>[ 18.525425] videodev: Linux video capture interface: v2.00
10917 23:10:03.504985 <6>[ 18.538708] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10918 23:10:03.511926 <6>[ 18.575929] usbcore: registered new interface driver cdc_ether
10919 23:10:03.514758 <6>[ 18.584565] Bluetooth: Core ver 2.22
10920 23:10:03.524919 <3>[ 18.605052] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10921 23:10:03.528362 <6>[ 18.605793] NET: Registered PF_BLUETOOTH protocol family
10922 23:10:03.538300 <4>[ 18.612838] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10923 23:10:03.545239 <6>[ 18.613449] usbcore: registered new interface driver r8153_ecm
10924 23:10:03.551717 <6>[ 18.617308] Bluetooth: HCI device and connection manager initialized
10925 23:10:03.558341 <6>[ 18.618604] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10926 23:10:03.561790 <6>[ 18.620448] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10927 23:10:03.572324 <6>[ 18.620488] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10928 23:10:03.581727 <6>[ 18.621932] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10929 23:10:03.588343 <6>[ 18.622735] usbcore: registered new interface driver uvcvideo
10930 23:10:03.595352 <4>[ 18.624906] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10931 23:10:03.601851 <6>[ 18.632135] Bluetooth: HCI socket layer initialized
10932 23:10:03.608480 <6>[ 18.632143] Bluetooth: L2CAP socket layer initialized
10933 23:10:03.611851 <6>[ 18.632170] Bluetooth: SCO socket layer initialized
10934 23:10:03.621775 <6>[ 18.632225] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10935 23:10:03.628271 <5>[ 18.634862] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10936 23:10:03.635115 <6>[ 18.635699] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10937 23:10:03.641726 <6>[ 18.640258] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10938 23:10:03.651573 <5>[ 18.652946] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10939 23:10:03.654983 <6>[ 18.694906] r8152 2-1.3:1.0 eth0: v1.12.13
10940 23:10:03.664847 <4>[ 18.696472] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10941 23:10:03.671670 <3>[ 18.704682] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10942 23:10:03.677986 <6>[ 18.705142] usbcore: registered new interface driver btusb
10943 23:10:03.688333 <3>[ 18.705320] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10944 23:10:03.697833 <4>[ 18.705839] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10945 23:10:03.704453 <3>[ 18.705853] Bluetooth: hci0: Failed to load firmware file (-2)
10946 23:10:03.707502 <3>[ 18.705857] Bluetooth: hci0: Failed to set up firmware (-2)
10947 23:10:03.720650 <4>[ 18.705861] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10948 23:10:03.727919 <3>[ 18.708578] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10949 23:10:03.734044 <6>[ 18.709765] cfg80211: failed to load regulatory.db
10950 23:10:03.740486 <6>[ 18.717904] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
10951 23:10:03.747148 <3>[ 18.899818] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10952 23:10:03.757219 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10953 23:10:03.783917 [[0;32m OK [0m] Started [0;<3>[ 19.045043] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10954 23:10:03.787042 1;39mNetwork Time Synchronization[0m.
10955 23:10:03.796969 <6>[ 19.059956] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10956 23:10:03.800901 <6>[ 19.067468] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10957 23:10:03.811452 [[0;32m OK [<3>[ 19.075222] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10958 23:10:03.818142 0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10959 23:10:03.828031 <6>[ 19.094141] mt7921e 0000:01:00.0: ASIC revision: 79610010
10960 23:10:03.836640 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10961 23:10:03.901752 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10962 23:10:03.935804 <4>[ 19.195130] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10963 23:10:04.024808 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10964 23:10:04.056096 [[0;32m OK [0m] Reached target [0;1;39mSystem Initializatio<4>[ 19.313471] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10965 23:10:04.056664 n[0m.
10966 23:10:04.073716 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10967 23:10:04.089730 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10968 23:10:04.105070 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10969 23:10:04.125296 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10970 23:10:04.141209 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10971 23:10:04.161906 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10972 23:10:04.171975 <4>[ 19.433247] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10973 23:10:04.178809 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10974 23:10:04.193403 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10975 23:10:04.213691 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10976 23:10:04.262618 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10977 23:10:04.294862 <4>[ 19.553955] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10978 23:10:04.311900 Starting [0;1;39mUser Login Management[0m...
10979 23:10:04.330179 Starting [0;1;39mPermit User Sessions[0m...
10980 23:10:04.351695 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10981 23:10:04.370950 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10982 23:10:04.385733 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10983 23:10:04.415525 [[0;32m OK [0m] Started [0;<4>[ 19.673340] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10984 23:10:04.418806 1;39mUser Login Management[0m.
10985 23:10:04.471227 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10986 23:10:04.488375 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10987 23:10:04.505549 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10988 23:10:04.533568 [[0;32m OK [0m] Reached target [0;1;39mMult<4>[ 19.793429] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10989 23:10:04.537203 i-User System[0m.
10990 23:10:04.550530 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10991 23:10:04.593792 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10992 23:10:04.633072 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10993 23:10:04.654212 <4>[ 19.913709] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10994 23:10:04.705090
10995 23:10:04.705833
10996 23:10:04.708873 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10997 23:10:04.709363
10998 23:10:04.711818 debian-bullseye-arm64 login: root (automatic login)
10999 23:10:04.712454
11000 23:10:04.712806
11001 23:10:04.727696 Linux debian-bullseye-arm64 6.1.64-cip10 #1 SMP PREEMPT Fri Dec 1 22:47:09 UTC 2023 aarch64
11002 23:10:04.728137
11003 23:10:04.733875 The programs included with the Debian GNU/Linux system are free software;
11004 23:10:04.740586 the exact distribution terms for each program are described in the
11005 23:10:04.743955 individual files in /usr/share/doc/*/copyright.
11006 23:10:04.744409
11007 23:10:04.750834 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11008 23:10:04.754159 permitted by applicable law.
11009 23:10:04.755456 Matched prompt #10: / #
11011 23:10:04.756438 Setting prompt string to ['/ #']
11012 23:10:04.756858 end: 2.2.5.1 login-action (duration 00:00:21) [common]
11014 23:10:04.757866 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
11015 23:10:04.758295 start: 2.2.6 expect-shell-connection (timeout 00:03:11) [common]
11016 23:10:04.758641 Setting prompt string to ['/ #']
11017 23:10:04.758951 Forcing a shell prompt, looking for ['/ #']
11019 23:10:04.809723 / #
11020 23:10:04.810384 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11021 23:10:04.810990 Waiting using forced prompt support (timeout 00:02:30)
11022 23:10:04.811721 <4>[ 20.033577] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11023 23:10:04.815755
11024 23:10:04.816593 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11025 23:10:04.817112 start: 2.2.7 export-device-env (timeout 00:03:11) [common]
11026 23:10:04.817559 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11027 23:10:04.818037 end: 2.2 depthcharge-retry (duration 00:01:49) [common]
11028 23:10:04.818472 end: 2 depthcharge-action (duration 00:01:49) [common]
11029 23:10:04.818902 start: 3 lava-test-retry (timeout 00:07:48) [common]
11030 23:10:04.819337 start: 3.1 lava-test-shell (timeout 00:07:48) [common]
11031 23:10:04.819694 Using namespace: common
11033 23:10:04.920561 / # #
11034 23:10:04.920799 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11035 23:10:04.921025 #<4>[ 20.157621] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11036 23:10:04.926028
11037 23:10:04.926439 Using /lava-12154438
11039 23:10:05.027013 / # export SHELL=/bin/sh
11040 23:10:05.027283 export SHELL=/bin/sh<4>[ 20.276945] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11041 23:10:05.032851
11043 23:10:05.133655 / # . /lava-12154438/environment
11044 23:10:05.134358 . /lava-12154438/environment<3>[ 20.395357] mt7921e 0000:01:00.0: hardware init failed
11045 23:10:05.139435
11047 23:10:05.240923 / # /lava-12154438/bin/lava-test-runner /lava-12154438/0
11048 23:10:05.241171 Test shell timeout: 10s (minimum of the action and connection timeout)
11049 23:10:05.246413 /lava-12154438/bin/lava-test-runner /lava-12154438/0
11050 23:10:05.274784 + export TESTRUN_ID=0_igt-gpu-pa<8>[ 20.540459] <LAVA_SIGNAL_STARTRUN 0_igt-gpu-panfrost 12154438_1.5.2.3.1>
11051 23:10:05.275202 Received signal: <STARTRUN> 0_igt-gpu-panfrost 12154438_1.5.2.3.1
11052 23:10:05.275347 Starting test lava.0_igt-gpu-panfrost (12154438_1.5.2.3.1)
11053 23:10:05.275496 Skipping test definition patterns.
11054 23:10:05.278399 nfrost
11055 23:10:05.281630 + cd /lava-12154438/0/tests/0_igt-gpu-panfrost
11056 23:10:05.281786 + cat uuid
11057 23:10:05.285241 + UUID=12154438_1.5.2.3.1
11058 23:10:05.285415 + set +x
11059 23:10:05.301409 + IGT_FORCE_DRIVER=panfrost /usr/bin/igt-parser.sh panfrost_gem_new panfrost_get_param panfrost_prime p<8>[ 20.564509] <LAVA_SIGNAL_TESTSET START panfrost_gem_new>
11060 23:10:05.301559 anfrost_submit
11061 23:10:05.301915 Received signal: <TESTSET> START panfrost_gem_new
11062 23:10:05.302048 Starting test_set panfrost_gem_new
11063 23:10:05.318353 <14>[ 20.584753] [IGT] panfrost_gem_new: executing
11064 23:10:05.325299 IGT-Version: 1.27.1-g621c2d3 (aa<14>[ 20.591531] [IGT] panfrost_gem_new: exiting, ret=77
11065 23:10:05.328553 rch64) (Linux: 6.1.64-cip10 aarch64)
11066 23:10:05.341550 Test requirement not met in function drm_open_driver, file<8>[ 20.604699] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-4096 RESULT=skip>
11067 23:10:05.341904 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-4096 RESULT=skip
11069 23:10:05.344812 ../lib/drmtest.c:621:
11070 23:10:05.344965 Test requirement: !(fd<0)
11071 23:10:05.351562 No known gpu found for chipset flags 0x32 (panfrost)
11072 23:10:05.355451 Last errno: 2, No such file or directory
11073 23:10:05.357877 [1mSubtest gem-new-4096: SKIP (0.000s)[0m
11074 23:10:05.366021 <14>[ 20.632480] [IGT] panfrost_gem_new: executing
11075 23:10:05.372598 IGT-Version: 1.27.1-g621c2d3 (aa<14>[ 20.640162] [IGT] panfrost_gem_new: exiting, ret=77
11076 23:10:05.376531 rch64) (Linux: 6.1.64-cip10 aarch64)
11077 23:10:05.386102 Test requirement not met i<8>[ 20.650800] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-0 RESULT=skip>
11078 23:10:05.386439 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-0 RESULT=skip
11080 23:10:05.392798 n function drm_open_driver, file ../lib/drmtest.c:621:
11081 23:10:05.392947 Test requirement: !(fd<0)
11082 23:10:05.399423 No known gpu found for chipset flags 0x32 (panfrost)
11083 23:10:05.405712 Last errno: 2, No such <14>[ 20.670326] [IGT] panfrost_gem_new: executing
11084 23:10:05.405858 file or directory
11085 23:10:05.412437 [1mSubtest g<14>[ 20.678183] [IGT] panfrost_gem_new: exiting, ret=77
11086 23:10:05.415976 em-new-0: SKIP (0.000s)[0m
11087 23:10:05.425868 IGT-Version: 1.27.1-g621c2d3 (aarch<8>[ 20.689109] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-zeroed RESULT=skip>
11088 23:10:05.426258 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-zeroed RESULT=skip
11090 23:10:05.432532 64) (Linux: 6.1.64-cip10 aarch64<8>[ 20.699585] <LAVA_SIGNAL_TESTSET STOP>
11091 23:10:05.432684 )
11092 23:10:05.432987 Received signal: <TESTSET> STOP
11093 23:10:05.433113 Closing test_set panfrost_gem_new
11094 23:10:05.438862 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
11095 23:10:05.442390 Test requirement: !(fd<0)
11096 23:10:05.445715 No known gpu found for chipset flags 0x32 (panfrost)
11097 23:10:05.455775 Last errno: 2, No such fil<8>[ 20.720566] <LAVA_SIGNAL_TESTSET START panfrost_get_param>
11098 23:10:05.455941 e or directory
11099 23:10:05.456273 Received signal: <TESTSET> START panfrost_get_param
11100 23:10:05.456409 Starting test_set panfrost_get_param
11101 23:10:05.462105 [1mSubtest gem-new-zeroed: SKIP (0.000s)[0m
11102 23:10:05.475121 <14>[ 20.741360] [IGT] panfrost_get_param: executing
11103 23:10:05.481774 IGT-Version: 1.27.1-g621c2d3 (aa<14>[ 20.748439] [IGT] panfrost_get_param: exiting, ret=77
11104 23:10:05.485381 rch64) (Linux: 6.1.64-cip10 aarch64)
11105 23:10:05.494412 Test requirement not met i<8>[ 20.760051] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=base-params RESULT=skip>
11106 23:10:05.494669 Received signal: <TESTCASE> TEST_CASE_ID=base-params RESULT=skip
11108 23:10:05.501505 n function drm_open_driver, file ../lib/drmtest.c:621:
11109 23:10:05.501627 Test requirement: !(fd<0)
11110 23:10:05.507769 No known gpu found for chipset flags 0x32 (panfrost)
11111 23:10:05.514281 Last er<14>[ 20.778657] [IGT] panfrost_get_param: executing
11112 23:10:05.521189 rno: 2, No such file or director<14>[ 20.786444] [IGT] panfrost_get_param: exiting, ret=77
11113 23:10:05.521279 y
11114 23:10:05.524627 [1mSubtest base-params: SKIP (0.000s)[0m
11115 23:10:05.534346 IGT-Version: 1.27<8>[ 20.798008] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-param RESULT=skip>
11116 23:10:05.534602 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-param RESULT=skip
11118 23:10:05.537622 .1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10 aarch64)
11119 23:10:05.544288 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
11120 23:10:05.550862 Test requ<14>[ 20.817403] [IGT] panfrost_get_param: executing
11121 23:10:05.554289 irement: !(fd<0)
11122 23:10:05.561285 No known gpu f<14>[ 20.824758] [IGT] panfrost_get_param: exiting, ret=77
11123 23:10:05.564151 ound for chipset flags 0x32 (panfrost)
11124 23:10:05.574226 Last errno: 2, No such file or directory<8>[ 20.837249] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-padding RESULT=skip>
11125 23:10:05.574364
11126 23:10:05.574655 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-padding RESULT=skip
11128 23:10:05.581027 [1mSubtest get-bad-param: SKI<8>[ 20.846734] <LAVA_SIGNAL_TESTSET STOP>
11129 23:10:05.581178 P (0.000s)[0m
11130 23:10:05.581482 Received signal: <TESTSET> STOP
11131 23:10:05.581617 Closing test_set panfrost_get_param
11132 23:10:05.587726 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10 aarch64)
11133 23:10:05.594017 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
11134 23:10:05.597712 Test requirement: !(fd<0)
11135 23:10:05.601318 No known gpu found for chipset flags 0x32 (panfrost)
11136 23:10:05.610575 Last errno: 2, No such file or director<8>[ 20.876903] <LAVA_SIGNAL_TESTSET START panfrost_prime>
11137 23:10:05.610752 y
11138 23:10:05.611084 Received signal: <TESTSET> START panfrost_prime
11139 23:10:05.611227 Starting test_set panfrost_prime
11140 23:10:05.613754 [1mSubtest get-bad-padding: SKIP (0.000s)[0m
11141 23:10:05.637279 <14>[ 20.903336] [IGT] panfrost_prime: executing
11142 23:10:05.643705 IGT-Version: 1.27.1-g621c2d3 (aa<14>[ 20.910881] [IGT] panfrost_prime: exiting, ret=77
11143 23:10:05.647176 rch64) (Linux: 6.1.64-cip10 aarch64)
11144 23:10:05.660443 Test requirement not met in function drm_open_driver, file<8>[ 20.923002] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-prime-import RESULT=skip>
11145 23:10:05.661137 Received signal: <TESTCASE> TEST_CASE_ID=gem-prime-import RESULT=skip
11147 23:10:05.663446 ../lib/drmtest.c:621:
11148 23:10:05.666977 Test req<8>[ 20.933237] <LAVA_SIGNAL_TESTSET STOP>
11149 23:10:05.667809 Received signal: <TESTSET> STOP
11150 23:10:05.668227 Closing test_set panfrost_prime
11151 23:10:05.670574 uirement: !(fd<0)
11152 23:10:05.674015 No known gpu found for chipset flags 0x32 (panfrost)
11153 23:10:05.676944 Last errno: 2, No such file or directory
11154 23:10:05.680265 [1mSubtest gem-prime-import: SKIP (0.000s)[0m
11155 23:10:05.697164 <8>[ 20.963385] <LAVA_SIGNAL_TESTSET START panfrost_submit>
11156 23:10:05.697883 Received signal: <TESTSET> START panfrost_submit
11157 23:10:05.698255 Starting test_set panfrost_submit
11158 23:10:05.723738 <14>[ 20.989850] [IGT] panfrost_submit: executing
11159 23:10:05.734123 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6<14>[ 20.997676] [IGT] panfrost_submit: exiting, ret=77
11160 23:10:05.734547 .1.64-cip10 aarch64)
11161 23:10:05.746950 Test requirement not met in function drm_open_driver, file ../lib/drmtest.<8>[ 21.011491] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit RESULT=skip>
11162 23:10:05.747643 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit RESULT=skip
11164 23:10:05.750478 c:621:
11165 23:10:05.751037 Test requirement: !(fd<0)
11166 23:10:05.756976 No known gpu found for chipset flags 0x32 (panfrost)
11167 23:10:05.760170 Last errno: 2, No such file or directory
11168 23:10:05.766818 [1mSubtest pan-submit: SKIP <14>[ 21.033047] [IGT] panfrost_submit: executing
11169 23:10:05.767380 (0.000s)[0m
11170 23:10:05.773649 IGT-Version: 1.2<14>[ 21.039954] [IGT] panfrost_submit: exiting, ret=77
11171 23:10:05.779997 7.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10 aarch64)
11172 23:10:05.786648 Test requi<8>[ 21.051012] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip>
11173 23:10:05.787341 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip
11175 23:10:05.793219 rement not met in function drm_open_driver, file ../lib/drmtest.c:621:
11176 23:10:05.796856 Test requirement: !(fd<0)
11177 23:10:05.806260 No known gpu found for chipset flags 0x32 (pa<14>[ 21.071175] [IGT] panfrost_submit: executing
11178 23:10:05.806698 nfrost)
11179 23:10:05.812911 Last errno: 2, No such <14>[ 21.078366] [IGT] panfrost_submit: exiting, ret=77
11180 23:10:05.815901 file or directory
11181 23:10:05.826301 [1mSubtest pan-submit-error-no-jc: SKIP (0.0<8>[ 21.089562] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip>
11182 23:10:05.826384 00s)[0m
11183 23:10:05.826623 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip
11185 23:10:05.832456 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10 aarch64)
11186 23:10:05.839144 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
11187 23:10:05.842693 Test requirement: !(fd<0)
11188 23:10:05.849430 No known gpu found for chipset flags 0x32 (panfrost)
11189 23:10:05.853013 Last errno: 2<14>[ 21.119889] [IGT] panfrost_submit: executing
11190 23:10:05.856282 , No such file or directory
11191 23:10:05.862783 [1mSubtest pan-sub<14>[ 21.128215] [IGT] panfrost_submit: exiting, ret=77
11192 23:10:05.866124 mit-error-bad-in-syncs: SKIP (0.000s)[0m
11193 23:10:05.879612 IGT-Version: 1.27.1-g621c2d3 (aarch64<8>[ 21.141117] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip>
11194 23:10:05.880307 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip
11196 23:10:05.882683 ) (Linux: 6.1.64-cip10 aarch64)
11197 23:10:05.889244 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
11198 23:10:05.892318 Test requirement: !(fd<0)
11199 23:10:05.895883 No known gpu found for chipset flags 0x32 (panfrost)
11200 23:10:05.899377 Last errno: 2, No such file or directory
11201 23:10:05.905954 [1mSubtest pan-submit-error-bad-b<14>[ 21.172859] [IGT] panfrost_submit: executing
11202 23:10:05.909808 o-handles: SKIP (0.000s)[0m
11203 23:10:05.916436 IGT-Version: 1.27.<14>[ 21.181320] [IGT] panfrost_submit: exiting, ret=77
11204 23:10:05.922677 1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10 aarch64)
11205 23:10:05.933162 Test requirement not met in function drm_ope<8>[ 21.195217] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip>
11206 23:10:05.934170 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip
11208 23:10:05.935577 n_driver, file ../lib/drmtest.c:621:
11209 23:10:05.939199 Test requirement: !(fd<0)
11210 23:10:05.946002 No known gpu found for chipset flags 0x32 (panfrost)
11211 23:10:05.952675 Last errno: 2, No such fi<14>[ 21.217007] [IGT] panfrost_submit: executing
11212 23:10:05.953227 le or directory
11213 23:10:05.959200 [1mSubtest pan<14>[ 21.224047] [IGT] panfrost_submit: exiting, ret=77
11214 23:10:05.962285 -submit-error-bad-requirements: SKIP (0.000s)[0m
11215 23:10:05.972671 IGT-Version: <8>[ 21.235254] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip>
11216 23:10:05.973490 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip
11218 23:10:05.978722 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10 aarch64)
11219 23:10:05.985915 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
11220 23:10:05.989384 Test requirement: !(fd<0)
11221 23:10:05.991953 No known g<14>[ 21.258556] [IGT] panfrost_submit: executing
11222 23:10:06.002348 pu found for chipset flags 0x32 <14>[ 21.265981] [IGT] panfrost_submit: exiting, ret=77
11223 23:10:06.002889 (panfrost)
11224 23:10:06.005319 Last errno: 2, No such file or directory
11225 23:10:06.012039 [1mSubtes<8>[ 21.277210] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-reset RESULT=skip>
11226 23:10:06.012795 Received signal: <TESTCASE> TEST_CASE_ID=pan-reset RESULT=skip
11228 23:10:06.018972 t pan-submit-error-bad-out-sync: SKIP (0.000s)[0m
11229 23:10:06.025630 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10 aarch64)
11230 23:10:06.031806 Test requirement not met in function d<14>[ 21.296742] [IGT] panfrost_submit: executing
11231 23:10:06.038250 rm_open_driver, file ../lib/drmt<14>[ 21.304765] [IGT] panfrost_submit: exiting, ret=77
11232 23:10:06.041951 est.c:621:
11233 23:10:06.042492 Test requirement: !(fd<0)
11234 23:10:06.051995 No known gpu found for ch<8>[ 21.316191] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-and-close RESULT=skip>
11235 23:10:06.052877 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-and-close RESULT=skip
11237 23:10:06.055326 ipset flags 0x32 (panfrost)
11238 23:10:06.057955 Last errno: 2, No such file or directory
11239 23:10:06.061302 [1mSubtest pan-reset: SKIP (0.000s)[0m
11240 23:10:06.071855 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: <14>[ 21.337475] [IGT] panfrost_submit: executing
11241 23:10:06.074661 6.1.64-cip10 aarch64)
11242 23:10:06.078463 Test requ<14>[ 21.344653] [IGT] panfrost_submit: exiting, ret=77
11243 23:10:06.094954 irement not met in function drm_open_driver, file ../lib/drmtest<8>[ 21.356195] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip>
11244 23:10:06.095536 .c:621:
11245 23:10:06.096310 Received signal: <TESTCASE> TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip
11247 23:10:06.101350 Test requirement: !(fd<<8>[ 21.365645] <LAVA_SIGNAL_TESTSET STOP>
11248 23:10:06.101987 0)
11249 23:10:06.102760 Received signal: <TESTSET> STOP
11250 23:10:06.103164 Closing test_set panfrost_submit
11251 23:10:06.107948 No known gpu<8>[ 21.371815] <LAVA_SIGNAL_ENDRUN 0_igt-gpu-panfrost 12154438_1.5.2.3.1>
11252 23:10:06.108676 Received signal: <ENDRUN> 0_igt-gpu-panfrost 12154438_1.5.2.3.1
11253 23:10:06.109139 Ending use of test pattern.
11254 23:10:06.109489 Ending test lava.0_igt-gpu-panfrost (12154438_1.5.2.3.1), duration 0.83
11256 23:10:06.111428 found for chipset flags 0x32 (panfrost)
11257 23:10:06.114525 Last errno: 2, No such file or directory
11258 23:10:06.121186 [1mSubtest pan-submit-and-close: SKIP (0.000s)[0m
11259 23:10:06.127664 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10 aarch64)
11260 23:10:06.134158 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
11261 23:10:06.134620 Test requirement: !(fd<0)
11262 23:10:06.141045 No known gpu found for chipset flags 0x32 (panfrost)
11263 23:10:06.144165 Last errno: 2, No such file or directory
11264 23:10:06.147436 [1mSubtest pan-unhandled-pagefault: SKIP (0.000s)[0m
11265 23:10:06.150864 + set +x
11266 23:10:06.151276 <LAVA_TEST_RUNNER EXIT>
11267 23:10:06.151859 ok: lava_test_shell seems to have completed
11268 23:10:06.153742 base-params:
result: skip
set: panfrost_get_param
gem-new-0:
result: skip
set: panfrost_gem_new
gem-new-4096:
result: skip
set: panfrost_gem_new
gem-new-zeroed:
result: skip
set: panfrost_gem_new
gem-prime-import:
result: skip
set: panfrost_prime
get-bad-padding:
result: skip
set: panfrost_get_param
get-bad-param:
result: skip
set: panfrost_get_param
pan-reset:
result: skip
set: panfrost_submit
pan-submit:
result: skip
set: panfrost_submit
pan-submit-and-close:
result: skip
set: panfrost_submit
pan-submit-error-bad-bo-handles:
result: skip
set: panfrost_submit
pan-submit-error-bad-in-syncs:
result: skip
set: panfrost_submit
pan-submit-error-bad-out-sync:
result: skip
set: panfrost_submit
pan-submit-error-bad-requirements:
result: skip
set: panfrost_submit
pan-submit-error-no-jc:
result: skip
set: panfrost_submit
pan-unhandled-pagefault:
result: skip
set: panfrost_submit
11269 23:10:06.154252 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11270 23:10:06.154671 end: 3 lava-test-retry (duration 00:00:01) [common]
11271 23:10:06.155094 start: 4 finalize (timeout 00:07:47) [common]
11272 23:10:06.155531 start: 4.1 power-off (timeout 00:00:30) [common]
11273 23:10:06.156250 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11274 23:10:06.276643 >> Command sent successfully.
11275 23:10:06.280460 Returned 0 in 0 seconds
11276 23:10:06.381367 end: 4.1 power-off (duration 00:00:00) [common]
11278 23:10:06.383392 start: 4.2 read-feedback (timeout 00:07:47) [common]
11279 23:10:06.384836 Listened to connection for namespace 'common' for up to 1s
11280 23:10:07.385258 Finalising connection for namespace 'common'
11281 23:10:07.385451 Disconnecting from shell: Finalise
11282 23:10:07.385567 / #
11283 23:10:07.485907 end: 4.2 read-feedback (duration 00:00:01) [common]
11284 23:10:07.486103 end: 4 finalize (duration 00:00:01) [common]
11285 23:10:07.486266 Cleaning after the job
11286 23:10:07.486396 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12154438/tftp-deploy-d_6wcibw/ramdisk
11287 23:10:07.494825 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12154438/tftp-deploy-d_6wcibw/kernel
11288 23:10:07.503835 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12154438/tftp-deploy-d_6wcibw/dtb
11289 23:10:07.504053 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12154438/tftp-deploy-d_6wcibw/modules
11290 23:10:07.511639 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12154438
11291 23:10:07.635842 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12154438
11292 23:10:07.636033 Job finished correctly