Boot log: mt8192-asurada-spherion-r0
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 27
- Kernel Errors: 37
- Errors: 0
1 23:06:01.717368 lava-dispatcher, installed at version: 2023.10
2 23:06:01.717582 start: 0 validate
3 23:06:01.717712 Start time: 2023-12-01 23:06:01.717705+00:00 (UTC)
4 23:06:01.717838 Using caching service: 'http://localhost/cache/?uri=%s'
5 23:06:01.717991 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 23:06:01.985204 Using caching service: 'http://localhost/cache/?uri=%s'
7 23:06:01.985395 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.64-cip10%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 23:06:02.251235 Using caching service: 'http://localhost/cache/?uri=%s'
9 23:06:02.251422 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.64-cip10%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 23:06:02.517734 Using caching service: 'http://localhost/cache/?uri=%s'
11 23:06:02.517910 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 23:06:02.783190 Using caching service: 'http://localhost/cache/?uri=%s'
13 23:06:02.783373 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.64-cip10%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 23:06:03.048901 validate duration: 1.33
16 23:06:03.049164 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 23:06:03.049276 start: 1.1 download-retry (timeout 00:10:00) [common]
18 23:06:03.049379 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 23:06:03.049502 Not decompressing ramdisk as can be used compressed.
20 23:06:03.049586 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20230623.0/arm64/initrd.cpio.gz
21 23:06:03.049649 saving as /var/lib/lava/dispatcher/tmp/12154437/tftp-deploy-jquy125z/ramdisk/initrd.cpio.gz
22 23:06:03.049713 total size: 5625687 (5 MB)
23 23:06:03.050792 progress 0 % (0 MB)
24 23:06:03.052423 progress 5 % (0 MB)
25 23:06:03.053979 progress 10 % (0 MB)
26 23:06:03.055466 progress 15 % (0 MB)
27 23:06:03.057045 progress 20 % (1 MB)
28 23:06:03.058429 progress 25 % (1 MB)
29 23:06:03.059967 progress 30 % (1 MB)
30 23:06:03.061462 progress 35 % (1 MB)
31 23:06:03.062855 progress 40 % (2 MB)
32 23:06:03.064351 progress 45 % (2 MB)
33 23:06:03.065685 progress 50 % (2 MB)
34 23:06:03.067228 progress 55 % (2 MB)
35 23:06:03.068716 progress 60 % (3 MB)
36 23:06:03.070085 progress 65 % (3 MB)
37 23:06:03.071701 progress 70 % (3 MB)
38 23:06:03.073038 progress 75 % (4 MB)
39 23:06:03.074586 progress 80 % (4 MB)
40 23:06:03.075917 progress 85 % (4 MB)
41 23:06:03.077435 progress 90 % (4 MB)
42 23:06:03.078976 progress 95 % (5 MB)
43 23:06:03.080383 progress 100 % (5 MB)
44 23:06:03.080576 5 MB downloaded in 0.03 s (173.84 MB/s)
45 23:06:03.080729 end: 1.1.1 http-download (duration 00:00:00) [common]
47 23:06:03.080964 end: 1.1 download-retry (duration 00:00:00) [common]
48 23:06:03.081049 start: 1.2 download-retry (timeout 00:10:00) [common]
49 23:06:03.081132 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 23:06:03.081258 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.64-cip10/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 23:06:03.081325 saving as /var/lib/lava/dispatcher/tmp/12154437/tftp-deploy-jquy125z/kernel/Image
52 23:06:03.081385 total size: 49172992 (46 MB)
53 23:06:03.081444 No compression specified
54 23:06:03.082508 progress 0 % (0 MB)
55 23:06:03.094743 progress 5 % (2 MB)
56 23:06:03.106840 progress 10 % (4 MB)
57 23:06:03.119081 progress 15 % (7 MB)
58 23:06:03.131696 progress 20 % (9 MB)
59 23:06:03.144141 progress 25 % (11 MB)
60 23:06:03.156568 progress 30 % (14 MB)
61 23:06:03.168932 progress 35 % (16 MB)
62 23:06:03.181318 progress 40 % (18 MB)
63 23:06:03.193677 progress 45 % (21 MB)
64 23:06:03.205959 progress 50 % (23 MB)
65 23:06:03.218171 progress 55 % (25 MB)
66 23:06:03.230544 progress 60 % (28 MB)
67 23:06:03.242745 progress 65 % (30 MB)
68 23:06:03.254971 progress 70 % (32 MB)
69 23:06:03.267291 progress 75 % (35 MB)
70 23:06:03.279625 progress 80 % (37 MB)
71 23:06:03.292326 progress 85 % (39 MB)
72 23:06:03.305328 progress 90 % (42 MB)
73 23:06:03.317547 progress 95 % (44 MB)
74 23:06:03.329734 progress 100 % (46 MB)
75 23:06:03.329939 46 MB downloaded in 0.25 s (188.67 MB/s)
76 23:06:03.330089 end: 1.2.1 http-download (duration 00:00:00) [common]
78 23:06:03.330327 end: 1.2 download-retry (duration 00:00:00) [common]
79 23:06:03.330421 start: 1.3 download-retry (timeout 00:10:00) [common]
80 23:06:03.330548 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 23:06:03.330679 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.64-cip10/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 23:06:03.330749 saving as /var/lib/lava/dispatcher/tmp/12154437/tftp-deploy-jquy125z/dtb/mt8192-asurada-spherion-r0.dtb
83 23:06:03.330812 total size: 47278 (0 MB)
84 23:06:03.330872 No compression specified
85 23:06:03.331969 progress 69 % (0 MB)
86 23:06:03.332245 progress 100 % (0 MB)
87 23:06:03.332400 0 MB downloaded in 0.00 s (28.42 MB/s)
88 23:06:03.332524 end: 1.3.1 http-download (duration 00:00:00) [common]
90 23:06:03.332746 end: 1.3 download-retry (duration 00:00:00) [common]
91 23:06:03.332835 start: 1.4 download-retry (timeout 00:10:00) [common]
92 23:06:03.332919 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 23:06:03.333028 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20230623.0/arm64/full.rootfs.tar.xz
94 23:06:03.333095 saving as /var/lib/lava/dispatcher/tmp/12154437/tftp-deploy-jquy125z/nfsrootfs/full.rootfs.tar
95 23:06:03.333155 total size: 195204440 (186 MB)
96 23:06:03.333217 Using unxz to decompress xz
97 23:06:03.336874 progress 0 % (0 MB)
98 23:06:03.877069 progress 5 % (9 MB)
99 23:06:04.364496 progress 10 % (18 MB)
100 23:06:04.933015 progress 15 % (27 MB)
101 23:06:05.207225 progress 20 % (37 MB)
102 23:06:05.656466 progress 25 % (46 MB)
103 23:06:06.213922 progress 30 % (55 MB)
104 23:06:06.760823 progress 35 % (65 MB)
105 23:06:07.321185 progress 40 % (74 MB)
106 23:06:07.905859 progress 45 % (83 MB)
107 23:06:08.508895 progress 50 % (93 MB)
108 23:06:09.112052 progress 55 % (102 MB)
109 23:06:09.770194 progress 60 % (111 MB)
110 23:06:10.142351 progress 65 % (121 MB)
111 23:06:10.222766 progress 70 % (130 MB)
112 23:06:10.361551 progress 75 % (139 MB)
113 23:06:10.441607 progress 80 % (148 MB)
114 23:06:10.486986 progress 85 % (158 MB)
115 23:06:10.577755 progress 90 % (167 MB)
116 23:06:10.951079 progress 95 % (176 MB)
117 23:06:11.530331 progress 100 % (186 MB)
118 23:06:11.535500 186 MB downloaded in 8.20 s (22.70 MB/s)
119 23:06:11.535831 end: 1.4.1 http-download (duration 00:00:08) [common]
121 23:06:11.536266 end: 1.4 download-retry (duration 00:00:08) [common]
122 23:06:11.536395 start: 1.5 download-retry (timeout 00:09:52) [common]
123 23:06:11.536521 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 23:06:11.536712 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.64-cip10/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 23:06:11.536813 saving as /var/lib/lava/dispatcher/tmp/12154437/tftp-deploy-jquy125z/modules/modules.tar
126 23:06:11.536917 total size: 8616152 (8 MB)
127 23:06:11.537014 Using unxz to decompress xz
128 23:06:11.541370 progress 0 % (0 MB)
129 23:06:11.563042 progress 5 % (0 MB)
130 23:06:11.587257 progress 10 % (0 MB)
131 23:06:11.611927 progress 15 % (1 MB)
132 23:06:11.636647 progress 20 % (1 MB)
133 23:06:11.661511 progress 25 % (2 MB)
134 23:06:11.688100 progress 30 % (2 MB)
135 23:06:11.715683 progress 35 % (2 MB)
136 23:06:11.740590 progress 40 % (3 MB)
137 23:06:11.765389 progress 45 % (3 MB)
138 23:06:11.791591 progress 50 % (4 MB)
139 23:06:11.816466 progress 55 % (4 MB)
140 23:06:11.841957 progress 60 % (4 MB)
141 23:06:11.868100 progress 65 % (5 MB)
142 23:06:11.896024 progress 70 % (5 MB)
143 23:06:11.920105 progress 75 % (6 MB)
144 23:06:11.947295 progress 80 % (6 MB)
145 23:06:11.973591 progress 85 % (7 MB)
146 23:06:11.999507 progress 90 % (7 MB)
147 23:06:12.029197 progress 95 % (7 MB)
148 23:06:12.057021 progress 100 % (8 MB)
149 23:06:12.063590 8 MB downloaded in 0.53 s (15.60 MB/s)
150 23:06:12.063902 end: 1.5.1 http-download (duration 00:00:01) [common]
152 23:06:12.064313 end: 1.5 download-retry (duration 00:00:01) [common]
153 23:06:12.064439 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 23:06:12.064568 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 23:06:15.977463 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12154437/extract-nfsrootfs-69vuva4v
156 23:06:15.977679 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 23:06:15.977783 start: 1.6.2 lava-overlay (timeout 00:09:47) [common]
158 23:06:15.977957 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12154437/lava-overlay-imvorbzi
159 23:06:15.978085 makedir: /var/lib/lava/dispatcher/tmp/12154437/lava-overlay-imvorbzi/lava-12154437/bin
160 23:06:15.978187 makedir: /var/lib/lava/dispatcher/tmp/12154437/lava-overlay-imvorbzi/lava-12154437/tests
161 23:06:15.978291 makedir: /var/lib/lava/dispatcher/tmp/12154437/lava-overlay-imvorbzi/lava-12154437/results
162 23:06:15.978417 Creating /var/lib/lava/dispatcher/tmp/12154437/lava-overlay-imvorbzi/lava-12154437/bin/lava-add-keys
163 23:06:15.978575 Creating /var/lib/lava/dispatcher/tmp/12154437/lava-overlay-imvorbzi/lava-12154437/bin/lava-add-sources
164 23:06:15.978702 Creating /var/lib/lava/dispatcher/tmp/12154437/lava-overlay-imvorbzi/lava-12154437/bin/lava-background-process-start
165 23:06:15.978829 Creating /var/lib/lava/dispatcher/tmp/12154437/lava-overlay-imvorbzi/lava-12154437/bin/lava-background-process-stop
166 23:06:15.979022 Creating /var/lib/lava/dispatcher/tmp/12154437/lava-overlay-imvorbzi/lava-12154437/bin/lava-common-functions
167 23:06:15.979145 Creating /var/lib/lava/dispatcher/tmp/12154437/lava-overlay-imvorbzi/lava-12154437/bin/lava-echo-ipv4
168 23:06:15.979268 Creating /var/lib/lava/dispatcher/tmp/12154437/lava-overlay-imvorbzi/lava-12154437/bin/lava-install-packages
169 23:06:15.979389 Creating /var/lib/lava/dispatcher/tmp/12154437/lava-overlay-imvorbzi/lava-12154437/bin/lava-installed-packages
170 23:06:15.979515 Creating /var/lib/lava/dispatcher/tmp/12154437/lava-overlay-imvorbzi/lava-12154437/bin/lava-os-build
171 23:06:15.979637 Creating /var/lib/lava/dispatcher/tmp/12154437/lava-overlay-imvorbzi/lava-12154437/bin/lava-probe-channel
172 23:06:15.979758 Creating /var/lib/lava/dispatcher/tmp/12154437/lava-overlay-imvorbzi/lava-12154437/bin/lava-probe-ip
173 23:06:15.979880 Creating /var/lib/lava/dispatcher/tmp/12154437/lava-overlay-imvorbzi/lava-12154437/bin/lava-target-ip
174 23:06:15.980001 Creating /var/lib/lava/dispatcher/tmp/12154437/lava-overlay-imvorbzi/lava-12154437/bin/lava-target-mac
175 23:06:15.980121 Creating /var/lib/lava/dispatcher/tmp/12154437/lava-overlay-imvorbzi/lava-12154437/bin/lava-target-storage
176 23:06:15.980245 Creating /var/lib/lava/dispatcher/tmp/12154437/lava-overlay-imvorbzi/lava-12154437/bin/lava-test-case
177 23:06:15.980369 Creating /var/lib/lava/dispatcher/tmp/12154437/lava-overlay-imvorbzi/lava-12154437/bin/lava-test-event
178 23:06:15.980490 Creating /var/lib/lava/dispatcher/tmp/12154437/lava-overlay-imvorbzi/lava-12154437/bin/lava-test-feedback
179 23:06:15.980611 Creating /var/lib/lava/dispatcher/tmp/12154437/lava-overlay-imvorbzi/lava-12154437/bin/lava-test-raise
180 23:06:15.980732 Creating /var/lib/lava/dispatcher/tmp/12154437/lava-overlay-imvorbzi/lava-12154437/bin/lava-test-reference
181 23:06:15.980856 Creating /var/lib/lava/dispatcher/tmp/12154437/lava-overlay-imvorbzi/lava-12154437/bin/lava-test-runner
182 23:06:15.980978 Creating /var/lib/lava/dispatcher/tmp/12154437/lava-overlay-imvorbzi/lava-12154437/bin/lava-test-set
183 23:06:15.981102 Creating /var/lib/lava/dispatcher/tmp/12154437/lava-overlay-imvorbzi/lava-12154437/bin/lava-test-shell
184 23:06:15.981226 Updating /var/lib/lava/dispatcher/tmp/12154437/lava-overlay-imvorbzi/lava-12154437/bin/lava-add-keys (debian)
185 23:06:15.981380 Updating /var/lib/lava/dispatcher/tmp/12154437/lava-overlay-imvorbzi/lava-12154437/bin/lava-add-sources (debian)
186 23:06:15.981527 Updating /var/lib/lava/dispatcher/tmp/12154437/lava-overlay-imvorbzi/lava-12154437/bin/lava-install-packages (debian)
187 23:06:15.981663 Updating /var/lib/lava/dispatcher/tmp/12154437/lava-overlay-imvorbzi/lava-12154437/bin/lava-installed-packages (debian)
188 23:06:15.981803 Updating /var/lib/lava/dispatcher/tmp/12154437/lava-overlay-imvorbzi/lava-12154437/bin/lava-os-build (debian)
189 23:06:15.981927 Creating /var/lib/lava/dispatcher/tmp/12154437/lava-overlay-imvorbzi/lava-12154437/environment
190 23:06:15.982026 LAVA metadata
191 23:06:15.982097 - LAVA_JOB_ID=12154437
192 23:06:15.982162 - LAVA_DISPATCHER_IP=192.168.201.1
193 23:06:15.982267 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:47) [common]
194 23:06:15.982338 skipped lava-vland-overlay
195 23:06:15.982593 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 23:06:15.982681 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:47) [common]
197 23:06:15.982746 skipped lava-multinode-overlay
198 23:06:15.982823 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 23:06:15.982906 start: 1.6.2.3 test-definition (timeout 00:09:47) [common]
200 23:06:15.982986 Loading test definitions
201 23:06:15.983080 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:47) [common]
202 23:06:15.983154 Using /lava-12154437 at stage 0
203 23:06:15.983461 uuid=12154437_1.6.2.3.1 testdef=None
204 23:06:15.983553 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 23:06:15.983641 start: 1.6.2.3.2 test-overlay (timeout 00:09:47) [common]
206 23:06:15.984088 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 23:06:15.984315 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:47) [common]
209 23:06:15.984862 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 23:06:15.985105 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:47) [common]
212 23:06:15.985642 runner path: /var/lib/lava/dispatcher/tmp/12154437/lava-overlay-imvorbzi/lava-12154437/0/tests/0_timesync-off test_uuid 12154437_1.6.2.3.1
213 23:06:15.985798 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 23:06:15.986029 start: 1.6.2.3.5 git-repo-action (timeout 00:09:47) [common]
216 23:06:15.986105 Using /lava-12154437 at stage 0
217 23:06:15.986203 Fetching tests from https://github.com/kernelci/test-definitions.git
218 23:06:15.986284 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/12154437/lava-overlay-imvorbzi/lava-12154437/0/tests/1_kselftest-alsa'
219 23:06:18.657454 Running '/usr/bin/git checkout kernelci.org
220 23:06:18.804834 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12154437/lava-overlay-imvorbzi/lava-12154437/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
221 23:06:18.805541 uuid=12154437_1.6.2.3.5 testdef=None
222 23:06:18.805707 end: 1.6.2.3.5 git-repo-action (duration 00:00:03) [common]
224 23:06:18.805957 start: 1.6.2.3.6 test-overlay (timeout 00:09:44) [common]
225 23:06:18.806744 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 23:06:18.806980 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:44) [common]
228 23:06:18.807966 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 23:06:18.808205 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:44) [common]
231 23:06:18.809120 runner path: /var/lib/lava/dispatcher/tmp/12154437/lava-overlay-imvorbzi/lava-12154437/0/tests/1_kselftest-alsa test_uuid 12154437_1.6.2.3.5
232 23:06:18.809213 BOARD='mt8192-asurada-spherion-r0'
233 23:06:18.809280 BRANCH='cip'
234 23:06:18.809341 SKIPFILE='/dev/null'
235 23:06:18.809401 SKIP_INSTALL='True'
236 23:06:18.809458 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.64-cip10/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 23:06:18.809518 TST_CASENAME=''
238 23:06:18.809574 TST_CMDFILES='alsa'
239 23:06:18.809711 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 23:06:18.809921 Creating lava-test-runner.conf files
242 23:06:18.809986 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12154437/lava-overlay-imvorbzi/lava-12154437/0 for stage 0
243 23:06:18.810078 - 0_timesync-off
244 23:06:18.810153 - 1_kselftest-alsa
245 23:06:18.810251 end: 1.6.2.3 test-definition (duration 00:00:03) [common]
246 23:06:18.810342 start: 1.6.2.4 compress-overlay (timeout 00:09:44) [common]
247 23:06:26.349930 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 23:06:26.350119 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:37) [common]
249 23:06:26.350246 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 23:06:26.350380 end: 1.6.2 lava-overlay (duration 00:00:10) [common]
251 23:06:26.350546 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:37) [common]
252 23:06:26.514585 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 23:06:26.515003 start: 1.6.4 extract-modules (timeout 00:09:37) [common]
254 23:06:26.515153 extracting modules file /var/lib/lava/dispatcher/tmp/12154437/tftp-deploy-jquy125z/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12154437/extract-nfsrootfs-69vuva4v
255 23:06:26.773355 extracting modules file /var/lib/lava/dispatcher/tmp/12154437/tftp-deploy-jquy125z/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12154437/extract-overlay-ramdisk-tte3osp4/ramdisk
256 23:06:26.980800 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 23:06:26.980997 start: 1.6.5 apply-overlay-tftp (timeout 00:09:36) [common]
258 23:06:26.981093 [common] Applying overlay to NFS
259 23:06:26.981193 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12154437/compress-overlay-he14pohm/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12154437/extract-nfsrootfs-69vuva4v
260 23:06:27.861329 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 23:06:27.861505 start: 1.6.6 configure-preseed-file (timeout 00:09:35) [common]
262 23:06:27.861599 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 23:06:27.861688 start: 1.6.7 compress-ramdisk (timeout 00:09:35) [common]
264 23:06:27.861773 Building ramdisk /var/lib/lava/dispatcher/tmp/12154437/extract-overlay-ramdisk-tte3osp4/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12154437/extract-overlay-ramdisk-tte3osp4/ramdisk
265 23:06:28.148224 >> 130532 blocks
266 23:06:30.204831 rename /var/lib/lava/dispatcher/tmp/12154437/extract-overlay-ramdisk-tte3osp4/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12154437/tftp-deploy-jquy125z/ramdisk/ramdisk.cpio.gz
267 23:06:30.205251 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 23:06:30.205372 start: 1.6.8 prepare-kernel (timeout 00:09:33) [common]
269 23:06:30.205476 start: 1.6.8.1 prepare-fit (timeout 00:09:33) [common]
270 23:06:30.205589 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12154437/tftp-deploy-jquy125z/kernel/Image'
271 23:06:42.158207 Returned 0 in 11 seconds
272 23:06:42.258838 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12154437/tftp-deploy-jquy125z/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12154437/tftp-deploy-jquy125z/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12154437/tftp-deploy-jquy125z/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12154437/tftp-deploy-jquy125z/kernel/image.itb
273 23:06:42.609060 output: FIT description: Kernel Image image with one or more FDT blobs
274 23:06:42.609422 output: Created: Fri Dec 1 23:06:42 2023
275 23:06:42.609498 output: Image 0 (kernel-1)
276 23:06:42.609566 output: Description:
277 23:06:42.609636 output: Created: Fri Dec 1 23:06:42 2023
278 23:06:42.609702 output: Type: Kernel Image
279 23:06:42.609767 output: Compression: lzma compressed
280 23:06:42.609828 output: Data Size: 11043984 Bytes = 10785.14 KiB = 10.53 MiB
281 23:06:42.609899 output: Architecture: AArch64
282 23:06:42.609957 output: OS: Linux
283 23:06:42.610017 output: Load Address: 0x00000000
284 23:06:42.610075 output: Entry Point: 0x00000000
285 23:06:42.610141 output: Hash algo: crc32
286 23:06:42.610200 output: Hash value: 36c84243
287 23:06:42.610257 output: Image 1 (fdt-1)
288 23:06:42.610314 output: Description: mt8192-asurada-spherion-r0
289 23:06:42.610375 output: Created: Fri Dec 1 23:06:42 2023
290 23:06:42.610476 output: Type: Flat Device Tree
291 23:06:42.610531 output: Compression: uncompressed
292 23:06:42.610585 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 23:06:42.610647 output: Architecture: AArch64
294 23:06:42.610701 output: Hash algo: crc32
295 23:06:42.610754 output: Hash value: cc4352de
296 23:06:42.610808 output: Image 2 (ramdisk-1)
297 23:06:42.610867 output: Description: unavailable
298 23:06:42.610923 output: Created: Fri Dec 1 23:06:42 2023
299 23:06:42.610976 output: Type: RAMDisk Image
300 23:06:42.611029 output: Compression: Unknown Compression
301 23:06:42.611083 output: Data Size: 18760031 Bytes = 18320.34 KiB = 17.89 MiB
302 23:06:42.611151 output: Architecture: AArch64
303 23:06:42.611220 output: OS: Linux
304 23:06:42.611275 output: Load Address: unavailable
305 23:06:42.611329 output: Entry Point: unavailable
306 23:06:42.611390 output: Hash algo: crc32
307 23:06:42.611445 output: Hash value: 41f68db0
308 23:06:42.611499 output: Default Configuration: 'conf-1'
309 23:06:42.611552 output: Configuration 0 (conf-1)
310 23:06:42.611611 output: Description: mt8192-asurada-spherion-r0
311 23:06:42.611666 output: Kernel: kernel-1
312 23:06:42.611719 output: Init Ramdisk: ramdisk-1
313 23:06:42.611772 output: FDT: fdt-1
314 23:06:42.611825 output: Loadables: kernel-1
315 23:06:42.611885 output:
316 23:06:42.612077 end: 1.6.8.1 prepare-fit (duration 00:00:12) [common]
317 23:06:42.612183 end: 1.6.8 prepare-kernel (duration 00:00:12) [common]
318 23:06:42.612289 end: 1.6 prepare-tftp-overlay (duration 00:00:31) [common]
319 23:06:42.612389 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:20) [common]
320 23:06:42.612473 No LXC device requested
321 23:06:42.612552 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 23:06:42.612649 start: 1.8 deploy-device-env (timeout 00:09:20) [common]
323 23:06:42.612730 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 23:06:42.612800 Checking files for TFTP limit of 4294967296 bytes.
325 23:06:42.613293 end: 1 tftp-deploy (duration 00:00:40) [common]
326 23:06:42.613409 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 23:06:42.613502 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 23:06:42.613634 substitutions:
329 23:06:42.613703 - {DTB}: 12154437/tftp-deploy-jquy125z/dtb/mt8192-asurada-spherion-r0.dtb
330 23:06:42.613769 - {INITRD}: 12154437/tftp-deploy-jquy125z/ramdisk/ramdisk.cpio.gz
331 23:06:42.613830 - {KERNEL}: 12154437/tftp-deploy-jquy125z/kernel/Image
332 23:06:42.613896 - {LAVA_MAC}: None
333 23:06:42.613956 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12154437/extract-nfsrootfs-69vuva4v
334 23:06:42.614014 - {NFS_SERVER_IP}: 192.168.201.1
335 23:06:42.614071 - {PRESEED_CONFIG}: None
336 23:06:42.614134 - {PRESEED_LOCAL}: None
337 23:06:42.614191 - {RAMDISK}: 12154437/tftp-deploy-jquy125z/ramdisk/ramdisk.cpio.gz
338 23:06:42.614245 - {ROOT_PART}: None
339 23:06:42.614300 - {ROOT}: None
340 23:06:42.614361 - {SERVER_IP}: 192.168.201.1
341 23:06:42.614457 - {TEE}: None
342 23:06:42.614513 Parsed boot commands:
343 23:06:42.614567 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 23:06:42.614751 Parsed boot commands: tftpboot 192.168.201.1 12154437/tftp-deploy-jquy125z/kernel/image.itb 12154437/tftp-deploy-jquy125z/kernel/cmdline
345 23:06:42.614842 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 23:06:42.614941 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 23:06:42.615057 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 23:06:42.615160 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 23:06:42.615233 Not connected, no need to disconnect.
350 23:06:42.615310 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 23:06:42.615404 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 23:06:42.615472 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-1'
353 23:06:42.618913 Setting prompt string to ['lava-test: # ']
354 23:06:42.619296 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 23:06:42.619450 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 23:06:42.619571 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 23:06:42.619684 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 23:06:42.619876 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=reboot'
359 23:06:47.753410 >> Command sent successfully.
360 23:06:47.755795 Returned 0 in 5 seconds
361 23:06:47.856166 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 23:06:47.856492 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 23:06:47.856602 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 23:06:47.856691 Setting prompt string to 'Starting depthcharge on Spherion...'
366 23:06:47.856760 Changing prompt to 'Starting depthcharge on Spherion...'
367 23:06:47.856837 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 23:06:47.857107 [Enter `^Ec?' for help]
369 23:06:48.031611
370 23:06:48.031758
371 23:06:48.031833 F0: 102B 0000
372 23:06:48.031902
373 23:06:48.031970 F3: 1001 0000 [0200]
374 23:06:48.032032
375 23:06:48.034840 F3: 1001 0000
376 23:06:48.034911
377 23:06:48.034979 F7: 102D 0000
378 23:06:48.035039
379 23:06:48.037999 F1: 0000 0000
380 23:06:48.038069
381 23:06:48.038133 V0: 0000 0000 [0001]
382 23:06:48.038192
383 23:06:48.041583 00: 0007 8000
384 23:06:48.041656
385 23:06:48.041723 01: 0000 0000
386 23:06:48.041782
387 23:06:48.044777 BP: 0C00 0209 [0000]
388 23:06:48.044883
389 23:06:48.044952 G0: 1182 0000
390 23:06:48.045016
391 23:06:48.045076 EC: 0000 0021 [4000]
392 23:06:48.048686
393 23:06:48.048772 S7: 0000 0000 [0000]
394 23:06:48.048840
395 23:06:48.051826 CC: 0000 0000 [0001]
396 23:06:48.051911
397 23:06:48.051979 T0: 0000 0040 [010F]
398 23:06:48.052043
399 23:06:48.052105 Jump to BL
400 23:06:48.052166
401 23:06:48.078967
402 23:06:48.079058
403 23:06:48.079125
404 23:06:48.085860 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 23:06:48.089516 ARM64: Exception handlers installed.
406 23:06:48.093294 ARM64: Testing exception
407 23:06:48.096194 ARM64: Done test exception
408 23:06:48.103047 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 23:06:48.113411 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 23:06:48.120404 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 23:06:48.129930 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 23:06:48.136656 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 23:06:48.143034 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 23:06:48.154901 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 23:06:48.161983 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 23:06:48.181428 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 23:06:48.184458 WDT: Last reset was cold boot
418 23:06:48.188148 SPI1(PAD0) initialized at 2873684 Hz
419 23:06:48.191280 SPI5(PAD0) initialized at 992727 Hz
420 23:06:48.194614 VBOOT: Loading verstage.
421 23:06:48.201114 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 23:06:48.204374 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 23:06:48.207658 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 23:06:48.210851 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 23:06:48.218651 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 23:06:48.225225 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 23:06:48.236382 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
428 23:06:48.236460
429 23:06:48.236526
430 23:06:48.246489 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 23:06:48.249672 ARM64: Exception handlers installed.
432 23:06:48.253147 ARM64: Testing exception
433 23:06:48.253224 ARM64: Done test exception
434 23:06:48.259539 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 23:06:48.262938 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 23:06:48.277070 Probing TPM: . done!
437 23:06:48.277148 TPM ready after 0 ms
438 23:06:48.284308 Connected to device vid:did:rid of 1ae0:0028:00
439 23:06:48.291143 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
440 23:06:48.295046 Initialized TPM device CR50 revision 0
441 23:06:48.360314 tlcl_send_startup: Startup return code is 0
442 23:06:48.360416 TPM: setup succeeded
443 23:06:48.371833 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 23:06:48.380128 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 23:06:48.390388 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 23:06:48.399562 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 23:06:48.402746 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 23:06:48.411732 in-header: 03 07 00 00 08 00 00 00
449 23:06:48.415302 in-data: aa e4 47 04 13 02 00 00
450 23:06:48.418836 Chrome EC: UHEPI supported
451 23:06:48.425953 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 23:06:48.429570 in-header: 03 ad 00 00 08 00 00 00
453 23:06:48.433341 in-data: 00 20 20 08 00 00 00 00
454 23:06:48.433421 Phase 1
455 23:06:48.437705 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 23:06:48.445028 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 23:06:48.449022 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 23:06:48.452297 Recovery requested (1009000e)
459 23:06:48.460845 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 23:06:48.466180 tlcl_extend: response is 0
461 23:06:48.476314 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 23:06:48.481217 tlcl_extend: response is 0
463 23:06:48.488165 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 23:06:48.508954 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 23:06:48.516118 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 23:06:48.516216
467 23:06:48.516287
468 23:06:48.525939 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 23:06:48.529156 ARM64: Exception handlers installed.
470 23:06:48.529247 ARM64: Testing exception
471 23:06:48.532289 ARM64: Done test exception
472 23:06:48.555190 pmic_efuse_setting: Set efuses in 11 msecs
473 23:06:48.558667 pmwrap_interface_init: Select PMIF_VLD_RDY
474 23:06:48.564645 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 23:06:48.568461 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 23:06:48.572030 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 23:06:48.578685 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 23:06:48.581959 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 23:06:48.586269 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 23:06:48.593131 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 23:06:48.597263 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 23:06:48.600941 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 23:06:48.604833 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 23:06:48.611725 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 23:06:48.615884 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 23:06:48.618894 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 23:06:48.625577 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 23:06:48.632324 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 23:06:48.636017 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 23:06:48.643039 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 23:06:48.650212 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 23:06:48.653710 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 23:06:48.660475 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 23:06:48.664012 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 23:06:48.671461 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 23:06:48.677950 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 23:06:48.681148 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 23:06:48.688040 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 23:06:48.695116 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 23:06:48.698069 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 23:06:48.704430 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 23:06:48.708117 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 23:06:48.711300 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 23:06:48.718170 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 23:06:48.721535 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 23:06:48.727996 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 23:06:48.731680 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 23:06:48.738535 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 23:06:48.741596 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 23:06:48.748192 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 23:06:48.751542 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 23:06:48.758580 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 23:06:48.761735 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 23:06:48.766140 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 23:06:48.769123 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 23:06:48.775723 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 23:06:48.779175 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 23:06:48.782707 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 23:06:48.789384 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 23:06:48.792674 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 23:06:48.795825 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 23:06:48.799382 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 23:06:48.805793 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 23:06:48.809264 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 23:06:48.815957 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 23:06:48.825698 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 23:06:48.829090 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 23:06:48.839501 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 23:06:48.846039 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 23:06:48.849293 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 23:06:48.856390 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 23:06:48.859633 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 23:06:48.866899 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x32
534 23:06:48.874203 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 23:06:48.877958 [RTC]rtc_osc_init,62: osc32con val = 0xde70
536 23:06:48.880956 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 23:06:48.891304 [RTC]rtc_get_frequency_meter,154: input=15, output=772
538 23:06:48.901149 [RTC]rtc_get_frequency_meter,154: input=23, output=957
539 23:06:48.910682 [RTC]rtc_get_frequency_meter,154: input=19, output=864
540 23:06:48.920036 [RTC]rtc_get_frequency_meter,154: input=17, output=817
541 23:06:48.928985 [RTC]rtc_get_frequency_meter,154: input=16, output=796
542 23:06:48.932754 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
543 23:06:48.939324 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
544 23:06:48.942861 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
545 23:06:48.946071 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
546 23:06:48.949486 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
547 23:06:48.952929 ADC[4]: Raw value=902876 ID=7
548 23:06:48.956219 ADC[3]: Raw value=213179 ID=1
549 23:06:48.956289 RAM Code: 0x71
550 23:06:48.962827 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
551 23:06:48.965872 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
552 23:06:48.976989 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
553 23:06:48.981106 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
554 23:06:48.984257 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
555 23:06:48.987833 in-header: 03 07 00 00 08 00 00 00
556 23:06:48.991433 in-data: aa e4 47 04 13 02 00 00
557 23:06:48.995202 Chrome EC: UHEPI supported
558 23:06:49.002252 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
559 23:06:49.005465 in-header: 03 ed 00 00 08 00 00 00
560 23:06:49.009101 in-data: 80 20 60 08 00 00 00 00
561 23:06:49.012153 MRC: failed to locate region type 0.
562 23:06:49.018890 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
563 23:06:49.022248 DRAM-K: Running full calibration
564 23:06:49.028944 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
565 23:06:49.029047 header.status = 0x0
566 23:06:49.032564 header.version = 0x6 (expected: 0x6)
567 23:06:49.035420 header.size = 0xd00 (expected: 0xd00)
568 23:06:49.039003 header.flags = 0x0
569 23:06:49.042407 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
570 23:06:49.061490 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
571 23:06:49.068049 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
572 23:06:49.071599 dram_init: ddr_geometry: 2
573 23:06:49.074621 [EMI] MDL number = 2
574 23:06:49.074764 [EMI] Get MDL freq = 0
575 23:06:49.078570 dram_init: ddr_type: 0
576 23:06:49.078710 is_discrete_lpddr4: 1
577 23:06:49.081421 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
578 23:06:49.081556
579 23:06:49.081679
580 23:06:49.084663 [Bian_co] ETT version 0.0.0.1
581 23:06:49.091826 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
582 23:06:49.091945
583 23:06:49.094919 dramc_set_vcore_voltage set vcore to 650000
584 23:06:49.095057 Read voltage for 800, 4
585 23:06:49.098283 Vio18 = 0
586 23:06:49.098425 Vcore = 650000
587 23:06:49.098550 Vdram = 0
588 23:06:49.101642 Vddq = 0
589 23:06:49.101728 Vmddr = 0
590 23:06:49.104871 dram_init: config_dvfs: 1
591 23:06:49.108286 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
592 23:06:49.115307 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
593 23:06:49.118350 [SwImpedanceCal] DRVP=9, DRVN=15, ODTN=9
594 23:06:49.121575 freq_region=0, Reg: DRVP=9, DRVN=15, ODTN=9
595 23:06:49.125180 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
596 23:06:49.128256 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
597 23:06:49.131733 MEM_TYPE=3, freq_sel=18
598 23:06:49.134903 sv_algorithm_assistance_LP4_1600
599 23:06:49.138309 ============ PULL DRAM RESETB DOWN ============
600 23:06:49.141428 ========== PULL DRAM RESETB DOWN end =========
601 23:06:49.148433 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
602 23:06:49.151439 ===================================
603 23:06:49.151544 LPDDR4 DRAM CONFIGURATION
604 23:06:49.155358 ===================================
605 23:06:49.158290 EX_ROW_EN[0] = 0x0
606 23:06:49.161687 EX_ROW_EN[1] = 0x0
607 23:06:49.161802 LP4Y_EN = 0x0
608 23:06:49.165250 WORK_FSP = 0x0
609 23:06:49.165362 WL = 0x2
610 23:06:49.168278 RL = 0x2
611 23:06:49.168382 BL = 0x2
612 23:06:49.171788 RPST = 0x0
613 23:06:49.171890 RD_PRE = 0x0
614 23:06:49.174690 WR_PRE = 0x1
615 23:06:49.174793 WR_PST = 0x0
616 23:06:49.178166 DBI_WR = 0x0
617 23:06:49.178269 DBI_RD = 0x0
618 23:06:49.181526 OTF = 0x1
619 23:06:49.184866 ===================================
620 23:06:49.188538 ===================================
621 23:06:49.188645 ANA top config
622 23:06:49.191601 ===================================
623 23:06:49.194967 DLL_ASYNC_EN = 0
624 23:06:49.198291 ALL_SLAVE_EN = 1
625 23:06:49.198417 NEW_RANK_MODE = 1
626 23:06:49.201736 DLL_IDLE_MODE = 1
627 23:06:49.205013 LP45_APHY_COMB_EN = 1
628 23:06:49.208301 TX_ODT_DIS = 1
629 23:06:49.211717 NEW_8X_MODE = 1
630 23:06:49.215156 ===================================
631 23:06:49.218417 ===================================
632 23:06:49.218509 data_rate = 1600
633 23:06:49.221763 CKR = 1
634 23:06:49.225048 DQ_P2S_RATIO = 8
635 23:06:49.228214 ===================================
636 23:06:49.232283 CA_P2S_RATIO = 8
637 23:06:49.235078 DQ_CA_OPEN = 0
638 23:06:49.238205 DQ_SEMI_OPEN = 0
639 23:06:49.238353 CA_SEMI_OPEN = 0
640 23:06:49.241812 CA_FULL_RATE = 0
641 23:06:49.244984 DQ_CKDIV4_EN = 1
642 23:06:49.248461 CA_CKDIV4_EN = 1
643 23:06:49.251708 CA_PREDIV_EN = 0
644 23:06:49.251813 PH8_DLY = 0
645 23:06:49.255227 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
646 23:06:49.258921 DQ_AAMCK_DIV = 4
647 23:06:49.261862 CA_AAMCK_DIV = 4
648 23:06:49.265467 CA_ADMCK_DIV = 4
649 23:06:49.268739 DQ_TRACK_CA_EN = 0
650 23:06:49.268846 CA_PICK = 800
651 23:06:49.271922 CA_MCKIO = 800
652 23:06:49.275302 MCKIO_SEMI = 0
653 23:06:49.278536 PLL_FREQ = 3068
654 23:06:49.282370 DQ_UI_PI_RATIO = 32
655 23:06:49.285371 CA_UI_PI_RATIO = 0
656 23:06:49.288924 ===================================
657 23:06:49.292085 ===================================
658 23:06:49.292171 memory_type:LPDDR4
659 23:06:49.295311 GP_NUM : 10
660 23:06:49.298639 SRAM_EN : 1
661 23:06:49.298726 MD32_EN : 0
662 23:06:49.302201 ===================================
663 23:06:49.306054 [ANA_INIT] >>>>>>>>>>>>>>
664 23:06:49.309567 <<<<<< [CONFIGURE PHASE]: ANA_TX
665 23:06:49.313116 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
666 23:06:49.313237 ===================================
667 23:06:49.317160 data_rate = 1600,PCW = 0X7600
668 23:06:49.321048 ===================================
669 23:06:49.324864 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
670 23:06:49.328470 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
671 23:06:49.335449 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
672 23:06:49.339464 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
673 23:06:49.342881 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
674 23:06:49.346286 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
675 23:06:49.349379 [ANA_INIT] flow start
676 23:06:49.349466 [ANA_INIT] PLL >>>>>>>>
677 23:06:49.352959 [ANA_INIT] PLL <<<<<<<<
678 23:06:49.355922 [ANA_INIT] MIDPI >>>>>>>>
679 23:06:49.359465 [ANA_INIT] MIDPI <<<<<<<<
680 23:06:49.359562 [ANA_INIT] DLL >>>>>>>>
681 23:06:49.362942 [ANA_INIT] flow end
682 23:06:49.366701 ============ LP4 DIFF to SE enter ============
683 23:06:49.369523 ============ LP4 DIFF to SE exit ============
684 23:06:49.372950 [ANA_INIT] <<<<<<<<<<<<<
685 23:06:49.376319 [Flow] Enable top DCM control >>>>>
686 23:06:49.379472 [Flow] Enable top DCM control <<<<<
687 23:06:49.383039 Enable DLL master slave shuffle
688 23:06:49.386572 ==============================================================
689 23:06:49.389601 Gating Mode config
690 23:06:49.396129 ==============================================================
691 23:06:49.396217 Config description:
692 23:06:49.406482 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
693 23:06:49.413491 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
694 23:06:49.417337 SELPH_MODE 0: By rank 1: By Phase
695 23:06:49.424702 ==============================================================
696 23:06:49.428142 GAT_TRACK_EN = 1
697 23:06:49.428228 RX_GATING_MODE = 2
698 23:06:49.432354 RX_GATING_TRACK_MODE = 2
699 23:06:49.435720 SELPH_MODE = 1
700 23:06:49.439343 PICG_EARLY_EN = 1
701 23:06:49.443017 VALID_LAT_VALUE = 1
702 23:06:49.447023 ==============================================================
703 23:06:49.450283 Enter into Gating configuration >>>>
704 23:06:49.454134 Exit from Gating configuration <<<<
705 23:06:49.457472 Enter into DVFS_PRE_config >>>>>
706 23:06:49.468644 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
707 23:06:49.471881 Exit from DVFS_PRE_config <<<<<
708 23:06:49.475809 Enter into PICG configuration >>>>
709 23:06:49.475896 Exit from PICG configuration <<<<
710 23:06:49.479501 [RX_INPUT] configuration >>>>>
711 23:06:49.483405 [RX_INPUT] configuration <<<<<
712 23:06:49.486971 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
713 23:06:49.494642 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
714 23:06:49.502082 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
715 23:06:49.506024 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
716 23:06:49.513250 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
717 23:06:49.517077 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
718 23:06:49.520618 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
719 23:06:49.524361 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
720 23:06:49.532302 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
721 23:06:49.535738 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
722 23:06:49.539469 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
723 23:06:49.543781 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
724 23:06:49.547426 ===================================
725 23:06:49.547512 LPDDR4 DRAM CONFIGURATION
726 23:06:49.551000 ===================================
727 23:06:49.554818 EX_ROW_EN[0] = 0x0
728 23:06:49.554904 EX_ROW_EN[1] = 0x0
729 23:06:49.558249 LP4Y_EN = 0x0
730 23:06:49.558334 WORK_FSP = 0x0
731 23:06:49.561961 WL = 0x2
732 23:06:49.562047 RL = 0x2
733 23:06:49.565607 BL = 0x2
734 23:06:49.565692 RPST = 0x0
735 23:06:49.569276 RD_PRE = 0x0
736 23:06:49.569361 WR_PRE = 0x1
737 23:06:49.573458 WR_PST = 0x0
738 23:06:49.573547 DBI_WR = 0x0
739 23:06:49.577567 DBI_RD = 0x0
740 23:06:49.577652 OTF = 0x1
741 23:06:49.580957 ===================================
742 23:06:49.584442 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
743 23:06:49.588262 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
744 23:06:49.592220 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
745 23:06:49.595527 ===================================
746 23:06:49.599537 LPDDR4 DRAM CONFIGURATION
747 23:06:49.603022 ===================================
748 23:06:49.603108 EX_ROW_EN[0] = 0x10
749 23:06:49.607115 EX_ROW_EN[1] = 0x0
750 23:06:49.607200 LP4Y_EN = 0x0
751 23:06:49.610293 WORK_FSP = 0x0
752 23:06:49.610430 WL = 0x2
753 23:06:49.613717 RL = 0x2
754 23:06:49.613818 BL = 0x2
755 23:06:49.617541 RPST = 0x0
756 23:06:49.617626 RD_PRE = 0x0
757 23:06:49.621032 WR_PRE = 0x1
758 23:06:49.621118 WR_PST = 0x0
759 23:06:49.625040 DBI_WR = 0x0
760 23:06:49.625128 DBI_RD = 0x0
761 23:06:49.625195 OTF = 0x1
762 23:06:49.628329 ===================================
763 23:06:49.635484 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
764 23:06:49.640091 nWR fixed to 40
765 23:06:49.643538 [ModeRegInit_LP4] CH0 RK0
766 23:06:49.643642 [ModeRegInit_LP4] CH0 RK1
767 23:06:49.647061 [ModeRegInit_LP4] CH1 RK0
768 23:06:49.650711 [ModeRegInit_LP4] CH1 RK1
769 23:06:49.650832 match AC timing 13
770 23:06:49.654806 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
771 23:06:49.658637 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
772 23:06:49.662592 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
773 23:06:49.669560 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
774 23:06:49.673609 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
775 23:06:49.673705 [EMI DOE] emi_dcm 0
776 23:06:49.677656 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
777 23:06:49.681307 ==
778 23:06:49.681393 Dram Type= 6, Freq= 0, CH_0, rank 0
779 23:06:49.685010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
780 23:06:49.689053 ==
781 23:06:49.692037 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
782 23:06:49.699199 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
783 23:06:49.707357 [CA 0] Center 37 (7~68) winsize 62
784 23:06:49.711264 [CA 1] Center 38 (7~69) winsize 63
785 23:06:49.715058 [CA 2] Center 35 (5~66) winsize 62
786 23:06:49.718045 [CA 3] Center 35 (5~66) winsize 62
787 23:06:49.721777 [CA 4] Center 34 (4~65) winsize 62
788 23:06:49.725021 [CA 5] Center 33 (3~64) winsize 62
789 23:06:49.725107
790 23:06:49.728244 [CmdBusTrainingLP45] Vref(ca) range 1: 32
791 23:06:49.728330
792 23:06:49.731752 [CATrainingPosCal] consider 1 rank data
793 23:06:49.734876 u2DelayCellTimex100 = 270/100 ps
794 23:06:49.738347 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
795 23:06:49.741491 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
796 23:06:49.744945 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
797 23:06:49.748491 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
798 23:06:49.751927 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
799 23:06:49.758253 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
800 23:06:49.758367
801 23:06:49.761864 CA PerBit enable=1, Macro0, CA PI delay=33
802 23:06:49.761949
803 23:06:49.765272 [CBTSetCACLKResult] CA Dly = 33
804 23:06:49.765357 CS Dly: 5 (0~36)
805 23:06:49.765425 ==
806 23:06:49.768515 Dram Type= 6, Freq= 0, CH_0, rank 1
807 23:06:49.771741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
808 23:06:49.771852 ==
809 23:06:49.778345 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
810 23:06:49.784878 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
811 23:06:49.793893 [CA 0] Center 38 (7~69) winsize 63
812 23:06:49.796883 [CA 1] Center 38 (7~69) winsize 63
813 23:06:49.800398 [CA 2] Center 35 (5~66) winsize 62
814 23:06:49.803603 [CA 3] Center 35 (5~66) winsize 62
815 23:06:49.807325 [CA 4] Center 35 (4~66) winsize 63
816 23:06:49.810351 [CA 5] Center 34 (4~65) winsize 62
817 23:06:49.810486
818 23:06:49.814163 [CmdBusTrainingLP45] Vref(ca) range 1: 32
819 23:06:49.814249
820 23:06:49.817222 [CATrainingPosCal] consider 2 rank data
821 23:06:49.820837 u2DelayCellTimex100 = 270/100 ps
822 23:06:49.823824 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
823 23:06:49.827422 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
824 23:06:49.830723 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
825 23:06:49.837310 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
826 23:06:49.840345 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
827 23:06:49.844136 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
828 23:06:49.844214
829 23:06:49.847265 CA PerBit enable=1, Macro0, CA PI delay=34
830 23:06:49.847341
831 23:06:49.850371 [CBTSetCACLKResult] CA Dly = 34
832 23:06:49.850488 CS Dly: 6 (0~38)
833 23:06:49.850553
834 23:06:49.854112 ----->DramcWriteLeveling(PI) begin...
835 23:06:49.854187 ==
836 23:06:49.857185 Dram Type= 6, Freq= 0, CH_0, rank 0
837 23:06:49.864335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
838 23:06:49.864439 ==
839 23:06:49.867628 Write leveling (Byte 0): 32 => 32
840 23:06:49.870497 Write leveling (Byte 1): 31 => 31
841 23:06:49.870597 DramcWriteLeveling(PI) end<-----
842 23:06:49.874066
843 23:06:49.874139 ==
844 23:06:49.877595 Dram Type= 6, Freq= 0, CH_0, rank 0
845 23:06:49.880581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
846 23:06:49.880656 ==
847 23:06:49.884675 [Gating] SW mode calibration
848 23:06:49.891948 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
849 23:06:49.895460 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
850 23:06:49.898931 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
851 23:06:49.902172 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
852 23:06:49.908818 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
853 23:06:49.912432 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 23:06:49.916086 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 23:06:49.923013 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 23:06:49.926075 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 23:06:49.929622 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 23:06:49.936164 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 23:06:49.939677 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 23:06:49.943195 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 23:06:49.946752 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 23:06:49.953018 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 23:06:49.956538 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 23:06:49.959855 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 23:06:49.966694 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 23:06:49.969958 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 23:06:49.973556 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
868 23:06:49.979828 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
869 23:06:49.983447 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 23:06:49.986389 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 23:06:49.993102 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 23:06:49.996454 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 23:06:49.999960 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 23:06:50.006609 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 23:06:50.009795 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 23:06:50.013284 0 9 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
877 23:06:50.019980 0 9 12 | B1->B0 | 2e2e 3434 | 1 1 | (0 0) (1 1)
878 23:06:50.023048 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
879 23:06:50.026584 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
880 23:06:50.029854 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
881 23:06:50.036641 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 23:06:50.040194 0 10 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
883 23:06:50.043262 0 10 4 | B1->B0 | 3434 3030 | 1 1 | (1 1) (0 1)
884 23:06:50.050531 0 10 8 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
885 23:06:50.053502 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
886 23:06:50.057100 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
887 23:06:50.063428 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
888 23:06:50.066624 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
889 23:06:50.070031 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 23:06:50.073800 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 23:06:50.080382 0 11 4 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
892 23:06:50.083664 0 11 8 | B1->B0 | 2e2e 4646 | 0 0 | (0 0) (0 0)
893 23:06:50.086780 0 11 12 | B1->B0 | 3d3d 4646 | 1 0 | (1 1) (0 0)
894 23:06:50.093471 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
895 23:06:50.096583 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
896 23:06:50.100299 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
897 23:06:50.106662 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 23:06:50.109985 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 23:06:50.113579 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
900 23:06:50.120136 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
901 23:06:50.123657 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 23:06:50.127099 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 23:06:50.133634 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 23:06:50.137156 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 23:06:50.140106 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 23:06:50.146891 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 23:06:50.150212 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 23:06:50.153648 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 23:06:50.160082 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 23:06:50.163569 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 23:06:50.166980 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 23:06:50.170065 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 23:06:50.176841 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 23:06:50.180134 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 23:06:50.183660 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
916 23:06:50.190506 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
917 23:06:50.193437 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
918 23:06:50.196712 Total UI for P1: 0, mck2ui 16
919 23:06:50.200079 best dqsien dly found for B0: ( 0, 14, 6)
920 23:06:50.203707 Total UI for P1: 0, mck2ui 16
921 23:06:50.206932 best dqsien dly found for B1: ( 0, 14, 6)
922 23:06:50.210278 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
923 23:06:50.213460 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
924 23:06:50.213559
925 23:06:50.216874 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
926 23:06:50.220190 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
927 23:06:50.223466 [Gating] SW calibration Done
928 23:06:50.223540 ==
929 23:06:50.227199 Dram Type= 6, Freq= 0, CH_0, rank 0
930 23:06:50.230422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
931 23:06:50.233608 ==
932 23:06:50.233748 RX Vref Scan: 0
933 23:06:50.233863
934 23:06:50.236971 RX Vref 0 -> 0, step: 1
935 23:06:50.237098
936 23:06:50.240559 RX Delay -130 -> 252, step: 16
937 23:06:50.243683 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
938 23:06:50.247304 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
939 23:06:50.250498 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
940 23:06:50.253951 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
941 23:06:50.256979 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
942 23:06:50.263807 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
943 23:06:50.267314 iDelay=222, Bit 6, Center 109 (-2 ~ 221) 224
944 23:06:50.270279 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
945 23:06:50.273763 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
946 23:06:50.277481 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
947 23:06:50.283812 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
948 23:06:50.287104 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
949 23:06:50.290460 iDelay=222, Bit 12, Center 85 (-18 ~ 189) 208
950 23:06:50.294136 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
951 23:06:50.297175 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
952 23:06:50.303943 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
953 23:06:50.304041 ==
954 23:06:50.307537 Dram Type= 6, Freq= 0, CH_0, rank 0
955 23:06:50.310550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
956 23:06:50.310624 ==
957 23:06:50.310687 DQS Delay:
958 23:06:50.314067 DQS0 = 0, DQS1 = 0
959 23:06:50.314134 DQM Delay:
960 23:06:50.317091 DQM0 = 94, DQM1 = 81
961 23:06:50.317159 DQ Delay:
962 23:06:50.320651 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
963 23:06:50.323850 DQ4 =93, DQ5 =77, DQ6 =109, DQ7 =101
964 23:06:50.327325 DQ8 =77, DQ9 =61, DQ10 =85, DQ11 =77
965 23:06:50.330487 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
966 23:06:50.330562
967 23:06:50.330627
968 23:06:50.330688 ==
969 23:06:50.334199 Dram Type= 6, Freq= 0, CH_0, rank 0
970 23:06:50.337359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
971 23:06:50.337460 ==
972 23:06:50.340625
973 23:06:50.340720
974 23:06:50.340809 TX Vref Scan disable
975 23:06:50.344209 == TX Byte 0 ==
976 23:06:50.347586 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
977 23:06:50.350685 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
978 23:06:50.354220 == TX Byte 1 ==
979 23:06:50.357348 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
980 23:06:50.360640 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
981 23:06:50.360719 ==
982 23:06:50.364407 Dram Type= 6, Freq= 0, CH_0, rank 0
983 23:06:50.370824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
984 23:06:50.370923 ==
985 23:06:50.382598 TX Vref=22, minBit 8, minWin=26, winSum=437
986 23:06:50.385911 TX Vref=24, minBit 7, minWin=27, winSum=441
987 23:06:50.389164 TX Vref=26, minBit 8, minWin=27, winSum=446
988 23:06:50.392579 TX Vref=28, minBit 8, minWin=27, winSum=451
989 23:06:50.395831 TX Vref=30, minBit 9, minWin=27, winSum=453
990 23:06:50.399442 TX Vref=32, minBit 10, minWin=27, winSum=454
991 23:06:50.405918 [TxChooseVref] Worse bit 10, Min win 27, Win sum 454, Final Vref 32
992 23:06:50.406023
993 23:06:50.409081 Final TX Range 1 Vref 32
994 23:06:50.409180
995 23:06:50.409273 ==
996 23:06:50.412611 Dram Type= 6, Freq= 0, CH_0, rank 0
997 23:06:50.415914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
998 23:06:50.416028 ==
999 23:06:50.416124
1000 23:06:50.419535
1001 23:06:50.419632 TX Vref Scan disable
1002 23:06:50.422492 == TX Byte 0 ==
1003 23:06:50.425702 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1004 23:06:50.429096 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1005 23:06:50.432744 == TX Byte 1 ==
1006 23:06:50.436025 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1007 23:06:50.439285 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1008 23:06:50.442603
1009 23:06:50.442678 [DATLAT]
1010 23:06:50.442740 Freq=800, CH0 RK0
1011 23:06:50.442802
1012 23:06:50.446112 DATLAT Default: 0xa
1013 23:06:50.446211 0, 0xFFFF, sum = 0
1014 23:06:50.449368 1, 0xFFFF, sum = 0
1015 23:06:50.449472 2, 0xFFFF, sum = 0
1016 23:06:50.452619 3, 0xFFFF, sum = 0
1017 23:06:50.452724 4, 0xFFFF, sum = 0
1018 23:06:50.455923 5, 0xFFFF, sum = 0
1019 23:06:50.456021 6, 0xFFFF, sum = 0
1020 23:06:50.459552 7, 0xFFFF, sum = 0
1021 23:06:50.462787 8, 0xFFFF, sum = 0
1022 23:06:50.462857 9, 0x0, sum = 1
1023 23:06:50.462922 10, 0x0, sum = 2
1024 23:06:50.466512 11, 0x0, sum = 3
1025 23:06:50.466586 12, 0x0, sum = 4
1026 23:06:50.469449 best_step = 10
1027 23:06:50.469542
1028 23:06:50.469630 ==
1029 23:06:50.472552 Dram Type= 6, Freq= 0, CH_0, rank 0
1030 23:06:50.475935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1031 23:06:50.476032 ==
1032 23:06:50.479501 RX Vref Scan: 1
1033 23:06:50.479571
1034 23:06:50.479629 Set Vref Range= 32 -> 127
1035 23:06:50.479686
1036 23:06:50.482741 RX Vref 32 -> 127, step: 1
1037 23:06:50.482808
1038 23:06:50.486056 RX Delay -95 -> 252, step: 8
1039 23:06:50.486155
1040 23:06:50.489366 Set Vref, RX VrefLevel [Byte0]: 32
1041 23:06:50.492758 [Byte1]: 32
1042 23:06:50.492854
1043 23:06:50.496732 Set Vref, RX VrefLevel [Byte0]: 33
1044 23:06:50.499523 [Byte1]: 33
1045 23:06:50.503501
1046 23:06:50.503595 Set Vref, RX VrefLevel [Byte0]: 34
1047 23:06:50.506310 [Byte1]: 34
1048 23:06:50.510746
1049 23:06:50.510817 Set Vref, RX VrefLevel [Byte0]: 35
1050 23:06:50.514181 [Byte1]: 35
1051 23:06:50.518014
1052 23:06:50.518110 Set Vref, RX VrefLevel [Byte0]: 36
1053 23:06:50.521276 [Byte1]: 36
1054 23:06:50.525609
1055 23:06:50.525685 Set Vref, RX VrefLevel [Byte0]: 37
1056 23:06:50.528785 [Byte1]: 37
1057 23:06:50.533469
1058 23:06:50.533542 Set Vref, RX VrefLevel [Byte0]: 38
1059 23:06:50.537021 [Byte1]: 38
1060 23:06:50.540664
1061 23:06:50.540762 Set Vref, RX VrefLevel [Byte0]: 39
1062 23:06:50.544115 [Byte1]: 39
1063 23:06:50.548574
1064 23:06:50.548671 Set Vref, RX VrefLevel [Byte0]: 40
1065 23:06:50.551759 [Byte1]: 40
1066 23:06:50.556725
1067 23:06:50.556824 Set Vref, RX VrefLevel [Byte0]: 41
1068 23:06:50.560053 [Byte1]: 41
1069 23:06:50.564058
1070 23:06:50.564156 Set Vref, RX VrefLevel [Byte0]: 42
1071 23:06:50.567432 [Byte1]: 42
1072 23:06:50.571746
1073 23:06:50.571834 Set Vref, RX VrefLevel [Byte0]: 43
1074 23:06:50.575064 [Byte1]: 43
1075 23:06:50.578910
1076 23:06:50.579013 Set Vref, RX VrefLevel [Byte0]: 44
1077 23:06:50.582219 [Byte1]: 44
1078 23:06:50.586855
1079 23:06:50.586972 Set Vref, RX VrefLevel [Byte0]: 45
1080 23:06:50.590320 [Byte1]: 45
1081 23:06:50.594423
1082 23:06:50.594511 Set Vref, RX VrefLevel [Byte0]: 46
1083 23:06:50.597435 [Byte1]: 46
1084 23:06:50.601808
1085 23:06:50.601906 Set Vref, RX VrefLevel [Byte0]: 47
1086 23:06:50.605099 [Byte1]: 47
1087 23:06:50.609389
1088 23:06:50.609486 Set Vref, RX VrefLevel [Byte0]: 48
1089 23:06:50.612588 [Byte1]: 48
1090 23:06:50.617286
1091 23:06:50.617387 Set Vref, RX VrefLevel [Byte0]: 49
1092 23:06:50.620241 [Byte1]: 49
1093 23:06:50.624675
1094 23:06:50.624787 Set Vref, RX VrefLevel [Byte0]: 50
1095 23:06:50.627826 [Byte1]: 50
1096 23:06:50.632076
1097 23:06:50.632179 Set Vref, RX VrefLevel [Byte0]: 51
1098 23:06:50.635596 [Byte1]: 51
1099 23:06:50.639433
1100 23:06:50.639532 Set Vref, RX VrefLevel [Byte0]: 52
1101 23:06:50.643103 [Byte1]: 52
1102 23:06:50.647716
1103 23:06:50.647792 Set Vref, RX VrefLevel [Byte0]: 53
1104 23:06:50.650957 [Byte1]: 53
1105 23:06:50.654914
1106 23:06:50.654987 Set Vref, RX VrefLevel [Byte0]: 54
1107 23:06:50.658283 [Byte1]: 54
1108 23:06:50.662347
1109 23:06:50.662466 Set Vref, RX VrefLevel [Byte0]: 55
1110 23:06:50.665648 [Byte1]: 55
1111 23:06:50.669788
1112 23:06:50.669899 Set Vref, RX VrefLevel [Byte0]: 56
1113 23:06:50.673458 [Byte1]: 56
1114 23:06:50.677654
1115 23:06:50.677734 Set Vref, RX VrefLevel [Byte0]: 57
1116 23:06:50.681097 [Byte1]: 57
1117 23:06:50.685185
1118 23:06:50.685290 Set Vref, RX VrefLevel [Byte0]: 58
1119 23:06:50.688488 [Byte1]: 58
1120 23:06:50.692806
1121 23:06:50.692911 Set Vref, RX VrefLevel [Byte0]: 59
1122 23:06:50.696071 [Byte1]: 59
1123 23:06:50.700558
1124 23:06:50.700656 Set Vref, RX VrefLevel [Byte0]: 60
1125 23:06:50.703758 [Byte1]: 60
1126 23:06:50.707892
1127 23:06:50.707991 Set Vref, RX VrefLevel [Byte0]: 61
1128 23:06:50.711482 [Byte1]: 61
1129 23:06:50.715535
1130 23:06:50.715610 Set Vref, RX VrefLevel [Byte0]: 62
1131 23:06:50.719082 [Byte1]: 62
1132 23:06:50.723170
1133 23:06:50.723244 Set Vref, RX VrefLevel [Byte0]: 63
1134 23:06:50.726558 [Byte1]: 63
1135 23:06:50.731115
1136 23:06:50.731187 Set Vref, RX VrefLevel [Byte0]: 64
1137 23:06:50.734075 [Byte1]: 64
1138 23:06:50.738413
1139 23:06:50.738527 Set Vref, RX VrefLevel [Byte0]: 65
1140 23:06:50.741643 [Byte1]: 65
1141 23:06:50.746119
1142 23:06:50.746230 Set Vref, RX VrefLevel [Byte0]: 66
1143 23:06:50.749332 [Byte1]: 66
1144 23:06:50.753618
1145 23:06:50.753720 Set Vref, RX VrefLevel [Byte0]: 67
1146 23:06:50.757164 [Byte1]: 67
1147 23:06:50.761115
1148 23:06:50.761214 Set Vref, RX VrefLevel [Byte0]: 68
1149 23:06:50.764485 [Byte1]: 68
1150 23:06:50.769253
1151 23:06:50.769351 Set Vref, RX VrefLevel [Byte0]: 69
1152 23:06:50.772074 [Byte1]: 69
1153 23:06:50.776479
1154 23:06:50.776578 Set Vref, RX VrefLevel [Byte0]: 70
1155 23:06:50.779909 [Byte1]: 70
1156 23:06:50.783920
1157 23:06:50.783991 Set Vref, RX VrefLevel [Byte0]: 71
1158 23:06:50.787315 [Byte1]: 71
1159 23:06:50.791780
1160 23:06:50.791860 Set Vref, RX VrefLevel [Byte0]: 72
1161 23:06:50.795162 [Byte1]: 72
1162 23:06:50.799159
1163 23:06:50.799230 Set Vref, RX VrefLevel [Byte0]: 73
1164 23:06:50.802373 [Byte1]: 73
1165 23:06:50.806743
1166 23:06:50.806815 Set Vref, RX VrefLevel [Byte0]: 74
1167 23:06:50.810286 [Byte1]: 74
1168 23:06:50.814279
1169 23:06:50.814399 Set Vref, RX VrefLevel [Byte0]: 75
1170 23:06:50.817834 [Byte1]: 75
1171 23:06:50.822366
1172 23:06:50.822496 Set Vref, RX VrefLevel [Byte0]: 76
1173 23:06:50.825303 [Byte1]: 76
1174 23:06:50.830200
1175 23:06:50.830297 Set Vref, RX VrefLevel [Byte0]: 77
1176 23:06:50.832999 [Byte1]: 77
1177 23:06:50.837270
1178 23:06:50.837372 Set Vref, RX VrefLevel [Byte0]: 78
1179 23:06:50.840818 [Byte1]: 78
1180 23:06:50.844627
1181 23:06:50.844723 Set Vref, RX VrefLevel [Byte0]: 79
1182 23:06:50.848036 [Byte1]: 79
1183 23:06:50.852439
1184 23:06:50.852538 Final RX Vref Byte 0 = 61 to rank0
1185 23:06:50.855731 Final RX Vref Byte 1 = 53 to rank0
1186 23:06:50.859203 Final RX Vref Byte 0 = 61 to rank1
1187 23:06:50.862670 Final RX Vref Byte 1 = 53 to rank1==
1188 23:06:50.865907 Dram Type= 6, Freq= 0, CH_0, rank 0
1189 23:06:50.869357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1190 23:06:50.872412 ==
1191 23:06:50.872490 DQS Delay:
1192 23:06:50.872581 DQS0 = 0, DQS1 = 0
1193 23:06:50.875742 DQM Delay:
1194 23:06:50.875842 DQM0 = 92, DQM1 = 81
1195 23:06:50.879543 DQ Delay:
1196 23:06:50.882265 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1197 23:06:50.882360 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1198 23:06:50.885701 DQ8 =76, DQ9 =68, DQ10 =80, DQ11 =76
1199 23:06:50.892581 DQ12 =88, DQ13 =84, DQ14 =92, DQ15 =88
1200 23:06:50.892682
1201 23:06:50.892775
1202 23:06:50.898938 [DQSOSCAuto] RK0, (LSB)MR18= 0x3d38, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
1203 23:06:50.902790 CH0 RK0: MR19=606, MR18=3D38
1204 23:06:50.909356 CH0_RK0: MR19=0x606, MR18=0x3D38, DQSOSC=394, MR23=63, INC=95, DEC=63
1205 23:06:50.909453
1206 23:06:50.912629 ----->DramcWriteLeveling(PI) begin...
1207 23:06:50.912725 ==
1208 23:06:50.915734 Dram Type= 6, Freq= 0, CH_0, rank 1
1209 23:06:50.918959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1210 23:06:50.919035 ==
1211 23:06:50.922745 Write leveling (Byte 0): 31 => 31
1212 23:06:50.925702 Write leveling (Byte 1): 30 => 30
1213 23:06:50.928910 DramcWriteLeveling(PI) end<-----
1214 23:06:50.929005
1215 23:06:50.929092 ==
1216 23:06:50.932458 Dram Type= 6, Freq= 0, CH_0, rank 1
1217 23:06:50.935610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1218 23:06:50.935680 ==
1219 23:06:50.939220 [Gating] SW mode calibration
1220 23:06:50.945808 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1221 23:06:50.952685 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1222 23:06:50.955708 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1223 23:06:50.999980 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1224 23:06:51.000445 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 23:06:51.001027 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 23:06:51.001125 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 23:06:51.001397 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 23:06:51.001778 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 23:06:51.002187 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 23:06:51.002416 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 23:06:51.002506 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 23:06:51.002807 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 23:06:51.044084 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 23:06:51.044385 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 23:06:51.044739 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 23:06:51.044844 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 23:06:51.045101 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 23:06:51.045174 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 23:06:51.045766 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1240 23:06:51.046576 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 23:06:51.046661 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 23:06:51.046914 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 23:06:51.071312 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 23:06:51.071589 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 23:06:51.071725 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 23:06:51.071793 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 23:06:51.072180 0 9 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
1248 23:06:51.072454 0 9 8 | B1->B0 | 2a2a 3231 | 1 1 | (1 1) (0 0)
1249 23:06:51.075396 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1250 23:06:51.078581 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1251 23:06:51.081774 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1252 23:06:51.088574 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1253 23:06:51.092016 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1254 23:06:51.095528 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1255 23:06:51.101993 0 10 4 | B1->B0 | 3333 2f2f | 1 0 | (1 1) (0 0)
1256 23:06:51.105433 0 10 8 | B1->B0 | 2d2d 2323 | 1 0 | (0 0) (0 0)
1257 23:06:51.109078 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1258 23:06:51.115628 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1259 23:06:51.118762 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1260 23:06:51.122152 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1261 23:06:51.128594 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1262 23:06:51.132519 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1263 23:06:51.135773 0 11 4 | B1->B0 | 2424 2f2f | 0 0 | (0 0) (0 0)
1264 23:06:51.139431 0 11 8 | B1->B0 | 3737 4141 | 0 1 | (1 1) (0 0)
1265 23:06:51.143474 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1266 23:06:51.151470 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1267 23:06:51.153989 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1268 23:06:51.157461 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1269 23:06:51.160896 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1270 23:06:51.167933 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1271 23:06:51.171366 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1272 23:06:51.174817 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 23:06:51.181660 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 23:06:51.184640 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 23:06:51.187869 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 23:06:51.194789 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 23:06:51.197997 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 23:06:51.201238 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 23:06:51.204722 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 23:06:51.211297 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 23:06:51.214691 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 23:06:51.217994 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 23:06:51.224743 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 23:06:51.228489 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1285 23:06:51.231596 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1286 23:06:51.238090 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1287 23:06:51.241396 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1288 23:06:51.245040 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1289 23:06:51.248149 Total UI for P1: 0, mck2ui 16
1290 23:06:51.251675 best dqsien dly found for B1: ( 0, 14, 6)
1291 23:06:51.258261 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1292 23:06:51.258365 Total UI for P1: 0, mck2ui 16
1293 23:06:51.261749 best dqsien dly found for B0: ( 0, 14, 6)
1294 23:06:51.268227 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1295 23:06:51.271807 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1296 23:06:51.271879
1297 23:06:51.275166 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1298 23:06:51.278596 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1299 23:06:51.281693 [Gating] SW calibration Done
1300 23:06:51.281767 ==
1301 23:06:51.284873 Dram Type= 6, Freq= 0, CH_0, rank 1
1302 23:06:51.288367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1303 23:06:51.288439 ==
1304 23:06:51.288505 RX Vref Scan: 0
1305 23:06:51.288563
1306 23:06:51.291660 RX Vref 0 -> 0, step: 1
1307 23:06:51.291740
1308 23:06:51.295161 RX Delay -130 -> 252, step: 16
1309 23:06:51.298606 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1310 23:06:51.301714 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
1311 23:06:51.308253 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
1312 23:06:51.311964 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1313 23:06:51.315204 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1314 23:06:51.319020 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1315 23:06:51.321734 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1316 23:06:51.328661 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1317 23:06:51.331797 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
1318 23:06:51.334948 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1319 23:06:51.338260 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1320 23:06:51.341581 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1321 23:06:51.348656 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1322 23:06:51.352238 iDelay=206, Bit 13, Center 85 (-18 ~ 189) 208
1323 23:06:51.354895 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1324 23:06:51.358880 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1325 23:06:51.358953 ==
1326 23:06:51.362226 Dram Type= 6, Freq= 0, CH_0, rank 1
1327 23:06:51.365269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1328 23:06:51.368721 ==
1329 23:06:51.368797 DQS Delay:
1330 23:06:51.368859 DQS0 = 0, DQS1 = 0
1331 23:06:51.372024 DQM Delay:
1332 23:06:51.372098 DQM0 = 87, DQM1 = 82
1333 23:06:51.375204 DQ Delay:
1334 23:06:51.375283 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =77
1335 23:06:51.378548 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1336 23:06:51.381853 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
1337 23:06:51.385318 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =93
1338 23:06:51.385397
1339 23:06:51.385468
1340 23:06:51.389615 ==
1341 23:06:51.392122 Dram Type= 6, Freq= 0, CH_0, rank 1
1342 23:06:51.395451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1343 23:06:51.395531 ==
1344 23:06:51.395596
1345 23:06:51.395657
1346 23:06:51.398810 TX Vref Scan disable
1347 23:06:51.398887 == TX Byte 0 ==
1348 23:06:51.405449 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1349 23:06:51.408854 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1350 23:06:51.408955 == TX Byte 1 ==
1351 23:06:51.415653 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1352 23:06:51.418933 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1353 23:06:51.419018 ==
1354 23:06:51.422108 Dram Type= 6, Freq= 0, CH_0, rank 1
1355 23:06:51.425432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1356 23:06:51.425516 ==
1357 23:06:51.439086 TX Vref=22, minBit 3, minWin=27, winSum=446
1358 23:06:51.442103 TX Vref=24, minBit 8, minWin=27, winSum=445
1359 23:06:51.445555 TX Vref=26, minBit 8, minWin=27, winSum=452
1360 23:06:51.448836 TX Vref=28, minBit 8, minWin=27, winSum=453
1361 23:06:51.452410 TX Vref=30, minBit 8, minWin=27, winSum=454
1362 23:06:51.455663 TX Vref=32, minBit 8, minWin=27, winSum=454
1363 23:06:51.462016 [TxChooseVref] Worse bit 8, Min win 27, Win sum 454, Final Vref 30
1364 23:06:51.462125
1365 23:06:51.465453 Final TX Range 1 Vref 30
1366 23:06:51.465552
1367 23:06:51.465642 ==
1368 23:06:51.469002 Dram Type= 6, Freq= 0, CH_0, rank 1
1369 23:06:51.472429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1370 23:06:51.472545 ==
1371 23:06:51.472610
1372 23:06:51.472670
1373 23:06:51.475367 TX Vref Scan disable
1374 23:06:51.479068 == TX Byte 0 ==
1375 23:06:51.482533 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1376 23:06:51.485883 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1377 23:06:51.489032 == TX Byte 1 ==
1378 23:06:51.492482 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1379 23:06:51.496047 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1380 23:06:51.496138
1381 23:06:51.499387 [DATLAT]
1382 23:06:51.499461 Freq=800, CH0 RK1
1383 23:06:51.499524
1384 23:06:51.502379 DATLAT Default: 0xa
1385 23:06:51.502459 0, 0xFFFF, sum = 0
1386 23:06:51.505747 1, 0xFFFF, sum = 0
1387 23:06:51.505823 2, 0xFFFF, sum = 0
1388 23:06:51.508981 3, 0xFFFF, sum = 0
1389 23:06:51.509065 4, 0xFFFF, sum = 0
1390 23:06:51.512501 5, 0xFFFF, sum = 0
1391 23:06:51.512581 6, 0xFFFF, sum = 0
1392 23:06:51.515767 7, 0xFFFF, sum = 0
1393 23:06:51.515856 8, 0xFFFF, sum = 0
1394 23:06:51.519017 9, 0x0, sum = 1
1395 23:06:51.519099 10, 0x0, sum = 2
1396 23:06:51.522761 11, 0x0, sum = 3
1397 23:06:51.522840 12, 0x0, sum = 4
1398 23:06:51.525782 best_step = 10
1399 23:06:51.525856
1400 23:06:51.525918 ==
1401 23:06:51.529128 Dram Type= 6, Freq= 0, CH_0, rank 1
1402 23:06:51.532403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1403 23:06:51.532477 ==
1404 23:06:51.535937 RX Vref Scan: 0
1405 23:06:51.536010
1406 23:06:51.536071 RX Vref 0 -> 0, step: 1
1407 23:06:51.536128
1408 23:06:51.539075 RX Delay -95 -> 252, step: 8
1409 23:06:51.546035 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1410 23:06:51.549454 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1411 23:06:51.552405 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1412 23:06:51.556194 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
1413 23:06:51.559235 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1414 23:06:51.562458 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1415 23:06:51.569855 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1416 23:06:51.572533 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1417 23:06:51.576229 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1418 23:06:51.579384 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1419 23:06:51.582724 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1420 23:06:51.589330 iDelay=209, Bit 11, Center 80 (-23 ~ 184) 208
1421 23:06:51.593037 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1422 23:06:51.595960 iDelay=209, Bit 13, Center 88 (-15 ~ 192) 208
1423 23:06:51.599475 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1424 23:06:51.602707 iDelay=209, Bit 15, Center 88 (-15 ~ 192) 208
1425 23:06:51.606250 ==
1426 23:06:51.609349 Dram Type= 6, Freq= 0, CH_0, rank 1
1427 23:06:51.612814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1428 23:06:51.612927 ==
1429 23:06:51.613022 DQS Delay:
1430 23:06:51.615823 DQS0 = 0, DQS1 = 0
1431 23:06:51.615910 DQM Delay:
1432 23:06:51.619521 DQM0 = 91, DQM1 = 82
1433 23:06:51.619631 DQ Delay:
1434 23:06:51.623084 DQ0 =88, DQ1 =92, DQ2 =88, DQ3 =88
1435 23:06:51.626473 DQ4 =92, DQ5 =84, DQ6 =100, DQ7 =100
1436 23:06:51.629356 DQ8 =76, DQ9 =68, DQ10 =84, DQ11 =80
1437 23:06:51.632698 DQ12 =84, DQ13 =88, DQ14 =92, DQ15 =88
1438 23:06:51.632839
1439 23:06:51.632934
1440 23:06:51.639593 [DQSOSCAuto] RK1, (LSB)MR18= 0x421d, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 393 ps
1441 23:06:51.643136 CH0 RK1: MR19=606, MR18=421D
1442 23:06:51.649758 CH0_RK1: MR19=0x606, MR18=0x421D, DQSOSC=393, MR23=63, INC=95, DEC=63
1443 23:06:51.653050 [RxdqsGatingPostProcess] freq 800
1444 23:06:51.656795 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1445 23:06:51.659598 Pre-setting of DQS Precalculation
1446 23:06:51.666489 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1447 23:06:51.666573 ==
1448 23:06:51.669741 Dram Type= 6, Freq= 0, CH_1, rank 0
1449 23:06:51.672847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1450 23:06:51.672933 ==
1451 23:06:51.679547 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1452 23:06:51.686493 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1453 23:06:51.693830 [CA 0] Center 36 (6~67) winsize 62
1454 23:06:51.697891 [CA 1] Center 36 (6~67) winsize 62
1455 23:06:51.700654 [CA 2] Center 34 (4~65) winsize 62
1456 23:06:51.703916 [CA 3] Center 34 (3~65) winsize 63
1457 23:06:51.707258 [CA 4] Center 34 (4~65) winsize 62
1458 23:06:51.710523 [CA 5] Center 33 (3~64) winsize 62
1459 23:06:51.710603
1460 23:06:51.714215 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1461 23:06:51.714292
1462 23:06:51.717109 [CATrainingPosCal] consider 1 rank data
1463 23:06:51.720679 u2DelayCellTimex100 = 270/100 ps
1464 23:06:51.723832 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1465 23:06:51.727672 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1466 23:06:51.734104 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1467 23:06:51.737413 CA3 delay=34 (3~65),Diff = 1 PI (7 cell)
1468 23:06:51.740592 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1469 23:06:51.744124 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1470 23:06:51.744209
1471 23:06:51.747680 CA PerBit enable=1, Macro0, CA PI delay=33
1472 23:06:51.747789
1473 23:06:51.750950 [CBTSetCACLKResult] CA Dly = 33
1474 23:06:51.751027 CS Dly: 5 (0~36)
1475 23:06:51.751091 ==
1476 23:06:51.753867 Dram Type= 6, Freq= 0, CH_1, rank 1
1477 23:06:51.760656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1478 23:06:51.760762 ==
1479 23:06:51.763953 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1480 23:06:51.770506 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1481 23:06:51.779858 [CA 0] Center 36 (6~67) winsize 62
1482 23:06:51.783557 [CA 1] Center 37 (6~68) winsize 63
1483 23:06:51.786936 [CA 2] Center 35 (4~66) winsize 63
1484 23:06:51.790106 [CA 3] Center 34 (4~65) winsize 62
1485 23:06:51.793203 [CA 4] Center 34 (4~65) winsize 62
1486 23:06:51.797233 [CA 5] Center 34 (4~64) winsize 61
1487 23:06:51.797336
1488 23:06:51.800107 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1489 23:06:51.800210
1490 23:06:51.804008 [CATrainingPosCal] consider 2 rank data
1491 23:06:51.807397 u2DelayCellTimex100 = 270/100 ps
1492 23:06:51.811215 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1493 23:06:51.815107 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1494 23:06:51.818632 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1495 23:06:51.822270 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1496 23:06:51.826068 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1497 23:06:51.829758 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1498 23:06:51.829875
1499 23:06:51.833479 CA PerBit enable=1, Macro0, CA PI delay=34
1500 23:06:51.833582
1501 23:06:51.837294 [CBTSetCACLKResult] CA Dly = 34
1502 23:06:51.837400 CS Dly: 6 (0~38)
1503 23:06:51.837499
1504 23:06:51.840472 ----->DramcWriteLeveling(PI) begin...
1505 23:06:51.840578 ==
1506 23:06:51.843959 Dram Type= 6, Freq= 0, CH_1, rank 0
1507 23:06:51.850805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1508 23:06:51.850922 ==
1509 23:06:51.853893 Write leveling (Byte 0): 25 => 25
1510 23:06:51.853999 Write leveling (Byte 1): 30 => 30
1511 23:06:51.857523 DramcWriteLeveling(PI) end<-----
1512 23:06:51.857614
1513 23:06:51.857707 ==
1514 23:06:51.860560 Dram Type= 6, Freq= 0, CH_1, rank 0
1515 23:06:51.867236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1516 23:06:51.867310 ==
1517 23:06:51.870860 [Gating] SW mode calibration
1518 23:06:51.877539 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1519 23:06:51.880822 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1520 23:06:51.884568 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1521 23:06:51.891009 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1522 23:06:51.894169 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 23:06:51.897265 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 23:06:51.904573 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 23:06:51.907834 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 23:06:51.911185 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 23:06:51.917596 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 23:06:51.920769 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 23:06:51.924354 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 23:06:51.930922 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 23:06:51.934306 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 23:06:51.937496 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 23:06:51.945068 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 23:06:51.948183 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 23:06:51.951529 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 23:06:51.954289 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1537 23:06:51.961570 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1538 23:06:51.964480 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1539 23:06:51.967737 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 23:06:51.974228 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 23:06:51.978105 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 23:06:51.981196 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 23:06:51.987706 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 23:06:51.990950 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 23:06:51.994857 0 9 4 | B1->B0 | 2424 2727 | 0 1 | (0 0) (1 1)
1546 23:06:52.000930 0 9 8 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1547 23:06:52.004471 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1548 23:06:52.007704 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1549 23:06:52.014326 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1550 23:06:52.017778 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1551 23:06:52.021084 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1552 23:06:52.027586 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1553 23:06:52.030946 0 10 4 | B1->B0 | 3030 2b2b | 0 1 | (0 0) (1 0)
1554 23:06:52.034124 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 23:06:52.040770 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 23:06:52.044427 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 23:06:52.047469 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1558 23:06:52.054405 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1559 23:06:52.057737 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1560 23:06:52.061657 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1561 23:06:52.064415 0 11 4 | B1->B0 | 3030 3838 | 0 1 | (0 0) (0 0)
1562 23:06:52.071001 0 11 8 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
1563 23:06:52.074704 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1564 23:06:52.077758 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1565 23:06:52.084098 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1566 23:06:52.087452 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1567 23:06:52.090911 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1568 23:06:52.097556 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1569 23:06:52.101150 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1570 23:06:52.104632 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1571 23:06:52.111625 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 23:06:52.114491 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 23:06:52.117565 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 23:06:52.124314 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 23:06:52.127656 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 23:06:52.131106 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 23:06:52.137603 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 23:06:52.140902 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 23:06:52.144280 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 23:06:52.147815 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 23:06:52.154346 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 23:06:52.157849 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1583 23:06:52.160926 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1584 23:06:52.167702 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1585 23:06:52.171293 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1586 23:06:52.174855 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1587 23:06:52.177768 Total UI for P1: 0, mck2ui 16
1588 23:06:52.181565 best dqsien dly found for B0: ( 0, 14, 4)
1589 23:06:52.184421 Total UI for P1: 0, mck2ui 16
1590 23:06:52.188033 best dqsien dly found for B1: ( 0, 14, 4)
1591 23:06:52.191314 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1592 23:06:52.194628 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1593 23:06:52.194715
1594 23:06:52.201095 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1595 23:06:52.204664 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1596 23:06:52.204751 [Gating] SW calibration Done
1597 23:06:52.207704 ==
1598 23:06:52.207790 Dram Type= 6, Freq= 0, CH_1, rank 0
1599 23:06:52.214353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1600 23:06:52.214491 ==
1601 23:06:52.214590 RX Vref Scan: 0
1602 23:06:52.214668
1603 23:06:52.217672 RX Vref 0 -> 0, step: 1
1604 23:06:52.217771
1605 23:06:52.221375 RX Delay -130 -> 252, step: 16
1606 23:06:52.224319 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1607 23:06:52.227804 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1608 23:06:52.231219 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1609 23:06:52.237936 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1610 23:06:52.241094 iDelay=222, Bit 4, Center 77 (-34 ~ 189) 224
1611 23:06:52.244485 iDelay=222, Bit 5, Center 101 (-2 ~ 205) 208
1612 23:06:52.248116 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1613 23:06:52.251014 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1614 23:06:52.257861 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1615 23:06:52.261073 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1616 23:06:52.264690 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1617 23:06:52.267965 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1618 23:06:52.271569 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1619 23:06:52.277903 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1620 23:06:52.281244 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1621 23:06:52.284610 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1622 23:06:52.284695 ==
1623 23:06:52.288445 Dram Type= 6, Freq= 0, CH_1, rank 0
1624 23:06:52.291538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1625 23:06:52.291623 ==
1626 23:06:52.294581 DQS Delay:
1627 23:06:52.294694 DQS0 = 0, DQS1 = 0
1628 23:06:52.297839 DQM Delay:
1629 23:06:52.297937 DQM0 = 87, DQM1 = 80
1630 23:06:52.298033 DQ Delay:
1631 23:06:52.301711 DQ0 =93, DQ1 =77, DQ2 =77, DQ3 =85
1632 23:06:52.304664 DQ4 =77, DQ5 =101, DQ6 =101, DQ7 =85
1633 23:06:52.308153 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1634 23:06:52.311381 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1635 23:06:52.311465
1636 23:06:52.311532
1637 23:06:52.314876 ==
1638 23:06:52.314961 Dram Type= 6, Freq= 0, CH_1, rank 0
1639 23:06:52.321641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1640 23:06:52.321740 ==
1641 23:06:52.321822
1642 23:06:52.321911
1643 23:06:52.324959 TX Vref Scan disable
1644 23:06:52.325043 == TX Byte 0 ==
1645 23:06:52.328279 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1646 23:06:52.334586 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1647 23:06:52.334671 == TX Byte 1 ==
1648 23:06:52.338104 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1649 23:06:52.344671 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1650 23:06:52.344771 ==
1651 23:06:52.348216 Dram Type= 6, Freq= 0, CH_1, rank 0
1652 23:06:52.351258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1653 23:06:52.351343 ==
1654 23:06:52.364979 TX Vref=22, minBit 8, minWin=27, winSum=448
1655 23:06:52.368462 TX Vref=24, minBit 8, minWin=27, winSum=453
1656 23:06:52.371647 TX Vref=26, minBit 15, minWin=27, winSum=456
1657 23:06:52.374841 TX Vref=28, minBit 15, minWin=27, winSum=458
1658 23:06:52.378223 TX Vref=30, minBit 15, minWin=27, winSum=458
1659 23:06:52.385328 TX Vref=32, minBit 15, minWin=27, winSum=457
1660 23:06:52.388716 [TxChooseVref] Worse bit 15, Min win 27, Win sum 458, Final Vref 28
1661 23:06:52.388817
1662 23:06:52.392434 Final TX Range 1 Vref 28
1663 23:06:52.392519
1664 23:06:52.392586 ==
1665 23:06:52.395688 Dram Type= 6, Freq= 0, CH_1, rank 0
1666 23:06:52.398756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1667 23:06:52.398840 ==
1668 23:06:52.398908
1669 23:06:52.398969
1670 23:06:52.402081 TX Vref Scan disable
1671 23:06:52.405754 == TX Byte 0 ==
1672 23:06:52.409129 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1673 23:06:52.412017 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1674 23:06:52.415684 == TX Byte 1 ==
1675 23:06:52.418718 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1676 23:06:52.422247 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1677 23:06:52.422337
1678 23:06:52.425709 [DATLAT]
1679 23:06:52.425793 Freq=800, CH1 RK0
1680 23:06:52.425859
1681 23:06:52.428946 DATLAT Default: 0xa
1682 23:06:52.429030 0, 0xFFFF, sum = 0
1683 23:06:52.432396 1, 0xFFFF, sum = 0
1684 23:06:52.432482 2, 0xFFFF, sum = 0
1685 23:06:52.435959 3, 0xFFFF, sum = 0
1686 23:06:52.436044 4, 0xFFFF, sum = 0
1687 23:06:52.438846 5, 0xFFFF, sum = 0
1688 23:06:52.438931 6, 0xFFFF, sum = 0
1689 23:06:52.442371 7, 0xFFFF, sum = 0
1690 23:06:52.442478 8, 0xFFFF, sum = 0
1691 23:06:52.445410 9, 0x0, sum = 1
1692 23:06:52.445496 10, 0x0, sum = 2
1693 23:06:52.449012 11, 0x0, sum = 3
1694 23:06:52.449097 12, 0x0, sum = 4
1695 23:06:52.452490 best_step = 10
1696 23:06:52.452574
1697 23:06:52.452640 ==
1698 23:06:52.455831 Dram Type= 6, Freq= 0, CH_1, rank 0
1699 23:06:52.458848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1700 23:06:52.458933 ==
1701 23:06:52.462302 RX Vref Scan: 1
1702 23:06:52.462399
1703 23:06:52.462480 Set Vref Range= 32 -> 127
1704 23:06:52.462543
1705 23:06:52.465703 RX Vref 32 -> 127, step: 1
1706 23:06:52.465787
1707 23:06:52.468868 RX Delay -95 -> 252, step: 8
1708 23:06:52.468952
1709 23:06:52.472486 Set Vref, RX VrefLevel [Byte0]: 32
1710 23:06:52.475914 [Byte1]: 32
1711 23:06:52.475999
1712 23:06:52.478987 Set Vref, RX VrefLevel [Byte0]: 33
1713 23:06:52.482215 [Byte1]: 33
1714 23:06:52.485581
1715 23:06:52.485655 Set Vref, RX VrefLevel [Byte0]: 34
1716 23:06:52.488623 [Byte1]: 34
1717 23:06:52.493056
1718 23:06:52.493133 Set Vref, RX VrefLevel [Byte0]: 35
1719 23:06:52.496635 [Byte1]: 35
1720 23:06:52.500781
1721 23:06:52.500856 Set Vref, RX VrefLevel [Byte0]: 36
1722 23:06:52.504145 [Byte1]: 36
1723 23:06:52.508194
1724 23:06:52.508270 Set Vref, RX VrefLevel [Byte0]: 37
1725 23:06:52.511491 [Byte1]: 37
1726 23:06:52.516180
1727 23:06:52.516258 Set Vref, RX VrefLevel [Byte0]: 38
1728 23:06:52.519399 [Byte1]: 38
1729 23:06:52.523439
1730 23:06:52.523511 Set Vref, RX VrefLevel [Byte0]: 39
1731 23:06:52.526818 [Byte1]: 39
1732 23:06:52.531164
1733 23:06:52.531267 Set Vref, RX VrefLevel [Byte0]: 40
1734 23:06:52.534317 [Byte1]: 40
1735 23:06:52.538881
1736 23:06:52.538955 Set Vref, RX VrefLevel [Byte0]: 41
1737 23:06:52.542050 [Byte1]: 41
1738 23:06:52.546157
1739 23:06:52.546232 Set Vref, RX VrefLevel [Byte0]: 42
1740 23:06:52.549698 [Byte1]: 42
1741 23:06:52.554337
1742 23:06:52.554431 Set Vref, RX VrefLevel [Byte0]: 43
1743 23:06:52.557932 [Byte1]: 43
1744 23:06:52.561489
1745 23:06:52.561576 Set Vref, RX VrefLevel [Byte0]: 44
1746 23:06:52.564921 [Byte1]: 44
1747 23:06:52.569025
1748 23:06:52.569112 Set Vref, RX VrefLevel [Byte0]: 45
1749 23:06:52.572641 [Byte1]: 45
1750 23:06:52.576821
1751 23:06:52.576907 Set Vref, RX VrefLevel [Byte0]: 46
1752 23:06:52.580160 [Byte1]: 46
1753 23:06:52.584200
1754 23:06:52.584321 Set Vref, RX VrefLevel [Byte0]: 47
1755 23:06:52.587601 [Byte1]: 47
1756 23:06:52.591699
1757 23:06:52.591786 Set Vref, RX VrefLevel [Byte0]: 48
1758 23:06:52.595136 [Byte1]: 48
1759 23:06:52.599515
1760 23:06:52.599602 Set Vref, RX VrefLevel [Byte0]: 49
1761 23:06:52.602889 [Byte1]: 49
1762 23:06:52.607282
1763 23:06:52.607370 Set Vref, RX VrefLevel [Byte0]: 50
1764 23:06:52.610558 [Byte1]: 50
1765 23:06:52.614702
1766 23:06:52.614789 Set Vref, RX VrefLevel [Byte0]: 51
1767 23:06:52.617907 [Byte1]: 51
1768 23:06:52.622311
1769 23:06:52.622420 Set Vref, RX VrefLevel [Byte0]: 52
1770 23:06:52.625497 [Byte1]: 52
1771 23:06:52.629888
1772 23:06:52.629975 Set Vref, RX VrefLevel [Byte0]: 53
1773 23:06:52.633478 [Byte1]: 53
1774 23:06:52.637520
1775 23:06:52.637606 Set Vref, RX VrefLevel [Byte0]: 54
1776 23:06:52.640829 [Byte1]: 54
1777 23:06:52.645261
1778 23:06:52.645348 Set Vref, RX VrefLevel [Byte0]: 55
1779 23:06:52.648394 [Byte1]: 55
1780 23:06:52.652895
1781 23:06:52.652982 Set Vref, RX VrefLevel [Byte0]: 56
1782 23:06:52.656364 [Byte1]: 56
1783 23:06:52.660346
1784 23:06:52.660432 Set Vref, RX VrefLevel [Byte0]: 57
1785 23:06:52.663622 [Byte1]: 57
1786 23:06:52.667917
1787 23:06:52.668004 Set Vref, RX VrefLevel [Byte0]: 58
1788 23:06:52.671368 [Byte1]: 58
1789 23:06:52.675580
1790 23:06:52.675667 Set Vref, RX VrefLevel [Byte0]: 59
1791 23:06:52.678994 [Byte1]: 59
1792 23:06:52.683023
1793 23:06:52.683109 Set Vref, RX VrefLevel [Byte0]: 60
1794 23:06:52.686392 [Byte1]: 60
1795 23:06:52.691189
1796 23:06:52.691276 Set Vref, RX VrefLevel [Byte0]: 61
1797 23:06:52.694323 [Byte1]: 61
1798 23:06:52.698962
1799 23:06:52.699049 Set Vref, RX VrefLevel [Byte0]: 62
1800 23:06:52.702040 [Byte1]: 62
1801 23:06:52.705898
1802 23:06:52.705988 Set Vref, RX VrefLevel [Byte0]: 63
1803 23:06:52.709051 [Byte1]: 63
1804 23:06:52.713624
1805 23:06:52.713712 Set Vref, RX VrefLevel [Byte0]: 64
1806 23:06:52.716693 [Byte1]: 64
1807 23:06:52.721395
1808 23:06:52.721482 Set Vref, RX VrefLevel [Byte0]: 65
1809 23:06:52.727443 [Byte1]: 65
1810 23:06:52.727585
1811 23:06:52.730963 Set Vref, RX VrefLevel [Byte0]: 66
1812 23:06:52.734204 [Byte1]: 66
1813 23:06:52.734308
1814 23:06:52.737687 Set Vref, RX VrefLevel [Byte0]: 67
1815 23:06:52.740812 [Byte1]: 67
1816 23:06:52.740923
1817 23:06:52.744140 Set Vref, RX VrefLevel [Byte0]: 68
1818 23:06:52.747427 [Byte1]: 68
1819 23:06:52.751422
1820 23:06:52.751510 Set Vref, RX VrefLevel [Byte0]: 69
1821 23:06:52.754674 [Byte1]: 69
1822 23:06:52.759075
1823 23:06:52.759179 Set Vref, RX VrefLevel [Byte0]: 70
1824 23:06:52.762355 [Byte1]: 70
1825 23:06:52.766767
1826 23:06:52.766873 Set Vref, RX VrefLevel [Byte0]: 71
1827 23:06:52.770028 [Byte1]: 71
1828 23:06:52.774276
1829 23:06:52.774376 Set Vref, RX VrefLevel [Byte0]: 72
1830 23:06:52.777874 [Byte1]: 72
1831 23:06:52.782060
1832 23:06:52.782138 Set Vref, RX VrefLevel [Byte0]: 73
1833 23:06:52.785208 [Byte1]: 73
1834 23:06:52.789986
1835 23:06:52.790088 Set Vref, RX VrefLevel [Byte0]: 74
1836 23:06:52.792676 [Byte1]: 74
1837 23:06:52.797113
1838 23:06:52.797192 Set Vref, RX VrefLevel [Byte0]: 75
1839 23:06:52.800389 [Byte1]: 75
1840 23:06:52.804593
1841 23:06:52.804688 Set Vref, RX VrefLevel [Byte0]: 76
1842 23:06:52.807913 [Byte1]: 76
1843 23:06:52.812409
1844 23:06:52.812522 Final RX Vref Byte 0 = 49 to rank0
1845 23:06:52.815651 Final RX Vref Byte 1 = 63 to rank0
1846 23:06:52.819054 Final RX Vref Byte 0 = 49 to rank1
1847 23:06:52.822406 Final RX Vref Byte 1 = 63 to rank1==
1848 23:06:52.826152 Dram Type= 6, Freq= 0, CH_1, rank 0
1849 23:06:52.829099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1850 23:06:52.832583 ==
1851 23:06:52.832685 DQS Delay:
1852 23:06:52.832784 DQS0 = 0, DQS1 = 0
1853 23:06:52.835850 DQM Delay:
1854 23:06:52.835951 DQM0 = 91, DQM1 = 83
1855 23:06:52.839126 DQ Delay:
1856 23:06:52.839214 DQ0 =96, DQ1 =84, DQ2 =84, DQ3 =88
1857 23:06:52.842345 DQ4 =92, DQ5 =100, DQ6 =100, DQ7 =88
1858 23:06:52.845905 DQ8 =72, DQ9 =72, DQ10 =88, DQ11 =80
1859 23:06:52.849259 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
1860 23:06:52.852704
1861 23:06:52.852809
1862 23:06:52.859242 [DQSOSCAuto] RK0, (LSB)MR18= 0x2d4a, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
1863 23:06:52.862674 CH1 RK0: MR19=606, MR18=2D4A
1864 23:06:52.869298 CH1_RK0: MR19=0x606, MR18=0x2D4A, DQSOSC=391, MR23=63, INC=96, DEC=64
1865 23:06:52.869403
1866 23:06:52.872590 ----->DramcWriteLeveling(PI) begin...
1867 23:06:52.872693 ==
1868 23:06:52.876110 Dram Type= 6, Freq= 0, CH_1, rank 1
1869 23:06:52.879375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1870 23:06:52.879468 ==
1871 23:06:52.882707 Write leveling (Byte 0): 26 => 26
1872 23:06:52.886444 Write leveling (Byte 1): 32 => 32
1873 23:06:52.889664 DramcWriteLeveling(PI) end<-----
1874 23:06:52.889771
1875 23:06:52.889863 ==
1876 23:06:52.892932 Dram Type= 6, Freq= 0, CH_1, rank 1
1877 23:06:52.895980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1878 23:06:52.896089 ==
1879 23:06:52.899532 [Gating] SW mode calibration
1880 23:06:52.906134 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1881 23:06:52.913424 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1882 23:06:52.916317 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1883 23:06:52.919654 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1884 23:06:52.922733 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 23:06:52.929492 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 23:06:52.932805 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 23:06:52.936378 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 23:06:52.942872 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 23:06:52.946732 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 23:06:52.949768 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 23:06:52.956284 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 23:06:52.959502 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 23:06:52.963116 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 23:06:52.969961 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 23:06:52.972935 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 23:06:52.976535 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 23:06:52.982977 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 23:06:52.986400 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1899 23:06:52.989861 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1900 23:06:52.997083 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 23:06:52.999760 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 23:06:53.003146 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 23:06:53.006487 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 23:06:53.013184 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 23:06:53.016649 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 23:06:53.019829 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 23:06:53.026498 0 9 4 | B1->B0 | 2424 2323 | 1 1 | (1 1) (1 1)
1908 23:06:53.029906 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1909 23:06:53.033159 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1910 23:06:53.039904 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1911 23:06:53.043032 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1912 23:06:53.046800 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1913 23:06:53.053022 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1914 23:06:53.056687 0 10 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1915 23:06:53.059996 0 10 4 | B1->B0 | 2d2d 3131 | 0 0 | (1 1) (0 1)
1916 23:06:53.066445 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1917 23:06:53.069966 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1918 23:06:53.073372 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1919 23:06:53.079710 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1920 23:06:53.083096 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1921 23:06:53.086390 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1922 23:06:53.093527 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1923 23:06:53.096503 0 11 4 | B1->B0 | 3232 3030 | 0 1 | (0 0) (0 0)
1924 23:06:53.099820 0 11 8 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
1925 23:06:53.103260 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1926 23:06:53.109706 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1927 23:06:53.113192 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1928 23:06:53.116481 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1929 23:06:53.123253 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1930 23:06:53.126773 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1931 23:06:53.129897 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1932 23:06:53.136847 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 23:06:53.140603 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 23:06:53.143350 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 23:06:53.150066 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 23:06:53.153427 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 23:06:53.156792 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 23:06:53.163485 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1939 23:06:53.166772 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1940 23:06:53.170672 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1941 23:06:53.173627 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1942 23:06:53.180054 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1943 23:06:53.183734 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1944 23:06:53.186693 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1945 23:06:53.193433 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1946 23:06:53.196813 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1947 23:06:53.200151 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1948 23:06:53.203230 Total UI for P1: 0, mck2ui 16
1949 23:06:53.206646 best dqsien dly found for B0: ( 0, 14, 2)
1950 23:06:53.210265 Total UI for P1: 0, mck2ui 16
1951 23:06:53.213495 best dqsien dly found for B1: ( 0, 14, 2)
1952 23:06:53.216776 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1953 23:06:53.220265 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1954 23:06:53.220343
1955 23:06:53.226636 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1956 23:06:53.230070 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1957 23:06:53.230174 [Gating] SW calibration Done
1958 23:06:53.230278 ==
1959 23:06:53.233921 Dram Type= 6, Freq= 0, CH_1, rank 1
1960 23:06:53.240047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1961 23:06:53.240133 ==
1962 23:06:53.240200 RX Vref Scan: 0
1963 23:06:53.240263
1964 23:06:53.243723 RX Vref 0 -> 0, step: 1
1965 23:06:53.243807
1966 23:06:53.246811 RX Delay -130 -> 252, step: 16
1967 23:06:53.250392 iDelay=206, Bit 0, Center 101 (-2 ~ 205) 208
1968 23:06:53.253563 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1969 23:06:53.257165 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1970 23:06:53.264056 iDelay=206, Bit 3, Center 85 (-18 ~ 189) 208
1971 23:06:53.267178 iDelay=206, Bit 4, Center 85 (-18 ~ 189) 208
1972 23:06:53.270280 iDelay=206, Bit 5, Center 101 (-2 ~ 205) 208
1973 23:06:53.273794 iDelay=206, Bit 6, Center 101 (-2 ~ 205) 208
1974 23:06:53.276852 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1975 23:06:53.283808 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1976 23:06:53.286958 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1977 23:06:53.290313 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1978 23:06:53.293708 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1979 23:06:53.297434 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1980 23:06:53.303859 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1981 23:06:53.307053 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1982 23:06:53.310987 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1983 23:06:53.311073 ==
1984 23:06:53.313672 Dram Type= 6, Freq= 0, CH_1, rank 1
1985 23:06:53.317280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1986 23:06:53.317380 ==
1987 23:06:53.320349 DQS Delay:
1988 23:06:53.320434 DQS0 = 0, DQS1 = 0
1989 23:06:53.320501 DQM Delay:
1990 23:06:53.323807 DQM0 = 90, DQM1 = 83
1991 23:06:53.323892 DQ Delay:
1992 23:06:53.327438 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =85
1993 23:06:53.330515 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1994 23:06:53.333766 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1995 23:06:53.337332 DQ12 =93, DQ13 =93, DQ14 =85, DQ15 =93
1996 23:06:53.337421
1997 23:06:53.337488
1998 23:06:53.337548 ==
1999 23:06:53.340365 Dram Type= 6, Freq= 0, CH_1, rank 1
2000 23:06:53.347031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2001 23:06:53.347112 ==
2002 23:06:53.347180
2003 23:06:53.347241
2004 23:06:53.347297 TX Vref Scan disable
2005 23:06:53.351416 == TX Byte 0 ==
2006 23:06:53.354619 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2007 23:06:53.357853 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2008 23:06:53.361173 == TX Byte 1 ==
2009 23:06:53.364860 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
2010 23:06:53.367688 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
2011 23:06:53.371280 ==
2012 23:06:53.374542 Dram Type= 6, Freq= 0, CH_1, rank 1
2013 23:06:53.377813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2014 23:06:53.377892 ==
2015 23:06:53.390564 TX Vref=22, minBit 8, minWin=27, winSum=449
2016 23:06:53.393925 TX Vref=24, minBit 9, minWin=27, winSum=452
2017 23:06:53.396975 TX Vref=26, minBit 13, minWin=27, winSum=453
2018 23:06:53.400683 TX Vref=28, minBit 7, minWin=28, winSum=457
2019 23:06:53.404028 TX Vref=30, minBit 9, minWin=27, winSum=457
2020 23:06:53.410798 TX Vref=32, minBit 15, minWin=27, winSum=457
2021 23:06:53.413837 [TxChooseVref] Worse bit 7, Min win 28, Win sum 457, Final Vref 28
2022 23:06:53.413915
2023 23:06:53.416966 Final TX Range 1 Vref 28
2024 23:06:53.417037
2025 23:06:53.417106 ==
2026 23:06:53.420397 Dram Type= 6, Freq= 0, CH_1, rank 1
2027 23:06:53.423561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2028 23:06:53.427426 ==
2029 23:06:53.427502
2030 23:06:53.427565
2031 23:06:53.427641 TX Vref Scan disable
2032 23:06:53.430772 == TX Byte 0 ==
2033 23:06:53.434286 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2034 23:06:53.437488 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2035 23:06:53.441014 == TX Byte 1 ==
2036 23:06:53.443898 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
2037 23:06:53.447513 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
2038 23:06:53.450825
2039 23:06:53.450898 [DATLAT]
2040 23:06:53.450962 Freq=800, CH1 RK1
2041 23:06:53.451034
2042 23:06:53.453793 DATLAT Default: 0xa
2043 23:06:53.453875 0, 0xFFFF, sum = 0
2044 23:06:53.457408 1, 0xFFFF, sum = 0
2045 23:06:53.457498 2, 0xFFFF, sum = 0
2046 23:06:53.460928 3, 0xFFFF, sum = 0
2047 23:06:53.461004 4, 0xFFFF, sum = 0
2048 23:06:53.464104 5, 0xFFFF, sum = 0
2049 23:06:53.467338 6, 0xFFFF, sum = 0
2050 23:06:53.467426 7, 0xFFFF, sum = 0
2051 23:06:53.470610 8, 0xFFFF, sum = 0
2052 23:06:53.470689 9, 0x0, sum = 1
2053 23:06:53.470752 10, 0x0, sum = 2
2054 23:06:53.474034 11, 0x0, sum = 3
2055 23:06:53.474104 12, 0x0, sum = 4
2056 23:06:53.477692 best_step = 10
2057 23:06:53.477778
2058 23:06:53.477846 ==
2059 23:06:53.480741 Dram Type= 6, Freq= 0, CH_1, rank 1
2060 23:06:53.484271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2061 23:06:53.484350 ==
2062 23:06:53.487247 RX Vref Scan: 0
2063 23:06:53.487320
2064 23:06:53.487382 RX Vref 0 -> 0, step: 1
2065 23:06:53.487450
2066 23:06:53.490909 RX Delay -95 -> 252, step: 8
2067 23:06:53.497590 iDelay=209, Bit 0, Center 92 (-7 ~ 192) 200
2068 23:06:53.501147 iDelay=209, Bit 1, Center 84 (-15 ~ 184) 200
2069 23:06:53.504280 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
2070 23:06:53.507430 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2071 23:06:53.510931 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
2072 23:06:53.517469 iDelay=209, Bit 5, Center 100 (-7 ~ 208) 216
2073 23:06:53.521019 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2074 23:06:53.524044 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2075 23:06:53.527753 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2076 23:06:53.530986 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2077 23:06:53.537608 iDelay=209, Bit 10, Center 88 (-23 ~ 200) 224
2078 23:06:53.540648 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2079 23:06:53.544114 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2080 23:06:53.547999 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2081 23:06:53.550772 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2082 23:06:53.557724 iDelay=209, Bit 15, Center 96 (-15 ~ 208) 224
2083 23:06:53.557811 ==
2084 23:06:53.560890 Dram Type= 6, Freq= 0, CH_1, rank 1
2085 23:06:53.564073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2086 23:06:53.564160 ==
2087 23:06:53.564227 DQS Delay:
2088 23:06:53.567654 DQS0 = 0, DQS1 = 0
2089 23:06:53.567739 DQM Delay:
2090 23:06:53.571079 DQM0 = 90, DQM1 = 84
2091 23:06:53.571164 DQ Delay:
2092 23:06:53.574264 DQ0 =92, DQ1 =84, DQ2 =80, DQ3 =88
2093 23:06:53.577324 DQ4 =92, DQ5 =100, DQ6 =96, DQ7 =88
2094 23:06:53.580820 DQ8 =68, DQ9 =72, DQ10 =88, DQ11 =80
2095 23:06:53.584281 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =96
2096 23:06:53.584366
2097 23:06:53.584433
2098 23:06:53.590969 [DQSOSCAuto] RK1, (LSB)MR18= 0x3b10, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
2099 23:06:53.594333 CH1 RK1: MR19=606, MR18=3B10
2100 23:06:53.600951 CH1_RK1: MR19=0x606, MR18=0x3B10, DQSOSC=394, MR23=63, INC=95, DEC=63
2101 23:06:53.604327 [RxdqsGatingPostProcess] freq 800
2102 23:06:53.610833 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2103 23:06:53.610919 Pre-setting of DQS Precalculation
2104 23:06:53.617500 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2105 23:06:53.624201 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2106 23:06:53.630938 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2107 23:06:53.631024
2108 23:06:53.631091
2109 23:06:53.634229 [Calibration Summary] 1600 Mbps
2110 23:06:53.637552 CH 0, Rank 0
2111 23:06:53.637637 SW Impedance : PASS
2112 23:06:53.641311 DUTY Scan : NO K
2113 23:06:53.644378 ZQ Calibration : PASS
2114 23:06:53.644464 Jitter Meter : NO K
2115 23:06:53.647639 CBT Training : PASS
2116 23:06:53.647724 Write leveling : PASS
2117 23:06:53.650847 RX DQS gating : PASS
2118 23:06:53.654368 RX DQ/DQS(RDDQC) : PASS
2119 23:06:53.654494 TX DQ/DQS : PASS
2120 23:06:53.657782 RX DATLAT : PASS
2121 23:06:53.661024 RX DQ/DQS(Engine): PASS
2122 23:06:53.661108 TX OE : NO K
2123 23:06:53.664437 All Pass.
2124 23:06:53.664522
2125 23:06:53.664589 CH 0, Rank 1
2126 23:06:53.667672 SW Impedance : PASS
2127 23:06:53.667823 DUTY Scan : NO K
2128 23:06:53.670854 ZQ Calibration : PASS
2129 23:06:53.674422 Jitter Meter : NO K
2130 23:06:53.674507 CBT Training : PASS
2131 23:06:53.677890 Write leveling : PASS
2132 23:06:53.681067 RX DQS gating : PASS
2133 23:06:53.681153 RX DQ/DQS(RDDQC) : PASS
2134 23:06:53.684439 TX DQ/DQS : PASS
2135 23:06:53.687709 RX DATLAT : PASS
2136 23:06:53.687795 RX DQ/DQS(Engine): PASS
2137 23:06:53.690935 TX OE : NO K
2138 23:06:53.691020 All Pass.
2139 23:06:53.691088
2140 23:06:53.694547 CH 1, Rank 0
2141 23:06:53.694659 SW Impedance : PASS
2142 23:06:53.697642 DUTY Scan : NO K
2143 23:06:53.697727 ZQ Calibration : PASS
2144 23:06:53.700858 Jitter Meter : NO K
2145 23:06:53.704382 CBT Training : PASS
2146 23:06:53.704466 Write leveling : PASS
2147 23:06:53.707983 RX DQS gating : PASS
2148 23:06:53.711124 RX DQ/DQS(RDDQC) : PASS
2149 23:06:53.711209 TX DQ/DQS : PASS
2150 23:06:53.714290 RX DATLAT : PASS
2151 23:06:53.717867 RX DQ/DQS(Engine): PASS
2152 23:06:53.717951 TX OE : NO K
2153 23:06:53.718019 All Pass.
2154 23:06:53.721295
2155 23:06:53.721379 CH 1, Rank 1
2156 23:06:53.724799 SW Impedance : PASS
2157 23:06:53.724883 DUTY Scan : NO K
2158 23:06:53.727909 ZQ Calibration : PASS
2159 23:06:53.728014 Jitter Meter : NO K
2160 23:06:53.731369 CBT Training : PASS
2161 23:06:53.734790 Write leveling : PASS
2162 23:06:53.734874 RX DQS gating : PASS
2163 23:06:53.737953 RX DQ/DQS(RDDQC) : PASS
2164 23:06:53.741521 TX DQ/DQS : PASS
2165 23:06:53.741640 RX DATLAT : PASS
2166 23:06:53.744528 RX DQ/DQS(Engine): PASS
2167 23:06:53.747949 TX OE : NO K
2168 23:06:53.748035 All Pass.
2169 23:06:53.748102
2170 23:06:53.748164 DramC Write-DBI off
2171 23:06:53.751690 PER_BANK_REFRESH: Hybrid Mode
2172 23:06:53.754660 TX_TRACKING: ON
2173 23:06:53.758128 [GetDramInforAfterCalByMRR] Vendor 6.
2174 23:06:53.761526 [GetDramInforAfterCalByMRR] Revision 606.
2175 23:06:53.764837 [GetDramInforAfterCalByMRR] Revision 2 0.
2176 23:06:53.764948 MR0 0x3b3b
2177 23:06:53.768274 MR8 0x5151
2178 23:06:53.771435 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2179 23:06:53.771520
2180 23:06:53.771588 MR0 0x3b3b
2181 23:06:53.771651 MR8 0x5151
2182 23:06:53.774738 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2183 23:06:53.777914
2184 23:06:53.785027 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2185 23:06:53.788240 [FAST_K] Save calibration result to emmc
2186 23:06:53.791376 [FAST_K] Save calibration result to emmc
2187 23:06:53.795034 dram_init: config_dvfs: 1
2188 23:06:53.798190 dramc_set_vcore_voltage set vcore to 662500
2189 23:06:53.801873 Read voltage for 1200, 2
2190 23:06:53.801959 Vio18 = 0
2191 23:06:53.805013 Vcore = 662500
2192 23:06:53.805098 Vdram = 0
2193 23:06:53.805166 Vddq = 0
2194 23:06:53.805228 Vmddr = 0
2195 23:06:53.811753 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2196 23:06:53.815166 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2197 23:06:53.818263 MEM_TYPE=3, freq_sel=15
2198 23:06:53.821770 sv_algorithm_assistance_LP4_1600
2199 23:06:53.824912 ============ PULL DRAM RESETB DOWN ============
2200 23:06:53.831592 ========== PULL DRAM RESETB DOWN end =========
2201 23:06:53.834888 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2202 23:06:53.838251 ===================================
2203 23:06:53.841545 LPDDR4 DRAM CONFIGURATION
2204 23:06:53.845022 ===================================
2205 23:06:53.845108 EX_ROW_EN[0] = 0x0
2206 23:06:53.848057 EX_ROW_EN[1] = 0x0
2207 23:06:53.848142 LP4Y_EN = 0x0
2208 23:06:53.852031 WORK_FSP = 0x0
2209 23:06:53.852116 WL = 0x4
2210 23:06:53.855024 RL = 0x4
2211 23:06:53.855146 BL = 0x2
2212 23:06:53.857932 RPST = 0x0
2213 23:06:53.858047 RD_PRE = 0x0
2214 23:06:53.861574 WR_PRE = 0x1
2215 23:06:53.861674 WR_PST = 0x0
2216 23:06:53.864862 DBI_WR = 0x0
2217 23:06:53.864960 DBI_RD = 0x0
2218 23:06:53.868282 OTF = 0x1
2219 23:06:53.871427 ===================================
2220 23:06:53.874845 ===================================
2221 23:06:53.874930 ANA top config
2222 23:06:53.878269 ===================================
2223 23:06:53.881673 DLL_ASYNC_EN = 0
2224 23:06:53.884796 ALL_SLAVE_EN = 0
2225 23:06:53.888197 NEW_RANK_MODE = 1
2226 23:06:53.888283 DLL_IDLE_MODE = 1
2227 23:06:53.891396 LP45_APHY_COMB_EN = 1
2228 23:06:53.895002 TX_ODT_DIS = 1
2229 23:06:53.898535 NEW_8X_MODE = 1
2230 23:06:53.901645 ===================================
2231 23:06:53.904891 ===================================
2232 23:06:53.908647 data_rate = 2400
2233 23:06:53.908732 CKR = 1
2234 23:06:53.911443 DQ_P2S_RATIO = 8
2235 23:06:53.915058 ===================================
2236 23:06:53.918424 CA_P2S_RATIO = 8
2237 23:06:53.921847 DQ_CA_OPEN = 0
2238 23:06:53.924849 DQ_SEMI_OPEN = 0
2239 23:06:53.928225 CA_SEMI_OPEN = 0
2240 23:06:53.928311 CA_FULL_RATE = 0
2241 23:06:53.931975 DQ_CKDIV4_EN = 0
2242 23:06:53.935146 CA_CKDIV4_EN = 0
2243 23:06:53.938388 CA_PREDIV_EN = 0
2244 23:06:53.941790 PH8_DLY = 17
2245 23:06:53.944775 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2246 23:06:53.944860 DQ_AAMCK_DIV = 4
2247 23:06:53.948131 CA_AAMCK_DIV = 4
2248 23:06:53.951924 CA_ADMCK_DIV = 4
2249 23:06:53.954782 DQ_TRACK_CA_EN = 0
2250 23:06:53.958539 CA_PICK = 1200
2251 23:06:53.961553 CA_MCKIO = 1200
2252 23:06:53.961638 MCKIO_SEMI = 0
2253 23:06:53.964880 PLL_FREQ = 2366
2254 23:06:53.968137 DQ_UI_PI_RATIO = 32
2255 23:06:53.971438 CA_UI_PI_RATIO = 0
2256 23:06:53.974779 ===================================
2257 23:06:53.978214 ===================================
2258 23:06:53.981487 memory_type:LPDDR4
2259 23:06:53.981572 GP_NUM : 10
2260 23:06:53.984711 SRAM_EN : 1
2261 23:06:53.988383 MD32_EN : 0
2262 23:06:53.991512 ===================================
2263 23:06:53.991596 [ANA_INIT] >>>>>>>>>>>>>>
2264 23:06:53.994888 <<<<<< [CONFIGURE PHASE]: ANA_TX
2265 23:06:53.998266 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2266 23:06:54.001559 ===================================
2267 23:06:54.004793 data_rate = 2400,PCW = 0X5b00
2268 23:06:54.008655 ===================================
2269 23:06:54.011859 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2270 23:06:54.018356 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2271 23:06:54.021563 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2272 23:06:54.028285 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2273 23:06:54.031476 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2274 23:06:54.034998 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2275 23:06:54.035092 [ANA_INIT] flow start
2276 23:06:54.038433 [ANA_INIT] PLL >>>>>>>>
2277 23:06:54.041793 [ANA_INIT] PLL <<<<<<<<
2278 23:06:54.041941 [ANA_INIT] MIDPI >>>>>>>>
2279 23:06:54.045138 [ANA_INIT] MIDPI <<<<<<<<
2280 23:06:54.048491 [ANA_INIT] DLL >>>>>>>>
2281 23:06:54.048578 [ANA_INIT] DLL <<<<<<<<
2282 23:06:54.051766 [ANA_INIT] flow end
2283 23:06:54.055015 ============ LP4 DIFF to SE enter ============
2284 23:06:54.061889 ============ LP4 DIFF to SE exit ============
2285 23:06:54.061975 [ANA_INIT] <<<<<<<<<<<<<
2286 23:06:54.065020 [Flow] Enable top DCM control >>>>>
2287 23:06:54.068431 [Flow] Enable top DCM control <<<<<
2288 23:06:54.072071 Enable DLL master slave shuffle
2289 23:06:54.078298 ==============================================================
2290 23:06:54.078394 Gating Mode config
2291 23:06:54.085106 ==============================================================
2292 23:06:54.085193 Config description:
2293 23:06:54.095357 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2294 23:06:54.102181 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2295 23:06:54.108654 SELPH_MODE 0: By rank 1: By Phase
2296 23:06:54.111905 ==============================================================
2297 23:06:54.115324 GAT_TRACK_EN = 1
2298 23:06:54.118505 RX_GATING_MODE = 2
2299 23:06:54.122035 RX_GATING_TRACK_MODE = 2
2300 23:06:54.125802 SELPH_MODE = 1
2301 23:06:54.128642 PICG_EARLY_EN = 1
2302 23:06:54.132044 VALID_LAT_VALUE = 1
2303 23:06:54.138901 ==============================================================
2304 23:06:54.141981 Enter into Gating configuration >>>>
2305 23:06:54.145583 Exit from Gating configuration <<<<
2306 23:06:54.145670 Enter into DVFS_PRE_config >>>>>
2307 23:06:54.159063 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2308 23:06:54.162121 Exit from DVFS_PRE_config <<<<<
2309 23:06:54.165610 Enter into PICG configuration >>>>
2310 23:06:54.165697 Exit from PICG configuration <<<<
2311 23:06:54.169066 [RX_INPUT] configuration >>>>>
2312 23:06:54.172220 [RX_INPUT] configuration <<<<<
2313 23:06:54.179125 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2314 23:06:54.182498 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2315 23:06:54.189190 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2316 23:06:54.195867 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2317 23:06:54.202370 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2318 23:06:54.208935 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2319 23:06:54.212785 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2320 23:06:54.215973 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2321 23:06:54.218886 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2322 23:06:54.225612 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2323 23:06:54.229145 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2324 23:06:54.232326 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2325 23:06:54.235749 ===================================
2326 23:06:54.239541 LPDDR4 DRAM CONFIGURATION
2327 23:06:54.242366 ===================================
2328 23:06:54.242493 EX_ROW_EN[0] = 0x0
2329 23:06:54.245728 EX_ROW_EN[1] = 0x0
2330 23:06:54.249127 LP4Y_EN = 0x0
2331 23:06:54.249211 WORK_FSP = 0x0
2332 23:06:54.252531 WL = 0x4
2333 23:06:54.252641 RL = 0x4
2334 23:06:54.255747 BL = 0x2
2335 23:06:54.255831 RPST = 0x0
2336 23:06:54.259272 RD_PRE = 0x0
2337 23:06:54.259355 WR_PRE = 0x1
2338 23:06:54.262580 WR_PST = 0x0
2339 23:06:54.262756 DBI_WR = 0x0
2340 23:06:54.266413 DBI_RD = 0x0
2341 23:06:54.266520 OTF = 0x1
2342 23:06:54.269006 ===================================
2343 23:06:54.272633 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2344 23:06:54.279178 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2345 23:06:54.282535 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2346 23:06:54.286234 ===================================
2347 23:06:54.289248 LPDDR4 DRAM CONFIGURATION
2348 23:06:54.292916 ===================================
2349 23:06:54.293001 EX_ROW_EN[0] = 0x10
2350 23:06:54.296056 EX_ROW_EN[1] = 0x0
2351 23:06:54.296140 LP4Y_EN = 0x0
2352 23:06:54.299533 WORK_FSP = 0x0
2353 23:06:54.299616 WL = 0x4
2354 23:06:54.302736 RL = 0x4
2355 23:06:54.302823 BL = 0x2
2356 23:06:54.305934 RPST = 0x0
2357 23:06:54.306043 RD_PRE = 0x0
2358 23:06:54.308954 WR_PRE = 0x1
2359 23:06:54.312329 WR_PST = 0x0
2360 23:06:54.312431 DBI_WR = 0x0
2361 23:06:54.315628 DBI_RD = 0x0
2362 23:06:54.315703 OTF = 0x1
2363 23:06:54.319369 ===================================
2364 23:06:54.325822 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2365 23:06:54.325930 ==
2366 23:06:54.328990 Dram Type= 6, Freq= 0, CH_0, rank 0
2367 23:06:54.332749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2368 23:06:54.332853 ==
2369 23:06:54.335985 [Duty_Offset_Calibration]
2370 23:06:54.336094 B0:2 B1:0 CA:1
2371 23:06:54.336188
2372 23:06:54.339402 [DutyScan_Calibration_Flow] k_type=0
2373 23:06:54.349330
2374 23:06:54.349437 ==CLK 0==
2375 23:06:54.352465 Final CLK duty delay cell = -4
2376 23:06:54.356022 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2377 23:06:54.359092 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2378 23:06:54.362297 [-4] AVG Duty = 4953%(X100)
2379 23:06:54.362415
2380 23:06:54.365902 CH0 CLK Duty spec in!! Max-Min= 156%
2381 23:06:54.369438 [DutyScan_Calibration_Flow] ====Done====
2382 23:06:54.369509
2383 23:06:54.372469 [DutyScan_Calibration_Flow] k_type=1
2384 23:06:54.388171
2385 23:06:54.388270 ==DQS 0 ==
2386 23:06:54.391426 Final DQS duty delay cell = 0
2387 23:06:54.395224 [0] MAX Duty = 5187%(X100), DQS PI = 30
2388 23:06:54.398372 [0] MIN Duty = 4938%(X100), DQS PI = 0
2389 23:06:54.398476 [0] AVG Duty = 5062%(X100)
2390 23:06:54.401726
2391 23:06:54.401833 ==DQS 1 ==
2392 23:06:54.404999 Final DQS duty delay cell = -4
2393 23:06:54.408243 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2394 23:06:54.411369 [-4] MIN Duty = 4938%(X100), DQS PI = 6
2395 23:06:54.415505 [-4] AVG Duty = 5031%(X100)
2396 23:06:54.415609
2397 23:06:54.418548 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2398 23:06:54.418625
2399 23:06:54.421510 CH0 DQS 1 Duty spec in!! Max-Min= 186%
2400 23:06:54.424651 [DutyScan_Calibration_Flow] ====Done====
2401 23:06:54.424747
2402 23:06:54.428365 [DutyScan_Calibration_Flow] k_type=3
2403 23:06:54.444823
2404 23:06:54.444929 ==DQM 0 ==
2405 23:06:54.448183 Final DQM duty delay cell = 0
2406 23:06:54.451317 [0] MAX Duty = 5062%(X100), DQS PI = 24
2407 23:06:54.454831 [0] MIN Duty = 4844%(X100), DQS PI = 0
2408 23:06:54.454901 [0] AVG Duty = 4953%(X100)
2409 23:06:54.458356
2410 23:06:54.458495 ==DQM 1 ==
2411 23:06:54.461682 Final DQM duty delay cell = 0
2412 23:06:54.465014 [0] MAX Duty = 5187%(X100), DQS PI = 46
2413 23:06:54.468371 [0] MIN Duty = 5000%(X100), DQS PI = 12
2414 23:06:54.468467 [0] AVG Duty = 5093%(X100)
2415 23:06:54.471801
2416 23:06:54.474917 CH0 DQM 0 Duty spec in!! Max-Min= 218%
2417 23:06:54.474989
2418 23:06:54.478321 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2419 23:06:54.481651 [DutyScan_Calibration_Flow] ====Done====
2420 23:06:54.481751
2421 23:06:54.484946 [DutyScan_Calibration_Flow] k_type=2
2422 23:06:54.501183
2423 23:06:54.501262 ==DQ 0 ==
2424 23:06:54.504791 Final DQ duty delay cell = -4
2425 23:06:54.508028 [-4] MAX Duty = 5031%(X100), DQS PI = 34
2426 23:06:54.511569 [-4] MIN Duty = 4875%(X100), DQS PI = 14
2427 23:06:54.514718 [-4] AVG Duty = 4953%(X100)
2428 23:06:54.514791
2429 23:06:54.514854 ==DQ 1 ==
2430 23:06:54.518477 Final DQ duty delay cell = 4
2431 23:06:54.521485 [4] MAX Duty = 5093%(X100), DQS PI = 4
2432 23:06:54.525156 [4] MIN Duty = 5031%(X100), DQS PI = 0
2433 23:06:54.525227 [4] AVG Duty = 5062%(X100)
2434 23:06:54.525290
2435 23:06:54.528078 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2436 23:06:54.531383
2437 23:06:54.534774 CH0 DQ 1 Duty spec in!! Max-Min= 62%
2438 23:06:54.537991 [DutyScan_Calibration_Flow] ====Done====
2439 23:06:54.538088 ==
2440 23:06:54.541465 Dram Type= 6, Freq= 0, CH_1, rank 0
2441 23:06:54.545248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2442 23:06:54.545349 ==
2443 23:06:54.548075 [Duty_Offset_Calibration]
2444 23:06:54.548172 B0:0 B1:-1 CA:2
2445 23:06:54.548261
2446 23:06:54.551283 [DutyScan_Calibration_Flow] k_type=0
2447 23:06:54.561795
2448 23:06:54.561899 ==CLK 0==
2449 23:06:54.565216 Final CLK duty delay cell = 0
2450 23:06:54.568387 [0] MAX Duty = 5156%(X100), DQS PI = 16
2451 23:06:54.571610 [0] MIN Duty = 4938%(X100), DQS PI = 44
2452 23:06:54.571709 [0] AVG Duty = 5047%(X100)
2453 23:06:54.574790
2454 23:06:54.574888 CH1 CLK Duty spec in!! Max-Min= 218%
2455 23:06:54.581559 [DutyScan_Calibration_Flow] ====Done====
2456 23:06:54.581635
2457 23:06:54.584891 [DutyScan_Calibration_Flow] k_type=1
2458 23:06:54.600803
2459 23:06:54.600887 ==DQS 0 ==
2460 23:06:54.604082 Final DQS duty delay cell = 0
2461 23:06:54.607711 [0] MAX Duty = 5093%(X100), DQS PI = 24
2462 23:06:54.611000 [0] MIN Duty = 4969%(X100), DQS PI = 0
2463 23:06:54.611112 [0] AVG Duty = 5031%(X100)
2464 23:06:54.614503
2465 23:06:54.614587 ==DQS 1 ==
2466 23:06:54.617971 Final DQS duty delay cell = 0
2467 23:06:54.621155 [0] MAX Duty = 5156%(X100), DQS PI = 0
2468 23:06:54.624349 [0] MIN Duty = 4813%(X100), DQS PI = 36
2469 23:06:54.624492 [0] AVG Duty = 4984%(X100)
2470 23:06:54.624625
2471 23:06:54.631378 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2472 23:06:54.631463
2473 23:06:54.634392 CH1 DQS 1 Duty spec in!! Max-Min= 343%
2474 23:06:54.637676 [DutyScan_Calibration_Flow] ====Done====
2475 23:06:54.637760
2476 23:06:54.640980 [DutyScan_Calibration_Flow] k_type=3
2477 23:06:54.658080
2478 23:06:54.658171 ==DQM 0 ==
2479 23:06:54.661957 Final DQM duty delay cell = 4
2480 23:06:54.664668 [4] MAX Duty = 5093%(X100), DQS PI = 22
2481 23:06:54.668176 [4] MIN Duty = 4938%(X100), DQS PI = 48
2482 23:06:54.668262 [4] AVG Duty = 5015%(X100)
2483 23:06:54.671573
2484 23:06:54.671658 ==DQM 1 ==
2485 23:06:54.675352 Final DQM duty delay cell = 0
2486 23:06:54.678109 [0] MAX Duty = 5249%(X100), DQS PI = 0
2487 23:06:54.681682 [0] MIN Duty = 4875%(X100), DQS PI = 38
2488 23:06:54.681769 [0] AVG Duty = 5062%(X100)
2489 23:06:54.684828
2490 23:06:54.688229 CH1 DQM 0 Duty spec in!! Max-Min= 155%
2491 23:06:54.688316
2492 23:06:54.691860 CH1 DQM 1 Duty spec in!! Max-Min= 374%
2493 23:06:54.695000 [DutyScan_Calibration_Flow] ====Done====
2494 23:06:54.695086
2495 23:06:54.698218 [DutyScan_Calibration_Flow] k_type=2
2496 23:06:54.714909
2497 23:06:54.714995 ==DQ 0 ==
2498 23:06:54.718400 Final DQ duty delay cell = 0
2499 23:06:54.721579 [0] MAX Duty = 5062%(X100), DQS PI = 20
2500 23:06:54.724663 [0] MIN Duty = 4938%(X100), DQS PI = 0
2501 23:06:54.724751 [0] AVG Duty = 5000%(X100)
2502 23:06:54.724819
2503 23:06:54.728201 ==DQ 1 ==
2504 23:06:54.731249 Final DQ duty delay cell = 0
2505 23:06:54.734700 [0] MAX Duty = 5031%(X100), DQS PI = 2
2506 23:06:54.738343 [0] MIN Duty = 4813%(X100), DQS PI = 34
2507 23:06:54.738446 [0] AVG Duty = 4922%(X100)
2508 23:06:54.738516
2509 23:06:54.741814 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2510 23:06:54.741900
2511 23:06:54.744978 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2512 23:06:54.751206 [DutyScan_Calibration_Flow] ====Done====
2513 23:06:54.755001 nWR fixed to 30
2514 23:06:54.755088 [ModeRegInit_LP4] CH0 RK0
2515 23:06:54.758135 [ModeRegInit_LP4] CH0 RK1
2516 23:06:54.761458 [ModeRegInit_LP4] CH1 RK0
2517 23:06:54.761540 [ModeRegInit_LP4] CH1 RK1
2518 23:06:54.764580 match AC timing 7
2519 23:06:54.768276 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2520 23:06:54.771452 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2521 23:06:54.777981 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2522 23:06:54.781232 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2523 23:06:54.787715 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2524 23:06:54.787796 ==
2525 23:06:54.791378 Dram Type= 6, Freq= 0, CH_0, rank 0
2526 23:06:54.794881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2527 23:06:54.794963 ==
2528 23:06:54.801622 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2529 23:06:54.804619 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2530 23:06:54.814610 [CA 0] Center 38 (7~69) winsize 63
2531 23:06:54.817847 [CA 1] Center 38 (7~69) winsize 63
2532 23:06:54.821196 [CA 2] Center 34 (4~65) winsize 62
2533 23:06:54.824649 [CA 3] Center 34 (4~65) winsize 62
2534 23:06:54.827943 [CA 4] Center 33 (3~64) winsize 62
2535 23:06:54.831064 [CA 5] Center 32 (2~63) winsize 62
2536 23:06:54.831140
2537 23:06:54.834446 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2538 23:06:54.834527
2539 23:06:54.837732 [CATrainingPosCal] consider 1 rank data
2540 23:06:54.840838 u2DelayCellTimex100 = 270/100 ps
2541 23:06:54.844312 CA0 delay=38 (7~69),Diff = 6 PI (28 cell)
2542 23:06:54.847551 CA1 delay=38 (7~69),Diff = 6 PI (28 cell)
2543 23:06:54.854319 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2544 23:06:54.857632 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2545 23:06:54.861588 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2546 23:06:54.864274 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2547 23:06:54.864355
2548 23:06:54.867939 CA PerBit enable=1, Macro0, CA PI delay=32
2549 23:06:54.868015
2550 23:06:54.871490 [CBTSetCACLKResult] CA Dly = 32
2551 23:06:54.871561 CS Dly: 6 (0~37)
2552 23:06:54.871623 ==
2553 23:06:54.874563 Dram Type= 6, Freq= 0, CH_0, rank 1
2554 23:06:54.881106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2555 23:06:54.881185 ==
2556 23:06:54.884413 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2557 23:06:54.891195 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2558 23:06:54.900129 [CA 0] Center 38 (7~69) winsize 63
2559 23:06:54.903441 [CA 1] Center 38 (7~69) winsize 63
2560 23:06:54.906597 [CA 2] Center 35 (5~66) winsize 62
2561 23:06:54.909882 [CA 3] Center 35 (5~66) winsize 62
2562 23:06:54.913348 [CA 4] Center 34 (3~65) winsize 63
2563 23:06:54.916724 [CA 5] Center 33 (3~63) winsize 61
2564 23:06:54.916797
2565 23:06:54.920238 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2566 23:06:54.920319
2567 23:06:54.923342 [CATrainingPosCal] consider 2 rank data
2568 23:06:54.926674 u2DelayCellTimex100 = 270/100 ps
2569 23:06:54.930323 CA0 delay=38 (7~69),Diff = 5 PI (24 cell)
2570 23:06:54.933753 CA1 delay=38 (7~69),Diff = 5 PI (24 cell)
2571 23:06:54.940030 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
2572 23:06:54.943633 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2573 23:06:54.946940 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2574 23:06:54.950351 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2575 23:06:54.950472
2576 23:06:54.953318 CA PerBit enable=1, Macro0, CA PI delay=33
2577 23:06:54.953388
2578 23:06:54.956723 [CBTSetCACLKResult] CA Dly = 33
2579 23:06:54.956810 CS Dly: 7 (0~39)
2580 23:06:54.956895
2581 23:06:54.960019 ----->DramcWriteLeveling(PI) begin...
2582 23:06:54.963351 ==
2583 23:06:54.963489 Dram Type= 6, Freq= 0, CH_0, rank 0
2584 23:06:54.970187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2585 23:06:54.970265 ==
2586 23:06:54.973571 Write leveling (Byte 0): 33 => 33
2587 23:06:54.976581 Write leveling (Byte 1): 32 => 32
2588 23:06:54.976656 DramcWriteLeveling(PI) end<-----
2589 23:06:54.980232
2590 23:06:54.980318 ==
2591 23:06:54.983580 Dram Type= 6, Freq= 0, CH_0, rank 0
2592 23:06:54.987167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2593 23:06:54.987243 ==
2594 23:06:54.990136 [Gating] SW mode calibration
2595 23:06:54.997184 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2596 23:06:55.000241 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2597 23:06:55.007020 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2598 23:06:55.010147 0 15 4 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
2599 23:06:55.013490 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2600 23:06:55.020287 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2601 23:06:55.023383 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2602 23:06:55.027055 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2603 23:06:55.033450 0 15 24 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
2604 23:06:55.037375 0 15 28 | B1->B0 | 3434 2424 | 0 0 | (0 0) (1 0)
2605 23:06:55.040238 1 0 0 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
2606 23:06:55.046909 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2607 23:06:55.050288 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2608 23:06:55.053527 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2609 23:06:55.060488 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2610 23:06:55.063697 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2611 23:06:55.066902 1 0 24 | B1->B0 | 2323 3939 | 0 1 | (0 0) (0 0)
2612 23:06:55.070309 1 0 28 | B1->B0 | 2726 4646 | 1 0 | (0 0) (0 0)
2613 23:06:55.076967 1 1 0 | B1->B0 | 3130 4646 | 1 0 | (0 0) (0 0)
2614 23:06:55.080030 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2615 23:06:55.083891 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2616 23:06:55.090495 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2617 23:06:55.093492 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2618 23:06:55.097316 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2619 23:06:55.103862 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2620 23:06:55.106873 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2621 23:06:55.110368 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2622 23:06:55.116861 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 23:06:55.120416 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 23:06:55.123929 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 23:06:55.130375 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 23:06:55.134037 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 23:06:55.137064 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2628 23:06:55.140722 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2629 23:06:55.147095 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2630 23:06:55.150884 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2631 23:06:55.154038 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2632 23:06:55.160739 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2633 23:06:55.164003 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2634 23:06:55.167441 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2635 23:06:55.173937 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2636 23:06:55.177492 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2637 23:06:55.180816 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2638 23:06:55.184061 Total UI for P1: 0, mck2ui 16
2639 23:06:55.187603 best dqsien dly found for B0: ( 1, 3, 26)
2640 23:06:55.194434 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2641 23:06:55.194520 Total UI for P1: 0, mck2ui 16
2642 23:06:55.197712 best dqsien dly found for B1: ( 1, 4, 0)
2643 23:06:55.201069 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2644 23:06:55.207490 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2645 23:06:55.207570
2646 23:06:55.211297 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2647 23:06:55.214278 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2648 23:06:55.217968 [Gating] SW calibration Done
2649 23:06:55.218053 ==
2650 23:06:55.221504 Dram Type= 6, Freq= 0, CH_0, rank 0
2651 23:06:55.224246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2652 23:06:55.224324 ==
2653 23:06:55.224389 RX Vref Scan: 0
2654 23:06:55.224450
2655 23:06:55.227532 RX Vref 0 -> 0, step: 1
2656 23:06:55.227604
2657 23:06:55.231049 RX Delay -40 -> 252, step: 8
2658 23:06:55.234202 iDelay=208, Bit 0, Center 123 (56 ~ 191) 136
2659 23:06:55.237778 iDelay=208, Bit 1, Center 123 (56 ~ 191) 136
2660 23:06:55.244968 iDelay=208, Bit 2, Center 119 (48 ~ 191) 144
2661 23:06:55.247575 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
2662 23:06:55.251248 iDelay=208, Bit 4, Center 127 (56 ~ 199) 144
2663 23:06:55.254817 iDelay=208, Bit 5, Center 115 (48 ~ 183) 136
2664 23:06:55.258160 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
2665 23:06:55.261397 iDelay=208, Bit 7, Center 127 (56 ~ 199) 144
2666 23:06:55.267673 iDelay=208, Bit 8, Center 103 (40 ~ 167) 128
2667 23:06:55.271103 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
2668 23:06:55.274487 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
2669 23:06:55.278338 iDelay=208, Bit 11, Center 107 (40 ~ 175) 136
2670 23:06:55.280951 iDelay=208, Bit 12, Center 115 (48 ~ 183) 136
2671 23:06:55.287924 iDelay=208, Bit 13, Center 115 (48 ~ 183) 136
2672 23:06:55.291353 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
2673 23:06:55.294368 iDelay=208, Bit 15, Center 115 (48 ~ 183) 136
2674 23:06:55.294499 ==
2675 23:06:55.297918 Dram Type= 6, Freq= 0, CH_0, rank 0
2676 23:06:55.301294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2677 23:06:55.301381 ==
2678 23:06:55.304481 DQS Delay:
2679 23:06:55.304559 DQS0 = 0, DQS1 = 0
2680 23:06:55.307793 DQM Delay:
2681 23:06:55.307881 DQM0 = 123, DQM1 = 110
2682 23:06:55.311471 DQ Delay:
2683 23:06:55.314536 DQ0 =123, DQ1 =123, DQ2 =119, DQ3 =119
2684 23:06:55.318083 DQ4 =127, DQ5 =115, DQ6 =131, DQ7 =127
2685 23:06:55.321090 DQ8 =103, DQ9 =99, DQ10 =107, DQ11 =107
2686 23:06:55.324704 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2687 23:06:55.324795
2688 23:06:55.324891
2689 23:06:55.324964 ==
2690 23:06:55.327663 Dram Type= 6, Freq= 0, CH_0, rank 0
2691 23:06:55.331142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2692 23:06:55.331214 ==
2693 23:06:55.331275
2694 23:06:55.331331
2695 23:06:55.334327 TX Vref Scan disable
2696 23:06:55.338099 == TX Byte 0 ==
2697 23:06:55.341044 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2698 23:06:55.344731 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2699 23:06:55.348130 == TX Byte 1 ==
2700 23:06:55.351129 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2701 23:06:55.354758 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2702 23:06:55.354828 ==
2703 23:06:55.358050 Dram Type= 6, Freq= 0, CH_0, rank 0
2704 23:06:55.361343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2705 23:06:55.361427 ==
2706 23:06:55.374532 TX Vref=22, minBit 2, minWin=23, winSum=399
2707 23:06:55.378172 TX Vref=24, minBit 3, minWin=24, winSum=402
2708 23:06:55.381752 TX Vref=26, minBit 0, minWin=25, winSum=410
2709 23:06:55.384566 TX Vref=28, minBit 0, minWin=25, winSum=417
2710 23:06:55.387988 TX Vref=30, minBit 0, minWin=25, winSum=413
2711 23:06:55.391015 TX Vref=32, minBit 1, minWin=25, winSum=411
2712 23:06:55.398097 [TxChooseVref] Worse bit 0, Min win 25, Win sum 417, Final Vref 28
2713 23:06:55.398188
2714 23:06:55.401025 Final TX Range 1 Vref 28
2715 23:06:55.401100
2716 23:06:55.401160 ==
2717 23:06:55.404627 Dram Type= 6, Freq= 0, CH_0, rank 0
2718 23:06:55.407851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2719 23:06:55.407954 ==
2720 23:06:55.408037
2721 23:06:55.408128
2722 23:06:55.411286 TX Vref Scan disable
2723 23:06:55.414831 == TX Byte 0 ==
2724 23:06:55.418086 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2725 23:06:55.421367 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2726 23:06:55.424815 == TX Byte 1 ==
2727 23:06:55.428083 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2728 23:06:55.431155 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2729 23:06:55.431240
2730 23:06:55.434874 [DATLAT]
2731 23:06:55.434958 Freq=1200, CH0 RK0
2732 23:06:55.435024
2733 23:06:55.437903 DATLAT Default: 0xd
2734 23:06:55.437987 0, 0xFFFF, sum = 0
2735 23:06:55.441600 1, 0xFFFF, sum = 0
2736 23:06:55.441727 2, 0xFFFF, sum = 0
2737 23:06:55.444571 3, 0xFFFF, sum = 0
2738 23:06:55.444661 4, 0xFFFF, sum = 0
2739 23:06:55.447809 5, 0xFFFF, sum = 0
2740 23:06:55.447933 6, 0xFFFF, sum = 0
2741 23:06:55.451486 7, 0xFFFF, sum = 0
2742 23:06:55.451594 8, 0xFFFF, sum = 0
2743 23:06:55.454380 9, 0xFFFF, sum = 0
2744 23:06:55.454521 10, 0xFFFF, sum = 0
2745 23:06:55.457811 11, 0xFFFF, sum = 0
2746 23:06:55.457916 12, 0x0, sum = 1
2747 23:06:55.461172 13, 0x0, sum = 2
2748 23:06:55.461276 14, 0x0, sum = 3
2749 23:06:55.464816 15, 0x0, sum = 4
2750 23:06:55.464919 best_step = 13
2751 23:06:55.465010
2752 23:06:55.465099 ==
2753 23:06:55.468264 Dram Type= 6, Freq= 0, CH_0, rank 0
2754 23:06:55.474617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2755 23:06:55.474785 ==
2756 23:06:55.474923 RX Vref Scan: 1
2757 23:06:55.475059
2758 23:06:55.477902 Set Vref Range= 32 -> 127
2759 23:06:55.478004
2760 23:06:55.481752 RX Vref 32 -> 127, step: 1
2761 23:06:55.481883
2762 23:06:55.481989 RX Delay -13 -> 252, step: 4
2763 23:06:55.484673
2764 23:06:55.484774 Set Vref, RX VrefLevel [Byte0]: 32
2765 23:06:55.487954 [Byte1]: 32
2766 23:06:55.492541
2767 23:06:55.492618 Set Vref, RX VrefLevel [Byte0]: 33
2768 23:06:55.496542 [Byte1]: 33
2769 23:06:55.500223
2770 23:06:55.500326 Set Vref, RX VrefLevel [Byte0]: 34
2771 23:06:55.503587 [Byte1]: 34
2772 23:06:55.508467
2773 23:06:55.508542 Set Vref, RX VrefLevel [Byte0]: 35
2774 23:06:55.511847 [Byte1]: 35
2775 23:06:55.516167
2776 23:06:55.516245 Set Vref, RX VrefLevel [Byte0]: 36
2777 23:06:55.519547 [Byte1]: 36
2778 23:06:55.524322
2779 23:06:55.524430 Set Vref, RX VrefLevel [Byte0]: 37
2780 23:06:55.527412 [Byte1]: 37
2781 23:06:55.532104
2782 23:06:55.532217 Set Vref, RX VrefLevel [Byte0]: 38
2783 23:06:55.535329 [Byte1]: 38
2784 23:06:55.539794
2785 23:06:55.539872 Set Vref, RX VrefLevel [Byte0]: 39
2786 23:06:55.543071 [Byte1]: 39
2787 23:06:55.547715
2788 23:06:55.547792 Set Vref, RX VrefLevel [Byte0]: 40
2789 23:06:55.551218 [Byte1]: 40
2790 23:06:55.555847
2791 23:06:55.555954 Set Vref, RX VrefLevel [Byte0]: 41
2792 23:06:55.559039 [Byte1]: 41
2793 23:06:55.563910
2794 23:06:55.563989 Set Vref, RX VrefLevel [Byte0]: 42
2795 23:06:55.566875 [Byte1]: 42
2796 23:06:55.571321
2797 23:06:55.571396 Set Vref, RX VrefLevel [Byte0]: 43
2798 23:06:55.574653 [Byte1]: 43
2799 23:06:55.579209
2800 23:06:55.579284 Set Vref, RX VrefLevel [Byte0]: 44
2801 23:06:55.582626 [Byte1]: 44
2802 23:06:55.587223
2803 23:06:55.587300 Set Vref, RX VrefLevel [Byte0]: 45
2804 23:06:55.590368 [Byte1]: 45
2805 23:06:55.595213
2806 23:06:55.595289 Set Vref, RX VrefLevel [Byte0]: 46
2807 23:06:55.598190 [Byte1]: 46
2808 23:06:55.602927
2809 23:06:55.603005 Set Vref, RX VrefLevel [Byte0]: 47
2810 23:06:55.606352 [Byte1]: 47
2811 23:06:55.610759
2812 23:06:55.610866 Set Vref, RX VrefLevel [Byte0]: 48
2813 23:06:55.614074 [Byte1]: 48
2814 23:06:55.618990
2815 23:06:55.619095 Set Vref, RX VrefLevel [Byte0]: 49
2816 23:06:55.622064 [Byte1]: 49
2817 23:06:55.626738
2818 23:06:55.626839 Set Vref, RX VrefLevel [Byte0]: 50
2819 23:06:55.630028 [Byte1]: 50
2820 23:06:55.634534
2821 23:06:55.634641 Set Vref, RX VrefLevel [Byte0]: 51
2822 23:06:55.637965 [Byte1]: 51
2823 23:06:55.642298
2824 23:06:55.642407 Set Vref, RX VrefLevel [Byte0]: 52
2825 23:06:55.645731 [Byte1]: 52
2826 23:06:55.650342
2827 23:06:55.650467 Set Vref, RX VrefLevel [Byte0]: 53
2828 23:06:55.653596 [Byte1]: 53
2829 23:06:55.658257
2830 23:06:55.658365 Set Vref, RX VrefLevel [Byte0]: 54
2831 23:06:55.661678 [Byte1]: 54
2832 23:06:55.666414
2833 23:06:55.666507 Set Vref, RX VrefLevel [Byte0]: 55
2834 23:06:55.669516 [Byte1]: 55
2835 23:06:55.674031
2836 23:06:55.674137 Set Vref, RX VrefLevel [Byte0]: 56
2837 23:06:55.677137 [Byte1]: 56
2838 23:06:55.682059
2839 23:06:55.682162 Set Vref, RX VrefLevel [Byte0]: 57
2840 23:06:55.685127 [Byte1]: 57
2841 23:06:55.689845
2842 23:06:55.689945 Set Vref, RX VrefLevel [Byte0]: 58
2843 23:06:55.693194 [Byte1]: 58
2844 23:06:55.697534
2845 23:06:55.697637 Set Vref, RX VrefLevel [Byte0]: 59
2846 23:06:55.701135 [Byte1]: 59
2847 23:06:55.705367
2848 23:06:55.705473 Set Vref, RX VrefLevel [Byte0]: 60
2849 23:06:55.708653 [Byte1]: 60
2850 23:06:55.713602
2851 23:06:55.713704 Set Vref, RX VrefLevel [Byte0]: 61
2852 23:06:55.716677 [Byte1]: 61
2853 23:06:55.721342
2854 23:06:55.721445 Set Vref, RX VrefLevel [Byte0]: 62
2855 23:06:55.724624 [Byte1]: 62
2856 23:06:55.729106
2857 23:06:55.729208 Set Vref, RX VrefLevel [Byte0]: 63
2858 23:06:55.732658 [Byte1]: 63
2859 23:06:55.737409
2860 23:06:55.737516 Set Vref, RX VrefLevel [Byte0]: 64
2861 23:06:55.740316 [Byte1]: 64
2862 23:06:55.745070
2863 23:06:55.745171 Set Vref, RX VrefLevel [Byte0]: 65
2864 23:06:55.748140 [Byte1]: 65
2865 23:06:55.753099
2866 23:06:55.753208 Set Vref, RX VrefLevel [Byte0]: 66
2867 23:06:55.756459 [Byte1]: 66
2868 23:06:55.760927
2869 23:06:55.761034 Set Vref, RX VrefLevel [Byte0]: 67
2870 23:06:55.764519 [Byte1]: 67
2871 23:06:55.768598
2872 23:06:55.768700 Set Vref, RX VrefLevel [Byte0]: 68
2873 23:06:55.772498 [Byte1]: 68
2874 23:06:55.776477
2875 23:06:55.776581 Set Vref, RX VrefLevel [Byte0]: 69
2876 23:06:55.780190 [Byte1]: 69
2877 23:06:55.784406
2878 23:06:55.784509 Final RX Vref Byte 0 = 57 to rank0
2879 23:06:55.788107 Final RX Vref Byte 1 = 50 to rank0
2880 23:06:55.791385 Final RX Vref Byte 0 = 57 to rank1
2881 23:06:55.794640 Final RX Vref Byte 1 = 50 to rank1==
2882 23:06:55.797870 Dram Type= 6, Freq= 0, CH_0, rank 0
2883 23:06:55.804532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2884 23:06:55.804637 ==
2885 23:06:55.804734 DQS Delay:
2886 23:06:55.804827 DQS0 = 0, DQS1 = 0
2887 23:06:55.807996 DQM Delay:
2888 23:06:55.808071 DQM0 = 123, DQM1 = 109
2889 23:06:55.811230 DQ Delay:
2890 23:06:55.814281 DQ0 =122, DQ1 =122, DQ2 =118, DQ3 =120
2891 23:06:55.817941 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =130
2892 23:06:55.821261 DQ8 =102, DQ9 =94, DQ10 =110, DQ11 =106
2893 23:06:55.825009 DQ12 =116, DQ13 =110, DQ14 =122, DQ15 =116
2894 23:06:55.825132
2895 23:06:55.825229
2896 23:06:55.830863 [DQSOSCAuto] RK0, (LSB)MR18= 0x704, (MSB)MR19= 0x404, tDQSOscB0 = 408 ps tDQSOscB1 = 407 ps
2897 23:06:55.834560 CH0 RK0: MR19=404, MR18=704
2898 23:06:55.841218 CH0_RK0: MR19=0x404, MR18=0x704, DQSOSC=407, MR23=63, INC=39, DEC=26
2899 23:06:55.841332
2900 23:06:55.844128 ----->DramcWriteLeveling(PI) begin...
2901 23:06:55.844233 ==
2902 23:06:55.847713 Dram Type= 6, Freq= 0, CH_0, rank 1
2903 23:06:55.851120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2904 23:06:55.851229 ==
2905 23:06:55.854468 Write leveling (Byte 0): 34 => 34
2906 23:06:55.858114 Write leveling (Byte 1): 30 => 30
2907 23:06:55.861159 DramcWriteLeveling(PI) end<-----
2908 23:06:55.861270
2909 23:06:55.861374 ==
2910 23:06:55.864199 Dram Type= 6, Freq= 0, CH_0, rank 1
2911 23:06:55.871102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2912 23:06:55.871207 ==
2913 23:06:55.871306 [Gating] SW mode calibration
2914 23:06:55.880826 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2915 23:06:55.884354 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2916 23:06:55.887908 0 15 0 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
2917 23:06:55.894058 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2918 23:06:55.897691 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2919 23:06:55.900905 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2920 23:06:55.907515 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2921 23:06:55.910779 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2922 23:06:55.914092 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2923 23:06:55.921040 0 15 28 | B1->B0 | 2d2d 2929 | 0 0 | (0 0) (1 0)
2924 23:06:55.924175 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
2925 23:06:55.927660 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2926 23:06:55.934105 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2927 23:06:55.937567 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2928 23:06:55.940869 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2929 23:06:55.947655 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2930 23:06:55.950926 1 0 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
2931 23:06:55.954121 1 0 28 | B1->B0 | 3737 4141 | 1 0 | (0 0) (0 0)
2932 23:06:55.961123 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2933 23:06:55.964270 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2934 23:06:55.967514 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2935 23:06:55.970871 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2936 23:06:55.977730 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2937 23:06:55.981199 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2938 23:06:55.984112 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2939 23:06:55.991279 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2940 23:06:55.994567 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2941 23:06:55.997664 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2942 23:06:56.004337 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2943 23:06:56.008149 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2944 23:06:56.011150 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2945 23:06:56.017993 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2946 23:06:56.021131 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2947 23:06:56.025049 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2948 23:06:56.030963 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2949 23:06:56.034380 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2950 23:06:56.037800 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2951 23:06:56.044464 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2952 23:06:56.047653 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2953 23:06:56.051156 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2954 23:06:56.054601 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2955 23:06:56.061117 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2956 23:06:56.064496 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2957 23:06:56.067831 Total UI for P1: 0, mck2ui 16
2958 23:06:56.070994 best dqsien dly found for B0: ( 1, 3, 28)
2959 23:06:56.074361 Total UI for P1: 0, mck2ui 16
2960 23:06:56.078078 best dqsien dly found for B1: ( 1, 3, 28)
2961 23:06:56.081581 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2962 23:06:56.084737 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2963 23:06:56.084841
2964 23:06:56.087784 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2965 23:06:56.091186 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2966 23:06:56.094717 [Gating] SW calibration Done
2967 23:06:56.094793 ==
2968 23:06:56.098031 Dram Type= 6, Freq= 0, CH_0, rank 1
2969 23:06:56.101439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2970 23:06:56.104457 ==
2971 23:06:56.104558 RX Vref Scan: 0
2972 23:06:56.104653
2973 23:06:56.108069 RX Vref 0 -> 0, step: 1
2974 23:06:56.108169
2975 23:06:56.111571 RX Delay -40 -> 252, step: 8
2976 23:06:56.114342 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2977 23:06:56.117882 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2978 23:06:56.121284 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2979 23:06:56.124580 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2980 23:06:56.131499 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2981 23:06:56.134550 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2982 23:06:56.138036 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2983 23:06:56.141432 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2984 23:06:56.144795 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2985 23:06:56.147794 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2986 23:06:56.154481 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2987 23:06:56.158288 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2988 23:06:56.161483 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2989 23:06:56.164936 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2990 23:06:56.168154 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2991 23:06:56.174883 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2992 23:06:56.174971 ==
2993 23:06:56.178111 Dram Type= 6, Freq= 0, CH_0, rank 1
2994 23:06:56.181469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2995 23:06:56.181549 ==
2996 23:06:56.181612 DQS Delay:
2997 23:06:56.185226 DQS0 = 0, DQS1 = 0
2998 23:06:56.185326 DQM Delay:
2999 23:06:56.188227 DQM0 = 120, DQM1 = 108
3000 23:06:56.188326 DQ Delay:
3001 23:06:56.191555 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
3002 23:06:56.194997 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
3003 23:06:56.198098 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
3004 23:06:56.201544 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
3005 23:06:56.201646
3006 23:06:56.201741
3007 23:06:56.204964 ==
3008 23:06:56.205063 Dram Type= 6, Freq= 0, CH_0, rank 1
3009 23:06:56.211425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3010 23:06:56.211529 ==
3011 23:06:56.211625
3012 23:06:56.211716
3013 23:06:56.214810 TX Vref Scan disable
3014 23:06:56.214911 == TX Byte 0 ==
3015 23:06:56.218167 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3016 23:06:56.224909 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3017 23:06:56.225012 == TX Byte 1 ==
3018 23:06:56.228095 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3019 23:06:56.234939 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3020 23:06:56.235015 ==
3021 23:06:56.238341 Dram Type= 6, Freq= 0, CH_0, rank 1
3022 23:06:56.241580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3023 23:06:56.241682 ==
3024 23:06:56.253404 TX Vref=22, minBit 3, minWin=23, winSum=406
3025 23:06:56.257626 TX Vref=24, minBit 4, minWin=24, winSum=409
3026 23:06:56.260581 TX Vref=26, minBit 0, minWin=24, winSum=411
3027 23:06:56.263969 TX Vref=28, minBit 3, minWin=24, winSum=412
3028 23:06:56.266953 TX Vref=30, minBit 7, minWin=24, winSum=416
3029 23:06:56.270318 TX Vref=32, minBit 0, minWin=25, winSum=415
3030 23:06:56.276900 [TxChooseVref] Worse bit 0, Min win 25, Win sum 415, Final Vref 32
3031 23:06:56.277004
3032 23:06:56.280803 Final TX Range 1 Vref 32
3033 23:06:56.280910
3034 23:06:56.281006 ==
3035 23:06:56.283657 Dram Type= 6, Freq= 0, CH_0, rank 1
3036 23:06:56.287033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3037 23:06:56.287144 ==
3038 23:06:56.287236
3039 23:06:56.287336
3040 23:06:56.290156 TX Vref Scan disable
3041 23:06:56.293656 == TX Byte 0 ==
3042 23:06:56.296828 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3043 23:06:56.300072 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3044 23:06:56.303483 == TX Byte 1 ==
3045 23:06:56.306945 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3046 23:06:56.310022 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3047 23:06:56.310129
3048 23:06:56.313250 [DATLAT]
3049 23:06:56.313349 Freq=1200, CH0 RK1
3050 23:06:56.313439
3051 23:06:56.316902 DATLAT Default: 0xd
3052 23:06:56.317001 0, 0xFFFF, sum = 0
3053 23:06:56.320168 1, 0xFFFF, sum = 0
3054 23:06:56.320243 2, 0xFFFF, sum = 0
3055 23:06:56.323463 3, 0xFFFF, sum = 0
3056 23:06:56.323567 4, 0xFFFF, sum = 0
3057 23:06:56.326536 5, 0xFFFF, sum = 0
3058 23:06:56.330513 6, 0xFFFF, sum = 0
3059 23:06:56.330591 7, 0xFFFF, sum = 0
3060 23:06:56.333106 8, 0xFFFF, sum = 0
3061 23:06:56.333205 9, 0xFFFF, sum = 0
3062 23:06:56.336402 10, 0xFFFF, sum = 0
3063 23:06:56.336519 11, 0xFFFF, sum = 0
3064 23:06:56.340321 12, 0x0, sum = 1
3065 23:06:56.340461 13, 0x0, sum = 2
3066 23:06:56.343287 14, 0x0, sum = 3
3067 23:06:56.343390 15, 0x0, sum = 4
3068 23:06:56.343482 best_step = 13
3069 23:06:56.343572
3070 23:06:56.346538 ==
3071 23:06:56.350063 Dram Type= 6, Freq= 0, CH_0, rank 1
3072 23:06:56.353515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3073 23:06:56.353614 ==
3074 23:06:56.353705 RX Vref Scan: 0
3075 23:06:56.353831
3076 23:06:56.356739 RX Vref 0 -> 0, step: 1
3077 23:06:56.356857
3078 23:06:56.360174 RX Delay -21 -> 252, step: 4
3079 23:06:56.363467 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3080 23:06:56.370237 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3081 23:06:56.373843 iDelay=195, Bit 2, Center 116 (51 ~ 182) 132
3082 23:06:56.376752 iDelay=195, Bit 3, Center 114 (51 ~ 178) 128
3083 23:06:56.380356 iDelay=195, Bit 4, Center 120 (55 ~ 186) 132
3084 23:06:56.383444 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3085 23:06:56.387194 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3086 23:06:56.393970 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3087 23:06:56.397005 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3088 23:06:56.400226 iDelay=195, Bit 9, Center 94 (31 ~ 158) 128
3089 23:06:56.403487 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3090 23:06:56.406700 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3091 23:06:56.413846 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3092 23:06:56.417365 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3093 23:06:56.420397 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3094 23:06:56.423678 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3095 23:06:56.423877 ==
3096 23:06:56.426990 Dram Type= 6, Freq= 0, CH_0, rank 1
3097 23:06:56.433823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3098 23:06:56.434052 ==
3099 23:06:56.434178 DQS Delay:
3100 23:06:56.436757 DQS0 = 0, DQS1 = 0
3101 23:06:56.436928 DQM Delay:
3102 23:06:56.437055 DQM0 = 119, DQM1 = 107
3103 23:06:56.440024 DQ Delay:
3104 23:06:56.443538 DQ0 =118, DQ1 =122, DQ2 =116, DQ3 =114
3105 23:06:56.446983 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =126
3106 23:06:56.450309 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =106
3107 23:06:56.453524 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =114
3108 23:06:56.453785
3109 23:06:56.453991
3110 23:06:56.460299 [DQSOSCAuto] RK1, (LSB)MR18= 0xff6, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 404 ps
3111 23:06:56.463878 CH0 RK1: MR19=403, MR18=FF6
3112 23:06:56.470701 CH0_RK1: MR19=0x403, MR18=0xFF6, DQSOSC=404, MR23=63, INC=40, DEC=26
3113 23:06:56.474143 [RxdqsGatingPostProcess] freq 1200
3114 23:06:56.480384 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3115 23:06:56.483716 best DQS0 dly(2T, 0.5T) = (0, 11)
3116 23:06:56.484384 best DQS1 dly(2T, 0.5T) = (0, 12)
3117 23:06:56.487271 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3118 23:06:56.490740 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3119 23:06:56.494211 best DQS0 dly(2T, 0.5T) = (0, 11)
3120 23:06:56.497354 best DQS1 dly(2T, 0.5T) = (0, 11)
3121 23:06:56.500447 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3122 23:06:56.504322 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3123 23:06:56.507426 Pre-setting of DQS Precalculation
3124 23:06:56.510782 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3125 23:06:56.513992 ==
3126 23:06:56.517481 Dram Type= 6, Freq= 0, CH_1, rank 0
3127 23:06:56.520926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3128 23:06:56.521404 ==
3129 23:06:56.524013 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3130 23:06:56.531265 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3131 23:06:56.539520 [CA 0] Center 37 (7~68) winsize 62
3132 23:06:56.542707 [CA 1] Center 37 (7~68) winsize 62
3133 23:06:56.546362 [CA 2] Center 34 (4~65) winsize 62
3134 23:06:56.549561 [CA 3] Center 33 (3~64) winsize 62
3135 23:06:56.552950 [CA 4] Center 33 (3~64) winsize 62
3136 23:06:56.556249 [CA 5] Center 33 (3~63) winsize 61
3137 23:06:56.556383
3138 23:06:56.559392 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3139 23:06:56.559522
3140 23:06:56.562959 [CATrainingPosCal] consider 1 rank data
3141 23:06:56.566153 u2DelayCellTimex100 = 270/100 ps
3142 23:06:56.569612 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3143 23:06:56.572710 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3144 23:06:56.579579 CA2 delay=34 (4~65),Diff = 1 PI (4 cell)
3145 23:06:56.583607 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3146 23:06:56.586421 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3147 23:06:56.589789 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3148 23:06:56.589907
3149 23:06:56.592907 CA PerBit enable=1, Macro0, CA PI delay=33
3150 23:06:56.593031
3151 23:06:56.596112 [CBTSetCACLKResult] CA Dly = 33
3152 23:06:56.596276 CS Dly: 5 (0~36)
3153 23:06:56.596387 ==
3154 23:06:56.599708 Dram Type= 6, Freq= 0, CH_1, rank 1
3155 23:06:56.606648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3156 23:06:56.606825 ==
3157 23:06:56.609773 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3158 23:06:56.616718 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3159 23:06:56.625624 [CA 0] Center 38 (8~68) winsize 61
3160 23:06:56.629225 [CA 1] Center 37 (7~68) winsize 62
3161 23:06:56.632286 [CA 2] Center 35 (4~66) winsize 63
3162 23:06:56.635515 [CA 3] Center 34 (4~65) winsize 62
3163 23:06:56.638546 [CA 4] Center 34 (4~64) winsize 61
3164 23:06:56.642454 [CA 5] Center 33 (3~63) winsize 61
3165 23:06:56.642933
3166 23:06:56.645997 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3167 23:06:56.646612
3168 23:06:56.649177 [CATrainingPosCal] consider 2 rank data
3169 23:06:56.652371 u2DelayCellTimex100 = 270/100 ps
3170 23:06:56.655719 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3171 23:06:56.658826 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3172 23:06:56.666242 CA2 delay=34 (4~65),Diff = 1 PI (4 cell)
3173 23:06:56.669101 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3174 23:06:56.672619 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3175 23:06:56.675419 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3176 23:06:56.675901
3177 23:06:56.678715 CA PerBit enable=1, Macro0, CA PI delay=33
3178 23:06:56.679193
3179 23:06:56.682351 [CBTSetCACLKResult] CA Dly = 33
3180 23:06:56.682884 CS Dly: 6 (0~38)
3181 23:06:56.683262
3182 23:06:56.686094 ----->DramcWriteLeveling(PI) begin...
3183 23:06:56.686614 ==
3184 23:06:56.688869 Dram Type= 6, Freq= 0, CH_1, rank 0
3185 23:06:56.695243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3186 23:06:56.695903 ==
3187 23:06:56.698773 Write leveling (Byte 0): 23 => 23
3188 23:06:56.702330 Write leveling (Byte 1): 28 => 28
3189 23:06:56.702838 DramcWriteLeveling(PI) end<-----
3190 23:06:56.705515
3191 23:06:56.705979 ==
3192 23:06:56.709099 Dram Type= 6, Freq= 0, CH_1, rank 0
3193 23:06:56.712685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3194 23:06:56.713262 ==
3195 23:06:56.716115 [Gating] SW mode calibration
3196 23:06:56.722256 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3197 23:06:56.725876 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3198 23:06:56.732856 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3199 23:06:56.735908 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3200 23:06:56.738941 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3201 23:06:56.746010 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3202 23:06:56.748893 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3203 23:06:56.752215 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3204 23:06:56.758878 0 15 24 | B1->B0 | 2d2d 2626 | 0 0 | (0 1) (0 1)
3205 23:06:56.762261 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3206 23:06:56.765465 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3207 23:06:56.772140 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3208 23:06:56.775979 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3209 23:06:56.778736 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3210 23:06:56.785978 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3211 23:06:56.789177 1 0 20 | B1->B0 | 2525 2525 | 0 0 | (0 0) (0 0)
3212 23:06:56.792699 1 0 24 | B1->B0 | 3e3e 4646 | 1 0 | (0 0) (0 0)
3213 23:06:56.795866 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3214 23:06:56.802506 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3215 23:06:56.805813 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3216 23:06:56.809420 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3217 23:06:56.815706 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3218 23:06:56.819278 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3219 23:06:56.822498 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3220 23:06:56.829002 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3221 23:06:56.832590 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3222 23:06:56.836032 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3223 23:06:56.842716 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3224 23:06:56.845922 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3225 23:06:56.849344 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3226 23:06:56.855876 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3227 23:06:56.859387 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3228 23:06:56.862420 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3229 23:06:56.869156 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3230 23:06:56.872416 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3231 23:06:56.875735 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3232 23:06:56.879042 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3233 23:06:56.885632 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3234 23:06:56.889050 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3235 23:06:56.892701 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3236 23:06:56.899209 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3237 23:06:56.902255 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3238 23:06:56.905675 Total UI for P1: 0, mck2ui 16
3239 23:06:56.909170 best dqsien dly found for B0: ( 1, 3, 22)
3240 23:06:56.912323 Total UI for P1: 0, mck2ui 16
3241 23:06:56.915970 best dqsien dly found for B1: ( 1, 3, 24)
3242 23:06:56.919670 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3243 23:06:56.922837 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3244 23:06:56.923316
3245 23:06:56.926482 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3246 23:06:56.929250 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3247 23:06:56.932769 [Gating] SW calibration Done
3248 23:06:56.933341 ==
3249 23:06:56.935878 Dram Type= 6, Freq= 0, CH_1, rank 0
3250 23:06:56.939185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3251 23:06:56.943118 ==
3252 23:06:56.943595 RX Vref Scan: 0
3253 23:06:56.943973
3254 23:06:56.945879 RX Vref 0 -> 0, step: 1
3255 23:06:56.946356
3256 23:06:56.949389 RX Delay -40 -> 252, step: 8
3257 23:06:56.952411 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3258 23:06:56.956204 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3259 23:06:56.958925 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3260 23:06:56.962639 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3261 23:06:56.968992 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3262 23:06:56.972627 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3263 23:06:56.975616 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3264 23:06:56.979379 iDelay=200, Bit 7, Center 119 (56 ~ 183) 128
3265 23:06:56.982454 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3266 23:06:56.985871 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3267 23:06:56.992482 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3268 23:06:56.995843 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3269 23:06:56.999025 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3270 23:06:57.002477 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3271 23:06:57.005642 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3272 23:06:57.012477 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3273 23:06:57.013061 ==
3274 23:06:57.015877 Dram Type= 6, Freq= 0, CH_1, rank 0
3275 23:06:57.019410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3276 23:06:57.019899 ==
3277 23:06:57.020272 DQS Delay:
3278 23:06:57.022829 DQS0 = 0, DQS1 = 0
3279 23:06:57.023482 DQM Delay:
3280 23:06:57.026136 DQM0 = 120, DQM1 = 113
3281 23:06:57.026718 DQ Delay:
3282 23:06:57.029407 DQ0 =123, DQ1 =115, DQ2 =111, DQ3 =123
3283 23:06:57.032671 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =119
3284 23:06:57.036010 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3285 23:06:57.039308 DQ12 =123, DQ13 =123, DQ14 =119, DQ15 =119
3286 23:06:57.039784
3287 23:06:57.040151
3288 23:06:57.042695 ==
3289 23:06:57.043187 Dram Type= 6, Freq= 0, CH_1, rank 0
3290 23:06:57.049612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3291 23:06:57.050088 ==
3292 23:06:57.050507
3293 23:06:57.050867
3294 23:06:57.053102 TX Vref Scan disable
3295 23:06:57.053577 == TX Byte 0 ==
3296 23:06:57.056550 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3297 23:06:57.062555 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3298 23:06:57.063036 == TX Byte 1 ==
3299 23:06:57.066028 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3300 23:06:57.072758 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3301 23:06:57.073234 ==
3302 23:06:57.076472 Dram Type= 6, Freq= 0, CH_1, rank 0
3303 23:06:57.079437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3304 23:06:57.079941 ==
3305 23:06:57.091507 TX Vref=22, minBit 10, minWin=23, winSum=400
3306 23:06:57.094466 TX Vref=24, minBit 1, minWin=24, winSum=402
3307 23:06:57.098255 TX Vref=26, minBit 3, minWin=24, winSum=409
3308 23:06:57.101168 TX Vref=28, minBit 8, minWin=25, winSum=417
3309 23:06:57.104663 TX Vref=30, minBit 8, minWin=25, winSum=417
3310 23:06:57.107887 TX Vref=32, minBit 9, minWin=25, winSum=418
3311 23:06:57.114806 [TxChooseVref] Worse bit 9, Min win 25, Win sum 418, Final Vref 32
3312 23:06:57.115369
3313 23:06:57.117977 Final TX Range 1 Vref 32
3314 23:06:57.118572
3315 23:06:57.119023 ==
3316 23:06:57.121285 Dram Type= 6, Freq= 0, CH_1, rank 0
3317 23:06:57.124575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3318 23:06:57.125080 ==
3319 23:06:57.125451
3320 23:06:57.127929
3321 23:06:57.128498 TX Vref Scan disable
3322 23:06:57.131376 == TX Byte 0 ==
3323 23:06:57.134513 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3324 23:06:57.138064 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3325 23:06:57.141540 == TX Byte 1 ==
3326 23:06:57.144901 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3327 23:06:57.148502 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3328 23:06:57.148974
3329 23:06:57.151342 [DATLAT]
3330 23:06:57.151815 Freq=1200, CH1 RK0
3331 23:06:57.152188
3332 23:06:57.154958 DATLAT Default: 0xd
3333 23:06:57.155428 0, 0xFFFF, sum = 0
3334 23:06:57.158356 1, 0xFFFF, sum = 0
3335 23:06:57.158880 2, 0xFFFF, sum = 0
3336 23:06:57.161646 3, 0xFFFF, sum = 0
3337 23:06:57.162122 4, 0xFFFF, sum = 0
3338 23:06:57.164620 5, 0xFFFF, sum = 0
3339 23:06:57.165095 6, 0xFFFF, sum = 0
3340 23:06:57.167820 7, 0xFFFF, sum = 0
3341 23:06:57.168295 8, 0xFFFF, sum = 0
3342 23:06:57.171547 9, 0xFFFF, sum = 0
3343 23:06:57.172135 10, 0xFFFF, sum = 0
3344 23:06:57.174948 11, 0xFFFF, sum = 0
3345 23:06:57.175428 12, 0x0, sum = 1
3346 23:06:57.178076 13, 0x0, sum = 2
3347 23:06:57.178578 14, 0x0, sum = 3
3348 23:06:57.181441 15, 0x0, sum = 4
3349 23:06:57.181915 best_step = 13
3350 23:06:57.182284
3351 23:06:57.182683 ==
3352 23:06:57.184742 Dram Type= 6, Freq= 0, CH_1, rank 0
3353 23:06:57.191500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3354 23:06:57.192081 ==
3355 23:06:57.192457 RX Vref Scan: 1
3356 23:06:57.192802
3357 23:06:57.194596 Set Vref Range= 32 -> 127
3358 23:06:57.195066
3359 23:06:57.197816 RX Vref 32 -> 127, step: 1
3360 23:06:57.198301
3361 23:06:57.201447 RX Delay -13 -> 252, step: 4
3362 23:06:57.202044
3363 23:06:57.204967 Set Vref, RX VrefLevel [Byte0]: 32
3364 23:06:57.207898 [Byte1]: 32
3365 23:06:57.208377
3366 23:06:57.211496 Set Vref, RX VrefLevel [Byte0]: 33
3367 23:06:57.214846 [Byte1]: 33
3368 23:06:57.215372
3369 23:06:57.218172 Set Vref, RX VrefLevel [Byte0]: 34
3370 23:06:57.221441 [Byte1]: 34
3371 23:06:57.225864
3372 23:06:57.226381 Set Vref, RX VrefLevel [Byte0]: 35
3373 23:06:57.228330 [Byte1]: 35
3374 23:06:57.233116
3375 23:06:57.233745 Set Vref, RX VrefLevel [Byte0]: 36
3376 23:06:57.236382 [Byte1]: 36
3377 23:06:57.240697
3378 23:06:57.241155 Set Vref, RX VrefLevel [Byte0]: 37
3379 23:06:57.244648 [Byte1]: 37
3380 23:06:57.248741
3381 23:06:57.249318 Set Vref, RX VrefLevel [Byte0]: 38
3382 23:06:57.251981 [Byte1]: 38
3383 23:06:57.256534
3384 23:06:57.257145 Set Vref, RX VrefLevel [Byte0]: 39
3385 23:06:57.260333 [Byte1]: 39
3386 23:06:57.264613
3387 23:06:57.265089 Set Vref, RX VrefLevel [Byte0]: 40
3388 23:06:57.267884 [Byte1]: 40
3389 23:06:57.272762
3390 23:06:57.273082 Set Vref, RX VrefLevel [Byte0]: 41
3391 23:06:57.276281 [Byte1]: 41
3392 23:06:57.280941
3393 23:06:57.281259 Set Vref, RX VrefLevel [Byte0]: 42
3394 23:06:57.283711 [Byte1]: 42
3395 23:06:57.288237
3396 23:06:57.288555 Set Vref, RX VrefLevel [Byte0]: 43
3397 23:06:57.291860 [Byte1]: 43
3398 23:06:57.297133
3399 23:06:57.297556 Set Vref, RX VrefLevel [Byte0]: 44
3400 23:06:57.299694 [Byte1]: 44
3401 23:06:57.304068
3402 23:06:57.304389 Set Vref, RX VrefLevel [Byte0]: 45
3403 23:06:57.307865 [Byte1]: 45
3404 23:06:57.312331
3405 23:06:57.312845 Set Vref, RX VrefLevel [Byte0]: 46
3406 23:06:57.318786 [Byte1]: 46
3407 23:06:57.319372
3408 23:06:57.322156 Set Vref, RX VrefLevel [Byte0]: 47
3409 23:06:57.325346 [Byte1]: 47
3410 23:06:57.325907
3411 23:06:57.328642 Set Vref, RX VrefLevel [Byte0]: 48
3412 23:06:57.331799 [Byte1]: 48
3413 23:06:57.335624
3414 23:06:57.336080 Set Vref, RX VrefLevel [Byte0]: 49
3415 23:06:57.339023 [Byte1]: 49
3416 23:06:57.343690
3417 23:06:57.344224 Set Vref, RX VrefLevel [Byte0]: 50
3418 23:06:57.346823 [Byte1]: 50
3419 23:06:57.351762
3420 23:06:57.352221 Set Vref, RX VrefLevel [Byte0]: 51
3421 23:06:57.354903 [Byte1]: 51
3422 23:06:57.359433
3423 23:06:57.359964 Set Vref, RX VrefLevel [Byte0]: 52
3424 23:06:57.362750 [Byte1]: 52
3425 23:06:57.367300
3426 23:06:57.367757 Set Vref, RX VrefLevel [Byte0]: 53
3427 23:06:57.370701 [Byte1]: 53
3428 23:06:57.375069
3429 23:06:57.375559 Set Vref, RX VrefLevel [Byte0]: 54
3430 23:06:57.378351 [Byte1]: 54
3431 23:06:57.382968
3432 23:06:57.383483 Set Vref, RX VrefLevel [Byte0]: 55
3433 23:06:57.386297 [Byte1]: 55
3434 23:06:57.391095
3435 23:06:57.391662 Set Vref, RX VrefLevel [Byte0]: 56
3436 23:06:57.394704 [Byte1]: 56
3437 23:06:57.399246
3438 23:06:57.399814 Set Vref, RX VrefLevel [Byte0]: 57
3439 23:06:57.401976 [Byte1]: 57
3440 23:06:57.407011
3441 23:06:57.407610 Set Vref, RX VrefLevel [Byte0]: 58
3442 23:06:57.410227 [Byte1]: 58
3443 23:06:57.414671
3444 23:06:57.415145 Set Vref, RX VrefLevel [Byte0]: 59
3445 23:06:57.418430 [Byte1]: 59
3446 23:06:57.422477
3447 23:06:57.423049 Set Vref, RX VrefLevel [Byte0]: 60
3448 23:06:57.426727 [Byte1]: 60
3449 23:06:57.430934
3450 23:06:57.431497 Set Vref, RX VrefLevel [Byte0]: 61
3451 23:06:57.434076 [Byte1]: 61
3452 23:06:57.439134
3453 23:06:57.439732 Set Vref, RX VrefLevel [Byte0]: 62
3454 23:06:57.441819 [Byte1]: 62
3455 23:06:57.446475
3456 23:06:57.446949 Set Vref, RX VrefLevel [Byte0]: 63
3457 23:06:57.449476 [Byte1]: 63
3458 23:06:57.454052
3459 23:06:57.454580 Set Vref, RX VrefLevel [Byte0]: 64
3460 23:06:57.457384 [Byte1]: 64
3461 23:06:57.461940
3462 23:06:57.462452 Set Vref, RX VrefLevel [Byte0]: 65
3463 23:06:57.465503 [Byte1]: 65
3464 23:06:57.469749
3465 23:06:57.470340 Set Vref, RX VrefLevel [Byte0]: 66
3466 23:06:57.473395 [Byte1]: 66
3467 23:06:57.477582
3468 23:06:57.478058 Set Vref, RX VrefLevel [Byte0]: 67
3469 23:06:57.481005 [Byte1]: 67
3470 23:06:57.485504
3471 23:06:57.485979 Final RX Vref Byte 0 = 54 to rank0
3472 23:06:57.489032 Final RX Vref Byte 1 = 54 to rank0
3473 23:06:57.492052 Final RX Vref Byte 0 = 54 to rank1
3474 23:06:57.495549 Final RX Vref Byte 1 = 54 to rank1==
3475 23:06:57.498789 Dram Type= 6, Freq= 0, CH_1, rank 0
3476 23:06:57.505461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3477 23:06:57.505547 ==
3478 23:06:57.505616 DQS Delay:
3479 23:06:57.505679 DQS0 = 0, DQS1 = 0
3480 23:06:57.508534 DQM Delay:
3481 23:06:57.508607 DQM0 = 119, DQM1 = 112
3482 23:06:57.511964 DQ Delay:
3483 23:06:57.515194 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =118
3484 23:06:57.518823 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =118
3485 23:06:57.522014 DQ8 =102, DQ9 =100, DQ10 =114, DQ11 =106
3486 23:06:57.525267 DQ12 =122, DQ13 =118, DQ14 =120, DQ15 =118
3487 23:06:57.525369
3488 23:06:57.525440
3489 23:06:57.531980 [DQSOSCAuto] RK0, (LSB)MR18= 0x518, (MSB)MR19= 0x404, tDQSOscB0 = 400 ps tDQSOscB1 = 408 ps
3490 23:06:57.535320 CH1 RK0: MR19=404, MR18=518
3491 23:06:57.542080 CH1_RK0: MR19=0x404, MR18=0x518, DQSOSC=400, MR23=63, INC=40, DEC=27
3492 23:06:57.542196
3493 23:06:57.546081 ----->DramcWriteLeveling(PI) begin...
3494 23:06:57.546614 ==
3495 23:06:57.549303 Dram Type= 6, Freq= 0, CH_1, rank 1
3496 23:06:57.552462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3497 23:06:57.552944 ==
3498 23:06:57.555666 Write leveling (Byte 0): 26 => 26
3499 23:06:57.559232 Write leveling (Byte 1): 28 => 28
3500 23:06:57.562901 DramcWriteLeveling(PI) end<-----
3501 23:06:57.563430
3502 23:06:57.564014 ==
3503 23:06:57.565868 Dram Type= 6, Freq= 0, CH_1, rank 1
3504 23:06:57.569381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3505 23:06:57.572510 ==
3506 23:06:57.572999 [Gating] SW mode calibration
3507 23:06:57.579839 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3508 23:06:57.586140 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3509 23:06:57.589635 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3510 23:06:57.596122 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3511 23:06:57.599425 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3512 23:06:57.603048 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3513 23:06:57.610513 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3514 23:06:57.613120 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3515 23:06:57.616486 0 15 24 | B1->B0 | 2626 3232 | 0 1 | (0 0) (1 0)
3516 23:06:57.619743 0 15 28 | B1->B0 | 2323 2c2c | 0 1 | (1 0) (1 0)
3517 23:06:57.626228 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3518 23:06:57.629733 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3519 23:06:57.632826 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3520 23:06:57.639944 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3521 23:06:57.642850 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3522 23:06:57.646381 1 0 20 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
3523 23:06:57.652851 1 0 24 | B1->B0 | 3a3a 2e2e | 0 0 | (0 0) (1 1)
3524 23:06:57.656370 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3525 23:06:57.659325 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3526 23:06:57.666228 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3527 23:06:57.669623 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3528 23:06:57.673011 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3529 23:06:57.679758 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3530 23:06:57.683045 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3531 23:06:57.686145 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3532 23:06:57.692754 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3533 23:06:57.696006 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3534 23:06:57.699570 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3535 23:06:57.706203 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3536 23:06:57.709927 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3537 23:06:57.712841 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3538 23:06:57.719201 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3539 23:06:57.722885 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3540 23:06:57.726435 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3541 23:06:57.729874 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3542 23:06:57.736004 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3543 23:06:57.739494 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3544 23:06:57.742557 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3545 23:06:57.749849 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3546 23:06:57.752726 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3547 23:06:57.756678 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3548 23:06:57.762808 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3549 23:06:57.765820 Total UI for P1: 0, mck2ui 16
3550 23:06:57.769535 best dqsien dly found for B0: ( 1, 3, 24)
3551 23:06:57.770012 Total UI for P1: 0, mck2ui 16
3552 23:06:57.775935 best dqsien dly found for B1: ( 1, 3, 24)
3553 23:06:57.779394 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3554 23:06:57.782494 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3555 23:06:57.783182
3556 23:06:57.785943 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3557 23:06:57.789198 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3558 23:06:57.792943 [Gating] SW calibration Done
3559 23:06:57.793424 ==
3560 23:06:57.795958 Dram Type= 6, Freq= 0, CH_1, rank 1
3561 23:06:57.799292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3562 23:06:57.799773 ==
3563 23:06:57.802600 RX Vref Scan: 0
3564 23:06:57.803079
3565 23:06:57.803555 RX Vref 0 -> 0, step: 1
3566 23:06:57.804006
3567 23:06:57.805959 RX Delay -40 -> 252, step: 8
3568 23:06:57.809592 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3569 23:06:57.815896 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3570 23:06:57.819486 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3571 23:06:57.822830 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3572 23:06:57.826121 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3573 23:06:57.829215 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3574 23:06:57.835683 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3575 23:06:57.839436 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3576 23:06:57.842414 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3577 23:06:57.845616 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3578 23:06:57.849022 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3579 23:06:57.856140 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3580 23:06:57.859163 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3581 23:06:57.862453 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3582 23:06:57.865796 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3583 23:06:57.869538 iDelay=200, Bit 15, Center 127 (56 ~ 199) 144
3584 23:06:57.872493 ==
3585 23:06:57.875678 Dram Type= 6, Freq= 0, CH_1, rank 1
3586 23:06:57.879069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3587 23:06:57.879681 ==
3588 23:06:57.880171 DQS Delay:
3589 23:06:57.882695 DQS0 = 0, DQS1 = 0
3590 23:06:57.883244 DQM Delay:
3591 23:06:57.885486 DQM0 = 120, DQM1 = 114
3592 23:06:57.886167 DQ Delay:
3593 23:06:57.888950 DQ0 =123, DQ1 =115, DQ2 =111, DQ3 =123
3594 23:06:57.892595 DQ4 =119, DQ5 =131, DQ6 =127, DQ7 =115
3595 23:06:57.895901 DQ8 =99, DQ9 =103, DQ10 =115, DQ11 =107
3596 23:06:57.898821 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =127
3597 23:06:57.899294
3598 23:06:57.899669
3599 23:06:57.900032 ==
3600 23:06:57.902090 Dram Type= 6, Freq= 0, CH_1, rank 1
3601 23:06:57.908992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3602 23:06:57.909611 ==
3603 23:06:57.910202
3604 23:06:57.910912
3605 23:06:57.911431 TX Vref Scan disable
3606 23:06:57.912384 == TX Byte 0 ==
3607 23:06:57.915972 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3608 23:06:57.918990 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3609 23:06:57.922496 == TX Byte 1 ==
3610 23:06:57.925772 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3611 23:06:57.932077 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3612 23:06:57.932820 ==
3613 23:06:57.935735 Dram Type= 6, Freq= 0, CH_1, rank 1
3614 23:06:57.938659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3615 23:06:57.939086 ==
3616 23:06:57.950463 TX Vref=22, minBit 9, minWin=24, winSum=409
3617 23:06:57.953833 TX Vref=24, minBit 1, minWin=25, winSum=413
3618 23:06:57.956750 TX Vref=26, minBit 1, minWin=25, winSum=416
3619 23:06:57.960465 TX Vref=28, minBit 10, minWin=25, winSum=426
3620 23:06:57.963680 TX Vref=30, minBit 1, minWin=26, winSum=426
3621 23:06:57.970187 TX Vref=32, minBit 0, minWin=26, winSum=423
3622 23:06:57.973736 [TxChooseVref] Worse bit 1, Min win 26, Win sum 426, Final Vref 30
3623 23:06:57.974267
3624 23:06:57.977128 Final TX Range 1 Vref 30
3625 23:06:57.977662
3626 23:06:57.977999 ==
3627 23:06:57.980620 Dram Type= 6, Freq= 0, CH_1, rank 1
3628 23:06:57.983151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3629 23:06:57.986675 ==
3630 23:06:57.987200
3631 23:06:57.987536
3632 23:06:57.987846 TX Vref Scan disable
3633 23:06:57.990298 == TX Byte 0 ==
3634 23:06:57.993313 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3635 23:06:57.999955 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3636 23:06:58.000500 == TX Byte 1 ==
3637 23:06:58.003255 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3638 23:06:58.006820 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3639 23:06:58.010057
3640 23:06:58.010542 [DATLAT]
3641 23:06:58.010907 Freq=1200, CH1 RK1
3642 23:06:58.011234
3643 23:06:58.013648 DATLAT Default: 0xd
3644 23:06:58.014100 0, 0xFFFF, sum = 0
3645 23:06:58.016472 1, 0xFFFF, sum = 0
3646 23:06:58.016934 2, 0xFFFF, sum = 0
3647 23:06:58.020077 3, 0xFFFF, sum = 0
3648 23:06:58.020638 4, 0xFFFF, sum = 0
3649 23:06:58.023609 5, 0xFFFF, sum = 0
3650 23:06:58.026573 6, 0xFFFF, sum = 0
3651 23:06:58.027007 7, 0xFFFF, sum = 0
3652 23:06:58.030179 8, 0xFFFF, sum = 0
3653 23:06:58.030635 9, 0xFFFF, sum = 0
3654 23:06:58.033085 10, 0xFFFF, sum = 0
3655 23:06:58.033519 11, 0xFFFF, sum = 0
3656 23:06:58.036859 12, 0x0, sum = 1
3657 23:06:58.037398 13, 0x0, sum = 2
3658 23:06:58.039692 14, 0x0, sum = 3
3659 23:06:58.040125 15, 0x0, sum = 4
3660 23:06:58.040467 best_step = 13
3661 23:06:58.043393
3662 23:06:58.043817 ==
3663 23:06:58.046431 Dram Type= 6, Freq= 0, CH_1, rank 1
3664 23:06:58.049872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3665 23:06:58.050517 ==
3666 23:06:58.050915 RX Vref Scan: 0
3667 23:06:58.051259
3668 23:06:58.053160 RX Vref 0 -> 0, step: 1
3669 23:06:58.053584
3670 23:06:58.056767 RX Delay -13 -> 252, step: 4
3671 23:06:58.059792 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3672 23:06:58.066171 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3673 23:06:58.069800 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3674 23:06:58.073351 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3675 23:06:58.076478 iDelay=195, Bit 4, Center 122 (63 ~ 182) 120
3676 23:06:58.079980 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3677 23:06:58.086279 iDelay=195, Bit 6, Center 128 (67 ~ 190) 124
3678 23:06:58.089723 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3679 23:06:58.092931 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3680 23:06:58.096548 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3681 23:06:58.099688 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3682 23:06:58.106492 iDelay=195, Bit 11, Center 108 (43 ~ 174) 132
3683 23:06:58.109947 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3684 23:06:58.113082 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3685 23:06:58.116737 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3686 23:06:58.119637 iDelay=195, Bit 15, Center 124 (59 ~ 190) 132
3687 23:06:58.123044 ==
3688 23:06:58.126150 Dram Type= 6, Freq= 0, CH_1, rank 1
3689 23:06:58.129372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3690 23:06:58.129879 ==
3691 23:06:58.130288 DQS Delay:
3692 23:06:58.132635 DQS0 = 0, DQS1 = 0
3693 23:06:58.133153 DQM Delay:
3694 23:06:58.135984 DQM0 = 119, DQM1 = 113
3695 23:06:58.136447 DQ Delay:
3696 23:06:58.139423 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =118
3697 23:06:58.142852 DQ4 =122, DQ5 =130, DQ6 =128, DQ7 =116
3698 23:06:58.146241 DQ8 =100, DQ9 =102, DQ10 =112, DQ11 =108
3699 23:06:58.149313 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =124
3700 23:06:58.149819
3701 23:06:58.150324
3702 23:06:58.159482 [DQSOSCAuto] RK1, (LSB)MR18= 0xbee, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 405 ps
3703 23:06:58.162633 CH1 RK1: MR19=403, MR18=BEE
3704 23:06:58.165818 CH1_RK1: MR19=0x403, MR18=0xBEE, DQSOSC=405, MR23=63, INC=39, DEC=26
3705 23:06:58.169300 [RxdqsGatingPostProcess] freq 1200
3706 23:06:58.175760 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3707 23:06:58.179476 best DQS0 dly(2T, 0.5T) = (0, 11)
3708 23:06:58.182514 best DQS1 dly(2T, 0.5T) = (0, 11)
3709 23:06:58.185728 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3710 23:06:58.189641 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3711 23:06:58.192494 best DQS0 dly(2T, 0.5T) = (0, 11)
3712 23:06:58.196150 best DQS1 dly(2T, 0.5T) = (0, 11)
3713 23:06:58.199084 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3714 23:06:58.202930 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3715 23:06:58.203503 Pre-setting of DQS Precalculation
3716 23:06:58.209419 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3717 23:06:58.215991 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3718 23:06:58.222690 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3719 23:06:58.223264
3720 23:06:58.223633
3721 23:06:58.226058 [Calibration Summary] 2400 Mbps
3722 23:06:58.229338 CH 0, Rank 0
3723 23:06:58.229810 SW Impedance : PASS
3724 23:06:58.232720 DUTY Scan : NO K
3725 23:06:58.236031 ZQ Calibration : PASS
3726 23:06:58.236609 Jitter Meter : NO K
3727 23:06:58.239138 CBT Training : PASS
3728 23:06:58.242566 Write leveling : PASS
3729 23:06:58.243133 RX DQS gating : PASS
3730 23:06:58.245799 RX DQ/DQS(RDDQC) : PASS
3731 23:06:58.249294 TX DQ/DQS : PASS
3732 23:06:58.249870 RX DATLAT : PASS
3733 23:06:58.252278 RX DQ/DQS(Engine): PASS
3734 23:06:58.252856 TX OE : NO K
3735 23:06:58.255868 All Pass.
3736 23:06:58.256336
3737 23:06:58.256706 CH 0, Rank 1
3738 23:06:58.259058 SW Impedance : PASS
3739 23:06:58.259529 DUTY Scan : NO K
3740 23:06:58.262253 ZQ Calibration : PASS
3741 23:06:58.265537 Jitter Meter : NO K
3742 23:06:58.266010 CBT Training : PASS
3743 23:06:58.268685 Write leveling : PASS
3744 23:06:58.272377 RX DQS gating : PASS
3745 23:06:58.272851 RX DQ/DQS(RDDQC) : PASS
3746 23:06:58.275131 TX DQ/DQS : PASS
3747 23:06:58.278214 RX DATLAT : PASS
3748 23:06:58.278322 RX DQ/DQS(Engine): PASS
3749 23:06:58.281650 TX OE : NO K
3750 23:06:58.281734 All Pass.
3751 23:06:58.281815
3752 23:06:58.285253 CH 1, Rank 0
3753 23:06:58.285336 SW Impedance : PASS
3754 23:06:58.288681 DUTY Scan : NO K
3755 23:06:58.291530 ZQ Calibration : PASS
3756 23:06:58.291609 Jitter Meter : NO K
3757 23:06:58.294885 CBT Training : PASS
3758 23:06:58.298253 Write leveling : PASS
3759 23:06:58.298334 RX DQS gating : PASS
3760 23:06:58.301537 RX DQ/DQS(RDDQC) : PASS
3761 23:06:58.304554 TX DQ/DQS : PASS
3762 23:06:58.304629 RX DATLAT : PASS
3763 23:06:58.308116 RX DQ/DQS(Engine): PASS
3764 23:06:58.308189 TX OE : NO K
3765 23:06:58.311391 All Pass.
3766 23:06:58.311462
3767 23:06:58.311522 CH 1, Rank 1
3768 23:06:58.314893 SW Impedance : PASS
3769 23:06:58.314977 DUTY Scan : NO K
3770 23:06:58.318307 ZQ Calibration : PASS
3771 23:06:58.321286 Jitter Meter : NO K
3772 23:06:58.321381 CBT Training : PASS
3773 23:06:58.324554 Write leveling : PASS
3774 23:06:58.327956 RX DQS gating : PASS
3775 23:06:58.328060 RX DQ/DQS(RDDQC) : PASS
3776 23:06:58.331311 TX DQ/DQS : PASS
3777 23:06:58.334907 RX DATLAT : PASS
3778 23:06:58.335045 RX DQ/DQS(Engine): PASS
3779 23:06:58.337664 TX OE : NO K
3780 23:06:58.337788 All Pass.
3781 23:06:58.337886
3782 23:06:58.341531 DramC Write-DBI off
3783 23:06:58.344512 PER_BANK_REFRESH: Hybrid Mode
3784 23:06:58.344666 TX_TRACKING: ON
3785 23:06:58.354556 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3786 23:06:58.357962 [FAST_K] Save calibration result to emmc
3787 23:06:58.361561 dramc_set_vcore_voltage set vcore to 650000
3788 23:06:58.364902 Read voltage for 600, 5
3789 23:06:58.365228 Vio18 = 0
3790 23:06:58.365542 Vcore = 650000
3791 23:06:58.368818 Vdram = 0
3792 23:06:58.369220 Vddq = 0
3793 23:06:58.369423 Vmddr = 0
3794 23:06:58.374977 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3795 23:06:58.377982 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3796 23:06:58.381088 MEM_TYPE=3, freq_sel=19
3797 23:06:58.384808 sv_algorithm_assistance_LP4_1600
3798 23:06:58.388864 ============ PULL DRAM RESETB DOWN ============
3799 23:06:58.391901 ========== PULL DRAM RESETB DOWN end =========
3800 23:06:58.398292 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3801 23:06:58.401604 ===================================
3802 23:06:58.404519 LPDDR4 DRAM CONFIGURATION
3803 23:06:58.408327 ===================================
3804 23:06:58.408901 EX_ROW_EN[0] = 0x0
3805 23:06:58.411586 EX_ROW_EN[1] = 0x0
3806 23:06:58.412156 LP4Y_EN = 0x0
3807 23:06:58.414550 WORK_FSP = 0x0
3808 23:06:58.415028 WL = 0x2
3809 23:06:58.418369 RL = 0x2
3810 23:06:58.418989 BL = 0x2
3811 23:06:58.421249 RPST = 0x0
3812 23:06:58.421726 RD_PRE = 0x0
3813 23:06:58.425021 WR_PRE = 0x1
3814 23:06:58.425594 WR_PST = 0x0
3815 23:06:58.428170 DBI_WR = 0x0
3816 23:06:58.428743 DBI_RD = 0x0
3817 23:06:58.431814 OTF = 0x1
3818 23:06:58.434990 ===================================
3819 23:06:58.438335 ===================================
3820 23:06:58.438986 ANA top config
3821 23:06:58.441537 ===================================
3822 23:06:58.444857 DLL_ASYNC_EN = 0
3823 23:06:58.448145 ALL_SLAVE_EN = 1
3824 23:06:58.451548 NEW_RANK_MODE = 1
3825 23:06:58.452030 DLL_IDLE_MODE = 1
3826 23:06:58.454921 LP45_APHY_COMB_EN = 1
3827 23:06:58.458084 TX_ODT_DIS = 1
3828 23:06:58.461603 NEW_8X_MODE = 1
3829 23:06:58.465028 ===================================
3830 23:06:58.467858 ===================================
3831 23:06:58.471143 data_rate = 1200
3832 23:06:58.471616 CKR = 1
3833 23:06:58.474482 DQ_P2S_RATIO = 8
3834 23:06:58.477976 ===================================
3835 23:06:58.481382 CA_P2S_RATIO = 8
3836 23:06:58.484466 DQ_CA_OPEN = 0
3837 23:06:58.487710 DQ_SEMI_OPEN = 0
3838 23:06:58.491331 CA_SEMI_OPEN = 0
3839 23:06:58.491900 CA_FULL_RATE = 0
3840 23:06:58.494484 DQ_CKDIV4_EN = 1
3841 23:06:58.497778 CA_CKDIV4_EN = 1
3842 23:06:58.500749 CA_PREDIV_EN = 0
3843 23:06:58.504059 PH8_DLY = 0
3844 23:06:58.507545 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3845 23:06:58.508119 DQ_AAMCK_DIV = 4
3846 23:06:58.511407 CA_AAMCK_DIV = 4
3847 23:06:58.514437 CA_ADMCK_DIV = 4
3848 23:06:58.517938 DQ_TRACK_CA_EN = 0
3849 23:06:58.521076 CA_PICK = 600
3850 23:06:58.524400 CA_MCKIO = 600
3851 23:06:58.527612 MCKIO_SEMI = 0
3852 23:06:58.528178 PLL_FREQ = 2288
3853 23:06:58.531061 DQ_UI_PI_RATIO = 32
3854 23:06:58.534485 CA_UI_PI_RATIO = 0
3855 23:06:58.537442 ===================================
3856 23:06:58.540786 ===================================
3857 23:06:58.544438 memory_type:LPDDR4
3858 23:06:58.544907 GP_NUM : 10
3859 23:06:58.547314 SRAM_EN : 1
3860 23:06:58.550839 MD32_EN : 0
3861 23:06:58.554250 ===================================
3862 23:06:58.554842 [ANA_INIT] >>>>>>>>>>>>>>
3863 23:06:58.557705 <<<<<< [CONFIGURE PHASE]: ANA_TX
3864 23:06:58.560782 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3865 23:06:58.564096 ===================================
3866 23:06:58.567345 data_rate = 1200,PCW = 0X5800
3867 23:06:58.570880 ===================================
3868 23:06:58.573851 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3869 23:06:58.581061 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3870 23:06:58.583811 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3871 23:06:58.590895 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3872 23:06:58.594138 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3873 23:06:58.597441 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3874 23:06:58.600501 [ANA_INIT] flow start
3875 23:06:58.600978 [ANA_INIT] PLL >>>>>>>>
3876 23:06:58.604214 [ANA_INIT] PLL <<<<<<<<
3877 23:06:58.606818 [ANA_INIT] MIDPI >>>>>>>>
3878 23:06:58.607309 [ANA_INIT] MIDPI <<<<<<<<
3879 23:06:58.610358 [ANA_INIT] DLL >>>>>>>>
3880 23:06:58.613928 [ANA_INIT] flow end
3881 23:06:58.617177 ============ LP4 DIFF to SE enter ============
3882 23:06:58.620463 ============ LP4 DIFF to SE exit ============
3883 23:06:58.624002 [ANA_INIT] <<<<<<<<<<<<<
3884 23:06:58.627390 [Flow] Enable top DCM control >>>>>
3885 23:06:58.630632 [Flow] Enable top DCM control <<<<<
3886 23:06:58.634461 Enable DLL master slave shuffle
3887 23:06:58.637269 ==============================================================
3888 23:06:58.640578 Gating Mode config
3889 23:06:58.643605 ==============================================================
3890 23:06:58.647126 Config description:
3891 23:06:58.657423 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3892 23:06:58.663634 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3893 23:06:58.666994 SELPH_MODE 0: By rank 1: By Phase
3894 23:06:58.674214 ==============================================================
3895 23:06:58.676993 GAT_TRACK_EN = 1
3896 23:06:58.680320 RX_GATING_MODE = 2
3897 23:06:58.683824 RX_GATING_TRACK_MODE = 2
3898 23:06:58.687016 SELPH_MODE = 1
3899 23:06:58.690491 PICG_EARLY_EN = 1
3900 23:06:58.690918 VALID_LAT_VALUE = 1
3901 23:06:58.696982 ==============================================================
3902 23:06:58.700791 Enter into Gating configuration >>>>
3903 23:06:58.703338 Exit from Gating configuration <<<<
3904 23:06:58.706865 Enter into DVFS_PRE_config >>>>>
3905 23:06:58.717196 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3906 23:06:58.720103 Exit from DVFS_PRE_config <<<<<
3907 23:06:58.723840 Enter into PICG configuration >>>>
3908 23:06:58.727083 Exit from PICG configuration <<<<
3909 23:06:58.730042 [RX_INPUT] configuration >>>>>
3910 23:06:58.733353 [RX_INPUT] configuration <<<<<
3911 23:06:58.739783 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3912 23:06:58.742975 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3913 23:06:58.749843 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3914 23:06:58.756876 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3915 23:06:58.763280 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3916 23:06:58.769987 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3917 23:06:58.773453 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3918 23:06:58.776582 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3919 23:06:58.779776 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3920 23:06:58.787314 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3921 23:06:58.789878 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3922 23:06:58.793800 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3923 23:06:58.796723 ===================================
3924 23:06:58.799858 LPDDR4 DRAM CONFIGURATION
3925 23:06:58.803276 ===================================
3926 23:06:58.803701 EX_ROW_EN[0] = 0x0
3927 23:06:58.806458 EX_ROW_EN[1] = 0x0
3928 23:06:58.806886 LP4Y_EN = 0x0
3929 23:06:58.809811 WORK_FSP = 0x0
3930 23:06:58.810334 WL = 0x2
3931 23:06:58.813123 RL = 0x2
3932 23:06:58.816465 BL = 0x2
3933 23:06:58.816984 RPST = 0x0
3934 23:06:58.819584 RD_PRE = 0x0
3935 23:06:58.820010 WR_PRE = 0x1
3936 23:06:58.823308 WR_PST = 0x0
3937 23:06:58.823803 DBI_WR = 0x0
3938 23:06:58.826288 DBI_RD = 0x0
3939 23:06:58.826844 OTF = 0x1
3940 23:06:58.829899 ===================================
3941 23:06:58.833363 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3942 23:06:58.836593 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3943 23:06:58.843003 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3944 23:06:58.846475 ===================================
3945 23:06:58.849805 LPDDR4 DRAM CONFIGURATION
3946 23:06:58.853361 ===================================
3947 23:06:58.853791 EX_ROW_EN[0] = 0x10
3948 23:06:58.856624 EX_ROW_EN[1] = 0x0
3949 23:06:58.857154 LP4Y_EN = 0x0
3950 23:06:58.859929 WORK_FSP = 0x0
3951 23:06:58.860352 WL = 0x2
3952 23:06:58.862927 RL = 0x2
3953 23:06:58.863362 BL = 0x2
3954 23:06:58.866418 RPST = 0x0
3955 23:06:58.866851 RD_PRE = 0x0
3956 23:06:58.869729 WR_PRE = 0x1
3957 23:06:58.870155 WR_PST = 0x0
3958 23:06:58.873231 DBI_WR = 0x0
3959 23:06:58.873655 DBI_RD = 0x0
3960 23:06:58.876521 OTF = 0x1
3961 23:06:58.879814 ===================================
3962 23:06:58.886293 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3963 23:06:58.889920 nWR fixed to 30
3964 23:06:58.893159 [ModeRegInit_LP4] CH0 RK0
3965 23:06:58.893679 [ModeRegInit_LP4] CH0 RK1
3966 23:06:58.896230 [ModeRegInit_LP4] CH1 RK0
3967 23:06:58.899315 [ModeRegInit_LP4] CH1 RK1
3968 23:06:58.899748 match AC timing 17
3969 23:06:58.906416 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3970 23:06:58.910218 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3971 23:06:58.913016 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3972 23:06:58.919834 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3973 23:06:58.922675 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3974 23:06:58.923149 ==
3975 23:06:58.926705 Dram Type= 6, Freq= 0, CH_0, rank 0
3976 23:06:58.929957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3977 23:06:58.930464 ==
3978 23:06:58.936453 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3979 23:06:58.942708 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3980 23:06:58.946559 [CA 0] Center 36 (5~67) winsize 63
3981 23:06:58.949301 [CA 1] Center 36 (6~67) winsize 62
3982 23:06:58.952671 [CA 2] Center 34 (4~65) winsize 62
3983 23:06:58.956450 [CA 3] Center 34 (3~65) winsize 63
3984 23:06:58.959222 [CA 4] Center 33 (3~64) winsize 62
3985 23:06:58.962761 [CA 5] Center 33 (2~64) winsize 63
3986 23:06:58.963188
3987 23:06:58.965799 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3988 23:06:58.966518
3989 23:06:58.969576 [CATrainingPosCal] consider 1 rank data
3990 23:06:58.972797 u2DelayCellTimex100 = 270/100 ps
3991 23:06:58.976228 CA0 delay=36 (5~67),Diff = 3 PI (28 cell)
3992 23:06:58.979060 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3993 23:06:58.983305 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3994 23:06:58.986121 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3995 23:06:58.989283 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3996 23:06:58.996131 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
3997 23:06:58.996669
3998 23:06:58.999933 CA PerBit enable=1, Macro0, CA PI delay=33
3999 23:06:59.000366
4000 23:06:59.002559 [CBTSetCACLKResult] CA Dly = 33
4001 23:06:59.002990 CS Dly: 4 (0~35)
4002 23:06:59.003330 ==
4003 23:06:59.005626 Dram Type= 6, Freq= 0, CH_0, rank 1
4004 23:06:59.009553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4005 23:06:59.012697 ==
4006 23:06:59.016010 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4007 23:06:59.022581 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4008 23:06:59.026259 [CA 0] Center 36 (6~67) winsize 62
4009 23:06:59.028957 [CA 1] Center 36 (6~67) winsize 62
4010 23:06:59.032456 [CA 2] Center 35 (4~66) winsize 63
4011 23:06:59.036073 [CA 3] Center 34 (4~65) winsize 62
4012 23:06:59.039213 [CA 4] Center 34 (3~65) winsize 63
4013 23:06:59.042173 [CA 5] Center 34 (3~65) winsize 63
4014 23:06:59.042670
4015 23:06:59.045673 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4016 23:06:59.046167
4017 23:06:59.049022 [CATrainingPosCal] consider 2 rank data
4018 23:06:59.052389 u2DelayCellTimex100 = 270/100 ps
4019 23:06:59.056083 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
4020 23:06:59.058940 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
4021 23:06:59.062252 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4022 23:06:59.065730 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4023 23:06:59.072438 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4024 23:06:59.076100 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4025 23:06:59.076635
4026 23:06:59.078991 CA PerBit enable=1, Macro0, CA PI delay=33
4027 23:06:59.079422
4028 23:06:59.082630 [CBTSetCACLKResult] CA Dly = 33
4029 23:06:59.083060 CS Dly: 4 (0~36)
4030 23:06:59.083401
4031 23:06:59.085517 ----->DramcWriteLeveling(PI) begin...
4032 23:06:59.085990 ==
4033 23:06:59.088998 Dram Type= 6, Freq= 0, CH_0, rank 0
4034 23:06:59.095497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4035 23:06:59.095958 ==
4036 23:06:59.098996 Write leveling (Byte 0): 34 => 34
4037 23:06:59.099429 Write leveling (Byte 1): 31 => 31
4038 23:06:59.102456 DramcWriteLeveling(PI) end<-----
4039 23:06:59.102886
4040 23:06:59.103227 ==
4041 23:06:59.105744 Dram Type= 6, Freq= 0, CH_0, rank 0
4042 23:06:59.112465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4043 23:06:59.112897 ==
4044 23:06:59.115367 [Gating] SW mode calibration
4045 23:06:59.122106 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4046 23:06:59.125285 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4047 23:06:59.132107 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4048 23:06:59.135241 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4049 23:06:59.138686 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4050 23:06:59.145186 0 9 12 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0)
4051 23:06:59.148672 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
4052 23:06:59.151901 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4053 23:06:59.158266 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4054 23:06:59.161673 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4055 23:06:59.165151 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4056 23:06:59.171670 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4057 23:06:59.175119 0 10 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (1 1)
4058 23:06:59.178372 0 10 12 | B1->B0 | 2a2a 4242 | 1 0 | (0 0) (0 0)
4059 23:06:59.184818 0 10 16 | B1->B0 | 3b3b 4646 | 0 0 | (1 1) (0 0)
4060 23:06:59.188550 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4061 23:06:59.191966 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4062 23:06:59.198499 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4063 23:06:59.201810 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4064 23:06:59.205404 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4065 23:06:59.208208 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4066 23:06:59.214717 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4067 23:06:59.218049 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4068 23:06:59.221675 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 23:06:59.228099 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 23:06:59.231351 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 23:06:59.234953 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 23:06:59.241192 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 23:06:59.244457 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 23:06:59.248010 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4075 23:06:59.254906 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4076 23:06:59.257959 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4077 23:06:59.261445 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4078 23:06:59.268109 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4079 23:06:59.271199 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4080 23:06:59.274684 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4081 23:06:59.281760 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4082 23:06:59.284655 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4083 23:06:59.287952 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4084 23:06:59.291180 Total UI for P1: 0, mck2ui 16
4085 23:06:59.295003 best dqsien dly found for B0: ( 0, 13, 12)
4086 23:06:59.301514 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4087 23:06:59.302043 Total UI for P1: 0, mck2ui 16
4088 23:06:59.304768 best dqsien dly found for B1: ( 0, 13, 16)
4089 23:06:59.311394 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4090 23:06:59.315174 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4091 23:06:59.315624
4092 23:06:59.318162 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4093 23:06:59.321551 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4094 23:06:59.324694 [Gating] SW calibration Done
4095 23:06:59.325120 ==
4096 23:06:59.328416 Dram Type= 6, Freq= 0, CH_0, rank 0
4097 23:06:59.331505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4098 23:06:59.331939 ==
4099 23:06:59.335212 RX Vref Scan: 0
4100 23:06:59.335636
4101 23:06:59.335971 RX Vref 0 -> 0, step: 1
4102 23:06:59.336282
4103 23:06:59.338178 RX Delay -230 -> 252, step: 16
4104 23:06:59.341461 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4105 23:06:59.348083 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4106 23:06:59.351757 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4107 23:06:59.354911 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4108 23:06:59.358100 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4109 23:06:59.364484 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4110 23:06:59.368189 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4111 23:06:59.371488 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4112 23:06:59.374563 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4113 23:06:59.377965 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4114 23:06:59.384396 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4115 23:06:59.387685 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4116 23:06:59.391416 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4117 23:06:59.394308 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4118 23:06:59.400721 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4119 23:06:59.404313 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4120 23:06:59.404398 ==
4121 23:06:59.407135 Dram Type= 6, Freq= 0, CH_0, rank 0
4122 23:06:59.410850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4123 23:06:59.410939 ==
4124 23:06:59.414172 DQS Delay:
4125 23:06:59.414256 DQS0 = 0, DQS1 = 0
4126 23:06:59.414321 DQM Delay:
4127 23:06:59.417189 DQM0 = 51, DQM1 = 40
4128 23:06:59.417288 DQ Delay:
4129 23:06:59.421166 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =41
4130 23:06:59.424129 DQ4 =57, DQ5 =41, DQ6 =65, DQ7 =65
4131 23:06:59.427674 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =33
4132 23:06:59.431058 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =41
4133 23:06:59.431142
4134 23:06:59.431207
4135 23:06:59.431266 ==
4136 23:06:59.434105 Dram Type= 6, Freq= 0, CH_0, rank 0
4137 23:06:59.440977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4138 23:06:59.441073 ==
4139 23:06:59.441148
4140 23:06:59.441217
4141 23:06:59.441283 TX Vref Scan disable
4142 23:06:59.444095 == TX Byte 0 ==
4143 23:06:59.447734 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4144 23:06:59.454232 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4145 23:06:59.454350 == TX Byte 1 ==
4146 23:06:59.457591 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4147 23:06:59.464279 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4148 23:06:59.464369 ==
4149 23:06:59.467829 Dram Type= 6, Freq= 0, CH_0, rank 0
4150 23:06:59.470741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4151 23:06:59.470838 ==
4152 23:06:59.470914
4153 23:06:59.470985
4154 23:06:59.474165 TX Vref Scan disable
4155 23:06:59.477798 == TX Byte 0 ==
4156 23:06:59.480864 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4157 23:06:59.484352 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4158 23:06:59.487524 == TX Byte 1 ==
4159 23:06:59.491152 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4160 23:06:59.494213 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4161 23:06:59.494691
4162 23:06:59.495033 [DATLAT]
4163 23:06:59.498150 Freq=600, CH0 RK0
4164 23:06:59.498671
4165 23:06:59.499118 DATLAT Default: 0x9
4166 23:06:59.501346 0, 0xFFFF, sum = 0
4167 23:06:59.501827 1, 0xFFFF, sum = 0
4168 23:06:59.504045 2, 0xFFFF, sum = 0
4169 23:06:59.507599 3, 0xFFFF, sum = 0
4170 23:06:59.508040 4, 0xFFFF, sum = 0
4171 23:06:59.511076 5, 0xFFFF, sum = 0
4172 23:06:59.511514 6, 0xFFFF, sum = 0
4173 23:06:59.514309 7, 0xFFFF, sum = 0
4174 23:06:59.514818 8, 0x0, sum = 1
4175 23:06:59.515169 9, 0x0, sum = 2
4176 23:06:59.517646 10, 0x0, sum = 3
4177 23:06:59.518083 11, 0x0, sum = 4
4178 23:06:59.520841 best_step = 9
4179 23:06:59.521273
4180 23:06:59.521628 ==
4181 23:06:59.524286 Dram Type= 6, Freq= 0, CH_0, rank 0
4182 23:06:59.527578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4183 23:06:59.528016 ==
4184 23:06:59.530925 RX Vref Scan: 1
4185 23:06:59.531374
4186 23:06:59.531775 RX Vref 0 -> 0, step: 1
4187 23:06:59.532186
4188 23:06:59.534205 RX Delay -179 -> 252, step: 8
4189 23:06:59.534777
4190 23:06:59.537784 Set Vref, RX VrefLevel [Byte0]: 57
4191 23:06:59.540981 [Byte1]: 50
4192 23:06:59.545044
4193 23:06:59.545636 Final RX Vref Byte 0 = 57 to rank0
4194 23:06:59.548390 Final RX Vref Byte 1 = 50 to rank0
4195 23:06:59.551662 Final RX Vref Byte 0 = 57 to rank1
4196 23:06:59.554773 Final RX Vref Byte 1 = 50 to rank1==
4197 23:06:59.558114 Dram Type= 6, Freq= 0, CH_0, rank 0
4198 23:06:59.564942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4199 23:06:59.565442 ==
4200 23:06:59.565874 DQS Delay:
4201 23:06:59.566367 DQS0 = 0, DQS1 = 0
4202 23:06:59.568205 DQM Delay:
4203 23:06:59.568657 DQM0 = 49, DQM1 = 40
4204 23:06:59.571877 DQ Delay:
4205 23:06:59.574945 DQ0 =48, DQ1 =52, DQ2 =44, DQ3 =44
4206 23:06:59.575400 DQ4 =52, DQ5 =40, DQ6 =60, DQ7 =56
4207 23:06:59.578214 DQ8 =36, DQ9 =24, DQ10 =36, DQ11 =36
4208 23:06:59.581447 DQ12 =48, DQ13 =44, DQ14 =52, DQ15 =48
4209 23:06:59.584933
4210 23:06:59.585359
4211 23:06:59.591478 [DQSOSCAuto] RK0, (LSB)MR18= 0x5b56, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
4212 23:06:59.594944 CH0 RK0: MR19=808, MR18=5B56
4213 23:06:59.602028 CH0_RK0: MR19=0x808, MR18=0x5B56, DQSOSC=392, MR23=63, INC=170, DEC=113
4214 23:06:59.602662
4215 23:06:59.604834 ----->DramcWriteLeveling(PI) begin...
4216 23:06:59.605398 ==
4217 23:06:59.607845 Dram Type= 6, Freq= 0, CH_0, rank 1
4218 23:06:59.611623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4219 23:06:59.612141 ==
4220 23:06:59.614746 Write leveling (Byte 0): 33 => 33
4221 23:06:59.617874 Write leveling (Byte 1): 30 => 30
4222 23:06:59.621423 DramcWriteLeveling(PI) end<-----
4223 23:06:59.621863
4224 23:06:59.622208 ==
4225 23:06:59.624715 Dram Type= 6, Freq= 0, CH_0, rank 1
4226 23:06:59.628148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4227 23:06:59.628588 ==
4228 23:06:59.631502 [Gating] SW mode calibration
4229 23:06:59.638089 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4230 23:06:59.644730 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4231 23:06:59.647716 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4232 23:06:59.651051 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4233 23:06:59.657524 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4234 23:06:59.661265 0 9 12 | B1->B0 | 3434 3333 | 1 0 | (1 0) (1 0)
4235 23:06:59.664773 0 9 16 | B1->B0 | 2828 2424 | 1 0 | (0 0) (0 0)
4236 23:06:59.671156 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4237 23:06:59.674130 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4238 23:06:59.677776 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4239 23:06:59.684696 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4240 23:06:59.687474 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4241 23:06:59.691214 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4242 23:06:59.697702 0 10 12 | B1->B0 | 3030 3333 | 0 1 | (0 0) (1 1)
4243 23:06:59.700987 0 10 16 | B1->B0 | 4040 4343 | 1 1 | (0 0) (0 0)
4244 23:06:59.704093 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4245 23:06:59.710923 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4246 23:06:59.714095 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4247 23:06:59.717217 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4248 23:06:59.724545 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4249 23:06:59.727782 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4250 23:06:59.731157 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4251 23:06:59.738459 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 23:06:59.741071 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 23:06:59.744252 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 23:06:59.751166 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 23:06:59.754370 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 23:06:59.757456 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 23:06:59.764369 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 23:06:59.767816 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 23:06:59.770984 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 23:06:59.774082 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4261 23:06:59.780915 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4262 23:06:59.784290 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 23:06:59.787286 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 23:06:59.794124 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4265 23:06:59.796987 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4266 23:06:59.800400 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4267 23:06:59.806948 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4268 23:06:59.810561 Total UI for P1: 0, mck2ui 16
4269 23:06:59.813996 best dqsien dly found for B0: ( 0, 13, 12)
4270 23:06:59.817305 Total UI for P1: 0, mck2ui 16
4271 23:06:59.820328 best dqsien dly found for B1: ( 0, 13, 12)
4272 23:06:59.823976 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4273 23:06:59.827166 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4274 23:06:59.827258
4275 23:06:59.830317 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4276 23:06:59.833713 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4277 23:06:59.837664 [Gating] SW calibration Done
4278 23:06:59.837799 ==
4279 23:06:59.840831 Dram Type= 6, Freq= 0, CH_0, rank 1
4280 23:06:59.843486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4281 23:06:59.843613 ==
4282 23:06:59.846786 RX Vref Scan: 0
4283 23:06:59.846871
4284 23:06:59.850503 RX Vref 0 -> 0, step: 1
4285 23:06:59.850587
4286 23:06:59.850657 RX Delay -230 -> 252, step: 16
4287 23:06:59.856921 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4288 23:06:59.860136 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4289 23:06:59.863683 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4290 23:06:59.867366 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4291 23:06:59.873339 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4292 23:06:59.876679 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4293 23:06:59.880492 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4294 23:06:59.883405 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4295 23:06:59.886915 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4296 23:06:59.893684 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4297 23:06:59.896787 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4298 23:06:59.900566 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4299 23:06:59.903395 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4300 23:06:59.910261 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4301 23:06:59.913591 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4302 23:06:59.916884 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4303 23:06:59.917353 ==
4304 23:06:59.920480 Dram Type= 6, Freq= 0, CH_0, rank 1
4305 23:06:59.923788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4306 23:06:59.927039 ==
4307 23:06:59.927606 DQS Delay:
4308 23:06:59.927979 DQS0 = 0, DQS1 = 0
4309 23:06:59.930605 DQM Delay:
4310 23:06:59.931076 DQM0 = 47, DQM1 = 40
4311 23:06:59.933466 DQ Delay:
4312 23:06:59.933936 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4313 23:06:59.937091 DQ4 =49, DQ5 =41, DQ6 =65, DQ7 =57
4314 23:06:59.940293 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =41
4315 23:06:59.943888 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =49
4316 23:06:59.944463
4317 23:06:59.946958
4318 23:06:59.947427 ==
4319 23:06:59.950146 Dram Type= 6, Freq= 0, CH_0, rank 1
4320 23:06:59.953675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4321 23:06:59.954246 ==
4322 23:06:59.954679
4323 23:06:59.955028
4324 23:06:59.957207 TX Vref Scan disable
4325 23:06:59.957677 == TX Byte 0 ==
4326 23:06:59.963459 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4327 23:06:59.966877 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4328 23:06:59.967373 == TX Byte 1 ==
4329 23:06:59.973262 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4330 23:06:59.976786 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4331 23:06:59.977284 ==
4332 23:06:59.980046 Dram Type= 6, Freq= 0, CH_0, rank 1
4333 23:06:59.983291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4334 23:06:59.983919 ==
4335 23:06:59.984321
4336 23:06:59.984822
4337 23:06:59.986628 TX Vref Scan disable
4338 23:06:59.989877 == TX Byte 0 ==
4339 23:06:59.993238 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4340 23:06:59.996468 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4341 23:06:59.999984 == TX Byte 1 ==
4342 23:07:00.003273 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4343 23:07:00.006282 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4344 23:07:00.006774
4345 23:07:00.010000 [DATLAT]
4346 23:07:00.010468 Freq=600, CH0 RK1
4347 23:07:00.010908
4348 23:07:00.013433 DATLAT Default: 0x9
4349 23:07:00.013871 0, 0xFFFF, sum = 0
4350 23:07:00.016375 1, 0xFFFF, sum = 0
4351 23:07:00.016816 2, 0xFFFF, sum = 0
4352 23:07:00.019919 3, 0xFFFF, sum = 0
4353 23:07:00.020363 4, 0xFFFF, sum = 0
4354 23:07:00.023625 5, 0xFFFF, sum = 0
4355 23:07:00.024288 6, 0xFFFF, sum = 0
4356 23:07:00.026496 7, 0xFFFF, sum = 0
4357 23:07:00.026943 8, 0x0, sum = 1
4358 23:07:00.029744 9, 0x0, sum = 2
4359 23:07:00.030185 10, 0x0, sum = 3
4360 23:07:00.033055 11, 0x0, sum = 4
4361 23:07:00.033596 best_step = 9
4362 23:07:00.034057
4363 23:07:00.034537 ==
4364 23:07:00.036917 Dram Type= 6, Freq= 0, CH_0, rank 1
4365 23:07:00.043195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4366 23:07:00.043707 ==
4367 23:07:00.044181 RX Vref Scan: 0
4368 23:07:00.044619
4369 23:07:00.046793 RX Vref 0 -> 0, step: 1
4370 23:07:00.047286
4371 23:07:00.049768 RX Delay -179 -> 252, step: 8
4372 23:07:00.053389 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4373 23:07:00.056454 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4374 23:07:00.062670 iDelay=205, Bit 2, Center 44 (-99 ~ 188) 288
4375 23:07:00.066231 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4376 23:07:00.069565 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4377 23:07:00.072949 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4378 23:07:00.076317 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4379 23:07:00.082696 iDelay=205, Bit 7, Center 52 (-91 ~ 196) 288
4380 23:07:00.086207 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4381 23:07:00.089495 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4382 23:07:00.092568 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4383 23:07:00.099603 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4384 23:07:00.102669 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4385 23:07:00.105969 iDelay=205, Bit 13, Center 44 (-99 ~ 188) 288
4386 23:07:00.109875 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4387 23:07:00.112682 iDelay=205, Bit 15, Center 44 (-99 ~ 188) 288
4388 23:07:00.116002 ==
4389 23:07:00.119894 Dram Type= 6, Freq= 0, CH_0, rank 1
4390 23:07:00.123100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4391 23:07:00.123567 ==
4392 23:07:00.123957 DQS Delay:
4393 23:07:00.126591 DQS0 = 0, DQS1 = 0
4394 23:07:00.127051 DQM Delay:
4395 23:07:00.129738 DQM0 = 47, DQM1 = 40
4396 23:07:00.130302 DQ Delay:
4397 23:07:00.133161 DQ0 =44, DQ1 =48, DQ2 =44, DQ3 =44
4398 23:07:00.136392 DQ4 =48, DQ5 =40, DQ6 =60, DQ7 =52
4399 23:07:00.139309 DQ8 =32, DQ9 =28, DQ10 =40, DQ11 =36
4400 23:07:00.143050 DQ12 =48, DQ13 =44, DQ14 =48, DQ15 =44
4401 23:07:00.143603
4402 23:07:00.143975
4403 23:07:00.149253 [DQSOSCAuto] RK1, (LSB)MR18= 0x6331, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
4404 23:07:00.152857 CH0 RK1: MR19=808, MR18=6331
4405 23:07:00.159768 CH0_RK1: MR19=0x808, MR18=0x6331, DQSOSC=391, MR23=63, INC=171, DEC=114
4406 23:07:00.162710 [RxdqsGatingPostProcess] freq 600
4407 23:07:00.169386 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4408 23:07:00.170026 Pre-setting of DQS Precalculation
4409 23:07:00.176185 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4410 23:07:00.176659 ==
4411 23:07:00.179489 Dram Type= 6, Freq= 0, CH_1, rank 0
4412 23:07:00.182723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4413 23:07:00.183204 ==
4414 23:07:00.189644 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4415 23:07:00.196418 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4416 23:07:00.199691 [CA 0] Center 35 (5~66) winsize 62
4417 23:07:00.203143 [CA 1] Center 35 (5~66) winsize 62
4418 23:07:00.206360 [CA 2] Center 34 (4~65) winsize 62
4419 23:07:00.209686 [CA 3] Center 33 (3~64) winsize 62
4420 23:07:00.212699 [CA 4] Center 34 (3~65) winsize 63
4421 23:07:00.216429 [CA 5] Center 33 (3~64) winsize 62
4422 23:07:00.216949
4423 23:07:00.219381 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4424 23:07:00.219854
4425 23:07:00.222913 [CATrainingPosCal] consider 1 rank data
4426 23:07:00.226068 u2DelayCellTimex100 = 270/100 ps
4427 23:07:00.229449 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4428 23:07:00.233000 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4429 23:07:00.236245 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4430 23:07:00.239475 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4431 23:07:00.242939 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4432 23:07:00.246087 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4433 23:07:00.246762
4434 23:07:00.253291 CA PerBit enable=1, Macro0, CA PI delay=33
4435 23:07:00.253839
4436 23:07:00.254183 [CBTSetCACLKResult] CA Dly = 33
4437 23:07:00.256538 CS Dly: 5 (0~36)
4438 23:07:00.257077 ==
4439 23:07:00.259507 Dram Type= 6, Freq= 0, CH_1, rank 1
4440 23:07:00.262988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4441 23:07:00.263536 ==
4442 23:07:00.269632 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4443 23:07:00.275831 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4444 23:07:00.279651 [CA 0] Center 35 (5~66) winsize 62
4445 23:07:00.282706 [CA 1] Center 35 (5~66) winsize 62
4446 23:07:00.286124 [CA 2] Center 34 (4~65) winsize 62
4447 23:07:00.289298 [CA 3] Center 34 (4~65) winsize 62
4448 23:07:00.292711 [CA 4] Center 34 (4~64) winsize 61
4449 23:07:00.296522 [CA 5] Center 33 (3~64) winsize 62
4450 23:07:00.297104
4451 23:07:00.299426 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4452 23:07:00.299909
4453 23:07:00.302747 [CATrainingPosCal] consider 2 rank data
4454 23:07:00.305983 u2DelayCellTimex100 = 270/100 ps
4455 23:07:00.309247 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4456 23:07:00.313274 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4457 23:07:00.316042 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4458 23:07:00.319819 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4459 23:07:00.322678 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4460 23:07:00.326123 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4461 23:07:00.326734
4462 23:07:00.333550 CA PerBit enable=1, Macro0, CA PI delay=33
4463 23:07:00.334125
4464 23:07:00.334548 [CBTSetCACLKResult] CA Dly = 33
4465 23:07:00.336052 CS Dly: 5 (0~37)
4466 23:07:00.336521
4467 23:07:00.339393 ----->DramcWriteLeveling(PI) begin...
4468 23:07:00.339972 ==
4469 23:07:00.343246 Dram Type= 6, Freq= 0, CH_1, rank 0
4470 23:07:00.346213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4471 23:07:00.346850 ==
4472 23:07:00.349637 Write leveling (Byte 0): 29 => 29
4473 23:07:00.352927 Write leveling (Byte 1): 30 => 30
4474 23:07:00.355886 DramcWriteLeveling(PI) end<-----
4475 23:07:00.356361
4476 23:07:00.356734 ==
4477 23:07:00.359361 Dram Type= 6, Freq= 0, CH_1, rank 0
4478 23:07:00.362812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4479 23:07:00.366110 ==
4480 23:07:00.366609 [Gating] SW mode calibration
4481 23:07:00.376220 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4482 23:07:00.379097 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4483 23:07:00.382493 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4484 23:07:00.388930 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4485 23:07:00.392646 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4486 23:07:00.395835 0 9 12 | B1->B0 | 2e2e 2f2f | 0 0 | (0 0) (1 1)
4487 23:07:00.402531 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4488 23:07:00.405438 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4489 23:07:00.408956 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4490 23:07:00.415682 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4491 23:07:00.419137 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4492 23:07:00.422781 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4493 23:07:00.429000 0 10 8 | B1->B0 | 2525 2b2b | 0 0 | (0 0) (1 1)
4494 23:07:00.432693 0 10 12 | B1->B0 | 3838 3c3c | 0 1 | (0 0) (0 0)
4495 23:07:00.435905 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4496 23:07:00.442148 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4497 23:07:00.445655 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4498 23:07:00.448909 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4499 23:07:00.455473 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4500 23:07:00.459037 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4501 23:07:00.462034 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4502 23:07:00.465968 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4503 23:07:00.472246 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 23:07:00.475317 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 23:07:00.478893 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 23:07:00.485664 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 23:07:00.489091 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4508 23:07:00.492372 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4509 23:07:00.499125 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 23:07:00.501972 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4511 23:07:00.505419 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4512 23:07:00.512285 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4513 23:07:00.515290 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4514 23:07:00.518669 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4515 23:07:00.525569 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4516 23:07:00.528838 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4517 23:07:00.532412 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4518 23:07:00.538848 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4519 23:07:00.539345 Total UI for P1: 0, mck2ui 16
4520 23:07:00.545300 best dqsien dly found for B0: ( 0, 13, 10)
4521 23:07:00.548745 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4522 23:07:00.552493 Total UI for P1: 0, mck2ui 16
4523 23:07:00.555740 best dqsien dly found for B1: ( 0, 13, 12)
4524 23:07:00.558817 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4525 23:07:00.562211 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4526 23:07:00.562754
4527 23:07:00.565544 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4528 23:07:00.569167 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4529 23:07:00.572216 [Gating] SW calibration Done
4530 23:07:00.572643 ==
4531 23:07:00.575300 Dram Type= 6, Freq= 0, CH_1, rank 0
4532 23:07:00.578648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4533 23:07:00.581969 ==
4534 23:07:00.582430 RX Vref Scan: 0
4535 23:07:00.582776
4536 23:07:00.585064 RX Vref 0 -> 0, step: 1
4537 23:07:00.585492
4538 23:07:00.588289 RX Delay -230 -> 252, step: 16
4539 23:07:00.591833 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4540 23:07:00.595110 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4541 23:07:00.598784 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4542 23:07:00.602011 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4543 23:07:00.608660 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4544 23:07:00.612208 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4545 23:07:00.615606 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4546 23:07:00.618618 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4547 23:07:00.621742 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4548 23:07:00.628623 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4549 23:07:00.631973 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4550 23:07:00.635376 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4551 23:07:00.639018 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4552 23:07:00.645234 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4553 23:07:00.648532 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4554 23:07:00.652526 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4555 23:07:00.653058 ==
4556 23:07:00.655522 Dram Type= 6, Freq= 0, CH_1, rank 0
4557 23:07:00.658667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4558 23:07:00.662097 ==
4559 23:07:00.662628 DQS Delay:
4560 23:07:00.662969 DQS0 = 0, DQS1 = 0
4561 23:07:00.665582 DQM Delay:
4562 23:07:00.666105 DQM0 = 53, DQM1 = 45
4563 23:07:00.666492 DQ Delay:
4564 23:07:00.668650 DQ0 =57, DQ1 =49, DQ2 =41, DQ3 =49
4565 23:07:00.672095 DQ4 =49, DQ5 =65, DQ6 =65, DQ7 =49
4566 23:07:00.675330 DQ8 =25, DQ9 =33, DQ10 =41, DQ11 =41
4567 23:07:00.678452 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4568 23:07:00.678883
4569 23:07:00.679360
4570 23:07:00.681790 ==
4571 23:07:00.684866 Dram Type= 6, Freq= 0, CH_1, rank 0
4572 23:07:00.688462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4573 23:07:00.688893 ==
4574 23:07:00.689231
4575 23:07:00.689611
4576 23:07:00.691596 TX Vref Scan disable
4577 23:07:00.691960 == TX Byte 0 ==
4578 23:07:00.698474 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4579 23:07:00.701738 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4580 23:07:00.702167 == TX Byte 1 ==
4581 23:07:00.708239 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4582 23:07:00.711745 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4583 23:07:00.712174 ==
4584 23:07:00.715346 Dram Type= 6, Freq= 0, CH_1, rank 0
4585 23:07:00.718509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4586 23:07:00.719194 ==
4587 23:07:00.719729
4588 23:07:00.720203
4589 23:07:00.721620 TX Vref Scan disable
4590 23:07:00.724972 == TX Byte 0 ==
4591 23:07:00.728548 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4592 23:07:00.731462 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4593 23:07:00.734938 == TX Byte 1 ==
4594 23:07:00.738448 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4595 23:07:00.741804 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4596 23:07:00.742279
4597 23:07:00.744904 [DATLAT]
4598 23:07:00.745382 Freq=600, CH1 RK0
4599 23:07:00.745789
4600 23:07:00.748407 DATLAT Default: 0x9
4601 23:07:00.748837 0, 0xFFFF, sum = 0
4602 23:07:00.751645 1, 0xFFFF, sum = 0
4603 23:07:00.752083 2, 0xFFFF, sum = 0
4604 23:07:00.754890 3, 0xFFFF, sum = 0
4605 23:07:00.755325 4, 0xFFFF, sum = 0
4606 23:07:00.758302 5, 0xFFFF, sum = 0
4607 23:07:00.758855 6, 0xFFFF, sum = 0
4608 23:07:00.761921 7, 0xFFFF, sum = 0
4609 23:07:00.762505 8, 0x0, sum = 1
4610 23:07:00.765113 9, 0x0, sum = 2
4611 23:07:00.765567 10, 0x0, sum = 3
4612 23:07:00.768136 11, 0x0, sum = 4
4613 23:07:00.768576 best_step = 9
4614 23:07:00.768920
4615 23:07:00.769235 ==
4616 23:07:00.771358 Dram Type= 6, Freq= 0, CH_1, rank 0
4617 23:07:00.775146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4618 23:07:00.778208 ==
4619 23:07:00.778667 RX Vref Scan: 1
4620 23:07:00.779015
4621 23:07:00.781573 RX Vref 0 -> 0, step: 1
4622 23:07:00.782006
4623 23:07:00.784725 RX Delay -179 -> 252, step: 8
4624 23:07:00.785160
4625 23:07:00.788270 Set Vref, RX VrefLevel [Byte0]: 54
4626 23:07:00.791779 [Byte1]: 54
4627 23:07:00.792212
4628 23:07:00.794895 Final RX Vref Byte 0 = 54 to rank0
4629 23:07:00.798324 Final RX Vref Byte 1 = 54 to rank0
4630 23:07:00.801318 Final RX Vref Byte 0 = 54 to rank1
4631 23:07:00.804744 Final RX Vref Byte 1 = 54 to rank1==
4632 23:07:00.807879 Dram Type= 6, Freq= 0, CH_1, rank 0
4633 23:07:00.811367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4634 23:07:00.811817 ==
4635 23:07:00.812260 DQS Delay:
4636 23:07:00.814550 DQS0 = 0, DQS1 = 0
4637 23:07:00.814636 DQM Delay:
4638 23:07:00.817322 DQM0 = 48, DQM1 = 41
4639 23:07:00.817409 DQ Delay:
4640 23:07:00.820890 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =48
4641 23:07:00.824425 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =44
4642 23:07:00.827733 DQ8 =28, DQ9 =32, DQ10 =44, DQ11 =32
4643 23:07:00.831126 DQ12 =52, DQ13 =48, DQ14 =48, DQ15 =48
4644 23:07:00.831569
4645 23:07:00.832009
4646 23:07:00.841340 [DQSOSCAuto] RK0, (LSB)MR18= 0x4970, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 396 ps
4647 23:07:00.841774 CH1 RK0: MR19=808, MR18=4970
4648 23:07:00.847711 CH1_RK0: MR19=0x808, MR18=0x4970, DQSOSC=388, MR23=63, INC=174, DEC=116
4649 23:07:00.848140
4650 23:07:00.851423 ----->DramcWriteLeveling(PI) begin...
4651 23:07:00.851931 ==
4652 23:07:00.854894 Dram Type= 6, Freq= 0, CH_1, rank 1
4653 23:07:00.861093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4654 23:07:00.861595 ==
4655 23:07:00.864917 Write leveling (Byte 0): 27 => 27
4656 23:07:00.867939 Write leveling (Byte 1): 30 => 30
4657 23:07:00.868367 DramcWriteLeveling(PI) end<-----
4658 23:07:00.871518
4659 23:07:00.872045 ==
4660 23:07:00.875029 Dram Type= 6, Freq= 0, CH_1, rank 1
4661 23:07:00.877757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4662 23:07:00.878373 ==
4663 23:07:00.881190 [Gating] SW mode calibration
4664 23:07:00.887868 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4665 23:07:00.891221 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4666 23:07:00.897947 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4667 23:07:00.901105 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4668 23:07:00.904252 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4669 23:07:00.910856 0 9 12 | B1->B0 | 3030 3232 | 0 0 | (0 1) (0 0)
4670 23:07:00.914561 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4671 23:07:00.917742 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4672 23:07:00.924378 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4673 23:07:00.927600 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4674 23:07:00.930954 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4675 23:07:00.937399 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4676 23:07:00.941264 0 10 8 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
4677 23:07:00.944069 0 10 12 | B1->B0 | 3e3e 3333 | 1 0 | (0 0) (1 1)
4678 23:07:00.950695 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4679 23:07:00.954038 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4680 23:07:00.957389 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4681 23:07:00.964161 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4682 23:07:00.967267 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4683 23:07:00.970917 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4684 23:07:00.977381 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4685 23:07:00.980522 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4686 23:07:00.984198 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4687 23:07:00.987439 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4688 23:07:00.993896 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4689 23:07:00.997321 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4690 23:07:01.000871 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4691 23:07:01.007450 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4692 23:07:01.010806 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4693 23:07:01.014209 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4694 23:07:01.020460 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4695 23:07:01.024120 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4696 23:07:01.027423 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4697 23:07:01.033854 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4698 23:07:01.037331 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4699 23:07:01.040675 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4700 23:07:01.047291 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4701 23:07:01.050571 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4702 23:07:01.054009 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4703 23:07:01.057104 Total UI for P1: 0, mck2ui 16
4704 23:07:01.060472 best dqsien dly found for B0: ( 0, 13, 12)
4705 23:07:01.063682 Total UI for P1: 0, mck2ui 16
4706 23:07:01.067158 best dqsien dly found for B1: ( 0, 13, 12)
4707 23:07:01.070570 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4708 23:07:01.073779 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4709 23:07:01.074209
4710 23:07:01.080516 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4711 23:07:01.083490 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4712 23:07:01.087016 [Gating] SW calibration Done
4713 23:07:01.087447 ==
4714 23:07:01.090305 Dram Type= 6, Freq= 0, CH_1, rank 1
4715 23:07:01.093640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4716 23:07:01.094075 ==
4717 23:07:01.094455 RX Vref Scan: 0
4718 23:07:01.094788
4719 23:07:01.097306 RX Vref 0 -> 0, step: 1
4720 23:07:01.097736
4721 23:07:01.100268 RX Delay -230 -> 252, step: 16
4722 23:07:01.103592 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4723 23:07:01.106806 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4724 23:07:01.113529 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4725 23:07:01.117309 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4726 23:07:01.120226 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4727 23:07:01.123469 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4728 23:07:01.127039 iDelay=218, Bit 6, Center 57 (-86 ~ 201) 288
4729 23:07:01.133670 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4730 23:07:01.136873 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4731 23:07:01.140327 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4732 23:07:01.143659 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4733 23:07:01.150117 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4734 23:07:01.153380 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4735 23:07:01.157130 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4736 23:07:01.160422 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4737 23:07:01.166834 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4738 23:07:01.167262 ==
4739 23:07:01.170216 Dram Type= 6, Freq= 0, CH_1, rank 1
4740 23:07:01.173524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4741 23:07:01.173969 ==
4742 23:07:01.174551 DQS Delay:
4743 23:07:01.176727 DQS0 = 0, DQS1 = 0
4744 23:07:01.177160 DQM Delay:
4745 23:07:01.180138 DQM0 = 51, DQM1 = 45
4746 23:07:01.180563 DQ Delay:
4747 23:07:01.183221 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4748 23:07:01.186727 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4749 23:07:01.190277 DQ8 =25, DQ9 =33, DQ10 =49, DQ11 =41
4750 23:07:01.193538 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4751 23:07:01.193964
4752 23:07:01.194295
4753 23:07:01.194645 ==
4754 23:07:01.197350 Dram Type= 6, Freq= 0, CH_1, rank 1
4755 23:07:01.200231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4756 23:07:01.200764 ==
4757 23:07:01.201102
4758 23:07:01.201413
4759 23:07:01.203497 TX Vref Scan disable
4760 23:07:01.206736 == TX Byte 0 ==
4761 23:07:01.209814 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4762 23:07:01.213507 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4763 23:07:01.217005 == TX Byte 1 ==
4764 23:07:01.219954 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4765 23:07:01.223474 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4766 23:07:01.224091 ==
4767 23:07:01.226614 Dram Type= 6, Freq= 0, CH_1, rank 1
4768 23:07:01.233068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4769 23:07:01.233497 ==
4770 23:07:01.233837
4771 23:07:01.234210
4772 23:07:01.234550 TX Vref Scan disable
4773 23:07:01.237546 == TX Byte 0 ==
4774 23:07:01.240810 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4775 23:07:01.247539 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4776 23:07:01.247969 == TX Byte 1 ==
4777 23:07:01.250563 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4778 23:07:01.257804 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4779 23:07:01.258336
4780 23:07:01.258715 [DATLAT]
4781 23:07:01.259031 Freq=600, CH1 RK1
4782 23:07:01.259334
4783 23:07:01.261276 DATLAT Default: 0x9
4784 23:07:01.261806 0, 0xFFFF, sum = 0
4785 23:07:01.264272 1, 0xFFFF, sum = 0
4786 23:07:01.267252 2, 0xFFFF, sum = 0
4787 23:07:01.267758 3, 0xFFFF, sum = 0
4788 23:07:01.270592 4, 0xFFFF, sum = 0
4789 23:07:01.271032 5, 0xFFFF, sum = 0
4790 23:07:01.273969 6, 0xFFFF, sum = 0
4791 23:07:01.274425 7, 0xFFFF, sum = 0
4792 23:07:01.277350 8, 0x0, sum = 1
4793 23:07:01.277781 9, 0x0, sum = 2
4794 23:07:01.278127 10, 0x0, sum = 3
4795 23:07:01.280794 11, 0x0, sum = 4
4796 23:07:01.281226 best_step = 9
4797 23:07:01.281560
4798 23:07:01.281872 ==
4799 23:07:01.283865 Dram Type= 6, Freq= 0, CH_1, rank 1
4800 23:07:01.290793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4801 23:07:01.291227 ==
4802 23:07:01.291565 RX Vref Scan: 0
4803 23:07:01.291875
4804 23:07:01.294063 RX Vref 0 -> 0, step: 1
4805 23:07:01.294542
4806 23:07:01.297250 RX Delay -179 -> 252, step: 8
4807 23:07:01.300682 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4808 23:07:01.307339 iDelay=205, Bit 1, Center 44 (-91 ~ 180) 272
4809 23:07:01.310446 iDelay=205, Bit 2, Center 40 (-99 ~ 180) 280
4810 23:07:01.313947 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4811 23:07:01.317392 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4812 23:07:01.320891 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4813 23:07:01.327391 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4814 23:07:01.330732 iDelay=205, Bit 7, Center 48 (-91 ~ 188) 280
4815 23:07:01.333749 iDelay=205, Bit 8, Center 28 (-115 ~ 172) 288
4816 23:07:01.337110 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4817 23:07:01.340414 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4818 23:07:01.347033 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4819 23:07:01.350137 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4820 23:07:01.353972 iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296
4821 23:07:01.357401 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4822 23:07:01.363666 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4823 23:07:01.364091 ==
4824 23:07:01.366965 Dram Type= 6, Freq= 0, CH_1, rank 1
4825 23:07:01.370410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4826 23:07:01.370843 ==
4827 23:07:01.371178 DQS Delay:
4828 23:07:01.373542 DQS0 = 0, DQS1 = 0
4829 23:07:01.373963 DQM Delay:
4830 23:07:01.376917 DQM0 = 49, DQM1 = 43
4831 23:07:01.377340 DQ Delay:
4832 23:07:01.380033 DQ0 =56, DQ1 =44, DQ2 =40, DQ3 =44
4833 23:07:01.383473 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4834 23:07:01.386841 DQ8 =28, DQ9 =36, DQ10 =44, DQ11 =40
4835 23:07:01.390231 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =56
4836 23:07:01.390729
4837 23:07:01.391064
4838 23:07:01.396864 [DQSOSCAuto] RK1, (LSB)MR18= 0x581d, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
4839 23:07:01.400060 CH1 RK1: MR19=808, MR18=581D
4840 23:07:01.406810 CH1_RK1: MR19=0x808, MR18=0x581D, DQSOSC=393, MR23=63, INC=169, DEC=113
4841 23:07:01.410246 [RxdqsGatingPostProcess] freq 600
4842 23:07:01.416918 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4843 23:07:01.420581 Pre-setting of DQS Precalculation
4844 23:07:01.423282 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4845 23:07:01.429948 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4846 23:07:01.436779 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4847 23:07:01.437311
4848 23:07:01.437651
4849 23:07:01.440387 [Calibration Summary] 1200 Mbps
4850 23:07:01.443112 CH 0, Rank 0
4851 23:07:01.443539 SW Impedance : PASS
4852 23:07:01.446659 DUTY Scan : NO K
4853 23:07:01.449797 ZQ Calibration : PASS
4854 23:07:01.450226 Jitter Meter : NO K
4855 23:07:01.453428 CBT Training : PASS
4856 23:07:01.456735 Write leveling : PASS
4857 23:07:01.457165 RX DQS gating : PASS
4858 23:07:01.460097 RX DQ/DQS(RDDQC) : PASS
4859 23:07:01.463302 TX DQ/DQS : PASS
4860 23:07:01.463832 RX DATLAT : PASS
4861 23:07:01.466630 RX DQ/DQS(Engine): PASS
4862 23:07:01.467168 TX OE : NO K
4863 23:07:01.469857 All Pass.
4864 23:07:01.470556
4865 23:07:01.470965 CH 0, Rank 1
4866 23:07:01.472990 SW Impedance : PASS
4867 23:07:01.473535 DUTY Scan : NO K
4868 23:07:01.476531 ZQ Calibration : PASS
4869 23:07:01.479878 Jitter Meter : NO K
4870 23:07:01.480336 CBT Training : PASS
4871 23:07:01.482984 Write leveling : PASS
4872 23:07:01.486224 RX DQS gating : PASS
4873 23:07:01.486739 RX DQ/DQS(RDDQC) : PASS
4874 23:07:01.489949 TX DQ/DQS : PASS
4875 23:07:01.493142 RX DATLAT : PASS
4876 23:07:01.493571 RX DQ/DQS(Engine): PASS
4877 23:07:01.496241 TX OE : NO K
4878 23:07:01.496672 All Pass.
4879 23:07:01.497011
4880 23:07:01.499626 CH 1, Rank 0
4881 23:07:01.500055 SW Impedance : PASS
4882 23:07:01.502882 DUTY Scan : NO K
4883 23:07:01.506450 ZQ Calibration : PASS
4884 23:07:01.506905 Jitter Meter : NO K
4885 23:07:01.509682 CBT Training : PASS
4886 23:07:01.513350 Write leveling : PASS
4887 23:07:01.513780 RX DQS gating : PASS
4888 23:07:01.516236 RX DQ/DQS(RDDQC) : PASS
4889 23:07:01.516662 TX DQ/DQS : PASS
4890 23:07:01.519685 RX DATLAT : PASS
4891 23:07:01.522892 RX DQ/DQS(Engine): PASS
4892 23:07:01.523324 TX OE : NO K
4893 23:07:01.526091 All Pass.
4894 23:07:01.526535
4895 23:07:01.526873 CH 1, Rank 1
4896 23:07:01.529677 SW Impedance : PASS
4897 23:07:01.530100 DUTY Scan : NO K
4898 23:07:01.532741 ZQ Calibration : PASS
4899 23:07:01.536073 Jitter Meter : NO K
4900 23:07:01.536502 CBT Training : PASS
4901 23:07:01.539766 Write leveling : PASS
4902 23:07:01.542863 RX DQS gating : PASS
4903 23:07:01.543290 RX DQ/DQS(RDDQC) : PASS
4904 23:07:01.546228 TX DQ/DQS : PASS
4905 23:07:01.549443 RX DATLAT : PASS
4906 23:07:01.549868 RX DQ/DQS(Engine): PASS
4907 23:07:01.552747 TX OE : NO K
4908 23:07:01.553181 All Pass.
4909 23:07:01.553519
4910 23:07:01.556558 DramC Write-DBI off
4911 23:07:01.559085 PER_BANK_REFRESH: Hybrid Mode
4912 23:07:01.559386 TX_TRACKING: ON
4913 23:07:01.569068 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4914 23:07:01.572790 [FAST_K] Save calibration result to emmc
4915 23:07:01.575771 dramc_set_vcore_voltage set vcore to 662500
4916 23:07:01.579134 Read voltage for 933, 3
4917 23:07:01.579218 Vio18 = 0
4918 23:07:01.579283 Vcore = 662500
4919 23:07:01.582369 Vdram = 0
4920 23:07:01.582489 Vddq = 0
4921 23:07:01.582554 Vmddr = 0
4922 23:07:01.589098 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4923 23:07:01.592223 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4924 23:07:01.595530 MEM_TYPE=3, freq_sel=17
4925 23:07:01.599149 sv_algorithm_assistance_LP4_1600
4926 23:07:01.602296 ============ PULL DRAM RESETB DOWN ============
4927 23:07:01.605596 ========== PULL DRAM RESETB DOWN end =========
4928 23:07:01.612430 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4929 23:07:01.615998 ===================================
4930 23:07:01.616084 LPDDR4 DRAM CONFIGURATION
4931 23:07:01.618772 ===================================
4932 23:07:01.622110 EX_ROW_EN[0] = 0x0
4933 23:07:01.625781 EX_ROW_EN[1] = 0x0
4934 23:07:01.625856 LP4Y_EN = 0x0
4935 23:07:01.629082 WORK_FSP = 0x0
4936 23:07:01.629161 WL = 0x3
4937 23:07:01.632412 RL = 0x3
4938 23:07:01.632485 BL = 0x2
4939 23:07:01.635392 RPST = 0x0
4940 23:07:01.635476 RD_PRE = 0x0
4941 23:07:01.638806 WR_PRE = 0x1
4942 23:07:01.638878 WR_PST = 0x0
4943 23:07:01.642002 DBI_WR = 0x0
4944 23:07:01.642073 DBI_RD = 0x0
4945 23:07:01.645472 OTF = 0x1
4946 23:07:01.648600 ===================================
4947 23:07:01.652182 ===================================
4948 23:07:01.652257 ANA top config
4949 23:07:01.655279 ===================================
4950 23:07:01.658637 DLL_ASYNC_EN = 0
4951 23:07:01.661963 ALL_SLAVE_EN = 1
4952 23:07:01.665700 NEW_RANK_MODE = 1
4953 23:07:01.665774 DLL_IDLE_MODE = 1
4954 23:07:01.668496 LP45_APHY_COMB_EN = 1
4955 23:07:01.671820 TX_ODT_DIS = 1
4956 23:07:01.675299 NEW_8X_MODE = 1
4957 23:07:01.678554 ===================================
4958 23:07:01.682061 ===================================
4959 23:07:01.682145 data_rate = 1866
4960 23:07:01.685555 CKR = 1
4961 23:07:01.688695 DQ_P2S_RATIO = 8
4962 23:07:01.691878 ===================================
4963 23:07:01.695285 CA_P2S_RATIO = 8
4964 23:07:01.698618 DQ_CA_OPEN = 0
4965 23:07:01.701895 DQ_SEMI_OPEN = 0
4966 23:07:01.701969 CA_SEMI_OPEN = 0
4967 23:07:01.705092 CA_FULL_RATE = 0
4968 23:07:01.708700 DQ_CKDIV4_EN = 1
4969 23:07:01.711761 CA_CKDIV4_EN = 1
4970 23:07:01.715290 CA_PREDIV_EN = 0
4971 23:07:01.718652 PH8_DLY = 0
4972 23:07:01.718730 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4973 23:07:01.721735 DQ_AAMCK_DIV = 4
4974 23:07:01.724990 CA_AAMCK_DIV = 4
4975 23:07:01.728718 CA_ADMCK_DIV = 4
4976 23:07:01.731910 DQ_TRACK_CA_EN = 0
4977 23:07:01.735346 CA_PICK = 933
4978 23:07:01.738358 CA_MCKIO = 933
4979 23:07:01.738455 MCKIO_SEMI = 0
4980 23:07:01.741591 PLL_FREQ = 3732
4981 23:07:01.744973 DQ_UI_PI_RATIO = 32
4982 23:07:01.748390 CA_UI_PI_RATIO = 0
4983 23:07:01.751940 ===================================
4984 23:07:01.755271 ===================================
4985 23:07:01.758722 memory_type:LPDDR4
4986 23:07:01.758797 GP_NUM : 10
4987 23:07:01.761786 SRAM_EN : 1
4988 23:07:01.761869 MD32_EN : 0
4989 23:07:01.765399 ===================================
4990 23:07:01.768469 [ANA_INIT] >>>>>>>>>>>>>>
4991 23:07:01.772030 <<<<<< [CONFIGURE PHASE]: ANA_TX
4992 23:07:01.775450 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4993 23:07:01.778322 ===================================
4994 23:07:01.782059 data_rate = 1866,PCW = 0X8f00
4995 23:07:01.785246 ===================================
4996 23:07:01.788663 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4997 23:07:01.795480 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4998 23:07:01.798684 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4999 23:07:01.805474 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5000 23:07:01.808719 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5001 23:07:01.811875 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5002 23:07:01.812306 [ANA_INIT] flow start
5003 23:07:01.815365 [ANA_INIT] PLL >>>>>>>>
5004 23:07:01.818510 [ANA_INIT] PLL <<<<<<<<
5005 23:07:01.818964 [ANA_INIT] MIDPI >>>>>>>>
5006 23:07:01.822045 [ANA_INIT] MIDPI <<<<<<<<
5007 23:07:01.825189 [ANA_INIT] DLL >>>>>>>>
5008 23:07:01.825618 [ANA_INIT] flow end
5009 23:07:01.831952 ============ LP4 DIFF to SE enter ============
5010 23:07:01.835425 ============ LP4 DIFF to SE exit ============
5011 23:07:01.838177 [ANA_INIT] <<<<<<<<<<<<<
5012 23:07:01.841441 [Flow] Enable top DCM control >>>>>
5013 23:07:01.844948 [Flow] Enable top DCM control <<<<<
5014 23:07:01.845379 Enable DLL master slave shuffle
5015 23:07:01.851856 ==============================================================
5016 23:07:01.855248 Gating Mode config
5017 23:07:01.858460 ==============================================================
5018 23:07:01.861671 Config description:
5019 23:07:01.871227 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5020 23:07:01.878196 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5021 23:07:01.881679 SELPH_MODE 0: By rank 1: By Phase
5022 23:07:01.887881 ==============================================================
5023 23:07:01.891339 GAT_TRACK_EN = 1
5024 23:07:01.894495 RX_GATING_MODE = 2
5025 23:07:01.898089 RX_GATING_TRACK_MODE = 2
5026 23:07:01.901184 SELPH_MODE = 1
5027 23:07:01.904240 PICG_EARLY_EN = 1
5028 23:07:01.904767 VALID_LAT_VALUE = 1
5029 23:07:01.911199 ==============================================================
5030 23:07:01.914826 Enter into Gating configuration >>>>
5031 23:07:01.917506 Exit from Gating configuration <<<<
5032 23:07:01.920945 Enter into DVFS_PRE_config >>>>>
5033 23:07:01.930806 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5034 23:07:01.934100 Exit from DVFS_PRE_config <<<<<
5035 23:07:01.937237 Enter into PICG configuration >>>>
5036 23:07:01.940747 Exit from PICG configuration <<<<
5037 23:07:01.944119 [RX_INPUT] configuration >>>>>
5038 23:07:01.947413 [RX_INPUT] configuration <<<<<
5039 23:07:01.954474 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5040 23:07:01.957696 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5041 23:07:01.964086 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5042 23:07:01.970482 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5043 23:07:01.977367 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5044 23:07:01.983967 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5045 23:07:01.987336 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5046 23:07:01.990340 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5047 23:07:01.993603 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5048 23:07:02.000423 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5049 23:07:02.004038 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5050 23:07:02.006842 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5051 23:07:02.010677 ===================================
5052 23:07:02.013683 LPDDR4 DRAM CONFIGURATION
5053 23:07:02.017333 ===================================
5054 23:07:02.017758 EX_ROW_EN[0] = 0x0
5055 23:07:02.020366 EX_ROW_EN[1] = 0x0
5056 23:07:02.023855 LP4Y_EN = 0x0
5057 23:07:02.024332 WORK_FSP = 0x0
5058 23:07:02.027036 WL = 0x3
5059 23:07:02.027460 RL = 0x3
5060 23:07:02.030108 BL = 0x2
5061 23:07:02.030558 RPST = 0x0
5062 23:07:02.033769 RD_PRE = 0x0
5063 23:07:02.034298 WR_PRE = 0x1
5064 23:07:02.036776 WR_PST = 0x0
5065 23:07:02.037211 DBI_WR = 0x0
5066 23:07:02.040189 DBI_RD = 0x0
5067 23:07:02.040666 OTF = 0x1
5068 23:07:02.043205 ===================================
5069 23:07:02.046693 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5070 23:07:02.053427 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5071 23:07:02.056759 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5072 23:07:02.059757 ===================================
5073 23:07:02.063416 LPDDR4 DRAM CONFIGURATION
5074 23:07:02.066566 ===================================
5075 23:07:02.067159 EX_ROW_EN[0] = 0x10
5076 23:07:02.069740 EX_ROW_EN[1] = 0x0
5077 23:07:02.072850 LP4Y_EN = 0x0
5078 23:07:02.073352 WORK_FSP = 0x0
5079 23:07:02.076350 WL = 0x3
5080 23:07:02.076783 RL = 0x3
5081 23:07:02.079688 BL = 0x2
5082 23:07:02.080120 RPST = 0x0
5083 23:07:02.083073 RD_PRE = 0x0
5084 23:07:02.083507 WR_PRE = 0x1
5085 23:07:02.086458 WR_PST = 0x0
5086 23:07:02.086889 DBI_WR = 0x0
5087 23:07:02.089652 DBI_RD = 0x0
5088 23:07:02.090069 OTF = 0x1
5089 23:07:02.093014 ===================================
5090 23:07:02.099529 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5091 23:07:02.104217 nWR fixed to 30
5092 23:07:02.107121 [ModeRegInit_LP4] CH0 RK0
5093 23:07:02.107588 [ModeRegInit_LP4] CH0 RK1
5094 23:07:02.111034 [ModeRegInit_LP4] CH1 RK0
5095 23:07:02.113952 [ModeRegInit_LP4] CH1 RK1
5096 23:07:02.114614 match AC timing 9
5097 23:07:02.120911 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5098 23:07:02.123956 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5099 23:07:02.127851 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5100 23:07:02.133785 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5101 23:07:02.137442 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5102 23:07:02.137920 ==
5103 23:07:02.140708 Dram Type= 6, Freq= 0, CH_0, rank 0
5104 23:07:02.144638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5105 23:07:02.145086 ==
5106 23:07:02.150279 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5107 23:07:02.156924 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5108 23:07:02.160515 [CA 0] Center 37 (7~68) winsize 62
5109 23:07:02.163498 [CA 1] Center 37 (7~68) winsize 62
5110 23:07:02.166994 [CA 2] Center 35 (5~66) winsize 62
5111 23:07:02.170298 [CA 3] Center 34 (4~65) winsize 62
5112 23:07:02.173460 [CA 4] Center 34 (4~65) winsize 62
5113 23:07:02.177056 [CA 5] Center 33 (3~64) winsize 62
5114 23:07:02.177433
5115 23:07:02.180226 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5116 23:07:02.180595
5117 23:07:02.183594 [CATrainingPosCal] consider 1 rank data
5118 23:07:02.186999 u2DelayCellTimex100 = 270/100 ps
5119 23:07:02.190518 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5120 23:07:02.193854 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5121 23:07:02.197382 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5122 23:07:02.201000 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5123 23:07:02.203717 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5124 23:07:02.206823 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5125 23:07:02.210261
5126 23:07:02.213316 CA PerBit enable=1, Macro0, CA PI delay=33
5127 23:07:02.213795
5128 23:07:02.217092 [CBTSetCACLKResult] CA Dly = 33
5129 23:07:02.217666 CS Dly: 7 (0~38)
5130 23:07:02.218050 ==
5131 23:07:02.220249 Dram Type= 6, Freq= 0, CH_0, rank 1
5132 23:07:02.223714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5133 23:07:02.224289 ==
5134 23:07:02.230064 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5135 23:07:02.237217 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5136 23:07:02.239974 [CA 0] Center 38 (7~69) winsize 63
5137 23:07:02.243596 [CA 1] Center 38 (8~69) winsize 62
5138 23:07:02.246690 [CA 2] Center 36 (6~66) winsize 61
5139 23:07:02.249840 [CA 3] Center 35 (5~66) winsize 62
5140 23:07:02.253230 [CA 4] Center 34 (4~65) winsize 62
5141 23:07:02.256651 [CA 5] Center 34 (4~64) winsize 61
5142 23:07:02.257098
5143 23:07:02.259824 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5144 23:07:02.260314
5145 23:07:02.263395 [CATrainingPosCal] consider 2 rank data
5146 23:07:02.266456 u2DelayCellTimex100 = 270/100 ps
5147 23:07:02.269633 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5148 23:07:02.273282 CA1 delay=38 (8~68),Diff = 4 PI (24 cell)
5149 23:07:02.276119 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5150 23:07:02.279445 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5151 23:07:02.282843 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5152 23:07:02.289764 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5153 23:07:02.289869
5154 23:07:02.292845 CA PerBit enable=1, Macro0, CA PI delay=34
5155 23:07:02.292918
5156 23:07:02.296182 [CBTSetCACLKResult] CA Dly = 34
5157 23:07:02.296253 CS Dly: 7 (0~39)
5158 23:07:02.296314
5159 23:07:02.299697 ----->DramcWriteLeveling(PI) begin...
5160 23:07:02.299768 ==
5161 23:07:02.302790 Dram Type= 6, Freq= 0, CH_0, rank 0
5162 23:07:02.309430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5163 23:07:02.309533 ==
5164 23:07:02.312701 Write leveling (Byte 0): 34 => 34
5165 23:07:02.312780 Write leveling (Byte 1): 29 => 29
5166 23:07:02.316480 DramcWriteLeveling(PI) end<-----
5167 23:07:02.316554
5168 23:07:02.316623 ==
5169 23:07:02.319650 Dram Type= 6, Freq= 0, CH_0, rank 0
5170 23:07:02.325830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5171 23:07:02.325927 ==
5172 23:07:02.329569 [Gating] SW mode calibration
5173 23:07:02.336024 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5174 23:07:02.339597 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5175 23:07:02.345879 0 14 0 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
5176 23:07:02.349216 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5177 23:07:02.352927 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5178 23:07:02.359523 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5179 23:07:02.362632 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5180 23:07:02.366341 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5181 23:07:02.372987 0 14 24 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
5182 23:07:02.375941 0 14 28 | B1->B0 | 3232 2323 | 0 0 | (0 1) (1 0)
5183 23:07:02.379489 0 15 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5184 23:07:02.385765 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5185 23:07:02.389599 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5186 23:07:02.392367 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5187 23:07:02.396013 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5188 23:07:02.402552 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5189 23:07:02.405810 0 15 24 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
5190 23:07:02.409084 0 15 28 | B1->B0 | 2e2e 4545 | 0 0 | (0 0) (0 0)
5191 23:07:02.416095 1 0 0 | B1->B0 | 4342 4646 | 1 0 | (0 0) (0 0)
5192 23:07:02.419412 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5193 23:07:02.422473 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5194 23:07:02.429371 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5195 23:07:02.432850 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5196 23:07:02.435774 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5197 23:07:02.442746 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5198 23:07:02.445897 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5199 23:07:02.449564 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5200 23:07:02.456307 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5201 23:07:02.459247 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5202 23:07:02.462374 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5203 23:07:02.469311 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5204 23:07:02.472327 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5205 23:07:02.475755 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5206 23:07:02.482691 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5207 23:07:02.485715 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5208 23:07:02.489026 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5209 23:07:02.496055 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5210 23:07:02.499020 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5211 23:07:02.502865 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5212 23:07:02.509338 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5213 23:07:02.512409 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5214 23:07:02.515918 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5215 23:07:02.522240 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5216 23:07:02.522841 Total UI for P1: 0, mck2ui 16
5217 23:07:02.525730 best dqsien dly found for B0: ( 1, 2, 26)
5218 23:07:02.528741 Total UI for P1: 0, mck2ui 16
5219 23:07:02.532255 best dqsien dly found for B1: ( 1, 2, 30)
5220 23:07:02.538829 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5221 23:07:02.542275 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5222 23:07:02.542757
5223 23:07:02.545523 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5224 23:07:02.548782 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5225 23:07:02.552429 [Gating] SW calibration Done
5226 23:07:02.552867 ==
5227 23:07:02.555384 Dram Type= 6, Freq= 0, CH_0, rank 0
5228 23:07:02.559141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5229 23:07:02.559630 ==
5230 23:07:02.562268 RX Vref Scan: 0
5231 23:07:02.562799
5232 23:07:02.563235 RX Vref 0 -> 0, step: 1
5233 23:07:02.563706
5234 23:07:02.565449 RX Delay -80 -> 252, step: 8
5235 23:07:02.568719 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5236 23:07:02.575290 iDelay=208, Bit 1, Center 111 (24 ~ 199) 176
5237 23:07:02.579278 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5238 23:07:02.582249 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5239 23:07:02.585499 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5240 23:07:02.588787 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5241 23:07:02.592312 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5242 23:07:02.595893 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5243 23:07:02.602552 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5244 23:07:02.605662 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5245 23:07:02.608712 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5246 23:07:02.612465 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5247 23:07:02.615405 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5248 23:07:02.618727 iDelay=208, Bit 13, Center 95 (8 ~ 183) 176
5249 23:07:02.625368 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5250 23:07:02.628921 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5251 23:07:02.629350 ==
5252 23:07:02.632010 Dram Type= 6, Freq= 0, CH_0, rank 0
5253 23:07:02.635430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5254 23:07:02.635864 ==
5255 23:07:02.638807 DQS Delay:
5256 23:07:02.639237 DQS0 = 0, DQS1 = 0
5257 23:07:02.639573 DQM Delay:
5258 23:07:02.642211 DQM0 = 105, DQM1 = 91
5259 23:07:02.642673 DQ Delay:
5260 23:07:02.645467 DQ0 =107, DQ1 =111, DQ2 =99, DQ3 =99
5261 23:07:02.648486 DQ4 =107, DQ5 =91, DQ6 =115, DQ7 =115
5262 23:07:02.652000 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5263 23:07:02.655183 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =99
5264 23:07:02.655612
5265 23:07:02.655946
5266 23:07:02.656256 ==
5267 23:07:02.658769 Dram Type= 6, Freq= 0, CH_0, rank 0
5268 23:07:02.665042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5269 23:07:02.665547 ==
5270 23:07:02.666006
5271 23:07:02.666440
5272 23:07:02.668485 TX Vref Scan disable
5273 23:07:02.668974 == TX Byte 0 ==
5274 23:07:02.672006 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5275 23:07:02.678729 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5276 23:07:02.679275 == TX Byte 1 ==
5277 23:07:02.682004 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5278 23:07:02.688541 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5279 23:07:02.688973 ==
5280 23:07:02.692142 Dram Type= 6, Freq= 0, CH_0, rank 0
5281 23:07:02.695437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5282 23:07:02.695896 ==
5283 23:07:02.696247
5284 23:07:02.696561
5285 23:07:02.698327 TX Vref Scan disable
5286 23:07:02.701709 == TX Byte 0 ==
5287 23:07:02.704870 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5288 23:07:02.708210 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5289 23:07:02.711798 == TX Byte 1 ==
5290 23:07:02.715213 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5291 23:07:02.718292 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5292 23:07:02.718443
5293 23:07:02.718512 [DATLAT]
5294 23:07:02.721496 Freq=933, CH0 RK0
5295 23:07:02.721581
5296 23:07:02.724707 DATLAT Default: 0xd
5297 23:07:02.724791 0, 0xFFFF, sum = 0
5298 23:07:02.728351 1, 0xFFFF, sum = 0
5299 23:07:02.728788 2, 0xFFFF, sum = 0
5300 23:07:02.731471 3, 0xFFFF, sum = 0
5301 23:07:02.731556 4, 0xFFFF, sum = 0
5302 23:07:02.734481 5, 0xFFFF, sum = 0
5303 23:07:02.734566 6, 0xFFFF, sum = 0
5304 23:07:02.737879 7, 0xFFFF, sum = 0
5305 23:07:02.737965 8, 0xFFFF, sum = 0
5306 23:07:02.741360 9, 0xFFFF, sum = 0
5307 23:07:02.741444 10, 0x0, sum = 1
5308 23:07:02.744663 11, 0x0, sum = 2
5309 23:07:02.744749 12, 0x0, sum = 3
5310 23:07:02.747930 13, 0x0, sum = 4
5311 23:07:02.748015 best_step = 11
5312 23:07:02.748081
5313 23:07:02.748140 ==
5314 23:07:02.751248 Dram Type= 6, Freq= 0, CH_0, rank 0
5315 23:07:02.754490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5316 23:07:02.754575 ==
5317 23:07:02.758119 RX Vref Scan: 1
5318 23:07:02.758202
5319 23:07:02.761393 RX Vref 0 -> 0, step: 1
5320 23:07:02.761477
5321 23:07:02.761542 RX Delay -53 -> 252, step: 4
5322 23:07:02.761604
5323 23:07:02.764551 Set Vref, RX VrefLevel [Byte0]: 57
5324 23:07:02.768087 [Byte1]: 50
5325 23:07:02.772536
5326 23:07:02.772623 Final RX Vref Byte 0 = 57 to rank0
5327 23:07:02.775923 Final RX Vref Byte 1 = 50 to rank0
5328 23:07:02.779515 Final RX Vref Byte 0 = 57 to rank1
5329 23:07:02.782580 Final RX Vref Byte 1 = 50 to rank1==
5330 23:07:02.785903 Dram Type= 6, Freq= 0, CH_0, rank 0
5331 23:07:02.792771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5332 23:07:02.792862 ==
5333 23:07:02.792933 DQS Delay:
5334 23:07:02.792999 DQS0 = 0, DQS1 = 0
5335 23:07:02.795931 DQM Delay:
5336 23:07:02.796021 DQM0 = 107, DQM1 = 92
5337 23:07:02.799442 DQ Delay:
5338 23:07:02.802925 DQ0 =106, DQ1 =108, DQ2 =104, DQ3 =104
5339 23:07:02.805810 DQ4 =110, DQ5 =100, DQ6 =116, DQ7 =112
5340 23:07:02.809375 DQ8 =82, DQ9 =78, DQ10 =94, DQ11 =92
5341 23:07:02.812638 DQ12 =96, DQ13 =92, DQ14 =104, DQ15 =98
5342 23:07:02.812804
5343 23:07:02.812906
5344 23:07:02.818893 [DQSOSCAuto] RK0, (LSB)MR18= 0x2824, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 409 ps
5345 23:07:02.822413 CH0 RK0: MR19=505, MR18=2824
5346 23:07:02.829068 CH0_RK0: MR19=0x505, MR18=0x2824, DQSOSC=409, MR23=63, INC=64, DEC=43
5347 23:07:02.829257
5348 23:07:02.832484 ----->DramcWriteLeveling(PI) begin...
5349 23:07:02.832702 ==
5350 23:07:02.835609 Dram Type= 6, Freq= 0, CH_0, rank 1
5351 23:07:02.839329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5352 23:07:02.839585 ==
5353 23:07:02.842758 Write leveling (Byte 0): 34 => 34
5354 23:07:02.845658 Write leveling (Byte 1): 29 => 29
5355 23:07:02.849165 DramcWriteLeveling(PI) end<-----
5356 23:07:02.849609
5357 23:07:02.850050 ==
5358 23:07:02.852396 Dram Type= 6, Freq= 0, CH_0, rank 1
5359 23:07:02.859427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5360 23:07:02.859983 ==
5361 23:07:02.860457 [Gating] SW mode calibration
5362 23:07:02.868883 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5363 23:07:02.872157 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5364 23:07:02.875800 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5365 23:07:02.882280 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5366 23:07:02.885872 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5367 23:07:02.888839 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5368 23:07:02.895253 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5369 23:07:02.898702 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5370 23:07:02.902312 0 14 24 | B1->B0 | 3434 3232 | 0 0 | (0 0) (0 0)
5371 23:07:02.908717 0 14 28 | B1->B0 | 3030 2424 | 0 0 | (0 1) (1 1)
5372 23:07:02.912316 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5373 23:07:02.915687 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5374 23:07:02.921925 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5375 23:07:02.925205 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5376 23:07:02.928431 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5377 23:07:02.935258 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5378 23:07:02.938733 0 15 24 | B1->B0 | 2727 2c2c | 0 0 | (1 1) (0 0)
5379 23:07:02.942357 0 15 28 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
5380 23:07:02.948160 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5381 23:07:02.951532 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5382 23:07:02.955240 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5383 23:07:02.961422 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5384 23:07:02.964880 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5385 23:07:02.968110 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5386 23:07:02.974586 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5387 23:07:02.977548 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5388 23:07:02.981209 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 23:07:02.987751 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 23:07:02.991206 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 23:07:02.994576 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 23:07:03.001444 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5393 23:07:03.004426 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 23:07:03.008053 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 23:07:03.014220 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 23:07:03.017373 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5397 23:07:03.021197 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5398 23:07:03.027540 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5399 23:07:03.030898 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5400 23:07:03.034531 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5401 23:07:03.041077 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5402 23:07:03.044382 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5403 23:07:03.047686 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5404 23:07:03.054061 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5405 23:07:03.054144 Total UI for P1: 0, mck2ui 16
5406 23:07:03.057505 best dqsien dly found for B0: ( 1, 2, 28)
5407 23:07:03.064248 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5408 23:07:03.067382 Total UI for P1: 0, mck2ui 16
5409 23:07:03.071067 best dqsien dly found for B1: ( 1, 2, 30)
5410 23:07:03.073878 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5411 23:07:03.077395 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5412 23:07:03.077478
5413 23:07:03.080730 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5414 23:07:03.084149 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5415 23:07:03.087175 [Gating] SW calibration Done
5416 23:07:03.087258 ==
5417 23:07:03.090374 Dram Type= 6, Freq= 0, CH_0, rank 1
5418 23:07:03.093833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5419 23:07:03.093916 ==
5420 23:07:03.097267 RX Vref Scan: 0
5421 23:07:03.097354
5422 23:07:03.100574 RX Vref 0 -> 0, step: 1
5423 23:07:03.100661
5424 23:07:03.100748 RX Delay -80 -> 252, step: 8
5425 23:07:03.107672 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5426 23:07:03.110421 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5427 23:07:03.113834 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5428 23:07:03.117304 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5429 23:07:03.120443 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5430 23:07:03.124102 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5431 23:07:03.130419 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5432 23:07:03.133708 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5433 23:07:03.137004 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5434 23:07:03.140161 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5435 23:07:03.143657 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5436 23:07:03.150001 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5437 23:07:03.153522 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5438 23:07:03.156882 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5439 23:07:03.160474 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5440 23:07:03.163550 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5441 23:07:03.163644 ==
5442 23:07:03.166869 Dram Type= 6, Freq= 0, CH_0, rank 1
5443 23:07:03.170766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5444 23:07:03.173832 ==
5445 23:07:03.173941 DQS Delay:
5446 23:07:03.174048 DQS0 = 0, DQS1 = 0
5447 23:07:03.177313 DQM Delay:
5448 23:07:03.177431 DQM0 = 104, DQM1 = 90
5449 23:07:03.180376 DQ Delay:
5450 23:07:03.183491 DQ0 =103, DQ1 =103, DQ2 =99, DQ3 =99
5451 23:07:03.187120 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =111
5452 23:07:03.190240 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5453 23:07:03.193721 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =99
5454 23:07:03.193898
5455 23:07:03.194057
5456 23:07:03.194246 ==
5457 23:07:03.197323 Dram Type= 6, Freq= 0, CH_0, rank 1
5458 23:07:03.200478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5459 23:07:03.200663 ==
5460 23:07:03.200848
5461 23:07:03.201019
5462 23:07:03.203757 TX Vref Scan disable
5463 23:07:03.203972 == TX Byte 0 ==
5464 23:07:03.210486 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5465 23:07:03.213718 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5466 23:07:03.214038 == TX Byte 1 ==
5467 23:07:03.220521 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5468 23:07:03.223827 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5469 23:07:03.224264 ==
5470 23:07:03.227450 Dram Type= 6, Freq= 0, CH_0, rank 1
5471 23:07:03.230578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5472 23:07:03.231016 ==
5473 23:07:03.231357
5474 23:07:03.233775
5475 23:07:03.234222 TX Vref Scan disable
5476 23:07:03.237179 == TX Byte 0 ==
5477 23:07:03.240607 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5478 23:07:03.244524 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5479 23:07:03.247369 == TX Byte 1 ==
5480 23:07:03.250898 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5481 23:07:03.253840 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5482 23:07:03.254225
5483 23:07:03.257273 [DATLAT]
5484 23:07:03.257770 Freq=933, CH0 RK1
5485 23:07:03.258208
5486 23:07:03.260603 DATLAT Default: 0xb
5487 23:07:03.261049 0, 0xFFFF, sum = 0
5488 23:07:03.263820 1, 0xFFFF, sum = 0
5489 23:07:03.264254 2, 0xFFFF, sum = 0
5490 23:07:03.267305 3, 0xFFFF, sum = 0
5491 23:07:03.267759 4, 0xFFFF, sum = 0
5492 23:07:03.270686 5, 0xFFFF, sum = 0
5493 23:07:03.271150 6, 0xFFFF, sum = 0
5494 23:07:03.274276 7, 0xFFFF, sum = 0
5495 23:07:03.274735 8, 0xFFFF, sum = 0
5496 23:07:03.277480 9, 0xFFFF, sum = 0
5497 23:07:03.277912 10, 0x0, sum = 1
5498 23:07:03.280630 11, 0x0, sum = 2
5499 23:07:03.281060 12, 0x0, sum = 3
5500 23:07:03.283827 13, 0x0, sum = 4
5501 23:07:03.284255 best_step = 11
5502 23:07:03.284590
5503 23:07:03.284901 ==
5504 23:07:03.287127 Dram Type= 6, Freq= 0, CH_0, rank 1
5505 23:07:03.293885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5506 23:07:03.294313 ==
5507 23:07:03.294696 RX Vref Scan: 0
5508 23:07:03.295014
5509 23:07:03.297401 RX Vref 0 -> 0, step: 1
5510 23:07:03.297828
5511 23:07:03.300285 RX Delay -53 -> 252, step: 4
5512 23:07:03.303923 iDelay=199, Bit 0, Center 102 (15 ~ 190) 176
5513 23:07:03.310481 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5514 23:07:03.313848 iDelay=199, Bit 2, Center 100 (15 ~ 186) 172
5515 23:07:03.316706 iDelay=199, Bit 3, Center 100 (19 ~ 182) 164
5516 23:07:03.320350 iDelay=199, Bit 4, Center 104 (19 ~ 190) 172
5517 23:07:03.323615 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5518 23:07:03.326884 iDelay=199, Bit 6, Center 114 (31 ~ 198) 168
5519 23:07:03.333520 iDelay=199, Bit 7, Center 110 (23 ~ 198) 176
5520 23:07:03.336696 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5521 23:07:03.340444 iDelay=199, Bit 9, Center 78 (-5 ~ 162) 168
5522 23:07:03.343693 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5523 23:07:03.346736 iDelay=199, Bit 11, Center 92 (11 ~ 174) 164
5524 23:07:03.353523 iDelay=199, Bit 12, Center 98 (15 ~ 182) 168
5525 23:07:03.356912 iDelay=199, Bit 13, Center 96 (15 ~ 178) 164
5526 23:07:03.360090 iDelay=199, Bit 14, Center 100 (15 ~ 186) 172
5527 23:07:03.363441 iDelay=199, Bit 15, Center 98 (15 ~ 182) 168
5528 23:07:03.363866 ==
5529 23:07:03.366740 Dram Type= 6, Freq= 0, CH_0, rank 1
5530 23:07:03.373206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5531 23:07:03.373675 ==
5532 23:07:03.374032 DQS Delay:
5533 23:07:03.374348 DQS0 = 0, DQS1 = 0
5534 23:07:03.376539 DQM Delay:
5535 23:07:03.376962 DQM0 = 104, DQM1 = 92
5536 23:07:03.380033 DQ Delay:
5537 23:07:03.383129 DQ0 =102, DQ1 =106, DQ2 =100, DQ3 =100
5538 23:07:03.386662 DQ4 =104, DQ5 =98, DQ6 =114, DQ7 =110
5539 23:07:03.390000 DQ8 =84, DQ9 =78, DQ10 =94, DQ11 =92
5540 23:07:03.393355 DQ12 =98, DQ13 =96, DQ14 =100, DQ15 =98
5541 23:07:03.393777
5542 23:07:03.394112
5543 23:07:03.400294 [DQSOSCAuto] RK1, (LSB)MR18= 0x2707, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 409 ps
5544 23:07:03.403406 CH0 RK1: MR19=505, MR18=2707
5545 23:07:03.409761 CH0_RK1: MR19=0x505, MR18=0x2707, DQSOSC=409, MR23=63, INC=64, DEC=43
5546 23:07:03.412867 [RxdqsGatingPostProcess] freq 933
5547 23:07:03.419963 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5548 23:07:03.420392 best DQS0 dly(2T, 0.5T) = (0, 10)
5549 23:07:03.423145 best DQS1 dly(2T, 0.5T) = (0, 10)
5550 23:07:03.426318 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5551 23:07:03.429730 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5552 23:07:03.432837 best DQS0 dly(2T, 0.5T) = (0, 10)
5553 23:07:03.436577 best DQS1 dly(2T, 0.5T) = (0, 10)
5554 23:07:03.439549 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5555 23:07:03.443016 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5556 23:07:03.446484 Pre-setting of DQS Precalculation
5557 23:07:03.453427 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5558 23:07:03.453884 ==
5559 23:07:03.456039 Dram Type= 6, Freq= 0, CH_1, rank 0
5560 23:07:03.459537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5561 23:07:03.459986 ==
5562 23:07:03.466339 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5563 23:07:03.469612 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5564 23:07:03.473364 [CA 0] Center 37 (7~68) winsize 62
5565 23:07:03.476720 [CA 1] Center 37 (7~68) winsize 62
5566 23:07:03.480103 [CA 2] Center 35 (5~65) winsize 61
5567 23:07:03.483163 [CA 3] Center 34 (4~65) winsize 62
5568 23:07:03.486351 [CA 4] Center 34 (4~65) winsize 62
5569 23:07:03.489728 [CA 5] Center 34 (4~65) winsize 62
5570 23:07:03.490152
5571 23:07:03.493241 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5572 23:07:03.493665
5573 23:07:03.496605 [CATrainingPosCal] consider 1 rank data
5574 23:07:03.499764 u2DelayCellTimex100 = 270/100 ps
5575 23:07:03.503203 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5576 23:07:03.510269 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5577 23:07:03.513325 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5578 23:07:03.516445 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5579 23:07:03.520260 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5580 23:07:03.522883 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
5581 23:07:03.523440
5582 23:07:03.526461 CA PerBit enable=1, Macro0, CA PI delay=34
5583 23:07:03.526889
5584 23:07:03.529457 [CBTSetCACLKResult] CA Dly = 34
5585 23:07:03.529934 CS Dly: 6 (0~37)
5586 23:07:03.532969 ==
5587 23:07:03.536321 Dram Type= 6, Freq= 0, CH_1, rank 1
5588 23:07:03.539499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5589 23:07:03.539927 ==
5590 23:07:03.542783 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5591 23:07:03.549342 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5592 23:07:03.553183 [CA 0] Center 37 (7~68) winsize 62
5593 23:07:03.557011 [CA 1] Center 38 (7~69) winsize 63
5594 23:07:03.560026 [CA 2] Center 36 (6~66) winsize 61
5595 23:07:03.563269 [CA 3] Center 35 (5~65) winsize 61
5596 23:07:03.566662 [CA 4] Center 35 (5~65) winsize 61
5597 23:07:03.569641 [CA 5] Center 34 (4~65) winsize 62
5598 23:07:03.570216
5599 23:07:03.573213 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5600 23:07:03.573637
5601 23:07:03.576556 [CATrainingPosCal] consider 2 rank data
5602 23:07:03.579902 u2DelayCellTimex100 = 270/100 ps
5603 23:07:03.583102 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5604 23:07:03.589743 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5605 23:07:03.593162 CA2 delay=35 (6~65),Diff = 1 PI (6 cell)
5606 23:07:03.596404 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5607 23:07:03.599838 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5608 23:07:03.603534 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
5609 23:07:03.603931
5610 23:07:03.606233 CA PerBit enable=1, Macro0, CA PI delay=34
5611 23:07:03.606638
5612 23:07:03.609804 [CBTSetCACLKResult] CA Dly = 34
5613 23:07:03.610199 CS Dly: 7 (0~39)
5614 23:07:03.613334
5615 23:07:03.616248 ----->DramcWriteLeveling(PI) begin...
5616 23:07:03.616623 ==
5617 23:07:03.619770 Dram Type= 6, Freq= 0, CH_1, rank 0
5618 23:07:03.623136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5619 23:07:03.623525 ==
5620 23:07:03.626766 Write leveling (Byte 0): 26 => 26
5621 23:07:03.629605 Write leveling (Byte 1): 27 => 27
5622 23:07:03.633242 DramcWriteLeveling(PI) end<-----
5623 23:07:03.633614
5624 23:07:03.633966 ==
5625 23:07:03.636396 Dram Type= 6, Freq= 0, CH_1, rank 0
5626 23:07:03.639954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5627 23:07:03.640326 ==
5628 23:07:03.642872 [Gating] SW mode calibration
5629 23:07:03.649751 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5630 23:07:03.656333 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5631 23:07:03.659907 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5632 23:07:03.663023 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5633 23:07:03.666371 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5634 23:07:03.673285 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5635 23:07:03.676183 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5636 23:07:03.679622 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5637 23:07:03.686360 0 14 24 | B1->B0 | 3333 2f2f | 0 0 | (0 0) (0 1)
5638 23:07:03.689642 0 14 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5639 23:07:03.693001 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5640 23:07:03.699588 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5641 23:07:03.702773 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5642 23:07:03.706275 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5643 23:07:03.712548 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5644 23:07:03.716001 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5645 23:07:03.719277 0 15 24 | B1->B0 | 2828 2a2a | 0 0 | (1 1) (0 0)
5646 23:07:03.726173 0 15 28 | B1->B0 | 3939 4444 | 0 0 | (0 0) (0 0)
5647 23:07:03.730224 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5648 23:07:03.732641 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5649 23:07:03.739188 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5650 23:07:03.742510 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5651 23:07:03.745921 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5652 23:07:03.752702 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5653 23:07:03.755974 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5654 23:07:03.759134 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5655 23:07:03.765780 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5656 23:07:03.769283 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5657 23:07:03.772364 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5658 23:07:03.778803 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5659 23:07:03.781887 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5660 23:07:03.785397 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5661 23:07:03.792291 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5662 23:07:03.795372 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5663 23:07:03.798905 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5664 23:07:03.805414 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5665 23:07:03.808429 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5666 23:07:03.812349 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5667 23:07:03.818741 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5668 23:07:03.821898 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5669 23:07:03.825550 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5670 23:07:03.832298 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5671 23:07:03.835533 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5672 23:07:03.838420 Total UI for P1: 0, mck2ui 16
5673 23:07:03.841676 best dqsien dly found for B0: ( 1, 2, 26)
5674 23:07:03.845228 Total UI for P1: 0, mck2ui 16
5675 23:07:03.848676 best dqsien dly found for B1: ( 1, 2, 26)
5676 23:07:03.851932 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5677 23:07:03.855234 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5678 23:07:03.855361
5679 23:07:03.858569 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5680 23:07:03.862420 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5681 23:07:03.865005 [Gating] SW calibration Done
5682 23:07:03.865162 ==
5683 23:07:03.868515 Dram Type= 6, Freq= 0, CH_1, rank 0
5684 23:07:03.871736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5685 23:07:03.871821 ==
5686 23:07:03.875157 RX Vref Scan: 0
5687 23:07:03.875248
5688 23:07:03.875319 RX Vref 0 -> 0, step: 1
5689 23:07:03.878317
5690 23:07:03.878420 RX Delay -80 -> 252, step: 8
5691 23:07:03.885044 iDelay=208, Bit 0, Center 103 (16 ~ 191) 176
5692 23:07:03.888421 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5693 23:07:03.891685 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5694 23:07:03.895206 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5695 23:07:03.898495 iDelay=208, Bit 4, Center 103 (16 ~ 191) 176
5696 23:07:03.901642 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5697 23:07:03.908703 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5698 23:07:03.911971 iDelay=208, Bit 7, Center 103 (16 ~ 191) 176
5699 23:07:03.914939 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5700 23:07:03.918618 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5701 23:07:03.921920 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5702 23:07:03.925105 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5703 23:07:03.931933 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5704 23:07:03.935649 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5705 23:07:03.938732 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5706 23:07:03.941906 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5707 23:07:03.942185 ==
5708 23:07:03.945759 Dram Type= 6, Freq= 0, CH_1, rank 0
5709 23:07:03.948776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5710 23:07:03.952121 ==
5711 23:07:03.952644 DQS Delay:
5712 23:07:03.953186 DQS0 = 0, DQS1 = 0
5713 23:07:03.955765 DQM Delay:
5714 23:07:03.956232 DQM0 = 102, DQM1 = 95
5715 23:07:03.958815 DQ Delay:
5716 23:07:03.961862 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =99
5717 23:07:03.965316 DQ4 =103, DQ5 =111, DQ6 =111, DQ7 =103
5718 23:07:03.968772 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =91
5719 23:07:03.972116 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =99
5720 23:07:03.972678
5721 23:07:03.973171
5722 23:07:03.973648 ==
5723 23:07:03.975576 Dram Type= 6, Freq= 0, CH_1, rank 0
5724 23:07:03.978526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5725 23:07:03.979088 ==
5726 23:07:03.979638
5727 23:07:03.980069
5728 23:07:03.981885 TX Vref Scan disable
5729 23:07:03.982319 == TX Byte 0 ==
5730 23:07:03.988384 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5731 23:07:03.991630 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5732 23:07:03.992189 == TX Byte 1 ==
5733 23:07:03.998369 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5734 23:07:04.001854 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5735 23:07:04.002467 ==
5736 23:07:04.005339 Dram Type= 6, Freq= 0, CH_1, rank 0
5737 23:07:04.008583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5738 23:07:04.009148 ==
5739 23:07:04.009681
5740 23:07:04.011920
5741 23:07:04.012386 TX Vref Scan disable
5742 23:07:04.015454 == TX Byte 0 ==
5743 23:07:04.018732 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5744 23:07:04.021962 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5745 23:07:04.025373 == TX Byte 1 ==
5746 23:07:04.028406 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5747 23:07:04.031700 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5748 23:07:04.032129
5749 23:07:04.034994 [DATLAT]
5750 23:07:04.035428 Freq=933, CH1 RK0
5751 23:07:04.035773
5752 23:07:04.038344 DATLAT Default: 0xd
5753 23:07:04.038829 0, 0xFFFF, sum = 0
5754 23:07:04.042068 1, 0xFFFF, sum = 0
5755 23:07:04.042557 2, 0xFFFF, sum = 0
5756 23:07:04.045025 3, 0xFFFF, sum = 0
5757 23:07:04.045467 4, 0xFFFF, sum = 0
5758 23:07:04.048425 5, 0xFFFF, sum = 0
5759 23:07:04.048866 6, 0xFFFF, sum = 0
5760 23:07:04.051582 7, 0xFFFF, sum = 0
5761 23:07:04.055035 8, 0xFFFF, sum = 0
5762 23:07:04.055474 9, 0xFFFF, sum = 0
5763 23:07:04.058221 10, 0x0, sum = 1
5764 23:07:04.058706 11, 0x0, sum = 2
5765 23:07:04.059054 12, 0x0, sum = 3
5766 23:07:04.061327 13, 0x0, sum = 4
5767 23:07:04.061767 best_step = 11
5768 23:07:04.062112
5769 23:07:04.062473 ==
5770 23:07:04.064690 Dram Type= 6, Freq= 0, CH_1, rank 0
5771 23:07:04.071525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5772 23:07:04.071964 ==
5773 23:07:04.072308 RX Vref Scan: 1
5774 23:07:04.072630
5775 23:07:04.074933 RX Vref 0 -> 0, step: 1
5776 23:07:04.075386
5777 23:07:04.078036 RX Delay -53 -> 252, step: 4
5778 23:07:04.078502
5779 23:07:04.081674 Set Vref, RX VrefLevel [Byte0]: 54
5780 23:07:04.085019 [Byte1]: 54
5781 23:07:04.085482
5782 23:07:04.088138 Final RX Vref Byte 0 = 54 to rank0
5783 23:07:04.091342 Final RX Vref Byte 1 = 54 to rank0
5784 23:07:04.094952 Final RX Vref Byte 0 = 54 to rank1
5785 23:07:04.098058 Final RX Vref Byte 1 = 54 to rank1==
5786 23:07:04.101566 Dram Type= 6, Freq= 0, CH_1, rank 0
5787 23:07:04.104734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5788 23:07:04.105286 ==
5789 23:07:04.108047 DQS Delay:
5790 23:07:04.108584 DQS0 = 0, DQS1 = 0
5791 23:07:04.111324 DQM Delay:
5792 23:07:04.111829 DQM0 = 104, DQM1 = 97
5793 23:07:04.112171 DQ Delay:
5794 23:07:04.114614 DQ0 =108, DQ1 =98, DQ2 =96, DQ3 =102
5795 23:07:04.118107 DQ4 =104, DQ5 =112, DQ6 =112, DQ7 =102
5796 23:07:04.121319 DQ8 =86, DQ9 =84, DQ10 =100, DQ11 =92
5797 23:07:04.128228 DQ12 =108, DQ13 =102, DQ14 =104, DQ15 =104
5798 23:07:04.128713
5799 23:07:04.129092
5800 23:07:04.135022 [DQSOSCAuto] RK0, (LSB)MR18= 0x1c34, (MSB)MR19= 0x505, tDQSOscB0 = 405 ps tDQSOscB1 = 412 ps
5801 23:07:04.138047 CH1 RK0: MR19=505, MR18=1C34
5802 23:07:04.144735 CH1_RK0: MR19=0x505, MR18=0x1C34, DQSOSC=405, MR23=63, INC=66, DEC=44
5803 23:07:04.145213
5804 23:07:04.147892 ----->DramcWriteLeveling(PI) begin...
5805 23:07:04.148324 ==
5806 23:07:04.151505 Dram Type= 6, Freq= 0, CH_1, rank 1
5807 23:07:04.154550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5808 23:07:04.155061 ==
5809 23:07:04.158000 Write leveling (Byte 0): 27 => 27
5810 23:07:04.161028 Write leveling (Byte 1): 28 => 28
5811 23:07:04.164706 DramcWriteLeveling(PI) end<-----
5812 23:07:04.165178
5813 23:07:04.165520 ==
5814 23:07:04.168370 Dram Type= 6, Freq= 0, CH_1, rank 1
5815 23:07:04.171303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5816 23:07:04.171786 ==
5817 23:07:04.174408 [Gating] SW mode calibration
5818 23:07:04.181464 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5819 23:07:04.187780 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5820 23:07:04.191360 0 14 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5821 23:07:04.197766 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5822 23:07:04.201342 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5823 23:07:04.204393 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5824 23:07:04.211271 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5825 23:07:04.214554 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5826 23:07:04.218442 0 14 24 | B1->B0 | 2e2e 3333 | 1 0 | (1 1) (0 0)
5827 23:07:04.221434 0 14 28 | B1->B0 | 2323 2727 | 0 0 | (0 0) (1 1)
5828 23:07:04.227813 0 15 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5829 23:07:04.231010 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5830 23:07:04.234434 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5831 23:07:04.241038 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5832 23:07:04.244576 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5833 23:07:04.247984 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5834 23:07:04.254317 0 15 24 | B1->B0 | 2e2e 2828 | 0 0 | (0 0) (0 0)
5835 23:07:04.257852 0 15 28 | B1->B0 | 4242 4040 | 1 0 | (0 0) (0 0)
5836 23:07:04.261329 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5837 23:07:04.268536 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5838 23:07:04.271411 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5839 23:07:04.274442 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5840 23:07:04.280999 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5841 23:07:04.284282 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5842 23:07:04.287710 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5843 23:07:04.294189 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5844 23:07:04.297997 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5845 23:07:04.301011 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5846 23:07:04.307994 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5847 23:07:04.310792 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5848 23:07:04.314460 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5849 23:07:04.320807 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5850 23:07:04.324476 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5851 23:07:04.327702 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5852 23:07:04.330842 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5853 23:07:04.337578 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5854 23:07:04.341189 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5855 23:07:04.344193 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5856 23:07:04.350615 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5857 23:07:04.354417 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5858 23:07:04.357314 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5859 23:07:04.364155 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5860 23:07:04.367400 Total UI for P1: 0, mck2ui 16
5861 23:07:04.370743 best dqsien dly found for B1: ( 1, 2, 24)
5862 23:07:04.374176 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5863 23:07:04.377601 Total UI for P1: 0, mck2ui 16
5864 23:07:04.380518 best dqsien dly found for B0: ( 1, 2, 28)
5865 23:07:04.384116 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5866 23:07:04.387441 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5867 23:07:04.387874
5868 23:07:04.390613 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5869 23:07:04.393831 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5870 23:07:04.397130 [Gating] SW calibration Done
5871 23:07:04.397567 ==
5872 23:07:04.400616 Dram Type= 6, Freq= 0, CH_1, rank 1
5873 23:07:04.407532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5874 23:07:04.407971 ==
5875 23:07:04.408316 RX Vref Scan: 0
5876 23:07:04.408638
5877 23:07:04.410513 RX Vref 0 -> 0, step: 1
5878 23:07:04.410949
5879 23:07:04.413599 RX Delay -80 -> 252, step: 8
5880 23:07:04.417080 iDelay=200, Bit 0, Center 107 (24 ~ 191) 168
5881 23:07:04.420460 iDelay=200, Bit 1, Center 95 (8 ~ 183) 176
5882 23:07:04.423866 iDelay=200, Bit 2, Center 91 (8 ~ 175) 168
5883 23:07:04.426979 iDelay=200, Bit 3, Center 99 (8 ~ 191) 184
5884 23:07:04.430497 iDelay=200, Bit 4, Center 99 (8 ~ 191) 184
5885 23:07:04.437238 iDelay=200, Bit 5, Center 111 (24 ~ 199) 176
5886 23:07:04.440593 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5887 23:07:04.443745 iDelay=200, Bit 7, Center 99 (8 ~ 191) 184
5888 23:07:04.447350 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5889 23:07:04.450749 iDelay=200, Bit 9, Center 83 (-8 ~ 175) 184
5890 23:07:04.454076 iDelay=200, Bit 10, Center 99 (8 ~ 191) 184
5891 23:07:04.460367 iDelay=200, Bit 11, Center 91 (0 ~ 183) 184
5892 23:07:04.463748 iDelay=200, Bit 12, Center 103 (8 ~ 199) 192
5893 23:07:04.467121 iDelay=200, Bit 13, Center 103 (8 ~ 199) 192
5894 23:07:04.470707 iDelay=200, Bit 14, Center 103 (8 ~ 199) 192
5895 23:07:04.473664 iDelay=200, Bit 15, Center 103 (8 ~ 199) 192
5896 23:07:04.477051 ==
5897 23:07:04.477491 Dram Type= 6, Freq= 0, CH_1, rank 1
5898 23:07:04.483449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5899 23:07:04.483889 ==
5900 23:07:04.484326 DQS Delay:
5901 23:07:04.487011 DQS0 = 0, DQS1 = 0
5902 23:07:04.487446 DQM Delay:
5903 23:07:04.490178 DQM0 = 101, DQM1 = 96
5904 23:07:04.490656 DQ Delay:
5905 23:07:04.493497 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5906 23:07:04.496955 DQ4 =99, DQ5 =111, DQ6 =107, DQ7 =99
5907 23:07:04.500581 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =91
5908 23:07:04.504013 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5909 23:07:04.504483
5910 23:07:04.504852
5911 23:07:04.505193 ==
5912 23:07:04.507564 Dram Type= 6, Freq= 0, CH_1, rank 1
5913 23:07:04.510566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5914 23:07:04.511140 ==
5915 23:07:04.511514
5916 23:07:04.511855
5917 23:07:04.513496 TX Vref Scan disable
5918 23:07:04.516981 == TX Byte 0 ==
5919 23:07:04.520203 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5920 23:07:04.523553 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5921 23:07:04.526869 == TX Byte 1 ==
5922 23:07:04.530297 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5923 23:07:04.533707 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5924 23:07:04.534325 ==
5925 23:07:04.536696 Dram Type= 6, Freq= 0, CH_1, rank 1
5926 23:07:04.543456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5927 23:07:04.543931 ==
5928 23:07:04.544304
5929 23:07:04.544644
5930 23:07:04.544973 TX Vref Scan disable
5931 23:07:04.547352 == TX Byte 0 ==
5932 23:07:04.550926 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5933 23:07:04.556877 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5934 23:07:04.556962 == TX Byte 1 ==
5935 23:07:04.560445 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5936 23:07:04.566896 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5937 23:07:04.566979
5938 23:07:04.567045 [DATLAT]
5939 23:07:04.567104 Freq=933, CH1 RK1
5940 23:07:04.567163
5941 23:07:04.570708 DATLAT Default: 0xb
5942 23:07:04.570791 0, 0xFFFF, sum = 0
5943 23:07:04.573729 1, 0xFFFF, sum = 0
5944 23:07:04.573819 2, 0xFFFF, sum = 0
5945 23:07:04.576851 3, 0xFFFF, sum = 0
5946 23:07:04.580268 4, 0xFFFF, sum = 0
5947 23:07:04.580366 5, 0xFFFF, sum = 0
5948 23:07:04.584012 6, 0xFFFF, sum = 0
5949 23:07:04.584096 7, 0xFFFF, sum = 0
5950 23:07:04.587018 8, 0xFFFF, sum = 0
5951 23:07:04.587103 9, 0xFFFF, sum = 0
5952 23:07:04.590245 10, 0x0, sum = 1
5953 23:07:04.590329 11, 0x0, sum = 2
5954 23:07:04.590401 12, 0x0, sum = 3
5955 23:07:04.593670 13, 0x0, sum = 4
5956 23:07:04.593760 best_step = 11
5957 23:07:04.593831
5958 23:07:04.596984 ==
5959 23:07:04.597073 Dram Type= 6, Freq= 0, CH_1, rank 1
5960 23:07:04.603994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5961 23:07:04.604078 ==
5962 23:07:04.604144 RX Vref Scan: 0
5963 23:07:04.604205
5964 23:07:04.607486 RX Vref 0 -> 0, step: 1
5965 23:07:04.607569
5966 23:07:04.610372 RX Delay -53 -> 252, step: 4
5967 23:07:04.613576 iDelay=199, Bit 0, Center 110 (35 ~ 186) 152
5968 23:07:04.620820 iDelay=199, Bit 1, Center 98 (19 ~ 178) 160
5969 23:07:04.623617 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5970 23:07:04.627029 iDelay=199, Bit 3, Center 104 (23 ~ 186) 164
5971 23:07:04.630093 iDelay=199, Bit 4, Center 106 (23 ~ 190) 168
5972 23:07:04.633559 iDelay=199, Bit 5, Center 116 (35 ~ 198) 164
5973 23:07:04.637048 iDelay=199, Bit 6, Center 110 (27 ~ 194) 168
5974 23:07:04.643487 iDelay=199, Bit 7, Center 102 (23 ~ 182) 160
5975 23:07:04.647005 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5976 23:07:04.650148 iDelay=199, Bit 9, Center 90 (7 ~ 174) 168
5977 23:07:04.653449 iDelay=199, Bit 10, Center 98 (15 ~ 182) 168
5978 23:07:04.657044 iDelay=199, Bit 11, Center 92 (7 ~ 178) 172
5979 23:07:04.663573 iDelay=199, Bit 12, Center 106 (19 ~ 194) 176
5980 23:07:04.666758 iDelay=199, Bit 13, Center 104 (19 ~ 190) 172
5981 23:07:04.670119 iDelay=199, Bit 14, Center 104 (19 ~ 190) 172
5982 23:07:04.673707 iDelay=199, Bit 15, Center 106 (19 ~ 194) 176
5983 23:07:04.673791 ==
5984 23:07:04.676740 Dram Type= 6, Freq= 0, CH_1, rank 1
5985 23:07:04.683407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5986 23:07:04.683504 ==
5987 23:07:04.683579 DQS Delay:
5988 23:07:04.686658 DQS0 = 0, DQS1 = 0
5989 23:07:04.686752 DQM Delay:
5990 23:07:04.686827 DQM0 = 105, DQM1 = 98
5991 23:07:04.690052 DQ Delay:
5992 23:07:04.693376 DQ0 =110, DQ1 =98, DQ2 =94, DQ3 =104
5993 23:07:04.696930 DQ4 =106, DQ5 =116, DQ6 =110, DQ7 =102
5994 23:07:04.700243 DQ8 =84, DQ9 =90, DQ10 =98, DQ11 =92
5995 23:07:04.703268 DQ12 =106, DQ13 =104, DQ14 =104, DQ15 =106
5996 23:07:04.703401
5997 23:07:04.703508
5998 23:07:04.709934 [DQSOSCAuto] RK1, (LSB)MR18= 0x2703, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 409 ps
5999 23:07:04.713682 CH1 RK1: MR19=505, MR18=2703
6000 23:07:04.720138 CH1_RK1: MR19=0x505, MR18=0x2703, DQSOSC=409, MR23=63, INC=64, DEC=43
6001 23:07:04.723317 [RxdqsGatingPostProcess] freq 933
6002 23:07:04.730142 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6003 23:07:04.733728 best DQS0 dly(2T, 0.5T) = (0, 10)
6004 23:07:04.734129 best DQS1 dly(2T, 0.5T) = (0, 10)
6005 23:07:04.736735 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6006 23:07:04.740342 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6007 23:07:04.743553 best DQS0 dly(2T, 0.5T) = (0, 10)
6008 23:07:04.746988 best DQS1 dly(2T, 0.5T) = (0, 10)
6009 23:07:04.749971 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6010 23:07:04.753523 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6011 23:07:04.756977 Pre-setting of DQS Precalculation
6012 23:07:04.763742 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6013 23:07:04.770304 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6014 23:07:04.776703 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6015 23:07:04.777142
6016 23:07:04.777486
6017 23:07:04.780373 [Calibration Summary] 1866 Mbps
6018 23:07:04.780810 CH 0, Rank 0
6019 23:07:04.783581 SW Impedance : PASS
6020 23:07:04.784016 DUTY Scan : NO K
6021 23:07:04.786766 ZQ Calibration : PASS
6022 23:07:04.790102 Jitter Meter : NO K
6023 23:07:04.790612 CBT Training : PASS
6024 23:07:04.793448 Write leveling : PASS
6025 23:07:04.796982 RX DQS gating : PASS
6026 23:07:04.797418 RX DQ/DQS(RDDQC) : PASS
6027 23:07:04.800483 TX DQ/DQS : PASS
6028 23:07:04.803702 RX DATLAT : PASS
6029 23:07:04.804245 RX DQ/DQS(Engine): PASS
6030 23:07:04.806941 TX OE : NO K
6031 23:07:04.807421 All Pass.
6032 23:07:04.807799
6033 23:07:04.810282 CH 0, Rank 1
6034 23:07:04.810839 SW Impedance : PASS
6035 23:07:04.813344 DUTY Scan : NO K
6036 23:07:04.817104 ZQ Calibration : PASS
6037 23:07:04.817581 Jitter Meter : NO K
6038 23:07:04.820168 CBT Training : PASS
6039 23:07:04.823669 Write leveling : PASS
6040 23:07:04.824245 RX DQS gating : PASS
6041 23:07:04.826907 RX DQ/DQS(RDDQC) : PASS
6042 23:07:04.827382 TX DQ/DQS : PASS
6043 23:07:04.830122 RX DATLAT : PASS
6044 23:07:04.834001 RX DQ/DQS(Engine): PASS
6045 23:07:04.834636 TX OE : NO K
6046 23:07:04.836987 All Pass.
6047 23:07:04.837748
6048 23:07:04.838145 CH 1, Rank 0
6049 23:07:04.840327 SW Impedance : PASS
6050 23:07:04.840806 DUTY Scan : NO K
6051 23:07:04.843973 ZQ Calibration : PASS
6052 23:07:04.847095 Jitter Meter : NO K
6053 23:07:04.847677 CBT Training : PASS
6054 23:07:04.850087 Write leveling : PASS
6055 23:07:04.853637 RX DQS gating : PASS
6056 23:07:04.854144 RX DQ/DQS(RDDQC) : PASS
6057 23:07:04.856789 TX DQ/DQS : PASS
6058 23:07:04.859992 RX DATLAT : PASS
6059 23:07:04.860490 RX DQ/DQS(Engine): PASS
6060 23:07:04.863857 TX OE : NO K
6061 23:07:04.864331 All Pass.
6062 23:07:04.864700
6063 23:07:04.866563 CH 1, Rank 1
6064 23:07:04.867035 SW Impedance : PASS
6065 23:07:04.870161 DUTY Scan : NO K
6066 23:07:04.873348 ZQ Calibration : PASS
6067 23:07:04.873819 Jitter Meter : NO K
6068 23:07:04.876856 CBT Training : PASS
6069 23:07:04.877404 Write leveling : PASS
6070 23:07:04.879944 RX DQS gating : PASS
6071 23:07:04.883036 RX DQ/DQS(RDDQC) : PASS
6072 23:07:04.883125 TX DQ/DQS : PASS
6073 23:07:04.886171 RX DATLAT : PASS
6074 23:07:04.889673 RX DQ/DQS(Engine): PASS
6075 23:07:04.889756 TX OE : NO K
6076 23:07:04.893075 All Pass.
6077 23:07:04.893158
6078 23:07:04.893224 DramC Write-DBI off
6079 23:07:04.896270 PER_BANK_REFRESH: Hybrid Mode
6080 23:07:04.899462 TX_TRACKING: ON
6081 23:07:04.906521 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6082 23:07:04.909779 [FAST_K] Save calibration result to emmc
6083 23:07:04.913040 dramc_set_vcore_voltage set vcore to 650000
6084 23:07:04.916236 Read voltage for 400, 6
6085 23:07:04.916397 Vio18 = 0
6086 23:07:04.919640 Vcore = 650000
6087 23:07:04.919788 Vdram = 0
6088 23:07:04.919879 Vddq = 0
6089 23:07:04.922945 Vmddr = 0
6090 23:07:04.926468 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6091 23:07:04.932489 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6092 23:07:04.932710 MEM_TYPE=3, freq_sel=20
6093 23:07:04.935900 sv_algorithm_assistance_LP4_800
6094 23:07:04.942613 ============ PULL DRAM RESETB DOWN ============
6095 23:07:04.945851 ========== PULL DRAM RESETB DOWN end =========
6096 23:07:04.949244 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6097 23:07:04.952704 ===================================
6098 23:07:04.955626 LPDDR4 DRAM CONFIGURATION
6099 23:07:04.958910 ===================================
6100 23:07:04.962314 EX_ROW_EN[0] = 0x0
6101 23:07:04.962404 EX_ROW_EN[1] = 0x0
6102 23:07:04.966490 LP4Y_EN = 0x0
6103 23:07:04.966574 WORK_FSP = 0x0
6104 23:07:04.968908 WL = 0x2
6105 23:07:04.968991 RL = 0x2
6106 23:07:04.972344 BL = 0x2
6107 23:07:04.972427 RPST = 0x0
6108 23:07:04.975704 RD_PRE = 0x0
6109 23:07:04.975789 WR_PRE = 0x1
6110 23:07:04.978936 WR_PST = 0x0
6111 23:07:04.979019 DBI_WR = 0x0
6112 23:07:04.982325 DBI_RD = 0x0
6113 23:07:04.982458 OTF = 0x1
6114 23:07:04.985843 ===================================
6115 23:07:04.989027 ===================================
6116 23:07:04.992075 ANA top config
6117 23:07:04.995502 ===================================
6118 23:07:04.998754 DLL_ASYNC_EN = 0
6119 23:07:04.998858 ALL_SLAVE_EN = 1
6120 23:07:05.002677 NEW_RANK_MODE = 1
6121 23:07:05.005806 DLL_IDLE_MODE = 1
6122 23:07:05.008999 LP45_APHY_COMB_EN = 1
6123 23:07:05.009206 TX_ODT_DIS = 1
6124 23:07:05.012340 NEW_8X_MODE = 1
6125 23:07:05.015352 ===================================
6126 23:07:05.018595 ===================================
6127 23:07:05.022056 data_rate = 800
6128 23:07:05.025072 CKR = 1
6129 23:07:05.028706 DQ_P2S_RATIO = 4
6130 23:07:05.031898 ===================================
6131 23:07:05.035306 CA_P2S_RATIO = 4
6132 23:07:05.035390 DQ_CA_OPEN = 0
6133 23:07:05.038524 DQ_SEMI_OPEN = 1
6134 23:07:05.041781 CA_SEMI_OPEN = 1
6135 23:07:05.045454 CA_FULL_RATE = 0
6136 23:07:05.048291 DQ_CKDIV4_EN = 0
6137 23:07:05.051896 CA_CKDIV4_EN = 1
6138 23:07:05.051980 CA_PREDIV_EN = 0
6139 23:07:05.055057 PH8_DLY = 0
6140 23:07:05.058657 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6141 23:07:05.062271 DQ_AAMCK_DIV = 0
6142 23:07:05.065449 CA_AAMCK_DIV = 0
6143 23:07:05.068685 CA_ADMCK_DIV = 4
6144 23:07:05.068865 DQ_TRACK_CA_EN = 0
6145 23:07:05.071772 CA_PICK = 800
6146 23:07:05.074827 CA_MCKIO = 400
6147 23:07:05.078420 MCKIO_SEMI = 400
6148 23:07:05.082564 PLL_FREQ = 3016
6149 23:07:05.085106 DQ_UI_PI_RATIO = 32
6150 23:07:05.088439 CA_UI_PI_RATIO = 32
6151 23:07:05.091345 ===================================
6152 23:07:05.094919 ===================================
6153 23:07:05.095003 memory_type:LPDDR4
6154 23:07:05.098082 GP_NUM : 10
6155 23:07:05.101184 SRAM_EN : 1
6156 23:07:05.101269 MD32_EN : 0
6157 23:07:05.104729 ===================================
6158 23:07:05.107789 [ANA_INIT] >>>>>>>>>>>>>>
6159 23:07:05.111308 <<<<<< [CONFIGURE PHASE]: ANA_TX
6160 23:07:05.115087 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6161 23:07:05.118014 ===================================
6162 23:07:05.121404 data_rate = 800,PCW = 0X7400
6163 23:07:05.124874 ===================================
6164 23:07:05.127906 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6165 23:07:05.131134 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6166 23:07:05.144819 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6167 23:07:05.147922 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6168 23:07:05.151325 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6169 23:07:05.154521 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6170 23:07:05.157959 [ANA_INIT] flow start
6171 23:07:05.161727 [ANA_INIT] PLL >>>>>>>>
6172 23:07:05.162304 [ANA_INIT] PLL <<<<<<<<
6173 23:07:05.164773 [ANA_INIT] MIDPI >>>>>>>>
6174 23:07:05.168452 [ANA_INIT] MIDPI <<<<<<<<
6175 23:07:05.168924 [ANA_INIT] DLL >>>>>>>>
6176 23:07:05.171810 [ANA_INIT] flow end
6177 23:07:05.174840 ============ LP4 DIFF to SE enter ============
6178 23:07:05.177911 ============ LP4 DIFF to SE exit ============
6179 23:07:05.181335 [ANA_INIT] <<<<<<<<<<<<<
6180 23:07:05.184871 [Flow] Enable top DCM control >>>>>
6181 23:07:05.187947 [Flow] Enable top DCM control <<<<<
6182 23:07:05.191318 Enable DLL master slave shuffle
6183 23:07:05.197883 ==============================================================
6184 23:07:05.197970 Gating Mode config
6185 23:07:05.204457 ==============================================================
6186 23:07:05.204542 Config description:
6187 23:07:05.214244 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6188 23:07:05.221296 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6189 23:07:05.227760 SELPH_MODE 0: By rank 1: By Phase
6190 23:07:05.231494 ==============================================================
6191 23:07:05.234853 GAT_TRACK_EN = 0
6192 23:07:05.238282 RX_GATING_MODE = 2
6193 23:07:05.241139 RX_GATING_TRACK_MODE = 2
6194 23:07:05.244536 SELPH_MODE = 1
6195 23:07:05.247843 PICG_EARLY_EN = 1
6196 23:07:05.250701 VALID_LAT_VALUE = 1
6197 23:07:05.257227 ==============================================================
6198 23:07:05.260944 Enter into Gating configuration >>>>
6199 23:07:05.263918 Exit from Gating configuration <<<<
6200 23:07:05.267441 Enter into DVFS_PRE_config >>>>>
6201 23:07:05.277309 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6202 23:07:05.280967 Exit from DVFS_PRE_config <<<<<
6203 23:07:05.284137 Enter into PICG configuration >>>>
6204 23:07:05.287410 Exit from PICG configuration <<<<
6205 23:07:05.290351 [RX_INPUT] configuration >>>>>
6206 23:07:05.290477 [RX_INPUT] configuration <<<<<
6207 23:07:05.297435 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6208 23:07:05.304184 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6209 23:07:05.307546 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6210 23:07:05.313904 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6211 23:07:05.320753 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6212 23:07:05.327913 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6213 23:07:05.330529 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6214 23:07:05.333689 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6215 23:07:05.340359 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6216 23:07:05.343438 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6217 23:07:05.347112 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6218 23:07:05.353937 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6219 23:07:05.357010 ===================================
6220 23:07:05.357114 LPDDR4 DRAM CONFIGURATION
6221 23:07:05.360230 ===================================
6222 23:07:05.363321 EX_ROW_EN[0] = 0x0
6223 23:07:05.363395 EX_ROW_EN[1] = 0x0
6224 23:07:05.367004 LP4Y_EN = 0x0
6225 23:07:05.367077 WORK_FSP = 0x0
6226 23:07:05.370021 WL = 0x2
6227 23:07:05.373503 RL = 0x2
6228 23:07:05.373574 BL = 0x2
6229 23:07:05.376890 RPST = 0x0
6230 23:07:05.376973 RD_PRE = 0x0
6231 23:07:05.380281 WR_PRE = 0x1
6232 23:07:05.380370 WR_PST = 0x0
6233 23:07:05.383753 DBI_WR = 0x0
6234 23:07:05.383848 DBI_RD = 0x0
6235 23:07:05.386975 OTF = 0x1
6236 23:07:05.390582 ===================================
6237 23:07:05.393501 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6238 23:07:05.397206 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6239 23:07:05.400259 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6240 23:07:05.403776 ===================================
6241 23:07:05.406895 LPDDR4 DRAM CONFIGURATION
6242 23:07:05.410223 ===================================
6243 23:07:05.413848 EX_ROW_EN[0] = 0x10
6244 23:07:05.414070 EX_ROW_EN[1] = 0x0
6245 23:07:05.416812 LP4Y_EN = 0x0
6246 23:07:05.417044 WORK_FSP = 0x0
6247 23:07:05.419960 WL = 0x2
6248 23:07:05.420241 RL = 0x2
6249 23:07:05.423554 BL = 0x2
6250 23:07:05.423840 RPST = 0x0
6251 23:07:05.426580 RD_PRE = 0x0
6252 23:07:05.426876 WR_PRE = 0x1
6253 23:07:05.429953 WR_PST = 0x0
6254 23:07:05.433834 DBI_WR = 0x0
6255 23:07:05.434282 DBI_RD = 0x0
6256 23:07:05.436939 OTF = 0x1
6257 23:07:05.440145 ===================================
6258 23:07:05.443323 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6259 23:07:05.448570 nWR fixed to 30
6260 23:07:05.451718 [ModeRegInit_LP4] CH0 RK0
6261 23:07:05.451801 [ModeRegInit_LP4] CH0 RK1
6262 23:07:05.454819 [ModeRegInit_LP4] CH1 RK0
6263 23:07:05.458433 [ModeRegInit_LP4] CH1 RK1
6264 23:07:05.458523 match AC timing 19
6265 23:07:05.465494 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6266 23:07:05.468637 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6267 23:07:05.472022 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6268 23:07:05.478336 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6269 23:07:05.481640 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6270 23:07:05.481752 ==
6271 23:07:05.484925 Dram Type= 6, Freq= 0, CH_0, rank 0
6272 23:07:05.488580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6273 23:07:05.488655 ==
6274 23:07:05.495206 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6275 23:07:05.501811 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6276 23:07:05.505376 [CA 0] Center 36 (8~64) winsize 57
6277 23:07:05.508101 [CA 1] Center 36 (8~64) winsize 57
6278 23:07:05.511852 [CA 2] Center 36 (8~64) winsize 57
6279 23:07:05.511957 [CA 3] Center 36 (8~64) winsize 57
6280 23:07:05.514769 [CA 4] Center 36 (8~64) winsize 57
6281 23:07:05.517974 [CA 5] Center 36 (8~64) winsize 57
6282 23:07:05.518074
6283 23:07:05.524654 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6284 23:07:05.524734
6285 23:07:05.527944 [CATrainingPosCal] consider 1 rank data
6286 23:07:05.531341 u2DelayCellTimex100 = 270/100 ps
6287 23:07:05.534968 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6288 23:07:05.538089 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6289 23:07:05.541768 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6290 23:07:05.544951 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6291 23:07:05.548388 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6292 23:07:05.551536 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6293 23:07:05.551715
6294 23:07:05.554681 CA PerBit enable=1, Macro0, CA PI delay=36
6295 23:07:05.554781
6296 23:07:05.557782 [CBTSetCACLKResult] CA Dly = 36
6297 23:07:05.561276 CS Dly: 1 (0~32)
6298 23:07:05.561376 ==
6299 23:07:05.564264 Dram Type= 6, Freq= 0, CH_0, rank 1
6300 23:07:05.568097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6301 23:07:05.568199 ==
6302 23:07:05.574519 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6303 23:07:05.577798 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6304 23:07:05.581082 [CA 0] Center 36 (8~64) winsize 57
6305 23:07:05.584403 [CA 1] Center 36 (8~64) winsize 57
6306 23:07:05.587609 [CA 2] Center 36 (8~64) winsize 57
6307 23:07:05.591184 [CA 3] Center 36 (8~64) winsize 57
6308 23:07:05.595058 [CA 4] Center 36 (8~64) winsize 57
6309 23:07:05.597875 [CA 5] Center 36 (8~64) winsize 57
6310 23:07:05.597948
6311 23:07:05.601464 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6312 23:07:05.601548
6313 23:07:05.604570 [CATrainingPosCal] consider 2 rank data
6314 23:07:05.608358 u2DelayCellTimex100 = 270/100 ps
6315 23:07:05.611288 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6316 23:07:05.614670 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6317 23:07:05.618068 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6318 23:07:05.624771 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6319 23:07:05.627995 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6320 23:07:05.630853 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6321 23:07:05.630938
6322 23:07:05.634366 CA PerBit enable=1, Macro0, CA PI delay=36
6323 23:07:05.634488
6324 23:07:05.637474 [CBTSetCACLKResult] CA Dly = 36
6325 23:07:05.637558 CS Dly: 1 (0~32)
6326 23:07:05.637624
6327 23:07:05.640827 ----->DramcWriteLeveling(PI) begin...
6328 23:07:05.644203 ==
6329 23:07:05.644288 Dram Type= 6, Freq= 0, CH_0, rank 0
6330 23:07:05.651085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6331 23:07:05.651176 ==
6332 23:07:05.654558 Write leveling (Byte 0): 40 => 8
6333 23:07:05.657750 Write leveling (Byte 1): 32 => 0
6334 23:07:05.657852 DramcWriteLeveling(PI) end<-----
6335 23:07:05.661148
6336 23:07:05.661263 ==
6337 23:07:05.663973 Dram Type= 6, Freq= 0, CH_0, rank 0
6338 23:07:05.667563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6339 23:07:05.667669 ==
6340 23:07:05.670895 [Gating] SW mode calibration
6341 23:07:05.677975 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6342 23:07:05.681630 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6343 23:07:05.688158 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6344 23:07:05.691631 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6345 23:07:05.694636 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6346 23:07:05.701156 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6347 23:07:05.704500 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6348 23:07:05.707757 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6349 23:07:05.714028 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6350 23:07:05.717336 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6351 23:07:05.720847 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6352 23:07:05.724110 Total UI for P1: 0, mck2ui 16
6353 23:07:05.727465 best dqsien dly found for B0: ( 0, 14, 24)
6354 23:07:05.730595 Total UI for P1: 0, mck2ui 16
6355 23:07:05.733988 best dqsien dly found for B1: ( 0, 14, 24)
6356 23:07:05.737116 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6357 23:07:05.740304 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6358 23:07:05.740391
6359 23:07:05.747171 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6360 23:07:05.750429 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6361 23:07:05.754478 [Gating] SW calibration Done
6362 23:07:05.754942 ==
6363 23:07:05.757465 Dram Type= 6, Freq= 0, CH_0, rank 0
6364 23:07:05.761183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6365 23:07:05.761750 ==
6366 23:07:05.762118 RX Vref Scan: 0
6367 23:07:05.762491
6368 23:07:05.763966 RX Vref 0 -> 0, step: 1
6369 23:07:05.764423
6370 23:07:05.768259 RX Delay -410 -> 252, step: 16
6371 23:07:05.771086 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6372 23:07:05.777592 iDelay=230, Bit 1, Center -3 (-234 ~ 229) 464
6373 23:07:05.780801 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6374 23:07:05.784014 iDelay=230, Bit 3, Center -11 (-234 ~ 213) 448
6375 23:07:05.787292 iDelay=230, Bit 4, Center -3 (-234 ~ 229) 464
6376 23:07:05.790772 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6377 23:07:05.797370 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6378 23:07:05.800622 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6379 23:07:05.803995 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6380 23:07:05.807496 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6381 23:07:05.813813 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6382 23:07:05.817306 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6383 23:07:05.820399 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6384 23:07:05.824194 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6385 23:07:05.830770 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6386 23:07:05.833985 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6387 23:07:05.834473 ==
6388 23:07:05.837712 Dram Type= 6, Freq= 0, CH_0, rank 0
6389 23:07:05.840704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6390 23:07:05.841168 ==
6391 23:07:05.844541 DQS Delay:
6392 23:07:05.845000 DQS0 = 27, DQS1 = 43
6393 23:07:05.847368 DQM Delay:
6394 23:07:05.847822 DQM0 = 16, DQM1 = 13
6395 23:07:05.848183 DQ Delay:
6396 23:07:05.850690 DQ0 =8, DQ1 =24, DQ2 =8, DQ3 =16
6397 23:07:05.853946 DQ4 =24, DQ5 =0, DQ6 =24, DQ7 =24
6398 23:07:05.857267 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6399 23:07:05.860652 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6400 23:07:05.861122
6401 23:07:05.861490
6402 23:07:05.861826 ==
6403 23:07:05.863826 Dram Type= 6, Freq= 0, CH_0, rank 0
6404 23:07:05.870700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6405 23:07:05.871173 ==
6406 23:07:05.871540
6407 23:07:05.871878
6408 23:07:05.872206 TX Vref Scan disable
6409 23:07:05.874005 == TX Byte 0 ==
6410 23:07:05.877331 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6411 23:07:05.880849 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6412 23:07:05.884332 == TX Byte 1 ==
6413 23:07:05.887463 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6414 23:07:05.890261 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6415 23:07:05.890349 ==
6416 23:07:05.894029 Dram Type= 6, Freq= 0, CH_0, rank 0
6417 23:07:05.900133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6418 23:07:05.900224 ==
6419 23:07:05.900291
6420 23:07:05.900354
6421 23:07:05.900412 TX Vref Scan disable
6422 23:07:05.903921 == TX Byte 0 ==
6423 23:07:05.907256 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6424 23:07:05.910598 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6425 23:07:05.913947 == TX Byte 1 ==
6426 23:07:05.916700 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6427 23:07:05.920109 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6428 23:07:05.923603
6429 23:07:05.923797 [DATLAT]
6430 23:07:05.923897 Freq=400, CH0 RK0
6431 23:07:05.923988
6432 23:07:05.927185 DATLAT Default: 0xf
6433 23:07:05.927407 0, 0xFFFF, sum = 0
6434 23:07:05.930554 1, 0xFFFF, sum = 0
6435 23:07:05.930767 2, 0xFFFF, sum = 0
6436 23:07:05.933217 3, 0xFFFF, sum = 0
6437 23:07:05.936751 4, 0xFFFF, sum = 0
6438 23:07:05.936838 5, 0xFFFF, sum = 0
6439 23:07:05.939714 6, 0xFFFF, sum = 0
6440 23:07:05.939800 7, 0xFFFF, sum = 0
6441 23:07:05.943463 8, 0xFFFF, sum = 0
6442 23:07:05.943550 9, 0xFFFF, sum = 0
6443 23:07:05.946480 10, 0xFFFF, sum = 0
6444 23:07:05.946566 11, 0xFFFF, sum = 0
6445 23:07:05.950268 12, 0xFFFF, sum = 0
6446 23:07:05.950355 13, 0x0, sum = 1
6447 23:07:05.953262 14, 0x0, sum = 2
6448 23:07:05.953348 15, 0x0, sum = 3
6449 23:07:05.956494 16, 0x0, sum = 4
6450 23:07:05.956581 best_step = 14
6451 23:07:05.956648
6452 23:07:05.956710 ==
6453 23:07:05.959937 Dram Type= 6, Freq= 0, CH_0, rank 0
6454 23:07:05.963245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6455 23:07:05.963331 ==
6456 23:07:05.966637 RX Vref Scan: 1
6457 23:07:05.966722
6458 23:07:05.970097 RX Vref 0 -> 0, step: 1
6459 23:07:05.970182
6460 23:07:05.970249 RX Delay -327 -> 252, step: 8
6461 23:07:05.973002
6462 23:07:05.973086 Set Vref, RX VrefLevel [Byte0]: 57
6463 23:07:05.976219 [Byte1]: 50
6464 23:07:05.982204
6465 23:07:05.982290 Final RX Vref Byte 0 = 57 to rank0
6466 23:07:05.985324 Final RX Vref Byte 1 = 50 to rank0
6467 23:07:05.988767 Final RX Vref Byte 0 = 57 to rank1
6468 23:07:05.992245 Final RX Vref Byte 1 = 50 to rank1==
6469 23:07:05.995470 Dram Type= 6, Freq= 0, CH_0, rank 0
6470 23:07:06.002397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6471 23:07:06.002591 ==
6472 23:07:06.002685 DQS Delay:
6473 23:07:06.002771 DQS0 = 28, DQS1 = 48
6474 23:07:06.005485 DQM Delay:
6475 23:07:06.005645 DQM0 = 11, DQM1 = 16
6476 23:07:06.009224 DQ Delay:
6477 23:07:06.012325 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6478 23:07:06.012536 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6479 23:07:06.015837 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =12
6480 23:07:06.018599 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =24
6481 23:07:06.018748
6482 23:07:06.022207
6483 23:07:06.028579 [DQSOSCAuto] RK0, (LSB)MR18= 0xb2aa, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 387 ps
6484 23:07:06.031775 CH0 RK0: MR19=C0C, MR18=B2AA
6485 23:07:06.038958 CH0_RK0: MR19=0xC0C, MR18=0xB2AA, DQSOSC=387, MR23=63, INC=394, DEC=262
6486 23:07:06.039044 ==
6487 23:07:06.042139 Dram Type= 6, Freq= 0, CH_0, rank 1
6488 23:07:06.045225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6489 23:07:06.045311 ==
6490 23:07:06.048690 [Gating] SW mode calibration
6491 23:07:06.055566 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6492 23:07:06.062838 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6493 23:07:06.065892 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6494 23:07:06.068911 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6495 23:07:06.072580 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6496 23:07:06.079069 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6497 23:07:06.082484 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6498 23:07:06.085598 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6499 23:07:06.092303 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6500 23:07:06.095682 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6501 23:07:06.098587 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6502 23:07:06.102021 Total UI for P1: 0, mck2ui 16
6503 23:07:06.105487 best dqsien dly found for B0: ( 0, 14, 24)
6504 23:07:06.108913 Total UI for P1: 0, mck2ui 16
6505 23:07:06.112049 best dqsien dly found for B1: ( 0, 14, 24)
6506 23:07:06.115410 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6507 23:07:06.118815 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6508 23:07:06.121990
6509 23:07:06.125333 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6510 23:07:06.128883 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6511 23:07:06.131889 [Gating] SW calibration Done
6512 23:07:06.132528 ==
6513 23:07:06.135000 Dram Type= 6, Freq= 0, CH_0, rank 1
6514 23:07:06.138461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6515 23:07:06.139095 ==
6516 23:07:06.141611 RX Vref Scan: 0
6517 23:07:06.142081
6518 23:07:06.142495 RX Vref 0 -> 0, step: 1
6519 23:07:06.142865
6520 23:07:06.144991 RX Delay -410 -> 252, step: 16
6521 23:07:06.148561 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6522 23:07:06.154996 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6523 23:07:06.158425 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6524 23:07:06.161652 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6525 23:07:06.165152 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6526 23:07:06.171332 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6527 23:07:06.174737 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6528 23:07:06.178214 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6529 23:07:06.181563 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6530 23:07:06.187876 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6531 23:07:06.191632 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6532 23:07:06.194622 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6533 23:07:06.201316 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6534 23:07:06.204378 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6535 23:07:06.207883 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6536 23:07:06.211525 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6537 23:07:06.211978 ==
6538 23:07:06.214468 Dram Type= 6, Freq= 0, CH_0, rank 1
6539 23:07:06.221163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6540 23:07:06.221683 ==
6541 23:07:06.222028 DQS Delay:
6542 23:07:06.224537 DQS0 = 27, DQS1 = 43
6543 23:07:06.225009 DQM Delay:
6544 23:07:06.225493 DQM0 = 9, DQM1 = 15
6545 23:07:06.228013 DQ Delay:
6546 23:07:06.231069 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6547 23:07:06.234548 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6548 23:07:06.235081 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6549 23:07:06.238157 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6550 23:07:06.241264
6551 23:07:06.241793
6552 23:07:06.242131 ==
6553 23:07:06.244304 Dram Type= 6, Freq= 0, CH_0, rank 1
6554 23:07:06.248489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6555 23:07:06.249023 ==
6556 23:07:06.249368
6557 23:07:06.249682
6558 23:07:06.250907 TX Vref Scan disable
6559 23:07:06.251344 == TX Byte 0 ==
6560 23:07:06.254467 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6561 23:07:06.261012 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6562 23:07:06.261587 == TX Byte 1 ==
6563 23:07:06.264385 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6564 23:07:06.271099 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6565 23:07:06.271548 ==
6566 23:07:06.274422 Dram Type= 6, Freq= 0, CH_0, rank 1
6567 23:07:06.277558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6568 23:07:06.278001 ==
6569 23:07:06.278422
6570 23:07:06.278773
6571 23:07:06.281437 TX Vref Scan disable
6572 23:07:06.281896 == TX Byte 0 ==
6573 23:07:06.284352 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6574 23:07:06.291070 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6575 23:07:06.291520 == TX Byte 1 ==
6576 23:07:06.294079 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6577 23:07:06.300814 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6578 23:07:06.301388
6579 23:07:06.301888 [DATLAT]
6580 23:07:06.302423 Freq=400, CH0 RK1
6581 23:07:06.302786
6582 23:07:06.304236 DATLAT Default: 0xe
6583 23:07:06.307565 0, 0xFFFF, sum = 0
6584 23:07:06.308024 1, 0xFFFF, sum = 0
6585 23:07:06.311098 2, 0xFFFF, sum = 0
6586 23:07:06.311533 3, 0xFFFF, sum = 0
6587 23:07:06.314315 4, 0xFFFF, sum = 0
6588 23:07:06.315010 5, 0xFFFF, sum = 0
6589 23:07:06.317607 6, 0xFFFF, sum = 0
6590 23:07:06.318041 7, 0xFFFF, sum = 0
6591 23:07:06.321126 8, 0xFFFF, sum = 0
6592 23:07:06.321559 9, 0xFFFF, sum = 0
6593 23:07:06.324457 10, 0xFFFF, sum = 0
6594 23:07:06.324993 11, 0xFFFF, sum = 0
6595 23:07:06.327702 12, 0xFFFF, sum = 0
6596 23:07:06.328165 13, 0x0, sum = 1
6597 23:07:06.330927 14, 0x0, sum = 2
6598 23:07:06.331392 15, 0x0, sum = 3
6599 23:07:06.333932 16, 0x0, sum = 4
6600 23:07:06.334416 best_step = 14
6601 23:07:06.334795
6602 23:07:06.335122 ==
6603 23:07:06.337364 Dram Type= 6, Freq= 0, CH_0, rank 1
6604 23:07:06.340814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6605 23:07:06.343840 ==
6606 23:07:06.344282 RX Vref Scan: 0
6607 23:07:06.344637
6608 23:07:06.347212 RX Vref 0 -> 0, step: 1
6609 23:07:06.347721
6610 23:07:06.350827 RX Delay -327 -> 252, step: 8
6611 23:07:06.357220 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6612 23:07:06.360575 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6613 23:07:06.364240 iDelay=217, Bit 2, Center -20 (-239 ~ 200) 440
6614 23:07:06.367059 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6615 23:07:06.370734 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6616 23:07:06.377406 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6617 23:07:06.380529 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6618 23:07:06.384149 iDelay=217, Bit 7, Center -12 (-239 ~ 216) 456
6619 23:07:06.387275 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6620 23:07:06.393713 iDelay=217, Bit 9, Center -40 (-263 ~ 184) 448
6621 23:07:06.397210 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6622 23:07:06.400434 iDelay=217, Bit 11, Center -36 (-263 ~ 192) 456
6623 23:07:06.407083 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
6624 23:07:06.410690 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6625 23:07:06.413726 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6626 23:07:06.416939 iDelay=217, Bit 15, Center -24 (-247 ~ 200) 448
6627 23:07:06.417393 ==
6628 23:07:06.420651 Dram Type= 6, Freq= 0, CH_0, rank 1
6629 23:07:06.427151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6630 23:07:06.427582 ==
6631 23:07:06.427922 DQS Delay:
6632 23:07:06.430449 DQS0 = 28, DQS1 = 40
6633 23:07:06.430878 DQM Delay:
6634 23:07:06.433834 DQM0 = 10, DQM1 = 11
6635 23:07:06.434256 DQ Delay:
6636 23:07:06.437366 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =4
6637 23:07:06.440643 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6638 23:07:06.443630 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6639 23:07:06.447269 DQ12 =20, DQ13 =16, DQ14 =20, DQ15 =16
6640 23:07:06.447739
6641 23:07:06.448109
6642 23:07:06.453732 [DQSOSCAuto] RK1, (LSB)MR18= 0xbe71, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 386 ps
6643 23:07:06.456757 CH0 RK1: MR19=C0C, MR18=BE71
6644 23:07:06.463605 CH0_RK1: MR19=0xC0C, MR18=0xBE71, DQSOSC=386, MR23=63, INC=396, DEC=264
6645 23:07:06.467003 [RxdqsGatingPostProcess] freq 400
6646 23:07:06.470456 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6647 23:07:06.473455 best DQS0 dly(2T, 0.5T) = (0, 10)
6648 23:07:06.476785 best DQS1 dly(2T, 0.5T) = (0, 10)
6649 23:07:06.480223 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6650 23:07:06.483436 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6651 23:07:06.486866 best DQS0 dly(2T, 0.5T) = (0, 10)
6652 23:07:06.490116 best DQS1 dly(2T, 0.5T) = (0, 10)
6653 23:07:06.493969 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6654 23:07:06.496695 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6655 23:07:06.500092 Pre-setting of DQS Precalculation
6656 23:07:06.503397 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6657 23:07:06.503869 ==
6658 23:07:06.506719 Dram Type= 6, Freq= 0, CH_1, rank 0
6659 23:07:06.513398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6660 23:07:06.513976 ==
6661 23:07:06.516617 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6662 23:07:06.523311 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6663 23:07:06.527109 [CA 0] Center 36 (8~64) winsize 57
6664 23:07:06.529935 [CA 1] Center 36 (8~64) winsize 57
6665 23:07:06.533104 [CA 2] Center 36 (8~64) winsize 57
6666 23:07:06.536670 [CA 3] Center 36 (8~64) winsize 57
6667 23:07:06.540096 [CA 4] Center 36 (8~64) winsize 57
6668 23:07:06.543398 [CA 5] Center 36 (8~64) winsize 57
6669 23:07:06.543870
6670 23:07:06.546353 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6671 23:07:06.546442
6672 23:07:06.549516 [CATrainingPosCal] consider 1 rank data
6673 23:07:06.553297 u2DelayCellTimex100 = 270/100 ps
6674 23:07:06.556154 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6675 23:07:06.559504 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6676 23:07:06.563147 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6677 23:07:06.566326 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6678 23:07:06.569753 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6679 23:07:06.573196 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6680 23:07:06.573292
6681 23:07:06.579719 CA PerBit enable=1, Macro0, CA PI delay=36
6682 23:07:06.579833
6683 23:07:06.579922 [CBTSetCACLKResult] CA Dly = 36
6684 23:07:06.583350 CS Dly: 1 (0~32)
6685 23:07:06.583462 ==
6686 23:07:06.586241 Dram Type= 6, Freq= 0, CH_1, rank 1
6687 23:07:06.589861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6688 23:07:06.590000 ==
6689 23:07:06.596386 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6690 23:07:06.603358 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6691 23:07:06.606564 [CA 0] Center 36 (8~64) winsize 57
6692 23:07:06.610151 [CA 1] Center 36 (8~64) winsize 57
6693 23:07:06.613269 [CA 2] Center 36 (8~64) winsize 57
6694 23:07:06.613513 [CA 3] Center 36 (8~64) winsize 57
6695 23:07:06.616358 [CA 4] Center 36 (8~64) winsize 57
6696 23:07:06.619731 [CA 5] Center 36 (8~64) winsize 57
6697 23:07:06.620201
6698 23:07:06.626407 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6699 23:07:06.626894
6700 23:07:06.629915 [CATrainingPosCal] consider 2 rank data
6701 23:07:06.633119 u2DelayCellTimex100 = 270/100 ps
6702 23:07:06.636689 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6703 23:07:06.639707 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6704 23:07:06.643093 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6705 23:07:06.646207 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6706 23:07:06.649746 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6707 23:07:06.653131 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6708 23:07:06.653570
6709 23:07:06.656582 CA PerBit enable=1, Macro0, CA PI delay=36
6710 23:07:06.657147
6711 23:07:06.659408 [CBTSetCACLKResult] CA Dly = 36
6712 23:07:06.662843 CS Dly: 1 (0~32)
6713 23:07:06.663278
6714 23:07:06.666454 ----->DramcWriteLeveling(PI) begin...
6715 23:07:06.666908 ==
6716 23:07:06.669664 Dram Type= 6, Freq= 0, CH_1, rank 0
6717 23:07:06.673025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6718 23:07:06.673513 ==
6719 23:07:06.676198 Write leveling (Byte 0): 40 => 8
6720 23:07:06.679572 Write leveling (Byte 1): 32 => 0
6721 23:07:06.682717 DramcWriteLeveling(PI) end<-----
6722 23:07:06.683236
6723 23:07:06.683729 ==
6724 23:07:06.686302 Dram Type= 6, Freq= 0, CH_1, rank 0
6725 23:07:06.689833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6726 23:07:06.690296 ==
6727 23:07:06.693063 [Gating] SW mode calibration
6728 23:07:06.699337 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6729 23:07:06.706284 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6730 23:07:06.709760 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6731 23:07:06.712595 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6732 23:07:06.719596 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6733 23:07:06.722540 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6734 23:07:06.725956 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6735 23:07:06.732571 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6736 23:07:06.736151 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6737 23:07:06.739035 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6738 23:07:06.745733 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6739 23:07:06.746162 Total UI for P1: 0, mck2ui 16
6740 23:07:06.752797 best dqsien dly found for B0: ( 0, 14, 24)
6741 23:07:06.753247 Total UI for P1: 0, mck2ui 16
6742 23:07:06.759523 best dqsien dly found for B1: ( 0, 14, 24)
6743 23:07:06.763238 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6744 23:07:06.766066 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6745 23:07:06.766535
6746 23:07:06.769129 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6747 23:07:06.772912 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6748 23:07:06.776279 [Gating] SW calibration Done
6749 23:07:06.776708 ==
6750 23:07:06.778985 Dram Type= 6, Freq= 0, CH_1, rank 0
6751 23:07:06.782560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6752 23:07:06.782988 ==
6753 23:07:06.786161 RX Vref Scan: 0
6754 23:07:06.786631
6755 23:07:06.786972 RX Vref 0 -> 0, step: 1
6756 23:07:06.787293
6757 23:07:06.789174 RX Delay -410 -> 252, step: 16
6758 23:07:06.795767 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6759 23:07:06.799173 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6760 23:07:06.802603 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6761 23:07:06.805735 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6762 23:07:06.812156 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6763 23:07:06.815519 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6764 23:07:06.818956 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6765 23:07:06.822144 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6766 23:07:06.829473 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6767 23:07:06.832163 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6768 23:07:06.835592 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6769 23:07:06.839172 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6770 23:07:06.845412 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6771 23:07:06.848680 iDelay=230, Bit 13, Center -11 (-250 ~ 229) 480
6772 23:07:06.851851 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6773 23:07:06.855261 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6774 23:07:06.858368 ==
6775 23:07:06.861932 Dram Type= 6, Freq= 0, CH_1, rank 0
6776 23:07:06.865015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6777 23:07:06.865417 ==
6778 23:07:06.865768 DQS Delay:
6779 23:07:06.868478 DQS0 = 27, DQS1 = 43
6780 23:07:06.868929 DQM Delay:
6781 23:07:06.871858 DQM0 = 6, DQM1 = 17
6782 23:07:06.872312 DQ Delay:
6783 23:07:06.874904 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6784 23:07:06.878821 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6785 23:07:06.881789 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6786 23:07:06.885138 DQ12 =32, DQ13 =32, DQ14 =16, DQ15 =24
6787 23:07:06.885566
6788 23:07:06.885930
6789 23:07:06.886259 ==
6790 23:07:06.888700 Dram Type= 6, Freq= 0, CH_1, rank 0
6791 23:07:06.891669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6792 23:07:06.892103 ==
6793 23:07:06.892443
6794 23:07:06.892755
6795 23:07:06.895117 TX Vref Scan disable
6796 23:07:06.895583 == TX Byte 0 ==
6797 23:07:06.901964 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6798 23:07:06.905111 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6799 23:07:06.905564 == TX Byte 1 ==
6800 23:07:06.911873 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6801 23:07:06.914846 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6802 23:07:06.915275 ==
6803 23:07:06.918619 Dram Type= 6, Freq= 0, CH_1, rank 0
6804 23:07:06.921926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6805 23:07:06.922376 ==
6806 23:07:06.922757
6807 23:07:06.923079
6808 23:07:06.925191 TX Vref Scan disable
6809 23:07:06.928105 == TX Byte 0 ==
6810 23:07:06.931554 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6811 23:07:06.934875 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6812 23:07:06.935316 == TX Byte 1 ==
6813 23:07:06.941511 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6814 23:07:06.944866 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6815 23:07:06.945297
6816 23:07:06.945659 [DATLAT]
6817 23:07:06.947987 Freq=400, CH1 RK0
6818 23:07:06.948441
6819 23:07:06.948792 DATLAT Default: 0xf
6820 23:07:06.951230 0, 0xFFFF, sum = 0
6821 23:07:06.951676 1, 0xFFFF, sum = 0
6822 23:07:06.954660 2, 0xFFFF, sum = 0
6823 23:07:06.957951 3, 0xFFFF, sum = 0
6824 23:07:06.958406 4, 0xFFFF, sum = 0
6825 23:07:06.961527 5, 0xFFFF, sum = 0
6826 23:07:06.961958 6, 0xFFFF, sum = 0
6827 23:07:06.964771 7, 0xFFFF, sum = 0
6828 23:07:06.965200 8, 0xFFFF, sum = 0
6829 23:07:06.967786 9, 0xFFFF, sum = 0
6830 23:07:06.968216 10, 0xFFFF, sum = 0
6831 23:07:06.971105 11, 0xFFFF, sum = 0
6832 23:07:06.971535 12, 0xFFFF, sum = 0
6833 23:07:06.974648 13, 0x0, sum = 1
6834 23:07:06.975082 14, 0x0, sum = 2
6835 23:07:06.978184 15, 0x0, sum = 3
6836 23:07:06.978643 16, 0x0, sum = 4
6837 23:07:06.980708 best_step = 14
6838 23:07:06.980790
6839 23:07:06.980855 ==
6840 23:07:06.984236 Dram Type= 6, Freq= 0, CH_1, rank 0
6841 23:07:06.987904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6842 23:07:06.988069 ==
6843 23:07:06.988145 RX Vref Scan: 1
6844 23:07:06.990654
6845 23:07:06.990824 RX Vref 0 -> 0, step: 1
6846 23:07:06.990916
6847 23:07:06.994372 RX Delay -327 -> 252, step: 8
6848 23:07:06.994562
6849 23:07:06.997482 Set Vref, RX VrefLevel [Byte0]: 54
6850 23:07:07.000669 [Byte1]: 54
6851 23:07:07.005202
6852 23:07:07.005396 Final RX Vref Byte 0 = 54 to rank0
6853 23:07:07.008771 Final RX Vref Byte 1 = 54 to rank0
6854 23:07:07.011555 Final RX Vref Byte 0 = 54 to rank1
6855 23:07:07.015234 Final RX Vref Byte 1 = 54 to rank1==
6856 23:07:07.018466 Dram Type= 6, Freq= 0, CH_1, rank 0
6857 23:07:07.024814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6858 23:07:07.025073 ==
6859 23:07:07.025229 DQS Delay:
6860 23:07:07.028511 DQS0 = 28, DQS1 = 40
6861 23:07:07.028773 DQM Delay:
6862 23:07:07.028922 DQM0 = 8, DQM1 = 14
6863 23:07:07.032080 DQ Delay:
6864 23:07:07.035084 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6865 23:07:07.035421 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =4
6866 23:07:07.038474 DQ8 =0, DQ9 =0, DQ10 =20, DQ11 =4
6867 23:07:07.042273 DQ12 =28, DQ13 =20, DQ14 =20, DQ15 =20
6868 23:07:07.042702
6869 23:07:07.042954
6870 23:07:07.051800 [DQSOSCAuto] RK0, (LSB)MR18= 0x92cc, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6871 23:07:07.054806 CH1 RK0: MR19=C0C, MR18=92CC
6872 23:07:07.061804 CH1_RK0: MR19=0xC0C, MR18=0x92CC, DQSOSC=384, MR23=63, INC=400, DEC=267
6873 23:07:07.062278 ==
6874 23:07:07.064837 Dram Type= 6, Freq= 0, CH_1, rank 1
6875 23:07:07.068359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6876 23:07:07.068873 ==
6877 23:07:07.071529 [Gating] SW mode calibration
6878 23:07:07.078011 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6879 23:07:07.081565 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6880 23:07:07.088044 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6881 23:07:07.091408 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6882 23:07:07.094851 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6883 23:07:07.101288 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6884 23:07:07.104741 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6885 23:07:07.108032 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6886 23:07:07.115007 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6887 23:07:07.118001 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6888 23:07:07.121173 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6889 23:07:07.124547 Total UI for P1: 0, mck2ui 16
6890 23:07:07.127770 best dqsien dly found for B0: ( 0, 14, 24)
6891 23:07:07.131619 Total UI for P1: 0, mck2ui 16
6892 23:07:07.134696 best dqsien dly found for B1: ( 0, 14, 24)
6893 23:07:07.137865 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6894 23:07:07.141456 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6895 23:07:07.144554
6896 23:07:07.147871 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6897 23:07:07.151130 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6898 23:07:07.154363 [Gating] SW calibration Done
6899 23:07:07.155028 ==
6900 23:07:07.157664 Dram Type= 6, Freq= 0, CH_1, rank 1
6901 23:07:07.161225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6902 23:07:07.161800 ==
6903 23:07:07.162278 RX Vref Scan: 0
6904 23:07:07.162826
6905 23:07:07.164519 RX Vref 0 -> 0, step: 1
6906 23:07:07.165050
6907 23:07:07.167767 RX Delay -410 -> 252, step: 16
6908 23:07:07.171296 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6909 23:07:07.177705 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6910 23:07:07.180893 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6911 23:07:07.184222 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6912 23:07:07.187545 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6913 23:07:07.194358 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6914 23:07:07.197279 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6915 23:07:07.201116 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6916 23:07:07.204600 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6917 23:07:07.210842 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6918 23:07:07.214123 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6919 23:07:07.217417 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6920 23:07:07.220831 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6921 23:07:07.227436 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6922 23:07:07.230885 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6923 23:07:07.234602 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6924 23:07:07.235123 ==
6925 23:07:07.237743 Dram Type= 6, Freq= 0, CH_1, rank 1
6926 23:07:07.241194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6927 23:07:07.244715 ==
6928 23:07:07.245286 DQS Delay:
6929 23:07:07.245659 DQS0 = 35, DQS1 = 43
6930 23:07:07.247526 DQM Delay:
6931 23:07:07.248098 DQM0 = 17, DQM1 = 18
6932 23:07:07.250548 DQ Delay:
6933 23:07:07.254327 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6934 23:07:07.257885 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6935 23:07:07.258510 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6936 23:07:07.260947 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =32
6937 23:07:07.264027
6938 23:07:07.264494
6939 23:07:07.264864 ==
6940 23:07:07.267303 Dram Type= 6, Freq= 0, CH_1, rank 1
6941 23:07:07.271293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6942 23:07:07.271889 ==
6943 23:07:07.272264
6944 23:07:07.272607
6945 23:07:07.274050 TX Vref Scan disable
6946 23:07:07.274549 == TX Byte 0 ==
6947 23:07:07.277224 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6948 23:07:07.284369 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6949 23:07:07.284841 == TX Byte 1 ==
6950 23:07:07.287488 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6951 23:07:07.293497 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6952 23:07:07.293581 ==
6953 23:07:07.297047 Dram Type= 6, Freq= 0, CH_1, rank 1
6954 23:07:07.300167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6955 23:07:07.300251 ==
6956 23:07:07.300317
6957 23:07:07.300378
6958 23:07:07.303700 TX Vref Scan disable
6959 23:07:07.303783 == TX Byte 0 ==
6960 23:07:07.306829 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6961 23:07:07.313527 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6962 23:07:07.313611 == TX Byte 1 ==
6963 23:07:07.316992 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6964 23:07:07.323423 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6965 23:07:07.323508
6966 23:07:07.323573 [DATLAT]
6967 23:07:07.323634 Freq=400, CH1 RK1
6968 23:07:07.323693
6969 23:07:07.326508 DATLAT Default: 0xe
6970 23:07:07.329915 0, 0xFFFF, sum = 0
6971 23:07:07.330000 1, 0xFFFF, sum = 0
6972 23:07:07.333206 2, 0xFFFF, sum = 0
6973 23:07:07.333290 3, 0xFFFF, sum = 0
6974 23:07:07.336408 4, 0xFFFF, sum = 0
6975 23:07:07.336493 5, 0xFFFF, sum = 0
6976 23:07:07.340017 6, 0xFFFF, sum = 0
6977 23:07:07.340101 7, 0xFFFF, sum = 0
6978 23:07:07.343128 8, 0xFFFF, sum = 0
6979 23:07:07.343212 9, 0xFFFF, sum = 0
6980 23:07:07.346929 10, 0xFFFF, sum = 0
6981 23:07:07.347013 11, 0xFFFF, sum = 0
6982 23:07:07.349727 12, 0xFFFF, sum = 0
6983 23:07:07.349811 13, 0x0, sum = 1
6984 23:07:07.353087 14, 0x0, sum = 2
6985 23:07:07.353171 15, 0x0, sum = 3
6986 23:07:07.356517 16, 0x0, sum = 4
6987 23:07:07.356601 best_step = 14
6988 23:07:07.356666
6989 23:07:07.356751 ==
6990 23:07:07.360619 Dram Type= 6, Freq= 0, CH_1, rank 1
6991 23:07:07.363596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6992 23:07:07.366629 ==
6993 23:07:07.366711 RX Vref Scan: 0
6994 23:07:07.366777
6995 23:07:07.369938 RX Vref 0 -> 0, step: 1
6996 23:07:07.370021
6997 23:07:07.373196 RX Delay -327 -> 252, step: 8
6998 23:07:07.376601 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6999 23:07:07.383133 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
7000 23:07:07.386761 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
7001 23:07:07.389777 iDelay=217, Bit 3, Center -20 (-247 ~ 208) 456
7002 23:07:07.396457 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
7003 23:07:07.399812 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
7004 23:07:07.402899 iDelay=217, Bit 6, Center -16 (-239 ~ 208) 448
7005 23:07:07.406575 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
7006 23:07:07.410031 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
7007 23:07:07.416428 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
7008 23:07:07.419784 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
7009 23:07:07.422858 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
7010 23:07:07.429733 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
7011 23:07:07.432988 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
7012 23:07:07.436113 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
7013 23:07:07.439439 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
7014 23:07:07.439522 ==
7015 23:07:07.442769 Dram Type= 6, Freq= 0, CH_1, rank 1
7016 23:07:07.449268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7017 23:07:07.449354 ==
7018 23:07:07.449420 DQS Delay:
7019 23:07:07.452787 DQS0 = 32, DQS1 = 36
7020 23:07:07.452870 DQM Delay:
7021 23:07:07.456080 DQM0 = 13, DQM1 = 12
7022 23:07:07.456163 DQ Delay:
7023 23:07:07.459524 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =12
7024 23:07:07.462656 DQ4 =16, DQ5 =24, DQ6 =16, DQ7 =12
7025 23:07:07.466374 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =8
7026 23:07:07.469392 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =24
7027 23:07:07.469475
7028 23:07:07.469540
7029 23:07:07.475756 [DQSOSCAuto] RK1, (LSB)MR18= 0xab52, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 388 ps
7030 23:07:07.479454 CH1 RK1: MR19=C0C, MR18=AB52
7031 23:07:07.485829 CH1_RK1: MR19=0xC0C, MR18=0xAB52, DQSOSC=388, MR23=63, INC=392, DEC=261
7032 23:07:07.489310 [RxdqsGatingPostProcess] freq 400
7033 23:07:07.492368 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7034 23:07:07.495632 best DQS0 dly(2T, 0.5T) = (0, 10)
7035 23:07:07.499285 best DQS1 dly(2T, 0.5T) = (0, 10)
7036 23:07:07.502033 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7037 23:07:07.505441 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7038 23:07:07.508966 best DQS0 dly(2T, 0.5T) = (0, 10)
7039 23:07:07.511968 best DQS1 dly(2T, 0.5T) = (0, 10)
7040 23:07:07.515367 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7041 23:07:07.518640 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7042 23:07:07.522141 Pre-setting of DQS Precalculation
7043 23:07:07.528582 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7044 23:07:07.535306 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7045 23:07:07.541861 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7046 23:07:07.541946
7047 23:07:07.542013
7048 23:07:07.545168 [Calibration Summary] 800 Mbps
7049 23:07:07.545251 CH 0, Rank 0
7050 23:07:07.548881 SW Impedance : PASS
7051 23:07:07.548964 DUTY Scan : NO K
7052 23:07:07.551708 ZQ Calibration : PASS
7053 23:07:07.555160 Jitter Meter : NO K
7054 23:07:07.555244 CBT Training : PASS
7055 23:07:07.558560 Write leveling : PASS
7056 23:07:07.561762 RX DQS gating : PASS
7057 23:07:07.561844 RX DQ/DQS(RDDQC) : PASS
7058 23:07:07.565080 TX DQ/DQS : PASS
7059 23:07:07.568514 RX DATLAT : PASS
7060 23:07:07.568598 RX DQ/DQS(Engine): PASS
7061 23:07:07.571956 TX OE : NO K
7062 23:07:07.572040 All Pass.
7063 23:07:07.572105
7064 23:07:07.574950 CH 0, Rank 1
7065 23:07:07.575032 SW Impedance : PASS
7066 23:07:07.578323 DUTY Scan : NO K
7067 23:07:07.582227 ZQ Calibration : PASS
7068 23:07:07.582336 Jitter Meter : NO K
7069 23:07:07.585003 CBT Training : PASS
7070 23:07:07.588328 Write leveling : NO K
7071 23:07:07.588412 RX DQS gating : PASS
7072 23:07:07.591538 RX DQ/DQS(RDDQC) : PASS
7073 23:07:07.595213 TX DQ/DQS : PASS
7074 23:07:07.595296 RX DATLAT : PASS
7075 23:07:07.598017 RX DQ/DQS(Engine): PASS
7076 23:07:07.598126 TX OE : NO K
7077 23:07:07.601482 All Pass.
7078 23:07:07.601579
7079 23:07:07.601646 CH 1, Rank 0
7080 23:07:07.604751 SW Impedance : PASS
7081 23:07:07.604834 DUTY Scan : NO K
7082 23:07:07.608290 ZQ Calibration : PASS
7083 23:07:07.611220 Jitter Meter : NO K
7084 23:07:07.611303 CBT Training : PASS
7085 23:07:07.614827 Write leveling : PASS
7086 23:07:07.618077 RX DQS gating : PASS
7087 23:07:07.618160 RX DQ/DQS(RDDQC) : PASS
7088 23:07:07.621644 TX DQ/DQS : PASS
7089 23:07:07.624711 RX DATLAT : PASS
7090 23:07:07.624795 RX DQ/DQS(Engine): PASS
7091 23:07:07.628282 TX OE : NO K
7092 23:07:07.628366 All Pass.
7093 23:07:07.628432
7094 23:07:07.631366 CH 1, Rank 1
7095 23:07:07.631449 SW Impedance : PASS
7096 23:07:07.634551 DUTY Scan : NO K
7097 23:07:07.638050 ZQ Calibration : PASS
7098 23:07:07.638134 Jitter Meter : NO K
7099 23:07:07.641178 CBT Training : PASS
7100 23:07:07.644503 Write leveling : NO K
7101 23:07:07.644586 RX DQS gating : PASS
7102 23:07:07.647952 RX DQ/DQS(RDDQC) : PASS
7103 23:07:07.651317 TX DQ/DQS : PASS
7104 23:07:07.651400 RX DATLAT : PASS
7105 23:07:07.654489 RX DQ/DQS(Engine): PASS
7106 23:07:07.654572 TX OE : NO K
7107 23:07:07.657866 All Pass.
7108 23:07:07.657948
7109 23:07:07.658012 DramC Write-DBI off
7110 23:07:07.661269 PER_BANK_REFRESH: Hybrid Mode
7111 23:07:07.664569 TX_TRACKING: ON
7112 23:07:07.671378 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7113 23:07:07.674237 [FAST_K] Save calibration result to emmc
7114 23:07:07.681165 dramc_set_vcore_voltage set vcore to 725000
7115 23:07:07.681249 Read voltage for 1600, 0
7116 23:07:07.684385 Vio18 = 0
7117 23:07:07.684474 Vcore = 725000
7118 23:07:07.684544 Vdram = 0
7119 23:07:07.684608 Vddq = 0
7120 23:07:07.687724 Vmddr = 0
7121 23:07:07.690953 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7122 23:07:07.697785 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7123 23:07:07.701323 MEM_TYPE=3, freq_sel=13
7124 23:07:07.701436 sv_algorithm_assistance_LP4_3733
7125 23:07:07.707611 ============ PULL DRAM RESETB DOWN ============
7126 23:07:07.711019 ========== PULL DRAM RESETB DOWN end =========
7127 23:07:07.714583 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7128 23:07:07.718087 ===================================
7129 23:07:07.721318 LPDDR4 DRAM CONFIGURATION
7130 23:07:07.724584 ===================================
7131 23:07:07.727620 EX_ROW_EN[0] = 0x0
7132 23:07:07.727823 EX_ROW_EN[1] = 0x0
7133 23:07:07.731055 LP4Y_EN = 0x0
7134 23:07:07.731308 WORK_FSP = 0x1
7135 23:07:07.734610 WL = 0x5
7136 23:07:07.734698 RL = 0x5
7137 23:07:07.737678 BL = 0x2
7138 23:07:07.737767 RPST = 0x0
7139 23:07:07.741063 RD_PRE = 0x0
7140 23:07:07.741159 WR_PRE = 0x1
7141 23:07:07.744237 WR_PST = 0x1
7142 23:07:07.744340 DBI_WR = 0x0
7143 23:07:07.747734 DBI_RD = 0x0
7144 23:07:07.747837 OTF = 0x1
7145 23:07:07.750850 ===================================
7146 23:07:07.754208 ===================================
7147 23:07:07.757609 ANA top config
7148 23:07:07.761040 ===================================
7149 23:07:07.764093 DLL_ASYNC_EN = 0
7150 23:07:07.764253 ALL_SLAVE_EN = 0
7151 23:07:07.767593 NEW_RANK_MODE = 1
7152 23:07:07.771000 DLL_IDLE_MODE = 1
7153 23:07:07.774072 LP45_APHY_COMB_EN = 1
7154 23:07:07.774274 TX_ODT_DIS = 0
7155 23:07:07.777534 NEW_8X_MODE = 1
7156 23:07:07.781183 ===================================
7157 23:07:07.784330 ===================================
7158 23:07:07.787690 data_rate = 3200
7159 23:07:07.791029 CKR = 1
7160 23:07:07.794293 DQ_P2S_RATIO = 8
7161 23:07:07.797854 ===================================
7162 23:07:07.801006 CA_P2S_RATIO = 8
7163 23:07:07.801481 DQ_CA_OPEN = 0
7164 23:07:07.804156 DQ_SEMI_OPEN = 0
7165 23:07:07.807710 CA_SEMI_OPEN = 0
7166 23:07:07.811194 CA_FULL_RATE = 0
7167 23:07:07.814092 DQ_CKDIV4_EN = 0
7168 23:07:07.817731 CA_CKDIV4_EN = 0
7169 23:07:07.818238 CA_PREDIV_EN = 0
7170 23:07:07.821249 PH8_DLY = 12
7171 23:07:07.824294 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7172 23:07:07.827891 DQ_AAMCK_DIV = 4
7173 23:07:07.830680 CA_AAMCK_DIV = 4
7174 23:07:07.834345 CA_ADMCK_DIV = 4
7175 23:07:07.834897 DQ_TRACK_CA_EN = 0
7176 23:07:07.837543 CA_PICK = 1600
7177 23:07:07.840539 CA_MCKIO = 1600
7178 23:07:07.844086 MCKIO_SEMI = 0
7179 23:07:07.847249 PLL_FREQ = 3068
7180 23:07:07.850818 DQ_UI_PI_RATIO = 32
7181 23:07:07.854094 CA_UI_PI_RATIO = 0
7182 23:07:07.857525 ===================================
7183 23:07:07.860513 ===================================
7184 23:07:07.861155 memory_type:LPDDR4
7185 23:07:07.864137 GP_NUM : 10
7186 23:07:07.867439 SRAM_EN : 1
7187 23:07:07.867912 MD32_EN : 0
7188 23:07:07.870706 ===================================
7189 23:07:07.874096 [ANA_INIT] >>>>>>>>>>>>>>
7190 23:07:07.877176 <<<<<< [CONFIGURE PHASE]: ANA_TX
7191 23:07:07.880700 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7192 23:07:07.883698 ===================================
7193 23:07:07.887135 data_rate = 3200,PCW = 0X7600
7194 23:07:07.890543 ===================================
7195 23:07:07.893899 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7196 23:07:07.897204 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7197 23:07:07.904198 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7198 23:07:07.907371 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7199 23:07:07.913604 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7200 23:07:07.916915 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7201 23:07:07.917358 [ANA_INIT] flow start
7202 23:07:07.920440 [ANA_INIT] PLL >>>>>>>>
7203 23:07:07.923728 [ANA_INIT] PLL <<<<<<<<
7204 23:07:07.924169 [ANA_INIT] MIDPI >>>>>>>>
7205 23:07:07.926741 [ANA_INIT] MIDPI <<<<<<<<
7206 23:07:07.930218 [ANA_INIT] DLL >>>>>>>>
7207 23:07:07.930701 [ANA_INIT] DLL <<<<<<<<
7208 23:07:07.933660 [ANA_INIT] flow end
7209 23:07:07.936794 ============ LP4 DIFF to SE enter ============
7210 23:07:07.940277 ============ LP4 DIFF to SE exit ============
7211 23:07:07.943422 [ANA_INIT] <<<<<<<<<<<<<
7212 23:07:07.946848 [Flow] Enable top DCM control >>>>>
7213 23:07:07.950020 [Flow] Enable top DCM control <<<<<
7214 23:07:07.953523 Enable DLL master slave shuffle
7215 23:07:07.960077 ==============================================================
7216 23:07:07.960512 Gating Mode config
7217 23:07:07.966752 ==============================================================
7218 23:07:07.967193 Config description:
7219 23:07:07.976525 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7220 23:07:07.983395 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7221 23:07:07.990088 SELPH_MODE 0: By rank 1: By Phase
7222 23:07:07.992979 ==============================================================
7223 23:07:07.996216 GAT_TRACK_EN = 1
7224 23:07:07.999738 RX_GATING_MODE = 2
7225 23:07:08.003110 RX_GATING_TRACK_MODE = 2
7226 23:07:08.006106 SELPH_MODE = 1
7227 23:07:08.009664 PICG_EARLY_EN = 1
7228 23:07:08.013229 VALID_LAT_VALUE = 1
7229 23:07:08.019366 ==============================================================
7230 23:07:08.022639 Enter into Gating configuration >>>>
7231 23:07:08.026075 Exit from Gating configuration <<<<
7232 23:07:08.029188 Enter into DVFS_PRE_config >>>>>
7233 23:07:08.039703 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7234 23:07:08.043306 Exit from DVFS_PRE_config <<<<<
7235 23:07:08.046197 Enter into PICG configuration >>>>
7236 23:07:08.049764 Exit from PICG configuration <<<<
7237 23:07:08.050167 [RX_INPUT] configuration >>>>>
7238 23:07:08.052602 [RX_INPUT] configuration <<<<<
7239 23:07:08.059251 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7240 23:07:08.066338 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7241 23:07:08.069492 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7242 23:07:08.075899 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7243 23:07:08.082655 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7244 23:07:08.089348 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7245 23:07:08.092873 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7246 23:07:08.096080 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7247 23:07:08.102932 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7248 23:07:08.106094 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7249 23:07:08.109504 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7250 23:07:08.112517 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7251 23:07:08.116023 ===================================
7252 23:07:08.119677 LPDDR4 DRAM CONFIGURATION
7253 23:07:08.122581 ===================================
7254 23:07:08.126158 EX_ROW_EN[0] = 0x0
7255 23:07:08.126634 EX_ROW_EN[1] = 0x0
7256 23:07:08.129113 LP4Y_EN = 0x0
7257 23:07:08.129632 WORK_FSP = 0x1
7258 23:07:08.132598 WL = 0x5
7259 23:07:08.133035 RL = 0x5
7260 23:07:08.135886 BL = 0x2
7261 23:07:08.136315 RPST = 0x0
7262 23:07:08.139324 RD_PRE = 0x0
7263 23:07:08.142651 WR_PRE = 0x1
7264 23:07:08.143082 WR_PST = 0x1
7265 23:07:08.145756 DBI_WR = 0x0
7266 23:07:08.146217 DBI_RD = 0x0
7267 23:07:08.149147 OTF = 0x1
7268 23:07:08.152529 ===================================
7269 23:07:08.156173 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7270 23:07:08.159156 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7271 23:07:08.162818 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7272 23:07:08.165950 ===================================
7273 23:07:08.169137 LPDDR4 DRAM CONFIGURATION
7274 23:07:08.172849 ===================================
7275 23:07:08.175871 EX_ROW_EN[0] = 0x10
7276 23:07:08.176347 EX_ROW_EN[1] = 0x0
7277 23:07:08.179604 LP4Y_EN = 0x0
7278 23:07:08.180202 WORK_FSP = 0x1
7279 23:07:08.182347 WL = 0x5
7280 23:07:08.182857 RL = 0x5
7281 23:07:08.185782 BL = 0x2
7282 23:07:08.186269 RPST = 0x0
7283 23:07:08.189334 RD_PRE = 0x0
7284 23:07:08.189959 WR_PRE = 0x1
7285 23:07:08.192253 WR_PST = 0x1
7286 23:07:08.192744 DBI_WR = 0x0
7287 23:07:08.196031 DBI_RD = 0x0
7288 23:07:08.196617 OTF = 0x1
7289 23:07:08.199131 ===================================
7290 23:07:08.205796 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7291 23:07:08.206297 ==
7292 23:07:08.209064 Dram Type= 6, Freq= 0, CH_0, rank 0
7293 23:07:08.215944 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7294 23:07:08.216425 ==
7295 23:07:08.216837 [Duty_Offset_Calibration]
7296 23:07:08.219221 B0:2 B1:0 CA:1
7297 23:07:08.219710
7298 23:07:08.222507 [DutyScan_Calibration_Flow] k_type=0
7299 23:07:08.230756
7300 23:07:08.231236 ==CLK 0==
7301 23:07:08.233964 Final CLK duty delay cell = -4
7302 23:07:08.237510 [-4] MAX Duty = 5031%(X100), DQS PI = 28
7303 23:07:08.240919 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7304 23:07:08.244415 [-4] AVG Duty = 4937%(X100)
7305 23:07:08.245181
7306 23:07:08.247336 CH0 CLK Duty spec in!! Max-Min= 187%
7307 23:07:08.250647 [DutyScan_Calibration_Flow] ====Done====
7308 23:07:08.251273
7309 23:07:08.253854 [DutyScan_Calibration_Flow] k_type=1
7310 23:07:08.270457
7311 23:07:08.270888 ==DQS 0 ==
7312 23:07:08.273939 Final DQS duty delay cell = 0
7313 23:07:08.276934 [0] MAX Duty = 5249%(X100), DQS PI = 32
7314 23:07:08.280284 [0] MIN Duty = 4969%(X100), DQS PI = 2
7315 23:07:08.280711 [0] AVG Duty = 5109%(X100)
7316 23:07:08.284018
7317 23:07:08.284474 ==DQS 1 ==
7318 23:07:08.286974 Final DQS duty delay cell = -4
7319 23:07:08.290187 [-4] MAX Duty = 5125%(X100), DQS PI = 28
7320 23:07:08.293568 [-4] MIN Duty = 4875%(X100), DQS PI = 4
7321 23:07:08.296926 [-4] AVG Duty = 5000%(X100)
7322 23:07:08.297357
7323 23:07:08.300694 CH0 DQS 0 Duty spec in!! Max-Min= 280%
7324 23:07:08.301124
7325 23:07:08.303922 CH0 DQS 1 Duty spec in!! Max-Min= 250%
7326 23:07:08.306954 [DutyScan_Calibration_Flow] ====Done====
7327 23:07:08.307378
7328 23:07:08.309952 [DutyScan_Calibration_Flow] k_type=3
7329 23:07:08.327906
7330 23:07:08.328378 ==DQM 0 ==
7331 23:07:08.330978 Final DQM duty delay cell = 0
7332 23:07:08.335077 [0] MAX Duty = 5093%(X100), DQS PI = 26
7333 23:07:08.337865 [0] MIN Duty = 4813%(X100), DQS PI = 50
7334 23:07:08.341165 [0] AVG Duty = 4953%(X100)
7335 23:07:08.341744
7336 23:07:08.342117 ==DQM 1 ==
7337 23:07:08.344254 Final DQM duty delay cell = 0
7338 23:07:08.347476 [0] MAX Duty = 5249%(X100), DQS PI = 28
7339 23:07:08.351067 [0] MIN Duty = 5031%(X100), DQS PI = 6
7340 23:07:08.354046 [0] AVG Duty = 5140%(X100)
7341 23:07:08.354556
7342 23:07:08.357320 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7343 23:07:08.357788
7344 23:07:08.360874 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7345 23:07:08.364145 [DutyScan_Calibration_Flow] ====Done====
7346 23:07:08.364641
7347 23:07:08.367626 [DutyScan_Calibration_Flow] k_type=2
7348 23:07:08.384663
7349 23:07:08.385089 ==DQ 0 ==
7350 23:07:08.388328 Final DQ duty delay cell = 0
7351 23:07:08.391551 [0] MAX Duty = 5124%(X100), DQS PI = 34
7352 23:07:08.394302 [0] MIN Duty = 5000%(X100), DQS PI = 0
7353 23:07:08.394440 [0] AVG Duty = 5062%(X100)
7354 23:07:08.397978
7355 23:07:08.398060 ==DQ 1 ==
7356 23:07:08.401432 Final DQ duty delay cell = 0
7357 23:07:08.404280 [0] MAX Duty = 4969%(X100), DQS PI = 44
7358 23:07:08.408087 [0] MIN Duty = 4875%(X100), DQS PI = 10
7359 23:07:08.408182 [0] AVG Duty = 4922%(X100)
7360 23:07:08.408256
7361 23:07:08.411264 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7362 23:07:08.414549
7363 23:07:08.417952 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7364 23:07:08.421218 [DutyScan_Calibration_Flow] ====Done====
7365 23:07:08.421332 ==
7366 23:07:08.424530 Dram Type= 6, Freq= 0, CH_1, rank 0
7367 23:07:08.427965 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7368 23:07:08.428408 ==
7369 23:07:08.431464 [Duty_Offset_Calibration]
7370 23:07:08.431980 B0:0 B1:-1 CA:2
7371 23:07:08.432433
7372 23:07:08.434987 [DutyScan_Calibration_Flow] k_type=0
7373 23:07:08.444846
7374 23:07:08.445262 ==CLK 0==
7375 23:07:08.448149 Final CLK duty delay cell = 0
7376 23:07:08.451544 [0] MAX Duty = 5156%(X100), DQS PI = 40
7377 23:07:08.455148 [0] MIN Duty = 4906%(X100), DQS PI = 12
7378 23:07:08.455564 [0] AVG Duty = 5031%(X100)
7379 23:07:08.458209
7380 23:07:08.461597 CH1 CLK Duty spec in!! Max-Min= 250%
7381 23:07:08.464774 [DutyScan_Calibration_Flow] ====Done====
7382 23:07:08.465321
7383 23:07:08.468098 [DutyScan_Calibration_Flow] k_type=1
7384 23:07:08.485906
7385 23:07:08.486434 ==DQS 0 ==
7386 23:07:08.488240 Final DQS duty delay cell = 0
7387 23:07:08.491331 [0] MAX Duty = 5093%(X100), DQS PI = 8
7388 23:07:08.494787 [0] MIN Duty = 4969%(X100), DQS PI = 50
7389 23:07:08.498146 [0] AVG Duty = 5031%(X100)
7390 23:07:08.498591
7391 23:07:08.498945 ==DQS 1 ==
7392 23:07:08.501189 Final DQS duty delay cell = 0
7393 23:07:08.504597 [0] MAX Duty = 5187%(X100), DQS PI = 26
7394 23:07:08.508115 [0] MIN Duty = 4813%(X100), DQS PI = 2
7395 23:07:08.511329 [0] AVG Duty = 5000%(X100)
7396 23:07:08.511743
7397 23:07:08.514498 CH1 DQS 0 Duty spec in!! Max-Min= 124%
7398 23:07:08.514917
7399 23:07:08.517591 CH1 DQS 1 Duty spec in!! Max-Min= 374%
7400 23:07:08.520934 [DutyScan_Calibration_Flow] ====Done====
7401 23:07:08.521367
7402 23:07:08.524231 [DutyScan_Calibration_Flow] k_type=3
7403 23:07:08.542622
7404 23:07:08.543069 ==DQM 0 ==
7405 23:07:08.545616 Final DQM duty delay cell = 4
7406 23:07:08.548737 [4] MAX Duty = 5156%(X100), DQS PI = 24
7407 23:07:08.552109 [4] MIN Duty = 4969%(X100), DQS PI = 0
7408 23:07:08.555448 [4] AVG Duty = 5062%(X100)
7409 23:07:08.555895
7410 23:07:08.556236 ==DQM 1 ==
7411 23:07:08.558649 Final DQM duty delay cell = 0
7412 23:07:08.562184 [0] MAX Duty = 5312%(X100), DQS PI = 26
7413 23:07:08.565869 [0] MIN Duty = 4907%(X100), DQS PI = 2
7414 23:07:08.568572 [0] AVG Duty = 5109%(X100)
7415 23:07:08.568996
7416 23:07:08.572086 CH1 DQM 0 Duty spec in!! Max-Min= 187%
7417 23:07:08.572516
7418 23:07:08.575420 CH1 DQM 1 Duty spec in!! Max-Min= 405%
7419 23:07:08.578430 [DutyScan_Calibration_Flow] ====Done====
7420 23:07:08.578916
7421 23:07:08.581817 [DutyScan_Calibration_Flow] k_type=2
7422 23:07:08.599099
7423 23:07:08.599527 ==DQ 0 ==
7424 23:07:08.602297 Final DQ duty delay cell = 0
7425 23:07:08.606145 [0] MAX Duty = 5093%(X100), DQS PI = 22
7426 23:07:08.608997 [0] MIN Duty = 4938%(X100), DQS PI = 0
7427 23:07:08.609468 [0] AVG Duty = 5015%(X100)
7428 23:07:08.609869
7429 23:07:08.612313 ==DQ 1 ==
7430 23:07:08.615744 Final DQ duty delay cell = 0
7431 23:07:08.618862 [0] MAX Duty = 5094%(X100), DQS PI = 34
7432 23:07:08.622155 [0] MIN Duty = 4813%(X100), DQS PI = 2
7433 23:07:08.622709 [0] AVG Duty = 4953%(X100)
7434 23:07:08.623156
7435 23:07:08.625907 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7436 23:07:08.629263
7437 23:07:08.632360 CH1 DQ 1 Duty spec in!! Max-Min= 281%
7438 23:07:08.635810 [DutyScan_Calibration_Flow] ====Done====
7439 23:07:08.638882 nWR fixed to 30
7440 23:07:08.639375 [ModeRegInit_LP4] CH0 RK0
7441 23:07:08.642290 [ModeRegInit_LP4] CH0 RK1
7442 23:07:08.645747 [ModeRegInit_LP4] CH1 RK0
7443 23:07:08.648576 [ModeRegInit_LP4] CH1 RK1
7444 23:07:08.649103 match AC timing 5
7445 23:07:08.651995 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7446 23:07:08.658798 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7447 23:07:08.662294 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7448 23:07:08.668616 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7449 23:07:08.671942 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7450 23:07:08.672367 [MiockJmeterHQA]
7451 23:07:08.672750
7452 23:07:08.675149 [DramcMiockJmeter] u1RxGatingPI = 0
7453 23:07:08.678561 0 : 4255, 4026
7454 23:07:08.679011 4 : 4252, 4027
7455 23:07:08.679353 8 : 4253, 4026
7456 23:07:08.682117 12 : 4253, 4026
7457 23:07:08.682609 16 : 4252, 4027
7458 23:07:08.685143 20 : 4252, 4027
7459 23:07:08.685573 24 : 4255, 4029
7460 23:07:08.688442 28 : 4363, 4138
7461 23:07:08.688905 32 : 4252, 4027
7462 23:07:08.691916 36 : 4252, 4027
7463 23:07:08.692346 40 : 4253, 4026
7464 23:07:08.692689 44 : 4255, 4030
7465 23:07:08.695207 48 : 4252, 4027
7466 23:07:08.695676 52 : 4363, 4137
7467 23:07:08.698678 56 : 4363, 4137
7468 23:07:08.699107 60 : 4250, 4027
7469 23:07:08.701745 64 : 4253, 4026
7470 23:07:08.702274 68 : 4252, 4027
7471 23:07:08.705149 72 : 4252, 4027
7472 23:07:08.705619 76 : 4253, 4029
7473 23:07:08.705964 80 : 4360, 4137
7474 23:07:08.708618 84 : 4250, 4026
7475 23:07:08.709075 88 : 4250, 3670
7476 23:07:08.711760 92 : 4250, 0
7477 23:07:08.712212 96 : 4361, 0
7478 23:07:08.712562 100 : 4361, 0
7479 23:07:08.715050 104 : 4363, 0
7480 23:07:08.715510 108 : 4250, 0
7481 23:07:08.718315 112 : 4250, 0
7482 23:07:08.718790 116 : 4250, 0
7483 23:07:08.719165 120 : 4252, 0
7484 23:07:08.721768 124 : 4361, 0
7485 23:07:08.722244 128 : 4361, 0
7486 23:07:08.725449 132 : 4250, 0
7487 23:07:08.725914 136 : 4250, 0
7488 23:07:08.726264 140 : 4250, 0
7489 23:07:08.728460 144 : 4252, 0
7490 23:07:08.728891 148 : 4250, 0
7491 23:07:08.731842 152 : 4250, 0
7492 23:07:08.732275 156 : 4253, 0
7493 23:07:08.732614 160 : 4250, 0
7494 23:07:08.735257 164 : 4250, 0
7495 23:07:08.735692 168 : 4253, 0
7496 23:07:08.736088 172 : 4360, 0
7497 23:07:08.738437 176 : 4361, 0
7498 23:07:08.738869 180 : 4363, 0
7499 23:07:08.741773 184 : 4250, 0
7500 23:07:08.742202 188 : 4250, 0
7501 23:07:08.742614 192 : 4250, 0
7502 23:07:08.744801 196 : 4250, 0
7503 23:07:08.745231 200 : 4250, 6
7504 23:07:08.748450 204 : 4250, 2470
7505 23:07:08.748903 208 : 4250, 4027
7506 23:07:08.751790 212 : 4360, 4137
7507 23:07:08.752244 216 : 4250, 4027
7508 23:07:08.754792 220 : 4250, 4027
7509 23:07:08.755251 224 : 4361, 4137
7510 23:07:08.755592 228 : 4250, 4027
7511 23:07:08.758210 232 : 4250, 4026
7512 23:07:08.758690 236 : 4364, 4140
7513 23:07:08.761901 240 : 4250, 4026
7514 23:07:08.762348 244 : 4250, 4027
7515 23:07:08.764884 248 : 4250, 4027
7516 23:07:08.765315 252 : 4253, 4029
7517 23:07:08.768057 256 : 4250, 4027
7518 23:07:08.768521 260 : 4250, 4027
7519 23:07:08.771575 264 : 4360, 4137
7520 23:07:08.772031 268 : 4249, 4027
7521 23:07:08.774798 272 : 4250, 4027
7522 23:07:08.775251 276 : 4361, 4138
7523 23:07:08.775604 280 : 4252, 4027
7524 23:07:08.778144 284 : 4250, 4027
7525 23:07:08.778620 288 : 4364, 4140
7526 23:07:08.781658 292 : 4250, 4026
7527 23:07:08.782177 296 : 4250, 4027
7528 23:07:08.785151 300 : 4250, 4026
7529 23:07:08.785588 304 : 4253, 4029
7530 23:07:08.788015 308 : 4250, 4027
7531 23:07:08.788491 312 : 4250, 3925
7532 23:07:08.791676 316 : 4360, 2091
7533 23:07:08.792110
7534 23:07:08.792443 MIOCK jitter meter ch=0
7535 23:07:08.794901
7536 23:07:08.795356 1T = (316-92) = 224 dly cells
7537 23:07:08.801224 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7538 23:07:08.801674 ==
7539 23:07:08.804551 Dram Type= 6, Freq= 0, CH_0, rank 0
7540 23:07:08.807878 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7541 23:07:08.808481 ==
7542 23:07:08.814590 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7543 23:07:08.818040 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7544 23:07:08.824636 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7545 23:07:08.827790 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7546 23:07:08.837936 [CA 0] Center 42 (12~73) winsize 62
7547 23:07:08.841338 [CA 1] Center 43 (13~73) winsize 61
7548 23:07:08.844497 [CA 2] Center 38 (8~68) winsize 61
7549 23:07:08.847842 [CA 3] Center 37 (8~67) winsize 60
7550 23:07:08.851281 [CA 4] Center 36 (6~66) winsize 61
7551 23:07:08.854627 [CA 5] Center 35 (5~66) winsize 62
7552 23:07:08.855053
7553 23:07:08.857934 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7554 23:07:08.858359
7555 23:07:08.861233 [CATrainingPosCal] consider 1 rank data
7556 23:07:08.864266 u2DelayCellTimex100 = 290/100 ps
7557 23:07:08.867664 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7558 23:07:08.874380 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7559 23:07:08.877804 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7560 23:07:08.881268 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7561 23:07:08.884372 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7562 23:07:08.887691 CA5 delay=35 (5~66),Diff = 0 PI (0 cell)
7563 23:07:08.888306
7564 23:07:08.891153 CA PerBit enable=1, Macro0, CA PI delay=35
7565 23:07:08.891599
7566 23:07:08.894081 [CBTSetCACLKResult] CA Dly = 35
7567 23:07:08.897742 CS Dly: 9 (0~40)
7568 23:07:08.900903 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7569 23:07:08.904120 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7570 23:07:08.904553 ==
7571 23:07:08.907960 Dram Type= 6, Freq= 0, CH_0, rank 1
7572 23:07:08.911591 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7573 23:07:08.912133 ==
7574 23:07:08.917565 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7575 23:07:08.921217 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7576 23:07:08.927479 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7577 23:07:08.931044 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7578 23:07:08.941012 [CA 0] Center 43 (13~74) winsize 62
7579 23:07:08.944685 [CA 1] Center 43 (13~73) winsize 61
7580 23:07:08.947680 [CA 2] Center 38 (9~68) winsize 60
7581 23:07:08.951321 [CA 3] Center 38 (9~68) winsize 60
7582 23:07:08.954574 [CA 4] Center 37 (7~67) winsize 61
7583 23:07:08.957872 [CA 5] Center 36 (6~66) winsize 61
7584 23:07:08.958302
7585 23:07:08.961587 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7586 23:07:08.962020
7587 23:07:08.964465 [CATrainingPosCal] consider 2 rank data
7588 23:07:08.968083 u2DelayCellTimex100 = 290/100 ps
7589 23:07:08.971290 CA0 delay=43 (13~73),Diff = 7 PI (23 cell)
7590 23:07:08.977704 CA1 delay=43 (13~73),Diff = 7 PI (23 cell)
7591 23:07:08.981567 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
7592 23:07:08.984724 CA3 delay=38 (9~67),Diff = 2 PI (6 cell)
7593 23:07:08.987671 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7594 23:07:08.991209 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7595 23:07:08.991634
7596 23:07:08.994773 CA PerBit enable=1, Macro0, CA PI delay=36
7597 23:07:08.995197
7598 23:07:08.997926 [CBTSetCACLKResult] CA Dly = 36
7599 23:07:09.001236 CS Dly: 10 (0~43)
7600 23:07:09.004307 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7601 23:07:09.008067 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7602 23:07:09.008547
7603 23:07:09.011058 ----->DramcWriteLeveling(PI) begin...
7604 23:07:09.011492 ==
7605 23:07:09.014168 Dram Type= 6, Freq= 0, CH_0, rank 0
7606 23:07:09.020799 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7607 23:07:09.021294 ==
7608 23:07:09.021664 Write leveling (Byte 0): 36 => 36
7609 23:07:09.024361 Write leveling (Byte 1): 30 => 30
7610 23:07:09.027804 DramcWriteLeveling(PI) end<-----
7611 23:07:09.028283
7612 23:07:09.028632 ==
7613 23:07:09.031030 Dram Type= 6, Freq= 0, CH_0, rank 0
7614 23:07:09.037603 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7615 23:07:09.038032 ==
7616 23:07:09.040956 [Gating] SW mode calibration
7617 23:07:09.047476 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7618 23:07:09.050849 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7619 23:07:09.057408 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7620 23:07:09.060750 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7621 23:07:09.064292 1 4 8 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (1 1)
7622 23:07:09.070627 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7623 23:07:09.073773 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7624 23:07:09.076953 1 4 20 | B1->B0 | 3131 3434 | 0 1 | (1 1) (1 1)
7625 23:07:09.083768 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7626 23:07:09.087283 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7627 23:07:09.090369 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7628 23:07:09.097092 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7629 23:07:09.100311 1 5 8 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
7630 23:07:09.103751 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7631 23:07:09.110422 1 5 16 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
7632 23:07:09.113949 1 5 20 | B1->B0 | 2a2a 2323 | 0 0 | (0 1) (0 0)
7633 23:07:09.117363 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7634 23:07:09.120268 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7635 23:07:09.127332 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7636 23:07:09.130581 1 6 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
7637 23:07:09.133931 1 6 8 | B1->B0 | 2323 3c3c | 0 1 | (0 0) (1 1)
7638 23:07:09.140629 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7639 23:07:09.143744 1 6 16 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
7640 23:07:09.147160 1 6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7641 23:07:09.153812 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7642 23:07:09.157181 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7643 23:07:09.160342 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7644 23:07:09.167172 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7645 23:07:09.170445 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7646 23:07:09.173711 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7647 23:07:09.180646 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7648 23:07:09.183784 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7649 23:07:09.186944 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7650 23:07:09.193709 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7651 23:07:09.197019 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7652 23:07:09.200102 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7653 23:07:09.207067 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7654 23:07:09.210256 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7655 23:07:09.213644 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7656 23:07:09.220229 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7657 23:07:09.223602 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7658 23:07:09.227427 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7659 23:07:09.230497 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7660 23:07:09.236971 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7661 23:07:09.240237 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7662 23:07:09.243400 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7663 23:07:09.250186 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7664 23:07:09.253618 Total UI for P1: 0, mck2ui 16
7665 23:07:09.257282 best dqsien dly found for B0: ( 1, 9, 10)
7666 23:07:09.260422 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7667 23:07:09.263695 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7668 23:07:09.266915 Total UI for P1: 0, mck2ui 16
7669 23:07:09.270135 best dqsien dly found for B1: ( 1, 9, 18)
7670 23:07:09.273590 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7671 23:07:09.276398 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7672 23:07:09.276924
7673 23:07:09.283069 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7674 23:07:09.286818 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7675 23:07:09.289617 [Gating] SW calibration Done
7676 23:07:09.290060 ==
7677 23:07:09.293343 Dram Type= 6, Freq= 0, CH_0, rank 0
7678 23:07:09.296685 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7679 23:07:09.297114 ==
7680 23:07:09.297505 RX Vref Scan: 0
7681 23:07:09.299657
7682 23:07:09.300125 RX Vref 0 -> 0, step: 1
7683 23:07:09.300463
7684 23:07:09.303593 RX Delay 0 -> 252, step: 8
7685 23:07:09.306483 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7686 23:07:09.309979 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7687 23:07:09.316842 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7688 23:07:09.319996 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7689 23:07:09.322858 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7690 23:07:09.326334 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7691 23:07:09.329931 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7692 23:07:09.333389 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7693 23:07:09.339523 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7694 23:07:09.343029 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7695 23:07:09.346366 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7696 23:07:09.350061 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
7697 23:07:09.356070 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7698 23:07:09.359519 iDelay=200, Bit 13, Center 131 (88 ~ 175) 88
7699 23:07:09.362657 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7700 23:07:09.366021 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7701 23:07:09.366564 ==
7702 23:07:09.369478 Dram Type= 6, Freq= 0, CH_0, rank 0
7703 23:07:09.372614 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7704 23:07:09.376061 ==
7705 23:07:09.376487 DQS Delay:
7706 23:07:09.376821 DQS0 = 0, DQS1 = 0
7707 23:07:09.379494 DQM Delay:
7708 23:07:09.380033 DQM0 = 137, DQM1 = 127
7709 23:07:09.382731 DQ Delay:
7710 23:07:09.385904 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
7711 23:07:09.389146 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =147
7712 23:07:09.392621 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =127
7713 23:07:09.395888 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7714 23:07:09.396312
7715 23:07:09.396704
7716 23:07:09.397014 ==
7717 23:07:09.399539 Dram Type= 6, Freq= 0, CH_0, rank 0
7718 23:07:09.402814 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7719 23:07:09.403241 ==
7720 23:07:09.403578
7721 23:07:09.406086
7722 23:07:09.406602 TX Vref Scan disable
7723 23:07:09.409302 == TX Byte 0 ==
7724 23:07:09.412485 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7725 23:07:09.415987 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7726 23:07:09.419785 == TX Byte 1 ==
7727 23:07:09.422483 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7728 23:07:09.426359 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7729 23:07:09.426883 ==
7730 23:07:09.429829 Dram Type= 6, Freq= 0, CH_0, rank 0
7731 23:07:09.435954 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7732 23:07:09.436448 ==
7733 23:07:09.448085
7734 23:07:09.451406 TX Vref early break, caculate TX vref
7735 23:07:09.454545 TX Vref=16, minBit 12, minWin=22, winSum=380
7736 23:07:09.457641 TX Vref=18, minBit 1, minWin=23, winSum=390
7737 23:07:09.461041 TX Vref=20, minBit 12, minWin=23, winSum=400
7738 23:07:09.464463 TX Vref=22, minBit 2, minWin=24, winSum=406
7739 23:07:09.467865 TX Vref=24, minBit 6, minWin=25, winSum=418
7740 23:07:09.474511 TX Vref=26, minBit 0, minWin=25, winSum=424
7741 23:07:09.477918 TX Vref=28, minBit 0, minWin=25, winSum=424
7742 23:07:09.480942 TX Vref=30, minBit 0, minWin=25, winSum=419
7743 23:07:09.484516 TX Vref=32, minBit 2, minWin=24, winSum=410
7744 23:07:09.487610 TX Vref=34, minBit 1, minWin=24, winSum=395
7745 23:07:09.494460 [TxChooseVref] Worse bit 0, Min win 25, Win sum 424, Final Vref 26
7746 23:07:09.494937
7747 23:07:09.497745 Final TX Range 0 Vref 26
7748 23:07:09.498220
7749 23:07:09.498632 ==
7750 23:07:09.501341 Dram Type= 6, Freq= 0, CH_0, rank 0
7751 23:07:09.504189 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7752 23:07:09.504672 ==
7753 23:07:09.505051
7754 23:07:09.505398
7755 23:07:09.507917 TX Vref Scan disable
7756 23:07:09.514517 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7757 23:07:09.514990 == TX Byte 0 ==
7758 23:07:09.517698 u2DelayCellOfst[0]=13 cells (4 PI)
7759 23:07:09.520826 u2DelayCellOfst[1]=16 cells (5 PI)
7760 23:07:09.524136 u2DelayCellOfst[2]=10 cells (3 PI)
7761 23:07:09.527561 u2DelayCellOfst[3]=10 cells (3 PI)
7762 23:07:09.530831 u2DelayCellOfst[4]=6 cells (2 PI)
7763 23:07:09.534079 u2DelayCellOfst[5]=0 cells (0 PI)
7764 23:07:09.537902 u2DelayCellOfst[6]=16 cells (5 PI)
7765 23:07:09.540964 u2DelayCellOfst[7]=16 cells (5 PI)
7766 23:07:09.544014 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7767 23:07:09.547436 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7768 23:07:09.550885 == TX Byte 1 ==
7769 23:07:09.551418 u2DelayCellOfst[8]=0 cells (0 PI)
7770 23:07:09.553964 u2DelayCellOfst[9]=0 cells (0 PI)
7771 23:07:09.557396 u2DelayCellOfst[10]=6 cells (2 PI)
7772 23:07:09.560613 u2DelayCellOfst[11]=3 cells (1 PI)
7773 23:07:09.564194 u2DelayCellOfst[12]=13 cells (4 PI)
7774 23:07:09.567517 u2DelayCellOfst[13]=13 cells (4 PI)
7775 23:07:09.570626 u2DelayCellOfst[14]=13 cells (4 PI)
7776 23:07:09.573762 u2DelayCellOfst[15]=10 cells (3 PI)
7777 23:07:09.577526 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7778 23:07:09.584049 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7779 23:07:09.584566 DramC Write-DBI on
7780 23:07:09.584967 ==
7781 23:07:09.587473 Dram Type= 6, Freq= 0, CH_0, rank 0
7782 23:07:09.590637 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7783 23:07:09.594124 ==
7784 23:07:09.594654
7785 23:07:09.594998
7786 23:07:09.595334 TX Vref Scan disable
7787 23:07:09.597628 == TX Byte 0 ==
7788 23:07:09.601283 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7789 23:07:09.604112 == TX Byte 1 ==
7790 23:07:09.607484 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
7791 23:07:09.610787 DramC Write-DBI off
7792 23:07:09.611214
7793 23:07:09.611547 [DATLAT]
7794 23:07:09.611889 Freq=1600, CH0 RK0
7795 23:07:09.612199
7796 23:07:09.614096 DATLAT Default: 0xf
7797 23:07:09.614560 0, 0xFFFF, sum = 0
7798 23:07:09.617304 1, 0xFFFF, sum = 0
7799 23:07:09.620820 2, 0xFFFF, sum = 0
7800 23:07:09.621294 3, 0xFFFF, sum = 0
7801 23:07:09.623865 4, 0xFFFF, sum = 0
7802 23:07:09.624299 5, 0xFFFF, sum = 0
7803 23:07:09.627068 6, 0xFFFF, sum = 0
7804 23:07:09.627523 7, 0xFFFF, sum = 0
7805 23:07:09.630413 8, 0xFFFF, sum = 0
7806 23:07:09.630859 9, 0xFFFF, sum = 0
7807 23:07:09.633642 10, 0xFFFF, sum = 0
7808 23:07:09.634084 11, 0xFFFF, sum = 0
7809 23:07:09.637143 12, 0xFFFF, sum = 0
7810 23:07:09.637586 13, 0xFFFF, sum = 0
7811 23:07:09.641200 14, 0x0, sum = 1
7812 23:07:09.641643 15, 0x0, sum = 2
7813 23:07:09.643989 16, 0x0, sum = 3
7814 23:07:09.644432 17, 0x0, sum = 4
7815 23:07:09.647375 best_step = 15
7816 23:07:09.647810
7817 23:07:09.648246 ==
7818 23:07:09.650459 Dram Type= 6, Freq= 0, CH_0, rank 0
7819 23:07:09.653735 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7820 23:07:09.654172 ==
7821 23:07:09.657016 RX Vref Scan: 1
7822 23:07:09.657451
7823 23:07:09.657881 Set Vref Range= 24 -> 127
7824 23:07:09.658287
7825 23:07:09.660072 RX Vref 24 -> 127, step: 1
7826 23:07:09.660507
7827 23:07:09.663698 RX Delay 19 -> 252, step: 4
7828 23:07:09.664135
7829 23:07:09.667223 Set Vref, RX VrefLevel [Byte0]: 24
7830 23:07:09.670417 [Byte1]: 24
7831 23:07:09.670855
7832 23:07:09.673603 Set Vref, RX VrefLevel [Byte0]: 25
7833 23:07:09.677214 [Byte1]: 25
7834 23:07:09.677652
7835 23:07:09.680608 Set Vref, RX VrefLevel [Byte0]: 26
7836 23:07:09.683573 [Byte1]: 26
7837 23:07:09.687878
7838 23:07:09.688313 Set Vref, RX VrefLevel [Byte0]: 27
7839 23:07:09.691001 [Byte1]: 27
7840 23:07:09.695227
7841 23:07:09.695664 Set Vref, RX VrefLevel [Byte0]: 28
7842 23:07:09.698713 [Byte1]: 28
7843 23:07:09.702800
7844 23:07:09.703233 Set Vref, RX VrefLevel [Byte0]: 29
7845 23:07:09.706292 [Byte1]: 29
7846 23:07:09.710665
7847 23:07:09.711101 Set Vref, RX VrefLevel [Byte0]: 30
7848 23:07:09.713741 [Byte1]: 30
7849 23:07:09.717975
7850 23:07:09.718436 Set Vref, RX VrefLevel [Byte0]: 31
7851 23:07:09.721235 [Byte1]: 31
7852 23:07:09.725828
7853 23:07:09.726273 Set Vref, RX VrefLevel [Byte0]: 32
7854 23:07:09.729781 [Byte1]: 32
7855 23:07:09.733096
7856 23:07:09.733531 Set Vref, RX VrefLevel [Byte0]: 33
7857 23:07:09.736418 [Byte1]: 33
7858 23:07:09.741200
7859 23:07:09.741738 Set Vref, RX VrefLevel [Byte0]: 34
7860 23:07:09.743941 [Byte1]: 34
7861 23:07:09.748384
7862 23:07:09.748820 Set Vref, RX VrefLevel [Byte0]: 35
7863 23:07:09.751469 [Byte1]: 35
7864 23:07:09.755993
7865 23:07:09.756548 Set Vref, RX VrefLevel [Byte0]: 36
7866 23:07:09.759011 [Byte1]: 36
7867 23:07:09.763395
7868 23:07:09.763829 Set Vref, RX VrefLevel [Byte0]: 37
7869 23:07:09.766650 [Byte1]: 37
7870 23:07:09.771358
7871 23:07:09.771794 Set Vref, RX VrefLevel [Byte0]: 38
7872 23:07:09.774286 [Byte1]: 38
7873 23:07:09.778692
7874 23:07:09.779127 Set Vref, RX VrefLevel [Byte0]: 39
7875 23:07:09.781689 [Byte1]: 39
7876 23:07:09.786464
7877 23:07:09.786898 Set Vref, RX VrefLevel [Byte0]: 40
7878 23:07:09.789231 [Byte1]: 40
7879 23:07:09.793749
7880 23:07:09.794184 Set Vref, RX VrefLevel [Byte0]: 41
7881 23:07:09.796648 [Byte1]: 41
7882 23:07:09.801067
7883 23:07:09.801149 Set Vref, RX VrefLevel [Byte0]: 42
7884 23:07:09.804433 [Byte1]: 42
7885 23:07:09.808737
7886 23:07:09.808826 Set Vref, RX VrefLevel [Byte0]: 43
7887 23:07:09.811988 [Byte1]: 43
7888 23:07:09.816123
7889 23:07:09.816226 Set Vref, RX VrefLevel [Byte0]: 44
7890 23:07:09.819463 [Byte1]: 44
7891 23:07:09.823710
7892 23:07:09.823821 Set Vref, RX VrefLevel [Byte0]: 45
7893 23:07:09.826924 [Byte1]: 45
7894 23:07:09.831560
7895 23:07:09.831649 Set Vref, RX VrefLevel [Byte0]: 46
7896 23:07:09.834656 [Byte1]: 46
7897 23:07:09.838955
7898 23:07:09.839038 Set Vref, RX VrefLevel [Byte0]: 47
7899 23:07:09.841821 [Byte1]: 47
7900 23:07:09.846370
7901 23:07:09.846490 Set Vref, RX VrefLevel [Byte0]: 48
7902 23:07:09.849750 [Byte1]: 48
7903 23:07:09.853918
7904 23:07:09.854000 Set Vref, RX VrefLevel [Byte0]: 49
7905 23:07:09.857295 [Byte1]: 49
7906 23:07:09.861661
7907 23:07:09.861744 Set Vref, RX VrefLevel [Byte0]: 50
7908 23:07:09.864909 [Byte1]: 50
7909 23:07:09.868999
7910 23:07:09.869082 Set Vref, RX VrefLevel [Byte0]: 51
7911 23:07:09.872416 [Byte1]: 51
7912 23:07:09.876579
7913 23:07:09.876662 Set Vref, RX VrefLevel [Byte0]: 52
7914 23:07:09.879962 [Byte1]: 52
7915 23:07:09.884279
7916 23:07:09.884365 Set Vref, RX VrefLevel [Byte0]: 53
7917 23:07:09.887863 [Byte1]: 53
7918 23:07:09.891827
7919 23:07:09.891910 Set Vref, RX VrefLevel [Byte0]: 54
7920 23:07:09.897990 [Byte1]: 54
7921 23:07:09.898073
7922 23:07:09.901627 Set Vref, RX VrefLevel [Byte0]: 55
7923 23:07:09.905257 [Byte1]: 55
7924 23:07:09.905340
7925 23:07:09.908162 Set Vref, RX VrefLevel [Byte0]: 56
7926 23:07:09.911477 [Byte1]: 56
7927 23:07:09.911560
7928 23:07:09.914867 Set Vref, RX VrefLevel [Byte0]: 57
7929 23:07:09.918073 [Byte1]: 57
7930 23:07:09.922301
7931 23:07:09.922446 Set Vref, RX VrefLevel [Byte0]: 58
7932 23:07:09.925554 [Byte1]: 58
7933 23:07:09.929609
7934 23:07:09.929692 Set Vref, RX VrefLevel [Byte0]: 59
7935 23:07:09.933344 [Byte1]: 59
7936 23:07:09.937335
7937 23:07:09.937418 Set Vref, RX VrefLevel [Byte0]: 60
7938 23:07:09.941182 [Byte1]: 60
7939 23:07:09.944751
7940 23:07:09.944834 Set Vref, RX VrefLevel [Byte0]: 61
7941 23:07:09.947929 [Byte1]: 61
7942 23:07:09.952408
7943 23:07:09.952491 Set Vref, RX VrefLevel [Byte0]: 62
7944 23:07:09.955537 [Byte1]: 62
7945 23:07:09.960066
7946 23:07:09.960149 Set Vref, RX VrefLevel [Byte0]: 63
7947 23:07:09.963069 [Byte1]: 63
7948 23:07:09.967845
7949 23:07:09.967928 Set Vref, RX VrefLevel [Byte0]: 64
7950 23:07:09.970906 [Byte1]: 64
7951 23:07:09.975438
7952 23:07:09.975521 Set Vref, RX VrefLevel [Byte0]: 65
7953 23:07:09.978911 [Byte1]: 65
7954 23:07:09.982728
7955 23:07:09.982810 Set Vref, RX VrefLevel [Byte0]: 66
7956 23:07:09.985980 [Byte1]: 66
7957 23:07:09.990057
7958 23:07:09.990140 Set Vref, RX VrefLevel [Byte0]: 67
7959 23:07:09.993648 [Byte1]: 67
7960 23:07:09.997728
7961 23:07:09.997811 Set Vref, RX VrefLevel [Byte0]: 68
7962 23:07:10.001157 [Byte1]: 68
7963 23:07:10.005517
7964 23:07:10.005599 Set Vref, RX VrefLevel [Byte0]: 69
7965 23:07:10.008730 [Byte1]: 69
7966 23:07:10.013395
7967 23:07:10.013477 Set Vref, RX VrefLevel [Byte0]: 70
7968 23:07:10.016409 [Byte1]: 70
7969 23:07:10.020898
7970 23:07:10.020981 Set Vref, RX VrefLevel [Byte0]: 71
7971 23:07:10.023729 [Byte1]: 71
7972 23:07:10.028008
7973 23:07:10.028091 Set Vref, RX VrefLevel [Byte0]: 72
7974 23:07:10.031349 [Byte1]: 72
7975 23:07:10.035829
7976 23:07:10.035912 Set Vref, RX VrefLevel [Byte0]: 73
7977 23:07:10.039090 [Byte1]: 73
7978 23:07:10.043283
7979 23:07:10.043366 Set Vref, RX VrefLevel [Byte0]: 74
7980 23:07:10.046590 [Byte1]: 74
7981 23:07:10.050807
7982 23:07:10.050893 Set Vref, RX VrefLevel [Byte0]: 75
7983 23:07:10.054086 [Byte1]: 75
7984 23:07:10.058267
7985 23:07:10.058376 Set Vref, RX VrefLevel [Byte0]: 76
7986 23:07:10.061488 [Byte1]: 76
7987 23:07:10.065863
7988 23:07:10.065945 Set Vref, RX VrefLevel [Byte0]: 77
7989 23:07:10.069254 [Byte1]: 77
7990 23:07:10.073645
7991 23:07:10.073728 Set Vref, RX VrefLevel [Byte0]: 78
7992 23:07:10.076681 [Byte1]: 78
7993 23:07:10.081082
7994 23:07:10.081165 Set Vref, RX VrefLevel [Byte0]: 79
7995 23:07:10.084358 [Byte1]: 79
7996 23:07:10.088612
7997 23:07:10.088694 Set Vref, RX VrefLevel [Byte0]: 80
7998 23:07:10.091828 [Byte1]: 80
7999 23:07:10.096204
8000 23:07:10.096286 Set Vref, RX VrefLevel [Byte0]: 81
8001 23:07:10.099480 [Byte1]: 81
8002 23:07:10.103679
8003 23:07:10.103762 Set Vref, RX VrefLevel [Byte0]: 82
8004 23:07:10.107105 [Byte1]: 82
8005 23:07:10.111410
8006 23:07:10.111493 Set Vref, RX VrefLevel [Byte0]: 83
8007 23:07:10.114850 [Byte1]: 83
8008 23:07:10.119042
8009 23:07:10.119125 Set Vref, RX VrefLevel [Byte0]: 84
8010 23:07:10.122327 [Byte1]: 84
8011 23:07:10.126957
8012 23:07:10.127040 Final RX Vref Byte 0 = 61 to rank0
8013 23:07:10.129755 Final RX Vref Byte 1 = 62 to rank0
8014 23:07:10.132988 Final RX Vref Byte 0 = 61 to rank1
8015 23:07:10.136503 Final RX Vref Byte 1 = 62 to rank1==
8016 23:07:10.140111 Dram Type= 6, Freq= 0, CH_0, rank 0
8017 23:07:10.146343 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8018 23:07:10.146444 ==
8019 23:07:10.146510 DQS Delay:
8020 23:07:10.146572 DQS0 = 0, DQS1 = 0
8021 23:07:10.150280 DQM Delay:
8022 23:07:10.150393 DQM0 = 136, DQM1 = 125
8023 23:07:10.154063 DQ Delay:
8024 23:07:10.156404 DQ0 =136, DQ1 =138, DQ2 =132, DQ3 =132
8025 23:07:10.159648 DQ4 =140, DQ5 =126, DQ6 =142, DQ7 =144
8026 23:07:10.162919 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =120
8027 23:07:10.166586 DQ12 =128, DQ13 =128, DQ14 =136, DQ15 =134
8028 23:07:10.166669
8029 23:07:10.166734
8030 23:07:10.166795
8031 23:07:10.169824 [DramC_TX_OE_Calibration] TA2
8032 23:07:10.173030 Original DQ_B0 (3 6) =30, OEN = 27
8033 23:07:10.176295 Original DQ_B1 (3 6) =30, OEN = 27
8034 23:07:10.179621 24, 0x0, End_B0=24 End_B1=24
8035 23:07:10.179705 25, 0x0, End_B0=25 End_B1=25
8036 23:07:10.183392 26, 0x0, End_B0=26 End_B1=26
8037 23:07:10.186549 27, 0x0, End_B0=27 End_B1=27
8038 23:07:10.189806 28, 0x0, End_B0=28 End_B1=28
8039 23:07:10.189890 29, 0x0, End_B0=29 End_B1=29
8040 23:07:10.192980 30, 0x0, End_B0=30 End_B1=30
8041 23:07:10.196554 31, 0x4141, End_B0=30 End_B1=30
8042 23:07:10.199783 Byte0 end_step=30 best_step=27
8043 23:07:10.203064 Byte1 end_step=30 best_step=27
8044 23:07:10.206355 Byte0 TX OE(2T, 0.5T) = (3, 3)
8045 23:07:10.209528 Byte1 TX OE(2T, 0.5T) = (3, 3)
8046 23:07:10.209613
8047 23:07:10.209699
8048 23:07:10.215938 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f1d, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
8049 23:07:10.219316 CH0 RK0: MR19=303, MR18=1F1D
8050 23:07:10.226123 CH0_RK0: MR19=0x303, MR18=0x1F1D, DQSOSC=394, MR23=63, INC=23, DEC=15
8051 23:07:10.226210
8052 23:07:10.229300 ----->DramcWriteLeveling(PI) begin...
8053 23:07:10.229386 ==
8054 23:07:10.232845 Dram Type= 6, Freq= 0, CH_0, rank 1
8055 23:07:10.235897 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8056 23:07:10.235983 ==
8057 23:07:10.239493 Write leveling (Byte 0): 38 => 38
8058 23:07:10.242607 Write leveling (Byte 1): 28 => 28
8059 23:07:10.246069 DramcWriteLeveling(PI) end<-----
8060 23:07:10.246154
8061 23:07:10.246238 ==
8062 23:07:10.249622 Dram Type= 6, Freq= 0, CH_0, rank 1
8063 23:07:10.252536 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8064 23:07:10.252621 ==
8065 23:07:10.255862 [Gating] SW mode calibration
8066 23:07:10.262525 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8067 23:07:10.269487 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8068 23:07:10.272312 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8069 23:07:10.278988 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8070 23:07:10.282216 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8071 23:07:10.285685 1 4 12 | B1->B0 | 2828 3434 | 0 0 | (0 0) (0 0)
8072 23:07:10.289549 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8073 23:07:10.295614 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8074 23:07:10.298851 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8075 23:07:10.302251 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8076 23:07:10.309292 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8077 23:07:10.312068 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8078 23:07:10.315493 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8079 23:07:10.322232 1 5 12 | B1->B0 | 3434 2828 | 1 0 | (1 0) (0 1)
8080 23:07:10.325330 1 5 16 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
8081 23:07:10.328704 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8082 23:07:10.335347 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8083 23:07:10.338865 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8084 23:07:10.342237 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8085 23:07:10.349034 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8086 23:07:10.352562 1 6 8 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
8087 23:07:10.355954 1 6 12 | B1->B0 | 2b2a 4444 | 1 1 | (0 0) (0 0)
8088 23:07:10.362257 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8089 23:07:10.365971 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8090 23:07:10.368609 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8091 23:07:10.375396 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8092 23:07:10.378877 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8093 23:07:10.381974 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8094 23:07:10.389014 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8095 23:07:10.392257 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8096 23:07:10.395502 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8097 23:07:10.401966 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8098 23:07:10.405391 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8099 23:07:10.409025 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8100 23:07:10.415151 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8101 23:07:10.418483 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8102 23:07:10.422079 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8103 23:07:10.425382 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8104 23:07:10.431976 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8105 23:07:10.435216 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8106 23:07:10.438582 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8107 23:07:10.445461 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8108 23:07:10.448660 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8109 23:07:10.452087 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8110 23:07:10.458772 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8111 23:07:10.461783 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8112 23:07:10.465537 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8113 23:07:10.468664 Total UI for P1: 0, mck2ui 16
8114 23:07:10.471665 best dqsien dly found for B0: ( 1, 9, 10)
8115 23:07:10.478300 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8116 23:07:10.478413 Total UI for P1: 0, mck2ui 16
8117 23:07:10.485090 best dqsien dly found for B1: ( 1, 9, 14)
8118 23:07:10.488310 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8119 23:07:10.491667 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8120 23:07:10.491762
8121 23:07:10.495262 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8122 23:07:10.498227 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8123 23:07:10.502060 [Gating] SW calibration Done
8124 23:07:10.502172 ==
8125 23:07:10.504956 Dram Type= 6, Freq= 0, CH_0, rank 1
8126 23:07:10.508230 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8127 23:07:10.508353 ==
8128 23:07:10.512017 RX Vref Scan: 0
8129 23:07:10.512152
8130 23:07:10.512258 RX Vref 0 -> 0, step: 1
8131 23:07:10.512357
8132 23:07:10.515193 RX Delay 0 -> 252, step: 8
8133 23:07:10.518395 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8134 23:07:10.525359 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8135 23:07:10.528623 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8136 23:07:10.531982 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8137 23:07:10.535507 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8138 23:07:10.538512 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8139 23:07:10.545218 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8140 23:07:10.549071 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8141 23:07:10.552425 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8142 23:07:10.555741 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8143 23:07:10.558494 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8144 23:07:10.565244 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8145 23:07:10.569098 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
8146 23:07:10.571715 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8147 23:07:10.575031 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8148 23:07:10.578561 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8149 23:07:10.581991 ==
8150 23:07:10.585499 Dram Type= 6, Freq= 0, CH_0, rank 1
8151 23:07:10.588312 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8152 23:07:10.588796 ==
8153 23:07:10.589199 DQS Delay:
8154 23:07:10.592190 DQS0 = 0, DQS1 = 0
8155 23:07:10.592771 DQM Delay:
8156 23:07:10.594967 DQM0 = 135, DQM1 = 125
8157 23:07:10.595445 DQ Delay:
8158 23:07:10.598156 DQ0 =135, DQ1 =135, DQ2 =135, DQ3 =131
8159 23:07:10.601490 DQ4 =135, DQ5 =127, DQ6 =143, DQ7 =143
8160 23:07:10.605355 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =123
8161 23:07:10.608427 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
8162 23:07:10.608905
8163 23:07:10.609281
8164 23:07:10.609891 ==
8165 23:07:10.611740 Dram Type= 6, Freq= 0, CH_0, rank 1
8166 23:07:10.618430 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8167 23:07:10.618915 ==
8168 23:07:10.619293
8169 23:07:10.619665
8170 23:07:10.620000 TX Vref Scan disable
8171 23:07:10.622235 == TX Byte 0 ==
8172 23:07:10.625509 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
8173 23:07:10.631867 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8174 23:07:10.632343 == TX Byte 1 ==
8175 23:07:10.635923 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8176 23:07:10.642187 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8177 23:07:10.642801 ==
8178 23:07:10.645390 Dram Type= 6, Freq= 0, CH_0, rank 1
8179 23:07:10.648811 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8180 23:07:10.649385 ==
8181 23:07:10.662435
8182 23:07:10.665819 TX Vref early break, caculate TX vref
8183 23:07:10.668591 TX Vref=16, minBit 0, minWin=23, winSum=390
8184 23:07:10.672253 TX Vref=18, minBit 0, minWin=23, winSum=397
8185 23:07:10.675765 TX Vref=20, minBit 8, minWin=24, winSum=407
8186 23:07:10.678913 TX Vref=22, minBit 0, minWin=25, winSum=411
8187 23:07:10.682482 TX Vref=24, minBit 8, minWin=25, winSum=420
8188 23:07:10.688857 TX Vref=26, minBit 0, minWin=26, winSum=426
8189 23:07:10.692400 TX Vref=28, minBit 0, minWin=26, winSum=429
8190 23:07:10.695647 TX Vref=30, minBit 8, minWin=25, winSum=422
8191 23:07:10.698846 TX Vref=32, minBit 0, minWin=25, winSum=413
8192 23:07:10.702266 TX Vref=34, minBit 2, minWin=24, winSum=401
8193 23:07:10.708514 [TxChooseVref] Worse bit 0, Min win 26, Win sum 429, Final Vref 28
8194 23:07:10.709117
8195 23:07:10.711986 Final TX Range 0 Vref 28
8196 23:07:10.712470
8197 23:07:10.712835 ==
8198 23:07:10.715205 Dram Type= 6, Freq= 0, CH_0, rank 1
8199 23:07:10.718606 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8200 23:07:10.719078 ==
8201 23:07:10.719448
8202 23:07:10.719788
8203 23:07:10.722111 TX Vref Scan disable
8204 23:07:10.728655 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8205 23:07:10.729232 == TX Byte 0 ==
8206 23:07:10.731829 u2DelayCellOfst[0]=10 cells (3 PI)
8207 23:07:10.735335 u2DelayCellOfst[1]=16 cells (5 PI)
8208 23:07:10.739130 u2DelayCellOfst[2]=10 cells (3 PI)
8209 23:07:10.742213 u2DelayCellOfst[3]=10 cells (3 PI)
8210 23:07:10.745547 u2DelayCellOfst[4]=6 cells (2 PI)
8211 23:07:10.748752 u2DelayCellOfst[5]=0 cells (0 PI)
8212 23:07:10.751776 u2DelayCellOfst[6]=16 cells (5 PI)
8213 23:07:10.755298 u2DelayCellOfst[7]=16 cells (5 PI)
8214 23:07:10.758731 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8215 23:07:10.762099 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8216 23:07:10.765418 == TX Byte 1 ==
8217 23:07:10.765990 u2DelayCellOfst[8]=3 cells (1 PI)
8218 23:07:10.768524 u2DelayCellOfst[9]=0 cells (0 PI)
8219 23:07:10.772328 u2DelayCellOfst[10]=10 cells (3 PI)
8220 23:07:10.775223 u2DelayCellOfst[11]=3 cells (1 PI)
8221 23:07:10.778806 u2DelayCellOfst[12]=13 cells (4 PI)
8222 23:07:10.781683 u2DelayCellOfst[13]=10 cells (3 PI)
8223 23:07:10.784784 u2DelayCellOfst[14]=13 cells (4 PI)
8224 23:07:10.788679 u2DelayCellOfst[15]=10 cells (3 PI)
8225 23:07:10.791897 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8226 23:07:10.798402 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8227 23:07:10.798981 DramC Write-DBI on
8228 23:07:10.799356 ==
8229 23:07:10.801752 Dram Type= 6, Freq= 0, CH_0, rank 1
8230 23:07:10.805057 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8231 23:07:10.808071 ==
8232 23:07:10.808565
8233 23:07:10.808942
8234 23:07:10.809286 TX Vref Scan disable
8235 23:07:10.811908 == TX Byte 0 ==
8236 23:07:10.815095 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8237 23:07:10.818491 == TX Byte 1 ==
8238 23:07:10.821622 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8239 23:07:10.824934 DramC Write-DBI off
8240 23:07:10.825422
8241 23:07:10.825787 [DATLAT]
8242 23:07:10.826152 Freq=1600, CH0 RK1
8243 23:07:10.826547
8244 23:07:10.828426 DATLAT Default: 0xf
8245 23:07:10.828895 0, 0xFFFF, sum = 0
8246 23:07:10.831928 1, 0xFFFF, sum = 0
8247 23:07:10.834994 2, 0xFFFF, sum = 0
8248 23:07:10.835618 3, 0xFFFF, sum = 0
8249 23:07:10.838528 4, 0xFFFF, sum = 0
8250 23:07:10.839005 5, 0xFFFF, sum = 0
8251 23:07:10.841680 6, 0xFFFF, sum = 0
8252 23:07:10.842257 7, 0xFFFF, sum = 0
8253 23:07:10.845297 8, 0xFFFF, sum = 0
8254 23:07:10.845973 9, 0xFFFF, sum = 0
8255 23:07:10.848177 10, 0xFFFF, sum = 0
8256 23:07:10.848679 11, 0xFFFF, sum = 0
8257 23:07:10.852090 12, 0xFFFF, sum = 0
8258 23:07:10.852696 13, 0xFFFF, sum = 0
8259 23:07:10.854869 14, 0x0, sum = 1
8260 23:07:10.855345 15, 0x0, sum = 2
8261 23:07:10.858646 16, 0x0, sum = 3
8262 23:07:10.859225 17, 0x0, sum = 4
8263 23:07:10.861689 best_step = 15
8264 23:07:10.862257
8265 23:07:10.862665 ==
8266 23:07:10.864916 Dram Type= 6, Freq= 0, CH_0, rank 1
8267 23:07:10.868491 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8268 23:07:10.869165 ==
8269 23:07:10.871568 RX Vref Scan: 0
8270 23:07:10.872038
8271 23:07:10.872474 RX Vref 0 -> 0, step: 1
8272 23:07:10.872823
8273 23:07:10.874537 RX Delay 11 -> 252, step: 4
8274 23:07:10.877977 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8275 23:07:10.885034 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8276 23:07:10.888658 iDelay=191, Bit 2, Center 130 (83 ~ 178) 96
8277 23:07:10.891627 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8278 23:07:10.895132 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8279 23:07:10.897898 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8280 23:07:10.904922 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8281 23:07:10.907916 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8282 23:07:10.911494 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8283 23:07:10.914631 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8284 23:07:10.917851 iDelay=191, Bit 10, Center 124 (75 ~ 174) 100
8285 23:07:10.924463 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8286 23:07:10.928013 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8287 23:07:10.931479 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8288 23:07:10.934954 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8289 23:07:10.938053 iDelay=191, Bit 15, Center 130 (79 ~ 182) 104
8290 23:07:10.941341 ==
8291 23:07:10.944547 Dram Type= 6, Freq= 0, CH_0, rank 1
8292 23:07:10.947849 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8293 23:07:10.948347 ==
8294 23:07:10.948719 DQS Delay:
8295 23:07:10.951505 DQS0 = 0, DQS1 = 0
8296 23:07:10.952213 DQM Delay:
8297 23:07:10.954966 DQM0 = 133, DQM1 = 123
8298 23:07:10.955439 DQ Delay:
8299 23:07:10.957775 DQ0 =132, DQ1 =136, DQ2 =130, DQ3 =130
8300 23:07:10.961195 DQ4 =136, DQ5 =124, DQ6 =140, DQ7 =140
8301 23:07:10.964684 DQ8 =116, DQ9 =110, DQ10 =124, DQ11 =120
8302 23:07:10.968125 DQ12 =126, DQ13 =128, DQ14 =132, DQ15 =130
8303 23:07:10.968809
8304 23:07:10.969420
8305 23:07:10.969940
8306 23:07:10.971177 [DramC_TX_OE_Calibration] TA2
8307 23:07:10.974890 Original DQ_B0 (3 6) =30, OEN = 27
8308 23:07:10.978138 Original DQ_B1 (3 6) =30, OEN = 27
8309 23:07:10.981290 24, 0x0, End_B0=24 End_B1=24
8310 23:07:10.984841 25, 0x0, End_B0=25 End_B1=25
8311 23:07:10.985424 26, 0x0, End_B0=26 End_B1=26
8312 23:07:10.988366 27, 0x0, End_B0=27 End_B1=27
8313 23:07:10.991224 28, 0x0, End_B0=28 End_B1=28
8314 23:07:10.994552 29, 0x0, End_B0=29 End_B1=29
8315 23:07:10.997726 30, 0x0, End_B0=30 End_B1=30
8316 23:07:10.998305 31, 0x5151, End_B0=30 End_B1=30
8317 23:07:11.000995 Byte0 end_step=30 best_step=27
8318 23:07:11.004500 Byte1 end_step=30 best_step=27
8319 23:07:11.007620 Byte0 TX OE(2T, 0.5T) = (3, 3)
8320 23:07:11.010904 Byte1 TX OE(2T, 0.5T) = (3, 3)
8321 23:07:11.011376
8322 23:07:11.011745
8323 23:07:11.017734 [DQSOSCAuto] RK1, (LSB)MR18= 0x200d, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 393 ps
8324 23:07:11.020910 CH0 RK1: MR19=303, MR18=200D
8325 23:07:11.027261 CH0_RK1: MR19=0x303, MR18=0x200D, DQSOSC=393, MR23=63, INC=23, DEC=15
8326 23:07:11.030748 [RxdqsGatingPostProcess] freq 1600
8327 23:07:11.037461 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8328 23:07:11.037932 best DQS0 dly(2T, 0.5T) = (1, 1)
8329 23:07:11.041094 best DQS1 dly(2T, 0.5T) = (1, 1)
8330 23:07:11.044207 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8331 23:07:11.047821 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8332 23:07:11.050508 best DQS0 dly(2T, 0.5T) = (1, 1)
8333 23:07:11.054518 best DQS1 dly(2T, 0.5T) = (1, 1)
8334 23:07:11.057201 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8335 23:07:11.060561 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8336 23:07:11.064364 Pre-setting of DQS Precalculation
8337 23:07:11.067308 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8338 23:07:11.067783 ==
8339 23:07:11.070747 Dram Type= 6, Freq= 0, CH_1, rank 0
8340 23:07:11.077357 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8341 23:07:11.077829 ==
8342 23:07:11.080637 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8343 23:07:11.087256 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8344 23:07:11.090501 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8345 23:07:11.097664 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8346 23:07:11.104766 [CA 0] Center 41 (12~71) winsize 60
8347 23:07:11.108106 [CA 1] Center 41 (11~72) winsize 62
8348 23:07:11.111502 [CA 2] Center 38 (9~67) winsize 59
8349 23:07:11.114959 [CA 3] Center 36 (7~66) winsize 60
8350 23:07:11.118522 [CA 4] Center 37 (7~68) winsize 62
8351 23:07:11.121384 [CA 5] Center 36 (7~66) winsize 60
8352 23:07:11.121854
8353 23:07:11.124930 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8354 23:07:11.125418
8355 23:07:11.128506 [CATrainingPosCal] consider 1 rank data
8356 23:07:11.131547 u2DelayCellTimex100 = 290/100 ps
8357 23:07:11.134822 CA0 delay=41 (12~71),Diff = 5 PI (16 cell)
8358 23:07:11.141600 CA1 delay=41 (11~72),Diff = 5 PI (16 cell)
8359 23:07:11.144656 CA2 delay=38 (9~67),Diff = 2 PI (6 cell)
8360 23:07:11.148305 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8361 23:07:11.151398 CA4 delay=37 (7~68),Diff = 1 PI (3 cell)
8362 23:07:11.154710 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8363 23:07:11.155252
8364 23:07:11.158080 CA PerBit enable=1, Macro0, CA PI delay=36
8365 23:07:11.158568
8366 23:07:11.161333 [CBTSetCACLKResult] CA Dly = 36
8367 23:07:11.161898 CS Dly: 9 (0~40)
8368 23:07:11.168278 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8369 23:07:11.171598 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8370 23:07:11.172086 ==
8371 23:07:11.174695 Dram Type= 6, Freq= 0, CH_1, rank 1
8372 23:07:11.178007 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8373 23:07:11.178512 ==
8374 23:07:11.184619 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8375 23:07:11.188251 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8376 23:07:11.194854 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8377 23:07:11.197997 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8378 23:07:11.207727 [CA 0] Center 43 (14~73) winsize 60
8379 23:07:11.211285 [CA 1] Center 43 (14~73) winsize 60
8380 23:07:11.214715 [CA 2] Center 38 (9~68) winsize 60
8381 23:07:11.218130 [CA 3] Center 38 (9~67) winsize 59
8382 23:07:11.221488 [CA 4] Center 38 (9~68) winsize 60
8383 23:07:11.224813 [CA 5] Center 37 (8~67) winsize 60
8384 23:07:11.225385
8385 23:07:11.228005 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8386 23:07:11.228467
8387 23:07:11.231243 [CATrainingPosCal] consider 2 rank data
8388 23:07:11.235022 u2DelayCellTimex100 = 290/100 ps
8389 23:07:11.237837 CA0 delay=42 (14~71),Diff = 5 PI (16 cell)
8390 23:07:11.244904 CA1 delay=43 (14~72),Diff = 6 PI (20 cell)
8391 23:07:11.248047 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8392 23:07:11.251323 CA3 delay=37 (9~66),Diff = 0 PI (0 cell)
8393 23:07:11.254687 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8394 23:07:11.257730 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8395 23:07:11.258230
8396 23:07:11.261333 CA PerBit enable=1, Macro0, CA PI delay=37
8397 23:07:11.261829
8398 23:07:11.264654 [CBTSetCACLKResult] CA Dly = 37
8399 23:07:11.265226 CS Dly: 10 (0~42)
8400 23:07:11.271377 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8401 23:07:11.274411 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8402 23:07:11.274934
8403 23:07:11.277863 ----->DramcWriteLeveling(PI) begin...
8404 23:07:11.278374 ==
8405 23:07:11.281385 Dram Type= 6, Freq= 0, CH_1, rank 0
8406 23:07:11.284335 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8407 23:07:11.287884 ==
8408 23:07:11.288343 Write leveling (Byte 0): 25 => 25
8409 23:07:11.291071 Write leveling (Byte 1): 28 => 28
8410 23:07:11.294475 DramcWriteLeveling(PI) end<-----
8411 23:07:11.295068
8412 23:07:11.295440 ==
8413 23:07:11.297715 Dram Type= 6, Freq= 0, CH_1, rank 0
8414 23:07:11.304525 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8415 23:07:11.305113 ==
8416 23:07:11.307398 [Gating] SW mode calibration
8417 23:07:11.314112 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8418 23:07:11.317423 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8419 23:07:11.324462 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8420 23:07:11.327211 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8421 23:07:11.331551 1 4 8 | B1->B0 | 2d2d 3333 | 0 0 | (0 0) (0 0)
8422 23:07:11.337260 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8423 23:07:11.340513 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8424 23:07:11.344107 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8425 23:07:11.350498 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8426 23:07:11.353660 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8427 23:07:11.357163 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8428 23:07:11.360483 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8429 23:07:11.366994 1 5 8 | B1->B0 | 2f2f 2e2e | 0 0 | (0 0) (1 0)
8430 23:07:11.370464 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8431 23:07:11.373724 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8432 23:07:11.380162 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8433 23:07:11.383806 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8434 23:07:11.386810 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8435 23:07:11.393823 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8436 23:07:11.397082 1 6 4 | B1->B0 | 2424 2626 | 0 0 | (0 0) (0 0)
8437 23:07:11.400272 1 6 8 | B1->B0 | 4444 4343 | 0 1 | (0 0) (0 0)
8438 23:07:11.406887 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8439 23:07:11.410095 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8440 23:07:11.413373 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8441 23:07:11.419847 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8442 23:07:11.423371 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8443 23:07:11.426754 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8444 23:07:11.433614 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8445 23:07:11.436874 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8446 23:07:11.439646 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8447 23:07:11.446675 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8448 23:07:11.450082 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8449 23:07:11.453118 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8450 23:07:11.459589 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8451 23:07:11.462843 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8452 23:07:11.466300 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8453 23:07:11.472722 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8454 23:07:11.476040 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8455 23:07:11.479761 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8456 23:07:11.485991 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8457 23:07:11.489327 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8458 23:07:11.492696 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8459 23:07:11.499500 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8460 23:07:11.502702 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8461 23:07:11.506459 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8462 23:07:11.512357 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8463 23:07:11.512892 Total UI for P1: 0, mck2ui 16
8464 23:07:11.519472 best dqsien dly found for B0: ( 1, 9, 8)
8465 23:07:11.522236 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8466 23:07:11.525690 Total UI for P1: 0, mck2ui 16
8467 23:07:11.528980 best dqsien dly found for B1: ( 1, 9, 10)
8468 23:07:11.532402 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8469 23:07:11.536057 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8470 23:07:11.536516
8471 23:07:11.539150 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8472 23:07:11.541978 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8473 23:07:11.545251 [Gating] SW calibration Done
8474 23:07:11.545336 ==
8475 23:07:11.548969 Dram Type= 6, Freq= 0, CH_1, rank 0
8476 23:07:11.551879 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8477 23:07:11.555495 ==
8478 23:07:11.555580 RX Vref Scan: 0
8479 23:07:11.555647
8480 23:07:11.558952 RX Vref 0 -> 0, step: 1
8481 23:07:11.559037
8482 23:07:11.559103 RX Delay 0 -> 252, step: 8
8483 23:07:11.565421 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8484 23:07:11.568703 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8485 23:07:11.572161 iDelay=200, Bit 2, Center 127 (80 ~ 175) 96
8486 23:07:11.575305 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8487 23:07:11.578711 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8488 23:07:11.585181 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8489 23:07:11.588430 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8490 23:07:11.591858 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8491 23:07:11.595183 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8492 23:07:11.598649 iDelay=200, Bit 9, Center 123 (80 ~ 167) 88
8493 23:07:11.601947 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8494 23:07:11.608364 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8495 23:07:11.611752 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8496 23:07:11.615252 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8497 23:07:11.618798 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8498 23:07:11.625141 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8499 23:07:11.625225 ==
8500 23:07:11.628844 Dram Type= 6, Freq= 0, CH_1, rank 0
8501 23:07:11.631728 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8502 23:07:11.631822 ==
8503 23:07:11.631890 DQS Delay:
8504 23:07:11.634935 DQS0 = 0, DQS1 = 0
8505 23:07:11.635021 DQM Delay:
8506 23:07:11.638554 DQM0 = 138, DQM1 = 130
8507 23:07:11.638639 DQ Delay:
8508 23:07:11.641875 DQ0 =143, DQ1 =135, DQ2 =127, DQ3 =139
8509 23:07:11.644956 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8510 23:07:11.648493 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =123
8511 23:07:11.652217 DQ12 =139, DQ13 =135, DQ14 =139, DQ15 =135
8512 23:07:11.652303
8513 23:07:11.652404
8514 23:07:11.655147 ==
8515 23:07:11.658307 Dram Type= 6, Freq= 0, CH_1, rank 0
8516 23:07:11.661951 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8517 23:07:11.662037 ==
8518 23:07:11.662103
8519 23:07:11.662165
8520 23:07:11.665087 TX Vref Scan disable
8521 23:07:11.665172 == TX Byte 0 ==
8522 23:07:11.668849 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8523 23:07:11.674892 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8524 23:07:11.675004 == TX Byte 1 ==
8525 23:07:11.678265 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8526 23:07:11.685159 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8527 23:07:11.685273 ==
8528 23:07:11.688112 Dram Type= 6, Freq= 0, CH_1, rank 0
8529 23:07:11.691940 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8530 23:07:11.692031 ==
8531 23:07:11.703306
8532 23:07:11.706663 TX Vref early break, caculate TX vref
8533 23:07:11.710042 TX Vref=16, minBit 10, minWin=21, winSum=369
8534 23:07:11.713194 TX Vref=18, minBit 10, minWin=22, winSum=376
8535 23:07:11.716305 TX Vref=20, minBit 10, minWin=23, winSum=391
8536 23:07:11.719758 TX Vref=22, minBit 10, minWin=23, winSum=400
8537 23:07:11.726350 TX Vref=24, minBit 10, minWin=24, winSum=406
8538 23:07:11.729952 TX Vref=26, minBit 8, minWin=25, winSum=418
8539 23:07:11.732969 TX Vref=28, minBit 10, minWin=25, winSum=416
8540 23:07:11.736258 TX Vref=30, minBit 10, minWin=23, winSum=404
8541 23:07:11.739799 TX Vref=32, minBit 9, minWin=23, winSum=395
8542 23:07:11.746394 [TxChooseVref] Worse bit 8, Min win 25, Win sum 418, Final Vref 26
8543 23:07:11.746480
8544 23:07:11.749550 Final TX Range 0 Vref 26
8545 23:07:11.749634
8546 23:07:11.749701 ==
8547 23:07:11.752991 Dram Type= 6, Freq= 0, CH_1, rank 0
8548 23:07:11.756540 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8549 23:07:11.756635 ==
8550 23:07:11.756733
8551 23:07:11.756830
8552 23:07:11.759639 TX Vref Scan disable
8553 23:07:11.766180 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8554 23:07:11.766297 == TX Byte 0 ==
8555 23:07:11.769400 u2DelayCellOfst[0]=13 cells (4 PI)
8556 23:07:11.772848 u2DelayCellOfst[1]=10 cells (3 PI)
8557 23:07:11.776245 u2DelayCellOfst[2]=0 cells (0 PI)
8558 23:07:11.779819 u2DelayCellOfst[3]=6 cells (2 PI)
8559 23:07:11.782688 u2DelayCellOfst[4]=6 cells (2 PI)
8560 23:07:11.786074 u2DelayCellOfst[5]=16 cells (5 PI)
8561 23:07:11.789527 u2DelayCellOfst[6]=16 cells (5 PI)
8562 23:07:11.789630 u2DelayCellOfst[7]=6 cells (2 PI)
8563 23:07:11.796091 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8564 23:07:11.799553 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8565 23:07:11.802704 == TX Byte 1 ==
8566 23:07:11.802807 u2DelayCellOfst[8]=0 cells (0 PI)
8567 23:07:11.806478 u2DelayCellOfst[9]=3 cells (1 PI)
8568 23:07:11.809541 u2DelayCellOfst[10]=10 cells (3 PI)
8569 23:07:11.813196 u2DelayCellOfst[11]=3 cells (1 PI)
8570 23:07:11.816045 u2DelayCellOfst[12]=16 cells (5 PI)
8571 23:07:11.819577 u2DelayCellOfst[13]=20 cells (6 PI)
8572 23:07:11.823163 u2DelayCellOfst[14]=16 cells (5 PI)
8573 23:07:11.826494 u2DelayCellOfst[15]=16 cells (5 PI)
8574 23:07:11.829306 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8575 23:07:11.836066 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8576 23:07:11.836150 DramC Write-DBI on
8577 23:07:11.836217 ==
8578 23:07:11.839309 Dram Type= 6, Freq= 0, CH_1, rank 0
8579 23:07:11.842927 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8580 23:07:11.843012 ==
8581 23:07:11.846106
8582 23:07:11.846189
8583 23:07:11.846255 TX Vref Scan disable
8584 23:07:11.849484 == TX Byte 0 ==
8585 23:07:11.852534 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8586 23:07:11.855834 == TX Byte 1 ==
8587 23:07:11.859300 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8588 23:07:11.859384 DramC Write-DBI off
8589 23:07:11.862579
8590 23:07:11.862665 [DATLAT]
8591 23:07:11.862748 Freq=1600, CH1 RK0
8592 23:07:11.862811
8593 23:07:11.865893 DATLAT Default: 0xf
8594 23:07:11.865976 0, 0xFFFF, sum = 0
8595 23:07:11.869219 1, 0xFFFF, sum = 0
8596 23:07:11.872648 2, 0xFFFF, sum = 0
8597 23:07:11.872732 3, 0xFFFF, sum = 0
8598 23:07:11.875684 4, 0xFFFF, sum = 0
8599 23:07:11.875769 5, 0xFFFF, sum = 0
8600 23:07:11.879348 6, 0xFFFF, sum = 0
8601 23:07:11.879433 7, 0xFFFF, sum = 0
8602 23:07:11.882626 8, 0xFFFF, sum = 0
8603 23:07:11.882711 9, 0xFFFF, sum = 0
8604 23:07:11.885638 10, 0xFFFF, sum = 0
8605 23:07:11.885722 11, 0xFFFF, sum = 0
8606 23:07:11.889056 12, 0xFFFF, sum = 0
8607 23:07:11.889177 13, 0xFFFF, sum = 0
8608 23:07:11.892539 14, 0x0, sum = 1
8609 23:07:11.892649 15, 0x0, sum = 2
8610 23:07:11.895892 16, 0x0, sum = 3
8611 23:07:11.896003 17, 0x0, sum = 4
8612 23:07:11.898918 best_step = 15
8613 23:07:11.899029
8614 23:07:11.899129 ==
8615 23:07:11.902216 Dram Type= 6, Freq= 0, CH_1, rank 0
8616 23:07:11.905665 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8617 23:07:11.905778 ==
8618 23:07:11.905874 RX Vref Scan: 1
8619 23:07:11.908875
8620 23:07:11.908988 Set Vref Range= 24 -> 127
8621 23:07:11.909083
8622 23:07:11.912464 RX Vref 24 -> 127, step: 1
8623 23:07:11.912573
8624 23:07:11.915602 RX Delay 19 -> 252, step: 4
8625 23:07:11.915708
8626 23:07:11.919167 Set Vref, RX VrefLevel [Byte0]: 24
8627 23:07:11.922275 [Byte1]: 24
8628 23:07:11.922408
8629 23:07:11.925557 Set Vref, RX VrefLevel [Byte0]: 25
8630 23:07:11.928972 [Byte1]: 25
8631 23:07:11.929086
8632 23:07:11.932283 Set Vref, RX VrefLevel [Byte0]: 26
8633 23:07:11.935454 [Byte1]: 26
8634 23:07:11.939447
8635 23:07:11.939562 Set Vref, RX VrefLevel [Byte0]: 27
8636 23:07:11.943252 [Byte1]: 27
8637 23:07:11.947044
8638 23:07:11.947158 Set Vref, RX VrefLevel [Byte0]: 28
8639 23:07:11.950562 [Byte1]: 28
8640 23:07:11.954357
8641 23:07:11.954506 Set Vref, RX VrefLevel [Byte0]: 29
8642 23:07:11.957980 [Byte1]: 29
8643 23:07:11.962234
8644 23:07:11.962346 Set Vref, RX VrefLevel [Byte0]: 30
8645 23:07:11.965336 [Byte1]: 30
8646 23:07:11.969808
8647 23:07:11.969891 Set Vref, RX VrefLevel [Byte0]: 31
8648 23:07:11.973409 [Byte1]: 31
8649 23:07:11.977505
8650 23:07:11.977609 Set Vref, RX VrefLevel [Byte0]: 32
8651 23:07:11.980622 [Byte1]: 32
8652 23:07:11.985164
8653 23:07:11.985274 Set Vref, RX VrefLevel [Byte0]: 33
8654 23:07:11.988176 [Byte1]: 33
8655 23:07:11.992342
8656 23:07:11.992483 Set Vref, RX VrefLevel [Byte0]: 34
8657 23:07:11.995550 [Byte1]: 34
8658 23:07:12.000007
8659 23:07:12.000111 Set Vref, RX VrefLevel [Byte0]: 35
8660 23:07:12.003240 [Byte1]: 35
8661 23:07:12.007613
8662 23:07:12.007729 Set Vref, RX VrefLevel [Byte0]: 36
8663 23:07:12.014193 [Byte1]: 36
8664 23:07:12.014303
8665 23:07:12.017496 Set Vref, RX VrefLevel [Byte0]: 37
8666 23:07:12.020557 [Byte1]: 37
8667 23:07:12.020659
8668 23:07:12.024028 Set Vref, RX VrefLevel [Byte0]: 38
8669 23:07:12.027474 [Byte1]: 38
8670 23:07:12.027556
8671 23:07:12.031322 Set Vref, RX VrefLevel [Byte0]: 39
8672 23:07:12.033920 [Byte1]: 39
8673 23:07:12.037877
8674 23:07:12.037976 Set Vref, RX VrefLevel [Byte0]: 40
8675 23:07:12.041281 [Byte1]: 40
8676 23:07:12.045644
8677 23:07:12.045721 Set Vref, RX VrefLevel [Byte0]: 41
8678 23:07:12.048600 [Byte1]: 41
8679 23:07:12.053213
8680 23:07:12.053315 Set Vref, RX VrefLevel [Byte0]: 42
8681 23:07:12.056657 [Byte1]: 42
8682 23:07:12.060682
8683 23:07:12.060792 Set Vref, RX VrefLevel [Byte0]: 43
8684 23:07:12.063996 [Byte1]: 43
8685 23:07:12.068241
8686 23:07:12.068351 Set Vref, RX VrefLevel [Byte0]: 44
8687 23:07:12.071514 [Byte1]: 44
8688 23:07:12.075669
8689 23:07:12.075746 Set Vref, RX VrefLevel [Byte0]: 45
8690 23:07:12.079502 [Byte1]: 45
8691 23:07:12.083552
8692 23:07:12.083660 Set Vref, RX VrefLevel [Byte0]: 46
8693 23:07:12.087298 [Byte1]: 46
8694 23:07:12.091162
8695 23:07:12.091277 Set Vref, RX VrefLevel [Byte0]: 47
8696 23:07:12.094610 [Byte1]: 47
8697 23:07:12.098773
8698 23:07:12.098899 Set Vref, RX VrefLevel [Byte0]: 48
8699 23:07:12.102208 [Byte1]: 48
8700 23:07:12.105921
8701 23:07:12.106075 Set Vref, RX VrefLevel [Byte0]: 49
8702 23:07:12.109392 [Byte1]: 49
8703 23:07:12.113651
8704 23:07:12.113782 Set Vref, RX VrefLevel [Byte0]: 50
8705 23:07:12.117281 [Byte1]: 50
8706 23:07:12.121126
8707 23:07:12.121297 Set Vref, RX VrefLevel [Byte0]: 51
8708 23:07:12.124879 [Byte1]: 51
8709 23:07:12.128857
8710 23:07:12.129030 Set Vref, RX VrefLevel [Byte0]: 52
8711 23:07:12.132153 [Byte1]: 52
8712 23:07:12.136327
8713 23:07:12.136467 Set Vref, RX VrefLevel [Byte0]: 53
8714 23:07:12.140156 [Byte1]: 53
8715 23:07:12.143902
8716 23:07:12.143984 Set Vref, RX VrefLevel [Byte0]: 54
8717 23:07:12.147323 [Byte1]: 54
8718 23:07:12.151649
8719 23:07:12.151733 Set Vref, RX VrefLevel [Byte0]: 55
8720 23:07:12.154911 [Byte1]: 55
8721 23:07:12.158802
8722 23:07:12.158886 Set Vref, RX VrefLevel [Byte0]: 56
8723 23:07:12.162346 [Byte1]: 56
8724 23:07:12.166735
8725 23:07:12.166818 Set Vref, RX VrefLevel [Byte0]: 57
8726 23:07:12.169825 [Byte1]: 57
8727 23:07:12.174337
8728 23:07:12.174443 Set Vref, RX VrefLevel [Byte0]: 58
8729 23:07:12.177498 [Byte1]: 58
8730 23:07:12.181938
8731 23:07:12.182021 Set Vref, RX VrefLevel [Byte0]: 59
8732 23:07:12.185339 [Byte1]: 59
8733 23:07:12.189440
8734 23:07:12.189523 Set Vref, RX VrefLevel [Byte0]: 60
8735 23:07:12.192640 [Byte1]: 60
8736 23:07:12.196739
8737 23:07:12.196822 Set Vref, RX VrefLevel [Byte0]: 61
8738 23:07:12.200372 [Byte1]: 61
8739 23:07:12.204543
8740 23:07:12.204626 Set Vref, RX VrefLevel [Byte0]: 62
8741 23:07:12.207820 [Byte1]: 62
8742 23:07:12.211792
8743 23:07:12.211875 Set Vref, RX VrefLevel [Byte0]: 63
8744 23:07:12.215517 [Byte1]: 63
8745 23:07:12.219647
8746 23:07:12.219739 Set Vref, RX VrefLevel [Byte0]: 64
8747 23:07:12.222818 [Byte1]: 64
8748 23:07:12.227396
8749 23:07:12.227479 Set Vref, RX VrefLevel [Byte0]: 65
8750 23:07:12.230315 [Byte1]: 65
8751 23:07:12.234841
8752 23:07:12.234925 Set Vref, RX VrefLevel [Byte0]: 66
8753 23:07:12.241178 [Byte1]: 66
8754 23:07:12.241303
8755 23:07:12.244770 Set Vref, RX VrefLevel [Byte0]: 67
8756 23:07:12.247829 [Byte1]: 67
8757 23:07:12.247906
8758 23:07:12.251164 Set Vref, RX VrefLevel [Byte0]: 68
8759 23:07:12.254491 [Byte1]: 68
8760 23:07:12.254566
8761 23:07:12.258060 Set Vref, RX VrefLevel [Byte0]: 69
8762 23:07:12.261113 [Byte1]: 69
8763 23:07:12.264865
8764 23:07:12.264945 Set Vref, RX VrefLevel [Byte0]: 70
8765 23:07:12.268484 [Byte1]: 70
8766 23:07:12.272578
8767 23:07:12.272651 Set Vref, RX VrefLevel [Byte0]: 71
8768 23:07:12.275891 [Byte1]: 71
8769 23:07:12.280229
8770 23:07:12.280305 Set Vref, RX VrefLevel [Byte0]: 72
8771 23:07:12.283288 [Byte1]: 72
8772 23:07:12.287727
8773 23:07:12.287801 Set Vref, RX VrefLevel [Byte0]: 73
8774 23:07:12.291295 [Byte1]: 73
8775 23:07:12.295194
8776 23:07:12.295282 Final RX Vref Byte 0 = 53 to rank0
8777 23:07:12.298710 Final RX Vref Byte 1 = 62 to rank0
8778 23:07:12.302246 Final RX Vref Byte 0 = 53 to rank1
8779 23:07:12.305165 Final RX Vref Byte 1 = 62 to rank1==
8780 23:07:12.308630 Dram Type= 6, Freq= 0, CH_1, rank 0
8781 23:07:12.315354 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8782 23:07:12.315431 ==
8783 23:07:12.315495 DQS Delay:
8784 23:07:12.315564 DQS0 = 0, DQS1 = 0
8785 23:07:12.318733 DQM Delay:
8786 23:07:12.318808 DQM0 = 133, DQM1 = 129
8787 23:07:12.322174 DQ Delay:
8788 23:07:12.325107 DQ0 =136, DQ1 =130, DQ2 =122, DQ3 =132
8789 23:07:12.329324 DQ4 =132, DQ5 =144, DQ6 =144, DQ7 =130
8790 23:07:12.332261 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =122
8791 23:07:12.335187 DQ12 =140, DQ13 =134, DQ14 =136, DQ15 =138
8792 23:07:12.335291
8793 23:07:12.335383
8794 23:07:12.335473
8795 23:07:12.338763 [DramC_TX_OE_Calibration] TA2
8796 23:07:12.341969 Original DQ_B0 (3 6) =30, OEN = 27
8797 23:07:12.345188 Original DQ_B1 (3 6) =30, OEN = 27
8798 23:07:12.348534 24, 0x0, End_B0=24 End_B1=24
8799 23:07:12.348613 25, 0x0, End_B0=25 End_B1=25
8800 23:07:12.351865 26, 0x0, End_B0=26 End_B1=26
8801 23:07:12.355358 27, 0x0, End_B0=27 End_B1=27
8802 23:07:12.358757 28, 0x0, End_B0=28 End_B1=28
8803 23:07:12.358898 29, 0x0, End_B0=29 End_B1=29
8804 23:07:12.361652 30, 0x0, End_B0=30 End_B1=30
8805 23:07:12.365137 31, 0x4141, End_B0=30 End_B1=30
8806 23:07:12.368678 Byte0 end_step=30 best_step=27
8807 23:07:12.371829 Byte1 end_step=30 best_step=27
8808 23:07:12.375350 Byte0 TX OE(2T, 0.5T) = (3, 3)
8809 23:07:12.375443 Byte1 TX OE(2T, 0.5T) = (3, 3)
8810 23:07:12.378319
8811 23:07:12.378428
8812 23:07:12.385008 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a28, (MSB)MR19= 0x303, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
8813 23:07:12.388411 CH1 RK0: MR19=303, MR18=1A28
8814 23:07:12.395209 CH1_RK0: MR19=0x303, MR18=0x1A28, DQSOSC=389, MR23=63, INC=24, DEC=16
8815 23:07:12.395303
8816 23:07:12.398769 ----->DramcWriteLeveling(PI) begin...
8817 23:07:12.398864 ==
8818 23:07:12.401829 Dram Type= 6, Freq= 0, CH_1, rank 1
8819 23:07:12.405124 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8820 23:07:12.405219 ==
8821 23:07:12.408381 Write leveling (Byte 0): 23 => 23
8822 23:07:12.411794 Write leveling (Byte 1): 27 => 27
8823 23:07:12.415174 DramcWriteLeveling(PI) end<-----
8824 23:07:12.415257
8825 23:07:12.415322 ==
8826 23:07:12.418355 Dram Type= 6, Freq= 0, CH_1, rank 1
8827 23:07:12.421831 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8828 23:07:12.421948 ==
8829 23:07:12.424908 [Gating] SW mode calibration
8830 23:07:12.431820 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8831 23:07:12.438204 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8832 23:07:12.441979 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8833 23:07:12.444698 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8834 23:07:12.451341 1 4 8 | B1->B0 | 3333 2323 | 0 0 | (0 0) (0 0)
8835 23:07:12.455176 1 4 12 | B1->B0 | 3434 3130 | 1 1 | (1 1) (1 1)
8836 23:07:12.458168 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8837 23:07:12.464595 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8838 23:07:12.468033 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8839 23:07:12.471500 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8840 23:07:12.478294 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8841 23:07:12.481645 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8842 23:07:12.485039 1 5 8 | B1->B0 | 2727 3434 | 0 1 | (1 0) (1 0)
8843 23:07:12.491751 1 5 12 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
8844 23:07:12.495397 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8845 23:07:12.498362 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8846 23:07:12.504811 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8847 23:07:12.508316 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8848 23:07:12.511793 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8849 23:07:12.518753 1 6 4 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
8850 23:07:12.521826 1 6 8 | B1->B0 | 4444 2323 | 0 0 | (0 0) (0 0)
8851 23:07:12.525416 1 6 12 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
8852 23:07:12.528579 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8853 23:07:12.534836 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8854 23:07:12.538058 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8855 23:07:12.541363 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8856 23:07:12.548291 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8857 23:07:12.551566 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8858 23:07:12.554760 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8859 23:07:12.561475 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8860 23:07:12.564952 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8861 23:07:12.567988 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8862 23:07:12.575184 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8863 23:07:12.578466 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8864 23:07:12.581435 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8865 23:07:12.587985 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8866 23:07:12.591748 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8867 23:07:12.594934 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8868 23:07:12.601483 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8869 23:07:12.605026 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8870 23:07:12.608239 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8871 23:07:12.615010 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8872 23:07:12.618477 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8873 23:07:12.621930 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8874 23:07:12.627828 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8875 23:07:12.631634 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8876 23:07:12.635194 Total UI for P1: 0, mck2ui 16
8877 23:07:12.638473 best dqsien dly found for B0: ( 1, 9, 8)
8878 23:07:12.641888 Total UI for P1: 0, mck2ui 16
8879 23:07:12.644867 best dqsien dly found for B1: ( 1, 9, 6)
8880 23:07:12.648389 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8881 23:07:12.651510 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8882 23:07:12.652076
8883 23:07:12.654771 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8884 23:07:12.658252 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8885 23:07:12.661734 [Gating] SW calibration Done
8886 23:07:12.662215 ==
8887 23:07:12.664994 Dram Type= 6, Freq= 0, CH_1, rank 1
8888 23:07:12.667995 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8889 23:07:12.668476 ==
8890 23:07:12.671671 RX Vref Scan: 0
8891 23:07:12.672239
8892 23:07:12.674896 RX Vref 0 -> 0, step: 1
8893 23:07:12.675366
8894 23:07:12.675837 RX Delay 0 -> 252, step: 8
8895 23:07:12.681713 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8896 23:07:12.684825 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8897 23:07:12.688578 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8898 23:07:12.691767 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8899 23:07:12.694842 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8900 23:07:12.698561 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8901 23:07:12.705087 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8902 23:07:12.707995 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8903 23:07:12.711582 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8904 23:07:12.715155 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8905 23:07:12.718258 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8906 23:07:12.725158 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8907 23:07:12.727974 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8908 23:07:12.731111 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8909 23:07:12.734948 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8910 23:07:12.741267 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8911 23:07:12.741839 ==
8912 23:07:12.744449 Dram Type= 6, Freq= 0, CH_1, rank 1
8913 23:07:12.747929 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8914 23:07:12.748509 ==
8915 23:07:12.748890 DQS Delay:
8916 23:07:12.751210 DQS0 = 0, DQS1 = 0
8917 23:07:12.751681 DQM Delay:
8918 23:07:12.755012 DQM0 = 136, DQM1 = 133
8919 23:07:12.755583 DQ Delay:
8920 23:07:12.758227 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8921 23:07:12.761589 DQ4 =135, DQ5 =147, DQ6 =143, DQ7 =135
8922 23:07:12.764702 DQ8 =115, DQ9 =119, DQ10 =135, DQ11 =127
8923 23:07:12.767951 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8924 23:07:12.768454
8925 23:07:12.768825
8926 23:07:12.770922 ==
8927 23:07:12.771392 Dram Type= 6, Freq= 0, CH_1, rank 1
8928 23:07:12.777844 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8929 23:07:12.778513 ==
8930 23:07:12.779050
8931 23:07:12.779433
8932 23:07:12.781336 TX Vref Scan disable
8933 23:07:12.781909 == TX Byte 0 ==
8934 23:07:12.784462 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8935 23:07:12.791289 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8936 23:07:12.791848 == TX Byte 1 ==
8937 23:07:12.794261 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8938 23:07:12.801312 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8939 23:07:12.801886 ==
8940 23:07:12.804508 Dram Type= 6, Freq= 0, CH_1, rank 1
8941 23:07:12.807569 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8942 23:07:12.808148 ==
8943 23:07:12.820752
8944 23:07:12.823965 TX Vref early break, caculate TX vref
8945 23:07:12.827165 TX Vref=16, minBit 12, minWin=22, winSum=384
8946 23:07:12.830470 TX Vref=18, minBit 9, minWin=23, winSum=397
8947 23:07:12.834142 TX Vref=20, minBit 12, minWin=24, winSum=406
8948 23:07:12.837152 TX Vref=22, minBit 9, minWin=24, winSum=412
8949 23:07:12.840680 TX Vref=24, minBit 11, minWin=25, winSum=420
8950 23:07:12.847558 TX Vref=26, minBit 12, minWin=25, winSum=429
8951 23:07:12.851002 TX Vref=28, minBit 0, minWin=25, winSum=421
8952 23:07:12.853974 TX Vref=30, minBit 10, minWin=24, winSum=414
8953 23:07:12.857290 TX Vref=32, minBit 0, minWin=25, winSum=408
8954 23:07:12.860648 TX Vref=34, minBit 10, minWin=23, winSum=396
8955 23:07:12.866887 [TxChooseVref] Worse bit 12, Min win 25, Win sum 429, Final Vref 26
8956 23:07:12.867450
8957 23:07:12.870120 Final TX Range 0 Vref 26
8958 23:07:12.870620
8959 23:07:12.870993 ==
8960 23:07:12.873753 Dram Type= 6, Freq= 0, CH_1, rank 1
8961 23:07:12.876942 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8962 23:07:12.877429 ==
8963 23:07:12.877802
8964 23:07:12.878142
8965 23:07:12.880368 TX Vref Scan disable
8966 23:07:12.886805 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8967 23:07:12.887365 == TX Byte 0 ==
8968 23:07:12.890509 u2DelayCellOfst[0]=16 cells (5 PI)
8969 23:07:12.893281 u2DelayCellOfst[1]=13 cells (4 PI)
8970 23:07:12.896758 u2DelayCellOfst[2]=0 cells (0 PI)
8971 23:07:12.900542 u2DelayCellOfst[3]=6 cells (2 PI)
8972 23:07:12.903729 u2DelayCellOfst[4]=10 cells (3 PI)
8973 23:07:12.906724 u2DelayCellOfst[5]=20 cells (6 PI)
8974 23:07:12.910343 u2DelayCellOfst[6]=16 cells (5 PI)
8975 23:07:12.913473 u2DelayCellOfst[7]=6 cells (2 PI)
8976 23:07:12.917107 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8977 23:07:12.920559 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8978 23:07:12.923200 == TX Byte 1 ==
8979 23:07:12.926522 u2DelayCellOfst[8]=0 cells (0 PI)
8980 23:07:12.926992 u2DelayCellOfst[9]=3 cells (1 PI)
8981 23:07:12.930174 u2DelayCellOfst[10]=6 cells (2 PI)
8982 23:07:12.933488 u2DelayCellOfst[11]=3 cells (1 PI)
8983 23:07:12.936966 u2DelayCellOfst[12]=13 cells (4 PI)
8984 23:07:12.940078 u2DelayCellOfst[13]=16 cells (5 PI)
8985 23:07:12.943439 u2DelayCellOfst[14]=20 cells (6 PI)
8986 23:07:12.946492 u2DelayCellOfst[15]=20 cells (6 PI)
8987 23:07:12.950551 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8988 23:07:12.956742 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8989 23:07:12.957319 DramC Write-DBI on
8990 23:07:12.957696 ==
8991 23:07:12.960438 Dram Type= 6, Freq= 0, CH_1, rank 1
8992 23:07:12.966731 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8993 23:07:12.967310 ==
8994 23:07:12.967682
8995 23:07:12.968022
8996 23:07:12.968347 TX Vref Scan disable
8997 23:07:12.970145 == TX Byte 0 ==
8998 23:07:12.974230 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8999 23:07:12.977235 == TX Byte 1 ==
9000 23:07:12.980365 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
9001 23:07:12.983631 DramC Write-DBI off
9002 23:07:12.984213
9003 23:07:12.984586 [DATLAT]
9004 23:07:12.984929 Freq=1600, CH1 RK1
9005 23:07:12.985260
9006 23:07:12.986999 DATLAT Default: 0xf
9007 23:07:12.987467 0, 0xFFFF, sum = 0
9008 23:07:12.990428 1, 0xFFFF, sum = 0
9009 23:07:12.994200 2, 0xFFFF, sum = 0
9010 23:07:12.994724 3, 0xFFFF, sum = 0
9011 23:07:12.996938 4, 0xFFFF, sum = 0
9012 23:07:12.997518 5, 0xFFFF, sum = 0
9013 23:07:13.000568 6, 0xFFFF, sum = 0
9014 23:07:13.001191 7, 0xFFFF, sum = 0
9015 23:07:13.003968 8, 0xFFFF, sum = 0
9016 23:07:13.004549 9, 0xFFFF, sum = 0
9017 23:07:13.007131 10, 0xFFFF, sum = 0
9018 23:07:13.007611 11, 0xFFFF, sum = 0
9019 23:07:13.010381 12, 0xFFFF, sum = 0
9020 23:07:13.011006 13, 0xFFFF, sum = 0
9021 23:07:13.013438 14, 0x0, sum = 1
9022 23:07:13.013914 15, 0x0, sum = 2
9023 23:07:13.016986 16, 0x0, sum = 3
9024 23:07:13.017569 17, 0x0, sum = 4
9025 23:07:13.020146 best_step = 15
9026 23:07:13.020618
9027 23:07:13.020982 ==
9028 23:07:13.023244 Dram Type= 6, Freq= 0, CH_1, rank 1
9029 23:07:13.026998 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9030 23:07:13.027574 ==
9031 23:07:13.030013 RX Vref Scan: 0
9032 23:07:13.030508
9033 23:07:13.030877 RX Vref 0 -> 0, step: 1
9034 23:07:13.031216
9035 23:07:13.033583 RX Delay 19 -> 252, step: 4
9036 23:07:13.037038 iDelay=195, Bit 0, Center 136 (95 ~ 178) 84
9037 23:07:13.043395 iDelay=195, Bit 1, Center 130 (87 ~ 174) 88
9038 23:07:13.046811 iDelay=195, Bit 2, Center 118 (71 ~ 166) 96
9039 23:07:13.050364 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
9040 23:07:13.053692 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
9041 23:07:13.056935 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
9042 23:07:13.060045 iDelay=195, Bit 6, Center 142 (95 ~ 190) 96
9043 23:07:13.066975 iDelay=195, Bit 7, Center 130 (83 ~ 178) 96
9044 23:07:13.070288 iDelay=195, Bit 8, Center 112 (63 ~ 162) 100
9045 23:07:13.074112 iDelay=195, Bit 9, Center 120 (71 ~ 170) 100
9046 23:07:13.076897 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
9047 23:07:13.080575 iDelay=195, Bit 11, Center 126 (75 ~ 178) 104
9048 23:07:13.086931 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
9049 23:07:13.090368 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
9050 23:07:13.094081 iDelay=195, Bit 14, Center 138 (91 ~ 186) 96
9051 23:07:13.097098 iDelay=195, Bit 15, Center 142 (91 ~ 194) 104
9052 23:07:13.097674 ==
9053 23:07:13.100099 Dram Type= 6, Freq= 0, CH_1, rank 1
9054 23:07:13.106828 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9055 23:07:13.107411 ==
9056 23:07:13.107787 DQS Delay:
9057 23:07:13.108132 DQS0 = 0, DQS1 = 0
9058 23:07:13.109829 DQM Delay:
9059 23:07:13.110300 DQM0 = 133, DQM1 = 130
9060 23:07:13.113215 DQ Delay:
9061 23:07:13.116549 DQ0 =136, DQ1 =130, DQ2 =118, DQ3 =130
9062 23:07:13.120167 DQ4 =134, DQ5 =146, DQ6 =142, DQ7 =130
9063 23:07:13.122993 DQ8 =112, DQ9 =120, DQ10 =130, DQ11 =126
9064 23:07:13.126609 DQ12 =138, DQ13 =138, DQ14 =138, DQ15 =142
9065 23:07:13.127207
9066 23:07:13.127580
9067 23:07:13.127921
9068 23:07:13.129833 [DramC_TX_OE_Calibration] TA2
9069 23:07:13.133221 Original DQ_B0 (3 6) =30, OEN = 27
9070 23:07:13.136620 Original DQ_B1 (3 6) =30, OEN = 27
9071 23:07:13.140451 24, 0x0, End_B0=24 End_B1=24
9072 23:07:13.141035 25, 0x0, End_B0=25 End_B1=25
9073 23:07:13.143072 26, 0x0, End_B0=26 End_B1=26
9074 23:07:13.146513 27, 0x0, End_B0=27 End_B1=27
9075 23:07:13.149946 28, 0x0, End_B0=28 End_B1=28
9076 23:07:13.153138 29, 0x0, End_B0=29 End_B1=29
9077 23:07:13.153720 30, 0x0, End_B0=30 End_B1=30
9078 23:07:13.156325 31, 0x4141, End_B0=30 End_B1=30
9079 23:07:13.160065 Byte0 end_step=30 best_step=27
9080 23:07:13.162985 Byte1 end_step=30 best_step=27
9081 23:07:13.166286 Byte0 TX OE(2T, 0.5T) = (3, 3)
9082 23:07:13.169427 Byte1 TX OE(2T, 0.5T) = (3, 3)
9083 23:07:13.169897
9084 23:07:13.170263
9085 23:07:13.176843 [DQSOSCAuto] RK1, (LSB)MR18= 0x1a04, (MSB)MR19= 0x303, tDQSOscB0 = 408 ps tDQSOscB1 = 396 ps
9086 23:07:13.179478 CH1 RK1: MR19=303, MR18=1A04
9087 23:07:13.186268 CH1_RK1: MR19=0x303, MR18=0x1A04, DQSOSC=396, MR23=63, INC=23, DEC=15
9088 23:07:13.189598 [RxdqsGatingPostProcess] freq 1600
9089 23:07:13.193537 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9090 23:07:13.196303 best DQS0 dly(2T, 0.5T) = (1, 1)
9091 23:07:13.199171 best DQS1 dly(2T, 0.5T) = (1, 1)
9092 23:07:13.202926 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9093 23:07:13.206367 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9094 23:07:13.209275 best DQS0 dly(2T, 0.5T) = (1, 1)
9095 23:07:13.212858 best DQS1 dly(2T, 0.5T) = (1, 1)
9096 23:07:13.215865 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9097 23:07:13.219651 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9098 23:07:13.222877 Pre-setting of DQS Precalculation
9099 23:07:13.225771 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9100 23:07:13.232999 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9101 23:07:13.242764 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9102 23:07:13.243332
9103 23:07:13.243706
9104 23:07:13.244050 [Calibration Summary] 3200 Mbps
9105 23:07:13.245708 CH 0, Rank 0
9106 23:07:13.246279 SW Impedance : PASS
9107 23:07:13.249553 DUTY Scan : NO K
9108 23:07:13.252420 ZQ Calibration : PASS
9109 23:07:13.253000 Jitter Meter : NO K
9110 23:07:13.255661 CBT Training : PASS
9111 23:07:13.258804 Write leveling : PASS
9112 23:07:13.259280 RX DQS gating : PASS
9113 23:07:13.262283 RX DQ/DQS(RDDQC) : PASS
9114 23:07:13.265870 TX DQ/DQS : PASS
9115 23:07:13.266498 RX DATLAT : PASS
9116 23:07:13.268797 RX DQ/DQS(Engine): PASS
9117 23:07:13.272508 TX OE : PASS
9118 23:07:13.273097 All Pass.
9119 23:07:13.273473
9120 23:07:13.273815 CH 0, Rank 1
9121 23:07:13.275697 SW Impedance : PASS
9122 23:07:13.278652 DUTY Scan : NO K
9123 23:07:13.279149 ZQ Calibration : PASS
9124 23:07:13.282295 Jitter Meter : NO K
9125 23:07:13.285669 CBT Training : PASS
9126 23:07:13.286249 Write leveling : PASS
9127 23:07:13.288894 RX DQS gating : PASS
9128 23:07:13.292047 RX DQ/DQS(RDDQC) : PASS
9129 23:07:13.292621 TX DQ/DQS : PASS
9130 23:07:13.295203 RX DATLAT : PASS
9131 23:07:13.299072 RX DQ/DQS(Engine): PASS
9132 23:07:13.299655 TX OE : PASS
9133 23:07:13.300104 All Pass.
9134 23:07:13.302249
9135 23:07:13.302878 CH 1, Rank 0
9136 23:07:13.305383 SW Impedance : PASS
9137 23:07:13.305961 DUTY Scan : NO K
9138 23:07:13.308458 ZQ Calibration : PASS
9139 23:07:13.308928 Jitter Meter : NO K
9140 23:07:13.311740 CBT Training : PASS
9141 23:07:13.315412 Write leveling : PASS
9142 23:07:13.316085 RX DQS gating : PASS
9143 23:07:13.318675 RX DQ/DQS(RDDQC) : PASS
9144 23:07:13.321722 TX DQ/DQS : PASS
9145 23:07:13.322495 RX DATLAT : PASS
9146 23:07:13.325176 RX DQ/DQS(Engine): PASS
9147 23:07:13.328731 TX OE : PASS
9148 23:07:13.329320 All Pass.
9149 23:07:13.329721
9150 23:07:13.330074 CH 1, Rank 1
9151 23:07:13.331706 SW Impedance : PASS
9152 23:07:13.335367 DUTY Scan : NO K
9153 23:07:13.335844 ZQ Calibration : PASS
9154 23:07:13.338108 Jitter Meter : NO K
9155 23:07:13.341794 CBT Training : PASS
9156 23:07:13.342436 Write leveling : PASS
9157 23:07:13.345357 RX DQS gating : PASS
9158 23:07:13.348858 RX DQ/DQS(RDDQC) : PASS
9159 23:07:13.349441 TX DQ/DQS : PASS
9160 23:07:13.351920 RX DATLAT : PASS
9161 23:07:13.355503 RX DQ/DQS(Engine): PASS
9162 23:07:13.356090 TX OE : PASS
9163 23:07:13.356475 All Pass.
9164 23:07:13.358626
9165 23:07:13.359104 DramC Write-DBI on
9166 23:07:13.362096 PER_BANK_REFRESH: Hybrid Mode
9167 23:07:13.362716 TX_TRACKING: ON
9168 23:07:13.371521 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9169 23:07:13.378189 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9170 23:07:13.388202 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9171 23:07:13.391754 [FAST_K] Save calibration result to emmc
9172 23:07:13.394736 sync common calibartion params.
9173 23:07:13.395219 sync cbt_mode0:1, 1:1
9174 23:07:13.398121 dram_init: ddr_geometry: 2
9175 23:07:13.401995 dram_init: ddr_geometry: 2
9176 23:07:13.402545 dram_init: ddr_geometry: 2
9177 23:07:13.404866 0:dram_rank_size:100000000
9178 23:07:13.408186 1:dram_rank_size:100000000
9179 23:07:13.411388 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9180 23:07:13.414592 DFS_SHUFFLE_HW_MODE: ON
9181 23:07:13.417944 dramc_set_vcore_voltage set vcore to 725000
9182 23:07:13.420981 Read voltage for 1600, 0
9183 23:07:13.421582 Vio18 = 0
9184 23:07:13.424602 Vcore = 725000
9185 23:07:13.425105 Vdram = 0
9186 23:07:13.425562 Vddq = 0
9187 23:07:13.428118 Vmddr = 0
9188 23:07:13.428594 switch to 3200 Mbps bootup
9189 23:07:13.431196 [DramcRunTimeConfig]
9190 23:07:13.431677 PHYPLL
9191 23:07:13.434486 DPM_CONTROL_AFTERK: ON
9192 23:07:13.434922 PER_BANK_REFRESH: ON
9193 23:07:13.437667 REFRESH_OVERHEAD_REDUCTION: ON
9194 23:07:13.441081 CMD_PICG_NEW_MODE: OFF
9195 23:07:13.441567 XRTWTW_NEW_MODE: ON
9196 23:07:13.444867 XRTRTR_NEW_MODE: ON
9197 23:07:13.445336 TX_TRACKING: ON
9198 23:07:13.448113 RDSEL_TRACKING: OFF
9199 23:07:13.451328 DQS Precalculation for DVFS: ON
9200 23:07:13.451796 RX_TRACKING: OFF
9201 23:07:13.454576 HW_GATING DBG: ON
9202 23:07:13.455044 ZQCS_ENABLE_LP4: ON
9203 23:07:13.458101 RX_PICG_NEW_MODE: ON
9204 23:07:13.458748 TX_PICG_NEW_MODE: ON
9205 23:07:13.460918 ENABLE_RX_DCM_DPHY: ON
9206 23:07:13.464631 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9207 23:07:13.467626 DUMMY_READ_FOR_TRACKING: OFF
9208 23:07:13.468099 !!! SPM_CONTROL_AFTERK: OFF
9209 23:07:13.471351 !!! SPM could not control APHY
9210 23:07:13.474601 IMPEDANCE_TRACKING: ON
9211 23:07:13.475173 TEMP_SENSOR: ON
9212 23:07:13.477758 HW_SAVE_FOR_SR: OFF
9213 23:07:13.481168 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9214 23:07:13.484313 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9215 23:07:13.484884 Read ODT Tracking: ON
9216 23:07:13.487690 Refresh Rate DeBounce: ON
9217 23:07:13.491278 DFS_NO_QUEUE_FLUSH: ON
9218 23:07:13.494417 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9219 23:07:13.494998 ENABLE_DFS_RUNTIME_MRW: OFF
9220 23:07:13.498081 DDR_RESERVE_NEW_MODE: ON
9221 23:07:13.500980 MR_CBT_SWITCH_FREQ: ON
9222 23:07:13.501450 =========================
9223 23:07:13.521825 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9224 23:07:13.524676 dram_init: ddr_geometry: 2
9225 23:07:13.542520 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9226 23:07:13.546067 dram_init: dram init end (result: 0)
9227 23:07:13.553012 DRAM-K: Full calibration passed in 24519 msecs
9228 23:07:13.556049 MRC: failed to locate region type 0.
9229 23:07:13.556617 DRAM rank0 size:0x100000000,
9230 23:07:13.559123 DRAM rank1 size=0x100000000
9231 23:07:13.569437 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9232 23:07:13.576195 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9233 23:07:13.582536 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9234 23:07:13.589451 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9235 23:07:13.592607 DRAM rank0 size:0x100000000,
9236 23:07:13.595932 DRAM rank1 size=0x100000000
9237 23:07:13.596503 CBMEM:
9238 23:07:13.598991 IMD: root @ 0xfffff000 254 entries.
9239 23:07:13.602483 IMD: root @ 0xffffec00 62 entries.
9240 23:07:13.605780 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9241 23:07:13.612166 WARNING: RO_VPD is uninitialized or empty.
9242 23:07:13.616061 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9243 23:07:13.623019 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9244 23:07:13.635376 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9245 23:07:13.647059 BS: romstage times (exec / console): total (unknown) / 24014 ms
9246 23:07:13.647640
9247 23:07:13.648014
9248 23:07:13.656850 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9249 23:07:13.660602 ARM64: Exception handlers installed.
9250 23:07:13.663742 ARM64: Testing exception
9251 23:07:13.674540 ARM64: Done test exception
9252 23:07:13.675020 Enumerating buses...
9253 23:07:13.675395 Show all devs... Before device enumeration.
9254 23:07:13.675766 Root Device: enabled 1
9255 23:07:13.676803 CPU_CLUSTER: 0: enabled 1
9256 23:07:13.677274 CPU: 00: enabled 1
9257 23:07:13.680234 Compare with tree...
9258 23:07:13.680705 Root Device: enabled 1
9259 23:07:13.683302 CPU_CLUSTER: 0: enabled 1
9260 23:07:13.686886 CPU: 00: enabled 1
9261 23:07:13.687360 Root Device scanning...
9262 23:07:13.690499 scan_static_bus for Root Device
9263 23:07:13.693830 CPU_CLUSTER: 0 enabled
9264 23:07:13.696844 scan_static_bus for Root Device done
9265 23:07:13.699874 scan_bus: bus Root Device finished in 8 msecs
9266 23:07:13.700463 done
9267 23:07:13.707092 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9268 23:07:13.709747 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9269 23:07:13.716845 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9270 23:07:13.720058 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9271 23:07:13.723428 Allocating resources...
9272 23:07:13.726739 Reading resources...
9273 23:07:13.729791 Root Device read_resources bus 0 link: 0
9274 23:07:13.730375 DRAM rank0 size:0x100000000,
9275 23:07:13.732959 DRAM rank1 size=0x100000000
9276 23:07:13.736287 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9277 23:07:13.739675 CPU: 00 missing read_resources
9278 23:07:13.746933 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9279 23:07:13.750381 Root Device read_resources bus 0 link: 0 done
9280 23:07:13.751008 Done reading resources.
9281 23:07:13.756194 Show resources in subtree (Root Device)...After reading.
9282 23:07:13.759470 Root Device child on link 0 CPU_CLUSTER: 0
9283 23:07:13.763212 CPU_CLUSTER: 0 child on link 0 CPU: 00
9284 23:07:13.772779 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9285 23:07:13.773422 CPU: 00
9286 23:07:13.775848 Root Device assign_resources, bus 0 link: 0
9287 23:07:13.779356 CPU_CLUSTER: 0 missing set_resources
9288 23:07:13.785735 Root Device assign_resources, bus 0 link: 0 done
9289 23:07:13.786216 Done setting resources.
9290 23:07:13.792548 Show resources in subtree (Root Device)...After assigning values.
9291 23:07:13.795603 Root Device child on link 0 CPU_CLUSTER: 0
9292 23:07:13.798950 CPU_CLUSTER: 0 child on link 0 CPU: 00
9293 23:07:13.808817 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9294 23:07:13.809027 CPU: 00
9295 23:07:13.812093 Done allocating resources.
9296 23:07:13.818559 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9297 23:07:13.818704 Enabling resources...
9298 23:07:13.818817 done.
9299 23:07:13.825421 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9300 23:07:13.825534 Initializing devices...
9301 23:07:13.828507 Root Device init
9302 23:07:13.828617 init hardware done!
9303 23:07:13.832062 0x00000018: ctrlr->caps
9304 23:07:13.835063 52.000 MHz: ctrlr->f_max
9305 23:07:13.835160 0.400 MHz: ctrlr->f_min
9306 23:07:13.838328 0x40ff8080: ctrlr->voltages
9307 23:07:13.842197 sclk: 390625
9308 23:07:13.842283 Bus Width = 1
9309 23:07:13.842349 sclk: 390625
9310 23:07:13.845121 Bus Width = 1
9311 23:07:13.845205 Early init status = 3
9312 23:07:13.851816 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9313 23:07:13.854948 in-header: 03 fc 00 00 01 00 00 00
9314 23:07:13.855035 in-data: 00
9315 23:07:13.861892 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9316 23:07:13.865774 in-header: 03 fd 00 00 00 00 00 00
9317 23:07:13.868745 in-data:
9318 23:07:13.871809 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9319 23:07:13.875957 in-header: 03 fc 00 00 01 00 00 00
9320 23:07:13.879638 in-data: 00
9321 23:07:13.882636 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9322 23:07:13.888387 in-header: 03 fd 00 00 00 00 00 00
9323 23:07:13.891640 in-data:
9324 23:07:13.894678 [SSUSB] Setting up USB HOST controller...
9325 23:07:13.898795 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9326 23:07:13.901524 [SSUSB] phy power-on done.
9327 23:07:13.905184 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9328 23:07:13.911212 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9329 23:07:13.914619 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9330 23:07:13.921322 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9331 23:07:13.927904 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9332 23:07:13.934894 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9333 23:07:13.941137 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9334 23:07:13.947743 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9335 23:07:13.951298 SPM: binary array size = 0x9dc
9336 23:07:13.954257 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9337 23:07:13.961041 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9338 23:07:13.967686 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9339 23:07:13.974320 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9340 23:07:13.977508 configure_display: Starting display init
9341 23:07:14.011326 anx7625_power_on_init: Init interface.
9342 23:07:14.015012 anx7625_disable_pd_protocol: Disabled PD feature.
9343 23:07:14.017936 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9344 23:07:14.046119 anx7625_start_dp_work: Secure OCM version=00
9345 23:07:14.049097 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9346 23:07:14.063748 sp_tx_get_edid_block: EDID Block = 1
9347 23:07:14.166672 Extracted contents:
9348 23:07:14.169826 header: 00 ff ff ff ff ff ff 00
9349 23:07:14.173143 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9350 23:07:14.176395 version: 01 04
9351 23:07:14.179542 basic params: 95 1f 11 78 0a
9352 23:07:14.183038 chroma info: 76 90 94 55 54 90 27 21 50 54
9353 23:07:14.186351 established: 00 00 00
9354 23:07:14.193066 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9355 23:07:14.196800 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9356 23:07:14.202937 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9357 23:07:14.209870 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9358 23:07:14.216392 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9359 23:07:14.219613 extensions: 00
9360 23:07:14.219698 checksum: fb
9361 23:07:14.219762
9362 23:07:14.222941 Manufacturer: IVO Model 57d Serial Number 0
9363 23:07:14.226310 Made week 0 of 2020
9364 23:07:14.226415 EDID version: 1.4
9365 23:07:14.230336 Digital display
9366 23:07:14.233148 6 bits per primary color channel
9367 23:07:14.233230 DisplayPort interface
9368 23:07:14.236218 Maximum image size: 31 cm x 17 cm
9369 23:07:14.239691 Gamma: 220%
9370 23:07:14.239772 Check DPMS levels
9371 23:07:14.242957 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9372 23:07:14.246357 First detailed timing is preferred timing
9373 23:07:14.250033 Established timings supported:
9374 23:07:14.253046 Standard timings supported:
9375 23:07:14.253127 Detailed timings
9376 23:07:14.259355 Hex of detail: 383680a07038204018303c0035ae10000019
9377 23:07:14.262647 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9378 23:07:14.269262 0780 0798 07c8 0820 hborder 0
9379 23:07:14.273004 0438 043b 0447 0458 vborder 0
9380 23:07:14.276002 -hsync -vsync
9381 23:07:14.276094 Did detailed timing
9382 23:07:14.279536 Hex of detail: 000000000000000000000000000000000000
9383 23:07:14.282585 Manufacturer-specified data, tag 0
9384 23:07:14.289382 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9385 23:07:14.289470 ASCII string: InfoVision
9386 23:07:14.296034 Hex of detail: 000000fe00523134304e574635205248200a
9387 23:07:14.299360 ASCII string: R140NWF5 RH
9388 23:07:14.299443 Checksum
9389 23:07:14.299507 Checksum: 0xfb (valid)
9390 23:07:14.306144 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9391 23:07:14.309275 DSI data_rate: 832800000 bps
9392 23:07:14.312413 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9393 23:07:14.319182 anx7625_parse_edid: pixelclock(138800).
9394 23:07:14.322330 hactive(1920), hsync(48), hfp(24), hbp(88)
9395 23:07:14.325786 vactive(1080), vsync(12), vfp(3), vbp(17)
9396 23:07:14.329113 anx7625_dsi_config: config dsi.
9397 23:07:14.335429 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9398 23:07:14.348357 anx7625_dsi_config: success to config DSI
9399 23:07:14.352172 anx7625_dp_start: MIPI phy setup OK.
9400 23:07:14.355244 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9401 23:07:14.359217 mtk_ddp_mode_set invalid vrefresh 60
9402 23:07:14.361680 main_disp_path_setup
9403 23:07:14.361762 ovl_layer_smi_id_en
9404 23:07:14.365195 ovl_layer_smi_id_en
9405 23:07:14.365277 ccorr_config
9406 23:07:14.365342 aal_config
9407 23:07:14.368434 gamma_config
9408 23:07:14.368515 postmask_config
9409 23:07:14.372026 dither_config
9410 23:07:14.374987 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9411 23:07:14.381741 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9412 23:07:14.384956 Root Device init finished in 553 msecs
9413 23:07:14.388523 CPU_CLUSTER: 0 init
9414 23:07:14.395245 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9415 23:07:14.398573 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9416 23:07:14.402021 APU_MBOX 0x190000b0 = 0x10001
9417 23:07:14.405033 APU_MBOX 0x190001b0 = 0x10001
9418 23:07:14.408405 APU_MBOX 0x190005b0 = 0x10001
9419 23:07:14.411502 APU_MBOX 0x190006b0 = 0x10001
9420 23:07:14.414880 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9421 23:07:14.427661 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9422 23:07:14.440221 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9423 23:07:14.446303 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9424 23:07:14.458347 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9425 23:07:14.467659 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9426 23:07:14.470777 CPU_CLUSTER: 0 init finished in 81 msecs
9427 23:07:14.474205 Devices initialized
9428 23:07:14.477366 Show all devs... After init.
9429 23:07:14.477658 Root Device: enabled 1
9430 23:07:14.480823 CPU_CLUSTER: 0: enabled 1
9431 23:07:14.484560 CPU: 00: enabled 1
9432 23:07:14.487717 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9433 23:07:14.490897 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9434 23:07:14.494526 ELOG: NV offset 0x57f000 size 0x1000
9435 23:07:14.500636 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9436 23:07:14.507760 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9437 23:07:14.510517 ELOG: Event(17) added with size 13 at 2023-12-01 23:06:40 UTC
9438 23:07:14.517473 out: cmd=0x121: 03 db 21 01 00 00 00 00
9439 23:07:14.520735 in-header: 03 20 00 00 2c 00 00 00
9440 23:07:14.530269 in-data: 3f 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9441 23:07:14.536861 ELOG: Event(A1) added with size 10 at 2023-12-01 23:06:40 UTC
9442 23:07:14.543531 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9443 23:07:14.550150 ELOG: Event(A0) added with size 9 at 2023-12-01 23:06:40 UTC
9444 23:07:14.553542 elog_add_boot_reason: Logged dev mode boot
9445 23:07:14.557515 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9446 23:07:14.560549 Finalize devices...
9447 23:07:14.563752 Devices finalized
9448 23:07:14.566979 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9449 23:07:14.570232 Writing coreboot table at 0xffe64000
9450 23:07:14.573518 0. 000000000010a000-0000000000113fff: RAMSTAGE
9451 23:07:14.577136 1. 0000000040000000-00000000400fffff: RAM
9452 23:07:14.583455 2. 0000000040100000-000000004032afff: RAMSTAGE
9453 23:07:14.586871 3. 000000004032b000-00000000545fffff: RAM
9454 23:07:14.590179 4. 0000000054600000-000000005465ffff: BL31
9455 23:07:14.593274 5. 0000000054660000-00000000ffe63fff: RAM
9456 23:07:14.600283 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9457 23:07:14.603911 7. 0000000100000000-000000023fffffff: RAM
9458 23:07:14.607696 Passing 5 GPIOs to payload:
9459 23:07:14.610379 NAME | PORT | POLARITY | VALUE
9460 23:07:14.613434 EC in RW | 0x000000aa | low | undefined
9461 23:07:14.620137 EC interrupt | 0x00000005 | low | undefined
9462 23:07:14.623289 TPM interrupt | 0x000000ab | high | undefined
9463 23:07:14.630070 SD card detect | 0x00000011 | high | undefined
9464 23:07:14.633218 speaker enable | 0x00000093 | high | undefined
9465 23:07:14.636472 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9466 23:07:14.639999 in-header: 03 f9 00 00 02 00 00 00
9467 23:07:14.643268 in-data: 02 00
9468 23:07:14.643645 ADC[4]: Raw value=900663 ID=7
9469 23:07:14.646551 ADC[3]: Raw value=213179 ID=1
9470 23:07:14.650136 RAM Code: 0x71
9471 23:07:14.650588 ADC[6]: Raw value=74502 ID=0
9472 23:07:14.653659 ADC[5]: Raw value=212441 ID=1
9473 23:07:14.657132 SKU Code: 0x1
9474 23:07:14.660179 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 844e
9475 23:07:14.663400 coreboot table: 964 bytes.
9476 23:07:14.666784 IMD ROOT 0. 0xfffff000 0x00001000
9477 23:07:14.670134 IMD SMALL 1. 0xffffe000 0x00001000
9478 23:07:14.673777 RO MCACHE 2. 0xffffc000 0x00001104
9479 23:07:14.676776 CONSOLE 3. 0xfff7c000 0x00080000
9480 23:07:14.679839 FMAP 4. 0xfff7b000 0x00000452
9481 23:07:14.683538 TIME STAMP 5. 0xfff7a000 0x00000910
9482 23:07:14.686630 VBOOT WORK 6. 0xfff66000 0x00014000
9483 23:07:14.690297 RAMOOPS 7. 0xffe66000 0x00100000
9484 23:07:14.693289 COREBOOT 8. 0xffe64000 0x00002000
9485 23:07:14.693862 IMD small region:
9486 23:07:14.696556 IMD ROOT 0. 0xffffec00 0x00000400
9487 23:07:14.703219 VPD 1. 0xffffeb80 0x0000006c
9488 23:07:14.707117 MMC STATUS 2. 0xffffeb60 0x00000004
9489 23:07:14.709694 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9490 23:07:14.713832 Probing TPM: done!
9491 23:07:14.716765 Connected to device vid:did:rid of 1ae0:0028:00
9492 23:07:14.726616 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9493 23:07:14.730341 Initialized TPM device CR50 revision 0
9494 23:07:14.733950 Checking cr50 for pending updates
9495 23:07:14.737418 Reading cr50 TPM mode
9496 23:07:14.746131 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9497 23:07:14.752793 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9498 23:07:14.793041 read SPI 0x3990ec 0x4f1b0: 34846 us, 9298 KB/s, 74.384 Mbps
9499 23:07:14.796074 Checking segment from ROM address 0x40100000
9500 23:07:14.799181 Checking segment from ROM address 0x4010001c
9501 23:07:14.806017 Loading segment from ROM address 0x40100000
9502 23:07:14.806584 code (compression=0)
9503 23:07:14.816116 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9504 23:07:14.822739 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9505 23:07:14.823259 it's not compressed!
9506 23:07:14.829213 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9507 23:07:14.832643 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9508 23:07:14.852989 Loading segment from ROM address 0x4010001c
9509 23:07:14.853512 Entry Point 0x80000000
9510 23:07:14.856304 Loaded segments
9511 23:07:14.859642 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9512 23:07:14.866555 Jumping to boot code at 0x80000000(0xffe64000)
9513 23:07:14.872992 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9514 23:07:14.879591 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9515 23:07:14.887381 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9516 23:07:14.890876 Checking segment from ROM address 0x40100000
9517 23:07:14.893959 Checking segment from ROM address 0x4010001c
9518 23:07:14.900914 Loading segment from ROM address 0x40100000
9519 23:07:14.901501 code (compression=1)
9520 23:07:14.907689 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9521 23:07:14.917645 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9522 23:07:14.918191 using LZMA
9523 23:07:14.925624 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9524 23:07:14.932330 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9525 23:07:14.935883 Loading segment from ROM address 0x4010001c
9526 23:07:14.936314 Entry Point 0x54601000
9527 23:07:14.939147 Loaded segments
9528 23:07:14.942181 NOTICE: MT8192 bl31_setup
9529 23:07:14.949756 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9530 23:07:14.953040 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9531 23:07:14.956333 WARNING: region 0:
9532 23:07:14.959488 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9533 23:07:14.959917 WARNING: region 1:
9534 23:07:14.966195 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9535 23:07:14.969236 WARNING: region 2:
9536 23:07:14.972936 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9537 23:07:14.976314 WARNING: region 3:
9538 23:07:14.979636 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9539 23:07:14.982724 WARNING: region 4:
9540 23:07:14.986231 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9541 23:07:14.989864 WARNING: region 5:
9542 23:07:14.993513 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9543 23:07:14.996290 WARNING: region 6:
9544 23:07:14.999395 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9545 23:07:14.999831 WARNING: region 7:
9546 23:07:15.006303 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9547 23:07:15.012903 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9548 23:07:15.016464 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9549 23:07:15.019485 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9550 23:07:15.026046 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9551 23:07:15.029481 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9552 23:07:15.032662 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9553 23:07:15.039272 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9554 23:07:15.043073 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9555 23:07:15.046272 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9556 23:07:15.053510 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9557 23:07:15.056152 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9558 23:07:15.063094 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9559 23:07:15.066158 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9560 23:07:15.069872 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9561 23:07:15.076524 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9562 23:07:15.079665 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9563 23:07:15.083218 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9564 23:07:15.090068 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9565 23:07:15.093382 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9566 23:07:15.096845 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9567 23:07:15.103362 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9568 23:07:15.106922 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9569 23:07:15.112898 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9570 23:07:15.116636 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9571 23:07:15.123316 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9572 23:07:15.126748 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9573 23:07:15.129901 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9574 23:07:15.136972 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9575 23:07:15.139506 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9576 23:07:15.142912 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9577 23:07:15.149860 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9578 23:07:15.153165 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9579 23:07:15.156669 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9580 23:07:15.163160 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9581 23:07:15.166675 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9582 23:07:15.169693 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9583 23:07:15.173000 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9584 23:07:15.179953 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9585 23:07:15.183272 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9586 23:07:15.186652 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9587 23:07:15.189934 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9588 23:07:15.196568 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9589 23:07:15.199960 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9590 23:07:15.203537 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9591 23:07:15.207131 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9592 23:07:15.213153 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9593 23:07:15.216283 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9594 23:07:15.219759 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9595 23:07:15.226636 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9596 23:07:15.230002 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9597 23:07:15.233069 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9598 23:07:15.239771 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9599 23:07:15.243209 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9600 23:07:15.249777 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9601 23:07:15.253017 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9602 23:07:15.260344 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9603 23:07:15.263286 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9604 23:07:15.266792 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9605 23:07:15.273717 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9606 23:07:15.276762 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9607 23:07:15.283244 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9608 23:07:15.286512 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9609 23:07:15.293538 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9610 23:07:15.296700 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9611 23:07:15.300254 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9612 23:07:15.307251 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9613 23:07:15.310869 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9614 23:07:15.316661 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9615 23:07:15.320547 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9616 23:07:15.327011 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9617 23:07:15.330329 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9618 23:07:15.333973 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9619 23:07:15.340096 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9620 23:07:15.343732 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9621 23:07:15.350304 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9622 23:07:15.353626 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9623 23:07:15.360405 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9624 23:07:15.363714 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9625 23:07:15.367146 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9626 23:07:15.373621 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9627 23:07:15.377165 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9628 23:07:15.383539 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9629 23:07:15.386906 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9630 23:07:15.393553 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9631 23:07:15.396687 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9632 23:07:15.400249 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9633 23:07:15.406887 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9634 23:07:15.410321 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9635 23:07:15.416954 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9636 23:07:15.419940 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9637 23:07:15.426672 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9638 23:07:15.430101 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9639 23:07:15.436760 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9640 23:07:15.440149 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9641 23:07:15.443291 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9642 23:07:15.450306 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9643 23:07:15.453171 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9644 23:07:15.456176 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9645 23:07:15.463807 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9646 23:07:15.466450 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9647 23:07:15.470323 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9648 23:07:15.476384 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9649 23:07:15.479644 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9650 23:07:15.483003 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9651 23:07:15.489566 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9652 23:07:15.493116 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9653 23:07:15.500122 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9654 23:07:15.503029 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9655 23:07:15.506350 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9656 23:07:15.513359 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9657 23:07:15.516608 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9658 23:07:15.519813 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9659 23:07:15.526750 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9660 23:07:15.530345 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9661 23:07:15.536689 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9662 23:07:15.540081 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9663 23:07:15.543056 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9664 23:07:15.550371 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9665 23:07:15.553569 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9666 23:07:15.557059 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9667 23:07:15.559977 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9668 23:07:15.566584 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9669 23:07:15.570338 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9670 23:07:15.573357 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9671 23:07:15.576701 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9672 23:07:15.583281 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9673 23:07:15.586940 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9674 23:07:15.593359 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9675 23:07:15.596877 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9676 23:07:15.600429 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9677 23:07:15.607046 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9678 23:07:15.610138 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9679 23:07:15.616773 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9680 23:07:15.620412 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9681 23:07:15.623205 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9682 23:07:15.629962 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9683 23:07:15.633337 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9684 23:07:15.636713 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9685 23:07:15.643210 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9686 23:07:15.646895 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9687 23:07:15.653399 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9688 23:07:15.656921 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9689 23:07:15.660486 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9690 23:07:15.667448 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9691 23:07:15.670150 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9692 23:07:15.677146 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9693 23:07:15.679903 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9694 23:07:15.683712 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9695 23:07:15.690415 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9696 23:07:15.693729 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9697 23:07:15.699998 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9698 23:07:15.703298 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9699 23:07:15.706757 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9700 23:07:15.713310 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9701 23:07:15.716865 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9702 23:07:15.720177 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9703 23:07:15.726613 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9704 23:07:15.730175 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9705 23:07:15.736459 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9706 23:07:15.739870 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9707 23:07:15.743089 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9708 23:07:15.749789 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9709 23:07:15.753022 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9710 23:07:15.760012 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9711 23:07:15.762921 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9712 23:07:15.767259 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9713 23:07:15.773073 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9714 23:07:15.776256 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9715 23:07:15.783089 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9716 23:07:15.786062 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9717 23:07:15.789657 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9718 23:07:15.796353 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9719 23:07:15.799273 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9720 23:07:15.806330 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9721 23:07:15.809553 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9722 23:07:15.812484 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9723 23:07:15.819555 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9724 23:07:15.822373 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9725 23:07:15.829349 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9726 23:07:15.832351 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9727 23:07:15.835968 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9728 23:07:15.843196 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9729 23:07:15.845783 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9730 23:07:15.849200 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9731 23:07:15.855846 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9732 23:07:15.858916 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9733 23:07:15.865929 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9734 23:07:15.869231 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9735 23:07:15.872186 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9736 23:07:15.879203 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9737 23:07:15.882057 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9738 23:07:15.889535 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9739 23:07:15.892425 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9740 23:07:15.895643 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9741 23:07:15.902621 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9742 23:07:15.905713 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9743 23:07:15.912553 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9744 23:07:15.915544 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9745 23:07:15.922252 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9746 23:07:15.925444 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9747 23:07:15.928855 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9748 23:07:15.935440 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9749 23:07:15.938854 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9750 23:07:15.945601 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9751 23:07:15.949055 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9752 23:07:15.955119 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9753 23:07:15.958957 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9754 23:07:15.962028 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9755 23:07:15.969422 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9756 23:07:15.971661 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9757 23:07:15.978731 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9758 23:07:15.981977 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9759 23:07:15.988606 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9760 23:07:15.991953 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9761 23:07:15.995227 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9762 23:07:16.001886 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9763 23:07:16.005099 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9764 23:07:16.011851 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9765 23:07:16.015129 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9766 23:07:16.018333 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9767 23:07:16.024903 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9768 23:07:16.027977 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9769 23:07:16.034713 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9770 23:07:16.037836 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9771 23:07:16.044518 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9772 23:07:16.047601 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9773 23:07:16.051631 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9774 23:07:16.057617 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9775 23:07:16.061474 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9776 23:07:16.064582 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9777 23:07:16.071318 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9778 23:07:16.074245 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9779 23:07:16.077674 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9780 23:07:16.081213 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9781 23:07:16.087650 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9782 23:07:16.091543 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9783 23:07:16.098052 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9784 23:07:16.100883 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9785 23:07:16.104725 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9786 23:07:16.111194 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9787 23:07:16.114724 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9788 23:07:16.117858 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9789 23:07:16.124643 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9790 23:07:16.127896 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9791 23:07:16.131174 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9792 23:07:16.137378 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9793 23:07:16.141083 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9794 23:07:16.147470 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9795 23:07:16.151069 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9796 23:07:16.154648 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9797 23:07:16.160697 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9798 23:07:16.164291 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9799 23:07:16.167447 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9800 23:07:16.173969 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9801 23:07:16.177138 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9802 23:07:16.180318 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9803 23:07:16.187168 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9804 23:07:16.190799 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9805 23:07:16.194335 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9806 23:07:16.200838 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9807 23:07:16.204017 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9808 23:07:16.210584 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9809 23:07:16.214021 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9810 23:07:16.217243 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9811 23:07:16.224138 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9812 23:07:16.227406 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9813 23:07:16.230768 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9814 23:07:16.236876 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9815 23:07:16.240237 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9816 23:07:16.243578 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9817 23:07:16.250557 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9818 23:07:16.254103 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9819 23:07:16.256863 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9820 23:07:16.261354 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9821 23:07:16.266999 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9822 23:07:16.270356 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9823 23:07:16.273559 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9824 23:07:16.276710 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9825 23:07:16.283675 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9826 23:07:16.286546 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9827 23:07:16.289855 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9828 23:07:16.293049 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9829 23:07:16.299945 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9830 23:07:16.303259 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9831 23:07:16.310162 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9832 23:07:16.313659 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9833 23:07:16.320100 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9834 23:07:16.323313 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9835 23:07:16.326368 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9836 23:07:16.333059 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9837 23:07:16.336744 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9838 23:07:16.339756 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9839 23:07:16.346644 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9840 23:07:16.350069 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9841 23:07:16.356548 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9842 23:07:16.359875 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9843 23:07:16.366621 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9844 23:07:16.369623 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9845 23:07:16.372989 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9846 23:07:16.379413 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9847 23:07:16.382792 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9848 23:07:16.389683 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9849 23:07:16.392774 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9850 23:07:16.399231 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9851 23:07:16.402638 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9852 23:07:16.406447 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9853 23:07:16.412792 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9854 23:07:16.415714 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9855 23:07:16.423022 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9856 23:07:16.426067 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9857 23:07:16.429448 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9858 23:07:16.435448 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9859 23:07:16.439077 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9860 23:07:16.445626 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9861 23:07:16.449154 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9862 23:07:16.452158 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9863 23:07:16.459332 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9864 23:07:16.462269 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9865 23:07:16.469397 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9866 23:07:16.472442 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9867 23:07:16.478550 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9868 23:07:16.482173 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9869 23:07:16.485305 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9870 23:07:16.491958 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9871 23:07:16.495195 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9872 23:07:16.501658 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9873 23:07:16.504956 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9874 23:07:16.508856 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9875 23:07:16.514953 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9876 23:07:16.518441 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9877 23:07:16.524882 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9878 23:07:16.528082 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9879 23:07:16.531507 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9880 23:07:16.538158 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9881 23:07:16.541424 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9882 23:07:16.548950 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9883 23:07:16.551673 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9884 23:07:16.555075 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9885 23:07:16.561495 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9886 23:07:16.564994 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9887 23:07:16.571154 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9888 23:07:16.574893 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9889 23:07:16.581336 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9890 23:07:16.584568 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9891 23:07:16.591191 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9892 23:07:16.594733 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9893 23:07:16.597567 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9894 23:07:16.605096 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9895 23:07:16.607251 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9896 23:07:16.613940 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9897 23:07:16.617689 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9898 23:07:16.620742 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9899 23:07:16.627893 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9900 23:07:16.630651 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9901 23:07:16.637401 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9902 23:07:16.640904 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9903 23:07:16.643750 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9904 23:07:16.650574 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9905 23:07:16.654259 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9906 23:07:16.660763 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9907 23:07:16.664084 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9908 23:07:16.670648 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9909 23:07:16.673680 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9910 23:07:16.680436 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9911 23:07:16.683676 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9912 23:07:16.686870 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9913 23:07:16.693736 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9914 23:07:16.696909 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9915 23:07:16.703567 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9916 23:07:16.707017 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9917 23:07:16.713196 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9918 23:07:16.716787 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9919 23:07:16.723455 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9920 23:07:16.726699 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9921 23:07:16.730116 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9922 23:07:16.736496 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9923 23:07:16.740103 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9924 23:07:16.746754 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9925 23:07:16.750248 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9926 23:07:16.757242 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9927 23:07:16.760307 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9928 23:07:16.763089 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9929 23:07:16.770628 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9930 23:07:16.773363 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9931 23:07:16.780039 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9932 23:07:16.783199 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9933 23:07:16.790001 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9934 23:07:16.793412 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9935 23:07:16.796276 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9936 23:07:16.803037 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9937 23:07:16.806737 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9938 23:07:16.813466 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9939 23:07:16.816694 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9940 23:07:16.823054 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9941 23:07:16.826280 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9942 23:07:16.829907 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9943 23:07:16.836042 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9944 23:07:16.839424 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9945 23:07:16.846014 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9946 23:07:16.849780 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9947 23:07:16.856849 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9948 23:07:16.859551 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9949 23:07:16.862999 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9950 23:07:16.869647 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9951 23:07:16.872526 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9952 23:07:16.879428 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9953 23:07:16.882918 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9954 23:07:16.889923 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9955 23:07:16.892767 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9956 23:07:16.899599 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9957 23:07:16.903019 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9958 23:07:16.909663 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9959 23:07:16.912913 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9960 23:07:16.920342 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9961 23:07:16.922731 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9962 23:07:16.929434 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9963 23:07:16.932916 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9964 23:07:16.938891 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9965 23:07:16.942117 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9966 23:07:16.945739 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9967 23:07:16.952246 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9968 23:07:16.955461 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9969 23:07:16.962257 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9970 23:07:16.966172 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9971 23:07:16.972438 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9972 23:07:16.978825 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9973 23:07:16.982545 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9974 23:07:16.989231 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9975 23:07:16.992490 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9976 23:07:16.998977 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9977 23:07:17.002767 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9978 23:07:17.008440 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9979 23:07:17.012014 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9980 23:07:17.018612 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9981 23:07:17.022079 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9982 23:07:17.022698 INFO: [APUAPC] vio 0
9983 23:07:17.029654 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9984 23:07:17.032925 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9985 23:07:17.035890 INFO: [APUAPC] D0_APC_0: 0x400510
9986 23:07:17.039037 INFO: [APUAPC] D0_APC_1: 0x0
9987 23:07:17.042598 INFO: [APUAPC] D0_APC_2: 0x1540
9988 23:07:17.046219 INFO: [APUAPC] D0_APC_3: 0x0
9989 23:07:17.049384 INFO: [APUAPC] D1_APC_0: 0xffffffff
9990 23:07:17.053097 INFO: [APUAPC] D1_APC_1: 0xffffffff
9991 23:07:17.056371 INFO: [APUAPC] D1_APC_2: 0x3fffff
9992 23:07:17.059388 INFO: [APUAPC] D1_APC_3: 0x0
9993 23:07:17.062444 INFO: [APUAPC] D2_APC_0: 0xffffffff
9994 23:07:17.066052 INFO: [APUAPC] D2_APC_1: 0xffffffff
9995 23:07:17.069376 INFO: [APUAPC] D2_APC_2: 0x3fffff
9996 23:07:17.072801 INFO: [APUAPC] D2_APC_3: 0x0
9997 23:07:17.075764 INFO: [APUAPC] D3_APC_0: 0xffffffff
9998 23:07:17.079259 INFO: [APUAPC] D3_APC_1: 0xffffffff
9999 23:07:17.082486 INFO: [APUAPC] D3_APC_2: 0x3fffff
10000 23:07:17.082962 INFO: [APUAPC] D3_APC_3: 0x0
10001 23:07:17.085814 INFO: [APUAPC] D4_APC_0: 0xffffffff
10002 23:07:17.093302 INFO: [APUAPC] D4_APC_1: 0xffffffff
10003 23:07:17.095935 INFO: [APUAPC] D4_APC_2: 0x3fffff
10004 23:07:17.096415 INFO: [APUAPC] D4_APC_3: 0x0
10005 23:07:17.098946 INFO: [APUAPC] D5_APC_0: 0xffffffff
10006 23:07:17.102985 INFO: [APUAPC] D5_APC_1: 0xffffffff
10007 23:07:17.105444 INFO: [APUAPC] D5_APC_2: 0x3fffff
10008 23:07:17.109817 INFO: [APUAPC] D5_APC_3: 0x0
10009 23:07:17.112595 INFO: [APUAPC] D6_APC_0: 0xffffffff
10010 23:07:17.115530 INFO: [APUAPC] D6_APC_1: 0xffffffff
10011 23:07:17.118927 INFO: [APUAPC] D6_APC_2: 0x3fffff
10012 23:07:17.122360 INFO: [APUAPC] D6_APC_3: 0x0
10013 23:07:17.125793 INFO: [APUAPC] D7_APC_0: 0xffffffff
10014 23:07:17.129334 INFO: [APUAPC] D7_APC_1: 0xffffffff
10015 23:07:17.132189 INFO: [APUAPC] D7_APC_2: 0x3fffff
10016 23:07:17.135755 INFO: [APUAPC] D7_APC_3: 0x0
10017 23:07:17.138924 INFO: [APUAPC] D8_APC_0: 0xffffffff
10018 23:07:17.142157 INFO: [APUAPC] D8_APC_1: 0xffffffff
10019 23:07:17.145868 INFO: [APUAPC] D8_APC_2: 0x3fffff
10020 23:07:17.148991 INFO: [APUAPC] D8_APC_3: 0x0
10021 23:07:17.152278 INFO: [APUAPC] D9_APC_0: 0xffffffff
10022 23:07:17.155100 INFO: [APUAPC] D9_APC_1: 0xffffffff
10023 23:07:17.158355 INFO: [APUAPC] D9_APC_2: 0x3fffff
10024 23:07:17.162027 INFO: [APUAPC] D9_APC_3: 0x0
10025 23:07:17.165109 INFO: [APUAPC] D10_APC_0: 0xffffffff
10026 23:07:17.168509 INFO: [APUAPC] D10_APC_1: 0xffffffff
10027 23:07:17.171812 INFO: [APUAPC] D10_APC_2: 0x3fffff
10028 23:07:17.174905 INFO: [APUAPC] D10_APC_3: 0x0
10029 23:07:17.178705 INFO: [APUAPC] D11_APC_0: 0xffffffff
10030 23:07:17.181905 INFO: [APUAPC] D11_APC_1: 0xffffffff
10031 23:07:17.185214 INFO: [APUAPC] D11_APC_2: 0x3fffff
10032 23:07:17.188719 INFO: [APUAPC] D11_APC_3: 0x0
10033 23:07:17.191685 INFO: [APUAPC] D12_APC_0: 0xffffffff
10034 23:07:17.194767 INFO: [APUAPC] D12_APC_1: 0xffffffff
10035 23:07:17.198350 INFO: [APUAPC] D12_APC_2: 0x3fffff
10036 23:07:17.202041 INFO: [APUAPC] D12_APC_3: 0x0
10037 23:07:17.204944 INFO: [APUAPC] D13_APC_0: 0xffffffff
10038 23:07:17.208277 INFO: [APUAPC] D13_APC_1: 0xffffffff
10039 23:07:17.211562 INFO: [APUAPC] D13_APC_2: 0x3fffff
10040 23:07:17.214748 INFO: [APUAPC] D13_APC_3: 0x0
10041 23:07:17.218251 INFO: [APUAPC] D14_APC_0: 0xffffffff
10042 23:07:17.221212 INFO: [APUAPC] D14_APC_1: 0xffffffff
10043 23:07:17.224974 INFO: [APUAPC] D14_APC_2: 0x3fffff
10044 23:07:17.228026 INFO: [APUAPC] D14_APC_3: 0x0
10045 23:07:17.231619 INFO: [APUAPC] D15_APC_0: 0xffffffff
10046 23:07:17.234757 INFO: [APUAPC] D15_APC_1: 0xffffffff
10047 23:07:17.238418 INFO: [APUAPC] D15_APC_2: 0x3fffff
10048 23:07:17.241054 INFO: [APUAPC] D15_APC_3: 0x0
10049 23:07:17.244446 INFO: [APUAPC] APC_CON: 0x4
10050 23:07:17.247862 INFO: [NOCDAPC] D0_APC_0: 0x0
10051 23:07:17.250964 INFO: [NOCDAPC] D0_APC_1: 0x0
10052 23:07:17.254510 INFO: [NOCDAPC] D1_APC_0: 0x0
10053 23:07:17.257667 INFO: [NOCDAPC] D1_APC_1: 0xfff
10054 23:07:17.260884 INFO: [NOCDAPC] D2_APC_0: 0x0
10055 23:07:17.264008 INFO: [NOCDAPC] D2_APC_1: 0xfff
10056 23:07:17.267340 INFO: [NOCDAPC] D3_APC_0: 0x0
10057 23:07:17.270867 INFO: [NOCDAPC] D3_APC_1: 0xfff
10058 23:07:17.271449 INFO: [NOCDAPC] D4_APC_0: 0x0
10059 23:07:17.273869 INFO: [NOCDAPC] D4_APC_1: 0xfff
10060 23:07:17.277347 INFO: [NOCDAPC] D5_APC_0: 0x0
10061 23:07:17.280643 INFO: [NOCDAPC] D5_APC_1: 0xfff
10062 23:07:17.283983 INFO: [NOCDAPC] D6_APC_0: 0x0
10063 23:07:17.288033 INFO: [NOCDAPC] D6_APC_1: 0xfff
10064 23:07:17.290497 INFO: [NOCDAPC] D7_APC_0: 0x0
10065 23:07:17.294069 INFO: [NOCDAPC] D7_APC_1: 0xfff
10066 23:07:17.297221 INFO: [NOCDAPC] D8_APC_0: 0x0
10067 23:07:17.300738 INFO: [NOCDAPC] D8_APC_1: 0xfff
10068 23:07:17.301320 INFO: [NOCDAPC] D9_APC_0: 0x0
10069 23:07:17.303771 INFO: [NOCDAPC] D9_APC_1: 0xfff
10070 23:07:17.307586 INFO: [NOCDAPC] D10_APC_0: 0x0
10071 23:07:17.310821 INFO: [NOCDAPC] D10_APC_1: 0xfff
10072 23:07:17.314128 INFO: [NOCDAPC] D11_APC_0: 0x0
10073 23:07:17.317253 INFO: [NOCDAPC] D11_APC_1: 0xfff
10074 23:07:17.320774 INFO: [NOCDAPC] D12_APC_0: 0x0
10075 23:07:17.324016 INFO: [NOCDAPC] D12_APC_1: 0xfff
10076 23:07:17.327190 INFO: [NOCDAPC] D13_APC_0: 0x0
10077 23:07:17.331057 INFO: [NOCDAPC] D13_APC_1: 0xfff
10078 23:07:17.333794 INFO: [NOCDAPC] D14_APC_0: 0x0
10079 23:07:17.337291 INFO: [NOCDAPC] D14_APC_1: 0xfff
10080 23:07:17.339986 INFO: [NOCDAPC] D15_APC_0: 0x0
10081 23:07:17.343593 INFO: [NOCDAPC] D15_APC_1: 0xfff
10082 23:07:17.346779 INFO: [NOCDAPC] APC_CON: 0x4
10083 23:07:17.350579 INFO: [APUAPC] set_apusys_apc done
10084 23:07:17.351062 INFO: [DEVAPC] devapc_init done
10085 23:07:17.357187 INFO: GICv3 without legacy support detected.
10086 23:07:17.360593 INFO: ARM GICv3 driver initialized in EL3
10087 23:07:17.363595 INFO: Maximum SPI INTID supported: 639
10088 23:07:17.366618 INFO: BL31: Initializing runtime services
10089 23:07:17.373083 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10090 23:07:17.376761 INFO: SPM: enable CPC mode
10091 23:07:17.380573 INFO: mcdi ready for mcusys-off-idle and system suspend
10092 23:07:17.386744 INFO: BL31: Preparing for EL3 exit to normal world
10093 23:07:17.389882 INFO: Entry point address = 0x80000000
10094 23:07:17.390363 INFO: SPSR = 0x8
10095 23:07:17.397633
10096 23:07:17.398211
10097 23:07:17.398668
10098 23:07:17.401137 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10099 23:07:17.401682 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10100 23:07:17.402147 Setting prompt string to ['asurada:']
10101 23:07:17.402623 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10102 23:07:17.403353 Starting depthcharge on Spherion...
10103 23:07:17.403739
10104 23:07:17.404180 Wipe memory regions:
10105 23:07:17.404535
10106 23:07:17.404930 [0x00000040000000, 0x00000054600000)
10107 23:07:17.526766
10108 23:07:17.527341 [0x00000054660000, 0x00000080000000)
10109 23:07:17.786787
10110 23:07:17.787357 [0x000000821a7280, 0x000000ffe64000)
10111 23:07:18.532067
10112 23:07:18.532639 [0x00000100000000, 0x00000240000000)
10113 23:07:20.421802
10114 23:07:20.425093 Initializing XHCI USB controller at 0x11200000.
10115 23:07:21.463906
10116 23:07:21.467046 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10117 23:07:21.467224
10118 23:07:21.467341
10119 23:07:21.467451
10120 23:07:21.467817 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10122 23:07:21.568481 asurada: tftpboot 192.168.201.1 12154437/tftp-deploy-jquy125z/kernel/image.itb 12154437/tftp-deploy-jquy125z/kernel/cmdline
10123 23:07:21.569208 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10124 23:07:21.569792 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10125 23:07:21.574647 tftpboot 192.168.201.1 12154437/tftp-deploy-jquy125z/kernel/image.itp-deploy-jquy125z/kernel/cmdline
10126 23:07:21.575189
10127 23:07:21.575678 Waiting for link
10128 23:07:21.734719
10129 23:07:21.735286 R8152: Initializing
10130 23:07:21.735656
10131 23:07:21.737806 Version 9 (ocp_data = 6010)
10132 23:07:21.738319
10133 23:07:21.741009 R8152: Done initializing
10134 23:07:21.741504
10135 23:07:21.741878 Adding net device
10136 23:07:23.623217
10137 23:07:23.623789 done.
10138 23:07:23.624169
10139 23:07:23.624518 MAC: 00:e0:4c:72:2d:d6
10140 23:07:23.624855
10141 23:07:23.625642 Sending DHCP discover... done.
10142 23:07:23.626043
10143 23:07:23.629161 Waiting for reply... done.
10144 23:07:23.629753
10145 23:07:23.632555 Sending DHCP request... done.
10146 23:07:23.633129
10147 23:07:23.633502 Waiting for reply... done.
10148 23:07:23.633844
10149 23:07:23.635796 My ip is 192.168.201.21
10150 23:07:23.636264
10151 23:07:23.639011 The DHCP server ip is 192.168.201.1
10152 23:07:23.639485
10153 23:07:23.642688 TFTP server IP predefined by user: 192.168.201.1
10154 23:07:23.643254
10155 23:07:23.648972 Bootfile predefined by user: 12154437/tftp-deploy-jquy125z/kernel/image.itb
10156 23:07:23.649532
10157 23:07:23.652345 Sending tftp read request... done.
10158 23:07:23.652822
10159 23:07:23.659185 Waiting for the transfer...
10160 23:07:23.659675
10161 23:07:24.016521 00000000 ################################################################
10162 23:07:24.016658
10163 23:07:24.274445 00080000 ################################################################
10164 23:07:24.274586
10165 23:07:24.519267 00100000 ################################################################
10166 23:07:24.519406
10167 23:07:24.762885 00180000 ################################################################
10168 23:07:24.763039
10169 23:07:25.006774 00200000 ################################################################
10170 23:07:25.006922
10171 23:07:25.250686 00280000 ################################################################
10172 23:07:25.250838
10173 23:07:25.521210 00300000 ################################################################
10174 23:07:25.521391
10175 23:07:25.765705 00380000 ################################################################
10176 23:07:25.765867
10177 23:07:26.014669 00400000 ################################################################
10178 23:07:26.014820
10179 23:07:26.270297 00480000 ################################################################
10180 23:07:26.270470
10181 23:07:26.522101 00500000 ################################################################
10182 23:07:26.522235
10183 23:07:26.786799 00580000 ################################################################
10184 23:07:26.786939
10185 23:07:27.050567 00600000 ################################################################
10186 23:07:27.050706
10187 23:07:27.308027 00680000 ################################################################
10188 23:07:27.308213
10189 23:07:27.564175 00700000 ################################################################
10190 23:07:27.564354
10191 23:07:27.809131 00780000 ################################################################
10192 23:07:27.809288
10193 23:07:28.059213 00800000 ################################################################
10194 23:07:28.059352
10195 23:07:28.314840 00880000 ################################################################
10196 23:07:28.314996
10197 23:07:28.575312 00900000 ################################################################
10198 23:07:28.575448
10199 23:07:28.854863 00980000 ################################################################
10200 23:07:28.854995
10201 23:07:29.121961 00a00000 ################################################################
10202 23:07:29.122098
10203 23:07:29.379495 00a80000 ################################################################
10204 23:07:29.379639
10205 23:07:29.671488 00b00000 ################################################################
10206 23:07:29.671635
10207 23:07:29.942569 00b80000 ################################################################
10208 23:07:29.942719
10209 23:07:30.234830 00c00000 ################################################################
10210 23:07:30.234978
10211 23:07:30.558356 00c80000 ################################################################
10212 23:07:30.558539
10213 23:07:30.894051 00d00000 ################################################################
10214 23:07:30.894594
10215 23:07:31.280379 00d80000 ################################################################
10216 23:07:31.280889
10217 23:07:31.594713 00e00000 ################################################################
10218 23:07:31.594861
10219 23:07:31.888498 00e80000 ################################################################
10220 23:07:31.888637
10221 23:07:32.176241 00f00000 ################################################################
10222 23:07:32.176377
10223 23:07:32.437064 00f80000 ################################################################
10224 23:07:32.437203
10225 23:07:32.722460 01000000 ################################################################
10226 23:07:32.722607
10227 23:07:33.019496 01080000 ################################################################
10228 23:07:33.019644
10229 23:07:33.308044 01100000 ################################################################
10230 23:07:33.308194
10231 23:07:33.589980 01180000 ################################################################
10232 23:07:33.590132
10233 23:07:33.868626 01200000 ################################################################
10234 23:07:33.868762
10235 23:07:34.137498 01280000 ################################################################
10236 23:07:34.137638
10237 23:07:34.390703 01300000 ################################################################
10238 23:07:34.390856
10239 23:07:34.636892 01380000 ################################################################
10240 23:07:34.637047
10241 23:07:34.898594 01400000 ################################################################
10242 23:07:34.898745
10243 23:07:35.144291 01480000 ################################################################
10244 23:07:35.144443
10245 23:07:35.393816 01500000 ################################################################
10246 23:07:35.393971
10247 23:07:35.643678 01580000 ################################################################
10248 23:07:35.643827
10249 23:07:35.888400 01600000 ################################################################
10250 23:07:35.888554
10251 23:07:36.135725 01680000 ################################################################
10252 23:07:36.135872
10253 23:07:36.384142 01700000 ################################################################
10254 23:07:36.384291
10255 23:07:36.631010 01780000 ################################################################
10256 23:07:36.631159
10257 23:07:36.878607 01800000 ################################################################
10258 23:07:36.878772
10259 23:07:37.142953 01880000 ################################################################
10260 23:07:37.143129
10261 23:07:37.418358 01900000 ################################################################
10262 23:07:37.418517
10263 23:07:37.691773 01980000 ################################################################
10264 23:07:37.691923
10265 23:07:37.966594 01a00000 ################################################################
10266 23:07:37.966747
10267 23:07:38.226334 01a80000 ################################################################
10268 23:07:38.226509
10269 23:07:38.489941 01b00000 ################################################################
10270 23:07:38.490096
10271 23:07:38.749496 01b80000 ################################################################
10272 23:07:38.749647
10273 23:07:38.998143 01c00000 ############################################################# done.
10274 23:07:38.998314
10275 23:07:39.001876 The bootfile was 29853326 bytes long.
10276 23:07:39.001955
10277 23:07:39.005236 Sending tftp read request... done.
10278 23:07:39.005341
10279 23:07:39.008257 Waiting for the transfer...
10280 23:07:39.008333
10281 23:07:39.008396 00000000 # done.
10282 23:07:39.008457
10283 23:07:39.018696 Command line loaded dynamically from TFTP file: 12154437/tftp-deploy-jquy125z/kernel/cmdline
10284 23:07:39.019193
10285 23:07:39.039458 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12154437/extract-nfsrootfs-69vuva4v,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10286 23:07:39.039983
10287 23:07:39.042111 Loading FIT.
10288 23:07:39.042698
10289 23:07:39.045517 Image ramdisk-1 has 18760031 bytes.
10290 23:07:39.046078
10291 23:07:39.046650 Image fdt-1 has 47278 bytes.
10292 23:07:39.047001
10293 23:07:39.048589 Image kernel-1 has 11043984 bytes.
10294 23:07:39.048992
10295 23:07:39.058524 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10296 23:07:39.059152
10297 23:07:39.075058 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10298 23:07:39.075551
10299 23:07:39.081463 Choosing best match conf-1 for compat google,spherion-rev2.
10300 23:07:39.085111
10301 23:07:39.089782 Connected to device vid:did:rid of 1ae0:0028:00
10302 23:07:39.096780
10303 23:07:39.100150 tpm_get_response: command 0x17b, return code 0x0
10304 23:07:39.100623
10305 23:07:39.103207 ec_init: CrosEC protocol v3 supported (256, 248)
10306 23:07:39.107240
10307 23:07:39.110803 tpm_cleanup: add release locality here.
10308 23:07:39.111275
10309 23:07:39.111643 Shutting down all USB controllers.
10310 23:07:39.114202
10311 23:07:39.114696 Removing current net device
10312 23:07:39.115066
10313 23:07:39.120601 Exiting depthcharge with code 4 at timestamp: 51038354
10314 23:07:39.121072
10315 23:07:39.124223 LZMA decompressing kernel-1 to 0x821a6718
10316 23:07:39.124688
10317 23:07:39.127191 LZMA decompressing kernel-1 to 0x40000000
10318 23:07:40.521877
10319 23:07:40.522426 jumping to kernel
10320 23:07:40.523980 end: 2.2.4 bootloader-commands (duration 00:00:23) [common]
10321 23:07:40.524477 start: 2.2.5 auto-login-action (timeout 00:04:02) [common]
10322 23:07:40.524855 Setting prompt string to ['Linux version [0-9]']
10323 23:07:40.525198 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10324 23:07:40.525543 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10325 23:07:40.603322
10326 23:07:40.606672 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10327 23:07:40.610596 start: 2.2.5.1 login-action (timeout 00:04:02) [common]
10328 23:07:40.611196 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10329 23:07:40.611706 Setting prompt string to []
10330 23:07:40.612336 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10331 23:07:40.612951 Using line separator: #'\n'#
10332 23:07:40.613494 No login prompt set.
10333 23:07:40.613973 Parsing kernel messages
10334 23:07:40.614622 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10335 23:07:40.615241 [login-action] Waiting for messages, (timeout 00:04:02)
10336 23:07:40.629908 [ 0.000000] Linux version 6.1.64-cip10 (KernelCI@build-j31357-arm64-gcc-10-defconfig-arm64-chromebook-69txj) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Dec 1 22:47:09 UTC 2023
10337 23:07:40.633207 [ 0.000000] random: crng init done
10338 23:07:40.640234 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10339 23:07:40.640666 [ 0.000000] efi: UEFI not found.
10340 23:07:40.649725 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10341 23:07:40.656369 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10342 23:07:40.666759 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10343 23:07:40.676318 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10344 23:07:40.683111 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10345 23:07:40.686377 [ 0.000000] printk: bootconsole [mtk8250] enabled
10346 23:07:40.695295 [ 0.000000] NUMA: No NUMA configuration found
10347 23:07:40.701659 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10348 23:07:40.708315 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10349 23:07:40.708747 [ 0.000000] Zone ranges:
10350 23:07:40.715294 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10351 23:07:40.718304 [ 0.000000] DMA32 empty
10352 23:07:40.725004 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10353 23:07:40.728462 [ 0.000000] Movable zone start for each node
10354 23:07:40.731637 [ 0.000000] Early memory node ranges
10355 23:07:40.738163 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10356 23:07:40.744946 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10357 23:07:40.751574 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10358 23:07:40.758069 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10359 23:07:40.764855 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10360 23:07:40.771571 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10361 23:07:40.827782 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10362 23:07:40.834520 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10363 23:07:40.841107 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10364 23:07:40.844194 [ 0.000000] psci: probing for conduit method from DT.
10365 23:07:40.851002 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10366 23:07:40.854449 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10367 23:07:40.861475 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10368 23:07:40.864023 [ 0.000000] psci: SMC Calling Convention v1.2
10369 23:07:40.870835 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10370 23:07:40.874073 [ 0.000000] Detected VIPT I-cache on CPU0
10371 23:07:40.880701 [ 0.000000] CPU features: detected: GIC system register CPU interface
10372 23:07:40.887380 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10373 23:07:40.893934 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10374 23:07:40.900848 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10375 23:07:40.907557 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10376 23:07:40.917529 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10377 23:07:40.920758 [ 0.000000] alternatives: applying boot alternatives
10378 23:07:40.927890 [ 0.000000] Fallback order for Node 0: 0
10379 23:07:40.934294 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10380 23:07:40.934768 [ 0.000000] Policy zone: Normal
10381 23:07:40.957258 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12154437/extract-nfsrootfs-69vuva4v,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10382 23:07:40.970543 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10383 23:07:40.980411 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10384 23:07:40.990367 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10385 23:07:40.997389 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10386 23:07:41.000201 <6>[ 0.000000] software IO TLB: area num 8.
10387 23:07:41.056601 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10388 23:07:41.205439 <6>[ 0.000000] Memory: 7951232K/8385536K available (17984K kernel code, 4116K rwdata, 17316K rodata, 8448K init, 615K bss, 401536K reserved, 32768K cma-reserved)
10389 23:07:41.211747 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10390 23:07:41.218548 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10391 23:07:41.221728 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10392 23:07:41.228590 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10393 23:07:41.235513 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10394 23:07:41.238696 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10395 23:07:41.249164 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10396 23:07:41.255656 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10397 23:07:41.258646 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10398 23:07:41.266334 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10399 23:07:41.270062 <6>[ 0.000000] GICv3: 608 SPIs implemented
10400 23:07:41.276440 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10401 23:07:41.279868 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10402 23:07:41.282913 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10403 23:07:41.292972 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10404 23:07:41.303249 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10405 23:07:41.316191 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10406 23:07:41.322862 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10407 23:07:41.332077 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10408 23:07:41.344981 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10409 23:07:41.351685 <6>[ 0.000001] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10410 23:07:41.358706 <6>[ 0.009190] Console: colour dummy device 80x25
10411 23:07:41.368385 <6>[ 0.013916] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10412 23:07:41.375440 <6>[ 0.024358] pid_max: default: 32768 minimum: 301
10413 23:07:41.378090 <6>[ 0.029230] LSM: Security Framework initializing
10414 23:07:41.384727 <6>[ 0.034170] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10415 23:07:41.394791 <6>[ 0.042031] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10416 23:07:41.401470 <6>[ 0.051499] cblist_init_generic: Setting adjustable number of callback queues.
10417 23:07:41.408127 <6>[ 0.058941] cblist_init_generic: Setting shift to 3 and lim to 1.
10418 23:07:41.418129 <6>[ 0.065278] cblist_init_generic: Setting adjustable number of callback queues.
10419 23:07:41.421730 <6>[ 0.072705] cblist_init_generic: Setting shift to 3 and lim to 1.
10420 23:07:41.428357 <6>[ 0.079104] rcu: Hierarchical SRCU implementation.
10421 23:07:41.434902 <6>[ 0.084121] rcu: Max phase no-delay instances is 1000.
10422 23:07:41.441213 <6>[ 0.091152] EFI services will not be available.
10423 23:07:41.445073 <6>[ 0.096105] smp: Bringing up secondary CPUs ...
10424 23:07:41.452542 <6>[ 0.101186] Detected VIPT I-cache on CPU1
10425 23:07:41.459420 <6>[ 0.101256] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10426 23:07:41.466329 <6>[ 0.101286] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10427 23:07:41.469062 <6>[ 0.101626] Detected VIPT I-cache on CPU2
10428 23:07:41.475941 <6>[ 0.101676] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10429 23:07:41.482722 <6>[ 0.101691] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10430 23:07:41.489062 <6>[ 0.101950] Detected VIPT I-cache on CPU3
10431 23:07:41.495876 <6>[ 0.101996] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10432 23:07:41.502490 <6>[ 0.102010] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10433 23:07:41.505647 <6>[ 0.102315] CPU features: detected: Spectre-v4
10434 23:07:41.512502 <6>[ 0.102322] CPU features: detected: Spectre-BHB
10435 23:07:41.515919 <6>[ 0.102327] Detected PIPT I-cache on CPU4
10436 23:07:41.522809 <6>[ 0.102383] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10437 23:07:41.529216 <6>[ 0.102400] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10438 23:07:41.535400 <6>[ 0.102694] Detected PIPT I-cache on CPU5
10439 23:07:41.542298 <6>[ 0.102756] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10440 23:07:41.548759 <6>[ 0.102773] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10441 23:07:41.552121 <6>[ 0.103055] Detected PIPT I-cache on CPU6
10442 23:07:41.559075 <6>[ 0.103118] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10443 23:07:41.565429 <6>[ 0.103135] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10444 23:07:41.572323 <6>[ 0.103430] Detected PIPT I-cache on CPU7
10445 23:07:41.578506 <6>[ 0.103494] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10446 23:07:41.585039 <6>[ 0.103510] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10447 23:07:41.588789 <6>[ 0.103557] smp: Brought up 1 node, 8 CPUs
10448 23:07:41.595334 <6>[ 0.244997] SMP: Total of 8 processors activated.
10449 23:07:41.598914 <6>[ 0.249948] CPU features: detected: 32-bit EL0 Support
10450 23:07:41.609049 <6>[ 0.255345] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10451 23:07:41.615502 <6>[ 0.264200] CPU features: detected: Common not Private translations
10452 23:07:41.621690 <6>[ 0.270676] CPU features: detected: CRC32 instructions
10453 23:07:41.625118 <6>[ 0.276028] CPU features: detected: RCpc load-acquire (LDAPR)
10454 23:07:41.631591 <6>[ 0.282025] CPU features: detected: LSE atomic instructions
10455 23:07:41.638706 <6>[ 0.287842] CPU features: detected: Privileged Access Never
10456 23:07:41.644986 <6>[ 0.293622] CPU features: detected: RAS Extension Support
10457 23:07:41.651348 <6>[ 0.299265] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10458 23:07:41.654878 <6>[ 0.306485] CPU: All CPU(s) started at EL2
10459 23:07:41.661439 <6>[ 0.310802] alternatives: applying system-wide alternatives
10460 23:07:41.670484 <6>[ 0.321536] devtmpfs: initialized
10461 23:07:41.685993 <6>[ 0.330448] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10462 23:07:41.692728 <6>[ 0.340411] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10463 23:07:41.699402 <6>[ 0.348628] pinctrl core: initialized pinctrl subsystem
10464 23:07:41.702575 <6>[ 0.355270] DMI not present or invalid.
10465 23:07:41.709246 <6>[ 0.359675] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10466 23:07:41.719255 <6>[ 0.366548] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10467 23:07:41.725807 <6>[ 0.374133] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10468 23:07:41.735763 <6>[ 0.382361] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10469 23:07:41.739071 <6>[ 0.390606] audit: initializing netlink subsys (disabled)
10470 23:07:41.749117 <5>[ 0.396286] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10471 23:07:41.755678 <6>[ 0.396958] thermal_sys: Registered thermal governor 'step_wise'
10472 23:07:41.762337 <6>[ 0.404255] thermal_sys: Registered thermal governor 'power_allocator'
10473 23:07:41.766020 <6>[ 0.410511] cpuidle: using governor menu
10474 23:07:41.772321 <6>[ 0.421472] NET: Registered PF_QIPCRTR protocol family
10475 23:07:41.779235 <6>[ 0.426951] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10476 23:07:41.782199 <6>[ 0.434053] ASID allocator initialised with 32768 entries
10477 23:07:41.789486 <6>[ 0.440612] Serial: AMBA PL011 UART driver
10478 23:07:41.798520 <4>[ 0.449363] Trying to register duplicate clock ID: 134
10479 23:07:41.853454 <6>[ 0.507036] KASLR enabled
10480 23:07:41.867061 <6>[ 0.514726] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10481 23:07:41.873796 <6>[ 0.521740] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10482 23:07:41.880615 <6>[ 0.528230] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10483 23:07:41.886849 <6>[ 0.535235] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10484 23:07:41.893548 <6>[ 0.541722] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10485 23:07:41.900417 <6>[ 0.548725] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10486 23:07:41.906815 <6>[ 0.555211] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10487 23:07:41.913647 <6>[ 0.562216] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10488 23:07:41.916740 <6>[ 0.569727] ACPI: Interpreter disabled.
10489 23:07:41.925342 <6>[ 0.576130] iommu: Default domain type: Translated
10490 23:07:41.931797 <6>[ 0.581244] iommu: DMA domain TLB invalidation policy: strict mode
10491 23:07:41.935255 <5>[ 0.587902] SCSI subsystem initialized
10492 23:07:41.942082 <6>[ 0.592066] usbcore: registered new interface driver usbfs
10493 23:07:41.949332 <6>[ 0.597801] usbcore: registered new interface driver hub
10494 23:07:41.952292 <6>[ 0.603350] usbcore: registered new device driver usb
10495 23:07:41.958659 <6>[ 0.609457] pps_core: LinuxPPS API ver. 1 registered
10496 23:07:41.968688 <6>[ 0.614651] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10497 23:07:41.971834 <6>[ 0.623999] PTP clock support registered
10498 23:07:41.975034 <6>[ 0.628241] EDAC MC: Ver: 3.0.0
10499 23:07:41.982502 <6>[ 0.633395] FPGA manager framework
10500 23:07:41.986152 <6>[ 0.637076] Advanced Linux Sound Architecture Driver Initialized.
10501 23:07:41.989649 <6>[ 0.643851] vgaarb: loaded
10502 23:07:41.996015 <6>[ 0.647013] clocksource: Switched to clocksource arch_sys_counter
10503 23:07:42.002878 <5>[ 0.653453] VFS: Disk quotas dquot_6.6.0
10504 23:07:42.009351 <6>[ 0.657639] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10505 23:07:42.012531 <6>[ 0.664827] pnp: PnP ACPI: disabled
10506 23:07:42.020686 <6>[ 0.671514] NET: Registered PF_INET protocol family
10507 23:07:42.030507 <6>[ 0.677103] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10508 23:07:42.041902 <6>[ 0.689443] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10509 23:07:42.051716 <6>[ 0.698258] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10510 23:07:42.058332 <6>[ 0.706228] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10511 23:07:42.068293 <6>[ 0.714885] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10512 23:07:42.074746 <6>[ 0.724644] TCP: Hash tables configured (established 65536 bind 65536)
10513 23:07:42.081728 <6>[ 0.731445] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10514 23:07:42.091275 <6>[ 0.738645] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10515 23:07:42.094872 <6>[ 0.746348] NET: Registered PF_UNIX/PF_LOCAL protocol family
10516 23:07:42.101478 <6>[ 0.752500] RPC: Registered named UNIX socket transport module.
10517 23:07:42.108211 <6>[ 0.758653] RPC: Registered udp transport module.
10518 23:07:42.111529 <6>[ 0.763588] RPC: Registered tcp transport module.
10519 23:07:42.118030 <6>[ 0.768520] RPC: Registered tcp NFSv4.1 backchannel transport module.
10520 23:07:42.124787 <6>[ 0.775184] PCI: CLS 0 bytes, default 64
10521 23:07:42.127897 <6>[ 0.779519] Unpacking initramfs...
10522 23:07:42.151535 <6>[ 0.799102] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10523 23:07:42.161476 <6>[ 0.807749] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10524 23:07:42.164603 <6>[ 0.816594] kvm [1]: IPA Size Limit: 40 bits
10525 23:07:42.171261 <6>[ 0.821120] kvm [1]: GICv3: no GICV resource entry
10526 23:07:42.174713 <6>[ 0.826142] kvm [1]: disabling GICv2 emulation
10527 23:07:42.181451 <6>[ 0.830832] kvm [1]: GIC system register CPU interface enabled
10528 23:07:42.184577 <6>[ 0.836986] kvm [1]: vgic interrupt IRQ18
10529 23:07:42.191324 <6>[ 0.841337] kvm [1]: VHE mode initialized successfully
10530 23:07:42.197921 <5>[ 0.847746] Initialise system trusted keyrings
10531 23:07:42.204538 <6>[ 0.852555] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10532 23:07:42.211532 <6>[ 0.862543] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10533 23:07:42.217970 <5>[ 0.868987] NFS: Registering the id_resolver key type
10534 23:07:42.221231 <5>[ 0.874302] Key type id_resolver registered
10535 23:07:42.228519 <5>[ 0.878715] Key type id_legacy registered
10536 23:07:42.234877 <6>[ 0.882990] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10537 23:07:42.241849 <6>[ 0.889914] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10538 23:07:42.248120 <6>[ 0.897642] 9p: Installing v9fs 9p2000 file system support
10539 23:07:42.284763 <5>[ 0.935596] Key type asymmetric registered
10540 23:07:42.287818 <5>[ 0.939926] Asymmetric key parser 'x509' registered
10541 23:07:42.297940 <6>[ 0.945071] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10542 23:07:42.301248 <6>[ 0.952686] io scheduler mq-deadline registered
10543 23:07:42.304544 <6>[ 0.957447] io scheduler kyber registered
10544 23:07:42.323085 <6>[ 0.974362] EINJ: ACPI disabled.
10545 23:07:42.355092 <4>[ 0.999644] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10546 23:07:42.365279 <4>[ 1.010279] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10547 23:07:42.380004 <6>[ 1.031131] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10548 23:07:42.388156 <6>[ 1.039210] printk: console [ttyS0] disabled
10549 23:07:42.415871 <6>[ 1.063859] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10550 23:07:42.422573 <6>[ 1.073339] printk: console [ttyS0] enabled
10551 23:07:42.426003 <6>[ 1.073339] printk: console [ttyS0] enabled
10552 23:07:42.432915 <6>[ 1.082233] printk: bootconsole [mtk8250] disabled
10553 23:07:42.435847 <6>[ 1.082233] printk: bootconsole [mtk8250] disabled
10554 23:07:42.442788 <6>[ 1.093429] SuperH (H)SCI(F) driver initialized
10555 23:07:42.445697 <6>[ 1.098708] msm_serial: driver initialized
10556 23:07:42.459812 <6>[ 1.107700] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10557 23:07:42.469854 <6>[ 1.116247] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10558 23:07:42.476326 <6>[ 1.124788] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10559 23:07:42.486535 <6>[ 1.133416] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10560 23:07:42.496661 <6>[ 1.142123] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10561 23:07:42.502846 <6>[ 1.150844] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10562 23:07:42.512805 <6>[ 1.159384] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10563 23:07:42.519844 <6>[ 1.168185] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10564 23:07:42.529583 <6>[ 1.176728] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10565 23:07:42.541236 <6>[ 1.192373] loop: module loaded
10566 23:07:42.547986 <6>[ 1.198427] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10567 23:07:42.570529 <4>[ 1.221793] mtk-pmic-keys: Failed to locate of_node [id: -1]
10568 23:07:42.577494 <6>[ 1.228722] megasas: 07.719.03.00-rc1
10569 23:07:42.587214 <6>[ 1.238352] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10570 23:07:42.595307 <6>[ 1.246376] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10571 23:07:42.612008 <6>[ 1.262870] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10572 23:07:42.668005 <6>[ 1.312020] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10573 23:07:42.916188 <6>[ 1.567338] Freeing initrd memory: 18320K
10574 23:07:42.927830 <6>[ 1.578855] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10575 23:07:42.939082 <6>[ 1.589696] tun: Universal TUN/TAP device driver, 1.6
10576 23:07:42.942155 <6>[ 1.595754] thunder_xcv, ver 1.0
10577 23:07:42.945508 <6>[ 1.599258] thunder_bgx, ver 1.0
10578 23:07:42.948687 <6>[ 1.602749] nicpf, ver 1.0
10579 23:07:42.959088 <6>[ 1.606760] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10580 23:07:42.962258 <6>[ 1.614237] hns3: Copyright (c) 2017 Huawei Corporation.
10581 23:07:42.968701 <6>[ 1.619831] hclge is initializing
10582 23:07:42.972325 <6>[ 1.623411] e1000: Intel(R) PRO/1000 Network Driver
10583 23:07:42.978964 <6>[ 1.628542] e1000: Copyright (c) 1999-2006 Intel Corporation.
10584 23:07:42.982500 <6>[ 1.634557] e1000e: Intel(R) PRO/1000 Network Driver
10585 23:07:42.988799 <6>[ 1.639771] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10586 23:07:42.995917 <6>[ 1.645957] igb: Intel(R) Gigabit Ethernet Network Driver
10587 23:07:43.002078 <6>[ 1.651609] igb: Copyright (c) 2007-2014 Intel Corporation.
10588 23:07:43.008912 <6>[ 1.657445] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10589 23:07:43.015474 <6>[ 1.663962] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10590 23:07:43.018881 <6>[ 1.670428] sky2: driver version 1.30
10591 23:07:43.025431 <6>[ 1.675428] VFIO - User Level meta-driver version: 0.3
10592 23:07:43.033082 <6>[ 1.683666] usbcore: registered new interface driver usb-storage
10593 23:07:43.039100 <6>[ 1.690109] usbcore: registered new device driver onboard-usb-hub
10594 23:07:43.048410 <6>[ 1.699238] mt6397-rtc mt6359-rtc: registered as rtc0
10595 23:07:43.058076 <6>[ 1.704706] mt6397-rtc mt6359-rtc: setting system clock to 2023-12-01T23:07:09 UTC (1701472029)
10596 23:07:43.061587 <6>[ 1.714271] i2c_dev: i2c /dev entries driver
10597 23:07:43.078299 <6>[ 1.725882] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10598 23:07:43.098297 <6>[ 1.748879] cpu cpu0: EM: created perf domain
10599 23:07:43.101185 <6>[ 1.753737] cpu cpu4: EM: created perf domain
10600 23:07:43.108083 <6>[ 1.759321] sdhci: Secure Digital Host Controller Interface driver
10601 23:07:43.115046 <6>[ 1.765754] sdhci: Copyright(c) Pierre Ossman
10602 23:07:43.121506 <6>[ 1.770691] Synopsys Designware Multimedia Card Interface Driver
10603 23:07:43.128384 <6>[ 1.777328] sdhci-pltfm: SDHCI platform and OF driver helper
10604 23:07:43.131611 <6>[ 1.777360] mmc0: CQHCI version 5.10
10605 23:07:43.138543 <6>[ 1.787218] ledtrig-cpu: registered to indicate activity on CPUs
10606 23:07:43.145107 <6>[ 1.794180] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10607 23:07:43.151466 <6>[ 1.801224] usbcore: registered new interface driver usbhid
10608 23:07:43.154867 <6>[ 1.807045] usbhid: USB HID core driver
10609 23:07:43.161528 <6>[ 1.811232] spi_master spi0: will run message pump with realtime priority
10610 23:07:43.204913 <6>[ 1.849448] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10611 23:07:43.221256 <6>[ 1.865596] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10612 23:07:43.228385 <6>[ 1.879198] mmc0: Command Queue Engine enabled
10613 23:07:43.235072 <6>[ 1.883966] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10614 23:07:43.238631 <6>[ 1.891408] mmcblk0: mmc0:0001 DA4128 116 GiB
10615 23:07:43.245537 <6>[ 1.896286] cros-ec-spi spi0.0: Chrome EC device registered
10616 23:07:43.252354 <6>[ 1.900075] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10617 23:07:43.258921 <6>[ 1.909951] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10618 23:07:43.265546 <6>[ 1.915917] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10619 23:07:43.272168 <6>[ 1.922069] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10620 23:07:43.291065 <6>[ 1.938769] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10621 23:07:43.299288 <6>[ 1.949744] NET: Registered PF_PACKET protocol family
10622 23:07:43.302447 <6>[ 1.955115] 9pnet: Installing 9P2000 support
10623 23:07:43.308679 <5>[ 1.959682] Key type dns_resolver registered
10624 23:07:43.311869 <6>[ 1.964711] registered taskstats version 1
10625 23:07:43.318697 <5>[ 1.969096] Loading compiled-in X.509 certificates
10626 23:07:43.349996 <4>[ 1.994172] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10627 23:07:43.359844 <4>[ 2.004982] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10628 23:07:43.366502 <3>[ 2.015520] debugfs: File 'uA_load' in directory '/' already present!
10629 23:07:43.373316 <3>[ 2.022230] debugfs: File 'min_uV' in directory '/' already present!
10630 23:07:43.379936 <3>[ 2.028837] debugfs: File 'max_uV' in directory '/' already present!
10631 23:07:43.386455 <3>[ 2.035445] debugfs: File 'constraint_flags' in directory '/' already present!
10632 23:07:43.397811 <3>[ 2.045577] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10633 23:07:43.410262 <6>[ 2.061280] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10634 23:07:43.416970 <6>[ 2.068161] xhci-mtk 11200000.usb: xHCI Host Controller
10635 23:07:43.423866 <6>[ 2.073665] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10636 23:07:43.433864 <6>[ 2.081580] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10637 23:07:43.440571 <6>[ 2.091019] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10638 23:07:43.447200 <6>[ 2.097093] xhci-mtk 11200000.usb: xHCI Host Controller
10639 23:07:43.453779 <6>[ 2.102574] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10640 23:07:43.460534 <6>[ 2.110223] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10641 23:07:43.467164 <6>[ 2.118042] hub 1-0:1.0: USB hub found
10642 23:07:43.470269 <6>[ 2.122076] hub 1-0:1.0: 1 port detected
10643 23:07:43.477700 <6>[ 2.126373] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10644 23:07:43.484192 <6>[ 2.135115] hub 2-0:1.0: USB hub found
10645 23:07:43.487330 <6>[ 2.139134] hub 2-0:1.0: 1 port detected
10646 23:07:43.494658 <6>[ 2.145811] mtk-msdc 11f70000.mmc: Got CD GPIO
10647 23:07:43.508778 <6>[ 2.156434] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10648 23:07:43.515072 <6>[ 2.164472] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10649 23:07:43.525297 <4>[ 2.172384] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10650 23:07:43.535376 <6>[ 2.181960] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10651 23:07:43.541797 <6>[ 2.190037] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10652 23:07:43.548299 <6>[ 2.198054] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10653 23:07:43.558434 <6>[ 2.205969] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10654 23:07:43.565333 <6>[ 2.213786] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10655 23:07:43.574825 <6>[ 2.221606] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10656 23:07:43.584898 <6>[ 2.232046] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10657 23:07:43.591553 <6>[ 2.240413] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10658 23:07:43.602025 <6>[ 2.248758] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10659 23:07:43.608695 <6>[ 2.257097] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10660 23:07:43.617925 <6>[ 2.265436] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10661 23:07:43.624730 <6>[ 2.273774] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10662 23:07:43.634731 <6>[ 2.282113] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10663 23:07:43.641473 <6>[ 2.290452] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10664 23:07:43.651405 <6>[ 2.298791] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10665 23:07:43.657871 <6>[ 2.307129] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10666 23:07:43.668079 <6>[ 2.315472] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10667 23:07:43.674580 <6>[ 2.323811] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10668 23:07:43.684451 <6>[ 2.332149] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10669 23:07:43.694532 <6>[ 2.340488] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10670 23:07:43.700990 <6>[ 2.348827] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10671 23:07:43.707580 <6>[ 2.357421] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10672 23:07:43.714291 <6>[ 2.364551] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10673 23:07:43.720764 <6>[ 2.371303] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10674 23:07:43.727240 <6>[ 2.378060] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10675 23:07:43.737293 <6>[ 2.384992] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10676 23:07:43.743876 <6>[ 2.391845] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10677 23:07:43.753810 <6>[ 2.400978] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10678 23:07:43.764156 <6>[ 2.410096] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10679 23:07:43.773512 <6>[ 2.419390] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10680 23:07:43.784063 <6>[ 2.428865] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10681 23:07:43.790372 <6>[ 2.438332] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10682 23:07:43.800081 <6>[ 2.447453] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10683 23:07:43.809714 <6>[ 2.456923] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10684 23:07:43.819972 <6>[ 2.466042] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10685 23:07:43.829541 <6>[ 2.475335] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10686 23:07:43.839486 <6>[ 2.485496] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10687 23:07:43.849938 <6>[ 2.497114] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10688 23:07:43.856533 <6>[ 2.506818] Trying to probe devices needed for running init ...
10689 23:07:43.899415 <6>[ 2.547306] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10690 23:07:44.053908 <6>[ 2.705112] hub 1-1:1.0: USB hub found
10691 23:07:44.057011 <6>[ 2.709611] hub 1-1:1.0: 4 ports detected
10692 23:07:44.067353 <6>[ 2.718479] hub 1-1:1.0: USB hub found
10693 23:07:44.070874 <6>[ 2.722837] hub 1-1:1.0: 4 ports detected
10694 23:07:44.179676 <6>[ 2.827611] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10695 23:07:44.206419 <6>[ 2.856929] hub 2-1:1.0: USB hub found
10696 23:07:44.209402 <6>[ 2.861422] hub 2-1:1.0: 3 ports detected
10697 23:07:44.219110 <6>[ 2.869599] hub 2-1:1.0: USB hub found
10698 23:07:44.221555 <6>[ 2.874043] hub 2-1:1.0: 3 ports detected
10699 23:07:44.395550 <6>[ 3.043328] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10700 23:07:44.528094 <6>[ 3.179139] hub 1-1.4:1.0: USB hub found
10701 23:07:44.531088 <6>[ 3.183805] hub 1-1.4:1.0: 2 ports detected
10702 23:07:44.540986 <6>[ 3.191836] hub 1-1.4:1.0: USB hub found
10703 23:07:44.543834 <6>[ 3.196435] hub 1-1.4:1.0: 2 ports detected
10704 23:07:44.607575 <6>[ 3.255449] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10705 23:07:44.839560 <6>[ 3.487323] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10706 23:07:45.031333 <6>[ 3.679328] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10707 23:07:56.144278 <6>[ 14.800301] ALSA device list:
10708 23:07:56.150991 <6>[ 14.803597] No soundcards found.
10709 23:07:56.159052 <6>[ 14.811604] Freeing unused kernel memory: 8448K
10710 23:07:56.162454 <6>[ 14.816581] Run /init as init process
10711 23:07:56.174142 Loading, please wait...
10712 23:07:56.199373 Starting systemd-udevd version 252.6-1
10713 23:07:56.423817 <3>[ 15.072975] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10714 23:07:56.430883 <6>[ 15.075893] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10715 23:07:56.451434 <3>[ 15.100740] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10716 23:07:56.458557 <3>[ 15.108904] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10717 23:07:56.464759 <6>[ 15.113295] remoteproc remoteproc0: scp is available
10718 23:07:56.471377 <6>[ 15.113542] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10719 23:07:56.481460 <6>[ 15.113563] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10720 23:07:56.487808 <6>[ 15.113571] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10721 23:07:56.498157 <3>[ 15.117115] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10722 23:07:56.501388 <6>[ 15.122813] remoteproc remoteproc0: powering up scp
10723 23:07:56.511562 <6>[ 15.124336] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10724 23:07:56.518730 <3>[ 15.129885] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10725 23:07:56.528070 <3>[ 15.129890] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10726 23:07:56.535247 <3>[ 15.129897] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10727 23:07:56.538660 <6>[ 15.130380] mc: Linux media interface: v0.10
10728 23:07:56.545285 <6>[ 15.135734] usbcore: registered new interface driver r8152
10729 23:07:56.555178 <6>[ 15.138584] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10730 23:07:56.561696 <3>[ 15.147275] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10731 23:07:56.571807 <4>[ 15.149237] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10732 23:07:56.574943 <4>[ 15.149237] Fallback method does not support PEC.
10733 23:07:56.581980 <6>[ 15.156284] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10734 23:07:56.587994 <3>[ 15.164373] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10735 23:07:56.598237 <3>[ 15.167172] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10736 23:07:56.604728 <4>[ 15.189184] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10737 23:07:56.611114 <6>[ 15.193989] videodev: Linux video capture interface: v2.00
10738 23:07:56.621478 <3>[ 15.198039] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10739 23:07:56.627634 <3>[ 15.203250] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10740 23:07:56.634298 <4>[ 15.203398] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10741 23:07:56.641492 <6>[ 15.215426] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10742 23:07:56.651317 <3>[ 15.219513] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10743 23:07:56.657973 <6>[ 15.236306] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10744 23:07:56.664350 <3>[ 15.238793] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10745 23:07:56.670921 <6>[ 15.246871] pci_bus 0000:00: root bus resource [bus 00-ff]
10746 23:07:56.680776 <6>[ 15.248035] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10747 23:07:56.690804 <6>[ 15.248483] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10748 23:07:56.697653 <3>[ 15.255687] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10749 23:07:56.707187 <4>[ 15.262723] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10750 23:07:56.714154 <4>[ 15.262730] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10751 23:07:56.724232 <6>[ 15.262931] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10752 23:07:56.730991 <3>[ 15.268664] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10753 23:07:56.740447 <6>[ 15.277433] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10754 23:07:56.747191 <3>[ 15.285509] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10755 23:07:56.753840 <6>[ 15.292826] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10756 23:07:56.764280 <6>[ 15.293988] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10757 23:07:56.770493 <6>[ 15.299952] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10758 23:07:56.780238 <3>[ 15.303076] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10759 23:07:56.786925 <3>[ 15.303086] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10760 23:07:56.793242 <3>[ 15.303128] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10761 23:07:56.803303 <6>[ 15.308017] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10762 23:07:56.809790 <6>[ 15.309686] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10763 23:07:56.819885 <6>[ 15.311635] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10764 23:07:56.826778 <6>[ 15.314880] remoteproc remoteproc0: remote processor scp is now up
10765 23:07:56.833472 <6>[ 15.315235] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10766 23:07:56.840158 <6>[ 15.323455] pci 0000:00:00.0: supports D1 D2
10767 23:07:56.843181 <6>[ 15.329021] r8152 2-1.3:1.0 eth0: v1.12.13
10768 23:07:56.849699 <6>[ 15.338919] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10769 23:07:56.859771 <6>[ 15.340169] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10770 23:07:56.866573 <6>[ 15.356381] usbcore: registered new interface driver cdc_ether
10771 23:07:56.869732 <6>[ 15.365296] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10772 23:07:56.876208 <6>[ 15.365964] Bluetooth: Core ver 2.22
10773 23:07:56.879592 <6>[ 15.366055] NET: Registered PF_BLUETOOTH protocol family
10774 23:07:56.886067 <6>[ 15.366058] Bluetooth: HCI device and connection manager initialized
10775 23:07:56.892707 <6>[ 15.366086] Bluetooth: HCI socket layer initialized
10776 23:07:56.895900 <6>[ 15.366093] Bluetooth: L2CAP socket layer initialized
10777 23:07:56.902929 <6>[ 15.366105] Bluetooth: SCO socket layer initialized
10778 23:07:56.909278 <6>[ 15.380635] usbcore: registered new interface driver r8153_ecm
10779 23:07:56.916272 <6>[ 15.388478] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10780 23:07:56.922508 <6>[ 15.407241] r8152 2-1.3:1.0 enx00e04c722dd6: renamed from eth0
10781 23:07:56.929338 <6>[ 15.412701] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10782 23:07:56.935779 <6>[ 15.412716] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10783 23:07:56.945794 <6>[ 15.414359] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10784 23:07:56.955735 <6>[ 15.415593] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10785 23:07:56.962092 <6>[ 15.415697] usbcore: registered new interface driver uvcvideo
10786 23:07:56.969210 <6>[ 15.429079] usbcore: registered new interface driver btusb
10787 23:07:56.978750 <4>[ 15.429731] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10788 23:07:56.985254 <3>[ 15.429740] Bluetooth: hci0: Failed to load firmware file (-2)
10789 23:07:56.991601 <3>[ 15.429743] Bluetooth: hci0: Failed to set up firmware (-2)
10790 23:07:57.001656 <4>[ 15.429747] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10791 23:07:57.005155 <6>[ 15.436448] pci 0000:01:00.0: supports D1 D2
10792 23:07:57.011920 <6>[ 15.436927] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10793 23:07:57.018724 <6>[ 15.669594] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10794 23:07:57.041777 <6>[ 15.691166] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10795 23:07:57.048618 <6>[ 15.698069] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10796 23:07:57.055176 <6>[ 15.706148] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10797 23:07:57.065145 <6>[ 15.714142] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10798 23:07:57.071787 <6>[ 15.722143] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10799 23:07:57.082198 <6>[ 15.730144] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10800 23:07:57.085258 <6>[ 15.738144] pci 0000:00:00.0: PCI bridge to [bus 01]
10801 23:07:57.094810 <6>[ 15.743360] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10802 23:07:57.101668 <6>[ 15.751463] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10803 23:07:57.108282 <6>[ 15.758272] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10804 23:07:57.114229 <6>[ 15.764866] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10805 23:07:57.129710 <5>[ 15.778899] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10806 23:07:57.155298 <5>[ 15.804605] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10807 23:07:57.162176 <4>[ 15.811664] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10808 23:07:57.168573 <6>[ 15.820553] cfg80211: failed to load regulatory.db
10809 23:07:57.210943 <6>[ 15.860356] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10810 23:07:57.217578 <6>[ 15.867865] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10811 23:07:57.241972 <6>[ 15.894561] mt7921e 0000:01:00.0: ASIC revision: 79610010
10812 23:07:57.349598 <4>[ 15.995357] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10813 23:07:57.361084 Begin: Loading essential drivers ... done.
10814 23:07:57.364418 Begin: Running /scripts/init-premount ... done.
10815 23:07:57.371324 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10816 23:07:57.380960 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10817 23:07:57.384274 Device /sys/class/net/enx00e04c722dd6 found
10818 23:07:57.384858 done.
10819 23:07:57.410482 Begin: Waiting up to 180 secs for any network device to become available ... done.
10820 23:07:57.469779 <4>[ 16.115595] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10821 23:07:57.476537 IP-Config: enx00e04c722dd6 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP
10822 23:07:57.592887 <4>[ 16.238836] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10823 23:07:57.712720 <4>[ 16.358906] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10824 23:07:57.832651 <4>[ 16.479056] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10825 23:07:57.952941 <4>[ 16.598898] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10826 23:07:58.072824 <4>[ 16.719103] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10827 23:07:58.192777 <4>[ 16.838989] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10828 23:07:58.313123 <4>[ 16.959135] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10829 23:07:58.319564 <6>[ 16.971728] r8152 2-1.3:1.0 enx00e04c722dd6: carrier on
10830 23:07:58.432873 <4>[ 17.078919] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10831 23:07:58.543973 <3>[ 17.196906] mt7921e 0000:01:00.0: hardware init failed
10832 23:07:58.551915 IP-Config: no response after 2 secs - giving up
10833 23:07:58.601882 IP-Config: enx00e04c722dd6 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP
10834 23:07:58.604870 IP-Config: enx00e04c722dd6 complete (dhcp from 192.168.201.1):
10835 23:07:58.611777 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10836 23:07:58.621775 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10837 23:07:58.627961 host : mt8192-asurada-spherion-r0-cbg-1
10838 23:07:58.634557 domain : lava-rack
10839 23:07:58.638186 rootserver: 192.168.201.1 rootpath:
10840 23:07:58.638855 filename :
10841 23:07:58.742438 done.
10842 23:07:58.750324 Begin: Running /scripts/nfs-bottom ... done.
10843 23:07:58.768522 Begin: Running /scripts/init-bottom ... done.
10844 23:08:00.106564 <6>[ 18.759386] NET: Registered PF_INET6 protocol family
10845 23:08:00.113965 <6>[ 18.766469] Segment Routing with IPv6
10846 23:08:00.116966 <6>[ 18.770433] In-situ OAM (IOAM) with IPv6
10847 23:08:00.297466 <30>[ 18.923755] systemd[1]: systemd 252.6-1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10848 23:08:00.304076 <30>[ 18.956114] systemd[1]: Detected architecture arm64.
10849 23:08:00.311511
10850 23:08:00.315001 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10851 23:08:00.315580
10852 23:08:00.343933 <30>[ 18.996959] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10853 23:08:01.449152 <30>[ 20.098850] systemd[1]: Queued start job for default target graphical.target.
10854 23:08:01.502290 <30>[ 20.152261] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10855 23:08:01.509040 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10856 23:08:01.531312 <30>[ 20.181265] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10857 23:08:01.541423 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10858 23:08:01.559230 <30>[ 20.209079] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10859 23:08:01.569134 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10860 23:08:01.587581 <30>[ 20.237437] systemd[1]: Created slice user.slice - User and Session Slice.
10861 23:08:01.594195 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10862 23:08:01.617593 <30>[ 20.264220] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10863 23:08:01.627700 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10864 23:08:01.649121 <30>[ 20.295564] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10865 23:08:01.655678 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10866 23:08:01.683225 <30>[ 20.323507] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10867 23:08:01.693115 <30>[ 20.343418] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10868 23:08:01.699961 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10869 23:08:01.717108 <30>[ 20.367379] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10870 23:08:01.726841 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10871 23:08:01.741638 <30>[ 20.395442] systemd[1]: Reached target paths.target - Path Units.
10872 23:08:01.748537 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10873 23:08:01.768823 <30>[ 20.419331] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10874 23:08:01.776032 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10875 23:08:01.789636 <30>[ 20.443299] systemd[1]: Reached target slices.target - Slice Units.
10876 23:08:01.799970 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10877 23:08:01.814557 <30>[ 20.467801] systemd[1]: Reached target swap.target - Swaps.
10878 23:08:01.821143 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10879 23:08:01.841750 <30>[ 20.491708] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10880 23:08:01.851227 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10881 23:08:01.869318 <30>[ 20.519777] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10882 23:08:01.879512 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10883 23:08:01.900581 <30>[ 20.550743] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10884 23:08:01.910663 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10885 23:08:01.926505 <30>[ 20.576759] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10886 23:08:01.936391 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10887 23:08:01.953607 <30>[ 20.603947] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10888 23:08:01.960505 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10889 23:08:01.978290 <30>[ 20.628699] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10890 23:08:01.988165 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10891 23:08:02.007906 <30>[ 20.658071] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10892 23:08:02.017544 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10893 23:08:02.034502 <30>[ 20.684406] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10894 23:08:02.044211 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10895 23:08:02.093726 <30>[ 20.743818] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10896 23:08:02.100291 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10897 23:08:02.119432 <30>[ 20.769797] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10898 23:08:02.125943 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10899 23:08:02.148154 <30>[ 20.798633] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10900 23:08:02.154646 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10901 23:08:02.180540 <30>[ 20.823881] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10902 23:08:02.217890 <30>[ 20.868051] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10903 23:08:02.228551 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10904 23:08:02.251281 <30>[ 20.901318] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10905 23:08:02.257855 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10906 23:08:02.283719 <30>[ 20.933205] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10907 23:08:02.289846 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10908 23:08:02.325970 <6>[ 20.975700] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10909 23:08:02.354523 <30>[ 21.004290] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10910 23:08:02.361072 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10911 23:08:02.387281 <30>[ 21.037313] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10912 23:08:02.397341 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10913 23:08:02.419092 <30>[ 21.069217] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10914 23:08:02.426078 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10915 23:08:02.459051 <6>[ 21.112648] fuse: init (API version 7.37)
10916 23:08:02.478432 <30>[ 21.128276] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10917 23:08:02.484708 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10918 23:08:02.515597 <30>[ 21.165491] systemd[1]: Starting systemd-journald.service - Journal Service...
10919 23:08:02.521910 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10920 23:08:02.556139 <30>[ 21.206177] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10921 23:08:02.562503 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10922 23:08:02.592638 <30>[ 21.239366] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10923 23:08:02.599311 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10924 23:08:02.623808 <30>[ 21.273890] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10925 23:08:02.633993 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10926 23:08:02.656338 <30>[ 21.305754] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10927 23:08:02.666046 <3>[ 21.313255] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10928 23:08:02.672445 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10929 23:08:02.696609 <3>[ 21.346753] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10930 23:08:02.703649 <30>[ 21.348541] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10931 23:08:02.714061 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10932 23:08:02.730065 <30>[ 21.379761] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10933 23:08:02.739512 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10934 23:08:02.755509 <3>[ 21.405282] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10935 23:08:02.765296 <30>[ 21.414681] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10936 23:08:02.772168 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10937 23:08:02.784800 <3>[ 21.434955] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10938 23:08:02.794721 <30>[ 21.444747] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10939 23:08:02.805223 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10940 23:08:02.815163 <3>[ 21.464713] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10941 23:08:02.825332 <30>[ 21.474747] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10942 23:08:02.832572 <30>[ 21.482664] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10943 23:08:02.846109 [[0;32m OK [0m] Finished [0;1;39mmodprobe@c<3>[ 21.494815] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10944 23:08:02.849039 onfigfs…[0m - Load Kernel Module configfs.
10945 23:08:02.875589 <30>[ 21.524563] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10946 23:08:02.881873 <3>[ 21.525519] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10947 23:08:02.891100 <30>[ 21.532718] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10948 23:08:02.897880 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10949 23:08:02.910896 <3>[ 21.560875] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10950 23:08:02.922147 <30>[ 21.571882] systemd[1]: modprobe@drm.service: Deactivated successfully.
10951 23:08:02.928495 <30>[ 21.579646] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10952 23:08:02.945039 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m -<3>[ 21.593026] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10953 23:08:02.945614 Load Kernel Module drm.
10954 23:08:02.968006 <30>[ 21.617411] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10955 23:08:02.975002 <3>[ 21.624934] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10956 23:08:02.984755 <30>[ 21.625888] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10957 23:08:02.992058 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10958 23:08:03.011257 <30>[ 21.661222] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10959 23:08:03.017512 <30>[ 21.669163] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10960 23:08:03.028539 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10961 23:08:03.050222 <30>[ 21.700395] systemd[1]: Started systemd-journald.service - Journal Service.
10962 23:08:03.056937 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10963 23:08:03.082332 <4>[ 21.725381] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10964 23:08:03.089061 <3>[ 21.741045] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10965 23:08:03.098928 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10966 23:08:03.122565 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10967 23:08:03.142585 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10968 23:08:03.163067 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10969 23:08:03.182899 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10970 23:08:03.204791 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10971 23:08:03.253674 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10972 23:08:03.274049 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10973 23:08:03.345580 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10974 23:08:03.370491 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10975 23:08:03.399399 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10976 23:08:03.426975 Starting [0;1;39msyste<46>[ 22.076787] systemd-journald[308]: Received client request to flush runtime journal.
10977 23:08:03.430690 md-sysusers.…rvice[0m - Create System Users...
10978 23:08:03.463556 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10979 23:08:03.481405 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10980 23:08:03.502234 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10981 23:08:03.522071 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10982 23:08:03.660268 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10983 23:08:03.730019 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10984 23:08:04.883594 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10985 23:08:04.908899 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10986 23:08:04.929365 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10987 23:08:04.945024 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10988 23:08:05.009942 Starting [0;1;39msystemd-binfmt.se…et Up Additional Binary Formats...
10989 23:08:05.032486 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10990 23:08:05.054980 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10991 23:08:05.079456 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-bi… Set Up Additional Binary Formats.
10992 23:08:05.097291 See 'systemctl status systemd-binfmt.service' for details.
10993 23:08:05.297763 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10994 23:08:05.318907 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10995 23:08:05.398628 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10996 23:08:05.535226 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10997 23:08:05.560070 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10998 23:08:05.591557 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10999 23:08:05.786286 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11000 23:08:05.815559 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11001 23:08:05.867251 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11002 23:08:05.924459 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11003 23:08:05.947980 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11004 23:08:05.965048 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11005 23:08:05.980894 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11006 23:08:05.990943 <46>[ 24.645113] systemd-journald[308]: Time jumped backwards, rotating.
11007 23:08:06.003224 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11008 23:08:06.022216 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11009 23:08:06.044727 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11010 23:08:06.061023 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11011 23:08:06.076513 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11012 23:08:06.774632 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11013 23:08:07.102837 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11014 23:08:07.121245 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11015 23:08:07.462520 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11016 23:08:07.482139 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11017 23:08:07.500350 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11018 23:08:07.762678 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11019 23:08:07.780172 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11020 23:08:07.796548 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11021 23:08:07.873805 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11022 23:08:07.904592 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11023 23:08:07.977467 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11024 23:08:08.002141 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11025 23:08:08.028132 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11026 23:08:08.252932 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11027 23:08:08.305795 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11028 23:08:08.336221 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11029 23:08:08.353233 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11030 23:08:08.373642 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11031 23:08:08.397227 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11032 23:08:08.432024 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11033 23:08:08.452639 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11034 23:08:08.483503 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11035 23:08:08.501271 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11036 23:08:08.568599 Starting [0;1;39msystemd-hostnamed.service[0m - Hostname Service...
11037 23:08:08.591997 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11038 23:08:08.637423 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11039 23:08:08.748446 [[0;32m OK [0m] Started [0;1;39msystemd-hostnamed.service[0m - Hostname Service.
11040 23:08:08.825572
11041 23:08:08.825732
11042 23:08:08.829076 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11043 23:08:08.829163
11044 23:08:08.832122 debian-bookworm-arm64 login: root (automatic login)
11045 23:08:08.832208
11046 23:08:08.832275
11047 23:08:09.098362 Linux debian-bookworm-arm64 6.1.64-cip10 #1 SMP PREEMPT Fri Dec 1 22:47:09 UTC 2023 aarch64
11048 23:08:09.098544
11049 23:08:09.104466 The programs included with the Debian GNU/Linux system are free software;
11050 23:08:09.110982 the exact distribution terms for each program are described in the
11051 23:08:09.114131 individual files in /usr/share/doc/*/copyright.
11052 23:08:09.114216
11053 23:08:09.120826 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11054 23:08:09.124171 permitted by applicable law.
11055 23:08:10.125413 Matched prompt #10: / #
11057 23:08:10.125710 Setting prompt string to ['/ #']
11058 23:08:10.125807 end: 2.2.5.1 login-action (duration 00:00:30) [common]
11060 23:08:10.126005 end: 2.2.5 auto-login-action (duration 00:00:30) [common]
11061 23:08:10.126094 start: 2.2.6 expect-shell-connection (timeout 00:03:32) [common]
11062 23:08:10.126164 Setting prompt string to ['/ #']
11063 23:08:10.126225 Forcing a shell prompt, looking for ['/ #']
11065 23:08:10.176449 / #
11066 23:08:10.176604 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11067 23:08:10.176707 Waiting using forced prompt support (timeout 00:02:30)
11068 23:08:10.181648
11069 23:08:10.181929 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11070 23:08:10.182027 start: 2.2.7 export-device-env (timeout 00:03:32) [common]
11072 23:08:10.282405 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12154437/extract-nfsrootfs-69vuva4v'
11073 23:08:10.287621 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12154437/extract-nfsrootfs-69vuva4v'
11075 23:08:10.388188 / # export NFS_SERVER_IP='192.168.201.1'
11076 23:08:10.393181 export NFS_SERVER_IP='192.168.201.1'
11077 23:08:10.393475 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11078 23:08:10.393578 end: 2.2 depthcharge-retry (duration 00:01:28) [common]
11079 23:08:10.393674 end: 2 depthcharge-action (duration 00:01:28) [common]
11080 23:08:10.393766 start: 3 lava-test-retry (timeout 00:07:53) [common]
11081 23:08:10.393855 start: 3.1 lava-test-shell (timeout 00:07:53) [common]
11082 23:08:10.393934 Using namespace: common
11084 23:08:10.494300 / # #
11085 23:08:10.494479 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11086 23:08:10.499457 #
11087 23:08:10.499731 Using /lava-12154437
11089 23:08:10.600090 / # export SHELL=/bin/bash
11090 23:08:10.605390 export SHELL=/bin/bash
11092 23:08:10.705945 / # . /lava-12154437/environment
11093 23:08:10.711042 . /lava-12154437/environment
11095 23:08:10.816821 / # /lava-12154437/bin/lava-test-runner /lava-12154437/0
11096 23:08:10.816996 Test shell timeout: 10s (minimum of the action and connection timeout)
11097 23:08:10.822095 /lava-12154437/bin/lava-test-runner /lava-12154437/0
11098 23:08:11.028515 + export TESTRUN_ID=0_timesync-off
11099 23:08:11.031704 + TESTRUN_ID=0_timesync-off
11100 23:08:11.034947 + cd /lava-12154437/0/tests/0_timesync-off
11101 23:08:11.038344 ++ cat uuid
11102 23:08:11.038480 + UUID=12154437_1.6.2.3.1
11103 23:08:11.041677 + set +x
11104 23:08:11.045050 <LAVA_SIGNAL_STARTRUN 0_timesync-off 12154437_1.6.2.3.1>
11105 23:08:11.045314 Received signal: <STARTRUN> 0_timesync-off 12154437_1.6.2.3.1
11106 23:08:11.045394 Starting test lava.0_timesync-off (12154437_1.6.2.3.1)
11107 23:08:11.045483 Skipping test definition patterns.
11108 23:08:11.048559 + systemctl stop systemd-timesyncd
11109 23:08:11.094326 + set +x
11110 23:08:11.097381 <LAVA_SIGNAL_ENDRUN 0_timesync-off 12154437_1.6.2.3.1>
11111 23:08:11.097648 Received signal: <ENDRUN> 0_timesync-off 12154437_1.6.2.3.1
11112 23:08:11.097735 Ending use of test pattern.
11113 23:08:11.097800 Ending test lava.0_timesync-off (12154437_1.6.2.3.1), duration 0.05
11115 23:08:11.142402 + export TESTRUN_ID=1_kselftest-alsa
11116 23:08:11.145505 + TESTRUN_ID=1_kselftest-alsa
11117 23:08:11.152043 + cd /lava-12154437/0/tests/1_kselftest-alsa
11118 23:08:11.152132 ++ cat uuid
11119 23:08:11.155613 + UUID=12154437_1.6.2.3.5
11120 23:08:11.155699 + set +x
11121 23:08:11.159025 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 12154437_1.6.2.3.5>
11122 23:08:11.159310 Received signal: <STARTRUN> 1_kselftest-alsa 12154437_1.6.2.3.5
11123 23:08:11.159384 Starting test lava.1_kselftest-alsa (12154437_1.6.2.3.5)
11124 23:08:11.159466 Skipping test definition patterns.
11125 23:08:11.161906 + cd ./automated/linux/kselftest/
11126 23:08:11.188305 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.64-cip10/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11127 23:08:11.209486 INFO: install_deps skipped
11128 23:08:11.683042 --2023-12-01 23:07:37-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.64-cip10/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11129 23:08:11.693472 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11130 23:08:11.822271 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11131 23:08:11.951136 HTTP request sent, awaiting response... 200 OK
11132 23:08:11.954129 Length: 2967588 (2.8M) [application/octet-stream]
11133 23:08:11.957545 Saving to: 'kselftest.tar.xz'
11134 23:08:11.957629
11135 23:08:11.957697
11136 23:08:12.208684 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11137 23:08:12.466421 kselftest.tar.xz 1%[ ] 50.15K 196KB/s
11138 23:08:12.901901 kselftest.tar.xz 7%[> ] 218.91K 426KB/s
11139 23:08:13.169391 kselftest.tar.xz 28%[====> ] 815.64K 859KB/s
11140 23:08:13.176245 kselftest.tar.xz 83%[===============> ] 2.36M 1.94MB/s
11141 23:08:13.182531 kselftest.tar.xz 100%[===================>] 2.83M 2.31MB/s in 1.2s
11142 23:08:13.182621
11143 23:08:13.442200 2023-12-01 23:07:39 (2.31 MB/s) - 'kselftest.tar.xz' saved [2967588/2967588]
11144 23:08:13.442402
11145 23:08:18.871968 skiplist:
11146 23:08:18.875158 ========================================
11147 23:08:18.878305 ========================================
11148 23:08:18.922828 alsa:mixer-test
11149 23:08:18.939839 ============== Tests to run ===============
11150 23:08:18.939934 alsa:mixer-test
11151 23:08:18.943819 ===========End Tests to run ===============
11152 23:08:18.946332 shardfile-alsa pass
11153 23:08:19.046845 <12>[ 37.702160] kselftest: Running tests in alsa
11154 23:08:19.054364 TAP version 13
11155 23:08:19.067796 1..1
11156 23:08:19.081366 # selftests: alsa: mixer-test
11157 23:08:19.564085 # TAP version 13
11158 23:08:19.564239 # 1..0
11159 23:08:19.570661 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:0 error:0
11160 23:08:19.573895 ok 1 selftests: alsa: mixer-test
11161 23:08:20.274054 alsa_mixer-test pass
11162 23:08:20.319465 + ../../utils/send-to-lava.sh ./output/result.txt
11163 23:08:20.373594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
11164 23:08:20.373893 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
11166 23:08:20.410352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
11167 23:08:20.410448 + set +x
11168 23:08:20.410684 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
11170 23:08:20.417151 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 12154437_1.6.2.3.5>
11171 23:08:20.417404 Received signal: <ENDRUN> 1_kselftest-alsa 12154437_1.6.2.3.5
11172 23:08:20.417478 Ending use of test pattern.
11173 23:08:20.417540 Ending test lava.1_kselftest-alsa (12154437_1.6.2.3.5), duration 9.26
11175 23:08:20.420093 <LAVA_TEST_RUNNER EXIT>
11176 23:08:20.420343 ok: lava_test_shell seems to have completed
11177 23:08:20.420443 alsa_mixer-test: pass
shardfile-alsa: pass
11178 23:08:20.420543 end: 3.1 lava-test-shell (duration 00:00:10) [common]
11179 23:08:20.420631 end: 3 lava-test-retry (duration 00:00:10) [common]
11180 23:08:20.420718 start: 4 finalize (timeout 00:07:43) [common]
11181 23:08:20.420810 start: 4.1 power-off (timeout 00:00:30) [common]
11182 23:08:20.420964 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
11183 23:08:20.495843 >> Command sent successfully.
11184 23:08:20.498225 Returned 0 in 0 seconds
11185 23:08:20.598535 end: 4.1 power-off (duration 00:00:00) [common]
11187 23:08:20.598887 start: 4.2 read-feedback (timeout 00:07:42) [common]
11188 23:08:20.599152 Listened to connection for namespace 'common' for up to 1s
11189 23:08:21.600129 Finalising connection for namespace 'common'
11190 23:08:21.600314 Disconnecting from shell: Finalise
11191 23:08:21.600416 / #
11192 23:08:21.700754 end: 4.2 read-feedback (duration 00:00:01) [common]
11193 23:08:21.700936 end: 4 finalize (duration 00:00:01) [common]
11194 23:08:21.701070 Cleaning after the job
11195 23:08:21.701178 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12154437/tftp-deploy-jquy125z/ramdisk
11196 23:08:21.703567 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12154437/tftp-deploy-jquy125z/kernel
11197 23:08:21.712873 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12154437/tftp-deploy-jquy125z/dtb
11198 23:08:21.713054 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12154437/tftp-deploy-jquy125z/nfsrootfs
11199 23:08:21.787149 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12154437/tftp-deploy-jquy125z/modules
11200 23:08:21.792670 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12154437
11201 23:08:22.313488 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12154437
11202 23:08:22.313674 Job finished correctly