Boot log: mt8192-asurada-spherion-r0
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 27
- Kernel Errors: 36
- Errors: 0
1 23:04:11.990767 lava-dispatcher, installed at version: 2023.10
2 23:04:11.990987 start: 0 validate
3 23:04:11.991129 Start time: 2023-12-01 23:04:11.991120+00:00 (UTC)
4 23:04:11.991252 Using caching service: 'http://localhost/cache/?uri=%s'
5 23:04:11.991389 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 23:04:11.994280 Using caching service: 'http://localhost/cache/?uri=%s'
7 23:04:11.994415 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.64-cip10%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 23:04:29.759537 Using caching service: 'http://localhost/cache/?uri=%s'
9 23:04:29.760296 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.64-cip10%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 23:04:30.030384 Using caching service: 'http://localhost/cache/?uri=%s'
11 23:04:30.031101 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 23:04:30.295038 Using caching service: 'http://localhost/cache/?uri=%s'
13 23:04:30.295769 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.64-cip10%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 23:04:35.810248 validate duration: 23.82
16 23:04:35.810501 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 23:04:35.810598 start: 1.1 download-retry (timeout 00:10:00) [common]
18 23:04:35.810682 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 23:04:35.810820 Not decompressing ramdisk as can be used compressed.
20 23:04:35.810903 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/initrd.cpio.gz
21 23:04:35.810966 saving as /var/lib/lava/dispatcher/tmp/12154385/tftp-deploy-cllkt166/ramdisk/initrd.cpio.gz
22 23:04:35.811029 total size: 4665395 (4 MB)
23 23:04:36.076287 progress 0 % (0 MB)
24 23:04:36.077817 progress 5 % (0 MB)
25 23:04:36.079093 progress 10 % (0 MB)
26 23:04:36.080345 progress 15 % (0 MB)
27 23:04:36.081598 progress 20 % (0 MB)
28 23:04:36.082829 progress 25 % (1 MB)
29 23:04:36.084150 progress 30 % (1 MB)
30 23:04:36.085390 progress 35 % (1 MB)
31 23:04:36.086655 progress 40 % (1 MB)
32 23:04:36.088105 progress 45 % (2 MB)
33 23:04:36.089334 progress 50 % (2 MB)
34 23:04:36.090574 progress 55 % (2 MB)
35 23:04:36.091803 progress 60 % (2 MB)
36 23:04:36.093034 progress 65 % (2 MB)
37 23:04:36.094307 progress 70 % (3 MB)
38 23:04:36.095529 progress 75 % (3 MB)
39 23:04:36.096749 progress 80 % (3 MB)
40 23:04:36.098145 progress 85 % (3 MB)
41 23:04:36.099369 progress 90 % (4 MB)
42 23:04:36.100590 progress 95 % (4 MB)
43 23:04:36.101867 progress 100 % (4 MB)
44 23:04:36.102020 4 MB downloaded in 0.29 s (15.29 MB/s)
45 23:04:36.102176 end: 1.1.1 http-download (duration 00:00:00) [common]
47 23:04:36.102411 end: 1.1 download-retry (duration 00:00:00) [common]
48 23:04:36.102497 start: 1.2 download-retry (timeout 00:10:00) [common]
49 23:04:36.102579 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 23:04:36.102719 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.64-cip10/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 23:04:36.102786 saving as /var/lib/lava/dispatcher/tmp/12154385/tftp-deploy-cllkt166/kernel/Image
52 23:04:36.102845 total size: 49172992 (46 MB)
53 23:04:36.102905 No compression specified
54 23:04:36.104057 progress 0 % (0 MB)
55 23:04:36.116867 progress 5 % (2 MB)
56 23:04:36.129791 progress 10 % (4 MB)
57 23:04:36.142546 progress 15 % (7 MB)
58 23:04:36.155373 progress 20 % (9 MB)
59 23:04:36.168292 progress 25 % (11 MB)
60 23:04:36.181720 progress 30 % (14 MB)
61 23:04:36.195421 progress 35 % (16 MB)
62 23:04:36.208817 progress 40 % (18 MB)
63 23:04:36.221914 progress 45 % (21 MB)
64 23:04:36.234966 progress 50 % (23 MB)
65 23:04:36.248161 progress 55 % (25 MB)
66 23:04:36.261553 progress 60 % (28 MB)
67 23:04:36.275118 progress 65 % (30 MB)
68 23:04:36.288495 progress 70 % (32 MB)
69 23:04:36.301546 progress 75 % (35 MB)
70 23:04:36.315095 progress 80 % (37 MB)
71 23:04:36.328987 progress 85 % (39 MB)
72 23:04:36.343058 progress 90 % (42 MB)
73 23:04:36.356680 progress 95 % (44 MB)
74 23:04:36.369599 progress 100 % (46 MB)
75 23:04:36.369854 46 MB downloaded in 0.27 s (175.63 MB/s)
76 23:04:36.370016 end: 1.2.1 http-download (duration 00:00:00) [common]
78 23:04:36.370259 end: 1.2 download-retry (duration 00:00:00) [common]
79 23:04:36.370347 start: 1.3 download-retry (timeout 00:09:59) [common]
80 23:04:36.370436 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 23:04:36.370578 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.64-cip10/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 23:04:36.370651 saving as /var/lib/lava/dispatcher/tmp/12154385/tftp-deploy-cllkt166/dtb/mt8192-asurada-spherion-r0.dtb
83 23:04:36.370720 total size: 47278 (0 MB)
84 23:04:36.370796 No compression specified
85 23:04:36.371947 progress 69 % (0 MB)
86 23:04:36.372232 progress 100 % (0 MB)
87 23:04:36.372393 0 MB downloaded in 0.00 s (26.98 MB/s)
88 23:04:36.372523 end: 1.3.1 http-download (duration 00:00:00) [common]
90 23:04:36.372753 end: 1.3 download-retry (duration 00:00:00) [common]
91 23:04:36.372843 start: 1.4 download-retry (timeout 00:09:59) [common]
92 23:04:36.372927 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 23:04:36.373049 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/full.rootfs.tar.xz
94 23:04:36.373117 saving as /var/lib/lava/dispatcher/tmp/12154385/tftp-deploy-cllkt166/nfsrootfs/full.rootfs.tar
95 23:04:36.373177 total size: 200813988 (191 MB)
96 23:04:36.373238 Using unxz to decompress xz
97 23:04:36.377519 progress 0 % (0 MB)
98 23:04:36.930651 progress 5 % (9 MB)
99 23:04:37.472844 progress 10 % (19 MB)
100 23:04:38.095608 progress 15 % (28 MB)
101 23:04:38.502469 progress 20 % (38 MB)
102 23:04:38.874363 progress 25 % (47 MB)
103 23:04:39.500361 progress 30 % (57 MB)
104 23:04:40.084251 progress 35 % (67 MB)
105 23:04:40.714634 progress 40 % (76 MB)
106 23:04:41.308155 progress 45 % (86 MB)
107 23:04:41.909425 progress 50 % (95 MB)
108 23:04:42.566995 progress 55 % (105 MB)
109 23:04:43.272523 progress 60 % (114 MB)
110 23:04:43.405723 progress 65 % (124 MB)
111 23:04:43.575449 progress 70 % (134 MB)
112 23:04:43.683930 progress 75 % (143 MB)
113 23:04:43.779460 progress 80 % (153 MB)
114 23:04:43.857006 progress 85 % (162 MB)
115 23:04:43.975337 progress 90 % (172 MB)
116 23:04:44.300642 progress 95 % (181 MB)
117 23:04:44.909420 progress 100 % (191 MB)
118 23:04:44.914687 191 MB downloaded in 8.54 s (22.42 MB/s)
119 23:04:44.914955 end: 1.4.1 http-download (duration 00:00:09) [common]
121 23:04:44.915225 end: 1.4 download-retry (duration 00:00:09) [common]
122 23:04:44.915315 start: 1.5 download-retry (timeout 00:09:51) [common]
123 23:04:44.915403 start: 1.5.1 http-download (timeout 00:09:51) [common]
124 23:04:44.915566 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.64-cip10/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 23:04:44.915637 saving as /var/lib/lava/dispatcher/tmp/12154385/tftp-deploy-cllkt166/modules/modules.tar
126 23:04:44.915700 total size: 8616152 (8 MB)
127 23:04:44.915765 Using unxz to decompress xz
128 23:04:45.176101 progress 0 % (0 MB)
129 23:04:45.198826 progress 5 % (0 MB)
130 23:04:45.223101 progress 10 % (0 MB)
131 23:04:45.247362 progress 15 % (1 MB)
132 23:04:45.271681 progress 20 % (1 MB)
133 23:04:45.296276 progress 25 % (2 MB)
134 23:04:45.322543 progress 30 % (2 MB)
135 23:04:45.349556 progress 35 % (2 MB)
136 23:04:45.373419 progress 40 % (3 MB)
137 23:04:45.398435 progress 45 % (3 MB)
138 23:04:45.424343 progress 50 % (4 MB)
139 23:04:45.449652 progress 55 % (4 MB)
140 23:04:45.476371 progress 60 % (4 MB)
141 23:04:45.503740 progress 65 % (5 MB)
142 23:04:45.532132 progress 70 % (5 MB)
143 23:04:45.556193 progress 75 % (6 MB)
144 23:04:45.583851 progress 80 % (6 MB)
145 23:04:45.610313 progress 85 % (7 MB)
146 23:04:45.639152 progress 90 % (7 MB)
147 23:04:45.669549 progress 95 % (7 MB)
148 23:04:45.698458 progress 100 % (8 MB)
149 23:04:45.705000 8 MB downloaded in 0.79 s (10.41 MB/s)
150 23:04:45.705289 end: 1.5.1 http-download (duration 00:00:01) [common]
152 23:04:45.705716 end: 1.5 download-retry (duration 00:00:01) [common]
153 23:04:45.705827 start: 1.6 prepare-tftp-overlay (timeout 00:09:50) [common]
154 23:04:45.705941 start: 1.6.1 extract-nfsrootfs (timeout 00:09:50) [common]
155 23:04:49.366497 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12154385/extract-nfsrootfs-p6jmt7b4
156 23:04:49.366693 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 23:04:49.366800 start: 1.6.2 lava-overlay (timeout 00:09:46) [common]
158 23:04:49.366962 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12154385/lava-overlay-svv3eerx
159 23:04:49.367097 makedir: /var/lib/lava/dispatcher/tmp/12154385/lava-overlay-svv3eerx/lava-12154385/bin
160 23:04:49.367201 makedir: /var/lib/lava/dispatcher/tmp/12154385/lava-overlay-svv3eerx/lava-12154385/tests
161 23:04:49.367302 makedir: /var/lib/lava/dispatcher/tmp/12154385/lava-overlay-svv3eerx/lava-12154385/results
162 23:04:49.367402 Creating /var/lib/lava/dispatcher/tmp/12154385/lava-overlay-svv3eerx/lava-12154385/bin/lava-add-keys
163 23:04:49.367550 Creating /var/lib/lava/dispatcher/tmp/12154385/lava-overlay-svv3eerx/lava-12154385/bin/lava-add-sources
164 23:04:49.367685 Creating /var/lib/lava/dispatcher/tmp/12154385/lava-overlay-svv3eerx/lava-12154385/bin/lava-background-process-start
165 23:04:49.367816 Creating /var/lib/lava/dispatcher/tmp/12154385/lava-overlay-svv3eerx/lava-12154385/bin/lava-background-process-stop
166 23:04:49.367942 Creating /var/lib/lava/dispatcher/tmp/12154385/lava-overlay-svv3eerx/lava-12154385/bin/lava-common-functions
167 23:04:49.368069 Creating /var/lib/lava/dispatcher/tmp/12154385/lava-overlay-svv3eerx/lava-12154385/bin/lava-echo-ipv4
168 23:04:49.368195 Creating /var/lib/lava/dispatcher/tmp/12154385/lava-overlay-svv3eerx/lava-12154385/bin/lava-install-packages
169 23:04:49.368320 Creating /var/lib/lava/dispatcher/tmp/12154385/lava-overlay-svv3eerx/lava-12154385/bin/lava-installed-packages
170 23:04:49.368446 Creating /var/lib/lava/dispatcher/tmp/12154385/lava-overlay-svv3eerx/lava-12154385/bin/lava-os-build
171 23:04:49.368571 Creating /var/lib/lava/dispatcher/tmp/12154385/lava-overlay-svv3eerx/lava-12154385/bin/lava-probe-channel
172 23:04:49.368698 Creating /var/lib/lava/dispatcher/tmp/12154385/lava-overlay-svv3eerx/lava-12154385/bin/lava-probe-ip
173 23:04:49.368824 Creating /var/lib/lava/dispatcher/tmp/12154385/lava-overlay-svv3eerx/lava-12154385/bin/lava-target-ip
174 23:04:49.368949 Creating /var/lib/lava/dispatcher/tmp/12154385/lava-overlay-svv3eerx/lava-12154385/bin/lava-target-mac
175 23:04:49.369077 Creating /var/lib/lava/dispatcher/tmp/12154385/lava-overlay-svv3eerx/lava-12154385/bin/lava-target-storage
176 23:04:49.369204 Creating /var/lib/lava/dispatcher/tmp/12154385/lava-overlay-svv3eerx/lava-12154385/bin/lava-test-case
177 23:04:49.369333 Creating /var/lib/lava/dispatcher/tmp/12154385/lava-overlay-svv3eerx/lava-12154385/bin/lava-test-event
178 23:04:49.369458 Creating /var/lib/lava/dispatcher/tmp/12154385/lava-overlay-svv3eerx/lava-12154385/bin/lava-test-feedback
179 23:04:49.369610 Creating /var/lib/lava/dispatcher/tmp/12154385/lava-overlay-svv3eerx/lava-12154385/bin/lava-test-raise
180 23:04:49.369749 Creating /var/lib/lava/dispatcher/tmp/12154385/lava-overlay-svv3eerx/lava-12154385/bin/lava-test-reference
181 23:04:49.369875 Creating /var/lib/lava/dispatcher/tmp/12154385/lava-overlay-svv3eerx/lava-12154385/bin/lava-test-runner
182 23:04:49.369999 Creating /var/lib/lava/dispatcher/tmp/12154385/lava-overlay-svv3eerx/lava-12154385/bin/lava-test-set
183 23:04:49.370126 Creating /var/lib/lava/dispatcher/tmp/12154385/lava-overlay-svv3eerx/lava-12154385/bin/lava-test-shell
184 23:04:49.370252 Updating /var/lib/lava/dispatcher/tmp/12154385/lava-overlay-svv3eerx/lava-12154385/bin/lava-add-keys (debian)
185 23:04:49.370406 Updating /var/lib/lava/dispatcher/tmp/12154385/lava-overlay-svv3eerx/lava-12154385/bin/lava-add-sources (debian)
186 23:04:49.370598 Updating /var/lib/lava/dispatcher/tmp/12154385/lava-overlay-svv3eerx/lava-12154385/bin/lava-install-packages (debian)
187 23:04:49.370743 Updating /var/lib/lava/dispatcher/tmp/12154385/lava-overlay-svv3eerx/lava-12154385/bin/lava-installed-packages (debian)
188 23:04:49.370887 Updating /var/lib/lava/dispatcher/tmp/12154385/lava-overlay-svv3eerx/lava-12154385/bin/lava-os-build (debian)
189 23:04:49.371014 Creating /var/lib/lava/dispatcher/tmp/12154385/lava-overlay-svv3eerx/lava-12154385/environment
190 23:04:49.371116 LAVA metadata
191 23:04:49.371187 - LAVA_JOB_ID=12154385
192 23:04:49.371251 - LAVA_DISPATCHER_IP=192.168.201.1
193 23:04:49.371368 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:46) [common]
194 23:04:49.371435 skipped lava-vland-overlay
195 23:04:49.371511 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 23:04:49.371591 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:46) [common]
197 23:04:49.371651 skipped lava-multinode-overlay
198 23:04:49.371723 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 23:04:49.371801 start: 1.6.2.3 test-definition (timeout 00:09:46) [common]
200 23:04:49.371877 Loading test definitions
201 23:04:49.371968 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:46) [common]
202 23:04:49.372040 Using /lava-12154385 at stage 0
203 23:04:49.372332 uuid=12154385_1.6.2.3.1 testdef=None
204 23:04:49.372419 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 23:04:49.372504 start: 1.6.2.3.2 test-overlay (timeout 00:09:46) [common]
206 23:04:49.372971 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 23:04:49.373188 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:46) [common]
209 23:04:49.373835 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 23:04:49.374066 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:46) [common]
212 23:04:49.374609 runner path: /var/lib/lava/dispatcher/tmp/12154385/lava-overlay-svv3eerx/lava-12154385/0/tests/0_timesync-off test_uuid 12154385_1.6.2.3.1
213 23:04:49.374768 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 23:04:49.374990 start: 1.6.2.3.5 git-repo-action (timeout 00:09:46) [common]
216 23:04:49.375064 Using /lava-12154385 at stage 0
217 23:04:49.375163 Fetching tests from https://github.com/kernelci/test-definitions.git
218 23:04:49.375241 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/12154385/lava-overlay-svv3eerx/lava-12154385/0/tests/1_kselftest-arm64'
219 23:04:54.486164 Running '/usr/bin/git checkout kernelci.org
220 23:04:54.639890 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12154385/lava-overlay-svv3eerx/lava-12154385/0/tests/1_kselftest-arm64/automated/linux/kselftest/kselftest.yaml
221 23:04:54.640662 uuid=12154385_1.6.2.3.5 testdef=None
222 23:04:54.640855 end: 1.6.2.3.5 git-repo-action (duration 00:00:05) [common]
224 23:04:54.641120 start: 1.6.2.3.6 test-overlay (timeout 00:09:41) [common]
225 23:04:54.641918 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 23:04:54.642158 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:41) [common]
228 23:04:54.643166 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 23:04:54.643407 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:41) [common]
231 23:04:54.644359 runner path: /var/lib/lava/dispatcher/tmp/12154385/lava-overlay-svv3eerx/lava-12154385/0/tests/1_kselftest-arm64 test_uuid 12154385_1.6.2.3.5
232 23:04:54.644455 BOARD='mt8192-asurada-spherion-r0'
233 23:04:54.644522 BRANCH='cip'
234 23:04:54.644583 SKIPFILE='/dev/null'
235 23:04:54.644641 SKIP_INSTALL='True'
236 23:04:54.644698 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.64-cip10/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 23:04:54.644759 TST_CASENAME=''
238 23:04:54.644816 TST_CMDFILES='arm64'
239 23:04:54.644966 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 23:04:54.645192 Creating lava-test-runner.conf files
242 23:04:54.645258 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12154385/lava-overlay-svv3eerx/lava-12154385/0 for stage 0
243 23:04:54.645356 - 0_timesync-off
244 23:04:54.645428 - 1_kselftest-arm64
245 23:04:54.645527 end: 1.6.2.3 test-definition (duration 00:00:05) [common]
246 23:04:54.645628 start: 1.6.2.4 compress-overlay (timeout 00:09:41) [common]
247 23:05:02.710610 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 23:05:02.710773 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:33) [common]
249 23:05:02.710868 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 23:05:02.710971 end: 1.6.2 lava-overlay (duration 00:00:13) [common]
251 23:05:02.711059 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:33) [common]
252 23:05:02.833752 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 23:05:02.834164 start: 1.6.4 extract-modules (timeout 00:09:33) [common]
254 23:05:02.834287 extracting modules file /var/lib/lava/dispatcher/tmp/12154385/tftp-deploy-cllkt166/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12154385/extract-nfsrootfs-p6jmt7b4
255 23:05:03.062863 extracting modules file /var/lib/lava/dispatcher/tmp/12154385/tftp-deploy-cllkt166/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12154385/extract-overlay-ramdisk-hui47phn/ramdisk
256 23:05:03.297917 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 23:05:03.298088 start: 1.6.5 apply-overlay-tftp (timeout 00:09:33) [common]
258 23:05:03.298190 [common] Applying overlay to NFS
259 23:05:03.298261 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12154385/compress-overlay-zfe4u4l4/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12154385/extract-nfsrootfs-p6jmt7b4
260 23:05:04.239989 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 23:05:04.240166 start: 1.6.6 configure-preseed-file (timeout 00:09:32) [common]
262 23:05:04.240265 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 23:05:04.240357 start: 1.6.7 compress-ramdisk (timeout 00:09:32) [common]
264 23:05:04.240445 Building ramdisk /var/lib/lava/dispatcher/tmp/12154385/extract-overlay-ramdisk-hui47phn/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12154385/extract-overlay-ramdisk-hui47phn/ramdisk
265 23:05:04.795271 >> 119410 blocks
266 23:05:07.127069 rename /var/lib/lava/dispatcher/tmp/12154385/extract-overlay-ramdisk-hui47phn/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12154385/tftp-deploy-cllkt166/ramdisk/ramdisk.cpio.gz
267 23:05:07.127545 end: 1.6.7 compress-ramdisk (duration 00:00:03) [common]
268 23:05:07.127672 start: 1.6.8 prepare-kernel (timeout 00:09:29) [common]
269 23:05:07.127780 start: 1.6.8.1 prepare-fit (timeout 00:09:29) [common]
270 23:05:07.127887 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12154385/tftp-deploy-cllkt166/kernel/Image'
271 23:05:20.864384 Returned 0 in 13 seconds
272 23:05:20.965071 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12154385/tftp-deploy-cllkt166/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12154385/tftp-deploy-cllkt166/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12154385/tftp-deploy-cllkt166/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12154385/tftp-deploy-cllkt166/kernel/image.itb
273 23:05:21.313458 output: FIT description: Kernel Image image with one or more FDT blobs
274 23:05:21.313889 output: Created: Fri Dec 1 23:05:21 2023
275 23:05:21.313963 output: Image 0 (kernel-1)
276 23:05:21.314030 output: Description:
277 23:05:21.314092 output: Created: Fri Dec 1 23:05:21 2023
278 23:05:21.314152 output: Type: Kernel Image
279 23:05:21.314210 output: Compression: lzma compressed
280 23:05:21.314270 output: Data Size: 11043984 Bytes = 10785.14 KiB = 10.53 MiB
281 23:05:21.314328 output: Architecture: AArch64
282 23:05:21.314386 output: OS: Linux
283 23:05:21.314445 output: Load Address: 0x00000000
284 23:05:21.314504 output: Entry Point: 0x00000000
285 23:05:21.314561 output: Hash algo: crc32
286 23:05:21.314616 output: Hash value: 36c84243
287 23:05:21.314674 output: Image 1 (fdt-1)
288 23:05:21.314729 output: Description: mt8192-asurada-spherion-r0
289 23:05:21.314783 output: Created: Fri Dec 1 23:05:21 2023
290 23:05:21.314836 output: Type: Flat Device Tree
291 23:05:21.314889 output: Compression: uncompressed
292 23:05:21.314942 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 23:05:21.314994 output: Architecture: AArch64
294 23:05:21.315047 output: Hash algo: crc32
295 23:05:21.315099 output: Hash value: cc4352de
296 23:05:21.315151 output: Image 2 (ramdisk-1)
297 23:05:21.315203 output: Description: unavailable
298 23:05:21.315256 output: Created: Fri Dec 1 23:05:21 2023
299 23:05:21.315308 output: Type: RAMDisk Image
300 23:05:21.315361 output: Compression: Unknown Compression
301 23:05:21.315413 output: Data Size: 17792366 Bytes = 17375.36 KiB = 16.97 MiB
302 23:05:21.315466 output: Architecture: AArch64
303 23:05:21.315518 output: OS: Linux
304 23:05:21.315570 output: Load Address: unavailable
305 23:05:21.315622 output: Entry Point: unavailable
306 23:05:21.315674 output: Hash algo: crc32
307 23:05:21.315726 output: Hash value: 532c9859
308 23:05:21.315777 output: Default Configuration: 'conf-1'
309 23:05:21.315851 output: Configuration 0 (conf-1)
310 23:05:21.315945 output: Description: mt8192-asurada-spherion-r0
311 23:05:21.316004 output: Kernel: kernel-1
312 23:05:21.316059 output: Init Ramdisk: ramdisk-1
313 23:05:21.316112 output: FDT: fdt-1
314 23:05:21.316165 output: Loadables: kernel-1
315 23:05:21.316217 output:
316 23:05:21.316418 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
317 23:05:21.316517 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
318 23:05:21.316627 end: 1.6 prepare-tftp-overlay (duration 00:00:36) [common]
319 23:05:21.316722 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:14) [common]
320 23:05:21.316805 No LXC device requested
321 23:05:21.316885 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 23:05:21.316968 start: 1.8 deploy-device-env (timeout 00:09:14) [common]
323 23:05:21.317046 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 23:05:21.317112 Checking files for TFTP limit of 4294967296 bytes.
325 23:05:21.317678 end: 1 tftp-deploy (duration 00:00:46) [common]
326 23:05:21.317779 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 23:05:21.317872 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 23:05:21.318000 substitutions:
329 23:05:21.318067 - {DTB}: 12154385/tftp-deploy-cllkt166/dtb/mt8192-asurada-spherion-r0.dtb
330 23:05:21.318131 - {INITRD}: 12154385/tftp-deploy-cllkt166/ramdisk/ramdisk.cpio.gz
331 23:05:21.318189 - {KERNEL}: 12154385/tftp-deploy-cllkt166/kernel/Image
332 23:05:21.318247 - {LAVA_MAC}: None
333 23:05:21.318303 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12154385/extract-nfsrootfs-p6jmt7b4
334 23:05:21.318358 - {NFS_SERVER_IP}: 192.168.201.1
335 23:05:21.318412 - {PRESEED_CONFIG}: None
336 23:05:21.318466 - {PRESEED_LOCAL}: None
337 23:05:21.318520 - {RAMDISK}: 12154385/tftp-deploy-cllkt166/ramdisk/ramdisk.cpio.gz
338 23:05:21.318573 - {ROOT_PART}: None
339 23:05:21.318626 - {ROOT}: None
340 23:05:21.318679 - {SERVER_IP}: 192.168.201.1
341 23:05:21.318732 - {TEE}: None
342 23:05:21.318785 Parsed boot commands:
343 23:05:21.318837 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 23:05:21.319025 Parsed boot commands: tftpboot 192.168.201.1 12154385/tftp-deploy-cllkt166/kernel/image.itb 12154385/tftp-deploy-cllkt166/kernel/cmdline
345 23:05:21.319113 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 23:05:21.319196 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 23:05:21.319287 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 23:05:21.319373 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 23:05:21.319442 Not connected, no need to disconnect.
350 23:05:21.319515 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 23:05:21.319595 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 23:05:21.319660 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
353 23:05:21.323871 Setting prompt string to ['lava-test: # ']
354 23:05:21.324271 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 23:05:21.324377 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 23:05:21.324520 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 23:05:21.324615 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 23:05:21.324842 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
359 23:05:26.459496 >> Command sent successfully.
360 23:05:26.461934 Returned 0 in 5 seconds
361 23:05:26.562335 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 23:05:26.562763 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 23:05:26.562903 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 23:05:26.563030 Setting prompt string to 'Starting depthcharge on Spherion...'
366 23:05:26.563128 Changing prompt to 'Starting depthcharge on Spherion...'
367 23:05:26.563228 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 23:05:26.563641 [Enter `^Ec?' for help]
369 23:05:26.734368
370 23:05:26.734523
371 23:05:26.734594 F0: 102B 0000
372 23:05:26.734674
373 23:05:26.734736 F3: 1001 0000 [0200]
374 23:05:26.734795
375 23:05:26.738025 F3: 1001 0000
376 23:05:26.738109
377 23:05:26.738180 F7: 102D 0000
378 23:05:26.738251
379 23:05:26.741545 F1: 0000 0000
380 23:05:26.741690
381 23:05:26.741760 V0: 0000 0000 [0001]
382 23:05:26.741827
383 23:05:26.741911 00: 0007 8000
384 23:05:26.741983
385 23:05:26.745477 01: 0000 0000
386 23:05:26.745611
387 23:05:26.745722 BP: 0C00 0209 [0000]
388 23:05:26.745813
389 23:05:26.749352 G0: 1182 0000
390 23:05:26.749452
391 23:05:26.749541 EC: 0000 0021 [4000]
392 23:05:26.749702
393 23:05:26.752712 S7: 0000 0000 [0000]
394 23:05:26.752816
395 23:05:26.752910 CC: 0000 0000 [0001]
396 23:05:26.752997
397 23:05:26.756564 T0: 0000 0040 [010F]
398 23:05:26.756670
399 23:05:26.756762 Jump to BL
400 23:05:26.756859
401 23:05:26.781166
402 23:05:26.781297
403 23:05:26.781395
404 23:05:26.789154 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 23:05:26.792411 ARM64: Exception handlers installed.
406 23:05:26.796538 ARM64: Testing exception
407 23:05:26.800387 ARM64: Done test exception
408 23:05:26.804287 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 23:05:26.815549 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 23:05:26.822722 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 23:05:26.833043 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 23:05:26.839278 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 23:05:26.846479 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 23:05:26.858197 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 23:05:26.864653 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 23:05:26.884560 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 23:05:26.887178 WDT: Last reset was cold boot
418 23:05:26.891030 SPI1(PAD0) initialized at 2873684 Hz
419 23:05:26.894413 SPI5(PAD0) initialized at 992727 Hz
420 23:05:26.897608 VBOOT: Loading verstage.
421 23:05:26.904364 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 23:05:26.908347 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 23:05:26.911561 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 23:05:26.914778 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 23:05:26.921674 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 23:05:26.928568 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 23:05:26.939344 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 23:05:26.939457
429 23:05:26.939544
430 23:05:26.949798 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 23:05:26.953289 ARM64: Exception handlers installed.
432 23:05:26.953409 ARM64: Testing exception
433 23:05:26.956410 ARM64: Done test exception
434 23:05:26.960137 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 23:05:26.966775 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 23:05:26.979690 Probing TPM: . done!
437 23:05:26.979807 TPM ready after 0 ms
438 23:05:26.987095 Connected to device vid:did:rid of 1ae0:0028:00
439 23:05:26.993881 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
440 23:05:27.054927 Initialized TPM device CR50 revision 0
441 23:05:27.065375 tlcl_send_startup: Startup return code is 0
442 23:05:27.065504 TPM: setup succeeded
443 23:05:27.076798 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 23:05:27.085605 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 23:05:27.099421 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 23:05:27.106931 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 23:05:27.109508 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 23:05:27.113708 in-header: 03 07 00 00 08 00 00 00
449 23:05:27.117441 in-data: aa e4 47 04 13 02 00 00
450 23:05:27.120705 Chrome EC: UHEPI supported
451 23:05:27.127884 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 23:05:27.131821 in-header: 03 95 00 00 08 00 00 00
453 23:05:27.135709 in-data: 18 20 20 08 00 00 00 00
454 23:05:27.135796 Phase 1
455 23:05:27.138796 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 23:05:27.146532 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 23:05:27.150134 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 23:05:27.154148 Recovery requested (1009000e)
459 23:05:27.162905 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 23:05:27.168089 tlcl_extend: response is 0
461 23:05:27.177267 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 23:05:27.183092 tlcl_extend: response is 0
463 23:05:27.190252 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 23:05:27.209587 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
465 23:05:27.216044 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 23:05:27.216163
467 23:05:27.216262
468 23:05:27.226445 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 23:05:27.229554 ARM64: Exception handlers installed.
470 23:05:27.232676 ARM64: Testing exception
471 23:05:27.232756 ARM64: Done test exception
472 23:05:27.255330 pmic_efuse_setting: Set efuses in 11 msecs
473 23:05:27.258638 pmwrap_interface_init: Select PMIF_VLD_RDY
474 23:05:27.265249 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 23:05:27.268608 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 23:05:27.276387 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 23:05:27.280081 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 23:05:27.283312 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 23:05:27.287203 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 23:05:27.294814 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 23:05:27.298687 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 23:05:27.302251 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 23:05:27.305930 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 23:05:27.313340 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 23:05:27.317360 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 23:05:27.320347 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 23:05:27.328101 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 23:05:27.331919 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 23:05:27.339672 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 23:05:27.342791 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 23:05:27.350458 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 23:05:27.354471 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 23:05:27.361356 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 23:05:27.368826 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 23:05:27.372729 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 23:05:27.380389 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 23:05:27.383801 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 23:05:27.387627 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 23:05:27.394918 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 23:05:27.398270 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 23:05:27.405886 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 23:05:27.409567 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 23:05:27.413736 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 23:05:27.420107 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 23:05:27.423961 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 23:05:27.431051 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 23:05:27.435043 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 23:05:27.438125 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 23:05:27.445790 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 23:05:27.449552 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 23:05:27.453985 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 23:05:27.457160 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 23:05:27.464893 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 23:05:27.468967 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 23:05:27.472155 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 23:05:27.475977 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 23:05:27.479779 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 23:05:27.486880 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 23:05:27.490671 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 23:05:27.494276 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 23:05:27.498405 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 23:05:27.502035 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 23:05:27.505622 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 23:05:27.508915 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 23:05:27.520595 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 23:05:27.528309 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 23:05:27.532135 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 23:05:27.539304 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 23:05:27.546823 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 23:05:27.553901 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 23:05:27.558043 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 23:05:27.561418 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 23:05:27.568453 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x29
534 23:05:27.572178 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 23:05:27.580735 [RTC]rtc_osc_init,62: osc32con val = 0xde70
536 23:05:27.583939 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 23:05:27.593676 [RTC]rtc_get_frequency_meter,154: input=15, output=760
538 23:05:27.602660 [RTC]rtc_get_frequency_meter,154: input=23, output=943
539 23:05:27.611525 [RTC]rtc_get_frequency_meter,154: input=19, output=851
540 23:05:27.621480 [RTC]rtc_get_frequency_meter,154: input=17, output=805
541 23:05:27.631323 [RTC]rtc_get_frequency_meter,154: input=16, output=783
542 23:05:27.640218 [RTC]rtc_get_frequency_meter,154: input=16, output=783
543 23:05:27.650497 [RTC]rtc_get_frequency_meter,154: input=17, output=805
544 23:05:27.654423 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
545 23:05:27.658214 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
546 23:05:27.661735 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 23:05:27.668950 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
548 23:05:27.672732 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 23:05:27.676137 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
550 23:05:27.679930 ADC[4]: Raw value=905834 ID=7
551 23:05:27.680066 ADC[3]: Raw value=213441 ID=1
552 23:05:27.683500 RAM Code: 0x71
553 23:05:27.687095 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 23:05:27.690552 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 23:05:27.702560 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 23:05:27.706442 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 23:05:27.709192 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 23:05:27.713424 in-header: 03 07 00 00 08 00 00 00
559 23:05:27.717218 in-data: aa e4 47 04 13 02 00 00
560 23:05:27.720741 Chrome EC: UHEPI supported
561 23:05:27.728625 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 23:05:27.732194 in-header: 03 95 00 00 08 00 00 00
563 23:05:27.732279 in-data: 18 20 20 08 00 00 00 00
564 23:05:27.736171 MRC: failed to locate region type 0.
565 23:05:27.743302 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 23:05:27.747362 DRAM-K: Running full calibration
567 23:05:27.754462 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 23:05:27.754599 header.status = 0x0
569 23:05:27.758127 header.version = 0x6 (expected: 0x6)
570 23:05:27.761665 header.size = 0xd00 (expected: 0xd00)
571 23:05:27.761795 header.flags = 0x0
572 23:05:27.768714 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 23:05:27.786775 read SPI 0x72590 0x1c583: 12497 us, 9290 KB/s, 74.320 Mbps
574 23:05:27.794269 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 23:05:27.798451 dram_init: ddr_geometry: 2
576 23:05:27.798572 [EMI] MDL number = 2
577 23:05:27.801610 [EMI] Get MDL freq = 0
578 23:05:27.801692 dram_init: ddr_type: 0
579 23:05:27.805038 is_discrete_lpddr4: 1
580 23:05:27.808923 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 23:05:27.809037
582 23:05:27.809132
583 23:05:27.812390 [Bian_co] ETT version 0.0.0.1
584 23:05:27.816210 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 23:05:27.816327
586 23:05:27.820334 dramc_set_vcore_voltage set vcore to 650000
587 23:05:27.820459 Read voltage for 800, 4
588 23:05:27.824139 Vio18 = 0
589 23:05:27.824250 Vcore = 650000
590 23:05:27.824345 Vdram = 0
591 23:05:27.824450 Vddq = 0
592 23:05:27.827966 Vmddr = 0
593 23:05:27.828071 dram_init: config_dvfs: 1
594 23:05:27.835206 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 23:05:27.839350 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 23:05:27.842357 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
597 23:05:27.846748 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
598 23:05:27.849926 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
599 23:05:27.853520 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
600 23:05:27.856734 MEM_TYPE=3, freq_sel=18
601 23:05:27.860227 sv_algorithm_assistance_LP4_1600
602 23:05:27.863854 ============ PULL DRAM RESETB DOWN ============
603 23:05:27.867360 ========== PULL DRAM RESETB DOWN end =========
604 23:05:27.874513 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 23:05:27.874607 ===================================
606 23:05:27.877833 LPDDR4 DRAM CONFIGURATION
607 23:05:27.881672 ===================================
608 23:05:27.885986 EX_ROW_EN[0] = 0x0
609 23:05:27.886083 EX_ROW_EN[1] = 0x0
610 23:05:27.886156 LP4Y_EN = 0x0
611 23:05:27.889894 WORK_FSP = 0x0
612 23:05:27.889986 WL = 0x2
613 23:05:27.893764 RL = 0x2
614 23:05:27.893850 BL = 0x2
615 23:05:27.896880 RPST = 0x0
616 23:05:27.896961 RD_PRE = 0x0
617 23:05:27.900142 WR_PRE = 0x1
618 23:05:27.900216 WR_PST = 0x0
619 23:05:27.903481 DBI_WR = 0x0
620 23:05:27.903552 DBI_RD = 0x0
621 23:05:27.906615 OTF = 0x1
622 23:05:27.910514 ===================================
623 23:05:27.913674 ===================================
624 23:05:27.913744 ANA top config
625 23:05:27.917682 ===================================
626 23:05:27.920899 DLL_ASYNC_EN = 0
627 23:05:27.924944 ALL_SLAVE_EN = 1
628 23:05:27.925024 NEW_RANK_MODE = 1
629 23:05:27.928155 DLL_IDLE_MODE = 1
630 23:05:27.931052 LP45_APHY_COMB_EN = 1
631 23:05:27.934816 TX_ODT_DIS = 1
632 23:05:27.934894 NEW_8X_MODE = 1
633 23:05:27.938146 ===================================
634 23:05:27.942133 ===================================
635 23:05:27.945343 data_rate = 1600
636 23:05:27.948550 CKR = 1
637 23:05:27.951794 DQ_P2S_RATIO = 8
638 23:05:27.955381 ===================================
639 23:05:27.955492 CA_P2S_RATIO = 8
640 23:05:27.958720 DQ_CA_OPEN = 0
641 23:05:27.962224 DQ_SEMI_OPEN = 0
642 23:05:27.965540 CA_SEMI_OPEN = 0
643 23:05:27.968872 CA_FULL_RATE = 0
644 23:05:27.968950 DQ_CKDIV4_EN = 1
645 23:05:27.972059 CA_CKDIV4_EN = 1
646 23:05:27.975769 CA_PREDIV_EN = 0
647 23:05:27.978659 PH8_DLY = 0
648 23:05:27.982238 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 23:05:27.985861 DQ_AAMCK_DIV = 4
650 23:05:27.985946 CA_AAMCK_DIV = 4
651 23:05:27.989013 CA_ADMCK_DIV = 4
652 23:05:27.991907 DQ_TRACK_CA_EN = 0
653 23:05:27.995186 CA_PICK = 800
654 23:05:27.998826 CA_MCKIO = 800
655 23:05:28.002783 MCKIO_SEMI = 0
656 23:05:28.002885 PLL_FREQ = 3068
657 23:05:28.006268 DQ_UI_PI_RATIO = 32
658 23:05:28.010021 CA_UI_PI_RATIO = 0
659 23:05:28.014057 ===================================
660 23:05:28.017994 ===================================
661 23:05:28.018073 memory_type:LPDDR4
662 23:05:28.021401 GP_NUM : 10
663 23:05:28.021482 SRAM_EN : 1
664 23:05:28.025248 MD32_EN : 0
665 23:05:28.029259 ===================================
666 23:05:28.029342 [ANA_INIT] >>>>>>>>>>>>>>
667 23:05:28.033395 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 23:05:28.037119 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 23:05:28.040251 ===================================
670 23:05:28.043577 data_rate = 1600,PCW = 0X7600
671 23:05:28.046793 ===================================
672 23:05:28.050029 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 23:05:28.053748 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 23:05:28.059991 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 23:05:28.063820 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 23:05:28.067061 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 23:05:28.073758 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 23:05:28.073848 [ANA_INIT] flow start
679 23:05:28.077094 [ANA_INIT] PLL >>>>>>>>
680 23:05:28.080542 [ANA_INIT] PLL <<<<<<<<
681 23:05:28.080617 [ANA_INIT] MIDPI >>>>>>>>
682 23:05:28.083518 [ANA_INIT] MIDPI <<<<<<<<
683 23:05:28.087002 [ANA_INIT] DLL >>>>>>>>
684 23:05:28.087085 [ANA_INIT] flow end
685 23:05:28.090201 ============ LP4 DIFF to SE enter ============
686 23:05:28.096827 ============ LP4 DIFF to SE exit ============
687 23:05:28.096918 [ANA_INIT] <<<<<<<<<<<<<
688 23:05:28.100610 [Flow] Enable top DCM control >>>>>
689 23:05:28.103186 [Flow] Enable top DCM control <<<<<
690 23:05:28.107172 Enable DLL master slave shuffle
691 23:05:28.113400 ==============================================================
692 23:05:28.113509 Gating Mode config
693 23:05:28.120162 ==============================================================
694 23:05:28.123731 Config description:
695 23:05:28.130316 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 23:05:28.136692 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 23:05:28.144055 SELPH_MODE 0: By rank 1: By Phase
698 23:05:28.150268 ==============================================================
699 23:05:28.153734 GAT_TRACK_EN = 1
700 23:05:28.153830 RX_GATING_MODE = 2
701 23:05:28.156931 RX_GATING_TRACK_MODE = 2
702 23:05:28.160149 SELPH_MODE = 1
703 23:05:28.163277 PICG_EARLY_EN = 1
704 23:05:28.166949 VALID_LAT_VALUE = 1
705 23:05:28.173690 ==============================================================
706 23:05:28.176948 Enter into Gating configuration >>>>
707 23:05:28.180365 Exit from Gating configuration <<<<
708 23:05:28.183570 Enter into DVFS_PRE_config >>>>>
709 23:05:28.193739 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 23:05:28.196699 Exit from DVFS_PRE_config <<<<<
711 23:05:28.200069 Enter into PICG configuration >>>>
712 23:05:28.203793 Exit from PICG configuration <<<<
713 23:05:28.207208 [RX_INPUT] configuration >>>>>
714 23:05:28.207283 [RX_INPUT] configuration <<<<<
715 23:05:28.213790 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 23:05:28.220156 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 23:05:28.223746 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 23:05:28.230412 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 23:05:28.236826 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 23:05:28.243455 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 23:05:28.247235 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 23:05:28.250590 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 23:05:28.257481 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 23:05:28.260622 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 23:05:28.263912 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 23:05:28.266900 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 23:05:28.270477 ===================================
728 23:05:28.274060 LPDDR4 DRAM CONFIGURATION
729 23:05:28.277682 ===================================
730 23:05:28.280702 EX_ROW_EN[0] = 0x0
731 23:05:28.280811 EX_ROW_EN[1] = 0x0
732 23:05:28.283871 LP4Y_EN = 0x0
733 23:05:28.283953 WORK_FSP = 0x0
734 23:05:28.287548 WL = 0x2
735 23:05:28.287629 RL = 0x2
736 23:05:28.290886 BL = 0x2
737 23:05:28.290972 RPST = 0x0
738 23:05:28.294253 RD_PRE = 0x0
739 23:05:28.294343 WR_PRE = 0x1
740 23:05:28.297270 WR_PST = 0x0
741 23:05:28.297379 DBI_WR = 0x0
742 23:05:28.300509 DBI_RD = 0x0
743 23:05:28.300592 OTF = 0x1
744 23:05:28.304373 ===================================
745 23:05:28.310815 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 23:05:28.314080 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 23:05:28.317226 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 23:05:28.320502 ===================================
749 23:05:28.323798 LPDDR4 DRAM CONFIGURATION
750 23:05:28.327634 ===================================
751 23:05:28.330567 EX_ROW_EN[0] = 0x10
752 23:05:28.330649 EX_ROW_EN[1] = 0x0
753 23:05:28.334433 LP4Y_EN = 0x0
754 23:05:28.334515 WORK_FSP = 0x0
755 23:05:28.337686 WL = 0x2
756 23:05:28.337768 RL = 0x2
757 23:05:28.340745 BL = 0x2
758 23:05:28.340836 RPST = 0x0
759 23:05:28.343760 RD_PRE = 0x0
760 23:05:28.343842 WR_PRE = 0x1
761 23:05:28.347365 WR_PST = 0x0
762 23:05:28.347447 DBI_WR = 0x0
763 23:05:28.350434 DBI_RD = 0x0
764 23:05:28.350516 OTF = 0x1
765 23:05:28.354367 ===================================
766 23:05:28.360449 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 23:05:28.364961 nWR fixed to 40
768 23:05:28.368669 [ModeRegInit_LP4] CH0 RK0
769 23:05:28.368751 [ModeRegInit_LP4] CH0 RK1
770 23:05:28.371851 [ModeRegInit_LP4] CH1 RK0
771 23:05:28.374791 [ModeRegInit_LP4] CH1 RK1
772 23:05:28.374880 match AC timing 13
773 23:05:28.381653 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 23:05:28.384949 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 23:05:28.388269 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 23:05:28.395428 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 23:05:28.398781 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 23:05:28.398888 [EMI DOE] emi_dcm 0
779 23:05:28.405081 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 23:05:28.405184 ==
781 23:05:28.408710 Dram Type= 6, Freq= 0, CH_0, rank 0
782 23:05:28.411798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 23:05:28.411879 ==
784 23:05:28.418714 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 23:05:28.425099 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 23:05:28.432172 [CA 0] Center 36 (6~67) winsize 62
787 23:05:28.435908 [CA 1] Center 36 (6~67) winsize 62
788 23:05:28.439040 [CA 2] Center 34 (4~65) winsize 62
789 23:05:28.442485 [CA 3] Center 34 (4~64) winsize 61
790 23:05:28.445688 [CA 4] Center 33 (2~64) winsize 63
791 23:05:28.448909 [CA 5] Center 32 (2~62) winsize 61
792 23:05:28.449016
793 23:05:28.452304 [CmdBusTrainingLP45] Vref(ca) range 1: 34
794 23:05:28.452422
795 23:05:28.455838 [CATrainingPosCal] consider 1 rank data
796 23:05:28.458893 u2DelayCellTimex100 = 270/100 ps
797 23:05:28.462594 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
798 23:05:28.465627 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
799 23:05:28.472237 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
800 23:05:28.475735 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
801 23:05:28.478752 CA4 delay=33 (2~64),Diff = 1 PI (7 cell)
802 23:05:28.482379 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
803 23:05:28.482487
804 23:05:28.485524 CA PerBit enable=1, Macro0, CA PI delay=32
805 23:05:28.485632
806 23:05:28.489216 [CBTSetCACLKResult] CA Dly = 32
807 23:05:28.489297 CS Dly: 4 (0~35)
808 23:05:28.492592 ==
809 23:05:28.492675 Dram Type= 6, Freq= 0, CH_0, rank 1
810 23:05:28.498949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 23:05:28.499032 ==
812 23:05:28.502144 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 23:05:28.509073 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 23:05:28.518967 [CA 0] Center 36 (6~67) winsize 62
815 23:05:28.521907 [CA 1] Center 36 (6~67) winsize 62
816 23:05:28.525482 [CA 2] Center 34 (4~65) winsize 62
817 23:05:28.528605 [CA 3] Center 33 (3~64) winsize 62
818 23:05:28.531734 [CA 4] Center 33 (3~63) winsize 61
819 23:05:28.535271 [CA 5] Center 32 (2~63) winsize 62
820 23:05:28.535354
821 23:05:28.538581 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 23:05:28.538673
823 23:05:28.542230 [CATrainingPosCal] consider 2 rank data
824 23:05:28.545433 u2DelayCellTimex100 = 270/100 ps
825 23:05:28.548723 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
826 23:05:28.551913 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
827 23:05:28.558537 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
828 23:05:28.562423 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
829 23:05:28.565302 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
830 23:05:28.568535 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
831 23:05:28.568617
832 23:05:28.572092 CA PerBit enable=1, Macro0, CA PI delay=32
833 23:05:28.572174
834 23:05:28.575261 [CBTSetCACLKResult] CA Dly = 32
835 23:05:28.575381 CS Dly: 4 (0~36)
836 23:05:28.575478
837 23:05:28.578458 ----->DramcWriteLeveling(PI) begin...
838 23:05:28.582041 ==
839 23:05:28.582137 Dram Type= 6, Freq= 0, CH_0, rank 0
840 23:05:28.589443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 23:05:28.589562 ==
842 23:05:28.589765 Write leveling (Byte 0): 32 => 32
843 23:05:28.593568 Write leveling (Byte 1): 31 => 31
844 23:05:28.596817 DramcWriteLeveling(PI) end<-----
845 23:05:28.596893
846 23:05:28.596971 ==
847 23:05:28.601029 Dram Type= 6, Freq= 0, CH_0, rank 0
848 23:05:28.604030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 23:05:28.604124 ==
850 23:05:28.607405 [Gating] SW mode calibration
851 23:05:28.615269 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 23:05:28.618883 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 23:05:28.625628 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 23:05:28.628483 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
855 23:05:28.632146 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
856 23:05:28.639067 0 6 12 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
857 23:05:28.642199 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 23:05:28.645547 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 23:05:28.651961 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 23:05:28.655819 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 23:05:28.659031 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 23:05:28.665565 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 23:05:28.668463 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 23:05:28.672025 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 23:05:28.678576 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 23:05:28.682238 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 23:05:28.685410 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 23:05:28.692284 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 23:05:28.695065 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 23:05:28.698684 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
871 23:05:28.705044 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
872 23:05:28.708664 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 23:05:28.711991 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 23:05:28.715865 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 23:05:28.722236 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 23:05:28.725556 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 23:05:28.729205 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 23:05:28.735503 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 23:05:28.738750 0 9 8 | B1->B0 | 2323 3131 | 0 1 | (0 0) (0 0)
880 23:05:28.742248 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
881 23:05:28.749007 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 23:05:28.752298 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 23:05:28.755625 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 23:05:28.762097 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 23:05:28.765386 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 23:05:28.769425 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
887 23:05:28.772615 0 10 8 | B1->B0 | 2f2f 2626 | 0 0 | (0 0) (0 0)
888 23:05:28.779306 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
889 23:05:28.782451 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 23:05:28.785800 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 23:05:28.792153 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 23:05:28.795481 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 23:05:28.798914 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 23:05:28.805998 0 11 4 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
895 23:05:28.808852 0 11 8 | B1->B0 | 3030 3e3e | 0 0 | (0 0) (0 0)
896 23:05:28.812338 0 11 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
897 23:05:28.818924 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 23:05:28.822651 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 23:05:28.826045 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 23:05:28.832133 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 23:05:28.836008 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 23:05:28.839430 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
903 23:05:28.845846 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
904 23:05:28.849094 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
905 23:05:28.852365 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 23:05:28.858902 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 23:05:28.862043 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 23:05:28.866010 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 23:05:28.869039 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 23:05:28.875473 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 23:05:28.878705 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 23:05:28.882130 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 23:05:28.888578 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 23:05:28.892258 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 23:05:28.895741 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 23:05:28.902469 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 23:05:28.905506 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 23:05:28.908631 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
919 23:05:28.915449 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
920 23:05:28.918795 Total UI for P1: 0, mck2ui 16
921 23:05:28.922422 best dqsien dly found for B0: ( 0, 14, 4)
922 23:05:28.925207 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
923 23:05:28.928518 Total UI for P1: 0, mck2ui 16
924 23:05:28.932034 best dqsien dly found for B1: ( 0, 14, 8)
925 23:05:28.935716 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
926 23:05:28.939521 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
927 23:05:28.939635
928 23:05:28.943176 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
929 23:05:28.946504 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
930 23:05:28.949699 [Gating] SW calibration Done
931 23:05:28.949804 ==
932 23:05:28.953027 Dram Type= 6, Freq= 0, CH_0, rank 0
933 23:05:28.956397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 23:05:28.956502 ==
935 23:05:28.960045 RX Vref Scan: 0
936 23:05:28.960156
937 23:05:28.960252 RX Vref 0 -> 0, step: 1
938 23:05:28.960344
939 23:05:28.963093 RX Delay -130 -> 252, step: 16
940 23:05:28.966460 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
941 23:05:28.973119 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
942 23:05:28.976068 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
943 23:05:28.979339 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
944 23:05:28.983029 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
945 23:05:28.986220 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
946 23:05:28.992831 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
947 23:05:28.996651 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
948 23:05:29.000006 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
949 23:05:29.002828 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
950 23:05:29.006714 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
951 23:05:29.013403 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
952 23:05:29.016643 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
953 23:05:29.019784 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
954 23:05:29.023268 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
955 23:05:29.026473 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
956 23:05:29.030059 ==
957 23:05:29.030165 Dram Type= 6, Freq= 0, CH_0, rank 0
958 23:05:29.036678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
959 23:05:29.036760 ==
960 23:05:29.036885 DQS Delay:
961 23:05:29.040053 DQS0 = 0, DQS1 = 0
962 23:05:29.040158 DQM Delay:
963 23:05:29.040252 DQM0 = 90, DQM1 = 84
964 23:05:29.043247 DQ Delay:
965 23:05:29.046705 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
966 23:05:29.050303 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =101
967 23:05:29.053531 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
968 23:05:29.056740 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
969 23:05:29.056843
970 23:05:29.056939
971 23:05:29.057028 ==
972 23:05:29.059938 Dram Type= 6, Freq= 0, CH_0, rank 0
973 23:05:29.063208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 23:05:29.063316 ==
975 23:05:29.063410
976 23:05:29.063498
977 23:05:29.066938 TX Vref Scan disable
978 23:05:29.067039 == TX Byte 0 ==
979 23:05:29.073726 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
980 23:05:29.077016 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
981 23:05:29.077122 == TX Byte 1 ==
982 23:05:29.083817 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
983 23:05:29.086708 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
984 23:05:29.086810 ==
985 23:05:29.090179 Dram Type= 6, Freq= 0, CH_0, rank 0
986 23:05:29.093316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 23:05:29.093420 ==
988 23:05:29.107400 TX Vref=22, minBit 4, minWin=27, winSum=446
989 23:05:29.111398 TX Vref=24, minBit 10, minWin=27, winSum=450
990 23:05:29.114438 TX Vref=26, minBit 8, minWin=27, winSum=453
991 23:05:29.117849 TX Vref=28, minBit 0, minWin=28, winSum=457
992 23:05:29.121144 TX Vref=30, minBit 5, minWin=28, winSum=457
993 23:05:29.124418 TX Vref=32, minBit 0, minWin=28, winSum=455
994 23:05:29.130815 [TxChooseVref] Worse bit 0, Min win 28, Win sum 457, Final Vref 28
995 23:05:29.130925
996 23:05:29.134346 Final TX Range 1 Vref 28
997 23:05:29.134449
998 23:05:29.134543 ==
999 23:05:29.137380 Dram Type= 6, Freq= 0, CH_0, rank 0
1000 23:05:29.140950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1001 23:05:29.141054 ==
1002 23:05:29.141151
1003 23:05:29.144122
1004 23:05:29.144226 TX Vref Scan disable
1005 23:05:29.147891 == TX Byte 0 ==
1006 23:05:29.151084 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1007 23:05:29.154047 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1008 23:05:29.157466 == TX Byte 1 ==
1009 23:05:29.161076 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1010 23:05:29.164587 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1011 23:05:29.164694
1012 23:05:29.167789 [DATLAT]
1013 23:05:29.167887 Freq=800, CH0 RK0
1014 23:05:29.167982
1015 23:05:29.171095 DATLAT Default: 0xa
1016 23:05:29.171192 0, 0xFFFF, sum = 0
1017 23:05:29.174493 1, 0xFFFF, sum = 0
1018 23:05:29.174605 2, 0xFFFF, sum = 0
1019 23:05:29.177805 3, 0xFFFF, sum = 0
1020 23:05:29.177904 4, 0xFFFF, sum = 0
1021 23:05:29.180941 5, 0xFFFF, sum = 0
1022 23:05:29.181038 6, 0xFFFF, sum = 0
1023 23:05:29.184754 7, 0xFFFF, sum = 0
1024 23:05:29.184867 8, 0xFFFF, sum = 0
1025 23:05:29.187675 9, 0x0, sum = 1
1026 23:05:29.187782 10, 0x0, sum = 2
1027 23:05:29.191251 11, 0x0, sum = 3
1028 23:05:29.191326 12, 0x0, sum = 4
1029 23:05:29.194310 best_step = 10
1030 23:05:29.194382
1031 23:05:29.194457 ==
1032 23:05:29.197818 Dram Type= 6, Freq= 0, CH_0, rank 0
1033 23:05:29.200976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1034 23:05:29.201085 ==
1035 23:05:29.204553 RX Vref Scan: 1
1036 23:05:29.204652
1037 23:05:29.204751 Set Vref Range= 32 -> 127
1038 23:05:29.204840
1039 23:05:29.207636 RX Vref 32 -> 127, step: 1
1040 23:05:29.207738
1041 23:05:29.211202 RX Delay -95 -> 252, step: 8
1042 23:05:29.211273
1043 23:05:29.214526 Set Vref, RX VrefLevel [Byte0]: 32
1044 23:05:29.217917 [Byte1]: 32
1045 23:05:29.218021
1046 23:05:29.221024 Set Vref, RX VrefLevel [Byte0]: 33
1047 23:05:29.224421 [Byte1]: 33
1048 23:05:29.227692
1049 23:05:29.227791 Set Vref, RX VrefLevel [Byte0]: 34
1050 23:05:29.231089 [Byte1]: 34
1051 23:05:29.235418
1052 23:05:29.235519 Set Vref, RX VrefLevel [Byte0]: 35
1053 23:05:29.238693 [Byte1]: 35
1054 23:05:29.243007
1055 23:05:29.243099 Set Vref, RX VrefLevel [Byte0]: 36
1056 23:05:29.246137 [Byte1]: 36
1057 23:05:29.251239
1058 23:05:29.251350 Set Vref, RX VrefLevel [Byte0]: 37
1059 23:05:29.254379 [Byte1]: 37
1060 23:05:29.258502
1061 23:05:29.258607 Set Vref, RX VrefLevel [Byte0]: 38
1062 23:05:29.262314 [Byte1]: 38
1063 23:05:29.266216
1064 23:05:29.266330 Set Vref, RX VrefLevel [Byte0]: 39
1065 23:05:29.269104 [Byte1]: 39
1066 23:05:29.274114
1067 23:05:29.274198 Set Vref, RX VrefLevel [Byte0]: 40
1068 23:05:29.277121 [Byte1]: 40
1069 23:05:29.281189
1070 23:05:29.281294 Set Vref, RX VrefLevel [Byte0]: 41
1071 23:05:29.284462 [Byte1]: 41
1072 23:05:29.289000
1073 23:05:29.289113 Set Vref, RX VrefLevel [Byte0]: 42
1074 23:05:29.292357 [Byte1]: 42
1075 23:05:29.296074
1076 23:05:29.296181 Set Vref, RX VrefLevel [Byte0]: 43
1077 23:05:29.299635 [Byte1]: 43
1078 23:05:29.304101
1079 23:05:29.304179 Set Vref, RX VrefLevel [Byte0]: 44
1080 23:05:29.307148 [Byte1]: 44
1081 23:05:29.311186
1082 23:05:29.311261 Set Vref, RX VrefLevel [Byte0]: 45
1083 23:05:29.314819 [Byte1]: 45
1084 23:05:29.319078
1085 23:05:29.319151 Set Vref, RX VrefLevel [Byte0]: 46
1086 23:05:29.322194 [Byte1]: 46
1087 23:05:29.326904
1088 23:05:29.326985 Set Vref, RX VrefLevel [Byte0]: 47
1089 23:05:29.330193 [Byte1]: 47
1090 23:05:29.334106
1091 23:05:29.334189 Set Vref, RX VrefLevel [Byte0]: 48
1092 23:05:29.337442 [Byte1]: 48
1093 23:05:29.341885
1094 23:05:29.341968 Set Vref, RX VrefLevel [Byte0]: 49
1095 23:05:29.345025 [Byte1]: 49
1096 23:05:29.349331
1097 23:05:29.349450 Set Vref, RX VrefLevel [Byte0]: 50
1098 23:05:29.352399 [Byte1]: 50
1099 23:05:29.356924
1100 23:05:29.357024 Set Vref, RX VrefLevel [Byte0]: 51
1101 23:05:29.360564 [Byte1]: 51
1102 23:05:29.364554
1103 23:05:29.364670 Set Vref, RX VrefLevel [Byte0]: 52
1104 23:05:29.367746 [Byte1]: 52
1105 23:05:29.372247
1106 23:05:29.372331 Set Vref, RX VrefLevel [Byte0]: 53
1107 23:05:29.375567 [Byte1]: 53
1108 23:05:29.379636
1109 23:05:29.379722 Set Vref, RX VrefLevel [Byte0]: 54
1110 23:05:29.383138 [Byte1]: 54
1111 23:05:29.387147
1112 23:05:29.387229 Set Vref, RX VrefLevel [Byte0]: 55
1113 23:05:29.390696 [Byte1]: 55
1114 23:05:29.395257
1115 23:05:29.395338 Set Vref, RX VrefLevel [Byte0]: 56
1116 23:05:29.398499 [Byte1]: 56
1117 23:05:29.402871
1118 23:05:29.402951 Set Vref, RX VrefLevel [Byte0]: 57
1119 23:05:29.406595 [Byte1]: 57
1120 23:05:29.410202
1121 23:05:29.410282 Set Vref, RX VrefLevel [Byte0]: 58
1122 23:05:29.413745 [Byte1]: 58
1123 23:05:29.417941
1124 23:05:29.418022 Set Vref, RX VrefLevel [Byte0]: 59
1125 23:05:29.421415 [Byte1]: 59
1126 23:05:29.425166
1127 23:05:29.425248 Set Vref, RX VrefLevel [Byte0]: 60
1128 23:05:29.428890 [Byte1]: 60
1129 23:05:29.433525
1130 23:05:29.433645 Set Vref, RX VrefLevel [Byte0]: 61
1131 23:05:29.436041 [Byte1]: 61
1132 23:05:29.440647
1133 23:05:29.440727 Set Vref, RX VrefLevel [Byte0]: 62
1134 23:05:29.443698 [Byte1]: 62
1135 23:05:29.447987
1136 23:05:29.448068 Set Vref, RX VrefLevel [Byte0]: 63
1137 23:05:29.451854 [Byte1]: 63
1138 23:05:29.455723
1139 23:05:29.455804 Set Vref, RX VrefLevel [Byte0]: 64
1140 23:05:29.458846 [Byte1]: 64
1141 23:05:29.463228
1142 23:05:29.463334 Set Vref, RX VrefLevel [Byte0]: 65
1143 23:05:29.466878 [Byte1]: 65
1144 23:05:29.470779
1145 23:05:29.470859 Set Vref, RX VrefLevel [Byte0]: 66
1146 23:05:29.474436 [Byte1]: 66
1147 23:05:29.478897
1148 23:05:29.478978 Set Vref, RX VrefLevel [Byte0]: 67
1149 23:05:29.482203 [Byte1]: 67
1150 23:05:29.486053
1151 23:05:29.486133 Set Vref, RX VrefLevel [Byte0]: 68
1152 23:05:29.489447 [Byte1]: 68
1153 23:05:29.493979
1154 23:05:29.494059 Set Vref, RX VrefLevel [Byte0]: 69
1155 23:05:29.496910 [Byte1]: 69
1156 23:05:29.501325
1157 23:05:29.501407 Set Vref, RX VrefLevel [Byte0]: 70
1158 23:05:29.505338 [Byte1]: 70
1159 23:05:29.509248
1160 23:05:29.509329 Set Vref, RX VrefLevel [Byte0]: 71
1161 23:05:29.512486 [Byte1]: 71
1162 23:05:29.516396
1163 23:05:29.516477 Set Vref, RX VrefLevel [Byte0]: 72
1164 23:05:29.520201 [Byte1]: 72
1165 23:05:29.524349
1166 23:05:29.524443 Set Vref, RX VrefLevel [Byte0]: 73
1167 23:05:29.527578 [Byte1]: 73
1168 23:05:29.531848
1169 23:05:29.531929 Set Vref, RX VrefLevel [Byte0]: 74
1170 23:05:29.538320 [Byte1]: 74
1171 23:05:29.538402
1172 23:05:29.541520 Set Vref, RX VrefLevel [Byte0]: 75
1173 23:05:29.544904 [Byte1]: 75
1174 23:05:29.544984
1175 23:05:29.548070 Final RX Vref Byte 0 = 59 to rank0
1176 23:05:29.551263 Final RX Vref Byte 1 = 57 to rank0
1177 23:05:29.554513 Final RX Vref Byte 0 = 59 to rank1
1178 23:05:29.557881 Final RX Vref Byte 1 = 57 to rank1==
1179 23:05:29.561309 Dram Type= 6, Freq= 0, CH_0, rank 0
1180 23:05:29.565002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1181 23:05:29.565084 ==
1182 23:05:29.567984 DQS Delay:
1183 23:05:29.568065 DQS0 = 0, DQS1 = 0
1184 23:05:29.568130 DQM Delay:
1185 23:05:29.571642 DQM0 = 92, DQM1 = 85
1186 23:05:29.571724 DQ Delay:
1187 23:05:29.574659 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1188 23:05:29.577886 DQ4 =96, DQ5 =80, DQ6 =100, DQ7 =100
1189 23:05:29.580915 DQ8 =72, DQ9 =76, DQ10 =88, DQ11 =76
1190 23:05:29.584227 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92
1191 23:05:29.584308
1192 23:05:29.584370
1193 23:05:29.594855 [DQSOSCAuto] RK0, (LSB)MR18= 0x4b41, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
1194 23:05:29.598050 CH0 RK0: MR19=606, MR18=4B41
1195 23:05:29.604523 CH0_RK0: MR19=0x606, MR18=0x4B41, DQSOSC=391, MR23=63, INC=96, DEC=64
1196 23:05:29.604604
1197 23:05:29.607594 ----->DramcWriteLeveling(PI) begin...
1198 23:05:29.607702 ==
1199 23:05:29.610913 Dram Type= 6, Freq= 0, CH_0, rank 1
1200 23:05:29.614205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1201 23:05:29.614300 ==
1202 23:05:29.617328 Write leveling (Byte 0): 33 => 33
1203 23:05:29.621069 Write leveling (Byte 1): 31 => 31
1204 23:05:29.624210 DramcWriteLeveling(PI) end<-----
1205 23:05:29.624306
1206 23:05:29.624370 ==
1207 23:05:29.627781 Dram Type= 6, Freq= 0, CH_0, rank 1
1208 23:05:29.630565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1209 23:05:29.630674 ==
1210 23:05:29.634433 [Gating] SW mode calibration
1211 23:05:29.640885 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1212 23:05:29.647954 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1213 23:05:29.650906 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1214 23:05:29.654519 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1215 23:05:29.698209 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1216 23:05:29.698550 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 23:05:29.698667 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 23:05:29.698755 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 23:05:29.698862 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 23:05:29.698960 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 23:05:29.699104 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 23:05:29.699243 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 23:05:29.699361 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 23:05:29.699447 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 23:05:29.742693 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 23:05:29.743090 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 23:05:29.743205 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 23:05:29.743301 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 23:05:29.743441 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 23:05:29.743777 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 23:05:29.744448 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1232 23:05:29.744728 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 23:05:29.744795 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 23:05:29.744884 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 23:05:29.768268 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 23:05:29.768576 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 23:05:29.768649 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 23:05:29.768712 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 23:05:29.769480 0 9 8 | B1->B0 | 3030 2a2a | 0 1 | (0 0) (1 1)
1240 23:05:29.772093 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1241 23:05:29.775575 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1242 23:05:29.778659 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1243 23:05:29.781917 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1244 23:05:29.785483 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1245 23:05:29.792346 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1246 23:05:29.795502 0 10 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1247 23:05:29.798592 0 10 8 | B1->B0 | 2929 2828 | 0 0 | (0 0) (0 0)
1248 23:05:29.805199 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 23:05:29.808665 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 23:05:29.811984 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1251 23:05:29.819001 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 23:05:29.822277 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 23:05:29.825490 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 23:05:29.829357 0 11 4 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
1255 23:05:29.836910 0 11 8 | B1->B0 | 3a3a 3b3b | 0 0 | (1 1) (0 0)
1256 23:05:29.840279 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1257 23:05:29.844349 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1258 23:05:29.847610 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1259 23:05:29.854093 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1260 23:05:29.857614 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1261 23:05:29.861100 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1262 23:05:29.864050 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1263 23:05:29.870855 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1264 23:05:29.873945 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1265 23:05:29.877210 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 23:05:29.884270 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 23:05:29.887224 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 23:05:29.890932 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 23:05:29.897517 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 23:05:29.901168 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 23:05:29.904579 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 23:05:29.910942 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 23:05:29.914032 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 23:05:29.917785 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 23:05:29.924262 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 23:05:29.927530 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 23:05:29.930784 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 23:05:29.934591 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 23:05:29.941050 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1280 23:05:29.944529 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1281 23:05:29.947547 Total UI for P1: 0, mck2ui 16
1282 23:05:29.950964 best dqsien dly found for B1: ( 0, 14, 8)
1283 23:05:29.954589 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1284 23:05:29.957717 Total UI for P1: 0, mck2ui 16
1285 23:05:29.961282 best dqsien dly found for B0: ( 0, 14, 10)
1286 23:05:29.964823 best DQS0 dly(MCK, UI, PI) = (0, 14, 10)
1287 23:05:29.967852 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1288 23:05:29.967928
1289 23:05:29.974563 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 10)
1290 23:05:29.977754 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1291 23:05:29.981411 [Gating] SW calibration Done
1292 23:05:29.981512 ==
1293 23:05:29.984484 Dram Type= 6, Freq= 0, CH_0, rank 1
1294 23:05:29.987775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1295 23:05:29.987877 ==
1296 23:05:29.987969 RX Vref Scan: 0
1297 23:05:29.988055
1298 23:05:29.991832 RX Vref 0 -> 0, step: 1
1299 23:05:29.991926
1300 23:05:29.994840 RX Delay -130 -> 252, step: 16
1301 23:05:29.998012 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1302 23:05:30.001265 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1303 23:05:30.007720 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1304 23:05:30.011599 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1305 23:05:30.014843 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1306 23:05:30.018053 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1307 23:05:30.021542 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1308 23:05:30.024526 iDelay=222, Bit 7, Center 109 (-2 ~ 221) 224
1309 23:05:30.031351 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1310 23:05:30.035014 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1311 23:05:30.038112 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1312 23:05:30.041186 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1313 23:05:30.044896 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1314 23:05:30.051444 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1315 23:05:30.054554 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1316 23:05:30.057706 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1317 23:05:30.057788 ==
1318 23:05:30.061501 Dram Type= 6, Freq= 0, CH_0, rank 1
1319 23:05:30.064787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1320 23:05:30.064867 ==
1321 23:05:30.068246 DQS Delay:
1322 23:05:30.068346 DQS0 = 0, DQS1 = 0
1323 23:05:30.071795 DQM Delay:
1324 23:05:30.071895 DQM0 = 94, DQM1 = 81
1325 23:05:30.071987 DQ Delay:
1326 23:05:30.074946 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =85
1327 23:05:30.078233 DQ4 =93, DQ5 =85, DQ6 =101, DQ7 =109
1328 23:05:30.081981 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =77
1329 23:05:30.084926 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =93
1330 23:05:30.085027
1331 23:05:30.085120
1332 23:05:30.087926 ==
1333 23:05:30.091601 Dram Type= 6, Freq= 0, CH_0, rank 1
1334 23:05:30.094778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1335 23:05:30.094875 ==
1336 23:05:30.094971
1337 23:05:30.095042
1338 23:05:30.098404 TX Vref Scan disable
1339 23:05:30.098475 == TX Byte 0 ==
1340 23:05:30.104668 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1341 23:05:30.107881 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1342 23:05:30.107982 == TX Byte 1 ==
1343 23:05:30.114949 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1344 23:05:30.118246 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1345 23:05:30.118320 ==
1346 23:05:30.121518 Dram Type= 6, Freq= 0, CH_0, rank 1
1347 23:05:30.124725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1348 23:05:30.124805 ==
1349 23:05:30.138292 TX Vref=22, minBit 10, minWin=27, winSum=446
1350 23:05:30.141969 TX Vref=24, minBit 11, minWin=27, winSum=453
1351 23:05:30.145197 TX Vref=26, minBit 1, minWin=28, winSum=456
1352 23:05:30.148394 TX Vref=28, minBit 4, minWin=28, winSum=456
1353 23:05:30.151649 TX Vref=30, minBit 4, minWin=28, winSum=458
1354 23:05:30.158214 TX Vref=32, minBit 2, minWin=28, winSum=456
1355 23:05:30.161969 [TxChooseVref] Worse bit 4, Min win 28, Win sum 458, Final Vref 30
1356 23:05:30.162059
1357 23:05:30.165110 Final TX Range 1 Vref 30
1358 23:05:30.165211
1359 23:05:30.165299 ==
1360 23:05:30.168150 Dram Type= 6, Freq= 0, CH_0, rank 1
1361 23:05:30.171877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1362 23:05:30.171981 ==
1363 23:05:30.172071
1364 23:05:30.174914
1365 23:05:30.175009 TX Vref Scan disable
1366 23:05:30.178332 == TX Byte 0 ==
1367 23:05:30.181823 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1368 23:05:30.184821 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1369 23:05:30.188336 == TX Byte 1 ==
1370 23:05:30.192118 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1371 23:05:30.195022 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1372 23:05:30.198617
1373 23:05:30.198714 [DATLAT]
1374 23:05:30.198805 Freq=800, CH0 RK1
1375 23:05:30.198895
1376 23:05:30.201773 DATLAT Default: 0xa
1377 23:05:30.201849 0, 0xFFFF, sum = 0
1378 23:05:30.205246 1, 0xFFFF, sum = 0
1379 23:05:30.205342 2, 0xFFFF, sum = 0
1380 23:05:30.208659 3, 0xFFFF, sum = 0
1381 23:05:30.208739 4, 0xFFFF, sum = 0
1382 23:05:30.211925 5, 0xFFFF, sum = 0
1383 23:05:30.212024 6, 0xFFFF, sum = 0
1384 23:05:30.215217 7, 0xFFFF, sum = 0
1385 23:05:30.215316 8, 0xFFFF, sum = 0
1386 23:05:30.218265 9, 0x0, sum = 1
1387 23:05:30.218342 10, 0x0, sum = 2
1388 23:05:30.222184 11, 0x0, sum = 3
1389 23:05:30.222280 12, 0x0, sum = 4
1390 23:05:30.224959 best_step = 10
1391 23:05:30.225058
1392 23:05:30.225149 ==
1393 23:05:30.228686 Dram Type= 6, Freq= 0, CH_0, rank 1
1394 23:05:30.231817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1395 23:05:30.231923 ==
1396 23:05:30.234968 RX Vref Scan: 0
1397 23:05:30.235071
1398 23:05:30.235164 RX Vref 0 -> 0, step: 1
1399 23:05:30.235292
1400 23:05:30.238803 RX Delay -95 -> 252, step: 8
1401 23:05:30.245259 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1402 23:05:30.249070 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1403 23:05:30.251933 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1404 23:05:30.255203 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1405 23:05:30.258438 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1406 23:05:30.265019 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1407 23:05:30.268331 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1408 23:05:30.272018 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1409 23:05:30.274992 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1410 23:05:30.278899 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1411 23:05:30.285024 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1412 23:05:30.288447 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1413 23:05:30.291593 iDelay=209, Bit 12, Center 88 (-15 ~ 192) 208
1414 23:05:30.295284 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
1415 23:05:30.298725 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1416 23:05:30.305343 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1417 23:05:30.305447 ==
1418 23:05:30.308557 Dram Type= 6, Freq= 0, CH_0, rank 1
1419 23:05:30.311779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1420 23:05:30.311883 ==
1421 23:05:30.311976 DQS Delay:
1422 23:05:30.315239 DQS0 = 0, DQS1 = 0
1423 23:05:30.315335 DQM Delay:
1424 23:05:30.318692 DQM0 = 92, DQM1 = 83
1425 23:05:30.318792 DQ Delay:
1426 23:05:30.321804 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1427 23:05:30.325372 DQ4 =92, DQ5 =84, DQ6 =100, DQ7 =100
1428 23:05:30.328777 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =76
1429 23:05:30.331946 DQ12 =88, DQ13 =92, DQ14 =92, DQ15 =88
1430 23:05:30.332050
1431 23:05:30.332143
1432 23:05:30.338545 [DQSOSCAuto] RK1, (LSB)MR18= 0x4313, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
1433 23:05:30.341997 CH0 RK1: MR19=606, MR18=4313
1434 23:05:30.348298 CH0_RK1: MR19=0x606, MR18=0x4313, DQSOSC=393, MR23=63, INC=95, DEC=63
1435 23:05:30.352056 [RxdqsGatingPostProcess] freq 800
1436 23:05:30.358572 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1437 23:05:30.361858 Pre-setting of DQS Precalculation
1438 23:05:30.365749 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1439 23:05:30.365846 ==
1440 23:05:30.368877 Dram Type= 6, Freq= 0, CH_1, rank 0
1441 23:05:30.372066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1442 23:05:30.372174 ==
1443 23:05:30.379013 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1444 23:05:30.385209 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1445 23:05:30.393394 [CA 0] Center 36 (6~67) winsize 62
1446 23:05:30.396601 [CA 1] Center 36 (6~67) winsize 62
1447 23:05:30.400360 [CA 2] Center 34 (4~65) winsize 62
1448 23:05:30.403215 [CA 3] Center 34 (4~65) winsize 62
1449 23:05:30.406800 [CA 4] Center 34 (4~65) winsize 62
1450 23:05:30.410200 [CA 5] Center 34 (4~65) winsize 62
1451 23:05:30.410305
1452 23:05:30.413665 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1453 23:05:30.413766
1454 23:05:30.416829 [CATrainingPosCal] consider 1 rank data
1455 23:05:30.420314 u2DelayCellTimex100 = 270/100 ps
1456 23:05:30.423771 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1457 23:05:30.426842 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1458 23:05:30.430303 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1459 23:05:30.436811 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1460 23:05:30.440512 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1461 23:05:30.443883 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1462 23:05:30.443985
1463 23:05:30.447233 CA PerBit enable=1, Macro0, CA PI delay=34
1464 23:05:30.447335
1465 23:05:30.450700 [CBTSetCACLKResult] CA Dly = 34
1466 23:05:30.450810 CS Dly: 6 (0~37)
1467 23:05:30.450902 ==
1468 23:05:30.453527 Dram Type= 6, Freq= 0, CH_1, rank 1
1469 23:05:30.460689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1470 23:05:30.460792 ==
1471 23:05:30.463894 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1472 23:05:30.470395 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1473 23:05:30.479948 [CA 0] Center 36 (6~67) winsize 62
1474 23:05:30.483078 [CA 1] Center 37 (6~68) winsize 63
1475 23:05:30.486198 [CA 2] Center 35 (4~66) winsize 63
1476 23:05:30.489489 [CA 3] Center 35 (5~65) winsize 61
1477 23:05:30.493705 [CA 4] Center 35 (5~66) winsize 62
1478 23:05:30.497275 [CA 5] Center 34 (4~65) winsize 62
1479 23:05:30.497374
1480 23:05:30.500854 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1481 23:05:30.500964
1482 23:05:30.504729 [CATrainingPosCal] consider 2 rank data
1483 23:05:30.508533 u2DelayCellTimex100 = 270/100 ps
1484 23:05:30.512460 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1485 23:05:30.516646 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1486 23:05:30.516760 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1487 23:05:30.520149 CA3 delay=35 (5~65),Diff = 1 PI (7 cell)
1488 23:05:30.523732 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1489 23:05:30.527787 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1490 23:05:30.527901
1491 23:05:30.534259 CA PerBit enable=1, Macro0, CA PI delay=34
1492 23:05:30.534372
1493 23:05:30.537329 [CBTSetCACLKResult] CA Dly = 34
1494 23:05:30.537431 CS Dly: 6 (0~38)
1495 23:05:30.537531
1496 23:05:30.540765 ----->DramcWriteLeveling(PI) begin...
1497 23:05:30.540866 ==
1498 23:05:30.543912 Dram Type= 6, Freq= 0, CH_1, rank 0
1499 23:05:30.547882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1500 23:05:30.547982 ==
1501 23:05:30.551098 Write leveling (Byte 0): 28 => 28
1502 23:05:30.554070 Write leveling (Byte 1): 28 => 28
1503 23:05:30.557489 DramcWriteLeveling(PI) end<-----
1504 23:05:30.557618
1505 23:05:30.557685 ==
1506 23:05:30.561132 Dram Type= 6, Freq= 0, CH_1, rank 0
1507 23:05:30.564063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1508 23:05:30.567976 ==
1509 23:05:30.568077 [Gating] SW mode calibration
1510 23:05:30.577639 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1511 23:05:30.580784 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1512 23:05:30.583970 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1513 23:05:30.590956 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1514 23:05:30.594576 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 23:05:30.597835 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 23:05:30.604198 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 23:05:30.607988 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 23:05:30.611040 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 23:05:30.617555 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 23:05:30.621328 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 23:05:30.624430 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 23:05:30.627984 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 23:05:30.634450 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 23:05:30.637845 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 23:05:30.641304 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 23:05:30.647705 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 23:05:30.651592 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 23:05:30.654773 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1529 23:05:30.661246 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1530 23:05:30.664640 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 23:05:30.667859 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 23:05:30.674548 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 23:05:30.678551 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 23:05:30.681176 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 23:05:30.687899 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 23:05:30.691500 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 23:05:30.695044 0 9 4 | B1->B0 | 2323 2828 | 1 0 | (1 1) (0 0)
1538 23:05:30.698400 0 9 8 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
1539 23:05:30.704805 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1540 23:05:30.707819 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1541 23:05:30.711739 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1542 23:05:30.718147 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1543 23:05:30.721307 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1544 23:05:30.724448 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1545 23:05:30.731184 0 10 4 | B1->B0 | 3030 2a2a | 0 0 | (0 1) (0 0)
1546 23:05:30.734728 0 10 8 | B1->B0 | 2828 2323 | 1 0 | (0 0) (0 0)
1547 23:05:30.737893 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 23:05:30.744861 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 23:05:30.747863 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 23:05:30.751420 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 23:05:30.758534 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 23:05:30.761973 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 23:05:30.765152 0 11 4 | B1->B0 | 2d2d 3b3a | 0 1 | (0 0) (0 0)
1554 23:05:30.771691 0 11 8 | B1->B0 | 4343 4646 | 1 0 | (0 0) (0 0)
1555 23:05:30.775027 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1556 23:05:30.778362 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1557 23:05:30.781463 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1558 23:05:30.788526 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1559 23:05:30.791699 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1560 23:05:30.794638 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1561 23:05:30.801448 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1562 23:05:30.805462 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1563 23:05:30.808568 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 23:05:30.814964 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 23:05:30.818775 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 23:05:30.822031 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 23:05:30.828747 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 23:05:30.832039 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 23:05:30.835272 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 23:05:30.841937 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 23:05:30.845398 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 23:05:30.848775 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 23:05:30.852153 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 23:05:30.858793 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 23:05:30.862176 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 23:05:30.865037 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1577 23:05:30.872014 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1578 23:05:30.875113 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1579 23:05:30.878482 Total UI for P1: 0, mck2ui 16
1580 23:05:30.882053 best dqsien dly found for B0: ( 0, 14, 2)
1581 23:05:30.885010 Total UI for P1: 0, mck2ui 16
1582 23:05:30.888641 best dqsien dly found for B1: ( 0, 14, 4)
1583 23:05:30.891837 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1584 23:05:30.895647 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1585 23:05:30.895759
1586 23:05:30.898928 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1587 23:05:30.902006 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1588 23:05:30.905522 [Gating] SW calibration Done
1589 23:05:30.905640 ==
1590 23:05:30.909062 Dram Type= 6, Freq= 0, CH_1, rank 0
1591 23:05:30.912256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1592 23:05:30.912337 ==
1593 23:05:30.915523 RX Vref Scan: 0
1594 23:05:30.915604
1595 23:05:30.918789 RX Vref 0 -> 0, step: 1
1596 23:05:30.918870
1597 23:05:30.918934 RX Delay -130 -> 252, step: 16
1598 23:05:30.925294 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1599 23:05:30.928371 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1600 23:05:30.932259 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1601 23:05:30.935540 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1602 23:05:30.938810 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1603 23:05:30.945167 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1604 23:05:30.948914 iDelay=222, Bit 6, Center 109 (-2 ~ 221) 224
1605 23:05:30.952177 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1606 23:05:30.955280 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1607 23:05:30.958869 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1608 23:05:30.965229 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1609 23:05:30.968524 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1610 23:05:30.972289 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1611 23:05:30.975315 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1612 23:05:30.978408 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1613 23:05:30.985040 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1614 23:05:30.985138 ==
1615 23:05:30.988811 Dram Type= 6, Freq= 0, CH_1, rank 0
1616 23:05:30.991732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1617 23:05:30.991814 ==
1618 23:05:30.991877 DQS Delay:
1619 23:05:30.995347 DQS0 = 0, DQS1 = 0
1620 23:05:30.995427 DQM Delay:
1621 23:05:30.998637 DQM0 = 94, DQM1 = 88
1622 23:05:30.998718 DQ Delay:
1623 23:05:31.001802 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1624 23:05:31.005620 DQ4 =93, DQ5 =109, DQ6 =109, DQ7 =93
1625 23:05:31.008874 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1626 23:05:31.012109 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =101
1627 23:05:31.012190
1628 23:05:31.012253
1629 23:05:31.012312 ==
1630 23:05:31.015098 Dram Type= 6, Freq= 0, CH_1, rank 0
1631 23:05:31.018885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1632 23:05:31.021745 ==
1633 23:05:31.021828
1634 23:05:31.021892
1635 23:05:31.021950 TX Vref Scan disable
1636 23:05:31.025271 == TX Byte 0 ==
1637 23:05:31.028795 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1638 23:05:31.031985 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1639 23:05:31.035148 == TX Byte 1 ==
1640 23:05:31.038512 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1641 23:05:31.041749 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1642 23:05:31.044963 ==
1643 23:05:31.048834 Dram Type= 6, Freq= 0, CH_1, rank 0
1644 23:05:31.051985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1645 23:05:31.052093 ==
1646 23:05:31.064108 TX Vref=22, minBit 1, minWin=26, winSum=439
1647 23:05:31.067240 TX Vref=24, minBit 3, minWin=26, winSum=445
1648 23:05:31.070546 TX Vref=26, minBit 2, minWin=27, winSum=447
1649 23:05:31.074403 TX Vref=28, minBit 1, minWin=27, winSum=450
1650 23:05:31.078248 TX Vref=30, minBit 1, minWin=27, winSum=453
1651 23:05:31.081428 TX Vref=32, minBit 1, minWin=27, winSum=450
1652 23:05:31.088535 [TxChooseVref] Worse bit 1, Min win 27, Win sum 453, Final Vref 30
1653 23:05:31.088652
1654 23:05:31.091767 Final TX Range 1 Vref 30
1655 23:05:31.091878
1656 23:05:31.091973 ==
1657 23:05:31.094909 Dram Type= 6, Freq= 0, CH_1, rank 0
1658 23:05:31.097870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1659 23:05:31.097976 ==
1660 23:05:31.098074
1661 23:05:31.098164
1662 23:05:31.101519 TX Vref Scan disable
1663 23:05:31.104959 == TX Byte 0 ==
1664 23:05:31.108367 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1665 23:05:31.111044 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1666 23:05:31.114367 == TX Byte 1 ==
1667 23:05:31.118165 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1668 23:05:31.121491 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1669 23:05:31.121635
1670 23:05:31.124643 [DATLAT]
1671 23:05:31.124745 Freq=800, CH1 RK0
1672 23:05:31.124839
1673 23:05:31.127809 DATLAT Default: 0xa
1674 23:05:31.127914 0, 0xFFFF, sum = 0
1675 23:05:31.131580 1, 0xFFFF, sum = 0
1676 23:05:31.131687 2, 0xFFFF, sum = 0
1677 23:05:31.134638 3, 0xFFFF, sum = 0
1678 23:05:31.134754 4, 0xFFFF, sum = 0
1679 23:05:31.138284 5, 0xFFFF, sum = 0
1680 23:05:31.138386 6, 0xFFFF, sum = 0
1681 23:05:31.141328 7, 0xFFFF, sum = 0
1682 23:05:31.141431 8, 0xFFFF, sum = 0
1683 23:05:31.144830 9, 0x0, sum = 1
1684 23:05:31.144933 10, 0x0, sum = 2
1685 23:05:31.148281 11, 0x0, sum = 3
1686 23:05:31.148385 12, 0x0, sum = 4
1687 23:05:31.148481 best_step = 10
1688 23:05:31.148570
1689 23:05:31.151471 ==
1690 23:05:31.155037 Dram Type= 6, Freq= 0, CH_1, rank 0
1691 23:05:31.158241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1692 23:05:31.158346 ==
1693 23:05:31.158440 RX Vref Scan: 1
1694 23:05:31.158532
1695 23:05:31.161516 Set Vref Range= 32 -> 127
1696 23:05:31.161655
1697 23:05:31.165136 RX Vref 32 -> 127, step: 1
1698 23:05:31.165236
1699 23:05:31.168636 RX Delay -79 -> 252, step: 8
1700 23:05:31.168737
1701 23:05:31.172043 Set Vref, RX VrefLevel [Byte0]: 32
1702 23:05:31.174947 [Byte1]: 32
1703 23:05:31.175051
1704 23:05:31.178798 Set Vref, RX VrefLevel [Byte0]: 33
1705 23:05:31.182260 [Byte1]: 33
1706 23:05:31.182364
1707 23:05:31.185249 Set Vref, RX VrefLevel [Byte0]: 34
1708 23:05:31.188463 [Byte1]: 34
1709 23:05:31.188575
1710 23:05:31.191725 Set Vref, RX VrefLevel [Byte0]: 35
1711 23:05:31.194905 [Byte1]: 35
1712 23:05:31.198951
1713 23:05:31.199059 Set Vref, RX VrefLevel [Byte0]: 36
1714 23:05:31.202585 [Byte1]: 36
1715 23:05:31.206497
1716 23:05:31.206601 Set Vref, RX VrefLevel [Byte0]: 37
1717 23:05:31.209812 [Byte1]: 37
1718 23:05:31.214099
1719 23:05:31.214211 Set Vref, RX VrefLevel [Byte0]: 38
1720 23:05:31.217466 [Byte1]: 38
1721 23:05:31.222155
1722 23:05:31.222259 Set Vref, RX VrefLevel [Byte0]: 39
1723 23:05:31.225176 [Byte1]: 39
1724 23:05:31.229271
1725 23:05:31.229387 Set Vref, RX VrefLevel [Byte0]: 40
1726 23:05:31.232390 [Byte1]: 40
1727 23:05:31.237184
1728 23:05:31.237305 Set Vref, RX VrefLevel [Byte0]: 41
1729 23:05:31.240262 [Byte1]: 41
1730 23:05:31.244690
1731 23:05:31.244797 Set Vref, RX VrefLevel [Byte0]: 42
1732 23:05:31.247759 [Byte1]: 42
1733 23:05:31.251825
1734 23:05:31.251930 Set Vref, RX VrefLevel [Byte0]: 43
1735 23:05:31.255543 [Byte1]: 43
1736 23:05:31.259507
1737 23:05:31.259613 Set Vref, RX VrefLevel [Byte0]: 44
1738 23:05:31.263134 [Byte1]: 44
1739 23:05:31.267218
1740 23:05:31.267324 Set Vref, RX VrefLevel [Byte0]: 45
1741 23:05:31.270482 [Byte1]: 45
1742 23:05:31.274274
1743 23:05:31.274385 Set Vref, RX VrefLevel [Byte0]: 46
1744 23:05:31.277781 [Byte1]: 46
1745 23:05:31.282165
1746 23:05:31.282273 Set Vref, RX VrefLevel [Byte0]: 47
1747 23:05:31.285288 [Byte1]: 47
1748 23:05:31.289526
1749 23:05:31.289687 Set Vref, RX VrefLevel [Byte0]: 48
1750 23:05:31.293348 [Byte1]: 48
1751 23:05:31.297281
1752 23:05:31.297385 Set Vref, RX VrefLevel [Byte0]: 49
1753 23:05:31.300555 [Byte1]: 49
1754 23:05:31.305050
1755 23:05:31.305156 Set Vref, RX VrefLevel [Byte0]: 50
1756 23:05:31.308050 [Byte1]: 50
1757 23:05:31.312517
1758 23:05:31.312622 Set Vref, RX VrefLevel [Byte0]: 51
1759 23:05:31.315755 [Byte1]: 51
1760 23:05:31.319716
1761 23:05:31.319827 Set Vref, RX VrefLevel [Byte0]: 52
1762 23:05:31.323457 [Byte1]: 52
1763 23:05:31.327407
1764 23:05:31.327516 Set Vref, RX VrefLevel [Byte0]: 53
1765 23:05:31.330488 [Byte1]: 53
1766 23:05:31.335137
1767 23:05:31.335256 Set Vref, RX VrefLevel [Byte0]: 54
1768 23:05:31.338165 [Byte1]: 54
1769 23:05:31.342641
1770 23:05:31.342751 Set Vref, RX VrefLevel [Byte0]: 55
1771 23:05:31.345826 [Byte1]: 55
1772 23:05:31.350286
1773 23:05:31.350389 Set Vref, RX VrefLevel [Byte0]: 56
1774 23:05:31.353542 [Byte1]: 56
1775 23:05:31.357326
1776 23:05:31.357420 Set Vref, RX VrefLevel [Byte0]: 57
1777 23:05:31.360839 [Byte1]: 57
1778 23:05:31.365362
1779 23:05:31.365444 Set Vref, RX VrefLevel [Byte0]: 58
1780 23:05:31.368291 [Byte1]: 58
1781 23:05:31.372480
1782 23:05:31.372562 Set Vref, RX VrefLevel [Byte0]: 59
1783 23:05:31.376053 [Byte1]: 59
1784 23:05:31.380423
1785 23:05:31.380504 Set Vref, RX VrefLevel [Byte0]: 60
1786 23:05:31.383524 [Byte1]: 60
1787 23:05:31.387936
1788 23:05:31.388016 Set Vref, RX VrefLevel [Byte0]: 61
1789 23:05:31.391111 [Byte1]: 61
1790 23:05:31.395506
1791 23:05:31.395617 Set Vref, RX VrefLevel [Byte0]: 62
1792 23:05:31.398651 [Byte1]: 62
1793 23:05:31.403285
1794 23:05:31.403389 Set Vref, RX VrefLevel [Byte0]: 63
1795 23:05:31.406640 [Byte1]: 63
1796 23:05:31.410454
1797 23:05:31.410559 Set Vref, RX VrefLevel [Byte0]: 64
1798 23:05:31.413506 [Byte1]: 64
1799 23:05:31.418113
1800 23:05:31.418216 Set Vref, RX VrefLevel [Byte0]: 65
1801 23:05:31.421313 [Byte1]: 65
1802 23:05:31.425315
1803 23:05:31.425423 Set Vref, RX VrefLevel [Byte0]: 66
1804 23:05:31.429051 [Byte1]: 66
1805 23:05:31.433049
1806 23:05:31.433154 Set Vref, RX VrefLevel [Byte0]: 67
1807 23:05:31.436296 [Byte1]: 67
1808 23:05:31.440629
1809 23:05:31.440734 Set Vref, RX VrefLevel [Byte0]: 68
1810 23:05:31.443867 [Byte1]: 68
1811 23:05:31.448280
1812 23:05:31.448391 Set Vref, RX VrefLevel [Byte0]: 69
1813 23:05:31.451553 [Byte1]: 69
1814 23:05:31.456053
1815 23:05:31.456140 Set Vref, RX VrefLevel [Byte0]: 70
1816 23:05:31.459225 [Byte1]: 70
1817 23:05:31.463421
1818 23:05:31.463541 Set Vref, RX VrefLevel [Byte0]: 71
1819 23:05:31.466924 [Byte1]: 71
1820 23:05:31.471016
1821 23:05:31.471129 Final RX Vref Byte 0 = 54 to rank0
1822 23:05:31.474180 Final RX Vref Byte 1 = 56 to rank0
1823 23:05:31.477571 Final RX Vref Byte 0 = 54 to rank1
1824 23:05:31.480811 Final RX Vref Byte 1 = 56 to rank1==
1825 23:05:31.484245 Dram Type= 6, Freq= 0, CH_1, rank 0
1826 23:05:31.490789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1827 23:05:31.490902 ==
1828 23:05:31.491008 DQS Delay:
1829 23:05:31.491110 DQS0 = 0, DQS1 = 0
1830 23:05:31.494114 DQM Delay:
1831 23:05:31.494224 DQM0 = 94, DQM1 = 89
1832 23:05:31.497383 DQ Delay:
1833 23:05:31.500627 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =88
1834 23:05:31.503802 DQ4 =96, DQ5 =108, DQ6 =104, DQ7 =92
1835 23:05:31.507577 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84
1836 23:05:31.510737 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1837 23:05:31.510849
1838 23:05:31.510945
1839 23:05:31.517674 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e4a, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
1840 23:05:31.520615 CH1 RK0: MR19=606, MR18=2E4A
1841 23:05:31.527780 CH1_RK0: MR19=0x606, MR18=0x2E4A, DQSOSC=391, MR23=63, INC=96, DEC=64
1842 23:05:31.527894
1843 23:05:31.530979 ----->DramcWriteLeveling(PI) begin...
1844 23:05:31.531089 ==
1845 23:05:31.534594 Dram Type= 6, Freq= 0, CH_1, rank 1
1846 23:05:31.537757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1847 23:05:31.537873 ==
1848 23:05:31.540858 Write leveling (Byte 0): 25 => 25
1849 23:05:31.544188 Write leveling (Byte 1): 25 => 25
1850 23:05:31.547945 DramcWriteLeveling(PI) end<-----
1851 23:05:31.548048
1852 23:05:31.548144 ==
1853 23:05:31.550952 Dram Type= 6, Freq= 0, CH_1, rank 1
1854 23:05:31.554252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1855 23:05:31.554361 ==
1856 23:05:31.557376 [Gating] SW mode calibration
1857 23:05:31.564258 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1858 23:05:31.570858 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1859 23:05:31.574027 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1860 23:05:31.577281 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1861 23:05:31.584292 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 23:05:31.587909 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 23:05:31.590807 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 23:05:31.597747 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 23:05:31.600869 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 23:05:31.604243 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 23:05:31.610839 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 23:05:31.613933 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 23:05:31.617368 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 23:05:31.624230 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 23:05:31.627580 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 23:05:31.630642 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 23:05:31.637290 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 23:05:31.640865 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1875 23:05:31.644057 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1876 23:05:31.647414 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1877 23:05:31.654252 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 23:05:31.657460 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 23:05:31.660720 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 23:05:31.667442 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 23:05:31.671185 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 23:05:31.674471 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 23:05:31.680896 0 9 0 | B1->B0 | 2323 2323 | 1 0 | (1 1) (0 0)
1884 23:05:31.684015 0 9 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1885 23:05:31.687886 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1886 23:05:31.694538 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1887 23:05:31.697562 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1888 23:05:31.700806 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1889 23:05:31.707605 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1890 23:05:31.711019 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1891 23:05:31.714057 0 10 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1892 23:05:31.721378 0 10 4 | B1->B0 | 2727 3030 | 0 0 | (1 0) (1 0)
1893 23:05:31.724353 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1894 23:05:31.727538 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 23:05:31.730689 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 23:05:31.737642 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 23:05:31.741492 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 23:05:31.744493 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 23:05:31.751357 0 11 0 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
1900 23:05:31.754209 0 11 4 | B1->B0 | 3838 2d2d | 0 0 | (1 1) (0 0)
1901 23:05:31.758159 0 11 8 | B1->B0 | 4646 4343 | 0 1 | (0 0) (0 0)
1902 23:05:31.764130 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1903 23:05:31.767620 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1904 23:05:31.771515 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1905 23:05:31.777712 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1906 23:05:31.781122 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1907 23:05:31.784325 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1908 23:05:31.788186 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1909 23:05:31.794524 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1910 23:05:31.798397 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1911 23:05:31.801324 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1912 23:05:31.808111 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1913 23:05:31.811320 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1914 23:05:31.814819 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1915 23:05:31.821378 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1916 23:05:31.824664 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1917 23:05:31.827820 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1918 23:05:31.834390 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 23:05:31.838051 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 23:05:31.841812 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 23:05:31.848237 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 23:05:31.851534 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 23:05:31.854667 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 23:05:31.861444 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1925 23:05:31.861549 Total UI for P1: 0, mck2ui 16
1926 23:05:31.864831 best dqsien dly found for B0: ( 0, 14, 2)
1927 23:05:31.868418 Total UI for P1: 0, mck2ui 16
1928 23:05:31.871432 best dqsien dly found for B1: ( 0, 14, 2)
1929 23:05:31.874783 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1930 23:05:31.878074 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1931 23:05:31.881610
1932 23:05:31.885211 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1933 23:05:31.888159 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1934 23:05:31.888266 [Gating] SW calibration Done
1935 23:05:31.891899 ==
1936 23:05:31.895120 Dram Type= 6, Freq= 0, CH_1, rank 1
1937 23:05:31.898576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1938 23:05:31.898682 ==
1939 23:05:31.898780 RX Vref Scan: 0
1940 23:05:31.898873
1941 23:05:31.901615 RX Vref 0 -> 0, step: 1
1942 23:05:31.901724
1943 23:05:31.905227 RX Delay -130 -> 252, step: 16
1944 23:05:31.908684 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1945 23:05:31.911643 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1946 23:05:31.915135 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1947 23:05:31.922115 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1948 23:05:31.925191 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1949 23:05:31.928284 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1950 23:05:31.931679 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1951 23:05:31.935003 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1952 23:05:31.941612 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1953 23:05:31.944932 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1954 23:05:31.948563 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1955 23:05:31.951830 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1956 23:05:31.954996 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1957 23:05:31.961878 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1958 23:05:31.965063 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1959 23:05:31.968899 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1960 23:05:31.968981 ==
1961 23:05:31.972101 Dram Type= 6, Freq= 0, CH_1, rank 1
1962 23:05:31.975158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1963 23:05:31.978401 ==
1964 23:05:31.978511 DQS Delay:
1965 23:05:31.978606 DQS0 = 0, DQS1 = 0
1966 23:05:31.981865 DQM Delay:
1967 23:05:31.981964 DQM0 = 92, DQM1 = 88
1968 23:05:31.982030 DQ Delay:
1969 23:05:31.985052 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =85
1970 23:05:31.988564 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1971 23:05:31.991625 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =77
1972 23:05:31.995521 DQ12 =93, DQ13 =101, DQ14 =93, DQ15 =93
1973 23:05:31.995617
1974 23:05:31.998729
1975 23:05:31.998834 ==
1976 23:05:32.001730 Dram Type= 6, Freq= 0, CH_1, rank 1
1977 23:05:32.005153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1978 23:05:32.005250 ==
1979 23:05:32.005349
1980 23:05:32.005473
1981 23:05:32.008669 TX Vref Scan disable
1982 23:05:32.008739 == TX Byte 0 ==
1983 23:05:32.015452 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1984 23:05:32.018766 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1985 23:05:32.018882 == TX Byte 1 ==
1986 23:05:32.025051 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1987 23:05:32.028372 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1988 23:05:32.028482 ==
1989 23:05:32.032344 Dram Type= 6, Freq= 0, CH_1, rank 1
1990 23:05:32.034918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1991 23:05:32.035021 ==
1992 23:05:32.048698 TX Vref=22, minBit 1, minWin=26, winSum=434
1993 23:05:32.051791 TX Vref=24, minBit 1, minWin=26, winSum=436
1994 23:05:32.055476 TX Vref=26, minBit 2, minWin=27, winSum=442
1995 23:05:32.058668 TX Vref=28, minBit 0, minWin=27, winSum=445
1996 23:05:32.062026 TX Vref=30, minBit 0, minWin=27, winSum=443
1997 23:05:32.065711 TX Vref=32, minBit 0, minWin=27, winSum=444
1998 23:05:32.071993 [TxChooseVref] Worse bit 0, Min win 27, Win sum 445, Final Vref 28
1999 23:05:32.072101
2000 23:05:32.075350 Final TX Range 1 Vref 28
2001 23:05:32.075431
2002 23:05:32.075496 ==
2003 23:05:32.078592 Dram Type= 6, Freq= 0, CH_1, rank 1
2004 23:05:32.082241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2005 23:05:32.082326 ==
2006 23:05:32.082390
2007 23:05:32.082448
2008 23:05:32.085304 TX Vref Scan disable
2009 23:05:32.088749 == TX Byte 0 ==
2010 23:05:32.092149 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2011 23:05:32.095227 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2012 23:05:32.098923 == TX Byte 1 ==
2013 23:05:32.102147 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
2014 23:05:32.105219 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
2015 23:05:32.105330
2016 23:05:32.109271 [DATLAT]
2017 23:05:32.109351 Freq=800, CH1 RK1
2018 23:05:32.109415
2019 23:05:32.112419 DATLAT Default: 0xa
2020 23:05:32.112499 0, 0xFFFF, sum = 0
2021 23:05:32.115648 1, 0xFFFF, sum = 0
2022 23:05:32.115730 2, 0xFFFF, sum = 0
2023 23:05:32.119004 3, 0xFFFF, sum = 0
2024 23:05:32.119086 4, 0xFFFF, sum = 0
2025 23:05:32.122604 5, 0xFFFF, sum = 0
2026 23:05:32.122686 6, 0xFFFF, sum = 0
2027 23:05:32.125668 7, 0xFFFF, sum = 0
2028 23:05:32.125750 8, 0xFFFF, sum = 0
2029 23:05:32.129072 9, 0x0, sum = 1
2030 23:05:32.129154 10, 0x0, sum = 2
2031 23:05:32.132487 11, 0x0, sum = 3
2032 23:05:32.132596 12, 0x0, sum = 4
2033 23:05:32.135696 best_step = 10
2034 23:05:32.135808
2035 23:05:32.135901 ==
2036 23:05:32.138968 Dram Type= 6, Freq= 0, CH_1, rank 1
2037 23:05:32.142981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2038 23:05:32.143063 ==
2039 23:05:32.143127 RX Vref Scan: 0
2040 23:05:32.145833
2041 23:05:32.145913 RX Vref 0 -> 0, step: 1
2042 23:05:32.145977
2043 23:05:32.149243 RX Delay -79 -> 252, step: 8
2044 23:05:32.152660 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
2045 23:05:32.159535 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
2046 23:05:32.162223 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
2047 23:05:32.165976 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
2048 23:05:32.169111 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
2049 23:05:32.172669 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
2050 23:05:32.175873 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2051 23:05:32.182663 iDelay=209, Bit 7, Center 92 (-7 ~ 192) 200
2052 23:05:32.185911 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2053 23:05:32.188915 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2054 23:05:32.192737 iDelay=209, Bit 10, Center 92 (-7 ~ 192) 200
2055 23:05:32.195737 iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208
2056 23:05:32.202770 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2057 23:05:32.205830 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2058 23:05:32.209094 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2059 23:05:32.212297 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2060 23:05:32.212378 ==
2061 23:05:32.216153 Dram Type= 6, Freq= 0, CH_1, rank 1
2062 23:05:32.222627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2063 23:05:32.222709 ==
2064 23:05:32.222773 DQS Delay:
2065 23:05:32.222833 DQS0 = 0, DQS1 = 0
2066 23:05:32.225879 DQM Delay:
2067 23:05:32.225974 DQM0 = 97, DQM1 = 91
2068 23:05:32.229028 DQ Delay:
2069 23:05:32.233162 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2070 23:05:32.236169 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =92
2071 23:05:32.236277 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =88
2072 23:05:32.242781 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2073 23:05:32.242868
2074 23:05:32.242963
2075 23:05:32.249239 [DQSOSCAuto] RK1, (LSB)MR18= 0x460f, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
2076 23:05:32.252297 CH1 RK1: MR19=606, MR18=460F
2077 23:05:32.259334 CH1_RK1: MR19=0x606, MR18=0x460F, DQSOSC=392, MR23=63, INC=96, DEC=64
2078 23:05:32.262473 [RxdqsGatingPostProcess] freq 800
2079 23:05:32.265990 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2080 23:05:32.269383 Pre-setting of DQS Precalculation
2081 23:05:32.275910 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2082 23:05:32.282521 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2083 23:05:32.289326 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2084 23:05:32.289442
2085 23:05:32.289542
2086 23:05:32.293029 [Calibration Summary] 1600 Mbps
2087 23:05:32.293106 CH 0, Rank 0
2088 23:05:32.296460 SW Impedance : PASS
2089 23:05:32.299875 DUTY Scan : NO K
2090 23:05:32.299951 ZQ Calibration : PASS
2091 23:05:32.302817 Jitter Meter : NO K
2092 23:05:32.302891 CBT Training : PASS
2093 23:05:32.306212 Write leveling : PASS
2094 23:05:32.309517 RX DQS gating : PASS
2095 23:05:32.309646 RX DQ/DQS(RDDQC) : PASS
2096 23:05:32.312685 TX DQ/DQS : PASS
2097 23:05:32.315992 RX DATLAT : PASS
2098 23:05:32.316092 RX DQ/DQS(Engine): PASS
2099 23:05:32.319739 TX OE : NO K
2100 23:05:32.319812 All Pass.
2101 23:05:32.319872
2102 23:05:32.322977 CH 0, Rank 1
2103 23:05:32.323066 SW Impedance : PASS
2104 23:05:32.326036 DUTY Scan : NO K
2105 23:05:32.329389 ZQ Calibration : PASS
2106 23:05:32.329495 Jitter Meter : NO K
2107 23:05:32.332732 CBT Training : PASS
2108 23:05:32.336595 Write leveling : PASS
2109 23:05:32.336676 RX DQS gating : PASS
2110 23:05:32.339715 RX DQ/DQS(RDDQC) : PASS
2111 23:05:32.339796 TX DQ/DQS : PASS
2112 23:05:32.342844 RX DATLAT : PASS
2113 23:05:32.346205 RX DQ/DQS(Engine): PASS
2114 23:05:32.346285 TX OE : NO K
2115 23:05:32.349934 All Pass.
2116 23:05:32.350050
2117 23:05:32.350155 CH 1, Rank 0
2118 23:05:32.353072 SW Impedance : PASS
2119 23:05:32.353183 DUTY Scan : NO K
2120 23:05:32.356125 ZQ Calibration : PASS
2121 23:05:32.359493 Jitter Meter : NO K
2122 23:05:32.359581 CBT Training : PASS
2123 23:05:32.362805 Write leveling : PASS
2124 23:05:32.366578 RX DQS gating : PASS
2125 23:05:32.366661 RX DQ/DQS(RDDQC) : PASS
2126 23:05:32.369812 TX DQ/DQS : PASS
2127 23:05:32.372961 RX DATLAT : PASS
2128 23:05:32.373041 RX DQ/DQS(Engine): PASS
2129 23:05:32.376172 TX OE : NO K
2130 23:05:32.376253 All Pass.
2131 23:05:32.376316
2132 23:05:32.379966 CH 1, Rank 1
2133 23:05:32.380046 SW Impedance : PASS
2134 23:05:32.383201 DUTY Scan : NO K
2135 23:05:32.383283 ZQ Calibration : PASS
2136 23:05:32.386672 Jitter Meter : NO K
2137 23:05:32.389848 CBT Training : PASS
2138 23:05:32.389959 Write leveling : PASS
2139 23:05:32.392730 RX DQS gating : PASS
2140 23:05:32.396473 RX DQ/DQS(RDDQC) : PASS
2141 23:05:32.396585 TX DQ/DQS : PASS
2142 23:05:32.399727 RX DATLAT : PASS
2143 23:05:32.403067 RX DQ/DQS(Engine): PASS
2144 23:05:32.403148 TX OE : NO K
2145 23:05:32.406370 All Pass.
2146 23:05:32.406469
2147 23:05:32.406536 DramC Write-DBI off
2148 23:05:32.409569 PER_BANK_REFRESH: Hybrid Mode
2149 23:05:32.409705 TX_TRACKING: ON
2150 23:05:32.413194 [GetDramInforAfterCalByMRR] Vendor 6.
2151 23:05:32.419840 [GetDramInforAfterCalByMRR] Revision 606.
2152 23:05:32.422736 [GetDramInforAfterCalByMRR] Revision 2 0.
2153 23:05:32.422849 MR0 0x3b3b
2154 23:05:32.422945 MR8 0x5151
2155 23:05:32.426032 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2156 23:05:32.426141
2157 23:05:32.429917 MR0 0x3b3b
2158 23:05:32.430030 MR8 0x5151
2159 23:05:32.433159 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2160 23:05:32.433272
2161 23:05:32.443151 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2162 23:05:32.446494 [FAST_K] Save calibration result to emmc
2163 23:05:32.449853 [FAST_K] Save calibration result to emmc
2164 23:05:32.452861 dram_init: config_dvfs: 1
2165 23:05:32.456076 dramc_set_vcore_voltage set vcore to 662500
2166 23:05:32.459660 Read voltage for 1200, 2
2167 23:05:32.459764 Vio18 = 0
2168 23:05:32.459860 Vcore = 662500
2169 23:05:32.462761 Vdram = 0
2170 23:05:32.462873 Vddq = 0
2171 23:05:32.462969 Vmddr = 0
2172 23:05:32.469221 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2173 23:05:32.472999 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2174 23:05:32.476411 MEM_TYPE=3, freq_sel=15
2175 23:05:32.479542 sv_algorithm_assistance_LP4_1600
2176 23:05:32.482770 ============ PULL DRAM RESETB DOWN ============
2177 23:05:32.486486 ========== PULL DRAM RESETB DOWN end =========
2178 23:05:32.492768 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2179 23:05:32.496266 ===================================
2180 23:05:32.496368 LPDDR4 DRAM CONFIGURATION
2181 23:05:32.499490 ===================================
2182 23:05:32.503112 EX_ROW_EN[0] = 0x0
2183 23:05:32.506170 EX_ROW_EN[1] = 0x0
2184 23:05:32.506251 LP4Y_EN = 0x0
2185 23:05:32.509451 WORK_FSP = 0x0
2186 23:05:32.509531 WL = 0x4
2187 23:05:32.512763 RL = 0x4
2188 23:05:32.512860 BL = 0x2
2189 23:05:32.516001 RPST = 0x0
2190 23:05:32.516081 RD_PRE = 0x0
2191 23:05:32.519928 WR_PRE = 0x1
2192 23:05:32.520009 WR_PST = 0x0
2193 23:05:32.523135 DBI_WR = 0x0
2194 23:05:32.523215 DBI_RD = 0x0
2195 23:05:32.526247 OTF = 0x1
2196 23:05:32.529463 ===================================
2197 23:05:32.532954 ===================================
2198 23:05:32.533035 ANA top config
2199 23:05:32.536410 ===================================
2200 23:05:32.539573 DLL_ASYNC_EN = 0
2201 23:05:32.543017 ALL_SLAVE_EN = 0
2202 23:05:32.543098 NEW_RANK_MODE = 1
2203 23:05:32.546559 DLL_IDLE_MODE = 1
2204 23:05:32.549541 LP45_APHY_COMB_EN = 1
2205 23:05:32.552832 TX_ODT_DIS = 1
2206 23:05:32.552940 NEW_8X_MODE = 1
2207 23:05:32.556447 ===================================
2208 23:05:32.559853 ===================================
2209 23:05:32.563183 data_rate = 2400
2210 23:05:32.566514 CKR = 1
2211 23:05:32.569585 DQ_P2S_RATIO = 8
2212 23:05:32.573119 ===================================
2213 23:05:32.576276 CA_P2S_RATIO = 8
2214 23:05:32.579529 DQ_CA_OPEN = 0
2215 23:05:32.579611 DQ_SEMI_OPEN = 0
2216 23:05:32.583384 CA_SEMI_OPEN = 0
2217 23:05:32.586661 CA_FULL_RATE = 0
2218 23:05:32.589766 DQ_CKDIV4_EN = 0
2219 23:05:32.593011 CA_CKDIV4_EN = 0
2220 23:05:32.596237 CA_PREDIV_EN = 0
2221 23:05:32.596319 PH8_DLY = 17
2222 23:05:32.599858 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2223 23:05:32.603332 DQ_AAMCK_DIV = 4
2224 23:05:32.606284 CA_AAMCK_DIV = 4
2225 23:05:32.610025 CA_ADMCK_DIV = 4
2226 23:05:32.613355 DQ_TRACK_CA_EN = 0
2227 23:05:32.613437 CA_PICK = 1200
2228 23:05:32.616519 CA_MCKIO = 1200
2229 23:05:32.619699 MCKIO_SEMI = 0
2230 23:05:32.623540 PLL_FREQ = 2366
2231 23:05:32.626729 DQ_UI_PI_RATIO = 32
2232 23:05:32.630025 CA_UI_PI_RATIO = 0
2233 23:05:32.633123 ===================================
2234 23:05:32.636600 ===================================
2235 23:05:32.639687 memory_type:LPDDR4
2236 23:05:32.639769 GP_NUM : 10
2237 23:05:32.643549 SRAM_EN : 1
2238 23:05:32.643630 MD32_EN : 0
2239 23:05:32.646587 ===================================
2240 23:05:32.649923 [ANA_INIT] >>>>>>>>>>>>>>
2241 23:05:32.653107 <<<<<< [CONFIGURE PHASE]: ANA_TX
2242 23:05:32.656769 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2243 23:05:32.659866 ===================================
2244 23:05:32.663080 data_rate = 2400,PCW = 0X5b00
2245 23:05:32.666832 ===================================
2246 23:05:32.670005 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2247 23:05:32.673023 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2248 23:05:32.680182 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2249 23:05:32.683301 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2250 23:05:32.686641 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2251 23:05:32.689885 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2252 23:05:32.693066 [ANA_INIT] flow start
2253 23:05:32.696308 [ANA_INIT] PLL >>>>>>>>
2254 23:05:32.696416 [ANA_INIT] PLL <<<<<<<<
2255 23:05:32.699896 [ANA_INIT] MIDPI >>>>>>>>
2256 23:05:32.703414 [ANA_INIT] MIDPI <<<<<<<<
2257 23:05:32.706791 [ANA_INIT] DLL >>>>>>>>
2258 23:05:32.706899 [ANA_INIT] DLL <<<<<<<<
2259 23:05:32.709798 [ANA_INIT] flow end
2260 23:05:32.712946 ============ LP4 DIFF to SE enter ============
2261 23:05:32.716911 ============ LP4 DIFF to SE exit ============
2262 23:05:32.719819 [ANA_INIT] <<<<<<<<<<<<<
2263 23:05:32.723123 [Flow] Enable top DCM control >>>>>
2264 23:05:32.726859 [Flow] Enable top DCM control <<<<<
2265 23:05:32.730114 Enable DLL master slave shuffle
2266 23:05:32.733278 ==============================================================
2267 23:05:32.736498 Gating Mode config
2268 23:05:32.743097 ==============================================================
2269 23:05:32.743183 Config description:
2270 23:05:32.753352 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2271 23:05:32.759717 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2272 23:05:32.766463 SELPH_MODE 0: By rank 1: By Phase
2273 23:05:32.770122 ==============================================================
2274 23:05:32.772994 GAT_TRACK_EN = 1
2275 23:05:32.776357 RX_GATING_MODE = 2
2276 23:05:32.779687 RX_GATING_TRACK_MODE = 2
2277 23:05:32.783015 SELPH_MODE = 1
2278 23:05:32.786887 PICG_EARLY_EN = 1
2279 23:05:32.790121 VALID_LAT_VALUE = 1
2280 23:05:32.793639 ==============================================================
2281 23:05:32.796452 Enter into Gating configuration >>>>
2282 23:05:32.800100 Exit from Gating configuration <<<<
2283 23:05:32.803685 Enter into DVFS_PRE_config >>>>>
2284 23:05:32.813508 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2285 23:05:32.817084 Exit from DVFS_PRE_config <<<<<
2286 23:05:32.819912 Enter into PICG configuration >>>>
2287 23:05:32.823768 Exit from PICG configuration <<<<
2288 23:05:32.826896 [RX_INPUT] configuration >>>>>
2289 23:05:32.830436 [RX_INPUT] configuration <<<<<
2290 23:05:32.836606 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2291 23:05:32.840353 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2292 23:05:32.846958 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2293 23:05:32.853220 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2294 23:05:32.860254 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2295 23:05:32.866600 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2296 23:05:32.869877 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2297 23:05:32.873805 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2298 23:05:32.876713 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2299 23:05:32.880306 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2300 23:05:32.886999 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2301 23:05:32.890294 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2302 23:05:32.893467 ===================================
2303 23:05:32.896784 LPDDR4 DRAM CONFIGURATION
2304 23:05:32.900371 ===================================
2305 23:05:32.900449 EX_ROW_EN[0] = 0x0
2306 23:05:32.903946 EX_ROW_EN[1] = 0x0
2307 23:05:32.904052 LP4Y_EN = 0x0
2308 23:05:32.906620 WORK_FSP = 0x0
2309 23:05:32.906705 WL = 0x4
2310 23:05:32.910472 RL = 0x4
2311 23:05:32.910552 BL = 0x2
2312 23:05:32.913571 RPST = 0x0
2313 23:05:32.913698 RD_PRE = 0x0
2314 23:05:32.916947 WR_PRE = 0x1
2315 23:05:32.920279 WR_PST = 0x0
2316 23:05:32.920356 DBI_WR = 0x0
2317 23:05:32.923943 DBI_RD = 0x0
2318 23:05:32.924047 OTF = 0x1
2319 23:05:32.927189 ===================================
2320 23:05:32.930262 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2321 23:05:32.933434 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2322 23:05:32.940305 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2323 23:05:32.943497 ===================================
2324 23:05:32.943654 LPDDR4 DRAM CONFIGURATION
2325 23:05:32.947154 ===================================
2326 23:05:32.950254 EX_ROW_EN[0] = 0x10
2327 23:05:32.953971 EX_ROW_EN[1] = 0x0
2328 23:05:32.954054 LP4Y_EN = 0x0
2329 23:05:32.956762 WORK_FSP = 0x0
2330 23:05:32.956843 WL = 0x4
2331 23:05:32.960210 RL = 0x4
2332 23:05:32.960352 BL = 0x2
2333 23:05:32.963508 RPST = 0x0
2334 23:05:32.963661 RD_PRE = 0x0
2335 23:05:32.967417 WR_PRE = 0x1
2336 23:05:32.967552 WR_PST = 0x0
2337 23:05:32.970795 DBI_WR = 0x0
2338 23:05:32.970926 DBI_RD = 0x0
2339 23:05:32.973946 OTF = 0x1
2340 23:05:32.977195 ===================================
2341 23:05:32.983553 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2342 23:05:32.983728 ==
2343 23:05:32.987260 Dram Type= 6, Freq= 0, CH_0, rank 0
2344 23:05:32.990449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2345 23:05:32.990556 ==
2346 23:05:32.994170 [Duty_Offset_Calibration]
2347 23:05:32.994276 B0:2 B1:1 CA:1
2348 23:05:32.994366
2349 23:05:32.997390 [DutyScan_Calibration_Flow] k_type=0
2350 23:05:33.007434
2351 23:05:33.007544 ==CLK 0==
2352 23:05:33.010404 Final CLK duty delay cell = 0
2353 23:05:33.013701 [0] MAX Duty = 5187%(X100), DQS PI = 24
2354 23:05:33.017627 [0] MIN Duty = 4844%(X100), DQS PI = 48
2355 23:05:33.017761 [0] AVG Duty = 5015%(X100)
2356 23:05:33.020453
2357 23:05:33.024159 CH0 CLK Duty spec in!! Max-Min= 343%
2358 23:05:33.027659 [DutyScan_Calibration_Flow] ====Done====
2359 23:05:33.027768
2360 23:05:33.030294 [DutyScan_Calibration_Flow] k_type=1
2361 23:05:33.045784
2362 23:05:33.045924 ==DQS 0 ==
2363 23:05:33.049055 Final DQS duty delay cell = -4
2364 23:05:33.052306 [-4] MAX Duty = 5124%(X100), DQS PI = 24
2365 23:05:33.056106 [-4] MIN Duty = 4782%(X100), DQS PI = 0
2366 23:05:33.059182 [-4] AVG Duty = 4953%(X100)
2367 23:05:33.059275
2368 23:05:33.059345 ==DQS 1 ==
2369 23:05:33.062238 Final DQS duty delay cell = 0
2370 23:05:33.065977 [0] MAX Duty = 5156%(X100), DQS PI = 62
2371 23:05:33.069672 [0] MIN Duty = 5000%(X100), DQS PI = 34
2372 23:05:33.072394 [0] AVG Duty = 5078%(X100)
2373 23:05:33.072479
2374 23:05:33.075657 CH0 DQS 0 Duty spec in!! Max-Min= 342%
2375 23:05:33.075744
2376 23:05:33.078952 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2377 23:05:33.082410 [DutyScan_Calibration_Flow] ====Done====
2378 23:05:33.082539
2379 23:05:33.085565 [DutyScan_Calibration_Flow] k_type=3
2380 23:05:33.103206
2381 23:05:33.103297 ==DQM 0 ==
2382 23:05:33.106265 Final DQM duty delay cell = 0
2383 23:05:33.109524 [0] MAX Duty = 5156%(X100), DQS PI = 30
2384 23:05:33.112965 [0] MIN Duty = 4906%(X100), DQS PI = 58
2385 23:05:33.113048 [0] AVG Duty = 5031%(X100)
2386 23:05:33.116100
2387 23:05:33.116192 ==DQM 1 ==
2388 23:05:33.119343 Final DQM duty delay cell = 0
2389 23:05:33.122618 [0] MAX Duty = 5093%(X100), DQS PI = 0
2390 23:05:33.125851 [0] MIN Duty = 5031%(X100), DQS PI = 36
2391 23:05:33.125936 [0] AVG Duty = 5062%(X100)
2392 23:05:33.129841
2393 23:05:33.133082 CH0 DQM 0 Duty spec in!! Max-Min= 250%
2394 23:05:33.133169
2395 23:05:33.136326 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2396 23:05:33.139343 [DutyScan_Calibration_Flow] ====Done====
2397 23:05:33.139438
2398 23:05:33.142568 [DutyScan_Calibration_Flow] k_type=2
2399 23:05:33.159674
2400 23:05:33.159866 ==DQ 0 ==
2401 23:05:33.162275 Final DQ duty delay cell = 0
2402 23:05:33.165928 [0] MAX Duty = 5031%(X100), DQS PI = 24
2403 23:05:33.169479 [0] MIN Duty = 4906%(X100), DQS PI = 0
2404 23:05:33.169627 [0] AVG Duty = 4968%(X100)
2405 23:05:33.169749
2406 23:05:33.172537 ==DQ 1 ==
2407 23:05:33.175765 Final DQ duty delay cell = 0
2408 23:05:33.179528 [0] MAX Duty = 5093%(X100), DQS PI = 10
2409 23:05:33.182414 [0] MIN Duty = 4907%(X100), DQS PI = 36
2410 23:05:33.182525 [0] AVG Duty = 5000%(X100)
2411 23:05:33.182629
2412 23:05:33.186010 CH0 DQ 0 Duty spec in!! Max-Min= 125%
2413 23:05:33.186106
2414 23:05:33.189244 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2415 23:05:33.195580 [DutyScan_Calibration_Flow] ====Done====
2416 23:05:33.195662 ==
2417 23:05:33.198817 Dram Type= 6, Freq= 0, CH_1, rank 0
2418 23:05:33.202734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2419 23:05:33.202836 ==
2420 23:05:33.206110 [Duty_Offset_Calibration]
2421 23:05:33.206185 B0:1 B1:0 CA:0
2422 23:05:33.206253
2423 23:05:33.209158 [DutyScan_Calibration_Flow] k_type=0
2424 23:05:33.218490
2425 23:05:33.218606 ==CLK 0==
2426 23:05:33.221924 Final CLK duty delay cell = -4
2427 23:05:33.225081 [-4] MAX Duty = 5000%(X100), DQS PI = 20
2428 23:05:33.228365 [-4] MIN Duty = 4907%(X100), DQS PI = 50
2429 23:05:33.232134 [-4] AVG Duty = 4953%(X100)
2430 23:05:33.232240
2431 23:05:33.234882 CH1 CLK Duty spec in!! Max-Min= 93%
2432 23:05:33.238837 [DutyScan_Calibration_Flow] ====Done====
2433 23:05:33.238910
2434 23:05:33.241899 [DutyScan_Calibration_Flow] k_type=1
2435 23:05:33.258264
2436 23:05:33.258372 ==DQS 0 ==
2437 23:05:33.261213 Final DQS duty delay cell = 0
2438 23:05:33.264537 [0] MAX Duty = 5094%(X100), DQS PI = 24
2439 23:05:33.268211 [0] MIN Duty = 4875%(X100), DQS PI = 0
2440 23:05:33.268292 [0] AVG Duty = 4984%(X100)
2441 23:05:33.271390
2442 23:05:33.271471 ==DQS 1 ==
2443 23:05:33.274612 Final DQS duty delay cell = 0
2444 23:05:33.278001 [0] MAX Duty = 5187%(X100), DQS PI = 20
2445 23:05:33.281566 [0] MIN Duty = 4969%(X100), DQS PI = 8
2446 23:05:33.281688 [0] AVG Duty = 5078%(X100)
2447 23:05:33.284908
2448 23:05:33.287974 CH1 DQS 0 Duty spec in!! Max-Min= 219%
2449 23:05:33.288083
2450 23:05:33.291589 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2451 23:05:33.294648 [DutyScan_Calibration_Flow] ====Done====
2452 23:05:33.294725
2453 23:05:33.297752 [DutyScan_Calibration_Flow] k_type=3
2454 23:05:33.315008
2455 23:05:33.315101 ==DQM 0 ==
2456 23:05:33.317871 Final DQM duty delay cell = 0
2457 23:05:33.321288 [0] MAX Duty = 5156%(X100), DQS PI = 8
2458 23:05:33.324453 [0] MIN Duty = 5031%(X100), DQS PI = 0
2459 23:05:33.324552 [0] AVG Duty = 5093%(X100)
2460 23:05:33.324641
2461 23:05:33.328166 ==DQM 1 ==
2462 23:05:33.331780 Final DQM duty delay cell = 0
2463 23:05:33.334508 [0] MAX Duty = 5031%(X100), DQS PI = 16
2464 23:05:33.337899 [0] MIN Duty = 4907%(X100), DQS PI = 36
2465 23:05:33.337981 [0] AVG Duty = 4969%(X100)
2466 23:05:33.338047
2467 23:05:33.344896 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2468 23:05:33.344978
2469 23:05:33.348190 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2470 23:05:33.351556 [DutyScan_Calibration_Flow] ====Done====
2471 23:05:33.351638
2472 23:05:33.354660 [DutyScan_Calibration_Flow] k_type=2
2473 23:05:33.370647
2474 23:05:33.370730 ==DQ 0 ==
2475 23:05:33.373781 Final DQ duty delay cell = -4
2476 23:05:33.377176 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2477 23:05:33.380778 [-4] MIN Duty = 4938%(X100), DQS PI = 0
2478 23:05:33.380861 [-4] AVG Duty = 5000%(X100)
2479 23:05:33.384170
2480 23:05:33.384251 ==DQ 1 ==
2481 23:05:33.387199 Final DQ duty delay cell = 0
2482 23:05:33.390589 [0] MAX Duty = 5125%(X100), DQS PI = 20
2483 23:05:33.394265 [0] MIN Duty = 4969%(X100), DQS PI = 12
2484 23:05:33.394348 [0] AVG Duty = 5047%(X100)
2485 23:05:33.394413
2486 23:05:33.397295 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2487 23:05:33.400297
2488 23:05:33.403600 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2489 23:05:33.407529 [DutyScan_Calibration_Flow] ====Done====
2490 23:05:33.410573 nWR fixed to 30
2491 23:05:33.410656 [ModeRegInit_LP4] CH0 RK0
2492 23:05:33.413841 [ModeRegInit_LP4] CH0 RK1
2493 23:05:33.417399 [ModeRegInit_LP4] CH1 RK0
2494 23:05:33.417481 [ModeRegInit_LP4] CH1 RK1
2495 23:05:33.420707 match AC timing 7
2496 23:05:33.424022 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2497 23:05:33.427299 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2498 23:05:33.434322 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2499 23:05:33.437255 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2500 23:05:33.443805 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2501 23:05:33.443887 ==
2502 23:05:33.447592 Dram Type= 6, Freq= 0, CH_0, rank 0
2503 23:05:33.450476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2504 23:05:33.450559 ==
2505 23:05:33.457365 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2506 23:05:33.460933 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2507 23:05:33.470600 [CA 0] Center 39 (8~70) winsize 63
2508 23:05:33.473784 [CA 1] Center 39 (8~70) winsize 63
2509 23:05:33.477448 [CA 2] Center 35 (5~66) winsize 62
2510 23:05:33.480497 [CA 3] Center 34 (4~65) winsize 62
2511 23:05:33.483771 [CA 4] Center 33 (3~64) winsize 62
2512 23:05:33.487228 [CA 5] Center 32 (3~62) winsize 60
2513 23:05:33.487312
2514 23:05:33.490584 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2515 23:05:33.490681
2516 23:05:33.493505 [CATrainingPosCal] consider 1 rank data
2517 23:05:33.497396 u2DelayCellTimex100 = 270/100 ps
2518 23:05:33.500283 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2519 23:05:33.507373 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2520 23:05:33.510932 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2521 23:05:33.513799 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2522 23:05:33.517585 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2523 23:05:33.520754 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2524 23:05:33.520852
2525 23:05:33.523898 CA PerBit enable=1, Macro0, CA PI delay=32
2526 23:05:33.523975
2527 23:05:33.527040 [CBTSetCACLKResult] CA Dly = 32
2528 23:05:33.527139 CS Dly: 6 (0~37)
2529 23:05:33.527235 ==
2530 23:05:33.530929 Dram Type= 6, Freq= 0, CH_0, rank 1
2531 23:05:33.537345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2532 23:05:33.537453 ==
2533 23:05:33.540441 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2534 23:05:33.547078 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2535 23:05:33.556794 [CA 0] Center 38 (8~69) winsize 62
2536 23:05:33.559581 [CA 1] Center 38 (8~69) winsize 62
2537 23:05:33.563087 [CA 2] Center 35 (4~66) winsize 63
2538 23:05:33.566353 [CA 3] Center 34 (4~65) winsize 62
2539 23:05:33.570006 [CA 4] Center 33 (3~64) winsize 62
2540 23:05:33.573260 [CA 5] Center 32 (3~62) winsize 60
2541 23:05:33.573366
2542 23:05:33.576392 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2543 23:05:33.576492
2544 23:05:33.579431 [CATrainingPosCal] consider 2 rank data
2545 23:05:33.583240 u2DelayCellTimex100 = 270/100 ps
2546 23:05:33.586444 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2547 23:05:33.589755 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2548 23:05:33.596604 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2549 23:05:33.599628 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2550 23:05:33.602745 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2551 23:05:33.606217 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2552 23:05:33.606298
2553 23:05:33.609898 CA PerBit enable=1, Macro0, CA PI delay=32
2554 23:05:33.609979
2555 23:05:33.613296 [CBTSetCACLKResult] CA Dly = 32
2556 23:05:33.613376 CS Dly: 6 (0~38)
2557 23:05:33.613440
2558 23:05:33.616505 ----->DramcWriteLeveling(PI) begin...
2559 23:05:33.619684 ==
2560 23:05:33.619765 Dram Type= 6, Freq= 0, CH_0, rank 0
2561 23:05:33.626301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2562 23:05:33.626387 ==
2563 23:05:33.629497 Write leveling (Byte 0): 34 => 34
2564 23:05:33.633389 Write leveling (Byte 1): 27 => 27
2565 23:05:33.636519 DramcWriteLeveling(PI) end<-----
2566 23:05:33.636621
2567 23:05:33.636710 ==
2568 23:05:33.639804 Dram Type= 6, Freq= 0, CH_0, rank 0
2569 23:05:33.642948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2570 23:05:33.643048 ==
2571 23:05:33.646234 [Gating] SW mode calibration
2572 23:05:33.653417 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2573 23:05:33.656550 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2574 23:05:33.663252 0 15 0 | B1->B0 | 2424 3333 | 0 1 | (0 0) (1 1)
2575 23:05:33.666591 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2576 23:05:33.669770 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2577 23:05:33.676355 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2578 23:05:33.679927 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2579 23:05:33.683630 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2580 23:05:33.689639 0 15 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
2581 23:05:33.692949 0 15 28 | B1->B0 | 3434 2626 | 1 0 | (1 1) (1 0)
2582 23:05:33.696612 1 0 0 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
2583 23:05:33.703199 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2584 23:05:33.706516 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2585 23:05:33.710058 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2586 23:05:33.716410 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2587 23:05:33.720076 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2588 23:05:33.723233 1 0 24 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
2589 23:05:33.726557 1 0 28 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
2590 23:05:33.733114 1 1 0 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
2591 23:05:33.736661 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2592 23:05:33.739846 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2593 23:05:33.746333 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2594 23:05:33.750134 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2595 23:05:33.753428 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2596 23:05:33.759923 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2597 23:05:33.762949 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2598 23:05:33.766820 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2599 23:05:33.773524 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2600 23:05:33.776781 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2601 23:05:33.779763 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2602 23:05:33.786544 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2603 23:05:33.789884 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2604 23:05:33.793643 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2605 23:05:33.799804 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2606 23:05:33.803242 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2607 23:05:33.806690 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2608 23:05:33.810415 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2609 23:05:33.816753 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2610 23:05:33.819946 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 23:05:33.823522 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 23:05:33.829947 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 23:05:33.833735 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2614 23:05:33.836655 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2615 23:05:33.840508 Total UI for P1: 0, mck2ui 16
2616 23:05:33.843620 best dqsien dly found for B0: ( 1, 3, 28)
2617 23:05:33.846774 Total UI for P1: 0, mck2ui 16
2618 23:05:33.850181 best dqsien dly found for B1: ( 1, 3, 30)
2619 23:05:33.853264 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2620 23:05:33.857055 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2621 23:05:33.857132
2622 23:05:33.863473 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2623 23:05:33.866502 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2624 23:05:33.866579 [Gating] SW calibration Done
2625 23:05:33.870262 ==
2626 23:05:33.873315 Dram Type= 6, Freq= 0, CH_0, rank 0
2627 23:05:33.877192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2628 23:05:33.877266 ==
2629 23:05:33.877327 RX Vref Scan: 0
2630 23:05:33.877385
2631 23:05:33.880419 RX Vref 0 -> 0, step: 1
2632 23:05:33.880500
2633 23:05:33.883549 RX Delay -40 -> 252, step: 8
2634 23:05:33.886827 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2635 23:05:33.890497 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2636 23:05:33.893438 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2637 23:05:33.900163 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2638 23:05:33.903559 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2639 23:05:33.906491 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2640 23:05:33.910168 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2641 23:05:33.913525 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2642 23:05:33.920333 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2643 23:05:33.923419 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2644 23:05:33.927094 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2645 23:05:33.930276 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2646 23:05:33.933538 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2647 23:05:33.940431 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2648 23:05:33.943728 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2649 23:05:33.946904 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2650 23:05:33.946979 ==
2651 23:05:33.950048 Dram Type= 6, Freq= 0, CH_0, rank 0
2652 23:05:33.953767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2653 23:05:33.953843 ==
2654 23:05:33.956749 DQS Delay:
2655 23:05:33.956826 DQS0 = 0, DQS1 = 0
2656 23:05:33.960531 DQM Delay:
2657 23:05:33.960632 DQM0 = 121, DQM1 = 113
2658 23:05:33.960723 DQ Delay:
2659 23:05:33.963429 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2660 23:05:33.967263 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2661 23:05:33.974057 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2662 23:05:33.977298 DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =119
2663 23:05:33.977394
2664 23:05:33.977459
2665 23:05:33.977519 ==
2666 23:05:33.980561 Dram Type= 6, Freq= 0, CH_0, rank 0
2667 23:05:33.983814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2668 23:05:33.983895 ==
2669 23:05:33.983960
2670 23:05:33.984019
2671 23:05:33.987626 TX Vref Scan disable
2672 23:05:33.987707 == TX Byte 0 ==
2673 23:05:33.994238 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2674 23:05:33.997472 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2675 23:05:33.997553 == TX Byte 1 ==
2676 23:05:34.003911 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2677 23:05:34.007085 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2678 23:05:34.007166 ==
2679 23:05:34.010350 Dram Type= 6, Freq= 0, CH_0, rank 0
2680 23:05:34.013923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2681 23:05:34.014004 ==
2682 23:05:34.027082 TX Vref=22, minBit 0, minWin=24, winSum=404
2683 23:05:34.030790 TX Vref=24, minBit 0, minWin=25, winSum=413
2684 23:05:34.033864 TX Vref=26, minBit 4, minWin=25, winSum=421
2685 23:05:34.037040 TX Vref=28, minBit 0, minWin=26, winSum=421
2686 23:05:34.040398 TX Vref=30, minBit 0, minWin=26, winSum=424
2687 23:05:34.043672 TX Vref=32, minBit 1, minWin=26, winSum=423
2688 23:05:34.050573 [TxChooseVref] Worse bit 0, Min win 26, Win sum 424, Final Vref 30
2689 23:05:34.050663
2690 23:05:34.053808 Final TX Range 1 Vref 30
2691 23:05:34.053894
2692 23:05:34.053958 ==
2693 23:05:34.057165 Dram Type= 6, Freq= 0, CH_0, rank 0
2694 23:05:34.060312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2695 23:05:34.060393 ==
2696 23:05:34.060457
2697 23:05:34.063969
2698 23:05:34.064048 TX Vref Scan disable
2699 23:05:34.067169 == TX Byte 0 ==
2700 23:05:34.070197 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2701 23:05:34.073770 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2702 23:05:34.076992 == TX Byte 1 ==
2703 23:05:34.080573 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2704 23:05:34.083547 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2705 23:05:34.083628
2706 23:05:34.087472 [DATLAT]
2707 23:05:34.087552 Freq=1200, CH0 RK0
2708 23:05:34.087616
2709 23:05:34.090643 DATLAT Default: 0xd
2710 23:05:34.090723 0, 0xFFFF, sum = 0
2711 23:05:34.093754 1, 0xFFFF, sum = 0
2712 23:05:34.093862 2, 0xFFFF, sum = 0
2713 23:05:34.097316 3, 0xFFFF, sum = 0
2714 23:05:34.097397 4, 0xFFFF, sum = 0
2715 23:05:34.100513 5, 0xFFFF, sum = 0
2716 23:05:34.100595 6, 0xFFFF, sum = 0
2717 23:05:34.103693 7, 0xFFFF, sum = 0
2718 23:05:34.103775 8, 0xFFFF, sum = 0
2719 23:05:34.107567 9, 0xFFFF, sum = 0
2720 23:05:34.110828 10, 0xFFFF, sum = 0
2721 23:05:34.110909 11, 0xFFFF, sum = 0
2722 23:05:34.114131 12, 0x0, sum = 1
2723 23:05:34.114212 13, 0x0, sum = 2
2724 23:05:34.114277 14, 0x0, sum = 3
2725 23:05:34.117472 15, 0x0, sum = 4
2726 23:05:34.117562 best_step = 13
2727 23:05:34.117661
2728 23:05:34.117720 ==
2729 23:05:34.120968 Dram Type= 6, Freq= 0, CH_0, rank 0
2730 23:05:34.127455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2731 23:05:34.127536 ==
2732 23:05:34.127600 RX Vref Scan: 1
2733 23:05:34.127659
2734 23:05:34.130867 Set Vref Range= 32 -> 127
2735 23:05:34.130950
2736 23:05:34.134045 RX Vref 32 -> 127, step: 1
2737 23:05:34.134126
2738 23:05:34.137279 RX Delay -13 -> 252, step: 4
2739 23:05:34.137359
2740 23:05:34.140456 Set Vref, RX VrefLevel [Byte0]: 32
2741 23:05:34.144058 [Byte1]: 32
2742 23:05:34.144138
2743 23:05:34.147606 Set Vref, RX VrefLevel [Byte0]: 33
2744 23:05:34.150768 [Byte1]: 33
2745 23:05:34.150848
2746 23:05:34.153836 Set Vref, RX VrefLevel [Byte0]: 34
2747 23:05:34.157050 [Byte1]: 34
2748 23:05:34.161539
2749 23:05:34.161670 Set Vref, RX VrefLevel [Byte0]: 35
2750 23:05:34.164845 [Byte1]: 35
2751 23:05:34.168941
2752 23:05:34.169021 Set Vref, RX VrefLevel [Byte0]: 36
2753 23:05:34.172293 [Byte1]: 36
2754 23:05:34.176724
2755 23:05:34.176869 Set Vref, RX VrefLevel [Byte0]: 37
2756 23:05:34.180569 [Byte1]: 37
2757 23:05:34.184890
2758 23:05:34.184991 Set Vref, RX VrefLevel [Byte0]: 38
2759 23:05:34.187989 [Byte1]: 38
2760 23:05:34.192889
2761 23:05:34.193007 Set Vref, RX VrefLevel [Byte0]: 39
2762 23:05:34.195888 [Byte1]: 39
2763 23:05:34.200564
2764 23:05:34.200666 Set Vref, RX VrefLevel [Byte0]: 40
2765 23:05:34.204093 [Byte1]: 40
2766 23:05:34.208392
2767 23:05:34.208511 Set Vref, RX VrefLevel [Byte0]: 41
2768 23:05:34.212054 [Byte1]: 41
2769 23:05:34.216753
2770 23:05:34.216872 Set Vref, RX VrefLevel [Byte0]: 42
2771 23:05:34.219992 [Byte1]: 42
2772 23:05:34.224209
2773 23:05:34.224303 Set Vref, RX VrefLevel [Byte0]: 43
2774 23:05:34.227462 [Byte1]: 43
2775 23:05:34.232535
2776 23:05:34.232638 Set Vref, RX VrefLevel [Byte0]: 44
2777 23:05:34.235767 [Byte1]: 44
2778 23:05:34.240267
2779 23:05:34.240377 Set Vref, RX VrefLevel [Byte0]: 45
2780 23:05:34.243655 [Byte1]: 45
2781 23:05:34.248020
2782 23:05:34.248126 Set Vref, RX VrefLevel [Byte0]: 46
2783 23:05:34.251334 [Byte1]: 46
2784 23:05:34.256116
2785 23:05:34.256237 Set Vref, RX VrefLevel [Byte0]: 47
2786 23:05:34.259480 [Byte1]: 47
2787 23:05:34.263946
2788 23:05:34.264047 Set Vref, RX VrefLevel [Byte0]: 48
2789 23:05:34.267263 [Byte1]: 48
2790 23:05:34.271660
2791 23:05:34.271763 Set Vref, RX VrefLevel [Byte0]: 49
2792 23:05:34.274670 [Byte1]: 49
2793 23:05:34.279575
2794 23:05:34.279671 Set Vref, RX VrefLevel [Byte0]: 50
2795 23:05:34.282909 [Byte1]: 50
2796 23:05:34.287452
2797 23:05:34.287535 Set Vref, RX VrefLevel [Byte0]: 51
2798 23:05:34.291088 [Byte1]: 51
2799 23:05:34.295541
2800 23:05:34.295616 Set Vref, RX VrefLevel [Byte0]: 52
2801 23:05:34.298377 [Byte1]: 52
2802 23:05:34.303598
2803 23:05:34.303671 Set Vref, RX VrefLevel [Byte0]: 53
2804 23:05:34.306786 [Byte1]: 53
2805 23:05:34.311129
2806 23:05:34.311205 Set Vref, RX VrefLevel [Byte0]: 54
2807 23:05:34.314530 [Byte1]: 54
2808 23:05:34.319029
2809 23:05:34.319097 Set Vref, RX VrefLevel [Byte0]: 55
2810 23:05:34.322321 [Byte1]: 55
2811 23:05:34.326997
2812 23:05:34.327104 Set Vref, RX VrefLevel [Byte0]: 56
2813 23:05:34.330166 [Byte1]: 56
2814 23:05:34.334532
2815 23:05:34.334613 Set Vref, RX VrefLevel [Byte0]: 57
2816 23:05:34.338299 [Byte1]: 57
2817 23:05:34.342711
2818 23:05:34.342789 Set Vref, RX VrefLevel [Byte0]: 58
2819 23:05:34.346057 [Byte1]: 58
2820 23:05:34.350684
2821 23:05:34.350753 Set Vref, RX VrefLevel [Byte0]: 59
2822 23:05:34.353775 [Byte1]: 59
2823 23:05:34.358442
2824 23:05:34.358535 Set Vref, RX VrefLevel [Byte0]: 60
2825 23:05:34.362029 [Byte1]: 60
2826 23:05:34.366852
2827 23:05:34.366954 Set Vref, RX VrefLevel [Byte0]: 61
2828 23:05:34.369792 [Byte1]: 61
2829 23:05:34.374273
2830 23:05:34.374372 Set Vref, RX VrefLevel [Byte0]: 62
2831 23:05:34.377938 [Byte1]: 62
2832 23:05:34.382432
2833 23:05:34.382514 Set Vref, RX VrefLevel [Byte0]: 63
2834 23:05:34.385701 [Byte1]: 63
2835 23:05:34.390022
2836 23:05:34.390126 Set Vref, RX VrefLevel [Byte0]: 64
2837 23:05:34.393429 [Byte1]: 64
2838 23:05:34.397999
2839 23:05:34.398081 Set Vref, RX VrefLevel [Byte0]: 65
2840 23:05:34.401385 [Byte1]: 65
2841 23:05:34.405914
2842 23:05:34.405995 Set Vref, RX VrefLevel [Byte0]: 66
2843 23:05:34.408968 [Byte1]: 66
2844 23:05:34.413629
2845 23:05:34.413710 Set Vref, RX VrefLevel [Byte0]: 67
2846 23:05:34.416940 [Byte1]: 67
2847 23:05:34.421935
2848 23:05:34.422041 Set Vref, RX VrefLevel [Byte0]: 68
2849 23:05:34.424850 [Byte1]: 68
2850 23:05:34.429899
2851 23:05:34.429979 Set Vref, RX VrefLevel [Byte0]: 69
2852 23:05:34.432857 [Byte1]: 69
2853 23:05:34.437400
2854 23:05:34.437507 Set Vref, RX VrefLevel [Byte0]: 70
2855 23:05:34.440659 [Byte1]: 70
2856 23:05:34.445017
2857 23:05:34.445123 Final RX Vref Byte 0 = 54 to rank0
2858 23:05:34.448369 Final RX Vref Byte 1 = 53 to rank0
2859 23:05:34.452218 Final RX Vref Byte 0 = 54 to rank1
2860 23:05:34.455553 Final RX Vref Byte 1 = 53 to rank1==
2861 23:05:34.458847 Dram Type= 6, Freq= 0, CH_0, rank 0
2862 23:05:34.461908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2863 23:05:34.465713 ==
2864 23:05:34.465828 DQS Delay:
2865 23:05:34.465921 DQS0 = 0, DQS1 = 0
2866 23:05:34.468703 DQM Delay:
2867 23:05:34.468793 DQM0 = 120, DQM1 = 112
2868 23:05:34.471758 DQ Delay:
2869 23:05:34.475415 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
2870 23:05:34.478583 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =128
2871 23:05:34.482358 DQ8 =100, DQ9 =102, DQ10 =112, DQ11 =106
2872 23:05:34.485704 DQ12 =118, DQ13 =116, DQ14 =124, DQ15 =122
2873 23:05:34.485781
2874 23:05:34.485849
2875 23:05:34.492040 [DQSOSCAuto] RK0, (LSB)MR18= 0x1812, (MSB)MR19= 0x404, tDQSOscB0 = 403 ps tDQSOscB1 = 400 ps
2876 23:05:34.495216 CH0 RK0: MR19=404, MR18=1812
2877 23:05:34.502261 CH0_RK0: MR19=0x404, MR18=0x1812, DQSOSC=400, MR23=63, INC=40, DEC=27
2878 23:05:34.502344
2879 23:05:34.505343 ----->DramcWriteLeveling(PI) begin...
2880 23:05:34.505456 ==
2881 23:05:34.508628 Dram Type= 6, Freq= 0, CH_0, rank 1
2882 23:05:34.512305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2883 23:05:34.515406 ==
2884 23:05:34.515487 Write leveling (Byte 0): 34 => 34
2885 23:05:34.518576 Write leveling (Byte 1): 28 => 28
2886 23:05:34.522528 DramcWriteLeveling(PI) end<-----
2887 23:05:34.522608
2888 23:05:34.522671 ==
2889 23:05:34.525150 Dram Type= 6, Freq= 0, CH_0, rank 1
2890 23:05:34.532117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2891 23:05:34.532198 ==
2892 23:05:34.532263 [Gating] SW mode calibration
2893 23:05:34.541797 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2894 23:05:34.545436 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2895 23:05:34.548822 0 15 0 | B1->B0 | 3434 3030 | 0 1 | (0 0) (0 0)
2896 23:05:34.555226 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2897 23:05:34.558652 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2898 23:05:34.562197 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2899 23:05:34.568926 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2900 23:05:34.571967 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2901 23:05:34.575582 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
2902 23:05:34.582193 0 15 28 | B1->B0 | 3232 3131 | 0 0 | (1 0) (0 0)
2903 23:05:34.585363 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
2904 23:05:34.589287 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2905 23:05:34.595660 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2906 23:05:34.598914 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2907 23:05:34.602114 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2908 23:05:34.609110 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2909 23:05:34.612216 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2910 23:05:34.615731 1 0 28 | B1->B0 | 3a3a 3939 | 0 1 | (0 0) (0 0)
2911 23:05:34.618789 1 1 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
2912 23:05:34.625433 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2913 23:05:34.628934 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2914 23:05:34.632430 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2915 23:05:34.638685 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2916 23:05:34.641873 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2917 23:05:34.645773 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2918 23:05:34.652189 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2919 23:05:34.655846 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2920 23:05:34.658884 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2921 23:05:34.665331 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2922 23:05:34.668734 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2923 23:05:34.672271 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2924 23:05:34.678764 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2925 23:05:34.682369 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2926 23:05:34.685858 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2927 23:05:34.692191 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 23:05:34.695382 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 23:05:34.698617 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 23:05:34.705749 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 23:05:34.709004 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 23:05:34.712239 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2933 23:05:34.715364 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2934 23:05:34.722089 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2935 23:05:34.725861 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
2936 23:05:34.728737 Total UI for P1: 0, mck2ui 16
2937 23:05:34.732386 best dqsien dly found for B1: ( 1, 3, 28)
2938 23:05:34.735775 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2939 23:05:34.739039 Total UI for P1: 0, mck2ui 16
2940 23:05:34.742438 best dqsien dly found for B0: ( 1, 3, 30)
2941 23:05:34.745708 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2942 23:05:34.749070 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2943 23:05:34.749151
2944 23:05:34.755674 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2945 23:05:34.758914 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2946 23:05:34.758995 [Gating] SW calibration Done
2947 23:05:34.762473 ==
2948 23:05:34.765699 Dram Type= 6, Freq= 0, CH_0, rank 1
2949 23:05:34.768879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2950 23:05:34.768960 ==
2951 23:05:34.769025 RX Vref Scan: 0
2952 23:05:34.769085
2953 23:05:34.772734 RX Vref 0 -> 0, step: 1
2954 23:05:34.772839
2955 23:05:34.776049 RX Delay -40 -> 252, step: 8
2956 23:05:34.779063 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2957 23:05:34.782589 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2958 23:05:34.785555 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2959 23:05:34.792639 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2960 23:05:34.795975 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2961 23:05:34.799543 iDelay=200, Bit 5, Center 119 (48 ~ 191) 144
2962 23:05:34.802423 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2963 23:05:34.805750 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2964 23:05:34.812832 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2965 23:05:34.815941 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2966 23:05:34.819446 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
2967 23:05:34.822608 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2968 23:05:34.825582 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2969 23:05:34.832810 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2970 23:05:34.836023 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2971 23:05:34.839213 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2972 23:05:34.839296 ==
2973 23:05:34.842599 Dram Type= 6, Freq= 0, CH_0, rank 1
2974 23:05:34.845798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2975 23:05:34.845874 ==
2976 23:05:34.849143 DQS Delay:
2977 23:05:34.849212 DQS0 = 0, DQS1 = 0
2978 23:05:34.852444 DQM Delay:
2979 23:05:34.852513 DQM0 = 122, DQM1 = 113
2980 23:05:34.852580 DQ Delay:
2981 23:05:34.855881 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2982 23:05:34.862872 DQ4 =127, DQ5 =119, DQ6 =127, DQ7 =127
2983 23:05:34.866317 DQ8 =99, DQ9 =103, DQ10 =115, DQ11 =107
2984 23:05:34.869223 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =123
2985 23:05:34.869299
2986 23:05:34.869365
2987 23:05:34.869429 ==
2988 23:05:34.872468 Dram Type= 6, Freq= 0, CH_0, rank 1
2989 23:05:34.876477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2990 23:05:34.876548 ==
2991 23:05:34.876620
2992 23:05:34.876682
2993 23:05:34.879582 TX Vref Scan disable
2994 23:05:34.882608 == TX Byte 0 ==
2995 23:05:34.885816 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2996 23:05:34.889777 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2997 23:05:34.889858 == TX Byte 1 ==
2998 23:05:34.896014 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2999 23:05:34.899546 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3000 23:05:34.899622 ==
3001 23:05:34.902956 Dram Type= 6, Freq= 0, CH_0, rank 1
3002 23:05:34.906024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3003 23:05:34.906106 ==
3004 23:05:34.919971 TX Vref=22, minBit 1, minWin=25, winSum=414
3005 23:05:34.923350 TX Vref=24, minBit 0, minWin=26, winSum=420
3006 23:05:34.926614 TX Vref=26, minBit 0, minWin=26, winSum=421
3007 23:05:34.929860 TX Vref=28, minBit 1, minWin=26, winSum=428
3008 23:05:34.933051 TX Vref=30, minBit 1, minWin=26, winSum=431
3009 23:05:34.936306 TX Vref=32, minBit 5, minWin=25, winSum=427
3010 23:05:34.942958 [TxChooseVref] Worse bit 1, Min win 26, Win sum 431, Final Vref 30
3011 23:05:34.943041
3012 23:05:34.946407 Final TX Range 1 Vref 30
3013 23:05:34.946514
3014 23:05:34.946604 ==
3015 23:05:34.949929 Dram Type= 6, Freq= 0, CH_0, rank 1
3016 23:05:34.953211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3017 23:05:34.953318 ==
3018 23:05:34.953409
3019 23:05:34.953506
3020 23:05:34.956521 TX Vref Scan disable
3021 23:05:34.959764 == TX Byte 0 ==
3022 23:05:34.963352 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3023 23:05:34.966355 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3024 23:05:34.969909 == TX Byte 1 ==
3025 23:05:34.973623 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3026 23:05:34.976493 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3027 23:05:34.976574
3028 23:05:34.979884 [DATLAT]
3029 23:05:34.979969 Freq=1200, CH0 RK1
3030 23:05:34.980058
3031 23:05:34.983057 DATLAT Default: 0xd
3032 23:05:34.983147 0, 0xFFFF, sum = 0
3033 23:05:34.986881 1, 0xFFFF, sum = 0
3034 23:05:34.986988 2, 0xFFFF, sum = 0
3035 23:05:34.989980 3, 0xFFFF, sum = 0
3036 23:05:34.990111 4, 0xFFFF, sum = 0
3037 23:05:34.993252 5, 0xFFFF, sum = 0
3038 23:05:34.993356 6, 0xFFFF, sum = 0
3039 23:05:34.996436 7, 0xFFFF, sum = 0
3040 23:05:34.996518 8, 0xFFFF, sum = 0
3041 23:05:34.999564 9, 0xFFFF, sum = 0
3042 23:05:34.999648 10, 0xFFFF, sum = 0
3043 23:05:35.003567 11, 0xFFFF, sum = 0
3044 23:05:35.003650 12, 0x0, sum = 1
3045 23:05:35.006888 13, 0x0, sum = 2
3046 23:05:35.006989 14, 0x0, sum = 3
3047 23:05:35.009969 15, 0x0, sum = 4
3048 23:05:35.010057 best_step = 13
3049 23:05:35.010122
3050 23:05:35.010181 ==
3051 23:05:35.012987 Dram Type= 6, Freq= 0, CH_0, rank 1
3052 23:05:35.020097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3053 23:05:35.020179 ==
3054 23:05:35.020244 RX Vref Scan: 0
3055 23:05:35.020304
3056 23:05:35.023321 RX Vref 0 -> 0, step: 1
3057 23:05:35.023402
3058 23:05:35.026482 RX Delay -13 -> 252, step: 4
3059 23:05:35.030067 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3060 23:05:35.033454 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3061 23:05:35.039853 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3062 23:05:35.043536 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3063 23:05:35.046829 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3064 23:05:35.050123 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3065 23:05:35.053082 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3066 23:05:35.059815 iDelay=195, Bit 7, Center 128 (63 ~ 194) 132
3067 23:05:35.063323 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3068 23:05:35.066501 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3069 23:05:35.069636 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3070 23:05:35.073167 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3071 23:05:35.080090 iDelay=195, Bit 12, Center 116 (55 ~ 178) 124
3072 23:05:35.083509 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3073 23:05:35.086334 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3074 23:05:35.090301 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3075 23:05:35.090381 ==
3076 23:05:35.093154 Dram Type= 6, Freq= 0, CH_0, rank 1
3077 23:05:35.099686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3078 23:05:35.099770 ==
3079 23:05:35.099839 DQS Delay:
3080 23:05:35.099899 DQS0 = 0, DQS1 = 0
3081 23:05:35.103487 DQM Delay:
3082 23:05:35.103568 DQM0 = 121, DQM1 = 111
3083 23:05:35.106745 DQ Delay:
3084 23:05:35.110077 DQ0 =118, DQ1 =122, DQ2 =118, DQ3 =118
3085 23:05:35.113316 DQ4 =122, DQ5 =116, DQ6 =128, DQ7 =128
3086 23:05:35.116541 DQ8 =100, DQ9 =100, DQ10 =110, DQ11 =104
3087 23:05:35.119730 DQ12 =116, DQ13 =118, DQ14 =122, DQ15 =118
3088 23:05:35.119811
3089 23:05:35.119875
3090 23:05:35.126714 [DQSOSCAuto] RK1, (LSB)MR18= 0x12f3, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 403 ps
3091 23:05:35.129853 CH0 RK1: MR19=403, MR18=12F3
3092 23:05:35.136526 CH0_RK1: MR19=0x403, MR18=0x12F3, DQSOSC=403, MR23=63, INC=40, DEC=26
3093 23:05:35.140043 [RxdqsGatingPostProcess] freq 1200
3094 23:05:35.146400 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3095 23:05:35.149884 best DQS0 dly(2T, 0.5T) = (0, 11)
3096 23:05:35.153083 best DQS1 dly(2T, 0.5T) = (0, 11)
3097 23:05:35.153165 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3098 23:05:35.156457 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3099 23:05:35.160101 best DQS0 dly(2T, 0.5T) = (0, 11)
3100 23:05:35.163128 best DQS1 dly(2T, 0.5T) = (0, 11)
3101 23:05:35.166746 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3102 23:05:35.169858 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3103 23:05:35.173539 Pre-setting of DQS Precalculation
3104 23:05:35.179831 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3105 23:05:35.179914 ==
3106 23:05:35.183051 Dram Type= 6, Freq= 0, CH_1, rank 0
3107 23:05:35.186414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3108 23:05:35.186497 ==
3109 23:05:35.193328 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3110 23:05:35.196375 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3111 23:05:35.206208 [CA 0] Center 37 (7~68) winsize 62
3112 23:05:35.209562 [CA 1] Center 37 (7~68) winsize 62
3113 23:05:35.212828 [CA 2] Center 35 (5~65) winsize 61
3114 23:05:35.216002 [CA 3] Center 34 (4~65) winsize 62
3115 23:05:35.219862 [CA 4] Center 34 (4~64) winsize 61
3116 23:05:35.223022 [CA 5] Center 33 (3~63) winsize 61
3117 23:05:35.223103
3118 23:05:35.226329 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3119 23:05:35.226410
3120 23:05:35.229410 [CATrainingPosCal] consider 1 rank data
3121 23:05:35.232989 u2DelayCellTimex100 = 270/100 ps
3122 23:05:35.236285 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3123 23:05:35.240343 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3124 23:05:35.246321 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3125 23:05:35.249897 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3126 23:05:35.252943 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3127 23:05:35.256169 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3128 23:05:35.256308
3129 23:05:35.259413 CA PerBit enable=1, Macro0, CA PI delay=33
3130 23:05:35.259494
3131 23:05:35.263060 [CBTSetCACLKResult] CA Dly = 33
3132 23:05:35.263141 CS Dly: 6 (0~37)
3133 23:05:35.263205 ==
3134 23:05:35.265928 Dram Type= 6, Freq= 0, CH_1, rank 1
3135 23:05:35.272970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3136 23:05:35.273053 ==
3137 23:05:35.276507 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3138 23:05:35.282861 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3139 23:05:35.291709 [CA 0] Center 37 (7~68) winsize 62
3140 23:05:35.295182 [CA 1] Center 37 (7~68) winsize 62
3141 23:05:35.298325 [CA 2] Center 35 (5~65) winsize 61
3142 23:05:35.301621 [CA 3] Center 34 (4~65) winsize 62
3143 23:05:35.305322 [CA 4] Center 34 (4~65) winsize 62
3144 23:05:35.308446 [CA 5] Center 34 (4~64) winsize 61
3145 23:05:35.308552
3146 23:05:35.311667 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3147 23:05:35.311746
3148 23:05:35.314950 [CATrainingPosCal] consider 2 rank data
3149 23:05:35.318859 u2DelayCellTimex100 = 270/100 ps
3150 23:05:35.322095 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3151 23:05:35.325363 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3152 23:05:35.331708 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3153 23:05:35.335454 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3154 23:05:35.338581 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3155 23:05:35.341935 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3156 23:05:35.342016
3157 23:05:35.345154 CA PerBit enable=1, Macro0, CA PI delay=33
3158 23:05:35.345235
3159 23:05:35.348768 [CBTSetCACLKResult] CA Dly = 33
3160 23:05:35.348848 CS Dly: 8 (0~41)
3161 23:05:35.348911
3162 23:05:35.352042 ----->DramcWriteLeveling(PI) begin...
3163 23:05:35.352124 ==
3164 23:05:35.355159 Dram Type= 6, Freq= 0, CH_1, rank 0
3165 23:05:35.362106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3166 23:05:35.362191 ==
3167 23:05:35.365318 Write leveling (Byte 0): 26 => 26
3168 23:05:35.369299 Write leveling (Byte 1): 28 => 28
3169 23:05:35.369379 DramcWriteLeveling(PI) end<-----
3170 23:05:35.369476
3171 23:05:35.372502 ==
3172 23:05:35.375738 Dram Type= 6, Freq= 0, CH_1, rank 0
3173 23:05:35.378691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3174 23:05:35.378782 ==
3175 23:05:35.382170 [Gating] SW mode calibration
3176 23:05:35.389030 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3177 23:05:35.392116 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3178 23:05:35.398534 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3179 23:05:35.402105 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3180 23:05:35.405474 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3181 23:05:35.412681 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3182 23:05:35.415723 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3183 23:05:35.418945 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3184 23:05:35.425853 0 15 24 | B1->B0 | 3232 2828 | 1 0 | (1 0) (0 0)
3185 23:05:35.428994 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
3186 23:05:35.432115 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3187 23:05:35.435932 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3188 23:05:35.442776 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3189 23:05:35.445480 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3190 23:05:35.449332 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3191 23:05:35.456159 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3192 23:05:35.459332 1 0 24 | B1->B0 | 2f2f 4040 | 0 0 | (0 0) (0 0)
3193 23:05:35.462574 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3194 23:05:35.469184 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3195 23:05:35.472526 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3196 23:05:35.475852 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3197 23:05:35.482204 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3198 23:05:35.485975 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3199 23:05:35.489028 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3200 23:05:35.495562 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3201 23:05:35.499237 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3202 23:05:35.502383 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3203 23:05:35.508894 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3204 23:05:35.512574 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3205 23:05:35.516139 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3206 23:05:35.519116 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3207 23:05:35.525474 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3208 23:05:35.529080 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3209 23:05:35.532393 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 23:05:35.538847 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 23:05:35.542233 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 23:05:35.545797 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 23:05:35.552095 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 23:05:35.555511 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 23:05:35.559061 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 23:05:35.565410 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3217 23:05:35.569309 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3218 23:05:35.572317 Total UI for P1: 0, mck2ui 16
3219 23:05:35.575602 best dqsien dly found for B1: ( 1, 3, 24)
3220 23:05:35.578829 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3221 23:05:35.582610 Total UI for P1: 0, mck2ui 16
3222 23:05:35.585993 best dqsien dly found for B0: ( 1, 3, 26)
3223 23:05:35.588980 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3224 23:05:35.592029 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3225 23:05:35.592110
3226 23:05:35.598735 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3227 23:05:35.602316 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3228 23:05:35.602397 [Gating] SW calibration Done
3229 23:05:35.605982 ==
3230 23:05:35.608792 Dram Type= 6, Freq= 0, CH_1, rank 0
3231 23:05:35.612216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3232 23:05:35.612292 ==
3233 23:05:35.612356 RX Vref Scan: 0
3234 23:05:35.612416
3235 23:05:35.616016 RX Vref 0 -> 0, step: 1
3236 23:05:35.616086
3237 23:05:35.619117 RX Delay -40 -> 252, step: 8
3238 23:05:35.622023 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3239 23:05:35.625497 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3240 23:05:35.628885 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3241 23:05:35.635897 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3242 23:05:35.638856 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3243 23:05:35.642376 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3244 23:05:35.645839 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3245 23:05:35.648694 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3246 23:05:35.655407 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3247 23:05:35.658705 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3248 23:05:35.662384 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3249 23:05:35.665651 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3250 23:05:35.668720 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3251 23:05:35.675479 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3252 23:05:35.678710 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3253 23:05:35.682893 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3254 23:05:35.682974 ==
3255 23:05:35.685986 Dram Type= 6, Freq= 0, CH_1, rank 0
3256 23:05:35.689235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3257 23:05:35.689316 ==
3258 23:05:35.692371 DQS Delay:
3259 23:05:35.692478 DQS0 = 0, DQS1 = 0
3260 23:05:35.695414 DQM Delay:
3261 23:05:35.695494 DQM0 = 119, DQM1 = 116
3262 23:05:35.695558 DQ Delay:
3263 23:05:35.702400 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3264 23:05:35.705478 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =119
3265 23:05:35.708791 DQ8 =103, DQ9 =103, DQ10 =115, DQ11 =111
3266 23:05:35.711973 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3267 23:05:35.712054
3268 23:05:35.712118
3269 23:05:35.712177 ==
3270 23:05:35.715699 Dram Type= 6, Freq= 0, CH_1, rank 0
3271 23:05:35.718978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3272 23:05:35.719060 ==
3273 23:05:35.719124
3274 23:05:35.719182
3275 23:05:35.722207 TX Vref Scan disable
3276 23:05:35.725325 == TX Byte 0 ==
3277 23:05:35.729041 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3278 23:05:35.732053 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3279 23:05:35.735417 == TX Byte 1 ==
3280 23:05:35.738738 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3281 23:05:35.741755 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3282 23:05:35.741837 ==
3283 23:05:35.745261 Dram Type= 6, Freq= 0, CH_1, rank 0
3284 23:05:35.748900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3285 23:05:35.751752 ==
3286 23:05:35.762295 TX Vref=22, minBit 9, minWin=24, winSum=413
3287 23:05:35.765457 TX Vref=24, minBit 10, minWin=25, winSum=421
3288 23:05:35.768834 TX Vref=26, minBit 9, minWin=25, winSum=421
3289 23:05:35.772533 TX Vref=28, minBit 2, minWin=26, winSum=429
3290 23:05:35.776085 TX Vref=30, minBit 2, minWin=26, winSum=432
3291 23:05:35.782209 TX Vref=32, minBit 10, minWin=25, winSum=431
3292 23:05:35.785418 [TxChooseVref] Worse bit 2, Min win 26, Win sum 432, Final Vref 30
3293 23:05:35.785500
3294 23:05:35.788634 Final TX Range 1 Vref 30
3295 23:05:35.788715
3296 23:05:35.788780 ==
3297 23:05:35.792450 Dram Type= 6, Freq= 0, CH_1, rank 0
3298 23:05:35.795868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3299 23:05:35.795950 ==
3300 23:05:35.796013
3301 23:05:35.798848
3302 23:05:35.798940 TX Vref Scan disable
3303 23:05:35.802236 == TX Byte 0 ==
3304 23:05:35.806121 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3305 23:05:35.809095 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3306 23:05:35.812159 == TX Byte 1 ==
3307 23:05:35.815377 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3308 23:05:35.819162 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3309 23:05:35.819244
3310 23:05:35.822014 [DATLAT]
3311 23:05:35.822095 Freq=1200, CH1 RK0
3312 23:05:35.822159
3313 23:05:35.825248 DATLAT Default: 0xd
3314 23:05:35.825329 0, 0xFFFF, sum = 0
3315 23:05:35.829080 1, 0xFFFF, sum = 0
3316 23:05:35.829162 2, 0xFFFF, sum = 0
3317 23:05:35.832392 3, 0xFFFF, sum = 0
3318 23:05:35.832474 4, 0xFFFF, sum = 0
3319 23:05:35.835605 5, 0xFFFF, sum = 0
3320 23:05:35.835687 6, 0xFFFF, sum = 0
3321 23:05:35.838909 7, 0xFFFF, sum = 0
3322 23:05:35.838992 8, 0xFFFF, sum = 0
3323 23:05:35.842520 9, 0xFFFF, sum = 0
3324 23:05:35.845397 10, 0xFFFF, sum = 0
3325 23:05:35.845479 11, 0xFFFF, sum = 0
3326 23:05:35.848914 12, 0x0, sum = 1
3327 23:05:35.848996 13, 0x0, sum = 2
3328 23:05:35.849077 14, 0x0, sum = 3
3329 23:05:35.852054 15, 0x0, sum = 4
3330 23:05:35.852135 best_step = 13
3331 23:05:35.852199
3332 23:05:35.855871 ==
3333 23:05:35.855953 Dram Type= 6, Freq= 0, CH_1, rank 0
3334 23:05:35.862435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3335 23:05:35.862516 ==
3336 23:05:35.862582 RX Vref Scan: 1
3337 23:05:35.862642
3338 23:05:35.865938 Set Vref Range= 32 -> 127
3339 23:05:35.866019
3340 23:05:35.868913 RX Vref 32 -> 127, step: 1
3341 23:05:35.868994
3342 23:05:35.872061 RX Delay -5 -> 252, step: 4
3343 23:05:35.872142
3344 23:05:35.875949 Set Vref, RX VrefLevel [Byte0]: 32
3345 23:05:35.879128 [Byte1]: 32
3346 23:05:35.879209
3347 23:05:35.882276 Set Vref, RX VrefLevel [Byte0]: 33
3348 23:05:35.885126 [Byte1]: 33
3349 23:05:35.885231
3350 23:05:35.889034 Set Vref, RX VrefLevel [Byte0]: 34
3351 23:05:35.892263 [Byte1]: 34
3352 23:05:35.896322
3353 23:05:35.896401 Set Vref, RX VrefLevel [Byte0]: 35
3354 23:05:35.899454 [Byte1]: 35
3355 23:05:35.904025
3356 23:05:35.904105 Set Vref, RX VrefLevel [Byte0]: 36
3357 23:05:35.907269 [Byte1]: 36
3358 23:05:35.911640
3359 23:05:35.911719 Set Vref, RX VrefLevel [Byte0]: 37
3360 23:05:35.914944 [Byte1]: 37
3361 23:05:35.919860
3362 23:05:35.919940 Set Vref, RX VrefLevel [Byte0]: 38
3363 23:05:35.923085 [Byte1]: 38
3364 23:05:35.927367
3365 23:05:35.927449 Set Vref, RX VrefLevel [Byte0]: 39
3366 23:05:35.930613 [Byte1]: 39
3367 23:05:35.935119
3368 23:05:35.935199 Set Vref, RX VrefLevel [Byte0]: 40
3369 23:05:35.938377 [Byte1]: 40
3370 23:05:35.943289
3371 23:05:35.943369 Set Vref, RX VrefLevel [Byte0]: 41
3372 23:05:35.946573 [Byte1]: 41
3373 23:05:35.950936
3374 23:05:35.951015 Set Vref, RX VrefLevel [Byte0]: 42
3375 23:05:35.954493 [Byte1]: 42
3376 23:05:35.958723
3377 23:05:35.958803 Set Vref, RX VrefLevel [Byte0]: 43
3378 23:05:35.962621 [Byte1]: 43
3379 23:05:35.966962
3380 23:05:35.967041 Set Vref, RX VrefLevel [Byte0]: 44
3381 23:05:35.970540 [Byte1]: 44
3382 23:05:35.974641
3383 23:05:35.974719 Set Vref, RX VrefLevel [Byte0]: 45
3384 23:05:35.977873 [Byte1]: 45
3385 23:05:35.982368
3386 23:05:35.982447 Set Vref, RX VrefLevel [Byte0]: 46
3387 23:05:35.985510 [Byte1]: 46
3388 23:05:35.990606
3389 23:05:35.990685 Set Vref, RX VrefLevel [Byte0]: 47
3390 23:05:35.993788 [Byte1]: 47
3391 23:05:35.998229
3392 23:05:35.998312 Set Vref, RX VrefLevel [Byte0]: 48
3393 23:05:36.001260 [Byte1]: 48
3394 23:05:36.006321
3395 23:05:36.006400 Set Vref, RX VrefLevel [Byte0]: 49
3396 23:05:36.009324 [Byte1]: 49
3397 23:05:36.013780
3398 23:05:36.013858 Set Vref, RX VrefLevel [Byte0]: 50
3399 23:05:36.017615 [Byte1]: 50
3400 23:05:36.021608
3401 23:05:36.021721 Set Vref, RX VrefLevel [Byte0]: 51
3402 23:05:36.025332 [Byte1]: 51
3403 23:05:36.029724
3404 23:05:36.029806 Set Vref, RX VrefLevel [Byte0]: 52
3405 23:05:36.032672 [Byte1]: 52
3406 23:05:36.037616
3407 23:05:36.037716 Set Vref, RX VrefLevel [Byte0]: 53
3408 23:05:36.040371 [Byte1]: 53
3409 23:05:36.045293
3410 23:05:36.045403 Set Vref, RX VrefLevel [Byte0]: 54
3411 23:05:36.048707 [Byte1]: 54
3412 23:05:36.053354
3413 23:05:36.053460 Set Vref, RX VrefLevel [Byte0]: 55
3414 23:05:36.056343 [Byte1]: 55
3415 23:05:36.061247
3416 23:05:36.061354 Set Vref, RX VrefLevel [Byte0]: 56
3417 23:05:36.064370 [Byte1]: 56
3418 23:05:36.068842
3419 23:05:36.068948 Set Vref, RX VrefLevel [Byte0]: 57
3420 23:05:36.072075 [Byte1]: 57
3421 23:05:36.076768
3422 23:05:36.076851 Set Vref, RX VrefLevel [Byte0]: 58
3423 23:05:36.080101 [Byte1]: 58
3424 23:05:36.084342
3425 23:05:36.084422 Set Vref, RX VrefLevel [Byte0]: 59
3426 23:05:36.087566 [Byte1]: 59
3427 23:05:36.092625
3428 23:05:36.092704 Set Vref, RX VrefLevel [Byte0]: 60
3429 23:05:36.095615 [Byte1]: 60
3430 23:05:36.100059
3431 23:05:36.100139 Set Vref, RX VrefLevel [Byte0]: 61
3432 23:05:36.103317 [Byte1]: 61
3433 23:05:36.108377
3434 23:05:36.108457 Set Vref, RX VrefLevel [Byte0]: 62
3435 23:05:36.111026 [Byte1]: 62
3436 23:05:36.115961
3437 23:05:36.116041 Set Vref, RX VrefLevel [Byte0]: 63
3438 23:05:36.119505 [Byte1]: 63
3439 23:05:36.123666
3440 23:05:36.123747 Set Vref, RX VrefLevel [Byte0]: 64
3441 23:05:36.127198 [Byte1]: 64
3442 23:05:36.131935
3443 23:05:36.132015 Set Vref, RX VrefLevel [Byte0]: 65
3444 23:05:36.135023 [Byte1]: 65
3445 23:05:36.139414
3446 23:05:36.139497 Set Vref, RX VrefLevel [Byte0]: 66
3447 23:05:36.142924 [Byte1]: 66
3448 23:05:36.147039
3449 23:05:36.147120 Set Vref, RX VrefLevel [Byte0]: 67
3450 23:05:36.150631 [Byte1]: 67
3451 23:05:36.154868
3452 23:05:36.154949 Set Vref, RX VrefLevel [Byte0]: 68
3453 23:05:36.158126 [Byte1]: 68
3454 23:05:36.163052
3455 23:05:36.163136 Final RX Vref Byte 0 = 57 to rank0
3456 23:05:36.166274 Final RX Vref Byte 1 = 53 to rank0
3457 23:05:36.169424 Final RX Vref Byte 0 = 57 to rank1
3458 23:05:36.173045 Final RX Vref Byte 1 = 53 to rank1==
3459 23:05:36.176256 Dram Type= 6, Freq= 0, CH_1, rank 0
3460 23:05:36.183242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3461 23:05:36.183324 ==
3462 23:05:36.183389 DQS Delay:
3463 23:05:36.183449 DQS0 = 0, DQS1 = 0
3464 23:05:36.186109 DQM Delay:
3465 23:05:36.186190 DQM0 = 120, DQM1 = 117
3466 23:05:36.189518 DQ Delay:
3467 23:05:36.192854 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =118
3468 23:05:36.196761 DQ4 =120, DQ5 =128, DQ6 =128, DQ7 =120
3469 23:05:36.199803 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =112
3470 23:05:36.202781 DQ12 =122, DQ13 =124, DQ14 =124, DQ15 =126
3471 23:05:36.202861
3472 23:05:36.202926
3473 23:05:36.212874 [DQSOSCAuto] RK0, (LSB)MR18= 0x214, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 409 ps
3474 23:05:36.212956 CH1 RK0: MR19=404, MR18=214
3475 23:05:36.219992 CH1_RK0: MR19=0x404, MR18=0x214, DQSOSC=402, MR23=63, INC=40, DEC=27
3476 23:05:36.220074
3477 23:05:36.223155 ----->DramcWriteLeveling(PI) begin...
3478 23:05:36.223238 ==
3479 23:05:36.226605 Dram Type= 6, Freq= 0, CH_1, rank 1
3480 23:05:36.229553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3481 23:05:36.229713 ==
3482 23:05:36.232822 Write leveling (Byte 0): 26 => 26
3483 23:05:36.236027 Write leveling (Byte 1): 28 => 28
3484 23:05:36.239741 DramcWriteLeveling(PI) end<-----
3485 23:05:36.239823
3486 23:05:36.239896 ==
3487 23:05:36.243080 Dram Type= 6, Freq= 0, CH_1, rank 1
3488 23:05:36.249826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3489 23:05:36.249937 ==
3490 23:05:36.250044 [Gating] SW mode calibration
3491 23:05:36.259607 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3492 23:05:36.263057 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3493 23:05:36.266480 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3494 23:05:36.272939 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3495 23:05:36.276188 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3496 23:05:36.279802 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3497 23:05:36.286336 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3498 23:05:36.289771 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3499 23:05:36.293507 0 15 24 | B1->B0 | 2929 3434 | 0 1 | (1 0) (1 1)
3500 23:05:36.300097 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
3501 23:05:36.303361 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3502 23:05:36.306701 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3503 23:05:36.313407 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3504 23:05:36.316419 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3505 23:05:36.319650 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3506 23:05:36.323471 1 0 20 | B1->B0 | 2626 2323 | 1 0 | (0 0) (0 0)
3507 23:05:36.330010 1 0 24 | B1->B0 | 4343 2e2e | 0 0 | (0 0) (0 0)
3508 23:05:36.333281 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3509 23:05:36.336443 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3510 23:05:36.343083 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3511 23:05:36.346198 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3512 23:05:36.350046 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3513 23:05:36.356490 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3514 23:05:36.359477 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3515 23:05:36.363446 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3516 23:05:36.369821 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3517 23:05:36.373308 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3518 23:05:36.376691 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3519 23:05:36.383485 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3520 23:05:36.386682 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3521 23:05:36.389507 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3522 23:05:36.396267 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3523 23:05:36.399883 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3524 23:05:36.402962 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3525 23:05:36.409813 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3526 23:05:36.413023 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3527 23:05:36.416589 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3528 23:05:36.419957 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3529 23:05:36.426310 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3530 23:05:36.429526 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3531 23:05:36.433517 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3532 23:05:36.439962 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3533 23:05:36.442818 Total UI for P1: 0, mck2ui 16
3534 23:05:36.446465 best dqsien dly found for B1: ( 1, 3, 22)
3535 23:05:36.449625 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3536 23:05:36.453429 Total UI for P1: 0, mck2ui 16
3537 23:05:36.456005 best dqsien dly found for B0: ( 1, 3, 26)
3538 23:05:36.459963 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3539 23:05:36.463215 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3540 23:05:36.463319
3541 23:05:36.466475 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3542 23:05:36.469629 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3543 23:05:36.473309 [Gating] SW calibration Done
3544 23:05:36.473391 ==
3545 23:05:36.476648 Dram Type= 6, Freq= 0, CH_1, rank 1
3546 23:05:36.483090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3547 23:05:36.483175 ==
3548 23:05:36.483246 RX Vref Scan: 0
3549 23:05:36.483310
3550 23:05:36.486227 RX Vref 0 -> 0, step: 1
3551 23:05:36.486309
3552 23:05:36.489294 RX Delay -40 -> 252, step: 8
3553 23:05:36.493125 iDelay=208, Bit 0, Center 123 (56 ~ 191) 136
3554 23:05:36.495974 iDelay=208, Bit 1, Center 115 (48 ~ 183) 136
3555 23:05:36.499267 iDelay=208, Bit 2, Center 107 (40 ~ 175) 136
3556 23:05:36.502689 iDelay=208, Bit 3, Center 119 (56 ~ 183) 128
3557 23:05:36.509541 iDelay=208, Bit 4, Center 115 (48 ~ 183) 136
3558 23:05:36.512772 iDelay=208, Bit 5, Center 135 (64 ~ 207) 144
3559 23:05:36.516367 iDelay=208, Bit 6, Center 131 (64 ~ 199) 136
3560 23:05:36.519925 iDelay=208, Bit 7, Center 119 (48 ~ 191) 144
3561 23:05:36.523089 iDelay=208, Bit 8, Center 103 (40 ~ 167) 128
3562 23:05:36.529459 iDelay=208, Bit 9, Center 107 (40 ~ 175) 136
3563 23:05:36.532738 iDelay=208, Bit 10, Center 119 (48 ~ 191) 144
3564 23:05:36.536021 iDelay=208, Bit 11, Center 115 (48 ~ 183) 136
3565 23:05:36.539266 iDelay=208, Bit 12, Center 127 (56 ~ 199) 144
3566 23:05:36.542495 iDelay=208, Bit 13, Center 127 (64 ~ 191) 128
3567 23:05:36.549538 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
3568 23:05:36.552624 iDelay=208, Bit 15, Center 123 (56 ~ 191) 136
3569 23:05:36.552701 ==
3570 23:05:36.555763 Dram Type= 6, Freq= 0, CH_1, rank 1
3571 23:05:36.559061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3572 23:05:36.559141 ==
3573 23:05:36.562850 DQS Delay:
3574 23:05:36.562929 DQS0 = 0, DQS1 = 0
3575 23:05:36.562994 DQM Delay:
3576 23:05:36.566261 DQM0 = 120, DQM1 = 118
3577 23:05:36.566337 DQ Delay:
3578 23:05:36.569416 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3579 23:05:36.572674 DQ4 =115, DQ5 =135, DQ6 =131, DQ7 =119
3580 23:05:36.579696 DQ8 =103, DQ9 =107, DQ10 =119, DQ11 =115
3581 23:05:36.582960 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3582 23:05:36.583037
3583 23:05:36.583104
3584 23:05:36.583166 ==
3585 23:05:36.586172 Dram Type= 6, Freq= 0, CH_1, rank 1
3586 23:05:36.589026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3587 23:05:36.589106 ==
3588 23:05:36.589172
3589 23:05:36.589238
3590 23:05:36.592402 TX Vref Scan disable
3591 23:05:36.592481 == TX Byte 0 ==
3592 23:05:36.599275 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3593 23:05:36.602487 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3594 23:05:36.602571 == TX Byte 1 ==
3595 23:05:36.609239 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3596 23:05:36.612173 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3597 23:05:36.612254 ==
3598 23:05:36.616251 Dram Type= 6, Freq= 0, CH_1, rank 1
3599 23:05:36.619301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3600 23:05:36.619381 ==
3601 23:05:36.632192 TX Vref=22, minBit 7, minWin=25, winSum=418
3602 23:05:36.635405 TX Vref=24, minBit 1, minWin=26, winSum=424
3603 23:05:36.638615 TX Vref=26, minBit 1, minWin=26, winSum=428
3604 23:05:36.641981 TX Vref=28, minBit 9, minWin=26, winSum=435
3605 23:05:36.645488 TX Vref=30, minBit 9, minWin=26, winSum=436
3606 23:05:36.648434 TX Vref=32, minBit 9, minWin=26, winSum=432
3607 23:05:36.655636 [TxChooseVref] Worse bit 9, Min win 26, Win sum 436, Final Vref 30
3608 23:05:36.655726
3609 23:05:36.658576 Final TX Range 1 Vref 30
3610 23:05:36.658656
3611 23:05:36.658728 ==
3612 23:05:36.661782 Dram Type= 6, Freq= 0, CH_1, rank 1
3613 23:05:36.665729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3614 23:05:36.665807 ==
3615 23:05:36.665878
3616 23:05:36.668991
3617 23:05:36.669098 TX Vref Scan disable
3618 23:05:36.671664 == TX Byte 0 ==
3619 23:05:36.675544 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3620 23:05:36.678949 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3621 23:05:36.682004 == TX Byte 1 ==
3622 23:05:36.685330 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3623 23:05:36.688625 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3624 23:05:36.688708
3625 23:05:36.692150 [DATLAT]
3626 23:05:36.692236 Freq=1200, CH1 RK1
3627 23:05:36.692307
3628 23:05:36.695029 DATLAT Default: 0xd
3629 23:05:36.695111 0, 0xFFFF, sum = 0
3630 23:05:36.698467 1, 0xFFFF, sum = 0
3631 23:05:36.698551 2, 0xFFFF, sum = 0
3632 23:05:36.701753 3, 0xFFFF, sum = 0
3633 23:05:36.701829 4, 0xFFFF, sum = 0
3634 23:05:36.705032 5, 0xFFFF, sum = 0
3635 23:05:36.708244 6, 0xFFFF, sum = 0
3636 23:05:36.708327 7, 0xFFFF, sum = 0
3637 23:05:36.712260 8, 0xFFFF, sum = 0
3638 23:05:36.712342 9, 0xFFFF, sum = 0
3639 23:05:36.715050 10, 0xFFFF, sum = 0
3640 23:05:36.715133 11, 0xFFFF, sum = 0
3641 23:05:36.718575 12, 0x0, sum = 1
3642 23:05:36.718658 13, 0x0, sum = 2
3643 23:05:36.721794 14, 0x0, sum = 3
3644 23:05:36.721903 15, 0x0, sum = 4
3645 23:05:36.721997 best_step = 13
3646 23:05:36.722085
3647 23:05:36.725278 ==
3648 23:05:36.728581 Dram Type= 6, Freq= 0, CH_1, rank 1
3649 23:05:36.731666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3650 23:05:36.731756 ==
3651 23:05:36.731825 RX Vref Scan: 0
3652 23:05:36.731894
3653 23:05:36.734854 RX Vref 0 -> 0, step: 1
3654 23:05:36.734934
3655 23:05:36.738552 RX Delay -5 -> 252, step: 4
3656 23:05:36.741537 iDelay=195, Bit 0, Center 124 (59 ~ 190) 132
3657 23:05:36.747924 iDelay=195, Bit 1, Center 118 (55 ~ 182) 128
3658 23:05:36.751774 iDelay=195, Bit 2, Center 114 (55 ~ 174) 120
3659 23:05:36.754663 iDelay=195, Bit 3, Center 116 (59 ~ 174) 116
3660 23:05:36.758091 iDelay=195, Bit 4, Center 118 (59 ~ 178) 120
3661 23:05:36.761338 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3662 23:05:36.768185 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3663 23:05:36.771404 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3664 23:05:36.774732 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3665 23:05:36.777889 iDelay=195, Bit 9, Center 108 (47 ~ 170) 124
3666 23:05:36.781153 iDelay=195, Bit 10, Center 120 (59 ~ 182) 124
3667 23:05:36.787979 iDelay=195, Bit 11, Center 112 (51 ~ 174) 124
3668 23:05:36.791310 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3669 23:05:36.794630 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3670 23:05:36.798405 iDelay=195, Bit 14, Center 122 (63 ~ 182) 120
3671 23:05:36.801248 iDelay=195, Bit 15, Center 128 (67 ~ 190) 124
3672 23:05:36.804954 ==
3673 23:05:36.808179 Dram Type= 6, Freq= 0, CH_1, rank 1
3674 23:05:36.811543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3675 23:05:36.811625 ==
3676 23:05:36.811690 DQS Delay:
3677 23:05:36.814877 DQS0 = 0, DQS1 = 0
3678 23:05:36.814958 DQM Delay:
3679 23:05:36.818014 DQM0 = 121, DQM1 = 118
3680 23:05:36.818098 DQ Delay:
3681 23:05:36.821537 DQ0 =124, DQ1 =118, DQ2 =114, DQ3 =116
3682 23:05:36.824972 DQ4 =118, DQ5 =130, DQ6 =130, DQ7 =120
3683 23:05:36.828077 DQ8 =106, DQ9 =108, DQ10 =120, DQ11 =112
3684 23:05:36.831263 DQ12 =126, DQ13 =124, DQ14 =122, DQ15 =128
3685 23:05:36.831344
3686 23:05:36.831407
3687 23:05:36.841432 [DQSOSCAuto] RK1, (LSB)MR18= 0x14f2, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 402 ps
3688 23:05:36.841543 CH1 RK1: MR19=403, MR18=14F2
3689 23:05:36.848125 CH1_RK1: MR19=0x403, MR18=0x14F2, DQSOSC=402, MR23=63, INC=40, DEC=27
3690 23:05:36.851541 [RxdqsGatingPostProcess] freq 1200
3691 23:05:36.858337 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3692 23:05:36.861330 best DQS0 dly(2T, 0.5T) = (0, 11)
3693 23:05:36.864723 best DQS1 dly(2T, 0.5T) = (0, 11)
3694 23:05:36.868211 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3695 23:05:36.871553 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3696 23:05:36.874836 best DQS0 dly(2T, 0.5T) = (0, 11)
3697 23:05:36.878295 best DQS1 dly(2T, 0.5T) = (0, 11)
3698 23:05:36.881538 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3699 23:05:36.881642 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3700 23:05:36.884433 Pre-setting of DQS Precalculation
3701 23:05:36.891016 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3702 23:05:36.898032 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3703 23:05:36.904252 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3704 23:05:36.904360
3705 23:05:36.904454
3706 23:05:36.907807 [Calibration Summary] 2400 Mbps
3707 23:05:36.911203 CH 0, Rank 0
3708 23:05:36.911307 SW Impedance : PASS
3709 23:05:36.914396 DUTY Scan : NO K
3710 23:05:36.917504 ZQ Calibration : PASS
3711 23:05:36.917646 Jitter Meter : NO K
3712 23:05:36.920714 CBT Training : PASS
3713 23:05:36.923953 Write leveling : PASS
3714 23:05:36.924055 RX DQS gating : PASS
3715 23:05:36.927388 RX DQ/DQS(RDDQC) : PASS
3716 23:05:36.927487 TX DQ/DQS : PASS
3717 23:05:36.930904 RX DATLAT : PASS
3718 23:05:36.934746 RX DQ/DQS(Engine): PASS
3719 23:05:36.934846 TX OE : NO K
3720 23:05:36.937333 All Pass.
3721 23:05:36.937434
3722 23:05:36.937526 CH 0, Rank 1
3723 23:05:36.940815 SW Impedance : PASS
3724 23:05:36.940919 DUTY Scan : NO K
3725 23:05:36.944108 ZQ Calibration : PASS
3726 23:05:36.947226 Jitter Meter : NO K
3727 23:05:36.947326 CBT Training : PASS
3728 23:05:36.950623 Write leveling : PASS
3729 23:05:36.953780 RX DQS gating : PASS
3730 23:05:36.953881 RX DQ/DQS(RDDQC) : PASS
3731 23:05:36.957697 TX DQ/DQS : PASS
3732 23:05:36.960777 RX DATLAT : PASS
3733 23:05:36.960876 RX DQ/DQS(Engine): PASS
3734 23:05:36.963819 TX OE : NO K
3735 23:05:36.963917 All Pass.
3736 23:05:36.964009
3737 23:05:36.967115 CH 1, Rank 0
3738 23:05:36.967219 SW Impedance : PASS
3739 23:05:36.970970 DUTY Scan : NO K
3740 23:05:36.974201 ZQ Calibration : PASS
3741 23:05:36.974301 Jitter Meter : NO K
3742 23:05:36.977450 CBT Training : PASS
3743 23:05:36.980531 Write leveling : PASS
3744 23:05:36.980650 RX DQS gating : PASS
3745 23:05:36.983596 RX DQ/DQS(RDDQC) : PASS
3746 23:05:36.986934 TX DQ/DQS : PASS
3747 23:05:36.987039 RX DATLAT : PASS
3748 23:05:36.990383 RX DQ/DQS(Engine): PASS
3749 23:05:36.990485 TX OE : NO K
3750 23:05:36.993751 All Pass.
3751 23:05:36.993861
3752 23:05:36.993948 CH 1, Rank 1
3753 23:05:36.996960 SW Impedance : PASS
3754 23:05:36.997062 DUTY Scan : NO K
3755 23:05:37.000151 ZQ Calibration : PASS
3756 23:05:37.003660 Jitter Meter : NO K
3757 23:05:37.003766 CBT Training : PASS
3758 23:05:37.006717 Write leveling : PASS
3759 23:05:37.009912 RX DQS gating : PASS
3760 23:05:37.010025 RX DQ/DQS(RDDQC) : PASS
3761 23:05:37.013898 TX DQ/DQS : PASS
3762 23:05:37.016660 RX DATLAT : PASS
3763 23:05:37.016735 RX DQ/DQS(Engine): PASS
3764 23:05:37.019732 TX OE : NO K
3765 23:05:37.019813 All Pass.
3766 23:05:37.019877
3767 23:05:37.023207 DramC Write-DBI off
3768 23:05:37.026443 PER_BANK_REFRESH: Hybrid Mode
3769 23:05:37.026524 TX_TRACKING: ON
3770 23:05:37.036898 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3771 23:05:37.039812 [FAST_K] Save calibration result to emmc
3772 23:05:37.043467 dramc_set_vcore_voltage set vcore to 650000
3773 23:05:37.046563 Read voltage for 600, 5
3774 23:05:37.046644 Vio18 = 0
3775 23:05:37.046709 Vcore = 650000
3776 23:05:37.049899 Vdram = 0
3777 23:05:37.049981 Vddq = 0
3778 23:05:37.050045 Vmddr = 0
3779 23:05:37.056570 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3780 23:05:37.059810 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3781 23:05:37.063087 MEM_TYPE=3, freq_sel=19
3782 23:05:37.066302 sv_algorithm_assistance_LP4_1600
3783 23:05:37.070015 ============ PULL DRAM RESETB DOWN ============
3784 23:05:37.076680 ========== PULL DRAM RESETB DOWN end =========
3785 23:05:37.080000 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3786 23:05:37.083250 ===================================
3787 23:05:37.086248 LPDDR4 DRAM CONFIGURATION
3788 23:05:37.089513 ===================================
3789 23:05:37.089668 EX_ROW_EN[0] = 0x0
3790 23:05:37.093375 EX_ROW_EN[1] = 0x0
3791 23:05:37.093479 LP4Y_EN = 0x0
3792 23:05:37.096599 WORK_FSP = 0x0
3793 23:05:37.096708 WL = 0x2
3794 23:05:37.099928 RL = 0x2
3795 23:05:37.100031 BL = 0x2
3796 23:05:37.103203 RPST = 0x0
3797 23:05:37.103311 RD_PRE = 0x0
3798 23:05:37.106326 WR_PRE = 0x1
3799 23:05:37.106438 WR_PST = 0x0
3800 23:05:37.109330 DBI_WR = 0x0
3801 23:05:37.112652 DBI_RD = 0x0
3802 23:05:37.112752 OTF = 0x1
3803 23:05:37.116127 ===================================
3804 23:05:37.119467 ===================================
3805 23:05:37.119569 ANA top config
3806 23:05:37.123186 ===================================
3807 23:05:37.126374 DLL_ASYNC_EN = 0
3808 23:05:37.129696 ALL_SLAVE_EN = 1
3809 23:05:37.132784 NEW_RANK_MODE = 1
3810 23:05:37.132892 DLL_IDLE_MODE = 1
3811 23:05:37.135966 LP45_APHY_COMB_EN = 1
3812 23:05:37.139648 TX_ODT_DIS = 1
3813 23:05:37.142873 NEW_8X_MODE = 1
3814 23:05:37.146642 ===================================
3815 23:05:37.149910 ===================================
3816 23:05:37.152980 data_rate = 1200
3817 23:05:37.156139 CKR = 1
3818 23:05:37.156240 DQ_P2S_RATIO = 8
3819 23:05:37.159732 ===================================
3820 23:05:37.162702 CA_P2S_RATIO = 8
3821 23:05:37.166314 DQ_CA_OPEN = 0
3822 23:05:37.169406 DQ_SEMI_OPEN = 0
3823 23:05:37.172692 CA_SEMI_OPEN = 0
3824 23:05:37.172803 CA_FULL_RATE = 0
3825 23:05:37.175814 DQ_CKDIV4_EN = 1
3826 23:05:37.179460 CA_CKDIV4_EN = 1
3827 23:05:37.182742 CA_PREDIV_EN = 0
3828 23:05:37.185961 PH8_DLY = 0
3829 23:05:37.189611 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3830 23:05:37.189726 DQ_AAMCK_DIV = 4
3831 23:05:37.192575 CA_AAMCK_DIV = 4
3832 23:05:37.195689 CA_ADMCK_DIV = 4
3833 23:05:37.199709 DQ_TRACK_CA_EN = 0
3834 23:05:37.202853 CA_PICK = 600
3835 23:05:37.206256 CA_MCKIO = 600
3836 23:05:37.209448 MCKIO_SEMI = 0
3837 23:05:37.209555 PLL_FREQ = 2288
3838 23:05:37.212779 DQ_UI_PI_RATIO = 32
3839 23:05:37.215829 CA_UI_PI_RATIO = 0
3840 23:05:37.219012 ===================================
3841 23:05:37.222344 ===================================
3842 23:05:37.225880 memory_type:LPDDR4
3843 23:05:37.229500 GP_NUM : 10
3844 23:05:37.229640 SRAM_EN : 1
3845 23:05:37.232672 MD32_EN : 0
3846 23:05:37.235757 ===================================
3847 23:05:37.235839 [ANA_INIT] >>>>>>>>>>>>>>
3848 23:05:37.239073 <<<<<< [CONFIGURE PHASE]: ANA_TX
3849 23:05:37.242442 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3850 23:05:37.245956 ===================================
3851 23:05:37.249021 data_rate = 1200,PCW = 0X5800
3852 23:05:37.252315 ===================================
3853 23:05:37.255897 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3854 23:05:37.262608 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3855 23:05:37.265991 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3856 23:05:37.272504 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3857 23:05:37.276062 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3858 23:05:37.278791 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3859 23:05:37.282331 [ANA_INIT] flow start
3860 23:05:37.282412 [ANA_INIT] PLL >>>>>>>>
3861 23:05:37.285361 [ANA_INIT] PLL <<<<<<<<
3862 23:05:37.288541 [ANA_INIT] MIDPI >>>>>>>>
3863 23:05:37.288622 [ANA_INIT] MIDPI <<<<<<<<
3864 23:05:37.292398 [ANA_INIT] DLL >>>>>>>>
3865 23:05:37.295720 [ANA_INIT] flow end
3866 23:05:37.298775 ============ LP4 DIFF to SE enter ============
3867 23:05:37.301848 ============ LP4 DIFF to SE exit ============
3868 23:05:37.306022 [ANA_INIT] <<<<<<<<<<<<<
3869 23:05:37.308539 [Flow] Enable top DCM control >>>>>
3870 23:05:37.312195 [Flow] Enable top DCM control <<<<<
3871 23:05:37.315530 Enable DLL master slave shuffle
3872 23:05:37.318800 ==============================================================
3873 23:05:37.322086 Gating Mode config
3874 23:05:37.329037 ==============================================================
3875 23:05:37.329118 Config description:
3876 23:05:37.338556 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3877 23:05:37.345208 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3878 23:05:37.349109 SELPH_MODE 0: By rank 1: By Phase
3879 23:05:37.355126 ==============================================================
3880 23:05:37.358326 GAT_TRACK_EN = 1
3881 23:05:37.361907 RX_GATING_MODE = 2
3882 23:05:37.365371 RX_GATING_TRACK_MODE = 2
3883 23:05:37.368694 SELPH_MODE = 1
3884 23:05:37.371914 PICG_EARLY_EN = 1
3885 23:05:37.375220 VALID_LAT_VALUE = 1
3886 23:05:37.378523 ==============================================================
3887 23:05:37.381473 Enter into Gating configuration >>>>
3888 23:05:37.385128 Exit from Gating configuration <<<<
3889 23:05:37.388240 Enter into DVFS_PRE_config >>>>>
3890 23:05:37.401246 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3891 23:05:37.401358 Exit from DVFS_PRE_config <<<<<
3892 23:05:37.405044 Enter into PICG configuration >>>>
3893 23:05:37.408084 Exit from PICG configuration <<<<
3894 23:05:37.411332 [RX_INPUT] configuration >>>>>
3895 23:05:37.415305 [RX_INPUT] configuration <<<<<
3896 23:05:37.421839 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3897 23:05:37.425029 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3898 23:05:37.431363 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3899 23:05:37.438328 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3900 23:05:37.445044 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3901 23:05:37.451345 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3902 23:05:37.454715 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3903 23:05:37.458427 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3904 23:05:37.461765 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3905 23:05:37.468165 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3906 23:05:37.471950 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3907 23:05:37.474861 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3908 23:05:37.477916 ===================================
3909 23:05:37.481484 LPDDR4 DRAM CONFIGURATION
3910 23:05:37.484861 ===================================
3911 23:05:37.484992 EX_ROW_EN[0] = 0x0
3912 23:05:37.488139 EX_ROW_EN[1] = 0x0
3913 23:05:37.491291 LP4Y_EN = 0x0
3914 23:05:37.491393 WORK_FSP = 0x0
3915 23:05:37.494559 WL = 0x2
3916 23:05:37.494660 RL = 0x2
3917 23:05:37.498170 BL = 0x2
3918 23:05:37.498269 RPST = 0x0
3919 23:05:37.501102 RD_PRE = 0x0
3920 23:05:37.501200 WR_PRE = 0x1
3921 23:05:37.504516 WR_PST = 0x0
3922 23:05:37.504614 DBI_WR = 0x0
3923 23:05:37.507683 DBI_RD = 0x0
3924 23:05:37.507788 OTF = 0x1
3925 23:05:37.511526 ===================================
3926 23:05:37.514822 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3927 23:05:37.521423 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3928 23:05:37.524820 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3929 23:05:37.528130 ===================================
3930 23:05:37.531197 LPDDR4 DRAM CONFIGURATION
3931 23:05:37.534354 ===================================
3932 23:05:37.534462 EX_ROW_EN[0] = 0x10
3933 23:05:37.537602 EX_ROW_EN[1] = 0x0
3934 23:05:37.540905 LP4Y_EN = 0x0
3935 23:05:37.541010 WORK_FSP = 0x0
3936 23:05:37.544533 WL = 0x2
3937 23:05:37.544639 RL = 0x2
3938 23:05:37.547468 BL = 0x2
3939 23:05:37.547572 RPST = 0x0
3940 23:05:37.550735 RD_PRE = 0x0
3941 23:05:37.550840 WR_PRE = 0x1
3942 23:05:37.554671 WR_PST = 0x0
3943 23:05:37.554757 DBI_WR = 0x0
3944 23:05:37.557832 DBI_RD = 0x0
3945 23:05:37.557912 OTF = 0x1
3946 23:05:37.561067 ===================================
3947 23:05:37.567904 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3948 23:05:37.571673 nWR fixed to 30
3949 23:05:37.575416 [ModeRegInit_LP4] CH0 RK0
3950 23:05:37.575496 [ModeRegInit_LP4] CH0 RK1
3951 23:05:37.578506 [ModeRegInit_LP4] CH1 RK0
3952 23:05:37.581764 [ModeRegInit_LP4] CH1 RK1
3953 23:05:37.581845 match AC timing 17
3954 23:05:37.587985 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3955 23:05:37.591656 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3956 23:05:37.594998 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3957 23:05:37.601881 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3958 23:05:37.604974 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3959 23:05:37.605055 ==
3960 23:05:37.608252 Dram Type= 6, Freq= 0, CH_0, rank 0
3961 23:05:37.611434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3962 23:05:37.611517 ==
3963 23:05:37.618325 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3964 23:05:37.624846 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3965 23:05:37.628451 [CA 0] Center 35 (5~66) winsize 62
3966 23:05:37.631569 [CA 1] Center 36 (5~67) winsize 63
3967 23:05:37.634587 [CA 2] Center 33 (3~64) winsize 62
3968 23:05:37.637834 [CA 3] Center 33 (2~64) winsize 63
3969 23:05:37.641273 [CA 4] Center 33 (2~64) winsize 63
3970 23:05:37.645039 [CA 5] Center 32 (2~63) winsize 62
3971 23:05:37.645146
3972 23:05:37.647976 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3973 23:05:37.648080
3974 23:05:37.651625 [CATrainingPosCal] consider 1 rank data
3975 23:05:37.654741 u2DelayCellTimex100 = 270/100 ps
3976 23:05:37.658095 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3977 23:05:37.661740 CA1 delay=36 (5~67),Diff = 4 PI (38 cell)
3978 23:05:37.665110 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3979 23:05:37.667889 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3980 23:05:37.671403 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3981 23:05:37.674738 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3982 23:05:37.678432
3983 23:05:37.681417 CA PerBit enable=1, Macro0, CA PI delay=32
3984 23:05:37.681522
3985 23:05:37.684603 [CBTSetCACLKResult] CA Dly = 32
3986 23:05:37.684706 CS Dly: 4 (0~35)
3987 23:05:37.684799 ==
3988 23:05:37.687729 Dram Type= 6, Freq= 0, CH_0, rank 1
3989 23:05:37.691162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3990 23:05:37.691267 ==
3991 23:05:37.698137 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3992 23:05:37.704521 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3993 23:05:37.707651 [CA 0] Center 35 (5~66) winsize 62
3994 23:05:37.711531 [CA 1] Center 35 (5~66) winsize 62
3995 23:05:37.714878 [CA 2] Center 34 (3~65) winsize 63
3996 23:05:37.718032 [CA 3] Center 33 (3~64) winsize 62
3997 23:05:37.721311 [CA 4] Center 32 (2~63) winsize 62
3998 23:05:37.724262 [CA 5] Center 32 (1~63) winsize 63
3999 23:05:37.724362
4000 23:05:37.727832 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4001 23:05:37.727933
4002 23:05:37.731210 [CATrainingPosCal] consider 2 rank data
4003 23:05:37.734409 u2DelayCellTimex100 = 270/100 ps
4004 23:05:37.737776 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4005 23:05:37.741137 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
4006 23:05:37.744799 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4007 23:05:37.747983 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4008 23:05:37.750895 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4009 23:05:37.757720 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4010 23:05:37.757832
4011 23:05:37.760962 CA PerBit enable=1, Macro0, CA PI delay=32
4012 23:05:37.761058
4013 23:05:37.764424 [CBTSetCACLKResult] CA Dly = 32
4014 23:05:37.764505 CS Dly: 4 (0~36)
4015 23:05:37.764570
4016 23:05:37.767910 ----->DramcWriteLeveling(PI) begin...
4017 23:05:37.768004 ==
4018 23:05:37.770935 Dram Type= 6, Freq= 0, CH_0, rank 0
4019 23:05:37.774617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4020 23:05:37.778177 ==
4021 23:05:37.778253 Write leveling (Byte 0): 34 => 34
4022 23:05:37.781532 Write leveling (Byte 1): 31 => 31
4023 23:05:37.784493 DramcWriteLeveling(PI) end<-----
4024 23:05:37.784599
4025 23:05:37.784694 ==
4026 23:05:37.787694 Dram Type= 6, Freq= 0, CH_0, rank 0
4027 23:05:37.794696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4028 23:05:37.794805 ==
4029 23:05:37.794912 [Gating] SW mode calibration
4030 23:05:37.804351 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4031 23:05:37.807899 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4032 23:05:37.814744 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4033 23:05:37.817884 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4034 23:05:37.821255 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4035 23:05:37.824481 0 9 12 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (1 1)
4036 23:05:37.830908 0 9 16 | B1->B0 | 3131 2323 | 1 0 | (1 1) (0 0)
4037 23:05:37.834578 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4038 23:05:37.838217 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4039 23:05:37.844312 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4040 23:05:37.847955 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4041 23:05:37.851055 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4042 23:05:37.858189 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4043 23:05:37.861130 0 10 12 | B1->B0 | 2525 3636 | 0 0 | (0 0) (0 0)
4044 23:05:37.864066 0 10 16 | B1->B0 | 3030 4646 | 0 0 | (0 0) (0 0)
4045 23:05:37.871172 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4046 23:05:37.874476 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4047 23:05:37.877732 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4048 23:05:37.884833 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4049 23:05:37.887699 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4050 23:05:37.891412 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4051 23:05:37.897475 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4052 23:05:37.900764 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4053 23:05:37.904564 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 23:05:37.910929 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 23:05:37.914634 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 23:05:37.917560 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 23:05:37.924429 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 23:05:37.927816 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 23:05:37.930945 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 23:05:37.934222 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 23:05:37.941058 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 23:05:37.944278 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 23:05:37.947418 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 23:05:37.953917 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 23:05:37.957736 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 23:05:37.960907 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 23:05:37.967726 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 23:05:37.970888 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4069 23:05:37.974186 Total UI for P1: 0, mck2ui 16
4070 23:05:37.977214 best dqsien dly found for B0: ( 0, 13, 14)
4071 23:05:37.980896 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4072 23:05:37.984280 Total UI for P1: 0, mck2ui 16
4073 23:05:37.987185 best dqsien dly found for B1: ( 0, 13, 18)
4074 23:05:37.990610 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4075 23:05:37.994154 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4076 23:05:37.997226
4077 23:05:38.001010 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4078 23:05:38.003923 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4079 23:05:38.006988 [Gating] SW calibration Done
4080 23:05:38.007063 ==
4081 23:05:38.011012 Dram Type= 6, Freq= 0, CH_0, rank 0
4082 23:05:38.013738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4083 23:05:38.013849 ==
4084 23:05:38.013945 RX Vref Scan: 0
4085 23:05:38.014040
4086 23:05:38.017504 RX Vref 0 -> 0, step: 1
4087 23:05:38.017628
4088 23:05:38.020632 RX Delay -230 -> 252, step: 16
4089 23:05:38.024124 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4090 23:05:38.030445 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4091 23:05:38.033781 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4092 23:05:38.037543 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4093 23:05:38.040752 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4094 23:05:38.043900 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4095 23:05:38.050746 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4096 23:05:38.053882 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4097 23:05:38.057000 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4098 23:05:38.060901 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4099 23:05:38.064319 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4100 23:05:38.070327 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4101 23:05:38.074208 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4102 23:05:38.077412 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4103 23:05:38.080622 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4104 23:05:38.087422 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4105 23:05:38.087532 ==
4106 23:05:38.090607 Dram Type= 6, Freq= 0, CH_0, rank 0
4107 23:05:38.093711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4108 23:05:38.093819 ==
4109 23:05:38.093916 DQS Delay:
4110 23:05:38.096946 DQS0 = 0, DQS1 = 0
4111 23:05:38.097017 DQM Delay:
4112 23:05:38.100764 DQM0 = 51, DQM1 = 46
4113 23:05:38.100871 DQ Delay:
4114 23:05:38.103884 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4115 23:05:38.107932 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4116 23:05:38.110875 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4117 23:05:38.113676 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4118 23:05:38.113757
4119 23:05:38.113821
4120 23:05:38.113879 ==
4121 23:05:38.117343 Dram Type= 6, Freq= 0, CH_0, rank 0
4122 23:05:38.120782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4123 23:05:38.120866 ==
4124 23:05:38.124010
4125 23:05:38.124090
4126 23:05:38.124154 TX Vref Scan disable
4127 23:05:38.127416 == TX Byte 0 ==
4128 23:05:38.130614 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4129 23:05:38.133779 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4130 23:05:38.137398 == TX Byte 1 ==
4131 23:05:38.140574 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4132 23:05:38.143768 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4133 23:05:38.147031 ==
4134 23:05:38.147111 Dram Type= 6, Freq= 0, CH_0, rank 0
4135 23:05:38.153880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4136 23:05:38.153976 ==
4137 23:05:38.154042
4138 23:05:38.154102
4139 23:05:38.157112 TX Vref Scan disable
4140 23:05:38.157217 == TX Byte 0 ==
4141 23:05:38.163401 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4142 23:05:38.166838 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4143 23:05:38.166913 == TX Byte 1 ==
4144 23:05:38.173537 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4145 23:05:38.176646 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4146 23:05:38.176744
4147 23:05:38.176840 [DATLAT]
4148 23:05:38.179845 Freq=600, CH0 RK0
4149 23:05:38.179949
4150 23:05:38.180037 DATLAT Default: 0x9
4151 23:05:38.183776 0, 0xFFFF, sum = 0
4152 23:05:38.183847 1, 0xFFFF, sum = 0
4153 23:05:38.187124 2, 0xFFFF, sum = 0
4154 23:05:38.187194 3, 0xFFFF, sum = 0
4155 23:05:38.190380 4, 0xFFFF, sum = 0
4156 23:05:38.190477 5, 0xFFFF, sum = 0
4157 23:05:38.193332 6, 0xFFFF, sum = 0
4158 23:05:38.196766 7, 0xFFFF, sum = 0
4159 23:05:38.196857 8, 0x0, sum = 1
4160 23:05:38.196924 9, 0x0, sum = 2
4161 23:05:38.200449 10, 0x0, sum = 3
4162 23:05:38.200541 11, 0x0, sum = 4
4163 23:05:38.203594 best_step = 9
4164 23:05:38.203698
4165 23:05:38.203786 ==
4166 23:05:38.206466 Dram Type= 6, Freq= 0, CH_0, rank 0
4167 23:05:38.210204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4168 23:05:38.210278 ==
4169 23:05:38.213506 RX Vref Scan: 1
4170 23:05:38.213643
4171 23:05:38.213707 RX Vref 0 -> 0, step: 1
4172 23:05:38.213779
4173 23:05:38.216484 RX Delay -163 -> 252, step: 8
4174 23:05:38.216580
4175 23:05:38.219794 Set Vref, RX VrefLevel [Byte0]: 54
4176 23:05:38.223114 [Byte1]: 53
4177 23:05:38.227482
4178 23:05:38.227610 Final RX Vref Byte 0 = 54 to rank0
4179 23:05:38.230475 Final RX Vref Byte 1 = 53 to rank0
4180 23:05:38.234042 Final RX Vref Byte 0 = 54 to rank1
4181 23:05:38.237098 Final RX Vref Byte 1 = 53 to rank1==
4182 23:05:38.240114 Dram Type= 6, Freq= 0, CH_0, rank 0
4183 23:05:38.246899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4184 23:05:38.247014 ==
4185 23:05:38.247114 DQS Delay:
4186 23:05:38.247242 DQS0 = 0, DQS1 = 0
4187 23:05:38.250122 DQM Delay:
4188 23:05:38.250230 DQM0 = 52, DQM1 = 47
4189 23:05:38.253777 DQ Delay:
4190 23:05:38.257010 DQ0 =52, DQ1 =56, DQ2 =48, DQ3 =48
4191 23:05:38.260250 DQ4 =56, DQ5 =44, DQ6 =60, DQ7 =56
4192 23:05:38.263525 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =44
4193 23:05:38.266688 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4194 23:05:38.266761
4195 23:05:38.266822
4196 23:05:38.273158 [DQSOSCAuto] RK0, (LSB)MR18= 0x7164, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 388 ps
4197 23:05:38.276897 CH0 RK0: MR19=808, MR18=7164
4198 23:05:38.283306 CH0_RK0: MR19=0x808, MR18=0x7164, DQSOSC=388, MR23=63, INC=174, DEC=116
4199 23:05:38.283411
4200 23:05:38.286793 ----->DramcWriteLeveling(PI) begin...
4201 23:05:38.286905 ==
4202 23:05:38.289831 Dram Type= 6, Freq= 0, CH_0, rank 1
4203 23:05:38.293907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4204 23:05:38.294010 ==
4205 23:05:38.297169 Write leveling (Byte 0): 33 => 33
4206 23:05:38.300377 Write leveling (Byte 1): 34 => 34
4207 23:05:38.303299 DramcWriteLeveling(PI) end<-----
4208 23:05:38.303373
4209 23:05:38.303436 ==
4210 23:05:38.306819 Dram Type= 6, Freq= 0, CH_0, rank 1
4211 23:05:38.309780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4212 23:05:38.309854 ==
4213 23:05:38.313085 [Gating] SW mode calibration
4214 23:05:38.320261 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4215 23:05:38.326613 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4216 23:05:38.329870 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4217 23:05:38.336721 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4218 23:05:38.339892 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4219 23:05:38.342975 0 9 12 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
4220 23:05:38.346296 0 9 16 | B1->B0 | 2a2a 2424 | 1 1 | (1 0) (1 0)
4221 23:05:38.353053 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4222 23:05:38.356298 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4223 23:05:38.359570 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4224 23:05:38.366107 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4225 23:05:38.369804 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4226 23:05:38.373089 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4227 23:05:38.379761 0 10 12 | B1->B0 | 2626 2b2b | 0 0 | (0 0) (0 0)
4228 23:05:38.383346 0 10 16 | B1->B0 | 3f3f 4646 | 1 0 | (0 0) (0 0)
4229 23:05:38.386473 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4230 23:05:38.392991 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4231 23:05:38.396659 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4232 23:05:38.399870 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4233 23:05:38.406205 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4234 23:05:38.409864 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4235 23:05:38.412965 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4236 23:05:38.419624 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 23:05:38.422836 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 23:05:38.426137 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 23:05:38.432891 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 23:05:38.436610 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 23:05:38.439902 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 23:05:38.446557 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 23:05:38.449403 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 23:05:38.452667 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 23:05:38.459511 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 23:05:38.462615 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 23:05:38.466159 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 23:05:38.472549 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 23:05:38.476188 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 23:05:38.479247 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 23:05:38.482674 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4252 23:05:38.489158 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4253 23:05:38.492878 Total UI for P1: 0, mck2ui 16
4254 23:05:38.496161 best dqsien dly found for B0: ( 0, 13, 12)
4255 23:05:38.499393 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4256 23:05:38.502778 Total UI for P1: 0, mck2ui 16
4257 23:05:38.506289 best dqsien dly found for B1: ( 0, 13, 14)
4258 23:05:38.509465 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4259 23:05:38.512548 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4260 23:05:38.512721
4261 23:05:38.516301 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4262 23:05:38.522724 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4263 23:05:38.522827 [Gating] SW calibration Done
4264 23:05:38.522925 ==
4265 23:05:38.525812 Dram Type= 6, Freq= 0, CH_0, rank 1
4266 23:05:38.532784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4267 23:05:38.532884 ==
4268 23:05:38.532982 RX Vref Scan: 0
4269 23:05:38.533076
4270 23:05:38.535689 RX Vref 0 -> 0, step: 1
4271 23:05:38.535801
4272 23:05:38.539150 RX Delay -230 -> 252, step: 16
4273 23:05:38.542272 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4274 23:05:38.545934 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4275 23:05:38.552541 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4276 23:05:38.555474 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4277 23:05:38.559224 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4278 23:05:38.562237 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4279 23:05:38.565560 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4280 23:05:38.572376 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4281 23:05:38.575348 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4282 23:05:38.578793 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4283 23:05:38.582456 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4284 23:05:38.588974 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4285 23:05:38.592309 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4286 23:05:38.595493 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4287 23:05:38.598847 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4288 23:05:38.605175 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4289 23:05:38.605257 ==
4290 23:05:38.608821 Dram Type= 6, Freq= 0, CH_0, rank 1
4291 23:05:38.611938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4292 23:05:38.612021 ==
4293 23:05:38.612085 DQS Delay:
4294 23:05:38.615355 DQS0 = 0, DQS1 = 0
4295 23:05:38.615436 DQM Delay:
4296 23:05:38.618479 DQM0 = 51, DQM1 = 44
4297 23:05:38.618560 DQ Delay:
4298 23:05:38.621907 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4299 23:05:38.624995 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4300 23:05:38.628891 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =33
4301 23:05:38.632061 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =49
4302 23:05:38.632142
4303 23:05:38.632206
4304 23:05:38.632265 ==
4305 23:05:38.635163 Dram Type= 6, Freq= 0, CH_0, rank 1
4306 23:05:38.638393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4307 23:05:38.638475 ==
4308 23:05:38.638539
4309 23:05:38.638597
4310 23:05:38.641656 TX Vref Scan disable
4311 23:05:38.645425 == TX Byte 0 ==
4312 23:05:38.648505 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4313 23:05:38.652046 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4314 23:05:38.655026 == TX Byte 1 ==
4315 23:05:38.658459 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4316 23:05:38.662097 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4317 23:05:38.662184 ==
4318 23:05:38.665386 Dram Type= 6, Freq= 0, CH_0, rank 1
4319 23:05:38.671765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4320 23:05:38.671847 ==
4321 23:05:38.671911
4322 23:05:38.671970
4323 23:05:38.672027 TX Vref Scan disable
4324 23:05:38.675756 == TX Byte 0 ==
4325 23:05:38.679513 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4326 23:05:38.685847 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4327 23:05:38.685962 == TX Byte 1 ==
4328 23:05:38.689731 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4329 23:05:38.696445 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4330 23:05:38.696552
4331 23:05:38.696651 [DATLAT]
4332 23:05:38.696749 Freq=600, CH0 RK1
4333 23:05:38.696836
4334 23:05:38.699650 DATLAT Default: 0x9
4335 23:05:38.699752 0, 0xFFFF, sum = 0
4336 23:05:38.702949 1, 0xFFFF, sum = 0
4337 23:05:38.703021 2, 0xFFFF, sum = 0
4338 23:05:38.706096 3, 0xFFFF, sum = 0
4339 23:05:38.706171 4, 0xFFFF, sum = 0
4340 23:05:38.709334 5, 0xFFFF, sum = 0
4341 23:05:38.712580 6, 0xFFFF, sum = 0
4342 23:05:38.712694 7, 0xFFFF, sum = 0
4343 23:05:38.712795 8, 0x0, sum = 1
4344 23:05:38.716489 9, 0x0, sum = 2
4345 23:05:38.716594 10, 0x0, sum = 3
4346 23:05:38.719571 11, 0x0, sum = 4
4347 23:05:38.719671 best_step = 9
4348 23:05:38.719767
4349 23:05:38.719862 ==
4350 23:05:38.722485 Dram Type= 6, Freq= 0, CH_0, rank 1
4351 23:05:38.729050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4352 23:05:38.729159 ==
4353 23:05:38.729259 RX Vref Scan: 0
4354 23:05:38.729348
4355 23:05:38.732648 RX Vref 0 -> 0, step: 1
4356 23:05:38.732755
4357 23:05:38.736088 RX Delay -163 -> 252, step: 8
4358 23:05:38.739289 iDelay=197, Bit 0, Center 52 (-91 ~ 196) 288
4359 23:05:38.745818 iDelay=197, Bit 1, Center 56 (-83 ~ 196) 280
4360 23:05:38.749004 iDelay=197, Bit 2, Center 52 (-91 ~ 196) 288
4361 23:05:38.752882 iDelay=197, Bit 3, Center 52 (-91 ~ 196) 288
4362 23:05:38.755941 iDelay=197, Bit 4, Center 56 (-83 ~ 196) 280
4363 23:05:38.759656 iDelay=197, Bit 5, Center 44 (-99 ~ 188) 288
4364 23:05:38.762715 iDelay=197, Bit 6, Center 56 (-83 ~ 196) 280
4365 23:05:38.769077 iDelay=197, Bit 7, Center 60 (-75 ~ 196) 272
4366 23:05:38.772461 iDelay=197, Bit 8, Center 36 (-107 ~ 180) 288
4367 23:05:38.776027 iDelay=197, Bit 9, Center 36 (-107 ~ 180) 288
4368 23:05:38.778984 iDelay=197, Bit 10, Center 48 (-91 ~ 188) 280
4369 23:05:38.785510 iDelay=197, Bit 11, Center 40 (-99 ~ 180) 280
4370 23:05:38.789117 iDelay=197, Bit 12, Center 56 (-83 ~ 196) 280
4371 23:05:38.792365 iDelay=197, Bit 13, Center 56 (-83 ~ 196) 280
4372 23:05:38.796228 iDelay=197, Bit 14, Center 56 (-83 ~ 196) 280
4373 23:05:38.799399 iDelay=197, Bit 15, Center 52 (-91 ~ 196) 288
4374 23:05:38.799480 ==
4375 23:05:38.802655 Dram Type= 6, Freq= 0, CH_0, rank 1
4376 23:05:38.809392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4377 23:05:38.809476 ==
4378 23:05:38.809542 DQS Delay:
4379 23:05:38.812687 DQS0 = 0, DQS1 = 0
4380 23:05:38.812759 DQM Delay:
4381 23:05:38.815882 DQM0 = 53, DQM1 = 47
4382 23:05:38.815992 DQ Delay:
4383 23:05:38.819122 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4384 23:05:38.822287 DQ4 =56, DQ5 =44, DQ6 =56, DQ7 =60
4385 23:05:38.825421 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4386 23:05:38.829033 DQ12 =56, DQ13 =56, DQ14 =56, DQ15 =52
4387 23:05:38.829132
4388 23:05:38.829220
4389 23:05:38.835986 [DQSOSCAuto] RK1, (LSB)MR18= 0x6322, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 391 ps
4390 23:05:38.838818 CH0 RK1: MR19=808, MR18=6322
4391 23:05:38.845689 CH0_RK1: MR19=0x808, MR18=0x6322, DQSOSC=391, MR23=63, INC=171, DEC=114
4392 23:05:38.848787 [RxdqsGatingPostProcess] freq 600
4393 23:05:38.852129 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4394 23:05:38.855821 Pre-setting of DQS Precalculation
4395 23:05:38.862337 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4396 23:05:38.862413 ==
4397 23:05:38.865886 Dram Type= 6, Freq= 0, CH_1, rank 0
4398 23:05:38.869037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4399 23:05:38.869132 ==
4400 23:05:38.875398 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4401 23:05:38.881967 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4402 23:05:38.885762 [CA 0] Center 36 (5~67) winsize 63
4403 23:05:38.888821 [CA 1] Center 36 (5~67) winsize 63
4404 23:05:38.892031 [CA 2] Center 35 (4~66) winsize 63
4405 23:05:38.895190 [CA 3] Center 34 (4~65) winsize 62
4406 23:05:38.898594 [CA 4] Center 34 (4~65) winsize 62
4407 23:05:38.902333 [CA 5] Center 34 (4~65) winsize 62
4408 23:05:38.902420
4409 23:05:38.905539 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4410 23:05:38.905675
4411 23:05:38.908845 [CATrainingPosCal] consider 1 rank data
4412 23:05:38.912383 u2DelayCellTimex100 = 270/100 ps
4413 23:05:38.915418 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4414 23:05:38.918889 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4415 23:05:38.922071 CA2 delay=35 (4~66),Diff = 1 PI (9 cell)
4416 23:05:38.925448 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4417 23:05:38.928827 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4418 23:05:38.932042 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4419 23:05:38.932140
4420 23:05:38.935525 CA PerBit enable=1, Macro0, CA PI delay=34
4421 23:05:38.938712
4422 23:05:38.938795 [CBTSetCACLKResult] CA Dly = 34
4423 23:05:38.941911 CS Dly: 6 (0~37)
4424 23:05:38.941993 ==
4425 23:05:38.945630 Dram Type= 6, Freq= 0, CH_1, rank 1
4426 23:05:38.948657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4427 23:05:38.948764 ==
4428 23:05:38.955205 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4429 23:05:38.962340 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4430 23:05:38.965488 [CA 0] Center 36 (6~67) winsize 62
4431 23:05:38.968576 [CA 1] Center 36 (6~67) winsize 62
4432 23:05:38.972178 [CA 2] Center 35 (4~66) winsize 63
4433 23:05:38.975243 [CA 3] Center 35 (4~66) winsize 63
4434 23:05:38.978555 [CA 4] Center 35 (4~66) winsize 63
4435 23:05:38.981774 [CA 5] Center 34 (4~65) winsize 62
4436 23:05:38.981872
4437 23:05:38.985012 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4438 23:05:38.985116
4439 23:05:38.988879 [CATrainingPosCal] consider 2 rank data
4440 23:05:38.991899 u2DelayCellTimex100 = 270/100 ps
4441 23:05:38.995121 CA0 delay=36 (6~67),Diff = 2 PI (19 cell)
4442 23:05:38.998344 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
4443 23:05:39.001922 CA2 delay=35 (4~66),Diff = 1 PI (9 cell)
4444 23:05:39.004996 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4445 23:05:39.008432 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4446 23:05:39.011543 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4447 23:05:39.011617
4448 23:05:39.018627 CA PerBit enable=1, Macro0, CA PI delay=34
4449 23:05:39.018735
4450 23:05:39.021929 [CBTSetCACLKResult] CA Dly = 34
4451 23:05:39.022028 CS Dly: 7 (0~39)
4452 23:05:39.022119
4453 23:05:39.025466 ----->DramcWriteLeveling(PI) begin...
4454 23:05:39.025564 ==
4455 23:05:39.028389 Dram Type= 6, Freq= 0, CH_1, rank 0
4456 23:05:39.031680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4457 23:05:39.031755 ==
4458 23:05:39.035202 Write leveling (Byte 0): 31 => 31
4459 23:05:39.038090 Write leveling (Byte 1): 31 => 31
4460 23:05:39.041428 DramcWriteLeveling(PI) end<-----
4461 23:05:39.041532
4462 23:05:39.041650 ==
4463 23:05:39.044907 Dram Type= 6, Freq= 0, CH_1, rank 0
4464 23:05:39.051789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4465 23:05:39.051884 ==
4466 23:05:39.051950 [Gating] SW mode calibration
4467 23:05:39.061529 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4468 23:05:39.064880 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4469 23:05:39.068043 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4470 23:05:39.075067 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4471 23:05:39.078059 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4472 23:05:39.081754 0 9 12 | B1->B0 | 2e2e 2e2e | 0 0 | (0 0) (0 0)
4473 23:05:39.088535 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4474 23:05:39.091701 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4475 23:05:39.094902 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4476 23:05:39.101368 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4477 23:05:39.105311 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4478 23:05:39.108081 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4479 23:05:39.114645 0 10 8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
4480 23:05:39.118385 0 10 12 | B1->B0 | 3737 3f3f | 0 0 | (0 0) (0 0)
4481 23:05:39.121768 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4482 23:05:39.128084 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4483 23:05:39.131858 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4484 23:05:39.134862 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4485 23:05:39.141955 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4486 23:05:39.144984 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4487 23:05:39.148179 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4488 23:05:39.152061 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4489 23:05:39.158329 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 23:05:39.161583 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 23:05:39.164571 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 23:05:39.171724 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 23:05:39.174631 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 23:05:39.178039 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 23:05:39.184505 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 23:05:39.187861 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 23:05:39.191226 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 23:05:39.197638 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 23:05:39.201210 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 23:05:39.204454 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 23:05:39.211000 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 23:05:39.214562 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 23:05:39.217915 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 23:05:39.224316 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4505 23:05:39.228066 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4506 23:05:39.231194 Total UI for P1: 0, mck2ui 16
4507 23:05:39.234527 best dqsien dly found for B0: ( 0, 13, 12)
4508 23:05:39.237785 Total UI for P1: 0, mck2ui 16
4509 23:05:39.240909 best dqsien dly found for B1: ( 0, 13, 12)
4510 23:05:39.244414 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4511 23:05:39.247509 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4512 23:05:39.247586
4513 23:05:39.250770 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4514 23:05:39.253947 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4515 23:05:39.257771 [Gating] SW calibration Done
4516 23:05:39.257867 ==
4517 23:05:39.260826 Dram Type= 6, Freq= 0, CH_1, rank 0
4518 23:05:39.267518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4519 23:05:39.267633 ==
4520 23:05:39.267726 RX Vref Scan: 0
4521 23:05:39.267822
4522 23:05:39.270742 RX Vref 0 -> 0, step: 1
4523 23:05:39.270848
4524 23:05:39.273863 RX Delay -230 -> 252, step: 16
4525 23:05:39.277503 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4526 23:05:39.280631 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4527 23:05:39.284347 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4528 23:05:39.290507 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4529 23:05:39.293855 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4530 23:05:39.297670 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4531 23:05:39.300764 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4532 23:05:39.303993 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4533 23:05:39.310699 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4534 23:05:39.314196 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4535 23:05:39.316903 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4536 23:05:39.320522 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4537 23:05:39.327210 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4538 23:05:39.330712 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4539 23:05:39.333719 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4540 23:05:39.337475 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4541 23:05:39.340640 ==
4542 23:05:39.340748 Dram Type= 6, Freq= 0, CH_1, rank 0
4543 23:05:39.346801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4544 23:05:39.346911 ==
4545 23:05:39.347004 DQS Delay:
4546 23:05:39.350452 DQS0 = 0, DQS1 = 0
4547 23:05:39.350527 DQM Delay:
4548 23:05:39.353533 DQM0 = 50, DQM1 = 46
4549 23:05:39.353642 DQ Delay:
4550 23:05:39.357364 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =49
4551 23:05:39.360484 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4552 23:05:39.363724 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4553 23:05:39.367072 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4554 23:05:39.367146
4555 23:05:39.367207
4556 23:05:39.367265 ==
4557 23:05:39.370377 Dram Type= 6, Freq= 0, CH_1, rank 0
4558 23:05:39.373333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4559 23:05:39.373437 ==
4560 23:05:39.373528
4561 23:05:39.373623
4562 23:05:39.376710 TX Vref Scan disable
4563 23:05:39.380348 == TX Byte 0 ==
4564 23:05:39.383653 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4565 23:05:39.386665 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4566 23:05:39.389748 == TX Byte 1 ==
4567 23:05:39.393745 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4568 23:05:39.397063 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4569 23:05:39.397139 ==
4570 23:05:39.400074 Dram Type= 6, Freq= 0, CH_1, rank 0
4571 23:05:39.406654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4572 23:05:39.406759 ==
4573 23:05:39.406829
4574 23:05:39.406905
4575 23:05:39.406963 TX Vref Scan disable
4576 23:05:39.410676 == TX Byte 0 ==
4577 23:05:39.413915 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4578 23:05:39.420824 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4579 23:05:39.420929 == TX Byte 1 ==
4580 23:05:39.424109 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4581 23:05:39.430538 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4582 23:05:39.430639
4583 23:05:39.430728 [DATLAT]
4584 23:05:39.430789 Freq=600, CH1 RK0
4585 23:05:39.430847
4586 23:05:39.434024 DATLAT Default: 0x9
4587 23:05:39.434128 0, 0xFFFF, sum = 0
4588 23:05:39.436991 1, 0xFFFF, sum = 0
4589 23:05:39.440821 2, 0xFFFF, sum = 0
4590 23:05:39.440924 3, 0xFFFF, sum = 0
4591 23:05:39.443545 4, 0xFFFF, sum = 0
4592 23:05:39.443636 5, 0xFFFF, sum = 0
4593 23:05:39.447014 6, 0xFFFF, sum = 0
4594 23:05:39.447096 7, 0xFFFF, sum = 0
4595 23:05:39.450770 8, 0x0, sum = 1
4596 23:05:39.450870 9, 0x0, sum = 2
4597 23:05:39.450937 10, 0x0, sum = 3
4598 23:05:39.453806 11, 0x0, sum = 4
4599 23:05:39.453900 best_step = 9
4600 23:05:39.453993
4601 23:05:39.454079 ==
4602 23:05:39.457033 Dram Type= 6, Freq= 0, CH_1, rank 0
4603 23:05:39.463762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4604 23:05:39.463866 ==
4605 23:05:39.463967 RX Vref Scan: 1
4606 23:05:39.464055
4607 23:05:39.467009 RX Vref 0 -> 0, step: 1
4608 23:05:39.467105
4609 23:05:39.470748 RX Delay -163 -> 252, step: 8
4610 23:05:39.470821
4611 23:05:39.473950 Set Vref, RX VrefLevel [Byte0]: 57
4612 23:05:39.477114 [Byte1]: 53
4613 23:05:39.477212
4614 23:05:39.480379 Final RX Vref Byte 0 = 57 to rank0
4615 23:05:39.483429 Final RX Vref Byte 1 = 53 to rank0
4616 23:05:39.486715 Final RX Vref Byte 0 = 57 to rank1
4617 23:05:39.490490 Final RX Vref Byte 1 = 53 to rank1==
4618 23:05:39.493673 Dram Type= 6, Freq= 0, CH_1, rank 0
4619 23:05:39.496662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4620 23:05:39.496739 ==
4621 23:05:39.499916 DQS Delay:
4622 23:05:39.500015 DQS0 = 0, DQS1 = 0
4623 23:05:39.503202 DQM Delay:
4624 23:05:39.503278 DQM0 = 49, DQM1 = 45
4625 23:05:39.503341 DQ Delay:
4626 23:05:39.506938 DQ0 =52, DQ1 =44, DQ2 =40, DQ3 =48
4627 23:05:39.509859 DQ4 =48, DQ5 =56, DQ6 =56, DQ7 =48
4628 23:05:39.513177 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =36
4629 23:05:39.516845 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =56
4630 23:05:39.516943
4631 23:05:39.517038
4632 23:05:39.526993 [DQSOSCAuto] RK0, (LSB)MR18= 0x456a, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4633 23:05:39.530184 CH1 RK0: MR19=808, MR18=456A
4634 23:05:39.536785 CH1_RK0: MR19=0x808, MR18=0x456A, DQSOSC=389, MR23=63, INC=173, DEC=115
4635 23:05:39.536886
4636 23:05:39.539614 ----->DramcWriteLeveling(PI) begin...
4637 23:05:39.539710 ==
4638 23:05:39.543161 Dram Type= 6, Freq= 0, CH_1, rank 1
4639 23:05:39.546494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4640 23:05:39.546576 ==
4641 23:05:39.550006 Write leveling (Byte 0): 31 => 31
4642 23:05:39.553614 Write leveling (Byte 1): 31 => 31
4643 23:05:39.556824 DramcWriteLeveling(PI) end<-----
4644 23:05:39.556950
4645 23:05:39.557013 ==
4646 23:05:39.560174 Dram Type= 6, Freq= 0, CH_1, rank 1
4647 23:05:39.563400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4648 23:05:39.563486 ==
4649 23:05:39.566538 [Gating] SW mode calibration
4650 23:05:39.573430 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4651 23:05:39.580426 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4652 23:05:39.583463 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4653 23:05:39.586521 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4654 23:05:39.592856 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4655 23:05:39.596685 0 9 12 | B1->B0 | 2e2e 2f2f | 0 0 | (1 1) (0 0)
4656 23:05:39.599958 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4657 23:05:39.606556 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4658 23:05:39.609509 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4659 23:05:39.613199 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4660 23:05:39.619591 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4661 23:05:39.622740 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4662 23:05:39.626448 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4663 23:05:39.632839 0 10 12 | B1->B0 | 3a3a 3737 | 1 0 | (0 0) (1 1)
4664 23:05:39.636035 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4665 23:05:39.639248 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4666 23:05:39.645949 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4667 23:05:39.649466 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4668 23:05:39.652713 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4669 23:05:39.656269 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4670 23:05:39.662935 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4671 23:05:39.666091 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4672 23:05:39.669395 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4673 23:05:39.675989 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4674 23:05:39.679072 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4675 23:05:39.682900 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4676 23:05:39.689376 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4677 23:05:39.692865 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4678 23:05:39.696158 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4679 23:05:39.702520 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4680 23:05:39.705910 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4681 23:05:39.709041 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4682 23:05:39.716009 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4683 23:05:39.719121 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4684 23:05:39.722203 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4685 23:05:39.729234 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4686 23:05:39.732377 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4687 23:05:39.735641 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4688 23:05:39.738786 Total UI for P1: 0, mck2ui 16
4689 23:05:39.742078 best dqsien dly found for B0: ( 0, 13, 10)
4690 23:05:39.745852 Total UI for P1: 0, mck2ui 16
4691 23:05:39.749146 best dqsien dly found for B1: ( 0, 13, 8)
4692 23:05:39.752102 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4693 23:05:39.755678 best DQS1 dly(MCK, UI, PI) = (0, 13, 8)
4694 23:05:39.755758
4695 23:05:39.762075 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4696 23:05:39.765214 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 8)
4697 23:05:39.765295 [Gating] SW calibration Done
4698 23:05:39.769034 ==
4699 23:05:39.771838 Dram Type= 6, Freq= 0, CH_1, rank 1
4700 23:05:39.775466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4701 23:05:39.775547 ==
4702 23:05:39.775612 RX Vref Scan: 0
4703 23:05:39.775672
4704 23:05:39.779212 RX Vref 0 -> 0, step: 1
4705 23:05:39.779292
4706 23:05:39.781755 RX Delay -230 -> 252, step: 16
4707 23:05:39.785321 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4708 23:05:39.788463 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4709 23:05:39.795624 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4710 23:05:39.798569 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4711 23:05:39.801760 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4712 23:05:39.805484 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4713 23:05:39.812011 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4714 23:05:39.814970 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4715 23:05:39.818303 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4716 23:05:39.821821 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4717 23:05:39.825267 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4718 23:05:39.832209 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4719 23:05:39.835004 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4720 23:05:39.838380 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4721 23:05:39.841486 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4722 23:05:39.848467 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4723 23:05:39.848555 ==
4724 23:05:39.851648 Dram Type= 6, Freq= 0, CH_1, rank 1
4725 23:05:39.854839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4726 23:05:39.854921 ==
4727 23:05:39.854985 DQS Delay:
4728 23:05:39.858143 DQS0 = 0, DQS1 = 0
4729 23:05:39.858223 DQM Delay:
4730 23:05:39.861355 DQM0 = 50, DQM1 = 47
4731 23:05:39.861461 DQ Delay:
4732 23:05:39.865055 DQ0 =49, DQ1 =49, DQ2 =33, DQ3 =49
4733 23:05:39.868216 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4734 23:05:39.871928 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4735 23:05:39.875326 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4736 23:05:39.875424
4737 23:05:39.875513
4738 23:05:39.875598 ==
4739 23:05:39.878394 Dram Type= 6, Freq= 0, CH_1, rank 1
4740 23:05:39.881519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4741 23:05:39.881621 ==
4742 23:05:39.881686
4743 23:05:39.885146
4744 23:05:39.885225 TX Vref Scan disable
4745 23:05:39.888270 == TX Byte 0 ==
4746 23:05:39.891484 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4747 23:05:39.894764 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4748 23:05:39.898741 == TX Byte 1 ==
4749 23:05:39.901911 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4750 23:05:39.904871 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4751 23:05:39.904951 ==
4752 23:05:39.908571 Dram Type= 6, Freq= 0, CH_1, rank 1
4753 23:05:39.914950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4754 23:05:39.915045 ==
4755 23:05:39.915111
4756 23:05:39.915170
4757 23:05:39.915227 TX Vref Scan disable
4758 23:05:39.919476 == TX Byte 0 ==
4759 23:05:39.922686 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4760 23:05:39.926550 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4761 23:05:39.929413 == TX Byte 1 ==
4762 23:05:39.932563 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4763 23:05:39.939433 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4764 23:05:39.939513
4765 23:05:39.939584 [DATLAT]
4766 23:05:39.939643 Freq=600, CH1 RK1
4767 23:05:39.939700
4768 23:05:39.942712 DATLAT Default: 0x9
4769 23:05:39.942788 0, 0xFFFF, sum = 0
4770 23:05:39.946004 1, 0xFFFF, sum = 0
4771 23:05:39.946076 2, 0xFFFF, sum = 0
4772 23:05:39.949525 3, 0xFFFF, sum = 0
4773 23:05:39.952579 4, 0xFFFF, sum = 0
4774 23:05:39.952664 5, 0xFFFF, sum = 0
4775 23:05:39.955692 6, 0xFFFF, sum = 0
4776 23:05:39.955775 7, 0xFFFF, sum = 0
4777 23:05:39.958841 8, 0x0, sum = 1
4778 23:05:39.958923 9, 0x0, sum = 2
4779 23:05:39.958988 10, 0x0, sum = 3
4780 23:05:39.962500 11, 0x0, sum = 4
4781 23:05:39.962581 best_step = 9
4782 23:05:39.962646
4783 23:05:39.962705 ==
4784 23:05:39.965560 Dram Type= 6, Freq= 0, CH_1, rank 1
4785 23:05:39.972872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4786 23:05:39.972986 ==
4787 23:05:39.973078 RX Vref Scan: 0
4788 23:05:39.973170
4789 23:05:39.975816 RX Vref 0 -> 0, step: 1
4790 23:05:39.975888
4791 23:05:39.979026 RX Delay -163 -> 252, step: 8
4792 23:05:39.982251 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4793 23:05:39.989152 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4794 23:05:39.992258 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4795 23:05:39.995523 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4796 23:05:39.998703 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288
4797 23:05:40.002088 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4798 23:05:40.009209 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4799 23:05:40.012067 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4800 23:05:40.015546 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4801 23:05:40.018674 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4802 23:05:40.021901 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4803 23:05:40.028910 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4804 23:05:40.032028 iDelay=205, Bit 12, Center 56 (-91 ~ 204) 296
4805 23:05:40.035262 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4806 23:05:40.038459 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4807 23:05:40.045500 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4808 23:05:40.045630 ==
4809 23:05:40.048802 Dram Type= 6, Freq= 0, CH_1, rank 1
4810 23:05:40.051957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4811 23:05:40.052054 ==
4812 23:05:40.052143 DQS Delay:
4813 23:05:40.055263 DQS0 = 0, DQS1 = 0
4814 23:05:40.055359 DQM Delay:
4815 23:05:40.058718 DQM0 = 48, DQM1 = 46
4816 23:05:40.058789 DQ Delay:
4817 23:05:40.062053 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4818 23:05:40.065268 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =48
4819 23:05:40.068301 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4820 23:05:40.071624 DQ12 =56, DQ13 =52, DQ14 =52, DQ15 =56
4821 23:05:40.071698
4822 23:05:40.071760
4823 23:05:40.078524 [DQSOSCAuto] RK1, (LSB)MR18= 0x6a22, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 389 ps
4824 23:05:40.081906 CH1 RK1: MR19=808, MR18=6A22
4825 23:05:40.088085 CH1_RK1: MR19=0x808, MR18=0x6A22, DQSOSC=389, MR23=63, INC=173, DEC=115
4826 23:05:40.091443 [RxdqsGatingPostProcess] freq 600
4827 23:05:40.098356 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4828 23:05:40.101693 Pre-setting of DQS Precalculation
4829 23:05:40.104869 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4830 23:05:40.111603 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4831 23:05:40.118272 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4832 23:05:40.118363
4833 23:05:40.118429
4834 23:05:40.121863 [Calibration Summary] 1200 Mbps
4835 23:05:40.124993 CH 0, Rank 0
4836 23:05:40.125067 SW Impedance : PASS
4837 23:05:40.128126 DUTY Scan : NO K
4838 23:05:40.131961 ZQ Calibration : PASS
4839 23:05:40.132069 Jitter Meter : NO K
4840 23:05:40.134974 CBT Training : PASS
4841 23:05:40.138116 Write leveling : PASS
4842 23:05:40.138201 RX DQS gating : PASS
4843 23:05:40.141405 RX DQ/DQS(RDDQC) : PASS
4844 23:05:40.145295 TX DQ/DQS : PASS
4845 23:05:40.145377 RX DATLAT : PASS
4846 23:05:40.148294 RX DQ/DQS(Engine): PASS
4847 23:05:40.148489 TX OE : NO K
4848 23:05:40.151588 All Pass.
4849 23:05:40.151669
4850 23:05:40.151733 CH 0, Rank 1
4851 23:05:40.154837 SW Impedance : PASS
4852 23:05:40.154944 DUTY Scan : NO K
4853 23:05:40.158297 ZQ Calibration : PASS
4854 23:05:40.161188 Jitter Meter : NO K
4855 23:05:40.161294 CBT Training : PASS
4856 23:05:40.164423 Write leveling : PASS
4857 23:05:40.168104 RX DQS gating : PASS
4858 23:05:40.168184 RX DQ/DQS(RDDQC) : PASS
4859 23:05:40.171172 TX DQ/DQS : PASS
4860 23:05:40.174887 RX DATLAT : PASS
4861 23:05:40.174968 RX DQ/DQS(Engine): PASS
4862 23:05:40.178036 TX OE : NO K
4863 23:05:40.178116 All Pass.
4864 23:05:40.178180
4865 23:05:40.181257 CH 1, Rank 0
4866 23:05:40.181336 SW Impedance : PASS
4867 23:05:40.184451 DUTY Scan : NO K
4868 23:05:40.188197 ZQ Calibration : PASS
4869 23:05:40.188278 Jitter Meter : NO K
4870 23:05:40.191325 CBT Training : PASS
4871 23:05:40.194944 Write leveling : PASS
4872 23:05:40.195026 RX DQS gating : PASS
4873 23:05:40.197768 RX DQ/DQS(RDDQC) : PASS
4874 23:05:40.201282 TX DQ/DQS : PASS
4875 23:05:40.201362 RX DATLAT : PASS
4876 23:05:40.205083 RX DQ/DQS(Engine): PASS
4877 23:05:40.205162 TX OE : NO K
4878 23:05:40.208117 All Pass.
4879 23:05:40.208198
4880 23:05:40.208263 CH 1, Rank 1
4881 23:05:40.211085 SW Impedance : PASS
4882 23:05:40.211167 DUTY Scan : NO K
4883 23:05:40.214643 ZQ Calibration : PASS
4884 23:05:40.217468 Jitter Meter : NO K
4885 23:05:40.217550 CBT Training : PASS
4886 23:05:40.220999 Write leveling : PASS
4887 23:05:40.224748 RX DQS gating : PASS
4888 23:05:40.224831 RX DQ/DQS(RDDQC) : PASS
4889 23:05:40.227646 TX DQ/DQS : PASS
4890 23:05:40.231047 RX DATLAT : PASS
4891 23:05:40.231129 RX DQ/DQS(Engine): PASS
4892 23:05:40.234439 TX OE : NO K
4893 23:05:40.234521 All Pass.
4894 23:05:40.234586
4895 23:05:40.237728 DramC Write-DBI off
4896 23:05:40.240850 PER_BANK_REFRESH: Hybrid Mode
4897 23:05:40.240947 TX_TRACKING: ON
4898 23:05:40.251226 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4899 23:05:40.254582 [FAST_K] Save calibration result to emmc
4900 23:05:40.257780 dramc_set_vcore_voltage set vcore to 662500
4901 23:05:40.260931 Read voltage for 933, 3
4902 23:05:40.261013 Vio18 = 0
4903 23:05:40.261078 Vcore = 662500
4904 23:05:40.264798 Vdram = 0
4905 23:05:40.264880 Vddq = 0
4906 23:05:40.264945 Vmddr = 0
4907 23:05:40.271345 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4908 23:05:40.274441 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4909 23:05:40.277708 MEM_TYPE=3, freq_sel=17
4910 23:05:40.280813 sv_algorithm_assistance_LP4_1600
4911 23:05:40.284648 ============ PULL DRAM RESETB DOWN ============
4912 23:05:40.287817 ========== PULL DRAM RESETB DOWN end =========
4913 23:05:40.294336 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4914 23:05:40.297537 ===================================
4915 23:05:40.297668 LPDDR4 DRAM CONFIGURATION
4916 23:05:40.301241 ===================================
4917 23:05:40.304315 EX_ROW_EN[0] = 0x0
4918 23:05:40.307492 EX_ROW_EN[1] = 0x0
4919 23:05:40.307573 LP4Y_EN = 0x0
4920 23:05:40.310655 WORK_FSP = 0x0
4921 23:05:40.310728 WL = 0x3
4922 23:05:40.314229 RL = 0x3
4923 23:05:40.314316 BL = 0x2
4924 23:05:40.317418 RPST = 0x0
4925 23:05:40.317490 RD_PRE = 0x0
4926 23:05:40.320624 WR_PRE = 0x1
4927 23:05:40.320725 WR_PST = 0x0
4928 23:05:40.323892 DBI_WR = 0x0
4929 23:05:40.323965 DBI_RD = 0x0
4930 23:05:40.327631 OTF = 0x1
4931 23:05:40.330335 ===================================
4932 23:05:40.333883 ===================================
4933 23:05:40.333954 ANA top config
4934 23:05:40.337334 ===================================
4935 23:05:40.340668 DLL_ASYNC_EN = 0
4936 23:05:40.343596 ALL_SLAVE_EN = 1
4937 23:05:40.347337 NEW_RANK_MODE = 1
4938 23:05:40.347424 DLL_IDLE_MODE = 1
4939 23:05:40.350401 LP45_APHY_COMB_EN = 1
4940 23:05:40.353863 TX_ODT_DIS = 1
4941 23:05:40.356870 NEW_8X_MODE = 1
4942 23:05:40.360599 ===================================
4943 23:05:40.363634 ===================================
4944 23:05:40.367334 data_rate = 1866
4945 23:05:40.367417 CKR = 1
4946 23:05:40.370637 DQ_P2S_RATIO = 8
4947 23:05:40.373821 ===================================
4948 23:05:40.376982 CA_P2S_RATIO = 8
4949 23:05:40.380644 DQ_CA_OPEN = 0
4950 23:05:40.383674 DQ_SEMI_OPEN = 0
4951 23:05:40.386684 CA_SEMI_OPEN = 0
4952 23:05:40.386770 CA_FULL_RATE = 0
4953 23:05:40.390635 DQ_CKDIV4_EN = 1
4954 23:05:40.393697 CA_CKDIV4_EN = 1
4955 23:05:40.396828 CA_PREDIV_EN = 0
4956 23:05:40.400062 PH8_DLY = 0
4957 23:05:40.403996 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4958 23:05:40.404081 DQ_AAMCK_DIV = 4
4959 23:05:40.407071 CA_AAMCK_DIV = 4
4960 23:05:40.410276 CA_ADMCK_DIV = 4
4961 23:05:40.413473 DQ_TRACK_CA_EN = 0
4962 23:05:40.417225 CA_PICK = 933
4963 23:05:40.420227 CA_MCKIO = 933
4964 23:05:40.423630 MCKIO_SEMI = 0
4965 23:05:40.423721 PLL_FREQ = 3732
4966 23:05:40.426816 DQ_UI_PI_RATIO = 32
4967 23:05:40.430070 CA_UI_PI_RATIO = 0
4968 23:05:40.433260 ===================================
4969 23:05:40.437051 ===================================
4970 23:05:40.439988 memory_type:LPDDR4
4971 23:05:40.440069 GP_NUM : 10
4972 23:05:40.443285 SRAM_EN : 1
4973 23:05:40.446865 MD32_EN : 0
4974 23:05:40.450243 ===================================
4975 23:05:40.450345 [ANA_INIT] >>>>>>>>>>>>>>
4976 23:05:40.453185 <<<<<< [CONFIGURE PHASE]: ANA_TX
4977 23:05:40.456455 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4978 23:05:40.459649 ===================================
4979 23:05:40.463307 data_rate = 1866,PCW = 0X8f00
4980 23:05:40.466242 ===================================
4981 23:05:40.469547 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4982 23:05:40.476437 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4983 23:05:40.479781 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4984 23:05:40.486577 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4985 23:05:40.489457 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4986 23:05:40.492868 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4987 23:05:40.496697 [ANA_INIT] flow start
4988 23:05:40.496815 [ANA_INIT] PLL >>>>>>>>
4989 23:05:40.499873 [ANA_INIT] PLL <<<<<<<<
4990 23:05:40.503282 [ANA_INIT] MIDPI >>>>>>>>
4991 23:05:40.503359 [ANA_INIT] MIDPI <<<<<<<<
4992 23:05:40.506267 [ANA_INIT] DLL >>>>>>>>
4993 23:05:40.509516 [ANA_INIT] flow end
4994 23:05:40.513417 ============ LP4 DIFF to SE enter ============
4995 23:05:40.516528 ============ LP4 DIFF to SE exit ============
4996 23:05:40.519720 [ANA_INIT] <<<<<<<<<<<<<
4997 23:05:40.522878 [Flow] Enable top DCM control >>>>>
4998 23:05:40.526600 [Flow] Enable top DCM control <<<<<
4999 23:05:40.529779 Enable DLL master slave shuffle
5000 23:05:40.533018 ==============================================================
5001 23:05:40.536175 Gating Mode config
5002 23:05:40.539376 ==============================================================
5003 23:05:40.543205 Config description:
5004 23:05:40.553176 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5005 23:05:40.559449 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5006 23:05:40.562638 SELPH_MODE 0: By rank 1: By Phase
5007 23:05:40.569784 ==============================================================
5008 23:05:40.572823 GAT_TRACK_EN = 1
5009 23:05:40.576448 RX_GATING_MODE = 2
5010 23:05:40.579749 RX_GATING_TRACK_MODE = 2
5011 23:05:40.582869 SELPH_MODE = 1
5012 23:05:40.586174 PICG_EARLY_EN = 1
5013 23:05:40.586252 VALID_LAT_VALUE = 1
5014 23:05:40.593008 ==============================================================
5015 23:05:40.596608 Enter into Gating configuration >>>>
5016 23:05:40.599479 Exit from Gating configuration <<<<
5017 23:05:40.602737 Enter into DVFS_PRE_config >>>>>
5018 23:05:40.612660 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5019 23:05:40.615877 Exit from DVFS_PRE_config <<<<<
5020 23:05:40.619544 Enter into PICG configuration >>>>
5021 23:05:40.622782 Exit from PICG configuration <<<<
5022 23:05:40.626069 [RX_INPUT] configuration >>>>>
5023 23:05:40.629133 [RX_INPUT] configuration <<<<<
5024 23:05:40.632895 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5025 23:05:40.639274 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5026 23:05:40.646385 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5027 23:05:40.653068 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5028 23:05:40.659261 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5029 23:05:40.662992 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5030 23:05:40.669449 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5031 23:05:40.672479 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5032 23:05:40.676478 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5033 23:05:40.679503 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5034 23:05:40.685963 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5035 23:05:40.689156 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5036 23:05:40.692945 ===================================
5037 23:05:40.696032 LPDDR4 DRAM CONFIGURATION
5038 23:05:40.699229 ===================================
5039 23:05:40.699337 EX_ROW_EN[0] = 0x0
5040 23:05:40.702609 EX_ROW_EN[1] = 0x0
5041 23:05:40.702690 LP4Y_EN = 0x0
5042 23:05:40.706464 WORK_FSP = 0x0
5043 23:05:40.706545 WL = 0x3
5044 23:05:40.709361 RL = 0x3
5045 23:05:40.709502 BL = 0x2
5046 23:05:40.712618 RPST = 0x0
5047 23:05:40.712698 RD_PRE = 0x0
5048 23:05:40.715917 WR_PRE = 0x1
5049 23:05:40.715997 WR_PST = 0x0
5050 23:05:40.719160 DBI_WR = 0x0
5051 23:05:40.722960 DBI_RD = 0x0
5052 23:05:40.723073 OTF = 0x1
5053 23:05:40.726307 ===================================
5054 23:05:40.729852 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5055 23:05:40.732550 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5056 23:05:40.739486 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5057 23:05:40.742612 ===================================
5058 23:05:40.742693 LPDDR4 DRAM CONFIGURATION
5059 23:05:40.746052 ===================================
5060 23:05:40.749132 EX_ROW_EN[0] = 0x10
5061 23:05:40.752369 EX_ROW_EN[1] = 0x0
5062 23:05:40.752451 LP4Y_EN = 0x0
5063 23:05:40.756260 WORK_FSP = 0x0
5064 23:05:40.756341 WL = 0x3
5065 23:05:40.759805 RL = 0x3
5066 23:05:40.759887 BL = 0x2
5067 23:05:40.762722 RPST = 0x0
5068 23:05:40.762807 RD_PRE = 0x0
5069 23:05:40.765765 WR_PRE = 0x1
5070 23:05:40.765846 WR_PST = 0x0
5071 23:05:40.769220 DBI_WR = 0x0
5072 23:05:40.769302 DBI_RD = 0x0
5073 23:05:40.772828 OTF = 0x1
5074 23:05:40.776206 ===================================
5075 23:05:40.782436 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5076 23:05:40.786305 nWR fixed to 30
5077 23:05:40.789435 [ModeRegInit_LP4] CH0 RK0
5078 23:05:40.789515 [ModeRegInit_LP4] CH0 RK1
5079 23:05:40.792844 [ModeRegInit_LP4] CH1 RK0
5080 23:05:40.795895 [ModeRegInit_LP4] CH1 RK1
5081 23:05:40.795975 match AC timing 9
5082 23:05:40.802525 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5083 23:05:40.805793 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5084 23:05:40.808855 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5085 23:05:40.815618 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5086 23:05:40.819401 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5087 23:05:40.819511 ==
5088 23:05:40.822520 Dram Type= 6, Freq= 0, CH_0, rank 0
5089 23:05:40.825834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5090 23:05:40.825933 ==
5091 23:05:40.831987 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5092 23:05:40.838612 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5093 23:05:40.842006 [CA 0] Center 37 (6~68) winsize 63
5094 23:05:40.845835 [CA 1] Center 37 (7~68) winsize 62
5095 23:05:40.848988 [CA 2] Center 34 (4~65) winsize 62
5096 23:05:40.852390 [CA 3] Center 34 (3~65) winsize 63
5097 23:05:40.855531 [CA 4] Center 33 (3~64) winsize 62
5098 23:05:40.859172 [CA 5] Center 32 (2~62) winsize 61
5099 23:05:40.859307
5100 23:05:40.862039 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5101 23:05:40.862120
5102 23:05:40.865611 [CATrainingPosCal] consider 1 rank data
5103 23:05:40.868679 u2DelayCellTimex100 = 270/100 ps
5104 23:05:40.871657 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5105 23:05:40.875002 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5106 23:05:40.878620 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5107 23:05:40.881951 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5108 23:05:40.885166 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5109 23:05:40.888679 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5110 23:05:40.891921
5111 23:05:40.895310 CA PerBit enable=1, Macro0, CA PI delay=32
5112 23:05:40.895398
5113 23:05:40.898475 [CBTSetCACLKResult] CA Dly = 32
5114 23:05:40.898548 CS Dly: 5 (0~36)
5115 23:05:40.898612 ==
5116 23:05:40.902372 Dram Type= 6, Freq= 0, CH_0, rank 1
5117 23:05:40.905530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5118 23:05:40.905619 ==
5119 23:05:40.911796 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5120 23:05:40.918663 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5121 23:05:40.921721 [CA 0] Center 37 (6~68) winsize 63
5122 23:05:40.925085 [CA 1] Center 37 (7~68) winsize 62
5123 23:05:40.928702 [CA 2] Center 34 (4~65) winsize 62
5124 23:05:40.931992 [CA 3] Center 34 (3~65) winsize 63
5125 23:05:40.935006 [CA 4] Center 33 (3~63) winsize 61
5126 23:05:40.938212 [CA 5] Center 32 (2~62) winsize 61
5127 23:05:40.938293
5128 23:05:40.941963 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5129 23:05:40.942046
5130 23:05:40.945078 [CATrainingPosCal] consider 2 rank data
5131 23:05:40.948064 u2DelayCellTimex100 = 270/100 ps
5132 23:05:40.951638 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5133 23:05:40.954842 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5134 23:05:40.958422 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5135 23:05:40.961663 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5136 23:05:40.968018 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5137 23:05:40.971278 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5138 23:05:40.971358
5139 23:05:40.974589 CA PerBit enable=1, Macro0, CA PI delay=32
5140 23:05:40.974670
5141 23:05:40.977713 [CBTSetCACLKResult] CA Dly = 32
5142 23:05:40.977795 CS Dly: 6 (0~38)
5143 23:05:40.977860
5144 23:05:40.981441 ----->DramcWriteLeveling(PI) begin...
5145 23:05:40.981549 ==
5146 23:05:40.984677 Dram Type= 6, Freq= 0, CH_0, rank 0
5147 23:05:40.991250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5148 23:05:40.991332 ==
5149 23:05:40.994379 Write leveling (Byte 0): 32 => 32
5150 23:05:40.997815 Write leveling (Byte 1): 32 => 32
5151 23:05:40.997896 DramcWriteLeveling(PI) end<-----
5152 23:05:40.997960
5153 23:05:41.001689 ==
5154 23:05:41.004646 Dram Type= 6, Freq= 0, CH_0, rank 0
5155 23:05:41.007850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5156 23:05:41.007933 ==
5157 23:05:41.011463 [Gating] SW mode calibration
5158 23:05:41.017912 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5159 23:05:41.021070 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5160 23:05:41.028132 0 14 0 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
5161 23:05:41.031483 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5162 23:05:41.034310 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5163 23:05:41.041462 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5164 23:05:41.044645 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5165 23:05:41.047910 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5166 23:05:41.054302 0 14 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
5167 23:05:41.058191 0 14 28 | B1->B0 | 3434 2929 | 1 0 | (0 1) (0 0)
5168 23:05:41.060916 0 15 0 | B1->B0 | 2e2e 2323 | 0 0 | (1 0) (1 0)
5169 23:05:41.067687 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5170 23:05:41.071569 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5171 23:05:41.074731 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5172 23:05:41.081309 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5173 23:05:41.084652 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5174 23:05:41.087845 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5175 23:05:41.094431 0 15 28 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
5176 23:05:41.097604 1 0 0 | B1->B0 | 3b3b 4646 | 1 0 | (0 0) (0 0)
5177 23:05:41.100938 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5178 23:05:41.107184 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5179 23:05:41.110665 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5180 23:05:41.114404 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5181 23:05:41.117454 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5182 23:05:41.124290 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5183 23:05:41.127498 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5184 23:05:41.130687 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5185 23:05:41.137222 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 23:05:41.140345 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 23:05:41.144039 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 23:05:41.150508 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 23:05:41.153769 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 23:05:41.157274 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 23:05:41.163964 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 23:05:41.167100 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 23:05:41.170739 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 23:05:41.177340 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 23:05:41.181029 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 23:05:41.183916 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 23:05:41.191128 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 23:05:41.194321 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 23:05:41.197717 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5200 23:05:41.204189 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5201 23:05:41.204314 Total UI for P1: 0, mck2ui 16
5202 23:05:41.207425 best dqsien dly found for B0: ( 1, 2, 28)
5203 23:05:41.214384 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5204 23:05:41.217762 Total UI for P1: 0, mck2ui 16
5205 23:05:41.220828 best dqsien dly found for B1: ( 1, 3, 0)
5206 23:05:41.224079 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5207 23:05:41.227232 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5208 23:05:41.227336
5209 23:05:41.230567 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5210 23:05:41.233850 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5211 23:05:41.237870 [Gating] SW calibration Done
5212 23:05:41.237954 ==
5213 23:05:41.240850 Dram Type= 6, Freq= 0, CH_0, rank 0
5214 23:05:41.243900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5215 23:05:41.243987 ==
5216 23:05:41.247294 RX Vref Scan: 0
5217 23:05:41.247378
5218 23:05:41.247444 RX Vref 0 -> 0, step: 1
5219 23:05:41.250847
5220 23:05:41.250931 RX Delay -80 -> 252, step: 8
5221 23:05:41.257415 iDelay=200, Bit 0, Center 107 (16 ~ 199) 184
5222 23:05:41.260804 iDelay=200, Bit 1, Center 107 (16 ~ 199) 184
5223 23:05:41.264251 iDelay=200, Bit 2, Center 99 (8 ~ 191) 184
5224 23:05:41.267124 iDelay=200, Bit 3, Center 99 (8 ~ 191) 184
5225 23:05:41.270344 iDelay=200, Bit 4, Center 107 (16 ~ 199) 184
5226 23:05:41.273973 iDelay=200, Bit 5, Center 95 (8 ~ 183) 176
5227 23:05:41.280282 iDelay=200, Bit 6, Center 111 (24 ~ 199) 176
5228 23:05:41.283936 iDelay=200, Bit 7, Center 111 (24 ~ 199) 176
5229 23:05:41.287053 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5230 23:05:41.290296 iDelay=200, Bit 9, Center 83 (-8 ~ 175) 184
5231 23:05:41.293518 iDelay=200, Bit 10, Center 95 (8 ~ 183) 176
5232 23:05:41.297499 iDelay=200, Bit 11, Center 87 (0 ~ 175) 176
5233 23:05:41.303442 iDelay=200, Bit 12, Center 99 (8 ~ 191) 184
5234 23:05:41.306725 iDelay=200, Bit 13, Center 99 (8 ~ 191) 184
5235 23:05:41.310096 iDelay=200, Bit 14, Center 103 (8 ~ 199) 192
5236 23:05:41.313848 iDelay=200, Bit 15, Center 99 (8 ~ 191) 184
5237 23:05:41.313933 ==
5238 23:05:41.317234 Dram Type= 6, Freq= 0, CH_0, rank 0
5239 23:05:41.320352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5240 23:05:41.323645 ==
5241 23:05:41.323728 DQS Delay:
5242 23:05:41.323795 DQS0 = 0, DQS1 = 0
5243 23:05:41.326821 DQM Delay:
5244 23:05:41.326904 DQM0 = 104, DQM1 = 93
5245 23:05:41.330693 DQ Delay:
5246 23:05:41.333930 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5247 23:05:41.337158 DQ4 =107, DQ5 =95, DQ6 =111, DQ7 =111
5248 23:05:41.340353 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5249 23:05:41.343583 DQ12 =99, DQ13 =99, DQ14 =103, DQ15 =99
5250 23:05:41.343685
5251 23:05:41.343768
5252 23:05:41.343842 ==
5253 23:05:41.347219 Dram Type= 6, Freq= 0, CH_0, rank 0
5254 23:05:41.350255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5255 23:05:41.350339 ==
5256 23:05:41.350404
5257 23:05:41.350464
5258 23:05:41.353491 TX Vref Scan disable
5259 23:05:41.353574 == TX Byte 0 ==
5260 23:05:41.360580 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5261 23:05:41.363651 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5262 23:05:41.363735 == TX Byte 1 ==
5263 23:05:41.370411 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5264 23:05:41.373549 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5265 23:05:41.373644 ==
5266 23:05:41.376725 Dram Type= 6, Freq= 0, CH_0, rank 0
5267 23:05:41.380428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5268 23:05:41.380513 ==
5269 23:05:41.380578
5270 23:05:41.383674
5271 23:05:41.383755 TX Vref Scan disable
5272 23:05:41.386550 == TX Byte 0 ==
5273 23:05:41.389855 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5274 23:05:41.393783 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5275 23:05:41.396997 == TX Byte 1 ==
5276 23:05:41.399960 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5277 23:05:41.403531 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5278 23:05:41.407212
5279 23:05:41.407291 [DATLAT]
5280 23:05:41.407355 Freq=933, CH0 RK0
5281 23:05:41.407414
5282 23:05:41.410308 DATLAT Default: 0xd
5283 23:05:41.410388 0, 0xFFFF, sum = 0
5284 23:05:41.413221 1, 0xFFFF, sum = 0
5285 23:05:41.413303 2, 0xFFFF, sum = 0
5286 23:05:41.416829 3, 0xFFFF, sum = 0
5287 23:05:41.416943 4, 0xFFFF, sum = 0
5288 23:05:41.419952 5, 0xFFFF, sum = 0
5289 23:05:41.420035 6, 0xFFFF, sum = 0
5290 23:05:41.423312 7, 0xFFFF, sum = 0
5291 23:05:41.426612 8, 0xFFFF, sum = 0
5292 23:05:41.426696 9, 0xFFFF, sum = 0
5293 23:05:41.430056 10, 0x0, sum = 1
5294 23:05:41.430139 11, 0x0, sum = 2
5295 23:05:41.430237 12, 0x0, sum = 3
5296 23:05:41.432977 13, 0x0, sum = 4
5297 23:05:41.433077 best_step = 11
5298 23:05:41.433175
5299 23:05:41.436933 ==
5300 23:05:41.437031 Dram Type= 6, Freq= 0, CH_0, rank 0
5301 23:05:41.443275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5302 23:05:41.443375 ==
5303 23:05:41.443475 RX Vref Scan: 1
5304 23:05:41.443568
5305 23:05:41.446752 RX Vref 0 -> 0, step: 1
5306 23:05:41.446860
5307 23:05:41.449751 RX Delay -53 -> 252, step: 4
5308 23:05:41.449833
5309 23:05:41.453543 Set Vref, RX VrefLevel [Byte0]: 54
5310 23:05:41.456693 [Byte1]: 53
5311 23:05:41.456775
5312 23:05:41.459876 Final RX Vref Byte 0 = 54 to rank0
5313 23:05:41.463481 Final RX Vref Byte 1 = 53 to rank0
5314 23:05:41.466843 Final RX Vref Byte 0 = 54 to rank1
5315 23:05:41.469853 Final RX Vref Byte 1 = 53 to rank1==
5316 23:05:41.473510 Dram Type= 6, Freq= 0, CH_0, rank 0
5317 23:05:41.476833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5318 23:05:41.476915 ==
5319 23:05:41.479933 DQS Delay:
5320 23:05:41.480014 DQS0 = 0, DQS1 = 0
5321 23:05:41.483115 DQM Delay:
5322 23:05:41.483198 DQM0 = 104, DQM1 = 96
5323 23:05:41.483264 DQ Delay:
5324 23:05:41.486224 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =102
5325 23:05:41.489786 DQ4 =104, DQ5 =94, DQ6 =110, DQ7 =110
5326 23:05:41.492839 DQ8 =86, DQ9 =86, DQ10 =96, DQ11 =92
5327 23:05:41.500018 DQ12 =100, DQ13 =100, DQ14 =104, DQ15 =104
5328 23:05:41.500117
5329 23:05:41.500214
5330 23:05:41.506451 [DQSOSCAuto] RK0, (LSB)MR18= 0x3229, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 406 ps
5331 23:05:41.509413 CH0 RK0: MR19=505, MR18=3229
5332 23:05:41.516180 CH0_RK0: MR19=0x505, MR18=0x3229, DQSOSC=406, MR23=63, INC=65, DEC=43
5333 23:05:41.516281
5334 23:05:41.519452 ----->DramcWriteLeveling(PI) begin...
5335 23:05:41.519535 ==
5336 23:05:41.522757 Dram Type= 6, Freq= 0, CH_0, rank 1
5337 23:05:41.526728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5338 23:05:41.526810 ==
5339 23:05:41.529881 Write leveling (Byte 0): 33 => 33
5340 23:05:41.532941 Write leveling (Byte 1): 28 => 28
5341 23:05:41.536154 DramcWriteLeveling(PI) end<-----
5342 23:05:41.536245
5343 23:05:41.536310 ==
5344 23:05:41.539862 Dram Type= 6, Freq= 0, CH_0, rank 1
5345 23:05:41.542752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5346 23:05:41.542850 ==
5347 23:05:41.546415 [Gating] SW mode calibration
5348 23:05:41.552776 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5349 23:05:41.559328 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5350 23:05:41.563000 0 14 0 | B1->B0 | 3131 3232 | 0 0 | (0 0) (0 0)
5351 23:05:41.569368 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5352 23:05:41.572662 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5353 23:05:41.576522 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5354 23:05:41.582748 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5355 23:05:41.586020 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5356 23:05:41.589706 0 14 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5357 23:05:41.595896 0 14 28 | B1->B0 | 2c2c 2b2b | 0 1 | (0 0) (1 0)
5358 23:05:41.599730 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5359 23:05:41.602997 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5360 23:05:41.606158 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5361 23:05:41.612390 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5362 23:05:41.615699 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5363 23:05:41.619358 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5364 23:05:41.625949 0 15 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5365 23:05:41.629094 0 15 28 | B1->B0 | 3535 3635 | 0 1 | (0 0) (0 0)
5366 23:05:41.633104 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5367 23:05:41.639346 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5368 23:05:41.642589 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5369 23:05:41.645675 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5370 23:05:41.652460 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5371 23:05:41.656174 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5372 23:05:41.659250 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5373 23:05:41.666114 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5374 23:05:41.669317 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 23:05:41.672245 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 23:05:41.679459 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 23:05:41.682285 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 23:05:41.685842 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 23:05:41.692706 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 23:05:41.695980 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 23:05:41.699125 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 23:05:41.705975 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 23:05:41.709266 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 23:05:41.712296 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 23:05:41.719132 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 23:05:41.722415 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 23:05:41.725448 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 23:05:41.731909 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 23:05:41.735666 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5390 23:05:41.739008 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5391 23:05:41.742105 Total UI for P1: 0, mck2ui 16
5392 23:05:41.745451 best dqsien dly found for B1: ( 1, 2, 28)
5393 23:05:41.748602 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5394 23:05:41.751712 Total UI for P1: 0, mck2ui 16
5395 23:05:41.755636 best dqsien dly found for B0: ( 1, 2, 30)
5396 23:05:41.759048 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5397 23:05:41.765084 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5398 23:05:41.765180
5399 23:05:41.768714 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5400 23:05:41.771921 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5401 23:05:41.775122 [Gating] SW calibration Done
5402 23:05:41.775236 ==
5403 23:05:41.778350 Dram Type= 6, Freq= 0, CH_0, rank 1
5404 23:05:41.781599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5405 23:05:41.781715 ==
5406 23:05:41.785462 RX Vref Scan: 0
5407 23:05:41.785544
5408 23:05:41.785620 RX Vref 0 -> 0, step: 1
5409 23:05:41.785683
5410 23:05:41.788385 RX Delay -80 -> 252, step: 8
5411 23:05:41.791898 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5412 23:05:41.798249 iDelay=208, Bit 1, Center 111 (24 ~ 199) 176
5413 23:05:41.801701 iDelay=208, Bit 2, Center 103 (16 ~ 191) 176
5414 23:05:41.805027 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5415 23:05:41.808027 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5416 23:05:41.811273 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5417 23:05:41.814803 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5418 23:05:41.821520 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5419 23:05:41.825376 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5420 23:05:41.827708 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5421 23:05:41.831589 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5422 23:05:41.834477 iDelay=208, Bit 11, Center 91 (8 ~ 175) 168
5423 23:05:41.838202 iDelay=208, Bit 12, Center 103 (16 ~ 191) 176
5424 23:05:41.844903 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5425 23:05:41.847999 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5426 23:05:41.851348 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5427 23:05:41.851429 ==
5428 23:05:41.854561 Dram Type= 6, Freq= 0, CH_0, rank 1
5429 23:05:41.857791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5430 23:05:41.861113 ==
5431 23:05:41.861189 DQS Delay:
5432 23:05:41.861263 DQS0 = 0, DQS1 = 0
5433 23:05:41.864871 DQM Delay:
5434 23:05:41.864948 DQM0 = 106, DQM1 = 96
5435 23:05:41.868123 DQ Delay:
5436 23:05:41.871277 DQ0 =107, DQ1 =111, DQ2 =103, DQ3 =99
5437 23:05:41.874296 DQ4 =107, DQ5 =99, DQ6 =111, DQ7 =115
5438 23:05:41.878340 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =91
5439 23:05:41.881325 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5440 23:05:41.881434
5441 23:05:41.881538
5442 23:05:41.881628 ==
5443 23:05:41.884710 Dram Type= 6, Freq= 0, CH_0, rank 1
5444 23:05:41.887982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5445 23:05:41.888061 ==
5446 23:05:41.888134
5447 23:05:41.888194
5448 23:05:41.891117 TX Vref Scan disable
5449 23:05:41.894337 == TX Byte 0 ==
5450 23:05:41.897850 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5451 23:05:41.901092 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5452 23:05:41.904528 == TX Byte 1 ==
5453 23:05:41.907465 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5454 23:05:41.911176 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5455 23:05:41.911258 ==
5456 23:05:41.914325 Dram Type= 6, Freq= 0, CH_0, rank 1
5457 23:05:41.917481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5458 23:05:41.920629 ==
5459 23:05:41.920704
5460 23:05:41.920768
5461 23:05:41.920836 TX Vref Scan disable
5462 23:05:41.924898 == TX Byte 0 ==
5463 23:05:41.928116 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5464 23:05:41.931294 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5465 23:05:41.934634 == TX Byte 1 ==
5466 23:05:41.938007 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5467 23:05:41.941275 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5468 23:05:41.944957
5469 23:05:41.945041 [DATLAT]
5470 23:05:41.945109 Freq=933, CH0 RK1
5471 23:05:41.945179
5472 23:05:41.947966 DATLAT Default: 0xb
5473 23:05:41.948051 0, 0xFFFF, sum = 0
5474 23:05:41.951129 1, 0xFFFF, sum = 0
5475 23:05:41.951209 2, 0xFFFF, sum = 0
5476 23:05:41.954821 3, 0xFFFF, sum = 0
5477 23:05:41.954902 4, 0xFFFF, sum = 0
5478 23:05:41.958077 5, 0xFFFF, sum = 0
5479 23:05:41.961080 6, 0xFFFF, sum = 0
5480 23:05:41.961173 7, 0xFFFF, sum = 0
5481 23:05:41.965037 8, 0xFFFF, sum = 0
5482 23:05:41.965129 9, 0xFFFF, sum = 0
5483 23:05:41.968408 10, 0x0, sum = 1
5484 23:05:41.968490 11, 0x0, sum = 2
5485 23:05:41.968563 12, 0x0, sum = 3
5486 23:05:41.971449 13, 0x0, sum = 4
5487 23:05:41.971526 best_step = 11
5488 23:05:41.971594
5489 23:05:41.974566 ==
5490 23:05:41.974643 Dram Type= 6, Freq= 0, CH_0, rank 1
5491 23:05:41.981396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5492 23:05:41.981484 ==
5493 23:05:41.981552 RX Vref Scan: 0
5494 23:05:41.981624
5495 23:05:41.984501 RX Vref 0 -> 0, step: 1
5496 23:05:41.984629
5497 23:05:41.987993 RX Delay -45 -> 252, step: 4
5498 23:05:41.991646 iDelay=199, Bit 0, Center 100 (11 ~ 190) 180
5499 23:05:41.998194 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5500 23:05:42.001223 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5501 23:05:42.005213 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5502 23:05:42.008411 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5503 23:05:42.011563 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5504 23:05:42.014748 iDelay=199, Bit 6, Center 108 (23 ~ 194) 172
5505 23:05:42.021503 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5506 23:05:42.025087 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5507 23:05:42.028277 iDelay=199, Bit 9, Center 84 (-1 ~ 170) 172
5508 23:05:42.031640 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5509 23:05:42.034697 iDelay=199, Bit 11, Center 88 (7 ~ 170) 164
5510 23:05:42.041196 iDelay=199, Bit 12, Center 100 (19 ~ 182) 164
5511 23:05:42.044551 iDelay=199, Bit 13, Center 100 (15 ~ 186) 172
5512 23:05:42.047799 iDelay=199, Bit 14, Center 104 (19 ~ 190) 172
5513 23:05:42.051394 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5514 23:05:42.051476 ==
5515 23:05:42.054381 Dram Type= 6, Freq= 0, CH_0, rank 1
5516 23:05:42.057844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5517 23:05:42.061557 ==
5518 23:05:42.061662 DQS Delay:
5519 23:05:42.061731 DQS0 = 0, DQS1 = 0
5520 23:05:42.065284 DQM Delay:
5521 23:05:42.065360 DQM0 = 104, DQM1 = 94
5522 23:05:42.068399 DQ Delay:
5523 23:05:42.071521 DQ0 =100, DQ1 =106, DQ2 =102, DQ3 =102
5524 23:05:42.074456 DQ4 =106, DQ5 =98, DQ6 =108, DQ7 =112
5525 23:05:42.078072 DQ8 =84, DQ9 =84, DQ10 =94, DQ11 =88
5526 23:05:42.081319 DQ12 =100, DQ13 =100, DQ14 =104, DQ15 =102
5527 23:05:42.081423
5528 23:05:42.081523
5529 23:05:42.088234 [DQSOSCAuto] RK1, (LSB)MR18= 0x2b04, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 408 ps
5530 23:05:42.091140 CH0 RK1: MR19=505, MR18=2B04
5531 23:05:42.097667 CH0_RK1: MR19=0x505, MR18=0x2B04, DQSOSC=408, MR23=63, INC=65, DEC=43
5532 23:05:42.101517 [RxdqsGatingPostProcess] freq 933
5533 23:05:42.104564 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5534 23:05:42.107769 best DQS0 dly(2T, 0.5T) = (0, 10)
5535 23:05:42.111076 best DQS1 dly(2T, 0.5T) = (0, 11)
5536 23:05:42.114417 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5537 23:05:42.118362 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5538 23:05:42.120881 best DQS0 dly(2T, 0.5T) = (0, 10)
5539 23:05:42.124644 best DQS1 dly(2T, 0.5T) = (0, 10)
5540 23:05:42.127906 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5541 23:05:42.131282 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5542 23:05:42.134398 Pre-setting of DQS Precalculation
5543 23:05:42.137619 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5544 23:05:42.141446 ==
5545 23:05:42.144613 Dram Type= 6, Freq= 0, CH_1, rank 0
5546 23:05:42.147706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5547 23:05:42.147789 ==
5548 23:05:42.151327 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5549 23:05:42.157385 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5550 23:05:42.161685 [CA 0] Center 36 (6~67) winsize 62
5551 23:05:42.164811 [CA 1] Center 36 (6~67) winsize 62
5552 23:05:42.168092 [CA 2] Center 35 (5~65) winsize 61
5553 23:05:42.171439 [CA 3] Center 34 (4~65) winsize 62
5554 23:05:42.174580 [CA 4] Center 34 (4~65) winsize 62
5555 23:05:42.177916 [CA 5] Center 33 (3~64) winsize 62
5556 23:05:42.177998
5557 23:05:42.181383 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5558 23:05:42.181463
5559 23:05:42.184507 [CATrainingPosCal] consider 1 rank data
5560 23:05:42.187991 u2DelayCellTimex100 = 270/100 ps
5561 23:05:42.191528 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5562 23:05:42.198025 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5563 23:05:42.201165 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5564 23:05:42.204615 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5565 23:05:42.208025 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5566 23:05:42.211124 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5567 23:05:42.211211
5568 23:05:42.214354 CA PerBit enable=1, Macro0, CA PI delay=33
5569 23:05:42.214472
5570 23:05:42.218062 [CBTSetCACLKResult] CA Dly = 33
5571 23:05:42.218198 CS Dly: 6 (0~37)
5572 23:05:42.221157 ==
5573 23:05:42.224916 Dram Type= 6, Freq= 0, CH_1, rank 1
5574 23:05:42.227865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5575 23:05:42.227952 ==
5576 23:05:42.231121 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5577 23:05:42.237737 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5578 23:05:42.241448 [CA 0] Center 36 (6~67) winsize 62
5579 23:05:42.244687 [CA 1] Center 37 (7~68) winsize 62
5580 23:05:42.248469 [CA 2] Center 35 (5~65) winsize 61
5581 23:05:42.251679 [CA 3] Center 34 (4~65) winsize 62
5582 23:05:42.254807 [CA 4] Center 34 (4~65) winsize 62
5583 23:05:42.257813 [CA 5] Center 33 (3~64) winsize 62
5584 23:05:42.257892
5585 23:05:42.261297 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5586 23:05:42.261372
5587 23:05:42.265314 [CATrainingPosCal] consider 2 rank data
5588 23:05:42.268193 u2DelayCellTimex100 = 270/100 ps
5589 23:05:42.271380 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5590 23:05:42.277857 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5591 23:05:42.281127 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5592 23:05:42.284324 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5593 23:05:42.288310 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5594 23:05:42.291451 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5595 23:05:42.291537
5596 23:05:42.294331 CA PerBit enable=1, Macro0, CA PI delay=33
5597 23:05:42.294412
5598 23:05:42.298361 [CBTSetCACLKResult] CA Dly = 33
5599 23:05:42.298447 CS Dly: 7 (0~40)
5600 23:05:42.300965
5601 23:05:42.304741 ----->DramcWriteLeveling(PI) begin...
5602 23:05:42.304826 ==
5603 23:05:42.307882 Dram Type= 6, Freq= 0, CH_1, rank 0
5604 23:05:42.311023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5605 23:05:42.311106 ==
5606 23:05:42.314839 Write leveling (Byte 0): 29 => 29
5607 23:05:42.318129 Write leveling (Byte 1): 27 => 27
5608 23:05:42.321190 DramcWriteLeveling(PI) end<-----
5609 23:05:42.321276
5610 23:05:42.321342 ==
5611 23:05:42.324697 Dram Type= 6, Freq= 0, CH_1, rank 0
5612 23:05:42.327892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5613 23:05:42.327976 ==
5614 23:05:42.331973 [Gating] SW mode calibration
5615 23:05:42.338285 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5616 23:05:42.344543 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5617 23:05:42.347862 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5618 23:05:42.351377 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5619 23:05:42.357699 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5620 23:05:42.360708 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5621 23:05:42.364384 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5622 23:05:42.370644 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5623 23:05:42.374193 0 14 24 | B1->B0 | 3333 2f2f | 1 0 | (1 0) (1 0)
5624 23:05:42.377372 0 14 28 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (1 0)
5625 23:05:42.383849 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5626 23:05:42.387251 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5627 23:05:42.391000 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5628 23:05:42.397479 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5629 23:05:42.400741 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5630 23:05:42.403968 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5631 23:05:42.407830 0 15 24 | B1->B0 | 2525 3434 | 0 0 | (0 0) (0 0)
5632 23:05:42.414116 0 15 28 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
5633 23:05:42.417201 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5634 23:05:42.420467 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5635 23:05:42.427631 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5636 23:05:42.430863 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5637 23:05:42.433848 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5638 23:05:42.440334 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5639 23:05:42.444277 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5640 23:05:42.447495 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5641 23:05:42.453943 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 23:05:42.457179 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 23:05:42.460600 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 23:05:42.467193 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 23:05:42.470457 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 23:05:42.473530 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 23:05:42.480200 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 23:05:42.483637 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5649 23:05:42.486967 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5650 23:05:42.493421 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5651 23:05:42.497018 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 23:05:42.500429 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5653 23:05:42.506930 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5654 23:05:42.510411 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5655 23:05:42.513854 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5656 23:05:42.520124 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5657 23:05:42.520207 Total UI for P1: 0, mck2ui 16
5658 23:05:42.527161 best dqsien dly found for B0: ( 1, 2, 26)
5659 23:05:42.527265 Total UI for P1: 0, mck2ui 16
5660 23:05:42.530483 best dqsien dly found for B1: ( 1, 2, 24)
5661 23:05:42.536954 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5662 23:05:42.540343 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5663 23:05:42.540474
5664 23:05:42.543433 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5665 23:05:42.546622 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5666 23:05:42.549834 [Gating] SW calibration Done
5667 23:05:42.549917 ==
5668 23:05:42.553679 Dram Type= 6, Freq= 0, CH_1, rank 0
5669 23:05:42.556883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5670 23:05:42.557000 ==
5671 23:05:42.560149 RX Vref Scan: 0
5672 23:05:42.560246
5673 23:05:42.560345 RX Vref 0 -> 0, step: 1
5674 23:05:42.560488
5675 23:05:42.563525 RX Delay -80 -> 252, step: 8
5676 23:05:42.566811 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5677 23:05:42.573215 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5678 23:05:42.576544 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5679 23:05:42.580236 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5680 23:05:42.583434 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5681 23:05:42.586394 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5682 23:05:42.590360 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5683 23:05:42.593521 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5684 23:05:42.599826 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5685 23:05:42.603283 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5686 23:05:42.606687 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5687 23:05:42.609890 iDelay=208, Bit 11, Center 95 (8 ~ 183) 176
5688 23:05:42.613017 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5689 23:05:42.620007 iDelay=208, Bit 13, Center 107 (24 ~ 191) 168
5690 23:05:42.623421 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5691 23:05:42.626279 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5692 23:05:42.626359 ==
5693 23:05:42.630140 Dram Type= 6, Freq= 0, CH_1, rank 0
5694 23:05:42.633247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5695 23:05:42.633329 ==
5696 23:05:42.636290 DQS Delay:
5697 23:05:42.636372 DQS0 = 0, DQS1 = 0
5698 23:05:42.639754 DQM Delay:
5699 23:05:42.639834 DQM0 = 102, DQM1 = 99
5700 23:05:42.639920 DQ Delay:
5701 23:05:42.643105 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5702 23:05:42.646436 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =103
5703 23:05:42.649526 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =95
5704 23:05:42.656844 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5705 23:05:42.656933
5706 23:05:42.657010
5707 23:05:42.657121 ==
5708 23:05:42.659650 Dram Type= 6, Freq= 0, CH_1, rank 0
5709 23:05:42.663087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5710 23:05:42.663199 ==
5711 23:05:42.663298
5712 23:05:42.663388
5713 23:05:42.666321 TX Vref Scan disable
5714 23:05:42.666399 == TX Byte 0 ==
5715 23:05:42.673551 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5716 23:05:42.676686 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5717 23:05:42.676764 == TX Byte 1 ==
5718 23:05:42.683190 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5719 23:05:42.686203 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5720 23:05:42.686280 ==
5721 23:05:42.689471 Dram Type= 6, Freq= 0, CH_1, rank 0
5722 23:05:42.693104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5723 23:05:42.693208 ==
5724 23:05:42.693299
5725 23:05:42.693399
5726 23:05:42.696521 TX Vref Scan disable
5727 23:05:42.699609 == TX Byte 0 ==
5728 23:05:42.702582 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5729 23:05:42.705969 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5730 23:05:42.709265 == TX Byte 1 ==
5731 23:05:42.712554 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5732 23:05:42.716344 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5733 23:05:42.716421
5734 23:05:42.719570 [DATLAT]
5735 23:05:42.719641 Freq=933, CH1 RK0
5736 23:05:42.719723
5737 23:05:42.722854 DATLAT Default: 0xd
5738 23:05:42.722928 0, 0xFFFF, sum = 0
5739 23:05:42.726010 1, 0xFFFF, sum = 0
5740 23:05:42.726096 2, 0xFFFF, sum = 0
5741 23:05:42.729329 3, 0xFFFF, sum = 0
5742 23:05:42.729426 4, 0xFFFF, sum = 0
5743 23:05:42.732727 5, 0xFFFF, sum = 0
5744 23:05:42.732798 6, 0xFFFF, sum = 0
5745 23:05:42.735938 7, 0xFFFF, sum = 0
5746 23:05:42.736041 8, 0xFFFF, sum = 0
5747 23:05:42.739137 9, 0xFFFF, sum = 0
5748 23:05:42.739229 10, 0x0, sum = 1
5749 23:05:42.742834 11, 0x0, sum = 2
5750 23:05:42.742909 12, 0x0, sum = 3
5751 23:05:42.746166 13, 0x0, sum = 4
5752 23:05:42.746289 best_step = 11
5753 23:05:42.746359
5754 23:05:42.746422 ==
5755 23:05:42.749244 Dram Type= 6, Freq= 0, CH_1, rank 0
5756 23:05:42.755901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5757 23:05:42.756015 ==
5758 23:05:42.756109 RX Vref Scan: 1
5759 23:05:42.756208
5760 23:05:42.759110 RX Vref 0 -> 0, step: 1
5761 23:05:42.759212
5762 23:05:42.762780 RX Delay -45 -> 252, step: 4
5763 23:05:42.762880
5764 23:05:42.765764 Set Vref, RX VrefLevel [Byte0]: 57
5765 23:05:42.769421 [Byte1]: 53
5766 23:05:42.769521
5767 23:05:42.772652 Final RX Vref Byte 0 = 57 to rank0
5768 23:05:42.776041 Final RX Vref Byte 1 = 53 to rank0
5769 23:05:42.779101 Final RX Vref Byte 0 = 57 to rank1
5770 23:05:42.782591 Final RX Vref Byte 1 = 53 to rank1==
5771 23:05:42.785991 Dram Type= 6, Freq= 0, CH_1, rank 0
5772 23:05:42.789571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5773 23:05:42.789660 ==
5774 23:05:42.792582 DQS Delay:
5775 23:05:42.792683 DQS0 = 0, DQS1 = 0
5776 23:05:42.792774 DQM Delay:
5777 23:05:42.795955 DQM0 = 103, DQM1 = 99
5778 23:05:42.796063 DQ Delay:
5779 23:05:42.799272 DQ0 =106, DQ1 =98, DQ2 =94, DQ3 =100
5780 23:05:42.803032 DQ4 =102, DQ5 =112, DQ6 =114, DQ7 =102
5781 23:05:42.806238 DQ8 =88, DQ9 =90, DQ10 =100, DQ11 =92
5782 23:05:42.809381 DQ12 =108, DQ13 =104, DQ14 =108, DQ15 =106
5783 23:05:42.809485
5784 23:05:42.812786
5785 23:05:42.819276 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b33, (MSB)MR19= 0x505, tDQSOscB0 = 405 ps tDQSOscB1 = 413 ps
5786 23:05:42.823052 CH1 RK0: MR19=505, MR18=1B33
5787 23:05:42.829501 CH1_RK0: MR19=0x505, MR18=0x1B33, DQSOSC=405, MR23=63, INC=66, DEC=44
5788 23:05:42.829623
5789 23:05:42.832655 ----->DramcWriteLeveling(PI) begin...
5790 23:05:42.832756 ==
5791 23:05:42.835936 Dram Type= 6, Freq= 0, CH_1, rank 1
5792 23:05:42.839808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5793 23:05:42.839882 ==
5794 23:05:42.842892 Write leveling (Byte 0): 25 => 25
5795 23:05:42.846265 Write leveling (Byte 1): 28 => 28
5796 23:05:42.849278 DramcWriteLeveling(PI) end<-----
5797 23:05:42.849359
5798 23:05:42.849434 ==
5799 23:05:42.852600 Dram Type= 6, Freq= 0, CH_1, rank 1
5800 23:05:42.855722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5801 23:05:42.855831 ==
5802 23:05:42.859106 [Gating] SW mode calibration
5803 23:05:42.866059 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5804 23:05:42.872480 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5805 23:05:42.875566 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5806 23:05:42.879570 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5807 23:05:42.885784 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5808 23:05:42.888821 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5809 23:05:42.892381 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5810 23:05:42.899132 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5811 23:05:42.902243 0 14 24 | B1->B0 | 2e2e 3030 | 0 0 | (0 0) (0 1)
5812 23:05:42.905600 0 14 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5813 23:05:42.912427 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5814 23:05:42.916076 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5815 23:05:42.919143 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5816 23:05:42.925655 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5817 23:05:42.928757 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5818 23:05:42.932158 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5819 23:05:42.938975 0 15 24 | B1->B0 | 3737 2e2e | 0 1 | (0 0) (0 0)
5820 23:05:42.942288 0 15 28 | B1->B0 | 4646 4141 | 0 0 | (0 0) (0 0)
5821 23:05:42.945705 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5822 23:05:42.949080 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5823 23:05:42.955560 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5824 23:05:42.958706 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5825 23:05:42.962578 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5826 23:05:42.968868 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5827 23:05:42.972665 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5828 23:05:42.975803 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5829 23:05:42.982122 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5830 23:05:42.985758 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5831 23:05:42.988716 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5832 23:05:42.995482 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5833 23:05:42.999102 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5834 23:05:43.002384 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5835 23:05:43.008572 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5836 23:05:43.012272 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5837 23:05:43.015685 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5838 23:05:43.022210 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5839 23:05:43.025434 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5840 23:05:43.029049 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5841 23:05:43.035516 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5842 23:05:43.039042 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5843 23:05:43.042404 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5844 23:05:43.049058 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5845 23:05:43.049166 Total UI for P1: 0, mck2ui 16
5846 23:05:43.055581 best dqsien dly found for B0: ( 1, 2, 24)
5847 23:05:43.055693 Total UI for P1: 0, mck2ui 16
5848 23:05:43.058611 best dqsien dly found for B1: ( 1, 2, 24)
5849 23:05:43.065173 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5850 23:05:43.068444 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5851 23:05:43.068561
5852 23:05:43.071751 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5853 23:05:43.075522 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5854 23:05:43.078647 [Gating] SW calibration Done
5855 23:05:43.078721 ==
5856 23:05:43.082043 Dram Type= 6, Freq= 0, CH_1, rank 1
5857 23:05:43.085317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5858 23:05:43.085390 ==
5859 23:05:43.088460 RX Vref Scan: 0
5860 23:05:43.088532
5861 23:05:43.088614 RX Vref 0 -> 0, step: 1
5862 23:05:43.088676
5863 23:05:43.092327 RX Delay -80 -> 252, step: 8
5864 23:05:43.095136 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5865 23:05:43.098456 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5866 23:05:43.105719 iDelay=208, Bit 2, Center 95 (8 ~ 183) 176
5867 23:05:43.108554 iDelay=208, Bit 3, Center 95 (8 ~ 183) 176
5868 23:05:43.111945 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5869 23:05:43.115284 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5870 23:05:43.119173 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5871 23:05:43.122292 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5872 23:05:43.128806 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5873 23:05:43.132035 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5874 23:05:43.135193 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5875 23:05:43.138340 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5876 23:05:43.141697 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5877 23:05:43.145384 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5878 23:05:43.151651 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5879 23:05:43.155037 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5880 23:05:43.155145 ==
5881 23:05:43.158607 Dram Type= 6, Freq= 0, CH_1, rank 1
5882 23:05:43.161663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5883 23:05:43.161744 ==
5884 23:05:43.165403 DQS Delay:
5885 23:05:43.165507 DQS0 = 0, DQS1 = 0
5886 23:05:43.165605 DQM Delay:
5887 23:05:43.168332 DQM0 = 102, DQM1 = 98
5888 23:05:43.168430 DQ Delay:
5889 23:05:43.171809 DQ0 =107, DQ1 =99, DQ2 =95, DQ3 =95
5890 23:05:43.175026 DQ4 =95, DQ5 =115, DQ6 =115, DQ7 =99
5891 23:05:43.178172 DQ8 =87, DQ9 =91, DQ10 =99, DQ11 =91
5892 23:05:43.181804 DQ12 =107, DQ13 =107, DQ14 =99, DQ15 =107
5893 23:05:43.181881
5894 23:05:43.181944
5895 23:05:43.184985 ==
5896 23:05:43.185086 Dram Type= 6, Freq= 0, CH_1, rank 1
5897 23:05:43.191734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5898 23:05:43.191874 ==
5899 23:05:43.191979
5900 23:05:43.192053
5901 23:05:43.192115 TX Vref Scan disable
5902 23:05:43.195704 == TX Byte 0 ==
5903 23:05:43.199132 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5904 23:05:43.205947 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5905 23:05:43.206030 == TX Byte 1 ==
5906 23:05:43.209166 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5907 23:05:43.212558 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5908 23:05:43.215505 ==
5909 23:05:43.219034 Dram Type= 6, Freq= 0, CH_1, rank 1
5910 23:05:43.222418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5911 23:05:43.222501 ==
5912 23:05:43.222574
5913 23:05:43.222637
5914 23:05:43.225857 TX Vref Scan disable
5915 23:05:43.225960 == TX Byte 0 ==
5916 23:05:43.232249 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5917 23:05:43.235439 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5918 23:05:43.235551 == TX Byte 1 ==
5919 23:05:43.242388 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5920 23:05:43.245848 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5921 23:05:43.245982
5922 23:05:43.246104 [DATLAT]
5923 23:05:43.248788 Freq=933, CH1 RK1
5924 23:05:43.248927
5925 23:05:43.249021 DATLAT Default: 0xb
5926 23:05:43.252025 0, 0xFFFF, sum = 0
5927 23:05:43.252180 1, 0xFFFF, sum = 0
5928 23:05:43.255245 2, 0xFFFF, sum = 0
5929 23:05:43.255354 3, 0xFFFF, sum = 0
5930 23:05:43.259201 4, 0xFFFF, sum = 0
5931 23:05:43.259312 5, 0xFFFF, sum = 0
5932 23:05:43.262329 6, 0xFFFF, sum = 0
5933 23:05:43.262437 7, 0xFFFF, sum = 0
5934 23:05:43.265556 8, 0xFFFF, sum = 0
5935 23:05:43.268504 9, 0xFFFF, sum = 0
5936 23:05:43.268610 10, 0x0, sum = 1
5937 23:05:43.268704 11, 0x0, sum = 2
5938 23:05:43.272395 12, 0x0, sum = 3
5939 23:05:43.272513 13, 0x0, sum = 4
5940 23:05:43.275743 best_step = 11
5941 23:05:43.275847
5942 23:05:43.275944 ==
5943 23:05:43.278805 Dram Type= 6, Freq= 0, CH_1, rank 1
5944 23:05:43.282029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5945 23:05:43.282106 ==
5946 23:05:43.285265 RX Vref Scan: 0
5947 23:05:43.285357
5948 23:05:43.285449 RX Vref 0 -> 0, step: 1
5949 23:05:43.285538
5950 23:05:43.288941 RX Delay -45 -> 252, step: 4
5951 23:05:43.295754 iDelay=203, Bit 0, Center 110 (27 ~ 194) 168
5952 23:05:43.299053 iDelay=203, Bit 1, Center 102 (19 ~ 186) 168
5953 23:05:43.302673 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5954 23:05:43.305912 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5955 23:05:43.309469 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5956 23:05:43.316100 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5957 23:05:43.318991 iDelay=203, Bit 6, Center 112 (27 ~ 198) 172
5958 23:05:43.322498 iDelay=203, Bit 7, Center 104 (19 ~ 190) 172
5959 23:05:43.325867 iDelay=203, Bit 8, Center 90 (7 ~ 174) 168
5960 23:05:43.329070 iDelay=203, Bit 9, Center 90 (3 ~ 178) 176
5961 23:05:43.335819 iDelay=203, Bit 10, Center 100 (15 ~ 186) 172
5962 23:05:43.338756 iDelay=203, Bit 11, Center 94 (11 ~ 178) 168
5963 23:05:43.342606 iDelay=203, Bit 12, Center 110 (23 ~ 198) 176
5964 23:05:43.345784 iDelay=203, Bit 13, Center 106 (23 ~ 190) 168
5965 23:05:43.349032 iDelay=203, Bit 14, Center 106 (23 ~ 190) 168
5966 23:05:43.355591 iDelay=203, Bit 15, Center 108 (23 ~ 194) 172
5967 23:05:43.355702 ==
5968 23:05:43.359360 Dram Type= 6, Freq= 0, CH_1, rank 1
5969 23:05:43.362612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5970 23:05:43.362716 ==
5971 23:05:43.362813 DQS Delay:
5972 23:05:43.365613 DQS0 = 0, DQS1 = 0
5973 23:05:43.365691 DQM Delay:
5974 23:05:43.369016 DQM0 = 105, DQM1 = 100
5975 23:05:43.369099 DQ Delay:
5976 23:05:43.372955 DQ0 =110, DQ1 =102, DQ2 =94, DQ3 =100
5977 23:05:43.375860 DQ4 =100, DQ5 =118, DQ6 =112, DQ7 =104
5978 23:05:43.379239 DQ8 =90, DQ9 =90, DQ10 =100, DQ11 =94
5979 23:05:43.382390 DQ12 =110, DQ13 =106, DQ14 =106, DQ15 =108
5980 23:05:43.382471
5981 23:05:43.382535
5982 23:05:43.392100 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f02, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 407 ps
5983 23:05:43.395531 CH1 RK1: MR19=505, MR18=2F02
5984 23:05:43.398531 CH1_RK1: MR19=0x505, MR18=0x2F02, DQSOSC=407, MR23=63, INC=65, DEC=43
5985 23:05:43.402183 [RxdqsGatingPostProcess] freq 933
5986 23:05:43.408639 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5987 23:05:43.412221 best DQS0 dly(2T, 0.5T) = (0, 10)
5988 23:05:43.415571 best DQS1 dly(2T, 0.5T) = (0, 10)
5989 23:05:43.418829 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5990 23:05:43.422063 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5991 23:05:43.425348 best DQS0 dly(2T, 0.5T) = (0, 10)
5992 23:05:43.428612 best DQS1 dly(2T, 0.5T) = (0, 10)
5993 23:05:43.432280 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5994 23:05:43.435488 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5995 23:05:43.438729 Pre-setting of DQS Precalculation
5996 23:05:43.441797 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5997 23:05:43.448686 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5998 23:05:43.455346 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5999 23:05:43.455462
6000 23:05:43.455557
6001 23:05:43.458392 [Calibration Summary] 1866 Mbps
6002 23:05:43.462092 CH 0, Rank 0
6003 23:05:43.462179 SW Impedance : PASS
6004 23:05:43.465356 DUTY Scan : NO K
6005 23:05:43.468437 ZQ Calibration : PASS
6006 23:05:43.468522 Jitter Meter : NO K
6007 23:05:43.471749 CBT Training : PASS
6008 23:05:43.475346 Write leveling : PASS
6009 23:05:43.475424 RX DQS gating : PASS
6010 23:05:43.478415 RX DQ/DQS(RDDQC) : PASS
6011 23:05:43.481782 TX DQ/DQS : PASS
6012 23:05:43.481867 RX DATLAT : PASS
6013 23:05:43.485132 RX DQ/DQS(Engine): PASS
6014 23:05:43.485213 TX OE : NO K
6015 23:05:43.488340 All Pass.
6016 23:05:43.488424
6017 23:05:43.488490 CH 0, Rank 1
6018 23:05:43.491542 SW Impedance : PASS
6019 23:05:43.491626 DUTY Scan : NO K
6020 23:05:43.495377 ZQ Calibration : PASS
6021 23:05:43.498434 Jitter Meter : NO K
6022 23:05:43.498515 CBT Training : PASS
6023 23:05:43.501760 Write leveling : PASS
6024 23:05:43.504992 RX DQS gating : PASS
6025 23:05:43.505072 RX DQ/DQS(RDDQC) : PASS
6026 23:05:43.508369 TX DQ/DQS : PASS
6027 23:05:43.512022 RX DATLAT : PASS
6028 23:05:43.512109 RX DQ/DQS(Engine): PASS
6029 23:05:43.514799 TX OE : NO K
6030 23:05:43.514886 All Pass.
6031 23:05:43.514954
6032 23:05:43.518436 CH 1, Rank 0
6033 23:05:43.518519 SW Impedance : PASS
6034 23:05:43.521603 DUTY Scan : NO K
6035 23:05:43.525031 ZQ Calibration : PASS
6036 23:05:43.525111 Jitter Meter : NO K
6037 23:05:43.528271 CBT Training : PASS
6038 23:05:43.531618 Write leveling : PASS
6039 23:05:43.531696 RX DQS gating : PASS
6040 23:05:43.535164 RX DQ/DQS(RDDQC) : PASS
6041 23:05:43.535245 TX DQ/DQS : PASS
6042 23:05:43.538654 RX DATLAT : PASS
6043 23:05:43.541427 RX DQ/DQS(Engine): PASS
6044 23:05:43.541506 TX OE : NO K
6045 23:05:43.545387 All Pass.
6046 23:05:43.545468
6047 23:05:43.545542 CH 1, Rank 1
6048 23:05:43.548414 SW Impedance : PASS
6049 23:05:43.548497 DUTY Scan : NO K
6050 23:05:43.551632 ZQ Calibration : PASS
6051 23:05:43.554922 Jitter Meter : NO K
6052 23:05:43.555009 CBT Training : PASS
6053 23:05:43.558455 Write leveling : PASS
6054 23:05:43.561810 RX DQS gating : PASS
6055 23:05:43.561891 RX DQ/DQS(RDDQC) : PASS
6056 23:05:43.565136 TX DQ/DQS : PASS
6057 23:05:43.568670 RX DATLAT : PASS
6058 23:05:43.568751 RX DQ/DQS(Engine): PASS
6059 23:05:43.571467 TX OE : NO K
6060 23:05:43.571548 All Pass.
6061 23:05:43.571615
6062 23:05:43.574924 DramC Write-DBI off
6063 23:05:43.578278 PER_BANK_REFRESH: Hybrid Mode
6064 23:05:43.578363 TX_TRACKING: ON
6065 23:05:43.588211 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6066 23:05:43.591959 [FAST_K] Save calibration result to emmc
6067 23:05:43.594934 dramc_set_vcore_voltage set vcore to 650000
6068 23:05:43.598550 Read voltage for 400, 6
6069 23:05:43.598654 Vio18 = 0
6070 23:05:43.598788 Vcore = 650000
6071 23:05:43.601757 Vdram = 0
6072 23:05:43.601832 Vddq = 0
6073 23:05:43.601897 Vmddr = 0
6074 23:05:43.608233 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6075 23:05:43.611375 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6076 23:05:43.614711 MEM_TYPE=3, freq_sel=20
6077 23:05:43.618544 sv_algorithm_assistance_LP4_800
6078 23:05:43.621687 ============ PULL DRAM RESETB DOWN ============
6079 23:05:43.624982 ========== PULL DRAM RESETB DOWN end =========
6080 23:05:43.631671 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6081 23:05:43.634778 ===================================
6082 23:05:43.634865 LPDDR4 DRAM CONFIGURATION
6083 23:05:43.638097 ===================================
6084 23:05:43.641233 EX_ROW_EN[0] = 0x0
6085 23:05:43.644783 EX_ROW_EN[1] = 0x0
6086 23:05:43.644889 LP4Y_EN = 0x0
6087 23:05:43.648382 WORK_FSP = 0x0
6088 23:05:43.648486 WL = 0x2
6089 23:05:43.651260 RL = 0x2
6090 23:05:43.651361 BL = 0x2
6091 23:05:43.655067 RPST = 0x0
6092 23:05:43.655168 RD_PRE = 0x0
6093 23:05:43.658458 WR_PRE = 0x1
6094 23:05:43.658564 WR_PST = 0x0
6095 23:05:43.661649 DBI_WR = 0x0
6096 23:05:43.661738 DBI_RD = 0x0
6097 23:05:43.664874 OTF = 0x1
6098 23:05:43.668112 ===================================
6099 23:05:43.671342 ===================================
6100 23:05:43.671444 ANA top config
6101 23:05:43.674593 ===================================
6102 23:05:43.678346 DLL_ASYNC_EN = 0
6103 23:05:43.681266 ALL_SLAVE_EN = 1
6104 23:05:43.681348 NEW_RANK_MODE = 1
6105 23:05:43.685126 DLL_IDLE_MODE = 1
6106 23:05:43.688348 LP45_APHY_COMB_EN = 1
6107 23:05:43.691536 TX_ODT_DIS = 1
6108 23:05:43.694832 NEW_8X_MODE = 1
6109 23:05:43.697998 ===================================
6110 23:05:43.701464 ===================================
6111 23:05:43.701564 data_rate = 800
6112 23:05:43.704701 CKR = 1
6113 23:05:43.708113 DQ_P2S_RATIO = 4
6114 23:05:43.711709 ===================================
6115 23:05:43.714617 CA_P2S_RATIO = 4
6116 23:05:43.718337 DQ_CA_OPEN = 0
6117 23:05:43.721259 DQ_SEMI_OPEN = 1
6118 23:05:43.721341 CA_SEMI_OPEN = 1
6119 23:05:43.724587 CA_FULL_RATE = 0
6120 23:05:43.727830 DQ_CKDIV4_EN = 0
6121 23:05:43.731684 CA_CKDIV4_EN = 1
6122 23:05:43.734481 CA_PREDIV_EN = 0
6123 23:05:43.738249 PH8_DLY = 0
6124 23:05:43.738353 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6125 23:05:43.741124 DQ_AAMCK_DIV = 0
6126 23:05:43.745026 CA_AAMCK_DIV = 0
6127 23:05:43.748054 CA_ADMCK_DIV = 4
6128 23:05:43.751405 DQ_TRACK_CA_EN = 0
6129 23:05:43.755008 CA_PICK = 800
6130 23:05:43.755116 CA_MCKIO = 400
6131 23:05:43.757960 MCKIO_SEMI = 400
6132 23:05:43.761169 PLL_FREQ = 3016
6133 23:05:43.764353 DQ_UI_PI_RATIO = 32
6134 23:05:43.767550 CA_UI_PI_RATIO = 32
6135 23:05:43.770848 ===================================
6136 23:05:43.774561 ===================================
6137 23:05:43.777964 memory_type:LPDDR4
6138 23:05:43.778045 GP_NUM : 10
6139 23:05:43.780642 SRAM_EN : 1
6140 23:05:43.784253 MD32_EN : 0
6141 23:05:43.787817 ===================================
6142 23:05:43.787920 [ANA_INIT] >>>>>>>>>>>>>>
6143 23:05:43.790976 <<<<<< [CONFIGURE PHASE]: ANA_TX
6144 23:05:43.794193 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6145 23:05:43.797374 ===================================
6146 23:05:43.800730 data_rate = 800,PCW = 0X7400
6147 23:05:43.803990 ===================================
6148 23:05:43.807135 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6149 23:05:43.813753 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6150 23:05:43.823973 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6151 23:05:43.830799 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6152 23:05:43.833809 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6153 23:05:43.836912 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6154 23:05:43.836991 [ANA_INIT] flow start
6155 23:05:43.840240 [ANA_INIT] PLL >>>>>>>>
6156 23:05:43.843738 [ANA_INIT] PLL <<<<<<<<
6157 23:05:43.843831 [ANA_INIT] MIDPI >>>>>>>>
6158 23:05:43.846632 [ANA_INIT] MIDPI <<<<<<<<
6159 23:05:43.849921 [ANA_INIT] DLL >>>>>>>>
6160 23:05:43.850000 [ANA_INIT] flow end
6161 23:05:43.856472 ============ LP4 DIFF to SE enter ============
6162 23:05:43.859838 ============ LP4 DIFF to SE exit ============
6163 23:05:43.863358 [ANA_INIT] <<<<<<<<<<<<<
6164 23:05:43.866746 [Flow] Enable top DCM control >>>>>
6165 23:05:43.869906 [Flow] Enable top DCM control <<<<<
6166 23:05:43.869988 Enable DLL master slave shuffle
6167 23:05:43.876818 ==============================================================
6168 23:05:43.880092 Gating Mode config
6169 23:05:43.883190 ==============================================================
6170 23:05:43.886508 Config description:
6171 23:05:43.896828 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6172 23:05:43.903196 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6173 23:05:43.906415 SELPH_MODE 0: By rank 1: By Phase
6174 23:05:43.912909 ==============================================================
6175 23:05:43.916178 GAT_TRACK_EN = 0
6176 23:05:43.919434 RX_GATING_MODE = 2
6177 23:05:43.923380 RX_GATING_TRACK_MODE = 2
6178 23:05:43.926592 SELPH_MODE = 1
6179 23:05:43.926665 PICG_EARLY_EN = 1
6180 23:05:43.929821 VALID_LAT_VALUE = 1
6181 23:05:43.936361 ==============================================================
6182 23:05:43.939428 Enter into Gating configuration >>>>
6183 23:05:43.943652 Exit from Gating configuration <<<<
6184 23:05:43.946091 Enter into DVFS_PRE_config >>>>>
6185 23:05:43.956057 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6186 23:05:43.959600 Exit from DVFS_PRE_config <<<<<
6187 23:05:43.963099 Enter into PICG configuration >>>>
6188 23:05:43.966103 Exit from PICG configuration <<<<
6189 23:05:43.969704 [RX_INPUT] configuration >>>>>
6190 23:05:43.972762 [RX_INPUT] configuration <<<<<
6191 23:05:43.976621 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6192 23:05:43.982573 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6193 23:05:43.989224 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6194 23:05:43.995832 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6195 23:05:44.002870 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6196 23:05:44.006349 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6197 23:05:44.012656 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6198 23:05:44.015961 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6199 23:05:44.019829 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6200 23:05:44.023047 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6201 23:05:44.029647 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6202 23:05:44.032761 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6203 23:05:44.036020 ===================================
6204 23:05:44.039229 LPDDR4 DRAM CONFIGURATION
6205 23:05:44.042521 ===================================
6206 23:05:44.042611 EX_ROW_EN[0] = 0x0
6207 23:05:44.045678 EX_ROW_EN[1] = 0x0
6208 23:05:44.045761 LP4Y_EN = 0x0
6209 23:05:44.049279 WORK_FSP = 0x0
6210 23:05:44.049370 WL = 0x2
6211 23:05:44.052679 RL = 0x2
6212 23:05:44.052762 BL = 0x2
6213 23:05:44.055813 RPST = 0x0
6214 23:05:44.055885 RD_PRE = 0x0
6215 23:05:44.059012 WR_PRE = 0x1
6216 23:05:44.059088 WR_PST = 0x0
6217 23:05:44.062288 DBI_WR = 0x0
6218 23:05:44.065526 DBI_RD = 0x0
6219 23:05:44.065623 OTF = 0x1
6220 23:05:44.069156 ===================================
6221 23:05:44.072384 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6222 23:05:44.076131 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6223 23:05:44.082624 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6224 23:05:44.085983 ===================================
6225 23:05:44.089181 LPDDR4 DRAM CONFIGURATION
6226 23:05:44.092564 ===================================
6227 23:05:44.092642 EX_ROW_EN[0] = 0x10
6228 23:05:44.095568 EX_ROW_EN[1] = 0x0
6229 23:05:44.095647 LP4Y_EN = 0x0
6230 23:05:44.098822 WORK_FSP = 0x0
6231 23:05:44.098896 WL = 0x2
6232 23:05:44.102674 RL = 0x2
6233 23:05:44.102749 BL = 0x2
6234 23:05:44.105874 RPST = 0x0
6235 23:05:44.105947 RD_PRE = 0x0
6236 23:05:44.109072 WR_PRE = 0x1
6237 23:05:44.109145 WR_PST = 0x0
6238 23:05:44.112588 DBI_WR = 0x0
6239 23:05:44.112663 DBI_RD = 0x0
6240 23:05:44.115425 OTF = 0x1
6241 23:05:44.118739 ===================================
6242 23:05:44.126056 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6243 23:05:44.128800 nWR fixed to 30
6244 23:05:44.132001 [ModeRegInit_LP4] CH0 RK0
6245 23:05:44.132071 [ModeRegInit_LP4] CH0 RK1
6246 23:05:44.135392 [ModeRegInit_LP4] CH1 RK0
6247 23:05:44.139356 [ModeRegInit_LP4] CH1 RK1
6248 23:05:44.139433 match AC timing 19
6249 23:05:44.145875 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6250 23:05:44.148803 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6251 23:05:44.152538 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6252 23:05:44.158819 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6253 23:05:44.162459 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6254 23:05:44.162536 ==
6255 23:05:44.165692 Dram Type= 6, Freq= 0, CH_0, rank 0
6256 23:05:44.168900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6257 23:05:44.168977 ==
6258 23:05:44.175074 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6259 23:05:44.182013 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6260 23:05:44.185290 [CA 0] Center 36 (8~64) winsize 57
6261 23:05:44.188930 [CA 1] Center 36 (8~64) winsize 57
6262 23:05:44.192096 [CA 2] Center 36 (8~64) winsize 57
6263 23:05:44.192214 [CA 3] Center 36 (8~64) winsize 57
6264 23:05:44.195135 [CA 4] Center 36 (8~64) winsize 57
6265 23:05:44.198724 [CA 5] Center 36 (8~64) winsize 57
6266 23:05:44.198812
6267 23:05:44.201838 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6268 23:05:44.205346
6269 23:05:44.208943 [CATrainingPosCal] consider 1 rank data
6270 23:05:44.209019 u2DelayCellTimex100 = 270/100 ps
6271 23:05:44.215376 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6272 23:05:44.218441 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6273 23:05:44.221849 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6274 23:05:44.225491 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6275 23:05:44.228402 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6276 23:05:44.232120 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6277 23:05:44.232227
6278 23:05:44.235242 CA PerBit enable=1, Macro0, CA PI delay=36
6279 23:05:44.235316
6280 23:05:44.238447 [CBTSetCACLKResult] CA Dly = 36
6281 23:05:44.242332 CS Dly: 1 (0~32)
6282 23:05:44.242405 ==
6283 23:05:44.245042 Dram Type= 6, Freq= 0, CH_0, rank 1
6284 23:05:44.248137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6285 23:05:44.248248 ==
6286 23:05:44.255024 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6287 23:05:44.258451 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6288 23:05:44.261396 [CA 0] Center 36 (8~64) winsize 57
6289 23:05:44.265211 [CA 1] Center 36 (8~64) winsize 57
6290 23:05:44.268718 [CA 2] Center 36 (8~64) winsize 57
6291 23:05:44.272077 [CA 3] Center 36 (8~64) winsize 57
6292 23:05:44.275195 [CA 4] Center 36 (8~64) winsize 57
6293 23:05:44.278319 [CA 5] Center 36 (8~64) winsize 57
6294 23:05:44.278396
6295 23:05:44.281904 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6296 23:05:44.282010
6297 23:05:44.285113 [CATrainingPosCal] consider 2 rank data
6298 23:05:44.288540 u2DelayCellTimex100 = 270/100 ps
6299 23:05:44.292174 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6300 23:05:44.295257 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6301 23:05:44.298329 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6302 23:05:44.304808 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6303 23:05:44.307893 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6304 23:05:44.311351 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6305 23:05:44.311454
6306 23:05:44.315020 CA PerBit enable=1, Macro0, CA PI delay=36
6307 23:05:44.315130
6308 23:05:44.318285 [CBTSetCACLKResult] CA Dly = 36
6309 23:05:44.318360 CS Dly: 1 (0~32)
6310 23:05:44.318422
6311 23:05:44.321827 ----->DramcWriteLeveling(PI) begin...
6312 23:05:44.324871 ==
6313 23:05:44.324949 Dram Type= 6, Freq= 0, CH_0, rank 0
6314 23:05:44.331270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6315 23:05:44.331347 ==
6316 23:05:44.334939 Write leveling (Byte 0): 40 => 8
6317 23:05:44.338144 Write leveling (Byte 1): 40 => 8
6318 23:05:44.338221 DramcWriteLeveling(PI) end<-----
6319 23:05:44.341410
6320 23:05:44.341484 ==
6321 23:05:44.344694 Dram Type= 6, Freq= 0, CH_0, rank 0
6322 23:05:44.347929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6323 23:05:44.348007 ==
6324 23:05:44.351095 [Gating] SW mode calibration
6325 23:05:44.358030 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6326 23:05:44.361047 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6327 23:05:44.368160 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6328 23:05:44.371130 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6329 23:05:44.374353 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6330 23:05:44.381027 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6331 23:05:44.384236 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6332 23:05:44.387682 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6333 23:05:44.394195 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6334 23:05:44.398076 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6335 23:05:44.401065 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6336 23:05:44.404333 Total UI for P1: 0, mck2ui 16
6337 23:05:44.407531 best dqsien dly found for B0: ( 0, 14, 24)
6338 23:05:44.411241 Total UI for P1: 0, mck2ui 16
6339 23:05:44.414314 best dqsien dly found for B1: ( 0, 14, 24)
6340 23:05:44.417864 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6341 23:05:44.420839 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6342 23:05:44.420949
6343 23:05:44.427731 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6344 23:05:44.430795 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6345 23:05:44.433909 [Gating] SW calibration Done
6346 23:05:44.433989 ==
6347 23:05:44.437667 Dram Type= 6, Freq= 0, CH_0, rank 0
6348 23:05:44.440749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6349 23:05:44.440854 ==
6350 23:05:44.440944 RX Vref Scan: 0
6351 23:05:44.441037
6352 23:05:44.444133 RX Vref 0 -> 0, step: 1
6353 23:05:44.444237
6354 23:05:44.447306 RX Delay -410 -> 252, step: 16
6355 23:05:44.451123 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6356 23:05:44.457688 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6357 23:05:44.460769 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6358 23:05:44.464101 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6359 23:05:44.467283 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6360 23:05:44.474019 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6361 23:05:44.477675 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6362 23:05:44.480818 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6363 23:05:44.483942 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6364 23:05:44.487569 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6365 23:05:44.493900 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6366 23:05:44.497490 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6367 23:05:44.501121 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6368 23:05:44.507139 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6369 23:05:44.510328 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6370 23:05:44.513996 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6371 23:05:44.514082 ==
6372 23:05:44.517151 Dram Type= 6, Freq= 0, CH_0, rank 0
6373 23:05:44.520232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6374 23:05:44.523819 ==
6375 23:05:44.523912 DQS Delay:
6376 23:05:44.523980 DQS0 = 27, DQS1 = 35
6377 23:05:44.527302 DQM Delay:
6378 23:05:44.527382 DQM0 = 10, DQM1 = 12
6379 23:05:44.530422 DQ Delay:
6380 23:05:44.530501 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =0
6381 23:05:44.534084 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6382 23:05:44.537386 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6383 23:05:44.540826 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6384 23:05:44.540904
6385 23:05:44.540967
6386 23:05:44.541025 ==
6387 23:05:44.543763 Dram Type= 6, Freq= 0, CH_0, rank 0
6388 23:05:44.550507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6389 23:05:44.550594 ==
6390 23:05:44.550670
6391 23:05:44.550733
6392 23:05:44.550793 TX Vref Scan disable
6393 23:05:44.553782 == TX Byte 0 ==
6394 23:05:44.557009 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6395 23:05:44.560194 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6396 23:05:44.563539 == TX Byte 1 ==
6397 23:05:44.566707 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6398 23:05:44.570680 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6399 23:05:44.570793 ==
6400 23:05:44.573767 Dram Type= 6, Freq= 0, CH_0, rank 0
6401 23:05:44.580592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6402 23:05:44.580698 ==
6403 23:05:44.580804
6404 23:05:44.580894
6405 23:05:44.583683 TX Vref Scan disable
6406 23:05:44.583765 == TX Byte 0 ==
6407 23:05:44.586898 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6408 23:05:44.593849 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6409 23:05:44.593926 == TX Byte 1 ==
6410 23:05:44.597039 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6411 23:05:44.603744 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6412 23:05:44.603855
6413 23:05:44.603922 [DATLAT]
6414 23:05:44.603982 Freq=400, CH0 RK0
6415 23:05:44.604040
6416 23:05:44.606758 DATLAT Default: 0xf
6417 23:05:44.606833 0, 0xFFFF, sum = 0
6418 23:05:44.610014 1, 0xFFFF, sum = 0
6419 23:05:44.610094 2, 0xFFFF, sum = 0
6420 23:05:44.613174 3, 0xFFFF, sum = 0
6421 23:05:44.613248 4, 0xFFFF, sum = 0
6422 23:05:44.616736 5, 0xFFFF, sum = 0
6423 23:05:44.619694 6, 0xFFFF, sum = 0
6424 23:05:44.619784 7, 0xFFFF, sum = 0
6425 23:05:44.623433 8, 0xFFFF, sum = 0
6426 23:05:44.623519 9, 0xFFFF, sum = 0
6427 23:05:44.626337 10, 0xFFFF, sum = 0
6428 23:05:44.626412 11, 0xFFFF, sum = 0
6429 23:05:44.630211 12, 0xFFFF, sum = 0
6430 23:05:44.630294 13, 0x0, sum = 1
6431 23:05:44.633129 14, 0x0, sum = 2
6432 23:05:44.633236 15, 0x0, sum = 3
6433 23:05:44.636563 16, 0x0, sum = 4
6434 23:05:44.636636 best_step = 14
6435 23:05:44.636701
6436 23:05:44.636759 ==
6437 23:05:44.639812 Dram Type= 6, Freq= 0, CH_0, rank 0
6438 23:05:44.643316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6439 23:05:44.643389 ==
6440 23:05:44.646362 RX Vref Scan: 1
6441 23:05:44.646438
6442 23:05:44.649811 RX Vref 0 -> 0, step: 1
6443 23:05:44.649886
6444 23:05:44.649952 RX Delay -311 -> 252, step: 8
6445 23:05:44.653092
6446 23:05:44.653201 Set Vref, RX VrefLevel [Byte0]: 54
6447 23:05:44.656399 [Byte1]: 53
6448 23:05:44.661774
6449 23:05:44.661855 Final RX Vref Byte 0 = 54 to rank0
6450 23:05:44.665007 Final RX Vref Byte 1 = 53 to rank0
6451 23:05:44.668344 Final RX Vref Byte 0 = 54 to rank1
6452 23:05:44.672129 Final RX Vref Byte 1 = 53 to rank1==
6453 23:05:44.675393 Dram Type= 6, Freq= 0, CH_0, rank 0
6454 23:05:44.681667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6455 23:05:44.681752 ==
6456 23:05:44.681820 DQS Delay:
6457 23:05:44.685482 DQS0 = 28, DQS1 = 36
6458 23:05:44.685564 DQM Delay:
6459 23:05:44.685666 DQM0 = 11, DQM1 = 13
6460 23:05:44.688305 DQ Delay:
6461 23:05:44.691972 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6462 23:05:44.692069 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6463 23:05:44.695438 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6464 23:05:44.698521 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =20
6465 23:05:44.698610
6466 23:05:44.698672
6467 23:05:44.708297 [DQSOSCAuto] RK0, (LSB)MR18= 0xd1bd, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 384 ps
6468 23:05:44.711512 CH0 RK0: MR19=C0C, MR18=D1BD
6469 23:05:44.718709 CH0_RK0: MR19=0xC0C, MR18=0xD1BD, DQSOSC=384, MR23=63, INC=400, DEC=267
6470 23:05:44.718831 ==
6471 23:05:44.721794 Dram Type= 6, Freq= 0, CH_0, rank 1
6472 23:05:44.725002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6473 23:05:44.725107 ==
6474 23:05:44.728730 [Gating] SW mode calibration
6475 23:05:44.734828 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6476 23:05:44.742027 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6477 23:05:44.745228 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6478 23:05:44.748190 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6479 23:05:44.751800 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6480 23:05:44.758300 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6481 23:05:44.761946 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6482 23:05:44.764721 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6483 23:05:44.771810 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6484 23:05:44.775028 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6485 23:05:44.778415 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6486 23:05:44.781843 Total UI for P1: 0, mck2ui 16
6487 23:05:44.784912 best dqsien dly found for B0: ( 0, 14, 24)
6488 23:05:44.788524 Total UI for P1: 0, mck2ui 16
6489 23:05:44.792024 best dqsien dly found for B1: ( 0, 14, 24)
6490 23:05:44.795258 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6491 23:05:44.798338 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6492 23:05:44.798409
6493 23:05:44.805018 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6494 23:05:44.808334 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6495 23:05:44.811567 [Gating] SW calibration Done
6496 23:05:44.811649 ==
6497 23:05:44.815273 Dram Type= 6, Freq= 0, CH_0, rank 1
6498 23:05:44.818481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6499 23:05:44.818565 ==
6500 23:05:44.818629 RX Vref Scan: 0
6501 23:05:44.818688
6502 23:05:44.821817 RX Vref 0 -> 0, step: 1
6503 23:05:44.821892
6504 23:05:44.825154 RX Delay -410 -> 252, step: 16
6505 23:05:44.828408 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6506 23:05:44.835165 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6507 23:05:44.838440 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6508 23:05:44.841478 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6509 23:05:44.845167 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6510 23:05:44.851452 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6511 23:05:44.855054 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6512 23:05:44.858183 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6513 23:05:44.861413 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6514 23:05:44.864578 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6515 23:05:44.871712 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6516 23:05:44.874968 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6517 23:05:44.878105 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6518 23:05:44.884657 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6519 23:05:44.887809 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6520 23:05:44.890817 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6521 23:05:44.890899 ==
6522 23:05:44.894399 Dram Type= 6, Freq= 0, CH_0, rank 1
6523 23:05:44.900791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6524 23:05:44.900872 ==
6525 23:05:44.900937 DQS Delay:
6526 23:05:44.900997 DQS0 = 27, DQS1 = 35
6527 23:05:44.904059 DQM Delay:
6528 23:05:44.904160 DQM0 = 12, DQM1 = 10
6529 23:05:44.907441 DQ Delay:
6530 23:05:44.907577 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6531 23:05:44.910617 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6532 23:05:44.914067 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6533 23:05:44.917459 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6534 23:05:44.917672
6535 23:05:44.917820
6536 23:05:44.920651 ==
6537 23:05:44.923795 Dram Type= 6, Freq= 0, CH_0, rank 1
6538 23:05:44.927288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6539 23:05:44.927379 ==
6540 23:05:44.927473
6541 23:05:44.927570
6542 23:05:44.930610 TX Vref Scan disable
6543 23:05:44.930692 == TX Byte 0 ==
6544 23:05:44.933801 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6545 23:05:44.940906 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6546 23:05:44.940994 == TX Byte 1 ==
6547 23:05:44.944372 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6548 23:05:44.947347 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6549 23:05:44.950406 ==
6550 23:05:44.954280 Dram Type= 6, Freq= 0, CH_0, rank 1
6551 23:05:44.957422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6552 23:05:44.957547 ==
6553 23:05:44.957654
6554 23:05:44.957716
6555 23:05:44.960405 TX Vref Scan disable
6556 23:05:44.960479 == TX Byte 0 ==
6557 23:05:44.963851 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6558 23:05:44.970344 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6559 23:05:44.970441 == TX Byte 1 ==
6560 23:05:44.974111 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6561 23:05:44.980752 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6562 23:05:44.980877
6563 23:05:44.980939 [DATLAT]
6564 23:05:44.980999 Freq=400, CH0 RK1
6565 23:05:44.981107
6566 23:05:44.984116 DATLAT Default: 0xe
6567 23:05:44.984189 0, 0xFFFF, sum = 0
6568 23:05:44.987474 1, 0xFFFF, sum = 0
6569 23:05:44.990368 2, 0xFFFF, sum = 0
6570 23:05:44.990445 3, 0xFFFF, sum = 0
6571 23:05:44.993388 4, 0xFFFF, sum = 0
6572 23:05:44.993460 5, 0xFFFF, sum = 0
6573 23:05:44.997012 6, 0xFFFF, sum = 0
6574 23:05:44.997082 7, 0xFFFF, sum = 0
6575 23:05:45.000493 8, 0xFFFF, sum = 0
6576 23:05:45.000566 9, 0xFFFF, sum = 0
6577 23:05:45.003783 10, 0xFFFF, sum = 0
6578 23:05:45.003854 11, 0xFFFF, sum = 0
6579 23:05:45.007017 12, 0xFFFF, sum = 0
6580 23:05:45.007089 13, 0x0, sum = 1
6581 23:05:45.010349 14, 0x0, sum = 2
6582 23:05:45.010434 15, 0x0, sum = 3
6583 23:05:45.013657 16, 0x0, sum = 4
6584 23:05:45.013736 best_step = 14
6585 23:05:45.013806
6586 23:05:45.013866 ==
6587 23:05:45.017032 Dram Type= 6, Freq= 0, CH_0, rank 1
6588 23:05:45.020474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6589 23:05:45.023766 ==
6590 23:05:45.023839 RX Vref Scan: 0
6591 23:05:45.023901
6592 23:05:45.026833 RX Vref 0 -> 0, step: 1
6593 23:05:45.026903
6594 23:05:45.030018 RX Delay -311 -> 252, step: 8
6595 23:05:45.033485 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6596 23:05:45.040306 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6597 23:05:45.043588 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6598 23:05:45.046901 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6599 23:05:45.049919 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6600 23:05:45.056851 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6601 23:05:45.059891 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6602 23:05:45.063273 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6603 23:05:45.066812 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6604 23:05:45.073180 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6605 23:05:45.076929 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6606 23:05:45.080114 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6607 23:05:45.083323 iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440
6608 23:05:45.089897 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6609 23:05:45.092993 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6610 23:05:45.096820 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6611 23:05:45.096893 ==
6612 23:05:45.100120 Dram Type= 6, Freq= 0, CH_0, rank 1
6613 23:05:45.106489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6614 23:05:45.106572 ==
6615 23:05:45.106636 DQS Delay:
6616 23:05:45.109864 DQS0 = 24, DQS1 = 32
6617 23:05:45.109942 DQM Delay:
6618 23:05:45.110004 DQM0 = 8, DQM1 = 9
6619 23:05:45.112914 DQ Delay:
6620 23:05:45.116752 DQ0 =8, DQ1 =8, DQ2 =4, DQ3 =8
6621 23:05:45.116839 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6622 23:05:45.120156 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6623 23:05:45.123152 DQ12 =12, DQ13 =12, DQ14 =20, DQ15 =16
6624 23:05:45.123224
6625 23:05:45.123294
6626 23:05:45.133199 [DQSOSCAuto] RK1, (LSB)MR18= 0xba5a, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 386 ps
6627 23:05:45.136163 CH0 RK1: MR19=C0C, MR18=BA5A
6628 23:05:45.143271 CH0_RK1: MR19=0xC0C, MR18=0xBA5A, DQSOSC=386, MR23=63, INC=396, DEC=264
6629 23:05:45.143347 [RxdqsGatingPostProcess] freq 400
6630 23:05:45.149481 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6631 23:05:45.152859 best DQS0 dly(2T, 0.5T) = (0, 10)
6632 23:05:45.156135 best DQS1 dly(2T, 0.5T) = (0, 10)
6633 23:05:45.159454 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6634 23:05:45.163073 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6635 23:05:45.166722 best DQS0 dly(2T, 0.5T) = (0, 10)
6636 23:05:45.169718 best DQS1 dly(2T, 0.5T) = (0, 10)
6637 23:05:45.173076 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6638 23:05:45.176172 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6639 23:05:45.179841 Pre-setting of DQS Precalculation
6640 23:05:45.183109 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6641 23:05:45.183185 ==
6642 23:05:45.186237 Dram Type= 6, Freq= 0, CH_1, rank 0
6643 23:05:45.189521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6644 23:05:45.192870 ==
6645 23:05:45.196061 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6646 23:05:45.202614 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6647 23:05:45.206674 [CA 0] Center 36 (8~64) winsize 57
6648 23:05:45.209747 [CA 1] Center 36 (8~64) winsize 57
6649 23:05:45.212820 [CA 2] Center 36 (8~64) winsize 57
6650 23:05:45.216196 [CA 3] Center 36 (8~64) winsize 57
6651 23:05:45.219364 [CA 4] Center 36 (8~64) winsize 57
6652 23:05:45.222657 [CA 5] Center 36 (8~64) winsize 57
6653 23:05:45.222732
6654 23:05:45.225837 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6655 23:05:45.225913
6656 23:05:45.229554 [CATrainingPosCal] consider 1 rank data
6657 23:05:45.232919 u2DelayCellTimex100 = 270/100 ps
6658 23:05:45.236056 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6659 23:05:45.239280 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6660 23:05:45.242848 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6661 23:05:45.246051 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6662 23:05:45.249476 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6663 23:05:45.252687 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6664 23:05:45.252767
6665 23:05:45.255773 CA PerBit enable=1, Macro0, CA PI delay=36
6666 23:05:45.259560
6667 23:05:45.259641 [CBTSetCACLKResult] CA Dly = 36
6668 23:05:45.262707 CS Dly: 1 (0~32)
6669 23:05:45.262783 ==
6670 23:05:45.266018 Dram Type= 6, Freq= 0, CH_1, rank 1
6671 23:05:45.269316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6672 23:05:45.269400 ==
6673 23:05:45.275855 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6674 23:05:45.282308 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6675 23:05:45.285888 [CA 0] Center 36 (8~64) winsize 57
6676 23:05:45.288923 [CA 1] Center 36 (8~64) winsize 57
6677 23:05:45.288993 [CA 2] Center 36 (8~64) winsize 57
6678 23:05:45.292702 [CA 3] Center 36 (8~64) winsize 57
6679 23:05:45.295787 [CA 4] Center 36 (8~64) winsize 57
6680 23:05:45.299300 [CA 5] Center 36 (8~64) winsize 57
6681 23:05:45.299377
6682 23:05:45.302647 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6683 23:05:45.305943
6684 23:05:45.309119 [CATrainingPosCal] consider 2 rank data
6685 23:05:45.309203 u2DelayCellTimex100 = 270/100 ps
6686 23:05:45.315648 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6687 23:05:45.318960 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6688 23:05:45.322129 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6689 23:05:45.326058 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6690 23:05:45.329221 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6691 23:05:45.332564 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6692 23:05:45.332641
6693 23:05:45.335793 CA PerBit enable=1, Macro0, CA PI delay=36
6694 23:05:45.335867
6695 23:05:45.338993 [CBTSetCACLKResult] CA Dly = 36
6696 23:05:45.342655 CS Dly: 1 (0~32)
6697 23:05:45.342726
6698 23:05:45.345686 ----->DramcWriteLeveling(PI) begin...
6699 23:05:45.345763 ==
6700 23:05:45.348886 Dram Type= 6, Freq= 0, CH_1, rank 0
6701 23:05:45.352396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6702 23:05:45.352478 ==
6703 23:05:45.355848 Write leveling (Byte 0): 40 => 8
6704 23:05:45.359302 Write leveling (Byte 1): 40 => 8
6705 23:05:45.362523 DramcWriteLeveling(PI) end<-----
6706 23:05:45.362598
6707 23:05:45.362661 ==
6708 23:05:45.365701 Dram Type= 6, Freq= 0, CH_1, rank 0
6709 23:05:45.369340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6710 23:05:45.369414 ==
6711 23:05:45.372473 [Gating] SW mode calibration
6712 23:05:45.378904 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6713 23:05:45.385764 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6714 23:05:45.388921 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6715 23:05:45.392435 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6716 23:05:45.398841 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6717 23:05:45.402010 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6718 23:05:45.405566 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6719 23:05:45.412397 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6720 23:05:45.415537 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6721 23:05:45.418912 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6722 23:05:45.425119 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6723 23:05:45.425196 Total UI for P1: 0, mck2ui 16
6724 23:05:45.428334 best dqsien dly found for B0: ( 0, 14, 24)
6725 23:05:45.432215 Total UI for P1: 0, mck2ui 16
6726 23:05:45.435456 best dqsien dly found for B1: ( 0, 14, 24)
6727 23:05:45.441819 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6728 23:05:45.445004 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6729 23:05:45.445074
6730 23:05:45.448961 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6731 23:05:45.452059 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6732 23:05:45.455161 [Gating] SW calibration Done
6733 23:05:45.455237 ==
6734 23:05:45.458889 Dram Type= 6, Freq= 0, CH_1, rank 0
6735 23:05:45.461747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6736 23:05:45.461819 ==
6737 23:05:45.465281 RX Vref Scan: 0
6738 23:05:45.465353
6739 23:05:45.465413 RX Vref 0 -> 0, step: 1
6740 23:05:45.465469
6741 23:05:45.468829 RX Delay -410 -> 252, step: 16
6742 23:05:45.471941 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6743 23:05:45.478886 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6744 23:05:45.482116 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6745 23:05:45.485181 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6746 23:05:45.488245 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6747 23:05:45.495161 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6748 23:05:45.498270 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6749 23:05:45.502436 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6750 23:05:45.505260 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6751 23:05:45.511943 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6752 23:05:45.514944 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6753 23:05:45.518497 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6754 23:05:45.525060 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6755 23:05:45.528323 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6756 23:05:45.531729 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6757 23:05:45.535083 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6758 23:05:45.535161 ==
6759 23:05:45.538060 Dram Type= 6, Freq= 0, CH_1, rank 0
6760 23:05:45.544740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6761 23:05:45.544815 ==
6762 23:05:45.544885 DQS Delay:
6763 23:05:45.548394 DQS0 = 35, DQS1 = 35
6764 23:05:45.548463 DQM Delay:
6765 23:05:45.548523 DQM0 = 17, DQM1 = 13
6766 23:05:45.551619 DQ Delay:
6767 23:05:45.554797 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =16
6768 23:05:45.557897 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6769 23:05:45.557971 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6770 23:05:45.564648 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6771 23:05:45.564724
6772 23:05:45.564787
6773 23:05:45.564847 ==
6774 23:05:45.568516 Dram Type= 6, Freq= 0, CH_1, rank 0
6775 23:05:45.571409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6776 23:05:45.571485 ==
6777 23:05:45.571547
6778 23:05:45.571606
6779 23:05:45.575306 TX Vref Scan disable
6780 23:05:45.575386 == TX Byte 0 ==
6781 23:05:45.578240 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6782 23:05:45.584616 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6783 23:05:45.584729 == TX Byte 1 ==
6784 23:05:45.587972 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6785 23:05:45.594797 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6786 23:05:45.594873 ==
6787 23:05:45.598343 Dram Type= 6, Freq= 0, CH_1, rank 0
6788 23:05:45.601493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6789 23:05:45.601569 ==
6790 23:05:45.601681
6791 23:05:45.601741
6792 23:05:45.604753 TX Vref Scan disable
6793 23:05:45.604823 == TX Byte 0 ==
6794 23:05:45.611153 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6795 23:05:45.614752 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6796 23:05:45.614822 == TX Byte 1 ==
6797 23:05:45.617773 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6798 23:05:45.625104 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6799 23:05:45.625179
6800 23:05:45.625241 [DATLAT]
6801 23:05:45.627940 Freq=400, CH1 RK0
6802 23:05:45.628015
6803 23:05:45.628076 DATLAT Default: 0xf
6804 23:05:45.631113 0, 0xFFFF, sum = 0
6805 23:05:45.631182 1, 0xFFFF, sum = 0
6806 23:05:45.634729 2, 0xFFFF, sum = 0
6807 23:05:45.634819 3, 0xFFFF, sum = 0
6808 23:05:45.637744 4, 0xFFFF, sum = 0
6809 23:05:45.637818 5, 0xFFFF, sum = 0
6810 23:05:45.641422 6, 0xFFFF, sum = 0
6811 23:05:45.641492 7, 0xFFFF, sum = 0
6812 23:05:45.644466 8, 0xFFFF, sum = 0
6813 23:05:45.644543 9, 0xFFFF, sum = 0
6814 23:05:45.647914 10, 0xFFFF, sum = 0
6815 23:05:45.647984 11, 0xFFFF, sum = 0
6816 23:05:45.651414 12, 0xFFFF, sum = 0
6817 23:05:45.651492 13, 0x0, sum = 1
6818 23:05:45.654615 14, 0x0, sum = 2
6819 23:05:45.654691 15, 0x0, sum = 3
6820 23:05:45.657729 16, 0x0, sum = 4
6821 23:05:45.657806 best_step = 14
6822 23:05:45.657867
6823 23:05:45.657924 ==
6824 23:05:45.661362 Dram Type= 6, Freq= 0, CH_1, rank 0
6825 23:05:45.667783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6826 23:05:45.667856 ==
6827 23:05:45.667918 RX Vref Scan: 1
6828 23:05:45.667993
6829 23:05:45.671093 RX Vref 0 -> 0, step: 1
6830 23:05:45.671163
6831 23:05:45.674611 RX Delay -311 -> 252, step: 8
6832 23:05:45.674680
6833 23:05:45.677654 Set Vref, RX VrefLevel [Byte0]: 57
6834 23:05:45.681424 [Byte1]: 53
6835 23:05:45.681493
6836 23:05:45.684108 Final RX Vref Byte 0 = 57 to rank0
6837 23:05:45.687551 Final RX Vref Byte 1 = 53 to rank0
6838 23:05:45.691095 Final RX Vref Byte 0 = 57 to rank1
6839 23:05:45.694627 Final RX Vref Byte 1 = 53 to rank1==
6840 23:05:45.697933 Dram Type= 6, Freq= 0, CH_1, rank 0
6841 23:05:45.700657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6842 23:05:45.704157 ==
6843 23:05:45.704231 DQS Delay:
6844 23:05:45.704330 DQS0 = 28, DQS1 = 32
6845 23:05:45.707680 DQM Delay:
6846 23:05:45.707758 DQM0 = 9, DQM1 = 10
6847 23:05:45.710967 DQ Delay:
6848 23:05:45.711043 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6849 23:05:45.713920 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
6850 23:05:45.717817 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6851 23:05:45.720794 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =20
6852 23:05:45.720863
6853 23:05:45.720923
6854 23:05:45.730724 [DQSOSCAuto] RK0, (LSB)MR18= 0x8dc7, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 392 ps
6855 23:05:45.734457 CH1 RK0: MR19=C0C, MR18=8DC7
6856 23:05:45.737829 CH1_RK0: MR19=0xC0C, MR18=0x8DC7, DQSOSC=385, MR23=63, INC=398, DEC=265
6857 23:05:45.740516 ==
6858 23:05:45.744177 Dram Type= 6, Freq= 0, CH_1, rank 1
6859 23:05:45.747361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6860 23:05:45.747430 ==
6861 23:05:45.750642 [Gating] SW mode calibration
6862 23:05:45.757413 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6863 23:05:45.760808 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6864 23:05:45.767529 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6865 23:05:45.770536 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6866 23:05:45.773808 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6867 23:05:45.780641 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6868 23:05:45.783596 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6869 23:05:45.787077 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6870 23:05:45.793737 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6871 23:05:45.796980 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6872 23:05:45.800249 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6873 23:05:45.803906 Total UI for P1: 0, mck2ui 16
6874 23:05:45.807157 best dqsien dly found for B0: ( 0, 14, 24)
6875 23:05:45.810166 Total UI for P1: 0, mck2ui 16
6876 23:05:45.813483 best dqsien dly found for B1: ( 0, 14, 24)
6877 23:05:45.817109 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6878 23:05:45.820437 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6879 23:05:45.820514
6880 23:05:45.823898 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6881 23:05:45.830775 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6882 23:05:45.830853 [Gating] SW calibration Done
6883 23:05:45.830918 ==
6884 23:05:45.833606 Dram Type= 6, Freq= 0, CH_1, rank 1
6885 23:05:45.840267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6886 23:05:45.840346 ==
6887 23:05:45.840413 RX Vref Scan: 0
6888 23:05:45.840472
6889 23:05:45.843992 RX Vref 0 -> 0, step: 1
6890 23:05:45.844058
6891 23:05:45.847097 RX Delay -410 -> 252, step: 16
6892 23:05:45.850739 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6893 23:05:45.853550 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6894 23:05:45.860761 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6895 23:05:45.863701 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6896 23:05:45.866801 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6897 23:05:45.869956 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6898 23:05:45.877054 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6899 23:05:45.879929 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6900 23:05:45.883689 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6901 23:05:45.886929 iDelay=230, Bit 9, Center -27 (-266 ~ 213) 480
6902 23:05:45.893608 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6903 23:05:45.897104 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6904 23:05:45.900459 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6905 23:05:45.903384 iDelay=230, Bit 13, Center -11 (-250 ~ 229) 480
6906 23:05:45.910391 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6907 23:05:45.913739 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6908 23:05:45.913813 ==
6909 23:05:45.916679 Dram Type= 6, Freq= 0, CH_1, rank 1
6910 23:05:45.919939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6911 23:05:45.920020 ==
6912 23:05:45.923657 DQS Delay:
6913 23:05:45.923729 DQS0 = 27, DQS1 = 35
6914 23:05:45.926511 DQM Delay:
6915 23:05:45.926592 DQM0 = 12, DQM1 = 15
6916 23:05:45.926654 DQ Delay:
6917 23:05:45.930399 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6918 23:05:45.933294 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6919 23:05:45.936437 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6920 23:05:45.939868 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6921 23:05:45.939937
6922 23:05:45.939998
6923 23:05:45.940074 ==
6924 23:05:45.943429 Dram Type= 6, Freq= 0, CH_1, rank 1
6925 23:05:45.950167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6926 23:05:45.950284 ==
6927 23:05:45.950395
6928 23:05:45.950463
6929 23:05:45.950522 TX Vref Scan disable
6930 23:05:45.953401 == TX Byte 0 ==
6931 23:05:45.956492 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6932 23:05:45.959861 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6933 23:05:45.963055 == TX Byte 1 ==
6934 23:05:45.966444 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6935 23:05:45.969622 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6936 23:05:45.969696 ==
6937 23:05:45.972894 Dram Type= 6, Freq= 0, CH_1, rank 1
6938 23:05:45.979930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6939 23:05:45.980003 ==
6940 23:05:45.980069
6941 23:05:45.980125
6942 23:05:45.980207 TX Vref Scan disable
6943 23:05:45.983082 == TX Byte 0 ==
6944 23:05:45.986621 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6945 23:05:45.989961 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6946 23:05:45.993286 == TX Byte 1 ==
6947 23:05:45.996005 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6948 23:05:45.999693 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6949 23:05:45.999765
6950 23:05:46.003123 [DATLAT]
6951 23:05:46.003200 Freq=400, CH1 RK1
6952 23:05:46.003263
6953 23:05:46.006507 DATLAT Default: 0xe
6954 23:05:46.006583 0, 0xFFFF, sum = 0
6955 23:05:46.009636 1, 0xFFFF, sum = 0
6956 23:05:46.009708 2, 0xFFFF, sum = 0
6957 23:05:46.012936 3, 0xFFFF, sum = 0
6958 23:05:46.013007 4, 0xFFFF, sum = 0
6959 23:05:46.016175 5, 0xFFFF, sum = 0
6960 23:05:46.016275 6, 0xFFFF, sum = 0
6961 23:05:46.019230 7, 0xFFFF, sum = 0
6962 23:05:46.019305 8, 0xFFFF, sum = 0
6963 23:05:46.023058 9, 0xFFFF, sum = 0
6964 23:05:46.023129 10, 0xFFFF, sum = 0
6965 23:05:46.026412 11, 0xFFFF, sum = 0
6966 23:05:46.029393 12, 0xFFFF, sum = 0
6967 23:05:46.029467 13, 0x0, sum = 1
6968 23:05:46.032565 14, 0x0, sum = 2
6969 23:05:46.032655 15, 0x0, sum = 3
6970 23:05:46.032723 16, 0x0, sum = 4
6971 23:05:46.036285 best_step = 14
6972 23:05:46.036357
6973 23:05:46.036424 ==
6974 23:05:46.039455 Dram Type= 6, Freq= 0, CH_1, rank 1
6975 23:05:46.043023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6976 23:05:46.043103 ==
6977 23:05:46.046256 RX Vref Scan: 0
6978 23:05:46.046326
6979 23:05:46.046393 RX Vref 0 -> 0, step: 1
6980 23:05:46.049649
6981 23:05:46.049717 RX Delay -311 -> 252, step: 8
6982 23:05:46.057860 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6983 23:05:46.060917 iDelay=217, Bit 1, Center -20 (-239 ~ 200) 440
6984 23:05:46.063975 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6985 23:05:46.067971 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6986 23:05:46.074461 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6987 23:05:46.077729 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6988 23:05:46.080706 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6989 23:05:46.084138 iDelay=217, Bit 7, Center -16 (-239 ~ 208) 448
6990 23:05:46.090532 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6991 23:05:46.094308 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6992 23:05:46.097563 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
6993 23:05:46.101052 iDelay=217, Bit 11, Center -24 (-247 ~ 200) 448
6994 23:05:46.107679 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6995 23:05:46.110892 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6996 23:05:46.114030 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6997 23:05:46.120514 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6998 23:05:46.120592 ==
6999 23:05:46.123752 Dram Type= 6, Freq= 0, CH_1, rank 1
7000 23:05:46.127611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7001 23:05:46.127688 ==
7002 23:05:46.127750 DQS Delay:
7003 23:05:46.130789 DQS0 = 28, DQS1 = 36
7004 23:05:46.130859 DQM Delay:
7005 23:05:46.133884 DQM0 = 11, DQM1 = 15
7006 23:05:46.133954 DQ Delay:
7007 23:05:46.137134 DQ0 =12, DQ1 =8, DQ2 =0, DQ3 =8
7008 23:05:46.140179 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =12
7009 23:05:46.143851 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =12
7010 23:05:46.146889 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
7011 23:05:46.146964
7012 23:05:46.147027
7013 23:05:46.153860 [DQSOSCAuto] RK1, (LSB)MR18= 0xc152, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 385 ps
7014 23:05:46.157141 CH1 RK1: MR19=C0C, MR18=C152
7015 23:05:46.164078 CH1_RK1: MR19=0xC0C, MR18=0xC152, DQSOSC=385, MR23=63, INC=398, DEC=265
7016 23:05:46.166906 [RxdqsGatingPostProcess] freq 400
7017 23:05:46.173458 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7018 23:05:46.173565 best DQS0 dly(2T, 0.5T) = (0, 10)
7019 23:05:46.177102 best DQS1 dly(2T, 0.5T) = (0, 10)
7020 23:05:46.180040 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7021 23:05:46.183381 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7022 23:05:46.187414 best DQS0 dly(2T, 0.5T) = (0, 10)
7023 23:05:46.190494 best DQS1 dly(2T, 0.5T) = (0, 10)
7024 23:05:46.193856 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7025 23:05:46.196955 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7026 23:05:46.200163 Pre-setting of DQS Precalculation
7027 23:05:46.206890 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7028 23:05:46.213349 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7029 23:05:46.219869 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7030 23:05:46.219953
7031 23:05:46.220016
7032 23:05:46.223271 [Calibration Summary] 800 Mbps
7033 23:05:46.223339 CH 0, Rank 0
7034 23:05:46.226586 SW Impedance : PASS
7035 23:05:46.230313 DUTY Scan : NO K
7036 23:05:46.230384 ZQ Calibration : PASS
7037 23:05:46.233355 Jitter Meter : NO K
7038 23:05:46.233429 CBT Training : PASS
7039 23:05:46.237078 Write leveling : PASS
7040 23:05:46.240050 RX DQS gating : PASS
7041 23:05:46.240123 RX DQ/DQS(RDDQC) : PASS
7042 23:05:46.243303 TX DQ/DQS : PASS
7043 23:05:46.246425 RX DATLAT : PASS
7044 23:05:46.246497 RX DQ/DQS(Engine): PASS
7045 23:05:46.250390 TX OE : NO K
7046 23:05:46.250464 All Pass.
7047 23:05:46.250524
7048 23:05:46.253186 CH 0, Rank 1
7049 23:05:46.253266 SW Impedance : PASS
7050 23:05:46.257044 DUTY Scan : NO K
7051 23:05:46.260181 ZQ Calibration : PASS
7052 23:05:46.260249 Jitter Meter : NO K
7053 23:05:46.263574 CBT Training : PASS
7054 23:05:46.266660 Write leveling : NO K
7055 23:05:46.266731 RX DQS gating : PASS
7056 23:05:46.269959 RX DQ/DQS(RDDQC) : PASS
7057 23:05:46.273082 TX DQ/DQS : PASS
7058 23:05:46.273168 RX DATLAT : PASS
7059 23:05:46.276691 RX DQ/DQS(Engine): PASS
7060 23:05:46.276762 TX OE : NO K
7061 23:05:46.280134 All Pass.
7062 23:05:46.280209
7063 23:05:46.280270 CH 1, Rank 0
7064 23:05:46.283390 SW Impedance : PASS
7065 23:05:46.283461 DUTY Scan : NO K
7066 23:05:46.286632 ZQ Calibration : PASS
7067 23:05:46.290129 Jitter Meter : NO K
7068 23:05:46.290201 CBT Training : PASS
7069 23:05:46.292825 Write leveling : PASS
7070 23:05:46.296659 RX DQS gating : PASS
7071 23:05:46.296729 RX DQ/DQS(RDDQC) : PASS
7072 23:05:46.299420 TX DQ/DQS : PASS
7073 23:05:46.303050 RX DATLAT : PASS
7074 23:05:46.303124 RX DQ/DQS(Engine): PASS
7075 23:05:46.306390 TX OE : NO K
7076 23:05:46.306463 All Pass.
7077 23:05:46.306526
7078 23:05:46.309565 CH 1, Rank 1
7079 23:05:46.309688 SW Impedance : PASS
7080 23:05:46.312570 DUTY Scan : NO K
7081 23:05:46.316244 ZQ Calibration : PASS
7082 23:05:46.316316 Jitter Meter : NO K
7083 23:05:46.319390 CBT Training : PASS
7084 23:05:46.323424 Write leveling : NO K
7085 23:05:46.323496 RX DQS gating : PASS
7086 23:05:46.326480 RX DQ/DQS(RDDQC) : PASS
7087 23:05:46.329711 TX DQ/DQS : PASS
7088 23:05:46.329782 RX DATLAT : PASS
7089 23:05:46.332875 RX DQ/DQS(Engine): PASS
7090 23:05:46.332945 TX OE : NO K
7091 23:05:46.335989 All Pass.
7092 23:05:46.336060
7093 23:05:46.336124 DramC Write-DBI off
7094 23:05:46.339716 PER_BANK_REFRESH: Hybrid Mode
7095 23:05:46.342607 TX_TRACKING: ON
7096 23:05:46.349810 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7097 23:05:46.352702 [FAST_K] Save calibration result to emmc
7098 23:05:46.359198 dramc_set_vcore_voltage set vcore to 725000
7099 23:05:46.359285 Read voltage for 1600, 0
7100 23:05:46.363058 Vio18 = 0
7101 23:05:46.363133 Vcore = 725000
7102 23:05:46.363195 Vdram = 0
7103 23:05:46.363255 Vddq = 0
7104 23:05:46.365901 Vmddr = 0
7105 23:05:46.369316 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7106 23:05:46.375897 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7107 23:05:46.379637 MEM_TYPE=3, freq_sel=13
7108 23:05:46.379719 sv_algorithm_assistance_LP4_3733
7109 23:05:46.385727 ============ PULL DRAM RESETB DOWN ============
7110 23:05:46.389587 ========== PULL DRAM RESETB DOWN end =========
7111 23:05:46.392688 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7112 23:05:46.395801 ===================================
7113 23:05:46.399416 LPDDR4 DRAM CONFIGURATION
7114 23:05:46.402427 ===================================
7115 23:05:46.406395 EX_ROW_EN[0] = 0x0
7116 23:05:46.406476 EX_ROW_EN[1] = 0x0
7117 23:05:46.409546 LP4Y_EN = 0x0
7118 23:05:46.409636 WORK_FSP = 0x1
7119 23:05:46.412844 WL = 0x5
7120 23:05:46.412933 RL = 0x5
7121 23:05:46.416085 BL = 0x2
7122 23:05:46.416167 RPST = 0x0
7123 23:05:46.419615 RD_PRE = 0x0
7124 23:05:46.419695 WR_PRE = 0x1
7125 23:05:46.422678 WR_PST = 0x1
7126 23:05:46.422758 DBI_WR = 0x0
7127 23:05:46.425796 DBI_RD = 0x0
7128 23:05:46.425877 OTF = 0x1
7129 23:05:46.428975 ===================================
7130 23:05:46.432770 ===================================
7131 23:05:46.435859 ANA top config
7132 23:05:46.439197 ===================================
7133 23:05:46.442436 DLL_ASYNC_EN = 0
7134 23:05:46.442517 ALL_SLAVE_EN = 0
7135 23:05:46.445731 NEW_RANK_MODE = 1
7136 23:05:46.449501 DLL_IDLE_MODE = 1
7137 23:05:46.452631 LP45_APHY_COMB_EN = 1
7138 23:05:46.452712 TX_ODT_DIS = 0
7139 23:05:46.455610 NEW_8X_MODE = 1
7140 23:05:46.459099 ===================================
7141 23:05:46.462621 ===================================
7142 23:05:46.465481 data_rate = 3200
7143 23:05:46.468891 CKR = 1
7144 23:05:46.472225 DQ_P2S_RATIO = 8
7145 23:05:46.475927 ===================================
7146 23:05:46.479290 CA_P2S_RATIO = 8
7147 23:05:46.479372 DQ_CA_OPEN = 0
7148 23:05:46.482630 DQ_SEMI_OPEN = 0
7149 23:05:46.486263 CA_SEMI_OPEN = 0
7150 23:05:46.489316 CA_FULL_RATE = 0
7151 23:05:46.492234 DQ_CKDIV4_EN = 0
7152 23:05:46.495638 CA_CKDIV4_EN = 0
7153 23:05:46.495719 CA_PREDIV_EN = 0
7154 23:05:46.499519 PH8_DLY = 12
7155 23:05:46.502864 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7156 23:05:46.506118 DQ_AAMCK_DIV = 4
7157 23:05:46.509316 CA_AAMCK_DIV = 4
7158 23:05:46.512434 CA_ADMCK_DIV = 4
7159 23:05:46.512503 DQ_TRACK_CA_EN = 0
7160 23:05:46.515640 CA_PICK = 1600
7161 23:05:46.518859 CA_MCKIO = 1600
7162 23:05:46.521963 MCKIO_SEMI = 0
7163 23:05:46.525775 PLL_FREQ = 3068
7164 23:05:46.529079 DQ_UI_PI_RATIO = 32
7165 23:05:46.531955 CA_UI_PI_RATIO = 0
7166 23:05:46.535583 ===================================
7167 23:05:46.538695 ===================================
7168 23:05:46.538768 memory_type:LPDDR4
7169 23:05:46.541929 GP_NUM : 10
7170 23:05:46.545194 SRAM_EN : 1
7171 23:05:46.545265 MD32_EN : 0
7172 23:05:46.548588 ===================================
7173 23:05:46.552543 [ANA_INIT] >>>>>>>>>>>>>>
7174 23:05:46.555692 <<<<<< [CONFIGURE PHASE]: ANA_TX
7175 23:05:46.558863 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7176 23:05:46.562558 ===================================
7177 23:05:46.565551 data_rate = 3200,PCW = 0X7600
7178 23:05:46.569134 ===================================
7179 23:05:46.572313 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7180 23:05:46.575415 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7181 23:05:46.582148 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7182 23:05:46.585293 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7183 23:05:46.588861 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7184 23:05:46.591790 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7185 23:05:46.595439 [ANA_INIT] flow start
7186 23:05:46.598781 [ANA_INIT] PLL >>>>>>>>
7187 23:05:46.598862 [ANA_INIT] PLL <<<<<<<<
7188 23:05:46.602265 [ANA_INIT] MIDPI >>>>>>>>
7189 23:05:46.605236 [ANA_INIT] MIDPI <<<<<<<<
7190 23:05:46.608825 [ANA_INIT] DLL >>>>>>>>
7191 23:05:46.608908 [ANA_INIT] DLL <<<<<<<<
7192 23:05:46.612125 [ANA_INIT] flow end
7193 23:05:46.615377 ============ LP4 DIFF to SE enter ============
7194 23:05:46.618544 ============ LP4 DIFF to SE exit ============
7195 23:05:46.621710 [ANA_INIT] <<<<<<<<<<<<<
7196 23:05:46.624980 [Flow] Enable top DCM control >>>>>
7197 23:05:46.628917 [Flow] Enable top DCM control <<<<<
7198 23:05:46.631962 Enable DLL master slave shuffle
7199 23:05:46.635684 ==============================================================
7200 23:05:46.638513 Gating Mode config
7201 23:05:46.644942 ==============================================================
7202 23:05:46.645015 Config description:
7203 23:05:46.654934 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7204 23:05:46.662036 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7205 23:05:46.668421 SELPH_MODE 0: By rank 1: By Phase
7206 23:05:46.671894 ==============================================================
7207 23:05:46.675084 GAT_TRACK_EN = 1
7208 23:05:46.678517 RX_GATING_MODE = 2
7209 23:05:46.681872 RX_GATING_TRACK_MODE = 2
7210 23:05:46.684960 SELPH_MODE = 1
7211 23:05:46.688667 PICG_EARLY_EN = 1
7212 23:05:46.691589 VALID_LAT_VALUE = 1
7213 23:05:46.695530 ==============================================================
7214 23:05:46.698419 Enter into Gating configuration >>>>
7215 23:05:46.702000 Exit from Gating configuration <<<<
7216 23:05:46.705034 Enter into DVFS_PRE_config >>>>>
7217 23:05:46.718446 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7218 23:05:46.721703 Exit from DVFS_PRE_config <<<<<
7219 23:05:46.721777 Enter into PICG configuration >>>>
7220 23:05:46.724943 Exit from PICG configuration <<<<
7221 23:05:46.728168 [RX_INPUT] configuration >>>>>
7222 23:05:46.731415 [RX_INPUT] configuration <<<<<
7223 23:05:46.738629 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7224 23:05:46.741527 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7225 23:05:46.748219 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7226 23:05:46.755077 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7227 23:05:46.761201 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7228 23:05:46.767885 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7229 23:05:46.771718 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7230 23:05:46.774772 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7231 23:05:46.777907 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7232 23:05:46.784612 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7233 23:05:46.787748 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7234 23:05:46.791075 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7235 23:05:46.794552 ===================================
7236 23:05:46.798201 LPDDR4 DRAM CONFIGURATION
7237 23:05:46.801703 ===================================
7238 23:05:46.804851 EX_ROW_EN[0] = 0x0
7239 23:05:46.804925 EX_ROW_EN[1] = 0x0
7240 23:05:46.808128 LP4Y_EN = 0x0
7241 23:05:46.808200 WORK_FSP = 0x1
7242 23:05:46.811614 WL = 0x5
7243 23:05:46.811686 RL = 0x5
7244 23:05:46.814703 BL = 0x2
7245 23:05:46.814785 RPST = 0x0
7246 23:05:46.817789 RD_PRE = 0x0
7247 23:05:46.817855 WR_PRE = 0x1
7248 23:05:46.821412 WR_PST = 0x1
7249 23:05:46.821484 DBI_WR = 0x0
7250 23:05:46.824739 DBI_RD = 0x0
7251 23:05:46.824813 OTF = 0x1
7252 23:05:46.828273 ===================================
7253 23:05:46.834873 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7254 23:05:46.838150 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7255 23:05:46.841272 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7256 23:05:46.844599 ===================================
7257 23:05:46.848152 LPDDR4 DRAM CONFIGURATION
7258 23:05:46.851179 ===================================
7259 23:05:46.851253 EX_ROW_EN[0] = 0x10
7260 23:05:46.854767 EX_ROW_EN[1] = 0x0
7261 23:05:46.858253 LP4Y_EN = 0x0
7262 23:05:46.858326 WORK_FSP = 0x1
7263 23:05:46.861478 WL = 0x5
7264 23:05:46.861552 RL = 0x5
7265 23:05:46.864433 BL = 0x2
7266 23:05:46.864506 RPST = 0x0
7267 23:05:46.867765 RD_PRE = 0x0
7268 23:05:46.867836 WR_PRE = 0x1
7269 23:05:46.871040 WR_PST = 0x1
7270 23:05:46.871123 DBI_WR = 0x0
7271 23:05:46.874783 DBI_RD = 0x0
7272 23:05:46.874863 OTF = 0x1
7273 23:05:46.878101 ===================================
7274 23:05:46.884760 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7275 23:05:46.884843 ==
7276 23:05:46.887927 Dram Type= 6, Freq= 0, CH_0, rank 0
7277 23:05:46.891142 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7278 23:05:46.894329 ==
7279 23:05:46.894403 [Duty_Offset_Calibration]
7280 23:05:46.897526 B0:2 B1:1 CA:1
7281 23:05:46.897638
7282 23:05:46.900890 [DutyScan_Calibration_Flow] k_type=0
7283 23:05:46.909556
7284 23:05:46.909643 ==CLK 0==
7285 23:05:46.913125 Final CLK duty delay cell = 0
7286 23:05:46.916264 [0] MAX Duty = 5156%(X100), DQS PI = 22
7287 23:05:46.919537 [0] MIN Duty = 4876%(X100), DQS PI = 48
7288 23:05:46.922887 [0] AVG Duty = 5016%(X100)
7289 23:05:46.922961
7290 23:05:46.925968 CH0 CLK Duty spec in!! Max-Min= 280%
7291 23:05:46.929789 [DutyScan_Calibration_Flow] ====Done====
7292 23:05:46.929862
7293 23:05:46.932742 [DutyScan_Calibration_Flow] k_type=1
7294 23:05:46.949078
7295 23:05:46.949160 ==DQS 0 ==
7296 23:05:46.952108 Final DQS duty delay cell = -4
7297 23:05:46.955507 [-4] MAX Duty = 5156%(X100), DQS PI = 26
7298 23:05:46.958827 [-4] MIN Duty = 4688%(X100), DQS PI = 0
7299 23:05:46.962496 [-4] AVG Duty = 4922%(X100)
7300 23:05:46.962601
7301 23:05:46.962691 ==DQS 1 ==
7302 23:05:46.965469 Final DQS duty delay cell = 0
7303 23:05:46.969089 [0] MAX Duty = 5187%(X100), DQS PI = 4
7304 23:05:46.972402 [0] MIN Duty = 5031%(X100), DQS PI = 52
7305 23:05:46.975616 [0] AVG Duty = 5109%(X100)
7306 23:05:46.975688
7307 23:05:46.978882 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7308 23:05:46.978952
7309 23:05:46.982126 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7310 23:05:46.985924 [DutyScan_Calibration_Flow] ====Done====
7311 23:05:46.985996
7312 23:05:46.988886 [DutyScan_Calibration_Flow] k_type=3
7313 23:05:47.005671
7314 23:05:47.005806 ==DQM 0 ==
7315 23:05:47.009095 Final DQM duty delay cell = 0
7316 23:05:47.012236 [0] MAX Duty = 5218%(X100), DQS PI = 34
7317 23:05:47.015602 [0] MIN Duty = 4875%(X100), DQS PI = 60
7318 23:05:47.019160 [0] AVG Duty = 5046%(X100)
7319 23:05:47.019250
7320 23:05:47.019319 ==DQM 1 ==
7321 23:05:47.022026 Final DQM duty delay cell = -4
7322 23:05:47.025565 [-4] MAX Duty = 4969%(X100), DQS PI = 22
7323 23:05:47.028691 [-4] MIN Duty = 4813%(X100), DQS PI = 12
7324 23:05:47.032685 [-4] AVG Duty = 4891%(X100)
7325 23:05:47.032765
7326 23:05:47.035881 CH0 DQM 0 Duty spec in!! Max-Min= 343%
7327 23:05:47.035955
7328 23:05:47.038455 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7329 23:05:47.041804 [DutyScan_Calibration_Flow] ====Done====
7330 23:05:47.041924
7331 23:05:47.045381 [DutyScan_Calibration_Flow] k_type=2
7332 23:05:47.063227
7333 23:05:47.063319 ==DQ 0 ==
7334 23:05:47.066288 Final DQ duty delay cell = 0
7335 23:05:47.070029 [0] MAX Duty = 5062%(X100), DQS PI = 26
7336 23:05:47.073035 [0] MIN Duty = 4907%(X100), DQS PI = 0
7337 23:05:47.073116 [0] AVG Duty = 4984%(X100)
7338 23:05:47.073181
7339 23:05:47.076156 ==DQ 1 ==
7340 23:05:47.080044 Final DQ duty delay cell = 0
7341 23:05:47.083465 [0] MAX Duty = 5125%(X100), DQS PI = 6
7342 23:05:47.086579 [0] MIN Duty = 4938%(X100), DQS PI = 34
7343 23:05:47.086659 [0] AVG Duty = 5031%(X100)
7344 23:05:47.086724
7345 23:05:47.089394 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7346 23:05:47.089471
7347 23:05:47.092716 CH0 DQ 1 Duty spec in!! Max-Min= 187%
7348 23:05:47.099628 [DutyScan_Calibration_Flow] ====Done====
7349 23:05:47.099712 ==
7350 23:05:47.103166 Dram Type= 6, Freq= 0, CH_1, rank 0
7351 23:05:47.106239 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7352 23:05:47.106319 ==
7353 23:05:47.109389 [Duty_Offset_Calibration]
7354 23:05:47.109457 B0:1 B1:0 CA:0
7355 23:05:47.109518
7356 23:05:47.112676 [DutyScan_Calibration_Flow] k_type=0
7357 23:05:47.122505
7358 23:05:47.122583 ==CLK 0==
7359 23:05:47.125467 Final CLK duty delay cell = -4
7360 23:05:47.129163 [-4] MAX Duty = 4969%(X100), DQS PI = 22
7361 23:05:47.132171 [-4] MIN Duty = 4844%(X100), DQS PI = 50
7362 23:05:47.135307 [-4] AVG Duty = 4906%(X100)
7363 23:05:47.135388
7364 23:05:47.139019 CH1 CLK Duty spec in!! Max-Min= 125%
7365 23:05:47.142486 [DutyScan_Calibration_Flow] ====Done====
7366 23:05:47.142566
7367 23:05:47.145798 [DutyScan_Calibration_Flow] k_type=1
7368 23:05:47.162615
7369 23:05:47.162705 ==DQS 0 ==
7370 23:05:47.165851 Final DQS duty delay cell = 0
7371 23:05:47.169190 [0] MAX Duty = 5094%(X100), DQS PI = 16
7372 23:05:47.172137 [0] MIN Duty = 4844%(X100), DQS PI = 50
7373 23:05:47.176150 [0] AVG Duty = 4969%(X100)
7374 23:05:47.176250
7375 23:05:47.176344 ==DQS 1 ==
7376 23:05:47.179038 Final DQS duty delay cell = 0
7377 23:05:47.182055 [0] MAX Duty = 5249%(X100), DQS PI = 16
7378 23:05:47.185916 [0] MIN Duty = 4938%(X100), DQS PI = 8
7379 23:05:47.189117 [0] AVG Duty = 5093%(X100)
7380 23:05:47.189193
7381 23:05:47.192408 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7382 23:05:47.192484
7383 23:05:47.195655 CH1 DQS 1 Duty spec in!! Max-Min= 311%
7384 23:05:47.198918 [DutyScan_Calibration_Flow] ====Done====
7385 23:05:47.198994
7386 23:05:47.202386 [DutyScan_Calibration_Flow] k_type=3
7387 23:05:47.219125
7388 23:05:47.219208 ==DQM 0 ==
7389 23:05:47.222432 Final DQM duty delay cell = 0
7390 23:05:47.225588 [0] MAX Duty = 5218%(X100), DQS PI = 18
7391 23:05:47.229322 [0] MIN Duty = 4969%(X100), DQS PI = 48
7392 23:05:47.232364 [0] AVG Duty = 5093%(X100)
7393 23:05:47.232458
7394 23:05:47.232526 ==DQM 1 ==
7395 23:05:47.235878 Final DQM duty delay cell = 0
7396 23:05:47.239530 [0] MAX Duty = 5093%(X100), DQS PI = 16
7397 23:05:47.242460 [0] MIN Duty = 4907%(X100), DQS PI = 34
7398 23:05:47.245982 [0] AVG Duty = 5000%(X100)
7399 23:05:47.246061
7400 23:05:47.249437 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7401 23:05:47.249515
7402 23:05:47.252919 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7403 23:05:47.256087 [DutyScan_Calibration_Flow] ====Done====
7404 23:05:47.256167
7405 23:05:47.259389 [DutyScan_Calibration_Flow] k_type=2
7406 23:05:47.275655
7407 23:05:47.275769 ==DQ 0 ==
7408 23:05:47.278844 Final DQ duty delay cell = -4
7409 23:05:47.281784 [-4] MAX Duty = 5031%(X100), DQS PI = 10
7410 23:05:47.285366 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7411 23:05:47.288771 [-4] AVG Duty = 4953%(X100)
7412 23:05:47.288849
7413 23:05:47.288913 ==DQ 1 ==
7414 23:05:47.291977 Final DQ duty delay cell = 0
7415 23:05:47.295680 [0] MAX Duty = 5124%(X100), DQS PI = 18
7416 23:05:47.298676 [0] MIN Duty = 4938%(X100), DQS PI = 8
7417 23:05:47.301938 [0] AVG Duty = 5031%(X100)
7418 23:05:47.302017
7419 23:05:47.305233 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7420 23:05:47.305311
7421 23:05:47.308398 CH1 DQ 1 Duty spec in!! Max-Min= 186%
7422 23:05:47.311477 [DutyScan_Calibration_Flow] ====Done====
7423 23:05:47.315376 nWR fixed to 30
7424 23:05:47.318403 [ModeRegInit_LP4] CH0 RK0
7425 23:05:47.318478 [ModeRegInit_LP4] CH0 RK1
7426 23:05:47.321880 [ModeRegInit_LP4] CH1 RK0
7427 23:05:47.325300 [ModeRegInit_LP4] CH1 RK1
7428 23:05:47.325376 match AC timing 5
7429 23:05:47.331498 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7430 23:05:47.335440 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7431 23:05:47.338679 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7432 23:05:47.345155 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7433 23:05:47.348158 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7434 23:05:47.348234 [MiockJmeterHQA]
7435 23:05:47.348297
7436 23:05:47.351851 [DramcMiockJmeter] u1RxGatingPI = 0
7437 23:05:47.355065 0 : 4255, 4026
7438 23:05:47.355148 4 : 4252, 4027
7439 23:05:47.358326 8 : 4252, 4027
7440 23:05:47.358402 12 : 4252, 4026
7441 23:05:47.358471 16 : 4252, 4027
7442 23:05:47.361513 20 : 4363, 4138
7443 23:05:47.361621 24 : 4253, 4027
7444 23:05:47.365097 28 : 4252, 4026
7445 23:05:47.365173 32 : 4252, 4027
7446 23:05:47.368173 36 : 4255, 4029
7447 23:05:47.368242 40 : 4252, 4026
7448 23:05:47.372056 44 : 4363, 4138
7449 23:05:47.372132 48 : 4363, 4137
7450 23:05:47.372199 52 : 4252, 4027
7451 23:05:47.375105 56 : 4252, 4027
7452 23:05:47.375180 60 : 4252, 4027
7453 23:05:47.378422 64 : 4253, 4026
7454 23:05:47.378495 68 : 4255, 4030
7455 23:05:47.381628 72 : 4360, 4138
7456 23:05:47.381709 76 : 4250, 4027
7457 23:05:47.384640 80 : 4250, 4027
7458 23:05:47.384718 84 : 4250, 4027
7459 23:05:47.384810 88 : 4252, 84
7460 23:05:47.388138 92 : 4250, 0
7461 23:05:47.388214 96 : 4255, 0
7462 23:05:47.391162 100 : 4250, 0
7463 23:05:47.391235 104 : 4250, 0
7464 23:05:47.391296 108 : 4360, 0
7465 23:05:47.394650 112 : 4361, 0
7466 23:05:47.394727 116 : 4363, 0
7467 23:05:47.394790 120 : 4250, 0
7468 23:05:47.398231 124 : 4250, 0
7469 23:05:47.398359 128 : 4363, 0
7470 23:05:47.401601 132 : 4250, 0
7471 23:05:47.401684 136 : 4250, 0
7472 23:05:47.401749 140 : 4250, 0
7473 23:05:47.404482 144 : 4253, 0
7474 23:05:47.404560 148 : 4250, 0
7475 23:05:47.408156 152 : 4250, 0
7476 23:05:47.408296 156 : 4253, 0
7477 23:05:47.408393 160 : 4360, 0
7478 23:05:47.411472 164 : 4361, 0
7479 23:05:47.411561 168 : 4362, 0
7480 23:05:47.414759 172 : 4250, 0
7481 23:05:47.414848 176 : 4250, 0
7482 23:05:47.414914 180 : 4250, 0
7483 23:05:47.418124 184 : 4250, 0
7484 23:05:47.418201 188 : 4250, 0
7485 23:05:47.418283 192 : 4250, 0
7486 23:05:47.421660 196 : 4253, 0
7487 23:05:47.421739 200 : 4250, 0
7488 23:05:47.424543 204 : 4250, 1532
7489 23:05:47.424652 208 : 4250, 3992
7490 23:05:47.427933 212 : 4250, 4026
7491 23:05:47.428066 216 : 4250, 4027
7492 23:05:47.430934 220 : 4250, 4027
7493 23:05:47.431028 224 : 4250, 4027
7494 23:05:47.434621 228 : 4360, 4138
7495 23:05:47.434694 232 : 4250, 4027
7496 23:05:47.434758 236 : 4250, 4027
7497 23:05:47.437764 240 : 4361, 4137
7498 23:05:47.437853 244 : 4250, 4027
7499 23:05:47.441083 248 : 4250, 4027
7500 23:05:47.441159 252 : 4363, 4140
7501 23:05:47.444342 256 : 4250, 4027
7502 23:05:47.444459 260 : 4250, 4027
7503 23:05:47.447532 264 : 4250, 4027
7504 23:05:47.447612 268 : 4252, 4029
7505 23:05:47.451813 272 : 4250, 4026
7506 23:05:47.451888 276 : 4250, 4027
7507 23:05:47.454199 280 : 4360, 4138
7508 23:05:47.454338 284 : 4249, 4027
7509 23:05:47.457985 288 : 4250, 4026
7510 23:05:47.458087 292 : 4361, 4138
7511 23:05:47.458170 296 : 4250, 4027
7512 23:05:47.461122 300 : 4253, 4026
7513 23:05:47.461205 304 : 4363, 4140
7514 23:05:47.464425 308 : 4250, 3972
7515 23:05:47.464527 312 : 4250, 2071
7516 23:05:47.464597
7517 23:05:47.467711 MIOCK jitter meter ch=0
7518 23:05:47.467793
7519 23:05:47.471256 1T = (312-88) = 224 dly cells
7520 23:05:47.477867 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7521 23:05:47.477950 ==
7522 23:05:47.481005 Dram Type= 6, Freq= 0, CH_0, rank 0
7523 23:05:47.484232 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7524 23:05:47.484316 ==
7525 23:05:47.490826 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7526 23:05:47.494116 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7527 23:05:47.497461 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7528 23:05:47.504332 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7529 23:05:47.513008 [CA 0] Center 42 (12~73) winsize 62
7530 23:05:47.516398 [CA 1] Center 42 (12~73) winsize 62
7531 23:05:47.519782 [CA 2] Center 38 (8~68) winsize 61
7532 23:05:47.523069 [CA 3] Center 37 (8~67) winsize 60
7533 23:05:47.526454 [CA 4] Center 36 (6~66) winsize 61
7534 23:05:47.529967 [CA 5] Center 35 (6~64) winsize 59
7535 23:05:47.530071
7536 23:05:47.533185 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7537 23:05:47.533286
7538 23:05:47.536328 [CATrainingPosCal] consider 1 rank data
7539 23:05:47.539572 u2DelayCellTimex100 = 290/100 ps
7540 23:05:47.542748 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7541 23:05:47.549609 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7542 23:05:47.552815 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7543 23:05:47.555989 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7544 23:05:47.559794 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7545 23:05:47.562792 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7546 23:05:47.562915
7547 23:05:47.566477 CA PerBit enable=1, Macro0, CA PI delay=35
7548 23:05:47.566552
7549 23:05:47.569690 [CBTSetCACLKResult] CA Dly = 35
7550 23:05:47.572921 CS Dly: 8 (0~39)
7551 23:05:47.576197 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7552 23:05:47.579271 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7553 23:05:47.579373 ==
7554 23:05:47.582754 Dram Type= 6, Freq= 0, CH_0, rank 1
7555 23:05:47.585826 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7556 23:05:47.589074 ==
7557 23:05:47.592798 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7558 23:05:47.595993 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7559 23:05:47.602576 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7560 23:05:47.605736 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7561 23:05:47.616338 [CA 0] Center 42 (12~73) winsize 62
7562 23:05:47.619654 [CA 1] Center 42 (12~73) winsize 62
7563 23:05:47.622896 [CA 2] Center 37 (8~67) winsize 60
7564 23:05:47.626465 [CA 3] Center 38 (8~68) winsize 61
7565 23:05:47.629527 [CA 4] Center 35 (6~65) winsize 60
7566 23:05:47.633014 [CA 5] Center 35 (5~65) winsize 61
7567 23:05:47.633097
7568 23:05:47.636270 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7569 23:05:47.636353
7570 23:05:47.639720 [CATrainingPosCal] consider 2 rank data
7571 23:05:47.642900 u2DelayCellTimex100 = 290/100 ps
7572 23:05:47.646204 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7573 23:05:47.652425 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7574 23:05:47.656164 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7575 23:05:47.659195 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7576 23:05:47.662632 CA4 delay=35 (6~65),Diff = 0 PI (0 cell)
7577 23:05:47.665921 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7578 23:05:47.666005
7579 23:05:47.669196 CA PerBit enable=1, Macro0, CA PI delay=35
7580 23:05:47.669280
7581 23:05:47.672400 [CBTSetCACLKResult] CA Dly = 35
7582 23:05:47.676132 CS Dly: 9 (0~42)
7583 23:05:47.679107 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7584 23:05:47.682102 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7585 23:05:47.682182
7586 23:05:47.685513 ----->DramcWriteLeveling(PI) begin...
7587 23:05:47.685624 ==
7588 23:05:47.688847 Dram Type= 6, Freq= 0, CH_0, rank 0
7589 23:05:47.692436 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7590 23:05:47.695602 ==
7591 23:05:47.699492 Write leveling (Byte 0): 35 => 35
7592 23:05:47.699567 Write leveling (Byte 1): 28 => 28
7593 23:05:47.702326 DramcWriteLeveling(PI) end<-----
7594 23:05:47.702429
7595 23:05:47.702519 ==
7596 23:05:47.705928 Dram Type= 6, Freq= 0, CH_0, rank 0
7597 23:05:47.712511 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7598 23:05:47.712616 ==
7599 23:05:47.715604 [Gating] SW mode calibration
7600 23:05:47.722387 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7601 23:05:47.725450 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7602 23:05:47.732206 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7603 23:05:47.735625 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7604 23:05:47.738894 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 1)
7605 23:05:47.745678 1 4 12 | B1->B0 | 2323 3231 | 0 1 | (0 0) (0 0)
7606 23:05:47.749020 1 4 16 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
7607 23:05:47.751758 1 4 20 | B1->B0 | 3333 3737 | 1 0 | (1 1) (0 0)
7608 23:05:47.759024 1 4 24 | B1->B0 | 3434 3636 | 1 0 | (1 1) (1 1)
7609 23:05:47.762130 1 4 28 | B1->B0 | 3434 3535 | 1 0 | (1 1) (1 1)
7610 23:05:47.765303 1 5 0 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7611 23:05:47.771727 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7612 23:05:47.775582 1 5 8 | B1->B0 | 3434 3737 | 1 0 | (1 1) (0 1)
7613 23:05:47.778423 1 5 12 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 0)
7614 23:05:47.782028 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7615 23:05:47.788741 1 5 20 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
7616 23:05:47.791663 1 5 24 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
7617 23:05:47.795313 1 5 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7618 23:05:47.801734 1 6 0 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7619 23:05:47.805180 1 6 4 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7620 23:05:47.808607 1 6 8 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (0 0)
7621 23:05:47.814865 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7622 23:05:47.818816 1 6 16 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)
7623 23:05:47.821941 1 6 20 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7624 23:05:47.828681 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7625 23:05:47.832106 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7626 23:05:47.835442 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7627 23:05:47.841862 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7628 23:05:47.845012 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7629 23:05:47.848498 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7630 23:05:47.855044 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7631 23:05:47.858360 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7632 23:05:47.861428 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7633 23:05:47.868472 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7634 23:05:47.871743 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7635 23:05:47.875016 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7636 23:05:47.882001 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7637 23:05:47.885236 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7638 23:05:47.888338 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7639 23:05:47.894922 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7640 23:05:47.898499 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7641 23:05:47.901458 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7642 23:05:47.908132 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7643 23:05:47.911860 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7644 23:05:47.915526 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7645 23:05:47.918426 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7646 23:05:47.925190 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7647 23:05:47.928106 Total UI for P1: 0, mck2ui 16
7648 23:05:47.931780 best dqsien dly found for B0: ( 1, 9, 12)
7649 23:05:47.934977 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7650 23:05:47.938374 Total UI for P1: 0, mck2ui 16
7651 23:05:47.941487 best dqsien dly found for B1: ( 1, 9, 18)
7652 23:05:47.944864 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7653 23:05:47.948562 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7654 23:05:47.948647
7655 23:05:47.951719 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7656 23:05:47.955020 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7657 23:05:47.958153 [Gating] SW calibration Done
7658 23:05:47.958238 ==
7659 23:05:47.961488 Dram Type= 6, Freq= 0, CH_0, rank 0
7660 23:05:47.968261 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7661 23:05:47.968372 ==
7662 23:05:47.968467 RX Vref Scan: 0
7663 23:05:47.968557
7664 23:05:47.971326 RX Vref 0 -> 0, step: 1
7665 23:05:47.971425
7666 23:05:47.975042 RX Delay 0 -> 252, step: 8
7667 23:05:47.978443 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7668 23:05:47.981798 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7669 23:05:47.984999 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7670 23:05:47.988199 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7671 23:05:47.994409 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7672 23:05:47.998157 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7673 23:05:48.001368 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7674 23:05:48.004522 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7675 23:05:48.007981 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7676 23:05:48.014273 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
7677 23:05:48.017964 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7678 23:05:48.020887 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7679 23:05:48.024570 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
7680 23:05:48.027643 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
7681 23:05:48.034631 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7682 23:05:48.037967 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7683 23:05:48.038048 ==
7684 23:05:48.041269 Dram Type= 6, Freq= 0, CH_0, rank 0
7685 23:05:48.044793 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7686 23:05:48.044893 ==
7687 23:05:48.047918 DQS Delay:
7688 23:05:48.048018 DQS0 = 0, DQS1 = 0
7689 23:05:48.048108 DQM Delay:
7690 23:05:48.051063 DQM0 = 136, DQM1 = 131
7691 23:05:48.051137 DQ Delay:
7692 23:05:48.054228 DQ0 =135, DQ1 =143, DQ2 =131, DQ3 =131
7693 23:05:48.057795 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7694 23:05:48.061307 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =123
7695 23:05:48.067709 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =135
7696 23:05:48.067788
7697 23:05:48.067852
7698 23:05:48.067921 ==
7699 23:05:48.070905 Dram Type= 6, Freq= 0, CH_0, rank 0
7700 23:05:48.074402 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7701 23:05:48.074478 ==
7702 23:05:48.074541
7703 23:05:48.074606
7704 23:05:48.077350 TX Vref Scan disable
7705 23:05:48.077450 == TX Byte 0 ==
7706 23:05:48.084351 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7707 23:05:48.087782 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7708 23:05:48.087857 == TX Byte 1 ==
7709 23:05:48.094437 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7710 23:05:48.097610 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7711 23:05:48.097733 ==
7712 23:05:48.101065 Dram Type= 6, Freq= 0, CH_0, rank 0
7713 23:05:48.104147 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7714 23:05:48.104254 ==
7715 23:05:48.117749
7716 23:05:48.121130 TX Vref early break, caculate TX vref
7717 23:05:48.124538 TX Vref=16, minBit 1, minWin=23, winSum=379
7718 23:05:48.127652 TX Vref=18, minBit 8, minWin=23, winSum=389
7719 23:05:48.131276 TX Vref=20, minBit 0, minWin=24, winSum=401
7720 23:05:48.134293 TX Vref=22, minBit 0, minWin=24, winSum=410
7721 23:05:48.137319 TX Vref=24, minBit 1, minWin=25, winSum=416
7722 23:05:48.144298 TX Vref=26, minBit 2, minWin=25, winSum=424
7723 23:05:48.147433 TX Vref=28, minBit 2, minWin=25, winSum=424
7724 23:05:48.150872 TX Vref=30, minBit 6, minWin=24, winSum=413
7725 23:05:48.154185 TX Vref=32, minBit 2, minWin=23, winSum=400
7726 23:05:48.160962 [TxChooseVref] Worse bit 2, Min win 25, Win sum 424, Final Vref 26
7727 23:05:48.161076
7728 23:05:48.164234 Final TX Range 0 Vref 26
7729 23:05:48.164337
7730 23:05:48.164426 ==
7731 23:05:48.167660 Dram Type= 6, Freq= 0, CH_0, rank 0
7732 23:05:48.171066 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7733 23:05:48.171148 ==
7734 23:05:48.171228
7735 23:05:48.171302
7736 23:05:48.174242 TX Vref Scan disable
7737 23:05:48.177744 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7738 23:05:48.180573 == TX Byte 0 ==
7739 23:05:48.184537 u2DelayCellOfst[0]=13 cells (4 PI)
7740 23:05:48.187901 u2DelayCellOfst[1]=16 cells (5 PI)
7741 23:05:48.190989 u2DelayCellOfst[2]=13 cells (4 PI)
7742 23:05:48.194079 u2DelayCellOfst[3]=10 cells (3 PI)
7743 23:05:48.197355 u2DelayCellOfst[4]=10 cells (3 PI)
7744 23:05:48.200508 u2DelayCellOfst[5]=0 cells (0 PI)
7745 23:05:48.200591 u2DelayCellOfst[6]=20 cells (6 PI)
7746 23:05:48.203991 u2DelayCellOfst[7]=20 cells (6 PI)
7747 23:05:48.210991 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7748 23:05:48.214079 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7749 23:05:48.214164 == TX Byte 1 ==
7750 23:05:48.217871 u2DelayCellOfst[8]=0 cells (0 PI)
7751 23:05:48.220991 u2DelayCellOfst[9]=0 cells (0 PI)
7752 23:05:48.224143 u2DelayCellOfst[10]=6 cells (2 PI)
7753 23:05:48.227305 u2DelayCellOfst[11]=3 cells (1 PI)
7754 23:05:48.230997 u2DelayCellOfst[12]=10 cells (3 PI)
7755 23:05:48.234305 u2DelayCellOfst[13]=13 cells (4 PI)
7756 23:05:48.237551 u2DelayCellOfst[14]=16 cells (5 PI)
7757 23:05:48.240917 u2DelayCellOfst[15]=10 cells (3 PI)
7758 23:05:48.244087 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7759 23:05:48.247075 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7760 23:05:48.250440 DramC Write-DBI on
7761 23:05:48.250523 ==
7762 23:05:48.254410 Dram Type= 6, Freq= 0, CH_0, rank 0
7763 23:05:48.257214 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7764 23:05:48.257301 ==
7765 23:05:48.257368
7766 23:05:48.257428
7767 23:05:48.260324 TX Vref Scan disable
7768 23:05:48.263978 == TX Byte 0 ==
7769 23:05:48.267351 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7770 23:05:48.270588 == TX Byte 1 ==
7771 23:05:48.273820 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7772 23:05:48.273905 DramC Write-DBI off
7773 23:05:48.273972
7774 23:05:48.277874 [DATLAT]
7775 23:05:48.277987 Freq=1600, CH0 RK0
7776 23:05:48.278086
7777 23:05:48.280457 DATLAT Default: 0xf
7778 23:05:48.280557 0, 0xFFFF, sum = 0
7779 23:05:48.283817 1, 0xFFFF, sum = 0
7780 23:05:48.283902 2, 0xFFFF, sum = 0
7781 23:05:48.287011 3, 0xFFFF, sum = 0
7782 23:05:48.287096 4, 0xFFFF, sum = 0
7783 23:05:48.290219 5, 0xFFFF, sum = 0
7784 23:05:48.290304 6, 0xFFFF, sum = 0
7785 23:05:48.293509 7, 0xFFFF, sum = 0
7786 23:05:48.293603 8, 0xFFFF, sum = 0
7787 23:05:48.296851 9, 0xFFFF, sum = 0
7788 23:05:48.300395 10, 0xFFFF, sum = 0
7789 23:05:48.300485 11, 0xFFFF, sum = 0
7790 23:05:48.304102 12, 0xFFFF, sum = 0
7791 23:05:48.304186 13, 0xFFFF, sum = 0
7792 23:05:48.307053 14, 0x0, sum = 1
7793 23:05:48.307136 15, 0x0, sum = 2
7794 23:05:48.310741 16, 0x0, sum = 3
7795 23:05:48.310825 17, 0x0, sum = 4
7796 23:05:48.310891 best_step = 15
7797 23:05:48.310952
7798 23:05:48.313513 ==
7799 23:05:48.317633 Dram Type= 6, Freq= 0, CH_0, rank 0
7800 23:05:48.320802 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7801 23:05:48.320885 ==
7802 23:05:48.320952 RX Vref Scan: 1
7803 23:05:48.321014
7804 23:05:48.324047 Set Vref Range= 24 -> 127
7805 23:05:48.324130
7806 23:05:48.327324 RX Vref 24 -> 127, step: 1
7807 23:05:48.327408
7808 23:05:48.330614 RX Delay 27 -> 252, step: 4
7809 23:05:48.330698
7810 23:05:48.333967 Set Vref, RX VrefLevel [Byte0]: 24
7811 23:05:48.336955 [Byte1]: 24
7812 23:05:48.337052
7813 23:05:48.340375 Set Vref, RX VrefLevel [Byte0]: 25
7814 23:05:48.343913 [Byte1]: 25
7815 23:05:48.343997
7816 23:05:48.346850 Set Vref, RX VrefLevel [Byte0]: 26
7817 23:05:48.350188 [Byte1]: 26
7818 23:05:48.353599
7819 23:05:48.353703 Set Vref, RX VrefLevel [Byte0]: 27
7820 23:05:48.356647 [Byte1]: 27
7821 23:05:48.361026
7822 23:05:48.361109 Set Vref, RX VrefLevel [Byte0]: 28
7823 23:05:48.364250 [Byte1]: 28
7824 23:05:48.368576
7825 23:05:48.368659 Set Vref, RX VrefLevel [Byte0]: 29
7826 23:05:48.371872 [Byte1]: 29
7827 23:05:48.376075
7828 23:05:48.376184 Set Vref, RX VrefLevel [Byte0]: 30
7829 23:05:48.379324 [Byte1]: 30
7830 23:05:48.383969
7831 23:05:48.384052 Set Vref, RX VrefLevel [Byte0]: 31
7832 23:05:48.387148 [Byte1]: 31
7833 23:05:48.391466
7834 23:05:48.391548 Set Vref, RX VrefLevel [Byte0]: 32
7835 23:05:48.394806 [Byte1]: 32
7836 23:05:48.398620
7837 23:05:48.398702 Set Vref, RX VrefLevel [Byte0]: 33
7838 23:05:48.401926 [Byte1]: 33
7839 23:05:48.406350
7840 23:05:48.406432 Set Vref, RX VrefLevel [Byte0]: 34
7841 23:05:48.409774 [Byte1]: 34
7842 23:05:48.414015
7843 23:05:48.414129 Set Vref, RX VrefLevel [Byte0]: 35
7844 23:05:48.417173 [Byte1]: 35
7845 23:05:48.421106
7846 23:05:48.421188 Set Vref, RX VrefLevel [Byte0]: 36
7847 23:05:48.424444 [Byte1]: 36
7848 23:05:48.429204
7849 23:05:48.429288 Set Vref, RX VrefLevel [Byte0]: 37
7850 23:05:48.432522 [Byte1]: 37
7851 23:05:48.436676
7852 23:05:48.436762 Set Vref, RX VrefLevel [Byte0]: 38
7853 23:05:48.439705 [Byte1]: 38
7854 23:05:48.443823
7855 23:05:48.443911 Set Vref, RX VrefLevel [Byte0]: 39
7856 23:05:48.447038 [Byte1]: 39
7857 23:05:48.451445
7858 23:05:48.451531 Set Vref, RX VrefLevel [Byte0]: 40
7859 23:05:48.454949 [Byte1]: 40
7860 23:05:48.458902
7861 23:05:48.458986 Set Vref, RX VrefLevel [Byte0]: 41
7862 23:05:48.462182 [Byte1]: 41
7863 23:05:48.466387
7864 23:05:48.466471 Set Vref, RX VrefLevel [Byte0]: 42
7865 23:05:48.469971 [Byte1]: 42
7866 23:05:48.474379
7867 23:05:48.474463 Set Vref, RX VrefLevel [Byte0]: 43
7868 23:05:48.477264 [Byte1]: 43
7869 23:05:48.481933
7870 23:05:48.482030 Set Vref, RX VrefLevel [Byte0]: 44
7871 23:05:48.485160 [Byte1]: 44
7872 23:05:48.489222
7873 23:05:48.489331 Set Vref, RX VrefLevel [Byte0]: 45
7874 23:05:48.492395 [Byte1]: 45
7875 23:05:48.496427
7876 23:05:48.496528 Set Vref, RX VrefLevel [Byte0]: 46
7877 23:05:48.499869 [Byte1]: 46
7878 23:05:48.504401
7879 23:05:48.504475 Set Vref, RX VrefLevel [Byte0]: 47
7880 23:05:48.507590 [Byte1]: 47
7881 23:05:48.511841
7882 23:05:48.511922 Set Vref, RX VrefLevel [Byte0]: 48
7883 23:05:48.515243 [Byte1]: 48
7884 23:05:48.519155
7885 23:05:48.519236 Set Vref, RX VrefLevel [Byte0]: 49
7886 23:05:48.522247 [Byte1]: 49
7887 23:05:48.526828
7888 23:05:48.526974 Set Vref, RX VrefLevel [Byte0]: 50
7889 23:05:48.530424 [Byte1]: 50
7890 23:05:48.534267
7891 23:05:48.534368 Set Vref, RX VrefLevel [Byte0]: 51
7892 23:05:48.537894 [Byte1]: 51
7893 23:05:48.541531
7894 23:05:48.541662 Set Vref, RX VrefLevel [Byte0]: 52
7895 23:05:48.544897 [Byte1]: 52
7896 23:05:48.549519
7897 23:05:48.549674 Set Vref, RX VrefLevel [Byte0]: 53
7898 23:05:48.552647 [Byte1]: 53
7899 23:05:48.557168
7900 23:05:48.557275 Set Vref, RX VrefLevel [Byte0]: 54
7901 23:05:48.560315 [Byte1]: 54
7902 23:05:48.564211
7903 23:05:48.564317 Set Vref, RX VrefLevel [Byte0]: 55
7904 23:05:48.567746 [Byte1]: 55
7905 23:05:48.571757
7906 23:05:48.571864 Set Vref, RX VrefLevel [Byte0]: 56
7907 23:05:48.575570 [Byte1]: 56
7908 23:05:48.579879
7909 23:05:48.580003 Set Vref, RX VrefLevel [Byte0]: 57
7910 23:05:48.583175 [Byte1]: 57
7911 23:05:48.587268
7912 23:05:48.587355 Set Vref, RX VrefLevel [Byte0]: 58
7913 23:05:48.590229 [Byte1]: 58
7914 23:05:48.594706
7915 23:05:48.594789 Set Vref, RX VrefLevel [Byte0]: 59
7916 23:05:48.598063 [Byte1]: 59
7917 23:05:48.602523
7918 23:05:48.602608 Set Vref, RX VrefLevel [Byte0]: 60
7919 23:05:48.605680 [Byte1]: 60
7920 23:05:48.609548
7921 23:05:48.609646 Set Vref, RX VrefLevel [Byte0]: 61
7922 23:05:48.612854 [Byte1]: 61
7923 23:05:48.617475
7924 23:05:48.617591 Set Vref, RX VrefLevel [Byte0]: 62
7925 23:05:48.620531 [Byte1]: 62
7926 23:05:48.624979
7927 23:05:48.625062 Set Vref, RX VrefLevel [Byte0]: 63
7928 23:05:48.628028 [Byte1]: 63
7929 23:05:48.632350
7930 23:05:48.632433 Set Vref, RX VrefLevel [Byte0]: 64
7931 23:05:48.635800 [Byte1]: 64
7932 23:05:48.640060
7933 23:05:48.640143 Set Vref, RX VrefLevel [Byte0]: 65
7934 23:05:48.643064 [Byte1]: 65
7935 23:05:48.647469
7936 23:05:48.647552 Set Vref, RX VrefLevel [Byte0]: 66
7937 23:05:48.650573 [Byte1]: 66
7938 23:05:48.654844
7939 23:05:48.654927 Set Vref, RX VrefLevel [Byte0]: 67
7940 23:05:48.658175 [Byte1]: 67
7941 23:05:48.662631
7942 23:05:48.662712 Set Vref, RX VrefLevel [Byte0]: 68
7943 23:05:48.665820 [Byte1]: 68
7944 23:05:48.670140
7945 23:05:48.670221 Set Vref, RX VrefLevel [Byte0]: 69
7946 23:05:48.673277 [Byte1]: 69
7947 23:05:48.677539
7948 23:05:48.677639 Set Vref, RX VrefLevel [Byte0]: 70
7949 23:05:48.680524 [Byte1]: 70
7950 23:05:48.685249
7951 23:05:48.685329 Set Vref, RX VrefLevel [Byte0]: 71
7952 23:05:48.688255 [Byte1]: 71
7953 23:05:48.692727
7954 23:05:48.692808 Set Vref, RX VrefLevel [Byte0]: 72
7955 23:05:48.695858 [Byte1]: 72
7956 23:05:48.699978
7957 23:05:48.700058 Set Vref, RX VrefLevel [Byte0]: 73
7958 23:05:48.703595 [Byte1]: 73
7959 23:05:48.707565
7960 23:05:48.707689 Set Vref, RX VrefLevel [Byte0]: 74
7961 23:05:48.710771 [Byte1]: 74
7962 23:05:48.715145
7963 23:05:48.715294 Final RX Vref Byte 0 = 60 to rank0
7964 23:05:48.718430 Final RX Vref Byte 1 = 57 to rank0
7965 23:05:48.721450 Final RX Vref Byte 0 = 60 to rank1
7966 23:05:48.724808 Final RX Vref Byte 1 = 57 to rank1==
7967 23:05:48.728613 Dram Type= 6, Freq= 0, CH_0, rank 0
7968 23:05:48.734750 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7969 23:05:48.734831 ==
7970 23:05:48.734895 DQS Delay:
7971 23:05:48.738848 DQS0 = 0, DQS1 = 0
7972 23:05:48.738929 DQM Delay:
7973 23:05:48.738993 DQM0 = 134, DQM1 = 127
7974 23:05:48.741836 DQ Delay:
7975 23:05:48.745048 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =132
7976 23:05:48.748757 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =140
7977 23:05:48.751761 DQ8 =118, DQ9 =118, DQ10 =128, DQ11 =120
7978 23:05:48.755133 DQ12 =132, DQ13 =134, DQ14 =138, DQ15 =134
7979 23:05:48.755213
7980 23:05:48.755276
7981 23:05:48.755334
7982 23:05:48.758427 [DramC_TX_OE_Calibration] TA2
7983 23:05:48.761546 Original DQ_B0 (3 6) =30, OEN = 27
7984 23:05:48.765473 Original DQ_B1 (3 6) =30, OEN = 27
7985 23:05:48.768640 24, 0x0, End_B0=24 End_B1=24
7986 23:05:48.768721 25, 0x0, End_B0=25 End_B1=25
7987 23:05:48.771654 26, 0x0, End_B0=26 End_B1=26
7988 23:05:48.774908 27, 0x0, End_B0=27 End_B1=27
7989 23:05:48.777932 28, 0x0, End_B0=28 End_B1=28
7990 23:05:48.781854 29, 0x0, End_B0=29 End_B1=29
7991 23:05:48.781936 30, 0x0, End_B0=30 End_B1=30
7992 23:05:48.785078 31, 0x4545, End_B0=30 End_B1=30
7993 23:05:48.788076 Byte0 end_step=30 best_step=27
7994 23:05:48.791690 Byte1 end_step=30 best_step=27
7995 23:05:48.794970 Byte0 TX OE(2T, 0.5T) = (3, 3)
7996 23:05:48.798272 Byte1 TX OE(2T, 0.5T) = (3, 3)
7997 23:05:48.798425
7998 23:05:48.798592
7999 23:05:48.804758 [DQSOSCAuto] RK0, (LSB)MR18= 0x2722, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
8000 23:05:48.808036 CH0 RK0: MR19=303, MR18=2722
8001 23:05:48.815123 CH0_RK0: MR19=0x303, MR18=0x2722, DQSOSC=390, MR23=63, INC=24, DEC=16
8002 23:05:48.815279
8003 23:05:48.818409 ----->DramcWriteLeveling(PI) begin...
8004 23:05:48.818491 ==
8005 23:05:48.821457 Dram Type= 6, Freq= 0, CH_0, rank 1
8006 23:05:48.824771 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8007 23:05:48.824870 ==
8008 23:05:48.828027 Write leveling (Byte 0): 36 => 36
8009 23:05:48.831321 Write leveling (Byte 1): 26 => 26
8010 23:05:48.834697 DramcWriteLeveling(PI) end<-----
8011 23:05:48.834778
8012 23:05:48.834842 ==
8013 23:05:48.837707 Dram Type= 6, Freq= 0, CH_0, rank 1
8014 23:05:48.841163 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8015 23:05:48.841284 ==
8016 23:05:48.844275 [Gating] SW mode calibration
8017 23:05:48.851148 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8018 23:05:48.858151 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8019 23:05:48.860812 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8020 23:05:48.864500 1 4 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8021 23:05:48.871228 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8022 23:05:48.874568 1 4 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8023 23:05:48.877464 1 4 16 | B1->B0 | 2d2d 3535 | 0 1 | (0 0) (0 0)
8024 23:05:48.883914 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8025 23:05:48.887511 1 4 24 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
8026 23:05:48.890535 1 4 28 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
8027 23:05:48.897472 1 5 0 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
8028 23:05:48.900752 1 5 4 | B1->B0 | 3434 3838 | 1 1 | (1 1) (0 0)
8029 23:05:48.904307 1 5 8 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 0)
8030 23:05:48.910605 1 5 12 | B1->B0 | 3434 3535 | 1 1 | (1 0) (1 0)
8031 23:05:48.914051 1 5 16 | B1->B0 | 2e2e 2525 | 0 0 | (1 1) (0 0)
8032 23:05:48.918020 1 5 20 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8033 23:05:48.924369 1 5 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8034 23:05:48.927792 1 5 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8035 23:05:48.930882 1 6 0 | B1->B0 | 2323 2827 | 0 1 | (0 0) (0 0)
8036 23:05:48.937413 1 6 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
8037 23:05:48.941033 1 6 8 | B1->B0 | 2323 2525 | 0 1 | (0 0) (1 1)
8038 23:05:48.944001 1 6 12 | B1->B0 | 2323 3131 | 0 1 | (0 0) (0 0)
8039 23:05:48.951054 1 6 16 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
8040 23:05:48.954092 1 6 20 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
8041 23:05:48.957596 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8042 23:05:48.964183 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8043 23:05:48.967386 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8044 23:05:48.970538 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8045 23:05:48.977351 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8046 23:05:48.980666 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8047 23:05:48.983650 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8048 23:05:48.990786 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8049 23:05:48.993884 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8050 23:05:48.997087 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8051 23:05:49.004109 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8052 23:05:49.007048 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8053 23:05:49.011021 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8054 23:05:49.013899 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8055 23:05:49.020754 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8056 23:05:49.024157 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8057 23:05:49.027305 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8058 23:05:49.033782 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8059 23:05:49.037114 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8060 23:05:49.040767 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8061 23:05:49.047018 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8062 23:05:49.050159 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8063 23:05:49.053978 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8064 23:05:49.057127 Total UI for P1: 0, mck2ui 16
8065 23:05:49.060764 best dqsien dly found for B0: ( 1, 9, 12)
8066 23:05:49.066947 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8067 23:05:49.067033 Total UI for P1: 0, mck2ui 16
8068 23:05:49.073457 best dqsien dly found for B1: ( 1, 9, 14)
8069 23:05:49.077135 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8070 23:05:49.080295 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8071 23:05:49.080380
8072 23:05:49.083437 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8073 23:05:49.087232 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8074 23:05:49.090450 [Gating] SW calibration Done
8075 23:05:49.090535 ==
8076 23:05:49.093688 Dram Type= 6, Freq= 0, CH_0, rank 1
8077 23:05:49.096703 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8078 23:05:49.096789 ==
8079 23:05:49.100021 RX Vref Scan: 0
8080 23:05:49.100130
8081 23:05:49.100232 RX Vref 0 -> 0, step: 1
8082 23:05:49.100331
8083 23:05:49.103344 RX Delay 0 -> 252, step: 8
8084 23:05:49.107174 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8085 23:05:49.113278 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8086 23:05:49.116829 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8087 23:05:49.120013 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8088 23:05:49.123172 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8089 23:05:49.126950 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8090 23:05:49.133818 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8091 23:05:49.136804 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8092 23:05:49.140202 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8093 23:05:49.143597 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8094 23:05:49.146835 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8095 23:05:49.153028 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8096 23:05:49.156533 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8097 23:05:49.160307 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8098 23:05:49.163250 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8099 23:05:49.170305 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8100 23:05:49.170412 ==
8101 23:05:49.173564 Dram Type= 6, Freq= 0, CH_0, rank 1
8102 23:05:49.176862 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8103 23:05:49.176947 ==
8104 23:05:49.177033 DQS Delay:
8105 23:05:49.180288 DQS0 = 0, DQS1 = 0
8106 23:05:49.180373 DQM Delay:
8107 23:05:49.183059 DQM0 = 137, DQM1 = 129
8108 23:05:49.183145 DQ Delay:
8109 23:05:49.186562 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8110 23:05:49.190049 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8111 23:05:49.192933 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =119
8112 23:05:49.196878 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =139
8113 23:05:49.196964
8114 23:05:49.197066
8115 23:05:49.197147 ==
8116 23:05:49.199813 Dram Type= 6, Freq= 0, CH_0, rank 1
8117 23:05:49.206345 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8118 23:05:49.206433 ==
8119 23:05:49.206519
8120 23:05:49.206604
8121 23:05:49.206702 TX Vref Scan disable
8122 23:05:49.210348 == TX Byte 0 ==
8123 23:05:49.213534 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8124 23:05:49.219995 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8125 23:05:49.220121 == TX Byte 1 ==
8126 23:05:49.223900 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8127 23:05:49.230045 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8128 23:05:49.230161 ==
8129 23:05:49.233280 Dram Type= 6, Freq= 0, CH_0, rank 1
8130 23:05:49.236573 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8131 23:05:49.236656 ==
8132 23:05:49.251442
8133 23:05:49.255181 TX Vref early break, caculate TX vref
8134 23:05:49.258230 TX Vref=16, minBit 3, minWin=22, winSum=384
8135 23:05:49.261765 TX Vref=18, minBit 1, minWin=23, winSum=393
8136 23:05:49.264804 TX Vref=20, minBit 0, minWin=24, winSum=406
8137 23:05:49.268075 TX Vref=22, minBit 3, minWin=24, winSum=410
8138 23:05:49.271443 TX Vref=24, minBit 4, minWin=25, winSum=423
8139 23:05:49.278516 TX Vref=26, minBit 1, minWin=24, winSum=422
8140 23:05:49.281340 TX Vref=28, minBit 0, minWin=25, winSum=423
8141 23:05:49.284849 TX Vref=30, minBit 1, minWin=25, winSum=419
8142 23:05:49.288548 TX Vref=32, minBit 0, minWin=24, winSum=407
8143 23:05:49.291469 TX Vref=34, minBit 1, minWin=24, winSum=401
8144 23:05:49.295006 TX Vref=36, minBit 0, minWin=23, winSum=391
8145 23:05:49.301291 [TxChooseVref] Worse bit 4, Min win 25, Win sum 423, Final Vref 24
8146 23:05:49.301374
8147 23:05:49.304762 Final TX Range 0 Vref 24
8148 23:05:49.304844
8149 23:05:49.304909 ==
8150 23:05:49.308344 Dram Type= 6, Freq= 0, CH_0, rank 1
8151 23:05:49.311450 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8152 23:05:49.311533 ==
8153 23:05:49.311598
8154 23:05:49.311658
8155 23:05:49.314623 TX Vref Scan disable
8156 23:05:49.321470 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8157 23:05:49.321584 == TX Byte 0 ==
8158 23:05:49.324748 u2DelayCellOfst[0]=10 cells (3 PI)
8159 23:05:49.328054 u2DelayCellOfst[1]=13 cells (4 PI)
8160 23:05:49.331119 u2DelayCellOfst[2]=6 cells (2 PI)
8161 23:05:49.334555 u2DelayCellOfst[3]=10 cells (3 PI)
8162 23:05:49.337959 u2DelayCellOfst[4]=6 cells (2 PI)
8163 23:05:49.341489 u2DelayCellOfst[5]=0 cells (0 PI)
8164 23:05:49.344667 u2DelayCellOfst[6]=13 cells (4 PI)
8165 23:05:49.347922 u2DelayCellOfst[7]=13 cells (4 PI)
8166 23:05:49.350998 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8167 23:05:49.354237 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8168 23:05:49.357736 == TX Byte 1 ==
8169 23:05:49.361221 u2DelayCellOfst[8]=0 cells (0 PI)
8170 23:05:49.364230 u2DelayCellOfst[9]=0 cells (0 PI)
8171 23:05:49.364312 u2DelayCellOfst[10]=6 cells (2 PI)
8172 23:05:49.367802 u2DelayCellOfst[11]=6 cells (2 PI)
8173 23:05:49.370788 u2DelayCellOfst[12]=10 cells (3 PI)
8174 23:05:49.374495 u2DelayCellOfst[13]=10 cells (3 PI)
8175 23:05:49.377600 u2DelayCellOfst[14]=16 cells (5 PI)
8176 23:05:49.380757 u2DelayCellOfst[15]=10 cells (3 PI)
8177 23:05:49.387780 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8178 23:05:49.390992 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8179 23:05:49.391075 DramC Write-DBI on
8180 23:05:49.391141 ==
8181 23:05:49.394079 Dram Type= 6, Freq= 0, CH_0, rank 1
8182 23:05:49.400595 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8183 23:05:49.400678 ==
8184 23:05:49.400743
8185 23:05:49.400803
8186 23:05:49.400861 TX Vref Scan disable
8187 23:05:49.405153 == TX Byte 0 ==
8188 23:05:49.408630 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8189 23:05:49.411742 == TX Byte 1 ==
8190 23:05:49.415019 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8191 23:05:49.418404 DramC Write-DBI off
8192 23:05:49.418486
8193 23:05:49.418551 [DATLAT]
8194 23:05:49.418612 Freq=1600, CH0 RK1
8195 23:05:49.418672
8196 23:05:49.421634 DATLAT Default: 0xf
8197 23:05:49.421716 0, 0xFFFF, sum = 0
8198 23:05:49.424784 1, 0xFFFF, sum = 0
8199 23:05:49.424867 2, 0xFFFF, sum = 0
8200 23:05:49.428411 3, 0xFFFF, sum = 0
8201 23:05:49.431828 4, 0xFFFF, sum = 0
8202 23:05:49.431912 5, 0xFFFF, sum = 0
8203 23:05:49.434816 6, 0xFFFF, sum = 0
8204 23:05:49.434900 7, 0xFFFF, sum = 0
8205 23:05:49.438190 8, 0xFFFF, sum = 0
8206 23:05:49.438276 9, 0xFFFF, sum = 0
8207 23:05:49.441494 10, 0xFFFF, sum = 0
8208 23:05:49.441638 11, 0xFFFF, sum = 0
8209 23:05:49.445095 12, 0xFFFF, sum = 0
8210 23:05:49.445178 13, 0xFFFF, sum = 0
8211 23:05:49.447982 14, 0x0, sum = 1
8212 23:05:49.448065 15, 0x0, sum = 2
8213 23:05:49.451743 16, 0x0, sum = 3
8214 23:05:49.451825 17, 0x0, sum = 4
8215 23:05:49.455106 best_step = 15
8216 23:05:49.455188
8217 23:05:49.455253 ==
8218 23:05:49.458398 Dram Type= 6, Freq= 0, CH_0, rank 1
8219 23:05:49.461723 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8220 23:05:49.461807 ==
8221 23:05:49.461877 RX Vref Scan: 0
8222 23:05:49.465021
8223 23:05:49.465103 RX Vref 0 -> 0, step: 1
8224 23:05:49.465168
8225 23:05:49.468252 RX Delay 19 -> 252, step: 4
8226 23:05:49.471854 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8227 23:05:49.478179 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8228 23:05:49.481149 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8229 23:05:49.484905 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8230 23:05:49.487942 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8231 23:05:49.491197 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8232 23:05:49.498401 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8233 23:05:49.501533 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8234 23:05:49.504399 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8235 23:05:49.507916 iDelay=191, Bit 9, Center 116 (63 ~ 170) 108
8236 23:05:49.511260 iDelay=191, Bit 10, Center 126 (75 ~ 178) 104
8237 23:05:49.518064 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8238 23:05:49.521162 iDelay=191, Bit 12, Center 132 (83 ~ 182) 100
8239 23:05:49.524568 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8240 23:05:49.528045 iDelay=191, Bit 14, Center 138 (87 ~ 190) 104
8241 23:05:49.531244 iDelay=191, Bit 15, Center 134 (83 ~ 186) 104
8242 23:05:49.534695 ==
8243 23:05:49.538306 Dram Type= 6, Freq= 0, CH_0, rank 1
8244 23:05:49.541457 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8245 23:05:49.541568 ==
8246 23:05:49.541660 DQS Delay:
8247 23:05:49.544850 DQS0 = 0, DQS1 = 0
8248 23:05:49.544931 DQM Delay:
8249 23:05:49.548178 DQM0 = 134, DQM1 = 127
8250 23:05:49.548260 DQ Delay:
8251 23:05:49.551471 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =134
8252 23:05:49.554605 DQ4 =136, DQ5 =124, DQ6 =140, DQ7 =140
8253 23:05:49.557839 DQ8 =118, DQ9 =116, DQ10 =126, DQ11 =118
8254 23:05:49.561206 DQ12 =132, DQ13 =134, DQ14 =138, DQ15 =134
8255 23:05:49.561288
8256 23:05:49.561353
8257 23:05:49.561413
8258 23:05:49.564563 [DramC_TX_OE_Calibration] TA2
8259 23:05:49.567984 Original DQ_B0 (3 6) =30, OEN = 27
8260 23:05:49.571192 Original DQ_B1 (3 6) =30, OEN = 27
8261 23:05:49.574329 24, 0x0, End_B0=24 End_B1=24
8262 23:05:49.577979 25, 0x0, End_B0=25 End_B1=25
8263 23:05:49.578062 26, 0x0, End_B0=26 End_B1=26
8264 23:05:49.581117 27, 0x0, End_B0=27 End_B1=27
8265 23:05:49.584350 28, 0x0, End_B0=28 End_B1=28
8266 23:05:49.587503 29, 0x0, End_B0=29 End_B1=29
8267 23:05:49.591154 30, 0x0, End_B0=30 End_B1=30
8268 23:05:49.591265 31, 0x4141, End_B0=30 End_B1=30
8269 23:05:49.594414 Byte0 end_step=30 best_step=27
8270 23:05:49.597541 Byte1 end_step=30 best_step=27
8271 23:05:49.601144 Byte0 TX OE(2T, 0.5T) = (3, 3)
8272 23:05:49.604263 Byte1 TX OE(2T, 0.5T) = (3, 3)
8273 23:05:49.604336
8274 23:05:49.604397
8275 23:05:49.611166 [DQSOSCAuto] RK1, (LSB)MR18= 0x2108, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
8276 23:05:49.614625 CH0 RK1: MR19=303, MR18=2108
8277 23:05:49.620899 CH0_RK1: MR19=0x303, MR18=0x2108, DQSOSC=393, MR23=63, INC=23, DEC=15
8278 23:05:49.624578 [RxdqsGatingPostProcess] freq 1600
8279 23:05:49.627763 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8280 23:05:49.630938 best DQS0 dly(2T, 0.5T) = (1, 1)
8281 23:05:49.634263 best DQS1 dly(2T, 0.5T) = (1, 1)
8282 23:05:49.638008 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8283 23:05:49.641152 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8284 23:05:49.644180 best DQS0 dly(2T, 0.5T) = (1, 1)
8285 23:05:49.647614 best DQS1 dly(2T, 0.5T) = (1, 1)
8286 23:05:49.651308 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8287 23:05:49.654471 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8288 23:05:49.657536 Pre-setting of DQS Precalculation
8289 23:05:49.660848 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8290 23:05:49.660933 ==
8291 23:05:49.664135 Dram Type= 6, Freq= 0, CH_1, rank 0
8292 23:05:49.670413 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8293 23:05:49.670498 ==
8294 23:05:49.673871 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8295 23:05:49.680767 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8296 23:05:49.683823 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8297 23:05:49.690811 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8298 23:05:49.697947 [CA 0] Center 42 (12~72) winsize 61
8299 23:05:49.701435 [CA 1] Center 42 (12~72) winsize 61
8300 23:05:49.704809 [CA 2] Center 39 (10~68) winsize 59
8301 23:05:49.707995 [CA 3] Center 38 (9~67) winsize 59
8302 23:05:49.711340 [CA 4] Center 38 (9~68) winsize 60
8303 23:05:49.714555 [CA 5] Center 37 (7~67) winsize 61
8304 23:05:49.714652
8305 23:05:49.717777 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8306 23:05:49.717887
8307 23:05:49.721333 [CATrainingPosCal] consider 1 rank data
8308 23:05:49.724684 u2DelayCellTimex100 = 290/100 ps
8309 23:05:49.731445 CA0 delay=42 (12~72),Diff = 5 PI (16 cell)
8310 23:05:49.734719 CA1 delay=42 (12~72),Diff = 5 PI (16 cell)
8311 23:05:49.737871 CA2 delay=39 (10~68),Diff = 2 PI (6 cell)
8312 23:05:49.741391 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8313 23:05:49.744455 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8314 23:05:49.747670 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8315 23:05:49.747750
8316 23:05:49.751255 CA PerBit enable=1, Macro0, CA PI delay=37
8317 23:05:49.751336
8318 23:05:49.754450 [CBTSetCACLKResult] CA Dly = 37
8319 23:05:49.757873 CS Dly: 10 (0~41)
8320 23:05:49.761095 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8321 23:05:49.764429 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8322 23:05:49.764510 ==
8323 23:05:49.767941 Dram Type= 6, Freq= 0, CH_1, rank 1
8324 23:05:49.770949 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8325 23:05:49.774205 ==
8326 23:05:49.777902 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8327 23:05:49.780976 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8328 23:05:49.787237 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8329 23:05:49.794195 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8330 23:05:49.801511 [CA 0] Center 42 (12~72) winsize 61
8331 23:05:49.804781 [CA 1] Center 41 (12~71) winsize 60
8332 23:05:49.808391 [CA 2] Center 38 (9~68) winsize 60
8333 23:05:49.811210 [CA 3] Center 37 (8~67) winsize 60
8334 23:05:49.814701 [CA 4] Center 38 (8~68) winsize 61
8335 23:05:49.818063 [CA 5] Center 37 (8~67) winsize 60
8336 23:05:49.818162
8337 23:05:49.821816 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8338 23:05:49.821900
8339 23:05:49.824602 [CATrainingPosCal] consider 2 rank data
8340 23:05:49.828408 u2DelayCellTimex100 = 290/100 ps
8341 23:05:49.831300 CA0 delay=42 (12~72),Diff = 5 PI (16 cell)
8342 23:05:49.837868 CA1 delay=41 (12~71),Diff = 4 PI (13 cell)
8343 23:05:49.841568 CA2 delay=39 (10~68),Diff = 2 PI (6 cell)
8344 23:05:49.844945 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8345 23:05:49.848125 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8346 23:05:49.851180 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8347 23:05:49.851289
8348 23:05:49.854555 CA PerBit enable=1, Macro0, CA PI delay=37
8349 23:05:49.854689
8350 23:05:49.857888 [CBTSetCACLKResult] CA Dly = 37
8351 23:05:49.861156 CS Dly: 11 (0~44)
8352 23:05:49.864282 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8353 23:05:49.868003 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8354 23:05:49.868134
8355 23:05:49.870889 ----->DramcWriteLeveling(PI) begin...
8356 23:05:49.870975 ==
8357 23:05:49.874545 Dram Type= 6, Freq= 0, CH_1, rank 0
8358 23:05:49.881034 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8359 23:05:49.881116 ==
8360 23:05:49.884760 Write leveling (Byte 0): 25 => 25
8361 23:05:49.884851 Write leveling (Byte 1): 28 => 28
8362 23:05:49.887675 DramcWriteLeveling(PI) end<-----
8363 23:05:49.887783
8364 23:05:49.887876 ==
8365 23:05:49.890883 Dram Type= 6, Freq= 0, CH_1, rank 0
8366 23:05:49.898390 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8367 23:05:49.898494 ==
8368 23:05:49.901509 [Gating] SW mode calibration
8369 23:05:49.907858 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8370 23:05:49.911067 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8371 23:05:49.918193 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8372 23:05:49.921329 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8373 23:05:49.924063 1 4 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (1 1)
8374 23:05:49.931349 1 4 12 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
8375 23:05:49.934056 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8376 23:05:49.937473 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8377 23:05:49.943860 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8378 23:05:49.947275 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8379 23:05:49.950915 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8380 23:05:49.957262 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8381 23:05:49.960635 1 5 8 | B1->B0 | 3434 2f2f | 0 0 | (0 0) (0 1)
8382 23:05:49.963888 1 5 12 | B1->B0 | 2a2a 2424 | 0 0 | (0 0) (0 0)
8383 23:05:49.970711 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
8384 23:05:49.973994 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8385 23:05:49.977143 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8386 23:05:49.980306 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8387 23:05:49.987581 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8388 23:05:49.991078 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8389 23:05:49.993973 1 6 8 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (0 0)
8390 23:05:50.000387 1 6 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
8391 23:05:50.003636 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8392 23:05:50.006926 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8393 23:05:50.013975 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8394 23:05:50.017767 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8395 23:05:50.020867 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8396 23:05:50.027338 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8397 23:05:50.030482 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8398 23:05:50.033930 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8399 23:05:50.040638 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 23:05:50.043866 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 23:05:50.047090 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 23:05:50.053936 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 23:05:50.056791 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 23:05:50.060131 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 23:05:50.067006 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8406 23:05:50.070268 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 23:05:50.073312 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 23:05:50.080595 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8409 23:05:50.083699 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8410 23:05:50.086973 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 23:05:50.093536 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8412 23:05:50.096914 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8413 23:05:50.099977 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8414 23:05:50.106599 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8415 23:05:50.109986 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8416 23:05:50.113415 Total UI for P1: 0, mck2ui 16
8417 23:05:50.116544 best dqsien dly found for B0: ( 1, 9, 12)
8418 23:05:50.120189 Total UI for P1: 0, mck2ui 16
8419 23:05:50.123265 best dqsien dly found for B1: ( 1, 9, 10)
8420 23:05:50.126719 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8421 23:05:50.129761 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8422 23:05:50.129843
8423 23:05:50.133881 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8424 23:05:50.137029 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8425 23:05:50.140378 [Gating] SW calibration Done
8426 23:05:50.140475 ==
8427 23:05:50.143523 Dram Type= 6, Freq= 0, CH_1, rank 0
8428 23:05:50.146693 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8429 23:05:50.146771 ==
8430 23:05:50.149920 RX Vref Scan: 0
8431 23:05:50.150043
8432 23:05:50.153288 RX Vref 0 -> 0, step: 1
8433 23:05:50.153423
8434 23:05:50.153521 RX Delay 0 -> 252, step: 8
8435 23:05:50.160220 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8436 23:05:50.163199 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8437 23:05:50.166861 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8438 23:05:50.170117 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8439 23:05:50.173489 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8440 23:05:50.179866 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8441 23:05:50.183517 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8442 23:05:50.186676 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8443 23:05:50.189967 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8444 23:05:50.193275 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8445 23:05:50.199692 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8446 23:05:50.203537 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8447 23:05:50.206552 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8448 23:05:50.209498 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8449 23:05:50.213309 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8450 23:05:50.219648 iDelay=200, Bit 15, Center 143 (96 ~ 191) 96
8451 23:05:50.219760 ==
8452 23:05:50.222898 Dram Type= 6, Freq= 0, CH_1, rank 0
8453 23:05:50.226636 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8454 23:05:50.226714 ==
8455 23:05:50.226777 DQS Delay:
8456 23:05:50.229897 DQS0 = 0, DQS1 = 0
8457 23:05:50.229971 DQM Delay:
8458 23:05:50.233136 DQM0 = 136, DQM1 = 133
8459 23:05:50.233240 DQ Delay:
8460 23:05:50.236577 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8461 23:05:50.239718 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8462 23:05:50.243048 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8463 23:05:50.246428 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8464 23:05:50.246530
8465 23:05:50.246620
8466 23:05:50.246713 ==
8467 23:05:50.249640 Dram Type= 6, Freq= 0, CH_1, rank 0
8468 23:05:50.256303 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8469 23:05:50.256406 ==
8470 23:05:50.256501
8471 23:05:50.256595
8472 23:05:50.256688 TX Vref Scan disable
8473 23:05:50.259856 == TX Byte 0 ==
8474 23:05:50.263575 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8475 23:05:50.269979 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8476 23:05:50.270085 == TX Byte 1 ==
8477 23:05:50.273836 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8478 23:05:50.279782 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8479 23:05:50.279887 ==
8480 23:05:50.283160 Dram Type= 6, Freq= 0, CH_1, rank 0
8481 23:05:50.286914 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8482 23:05:50.286993 ==
8483 23:05:50.300082
8484 23:05:50.303380 TX Vref early break, caculate TX vref
8485 23:05:50.307085 TX Vref=16, minBit 9, minWin=22, winSum=379
8486 23:05:50.310221 TX Vref=18, minBit 1, minWin=23, winSum=383
8487 23:05:50.313447 TX Vref=20, minBit 1, minWin=23, winSum=400
8488 23:05:50.316615 TX Vref=22, minBit 6, minWin=24, winSum=408
8489 23:05:50.320320 TX Vref=24, minBit 0, minWin=25, winSum=415
8490 23:05:50.327205 TX Vref=26, minBit 0, minWin=25, winSum=426
8491 23:05:50.330247 TX Vref=28, minBit 0, minWin=24, winSum=423
8492 23:05:50.333425 TX Vref=30, minBit 0, minWin=25, winSum=418
8493 23:05:50.336437 TX Vref=32, minBit 0, minWin=24, winSum=412
8494 23:05:50.340158 TX Vref=34, minBit 0, minWin=24, winSum=405
8495 23:05:50.343158 TX Vref=36, minBit 0, minWin=23, winSum=393
8496 23:05:50.350179 [TxChooseVref] Worse bit 0, Min win 25, Win sum 426, Final Vref 26
8497 23:05:50.350263
8498 23:05:50.353338 Final TX Range 0 Vref 26
8499 23:05:50.353450
8500 23:05:50.353543 ==
8501 23:05:50.356720 Dram Type= 6, Freq= 0, CH_1, rank 0
8502 23:05:50.360018 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8503 23:05:50.360111 ==
8504 23:05:50.360186
8505 23:05:50.360276
8506 23:05:50.363280 TX Vref Scan disable
8507 23:05:50.369503 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8508 23:05:50.369615 == TX Byte 0 ==
8509 23:05:50.373012 u2DelayCellOfst[0]=13 cells (4 PI)
8510 23:05:50.376389 u2DelayCellOfst[1]=10 cells (3 PI)
8511 23:05:50.379787 u2DelayCellOfst[2]=0 cells (0 PI)
8512 23:05:50.383052 u2DelayCellOfst[3]=6 cells (2 PI)
8513 23:05:50.386251 u2DelayCellOfst[4]=6 cells (2 PI)
8514 23:05:50.389823 u2DelayCellOfst[5]=16 cells (5 PI)
8515 23:05:50.392674 u2DelayCellOfst[6]=16 cells (5 PI)
8516 23:05:50.396596 u2DelayCellOfst[7]=3 cells (1 PI)
8517 23:05:50.399620 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8518 23:05:50.402861 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8519 23:05:50.406106 == TX Byte 1 ==
8520 23:05:50.409512 u2DelayCellOfst[8]=0 cells (0 PI)
8521 23:05:50.413078 u2DelayCellOfst[9]=3 cells (1 PI)
8522 23:05:50.413160 u2DelayCellOfst[10]=13 cells (4 PI)
8523 23:05:50.416071 u2DelayCellOfst[11]=3 cells (1 PI)
8524 23:05:50.419243 u2DelayCellOfst[12]=13 cells (4 PI)
8525 23:05:50.422370 u2DelayCellOfst[13]=16 cells (5 PI)
8526 23:05:50.425694 u2DelayCellOfst[14]=16 cells (5 PI)
8527 23:05:50.429004 u2DelayCellOfst[15]=16 cells (5 PI)
8528 23:05:50.436274 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8529 23:05:50.439174 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8530 23:05:50.439255 DramC Write-DBI on
8531 23:05:50.439319 ==
8532 23:05:50.442512 Dram Type= 6, Freq= 0, CH_1, rank 0
8533 23:05:50.449521 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8534 23:05:50.449687 ==
8535 23:05:50.449798
8536 23:05:50.449925
8537 23:05:50.450022 TX Vref Scan disable
8538 23:05:50.453300 == TX Byte 0 ==
8539 23:05:50.456725 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8540 23:05:50.460530 == TX Byte 1 ==
8541 23:05:50.463494 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8542 23:05:50.463577 DramC Write-DBI off
8543 23:05:50.466537
8544 23:05:50.466618 [DATLAT]
8545 23:05:50.466682 Freq=1600, CH1 RK0
8546 23:05:50.466742
8547 23:05:50.469789 DATLAT Default: 0xf
8548 23:05:50.469870 0, 0xFFFF, sum = 0
8549 23:05:50.472991 1, 0xFFFF, sum = 0
8550 23:05:50.473104 2, 0xFFFF, sum = 0
8551 23:05:50.476698 3, 0xFFFF, sum = 0
8552 23:05:50.479834 4, 0xFFFF, sum = 0
8553 23:05:50.479916 5, 0xFFFF, sum = 0
8554 23:05:50.483581 6, 0xFFFF, sum = 0
8555 23:05:50.483664 7, 0xFFFF, sum = 0
8556 23:05:50.486345 8, 0xFFFF, sum = 0
8557 23:05:50.486492 9, 0xFFFF, sum = 0
8558 23:05:50.490102 10, 0xFFFF, sum = 0
8559 23:05:50.490185 11, 0xFFFF, sum = 0
8560 23:05:50.492953 12, 0xFFFF, sum = 0
8561 23:05:50.493036 13, 0xFFFF, sum = 0
8562 23:05:50.496344 14, 0x0, sum = 1
8563 23:05:50.496474 15, 0x0, sum = 2
8564 23:05:50.499815 16, 0x0, sum = 3
8565 23:05:50.499914 17, 0x0, sum = 4
8566 23:05:50.502819 best_step = 15
8567 23:05:50.502927
8568 23:05:50.503019 ==
8569 23:05:50.506340 Dram Type= 6, Freq= 0, CH_1, rank 0
8570 23:05:50.509381 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8571 23:05:50.509459 ==
8572 23:05:50.509524 RX Vref Scan: 1
8573 23:05:50.513338
8574 23:05:50.513474 Set Vref Range= 24 -> 127
8575 23:05:50.513564
8576 23:05:50.516713 RX Vref 24 -> 127, step: 1
8577 23:05:50.516849
8578 23:05:50.519352 RX Delay 27 -> 252, step: 4
8579 23:05:50.519427
8580 23:05:50.522987 Set Vref, RX VrefLevel [Byte0]: 24
8581 23:05:50.526190 [Byte1]: 24
8582 23:05:50.526262
8583 23:05:50.529413 Set Vref, RX VrefLevel [Byte0]: 25
8584 23:05:50.532544 [Byte1]: 25
8585 23:05:50.532615
8586 23:05:50.535828 Set Vref, RX VrefLevel [Byte0]: 26
8587 23:05:50.539631 [Byte1]: 26
8588 23:05:50.543425
8589 23:05:50.543507 Set Vref, RX VrefLevel [Byte0]: 27
8590 23:05:50.546619 [Byte1]: 27
8591 23:05:50.551202
8592 23:05:50.551284 Set Vref, RX VrefLevel [Byte0]: 28
8593 23:05:50.554165 [Byte1]: 28
8594 23:05:50.558278
8595 23:05:50.558385 Set Vref, RX VrefLevel [Byte0]: 29
8596 23:05:50.561853 [Byte1]: 29
8597 23:05:50.565883
8598 23:05:50.565964 Set Vref, RX VrefLevel [Byte0]: 30
8599 23:05:50.569173 [Byte1]: 30
8600 23:05:50.573666
8601 23:05:50.573750 Set Vref, RX VrefLevel [Byte0]: 31
8602 23:05:50.576591 [Byte1]: 31
8603 23:05:50.580944
8604 23:05:50.581026 Set Vref, RX VrefLevel [Byte0]: 32
8605 23:05:50.584446 [Byte1]: 32
8606 23:05:50.588785
8607 23:05:50.588894 Set Vref, RX VrefLevel [Byte0]: 33
8608 23:05:50.592062 [Byte1]: 33
8609 23:05:50.596373
8610 23:05:50.596482 Set Vref, RX VrefLevel [Byte0]: 34
8611 23:05:50.599329 [Byte1]: 34
8612 23:05:50.604066
8613 23:05:50.604155 Set Vref, RX VrefLevel [Byte0]: 35
8614 23:05:50.606974 [Byte1]: 35
8615 23:05:50.610939
8616 23:05:50.611027 Set Vref, RX VrefLevel [Byte0]: 36
8617 23:05:50.614308 [Byte1]: 36
8618 23:05:50.618721
8619 23:05:50.618803 Set Vref, RX VrefLevel [Byte0]: 37
8620 23:05:50.622016 [Byte1]: 37
8621 23:05:50.626528
8622 23:05:50.626611 Set Vref, RX VrefLevel [Byte0]: 38
8623 23:05:50.629589 [Byte1]: 38
8624 23:05:50.633496
8625 23:05:50.633585 Set Vref, RX VrefLevel [Byte0]: 39
8626 23:05:50.636910 [Byte1]: 39
8627 23:05:50.641251
8628 23:05:50.641360 Set Vref, RX VrefLevel [Byte0]: 40
8629 23:05:50.644352 [Byte1]: 40
8630 23:05:50.649026
8631 23:05:50.649106 Set Vref, RX VrefLevel [Byte0]: 41
8632 23:05:50.652472 [Byte1]: 41
8633 23:05:50.656405
8634 23:05:50.656487 Set Vref, RX VrefLevel [Byte0]: 42
8635 23:05:50.659607 [Byte1]: 42
8636 23:05:50.663909
8637 23:05:50.663992 Set Vref, RX VrefLevel [Byte0]: 43
8638 23:05:50.667722 [Byte1]: 43
8639 23:05:50.671360
8640 23:05:50.671443 Set Vref, RX VrefLevel [Byte0]: 44
8641 23:05:50.674615 [Byte1]: 44
8642 23:05:50.678863
8643 23:05:50.678945 Set Vref, RX VrefLevel [Byte0]: 45
8644 23:05:50.682060 [Byte1]: 45
8645 23:05:50.686449
8646 23:05:50.686529 Set Vref, RX VrefLevel [Byte0]: 46
8647 23:05:50.689604 [Byte1]: 46
8648 23:05:50.693851
8649 23:05:50.693933 Set Vref, RX VrefLevel [Byte0]: 47
8650 23:05:50.697536 [Byte1]: 47
8651 23:05:50.701253
8652 23:05:50.701334 Set Vref, RX VrefLevel [Byte0]: 48
8653 23:05:50.704539 [Byte1]: 48
8654 23:05:50.709264
8655 23:05:50.709345 Set Vref, RX VrefLevel [Byte0]: 49
8656 23:05:50.712648 [Byte1]: 49
8657 23:05:50.716773
8658 23:05:50.716854 Set Vref, RX VrefLevel [Byte0]: 50
8659 23:05:50.719753 [Byte1]: 50
8660 23:05:50.724254
8661 23:05:50.724335 Set Vref, RX VrefLevel [Byte0]: 51
8662 23:05:50.727406 [Byte1]: 51
8663 23:05:50.731730
8664 23:05:50.731811 Set Vref, RX VrefLevel [Byte0]: 52
8665 23:05:50.734845 [Byte1]: 52
8666 23:05:50.739397
8667 23:05:50.739478 Set Vref, RX VrefLevel [Byte0]: 53
8668 23:05:50.742544 [Byte1]: 53
8669 23:05:50.746906
8670 23:05:50.746986 Set Vref, RX VrefLevel [Byte0]: 54
8671 23:05:50.750346 [Byte1]: 54
8672 23:05:50.754765
8673 23:05:50.754846 Set Vref, RX VrefLevel [Byte0]: 55
8674 23:05:50.758217 [Byte1]: 55
8675 23:05:50.761840
8676 23:05:50.761924 Set Vref, RX VrefLevel [Byte0]: 56
8677 23:05:50.765600 [Byte1]: 56
8678 23:05:50.769378
8679 23:05:50.769485 Set Vref, RX VrefLevel [Byte0]: 57
8680 23:05:50.772412 [Byte1]: 57
8681 23:05:50.776661
8682 23:05:50.776765 Set Vref, RX VrefLevel [Byte0]: 58
8683 23:05:50.780134 [Byte1]: 58
8684 23:05:50.784382
8685 23:05:50.784485 Set Vref, RX VrefLevel [Byte0]: 59
8686 23:05:50.787707 [Byte1]: 59
8687 23:05:50.791663
8688 23:05:50.791764 Set Vref, RX VrefLevel [Byte0]: 60
8689 23:05:50.795485 [Byte1]: 60
8690 23:05:50.799246
8691 23:05:50.799330 Set Vref, RX VrefLevel [Byte0]: 61
8692 23:05:50.802509 [Byte1]: 61
8693 23:05:50.806976
8694 23:05:50.807060 Set Vref, RX VrefLevel [Byte0]: 62
8695 23:05:50.810285 [Byte1]: 62
8696 23:05:50.814373
8697 23:05:50.814453 Set Vref, RX VrefLevel [Byte0]: 63
8698 23:05:50.817801 [Byte1]: 63
8699 23:05:50.822185
8700 23:05:50.822297 Set Vref, RX VrefLevel [Byte0]: 64
8701 23:05:50.825406 [Byte1]: 64
8702 23:05:50.829288
8703 23:05:50.829374 Set Vref, RX VrefLevel [Byte0]: 65
8704 23:05:50.832833 [Byte1]: 65
8705 23:05:50.837096
8706 23:05:50.837181 Set Vref, RX VrefLevel [Byte0]: 66
8707 23:05:50.840074 [Byte1]: 66
8708 23:05:50.844604
8709 23:05:50.844688 Set Vref, RX VrefLevel [Byte0]: 67
8710 23:05:50.847727 [Byte1]: 67
8711 23:05:50.852080
8712 23:05:50.852165 Set Vref, RX VrefLevel [Byte0]: 68
8713 23:05:50.855377 [Byte1]: 68
8714 23:05:50.859452
8715 23:05:50.859539 Set Vref, RX VrefLevel [Byte0]: 69
8716 23:05:50.862919 [Byte1]: 69
8717 23:05:50.867211
8718 23:05:50.867293 Set Vref, RX VrefLevel [Byte0]: 70
8719 23:05:50.870408 [Byte1]: 70
8720 23:05:50.874880
8721 23:05:50.874963 Set Vref, RX VrefLevel [Byte0]: 71
8722 23:05:50.878051 [Byte1]: 71
8723 23:05:50.882566
8724 23:05:50.882652 Set Vref, RX VrefLevel [Byte0]: 72
8725 23:05:50.885433 [Byte1]: 72
8726 23:05:50.890010
8727 23:05:50.890097 Set Vref, RX VrefLevel [Byte0]: 73
8728 23:05:50.893259 [Byte1]: 73
8729 23:05:50.897260
8730 23:05:50.897342 Set Vref, RX VrefLevel [Byte0]: 74
8731 23:05:50.900444 [Byte1]: 74
8732 23:05:50.904802
8733 23:05:50.904883 Set Vref, RX VrefLevel [Byte0]: 75
8734 23:05:50.908066 [Byte1]: 75
8735 23:05:50.912659
8736 23:05:50.912740 Set Vref, RX VrefLevel [Byte0]: 76
8737 23:05:50.915536 [Byte1]: 76
8738 23:05:50.920048
8739 23:05:50.920129 Final RX Vref Byte 0 = 57 to rank0
8740 23:05:50.923162 Final RX Vref Byte 1 = 54 to rank0
8741 23:05:50.926846 Final RX Vref Byte 0 = 57 to rank1
8742 23:05:50.929941 Final RX Vref Byte 1 = 54 to rank1==
8743 23:05:50.933242 Dram Type= 6, Freq= 0, CH_1, rank 0
8744 23:05:50.939723 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8745 23:05:50.939806 ==
8746 23:05:50.939871 DQS Delay:
8747 23:05:50.939932 DQS0 = 0, DQS1 = 0
8748 23:05:50.943410 DQM Delay:
8749 23:05:50.943512 DQM0 = 133, DQM1 = 131
8750 23:05:50.946345 DQ Delay:
8751 23:05:50.949976 DQ0 =140, DQ1 =128, DQ2 =122, DQ3 =130
8752 23:05:50.953271 DQ4 =132, DQ5 =144, DQ6 =142, DQ7 =132
8753 23:05:50.956417 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =124
8754 23:05:50.959887 DQ12 =140, DQ13 =140, DQ14 =140, DQ15 =140
8755 23:05:50.959978
8756 23:05:50.960063
8757 23:05:50.960182
8758 23:05:50.963294 [DramC_TX_OE_Calibration] TA2
8759 23:05:50.966270 Original DQ_B0 (3 6) =30, OEN = 27
8760 23:05:50.969670 Original DQ_B1 (3 6) =30, OEN = 27
8761 23:05:50.973421 24, 0x0, End_B0=24 End_B1=24
8762 23:05:50.973508 25, 0x0, End_B0=25 End_B1=25
8763 23:05:50.976678 26, 0x0, End_B0=26 End_B1=26
8764 23:05:50.979861 27, 0x0, End_B0=27 End_B1=27
8765 23:05:50.983292 28, 0x0, End_B0=28 End_B1=28
8766 23:05:50.983378 29, 0x0, End_B0=29 End_B1=29
8767 23:05:50.986393 30, 0x0, End_B0=30 End_B1=30
8768 23:05:50.989898 31, 0x4141, End_B0=30 End_B1=30
8769 23:05:50.993347 Byte0 end_step=30 best_step=27
8770 23:05:50.996223 Byte1 end_step=30 best_step=27
8771 23:05:50.999783 Byte0 TX OE(2T, 0.5T) = (3, 3)
8772 23:05:50.999868 Byte1 TX OE(2T, 0.5T) = (3, 3)
8773 23:05:51.003025
8774 23:05:51.003109
8775 23:05:51.009331 [DQSOSCAuto] RK0, (LSB)MR18= 0x1623, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 398 ps
8776 23:05:51.013209 CH1 RK0: MR19=303, MR18=1623
8777 23:05:51.019541 CH1_RK0: MR19=0x303, MR18=0x1623, DQSOSC=392, MR23=63, INC=24, DEC=16
8778 23:05:51.019626
8779 23:05:51.022761 ----->DramcWriteLeveling(PI) begin...
8780 23:05:51.022848 ==
8781 23:05:51.026079 Dram Type= 6, Freq= 0, CH_1, rank 1
8782 23:05:51.029182 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8783 23:05:51.029267 ==
8784 23:05:51.032487 Write leveling (Byte 0): 24 => 24
8785 23:05:51.036180 Write leveling (Byte 1): 29 => 29
8786 23:05:51.039529 DramcWriteLeveling(PI) end<-----
8787 23:05:51.039614
8788 23:05:51.039699 ==
8789 23:05:51.042398 Dram Type= 6, Freq= 0, CH_1, rank 1
8790 23:05:51.046139 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8791 23:05:51.046224 ==
8792 23:05:51.049484 [Gating] SW mode calibration
8793 23:05:51.055698 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8794 23:05:51.062834 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8795 23:05:51.065866 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8796 23:05:51.069144 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8797 23:05:51.076278 1 4 8 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
8798 23:05:51.079189 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8799 23:05:51.082454 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8800 23:05:51.089328 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8801 23:05:51.092718 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8802 23:05:51.095729 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8803 23:05:51.102496 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8804 23:05:51.105466 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8805 23:05:51.108929 1 5 8 | B1->B0 | 3333 3434 | 1 1 | (1 0) (1 1)
8806 23:05:51.115596 1 5 12 | B1->B0 | 2323 2c2c | 1 1 | (1 0) (1 0)
8807 23:05:51.118707 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
8808 23:05:51.121951 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8809 23:05:51.128769 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8810 23:05:51.132064 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8811 23:05:51.135368 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8812 23:05:51.142207 1 6 4 | B1->B0 | 2625 2323 | 1 0 | (0 0) (0 0)
8813 23:05:51.145643 1 6 8 | B1->B0 | 3838 2323 | 0 0 | (0 0) (0 0)
8814 23:05:51.148774 1 6 12 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
8815 23:05:51.155315 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8816 23:05:51.158983 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8817 23:05:51.162182 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8818 23:05:51.169327 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8819 23:05:51.172242 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8820 23:05:51.175511 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8821 23:05:51.182248 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8822 23:05:51.185184 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8823 23:05:51.188948 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8824 23:05:51.195369 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8825 23:05:51.198692 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8826 23:05:51.201735 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8827 23:05:51.205357 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8828 23:05:51.212183 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8829 23:05:51.215495 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8830 23:05:51.219161 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8831 23:05:51.225729 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8832 23:05:51.228704 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8833 23:05:51.231779 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8834 23:05:51.238372 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8835 23:05:51.242370 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8836 23:05:51.245553 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8837 23:05:51.252121 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8838 23:05:51.255394 Total UI for P1: 0, mck2ui 16
8839 23:05:51.258733 best dqsien dly found for B1: ( 1, 9, 4)
8840 23:05:51.261717 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8841 23:05:51.265505 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8842 23:05:51.272005 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8843 23:05:51.272093 Total UI for P1: 0, mck2ui 16
8844 23:05:51.278808 best dqsien dly found for B0: ( 1, 9, 12)
8845 23:05:51.281918 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8846 23:05:51.285211 best DQS1 dly(MCK, UI, PI) = (1, 9, 4)
8847 23:05:51.285295
8848 23:05:51.288865 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8849 23:05:51.291962 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 4)
8850 23:05:51.295431 [Gating] SW calibration Done
8851 23:05:51.295516 ==
8852 23:05:51.298572 Dram Type= 6, Freq= 0, CH_1, rank 1
8853 23:05:51.301776 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8854 23:05:51.301861 ==
8855 23:05:51.305474 RX Vref Scan: 0
8856 23:05:51.305558
8857 23:05:51.305683 RX Vref 0 -> 0, step: 1
8858 23:05:51.305766
8859 23:05:51.308700 RX Delay 0 -> 252, step: 8
8860 23:05:51.311849 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8861 23:05:51.318347 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8862 23:05:51.321732 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8863 23:05:51.325441 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8864 23:05:51.328489 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8865 23:05:51.331990 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8866 23:05:51.335410 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8867 23:05:51.341561 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8868 23:05:51.344887 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8869 23:05:51.348114 iDelay=208, Bit 9, Center 123 (64 ~ 183) 120
8870 23:05:51.351824 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8871 23:05:51.358106 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8872 23:05:51.361477 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8873 23:05:51.364704 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8874 23:05:51.368447 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8875 23:05:51.371687 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8876 23:05:51.374954 ==
8877 23:05:51.375044 Dram Type= 6, Freq= 0, CH_1, rank 1
8878 23:05:51.381362 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8879 23:05:51.381449 ==
8880 23:05:51.381552 DQS Delay:
8881 23:05:51.385247 DQS0 = 0, DQS1 = 0
8882 23:05:51.385332 DQM Delay:
8883 23:05:51.388172 DQM0 = 136, DQM1 = 134
8884 23:05:51.388257 DQ Delay:
8885 23:05:51.391443 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8886 23:05:51.394749 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8887 23:05:51.398355 DQ8 =119, DQ9 =123, DQ10 =135, DQ11 =127
8888 23:05:51.401896 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8889 23:05:51.401980
8890 23:05:51.402066
8891 23:05:51.402146 ==
8892 23:05:51.404984 Dram Type= 6, Freq= 0, CH_1, rank 1
8893 23:05:51.411857 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8894 23:05:51.411954 ==
8895 23:05:51.412041
8896 23:05:51.412122
8897 23:05:51.412202 TX Vref Scan disable
8898 23:05:51.415105 == TX Byte 0 ==
8899 23:05:51.418327 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8900 23:05:51.424997 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8901 23:05:51.425082 == TX Byte 1 ==
8902 23:05:51.428139 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8903 23:05:51.434630 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8904 23:05:51.434716 ==
8905 23:05:51.438501 Dram Type= 6, Freq= 0, CH_1, rank 1
8906 23:05:51.441477 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8907 23:05:51.441562 ==
8908 23:05:51.454932
8909 23:05:51.458275 TX Vref early break, caculate TX vref
8910 23:05:51.461458 TX Vref=16, minBit 0, minWin=23, winSum=383
8911 23:05:51.465014 TX Vref=18, minBit 0, minWin=23, winSum=392
8912 23:05:51.468318 TX Vref=20, minBit 0, minWin=24, winSum=400
8913 23:05:51.471400 TX Vref=22, minBit 0, minWin=24, winSum=414
8914 23:05:51.474843 TX Vref=24, minBit 0, minWin=25, winSum=422
8915 23:05:51.481325 TX Vref=26, minBit 0, minWin=25, winSum=424
8916 23:05:51.484783 TX Vref=28, minBit 6, minWin=25, winSum=427
8917 23:05:51.488477 TX Vref=30, minBit 1, minWin=25, winSum=422
8918 23:05:51.492035 TX Vref=32, minBit 0, minWin=25, winSum=412
8919 23:05:51.495134 TX Vref=34, minBit 0, minWin=25, winSum=406
8920 23:05:51.497980 TX Vref=36, minBit 6, minWin=23, winSum=396
8921 23:05:51.505105 [TxChooseVref] Worse bit 6, Min win 25, Win sum 427, Final Vref 28
8922 23:05:51.505256
8923 23:05:51.508200 Final TX Range 0 Vref 28
8924 23:05:51.508285
8925 23:05:51.508371 ==
8926 23:05:51.511873 Dram Type= 6, Freq= 0, CH_1, rank 1
8927 23:05:51.514969 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8928 23:05:51.515055 ==
8929 23:05:51.515142
8930 23:05:51.515224
8931 23:05:51.518345 TX Vref Scan disable
8932 23:05:51.524665 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8933 23:05:51.524752 == TX Byte 0 ==
8934 23:05:51.528439 u2DelayCellOfst[0]=16 cells (5 PI)
8935 23:05:51.531396 u2DelayCellOfst[1]=10 cells (3 PI)
8936 23:05:51.534714 u2DelayCellOfst[2]=0 cells (0 PI)
8937 23:05:51.538346 u2DelayCellOfst[3]=6 cells (2 PI)
8938 23:05:51.541414 u2DelayCellOfst[4]=10 cells (3 PI)
8939 23:05:51.544950 u2DelayCellOfst[5]=20 cells (6 PI)
8940 23:05:51.547790 u2DelayCellOfst[6]=20 cells (6 PI)
8941 23:05:51.551659 u2DelayCellOfst[7]=6 cells (2 PI)
8942 23:05:51.554696 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8943 23:05:51.557826 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8944 23:05:51.560979 == TX Byte 1 ==
8945 23:05:51.564482 u2DelayCellOfst[8]=0 cells (0 PI)
8946 23:05:51.564567 u2DelayCellOfst[9]=3 cells (1 PI)
8947 23:05:51.567861 u2DelayCellOfst[10]=10 cells (3 PI)
8948 23:05:51.571283 u2DelayCellOfst[11]=3 cells (1 PI)
8949 23:05:51.574802 u2DelayCellOfst[12]=13 cells (4 PI)
8950 23:05:51.577613 u2DelayCellOfst[13]=16 cells (5 PI)
8951 23:05:51.581112 u2DelayCellOfst[14]=16 cells (5 PI)
8952 23:05:51.584728 u2DelayCellOfst[15]=16 cells (5 PI)
8953 23:05:51.587978 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8954 23:05:51.594370 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8955 23:05:51.594456 DramC Write-DBI on
8956 23:05:51.594542 ==
8957 23:05:51.598009 Dram Type= 6, Freq= 0, CH_1, rank 1
8958 23:05:51.604402 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8959 23:05:51.604488 ==
8960 23:05:51.604575
8961 23:05:51.604656
8962 23:05:51.604735 TX Vref Scan disable
8963 23:05:51.608455 == TX Byte 0 ==
8964 23:05:51.612059 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8965 23:05:51.615156 == TX Byte 1 ==
8966 23:05:51.618116 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8967 23:05:51.621514 DramC Write-DBI off
8968 23:05:51.621635
8969 23:05:51.621702 [DATLAT]
8970 23:05:51.621761 Freq=1600, CH1 RK1
8971 23:05:51.621819
8972 23:05:51.624769 DATLAT Default: 0xf
8973 23:05:51.624851 0, 0xFFFF, sum = 0
8974 23:05:51.628116 1, 0xFFFF, sum = 0
8975 23:05:51.631297 2, 0xFFFF, sum = 0
8976 23:05:51.631380 3, 0xFFFF, sum = 0
8977 23:05:51.634809 4, 0xFFFF, sum = 0
8978 23:05:51.634907 5, 0xFFFF, sum = 0
8979 23:05:51.638054 6, 0xFFFF, sum = 0
8980 23:05:51.638137 7, 0xFFFF, sum = 0
8981 23:05:51.641365 8, 0xFFFF, sum = 0
8982 23:05:51.641448 9, 0xFFFF, sum = 0
8983 23:05:51.644392 10, 0xFFFF, sum = 0
8984 23:05:51.644475 11, 0xFFFF, sum = 0
8985 23:05:51.647730 12, 0xFFFF, sum = 0
8986 23:05:51.647813 13, 0xFFFF, sum = 0
8987 23:05:51.651332 14, 0x0, sum = 1
8988 23:05:51.651415 15, 0x0, sum = 2
8989 23:05:51.654474 16, 0x0, sum = 3
8990 23:05:51.654557 17, 0x0, sum = 4
8991 23:05:51.657853 best_step = 15
8992 23:05:51.657935
8993 23:05:51.658000 ==
8994 23:05:51.661151 Dram Type= 6, Freq= 0, CH_1, rank 1
8995 23:05:51.664696 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8996 23:05:51.664779 ==
8997 23:05:51.667900 RX Vref Scan: 0
8998 23:05:51.667982
8999 23:05:51.668047 RX Vref 0 -> 0, step: 1
9000 23:05:51.668107
9001 23:05:51.671410 RX Delay 19 -> 252, step: 4
9002 23:05:51.674534 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
9003 23:05:51.681166 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
9004 23:05:51.684785 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
9005 23:05:51.687814 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
9006 23:05:51.691476 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
9007 23:05:51.694780 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
9008 23:05:51.697979 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
9009 23:05:51.704475 iDelay=195, Bit 7, Center 132 (79 ~ 186) 108
9010 23:05:51.708056 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
9011 23:05:51.711488 iDelay=195, Bit 9, Center 120 (67 ~ 174) 108
9012 23:05:51.714529 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
9013 23:05:51.717964 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
9014 23:05:51.724800 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
9015 23:05:51.728022 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
9016 23:05:51.731177 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
9017 23:05:51.734474 iDelay=195, Bit 15, Center 142 (91 ~ 194) 104
9018 23:05:51.734556 ==
9019 23:05:51.738422 Dram Type= 6, Freq= 0, CH_1, rank 1
9020 23:05:51.744594 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9021 23:05:51.744681 ==
9022 23:05:51.744768 DQS Delay:
9023 23:05:51.747907 DQS0 = 0, DQS1 = 0
9024 23:05:51.747992 DQM Delay:
9025 23:05:51.748078 DQM0 = 134, DQM1 = 131
9026 23:05:51.751043 DQ Delay:
9027 23:05:51.754489 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =130
9028 23:05:51.758163 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =132
9029 23:05:51.761463 DQ8 =116, DQ9 =120, DQ10 =132, DQ11 =124
9030 23:05:51.764583 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =142
9031 23:05:51.764685
9032 23:05:51.764770
9033 23:05:51.764852
9034 23:05:51.767652 [DramC_TX_OE_Calibration] TA2
9035 23:05:51.771074 Original DQ_B0 (3 6) =30, OEN = 27
9036 23:05:51.774463 Original DQ_B1 (3 6) =30, OEN = 27
9037 23:05:51.777604 24, 0x0, End_B0=24 End_B1=24
9038 23:05:51.777705 25, 0x0, End_B0=25 End_B1=25
9039 23:05:51.781250 26, 0x0, End_B0=26 End_B1=26
9040 23:05:51.784417 27, 0x0, End_B0=27 End_B1=27
9041 23:05:51.787830 28, 0x0, End_B0=28 End_B1=28
9042 23:05:51.790801 29, 0x0, End_B0=29 End_B1=29
9043 23:05:51.790887 30, 0x0, End_B0=30 End_B1=30
9044 23:05:51.794426 31, 0x4545, End_B0=30 End_B1=30
9045 23:05:51.797560 Byte0 end_step=30 best_step=27
9046 23:05:51.800878 Byte1 end_step=30 best_step=27
9047 23:05:51.804551 Byte0 TX OE(2T, 0.5T) = (3, 3)
9048 23:05:51.807484 Byte1 TX OE(2T, 0.5T) = (3, 3)
9049 23:05:51.807569
9050 23:05:51.807655
9051 23:05:51.814172 [DQSOSCAuto] RK1, (LSB)MR18= 0x2107, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 393 ps
9052 23:05:51.817223 CH1 RK1: MR19=303, MR18=2107
9053 23:05:51.824167 CH1_RK1: MR19=0x303, MR18=0x2107, DQSOSC=393, MR23=63, INC=23, DEC=15
9054 23:05:51.827642 [RxdqsGatingPostProcess] freq 1600
9055 23:05:51.830870 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9056 23:05:51.834096 best DQS0 dly(2T, 0.5T) = (1, 1)
9057 23:05:51.837351 best DQS1 dly(2T, 0.5T) = (1, 1)
9058 23:05:51.840501 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9059 23:05:51.844149 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9060 23:05:51.847378 best DQS0 dly(2T, 0.5T) = (1, 1)
9061 23:05:51.850734 best DQS1 dly(2T, 0.5T) = (1, 1)
9062 23:05:51.853808 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9063 23:05:51.857131 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9064 23:05:51.860935 Pre-setting of DQS Precalculation
9065 23:05:51.864236 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9066 23:05:51.870683 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9067 23:05:51.880744 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9068 23:05:51.880829
9069 23:05:51.880915
9070 23:05:51.880996 [Calibration Summary] 3200 Mbps
9071 23:05:51.884142 CH 0, Rank 0
9072 23:05:51.884254 SW Impedance : PASS
9073 23:05:51.887564 DUTY Scan : NO K
9074 23:05:51.890993 ZQ Calibration : PASS
9075 23:05:51.891074 Jitter Meter : NO K
9076 23:05:51.893999 CBT Training : PASS
9077 23:05:51.897411 Write leveling : PASS
9078 23:05:51.897492 RX DQS gating : PASS
9079 23:05:51.900935 RX DQ/DQS(RDDQC) : PASS
9080 23:05:51.903841 TX DQ/DQS : PASS
9081 23:05:51.903922 RX DATLAT : PASS
9082 23:05:51.907489 RX DQ/DQS(Engine): PASS
9083 23:05:51.910666 TX OE : PASS
9084 23:05:51.910747 All Pass.
9085 23:05:51.910811
9086 23:05:51.910870 CH 0, Rank 1
9087 23:05:51.913851 SW Impedance : PASS
9088 23:05:51.917110 DUTY Scan : NO K
9089 23:05:51.917191 ZQ Calibration : PASS
9090 23:05:51.920488 Jitter Meter : NO K
9091 23:05:51.923734 CBT Training : PASS
9092 23:05:51.923815 Write leveling : PASS
9093 23:05:51.926900 RX DQS gating : PASS
9094 23:05:51.930231 RX DQ/DQS(RDDQC) : PASS
9095 23:05:51.930312 TX DQ/DQS : PASS
9096 23:05:51.933910 RX DATLAT : PASS
9097 23:05:51.937338 RX DQ/DQS(Engine): PASS
9098 23:05:51.937420 TX OE : PASS
9099 23:05:51.937508 All Pass.
9100 23:05:51.937625
9101 23:05:51.940371 CH 1, Rank 0
9102 23:05:51.943871 SW Impedance : PASS
9103 23:05:51.943952 DUTY Scan : NO K
9104 23:05:51.946862 ZQ Calibration : PASS
9105 23:05:51.946944 Jitter Meter : NO K
9106 23:05:51.950316 CBT Training : PASS
9107 23:05:51.953447 Write leveling : PASS
9108 23:05:51.953569 RX DQS gating : PASS
9109 23:05:51.956690 RX DQ/DQS(RDDQC) : PASS
9110 23:05:51.960495 TX DQ/DQS : PASS
9111 23:05:51.960576 RX DATLAT : PASS
9112 23:05:51.963916 RX DQ/DQS(Engine): PASS
9113 23:05:51.966993 TX OE : PASS
9114 23:05:51.967075 All Pass.
9115 23:05:51.967139
9116 23:05:51.967199 CH 1, Rank 1
9117 23:05:51.970228 SW Impedance : PASS
9118 23:05:51.973365 DUTY Scan : NO K
9119 23:05:51.973446 ZQ Calibration : PASS
9120 23:05:51.976693 Jitter Meter : NO K
9121 23:05:51.980509 CBT Training : PASS
9122 23:05:51.980591 Write leveling : PASS
9123 23:05:51.983566 RX DQS gating : PASS
9124 23:05:51.986861 RX DQ/DQS(RDDQC) : PASS
9125 23:05:51.986942 TX DQ/DQS : PASS
9126 23:05:51.990209 RX DATLAT : PASS
9127 23:05:51.990289 RX DQ/DQS(Engine): PASS
9128 23:05:51.993331 TX OE : PASS
9129 23:05:51.993439 All Pass.
9130 23:05:51.993544
9131 23:05:51.997051 DramC Write-DBI on
9132 23:05:52.000398 PER_BANK_REFRESH: Hybrid Mode
9133 23:05:52.000479 TX_TRACKING: ON
9134 23:05:52.010203 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9135 23:05:52.017055 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9136 23:05:52.026942 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9137 23:05:52.029915 [FAST_K] Save calibration result to emmc
9138 23:05:52.030000 sync common calibartion params.
9139 23:05:52.033548 sync cbt_mode0:1, 1:1
9140 23:05:52.036918 dram_init: ddr_geometry: 2
9141 23:05:52.037018 dram_init: ddr_geometry: 2
9142 23:05:52.039795 dram_init: ddr_geometry: 2
9143 23:05:52.043160 0:dram_rank_size:100000000
9144 23:05:52.046758 1:dram_rank_size:100000000
9145 23:05:52.050492 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9146 23:05:52.053403 DFS_SHUFFLE_HW_MODE: ON
9147 23:05:52.057113 dramc_set_vcore_voltage set vcore to 725000
9148 23:05:52.060004 Read voltage for 1600, 0
9149 23:05:52.060088 Vio18 = 0
9150 23:05:52.063669 Vcore = 725000
9151 23:05:52.063755 Vdram = 0
9152 23:05:52.063843 Vddq = 0
9153 23:05:52.063926 Vmddr = 0
9154 23:05:52.066716 switch to 3200 Mbps bootup
9155 23:05:52.069894 [DramcRunTimeConfig]
9156 23:05:52.069978 PHYPLL
9157 23:05:52.070066 DPM_CONTROL_AFTERK: ON
9158 23:05:52.073917 PER_BANK_REFRESH: ON
9159 23:05:52.077157 REFRESH_OVERHEAD_REDUCTION: ON
9160 23:05:52.077241 CMD_PICG_NEW_MODE: OFF
9161 23:05:52.080419 XRTWTW_NEW_MODE: ON
9162 23:05:52.083624 XRTRTR_NEW_MODE: ON
9163 23:05:52.083708 TX_TRACKING: ON
9164 23:05:52.086895 RDSEL_TRACKING: OFF
9165 23:05:52.086980 DQS Precalculation for DVFS: ON
9166 23:05:52.090234 RX_TRACKING: OFF
9167 23:05:52.090317 HW_GATING DBG: ON
9168 23:05:52.093416 ZQCS_ENABLE_LP4: ON
9169 23:05:52.093517 RX_PICG_NEW_MODE: ON
9170 23:05:52.097184 TX_PICG_NEW_MODE: ON
9171 23:05:52.100217 ENABLE_RX_DCM_DPHY: ON
9172 23:05:52.103464 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9173 23:05:52.103550 DUMMY_READ_FOR_TRACKING: OFF
9174 23:05:52.106412 !!! SPM_CONTROL_AFTERK: OFF
9175 23:05:52.110283 !!! SPM could not control APHY
9176 23:05:52.113385 IMPEDANCE_TRACKING: ON
9177 23:05:52.113470 TEMP_SENSOR: ON
9178 23:05:52.116500 HW_SAVE_FOR_SR: OFF
9179 23:05:52.116582 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9180 23:05:52.123579 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9181 23:05:52.123661 Read ODT Tracking: ON
9182 23:05:52.126654 Refresh Rate DeBounce: ON
9183 23:05:52.129760 DFS_NO_QUEUE_FLUSH: ON
9184 23:05:52.129841 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9185 23:05:52.133094 ENABLE_DFS_RUNTIME_MRW: OFF
9186 23:05:52.136531 DDR_RESERVE_NEW_MODE: ON
9187 23:05:52.140066 MR_CBT_SWITCH_FREQ: ON
9188 23:05:52.140147 =========================
9189 23:05:52.159853 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9190 23:05:52.162955 dram_init: ddr_geometry: 2
9191 23:05:52.180754 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9192 23:05:52.183958 dram_init: dram init end (result: 0)
9193 23:05:52.191014 DRAM-K: Full calibration passed in 24432 msecs
9194 23:05:52.194275 MRC: failed to locate region type 0.
9195 23:05:52.194360 DRAM rank0 size:0x100000000,
9196 23:05:52.197470 DRAM rank1 size=0x100000000
9197 23:05:52.207095 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9198 23:05:52.214063 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9199 23:05:52.220794 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9200 23:05:52.227343 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9201 23:05:52.230541 DRAM rank0 size:0x100000000,
9202 23:05:52.234379 DRAM rank1 size=0x100000000
9203 23:05:52.234465 CBMEM:
9204 23:05:52.237520 IMD: root @ 0xfffff000 254 entries.
9205 23:05:52.240457 IMD: root @ 0xffffec00 62 entries.
9206 23:05:52.244200 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9207 23:05:52.247109 WARNING: RO_VPD is uninitialized or empty.
9208 23:05:52.254132 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9209 23:05:52.260968 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9210 23:05:52.273833 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9211 23:05:52.285066 BS: romstage times (exec / console): total (unknown) / 23966 ms
9212 23:05:52.285155
9213 23:05:52.285240
9214 23:05:52.294889 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9215 23:05:52.298781 ARM64: Exception handlers installed.
9216 23:05:52.301916 ARM64: Testing exception
9217 23:05:52.305076 ARM64: Done test exception
9218 23:05:52.305184 Enumerating buses...
9219 23:05:52.308254 Show all devs... Before device enumeration.
9220 23:05:52.311637 Root Device: enabled 1
9221 23:05:52.314906 CPU_CLUSTER: 0: enabled 1
9222 23:05:52.314989 CPU: 00: enabled 1
9223 23:05:52.318597 Compare with tree...
9224 23:05:52.318681 Root Device: enabled 1
9225 23:05:52.321743 CPU_CLUSTER: 0: enabled 1
9226 23:05:52.325181 CPU: 00: enabled 1
9227 23:05:52.325264 Root Device scanning...
9228 23:05:52.328605 scan_static_bus for Root Device
9229 23:05:52.331635 CPU_CLUSTER: 0 enabled
9230 23:05:52.335324 scan_static_bus for Root Device done
9231 23:05:52.338571 scan_bus: bus Root Device finished in 8 msecs
9232 23:05:52.338657 done
9233 23:05:52.344929 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9234 23:05:52.348704 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9235 23:05:52.355299 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9236 23:05:52.358041 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9237 23:05:52.361853 Allocating resources...
9238 23:05:52.365106 Reading resources...
9239 23:05:52.368393 Root Device read_resources bus 0 link: 0
9240 23:05:52.368477 DRAM rank0 size:0x100000000,
9241 23:05:52.371787 DRAM rank1 size=0x100000000
9242 23:05:52.375296 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9243 23:05:52.378294 CPU: 00 missing read_resources
9244 23:05:52.381607 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9245 23:05:52.388352 Root Device read_resources bus 0 link: 0 done
9246 23:05:52.388437 Done reading resources.
9247 23:05:52.394922 Show resources in subtree (Root Device)...After reading.
9248 23:05:52.398032 Root Device child on link 0 CPU_CLUSTER: 0
9249 23:05:52.401291 CPU_CLUSTER: 0 child on link 0 CPU: 00
9250 23:05:52.411409 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9251 23:05:52.411494 CPU: 00
9252 23:05:52.414555 Root Device assign_resources, bus 0 link: 0
9253 23:05:52.417855 CPU_CLUSTER: 0 missing set_resources
9254 23:05:52.424922 Root Device assign_resources, bus 0 link: 0 done
9255 23:05:52.425010 Done setting resources.
9256 23:05:52.431163 Show resources in subtree (Root Device)...After assigning values.
9257 23:05:52.434378 Root Device child on link 0 CPU_CLUSTER: 0
9258 23:05:52.437965 CPU_CLUSTER: 0 child on link 0 CPU: 00
9259 23:05:52.447868 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9260 23:05:52.447953 CPU: 00
9261 23:05:52.451001 Done allocating resources.
9262 23:05:52.454384 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9263 23:05:52.457549 Enabling resources...
9264 23:05:52.457672 done.
9265 23:05:52.464639 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9266 23:05:52.464726 Initializing devices...
9267 23:05:52.467760 Root Device init
9268 23:05:52.467844 init hardware done!
9269 23:05:52.470858 0x00000018: ctrlr->caps
9270 23:05:52.474501 52.000 MHz: ctrlr->f_max
9271 23:05:52.474587 0.400 MHz: ctrlr->f_min
9272 23:05:52.477496 0x40ff8080: ctrlr->voltages
9273 23:05:52.477603 sclk: 390625
9274 23:05:52.481221 Bus Width = 1
9275 23:05:52.481304 sclk: 390625
9276 23:05:52.484587 Bus Width = 1
9277 23:05:52.484670 Early init status = 3
9278 23:05:52.490910 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9279 23:05:52.494031 in-header: 03 fc 00 00 01 00 00 00
9280 23:05:52.494116 in-data: 00
9281 23:05:52.500775 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9282 23:05:52.504320 in-header: 03 fd 00 00 00 00 00 00
9283 23:05:52.507702 in-data:
9284 23:05:52.510798 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9285 23:05:52.514543 in-header: 03 fc 00 00 01 00 00 00
9286 23:05:52.518374 in-data: 00
9287 23:05:52.521002 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9288 23:05:52.526935 in-header: 03 fd 00 00 00 00 00 00
9289 23:05:52.530101 in-data:
9290 23:05:52.533234 [SSUSB] Setting up USB HOST controller...
9291 23:05:52.536346 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9292 23:05:52.539769 [SSUSB] phy power-on done.
9293 23:05:52.543254 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9294 23:05:52.549965 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9295 23:05:52.552760 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9296 23:05:52.559639 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9297 23:05:52.566596 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9298 23:05:52.572995 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9299 23:05:52.579470 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9300 23:05:52.586463 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9301 23:05:52.589439 SPM: binary array size = 0x9dc
9302 23:05:52.593096 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9303 23:05:52.599354 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9304 23:05:52.606141 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9305 23:05:52.612714 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9306 23:05:52.615693 configure_display: Starting display init
9307 23:05:52.650187 anx7625_power_on_init: Init interface.
9308 23:05:52.653227 anx7625_disable_pd_protocol: Disabled PD feature.
9309 23:05:52.656881 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9310 23:05:52.684238 anx7625_start_dp_work: Secure OCM version=00
9311 23:05:52.687755 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9312 23:05:52.702124 sp_tx_get_edid_block: EDID Block = 1
9313 23:05:52.805246 Extracted contents:
9314 23:05:52.808287 header: 00 ff ff ff ff ff ff 00
9315 23:05:52.811561 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9316 23:05:52.814729 version: 01 04
9317 23:05:52.818469 basic params: 95 1f 11 78 0a
9318 23:05:52.821216 chroma info: 76 90 94 55 54 90 27 21 50 54
9319 23:05:52.824842 established: 00 00 00
9320 23:05:52.831159 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9321 23:05:52.834934 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9322 23:05:52.841016 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9323 23:05:52.848198 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9324 23:05:52.854727 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9325 23:05:52.857777 extensions: 00
9326 23:05:52.857862 checksum: fb
9327 23:05:52.857947
9328 23:05:52.861529 Manufacturer: IVO Model 57d Serial Number 0
9329 23:05:52.864957 Made week 0 of 2020
9330 23:05:52.865042 EDID version: 1.4
9331 23:05:52.867706 Digital display
9332 23:05:52.871195 6 bits per primary color channel
9333 23:05:52.871281 DisplayPort interface
9334 23:05:52.874550 Maximum image size: 31 cm x 17 cm
9335 23:05:52.877808 Gamma: 220%
9336 23:05:52.877891 Check DPMS levels
9337 23:05:52.880943 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9338 23:05:52.888145 First detailed timing is preferred timing
9339 23:05:52.888233 Established timings supported:
9340 23:05:52.891450 Standard timings supported:
9341 23:05:52.894456 Detailed timings
9342 23:05:52.898263 Hex of detail: 383680a07038204018303c0035ae10000019
9343 23:05:52.901504 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9344 23:05:52.907567 0780 0798 07c8 0820 hborder 0
9345 23:05:52.911174 0438 043b 0447 0458 vborder 0
9346 23:05:52.914796 -hsync -vsync
9347 23:05:52.914913 Did detailed timing
9348 23:05:52.917750 Hex of detail: 000000000000000000000000000000000000
9349 23:05:52.921169 Manufacturer-specified data, tag 0
9350 23:05:52.927869 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9351 23:05:52.927952 ASCII string: InfoVision
9352 23:05:52.934509 Hex of detail: 000000fe00523134304e574635205248200a
9353 23:05:52.938188 ASCII string: R140NWF5 RH
9354 23:05:52.938272 Checksum
9355 23:05:52.938358 Checksum: 0xfb (valid)
9356 23:05:52.944437 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9357 23:05:52.947589 DSI data_rate: 832800000 bps
9358 23:05:52.950835 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9359 23:05:52.957434 anx7625_parse_edid: pixelclock(138800).
9360 23:05:52.961218 hactive(1920), hsync(48), hfp(24), hbp(88)
9361 23:05:52.964489 vactive(1080), vsync(12), vfp(3), vbp(17)
9362 23:05:52.967604 anx7625_dsi_config: config dsi.
9363 23:05:52.973987 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9364 23:05:52.987367 anx7625_dsi_config: success to config DSI
9365 23:05:52.990613 anx7625_dp_start: MIPI phy setup OK.
9366 23:05:52.993776 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9367 23:05:52.996901 mtk_ddp_mode_set invalid vrefresh 60
9368 23:05:53.000014 main_disp_path_setup
9369 23:05:53.000094 ovl_layer_smi_id_en
9370 23:05:53.003724 ovl_layer_smi_id_en
9371 23:05:53.003805 ccorr_config
9372 23:05:53.003869 aal_config
9373 23:05:53.006840 gamma_config
9374 23:05:53.006920 postmask_config
9375 23:05:53.009977 dither_config
9376 23:05:53.013974 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9377 23:05:53.020231 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9378 23:05:53.023299 Root Device init finished in 553 msecs
9379 23:05:53.027024 CPU_CLUSTER: 0 init
9380 23:05:53.033350 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9381 23:05:53.036961 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9382 23:05:53.039899 APU_MBOX 0x190000b0 = 0x10001
9383 23:05:53.043195 APU_MBOX 0x190001b0 = 0x10001
9384 23:05:53.046747 APU_MBOX 0x190005b0 = 0x10001
9385 23:05:53.049999 APU_MBOX 0x190006b0 = 0x10001
9386 23:05:53.053282 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9387 23:05:53.066249 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9388 23:05:53.078281 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9389 23:05:53.085136 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9390 23:05:53.096842 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9391 23:05:53.105712 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9392 23:05:53.109402 CPU_CLUSTER: 0 init finished in 81 msecs
9393 23:05:53.112513 Devices initialized
9394 23:05:53.115806 Show all devs... After init.
9395 23:05:53.115886 Root Device: enabled 1
9396 23:05:53.118965 CPU_CLUSTER: 0: enabled 1
9397 23:05:53.122246 CPU: 00: enabled 1
9398 23:05:53.125436 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9399 23:05:53.128978 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9400 23:05:53.132513 ELOG: NV offset 0x57f000 size 0x1000
9401 23:05:53.138964 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9402 23:05:53.145911 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9403 23:05:53.149112 ELOG: Event(17) added with size 13 at 2023-12-01 23:03:41 UTC
9404 23:05:53.155770 out: cmd=0x121: 03 db 21 01 00 00 00 00
9405 23:05:53.159109 in-header: 03 f7 00 00 2c 00 00 00
9406 23:05:53.168963 in-data: 68 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9407 23:05:53.175602 ELOG: Event(A1) added with size 10 at 2023-12-01 23:03:41 UTC
9408 23:05:53.182014 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9409 23:05:53.188782 ELOG: Event(A0) added with size 9 at 2023-12-01 23:03:41 UTC
9410 23:05:53.192102 elog_add_boot_reason: Logged dev mode boot
9411 23:05:53.195856 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9412 23:05:53.198635 Finalize devices...
9413 23:05:53.198716 Devices finalized
9414 23:05:53.205705 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9415 23:05:53.209053 Writing coreboot table at 0xffe64000
9416 23:05:53.212093 0. 000000000010a000-0000000000113fff: RAMSTAGE
9417 23:05:53.215094 1. 0000000040000000-00000000400fffff: RAM
9418 23:05:53.222352 2. 0000000040100000-000000004032afff: RAMSTAGE
9419 23:05:53.225388 3. 000000004032b000-00000000545fffff: RAM
9420 23:05:53.228348 4. 0000000054600000-000000005465ffff: BL31
9421 23:05:53.232011 5. 0000000054660000-00000000ffe63fff: RAM
9422 23:05:53.238940 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9423 23:05:53.242171 7. 0000000100000000-000000023fffffff: RAM
9424 23:05:53.245286 Passing 5 GPIOs to payload:
9425 23:05:53.248471 NAME | PORT | POLARITY | VALUE
9426 23:05:53.251750 EC in RW | 0x000000aa | low | undefined
9427 23:05:53.258446 EC interrupt | 0x00000005 | low | undefined
9428 23:05:53.261877 TPM interrupt | 0x000000ab | high | undefined
9429 23:05:53.268773 SD card detect | 0x00000011 | high | undefined
9430 23:05:53.271968 speaker enable | 0x00000093 | high | undefined
9431 23:05:53.275659 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9432 23:05:53.278955 in-header: 03 f9 00 00 02 00 00 00
9433 23:05:53.282053 in-data: 02 00
9434 23:05:53.282137 ADC[4]: Raw value=904726 ID=7
9435 23:05:53.285341 ADC[3]: Raw value=213810 ID=1
9436 23:05:53.288331 RAM Code: 0x71
9437 23:05:53.288416 ADC[6]: Raw value=75701 ID=0
9438 23:05:53.292045 ADC[5]: Raw value=213072 ID=1
9439 23:05:53.295261 SKU Code: 0x1
9440 23:05:53.298459 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum dbc0
9441 23:05:53.301546 coreboot table: 964 bytes.
9442 23:05:53.305133 IMD ROOT 0. 0xfffff000 0x00001000
9443 23:05:53.308371 IMD SMALL 1. 0xffffe000 0x00001000
9444 23:05:53.311559 RO MCACHE 2. 0xffffc000 0x00001104
9445 23:05:53.314758 CONSOLE 3. 0xfff7c000 0x00080000
9446 23:05:53.318411 FMAP 4. 0xfff7b000 0x00000452
9447 23:05:53.321491 TIME STAMP 5. 0xfff7a000 0x00000910
9448 23:05:53.324709 VBOOT WORK 6. 0xfff66000 0x00014000
9449 23:05:53.328511 RAMOOPS 7. 0xffe66000 0x00100000
9450 23:05:53.331835 COREBOOT 8. 0xffe64000 0x00002000
9451 23:05:53.331920 IMD small region:
9452 23:05:53.334935 IMD ROOT 0. 0xffffec00 0x00000400
9453 23:05:53.338635 VPD 1. 0xffffeb80 0x0000006c
9454 23:05:53.344937 MMC STATUS 2. 0xffffeb60 0x00000004
9455 23:05:53.348416 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9456 23:05:53.351863 Probing TPM: done!
9457 23:05:53.355408 Connected to device vid:did:rid of 1ae0:0028:00
9458 23:05:53.365528 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9459 23:05:53.368416 Initialized TPM device CR50 revision 0
9460 23:05:53.372269 Checking cr50 for pending updates
9461 23:05:53.375860 Reading cr50 TPM mode
9462 23:05:53.384168 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9463 23:05:53.390911 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9464 23:05:53.430838 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9465 23:05:53.434660 Checking segment from ROM address 0x40100000
9466 23:05:53.438095 Checking segment from ROM address 0x4010001c
9467 23:05:53.444686 Loading segment from ROM address 0x40100000
9468 23:05:53.444771 code (compression=0)
9469 23:05:53.451253 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9470 23:05:53.461076 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9471 23:05:53.461161 it's not compressed!
9472 23:05:53.468166 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9473 23:05:53.471269 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9474 23:05:53.491251 Loading segment from ROM address 0x4010001c
9475 23:05:53.491336 Entry Point 0x80000000
9476 23:05:53.494918 Loaded segments
9477 23:05:53.497979 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9478 23:05:53.505033 Jumping to boot code at 0x80000000(0xffe64000)
9479 23:05:53.511573 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9480 23:05:53.518213 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9481 23:05:53.526348 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9482 23:05:53.529253 Checking segment from ROM address 0x40100000
9483 23:05:53.532676 Checking segment from ROM address 0x4010001c
9484 23:05:53.536363 Loading segment from ROM address 0x40100000
9485 23:05:53.539572 code (compression=1)
9486 23:05:53.546431 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9487 23:05:53.556166 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9488 23:05:53.556251 using LZMA
9489 23:05:53.564084 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9490 23:05:53.570829 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9491 23:05:53.574052 Loading segment from ROM address 0x4010001c
9492 23:05:53.574135 Entry Point 0x54601000
9493 23:05:53.577414 Loaded segments
9494 23:05:53.581168 NOTICE: MT8192 bl31_setup
9495 23:05:53.587989 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9496 23:05:53.591351 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9497 23:05:53.594684 WARNING: region 0:
9498 23:05:53.597964 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9499 23:05:53.598047 WARNING: region 1:
9500 23:05:53.604951 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9501 23:05:53.608011 WARNING: region 2:
9502 23:05:53.611316 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9503 23:05:53.614330 WARNING: region 3:
9504 23:05:53.618096 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9505 23:05:53.621480 WARNING: region 4:
9506 23:05:53.624539 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9507 23:05:53.628281 WARNING: region 5:
9508 23:05:53.631069 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9509 23:05:53.634730 WARNING: region 6:
9510 23:05:53.638135 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9511 23:05:53.638217 WARNING: region 7:
9512 23:05:53.644407 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9513 23:05:53.651505 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9514 23:05:53.654836 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9515 23:05:53.657967 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9516 23:05:53.664992 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9517 23:05:53.668072 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9518 23:05:53.671075 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9519 23:05:53.677968 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9520 23:05:53.681297 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9521 23:05:53.687761 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9522 23:05:53.690844 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9523 23:05:53.694728 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9524 23:05:53.701382 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9525 23:05:53.704380 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9526 23:05:53.707875 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9527 23:05:53.714682 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9528 23:05:53.717851 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9529 23:05:53.721496 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9530 23:05:53.728259 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9531 23:05:53.731291 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9532 23:05:53.734582 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9533 23:05:53.741374 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9534 23:05:53.744960 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9535 23:05:53.751870 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9536 23:05:53.754895 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9537 23:05:53.758176 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9538 23:05:53.764842 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9539 23:05:53.768279 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9540 23:05:53.774769 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9541 23:05:53.778357 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9542 23:05:53.781348 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9543 23:05:53.788666 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9544 23:05:53.791856 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9545 23:05:53.795150 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9546 23:05:53.801688 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9547 23:05:53.805422 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9548 23:05:53.808468 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9549 23:05:53.811601 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9550 23:05:53.818776 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9551 23:05:53.822145 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9552 23:05:53.825033 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9553 23:05:53.828479 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9554 23:05:53.835563 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9555 23:05:53.838606 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9556 23:05:53.842130 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9557 23:05:53.845384 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9558 23:05:53.851789 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9559 23:05:53.855060 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9560 23:05:53.858552 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9561 23:05:53.865010 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9562 23:05:53.868398 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9563 23:05:53.871986 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9564 23:05:53.878474 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9565 23:05:53.881723 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9566 23:05:53.888660 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9567 23:05:53.891559 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9568 23:05:53.895343 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9569 23:05:53.901780 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9570 23:05:53.905081 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9571 23:05:53.912008 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9572 23:05:53.915121 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9573 23:05:53.922138 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9574 23:05:53.925368 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9575 23:05:53.931945 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9576 23:05:53.935609 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9577 23:05:53.938613 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9578 23:05:53.945235 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9579 23:05:53.948766 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9580 23:05:53.955722 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9581 23:05:53.959016 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9582 23:05:53.962269 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9583 23:05:53.968643 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9584 23:05:53.972133 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9585 23:05:53.978523 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9586 23:05:53.982024 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9587 23:05:53.988817 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9588 23:05:53.991908 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9589 23:05:53.995762 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9590 23:05:54.002274 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9591 23:05:54.005758 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9592 23:05:54.012151 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9593 23:05:54.015444 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9594 23:05:54.022216 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9595 23:05:54.025481 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9596 23:05:54.029147 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9597 23:05:54.035739 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9598 23:05:54.038842 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9599 23:05:54.045950 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9600 23:05:54.048816 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9601 23:05:54.055331 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9602 23:05:54.059247 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9603 23:05:54.062566 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9604 23:05:54.069111 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9605 23:05:54.072217 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9606 23:05:54.079239 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9607 23:05:54.082589 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9608 23:05:54.089021 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9609 23:05:54.092272 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9610 23:05:54.095478 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9611 23:05:54.099214 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9612 23:05:54.105387 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9613 23:05:54.109149 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9614 23:05:54.112367 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9615 23:05:54.119232 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9616 23:05:54.122387 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9617 23:05:54.129080 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9618 23:05:54.132057 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9619 23:05:54.135837 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9620 23:05:54.142137 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9621 23:05:54.145796 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9622 23:05:54.152129 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9623 23:05:54.155588 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9624 23:05:54.158977 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9625 23:05:54.165667 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9626 23:05:54.168739 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9627 23:05:54.172817 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9628 23:05:54.179226 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9629 23:05:54.182415 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9630 23:05:54.186079 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9631 23:05:54.192354 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9632 23:05:54.195362 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9633 23:05:54.199142 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9634 23:05:54.202814 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9635 23:05:54.209131 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9636 23:05:54.212215 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9637 23:05:54.216043 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9638 23:05:54.222854 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9639 23:05:54.225892 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9640 23:05:54.229259 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9641 23:05:54.235768 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9642 23:05:54.239639 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9643 23:05:54.246485 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9644 23:05:54.249339 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9645 23:05:54.253003 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9646 23:05:54.259282 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9647 23:05:54.262862 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9648 23:05:54.266288 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9649 23:05:54.273251 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9650 23:05:54.276208 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9651 23:05:54.279486 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9652 23:05:54.286431 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9653 23:05:54.289413 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9654 23:05:54.296393 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9655 23:05:54.299558 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9656 23:05:54.303171 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9657 23:05:54.309627 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9658 23:05:54.313244 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9659 23:05:54.319418 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9660 23:05:54.322945 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9661 23:05:54.326047 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9662 23:05:54.333340 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9663 23:05:54.336559 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9664 23:05:54.340018 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9665 23:05:54.346215 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9666 23:05:54.349974 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9667 23:05:54.356195 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9668 23:05:54.359475 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9669 23:05:54.362703 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9670 23:05:54.369704 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9671 23:05:54.372846 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9672 23:05:54.379854 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9673 23:05:54.383236 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9674 23:05:54.386267 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9675 23:05:54.393271 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9676 23:05:54.396506 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9677 23:05:54.402865 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9678 23:05:54.406539 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9679 23:05:54.409689 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9680 23:05:54.416669 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9681 23:05:54.419945 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9682 23:05:54.422983 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9683 23:05:54.429727 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9684 23:05:54.432660 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9685 23:05:54.439310 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9686 23:05:54.442750 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9687 23:05:54.445976 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9688 23:05:54.452896 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9689 23:05:54.456014 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9690 23:05:54.462398 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9691 23:05:54.466302 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9692 23:05:54.469500 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9693 23:05:54.475944 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9694 23:05:54.479069 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9695 23:05:54.485712 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9696 23:05:54.488981 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9697 23:05:54.492540 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9698 23:05:54.499165 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9699 23:05:54.502572 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9700 23:05:54.508925 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9701 23:05:54.512477 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9702 23:05:54.515531 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9703 23:05:54.522653 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9704 23:05:54.525751 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9705 23:05:54.532532 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9706 23:05:54.535803 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9707 23:05:54.538710 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9708 23:05:54.545705 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9709 23:05:54.549593 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9710 23:05:54.555575 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9711 23:05:54.558869 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9712 23:05:54.565770 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9713 23:05:54.569001 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9714 23:05:54.572187 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9715 23:05:54.578758 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9716 23:05:54.582654 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9717 23:05:54.589074 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9718 23:05:54.592021 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9719 23:05:54.598503 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9720 23:05:54.601879 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9721 23:05:54.605512 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9722 23:05:54.612165 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9723 23:05:54.615117 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9724 23:05:54.621905 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9725 23:05:54.625395 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9726 23:05:54.628701 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9727 23:05:54.634982 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9728 23:05:54.638734 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9729 23:05:54.645072 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9730 23:05:54.648411 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9731 23:05:54.654843 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9732 23:05:54.658568 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9733 23:05:54.661785 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9734 23:05:54.668011 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9735 23:05:54.671983 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9736 23:05:54.678268 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9737 23:05:54.681511 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9738 23:05:54.684760 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9739 23:05:54.691298 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9740 23:05:54.695131 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9741 23:05:54.701610 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9742 23:05:54.704500 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9743 23:05:54.708009 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9744 23:05:54.710996 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9745 23:05:54.717499 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9746 23:05:54.721188 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9747 23:05:54.724460 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9748 23:05:54.730972 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9749 23:05:54.734069 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9750 23:05:54.737488 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9751 23:05:54.744103 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9752 23:05:54.747314 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9753 23:05:54.754194 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9754 23:05:54.757685 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9755 23:05:54.760547 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9756 23:05:54.767170 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9757 23:05:54.770807 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9758 23:05:54.773771 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9759 23:05:54.780416 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9760 23:05:54.784174 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9761 23:05:54.787605 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9762 23:05:54.793962 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9763 23:05:54.797175 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9764 23:05:54.803954 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9765 23:05:54.807514 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9766 23:05:54.810454 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9767 23:05:54.817018 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9768 23:05:54.820722 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9769 23:05:54.823669 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9770 23:05:54.830771 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9771 23:05:54.833715 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9772 23:05:54.836844 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9773 23:05:54.843772 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9774 23:05:54.846672 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9775 23:05:54.853847 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9776 23:05:54.857092 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9777 23:05:54.860143 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9778 23:05:54.866788 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9779 23:05:54.870613 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9780 23:05:54.873743 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9781 23:05:54.880100 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9782 23:05:54.883597 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9783 23:05:54.887193 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9784 23:05:54.890574 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9785 23:05:54.896878 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9786 23:05:54.900020 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9787 23:05:54.903261 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9788 23:05:54.907076 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9789 23:05:54.913379 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9790 23:05:54.916556 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9791 23:05:54.920163 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9792 23:05:54.923201 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9793 23:05:54.929733 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9794 23:05:54.933440 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9795 23:05:54.936682 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9796 23:05:54.942949 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9797 23:05:54.946577 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9798 23:05:54.952881 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9799 23:05:54.956376 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9800 23:05:54.960013 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9801 23:05:54.966376 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9802 23:05:54.969698 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9803 23:05:54.976507 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9804 23:05:54.979640 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9805 23:05:54.983222 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9806 23:05:54.989527 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9807 23:05:54.993045 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9808 23:05:54.999711 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9809 23:05:55.002949 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9810 23:05:55.006035 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9811 23:05:55.012736 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9812 23:05:55.016400 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9813 23:05:55.022739 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9814 23:05:55.026262 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9815 23:05:55.032956 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9816 23:05:55.035947 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9817 23:05:55.039607 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9818 23:05:55.045854 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9819 23:05:55.049283 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9820 23:05:55.055862 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9821 23:05:55.058869 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9822 23:05:55.065666 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9823 23:05:55.068902 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9824 23:05:55.072022 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9825 23:05:55.079020 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9826 23:05:55.081964 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9827 23:05:55.088857 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9828 23:05:55.092477 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9829 23:05:55.095887 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9830 23:05:55.102226 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9831 23:05:55.106050 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9832 23:05:55.112460 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9833 23:05:55.115978 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9834 23:05:55.119179 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9835 23:05:55.126004 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9836 23:05:55.129146 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9837 23:05:55.135940 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9838 23:05:55.139078 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9839 23:05:55.145667 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9840 23:05:55.149221 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9841 23:05:55.151893 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9842 23:05:55.158863 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9843 23:05:55.162786 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9844 23:05:55.165872 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9845 23:05:55.172985 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9846 23:05:55.175691 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9847 23:05:55.182179 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9848 23:05:55.186301 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9849 23:05:55.192359 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9850 23:05:55.196253 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9851 23:05:55.198982 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9852 23:05:55.206001 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9853 23:05:55.209225 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9854 23:05:55.215925 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9855 23:05:55.219676 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9856 23:05:55.222695 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9857 23:05:55.229410 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9858 23:05:55.232369 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9859 23:05:55.238609 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9860 23:05:55.242437 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9861 23:05:55.245747 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9862 23:05:55.252556 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9863 23:05:55.255688 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9864 23:05:55.262149 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9865 23:05:55.265364 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9866 23:05:55.268974 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9867 23:05:55.275511 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9868 23:05:55.278685 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9869 23:05:55.285659 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9870 23:05:55.288566 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9871 23:05:55.295356 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9872 23:05:55.298789 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9873 23:05:55.305711 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9874 23:05:55.308575 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9875 23:05:55.311713 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9876 23:05:55.318604 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9877 23:05:55.322197 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9878 23:05:55.328581 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9879 23:05:55.331886 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9880 23:05:55.338442 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9881 23:05:55.342203 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9882 23:05:55.345616 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9883 23:05:55.351602 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9884 23:05:55.355446 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9885 23:05:55.361635 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9886 23:05:55.365289 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9887 23:05:55.371451 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9888 23:05:55.375019 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9889 23:05:55.381353 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9890 23:05:55.384629 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9891 23:05:55.388095 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9892 23:05:55.395192 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9893 23:05:55.398577 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9894 23:05:55.405019 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9895 23:05:55.408375 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9896 23:05:55.414663 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9897 23:05:55.418072 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9898 23:05:55.421730 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9899 23:05:55.428617 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9900 23:05:55.431057 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9901 23:05:55.438306 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9902 23:05:55.441709 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9903 23:05:55.447994 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9904 23:05:55.451714 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9905 23:05:55.454885 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9906 23:05:55.461828 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9907 23:05:55.465112 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9908 23:05:55.471303 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9909 23:05:55.474534 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9910 23:05:55.481354 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9911 23:05:55.484476 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9912 23:05:55.488429 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9913 23:05:55.494356 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9914 23:05:55.498193 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9915 23:05:55.504015 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9916 23:05:55.507743 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9917 23:05:55.511061 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9918 23:05:55.517902 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9919 23:05:55.521380 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9920 23:05:55.528350 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9921 23:05:55.531130 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9922 23:05:55.538196 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9923 23:05:55.540935 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9924 23:05:55.547824 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9925 23:05:55.551172 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9926 23:05:55.557654 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9927 23:05:55.561017 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9928 23:05:55.567216 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9929 23:05:55.571269 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9930 23:05:55.577425 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9931 23:05:55.580976 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9932 23:05:55.587290 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9933 23:05:55.591205 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9934 23:05:55.597218 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9935 23:05:55.601068 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9936 23:05:55.607441 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9937 23:05:55.610975 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9938 23:05:55.617029 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9939 23:05:55.620892 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9940 23:05:55.626808 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9941 23:05:55.630710 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9942 23:05:55.637199 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9943 23:05:55.640205 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9944 23:05:55.646945 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9945 23:05:55.650260 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9946 23:05:55.657101 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9947 23:05:55.660286 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9948 23:05:55.663713 INFO: [APUAPC] vio 0
9949 23:05:55.667340 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9950 23:05:55.674039 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9951 23:05:55.677240 INFO: [APUAPC] D0_APC_0: 0x400510
9952 23:05:55.677805 INFO: [APUAPC] D0_APC_1: 0x0
9953 23:05:55.680170 INFO: [APUAPC] D0_APC_2: 0x1540
9954 23:05:55.683449 INFO: [APUAPC] D0_APC_3: 0x0
9955 23:05:55.687297 INFO: [APUAPC] D1_APC_0: 0xffffffff
9956 23:05:55.690291 INFO: [APUAPC] D1_APC_1: 0xffffffff
9957 23:05:55.693448 INFO: [APUAPC] D1_APC_2: 0x3fffff
9958 23:05:55.696591 INFO: [APUAPC] D1_APC_3: 0x0
9959 23:05:55.700156 INFO: [APUAPC] D2_APC_0: 0xffffffff
9960 23:05:55.703293 INFO: [APUAPC] D2_APC_1: 0xffffffff
9961 23:05:55.706595 INFO: [APUAPC] D2_APC_2: 0x3fffff
9962 23:05:55.710058 INFO: [APUAPC] D2_APC_3: 0x0
9963 23:05:55.713420 INFO: [APUAPC] D3_APC_0: 0xffffffff
9964 23:05:55.716559 INFO: [APUAPC] D3_APC_1: 0xffffffff
9965 23:05:55.720158 INFO: [APUAPC] D3_APC_2: 0x3fffff
9966 23:05:55.723328 INFO: [APUAPC] D3_APC_3: 0x0
9967 23:05:55.726232 INFO: [APUAPC] D4_APC_0: 0xffffffff
9968 23:05:55.729879 INFO: [APUAPC] D4_APC_1: 0xffffffff
9969 23:05:55.733260 INFO: [APUAPC] D4_APC_2: 0x3fffff
9970 23:05:55.736684 INFO: [APUAPC] D4_APC_3: 0x0
9971 23:05:55.740106 INFO: [APUAPC] D5_APC_0: 0xffffffff
9972 23:05:55.743000 INFO: [APUAPC] D5_APC_1: 0xffffffff
9973 23:05:55.746429 INFO: [APUAPC] D5_APC_2: 0x3fffff
9974 23:05:55.749738 INFO: [APUAPC] D5_APC_3: 0x0
9975 23:05:55.753083 INFO: [APUAPC] D6_APC_0: 0xffffffff
9976 23:05:55.756848 INFO: [APUAPC] D6_APC_1: 0xffffffff
9977 23:05:55.759983 INFO: [APUAPC] D6_APC_2: 0x3fffff
9978 23:05:55.762818 INFO: [APUAPC] D6_APC_3: 0x0
9979 23:05:55.766162 INFO: [APUAPC] D7_APC_0: 0xffffffff
9980 23:05:55.769696 INFO: [APUAPC] D7_APC_1: 0xffffffff
9981 23:05:55.772935 INFO: [APUAPC] D7_APC_2: 0x3fffff
9982 23:05:55.776100 INFO: [APUAPC] D7_APC_3: 0x0
9983 23:05:55.779373 INFO: [APUAPC] D8_APC_0: 0xffffffff
9984 23:05:55.782534 INFO: [APUAPC] D8_APC_1: 0xffffffff
9985 23:05:55.785725 INFO: [APUAPC] D8_APC_2: 0x3fffff
9986 23:05:55.789705 INFO: [APUAPC] D8_APC_3: 0x0
9987 23:05:55.792618 INFO: [APUAPC] D9_APC_0: 0xffffffff
9988 23:05:55.796394 INFO: [APUAPC] D9_APC_1: 0xffffffff
9989 23:05:55.799285 INFO: [APUAPC] D9_APC_2: 0x3fffff
9990 23:05:55.799466 INFO: [APUAPC] D9_APC_3: 0x0
9991 23:05:55.805458 INFO: [APUAPC] D10_APC_0: 0xffffffff
9992 23:05:55.809148 INFO: [APUAPC] D10_APC_1: 0xffffffff
9993 23:05:55.812413 INFO: [APUAPC] D10_APC_2: 0x3fffff
9994 23:05:55.815346 INFO: [APUAPC] D10_APC_3: 0x0
9995 23:05:55.818925 INFO: [APUAPC] D11_APC_0: 0xffffffff
9996 23:05:55.821950 INFO: [APUAPC] D11_APC_1: 0xffffffff
9997 23:05:55.825718 INFO: [APUAPC] D11_APC_2: 0x3fffff
9998 23:05:55.828857 INFO: [APUAPC] D11_APC_3: 0x0
9999 23:05:55.831974 INFO: [APUAPC] D12_APC_0: 0xffffffff
10000 23:05:55.835249 INFO: [APUAPC] D12_APC_1: 0xffffffff
10001 23:05:55.838790 INFO: [APUAPC] D12_APC_2: 0x3fffff
10002 23:05:55.841862 INFO: [APUAPC] D12_APC_3: 0x0
10003 23:05:55.845080 INFO: [APUAPC] D13_APC_0: 0xffffffff
10004 23:05:55.848754 INFO: [APUAPC] D13_APC_1: 0xffffffff
10005 23:05:55.851806 INFO: [APUAPC] D13_APC_2: 0x3fffff
10006 23:05:55.855794 INFO: [APUAPC] D13_APC_3: 0x0
10007 23:05:55.858473 INFO: [APUAPC] D14_APC_0: 0xffffffff
10008 23:05:55.862034 INFO: [APUAPC] D14_APC_1: 0xffffffff
10009 23:05:55.865464 INFO: [APUAPC] D14_APC_2: 0x3fffff
10010 23:05:55.868667 INFO: [APUAPC] D14_APC_3: 0x0
10011 23:05:55.871697 INFO: [APUAPC] D15_APC_0: 0xffffffff
10012 23:05:55.875368 INFO: [APUAPC] D15_APC_1: 0xffffffff
10013 23:05:55.878608 INFO: [APUAPC] D15_APC_2: 0x3fffff
10014 23:05:55.881757 INFO: [APUAPC] D15_APC_3: 0x0
10015 23:05:55.881839 INFO: [APUAPC] APC_CON: 0x4
10016 23:05:55.885853 INFO: [NOCDAPC] D0_APC_0: 0x0
10017 23:05:55.888936 INFO: [NOCDAPC] D0_APC_1: 0x0
10018 23:05:55.891921 INFO: [NOCDAPC] D1_APC_0: 0x0
10019 23:05:55.895091 INFO: [NOCDAPC] D1_APC_1: 0xfff
10020 23:05:55.898741 INFO: [NOCDAPC] D2_APC_0: 0x0
10021 23:05:55.901922 INFO: [NOCDAPC] D2_APC_1: 0xfff
10022 23:05:55.905080 INFO: [NOCDAPC] D3_APC_0: 0x0
10023 23:05:55.908107 INFO: [NOCDAPC] D3_APC_1: 0xfff
10024 23:05:55.912044 INFO: [NOCDAPC] D4_APC_0: 0x0
10025 23:05:55.915367 INFO: [NOCDAPC] D4_APC_1: 0xfff
10026 23:05:55.915447 INFO: [NOCDAPC] D5_APC_0: 0x0
10027 23:05:55.918467 INFO: [NOCDAPC] D5_APC_1: 0xfff
10028 23:05:55.921934 INFO: [NOCDAPC] D6_APC_0: 0x0
10029 23:05:55.924872 INFO: [NOCDAPC] D6_APC_1: 0xfff
10030 23:05:55.928492 INFO: [NOCDAPC] D7_APC_0: 0x0
10031 23:05:55.931811 INFO: [NOCDAPC] D7_APC_1: 0xfff
10032 23:05:55.934579 INFO: [NOCDAPC] D8_APC_0: 0x0
10033 23:05:55.938382 INFO: [NOCDAPC] D8_APC_1: 0xfff
10034 23:05:55.941530 INFO: [NOCDAPC] D9_APC_0: 0x0
10035 23:05:55.944912 INFO: [NOCDAPC] D9_APC_1: 0xfff
10036 23:05:55.947858 INFO: [NOCDAPC] D10_APC_0: 0x0
10037 23:05:55.951686 INFO: [NOCDAPC] D10_APC_1: 0xfff
10038 23:05:55.951768 INFO: [NOCDAPC] D11_APC_0: 0x0
10039 23:05:55.954721 INFO: [NOCDAPC] D11_APC_1: 0xfff
10040 23:05:55.958163 INFO: [NOCDAPC] D12_APC_0: 0x0
10041 23:05:55.961466 INFO: [NOCDAPC] D12_APC_1: 0xfff
10042 23:05:55.964629 INFO: [NOCDAPC] D13_APC_0: 0x0
10043 23:05:55.968599 INFO: [NOCDAPC] D13_APC_1: 0xfff
10044 23:05:55.971445 INFO: [NOCDAPC] D14_APC_0: 0x0
10045 23:05:55.975002 INFO: [NOCDAPC] D14_APC_1: 0xfff
10046 23:05:55.977785 INFO: [NOCDAPC] D15_APC_0: 0x0
10047 23:05:55.981320 INFO: [NOCDAPC] D15_APC_1: 0xfff
10048 23:05:55.984951 INFO: [NOCDAPC] APC_CON: 0x4
10049 23:05:55.988080 INFO: [APUAPC] set_apusys_apc done
10050 23:05:55.991478 INFO: [DEVAPC] devapc_init done
10051 23:05:55.994378 INFO: GICv3 without legacy support detected.
10052 23:05:55.998292 INFO: ARM GICv3 driver initialized in EL3
10053 23:05:56.001287 INFO: Maximum SPI INTID supported: 639
10054 23:05:56.004625 INFO: BL31: Initializing runtime services
10055 23:05:56.011176 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10056 23:05:56.014414 INFO: SPM: enable CPC mode
10057 23:05:56.020976 INFO: mcdi ready for mcusys-off-idle and system suspend
10058 23:05:56.024242 INFO: BL31: Preparing for EL3 exit to normal world
10059 23:05:56.027836 INFO: Entry point address = 0x80000000
10060 23:05:56.030979 INFO: SPSR = 0x8
10061 23:05:56.035986
10062 23:05:56.036067
10063 23:05:56.036131
10064 23:05:56.036796 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10065 23:05:56.036894 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10066 23:05:56.036983 Setting prompt string to ['asurada:']
10067 23:05:56.037063 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10068 23:05:56.039246 Starting depthcharge on Spherion...
10069 23:05:56.039328
10070 23:05:56.039391 Wipe memory regions:
10071 23:05:56.039450
10072 23:05:56.042691 [0x00000040000000, 0x00000054600000)
10073 23:05:56.164697
10074 23:05:56.164813 [0x00000054660000, 0x00000080000000)
10075 23:05:56.425051
10076 23:05:56.425193 [0x000000821a7280, 0x000000ffe64000)
10077 23:05:57.170185
10078 23:05:57.170330 [0x00000100000000, 0x00000240000000)
10079 23:05:59.060680
10080 23:05:59.063602 Initializing XHCI USB controller at 0x11200000.
10081 23:06:00.102336
10082 23:06:00.105368 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10083 23:06:00.105451
10084 23:06:00.105516
10085 23:06:00.105584
10086 23:06:00.105870 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10088 23:06:00.206232 asurada: tftpboot 192.168.201.1 12154385/tftp-deploy-cllkt166/kernel/image.itb 12154385/tftp-deploy-cllkt166/kernel/cmdline
10089 23:06:00.206383 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10090 23:06:00.206467 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10091 23:06:00.210595 tftpboot 192.168.201.1 12154385/tftp-deploy-cllkt166/kernel/image.itp-deploy-cllkt166/kernel/cmdline
10092 23:06:00.210679
10093 23:06:00.210743 Waiting for link
10094 23:06:00.369044
10095 23:06:00.369174 R8152: Initializing
10096 23:06:00.369285
10097 23:06:00.372200 Version 9 (ocp_data = 6010)
10098 23:06:00.372281
10099 23:06:00.375333 R8152: Done initializing
10100 23:06:00.375472
10101 23:06:00.375597 Adding net device
10102 23:06:02.250332
10103 23:06:02.250478 done.
10104 23:06:02.250548
10105 23:06:02.250620 MAC: 00:e0:4c:78:7a:aa
10106 23:06:02.250681
10107 23:06:02.253490 Sending DHCP discover... done.
10108 23:06:02.253597
10109 23:06:02.256880 Waiting for reply... done.
10110 23:06:02.256975
10111 23:06:02.259812 Sending DHCP request... done.
10112 23:06:02.259913
10113 23:06:02.260003 Waiting for reply... done.
10114 23:06:02.260097
10115 23:06:02.263697 My ip is 192.168.201.12
10116 23:06:02.263778
10117 23:06:02.266570 The DHCP server ip is 192.168.201.1
10118 23:06:02.266672
10119 23:06:02.269891 TFTP server IP predefined by user: 192.168.201.1
10120 23:06:02.269972
10121 23:06:02.276458 Bootfile predefined by user: 12154385/tftp-deploy-cllkt166/kernel/image.itb
10122 23:06:02.276564
10123 23:06:02.279528 Sending tftp read request... done.
10124 23:06:02.279616
10125 23:06:02.282827 Waiting for the transfer...
10126 23:06:02.282936
10127 23:06:02.570103 00000000 ################################################################
10128 23:06:02.570241
10129 23:06:02.842305 00080000 ################################################################
10130 23:06:02.842467
10131 23:06:03.129686 00100000 ################################################################
10132 23:06:03.129816
10133 23:06:03.399374 00180000 ################################################################
10134 23:06:03.399570
10135 23:06:03.642552 00200000 ################################################################
10136 23:06:03.642690
10137 23:06:03.890352 00280000 ################################################################
10138 23:06:03.890523
10139 23:06:04.135280 00300000 ################################################################
10140 23:06:04.135415
10141 23:06:04.382705 00380000 ################################################################
10142 23:06:04.382868
10143 23:06:04.629526 00400000 ################################################################
10144 23:06:04.629693
10145 23:06:04.912456 00480000 ################################################################
10146 23:06:04.912607
10147 23:06:05.180577 00500000 ################################################################
10148 23:06:05.180712
10149 23:06:05.450684 00580000 ################################################################
10150 23:06:05.450815
10151 23:06:05.709718 00600000 ################################################################
10152 23:06:05.709850
10153 23:06:05.976194 00680000 ################################################################
10154 23:06:05.976332
10155 23:06:06.267709 00700000 ################################################################
10156 23:06:06.267847
10157 23:06:06.562363 00780000 ################################################################
10158 23:06:06.562494
10159 23:06:06.833113 00800000 ################################################################
10160 23:06:06.833250
10161 23:06:07.118877 00880000 ################################################################
10162 23:06:07.119007
10163 23:06:07.381006 00900000 ################################################################
10164 23:06:07.381138
10165 23:06:07.641605 00980000 ################################################################
10166 23:06:07.641736
10167 23:06:07.914207 00a00000 ################################################################
10168 23:06:07.914340
10169 23:06:08.182600 00a80000 ################################################################
10170 23:06:08.182740
10171 23:06:08.449781 00b00000 ################################################################
10172 23:06:08.449926
10173 23:06:08.738558 00b80000 ################################################################
10174 23:06:08.738690
10175 23:06:09.024227 00c00000 ################################################################
10176 23:06:09.024364
10177 23:06:09.295553 00c80000 ################################################################
10178 23:06:09.295693
10179 23:06:09.573063 00d00000 ################################################################
10180 23:06:09.573198
10181 23:06:09.866547 00d80000 ################################################################
10182 23:06:09.866682
10183 23:06:10.122813 00e00000 ################################################################
10184 23:06:10.122955
10185 23:06:10.383243 00e80000 ################################################################
10186 23:06:10.383375
10187 23:06:10.659032 00f00000 ################################################################
10188 23:06:10.659166
10189 23:06:10.952544 00f80000 ################################################################
10190 23:06:10.952693
10191 23:06:11.201900 01000000 ################################################################
10192 23:06:11.202073
10193 23:06:11.485881 01080000 ################################################################
10194 23:06:11.486015
10195 23:06:11.753796 01100000 ################################################################
10196 23:06:11.753934
10197 23:06:12.036058 01180000 ################################################################
10198 23:06:12.036198
10199 23:06:12.301820 01200000 ################################################################
10200 23:06:12.301962
10201 23:06:12.555357 01280000 ################################################################
10202 23:06:12.555495
10203 23:06:12.829521 01300000 ################################################################
10204 23:06:12.829665
10205 23:06:13.090724 01380000 ################################################################
10206 23:06:13.090870
10207 23:06:13.355121 01400000 ################################################################
10208 23:06:13.355268
10209 23:06:13.650069 01480000 ################################################################
10210 23:06:13.650215
10211 23:06:13.927309 01500000 ################################################################
10212 23:06:13.927442
10213 23:06:14.193512 01580000 ################################################################
10214 23:06:14.193683
10215 23:06:14.465269 01600000 ################################################################
10216 23:06:14.465436
10217 23:06:14.729192 01680000 ################################################################
10218 23:06:14.729353
10219 23:06:14.993852 01700000 ################################################################
10220 23:06:14.994010
10221 23:06:15.330714 01780000 ################################################################
10222 23:06:15.330862
10223 23:06:15.618069 01800000 ################################################################
10224 23:06:15.618198
10225 23:06:15.915843 01880000 ################################################################
10226 23:06:15.915985
10227 23:06:16.195933 01900000 ################################################################
10228 23:06:16.196069
10229 23:06:16.463776 01980000 ################################################################
10230 23:06:16.463924
10231 23:06:16.753389 01a00000 ################################################################
10232 23:06:16.753533
10233 23:06:17.050351 01a80000 ################################################################
10234 23:06:17.050497
10235 23:06:17.339199 01b00000 ################################################################
10236 23:06:17.339355
10237 23:06:17.368509 01b80000 ####### done.
10238 23:06:17.368600
10239 23:06:17.371820 The bootfile was 28885662 bytes long.
10240 23:06:17.371904
10241 23:06:17.375149 Sending tftp read request... done.
10242 23:06:17.375232
10243 23:06:17.378626 Waiting for the transfer...
10244 23:06:17.378710
10245 23:06:17.378776 00000000 # done.
10246 23:06:17.378838
10247 23:06:17.385777 Command line loaded dynamically from TFTP file: 12154385/tftp-deploy-cllkt166/kernel/cmdline
10248 23:06:17.388749
10249 23:06:17.408698 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12154385/extract-nfsrootfs-p6jmt7b4,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10250 23:06:17.408787
10251 23:06:17.408853 Loading FIT.
10252 23:06:17.411717
10253 23:06:17.411805 Image ramdisk-1 has 17792366 bytes.
10254 23:06:17.411875
10255 23:06:17.415930 Image fdt-1 has 47278 bytes.
10256 23:06:17.416102
10257 23:06:17.418372 Image kernel-1 has 11043984 bytes.
10258 23:06:17.418496
10259 23:06:17.428129 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10260 23:06:17.428313
10261 23:06:17.444863 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10262 23:06:17.445036
10263 23:06:17.452104 Choosing best match conf-1 for compat google,spherion-rev2.
10264 23:06:17.452307
10265 23:06:17.459666 Connected to device vid:did:rid of 1ae0:0028:00
10266 23:06:17.467911
10267 23:06:17.471504 tpm_get_response: command 0x17b, return code 0x0
10268 23:06:17.471930
10269 23:06:17.474654 ec_init: CrosEC protocol v3 supported (256, 248)
10270 23:06:17.479068
10271 23:06:17.482554 tpm_cleanup: add release locality here.
10272 23:06:17.482979
10273 23:06:17.483314 Shutting down all USB controllers.
10274 23:06:17.483621
10275 23:06:17.485876 Removing current net device
10276 23:06:17.486371
10277 23:06:17.493055 Exiting depthcharge with code 4 at timestamp: 50707042
10278 23:06:17.493478
10279 23:06:17.496198 LZMA decompressing kernel-1 to 0x821a6718
10280 23:06:17.496660
10281 23:06:17.499222 LZMA decompressing kernel-1 to 0x40000000
10282 23:06:18.893059
10283 23:06:18.893493 jumping to kernel
10284 23:06:18.894764 end: 2.2.4 bootloader-commands (duration 00:00:23) [common]
10285 23:06:18.895116 start: 2.2.5 auto-login-action (timeout 00:04:02) [common]
10286 23:06:18.895386 Setting prompt string to ['Linux version [0-9]']
10287 23:06:18.895635 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10288 23:06:18.895883 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10289 23:06:18.975224
10290 23:06:18.978442 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10291 23:06:18.982222 start: 2.2.5.1 login-action (timeout 00:04:02) [common]
10292 23:06:18.982692 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10293 23:06:18.983062 Setting prompt string to []
10294 23:06:18.983444 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10295 23:06:18.983811 Using line separator: #'\n'#
10296 23:06:18.984119 No login prompt set.
10297 23:06:18.984445 Parsing kernel messages
10298 23:06:18.984732 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10299 23:06:18.985233 [login-action] Waiting for messages, (timeout 00:04:02)
10300 23:06:19.001648 [ 0.000000] Linux version 6.1.64-cip10 (KernelCI@build-j31357-arm64-gcc-10-defconfig-arm64-chromebook-69txj) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Dec 1 22:47:09 UTC 2023
10301 23:06:19.004958 [ 0.000000] random: crng init done
10302 23:06:19.011598 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10303 23:06:19.014994 [ 0.000000] efi: UEFI not found.
10304 23:06:19.021659 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10305 23:06:19.027860 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10306 23:06:19.037767 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10307 23:06:19.048403 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10308 23:06:19.054907 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10309 23:06:19.060914 [ 0.000000] printk: bootconsole [mtk8250] enabled
10310 23:06:19.068077 [ 0.000000] NUMA: No NUMA configuration found
10311 23:06:19.074337 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10312 23:06:19.077663 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10313 23:06:19.081488 [ 0.000000] Zone ranges:
10314 23:06:19.088156 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10315 23:06:19.091340 [ 0.000000] DMA32 empty
10316 23:06:19.097779 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10317 23:06:19.101503 [ 0.000000] Movable zone start for each node
10318 23:06:19.104685 [ 0.000000] Early memory node ranges
10319 23:06:19.111086 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10320 23:06:19.117832 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10321 23:06:19.124293 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10322 23:06:19.130990 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10323 23:06:19.134570 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10324 23:06:19.140522 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10325 23:06:19.199207 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10326 23:06:19.205656 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10327 23:06:19.212850 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10328 23:06:19.216278 [ 0.000000] psci: probing for conduit method from DT.
10329 23:06:19.222796 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10330 23:06:19.226418 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10331 23:06:19.232590 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10332 23:06:19.235694 [ 0.000000] psci: SMC Calling Convention v1.2
10333 23:06:19.242337 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10334 23:06:19.245531 [ 0.000000] Detected VIPT I-cache on CPU0
10335 23:06:19.252973 [ 0.000000] CPU features: detected: GIC system register CPU interface
10336 23:06:19.259005 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10337 23:06:19.265721 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10338 23:06:19.272339 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10339 23:06:19.281784 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10340 23:06:19.288846 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10341 23:06:19.292151 [ 0.000000] alternatives: applying boot alternatives
10342 23:06:19.298371 [ 0.000000] Fallback order for Node 0: 0
10343 23:06:19.305233 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10344 23:06:19.308161 [ 0.000000] Policy zone: Normal
10345 23:06:19.331144 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12154385/extract-nfsrootfs-p6jmt7b4,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10346 23:06:19.341559 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10347 23:06:19.352216 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10348 23:06:19.362002 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10349 23:06:19.368513 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10350 23:06:19.371444 <6>[ 0.000000] software IO TLB: area num 8.
10351 23:06:19.428683 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10352 23:06:19.577861 <6>[ 0.000000] Memory: 7952180K/8385536K available (17984K kernel code, 4116K rwdata, 17316K rodata, 8448K init, 615K bss, 400588K reserved, 32768K cma-reserved)
10353 23:06:19.584639 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10354 23:06:19.591479 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10355 23:06:19.594529 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10356 23:06:19.600969 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10357 23:06:19.607620 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10358 23:06:19.611450 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10359 23:06:19.621304 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10360 23:06:19.627996 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10361 23:06:19.634430 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10362 23:06:19.641131 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10363 23:06:19.644249 <6>[ 0.000000] GICv3: 608 SPIs implemented
10364 23:06:19.647465 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10365 23:06:19.654157 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10366 23:06:19.657747 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10367 23:06:19.664213 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10368 23:06:19.676998 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10369 23:06:19.690254 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10370 23:06:19.696667 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10371 23:06:19.704566 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10372 23:06:19.717837 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10373 23:06:19.724206 <6>[ 0.000001] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10374 23:06:19.731248 <6>[ 0.009175] Console: colour dummy device 80x25
10375 23:06:19.740580 <6>[ 0.013903] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10376 23:06:19.747276 <6>[ 0.024409] pid_max: default: 32768 minimum: 301
10377 23:06:19.750907 <6>[ 0.029280] LSM: Security Framework initializing
10378 23:06:19.757724 <6>[ 0.034218] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10379 23:06:19.767360 <6>[ 0.042032] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10380 23:06:19.777474 <6>[ 0.051497] cblist_init_generic: Setting adjustable number of callback queues.
10381 23:06:19.780911 <6>[ 0.058938] cblist_init_generic: Setting shift to 3 and lim to 1.
10382 23:06:19.790587 <6>[ 0.065276] cblist_init_generic: Setting adjustable number of callback queues.
10383 23:06:19.797239 <6>[ 0.072749] cblist_init_generic: Setting shift to 3 and lim to 1.
10384 23:06:19.800398 <6>[ 0.079186] rcu: Hierarchical SRCU implementation.
10385 23:06:19.807371 <6>[ 0.084233] rcu: Max phase no-delay instances is 1000.
10386 23:06:19.814276 <6>[ 0.091295] EFI services will not be available.
10387 23:06:19.816982 <6>[ 0.096251] smp: Bringing up secondary CPUs ...
10388 23:06:19.825287 <6>[ 0.101332] Detected VIPT I-cache on CPU1
10389 23:06:19.832066 <6>[ 0.101400] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10390 23:06:19.839101 <6>[ 0.101431] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10391 23:06:19.842379 <6>[ 0.101763] Detected VIPT I-cache on CPU2
10392 23:06:19.848568 <6>[ 0.101813] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10393 23:06:19.855325 <6>[ 0.101828] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10394 23:06:19.861843 <6>[ 0.102084] Detected VIPT I-cache on CPU3
10395 23:06:19.868661 <6>[ 0.102130] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10396 23:06:19.874630 <6>[ 0.102143] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10397 23:06:19.878354 <6>[ 0.102446] CPU features: detected: Spectre-v4
10398 23:06:19.884772 <6>[ 0.102452] CPU features: detected: Spectre-BHB
10399 23:06:19.888231 <6>[ 0.102457] Detected PIPT I-cache on CPU4
10400 23:06:19.894751 <6>[ 0.102515] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10401 23:06:19.901406 <6>[ 0.102531] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10402 23:06:19.908135 <6>[ 0.102825] Detected PIPT I-cache on CPU5
10403 23:06:19.915118 <6>[ 0.102886] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10404 23:06:19.921269 <6>[ 0.102902] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10405 23:06:19.924506 <6>[ 0.103184] Detected PIPT I-cache on CPU6
10406 23:06:19.931384 <6>[ 0.103248] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10407 23:06:19.937875 <6>[ 0.103265] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10408 23:06:19.944029 <6>[ 0.103561] Detected PIPT I-cache on CPU7
10409 23:06:19.950986 <6>[ 0.103625] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10410 23:06:19.957488 <6>[ 0.103642] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10411 23:06:19.960599 <6>[ 0.103689] smp: Brought up 1 node, 8 CPUs
10412 23:06:19.967452 <6>[ 0.244981] SMP: Total of 8 processors activated.
10413 23:06:19.970822 <6>[ 0.249903] CPU features: detected: 32-bit EL0 Support
10414 23:06:19.980550 <6>[ 0.255267] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10415 23:06:19.986800 <6>[ 0.264067] CPU features: detected: Common not Private translations
10416 23:06:19.993553 <6>[ 0.270543] CPU features: detected: CRC32 instructions
10417 23:06:19.997017 <6>[ 0.275894] CPU features: detected: RCpc load-acquire (LDAPR)
10418 23:06:20.003850 <6>[ 0.281853] CPU features: detected: LSE atomic instructions
10419 23:06:20.010319 <6>[ 0.287657] CPU features: detected: Privileged Access Never
10420 23:06:20.017302 <6>[ 0.293437] CPU features: detected: RAS Extension Support
10421 23:06:20.023404 <6>[ 0.299045] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10422 23:06:20.027200 <6>[ 0.306265] CPU: All CPU(s) started at EL2
10423 23:06:20.033223 <6>[ 0.310608] alternatives: applying system-wide alternatives
10424 23:06:20.042632 <6>[ 0.321346] devtmpfs: initialized
10425 23:06:20.058559 <6>[ 0.330251] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10426 23:06:20.065135 <6>[ 0.340215] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10427 23:06:20.071651 <6>[ 0.348425] pinctrl core: initialized pinctrl subsystem
10428 23:06:20.074899 <6>[ 0.355072] DMI not present or invalid.
10429 23:06:20.081390 <6>[ 0.359483] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10430 23:06:20.091249 <6>[ 0.366356] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10431 23:06:20.098172 <6>[ 0.373947] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10432 23:06:20.108021 <6>[ 0.382171] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10433 23:06:20.111396 <6>[ 0.390417] audit: initializing netlink subsys (disabled)
10434 23:06:20.121066 <5>[ 0.396106] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10435 23:06:20.127563 <6>[ 0.396804] thermal_sys: Registered thermal governor 'step_wise'
10436 23:06:20.134224 <6>[ 0.404074] thermal_sys: Registered thermal governor 'power_allocator'
10437 23:06:20.137471 <6>[ 0.410329] cpuidle: using governor menu
10438 23:06:20.144378 <6>[ 0.421290] NET: Registered PF_QIPCRTR protocol family
10439 23:06:20.150693 <6>[ 0.426773] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10440 23:06:20.157703 <6>[ 0.433875] ASID allocator initialised with 32768 entries
10441 23:06:20.160755 <6>[ 0.440428] Serial: AMBA PL011 UART driver
10442 23:06:20.171456 <4>[ 0.449188] Trying to register duplicate clock ID: 134
10443 23:06:20.225388 <6>[ 0.506717] KASLR enabled
10444 23:06:20.239416 <6>[ 0.514403] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10445 23:06:20.246125 <6>[ 0.521416] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10446 23:06:20.252306 <6>[ 0.527907] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10447 23:06:20.259178 <6>[ 0.534912] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10448 23:06:20.265534 <6>[ 0.541398] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10449 23:06:20.272019 <6>[ 0.548404] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10450 23:06:20.278438 <6>[ 0.554890] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10451 23:06:20.285090 <6>[ 0.561897] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10452 23:06:20.288665 <6>[ 0.569410] ACPI: Interpreter disabled.
10453 23:06:20.297411 <6>[ 0.575813] iommu: Default domain type: Translated
10454 23:06:20.304102 <6>[ 0.580925] iommu: DMA domain TLB invalidation policy: strict mode
10455 23:06:20.307083 <5>[ 0.587583] SCSI subsystem initialized
10456 23:06:20.313611 <6>[ 0.591748] usbcore: registered new interface driver usbfs
10457 23:06:20.320816 <6>[ 0.597481] usbcore: registered new interface driver hub
10458 23:06:20.323701 <6>[ 0.603033] usbcore: registered new device driver usb
10459 23:06:20.330223 <6>[ 0.609138] pps_core: LinuxPPS API ver. 1 registered
10460 23:06:20.340753 <6>[ 0.614332] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10461 23:06:20.343494 <6>[ 0.623678] PTP clock support registered
10462 23:06:20.346804 <6>[ 0.627920] EDAC MC: Ver: 3.0.0
10463 23:06:20.354393 <6>[ 0.633083] FPGA manager framework
10464 23:06:20.361091 <6>[ 0.636763] Advanced Linux Sound Architecture Driver Initialized.
10465 23:06:20.364473 <6>[ 0.643541] vgaarb: loaded
10466 23:06:20.370901 <6>[ 0.646709] clocksource: Switched to clocksource arch_sys_counter
10467 23:06:20.374149 <5>[ 0.653146] VFS: Disk quotas dquot_6.6.0
10468 23:06:20.381049 <6>[ 0.657329] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10469 23:06:20.384171 <6>[ 0.664516] pnp: PnP ACPI: disabled
10470 23:06:20.392451 <6>[ 0.671180] NET: Registered PF_INET protocol family
10471 23:06:20.402416 <6>[ 0.676773] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10472 23:06:20.413969 <6>[ 0.689111] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10473 23:06:20.423533 <6>[ 0.697926] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10474 23:06:20.430410 <6>[ 0.705900] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10475 23:06:20.439872 <6>[ 0.714600] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10476 23:06:20.446710 <6>[ 0.724356] TCP: Hash tables configured (established 65536 bind 65536)
10477 23:06:20.453426 <6>[ 0.731227] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10478 23:06:20.463243 <6>[ 0.738427] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10479 23:06:20.470080 <6>[ 0.746103] NET: Registered PF_UNIX/PF_LOCAL protocol family
10480 23:06:20.473568 <6>[ 0.752253] RPC: Registered named UNIX socket transport module.
10481 23:06:20.479836 <6>[ 0.758406] RPC: Registered udp transport module.
10482 23:06:20.483191 <6>[ 0.763338] RPC: Registered tcp transport module.
10483 23:06:20.489852 <6>[ 0.768269] RPC: Registered tcp NFSv4.1 backchannel transport module.
10484 23:06:20.496482 <6>[ 0.774935] PCI: CLS 0 bytes, default 64
10485 23:06:20.499524 <6>[ 0.779272] Unpacking initramfs...
10486 23:06:20.523619 <6>[ 0.798817] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10487 23:06:20.533348 <6>[ 0.807496] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10488 23:06:20.537259 <6>[ 0.816347] kvm [1]: IPA Size Limit: 40 bits
10489 23:06:20.543665 <6>[ 0.820877] kvm [1]: GICv3: no GICV resource entry
10490 23:06:20.546691 <6>[ 0.825900] kvm [1]: disabling GICv2 emulation
10491 23:06:20.553199 <6>[ 0.830594] kvm [1]: GIC system register CPU interface enabled
10492 23:06:20.557026 <6>[ 0.836772] kvm [1]: vgic interrupt IRQ18
10493 23:06:20.563271 <6>[ 0.841123] kvm [1]: VHE mode initialized successfully
10494 23:06:20.570273 <5>[ 0.847456] Initialise system trusted keyrings
10495 23:06:20.576193 <6>[ 0.852259] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10496 23:06:20.583897 <6>[ 0.862282] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10497 23:06:20.590189 <5>[ 0.868668] NFS: Registering the id_resolver key type
10498 23:06:20.593904 <5>[ 0.873972] Key type id_resolver registered
10499 23:06:20.600440 <5>[ 0.878388] Key type id_legacy registered
10500 23:06:20.606715 <6>[ 0.882664] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10501 23:06:20.613602 <6>[ 0.889585] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10502 23:06:20.620326 <6>[ 0.897291] 9p: Installing v9fs 9p2000 file system support
10503 23:06:20.656685 <5>[ 0.935503] Key type asymmetric registered
10504 23:06:20.660432 <5>[ 0.939834] Asymmetric key parser 'x509' registered
10505 23:06:20.669861 <6>[ 0.945022] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10506 23:06:20.673744 <6>[ 0.952647] io scheduler mq-deadline registered
10507 23:06:20.676740 <6>[ 0.957414] io scheduler kyber registered
10508 23:06:20.695648 <6>[ 0.974332] EINJ: ACPI disabled.
10509 23:06:20.727761 <4>[ 0.999715] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10510 23:06:20.737775 <4>[ 1.010338] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10511 23:06:20.752825 <6>[ 1.031101] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10512 23:06:20.760483 <6>[ 1.039209] printk: console [ttyS0] disabled
10513 23:06:20.788664 <6>[ 1.063859] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10514 23:06:20.795009 <6>[ 1.073334] printk: console [ttyS0] enabled
10515 23:06:20.798269 <6>[ 1.073334] printk: console [ttyS0] enabled
10516 23:06:20.805113 <6>[ 1.082228] printk: bootconsole [mtk8250] disabled
10517 23:06:20.808478 <6>[ 1.082228] printk: bootconsole [mtk8250] disabled
10518 23:06:20.815292 <6>[ 1.093513] SuperH (H)SCI(F) driver initialized
10519 23:06:20.818237 <6>[ 1.098804] msm_serial: driver initialized
10520 23:06:20.832031 <6>[ 1.107767] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10521 23:06:20.842060 <6>[ 1.116313] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10522 23:06:20.849103 <6>[ 1.124854] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10523 23:06:20.859127 <6>[ 1.133482] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10524 23:06:20.869118 <6>[ 1.142189] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10525 23:06:20.875878 <6>[ 1.150910] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10526 23:06:20.885493 <6>[ 1.159453] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10527 23:06:20.891841 <6>[ 1.168259] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10528 23:06:20.901968 <6>[ 1.176805] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10529 23:06:20.913515 <6>[ 1.192345] loop: module loaded
10530 23:06:20.920504 <6>[ 1.198314] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10531 23:06:20.943264 <4>[ 1.221798] mtk-pmic-keys: Failed to locate of_node [id: -1]
10532 23:06:20.949980 <6>[ 1.228992] megasas: 07.719.03.00-rc1
10533 23:06:20.960112 <6>[ 1.238680] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10534 23:06:20.967349 <6>[ 1.246100] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10535 23:06:20.984815 <6>[ 1.262915] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10536 23:06:21.041742 <6>[ 1.313246] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10537 23:06:21.244445 <6>[ 1.523532] Freeing initrd memory: 17372K
10538 23:06:21.254851 <6>[ 1.533707] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10539 23:06:21.265979 <6>[ 1.544487] tun: Universal TUN/TAP device driver, 1.6
10540 23:06:21.269235 <6>[ 1.550540] thunder_xcv, ver 1.0
10541 23:06:21.272362 <6>[ 1.554062] thunder_bgx, ver 1.0
10542 23:06:21.275559 <6>[ 1.557558] nicpf, ver 1.0
10543 23:06:21.286502 <6>[ 1.561552] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10544 23:06:21.289366 <6>[ 1.569028] hns3: Copyright (c) 2017 Huawei Corporation.
10545 23:06:21.296381 <6>[ 1.574612] hclge is initializing
10546 23:06:21.299644 <6>[ 1.578185] e1000: Intel(R) PRO/1000 Network Driver
10547 23:06:21.306411 <6>[ 1.583315] e1000: Copyright (c) 1999-2006 Intel Corporation.
10548 23:06:21.309469 <6>[ 1.589326] e1000e: Intel(R) PRO/1000 Network Driver
10549 23:06:21.316096 <6>[ 1.594541] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10550 23:06:21.323162 <6>[ 1.600725] igb: Intel(R) Gigabit Ethernet Network Driver
10551 23:06:21.329504 <6>[ 1.606374] igb: Copyright (c) 2007-2014 Intel Corporation.
10552 23:06:21.336540 <6>[ 1.612211] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10553 23:06:21.339609 <6>[ 1.618730] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10554 23:06:21.346667 <6>[ 1.625194] sky2: driver version 1.30
10555 23:06:21.353089 <6>[ 1.630173] VFIO - User Level meta-driver version: 0.3
10556 23:06:21.359838 <6>[ 1.638390] usbcore: registered new interface driver usb-storage
10557 23:06:21.366602 <6>[ 1.644841] usbcore: registered new device driver onboard-usb-hub
10558 23:06:21.375486 <6>[ 1.653960] mt6397-rtc mt6359-rtc: registered as rtc0
10559 23:06:21.385354 <6>[ 1.659426] mt6397-rtc mt6359-rtc: setting system clock to 2023-12-01T23:04:10 UTC (1701471850)
10560 23:06:21.388480 <6>[ 1.668982] i2c_dev: i2c /dev entries driver
10561 23:06:21.405233 <6>[ 1.680620] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10562 23:06:21.425306 <6>[ 1.703597] cpu cpu0: EM: created perf domain
10563 23:06:21.427950 <6>[ 1.708510] cpu cpu4: EM: created perf domain
10564 23:06:21.435096 <6>[ 1.714080] sdhci: Secure Digital Host Controller Interface driver
10565 23:06:21.442013 <6>[ 1.720511] sdhci: Copyright(c) Pierre Ossman
10566 23:06:21.449040 <6>[ 1.725456] Synopsys Designware Multimedia Card Interface Driver
10567 23:06:21.455144 <6>[ 1.732091] sdhci-pltfm: SDHCI platform and OF driver helper
10568 23:06:21.458688 <6>[ 1.732146] mmc0: CQHCI version 5.10
10569 23:06:21.465381 <6>[ 1.742164] ledtrig-cpu: registered to indicate activity on CPUs
10570 23:06:21.472594 <6>[ 1.749189] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10571 23:06:21.478674 <6>[ 1.756258] usbcore: registered new interface driver usbhid
10572 23:06:21.482538 <6>[ 1.762080] usbhid: USB HID core driver
10573 23:06:21.488488 <6>[ 1.766281] spi_master spi0: will run message pump with realtime priority
10574 23:06:21.539031 <6>[ 1.811378] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10575 23:06:21.556004 <6>[ 1.827647] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10576 23:06:21.563119 <6>[ 1.841173] mmc0: Command Queue Engine enabled
10577 23:06:21.570107 <6>[ 1.845911] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10578 23:06:21.573012 <6>[ 1.853460] mmcblk0: mmc0:0001 DA4128 116 GiB
10579 23:06:21.579357 <6>[ 1.854564] cros-ec-spi spi0.0: Chrome EC device registered
10580 23:06:21.586301 <6>[ 1.862365] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10581 23:06:21.593118 <6>[ 1.870927] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10582 23:06:21.599892 <6>[ 1.876995] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10583 23:06:21.606297 <6>[ 1.877996] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10584 23:06:21.613196 <6>[ 1.882920] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10585 23:06:21.619548 <6>[ 1.892638] NET: Registered PF_PACKET protocol family
10586 23:06:21.622889 <6>[ 1.903457] 9pnet: Installing 9P2000 support
10587 23:06:21.629773 <5>[ 1.908025] Key type dns_resolver registered
10588 23:06:21.633003 <6>[ 1.913159] registered taskstats version 1
10589 23:06:21.639672 <5>[ 1.917562] Loading compiled-in X.509 certificates
10590 23:06:21.668966 <4>[ 1.941025] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10591 23:06:21.679471 <4>[ 1.951753] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10592 23:06:21.686120 <3>[ 1.962346] debugfs: File 'uA_load' in directory '/' already present!
10593 23:06:21.692432 <3>[ 1.969048] debugfs: File 'min_uV' in directory '/' already present!
10594 23:06:21.699349 <3>[ 1.975656] debugfs: File 'max_uV' in directory '/' already present!
10595 23:06:21.705934 <3>[ 1.982263] debugfs: File 'constraint_flags' in directory '/' already present!
10596 23:06:21.716884 <3>[ 1.991903] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10597 23:06:21.725412 <6>[ 2.004093] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10598 23:06:21.732294 <6>[ 2.011044] xhci-mtk 11200000.usb: xHCI Host Controller
10599 23:06:21.739075 <6>[ 2.016544] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10600 23:06:21.749098 <6>[ 2.024404] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10601 23:06:21.756065 <6>[ 2.033824] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10602 23:06:21.762212 <6>[ 2.039898] xhci-mtk 11200000.usb: xHCI Host Controller
10603 23:06:21.768716 <6>[ 2.045373] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10604 23:06:21.775450 <6>[ 2.053021] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10605 23:06:21.782904 <6>[ 2.060687] hub 1-0:1.0: USB hub found
10606 23:06:21.785569 <6>[ 2.064697] hub 1-0:1.0: 1 port detected
10607 23:06:21.792480 <6>[ 2.068960] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10608 23:06:21.798843 <6>[ 2.077508] hub 2-0:1.0: USB hub found
10609 23:06:21.802012 <6>[ 2.081511] hub 2-0:1.0: 1 port detected
10610 23:06:21.811211 <6>[ 2.089566] mtk-msdc 11f70000.mmc: Got CD GPIO
10611 23:06:21.822906 <6>[ 2.097714] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10612 23:06:21.829516 <6>[ 2.105740] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10613 23:06:21.839726 <4>[ 2.113658] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10614 23:06:21.849491 <6>[ 2.123186] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10615 23:06:21.855901 <6>[ 2.131270] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10616 23:06:21.862995 <6>[ 2.139301] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10617 23:06:21.872654 <6>[ 2.147213] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10618 23:06:21.879101 <6>[ 2.155036] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10619 23:06:21.889189 <6>[ 2.162861] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10620 23:06:21.899620 <6>[ 2.173205] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10621 23:06:21.906012 <6>[ 2.181564] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10622 23:06:21.916151 <6>[ 2.189902] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10623 23:06:21.922644 <6>[ 2.198241] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10624 23:06:21.932883 <6>[ 2.206579] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10625 23:06:21.939443 <6>[ 2.214917] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10626 23:06:21.949273 <6>[ 2.223256] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10627 23:06:21.956052 <6>[ 2.231594] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10628 23:06:21.965960 <6>[ 2.239948] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10629 23:06:21.972519 <6>[ 2.248288] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10630 23:06:21.983062 <6>[ 2.256635] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10631 23:06:21.989223 <6>[ 2.264973] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10632 23:06:21.999336 <6>[ 2.273314] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10633 23:06:22.006053 <6>[ 2.281653] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10634 23:06:22.016181 <6>[ 2.289992] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10635 23:06:22.022318 <6>[ 2.298745] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10636 23:06:22.029036 <6>[ 2.305884] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10637 23:06:22.036160 <6>[ 2.312662] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10638 23:06:22.042575 <6>[ 2.319424] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10639 23:06:22.049067 <6>[ 2.326360] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10640 23:06:22.059357 <6>[ 2.333198] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10641 23:06:22.069123 <6>[ 2.342323] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10642 23:06:22.075700 <6>[ 2.351442] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10643 23:06:22.085444 <6>[ 2.360737] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10644 23:06:22.095548 <6>[ 2.370209] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10645 23:06:22.105462 <6>[ 2.379677] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10646 23:06:22.115492 <6>[ 2.388798] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10647 23:06:22.125262 <6>[ 2.398265] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10648 23:06:22.132016 <6>[ 2.407383] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10649 23:06:22.141705 <6>[ 2.416677] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10650 23:06:22.155203 <6>[ 2.426837] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10651 23:06:22.164738 <6>[ 2.438753] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10652 23:06:22.171617 <6>[ 2.448444] Trying to probe devices needed for running init ...
10653 23:06:22.191807 <6>[ 2.467247] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10654 23:06:22.220352 <6>[ 2.498855] hub 2-1:1.0: USB hub found
10655 23:06:22.223360 <6>[ 2.503412] hub 2-1:1.0: 3 ports detected
10656 23:06:22.232456 <6>[ 2.510743] hub 2-1:1.0: USB hub found
10657 23:06:22.235475 <6>[ 2.515095] hub 2-1:1.0: 3 ports detected
10658 23:06:22.343400 <6>[ 2.618996] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10659 23:06:22.498747 <6>[ 2.777144] hub 1-1:1.0: USB hub found
10660 23:06:22.501920 <6>[ 2.781580] hub 1-1:1.0: 4 ports detected
10661 23:06:22.511211 <6>[ 2.789512] hub 1-1:1.0: USB hub found
10662 23:06:22.514269 <6>[ 2.793825] hub 1-1:1.0: 4 ports detected
10663 23:06:22.584086 <6>[ 2.859198] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10664 23:06:22.835266 <6>[ 3.111010] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10665 23:06:22.968073 <6>[ 3.246898] hub 1-1.4:1.0: USB hub found
10666 23:06:22.971303 <6>[ 3.251554] hub 1-1.4:1.0: 2 ports detected
10667 23:06:22.981025 <6>[ 3.260167] hub 1-1.4:1.0: USB hub found
10668 23:06:22.984990 <6>[ 3.264791] hub 1-1.4:1.0: 2 ports detected
10669 23:06:23.283807 <6>[ 3.558999] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10670 23:06:23.475496 <6>[ 3.750997] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10671 23:06:34.453038 <6>[ 14.736063] ALSA device list:
10672 23:06:34.459315 <6>[ 14.739358] No soundcards found.
10673 23:06:34.467499 <6>[ 14.747438] Freeing unused kernel memory: 8448K
10674 23:06:34.470937 <6>[ 14.752474] Run /init as init process
10675 23:06:34.482651 Loading, please wait...
10676 23:06:34.502453 Starting version 247.3-7+deb11u2
10677 23:06:34.723510 <6>[ 15.000165] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10678 23:06:34.739570 <6>[ 15.016344] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10679 23:06:34.743320 <6>[ 15.018793] remoteproc remoteproc0: scp is available
10680 23:06:34.753087 <6>[ 15.024133] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10681 23:06:34.756186 <6>[ 15.029764] remoteproc remoteproc0: powering up scp
10682 23:06:34.766206 <6>[ 15.037938] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10683 23:06:34.776379 <6>[ 15.043054] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10684 23:06:34.779201 <6>[ 15.043093] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10685 23:06:34.786394 <6>[ 15.047563] mc: Linux media interface: v0.10
10686 23:06:34.803319 <3>[ 15.080035] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10687 23:06:34.810139 <6>[ 15.081333] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10688 23:06:34.819846 <3>[ 15.088336] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10689 23:06:34.823072 <6>[ 15.097450] videodev: Linux video capture interface: v2.00
10690 23:06:34.833384 <3>[ 15.103983] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10691 23:06:34.839742 <4>[ 15.109625] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10692 23:06:34.846630 <4>[ 15.110019] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10693 23:06:34.853002 <6>[ 15.110430] usbcore: registered new interface driver r8152
10694 23:06:34.859479 <3>[ 15.117888] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10695 23:06:34.870231 <4>[ 15.128222] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10696 23:06:34.873649 <4>[ 15.128222] Fallback method does not support PEC.
10697 23:06:34.883785 <3>[ 15.132417] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10698 23:06:34.893543 <3>[ 15.155330] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10699 23:06:34.900456 <3>[ 15.159868] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10700 23:06:34.906424 <3>[ 15.159877] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10701 23:06:34.916636 <3>[ 15.159880] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10702 23:06:34.923056 <3>[ 15.159913] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10703 23:06:34.933711 <6>[ 15.168315] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10704 23:06:34.940318 <6>[ 15.168319] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10705 23:06:34.950456 <6>[ 15.171213] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10706 23:06:34.959989 <6>[ 15.171535] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10707 23:06:34.966486 <3>[ 15.176768] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10708 23:06:34.973090 <6>[ 15.181378] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10709 23:06:34.979991 <6>[ 15.181388] pci_bus 0000:00: root bus resource [bus 00-ff]
10710 23:06:34.986367 <6>[ 15.181397] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10711 23:06:34.996860 <6>[ 15.181403] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10712 23:06:35.002967 <6>[ 15.181442] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10713 23:06:35.010399 <6>[ 15.181466] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10714 23:06:35.013200 <6>[ 15.181552] pci 0000:00:00.0: supports D1 D2
10715 23:06:35.023235 <6>[ 15.181556] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10716 23:06:35.029821 <6>[ 15.183209] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10717 23:06:35.036175 <6>[ 15.183312] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10718 23:06:35.042960 <6>[ 15.183344] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10719 23:06:35.049833 <6>[ 15.183363] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10720 23:06:35.059514 <6>[ 15.183382] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10721 23:06:35.062756 <6>[ 15.183494] pci 0000:01:00.0: supports D1 D2
10722 23:06:35.069705 <6>[ 15.183497] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10723 23:06:35.075989 <6>[ 15.184832] remoteproc remoteproc0: remote processor scp is now up
10724 23:06:35.082730 <6>[ 15.186038] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10725 23:06:35.093393 <6>[ 15.187898] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10726 23:06:35.099919 <3>[ 15.192907] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10727 23:06:35.109689 <3>[ 15.192910] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10728 23:06:35.116528 <3>[ 15.192932] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10729 23:06:35.123524 <6>[ 15.194863] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10730 23:06:35.133059 <6>[ 15.194903] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10731 23:06:35.140069 <6>[ 15.194910] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10732 23:06:35.149536 <6>[ 15.194922] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10733 23:06:35.156144 <6>[ 15.194938] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10734 23:06:35.162500 <6>[ 15.194954] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10735 23:06:35.169721 <6>[ 15.194970] pci 0000:00:00.0: PCI bridge to [bus 01]
10736 23:06:35.176324 <6>[ 15.194979] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10737 23:06:35.185742 <6>[ 15.194992] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10738 23:06:35.192289 <6>[ 15.195174] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10739 23:06:35.195780 <6>[ 15.196054] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10740 23:06:35.202302 <6>[ 15.196560] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10741 23:06:35.212767 <4>[ 15.213620] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10742 23:06:35.218951 <3>[ 15.217577] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10743 23:06:35.229489 <3>[ 15.217580] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10744 23:06:35.236000 <3>[ 15.217583] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10745 23:06:35.245407 <3>[ 15.217586] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10746 23:06:35.252436 <3>[ 15.220308] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10747 23:06:35.262216 <4>[ 15.224636] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10748 23:06:35.269119 <3>[ 15.234709] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10749 23:06:35.278795 <6>[ 15.237866] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10750 23:06:35.285272 <6>[ 15.265330] usbcore: registered new interface driver cdc_ether
10751 23:06:35.288404 <6>[ 15.283019] Bluetooth: Core ver 2.22
10752 23:06:35.294913 <5>[ 15.284812] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10753 23:06:35.301939 <6>[ 15.295601] usbcore: registered new interface driver r8153_ecm
10754 23:06:35.308241 <5>[ 15.298007] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10755 23:06:35.318585 <4>[ 15.298082] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10756 23:06:35.321692 <6>[ 15.298090] cfg80211: failed to load regulatory.db
10757 23:06:35.328448 <6>[ 15.299892] NET: Registered PF_BLUETOOTH protocol family
10758 23:06:35.335091 <6>[ 15.300978] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10759 23:06:35.348713 <6>[ 15.302288] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10760 23:06:35.355218 <6>[ 15.302375] usbcore: registered new interface driver uvcvideo
10761 23:06:35.362202 <6>[ 15.321861] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10762 23:06:35.368362 <6>[ 15.328800] Bluetooth: HCI device and connection manager initialized
10763 23:06:35.371776 <6>[ 15.328860] r8152 2-1.3:1.0 eth0: v1.12.13
10764 23:06:35.378233 <6>[ 15.334518] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
10765 23:06:35.384747 <6>[ 15.381781] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10766 23:06:35.390854 <6>[ 15.386125] Bluetooth: HCI socket layer initialized
10767 23:06:35.397868 <6>[ 15.394269] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10768 23:06:35.400809 <6>[ 15.402270] Bluetooth: L2CAP socket layer initialized
10769 23:06:35.407568 <6>[ 15.426883] mt7921e 0000:01:00.0: ASIC revision: 79610010
10770 23:06:35.410670 <6>[ 15.433186] Bluetooth: SCO socket layer initialized
10771 23:06:35.424109 <4>[ 15.541576] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10772 23:06:35.430290 <6>[ 15.608433] usbcore: registered new interface driver btusb
10773 23:06:35.440134 <4>[ 15.609508] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10774 23:06:35.447002 <3>[ 15.609526] Bluetooth: hci0: Failed to load firmware file (-2)
10775 23:06:35.450108 <3>[ 15.609533] Bluetooth: hci0: Failed to set up firmware (-2)
10776 23:06:35.463808 <4>[ 15.609540] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10777 23:06:35.473648 <4>[ 15.716477] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10778 23:06:35.476636 Begin: Loading essential drivers ... done.
10779 23:06:35.483571 Begin: Running /scripts/init-premount ... done.
10780 23:06:35.490642 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10781 23:06:35.496923 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10782 23:06:35.500440 Device /sys/class/net/enx00e04c787aaa found
10783 23:06:35.503297 done.
10784 23:06:35.554611 IP-Config: enx00e04c787aaa hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10785 23:06:35.595130 <4>[ 15.869123] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10786 23:06:35.710457 <4>[ 15.984115] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10787 23:06:35.826016 <4>[ 16.099906] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10788 23:06:35.942556 <4>[ 16.215845] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10789 23:06:36.058219 <4>[ 16.331772] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10790 23:06:36.174552 <4>[ 16.447856] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10791 23:06:36.290735 <4>[ 16.563786] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10792 23:06:36.406053 <4>[ 16.679780] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10793 23:06:36.513770 <3>[ 16.793686] mt7921e 0000:01:00.0: hardware init failed
10794 23:06:36.681675 <6>[ 16.962219] r8152 2-1.3:1.0 enx00e04c787aaa: carrier on
10795 23:06:36.878930 IP-Config: no response after 2 secs - giving up
10796 23:06:36.921784 IP-Config: enx00e04c787aaa hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10797 23:06:36.925323 IP-Config: enx00e04c787aaa complete (dhcp from 192.168.201.1):
10798 23:06:36.931819 address: 192.168.201.12 broadcast: 192.168.201.255 netmask: 255.255.255.0
10799 23:06:36.938646 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10800 23:06:36.944784 host : mt8192-asurada-spherion-r0-cbg-0
10801 23:06:36.951602 domain : lava-rack
10802 23:06:36.958006 rootserver: 192.168.201.1 rootpath:
10803 23:06:36.958098 filename :
10804 23:06:37.042401 done.
10805 23:06:37.045269 Begin: Running /scripts/nfs-bottom ... done.
10806 23:06:37.069732 Begin: Running /scripts/init-bottom ... done.
10807 23:06:38.273752 <6>[ 18.554088] NET: Registered PF_INET6 protocol family
10808 23:06:38.280732 <6>[ 18.560851] Segment Routing with IPv6
10809 23:06:38.284211 <6>[ 18.564825] In-situ OAM (IOAM) with IPv6
10810 23:06:38.396787 <30>[ 18.660529] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10811 23:06:38.404536 <30>[ 18.685085] systemd[1]: Detected architecture arm64.
10812 23:06:38.423494
10813 23:06:38.426873 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10814 23:06:38.426949
10815 23:06:38.444312 <30>[ 18.725219] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10816 23:06:39.361209 <30>[ 19.638420] systemd[1]: Queued start job for default target Graphical Interface.
10817 23:06:39.393340 <30>[ 19.673639] systemd[1]: Created slice system-getty.slice.
10818 23:06:39.400013 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10819 23:06:39.415975 <30>[ 19.696597] systemd[1]: Created slice system-modprobe.slice.
10820 23:06:39.423257 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10821 23:06:39.440283 <30>[ 19.720404] systemd[1]: Created slice system-serial\x2dgetty.slice.
10822 23:06:39.450392 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10823 23:06:39.463826 <30>[ 19.744202] systemd[1]: Created slice User and Session Slice.
10824 23:06:39.470121 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10825 23:06:39.490107 <30>[ 19.767351] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10826 23:06:39.500541 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10827 23:06:39.518819 <30>[ 19.795844] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10828 23:06:39.525606 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10829 23:06:39.550021 <30>[ 19.823854] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10830 23:06:39.557138 <30>[ 19.836141] systemd[1]: Reached target Local Encrypted Volumes.
10831 23:06:39.563360 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10832 23:06:39.578299 <30>[ 19.859188] systemd[1]: Reached target Paths.
10833 23:06:39.581493 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10834 23:06:39.598221 <30>[ 19.879032] systemd[1]: Reached target Remote File Systems.
10835 23:06:39.605152 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10836 23:06:39.622083 <30>[ 19.902985] systemd[1]: Reached target Slices.
10837 23:06:39.628876 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10838 23:06:39.642728 <30>[ 19.923028] systemd[1]: Reached target Swap.
10839 23:06:39.645636 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10840 23:06:39.666137 <30>[ 19.943501] systemd[1]: Listening on initctl Compatibility Named Pipe.
10841 23:06:39.672922 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10842 23:06:39.679377 <30>[ 19.959776] systemd[1]: Listening on Journal Audit Socket.
10843 23:06:39.685956 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10844 23:06:39.703582 <30>[ 19.984345] systemd[1]: Listening on Journal Socket (/dev/log).
10845 23:06:39.710302 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10846 23:06:39.727273 <30>[ 20.007667] systemd[1]: Listening on Journal Socket.
10847 23:06:39.733665 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10848 23:06:39.747496 <30>[ 20.028470] systemd[1]: Listening on Network Service Netlink Socket.
10849 23:06:39.758039 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10850 23:06:39.772639 <30>[ 20.053638] systemd[1]: Listening on udev Control Socket.
10851 23:06:39.779890 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10852 23:06:39.794741 <30>[ 20.075581] systemd[1]: Listening on udev Kernel Socket.
10853 23:06:39.801479 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10854 23:06:39.858332 <30>[ 20.139187] systemd[1]: Mounting Huge Pages File System...
10855 23:06:39.865368 Mounting [0;1;39mHuge Pages File System[0m...
10856 23:06:39.883148 <30>[ 20.163842] systemd[1]: Mounting POSIX Message Queue File System...
10857 23:06:39.890168 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10858 23:06:39.911686 <30>[ 20.192213] systemd[1]: Mounting Kernel Debug File System...
10859 23:06:39.917993 Mounting [0;1;39mKernel Debug File System[0m...
10860 23:06:39.938300 <30>[ 20.215585] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10861 23:06:39.956319 <30>[ 20.233505] systemd[1]: Starting Create list of static device nodes for the current kernel...
10862 23:06:39.962467 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10863 23:06:39.981468 <30>[ 20.262263] systemd[1]: Starting Load Kernel Module configfs...
10864 23:06:39.988148 Starting [0;1;39mLoad Kernel Module configfs[0m...
10865 23:06:40.007583 <30>[ 20.288448] systemd[1]: Starting Load Kernel Module drm...
10866 23:06:40.014282 Starting [0;1;39mLoad Kernel Module drm[0m...
10867 23:06:40.035553 <30>[ 20.316599] systemd[1]: Starting Load Kernel Module fuse...
10868 23:06:40.042147 Starting [0;1;39mLoad Kernel Module fuse[0m...
10869 23:06:40.075451 <6>[ 20.356230] fuse: init (API version 7.37)
10870 23:06:40.085407 <30>[ 20.357692] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10871 23:06:40.115138 <30>[ 20.396009] systemd[1]: Starting Journal Service...
10872 23:06:40.121585 Starting [0;1;39mJournal Service[0m...
10873 23:06:40.145458 <30>[ 20.426217] systemd[1]: Starting Load Kernel Modules...
10874 23:06:40.152146 Starting [0;1;39mLoad Kernel Modules[0m...
10875 23:06:40.176893 <30>[ 20.454468] systemd[1]: Starting Remount Root and Kernel File Systems...
10876 23:06:40.183713 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10877 23:06:40.227362 <30>[ 20.508040] systemd[1]: Starting Coldplug All udev Devices...
10878 23:06:40.241416 Starting [0;1;39mColdplug All udev Dev<3>[ 20.518348] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10879 23:06:40.241564 ices[0m...
10880 23:06:40.262173 <30>[ 20.542521] systemd[1]: Mounted Huge Pages File System.
10881 23:06:40.275846 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages <3>[ 20.552239] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10882 23:06:40.275944 File System[0m.
10883 23:06:40.290345 <30>[ 20.571401] systemd[1]: Mounted POSIX Message Queue File System.
10884 23:06:40.297170 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10885 23:06:40.309532 <3>[ 20.587002] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10886 23:06:40.316183 <30>[ 20.596248] systemd[1]: Mounted Kernel Debug File System.
10887 23:06:40.322926 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10888 23:06:40.340897 <3>[ 20.618300] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10889 23:06:40.354433 <30>[ 20.631889] systemd[1]: Finished Create list of static device nodes for the current kernel.
10890 23:06:40.364791 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10891 23:06:40.371689 <3>[ 20.648216] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10892 23:06:40.379120 <30>[ 20.660242] systemd[1]: modprobe@configfs.service: Succeeded.
10893 23:06:40.386729 <30>[ 20.667157] systemd[1]: Finished Load Kernel Module configfs.
10894 23:06:40.393094 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10895 23:06:40.404628 <3>[ 20.682257] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10896 23:06:40.415879 <30>[ 20.696733] systemd[1]: modprobe@drm.service: Succeeded.
10897 23:06:40.423088 <30>[ 20.703656] systemd[1]: Finished Load Kernel Module drm.
10898 23:06:40.436921 [[0;32m OK [0m] Finished [0;1;39mLoad Kerne<3>[ 20.712715] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10899 23:06:40.440260 l Module drm[0m.
10900 23:06:40.455627 <30>[ 20.736558] systemd[1]: modprobe@fuse.service: Succeeded.
10901 23:06:40.463063 <30>[ 20.743869] systemd[1]: Finished Load Kernel Module fuse.
10902 23:06:40.473692 <3>[ 20.746579] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10903 23:06:40.479726 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10904 23:06:40.496877 <30>[ 20.777182] systemd[1]: Finished Load Kernel Modules.
10905 23:06:40.507266 <3>[ 20.782842] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10906 23:06:40.510108 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10907 23:06:40.529837 <30>[ 20.809229] systemd[1]: Finished Remount Root and Kernel File Systems.
10908 23:06:40.539298 <3>[ 20.813696] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10909 23:06:40.545837 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10910 23:06:40.597560 <30>[ 20.878564] systemd[1]: Mounting FUSE Control File System...
10911 23:06:40.604787 Mounting [0;1;39mFUSE Control File System[0m...
10912 23:06:40.625555 <30>[ 20.906560] systemd[1]: Mounting Kernel Configuration File System...
10913 23:06:40.632838 Mounting [0;1;39mKernel Configuration File System[0m...
10914 23:06:40.662099 <30>[ 20.939972] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10915 23:06:40.672497 <30>[ 20.949212] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10916 23:06:40.718944 <30>[ 20.999847] systemd[1]: Starting Load/Save Random Seed...
10917 23:06:40.725750 Starting [0;1;39mLoad/Save Random Seed[0m...
10918 23:06:40.741485 <30>[ 21.022262] systemd[1]: Starting Apply Kernel Variables...
10919 23:06:40.758205 <4>[ 21.023733] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10920 23:06:40.764828 <3>[ 21.044058] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10921 23:06:40.771404 Starting [0;1;39mApply Kernel Variables[0m...
10922 23:06:40.830624 <30>[ 21.111812] systemd[1]: Starting Create System Users...
10923 23:06:40.837694 Starting [0;1;39mCreate System Users[0m...
10924 23:06:40.856892 <30>[ 21.137245] systemd[1]: Started Journal Service.
10925 23:06:40.862820 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10926 23:06:40.880649 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10927 23:06:40.894296 See 'systemctl status systemd-udev-trigger.service' for details.
10928 23:06:40.911338 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10929 23:06:40.927267 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10930 23:06:40.945043 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10931 23:06:40.964396 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10932 23:06:40.984438 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10933 23:06:41.015114 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10934 23:06:41.033393 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10935 23:06:41.069433 <46>[ 21.346923] systemd-journald[300]: Received client request to flush runtime journal.
10936 23:06:41.830034 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10937 23:06:41.842549 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10938 23:06:41.858144 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10939 23:06:41.915083 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10940 23:06:42.487077 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10941 23:06:42.522957 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10942 23:06:42.561543 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10943 23:06:42.621456 Starting [0;1;39mNetwork Service[0m...
10944 23:06:42.781475 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10945 23:06:42.944045 Starting [0;1;39mNetwork Time Synchronization[0m...
10946 23:06:42.960853 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10947 23:06:43.086971 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10948 23:06:43.317974 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10949 23:06:43.330494 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10950 23:06:43.349406 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10951 23:06:43.398038 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10952 23:06:43.415250 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10953 23:06:43.439277 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10954 23:06:43.527302 Starting [0;1;39mNetwork Name Resolution[0m...
10955 23:06:43.549483 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10956 23:06:43.570771 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10957 23:06:43.593698 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10958 23:06:43.607578 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10959 23:06:43.622900 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10960 23:06:43.641375 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10961 23:06:43.653981 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10962 23:06:43.670070 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10963 23:06:44.349304 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10964 23:06:44.685610 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10965 23:06:44.714524 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10966 23:06:44.747275 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10967 23:06:44.761906 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10968 23:06:44.783671 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10969 23:06:44.798416 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10970 23:06:44.817945 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10971 23:06:44.883007 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10972 23:06:45.026505 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10973 23:06:45.172320 Starting [0;1;39mUser Login Management[0m...
10974 23:06:45.428266 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10975 23:06:45.436291 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10976 23:06:45.453004 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10977 23:06:45.502971 Starting [0;1;39mPermit User Sessions[0m...
10978 23:06:45.525836 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10979 23:06:45.545362 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10980 23:06:45.591032 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10981 23:06:45.642962 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10982 23:06:45.658303 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10983 23:06:45.674867 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10984 23:06:45.691725 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10985 23:06:45.705509 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10986 23:06:45.754323 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10987 23:06:45.811079 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10988 23:06:45.891396
10989 23:06:45.891659
10990 23:06:45.894098 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10991 23:06:45.894283
10992 23:06:45.897641 debian-bullseye-arm64 login: root (automatic login)
10993 23:06:45.897799
10994 23:06:45.897919
10995 23:06:46.272837 Linux debian-bullseye-arm64 6.1.64-cip10 #1 SMP PREEMPT Fri Dec 1 22:47:09 UTC 2023 aarch64
10996 23:06:46.273337
10997 23:06:46.279280 The programs included with the Debian GNU/Linux system are free software;
10998 23:06:46.285667 the exact distribution terms for each program are described in the
10999 23:06:46.288781 individual files in /usr/share/doc/*/copyright.
11000 23:06:46.289195
11001 23:06:46.295569 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11002 23:06:46.299095 permitted by applicable law.
11003 23:06:47.215256 Matched prompt #10: / #
11005 23:06:47.215557 Setting prompt string to ['/ #']
11006 23:06:47.215656 end: 2.2.5.1 login-action (duration 00:00:28) [common]
11008 23:06:47.215863 end: 2.2.5 auto-login-action (duration 00:00:28) [common]
11009 23:06:47.215957 start: 2.2.6 expect-shell-connection (timeout 00:03:34) [common]
11010 23:06:47.216029 Setting prompt string to ['/ #']
11011 23:06:47.216093 Forcing a shell prompt, looking for ['/ #']
11013 23:06:47.266410 / #
11014 23:06:47.266879 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11015 23:06:47.267196 Waiting using forced prompt support (timeout 00:02:30)
11016 23:06:47.273306
11017 23:06:47.274178 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11018 23:06:47.274663 start: 2.2.7 export-device-env (timeout 00:03:34) [common]
11020 23:06:47.376057 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12154385/extract-nfsrootfs-p6jmt7b4'
11021 23:06:47.382629 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12154385/extract-nfsrootfs-p6jmt7b4'
11023 23:06:47.484134 / # export NFS_SERVER_IP='192.168.201.1'
11024 23:06:47.489740 export NFS_SERVER_IP='192.168.201.1'
11025 23:06:47.490315 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11026 23:06:47.490624 end: 2.2 depthcharge-retry (duration 00:01:26) [common]
11027 23:06:47.490886 end: 2 depthcharge-action (duration 00:01:26) [common]
11028 23:06:47.491144 start: 3 lava-test-retry (timeout 00:07:48) [common]
11029 23:06:47.491387 start: 3.1 lava-test-shell (timeout 00:07:48) [common]
11030 23:06:47.491599 Using namespace: common
11032 23:06:47.592480 / # #
11033 23:06:47.593155 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11034 23:06:47.599090 #
11035 23:06:47.599979 Using /lava-12154385
11037 23:06:47.701394 / # export SHELL=/bin/bash
11038 23:06:47.707780 export SHELL=/bin/bash
11040 23:06:47.809631 / # . /lava-12154385/environment
11041 23:06:47.816180 . /lava-12154385/environment
11043 23:06:47.924336 / # /lava-12154385/bin/lava-test-runner /lava-12154385/0
11044 23:06:47.925103 Test shell timeout: 10s (minimum of the action and connection timeout)
11045 23:06:47.931377 /lava-12154385/bin/lava-test-runner /lava-12154385/0
11046 23:06:48.229438 + export TESTRUN_ID=0_timesync-off
11047 23:06:48.232413 + TESTRUN_ID=0_timesync-off
11048 23:06:48.235330 + cd /lava-12154385/0/tests/0_timesync-off
11049 23:06:48.238970 ++ cat uuid
11050 23:06:48.244135 + UUID=12154385_1.6.2.3.1
11051 23:06:48.244362 + set +x
11052 23:06:48.250715 <LAVA_SIGNAL_STARTRUN 0_timesync-off 12154385_1.6.2.3.1>
11053 23:06:48.251098 Received signal: <STARTRUN> 0_timesync-off 12154385_1.6.2.3.1
11054 23:06:48.251267 Starting test lava.0_timesync-off (12154385_1.6.2.3.1)
11055 23:06:48.251421 Skipping test definition patterns.
11056 23:06:48.253710 + systemctl stop systemd-timesyncd
11057 23:06:48.321085 + set +x
11058 23:06:48.324120 <LAVA_SIGNAL_ENDRUN 0_timesync-off 12154385_1.6.2.3.1>
11059 23:06:48.324801 Received signal: <ENDRUN> 0_timesync-off 12154385_1.6.2.3.1
11060 23:06:48.325199 Ending use of test pattern.
11061 23:06:48.325517 Ending test lava.0_timesync-off (12154385_1.6.2.3.1), duration 0.07
11063 23:06:48.403536 + export TESTRUN_ID=1_kselftest-arm64
11064 23:06:48.404045 + TESTRUN_ID=1_kselftest-arm64
11065 23:06:48.410652 + cd /lava-12154385/0/tests/1_kselftest-arm64
11066 23:06:48.411101 ++ cat uuid
11067 23:06:48.414205 + UUID=12154385_1.6.2.3.5
11068 23:06:48.414643 + set +x
11069 23:06:48.420599 <LAVA_SIGNAL_STARTRUN 1_kselftest-arm64 12154385_1.6.2.3.5>
11070 23:06:48.421302 Received signal: <STARTRUN> 1_kselftest-arm64 12154385_1.6.2.3.5
11071 23:06:48.421764 Starting test lava.1_kselftest-arm64 (12154385_1.6.2.3.5)
11072 23:06:48.422182 Skipping test definition patterns.
11073 23:06:48.423858 + cd ./automated/linux/kselftest/
11074 23:06:48.450082 + ./kselftest.sh -c arm64 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.64-cip10/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11075 23:06:48.488743 INFO: install_deps skipped
11076 23:06:48.603840 --2023-12-01 23:04:35-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.64-cip10/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11077 23:06:48.629437 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11078 23:06:48.762898 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11079 23:06:48.896587 HTTP request sent, awaiting response... 200 OK
11080 23:06:48.900198 Length: 2967588 (2.8M) [application/octet-stream]
11081 23:06:48.903133 Saving to: 'kselftest.tar.xz'
11082 23:06:48.903598
11083 23:06:48.903967
11084 23:06:49.163542 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11085 23:06:49.429475 kselftest.tar.xz 1%[ ] 49.22K 186KB/s
11086 23:06:49.745978 kselftest.tar.xz 7%[> ] 217.50K 409KB/s
11087 23:06:50.023891 kselftest.tar.xz 28%[====> ] 824.13K 973KB/s
11088 23:06:50.150377 kselftest.tar.xz 68%[============> ] 1.94M 1.72MB/s
11089 23:06:50.156856 kselftest.tar.xz 100%[===================>] 2.83M 2.26MB/s in 1.3s
11090 23:06:50.156942
11091 23:06:50.415152 2023-12-01 23:04:36 (2.26 MB/s) - 'kselftest.tar.xz' saved [2967588/2967588]
11092 23:06:50.415326
11093 23:06:55.863142 skiplist:
11094 23:06:55.866362 ========================================
11095 23:06:55.869746 ========================================
11096 23:06:55.907396 arm64:tags_test
11097 23:06:55.910868 arm64:run_tags_test.sh
11098 23:06:55.910966 arm64:fake_sigreturn_bad_magic
11099 23:06:55.914128 arm64:fake_sigreturn_bad_size
11100 23:06:55.917243 arm64:fake_sigreturn_bad_size_for_magic0
11101 23:06:55.920974 arm64:fake_sigreturn_duplicated_fpsimd
11102 23:06:55.924040 arm64:fake_sigreturn_misaligned_sp
11103 23:06:55.927035 arm64:fake_sigreturn_missing_fpsimd
11104 23:06:55.930622 arm64:fake_sigreturn_sme_change_vl
11105 23:06:55.934132 arm64:fake_sigreturn_sve_change_vl
11106 23:06:55.937137 arm64:mangle_pstate_invalid_compat_toggle
11107 23:06:55.940625 arm64:mangle_pstate_invalid_daif_bits
11108 23:06:55.943566 arm64:mangle_pstate_invalid_mode_el1h
11109 23:06:55.947507 arm64:mangle_pstate_invalid_mode_el1t
11110 23:06:55.950623 arm64:mangle_pstate_invalid_mode_el2h
11111 23:06:55.953793 arm64:mangle_pstate_invalid_mode_el2t
11112 23:06:55.957384 arm64:mangle_pstate_invalid_mode_el3h
11113 23:06:55.960365 arm64:mangle_pstate_invalid_mode_el3t
11114 23:06:55.963965 arm64:sme_trap_no_sm
11115 23:06:55.966672 arm64:sme_trap_non_streaming
11116 23:06:55.966756 arm64:sme_trap_za
11117 23:06:55.970158 arm64:sme_vl
11118 23:06:55.970239 arm64:ssve_regs
11119 23:06:55.973515 arm64:sve_regs
11120 23:06:55.973625 arm64:sve_vl
11121 23:06:55.973691 arm64:za_no_regs
11122 23:06:55.977097 arm64:za_regs
11123 23:06:55.977178 arm64:pac
11124 23:06:55.980776 arm64:fp-stress
11125 23:06:55.980857 arm64:sve-ptrace
11126 23:06:55.983786 arm64:sve-probe-vls
11127 23:06:55.983869 arm64:vec-syscfg
11128 23:06:55.983934 arm64:za-fork
11129 23:06:55.987034 arm64:za-ptrace
11130 23:06:55.989893 arm64:check_buffer_fill
11131 23:06:55.989976 arm64:check_child_memory
11132 23:06:55.993302 arm64:check_gcr_el1_cswitch
11133 23:06:55.996699 arm64:check_ksm_options
11134 23:06:55.996781 arm64:check_mmap_options
11135 23:06:55.999757 arm64:check_prctl
11136 23:06:56.003772 arm64:check_tags_inclusion
11137 23:06:56.003855 arm64:check_user_mem
11138 23:06:56.006286 arm64:btitest
11139 23:06:56.006368 arm64:nobtitest
11140 23:06:56.006432 arm64:hwcap
11141 23:06:56.010199 arm64:ptrace
11142 23:06:56.010280 arm64:syscall-abi
11143 23:06:56.013128 arm64:tpidr2
11144 23:06:56.016697 ============== Tests to run ===============
11145 23:06:56.016781 arm64:tags_test
11146 23:06:56.019998 arm64:run_tags_test.sh
11147 23:06:56.023328 arm64:fake_sigreturn_bad_magic
11148 23:06:56.023409 arm64:fake_sigreturn_bad_size
11149 23:06:56.029723 arm64:fake_sigreturn_bad_size_for_magic0
11150 23:06:56.033216 arm64:fake_sigreturn_duplicated_fpsimd
11151 23:06:56.036147 arm64:fake_sigreturn_misaligned_sp
11152 23:06:56.036230 arm64:fake_sigreturn_missing_fpsimd
11153 23:06:56.040142 arm64:fake_sigreturn_sme_change_vl
11154 23:06:56.043082 arm64:fake_sigreturn_sve_change_vl
11155 23:06:56.049358 arm64:mangle_pstate_invalid_compat_toggle
11156 23:06:56.052722 arm64:mangle_pstate_invalid_daif_bits
11157 23:06:56.056348 arm64:mangle_pstate_invalid_mode_el1h
11158 23:06:56.059401 arm64:mangle_pstate_invalid_mode_el1t
11159 23:06:56.062650 arm64:mangle_pstate_invalid_mode_el2h
11160 23:06:56.065858 arm64:mangle_pstate_invalid_mode_el2t
11161 23:06:56.069384 arm64:mangle_pstate_invalid_mode_el3h
11162 23:06:56.072929 arm64:mangle_pstate_invalid_mode_el3t
11163 23:06:56.073011 arm64:sme_trap_no_sm
11164 23:06:56.076318 arm64:sme_trap_non_streaming
11165 23:06:56.079246 arm64:sme_trap_za
11166 23:06:56.079328 arm64:sme_vl
11167 23:06:56.079393 arm64:ssve_regs
11168 23:06:56.082719 arm64:sve_regs
11169 23:06:56.082800 arm64:sve_vl
11170 23:06:56.085681 arm64:za_no_regs
11171 23:06:56.085762 arm64:za_regs
11172 23:06:56.085826 arm64:pac
11173 23:06:56.089364 arm64:fp-stress
11174 23:06:56.089446 arm64:sve-ptrace
11175 23:06:56.092264 arm64:sve-probe-vls
11176 23:06:56.092346 arm64:vec-syscfg
11177 23:06:56.095883 arm64:za-fork
11178 23:06:56.095965 arm64:za-ptrace
11179 23:06:56.099017 arm64:check_buffer_fill
11180 23:06:56.099099 arm64:check_child_memory
11181 23:06:56.102545 arm64:check_gcr_el1_cswitch
11182 23:06:56.105743 arm64:check_ksm_options
11183 23:06:56.105825 arm64:check_mmap_options
11184 23:06:56.109564 arm64:check_prctl
11185 23:06:56.112737 arm64:check_tags_inclusion
11186 23:06:56.112819 arm64:check_user_mem
11187 23:06:56.115699 arm64:btitest
11188 23:06:56.115780 arm64:nobtitest
11189 23:06:56.115844 arm64:hwcap
11190 23:06:56.119326 arm64:ptrace
11191 23:06:56.119407 arm64:syscall-abi
11192 23:06:56.122619 arm64:tpidr2
11193 23:06:56.125989 ===========End Tests to run ===============
11194 23:06:56.126075 shardfile-arm64 pass
11195 23:06:56.299937 <12>[ 36.582133] kselftest: Running tests in arm64
11196 23:06:56.307994 TAP version 13
11197 23:06:56.319946 1..48
11198 23:06:56.333834 # selftests: arm64: tags_test
11199 23:06:56.774288 ok 1 selftests: arm64: tags_test
11200 23:06:56.791506 # selftests: arm64: run_tags_test.sh
11201 23:06:56.849588 # --------------------
11202 23:06:56.852975 # running tags test
11203 23:06:56.853064 # --------------------
11204 23:06:56.856305 # [PASS]
11205 23:06:56.859308 ok 2 selftests: arm64: run_tags_test.sh
11206 23:06:56.871901 # selftests: arm64: fake_sigreturn_bad_magic
11207 23:06:56.922259 # Registered handlers for all signals.
11208 23:06:56.922389 # Detected MINSTKSIGSZ:4720
11209 23:06:56.925847 # Testcase initialized.
11210 23:06:56.929024 # uc context validated.
11211 23:06:56.932008 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11212 23:06:56.935527 # Handled SIG_COPYCTX
11213 23:06:56.935608 # Available space:3568
11214 23:06:56.942292 # Using badly built context - ERR: BAD MAGIC !
11215 23:06:56.949473 # SIG_OK -- SP:0xFFFFCA059CC0 si_addr@:0xffffca059cc0 si_code:2 token@:0xffffca058a60 offset:-4704
11216 23:06:56.952126 # ==>> completed. PASS(1)
11217 23:06:56.958680 # # FAKE_SIGRETURN_BAD_MAGIC :: Trigger a sigreturn with a sigframe with a bad magic
11218 23:06:56.965371 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFCA058A60
11219 23:06:56.968781 ok 3 selftests: arm64: fake_sigreturn_bad_magic
11220 23:06:56.975026 # selftests: arm64: fake_sigreturn_bad_size
11221 23:06:56.991718 # Registered handlers for all signals.
11222 23:06:56.991821 # Detected MINSTKSIGSZ:4720
11223 23:06:56.995497 # Testcase initialized.
11224 23:06:56.998930 # uc context validated.
11225 23:06:57.001800 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11226 23:06:57.005383 # Handled SIG_COPYCTX
11227 23:06:57.005467 # Available space:3568
11228 23:06:57.008490 # uc context validated.
11229 23:06:57.015388 # Using badly built context - ERR: Bad size for esr_context
11230 23:06:57.022188 # SIG_OK -- SP:0xFFFFEFF5CA80 si_addr@:0xffffeff5ca80 si_code:2 token@:0xffffeff5b820 offset:-4704
11231 23:06:57.024932 # ==>> completed. PASS(1)
11232 23:06:57.032032 # # FAKE_SIGRETURN_BAD_SIZE :: Triggers a sigreturn with a overrun __reserved area
11233 23:06:57.038887 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFEFF5B820
11234 23:06:57.042001 ok 4 selftests: arm64: fake_sigreturn_bad_size
11235 23:06:57.048168 # selftests: arm64: fake_sigreturn_bad_size_for_magic0
11236 23:06:57.071826 # Registered handlers for all signals.
11237 23:06:57.071923 # Detected MINSTKSIGSZ:4720
11238 23:06:57.075585 # Testcase initialized.
11239 23:06:57.078463 # uc context validated.
11240 23:06:57.081784 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11241 23:06:57.085821 # Handled SIG_COPYCTX
11242 23:06:57.085904 # Available space:3568
11243 23:06:57.091754 # Using badly built context - ERR: Bad size for terminator
11244 23:06:57.101455 # SIG_OK -- SP:0xFFFFFADAC6C0 si_addr@:0xfffffadac6c0 si_code:2 token@:0xfffffadab460 offset:-4704
11245 23:06:57.101541 # ==>> completed. PASS(1)
11246 23:06:57.111841 # # FAKE_SIGRETURN_BAD_SIZE_FOR_TERMINATOR :: Trigger a sigreturn using non-zero size terminator
11247 23:06:57.118089 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFFADAB460
11248 23:06:57.121134 ok 5 selftests: arm64: fake_sigreturn_bad_size_for_magic0
11249 23:06:57.128420 # selftests: arm64: fake_sigreturn_duplicated_fpsimd
11250 23:06:57.151391 # Registered handlers for all signals.
11251 23:06:57.151505 # Detected MINSTKSIGSZ:4720
11252 23:06:57.153975 # Testcase initialized.
11253 23:06:57.158061 # uc context validated.
11254 23:06:57.160896 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11255 23:06:57.163983 # Handled SIG_COPYCTX
11256 23:06:57.164063 # Available space:3568
11257 23:06:57.170533 # Using badly built context - ERR: Multiple FPSIMD_MAGIC
11258 23:06:57.180909 # SIG_OK -- SP:0xFFFFF485F2A0 si_addr@:0xfffff485f2a0 si_code:2 token@:0xfffff485e040 offset:-4704
11259 23:06:57.180998 # ==>> completed. PASS(1)
11260 23:06:57.190972 # # FAKE_SIGRETURN_DUPLICATED_FPSIMD :: Triggers a sigreturn including two fpsimd_context
11261 23:06:57.197558 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFF485E040
11262 23:06:57.200319 ok 6 selftests: arm64: fake_sigreturn_duplicated_fpsimd
11263 23:06:57.203747 # selftests: arm64: fake_sigreturn_misaligned_sp
11264 23:06:57.225528 # Registered handlers for all signals.
11265 23:06:57.225672 # Detected MINSTKSIGSZ:4720
11266 23:06:57.228579 # Testcase initialized.
11267 23:06:57.232131 # uc context validated.
11268 23:06:57.235542 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11269 23:06:57.238518 # Handled SIG_COPYCTX
11270 23:06:57.245490 # SIG_OK -- SP:0xFFFFD4D79063 si_addr@:0xffffd4d79063 si_code:2 token@:0xffffd4d79063 offset:0
11271 23:06:57.248614 # ==>> completed. PASS(1)
11272 23:06:57.255058 # # FAKE_SIGRETURN_MISALIGNED_SP :: Triggers a sigreturn with a misaligned sigframe
11273 23:06:57.261898 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFD4D79063
11274 23:06:57.269256 ok 7 selftests: arm64: fake_sigreturn_misaligned_sp
11275 23:06:57.271861 # selftests: arm64: fake_sigreturn_missing_fpsimd
11276 23:06:57.307222 # Registered handlers for all signals.
11277 23:06:57.307345 # Detected MINSTKSIGSZ:4720
11278 23:06:57.310858 # Testcase initialized.
11279 23:06:57.313506 # uc context validated.
11280 23:06:57.316973 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11281 23:06:57.320279 # Handled SIG_COPYCTX
11282 23:06:57.323708 # Mangling template header. Spare space:4096
11283 23:06:57.327179 # Using badly built context - ERR: Missing FPSIMD
11284 23:06:57.336499 # SIG_OK -- SP:0xFFFFE19F8180 si_addr@:0xffffe19f8180 si_code:2 token@:0xffffe19f6f20 offset:-4704
11285 23:06:57.339812 # ==>> completed. PASS(1)
11286 23:06:57.346492 # # FAKE_SIGRETURN_MISSING_FPSIMD :: Triggers a sigreturn with a missing fpsimd_context
11287 23:06:57.353161 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFE19F6F20
11288 23:06:57.356583 ok 8 selftests: arm64: fake_sigreturn_missing_fpsimd
11289 23:06:57.363359 # selftests: arm64: fake_sigreturn_sme_change_vl
11290 23:06:57.391574 # Registered handlers for all signals.
11291 23:06:57.391685 # Detected MINSTKSIGSZ:4720
11292 23:06:57.394418 # ==>> completed. SKIP.
11293 23:06:57.401433 # # FAKE_SIGRETURN_SSVE_CHANGE :: Attempt to change Streaming SVE VL
11294 23:06:57.404428 ok 9 selftests: arm64: fake_sigreturn_sme_change_vl # SKIP
11295 23:06:57.411308 # selftests: arm64: fake_sigreturn_sve_change_vl
11296 23:06:57.461470 # Registered handlers for all signals.
11297 23:06:57.461616 # Detected MINSTKSIGSZ:4720
11298 23:06:57.464986 # ==>> completed. SKIP.
11299 23:06:57.471410 # # FAKE_SIGRETURN_SVE_CHANGE :: Attempt to change SVE VL
11300 23:06:57.474958 ok 10 selftests: arm64: fake_sigreturn_sve_change_vl # SKIP
11301 23:06:57.481558 # selftests: arm64: mangle_pstate_invalid_compat_toggle
11302 23:06:57.538720 # Registered handlers for all signals.
11303 23:06:57.538868 # Detected MINSTKSIGSZ:4720
11304 23:06:57.542113 # Testcase initialized.
11305 23:06:57.545751 # uc context validated.
11306 23:06:57.545833 # Handled SIG_TRIG
11307 23:06:57.555379 # SIG_OK -- SP:0xFFFFEDEC5EC0 si_addr@:0xffffedec5ec0 si_code:2 token@:(nil) offset:-281474673434304
11308 23:06:57.558888 # ==>> completed. PASS(1)
11309 23:06:57.565337 # # MANGLE_PSTATE_INVALID_STATE_TOGGLE :: Mangling uc_mcontext with INVALID STATE_TOGGLE
11310 23:06:57.571956 ok 11 selftests: arm64: mangle_pstate_invalid_compat_toggle
11311 23:06:57.574913 # selftests: arm64: mangle_pstate_invalid_daif_bits
11312 23:06:57.604240 # Registered handlers for all signals.
11313 23:06:57.604345 # Detected MINSTKSIGSZ:4720
11314 23:06:57.607960 # Testcase initialized.
11315 23:06:57.611144 # uc context validated.
11316 23:06:57.611225 # Handled SIG_TRIG
11317 23:06:57.620808 # SIG_OK -- SP:0xFFFFE7570C10 si_addr@:0xffffe7570c10 si_code:2 token@:(nil) offset:-281474562984976
11318 23:06:57.624205 # ==>> completed. PASS(1)
11319 23:06:57.630821 # # MANGLE_PSTATE_INVALID_DAIF_BITS :: Mangling uc_mcontext with INVALID DAIF_BITS
11320 23:06:57.634583 ok 12 selftests: arm64: mangle_pstate_invalid_daif_bits
11321 23:06:57.641046 # selftests: arm64: mangle_pstate_invalid_mode_el1h
11322 23:06:57.681450 # Registered handlers for all signals.
11323 23:06:57.681617 # Detected MINSTKSIGSZ:4720
11324 23:06:57.685032 # Testcase initialized.
11325 23:06:57.688101 # uc context validated.
11326 23:06:57.688182 # Handled SIG_TRIG
11327 23:06:57.697889 # SIG_OK -- SP:0xFFFFC411D980 si_addr@:0xffffc411d980 si_code:2 token@:(nil) offset:-281473971247488
11328 23:06:57.701453 # ==>> completed. PASS(1)
11329 23:06:57.707840 # # MANGLE_PSTATE_INVALID_MODE_EL1h :: Mangling uc_mcontext INVALID MODE EL1h
11330 23:06:57.711492 ok 13 selftests: arm64: mangle_pstate_invalid_mode_el1h
11331 23:06:57.717824 # selftests: arm64: mangle_pstate_invalid_mode_el1t
11332 23:06:57.761424 # Registered handlers for all signals.
11333 23:06:57.761555 # Detected MINSTKSIGSZ:4720
11334 23:06:57.764981 # Testcase initialized.
11335 23:06:57.767800 # uc context validated.
11336 23:06:57.767883 # Handled SIG_TRIG
11337 23:06:57.778126 # SIG_OK -- SP:0xFFFFDCDAD300 si_addr@:0xffffdcdad300 si_code:2 token@:(nil) offset:-281474387071744
11338 23:06:57.781316 # ==>> completed. PASS(1)
11339 23:06:57.788183 # # MANGLE_PSTATE_INVALID_MODE_EL1t :: Mangling uc_mcontext INVALID MODE EL1t
11340 23:06:57.791133 ok 14 selftests: arm64: mangle_pstate_invalid_mode_el1t
11341 23:06:57.795067 # selftests: arm64: mangle_pstate_invalid_mode_el2h
11342 23:06:57.836898 # Registered handlers for all signals.
11343 23:06:57.837021 # Detected MINSTKSIGSZ:4720
11344 23:06:57.840251 # Testcase initialized.
11345 23:06:57.843302 # uc context validated.
11346 23:06:57.843383 # Handled SIG_TRIG
11347 23:06:57.853297 # SIG_OK -- SP:0xFFFFEB7546E0 si_addr@:0xffffeb7546e0 si_code:2 token@:(nil) offset:-281474632074976
11348 23:06:57.856480 # ==>> completed. PASS(1)
11349 23:06:57.863209 # # MANGLE_PSTATE_INVALID_MODE_EL2h :: Mangling uc_mcontext INVALID MODE EL2h
11350 23:06:57.866495 ok 15 selftests: arm64: mangle_pstate_invalid_mode_el2h
11351 23:06:57.873035 # selftests: arm64: mangle_pstate_invalid_mode_el2t
11352 23:06:57.916556 # Registered handlers for all signals.
11353 23:06:57.916677 # Detected MINSTKSIGSZ:4720
11354 23:06:57.920067 # Testcase initialized.
11355 23:06:57.923589 # uc context validated.
11356 23:06:57.923671 # Handled SIG_TRIG
11357 23:06:57.933453 # SIG_OK -- SP:0xFFFFE7453A60 si_addr@:0xffffe7453a60 si_code:2 token@:(nil) offset:-281474561817184
11358 23:06:57.936557 # ==>> completed. PASS(1)
11359 23:06:57.943359 # # MANGLE_PSTATE_INVALID_MODE_EL2t :: Mangling uc_mcontext INVALID MODE EL2t
11360 23:06:57.946491 ok 16 selftests: arm64: mangle_pstate_invalid_mode_el2t
11361 23:06:57.952957 # selftests: arm64: mangle_pstate_invalid_mode_el3h
11362 23:06:57.998831 # Registered handlers for all signals.
11363 23:06:57.998956 # Detected MINSTKSIGSZ:4720
11364 23:06:58.001521 # Testcase initialized.
11365 23:06:58.005106 # uc context validated.
11366 23:06:58.005187 # Handled SIG_TRIG
11367 23:06:58.015262 # SIG_OK -- SP:0xFFFFE5CB1560 si_addr@:0xffffe5cb1560 si_code:2 token@:(nil) offset:-281474537035104
11368 23:06:58.018179 # ==>> completed. PASS(1)
11369 23:06:58.024689 # # MANGLE_PSTATE_INVALID_MODE_EL3h :: Mangling uc_mcontext INVALID MODE EL3h
11370 23:06:58.028179 ok 17 selftests: arm64: mangle_pstate_invalid_mode_el3h
11371 23:06:58.034591 # selftests: arm64: mangle_pstate_invalid_mode_el3t
11372 23:06:58.073271 # Registered handlers for all signals.
11373 23:06:58.073401 # Detected MINSTKSIGSZ:4720
11374 23:06:58.076626 # Testcase initialized.
11375 23:06:58.079950 # uc context validated.
11376 23:06:58.080033 # Handled SIG_TRIG
11377 23:06:58.089693 # SIG_OK -- SP:0xFFFFC6C78080 si_addr@:0xffffc6c78080 si_code:2 token@:(nil) offset:-281474016706688
11378 23:06:58.093373 # ==>> completed. PASS(1)
11379 23:06:58.099655 # # MANGLE_PSTATE_INVALID_MODE_EL3t :: Mangling uc_mcontext INVALID MODE EL3t
11380 23:06:58.103129 ok 18 selftests: arm64: mangle_pstate_invalid_mode_el3t
11381 23:06:58.106269 # selftests: arm64: sme_trap_no_sm
11382 23:06:58.146860 # Registered handlers for all signals.
11383 23:06:58.146985 # Detected MINSTKSIGSZ:4720
11384 23:06:58.149516 # ==>> completed. SKIP.
11385 23:06:58.159864 # # SME trap without SM :: Check that we get a SIGILL if we use streaming mode without enabling it
11386 23:06:58.163306 ok 19 selftests: arm64: sme_trap_no_sm # SKIP
11387 23:06:58.166027 # selftests: arm64: sme_trap_non_streaming
11388 23:06:58.213712 # Registered handlers for all signals.
11389 23:06:58.213840 # Detected MINSTKSIGSZ:4720
11390 23:06:58.217047 # ==>> completed. SKIP.
11391 23:06:58.226949 # # SME SM trap unsupported instruction :: Check that we get a SIGILL if we use an unsupported instruction in streaming mode
11392 23:06:58.234097 ok 20 selftests: arm64: sme_trap_non_streaming # SKIP
11393 23:06:58.234185 # selftests: arm64: sme_trap_za
11394 23:06:58.285198 # Registered handlers for all signals.
11395 23:06:58.285333 # Detected MINSTKSIGSZ:4720
11396 23:06:58.288746 # Testcase initialized.
11397 23:06:58.298461 # SIG_OK -- SP:0xFFFFF67E3FE0 si_addr@:0xaaaad8f92510 si_code:1 token@:(nil) offset:-187650761368848
11398 23:06:58.298606 # ==>> completed. PASS(1)
11399 23:06:58.308914 # # SME ZA trap :: Check that we get a SIGILL if we access ZA without enabling
11400 23:06:58.311763 ok 21 selftests: arm64: sme_trap_za
11401 23:06:58.311848 # selftests: arm64: sme_vl
11402 23:06:58.363955 # Registered handlers for all signals.
11403 23:06:58.364094 # Detected MINSTKSIGSZ:4720
11404 23:06:58.366877 # ==>> completed. SKIP.
11405 23:06:58.370660 # # SME VL :: Check that we get the right SME VL reported
11406 23:06:58.373400 ok 22 selftests: arm64: sme_vl # SKIP
11407 23:06:58.379815 # selftests: arm64: ssve_regs
11408 23:06:58.449366 # Registered handlers for all signals.
11409 23:06:58.449512 # Detected MINSTKSIGSZ:4720
11410 23:06:58.452459 # ==>> completed. SKIP.
11411 23:06:58.459351 # # Streaming SVE registers :: Check that we get the right Streaming SVE registers reported
11412 23:06:58.462554 ok 23 selftests: arm64: ssve_regs # SKIP
11413 23:06:58.465804 # selftests: arm64: sve_regs
11414 23:06:58.532780 # Registered handlers for all signals.
11415 23:06:58.532925 # Detected MINSTKSIGSZ:4720
11416 23:06:58.536538 # ==>> completed. SKIP.
11417 23:06:58.542982 # # SVE registers :: Check that we get the right SVE registers reported
11418 23:06:58.546634 ok 24 selftests: arm64: sve_regs # SKIP
11419 23:06:58.551388 # selftests: arm64: sve_vl
11420 23:06:58.617527 # Registered handlers for all signals.
11421 23:06:58.617681 # Detected MINSTKSIGSZ:4720
11422 23:06:58.620145 # ==>> completed. SKIP.
11423 23:06:58.627548 # # SVE VL :: Check that we get the right SVE VL reported
11424 23:06:58.630075 ok 25 selftests: arm64: sve_vl # SKIP
11425 23:06:58.633401 # selftests: arm64: za_no_regs
11426 23:06:58.670083 # Registered handlers for all signals.
11427 23:06:58.670213 # Detected MINSTKSIGSZ:4720
11428 23:06:58.673429 # ==>> completed. SKIP.
11429 23:06:58.680019 # # ZA registers - ZA disabled :: Check ZA context with ZA disabled
11430 23:06:58.683463 ok 26 selftests: arm64: za_no_regs # SKIP
11431 23:06:58.687081 # selftests: arm64: za_regs
11432 23:06:58.726717 # Registered handlers for all signals.
11433 23:06:58.726841 # Detected MINSTKSIGSZ:4720
11434 23:06:58.729326 # ==>> completed. SKIP.
11435 23:06:58.736050 # # ZA register :: Check that we get the right ZA registers reported
11436 23:06:58.739419 ok 27 selftests: arm64: za_regs # SKIP
11437 23:06:58.743026 # selftests: arm64: pac
11438 23:06:58.789393 # TAP version 13
11439 23:06:58.789527 # 1..7
11440 23:06:58.792873 # # Starting 7 tests from 1 test cases.
11441 23:06:58.796268 # # RUN global.corrupt_pac ...
11442 23:06:58.799361 # # SKIP PAUTH not enabled
11443 23:06:58.802447 # # OK global.corrupt_pac
11444 23:06:58.805697 # ok 1 # SKIP PAUTH not enabled
11445 23:06:58.812365 # # RUN global.pac_instructions_not_nop ...
11446 23:06:58.815813 # # SKIP PAUTH not enabled
11447 23:06:58.819031 # # OK global.pac_instructions_not_nop
11448 23:06:58.822484 # ok 2 # SKIP PAUTH not enabled
11449 23:06:58.828796 # # RUN global.pac_instructions_not_nop_generic ...
11450 23:06:58.832096 # # SKIP Generic PAUTH not enabled
11451 23:06:58.835307 # # OK global.pac_instructions_not_nop_generic
11452 23:06:58.842173 # ok 3 # SKIP Generic PAUTH not enabled
11453 23:06:58.845424 # # RUN global.single_thread_different_keys ...
11454 23:06:58.848656 # # SKIP PAUTH not enabled
11455 23:06:58.855469 # # OK global.single_thread_different_keys
11456 23:06:58.855554 # ok 4 # SKIP PAUTH not enabled
11457 23:06:58.862745 # # RUN global.exec_changed_keys ...
11458 23:06:58.865605 # # SKIP PAUTH not enabled
11459 23:06:58.869424 # # OK global.exec_changed_keys
11460 23:06:58.872029 # ok 5 # SKIP PAUTH not enabled
11461 23:06:58.875432 # # RUN global.context_switch_keep_keys ...
11462 23:06:58.878640 # # SKIP PAUTH not enabled
11463 23:06:58.885991 # # OK global.context_switch_keep_keys
11464 23:06:58.886074 # ok 6 # SKIP PAUTH not enabled
11465 23:06:58.892319 # # RUN global.context_switch_keep_keys_generic ...
11466 23:06:58.895163 # # SKIP Generic PAUTH not enabled
11467 23:06:58.901725 # # OK global.context_switch_keep_keys_generic
11468 23:06:58.905246 # ok 7 # SKIP Generic PAUTH not enabled
11469 23:06:58.908872 # # PASSED: 7 / 7 tests passed.
11470 23:06:58.911841 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:7 error:0
11471 23:06:58.915454 ok 28 selftests: arm64: pac
11472 23:06:58.918371 # selftests: arm64: fp-stress
11473 23:07:05.872286 <6>[ 46.158791] vpu: disabling
11474 23:07:05.875564 <6>[ 46.161839] vproc2: disabling
11475 23:07:05.878891 <6>[ 46.165111] vproc1: disabling
11476 23:07:05.881843 <6>[ 46.168386] vaud18: disabling
11477 23:07:05.888780 <6>[ 46.171821] vsram_others: disabling
11478 23:07:05.891671 <6>[ 46.175715] va09: disabling
11479 23:07:05.895601 <6>[ 46.178834] vsram_md: disabling
11480 23:07:05.898431 <6>[ 46.182332] Vgpu: disabling
11481 23:07:08.857070 # TAP version 13
11482 23:07:08.857699 # 1..16
11483 23:07:08.860499 # # 8 CPUs, 0 SVE VLs, 0 SME VLs
11484 23:07:08.863956 # # Will run for 10s
11485 23:07:08.864378 # # Started FPSIMD-0-0
11486 23:07:08.867482 # # Started FPSIMD-0-1
11487 23:07:08.871018 # # Started FPSIMD-1-0
11488 23:07:08.871631 # # Started FPSIMD-1-1
11489 23:07:08.873419 # # Started FPSIMD-2-0
11490 23:07:08.877507 # # Started FPSIMD-2-1
11491 23:07:08.877960 # # Started FPSIMD-3-0
11492 23:07:08.880233 # # Started FPSIMD-3-1
11493 23:07:08.883764 # # Started FPSIMD-4-0
11494 23:07:08.884178 # # Started FPSIMD-4-1
11495 23:07:08.886755 # # Started FPSIMD-5-0
11496 23:07:08.887170 # # Started FPSIMD-5-1
11497 23:07:08.890118 # # Started FPSIMD-6-0
11498 23:07:08.893080 # # Started FPSIMD-6-1
11499 23:07:08.893161 # # Started FPSIMD-7-0
11500 23:07:08.896657 # # Started FPSIMD-7-1
11501 23:07:08.900225 # # FPSIMD-1-0: Vector length: 128 bits
11502 23:07:08.903792 # # FPSIMD-1-0: PID: 1173
11503 23:07:08.907090 # # FPSIMD-0-1: Vector length: 128 bits
11504 23:07:08.907251 # # FPSIMD-0-1: PID: 1172
11505 23:07:08.913495 # # FPSIMD-0-0: Vector length: 128 bits
11506 23:07:08.913699 # # FPSIMD-0-0: PID: 1171
11507 23:07:08.916715 # # FPSIMD-2-0: Vector length: 128 bits
11508 23:07:08.919852 # # FPSIMD-2-0: PID: 1175
11509 23:07:08.923829 # # FPSIMD-2-1: Vector length: 128 bits
11510 23:07:08.926803 # # FPSIMD-2-1: PID: 1176
11511 23:07:08.930330 # # FPSIMD-1-1: Vector length: 128 bits
11512 23:07:08.933503 # # FPSIMD-1-1: PID: 1174
11513 23:07:08.937275 # # FPSIMD-3-1: Vector length: 128 bits
11514 23:07:08.937858 # # FPSIMD-3-1: PID: 1178
11515 23:07:08.940264 # # FPSIMD-7-1: Vector length: 128 bits
11516 23:07:08.943661 # # FPSIMD-7-1: PID: 1186
11517 23:07:08.946928 # # FPSIMD-7-0: Vector length: 128 bits
11518 23:07:08.949831 # # FPSIMD-7-0: PID: 1185
11519 23:07:08.953609 # # FPSIMD-5-1: Vector length: 128 bits
11520 23:07:08.956947 # # FPSIMD-5-1: PID: 1182
11521 23:07:08.959588 # # FPSIMD-6-0: Vector length: 128 bits
11522 23:07:08.960010 # # FPSIMD-6-0: PID: 1183
11523 23:07:08.966460 # # FPSIMD-4-1: Vector length: 128 bits
11524 23:07:08.966995 # # FPSIMD-4-1: PID: 1180
11525 23:07:08.969881 # # FPSIMD-6-1: Vector length: 128 bits
11526 23:07:08.973521 # # FPSIMD-6-1: PID: 1184
11527 23:07:08.976342 # # FPSIMD-4-0: Vector length: 128 bits
11528 23:07:08.980096 # # FPSIMD-4-0: PID: 1179
11529 23:07:08.983689 # # FPSIMD-3-0: Vector length: 128 bits
11530 23:07:08.986724 # # FPSIMD-3-0: PID: 1177
11531 23:07:08.990287 # # FPSIMD-5-0: Vector length: 128 bits
11532 23:07:08.990761 # # FPSIMD-5-0: PID: 1181
11533 23:07:08.993301 # # Finishing up...
11534 23:07:09.000256 # # FPSIMD-3-0: Terminated by signal 15, no error, iterations=1070335, signals=10
11535 23:07:09.006509 # # FPSIMD-2-0: Terminated by signal 15, no error, iterations=1175032, signals=10
11536 23:07:09.012823 # # FPSIMD-3-1: Terminated by signal 15, no error, iterations=999631, signals=10
11537 23:07:09.022884 # # FPSIMD-0-0: Terminated by signal 15, no error, iterations=1531220, signals=10
11538 23:07:09.029373 # # FPSIMD-4-1: Terminated by signal 15, no error, iterations=1822789, signals=10
11539 23:07:09.036207 # # FPSIMD-5-1: Terminated by signal 15, no error, iterations=2156296, signals=10
11540 23:07:09.042876 # # FPSIMD-6-1: Terminated by signal 15, no error, iterations=1202768, signals=10
11541 23:07:09.046058 # ok 1 FPSIMD-0-0
11542 23:07:09.046563 # ok 2 FPSIMD-0-1
11543 23:07:09.049189 # ok 3 FPSIMD-1-0
11544 23:07:09.049753 # ok 4 FPSIMD-1-1
11545 23:07:09.052772 # ok 5 FPSIMD-2-0
11546 23:07:09.053193 # ok 6 FPSIMD-2-1
11547 23:07:09.056410 # ok 7 FPSIMD-3-0
11548 23:07:09.056831 # ok 8 FPSIMD-3-1
11549 23:07:09.059076 # ok 9 FPSIMD-4-0
11550 23:07:09.059375 # ok 10 FPSIMD-4-1
11551 23:07:09.062463 # ok 11 FPSIMD-5-0
11552 23:07:09.062781 # ok 12 FPSIMD-5-1
11553 23:07:09.066184 # ok 13 FPSIMD-6-0
11554 23:07:09.066484 # ok 14 FPSIMD-6-1
11555 23:07:09.068862 # ok 15 FPSIMD-7-0
11556 23:07:09.069164 # ok 16 FPSIMD-7-1
11557 23:07:09.075630 # # FPSIMD-4-0: Terminated by signal 15, no error, iterations=1071096, signals=9
11558 23:07:09.085505 # # FPSIMD-7-0: Terminated by signal 15, no error, iterations=1020071, signals=10
11559 23:07:09.092248 # # FPSIMD-1-1: Terminated by signal 15, no error, iterations=1026501, signals=10
11560 23:07:09.098701 # # FPSIMD-2-1: Terminated by signal 15, no error, iterations=1024737, signals=10
11561 23:07:09.105887 # # FPSIMD-5-0: Terminated by signal 15, no error, iterations=1077411, signals=10
11562 23:07:09.112105 # # FPSIMD-0-1: Terminated by signal 15, no error, iterations=1632556, signals=9
11563 23:07:09.121751 # # FPSIMD-7-1: Terminated by signal 15, no error, iterations=1225628, signals=10
11564 23:07:09.128757 # # FPSIMD-6-0: Terminated by signal 15, no error, iterations=1156950, signals=10
11565 23:07:09.135271 # # FPSIMD-1-0: Terminated by signal 15, no error, iterations=1231422, signals=9
11566 23:07:09.138724 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:0 error:0
11567 23:07:09.142062 ok 29 selftests: arm64: fp-stress
11568 23:07:09.145632 # selftests: arm64: sve-ptrace
11569 23:07:09.148498 # TAP version 13
11570 23:07:09.148790 # 1..4104
11571 23:07:09.152047 # ok 2 # SKIP SVE not available
11572 23:07:09.155624 # # Planned tests != run tests (4104 != 1)
11573 23:07:09.158448 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11574 23:07:09.165050 ok 30 selftests: arm64: sve-ptrace # SKIP
11575 23:07:09.165368 # selftests: arm64: sve-probe-vls
11576 23:07:09.168570 # TAP version 13
11577 23:07:09.168958 # 1..2
11578 23:07:09.171934 # ok 2 # SKIP SVE not available
11579 23:07:09.175179 # # Planned tests != run tests (2 != 1)
11580 23:07:09.181962 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11581 23:07:09.185102 ok 31 selftests: arm64: sve-probe-vls # SKIP
11582 23:07:09.188495 # selftests: arm64: vec-syscfg
11583 23:07:09.188806 # TAP version 13
11584 23:07:09.189068 # 1..20
11585 23:07:09.191900 # ok 1 # SKIP SVE not supported
11586 23:07:09.195331 # ok 2 # SKIP SVE not supported
11587 23:07:09.198371 # ok 3 # SKIP SVE not supported
11588 23:07:09.201880 # ok 4 # SKIP SVE not supported
11589 23:07:09.204993 # ok 5 # SKIP SVE not supported
11590 23:07:09.205294 # ok 6 # SKIP SVE not supported
11591 23:07:09.208150 # ok 7 # SKIP SVE not supported
11592 23:07:09.211716 # ok 8 # SKIP SVE not supported
11593 23:07:09.214790 # ok 9 # SKIP SVE not supported
11594 23:07:09.217983 # ok 10 # SKIP SVE not supported
11595 23:07:09.221570 # ok 11 # SKIP SME not supported
11596 23:07:09.224969 # ok 12 # SKIP SME not supported
11597 23:07:09.228005 # ok 13 # SKIP SME not supported
11598 23:07:09.231391 # ok 14 # SKIP SME not supported
11599 23:07:09.231651 # ok 15 # SKIP SME not supported
11600 23:07:09.235021 # ok 16 # SKIP SME not supported
11601 23:07:09.238641 # ok 17 # SKIP SME not supported
11602 23:07:09.241709 # ok 18 # SKIP SME not supported
11603 23:07:09.244652 # ok 19 # SKIP SME not supported
11604 23:07:09.248118 # ok 20 # SKIP SME not supported
11605 23:07:09.251219 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:20 error:0
11606 23:07:09.254669 ok 32 selftests: arm64: vec-syscfg
11607 23:07:09.257852 # selftests: arm64: za-fork
11608 23:07:09.261645 # TAP version 13
11609 23:07:09.261877 # 1..1
11610 23:07:09.262072 # # PID: 1261
11611 23:07:09.264427 # # SME support not present
11612 23:07:09.264786 # ok 0 skipped
11613 23:07:09.271228 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11614 23:07:09.274832 ok 33 selftests: arm64: za-fork
11615 23:07:09.277773 # selftests: arm64: za-ptrace
11616 23:07:09.278051 # TAP version 13
11617 23:07:09.278270 # 1..1
11618 23:07:09.281534 # ok 2 # SKIP SME not available
11619 23:07:09.287922 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11620 23:07:09.291173 ok 34 selftests: arm64: za-ptrace # SKIP
11621 23:07:09.294746 # selftests: arm64: check_buffer_fill
11622 23:07:09.307999 # # SKIP: MTE features unavailable
11623 23:07:09.315543 ok 35 selftests: arm64: check_buffer_fill # SKIP
11624 23:07:09.333348 # selftests: arm64: check_child_memory
11625 23:07:09.387470 # # SKIP: MTE features unavailable
11626 23:07:09.394863 ok 36 selftests: arm64: check_child_memory # SKIP
11627 23:07:09.409168 # selftests: arm64: check_gcr_el1_cswitch
11628 23:07:09.474165 # # SKIP: MTE features unavailable
11629 23:07:09.481357 ok 37 selftests: arm64: check_gcr_el1_cswitch # SKIP
11630 23:07:09.494141 # selftests: arm64: check_ksm_options
11631 23:07:09.549599 # # SKIP: MTE features unavailable
11632 23:07:09.557831 ok 38 selftests: arm64: check_ksm_options # SKIP
11633 23:07:09.575985 # selftests: arm64: check_mmap_options
11634 23:07:09.619877 # # SKIP: MTE features unavailable
11635 23:07:09.627061 ok 39 selftests: arm64: check_mmap_options # SKIP
11636 23:07:09.640532 # selftests: arm64: check_prctl
11637 23:07:09.696329 # TAP version 13
11638 23:07:09.696848 # 1..5
11639 23:07:09.699338 # ok 1 check_basic_read
11640 23:07:09.699761 # ok 2 NONE
11641 23:07:09.702764 # ok 3 # SKIP SYNC
11642 23:07:09.703319 # ok 4 # SKIP ASYNC
11643 23:07:09.705962 # ok 5 # SKIP SYNC+ASYNC
11644 23:07:09.709528 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:3 error:0
11645 23:07:09.712329 ok 40 selftests: arm64: check_prctl
11646 23:07:09.721378 # selftests: arm64: check_tags_inclusion
11647 23:07:09.776216 # # SKIP: MTE features unavailable
11648 23:07:09.783099 ok 41 selftests: arm64: check_tags_inclusion # SKIP
11649 23:07:09.795835 # selftests: arm64: check_user_mem
11650 23:07:09.860875 # # SKIP: MTE features unavailable
11651 23:07:09.867191 ok 42 selftests: arm64: check_user_mem # SKIP
11652 23:07:09.881616 # selftests: arm64: btitest
11653 23:07:09.923419 # TAP version 13
11654 23:07:09.923961 # 1..18
11655 23:07:09.926944 # # HWCAP_PACA not present
11656 23:07:09.930005 # # HWCAP2_BTI not present
11657 23:07:09.930511 # # Test binary built for BTI
11658 23:07:09.936353 # ok 1 nohint_func/call_using_br_x0 # SKIP
11659 23:07:09.939845 # ok 1 nohint_func/call_using_br_x16 # SKIP
11660 23:07:09.942806 # ok 1 nohint_func/call_using_blr # SKIP
11661 23:07:09.946113 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11662 23:07:09.949318 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11663 23:07:09.952742 # ok 1 bti_none_func/call_using_blr # SKIP
11664 23:07:09.959534 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11665 23:07:09.962861 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11666 23:07:09.966684 # ok 1 bti_c_func/call_using_blr # SKIP
11667 23:07:09.969101 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11668 23:07:09.972634 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11669 23:07:09.975880 # ok 1 bti_j_func/call_using_blr # SKIP
11670 23:07:09.979041 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11671 23:07:09.985485 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11672 23:07:09.989013 # ok 1 bti_jc_func/call_using_blr # SKIP
11673 23:07:09.992158 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11674 23:07:09.995739 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11675 23:07:09.999215 # ok 1 paciasp_func/call_using_blr # SKIP
11676 23:07:10.005595 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11677 23:07:10.008632 # # WARNING - EXPECTED TEST COUNT WRONG
11678 23:07:10.012548 ok 43 selftests: arm64: btitest
11679 23:07:10.015619 # selftests: arm64: nobtitest
11680 23:07:10.015945 # TAP version 13
11681 23:07:10.016232 # 1..18
11682 23:07:10.019260 # # HWCAP_PACA not present
11683 23:07:10.022289 # # HWCAP2_BTI not present
11684 23:07:10.025479 # # Test binary not built for BTI
11685 23:07:10.028562 # ok 1 nohint_func/call_using_br_x0 # SKIP
11686 23:07:10.032135 # ok 1 nohint_func/call_using_br_x16 # SKIP
11687 23:07:10.035140 # ok 1 nohint_func/call_using_blr # SKIP
11688 23:07:10.038554 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11689 23:07:10.042117 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11690 23:07:10.048545 # ok 1 bti_none_func/call_using_blr # SKIP
11691 23:07:10.052281 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11692 23:07:10.055743 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11693 23:07:10.058707 # ok 1 bti_c_func/call_using_blr # SKIP
11694 23:07:10.062006 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11695 23:07:10.065369 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11696 23:07:10.068321 # ok 1 bti_j_func/call_using_blr # SKIP
11697 23:07:10.071752 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11698 23:07:10.078607 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11699 23:07:10.081842 # ok 1 bti_jc_func/call_using_blr # SKIP
11700 23:07:10.085307 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11701 23:07:10.088722 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11702 23:07:10.092134 # ok 1 paciasp_func/call_using_blr # SKIP
11703 23:07:10.098677 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11704 23:07:10.101692 # # WARNING - EXPECTED TEST COUNT WRONG
11705 23:07:10.105072 ok 44 selftests: arm64: nobtitest
11706 23:07:10.105462 # selftests: arm64: hwcap
11707 23:07:10.108258 # TAP version 13
11708 23:07:10.108644 # 1..28
11709 23:07:10.111832 # ok 1 cpuinfo_match_RNG
11710 23:07:10.114800 # # SIGILL reported for RNG
11711 23:07:10.115214 # ok 2 # SKIP sigill_RNG
11712 23:07:10.118340 # ok 3 cpuinfo_match_SME
11713 23:07:10.118728 # ok 4 sigill_SME
11714 23:07:10.121648 # ok 5 cpuinfo_match_SVE
11715 23:07:10.124846 # ok 6 sigill_SVE
11716 23:07:10.125248 # ok 7 cpuinfo_match_SVE 2
11717 23:07:10.128484 # # SIGILL reported for SVE 2
11718 23:07:10.131724 # ok 8 # SKIP sigill_SVE 2
11719 23:07:10.134875 # ok 9 cpuinfo_match_SVE AES
11720 23:07:10.138054 # # SIGILL reported for SVE AES
11721 23:07:10.138442 # ok 10 # SKIP sigill_SVE AES
11722 23:07:10.141297 # ok 11 cpuinfo_match_SVE2 PMULL
11723 23:07:10.144942 # # SIGILL reported for SVE2 PMULL
11724 23:07:10.148215 # ok 12 # SKIP sigill_SVE2 PMULL
11725 23:07:10.151487 # ok 13 cpuinfo_match_SVE2 BITPERM
11726 23:07:10.154693 # # SIGILL reported for SVE2 BITPERM
11727 23:07:10.158091 # ok 14 # SKIP sigill_SVE2 BITPERM
11728 23:07:10.161353 # ok 15 cpuinfo_match_SVE2 SHA3
11729 23:07:10.165197 # # SIGILL reported for SVE2 SHA3
11730 23:07:10.168177 # ok 16 # SKIP sigill_SVE2 SHA3
11731 23:07:10.171544 # ok 17 cpuinfo_match_SVE2 SM4
11732 23:07:10.171963 # # SIGILL reported for SVE2 SM4
11733 23:07:10.174598 # ok 18 # SKIP sigill_SVE2 SM4
11734 23:07:10.177756 # ok 19 cpuinfo_match_SVE2 I8MM
11735 23:07:10.181140 # # SIGILL reported for SVE2 I8MM
11736 23:07:10.185033 # ok 20 # SKIP sigill_SVE2 I8MM
11737 23:07:10.188046 # ok 21 cpuinfo_match_SVE2 F32MM
11738 23:07:10.191476 # # SIGILL reported for SVE2 F32MM
11739 23:07:10.194337 # ok 22 # SKIP sigill_SVE2 F32MM
11740 23:07:10.197660 # ok 23 cpuinfo_match_SVE2 F64MM
11741 23:07:10.198090 # # SIGILL reported for SVE2 F64MM
11742 23:07:10.201647 # ok 24 # SKIP sigill_SVE2 F64MM
11743 23:07:10.204348 # ok 25 cpuinfo_match_SVE2 BF16
11744 23:07:10.207829 # # SIGILL reported for SVE2 BF16
11745 23:07:10.210761 # ok 26 # SKIP sigill_SVE2 BF16
11746 23:07:10.214532 # ok 27 cpuinfo_match_SVE2 EBF16
11747 23:07:10.217731 # ok 28 # SKIP sigill_SVE2 EBF16
11748 23:07:10.221115 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:12 error:0
11749 23:07:10.224234 ok 45 selftests: arm64: hwcap
11750 23:07:10.228002 # selftests: arm64: ptrace
11751 23:07:10.228422 # TAP version 13
11752 23:07:10.231163 # 1..7
11753 23:07:10.234397 # # Parent is 1503, child is 1504
11754 23:07:10.234841 # ok 1 read_tpidr_one
11755 23:07:10.237533 # ok 2 write_tpidr_one
11756 23:07:10.237987 # ok 3 verify_tpidr_one
11757 23:07:10.240914 # ok 4 count_tpidrs
11758 23:07:10.241333 # ok 5 tpidr2_write
11759 23:07:10.244895 # ok 6 tpidr2_read
11760 23:07:10.247594 # ok 7 write_tpidr_only
11761 23:07:10.250771 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
11762 23:07:10.254330 ok 46 selftests: arm64: ptrace
11763 23:07:10.257731 # selftests: arm64: syscall-abi
11764 23:07:10.258155 # TAP version 13
11765 23:07:10.260918 # 1..2
11766 23:07:10.261370 # ok 1 getpid() FPSIMD
11767 23:07:10.264453 # ok 2 sched_yield() FPSIMD
11768 23:07:10.267288 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:0 error:0
11769 23:07:10.271062 ok 47 selftests: arm64: syscall-abi
11770 23:07:10.273868 # selftests: arm64: tpidr2
11771 23:07:10.283484 # TAP version 13
11772 23:07:10.284009 # 1..5
11773 23:07:10.286610 # # PID: 1540
11774 23:07:10.287131 # # SME support not present
11775 23:07:10.289966 # ok 0 skipped, TPIDR2 not supported
11776 23:07:10.293295 # ok 1 skipped, TPIDR2 not supported
11777 23:07:10.296513 # ok 2 skipped, TPIDR2 not supported
11778 23:07:10.300172 # ok 3 skipped, TPIDR2 not supported
11779 23:07:10.303405 # ok 4 skipped, TPIDR2 not supported
11780 23:07:10.310064 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0
11781 23:07:10.312888 ok 48 selftests: arm64: tpidr2
11782 23:07:10.973755 arm64_tags_test pass
11783 23:07:10.977026 arm64_run_tags_test_sh pass
11784 23:07:10.980480 arm64_fake_sigreturn_bad_magic pass
11785 23:07:10.983807 arm64_fake_sigreturn_bad_size pass
11786 23:07:10.987344 arm64_fake_sigreturn_bad_size_for_magic0 pass
11787 23:07:10.990118 arm64_fake_sigreturn_duplicated_fpsimd pass
11788 23:07:10.993990 arm64_fake_sigreturn_misaligned_sp pass
11789 23:07:10.996927 arm64_fake_sigreturn_missing_fpsimd pass
11790 23:07:11.000310 arm64_fake_sigreturn_sme_change_vl skip
11791 23:07:11.003874 arm64_fake_sigreturn_sve_change_vl skip
11792 23:07:11.010095 arm64_mangle_pstate_invalid_compat_toggle pass
11793 23:07:11.013758 arm64_mangle_pstate_invalid_daif_bits pass
11794 23:07:11.017656 arm64_mangle_pstate_invalid_mode_el1h pass
11795 23:07:11.020471 arm64_mangle_pstate_invalid_mode_el1t pass
11796 23:07:11.023315 arm64_mangle_pstate_invalid_mode_el2h pass
11797 23:07:11.026869 arm64_mangle_pstate_invalid_mode_el2t pass
11798 23:07:11.033438 arm64_mangle_pstate_invalid_mode_el3h pass
11799 23:07:11.036764 arm64_mangle_pstate_invalid_mode_el3t pass
11800 23:07:11.040192 arm64_sme_trap_no_sm skip
11801 23:07:11.040648 arm64_sme_trap_non_streaming skip
11802 23:07:11.043529 arm64_sme_trap_za pass
11803 23:07:11.046511 arm64_sme_vl skip
11804 23:07:11.046925 arm64_ssve_regs skip
11805 23:07:11.050432 arm64_sve_regs skip
11806 23:07:11.050846 arm64_sve_vl skip
11807 23:07:11.053003 arm64_za_no_regs skip
11808 23:07:11.053414 arm64_za_regs skip
11809 23:07:11.056804 arm64_pac_pauth_not_enabled skip
11810 23:07:11.060133 arm64_pac_pauth_not_enabled skip
11811 23:07:11.063330 arm64_pac_generic_pauth_not_enabled skip
11812 23:07:11.066340 arm64_pac_pauth_not_enabled skip
11813 23:07:11.069938 arm64_pac_pauth_not_enabled skip
11814 23:07:11.072876 arm64_pac_pauth_not_enabled skip
11815 23:07:11.076395 arm64_pac_generic_pauth_not_enabled skip
11816 23:07:11.076816 arm64_pac pass
11817 23:07:11.079956 arm64_fp-stress_FPSIMD-0-0 pass
11818 23:07:11.083347 arm64_fp-stress_FPSIMD-0-1 pass
11819 23:07:11.086111 arm64_fp-stress_FPSIMD-1-0 pass
11820 23:07:11.089727 arm64_fp-stress_FPSIMD-1-1 pass
11821 23:07:11.092767 arm64_fp-stress_FPSIMD-2-0 pass
11822 23:07:11.096077 arm64_fp-stress_FPSIMD-2-1 pass
11823 23:07:11.096491 arm64_fp-stress_FPSIMD-3-0 pass
11824 23:07:11.099642 arm64_fp-stress_FPSIMD-3-1 pass
11825 23:07:11.102664 arm64_fp-stress_FPSIMD-4-0 pass
11826 23:07:11.106772 arm64_fp-stress_FPSIMD-4-1 pass
11827 23:07:11.109797 arm64_fp-stress_FPSIMD-5-0 pass
11828 23:07:11.112857 arm64_fp-stress_FPSIMD-5-1 pass
11829 23:07:11.116396 arm64_fp-stress_FPSIMD-6-0 pass
11830 23:07:11.119812 arm64_fp-stress_FPSIMD-6-1 pass
11831 23:07:11.120327 arm64_fp-stress_FPSIMD-7-0 pass
11832 23:07:11.123018 arm64_fp-stress_FPSIMD-7-1 pass
11833 23:07:11.125964 arm64_fp-stress pass
11834 23:07:11.129651 arm64_sve-ptrace_sve_not_available skip
11835 23:07:11.132515 arm64_sve-ptrace skip
11836 23:07:11.136126 arm64_sve-probe-vls_sve_not_available skip
11837 23:07:11.136547 arm64_sve-probe-vls skip
11838 23:07:11.139329 arm64_vec-syscfg_sve_not_supported skip
11839 23:07:11.146313 arm64_vec-syscfg_sve_not_supported skip
11840 23:07:11.148824 arm64_vec-syscfg_sve_not_supported skip
11841 23:07:11.152550 arm64_vec-syscfg_sve_not_supported skip
11842 23:07:11.155770 arm64_vec-syscfg_sve_not_supported skip
11843 23:07:11.159282 arm64_vec-syscfg_sve_not_supported skip
11844 23:07:11.162641 arm64_vec-syscfg_sve_not_supported skip
11845 23:07:11.165827 arm64_vec-syscfg_sve_not_supported skip
11846 23:07:11.169071 arm64_vec-syscfg_sve_not_supported skip
11847 23:07:11.172217 arm64_vec-syscfg_sve_not_supported skip
11848 23:07:11.175723 arm64_vec-syscfg_sme_not_supported skip
11849 23:07:11.179484 arm64_vec-syscfg_sme_not_supported skip
11850 23:07:11.182132 arm64_vec-syscfg_sme_not_supported skip
11851 23:07:11.185359 arm64_vec-syscfg_sme_not_supported skip
11852 23:07:11.192110 arm64_vec-syscfg_sme_not_supported skip
11853 23:07:11.196808 arm64_vec-syscfg_sme_not_supported skip
11854 23:07:11.198885 arm64_vec-syscfg_sme_not_supported skip
11855 23:07:11.202190 arm64_vec-syscfg_sme_not_supported skip
11856 23:07:11.205820 arm64_vec-syscfg_sme_not_supported skip
11857 23:07:11.208874 arm64_vec-syscfg_sme_not_supported skip
11858 23:07:11.209409 arm64_vec-syscfg pass
11859 23:07:11.212013 arm64_za-fork_skipped pass
11860 23:07:11.215500 arm64_za-fork pass
11861 23:07:11.218711 arm64_za-ptrace_sme_not_available skip
11862 23:07:11.219379 arm64_za-ptrace skip
11863 23:07:11.222022 arm64_check_buffer_fill skip
11864 23:07:11.225798 arm64_check_child_memory skip
11865 23:07:11.228589 arm64_check_gcr_el1_cswitch skip
11866 23:07:11.232233 arm64_check_ksm_options skip
11867 23:07:11.232721 arm64_check_mmap_options skip
11868 23:07:11.235398 arm64_check_prctl_check_basic_read pass
11869 23:07:11.238894 arm64_check_prctl_NONE pass
11870 23:07:11.242024 arm64_check_prctl_sync skip
11871 23:07:11.245425 arm64_check_prctl_async skip
11872 23:07:11.248393 arm64_check_prctl_sync_async skip
11873 23:07:11.248710 arm64_check_prctl pass
11874 23:07:11.252365 arm64_check_tags_inclusion skip
11875 23:07:11.255072 arm64_check_user_mem skip
11876 23:07:11.258314 arm64_btitest_nohint_func_call_using_br_x0 skip
11877 23:07:11.265485 arm64_btitest_nohint_func_call_using_br_x16 skip
11878 23:07:11.268228 arm64_btitest_nohint_func_call_using_blr skip
11879 23:07:11.271507 arm64_btitest_bti_none_func_call_using_br_x0 skip
11880 23:07:11.275101 arm64_btitest_bti_none_func_call_using_br_x16 skip
11881 23:07:11.281419 arm64_btitest_bti_none_func_call_using_blr skip
11882 23:07:11.285153 arm64_btitest_bti_c_func_call_using_br_x0 skip
11883 23:07:11.288021 arm64_btitest_bti_c_func_call_using_br_x16 skip
11884 23:07:11.291607 arm64_btitest_bti_c_func_call_using_blr skip
11885 23:07:11.298498 arm64_btitest_bti_j_func_call_using_br_x0 skip
11886 23:07:11.301805 arm64_btitest_bti_j_func_call_using_br_x16 skip
11887 23:07:11.304513 arm64_btitest_bti_j_func_call_using_blr skip
11888 23:07:11.308164 arm64_btitest_bti_jc_func_call_using_br_x0 skip
11889 23:07:11.314564 arm64_btitest_bti_jc_func_call_using_br_x16 skip
11890 23:07:11.318055 arm64_btitest_bti_jc_func_call_using_blr skip
11891 23:07:11.321503 arm64_btitest_paciasp_func_call_using_br_x0 skip
11892 23:07:11.327808 arm64_btitest_paciasp_func_call_using_br_x16 skip
11893 23:07:11.331162 arm64_btitest_paciasp_func_call_using_blr skip
11894 23:07:11.331589 arm64_btitest pass
11895 23:07:11.338143 arm64_nobtitest_nohint_func_call_using_br_x0 skip
11896 23:07:11.341282 arm64_nobtitest_nohint_func_call_using_br_x16 skip
11897 23:07:11.344252 arm64_nobtitest_nohint_func_call_using_blr skip
11898 23:07:11.351160 arm64_nobtitest_bti_none_func_call_using_br_x0 skip
11899 23:07:11.354264 arm64_nobtitest_bti_none_func_call_using_br_x16 skip
11900 23:07:11.361486 arm64_nobtitest_bti_none_func_call_using_blr skip
11901 23:07:11.364384 arm64_nobtitest_bti_c_func_call_using_br_x0 skip
11902 23:07:11.367561 arm64_nobtitest_bti_c_func_call_using_br_x16 skip
11903 23:07:11.374362 arm64_nobtitest_bti_c_func_call_using_blr skip
11904 23:07:11.377477 arm64_nobtitest_bti_j_func_call_using_br_x0 skip
11905 23:07:11.381047 arm64_nobtitest_bti_j_func_call_using_br_x16 skip
11906 23:07:11.384421 arm64_nobtitest_bti_j_func_call_using_blr skip
11907 23:07:11.391070 arm64_nobtitest_bti_jc_func_call_using_br_x0 skip
11908 23:07:11.394202 arm64_nobtitest_bti_jc_func_call_using_br_x16 skip
11909 23:07:11.397375 arm64_nobtitest_bti_jc_func_call_using_blr skip
11910 23:07:11.404174 arm64_nobtitest_paciasp_func_call_using_br_x0 skip
11911 23:07:11.406976 arm64_nobtitest_paciasp_func_call_using_br_x16 skip
11912 23:07:11.410607 arm64_nobtitest_paciasp_func_call_using_blr skip
11913 23:07:11.413881 arm64_nobtitest pass
11914 23:07:11.417188 arm64_hwcap_cpuinfo_match_RNG pass
11915 23:07:11.420343 arm64_hwcap_sigill_rng skip
11916 23:07:11.423967 arm64_hwcap_cpuinfo_match_SME pass
11917 23:07:11.424048 arm64_hwcap_sigill_SME pass
11918 23:07:11.426603 arm64_hwcap_cpuinfo_match_SVE pass
11919 23:07:11.429879 arm64_hwcap_sigill_SVE pass
11920 23:07:11.433126 arm64_hwcap_cpuinfo_match_SVE_2 pass
11921 23:07:11.436618 arm64_hwcap_sigill_sve_2 skip
11922 23:07:11.439857 arm64_hwcap_cpuinfo_match_SVE_AES pass
11923 23:07:11.443265 arm64_hwcap_sigill_sve_aes skip
11924 23:07:11.446712 arm64_hwcap_cpuinfo_match_SVE2_PMULL pass
11925 23:07:11.449724 arm64_hwcap_sigill_sve2_pmull skip
11926 23:07:11.453213 arm64_hwcap_cpuinfo_match_SVE2_BITPERM pass
11927 23:07:11.456535 arm64_hwcap_sigill_sve2_bitperm skip
11928 23:07:11.460202 arm64_hwcap_cpuinfo_match_SVE2_SHA3 pass
11929 23:07:11.463736 arm64_hwcap_sigill_sve2_sha3 skip
11930 23:07:11.466533 arm64_hwcap_cpuinfo_match_SVE2_SM4 pass
11931 23:07:11.469993 arm64_hwcap_sigill_sve2_sm4 skip
11932 23:07:11.473469 arm64_hwcap_cpuinfo_match_SVE2_I8MM pass
11933 23:07:11.476830 arm64_hwcap_sigill_sve2_i8mm skip
11934 23:07:11.479948 arm64_hwcap_cpuinfo_match_SVE2_F32MM pass
11935 23:07:11.483428 arm64_hwcap_sigill_sve2_f32mm skip
11936 23:07:11.486598 arm64_hwcap_cpuinfo_match_SVE2_F64MM pass
11937 23:07:11.489914 arm64_hwcap_sigill_sve2_f64mm skip
11938 23:07:11.493703 arm64_hwcap_cpuinfo_match_SVE2_BF16 pass
11939 23:07:11.496962 arm64_hwcap_sigill_sve2_bf16 skip
11940 23:07:11.499923 arm64_hwcap_cpuinfo_match_SVE2_EBF16 pass
11941 23:07:11.503455 arm64_hwcap_sigill_sve2_ebf16 skip
11942 23:07:11.506708 arm64_hwcap pass
11943 23:07:11.509723 arm64_ptrace_read_tpidr_one pass
11944 23:07:11.512893 arm64_ptrace_write_tpidr_one pass
11945 23:07:11.516446 arm64_ptrace_verify_tpidr_one pass
11946 23:07:11.516527 arm64_ptrace_count_tpidrs pass
11947 23:07:11.519962 arm64_ptrace_tpidr2_write pass
11948 23:07:11.522873 arm64_ptrace_tpidr2_read pass
11949 23:07:11.526451 arm64_ptrace_write_tpidr_only pass
11950 23:07:11.529544 arm64_ptrace pass
11951 23:07:11.532640 arm64_syscall-abi_getpid_FPSIMD pass
11952 23:07:11.536238 arm64_syscall-abi_sched_yield_FPSIMD pass
11953 23:07:11.536324 arm64_syscall-abi pass
11954 23:07:11.542721 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11955 23:07:11.545959 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11956 23:07:11.549448 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11957 23:07:11.553012 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11958 23:07:11.560133 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11959 23:07:11.560617 arm64_tpidr2 pass
11960 23:07:11.563073 + ../../utils/send-to-lava.sh ./output/result.txt
11961 23:07:11.569612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-arm64 RESULT=pass>
11962 23:07:11.570410 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-arm64 RESULT=pass
11964 23:07:11.575894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tags_test RESULT=pass>
11965 23:07:11.576788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tags_test RESULT=pass
11967 23:07:11.583147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass>
11968 23:07:11.584016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass
11970 23:07:11.589355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass>
11971 23:07:11.589918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass
11973 23:07:11.617959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass>
11974 23:07:11.618479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass
11976 23:07:11.672625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass>
11977 23:07:11.673004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass
11979 23:07:11.708644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass>
11980 23:07:11.708992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass
11982 23:07:11.745005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass>
11983 23:07:11.745323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass
11985 23:07:11.783812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass>
11986 23:07:11.784136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass
11988 23:07:11.823971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip>
11989 23:07:11.824292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip
11991 23:07:11.868011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip>
11992 23:07:11.868340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip
11994 23:07:11.909006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass>
11995 23:07:11.909331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass
11997 23:07:11.953201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass>
11998 23:07:11.953529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass
12000 23:07:11.998485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass>
12001 23:07:11.998800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass
12003 23:07:12.043487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass>
12004 23:07:12.043764 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass
12006 23:07:12.088321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass>
12007 23:07:12.088607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass
12009 23:07:12.132294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass>
12010 23:07:12.132580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass
12012 23:07:12.176359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass>
12013 23:07:12.176663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass
12015 23:07:12.218128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass>
12016 23:07:12.218401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass
12018 23:07:12.254607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip>
12019 23:07:12.254877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip
12021 23:07:12.302245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip
12023 23:07:12.305568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip>
12024 23:07:12.350113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_za RESULT=pass>
12025 23:07:12.350391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_za RESULT=pass
12027 23:07:12.389939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_vl RESULT=skip>
12028 23:07:12.390212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_vl RESULT=skip
12030 23:07:12.435206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ssve_regs RESULT=skip>
12031 23:07:12.435470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ssve_regs RESULT=skip
12033 23:07:12.482171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_regs RESULT=skip>
12034 23:07:12.482465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_regs RESULT=skip
12036 23:07:12.526255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_vl RESULT=skip>
12037 23:07:12.526523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_vl RESULT=skip
12039 23:07:12.565002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_no_regs RESULT=skip>
12040 23:07:12.565268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_no_regs RESULT=skip
12042 23:07:12.600292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_regs RESULT=skip>
12043 23:07:12.600568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_regs RESULT=skip
12045 23:07:12.641956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
12047 23:07:12.644953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
12048 23:07:12.691075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
12050 23:07:12.694232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
12051 23:07:12.742069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_generic_pauth_not_enabled RESULT=skip>
12052 23:07:12.742344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_generic_pauth_not_enabled RESULT=skip
12054 23:07:12.777367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
12056 23:07:12.780462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
12057 23:07:12.818245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
12059 23:07:12.821061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
12060 23:07:12.859011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
12061 23:07:12.859283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
12063 23:07:12.905199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_generic_pauth_not_enabled RESULT=skip>
12064 23:07:12.905484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_generic_pauth_not_enabled RESULT=skip
12066 23:07:12.946767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac RESULT=pass>
12067 23:07:12.947040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac RESULT=pass
12069 23:07:12.989493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass>
12070 23:07:12.989826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass
12072 23:07:13.030395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass>
12073 23:07:13.030662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass
12075 23:07:13.070583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass>
12076 23:07:13.070851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass
12078 23:07:13.107741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass>
12079 23:07:13.108010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass
12081 23:07:13.142290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass>
12082 23:07:13.142557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass
12084 23:07:13.183595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass>
12085 23:07:13.183871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass
12087 23:07:13.226893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass>
12088 23:07:13.227158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass
12090 23:07:13.270782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass>
12091 23:07:13.271034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass
12093 23:07:13.314312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass>
12094 23:07:13.314584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass
12096 23:07:13.353364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass>
12097 23:07:13.353633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass
12099 23:07:13.397086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass>
12100 23:07:13.397367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass
12102 23:07:13.443661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass>
12103 23:07:13.443985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass
12105 23:07:13.490001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass>
12106 23:07:13.490298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass
12108 23:07:13.532389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass>
12109 23:07:13.532657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass
12111 23:07:13.573502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass>
12112 23:07:13.573811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass
12114 23:07:13.620555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass>
12115 23:07:13.620827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass
12117 23:07:13.668586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress RESULT=pass>
12118 23:07:13.668846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress RESULT=pass
12120 23:07:13.718642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_sve_not_available RESULT=skip>
12121 23:07:13.718916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_sve_not_available RESULT=skip
12123 23:07:13.760671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace RESULT=skip>
12124 23:07:13.760950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace RESULT=skip
12126 23:07:13.805232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls_sve_not_available RESULT=skip>
12127 23:07:13.805509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls_sve_not_available RESULT=skip
12129 23:07:13.841416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip>
12130 23:07:13.841676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip
12132 23:07:13.888979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12133 23:07:13.889313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12135 23:07:13.933542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12136 23:07:13.933840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12138 23:07:13.975507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12139 23:07:13.975786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12141 23:07:14.024057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12142 23:07:14.024329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12144 23:07:14.073377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12145 23:07:14.073650 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12147 23:07:14.118361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12148 23:07:14.118627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12150 23:07:14.165446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12151 23:07:14.165713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12153 23:07:14.213135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12154 23:07:14.213411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12156 23:07:14.261799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12157 23:07:14.262099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12159 23:07:14.308512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12160 23:07:14.308788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12162 23:07:14.354069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12163 23:07:14.354333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12165 23:07:14.398897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12166 23:07:14.399166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12168 23:07:14.441645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12169 23:07:14.441933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12171 23:07:14.479125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12172 23:07:14.479390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12174 23:07:14.514138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12175 23:07:14.514399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12177 23:07:14.556838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12178 23:07:14.557103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12180 23:07:14.603655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12181 23:07:14.603930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12183 23:07:14.640616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12184 23:07:14.640871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12186 23:07:14.681748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12187 23:07:14.682014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12189 23:07:14.724370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12190 23:07:14.724667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12192 23:07:14.759978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg RESULT=pass>
12193 23:07:14.760237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg RESULT=pass
12195 23:07:14.803980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass>
12196 23:07:14.804251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass
12198 23:07:14.848028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork RESULT=pass>
12199 23:07:14.848291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork RESULT=pass
12201 23:07:14.889362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_sme_not_available RESULT=skip>
12202 23:07:14.889628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_sme_not_available RESULT=skip
12204 23:07:14.923863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace RESULT=skip>
12205 23:07:14.924130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace RESULT=skip
12207 23:07:14.959796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip>
12208 23:07:14.960062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip
12210 23:07:14.993283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory RESULT=skip>
12211 23:07:14.993554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory RESULT=skip
12213 23:07:15.029021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip
12215 23:07:15.032450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip>
12216 23:07:15.066823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_ksm_options RESULT=skip>
12217 23:07:15.067085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_ksm_options RESULT=skip
12219 23:07:15.109423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options RESULT=skip>
12220 23:07:15.109716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options RESULT=skip
12222 23:07:15.157036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass>
12223 23:07:15.157301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass
12225 23:07:15.196998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass>
12226 23:07:15.197267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass
12228 23:07:15.237864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_sync RESULT=skip>
12229 23:07:15.238157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_sync RESULT=skip
12231 23:07:15.277658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_async RESULT=skip>
12232 23:07:15.277955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_async RESULT=skip
12234 23:07:15.314512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_sync_async RESULT=skip
12236 23:07:15.317204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_sync_async RESULT=skip>
12237 23:07:15.358381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl RESULT=pass>
12238 23:07:15.358649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl RESULT=pass
12240 23:07:15.400660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip>
12241 23:07:15.400979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip
12243 23:07:15.442495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem RESULT=skip>
12244 23:07:15.442776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem RESULT=skip
12246 23:07:15.485299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip>
12247 23:07:15.485630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip
12249 23:07:15.523297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip>
12250 23:07:15.523633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip
12252 23:07:15.564797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip>
12253 23:07:15.565102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip
12255 23:07:15.602579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip>
12256 23:07:15.602881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip
12258 23:07:15.645236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip>
12259 23:07:15.645539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip
12261 23:07:15.683616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip>
12262 23:07:15.683913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip
12264 23:07:15.724924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip>
12265 23:07:15.725221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip
12267 23:07:15.763385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip>
12268 23:07:15.763675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip
12270 23:07:15.802947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip>
12271 23:07:15.803212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip
12273 23:07:15.845132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip>
12274 23:07:15.845385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip
12276 23:07:15.888429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip>
12277 23:07:15.888696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip
12279 23:07:15.933471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip>
12280 23:07:15.933754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip
12282 23:07:15.973165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12283 23:07:15.973431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip
12285 23:07:16.011179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12286 23:07:16.011460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip
12288 23:07:16.059155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip>
12289 23:07:16.059426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip
12291 23:07:16.103708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip>
12292 23:07:16.103982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip
12294 23:07:16.147670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip>
12295 23:07:16.147933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip
12297 23:07:16.190400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip>
12298 23:07:16.190670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip
12300 23:07:16.232020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest RESULT=pass>
12301 23:07:16.232282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest RESULT=pass
12303 23:07:16.280311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip>
12304 23:07:16.280632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip
12306 23:07:16.323244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip>
12307 23:07:16.323512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip
12309 23:07:16.366618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip>
12310 23:07:16.366912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip
12312 23:07:16.413728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip>
12313 23:07:16.414001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip
12315 23:07:16.459415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip>
12316 23:07:16.459679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip
12318 23:07:16.497569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip>
12319 23:07:16.497873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip
12321 23:07:16.545697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip>
12322 23:07:16.545966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip
12324 23:07:16.586825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip>
12325 23:07:16.587093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip
12327 23:07:16.627416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip>
12328 23:07:16.627683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip
12330 23:07:16.670370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip>
12331 23:07:16.670661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip
12333 23:07:16.711535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip>
12334 23:07:16.711832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip
12336 23:07:16.759457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip>
12337 23:07:16.759772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip
12339 23:07:16.800592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12340 23:07:16.800866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip
12342 23:07:16.845693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12343 23:07:16.845964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip
12345 23:07:16.889572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip>
12346 23:07:16.889909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip
12348 23:07:16.935955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip>
12349 23:07:16.936223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip
12351 23:07:16.984614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip>
12352 23:07:16.984933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip
12354 23:07:17.035732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip>
12355 23:07:17.036031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip
12357 23:07:17.078980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest RESULT=pass>
12358 23:07:17.079269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest RESULT=pass
12360 23:07:17.130988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass>
12361 23:07:17.131299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass
12363 23:07:17.172842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_rng RESULT=skip>
12364 23:07:17.173134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_rng RESULT=skip
12366 23:07:17.217343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass>
12367 23:07:17.217618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass
12369 23:07:17.257004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass>
12370 23:07:17.257299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass
12372 23:07:17.304934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass>
12373 23:07:17.305207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass
12375 23:07:17.349571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass>
12376 23:07:17.349871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass
12378 23:07:17.401116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass>
12379 23:07:17.401417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass
12381 23:07:17.444633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve_2 RESULT=skip>
12382 23:07:17.444892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve_2 RESULT=skip
12384 23:07:17.493320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass>
12385 23:07:17.493635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass
12387 23:07:17.537951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve_aes RESULT=skip>
12388 23:07:17.538245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve_aes RESULT=skip
12390 23:07:17.589787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass>
12391 23:07:17.590088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass
12393 23:07:17.633217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_pmull RESULT=skip>
12394 23:07:17.633507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_pmull RESULT=skip
12396 23:07:17.674233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass>
12397 23:07:17.674520 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass
12399 23:07:17.723194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_bitperm RESULT=skip>
12400 23:07:17.723474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_bitperm RESULT=skip
12402 23:07:17.764171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass>
12403 23:07:17.764436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass
12405 23:07:17.806245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_sha3 RESULT=skip
12407 23:07:17.809393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_sha3 RESULT=skip>
12408 23:07:17.855983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass>
12409 23:07:17.856253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass
12411 23:07:17.899629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_sm4 RESULT=skip>
12412 23:07:17.899921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_sm4 RESULT=skip
12414 23:07:17.948455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass>
12415 23:07:17.948754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass
12417 23:07:17.990604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_i8mm RESULT=skip
12419 23:07:17.994097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_i8mm RESULT=skip>
12420 23:07:18.037521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass>
12421 23:07:18.037828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass
12423 23:07:18.085110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_f32mm RESULT=skip>
12424 23:07:18.085391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_f32mm RESULT=skip
12426 23:07:18.129156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass>
12427 23:07:18.129445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass
12429 23:07:18.176526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_f64mm RESULT=skip>
12430 23:07:18.176797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_f64mm RESULT=skip
12432 23:07:18.223738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass>
12433 23:07:18.224034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass
12435 23:07:18.267604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_bf16 RESULT=skip
12437 23:07:18.270982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_bf16 RESULT=skip>
12438 23:07:18.317139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass>
12439 23:07:18.317445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass
12441 23:07:18.364500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_ebf16 RESULT=skip>
12442 23:07:18.364791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_ebf16 RESULT=skip
12444 23:07:18.410028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap RESULT=pass>
12445 23:07:18.410304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap RESULT=pass
12447 23:07:18.454628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass
12449 23:07:18.457651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass>
12450 23:07:18.503584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass
12452 23:07:18.506348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass>
12453 23:07:18.549716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass
12455 23:07:18.552807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass>
12456 23:07:18.594036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass>
12457 23:07:18.594325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass
12459 23:07:18.638947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass>
12460 23:07:18.639222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass
12462 23:07:18.678271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass>
12463 23:07:18.678529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass
12465 23:07:18.724947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass>
12466 23:07:18.725217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass
12468 23:07:18.762389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace RESULT=pass>
12469 23:07:18.762658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace RESULT=pass
12471 23:07:18.810544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass>
12472 23:07:18.810809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass
12474 23:07:18.853328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass>
12475 23:07:18.853614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass
12477 23:07:18.892878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi RESULT=pass>
12478 23:07:18.893142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi RESULT=pass
12480 23:07:18.938952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12481 23:07:18.939213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12483 23:07:18.975813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12484 23:07:18.976083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12486 23:07:19.012408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12487 23:07:19.012681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12489 23:07:19.045978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12490 23:07:19.046237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12492 23:07:19.079595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12493 23:07:19.079855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12495 23:07:19.118564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2 RESULT=pass>
12496 23:07:19.118660 + set +x
12497 23:07:19.118897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2 RESULT=pass
12499 23:07:19.125028 <LAVA_SIGNAL_ENDRUN 1_kselftest-arm64 12154385_1.6.2.3.5>
12500 23:07:19.125280 Received signal: <ENDRUN> 1_kselftest-arm64 12154385_1.6.2.3.5
12501 23:07:19.125353 Ending use of test pattern.
12502 23:07:19.125413 Ending test lava.1_kselftest-arm64 (12154385_1.6.2.3.5), duration 30.70
12504 23:07:19.128110 <LAVA_TEST_RUNNER EXIT>
12505 23:07:19.128361 ok: lava_test_shell seems to have completed
12506 23:07:19.129325 arm64_btitest: pass
arm64_btitest_bti_c_func_call_using_blr: skip
arm64_btitest_bti_c_func_call_using_br_x0: skip
arm64_btitest_bti_c_func_call_using_br_x16: skip
arm64_btitest_bti_j_func_call_using_blr: skip
arm64_btitest_bti_j_func_call_using_br_x0: skip
arm64_btitest_bti_j_func_call_using_br_x16: skip
arm64_btitest_bti_jc_func_call_using_blr: skip
arm64_btitest_bti_jc_func_call_using_br_x0: skip
arm64_btitest_bti_jc_func_call_using_br_x16: skip
arm64_btitest_bti_none_func_call_using_blr: skip
arm64_btitest_bti_none_func_call_using_br_x0: skip
arm64_btitest_bti_none_func_call_using_br_x16: skip
arm64_btitest_nohint_func_call_using_blr: skip
arm64_btitest_nohint_func_call_using_br_x0: skip
arm64_btitest_nohint_func_call_using_br_x16: skip
arm64_btitest_paciasp_func_call_using_blr: skip
arm64_btitest_paciasp_func_call_using_br_x0: skip
arm64_btitest_paciasp_func_call_using_br_x16: skip
arm64_check_buffer_fill: skip
arm64_check_child_memory: skip
arm64_check_gcr_el1_cswitch: skip
arm64_check_ksm_options: skip
arm64_check_mmap_options: skip
arm64_check_prctl: pass
arm64_check_prctl_NONE: pass
arm64_check_prctl_async: skip
arm64_check_prctl_check_basic_read: pass
arm64_check_prctl_sync: skip
arm64_check_prctl_sync_async: skip
arm64_check_tags_inclusion: skip
arm64_check_user_mem: skip
arm64_fake_sigreturn_bad_magic: pass
arm64_fake_sigreturn_bad_size: pass
arm64_fake_sigreturn_bad_size_for_magic0: pass
arm64_fake_sigreturn_duplicated_fpsimd: pass
arm64_fake_sigreturn_misaligned_sp: pass
arm64_fake_sigreturn_missing_fpsimd: pass
arm64_fake_sigreturn_sme_change_vl: skip
arm64_fake_sigreturn_sve_change_vl: skip
arm64_fp-stress: pass
arm64_fp-stress_FPSIMD-0-0: pass
arm64_fp-stress_FPSIMD-0-1: pass
arm64_fp-stress_FPSIMD-1-0: pass
arm64_fp-stress_FPSIMD-1-1: pass
arm64_fp-stress_FPSIMD-2-0: pass
arm64_fp-stress_FPSIMD-2-1: pass
arm64_fp-stress_FPSIMD-3-0: pass
arm64_fp-stress_FPSIMD-3-1: pass
arm64_fp-stress_FPSIMD-4-0: pass
arm64_fp-stress_FPSIMD-4-1: pass
arm64_fp-stress_FPSIMD-5-0: pass
arm64_fp-stress_FPSIMD-5-1: pass
arm64_fp-stress_FPSIMD-6-0: pass
arm64_fp-stress_FPSIMD-6-1: pass
arm64_fp-stress_FPSIMD-7-0: pass
arm64_fp-stress_FPSIMD-7-1: pass
arm64_hwcap: pass
arm64_hwcap_cpuinfo_match_RNG: pass
arm64_hwcap_cpuinfo_match_SME: pass
arm64_hwcap_cpuinfo_match_SVE: pass
arm64_hwcap_cpuinfo_match_SVE2_BF16: pass
arm64_hwcap_cpuinfo_match_SVE2_BITPERM: pass
arm64_hwcap_cpuinfo_match_SVE2_EBF16: pass
arm64_hwcap_cpuinfo_match_SVE2_F32MM: pass
arm64_hwcap_cpuinfo_match_SVE2_F64MM: pass
arm64_hwcap_cpuinfo_match_SVE2_I8MM: pass
arm64_hwcap_cpuinfo_match_SVE2_PMULL: pass
arm64_hwcap_cpuinfo_match_SVE2_SHA3: pass
arm64_hwcap_cpuinfo_match_SVE2_SM4: pass
arm64_hwcap_cpuinfo_match_SVE_2: pass
arm64_hwcap_cpuinfo_match_SVE_AES: pass
arm64_hwcap_sigill_SME: pass
arm64_hwcap_sigill_SVE: pass
arm64_hwcap_sigill_rng: skip
arm64_hwcap_sigill_sve2_bf16: skip
arm64_hwcap_sigill_sve2_bitperm: skip
arm64_hwcap_sigill_sve2_ebf16: skip
arm64_hwcap_sigill_sve2_f32mm: skip
arm64_hwcap_sigill_sve2_f64mm: skip
arm64_hwcap_sigill_sve2_i8mm: skip
arm64_hwcap_sigill_sve2_pmull: skip
arm64_hwcap_sigill_sve2_sha3: skip
arm64_hwcap_sigill_sve2_sm4: skip
arm64_hwcap_sigill_sve_2: skip
arm64_hwcap_sigill_sve_aes: skip
arm64_mangle_pstate_invalid_compat_toggle: pass
arm64_mangle_pstate_invalid_daif_bits: pass
arm64_mangle_pstate_invalid_mode_el1h: pass
arm64_mangle_pstate_invalid_mode_el1t: pass
arm64_mangle_pstate_invalid_mode_el2h: pass
arm64_mangle_pstate_invalid_mode_el2t: pass
arm64_mangle_pstate_invalid_mode_el3h: pass
arm64_mangle_pstate_invalid_mode_el3t: pass
arm64_nobtitest: pass
arm64_nobtitest_bti_c_func_call_using_blr: skip
arm64_nobtitest_bti_c_func_call_using_br_x0: skip
arm64_nobtitest_bti_c_func_call_using_br_x16: skip
arm64_nobtitest_bti_j_func_call_using_blr: skip
arm64_nobtitest_bti_j_func_call_using_br_x0: skip
arm64_nobtitest_bti_j_func_call_using_br_x16: skip
arm64_nobtitest_bti_jc_func_call_using_blr: skip
arm64_nobtitest_bti_jc_func_call_using_br_x0: skip
arm64_nobtitest_bti_jc_func_call_using_br_x16: skip
arm64_nobtitest_bti_none_func_call_using_blr: skip
arm64_nobtitest_bti_none_func_call_using_br_x0: skip
arm64_nobtitest_bti_none_func_call_using_br_x16: skip
arm64_nobtitest_nohint_func_call_using_blr: skip
arm64_nobtitest_nohint_func_call_using_br_x0: skip
arm64_nobtitest_nohint_func_call_using_br_x16: skip
arm64_nobtitest_paciasp_func_call_using_blr: skip
arm64_nobtitest_paciasp_func_call_using_br_x0: skip
arm64_nobtitest_paciasp_func_call_using_br_x16: skip
arm64_pac: pass
arm64_pac_generic_pauth_not_enabled: skip
arm64_pac_pauth_not_enabled: skip
arm64_ptrace: pass
arm64_ptrace_count_tpidrs: pass
arm64_ptrace_read_tpidr_one: pass
arm64_ptrace_tpidr2_read: pass
arm64_ptrace_tpidr2_write: pass
arm64_ptrace_verify_tpidr_one: pass
arm64_ptrace_write_tpidr_one: pass
arm64_ptrace_write_tpidr_only: pass
arm64_run_tags_test_sh: pass
arm64_sme_trap_no_sm: skip
arm64_sme_trap_non_streaming: skip
arm64_sme_trap_za: pass
arm64_sme_vl: skip
arm64_ssve_regs: skip
arm64_sve-probe-vls: skip
arm64_sve-probe-vls_sve_not_available: skip
arm64_sve-ptrace: skip
arm64_sve-ptrace_sve_not_available: skip
arm64_sve_regs: skip
arm64_sve_vl: skip
arm64_syscall-abi: pass
arm64_syscall-abi_getpid_FPSIMD: pass
arm64_syscall-abi_sched_yield_FPSIMD: pass
arm64_tags_test: pass
arm64_tpidr2: pass
arm64_tpidr2_skipped_TPIDR2_not_supported: pass
arm64_vec-syscfg: pass
arm64_vec-syscfg_sme_not_supported: skip
arm64_vec-syscfg_sve_not_supported: skip
arm64_za-fork: pass
arm64_za-fork_skipped: pass
arm64_za-ptrace: skip
arm64_za-ptrace_sme_not_available: skip
arm64_za_no_regs: skip
arm64_za_regs: skip
shardfile-arm64: pass
12507 23:07:19.129466 end: 3.1 lava-test-shell (duration 00:00:32) [common]
12508 23:07:19.129551 end: 3 lava-test-retry (duration 00:00:32) [common]
12509 23:07:19.129647 start: 4 finalize (timeout 00:07:17) [common]
12510 23:07:19.129735 start: 4.1 power-off (timeout 00:00:30) [common]
12511 23:07:19.129884 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
12512 23:07:19.208549 >> Command sent successfully.
12513 23:07:19.211004 Returned 0 in 0 seconds
12514 23:07:19.311398 end: 4.1 power-off (duration 00:00:00) [common]
12516 23:07:19.311716 start: 4.2 read-feedback (timeout 00:07:16) [common]
12517 23:07:19.311985 Listened to connection for namespace 'common' for up to 1s
12518 23:07:20.312928 Finalising connection for namespace 'common'
12519 23:07:20.313112 Disconnecting from shell: Finalise
12520 23:07:20.313195 / #
12521 23:07:20.413524 end: 4.2 read-feedback (duration 00:00:01) [common]
12522 23:07:20.413788 end: 4 finalize (duration 00:00:01) [common]
12523 23:07:20.413915 Cleaning after the job
12524 23:07:20.414018 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12154385/tftp-deploy-cllkt166/ramdisk
12525 23:07:20.416503 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12154385/tftp-deploy-cllkt166/kernel
12526 23:07:20.428964 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12154385/tftp-deploy-cllkt166/dtb
12527 23:07:20.429145 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12154385/tftp-deploy-cllkt166/nfsrootfs
12528 23:07:20.520068 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12154385/tftp-deploy-cllkt166/modules
12529 23:07:20.527636 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12154385
12530 23:07:21.188293 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12154385
12531 23:07:21.188472 Job finished correctly