Boot log: mt8192-asurada-spherion-r0
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 26
- Kernel Errors: 38
- Errors: 0
1 23:06:14.166700 lava-dispatcher, installed at version: 2023.10
2 23:06:14.166914 start: 0 validate
3 23:06:14.167045 Start time: 2023-12-01 23:06:14.167037+00:00 (UTC)
4 23:06:14.167164 Using caching service: 'http://localhost/cache/?uri=%s'
5 23:06:14.167296 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 23:06:14.437854 Using caching service: 'http://localhost/cache/?uri=%s'
7 23:06:14.438551 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.64-cip10%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 23:06:14.709901 Using caching service: 'http://localhost/cache/?uri=%s'
9 23:06:14.710631 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.64-cip10%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 23:06:14.979139 Using caching service: 'http://localhost/cache/?uri=%s'
11 23:06:14.979303 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 23:06:15.237267 Using caching service: 'http://localhost/cache/?uri=%s'
13 23:06:15.237450 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.64-cip10%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 23:06:15.503903 validate duration: 1.34
16 23:06:15.504150 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 23:06:15.504320 start: 1.1 download-retry (timeout 00:10:00) [common]
18 23:06:15.504407 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 23:06:15.504528 Not decompressing ramdisk as can be used compressed.
20 23:06:15.504611 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/initrd.cpio.gz
21 23:06:15.504674 saving as /var/lib/lava/dispatcher/tmp/12154441/tftp-deploy-apkqk93d/ramdisk/initrd.cpio.gz
22 23:06:15.504737 total size: 4665395 (4 MB)
23 23:06:15.505784 progress 0 % (0 MB)
24 23:06:15.507338 progress 5 % (0 MB)
25 23:06:15.508658 progress 10 % (0 MB)
26 23:06:15.509936 progress 15 % (0 MB)
27 23:06:15.511189 progress 20 % (0 MB)
28 23:06:15.512437 progress 25 % (1 MB)
29 23:06:15.513714 progress 30 % (1 MB)
30 23:06:15.515027 progress 35 % (1 MB)
31 23:06:15.516301 progress 40 % (1 MB)
32 23:06:15.517705 progress 45 % (2 MB)
33 23:06:15.518941 progress 50 % (2 MB)
34 23:06:15.520179 progress 55 % (2 MB)
35 23:06:15.521447 progress 60 % (2 MB)
36 23:06:15.522703 progress 65 % (2 MB)
37 23:06:15.523944 progress 70 % (3 MB)
38 23:06:15.525208 progress 75 % (3 MB)
39 23:06:15.526453 progress 80 % (3 MB)
40 23:06:15.527869 progress 85 % (3 MB)
41 23:06:15.529131 progress 90 % (4 MB)
42 23:06:15.530391 progress 95 % (4 MB)
43 23:06:15.531641 progress 100 % (4 MB)
44 23:06:15.531790 4 MB downloaded in 0.03 s (164.46 MB/s)
45 23:06:15.531937 end: 1.1.1 http-download (duration 00:00:00) [common]
47 23:06:15.532170 end: 1.1 download-retry (duration 00:00:00) [common]
48 23:06:15.532307 start: 1.2 download-retry (timeout 00:10:00) [common]
49 23:06:15.532391 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 23:06:15.532519 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.64-cip10/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 23:06:15.532585 saving as /var/lib/lava/dispatcher/tmp/12154441/tftp-deploy-apkqk93d/kernel/Image
52 23:06:15.532644 total size: 49172992 (46 MB)
53 23:06:15.532702 No compression specified
54 23:06:15.533732 progress 0 % (0 MB)
55 23:06:15.546585 progress 5 % (2 MB)
56 23:06:15.559254 progress 10 % (4 MB)
57 23:06:15.572440 progress 15 % (7 MB)
58 23:06:15.585198 progress 20 % (9 MB)
59 23:06:15.598029 progress 25 % (11 MB)
60 23:06:15.610773 progress 30 % (14 MB)
61 23:06:15.623663 progress 35 % (16 MB)
62 23:06:15.636639 progress 40 % (18 MB)
63 23:06:15.649505 progress 45 % (21 MB)
64 23:06:15.662368 progress 50 % (23 MB)
65 23:06:15.675245 progress 55 % (25 MB)
66 23:06:15.688097 progress 60 % (28 MB)
67 23:06:15.700897 progress 65 % (30 MB)
68 23:06:15.713566 progress 70 % (32 MB)
69 23:06:15.726395 progress 75 % (35 MB)
70 23:06:15.739207 progress 80 % (37 MB)
71 23:06:15.751947 progress 85 % (39 MB)
72 23:06:15.764869 progress 90 % (42 MB)
73 23:06:15.777420 progress 95 % (44 MB)
74 23:06:15.790034 progress 100 % (46 MB)
75 23:06:15.790244 46 MB downloaded in 0.26 s (182.05 MB/s)
76 23:06:15.790390 end: 1.2.1 http-download (duration 00:00:00) [common]
78 23:06:15.790623 end: 1.2 download-retry (duration 00:00:00) [common]
79 23:06:15.790709 start: 1.3 download-retry (timeout 00:10:00) [common]
80 23:06:15.790796 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 23:06:15.790933 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.64-cip10/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 23:06:15.791003 saving as /var/lib/lava/dispatcher/tmp/12154441/tftp-deploy-apkqk93d/dtb/mt8192-asurada-spherion-r0.dtb
83 23:06:15.791063 total size: 47278 (0 MB)
84 23:06:15.791122 No compression specified
85 23:06:15.792182 progress 69 % (0 MB)
86 23:06:15.792497 progress 100 % (0 MB)
87 23:06:15.792650 0 MB downloaded in 0.00 s (28.46 MB/s)
88 23:06:15.792768 end: 1.3.1 http-download (duration 00:00:00) [common]
90 23:06:15.792985 end: 1.3 download-retry (duration 00:00:00) [common]
91 23:06:15.793074 start: 1.4 download-retry (timeout 00:10:00) [common]
92 23:06:15.793156 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 23:06:15.793266 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/full.rootfs.tar.xz
94 23:06:15.793332 saving as /var/lib/lava/dispatcher/tmp/12154441/tftp-deploy-apkqk93d/nfsrootfs/full.rootfs.tar
95 23:06:15.793391 total size: 200813988 (191 MB)
96 23:06:15.793450 Using unxz to decompress xz
97 23:06:15.797511 progress 0 % (0 MB)
98 23:06:16.330975 progress 5 % (9 MB)
99 23:06:16.849597 progress 10 % (19 MB)
100 23:06:17.439922 progress 15 % (28 MB)
101 23:06:17.816294 progress 20 % (38 MB)
102 23:06:18.141128 progress 25 % (47 MB)
103 23:06:18.741528 progress 30 % (57 MB)
104 23:06:19.304384 progress 35 % (67 MB)
105 23:06:19.910644 progress 40 % (76 MB)
106 23:06:20.470392 progress 45 % (86 MB)
107 23:06:21.064081 progress 50 % (95 MB)
108 23:06:21.692577 progress 55 % (105 MB)
109 23:06:22.349302 progress 60 % (114 MB)
110 23:06:22.465225 progress 65 % (124 MB)
111 23:06:22.603090 progress 70 % (134 MB)
112 23:06:22.697828 progress 75 % (143 MB)
113 23:06:22.768631 progress 80 % (153 MB)
114 23:06:22.836615 progress 85 % (162 MB)
115 23:06:22.936725 progress 90 % (172 MB)
116 23:06:23.213651 progress 95 % (181 MB)
117 23:06:23.800680 progress 100 % (191 MB)
118 23:06:23.805957 191 MB downloaded in 8.01 s (23.90 MB/s)
119 23:06:23.806240 end: 1.4.1 http-download (duration 00:00:08) [common]
121 23:06:23.806775 end: 1.4 download-retry (duration 00:00:08) [common]
122 23:06:23.806877 start: 1.5 download-retry (timeout 00:09:52) [common]
123 23:06:23.806999 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 23:06:23.807199 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.64-cip10/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 23:06:23.807302 saving as /var/lib/lava/dispatcher/tmp/12154441/tftp-deploy-apkqk93d/modules/modules.tar
126 23:06:23.807400 total size: 8616152 (8 MB)
127 23:06:23.807497 Using unxz to decompress xz
128 23:06:23.811838 progress 0 % (0 MB)
129 23:06:23.832734 progress 5 % (0 MB)
130 23:06:23.856627 progress 10 % (0 MB)
131 23:06:23.880166 progress 15 % (1 MB)
132 23:06:23.903893 progress 20 % (1 MB)
133 23:06:23.928009 progress 25 % (2 MB)
134 23:06:23.953929 progress 30 % (2 MB)
135 23:06:23.979897 progress 35 % (2 MB)
136 23:06:24.003266 progress 40 % (3 MB)
137 23:06:24.027734 progress 45 % (3 MB)
138 23:06:24.053053 progress 50 % (4 MB)
139 23:06:24.077344 progress 55 % (4 MB)
140 23:06:24.102129 progress 60 % (4 MB)
141 23:06:24.128041 progress 65 % (5 MB)
142 23:06:24.156149 progress 70 % (5 MB)
143 23:06:24.180087 progress 75 % (6 MB)
144 23:06:24.207939 progress 80 % (6 MB)
145 23:06:24.233545 progress 85 % (7 MB)
146 23:06:24.258824 progress 90 % (7 MB)
147 23:06:24.288574 progress 95 % (7 MB)
148 23:06:24.316309 progress 100 % (8 MB)
149 23:06:24.322556 8 MB downloaded in 0.52 s (15.95 MB/s)
150 23:06:24.322819 end: 1.5.1 http-download (duration 00:00:01) [common]
152 23:06:24.323082 end: 1.5 download-retry (duration 00:00:01) [common]
153 23:06:24.323175 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 23:06:24.323271 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 23:06:27.855278 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12154441/extract-nfsrootfs-32vd6yh1
156 23:06:27.855468 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 23:06:27.855570 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 23:06:27.855742 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12154441/lava-overlay-cmkikjoj
159 23:06:27.855876 makedir: /var/lib/lava/dispatcher/tmp/12154441/lava-overlay-cmkikjoj/lava-12154441/bin
160 23:06:27.855978 makedir: /var/lib/lava/dispatcher/tmp/12154441/lava-overlay-cmkikjoj/lava-12154441/tests
161 23:06:27.856076 makedir: /var/lib/lava/dispatcher/tmp/12154441/lava-overlay-cmkikjoj/lava-12154441/results
162 23:06:27.856179 Creating /var/lib/lava/dispatcher/tmp/12154441/lava-overlay-cmkikjoj/lava-12154441/bin/lava-add-keys
163 23:06:27.856333 Creating /var/lib/lava/dispatcher/tmp/12154441/lava-overlay-cmkikjoj/lava-12154441/bin/lava-add-sources
164 23:06:27.856461 Creating /var/lib/lava/dispatcher/tmp/12154441/lava-overlay-cmkikjoj/lava-12154441/bin/lava-background-process-start
165 23:06:27.856589 Creating /var/lib/lava/dispatcher/tmp/12154441/lava-overlay-cmkikjoj/lava-12154441/bin/lava-background-process-stop
166 23:06:27.856714 Creating /var/lib/lava/dispatcher/tmp/12154441/lava-overlay-cmkikjoj/lava-12154441/bin/lava-common-functions
167 23:06:27.856838 Creating /var/lib/lava/dispatcher/tmp/12154441/lava-overlay-cmkikjoj/lava-12154441/bin/lava-echo-ipv4
168 23:06:27.856962 Creating /var/lib/lava/dispatcher/tmp/12154441/lava-overlay-cmkikjoj/lava-12154441/bin/lava-install-packages
169 23:06:27.857130 Creating /var/lib/lava/dispatcher/tmp/12154441/lava-overlay-cmkikjoj/lava-12154441/bin/lava-installed-packages
170 23:06:27.857320 Creating /var/lib/lava/dispatcher/tmp/12154441/lava-overlay-cmkikjoj/lava-12154441/bin/lava-os-build
171 23:06:27.857491 Creating /var/lib/lava/dispatcher/tmp/12154441/lava-overlay-cmkikjoj/lava-12154441/bin/lava-probe-channel
172 23:06:27.857615 Creating /var/lib/lava/dispatcher/tmp/12154441/lava-overlay-cmkikjoj/lava-12154441/bin/lava-probe-ip
173 23:06:27.857832 Creating /var/lib/lava/dispatcher/tmp/12154441/lava-overlay-cmkikjoj/lava-12154441/bin/lava-target-ip
174 23:06:27.857957 Creating /var/lib/lava/dispatcher/tmp/12154441/lava-overlay-cmkikjoj/lava-12154441/bin/lava-target-mac
175 23:06:27.858080 Creating /var/lib/lava/dispatcher/tmp/12154441/lava-overlay-cmkikjoj/lava-12154441/bin/lava-target-storage
176 23:06:27.858221 Creating /var/lib/lava/dispatcher/tmp/12154441/lava-overlay-cmkikjoj/lava-12154441/bin/lava-test-case
177 23:06:27.858361 Creating /var/lib/lava/dispatcher/tmp/12154441/lava-overlay-cmkikjoj/lava-12154441/bin/lava-test-event
178 23:06:27.858486 Creating /var/lib/lava/dispatcher/tmp/12154441/lava-overlay-cmkikjoj/lava-12154441/bin/lava-test-feedback
179 23:06:27.858609 Creating /var/lib/lava/dispatcher/tmp/12154441/lava-overlay-cmkikjoj/lava-12154441/bin/lava-test-raise
180 23:06:27.858733 Creating /var/lib/lava/dispatcher/tmp/12154441/lava-overlay-cmkikjoj/lava-12154441/bin/lava-test-reference
181 23:06:27.858857 Creating /var/lib/lava/dispatcher/tmp/12154441/lava-overlay-cmkikjoj/lava-12154441/bin/lava-test-runner
182 23:06:27.858980 Creating /var/lib/lava/dispatcher/tmp/12154441/lava-overlay-cmkikjoj/lava-12154441/bin/lava-test-set
183 23:06:27.859105 Creating /var/lib/lava/dispatcher/tmp/12154441/lava-overlay-cmkikjoj/lava-12154441/bin/lava-test-shell
184 23:06:27.859260 Updating /var/lib/lava/dispatcher/tmp/12154441/lava-overlay-cmkikjoj/lava-12154441/bin/lava-add-keys (debian)
185 23:06:28.032958 Updating /var/lib/lava/dispatcher/tmp/12154441/lava-overlay-cmkikjoj/lava-12154441/bin/lava-add-sources (debian)
186 23:06:28.033278 Updating /var/lib/lava/dispatcher/tmp/12154441/lava-overlay-cmkikjoj/lava-12154441/bin/lava-install-packages (debian)
187 23:06:28.033509 Updating /var/lib/lava/dispatcher/tmp/12154441/lava-overlay-cmkikjoj/lava-12154441/bin/lava-installed-packages (debian)
188 23:06:28.033729 Updating /var/lib/lava/dispatcher/tmp/12154441/lava-overlay-cmkikjoj/lava-12154441/bin/lava-os-build (debian)
189 23:06:28.033920 Creating /var/lib/lava/dispatcher/tmp/12154441/lava-overlay-cmkikjoj/lava-12154441/environment
190 23:06:28.034079 LAVA metadata
191 23:06:28.034192 - LAVA_JOB_ID=12154441
192 23:06:28.034290 - LAVA_DISPATCHER_IP=192.168.201.1
193 23:06:28.034463 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:47) [common]
194 23:06:28.034567 skipped lava-vland-overlay
195 23:06:28.034686 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 23:06:28.034809 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:47) [common]
197 23:06:28.034902 skipped lava-multinode-overlay
198 23:06:28.035013 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 23:06:28.035132 start: 1.6.2.3 test-definition (timeout 00:09:47) [common]
200 23:06:28.035247 Loading test definitions
201 23:06:28.035389 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:47) [common]
202 23:06:28.035502 Using /lava-12154441 at stage 0
203 23:06:28.035941 uuid=12154441_1.6.2.3.1 testdef=None
204 23:06:28.036077 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 23:06:28.036217 start: 1.6.2.3.2 test-overlay (timeout 00:09:47) [common]
206 23:06:28.036926 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 23:06:28.037263 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:47) [common]
209 23:06:28.038097 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 23:06:28.038461 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:47) [common]
212 23:06:29.381138 runner path: /var/lib/lava/dispatcher/tmp/12154441/lava-overlay-cmkikjoj/lava-12154441/0/tests/0_timesync-off test_uuid 12154441_1.6.2.3.1
213 23:06:29.382030 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:01) [common]
215 23:06:29.383202 start: 1.6.2.3.5 git-repo-action (timeout 00:09:46) [common]
216 23:06:29.383575 Using /lava-12154441 at stage 0
217 23:06:29.384072 Fetching tests from https://github.com/kernelci/test-definitions.git
218 23:06:29.384561 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/12154441/lava-overlay-cmkikjoj/lava-12154441/0/tests/1_kselftest-dt'
219 23:06:32.948528 Running '/usr/bin/git checkout kernelci.org
220 23:06:33.094842 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12154441/lava-overlay-cmkikjoj/lava-12154441/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
221 23:06:33.095712 uuid=12154441_1.6.2.3.5 testdef=None
222 23:06:33.095874 end: 1.6.2.3.5 git-repo-action (duration 00:00:04) [common]
224 23:06:33.096127 start: 1.6.2.3.6 test-overlay (timeout 00:09:42) [common]
225 23:06:33.096929 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 23:06:33.097157 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:42) [common]
228 23:06:33.098106 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 23:06:33.098338 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:42) [common]
231 23:06:33.099267 runner path: /var/lib/lava/dispatcher/tmp/12154441/lava-overlay-cmkikjoj/lava-12154441/0/tests/1_kselftest-dt test_uuid 12154441_1.6.2.3.5
232 23:06:33.099357 BOARD='mt8192-asurada-spherion-r0'
233 23:06:33.099420 BRANCH='cip'
234 23:06:33.099477 SKIPFILE='/dev/null'
235 23:06:33.099533 SKIP_INSTALL='True'
236 23:06:33.099606 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.64-cip10/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 23:06:33.099684 TST_CASENAME=''
238 23:06:33.099738 TST_CMDFILES='dt'
239 23:06:33.099876 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 23:06:33.100074 Creating lava-test-runner.conf files
242 23:06:33.100137 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12154441/lava-overlay-cmkikjoj/lava-12154441/0 for stage 0
243 23:06:33.100287 - 0_timesync-off
244 23:06:33.100371 - 1_kselftest-dt
245 23:06:33.100466 end: 1.6.2.3 test-definition (duration 00:00:05) [common]
246 23:06:33.100551 start: 1.6.2.4 compress-overlay (timeout 00:09:42) [common]
247 23:06:40.645314 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 23:06:40.645481 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:35) [common]
249 23:06:40.645571 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 23:06:40.645675 end: 1.6.2 lava-overlay (duration 00:00:13) [common]
251 23:06:40.645765 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:35) [common]
252 23:06:40.766804 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 23:06:40.767227 start: 1.6.4 extract-modules (timeout 00:09:35) [common]
254 23:06:40.767345 extracting modules file /var/lib/lava/dispatcher/tmp/12154441/tftp-deploy-apkqk93d/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12154441/extract-nfsrootfs-32vd6yh1
255 23:06:40.988266 extracting modules file /var/lib/lava/dispatcher/tmp/12154441/tftp-deploy-apkqk93d/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12154441/extract-overlay-ramdisk-3cga3tdb/ramdisk
256 23:06:41.214535 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 23:06:41.214712 start: 1.6.5 apply-overlay-tftp (timeout 00:09:34) [common]
258 23:06:41.214807 [common] Applying overlay to NFS
259 23:06:41.214880 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12154441/compress-overlay-ksblci6x/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12154441/extract-nfsrootfs-32vd6yh1
260 23:06:42.137116 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 23:06:42.137290 start: 1.6.6 configure-preseed-file (timeout 00:09:33) [common]
262 23:06:42.137384 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 23:06:42.137471 start: 1.6.7 compress-ramdisk (timeout 00:09:33) [common]
264 23:06:42.137552 Building ramdisk /var/lib/lava/dispatcher/tmp/12154441/extract-overlay-ramdisk-3cga3tdb/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12154441/extract-overlay-ramdisk-3cga3tdb/ramdisk
265 23:06:42.484109 >> 119410 blocks
266 23:06:44.397522 rename /var/lib/lava/dispatcher/tmp/12154441/extract-overlay-ramdisk-3cga3tdb/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12154441/tftp-deploy-apkqk93d/ramdisk/ramdisk.cpio.gz
267 23:06:44.398202 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 23:06:44.398381 start: 1.6.8 prepare-kernel (timeout 00:09:31) [common]
269 23:06:44.398520 start: 1.6.8.1 prepare-fit (timeout 00:09:31) [common]
270 23:06:44.398675 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12154441/tftp-deploy-apkqk93d/kernel/Image'
271 23:06:57.164943 Returned 0 in 12 seconds
272 23:06:57.265933 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12154441/tftp-deploy-apkqk93d/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12154441/tftp-deploy-apkqk93d/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12154441/tftp-deploy-apkqk93d/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12154441/tftp-deploy-apkqk93d/kernel/image.itb
273 23:06:57.629961 output: FIT description: Kernel Image image with one or more FDT blobs
274 23:06:57.630354 output: Created: Fri Dec 1 23:06:57 2023
275 23:06:57.630434 output: Image 0 (kernel-1)
276 23:06:57.630499 output: Description:
277 23:06:57.630561 output: Created: Fri Dec 1 23:06:57 2023
278 23:06:57.630619 output: Type: Kernel Image
279 23:06:57.630674 output: Compression: lzma compressed
280 23:06:57.630731 output: Data Size: 11043984 Bytes = 10785.14 KiB = 10.53 MiB
281 23:06:57.630789 output: Architecture: AArch64
282 23:06:57.630847 output: OS: Linux
283 23:06:57.630901 output: Load Address: 0x00000000
284 23:06:57.630959 output: Entry Point: 0x00000000
285 23:06:57.631020 output: Hash algo: crc32
286 23:06:57.631079 output: Hash value: 36c84243
287 23:06:57.631134 output: Image 1 (fdt-1)
288 23:06:57.631186 output: Description: mt8192-asurada-spherion-r0
289 23:06:57.631239 output: Created: Fri Dec 1 23:06:57 2023
290 23:06:57.631291 output: Type: Flat Device Tree
291 23:06:57.631343 output: Compression: uncompressed
292 23:06:57.631394 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 23:06:57.631446 output: Architecture: AArch64
294 23:06:57.631498 output: Hash algo: crc32
295 23:06:57.631550 output: Hash value: cc4352de
296 23:06:57.631602 output: Image 2 (ramdisk-1)
297 23:06:57.631654 output: Description: unavailable
298 23:06:57.631705 output: Created: Fri Dec 1 23:06:57 2023
299 23:06:57.631757 output: Type: RAMDisk Image
300 23:06:57.631808 output: Compression: Unknown Compression
301 23:06:57.631860 output: Data Size: 17798368 Bytes = 17381.22 KiB = 16.97 MiB
302 23:06:57.631912 output: Architecture: AArch64
303 23:06:57.631965 output: OS: Linux
304 23:06:57.632016 output: Load Address: unavailable
305 23:06:57.632068 output: Entry Point: unavailable
306 23:06:57.632120 output: Hash algo: crc32
307 23:06:57.632172 output: Hash value: 49809528
308 23:06:57.632253 output: Default Configuration: 'conf-1'
309 23:06:57.632320 output: Configuration 0 (conf-1)
310 23:06:57.632372 output: Description: mt8192-asurada-spherion-r0
311 23:06:57.632423 output: Kernel: kernel-1
312 23:06:57.632475 output: Init Ramdisk: ramdisk-1
313 23:06:57.632527 output: FDT: fdt-1
314 23:06:57.632579 output: Loadables: kernel-1
315 23:06:57.632630 output:
316 23:06:57.632828 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
317 23:06:57.632928 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
318 23:06:57.633035 end: 1.6 prepare-tftp-overlay (duration 00:00:33) [common]
319 23:06:57.633133 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:18) [common]
320 23:06:57.633208 No LXC device requested
321 23:06:57.633284 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 23:06:57.633365 start: 1.8 deploy-device-env (timeout 00:09:18) [common]
323 23:06:57.633438 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 23:06:57.633509 Checking files for TFTP limit of 4294967296 bytes.
325 23:06:57.633995 end: 1 tftp-deploy (duration 00:00:42) [common]
326 23:06:57.634093 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 23:06:57.634185 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 23:06:57.634311 substitutions:
329 23:06:57.634379 - {DTB}: 12154441/tftp-deploy-apkqk93d/dtb/mt8192-asurada-spherion-r0.dtb
330 23:06:57.634442 - {INITRD}: 12154441/tftp-deploy-apkqk93d/ramdisk/ramdisk.cpio.gz
331 23:06:57.634500 - {KERNEL}: 12154441/tftp-deploy-apkqk93d/kernel/Image
332 23:06:57.634557 - {LAVA_MAC}: None
333 23:06:57.634612 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12154441/extract-nfsrootfs-32vd6yh1
334 23:06:57.634667 - {NFS_SERVER_IP}: 192.168.201.1
335 23:06:57.634720 - {PRESEED_CONFIG}: None
336 23:06:57.634773 - {PRESEED_LOCAL}: None
337 23:06:57.634826 - {RAMDISK}: 12154441/tftp-deploy-apkqk93d/ramdisk/ramdisk.cpio.gz
338 23:06:57.634879 - {ROOT_PART}: None
339 23:06:57.634932 - {ROOT}: None
340 23:06:57.634985 - {SERVER_IP}: 192.168.201.1
341 23:06:57.635037 - {TEE}: None
342 23:06:57.635090 Parsed boot commands:
343 23:06:57.635142 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 23:06:57.635321 Parsed boot commands: tftpboot 192.168.201.1 12154441/tftp-deploy-apkqk93d/kernel/image.itb 12154441/tftp-deploy-apkqk93d/kernel/cmdline
345 23:06:57.635407 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 23:06:57.635488 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 23:06:57.635580 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 23:06:57.635662 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 23:06:57.635734 Not connected, no need to disconnect.
350 23:06:57.635817 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 23:06:57.635925 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 23:06:57.636004 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
353 23:06:57.640028 Setting prompt string to ['lava-test: # ']
354 23:06:57.640428 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 23:06:57.640533 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 23:06:57.640633 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 23:06:57.640738 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 23:06:57.640971 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
359 23:07:02.787492 >> Command sent successfully.
360 23:07:02.797944 Returned 0 in 5 seconds
361 23:07:02.899189 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 23:07:02.900803 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 23:07:02.901354 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 23:07:02.901926 Setting prompt string to 'Starting depthcharge on Spherion...'
366 23:07:02.902433 Changing prompt to 'Starting depthcharge on Spherion...'
367 23:07:02.902968 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 23:07:02.904786 [Enter `^Ec?' for help]
369 23:07:03.066551 SULT=pass>
370 23:07:03.067155 /lava-12154420/1/../
371 23:07:03.067511 F0: 102B 0000
372 23:07:03.067906
373 23:07:03.070133 F3: 1001 0000 [0200]
374 23:07:03.070535
375 23:07:03.070924 F3: 1001 0000
376 23:07:03.071255
377 23:07:03.071583 F7: 102D 0000
378 23:07:03.071789
379 23:07:03.071966 F1: 0000 0000
380 23:07:03.072127
381 23:07:03.073752 V0: 0000 0000 [0001]
382 23:07:03.074053
383 23:07:03.074291 00: 0007 8000
384 23:07:03.074512
385 23:07:03.077307 01: 0000 0000
386 23:07:03.077555
387 23:07:03.077728 BP: 0C00 0209 [0000]
388 23:07:03.077895
389 23:07:03.080999 G0: 1182 0000
390 23:07:03.081323
391 23:07:03.081626 EC: 0000 0021 [4000]
392 23:07:03.081870
393 23:07:03.084597 S7: 0000 0000 [0000]
394 23:07:03.084883
395 23:07:03.085067 CC: 0000 0000 [0001]
396 23:07:03.085260
397 23:07:03.088154 T0: 0000 0040 [010F]
398 23:07:03.088408
399 23:07:03.088615 Jump to BL
400 23:07:03.088838
401 23:07:03.113625
402 23:07:03.113982
403 23:07:03.114194
404 23:07:03.120738 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 23:07:03.124369 ARM64: Exception handlers installed.
406 23:07:03.127724 ARM64: Testing exception
407 23:07:03.131591 ARM64: Done test exception
408 23:07:03.138883 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 23:07:03.149771 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 23:07:03.156263 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 23:07:03.166573 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 23:07:03.173160 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 23:07:03.179660 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 23:07:03.190525 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 23:07:03.196628 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 23:07:03.216084 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 23:07:03.219018 WDT: Last reset was cold boot
418 23:07:03.222368 SPI1(PAD0) initialized at 2873684 Hz
419 23:07:03.226051 SPI5(PAD0) initialized at 992727 Hz
420 23:07:03.229089 VBOOT: Loading verstage.
421 23:07:03.235810 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 23:07:03.239471 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 23:07:03.242699 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 23:07:03.245888 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 23:07:03.253765 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 23:07:03.260343 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 23:07:03.271588 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
428 23:07:03.272176
429 23:07:03.272681
430 23:07:03.281417 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 23:07:03.284635 ARM64: Exception handlers installed.
432 23:07:03.287752 ARM64: Testing exception
433 23:07:03.288172 ARM64: Done test exception
434 23:07:03.294777 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 23:07:03.298341 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 23:07:03.312701 Probing TPM: . done!
437 23:07:03.313189 TPM ready after 0 ms
438 23:07:03.319465 Connected to device vid:did:rid of 1ae0:0028:00
439 23:07:03.325848 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
440 23:07:03.365575 Initialized TPM device CR50 revision 0
441 23:07:03.377571 tlcl_send_startup: Startup return code is 0
442 23:07:03.377859 TPM: setup succeeded
443 23:07:03.389588 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 23:07:03.398153 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 23:07:03.411406 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 23:07:03.419045 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 23:07:03.422001 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 23:07:03.426943 in-header: 03 07 00 00 08 00 00 00
449 23:07:03.430435 in-data: aa e4 47 04 13 02 00 00
450 23:07:03.433622 Chrome EC: UHEPI supported
451 23:07:03.440920 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 23:07:03.444261 in-header: 03 9d 00 00 08 00 00 00
453 23:07:03.447990 in-data: 10 20 20 08 00 00 00 00
454 23:07:03.448476 Phase 1
455 23:07:03.455350 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 23:07:03.459427 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 23:07:03.466025 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 23:07:03.469777 Recovery requested (1009000e)
459 23:07:03.475561 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 23:07:03.481070 tlcl_extend: response is 0
461 23:07:03.488988 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 23:07:03.494355 tlcl_extend: response is 0
463 23:07:03.501250 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 23:07:03.522405 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 23:07:03.529498 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 23:07:03.529943
467 23:07:03.530414
468 23:07:03.537360 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 23:07:03.541147 ARM64: Exception handlers installed.
470 23:07:03.544232 ARM64: Testing exception
471 23:07:03.547768 ARM64: Done test exception
472 23:07:03.567718 pmic_efuse_setting: Set efuses in 11 msecs
473 23:07:03.571291 pmwrap_interface_init: Select PMIF_VLD_RDY
474 23:07:03.574738 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 23:07:03.582834 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 23:07:03.586567 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 23:07:03.589986 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 23:07:03.597420 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 23:07:03.601052 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 23:07:03.604605 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 23:07:03.611305 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 23:07:03.615126 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 23:07:03.618162 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 23:07:03.624669 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 23:07:03.628006 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 23:07:03.631652 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 23:07:03.638893 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 23:07:03.645335 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 23:07:03.651654 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 23:07:03.655059 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 23:07:03.661740 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 23:07:03.669137 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 23:07:03.673162 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 23:07:03.680539 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 23:07:03.683826 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 23:07:03.690788 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 23:07:03.694217 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 23:07:03.701221 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 23:07:03.707880 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 23:07:03.711146 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 23:07:03.717802 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 23:07:03.721288 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 23:07:03.724982 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 23:07:03.732322 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 23:07:03.735620 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 23:07:03.743005 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 23:07:03.747013 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 23:07:03.750326 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 23:07:03.758316 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 23:07:03.761472 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 23:07:03.764738 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 23:07:03.771531 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 23:07:03.774953 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 23:07:03.778279 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 23:07:03.784643 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 23:07:03.788399 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 23:07:03.791803 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 23:07:03.798107 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 23:07:03.801780 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 23:07:03.804946 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 23:07:03.808479 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 23:07:03.815058 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 23:07:03.818163 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 23:07:03.821470 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 23:07:03.831361 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 23:07:03.838414 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 23:07:03.841337 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 23:07:03.851614 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 23:07:03.858562 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 23:07:03.865074 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 23:07:03.868401 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 23:07:03.871769 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 23:07:03.879715 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x2f
534 23:07:03.886329 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 23:07:03.890411 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
536 23:07:03.896096 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 23:07:03.904766 [RTC]rtc_get_frequency_meter,154: input=15, output=793
538 23:07:03.907823 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
539 23:07:03.914908 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
540 23:07:03.918123 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
541 23:07:03.921815 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
542 23:07:03.924701 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
543 23:07:03.928091 ADC[4]: Raw value=897780 ID=7
544 23:07:03.931144 ADC[3]: Raw value=212700 ID=1
545 23:07:03.931616 RAM Code: 0x71
546 23:07:03.938583 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
547 23:07:03.941351 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
548 23:07:03.951299 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
549 23:07:03.958226 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
550 23:07:03.961637 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
551 23:07:03.965178 in-header: 03 07 00 00 08 00 00 00
552 23:07:03.968867 in-data: aa e4 47 04 13 02 00 00
553 23:07:03.971475 Chrome EC: UHEPI supported
554 23:07:03.979232 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
555 23:07:03.982556 in-header: 03 d5 00 00 08 00 00 00
556 23:07:03.983114 in-data: 98 20 60 08 00 00 00 00
557 23:07:03.986463 MRC: failed to locate region type 0.
558 23:07:03.993999 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
559 23:07:03.997225 DRAM-K: Running full calibration
560 23:07:04.004689 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
561 23:07:04.005259 header.status = 0x0
562 23:07:04.008361 header.version = 0x6 (expected: 0x6)
563 23:07:04.011471 header.size = 0xd00 (expected: 0xd00)
564 23:07:04.014507 header.flags = 0x0
565 23:07:04.018163 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
566 23:07:04.037228 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
567 23:07:04.043851 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
568 23:07:04.046891 dram_init: ddr_geometry: 2
569 23:07:04.050140 [EMI] MDL number = 2
570 23:07:04.050626 [EMI] Get MDL freq = 0
571 23:07:04.053784 dram_init: ddr_type: 0
572 23:07:04.054251 is_discrete_lpddr4: 1
573 23:07:04.056888 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
574 23:07:04.057357
575 23:07:04.057792
576 23:07:04.060543 [Bian_co] ETT version 0.0.0.1
577 23:07:04.067249 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
578 23:07:04.067807
579 23:07:04.070729 dramc_set_vcore_voltage set vcore to 650000
580 23:07:04.071296 Read voltage for 800, 4
581 23:07:04.073921 Vio18 = 0
582 23:07:04.074483 Vcore = 650000
583 23:07:04.074859 Vdram = 0
584 23:07:04.077036 Vddq = 0
585 23:07:04.077522 Vmddr = 0
586 23:07:04.081080 dram_init: config_dvfs: 1
587 23:07:04.083926 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
588 23:07:04.090736 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
589 23:07:04.093775 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
590 23:07:04.097173 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
591 23:07:04.100356 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
592 23:07:04.103705 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
593 23:07:04.107286 MEM_TYPE=3, freq_sel=18
594 23:07:04.110481 sv_algorithm_assistance_LP4_1600
595 23:07:04.113874 ============ PULL DRAM RESETB DOWN ============
596 23:07:04.117114 ========== PULL DRAM RESETB DOWN end =========
597 23:07:04.123881 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
598 23:07:04.126898 ===================================
599 23:07:04.127373 LPDDR4 DRAM CONFIGURATION
600 23:07:04.130274 ===================================
601 23:07:04.133338 EX_ROW_EN[0] = 0x0
602 23:07:04.137311 EX_ROW_EN[1] = 0x0
603 23:07:04.137878 LP4Y_EN = 0x0
604 23:07:04.140926 WORK_FSP = 0x0
605 23:07:04.141494 WL = 0x2
606 23:07:04.144191 RL = 0x2
607 23:07:04.144804 BL = 0x2
608 23:07:04.147393 RPST = 0x0
609 23:07:04.147962 RD_PRE = 0x0
610 23:07:04.150657 WR_PRE = 0x1
611 23:07:04.151225 WR_PST = 0x0
612 23:07:04.154133 DBI_WR = 0x0
613 23:07:04.154721 DBI_RD = 0x0
614 23:07:04.156762 OTF = 0x1
615 23:07:04.161239 ===================================
616 23:07:04.164605 ===================================
617 23:07:04.165075 ANA top config
618 23:07:04.168070 ===================================
619 23:07:04.172096 DLL_ASYNC_EN = 0
620 23:07:04.172707 ALL_SLAVE_EN = 1
621 23:07:04.175666 NEW_RANK_MODE = 1
622 23:07:04.179291 DLL_IDLE_MODE = 1
623 23:07:04.179766 LP45_APHY_COMB_EN = 1
624 23:07:04.183016 TX_ODT_DIS = 1
625 23:07:04.186613 NEW_8X_MODE = 1
626 23:07:04.189517 ===================================
627 23:07:04.193188 ===================================
628 23:07:04.196926 data_rate = 1600
629 23:07:04.197463 CKR = 1
630 23:07:04.200421 DQ_P2S_RATIO = 8
631 23:07:04.204323 ===================================
632 23:07:04.207761 CA_P2S_RATIO = 8
633 23:07:04.211937 DQ_CA_OPEN = 0
634 23:07:04.212633 DQ_SEMI_OPEN = 0
635 23:07:04.215215 CA_SEMI_OPEN = 0
636 23:07:04.219032 CA_FULL_RATE = 0
637 23:07:04.222812 DQ_CKDIV4_EN = 1
638 23:07:04.223380 CA_CKDIV4_EN = 1
639 23:07:04.226278 CA_PREDIV_EN = 0
640 23:07:04.230000 PH8_DLY = 0
641 23:07:04.233380 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
642 23:07:04.233857 DQ_AAMCK_DIV = 4
643 23:07:04.237166 CA_AAMCK_DIV = 4
644 23:07:04.240914 CA_ADMCK_DIV = 4
645 23:07:04.244865 DQ_TRACK_CA_EN = 0
646 23:07:04.245435 CA_PICK = 800
647 23:07:04.248398 CA_MCKIO = 800
648 23:07:04.251841 MCKIO_SEMI = 0
649 23:07:04.255532 PLL_FREQ = 3068
650 23:07:04.258673 DQ_UI_PI_RATIO = 32
651 23:07:04.259243 CA_UI_PI_RATIO = 0
652 23:07:04.262309 ===================================
653 23:07:04.265115 ===================================
654 23:07:04.268973 memory_type:LPDDR4
655 23:07:04.272000 GP_NUM : 10
656 23:07:04.272596 SRAM_EN : 1
657 23:07:04.275656 MD32_EN : 0
658 23:07:04.279028 ===================================
659 23:07:04.282181 [ANA_INIT] >>>>>>>>>>>>>>
660 23:07:04.285691 <<<<<< [CONFIGURE PHASE]: ANA_TX
661 23:07:04.288972 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
662 23:07:04.292136 ===================================
663 23:07:04.292754 data_rate = 1600,PCW = 0X7600
664 23:07:04.295750 ===================================
665 23:07:04.299314 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
666 23:07:04.305735 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
667 23:07:04.312254 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
668 23:07:04.316000 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
669 23:07:04.319108 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
670 23:07:04.322585 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
671 23:07:04.325564 [ANA_INIT] flow start
672 23:07:04.326035 [ANA_INIT] PLL >>>>>>>>
673 23:07:04.329071 [ANA_INIT] PLL <<<<<<<<
674 23:07:04.333103 [ANA_INIT] MIDPI >>>>>>>>
675 23:07:04.333573 [ANA_INIT] MIDPI <<<<<<<<
676 23:07:04.336990 [ANA_INIT] DLL >>>>>>>>
677 23:07:04.337617 [ANA_INIT] flow end
678 23:07:04.340616 ============ LP4 DIFF to SE enter ============
679 23:07:04.347611 ============ LP4 DIFF to SE exit ============
680 23:07:04.348083 [ANA_INIT] <<<<<<<<<<<<<
681 23:07:04.351156 [Flow] Enable top DCM control >>>>>
682 23:07:04.355074 [Flow] Enable top DCM control <<<<<
683 23:07:04.358871 Enable DLL master slave shuffle
684 23:07:04.362519 ==============================================================
685 23:07:04.366003 Gating Mode config
686 23:07:04.369248 ==============================================================
687 23:07:04.373384 Config description:
688 23:07:04.382839 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
689 23:07:04.389273 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
690 23:07:04.392684 SELPH_MODE 0: By rank 1: By Phase
691 23:07:04.399324 ==============================================================
692 23:07:04.402481 GAT_TRACK_EN = 1
693 23:07:04.405866 RX_GATING_MODE = 2
694 23:07:04.409647 RX_GATING_TRACK_MODE = 2
695 23:07:04.412616 SELPH_MODE = 1
696 23:07:04.416155 PICG_EARLY_EN = 1
697 23:07:04.416803 VALID_LAT_VALUE = 1
698 23:07:04.423040 ==============================================================
699 23:07:04.426407 Enter into Gating configuration >>>>
700 23:07:04.430046 Exit from Gating configuration <<<<
701 23:07:04.433891 Enter into DVFS_PRE_config >>>>>
702 23:07:04.444737 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
703 23:07:04.448132 Exit from DVFS_PRE_config <<<<<
704 23:07:04.452036 Enter into PICG configuration >>>>
705 23:07:04.452732 Exit from PICG configuration <<<<
706 23:07:04.455557 [RX_INPUT] configuration >>>>>
707 23:07:04.459699 [RX_INPUT] configuration <<<<<
708 23:07:04.462957 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
709 23:07:04.470345 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
710 23:07:04.473911 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
711 23:07:04.481281 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
712 23:07:04.488353 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
713 23:07:04.495526 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
714 23:07:04.499428 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
715 23:07:04.503000 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
716 23:07:04.506900 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
717 23:07:04.510400 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
718 23:07:04.514375 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
719 23:07:04.517792 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
720 23:07:04.521419 ===================================
721 23:07:04.524887 LPDDR4 DRAM CONFIGURATION
722 23:07:04.528940 ===================================
723 23:07:04.529420 EX_ROW_EN[0] = 0x0
724 23:07:04.532737 EX_ROW_EN[1] = 0x0
725 23:07:04.533208 LP4Y_EN = 0x0
726 23:07:04.536186 WORK_FSP = 0x0
727 23:07:04.536702 WL = 0x2
728 23:07:04.540245 RL = 0x2
729 23:07:04.540725 BL = 0x2
730 23:07:04.544275 RPST = 0x0
731 23:07:04.544749 RD_PRE = 0x0
732 23:07:04.545127 WR_PRE = 0x1
733 23:07:04.547578 WR_PST = 0x0
734 23:07:04.548154 DBI_WR = 0x0
735 23:07:04.551398 DBI_RD = 0x0
736 23:07:04.551869 OTF = 0x1
737 23:07:04.555131 ===================================
738 23:07:04.559167 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
739 23:07:04.562989 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
740 23:07:04.570434 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
741 23:07:04.571059 ===================================
742 23:07:04.573639 LPDDR4 DRAM CONFIGURATION
743 23:07:04.577295 ===================================
744 23:07:04.581239 EX_ROW_EN[0] = 0x10
745 23:07:04.581815 EX_ROW_EN[1] = 0x0
746 23:07:04.584508 LP4Y_EN = 0x0
747 23:07:04.584984 WORK_FSP = 0x0
748 23:07:04.588511 WL = 0x2
749 23:07:04.589014 RL = 0x2
750 23:07:04.589387 BL = 0x2
751 23:07:04.592243 RPST = 0x0
752 23:07:04.592934 RD_PRE = 0x0
753 23:07:04.595954 WR_PRE = 0x1
754 23:07:04.596583 WR_PST = 0x0
755 23:07:04.599799 DBI_WR = 0x0
756 23:07:04.600343 DBI_RD = 0x0
757 23:07:04.603452 OTF = 0x1
758 23:07:04.607149 ===================================
759 23:07:04.610747 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
760 23:07:04.615506 nWR fixed to 40
761 23:07:04.615979 [ModeRegInit_LP4] CH0 RK0
762 23:07:04.619627 [ModeRegInit_LP4] CH0 RK1
763 23:07:04.623154 [ModeRegInit_LP4] CH1 RK0
764 23:07:04.623718 [ModeRegInit_LP4] CH1 RK1
765 23:07:04.626573 match AC timing 13
766 23:07:04.630473 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
767 23:07:04.634100 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
768 23:07:04.637679 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
769 23:07:04.644685 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
770 23:07:04.648313 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
771 23:07:04.652103 [EMI DOE] emi_dcm 0
772 23:07:04.655809 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
773 23:07:04.656350 ==
774 23:07:04.660157 Dram Type= 6, Freq= 0, CH_0, rank 0
775 23:07:04.663291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
776 23:07:04.663880 ==
777 23:07:04.667483 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
778 23:07:04.674173 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
779 23:07:04.683532 [CA 0] Center 38 (7~69) winsize 63
780 23:07:04.686801 [CA 1] Center 37 (7~68) winsize 62
781 23:07:04.690135 [CA 2] Center 36 (6~66) winsize 61
782 23:07:04.694040 [CA 3] Center 35 (5~66) winsize 62
783 23:07:04.698311 [CA 4] Center 34 (4~65) winsize 62
784 23:07:04.701844 [CA 5] Center 34 (4~65) winsize 62
785 23:07:04.702475
786 23:07:04.705475 [CmdBusTrainingLP45] Vref(ca) range 1: 30
787 23:07:04.705947
788 23:07:04.709585 [CATrainingPosCal] consider 1 rank data
789 23:07:04.710085 u2DelayCellTimex100 = 270/100 ps
790 23:07:04.713019 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
791 23:07:04.716473 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
792 23:07:04.720460 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
793 23:07:04.724587 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
794 23:07:04.727521 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
795 23:07:04.730904 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
796 23:07:04.731580
797 23:07:04.737195 CA PerBit enable=1, Macro0, CA PI delay=34
798 23:07:04.737702
799 23:07:04.740619 [CBTSetCACLKResult] CA Dly = 34
800 23:07:04.741088 CS Dly: 6 (0~37)
801 23:07:04.741461 ==
802 23:07:04.744518 Dram Type= 6, Freq= 0, CH_0, rank 1
803 23:07:04.747708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
804 23:07:04.748325 ==
805 23:07:04.754414 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
806 23:07:04.761128 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
807 23:07:04.769284 [CA 0] Center 38 (7~69) winsize 63
808 23:07:04.772564 [CA 1] Center 38 (7~69) winsize 63
809 23:07:04.776595 [CA 2] Center 35 (5~66) winsize 62
810 23:07:04.779509 [CA 3] Center 35 (5~66) winsize 62
811 23:07:04.783027 [CA 4] Center 34 (4~65) winsize 62
812 23:07:04.785611 [CA 5] Center 34 (4~65) winsize 62
813 23:07:04.786081
814 23:07:04.789239 [CmdBusTrainingLP45] Vref(ca) range 1: 34
815 23:07:04.789961
816 23:07:04.792605 [CATrainingPosCal] consider 2 rank data
817 23:07:04.795857 u2DelayCellTimex100 = 270/100 ps
818 23:07:04.799210 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
819 23:07:04.802418 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
820 23:07:04.808936 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
821 23:07:04.812383 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
822 23:07:04.815657 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
823 23:07:04.818813 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
824 23:07:04.819284
825 23:07:04.822427 CA PerBit enable=1, Macro0, CA PI delay=34
826 23:07:04.822896
827 23:07:04.825674 [CBTSetCACLKResult] CA Dly = 34
828 23:07:04.826144 CS Dly: 6 (0~37)
829 23:07:04.826518
830 23:07:04.829016 ----->DramcWriteLeveling(PI) begin...
831 23:07:04.832314 ==
832 23:07:04.835899 Dram Type= 6, Freq= 0, CH_0, rank 0
833 23:07:04.839007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
834 23:07:04.839480 ==
835 23:07:04.843051 Write leveling (Byte 0): 31 => 31
836 23:07:04.845972 Write leveling (Byte 1): 30 => 30
837 23:07:04.849139 DramcWriteLeveling(PI) end<-----
838 23:07:04.849604
839 23:07:04.849967 ==
840 23:07:04.852802 Dram Type= 6, Freq= 0, CH_0, rank 0
841 23:07:04.856008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
842 23:07:04.856534 ==
843 23:07:04.858994 [Gating] SW mode calibration
844 23:07:04.865908 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
845 23:07:04.869747 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
846 23:07:04.876030 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
847 23:07:04.879448 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
848 23:07:04.882766 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
849 23:07:04.889450 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
850 23:07:04.892315 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
851 23:07:04.895930 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
852 23:07:04.902521 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 23:07:04.906183 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 23:07:04.910120 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 23:07:04.916757 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 23:07:04.920550 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 23:07:04.924183 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 23:07:04.927506 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 23:07:04.930909 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 23:07:04.937943 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 23:07:04.941535 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 23:07:04.944712 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 23:07:04.948106 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
864 23:07:04.954785 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
865 23:07:04.957990 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
866 23:07:04.961700 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 23:07:04.968916 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 23:07:04.971882 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 23:07:04.975032 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 23:07:04.982129 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 23:07:04.985293 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 23:07:04.988357 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
873 23:07:04.994735 0 9 12 | B1->B0 | 2424 3030 | 0 1 | (0 0) (1 1)
874 23:07:04.997906 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
875 23:07:05.001786 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
876 23:07:05.008452 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
877 23:07:05.011863 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
878 23:07:05.014851 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
879 23:07:05.021497 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
880 23:07:05.024927 0 10 8 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
881 23:07:05.027865 0 10 12 | B1->B0 | 2b2b 2525 | 1 0 | (1 0) (0 0)
882 23:07:05.034671 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
883 23:07:05.037975 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
884 23:07:05.041555 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
885 23:07:05.047933 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
886 23:07:05.051521 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
887 23:07:05.054609 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
888 23:07:05.057793 0 11 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
889 23:07:05.064751 0 11 12 | B1->B0 | 3333 3e3e | 0 0 | (0 0) (0 0)
890 23:07:05.068333 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
891 23:07:05.071209 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
892 23:07:05.077938 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
893 23:07:05.081259 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
894 23:07:05.084687 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
895 23:07:05.091592 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
896 23:07:05.094685 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
897 23:07:05.097680 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
898 23:07:05.105021 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
899 23:07:05.107946 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
900 23:07:05.111417 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
901 23:07:05.117835 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 23:07:05.121269 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 23:07:05.124339 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 23:07:05.131231 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 23:07:05.134635 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 23:07:05.137929 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 23:07:05.144696 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 23:07:05.147611 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 23:07:05.151396 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 23:07:05.158455 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 23:07:05.161252 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 23:07:05.164636 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
913 23:07:05.168070 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
914 23:07:05.171671 Total UI for P1: 0, mck2ui 16
915 23:07:05.174709 best dqsien dly found for B0: ( 0, 14, 8)
916 23:07:05.181037 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
917 23:07:05.184628 Total UI for P1: 0, mck2ui 16
918 23:07:05.188378 best dqsien dly found for B1: ( 0, 14, 12)
919 23:07:05.191846 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
920 23:07:05.195017 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
921 23:07:05.195584
922 23:07:05.198057 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
923 23:07:05.201198 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
924 23:07:05.204821 [Gating] SW calibration Done
925 23:07:05.205389 ==
926 23:07:05.208383 Dram Type= 6, Freq= 0, CH_0, rank 0
927 23:07:05.211566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
928 23:07:05.212137 ==
929 23:07:05.214903 RX Vref Scan: 0
930 23:07:05.215470
931 23:07:05.215934 RX Vref 0 -> 0, step: 1
932 23:07:05.216354
933 23:07:05.218086 RX Delay -130 -> 252, step: 16
934 23:07:05.224520 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
935 23:07:05.228281 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
936 23:07:05.231691 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
937 23:07:05.234910 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
938 23:07:05.238198 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
939 23:07:05.244523 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
940 23:07:05.248192 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
941 23:07:05.251670 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
942 23:07:05.254628 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
943 23:07:05.257875 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
944 23:07:05.264324 iDelay=222, Bit 10, Center 61 (-66 ~ 189) 256
945 23:07:05.268045 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
946 23:07:05.271591 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
947 23:07:05.274470 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
948 23:07:05.278169 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
949 23:07:05.284407 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
950 23:07:05.284968 ==
951 23:07:05.288001 Dram Type= 6, Freq= 0, CH_0, rank 0
952 23:07:05.291185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
953 23:07:05.291761 ==
954 23:07:05.292134 DQS Delay:
955 23:07:05.294270 DQS0 = 0, DQS1 = 0
956 23:07:05.294776 DQM Delay:
957 23:07:05.297942 DQM0 = 81, DQM1 = 69
958 23:07:05.298510 DQ Delay:
959 23:07:05.301127 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
960 23:07:05.304795 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =93
961 23:07:05.308144 DQ8 =61, DQ9 =61, DQ10 =61, DQ11 =61
962 23:07:05.311357 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
963 23:07:05.311925
964 23:07:05.312354
965 23:07:05.312706 ==
966 23:07:05.315166 Dram Type= 6, Freq= 0, CH_0, rank 0
967 23:07:05.318625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
968 23:07:05.319260 ==
969 23:07:05.319905
970 23:07:05.320336
971 23:07:05.321490 TX Vref Scan disable
972 23:07:05.321960 == TX Byte 0 ==
973 23:07:05.328276 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
974 23:07:05.331739 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
975 23:07:05.332367 == TX Byte 1 ==
976 23:07:05.338689 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
977 23:07:05.341652 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
978 23:07:05.342126 ==
979 23:07:05.345126 Dram Type= 6, Freq= 0, CH_0, rank 0
980 23:07:05.348857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
981 23:07:05.349438 ==
982 23:07:05.362726 TX Vref=22, minBit 5, minWin=26, winSum=428
983 23:07:05.366241 TX Vref=24, minBit 0, minWin=27, winSum=438
984 23:07:05.369184 TX Vref=26, minBit 5, minWin=27, winSum=440
985 23:07:05.372939 TX Vref=28, minBit 8, minWin=27, winSum=443
986 23:07:05.376235 TX Vref=30, minBit 9, minWin=27, winSum=441
987 23:07:05.379474 TX Vref=32, minBit 9, minWin=27, winSum=442
988 23:07:05.386279 [TxChooseVref] Worse bit 8, Min win 27, Win sum 443, Final Vref 28
989 23:07:05.386901
990 23:07:05.389318 Final TX Range 1 Vref 28
991 23:07:05.389883
992 23:07:05.390252 ==
993 23:07:05.392790 Dram Type= 6, Freq= 0, CH_0, rank 0
994 23:07:05.395960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
995 23:07:05.396578 ==
996 23:07:05.397050
997 23:07:05.397485
998 23:07:05.398783 TX Vref Scan disable
999 23:07:05.402793 == TX Byte 0 ==
1000 23:07:05.406485 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1001 23:07:05.408982 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1002 23:07:05.412738 == TX Byte 1 ==
1003 23:07:05.416053 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1004 23:07:05.418977 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1005 23:07:05.422266
1006 23:07:05.422758 [DATLAT]
1007 23:07:05.423125 Freq=800, CH0 RK0
1008 23:07:05.423471
1009 23:07:05.426115 DATLAT Default: 0xa
1010 23:07:05.426755 0, 0xFFFF, sum = 0
1011 23:07:05.428780 1, 0xFFFF, sum = 0
1012 23:07:05.429256 2, 0xFFFF, sum = 0
1013 23:07:05.432407 3, 0xFFFF, sum = 0
1014 23:07:05.432916 4, 0xFFFF, sum = 0
1015 23:07:05.435985 5, 0xFFFF, sum = 0
1016 23:07:05.439185 6, 0xFFFF, sum = 0
1017 23:07:05.439750 7, 0xFFFF, sum = 0
1018 23:07:05.442034 8, 0xFFFF, sum = 0
1019 23:07:05.442502 9, 0x0, sum = 1
1020 23:07:05.442874 10, 0x0, sum = 2
1021 23:07:05.445493 11, 0x0, sum = 3
1022 23:07:05.445959 12, 0x0, sum = 4
1023 23:07:05.449098 best_step = 10
1024 23:07:05.449556
1025 23:07:05.449942 ==
1026 23:07:05.452139 Dram Type= 6, Freq= 0, CH_0, rank 0
1027 23:07:05.455963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1028 23:07:05.456605 ==
1029 23:07:05.459055 RX Vref Scan: 1
1030 23:07:05.459632
1031 23:07:05.462200 Set Vref Range= 32 -> 127
1032 23:07:05.462758
1033 23:07:05.463123 RX Vref 32 -> 127, step: 1
1034 23:07:05.463459
1035 23:07:05.465426 RX Delay -111 -> 252, step: 8
1036 23:07:05.465999
1037 23:07:05.468791 Set Vref, RX VrefLevel [Byte0]: 32
1038 23:07:05.472306 [Byte1]: 32
1039 23:07:05.472886
1040 23:07:05.475287 Set Vref, RX VrefLevel [Byte0]: 33
1041 23:07:05.478798 [Byte1]: 33
1042 23:07:05.482919
1043 23:07:05.483369 Set Vref, RX VrefLevel [Byte0]: 34
1044 23:07:05.486273 [Byte1]: 34
1045 23:07:05.490682
1046 23:07:05.491233 Set Vref, RX VrefLevel [Byte0]: 35
1047 23:07:05.493839 [Byte1]: 35
1048 23:07:05.498127
1049 23:07:05.498689 Set Vref, RX VrefLevel [Byte0]: 36
1050 23:07:05.501231 [Byte1]: 36
1051 23:07:05.506804
1052 23:07:05.507358 Set Vref, RX VrefLevel [Byte0]: 37
1053 23:07:05.508997 [Byte1]: 37
1054 23:07:05.513545
1055 23:07:05.513998 Set Vref, RX VrefLevel [Byte0]: 38
1056 23:07:05.516545 [Byte1]: 38
1057 23:07:05.521279
1058 23:07:05.521733 Set Vref, RX VrefLevel [Byte0]: 39
1059 23:07:05.524380 [Byte1]: 39
1060 23:07:05.528638
1061 23:07:05.529229 Set Vref, RX VrefLevel [Byte0]: 40
1062 23:07:05.532165 [Byte1]: 40
1063 23:07:05.536718
1064 23:07:05.537264 Set Vref, RX VrefLevel [Byte0]: 41
1065 23:07:05.539611 [Byte1]: 41
1066 23:07:05.543832
1067 23:07:05.544463 Set Vref, RX VrefLevel [Byte0]: 42
1068 23:07:05.547282 [Byte1]: 42
1069 23:07:05.551683
1070 23:07:05.552265 Set Vref, RX VrefLevel [Byte0]: 43
1071 23:07:05.554989 [Byte1]: 43
1072 23:07:05.559252
1073 23:07:05.559821 Set Vref, RX VrefLevel [Byte0]: 44
1074 23:07:05.563025 [Byte1]: 44
1075 23:07:05.567038
1076 23:07:05.567591 Set Vref, RX VrefLevel [Byte0]: 45
1077 23:07:05.570459 [Byte1]: 45
1078 23:07:05.575233
1079 23:07:05.575784 Set Vref, RX VrefLevel [Byte0]: 46
1080 23:07:05.578108 [Byte1]: 46
1081 23:07:05.582838
1082 23:07:05.583485 Set Vref, RX VrefLevel [Byte0]: 47
1083 23:07:05.585753 [Byte1]: 47
1084 23:07:05.589448
1085 23:07:05.593207 Set Vref, RX VrefLevel [Byte0]: 48
1086 23:07:05.593661 [Byte1]: 48
1087 23:07:05.597813
1088 23:07:05.598264 Set Vref, RX VrefLevel [Byte0]: 49
1089 23:07:05.601565 [Byte1]: 49
1090 23:07:05.605932
1091 23:07:05.606516 Set Vref, RX VrefLevel [Byte0]: 50
1092 23:07:05.609173 [Byte1]: 50
1093 23:07:05.612776
1094 23:07:05.613230 Set Vref, RX VrefLevel [Byte0]: 51
1095 23:07:05.616118 [Byte1]: 51
1096 23:07:05.620477
1097 23:07:05.621083 Set Vref, RX VrefLevel [Byte0]: 52
1098 23:07:05.623955 [Byte1]: 52
1099 23:07:05.628120
1100 23:07:05.628721 Set Vref, RX VrefLevel [Byte0]: 53
1101 23:07:05.631628 [Byte1]: 53
1102 23:07:05.636326
1103 23:07:05.637066 Set Vref, RX VrefLevel [Byte0]: 54
1104 23:07:05.638750 [Byte1]: 54
1105 23:07:05.643733
1106 23:07:05.644342 Set Vref, RX VrefLevel [Byte0]: 55
1107 23:07:05.646846 [Byte1]: 55
1108 23:07:05.651017
1109 23:07:05.654656 Set Vref, RX VrefLevel [Byte0]: 56
1110 23:07:05.657414 [Byte1]: 56
1111 23:07:05.657867
1112 23:07:05.660763 Set Vref, RX VrefLevel [Byte0]: 57
1113 23:07:05.664612 [Byte1]: 57
1114 23:07:05.665068
1115 23:07:05.667580 Set Vref, RX VrefLevel [Byte0]: 58
1116 23:07:05.670906 [Byte1]: 58
1117 23:07:05.671361
1118 23:07:05.674447 Set Vref, RX VrefLevel [Byte0]: 59
1119 23:07:05.677636 [Byte1]: 59
1120 23:07:05.681704
1121 23:07:05.682155 Set Vref, RX VrefLevel [Byte0]: 60
1122 23:07:05.684802 [Byte1]: 60
1123 23:07:05.689273
1124 23:07:05.689827 Set Vref, RX VrefLevel [Byte0]: 61
1125 23:07:05.692461 [Byte1]: 61
1126 23:07:05.696812
1127 23:07:05.697400 Set Vref, RX VrefLevel [Byte0]: 62
1128 23:07:05.699987 [Byte1]: 62
1129 23:07:05.704419
1130 23:07:05.704894 Set Vref, RX VrefLevel [Byte0]: 63
1131 23:07:05.707725 [Byte1]: 63
1132 23:07:05.711915
1133 23:07:05.712410 Set Vref, RX VrefLevel [Byte0]: 64
1134 23:07:05.715305 [Byte1]: 64
1135 23:07:05.719836
1136 23:07:05.720352 Set Vref, RX VrefLevel [Byte0]: 65
1137 23:07:05.723111 [Byte1]: 65
1138 23:07:05.727381
1139 23:07:05.727851 Set Vref, RX VrefLevel [Byte0]: 66
1140 23:07:05.730642 [Byte1]: 66
1141 23:07:05.734937
1142 23:07:05.735388 Set Vref, RX VrefLevel [Byte0]: 67
1143 23:07:05.738570 [Byte1]: 67
1144 23:07:05.742997
1145 23:07:05.743591 Set Vref, RX VrefLevel [Byte0]: 68
1146 23:07:05.745942 [Byte1]: 68
1147 23:07:05.750492
1148 23:07:05.751046 Set Vref, RX VrefLevel [Byte0]: 69
1149 23:07:05.754071 [Byte1]: 69
1150 23:07:05.758195
1151 23:07:05.758762 Set Vref, RX VrefLevel [Byte0]: 70
1152 23:07:05.761082 [Byte1]: 70
1153 23:07:05.765616
1154 23:07:05.766174 Set Vref, RX VrefLevel [Byte0]: 71
1155 23:07:05.768975 [Byte1]: 71
1156 23:07:05.773727
1157 23:07:05.774278 Set Vref, RX VrefLevel [Byte0]: 72
1158 23:07:05.777013 [Byte1]: 72
1159 23:07:05.781179
1160 23:07:05.781730 Set Vref, RX VrefLevel [Byte0]: 73
1161 23:07:05.784515 [Byte1]: 73
1162 23:07:05.788859
1163 23:07:05.789420 Set Vref, RX VrefLevel [Byte0]: 74
1164 23:07:05.792001 [Byte1]: 74
1165 23:07:05.796119
1166 23:07:05.796741 Set Vref, RX VrefLevel [Byte0]: 75
1167 23:07:05.799440 [Byte1]: 75
1168 23:07:05.804149
1169 23:07:05.804761 Set Vref, RX VrefLevel [Byte0]: 76
1170 23:07:05.807205 [Byte1]: 76
1171 23:07:05.811763
1172 23:07:05.812383 Set Vref, RX VrefLevel [Byte0]: 77
1173 23:07:05.815265 [Byte1]: 77
1174 23:07:05.819369
1175 23:07:05.819974 Set Vref, RX VrefLevel [Byte0]: 78
1176 23:07:05.822481 [Byte1]: 78
1177 23:07:05.827021
1178 23:07:05.827479 Set Vref, RX VrefLevel [Byte0]: 79
1179 23:07:05.829886 [Byte1]: 79
1180 23:07:05.834316
1181 23:07:05.834768 Final RX Vref Byte 0 = 61 to rank0
1182 23:07:05.837961 Final RX Vref Byte 1 = 56 to rank0
1183 23:07:05.841049 Final RX Vref Byte 0 = 61 to rank1
1184 23:07:05.844463 Final RX Vref Byte 1 = 56 to rank1==
1185 23:07:05.847962 Dram Type= 6, Freq= 0, CH_0, rank 0
1186 23:07:05.851641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1187 23:07:05.854742 ==
1188 23:07:05.855198 DQS Delay:
1189 23:07:05.855559 DQS0 = 0, DQS1 = 0
1190 23:07:05.857698 DQM Delay:
1191 23:07:05.858150 DQM0 = 82, DQM1 = 68
1192 23:07:05.861574 DQ Delay:
1193 23:07:05.864386 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1194 23:07:05.864843 DQ4 =80, DQ5 =68, DQ6 =92, DQ7 =92
1195 23:07:05.868128 DQ8 =60, DQ9 =52, DQ10 =68, DQ11 =60
1196 23:07:05.871225 DQ12 =76, DQ13 =72, DQ14 =80, DQ15 =76
1197 23:07:05.874684
1198 23:07:05.875135
1199 23:07:05.881168 [DQSOSCAuto] RK0, (LSB)MR18= 0x2b2b, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 398 ps
1200 23:07:05.884323 CH0 RK0: MR19=606, MR18=2B2B
1201 23:07:05.891415 CH0_RK0: MR19=0x606, MR18=0x2B2B, DQSOSC=398, MR23=63, INC=93, DEC=62
1202 23:07:05.891962
1203 23:07:05.894710 ----->DramcWriteLeveling(PI) begin...
1204 23:07:05.895171 ==
1205 23:07:05.897772 Dram Type= 6, Freq= 0, CH_0, rank 1
1206 23:07:05.901041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1207 23:07:05.901500 ==
1208 23:07:05.904798 Write leveling (Byte 0): 33 => 33
1209 23:07:05.908055 Write leveling (Byte 1): 30 => 30
1210 23:07:05.910974 DramcWriteLeveling(PI) end<-----
1211 23:07:05.911426
1212 23:07:05.911782 ==
1213 23:07:05.914890 Dram Type= 6, Freq= 0, CH_0, rank 1
1214 23:07:05.917703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1215 23:07:05.918177 ==
1216 23:07:05.921287 [Gating] SW mode calibration
1217 23:07:05.927697 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1218 23:07:05.934512 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1219 23:07:05.937920 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1220 23:07:05.941037 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1221 23:07:05.947707 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 23:07:05.951541 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 23:07:05.954428 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 23:07:05.960884 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 23:07:05.964124 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 23:07:05.967637 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 23:07:05.974373 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 23:07:05.977814 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 23:07:05.981675 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 23:07:05.984187 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 23:07:06.032149 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 23:07:06.032848 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 23:07:06.033801 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 23:07:06.034396 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 23:07:06.034757 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 23:07:06.035109 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1237 23:07:06.035428 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1238 23:07:06.035832 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 23:07:06.036260 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 23:07:06.036596 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 23:07:06.076166 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 23:07:06.076911 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 23:07:06.077499 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 23:07:06.078313 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 23:07:06.078697 0 9 8 | B1->B0 | 2424 2c2c | 0 1 | (1 1) (1 1)
1246 23:07:06.079055 0 9 12 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
1247 23:07:06.079601 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1248 23:07:06.079978 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1249 23:07:06.080354 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1250 23:07:06.080684 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1251 23:07:06.085581 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1252 23:07:06.086044 0 10 4 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
1253 23:07:06.089584 0 10 8 | B1->B0 | 3030 2525 | 0 0 | (0 1) (1 0)
1254 23:07:06.093130 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1255 23:07:06.096159 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1256 23:07:06.099167 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 23:07:06.105920 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1258 23:07:06.108930 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1259 23:07:06.112942 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1260 23:07:06.119564 0 11 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1261 23:07:06.122393 0 11 8 | B1->B0 | 3232 3b3b | 0 0 | (1 1) (0 0)
1262 23:07:06.126364 0 11 12 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
1263 23:07:06.132433 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1264 23:07:06.136029 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1265 23:07:06.139392 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1266 23:07:06.145717 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1267 23:07:06.149525 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1268 23:07:06.153610 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1269 23:07:06.156921 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1270 23:07:06.160784 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 23:07:06.168249 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 23:07:06.170931 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 23:07:06.174581 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 23:07:06.177934 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 23:07:06.184887 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 23:07:06.188307 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 23:07:06.191698 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 23:07:06.198279 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 23:07:06.201951 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 23:07:06.205480 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 23:07:06.211942 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 23:07:06.215045 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 23:07:06.218393 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 23:07:06.225297 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1285 23:07:06.228358 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1286 23:07:06.231843 Total UI for P1: 0, mck2ui 16
1287 23:07:06.235166 best dqsien dly found for B0: ( 0, 14, 4)
1288 23:07:06.238087 Total UI for P1: 0, mck2ui 16
1289 23:07:06.241420 best dqsien dly found for B1: ( 0, 14, 6)
1290 23:07:06.245207 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1291 23:07:06.248619 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1292 23:07:06.249177
1293 23:07:06.251939 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1294 23:07:06.255309 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1295 23:07:06.258182 [Gating] SW calibration Done
1296 23:07:06.258683 ==
1297 23:07:06.261733 Dram Type= 6, Freq= 0, CH_0, rank 1
1298 23:07:06.264659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1299 23:07:06.265120 ==
1300 23:07:06.268448 RX Vref Scan: 0
1301 23:07:06.268995
1302 23:07:06.269356 RX Vref 0 -> 0, step: 1
1303 23:07:06.269693
1304 23:07:06.271802 RX Delay -130 -> 252, step: 16
1305 23:07:06.278403 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1306 23:07:06.281601 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1307 23:07:06.285346 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1308 23:07:06.288604 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1309 23:07:06.291885 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1310 23:07:06.298480 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
1311 23:07:06.301551 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1312 23:07:06.304732 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1313 23:07:06.308077 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1314 23:07:06.311530 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1315 23:07:06.318642 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1316 23:07:06.321192 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1317 23:07:06.325075 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1318 23:07:06.328179 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1319 23:07:06.331569 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1320 23:07:06.338176 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1321 23:07:06.338742 ==
1322 23:07:06.341260 Dram Type= 6, Freq= 0, CH_0, rank 1
1323 23:07:06.344719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1324 23:07:06.345185 ==
1325 23:07:06.345543 DQS Delay:
1326 23:07:06.348342 DQS0 = 0, DQS1 = 0
1327 23:07:06.348913 DQM Delay:
1328 23:07:06.351924 DQM0 = 82, DQM1 = 70
1329 23:07:06.352547 DQ Delay:
1330 23:07:06.355217 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =77
1331 23:07:06.358178 DQ4 =85, DQ5 =61, DQ6 =93, DQ7 =93
1332 23:07:06.361726 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1333 23:07:06.365074 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =85
1334 23:07:06.365638
1335 23:07:06.365998
1336 23:07:06.366332 ==
1337 23:07:06.368639 Dram Type= 6, Freq= 0, CH_0, rank 1
1338 23:07:06.371576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1339 23:07:06.372040 ==
1340 23:07:06.372495
1341 23:07:06.372838
1342 23:07:06.374890 TX Vref Scan disable
1343 23:07:06.378359 == TX Byte 0 ==
1344 23:07:06.381841 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1345 23:07:06.385207 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1346 23:07:06.387917 == TX Byte 1 ==
1347 23:07:06.391497 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1348 23:07:06.394697 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1349 23:07:06.395160 ==
1350 23:07:06.397919 Dram Type= 6, Freq= 0, CH_0, rank 1
1351 23:07:06.405196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1352 23:07:06.405772 ==
1353 23:07:06.416845 TX Vref=22, minBit 11, minWin=26, winSum=439
1354 23:07:06.419706 TX Vref=24, minBit 1, minWin=27, winSum=436
1355 23:07:06.423277 TX Vref=26, minBit 13, minWin=26, winSum=439
1356 23:07:06.426583 TX Vref=28, minBit 1, minWin=27, winSum=442
1357 23:07:06.429975 TX Vref=30, minBit 1, minWin=27, winSum=442
1358 23:07:06.436712 TX Vref=32, minBit 8, minWin=27, winSum=444
1359 23:07:06.439752 [TxChooseVref] Worse bit 8, Min win 27, Win sum 444, Final Vref 32
1360 23:07:06.440248
1361 23:07:06.443447 Final TX Range 1 Vref 32
1362 23:07:06.443902
1363 23:07:06.444298 ==
1364 23:07:06.446392 Dram Type= 6, Freq= 0, CH_0, rank 1
1365 23:07:06.449643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1366 23:07:06.450100 ==
1367 23:07:06.452871
1368 23:07:06.453322
1369 23:07:06.453683 TX Vref Scan disable
1370 23:07:06.456536 == TX Byte 0 ==
1371 23:07:06.460283 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1372 23:07:06.463009 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1373 23:07:06.466737 == TX Byte 1 ==
1374 23:07:06.469869 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1375 23:07:06.473673 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1376 23:07:06.476859
1377 23:07:06.477413 [DATLAT]
1378 23:07:06.477774 Freq=800, CH0 RK1
1379 23:07:06.478112
1380 23:07:06.479812 DATLAT Default: 0xa
1381 23:07:06.480298 0, 0xFFFF, sum = 0
1382 23:07:06.483580 1, 0xFFFF, sum = 0
1383 23:07:06.484143 2, 0xFFFF, sum = 0
1384 23:07:06.486799 3, 0xFFFF, sum = 0
1385 23:07:06.487357 4, 0xFFFF, sum = 0
1386 23:07:06.489671 5, 0xFFFF, sum = 0
1387 23:07:06.490131 6, 0xFFFF, sum = 0
1388 23:07:06.493030 7, 0xFFFF, sum = 0
1389 23:07:06.496664 8, 0xFFFF, sum = 0
1390 23:07:06.497127 9, 0x0, sum = 1
1391 23:07:06.497494 10, 0x0, sum = 2
1392 23:07:06.499854 11, 0x0, sum = 3
1393 23:07:06.500401 12, 0x0, sum = 4
1394 23:07:06.503143 best_step = 10
1395 23:07:06.503592
1396 23:07:06.503945 ==
1397 23:07:06.506514 Dram Type= 6, Freq= 0, CH_0, rank 1
1398 23:07:06.510247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1399 23:07:06.510808 ==
1400 23:07:06.513282 RX Vref Scan: 0
1401 23:07:06.513733
1402 23:07:06.514089 RX Vref 0 -> 0, step: 1
1403 23:07:06.514484
1404 23:07:06.516513 RX Delay -111 -> 252, step: 8
1405 23:07:06.523120 iDelay=209, Bit 0, Center 76 (-39 ~ 192) 232
1406 23:07:06.526699 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1407 23:07:06.529963 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1408 23:07:06.533218 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1409 23:07:06.536617 iDelay=209, Bit 4, Center 76 (-39 ~ 192) 232
1410 23:07:06.543389 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1411 23:07:06.546738 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
1412 23:07:06.550210 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1413 23:07:06.553296 iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232
1414 23:07:06.556617 iDelay=209, Bit 9, Center 52 (-63 ~ 168) 232
1415 23:07:06.563292 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1416 23:07:06.566348 iDelay=209, Bit 11, Center 60 (-55 ~ 176) 232
1417 23:07:06.570250 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
1418 23:07:06.573430 iDelay=209, Bit 13, Center 76 (-39 ~ 192) 232
1419 23:07:06.576321 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1420 23:07:06.583240 iDelay=209, Bit 15, Center 76 (-39 ~ 192) 232
1421 23:07:06.583656 ==
1422 23:07:06.586224 Dram Type= 6, Freq= 0, CH_0, rank 1
1423 23:07:06.589616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1424 23:07:06.589790 ==
1425 23:07:06.589854 DQS Delay:
1426 23:07:06.593055 DQS0 = 0, DQS1 = 0
1427 23:07:06.593135 DQM Delay:
1428 23:07:06.596008 DQM0 = 78, DQM1 = 69
1429 23:07:06.596088 DQ Delay:
1430 23:07:06.599286 DQ0 =76, DQ1 =84, DQ2 =76, DQ3 =72
1431 23:07:06.602709 DQ4 =76, DQ5 =64, DQ6 =88, DQ7 =92
1432 23:07:06.606329 DQ8 =60, DQ9 =52, DQ10 =72, DQ11 =60
1433 23:07:06.609962 DQ12 =80, DQ13 =76, DQ14 =80, DQ15 =76
1434 23:07:06.610042
1435 23:07:06.610105
1436 23:07:06.616364 [DQSOSCAuto] RK1, (LSB)MR18= 0x4c26, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 390 ps
1437 23:07:06.620022 CH0 RK1: MR19=606, MR18=4C26
1438 23:07:06.627147 CH0_RK1: MR19=0x606, MR18=0x4C26, DQSOSC=390, MR23=63, INC=97, DEC=64
1439 23:07:06.629970 [RxdqsGatingPostProcess] freq 800
1440 23:07:06.636411 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1441 23:07:06.640267 Pre-setting of DQS Precalculation
1442 23:07:06.642902 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1443 23:07:06.643561 ==
1444 23:07:06.646560 Dram Type= 6, Freq= 0, CH_1, rank 0
1445 23:07:06.649949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1446 23:07:06.650411 ==
1447 23:07:06.656304 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1448 23:07:06.663391 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1449 23:07:06.672007 [CA 0] Center 36 (6~66) winsize 61
1450 23:07:06.674985 [CA 1] Center 36 (6~67) winsize 62
1451 23:07:06.678704 [CA 2] Center 34 (5~64) winsize 60
1452 23:07:06.681372 [CA 3] Center 34 (4~64) winsize 61
1453 23:07:06.685382 [CA 4] Center 34 (4~64) winsize 61
1454 23:07:06.688655 [CA 5] Center 34 (4~64) winsize 61
1455 23:07:06.689151
1456 23:07:06.691892 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1457 23:07:06.692398
1458 23:07:06.695127 [CATrainingPosCal] consider 1 rank data
1459 23:07:06.698273 u2DelayCellTimex100 = 270/100 ps
1460 23:07:06.701325 CA0 delay=36 (6~66),Diff = 2 PI (14 cell)
1461 23:07:06.705385 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1462 23:07:06.711761 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1463 23:07:06.714883 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1464 23:07:06.718099 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
1465 23:07:06.721838 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1466 23:07:06.722400
1467 23:07:06.725220 CA PerBit enable=1, Macro0, CA PI delay=34
1468 23:07:06.725727
1469 23:07:06.728149 [CBTSetCACLKResult] CA Dly = 34
1470 23:07:06.728681 CS Dly: 4 (0~35)
1471 23:07:06.729043 ==
1472 23:07:06.731550 Dram Type= 6, Freq= 0, CH_1, rank 1
1473 23:07:06.738575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1474 23:07:06.739106 ==
1475 23:07:06.741833 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1476 23:07:06.748100 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1477 23:07:06.757858 [CA 0] Center 36 (6~66) winsize 61
1478 23:07:06.761211 [CA 1] Center 37 (7~67) winsize 61
1479 23:07:06.764270 [CA 2] Center 34 (4~65) winsize 62
1480 23:07:06.767484 [CA 3] Center 33 (3~64) winsize 62
1481 23:07:06.770869 [CA 4] Center 34 (4~65) winsize 62
1482 23:07:06.774292 [CA 5] Center 33 (3~64) winsize 62
1483 23:07:06.774700
1484 23:07:06.777731 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1485 23:07:06.778144
1486 23:07:06.780929 [CATrainingPosCal] consider 2 rank data
1487 23:07:06.784070 u2DelayCellTimex100 = 270/100 ps
1488 23:07:06.787602 CA0 delay=36 (6~66),Diff = 2 PI (14 cell)
1489 23:07:06.790688 CA1 delay=37 (7~67),Diff = 3 PI (21 cell)
1490 23:07:06.797630 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1491 23:07:06.801028 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1492 23:07:06.803930 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
1493 23:07:06.807533 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1494 23:07:06.807646
1495 23:07:06.811191 CA PerBit enable=1, Macro0, CA PI delay=34
1496 23:07:06.811302
1497 23:07:06.814933 [CBTSetCACLKResult] CA Dly = 34
1498 23:07:06.815033 CS Dly: 5 (0~38)
1499 23:07:06.815112
1500 23:07:06.818489 ----->DramcWriteLeveling(PI) begin...
1501 23:07:06.818580 ==
1502 23:07:06.823086 Dram Type= 6, Freq= 0, CH_1, rank 0
1503 23:07:06.826856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1504 23:07:06.827316 ==
1505 23:07:06.830152 Write leveling (Byte 0): 27 => 27
1506 23:07:06.833689 Write leveling (Byte 1): 29 => 29
1507 23:07:06.837435 DramcWriteLeveling(PI) end<-----
1508 23:07:06.837888
1509 23:07:06.838245 ==
1510 23:07:06.840628 Dram Type= 6, Freq= 0, CH_1, rank 0
1511 23:07:06.844240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1512 23:07:06.844702 ==
1513 23:07:06.847748 [Gating] SW mode calibration
1514 23:07:06.854632 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1515 23:07:06.857770 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1516 23:07:06.864723 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1517 23:07:06.868058 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1518 23:07:06.871170 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1519 23:07:06.878026 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 23:07:06.881341 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 23:07:06.884189 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 23:07:06.891173 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 23:07:06.894401 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 23:07:06.897597 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 23:07:06.904691 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 23:07:06.907691 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 23:07:06.911147 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 23:07:06.917315 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 23:07:06.920691 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 23:07:06.923978 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 23:07:06.927309 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 23:07:06.934130 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 23:07:06.937287 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1534 23:07:06.940780 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 1)
1535 23:07:06.947033 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 23:07:06.950969 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 23:07:06.954165 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 23:07:06.960810 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 23:07:06.963960 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 23:07:06.967329 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 23:07:06.974299 0 9 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
1542 23:07:06.977623 0 9 8 | B1->B0 | 2e2e 2827 | 0 1 | (0 0) (0 0)
1543 23:07:06.980636 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1544 23:07:06.987088 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1545 23:07:06.990585 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1546 23:07:06.994024 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1547 23:07:07.000489 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1548 23:07:07.003733 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1549 23:07:07.007110 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
1550 23:07:07.013725 0 10 8 | B1->B0 | 2f2f 2f2f | 1 1 | (1 1) (1 0)
1551 23:07:07.017303 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 23:07:07.020381 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 23:07:07.027137 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 23:07:07.030287 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 23:07:07.033937 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 23:07:07.040572 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 23:07:07.044098 0 11 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1558 23:07:07.047302 0 11 8 | B1->B0 | 3838 3737 | 0 0 | (0 0) (0 0)
1559 23:07:07.054262 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1560 23:07:07.057813 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1561 23:07:07.060482 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1562 23:07:07.064167 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1563 23:07:07.071415 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1564 23:07:07.073936 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1565 23:07:07.077645 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1566 23:07:07.083963 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1567 23:07:07.087328 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 23:07:07.090560 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 23:07:07.097272 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 23:07:07.100713 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 23:07:07.104171 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 23:07:07.110335 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 23:07:07.114148 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 23:07:07.116810 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 23:07:07.123726 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 23:07:07.127217 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 23:07:07.130513 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 23:07:07.137649 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 23:07:07.140610 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 23:07:07.143727 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 23:07:07.150322 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1582 23:07:07.154009 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1583 23:07:07.157307 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1584 23:07:07.160455 Total UI for P1: 0, mck2ui 16
1585 23:07:07.164055 best dqsien dly found for B0: ( 0, 14, 6)
1586 23:07:07.167752 Total UI for P1: 0, mck2ui 16
1587 23:07:07.171133 best dqsien dly found for B1: ( 0, 14, 6)
1588 23:07:07.174021 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1589 23:07:07.177023 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1590 23:07:07.177480
1591 23:07:07.180720 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1592 23:07:07.184319 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1593 23:07:07.187595 [Gating] SW calibration Done
1594 23:07:07.188146 ==
1595 23:07:07.190917 Dram Type= 6, Freq= 0, CH_1, rank 0
1596 23:07:07.197208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1597 23:07:07.197765 ==
1598 23:07:07.198131 RX Vref Scan: 0
1599 23:07:07.198469
1600 23:07:07.200796 RX Vref 0 -> 0, step: 1
1601 23:07:07.201344
1602 23:07:07.203724 RX Delay -130 -> 252, step: 16
1603 23:07:07.207258 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1604 23:07:07.210857 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1605 23:07:07.214059 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1606 23:07:07.217829 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1607 23:07:07.223935 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1608 23:07:07.227609 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1609 23:07:07.231238 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1610 23:07:07.234009 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1611 23:07:07.237489 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1612 23:07:07.243607 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1613 23:07:07.247462 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1614 23:07:07.250314 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1615 23:07:07.253821 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1616 23:07:07.257289 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1617 23:07:07.263680 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1618 23:07:07.266977 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1619 23:07:07.267431 ==
1620 23:07:07.270695 Dram Type= 6, Freq= 0, CH_1, rank 0
1621 23:07:07.273794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1622 23:07:07.274254 ==
1623 23:07:07.276870 DQS Delay:
1624 23:07:07.277326 DQS0 = 0, DQS1 = 0
1625 23:07:07.277685 DQM Delay:
1626 23:07:07.280268 DQM0 = 81, DQM1 = 70
1627 23:07:07.280725 DQ Delay:
1628 23:07:07.284014 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1629 23:07:07.287521 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1630 23:07:07.290714 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
1631 23:07:07.294193 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1632 23:07:07.294748
1633 23:07:07.295112
1634 23:07:07.295446 ==
1635 23:07:07.297055 Dram Type= 6, Freq= 0, CH_1, rank 0
1636 23:07:07.303752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1637 23:07:07.304351 ==
1638 23:07:07.304726
1639 23:07:07.305061
1640 23:07:07.305381 TX Vref Scan disable
1641 23:07:07.307370 == TX Byte 0 ==
1642 23:07:07.311042 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1643 23:07:07.317732 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1644 23:07:07.318292 == TX Byte 1 ==
1645 23:07:07.321240 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1646 23:07:07.327647 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1647 23:07:07.328247 ==
1648 23:07:07.330613 Dram Type= 6, Freq= 0, CH_1, rank 0
1649 23:07:07.333658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1650 23:07:07.334120 ==
1651 23:07:07.346508 TX Vref=22, minBit 1, minWin=27, winSum=441
1652 23:07:07.350128 TX Vref=24, minBit 1, minWin=27, winSum=443
1653 23:07:07.352759 TX Vref=26, minBit 1, minWin=27, winSum=447
1654 23:07:07.356412 TX Vref=28, minBit 5, minWin=27, winSum=447
1655 23:07:07.360011 TX Vref=30, minBit 5, minWin=27, winSum=451
1656 23:07:07.363140 TX Vref=32, minBit 0, minWin=27, winSum=446
1657 23:07:07.369753 [TxChooseVref] Worse bit 5, Min win 27, Win sum 451, Final Vref 30
1658 23:07:07.370349
1659 23:07:07.373289 Final TX Range 1 Vref 30
1660 23:07:07.373747
1661 23:07:07.374105 ==
1662 23:07:07.376731 Dram Type= 6, Freq= 0, CH_1, rank 0
1663 23:07:07.379586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1664 23:07:07.380044 ==
1665 23:07:07.380525
1666 23:07:07.383352
1667 23:07:07.383803 TX Vref Scan disable
1668 23:07:07.386475 == TX Byte 0 ==
1669 23:07:07.390513 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1670 23:07:07.394426 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1671 23:07:07.397039 == TX Byte 1 ==
1672 23:07:07.401170 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1673 23:07:07.403897 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1674 23:07:07.404578
1675 23:07:07.407140 [DATLAT]
1676 23:07:07.407688 Freq=800, CH1 RK0
1677 23:07:07.408054
1678 23:07:07.410673 DATLAT Default: 0xa
1679 23:07:07.411230 0, 0xFFFF, sum = 0
1680 23:07:07.413795 1, 0xFFFF, sum = 0
1681 23:07:07.414258 2, 0xFFFF, sum = 0
1682 23:07:07.416992 3, 0xFFFF, sum = 0
1683 23:07:07.417519 4, 0xFFFF, sum = 0
1684 23:07:07.420684 5, 0xFFFF, sum = 0
1685 23:07:07.421248 6, 0xFFFF, sum = 0
1686 23:07:07.423749 7, 0xFFFF, sum = 0
1687 23:07:07.424437 8, 0xFFFF, sum = 0
1688 23:07:07.427713 9, 0x0, sum = 1
1689 23:07:07.428339 10, 0x0, sum = 2
1690 23:07:07.430534 11, 0x0, sum = 3
1691 23:07:07.431096 12, 0x0, sum = 4
1692 23:07:07.433553 best_step = 10
1693 23:07:07.434005
1694 23:07:07.434364 ==
1695 23:07:07.437216 Dram Type= 6, Freq= 0, CH_1, rank 0
1696 23:07:07.440389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1697 23:07:07.440852 ==
1698 23:07:07.441216 RX Vref Scan: 1
1699 23:07:07.441555
1700 23:07:07.443912 Set Vref Range= 32 -> 127
1701 23:07:07.444521
1702 23:07:07.447062 RX Vref 32 -> 127, step: 1
1703 23:07:07.447557
1704 23:07:07.450640 RX Delay -111 -> 252, step: 8
1705 23:07:07.451095
1706 23:07:07.454035 Set Vref, RX VrefLevel [Byte0]: 32
1707 23:07:07.457539 [Byte1]: 32
1708 23:07:07.458093
1709 23:07:07.460386 Set Vref, RX VrefLevel [Byte0]: 33
1710 23:07:07.464265 [Byte1]: 33
1711 23:07:07.464824
1712 23:07:07.467619 Set Vref, RX VrefLevel [Byte0]: 34
1713 23:07:07.470776 [Byte1]: 34
1714 23:07:07.474739
1715 23:07:07.475300 Set Vref, RX VrefLevel [Byte0]: 35
1716 23:07:07.477940 [Byte1]: 35
1717 23:07:07.482292
1718 23:07:07.482843 Set Vref, RX VrefLevel [Byte0]: 36
1719 23:07:07.485172 [Byte1]: 36
1720 23:07:07.489712
1721 23:07:07.490167 Set Vref, RX VrefLevel [Byte0]: 37
1722 23:07:07.492818 [Byte1]: 37
1723 23:07:07.497232
1724 23:07:07.497686 Set Vref, RX VrefLevel [Byte0]: 38
1725 23:07:07.501165 [Byte1]: 38
1726 23:07:07.504862
1727 23:07:07.505546 Set Vref, RX VrefLevel [Byte0]: 39
1728 23:07:07.507981 [Byte1]: 39
1729 23:07:07.512600
1730 23:07:07.513276 Set Vref, RX VrefLevel [Byte0]: 40
1731 23:07:07.515635 [Byte1]: 40
1732 23:07:07.520366
1733 23:07:07.520911 Set Vref, RX VrefLevel [Byte0]: 41
1734 23:07:07.523388 [Byte1]: 41
1735 23:07:07.528171
1736 23:07:07.528805 Set Vref, RX VrefLevel [Byte0]: 42
1737 23:07:07.531082 [Byte1]: 42
1738 23:07:07.535750
1739 23:07:07.536362 Set Vref, RX VrefLevel [Byte0]: 43
1740 23:07:07.538566 [Byte1]: 43
1741 23:07:07.543362
1742 23:07:07.543814 Set Vref, RX VrefLevel [Byte0]: 44
1743 23:07:07.547100 [Byte1]: 44
1744 23:07:07.551431
1745 23:07:07.552054 Set Vref, RX VrefLevel [Byte0]: 45
1746 23:07:07.554252 [Byte1]: 45
1747 23:07:07.558536
1748 23:07:07.559095 Set Vref, RX VrefLevel [Byte0]: 46
1749 23:07:07.561779 [Byte1]: 46
1750 23:07:07.566255
1751 23:07:07.566810 Set Vref, RX VrefLevel [Byte0]: 47
1752 23:07:07.569438 [Byte1]: 47
1753 23:07:07.573922
1754 23:07:07.574478 Set Vref, RX VrefLevel [Byte0]: 48
1755 23:07:07.577012 [Byte1]: 48
1756 23:07:07.581558
1757 23:07:07.582110 Set Vref, RX VrefLevel [Byte0]: 49
1758 23:07:07.584973 [Byte1]: 49
1759 23:07:07.589184
1760 23:07:07.589738 Set Vref, RX VrefLevel [Byte0]: 50
1761 23:07:07.592609 [Byte1]: 50
1762 23:07:07.596818
1763 23:07:07.597286 Set Vref, RX VrefLevel [Byte0]: 51
1764 23:07:07.599981 [Byte1]: 51
1765 23:07:07.604769
1766 23:07:07.605517 Set Vref, RX VrefLevel [Byte0]: 52
1767 23:07:07.607830 [Byte1]: 52
1768 23:07:07.612392
1769 23:07:07.612962 Set Vref, RX VrefLevel [Byte0]: 53
1770 23:07:07.615220 [Byte1]: 53
1771 23:07:07.620145
1772 23:07:07.620769 Set Vref, RX VrefLevel [Byte0]: 54
1773 23:07:07.622947 [Byte1]: 54
1774 23:07:07.627176
1775 23:07:07.627723 Set Vref, RX VrefLevel [Byte0]: 55
1776 23:07:07.630622 [Byte1]: 55
1777 23:07:07.634984
1778 23:07:07.635491 Set Vref, RX VrefLevel [Byte0]: 56
1779 23:07:07.637968 [Byte1]: 56
1780 23:07:07.642651
1781 23:07:07.643117 Set Vref, RX VrefLevel [Byte0]: 57
1782 23:07:07.646117 [Byte1]: 57
1783 23:07:07.650188
1784 23:07:07.650736 Set Vref, RX VrefLevel [Byte0]: 58
1785 23:07:07.653528 [Byte1]: 58
1786 23:07:07.658162
1787 23:07:07.658616 Set Vref, RX VrefLevel [Byte0]: 59
1788 23:07:07.661010 [Byte1]: 59
1789 23:07:07.665915
1790 23:07:07.666468 Set Vref, RX VrefLevel [Byte0]: 60
1791 23:07:07.668899 [Byte1]: 60
1792 23:07:07.673496
1793 23:07:07.674053 Set Vref, RX VrefLevel [Byte0]: 61
1794 23:07:07.676794 [Byte1]: 61
1795 23:07:07.680749
1796 23:07:07.681205 Set Vref, RX VrefLevel [Byte0]: 62
1797 23:07:07.684748 [Byte1]: 62
1798 23:07:07.688586
1799 23:07:07.689041 Set Vref, RX VrefLevel [Byte0]: 63
1800 23:07:07.691945 [Byte1]: 63
1801 23:07:07.696496
1802 23:07:07.697056 Set Vref, RX VrefLevel [Byte0]: 64
1803 23:07:07.699755 [Byte1]: 64
1804 23:07:07.704134
1805 23:07:07.704794 Set Vref, RX VrefLevel [Byte0]: 65
1806 23:07:07.706890 [Byte1]: 65
1807 23:07:07.711688
1808 23:07:07.712272 Set Vref, RX VrefLevel [Byte0]: 66
1809 23:07:07.715258 [Byte1]: 66
1810 23:07:07.719876
1811 23:07:07.720478 Set Vref, RX VrefLevel [Byte0]: 67
1812 23:07:07.722815 [Byte1]: 67
1813 23:07:07.727240
1814 23:07:07.727793 Set Vref, RX VrefLevel [Byte0]: 68
1815 23:07:07.730294 [Byte1]: 68
1816 23:07:07.734159
1817 23:07:07.734613 Set Vref, RX VrefLevel [Byte0]: 69
1818 23:07:07.737910 [Byte1]: 69
1819 23:07:07.742418
1820 23:07:07.743052 Set Vref, RX VrefLevel [Byte0]: 70
1821 23:07:07.745807 [Byte1]: 70
1822 23:07:07.749574
1823 23:07:07.750028 Set Vref, RX VrefLevel [Byte0]: 71
1824 23:07:07.753356 [Byte1]: 71
1825 23:07:07.757266
1826 23:07:07.757830 Set Vref, RX VrefLevel [Byte0]: 72
1827 23:07:07.760911 [Byte1]: 72
1828 23:07:07.764849
1829 23:07:07.765306 Set Vref, RX VrefLevel [Byte0]: 73
1830 23:07:07.768227 [Byte1]: 73
1831 23:07:07.772804
1832 23:07:07.773258 Set Vref, RX VrefLevel [Byte0]: 74
1833 23:07:07.775905 [Byte1]: 74
1834 23:07:07.780471
1835 23:07:07.780922 Final RX Vref Byte 0 = 59 to rank0
1836 23:07:07.783785 Final RX Vref Byte 1 = 59 to rank0
1837 23:07:07.786862 Final RX Vref Byte 0 = 59 to rank1
1838 23:07:07.790282 Final RX Vref Byte 1 = 59 to rank1==
1839 23:07:07.793839 Dram Type= 6, Freq= 0, CH_1, rank 0
1840 23:07:07.800232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1841 23:07:07.800802 ==
1842 23:07:07.801165 DQS Delay:
1843 23:07:07.801560 DQS0 = 0, DQS1 = 0
1844 23:07:07.803375 DQM Delay:
1845 23:07:07.803887 DQM0 = 81, DQM1 = 70
1846 23:07:07.806765 DQ Delay:
1847 23:07:07.810539 DQ0 =88, DQ1 =76, DQ2 =68, DQ3 =76
1848 23:07:07.811089 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
1849 23:07:07.813989 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =64
1850 23:07:07.816802 DQ12 =80, DQ13 =76, DQ14 =76, DQ15 =76
1851 23:07:07.820927
1852 23:07:07.821480
1853 23:07:07.826704 [DQSOSCAuto] RK0, (LSB)MR18= 0xe19, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 406 ps
1854 23:07:07.830419 CH1 RK0: MR19=606, MR18=E19
1855 23:07:07.836924 CH1_RK0: MR19=0x606, MR18=0xE19, DQSOSC=403, MR23=63, INC=90, DEC=60
1856 23:07:07.837503
1857 23:07:07.840227 ----->DramcWriteLeveling(PI) begin...
1858 23:07:07.840799 ==
1859 23:07:07.843698 Dram Type= 6, Freq= 0, CH_1, rank 1
1860 23:07:07.847328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1861 23:07:07.847903 ==
1862 23:07:07.850422 Write leveling (Byte 0): 30 => 30
1863 23:07:07.853827 Write leveling (Byte 1): 30 => 30
1864 23:07:07.857042 DramcWriteLeveling(PI) end<-----
1865 23:07:07.857594
1866 23:07:07.857956 ==
1867 23:07:07.859953 Dram Type= 6, Freq= 0, CH_1, rank 1
1868 23:07:07.863357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1869 23:07:07.863817 ==
1870 23:07:07.867098 [Gating] SW mode calibration
1871 23:07:07.873808 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1872 23:07:07.880308 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1873 23:07:07.883656 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1874 23:07:07.887314 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1875 23:07:07.893607 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1876 23:07:07.897151 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1877 23:07:07.900311 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 23:07:07.906724 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 23:07:07.910643 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 23:07:07.913607 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 23:07:07.920255 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 23:07:07.923309 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 23:07:07.926545 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 23:07:07.933588 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 23:07:07.937236 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 23:07:07.940104 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 23:07:07.943723 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 23:07:07.949726 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 23:07:07.953013 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 23:07:07.956811 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1891 23:07:07.963162 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1892 23:07:07.967167 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 23:07:07.970274 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 23:07:07.976746 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 23:07:07.980111 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 23:07:07.983045 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 23:07:07.989647 0 9 0 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
1898 23:07:07.993626 0 9 4 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
1899 23:07:07.997037 0 9 8 | B1->B0 | 2b2b 3434 | 1 1 | (1 1) (1 1)
1900 23:07:08.003862 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1901 23:07:08.007012 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1902 23:07:08.010151 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1903 23:07:08.016667 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1904 23:07:08.019860 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1905 23:07:08.022980 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1906 23:07:08.030341 0 10 4 | B1->B0 | 3030 2c2c | 1 0 | (1 1) (1 0)
1907 23:07:08.033091 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 23:07:08.036895 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 23:07:08.039989 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 23:07:08.046345 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1911 23:07:08.049704 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1912 23:07:08.053393 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1913 23:07:08.060347 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1914 23:07:08.063161 0 11 4 | B1->B0 | 2c2c 3939 | 0 0 | (0 0) (0 0)
1915 23:07:08.066745 0 11 8 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
1916 23:07:08.073543 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1917 23:07:08.076725 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1918 23:07:08.080112 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1919 23:07:08.086690 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1920 23:07:08.089783 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1921 23:07:08.093317 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1922 23:07:08.100053 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1923 23:07:08.103363 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1924 23:07:08.106306 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1925 23:07:08.113094 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 23:07:08.116385 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 23:07:08.119732 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 23:07:08.126473 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 23:07:08.129913 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 23:07:08.133403 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 23:07:08.139394 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 23:07:08.142714 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 23:07:08.146485 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 23:07:08.152670 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 23:07:08.156569 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 23:07:08.159406 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 23:07:08.166792 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 23:07:08.169825 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1939 23:07:08.173316 Total UI for P1: 0, mck2ui 16
1940 23:07:08.176573 best dqsien dly found for B0: ( 0, 14, 2)
1941 23:07:08.179699 Total UI for P1: 0, mck2ui 16
1942 23:07:08.183293 best dqsien dly found for B1: ( 0, 14, 2)
1943 23:07:08.186458 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1944 23:07:08.189397 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1945 23:07:08.189860
1946 23:07:08.192767 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1947 23:07:08.196168 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1948 23:07:08.199752 [Gating] SW calibration Done
1949 23:07:08.200390 ==
1950 23:07:08.202690 Dram Type= 6, Freq= 0, CH_1, rank 1
1951 23:07:08.206257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1952 23:07:08.206720 ==
1953 23:07:08.209443 RX Vref Scan: 0
1954 23:07:08.209898
1955 23:07:08.210258 RX Vref 0 -> 0, step: 1
1956 23:07:08.210593
1957 23:07:08.212611 RX Delay -130 -> 252, step: 16
1958 23:07:08.219651 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1959 23:07:08.223150 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1960 23:07:08.226356 iDelay=222, Bit 2, Center 61 (-66 ~ 189) 256
1961 23:07:08.229467 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1962 23:07:08.232931 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1963 23:07:08.236364 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1964 23:07:08.242867 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1965 23:07:08.246508 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1966 23:07:08.249619 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1967 23:07:08.252662 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1968 23:07:08.256434 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1969 23:07:08.263117 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1970 23:07:08.266683 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1971 23:07:08.269720 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1972 23:07:08.272987 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1973 23:07:08.276602 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1974 23:07:08.279353 ==
1975 23:07:08.283162 Dram Type= 6, Freq= 0, CH_1, rank 1
1976 23:07:08.286514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1977 23:07:08.287087 ==
1978 23:07:08.287583 DQS Delay:
1979 23:07:08.290262 DQS0 = 0, DQS1 = 0
1980 23:07:08.290836 DQM Delay:
1981 23:07:08.293393 DQM0 = 78, DQM1 = 71
1982 23:07:08.293872 DQ Delay:
1983 23:07:08.296648 DQ0 =85, DQ1 =69, DQ2 =61, DQ3 =77
1984 23:07:08.299594 DQ4 =77, DQ5 =85, DQ6 =93, DQ7 =77
1985 23:07:08.302879 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =61
1986 23:07:08.306411 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1987 23:07:08.306893
1988 23:07:08.307378
1989 23:07:08.307836 ==
1990 23:07:08.309809 Dram Type= 6, Freq= 0, CH_1, rank 1
1991 23:07:08.312800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1992 23:07:08.313285 ==
1993 23:07:08.313771
1994 23:07:08.314226
1995 23:07:08.316012 TX Vref Scan disable
1996 23:07:08.319794 == TX Byte 0 ==
1997 23:07:08.323442 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1998 23:07:08.325990 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1999 23:07:08.329683 == TX Byte 1 ==
2000 23:07:08.332806 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2001 23:07:08.336190 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2002 23:07:08.336708 ==
2003 23:07:08.339801 Dram Type= 6, Freq= 0, CH_1, rank 1
2004 23:07:08.342653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2005 23:07:08.346158 ==
2006 23:07:08.357635 TX Vref=22, minBit 5, minWin=27, winSum=446
2007 23:07:08.360800 TX Vref=24, minBit 5, minWin=27, winSum=450
2008 23:07:08.364164 TX Vref=26, minBit 1, minWin=27, winSum=453
2009 23:07:08.367793 TX Vref=28, minBit 1, minWin=27, winSum=455
2010 23:07:08.371239 TX Vref=30, minBit 1, minWin=27, winSum=458
2011 23:07:08.374201 TX Vref=32, minBit 1, minWin=27, winSum=457
2012 23:07:08.380667 [TxChooseVref] Worse bit 1, Min win 27, Win sum 458, Final Vref 30
2013 23:07:08.381246
2014 23:07:08.383761 Final TX Range 1 Vref 30
2015 23:07:08.384389
2016 23:07:08.384883 ==
2017 23:07:08.387547 Dram Type= 6, Freq= 0, CH_1, rank 1
2018 23:07:08.390965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2019 23:07:08.391452 ==
2020 23:07:08.391941
2021 23:07:08.393812
2022 23:07:08.394293 TX Vref Scan disable
2023 23:07:08.397572 == TX Byte 0 ==
2024 23:07:08.400987 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
2025 23:07:08.403800 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
2026 23:07:08.407495 == TX Byte 1 ==
2027 23:07:08.410537 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2028 23:07:08.416775 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2029 23:07:08.417335
2030 23:07:08.417830 [DATLAT]
2031 23:07:08.418289 Freq=800, CH1 RK1
2032 23:07:08.418741
2033 23:07:08.420757 DATLAT Default: 0xa
2034 23:07:08.421287 0, 0xFFFF, sum = 0
2035 23:07:08.424054 1, 0xFFFF, sum = 0
2036 23:07:08.424583 2, 0xFFFF, sum = 0
2037 23:07:08.427162 3, 0xFFFF, sum = 0
2038 23:07:08.427750 4, 0xFFFF, sum = 0
2039 23:07:08.430916 5, 0xFFFF, sum = 0
2040 23:07:08.433492 6, 0xFFFF, sum = 0
2041 23:07:08.433977 7, 0xFFFF, sum = 0
2042 23:07:08.436938 8, 0xFFFF, sum = 0
2043 23:07:08.437426 9, 0x0, sum = 1
2044 23:07:08.437918 10, 0x0, sum = 2
2045 23:07:08.440274 11, 0x0, sum = 3
2046 23:07:08.440778 12, 0x0, sum = 4
2047 23:07:08.443681 best_step = 10
2048 23:07:08.444111
2049 23:07:08.444588 ==
2050 23:07:08.447397 Dram Type= 6, Freq= 0, CH_1, rank 1
2051 23:07:08.450525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2052 23:07:08.451054 ==
2053 23:07:08.453617 RX Vref Scan: 0
2054 23:07:08.454058
2055 23:07:08.454496 RX Vref 0 -> 0, step: 1
2056 23:07:08.454913
2057 23:07:08.457337 RX Delay -111 -> 252, step: 8
2058 23:07:08.464376 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
2059 23:07:08.467276 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2060 23:07:08.470873 iDelay=209, Bit 2, Center 64 (-55 ~ 184) 240
2061 23:07:08.473751 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
2062 23:07:08.476992 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
2063 23:07:08.484396 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2064 23:07:08.487297 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2065 23:07:08.490302 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2066 23:07:08.494079 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
2067 23:07:08.496933 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2068 23:07:08.503642 iDelay=209, Bit 10, Center 76 (-47 ~ 200) 248
2069 23:07:08.507650 iDelay=209, Bit 11, Center 72 (-47 ~ 192) 240
2070 23:07:08.510365 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2071 23:07:08.514379 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2072 23:07:08.517424 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
2073 23:07:08.523991 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2074 23:07:08.524638 ==
2075 23:07:08.527082 Dram Type= 6, Freq= 0, CH_1, rank 1
2076 23:07:08.530963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2077 23:07:08.531518 ==
2078 23:07:08.531887 DQS Delay:
2079 23:07:08.534260 DQS0 = 0, DQS1 = 0
2080 23:07:08.534814 DQM Delay:
2081 23:07:08.537149 DQM0 = 77, DQM1 = 74
2082 23:07:08.537607 DQ Delay:
2083 23:07:08.540533 DQ0 =80, DQ1 =72, DQ2 =64, DQ3 =72
2084 23:07:08.544037 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2085 23:07:08.547214 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =72
2086 23:07:08.550360 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =80
2087 23:07:08.550820
2088 23:07:08.551184
2089 23:07:08.557509 [DQSOSCAuto] RK1, (LSB)MR18= 0x2037, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 401 ps
2090 23:07:08.560994 CH1 RK1: MR19=606, MR18=2037
2091 23:07:08.567795 CH1_RK1: MR19=0x606, MR18=0x2037, DQSOSC=395, MR23=63, INC=94, DEC=63
2092 23:07:08.571073 [RxdqsGatingPostProcess] freq 800
2093 23:07:08.577529 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2094 23:07:08.580836 Pre-setting of DQS Precalculation
2095 23:07:08.584170 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2096 23:07:08.591066 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2097 23:07:08.597151 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2098 23:07:08.597613
2099 23:07:08.597972
2100 23:07:08.601151 [Calibration Summary] 1600 Mbps
2101 23:07:08.604371 CH 0, Rank 0
2102 23:07:08.604932 SW Impedance : PASS
2103 23:07:08.607673 DUTY Scan : NO K
2104 23:07:08.610409 ZQ Calibration : PASS
2105 23:07:08.610900 Jitter Meter : NO K
2106 23:07:08.613951 CBT Training : PASS
2107 23:07:08.617122 Write leveling : PASS
2108 23:07:08.617579 RX DQS gating : PASS
2109 23:07:08.620423 RX DQ/DQS(RDDQC) : PASS
2110 23:07:08.620881 TX DQ/DQS : PASS
2111 23:07:08.623907 RX DATLAT : PASS
2112 23:07:08.627281 RX DQ/DQS(Engine): PASS
2113 23:07:08.627699 TX OE : NO K
2114 23:07:08.631181 All Pass.
2115 23:07:08.631688
2116 23:07:08.632019 CH 0, Rank 1
2117 23:07:08.634666 SW Impedance : PASS
2118 23:07:08.635206 DUTY Scan : NO K
2119 23:07:08.637378 ZQ Calibration : PASS
2120 23:07:08.640671 Jitter Meter : NO K
2121 23:07:08.641084 CBT Training : PASS
2122 23:07:08.644635 Write leveling : PASS
2123 23:07:08.647489 RX DQS gating : PASS
2124 23:07:08.647907 RX DQ/DQS(RDDQC) : PASS
2125 23:07:08.651045 TX DQ/DQS : PASS
2126 23:07:08.651564 RX DATLAT : PASS
2127 23:07:08.654465 RX DQ/DQS(Engine): PASS
2128 23:07:08.657962 TX OE : NO K
2129 23:07:08.658488 All Pass.
2130 23:07:08.658841
2131 23:07:08.659152 CH 1, Rank 0
2132 23:07:08.660896 SW Impedance : PASS
2133 23:07:08.664251 DUTY Scan : NO K
2134 23:07:08.664670 ZQ Calibration : PASS
2135 23:07:08.667313 Jitter Meter : NO K
2136 23:07:08.670876 CBT Training : PASS
2137 23:07:08.671389 Write leveling : PASS
2138 23:07:08.674578 RX DQS gating : PASS
2139 23:07:08.677059 RX DQ/DQS(RDDQC) : PASS
2140 23:07:08.677476 TX DQ/DQS : PASS
2141 23:07:08.680666 RX DATLAT : PASS
2142 23:07:08.684261 RX DQ/DQS(Engine): PASS
2143 23:07:08.684775 TX OE : NO K
2144 23:07:08.687411 All Pass.
2145 23:07:08.687914
2146 23:07:08.688295 CH 1, Rank 1
2147 23:07:08.690682 SW Impedance : PASS
2148 23:07:08.691196 DUTY Scan : NO K
2149 23:07:08.694234 ZQ Calibration : PASS
2150 23:07:08.697638 Jitter Meter : NO K
2151 23:07:08.698147 CBT Training : PASS
2152 23:07:08.700813 Write leveling : PASS
2153 23:07:08.704349 RX DQS gating : PASS
2154 23:07:08.704856 RX DQ/DQS(RDDQC) : PASS
2155 23:07:08.707062 TX DQ/DQS : PASS
2156 23:07:08.707480 RX DATLAT : PASS
2157 23:07:08.710833 RX DQ/DQS(Engine): PASS
2158 23:07:08.713930 TX OE : NO K
2159 23:07:08.714446 All Pass.
2160 23:07:08.714780
2161 23:07:08.717654 DramC Write-DBI off
2162 23:07:08.718186 PER_BANK_REFRESH: Hybrid Mode
2163 23:07:08.720645 TX_TRACKING: ON
2164 23:07:08.724107 [GetDramInforAfterCalByMRR] Vendor 6.
2165 23:07:08.727721 [GetDramInforAfterCalByMRR] Revision 606.
2166 23:07:08.731226 [GetDramInforAfterCalByMRR] Revision 2 0.
2167 23:07:08.731749 MR0 0x3b3b
2168 23:07:08.734043 MR8 0x5151
2169 23:07:08.737612 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2170 23:07:08.738034
2171 23:07:08.738362 MR0 0x3b3b
2172 23:07:08.741008 MR8 0x5151
2173 23:07:08.743890 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2174 23:07:08.744350
2175 23:07:08.751151 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2176 23:07:08.754551 [FAST_K] Save calibration result to emmc
2177 23:07:08.757552 [FAST_K] Save calibration result to emmc
2178 23:07:08.760893 dram_init: config_dvfs: 1
2179 23:07:08.763905 dramc_set_vcore_voltage set vcore to 662500
2180 23:07:08.767561 Read voltage for 1200, 2
2181 23:07:08.768082 Vio18 = 0
2182 23:07:08.770829 Vcore = 662500
2183 23:07:08.771341 Vdram = 0
2184 23:07:08.771674 Vddq = 0
2185 23:07:08.773992 Vmddr = 0
2186 23:07:08.777076 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2187 23:07:08.784391 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2188 23:07:08.784949 MEM_TYPE=3, freq_sel=15
2189 23:07:08.787211 sv_algorithm_assistance_LP4_1600
2190 23:07:08.793787 ============ PULL DRAM RESETB DOWN ============
2191 23:07:08.797210 ========== PULL DRAM RESETB DOWN end =========
2192 23:07:08.800725 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2193 23:07:08.804246 ===================================
2194 23:07:08.807123 LPDDR4 DRAM CONFIGURATION
2195 23:07:08.810530 ===================================
2196 23:07:08.811049 EX_ROW_EN[0] = 0x0
2197 23:07:08.813977 EX_ROW_EN[1] = 0x0
2198 23:07:08.817432 LP4Y_EN = 0x0
2199 23:07:08.817947 WORK_FSP = 0x0
2200 23:07:08.820968 WL = 0x4
2201 23:07:08.821380 RL = 0x4
2202 23:07:08.824064 BL = 0x2
2203 23:07:08.824621 RPST = 0x0
2204 23:07:08.827305 RD_PRE = 0x0
2205 23:07:08.827734 WR_PRE = 0x1
2206 23:07:08.830408 WR_PST = 0x0
2207 23:07:08.830824 DBI_WR = 0x0
2208 23:07:08.833839 DBI_RD = 0x0
2209 23:07:08.834359 OTF = 0x1
2210 23:07:08.837262 ===================================
2211 23:07:08.840342 ===================================
2212 23:07:08.843959 ANA top config
2213 23:07:08.847475 ===================================
2214 23:07:08.847889 DLL_ASYNC_EN = 0
2215 23:07:08.850463 ALL_SLAVE_EN = 0
2216 23:07:08.853805 NEW_RANK_MODE = 1
2217 23:07:08.857676 DLL_IDLE_MODE = 1
2218 23:07:08.858188 LP45_APHY_COMB_EN = 1
2219 23:07:08.860325 TX_ODT_DIS = 1
2220 23:07:08.864320 NEW_8X_MODE = 1
2221 23:07:08.867460 ===================================
2222 23:07:08.870881 ===================================
2223 23:07:08.874457 data_rate = 2400
2224 23:07:08.877623 CKR = 1
2225 23:07:08.880649 DQ_P2S_RATIO = 8
2226 23:07:08.884421 ===================================
2227 23:07:08.884981 CA_P2S_RATIO = 8
2228 23:07:08.887702 DQ_CA_OPEN = 0
2229 23:07:08.890767 DQ_SEMI_OPEN = 0
2230 23:07:08.894033 CA_SEMI_OPEN = 0
2231 23:07:08.897300 CA_FULL_RATE = 0
2232 23:07:08.897714 DQ_CKDIV4_EN = 0
2233 23:07:08.900817 CA_CKDIV4_EN = 0
2234 23:07:08.904359 CA_PREDIV_EN = 0
2235 23:07:08.907421 PH8_DLY = 17
2236 23:07:08.910534 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2237 23:07:08.913696 DQ_AAMCK_DIV = 4
2238 23:07:08.914114 CA_AAMCK_DIV = 4
2239 23:07:08.917400 CA_ADMCK_DIV = 4
2240 23:07:08.920727 DQ_TRACK_CA_EN = 0
2241 23:07:08.923943 CA_PICK = 1200
2242 23:07:08.927370 CA_MCKIO = 1200
2243 23:07:08.930574 MCKIO_SEMI = 0
2244 23:07:08.933831 PLL_FREQ = 2366
2245 23:07:08.937052 DQ_UI_PI_RATIO = 32
2246 23:07:08.937595 CA_UI_PI_RATIO = 0
2247 23:07:08.940388 ===================================
2248 23:07:08.943749 ===================================
2249 23:07:08.947480 memory_type:LPDDR4
2250 23:07:08.950651 GP_NUM : 10
2251 23:07:08.951166 SRAM_EN : 1
2252 23:07:08.953582 MD32_EN : 0
2253 23:07:08.957736 ===================================
2254 23:07:08.960798 [ANA_INIT] >>>>>>>>>>>>>>
2255 23:07:08.961309 <<<<<< [CONFIGURE PHASE]: ANA_TX
2256 23:07:08.964189 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2257 23:07:08.967395 ===================================
2258 23:07:08.970678 data_rate = 2400,PCW = 0X5b00
2259 23:07:08.974455 ===================================
2260 23:07:08.977703 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2261 23:07:08.984378 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2262 23:07:08.990517 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2263 23:07:08.993497 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2264 23:07:08.997017 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2265 23:07:09.000245 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2266 23:07:09.004307 [ANA_INIT] flow start
2267 23:07:09.004823 [ANA_INIT] PLL >>>>>>>>
2268 23:07:09.007146 [ANA_INIT] PLL <<<<<<<<
2269 23:07:09.010501 [ANA_INIT] MIDPI >>>>>>>>
2270 23:07:09.010936 [ANA_INIT] MIDPI <<<<<<<<
2271 23:07:09.013619 [ANA_INIT] DLL >>>>>>>>
2272 23:07:09.017332 [ANA_INIT] DLL <<<<<<<<
2273 23:07:09.017846 [ANA_INIT] flow end
2274 23:07:09.024045 ============ LP4 DIFF to SE enter ============
2275 23:07:09.027428 ============ LP4 DIFF to SE exit ============
2276 23:07:09.030581 [ANA_INIT] <<<<<<<<<<<<<
2277 23:07:09.033814 [Flow] Enable top DCM control >>>>>
2278 23:07:09.036862 [Flow] Enable top DCM control <<<<<
2279 23:07:09.037285 Enable DLL master slave shuffle
2280 23:07:09.043472 ==============================================================
2281 23:07:09.047051 Gating Mode config
2282 23:07:09.050400 ==============================================================
2283 23:07:09.053803 Config description:
2284 23:07:09.063987 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2285 23:07:09.070690 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2286 23:07:09.073947 SELPH_MODE 0: By rank 1: By Phase
2287 23:07:09.080573 ==============================================================
2288 23:07:09.083998 GAT_TRACK_EN = 1
2289 23:07:09.086936 RX_GATING_MODE = 2
2290 23:07:09.090721 RX_GATING_TRACK_MODE = 2
2291 23:07:09.091274 SELPH_MODE = 1
2292 23:07:09.093918 PICG_EARLY_EN = 1
2293 23:07:09.097053 VALID_LAT_VALUE = 1
2294 23:07:09.103761 ==============================================================
2295 23:07:09.106843 Enter into Gating configuration >>>>
2296 23:07:09.110630 Exit from Gating configuration <<<<
2297 23:07:09.113530 Enter into DVFS_PRE_config >>>>>
2298 23:07:09.123830 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2299 23:07:09.127141 Exit from DVFS_PRE_config <<<<<
2300 23:07:09.130402 Enter into PICG configuration >>>>
2301 23:07:09.133599 Exit from PICG configuration <<<<
2302 23:07:09.137151 [RX_INPUT] configuration >>>>>
2303 23:07:09.140768 [RX_INPUT] configuration <<<<<
2304 23:07:09.143698 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2305 23:07:09.150745 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2306 23:07:09.156782 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2307 23:07:09.164095 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2308 23:07:09.166790 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2309 23:07:09.173640 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2310 23:07:09.177179 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2311 23:07:09.183766 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2312 23:07:09.186993 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2313 23:07:09.190610 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2314 23:07:09.193796 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2315 23:07:09.200278 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2316 23:07:09.203756 ===================================
2317 23:07:09.204398 LPDDR4 DRAM CONFIGURATION
2318 23:07:09.207384 ===================================
2319 23:07:09.210481 EX_ROW_EN[0] = 0x0
2320 23:07:09.213371 EX_ROW_EN[1] = 0x0
2321 23:07:09.213847 LP4Y_EN = 0x0
2322 23:07:09.216740 WORK_FSP = 0x0
2323 23:07:09.217343 WL = 0x4
2324 23:07:09.220653 RL = 0x4
2325 23:07:09.221189 BL = 0x2
2326 23:07:09.223354 RPST = 0x0
2327 23:07:09.223831 RD_PRE = 0x0
2328 23:07:09.226672 WR_PRE = 0x1
2329 23:07:09.227179 WR_PST = 0x0
2330 23:07:09.230690 DBI_WR = 0x0
2331 23:07:09.231171 DBI_RD = 0x0
2332 23:07:09.234205 OTF = 0x1
2333 23:07:09.236752 ===================================
2334 23:07:09.240089 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2335 23:07:09.243791 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2336 23:07:09.250172 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2337 23:07:09.253389 ===================================
2338 23:07:09.253823 LPDDR4 DRAM CONFIGURATION
2339 23:07:09.256481 ===================================
2340 23:07:09.260391 EX_ROW_EN[0] = 0x10
2341 23:07:09.263565 EX_ROW_EN[1] = 0x0
2342 23:07:09.264093 LP4Y_EN = 0x0
2343 23:07:09.266493 WORK_FSP = 0x0
2344 23:07:09.266921 WL = 0x4
2345 23:07:09.269800 RL = 0x4
2346 23:07:09.270237 BL = 0x2
2347 23:07:09.273279 RPST = 0x0
2348 23:07:09.273712 RD_PRE = 0x0
2349 23:07:09.276986 WR_PRE = 0x1
2350 23:07:09.277420 WR_PST = 0x0
2351 23:07:09.279995 DBI_WR = 0x0
2352 23:07:09.280463 DBI_RD = 0x0
2353 23:07:09.283522 OTF = 0x1
2354 23:07:09.286753 ===================================
2355 23:07:09.293584 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2356 23:07:09.294022 ==
2357 23:07:09.297079 Dram Type= 6, Freq= 0, CH_0, rank 0
2358 23:07:09.300606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2359 23:07:09.301134 ==
2360 23:07:09.303678 [Duty_Offset_Calibration]
2361 23:07:09.304131 B0:2 B1:0 CA:3
2362 23:07:09.304555
2363 23:07:09.306703 [DutyScan_Calibration_Flow] k_type=0
2364 23:07:09.316288
2365 23:07:09.316697 ==CLK 0==
2366 23:07:09.319698 Final CLK duty delay cell = 0
2367 23:07:09.322823 [0] MAX Duty = 5031%(X100), DQS PI = 12
2368 23:07:09.326484 [0] MIN Duty = 4875%(X100), DQS PI = 58
2369 23:07:09.326794 [0] AVG Duty = 4953%(X100)
2370 23:07:09.329527
2371 23:07:09.333280 CH0 CLK Duty spec in!! Max-Min= 156%
2372 23:07:09.336499 [DutyScan_Calibration_Flow] ====Done====
2373 23:07:09.336807
2374 23:07:09.339533 [DutyScan_Calibration_Flow] k_type=1
2375 23:07:09.355121
2376 23:07:09.355430 ==DQS 0 ==
2377 23:07:09.358373 Final DQS duty delay cell = 0
2378 23:07:09.361791 [0] MAX Duty = 5062%(X100), DQS PI = 14
2379 23:07:09.364886 [0] MIN Duty = 4907%(X100), DQS PI = 46
2380 23:07:09.365197 [0] AVG Duty = 4984%(X100)
2381 23:07:09.368048
2382 23:07:09.368392 ==DQS 1 ==
2383 23:07:09.371659 Final DQS duty delay cell = -4
2384 23:07:09.375136 [-4] MAX Duty = 4969%(X100), DQS PI = 8
2385 23:07:09.378334 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2386 23:07:09.381801 [-4] AVG Duty = 4938%(X100)
2387 23:07:09.382269
2388 23:07:09.385054 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2389 23:07:09.385516
2390 23:07:09.388774 CH0 DQS 1 Duty spec in!! Max-Min= 62%
2391 23:07:09.392628 [DutyScan_Calibration_Flow] ====Done====
2392 23:07:09.393202
2393 23:07:09.394922 [DutyScan_Calibration_Flow] k_type=3
2394 23:07:09.412898
2395 23:07:09.413442 ==DQM 0 ==
2396 23:07:09.415853 Final DQM duty delay cell = 0
2397 23:07:09.419180 [0] MAX Duty = 5124%(X100), DQS PI = 28
2398 23:07:09.422891 [0] MIN Duty = 4907%(X100), DQS PI = 46
2399 23:07:09.423447 [0] AVG Duty = 5015%(X100)
2400 23:07:09.425834
2401 23:07:09.426289 ==DQM 1 ==
2402 23:07:09.429404 Final DQM duty delay cell = 4
2403 23:07:09.432789 [4] MAX Duty = 5124%(X100), DQS PI = 50
2404 23:07:09.436157 [4] MIN Duty = 5000%(X100), DQS PI = 14
2405 23:07:09.436784 [4] AVG Duty = 5062%(X100)
2406 23:07:09.439086
2407 23:07:09.442670 CH0 DQM 0 Duty spec in!! Max-Min= 217%
2408 23:07:09.443131
2409 23:07:09.445802 CH0 DQM 1 Duty spec in!! Max-Min= 124%
2410 23:07:09.449257 [DutyScan_Calibration_Flow] ====Done====
2411 23:07:09.449806
2412 23:07:09.452232 [DutyScan_Calibration_Flow] k_type=2
2413 23:07:09.467577
2414 23:07:09.468130 ==DQ 0 ==
2415 23:07:09.470446 Final DQ duty delay cell = -4
2416 23:07:09.474038 [-4] MAX Duty = 5000%(X100), DQS PI = 12
2417 23:07:09.477638 [-4] MIN Duty = 4907%(X100), DQS PI = 52
2418 23:07:09.480895 [-4] AVG Duty = 4953%(X100)
2419 23:07:09.481456
2420 23:07:09.481819 ==DQ 1 ==
2421 23:07:09.484397 Final DQ duty delay cell = -4
2422 23:07:09.487695 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2423 23:07:09.491000 [-4] MIN Duty = 4876%(X100), DQS PI = 18
2424 23:07:09.494344 [-4] AVG Duty = 4938%(X100)
2425 23:07:09.494894
2426 23:07:09.497355 CH0 DQ 0 Duty spec in!! Max-Min= 93%
2427 23:07:09.497814
2428 23:07:09.500668 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2429 23:07:09.503661 [DutyScan_Calibration_Flow] ====Done====
2430 23:07:09.504122 ==
2431 23:07:09.507049 Dram Type= 6, Freq= 0, CH_1, rank 0
2432 23:07:09.510447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2433 23:07:09.511013 ==
2434 23:07:09.514246 [Duty_Offset_Calibration]
2435 23:07:09.514795 B0:1 B1:-2 CA:0
2436 23:07:09.515161
2437 23:07:09.517299 [DutyScan_Calibration_Flow] k_type=0
2438 23:07:09.528511
2439 23:07:09.529058 ==CLK 0==
2440 23:07:09.531206 Final CLK duty delay cell = 0
2441 23:07:09.534981 [0] MAX Duty = 5031%(X100), DQS PI = 20
2442 23:07:09.537965 [0] MIN Duty = 4844%(X100), DQS PI = 2
2443 23:07:09.538518 [0] AVG Duty = 4937%(X100)
2444 23:07:09.538885
2445 23:07:09.541047 CH1 CLK Duty spec in!! Max-Min= 187%
2446 23:07:09.547764 [DutyScan_Calibration_Flow] ====Done====
2447 23:07:09.548377
2448 23:07:09.551030 [DutyScan_Calibration_Flow] k_type=1
2449 23:07:09.566233
2450 23:07:09.566780 ==DQS 0 ==
2451 23:07:09.569546 Final DQS duty delay cell = -4
2452 23:07:09.573132 [-4] MAX Duty = 5000%(X100), DQS PI = 24
2453 23:07:09.576499 [-4] MIN Duty = 4876%(X100), DQS PI = 52
2454 23:07:09.579764 [-4] AVG Duty = 4938%(X100)
2455 23:07:09.580360
2456 23:07:09.580733 ==DQS 1 ==
2457 23:07:09.583027 Final DQS duty delay cell = 0
2458 23:07:09.586525 [0] MAX Duty = 5093%(X100), DQS PI = 0
2459 23:07:09.590066 [0] MIN Duty = 4844%(X100), DQS PI = 26
2460 23:07:09.592791 [0] AVG Duty = 4968%(X100)
2461 23:07:09.593465
2462 23:07:09.596084 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2463 23:07:09.596760
2464 23:07:09.599356 CH1 DQS 1 Duty spec in!! Max-Min= 249%
2465 23:07:09.603275 [DutyScan_Calibration_Flow] ====Done====
2466 23:07:09.603848
2467 23:07:09.606096 [DutyScan_Calibration_Flow] k_type=3
2468 23:07:09.623139
2469 23:07:09.623699 ==DQM 0 ==
2470 23:07:09.626386 Final DQM duty delay cell = 0
2471 23:07:09.630017 [0] MAX Duty = 5000%(X100), DQS PI = 22
2472 23:07:09.633380 [0] MIN Duty = 4844%(X100), DQS PI = 52
2473 23:07:09.636683 [0] AVG Duty = 4922%(X100)
2474 23:07:09.637252
2475 23:07:09.637742 ==DQM 1 ==
2476 23:07:09.639799 Final DQM duty delay cell = 0
2477 23:07:09.643367 [0] MAX Duty = 5031%(X100), DQS PI = 36
2478 23:07:09.646365 [0] MIN Duty = 4907%(X100), DQS PI = 0
2479 23:07:09.649585 [0] AVG Duty = 4969%(X100)
2480 23:07:09.650064
2481 23:07:09.653416 CH1 DQM 0 Duty spec in!! Max-Min= 156%
2482 23:07:09.653985
2483 23:07:09.656519 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2484 23:07:09.660034 [DutyScan_Calibration_Flow] ====Done====
2485 23:07:09.660659
2486 23:07:09.663133 [DutyScan_Calibration_Flow] k_type=2
2487 23:07:09.679729
2488 23:07:09.680351 ==DQ 0 ==
2489 23:07:09.682993 Final DQ duty delay cell = 0
2490 23:07:09.686205 [0] MAX Duty = 5093%(X100), DQS PI = 20
2491 23:07:09.689227 [0] MIN Duty = 4907%(X100), DQS PI = 56
2492 23:07:09.689803 [0] AVG Duty = 5000%(X100)
2493 23:07:09.693022
2494 23:07:09.693584 ==DQ 1 ==
2495 23:07:09.695919 Final DQ duty delay cell = 0
2496 23:07:09.699180 [0] MAX Duty = 5124%(X100), DQS PI = 36
2497 23:07:09.703031 [0] MIN Duty = 4969%(X100), DQS PI = 26
2498 23:07:09.703604 [0] AVG Duty = 5046%(X100)
2499 23:07:09.706106
2500 23:07:09.709055 CH1 DQ 0 Duty spec in!! Max-Min= 186%
2501 23:07:09.709535
2502 23:07:09.712754 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2503 23:07:09.716021 [DutyScan_Calibration_Flow] ====Done====
2504 23:07:09.719536 nWR fixed to 30
2505 23:07:09.720114 [ModeRegInit_LP4] CH0 RK0
2506 23:07:09.722373 [ModeRegInit_LP4] CH0 RK1
2507 23:07:09.725934 [ModeRegInit_LP4] CH1 RK0
2508 23:07:09.729090 [ModeRegInit_LP4] CH1 RK1
2509 23:07:09.729573 match AC timing 7
2510 23:07:09.735946 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2511 23:07:09.739603 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2512 23:07:09.742572 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2513 23:07:09.748851 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2514 23:07:09.752582 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2515 23:07:09.753133 ==
2516 23:07:09.755696 Dram Type= 6, Freq= 0, CH_0, rank 0
2517 23:07:09.759789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2518 23:07:09.760390 ==
2519 23:07:09.766305 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2520 23:07:09.772706 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
2521 23:07:09.779942 [CA 0] Center 40 (10~71) winsize 62
2522 23:07:09.782733 [CA 1] Center 39 (9~70) winsize 62
2523 23:07:09.786443 [CA 2] Center 36 (6~66) winsize 61
2524 23:07:09.789976 [CA 3] Center 35 (5~66) winsize 62
2525 23:07:09.792759 [CA 4] Center 34 (4~65) winsize 62
2526 23:07:09.796337 [CA 5] Center 33 (3~63) winsize 61
2527 23:07:09.796795
2528 23:07:09.799608 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2529 23:07:09.800168
2530 23:07:09.803063 [CATrainingPosCal] consider 1 rank data
2531 23:07:09.806374 u2DelayCellTimex100 = 270/100 ps
2532 23:07:09.810097 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2533 23:07:09.813104 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2534 23:07:09.819365 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2535 23:07:09.823174 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2536 23:07:09.826163 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2537 23:07:09.829553 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2538 23:07:09.830012
2539 23:07:09.832989 CA PerBit enable=1, Macro0, CA PI delay=33
2540 23:07:09.833445
2541 23:07:09.836168 [CBTSetCACLKResult] CA Dly = 33
2542 23:07:09.836664 CS Dly: 7 (0~38)
2543 23:07:09.839400 ==
2544 23:07:09.839853 Dram Type= 6, Freq= 0, CH_0, rank 1
2545 23:07:09.845951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2546 23:07:09.846442 ==
2547 23:07:09.849271 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2548 23:07:09.856667 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2549 23:07:09.865870 [CA 0] Center 40 (10~70) winsize 61
2550 23:07:09.868940 [CA 1] Center 39 (9~70) winsize 62
2551 23:07:09.872461 [CA 2] Center 35 (5~66) winsize 62
2552 23:07:09.875728 [CA 3] Center 35 (5~66) winsize 62
2553 23:07:09.879109 [CA 4] Center 34 (4~65) winsize 62
2554 23:07:09.882291 [CA 5] Center 33 (3~64) winsize 62
2555 23:07:09.882848
2556 23:07:09.885960 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2557 23:07:09.886521
2558 23:07:09.889139 [CATrainingPosCal] consider 2 rank data
2559 23:07:09.892179 u2DelayCellTimex100 = 270/100 ps
2560 23:07:09.896078 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2561 23:07:09.899092 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2562 23:07:09.906012 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2563 23:07:09.908721 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2564 23:07:09.911877 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2565 23:07:09.915722 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2566 23:07:09.916318
2567 23:07:09.919125 CA PerBit enable=1, Macro0, CA PI delay=33
2568 23:07:09.919579
2569 23:07:09.922496 [CBTSetCACLKResult] CA Dly = 33
2570 23:07:09.922892 CS Dly: 8 (0~40)
2571 23:07:09.923230
2572 23:07:09.925629 ----->DramcWriteLeveling(PI) begin...
2573 23:07:09.928758 ==
2574 23:07:09.932399 Dram Type= 6, Freq= 0, CH_0, rank 0
2575 23:07:09.936110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2576 23:07:09.936721 ==
2577 23:07:09.939040 Write leveling (Byte 0): 32 => 32
2578 23:07:09.942230 Write leveling (Byte 1): 30 => 30
2579 23:07:09.945519 DramcWriteLeveling(PI) end<-----
2580 23:07:09.945977
2581 23:07:09.946379 ==
2582 23:07:09.948830 Dram Type= 6, Freq= 0, CH_0, rank 0
2583 23:07:09.952075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2584 23:07:09.952567 ==
2585 23:07:09.955970 [Gating] SW mode calibration
2586 23:07:09.962184 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2587 23:07:09.968797 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2588 23:07:09.972566 0 15 0 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
2589 23:07:09.975932 0 15 4 | B1->B0 | 2424 3333 | 0 0 | (0 0) (0 0)
2590 23:07:09.978862 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2591 23:07:09.985564 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2592 23:07:09.988868 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2593 23:07:09.992361 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2594 23:07:09.999041 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2595 23:07:10.002225 0 15 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2596 23:07:10.005325 1 0 0 | B1->B0 | 3333 2929 | 0 0 | (0 1) (0 0)
2597 23:07:10.012172 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2598 23:07:10.015542 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2599 23:07:10.018546 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2600 23:07:10.025070 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2601 23:07:10.028881 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2602 23:07:10.032227 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2603 23:07:10.038978 1 0 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
2604 23:07:10.041926 1 1 0 | B1->B0 | 2626 3131 | 0 0 | (0 0) (0 0)
2605 23:07:10.045664 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2606 23:07:10.052517 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2607 23:07:10.055564 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2608 23:07:10.058851 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2609 23:07:10.065338 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2610 23:07:10.069048 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2611 23:07:10.071933 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2612 23:07:10.078744 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2613 23:07:10.082244 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 23:07:10.085817 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 23:07:10.088736 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 23:07:10.095849 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 23:07:10.098960 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 23:07:10.102640 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 23:07:10.109063 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 23:07:10.112175 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 23:07:10.115978 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 23:07:10.122100 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 23:07:10.125256 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 23:07:10.128914 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 23:07:10.135744 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 23:07:10.138718 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 23:07:10.142203 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2628 23:07:10.148842 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2629 23:07:10.151946 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2630 23:07:10.155336 Total UI for P1: 0, mck2ui 16
2631 23:07:10.159306 best dqsien dly found for B0: ( 1, 3, 30)
2632 23:07:10.162536 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2633 23:07:10.165725 Total UI for P1: 0, mck2ui 16
2634 23:07:10.168956 best dqsien dly found for B1: ( 1, 4, 2)
2635 23:07:10.172131 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2636 23:07:10.175237 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2637 23:07:10.175788
2638 23:07:10.178513 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2639 23:07:10.185416 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2640 23:07:10.185975 [Gating] SW calibration Done
2641 23:07:10.186346 ==
2642 23:07:10.188464 Dram Type= 6, Freq= 0, CH_0, rank 0
2643 23:07:10.195468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2644 23:07:10.196033 ==
2645 23:07:10.196472 RX Vref Scan: 0
2646 23:07:10.196820
2647 23:07:10.198805 RX Vref 0 -> 0, step: 1
2648 23:07:10.199256
2649 23:07:10.202106 RX Delay -40 -> 252, step: 8
2650 23:07:10.205017 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2651 23:07:10.208608 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
2652 23:07:10.212006 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2653 23:07:10.218625 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2654 23:07:10.221934 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2655 23:07:10.225356 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2656 23:07:10.228621 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2657 23:07:10.231914 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2658 23:07:10.235486 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2659 23:07:10.241853 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2660 23:07:10.245474 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2661 23:07:10.248679 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2662 23:07:10.251848 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2663 23:07:10.254871 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2664 23:07:10.262171 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2665 23:07:10.265375 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2666 23:07:10.265930 ==
2667 23:07:10.268702 Dram Type= 6, Freq= 0, CH_0, rank 0
2668 23:07:10.272474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2669 23:07:10.273041 ==
2670 23:07:10.275666 DQS Delay:
2671 23:07:10.276268 DQS0 = 0, DQS1 = 0
2672 23:07:10.276650 DQM Delay:
2673 23:07:10.278644 DQM0 = 112, DQM1 = 102
2674 23:07:10.279100 DQ Delay:
2675 23:07:10.281940 DQ0 =111, DQ1 =111, DQ2 =115, DQ3 =107
2676 23:07:10.284938 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2677 23:07:10.288602 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
2678 23:07:10.292516 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =111
2679 23:07:10.295293
2680 23:07:10.295836
2681 23:07:10.296396 ==
2682 23:07:10.298275 Dram Type= 6, Freq= 0, CH_0, rank 0
2683 23:07:10.302009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2684 23:07:10.302563 ==
2685 23:07:10.303060
2686 23:07:10.303538
2687 23:07:10.304900 TX Vref Scan disable
2688 23:07:10.305358 == TX Byte 0 ==
2689 23:07:10.311630 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2690 23:07:10.315026 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2691 23:07:10.315558 == TX Byte 1 ==
2692 23:07:10.321789 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2693 23:07:10.325363 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2694 23:07:10.325916 ==
2695 23:07:10.328527 Dram Type= 6, Freq= 0, CH_0, rank 0
2696 23:07:10.332108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2697 23:07:10.332730 ==
2698 23:07:10.344395 TX Vref=22, minBit 1, minWin=25, winSum=418
2699 23:07:10.347260 TX Vref=24, minBit 1, minWin=26, winSum=421
2700 23:07:10.350760 TX Vref=26, minBit 4, minWin=26, winSum=430
2701 23:07:10.353956 TX Vref=28, minBit 4, minWin=26, winSum=432
2702 23:07:10.357447 TX Vref=30, minBit 4, minWin=26, winSum=432
2703 23:07:10.363861 TX Vref=32, minBit 8, minWin=26, winSum=429
2704 23:07:10.367825 [TxChooseVref] Worse bit 4, Min win 26, Win sum 432, Final Vref 28
2705 23:07:10.368442
2706 23:07:10.371201 Final TX Range 1 Vref 28
2707 23:07:10.371755
2708 23:07:10.372136 ==
2709 23:07:10.374069 Dram Type= 6, Freq= 0, CH_0, rank 0
2710 23:07:10.377471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2711 23:07:10.378029 ==
2712 23:07:10.380848
2713 23:07:10.381401
2714 23:07:10.381834 TX Vref Scan disable
2715 23:07:10.383740 == TX Byte 0 ==
2716 23:07:10.387538 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2717 23:07:10.394277 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2718 23:07:10.394831 == TX Byte 1 ==
2719 23:07:10.397213 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2720 23:07:10.400955 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2721 23:07:10.403889
2722 23:07:10.404541 [DATLAT]
2723 23:07:10.405083 Freq=1200, CH0 RK0
2724 23:07:10.405595
2725 23:07:10.407476 DATLAT Default: 0xd
2726 23:07:10.408036 0, 0xFFFF, sum = 0
2727 23:07:10.410796 1, 0xFFFF, sum = 0
2728 23:07:10.411371 2, 0xFFFF, sum = 0
2729 23:07:10.413829 3, 0xFFFF, sum = 0
2730 23:07:10.414388 4, 0xFFFF, sum = 0
2731 23:07:10.417497 5, 0xFFFF, sum = 0
2732 23:07:10.418130 6, 0xFFFF, sum = 0
2733 23:07:10.421021 7, 0xFFFF, sum = 0
2734 23:07:10.423934 8, 0xFFFF, sum = 0
2735 23:07:10.424433 9, 0xFFFF, sum = 0
2736 23:07:10.427383 10, 0xFFFF, sum = 0
2737 23:07:10.428151 11, 0xFFFF, sum = 0
2738 23:07:10.430749 12, 0x0, sum = 1
2739 23:07:10.431308 13, 0x0, sum = 2
2740 23:07:10.434017 14, 0x0, sum = 3
2741 23:07:10.434580 15, 0x0, sum = 4
2742 23:07:10.434959 best_step = 13
2743 23:07:10.435297
2744 23:07:10.437115 ==
2745 23:07:10.440799 Dram Type= 6, Freq= 0, CH_0, rank 0
2746 23:07:10.443924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2747 23:07:10.444460 ==
2748 23:07:10.444836 RX Vref Scan: 1
2749 23:07:10.445177
2750 23:07:10.447480 Set Vref Range= 32 -> 127
2751 23:07:10.448041
2752 23:07:10.450930 RX Vref 32 -> 127, step: 1
2753 23:07:10.451386
2754 23:07:10.454448 RX Delay -37 -> 252, step: 4
2755 23:07:10.454996
2756 23:07:10.457314 Set Vref, RX VrefLevel [Byte0]: 32
2757 23:07:10.460609 [Byte1]: 32
2758 23:07:10.461160
2759 23:07:10.463872 Set Vref, RX VrefLevel [Byte0]: 33
2760 23:07:10.467455 [Byte1]: 33
2761 23:07:10.470893
2762 23:07:10.471460 Set Vref, RX VrefLevel [Byte0]: 34
2763 23:07:10.473750 [Byte1]: 34
2764 23:07:10.478774
2765 23:07:10.479327 Set Vref, RX VrefLevel [Byte0]: 35
2766 23:07:10.482029 [Byte1]: 35
2767 23:07:10.486510
2768 23:07:10.487059 Set Vref, RX VrefLevel [Byte0]: 36
2769 23:07:10.490583 [Byte1]: 36
2770 23:07:10.494848
2771 23:07:10.495394 Set Vref, RX VrefLevel [Byte0]: 37
2772 23:07:10.498087 [Byte1]: 37
2773 23:07:10.502636
2774 23:07:10.503189 Set Vref, RX VrefLevel [Byte0]: 38
2775 23:07:10.505904 [Byte1]: 38
2776 23:07:10.510434
2777 23:07:10.510892 Set Vref, RX VrefLevel [Byte0]: 39
2778 23:07:10.513972 [Byte1]: 39
2779 23:07:10.518993
2780 23:07:10.519543 Set Vref, RX VrefLevel [Byte0]: 40
2781 23:07:10.521802 [Byte1]: 40
2782 23:07:10.526485
2783 23:07:10.527040 Set Vref, RX VrefLevel [Byte0]: 41
2784 23:07:10.529605 [Byte1]: 41
2785 23:07:10.534563
2786 23:07:10.535019 Set Vref, RX VrefLevel [Byte0]: 42
2787 23:07:10.538071 [Byte1]: 42
2788 23:07:10.543168
2789 23:07:10.543720 Set Vref, RX VrefLevel [Byte0]: 43
2790 23:07:10.546354 [Byte1]: 43
2791 23:07:10.550756
2792 23:07:10.551307 Set Vref, RX VrefLevel [Byte0]: 44
2793 23:07:10.553703 [Byte1]: 44
2794 23:07:10.558687
2795 23:07:10.559235 Set Vref, RX VrefLevel [Byte0]: 45
2796 23:07:10.561866 [Byte1]: 45
2797 23:07:10.566882
2798 23:07:10.567437 Set Vref, RX VrefLevel [Byte0]: 46
2799 23:07:10.569766 [Byte1]: 46
2800 23:07:10.574534
2801 23:07:10.577644 Set Vref, RX VrefLevel [Byte0]: 47
2802 23:07:10.578180 [Byte1]: 47
2803 23:07:10.582950
2804 23:07:10.583515 Set Vref, RX VrefLevel [Byte0]: 48
2805 23:07:10.586031 [Byte1]: 48
2806 23:07:10.591038
2807 23:07:10.591594 Set Vref, RX VrefLevel [Byte0]: 49
2808 23:07:10.594503 [Byte1]: 49
2809 23:07:10.598430
2810 23:07:10.598983 Set Vref, RX VrefLevel [Byte0]: 50
2811 23:07:10.602482 [Byte1]: 50
2812 23:07:10.606739
2813 23:07:10.607310 Set Vref, RX VrefLevel [Byte0]: 51
2814 23:07:10.609819 [Byte1]: 51
2815 23:07:10.614635
2816 23:07:10.615185 Set Vref, RX VrefLevel [Byte0]: 52
2817 23:07:10.618288 [Byte1]: 52
2818 23:07:10.622969
2819 23:07:10.623428 Set Vref, RX VrefLevel [Byte0]: 53
2820 23:07:10.626409 [Byte1]: 53
2821 23:07:10.630611
2822 23:07:10.631162 Set Vref, RX VrefLevel [Byte0]: 54
2823 23:07:10.634324 [Byte1]: 54
2824 23:07:10.639066
2825 23:07:10.639619 Set Vref, RX VrefLevel [Byte0]: 55
2826 23:07:10.642069 [Byte1]: 55
2827 23:07:10.646562
2828 23:07:10.647167 Set Vref, RX VrefLevel [Byte0]: 56
2829 23:07:10.649766 [Byte1]: 56
2830 23:07:10.654685
2831 23:07:10.655232 Set Vref, RX VrefLevel [Byte0]: 57
2832 23:07:10.657954 [Byte1]: 57
2833 23:07:10.662737
2834 23:07:10.663290 Set Vref, RX VrefLevel [Byte0]: 58
2835 23:07:10.665832 [Byte1]: 58
2836 23:07:10.670429
2837 23:07:10.670982 Set Vref, RX VrefLevel [Byte0]: 59
2838 23:07:10.674122 [Byte1]: 59
2839 23:07:10.678876
2840 23:07:10.679334 Set Vref, RX VrefLevel [Byte0]: 60
2841 23:07:10.682154 [Byte1]: 60
2842 23:07:10.686439
2843 23:07:10.686993 Set Vref, RX VrefLevel [Byte0]: 61
2844 23:07:10.689923 [Byte1]: 61
2845 23:07:10.694677
2846 23:07:10.695231 Set Vref, RX VrefLevel [Byte0]: 62
2847 23:07:10.697694 [Byte1]: 62
2848 23:07:10.702221
2849 23:07:10.702676 Set Vref, RX VrefLevel [Byte0]: 63
2850 23:07:10.706176 [Byte1]: 63
2851 23:07:10.710965
2852 23:07:10.711522 Set Vref, RX VrefLevel [Byte0]: 64
2853 23:07:10.714043 [Byte1]: 64
2854 23:07:10.718921
2855 23:07:10.719479 Set Vref, RX VrefLevel [Byte0]: 65
2856 23:07:10.722134 [Byte1]: 65
2857 23:07:10.726546
2858 23:07:10.727098 Set Vref, RX VrefLevel [Byte0]: 66
2859 23:07:10.729758 [Byte1]: 66
2860 23:07:10.734758
2861 23:07:10.735312 Set Vref, RX VrefLevel [Byte0]: 67
2862 23:07:10.737967 [Byte1]: 67
2863 23:07:10.742299
2864 23:07:10.742755 Set Vref, RX VrefLevel [Byte0]: 68
2865 23:07:10.745582 [Byte1]: 68
2866 23:07:10.750569
2867 23:07:10.751119 Set Vref, RX VrefLevel [Byte0]: 69
2868 23:07:10.754167 [Byte1]: 69
2869 23:07:10.758544
2870 23:07:10.759098 Set Vref, RX VrefLevel [Byte0]: 70
2871 23:07:10.762071 [Byte1]: 70
2872 23:07:10.766782
2873 23:07:10.767343 Set Vref, RX VrefLevel [Byte0]: 71
2874 23:07:10.770026 [Byte1]: 71
2875 23:07:10.774679
2876 23:07:10.775269 Set Vref, RX VrefLevel [Byte0]: 72
2877 23:07:10.777823 [Byte1]: 72
2878 23:07:10.782498
2879 23:07:10.783059 Set Vref, RX VrefLevel [Byte0]: 73
2880 23:07:10.785548 [Byte1]: 73
2881 23:07:10.790690
2882 23:07:10.791252 Final RX Vref Byte 0 = 61 to rank0
2883 23:07:10.794154 Final RX Vref Byte 1 = 47 to rank0
2884 23:07:10.797237 Final RX Vref Byte 0 = 61 to rank1
2885 23:07:10.800788 Final RX Vref Byte 1 = 47 to rank1==
2886 23:07:10.804039 Dram Type= 6, Freq= 0, CH_0, rank 0
2887 23:07:10.811074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2888 23:07:10.811636 ==
2889 23:07:10.812004 DQS Delay:
2890 23:07:10.812388 DQS0 = 0, DQS1 = 0
2891 23:07:10.815072 DQM Delay:
2892 23:07:10.815631 DQM0 = 111, DQM1 = 98
2893 23:07:10.817594 DQ Delay:
2894 23:07:10.820776 DQ0 =110, DQ1 =112, DQ2 =110, DQ3 =108
2895 23:07:10.823961 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120
2896 23:07:10.827324 DQ8 =90, DQ9 =82, DQ10 =100, DQ11 =92
2897 23:07:10.830915 DQ12 =104, DQ13 =104, DQ14 =112, DQ15 =106
2898 23:07:10.831477
2899 23:07:10.831843
2900 23:07:10.837887 [DQSOSCAuto] RK0, (LSB)MR18= 0xfefd, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 410 ps
2901 23:07:10.840679 CH0 RK0: MR19=303, MR18=FEFD
2902 23:07:10.847558 CH0_RK0: MR19=0x303, MR18=0xFEFD, DQSOSC=410, MR23=63, INC=39, DEC=26
2903 23:07:10.848118
2904 23:07:10.850357 ----->DramcWriteLeveling(PI) begin...
2905 23:07:10.850823 ==
2906 23:07:10.853956 Dram Type= 6, Freq= 0, CH_0, rank 1
2907 23:07:10.857398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2908 23:07:10.857953 ==
2909 23:07:10.860609 Write leveling (Byte 0): 33 => 33
2910 23:07:10.863855 Write leveling (Byte 1): 30 => 30
2911 23:07:10.867373 DramcWriteLeveling(PI) end<-----
2912 23:07:10.867924
2913 23:07:10.868368 ==
2914 23:07:10.870861 Dram Type= 6, Freq= 0, CH_0, rank 1
2915 23:07:10.877666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2916 23:07:10.878224 ==
2917 23:07:10.878596 [Gating] SW mode calibration
2918 23:07:10.887542 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2919 23:07:10.890805 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2920 23:07:10.894044 0 15 0 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
2921 23:07:10.901078 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2922 23:07:10.904027 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2923 23:07:10.907387 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2924 23:07:10.914189 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2925 23:07:10.917497 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2926 23:07:10.920656 0 15 24 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
2927 23:07:10.927408 0 15 28 | B1->B0 | 3434 2525 | 1 1 | (1 1) (1 0)
2928 23:07:10.930941 1 0 0 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
2929 23:07:10.934141 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2930 23:07:10.941032 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2931 23:07:10.944309 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2932 23:07:10.947272 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2933 23:07:10.953878 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2934 23:07:10.957685 1 0 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
2935 23:07:10.960829 1 0 28 | B1->B0 | 2323 4444 | 0 1 | (0 0) (0 0)
2936 23:07:10.964351 1 1 0 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
2937 23:07:10.970902 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2938 23:07:10.974191 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2939 23:07:10.977083 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2940 23:07:10.983976 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2941 23:07:10.987203 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2942 23:07:10.990764 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2943 23:07:10.997148 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2944 23:07:11.000825 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2945 23:07:11.004153 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2946 23:07:11.010646 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2947 23:07:11.014165 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2948 23:07:11.016972 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2949 23:07:11.024422 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2950 23:07:11.027815 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2951 23:07:11.031136 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2952 23:07:11.037381 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2953 23:07:11.040648 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2954 23:07:11.044254 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2955 23:07:11.050331 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2956 23:07:11.053589 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2957 23:07:11.057066 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2958 23:07:11.060683 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2959 23:07:11.067564 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2960 23:07:11.070727 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2961 23:07:11.073922 Total UI for P1: 0, mck2ui 16
2962 23:07:11.076962 best dqsien dly found for B0: ( 1, 3, 28)
2963 23:07:11.080461 Total UI for P1: 0, mck2ui 16
2964 23:07:11.084332 best dqsien dly found for B1: ( 1, 3, 30)
2965 23:07:11.087266 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2966 23:07:11.090720 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2967 23:07:11.091289
2968 23:07:11.094269 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2969 23:07:11.096931 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2970 23:07:11.100803 [Gating] SW calibration Done
2971 23:07:11.101372 ==
2972 23:07:11.103638 Dram Type= 6, Freq= 0, CH_0, rank 1
2973 23:07:11.110362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2974 23:07:11.110942 ==
2975 23:07:11.111432 RX Vref Scan: 0
2976 23:07:11.111896
2977 23:07:11.113612 RX Vref 0 -> 0, step: 1
2978 23:07:11.114166
2979 23:07:11.117406 RX Delay -40 -> 252, step: 8
2980 23:07:11.120455 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2981 23:07:11.124159 iDelay=200, Bit 1, Center 111 (32 ~ 191) 160
2982 23:07:11.127576 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2983 23:07:11.130257 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2984 23:07:11.137518 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2985 23:07:11.140662 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2986 23:07:11.143966 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2987 23:07:11.147155 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2988 23:07:11.150406 iDelay=200, Bit 8, Center 87 (16 ~ 159) 144
2989 23:07:11.153871 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2990 23:07:11.160309 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2991 23:07:11.163707 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2992 23:07:11.167521 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2993 23:07:11.170582 iDelay=200, Bit 13, Center 103 (32 ~ 175) 144
2994 23:07:11.177418 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2995 23:07:11.180446 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2996 23:07:11.181034 ==
2997 23:07:11.184081 Dram Type= 6, Freq= 0, CH_0, rank 1
2998 23:07:11.187399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2999 23:07:11.187975 ==
3000 23:07:11.188538 DQS Delay:
3001 23:07:11.190701 DQS0 = 0, DQS1 = 0
3002 23:07:11.191271 DQM Delay:
3003 23:07:11.193744 DQM0 = 112, DQM1 = 100
3004 23:07:11.194318 DQ Delay:
3005 23:07:11.197148 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
3006 23:07:11.200336 DQ4 =115, DQ5 =103, DQ6 =119, DQ7 =123
3007 23:07:11.204016 DQ8 =87, DQ9 =83, DQ10 =103, DQ11 =95
3008 23:07:11.207626 DQ12 =107, DQ13 =103, DQ14 =111, DQ15 =111
3009 23:07:11.208237
3010 23:07:11.208741
3011 23:07:11.210268 ==
3012 23:07:11.214246 Dram Type= 6, Freq= 0, CH_0, rank 1
3013 23:07:11.217145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3014 23:07:11.217717 ==
3015 23:07:11.218215
3016 23:07:11.218674
3017 23:07:11.220333 TX Vref Scan disable
3018 23:07:11.220914 == TX Byte 0 ==
3019 23:07:11.223735 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3020 23:07:11.230227 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3021 23:07:11.230722 == TX Byte 1 ==
3022 23:07:11.234095 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3023 23:07:11.240433 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3024 23:07:11.240914 ==
3025 23:07:11.243881 Dram Type= 6, Freq= 0, CH_0, rank 1
3026 23:07:11.247025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3027 23:07:11.247512 ==
3028 23:07:11.259687 TX Vref=22, minBit 1, minWin=26, winSum=427
3029 23:07:11.262643 TX Vref=24, minBit 1, minWin=26, winSum=432
3030 23:07:11.266581 TX Vref=26, minBit 13, minWin=26, winSum=436
3031 23:07:11.269617 TX Vref=28, minBit 0, minWin=27, winSum=440
3032 23:07:11.273005 TX Vref=30, minBit 1, minWin=27, winSum=441
3033 23:07:11.276315 TX Vref=32, minBit 10, minWin=26, winSum=440
3034 23:07:11.282891 [TxChooseVref] Worse bit 1, Min win 27, Win sum 441, Final Vref 30
3035 23:07:11.283460
3036 23:07:11.286152 Final TX Range 1 Vref 30
3037 23:07:11.286717
3038 23:07:11.287204 ==
3039 23:07:11.289688 Dram Type= 6, Freq= 0, CH_0, rank 1
3040 23:07:11.293488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3041 23:07:11.294064 ==
3042 23:07:11.294557
3043 23:07:11.295958
3044 23:07:11.296512 TX Vref Scan disable
3045 23:07:11.299774 == TX Byte 0 ==
3046 23:07:11.303046 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3047 23:07:11.306788 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3048 23:07:11.309463 == TX Byte 1 ==
3049 23:07:11.313328 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3050 23:07:11.316526 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3051 23:07:11.317008
3052 23:07:11.319896 [DATLAT]
3053 23:07:11.320561 Freq=1200, CH0 RK1
3054 23:07:11.321057
3055 23:07:11.323390 DATLAT Default: 0xd
3056 23:07:11.323955 0, 0xFFFF, sum = 0
3057 23:07:11.326418 1, 0xFFFF, sum = 0
3058 23:07:11.326904 2, 0xFFFF, sum = 0
3059 23:07:11.329538 3, 0xFFFF, sum = 0
3060 23:07:11.330025 4, 0xFFFF, sum = 0
3061 23:07:11.332883 5, 0xFFFF, sum = 0
3062 23:07:11.333372 6, 0xFFFF, sum = 0
3063 23:07:11.335866 7, 0xFFFF, sum = 0
3064 23:07:11.339465 8, 0xFFFF, sum = 0
3065 23:07:11.340035 9, 0xFFFF, sum = 0
3066 23:07:11.342669 10, 0xFFFF, sum = 0
3067 23:07:11.343132 11, 0xFFFF, sum = 0
3068 23:07:11.346095 12, 0x0, sum = 1
3069 23:07:11.346560 13, 0x0, sum = 2
3070 23:07:11.349764 14, 0x0, sum = 3
3071 23:07:11.350359 15, 0x0, sum = 4
3072 23:07:11.350742 best_step = 13
3073 23:07:11.351075
3074 23:07:11.352993 ==
3075 23:07:11.355844 Dram Type= 6, Freq= 0, CH_0, rank 1
3076 23:07:11.359181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3077 23:07:11.359636 ==
3078 23:07:11.359993 RX Vref Scan: 0
3079 23:07:11.360396
3080 23:07:11.363005 RX Vref 0 -> 0, step: 1
3081 23:07:11.363563
3082 23:07:11.366390 RX Delay -37 -> 252, step: 4
3083 23:07:11.369389 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3084 23:07:11.375851 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3085 23:07:11.379216 iDelay=195, Bit 2, Center 108 (39 ~ 178) 140
3086 23:07:11.382579 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3087 23:07:11.386035 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3088 23:07:11.389357 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3089 23:07:11.395628 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3090 23:07:11.399218 iDelay=195, Bit 7, Center 118 (43 ~ 194) 152
3091 23:07:11.402457 iDelay=195, Bit 8, Center 88 (19 ~ 158) 140
3092 23:07:11.405784 iDelay=195, Bit 9, Center 80 (11 ~ 150) 140
3093 23:07:11.408948 iDelay=195, Bit 10, Center 100 (31 ~ 170) 140
3094 23:07:11.415604 iDelay=195, Bit 11, Center 90 (23 ~ 158) 136
3095 23:07:11.418947 iDelay=195, Bit 12, Center 108 (39 ~ 178) 140
3096 23:07:11.422201 iDelay=195, Bit 13, Center 106 (35 ~ 178) 144
3097 23:07:11.425546 iDelay=195, Bit 14, Center 112 (47 ~ 178) 132
3098 23:07:11.429270 iDelay=195, Bit 15, Center 108 (39 ~ 178) 140
3099 23:07:11.429729 ==
3100 23:07:11.431921 Dram Type= 6, Freq= 0, CH_0, rank 1
3101 23:07:11.438783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3102 23:07:11.439241 ==
3103 23:07:11.439650 DQS Delay:
3104 23:07:11.442290 DQS0 = 0, DQS1 = 0
3105 23:07:11.442746 DQM Delay:
3106 23:07:11.445325 DQM0 = 110, DQM1 = 99
3107 23:07:11.445803 DQ Delay:
3108 23:07:11.448743 DQ0 =108, DQ1 =112, DQ2 =108, DQ3 =108
3109 23:07:11.452307 DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =118
3110 23:07:11.455307 DQ8 =88, DQ9 =80, DQ10 =100, DQ11 =90
3111 23:07:11.459107 DQ12 =108, DQ13 =106, DQ14 =112, DQ15 =108
3112 23:07:11.459550
3113 23:07:11.459950
3114 23:07:11.469524 [DQSOSCAuto] RK1, (LSB)MR18= 0x11f8, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 403 ps
3115 23:07:11.470086 CH0 RK1: MR19=403, MR18=11F8
3116 23:07:11.475899 CH0_RK1: MR19=0x403, MR18=0x11F8, DQSOSC=403, MR23=63, INC=40, DEC=26
3117 23:07:11.479253 [RxdqsGatingPostProcess] freq 1200
3118 23:07:11.486107 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3119 23:07:11.488693 best DQS0 dly(2T, 0.5T) = (0, 11)
3120 23:07:11.492090 best DQS1 dly(2T, 0.5T) = (0, 12)
3121 23:07:11.495947 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3122 23:07:11.499296 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3123 23:07:11.499923 best DQS0 dly(2T, 0.5T) = (0, 11)
3124 23:07:11.502247 best DQS1 dly(2T, 0.5T) = (0, 11)
3125 23:07:11.506182 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3126 23:07:11.509110 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3127 23:07:11.512301 Pre-setting of DQS Precalculation
3128 23:07:11.519000 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3129 23:07:11.519585 ==
3130 23:07:11.522545 Dram Type= 6, Freq= 0, CH_1, rank 0
3131 23:07:11.525762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3132 23:07:11.526323 ==
3133 23:07:11.532358 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3134 23:07:11.535519 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3135 23:07:11.545910 [CA 0] Center 37 (7~67) winsize 61
3136 23:07:11.548904 [CA 1] Center 38 (8~68) winsize 61
3137 23:07:11.552003 [CA 2] Center 34 (4~64) winsize 61
3138 23:07:11.555845 [CA 3] Center 33 (3~64) winsize 62
3139 23:07:11.558754 [CA 4] Center 34 (4~64) winsize 61
3140 23:07:11.562182 [CA 5] Center 33 (3~63) winsize 61
3141 23:07:11.562742
3142 23:07:11.565710 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3143 23:07:11.566274
3144 23:07:11.569124 [CATrainingPosCal] consider 1 rank data
3145 23:07:11.572269 u2DelayCellTimex100 = 270/100 ps
3146 23:07:11.575442 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3147 23:07:11.579372 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3148 23:07:11.585955 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3149 23:07:11.588905 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3150 23:07:11.592377 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3151 23:07:11.595328 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3152 23:07:11.595845
3153 23:07:11.598795 CA PerBit enable=1, Macro0, CA PI delay=33
3154 23:07:11.599348
3155 23:07:11.602520 [CBTSetCACLKResult] CA Dly = 33
3156 23:07:11.603074 CS Dly: 5 (0~36)
3157 23:07:11.603437 ==
3158 23:07:11.605559 Dram Type= 6, Freq= 0, CH_1, rank 1
3159 23:07:11.611966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3160 23:07:11.612542 ==
3161 23:07:11.616007 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3162 23:07:11.622447 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3163 23:07:11.631581 [CA 0] Center 37 (7~67) winsize 61
3164 23:07:11.634463 [CA 1] Center 37 (7~68) winsize 62
3165 23:07:11.638117 [CA 2] Center 34 (4~65) winsize 62
3166 23:07:11.641356 [CA 3] Center 33 (3~64) winsize 62
3167 23:07:11.644596 [CA 4] Center 34 (4~65) winsize 62
3168 23:07:11.647773 [CA 5] Center 32 (2~63) winsize 62
3169 23:07:11.648282
3170 23:07:11.650811 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3171 23:07:11.651264
3172 23:07:11.654760 [CATrainingPosCal] consider 2 rank data
3173 23:07:11.657567 u2DelayCellTimex100 = 270/100 ps
3174 23:07:11.661296 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3175 23:07:11.664110 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3176 23:07:11.671168 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3177 23:07:11.674384 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3178 23:07:11.678312 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3179 23:07:11.681155 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3180 23:07:11.681608
3181 23:07:11.684582 CA PerBit enable=1, Macro0, CA PI delay=33
3182 23:07:11.685169
3183 23:07:11.687968 [CBTSetCACLKResult] CA Dly = 33
3184 23:07:11.688627 CS Dly: 7 (0~40)
3185 23:07:11.689015
3186 23:07:11.691318 ----->DramcWriteLeveling(PI) begin...
3187 23:07:11.694218 ==
3188 23:07:11.697684 Dram Type= 6, Freq= 0, CH_1, rank 0
3189 23:07:11.701070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3190 23:07:11.701637 ==
3191 23:07:11.704385 Write leveling (Byte 0): 24 => 24
3192 23:07:11.708181 Write leveling (Byte 1): 28 => 28
3193 23:07:11.710895 DramcWriteLeveling(PI) end<-----
3194 23:07:11.711366
3195 23:07:11.711838 ==
3196 23:07:11.714511 Dram Type= 6, Freq= 0, CH_1, rank 0
3197 23:07:11.717750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3198 23:07:11.718328 ==
3199 23:07:11.721108 [Gating] SW mode calibration
3200 23:07:11.727934 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3201 23:07:11.730881 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3202 23:07:11.737929 0 15 0 | B1->B0 | 3131 2d2c | 1 1 | (1 1) (1 1)
3203 23:07:11.740946 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3204 23:07:11.744293 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3205 23:07:11.750968 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3206 23:07:11.754459 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3207 23:07:11.757689 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3208 23:07:11.764499 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3209 23:07:11.767750 0 15 28 | B1->B0 | 2b2b 2c2c | 1 0 | (1 0) (0 1)
3210 23:07:11.771145 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3211 23:07:11.777865 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3212 23:07:11.781332 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3213 23:07:11.784516 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3214 23:07:11.791326 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3215 23:07:11.794218 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3216 23:07:11.797971 1 0 24 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
3217 23:07:11.804634 1 0 28 | B1->B0 | 4242 3b3b | 0 1 | (0 0) (0 0)
3218 23:07:11.807604 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3219 23:07:11.810876 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3220 23:07:11.817727 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3221 23:07:11.821199 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3222 23:07:11.824188 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3223 23:07:11.827922 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3224 23:07:11.834639 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3225 23:07:11.837770 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3226 23:07:11.841786 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3227 23:07:11.848320 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3228 23:07:11.851070 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3229 23:07:11.854315 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3230 23:07:11.861356 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3231 23:07:11.864771 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3232 23:07:11.867875 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3233 23:07:11.875043 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3234 23:07:11.877696 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3235 23:07:11.881171 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3236 23:07:11.887971 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3237 23:07:11.891598 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3238 23:07:11.894659 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3239 23:07:11.898445 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3240 23:07:11.904973 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3241 23:07:11.908185 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3242 23:07:11.911389 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3243 23:07:11.914919 Total UI for P1: 0, mck2ui 16
3244 23:07:11.917503 best dqsien dly found for B0: ( 1, 3, 28)
3245 23:07:11.921233 Total UI for P1: 0, mck2ui 16
3246 23:07:11.924684 best dqsien dly found for B1: ( 1, 3, 26)
3247 23:07:11.927585 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3248 23:07:11.931020 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3249 23:07:11.934607
3250 23:07:11.937685 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3251 23:07:11.941102 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3252 23:07:11.944245 [Gating] SW calibration Done
3253 23:07:11.944724 ==
3254 23:07:11.947861 Dram Type= 6, Freq= 0, CH_1, rank 0
3255 23:07:11.951350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3256 23:07:11.951874 ==
3257 23:07:11.952372 RX Vref Scan: 0
3258 23:07:11.952752
3259 23:07:11.954115 RX Vref 0 -> 0, step: 1
3260 23:07:11.954687
3261 23:07:11.958093 RX Delay -40 -> 252, step: 8
3262 23:07:11.960906 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3263 23:07:11.964399 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3264 23:07:11.971191 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3265 23:07:11.974566 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3266 23:07:11.977660 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3267 23:07:11.981307 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3268 23:07:11.984663 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3269 23:07:11.987896 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3270 23:07:11.994441 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3271 23:07:11.997916 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3272 23:07:12.000932 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3273 23:07:12.004385 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3274 23:07:12.008056 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3275 23:07:12.014819 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
3276 23:07:12.018105 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3277 23:07:12.020952 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3278 23:07:12.021409 ==
3279 23:07:12.024653 Dram Type= 6, Freq= 0, CH_1, rank 0
3280 23:07:12.028161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3281 23:07:12.031048 ==
3282 23:07:12.031763 DQS Delay:
3283 23:07:12.032181 DQS0 = 0, DQS1 = 0
3284 23:07:12.034724 DQM Delay:
3285 23:07:12.035277 DQM0 = 114, DQM1 = 105
3286 23:07:12.038120 DQ Delay:
3287 23:07:12.041061 DQ0 =123, DQ1 =107, DQ2 =99, DQ3 =115
3288 23:07:12.044433 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =115
3289 23:07:12.048030 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =103
3290 23:07:12.051667 DQ12 =115, DQ13 =111, DQ14 =111, DQ15 =111
3291 23:07:12.052278
3292 23:07:12.052658
3293 23:07:12.052996 ==
3294 23:07:12.054393 Dram Type= 6, Freq= 0, CH_1, rank 0
3295 23:07:12.058231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3296 23:07:12.058791 ==
3297 23:07:12.059155
3298 23:07:12.059491
3299 23:07:12.061676 TX Vref Scan disable
3300 23:07:12.064513 == TX Byte 0 ==
3301 23:07:12.068183 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3302 23:07:12.071333 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3303 23:07:12.074504 == TX Byte 1 ==
3304 23:07:12.077748 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3305 23:07:12.081228 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3306 23:07:12.081783 ==
3307 23:07:12.084510 Dram Type= 6, Freq= 0, CH_1, rank 0
3308 23:07:12.087746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3309 23:07:12.090897 ==
3310 23:07:12.101200 TX Vref=22, minBit 1, minWin=24, winSum=407
3311 23:07:12.104447 TX Vref=24, minBit 8, minWin=25, winSum=415
3312 23:07:12.108419 TX Vref=26, minBit 10, minWin=24, winSum=420
3313 23:07:12.110843 TX Vref=28, minBit 9, minWin=25, winSum=425
3314 23:07:12.114128 TX Vref=30, minBit 9, minWin=25, winSum=422
3315 23:07:12.117648 TX Vref=32, minBit 9, minWin=25, winSum=419
3316 23:07:12.124494 [TxChooseVref] Worse bit 9, Min win 25, Win sum 425, Final Vref 28
3317 23:07:12.125039
3318 23:07:12.127700 Final TX Range 1 Vref 28
3319 23:07:12.128301
3320 23:07:12.128677 ==
3321 23:07:12.131341 Dram Type= 6, Freq= 0, CH_1, rank 0
3322 23:07:12.134199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3323 23:07:12.134669 ==
3324 23:07:12.137889
3325 23:07:12.138342
3326 23:07:12.138699 TX Vref Scan disable
3327 23:07:12.141239 == TX Byte 0 ==
3328 23:07:12.144344 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3329 23:07:12.147944 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3330 23:07:12.151130 == TX Byte 1 ==
3331 23:07:12.154435 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3332 23:07:12.158383 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3333 23:07:12.158778
3334 23:07:12.161132 [DATLAT]
3335 23:07:12.161453 Freq=1200, CH1 RK0
3336 23:07:12.161709
3337 23:07:12.164370 DATLAT Default: 0xd
3338 23:07:12.164608 0, 0xFFFF, sum = 0
3339 23:07:12.167508 1, 0xFFFF, sum = 0
3340 23:07:12.167750 2, 0xFFFF, sum = 0
3341 23:07:12.171230 3, 0xFFFF, sum = 0
3342 23:07:12.171423 4, 0xFFFF, sum = 0
3343 23:07:12.174323 5, 0xFFFF, sum = 0
3344 23:07:12.174481 6, 0xFFFF, sum = 0
3345 23:07:12.177618 7, 0xFFFF, sum = 0
3346 23:07:12.177777 8, 0xFFFF, sum = 0
3347 23:07:12.180806 9, 0xFFFF, sum = 0
3348 23:07:12.180942 10, 0xFFFF, sum = 0
3349 23:07:12.184362 11, 0xFFFF, sum = 0
3350 23:07:12.184480 12, 0x0, sum = 1
3351 23:07:12.187527 13, 0x0, sum = 2
3352 23:07:12.187645 14, 0x0, sum = 3
3353 23:07:12.190458 15, 0x0, sum = 4
3354 23:07:12.190562 best_step = 13
3355 23:07:12.190644
3356 23:07:12.194100 ==
3357 23:07:12.194194 Dram Type= 6, Freq= 0, CH_1, rank 0
3358 23:07:12.200799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3359 23:07:12.200884 ==
3360 23:07:12.200950 RX Vref Scan: 1
3361 23:07:12.201011
3362 23:07:12.203739 Set Vref Range= 32 -> 127
3363 23:07:12.203823
3364 23:07:12.207142 RX Vref 32 -> 127, step: 1
3365 23:07:12.207225
3366 23:07:12.210743 RX Delay -21 -> 252, step: 4
3367 23:07:12.210824
3368 23:07:12.213834 Set Vref, RX VrefLevel [Byte0]: 32
3369 23:07:12.217243 [Byte1]: 32
3370 23:07:12.217325
3371 23:07:12.220644 Set Vref, RX VrefLevel [Byte0]: 33
3372 23:07:12.223812 [Byte1]: 33
3373 23:07:12.223893
3374 23:07:12.227403 Set Vref, RX VrefLevel [Byte0]: 34
3375 23:07:12.230606 [Byte1]: 34
3376 23:07:12.234496
3377 23:07:12.234577 Set Vref, RX VrefLevel [Byte0]: 35
3378 23:07:12.238062 [Byte1]: 35
3379 23:07:12.242533
3380 23:07:12.242612 Set Vref, RX VrefLevel [Byte0]: 36
3381 23:07:12.246228 [Byte1]: 36
3382 23:07:12.250563
3383 23:07:12.250664 Set Vref, RX VrefLevel [Byte0]: 37
3384 23:07:12.253666 [Byte1]: 37
3385 23:07:12.258689
3386 23:07:12.258788 Set Vref, RX VrefLevel [Byte0]: 38
3387 23:07:12.262213 [Byte1]: 38
3388 23:07:12.266764
3389 23:07:12.266951 Set Vref, RX VrefLevel [Byte0]: 39
3390 23:07:12.269756 [Byte1]: 39
3391 23:07:12.274742
3392 23:07:12.274876 Set Vref, RX VrefLevel [Byte0]: 40
3393 23:07:12.277856 [Byte1]: 40
3394 23:07:12.282667
3395 23:07:12.282816 Set Vref, RX VrefLevel [Byte0]: 41
3396 23:07:12.285859 [Byte1]: 41
3397 23:07:12.290178
3398 23:07:12.290311 Set Vref, RX VrefLevel [Byte0]: 42
3399 23:07:12.293562 [Byte1]: 42
3400 23:07:12.298267
3401 23:07:12.298399 Set Vref, RX VrefLevel [Byte0]: 43
3402 23:07:12.301486 [Byte1]: 43
3403 23:07:12.306048
3404 23:07:12.306179 Set Vref, RX VrefLevel [Byte0]: 44
3405 23:07:12.309158 [Byte1]: 44
3406 23:07:12.314142
3407 23:07:12.314276 Set Vref, RX VrefLevel [Byte0]: 45
3408 23:07:12.317354 [Byte1]: 45
3409 23:07:12.321905
3410 23:07:12.322036 Set Vref, RX VrefLevel [Byte0]: 46
3411 23:07:12.325174 [Byte1]: 46
3412 23:07:12.330066
3413 23:07:12.330198 Set Vref, RX VrefLevel [Byte0]: 47
3414 23:07:12.333241 [Byte1]: 47
3415 23:07:12.337674
3416 23:07:12.337807 Set Vref, RX VrefLevel [Byte0]: 48
3417 23:07:12.340983 [Byte1]: 48
3418 23:07:12.345766
3419 23:07:12.345901 Set Vref, RX VrefLevel [Byte0]: 49
3420 23:07:12.348753 [Byte1]: 49
3421 23:07:12.353359
3422 23:07:12.353474 Set Vref, RX VrefLevel [Byte0]: 50
3423 23:07:12.356658 [Byte1]: 50
3424 23:07:12.361532
3425 23:07:12.361631 Set Vref, RX VrefLevel [Byte0]: 51
3426 23:07:12.364850 [Byte1]: 51
3427 23:07:12.369857
3428 23:07:12.370016 Set Vref, RX VrefLevel [Byte0]: 52
3429 23:07:12.372870 [Byte1]: 52
3430 23:07:12.377658
3431 23:07:12.377792 Set Vref, RX VrefLevel [Byte0]: 53
3432 23:07:12.381060 [Byte1]: 53
3433 23:07:12.385577
3434 23:07:12.385703 Set Vref, RX VrefLevel [Byte0]: 54
3435 23:07:12.388698 [Byte1]: 54
3436 23:07:12.393083
3437 23:07:12.393164 Set Vref, RX VrefLevel [Byte0]: 55
3438 23:07:12.396383 [Byte1]: 55
3439 23:07:12.401370
3440 23:07:12.401450 Set Vref, RX VrefLevel [Byte0]: 56
3441 23:07:12.404664 [Byte1]: 56
3442 23:07:12.408823
3443 23:07:12.408903 Set Vref, RX VrefLevel [Byte0]: 57
3444 23:07:12.412119 [Byte1]: 57
3445 23:07:12.417047
3446 23:07:12.417128 Set Vref, RX VrefLevel [Byte0]: 58
3447 23:07:12.420080 [Byte1]: 58
3448 23:07:12.425017
3449 23:07:12.425109 Set Vref, RX VrefLevel [Byte0]: 59
3450 23:07:12.428446 [Byte1]: 59
3451 23:07:12.432934
3452 23:07:12.433036 Set Vref, RX VrefLevel [Byte0]: 60
3453 23:07:12.436016 [Byte1]: 60
3454 23:07:12.440763
3455 23:07:12.440881 Set Vref, RX VrefLevel [Byte0]: 61
3456 23:07:12.443929 [Byte1]: 61
3457 23:07:12.449018
3458 23:07:12.449252 Set Vref, RX VrefLevel [Byte0]: 62
3459 23:07:12.451982 [Byte1]: 62
3460 23:07:12.456826
3461 23:07:12.457081 Set Vref, RX VrefLevel [Byte0]: 63
3462 23:07:12.459982 [Byte1]: 63
3463 23:07:12.464934
3464 23:07:12.465258 Set Vref, RX VrefLevel [Byte0]: 64
3465 23:07:12.468021 [Byte1]: 64
3466 23:07:12.472788
3467 23:07:12.473196 Set Vref, RX VrefLevel [Byte0]: 65
3468 23:07:12.476134 [Byte1]: 65
3469 23:07:12.480867
3470 23:07:12.481436 Set Vref, RX VrefLevel [Byte0]: 66
3471 23:07:12.484347 [Byte1]: 66
3472 23:07:12.489058
3473 23:07:12.489709 Set Vref, RX VrefLevel [Byte0]: 67
3474 23:07:12.492321 [Byte1]: 67
3475 23:07:12.496483
3476 23:07:12.496943 Set Vref, RX VrefLevel [Byte0]: 68
3477 23:07:12.500289 [Byte1]: 68
3478 23:07:12.504750
3479 23:07:12.505222 Final RX Vref Byte 0 = 54 to rank0
3480 23:07:12.507785 Final RX Vref Byte 1 = 50 to rank0
3481 23:07:12.511099 Final RX Vref Byte 0 = 54 to rank1
3482 23:07:12.514882 Final RX Vref Byte 1 = 50 to rank1==
3483 23:07:12.517820 Dram Type= 6, Freq= 0, CH_1, rank 0
3484 23:07:12.521148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3485 23:07:12.524675 ==
3486 23:07:12.525227 DQS Delay:
3487 23:07:12.525708 DQS0 = 0, DQS1 = 0
3488 23:07:12.528063 DQM Delay:
3489 23:07:12.528571 DQM0 = 114, DQM1 = 106
3490 23:07:12.531408 DQ Delay:
3491 23:07:12.534755 DQ0 =118, DQ1 =110, DQ2 =104, DQ3 =112
3492 23:07:12.537849 DQ4 =112, DQ5 =124, DQ6 =126, DQ7 =112
3493 23:07:12.541594 DQ8 =92, DQ9 =100, DQ10 =104, DQ11 =100
3494 23:07:12.544672 DQ12 =114, DQ13 =112, DQ14 =114, DQ15 =114
3495 23:07:12.545186
3496 23:07:12.545578
3497 23:07:12.550988 [DQSOSCAuto] RK0, (LSB)MR18= 0xeef5, (MSB)MR19= 0x303, tDQSOscB0 = 414 ps tDQSOscB1 = 417 ps
3498 23:07:12.554732 CH1 RK0: MR19=303, MR18=EEF5
3499 23:07:12.561139 CH1_RK0: MR19=0x303, MR18=0xEEF5, DQSOSC=414, MR23=63, INC=38, DEC=25
3500 23:07:12.561597
3501 23:07:12.564520 ----->DramcWriteLeveling(PI) begin...
3502 23:07:12.564981 ==
3503 23:07:12.568105 Dram Type= 6, Freq= 0, CH_1, rank 1
3504 23:07:12.571364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3505 23:07:12.574327 ==
3506 23:07:12.574816 Write leveling (Byte 0): 23 => 23
3507 23:07:12.577760 Write leveling (Byte 1): 29 => 29
3508 23:07:12.581098 DramcWriteLeveling(PI) end<-----
3509 23:07:12.581735
3510 23:07:12.582217 ==
3511 23:07:12.584606 Dram Type= 6, Freq= 0, CH_1, rank 1
3512 23:07:12.591067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3513 23:07:12.591530 ==
3514 23:07:12.591885 [Gating] SW mode calibration
3515 23:07:12.601277 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3516 23:07:12.604550 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3517 23:07:12.607504 0 15 0 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
3518 23:07:12.614176 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3519 23:07:12.617636 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3520 23:07:12.620853 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3521 23:07:12.627825 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3522 23:07:12.631005 0 15 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
3523 23:07:12.634821 0 15 24 | B1->B0 | 3333 2424 | 0 0 | (1 0) (1 0)
3524 23:07:12.641168 0 15 28 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
3525 23:07:12.644436 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3526 23:07:12.647446 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3527 23:07:12.654428 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3528 23:07:12.657536 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3529 23:07:12.660948 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3530 23:07:12.668130 1 0 20 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 1)
3531 23:07:12.671408 1 0 24 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)
3532 23:07:12.674495 1 0 28 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3533 23:07:12.680854 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3534 23:07:12.684155 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3535 23:07:12.687410 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3536 23:07:12.694287 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3537 23:07:12.697668 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3538 23:07:12.700837 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3539 23:07:12.707177 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3540 23:07:12.710561 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3541 23:07:12.714207 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3542 23:07:12.720886 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3543 23:07:12.723837 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3544 23:07:12.727494 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3545 23:07:12.734016 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3546 23:07:12.736992 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3547 23:07:12.740718 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3548 23:07:12.747481 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3549 23:07:12.750474 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3550 23:07:12.754058 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3551 23:07:12.760155 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3552 23:07:12.763608 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3553 23:07:12.766862 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3554 23:07:12.770461 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3555 23:07:12.777402 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3556 23:07:12.780575 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3557 23:07:12.783772 Total UI for P1: 0, mck2ui 16
3558 23:07:12.786894 best dqsien dly found for B0: ( 1, 3, 24)
3559 23:07:12.790283 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3560 23:07:12.793355 Total UI for P1: 0, mck2ui 16
3561 23:07:12.796802 best dqsien dly found for B1: ( 1, 3, 26)
3562 23:07:12.800114 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3563 23:07:12.804014 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3564 23:07:12.806994
3565 23:07:12.810234 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3566 23:07:12.813669 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3567 23:07:12.817139 [Gating] SW calibration Done
3568 23:07:12.817646 ==
3569 23:07:12.820065 Dram Type= 6, Freq= 0, CH_1, rank 1
3570 23:07:12.823602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3571 23:07:12.824117 ==
3572 23:07:12.824513 RX Vref Scan: 0
3573 23:07:12.826973
3574 23:07:12.827495 RX Vref 0 -> 0, step: 1
3575 23:07:12.827823
3576 23:07:12.829869 RX Delay -40 -> 252, step: 8
3577 23:07:12.833431 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3578 23:07:12.836743 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3579 23:07:12.843747 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3580 23:07:12.846860 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3581 23:07:12.850219 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3582 23:07:12.852921 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3583 23:07:12.856684 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3584 23:07:12.863442 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3585 23:07:12.866387 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3586 23:07:12.869758 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3587 23:07:12.873118 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3588 23:07:12.876496 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3589 23:07:12.883127 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3590 23:07:12.886644 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3591 23:07:12.889806 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3592 23:07:12.892740 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3593 23:07:12.893305 ==
3594 23:07:12.895912 Dram Type= 6, Freq= 0, CH_1, rank 1
3595 23:07:12.902928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3596 23:07:12.903497 ==
3597 23:07:12.903864 DQS Delay:
3598 23:07:12.906163 DQS0 = 0, DQS1 = 0
3599 23:07:12.906618 DQM Delay:
3600 23:07:12.909638 DQM0 = 111, DQM1 = 109
3601 23:07:12.910114 DQ Delay:
3602 23:07:12.913127 DQ0 =115, DQ1 =111, DQ2 =99, DQ3 =107
3603 23:07:12.915943 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =111
3604 23:07:12.919543 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3605 23:07:12.922399 DQ12 =115, DQ13 =119, DQ14 =115, DQ15 =115
3606 23:07:12.922942
3607 23:07:12.923306
3608 23:07:12.923644 ==
3609 23:07:12.925808 Dram Type= 6, Freq= 0, CH_1, rank 1
3610 23:07:12.932091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3611 23:07:12.932581 ==
3612 23:07:12.932947
3613 23:07:12.933284
3614 23:07:12.933605 TX Vref Scan disable
3615 23:07:12.936059 == TX Byte 0 ==
3616 23:07:12.938907 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3617 23:07:12.942217 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3618 23:07:12.945656 == TX Byte 1 ==
3619 23:07:12.949108 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3620 23:07:12.955661 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3621 23:07:12.956299 ==
3622 23:07:12.958698 Dram Type= 6, Freq= 0, CH_1, rank 1
3623 23:07:12.962127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3624 23:07:12.962587 ==
3625 23:07:12.974014 TX Vref=22, minBit 9, minWin=25, winSum=429
3626 23:07:12.977182 TX Vref=24, minBit 2, minWin=26, winSum=430
3627 23:07:12.980512 TX Vref=26, minBit 8, minWin=26, winSum=433
3628 23:07:12.983863 TX Vref=28, minBit 0, minWin=25, winSum=433
3629 23:07:12.987126 TX Vref=30, minBit 4, minWin=26, winSum=433
3630 23:07:12.994100 TX Vref=32, minBit 8, minWin=25, winSum=432
3631 23:07:12.997401 [TxChooseVref] Worse bit 8, Min win 26, Win sum 433, Final Vref 26
3632 23:07:12.997974
3633 23:07:13.000389 Final TX Range 1 Vref 26
3634 23:07:13.000951
3635 23:07:13.001312 ==
3636 23:07:13.003546 Dram Type= 6, Freq= 0, CH_1, rank 1
3637 23:07:13.007221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3638 23:07:13.007920 ==
3639 23:07:13.010442
3640 23:07:13.011000
3641 23:07:13.011364 TX Vref Scan disable
3642 23:07:13.013738 == TX Byte 0 ==
3643 23:07:13.016975 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3644 23:07:13.023739 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3645 23:07:13.024360 == TX Byte 1 ==
3646 23:07:13.027358 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3647 23:07:13.033765 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3648 23:07:13.034336
3649 23:07:13.034704 [DATLAT]
3650 23:07:13.035129 Freq=1200, CH1 RK1
3651 23:07:13.035668
3652 23:07:13.036755 DATLAT Default: 0xd
3653 23:07:13.037216 0, 0xFFFF, sum = 0
3654 23:07:13.040038 1, 0xFFFF, sum = 0
3655 23:07:13.043630 2, 0xFFFF, sum = 0
3656 23:07:13.044091 3, 0xFFFF, sum = 0
3657 23:07:13.046923 4, 0xFFFF, sum = 0
3658 23:07:13.047385 5, 0xFFFF, sum = 0
3659 23:07:13.050262 6, 0xFFFF, sum = 0
3660 23:07:13.050725 7, 0xFFFF, sum = 0
3661 23:07:13.053221 8, 0xFFFF, sum = 0
3662 23:07:13.053688 9, 0xFFFF, sum = 0
3663 23:07:13.057041 10, 0xFFFF, sum = 0
3664 23:07:13.057505 11, 0xFFFF, sum = 0
3665 23:07:13.059817 12, 0x0, sum = 1
3666 23:07:13.060350 13, 0x0, sum = 2
3667 23:07:13.063615 14, 0x0, sum = 3
3668 23:07:13.064184 15, 0x0, sum = 4
3669 23:07:13.067038 best_step = 13
3670 23:07:13.067597
3671 23:07:13.067963 ==
3672 23:07:13.070152 Dram Type= 6, Freq= 0, CH_1, rank 1
3673 23:07:13.073786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3674 23:07:13.074353 ==
3675 23:07:13.074718 RX Vref Scan: 0
3676 23:07:13.076893
3677 23:07:13.077349 RX Vref 0 -> 0, step: 1
3678 23:07:13.077714
3679 23:07:13.080394 RX Delay -21 -> 252, step: 4
3680 23:07:13.083715 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3681 23:07:13.090129 iDelay=195, Bit 1, Center 110 (43 ~ 178) 136
3682 23:07:13.093280 iDelay=195, Bit 2, Center 100 (31 ~ 170) 140
3683 23:07:13.096754 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3684 23:07:13.099882 iDelay=195, Bit 4, Center 110 (39 ~ 182) 144
3685 23:07:13.103226 iDelay=195, Bit 5, Center 122 (51 ~ 194) 144
3686 23:07:13.109795 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3687 23:07:13.113386 iDelay=195, Bit 7, Center 110 (43 ~ 178) 136
3688 23:07:13.116566 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3689 23:07:13.119823 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3690 23:07:13.123557 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3691 23:07:13.129654 iDelay=195, Bit 11, Center 102 (35 ~ 170) 136
3692 23:07:13.133258 iDelay=195, Bit 12, Center 118 (55 ~ 182) 128
3693 23:07:13.136568 iDelay=195, Bit 13, Center 116 (51 ~ 182) 132
3694 23:07:13.139549 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3695 23:07:13.146057 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3696 23:07:13.146679 ==
3697 23:07:13.149713 Dram Type= 6, Freq= 0, CH_1, rank 1
3698 23:07:13.153040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3699 23:07:13.153538 ==
3700 23:07:13.153903 DQS Delay:
3701 23:07:13.156404 DQS0 = 0, DQS1 = 0
3702 23:07:13.156906 DQM Delay:
3703 23:07:13.159387 DQM0 = 112, DQM1 = 110
3704 23:07:13.159843 DQ Delay:
3705 23:07:13.163270 DQ0 =114, DQ1 =110, DQ2 =100, DQ3 =108
3706 23:07:13.166611 DQ4 =110, DQ5 =122, DQ6 =122, DQ7 =110
3707 23:07:13.170075 DQ8 =96, DQ9 =100, DQ10 =112, DQ11 =102
3708 23:07:13.173011 DQ12 =118, DQ13 =116, DQ14 =118, DQ15 =118
3709 23:07:13.173471
3710 23:07:13.173831
3711 23:07:13.183222 [DQSOSCAuto] RK1, (LSB)MR18= 0xfc0c, (MSB)MR19= 0x304, tDQSOscB0 = 405 ps tDQSOscB1 = 411 ps
3712 23:07:13.186381 CH1 RK1: MR19=304, MR18=FC0C
3713 23:07:13.190029 CH1_RK1: MR19=0x304, MR18=0xFC0C, DQSOSC=405, MR23=63, INC=39, DEC=26
3714 23:07:13.192941 [RxdqsGatingPostProcess] freq 1200
3715 23:07:13.199202 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3716 23:07:13.203256 best DQS0 dly(2T, 0.5T) = (0, 11)
3717 23:07:13.206391 best DQS1 dly(2T, 0.5T) = (0, 11)
3718 23:07:13.209451 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3719 23:07:13.212813 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3720 23:07:13.216014 best DQS0 dly(2T, 0.5T) = (0, 11)
3721 23:07:13.219209 best DQS1 dly(2T, 0.5T) = (0, 11)
3722 23:07:13.222676 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3723 23:07:13.226006 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3724 23:07:13.229352 Pre-setting of DQS Precalculation
3725 23:07:13.232661 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3726 23:07:13.239043 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3727 23:07:13.245713 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3728 23:07:13.246255
3729 23:07:13.249502
3730 23:07:13.249961 [Calibration Summary] 2400 Mbps
3731 23:07:13.253072 CH 0, Rank 0
3732 23:07:13.253557 SW Impedance : PASS
3733 23:07:13.255866 DUTY Scan : NO K
3734 23:07:13.259247 ZQ Calibration : PASS
3735 23:07:13.259839 Jitter Meter : NO K
3736 23:07:13.262661 CBT Training : PASS
3737 23:07:13.266079 Write leveling : PASS
3738 23:07:13.266632 RX DQS gating : PASS
3739 23:07:13.268817 RX DQ/DQS(RDDQC) : PASS
3740 23:07:13.272610 TX DQ/DQS : PASS
3741 23:07:13.273172 RX DATLAT : PASS
3742 23:07:13.275546 RX DQ/DQS(Engine): PASS
3743 23:07:13.278937 TX OE : NO K
3744 23:07:13.279503 All Pass.
3745 23:07:13.279874
3746 23:07:13.280252 CH 0, Rank 1
3747 23:07:13.282425 SW Impedance : PASS
3748 23:07:13.285758 DUTY Scan : NO K
3749 23:07:13.286316 ZQ Calibration : PASS
3750 23:07:13.289067 Jitter Meter : NO K
3751 23:07:13.292243 CBT Training : PASS
3752 23:07:13.292968 Write leveling : PASS
3753 23:07:13.296194 RX DQS gating : PASS
3754 23:07:13.296804 RX DQ/DQS(RDDQC) : PASS
3755 23:07:13.298548 TX DQ/DQS : PASS
3756 23:07:13.302208 RX DATLAT : PASS
3757 23:07:13.302770 RX DQ/DQS(Engine): PASS
3758 23:07:13.305788 TX OE : NO K
3759 23:07:13.306350 All Pass.
3760 23:07:13.306716
3761 23:07:13.308779 CH 1, Rank 0
3762 23:07:13.309234 SW Impedance : PASS
3763 23:07:13.311927 DUTY Scan : NO K
3764 23:07:13.315923 ZQ Calibration : PASS
3765 23:07:13.316586 Jitter Meter : NO K
3766 23:07:13.319036 CBT Training : PASS
3767 23:07:13.322272 Write leveling : PASS
3768 23:07:13.322835 RX DQS gating : PASS
3769 23:07:13.325431 RX DQ/DQS(RDDQC) : PASS
3770 23:07:13.329044 TX DQ/DQS : PASS
3771 23:07:13.329605 RX DATLAT : PASS
3772 23:07:13.332568 RX DQ/DQS(Engine): PASS
3773 23:07:13.335662 TX OE : NO K
3774 23:07:13.336464 All Pass.
3775 23:07:13.337132
3776 23:07:13.337589 CH 1, Rank 1
3777 23:07:13.338976 SW Impedance : PASS
3778 23:07:13.342098 DUTY Scan : NO K
3779 23:07:13.342659 ZQ Calibration : PASS
3780 23:07:13.345420 Jitter Meter : NO K
3781 23:07:13.345878 CBT Training : PASS
3782 23:07:13.348928 Write leveling : PASS
3783 23:07:13.352288 RX DQS gating : PASS
3784 23:07:13.352750 RX DQ/DQS(RDDQC) : PASS
3785 23:07:13.355525 TX DQ/DQS : PASS
3786 23:07:13.358758 RX DATLAT : PASS
3787 23:07:13.359233 RX DQ/DQS(Engine): PASS
3788 23:07:13.362045 TX OE : NO K
3789 23:07:13.362510 All Pass.
3790 23:07:13.362872
3791 23:07:13.365695 DramC Write-DBI off
3792 23:07:13.368456 PER_BANK_REFRESH: Hybrid Mode
3793 23:07:13.369054 TX_TRACKING: ON
3794 23:07:13.378827 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3795 23:07:13.382278 [FAST_K] Save calibration result to emmc
3796 23:07:13.385625 dramc_set_vcore_voltage set vcore to 650000
3797 23:07:13.389173 Read voltage for 600, 5
3798 23:07:13.389736 Vio18 = 0
3799 23:07:13.390102 Vcore = 650000
3800 23:07:13.392348 Vdram = 0
3801 23:07:13.392991 Vddq = 0
3802 23:07:13.393548 Vmddr = 0
3803 23:07:13.398718 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3804 23:07:13.402394 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3805 23:07:13.405353 MEM_TYPE=3, freq_sel=19
3806 23:07:13.408681 sv_algorithm_assistance_LP4_1600
3807 23:07:13.411904 ============ PULL DRAM RESETB DOWN ============
3808 23:07:13.415049 ========== PULL DRAM RESETB DOWN end =========
3809 23:07:13.421755 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3810 23:07:13.425148 ===================================
3811 23:07:13.429156 LPDDR4 DRAM CONFIGURATION
3812 23:07:13.432143 ===================================
3813 23:07:13.432741 EX_ROW_EN[0] = 0x0
3814 23:07:13.435333 EX_ROW_EN[1] = 0x0
3815 23:07:13.435790 LP4Y_EN = 0x0
3816 23:07:13.438557 WORK_FSP = 0x0
3817 23:07:13.439015 WL = 0x2
3818 23:07:13.442240 RL = 0x2
3819 23:07:13.442799 BL = 0x2
3820 23:07:13.445279 RPST = 0x0
3821 23:07:13.445737 RD_PRE = 0x0
3822 23:07:13.448287 WR_PRE = 0x1
3823 23:07:13.448748 WR_PST = 0x0
3824 23:07:13.451306 DBI_WR = 0x0
3825 23:07:13.451759 DBI_RD = 0x0
3826 23:07:13.454925 OTF = 0x1
3827 23:07:13.458099 ===================================
3828 23:07:13.461364 ===================================
3829 23:07:13.461823 ANA top config
3830 23:07:13.465184 ===================================
3831 23:07:13.468360 DLL_ASYNC_EN = 0
3832 23:07:13.471493 ALL_SLAVE_EN = 1
3833 23:07:13.474918 NEW_RANK_MODE = 1
3834 23:07:13.475488 DLL_IDLE_MODE = 1
3835 23:07:13.477971 LP45_APHY_COMB_EN = 1
3836 23:07:13.481716 TX_ODT_DIS = 1
3837 23:07:13.485256 NEW_8X_MODE = 1
3838 23:07:13.488328 ===================================
3839 23:07:13.491150 ===================================
3840 23:07:13.494422 data_rate = 1200
3841 23:07:13.498281 CKR = 1
3842 23:07:13.498856 DQ_P2S_RATIO = 8
3843 23:07:13.501155 ===================================
3844 23:07:13.504564 CA_P2S_RATIO = 8
3845 23:07:13.508060 DQ_CA_OPEN = 0
3846 23:07:13.511198 DQ_SEMI_OPEN = 0
3847 23:07:13.514397 CA_SEMI_OPEN = 0
3848 23:07:13.518195 CA_FULL_RATE = 0
3849 23:07:13.518755 DQ_CKDIV4_EN = 1
3850 23:07:13.520817 CA_CKDIV4_EN = 1
3851 23:07:13.524367 CA_PREDIV_EN = 0
3852 23:07:13.527599 PH8_DLY = 0
3853 23:07:13.531075 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3854 23:07:13.534647 DQ_AAMCK_DIV = 4
3855 23:07:13.535226 CA_AAMCK_DIV = 4
3856 23:07:13.537811 CA_ADMCK_DIV = 4
3857 23:07:13.540823 DQ_TRACK_CA_EN = 0
3858 23:07:13.544235 CA_PICK = 600
3859 23:07:13.547461 CA_MCKIO = 600
3860 23:07:13.550620 MCKIO_SEMI = 0
3861 23:07:13.553838 PLL_FREQ = 2288
3862 23:07:13.554336 DQ_UI_PI_RATIO = 32
3863 23:07:13.557040 CA_UI_PI_RATIO = 0
3864 23:07:13.560322 ===================================
3865 23:07:13.563999 ===================================
3866 23:07:13.566921 memory_type:LPDDR4
3867 23:07:13.570657 GP_NUM : 10
3868 23:07:13.571128 SRAM_EN : 1
3869 23:07:13.573990 MD32_EN : 0
3870 23:07:13.576951 ===================================
3871 23:07:13.580222 [ANA_INIT] >>>>>>>>>>>>>>
3872 23:07:13.580686 <<<<<< [CONFIGURE PHASE]: ANA_TX
3873 23:07:13.583747 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3874 23:07:13.586938 ===================================
3875 23:07:13.590670 data_rate = 1200,PCW = 0X5800
3876 23:07:13.593779 ===================================
3877 23:07:13.596977 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3878 23:07:13.603725 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3879 23:07:13.610163 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3880 23:07:13.613955 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3881 23:07:13.617230 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3882 23:07:13.620163 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3883 23:07:13.623837 [ANA_INIT] flow start
3884 23:07:13.624338 [ANA_INIT] PLL >>>>>>>>
3885 23:07:13.626628 [ANA_INIT] PLL <<<<<<<<
3886 23:07:13.630163 [ANA_INIT] MIDPI >>>>>>>>
3887 23:07:13.633586 [ANA_INIT] MIDPI <<<<<<<<
3888 23:07:13.634145 [ANA_INIT] DLL >>>>>>>>
3889 23:07:13.636988 [ANA_INIT] flow end
3890 23:07:13.640252 ============ LP4 DIFF to SE enter ============
3891 23:07:13.643214 ============ LP4 DIFF to SE exit ============
3892 23:07:13.646875 [ANA_INIT] <<<<<<<<<<<<<
3893 23:07:13.649959 [Flow] Enable top DCM control >>>>>
3894 23:07:13.653384 [Flow] Enable top DCM control <<<<<
3895 23:07:13.656871 Enable DLL master slave shuffle
3896 23:07:13.663328 ==============================================================
3897 23:07:13.663911 Gating Mode config
3898 23:07:13.670323 ==============================================================
3899 23:07:13.670881 Config description:
3900 23:07:13.680489 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3901 23:07:13.686484 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3902 23:07:13.693130 SELPH_MODE 0: By rank 1: By Phase
3903 23:07:13.696827 ==============================================================
3904 23:07:13.699881 GAT_TRACK_EN = 1
3905 23:07:13.703137 RX_GATING_MODE = 2
3906 23:07:13.706653 RX_GATING_TRACK_MODE = 2
3907 23:07:13.709874 SELPH_MODE = 1
3908 23:07:13.713299 PICG_EARLY_EN = 1
3909 23:07:13.716620 VALID_LAT_VALUE = 1
3910 23:07:13.720006 ==============================================================
3911 23:07:13.722917 Enter into Gating configuration >>>>
3912 23:07:13.727037 Exit from Gating configuration <<<<
3913 23:07:13.729815 Enter into DVFS_PRE_config >>>>>
3914 23:07:13.743578 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3915 23:07:13.746780 Exit from DVFS_PRE_config <<<<<
3916 23:07:13.749927 Enter into PICG configuration >>>>
3917 23:07:13.750392 Exit from PICG configuration <<<<
3918 23:07:13.753015 [RX_INPUT] configuration >>>>>
3919 23:07:13.756541 [RX_INPUT] configuration <<<<<
3920 23:07:13.763538 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3921 23:07:13.766578 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3922 23:07:13.772848 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3923 23:07:13.779344 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3924 23:07:13.786528 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3925 23:07:13.792497 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3926 23:07:13.795749 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3927 23:07:13.802699 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3928 23:07:13.806057 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3929 23:07:13.809524 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3930 23:07:13.812413 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3931 23:07:13.815882 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3932 23:07:13.818937 ===================================
3933 23:07:13.822228 LPDDR4 DRAM CONFIGURATION
3934 23:07:13.825931 ===================================
3935 23:07:13.828922 EX_ROW_EN[0] = 0x0
3936 23:07:13.829583 EX_ROW_EN[1] = 0x0
3937 23:07:13.832479 LP4Y_EN = 0x0
3938 23:07:13.833088 WORK_FSP = 0x0
3939 23:07:13.835798 WL = 0x2
3940 23:07:13.836435 RL = 0x2
3941 23:07:13.839046 BL = 0x2
3942 23:07:13.839649 RPST = 0x0
3943 23:07:13.842316 RD_PRE = 0x0
3944 23:07:13.842937 WR_PRE = 0x1
3945 23:07:13.845589 WR_PST = 0x0
3946 23:07:13.846057 DBI_WR = 0x0
3947 23:07:13.848662 DBI_RD = 0x0
3948 23:07:13.852593 OTF = 0x1
3949 23:07:13.853049 ===================================
3950 23:07:13.858953 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3951 23:07:13.862386 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3952 23:07:13.865608 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3953 23:07:13.868869 ===================================
3954 23:07:13.872115 LPDDR4 DRAM CONFIGURATION
3955 23:07:13.875688 ===================================
3956 23:07:13.878697 EX_ROW_EN[0] = 0x10
3957 23:07:13.879157 EX_ROW_EN[1] = 0x0
3958 23:07:13.882079 LP4Y_EN = 0x0
3959 23:07:13.882539 WORK_FSP = 0x0
3960 23:07:13.885094 WL = 0x2
3961 23:07:13.885555 RL = 0x2
3962 23:07:13.888768 BL = 0x2
3963 23:07:13.889230 RPST = 0x0
3964 23:07:13.892084 RD_PRE = 0x0
3965 23:07:13.892585 WR_PRE = 0x1
3966 23:07:13.895417 WR_PST = 0x0
3967 23:07:13.895879 DBI_WR = 0x0
3968 23:07:13.898782 DBI_RD = 0x0
3969 23:07:13.899342 OTF = 0x1
3970 23:07:13.901831 ===================================
3971 23:07:13.908710 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3972 23:07:13.913403 nWR fixed to 30
3973 23:07:13.916787 [ModeRegInit_LP4] CH0 RK0
3974 23:07:13.917409 [ModeRegInit_LP4] CH0 RK1
3975 23:07:13.920310 [ModeRegInit_LP4] CH1 RK0
3976 23:07:13.923352 [ModeRegInit_LP4] CH1 RK1
3977 23:07:13.923815 match AC timing 17
3978 23:07:13.930286 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3979 23:07:13.933406 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3980 23:07:13.936677 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3981 23:07:13.943271 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3982 23:07:13.946593 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3983 23:07:13.947149 ==
3984 23:07:13.949947 Dram Type= 6, Freq= 0, CH_0, rank 0
3985 23:07:13.953497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3986 23:07:13.953957 ==
3987 23:07:13.959842 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3988 23:07:13.966448 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3989 23:07:13.969797 [CA 0] Center 37 (7~67) winsize 61
3990 23:07:13.973073 [CA 1] Center 37 (7~67) winsize 61
3991 23:07:13.976591 [CA 2] Center 35 (5~65) winsize 61
3992 23:07:13.979861 [CA 3] Center 34 (4~65) winsize 62
3993 23:07:13.982988 [CA 4] Center 34 (4~65) winsize 62
3994 23:07:13.986327 [CA 5] Center 34 (4~64) winsize 61
3995 23:07:13.986735
3996 23:07:13.989638 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3997 23:07:13.990050
3998 23:07:13.992886 [CATrainingPosCal] consider 1 rank data
3999 23:07:13.995913 u2DelayCellTimex100 = 270/100 ps
4000 23:07:13.999506 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
4001 23:07:14.002815 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
4002 23:07:14.005980 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4003 23:07:14.009690 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4004 23:07:14.016298 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4005 23:07:14.019416 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4006 23:07:14.019827
4007 23:07:14.022427 CA PerBit enable=1, Macro0, CA PI delay=34
4008 23:07:14.022892
4009 23:07:14.026263 [CBTSetCACLKResult] CA Dly = 34
4010 23:07:14.026710 CS Dly: 4 (0~35)
4011 23:07:14.027065 ==
4012 23:07:14.029162 Dram Type= 6, Freq= 0, CH_0, rank 1
4013 23:07:14.035824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4014 23:07:14.036267 ==
4015 23:07:14.038993 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4016 23:07:14.045576 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4017 23:07:14.049175 [CA 0] Center 37 (7~67) winsize 61
4018 23:07:14.052781 [CA 1] Center 37 (7~67) winsize 61
4019 23:07:14.055617 [CA 2] Center 35 (5~65) winsize 61
4020 23:07:14.058937 [CA 3] Center 35 (5~65) winsize 61
4021 23:07:14.062115 [CA 4] Center 34 (4~64) winsize 61
4022 23:07:14.065580 [CA 5] Center 34 (4~64) winsize 61
4023 23:07:14.066000
4024 23:07:14.068704 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4025 23:07:14.069235
4026 23:07:14.072103 [CATrainingPosCal] consider 2 rank data
4027 23:07:14.075340 u2DelayCellTimex100 = 270/100 ps
4028 23:07:14.078774 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
4029 23:07:14.081759 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
4030 23:07:14.088513 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4031 23:07:14.092094 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
4032 23:07:14.095335 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
4033 23:07:14.098720 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4034 23:07:14.099139
4035 23:07:14.102274 CA PerBit enable=1, Macro0, CA PI delay=34
4036 23:07:14.102694
4037 23:07:14.105385 [CBTSetCACLKResult] CA Dly = 34
4038 23:07:14.105803 CS Dly: 4 (0~36)
4039 23:07:14.106136
4040 23:07:14.111598 ----->DramcWriteLeveling(PI) begin...
4041 23:07:14.112022 ==
4042 23:07:14.115292 Dram Type= 6, Freq= 0, CH_0, rank 0
4043 23:07:14.118763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4044 23:07:14.119187 ==
4045 23:07:14.121875 Write leveling (Byte 0): 33 => 33
4046 23:07:14.125187 Write leveling (Byte 1): 32 => 32
4047 23:07:14.128785 DramcWriteLeveling(PI) end<-----
4048 23:07:14.129202
4049 23:07:14.129570 ==
4050 23:07:14.131562 Dram Type= 6, Freq= 0, CH_0, rank 0
4051 23:07:14.135075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4052 23:07:14.135499 ==
4053 23:07:14.138103 [Gating] SW mode calibration
4054 23:07:14.145184 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4055 23:07:14.151287 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4056 23:07:14.154839 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4057 23:07:14.158074 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4058 23:07:14.164713 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4059 23:07:14.167833 0 9 12 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
4060 23:07:14.171241 0 9 16 | B1->B0 | 3030 2d2d | 0 0 | (0 1) (0 0)
4061 23:07:14.177688 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4062 23:07:14.180930 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4063 23:07:14.184142 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4064 23:07:14.191196 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4065 23:07:14.194398 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4066 23:07:14.197498 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4067 23:07:14.204534 0 10 12 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
4068 23:07:14.207368 0 10 16 | B1->B0 | 3434 3a3a | 0 0 | (0 0) (0 0)
4069 23:07:14.211033 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4070 23:07:14.217537 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4071 23:07:14.221003 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4072 23:07:14.224013 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4073 23:07:14.230828 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4074 23:07:14.233963 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4075 23:07:14.237701 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4076 23:07:14.244297 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4077 23:07:14.247444 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4078 23:07:14.250693 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4079 23:07:14.254511 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4080 23:07:14.260533 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4081 23:07:14.263923 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4082 23:07:14.267608 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4083 23:07:14.273890 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4084 23:07:14.277381 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4085 23:07:14.280444 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4086 23:07:14.287060 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4087 23:07:14.291000 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4088 23:07:14.293614 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4089 23:07:14.300191 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4090 23:07:14.304186 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4091 23:07:14.307185 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4092 23:07:14.314104 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4093 23:07:14.316955 Total UI for P1: 0, mck2ui 16
4094 23:07:14.320513 best dqsien dly found for B0: ( 0, 13, 12)
4095 23:07:14.324066 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4096 23:07:14.327036 Total UI for P1: 0, mck2ui 16
4097 23:07:14.329907 best dqsien dly found for B1: ( 0, 13, 18)
4098 23:07:14.333499 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4099 23:07:14.337137 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4100 23:07:14.337667
4101 23:07:14.340164 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4102 23:07:14.343546 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4103 23:07:14.346798 [Gating] SW calibration Done
4104 23:07:14.347241 ==
4105 23:07:14.349797 Dram Type= 6, Freq= 0, CH_0, rank 0
4106 23:07:14.356622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4107 23:07:14.357151 ==
4108 23:07:14.357598 RX Vref Scan: 0
4109 23:07:14.358015
4110 23:07:14.360055 RX Vref 0 -> 0, step: 1
4111 23:07:14.360596
4112 23:07:14.363347 RX Delay -230 -> 252, step: 16
4113 23:07:14.366775 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4114 23:07:14.370346 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4115 23:07:14.373178 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4116 23:07:14.380030 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4117 23:07:14.383375 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4118 23:07:14.386351 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4119 23:07:14.389744 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4120 23:07:14.396450 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4121 23:07:14.400021 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4122 23:07:14.403120 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4123 23:07:14.406286 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4124 23:07:14.412912 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4125 23:07:14.416563 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4126 23:07:14.419665 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4127 23:07:14.422773 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4128 23:07:14.429496 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4129 23:07:14.429934 ==
4130 23:07:14.432592 Dram Type= 6, Freq= 0, CH_0, rank 0
4131 23:07:14.436060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4132 23:07:14.436577 ==
4133 23:07:14.436947 DQS Delay:
4134 23:07:14.439197 DQS0 = 0, DQS1 = 0
4135 23:07:14.439637 DQM Delay:
4136 23:07:14.442663 DQM0 = 38, DQM1 = 31
4137 23:07:14.443177 DQ Delay:
4138 23:07:14.446257 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4139 23:07:14.449102 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4140 23:07:14.452376 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4141 23:07:14.456026 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4142 23:07:14.456493
4143 23:07:14.456901
4144 23:07:14.457219 ==
4145 23:07:14.459094 Dram Type= 6, Freq= 0, CH_0, rank 0
4146 23:07:14.462422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4147 23:07:14.462862 ==
4148 23:07:14.463223
4149 23:07:14.463559
4150 23:07:14.466217 TX Vref Scan disable
4151 23:07:14.469255 == TX Byte 0 ==
4152 23:07:14.472423 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4153 23:07:14.475759 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4154 23:07:14.479360 == TX Byte 1 ==
4155 23:07:14.482719 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4156 23:07:14.485806 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4157 23:07:14.486387 ==
4158 23:07:14.489304 Dram Type= 6, Freq= 0, CH_0, rank 0
4159 23:07:14.495774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4160 23:07:14.496453 ==
4161 23:07:14.496825
4162 23:07:14.497166
4163 23:07:14.497474 TX Vref Scan disable
4164 23:07:14.500143 == TX Byte 0 ==
4165 23:07:14.503356 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4166 23:07:14.507151 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4167 23:07:14.510381 == TX Byte 1 ==
4168 23:07:14.513261 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4169 23:07:14.519942 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4170 23:07:14.520524
4171 23:07:14.521087 [DATLAT]
4172 23:07:14.521620 Freq=600, CH0 RK0
4173 23:07:14.522137
4174 23:07:14.523759 DATLAT Default: 0x9
4175 23:07:14.524334 0, 0xFFFF, sum = 0
4176 23:07:14.526620 1, 0xFFFF, sum = 0
4177 23:07:14.527203 2, 0xFFFF, sum = 0
4178 23:07:14.529868 3, 0xFFFF, sum = 0
4179 23:07:14.533857 4, 0xFFFF, sum = 0
4180 23:07:14.534377 5, 0xFFFF, sum = 0
4181 23:07:14.536699 6, 0xFFFF, sum = 0
4182 23:07:14.537152 7, 0xFFFF, sum = 0
4183 23:07:14.540165 8, 0x0, sum = 1
4184 23:07:14.540662 9, 0x0, sum = 2
4185 23:07:14.541123 10, 0x0, sum = 3
4186 23:07:14.543439 11, 0x0, sum = 4
4187 23:07:14.543974 best_step = 9
4188 23:07:14.544536
4189 23:07:14.544952 ==
4190 23:07:14.546479 Dram Type= 6, Freq= 0, CH_0, rank 0
4191 23:07:14.553121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4192 23:07:14.553642 ==
4193 23:07:14.554213 RX Vref Scan: 1
4194 23:07:14.554695
4195 23:07:14.556550 RX Vref 0 -> 0, step: 1
4196 23:07:14.557047
4197 23:07:14.560336 RX Delay -195 -> 252, step: 8
4198 23:07:14.560826
4199 23:07:14.563323 Set Vref, RX VrefLevel [Byte0]: 61
4200 23:07:14.566855 [Byte1]: 47
4201 23:07:14.567419
4202 23:07:14.570147 Final RX Vref Byte 0 = 61 to rank0
4203 23:07:14.573417 Final RX Vref Byte 1 = 47 to rank0
4204 23:07:14.576354 Final RX Vref Byte 0 = 61 to rank1
4205 23:07:14.580196 Final RX Vref Byte 1 = 47 to rank1==
4206 23:07:14.582852 Dram Type= 6, Freq= 0, CH_0, rank 0
4207 23:07:14.586662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4208 23:07:14.587178 ==
4209 23:07:14.589879 DQS Delay:
4210 23:07:14.590376 DQS0 = 0, DQS1 = 0
4211 23:07:14.592944 DQM Delay:
4212 23:07:14.593456 DQM0 = 34, DQM1 = 28
4213 23:07:14.593903 DQ Delay:
4214 23:07:14.596790 DQ0 =32, DQ1 =36, DQ2 =36, DQ3 =28
4215 23:07:14.599923 DQ4 =36, DQ5 =20, DQ6 =40, DQ7 =44
4216 23:07:14.602984 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =24
4217 23:07:14.606495 DQ12 =32, DQ13 =32, DQ14 =40, DQ15 =36
4218 23:07:14.607000
4219 23:07:14.607405
4220 23:07:14.616266 [DQSOSCAuto] RK0, (LSB)MR18= 0x4443, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 396 ps
4221 23:07:14.619862 CH0 RK0: MR19=808, MR18=4443
4222 23:07:14.626084 CH0_RK0: MR19=0x808, MR18=0x4443, DQSOSC=396, MR23=63, INC=167, DEC=111
4223 23:07:14.626581
4224 23:07:14.629509 ----->DramcWriteLeveling(PI) begin...
4225 23:07:14.630010 ==
4226 23:07:14.632515 Dram Type= 6, Freq= 0, CH_0, rank 1
4227 23:07:14.636024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4228 23:07:14.636629 ==
4229 23:07:14.639357 Write leveling (Byte 0): 31 => 31
4230 23:07:14.642464 Write leveling (Byte 1): 32 => 32
4231 23:07:14.645961 DramcWriteLeveling(PI) end<-----
4232 23:07:14.646380
4233 23:07:14.646710 ==
4234 23:07:14.649256 Dram Type= 6, Freq= 0, CH_0, rank 1
4235 23:07:14.652618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4236 23:07:14.653267 ==
4237 23:07:14.655819 [Gating] SW mode calibration
4238 23:07:14.662747 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4239 23:07:14.669015 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4240 23:07:14.672388 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4241 23:07:14.675580 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4242 23:07:14.682329 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4243 23:07:14.685488 0 9 12 | B1->B0 | 3333 2f2f | 1 1 | (1 1) (1 0)
4244 23:07:14.689117 0 9 16 | B1->B0 | 2f2f 2424 | 0 0 | (0 1) (0 0)
4245 23:07:14.695938 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4246 23:07:14.698900 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4247 23:07:14.702330 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4248 23:07:14.708808 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4249 23:07:14.711935 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4250 23:07:14.715593 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4251 23:07:14.722167 0 10 12 | B1->B0 | 2525 3333 | 1 0 | (0 0) (0 0)
4252 23:07:14.725430 0 10 16 | B1->B0 | 3838 4444 | 0 0 | (0 0) (0 0)
4253 23:07:14.728579 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4254 23:07:14.735507 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4255 23:07:14.738904 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4256 23:07:14.742339 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4257 23:07:14.748504 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4258 23:07:14.751833 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4259 23:07:14.755471 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4260 23:07:14.761791 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4261 23:07:14.764995 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4262 23:07:14.768077 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 23:07:14.775098 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 23:07:14.778616 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4265 23:07:14.781755 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4266 23:07:14.787995 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4267 23:07:14.791271 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4268 23:07:14.794949 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4269 23:07:14.800979 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4270 23:07:14.804494 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4271 23:07:14.807903 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4272 23:07:14.814626 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4273 23:07:14.817481 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4274 23:07:14.821197 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4275 23:07:14.827551 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4276 23:07:14.828166 Total UI for P1: 0, mck2ui 16
4277 23:07:14.834613 best dqsien dly found for B0: ( 0, 13, 10)
4278 23:07:14.837401 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4279 23:07:14.840966 Total UI for P1: 0, mck2ui 16
4280 23:07:14.844363 best dqsien dly found for B1: ( 0, 13, 12)
4281 23:07:14.847765 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4282 23:07:14.850868 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4283 23:07:14.851443
4284 23:07:14.854542 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4285 23:07:14.857445 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4286 23:07:14.861336 [Gating] SW calibration Done
4287 23:07:14.861894 ==
4288 23:07:14.863806 Dram Type= 6, Freq= 0, CH_0, rank 1
4289 23:07:14.867366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4290 23:07:14.870020 ==
4291 23:07:14.870101 RX Vref Scan: 0
4292 23:07:14.870166
4293 23:07:14.873692 RX Vref 0 -> 0, step: 1
4294 23:07:14.873774
4295 23:07:14.876829 RX Delay -230 -> 252, step: 16
4296 23:07:14.880040 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4297 23:07:14.883287 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4298 23:07:14.886603 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4299 23:07:14.893358 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4300 23:07:14.896681 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4301 23:07:14.900072 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4302 23:07:14.903070 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4303 23:07:14.906552 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4304 23:07:14.913241 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4305 23:07:14.916130 iDelay=218, Bit 9, Center 9 (-150 ~ 169) 320
4306 23:07:14.920181 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4307 23:07:14.923209 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4308 23:07:14.929956 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4309 23:07:14.933224 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4310 23:07:14.936609 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4311 23:07:14.939672 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4312 23:07:14.943031 ==
4313 23:07:14.943109 Dram Type= 6, Freq= 0, CH_0, rank 1
4314 23:07:14.949059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4315 23:07:14.949165 ==
4316 23:07:14.949256 DQS Delay:
4317 23:07:14.952932 DQS0 = 0, DQS1 = 0
4318 23:07:14.953006 DQM Delay:
4319 23:07:14.955872 DQM0 = 36, DQM1 = 30
4320 23:07:14.955947 DQ Delay:
4321 23:07:14.959193 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4322 23:07:14.962401 DQ4 =33, DQ5 =25, DQ6 =49, DQ7 =49
4323 23:07:14.965991 DQ8 =25, DQ9 =9, DQ10 =33, DQ11 =25
4324 23:07:14.969243 DQ12 =33, DQ13 =41, DQ14 =41, DQ15 =33
4325 23:07:14.969316
4326 23:07:14.969383
4327 23:07:14.969443 ==
4328 23:07:14.972634 Dram Type= 6, Freq= 0, CH_0, rank 1
4329 23:07:14.975867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4330 23:07:14.975965 ==
4331 23:07:14.976053
4332 23:07:14.976141
4333 23:07:14.979022 TX Vref Scan disable
4334 23:07:14.982372 == TX Byte 0 ==
4335 23:07:14.985820 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4336 23:07:14.989114 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4337 23:07:14.992395 == TX Byte 1 ==
4338 23:07:14.995575 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4339 23:07:14.998904 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4340 23:07:14.998976 ==
4341 23:07:15.001873 Dram Type= 6, Freq= 0, CH_0, rank 1
4342 23:07:15.008834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4343 23:07:15.008913 ==
4344 23:07:15.008977
4345 23:07:15.009050
4346 23:07:15.009113 TX Vref Scan disable
4347 23:07:15.012861 == TX Byte 0 ==
4348 23:07:15.016510 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4349 23:07:15.022894 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4350 23:07:15.022971 == TX Byte 1 ==
4351 23:07:15.026359 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4352 23:07:15.033098 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4353 23:07:15.033173
4354 23:07:15.033244 [DATLAT]
4355 23:07:15.033314 Freq=600, CH0 RK1
4356 23:07:15.033373
4357 23:07:15.036469 DATLAT Default: 0x9
4358 23:07:15.036542 0, 0xFFFF, sum = 0
4359 23:07:15.039464 1, 0xFFFF, sum = 0
4360 23:07:15.039535 2, 0xFFFF, sum = 0
4361 23:07:15.042960 3, 0xFFFF, sum = 0
4362 23:07:15.046359 4, 0xFFFF, sum = 0
4363 23:07:15.046433 5, 0xFFFF, sum = 0
4364 23:07:15.049676 6, 0xFFFF, sum = 0
4365 23:07:15.049749 7, 0xFFFF, sum = 0
4366 23:07:15.052858 8, 0x0, sum = 1
4367 23:07:15.052959 9, 0x0, sum = 2
4368 23:07:15.053050 10, 0x0, sum = 3
4369 23:07:15.055973 11, 0x0, sum = 4
4370 23:07:15.056045 best_step = 9
4371 23:07:15.056110
4372 23:07:15.056168 ==
4373 23:07:15.059119 Dram Type= 6, Freq= 0, CH_0, rank 1
4374 23:07:15.065832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4375 23:07:15.065910 ==
4376 23:07:15.065978 RX Vref Scan: 0
4377 23:07:15.066040
4378 23:07:15.069462 RX Vref 0 -> 0, step: 1
4379 23:07:15.069533
4380 23:07:15.072534 RX Delay -195 -> 252, step: 8
4381 23:07:15.075642 iDelay=205, Bit 0, Center 32 (-123 ~ 188) 312
4382 23:07:15.082426 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4383 23:07:15.085904 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4384 23:07:15.088935 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4385 23:07:15.092922 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4386 23:07:15.098907 iDelay=205, Bit 5, Center 20 (-139 ~ 180) 320
4387 23:07:15.102089 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4388 23:07:15.105379 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4389 23:07:15.108656 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4390 23:07:15.115849 iDelay=205, Bit 9, Center 12 (-139 ~ 164) 304
4391 23:07:15.118712 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4392 23:07:15.122189 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4393 23:07:15.125467 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4394 23:07:15.128616 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4395 23:07:15.135297 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4396 23:07:15.138610 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4397 23:07:15.138708 ==
4398 23:07:15.142493 Dram Type= 6, Freq= 0, CH_0, rank 1
4399 23:07:15.145791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4400 23:07:15.145865 ==
4401 23:07:15.148557 DQS Delay:
4402 23:07:15.148653 DQS0 = 0, DQS1 = 0
4403 23:07:15.152215 DQM Delay:
4404 23:07:15.152315 DQM0 = 33, DQM1 = 28
4405 23:07:15.152396 DQ Delay:
4406 23:07:15.155615 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =28
4407 23:07:15.158885 DQ4 =32, DQ5 =20, DQ6 =44, DQ7 =44
4408 23:07:15.162214 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4409 23:07:15.165237 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4410 23:07:15.165309
4411 23:07:15.165388
4412 23:07:15.175523 [DQSOSCAuto] RK1, (LSB)MR18= 0x6836, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 390 ps
4413 23:07:15.178314 CH0 RK1: MR19=808, MR18=6836
4414 23:07:15.185111 CH0_RK1: MR19=0x808, MR18=0x6836, DQSOSC=390, MR23=63, INC=172, DEC=114
4415 23:07:15.188281 [RxdqsGatingPostProcess] freq 600
4416 23:07:15.191787 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4417 23:07:15.194883 Pre-setting of DQS Precalculation
4418 23:07:15.198250 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4419 23:07:15.201566 ==
4420 23:07:15.204746 Dram Type= 6, Freq= 0, CH_1, rank 0
4421 23:07:15.207958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4422 23:07:15.208035 ==
4423 23:07:15.211801 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4424 23:07:15.217760 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4425 23:07:15.221867 [CA 0] Center 36 (6~66) winsize 61
4426 23:07:15.225370 [CA 1] Center 36 (6~66) winsize 61
4427 23:07:15.228934 [CA 2] Center 34 (4~65) winsize 62
4428 23:07:15.232125 [CA 3] Center 34 (4~65) winsize 62
4429 23:07:15.235259 [CA 4] Center 34 (4~65) winsize 62
4430 23:07:15.238832 [CA 5] Center 33 (3~64) winsize 62
4431 23:07:15.238911
4432 23:07:15.242129 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4433 23:07:15.242205
4434 23:07:15.245216 [CATrainingPosCal] consider 1 rank data
4435 23:07:15.248395 u2DelayCellTimex100 = 270/100 ps
4436 23:07:15.252182 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4437 23:07:15.255310 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4438 23:07:15.261754 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4439 23:07:15.265157 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4440 23:07:15.268405 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4441 23:07:15.272116 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4442 23:07:15.272240
4443 23:07:15.275125 CA PerBit enable=1, Macro0, CA PI delay=33
4444 23:07:15.275198
4445 23:07:15.278697 [CBTSetCACLKResult] CA Dly = 33
4446 23:07:15.278773 CS Dly: 4 (0~35)
4447 23:07:15.281748 ==
4448 23:07:15.284949 Dram Type= 6, Freq= 0, CH_1, rank 1
4449 23:07:15.288486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4450 23:07:15.288560 ==
4451 23:07:15.291618 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4452 23:07:15.298539 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4453 23:07:15.302266 [CA 0] Center 36 (6~66) winsize 61
4454 23:07:15.305700 [CA 1] Center 36 (6~67) winsize 62
4455 23:07:15.308935 [CA 2] Center 34 (4~65) winsize 62
4456 23:07:15.312137 [CA 3] Center 34 (3~65) winsize 63
4457 23:07:15.315478 [CA 4] Center 34 (4~65) winsize 62
4458 23:07:15.318484 [CA 5] Center 33 (3~64) winsize 62
4459 23:07:15.318558
4460 23:07:15.321713 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4461 23:07:15.321786
4462 23:07:15.325141 [CATrainingPosCal] consider 2 rank data
4463 23:07:15.328378 u2DelayCellTimex100 = 270/100 ps
4464 23:07:15.332040 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4465 23:07:15.338396 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4466 23:07:15.341953 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4467 23:07:15.345230 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4468 23:07:15.348140 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4469 23:07:15.351776 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4470 23:07:15.351863
4471 23:07:15.355211 CA PerBit enable=1, Macro0, CA PI delay=33
4472 23:07:15.355292
4473 23:07:15.358305 [CBTSetCACLKResult] CA Dly = 33
4474 23:07:15.361415 CS Dly: 4 (0~36)
4475 23:07:15.361496
4476 23:07:15.364739 ----->DramcWriteLeveling(PI) begin...
4477 23:07:15.364823 ==
4478 23:07:15.368354 Dram Type= 6, Freq= 0, CH_1, rank 0
4479 23:07:15.371484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4480 23:07:15.371570 ==
4481 23:07:15.374626 Write leveling (Byte 0): 29 => 29
4482 23:07:15.377981 Write leveling (Byte 1): 29 => 29
4483 23:07:15.381498 DramcWriteLeveling(PI) end<-----
4484 23:07:15.381571
4485 23:07:15.381632 ==
4486 23:07:15.385055 Dram Type= 6, Freq= 0, CH_1, rank 0
4487 23:07:15.388130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4488 23:07:15.388237 ==
4489 23:07:15.391785 [Gating] SW mode calibration
4490 23:07:15.398280 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4491 23:07:15.404800 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4492 23:07:15.407933 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4493 23:07:15.411470 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4494 23:07:15.417839 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4495 23:07:15.421257 0 9 12 | B1->B0 | 3333 3131 | 0 1 | (0 1) (1 0)
4496 23:07:15.424510 0 9 16 | B1->B0 | 2525 2424 | 0 0 | (0 0) (1 0)
4497 23:07:15.431074 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4498 23:07:15.434840 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4499 23:07:15.437965 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4500 23:07:15.444380 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4501 23:07:15.447619 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4502 23:07:15.450958 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4503 23:07:15.457722 0 10 12 | B1->B0 | 3131 3333 | 1 0 | (0 0) (0 0)
4504 23:07:15.460777 0 10 16 | B1->B0 | 4444 4545 | 0 0 | (0 0) (1 1)
4505 23:07:15.464305 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4506 23:07:15.470817 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4507 23:07:15.474245 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4508 23:07:15.477372 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4509 23:07:15.483903 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4510 23:07:15.487496 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4511 23:07:15.490546 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4512 23:07:15.497091 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4513 23:07:15.500595 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4514 23:07:15.504404 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4515 23:07:15.510399 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4516 23:07:15.514174 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4517 23:07:15.517235 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4518 23:07:15.523891 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4519 23:07:15.527032 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4520 23:07:15.530297 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4521 23:07:15.536806 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4522 23:07:15.540777 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4523 23:07:15.543527 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4524 23:07:15.547260 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4525 23:07:15.553301 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4526 23:07:15.556589 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4527 23:07:15.563362 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4528 23:07:15.566577 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4529 23:07:15.570132 Total UI for P1: 0, mck2ui 16
4530 23:07:15.573602 best dqsien dly found for B0: ( 0, 13, 14)
4531 23:07:15.576769 Total UI for P1: 0, mck2ui 16
4532 23:07:15.580066 best dqsien dly found for B1: ( 0, 13, 12)
4533 23:07:15.583408 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4534 23:07:15.586800 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4535 23:07:15.586883
4536 23:07:15.590307 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4537 23:07:15.593156 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4538 23:07:15.596670 [Gating] SW calibration Done
4539 23:07:15.596745 ==
4540 23:07:15.599839 Dram Type= 6, Freq= 0, CH_1, rank 0
4541 23:07:15.603192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4542 23:07:15.603264 ==
4543 23:07:15.606523 RX Vref Scan: 0
4544 23:07:15.606624
4545 23:07:15.609528 RX Vref 0 -> 0, step: 1
4546 23:07:15.609600
4547 23:07:15.609661 RX Delay -230 -> 252, step: 16
4548 23:07:15.616515 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4549 23:07:15.620047 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4550 23:07:15.623350 iDelay=218, Bit 2, Center 25 (-150 ~ 201) 352
4551 23:07:15.626500 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4552 23:07:15.632905 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4553 23:07:15.636401 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4554 23:07:15.639520 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4555 23:07:15.642786 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4556 23:07:15.649295 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4557 23:07:15.652598 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4558 23:07:15.655836 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4559 23:07:15.659122 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4560 23:07:15.665947 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4561 23:07:15.669196 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4562 23:07:15.672546 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4563 23:07:15.675919 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4564 23:07:15.676001 ==
4565 23:07:15.679379 Dram Type= 6, Freq= 0, CH_1, rank 0
4566 23:07:15.685939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4567 23:07:15.686021 ==
4568 23:07:15.686085 DQS Delay:
4569 23:07:15.688847 DQS0 = 0, DQS1 = 0
4570 23:07:15.688929 DQM Delay:
4571 23:07:15.688993 DQM0 = 39, DQM1 = 29
4572 23:07:15.692245 DQ Delay:
4573 23:07:15.695545 DQ0 =49, DQ1 =33, DQ2 =25, DQ3 =33
4574 23:07:15.698741 DQ4 =33, DQ5 =49, DQ6 =57, DQ7 =33
4575 23:07:15.702235 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4576 23:07:15.705877 DQ12 =33, DQ13 =41, DQ14 =33, DQ15 =33
4577 23:07:15.705959
4578 23:07:15.706023
4579 23:07:15.706082 ==
4580 23:07:15.709687 Dram Type= 6, Freq= 0, CH_1, rank 0
4581 23:07:15.712173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4582 23:07:15.712296 ==
4583 23:07:15.712361
4584 23:07:15.712420
4585 23:07:15.715558 TX Vref Scan disable
4586 23:07:15.718479 == TX Byte 0 ==
4587 23:07:15.721892 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4588 23:07:15.725580 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4589 23:07:15.729277 == TX Byte 1 ==
4590 23:07:15.732144 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4591 23:07:15.735212 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4592 23:07:15.735293 ==
4593 23:07:15.738837 Dram Type= 6, Freq= 0, CH_1, rank 0
4594 23:07:15.741941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4595 23:07:15.745379 ==
4596 23:07:15.745460
4597 23:07:15.745524
4598 23:07:15.745607 TX Vref Scan disable
4599 23:07:15.749177 == TX Byte 0 ==
4600 23:07:15.752417 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4601 23:07:15.759095 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4602 23:07:15.759181 == TX Byte 1 ==
4603 23:07:15.762637 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4604 23:07:15.768887 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4605 23:07:15.768968
4606 23:07:15.769033 [DATLAT]
4607 23:07:15.769093 Freq=600, CH1 RK0
4608 23:07:15.769150
4609 23:07:15.772398 DATLAT Default: 0x9
4610 23:07:15.772479 0, 0xFFFF, sum = 0
4611 23:07:15.775475 1, 0xFFFF, sum = 0
4612 23:07:15.778931 2, 0xFFFF, sum = 0
4613 23:07:15.779055 3, 0xFFFF, sum = 0
4614 23:07:15.782190 4, 0xFFFF, sum = 0
4615 23:07:15.782305 5, 0xFFFF, sum = 0
4616 23:07:15.785385 6, 0xFFFF, sum = 0
4617 23:07:15.785467 7, 0xFFFF, sum = 0
4618 23:07:15.788591 8, 0x0, sum = 1
4619 23:07:15.788673 9, 0x0, sum = 2
4620 23:07:15.788738 10, 0x0, sum = 3
4621 23:07:15.791778 11, 0x0, sum = 4
4622 23:07:15.791859 best_step = 9
4623 23:07:15.791924
4624 23:07:15.792013 ==
4625 23:07:15.795228 Dram Type= 6, Freq= 0, CH_1, rank 0
4626 23:07:15.802271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4627 23:07:15.802354 ==
4628 23:07:15.802418 RX Vref Scan: 1
4629 23:07:15.802478
4630 23:07:15.805021 RX Vref 0 -> 0, step: 1
4631 23:07:15.805103
4632 23:07:15.808662 RX Delay -195 -> 252, step: 8
4633 23:07:15.808747
4634 23:07:15.811544 Set Vref, RX VrefLevel [Byte0]: 54
4635 23:07:15.814831 [Byte1]: 50
4636 23:07:15.814934
4637 23:07:15.818245 Final RX Vref Byte 0 = 54 to rank0
4638 23:07:15.821719 Final RX Vref Byte 1 = 50 to rank0
4639 23:07:15.824885 Final RX Vref Byte 0 = 54 to rank1
4640 23:07:15.828408 Final RX Vref Byte 1 = 50 to rank1==
4641 23:07:15.831434 Dram Type= 6, Freq= 0, CH_1, rank 0
4642 23:07:15.834912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4643 23:07:15.838477 ==
4644 23:07:15.838563 DQS Delay:
4645 23:07:15.838653 DQS0 = 0, DQS1 = 0
4646 23:07:15.841516 DQM Delay:
4647 23:07:15.841607 DQM0 = 39, DQM1 = 29
4648 23:07:15.844601 DQ Delay:
4649 23:07:15.844738 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =36
4650 23:07:15.847932 DQ4 =36, DQ5 =52, DQ6 =48, DQ7 =36
4651 23:07:15.851278 DQ8 =16, DQ9 =16, DQ10 =32, DQ11 =20
4652 23:07:15.854656 DQ12 =40, DQ13 =36, DQ14 =36, DQ15 =36
4653 23:07:15.854774
4654 23:07:15.858366
4655 23:07:15.864862 [DQSOSCAuto] RK0, (LSB)MR18= 0x2532, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 402 ps
4656 23:07:15.868039 CH1 RK0: MR19=808, MR18=2532
4657 23:07:15.874614 CH1_RK0: MR19=0x808, MR18=0x2532, DQSOSC=400, MR23=63, INC=163, DEC=109
4658 23:07:15.874813
4659 23:07:15.878104 ----->DramcWriteLeveling(PI) begin...
4660 23:07:15.878305 ==
4661 23:07:15.881724 Dram Type= 6, Freq= 0, CH_1, rank 1
4662 23:07:15.884607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4663 23:07:15.884904 ==
4664 23:07:15.888022 Write leveling (Byte 0): 31 => 31
4665 23:07:15.891355 Write leveling (Byte 1): 31 => 31
4666 23:07:15.895033 DramcWriteLeveling(PI) end<-----
4667 23:07:15.895442
4668 23:07:15.895766 ==
4669 23:07:15.898278 Dram Type= 6, Freq= 0, CH_1, rank 1
4670 23:07:15.901562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4671 23:07:15.901982 ==
4672 23:07:15.904809 [Gating] SW mode calibration
4673 23:07:15.911435 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4674 23:07:15.918249 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4675 23:07:15.921362 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4676 23:07:15.924500 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4677 23:07:15.931306 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4678 23:07:15.934498 0 9 12 | B1->B0 | 3333 2b2b | 1 1 | (1 0) (1 1)
4679 23:07:15.937813 0 9 16 | B1->B0 | 2a2a 2323 | 1 0 | (0 0) (0 0)
4680 23:07:15.944446 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4681 23:07:15.948026 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4682 23:07:15.951044 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4683 23:07:15.957699 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4684 23:07:15.961131 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4685 23:07:15.964048 0 10 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
4686 23:07:15.971008 0 10 12 | B1->B0 | 2626 3b3b | 0 0 | (0 0) (0 0)
4687 23:07:15.974310 0 10 16 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
4688 23:07:15.977563 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4689 23:07:15.984646 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4690 23:07:15.987830 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4691 23:07:15.990772 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4692 23:07:15.997426 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4693 23:07:16.001221 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4694 23:07:16.003805 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4695 23:07:16.010818 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4696 23:07:16.013750 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4697 23:07:16.017203 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4698 23:07:16.023738 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4699 23:07:16.027044 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4700 23:07:16.030020 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4701 23:07:16.036577 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4702 23:07:16.040335 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4703 23:07:16.043211 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4704 23:07:16.049798 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4705 23:07:16.053511 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4706 23:07:16.056910 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4707 23:07:16.063368 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4708 23:07:16.066478 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4709 23:07:16.070143 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4710 23:07:16.076379 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4711 23:07:16.080125 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4712 23:07:16.083691 Total UI for P1: 0, mck2ui 16
4713 23:07:16.086332 best dqsien dly found for B0: ( 0, 13, 14)
4714 23:07:16.089964 Total UI for P1: 0, mck2ui 16
4715 23:07:16.093690 best dqsien dly found for B1: ( 0, 13, 14)
4716 23:07:16.096534 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4717 23:07:16.099747 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4718 23:07:16.099843
4719 23:07:16.102955 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4720 23:07:16.106530 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4721 23:07:16.109360 [Gating] SW calibration Done
4722 23:07:16.109433 ==
4723 23:07:16.112830 Dram Type= 6, Freq= 0, CH_1, rank 1
4724 23:07:16.115909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4725 23:07:16.119211 ==
4726 23:07:16.119281 RX Vref Scan: 0
4727 23:07:16.119349
4728 23:07:16.122921 RX Vref 0 -> 0, step: 1
4729 23:07:16.122999
4730 23:07:16.126011 RX Delay -230 -> 252, step: 16
4731 23:07:16.129294 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4732 23:07:16.133039 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4733 23:07:16.135986 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4734 23:07:16.142925 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4735 23:07:16.146071 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4736 23:07:16.148854 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4737 23:07:16.152691 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4738 23:07:16.155745 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4739 23:07:16.162461 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4740 23:07:16.165593 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4741 23:07:16.168726 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4742 23:07:16.172477 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4743 23:07:16.178967 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4744 23:07:16.182315 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4745 23:07:16.185914 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4746 23:07:16.188674 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4747 23:07:16.192524 ==
4748 23:07:16.195562 Dram Type= 6, Freq= 0, CH_1, rank 1
4749 23:07:16.199245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4750 23:07:16.199319 ==
4751 23:07:16.199382 DQS Delay:
4752 23:07:16.202606 DQS0 = 0, DQS1 = 0
4753 23:07:16.202676 DQM Delay:
4754 23:07:16.205805 DQM0 = 35, DQM1 = 30
4755 23:07:16.205877 DQ Delay:
4756 23:07:16.208862 DQ0 =33, DQ1 =33, DQ2 =17, DQ3 =33
4757 23:07:16.212121 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4758 23:07:16.215190 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4759 23:07:16.218767 DQ12 =33, DQ13 =41, DQ14 =33, DQ15 =33
4760 23:07:16.218871
4761 23:07:16.218938
4762 23:07:16.219010 ==
4763 23:07:16.221848 Dram Type= 6, Freq= 0, CH_1, rank 1
4764 23:07:16.225551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4765 23:07:16.225623 ==
4766 23:07:16.225683
4767 23:07:16.225740
4768 23:07:16.228609 TX Vref Scan disable
4769 23:07:16.231728 == TX Byte 0 ==
4770 23:07:16.235377 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4771 23:07:16.238607 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4772 23:07:16.241588 == TX Byte 1 ==
4773 23:07:16.245100 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4774 23:07:16.248183 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4775 23:07:16.248288 ==
4776 23:07:16.251548 Dram Type= 6, Freq= 0, CH_1, rank 1
4777 23:07:16.258115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4778 23:07:16.258233 ==
4779 23:07:16.258327
4780 23:07:16.258414
4781 23:07:16.258533 TX Vref Scan disable
4782 23:07:16.263038 == TX Byte 0 ==
4783 23:07:16.266181 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4784 23:07:16.272296 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4785 23:07:16.272370 == TX Byte 1 ==
4786 23:07:16.275553 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4787 23:07:16.282586 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4788 23:07:16.282662
4789 23:07:16.282729 [DATLAT]
4790 23:07:16.282788 Freq=600, CH1 RK1
4791 23:07:16.282847
4792 23:07:16.285535 DATLAT Default: 0x9
4793 23:07:16.285602 0, 0xFFFF, sum = 0
4794 23:07:16.289019 1, 0xFFFF, sum = 0
4795 23:07:16.289116 2, 0xFFFF, sum = 0
4796 23:07:16.292326 3, 0xFFFF, sum = 0
4797 23:07:16.295823 4, 0xFFFF, sum = 0
4798 23:07:16.295894 5, 0xFFFF, sum = 0
4799 23:07:16.298806 6, 0xFFFF, sum = 0
4800 23:07:16.298880 7, 0xFFFF, sum = 0
4801 23:07:16.302179 8, 0x0, sum = 1
4802 23:07:16.302253 9, 0x0, sum = 2
4803 23:07:16.302313 10, 0x0, sum = 3
4804 23:07:16.305263 11, 0x0, sum = 4
4805 23:07:16.305331 best_step = 9
4806 23:07:16.305389
4807 23:07:16.305449 ==
4808 23:07:16.308849 Dram Type= 6, Freq= 0, CH_1, rank 1
4809 23:07:16.315434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4810 23:07:16.315515 ==
4811 23:07:16.315577 RX Vref Scan: 0
4812 23:07:16.315636
4813 23:07:16.318860 RX Vref 0 -> 0, step: 1
4814 23:07:16.318955
4815 23:07:16.322287 RX Delay -195 -> 252, step: 8
4816 23:07:16.325564 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4817 23:07:16.332071 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4818 23:07:16.335600 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4819 23:07:16.338961 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4820 23:07:16.342328 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4821 23:07:16.348719 iDelay=205, Bit 5, Center 44 (-115 ~ 204) 320
4822 23:07:16.351831 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4823 23:07:16.355410 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4824 23:07:16.358726 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4825 23:07:16.361900 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4826 23:07:16.369053 iDelay=205, Bit 10, Center 32 (-131 ~ 196) 328
4827 23:07:16.372152 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4828 23:07:16.375324 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4829 23:07:16.378478 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4830 23:07:16.384790 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4831 23:07:16.388585 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4832 23:07:16.388666 ==
4833 23:07:16.391501 Dram Type= 6, Freq= 0, CH_1, rank 1
4834 23:07:16.395083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4835 23:07:16.395167 ==
4836 23:07:16.398378 DQS Delay:
4837 23:07:16.398461 DQS0 = 0, DQS1 = 0
4838 23:07:16.401372 DQM Delay:
4839 23:07:16.401463 DQM0 = 35, DQM1 = 29
4840 23:07:16.401540 DQ Delay:
4841 23:07:16.404907 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4842 23:07:16.408063 DQ4 =32, DQ5 =44, DQ6 =44, DQ7 =32
4843 23:07:16.411358 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =20
4844 23:07:16.415366 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4845 23:07:16.415499
4846 23:07:16.415605
4847 23:07:16.424895 [DQSOSCAuto] RK1, (LSB)MR18= 0x3d5d, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 398 ps
4848 23:07:16.427954 CH1 RK1: MR19=808, MR18=3D5D
4849 23:07:16.434647 CH1_RK1: MR19=0x808, MR18=0x3D5D, DQSOSC=392, MR23=63, INC=170, DEC=113
4850 23:07:16.434728 [RxdqsGatingPostProcess] freq 600
4851 23:07:16.441314 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4852 23:07:16.444499 Pre-setting of DQS Precalculation
4853 23:07:16.450977 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4854 23:07:16.457920 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4855 23:07:16.464372 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4856 23:07:16.464453
4857 23:07:16.464517
4858 23:07:16.467544 [Calibration Summary] 1200 Mbps
4859 23:07:16.467624 CH 0, Rank 0
4860 23:07:16.470789 SW Impedance : PASS
4861 23:07:16.473984 DUTY Scan : NO K
4862 23:07:16.474065 ZQ Calibration : PASS
4863 23:07:16.477240 Jitter Meter : NO K
4864 23:07:16.477320 CBT Training : PASS
4865 23:07:16.480564 Write leveling : PASS
4866 23:07:16.483867 RX DQS gating : PASS
4867 23:07:16.483947 RX DQ/DQS(RDDQC) : PASS
4868 23:07:16.487718 TX DQ/DQS : PASS
4869 23:07:16.490763 RX DATLAT : PASS
4870 23:07:16.490869 RX DQ/DQS(Engine): PASS
4871 23:07:16.493941 TX OE : NO K
4872 23:07:16.494022 All Pass.
4873 23:07:16.494085
4874 23:07:16.497561 CH 0, Rank 1
4875 23:07:16.497641 SW Impedance : PASS
4876 23:07:16.500518 DUTY Scan : NO K
4877 23:07:16.504206 ZQ Calibration : PASS
4878 23:07:16.504321 Jitter Meter : NO K
4879 23:07:16.507002 CBT Training : PASS
4880 23:07:16.510626 Write leveling : PASS
4881 23:07:16.510698 RX DQS gating : PASS
4882 23:07:16.513895 RX DQ/DQS(RDDQC) : PASS
4883 23:07:16.516992 TX DQ/DQS : PASS
4884 23:07:16.517095 RX DATLAT : PASS
4885 23:07:16.520502 RX DQ/DQS(Engine): PASS
4886 23:07:16.523285 TX OE : NO K
4887 23:07:16.523356 All Pass.
4888 23:07:16.523416
4889 23:07:16.523480 CH 1, Rank 0
4890 23:07:16.526891 SW Impedance : PASS
4891 23:07:16.530024 DUTY Scan : NO K
4892 23:07:16.530097 ZQ Calibration : PASS
4893 23:07:16.533338 Jitter Meter : NO K
4894 23:07:16.536681 CBT Training : PASS
4895 23:07:16.536752 Write leveling : PASS
4896 23:07:16.539974 RX DQS gating : PASS
4897 23:07:16.543484 RX DQ/DQS(RDDQC) : PASS
4898 23:07:16.543582 TX DQ/DQS : PASS
4899 23:07:16.546718 RX DATLAT : PASS
4900 23:07:16.546789 RX DQ/DQS(Engine): PASS
4901 23:07:16.549786 TX OE : NO K
4902 23:07:16.549854 All Pass.
4903 23:07:16.549913
4904 23:07:16.553510 CH 1, Rank 1
4905 23:07:16.553606 SW Impedance : PASS
4906 23:07:16.557037 DUTY Scan : NO K
4907 23:07:16.560316 ZQ Calibration : PASS
4908 23:07:16.560412 Jitter Meter : NO K
4909 23:07:16.563492 CBT Training : PASS
4910 23:07:16.566731 Write leveling : PASS
4911 23:07:16.566803 RX DQS gating : PASS
4912 23:07:16.569726 RX DQ/DQS(RDDQC) : PASS
4913 23:07:16.573298 TX DQ/DQS : PASS
4914 23:07:16.573369 RX DATLAT : PASS
4915 23:07:16.576973 RX DQ/DQS(Engine): PASS
4916 23:07:16.580066 TX OE : NO K
4917 23:07:16.580137 All Pass.
4918 23:07:16.580206
4919 23:07:16.583220 DramC Write-DBI off
4920 23:07:16.583289 PER_BANK_REFRESH: Hybrid Mode
4921 23:07:16.586136 TX_TRACKING: ON
4922 23:07:16.593296 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4923 23:07:16.599671 [FAST_K] Save calibration result to emmc
4924 23:07:16.603099 dramc_set_vcore_voltage set vcore to 662500
4925 23:07:16.603198 Read voltage for 933, 3
4926 23:07:16.605977 Vio18 = 0
4927 23:07:16.606048 Vcore = 662500
4928 23:07:16.606108 Vdram = 0
4929 23:07:16.609624 Vddq = 0
4930 23:07:16.609697 Vmddr = 0
4931 23:07:16.612973 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4932 23:07:16.619349 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4933 23:07:16.622752 MEM_TYPE=3, freq_sel=17
4934 23:07:16.626097 sv_algorithm_assistance_LP4_1600
4935 23:07:16.629368 ============ PULL DRAM RESETB DOWN ============
4936 23:07:16.633062 ========== PULL DRAM RESETB DOWN end =========
4937 23:07:16.639337 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4938 23:07:16.642635 ===================================
4939 23:07:16.642745 LPDDR4 DRAM CONFIGURATION
4940 23:07:16.645958 ===================================
4941 23:07:16.649027 EX_ROW_EN[0] = 0x0
4942 23:07:16.649130 EX_ROW_EN[1] = 0x0
4943 23:07:16.652444 LP4Y_EN = 0x0
4944 23:07:16.652552 WORK_FSP = 0x0
4945 23:07:16.655832 WL = 0x3
4946 23:07:16.655918 RL = 0x3
4947 23:07:16.659372 BL = 0x2
4948 23:07:16.662570 RPST = 0x0
4949 23:07:16.662644 RD_PRE = 0x0
4950 23:07:16.665680 WR_PRE = 0x1
4951 23:07:16.665753 WR_PST = 0x0
4952 23:07:16.669048 DBI_WR = 0x0
4953 23:07:16.669115 DBI_RD = 0x0
4954 23:07:16.672742 OTF = 0x1
4955 23:07:16.675923 ===================================
4956 23:07:16.678831 ===================================
4957 23:07:16.678926 ANA top config
4958 23:07:16.682219 ===================================
4959 23:07:16.685396 DLL_ASYNC_EN = 0
4960 23:07:16.689232 ALL_SLAVE_EN = 1
4961 23:07:16.689301 NEW_RANK_MODE = 1
4962 23:07:16.692170 DLL_IDLE_MODE = 1
4963 23:07:16.695357 LP45_APHY_COMB_EN = 1
4964 23:07:16.698665 TX_ODT_DIS = 1
4965 23:07:16.702063 NEW_8X_MODE = 1
4966 23:07:16.705645 ===================================
4967 23:07:16.708856 ===================================
4968 23:07:16.708929 data_rate = 1866
4969 23:07:16.712307 CKR = 1
4970 23:07:16.715487 DQ_P2S_RATIO = 8
4971 23:07:16.718552 ===================================
4972 23:07:16.721983 CA_P2S_RATIO = 8
4973 23:07:16.725680 DQ_CA_OPEN = 0
4974 23:07:16.728474 DQ_SEMI_OPEN = 0
4975 23:07:16.728572 CA_SEMI_OPEN = 0
4976 23:07:16.732154 CA_FULL_RATE = 0
4977 23:07:16.735249 DQ_CKDIV4_EN = 1
4978 23:07:16.738781 CA_CKDIV4_EN = 1
4979 23:07:16.742143 CA_PREDIV_EN = 0
4980 23:07:16.745202 PH8_DLY = 0
4981 23:07:16.745285 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4982 23:07:16.748471 DQ_AAMCK_DIV = 4
4983 23:07:16.752132 CA_AAMCK_DIV = 4
4984 23:07:16.755281 CA_ADMCK_DIV = 4
4985 23:07:16.758459 DQ_TRACK_CA_EN = 0
4986 23:07:16.762132 CA_PICK = 933
4987 23:07:16.762208 CA_MCKIO = 933
4988 23:07:16.765150 MCKIO_SEMI = 0
4989 23:07:16.768562 PLL_FREQ = 3732
4990 23:07:16.771548 DQ_UI_PI_RATIO = 32
4991 23:07:16.775153 CA_UI_PI_RATIO = 0
4992 23:07:16.778514 ===================================
4993 23:07:16.781604 ===================================
4994 23:07:16.785156 memory_type:LPDDR4
4995 23:07:16.785229 GP_NUM : 10
4996 23:07:16.788178 SRAM_EN : 1
4997 23:07:16.788261 MD32_EN : 0
4998 23:07:16.792034 ===================================
4999 23:07:16.795240 [ANA_INIT] >>>>>>>>>>>>>>
5000 23:07:16.798387 <<<<<< [CONFIGURE PHASE]: ANA_TX
5001 23:07:16.801442 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5002 23:07:16.804920 ===================================
5003 23:07:16.808152 data_rate = 1866,PCW = 0X8f00
5004 23:07:16.811325 ===================================
5005 23:07:16.815122 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5006 23:07:16.821466 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5007 23:07:16.824713 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5008 23:07:16.831281 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5009 23:07:16.835025 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5010 23:07:16.838199 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5011 23:07:16.838277 [ANA_INIT] flow start
5012 23:07:16.841407 [ANA_INIT] PLL >>>>>>>>
5013 23:07:16.844855 [ANA_INIT] PLL <<<<<<<<
5014 23:07:16.844949 [ANA_INIT] MIDPI >>>>>>>>
5015 23:07:16.847825 [ANA_INIT] MIDPI <<<<<<<<
5016 23:07:16.851335 [ANA_INIT] DLL >>>>>>>>
5017 23:07:16.851467 [ANA_INIT] flow end
5018 23:07:16.857646 ============ LP4 DIFF to SE enter ============
5019 23:07:16.861033 ============ LP4 DIFF to SE exit ============
5020 23:07:16.864176 [ANA_INIT] <<<<<<<<<<<<<
5021 23:07:16.867538 [Flow] Enable top DCM control >>>>>
5022 23:07:16.871447 [Flow] Enable top DCM control <<<<<
5023 23:07:16.871606 Enable DLL master slave shuffle
5024 23:07:16.877841 ==============================================================
5025 23:07:16.881052 Gating Mode config
5026 23:07:16.884685 ==============================================================
5027 23:07:16.888148 Config description:
5028 23:07:16.897668 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5029 23:07:16.904294 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5030 23:07:16.907749 SELPH_MODE 0: By rank 1: By Phase
5031 23:07:16.914396 ==============================================================
5032 23:07:16.917595 GAT_TRACK_EN = 1
5033 23:07:16.921131 RX_GATING_MODE = 2
5034 23:07:16.924052 RX_GATING_TRACK_MODE = 2
5035 23:07:16.928082 SELPH_MODE = 1
5036 23:07:16.931018 PICG_EARLY_EN = 1
5037 23:07:16.931499 VALID_LAT_VALUE = 1
5038 23:07:16.937671 ==============================================================
5039 23:07:16.941020 Enter into Gating configuration >>>>
5040 23:07:16.943904 Exit from Gating configuration <<<<
5041 23:07:16.947292 Enter into DVFS_PRE_config >>>>>
5042 23:07:16.957684 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5043 23:07:16.960715 Exit from DVFS_PRE_config <<<<<
5044 23:07:16.963980 Enter into PICG configuration >>>>
5045 23:07:16.967266 Exit from PICG configuration <<<<
5046 23:07:16.970566 [RX_INPUT] configuration >>>>>
5047 23:07:16.974308 [RX_INPUT] configuration <<<<<
5048 23:07:16.980903 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5049 23:07:16.983956 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5050 23:07:16.990501 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5051 23:07:16.997054 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5052 23:07:17.003970 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5053 23:07:17.010424 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5054 23:07:17.014048 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5055 23:07:17.017234 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5056 23:07:17.020245 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5057 23:07:17.027119 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5058 23:07:17.030460 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5059 23:07:17.034249 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5060 23:07:17.036932 ===================================
5061 23:07:17.040710 LPDDR4 DRAM CONFIGURATION
5062 23:07:17.043790 ===================================
5063 23:07:17.044245 EX_ROW_EN[0] = 0x0
5064 23:07:17.047181 EX_ROW_EN[1] = 0x0
5065 23:07:17.047597 LP4Y_EN = 0x0
5066 23:07:17.050283 WORK_FSP = 0x0
5067 23:07:17.050842 WL = 0x3
5068 23:07:17.053704 RL = 0x3
5069 23:07:17.057149 BL = 0x2
5070 23:07:17.057603 RPST = 0x0
5071 23:07:17.060298 RD_PRE = 0x0
5072 23:07:17.060730 WR_PRE = 0x1
5073 23:07:17.063619 WR_PST = 0x0
5074 23:07:17.064045 DBI_WR = 0x0
5075 23:07:17.067043 DBI_RD = 0x0
5076 23:07:17.067468 OTF = 0x1
5077 23:07:17.070504 ===================================
5078 23:07:17.073860 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5079 23:07:17.080644 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5080 23:07:17.083751 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5081 23:07:17.087089 ===================================
5082 23:07:17.090333 LPDDR4 DRAM CONFIGURATION
5083 23:07:17.094076 ===================================
5084 23:07:17.094513 EX_ROW_EN[0] = 0x10
5085 23:07:17.096817 EX_ROW_EN[1] = 0x0
5086 23:07:17.097318 LP4Y_EN = 0x0
5087 23:07:17.100034 WORK_FSP = 0x0
5088 23:07:17.100590 WL = 0x3
5089 23:07:17.103778 RL = 0x3
5090 23:07:17.104339 BL = 0x2
5091 23:07:17.106845 RPST = 0x0
5092 23:07:17.110182 RD_PRE = 0x0
5093 23:07:17.110672 WR_PRE = 0x1
5094 23:07:17.113117 WR_PST = 0x0
5095 23:07:17.113561 DBI_WR = 0x0
5096 23:07:17.116372 DBI_RD = 0x0
5097 23:07:17.116759 OTF = 0x1
5098 23:07:17.119994 ===================================
5099 23:07:17.126507 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5100 23:07:17.130311 nWR fixed to 30
5101 23:07:17.133656 [ModeRegInit_LP4] CH0 RK0
5102 23:07:17.134139 [ModeRegInit_LP4] CH0 RK1
5103 23:07:17.137496 [ModeRegInit_LP4] CH1 RK0
5104 23:07:17.140659 [ModeRegInit_LP4] CH1 RK1
5105 23:07:17.141138 match AC timing 9
5106 23:07:17.146947 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5107 23:07:17.150173 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5108 23:07:17.154173 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5109 23:07:17.160367 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5110 23:07:17.163623 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5111 23:07:17.164258 ==
5112 23:07:17.166720 Dram Type= 6, Freq= 0, CH_0, rank 0
5113 23:07:17.170155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5114 23:07:17.170751 ==
5115 23:07:17.177027 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5116 23:07:17.183363 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5117 23:07:17.187054 [CA 0] Center 38 (8~69) winsize 62
5118 23:07:17.190203 [CA 1] Center 38 (7~69) winsize 63
5119 23:07:17.193595 [CA 2] Center 35 (5~65) winsize 61
5120 23:07:17.196771 [CA 3] Center 35 (5~65) winsize 61
5121 23:07:17.199785 [CA 4] Center 34 (4~65) winsize 62
5122 23:07:17.203645 [CA 5] Center 33 (3~64) winsize 62
5123 23:07:17.204288
5124 23:07:17.206771 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5125 23:07:17.207334
5126 23:07:17.210008 [CATrainingPosCal] consider 1 rank data
5127 23:07:17.213314 u2DelayCellTimex100 = 270/100 ps
5128 23:07:17.216737 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5129 23:07:17.220265 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5130 23:07:17.223363 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5131 23:07:17.226583 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5132 23:07:17.230142 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5133 23:07:17.233393 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5134 23:07:17.236658
5135 23:07:17.239959 CA PerBit enable=1, Macro0, CA PI delay=33
5136 23:07:17.240464
5137 23:07:17.243309 [CBTSetCACLKResult] CA Dly = 33
5138 23:07:17.243720 CS Dly: 6 (0~37)
5139 23:07:17.244044 ==
5140 23:07:17.246604 Dram Type= 6, Freq= 0, CH_0, rank 1
5141 23:07:17.249730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5142 23:07:17.250145 ==
5143 23:07:17.256756 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5144 23:07:17.263224 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5145 23:07:17.266370 [CA 0] Center 38 (8~69) winsize 62
5146 23:07:17.269623 [CA 1] Center 38 (8~69) winsize 62
5147 23:07:17.273407 [CA 2] Center 35 (5~66) winsize 62
5148 23:07:17.276274 [CA 3] Center 35 (5~65) winsize 61
5149 23:07:17.280130 [CA 4] Center 34 (4~65) winsize 62
5150 23:07:17.283422 [CA 5] Center 34 (3~65) winsize 63
5151 23:07:17.283958
5152 23:07:17.286577 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5153 23:07:17.287084
5154 23:07:17.289518 [CATrainingPosCal] consider 2 rank data
5155 23:07:17.293013 u2DelayCellTimex100 = 270/100 ps
5156 23:07:17.296277 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5157 23:07:17.299912 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5158 23:07:17.302957 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5159 23:07:17.306651 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5160 23:07:17.310015 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5161 23:07:17.316193 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5162 23:07:17.316707
5163 23:07:17.319443 CA PerBit enable=1, Macro0, CA PI delay=33
5164 23:07:17.320067
5165 23:07:17.323260 [CBTSetCACLKResult] CA Dly = 33
5166 23:07:17.323881 CS Dly: 6 (0~38)
5167 23:07:17.324421
5168 23:07:17.326664 ----->DramcWriteLeveling(PI) begin...
5169 23:07:17.327213 ==
5170 23:07:17.329787 Dram Type= 6, Freq= 0, CH_0, rank 0
5171 23:07:17.336405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5172 23:07:17.336916 ==
5173 23:07:17.339705 Write leveling (Byte 0): 32 => 32
5174 23:07:17.340169 Write leveling (Byte 1): 30 => 30
5175 23:07:17.342863 DramcWriteLeveling(PI) end<-----
5176 23:07:17.343272
5177 23:07:17.346178 ==
5178 23:07:17.349617 Dram Type= 6, Freq= 0, CH_0, rank 0
5179 23:07:17.352522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5180 23:07:17.353123 ==
5181 23:07:17.356561 [Gating] SW mode calibration
5182 23:07:17.362546 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5183 23:07:17.366191 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5184 23:07:17.372798 0 14 0 | B1->B0 | 2323 3130 | 0 1 | (0 0) (1 1)
5185 23:07:17.375582 0 14 4 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
5186 23:07:17.379386 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5187 23:07:17.385852 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5188 23:07:17.389316 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5189 23:07:17.392300 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5190 23:07:17.399208 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5191 23:07:17.402074 0 14 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5192 23:07:17.405310 0 15 0 | B1->B0 | 3434 2c2c | 0 0 | (0 0) (1 1)
5193 23:07:17.411842 0 15 4 | B1->B0 | 2929 2323 | 0 0 | (1 1) (0 0)
5194 23:07:17.415147 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5195 23:07:17.418547 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5196 23:07:17.425255 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5197 23:07:17.428736 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5198 23:07:17.432190 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5199 23:07:17.438505 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5200 23:07:17.441707 1 0 0 | B1->B0 | 2424 3b3b | 1 0 | (0 0) (0 0)
5201 23:07:17.445041 1 0 4 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
5202 23:07:17.451623 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5203 23:07:17.454985 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5204 23:07:17.458099 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5205 23:07:17.465018 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5206 23:07:17.468148 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5207 23:07:17.472066 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5208 23:07:17.478017 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5209 23:07:17.481600 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5210 23:07:17.484758 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5211 23:07:17.491758 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5212 23:07:17.494768 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5213 23:07:17.497866 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5214 23:07:17.504330 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5215 23:07:17.507888 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5216 23:07:17.511266 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5217 23:07:17.517675 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5218 23:07:17.520958 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5219 23:07:17.524860 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5220 23:07:17.531348 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5221 23:07:17.534607 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5222 23:07:17.538221 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5223 23:07:17.544484 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5224 23:07:17.547521 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5225 23:07:17.550763 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5226 23:07:17.553978 Total UI for P1: 0, mck2ui 16
5227 23:07:17.557279 best dqsien dly found for B0: ( 1, 2, 30)
5228 23:07:17.560743 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5229 23:07:17.564061 Total UI for P1: 0, mck2ui 16
5230 23:07:17.567449 best dqsien dly found for B1: ( 1, 3, 4)
5231 23:07:17.570850 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5232 23:07:17.577293 best DQS1 dly(MCK, UI, PI) = (1, 3, 4)
5233 23:07:17.577660
5234 23:07:17.580794 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5235 23:07:17.584270 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 4)
5236 23:07:17.587349 [Gating] SW calibration Done
5237 23:07:17.587782 ==
5238 23:07:17.590659 Dram Type= 6, Freq= 0, CH_0, rank 0
5239 23:07:17.594252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5240 23:07:17.594614 ==
5241 23:07:17.597619 RX Vref Scan: 0
5242 23:07:17.597980
5243 23:07:17.598274 RX Vref 0 -> 0, step: 1
5244 23:07:17.598539
5245 23:07:17.600825 RX Delay -80 -> 252, step: 8
5246 23:07:17.604257 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5247 23:07:17.607716 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5248 23:07:17.614238 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5249 23:07:17.617699 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5250 23:07:17.620657 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5251 23:07:17.623765 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5252 23:07:17.627339 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5253 23:07:17.630802 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5254 23:07:17.637481 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5255 23:07:17.640657 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5256 23:07:17.644175 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5257 23:07:17.647506 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5258 23:07:17.650615 iDelay=208, Bit 12, Center 87 (-16 ~ 191) 208
5259 23:07:17.657121 iDelay=208, Bit 13, Center 87 (-16 ~ 191) 208
5260 23:07:17.660454 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5261 23:07:17.664262 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5262 23:07:17.664660 ==
5263 23:07:17.667206 Dram Type= 6, Freq= 0, CH_0, rank 0
5264 23:07:17.670724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5265 23:07:17.671226 ==
5266 23:07:17.673949 DQS Delay:
5267 23:07:17.674454 DQS0 = 0, DQS1 = 0
5268 23:07:17.677149 DQM Delay:
5269 23:07:17.677558 DQM0 = 95, DQM1 = 83
5270 23:07:17.677879 DQ Delay:
5271 23:07:17.680469 DQ0 =95, DQ1 =95, DQ2 =91, DQ3 =91
5272 23:07:17.684197 DQ4 =99, DQ5 =79, DQ6 =103, DQ7 =111
5273 23:07:17.687211 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =79
5274 23:07:17.690481 DQ12 =87, DQ13 =87, DQ14 =91, DQ15 =91
5275 23:07:17.690982
5276 23:07:17.691416
5277 23:07:17.693975 ==
5278 23:07:17.697100 Dram Type= 6, Freq= 0, CH_0, rank 0
5279 23:07:17.700253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5280 23:07:17.700615 ==
5281 23:07:17.700961
5282 23:07:17.701266
5283 23:07:17.704005 TX Vref Scan disable
5284 23:07:17.704405 == TX Byte 0 ==
5285 23:07:17.707339 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5286 23:07:17.713795 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5287 23:07:17.714162 == TX Byte 1 ==
5288 23:07:17.717062 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5289 23:07:17.723797 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5290 23:07:17.724158 ==
5291 23:07:17.727090 Dram Type= 6, Freq= 0, CH_0, rank 0
5292 23:07:17.730502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5293 23:07:17.730857 ==
5294 23:07:17.731152
5295 23:07:17.731426
5296 23:07:17.733777 TX Vref Scan disable
5297 23:07:17.737028 == TX Byte 0 ==
5298 23:07:17.740039 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5299 23:07:17.743960 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5300 23:07:17.746975 == TX Byte 1 ==
5301 23:07:17.750596 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5302 23:07:17.753622 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5303 23:07:17.754077
5304 23:07:17.756883 [DATLAT]
5305 23:07:17.757264 Freq=933, CH0 RK0
5306 23:07:17.757597
5307 23:07:17.760064 DATLAT Default: 0xd
5308 23:07:17.760549 0, 0xFFFF, sum = 0
5309 23:07:17.763321 1, 0xFFFF, sum = 0
5310 23:07:17.763690 2, 0xFFFF, sum = 0
5311 23:07:17.766537 3, 0xFFFF, sum = 0
5312 23:07:17.766929 4, 0xFFFF, sum = 0
5313 23:07:17.770520 5, 0xFFFF, sum = 0
5314 23:07:17.770961 6, 0xFFFF, sum = 0
5315 23:07:17.773629 7, 0xFFFF, sum = 0
5316 23:07:17.774019 8, 0xFFFF, sum = 0
5317 23:07:17.776867 9, 0xFFFF, sum = 0
5318 23:07:17.777244 10, 0x0, sum = 1
5319 23:07:17.780295 11, 0x0, sum = 2
5320 23:07:17.780688 12, 0x0, sum = 3
5321 23:07:17.783360 13, 0x0, sum = 4
5322 23:07:17.783858 best_step = 11
5323 23:07:17.784357
5324 23:07:17.784789 ==
5325 23:07:17.787136 Dram Type= 6, Freq= 0, CH_0, rank 0
5326 23:07:17.793335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5327 23:07:17.793819 ==
5328 23:07:17.794133 RX Vref Scan: 1
5329 23:07:17.794452
5330 23:07:17.796674 RX Vref 0 -> 0, step: 1
5331 23:07:17.797109
5332 23:07:17.800035 RX Delay -69 -> 252, step: 4
5333 23:07:17.800481
5334 23:07:17.803189 Set Vref, RX VrefLevel [Byte0]: 61
5335 23:07:17.806406 [Byte1]: 47
5336 23:07:17.806807
5337 23:07:17.809684 Final RX Vref Byte 0 = 61 to rank0
5338 23:07:17.813395 Final RX Vref Byte 1 = 47 to rank0
5339 23:07:17.816168 Final RX Vref Byte 0 = 61 to rank1
5340 23:07:17.819683 Final RX Vref Byte 1 = 47 to rank1==
5341 23:07:17.822867 Dram Type= 6, Freq= 0, CH_0, rank 0
5342 23:07:17.826176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5343 23:07:17.826702 ==
5344 23:07:17.829830 DQS Delay:
5345 23:07:17.830334 DQS0 = 0, DQS1 = 0
5346 23:07:17.830772 DQM Delay:
5347 23:07:17.833265 DQM0 = 95, DQM1 = 82
5348 23:07:17.833661 DQ Delay:
5349 23:07:17.836247 DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =92
5350 23:07:17.839625 DQ4 =96, DQ5 =84, DQ6 =102, DQ7 =106
5351 23:07:17.842712 DQ8 =74, DQ9 =70, DQ10 =82, DQ11 =76
5352 23:07:17.845856 DQ12 =86, DQ13 =88, DQ14 =94, DQ15 =90
5353 23:07:17.846357
5354 23:07:17.846801
5355 23:07:17.855909 [DQSOSCAuto] RK0, (LSB)MR18= 0x1413, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 415 ps
5356 23:07:17.859169 CH0 RK0: MR19=505, MR18=1413
5357 23:07:17.862623 CH0_RK0: MR19=0x505, MR18=0x1413, DQSOSC=415, MR23=63, INC=62, DEC=41
5358 23:07:17.866506
5359 23:07:17.869228 ----->DramcWriteLeveling(PI) begin...
5360 23:07:17.869601 ==
5361 23:07:17.873039 Dram Type= 6, Freq= 0, CH_0, rank 1
5362 23:07:17.876116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5363 23:07:17.876501 ==
5364 23:07:17.878978 Write leveling (Byte 0): 30 => 30
5365 23:07:17.882551 Write leveling (Byte 1): 29 => 29
5366 23:07:17.885896 DramcWriteLeveling(PI) end<-----
5367 23:07:17.886254
5368 23:07:17.886538 ==
5369 23:07:17.889161 Dram Type= 6, Freq= 0, CH_0, rank 1
5370 23:07:17.892498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5371 23:07:17.892850 ==
5372 23:07:17.896143 [Gating] SW mode calibration
5373 23:07:17.902600 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5374 23:07:17.908758 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5375 23:07:17.912019 0 14 0 | B1->B0 | 2828 3434 | 1 1 | (1 1) (1 1)
5376 23:07:17.915036 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5377 23:07:17.921769 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5378 23:07:17.925020 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5379 23:07:17.928488 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5380 23:07:17.934814 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5381 23:07:17.938047 0 14 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5382 23:07:17.941570 0 14 28 | B1->B0 | 3434 2c2c | 0 0 | (0 1) (0 0)
5383 23:07:17.948360 0 15 0 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
5384 23:07:17.951681 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5385 23:07:17.955056 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5386 23:07:17.961400 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5387 23:07:17.964452 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5388 23:07:17.967834 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5389 23:07:17.974569 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5390 23:07:17.978301 0 15 28 | B1->B0 | 2525 3737 | 0 0 | (0 0) (0 0)
5391 23:07:17.981279 1 0 0 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
5392 23:07:17.987877 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5393 23:07:17.991426 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5394 23:07:17.994609 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5395 23:07:18.001430 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5396 23:07:18.004655 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5397 23:07:18.007850 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5398 23:07:18.014501 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5399 23:07:18.018252 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5400 23:07:18.021375 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5401 23:07:18.027900 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5402 23:07:18.031332 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5403 23:07:18.034415 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5404 23:07:18.041114 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5405 23:07:18.044680 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5406 23:07:18.047493 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5407 23:07:18.051215 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5408 23:07:18.057682 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5409 23:07:18.061172 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5410 23:07:18.064591 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5411 23:07:18.071204 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5412 23:07:18.074380 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5413 23:07:18.078366 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5414 23:07:18.084497 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5415 23:07:18.087918 Total UI for P1: 0, mck2ui 16
5416 23:07:18.090836 best dqsien dly found for B0: ( 1, 2, 26)
5417 23:07:18.094033 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5418 23:07:18.097792 Total UI for P1: 0, mck2ui 16
5419 23:07:18.100783 best dqsien dly found for B1: ( 1, 2, 28)
5420 23:07:18.104004 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5421 23:07:18.107519 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5422 23:07:18.107973
5423 23:07:18.111076 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5424 23:07:18.117436 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5425 23:07:18.117893 [Gating] SW calibration Done
5426 23:07:18.118252 ==
5427 23:07:18.120713 Dram Type= 6, Freq= 0, CH_0, rank 1
5428 23:07:18.127536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5429 23:07:18.128096 ==
5430 23:07:18.128512 RX Vref Scan: 0
5431 23:07:18.128851
5432 23:07:18.130398 RX Vref 0 -> 0, step: 1
5433 23:07:18.130853
5434 23:07:18.133706 RX Delay -80 -> 252, step: 8
5435 23:07:18.137272 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5436 23:07:18.140575 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5437 23:07:18.143616 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5438 23:07:18.150550 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5439 23:07:18.153765 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5440 23:07:18.157222 iDelay=208, Bit 5, Center 75 (-24 ~ 175) 200
5441 23:07:18.160185 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5442 23:07:18.163863 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5443 23:07:18.167517 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5444 23:07:18.173651 iDelay=208, Bit 9, Center 63 (-32 ~ 159) 192
5445 23:07:18.177013 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5446 23:07:18.180522 iDelay=208, Bit 11, Center 71 (-24 ~ 167) 192
5447 23:07:18.183782 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5448 23:07:18.187064 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5449 23:07:18.193939 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5450 23:07:18.196712 iDelay=208, Bit 15, Center 87 (-8 ~ 183) 192
5451 23:07:18.197167 ==
5452 23:07:18.199965 Dram Type= 6, Freq= 0, CH_0, rank 1
5453 23:07:18.203399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5454 23:07:18.203854 ==
5455 23:07:18.206931 DQS Delay:
5456 23:07:18.207382 DQS0 = 0, DQS1 = 0
5457 23:07:18.207743 DQM Delay:
5458 23:07:18.210317 DQM0 = 92, DQM1 = 81
5459 23:07:18.210772 DQ Delay:
5460 23:07:18.213598 DQ0 =91, DQ1 =91, DQ2 =87, DQ3 =91
5461 23:07:18.216616 DQ4 =91, DQ5 =75, DQ6 =107, DQ7 =107
5462 23:07:18.220372 DQ8 =71, DQ9 =63, DQ10 =87, DQ11 =71
5463 23:07:18.223577 DQ12 =87, DQ13 =91, DQ14 =91, DQ15 =87
5464 23:07:18.224029
5465 23:07:18.224426
5466 23:07:18.224761 ==
5467 23:07:18.227101 Dram Type= 6, Freq= 0, CH_0, rank 1
5468 23:07:18.233392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5469 23:07:18.233853 ==
5470 23:07:18.234206
5471 23:07:18.234534
5472 23:07:18.234849 TX Vref Scan disable
5473 23:07:18.236567 == TX Byte 0 ==
5474 23:07:18.240317 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5475 23:07:18.246745 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5476 23:07:18.247286 == TX Byte 1 ==
5477 23:07:18.250268 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5478 23:07:18.256484 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5479 23:07:18.257039 ==
5480 23:07:18.260013 Dram Type= 6, Freq= 0, CH_0, rank 1
5481 23:07:18.263143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5482 23:07:18.263724 ==
5483 23:07:18.264162
5484 23:07:18.264639
5485 23:07:18.266250 TX Vref Scan disable
5486 23:07:18.266837 == TX Byte 0 ==
5487 23:07:18.272921 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5488 23:07:18.276422 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5489 23:07:18.276879 == TX Byte 1 ==
5490 23:07:18.282922 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5491 23:07:18.286373 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5492 23:07:18.286831
5493 23:07:18.287189 [DATLAT]
5494 23:07:18.289593 Freq=933, CH0 RK1
5495 23:07:18.290046
5496 23:07:18.290402 DATLAT Default: 0xb
5497 23:07:18.292726 0, 0xFFFF, sum = 0
5498 23:07:18.295947 1, 0xFFFF, sum = 0
5499 23:07:18.296468 2, 0xFFFF, sum = 0
5500 23:07:18.299292 3, 0xFFFF, sum = 0
5501 23:07:18.299814 4, 0xFFFF, sum = 0
5502 23:07:18.302767 5, 0xFFFF, sum = 0
5503 23:07:18.303227 6, 0xFFFF, sum = 0
5504 23:07:18.306445 7, 0xFFFF, sum = 0
5505 23:07:18.307007 8, 0xFFFF, sum = 0
5506 23:07:18.309068 9, 0xFFFF, sum = 0
5507 23:07:18.309530 10, 0x0, sum = 1
5508 23:07:18.312799 11, 0x0, sum = 2
5509 23:07:18.313258 12, 0x0, sum = 3
5510 23:07:18.316336 13, 0x0, sum = 4
5511 23:07:18.316797 best_step = 11
5512 23:07:18.317158
5513 23:07:18.317492 ==
5514 23:07:18.319416 Dram Type= 6, Freq= 0, CH_0, rank 1
5515 23:07:18.322674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5516 23:07:18.323159 ==
5517 23:07:18.325778 RX Vref Scan: 0
5518 23:07:18.326231
5519 23:07:18.329023 RX Vref 0 -> 0, step: 1
5520 23:07:18.329476
5521 23:07:18.329833 RX Delay -77 -> 252, step: 4
5522 23:07:18.337651 iDelay=199, Bit 0, Center 88 (-5 ~ 182) 188
5523 23:07:18.340310 iDelay=199, Bit 1, Center 94 (3 ~ 186) 184
5524 23:07:18.344047 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5525 23:07:18.347075 iDelay=199, Bit 3, Center 88 (-9 ~ 186) 196
5526 23:07:18.350718 iDelay=199, Bit 4, Center 90 (-5 ~ 186) 192
5527 23:07:18.357291 iDelay=199, Bit 5, Center 80 (-13 ~ 174) 188
5528 23:07:18.360344 iDelay=199, Bit 6, Center 102 (7 ~ 198) 192
5529 23:07:18.364013 iDelay=199, Bit 7, Center 102 (7 ~ 198) 192
5530 23:07:18.366917 iDelay=199, Bit 8, Center 76 (-13 ~ 166) 180
5531 23:07:18.370282 iDelay=199, Bit 9, Center 66 (-21 ~ 154) 176
5532 23:07:18.373642 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5533 23:07:18.380328 iDelay=199, Bit 11, Center 76 (-13 ~ 166) 180
5534 23:07:18.383406 iDelay=199, Bit 12, Center 90 (-1 ~ 182) 184
5535 23:07:18.387077 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5536 23:07:18.390521 iDelay=199, Bit 14, Center 94 (3 ~ 186) 184
5537 23:07:18.393844 iDelay=199, Bit 15, Center 92 (3 ~ 182) 180
5538 23:07:18.394302 ==
5539 23:07:18.396722 Dram Type= 6, Freq= 0, CH_0, rank 1
5540 23:07:18.403735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5541 23:07:18.404196 ==
5542 23:07:18.404600 DQS Delay:
5543 23:07:18.406704 DQS0 = 0, DQS1 = 0
5544 23:07:18.407157 DQM Delay:
5545 23:07:18.410080 DQM0 = 91, DQM1 = 83
5546 23:07:18.410535 DQ Delay:
5547 23:07:18.413577 DQ0 =88, DQ1 =94, DQ2 =88, DQ3 =88
5548 23:07:18.416714 DQ4 =90, DQ5 =80, DQ6 =102, DQ7 =102
5549 23:07:18.420013 DQ8 =76, DQ9 =66, DQ10 =86, DQ11 =76
5550 23:07:18.423669 DQ12 =90, DQ13 =90, DQ14 =94, DQ15 =92
5551 23:07:18.424122
5552 23:07:18.424512
5553 23:07:18.430138 [DQSOSCAuto] RK1, (LSB)MR18= 0x3213, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 406 ps
5554 23:07:18.433254 CH0 RK1: MR19=505, MR18=3213
5555 23:07:18.439957 CH0_RK1: MR19=0x505, MR18=0x3213, DQSOSC=406, MR23=63, INC=65, DEC=43
5556 23:07:18.443448 [RxdqsGatingPostProcess] freq 933
5557 23:07:18.449799 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5558 23:07:18.450258 best DQS0 dly(2T, 0.5T) = (0, 10)
5559 23:07:18.453653 best DQS1 dly(2T, 0.5T) = (0, 11)
5560 23:07:18.456757 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5561 23:07:18.459717 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5562 23:07:18.463242 best DQS0 dly(2T, 0.5T) = (0, 10)
5563 23:07:18.466621 best DQS1 dly(2T, 0.5T) = (0, 10)
5564 23:07:18.469892 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5565 23:07:18.472778 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5566 23:07:18.476340 Pre-setting of DQS Precalculation
5567 23:07:18.482968 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5568 23:07:18.483423 ==
5569 23:07:18.486592 Dram Type= 6, Freq= 0, CH_1, rank 0
5570 23:07:18.489408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5571 23:07:18.489918 ==
5572 23:07:18.496236 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5573 23:07:18.499631 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5574 23:07:18.503559 [CA 0] Center 37 (7~67) winsize 61
5575 23:07:18.507180 [CA 1] Center 37 (7~68) winsize 62
5576 23:07:18.510418 [CA 2] Center 34 (5~64) winsize 60
5577 23:07:18.513551 [CA 3] Center 34 (4~64) winsize 61
5578 23:07:18.516767 [CA 4] Center 34 (5~64) winsize 60
5579 23:07:18.519702 [CA 5] Center 34 (4~64) winsize 61
5580 23:07:18.520115
5581 23:07:18.523326 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5582 23:07:18.523740
5583 23:07:18.526926 [CATrainingPosCal] consider 1 rank data
5584 23:07:18.529767 u2DelayCellTimex100 = 270/100 ps
5585 23:07:18.533278 CA0 delay=37 (7~67),Diff = 3 PI (18 cell)
5586 23:07:18.536520 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5587 23:07:18.543456 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5588 23:07:18.546533 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
5589 23:07:18.549715 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5590 23:07:18.553243 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5591 23:07:18.553778
5592 23:07:18.556747 CA PerBit enable=1, Macro0, CA PI delay=34
5593 23:07:18.557312
5594 23:07:18.559804 [CBTSetCACLKResult] CA Dly = 34
5595 23:07:18.560478 CS Dly: 6 (0~37)
5596 23:07:18.563017 ==
5597 23:07:18.566162 Dram Type= 6, Freq= 0, CH_1, rank 1
5598 23:07:18.569612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5599 23:07:18.570224 ==
5600 23:07:18.573035 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5601 23:07:18.579825 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5602 23:07:18.583562 [CA 0] Center 38 (8~68) winsize 61
5603 23:07:18.586530 [CA 1] Center 37 (7~68) winsize 62
5604 23:07:18.590253 [CA 2] Center 35 (5~65) winsize 61
5605 23:07:18.592949 [CA 3] Center 34 (4~65) winsize 62
5606 23:07:18.596508 [CA 4] Center 35 (5~65) winsize 61
5607 23:07:18.599966 [CA 5] Center 34 (4~64) winsize 61
5608 23:07:18.600482
5609 23:07:18.603107 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5610 23:07:18.603526
5611 23:07:18.606594 [CATrainingPosCal] consider 2 rank data
5612 23:07:18.609550 u2DelayCellTimex100 = 270/100 ps
5613 23:07:18.612421 CA0 delay=37 (8~67),Diff = 3 PI (18 cell)
5614 23:07:18.619719 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5615 23:07:18.622370 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5616 23:07:18.626332 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
5617 23:07:18.629031 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5618 23:07:18.632525 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5619 23:07:18.632615
5620 23:07:18.635650 CA PerBit enable=1, Macro0, CA PI delay=34
5621 23:07:18.635759
5622 23:07:18.639006 [CBTSetCACLKResult] CA Dly = 34
5623 23:07:18.642781 CS Dly: 7 (0~39)
5624 23:07:18.642865
5625 23:07:18.645921 ----->DramcWriteLeveling(PI) begin...
5626 23:07:18.645998 ==
5627 23:07:18.649023 Dram Type= 6, Freq= 0, CH_1, rank 0
5628 23:07:18.652163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5629 23:07:18.652279 ==
5630 23:07:18.656009 Write leveling (Byte 0): 26 => 26
5631 23:07:18.659024 Write leveling (Byte 1): 28 => 28
5632 23:07:18.662200 DramcWriteLeveling(PI) end<-----
5633 23:07:18.662275
5634 23:07:18.662372 ==
5635 23:07:18.665781 Dram Type= 6, Freq= 0, CH_1, rank 0
5636 23:07:18.668934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5637 23:07:18.669034 ==
5638 23:07:18.672362 [Gating] SW mode calibration
5639 23:07:18.679171 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5640 23:07:18.685856 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5641 23:07:18.689185 0 14 0 | B1->B0 | 3131 3231 | 1 1 | (1 1) (1 1)
5642 23:07:18.692129 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5643 23:07:18.699169 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5644 23:07:18.702377 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5645 23:07:18.705504 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5646 23:07:18.712224 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5647 23:07:18.715207 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5648 23:07:18.718629 0 14 28 | B1->B0 | 3030 3030 | 0 0 | (1 0) (0 1)
5649 23:07:18.725473 0 15 0 | B1->B0 | 2b2b 2929 | 0 0 | (0 0) (0 0)
5650 23:07:18.728620 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5651 23:07:18.731733 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5652 23:07:18.738526 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5653 23:07:18.742146 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5654 23:07:18.745307 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5655 23:07:18.752131 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5656 23:07:18.755391 0 15 28 | B1->B0 | 2b2b 3434 | 0 0 | (0 0) (0 0)
5657 23:07:18.758172 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5658 23:07:18.765264 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5659 23:07:18.768475 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5660 23:07:18.771574 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5661 23:07:18.778035 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5662 23:07:18.781608 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5663 23:07:18.784900 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5664 23:07:18.788294 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5665 23:07:18.794617 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5666 23:07:18.798227 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5667 23:07:18.801433 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5668 23:07:18.808036 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5669 23:07:18.811433 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5670 23:07:18.814660 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5671 23:07:18.821540 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5672 23:07:18.824591 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5673 23:07:18.827643 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5674 23:07:18.835128 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5675 23:07:18.838181 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5676 23:07:18.841967 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5677 23:07:18.848652 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5678 23:07:18.851744 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5679 23:07:18.854947 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5680 23:07:18.861858 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5681 23:07:18.865071 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5682 23:07:18.868192 Total UI for P1: 0, mck2ui 16
5683 23:07:18.871494 best dqsien dly found for B0: ( 1, 2, 30)
5684 23:07:18.874910 Total UI for P1: 0, mck2ui 16
5685 23:07:18.878411 best dqsien dly found for B1: ( 1, 2, 28)
5686 23:07:18.881513 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5687 23:07:18.884751 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5688 23:07:18.885205
5689 23:07:18.887974 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5690 23:07:18.891087 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5691 23:07:18.894588 [Gating] SW calibration Done
5692 23:07:18.895202 ==
5693 23:07:18.897720 Dram Type= 6, Freq= 0, CH_1, rank 0
5694 23:07:18.904456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5695 23:07:18.904883 ==
5696 23:07:18.905285 RX Vref Scan: 0
5697 23:07:18.905594
5698 23:07:18.907744 RX Vref 0 -> 0, step: 1
5699 23:07:18.908151
5700 23:07:18.911265 RX Delay -80 -> 252, step: 8
5701 23:07:18.914170 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5702 23:07:18.917923 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5703 23:07:18.920720 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5704 23:07:18.924353 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5705 23:07:18.930664 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5706 23:07:18.934176 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5707 23:07:18.937253 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5708 23:07:18.941037 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5709 23:07:18.944140 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5710 23:07:18.950425 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5711 23:07:18.954157 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5712 23:07:18.956991 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5713 23:07:18.960608 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5714 23:07:18.963938 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5715 23:07:18.970742 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5716 23:07:18.973400 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5717 23:07:18.973845 ==
5718 23:07:18.976884 Dram Type= 6, Freq= 0, CH_1, rank 0
5719 23:07:18.980591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5720 23:07:18.981028 ==
5721 23:07:18.983416 DQS Delay:
5722 23:07:18.983828 DQS0 = 0, DQS1 = 0
5723 23:07:18.984150 DQM Delay:
5724 23:07:18.986703 DQM0 = 94, DQM1 = 86
5725 23:07:18.987108 DQ Delay:
5726 23:07:18.990107 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5727 23:07:18.993813 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5728 23:07:18.997198 DQ8 =75, DQ9 =79, DQ10 =87, DQ11 =83
5729 23:07:19.000237 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5730 23:07:19.000729
5731 23:07:19.001061
5732 23:07:19.001369 ==
5733 23:07:19.003509 Dram Type= 6, Freq= 0, CH_1, rank 0
5734 23:07:19.010385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5735 23:07:19.010805 ==
5736 23:07:19.011129
5737 23:07:19.011433
5738 23:07:19.011723 TX Vref Scan disable
5739 23:07:19.013650 == TX Byte 0 ==
5740 23:07:19.016984 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5741 23:07:19.023567 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5742 23:07:19.023985 == TX Byte 1 ==
5743 23:07:19.026815 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5744 23:07:19.033160 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5745 23:07:19.033576 ==
5746 23:07:19.036750 Dram Type= 6, Freq= 0, CH_1, rank 0
5747 23:07:19.039899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5748 23:07:19.040375 ==
5749 23:07:19.040715
5750 23:07:19.041019
5751 23:07:19.043347 TX Vref Scan disable
5752 23:07:19.043756 == TX Byte 0 ==
5753 23:07:19.049675 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5754 23:07:19.053513 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5755 23:07:19.053979 == TX Byte 1 ==
5756 23:07:19.059961 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5757 23:07:19.063076 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5758 23:07:19.063525
5759 23:07:19.063981 [DATLAT]
5760 23:07:19.066558 Freq=933, CH1 RK0
5761 23:07:19.066966
5762 23:07:19.067388 DATLAT Default: 0xd
5763 23:07:19.069615 0, 0xFFFF, sum = 0
5764 23:07:19.070016 1, 0xFFFF, sum = 0
5765 23:07:19.072884 2, 0xFFFF, sum = 0
5766 23:07:19.076152 3, 0xFFFF, sum = 0
5767 23:07:19.076687 4, 0xFFFF, sum = 0
5768 23:07:19.079729 5, 0xFFFF, sum = 0
5769 23:07:19.080185 6, 0xFFFF, sum = 0
5770 23:07:19.082847 7, 0xFFFF, sum = 0
5771 23:07:19.083299 8, 0xFFFF, sum = 0
5772 23:07:19.086329 9, 0xFFFF, sum = 0
5773 23:07:19.086791 10, 0x0, sum = 1
5774 23:07:19.089547 11, 0x0, sum = 2
5775 23:07:19.090011 12, 0x0, sum = 3
5776 23:07:19.090462 13, 0x0, sum = 4
5777 23:07:19.092861 best_step = 11
5778 23:07:19.093434
5779 23:07:19.093885 ==
5780 23:07:19.096079 Dram Type= 6, Freq= 0, CH_1, rank 0
5781 23:07:19.099798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5782 23:07:19.100376 ==
5783 23:07:19.103073 RX Vref Scan: 1
5784 23:07:19.103786
5785 23:07:19.106255 RX Vref 0 -> 0, step: 1
5786 23:07:19.106679
5787 23:07:19.107151 RX Delay -69 -> 252, step: 4
5788 23:07:19.107510
5789 23:07:19.109618 Set Vref, RX VrefLevel [Byte0]: 54
5790 23:07:19.112623 [Byte1]: 50
5791 23:07:19.117297
5792 23:07:19.118022 Final RX Vref Byte 0 = 54 to rank0
5793 23:07:19.120786 Final RX Vref Byte 1 = 50 to rank0
5794 23:07:19.123839 Final RX Vref Byte 0 = 54 to rank1
5795 23:07:19.127070 Final RX Vref Byte 1 = 50 to rank1==
5796 23:07:19.130787 Dram Type= 6, Freq= 0, CH_1, rank 0
5797 23:07:19.137528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5798 23:07:19.138087 ==
5799 23:07:19.138570 DQS Delay:
5800 23:07:19.140751 DQS0 = 0, DQS1 = 0
5801 23:07:19.141208 DQM Delay:
5802 23:07:19.141699 DQM0 = 97, DQM1 = 89
5803 23:07:19.144353 DQ Delay:
5804 23:07:19.147380 DQ0 =102, DQ1 =92, DQ2 =86, DQ3 =94
5805 23:07:19.150483 DQ4 =94, DQ5 =106, DQ6 =108, DQ7 =94
5806 23:07:19.153915 DQ8 =78, DQ9 =82, DQ10 =86, DQ11 =84
5807 23:07:19.157005 DQ12 =98, DQ13 =94, DQ14 =98, DQ15 =94
5808 23:07:19.157576
5809 23:07:19.158046
5810 23:07:19.163791 [DQSOSCAuto] RK0, (LSB)MR18= 0xff08, (MSB)MR19= 0x405, tDQSOscB0 = 419 ps tDQSOscB1 = 422 ps
5811 23:07:19.167228 CH1 RK0: MR19=405, MR18=FF08
5812 23:07:19.174328 CH1_RK0: MR19=0x405, MR18=0xFF08, DQSOSC=419, MR23=63, INC=61, DEC=41
5813 23:07:19.175041
5814 23:07:19.176934 ----->DramcWriteLeveling(PI) begin...
5815 23:07:19.177457 ==
5816 23:07:19.180738 Dram Type= 6, Freq= 0, CH_1, rank 1
5817 23:07:19.183838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5818 23:07:19.184420 ==
5819 23:07:19.186821 Write leveling (Byte 0): 25 => 25
5820 23:07:19.190217 Write leveling (Byte 1): 29 => 29
5821 23:07:19.193757 DramcWriteLeveling(PI) end<-----
5822 23:07:19.194363
5823 23:07:19.194887 ==
5824 23:07:19.196864 Dram Type= 6, Freq= 0, CH_1, rank 1
5825 23:07:19.200533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5826 23:07:19.203496 ==
5827 23:07:19.203918 [Gating] SW mode calibration
5828 23:07:19.210034 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5829 23:07:19.217076 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5830 23:07:19.220352 0 14 0 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
5831 23:07:19.226860 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5832 23:07:19.229995 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5833 23:07:19.233192 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5834 23:07:19.239688 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5835 23:07:19.243021 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5836 23:07:19.246813 0 14 24 | B1->B0 | 3333 2f2f | 1 0 | (1 0) (0 0)
5837 23:07:19.252811 0 14 28 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5838 23:07:19.256124 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5839 23:07:19.259314 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5840 23:07:19.266191 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5841 23:07:19.269413 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5842 23:07:19.272824 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5843 23:07:19.279413 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5844 23:07:19.282330 0 15 24 | B1->B0 | 2525 3535 | 0 1 | (0 0) (0 0)
5845 23:07:19.285571 0 15 28 | B1->B0 | 3636 4545 | 0 0 | (0 0) (0 0)
5846 23:07:19.292068 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5847 23:07:19.295729 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5848 23:07:19.299002 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5849 23:07:19.305260 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5850 23:07:19.308840 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5851 23:07:19.312173 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5852 23:07:19.318949 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5853 23:07:19.322084 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5854 23:07:19.325307 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5855 23:07:19.331670 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5856 23:07:19.335131 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5857 23:07:19.338670 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5858 23:07:19.345539 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5859 23:07:19.348342 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5860 23:07:19.351673 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5861 23:07:19.358084 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5862 23:07:19.361809 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5863 23:07:19.364691 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5864 23:07:19.371823 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5865 23:07:19.374835 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5866 23:07:19.378147 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5867 23:07:19.384662 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5868 23:07:19.388129 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5869 23:07:19.391163 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5870 23:07:19.398276 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5871 23:07:19.398359 Total UI for P1: 0, mck2ui 16
5872 23:07:19.404416 best dqsien dly found for B0: ( 1, 2, 28)
5873 23:07:19.404498 Total UI for P1: 0, mck2ui 16
5874 23:07:19.408186 best dqsien dly found for B1: ( 1, 2, 28)
5875 23:07:19.414524 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5876 23:07:19.418118 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5877 23:07:19.418188
5878 23:07:19.421223 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5879 23:07:19.424178 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5880 23:07:19.427931 [Gating] SW calibration Done
5881 23:07:19.428010 ==
5882 23:07:19.431308 Dram Type= 6, Freq= 0, CH_1, rank 1
5883 23:07:19.434319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5884 23:07:19.434415 ==
5885 23:07:19.437746 RX Vref Scan: 0
5886 23:07:19.437813
5887 23:07:19.437879 RX Vref 0 -> 0, step: 1
5888 23:07:19.437965
5889 23:07:19.440866 RX Delay -80 -> 252, step: 8
5890 23:07:19.444214 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5891 23:07:19.450503 iDelay=208, Bit 1, Center 87 (-16 ~ 191) 208
5892 23:07:19.454112 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5893 23:07:19.457310 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5894 23:07:19.460559 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5895 23:07:19.463710 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5896 23:07:19.470424 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5897 23:07:19.473962 iDelay=208, Bit 7, Center 87 (-16 ~ 191) 208
5898 23:07:19.477018 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5899 23:07:19.480297 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5900 23:07:19.484241 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5901 23:07:19.490440 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5902 23:07:19.493673 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5903 23:07:19.497060 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5904 23:07:19.500403 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5905 23:07:19.503494 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5906 23:07:19.503564 ==
5907 23:07:19.506881 Dram Type= 6, Freq= 0, CH_1, rank 1
5908 23:07:19.513499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5909 23:07:19.513590 ==
5910 23:07:19.513674 DQS Delay:
5911 23:07:19.516704 DQS0 = 0, DQS1 = 0
5912 23:07:19.516795 DQM Delay:
5913 23:07:19.516880 DQM0 = 92, DQM1 = 87
5914 23:07:19.520130 DQ Delay:
5915 23:07:19.523995 DQ0 =99, DQ1 =87, DQ2 =83, DQ3 =87
5916 23:07:19.526698 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =87
5917 23:07:19.530278 DQ8 =75, DQ9 =75, DQ10 =91, DQ11 =83
5918 23:07:19.533421 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =95
5919 23:07:19.533504
5920 23:07:19.533586
5921 23:07:19.533665 ==
5922 23:07:19.536820 Dram Type= 6, Freq= 0, CH_1, rank 1
5923 23:07:19.539948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5924 23:07:19.540031 ==
5925 23:07:19.540130
5926 23:07:19.540264
5927 23:07:19.543121 TX Vref Scan disable
5928 23:07:19.546530 == TX Byte 0 ==
5929 23:07:19.549898 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5930 23:07:19.553065 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5931 23:07:19.556443 == TX Byte 1 ==
5932 23:07:19.559796 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5933 23:07:19.563273 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5934 23:07:19.563355 ==
5935 23:07:19.566280 Dram Type= 6, Freq= 0, CH_1, rank 1
5936 23:07:19.569494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5937 23:07:19.573124 ==
5938 23:07:19.573227
5939 23:07:19.573338
5940 23:07:19.573417 TX Vref Scan disable
5941 23:07:19.576568 == TX Byte 0 ==
5942 23:07:19.579902 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5943 23:07:19.586606 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5944 23:07:19.586693 == TX Byte 1 ==
5945 23:07:19.589832 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5946 23:07:19.596241 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5947 23:07:19.596324
5948 23:07:19.596408 [DATLAT]
5949 23:07:19.596487 Freq=933, CH1 RK1
5950 23:07:19.596565
5951 23:07:19.599575 DATLAT Default: 0xb
5952 23:07:19.599658 0, 0xFFFF, sum = 0
5953 23:07:19.603146 1, 0xFFFF, sum = 0
5954 23:07:19.606661 2, 0xFFFF, sum = 0
5955 23:07:19.606745 3, 0xFFFF, sum = 0
5956 23:07:19.609789 4, 0xFFFF, sum = 0
5957 23:07:19.609874 5, 0xFFFF, sum = 0
5958 23:07:19.612950 6, 0xFFFF, sum = 0
5959 23:07:19.613033 7, 0xFFFF, sum = 0
5960 23:07:19.616393 8, 0xFFFF, sum = 0
5961 23:07:19.616477 9, 0xFFFF, sum = 0
5962 23:07:19.619563 10, 0x0, sum = 1
5963 23:07:19.619646 11, 0x0, sum = 2
5964 23:07:19.622896 12, 0x0, sum = 3
5965 23:07:19.622980 13, 0x0, sum = 4
5966 23:07:19.623065 best_step = 11
5967 23:07:19.626292
5968 23:07:19.626374 ==
5969 23:07:19.629648 Dram Type= 6, Freq= 0, CH_1, rank 1
5970 23:07:19.632712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5971 23:07:19.632794 ==
5972 23:07:19.632878 RX Vref Scan: 0
5973 23:07:19.632957
5974 23:07:19.636407 RX Vref 0 -> 0, step: 1
5975 23:07:19.636489
5976 23:07:19.639419 RX Delay -69 -> 252, step: 4
5977 23:07:19.646159 iDelay=203, Bit 0, Center 96 (-1 ~ 194) 196
5978 23:07:19.649279 iDelay=203, Bit 1, Center 86 (-9 ~ 182) 192
5979 23:07:19.652171 iDelay=203, Bit 2, Center 82 (-13 ~ 178) 192
5980 23:07:19.655898 iDelay=203, Bit 3, Center 88 (-9 ~ 186) 196
5981 23:07:19.659212 iDelay=203, Bit 4, Center 90 (-5 ~ 186) 192
5982 23:07:19.665584 iDelay=203, Bit 5, Center 102 (7 ~ 198) 192
5983 23:07:19.668952 iDelay=203, Bit 6, Center 104 (7 ~ 202) 196
5984 23:07:19.672070 iDelay=203, Bit 7, Center 88 (-9 ~ 186) 196
5985 23:07:19.675922 iDelay=203, Bit 8, Center 76 (-17 ~ 170) 188
5986 23:07:19.679154 iDelay=203, Bit 9, Center 82 (-13 ~ 178) 192
5987 23:07:19.685406 iDelay=203, Bit 10, Center 94 (3 ~ 186) 184
5988 23:07:19.688445 iDelay=203, Bit 11, Center 82 (-13 ~ 178) 192
5989 23:07:19.691933 iDelay=203, Bit 12, Center 98 (7 ~ 190) 184
5990 23:07:19.695229 iDelay=203, Bit 13, Center 98 (7 ~ 190) 184
5991 23:07:19.698489 iDelay=203, Bit 14, Center 98 (11 ~ 186) 176
5992 23:07:19.701692 iDelay=203, Bit 15, Center 98 (7 ~ 190) 184
5993 23:07:19.704956 ==
5994 23:07:19.705031 Dram Type= 6, Freq= 0, CH_1, rank 1
5995 23:07:19.711611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5996 23:07:19.711683 ==
5997 23:07:19.711748 DQS Delay:
5998 23:07:19.715269 DQS0 = 0, DQS1 = 0
5999 23:07:19.715374 DQM Delay:
6000 23:07:19.718577 DQM0 = 92, DQM1 = 90
6001 23:07:19.718675 DQ Delay:
6002 23:07:19.721995 DQ0 =96, DQ1 =86, DQ2 =82, DQ3 =88
6003 23:07:19.725563 DQ4 =90, DQ5 =102, DQ6 =104, DQ7 =88
6004 23:07:19.728214 DQ8 =76, DQ9 =82, DQ10 =94, DQ11 =82
6005 23:07:19.731752 DQ12 =98, DQ13 =98, DQ14 =98, DQ15 =98
6006 23:07:19.731855
6007 23:07:19.731944
6008 23:07:19.738306 [DQSOSCAuto] RK1, (LSB)MR18= 0xf23, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 417 ps
6009 23:07:19.741797 CH1 RK1: MR19=505, MR18=F23
6010 23:07:19.748440 CH1_RK1: MR19=0x505, MR18=0xF23, DQSOSC=410, MR23=63, INC=64, DEC=42
6011 23:07:19.751881 [RxdqsGatingPostProcess] freq 933
6012 23:07:19.758071 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6013 23:07:19.758169 best DQS0 dly(2T, 0.5T) = (0, 10)
6014 23:07:19.761327 best DQS1 dly(2T, 0.5T) = (0, 10)
6015 23:07:19.764796 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6016 23:07:19.767743 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6017 23:07:19.771590 best DQS0 dly(2T, 0.5T) = (0, 10)
6018 23:07:19.774918 best DQS1 dly(2T, 0.5T) = (0, 10)
6019 23:07:19.777863 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6020 23:07:19.781007 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6021 23:07:19.784749 Pre-setting of DQS Precalculation
6022 23:07:19.787949 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6023 23:07:19.797870 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6024 23:07:19.804276 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6025 23:07:19.804356
6026 23:07:19.804421
6027 23:07:19.807995 [Calibration Summary] 1866 Mbps
6028 23:07:19.808080 CH 0, Rank 0
6029 23:07:19.811251 SW Impedance : PASS
6030 23:07:19.811318 DUTY Scan : NO K
6031 23:07:19.814444 ZQ Calibration : PASS
6032 23:07:19.817648 Jitter Meter : NO K
6033 23:07:19.817717 CBT Training : PASS
6034 23:07:19.821114 Write leveling : PASS
6035 23:07:19.824531 RX DQS gating : PASS
6036 23:07:19.824626 RX DQ/DQS(RDDQC) : PASS
6037 23:07:19.827761 TX DQ/DQS : PASS
6038 23:07:19.830841 RX DATLAT : PASS
6039 23:07:19.830935 RX DQ/DQS(Engine): PASS
6040 23:07:19.834503 TX OE : NO K
6041 23:07:19.834571 All Pass.
6042 23:07:19.834631
6043 23:07:19.837485 CH 0, Rank 1
6044 23:07:19.837552 SW Impedance : PASS
6045 23:07:19.840855 DUTY Scan : NO K
6046 23:07:19.844530 ZQ Calibration : PASS
6047 23:07:19.844612 Jitter Meter : NO K
6048 23:07:19.847267 CBT Training : PASS
6049 23:07:19.850680 Write leveling : PASS
6050 23:07:19.850779 RX DQS gating : PASS
6051 23:07:19.853882 RX DQ/DQS(RDDQC) : PASS
6052 23:07:19.857561 TX DQ/DQS : PASS
6053 23:07:19.857628 RX DATLAT : PASS
6054 23:07:19.860918 RX DQ/DQS(Engine): PASS
6055 23:07:19.864010 TX OE : NO K
6056 23:07:19.864078 All Pass.
6057 23:07:19.864143
6058 23:07:19.864262 CH 1, Rank 0
6059 23:07:19.867325 SW Impedance : PASS
6060 23:07:19.870535 DUTY Scan : NO K
6061 23:07:19.870623 ZQ Calibration : PASS
6062 23:07:19.874390 Jitter Meter : NO K
6063 23:07:19.874472 CBT Training : PASS
6064 23:07:19.877423 Write leveling : PASS
6065 23:07:19.880954 RX DQS gating : PASS
6066 23:07:19.881036 RX DQ/DQS(RDDQC) : PASS
6067 23:07:19.883934 TX DQ/DQS : PASS
6068 23:07:19.887484 RX DATLAT : PASS
6069 23:07:19.887566 RX DQ/DQS(Engine): PASS
6070 23:07:19.890998 TX OE : NO K
6071 23:07:19.891081 All Pass.
6072 23:07:19.891164
6073 23:07:19.894233 CH 1, Rank 1
6074 23:07:19.894315 SW Impedance : PASS
6075 23:07:19.897095 DUTY Scan : NO K
6076 23:07:19.900498 ZQ Calibration : PASS
6077 23:07:19.900581 Jitter Meter : NO K
6078 23:07:19.903904 CBT Training : PASS
6079 23:07:19.907336 Write leveling : PASS
6080 23:07:19.907419 RX DQS gating : PASS
6081 23:07:19.910764 RX DQ/DQS(RDDQC) : PASS
6082 23:07:19.914123 TX DQ/DQS : PASS
6083 23:07:19.914206 RX DATLAT : PASS
6084 23:07:19.917188 RX DQ/DQS(Engine): PASS
6085 23:07:19.917271 TX OE : NO K
6086 23:07:19.920816 All Pass.
6087 23:07:19.920898
6088 23:07:19.920982 DramC Write-DBI off
6089 23:07:19.924096 PER_BANK_REFRESH: Hybrid Mode
6090 23:07:19.927201 TX_TRACKING: ON
6091 23:07:19.933978 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6092 23:07:19.937108 [FAST_K] Save calibration result to emmc
6093 23:07:19.943965 dramc_set_vcore_voltage set vcore to 650000
6094 23:07:19.944048 Read voltage for 400, 6
6095 23:07:19.944147 Vio18 = 0
6096 23:07:19.946937 Vcore = 650000
6097 23:07:19.947019 Vdram = 0
6098 23:07:19.947102 Vddq = 0
6099 23:07:19.950589 Vmddr = 0
6100 23:07:19.954017 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6101 23:07:19.960178 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6102 23:07:19.963754 MEM_TYPE=3, freq_sel=20
6103 23:07:19.963837 sv_algorithm_assistance_LP4_800
6104 23:07:19.970424 ============ PULL DRAM RESETB DOWN ============
6105 23:07:19.973481 ========== PULL DRAM RESETB DOWN end =========
6106 23:07:19.976728 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6107 23:07:19.980565 ===================================
6108 23:07:19.983466 LPDDR4 DRAM CONFIGURATION
6109 23:07:19.986920 ===================================
6110 23:07:19.990056 EX_ROW_EN[0] = 0x0
6111 23:07:19.990139 EX_ROW_EN[1] = 0x0
6112 23:07:19.993377 LP4Y_EN = 0x0
6113 23:07:19.993460 WORK_FSP = 0x0
6114 23:07:19.996590 WL = 0x2
6115 23:07:19.996672 RL = 0x2
6116 23:07:20.000095 BL = 0x2
6117 23:07:20.000177 RPST = 0x0
6118 23:07:20.003152 RD_PRE = 0x0
6119 23:07:20.003234 WR_PRE = 0x1
6120 23:07:20.006771 WR_PST = 0x0
6121 23:07:20.006853 DBI_WR = 0x0
6122 23:07:20.009965 DBI_RD = 0x0
6123 23:07:20.010048 OTF = 0x1
6124 23:07:20.013231 ===================================
6125 23:07:20.016970 ===================================
6126 23:07:20.019888 ANA top config
6127 23:07:20.023278 ===================================
6128 23:07:20.026760 DLL_ASYNC_EN = 0
6129 23:07:20.026842 ALL_SLAVE_EN = 1
6130 23:07:20.030057 NEW_RANK_MODE = 1
6131 23:07:20.033327 DLL_IDLE_MODE = 1
6132 23:07:20.036678 LP45_APHY_COMB_EN = 1
6133 23:07:20.036761 TX_ODT_DIS = 1
6134 23:07:20.039755 NEW_8X_MODE = 1
6135 23:07:20.043172 ===================================
6136 23:07:20.046906 ===================================
6137 23:07:20.049722 data_rate = 800
6138 23:07:20.053397 CKR = 1
6139 23:07:20.056453 DQ_P2S_RATIO = 4
6140 23:07:20.059990 ===================================
6141 23:07:20.063172 CA_P2S_RATIO = 4
6142 23:07:20.063255 DQ_CA_OPEN = 0
6143 23:07:20.066342 DQ_SEMI_OPEN = 1
6144 23:07:20.069760 CA_SEMI_OPEN = 1
6145 23:07:20.073395 CA_FULL_RATE = 0
6146 23:07:20.076578 DQ_CKDIV4_EN = 0
6147 23:07:20.079904 CA_CKDIV4_EN = 1
6148 23:07:20.079986 CA_PREDIV_EN = 0
6149 23:07:20.083195 PH8_DLY = 0
6150 23:07:20.086301 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6151 23:07:20.089617 DQ_AAMCK_DIV = 0
6152 23:07:20.092662 CA_AAMCK_DIV = 0
6153 23:07:20.096245 CA_ADMCK_DIV = 4
6154 23:07:20.096328 DQ_TRACK_CA_EN = 0
6155 23:07:20.099408 CA_PICK = 800
6156 23:07:20.102718 CA_MCKIO = 400
6157 23:07:20.106362 MCKIO_SEMI = 400
6158 23:07:20.109522 PLL_FREQ = 3016
6159 23:07:20.112849 DQ_UI_PI_RATIO = 32
6160 23:07:20.116235 CA_UI_PI_RATIO = 32
6161 23:07:20.119338 ===================================
6162 23:07:20.122914 ===================================
6163 23:07:20.122997 memory_type:LPDDR4
6164 23:07:20.125941 GP_NUM : 10
6165 23:07:20.129503 SRAM_EN : 1
6166 23:07:20.129585 MD32_EN : 0
6167 23:07:20.132820 ===================================
6168 23:07:20.135938 [ANA_INIT] >>>>>>>>>>>>>>
6169 23:07:20.139691 <<<<<< [CONFIGURE PHASE]: ANA_TX
6170 23:07:20.142694 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6171 23:07:20.146005 ===================================
6172 23:07:20.149231 data_rate = 800,PCW = 0X7400
6173 23:07:20.152945 ===================================
6174 23:07:20.156131 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6175 23:07:20.159428 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6176 23:07:20.172330 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6177 23:07:20.176076 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6178 23:07:20.179260 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6179 23:07:20.182245 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6180 23:07:20.185919 [ANA_INIT] flow start
6181 23:07:20.188804 [ANA_INIT] PLL >>>>>>>>
6182 23:07:20.188917 [ANA_INIT] PLL <<<<<<<<
6183 23:07:20.192288 [ANA_INIT] MIDPI >>>>>>>>
6184 23:07:20.195919 [ANA_INIT] MIDPI <<<<<<<<
6185 23:07:20.196038 [ANA_INIT] DLL >>>>>>>>
6186 23:07:20.198838 [ANA_INIT] flow end
6187 23:07:20.202622 ============ LP4 DIFF to SE enter ============
6188 23:07:20.205352 ============ LP4 DIFF to SE exit ============
6189 23:07:20.209074 [ANA_INIT] <<<<<<<<<<<<<
6190 23:07:20.212369 [Flow] Enable top DCM control >>>>>
6191 23:07:20.215394 [Flow] Enable top DCM control <<<<<
6192 23:07:20.218755 Enable DLL master slave shuffle
6193 23:07:20.225475 ==============================================================
6194 23:07:20.225570 Gating Mode config
6195 23:07:20.232030 ==============================================================
6196 23:07:20.235283 Config description:
6197 23:07:20.241949 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6198 23:07:20.248739 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6199 23:07:20.255276 SELPH_MODE 0: By rank 1: By Phase
6200 23:07:20.261764 ==============================================================
6201 23:07:20.261864 GAT_TRACK_EN = 0
6202 23:07:20.265432 RX_GATING_MODE = 2
6203 23:07:20.268558 RX_GATING_TRACK_MODE = 2
6204 23:07:20.272142 SELPH_MODE = 1
6205 23:07:20.274974 PICG_EARLY_EN = 1
6206 23:07:20.278341 VALID_LAT_VALUE = 1
6207 23:07:20.285289 ==============================================================
6208 23:07:20.288369 Enter into Gating configuration >>>>
6209 23:07:20.291653 Exit from Gating configuration <<<<
6210 23:07:20.294937 Enter into DVFS_PRE_config >>>>>
6211 23:07:20.305265 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6212 23:07:20.308510 Exit from DVFS_PRE_config <<<<<
6213 23:07:20.311919 Enter into PICG configuration >>>>
6214 23:07:20.314955 Exit from PICG configuration <<<<
6215 23:07:20.318337 [RX_INPUT] configuration >>>>>
6216 23:07:20.321376 [RX_INPUT] configuration <<<<<
6217 23:07:20.324789 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6218 23:07:20.331687 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6219 23:07:20.338112 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6220 23:07:20.341535 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6221 23:07:20.348143 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6222 23:07:20.354902 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6223 23:07:20.358319 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6224 23:07:20.361773 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6225 23:07:20.368312 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6226 23:07:20.371268 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6227 23:07:20.374909 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6228 23:07:20.381586 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6229 23:07:20.385032 ===================================
6230 23:07:20.385544 LPDDR4 DRAM CONFIGURATION
6231 23:07:20.388417 ===================================
6232 23:07:20.391401 EX_ROW_EN[0] = 0x0
6233 23:07:20.394918 EX_ROW_EN[1] = 0x0
6234 23:07:20.395553 LP4Y_EN = 0x0
6235 23:07:20.397914 WORK_FSP = 0x0
6236 23:07:20.398531 WL = 0x2
6237 23:07:20.401511 RL = 0x2
6238 23:07:20.402040 BL = 0x2
6239 23:07:20.404438 RPST = 0x0
6240 23:07:20.404990 RD_PRE = 0x0
6241 23:07:20.407950 WR_PRE = 0x1
6242 23:07:20.408551 WR_PST = 0x0
6243 23:07:20.411319 DBI_WR = 0x0
6244 23:07:20.411872 DBI_RD = 0x0
6245 23:07:20.414423 OTF = 0x1
6246 23:07:20.418065 ===================================
6247 23:07:20.421245 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6248 23:07:20.424316 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6249 23:07:20.431187 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6250 23:07:20.434273 ===================================
6251 23:07:20.434839 LPDDR4 DRAM CONFIGURATION
6252 23:07:20.437608 ===================================
6253 23:07:20.440818 EX_ROW_EN[0] = 0x10
6254 23:07:20.443989 EX_ROW_EN[1] = 0x0
6255 23:07:20.444540 LP4Y_EN = 0x0
6256 23:07:20.447553 WORK_FSP = 0x0
6257 23:07:20.448038 WL = 0x2
6258 23:07:20.450705 RL = 0x2
6259 23:07:20.451265 BL = 0x2
6260 23:07:20.453939 RPST = 0x0
6261 23:07:20.454542 RD_PRE = 0x0
6262 23:07:20.457250 WR_PRE = 0x1
6263 23:07:20.457810 WR_PST = 0x0
6264 23:07:20.460435 DBI_WR = 0x0
6265 23:07:20.461023 DBI_RD = 0x0
6266 23:07:20.464197 OTF = 0x1
6267 23:07:20.467551 ===================================
6268 23:07:20.473919 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6269 23:07:20.477172 nWR fixed to 30
6270 23:07:20.477585 [ModeRegInit_LP4] CH0 RK0
6271 23:07:20.480752 [ModeRegInit_LP4] CH0 RK1
6272 23:07:20.484095 [ModeRegInit_LP4] CH1 RK0
6273 23:07:20.487081 [ModeRegInit_LP4] CH1 RK1
6274 23:07:20.487491 match AC timing 19
6275 23:07:20.493613 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6276 23:07:20.496726 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6277 23:07:20.499928 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6278 23:07:20.506555 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6279 23:07:20.510093 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6280 23:07:20.510174 ==
6281 23:07:20.513198 Dram Type= 6, Freq= 0, CH_0, rank 0
6282 23:07:20.516962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6283 23:07:20.517043 ==
6284 23:07:20.523241 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6285 23:07:20.529617 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6286 23:07:20.533150 [CA 0] Center 36 (8~64) winsize 57
6287 23:07:20.536880 [CA 1] Center 36 (8~64) winsize 57
6288 23:07:20.536959 [CA 2] Center 36 (8~64) winsize 57
6289 23:07:20.539918 [CA 3] Center 36 (8~64) winsize 57
6290 23:07:20.543138 [CA 4] Center 36 (8~64) winsize 57
6291 23:07:20.546368 [CA 5] Center 36 (8~64) winsize 57
6292 23:07:20.546448
6293 23:07:20.549631 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6294 23:07:20.553119
6295 23:07:20.556424 [CATrainingPosCal] consider 1 rank data
6296 23:07:20.556536 u2DelayCellTimex100 = 270/100 ps
6297 23:07:20.563156 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6298 23:07:20.566560 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6299 23:07:20.569621 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6300 23:07:20.573001 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6301 23:07:20.576128 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6302 23:07:20.579665 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6303 23:07:20.579764
6304 23:07:20.582911 CA PerBit enable=1, Macro0, CA PI delay=36
6305 23:07:20.583004
6306 23:07:20.585912 [CBTSetCACLKResult] CA Dly = 36
6307 23:07:20.589229 CS Dly: 1 (0~32)
6308 23:07:20.589308 ==
6309 23:07:20.592779 Dram Type= 6, Freq= 0, CH_0, rank 1
6310 23:07:20.596025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6311 23:07:20.596120 ==
6312 23:07:20.602652 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6313 23:07:20.605869 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6314 23:07:20.608969 [CA 0] Center 36 (8~64) winsize 57
6315 23:07:20.612099 [CA 1] Center 36 (8~64) winsize 57
6316 23:07:20.615732 [CA 2] Center 36 (8~64) winsize 57
6317 23:07:20.618995 [CA 3] Center 36 (8~64) winsize 57
6318 23:07:20.622235 [CA 4] Center 36 (8~64) winsize 57
6319 23:07:20.625491 [CA 5] Center 36 (8~64) winsize 57
6320 23:07:20.625581
6321 23:07:20.628600 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6322 23:07:20.628695
6323 23:07:20.632198 [CATrainingPosCal] consider 2 rank data
6324 23:07:20.635195 u2DelayCellTimex100 = 270/100 ps
6325 23:07:20.638816 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6326 23:07:20.645385 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6327 23:07:20.648573 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6328 23:07:20.652218 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6329 23:07:20.655098 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6330 23:07:20.658598 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6331 23:07:20.658702
6332 23:07:20.662010 CA PerBit enable=1, Macro0, CA PI delay=36
6333 23:07:20.662116
6334 23:07:20.665304 [CBTSetCACLKResult] CA Dly = 36
6335 23:07:20.665402 CS Dly: 1 (0~32)
6336 23:07:20.668509
6337 23:07:20.671656 ----->DramcWriteLeveling(PI) begin...
6338 23:07:20.671760 ==
6339 23:07:20.675098 Dram Type= 6, Freq= 0, CH_0, rank 0
6340 23:07:20.678164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6341 23:07:20.678261 ==
6342 23:07:20.681676 Write leveling (Byte 0): 40 => 8
6343 23:07:20.684935 Write leveling (Byte 1): 40 => 8
6344 23:07:20.688421 DramcWriteLeveling(PI) end<-----
6345 23:07:20.688492
6346 23:07:20.688552 ==
6347 23:07:20.691765 Dram Type= 6, Freq= 0, CH_0, rank 0
6348 23:07:20.695035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6349 23:07:20.695135 ==
6350 23:07:20.698419 [Gating] SW mode calibration
6351 23:07:20.704970 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6352 23:07:20.711547 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6353 23:07:20.714944 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6354 23:07:20.717864 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6355 23:07:20.724951 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6356 23:07:20.727970 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6357 23:07:20.731234 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6358 23:07:20.737645 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6359 23:07:20.740973 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6360 23:07:20.744538 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6361 23:07:20.750802 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6362 23:07:20.750900 Total UI for P1: 0, mck2ui 16
6363 23:07:20.757465 best dqsien dly found for B0: ( 0, 14, 24)
6364 23:07:20.757571 Total UI for P1: 0, mck2ui 16
6365 23:07:20.764140 best dqsien dly found for B1: ( 0, 14, 24)
6366 23:07:20.767888 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6367 23:07:20.770783 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6368 23:07:20.770858
6369 23:07:20.773803 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6370 23:07:20.777333 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6371 23:07:20.780510 [Gating] SW calibration Done
6372 23:07:20.780582 ==
6373 23:07:20.783903 Dram Type= 6, Freq= 0, CH_0, rank 0
6374 23:07:20.787191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6375 23:07:20.787290 ==
6376 23:07:20.790606 RX Vref Scan: 0
6377 23:07:20.790704
6378 23:07:20.790792 RX Vref 0 -> 0, step: 1
6379 23:07:20.790876
6380 23:07:20.793866 RX Delay -410 -> 252, step: 16
6381 23:07:20.800750 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6382 23:07:20.804043 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6383 23:07:20.807369 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6384 23:07:20.810353 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6385 23:07:20.816836 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6386 23:07:20.819898 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6387 23:07:20.823661 iDelay=230, Bit 6, Center -35 (-282 ~ 213) 496
6388 23:07:20.826623 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6389 23:07:20.833503 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6390 23:07:20.836233 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6391 23:07:20.839663 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6392 23:07:20.846492 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6393 23:07:20.849971 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6394 23:07:20.853025 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6395 23:07:20.856370 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6396 23:07:20.862967 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6397 23:07:20.863042 ==
6398 23:07:20.866661 Dram Type= 6, Freq= 0, CH_0, rank 0
6399 23:07:20.869545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6400 23:07:20.869643 ==
6401 23:07:20.869738 DQS Delay:
6402 23:07:20.872948 DQS0 = 59, DQS1 = 59
6403 23:07:20.873042 DQM Delay:
6404 23:07:20.876438 DQM0 = 17, DQM1 = 10
6405 23:07:20.876507 DQ Delay:
6406 23:07:20.879604 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6407 23:07:20.882915 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =32
6408 23:07:20.886434 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6409 23:07:20.889514 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6410 23:07:20.889586
6411 23:07:20.889647
6412 23:07:20.889709 ==
6413 23:07:20.893124 Dram Type= 6, Freq= 0, CH_0, rank 0
6414 23:07:20.896603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6415 23:07:20.896698 ==
6416 23:07:20.896784
6417 23:07:20.899702
6418 23:07:20.899765 TX Vref Scan disable
6419 23:07:20.902913 == TX Byte 0 ==
6420 23:07:20.906404 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6421 23:07:20.909467 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6422 23:07:20.912727 == TX Byte 1 ==
6423 23:07:20.916231 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6424 23:07:20.919349 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6425 23:07:20.919442 ==
6426 23:07:20.922848 Dram Type= 6, Freq= 0, CH_0, rank 0
6427 23:07:20.926378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6428 23:07:20.926475 ==
6429 23:07:20.929711
6430 23:07:20.929778
6431 23:07:20.929836 TX Vref Scan disable
6432 23:07:20.932440 == TX Byte 0 ==
6433 23:07:20.936012 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6434 23:07:20.939015 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6435 23:07:20.942480 == TX Byte 1 ==
6436 23:07:20.945746 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6437 23:07:20.949171 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6438 23:07:20.949250
6439 23:07:20.949313 [DATLAT]
6440 23:07:20.952746 Freq=400, CH0 RK0
6441 23:07:20.952825
6442 23:07:20.955998 DATLAT Default: 0xf
6443 23:07:20.956076 0, 0xFFFF, sum = 0
6444 23:07:20.959414 1, 0xFFFF, sum = 0
6445 23:07:20.959494 2, 0xFFFF, sum = 0
6446 23:07:20.962679 3, 0xFFFF, sum = 0
6447 23:07:20.962768 4, 0xFFFF, sum = 0
6448 23:07:20.965998 5, 0xFFFF, sum = 0
6449 23:07:20.966078 6, 0xFFFF, sum = 0
6450 23:07:20.969188 7, 0xFFFF, sum = 0
6451 23:07:20.969268 8, 0xFFFF, sum = 0
6452 23:07:20.973219 9, 0xFFFF, sum = 0
6453 23:07:20.973300 10, 0xFFFF, sum = 0
6454 23:07:20.975883 11, 0xFFFF, sum = 0
6455 23:07:20.975963 12, 0xFFFF, sum = 0
6456 23:07:20.979509 13, 0x0, sum = 1
6457 23:07:20.979590 14, 0x0, sum = 2
6458 23:07:20.982488 15, 0x0, sum = 3
6459 23:07:20.982569 16, 0x0, sum = 4
6460 23:07:20.985536 best_step = 14
6461 23:07:20.985615
6462 23:07:20.985679 ==
6463 23:07:20.988993 Dram Type= 6, Freq= 0, CH_0, rank 0
6464 23:07:20.992566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6465 23:07:20.992647 ==
6466 23:07:20.995547 RX Vref Scan: 1
6467 23:07:20.995625
6468 23:07:20.995688 RX Vref 0 -> 0, step: 1
6469 23:07:20.995747
6470 23:07:20.998975 RX Delay -359 -> 252, step: 8
6471 23:07:20.999088
6472 23:07:21.002628 Set Vref, RX VrefLevel [Byte0]: 61
6473 23:07:21.006011 [Byte1]: 47
6474 23:07:21.010299
6475 23:07:21.010396 Final RX Vref Byte 0 = 61 to rank0
6476 23:07:21.013594 Final RX Vref Byte 1 = 47 to rank0
6477 23:07:21.016639 Final RX Vref Byte 0 = 61 to rank1
6478 23:07:21.019919 Final RX Vref Byte 1 = 47 to rank1==
6479 23:07:21.023519 Dram Type= 6, Freq= 0, CH_0, rank 0
6480 23:07:21.030182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6481 23:07:21.030257 ==
6482 23:07:21.030319 DQS Delay:
6483 23:07:21.033456 DQS0 = 60, DQS1 = 64
6484 23:07:21.033551 DQM Delay:
6485 23:07:21.033638 DQM0 = 14, DQM1 = 10
6486 23:07:21.036646 DQ Delay:
6487 23:07:21.039727 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =16
6488 23:07:21.043618 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6489 23:07:21.043711 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6490 23:07:21.046674 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =16
6491 23:07:21.049738
6492 23:07:21.049833
6493 23:07:21.056782 [DQSOSCAuto] RK0, (LSB)MR18= 0x8481, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6494 23:07:21.059834 CH0 RK0: MR19=C0C, MR18=8481
6495 23:07:21.066359 CH0_RK0: MR19=0xC0C, MR18=0x8481, DQSOSC=393, MR23=63, INC=382, DEC=254
6496 23:07:21.066459 ==
6497 23:07:21.069492 Dram Type= 6, Freq= 0, CH_0, rank 1
6498 23:07:21.073244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6499 23:07:21.073314 ==
6500 23:07:21.076375 [Gating] SW mode calibration
6501 23:07:21.082909 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6502 23:07:21.089686 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6503 23:07:21.093095 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6504 23:07:21.096173 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6505 23:07:21.102684 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6506 23:07:21.106073 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6507 23:07:21.109657 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6508 23:07:21.115870 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6509 23:07:21.119334 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6510 23:07:21.122478 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6511 23:07:21.129497 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6512 23:07:21.129576 Total UI for P1: 0, mck2ui 16
6513 23:07:21.136081 best dqsien dly found for B0: ( 0, 14, 24)
6514 23:07:21.136176 Total UI for P1: 0, mck2ui 16
6515 23:07:21.139456 best dqsien dly found for B1: ( 0, 14, 24)
6516 23:07:21.145847 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6517 23:07:21.149000 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6518 23:07:21.149068
6519 23:07:21.152828 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6520 23:07:21.155688 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6521 23:07:21.159272 [Gating] SW calibration Done
6522 23:07:21.159367 ==
6523 23:07:21.162297 Dram Type= 6, Freq= 0, CH_0, rank 1
6524 23:07:21.165549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6525 23:07:21.165622 ==
6526 23:07:21.168837 RX Vref Scan: 0
6527 23:07:21.168946
6528 23:07:21.169039 RX Vref 0 -> 0, step: 1
6529 23:07:21.169126
6530 23:07:21.172526 RX Delay -410 -> 252, step: 16
6531 23:07:21.178694 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6532 23:07:21.182461 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6533 23:07:21.185468 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6534 23:07:21.188869 iDelay=230, Bit 3, Center -51 (-314 ~ 213) 528
6535 23:07:21.195766 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6536 23:07:21.198915 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6537 23:07:21.202184 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6538 23:07:21.205476 iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528
6539 23:07:21.211992 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6540 23:07:21.215272 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6541 23:07:21.218466 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6542 23:07:21.221838 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6543 23:07:21.228404 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6544 23:07:21.231851 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6545 23:07:21.235608 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6546 23:07:21.238491 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6547 23:07:21.242067 ==
6548 23:07:21.245042 Dram Type= 6, Freq= 0, CH_0, rank 1
6549 23:07:21.248571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6550 23:07:21.248649 ==
6551 23:07:21.248733 DQS Delay:
6552 23:07:21.251798 DQS0 = 59, DQS1 = 59
6553 23:07:21.251893 DQM Delay:
6554 23:07:21.255033 DQM0 = 15, DQM1 = 10
6555 23:07:21.255128 DQ Delay:
6556 23:07:21.258292 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =8
6557 23:07:21.262213 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6558 23:07:21.265193 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6559 23:07:21.268482 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6560 23:07:21.268553
6561 23:07:21.268614
6562 23:07:21.268670 ==
6563 23:07:21.271758 Dram Type= 6, Freq= 0, CH_0, rank 1
6564 23:07:21.274809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6565 23:07:21.274908 ==
6566 23:07:21.274996
6567 23:07:21.275081
6568 23:07:21.278344 TX Vref Scan disable
6569 23:07:21.278412 == TX Byte 0 ==
6570 23:07:21.285241 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6571 23:07:21.288062 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6572 23:07:21.288139 == TX Byte 1 ==
6573 23:07:21.294665 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6574 23:07:21.297975 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6575 23:07:21.298060 ==
6576 23:07:21.301335 Dram Type= 6, Freq= 0, CH_0, rank 1
6577 23:07:21.304733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6578 23:07:21.304853 ==
6579 23:07:21.304953
6580 23:07:21.305040
6581 23:07:21.307942 TX Vref Scan disable
6582 23:07:21.308041 == TX Byte 0 ==
6583 23:07:21.314466 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6584 23:07:21.318035 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6585 23:07:21.318140 == TX Byte 1 ==
6586 23:07:21.324814 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6587 23:07:21.327594 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6588 23:07:21.327690
6589 23:07:21.327777 [DATLAT]
6590 23:07:21.331238 Freq=400, CH0 RK1
6591 23:07:21.331332
6592 23:07:21.331422 DATLAT Default: 0xe
6593 23:07:21.334705 0, 0xFFFF, sum = 0
6594 23:07:21.334799 1, 0xFFFF, sum = 0
6595 23:07:21.337964 2, 0xFFFF, sum = 0
6596 23:07:21.338049 3, 0xFFFF, sum = 0
6597 23:07:21.340875 4, 0xFFFF, sum = 0
6598 23:07:21.344118 5, 0xFFFF, sum = 0
6599 23:07:21.344252 6, 0xFFFF, sum = 0
6600 23:07:21.347792 7, 0xFFFF, sum = 0
6601 23:07:21.347895 8, 0xFFFF, sum = 0
6602 23:07:21.351028 9, 0xFFFF, sum = 0
6603 23:07:21.351136 10, 0xFFFF, sum = 0
6604 23:07:21.354365 11, 0xFFFF, sum = 0
6605 23:07:21.354466 12, 0xFFFF, sum = 0
6606 23:07:21.357576 13, 0x0, sum = 1
6607 23:07:21.357684 14, 0x0, sum = 2
6608 23:07:21.360777 15, 0x0, sum = 3
6609 23:07:21.360850 16, 0x0, sum = 4
6610 23:07:21.363978 best_step = 14
6611 23:07:21.364075
6612 23:07:21.364162 ==
6613 23:07:21.367151 Dram Type= 6, Freq= 0, CH_0, rank 1
6614 23:07:21.370515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6615 23:07:21.370612 ==
6616 23:07:21.370702 RX Vref Scan: 0
6617 23:07:21.374020
6618 23:07:21.374113 RX Vref 0 -> 0, step: 1
6619 23:07:21.374201
6620 23:07:21.377286 RX Delay -359 -> 252, step: 8
6621 23:07:21.384622 iDelay=217, Bit 0, Center -48 (-295 ~ 200) 496
6622 23:07:21.387999 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6623 23:07:21.391194 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6624 23:07:21.394582 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6625 23:07:21.400960 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6626 23:07:21.404667 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6627 23:07:21.407867 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6628 23:07:21.414191 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6629 23:07:21.417491 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6630 23:07:21.421072 iDelay=217, Bit 9, Center -68 (-311 ~ 176) 488
6631 23:07:21.424440 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6632 23:07:21.430978 iDelay=217, Bit 11, Center -64 (-311 ~ 184) 496
6633 23:07:21.434160 iDelay=217, Bit 12, Center -48 (-295 ~ 200) 496
6634 23:07:21.438110 iDelay=217, Bit 13, Center -44 (-295 ~ 208) 504
6635 23:07:21.441012 iDelay=217, Bit 14, Center -48 (-295 ~ 200) 496
6636 23:07:21.447272 iDelay=217, Bit 15, Center -48 (-295 ~ 200) 496
6637 23:07:21.447371 ==
6638 23:07:21.450597 Dram Type= 6, Freq= 0, CH_0, rank 1
6639 23:07:21.454235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6640 23:07:21.454331 ==
6641 23:07:21.454420 DQS Delay:
6642 23:07:21.457501 DQS0 = 60, DQS1 = 68
6643 23:07:21.457596 DQM Delay:
6644 23:07:21.460925 DQM0 = 12, DQM1 = 13
6645 23:07:21.461006 DQ Delay:
6646 23:07:21.464022 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =8
6647 23:07:21.467163 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24
6648 23:07:21.470555 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6649 23:07:21.474376 DQ12 =20, DQ13 =24, DQ14 =20, DQ15 =20
6650 23:07:21.474448
6651 23:07:21.474511
6652 23:07:21.480744 [DQSOSCAuto] RK1, (LSB)MR18= 0xc278, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 385 ps
6653 23:07:21.484090 CH0 RK1: MR19=C0C, MR18=C278
6654 23:07:21.490401 CH0_RK1: MR19=0xC0C, MR18=0xC278, DQSOSC=385, MR23=63, INC=398, DEC=265
6655 23:07:21.493602 [RxdqsGatingPostProcess] freq 400
6656 23:07:21.500723 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6657 23:07:21.503796 best DQS0 dly(2T, 0.5T) = (0, 10)
6658 23:07:21.506880 best DQS1 dly(2T, 0.5T) = (0, 10)
6659 23:07:21.510262 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6660 23:07:21.513456 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6661 23:07:21.513552 best DQS0 dly(2T, 0.5T) = (0, 10)
6662 23:07:21.517319 best DQS1 dly(2T, 0.5T) = (0, 10)
6663 23:07:21.520657 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6664 23:07:21.523409 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6665 23:07:21.526840 Pre-setting of DQS Precalculation
6666 23:07:21.533449 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6667 23:07:21.533547 ==
6668 23:07:21.536758 Dram Type= 6, Freq= 0, CH_1, rank 0
6669 23:07:21.540363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6670 23:07:21.540443 ==
6671 23:07:21.546902 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6672 23:07:21.553752 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6673 23:07:21.557008 [CA 0] Center 36 (8~64) winsize 57
6674 23:07:21.557083 [CA 1] Center 36 (8~64) winsize 57
6675 23:07:21.560064 [CA 2] Center 36 (8~64) winsize 57
6676 23:07:21.563804 [CA 3] Center 36 (8~64) winsize 57
6677 23:07:21.566847 [CA 4] Center 36 (8~64) winsize 57
6678 23:07:21.570231 [CA 5] Center 36 (8~64) winsize 57
6679 23:07:21.570311
6680 23:07:21.573479 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6681 23:07:21.573559
6682 23:07:21.576634 [CATrainingPosCal] consider 1 rank data
6683 23:07:21.580129 u2DelayCellTimex100 = 270/100 ps
6684 23:07:21.583043 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6685 23:07:21.590211 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6686 23:07:21.593237 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6687 23:07:21.596665 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6688 23:07:21.599911 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6689 23:07:21.603377 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6690 23:07:21.603459
6691 23:07:21.606627 CA PerBit enable=1, Macro0, CA PI delay=36
6692 23:07:21.606710
6693 23:07:21.609769 [CBTSetCACLKResult] CA Dly = 36
6694 23:07:21.609851 CS Dly: 1 (0~32)
6695 23:07:21.613012 ==
6696 23:07:21.616494 Dram Type= 6, Freq= 0, CH_1, rank 1
6697 23:07:21.619618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6698 23:07:21.619701 ==
6699 23:07:21.623268 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6700 23:07:21.629637 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6701 23:07:21.633036 [CA 0] Center 36 (8~64) winsize 57
6702 23:07:21.636598 [CA 1] Center 36 (8~64) winsize 57
6703 23:07:21.639742 [CA 2] Center 36 (8~64) winsize 57
6704 23:07:21.642784 [CA 3] Center 36 (8~64) winsize 57
6705 23:07:21.646369 [CA 4] Center 36 (8~64) winsize 57
6706 23:07:21.649701 [CA 5] Center 36 (8~64) winsize 57
6707 23:07:21.649784
6708 23:07:21.652894 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6709 23:07:21.652997
6710 23:07:21.656138 [CATrainingPosCal] consider 2 rank data
6711 23:07:21.659213 u2DelayCellTimex100 = 270/100 ps
6712 23:07:21.662746 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6713 23:07:21.666092 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6714 23:07:21.669284 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6715 23:07:21.673112 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6716 23:07:21.679575 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6717 23:07:21.682666 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6718 23:07:21.682745
6719 23:07:21.686035 CA PerBit enable=1, Macro0, CA PI delay=36
6720 23:07:21.686115
6721 23:07:21.689241 [CBTSetCACLKResult] CA Dly = 36
6722 23:07:21.689320 CS Dly: 1 (0~32)
6723 23:07:21.689383
6724 23:07:21.692933 ----->DramcWriteLeveling(PI) begin...
6725 23:07:21.693013 ==
6726 23:07:21.696041 Dram Type= 6, Freq= 0, CH_1, rank 0
6727 23:07:21.702713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6728 23:07:21.702797 ==
6729 23:07:21.705915 Write leveling (Byte 0): 40 => 8
6730 23:07:21.708994 Write leveling (Byte 1): 40 => 8
6731 23:07:21.709078 DramcWriteLeveling(PI) end<-----
6732 23:07:21.709162
6733 23:07:21.712409 ==
6734 23:07:21.716094 Dram Type= 6, Freq= 0, CH_1, rank 0
6735 23:07:21.718870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6736 23:07:21.718953 ==
6737 23:07:21.722247 [Gating] SW mode calibration
6738 23:07:21.728921 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6739 23:07:21.732510 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6740 23:07:21.739093 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6741 23:07:21.742271 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6742 23:07:21.745429 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6743 23:07:21.752130 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6744 23:07:21.755583 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6745 23:07:21.758675 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6746 23:07:21.765856 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6747 23:07:21.768698 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6748 23:07:21.772346 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6749 23:07:21.775554 Total UI for P1: 0, mck2ui 16
6750 23:07:21.778678 best dqsien dly found for B0: ( 0, 14, 24)
6751 23:07:21.782360 Total UI for P1: 0, mck2ui 16
6752 23:07:21.785717 best dqsien dly found for B1: ( 0, 14, 24)
6753 23:07:21.788775 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6754 23:07:21.792135 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6755 23:07:21.792225
6756 23:07:21.798479 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6757 23:07:21.801912 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6758 23:07:21.805108 [Gating] SW calibration Done
6759 23:07:21.805190 ==
6760 23:07:21.808503 Dram Type= 6, Freq= 0, CH_1, rank 0
6761 23:07:21.811889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6762 23:07:21.811972 ==
6763 23:07:21.812071 RX Vref Scan: 0
6764 23:07:21.812168
6765 23:07:21.815056 RX Vref 0 -> 0, step: 1
6766 23:07:21.815138
6767 23:07:21.818531 RX Delay -410 -> 252, step: 16
6768 23:07:21.821757 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6769 23:07:21.828815 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6770 23:07:21.831637 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6771 23:07:21.835031 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6772 23:07:21.838572 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6773 23:07:21.845030 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6774 23:07:21.848148 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6775 23:07:21.851453 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6776 23:07:21.855048 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6777 23:07:21.861304 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6778 23:07:21.864972 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6779 23:07:21.868159 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6780 23:07:21.871560 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6781 23:07:21.877995 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6782 23:07:21.881150 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6783 23:07:21.885049 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6784 23:07:21.885131 ==
6785 23:07:21.888132 Dram Type= 6, Freq= 0, CH_1, rank 0
6786 23:07:21.891520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6787 23:07:21.894625 ==
6788 23:07:21.894708 DQS Delay:
6789 23:07:21.894791 DQS0 = 43, DQS1 = 67
6790 23:07:21.897823 DQM Delay:
6791 23:07:21.897905 DQM0 = 6, DQM1 = 18
6792 23:07:21.901158 DQ Delay:
6793 23:07:21.904488 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6794 23:07:21.904571 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6795 23:07:21.907672 DQ8 =0, DQ9 =8, DQ10 =24, DQ11 =16
6796 23:07:21.911339 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6797 23:07:21.911421
6798 23:07:21.911505
6799 23:07:21.914387 ==
6800 23:07:21.917688 Dram Type= 6, Freq= 0, CH_1, rank 0
6801 23:07:21.921000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6802 23:07:21.921083 ==
6803 23:07:21.921206
6804 23:07:21.921285
6805 23:07:21.924118 TX Vref Scan disable
6806 23:07:21.924208 == TX Byte 0 ==
6807 23:07:21.927399 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6808 23:07:21.934397 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6809 23:07:21.934477 == TX Byte 1 ==
6810 23:07:21.937351 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6811 23:07:21.944190 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6812 23:07:21.944332 ==
6813 23:07:21.947306 Dram Type= 6, Freq= 0, CH_1, rank 0
6814 23:07:21.950644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6815 23:07:21.950727 ==
6816 23:07:21.950810
6817 23:07:21.950890
6818 23:07:21.953814 TX Vref Scan disable
6819 23:07:21.953896 == TX Byte 0 ==
6820 23:07:21.957676 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6821 23:07:21.964099 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6822 23:07:21.964186 == TX Byte 1 ==
6823 23:07:21.967018 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6824 23:07:21.973861 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6825 23:07:21.973944
6826 23:07:21.974027 [DATLAT]
6827 23:07:21.974106 Freq=400, CH1 RK0
6828 23:07:21.977000
6829 23:07:21.977083 DATLAT Default: 0xf
6830 23:07:21.980627 0, 0xFFFF, sum = 0
6831 23:07:21.980734 1, 0xFFFF, sum = 0
6832 23:07:21.983954 2, 0xFFFF, sum = 0
6833 23:07:21.984037 3, 0xFFFF, sum = 0
6834 23:07:21.987070 4, 0xFFFF, sum = 0
6835 23:07:21.987153 5, 0xFFFF, sum = 0
6836 23:07:21.990511 6, 0xFFFF, sum = 0
6837 23:07:21.990595 7, 0xFFFF, sum = 0
6838 23:07:21.993587 8, 0xFFFF, sum = 0
6839 23:07:21.993671 9, 0xFFFF, sum = 0
6840 23:07:21.997312 10, 0xFFFF, sum = 0
6841 23:07:21.997396 11, 0xFFFF, sum = 0
6842 23:07:22.000468 12, 0xFFFF, sum = 0
6843 23:07:22.000552 13, 0x0, sum = 1
6844 23:07:22.003773 14, 0x0, sum = 2
6845 23:07:22.003853 15, 0x0, sum = 3
6846 23:07:22.007181 16, 0x0, sum = 4
6847 23:07:22.007262 best_step = 14
6848 23:07:22.007325
6849 23:07:22.007383 ==
6850 23:07:22.010266 Dram Type= 6, Freq= 0, CH_1, rank 0
6851 23:07:22.016739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6852 23:07:22.016819 ==
6853 23:07:22.016881 RX Vref Scan: 1
6854 23:07:22.016939
6855 23:07:22.020682 RX Vref 0 -> 0, step: 1
6856 23:07:22.020787
6857 23:07:22.023275 RX Delay -375 -> 252, step: 8
6858 23:07:22.023355
6859 23:07:22.026739 Set Vref, RX VrefLevel [Byte0]: 54
6860 23:07:22.030064 [Byte1]: 50
6861 23:07:22.030144
6862 23:07:22.033559 Final RX Vref Byte 0 = 54 to rank0
6863 23:07:22.036666 Final RX Vref Byte 1 = 50 to rank0
6864 23:07:22.040195 Final RX Vref Byte 0 = 54 to rank1
6865 23:07:22.043369 Final RX Vref Byte 1 = 50 to rank1==
6866 23:07:22.047078 Dram Type= 6, Freq= 0, CH_1, rank 0
6867 23:07:22.050785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6868 23:07:22.053531 ==
6869 23:07:22.053610 DQS Delay:
6870 23:07:22.053673 DQS0 = 52, DQS1 = 64
6871 23:07:22.056591 DQM Delay:
6872 23:07:22.056670 DQM0 = 8, DQM1 = 10
6873 23:07:22.059897 DQ Delay:
6874 23:07:22.059976 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =4
6875 23:07:22.063468 DQ4 =8, DQ5 =16, DQ6 =20, DQ7 =4
6876 23:07:22.066691 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6877 23:07:22.070030 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
6878 23:07:22.070109
6879 23:07:22.070171
6880 23:07:22.080126 [DQSOSCAuto] RK0, (LSB)MR18= 0x5c6f, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 398 ps
6881 23:07:22.083199 CH1 RK0: MR19=C0C, MR18=5C6F
6882 23:07:22.086479 CH1_RK0: MR19=0xC0C, MR18=0x5C6F, DQSOSC=395, MR23=63, INC=378, DEC=252
6883 23:07:22.090088 ==
6884 23:07:22.093081 Dram Type= 6, Freq= 0, CH_1, rank 1
6885 23:07:22.096986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6886 23:07:22.097066 ==
6887 23:07:22.100171 [Gating] SW mode calibration
6888 23:07:22.106480 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6889 23:07:22.110162 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6890 23:07:22.116738 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6891 23:07:22.119811 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6892 23:07:22.123704 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6893 23:07:22.130021 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6894 23:07:22.133194 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6895 23:07:22.136368 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6896 23:07:22.143341 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6897 23:07:22.146729 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6898 23:07:22.149664 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6899 23:07:22.153062 Total UI for P1: 0, mck2ui 16
6900 23:07:22.156781 best dqsien dly found for B0: ( 0, 14, 24)
6901 23:07:22.159824 Total UI for P1: 0, mck2ui 16
6902 23:07:22.163077 best dqsien dly found for B1: ( 0, 14, 24)
6903 23:07:22.166395 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6904 23:07:22.169612 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6905 23:07:22.169694
6906 23:07:22.176175 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6907 23:07:22.179688 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6908 23:07:22.179771 [Gating] SW calibration Done
6909 23:07:22.182863 ==
6910 23:07:22.186319 Dram Type= 6, Freq= 0, CH_1, rank 1
6911 23:07:22.189561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6912 23:07:22.189652 ==
6913 23:07:22.189734 RX Vref Scan: 0
6914 23:07:22.189812
6915 23:07:22.192757 RX Vref 0 -> 0, step: 1
6916 23:07:22.192839
6917 23:07:22.196359 RX Delay -410 -> 252, step: 16
6918 23:07:22.199688 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6919 23:07:22.206090 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6920 23:07:22.209554 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6921 23:07:22.212611 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6922 23:07:22.216308 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6923 23:07:22.222772 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6924 23:07:22.226133 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6925 23:07:22.229226 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6926 23:07:22.232864 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6927 23:07:22.239424 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6928 23:07:22.242769 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6929 23:07:22.246148 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6930 23:07:22.249087 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6931 23:07:22.255537 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6932 23:07:22.259131 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6933 23:07:22.262500 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6934 23:07:22.262592 ==
6935 23:07:22.265752 Dram Type= 6, Freq= 0, CH_1, rank 1
6936 23:07:22.272505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6937 23:07:22.272588 ==
6938 23:07:22.272672 DQS Delay:
6939 23:07:22.272750 DQS0 = 59, DQS1 = 59
6940 23:07:22.275652 DQM Delay:
6941 23:07:22.275758 DQM0 = 19, DQM1 = 14
6942 23:07:22.279062 DQ Delay:
6943 23:07:22.282356 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6944 23:07:22.285882 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6945 23:07:22.285965 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6946 23:07:22.288680 DQ12 =16, DQ13 =24, DQ14 =16, DQ15 =24
6947 23:07:22.292478
6948 23:07:22.292560
6949 23:07:22.292643 ==
6950 23:07:22.295540 Dram Type= 6, Freq= 0, CH_1, rank 1
6951 23:07:22.298688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6952 23:07:22.298780 ==
6953 23:07:22.298864
6954 23:07:22.298943
6955 23:07:22.301800 TX Vref Scan disable
6956 23:07:22.301900 == TX Byte 0 ==
6957 23:07:22.305157 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6958 23:07:22.312045 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6959 23:07:22.312129 == TX Byte 1 ==
6960 23:07:22.314910 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6961 23:07:22.321510 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6962 23:07:22.321593 ==
6963 23:07:22.324806 Dram Type= 6, Freq= 0, CH_1, rank 1
6964 23:07:22.328130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6965 23:07:22.328239 ==
6966 23:07:22.328336
6967 23:07:22.328415
6968 23:07:22.331749 TX Vref Scan disable
6969 23:07:22.331831 == TX Byte 0 ==
6970 23:07:22.338050 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6971 23:07:22.342102 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6972 23:07:22.342185 == TX Byte 1 ==
6973 23:07:22.348587 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6974 23:07:22.351660 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6975 23:07:22.351785
6976 23:07:22.351869 [DATLAT]
6977 23:07:22.354866 Freq=400, CH1 RK1
6978 23:07:22.354949
6979 23:07:22.355032 DATLAT Default: 0xe
6980 23:07:22.357935 0, 0xFFFF, sum = 0
6981 23:07:22.358019 1, 0xFFFF, sum = 0
6982 23:07:22.361119 2, 0xFFFF, sum = 0
6983 23:07:22.361202 3, 0xFFFF, sum = 0
6984 23:07:22.364513 4, 0xFFFF, sum = 0
6985 23:07:22.364597 5, 0xFFFF, sum = 0
6986 23:07:22.368102 6, 0xFFFF, sum = 0
6987 23:07:22.368185 7, 0xFFFF, sum = 0
6988 23:07:22.371355 8, 0xFFFF, sum = 0
6989 23:07:22.371438 9, 0xFFFF, sum = 0
6990 23:07:22.374440 10, 0xFFFF, sum = 0
6991 23:07:22.377748 11, 0xFFFF, sum = 0
6992 23:07:22.377864 12, 0xFFFF, sum = 0
6993 23:07:22.380970 13, 0x0, sum = 1
6994 23:07:22.381044 14, 0x0, sum = 2
6995 23:07:22.381116 15, 0x0, sum = 3
6996 23:07:22.384473 16, 0x0, sum = 4
6997 23:07:22.384544 best_step = 14
6998 23:07:22.384613
6999 23:07:22.387842 ==
7000 23:07:22.387945 Dram Type= 6, Freq= 0, CH_1, rank 1
7001 23:07:22.394255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7002 23:07:22.394353 ==
7003 23:07:22.394442 RX Vref Scan: 0
7004 23:07:22.394526
7005 23:07:22.397775 RX Vref 0 -> 0, step: 1
7006 23:07:22.397870
7007 23:07:22.400852 RX Delay -359 -> 252, step: 8
7008 23:07:22.407704 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
7009 23:07:22.411220 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
7010 23:07:22.414688 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
7011 23:07:22.420904 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
7012 23:07:22.424044 iDelay=217, Bit 4, Center -48 (-303 ~ 208) 512
7013 23:07:22.427575 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
7014 23:07:22.430556 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
7015 23:07:22.437092 iDelay=217, Bit 7, Center -52 (-303 ~ 200) 504
7016 23:07:22.440773 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
7017 23:07:22.443955 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
7018 23:07:22.447266 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
7019 23:07:22.453768 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
7020 23:07:22.456995 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
7021 23:07:22.460916 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
7022 23:07:22.463451 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
7023 23:07:22.470197 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
7024 23:07:22.470300 ==
7025 23:07:22.473736 Dram Type= 6, Freq= 0, CH_1, rank 1
7026 23:07:22.476923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7027 23:07:22.477012 ==
7028 23:07:22.480187 DQS Delay:
7029 23:07:22.480297 DQS0 = 60, DQS1 = 64
7030 23:07:22.480359 DQM Delay:
7031 23:07:22.483252 DQM0 = 12, DQM1 = 10
7032 23:07:22.483324 DQ Delay:
7033 23:07:22.486645 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
7034 23:07:22.489928 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
7035 23:07:22.493542 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
7036 23:07:22.496279 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
7037 23:07:22.496375
7038 23:07:22.496442
7039 23:07:22.506190 [DQSOSCAuto] RK1, (LSB)MR18= 0x76a6, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 394 ps
7040 23:07:22.506294 CH1 RK1: MR19=C0C, MR18=76A6
7041 23:07:22.512993 CH1_RK1: MR19=0xC0C, MR18=0x76A6, DQSOSC=389, MR23=63, INC=390, DEC=260
7042 23:07:22.516316 [RxdqsGatingPostProcess] freq 400
7043 23:07:22.522967 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7044 23:07:22.526033 best DQS0 dly(2T, 0.5T) = (0, 10)
7045 23:07:22.529496 best DQS1 dly(2T, 0.5T) = (0, 10)
7046 23:07:22.532680 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7047 23:07:22.536564 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7048 23:07:22.539301 best DQS0 dly(2T, 0.5T) = (0, 10)
7049 23:07:22.542898 best DQS1 dly(2T, 0.5T) = (0, 10)
7050 23:07:22.546097 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7051 23:07:22.549585 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7052 23:07:22.549688 Pre-setting of DQS Precalculation
7053 23:07:22.555950 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7054 23:07:22.562951 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7055 23:07:22.569118 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7056 23:07:22.569196
7057 23:07:22.569258
7058 23:07:22.572644 [Calibration Summary] 800 Mbps
7059 23:07:22.575758 CH 0, Rank 0
7060 23:07:22.575860 SW Impedance : PASS
7061 23:07:22.579183 DUTY Scan : NO K
7062 23:07:22.579278 ZQ Calibration : PASS
7063 23:07:22.583006 Jitter Meter : NO K
7064 23:07:22.585712 CBT Training : PASS
7065 23:07:22.585782 Write leveling : PASS
7066 23:07:22.589032 RX DQS gating : PASS
7067 23:07:22.592759 RX DQ/DQS(RDDQC) : PASS
7068 23:07:22.592828 TX DQ/DQS : PASS
7069 23:07:22.596071 RX DATLAT : PASS
7070 23:07:22.599111 RX DQ/DQS(Engine): PASS
7071 23:07:22.599207 TX OE : NO K
7072 23:07:22.602635 All Pass.
7073 23:07:22.602728
7074 23:07:22.602814 CH 0, Rank 1
7075 23:07:22.605863 SW Impedance : PASS
7076 23:07:22.605932 DUTY Scan : NO K
7077 23:07:22.608932 ZQ Calibration : PASS
7078 23:07:22.612680 Jitter Meter : NO K
7079 23:07:22.612773 CBT Training : PASS
7080 23:07:22.615525 Write leveling : NO K
7081 23:07:22.618801 RX DQS gating : PASS
7082 23:07:22.618876 RX DQ/DQS(RDDQC) : PASS
7083 23:07:22.622251 TX DQ/DQS : PASS
7084 23:07:22.625148 RX DATLAT : PASS
7085 23:07:22.625243 RX DQ/DQS(Engine): PASS
7086 23:07:22.628523 TX OE : NO K
7087 23:07:22.628596 All Pass.
7088 23:07:22.628670
7089 23:07:22.631921 CH 1, Rank 0
7090 23:07:22.632015 SW Impedance : PASS
7091 23:07:22.635202 DUTY Scan : NO K
7092 23:07:22.638742 ZQ Calibration : PASS
7093 23:07:22.638839 Jitter Meter : NO K
7094 23:07:22.642004 CBT Training : PASS
7095 23:07:22.645374 Write leveling : PASS
7096 23:07:22.645471 RX DQS gating : PASS
7097 23:07:22.648495 RX DQ/DQS(RDDQC) : PASS
7098 23:07:22.648568 TX DQ/DQS : PASS
7099 23:07:22.651947 RX DATLAT : PASS
7100 23:07:22.655054 RX DQ/DQS(Engine): PASS
7101 23:07:22.655150 TX OE : NO K
7102 23:07:22.658453 All Pass.
7103 23:07:22.658556
7104 23:07:22.658644 CH 1, Rank 1
7105 23:07:22.662124 SW Impedance : PASS
7106 23:07:22.662219 DUTY Scan : NO K
7107 23:07:22.665353 ZQ Calibration : PASS
7108 23:07:22.668798 Jitter Meter : NO K
7109 23:07:22.668883 CBT Training : PASS
7110 23:07:22.671596 Write leveling : NO K
7111 23:07:22.674944 RX DQS gating : PASS
7112 23:07:22.675038 RX DQ/DQS(RDDQC) : PASS
7113 23:07:22.678031 TX DQ/DQS : PASS
7114 23:07:22.681355 RX DATLAT : PASS
7115 23:07:22.681433 RX DQ/DQS(Engine): PASS
7116 23:07:22.684526 TX OE : NO K
7117 23:07:22.684593 All Pass.
7118 23:07:22.684655
7119 23:07:22.687850 DramC Write-DBI off
7120 23:07:22.691623 PER_BANK_REFRESH: Hybrid Mode
7121 23:07:22.691716 TX_TRACKING: ON
7122 23:07:22.701428 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7123 23:07:22.704603 [FAST_K] Save calibration result to emmc
7124 23:07:22.707744 dramc_set_vcore_voltage set vcore to 725000
7125 23:07:22.711140 Read voltage for 1600, 0
7126 23:07:22.711232 Vio18 = 0
7127 23:07:22.711318 Vcore = 725000
7128 23:07:22.714551 Vdram = 0
7129 23:07:22.714642 Vddq = 0
7130 23:07:22.714727 Vmddr = 0
7131 23:07:22.720870 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7132 23:07:22.724995 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7133 23:07:22.727736 MEM_TYPE=3, freq_sel=13
7134 23:07:22.730863 sv_algorithm_assistance_LP4_3733
7135 23:07:22.734196 ============ PULL DRAM RESETB DOWN ============
7136 23:07:22.740894 ========== PULL DRAM RESETB DOWN end =========
7137 23:07:22.744102 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7138 23:07:22.747916 ===================================
7139 23:07:22.751445 LPDDR4 DRAM CONFIGURATION
7140 23:07:22.754343 ===================================
7141 23:07:22.754422 EX_ROW_EN[0] = 0x0
7142 23:07:22.757340 EX_ROW_EN[1] = 0x0
7143 23:07:22.757417 LP4Y_EN = 0x0
7144 23:07:22.760730 WORK_FSP = 0x1
7145 23:07:22.760802 WL = 0x5
7146 23:07:22.764184 RL = 0x5
7147 23:07:22.764288 BL = 0x2
7148 23:07:22.767395 RPST = 0x0
7149 23:07:22.767490 RD_PRE = 0x0
7150 23:07:22.770776 WR_PRE = 0x1
7151 23:07:22.774006 WR_PST = 0x1
7152 23:07:22.774076 DBI_WR = 0x0
7153 23:07:22.777186 DBI_RD = 0x0
7154 23:07:22.777255 OTF = 0x1
7155 23:07:22.780405 ===================================
7156 23:07:22.783546 ===================================
7157 23:07:22.786833 ANA top config
7158 23:07:22.790305 ===================================
7159 23:07:22.790413 DLL_ASYNC_EN = 0
7160 23:07:22.793578 ALL_SLAVE_EN = 0
7161 23:07:22.796768 NEW_RANK_MODE = 1
7162 23:07:22.800478 DLL_IDLE_MODE = 1
7163 23:07:22.800547 LP45_APHY_COMB_EN = 1
7164 23:07:22.803481 TX_ODT_DIS = 0
7165 23:07:22.806699 NEW_8X_MODE = 1
7166 23:07:22.810082 ===================================
7167 23:07:22.813686 ===================================
7168 23:07:22.816934 data_rate = 3200
7169 23:07:22.820133 CKR = 1
7170 23:07:22.823187 DQ_P2S_RATIO = 8
7171 23:07:22.826546 ===================================
7172 23:07:22.826653 CA_P2S_RATIO = 8
7173 23:07:22.830276 DQ_CA_OPEN = 0
7174 23:07:22.833454 DQ_SEMI_OPEN = 0
7175 23:07:22.836608 CA_SEMI_OPEN = 0
7176 23:07:22.839802 CA_FULL_RATE = 0
7177 23:07:22.843357 DQ_CKDIV4_EN = 0
7178 23:07:22.843456 CA_CKDIV4_EN = 0
7179 23:07:22.846373 CA_PREDIV_EN = 0
7180 23:07:22.850131 PH8_DLY = 12
7181 23:07:22.852925 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7182 23:07:22.856569 DQ_AAMCK_DIV = 4
7183 23:07:22.859799 CA_AAMCK_DIV = 4
7184 23:07:22.859894 CA_ADMCK_DIV = 4
7185 23:07:22.862924 DQ_TRACK_CA_EN = 0
7186 23:07:22.866539 CA_PICK = 1600
7187 23:07:22.869758 CA_MCKIO = 1600
7188 23:07:22.873028 MCKIO_SEMI = 0
7189 23:07:22.876382 PLL_FREQ = 3068
7190 23:07:22.880126 DQ_UI_PI_RATIO = 32
7191 23:07:22.882695 CA_UI_PI_RATIO = 0
7192 23:07:22.886038 ===================================
7193 23:07:22.889844 ===================================
7194 23:07:22.889941 memory_type:LPDDR4
7195 23:07:22.892747 GP_NUM : 10
7196 23:07:22.895967 SRAM_EN : 1
7197 23:07:22.896035 MD32_EN : 0
7198 23:07:22.899285 ===================================
7199 23:07:22.902406 [ANA_INIT] >>>>>>>>>>>>>>
7200 23:07:22.905863 <<<<<< [CONFIGURE PHASE]: ANA_TX
7201 23:07:22.909217 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7202 23:07:22.912497 ===================================
7203 23:07:22.915937 data_rate = 3200,PCW = 0X7600
7204 23:07:22.918942 ===================================
7205 23:07:22.922139 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7206 23:07:22.925980 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7207 23:07:22.932309 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7208 23:07:22.935972 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7209 23:07:22.939020 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7210 23:07:22.942393 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7211 23:07:22.945421 [ANA_INIT] flow start
7212 23:07:22.948503 [ANA_INIT] PLL >>>>>>>>
7213 23:07:22.948582 [ANA_INIT] PLL <<<<<<<<
7214 23:07:22.952133 [ANA_INIT] MIDPI >>>>>>>>
7215 23:07:22.955093 [ANA_INIT] MIDPI <<<<<<<<
7216 23:07:22.958355 [ANA_INIT] DLL >>>>>>>>
7217 23:07:22.958435 [ANA_INIT] DLL <<<<<<<<
7218 23:07:22.962222 [ANA_INIT] flow end
7219 23:07:22.965358 ============ LP4 DIFF to SE enter ============
7220 23:07:22.968539 ============ LP4 DIFF to SE exit ============
7221 23:07:22.972101 [ANA_INIT] <<<<<<<<<<<<<
7222 23:07:22.975021 [Flow] Enable top DCM control >>>>>
7223 23:07:22.978643 [Flow] Enable top DCM control <<<<<
7224 23:07:22.981848 Enable DLL master slave shuffle
7225 23:07:22.988196 ==============================================================
7226 23:07:22.988314 Gating Mode config
7227 23:07:22.994947 ==============================================================
7228 23:07:22.995027 Config description:
7229 23:07:23.005314 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7230 23:07:23.011697 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7231 23:07:23.018029 SELPH_MODE 0: By rank 1: By Phase
7232 23:07:23.021462 ==============================================================
7233 23:07:23.024583 GAT_TRACK_EN = 1
7234 23:07:23.028155 RX_GATING_MODE = 2
7235 23:07:23.031558 RX_GATING_TRACK_MODE = 2
7236 23:07:23.034795 SELPH_MODE = 1
7237 23:07:23.037999 PICG_EARLY_EN = 1
7238 23:07:23.041181 VALID_LAT_VALUE = 1
7239 23:07:23.047743 ==============================================================
7240 23:07:23.051307 Enter into Gating configuration >>>>
7241 23:07:23.054763 Exit from Gating configuration <<<<
7242 23:07:23.058045 Enter into DVFS_PRE_config >>>>>
7243 23:07:23.068002 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7244 23:07:23.070872 Exit from DVFS_PRE_config <<<<<
7245 23:07:23.074510 Enter into PICG configuration >>>>
7246 23:07:23.077685 Exit from PICG configuration <<<<
7247 23:07:23.081120 [RX_INPUT] configuration >>>>>
7248 23:07:23.081204 [RX_INPUT] configuration <<<<<
7249 23:07:23.087720 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7250 23:07:23.094089 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7251 23:07:23.097354 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7252 23:07:23.103908 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7253 23:07:23.110348 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7254 23:07:23.117209 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7255 23:07:23.120853 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7256 23:07:23.123923 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7257 23:07:23.130418 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7258 23:07:23.133551 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7259 23:07:23.137156 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7260 23:07:23.143849 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7261 23:07:23.146934 ===================================
7262 23:07:23.147014 LPDDR4 DRAM CONFIGURATION
7263 23:07:23.150183 ===================================
7264 23:07:23.153501 EX_ROW_EN[0] = 0x0
7265 23:07:23.153580 EX_ROW_EN[1] = 0x0
7266 23:07:23.156954 LP4Y_EN = 0x0
7267 23:07:23.160103 WORK_FSP = 0x1
7268 23:07:23.160184 WL = 0x5
7269 23:07:23.163626 RL = 0x5
7270 23:07:23.163706 BL = 0x2
7271 23:07:23.166954 RPST = 0x0
7272 23:07:23.167033 RD_PRE = 0x0
7273 23:07:23.170575 WR_PRE = 0x1
7274 23:07:23.170654 WR_PST = 0x1
7275 23:07:23.173460 DBI_WR = 0x0
7276 23:07:23.173540 DBI_RD = 0x0
7277 23:07:23.176678 OTF = 0x1
7278 23:07:23.180124 ===================================
7279 23:07:23.183439 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7280 23:07:23.186691 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7281 23:07:23.193235 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7282 23:07:23.196594 ===================================
7283 23:07:23.196683 LPDDR4 DRAM CONFIGURATION
7284 23:07:23.199813 ===================================
7285 23:07:23.203534 EX_ROW_EN[0] = 0x10
7286 23:07:23.206824 EX_ROW_EN[1] = 0x0
7287 23:07:23.206903 LP4Y_EN = 0x0
7288 23:07:23.210015 WORK_FSP = 0x1
7289 23:07:23.210095 WL = 0x5
7290 23:07:23.213037 RL = 0x5
7291 23:07:23.213137 BL = 0x2
7292 23:07:23.216729 RPST = 0x0
7293 23:07:23.216809 RD_PRE = 0x0
7294 23:07:23.219482 WR_PRE = 0x1
7295 23:07:23.219561 WR_PST = 0x1
7296 23:07:23.222966 DBI_WR = 0x0
7297 23:07:23.223046 DBI_RD = 0x0
7298 23:07:23.226526 OTF = 0x1
7299 23:07:23.229525 ===================================
7300 23:07:23.236344 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7301 23:07:23.236424 ==
7302 23:07:23.239388 Dram Type= 6, Freq= 0, CH_0, rank 0
7303 23:07:23.242680 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7304 23:07:23.242760 ==
7305 23:07:23.246362 [Duty_Offset_Calibration]
7306 23:07:23.246441 B0:2 B1:0 CA:3
7307 23:07:23.246504
7308 23:07:23.249780 [DutyScan_Calibration_Flow] k_type=0
7309 23:07:23.259988
7310 23:07:23.260067 ==CLK 0==
7311 23:07:23.263013 Final CLK duty delay cell = 0
7312 23:07:23.266263 [0] MAX Duty = 5031%(X100), DQS PI = 12
7313 23:07:23.270140 [0] MIN Duty = 4907%(X100), DQS PI = 6
7314 23:07:23.270220 [0] AVG Duty = 4969%(X100)
7315 23:07:23.273467
7316 23:07:23.276605 CH0 CLK Duty spec in!! Max-Min= 124%
7317 23:07:23.279984 [DutyScan_Calibration_Flow] ====Done====
7318 23:07:23.280064
7319 23:07:23.282986 [DutyScan_Calibration_Flow] k_type=1
7320 23:07:23.299931
7321 23:07:23.300010 ==DQS 0 ==
7322 23:07:23.303423 Final DQS duty delay cell = 0
7323 23:07:23.306534 [0] MAX Duty = 5125%(X100), DQS PI = 30
7324 23:07:23.309749 [0] MIN Duty = 4875%(X100), DQS PI = 48
7325 23:07:23.312960 [0] AVG Duty = 5000%(X100)
7326 23:07:23.313040
7327 23:07:23.313103 ==DQS 1 ==
7328 23:07:23.316637 Final DQS duty delay cell = 0
7329 23:07:23.319809 [0] MAX Duty = 5156%(X100), DQS PI = 32
7330 23:07:23.323045 [0] MIN Duty = 5031%(X100), DQS PI = 12
7331 23:07:23.326378 [0] AVG Duty = 5093%(X100)
7332 23:07:23.326458
7333 23:07:23.329907 CH0 DQS 0 Duty spec in!! Max-Min= 250%
7334 23:07:23.329986
7335 23:07:23.332780 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7336 23:07:23.336504 [DutyScan_Calibration_Flow] ====Done====
7337 23:07:23.336583
7338 23:07:23.339442 [DutyScan_Calibration_Flow] k_type=3
7339 23:07:23.357739
7340 23:07:23.357819 ==DQM 0 ==
7341 23:07:23.361066 Final DQM duty delay cell = 0
7342 23:07:23.364294 [0] MAX Duty = 5156%(X100), DQS PI = 14
7343 23:07:23.367749 [0] MIN Duty = 4875%(X100), DQS PI = 0
7344 23:07:23.371171 [0] AVG Duty = 5015%(X100)
7345 23:07:23.371284
7346 23:07:23.371349 ==DQM 1 ==
7347 23:07:23.374558 Final DQM duty delay cell = 4
7348 23:07:23.378090 [4] MAX Duty = 5187%(X100), DQS PI = 60
7349 23:07:23.381296 [4] MIN Duty = 5000%(X100), DQS PI = 14
7350 23:07:23.384160 [4] AVG Duty = 5093%(X100)
7351 23:07:23.384278
7352 23:07:23.388089 CH0 DQM 0 Duty spec in!! Max-Min= 281%
7353 23:07:23.388168
7354 23:07:23.391171 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7355 23:07:23.394530 [DutyScan_Calibration_Flow] ====Done====
7356 23:07:23.394610
7357 23:07:23.397710 [DutyScan_Calibration_Flow] k_type=2
7358 23:07:23.414156
7359 23:07:23.414235 ==DQ 0 ==
7360 23:07:23.417363 Final DQ duty delay cell = -4
7361 23:07:23.421169 [-4] MAX Duty = 5000%(X100), DQS PI = 14
7362 23:07:23.424044 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7363 23:07:23.427362 [-4] AVG Duty = 4938%(X100)
7364 23:07:23.427433
7365 23:07:23.427493 ==DQ 1 ==
7366 23:07:23.430548 Final DQ duty delay cell = 0
7367 23:07:23.434078 [0] MAX Duty = 5156%(X100), DQS PI = 60
7368 23:07:23.437234 [0] MIN Duty = 5000%(X100), DQS PI = 16
7369 23:07:23.440683 [0] AVG Duty = 5078%(X100)
7370 23:07:23.440761
7371 23:07:23.443911 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7372 23:07:23.443990
7373 23:07:23.447449 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7374 23:07:23.450856 [DutyScan_Calibration_Flow] ====Done====
7375 23:07:23.450934 ==
7376 23:07:23.453701 Dram Type= 6, Freq= 0, CH_1, rank 0
7377 23:07:23.456993 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7378 23:07:23.457073 ==
7379 23:07:23.460229 [Duty_Offset_Calibration]
7380 23:07:23.460308 B0:1 B1:-2 CA:0
7381 23:07:23.460370
7382 23:07:23.464075 [DutyScan_Calibration_Flow] k_type=0
7383 23:07:23.474896
7384 23:07:23.474984 ==CLK 0==
7385 23:07:23.478319 Final CLK duty delay cell = 0
7386 23:07:23.481528 [0] MAX Duty = 5093%(X100), DQS PI = 22
7387 23:07:23.484703 [0] MIN Duty = 4844%(X100), DQS PI = 2
7388 23:07:23.484782 [0] AVG Duty = 4968%(X100)
7389 23:07:23.487986
7390 23:07:23.491473 CH1 CLK Duty spec in!! Max-Min= 249%
7391 23:07:23.494656 [DutyScan_Calibration_Flow] ====Done====
7392 23:07:23.494734
7393 23:07:23.497902 [DutyScan_Calibration_Flow] k_type=1
7394 23:07:23.514332
7395 23:07:23.514412 ==DQS 0 ==
7396 23:07:23.517694 Final DQS duty delay cell = 0
7397 23:07:23.521091 [0] MAX Duty = 5187%(X100), DQS PI = 24
7398 23:07:23.524350 [0] MIN Duty = 5062%(X100), DQS PI = 0
7399 23:07:23.527929 [0] AVG Duty = 5124%(X100)
7400 23:07:23.528008
7401 23:07:23.528070 ==DQS 1 ==
7402 23:07:23.530934 Final DQS duty delay cell = 0
7403 23:07:23.534839 [0] MAX Duty = 5124%(X100), DQS PI = 62
7404 23:07:23.538023 [0] MIN Duty = 4844%(X100), DQS PI = 24
7405 23:07:23.541176 [0] AVG Duty = 4984%(X100)
7406 23:07:23.541255
7407 23:07:23.544552 CH1 DQS 0 Duty spec in!! Max-Min= 125%
7408 23:07:23.544632
7409 23:07:23.547558 CH1 DQS 1 Duty spec in!! Max-Min= 280%
7410 23:07:23.550951 [DutyScan_Calibration_Flow] ====Done====
7411 23:07:23.551031
7412 23:07:23.554235 [DutyScan_Calibration_Flow] k_type=3
7413 23:07:23.571631
7414 23:07:23.571711 ==DQM 0 ==
7415 23:07:23.574910 Final DQM duty delay cell = 0
7416 23:07:23.577859 [0] MAX Duty = 5031%(X100), DQS PI = 26
7417 23:07:23.581474 [0] MIN Duty = 4813%(X100), DQS PI = 54
7418 23:07:23.584440 [0] AVG Duty = 4922%(X100)
7419 23:07:23.584519
7420 23:07:23.584581 ==DQM 1 ==
7421 23:07:23.587905 Final DQM duty delay cell = 0
7422 23:07:23.591594 [0] MAX Duty = 5093%(X100), DQS PI = 36
7423 23:07:23.594842 [0] MIN Duty = 4875%(X100), DQS PI = 24
7424 23:07:23.598062 [0] AVG Duty = 4984%(X100)
7425 23:07:23.598141
7426 23:07:23.601434 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7427 23:07:23.601513
7428 23:07:23.604623 CH1 DQM 1 Duty spec in!! Max-Min= 218%
7429 23:07:23.608092 [DutyScan_Calibration_Flow] ====Done====
7430 23:07:23.608171
7431 23:07:23.610995 [DutyScan_Calibration_Flow] k_type=2
7432 23:07:23.628114
7433 23:07:23.628194 ==DQ 0 ==
7434 23:07:23.631536 Final DQ duty delay cell = 0
7435 23:07:23.634759 [0] MAX Duty = 5093%(X100), DQS PI = 22
7436 23:07:23.638124 [0] MIN Duty = 4907%(X100), DQS PI = 0
7437 23:07:23.638204 [0] AVG Duty = 5000%(X100)
7438 23:07:23.638266
7439 23:07:23.641697 ==DQ 1 ==
7440 23:07:23.644823 Final DQ duty delay cell = 0
7441 23:07:23.648504 [0] MAX Duty = 5125%(X100), DQS PI = 34
7442 23:07:23.651257 [0] MIN Duty = 4969%(X100), DQS PI = 24
7443 23:07:23.651336 [0] AVG Duty = 5047%(X100)
7444 23:07:23.654764
7445 23:07:23.657881 CH1 DQ 0 Duty spec in!! Max-Min= 186%
7446 23:07:23.657960
7447 23:07:23.661437 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7448 23:07:23.664539 [DutyScan_Calibration_Flow] ====Done====
7449 23:07:23.667781 nWR fixed to 30
7450 23:07:23.667861 [ModeRegInit_LP4] CH0 RK0
7451 23:07:23.671599 [ModeRegInit_LP4] CH0 RK1
7452 23:07:23.674686 [ModeRegInit_LP4] CH1 RK0
7453 23:07:23.677894 [ModeRegInit_LP4] CH1 RK1
7454 23:07:23.677974 match AC timing 5
7455 23:07:23.684667 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7456 23:07:23.687883 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7457 23:07:23.690844 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7458 23:07:23.697412 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7459 23:07:23.700592 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7460 23:07:23.700686 [MiockJmeterHQA]
7461 23:07:23.700764
7462 23:07:23.704133 [DramcMiockJmeter] u1RxGatingPI = 0
7463 23:07:23.707283 0 : 4255, 4030
7464 23:07:23.707367 4 : 4252, 4027
7465 23:07:23.711484 8 : 4257, 4029
7466 23:07:23.711567 12 : 4252, 4027
7467 23:07:23.714141 16 : 4253, 4027
7468 23:07:23.714225 20 : 4363, 4137
7469 23:07:23.714310 24 : 4252, 4027
7470 23:07:23.717465 28 : 4362, 4137
7471 23:07:23.717548 32 : 4252, 4027
7472 23:07:23.721138 36 : 4252, 4027
7473 23:07:23.721222 40 : 4252, 4027
7474 23:07:23.724114 44 : 4255, 4029
7475 23:07:23.724199 48 : 4252, 4027
7476 23:07:23.724322 52 : 4253, 4026
7477 23:07:23.727184 56 : 4365, 4140
7478 23:07:23.727268 60 : 4252, 4029
7479 23:07:23.731175 64 : 4252, 4029
7480 23:07:23.731259 68 : 4249, 4027
7481 23:07:23.734005 72 : 4361, 4137
7482 23:07:23.734089 76 : 4250, 4027
7483 23:07:23.737398 80 : 4360, 4138
7484 23:07:23.737482 84 : 4250, 4027
7485 23:07:23.737566 88 : 4250, 4027
7486 23:07:23.740646 92 : 4252, 4029
7487 23:07:23.740730 96 : 4252, 4029
7488 23:07:23.743900 100 : 4361, 4138
7489 23:07:23.743984 104 : 4252, 3733
7490 23:07:23.746942 108 : 4250, 8
7491 23:07:23.747025 112 : 4361, 0
7492 23:07:23.750217 116 : 4360, 0
7493 23:07:23.750300 120 : 4247, 0
7494 23:07:23.750384 124 : 4253, 0
7495 23:07:23.753710 128 : 4250, 0
7496 23:07:23.753793 132 : 4250, 0
7497 23:07:23.753878 136 : 4250, 0
7498 23:07:23.757235 140 : 4249, 0
7499 23:07:23.757319 144 : 4250, 0
7500 23:07:23.760160 148 : 4250, 0
7501 23:07:23.760268 152 : 4361, 0
7502 23:07:23.760352 156 : 4361, 0
7503 23:07:23.763768 160 : 4250, 0
7504 23:07:23.763852 164 : 4250, 0
7505 23:07:23.766759 168 : 4249, 0
7506 23:07:23.766843 172 : 4250, 0
7507 23:07:23.766927 176 : 4250, 0
7508 23:07:23.770030 180 : 4250, 0
7509 23:07:23.770114 184 : 4250, 0
7510 23:07:23.773751 188 : 4361, 0
7511 23:07:23.773835 192 : 4249, 0
7512 23:07:23.773919 196 : 4250, 0
7513 23:07:23.777032 200 : 4250, 0
7514 23:07:23.777116 204 : 4360, 0
7515 23:07:23.780098 208 : 4360, 0
7516 23:07:23.780182 212 : 4250, 0
7517 23:07:23.780306 216 : 4250, 0
7518 23:07:23.783455 220 : 4250, 0
7519 23:07:23.783538 224 : 4250, 0
7520 23:07:23.783623 228 : 4250, 0
7521 23:07:23.786913 232 : 4249, 0
7522 23:07:23.786996 236 : 4250, 838
7523 23:07:23.789877 240 : 4250, 4027
7524 23:07:23.789961 244 : 4250, 4027
7525 23:07:23.793181 248 : 4250, 4027
7526 23:07:23.793265 252 : 4250, 4027
7527 23:07:23.797098 256 : 4250, 4027
7528 23:07:23.797181 260 : 4250, 4026
7529 23:07:23.800228 264 : 4250, 4027
7530 23:07:23.800326 268 : 4250, 4027
7531 23:07:23.803071 272 : 4249, 4027
7532 23:07:23.803155 276 : 4361, 4137
7533 23:07:23.803241 280 : 4361, 4137
7534 23:07:23.806502 284 : 4250, 4027
7535 23:07:23.806586 288 : 4360, 4138
7536 23:07:23.809819 292 : 4249, 4027
7537 23:07:23.809903 296 : 4253, 4026
7538 23:07:23.813338 300 : 4250, 4027
7539 23:07:23.813422 304 : 4250, 4027
7540 23:07:23.816612 308 : 4250, 4027
7541 23:07:23.816696 312 : 4250, 4026
7542 23:07:23.819968 316 : 4250, 4027
7543 23:07:23.820074 320 : 4250, 4027
7544 23:07:23.823291 324 : 4249, 4027
7545 23:07:23.823402 328 : 4361, 4137
7546 23:07:23.826461 332 : 4361, 4137
7547 23:07:23.826557 336 : 4250, 4027
7548 23:07:23.826658 340 : 4360, 4138
7549 23:07:23.829672 344 : 4249, 4027
7550 23:07:23.829780 348 : 4250, 4026
7551 23:07:23.833172 352 : 4250, 4020
7552 23:07:23.833263 356 : 4250, 2803
7553 23:07:23.836421 360 : 4250, 2
7554 23:07:23.836490
7555 23:07:23.836550 MIOCK jitter meter ch=0
7556 23:07:23.839447
7557 23:07:23.839548 1T = (360-108) = 252 dly cells
7558 23:07:23.846267 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7559 23:07:23.846339 ==
7560 23:07:23.849553 Dram Type= 6, Freq= 0, CH_0, rank 0
7561 23:07:23.852792 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7562 23:07:23.852861 ==
7563 23:07:23.859463 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7564 23:07:23.862957 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7565 23:07:23.869133 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7566 23:07:23.872479 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7567 23:07:23.883024 [CA 0] Center 43 (13~74) winsize 62
7568 23:07:23.886197 [CA 1] Center 43 (13~74) winsize 62
7569 23:07:23.889540 [CA 2] Center 39 (10~68) winsize 59
7570 23:07:23.893138 [CA 3] Center 39 (10~68) winsize 59
7571 23:07:23.896149 [CA 4] Center 36 (7~66) winsize 60
7572 23:07:23.899385 [CA 5] Center 36 (7~66) winsize 60
7573 23:07:23.899468
7574 23:07:23.902601 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7575 23:07:23.902684
7576 23:07:23.909836 [CATrainingPosCal] consider 1 rank data
7577 23:07:23.909919 u2DelayCellTimex100 = 258/100 ps
7578 23:07:23.916018 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7579 23:07:23.919300 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7580 23:07:23.922919 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7581 23:07:23.926022 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7582 23:07:23.929097 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7583 23:07:23.932520 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7584 23:07:23.932602
7585 23:07:23.935916 CA PerBit enable=1, Macro0, CA PI delay=36
7586 23:07:23.935998
7587 23:07:23.939138 [CBTSetCACLKResult] CA Dly = 36
7588 23:07:23.942094 CS Dly: 11 (0~42)
7589 23:07:23.945391 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7590 23:07:23.948913 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7591 23:07:23.952154 ==
7592 23:07:23.952289 Dram Type= 6, Freq= 0, CH_0, rank 1
7593 23:07:23.958987 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7594 23:07:23.959071 ==
7595 23:07:23.962174 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7596 23:07:23.968956 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7597 23:07:23.971997 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7598 23:07:23.978964 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7599 23:07:23.987290 [CA 0] Center 43 (13~74) winsize 62
7600 23:07:23.990597 [CA 1] Center 43 (13~74) winsize 62
7601 23:07:23.993679 [CA 2] Center 39 (10~68) winsize 59
7602 23:07:23.996933 [CA 3] Center 39 (10~68) winsize 59
7603 23:07:24.000305 [CA 4] Center 36 (7~66) winsize 60
7604 23:07:24.003714 [CA 5] Center 36 (7~66) winsize 60
7605 23:07:24.003797
7606 23:07:24.006735 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7607 23:07:24.006817
7608 23:07:24.013410 [CATrainingPosCal] consider 2 rank data
7609 23:07:24.013493 u2DelayCellTimex100 = 258/100 ps
7610 23:07:24.020054 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7611 23:07:24.023328 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7612 23:07:24.026992 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7613 23:07:24.030325 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7614 23:07:24.033813 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7615 23:07:24.036951 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7616 23:07:24.037033
7617 23:07:24.040114 CA PerBit enable=1, Macro0, CA PI delay=36
7618 23:07:24.040197
7619 23:07:24.043386 [CBTSetCACLKResult] CA Dly = 36
7620 23:07:24.046675 CS Dly: 11 (0~43)
7621 23:07:24.050082 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7622 23:07:24.053521 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7623 23:07:24.053603
7624 23:07:24.056563 ----->DramcWriteLeveling(PI) begin...
7625 23:07:24.056647 ==
7626 23:07:24.060136 Dram Type= 6, Freq= 0, CH_0, rank 0
7627 23:07:24.066486 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7628 23:07:24.066602 ==
7629 23:07:24.069828 Write leveling (Byte 0): 34 => 34
7630 23:07:24.073281 Write leveling (Byte 1): 28 => 28
7631 23:07:24.073364 DramcWriteLeveling(PI) end<-----
7632 23:07:24.076216
7633 23:07:24.076313 ==
7634 23:07:24.080035 Dram Type= 6, Freq= 0, CH_0, rank 0
7635 23:07:24.083477 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7636 23:07:24.083560 ==
7637 23:07:24.086422 [Gating] SW mode calibration
7638 23:07:24.092765 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7639 23:07:24.096186 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7640 23:07:24.102748 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7641 23:07:24.106180 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7642 23:07:24.109502 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7643 23:07:24.116319 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7644 23:07:24.119500 1 4 16 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
7645 23:07:24.122724 1 4 20 | B1->B0 | 2323 3433 | 1 1 | (1 1) (1 1)
7646 23:07:24.129286 1 4 24 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
7647 23:07:24.133080 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7648 23:07:24.136393 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7649 23:07:24.142590 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7650 23:07:24.145874 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7651 23:07:24.149442 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7652 23:07:24.156047 1 5 16 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 1)
7653 23:07:24.159211 1 5 20 | B1->B0 | 3232 2323 | 0 0 | (0 0) (0 0)
7654 23:07:24.162580 1 5 24 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
7655 23:07:24.169384 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7656 23:07:24.172794 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7657 23:07:24.175969 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7658 23:07:24.182764 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7659 23:07:24.185794 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7660 23:07:24.189704 1 6 16 | B1->B0 | 2323 3d3d | 0 1 | (0 0) (0 0)
7661 23:07:24.195771 1 6 20 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
7662 23:07:24.199541 1 6 24 | B1->B0 | 4443 4646 | 1 0 | (0 0) (0 0)
7663 23:07:24.202232 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7664 23:07:24.209021 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7665 23:07:24.212310 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7666 23:07:24.215671 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7667 23:07:24.222202 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7668 23:07:24.225677 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7669 23:07:24.228809 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7670 23:07:24.235336 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7671 23:07:24.238858 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7672 23:07:24.242051 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7673 23:07:24.248798 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7674 23:07:24.251956 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7675 23:07:24.255446 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7676 23:07:24.261648 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7677 23:07:24.265402 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7678 23:07:24.268091 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7679 23:07:24.275008 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7680 23:07:24.278461 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7681 23:07:24.281405 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7682 23:07:24.288024 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7683 23:07:24.291735 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7684 23:07:24.294770 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7685 23:07:24.301382 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7686 23:07:24.304801 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7687 23:07:24.308144 Total UI for P1: 0, mck2ui 16
7688 23:07:24.311313 best dqsien dly found for B0: ( 1, 9, 16)
7689 23:07:24.314546 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7690 23:07:24.318284 Total UI for P1: 0, mck2ui 16
7691 23:07:24.321517 best dqsien dly found for B1: ( 1, 9, 24)
7692 23:07:24.324734 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
7693 23:07:24.328045 best DQS1 dly(MCK, UI, PI) = (1, 9, 24)
7694 23:07:24.328127
7695 23:07:24.331415 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
7696 23:07:24.337745 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 24)
7697 23:07:24.337828 [Gating] SW calibration Done
7698 23:07:24.340985 ==
7699 23:07:24.344388 Dram Type= 6, Freq= 0, CH_0, rank 0
7700 23:07:24.347487 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7701 23:07:24.347571 ==
7702 23:07:24.347655 RX Vref Scan: 0
7703 23:07:24.347733
7704 23:07:24.350981 RX Vref 0 -> 0, step: 1
7705 23:07:24.351063
7706 23:07:24.354158 RX Delay 0 -> 252, step: 8
7707 23:07:24.357925 iDelay=192, Bit 0, Center 127 (72 ~ 183) 112
7708 23:07:24.360930 iDelay=192, Bit 1, Center 131 (80 ~ 183) 104
7709 23:07:24.364148 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7710 23:07:24.370770 iDelay=192, Bit 3, Center 119 (64 ~ 175) 112
7711 23:07:24.374033 iDelay=192, Bit 4, Center 127 (72 ~ 183) 112
7712 23:07:24.377636 iDelay=192, Bit 5, Center 111 (56 ~ 167) 112
7713 23:07:24.381150 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7714 23:07:24.383811 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7715 23:07:24.391013 iDelay=192, Bit 8, Center 115 (56 ~ 175) 120
7716 23:07:24.394281 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7717 23:07:24.397249 iDelay=192, Bit 10, Center 123 (64 ~ 183) 120
7718 23:07:24.400543 iDelay=192, Bit 11, Center 119 (64 ~ 175) 112
7719 23:07:24.407499 iDelay=192, Bit 12, Center 127 (72 ~ 183) 112
7720 23:07:24.410362 iDelay=192, Bit 13, Center 131 (72 ~ 191) 120
7721 23:07:24.413721 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7722 23:07:24.416989 iDelay=192, Bit 15, Center 127 (72 ~ 183) 112
7723 23:07:24.417081 ==
7724 23:07:24.420237 Dram Type= 6, Freq= 0, CH_0, rank 0
7725 23:07:24.426663 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7726 23:07:24.426747 ==
7727 23:07:24.426831 DQS Delay:
7728 23:07:24.430083 DQS0 = 0, DQS1 = 0
7729 23:07:24.430165 DQM Delay:
7730 23:07:24.430249 DQM0 = 127, DQM1 = 123
7731 23:07:24.433159 DQ Delay:
7732 23:07:24.436784 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =119
7733 23:07:24.439921 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =139
7734 23:07:24.443091 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =119
7735 23:07:24.446427 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =127
7736 23:07:24.446510
7737 23:07:24.446593
7738 23:07:24.446671 ==
7739 23:07:24.450103 Dram Type= 6, Freq= 0, CH_0, rank 0
7740 23:07:24.453438 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7741 23:07:24.456805 ==
7742 23:07:24.456911
7743 23:07:24.456995
7744 23:07:24.457074 TX Vref Scan disable
7745 23:07:24.459735 == TX Byte 0 ==
7746 23:07:24.463410 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7747 23:07:24.469910 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7748 23:07:24.469993 == TX Byte 1 ==
7749 23:07:24.472937 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7750 23:07:24.479283 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7751 23:07:24.479366 ==
7752 23:07:24.482743 Dram Type= 6, Freq= 0, CH_0, rank 0
7753 23:07:24.486139 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7754 23:07:24.486249 ==
7755 23:07:24.499205
7756 23:07:24.502739 TX Vref early break, caculate TX vref
7757 23:07:24.505901 TX Vref=16, minBit 8, minWin=21, winSum=354
7758 23:07:24.508988 TX Vref=18, minBit 8, minWin=21, winSum=364
7759 23:07:24.512791 TX Vref=20, minBit 0, minWin=23, winSum=375
7760 23:07:24.516090 TX Vref=22, minBit 7, minWin=23, winSum=385
7761 23:07:24.518931 TX Vref=24, minBit 8, minWin=23, winSum=394
7762 23:07:24.525698 TX Vref=26, minBit 0, minWin=24, winSum=402
7763 23:07:24.528993 TX Vref=28, minBit 0, minWin=24, winSum=404
7764 23:07:24.532219 TX Vref=30, minBit 8, minWin=23, winSum=392
7765 23:07:24.535288 TX Vref=32, minBit 8, minWin=23, winSum=387
7766 23:07:24.539022 TX Vref=34, minBit 8, minWin=22, winSum=380
7767 23:07:24.545494 [TxChooseVref] Worse bit 0, Min win 24, Win sum 404, Final Vref 28
7768 23:07:24.545581
7769 23:07:24.548725 Final TX Range 0 Vref 28
7770 23:07:24.548805
7771 23:07:24.548875 ==
7772 23:07:24.551909 Dram Type= 6, Freq= 0, CH_0, rank 0
7773 23:07:24.555223 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7774 23:07:24.555304 ==
7775 23:07:24.555368
7776 23:07:24.555426
7777 23:07:24.558567 TX Vref Scan disable
7778 23:07:24.565021 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7779 23:07:24.565121 == TX Byte 0 ==
7780 23:07:24.568680 u2DelayCellOfst[0]=15 cells (4 PI)
7781 23:07:24.571666 u2DelayCellOfst[1]=18 cells (5 PI)
7782 23:07:24.574917 u2DelayCellOfst[2]=15 cells (4 PI)
7783 23:07:24.578670 u2DelayCellOfst[3]=15 cells (4 PI)
7784 23:07:24.582179 u2DelayCellOfst[4]=11 cells (3 PI)
7785 23:07:24.584981 u2DelayCellOfst[5]=0 cells (0 PI)
7786 23:07:24.588603 u2DelayCellOfst[6]=22 cells (6 PI)
7787 23:07:24.591597 u2DelayCellOfst[7]=22 cells (6 PI)
7788 23:07:24.594752 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7789 23:07:24.598419 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7790 23:07:24.601933 == TX Byte 1 ==
7791 23:07:24.605090 u2DelayCellOfst[8]=0 cells (0 PI)
7792 23:07:24.608021 u2DelayCellOfst[9]=3 cells (1 PI)
7793 23:07:24.608104 u2DelayCellOfst[10]=7 cells (2 PI)
7794 23:07:24.611478 u2DelayCellOfst[11]=7 cells (2 PI)
7795 23:07:24.614855 u2DelayCellOfst[12]=15 cells (4 PI)
7796 23:07:24.618263 u2DelayCellOfst[13]=11 cells (3 PI)
7797 23:07:24.621250 u2DelayCellOfst[14]=15 cells (4 PI)
7798 23:07:24.624720 u2DelayCellOfst[15]=11 cells (3 PI)
7799 23:07:24.631078 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7800 23:07:24.634401 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7801 23:07:24.634484 DramC Write-DBI on
7802 23:07:24.634568 ==
7803 23:07:24.637949 Dram Type= 6, Freq= 0, CH_0, rank 0
7804 23:07:24.644534 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7805 23:07:24.644617 ==
7806 23:07:24.644701
7807 23:07:24.644780
7808 23:07:24.647624 TX Vref Scan disable
7809 23:07:24.647706 == TX Byte 0 ==
7810 23:07:24.654474 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7811 23:07:24.654602 == TX Byte 1 ==
7812 23:07:24.657563 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7813 23:07:24.660879 DramC Write-DBI off
7814 23:07:24.660958
7815 23:07:24.661021 [DATLAT]
7816 23:07:24.664164 Freq=1600, CH0 RK0
7817 23:07:24.664283
7818 23:07:24.664347 DATLAT Default: 0xf
7819 23:07:24.667485 0, 0xFFFF, sum = 0
7820 23:07:24.667567 1, 0xFFFF, sum = 0
7821 23:07:24.671005 2, 0xFFFF, sum = 0
7822 23:07:24.671087 3, 0xFFFF, sum = 0
7823 23:07:24.674142 4, 0xFFFF, sum = 0
7824 23:07:24.674223 5, 0xFFFF, sum = 0
7825 23:07:24.677481 6, 0xFFFF, sum = 0
7826 23:07:24.677606 7, 0xFFFF, sum = 0
7827 23:07:24.681392 8, 0xFFFF, sum = 0
7828 23:07:24.681473 9, 0xFFFF, sum = 0
7829 23:07:24.684104 10, 0xFFFF, sum = 0
7830 23:07:24.687671 11, 0xFFFF, sum = 0
7831 23:07:24.687755 12, 0xFFFF, sum = 0
7832 23:07:24.690746 13, 0xFFFF, sum = 0
7833 23:07:24.690830 14, 0x0, sum = 1
7834 23:07:24.694628 15, 0x0, sum = 2
7835 23:07:24.694711 16, 0x0, sum = 3
7836 23:07:24.697228 17, 0x0, sum = 4
7837 23:07:24.697311 best_step = 15
7838 23:07:24.697394
7839 23:07:24.697473 ==
7840 23:07:24.700511 Dram Type= 6, Freq= 0, CH_0, rank 0
7841 23:07:24.703776 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7842 23:07:24.703859 ==
7843 23:07:24.707609 RX Vref Scan: 1
7844 23:07:24.707691
7845 23:07:24.710529 Set Vref Range= 24 -> 127
7846 23:07:24.710611
7847 23:07:24.710698 RX Vref 24 -> 127, step: 1
7848 23:07:24.710778
7849 23:07:24.714092 RX Delay 11 -> 252, step: 4
7850 23:07:24.714172
7851 23:07:24.717631 Set Vref, RX VrefLevel [Byte0]: 24
7852 23:07:24.721002 [Byte1]: 24
7853 23:07:24.723987
7854 23:07:24.724066 Set Vref, RX VrefLevel [Byte0]: 25
7855 23:07:24.727050 [Byte1]: 25
7856 23:07:24.731401
7857 23:07:24.731481 Set Vref, RX VrefLevel [Byte0]: 26
7858 23:07:24.735021 [Byte1]: 26
7859 23:07:24.739124
7860 23:07:24.739235 Set Vref, RX VrefLevel [Byte0]: 27
7861 23:07:24.742341 [Byte1]: 27
7862 23:07:24.746970
7863 23:07:24.747134 Set Vref, RX VrefLevel [Byte0]: 28
7864 23:07:24.750269 [Byte1]: 28
7865 23:07:24.754393
7866 23:07:24.754560 Set Vref, RX VrefLevel [Byte0]: 29
7867 23:07:24.757690 [Byte1]: 29
7868 23:07:24.761977
7869 23:07:24.762083 Set Vref, RX VrefLevel [Byte0]: 30
7870 23:07:24.765071 [Byte1]: 30
7871 23:07:24.769471
7872 23:07:24.769551 Set Vref, RX VrefLevel [Byte0]: 31
7873 23:07:24.772643 [Byte1]: 31
7874 23:07:24.778023
7875 23:07:24.778116 Set Vref, RX VrefLevel [Byte0]: 32
7876 23:07:24.780341 [Byte1]: 32
7877 23:07:24.784682
7878 23:07:24.784776 Set Vref, RX VrefLevel [Byte0]: 33
7879 23:07:24.787913 [Byte1]: 33
7880 23:07:24.792589
7881 23:07:24.792668 Set Vref, RX VrefLevel [Byte0]: 34
7882 23:07:24.795716 [Byte1]: 34
7883 23:07:24.800138
7884 23:07:24.800275 Set Vref, RX VrefLevel [Byte0]: 35
7885 23:07:24.803429 [Byte1]: 35
7886 23:07:24.807652
7887 23:07:24.807732 Set Vref, RX VrefLevel [Byte0]: 36
7888 23:07:24.810767 [Byte1]: 36
7889 23:07:24.815487
7890 23:07:24.815567 Set Vref, RX VrefLevel [Byte0]: 37
7891 23:07:24.818766 [Byte1]: 37
7892 23:07:24.823151
7893 23:07:24.823273 Set Vref, RX VrefLevel [Byte0]: 38
7894 23:07:24.826143 [Byte1]: 38
7895 23:07:24.830864
7896 23:07:24.830944 Set Vref, RX VrefLevel [Byte0]: 39
7897 23:07:24.833587 [Byte1]: 39
7898 23:07:24.837976
7899 23:07:24.838056 Set Vref, RX VrefLevel [Byte0]: 40
7900 23:07:24.841190 [Byte1]: 40
7901 23:07:24.845802
7902 23:07:24.845882 Set Vref, RX VrefLevel [Byte0]: 41
7903 23:07:24.849108 [Byte1]: 41
7904 23:07:24.853160
7905 23:07:24.853240 Set Vref, RX VrefLevel [Byte0]: 42
7906 23:07:24.856805 [Byte1]: 42
7907 23:07:24.860761
7908 23:07:24.860841 Set Vref, RX VrefLevel [Byte0]: 43
7909 23:07:24.864644 [Byte1]: 43
7910 23:07:24.868469
7911 23:07:24.868550 Set Vref, RX VrefLevel [Byte0]: 44
7912 23:07:24.871968 [Byte1]: 44
7913 23:07:24.876463
7914 23:07:24.876565 Set Vref, RX VrefLevel [Byte0]: 45
7915 23:07:24.879501 [Byte1]: 45
7916 23:07:24.883768
7917 23:07:24.883847 Set Vref, RX VrefLevel [Byte0]: 46
7918 23:07:24.887138 [Byte1]: 46
7919 23:07:24.891372
7920 23:07:24.891451 Set Vref, RX VrefLevel [Byte0]: 47
7921 23:07:24.894556 [Byte1]: 47
7922 23:07:24.898794
7923 23:07:24.898874 Set Vref, RX VrefLevel [Byte0]: 48
7924 23:07:24.902541 [Byte1]: 48
7925 23:07:24.906764
7926 23:07:24.906843 Set Vref, RX VrefLevel [Byte0]: 49
7927 23:07:24.910136 [Byte1]: 49
7928 23:07:24.913998
7929 23:07:24.914077 Set Vref, RX VrefLevel [Byte0]: 50
7930 23:07:24.917404 [Byte1]: 50
7931 23:07:24.921947
7932 23:07:24.922026 Set Vref, RX VrefLevel [Byte0]: 51
7933 23:07:24.925029 [Byte1]: 51
7934 23:07:24.929615
7935 23:07:24.929694 Set Vref, RX VrefLevel [Byte0]: 52
7936 23:07:24.932714 [Byte1]: 52
7937 23:07:24.936903
7938 23:07:24.936982 Set Vref, RX VrefLevel [Byte0]: 53
7939 23:07:24.940320 [Byte1]: 53
7940 23:07:24.944739
7941 23:07:24.944819 Set Vref, RX VrefLevel [Byte0]: 54
7942 23:07:24.947924 [Byte1]: 54
7943 23:07:24.952033
7944 23:07:24.952112 Set Vref, RX VrefLevel [Byte0]: 55
7945 23:07:24.955865 [Byte1]: 55
7946 23:07:24.959601
7947 23:07:24.959681 Set Vref, RX VrefLevel [Byte0]: 56
7948 23:07:24.962967 [Byte1]: 56
7949 23:07:24.967199
7950 23:07:24.967333 Set Vref, RX VrefLevel [Byte0]: 57
7951 23:07:24.970927 [Byte1]: 57
7952 23:07:24.975088
7953 23:07:24.975169 Set Vref, RX VrefLevel [Byte0]: 58
7954 23:07:24.978430 [Byte1]: 58
7955 23:07:24.982849
7956 23:07:24.982929 Set Vref, RX VrefLevel [Byte0]: 59
7957 23:07:24.985877 [Byte1]: 59
7958 23:07:24.990104
7959 23:07:24.990183 Set Vref, RX VrefLevel [Byte0]: 60
7960 23:07:24.993599 [Byte1]: 60
7961 23:07:24.997956
7962 23:07:24.998035 Set Vref, RX VrefLevel [Byte0]: 61
7963 23:07:25.001233 [Byte1]: 61
7964 23:07:25.005433
7965 23:07:25.005512 Set Vref, RX VrefLevel [Byte0]: 62
7966 23:07:25.008652 [Byte1]: 62
7967 23:07:25.013464
7968 23:07:25.013543 Set Vref, RX VrefLevel [Byte0]: 63
7969 23:07:25.016659 [Byte1]: 63
7970 23:07:25.021023
7971 23:07:25.021102 Set Vref, RX VrefLevel [Byte0]: 64
7972 23:07:25.024168 [Byte1]: 64
7973 23:07:25.028564
7974 23:07:25.028643 Set Vref, RX VrefLevel [Byte0]: 65
7975 23:07:25.031477 [Byte1]: 65
7976 23:07:25.035746
7977 23:07:25.035825 Set Vref, RX VrefLevel [Byte0]: 66
7978 23:07:25.039228 [Byte1]: 66
7979 23:07:25.043417
7980 23:07:25.043496 Set Vref, RX VrefLevel [Byte0]: 67
7981 23:07:25.046754 [Byte1]: 67
7982 23:07:25.051598
7983 23:07:25.051677 Set Vref, RX VrefLevel [Byte0]: 68
7984 23:07:25.054806 [Byte1]: 68
7985 23:07:25.058665
7986 23:07:25.058744 Set Vref, RX VrefLevel [Byte0]: 69
7987 23:07:25.061907 [Byte1]: 69
7988 23:07:25.066583
7989 23:07:25.066670 Set Vref, RX VrefLevel [Byte0]: 70
7990 23:07:25.069919 [Byte1]: 70
7991 23:07:25.073884
7992 23:07:25.073964 Set Vref, RX VrefLevel [Byte0]: 71
7993 23:07:25.077549 [Byte1]: 71
7994 23:07:25.081572
7995 23:07:25.081651 Set Vref, RX VrefLevel [Byte0]: 72
7996 23:07:25.084865 [Byte1]: 72
7997 23:07:25.089207
7998 23:07:25.089286 Set Vref, RX VrefLevel [Byte0]: 73
7999 23:07:25.093184 [Byte1]: 73
8000 23:07:25.097109
8001 23:07:25.097188 Set Vref, RX VrefLevel [Byte0]: 74
8002 23:07:25.100221 [Byte1]: 74
8003 23:07:25.104521
8004 23:07:25.104600 Set Vref, RX VrefLevel [Byte0]: 75
8005 23:07:25.107912 [Byte1]: 75
8006 23:07:25.111944
8007 23:07:25.112023 Set Vref, RX VrefLevel [Byte0]: 76
8008 23:07:25.115627 [Byte1]: 76
8009 23:07:25.120021
8010 23:07:25.120100 Final RX Vref Byte 0 = 64 to rank0
8011 23:07:25.122873 Final RX Vref Byte 1 = 58 to rank0
8012 23:07:25.126311 Final RX Vref Byte 0 = 64 to rank1
8013 23:07:25.129831 Final RX Vref Byte 1 = 58 to rank1==
8014 23:07:25.133405 Dram Type= 6, Freq= 0, CH_0, rank 0
8015 23:07:25.139849 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8016 23:07:25.139930 ==
8017 23:07:25.139993 DQS Delay:
8018 23:07:25.140052 DQS0 = 0, DQS1 = 0
8019 23:07:25.142929 DQM Delay:
8020 23:07:25.143008 DQM0 = 126, DQM1 = 120
8021 23:07:25.146301 DQ Delay:
8022 23:07:25.149306 DQ0 =126, DQ1 =128, DQ2 =126, DQ3 =122
8023 23:07:25.152879 DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =138
8024 23:07:25.156278 DQ8 =112, DQ9 =108, DQ10 =120, DQ11 =114
8025 23:07:25.159605 DQ12 =126, DQ13 =124, DQ14 =130, DQ15 =128
8026 23:07:25.159686
8027 23:07:25.159748
8028 23:07:25.159807
8029 23:07:25.162810 [DramC_TX_OE_Calibration] TA2
8030 23:07:25.166064 Original DQ_B0 (3 6) =30, OEN = 27
8031 23:07:25.169882 Original DQ_B1 (3 6) =30, OEN = 27
8032 23:07:25.172663 24, 0x0, End_B0=24 End_B1=24
8033 23:07:25.172744 25, 0x0, End_B0=25 End_B1=25
8034 23:07:25.176236 26, 0x0, End_B0=26 End_B1=26
8035 23:07:25.179521 27, 0x0, End_B0=27 End_B1=27
8036 23:07:25.182584 28, 0x0, End_B0=28 End_B1=28
8037 23:07:25.185931 29, 0x0, End_B0=29 End_B1=29
8038 23:07:25.186011 30, 0x0, End_B0=30 End_B1=30
8039 23:07:25.189541 31, 0x4141, End_B0=30 End_B1=30
8040 23:07:25.192575 Byte0 end_step=30 best_step=27
8041 23:07:25.195780 Byte1 end_step=30 best_step=27
8042 23:07:25.199622 Byte0 TX OE(2T, 0.5T) = (3, 3)
8043 23:07:25.202618 Byte1 TX OE(2T, 0.5T) = (3, 3)
8044 23:07:25.202698
8045 23:07:25.202761
8046 23:07:25.209661 [DQSOSCAuto] RK0, (LSB)MR18= 0x1515, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
8047 23:07:25.212894 CH0 RK0: MR19=303, MR18=1515
8048 23:07:25.219587 CH0_RK0: MR19=0x303, MR18=0x1515, DQSOSC=399, MR23=63, INC=23, DEC=15
8049 23:07:25.219674
8050 23:07:25.223002 ----->DramcWriteLeveling(PI) begin...
8051 23:07:25.223090 ==
8052 23:07:25.226116 Dram Type= 6, Freq= 0, CH_0, rank 1
8053 23:07:25.229183 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8054 23:07:25.229284 ==
8055 23:07:25.232476 Write leveling (Byte 0): 33 => 33
8056 23:07:25.235896 Write leveling (Byte 1): 27 => 27
8057 23:07:25.239424 DramcWriteLeveling(PI) end<-----
8058 23:07:25.239545
8059 23:07:25.239638 ==
8060 23:07:25.242359 Dram Type= 6, Freq= 0, CH_0, rank 1
8061 23:07:25.246223 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8062 23:07:25.246417 ==
8063 23:07:25.249344 [Gating] SW mode calibration
8064 23:07:25.256214 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8065 23:07:25.262447 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8066 23:07:25.266301 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8067 23:07:25.269282 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8068 23:07:25.275856 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8069 23:07:25.279320 1 4 12 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
8070 23:07:25.282611 1 4 16 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
8071 23:07:25.289193 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8072 23:07:25.292313 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8073 23:07:25.295970 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8074 23:07:25.302223 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8075 23:07:25.305450 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8076 23:07:25.308939 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8077 23:07:25.315757 1 5 12 | B1->B0 | 3434 2828 | 1 1 | (1 1) (1 0)
8078 23:07:25.318765 1 5 16 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
8079 23:07:25.322291 1 5 20 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
8080 23:07:25.328645 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8081 23:07:25.332094 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8082 23:07:25.335437 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8083 23:07:25.341762 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8084 23:07:25.345238 1 6 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
8085 23:07:25.348512 1 6 12 | B1->B0 | 2323 3d3d | 0 0 | (0 0) (0 0)
8086 23:07:25.355112 1 6 16 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
8087 23:07:25.358213 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8088 23:07:25.361503 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8089 23:07:25.368338 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8090 23:07:25.371938 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8091 23:07:25.375185 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8092 23:07:25.381718 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8093 23:07:25.384770 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8094 23:07:25.388353 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8095 23:07:25.394708 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8096 23:07:25.398314 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8097 23:07:25.401890 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8098 23:07:25.408268 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8099 23:07:25.411331 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8100 23:07:25.414447 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8101 23:07:25.421377 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8102 23:07:25.424651 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8103 23:07:25.427774 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8104 23:07:25.434690 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8105 23:07:25.437948 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8106 23:07:25.441439 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8107 23:07:25.447814 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8108 23:07:25.451103 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8109 23:07:25.454535 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8110 23:07:25.461253 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8111 23:07:25.461667 Total UI for P1: 0, mck2ui 16
8112 23:07:25.467504 best dqsien dly found for B0: ( 1, 9, 10)
8113 23:07:25.470623 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8114 23:07:25.474422 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8115 23:07:25.481572 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8116 23:07:25.481990 Total UI for P1: 0, mck2ui 16
8117 23:07:25.487255 best dqsien dly found for B1: ( 1, 9, 20)
8118 23:07:25.490981 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8119 23:07:25.494068 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8120 23:07:25.494483
8121 23:07:25.497552 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8122 23:07:25.500952 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8123 23:07:25.504119 [Gating] SW calibration Done
8124 23:07:25.504587 ==
8125 23:07:25.507447 Dram Type= 6, Freq= 0, CH_0, rank 1
8126 23:07:25.510512 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8127 23:07:25.510933 ==
8128 23:07:25.513921 RX Vref Scan: 0
8129 23:07:25.514333
8130 23:07:25.514657 RX Vref 0 -> 0, step: 1
8131 23:07:25.514962
8132 23:07:25.517176 RX Delay 0 -> 252, step: 8
8133 23:07:25.520669 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8134 23:07:25.527727 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8135 23:07:25.530702 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8136 23:07:25.533726 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8137 23:07:25.537266 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8138 23:07:25.540539 iDelay=200, Bit 5, Center 111 (56 ~ 167) 112
8139 23:07:25.547150 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8140 23:07:25.550607 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8141 23:07:25.553559 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8142 23:07:25.557118 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8143 23:07:25.560459 iDelay=200, Bit 10, Center 119 (56 ~ 183) 128
8144 23:07:25.567033 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8145 23:07:25.570179 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8146 23:07:25.573586 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
8147 23:07:25.576719 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8148 23:07:25.583471 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8149 23:07:25.583885 ==
8150 23:07:25.586983 Dram Type= 6, Freq= 0, CH_0, rank 1
8151 23:07:25.590182 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8152 23:07:25.590631 ==
8153 23:07:25.591033 DQS Delay:
8154 23:07:25.593635 DQS0 = 0, DQS1 = 0
8155 23:07:25.594046 DQM Delay:
8156 23:07:25.596618 DQM0 = 127, DQM1 = 120
8157 23:07:25.597028 DQ Delay:
8158 23:07:25.599882 DQ0 =127, DQ1 =131, DQ2 =123, DQ3 =123
8159 23:07:25.603400 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =139
8160 23:07:25.606873 DQ8 =111, DQ9 =107, DQ10 =119, DQ11 =115
8161 23:07:25.609934 DQ12 =127, DQ13 =127, DQ14 =131, DQ15 =127
8162 23:07:25.610345
8163 23:07:25.610666
8164 23:07:25.613029 ==
8165 23:07:25.616536 Dram Type= 6, Freq= 0, CH_0, rank 1
8166 23:07:25.620062 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8167 23:07:25.620735 ==
8168 23:07:25.621081
8169 23:07:25.621390
8170 23:07:25.623016 TX Vref Scan disable
8171 23:07:25.623428 == TX Byte 0 ==
8172 23:07:25.629656 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8173 23:07:25.633352 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8174 23:07:25.633762 == TX Byte 1 ==
8175 23:07:25.639713 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8176 23:07:25.643211 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8177 23:07:25.643628 ==
8178 23:07:25.646566 Dram Type= 6, Freq= 0, CH_0, rank 1
8179 23:07:25.649333 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8180 23:07:25.649750 ==
8181 23:07:25.665059
8182 23:07:25.668320 TX Vref early break, caculate TX vref
8183 23:07:25.671635 TX Vref=16, minBit 1, minWin=21, winSum=363
8184 23:07:25.674481 TX Vref=18, minBit 0, minWin=22, winSum=370
8185 23:07:25.677892 TX Vref=20, minBit 0, minWin=23, winSum=383
8186 23:07:25.681292 TX Vref=22, minBit 0, minWin=24, winSum=396
8187 23:07:25.684963 TX Vref=24, minBit 8, minWin=23, winSum=400
8188 23:07:25.691094 TX Vref=26, minBit 8, minWin=24, winSum=402
8189 23:07:25.694448 TX Vref=28, minBit 8, minWin=23, winSum=408
8190 23:07:25.697884 TX Vref=30, minBit 8, minWin=22, winSum=403
8191 23:07:25.701204 TX Vref=32, minBit 8, minWin=23, winSum=395
8192 23:07:25.704378 TX Vref=34, minBit 8, minWin=22, winSum=387
8193 23:07:25.708198 TX Vref=36, minBit 8, minWin=21, winSum=375
8194 23:07:25.714516 [TxChooseVref] Worse bit 8, Min win 24, Win sum 402, Final Vref 26
8195 23:07:25.714973
8196 23:07:25.718021 Final TX Range 0 Vref 26
8197 23:07:25.718483
8198 23:07:25.718935 ==
8199 23:07:25.721125 Dram Type= 6, Freq= 0, CH_0, rank 1
8200 23:07:25.724577 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8201 23:07:25.725038 ==
8202 23:07:25.725404
8203 23:07:25.725736
8204 23:07:25.727650 TX Vref Scan disable
8205 23:07:25.734120 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8206 23:07:25.734605 == TX Byte 0 ==
8207 23:07:25.737764 u2DelayCellOfst[0]=11 cells (3 PI)
8208 23:07:25.740779 u2DelayCellOfst[1]=18 cells (5 PI)
8209 23:07:25.744198 u2DelayCellOfst[2]=11 cells (3 PI)
8210 23:07:25.747774 u2DelayCellOfst[3]=11 cells (3 PI)
8211 23:07:25.750721 u2DelayCellOfst[4]=7 cells (2 PI)
8212 23:07:25.753984 u2DelayCellOfst[5]=0 cells (0 PI)
8213 23:07:25.757433 u2DelayCellOfst[6]=18 cells (5 PI)
8214 23:07:25.760791 u2DelayCellOfst[7]=18 cells (5 PI)
8215 23:07:25.764042 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8216 23:07:25.767322 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8217 23:07:25.770500 == TX Byte 1 ==
8218 23:07:25.774408 u2DelayCellOfst[8]=0 cells (0 PI)
8219 23:07:25.777734 u2DelayCellOfst[9]=0 cells (0 PI)
8220 23:07:25.780744 u2DelayCellOfst[10]=7 cells (2 PI)
8221 23:07:25.781160 u2DelayCellOfst[11]=7 cells (2 PI)
8222 23:07:25.783931 u2DelayCellOfst[12]=15 cells (4 PI)
8223 23:07:25.787115 u2DelayCellOfst[13]=15 cells (4 PI)
8224 23:07:25.790327 u2DelayCellOfst[14]=18 cells (5 PI)
8225 23:07:25.793828 u2DelayCellOfst[15]=11 cells (3 PI)
8226 23:07:25.800316 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8227 23:07:25.803739 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8228 23:07:25.804154 DramC Write-DBI on
8229 23:07:25.804539 ==
8230 23:07:25.807341 Dram Type= 6, Freq= 0, CH_0, rank 1
8231 23:07:25.813652 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8232 23:07:25.814084 ==
8233 23:07:25.814413
8234 23:07:25.814715
8235 23:07:25.815006 TX Vref Scan disable
8236 23:07:25.818452 == TX Byte 0 ==
8237 23:07:25.821584 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
8238 23:07:25.824580 == TX Byte 1 ==
8239 23:07:25.827968 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8240 23:07:25.831734 DramC Write-DBI off
8241 23:07:25.832197
8242 23:07:25.832582 [DATLAT]
8243 23:07:25.832892 Freq=1600, CH0 RK1
8244 23:07:25.833186
8245 23:07:25.834938 DATLAT Default: 0xf
8246 23:07:25.835350 0, 0xFFFF, sum = 0
8247 23:07:25.838040 1, 0xFFFF, sum = 0
8248 23:07:25.841091 2, 0xFFFF, sum = 0
8249 23:07:25.841510 3, 0xFFFF, sum = 0
8250 23:07:25.844751 4, 0xFFFF, sum = 0
8251 23:07:25.845168 5, 0xFFFF, sum = 0
8252 23:07:25.847773 6, 0xFFFF, sum = 0
8253 23:07:25.848192 7, 0xFFFF, sum = 0
8254 23:07:25.851396 8, 0xFFFF, sum = 0
8255 23:07:25.851812 9, 0xFFFF, sum = 0
8256 23:07:25.854306 10, 0xFFFF, sum = 0
8257 23:07:25.854726 11, 0xFFFF, sum = 0
8258 23:07:25.857797 12, 0xFFFF, sum = 0
8259 23:07:25.858215 13, 0xCFFF, sum = 0
8260 23:07:25.861134 14, 0x0, sum = 1
8261 23:07:25.861555 15, 0x0, sum = 2
8262 23:07:25.864351 16, 0x0, sum = 3
8263 23:07:25.864775 17, 0x0, sum = 4
8264 23:07:25.867620 best_step = 15
8265 23:07:25.868098
8266 23:07:25.868494 ==
8267 23:07:25.871371 Dram Type= 6, Freq= 0, CH_0, rank 1
8268 23:07:25.874324 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8269 23:07:25.874743 ==
8270 23:07:25.877684 RX Vref Scan: 0
8271 23:07:25.878093
8272 23:07:25.878419 RX Vref 0 -> 0, step: 1
8273 23:07:25.878722
8274 23:07:25.880952 RX Delay 3 -> 252, step: 4
8275 23:07:25.884498 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8276 23:07:25.890839 iDelay=191, Bit 1, Center 124 (71 ~ 178) 108
8277 23:07:25.894084 iDelay=191, Bit 2, Center 122 (71 ~ 174) 104
8278 23:07:25.897418 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8279 23:07:25.900471 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8280 23:07:25.903921 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8281 23:07:25.910736 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8282 23:07:25.914226 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8283 23:07:25.917130 iDelay=191, Bit 8, Center 112 (55 ~ 170) 116
8284 23:07:25.921124 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8285 23:07:25.923806 iDelay=191, Bit 10, Center 118 (59 ~ 178) 120
8286 23:07:25.930455 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8287 23:07:25.933873 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8288 23:07:25.937649 iDelay=191, Bit 13, Center 124 (67 ~ 182) 116
8289 23:07:25.940791 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8290 23:07:25.947085 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8291 23:07:25.947690 ==
8292 23:07:25.950358 Dram Type= 6, Freq= 0, CH_0, rank 1
8293 23:07:25.953745 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8294 23:07:25.954164 ==
8295 23:07:25.954491 DQS Delay:
8296 23:07:25.957466 DQS0 = 0, DQS1 = 0
8297 23:07:25.957880 DQM Delay:
8298 23:07:25.960616 DQM0 = 124, DQM1 = 118
8299 23:07:25.961031 DQ Delay:
8300 23:07:25.964099 DQ0 =124, DQ1 =124, DQ2 =122, DQ3 =122
8301 23:07:25.967046 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8302 23:07:25.970453 DQ8 =112, DQ9 =104, DQ10 =118, DQ11 =112
8303 23:07:25.974094 DQ12 =124, DQ13 =124, DQ14 =128, DQ15 =124
8304 23:07:25.974511
8305 23:07:25.974835
8306 23:07:25.977326
8307 23:07:25.977741 [DramC_TX_OE_Calibration] TA2
8308 23:07:25.980551 Original DQ_B0 (3 6) =30, OEN = 27
8309 23:07:25.984068 Original DQ_B1 (3 6) =30, OEN = 27
8310 23:07:25.987254 24, 0x0, End_B0=24 End_B1=24
8311 23:07:25.990447 25, 0x0, End_B0=25 End_B1=25
8312 23:07:25.990871 26, 0x0, End_B0=26 End_B1=26
8313 23:07:25.994003 27, 0x0, End_B0=27 End_B1=27
8314 23:07:25.997282 28, 0x0, End_B0=28 End_B1=28
8315 23:07:26.000138 29, 0x0, End_B0=29 End_B1=29
8316 23:07:26.003782 30, 0x0, End_B0=30 End_B1=30
8317 23:07:26.004241 31, 0x5151, End_B0=30 End_B1=30
8318 23:07:26.007340 Byte0 end_step=30 best_step=27
8319 23:07:26.010408 Byte1 end_step=30 best_step=27
8320 23:07:26.013984 Byte0 TX OE(2T, 0.5T) = (3, 3)
8321 23:07:26.017114 Byte1 TX OE(2T, 0.5T) = (3, 3)
8322 23:07:26.017529
8323 23:07:26.017858
8324 23:07:26.023828 [DQSOSCAuto] RK1, (LSB)MR18= 0x2614, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 390 ps
8325 23:07:26.026655 CH0 RK1: MR19=303, MR18=2614
8326 23:07:26.033363 CH0_RK1: MR19=0x303, MR18=0x2614, DQSOSC=390, MR23=63, INC=24, DEC=16
8327 23:07:26.036597 [RxdqsGatingPostProcess] freq 1600
8328 23:07:26.043673 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8329 23:07:26.046877 best DQS0 dly(2T, 0.5T) = (1, 1)
8330 23:07:26.047297 best DQS1 dly(2T, 0.5T) = (1, 1)
8331 23:07:26.049756 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8332 23:07:26.053272 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8333 23:07:26.056426 best DQS0 dly(2T, 0.5T) = (1, 1)
8334 23:07:26.060187 best DQS1 dly(2T, 0.5T) = (1, 1)
8335 23:07:26.063256 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8336 23:07:26.066670 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8337 23:07:26.069815 Pre-setting of DQS Precalculation
8338 23:07:26.073100 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8339 23:07:26.076307 ==
8340 23:07:26.079941 Dram Type= 6, Freq= 0, CH_1, rank 0
8341 23:07:26.082954 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8342 23:07:26.083373 ==
8343 23:07:26.086236 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8344 23:07:26.092905 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8345 23:07:26.096309 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8346 23:07:26.102925 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8347 23:07:26.110941 [CA 0] Center 42 (13~71) winsize 59
8348 23:07:26.114538 [CA 1] Center 42 (13~72) winsize 60
8349 23:07:26.118048 [CA 2] Center 38 (9~67) winsize 59
8350 23:07:26.121185 [CA 3] Center 37 (8~66) winsize 59
8351 23:07:26.124544 [CA 4] Center 37 (8~67) winsize 60
8352 23:07:26.128181 [CA 5] Center 36 (7~66) winsize 60
8353 23:07:26.128749
8354 23:07:26.131161 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8355 23:07:26.131577
8356 23:07:26.134224 [CATrainingPosCal] consider 1 rank data
8357 23:07:26.137905 u2DelayCellTimex100 = 258/100 ps
8358 23:07:26.141024 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8359 23:07:26.147625 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8360 23:07:26.151333 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8361 23:07:26.154572 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8362 23:07:26.157913 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8363 23:07:26.161043 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8364 23:07:26.161470
8365 23:07:26.164282 CA PerBit enable=1, Macro0, CA PI delay=36
8366 23:07:26.164576
8367 23:07:26.167333 [CBTSetCACLKResult] CA Dly = 36
8368 23:07:26.170662 CS Dly: 10 (0~41)
8369 23:07:26.173947 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8370 23:07:26.177310 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8371 23:07:26.177601 ==
8372 23:07:26.180452 Dram Type= 6, Freq= 0, CH_1, rank 1
8373 23:07:26.184334 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8374 23:07:26.187503 ==
8375 23:07:26.190640 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8376 23:07:26.194192 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8377 23:07:26.200453 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8378 23:07:26.203907 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8379 23:07:26.214122 [CA 0] Center 42 (13~71) winsize 59
8380 23:07:26.217808 [CA 1] Center 42 (12~72) winsize 61
8381 23:07:26.220910 [CA 2] Center 37 (8~67) winsize 60
8382 23:07:26.224453 [CA 3] Center 36 (7~66) winsize 60
8383 23:07:26.227646 [CA 4] Center 38 (8~68) winsize 61
8384 23:07:26.231019 [CA 5] Center 37 (7~67) winsize 61
8385 23:07:26.231614
8386 23:07:26.234156 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8387 23:07:26.234607
8388 23:07:26.237453 [CATrainingPosCal] consider 2 rank data
8389 23:07:26.241184 u2DelayCellTimex100 = 258/100 ps
8390 23:07:26.244073 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8391 23:07:26.250571 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8392 23:07:26.253752 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8393 23:07:26.257529 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8394 23:07:26.260520 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8395 23:07:26.264318 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8396 23:07:26.264727
8397 23:07:26.266940 CA PerBit enable=1, Macro0, CA PI delay=36
8398 23:07:26.267355
8399 23:07:26.270837 [CBTSetCACLKResult] CA Dly = 36
8400 23:07:26.273954 CS Dly: 11 (0~43)
8401 23:07:26.277222 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8402 23:07:26.280444 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8403 23:07:26.280852
8404 23:07:26.284047 ----->DramcWriteLeveling(PI) begin...
8405 23:07:26.284615 ==
8406 23:07:26.286968 Dram Type= 6, Freq= 0, CH_1, rank 0
8407 23:07:26.293988 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8408 23:07:26.294397 ==
8409 23:07:26.297139 Write leveling (Byte 0): 24 => 24
8410 23:07:26.297544 Write leveling (Byte 1): 29 => 29
8411 23:07:26.300528 DramcWriteLeveling(PI) end<-----
8412 23:07:26.300933
8413 23:07:26.301253 ==
8414 23:07:26.303680 Dram Type= 6, Freq= 0, CH_1, rank 0
8415 23:07:26.310311 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8416 23:07:26.310723 ==
8417 23:07:26.313823 [Gating] SW mode calibration
8418 23:07:26.320487 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8419 23:07:26.323330 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8420 23:07:26.329876 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8421 23:07:26.333600 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8422 23:07:26.336779 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8423 23:07:26.343286 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8424 23:07:26.346646 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8425 23:07:26.349933 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8426 23:07:26.356449 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8427 23:07:26.359668 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8428 23:07:26.363041 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8429 23:07:26.370163 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8430 23:07:26.373233 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8431 23:07:26.376499 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8432 23:07:26.383125 1 5 16 | B1->B0 | 2525 2424 | 0 0 | (0 1) (0 0)
8433 23:07:26.386386 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8434 23:07:26.389587 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8435 23:07:26.396031 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8436 23:07:26.399393 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8437 23:07:26.403118 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8438 23:07:26.409763 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8439 23:07:26.412522 1 6 12 | B1->B0 | 2b2b 2b2b | 0 0 | (0 0) (0 0)
8440 23:07:26.416190 1 6 16 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
8441 23:07:26.422701 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8442 23:07:26.426118 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8443 23:07:26.429370 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8444 23:07:26.435659 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8445 23:07:26.439385 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8446 23:07:26.442536 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8447 23:07:26.448877 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8448 23:07:26.452159 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8449 23:07:26.455557 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8450 23:07:26.462101 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8451 23:07:26.465691 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8452 23:07:26.468688 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8453 23:07:26.475235 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8454 23:07:26.478473 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8455 23:07:26.481796 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8456 23:07:26.488667 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8457 23:07:26.492017 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8458 23:07:26.495040 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8459 23:07:26.501526 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8460 23:07:26.504900 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8461 23:07:26.508114 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8462 23:07:26.514930 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8463 23:07:26.518123 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8464 23:07:26.521060 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8465 23:07:26.527915 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8466 23:07:26.527999 Total UI for P1: 0, mck2ui 16
8467 23:07:26.534520 best dqsien dly found for B0: ( 1, 9, 16)
8468 23:07:26.534601 Total UI for P1: 0, mck2ui 16
8469 23:07:26.537863 best dqsien dly found for B1: ( 1, 9, 16)
8470 23:07:26.544528 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8471 23:07:26.548135 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8472 23:07:26.548274
8473 23:07:26.551551 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8474 23:07:26.554678 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8475 23:07:26.557675 [Gating] SW calibration Done
8476 23:07:26.557755 ==
8477 23:07:26.561118 Dram Type= 6, Freq= 0, CH_1, rank 0
8478 23:07:26.564576 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8479 23:07:26.564657 ==
8480 23:07:26.567581 RX Vref Scan: 0
8481 23:07:26.567660
8482 23:07:26.567723 RX Vref 0 -> 0, step: 1
8483 23:07:26.567781
8484 23:07:26.570628 RX Delay 0 -> 252, step: 8
8485 23:07:26.574169 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8486 23:07:26.580656 iDelay=200, Bit 1, Center 127 (64 ~ 191) 128
8487 23:07:26.584055 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8488 23:07:26.587587 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8489 23:07:26.590608 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8490 23:07:26.593991 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8491 23:07:26.600709 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8492 23:07:26.603943 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8493 23:07:26.607408 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8494 23:07:26.610467 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8495 23:07:26.613798 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8496 23:07:26.620249 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8497 23:07:26.624001 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8498 23:07:26.627053 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8499 23:07:26.630443 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8500 23:07:26.637035 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8501 23:07:26.637332 ==
8502 23:07:26.640294 Dram Type= 6, Freq= 0, CH_1, rank 0
8503 23:07:26.643851 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8504 23:07:26.644309 ==
8505 23:07:26.644679 DQS Delay:
8506 23:07:26.647215 DQS0 = 0, DQS1 = 0
8507 23:07:26.647628 DQM Delay:
8508 23:07:26.650340 DQM0 = 132, DQM1 = 126
8509 23:07:26.650754 DQ Delay:
8510 23:07:26.653626 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8511 23:07:26.657049 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =131
8512 23:07:26.660417 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
8513 23:07:26.663630 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8514 23:07:26.664042
8515 23:07:26.664403
8516 23:07:26.666697 ==
8517 23:07:26.669634 Dram Type= 6, Freq= 0, CH_1, rank 0
8518 23:07:26.673483 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8519 23:07:26.673594 ==
8520 23:07:26.673661
8521 23:07:26.673720
8522 23:07:26.676519 TX Vref Scan disable
8523 23:07:26.676599 == TX Byte 0 ==
8524 23:07:26.682946 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8525 23:07:26.686863 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8526 23:07:26.686944 == TX Byte 1 ==
8527 23:07:26.693103 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8528 23:07:26.696475 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8529 23:07:26.696555 ==
8530 23:07:26.699522 Dram Type= 6, Freq= 0, CH_1, rank 0
8531 23:07:26.702750 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8532 23:07:26.702832 ==
8533 23:07:26.716486
8534 23:07:26.719587 TX Vref early break, caculate TX vref
8535 23:07:26.723289 TX Vref=16, minBit 8, minWin=21, winSum=360
8536 23:07:26.726624 TX Vref=18, minBit 9, minWin=21, winSum=374
8537 23:07:26.729658 TX Vref=20, minBit 10, minWin=22, winSum=379
8538 23:07:26.733021 TX Vref=22, minBit 8, minWin=23, winSum=393
8539 23:07:26.736347 TX Vref=24, minBit 8, minWin=24, winSum=400
8540 23:07:26.743086 TX Vref=26, minBit 11, minWin=24, winSum=414
8541 23:07:26.746340 TX Vref=28, minBit 6, minWin=25, winSum=415
8542 23:07:26.749562 TX Vref=30, minBit 9, minWin=24, winSum=413
8543 23:07:26.753112 TX Vref=32, minBit 0, minWin=24, winSum=406
8544 23:07:26.756091 TX Vref=34, minBit 9, minWin=23, winSum=391
8545 23:07:26.763062 [TxChooseVref] Worse bit 6, Min win 25, Win sum 415, Final Vref 28
8546 23:07:26.763188
8547 23:07:26.766231 Final TX Range 0 Vref 28
8548 23:07:26.766372
8549 23:07:26.766485 ==
8550 23:07:26.769415 Dram Type= 6, Freq= 0, CH_1, rank 0
8551 23:07:26.772728 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8552 23:07:26.772809 ==
8553 23:07:26.772873
8554 23:07:26.772932
8555 23:07:26.776134 TX Vref Scan disable
8556 23:07:26.782539 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8557 23:07:26.782620 == TX Byte 0 ==
8558 23:07:26.786221 u2DelayCellOfst[0]=18 cells (5 PI)
8559 23:07:26.789360 u2DelayCellOfst[1]=15 cells (4 PI)
8560 23:07:26.792810 u2DelayCellOfst[2]=0 cells (0 PI)
8561 23:07:26.796131 u2DelayCellOfst[3]=7 cells (2 PI)
8562 23:07:26.799339 u2DelayCellOfst[4]=7 cells (2 PI)
8563 23:07:26.802430 u2DelayCellOfst[5]=22 cells (6 PI)
8564 23:07:26.805645 u2DelayCellOfst[6]=22 cells (6 PI)
8565 23:07:26.809483 u2DelayCellOfst[7]=7 cells (2 PI)
8566 23:07:26.812130 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8567 23:07:26.815850 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8568 23:07:26.819030 == TX Byte 1 ==
8569 23:07:26.822166 u2DelayCellOfst[8]=0 cells (0 PI)
8570 23:07:26.822247 u2DelayCellOfst[9]=7 cells (2 PI)
8571 23:07:26.825414 u2DelayCellOfst[10]=18 cells (5 PI)
8572 23:07:26.828844 u2DelayCellOfst[11]=11 cells (3 PI)
8573 23:07:26.832443 u2DelayCellOfst[12]=18 cells (5 PI)
8574 23:07:26.835278 u2DelayCellOfst[13]=22 cells (6 PI)
8575 23:07:26.838601 u2DelayCellOfst[14]=22 cells (6 PI)
8576 23:07:26.841983 u2DelayCellOfst[15]=26 cells (7 PI)
8577 23:07:26.845620 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8578 23:07:26.851992 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8579 23:07:26.852073 DramC Write-DBI on
8580 23:07:26.852136 ==
8581 23:07:26.855378 Dram Type= 6, Freq= 0, CH_1, rank 0
8582 23:07:26.862191 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8583 23:07:26.862275 ==
8584 23:07:26.862340
8585 23:07:26.862404
8586 23:07:26.862461 TX Vref Scan disable
8587 23:07:26.865897 == TX Byte 0 ==
8588 23:07:26.869240 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8589 23:07:26.872433 == TX Byte 1 ==
8590 23:07:26.875732 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8591 23:07:26.879388 DramC Write-DBI off
8592 23:07:26.879468
8593 23:07:26.879532 [DATLAT]
8594 23:07:26.879591 Freq=1600, CH1 RK0
8595 23:07:26.879649
8596 23:07:26.882366 DATLAT Default: 0xf
8597 23:07:26.882472 0, 0xFFFF, sum = 0
8598 23:07:26.885579 1, 0xFFFF, sum = 0
8599 23:07:26.888883 2, 0xFFFF, sum = 0
8600 23:07:26.888977 3, 0xFFFF, sum = 0
8601 23:07:26.892180 4, 0xFFFF, sum = 0
8602 23:07:26.892285 5, 0xFFFF, sum = 0
8603 23:07:26.895775 6, 0xFFFF, sum = 0
8604 23:07:26.895877 7, 0xFFFF, sum = 0
8605 23:07:26.898838 8, 0xFFFF, sum = 0
8606 23:07:26.898949 9, 0xFFFF, sum = 0
8607 23:07:26.902090 10, 0xFFFF, sum = 0
8608 23:07:26.902201 11, 0xFFFF, sum = 0
8609 23:07:26.905596 12, 0xFFFF, sum = 0
8610 23:07:26.905718 13, 0x8FFF, sum = 0
8611 23:07:26.909007 14, 0x0, sum = 1
8612 23:07:26.909089 15, 0x0, sum = 2
8613 23:07:26.912415 16, 0x0, sum = 3
8614 23:07:26.912497 17, 0x0, sum = 4
8615 23:07:26.915461 best_step = 15
8616 23:07:26.915540
8617 23:07:26.915604 ==
8618 23:07:26.918890 Dram Type= 6, Freq= 0, CH_1, rank 0
8619 23:07:26.921986 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8620 23:07:26.922066 ==
8621 23:07:26.925473 RX Vref Scan: 1
8622 23:07:26.925553
8623 23:07:26.925615 Set Vref Range= 24 -> 127
8624 23:07:26.925674
8625 23:07:26.928748 RX Vref 24 -> 127, step: 1
8626 23:07:26.928827
8627 23:07:26.931927 RX Delay 11 -> 252, step: 4
8628 23:07:26.932006
8629 23:07:26.935265 Set Vref, RX VrefLevel [Byte0]: 24
8630 23:07:26.938982 [Byte1]: 24
8631 23:07:26.939062
8632 23:07:26.941755 Set Vref, RX VrefLevel [Byte0]: 25
8633 23:07:26.945625 [Byte1]: 25
8634 23:07:26.948566
8635 23:07:26.948646 Set Vref, RX VrefLevel [Byte0]: 26
8636 23:07:26.951887 [Byte1]: 26
8637 23:07:26.956132
8638 23:07:26.956268 Set Vref, RX VrefLevel [Byte0]: 27
8639 23:07:26.959760 [Byte1]: 27
8640 23:07:26.963996
8641 23:07:26.964076 Set Vref, RX VrefLevel [Byte0]: 28
8642 23:07:26.967011 [Byte1]: 28
8643 23:07:26.971438
8644 23:07:26.971517 Set Vref, RX VrefLevel [Byte0]: 29
8645 23:07:26.974578 [Byte1]: 29
8646 23:07:26.979428
8647 23:07:26.979508 Set Vref, RX VrefLevel [Byte0]: 30
8648 23:07:26.982157 [Byte1]: 30
8649 23:07:26.986903
8650 23:07:26.986983 Set Vref, RX VrefLevel [Byte0]: 31
8651 23:07:26.990519 [Byte1]: 31
8652 23:07:26.994466
8653 23:07:26.994545 Set Vref, RX VrefLevel [Byte0]: 32
8654 23:07:26.997943 [Byte1]: 32
8655 23:07:27.001717
8656 23:07:27.001796 Set Vref, RX VrefLevel [Byte0]: 33
8657 23:07:27.005007 [Byte1]: 33
8658 23:07:27.009673
8659 23:07:27.009753 Set Vref, RX VrefLevel [Byte0]: 34
8660 23:07:27.012726 [Byte1]: 34
8661 23:07:27.016899
8662 23:07:27.016978 Set Vref, RX VrefLevel [Byte0]: 35
8663 23:07:27.020743 [Byte1]: 35
8664 23:07:27.024957
8665 23:07:27.025036 Set Vref, RX VrefLevel [Byte0]: 36
8666 23:07:27.028089 [Byte1]: 36
8667 23:07:27.032334
8668 23:07:27.032412 Set Vref, RX VrefLevel [Byte0]: 37
8669 23:07:27.035470 [Byte1]: 37
8670 23:07:27.039814
8671 23:07:27.039905 Set Vref, RX VrefLevel [Byte0]: 38
8672 23:07:27.043200 [Byte1]: 38
8673 23:07:27.047580
8674 23:07:27.047679 Set Vref, RX VrefLevel [Byte0]: 39
8675 23:07:27.050658 [Byte1]: 39
8676 23:07:27.055459
8677 23:07:27.055577 Set Vref, RX VrefLevel [Byte0]: 40
8678 23:07:27.058466 [Byte1]: 40
8679 23:07:27.062921
8680 23:07:27.063052 Set Vref, RX VrefLevel [Byte0]: 41
8681 23:07:27.065989 [Byte1]: 41
8682 23:07:27.070498
8683 23:07:27.070665 Set Vref, RX VrefLevel [Byte0]: 42
8684 23:07:27.073890 [Byte1]: 42
8685 23:07:27.077998
8686 23:07:27.078077 Set Vref, RX VrefLevel [Byte0]: 43
8687 23:07:27.081557 [Byte1]: 43
8688 23:07:27.085981
8689 23:07:27.086091 Set Vref, RX VrefLevel [Byte0]: 44
8690 23:07:27.089280 [Byte1]: 44
8691 23:07:27.093591
8692 23:07:27.093671 Set Vref, RX VrefLevel [Byte0]: 45
8693 23:07:27.096586 [Byte1]: 45
8694 23:07:27.100639
8695 23:07:27.100718 Set Vref, RX VrefLevel [Byte0]: 46
8696 23:07:27.104489 [Byte1]: 46
8697 23:07:27.108566
8698 23:07:27.108645 Set Vref, RX VrefLevel [Byte0]: 47
8699 23:07:27.111803 [Byte1]: 47
8700 23:07:27.116521
8701 23:07:27.116601 Set Vref, RX VrefLevel [Byte0]: 48
8702 23:07:27.119368 [Byte1]: 48
8703 23:07:27.123638
8704 23:07:27.123720 Set Vref, RX VrefLevel [Byte0]: 49
8705 23:07:27.127041 [Byte1]: 49
8706 23:07:27.131595
8707 23:07:27.131721 Set Vref, RX VrefLevel [Byte0]: 50
8708 23:07:27.135160 [Byte1]: 50
8709 23:07:27.139585
8710 23:07:27.139992 Set Vref, RX VrefLevel [Byte0]: 51
8711 23:07:27.142420 [Byte1]: 51
8712 23:07:27.147215
8713 23:07:27.147670 Set Vref, RX VrefLevel [Byte0]: 52
8714 23:07:27.150583 [Byte1]: 52
8715 23:07:27.154364
8716 23:07:27.154773 Set Vref, RX VrefLevel [Byte0]: 53
8717 23:07:27.157728 [Byte1]: 53
8718 23:07:27.161884
8719 23:07:27.162294 Set Vref, RX VrefLevel [Byte0]: 54
8720 23:07:27.165472 [Byte1]: 54
8721 23:07:27.169850
8722 23:07:27.170258 Set Vref, RX VrefLevel [Byte0]: 55
8723 23:07:27.172877 [Byte1]: 55
8724 23:07:27.177395
8725 23:07:27.177810 Set Vref, RX VrefLevel [Byte0]: 56
8726 23:07:27.180687 [Byte1]: 56
8727 23:07:27.184655
8728 23:07:27.185066 Set Vref, RX VrefLevel [Byte0]: 57
8729 23:07:27.188561 [Byte1]: 57
8730 23:07:27.192501
8731 23:07:27.192920 Set Vref, RX VrefLevel [Byte0]: 58
8732 23:07:27.195709 [Byte1]: 58
8733 23:07:27.200082
8734 23:07:27.200538 Set Vref, RX VrefLevel [Byte0]: 59
8735 23:07:27.203307 [Byte1]: 59
8736 23:07:27.207709
8737 23:07:27.208118 Set Vref, RX VrefLevel [Byte0]: 60
8738 23:07:27.211325 [Byte1]: 60
8739 23:07:27.215569
8740 23:07:27.216021 Set Vref, RX VrefLevel [Byte0]: 61
8741 23:07:27.218490 [Byte1]: 61
8742 23:07:27.222929
8743 23:07:27.223338 Set Vref, RX VrefLevel [Byte0]: 62
8744 23:07:27.226267 [Byte1]: 62
8745 23:07:27.230857
8746 23:07:27.231267 Set Vref, RX VrefLevel [Byte0]: 63
8747 23:07:27.233986 [Byte1]: 63
8748 23:07:27.238312
8749 23:07:27.238718 Set Vref, RX VrefLevel [Byte0]: 64
8750 23:07:27.241443 [Byte1]: 64
8751 23:07:27.245964
8752 23:07:27.246451 Set Vref, RX VrefLevel [Byte0]: 65
8753 23:07:27.249271 [Byte1]: 65
8754 23:07:27.253304
8755 23:07:27.253755 Set Vref, RX VrefLevel [Byte0]: 66
8756 23:07:27.256635 [Byte1]: 66
8757 23:07:27.261122
8758 23:07:27.261529 Set Vref, RX VrefLevel [Byte0]: 67
8759 23:07:27.264134 [Byte1]: 67
8760 23:07:27.268472
8761 23:07:27.268882 Set Vref, RX VrefLevel [Byte0]: 68
8762 23:07:27.271928 [Byte1]: 68
8763 23:07:27.276469
8764 23:07:27.277044 Set Vref, RX VrefLevel [Byte0]: 69
8765 23:07:27.279538 [Byte1]: 69
8766 23:07:27.283939
8767 23:07:27.284384 Set Vref, RX VrefLevel [Byte0]: 70
8768 23:07:27.286819 [Byte1]: 70
8769 23:07:27.290969
8770 23:07:27.291048 Set Vref, RX VrefLevel [Byte0]: 71
8771 23:07:27.294514 [Byte1]: 71
8772 23:07:27.299118
8773 23:07:27.299197 Set Vref, RX VrefLevel [Byte0]: 72
8774 23:07:27.302199 [Byte1]: 72
8775 23:07:27.306603
8776 23:07:27.306682 Final RX Vref Byte 0 = 56 to rank0
8777 23:07:27.309896 Final RX Vref Byte 1 = 55 to rank0
8778 23:07:27.313009 Final RX Vref Byte 0 = 56 to rank1
8779 23:07:27.316183 Final RX Vref Byte 1 = 55 to rank1==
8780 23:07:27.319639 Dram Type= 6, Freq= 0, CH_1, rank 0
8781 23:07:27.326263 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8782 23:07:27.326344 ==
8783 23:07:27.326407 DQS Delay:
8784 23:07:27.329449 DQS0 = 0, DQS1 = 0
8785 23:07:27.329529 DQM Delay:
8786 23:07:27.329592 DQM0 = 130, DQM1 = 123
8787 23:07:27.332632 DQ Delay:
8788 23:07:27.335752 DQ0 =134, DQ1 =126, DQ2 =120, DQ3 =128
8789 23:07:27.339032 DQ4 =126, DQ5 =140, DQ6 =142, DQ7 =128
8790 23:07:27.342743 DQ8 =110, DQ9 =114, DQ10 =122, DQ11 =116
8791 23:07:27.346167 DQ12 =132, DQ13 =130, DQ14 =132, DQ15 =130
8792 23:07:27.346247
8793 23:07:27.346310
8794 23:07:27.346368
8795 23:07:27.349504 [DramC_TX_OE_Calibration] TA2
8796 23:07:27.352759 Original DQ_B0 (3 6) =30, OEN = 27
8797 23:07:27.356180 Original DQ_B1 (3 6) =30, OEN = 27
8798 23:07:27.359349 24, 0x0, End_B0=24 End_B1=24
8799 23:07:27.359429 25, 0x0, End_B0=25 End_B1=25
8800 23:07:27.362459 26, 0x0, End_B0=26 End_B1=26
8801 23:07:27.365850 27, 0x0, End_B0=27 End_B1=27
8802 23:07:27.369516 28, 0x0, End_B0=28 End_B1=28
8803 23:07:27.372737 29, 0x0, End_B0=29 End_B1=29
8804 23:07:27.372818 30, 0x0, End_B0=30 End_B1=30
8805 23:07:27.375911 31, 0x4141, End_B0=30 End_B1=30
8806 23:07:27.379257 Byte0 end_step=30 best_step=27
8807 23:07:27.382828 Byte1 end_step=30 best_step=27
8808 23:07:27.386146 Byte0 TX OE(2T, 0.5T) = (3, 3)
8809 23:07:27.389265 Byte1 TX OE(2T, 0.5T) = (3, 3)
8810 23:07:27.389345
8811 23:07:27.389408
8812 23:07:27.395657 [DQSOSCAuto] RK0, (LSB)MR18= 0x90e, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 405 ps
8813 23:07:27.399195 CH1 RK0: MR19=303, MR18=90E
8814 23:07:27.405921 CH1_RK0: MR19=0x303, MR18=0x90E, DQSOSC=402, MR23=63, INC=22, DEC=15
8815 23:07:27.406013
8816 23:07:27.408703 ----->DramcWriteLeveling(PI) begin...
8817 23:07:27.408805 ==
8818 23:07:27.412432 Dram Type= 6, Freq= 0, CH_1, rank 1
8819 23:07:27.415551 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8820 23:07:27.415661 ==
8821 23:07:27.418790 Write leveling (Byte 0): 25 => 25
8822 23:07:27.421974 Write leveling (Byte 1): 26 => 26
8823 23:07:27.425360 DramcWriteLeveling(PI) end<-----
8824 23:07:27.425492
8825 23:07:27.425595 ==
8826 23:07:27.428689 Dram Type= 6, Freq= 0, CH_1, rank 1
8827 23:07:27.432335 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8828 23:07:27.432544 ==
8829 23:07:27.435471 [Gating] SW mode calibration
8830 23:07:27.442165 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8831 23:07:27.448994 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8832 23:07:27.451845 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8833 23:07:27.458586 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8834 23:07:27.461981 1 4 8 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
8835 23:07:27.465389 1 4 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
8836 23:07:27.472465 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8837 23:07:27.475042 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8838 23:07:27.478545 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8839 23:07:27.485182 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8840 23:07:27.488563 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8841 23:07:27.491895 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8842 23:07:27.498334 1 5 8 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
8843 23:07:27.501799 1 5 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8844 23:07:27.505157 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8845 23:07:27.508555 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8846 23:07:27.514963 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8847 23:07:27.518486 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8848 23:07:27.521909 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8849 23:07:27.528455 1 6 4 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
8850 23:07:27.531642 1 6 8 | B1->B0 | 2424 4444 | 0 0 | (0 0) (0 0)
8851 23:07:27.535387 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8852 23:07:27.541824 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8853 23:07:27.544920 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8854 23:07:27.548528 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8855 23:07:27.555042 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8856 23:07:27.558272 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8857 23:07:27.561314 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8858 23:07:27.568622 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8859 23:07:27.571655 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8860 23:07:27.575133 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8861 23:07:27.581485 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8862 23:07:27.584694 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8863 23:07:27.587903 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8864 23:07:27.594664 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8865 23:07:27.598123 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8866 23:07:27.601408 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8867 23:07:27.608345 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8868 23:07:27.611526 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8869 23:07:27.614847 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8870 23:07:27.621045 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8871 23:07:27.624327 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8872 23:07:27.627768 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8873 23:07:27.634420 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8874 23:07:27.637921 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8875 23:07:27.640914 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8876 23:07:27.647874 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8877 23:07:27.648377 Total UI for P1: 0, mck2ui 16
8878 23:07:27.654312 best dqsien dly found for B0: ( 1, 9, 10)
8879 23:07:27.654774 Total UI for P1: 0, mck2ui 16
8880 23:07:27.660711 best dqsien dly found for B1: ( 1, 9, 10)
8881 23:07:27.664324 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8882 23:07:27.667689 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8883 23:07:27.668159
8884 23:07:27.670860 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8885 23:07:27.674329 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8886 23:07:27.677723 [Gating] SW calibration Done
8887 23:07:27.678193 ==
8888 23:07:27.680995 Dram Type= 6, Freq= 0, CH_1, rank 1
8889 23:07:27.684135 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8890 23:07:27.684707 ==
8891 23:07:27.687571 RX Vref Scan: 0
8892 23:07:27.688030
8893 23:07:27.688443 RX Vref 0 -> 0, step: 1
8894 23:07:27.688792
8895 23:07:27.690875 RX Delay 0 -> 252, step: 8
8896 23:07:27.694186 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8897 23:07:27.700647 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8898 23:07:27.704265 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8899 23:07:27.707192 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8900 23:07:27.710612 iDelay=200, Bit 4, Center 127 (64 ~ 191) 128
8901 23:07:27.714423 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8902 23:07:27.721186 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8903 23:07:27.724247 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8904 23:07:27.727419 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8905 23:07:27.730635 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8906 23:07:27.733668 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8907 23:07:27.740470 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8908 23:07:27.743936 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8909 23:07:27.747310 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8910 23:07:27.750367 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8911 23:07:27.754233 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8912 23:07:27.757308 ==
8913 23:07:27.760372 Dram Type= 6, Freq= 0, CH_1, rank 1
8914 23:07:27.763463 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8915 23:07:27.764153 ==
8916 23:07:27.764843 DQS Delay:
8917 23:07:27.767134 DQS0 = 0, DQS1 = 0
8918 23:07:27.767844 DQM Delay:
8919 23:07:27.770289 DQM0 = 131, DQM1 = 128
8920 23:07:27.770968 DQ Delay:
8921 23:07:27.773768 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8922 23:07:27.777000 DQ4 =127, DQ5 =143, DQ6 =139, DQ7 =131
8923 23:07:27.779897 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8924 23:07:27.783482 DQ12 =131, DQ13 =139, DQ14 =131, DQ15 =139
8925 23:07:27.783750
8926 23:07:27.783971
8927 23:07:27.784175 ==
8928 23:07:27.786683 Dram Type= 6, Freq= 0, CH_1, rank 1
8929 23:07:27.793075 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8930 23:07:27.793241 ==
8931 23:07:27.793366
8932 23:07:27.793482
8933 23:07:27.793599 TX Vref Scan disable
8934 23:07:27.796833 == TX Byte 0 ==
8935 23:07:27.800299 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8936 23:07:27.803603 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8937 23:07:27.806959 == TX Byte 1 ==
8938 23:07:27.810495 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8939 23:07:27.816655 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8940 23:07:27.816780 ==
8941 23:07:27.820009 Dram Type= 6, Freq= 0, CH_1, rank 1
8942 23:07:27.823662 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8943 23:07:27.823783 ==
8944 23:07:27.836775
8945 23:07:27.840099 TX Vref early break, caculate TX vref
8946 23:07:27.843510 TX Vref=16, minBit 0, minWin=23, winSum=387
8947 23:07:27.846892 TX Vref=18, minBit 0, minWin=23, winSum=397
8948 23:07:27.849818 TX Vref=20, minBit 0, minWin=23, winSum=404
8949 23:07:27.853407 TX Vref=22, minBit 0, minWin=25, winSum=413
8950 23:07:27.856666 TX Vref=24, minBit 0, minWin=25, winSum=419
8951 23:07:27.863241 TX Vref=26, minBit 0, minWin=25, winSum=428
8952 23:07:27.866599 TX Vref=28, minBit 5, minWin=25, winSum=429
8953 23:07:27.869415 TX Vref=30, minBit 1, minWin=25, winSum=423
8954 23:07:27.872908 TX Vref=32, minBit 5, minWin=24, winSum=415
8955 23:07:27.876129 TX Vref=34, minBit 1, minWin=23, winSum=410
8956 23:07:27.879797 TX Vref=36, minBit 1, minWin=23, winSum=397
8957 23:07:27.886545 [TxChooseVref] Worse bit 5, Min win 25, Win sum 429, Final Vref 28
8958 23:07:27.886623
8959 23:07:27.889813 Final TX Range 0 Vref 28
8960 23:07:27.889886
8961 23:07:27.889946 ==
8962 23:07:27.892607 Dram Type= 6, Freq= 0, CH_1, rank 1
8963 23:07:27.896130 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8964 23:07:27.896263 ==
8965 23:07:27.896328
8966 23:07:27.899343
8967 23:07:27.899429 TX Vref Scan disable
8968 23:07:27.905929 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8969 23:07:27.906013 == TX Byte 0 ==
8970 23:07:27.909448 u2DelayCellOfst[0]=15 cells (4 PI)
8971 23:07:27.912578 u2DelayCellOfst[1]=7 cells (2 PI)
8972 23:07:27.915665 u2DelayCellOfst[2]=0 cells (0 PI)
8973 23:07:27.919044 u2DelayCellOfst[3]=3 cells (1 PI)
8974 23:07:27.922598 u2DelayCellOfst[4]=3 cells (1 PI)
8975 23:07:27.925680 u2DelayCellOfst[5]=18 cells (5 PI)
8976 23:07:27.929680 u2DelayCellOfst[6]=15 cells (4 PI)
8977 23:07:27.932904 u2DelayCellOfst[7]=3 cells (1 PI)
8978 23:07:27.935971 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8979 23:07:27.939465 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8980 23:07:27.942853 == TX Byte 1 ==
8981 23:07:27.946002 u2DelayCellOfst[8]=0 cells (0 PI)
8982 23:07:27.946082 u2DelayCellOfst[9]=7 cells (2 PI)
8983 23:07:27.948980 u2DelayCellOfst[10]=11 cells (3 PI)
8984 23:07:27.952636 u2DelayCellOfst[11]=7 cells (2 PI)
8985 23:07:27.956043 u2DelayCellOfst[12]=15 cells (4 PI)
8986 23:07:27.959187 u2DelayCellOfst[13]=18 cells (5 PI)
8987 23:07:27.962592 u2DelayCellOfst[14]=22 cells (6 PI)
8988 23:07:27.965579 u2DelayCellOfst[15]=22 cells (6 PI)
8989 23:07:27.972505 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8990 23:07:27.975613 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8991 23:07:27.975690 DramC Write-DBI on
8992 23:07:27.975753 ==
8993 23:07:27.978694 Dram Type= 6, Freq= 0, CH_1, rank 1
8994 23:07:27.985545 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8995 23:07:27.985626 ==
8996 23:07:27.985689
8997 23:07:27.985748
8998 23:07:27.985813 TX Vref Scan disable
8999 23:07:27.989888 == TX Byte 0 ==
9000 23:07:27.992808 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
9001 23:07:27.996256 == TX Byte 1 ==
9002 23:07:27.999918 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
9003 23:07:28.003015 DramC Write-DBI off
9004 23:07:28.003101
9005 23:07:28.003169 [DATLAT]
9006 23:07:28.003232 Freq=1600, CH1 RK1
9007 23:07:28.003293
9008 23:07:28.006232 DATLAT Default: 0xf
9009 23:07:28.006355 0, 0xFFFF, sum = 0
9010 23:07:28.009737 1, 0xFFFF, sum = 0
9011 23:07:28.013145 2, 0xFFFF, sum = 0
9012 23:07:28.013250 3, 0xFFFF, sum = 0
9013 23:07:28.015846 4, 0xFFFF, sum = 0
9014 23:07:28.015957 5, 0xFFFF, sum = 0
9015 23:07:28.019452 6, 0xFFFF, sum = 0
9016 23:07:28.019575 7, 0xFFFF, sum = 0
9017 23:07:28.022622 8, 0xFFFF, sum = 0
9018 23:07:28.022745 9, 0xFFFF, sum = 0
9019 23:07:28.026219 10, 0xFFFF, sum = 0
9020 23:07:28.026401 11, 0xFFFF, sum = 0
9021 23:07:28.029578 12, 0xFFFF, sum = 0
9022 23:07:28.029730 13, 0x8FFF, sum = 0
9023 23:07:28.032563 14, 0x0, sum = 1
9024 23:07:28.032721 15, 0x0, sum = 2
9025 23:07:28.036431 16, 0x0, sum = 3
9026 23:07:28.036659 17, 0x0, sum = 4
9027 23:07:28.039337 best_step = 15
9028 23:07:28.039544
9029 23:07:28.039700 ==
9030 23:07:28.042553 Dram Type= 6, Freq= 0, CH_1, rank 1
9031 23:07:28.046438 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9032 23:07:28.046685 ==
9033 23:07:28.049789 RX Vref Scan: 0
9034 23:07:28.050107
9035 23:07:28.050364 RX Vref 0 -> 0, step: 1
9036 23:07:28.050593
9037 23:07:28.052878 RX Delay 11 -> 252, step: 4
9038 23:07:28.056456 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
9039 23:07:28.063059 iDelay=195, Bit 1, Center 128 (79 ~ 178) 100
9040 23:07:28.066024 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
9041 23:07:28.070233 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
9042 23:07:28.072720 iDelay=195, Bit 4, Center 124 (67 ~ 182) 116
9043 23:07:28.076158 iDelay=195, Bit 5, Center 140 (87 ~ 194) 108
9044 23:07:28.083106 iDelay=195, Bit 6, Center 140 (87 ~ 194) 108
9045 23:07:28.086288 iDelay=195, Bit 7, Center 124 (71 ~ 178) 108
9046 23:07:28.089350 iDelay=195, Bit 8, Center 112 (55 ~ 170) 116
9047 23:07:28.092657 iDelay=195, Bit 9, Center 114 (63 ~ 166) 104
9048 23:07:28.096268 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9049 23:07:28.102921 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
9050 23:07:28.106180 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
9051 23:07:28.109349 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
9052 23:07:28.112622 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
9053 23:07:28.119638 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
9054 23:07:28.120247 ==
9055 23:07:28.122806 Dram Type= 6, Freq= 0, CH_1, rank 1
9056 23:07:28.125864 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9057 23:07:28.126353 ==
9058 23:07:28.126736 DQS Delay:
9059 23:07:28.129097 DQS0 = 0, DQS1 = 0
9060 23:07:28.129575 DQM Delay:
9061 23:07:28.132655 DQM0 = 129, DQM1 = 125
9062 23:07:28.133116 DQ Delay:
9063 23:07:28.136010 DQ0 =134, DQ1 =128, DQ2 =118, DQ3 =126
9064 23:07:28.139055 DQ4 =124, DQ5 =140, DQ6 =140, DQ7 =124
9065 23:07:28.142374 DQ8 =112, DQ9 =114, DQ10 =128, DQ11 =120
9066 23:07:28.145599 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =136
9067 23:07:28.146075
9068 23:07:28.146452
9069 23:07:28.148836
9070 23:07:28.149306 [DramC_TX_OE_Calibration] TA2
9071 23:07:28.152583 Original DQ_B0 (3 6) =30, OEN = 27
9072 23:07:28.155610 Original DQ_B1 (3 6) =30, OEN = 27
9073 23:07:28.159354 24, 0x0, End_B0=24 End_B1=24
9074 23:07:28.162118 25, 0x0, End_B0=25 End_B1=25
9075 23:07:28.165598 26, 0x0, End_B0=26 End_B1=26
9076 23:07:28.166074 27, 0x0, End_B0=27 End_B1=27
9077 23:07:28.168928 28, 0x0, End_B0=28 End_B1=28
9078 23:07:28.172066 29, 0x0, End_B0=29 End_B1=29
9079 23:07:28.175422 30, 0x0, End_B0=30 End_B1=30
9080 23:07:28.178507 31, 0x4141, End_B0=30 End_B1=30
9081 23:07:28.179153 Byte0 end_step=30 best_step=27
9082 23:07:28.181895 Byte1 end_step=30 best_step=27
9083 23:07:28.185440 Byte0 TX OE(2T, 0.5T) = (3, 3)
9084 23:07:28.188361 Byte1 TX OE(2T, 0.5T) = (3, 3)
9085 23:07:28.188837
9086 23:07:28.189217
9087 23:07:28.198792 [DQSOSCAuto] RK1, (LSB)MR18= 0xf1b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 402 ps
9088 23:07:28.199453 CH1 RK1: MR19=303, MR18=F1B
9089 23:07:28.205113 CH1_RK1: MR19=0x303, MR18=0xF1B, DQSOSC=396, MR23=63, INC=23, DEC=15
9090 23:07:28.208594 [RxdqsGatingPostProcess] freq 1600
9091 23:07:28.215318 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9092 23:07:28.218561 best DQS0 dly(2T, 0.5T) = (1, 1)
9093 23:07:28.219044 best DQS1 dly(2T, 0.5T) = (1, 1)
9094 23:07:28.221764 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9095 23:07:28.225031 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9096 23:07:28.228451 best DQS0 dly(2T, 0.5T) = (1, 1)
9097 23:07:28.231979 best DQS1 dly(2T, 0.5T) = (1, 1)
9098 23:07:28.234871 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9099 23:07:28.238286 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9100 23:07:28.241515 Pre-setting of DQS Precalculation
9101 23:07:28.245185 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9102 23:07:28.254672 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9103 23:07:28.261390 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9104 23:07:28.261825
9105 23:07:28.262172
9106 23:07:28.264850 [Calibration Summary] 3200 Mbps
9107 23:07:28.265279 CH 0, Rank 0
9108 23:07:28.267985 SW Impedance : PASS
9109 23:07:28.271278 DUTY Scan : NO K
9110 23:07:28.271693 ZQ Calibration : PASS
9111 23:07:28.274402 Jitter Meter : NO K
9112 23:07:28.274877 CBT Training : PASS
9113 23:07:28.277668 Write leveling : PASS
9114 23:07:28.281396 RX DQS gating : PASS
9115 23:07:28.281829 RX DQ/DQS(RDDQC) : PASS
9116 23:07:28.284313 TX DQ/DQS : PASS
9117 23:07:28.287699 RX DATLAT : PASS
9118 23:07:28.288270 RX DQ/DQS(Engine): PASS
9119 23:07:28.291314 TX OE : PASS
9120 23:07:28.291748 All Pass.
9121 23:07:28.292105
9122 23:07:28.294180 CH 0, Rank 1
9123 23:07:28.294609 SW Impedance : PASS
9124 23:07:28.297923 DUTY Scan : NO K
9125 23:07:28.301397 ZQ Calibration : PASS
9126 23:07:28.301832 Jitter Meter : NO K
9127 23:07:28.304357 CBT Training : PASS
9128 23:07:28.307494 Write leveling : PASS
9129 23:07:28.307921 RX DQS gating : PASS
9130 23:07:28.311173 RX DQ/DQS(RDDQC) : PASS
9131 23:07:28.314540 TX DQ/DQS : PASS
9132 23:07:28.314971 RX DATLAT : PASS
9133 23:07:28.317811 RX DQ/DQS(Engine): PASS
9134 23:07:28.320843 TX OE : PASS
9135 23:07:28.321286 All Pass.
9136 23:07:28.321638
9137 23:07:28.321946 CH 1, Rank 0
9138 23:07:28.323934 SW Impedance : PASS
9139 23:07:28.327667 DUTY Scan : NO K
9140 23:07:28.328093 ZQ Calibration : PASS
9141 23:07:28.330995 Jitter Meter : NO K
9142 23:07:28.334278 CBT Training : PASS
9143 23:07:28.334706 Write leveling : PASS
9144 23:07:28.337511 RX DQS gating : PASS
9145 23:07:28.337946 RX DQ/DQS(RDDQC) : PASS
9146 23:07:28.341253 TX DQ/DQS : PASS
9147 23:07:28.343838 RX DATLAT : PASS
9148 23:07:28.344308 RX DQ/DQS(Engine): PASS
9149 23:07:28.347551 TX OE : PASS
9150 23:07:28.347981 All Pass.
9151 23:07:28.348411
9152 23:07:28.350852 CH 1, Rank 1
9153 23:07:28.351307 SW Impedance : PASS
9154 23:07:28.353909 DUTY Scan : NO K
9155 23:07:28.357451 ZQ Calibration : PASS
9156 23:07:28.357889 Jitter Meter : NO K
9157 23:07:28.360573 CBT Training : PASS
9158 23:07:28.364062 Write leveling : PASS
9159 23:07:28.364548 RX DQS gating : PASS
9160 23:07:28.367264 RX DQ/DQS(RDDQC) : PASS
9161 23:07:28.370539 TX DQ/DQS : PASS
9162 23:07:28.370984 RX DATLAT : PASS
9163 23:07:28.374375 RX DQ/DQS(Engine): PASS
9164 23:07:28.377067 TX OE : PASS
9165 23:07:28.377500 All Pass.
9166 23:07:28.377837
9167 23:07:28.378248 DramC Write-DBI on
9168 23:07:28.380748 PER_BANK_REFRESH: Hybrid Mode
9169 23:07:28.383773 TX_TRACKING: ON
9170 23:07:28.390302 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9171 23:07:28.400441 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9172 23:07:28.407328 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9173 23:07:28.410465 [FAST_K] Save calibration result to emmc
9174 23:07:28.413517 sync common calibartion params.
9175 23:07:28.416764 sync cbt_mode0:1, 1:1
9176 23:07:28.417194 dram_init: ddr_geometry: 2
9177 23:07:28.420005 dram_init: ddr_geometry: 2
9178 23:07:28.423834 dram_init: ddr_geometry: 2
9179 23:07:28.424301 0:dram_rank_size:100000000
9180 23:07:28.426752 1:dram_rank_size:100000000
9181 23:07:28.433513 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9182 23:07:28.436843 DFS_SHUFFLE_HW_MODE: ON
9183 23:07:28.439936 dramc_set_vcore_voltage set vcore to 725000
9184 23:07:28.440402 Read voltage for 1600, 0
9185 23:07:28.443264 Vio18 = 0
9186 23:07:28.443690 Vcore = 725000
9187 23:07:28.444040 Vdram = 0
9188 23:07:28.446576 Vddq = 0
9189 23:07:28.447000 Vmddr = 0
9190 23:07:28.449747 switch to 3200 Mbps bootup
9191 23:07:28.450176 [DramcRunTimeConfig]
9192 23:07:28.450531 PHYPLL
9193 23:07:28.453171 DPM_CONTROL_AFTERK: ON
9194 23:07:28.457027 PER_BANK_REFRESH: ON
9195 23:07:28.457463 REFRESH_OVERHEAD_REDUCTION: ON
9196 23:07:28.460273 CMD_PICG_NEW_MODE: OFF
9197 23:07:28.463140 XRTWTW_NEW_MODE: ON
9198 23:07:28.463569 XRTRTR_NEW_MODE: ON
9199 23:07:28.466590 TX_TRACKING: ON
9200 23:07:28.467036 RDSEL_TRACKING: OFF
9201 23:07:28.470414 DQS Precalculation for DVFS: ON
9202 23:07:28.470842 RX_TRACKING: OFF
9203 23:07:28.473233 HW_GATING DBG: ON
9204 23:07:28.476455 ZQCS_ENABLE_LP4: ON
9205 23:07:28.477079 RX_PICG_NEW_MODE: ON
9206 23:07:28.480256 TX_PICG_NEW_MODE: ON
9207 23:07:28.480739 ENABLE_RX_DCM_DPHY: ON
9208 23:07:28.482995 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9209 23:07:28.486184 DUMMY_READ_FOR_TRACKING: OFF
9210 23:07:28.489495 !!! SPM_CONTROL_AFTERK: OFF
9211 23:07:28.493286 !!! SPM could not control APHY
9212 23:07:28.493884 IMPEDANCE_TRACKING: ON
9213 23:07:28.496310 TEMP_SENSOR: ON
9214 23:07:28.496736 HW_SAVE_FOR_SR: OFF
9215 23:07:28.500095 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9216 23:07:28.502928 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9217 23:07:28.506236 Read ODT Tracking: ON
9218 23:07:28.510108 Refresh Rate DeBounce: ON
9219 23:07:28.510525 DFS_NO_QUEUE_FLUSH: ON
9220 23:07:28.513230 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9221 23:07:28.516311 ENABLE_DFS_RUNTIME_MRW: OFF
9222 23:07:28.519603 DDR_RESERVE_NEW_MODE: ON
9223 23:07:28.520028 MR_CBT_SWITCH_FREQ: ON
9224 23:07:28.522891 =========================
9225 23:07:28.541229 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9226 23:07:28.544677 dram_init: ddr_geometry: 2
9227 23:07:28.562954 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9228 23:07:28.566281 dram_init: dram init end (result: 0)
9229 23:07:28.572860 DRAM-K: Full calibration passed in 24564 msecs
9230 23:07:28.576276 MRC: failed to locate region type 0.
9231 23:07:28.576788 DRAM rank0 size:0x100000000,
9232 23:07:28.579526 DRAM rank1 size=0x100000000
9233 23:07:28.589218 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9234 23:07:28.595780 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9235 23:07:28.602894 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9236 23:07:28.609299 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9237 23:07:28.612551 DRAM rank0 size:0x100000000,
9238 23:07:28.616029 DRAM rank1 size=0x100000000
9239 23:07:28.616536 CBMEM:
9240 23:07:28.619091 IMD: root @ 0xfffff000 254 entries.
9241 23:07:28.622534 IMD: root @ 0xffffec00 62 entries.
9242 23:07:28.625666 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9243 23:07:28.628920 WARNING: RO_VPD is uninitialized or empty.
9244 23:07:28.635585 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9245 23:07:28.643099 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9246 23:07:28.655453 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9247 23:07:28.666868 BS: romstage times (exec / console): total (unknown) / 24027 ms
9248 23:07:28.667488
9249 23:07:28.667862
9250 23:07:28.677019 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9251 23:07:28.680545 ARM64: Exception handlers installed.
9252 23:07:28.683476 ARM64: Testing exception
9253 23:07:28.687282 ARM64: Done test exception
9254 23:07:28.687756 Enumerating buses...
9255 23:07:28.690074 Show all devs... Before device enumeration.
9256 23:07:28.693664 Root Device: enabled 1
9257 23:07:28.696777 CPU_CLUSTER: 0: enabled 1
9258 23:07:28.697290 CPU: 00: enabled 1
9259 23:07:28.700573 Compare with tree...
9260 23:07:28.701044 Root Device: enabled 1
9261 23:07:28.703435 CPU_CLUSTER: 0: enabled 1
9262 23:07:28.706778 CPU: 00: enabled 1
9263 23:07:28.707260 Root Device scanning...
9264 23:07:28.710151 scan_static_bus for Root Device
9265 23:07:28.713157 CPU_CLUSTER: 0 enabled
9266 23:07:28.716498 scan_static_bus for Root Device done
9267 23:07:28.720330 scan_bus: bus Root Device finished in 8 msecs
9268 23:07:28.720933 done
9269 23:07:28.726512 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9270 23:07:28.729701 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9271 23:07:28.736728 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9272 23:07:28.739847 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9273 23:07:28.743384 Allocating resources...
9274 23:07:28.746293 Reading resources...
9275 23:07:28.749984 Root Device read_resources bus 0 link: 0
9276 23:07:28.750409 DRAM rank0 size:0x100000000,
9277 23:07:28.753089 DRAM rank1 size=0x100000000
9278 23:07:28.756320 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9279 23:07:28.759445 CPU: 00 missing read_resources
9280 23:07:28.766307 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9281 23:07:28.769307 Root Device read_resources bus 0 link: 0 done
9282 23:07:28.769737 Done reading resources.
9283 23:07:28.776135 Show resources in subtree (Root Device)...After reading.
9284 23:07:28.779366 Root Device child on link 0 CPU_CLUSTER: 0
9285 23:07:28.782585 CPU_CLUSTER: 0 child on link 0 CPU: 00
9286 23:07:28.792305 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9287 23:07:28.792740 CPU: 00
9288 23:07:28.796508 Root Device assign_resources, bus 0 link: 0
9289 23:07:28.799285 CPU_CLUSTER: 0 missing set_resources
9290 23:07:28.805865 Root Device assign_resources, bus 0 link: 0 done
9291 23:07:28.806279 Done setting resources.
9292 23:07:28.812657 Show resources in subtree (Root Device)...After assigning values.
9293 23:07:28.815645 Root Device child on link 0 CPU_CLUSTER: 0
9294 23:07:28.819047 CPU_CLUSTER: 0 child on link 0 CPU: 00
9295 23:07:28.829053 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9296 23:07:28.829470 CPU: 00
9297 23:07:28.832190 Done allocating resources.
9298 23:07:28.838870 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9299 23:07:28.839287 Enabling resources...
9300 23:07:28.839632 done.
9301 23:07:28.845886 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9302 23:07:28.846456 Initializing devices...
9303 23:07:28.848949 Root Device init
9304 23:07:28.852314 init hardware done!
9305 23:07:28.852739 0x00000018: ctrlr->caps
9306 23:07:28.855850 52.000 MHz: ctrlr->f_max
9307 23:07:28.858620 0.400 MHz: ctrlr->f_min
9308 23:07:28.859062 0x40ff8080: ctrlr->voltages
9309 23:07:28.861936 sclk: 390625
9310 23:07:28.862362 Bus Width = 1
9311 23:07:28.862720 sclk: 390625
9312 23:07:28.865440 Bus Width = 1
9313 23:07:28.865870 Early init status = 3
9314 23:07:28.871920 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9315 23:07:28.875346 in-header: 03 fc 00 00 01 00 00 00
9316 23:07:28.878610 in-data: 00
9317 23:07:28.882245 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9318 23:07:28.886847 in-header: 03 fd 00 00 00 00 00 00
9319 23:07:28.890034 in-data:
9320 23:07:28.893353 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9321 23:07:28.897725 in-header: 03 fc 00 00 01 00 00 00
9322 23:07:28.900758 in-data: 00
9323 23:07:28.903971 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9324 23:07:28.909893 in-header: 03 fd 00 00 00 00 00 00
9325 23:07:28.913095 in-data:
9326 23:07:28.916306 [SSUSB] Setting up USB HOST controller...
9327 23:07:28.919643 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9328 23:07:28.922903 [SSUSB] phy power-on done.
9329 23:07:28.926380 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9330 23:07:28.933196 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9331 23:07:28.936308 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9332 23:07:28.943264 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9333 23:07:28.949590 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9334 23:07:28.955820 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9335 23:07:28.962400 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9336 23:07:28.969231 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9337 23:07:28.972497 SPM: binary array size = 0x9dc
9338 23:07:28.975813 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9339 23:07:28.982553 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9340 23:07:28.988869 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9341 23:07:28.995633 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9342 23:07:28.998799 configure_display: Starting display init
9343 23:07:29.032697 anx7625_power_on_init: Init interface.
9344 23:07:29.036137 anx7625_disable_pd_protocol: Disabled PD feature.
9345 23:07:29.039731 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9346 23:07:29.067180 anx7625_start_dp_work: Secure OCM version=00
9347 23:07:29.070355 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9348 23:07:29.085437 sp_tx_get_edid_block: EDID Block = 1
9349 23:07:29.187802 Extracted contents:
9350 23:07:29.191172 header: 00 ff ff ff ff ff ff 00
9351 23:07:29.194191 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9352 23:07:29.197518 version: 01 04
9353 23:07:29.200914 basic params: 95 1f 11 78 0a
9354 23:07:29.204138 chroma info: 76 90 94 55 54 90 27 21 50 54
9355 23:07:29.207886 established: 00 00 00
9356 23:07:29.214488 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9357 23:07:29.217362 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9358 23:07:29.223995 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9359 23:07:29.230620 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9360 23:07:29.237189 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9361 23:07:29.240899 extensions: 00
9362 23:07:29.240983 checksum: fb
9363 23:07:29.241054
9364 23:07:29.243905 Manufacturer: IVO Model 57d Serial Number 0
9365 23:07:29.247427 Made week 0 of 2020
9366 23:07:29.247521 EDID version: 1.4
9367 23:07:29.250879 Digital display
9368 23:07:29.253777 6 bits per primary color channel
9369 23:07:29.253889 DisplayPort interface
9370 23:07:29.257828 Maximum image size: 31 cm x 17 cm
9371 23:07:29.260476 Gamma: 220%
9372 23:07:29.260591 Check DPMS levels
9373 23:07:29.264142 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9374 23:07:29.270787 First detailed timing is preferred timing
9375 23:07:29.271001 Established timings supported:
9376 23:07:29.273642 Standard timings supported:
9377 23:07:29.277183 Detailed timings
9378 23:07:29.280320 Hex of detail: 383680a07038204018303c0035ae10000019
9379 23:07:29.283780 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9380 23:07:29.290809 0780 0798 07c8 0820 hborder 0
9381 23:07:29.293913 0438 043b 0447 0458 vborder 0
9382 23:07:29.297101 -hsync -vsync
9383 23:07:29.297472 Did detailed timing
9384 23:07:29.303765 Hex of detail: 000000000000000000000000000000000000
9385 23:07:29.307126 Manufacturer-specified data, tag 0
9386 23:07:29.310484 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9387 23:07:29.314110 ASCII string: InfoVision
9388 23:07:29.317000 Hex of detail: 000000fe00523134304e574635205248200a
9389 23:07:29.320125 ASCII string: R140NWF5 RH
9390 23:07:29.320542 Checksum
9391 23:07:29.323878 Checksum: 0xfb (valid)
9392 23:07:29.327076 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9393 23:07:29.330159 DSI data_rate: 832800000 bps
9394 23:07:29.337320 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9395 23:07:29.340340 anx7625_parse_edid: pixelclock(138800).
9396 23:07:29.343513 hactive(1920), hsync(48), hfp(24), hbp(88)
9397 23:07:29.346838 vactive(1080), vsync(12), vfp(3), vbp(17)
9398 23:07:29.350244 anx7625_dsi_config: config dsi.
9399 23:07:29.356738 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9400 23:07:29.370007 anx7625_dsi_config: success to config DSI
9401 23:07:29.373733 anx7625_dp_start: MIPI phy setup OK.
9402 23:07:29.376844 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9403 23:07:29.380560 mtk_ddp_mode_set invalid vrefresh 60
9404 23:07:29.383257 main_disp_path_setup
9405 23:07:29.383746 ovl_layer_smi_id_en
9406 23:07:29.386750 ovl_layer_smi_id_en
9407 23:07:29.387307 ccorr_config
9408 23:07:29.387710 aal_config
9409 23:07:29.389882 gamma_config
9410 23:07:29.390308 postmask_config
9411 23:07:29.393155 dither_config
9412 23:07:29.396844 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9413 23:07:29.403496 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9414 23:07:29.406693 Root Device init finished in 554 msecs
9415 23:07:29.410107 CPU_CLUSTER: 0 init
9416 23:07:29.416626 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9417 23:07:29.419863 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9418 23:07:29.423501 APU_MBOX 0x190000b0 = 0x10001
9419 23:07:29.426499 APU_MBOX 0x190001b0 = 0x10001
9420 23:07:29.429605 APU_MBOX 0x190005b0 = 0x10001
9421 23:07:29.433011 APU_MBOX 0x190006b0 = 0x10001
9422 23:07:29.436342 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9423 23:07:29.449465 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9424 23:07:29.461623 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9425 23:07:29.468068 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9426 23:07:29.479873 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9427 23:07:29.488886 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9428 23:07:29.492007 CPU_CLUSTER: 0 init finished in 81 msecs
9429 23:07:29.495530 Devices initialized
9430 23:07:29.498630 Show all devs... After init.
9431 23:07:29.499194 Root Device: enabled 1
9432 23:07:29.501996 CPU_CLUSTER: 0: enabled 1
9433 23:07:29.505471 CPU: 00: enabled 1
9434 23:07:29.509002 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9435 23:07:29.512459 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9436 23:07:29.515294 ELOG: NV offset 0x57f000 size 0x1000
9437 23:07:29.522332 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9438 23:07:29.528566 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9439 23:07:29.531833 ELOG: Event(17) added with size 13 at 2023-12-01 23:07:29 UTC
9440 23:07:29.538716 out: cmd=0x121: 03 db 21 01 00 00 00 00
9441 23:07:29.541729 in-header: 03 60 00 00 2c 00 00 00
9442 23:07:29.552115 in-data: ff 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9443 23:07:29.558430 ELOG: Event(A1) added with size 10 at 2023-12-01 23:07:29 UTC
9444 23:07:29.565228 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9445 23:07:29.571788 ELOG: Event(A0) added with size 9 at 2023-12-01 23:07:29 UTC
9446 23:07:29.574749 elog_add_boot_reason: Logged dev mode boot
9447 23:07:29.581608 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9448 23:07:29.582127 Finalize devices...
9449 23:07:29.584941 Devices finalized
9450 23:07:29.588278 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9451 23:07:29.591772 Writing coreboot table at 0xffe64000
9452 23:07:29.594788 0. 000000000010a000-0000000000113fff: RAMSTAGE
9453 23:07:29.598014 1. 0000000040000000-00000000400fffff: RAM
9454 23:07:29.604772 2. 0000000040100000-000000004032afff: RAMSTAGE
9455 23:07:29.607882 3. 000000004032b000-00000000545fffff: RAM
9456 23:07:29.611480 4. 0000000054600000-000000005465ffff: BL31
9457 23:07:29.614618 5. 0000000054660000-00000000ffe63fff: RAM
9458 23:07:29.621166 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9459 23:07:29.624863 7. 0000000100000000-000000023fffffff: RAM
9460 23:07:29.627933 Passing 5 GPIOs to payload:
9461 23:07:29.631681 NAME | PORT | POLARITY | VALUE
9462 23:07:29.635091 EC in RW | 0x000000aa | low | undefined
9463 23:07:29.641530 EC interrupt | 0x00000005 | low | undefined
9464 23:07:29.644550 TPM interrupt | 0x000000ab | high | undefined
9465 23:07:29.651492 SD card detect | 0x00000011 | high | undefined
9466 23:07:29.654481 speaker enable | 0x00000093 | high | undefined
9467 23:07:29.657868 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9468 23:07:29.660913 in-header: 03 f9 00 00 02 00 00 00
9469 23:07:29.664453 in-data: 02 00
9470 23:07:29.665068 ADC[4]: Raw value=897410 ID=7
9471 23:07:29.667754 ADC[3]: Raw value=213440 ID=1
9472 23:07:29.671343 RAM Code: 0x71
9473 23:07:29.671943 ADC[6]: Raw value=74722 ID=0
9474 23:07:29.674620 ADC[5]: Raw value=211960 ID=1
9475 23:07:29.677625 SKU Code: 0x1
9476 23:07:29.680754 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 59ba
9477 23:07:29.684537 coreboot table: 964 bytes.
9478 23:07:29.687546 IMD ROOT 0. 0xfffff000 0x00001000
9479 23:07:29.690788 IMD SMALL 1. 0xffffe000 0x00001000
9480 23:07:29.694342 RO MCACHE 2. 0xffffc000 0x00001104
9481 23:07:29.697548 CONSOLE 3. 0xfff7c000 0x00080000
9482 23:07:29.700854 FMAP 4. 0xfff7b000 0x00000452
9483 23:07:29.704010 TIME STAMP 5. 0xfff7a000 0x00000910
9484 23:07:29.707257 VBOOT WORK 6. 0xfff66000 0x00014000
9485 23:07:29.710641 RAMOOPS 7. 0xffe66000 0x00100000
9486 23:07:29.714164 COREBOOT 8. 0xffe64000 0x00002000
9487 23:07:29.717647 IMD small region:
9488 23:07:29.720966 IMD ROOT 0. 0xffffec00 0x00000400
9489 23:07:29.724042 VPD 1. 0xffffeb80 0x0000006c
9490 23:07:29.727689 MMC STATUS 2. 0xffffeb60 0x00000004
9491 23:07:29.730484 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9492 23:07:29.733768 Probing TPM: done!
9493 23:07:29.737835 Connected to device vid:did:rid of 1ae0:0028:00
9494 23:07:29.747945 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9495 23:07:29.751295 Initialized TPM device CR50 revision 0
9496 23:07:29.755558 Checking cr50 for pending updates
9497 23:07:29.758600 Reading cr50 TPM mode
9498 23:07:29.767335 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9499 23:07:29.773465 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9500 23:07:29.813757 read SPI 0x3990ec 0x4f1b0: 34850 us, 9297 KB/s, 74.376 Mbps
9501 23:07:29.817546 Checking segment from ROM address 0x40100000
9502 23:07:29.820785 Checking segment from ROM address 0x4010001c
9503 23:07:29.827415 Loading segment from ROM address 0x40100000
9504 23:07:29.827876 code (compression=0)
9505 23:07:29.837431 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9506 23:07:29.843984 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9507 23:07:29.844454 it's not compressed!
9508 23:07:29.850639 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9509 23:07:29.853628 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9510 23:07:29.874518 Loading segment from ROM address 0x4010001c
9511 23:07:29.875010 Entry Point 0x80000000
9512 23:07:29.877881 Loaded segments
9513 23:07:29.881084 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9514 23:07:29.887939 Jumping to boot code at 0x80000000(0xffe64000)
9515 23:07:29.894698 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9516 23:07:29.901208 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9517 23:07:29.909165 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9518 23:07:29.912255 Checking segment from ROM address 0x40100000
9519 23:07:29.915516 Checking segment from ROM address 0x4010001c
9520 23:07:29.922075 Loading segment from ROM address 0x40100000
9521 23:07:29.922493 code (compression=1)
9522 23:07:29.928888 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9523 23:07:29.938637 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9524 23:07:29.939108 using LZMA
9525 23:07:29.947103 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9526 23:07:29.953516 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9527 23:07:29.956697 Loading segment from ROM address 0x4010001c
9528 23:07:29.956805 Entry Point 0x54601000
9529 23:07:29.960380 Loaded segments
9530 23:07:29.963156 NOTICE: MT8192 bl31_setup
9531 23:07:29.970210 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9532 23:07:29.973875 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9533 23:07:29.977089 WARNING: region 0:
9534 23:07:29.980162 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9535 23:07:29.980267 WARNING: region 1:
9536 23:07:29.987044 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9537 23:07:29.990131 WARNING: region 2:
9538 23:07:29.993604 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9539 23:07:29.997398 WARNING: region 3:
9540 23:07:30.000086 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9541 23:07:30.003367 WARNING: region 4:
9542 23:07:30.010168 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9543 23:07:30.010249 WARNING: region 5:
9544 23:07:30.013837 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9545 23:07:30.016701 WARNING: region 6:
9546 23:07:30.020113 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9547 23:07:30.023733 WARNING: region 7:
9548 23:07:30.026860 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9549 23:07:30.033376 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9550 23:07:30.036894 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9551 23:07:30.039894 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9552 23:07:30.047326 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9553 23:07:30.050384 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9554 23:07:30.053737 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9555 23:07:30.060121 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9556 23:07:30.064064 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9557 23:07:30.070427 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9558 23:07:30.073232 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9559 23:07:30.076730 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9560 23:07:30.083916 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9561 23:07:30.086736 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9562 23:07:30.090574 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9563 23:07:30.097396 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9564 23:07:30.100602 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9565 23:07:30.107105 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9566 23:07:30.110695 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9567 23:07:30.113918 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9568 23:07:30.120837 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9569 23:07:30.123915 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9570 23:07:30.127089 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9571 23:07:30.133796 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9572 23:07:30.137357 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9573 23:07:30.143970 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9574 23:07:30.147286 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9575 23:07:30.150528 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9576 23:07:30.157234 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9577 23:07:30.160364 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9578 23:07:30.166928 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9579 23:07:30.170270 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9580 23:07:30.174242 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9581 23:07:30.180466 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9582 23:07:30.183922 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9583 23:07:30.187354 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9584 23:07:30.190442 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9585 23:07:30.197113 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9586 23:07:30.200907 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9587 23:07:30.203672 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9588 23:07:30.207288 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9589 23:07:30.214242 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9590 23:07:30.217181 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9591 23:07:30.220905 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9592 23:07:30.223714 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9593 23:07:30.230696 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9594 23:07:30.233809 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9595 23:07:30.236934 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9596 23:07:30.240632 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9597 23:07:30.247026 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9598 23:07:30.250289 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9599 23:07:30.257271 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9600 23:07:30.260178 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9601 23:07:30.267178 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9602 23:07:30.270367 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9603 23:07:30.273928 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9604 23:07:30.280421 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9605 23:07:30.283653 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9606 23:07:30.290185 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9607 23:07:30.293722 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9608 23:07:30.300457 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9609 23:07:30.303708 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9610 23:07:30.306747 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9611 23:07:30.313386 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9612 23:07:30.316600 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9613 23:07:30.323550 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9614 23:07:30.326634 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9615 23:07:30.333656 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9616 23:07:30.336699 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9617 23:07:30.340033 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9618 23:07:30.347073 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9619 23:07:30.350320 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9620 23:07:30.356943 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9621 23:07:30.359995 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9622 23:07:30.366769 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9623 23:07:30.370147 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9624 23:07:30.373636 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9625 23:07:30.380469 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9626 23:07:30.383429 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9627 23:07:30.390074 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9628 23:07:30.393685 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9629 23:07:30.400151 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9630 23:07:30.403595 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9631 23:07:30.410408 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9632 23:07:30.413780 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9633 23:07:30.417020 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9634 23:07:30.423374 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9635 23:07:30.426710 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9636 23:07:30.433277 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9637 23:07:30.436592 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9638 23:07:30.443355 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9639 23:07:30.446650 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9640 23:07:30.449932 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9641 23:07:30.456386 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9642 23:07:30.459937 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9643 23:07:30.466447 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9644 23:07:30.469701 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9645 23:07:30.476522 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9646 23:07:30.479749 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9647 23:07:30.483086 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9648 23:07:30.486489 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9649 23:07:30.489723 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9650 23:07:30.496285 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9651 23:07:30.499559 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9652 23:07:30.506530 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9653 23:07:30.509750 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9654 23:07:30.513210 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9655 23:07:30.519700 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9656 23:07:30.523350 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9657 23:07:30.529824 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9658 23:07:30.533089 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9659 23:07:30.536432 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9660 23:07:30.543272 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9661 23:07:30.546547 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9662 23:07:30.552659 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9663 23:07:30.555951 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9664 23:07:30.559120 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9665 23:07:30.565869 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9666 23:07:30.569377 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9667 23:07:30.572385 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9668 23:07:30.579049 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9669 23:07:30.582827 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9670 23:07:30.585936 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9671 23:07:30.589097 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9672 23:07:30.596060 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9673 23:07:30.598922 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9674 23:07:30.602676 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9675 23:07:30.609389 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9676 23:07:30.612178 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9677 23:07:30.618781 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9678 23:07:30.622627 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9679 23:07:30.625510 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9680 23:07:30.632399 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9681 23:07:30.635655 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9682 23:07:30.642333 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9683 23:07:30.645876 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9684 23:07:30.649197 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9685 23:07:30.655694 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9686 23:07:30.658976 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9687 23:07:30.662419 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9688 23:07:30.668981 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9689 23:07:30.672626 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9690 23:07:30.679253 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9691 23:07:30.682285 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9692 23:07:30.685931 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9693 23:07:30.692813 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9694 23:07:30.696100 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9695 23:07:30.698984 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9696 23:07:30.705835 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9697 23:07:30.709681 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9698 23:07:30.715734 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9699 23:07:30.718927 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9700 23:07:30.722483 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9701 23:07:30.729160 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9702 23:07:30.732574 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9703 23:07:30.739133 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9704 23:07:30.742427 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9705 23:07:30.745721 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9706 23:07:30.752150 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9707 23:07:30.755655 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9708 23:07:30.762622 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9709 23:07:30.765916 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9710 23:07:30.769072 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9711 23:07:30.775401 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9712 23:07:30.778734 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9713 23:07:30.785260 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9714 23:07:30.788470 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9715 23:07:30.791945 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9716 23:07:30.798703 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9717 23:07:30.801903 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9718 23:07:30.808286 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9719 23:07:30.811723 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9720 23:07:30.815108 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9721 23:07:30.821645 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9722 23:07:30.825263 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9723 23:07:30.828365 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9724 23:07:30.835147 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9725 23:07:30.838342 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9726 23:07:30.844811 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9727 23:07:30.848705 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9728 23:07:30.851427 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9729 23:07:30.858065 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9730 23:07:30.861446 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9731 23:07:30.868714 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9732 23:07:30.871935 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9733 23:07:30.874869 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9734 23:07:30.881673 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9735 23:07:30.884887 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9736 23:07:30.891589 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9737 23:07:30.894673 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9738 23:07:30.898842 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9739 23:07:30.905446 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9740 23:07:30.908648 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9741 23:07:30.915304 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9742 23:07:30.918343 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9743 23:07:30.922027 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9744 23:07:30.928314 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9745 23:07:30.931875 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9746 23:07:30.938351 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9747 23:07:30.941608 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9748 23:07:30.948258 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9749 23:07:30.951453 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9750 23:07:30.955216 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9751 23:07:30.961827 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9752 23:07:30.964587 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9753 23:07:30.971642 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9754 23:07:30.974856 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9755 23:07:30.981644 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9756 23:07:30.985173 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9757 23:07:30.987962 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9758 23:07:30.994548 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9759 23:07:30.997706 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9760 23:07:31.004379 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9761 23:07:31.007692 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9762 23:07:31.011262 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9763 23:07:31.018059 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9764 23:07:31.021151 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9765 23:07:31.027701 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9766 23:07:31.030850 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9767 23:07:31.037527 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9768 23:07:31.040850 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9769 23:07:31.044263 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9770 23:07:31.050908 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9771 23:07:31.054019 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9772 23:07:31.060606 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9773 23:07:31.064383 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9774 23:07:31.070501 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9775 23:07:31.074005 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9776 23:07:31.077048 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9777 23:07:31.083717 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9778 23:07:31.087140 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9779 23:07:31.090316 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9780 23:07:31.094160 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9781 23:07:31.100836 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9782 23:07:31.103431 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9783 23:07:31.106862 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9784 23:07:31.113451 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9785 23:07:31.117055 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9786 23:07:31.123346 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9787 23:07:31.126615 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9788 23:07:31.129927 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9789 23:07:31.136582 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9790 23:07:31.139708 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9791 23:07:31.142944 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9792 23:07:31.149932 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9793 23:07:31.153000 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9794 23:07:31.156181 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9795 23:07:31.163252 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9796 23:07:31.166179 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9797 23:07:31.172948 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9798 23:07:31.176434 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9799 23:07:31.179758 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9800 23:07:31.186750 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9801 23:07:31.189897 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9802 23:07:31.193031 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9803 23:07:31.199549 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9804 23:07:31.202596 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9805 23:07:31.209491 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9806 23:07:31.212905 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9807 23:07:31.215983 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9808 23:07:31.223274 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9809 23:07:31.225897 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9810 23:07:31.229413 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9811 23:07:31.236043 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9812 23:07:31.239034 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9813 23:07:31.242341 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9814 23:07:31.249012 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9815 23:07:31.252661 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9816 23:07:31.258800 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9817 23:07:31.262221 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9818 23:07:31.265510 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9819 23:07:31.268827 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9820 23:07:31.275877 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9821 23:07:31.278859 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9822 23:07:31.282280 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9823 23:07:31.285779 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9824 23:07:31.292266 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9825 23:07:31.295448 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9826 23:07:31.298793 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9827 23:07:31.302537 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9828 23:07:31.308766 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9829 23:07:31.311998 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9830 23:07:31.315265 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9831 23:07:31.322050 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9832 23:07:31.325244 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9833 23:07:31.329054 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9834 23:07:31.335280 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9835 23:07:31.338231 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9836 23:07:31.345370 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9837 23:07:31.348470 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9838 23:07:31.351643 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9839 23:07:31.358371 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9840 23:07:31.361587 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9841 23:07:31.368270 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9842 23:07:31.371388 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9843 23:07:31.378079 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9844 23:07:31.381575 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9845 23:07:31.384824 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9846 23:07:31.391342 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9847 23:07:31.394667 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9848 23:07:31.401468 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9849 23:07:31.404577 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9850 23:07:31.407802 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9851 23:07:31.414583 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9852 23:07:31.417683 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9853 23:07:31.424748 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9854 23:07:31.428290 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9855 23:07:31.430951 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9856 23:07:31.438009 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9857 23:07:31.441276 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9858 23:07:31.447627 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9859 23:07:31.450926 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9860 23:07:31.457454 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9861 23:07:31.460716 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9862 23:07:31.464178 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9863 23:07:31.470855 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9864 23:07:31.474142 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9865 23:07:31.480430 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9866 23:07:31.483968 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9867 23:07:31.490676 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9868 23:07:31.494431 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9869 23:07:31.498710 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9870 23:07:31.503756 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9871 23:07:31.507246 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9872 23:07:31.513917 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9873 23:07:31.517171 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9874 23:07:31.520418 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9875 23:07:31.527216 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9876 23:07:31.530480 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9877 23:07:31.537310 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9878 23:07:31.540572 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9879 23:07:31.543818 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9880 23:07:31.550189 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9881 23:07:31.553451 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9882 23:07:31.560067 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9883 23:07:31.563451 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9884 23:07:31.570122 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9885 23:07:31.573623 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9886 23:07:31.576887 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9887 23:07:31.583386 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9888 23:07:31.586615 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9889 23:07:31.593050 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9890 23:07:31.596334 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9891 23:07:31.600163 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9892 23:07:31.606575 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9893 23:07:31.609602 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9894 23:07:31.616370 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9895 23:07:31.619765 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9896 23:07:31.623615 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9897 23:07:31.629913 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9898 23:07:31.633102 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9899 23:07:31.639526 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9900 23:07:31.642799 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9901 23:07:31.649893 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9902 23:07:31.652980 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9903 23:07:31.656427 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9904 23:07:31.663123 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9905 23:07:31.666254 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9906 23:07:31.672664 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9907 23:07:31.675954 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9908 23:07:31.682863 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9909 23:07:31.685967 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9910 23:07:31.689758 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9911 23:07:31.696125 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9912 23:07:31.699186 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9913 23:07:31.705796 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9914 23:07:31.709297 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9915 23:07:31.715988 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9916 23:07:31.719173 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9917 23:07:31.725744 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9918 23:07:31.729014 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9919 23:07:31.732330 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9920 23:07:31.739181 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9921 23:07:31.742254 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9922 23:07:31.749033 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9923 23:07:31.752184 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9924 23:07:31.759295 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9925 23:07:31.762566 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9926 23:07:31.765753 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9927 23:07:31.772377 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9928 23:07:31.775982 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9929 23:07:31.782075 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9930 23:07:31.785885 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9931 23:07:31.792419 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9932 23:07:31.795557 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9933 23:07:31.798808 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9934 23:07:31.805511 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9935 23:07:31.809155 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9936 23:07:31.815266 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9937 23:07:31.818654 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9938 23:07:31.825146 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9939 23:07:31.828508 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9940 23:07:31.835304 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9941 23:07:31.838657 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9942 23:07:31.841686 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9943 23:07:31.848334 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9944 23:07:31.851727 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9945 23:07:31.858592 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9946 23:07:31.861946 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9947 23:07:31.868129 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9948 23:07:31.871558 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9949 23:07:31.874911 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9950 23:07:31.881755 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9951 23:07:31.885003 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9952 23:07:31.891812 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9953 23:07:31.894862 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9954 23:07:31.901411 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9955 23:07:31.904764 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9956 23:07:31.907932 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9957 23:07:31.914565 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9958 23:07:31.917801 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9959 23:07:31.925028 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9960 23:07:31.927863 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9961 23:07:31.934732 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9962 23:07:31.938081 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9963 23:07:31.944468 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9964 23:07:31.947649 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9965 23:07:31.954690 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9966 23:07:31.958090 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9967 23:07:31.964467 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9968 23:07:31.967780 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9969 23:07:31.974116 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9970 23:07:31.977464 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9971 23:07:31.984337 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9972 23:07:31.987478 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9973 23:07:31.994256 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9974 23:07:31.997298 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9975 23:07:32.003982 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9976 23:07:32.007333 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9977 23:07:32.014292 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9978 23:07:32.017631 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9979 23:07:32.024236 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9980 23:07:32.027355 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9981 23:07:32.033955 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9982 23:07:32.037222 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9983 23:07:32.043689 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9984 23:07:32.044109 INFO: [APUAPC] vio 0
9985 23:07:32.050402 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9986 23:07:32.053666 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9987 23:07:32.057449 INFO: [APUAPC] D0_APC_0: 0x400510
9988 23:07:32.060399 INFO: [APUAPC] D0_APC_1: 0x0
9989 23:07:32.063696 INFO: [APUAPC] D0_APC_2: 0x1540
9990 23:07:32.067024 INFO: [APUAPC] D0_APC_3: 0x0
9991 23:07:32.070203 INFO: [APUAPC] D1_APC_0: 0xffffffff
9992 23:07:32.073982 INFO: [APUAPC] D1_APC_1: 0xffffffff
9993 23:07:32.077002 INFO: [APUAPC] D1_APC_2: 0x3fffff
9994 23:07:32.080317 INFO: [APUAPC] D1_APC_3: 0x0
9995 23:07:32.083512 INFO: [APUAPC] D2_APC_0: 0xffffffff
9996 23:07:32.086677 INFO: [APUAPC] D2_APC_1: 0xffffffff
9997 23:07:32.090368 INFO: [APUAPC] D2_APC_2: 0x3fffff
9998 23:07:32.093745 INFO: [APUAPC] D2_APC_3: 0x0
9999 23:07:32.096505 INFO: [APUAPC] D3_APC_0: 0xffffffff
10000 23:07:32.100099 INFO: [APUAPC] D3_APC_1: 0xffffffff
10001 23:07:32.103230 INFO: [APUAPC] D3_APC_2: 0x3fffff
10002 23:07:32.106500 INFO: [APUAPC] D3_APC_3: 0x0
10003 23:07:32.109819 INFO: [APUAPC] D4_APC_0: 0xffffffff
10004 23:07:32.113367 INFO: [APUAPC] D4_APC_1: 0xffffffff
10005 23:07:32.116809 INFO: [APUAPC] D4_APC_2: 0x3fffff
10006 23:07:32.120117 INFO: [APUAPC] D4_APC_3: 0x0
10007 23:07:32.123169 INFO: [APUAPC] D5_APC_0: 0xffffffff
10008 23:07:32.126597 INFO: [APUAPC] D5_APC_1: 0xffffffff
10009 23:07:32.129780 INFO: [APUAPC] D5_APC_2: 0x3fffff
10010 23:07:32.133031 INFO: [APUAPC] D5_APC_3: 0x0
10011 23:07:32.136605 INFO: [APUAPC] D6_APC_0: 0xffffffff
10012 23:07:32.139430 INFO: [APUAPC] D6_APC_1: 0xffffffff
10013 23:07:32.142856 INFO: [APUAPC] D6_APC_2: 0x3fffff
10014 23:07:32.143357 INFO: [APUAPC] D6_APC_3: 0x0
10015 23:07:32.149658 INFO: [APUAPC] D7_APC_0: 0xffffffff
10016 23:07:32.152825 INFO: [APUAPC] D7_APC_1: 0xffffffff
10017 23:07:32.155895 INFO: [APUAPC] D7_APC_2: 0x3fffff
10018 23:07:32.155975 INFO: [APUAPC] D7_APC_3: 0x0
10019 23:07:32.159409 INFO: [APUAPC] D8_APC_0: 0xffffffff
10020 23:07:32.162627 INFO: [APUAPC] D8_APC_1: 0xffffffff
10021 23:07:32.165867 INFO: [APUAPC] D8_APC_2: 0x3fffff
10022 23:07:32.168986 INFO: [APUAPC] D8_APC_3: 0x0
10023 23:07:32.172235 INFO: [APUAPC] D9_APC_0: 0xffffffff
10024 23:07:32.175643 INFO: [APUAPC] D9_APC_1: 0xffffffff
10025 23:07:32.178820 INFO: [APUAPC] D9_APC_2: 0x3fffff
10026 23:07:32.182376 INFO: [APUAPC] D9_APC_3: 0x0
10027 23:07:32.185529 INFO: [APUAPC] D10_APC_0: 0xffffffff
10028 23:07:32.188935 INFO: [APUAPC] D10_APC_1: 0xffffffff
10029 23:07:32.191964 INFO: [APUAPC] D10_APC_2: 0x3fffff
10030 23:07:32.195225 INFO: [APUAPC] D10_APC_3: 0x0
10031 23:07:32.198494 INFO: [APUAPC] D11_APC_0: 0xffffffff
10032 23:07:32.202255 INFO: [APUAPC] D11_APC_1: 0xffffffff
10033 23:07:32.205440 INFO: [APUAPC] D11_APC_2: 0x3fffff
10034 23:07:32.208667 INFO: [APUAPC] D11_APC_3: 0x0
10035 23:07:32.212352 INFO: [APUAPC] D12_APC_0: 0xffffffff
10036 23:07:32.215726 INFO: [APUAPC] D12_APC_1: 0xffffffff
10037 23:07:32.221660 INFO: [APUAPC] D12_APC_2: 0x3fffff
10038 23:07:32.221745 INFO: [APUAPC] D12_APC_3: 0x0
10039 23:07:32.224894 INFO: [APUAPC] D13_APC_0: 0xffffffff
10040 23:07:32.232033 INFO: [APUAPC] D13_APC_1: 0xffffffff
10041 23:07:32.234881 INFO: [APUAPC] D13_APC_2: 0x3fffff
10042 23:07:32.234966 INFO: [APUAPC] D13_APC_3: 0x0
10043 23:07:32.241367 INFO: [APUAPC] D14_APC_0: 0xffffffff
10044 23:07:32.245071 INFO: [APUAPC] D14_APC_1: 0xffffffff
10045 23:07:32.248207 INFO: [APUAPC] D14_APC_2: 0x3fffff
10046 23:07:32.248293 INFO: [APUAPC] D14_APC_3: 0x0
10047 23:07:32.254742 INFO: [APUAPC] D15_APC_0: 0xffffffff
10048 23:07:32.257963 INFO: [APUAPC] D15_APC_1: 0xffffffff
10049 23:07:32.261264 INFO: [APUAPC] D15_APC_2: 0x3fffff
10050 23:07:32.264771 INFO: [APUAPC] D15_APC_3: 0x0
10051 23:07:32.264855 INFO: [APUAPC] APC_CON: 0x4
10052 23:07:32.267923 INFO: [NOCDAPC] D0_APC_0: 0x0
10053 23:07:32.271029 INFO: [NOCDAPC] D0_APC_1: 0x0
10054 23:07:32.274589 INFO: [NOCDAPC] D1_APC_0: 0x0
10055 23:07:32.277996 INFO: [NOCDAPC] D1_APC_1: 0xfff
10056 23:07:32.281061 INFO: [NOCDAPC] D2_APC_0: 0x0
10057 23:07:32.284434 INFO: [NOCDAPC] D2_APC_1: 0xfff
10058 23:07:32.287842 INFO: [NOCDAPC] D3_APC_0: 0x0
10059 23:07:32.290985 INFO: [NOCDAPC] D3_APC_1: 0xfff
10060 23:07:32.294286 INFO: [NOCDAPC] D4_APC_0: 0x0
10061 23:07:32.294370 INFO: [NOCDAPC] D4_APC_1: 0xfff
10062 23:07:32.297613 INFO: [NOCDAPC] D5_APC_0: 0x0
10063 23:07:32.301297 INFO: [NOCDAPC] D5_APC_1: 0xfff
10064 23:07:32.304567 INFO: [NOCDAPC] D6_APC_0: 0x0
10065 23:07:32.307674 INFO: [NOCDAPC] D6_APC_1: 0xfff
10066 23:07:32.310871 INFO: [NOCDAPC] D7_APC_0: 0x0
10067 23:07:32.314381 INFO: [NOCDAPC] D7_APC_1: 0xfff
10068 23:07:32.317603 INFO: [NOCDAPC] D8_APC_0: 0x0
10069 23:07:32.320672 INFO: [NOCDAPC] D8_APC_1: 0xfff
10070 23:07:32.324470 INFO: [NOCDAPC] D9_APC_0: 0x0
10071 23:07:32.327316 INFO: [NOCDAPC] D9_APC_1: 0xfff
10072 23:07:32.327400 INFO: [NOCDAPC] D10_APC_0: 0x0
10073 23:07:32.330929 INFO: [NOCDAPC] D10_APC_1: 0xfff
10074 23:07:32.334360 INFO: [NOCDAPC] D11_APC_0: 0x0
10075 23:07:32.337159 INFO: [NOCDAPC] D11_APC_1: 0xfff
10076 23:07:32.340700 INFO: [NOCDAPC] D12_APC_0: 0x0
10077 23:07:32.344010 INFO: [NOCDAPC] D12_APC_1: 0xfff
10078 23:07:32.347276 INFO: [NOCDAPC] D13_APC_0: 0x0
10079 23:07:32.350866 INFO: [NOCDAPC] D13_APC_1: 0xfff
10080 23:07:32.353868 INFO: [NOCDAPC] D14_APC_0: 0x0
10081 23:07:32.357595 INFO: [NOCDAPC] D14_APC_1: 0xfff
10082 23:07:32.360762 INFO: [NOCDAPC] D15_APC_0: 0x0
10083 23:07:32.363999 INFO: [NOCDAPC] D15_APC_1: 0xfff
10084 23:07:32.367267 INFO: [NOCDAPC] APC_CON: 0x4
10085 23:07:32.370747 INFO: [APUAPC] set_apusys_apc done
10086 23:07:32.373766 INFO: [DEVAPC] devapc_init done
10087 23:07:32.377230 INFO: GICv3 without legacy support detected.
10088 23:07:32.380512 INFO: ARM GICv3 driver initialized in EL3
10089 23:07:32.383944 INFO: Maximum SPI INTID supported: 639
10090 23:07:32.386736 INFO: BL31: Initializing runtime services
10091 23:07:32.393651 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10092 23:07:32.396902 INFO: SPM: enable CPC mode
10093 23:07:32.403603 INFO: mcdi ready for mcusys-off-idle and system suspend
10094 23:07:32.406791 INFO: BL31: Preparing for EL3 exit to normal world
10095 23:07:32.410094 INFO: Entry point address = 0x80000000
10096 23:07:32.413325 INFO: SPSR = 0x8
10097 23:07:32.418003
10098 23:07:32.418087
10099 23:07:32.418172
10100 23:07:32.421374 Starting depthcharge on Spherion...
10101 23:07:32.421482
10102 23:07:32.421569 Wipe memory regions:
10103 23:07:32.421668
10104 23:07:32.422524 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10105 23:07:32.422659 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10106 23:07:32.422777 Setting prompt string to ['asurada:']
10107 23:07:32.422901 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10108 23:07:32.425217 [0x00000040000000, 0x00000054600000)
10109 23:07:32.547010
10110 23:07:32.547130 [0x00000054660000, 0x00000080000000)
10111 23:07:32.807766
10112 23:07:32.807899 [0x000000821a7280, 0x000000ffe64000)
10113 23:07:33.552927
10114 23:07:33.553451 [0x00000100000000, 0x00000240000000)
10115 23:07:35.442883
10116 23:07:35.446391 Initializing XHCI USB controller at 0x11200000.
10117 23:07:36.483768
10118 23:07:36.487443 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10119 23:07:36.487533
10120 23:07:36.487617
10121 23:07:36.487697
10122 23:07:36.487999 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10124 23:07:36.588484 asurada: tftpboot 192.168.201.1 12154441/tftp-deploy-apkqk93d/kernel/image.itb 12154441/tftp-deploy-apkqk93d/kernel/cmdline
10125 23:07:36.589137 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10126 23:07:36.589605 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10127 23:07:36.593776 tftpboot 192.168.201.1 12154441/tftp-deploy-apkqk93d/kernel/image.itp-deploy-apkqk93d/kernel/cmdline
10128 23:07:36.593883
10129 23:07:36.593979 Waiting for link
10130 23:07:36.754565
10131 23:07:36.755043 R8152: Initializing
10132 23:07:36.755376
10133 23:07:36.758067 Version 6 (ocp_data = 5c30)
10134 23:07:36.758543
10135 23:07:36.761211 R8152: Done initializing
10136 23:07:36.761630
10137 23:07:36.762182 Adding net device
10138 23:07:38.664087
10139 23:07:38.664642 done.
10140 23:07:38.664981
10141 23:07:38.665293 MAC: 00:24:32:30:78:ff
10142 23:07:38.665614
10143 23:07:38.666897 Sending DHCP discover... done.
10144 23:07:38.667314
10145 23:07:48.980593 Waiting for reply... R8152: Bulk read error 0xffffffbf
10146 23:07:48.980747
10147 23:07:48.983776 Receive failed.
10148 23:07:48.983860
10149 23:07:48.983924 done.
10150 23:07:48.983984
10151 23:07:48.986976 Sending DHCP request... done.
10152 23:07:48.987057
10153 23:07:48.990384 Waiting for reply... done.
10154 23:07:48.990466
10155 23:07:48.993457 My ip is 192.168.201.21
10156 23:07:48.993538
10157 23:07:48.997370 The DHCP server ip is 192.168.201.1
10158 23:07:48.997452
10159 23:07:49.000606 TFTP server IP predefined by user: 192.168.201.1
10160 23:07:49.000688
10161 23:07:49.006818 Bootfile predefined by user: 12154441/tftp-deploy-apkqk93d/kernel/image.itb
10162 23:07:49.006948
10163 23:07:49.010123 Sending tftp read request... done.
10164 23:07:49.010203
10165 23:07:49.013264 Waiting for the transfer...
10166 23:07:49.013345
10167 23:07:49.569697 00000000 ################################################################
10168 23:07:49.569844
10169 23:07:50.111925 00080000 ################################################################
10170 23:07:50.112065
10171 23:07:50.680099 00100000 ################################################################
10172 23:07:50.680286
10173 23:07:51.246889 00180000 ################################################################
10174 23:07:51.247037
10175 23:07:51.789423 00200000 ################################################################
10176 23:07:51.789561
10177 23:07:52.320484 00280000 ################################################################
10178 23:07:52.320644
10179 23:07:52.852594 00300000 ################################################################
10180 23:07:52.852729
10181 23:07:53.393008 00380000 ################################################################
10182 23:07:53.393149
10183 23:07:53.911180 00400000 ################################################################
10184 23:07:53.911321
10185 23:07:54.437812 00480000 ################################################################
10186 23:07:54.437952
10187 23:07:54.975681 00500000 ################################################################
10188 23:07:54.975850
10189 23:07:55.522426 00580000 ################################################################
10190 23:07:55.522570
10191 23:07:56.178563 00600000 ################################################################
10192 23:07:56.179113
10193 23:07:56.853758 00680000 ################################################################
10194 23:07:56.854267
10195 23:07:57.533847 00700000 ################################################################
10196 23:07:57.534038
10197 23:07:58.163736 00780000 ################################################################
10198 23:07:58.163970
10199 23:07:58.730395 00800000 ################################################################
10200 23:07:58.730529
10201 23:07:59.287037 00880000 ################################################################
10202 23:07:59.287174
10203 23:07:59.869264 00900000 ################################################################
10204 23:07:59.869396
10205 23:08:00.519812 00980000 ################################################################
10206 23:08:00.519996
10207 23:08:01.135931 00a00000 ################################################################
10208 23:08:01.136600
10209 23:08:01.713002 00a80000 ################################################################
10210 23:08:01.713263
10211 23:08:02.342350 00b00000 ################################################################
10212 23:08:02.342888
10213 23:08:03.025169 00b80000 ################################################################
10214 23:08:03.025726
10215 23:08:03.717106 00c00000 ################################################################
10216 23:08:03.717630
10217 23:08:04.398106 00c80000 ################################################################
10218 23:08:04.398620
10219 23:08:05.080129 00d00000 ################################################################
10220 23:08:05.080719
10221 23:08:05.760922 00d80000 ################################################################
10222 23:08:05.761474
10223 23:08:06.438251 00e00000 ################################################################
10224 23:08:06.438801
10225 23:08:07.107997 00e80000 ################################################################
10226 23:08:07.108546
10227 23:08:07.808383 00f00000 ################################################################
10228 23:08:07.808915
10229 23:08:08.504069 00f80000 ################################################################
10230 23:08:08.504716
10231 23:08:09.171652 01000000 ################################################################
10232 23:08:09.172162
10233 23:08:09.841157 01080000 ################################################################
10234 23:08:09.841711
10235 23:08:10.517307 01100000 ################################################################
10236 23:08:10.517853
10237 23:08:11.194329 01180000 ################################################################
10238 23:08:11.194844
10239 23:08:11.874812 01200000 ################################################################
10240 23:08:11.875370
10241 23:08:12.565605 01280000 ################################################################
10242 23:08:12.566238
10243 23:08:13.260123 01300000 ################################################################
10244 23:08:13.260774
10245 23:08:13.970390 01380000 ################################################################
10246 23:08:13.970946
10247 23:08:14.621079 01400000 ################################################################
10248 23:08:14.621216
10249 23:08:15.267742 01480000 ################################################################
10250 23:08:15.268326
10251 23:08:15.942556 01500000 ################################################################
10252 23:08:15.943071
10253 23:08:16.613614 01580000 ################################################################
10254 23:08:16.614133
10255 23:08:17.281020 01600000 ################################################################
10256 23:08:17.281722
10257 23:08:17.970687 01680000 ################################################################
10258 23:08:17.971275
10259 23:08:18.644700 01700000 ################################################################
10260 23:08:18.645399
10261 23:08:19.337146 01780000 ################################################################
10262 23:08:19.337647
10263 23:08:20.028250 01800000 ################################################################
10264 23:08:20.028896
10265 23:08:20.718847 01880000 ################################################################
10266 23:08:20.719359
10267 23:08:21.411404 01900000 ################################################################
10268 23:08:21.411919
10269 23:08:22.087028 01980000 ################################################################
10270 23:08:22.087534
10271 23:08:22.769918 01a00000 ################################################################
10272 23:08:22.770578
10273 23:08:23.454417 01a80000 ################################################################
10274 23:08:23.454973
10275 23:08:24.135499 01b00000 ################################################################
10276 23:08:24.136022
10277 23:08:24.210477 01b80000 ####### done.
10278 23:08:24.210968
10279 23:08:24.213918 The bootfile was 28891662 bytes long.
10280 23:08:24.214383
10281 23:08:24.217157 Sending tftp read request... done.
10282 23:08:24.217614
10283 23:08:24.221293 Waiting for the transfer...
10284 23:08:24.221754
10285 23:08:24.222117 00000000 # done.
10286 23:08:24.222467
10287 23:08:24.228171 Command line loaded dynamically from TFTP file: 12154441/tftp-deploy-apkqk93d/kernel/cmdline
10288 23:08:24.228652
10289 23:08:24.251428 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12154441/extract-nfsrootfs-32vd6yh1,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10290 23:08:24.251964
10291 23:08:24.252338 Loading FIT.
10292 23:08:24.252760
10293 23:08:24.254450 Image ramdisk-1 has 17798368 bytes.
10294 23:08:24.254797
10295 23:08:24.257983 Image fdt-1 has 47278 bytes.
10296 23:08:24.258465
10297 23:08:24.261027 Image kernel-1 has 11043984 bytes.
10298 23:08:24.261440
10299 23:08:24.270876 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10300 23:08:24.271298
10301 23:08:24.287928 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10302 23:08:24.288511
10303 23:08:24.294579 Choosing best match conf-1 for compat google,spherion-rev2.
10304 23:08:24.295154
10305 23:08:24.302118 Connected to device vid:did:rid of 1ae0:0028:00
10306 23:08:24.310398
10307 23:08:24.313330 tpm_get_response: command 0x17b, return code 0x0
10308 23:08:24.313749
10309 23:08:24.316518 ec_init: CrosEC protocol v3 supported (256, 248)
10310 23:08:24.320753
10311 23:08:24.324363 tpm_cleanup: add release locality here.
10312 23:08:24.324874
10313 23:08:24.325205 Shutting down all USB controllers.
10314 23:08:24.327424
10315 23:08:24.327837 Removing current net device
10316 23:08:24.328165
10317 23:08:24.334062 Exiting depthcharge with code 4 at timestamp: 81216710
10318 23:08:24.334580
10319 23:08:24.337456 LZMA decompressing kernel-1 to 0x821a6718
10320 23:08:24.337872
10321 23:08:24.340924 LZMA decompressing kernel-1 to 0x40000000
10322 23:08:25.734618
10323 23:08:25.735106 jumping to kernel
10324 23:08:25.737085 end: 2.2.4 bootloader-commands (duration 00:00:53) [common]
10325 23:08:25.737566 start: 2.2.5 auto-login-action (timeout 00:03:32) [common]
10326 23:08:25.737994 Setting prompt string to ['Linux version [0-9]']
10327 23:08:25.738375 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10328 23:08:25.738750 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10329 23:08:25.817846
10330 23:08:25.820795 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10331 23:08:25.824658 start: 2.2.5.1 login-action (timeout 00:03:32) [common]
10332 23:08:25.825172 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10333 23:08:25.825566 Setting prompt string to []
10334 23:08:25.825974 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10335 23:08:25.826364 Using line separator: #'\n'#
10336 23:08:25.826695 No login prompt set.
10337 23:08:25.827039 Parsing kernel messages
10338 23:08:25.827345 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10339 23:08:25.827910 [login-action] Waiting for messages, (timeout 00:03:32)
10340 23:08:25.843713 [ 0.000000] Linux version 6.1.64-cip10 (KernelCI@build-j31357-arm64-gcc-10-defconfig-arm64-chromebook-69txj) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Dec 1 22:47:09 UTC 2023
10341 23:08:25.847038 [ 0.000000] random: crng init done
10342 23:08:25.853609 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10343 23:08:25.857195 [ 0.000000] efi: UEFI not found.
10344 23:08:25.863666 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10345 23:08:25.870065 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10346 23:08:25.879808 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10347 23:08:25.889390 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10348 23:08:25.896032 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10349 23:08:25.903025 [ 0.000000] printk: bootconsole [mtk8250] enabled
10350 23:08:25.909595 [ 0.000000] NUMA: No NUMA configuration found
10351 23:08:25.916061 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10352 23:08:25.922380 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10353 23:08:25.922626 [ 0.000000] Zone ranges:
10354 23:08:25.929236 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10355 23:08:25.932403 [ 0.000000] DMA32 empty
10356 23:08:25.938955 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10357 23:08:25.942348 [ 0.000000] Movable zone start for each node
10358 23:08:25.946142 [ 0.000000] Early memory node ranges
10359 23:08:25.952248 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10360 23:08:25.959209 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10361 23:08:25.965312 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10362 23:08:25.972502 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10363 23:08:25.979018 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10364 23:08:25.985108 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10365 23:08:26.041496 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10366 23:08:26.048154 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10367 23:08:26.054658 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10368 23:08:26.057849 [ 0.000000] psci: probing for conduit method from DT.
10369 23:08:26.064518 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10370 23:08:26.067767 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10371 23:08:26.074683 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10372 23:08:26.078195 [ 0.000000] psci: SMC Calling Convention v1.2
10373 23:08:26.084550 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10374 23:08:26.088080 [ 0.000000] Detected VIPT I-cache on CPU0
10375 23:08:26.094428 [ 0.000000] CPU features: detected: GIC system register CPU interface
10376 23:08:26.101182 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10377 23:08:26.107466 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10378 23:08:26.114516 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10379 23:08:26.120949 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10380 23:08:26.127673 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10381 23:08:26.134439 [ 0.000000] alternatives: applying boot alternatives
10382 23:08:26.137523 [ 0.000000] Fallback order for Node 0: 0
10383 23:08:26.147621 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10384 23:08:26.148132 [ 0.000000] Policy zone: Normal
10385 23:08:26.173930 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12154441/extract-nfsrootfs-32vd6yh1,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10386 23:08:26.183846 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10387 23:08:26.194277 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10388 23:08:26.204671 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10389 23:08:26.211434 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10390 23:08:26.213833 <6>[ 0.000000] software IO TLB: area num 8.
10391 23:08:26.270978 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10392 23:08:26.419800 <6>[ 0.000000] Memory: 7952172K/8385536K available (17984K kernel code, 4116K rwdata, 17316K rodata, 8448K init, 615K bss, 400596K reserved, 32768K cma-reserved)
10393 23:08:26.426502 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10394 23:08:26.432727 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10395 23:08:26.436038 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10396 23:08:26.442414 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10397 23:08:26.449320 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10398 23:08:26.452649 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10399 23:08:26.462864 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10400 23:08:26.469146 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10401 23:08:26.476134 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10402 23:08:26.482321 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10403 23:08:26.485635 <6>[ 0.000000] GICv3: 608 SPIs implemented
10404 23:08:26.489154 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10405 23:08:26.495757 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10406 23:08:26.498805 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10407 23:08:26.505713 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10408 23:08:26.519006 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10409 23:08:26.529181 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10410 23:08:26.538965 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10411 23:08:26.546031 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10412 23:08:26.559501 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10413 23:08:26.566080 <6>[ 0.000001] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10414 23:08:26.573159 <6>[ 0.009183] Console: colour dummy device 80x25
10415 23:08:26.582480 <6>[ 0.013900] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10416 23:08:26.589446 <6>[ 0.024341] pid_max: default: 32768 minimum: 301
10417 23:08:26.592274 <6>[ 0.029213] LSM: Security Framework initializing
10418 23:08:26.598645 <6>[ 0.034182] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10419 23:08:26.608980 <6>[ 0.041997] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10420 23:08:26.618250 <6>[ 0.051423] cblist_init_generic: Setting adjustable number of callback queues.
10421 23:08:26.621609 <6>[ 0.058865] cblist_init_generic: Setting shift to 3 and lim to 1.
10422 23:08:26.631754 <6>[ 0.065203] cblist_init_generic: Setting adjustable number of callback queues.
10423 23:08:26.638307 <6>[ 0.072630] cblist_init_generic: Setting shift to 3 and lim to 1.
10424 23:08:26.641733 <6>[ 0.079031] rcu: Hierarchical SRCU implementation.
10425 23:08:26.648845 <6>[ 0.084046] rcu: Max phase no-delay instances is 1000.
10426 23:08:26.655476 <6>[ 0.091072] EFI services will not be available.
10427 23:08:26.658547 <6>[ 0.096059] smp: Bringing up secondary CPUs ...
10428 23:08:26.666571 <6>[ 0.101109] Detected VIPT I-cache on CPU1
10429 23:08:26.673669 <6>[ 0.101178] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10430 23:08:26.680279 <6>[ 0.101208] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10431 23:08:26.683485 <6>[ 0.101545] Detected VIPT I-cache on CPU2
10432 23:08:26.690305 <6>[ 0.101594] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10433 23:08:26.696449 <6>[ 0.101610] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10434 23:08:26.703184 <6>[ 0.101867] Detected VIPT I-cache on CPU3
10435 23:08:26.710293 <6>[ 0.101914] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10436 23:08:26.716455 <6>[ 0.101928] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10437 23:08:26.720029 <6>[ 0.102229] CPU features: detected: Spectre-v4
10438 23:08:26.726556 <6>[ 0.102236] CPU features: detected: Spectre-BHB
10439 23:08:26.729867 <6>[ 0.102241] Detected PIPT I-cache on CPU4
10440 23:08:26.736705 <6>[ 0.102298] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10441 23:08:26.742964 <6>[ 0.102315] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10442 23:08:26.749703 <6>[ 0.102611] Detected PIPT I-cache on CPU5
10443 23:08:26.756130 <6>[ 0.102673] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10444 23:08:26.762821 <6>[ 0.102690] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10445 23:08:26.766445 <6>[ 0.102971] Detected PIPT I-cache on CPU6
10446 23:08:26.773025 <6>[ 0.103035] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10447 23:08:26.779351 <6>[ 0.103052] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10448 23:08:26.785898 <6>[ 0.103349] Detected PIPT I-cache on CPU7
10449 23:08:26.792189 <6>[ 0.103413] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10450 23:08:26.799732 <6>[ 0.103429] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10451 23:08:26.802493 <6>[ 0.103477] smp: Brought up 1 node, 8 CPUs
10452 23:08:26.809096 <6>[ 0.244828] SMP: Total of 8 processors activated.
10453 23:08:26.812294 <6>[ 0.249749] CPU features: detected: 32-bit EL0 Support
10454 23:08:26.822226 <6>[ 0.255113] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10455 23:08:26.828821 <6>[ 0.263913] CPU features: detected: Common not Private translations
10456 23:08:26.835850 <6>[ 0.270388] CPU features: detected: CRC32 instructions
10457 23:08:26.839289 <6>[ 0.275740] CPU features: detected: RCpc load-acquire (LDAPR)
10458 23:08:26.845640 <6>[ 0.281700] CPU features: detected: LSE atomic instructions
10459 23:08:26.852126 <6>[ 0.287481] CPU features: detected: Privileged Access Never
10460 23:08:26.858377 <6>[ 0.293297] CPU features: detected: RAS Extension Support
10461 23:08:26.865161 <6>[ 0.298940] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10462 23:08:26.868461 <6>[ 0.306203] CPU: All CPU(s) started at EL2
10463 23:08:26.875097 <6>[ 0.310520] alternatives: applying system-wide alternatives
10464 23:08:26.884863 <6>[ 0.321218] devtmpfs: initialized
10465 23:08:26.900538 <6>[ 0.330218] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10466 23:08:26.906606 <6>[ 0.340178] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10467 23:08:26.913484 <6>[ 0.348416] pinctrl core: initialized pinctrl subsystem
10468 23:08:26.916459 <6>[ 0.355063] DMI not present or invalid.
10469 23:08:26.923242 <6>[ 0.359476] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10470 23:08:26.933049 <6>[ 0.366258] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10471 23:08:26.939360 <6>[ 0.373842] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10472 23:08:26.949910 <6>[ 0.382067] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10473 23:08:26.953026 <6>[ 0.390308] audit: initializing netlink subsys (disabled)
10474 23:08:26.962802 <5>[ 0.395999] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10475 23:08:26.969636 <6>[ 0.396699] thermal_sys: Registered thermal governor 'step_wise'
10476 23:08:26.975846 <6>[ 0.403966] thermal_sys: Registered thermal governor 'power_allocator'
10477 23:08:26.979299 <6>[ 0.410221] cpuidle: using governor menu
10478 23:08:26.985901 <6>[ 0.421183] NET: Registered PF_QIPCRTR protocol family
10479 23:08:26.992316 <6>[ 0.426667] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10480 23:08:26.999327 <6>[ 0.433767] ASID allocator initialised with 32768 entries
10481 23:08:27.002269 <6>[ 0.440323] Serial: AMBA PL011 UART driver
10482 23:08:27.012246 <4>[ 0.449107] Trying to register duplicate clock ID: 134
10483 23:08:27.068412 <6>[ 0.508656] KASLR enabled
10484 23:08:27.083015 <6>[ 0.516423] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10485 23:08:27.089327 <6>[ 0.523434] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10486 23:08:27.095995 <6>[ 0.529923] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10487 23:08:27.103157 <6>[ 0.536928] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10488 23:08:27.109773 <6>[ 0.543415] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10489 23:08:27.116251 <6>[ 0.550416] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10490 23:08:27.122998 <6>[ 0.556900] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10491 23:08:27.129266 <6>[ 0.563903] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10492 23:08:27.132732 <6>[ 0.571437] ACPI: Interpreter disabled.
10493 23:08:27.141188 <6>[ 0.577858] iommu: Default domain type: Translated
10494 23:08:27.147390 <6>[ 0.582971] iommu: DMA domain TLB invalidation policy: strict mode
10495 23:08:27.151053 <5>[ 0.589632] SCSI subsystem initialized
10496 23:08:27.157787 <6>[ 0.593793] usbcore: registered new interface driver usbfs
10497 23:08:27.163957 <6>[ 0.599525] usbcore: registered new interface driver hub
10498 23:08:27.167823 <6>[ 0.605078] usbcore: registered new device driver usb
10499 23:08:27.174710 <6>[ 0.611189] pps_core: LinuxPPS API ver. 1 registered
10500 23:08:27.184054 <6>[ 0.616382] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10501 23:08:27.187413 <6>[ 0.625729] PTP clock support registered
10502 23:08:27.190627 <6>[ 0.629971] EDAC MC: Ver: 3.0.0
10503 23:08:27.198139 <6>[ 0.635129] FPGA manager framework
10504 23:08:27.204869 <6>[ 0.638807] Advanced Linux Sound Architecture Driver Initialized.
10505 23:08:27.208276 <6>[ 0.645591] vgaarb: loaded
10506 23:08:27.215041 <6>[ 0.648746] clocksource: Switched to clocksource arch_sys_counter
10507 23:08:27.217855 <5>[ 0.655184] VFS: Disk quotas dquot_6.6.0
10508 23:08:27.224367 <6>[ 0.659370] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10509 23:08:27.227513 <6>[ 0.666557] pnp: PnP ACPI: disabled
10510 23:08:27.236031 <6>[ 0.673261] NET: Registered PF_INET protocol family
10511 23:08:27.246344 <6>[ 0.678852] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10512 23:08:27.257433 <6>[ 0.691196] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10513 23:08:27.267525 <6>[ 0.700012] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10514 23:08:27.273515 <6>[ 0.707983] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10515 23:08:27.283911 <6>[ 0.716684] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10516 23:08:27.290401 <6>[ 0.726442] TCP: Hash tables configured (established 65536 bind 65536)
10517 23:08:27.297210 <6>[ 0.733308] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10518 23:08:27.307311 <6>[ 0.740505] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10519 23:08:27.313626 <6>[ 0.748208] NET: Registered PF_UNIX/PF_LOCAL protocol family
10520 23:08:27.320794 <6>[ 0.754364] RPC: Registered named UNIX socket transport module.
10521 23:08:27.323640 <6>[ 0.760516] RPC: Registered udp transport module.
10522 23:08:27.327056 <6>[ 0.765450] RPC: Registered tcp transport module.
10523 23:08:27.333665 <6>[ 0.770381] RPC: Registered tcp NFSv4.1 backchannel transport module.
10524 23:08:27.340424 <6>[ 0.777048] PCI: CLS 0 bytes, default 64
10525 23:08:27.343551 <6>[ 0.781386] Unpacking initramfs...
10526 23:08:27.367376 <6>[ 0.800854] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10527 23:08:27.377422 <6>[ 0.809517] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10528 23:08:27.380528 <6>[ 0.818304] kvm [1]: IPA Size Limit: 40 bits
10529 23:08:27.386838 <6>[ 0.822833] kvm [1]: GICv3: no GICV resource entry
10530 23:08:27.389965 <6>[ 0.827856] kvm [1]: disabling GICv2 emulation
10531 23:08:27.396513 <6>[ 0.832551] kvm [1]: GIC system register CPU interface enabled
10532 23:08:27.400290 <6>[ 0.838717] kvm [1]: vgic interrupt IRQ18
10533 23:08:27.406710 <6>[ 0.843073] kvm [1]: VHE mode initialized successfully
10534 23:08:27.413333 <5>[ 0.849575] Initialise system trusted keyrings
10535 23:08:27.420160 <6>[ 0.854415] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10536 23:08:27.427551 <6>[ 0.864592] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10537 23:08:27.434268 <5>[ 0.870993] NFS: Registering the id_resolver key type
10538 23:08:27.437626 <5>[ 0.876295] Key type id_resolver registered
10539 23:08:27.443984 <5>[ 0.880707] Key type id_legacy registered
10540 23:08:27.450920 <6>[ 0.884994] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10541 23:08:27.456942 <6>[ 0.891920] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10542 23:08:27.463746 <6>[ 0.899671] 9p: Installing v9fs 9p2000 file system support
10543 23:08:27.500222 <5>[ 0.937461] Key type asymmetric registered
10544 23:08:27.503486 <5>[ 0.941794] Asymmetric key parser 'x509' registered
10545 23:08:27.513290 <6>[ 0.946936] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10546 23:08:27.517003 <6>[ 0.954555] io scheduler mq-deadline registered
10547 23:08:27.520255 <6>[ 0.959334] io scheduler kyber registered
10548 23:08:27.539241 <6>[ 0.976407] EINJ: ACPI disabled.
10549 23:08:27.571498 <4>[ 1.002021] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10550 23:08:27.581434 <4>[ 1.012652] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10551 23:08:27.596658 <6>[ 1.033546] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10552 23:08:27.604666 <6>[ 1.041649] printk: console [ttyS0] disabled
10553 23:08:27.633147 <6>[ 1.066296] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10554 23:08:27.639596 <6>[ 1.075788] printk: console [ttyS0] enabled
10555 23:08:27.642858 <6>[ 1.075788] printk: console [ttyS0] enabled
10556 23:08:27.649578 <6>[ 1.084681] printk: bootconsole [mtk8250] disabled
10557 23:08:27.652891 <6>[ 1.084681] printk: bootconsole [mtk8250] disabled
10558 23:08:27.659627 <6>[ 1.095961] SuperH (H)SCI(F) driver initialized
10559 23:08:27.662699 <6>[ 1.101275] msm_serial: driver initialized
10560 23:08:27.676751 <6>[ 1.110288] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10561 23:08:27.686965 <6>[ 1.118838] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10562 23:08:27.693225 <6>[ 1.127383] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10563 23:08:27.703394 <6>[ 1.136011] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10564 23:08:27.713138 <6>[ 1.144718] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10565 23:08:27.719512 <6>[ 1.153438] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10566 23:08:27.729577 <6>[ 1.161979] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10567 23:08:27.736535 <6>[ 1.170780] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10568 23:08:27.746549 <6>[ 1.179323] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10569 23:08:27.758200 <6>[ 1.195218] loop: module loaded
10570 23:08:27.765228 <6>[ 1.201209] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10571 23:08:27.788178 <4>[ 1.224843] mtk-pmic-keys: Failed to locate of_node [id: -1]
10572 23:08:27.795345 <6>[ 1.232049] megasas: 07.719.03.00-rc1
10573 23:08:27.805367 <6>[ 1.241823] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10574 23:08:27.815685 <6>[ 1.252124] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10575 23:08:27.832662 <6>[ 1.268787] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10576 23:08:27.888338 <6>[ 1.318544] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10577 23:08:28.087260 <6>[ 1.524360] Freeing initrd memory: 17380K
10578 23:08:28.097313 <6>[ 1.534677] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10579 23:08:28.108713 <6>[ 1.545801] tun: Universal TUN/TAP device driver, 1.6
10580 23:08:28.111639 <6>[ 1.551872] thunder_xcv, ver 1.0
10581 23:08:28.115048 <6>[ 1.555379] thunder_bgx, ver 1.0
10582 23:08:28.118450 <6>[ 1.558876] nicpf, ver 1.0
10583 23:08:28.129360 <6>[ 1.562916] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10584 23:08:28.132184 <6>[ 1.570393] hns3: Copyright (c) 2017 Huawei Corporation.
10585 23:08:28.135562 <6>[ 1.575982] hclge is initializing
10586 23:08:28.142069 <6>[ 1.579564] e1000: Intel(R) PRO/1000 Network Driver
10587 23:08:28.148584 <6>[ 1.584694] e1000: Copyright (c) 1999-2006 Intel Corporation.
10588 23:08:28.152479 <6>[ 1.590707] e1000e: Intel(R) PRO/1000 Network Driver
10589 23:08:28.159244 <6>[ 1.595922] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10590 23:08:28.165625 <6>[ 1.602106] igb: Intel(R) Gigabit Ethernet Network Driver
10591 23:08:28.172266 <6>[ 1.607755] igb: Copyright (c) 2007-2014 Intel Corporation.
10592 23:08:28.178808 <6>[ 1.613595] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10593 23:08:28.185334 <6>[ 1.620113] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10594 23:08:28.188557 <6>[ 1.626576] sky2: driver version 1.30
10595 23:08:28.195320 <6>[ 1.631576] VFIO - User Level meta-driver version: 0.3
10596 23:08:28.202508 <6>[ 1.639792] usbcore: registered new interface driver usb-storage
10597 23:08:28.209486 <6>[ 1.646247] usbcore: registered new device driver onboard-usb-hub
10598 23:08:28.218027 <6>[ 1.655427] mt6397-rtc mt6359-rtc: registered as rtc0
10599 23:08:28.227898 <6>[ 1.660895] mt6397-rtc mt6359-rtc: setting system clock to 2023-12-01T23:08:28 UTC (1701472108)
10600 23:08:28.231188 <6>[ 1.670469] i2c_dev: i2c /dev entries driver
10601 23:08:28.248165 <6>[ 1.682318] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10602 23:08:28.268067 <6>[ 1.705315] cpu cpu0: EM: created perf domain
10603 23:08:28.271516 <6>[ 1.710239] cpu cpu4: EM: created perf domain
10604 23:08:28.278911 <6>[ 1.715855] sdhci: Secure Digital Host Controller Interface driver
10605 23:08:28.285320 <6>[ 1.722289] sdhci: Copyright(c) Pierre Ossman
10606 23:08:28.292152 <6>[ 1.727240] Synopsys Designware Multimedia Card Interface Driver
10607 23:08:28.298740 <6>[ 1.733869] sdhci-pltfm: SDHCI platform and OF driver helper
10608 23:08:28.301831 <6>[ 1.733898] mmc0: CQHCI version 5.10
10609 23:08:28.308661 <6>[ 1.744184] ledtrig-cpu: registered to indicate activity on CPUs
10610 23:08:28.315536 <6>[ 1.751232] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10611 23:08:28.322328 <6>[ 1.758283] usbcore: registered new interface driver usbhid
10612 23:08:28.325928 <6>[ 1.764104] usbhid: USB HID core driver
10613 23:08:28.331709 <6>[ 1.768310] spi_master spi0: will run message pump with realtime priority
10614 23:08:28.375514 <6>[ 1.806154] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10615 23:08:28.394487 <6>[ 1.821383] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10616 23:08:28.398140 <6>[ 1.836173] mmc0: Command Queue Engine enabled
10617 23:08:28.404851 <6>[ 1.840931] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10618 23:08:28.411001 <6>[ 1.847640] cros-ec-spi spi0.0: Chrome EC device registered
10619 23:08:28.414693 <6>[ 1.848261] mmcblk0: mmc0:0001 DA4128 116 GiB
10620 23:08:28.427065 <6>[ 1.864410] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10621 23:08:28.434594 <6>[ 1.871968] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10622 23:08:28.441083 <6>[ 1.878326] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10623 23:08:28.451667 <6>[ 1.882769] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10624 23:08:28.457678 <6>[ 1.884272] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10625 23:08:28.461418 <6>[ 1.894073] NET: Registered PF_PACKET protocol family
10626 23:08:28.467762 <6>[ 1.904821] 9pnet: Installing 9P2000 support
10627 23:08:28.471056 <5>[ 1.909408] Key type dns_resolver registered
10628 23:08:28.477607 <6>[ 1.914373] registered taskstats version 1
10629 23:08:28.481083 <5>[ 1.918757] Loading compiled-in X.509 certificates
10630 23:08:28.510021 <4>[ 1.939988] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10631 23:08:28.520018 <4>[ 1.950721] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10632 23:08:28.526539 <3>[ 1.961659] debugfs: File 'uA_load' in directory '/' already present!
10633 23:08:28.532844 <3>[ 1.968385] debugfs: File 'min_uV' in directory '/' already present!
10634 23:08:28.539587 <3>[ 1.975006] debugfs: File 'max_uV' in directory '/' already present!
10635 23:08:28.546246 <3>[ 1.981623] debugfs: File 'constraint_flags' in directory '/' already present!
10636 23:08:28.558678 <3>[ 1.991654] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10637 23:08:28.570495 <6>[ 2.007590] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10638 23:08:28.577340 <6>[ 2.014493] xhci-mtk 11200000.usb: xHCI Host Controller
10639 23:08:28.584134 <6>[ 2.019996] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10640 23:08:28.594471 <6>[ 2.027938] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10641 23:08:28.601033 <6>[ 2.037369] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10642 23:08:28.607703 <6>[ 2.043461] xhci-mtk 11200000.usb: xHCI Host Controller
10643 23:08:28.614408 <6>[ 2.048942] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10644 23:08:28.620936 <6>[ 2.056591] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10645 23:08:28.627670 <6>[ 2.064348] hub 1-0:1.0: USB hub found
10646 23:08:28.631159 <6>[ 2.068391] hub 1-0:1.0: 1 port detected
10647 23:08:28.640966 <6>[ 2.072681] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10648 23:08:28.644491 <6>[ 2.081468] hub 2-0:1.0: USB hub found
10649 23:08:28.647255 <6>[ 2.085510] hub 2-0:1.0: 1 port detected
10650 23:08:28.655878 <6>[ 2.092366] mtk-msdc 11f70000.mmc: Got CD GPIO
10651 23:08:28.672822 <6>[ 2.106211] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10652 23:08:28.679581 <6>[ 2.114267] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10653 23:08:28.689164 <4>[ 2.122180] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10654 23:08:28.698929 <6>[ 2.131715] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10655 23:08:28.705665 <6>[ 2.139797] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10656 23:08:28.712707 <6>[ 2.147816] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10657 23:08:28.722233 <6>[ 2.155739] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10658 23:08:28.729489 <6>[ 2.163557] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10659 23:08:28.738880 <6>[ 2.171374] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10660 23:08:28.749494 <6>[ 2.181808] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10661 23:08:28.755924 <6>[ 2.190190] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10662 23:08:28.765631 <6>[ 2.198537] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10663 23:08:28.772186 <6>[ 2.206875] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10664 23:08:28.782624 <6>[ 2.215215] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10665 23:08:28.788831 <6>[ 2.223552] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10666 23:08:28.798780 <6>[ 2.231892] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10667 23:08:28.805715 <6>[ 2.240230] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10668 23:08:28.815639 <6>[ 2.248569] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10669 23:08:28.822647 <6>[ 2.256913] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10670 23:08:28.832514 <6>[ 2.265251] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10671 23:08:28.838951 <6>[ 2.273590] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10672 23:08:28.848803 <6>[ 2.281928] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10673 23:08:28.855452 <6>[ 2.290266] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10674 23:08:28.865092 <6>[ 2.298605] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10675 23:08:28.872048 <6>[ 2.307322] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10676 23:08:28.878318 <6>[ 2.314451] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10677 23:08:28.884867 <6>[ 2.321207] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10678 23:08:28.891577 <6>[ 2.327959] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10679 23:08:28.898188 <6>[ 2.334896] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10680 23:08:28.908515 <6>[ 2.341756] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10681 23:08:28.918370 <6>[ 2.350883] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10682 23:08:28.928130 <6>[ 2.360001] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10683 23:08:28.938433 <6>[ 2.369295] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10684 23:08:28.944745 <6>[ 2.378767] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10685 23:08:28.955245 <6>[ 2.388234] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10686 23:08:28.964271 <6>[ 2.397355] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10687 23:08:28.974241 <6>[ 2.406824] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10688 23:08:28.984812 <6>[ 2.415942] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10689 23:08:28.994425 <6>[ 2.425235] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10690 23:08:29.004117 <6>[ 2.435395] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10691 23:08:29.014082 <6>[ 2.446906] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10692 23:08:29.020560 <6>[ 2.456637] Trying to probe devices needed for running init ...
10693 23:08:29.059684 <6>[ 2.493018] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10694 23:08:29.213923 <6>[ 2.650878] hub 1-1:1.0: USB hub found
10695 23:08:29.217460 <6>[ 2.655392] hub 1-1:1.0: 4 ports detected
10696 23:08:29.227401 <6>[ 2.663826] hub 1-1:1.0: USB hub found
10697 23:08:29.230262 <6>[ 2.668188] hub 1-1:1.0: 4 ports detected
10698 23:08:29.339715 <6>[ 2.773281] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10699 23:08:29.365111 <6>[ 2.801853] hub 2-1:1.0: USB hub found
10700 23:08:29.367997 <6>[ 2.806299] hub 2-1:1.0: 3 ports detected
10701 23:08:29.375896 <6>[ 2.813314] hub 2-1:1.0: USB hub found
10702 23:08:29.379120 <6>[ 2.817674] hub 2-1:1.0: 3 ports detected
10703 23:08:29.555493 <6>[ 2.989112] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10704 23:08:29.687240 <6>[ 3.124374] hub 1-1.4:1.0: USB hub found
10705 23:08:29.690605 <6>[ 3.129005] hub 1-1.4:1.0: 2 ports detected
10706 23:08:29.700012 <6>[ 3.136707] hub 1-1.4:1.0: USB hub found
10707 23:08:29.702832 <6>[ 3.141314] hub 1-1.4:1.0: 2 ports detected
10708 23:08:29.771221 <6>[ 3.205132] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10709 23:08:29.999599 <6>[ 3.433047] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10710 23:08:30.191525 <6>[ 3.625031] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10711 23:08:41.292423 <6>[ 14.734042] ALSA device list:
10712 23:08:41.299323 <6>[ 14.737337] No soundcards found.
10713 23:08:41.306836 <6>[ 14.745323] Freeing unused kernel memory: 8448K
10714 23:08:41.310307 <6>[ 14.750305] Run /init as init process
10715 23:08:41.321678 Loading, please wait...
10716 23:08:41.342035 Starting version 247.3-7+deb11u2
10717 23:08:41.540320 <6>[ 14.975519] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10718 23:08:41.553072 <3>[ 14.987810] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10719 23:08:41.559405 <6>[ 14.989802] remoteproc remoteproc0: scp is available
10720 23:08:41.566334 <6>[ 14.991876] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10721 23:08:41.572934 <3>[ 14.996074] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10722 23:08:41.582492 <6>[ 14.998040] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10723 23:08:41.589308 <6>[ 14.998058] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10724 23:08:41.600040 <6>[ 14.998062] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10725 23:08:41.603714 <6>[ 15.001357] remoteproc remoteproc0: powering up scp
10726 23:08:41.606787 <6>[ 15.001717] mc: Linux media interface: v0.10
10727 23:08:41.613138 <6>[ 15.003307] usbcore: registered new interface driver r8152
10728 23:08:41.620640 <3>[ 15.008912] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10729 23:08:41.630728 <4>[ 15.014911] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10730 23:08:41.637085 <4>[ 15.014911] Fallback method does not support PEC.
10731 23:08:41.643792 <6>[ 15.016991] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10732 23:08:41.650626 <6>[ 15.019329] videodev: Linux video capture interface: v2.00
10733 23:08:41.657300 <3>[ 15.024778] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10734 23:08:41.663798 <6>[ 15.033397] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10735 23:08:41.670456 <4>[ 15.035208] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10736 23:08:41.677123 <4>[ 15.035991] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10737 23:08:41.686993 <3>[ 15.042023] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10738 23:08:41.696696 <3>[ 15.043091] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10739 23:08:41.703094 <3>[ 15.066440] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10740 23:08:41.712764 <3>[ 15.079167] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10741 23:08:41.723048 <6>[ 15.134468] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10742 23:08:41.729344 <3>[ 15.138633] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10743 23:08:41.736338 <6>[ 15.138821] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10744 23:08:41.746288 <6>[ 15.147838] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10745 23:08:41.756509 <6>[ 15.149347] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10746 23:08:41.762801 <6>[ 15.151998] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10747 23:08:41.769151 <6>[ 15.152007] pci_bus 0000:00: root bus resource [bus 00-ff]
10748 23:08:41.776373 <6>[ 15.152014] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10749 23:08:41.786153 <6>[ 15.152022] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10750 23:08:41.792231 <6>[ 15.152062] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10751 23:08:41.799212 <6>[ 15.152090] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10752 23:08:41.802414 <6>[ 15.152188] pci 0000:00:00.0: supports D1 D2
10753 23:08:41.812361 <6>[ 15.152193] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10754 23:08:41.819214 <6>[ 15.154314] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10755 23:08:41.825524 <6>[ 15.154441] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10756 23:08:41.831936 <6>[ 15.154475] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10757 23:08:41.838663 <6>[ 15.154498] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10758 23:08:41.848876 <6>[ 15.154519] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10759 23:08:41.852168 <6>[ 15.154641] pci 0000:01:00.0: supports D1 D2
10760 23:08:41.859142 <6>[ 15.154645] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10761 23:08:41.868611 <3>[ 15.155606] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10762 23:08:41.875291 <4>[ 15.164665] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10763 23:08:41.884822 <4>[ 15.164673] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10764 23:08:41.891192 <6>[ 15.164844] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10765 23:08:41.898054 <6>[ 15.164873] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10766 23:08:41.908286 <6>[ 15.164879] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10767 23:08:41.914641 <6>[ 15.164892] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10768 23:08:41.924330 <6>[ 15.164908] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10769 23:08:41.931695 <6>[ 15.164924] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10770 23:08:41.937618 <6>[ 15.164940] pci 0000:00:00.0: PCI bridge to [bus 01]
10771 23:08:41.944504 <6>[ 15.164949] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10772 23:08:41.951013 <6>[ 15.165056] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10773 23:08:41.957567 <6>[ 15.167468] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10774 23:08:41.963652 <6>[ 15.173123] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10775 23:08:41.973668 <6>[ 15.173593] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10776 23:08:41.977095 <6>[ 15.173625] remoteproc remoteproc0: remote processor scp is now up
10777 23:08:41.987725 <3>[ 15.174184] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10778 23:08:41.994156 <6>[ 15.174885] usbcore: registered new interface driver cdc_ether
10779 23:08:42.000386 <6>[ 15.181419] usbcore: registered new interface driver r8153_ecm
10780 23:08:42.003850 <6>[ 15.181744] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10781 23:08:42.013337 <6>[ 15.183094] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10782 23:08:42.020063 <6>[ 15.186401] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10783 23:08:42.030438 <3>[ 15.190092] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10784 23:08:42.033668 <6>[ 15.190661] Bluetooth: Core ver 2.22
10785 23:08:42.040546 <6>[ 15.191166] NET: Registered PF_BLUETOOTH protocol family
10786 23:08:42.046753 <6>[ 15.191172] Bluetooth: HCI device and connection manager initialized
10787 23:08:42.049627 <6>[ 15.191213] Bluetooth: HCI socket layer initialized
10788 23:08:42.056747 <6>[ 15.191226] Bluetooth: L2CAP socket layer initialized
10789 23:08:42.059936 <6>[ 15.191248] Bluetooth: SCO socket layer initialized
10790 23:08:42.069978 <6>[ 15.201716] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10791 23:08:42.076752 <5>[ 15.205461] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10792 23:08:42.083169 <3>[ 15.206231] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10793 23:08:42.096358 <6>[ 15.213915] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10794 23:08:42.102412 <5>[ 15.214389] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10795 23:08:42.113149 <4>[ 15.214469] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10796 23:08:42.116272 <6>[ 15.214478] cfg80211: failed to load regulatory.db
10797 23:08:42.125978 <3>[ 15.219095] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10798 23:08:42.132421 <6>[ 15.221372] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10799 23:08:42.135645 <6>[ 15.229092] r8152 2-1.3:1.0 eth0: v1.12.13
10800 23:08:42.142868 <6>[ 15.230492] usbcore: registered new interface driver uvcvideo
10801 23:08:42.148769 <3>[ 15.235355] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10802 23:08:42.155754 <6>[ 15.248084] usbcore: registered new interface driver btusb
10803 23:08:42.165681 <4>[ 15.248888] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10804 23:08:42.171956 <3>[ 15.248902] Bluetooth: hci0: Failed to load firmware file (-2)
10805 23:08:42.178852 <3>[ 15.248905] Bluetooth: hci0: Failed to set up firmware (-2)
10806 23:08:42.188591 <4>[ 15.248909] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10807 23:08:42.195365 <6>[ 15.249440] r8152 2-1.3:1.0 enx0024323078ff: renamed from eth0
10808 23:08:42.201607 <3>[ 15.254104] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10809 23:08:42.211716 <3>[ 15.254112] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10810 23:08:42.218437 <3>[ 15.254118] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10811 23:08:42.224899 <6>[ 15.295444] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10812 23:08:42.234913 <3>[ 15.295605] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10813 23:08:42.241452 <6>[ 15.302551] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10814 23:08:42.248034 <3>[ 15.310562] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10815 23:08:42.254269 <6>[ 15.336925] mt7921e 0000:01:00.0: ASIC revision: 79610010
10816 23:08:42.361085 <4>[ 15.792324] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10817 23:08:42.363894 Begin: Loading essential drivers ... done.
10818 23:08:42.370718 Begin: Running /scripts/init-premount ... done.
10819 23:08:42.377003 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10820 23:08:42.387034 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10821 23:08:42.390503 Device /sys/class/net/enx0024323078ff found
10822 23:08:42.391058 done.
10823 23:08:42.453986 IP-Config: enx0024323078ff hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10824 23:08:42.479926 <4>[ 15.911059] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10825 23:08:42.594078 <4>[ 16.026202] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10826 23:08:42.710508 <4>[ 16.141975] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10827 23:08:42.825707 <4>[ 16.257899] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10828 23:08:42.942217 <4>[ 16.374029] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10829 23:08:43.058361 <4>[ 16.490053] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10830 23:08:43.173889 <4>[ 16.605887] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10831 23:08:43.289888 <4>[ 16.721938] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10832 23:08:43.405765 <4>[ 16.837839] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10833 23:08:43.476991 <6>[ 16.915421] r8152 2-1.3:1.0 enx0024323078ff: carrier on
10834 23:08:43.513657 <3>[ 16.951784] mt7921e 0000:01:00.0: hardware init failed
10835 23:08:43.722222 IP-Config: no response after 2 secs - giving up
10836 23:08:43.773835 IP-Config: enx0024323078ff hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10837 23:08:43.777423 IP-Config: enx0024323078ff complete (dhcp from 192.168.201.1):
10838 23:08:43.783989 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10839 23:08:43.793338 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10840 23:08:43.800388 host : mt8192-asurada-spherion-r0-cbg-8
10841 23:08:43.806814 domain : lava-rack
10842 23:08:43.810032 rootserver: 192.168.201.1 rootpath:
10843 23:08:43.810495 filename :
10844 23:08:43.932629 done.
10845 23:08:43.940815 Begin: Running /scripts/nfs-bottom ... done.
10846 23:08:43.958765 Begin: Running /scripts/init-bottom ... done.
10847 23:08:45.202344 <6>[ 18.641288] NET: Registered PF_INET6 protocol family
10848 23:08:45.210170 <6>[ 18.648774] Segment Routing with IPv6
10849 23:08:45.213393 <6>[ 18.652715] In-situ OAM (IOAM) with IPv6
10850 23:08:45.343972 <30>[ 18.762955] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10851 23:08:45.347424 <30>[ 18.787356] systemd[1]: Detected architecture arm64.
10852 23:08:45.372143
10853 23:08:45.375609 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10854 23:08:45.376173
10855 23:08:45.393939 <30>[ 18.832319] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10856 23:08:46.409410 <30>[ 19.845250] systemd[1]: Queued start job for default target Graphical Interface.
10857 23:08:46.436338 <30>[ 19.875433] systemd[1]: Created slice system-getty.slice.
10858 23:08:46.443258 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10859 23:08:46.459734 <30>[ 19.898451] systemd[1]: Created slice system-modprobe.slice.
10860 23:08:46.466178 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10861 23:08:46.483386 <30>[ 19.922249] systemd[1]: Created slice system-serial\x2dgetty.slice.
10862 23:08:46.493590 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10863 23:08:46.507360 <30>[ 19.946098] systemd[1]: Created slice User and Session Slice.
10864 23:08:46.513844 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10865 23:08:46.534845 <30>[ 19.969873] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10866 23:08:46.543949 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10867 23:08:46.562935 <30>[ 19.997794] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10868 23:08:46.568927 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10869 23:08:46.593246 <30>[ 20.025189] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10870 23:08:46.599988 <30>[ 20.037330] systemd[1]: Reached target Local Encrypted Volumes.
10871 23:08:46.606060 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10872 23:08:46.622393 <30>[ 20.061201] systemd[1]: Reached target Paths.
10873 23:08:46.625567 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10874 23:08:46.642103 <30>[ 20.081058] systemd[1]: Reached target Remote File Systems.
10875 23:08:46.648735 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10876 23:08:46.666248 <30>[ 20.105407] systemd[1]: Reached target Slices.
10877 23:08:46.673093 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10878 23:08:46.686203 <30>[ 20.125058] systemd[1]: Reached target Swap.
10879 23:08:46.689645 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10880 23:08:46.710611 <30>[ 20.145533] systemd[1]: Listening on initctl Compatibility Named Pipe.
10881 23:08:46.716553 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10882 23:08:46.723293 <30>[ 20.161906] systemd[1]: Listening on Journal Audit Socket.
10883 23:08:46.730238 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10884 23:08:46.747762 <30>[ 20.186648] systemd[1]: Listening on Journal Socket (/dev/log).
10885 23:08:46.754548 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10886 23:08:46.770616 <30>[ 20.209585] systemd[1]: Listening on Journal Socket.
10887 23:08:46.777419 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10888 23:08:46.795457 <30>[ 20.230911] systemd[1]: Listening on Network Service Netlink Socket.
10889 23:08:46.801981 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10890 23:08:46.817973 <30>[ 20.256933] systemd[1]: Listening on udev Control Socket.
10891 23:08:46.824600 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10892 23:08:46.838543 <30>[ 20.277457] systemd[1]: Listening on udev Kernel Socket.
10893 23:08:46.845415 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10894 23:08:46.886204 <30>[ 20.325144] systemd[1]: Mounting Huge Pages File System...
10895 23:08:46.892709 Mounting [0;1;39mHuge Pages File System[0m...
10896 23:08:46.910650 <30>[ 20.349404] systemd[1]: Mounting POSIX Message Queue File System...
10897 23:08:46.917145 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10898 23:08:46.970664 <30>[ 20.409238] systemd[1]: Mounting Kernel Debug File System...
10899 23:08:46.976680 Mounting [0;1;39mKernel Debug File System[0m...
10900 23:08:46.993196 <30>[ 20.429388] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10901 23:08:47.010705 <30>[ 20.446984] systemd[1]: Starting Create list of static device nodes for the current kernel...
10902 23:08:47.021071 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10903 23:08:47.054660 <30>[ 20.493738] systemd[1]: Starting Load Kernel Module configfs...
10904 23:08:47.061333 Starting [0;1;39mLoad Kernel Module configfs[0m...
10905 23:08:47.079516 <30>[ 20.518179] systemd[1]: Starting Load Kernel Module drm...
10906 23:08:47.085583 Starting [0;1;39mLoad Kernel Module drm[0m...
10907 23:08:47.102757 <30>[ 20.541924] systemd[1]: Starting Load Kernel Module fuse...
10908 23:08:47.109454 Starting [0;1;39mLoad Kernel Module fuse[0m...
10909 23:08:47.146569 <6>[ 20.585469] fuse: init (API version 7.37)
10910 23:08:47.156404 <30>[ 20.586440] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10911 23:08:47.195653 <30>[ 20.633912] systemd[1]: Starting Journal Service...
10912 23:08:47.201338 Starting [0;1;39mJournal Service[0m...
10913 23:08:47.226807 <30>[ 20.665816] systemd[1]: Starting Load Kernel Modules...
10914 23:08:47.233526 Starting [0;1;39mLoad Kernel Modules[0m...
10915 23:08:47.256327 <30>[ 20.692076] systemd[1]: Starting Remount Root and Kernel File Systems...
10916 23:08:47.262869 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10917 23:08:47.281997 <30>[ 20.721207] systemd[1]: Starting Coldplug All udev Devices...
10918 23:08:47.289316 Starting [0;1;39mColdplug All udev Devices[0m...
10919 23:08:47.309517 <30>[ 20.748639] systemd[1]: Mounted Huge Pages File System.
10920 23:08:47.315903 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10921 23:08:47.330797 <30>[ 20.769685] systemd[1]: Mounted POSIX Message Queue File System.
10922 23:08:47.337588 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10923 23:08:47.350850 <3>[ 20.786782] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10924 23:08:47.357404 <30>[ 20.796342] systemd[1]: Mounted Kernel Debug File System.
10925 23:08:47.364083 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10926 23:08:47.380478 <3>[ 20.816049] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10927 23:08:47.390419 <30>[ 20.825940] systemd[1]: Finished Create list of static device nodes for the current kernel.
10928 23:08:47.400171 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10929 23:08:47.418932 <30>[ 20.857835] systemd[1]: modprobe@configfs.service: Succeeded.
10930 23:08:47.426567 <30>[ 20.864916] systemd[1]: Finished Load Kernel Module configfs.
10931 23:08:47.436152 <3>[ 20.867610] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10932 23:08:47.443520 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10933 23:08:47.460289 <30>[ 20.898227] systemd[1]: modprobe@drm.service: Succeeded.
10934 23:08:47.469968 <3>[ 20.903982] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10935 23:08:47.473051 <30>[ 20.904524] systemd[1]: Finished Load Kernel Module drm.
10936 23:08:47.480167 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10937 23:08:47.498130 <3>[ 20.933512] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10938 23:08:47.505110 <30>[ 20.944128] systemd[1]: modprobe@fuse.service: Succeeded.
10939 23:08:47.512013 <30>[ 20.950862] systemd[1]: Finished Load Kernel Module fuse.
10940 23:08:47.519272 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10941 23:08:47.529557 <3>[ 20.963565] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10942 23:08:47.536641 <30>[ 20.974017] systemd[1]: Finished Load Kernel Modules.
10943 23:08:47.539513 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10944 23:08:47.557504 <3>[ 20.993254] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10945 23:08:47.564172 <30>[ 20.993937] systemd[1]: Finished Remount Root and Kernel File Systems.
10946 23:08:47.570977 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10947 23:08:47.587301 <3>[ 21.022909] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10948 23:08:47.616533 <3>[ 21.052363] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10949 23:08:47.623198 <30>[ 21.060580] systemd[1]: Mounting FUSE Control File System...
10950 23:08:47.629875 Mounting [0;1;39mFUSE Control File System[0m...
10951 23:08:47.646954 <3>[ 21.082576] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10952 23:08:47.653358 <30>[ 21.085015] systemd[1]: Mounting Kernel Configuration File System...
10953 23:08:47.660261 Mounting [0;1;39mKernel Configuration File System[0m...
10954 23:08:47.684621 <30>[ 21.120038] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10955 23:08:47.694754 <30>[ 21.129170] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10956 23:08:47.703343 <30>[ 21.142568] systemd[1]: Starting Load/Save Random Seed...
10957 23:08:47.710093 Starting [0;1;39mLoad/Save Random Seed[0m...
10958 23:08:47.730174 <30>[ 21.169226] systemd[1]: Starting Apply Kernel Variables...
10959 23:08:47.736821 Starting [0;1;39mApply Kernel Variables[0m...
10960 23:08:47.754443 <30>[ 21.193456] systemd[1]: Starting Create System Users...
10961 23:08:47.761304 Starting [0;1;39mCreate System Users[0m...
10962 23:08:47.776390 <30>[ 21.215198] systemd[1]: Started Journal Service.
10963 23:08:47.782711 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10964 23:08:47.810086 [[0;32m OK [0m] Mounted [0;1;39mFUSE Contro<4>[ 21.238643] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10965 23:08:47.820305 l File System[0<3>[ 21.255542] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10966 23:08:47.820808 m.
10967 23:08:47.835334 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10968 23:08:47.860086 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10969 23:08:47.878144 See 'systemctl status systemd-udev-trigger.service' for details.
10970 23:08:47.899651 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10971 23:08:47.916185 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10972 23:08:47.931402 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10973 23:08:47.983384 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10974 23:08:48.003519 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10975 23:08:48.065792 <46>[ 21.501815] systemd-journald[303]: Received client request to flush runtime journal.
10976 23:08:48.932854 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10977 23:08:48.946367 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10978 23:08:48.961681 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10979 23:08:49.013462 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10980 23:08:49.490874 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10981 23:08:49.534859 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10982 23:08:49.614605 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10983 23:08:49.671077 Starting [0;1;39mNetwork Service[0m...
10984 23:08:50.050730 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10985 23:08:50.075698 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10986 23:08:50.126826 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10987 23:08:50.377182 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10988 23:08:50.397691 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10989 23:08:50.414716 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10990 23:08:50.478789 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10991 23:08:50.498641 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10992 23:08:50.522912 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10993 23:08:50.542954 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10994 23:08:50.630443 Starting [0;1;39mNetwork Name Resolution[0m...
10995 23:08:50.657539 Starting [0;1;39mNetwork Time Synchronization[0m...
10996 23:08:50.680345 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10997 23:08:50.727670 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10998 23:08:50.888838 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10999 23:08:50.910110 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
11000 23:08:50.932807 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
11001 23:08:50.945711 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
11002 23:08:50.961512 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
11003 23:08:51.116134 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
11004 23:08:51.152332 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
11005 23:08:51.181099 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
11006 23:08:51.207733 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11007 23:08:51.221454 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11008 23:08:51.259512 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11009 23:08:51.273927 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11010 23:08:51.289729 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11011 23:08:51.334846 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11012 23:08:51.393346 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
11013 23:08:51.459910 Starting [0;1;39mUser Login Management[0m...
11014 23:08:51.476230 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
11015 23:08:51.496710 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
11016 23:08:51.516607 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
11017 23:08:51.563858 Starting [0;1;39mPermit User Sessions[0m...
11018 23:08:51.674330 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11019 23:08:51.696512 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
11020 23:08:51.740420 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11021 23:08:51.780335 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11022 23:08:51.796778 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11023 23:08:51.819970 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11024 23:08:51.838070 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11025 23:08:51.854085 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11026 23:08:51.916228 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11027 23:08:51.965633 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11028 23:08:52.056862
11029 23:08:52.057412
11030 23:08:52.059834 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11031 23:08:52.060315
11032 23:08:52.063292 debian-bullseye-arm64 login: root (automatic login)
11033 23:08:52.063748
11034 23:08:52.064105
11035 23:08:52.502499 Linux debian-bullseye-arm64 6.1.64-cip10 #1 SMP PREEMPT Fri Dec 1 22:47:09 UTC 2023 aarch64
11036 23:08:52.503101
11037 23:08:52.508714 The programs included with the Debian GNU/Linux system are free software;
11038 23:08:52.515581 the exact distribution terms for each program are described in the
11039 23:08:52.518843 individual files in /usr/share/doc/*/copyright.
11040 23:08:52.519298
11041 23:08:52.525279 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11042 23:08:52.528703 permitted by applicable law.
11043 23:08:53.518616 Matched prompt #10: / #
11045 23:08:53.519853 Setting prompt string to ['/ #']
11046 23:08:53.520406 end: 2.2.5.1 login-action (duration 00:00:28) [common]
11048 23:08:53.521482 end: 2.2.5 auto-login-action (duration 00:00:28) [common]
11049 23:08:53.522027 start: 2.2.6 expect-shell-connection (timeout 00:03:04) [common]
11050 23:08:53.522416 Setting prompt string to ['/ #']
11051 23:08:53.522751 Forcing a shell prompt, looking for ['/ #']
11053 23:08:53.573602 / #
11054 23:08:53.574261 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11055 23:08:53.574785 Waiting using forced prompt support (timeout 00:02:30)
11056 23:08:53.580272
11057 23:08:53.581209 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11058 23:08:53.581758 start: 2.2.7 export-device-env (timeout 00:03:04) [common]
11060 23:08:53.682833 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12154441/extract-nfsrootfs-32vd6yh1'
11061 23:08:53.687978 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12154441/extract-nfsrootfs-32vd6yh1'
11063 23:08:53.788755 / # export NFS_SERVER_IP='192.168.201.1'
11064 23:08:53.795406 export NFS_SERVER_IP='192.168.201.1'
11065 23:08:53.796245 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11066 23:08:53.796792 end: 2.2 depthcharge-retry (duration 00:01:56) [common]
11067 23:08:53.797273 end: 2 depthcharge-action (duration 00:01:56) [common]
11068 23:08:53.797869 start: 3 lava-test-retry (timeout 00:07:22) [common]
11069 23:08:53.798469 start: 3.1 lava-test-shell (timeout 00:07:22) [common]
11070 23:08:53.798975 Using namespace: common
11072 23:08:53.900301 / # #
11073 23:08:53.900950 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11074 23:08:53.907206 #
11075 23:08:53.908086 Using /lava-12154441
11077 23:08:54.009300 / # export SHELL=/bin/bash
11078 23:08:54.016616 export SHELL=/bin/bash
11080 23:08:54.118065 / # . /lava-12154441/environment
11081 23:08:54.123404 . /lava-12154441/environment
11083 23:08:54.230050 / # /lava-12154441/bin/lava-test-runner /lava-12154441/0
11084 23:08:54.230210 Test shell timeout: 10s (minimum of the action and connection timeout)
11085 23:08:54.235943 /lava-12154441/bin/lava-test-runner /lava-12154441/0
11086 23:08:54.607060 + export TESTRUN_ID=0_timesync-off
11087 23:08:54.610111 + TESTRUN_ID=0_timesync-off
11088 23:08:54.613647 + cd /lava-12154441/0/tests/0_timesync-off
11089 23:08:54.617477 ++ cat uuid
11090 23:08:54.627681 + UUID=12154441_1.6.2.3.1
11091 23:08:54.628150 + set +x
11092 23:08:54.633455 <LAVA_SIGNAL_STARTRUN 0_timesync-off 12154441_1.6.2.3.1>
11093 23:08:54.634221 Received signal: <STARTRUN> 0_timesync-off 12154441_1.6.2.3.1
11094 23:08:54.634647 Starting test lava.0_timesync-off (12154441_1.6.2.3.1)
11095 23:08:54.635089 Skipping test definition patterns.
11096 23:08:54.636665 + systemctl stop systemd-timesyncd
11097 23:08:54.717666 + set +x
11098 23:08:54.720664 <LAVA_SIGNAL_ENDRUN 0_timesync-off 12154441_1.6.2.3.1>
11099 23:08:54.721396 Received signal: <ENDRUN> 0_timesync-off 12154441_1.6.2.3.1
11100 23:08:54.721842 Ending use of test pattern.
11101 23:08:54.722190 Ending test lava.0_timesync-off (12154441_1.6.2.3.1), duration 0.09
11103 23:08:54.833272 + export TESTRUN_ID=1_kselftest-dt
11104 23:08:54.836182 + TESTRUN_ID=1_kselftest-dt
11105 23:08:54.839352 + cd /lava-12154441/0/tests/1_kselftest-dt
11106 23:08:54.842703 ++ cat uuid
11107 23:08:54.852319 + UUID=12154441_1.6.2.3.5
11108 23:08:54.852809 + set +x
11109 23:08:54.859125 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 12154441_1.6.2.3.5>
11110 23:08:54.860507 Received signal: <STARTRUN> 1_kselftest-dt 12154441_1.6.2.3.5
11111 23:08:54.860922 Starting test lava.1_kselftest-dt (12154441_1.6.2.3.5)
11112 23:08:54.861397 Skipping test definition patterns.
11113 23:08:54.862469 + cd ./automated/linux/kselftest/
11114 23:08:54.885448 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.64-cip10/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11115 23:08:54.949380 INFO: install_deps skipped
11116 23:08:55.085793 --2023-12-01 23:08:55-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.64-cip10/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11117 23:08:55.102626 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11118 23:08:55.231518 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11119 23:08:55.359916 HTTP request sent, awaiting response... 200 OK
11120 23:08:55.363372 Length: 2967588 (2.8M) [application/octet-stream]
11121 23:08:55.366909 Saving to: 'kselftest.tar.xz'
11122 23:08:55.366997
11123 23:08:55.367064
11124 23:08:55.618061 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11125 23:08:55.876391 kselftest.tar.xz 1%[ ] 47.81K 191KB/s
11126 23:08:56.135060 kselftest.tar.xz 7%[> ] 217.50K 433KB/s
11127 23:08:56.452974 kselftest.tar.xz 30%[=====> ] 896.25K 1.16MB/s
11128 23:08:56.468665 kselftest.tar.xz 46%[========> ] 1.31M 1.23MB/s
11129 23:08:56.474583 kselftest.tar.xz 100%[===================>] 2.83M 2.62MB/s in 1.1s
11130 23:08:56.474667
11131 23:08:56.732948 2023-12-01 23:08:56 (2.62 MB/s) - 'kselftest.tar.xz' saved [2967588/2967588]
11132 23:08:56.733103
11133 23:09:03.024208 skiplist:
11134 23:09:03.027495 ========================================
11135 23:09:03.030665 ========================================
11136 23:09:03.100878 ============== Tests to run ===============
11137 23:09:03.103891 ===========End Tests to run ===============
11138 23:09:03.110066 shardfile-dt fail
11139 23:09:03.135220 ./kselftest.sh: 131: cannot open /lava-12154441/0/tests/1_kselftest-dt/automated/linux/kselftest/output/kselftest.txt: No such file
11140 23:09:03.138850 + ../../utils/send-to-lava.sh ./output/result.txt
11141 23:09:03.225200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=fail>
11142 23:09:03.225306 + set +x
11143 23:09:03.225553 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=fail
11145 23:09:03.231586 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 12154441_1.6.2.3.5>
11146 23:09:03.231839 Received signal: <ENDRUN> 1_kselftest-dt 12154441_1.6.2.3.5
11147 23:09:03.231911 Ending use of test pattern.
11148 23:09:03.231972 Ending test lava.1_kselftest-dt (12154441_1.6.2.3.5), duration 8.37
11150 23:09:03.232183 ok: lava_test_shell seems to have completed
11151 23:09:03.232323 shardfile-dt: fail
11152 23:09:03.232411 end: 3.1 lava-test-shell (duration 00:00:09) [common]
11153 23:09:03.232492 end: 3 lava-test-retry (duration 00:00:09) [common]
11154 23:09:03.232577 start: 4 finalize (timeout 00:07:12) [common]
11155 23:09:03.232663 start: 4.1 power-off (timeout 00:00:30) [common]
11156 23:09:03.232817 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
11157 23:09:03.309281 >> Command sent successfully.
11158 23:09:03.311807 Returned 0 in 0 seconds
11159 23:09:03.412206 end: 4.1 power-off (duration 00:00:00) [common]
11161 23:09:03.412531 start: 4.2 read-feedback (timeout 00:07:12) [common]
11163 23:09:03.413094 Listened to connection for namespace 'common' for up to 1s
11164 23:09:04.413549 Finalising connection for namespace 'common'
11165 23:09:04.413732 Disconnecting from shell: Finalise
11166 23:09:04.413816 / #
11167 23:09:04.514151 end: 4.2 read-feedback (duration 00:00:01) [common]
11168 23:09:04.514304 end: 4 finalize (duration 00:00:01) [common]
11169 23:09:04.514425 Cleaning after the job
11170 23:09:04.514525 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12154441/tftp-deploy-apkqk93d/ramdisk
11171 23:09:04.517446 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12154441/tftp-deploy-apkqk93d/kernel
11172 23:09:04.529682 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12154441/tftp-deploy-apkqk93d/dtb
11173 23:09:04.529850 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12154441/tftp-deploy-apkqk93d/nfsrootfs
11174 23:09:04.619854 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12154441/tftp-deploy-apkqk93d/modules
11175 23:09:04.627195 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12154441
11176 23:09:05.257800 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12154441
11177 23:09:05.257988 Job finished correctly