Boot log: mt8192-asurada-spherion-r0
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 31
- Kernel Errors: 44
- Errors: 0
1 23:04:55.986846 lava-dispatcher, installed at version: 2023.10
2 23:04:55.987076 start: 0 validate
3 23:04:55.987215 Start time: 2023-12-01 23:04:55.987207+00:00 (UTC)
4 23:04:55.987344 Using caching service: 'http://localhost/cache/?uri=%s'
5 23:04:55.987483 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 23:04:56.254838 Using caching service: 'http://localhost/cache/?uri=%s'
7 23:04:56.255011 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.64-cip10%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 23:04:56.521076 Using caching service: 'http://localhost/cache/?uri=%s'
9 23:04:56.521278 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.64-cip10%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 23:04:56.779258 Using caching service: 'http://localhost/cache/?uri=%s'
11 23:04:56.779440 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 23:04:57.046086 Using caching service: 'http://localhost/cache/?uri=%s'
13 23:04:57.046276 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.64-cip10%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 23:04:57.314868 validate duration: 1.33
16 23:04:57.315131 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 23:04:57.315230 start: 1.1 download-retry (timeout 00:10:00) [common]
18 23:04:57.315318 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 23:04:57.315444 Not decompressing ramdisk as can be used compressed.
20 23:04:57.315528 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/initrd.cpio.gz
21 23:04:57.315592 saving as /var/lib/lava/dispatcher/tmp/12154432/tftp-deploy-jdza9gty/ramdisk/initrd.cpio.gz
22 23:04:57.315657 total size: 4665395 (4 MB)
23 23:04:57.316715 progress 0 % (0 MB)
24 23:04:57.318249 progress 5 % (0 MB)
25 23:04:57.319506 progress 10 % (0 MB)
26 23:04:57.320765 progress 15 % (0 MB)
27 23:04:57.322059 progress 20 % (0 MB)
28 23:04:57.323291 progress 25 % (1 MB)
29 23:04:57.324553 progress 30 % (1 MB)
30 23:04:57.325832 progress 35 % (1 MB)
31 23:04:57.327081 progress 40 % (1 MB)
32 23:04:57.328470 progress 45 % (2 MB)
33 23:04:57.329744 progress 50 % (2 MB)
34 23:04:57.331001 progress 55 % (2 MB)
35 23:04:57.332245 progress 60 % (2 MB)
36 23:04:57.333523 progress 65 % (2 MB)
37 23:04:57.334751 progress 70 % (3 MB)
38 23:04:57.335975 progress 75 % (3 MB)
39 23:04:57.337216 progress 80 % (3 MB)
40 23:04:57.338681 progress 85 % (3 MB)
41 23:04:57.339908 progress 90 % (4 MB)
42 23:04:57.341131 progress 95 % (4 MB)
43 23:04:57.342408 progress 100 % (4 MB)
44 23:04:57.342562 4 MB downloaded in 0.03 s (165.37 MB/s)
45 23:04:57.342720 end: 1.1.1 http-download (duration 00:00:00) [common]
47 23:04:57.342958 end: 1.1 download-retry (duration 00:00:00) [common]
48 23:04:57.343045 start: 1.2 download-retry (timeout 00:10:00) [common]
49 23:04:57.343129 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 23:04:57.343276 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.64-cip10/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 23:04:57.343346 saving as /var/lib/lava/dispatcher/tmp/12154432/tftp-deploy-jdza9gty/kernel/Image
52 23:04:57.343407 total size: 49172992 (46 MB)
53 23:04:57.343469 No compression specified
54 23:04:57.344544 progress 0 % (0 MB)
55 23:04:57.357221 progress 5 % (2 MB)
56 23:04:57.370209 progress 10 % (4 MB)
57 23:04:57.383060 progress 15 % (7 MB)
58 23:04:57.395699 progress 20 % (9 MB)
59 23:04:57.408443 progress 25 % (11 MB)
60 23:04:57.421386 progress 30 % (14 MB)
61 23:04:57.434299 progress 35 % (16 MB)
62 23:04:57.446945 progress 40 % (18 MB)
63 23:04:57.459613 progress 45 % (21 MB)
64 23:04:57.472472 progress 50 % (23 MB)
65 23:04:57.485129 progress 55 % (25 MB)
66 23:04:57.497975 progress 60 % (28 MB)
67 23:04:57.510918 progress 65 % (30 MB)
68 23:04:57.523692 progress 70 % (32 MB)
69 23:04:57.536564 progress 75 % (35 MB)
70 23:04:57.549234 progress 80 % (37 MB)
71 23:04:57.561912 progress 85 % (39 MB)
72 23:04:57.574610 progress 90 % (42 MB)
73 23:04:57.587219 progress 95 % (44 MB)
74 23:04:57.599693 progress 100 % (46 MB)
75 23:04:57.599927 46 MB downloaded in 0.26 s (182.82 MB/s)
76 23:04:57.600081 end: 1.2.1 http-download (duration 00:00:00) [common]
78 23:04:57.600323 end: 1.2 download-retry (duration 00:00:00) [common]
79 23:04:57.600412 start: 1.3 download-retry (timeout 00:10:00) [common]
80 23:04:57.600499 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 23:04:57.600644 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.64-cip10/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 23:04:57.600717 saving as /var/lib/lava/dispatcher/tmp/12154432/tftp-deploy-jdza9gty/dtb/mt8192-asurada-spherion-r0.dtb
83 23:04:57.600779 total size: 47278 (0 MB)
84 23:04:57.600841 No compression specified
85 23:04:57.601955 progress 69 % (0 MB)
86 23:04:57.602238 progress 100 % (0 MB)
87 23:04:57.602421 0 MB downloaded in 0.00 s (27.51 MB/s)
88 23:04:57.602575 end: 1.3.1 http-download (duration 00:00:00) [common]
90 23:04:57.602802 end: 1.3 download-retry (duration 00:00:00) [common]
91 23:04:57.602891 start: 1.4 download-retry (timeout 00:10:00) [common]
92 23:04:57.602974 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 23:04:57.603092 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/full.rootfs.tar.xz
94 23:04:57.603161 saving as /var/lib/lava/dispatcher/tmp/12154432/tftp-deploy-jdza9gty/nfsrootfs/full.rootfs.tar
95 23:04:57.603223 total size: 200813988 (191 MB)
96 23:04:57.603284 Using unxz to decompress xz
97 23:04:57.607413 progress 0 % (0 MB)
98 23:04:58.144166 progress 5 % (9 MB)
99 23:04:58.661482 progress 10 % (19 MB)
100 23:04:59.249722 progress 15 % (28 MB)
101 23:04:59.623713 progress 20 % (38 MB)
102 23:04:59.956236 progress 25 % (47 MB)
103 23:05:00.542954 progress 30 % (57 MB)
104 23:05:01.094798 progress 35 % (67 MB)
105 23:05:01.688832 progress 40 % (76 MB)
106 23:05:02.248201 progress 45 % (86 MB)
107 23:05:02.835625 progress 50 % (95 MB)
108 23:05:03.464641 progress 55 % (105 MB)
109 23:05:04.120797 progress 60 % (114 MB)
110 23:05:04.237922 progress 65 % (124 MB)
111 23:05:04.377556 progress 70 % (134 MB)
112 23:05:04.477957 progress 75 % (143 MB)
113 23:05:04.551221 progress 80 % (153 MB)
114 23:05:04.621075 progress 85 % (162 MB)
115 23:05:04.721480 progress 90 % (172 MB)
116 23:05:05.001751 progress 95 % (181 MB)
117 23:05:05.588122 progress 100 % (191 MB)
118 23:05:05.594074 191 MB downloaded in 7.99 s (23.97 MB/s)
119 23:05:05.594405 end: 1.4.1 http-download (duration 00:00:08) [common]
121 23:05:05.594734 end: 1.4 download-retry (duration 00:00:08) [common]
122 23:05:05.594862 start: 1.5 download-retry (timeout 00:09:52) [common]
123 23:05:05.594963 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 23:05:05.595162 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.64-cip10/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 23:05:05.595278 saving as /var/lib/lava/dispatcher/tmp/12154432/tftp-deploy-jdza9gty/modules/modules.tar
126 23:05:05.595363 total size: 8616152 (8 MB)
127 23:05:05.595474 Using unxz to decompress xz
128 23:05:05.600133 progress 0 % (0 MB)
129 23:05:05.624809 progress 5 % (0 MB)
130 23:05:05.650397 progress 10 % (0 MB)
131 23:05:05.678396 progress 15 % (1 MB)
132 23:05:05.702988 progress 20 % (1 MB)
133 23:05:05.727852 progress 25 % (2 MB)
134 23:05:05.754590 progress 30 % (2 MB)
135 23:05:05.781439 progress 35 % (2 MB)
136 23:05:05.805303 progress 40 % (3 MB)
137 23:05:05.830064 progress 45 % (3 MB)
138 23:05:05.855703 progress 50 % (4 MB)
139 23:05:05.880425 progress 55 % (4 MB)
140 23:05:05.906408 progress 60 % (4 MB)
141 23:05:05.934072 progress 65 % (5 MB)
142 23:05:05.964902 progress 70 % (5 MB)
143 23:05:05.990789 progress 75 % (6 MB)
144 23:05:06.019177 progress 80 % (6 MB)
145 23:05:06.046768 progress 85 % (7 MB)
146 23:05:06.073570 progress 90 % (7 MB)
147 23:05:06.104057 progress 95 % (7 MB)
148 23:05:06.132895 progress 100 % (8 MB)
149 23:05:06.139751 8 MB downloaded in 0.54 s (15.09 MB/s)
150 23:05:06.140035 end: 1.5.1 http-download (duration 00:00:01) [common]
152 23:05:06.140302 end: 1.5 download-retry (duration 00:00:01) [common]
153 23:05:06.140397 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 23:05:06.140492 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 23:05:09.781267 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12154432/extract-nfsrootfs-g7mgmqe7
156 23:05:09.781531 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 23:05:09.781632 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 23:05:09.781824 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12154432/lava-overlay-qr4ek4p9
159 23:05:09.781969 makedir: /var/lib/lava/dispatcher/tmp/12154432/lava-overlay-qr4ek4p9/lava-12154432/bin
160 23:05:09.782077 makedir: /var/lib/lava/dispatcher/tmp/12154432/lava-overlay-qr4ek4p9/lava-12154432/tests
161 23:05:09.782190 makedir: /var/lib/lava/dispatcher/tmp/12154432/lava-overlay-qr4ek4p9/lava-12154432/results
162 23:05:09.782298 Creating /var/lib/lava/dispatcher/tmp/12154432/lava-overlay-qr4ek4p9/lava-12154432/bin/lava-add-keys
163 23:05:09.782460 Creating /var/lib/lava/dispatcher/tmp/12154432/lava-overlay-qr4ek4p9/lava-12154432/bin/lava-add-sources
164 23:05:09.782595 Creating /var/lib/lava/dispatcher/tmp/12154432/lava-overlay-qr4ek4p9/lava-12154432/bin/lava-background-process-start
165 23:05:09.782734 Creating /var/lib/lava/dispatcher/tmp/12154432/lava-overlay-qr4ek4p9/lava-12154432/bin/lava-background-process-stop
166 23:05:09.782865 Creating /var/lib/lava/dispatcher/tmp/12154432/lava-overlay-qr4ek4p9/lava-12154432/bin/lava-common-functions
167 23:05:09.783003 Creating /var/lib/lava/dispatcher/tmp/12154432/lava-overlay-qr4ek4p9/lava-12154432/bin/lava-echo-ipv4
168 23:05:09.783133 Creating /var/lib/lava/dispatcher/tmp/12154432/lava-overlay-qr4ek4p9/lava-12154432/bin/lava-install-packages
169 23:05:09.783269 Creating /var/lib/lava/dispatcher/tmp/12154432/lava-overlay-qr4ek4p9/lava-12154432/bin/lava-installed-packages
170 23:05:09.783398 Creating /var/lib/lava/dispatcher/tmp/12154432/lava-overlay-qr4ek4p9/lava-12154432/bin/lava-os-build
171 23:05:09.783537 Creating /var/lib/lava/dispatcher/tmp/12154432/lava-overlay-qr4ek4p9/lava-12154432/bin/lava-probe-channel
172 23:05:09.783666 Creating /var/lib/lava/dispatcher/tmp/12154432/lava-overlay-qr4ek4p9/lava-12154432/bin/lava-probe-ip
173 23:05:09.783803 Creating /var/lib/lava/dispatcher/tmp/12154432/lava-overlay-qr4ek4p9/lava-12154432/bin/lava-target-ip
174 23:05:09.783938 Creating /var/lib/lava/dispatcher/tmp/12154432/lava-overlay-qr4ek4p9/lava-12154432/bin/lava-target-mac
175 23:05:09.784067 Creating /var/lib/lava/dispatcher/tmp/12154432/lava-overlay-qr4ek4p9/lava-12154432/bin/lava-target-storage
176 23:05:09.784205 Creating /var/lib/lava/dispatcher/tmp/12154432/lava-overlay-qr4ek4p9/lava-12154432/bin/lava-test-case
177 23:05:09.784338 Creating /var/lib/lava/dispatcher/tmp/12154432/lava-overlay-qr4ek4p9/lava-12154432/bin/lava-test-event
178 23:05:09.784472 Creating /var/lib/lava/dispatcher/tmp/12154432/lava-overlay-qr4ek4p9/lava-12154432/bin/lava-test-feedback
179 23:05:09.784601 Creating /var/lib/lava/dispatcher/tmp/12154432/lava-overlay-qr4ek4p9/lava-12154432/bin/lava-test-raise
180 23:05:09.784735 Creating /var/lib/lava/dispatcher/tmp/12154432/lava-overlay-qr4ek4p9/lava-12154432/bin/lava-test-reference
181 23:05:09.784865 Creating /var/lib/lava/dispatcher/tmp/12154432/lava-overlay-qr4ek4p9/lava-12154432/bin/lava-test-runner
182 23:05:09.785002 Creating /var/lib/lava/dispatcher/tmp/12154432/lava-overlay-qr4ek4p9/lava-12154432/bin/lava-test-set
183 23:05:09.785134 Creating /var/lib/lava/dispatcher/tmp/12154432/lava-overlay-qr4ek4p9/lava-12154432/bin/lava-test-shell
184 23:05:09.785273 Updating /var/lib/lava/dispatcher/tmp/12154432/lava-overlay-qr4ek4p9/lava-12154432/bin/lava-add-keys (debian)
185 23:05:09.785575 Updating /var/lib/lava/dispatcher/tmp/12154432/lava-overlay-qr4ek4p9/lava-12154432/bin/lava-add-sources (debian)
186 23:05:09.785768 Updating /var/lib/lava/dispatcher/tmp/12154432/lava-overlay-qr4ek4p9/lava-12154432/bin/lava-install-packages (debian)
187 23:05:09.785917 Updating /var/lib/lava/dispatcher/tmp/12154432/lava-overlay-qr4ek4p9/lava-12154432/bin/lava-installed-packages (debian)
188 23:05:09.786073 Updating /var/lib/lava/dispatcher/tmp/12154432/lava-overlay-qr4ek4p9/lava-12154432/bin/lava-os-build (debian)
189 23:05:09.786206 Creating /var/lib/lava/dispatcher/tmp/12154432/lava-overlay-qr4ek4p9/lava-12154432/environment
190 23:05:09.786319 LAVA metadata
191 23:05:09.786394 - LAVA_JOB_ID=12154432
192 23:05:09.786467 - LAVA_DISPATCHER_IP=192.168.201.1
193 23:05:09.786578 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
194 23:05:09.786647 skipped lava-vland-overlay
195 23:05:09.786731 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 23:05:09.786815 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
197 23:05:09.786880 skipped lava-multinode-overlay
198 23:05:09.786956 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 23:05:09.787044 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
200 23:05:09.787121 Loading test definitions
201 23:05:09.787214 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
202 23:05:09.787294 Using /lava-12154432 at stage 0
203 23:05:09.787600 uuid=12154432_1.6.2.3.1 testdef=None
204 23:05:09.787691 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 23:05:09.787788 start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
206 23:05:09.788310 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 23:05:09.788541 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
209 23:05:09.789131 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 23:05:09.789372 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
212 23:05:09.789997 runner path: /var/lib/lava/dispatcher/tmp/12154432/lava-overlay-qr4ek4p9/lava-12154432/0/tests/0_timesync-off test_uuid 12154432_1.6.2.3.1
213 23:05:09.790159 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 23:05:09.790396 start: 1.6.2.3.5 git-repo-action (timeout 00:09:48) [common]
216 23:05:09.790470 Using /lava-12154432 at stage 0
217 23:05:09.790576 Fetching tests from https://github.com/kernelci/test-definitions.git
218 23:05:09.790658 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/12154432/lava-overlay-qr4ek4p9/lava-12154432/0/tests/1_kselftest-rtc'
219 23:05:12.902517 Running '/usr/bin/git checkout kernelci.org
220 23:05:13.052118 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12154432/lava-overlay-qr4ek4p9/lava-12154432/0/tests/1_kselftest-rtc/automated/linux/kselftest/kselftest.yaml
221 23:05:13.052913 uuid=12154432_1.6.2.3.5 testdef=None
222 23:05:13.053082 end: 1.6.2.3.5 git-repo-action (duration 00:00:03) [common]
224 23:05:13.053349 start: 1.6.2.3.6 test-overlay (timeout 00:09:44) [common]
225 23:05:13.054193 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 23:05:13.054435 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:44) [common]
228 23:05:13.055478 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 23:05:13.055726 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:44) [common]
231 23:05:13.056766 runner path: /var/lib/lava/dispatcher/tmp/12154432/lava-overlay-qr4ek4p9/lava-12154432/0/tests/1_kselftest-rtc test_uuid 12154432_1.6.2.3.5
232 23:05:13.056865 BOARD='mt8192-asurada-spherion-r0'
233 23:05:13.056933 BRANCH='cip'
234 23:05:13.056996 SKIPFILE='/dev/null'
235 23:05:13.057055 SKIP_INSTALL='True'
236 23:05:13.057119 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.64-cip10/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 23:05:13.057182 TST_CASENAME=''
238 23:05:13.057240 TST_CMDFILES='rtc'
239 23:05:13.057386 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 23:05:13.057682 Creating lava-test-runner.conf files
242 23:05:13.057749 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12154432/lava-overlay-qr4ek4p9/lava-12154432/0 for stage 0
243 23:05:13.057846 - 0_timesync-off
244 23:05:13.057922 - 1_kselftest-rtc
245 23:05:13.058027 end: 1.6.2.3 test-definition (duration 00:00:03) [common]
246 23:05:13.058118 start: 1.6.2.4 compress-overlay (timeout 00:09:44) [common]
247 23:05:20.659765 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 23:05:20.659932 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:37) [common]
249 23:05:20.660025 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 23:05:20.660135 end: 1.6.2 lava-overlay (duration 00:00:11) [common]
251 23:05:20.660228 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:37) [common]
252 23:05:20.782311 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 23:05:20.782794 start: 1.6.4 extract-modules (timeout 00:09:37) [common]
254 23:05:20.782918 extracting modules file /var/lib/lava/dispatcher/tmp/12154432/tftp-deploy-jdza9gty/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12154432/extract-nfsrootfs-g7mgmqe7
255 23:05:21.018719 extracting modules file /var/lib/lava/dispatcher/tmp/12154432/tftp-deploy-jdza9gty/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12154432/extract-overlay-ramdisk-eux5dv6h/ramdisk
256 23:05:21.313023 end: 1.6.4 extract-modules (duration 00:00:01) [common]
257 23:05:21.313192 start: 1.6.5 apply-overlay-tftp (timeout 00:09:36) [common]
258 23:05:21.313288 [common] Applying overlay to NFS
259 23:05:21.313371 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12154432/compress-overlay-sp6rksm4/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12154432/extract-nfsrootfs-g7mgmqe7
260 23:05:22.265202 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 23:05:22.265374 start: 1.6.6 configure-preseed-file (timeout 00:09:35) [common]
262 23:05:22.265572 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 23:05:22.265663 start: 1.6.7 compress-ramdisk (timeout 00:09:35) [common]
264 23:05:22.265746 Building ramdisk /var/lib/lava/dispatcher/tmp/12154432/extract-overlay-ramdisk-eux5dv6h/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12154432/extract-overlay-ramdisk-eux5dv6h/ramdisk
265 23:05:22.564261 >> 119410 blocks
266 23:05:24.546659 rename /var/lib/lava/dispatcher/tmp/12154432/extract-overlay-ramdisk-eux5dv6h/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12154432/tftp-deploy-jdza9gty/ramdisk/ramdisk.cpio.gz
267 23:05:24.547103 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 23:05:24.547232 start: 1.6.8 prepare-kernel (timeout 00:09:33) [common]
269 23:05:24.547332 start: 1.6.8.1 prepare-fit (timeout 00:09:33) [common]
270 23:05:24.547442 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12154432/tftp-deploy-jdza9gty/kernel/Image'
271 23:05:36.643553 Returned 0 in 12 seconds
272 23:05:36.744202 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12154432/tftp-deploy-jdza9gty/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12154432/tftp-deploy-jdza9gty/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12154432/tftp-deploy-jdza9gty/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12154432/tftp-deploy-jdza9gty/kernel/image.itb
273 23:05:37.086283 output: FIT description: Kernel Image image with one or more FDT blobs
274 23:05:37.086686 output: Created: Fri Dec 1 23:05:37 2023
275 23:05:37.086765 output: Image 0 (kernel-1)
276 23:05:37.086836 output: Description:
277 23:05:37.086902 output: Created: Fri Dec 1 23:05:37 2023
278 23:05:37.086964 output: Type: Kernel Image
279 23:05:37.087023 output: Compression: lzma compressed
280 23:05:37.087084 output: Data Size: 11043984 Bytes = 10785.14 KiB = 10.53 MiB
281 23:05:37.087143 output: Architecture: AArch64
282 23:05:37.087201 output: OS: Linux
283 23:05:37.087258 output: Load Address: 0x00000000
284 23:05:37.087316 output: Entry Point: 0x00000000
285 23:05:37.087375 output: Hash algo: crc32
286 23:05:37.087434 output: Hash value: 36c84243
287 23:05:37.087494 output: Image 1 (fdt-1)
288 23:05:37.087550 output: Description: mt8192-asurada-spherion-r0
289 23:05:37.087605 output: Created: Fri Dec 1 23:05:37 2023
290 23:05:37.087659 output: Type: Flat Device Tree
291 23:05:37.087712 output: Compression: uncompressed
292 23:05:37.087765 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 23:05:37.087819 output: Architecture: AArch64
294 23:05:37.087873 output: Hash algo: crc32
295 23:05:37.087926 output: Hash value: cc4352de
296 23:05:37.087980 output: Image 2 (ramdisk-1)
297 23:05:37.088034 output: Description: unavailable
298 23:05:37.088087 output: Created: Fri Dec 1 23:05:37 2023
299 23:05:37.088141 output: Type: RAMDisk Image
300 23:05:37.088194 output: Compression: Unknown Compression
301 23:05:37.088248 output: Data Size: 17799737 Bytes = 17382.56 KiB = 16.98 MiB
302 23:05:37.088303 output: Architecture: AArch64
303 23:05:37.088356 output: OS: Linux
304 23:05:37.088412 output: Load Address: unavailable
305 23:05:37.088465 output: Entry Point: unavailable
306 23:05:37.088518 output: Hash algo: crc32
307 23:05:37.088572 output: Hash value: c18c5c1e
308 23:05:37.088625 output: Default Configuration: 'conf-1'
309 23:05:37.088678 output: Configuration 0 (conf-1)
310 23:05:37.088731 output: Description: mt8192-asurada-spherion-r0
311 23:05:37.088785 output: Kernel: kernel-1
312 23:05:37.088838 output: Init Ramdisk: ramdisk-1
313 23:05:37.088891 output: FDT: fdt-1
314 23:05:37.088944 output: Loadables: kernel-1
315 23:05:37.088997 output:
316 23:05:37.089204 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
317 23:05:37.089302 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
318 23:05:37.089415 end: 1.6 prepare-tftp-overlay (duration 00:00:31) [common]
319 23:05:37.089553 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:20) [common]
320 23:05:37.089633 No LXC device requested
321 23:05:37.089712 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 23:05:37.089795 start: 1.8 deploy-device-env (timeout 00:09:20) [common]
323 23:05:37.089874 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 23:05:37.089945 Checking files for TFTP limit of 4294967296 bytes.
325 23:05:37.090446 end: 1 tftp-deploy (duration 00:00:40) [common]
326 23:05:37.090552 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 23:05:37.090644 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 23:05:37.090777 substitutions:
329 23:05:37.090847 - {DTB}: 12154432/tftp-deploy-jdza9gty/dtb/mt8192-asurada-spherion-r0.dtb
330 23:05:37.090913 - {INITRD}: 12154432/tftp-deploy-jdza9gty/ramdisk/ramdisk.cpio.gz
331 23:05:37.090974 - {KERNEL}: 12154432/tftp-deploy-jdza9gty/kernel/Image
332 23:05:37.091032 - {LAVA_MAC}: None
333 23:05:37.091090 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12154432/extract-nfsrootfs-g7mgmqe7
334 23:05:37.091148 - {NFS_SERVER_IP}: 192.168.201.1
335 23:05:37.091204 - {PRESEED_CONFIG}: None
336 23:05:37.091259 - {PRESEED_LOCAL}: None
337 23:05:37.091315 - {RAMDISK}: 12154432/tftp-deploy-jdza9gty/ramdisk/ramdisk.cpio.gz
338 23:05:37.091370 - {ROOT_PART}: None
339 23:05:37.091425 - {ROOT}: None
340 23:05:37.091480 - {SERVER_IP}: 192.168.201.1
341 23:05:37.091535 - {TEE}: None
342 23:05:37.091590 Parsed boot commands:
343 23:05:37.091644 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 23:05:37.091830 Parsed boot commands: tftpboot 192.168.201.1 12154432/tftp-deploy-jdza9gty/kernel/image.itb 12154432/tftp-deploy-jdza9gty/kernel/cmdline
345 23:05:37.091919 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 23:05:37.092001 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 23:05:37.092097 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 23:05:37.092185 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 23:05:37.092262 Not connected, no need to disconnect.
350 23:05:37.092338 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 23:05:37.092417 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 23:05:37.092486 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-9'
353 23:05:37.096583 Setting prompt string to ['lava-test: # ']
354 23:05:37.096958 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 23:05:37.097069 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 23:05:37.097174 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 23:05:37.097271 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 23:05:37.097509 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=reboot'
359 23:05:42.224304 >> Command sent successfully.
360 23:05:42.226714 Returned 0 in 5 seconds
361 23:05:42.327085 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 23:05:42.327438 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 23:05:42.327559 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 23:05:42.327661 Setting prompt string to 'Starting depthcharge on Spherion...'
366 23:05:42.327738 Changing prompt to 'Starting depthcharge on Spherion...'
367 23:05:42.327813 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 23:05:42.328099 [Enter `^Ec?' for help]
369 23:05:42.500583
370 23:05:42.500760
371 23:05:42.500867 F0: 102B 0000
372 23:05:42.500964
373 23:05:42.501054 F3: 1001 0000 [0200]
374 23:05:42.501153
375 23:05:42.504048 F3: 1001 0000
376 23:05:42.504148
377 23:05:42.504217 F7: 102D 0000
378 23:05:42.504280
379 23:05:42.504343 F1: 0000 0000
380 23:05:42.504415
381 23:05:42.507736 V0: 0000 0000 [0001]
382 23:05:42.507835
383 23:05:42.507936 00: 0007 8000
384 23:05:42.508031
385 23:05:42.511229 01: 0000 0000
386 23:05:42.511334
387 23:05:42.511427 BP: 0C00 0209 [0000]
388 23:05:42.511516
389 23:05:42.515121 G0: 1182 0000
390 23:05:42.515194
391 23:05:42.515256 EC: 0000 0021 [4000]
392 23:05:42.515315
393 23:05:42.518745 S7: 0000 0000 [0000]
394 23:05:42.518820
395 23:05:42.518920 CC: 0000 0000 [0001]
396 23:05:42.519030
397 23:05:42.521975 T0: 0000 0040 [010F]
398 23:05:42.522047
399 23:05:42.522107 Jump to BL
400 23:05:42.522165
401 23:05:42.547002
402 23:05:42.547087
403 23:05:42.547155
404 23:05:42.554357 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 23:05:42.558063 ARM64: Exception handlers installed.
406 23:05:42.561330 ARM64: Testing exception
407 23:05:42.564941 ARM64: Done test exception
408 23:05:42.571977 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 23:05:42.582294 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 23:05:42.589822 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 23:05:42.600538 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 23:05:42.607453 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 23:05:42.613562 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 23:05:42.623979 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 23:05:42.630347 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 23:05:42.649785 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 23:05:42.653041 WDT: Last reset was cold boot
418 23:05:42.656659 SPI1(PAD0) initialized at 2873684 Hz
419 23:05:42.659504 SPI5(PAD0) initialized at 992727 Hz
420 23:05:42.662709 VBOOT: Loading verstage.
421 23:05:42.669345 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 23:05:42.672955 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 23:05:42.676481 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 23:05:42.682387 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 23:05:42.689159 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 23:05:42.696350 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 23:05:42.704972 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 23:05:42.705082
429 23:05:42.705177
430 23:05:42.714727 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 23:05:42.718453 ARM64: Exception handlers installed.
432 23:05:42.721302 ARM64: Testing exception
433 23:05:42.721386 ARM64: Done test exception
434 23:05:42.728295 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 23:05:42.731250 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 23:05:42.745328 Probing TPM: . done!
437 23:05:42.745418 TPM ready after 0 ms
438 23:05:42.753111 Connected to device vid:did:rid of 1ae0:0028:00
439 23:05:42.762000 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
440 23:05:42.800960 Initialized TPM device CR50 revision 0
441 23:05:42.812304 tlcl_send_startup: Startup return code is 0
442 23:05:42.812418 TPM: setup succeeded
443 23:05:42.824181 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 23:05:42.832232 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 23:05:42.842829 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 23:05:42.851727 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 23:05:42.854687 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 23:05:42.858585 in-header: 03 07 00 00 08 00 00 00
449 23:05:42.861361 in-data: aa e4 47 04 13 02 00 00
450 23:05:42.865116 Chrome EC: UHEPI supported
451 23:05:42.871575 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 23:05:42.874663 in-header: 03 ad 00 00 08 00 00 00
453 23:05:42.877887 in-data: 00 20 20 08 00 00 00 00
454 23:05:42.877973 Phase 1
455 23:05:42.881390 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 23:05:42.888044 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 23:05:42.894494 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 23:05:42.898110 Recovery requested (1009000e)
459 23:05:42.905316 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 23:05:42.910214 tlcl_extend: response is 0
461 23:05:42.918578 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 23:05:42.924130 tlcl_extend: response is 0
463 23:05:42.930633 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 23:05:42.951141 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 23:05:42.958181 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 23:05:42.958283
467 23:05:42.958384
468 23:05:42.968364 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 23:05:42.971629 ARM64: Exception handlers installed.
470 23:05:42.971731 ARM64: Testing exception
471 23:05:42.975284 ARM64: Done test exception
472 23:05:42.996776 pmic_efuse_setting: Set efuses in 11 msecs
473 23:05:43.000818 pmwrap_interface_init: Select PMIF_VLD_RDY
474 23:05:43.004283 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 23:05:43.011971 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 23:05:43.014410 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 23:05:43.020986 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 23:05:43.024469 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 23:05:43.031256 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 23:05:43.034348 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 23:05:43.041148 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 23:05:43.044264 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 23:05:43.047659 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 23:05:43.054333 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 23:05:43.058041 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 23:05:43.060752 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 23:05:43.068051 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 23:05:43.074462 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 23:05:43.081315 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 23:05:43.084296 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 23:05:43.090723 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 23:05:43.097430 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 23:05:43.104183 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 23:05:43.107930 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 23:05:43.114862 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 23:05:43.118547 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 23:05:43.126687 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 23:05:43.129405 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 23:05:43.135666 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 23:05:43.139780 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 23:05:43.146245 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 23:05:43.149240 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 23:05:43.156091 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 23:05:43.159272 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 23:05:43.166694 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 23:05:43.170021 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 23:05:43.176638 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 23:05:43.180369 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 23:05:43.186691 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 23:05:43.190400 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 23:05:43.196386 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 23:05:43.200003 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 23:05:43.204000 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 23:05:43.207540 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 23:05:43.214927 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 23:05:43.218066 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 23:05:43.221504 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 23:05:43.225080 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 23:05:43.231836 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 23:05:43.235197 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 23:05:43.237980 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 23:05:43.245014 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 23:05:43.248026 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 23:05:43.251771 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 23:05:43.257881 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 23:05:43.268249 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 23:05:43.271117 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 23:05:43.281650 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 23:05:43.287579 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 23:05:43.294377 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 23:05:43.297857 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 23:05:43.300810 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 23:05:43.308938 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x8
534 23:05:43.315671 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 23:05:43.319235 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
536 23:05:43.325300 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 23:05:43.333540 [RTC]rtc_get_frequency_meter,154: input=15, output=835
538 23:05:43.343298 [RTC]rtc_get_frequency_meter,154: input=7, output=709
539 23:05:43.352484 [RTC]rtc_get_frequency_meter,154: input=11, output=772
540 23:05:43.362140 [RTC]rtc_get_frequency_meter,154: input=13, output=804
541 23:05:43.371430 [RTC]rtc_get_frequency_meter,154: input=12, output=787
542 23:05:43.381274 [RTC]rtc_get_frequency_meter,154: input=12, output=788
543 23:05:43.390805 [RTC]rtc_get_frequency_meter,154: input=13, output=804
544 23:05:43.393795 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
545 23:05:43.401380 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
546 23:05:43.404525 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 23:05:43.407658 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 23:05:43.415245 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 23:05:43.417582 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 23:05:43.420879 ADC[4]: Raw value=902291 ID=7
551 23:05:43.421059 ADC[3]: Raw value=212912 ID=1
552 23:05:43.424400 RAM Code: 0x71
553 23:05:43.427518 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 23:05:43.434092 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 23:05:43.440717 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 23:05:43.447974 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 23:05:43.451070 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 23:05:43.455047 in-header: 03 07 00 00 08 00 00 00
559 23:05:43.457522 in-data: aa e4 47 04 13 02 00 00
560 23:05:43.461021 Chrome EC: UHEPI supported
561 23:05:43.467438 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 23:05:43.470989 in-header: 03 dd 00 00 08 00 00 00
563 23:05:43.473990 in-data: 90 20 60 08 00 00 00 00
564 23:05:43.477252 MRC: failed to locate region type 0.
565 23:05:43.484186 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 23:05:43.487513 DRAM-K: Running full calibration
567 23:05:43.494217 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 23:05:43.494304 header.status = 0x0
569 23:05:43.497008 header.version = 0x6 (expected: 0x6)
570 23:05:43.500605 header.size = 0xd00 (expected: 0xd00)
571 23:05:43.503678 header.flags = 0x0
572 23:05:43.510927 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 23:05:43.527674 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
574 23:05:43.533977 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 23:05:43.537065 dram_init: ddr_geometry: 2
576 23:05:43.540539 [EMI] MDL number = 2
577 23:05:43.540630 [EMI] Get MDL freq = 0
578 23:05:43.544220 dram_init: ddr_type: 0
579 23:05:43.544305 is_discrete_lpddr4: 1
580 23:05:43.547486 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 23:05:43.550197
582 23:05:43.550282
583 23:05:43.550350 [Bian_co] ETT version 0.0.0.1
584 23:05:43.557069 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 23:05:43.557155
586 23:05:43.560737 dramc_set_vcore_voltage set vcore to 650000
587 23:05:43.564112 Read voltage for 800, 4
588 23:05:43.564198 Vio18 = 0
589 23:05:43.564267 Vcore = 650000
590 23:05:43.567140 Vdram = 0
591 23:05:43.567226 Vddq = 0
592 23:05:43.567295 Vmddr = 0
593 23:05:43.570594 dram_init: config_dvfs: 1
594 23:05:43.573793 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 23:05:43.580543 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 23:05:43.583789 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
597 23:05:43.587447 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
598 23:05:43.590457 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
599 23:05:43.596769 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
600 23:05:43.596882 MEM_TYPE=3, freq_sel=18
601 23:05:43.600128 sv_algorithm_assistance_LP4_1600
602 23:05:43.603388 ============ PULL DRAM RESETB DOWN ============
603 23:05:43.610030 ========== PULL DRAM RESETB DOWN end =========
604 23:05:43.613146 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 23:05:43.616736 ===================================
606 23:05:43.620044 LPDDR4 DRAM CONFIGURATION
607 23:05:43.623039 ===================================
608 23:05:43.623125 EX_ROW_EN[0] = 0x0
609 23:05:43.626354 EX_ROW_EN[1] = 0x0
610 23:05:43.629792 LP4Y_EN = 0x0
611 23:05:43.629878 WORK_FSP = 0x0
612 23:05:43.633588 WL = 0x2
613 23:05:43.633673 RL = 0x2
614 23:05:43.636204 BL = 0x2
615 23:05:43.636289 RPST = 0x0
616 23:05:43.639607 RD_PRE = 0x0
617 23:05:43.639692 WR_PRE = 0x1
618 23:05:43.642806 WR_PST = 0x0
619 23:05:43.642892 DBI_WR = 0x0
620 23:05:43.645974 DBI_RD = 0x0
621 23:05:43.646059 OTF = 0x1
622 23:05:43.649294 ===================================
623 23:05:43.652670 ===================================
624 23:05:43.656290 ANA top config
625 23:05:43.660309 ===================================
626 23:05:43.660395 DLL_ASYNC_EN = 0
627 23:05:43.663268 ALL_SLAVE_EN = 1
628 23:05:43.666234 NEW_RANK_MODE = 1
629 23:05:43.669331 DLL_IDLE_MODE = 1
630 23:05:43.672580 LP45_APHY_COMB_EN = 1
631 23:05:43.672666 TX_ODT_DIS = 1
632 23:05:43.676495 NEW_8X_MODE = 1
633 23:05:43.679577 ===================================
634 23:05:43.683275 ===================================
635 23:05:43.686231 data_rate = 1600
636 23:05:43.689769 CKR = 1
637 23:05:43.692807 DQ_P2S_RATIO = 8
638 23:05:43.696484 ===================================
639 23:05:43.696570 CA_P2S_RATIO = 8
640 23:05:43.699192 DQ_CA_OPEN = 0
641 23:05:43.703354 DQ_SEMI_OPEN = 0
642 23:05:43.706305 CA_SEMI_OPEN = 0
643 23:05:43.709215 CA_FULL_RATE = 0
644 23:05:43.712665 DQ_CKDIV4_EN = 1
645 23:05:43.712770 CA_CKDIV4_EN = 1
646 23:05:43.716294 CA_PREDIV_EN = 0
647 23:05:43.719104 PH8_DLY = 0
648 23:05:43.722668 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 23:05:43.726106 DQ_AAMCK_DIV = 4
650 23:05:43.729110 CA_AAMCK_DIV = 4
651 23:05:43.729217 CA_ADMCK_DIV = 4
652 23:05:43.732556 DQ_TRACK_CA_EN = 0
653 23:05:43.736040 CA_PICK = 800
654 23:05:43.739375 CA_MCKIO = 800
655 23:05:43.742502 MCKIO_SEMI = 0
656 23:05:43.746025 PLL_FREQ = 3068
657 23:05:43.749109 DQ_UI_PI_RATIO = 32
658 23:05:43.749213 CA_UI_PI_RATIO = 0
659 23:05:43.752415 ===================================
660 23:05:43.756161 ===================================
661 23:05:43.759587 memory_type:LPDDR4
662 23:05:43.762332 GP_NUM : 10
663 23:05:43.762444 SRAM_EN : 1
664 23:05:43.766001 MD32_EN : 0
665 23:05:43.768981 ===================================
666 23:05:43.773247 [ANA_INIT] >>>>>>>>>>>>>>
667 23:05:43.776912 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 23:05:43.779193 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 23:05:43.782314 ===================================
670 23:05:43.782419 data_rate = 1600,PCW = 0X7600
671 23:05:43.785922 ===================================
672 23:05:43.789147 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 23:05:43.796251 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 23:05:43.802725 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 23:05:43.805780 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 23:05:43.809020 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 23:05:43.812742 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 23:05:43.815437 [ANA_INIT] flow start
679 23:05:43.815541 [ANA_INIT] PLL >>>>>>>>
680 23:05:43.818861 [ANA_INIT] PLL <<<<<<<<
681 23:05:43.822425 [ANA_INIT] MIDPI >>>>>>>>
682 23:05:43.825760 [ANA_INIT] MIDPI <<<<<<<<
683 23:05:43.825871 [ANA_INIT] DLL >>>>>>>>
684 23:05:43.829319 [ANA_INIT] flow end
685 23:05:43.832051 ============ LP4 DIFF to SE enter ============
686 23:05:43.835611 ============ LP4 DIFF to SE exit ============
687 23:05:43.839322 [ANA_INIT] <<<<<<<<<<<<<
688 23:05:43.842159 [Flow] Enable top DCM control >>>>>
689 23:05:43.845377 [Flow] Enable top DCM control <<<<<
690 23:05:43.848860 Enable DLL master slave shuffle
691 23:05:43.855525 ==============================================================
692 23:05:43.855640 Gating Mode config
693 23:05:43.862154 ==============================================================
694 23:05:43.862247 Config description:
695 23:05:43.872015 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 23:05:43.879105 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 23:05:43.885721 SELPH_MODE 0: By rank 1: By Phase
698 23:05:43.888839 ==============================================================
699 23:05:43.891820 GAT_TRACK_EN = 1
700 23:05:43.895425 RX_GATING_MODE = 2
701 23:05:43.898707 RX_GATING_TRACK_MODE = 2
702 23:05:43.902293 SELPH_MODE = 1
703 23:05:43.905623 PICG_EARLY_EN = 1
704 23:05:43.908700 VALID_LAT_VALUE = 1
705 23:05:43.911942 ==============================================================
706 23:05:43.915424 Enter into Gating configuration >>>>
707 23:05:43.918457 Exit from Gating configuration <<<<
708 23:05:43.922310 Enter into DVFS_PRE_config >>>>>
709 23:05:43.935442 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 23:05:43.938123 Exit from DVFS_PRE_config <<<<<
711 23:05:43.941571 Enter into PICG configuration >>>>
712 23:05:43.945266 Exit from PICG configuration <<<<
713 23:05:43.945374 [RX_INPUT] configuration >>>>>
714 23:05:43.948302 [RX_INPUT] configuration <<<<<
715 23:05:43.955074 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 23:05:43.958274 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 23:05:43.965864 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 23:05:43.972997 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 23:05:43.979700 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 23:05:43.983293 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 23:05:43.987256 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 23:05:43.990616 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 23:05:43.997666 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 23:05:44.001171 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 23:05:44.004778 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 23:05:44.008302 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 23:05:44.011483 ===================================
728 23:05:44.014994 LPDDR4 DRAM CONFIGURATION
729 23:05:44.019373 ===================================
730 23:05:44.019460 EX_ROW_EN[0] = 0x0
731 23:05:44.022472 EX_ROW_EN[1] = 0x0
732 23:05:44.022560 LP4Y_EN = 0x0
733 23:05:44.025440 WORK_FSP = 0x0
734 23:05:44.029346 WL = 0x2
735 23:05:44.029489 RL = 0x2
736 23:05:44.029560 BL = 0x2
737 23:05:44.033114 RPST = 0x0
738 23:05:44.033199 RD_PRE = 0x0
739 23:05:44.037067 WR_PRE = 0x1
740 23:05:44.037194 WR_PST = 0x0
741 23:05:44.040545 DBI_WR = 0x0
742 23:05:44.040632 DBI_RD = 0x0
743 23:05:44.044220 OTF = 0x1
744 23:05:44.048264 ===================================
745 23:05:44.051191 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 23:05:44.054940 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 23:05:44.058192 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 23:05:44.061635 ===================================
749 23:05:44.065242 LPDDR4 DRAM CONFIGURATION
750 23:05:44.069041 ===================================
751 23:05:44.069128 EX_ROW_EN[0] = 0x10
752 23:05:44.072680 EX_ROW_EN[1] = 0x0
753 23:05:44.072766 LP4Y_EN = 0x0
754 23:05:44.076316 WORK_FSP = 0x0
755 23:05:44.076402 WL = 0x2
756 23:05:44.080449 RL = 0x2
757 23:05:44.080544 BL = 0x2
758 23:05:44.083573 RPST = 0x0
759 23:05:44.083659 RD_PRE = 0x0
760 23:05:44.087231 WR_PRE = 0x1
761 23:05:44.087317 WR_PST = 0x0
762 23:05:44.090624 DBI_WR = 0x0
763 23:05:44.090709 DBI_RD = 0x0
764 23:05:44.094241 OTF = 0x1
765 23:05:44.094327 ===================================
766 23:05:44.101791 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 23:05:44.106051 nWR fixed to 40
768 23:05:44.109385 [ModeRegInit_LP4] CH0 RK0
769 23:05:44.109511 [ModeRegInit_LP4] CH0 RK1
770 23:05:44.113381 [ModeRegInit_LP4] CH1 RK0
771 23:05:44.117571 [ModeRegInit_LP4] CH1 RK1
772 23:05:44.117656 match AC timing 13
773 23:05:44.120515 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 23:05:44.124030 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 23:05:44.130586 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 23:05:44.134176 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 23:05:44.138094 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 23:05:44.140879 [EMI DOE] emi_dcm 0
779 23:05:44.144419 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 23:05:44.144651 ==
781 23:05:44.147425 Dram Type= 6, Freq= 0, CH_0, rank 0
782 23:05:44.154327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 23:05:44.154422 ==
784 23:05:44.157914 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 23:05:44.164348 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 23:05:44.173044 [CA 0] Center 37 (7~68) winsize 62
787 23:05:44.176538 [CA 1] Center 37 (6~68) winsize 63
788 23:05:44.179998 [CA 2] Center 34 (4~65) winsize 62
789 23:05:44.183335 [CA 3] Center 34 (4~65) winsize 62
790 23:05:44.187025 [CA 4] Center 33 (3~64) winsize 62
791 23:05:44.190266 [CA 5] Center 33 (3~64) winsize 62
792 23:05:44.190352
793 23:05:44.193872 [CmdBusTrainingLP45] Vref(ca) range 1: 34
794 23:05:44.193959
795 23:05:44.197144 [CATrainingPosCal] consider 1 rank data
796 23:05:44.200630 u2DelayCellTimex100 = 270/100 ps
797 23:05:44.203697 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
798 23:05:44.207016 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
799 23:05:44.210206 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
800 23:05:44.216977 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
801 23:05:44.220399 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
802 23:05:44.223972 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
803 23:05:44.224057
804 23:05:44.227109 CA PerBit enable=1, Macro0, CA PI delay=33
805 23:05:44.227194
806 23:05:44.230663 [CBTSetCACLKResult] CA Dly = 33
807 23:05:44.230748 CS Dly: 6 (0~37)
808 23:05:44.230817 ==
809 23:05:44.233493 Dram Type= 6, Freq= 0, CH_0, rank 1
810 23:05:44.240242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 23:05:44.240363 ==
812 23:05:44.243241 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 23:05:44.250000 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 23:05:44.259281 [CA 0] Center 37 (6~68) winsize 63
815 23:05:44.262618 [CA 1] Center 37 (7~68) winsize 62
816 23:05:44.266494 [CA 2] Center 34 (4~65) winsize 62
817 23:05:44.269652 [CA 3] Center 34 (4~65) winsize 62
818 23:05:44.273217 [CA 4] Center 33 (3~64) winsize 62
819 23:05:44.276236 [CA 5] Center 33 (3~64) winsize 62
820 23:05:44.276322
821 23:05:44.279280 [CmdBusTrainingLP45] Vref(ca) range 1: 32
822 23:05:44.279366
823 23:05:44.282886 [CATrainingPosCal] consider 2 rank data
824 23:05:44.286100 u2DelayCellTimex100 = 270/100 ps
825 23:05:44.289320 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
826 23:05:44.296218 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
827 23:05:44.299647 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
828 23:05:44.303251 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
829 23:05:44.307402 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
830 23:05:44.310637 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
831 23:05:44.310754
832 23:05:44.314409 CA PerBit enable=1, Macro0, CA PI delay=33
833 23:05:44.314506
834 23:05:44.314610 [CBTSetCACLKResult] CA Dly = 33
835 23:05:44.318055 CS Dly: 6 (0~38)
836 23:05:44.318176
837 23:05:44.321933 ----->DramcWriteLeveling(PI) begin...
838 23:05:44.322023 ==
839 23:05:44.325331 Dram Type= 6, Freq= 0, CH_0, rank 0
840 23:05:44.329643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 23:05:44.329751 ==
842 23:05:44.333030 Write leveling (Byte 0): 34 => 34
843 23:05:44.335973 Write leveling (Byte 1): 29 => 29
844 23:05:44.336084 DramcWriteLeveling(PI) end<-----
845 23:05:44.339580
846 23:05:44.339673 ==
847 23:05:44.343143 Dram Type= 6, Freq= 0, CH_0, rank 0
848 23:05:44.346450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 23:05:44.346543 ==
850 23:05:44.349769 [Gating] SW mode calibration
851 23:05:44.355993 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 23:05:44.358962 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 23:05:44.365936 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 23:05:44.369406 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
855 23:05:44.372480 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
856 23:05:44.379429 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 23:05:44.382627 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 23:05:44.386363 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 23:05:44.392496 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 23:05:44.395586 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 23:05:44.399143 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 23:05:44.405704 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 23:05:44.408937 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 23:05:44.412162 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 23:05:44.418927 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 23:05:44.422331 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 23:05:44.425351 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 23:05:44.432262 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 23:05:44.435172 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
870 23:05:44.438977 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 23:05:44.445564 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
872 23:05:44.448203 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
873 23:05:44.451639 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 23:05:44.458327 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 23:05:44.462211 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 23:05:44.465446 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 23:05:44.471751 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 23:05:44.475338 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 23:05:44.478537 0 9 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
880 23:05:44.484760 0 9 12 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
881 23:05:44.488007 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 23:05:44.491551 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 23:05:44.498045 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 23:05:44.501310 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 23:05:44.505021 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 23:05:44.511672 0 10 4 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
887 23:05:44.514856 0 10 8 | B1->B0 | 3232 2727 | 1 1 | (1 1) (1 0)
888 23:05:44.518344 0 10 12 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
889 23:05:44.525289 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 23:05:44.527833 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 23:05:44.531287 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 23:05:44.538659 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 23:05:44.541027 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 23:05:44.544766 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
895 23:05:44.551409 0 11 8 | B1->B0 | 2424 3c3c | 0 0 | (0 0) (0 0)
896 23:05:44.554784 0 11 12 | B1->B0 | 3939 4646 | 1 0 | (0 0) (0 0)
897 23:05:44.558024 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 23:05:44.564247 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 23:05:44.567692 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 23:05:44.570923 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 23:05:44.577771 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 23:05:44.581553 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
903 23:05:44.584646 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
904 23:05:44.590705 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 23:05:44.594684 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 23:05:44.597293 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 23:05:44.604369 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 23:05:44.607760 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 23:05:44.610935 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 23:05:44.617236 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 23:05:44.620473 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 23:05:44.623830 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 23:05:44.630677 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 23:05:44.633907 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 23:05:44.637226 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 23:05:44.640347 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 23:05:44.647359 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 23:05:44.650550 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
919 23:05:44.653750 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
920 23:05:44.657062 Total UI for P1: 0, mck2ui 16
921 23:05:44.660362 best dqsien dly found for B0: ( 0, 14, 6)
922 23:05:44.667096 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
923 23:05:44.670189 Total UI for P1: 0, mck2ui 16
924 23:05:44.673840 best dqsien dly found for B1: ( 0, 14, 8)
925 23:05:44.676836 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
926 23:05:44.680235 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
927 23:05:44.680320
928 23:05:44.683703 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
929 23:05:44.686925 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
930 23:05:44.690269 [Gating] SW calibration Done
931 23:05:44.690353 ==
932 23:05:44.693936 Dram Type= 6, Freq= 0, CH_0, rank 0
933 23:05:44.697539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 23:05:44.697651 ==
935 23:05:44.697751 RX Vref Scan: 0
936 23:05:44.701043
937 23:05:44.701127 RX Vref 0 -> 0, step: 1
938 23:05:44.701194
939 23:05:44.704954 RX Delay -130 -> 252, step: 16
940 23:05:44.707998 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
941 23:05:44.711062 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
942 23:05:44.717582 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
943 23:05:44.721138 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
944 23:05:44.724138 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
945 23:05:44.727799 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
946 23:05:44.730972 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
947 23:05:44.738073 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
948 23:05:44.741833 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
949 23:05:44.745575 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
950 23:05:44.748926 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
951 23:05:44.752841 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
952 23:05:44.756287 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
953 23:05:44.759981 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
954 23:05:44.763597 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
955 23:05:44.767540 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
956 23:05:44.771259 ==
957 23:05:44.771345 Dram Type= 6, Freq= 0, CH_0, rank 0
958 23:05:44.774853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
959 23:05:44.778901 ==
960 23:05:44.778987 DQS Delay:
961 23:05:44.779074 DQS0 = 0, DQS1 = 0
962 23:05:44.781961 DQM Delay:
963 23:05:44.782073 DQM0 = 86, DQM1 = 71
964 23:05:44.782171 DQ Delay:
965 23:05:44.786019 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
966 23:05:44.789920 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =93
967 23:05:44.793316 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
968 23:05:44.796517 DQ12 =77, DQ13 =77, DQ14 =85, DQ15 =77
969 23:05:44.796596
970 23:05:44.796680
971 23:05:44.796761 ==
972 23:05:44.800526 Dram Type= 6, Freq= 0, CH_0, rank 0
973 23:05:44.803725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 23:05:44.803812 ==
975 23:05:44.803899
976 23:05:44.806849
977 23:05:44.806935 TX Vref Scan disable
978 23:05:44.809951 == TX Byte 0 ==
979 23:05:44.813310 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
980 23:05:44.816648 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
981 23:05:44.819930 == TX Byte 1 ==
982 23:05:44.823186 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
983 23:05:44.826877 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
984 23:05:44.826964 ==
985 23:05:44.829998 Dram Type= 6, Freq= 0, CH_0, rank 0
986 23:05:44.836403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 23:05:44.836489 ==
988 23:05:44.849881 TX Vref=22, minBit 13, minWin=26, winSum=438
989 23:05:44.853086 TX Vref=24, minBit 12, minWin=26, winSum=438
990 23:05:44.857189 TX Vref=26, minBit 8, minWin=27, winSum=446
991 23:05:44.860891 TX Vref=28, minBit 8, minWin=27, winSum=447
992 23:05:44.864338 TX Vref=30, minBit 8, minWin=27, winSum=448
993 23:05:44.868326 TX Vref=32, minBit 11, minWin=26, winSum=440
994 23:05:44.871505 [TxChooseVref] Worse bit 8, Min win 27, Win sum 448, Final Vref 30
995 23:05:44.871589
996 23:05:44.874953 Final TX Range 1 Vref 30
997 23:05:44.875048
998 23:05:44.875115 ==
999 23:05:44.878256 Dram Type= 6, Freq= 0, CH_0, rank 0
1000 23:05:44.881878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1001 23:05:44.884974 ==
1002 23:05:44.885060
1003 23:05:44.885146
1004 23:05:44.885228 TX Vref Scan disable
1005 23:05:44.889037 == TX Byte 0 ==
1006 23:05:44.892055 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1007 23:05:44.899207 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1008 23:05:44.899294 == TX Byte 1 ==
1009 23:05:44.902680 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1010 23:05:44.908799 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1011 23:05:44.908886
1012 23:05:44.908974 [DATLAT]
1013 23:05:44.909056 Freq=800, CH0 RK0
1014 23:05:44.909156
1015 23:05:44.911998 DATLAT Default: 0xa
1016 23:05:44.912084 0, 0xFFFF, sum = 0
1017 23:05:44.915360 1, 0xFFFF, sum = 0
1018 23:05:44.915450 2, 0xFFFF, sum = 0
1019 23:05:44.919105 3, 0xFFFF, sum = 0
1020 23:05:44.922345 4, 0xFFFF, sum = 0
1021 23:05:44.922430 5, 0xFFFF, sum = 0
1022 23:05:44.925600 6, 0xFFFF, sum = 0
1023 23:05:44.925685 7, 0xFFFF, sum = 0
1024 23:05:44.928644 8, 0xFFFF, sum = 0
1025 23:05:44.928732 9, 0x0, sum = 1
1026 23:05:44.928800 10, 0x0, sum = 2
1027 23:05:44.932621 11, 0x0, sum = 3
1028 23:05:44.932705 12, 0x0, sum = 4
1029 23:05:44.935516 best_step = 10
1030 23:05:44.935598
1031 23:05:44.935668 ==
1032 23:05:44.939264 Dram Type= 6, Freq= 0, CH_0, rank 0
1033 23:05:44.942509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1034 23:05:44.942596 ==
1035 23:05:44.945445 RX Vref Scan: 1
1036 23:05:44.945543
1037 23:05:44.945628 Set Vref Range= 32 -> 127
1038 23:05:44.945709
1039 23:05:44.948735 RX Vref 32 -> 127, step: 1
1040 23:05:44.948836
1041 23:05:44.952370 RX Delay -111 -> 252, step: 8
1042 23:05:44.952455
1043 23:05:44.955710 Set Vref, RX VrefLevel [Byte0]: 32
1044 23:05:44.958629 [Byte1]: 32
1045 23:05:44.958714
1046 23:05:44.962335 Set Vref, RX VrefLevel [Byte0]: 33
1047 23:05:44.965229 [Byte1]: 33
1048 23:05:44.969377
1049 23:05:44.969494 Set Vref, RX VrefLevel [Byte0]: 34
1050 23:05:44.972582 [Byte1]: 34
1051 23:05:44.977342
1052 23:05:44.977453 Set Vref, RX VrefLevel [Byte0]: 35
1053 23:05:44.980423 [Byte1]: 35
1054 23:05:44.984673
1055 23:05:44.984758 Set Vref, RX VrefLevel [Byte0]: 36
1056 23:05:44.987867 [Byte1]: 36
1057 23:05:44.992493
1058 23:05:44.992578 Set Vref, RX VrefLevel [Byte0]: 37
1059 23:05:44.996106 [Byte1]: 37
1060 23:05:44.999892
1061 23:05:44.999977 Set Vref, RX VrefLevel [Byte0]: 38
1062 23:05:45.003242 [Byte1]: 38
1063 23:05:45.008028
1064 23:05:45.008110 Set Vref, RX VrefLevel [Byte0]: 39
1065 23:05:45.010867 [Byte1]: 39
1066 23:05:45.015313
1067 23:05:45.015395 Set Vref, RX VrefLevel [Byte0]: 40
1068 23:05:45.021655 [Byte1]: 40
1069 23:05:45.021738
1070 23:05:45.025030 Set Vref, RX VrefLevel [Byte0]: 41
1071 23:05:45.028172 [Byte1]: 41
1072 23:05:45.028254
1073 23:05:45.031610 Set Vref, RX VrefLevel [Byte0]: 42
1074 23:05:45.035432 [Byte1]: 42
1075 23:05:45.038385
1076 23:05:45.038468 Set Vref, RX VrefLevel [Byte0]: 43
1077 23:05:45.041337 [Byte1]: 43
1078 23:05:45.046174
1079 23:05:45.046256 Set Vref, RX VrefLevel [Byte0]: 44
1080 23:05:45.049549 [Byte1]: 44
1081 23:05:45.053404
1082 23:05:45.053532 Set Vref, RX VrefLevel [Byte0]: 45
1083 23:05:45.056650 [Byte1]: 45
1084 23:05:45.061298
1085 23:05:45.061446 Set Vref, RX VrefLevel [Byte0]: 46
1086 23:05:45.064134 [Byte1]: 46
1087 23:05:45.068716
1088 23:05:45.068799 Set Vref, RX VrefLevel [Byte0]: 47
1089 23:05:45.072352 [Byte1]: 47
1090 23:05:45.076991
1091 23:05:45.077074 Set Vref, RX VrefLevel [Byte0]: 48
1092 23:05:45.080062 [Byte1]: 48
1093 23:05:45.083939
1094 23:05:45.084051 Set Vref, RX VrefLevel [Byte0]: 49
1095 23:05:45.087886 [Byte1]: 49
1096 23:05:45.091835
1097 23:05:45.091947 Set Vref, RX VrefLevel [Byte0]: 50
1098 23:05:45.095194 [Byte1]: 50
1099 23:05:45.099200
1100 23:05:45.099283 Set Vref, RX VrefLevel [Byte0]: 51
1101 23:05:45.102784 [Byte1]: 51
1102 23:05:45.107004
1103 23:05:45.107087 Set Vref, RX VrefLevel [Byte0]: 52
1104 23:05:45.110389 [Byte1]: 52
1105 23:05:45.114689
1106 23:05:45.114772 Set Vref, RX VrefLevel [Byte0]: 53
1107 23:05:45.120972 [Byte1]: 53
1108 23:05:45.121055
1109 23:05:45.124801 Set Vref, RX VrefLevel [Byte0]: 54
1110 23:05:45.128087 [Byte1]: 54
1111 23:05:45.128170
1112 23:05:45.130855 Set Vref, RX VrefLevel [Byte0]: 55
1113 23:05:45.134579 [Byte1]: 55
1114 23:05:45.137815
1115 23:05:45.137897 Set Vref, RX VrefLevel [Byte0]: 56
1116 23:05:45.141109 [Byte1]: 56
1117 23:05:45.145135
1118 23:05:45.145219 Set Vref, RX VrefLevel [Byte0]: 57
1119 23:05:45.148957 [Byte1]: 57
1120 23:05:45.153256
1121 23:05:45.153333 Set Vref, RX VrefLevel [Byte0]: 58
1122 23:05:45.156626 [Byte1]: 58
1123 23:05:45.160587
1124 23:05:45.160671 Set Vref, RX VrefLevel [Byte0]: 59
1125 23:05:45.163843 [Byte1]: 59
1126 23:05:45.168555
1127 23:05:45.168640 Set Vref, RX VrefLevel [Byte0]: 60
1128 23:05:45.171516 [Byte1]: 60
1129 23:05:45.175861
1130 23:05:45.175945 Set Vref, RX VrefLevel [Byte0]: 61
1131 23:05:45.179149 [Byte1]: 61
1132 23:05:45.184041
1133 23:05:45.184126 Set Vref, RX VrefLevel [Byte0]: 62
1134 23:05:45.187227 [Byte1]: 62
1135 23:05:45.191523
1136 23:05:45.191608 Set Vref, RX VrefLevel [Byte0]: 63
1137 23:05:45.195315 [Byte1]: 63
1138 23:05:45.199271
1139 23:05:45.199356 Set Vref, RX VrefLevel [Byte0]: 64
1140 23:05:45.202721 [Byte1]: 64
1141 23:05:45.206576
1142 23:05:45.206661 Set Vref, RX VrefLevel [Byte0]: 65
1143 23:05:45.210291 [Byte1]: 65
1144 23:05:45.214298
1145 23:05:45.214383 Set Vref, RX VrefLevel [Byte0]: 66
1146 23:05:45.217504 [Byte1]: 66
1147 23:05:45.222217
1148 23:05:45.222302 Set Vref, RX VrefLevel [Byte0]: 67
1149 23:05:45.225629 [Byte1]: 67
1150 23:05:45.229785
1151 23:05:45.229866 Set Vref, RX VrefLevel [Byte0]: 68
1152 23:05:45.232659 [Byte1]: 68
1153 23:05:45.237603
1154 23:05:45.237685 Set Vref, RX VrefLevel [Byte0]: 69
1155 23:05:45.240348 [Byte1]: 69
1156 23:05:45.244292
1157 23:05:45.247780 Set Vref, RX VrefLevel [Byte0]: 70
1158 23:05:45.250832 [Byte1]: 70
1159 23:05:45.250916
1160 23:05:45.254816 Set Vref, RX VrefLevel [Byte0]: 71
1161 23:05:45.258438 [Byte1]: 71
1162 23:05:45.258520
1163 23:05:45.262576 Set Vref, RX VrefLevel [Byte0]: 72
1164 23:05:45.265551 [Byte1]: 72
1165 23:05:45.265634
1166 23:05:45.269437 Set Vref, RX VrefLevel [Byte0]: 73
1167 23:05:45.273382 [Byte1]: 73
1168 23:05:45.273511
1169 23:05:45.276721 Set Vref, RX VrefLevel [Byte0]: 74
1170 23:05:45.280517 [Byte1]: 74
1171 23:05:45.280600
1172 23:05:45.284085 Set Vref, RX VrefLevel [Byte0]: 75
1173 23:05:45.287315 [Byte1]: 75
1174 23:05:45.287399
1175 23:05:45.290948 Set Vref, RX VrefLevel [Byte0]: 76
1176 23:05:45.294538 [Byte1]: 76
1177 23:05:45.298182
1178 23:05:45.298267 Set Vref, RX VrefLevel [Byte0]: 77
1179 23:05:45.301561 [Byte1]: 77
1180 23:05:45.306185
1181 23:05:45.306321 Set Vref, RX VrefLevel [Byte0]: 78
1182 23:05:45.309829 [Byte1]: 78
1183 23:05:45.313933
1184 23:05:45.314041 Set Vref, RX VrefLevel [Byte0]: 79
1185 23:05:45.316988 [Byte1]: 79
1186 23:05:45.321629
1187 23:05:45.321719 Set Vref, RX VrefLevel [Byte0]: 80
1188 23:05:45.324759 [Byte1]: 80
1189 23:05:45.329221
1190 23:05:45.329307 Final RX Vref Byte 0 = 68 to rank0
1191 23:05:45.332291 Final RX Vref Byte 1 = 57 to rank0
1192 23:05:45.336501 Final RX Vref Byte 0 = 68 to rank1
1193 23:05:45.339803 Final RX Vref Byte 1 = 57 to rank1==
1194 23:05:45.344183 Dram Type= 6, Freq= 0, CH_0, rank 0
1195 23:05:45.347418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1196 23:05:45.347504 ==
1197 23:05:45.347591 DQS Delay:
1198 23:05:45.350793 DQS0 = 0, DQS1 = 0
1199 23:05:45.350878 DQM Delay:
1200 23:05:45.354097 DQM0 = 89, DQM1 = 75
1201 23:05:45.354182 DQ Delay:
1202 23:05:45.357248 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84
1203 23:05:45.361000 DQ4 =88, DQ5 =76, DQ6 =100, DQ7 =100
1204 23:05:45.365086 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1205 23:05:45.368699 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =84
1206 23:05:45.368784
1207 23:05:45.368870
1208 23:05:45.376450 [DQSOSCAuto] RK0, (LSB)MR18= 0x4123, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 393 ps
1209 23:05:45.378774 CH0 RK0: MR19=606, MR18=4123
1210 23:05:45.386289 CH0_RK0: MR19=0x606, MR18=0x4123, DQSOSC=393, MR23=63, INC=95, DEC=63
1211 23:05:45.386375
1212 23:05:45.389444 ----->DramcWriteLeveling(PI) begin...
1213 23:05:45.389541 ==
1214 23:05:45.393571 Dram Type= 6, Freq= 0, CH_0, rank 1
1215 23:05:45.396867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1216 23:05:45.396957 ==
1217 23:05:45.400695 Write leveling (Byte 0): 33 => 33
1218 23:05:45.400778 Write leveling (Byte 1): 30 => 30
1219 23:05:45.403958 DramcWriteLeveling(PI) end<-----
1220 23:05:45.404065
1221 23:05:45.404158 ==
1222 23:05:45.407558 Dram Type= 6, Freq= 0, CH_0, rank 1
1223 23:05:45.411479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1224 23:05:45.415095 ==
1225 23:05:45.415177 [Gating] SW mode calibration
1226 23:05:45.462864 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1227 23:05:45.463418 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1228 23:05:45.463948 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1229 23:05:45.464031 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1230 23:05:45.464760 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1231 23:05:45.465032 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 23:05:45.465536 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 23:05:45.466411 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 23:05:45.466502 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 23:05:45.466751 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 23:05:45.506869 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 23:05:45.507564 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 23:05:45.508068 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 23:05:45.508151 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 23:05:45.508526 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 23:05:45.508967 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 23:05:45.509482 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 23:05:45.510245 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 23:05:45.510327 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 23:05:45.510576 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1246 23:05:45.550728 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1247 23:05:45.551007 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1248 23:05:45.551264 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 23:05:45.551333 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 23:05:45.551395 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1251 23:05:45.551640 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 23:05:45.552048 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 23:05:45.552410 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 23:05:45.552484 0 9 8 | B1->B0 | 2424 3030 | 0 0 | (0 0) (0 0)
1255 23:05:45.552731 0 9 12 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
1256 23:05:45.595594 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1257 23:05:45.596096 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1258 23:05:45.596854 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1259 23:05:45.596968 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1260 23:05:45.597276 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1261 23:05:45.598257 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
1262 23:05:45.598614 0 10 8 | B1->B0 | 3030 2d2d | 1 1 | (1 0) (1 1)
1263 23:05:45.599173 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1264 23:05:45.599295 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1265 23:05:45.599869 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1266 23:05:45.636967 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1267 23:05:45.637337 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1268 23:05:45.637942 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1269 23:05:45.638019 0 11 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
1270 23:05:45.638286 0 11 8 | B1->B0 | 3030 3838 | 0 0 | (1 1) (0 0)
1271 23:05:45.638544 0 11 12 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
1272 23:05:45.638616 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1273 23:05:45.638713 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1274 23:05:45.638787 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1275 23:05:45.642510 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1276 23:05:45.645619 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1277 23:05:45.649225 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1278 23:05:45.652370 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1279 23:05:45.656151 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1280 23:05:45.662244 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 23:05:45.665533 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 23:05:45.668895 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 23:05:45.675301 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 23:05:45.678863 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1285 23:05:45.682146 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1286 23:05:45.688541 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1287 23:05:45.691913 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1288 23:05:45.695501 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1289 23:05:45.698768 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1290 23:05:45.705241 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1291 23:05:45.708621 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1292 23:05:45.715195 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1293 23:05:45.718491 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1294 23:05:45.721798 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1295 23:05:45.728024 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1296 23:05:45.728107 Total UI for P1: 0, mck2ui 16
1297 23:05:45.731504 best dqsien dly found for B0: ( 0, 14, 8)
1298 23:05:45.735079 Total UI for P1: 0, mck2ui 16
1299 23:05:45.738184 best dqsien dly found for B1: ( 0, 14, 8)
1300 23:05:45.744658 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1301 23:05:45.748017 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1302 23:05:45.748107
1303 23:05:45.751193 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1304 23:05:45.754931 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1305 23:05:45.757847 [Gating] SW calibration Done
1306 23:05:45.757929 ==
1307 23:05:45.761034 Dram Type= 6, Freq= 0, CH_0, rank 1
1308 23:05:45.764940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1309 23:05:45.765025 ==
1310 23:05:45.767845 RX Vref Scan: 0
1311 23:05:45.767931
1312 23:05:45.768007 RX Vref 0 -> 0, step: 1
1313 23:05:45.768122
1314 23:05:45.771101 RX Delay -130 -> 252, step: 16
1315 23:05:45.774566 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1316 23:05:45.781323 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1317 23:05:45.784719 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1318 23:05:45.788322 iDelay=222, Bit 3, Center 77 (-34 ~ 189) 224
1319 23:05:45.791226 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1320 23:05:45.794339 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1321 23:05:45.801070 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1322 23:05:45.804168 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1323 23:05:45.807417 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1324 23:05:45.810856 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1325 23:05:45.814157 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1326 23:05:45.820863 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1327 23:05:45.824243 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1328 23:05:45.827617 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1329 23:05:45.830944 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1330 23:05:45.834117 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1331 23:05:45.837205 ==
1332 23:05:45.841061 Dram Type= 6, Freq= 0, CH_0, rank 1
1333 23:05:45.844137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1334 23:05:45.844220 ==
1335 23:05:45.844286 DQS Delay:
1336 23:05:45.847614 DQS0 = 0, DQS1 = 0
1337 23:05:45.847696 DQM Delay:
1338 23:05:45.851185 DQM0 = 84, DQM1 = 79
1339 23:05:45.851267 DQ Delay:
1340 23:05:45.854282 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77
1341 23:05:45.857368 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1342 23:05:45.860676 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1343 23:05:45.864634 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1344 23:05:45.864717
1345 23:05:45.864782
1346 23:05:45.864842 ==
1347 23:05:45.868008 Dram Type= 6, Freq= 0, CH_0, rank 1
1348 23:05:45.871284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1349 23:05:45.871366 ==
1350 23:05:45.871431
1351 23:05:45.871491
1352 23:05:45.874303 TX Vref Scan disable
1353 23:05:45.877359 == TX Byte 0 ==
1354 23:05:45.880817 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1355 23:05:45.884230 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1356 23:05:45.888184 == TX Byte 1 ==
1357 23:05:45.890872 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1358 23:05:45.893814 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1359 23:05:45.893897 ==
1360 23:05:45.897260 Dram Type= 6, Freq= 0, CH_0, rank 1
1361 23:05:45.900606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1362 23:05:45.903974 ==
1363 23:05:45.915277 TX Vref=22, minBit 3, minWin=27, winSum=441
1364 23:05:45.918547 TX Vref=24, minBit 8, minWin=26, winSum=444
1365 23:05:45.922103 TX Vref=26, minBit 9, minWin=27, winSum=447
1366 23:05:45.925255 TX Vref=28, minBit 8, minWin=27, winSum=447
1367 23:05:45.928648 TX Vref=30, minBit 8, minWin=27, winSum=445
1368 23:05:45.935437 TX Vref=32, minBit 8, minWin=27, winSum=446
1369 23:05:45.938403 [TxChooseVref] Worse bit 9, Min win 27, Win sum 447, Final Vref 26
1370 23:05:45.938477
1371 23:05:45.942386 Final TX Range 1 Vref 26
1372 23:05:45.942468
1373 23:05:45.942533 ==
1374 23:05:45.945089 Dram Type= 6, Freq= 0, CH_0, rank 1
1375 23:05:45.948628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1376 23:05:45.948710 ==
1377 23:05:45.952080
1378 23:05:45.952150
1379 23:05:45.952212 TX Vref Scan disable
1380 23:05:45.955240 == TX Byte 0 ==
1381 23:05:45.958877 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1382 23:05:45.965541 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1383 23:05:45.965622 == TX Byte 1 ==
1384 23:05:45.968447 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1385 23:05:45.975155 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1386 23:05:45.975236
1387 23:05:45.975301 [DATLAT]
1388 23:05:45.975362 Freq=800, CH0 RK1
1389 23:05:45.975421
1390 23:05:45.978793 DATLAT Default: 0xa
1391 23:05:45.978875 0, 0xFFFF, sum = 0
1392 23:05:45.981522 1, 0xFFFF, sum = 0
1393 23:05:45.985378 2, 0xFFFF, sum = 0
1394 23:05:45.985494 3, 0xFFFF, sum = 0
1395 23:05:45.988197 4, 0xFFFF, sum = 0
1396 23:05:45.988279 5, 0xFFFF, sum = 0
1397 23:05:45.991976 6, 0xFFFF, sum = 0
1398 23:05:45.992059 7, 0xFFFF, sum = 0
1399 23:05:45.994816 8, 0xFFFF, sum = 0
1400 23:05:45.994898 9, 0x0, sum = 1
1401 23:05:45.998167 10, 0x0, sum = 2
1402 23:05:45.998250 11, 0x0, sum = 3
1403 23:05:45.998318 12, 0x0, sum = 4
1404 23:05:46.002130 best_step = 10
1405 23:05:46.002211
1406 23:05:46.002275 ==
1407 23:05:46.004917 Dram Type= 6, Freq= 0, CH_0, rank 1
1408 23:05:46.008160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1409 23:05:46.008242 ==
1410 23:05:46.011697 RX Vref Scan: 0
1411 23:05:46.011778
1412 23:05:46.015143 RX Vref 0 -> 0, step: 1
1413 23:05:46.015224
1414 23:05:46.015289 RX Delay -95 -> 252, step: 8
1415 23:05:46.022192 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1416 23:05:46.025312 iDelay=217, Bit 1, Center 92 (-23 ~ 208) 232
1417 23:05:46.028844 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
1418 23:05:46.032028 iDelay=217, Bit 3, Center 76 (-39 ~ 192) 232
1419 23:05:46.038620 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
1420 23:05:46.041813 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1421 23:05:46.044998 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1422 23:05:46.048523 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1423 23:05:46.051489 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
1424 23:05:46.055416 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1425 23:05:46.061357 iDelay=217, Bit 10, Center 80 (-39 ~ 200) 240
1426 23:05:46.064845 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
1427 23:05:46.068406 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1428 23:05:46.071839 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1429 23:05:46.078412 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1430 23:05:46.081563 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1431 23:05:46.081645 ==
1432 23:05:46.084676 Dram Type= 6, Freq= 0, CH_0, rank 1
1433 23:05:46.087914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1434 23:05:46.087995 ==
1435 23:05:46.091603 DQS Delay:
1436 23:05:46.091684 DQS0 = 0, DQS1 = 0
1437 23:05:46.091749 DQM Delay:
1438 23:05:46.094969 DQM0 = 84, DQM1 = 76
1439 23:05:46.095050 DQ Delay:
1440 23:05:46.097924 DQ0 =84, DQ1 =92, DQ2 =76, DQ3 =76
1441 23:05:46.101323 DQ4 =84, DQ5 =76, DQ6 =92, DQ7 =96
1442 23:05:46.105276 DQ8 =68, DQ9 =60, DQ10 =80, DQ11 =68
1443 23:05:46.107945 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1444 23:05:46.108026
1445 23:05:46.108090
1446 23:05:46.117973 [DQSOSCAuto] RK1, (LSB)MR18= 0x440a, (MSB)MR19= 0x606, tDQSOscB0 = 407 ps tDQSOscB1 = 392 ps
1447 23:05:46.118055 CH0 RK1: MR19=606, MR18=440A
1448 23:05:46.124459 CH0_RK1: MR19=0x606, MR18=0x440A, DQSOSC=392, MR23=63, INC=96, DEC=64
1449 23:05:46.128290 [RxdqsGatingPostProcess] freq 800
1450 23:05:46.134713 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1451 23:05:46.137639 Pre-setting of DQS Precalculation
1452 23:05:46.140982 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1453 23:05:46.141063 ==
1454 23:05:46.144621 Dram Type= 6, Freq= 0, CH_1, rank 0
1455 23:05:46.151207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1456 23:05:46.151289 ==
1457 23:05:46.154168 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1458 23:05:46.160761 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1459 23:05:46.170413 [CA 0] Center 36 (6~67) winsize 62
1460 23:05:46.173654 [CA 1] Center 36 (6~67) winsize 62
1461 23:05:46.177114 [CA 2] Center 34 (4~65) winsize 62
1462 23:05:46.180387 [CA 3] Center 34 (3~65) winsize 63
1463 23:05:46.183945 [CA 4] Center 34 (4~65) winsize 62
1464 23:05:46.187474 [CA 5] Center 34 (3~65) winsize 63
1465 23:05:46.187556
1466 23:05:46.190484 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1467 23:05:46.190572
1468 23:05:46.194028 [CATrainingPosCal] consider 1 rank data
1469 23:05:46.196868 u2DelayCellTimex100 = 270/100 ps
1470 23:05:46.200179 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1471 23:05:46.206656 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1472 23:05:46.209821 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1473 23:05:46.213285 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1474 23:05:46.216732 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1475 23:05:46.220342 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1476 23:05:46.220424
1477 23:05:46.223267 CA PerBit enable=1, Macro0, CA PI delay=34
1478 23:05:46.223349
1479 23:05:46.226816 [CBTSetCACLKResult] CA Dly = 34
1480 23:05:46.230092 CS Dly: 4 (0~35)
1481 23:05:46.230173 ==
1482 23:05:46.232837 Dram Type= 6, Freq= 0, CH_1, rank 1
1483 23:05:46.236454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1484 23:05:46.236526 ==
1485 23:05:46.242947 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1486 23:05:46.245835 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1487 23:05:46.256415 [CA 0] Center 36 (6~67) winsize 62
1488 23:05:46.259969 [CA 1] Center 36 (6~67) winsize 62
1489 23:05:46.262942 [CA 2] Center 34 (4~65) winsize 62
1490 23:05:46.266554 [CA 3] Center 34 (3~65) winsize 63
1491 23:05:46.270094 [CA 4] Center 34 (4~65) winsize 62
1492 23:05:46.273386 [CA 5] Center 34 (3~65) winsize 63
1493 23:05:46.273488
1494 23:05:46.276555 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1495 23:05:46.276636
1496 23:05:46.279435 [CATrainingPosCal] consider 2 rank data
1497 23:05:46.282926 u2DelayCellTimex100 = 270/100 ps
1498 23:05:46.285898 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1499 23:05:46.292849 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1500 23:05:46.296182 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1501 23:05:46.299414 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1502 23:05:46.302559 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1503 23:05:46.306054 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1504 23:05:46.306137
1505 23:05:46.309365 CA PerBit enable=1, Macro0, CA PI delay=34
1506 23:05:46.309470
1507 23:05:46.312444 [CBTSetCACLKResult] CA Dly = 34
1508 23:05:46.316789 CS Dly: 5 (0~38)
1509 23:05:46.316870
1510 23:05:46.319069 ----->DramcWriteLeveling(PI) begin...
1511 23:05:46.319152 ==
1512 23:05:46.323165 Dram Type= 6, Freq= 0, CH_1, rank 0
1513 23:05:46.326312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1514 23:05:46.326395 ==
1515 23:05:46.329098 Write leveling (Byte 0): 26 => 26
1516 23:05:46.332379 Write leveling (Byte 1): 27 => 27
1517 23:05:46.335553 DramcWriteLeveling(PI) end<-----
1518 23:05:46.335636
1519 23:05:46.335701 ==
1520 23:05:46.338825 Dram Type= 6, Freq= 0, CH_1, rank 0
1521 23:05:46.342493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1522 23:05:46.342579 ==
1523 23:05:46.346181 [Gating] SW mode calibration
1524 23:05:46.352352 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1525 23:05:46.358822 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1526 23:05:46.362267 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1527 23:05:46.365796 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1528 23:05:46.372147 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 23:05:46.375562 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 23:05:46.379312 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 23:05:46.385830 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 23:05:46.389315 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 23:05:46.392425 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 23:05:46.398948 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 23:05:46.402262 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 23:05:46.405689 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 23:05:46.408905 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 23:05:46.415674 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 23:05:46.418695 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 23:05:46.422334 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 23:05:46.428873 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 23:05:46.432173 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 23:05:46.435729 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1544 23:05:46.442261 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1545 23:05:46.445878 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 23:05:46.449293 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 23:05:46.455425 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 23:05:46.459322 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 23:05:46.462180 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 23:05:46.468552 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 23:05:46.472259 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 23:05:46.475124 0 9 8 | B1->B0 | 2d2d 3030 | 0 1 | (0 0) (1 1)
1553 23:05:46.481766 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1554 23:05:46.485160 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1555 23:05:46.488776 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1556 23:05:46.495069 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1557 23:05:46.498200 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1558 23:05:46.501439 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1559 23:05:46.508112 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
1560 23:05:46.511355 0 10 8 | B1->B0 | 2c2c 2525 | 0 1 | (0 0) (0 0)
1561 23:05:46.514995 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1562 23:05:46.521349 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1563 23:05:46.525051 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1564 23:05:46.528571 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1565 23:05:46.534849 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1566 23:05:46.538071 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1567 23:05:46.541307 0 11 4 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
1568 23:05:46.548448 0 11 8 | B1->B0 | 4343 4646 | 0 0 | (1 1) (0 0)
1569 23:05:46.551863 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1570 23:05:46.554676 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1571 23:05:46.561379 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1572 23:05:46.564753 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1573 23:05:46.568365 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1574 23:05:46.575066 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1575 23:05:46.577383 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1576 23:05:46.581029 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 23:05:46.587562 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 23:05:46.591118 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 23:05:46.594304 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 23:05:46.600502 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 23:05:46.604201 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 23:05:46.607686 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1583 23:05:46.614194 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1584 23:05:46.617268 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1585 23:05:46.620599 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1586 23:05:46.626858 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1587 23:05:46.630340 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1588 23:05:46.633320 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1589 23:05:46.640249 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1590 23:05:46.643618 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1591 23:05:46.647432 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1592 23:05:46.653284 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1593 23:05:46.653370 Total UI for P1: 0, mck2ui 16
1594 23:05:46.660136 best dqsien dly found for B0: ( 0, 14, 4)
1595 23:05:46.660221 Total UI for P1: 0, mck2ui 16
1596 23:05:46.663650 best dqsien dly found for B1: ( 0, 14, 6)
1597 23:05:46.670128 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1598 23:05:46.673883 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1599 23:05:46.673967
1600 23:05:46.676630 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1601 23:05:46.679979 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1602 23:05:46.684059 [Gating] SW calibration Done
1603 23:05:46.684143 ==
1604 23:05:46.686673 Dram Type= 6, Freq= 0, CH_1, rank 0
1605 23:05:46.690602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1606 23:05:46.690713 ==
1607 23:05:46.693205 RX Vref Scan: 0
1608 23:05:46.693314
1609 23:05:46.693435 RX Vref 0 -> 0, step: 1
1610 23:05:46.693577
1611 23:05:46.696976 RX Delay -130 -> 252, step: 16
1612 23:05:46.700230 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1613 23:05:46.706812 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1614 23:05:46.710488 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1615 23:05:46.713130 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1616 23:05:46.717136 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1617 23:05:46.720262 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1618 23:05:46.726932 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1619 23:05:46.730342 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1620 23:05:46.733307 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1621 23:05:46.736706 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1622 23:05:46.740100 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1623 23:05:46.746527 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1624 23:05:46.750052 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1625 23:05:46.753431 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1626 23:05:46.757554 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1627 23:05:46.759827 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1628 23:05:46.763518 ==
1629 23:05:46.766486 Dram Type= 6, Freq= 0, CH_1, rank 0
1630 23:05:46.769715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1631 23:05:46.769799 ==
1632 23:05:46.769866 DQS Delay:
1633 23:05:46.773053 DQS0 = 0, DQS1 = 0
1634 23:05:46.773136 DQM Delay:
1635 23:05:46.776589 DQM0 = 89, DQM1 = 78
1636 23:05:46.776672 DQ Delay:
1637 23:05:46.779567 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1638 23:05:46.783230 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1639 23:05:46.786080 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1640 23:05:46.789363 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1641 23:05:46.789487
1642 23:05:46.789553
1643 23:05:46.789616 ==
1644 23:05:46.793262 Dram Type= 6, Freq= 0, CH_1, rank 0
1645 23:05:46.796175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1646 23:05:46.796286 ==
1647 23:05:46.796382
1648 23:05:46.796472
1649 23:05:46.799812 TX Vref Scan disable
1650 23:05:46.802732 == TX Byte 0 ==
1651 23:05:46.806225 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1652 23:05:46.809364 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1653 23:05:46.812993 == TX Byte 1 ==
1654 23:05:46.815961 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1655 23:05:46.819393 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1656 23:05:46.819477 ==
1657 23:05:46.822394 Dram Type= 6, Freq= 0, CH_1, rank 0
1658 23:05:46.829495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1659 23:05:46.829579 ==
1660 23:05:46.840788 TX Vref=22, minBit 1, minWin=27, winSum=442
1661 23:05:46.844210 TX Vref=24, minBit 8, minWin=26, winSum=445
1662 23:05:46.847398 TX Vref=26, minBit 0, minWin=27, winSum=448
1663 23:05:46.851021 TX Vref=28, minBit 13, minWin=27, winSum=452
1664 23:05:46.854232 TX Vref=30, minBit 10, minWin=27, winSum=446
1665 23:05:46.860702 TX Vref=32, minBit 8, minWin=27, winSum=447
1666 23:05:46.863937 [TxChooseVref] Worse bit 13, Min win 27, Win sum 452, Final Vref 28
1667 23:05:46.864021
1668 23:05:46.867398 Final TX Range 1 Vref 28
1669 23:05:46.867482
1670 23:05:46.867548 ==
1671 23:05:46.870507 Dram Type= 6, Freq= 0, CH_1, rank 0
1672 23:05:46.873984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1673 23:05:46.877053 ==
1674 23:05:46.877136
1675 23:05:46.877202
1676 23:05:46.877265 TX Vref Scan disable
1677 23:05:46.881114 == TX Byte 0 ==
1678 23:05:46.885042 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1679 23:05:46.891020 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1680 23:05:46.891104 == TX Byte 1 ==
1681 23:05:46.894384 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1682 23:05:46.898094 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1683 23:05:46.901113
1684 23:05:46.901195 [DATLAT]
1685 23:05:46.901261 Freq=800, CH1 RK0
1686 23:05:46.901323
1687 23:05:46.904338 DATLAT Default: 0xa
1688 23:05:46.904421 0, 0xFFFF, sum = 0
1689 23:05:46.907777 1, 0xFFFF, sum = 0
1690 23:05:46.907860 2, 0xFFFF, sum = 0
1691 23:05:46.911079 3, 0xFFFF, sum = 0
1692 23:05:46.914217 4, 0xFFFF, sum = 0
1693 23:05:46.914301 5, 0xFFFF, sum = 0
1694 23:05:46.917523 6, 0xFFFF, sum = 0
1695 23:05:46.917606 7, 0xFFFF, sum = 0
1696 23:05:46.921181 8, 0xFFFF, sum = 0
1697 23:05:46.921264 9, 0x0, sum = 1
1698 23:05:46.921332 10, 0x0, sum = 2
1699 23:05:46.924295 11, 0x0, sum = 3
1700 23:05:46.924379 12, 0x0, sum = 4
1701 23:05:46.927876 best_step = 10
1702 23:05:46.927957
1703 23:05:46.928023 ==
1704 23:05:46.930752 Dram Type= 6, Freq= 0, CH_1, rank 0
1705 23:05:46.934171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1706 23:05:46.934253 ==
1707 23:05:46.937653 RX Vref Scan: 1
1708 23:05:46.937735
1709 23:05:46.937801 Set Vref Range= 32 -> 127
1710 23:05:46.940792
1711 23:05:46.940873 RX Vref 32 -> 127, step: 1
1712 23:05:46.940939
1713 23:05:46.944056 RX Delay -95 -> 252, step: 8
1714 23:05:46.944138
1715 23:05:46.947612 Set Vref, RX VrefLevel [Byte0]: 32
1716 23:05:46.951068 [Byte1]: 32
1717 23:05:46.951150
1718 23:05:46.954168 Set Vref, RX VrefLevel [Byte0]: 33
1719 23:05:46.957589 [Byte1]: 33
1720 23:05:46.961608
1721 23:05:46.961690 Set Vref, RX VrefLevel [Byte0]: 34
1722 23:05:46.964519 [Byte1]: 34
1723 23:05:46.969201
1724 23:05:46.969283 Set Vref, RX VrefLevel [Byte0]: 35
1725 23:05:46.972479 [Byte1]: 35
1726 23:05:46.976715
1727 23:05:46.976797 Set Vref, RX VrefLevel [Byte0]: 36
1728 23:05:46.980011 [Byte1]: 36
1729 23:05:46.983973
1730 23:05:46.984055 Set Vref, RX VrefLevel [Byte0]: 37
1731 23:05:46.987533 [Byte1]: 37
1732 23:05:46.991818
1733 23:05:46.991901 Set Vref, RX VrefLevel [Byte0]: 38
1734 23:05:46.995140 [Byte1]: 38
1735 23:05:46.999339
1736 23:05:46.999421 Set Vref, RX VrefLevel [Byte0]: 39
1737 23:05:47.002805 [Byte1]: 39
1738 23:05:47.007099
1739 23:05:47.007182 Set Vref, RX VrefLevel [Byte0]: 40
1740 23:05:47.010189 [Byte1]: 40
1741 23:05:47.014406
1742 23:05:47.014489 Set Vref, RX VrefLevel [Byte0]: 41
1743 23:05:47.018000 [Byte1]: 41
1744 23:05:47.022167
1745 23:05:47.022250 Set Vref, RX VrefLevel [Byte0]: 42
1746 23:05:47.028848 [Byte1]: 42
1747 23:05:47.028956
1748 23:05:47.031668 Set Vref, RX VrefLevel [Byte0]: 43
1749 23:05:47.035001 [Byte1]: 43
1750 23:05:47.035084
1751 23:05:47.038878 Set Vref, RX VrefLevel [Byte0]: 44
1752 23:05:47.042396 [Byte1]: 44
1753 23:05:47.042479
1754 23:05:47.045051 Set Vref, RX VrefLevel [Byte0]: 45
1755 23:05:47.048382 [Byte1]: 45
1756 23:05:47.052374
1757 23:05:47.052457 Set Vref, RX VrefLevel [Byte0]: 46
1758 23:05:47.055786 [Byte1]: 46
1759 23:05:47.060013
1760 23:05:47.060095 Set Vref, RX VrefLevel [Byte0]: 47
1761 23:05:47.063641 [Byte1]: 47
1762 23:05:47.067572
1763 23:05:47.067654 Set Vref, RX VrefLevel [Byte0]: 48
1764 23:05:47.070862 [Byte1]: 48
1765 23:05:47.075566
1766 23:05:47.075649 Set Vref, RX VrefLevel [Byte0]: 49
1767 23:05:47.078590 [Byte1]: 49
1768 23:05:47.082715
1769 23:05:47.082798 Set Vref, RX VrefLevel [Byte0]: 50
1770 23:05:47.086321 [Byte1]: 50
1771 23:05:47.090903
1772 23:05:47.090985 Set Vref, RX VrefLevel [Byte0]: 51
1773 23:05:47.093603 [Byte1]: 51
1774 23:05:47.097953
1775 23:05:47.098036 Set Vref, RX VrefLevel [Byte0]: 52
1776 23:05:47.101317 [Byte1]: 52
1777 23:05:47.105541
1778 23:05:47.105625 Set Vref, RX VrefLevel [Byte0]: 53
1779 23:05:47.108827 [Byte1]: 53
1780 23:05:47.113784
1781 23:05:47.113871 Set Vref, RX VrefLevel [Byte0]: 54
1782 23:05:47.116510 [Byte1]: 54
1783 23:05:47.120755
1784 23:05:47.120839 Set Vref, RX VrefLevel [Byte0]: 55
1785 23:05:47.127154 [Byte1]: 55
1786 23:05:47.127237
1787 23:05:47.131093 Set Vref, RX VrefLevel [Byte0]: 56
1788 23:05:47.133880 [Byte1]: 56
1789 23:05:47.133963
1790 23:05:47.137663 Set Vref, RX VrefLevel [Byte0]: 57
1791 23:05:47.140666 [Byte1]: 57
1792 23:05:47.140750
1793 23:05:47.144505 Set Vref, RX VrefLevel [Byte0]: 58
1794 23:05:47.147257 [Byte1]: 58
1795 23:05:47.151549
1796 23:05:47.151631 Set Vref, RX VrefLevel [Byte0]: 59
1797 23:05:47.154367 [Byte1]: 59
1798 23:05:47.158640
1799 23:05:47.158722 Set Vref, RX VrefLevel [Byte0]: 60
1800 23:05:47.162426 [Byte1]: 60
1801 23:05:47.166456
1802 23:05:47.166539 Set Vref, RX VrefLevel [Byte0]: 61
1803 23:05:47.170161 [Byte1]: 61
1804 23:05:47.174683
1805 23:05:47.174765 Set Vref, RX VrefLevel [Byte0]: 62
1806 23:05:47.177334 [Byte1]: 62
1807 23:05:47.181402
1808 23:05:47.181493 Set Vref, RX VrefLevel [Byte0]: 63
1809 23:05:47.185273 [Byte1]: 63
1810 23:05:47.189464
1811 23:05:47.189547 Set Vref, RX VrefLevel [Byte0]: 64
1812 23:05:47.192586 [Byte1]: 64
1813 23:05:47.197107
1814 23:05:47.197214 Set Vref, RX VrefLevel [Byte0]: 65
1815 23:05:47.199963 [Byte1]: 65
1816 23:05:47.204454
1817 23:05:47.204541 Set Vref, RX VrefLevel [Byte0]: 66
1818 23:05:47.208058 [Byte1]: 66
1819 23:05:47.211846
1820 23:05:47.211930 Set Vref, RX VrefLevel [Byte0]: 67
1821 23:05:47.215697 [Byte1]: 67
1822 23:05:47.219582
1823 23:05:47.219665 Set Vref, RX VrefLevel [Byte0]: 68
1824 23:05:47.226251 [Byte1]: 68
1825 23:05:47.226334
1826 23:05:47.229161 Set Vref, RX VrefLevel [Byte0]: 69
1827 23:05:47.232472 [Byte1]: 69
1828 23:05:47.232586
1829 23:05:47.235992 Set Vref, RX VrefLevel [Byte0]: 70
1830 23:05:47.239562 [Byte1]: 70
1831 23:05:47.239645
1832 23:05:47.242592 Set Vref, RX VrefLevel [Byte0]: 71
1833 23:05:47.245909 [Byte1]: 71
1834 23:05:47.250309
1835 23:05:47.250392 Set Vref, RX VrefLevel [Byte0]: 72
1836 23:05:47.253346 [Byte1]: 72
1837 23:05:47.257796
1838 23:05:47.257879 Set Vref, RX VrefLevel [Byte0]: 73
1839 23:05:47.261323 [Byte1]: 73
1840 23:05:47.266388
1841 23:05:47.266470 Set Vref, RX VrefLevel [Byte0]: 74
1842 23:05:47.268661 [Byte1]: 74
1843 23:05:47.272714
1844 23:05:47.272797 Set Vref, RX VrefLevel [Byte0]: 75
1845 23:05:47.276103 [Byte1]: 75
1846 23:05:47.280916
1847 23:05:47.280998 Set Vref, RX VrefLevel [Byte0]: 76
1848 23:05:47.283674 [Byte1]: 76
1849 23:05:47.287978
1850 23:05:47.288061 Set Vref, RX VrefLevel [Byte0]: 77
1851 23:05:47.291466 [Byte1]: 77
1852 23:05:47.296166
1853 23:05:47.296250 Final RX Vref Byte 0 = 55 to rank0
1854 23:05:47.299389 Final RX Vref Byte 1 = 66 to rank0
1855 23:05:47.302985 Final RX Vref Byte 0 = 55 to rank1
1856 23:05:47.305309 Final RX Vref Byte 1 = 66 to rank1==
1857 23:05:47.309142 Dram Type= 6, Freq= 0, CH_1, rank 0
1858 23:05:47.315715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1859 23:05:47.315800 ==
1860 23:05:47.315868 DQS Delay:
1861 23:05:47.315930 DQS0 = 0, DQS1 = 0
1862 23:05:47.318786 DQM Delay:
1863 23:05:47.318879 DQM0 = 86, DQM1 = 78
1864 23:05:47.322029 DQ Delay:
1865 23:05:47.325098 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1866 23:05:47.329066 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =80
1867 23:05:47.331990 DQ8 =68, DQ9 =68, DQ10 =84, DQ11 =68
1868 23:05:47.335383 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
1869 23:05:47.335467
1870 23:05:47.335533
1871 23:05:47.342271 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e1a, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 398 ps
1872 23:05:47.345190 CH1 RK0: MR19=606, MR18=2E1A
1873 23:05:47.351768 CH1_RK0: MR19=0x606, MR18=0x2E1A, DQSOSC=398, MR23=63, INC=93, DEC=62
1874 23:05:47.351853
1875 23:05:47.355142 ----->DramcWriteLeveling(PI) begin...
1876 23:05:47.355255 ==
1877 23:05:47.358280 Dram Type= 6, Freq= 0, CH_1, rank 1
1878 23:05:47.361435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1879 23:05:47.361534 ==
1880 23:05:47.365319 Write leveling (Byte 0): 26 => 26
1881 23:05:47.368473 Write leveling (Byte 1): 28 => 28
1882 23:05:47.371609 DramcWriteLeveling(PI) end<-----
1883 23:05:47.371692
1884 23:05:47.371759 ==
1885 23:05:47.375535 Dram Type= 6, Freq= 0, CH_1, rank 1
1886 23:05:47.378780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1887 23:05:47.378863 ==
1888 23:05:47.381800 [Gating] SW mode calibration
1889 23:05:47.388234 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1890 23:05:47.394829 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1891 23:05:47.397824 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1892 23:05:47.405028 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1893 23:05:47.408206 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1894 23:05:47.411449 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 23:05:47.418259 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 23:05:47.421306 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 23:05:47.424441 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 23:05:47.431547 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 23:05:47.434653 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 23:05:47.437768 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 23:05:47.444825 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 23:05:47.447946 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 23:05:47.451442 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 23:05:47.454974 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 23:05:47.461291 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 23:05:47.464374 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 23:05:47.468268 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1908 23:05:47.474626 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1909 23:05:47.477569 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 23:05:47.481136 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1911 23:05:47.487712 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1912 23:05:47.491090 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1913 23:05:47.494049 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1914 23:05:47.500677 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1915 23:05:47.504509 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1916 23:05:47.507571 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1917 23:05:47.513851 0 9 8 | B1->B0 | 3131 2727 | 1 1 | (1 1) (1 1)
1918 23:05:47.517723 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1919 23:05:47.520738 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1920 23:05:47.527721 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1921 23:05:47.530925 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1922 23:05:47.533871 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1923 23:05:47.540456 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1924 23:05:47.543822 0 10 4 | B1->B0 | 3030 3333 | 0 0 | (1 0) (0 1)
1925 23:05:47.547254 0 10 8 | B1->B0 | 2626 2828 | 0 0 | (1 1) (1 1)
1926 23:05:47.553734 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1927 23:05:47.557345 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1928 23:05:47.559938 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1929 23:05:47.567416 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1930 23:05:47.570095 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1931 23:05:47.573134 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1932 23:05:47.579923 0 11 4 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)
1933 23:05:47.583231 0 11 8 | B1->B0 | 4141 3838 | 0 0 | (0 0) (1 1)
1934 23:05:47.586557 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1935 23:05:47.594020 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1936 23:05:47.596889 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1937 23:05:47.600381 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1938 23:05:47.606953 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1939 23:05:47.610340 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1940 23:05:47.613960 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1941 23:05:47.619894 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1942 23:05:47.623075 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1943 23:05:47.626521 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1944 23:05:47.633331 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1945 23:05:47.636391 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1946 23:05:47.640061 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1947 23:05:47.646672 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1948 23:05:47.649822 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1949 23:05:47.653054 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1950 23:05:47.659501 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1951 23:05:47.662683 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1952 23:05:47.666100 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1953 23:05:47.672782 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1954 23:05:47.676148 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1955 23:05:47.679811 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1956 23:05:47.685965 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1957 23:05:47.689278 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1958 23:05:47.693264 Total UI for P1: 0, mck2ui 16
1959 23:05:47.696762 best dqsien dly found for B0: ( 0, 14, 6)
1960 23:05:47.699658 Total UI for P1: 0, mck2ui 16
1961 23:05:47.702665 best dqsien dly found for B1: ( 0, 14, 6)
1962 23:05:47.706391 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1963 23:05:47.709810 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1964 23:05:47.709893
1965 23:05:47.712346 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1966 23:05:47.716163 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1967 23:05:47.718868 [Gating] SW calibration Done
1968 23:05:47.718959 ==
1969 23:05:47.722280 Dram Type= 6, Freq= 0, CH_1, rank 1
1970 23:05:47.725616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1971 23:05:47.725701 ==
1972 23:05:47.728846 RX Vref Scan: 0
1973 23:05:47.728929
1974 23:05:47.732436 RX Vref 0 -> 0, step: 1
1975 23:05:47.732519
1976 23:05:47.735851 RX Delay -130 -> 252, step: 16
1977 23:05:47.738951 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1978 23:05:47.742233 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1979 23:05:47.745541 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1980 23:05:47.748839 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1981 23:05:47.755669 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1982 23:05:47.759032 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1983 23:05:47.762311 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1984 23:05:47.765344 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1985 23:05:47.768669 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1986 23:05:47.775132 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1987 23:05:47.778594 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1988 23:05:47.782116 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1989 23:05:47.784967 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1990 23:05:47.791396 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1991 23:05:47.795060 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1992 23:05:47.798523 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1993 23:05:47.798606 ==
1994 23:05:47.801302 Dram Type= 6, Freq= 0, CH_1, rank 1
1995 23:05:47.804477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1996 23:05:47.804562 ==
1997 23:05:47.808206 DQS Delay:
1998 23:05:47.808290 DQS0 = 0, DQS1 = 0
1999 23:05:47.811652 DQM Delay:
2000 23:05:47.811735 DQM0 = 86, DQM1 = 78
2001 23:05:47.811802 DQ Delay:
2002 23:05:47.815008 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
2003 23:05:47.818065 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
2004 23:05:47.821766 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
2005 23:05:47.825014 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
2006 23:05:47.825098
2007 23:05:47.825164
2008 23:05:47.827976 ==
2009 23:05:47.831215 Dram Type= 6, Freq= 0, CH_1, rank 1
2010 23:05:47.834397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2011 23:05:47.834481 ==
2012 23:05:47.834547
2013 23:05:47.834610
2014 23:05:47.837824 TX Vref Scan disable
2015 23:05:47.837908 == TX Byte 0 ==
2016 23:05:47.844245 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2017 23:05:47.847630 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2018 23:05:47.847714 == TX Byte 1 ==
2019 23:05:47.854310 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2020 23:05:47.857493 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2021 23:05:47.857576 ==
2022 23:05:47.861038 Dram Type= 6, Freq= 0, CH_1, rank 1
2023 23:05:47.864630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2024 23:05:47.864714 ==
2025 23:05:47.878043 TX Vref=22, minBit 1, minWin=27, winSum=445
2026 23:05:47.881762 TX Vref=24, minBit 8, minWin=27, winSum=449
2027 23:05:47.884465 TX Vref=26, minBit 1, minWin=27, winSum=449
2028 23:05:47.887959 TX Vref=28, minBit 13, minWin=27, winSum=451
2029 23:05:47.892306 TX Vref=30, minBit 8, minWin=27, winSum=450
2030 23:05:47.897674 TX Vref=32, minBit 8, minWin=27, winSum=449
2031 23:05:47.901010 [TxChooseVref] Worse bit 13, Min win 27, Win sum 451, Final Vref 28
2032 23:05:47.901120
2033 23:05:47.904776 Final TX Range 1 Vref 28
2034 23:05:47.904888
2035 23:05:47.904990 ==
2036 23:05:47.907791 Dram Type= 6, Freq= 0, CH_1, rank 1
2037 23:05:47.911589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2038 23:05:47.914226 ==
2039 23:05:47.914309
2040 23:05:47.914375
2041 23:05:47.914437 TX Vref Scan disable
2042 23:05:47.918265 == TX Byte 0 ==
2043 23:05:47.921227 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2044 23:05:47.928136 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2045 23:05:47.928220 == TX Byte 1 ==
2046 23:05:47.931482 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2047 23:05:47.937934 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2048 23:05:47.938018
2049 23:05:47.938085 [DATLAT]
2050 23:05:47.938147 Freq=800, CH1 RK1
2051 23:05:47.938208
2052 23:05:47.941289 DATLAT Default: 0xa
2053 23:05:47.941372 0, 0xFFFF, sum = 0
2054 23:05:47.944703 1, 0xFFFF, sum = 0
2055 23:05:47.944787 2, 0xFFFF, sum = 0
2056 23:05:47.948115 3, 0xFFFF, sum = 0
2057 23:05:47.951023 4, 0xFFFF, sum = 0
2058 23:05:47.951132 5, 0xFFFF, sum = 0
2059 23:05:47.954469 6, 0xFFFF, sum = 0
2060 23:05:47.954553 7, 0xFFFF, sum = 0
2061 23:05:47.958034 8, 0xFFFF, sum = 0
2062 23:05:47.958119 9, 0x0, sum = 1
2063 23:05:47.961119 10, 0x0, sum = 2
2064 23:05:47.961204 11, 0x0, sum = 3
2065 23:05:47.961272 12, 0x0, sum = 4
2066 23:05:47.964666 best_step = 10
2067 23:05:47.964748
2068 23:05:47.964815 ==
2069 23:05:47.967835 Dram Type= 6, Freq= 0, CH_1, rank 1
2070 23:05:47.970990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2071 23:05:47.971074 ==
2072 23:05:47.974151 RX Vref Scan: 0
2073 23:05:47.974234
2074 23:05:47.977940 RX Vref 0 -> 0, step: 1
2075 23:05:47.978023
2076 23:05:47.978090 RX Delay -95 -> 252, step: 8
2077 23:05:47.984836 iDelay=217, Bit 0, Center 92 (-23 ~ 208) 232
2078 23:05:47.988412 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2079 23:05:47.991506 iDelay=217, Bit 2, Center 80 (-31 ~ 192) 224
2080 23:05:47.994754 iDelay=217, Bit 3, Center 84 (-23 ~ 192) 216
2081 23:05:47.997844 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2082 23:05:48.004620 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2083 23:05:48.008106 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2084 23:05:48.011288 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2085 23:05:48.014862 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2086 23:05:48.017760 iDelay=217, Bit 9, Center 72 (-39 ~ 184) 224
2087 23:05:48.024590 iDelay=217, Bit 10, Center 80 (-39 ~ 200) 240
2088 23:05:48.028314 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
2089 23:05:48.031079 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
2090 23:05:48.034761 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2091 23:05:48.040901 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2092 23:05:48.044741 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2093 23:05:48.044825 ==
2094 23:05:48.047763 Dram Type= 6, Freq= 0, CH_1, rank 1
2095 23:05:48.051380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2096 23:05:48.051465 ==
2097 23:05:48.054388 DQS Delay:
2098 23:05:48.054471 DQS0 = 0, DQS1 = 0
2099 23:05:48.054538 DQM Delay:
2100 23:05:48.057855 DQM0 = 87, DQM1 = 78
2101 23:05:48.057939 DQ Delay:
2102 23:05:48.060756 DQ0 =92, DQ1 =80, DQ2 =80, DQ3 =84
2103 23:05:48.064413 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2104 23:05:48.067353 DQ8 =68, DQ9 =72, DQ10 =80, DQ11 =68
2105 23:05:48.071265 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
2106 23:05:48.071349
2107 23:05:48.071415
2108 23:05:48.080623 [DQSOSCAuto] RK1, (LSB)MR18= 0x180f, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 403 ps
2109 23:05:48.080708 CH1 RK1: MR19=606, MR18=180F
2110 23:05:48.087717 CH1_RK1: MR19=0x606, MR18=0x180F, DQSOSC=403, MR23=63, INC=90, DEC=60
2111 23:05:48.090632 [RxdqsGatingPostProcess] freq 800
2112 23:05:48.097678 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2113 23:05:48.100950 Pre-setting of DQS Precalculation
2114 23:05:48.104131 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2115 23:05:48.110789 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2116 23:05:48.120980 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2117 23:05:48.121122
2118 23:05:48.121204
2119 23:05:48.124441 [Calibration Summary] 1600 Mbps
2120 23:05:48.124524 CH 0, Rank 0
2121 23:05:48.127547 SW Impedance : PASS
2122 23:05:48.127631 DUTY Scan : NO K
2123 23:05:48.130691 ZQ Calibration : PASS
2124 23:05:48.133759 Jitter Meter : NO K
2125 23:05:48.133863 CBT Training : PASS
2126 23:05:48.137397 Write leveling : PASS
2127 23:05:48.137520 RX DQS gating : PASS
2128 23:05:48.140517 RX DQ/DQS(RDDQC) : PASS
2129 23:05:48.144028 TX DQ/DQS : PASS
2130 23:05:48.144112 RX DATLAT : PASS
2131 23:05:48.147360 RX DQ/DQS(Engine): PASS
2132 23:05:48.150680 TX OE : NO K
2133 23:05:48.150764 All Pass.
2134 23:05:48.150831
2135 23:05:48.150893 CH 0, Rank 1
2136 23:05:48.153824 SW Impedance : PASS
2137 23:05:48.157608 DUTY Scan : NO K
2138 23:05:48.157692 ZQ Calibration : PASS
2139 23:05:48.160294 Jitter Meter : NO K
2140 23:05:48.163671 CBT Training : PASS
2141 23:05:48.163754 Write leveling : PASS
2142 23:05:48.167358 RX DQS gating : PASS
2143 23:05:48.170324 RX DQ/DQS(RDDQC) : PASS
2144 23:05:48.170407 TX DQ/DQS : PASS
2145 23:05:48.174083 RX DATLAT : PASS
2146 23:05:48.176876 RX DQ/DQS(Engine): PASS
2147 23:05:48.176958 TX OE : NO K
2148 23:05:48.180477 All Pass.
2149 23:05:48.180560
2150 23:05:48.180627 CH 1, Rank 0
2151 23:05:48.183570 SW Impedance : PASS
2152 23:05:48.183654 DUTY Scan : NO K
2153 23:05:48.187126 ZQ Calibration : PASS
2154 23:05:48.190335 Jitter Meter : NO K
2155 23:05:48.190423 CBT Training : PASS
2156 23:05:48.193879 Write leveling : PASS
2157 23:05:48.197053 RX DQS gating : PASS
2158 23:05:48.197137 RX DQ/DQS(RDDQC) : PASS
2159 23:05:48.200016 TX DQ/DQS : PASS
2160 23:05:48.200100 RX DATLAT : PASS
2161 23:05:48.203551 RX DQ/DQS(Engine): PASS
2162 23:05:48.207138 TX OE : NO K
2163 23:05:48.207223 All Pass.
2164 23:05:48.207289
2165 23:05:48.207351 CH 1, Rank 1
2166 23:05:48.210204 SW Impedance : PASS
2167 23:05:48.213257 DUTY Scan : NO K
2168 23:05:48.213363 ZQ Calibration : PASS
2169 23:05:48.216650 Jitter Meter : NO K
2170 23:05:48.220595 CBT Training : PASS
2171 23:05:48.220678 Write leveling : PASS
2172 23:05:48.223197 RX DQS gating : PASS
2173 23:05:48.226711 RX DQ/DQS(RDDQC) : PASS
2174 23:05:48.226822 TX DQ/DQS : PASS
2175 23:05:48.229815 RX DATLAT : PASS
2176 23:05:48.233660 RX DQ/DQS(Engine): PASS
2177 23:05:48.233743 TX OE : NO K
2178 23:05:48.236645 All Pass.
2179 23:05:48.236728
2180 23:05:48.236794 DramC Write-DBI off
2181 23:05:48.239791 PER_BANK_REFRESH: Hybrid Mode
2182 23:05:48.239897 TX_TRACKING: ON
2183 23:05:48.243260 [GetDramInforAfterCalByMRR] Vendor 6.
2184 23:05:48.250050 [GetDramInforAfterCalByMRR] Revision 606.
2185 23:05:48.252994 [GetDramInforAfterCalByMRR] Revision 2 0.
2186 23:05:48.253080 MR0 0x3b3b
2187 23:05:48.253167 MR8 0x5151
2188 23:05:48.256391 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2189 23:05:48.256476
2190 23:05:48.260101 MR0 0x3b3b
2191 23:05:48.260186 MR8 0x5151
2192 23:05:48.263595 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2193 23:05:48.263680
2194 23:05:48.273153 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2195 23:05:48.276493 [FAST_K] Save calibration result to emmc
2196 23:05:48.279785 [FAST_K] Save calibration result to emmc
2197 23:05:48.283054 dram_init: config_dvfs: 1
2198 23:05:48.286889 dramc_set_vcore_voltage set vcore to 662500
2199 23:05:48.289543 Read voltage for 1200, 2
2200 23:05:48.289643 Vio18 = 0
2201 23:05:48.289718 Vcore = 662500
2202 23:05:48.293198 Vdram = 0
2203 23:05:48.293291 Vddq = 0
2204 23:05:48.293388 Vmddr = 0
2205 23:05:48.299970 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2206 23:05:48.303255 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2207 23:05:48.306069 MEM_TYPE=3, freq_sel=15
2208 23:05:48.309454 sv_algorithm_assistance_LP4_1600
2209 23:05:48.312740 ============ PULL DRAM RESETB DOWN ============
2210 23:05:48.316436 ========== PULL DRAM RESETB DOWN end =========
2211 23:05:48.322729 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2212 23:05:48.326075 ===================================
2213 23:05:48.326159 LPDDR4 DRAM CONFIGURATION
2214 23:05:48.329604 ===================================
2215 23:05:48.333162 EX_ROW_EN[0] = 0x0
2216 23:05:48.336032 EX_ROW_EN[1] = 0x0
2217 23:05:48.336115 LP4Y_EN = 0x0
2218 23:05:48.339232 WORK_FSP = 0x0
2219 23:05:48.339315 WL = 0x4
2220 23:05:48.342682 RL = 0x4
2221 23:05:48.342765 BL = 0x2
2222 23:05:48.346076 RPST = 0x0
2223 23:05:48.346160 RD_PRE = 0x0
2224 23:05:48.349142 WR_PRE = 0x1
2225 23:05:48.349227 WR_PST = 0x0
2226 23:05:48.352667 DBI_WR = 0x0
2227 23:05:48.352750 DBI_RD = 0x0
2228 23:05:48.356214 OTF = 0x1
2229 23:05:48.359331 ===================================
2230 23:05:48.363039 ===================================
2231 23:05:48.363123 ANA top config
2232 23:05:48.365825 ===================================
2233 23:05:48.368999 DLL_ASYNC_EN = 0
2234 23:05:48.372734 ALL_SLAVE_EN = 0
2235 23:05:48.375836 NEW_RANK_MODE = 1
2236 23:05:48.375921 DLL_IDLE_MODE = 1
2237 23:05:48.379291 LP45_APHY_COMB_EN = 1
2238 23:05:48.382546 TX_ODT_DIS = 1
2239 23:05:48.385664 NEW_8X_MODE = 1
2240 23:05:48.389081 ===================================
2241 23:05:48.392344 ===================================
2242 23:05:48.396051 data_rate = 2400
2243 23:05:48.399006 CKR = 1
2244 23:05:48.399089 DQ_P2S_RATIO = 8
2245 23:05:48.402171 ===================================
2246 23:05:48.405764 CA_P2S_RATIO = 8
2247 23:05:48.408843 DQ_CA_OPEN = 0
2248 23:05:48.412123 DQ_SEMI_OPEN = 0
2249 23:05:48.415604 CA_SEMI_OPEN = 0
2250 23:05:48.415688 CA_FULL_RATE = 0
2251 23:05:48.419301 DQ_CKDIV4_EN = 0
2252 23:05:48.422182 CA_CKDIV4_EN = 0
2253 23:05:48.425381 CA_PREDIV_EN = 0
2254 23:05:48.428642 PH8_DLY = 17
2255 23:05:48.432193 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2256 23:05:48.435201 DQ_AAMCK_DIV = 4
2257 23:05:48.435284 CA_AAMCK_DIV = 4
2258 23:05:48.438832 CA_ADMCK_DIV = 4
2259 23:05:48.442258 DQ_TRACK_CA_EN = 0
2260 23:05:48.445386 CA_PICK = 1200
2261 23:05:48.448642 CA_MCKIO = 1200
2262 23:05:48.452032 MCKIO_SEMI = 0
2263 23:05:48.455348 PLL_FREQ = 2366
2264 23:05:48.455432 DQ_UI_PI_RATIO = 32
2265 23:05:48.458496 CA_UI_PI_RATIO = 0
2266 23:05:48.462165 ===================================
2267 23:05:48.465263 ===================================
2268 23:05:48.468425 memory_type:LPDDR4
2269 23:05:48.471952 GP_NUM : 10
2270 23:05:48.472036 SRAM_EN : 1
2271 23:05:48.475397 MD32_EN : 0
2272 23:05:48.478415 ===================================
2273 23:05:48.482193 [ANA_INIT] >>>>>>>>>>>>>>
2274 23:05:48.482277 <<<<<< [CONFIGURE PHASE]: ANA_TX
2275 23:05:48.485057 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2276 23:05:48.488301 ===================================
2277 23:05:48.491624 data_rate = 2400,PCW = 0X5b00
2278 23:05:48.495163 ===================================
2279 23:05:48.498842 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2280 23:05:48.505332 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2281 23:05:48.511533 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2282 23:05:48.514557 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2283 23:05:48.518277 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2284 23:05:48.521337 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2285 23:05:48.524654 [ANA_INIT] flow start
2286 23:05:48.524739 [ANA_INIT] PLL >>>>>>>>
2287 23:05:48.528117 [ANA_INIT] PLL <<<<<<<<
2288 23:05:48.531615 [ANA_INIT] MIDPI >>>>>>>>
2289 23:05:48.535207 [ANA_INIT] MIDPI <<<<<<<<
2290 23:05:48.535287 [ANA_INIT] DLL >>>>>>>>
2291 23:05:48.537970 [ANA_INIT] DLL <<<<<<<<
2292 23:05:48.538056 [ANA_INIT] flow end
2293 23:05:48.544416 ============ LP4 DIFF to SE enter ============
2294 23:05:48.547938 ============ LP4 DIFF to SE exit ============
2295 23:05:48.551084 [ANA_INIT] <<<<<<<<<<<<<
2296 23:05:48.554414 [Flow] Enable top DCM control >>>>>
2297 23:05:48.557622 [Flow] Enable top DCM control <<<<<
2298 23:05:48.561415 Enable DLL master slave shuffle
2299 23:05:48.564600 ==============================================================
2300 23:05:48.567720 Gating Mode config
2301 23:05:48.571099 ==============================================================
2302 23:05:48.574820 Config description:
2303 23:05:48.584194 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2304 23:05:48.591205 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2305 23:05:48.594425 SELPH_MODE 0: By rank 1: By Phase
2306 23:05:48.601000 ==============================================================
2307 23:05:48.604234 GAT_TRACK_EN = 1
2308 23:05:48.607506 RX_GATING_MODE = 2
2309 23:05:48.611048 RX_GATING_TRACK_MODE = 2
2310 23:05:48.614423 SELPH_MODE = 1
2311 23:05:48.617731 PICG_EARLY_EN = 1
2312 23:05:48.617816 VALID_LAT_VALUE = 1
2313 23:05:48.624132 ==============================================================
2314 23:05:48.627244 Enter into Gating configuration >>>>
2315 23:05:48.630497 Exit from Gating configuration <<<<
2316 23:05:48.634149 Enter into DVFS_PRE_config >>>>>
2317 23:05:48.644126 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2318 23:05:48.647431 Exit from DVFS_PRE_config <<<<<
2319 23:05:48.650757 Enter into PICG configuration >>>>
2320 23:05:48.653650 Exit from PICG configuration <<<<
2321 23:05:48.657310 [RX_INPUT] configuration >>>>>
2322 23:05:48.660594 [RX_INPUT] configuration <<<<<
2323 23:05:48.666937 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2324 23:05:48.670602 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2325 23:05:48.676918 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2326 23:05:48.683486 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2327 23:05:48.690137 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2328 23:05:48.696580 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2329 23:05:48.700593 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2330 23:05:48.703510 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2331 23:05:48.706691 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2332 23:05:48.713339 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2333 23:05:48.716687 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2334 23:05:48.719976 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2335 23:05:48.723533 ===================================
2336 23:05:48.726616 LPDDR4 DRAM CONFIGURATION
2337 23:05:48.729892 ===================================
2338 23:05:48.729975 EX_ROW_EN[0] = 0x0
2339 23:05:48.733526 EX_ROW_EN[1] = 0x0
2340 23:05:48.736489 LP4Y_EN = 0x0
2341 23:05:48.736572 WORK_FSP = 0x0
2342 23:05:48.739952 WL = 0x4
2343 23:05:48.740035 RL = 0x4
2344 23:05:48.742934 BL = 0x2
2345 23:05:48.743017 RPST = 0x0
2346 23:05:48.746496 RD_PRE = 0x0
2347 23:05:48.746579 WR_PRE = 0x1
2348 23:05:48.749491 WR_PST = 0x0
2349 23:05:48.749600 DBI_WR = 0x0
2350 23:05:48.752976 DBI_RD = 0x0
2351 23:05:48.753075 OTF = 0x1
2352 23:05:48.756238 ===================================
2353 23:05:48.759978 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2354 23:05:48.766687 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2355 23:05:48.770375 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2356 23:05:48.773195 ===================================
2357 23:05:48.776540 LPDDR4 DRAM CONFIGURATION
2358 23:05:48.779483 ===================================
2359 23:05:48.779566 EX_ROW_EN[0] = 0x10
2360 23:05:48.783074 EX_ROW_EN[1] = 0x0
2361 23:05:48.786553 LP4Y_EN = 0x0
2362 23:05:48.786637 WORK_FSP = 0x0
2363 23:05:48.789934 WL = 0x4
2364 23:05:48.790017 RL = 0x4
2365 23:05:48.792918 BL = 0x2
2366 23:05:48.793000 RPST = 0x0
2367 23:05:48.795944 RD_PRE = 0x0
2368 23:05:48.796050 WR_PRE = 0x1
2369 23:05:48.799209 WR_PST = 0x0
2370 23:05:48.799292 DBI_WR = 0x0
2371 23:05:48.802758 DBI_RD = 0x0
2372 23:05:48.802841 OTF = 0x1
2373 23:05:48.805977 ===================================
2374 23:05:48.812308 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2375 23:05:48.812403 ==
2376 23:05:48.816163 Dram Type= 6, Freq= 0, CH_0, rank 0
2377 23:05:48.819648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2378 23:05:48.822427 ==
2379 23:05:48.822509 [Duty_Offset_Calibration]
2380 23:05:48.825732 B0:1 B1:-1 CA:0
2381 23:05:48.825815
2382 23:05:48.829115 [DutyScan_Calibration_Flow] k_type=0
2383 23:05:48.837787
2384 23:05:48.837869 ==CLK 0==
2385 23:05:48.841014 Final CLK duty delay cell = 0
2386 23:05:48.844450 [0] MAX Duty = 5125%(X100), DQS PI = 24
2387 23:05:48.847398 [0] MIN Duty = 4875%(X100), DQS PI = 8
2388 23:05:48.847494 [0] AVG Duty = 5000%(X100)
2389 23:05:48.850832
2390 23:05:48.854298 CH0 CLK Duty spec in!! Max-Min= 250%
2391 23:05:48.857851 [DutyScan_Calibration_Flow] ====Done====
2392 23:05:48.857934
2393 23:05:48.860778 [DutyScan_Calibration_Flow] k_type=1
2394 23:05:48.875449
2395 23:05:48.875531 ==DQS 0 ==
2396 23:05:48.879196 Final DQS duty delay cell = -4
2397 23:05:48.882461 [-4] MAX Duty = 5062%(X100), DQS PI = 18
2398 23:05:48.885218 [-4] MIN Duty = 4875%(X100), DQS PI = 8
2399 23:05:48.888433 [-4] AVG Duty = 4968%(X100)
2400 23:05:48.888513
2401 23:05:48.888579 ==DQS 1 ==
2402 23:05:48.892013 Final DQS duty delay cell = -4
2403 23:05:48.895156 [-4] MAX Duty = 5000%(X100), DQS PI = 6
2404 23:05:48.898638 [-4] MIN Duty = 4876%(X100), DQS PI = 22
2405 23:05:48.902416 [-4] AVG Duty = 4938%(X100)
2406 23:05:48.902499
2407 23:05:48.905219 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2408 23:05:48.905302
2409 23:05:48.909034 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2410 23:05:48.911931 [DutyScan_Calibration_Flow] ====Done====
2411 23:05:48.912014
2412 23:05:48.915089 [DutyScan_Calibration_Flow] k_type=3
2413 23:05:48.933186
2414 23:05:48.933269 ==DQM 0 ==
2415 23:05:48.936721 Final DQM duty delay cell = 0
2416 23:05:48.940030 [0] MAX Duty = 5031%(X100), DQS PI = 16
2417 23:05:48.943205 [0] MIN Duty = 4875%(X100), DQS PI = 6
2418 23:05:48.946891 [0] AVG Duty = 4953%(X100)
2419 23:05:48.946975
2420 23:05:48.947042 ==DQM 1 ==
2421 23:05:48.949862 Final DQM duty delay cell = 4
2422 23:05:48.952892 [4] MAX Duty = 5187%(X100), DQS PI = 16
2423 23:05:48.956330 [4] MIN Duty = 5000%(X100), DQS PI = 24
2424 23:05:48.959648 [4] AVG Duty = 5093%(X100)
2425 23:05:48.959736
2426 23:05:48.963187 CH0 DQM 0 Duty spec in!! Max-Min= 156%
2427 23:05:48.963271
2428 23:05:48.966819 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2429 23:05:48.969366 [DutyScan_Calibration_Flow] ====Done====
2430 23:05:48.969489
2431 23:05:48.973540 [DutyScan_Calibration_Flow] k_type=2
2432 23:05:48.988362
2433 23:05:48.988445 ==DQ 0 ==
2434 23:05:48.991811 Final DQ duty delay cell = -4
2435 23:05:48.995191 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2436 23:05:48.998129 [-4] MIN Duty = 4875%(X100), DQS PI = 54
2437 23:05:49.001365 [-4] AVG Duty = 4953%(X100)
2438 23:05:49.001500
2439 23:05:49.001568 ==DQ 1 ==
2440 23:05:49.004681 Final DQ duty delay cell = -4
2441 23:05:49.008371 [-4] MAX Duty = 5000%(X100), DQS PI = 54
2442 23:05:49.011125 [-4] MIN Duty = 4876%(X100), DQS PI = 40
2443 23:05:49.014883 [-4] AVG Duty = 4938%(X100)
2444 23:05:49.014967
2445 23:05:49.018149 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2446 23:05:49.018232
2447 23:05:49.021203 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2448 23:05:49.024605 [DutyScan_Calibration_Flow] ====Done====
2449 23:05:49.024689 ==
2450 23:05:49.027797 Dram Type= 6, Freq= 0, CH_1, rank 0
2451 23:05:49.031366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2452 23:05:49.031450 ==
2453 23:05:49.034285 [Duty_Offset_Calibration]
2454 23:05:49.034369 B0:-1 B1:1 CA:1
2455 23:05:49.037777
2456 23:05:49.041158 [DutyScan_Calibration_Flow] k_type=0
2457 23:05:49.048718
2458 23:05:49.048801 ==CLK 0==
2459 23:05:49.052505 Final CLK duty delay cell = 0
2460 23:05:49.055920 [0] MAX Duty = 5156%(X100), DQS PI = 22
2461 23:05:49.059029 [0] MIN Duty = 4969%(X100), DQS PI = 60
2462 23:05:49.059113 [0] AVG Duty = 5062%(X100)
2463 23:05:49.062177
2464 23:05:49.065415 CH1 CLK Duty spec in!! Max-Min= 187%
2465 23:05:49.069403 [DutyScan_Calibration_Flow] ====Done====
2466 23:05:49.069524
2467 23:05:49.072235 [DutyScan_Calibration_Flow] k_type=1
2468 23:05:49.088530
2469 23:05:49.088614 ==DQS 0 ==
2470 23:05:49.092083 Final DQS duty delay cell = 0
2471 23:05:49.094884 [0] MAX Duty = 5156%(X100), DQS PI = 50
2472 23:05:49.098092 [0] MIN Duty = 4907%(X100), DQS PI = 8
2473 23:05:49.098176 [0] AVG Duty = 5031%(X100)
2474 23:05:49.101354
2475 23:05:49.101460 ==DQS 1 ==
2476 23:05:49.104611 Final DQS duty delay cell = 0
2477 23:05:49.108238 [0] MAX Duty = 5094%(X100), DQS PI = 12
2478 23:05:49.111741 [0] MIN Duty = 4969%(X100), DQS PI = 58
2479 23:05:49.114707 [0] AVG Duty = 5031%(X100)
2480 23:05:49.114816
2481 23:05:49.117703 CH1 DQS 0 Duty spec in!! Max-Min= 249%
2482 23:05:49.117787
2483 23:05:49.121307 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2484 23:05:49.124653 [DutyScan_Calibration_Flow] ====Done====
2485 23:05:49.124736
2486 23:05:49.127962 [DutyScan_Calibration_Flow] k_type=3
2487 23:05:49.143784
2488 23:05:49.143899 ==DQM 0 ==
2489 23:05:49.147170 Final DQM duty delay cell = -4
2490 23:05:49.150542 [-4] MAX Duty = 5031%(X100), DQS PI = 16
2491 23:05:49.154086 [-4] MIN Duty = 4876%(X100), DQS PI = 8
2492 23:05:49.157391 [-4] AVG Duty = 4953%(X100)
2493 23:05:49.157495
2494 23:05:49.157563 ==DQM 1 ==
2495 23:05:49.160251 Final DQM duty delay cell = 0
2496 23:05:49.163712 [0] MAX Duty = 5187%(X100), DQS PI = 6
2497 23:05:49.167385 [0] MIN Duty = 5000%(X100), DQS PI = 28
2498 23:05:49.170485 [0] AVG Duty = 5093%(X100)
2499 23:05:49.170568
2500 23:05:49.173683 CH1 DQM 0 Duty spec in!! Max-Min= 155%
2501 23:05:49.173767
2502 23:05:49.176729 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2503 23:05:49.180169 [DutyScan_Calibration_Flow] ====Done====
2504 23:05:49.180253
2505 23:05:49.183434 [DutyScan_Calibration_Flow] k_type=2
2506 23:05:49.200342
2507 23:05:49.200424 ==DQ 0 ==
2508 23:05:49.204304 Final DQ duty delay cell = 0
2509 23:05:49.207392 [0] MAX Duty = 5156%(X100), DQS PI = 28
2510 23:05:49.210506 [0] MIN Duty = 4907%(X100), DQS PI = 6
2511 23:05:49.210590 [0] AVG Duty = 5031%(X100)
2512 23:05:49.210679
2513 23:05:49.213971 ==DQ 1 ==
2514 23:05:49.216998 Final DQ duty delay cell = 0
2515 23:05:49.220343 [0] MAX Duty = 5093%(X100), DQS PI = 8
2516 23:05:49.223793 [0] MIN Duty = 4969%(X100), DQS PI = 0
2517 23:05:49.223898 [0] AVG Duty = 5031%(X100)
2518 23:05:49.223994
2519 23:05:49.227033 CH1 DQ 0 Duty spec in!! Max-Min= 249%
2520 23:05:49.227147
2521 23:05:49.230698 CH1 DQ 1 Duty spec in!! Max-Min= 124%
2522 23:05:49.237138 [DutyScan_Calibration_Flow] ====Done====
2523 23:05:49.240485 nWR fixed to 30
2524 23:05:49.240642 [ModeRegInit_LP4] CH0 RK0
2525 23:05:49.243791 [ModeRegInit_LP4] CH0 RK1
2526 23:05:49.246889 [ModeRegInit_LP4] CH1 RK0
2527 23:05:49.246965 [ModeRegInit_LP4] CH1 RK1
2528 23:05:49.250650 match AC timing 7
2529 23:05:49.253267 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2530 23:05:49.260294 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2531 23:05:49.263791 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2532 23:05:49.267152 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2533 23:05:49.273372 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2534 23:05:49.273513 ==
2535 23:05:49.276549 Dram Type= 6, Freq= 0, CH_0, rank 0
2536 23:05:49.279980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2537 23:05:49.280078 ==
2538 23:05:49.286937 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2539 23:05:49.293377 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2540 23:05:49.300236 [CA 0] Center 39 (9~70) winsize 62
2541 23:05:49.303858 [CA 1] Center 39 (9~70) winsize 62
2542 23:05:49.307150 [CA 2] Center 35 (5~66) winsize 62
2543 23:05:49.310297 [CA 3] Center 35 (5~65) winsize 61
2544 23:05:49.313947 [CA 4] Center 33 (3~64) winsize 62
2545 23:05:49.317226 [CA 5] Center 33 (4~63) winsize 60
2546 23:05:49.317326
2547 23:05:49.320403 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2548 23:05:49.320509
2549 23:05:49.323428 [CATrainingPosCal] consider 1 rank data
2550 23:05:49.326587 u2DelayCellTimex100 = 270/100 ps
2551 23:05:49.330349 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2552 23:05:49.333640 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2553 23:05:49.340120 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2554 23:05:49.343500 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2555 23:05:49.347053 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2556 23:05:49.350243 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2557 23:05:49.350342
2558 23:05:49.353654 CA PerBit enable=1, Macro0, CA PI delay=33
2559 23:05:49.353763
2560 23:05:49.356830 [CBTSetCACLKResult] CA Dly = 33
2561 23:05:49.356933 CS Dly: 8 (0~39)
2562 23:05:49.360854 ==
2563 23:05:49.360959 Dram Type= 6, Freq= 0, CH_0, rank 1
2564 23:05:49.367091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2565 23:05:49.367191 ==
2566 23:05:49.369827 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2567 23:05:49.376664 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2568 23:05:49.385925 [CA 0] Center 39 (8~70) winsize 63
2569 23:05:49.389400 [CA 1] Center 39 (9~70) winsize 62
2570 23:05:49.392719 [CA 2] Center 35 (5~66) winsize 62
2571 23:05:49.395673 [CA 3] Center 34 (4~65) winsize 62
2572 23:05:49.399618 [CA 4] Center 33 (3~64) winsize 62
2573 23:05:49.402812 [CA 5] Center 33 (3~63) winsize 61
2574 23:05:49.402896
2575 23:05:49.405717 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2576 23:05:49.405801
2577 23:05:49.409346 [CATrainingPosCal] consider 2 rank data
2578 23:05:49.413096 u2DelayCellTimex100 = 270/100 ps
2579 23:05:49.416038 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2580 23:05:49.422299 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2581 23:05:49.425807 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2582 23:05:49.428820 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2583 23:05:49.432406 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2584 23:05:49.435660 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2585 23:05:49.435744
2586 23:05:49.438930 CA PerBit enable=1, Macro0, CA PI delay=33
2587 23:05:49.439014
2588 23:05:49.442274 [CBTSetCACLKResult] CA Dly = 33
2589 23:05:49.442355 CS Dly: 9 (0~41)
2590 23:05:49.445674
2591 23:05:49.448757 ----->DramcWriteLeveling(PI) begin...
2592 23:05:49.448843 ==
2593 23:05:49.452348 Dram Type= 6, Freq= 0, CH_0, rank 0
2594 23:05:49.455937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2595 23:05:49.456022 ==
2596 23:05:49.458805 Write leveling (Byte 0): 31 => 31
2597 23:05:49.461937 Write leveling (Byte 1): 29 => 29
2598 23:05:49.465351 DramcWriteLeveling(PI) end<-----
2599 23:05:49.465490
2600 23:05:49.465558 ==
2601 23:05:49.468718 Dram Type= 6, Freq= 0, CH_0, rank 0
2602 23:05:49.471996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2603 23:05:49.472080 ==
2604 23:05:49.475108 [Gating] SW mode calibration
2605 23:05:49.482232 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2606 23:05:49.488733 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2607 23:05:49.491682 0 15 0 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
2608 23:05:49.495244 0 15 4 | B1->B0 | 2727 3434 | 1 1 | (0 0) (1 1)
2609 23:05:49.502140 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2610 23:05:49.505110 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2611 23:05:49.508487 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2612 23:05:49.515143 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2613 23:05:49.518439 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2614 23:05:49.521852 0 15 28 | B1->B0 | 3434 2c2c | 1 1 | (1 1) (1 0)
2615 23:05:49.528185 1 0 0 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
2616 23:05:49.531424 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2617 23:05:49.534697 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2618 23:05:49.541738 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2619 23:05:49.544652 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2620 23:05:49.548001 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2621 23:05:49.554559 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2622 23:05:49.558201 1 0 28 | B1->B0 | 2323 3332 | 0 1 | (0 0) (0 0)
2623 23:05:49.561725 1 1 0 | B1->B0 | 2525 4444 | 0 0 | (0 0) (0 0)
2624 23:05:49.568225 1 1 4 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
2625 23:05:49.572047 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2626 23:05:49.574660 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2627 23:05:49.581227 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2628 23:05:49.584890 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2629 23:05:49.587826 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2630 23:05:49.594495 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2631 23:05:49.598041 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2632 23:05:49.601339 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2633 23:05:49.604607 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2634 23:05:49.611245 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2635 23:05:49.614581 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2636 23:05:49.617969 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2637 23:05:49.624240 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2638 23:05:49.627884 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2639 23:05:49.631408 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2640 23:05:49.637804 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2641 23:05:49.641270 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2642 23:05:49.644858 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2643 23:05:49.651101 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2644 23:05:49.654469 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2645 23:05:49.657512 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2646 23:05:49.664615 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2647 23:05:49.667781 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2648 23:05:49.671017 Total UI for P1: 0, mck2ui 16
2649 23:05:49.673883 best dqsien dly found for B0: ( 1, 3, 26)
2650 23:05:49.677398 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2651 23:05:49.684387 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2652 23:05:49.684471 Total UI for P1: 0, mck2ui 16
2653 23:05:49.690542 best dqsien dly found for B1: ( 1, 4, 0)
2654 23:05:49.693823 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2655 23:05:49.697552 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2656 23:05:49.697636
2657 23:05:49.700651 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2658 23:05:49.704434 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2659 23:05:49.707264 [Gating] SW calibration Done
2660 23:05:49.707376 ==
2661 23:05:49.711146 Dram Type= 6, Freq= 0, CH_0, rank 0
2662 23:05:49.713854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2663 23:05:49.713960 ==
2664 23:05:49.717080 RX Vref Scan: 0
2665 23:05:49.717180
2666 23:05:49.717283 RX Vref 0 -> 0, step: 1
2667 23:05:49.717374
2668 23:05:49.720769 RX Delay -40 -> 252, step: 8
2669 23:05:49.723721 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2670 23:05:49.730287 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2671 23:05:49.733750 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2672 23:05:49.736994 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2673 23:05:49.741337 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2674 23:05:49.743902 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2675 23:05:49.750391 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2676 23:05:49.753325 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2677 23:05:49.757153 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2678 23:05:49.760444 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2679 23:05:49.763287 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2680 23:05:49.770314 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2681 23:05:49.773464 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2682 23:05:49.777147 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2683 23:05:49.780255 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2684 23:05:49.783491 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2685 23:05:49.786972 ==
2686 23:05:49.790447 Dram Type= 6, Freq= 0, CH_0, rank 0
2687 23:05:49.793512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2688 23:05:49.793595 ==
2689 23:05:49.793663 DQS Delay:
2690 23:05:49.796689 DQS0 = 0, DQS1 = 0
2691 23:05:49.796772 DQM Delay:
2692 23:05:49.799948 DQM0 = 119, DQM1 = 106
2693 23:05:49.800031 DQ Delay:
2694 23:05:49.803447 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2695 23:05:49.806692 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =127
2696 23:05:49.809942 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2697 23:05:49.813592 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2698 23:05:49.813700
2699 23:05:49.813799
2700 23:05:49.813891 ==
2701 23:05:49.816526 Dram Type= 6, Freq= 0, CH_0, rank 0
2702 23:05:49.823581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2703 23:05:49.823695 ==
2704 23:05:49.823790
2705 23:05:49.823880
2706 23:05:49.823968 TX Vref Scan disable
2707 23:05:49.826958 == TX Byte 0 ==
2708 23:05:49.829973 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2709 23:05:49.837526 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2710 23:05:49.837631 == TX Byte 1 ==
2711 23:05:49.840091 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2712 23:05:49.846759 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2713 23:05:49.846862 ==
2714 23:05:49.850201 Dram Type= 6, Freq= 0, CH_0, rank 0
2715 23:05:49.853231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2716 23:05:49.853334 ==
2717 23:05:49.864542 TX Vref=22, minBit 1, minWin=25, winSum=413
2718 23:05:49.868384 TX Vref=24, minBit 0, minWin=26, winSum=421
2719 23:05:49.871524 TX Vref=26, minBit 1, minWin=25, winSum=425
2720 23:05:49.874797 TX Vref=28, minBit 1, minWin=25, winSum=429
2721 23:05:49.878064 TX Vref=30, minBit 5, minWin=26, winSum=432
2722 23:05:49.884394 TX Vref=32, minBit 4, minWin=26, winSum=432
2723 23:05:49.887788 [TxChooseVref] Worse bit 5, Min win 26, Win sum 432, Final Vref 30
2724 23:05:49.887873
2725 23:05:49.891418 Final TX Range 1 Vref 30
2726 23:05:49.891529
2727 23:05:49.891624 ==
2728 23:05:49.894519 Dram Type= 6, Freq= 0, CH_0, rank 0
2729 23:05:49.897765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2730 23:05:49.897869 ==
2731 23:05:49.901240
2732 23:05:49.901373
2733 23:05:49.901478 TX Vref Scan disable
2734 23:05:49.904200 == TX Byte 0 ==
2735 23:05:49.907940 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2736 23:05:49.910935 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2737 23:05:49.914508 == TX Byte 1 ==
2738 23:05:49.918132 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2739 23:05:49.921389 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2740 23:05:49.924647
2741 23:05:49.924729 [DATLAT]
2742 23:05:49.924796 Freq=1200, CH0 RK0
2743 23:05:49.924859
2744 23:05:49.928012 DATLAT Default: 0xd
2745 23:05:49.928095 0, 0xFFFF, sum = 0
2746 23:05:49.931046 1, 0xFFFF, sum = 0
2747 23:05:49.931131 2, 0xFFFF, sum = 0
2748 23:05:49.934197 3, 0xFFFF, sum = 0
2749 23:05:49.937607 4, 0xFFFF, sum = 0
2750 23:05:49.937691 5, 0xFFFF, sum = 0
2751 23:05:49.941318 6, 0xFFFF, sum = 0
2752 23:05:49.941404 7, 0xFFFF, sum = 0
2753 23:05:49.944198 8, 0xFFFF, sum = 0
2754 23:05:49.944283 9, 0xFFFF, sum = 0
2755 23:05:49.947584 10, 0xFFFF, sum = 0
2756 23:05:49.947669 11, 0xFFFF, sum = 0
2757 23:05:49.951150 12, 0x0, sum = 1
2758 23:05:49.951234 13, 0x0, sum = 2
2759 23:05:49.954263 14, 0x0, sum = 3
2760 23:05:49.954347 15, 0x0, sum = 4
2761 23:05:49.954415 best_step = 13
2762 23:05:49.957772
2763 23:05:49.957855 ==
2764 23:05:49.960790 Dram Type= 6, Freq= 0, CH_0, rank 0
2765 23:05:49.964217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2766 23:05:49.964301 ==
2767 23:05:49.964368 RX Vref Scan: 1
2768 23:05:49.964432
2769 23:05:49.967859 Set Vref Range= 32 -> 127
2770 23:05:49.967942
2771 23:05:49.970993 RX Vref 32 -> 127, step: 1
2772 23:05:49.971076
2773 23:05:49.974005 RX Delay -21 -> 252, step: 4
2774 23:05:49.974114
2775 23:05:49.978563 Set Vref, RX VrefLevel [Byte0]: 32
2776 23:05:49.981333 [Byte1]: 32
2777 23:05:49.981487
2778 23:05:49.984019 Set Vref, RX VrefLevel [Byte0]: 33
2779 23:05:49.987580 [Byte1]: 33
2780 23:05:49.990888
2781 23:05:49.990993 Set Vref, RX VrefLevel [Byte0]: 34
2782 23:05:49.994004 [Byte1]: 34
2783 23:05:49.998908
2784 23:05:49.999016 Set Vref, RX VrefLevel [Byte0]: 35
2785 23:05:50.002309 [Byte1]: 35
2786 23:05:50.006852
2787 23:05:50.006975 Set Vref, RX VrefLevel [Byte0]: 36
2788 23:05:50.009789 [Byte1]: 36
2789 23:05:50.014661
2790 23:05:50.014773 Set Vref, RX VrefLevel [Byte0]: 37
2791 23:05:50.018236 [Byte1]: 37
2792 23:05:50.022543
2793 23:05:50.022653 Set Vref, RX VrefLevel [Byte0]: 38
2794 23:05:50.026379 [Byte1]: 38
2795 23:05:50.030263
2796 23:05:50.030362 Set Vref, RX VrefLevel [Byte0]: 39
2797 23:05:50.033995 [Byte1]: 39
2798 23:05:50.038318
2799 23:05:50.038420 Set Vref, RX VrefLevel [Byte0]: 40
2800 23:05:50.041869 [Byte1]: 40
2801 23:05:50.046683
2802 23:05:50.046793 Set Vref, RX VrefLevel [Byte0]: 41
2803 23:05:50.049662 [Byte1]: 41
2804 23:05:50.054600
2805 23:05:50.054702 Set Vref, RX VrefLevel [Byte0]: 42
2806 23:05:50.057959 [Byte1]: 42
2807 23:05:50.062071
2808 23:05:50.062170 Set Vref, RX VrefLevel [Byte0]: 43
2809 23:05:50.065691 [Byte1]: 43
2810 23:05:50.070182
2811 23:05:50.070284 Set Vref, RX VrefLevel [Byte0]: 44
2812 23:05:50.073305 [Byte1]: 44
2813 23:05:50.078371
2814 23:05:50.078477 Set Vref, RX VrefLevel [Byte0]: 45
2815 23:05:50.081317 [Byte1]: 45
2816 23:05:50.085757
2817 23:05:50.085859 Set Vref, RX VrefLevel [Byte0]: 46
2818 23:05:50.089302 [Byte1]: 46
2819 23:05:50.093697
2820 23:05:50.093810 Set Vref, RX VrefLevel [Byte0]: 47
2821 23:05:50.096936 [Byte1]: 47
2822 23:05:50.101557
2823 23:05:50.101659 Set Vref, RX VrefLevel [Byte0]: 48
2824 23:05:50.105320 [Byte1]: 48
2825 23:05:50.109533
2826 23:05:50.109642 Set Vref, RX VrefLevel [Byte0]: 49
2827 23:05:50.112893 [Byte1]: 49
2828 23:05:50.118472
2829 23:05:50.118592 Set Vref, RX VrefLevel [Byte0]: 50
2830 23:05:50.120875 [Byte1]: 50
2831 23:05:50.125293
2832 23:05:50.125377 Set Vref, RX VrefLevel [Byte0]: 51
2833 23:05:50.128928 [Byte1]: 51
2834 23:05:50.133746
2835 23:05:50.133829 Set Vref, RX VrefLevel [Byte0]: 52
2836 23:05:50.137069 [Byte1]: 52
2837 23:05:50.141733
2838 23:05:50.141816 Set Vref, RX VrefLevel [Byte0]: 53
2839 23:05:50.144605 [Byte1]: 53
2840 23:05:50.149729
2841 23:05:50.149828 Set Vref, RX VrefLevel [Byte0]: 54
2842 23:05:50.152970 [Byte1]: 54
2843 23:05:50.157394
2844 23:05:50.157516 Set Vref, RX VrefLevel [Byte0]: 55
2845 23:05:50.160457 [Byte1]: 55
2846 23:05:50.165554
2847 23:05:50.165637 Set Vref, RX VrefLevel [Byte0]: 56
2848 23:05:50.168754 [Byte1]: 56
2849 23:05:50.173126
2850 23:05:50.173209 Set Vref, RX VrefLevel [Byte0]: 57
2851 23:05:50.176225 [Byte1]: 57
2852 23:05:50.180966
2853 23:05:50.181049 Set Vref, RX VrefLevel [Byte0]: 58
2854 23:05:50.184333 [Byte1]: 58
2855 23:05:50.188929
2856 23:05:50.189012 Set Vref, RX VrefLevel [Byte0]: 59
2857 23:05:50.192729 [Byte1]: 59
2858 23:05:50.197626
2859 23:05:50.200472 Set Vref, RX VrefLevel [Byte0]: 60
2860 23:05:50.203396 [Byte1]: 60
2861 23:05:50.203479
2862 23:05:50.206511 Set Vref, RX VrefLevel [Byte0]: 61
2863 23:05:50.209819 [Byte1]: 61
2864 23:05:50.209902
2865 23:05:50.213404 Set Vref, RX VrefLevel [Byte0]: 62
2866 23:05:50.216454 [Byte1]: 62
2867 23:05:50.221137
2868 23:05:50.221246 Set Vref, RX VrefLevel [Byte0]: 63
2869 23:05:50.224131 [Byte1]: 63
2870 23:05:50.228724
2871 23:05:50.228828 Set Vref, RX VrefLevel [Byte0]: 64
2872 23:05:50.231985 [Byte1]: 64
2873 23:05:50.236601
2874 23:05:50.236705 Set Vref, RX VrefLevel [Byte0]: 65
2875 23:05:50.240042 [Byte1]: 65
2876 23:05:50.244715
2877 23:05:50.244819 Set Vref, RX VrefLevel [Byte0]: 66
2878 23:05:50.247930 [Byte1]: 66
2879 23:05:50.252276
2880 23:05:50.252376 Set Vref, RX VrefLevel [Byte0]: 67
2881 23:05:50.255993 [Byte1]: 67
2882 23:05:50.260343
2883 23:05:50.260433 Set Vref, RX VrefLevel [Byte0]: 68
2884 23:05:50.263552 [Byte1]: 68
2885 23:05:50.268522
2886 23:05:50.268605 Set Vref, RX VrefLevel [Byte0]: 69
2887 23:05:50.271688 [Byte1]: 69
2888 23:05:50.276151
2889 23:05:50.276233 Set Vref, RX VrefLevel [Byte0]: 70
2890 23:05:50.279965 [Byte1]: 70
2891 23:05:50.284223
2892 23:05:50.284305 Set Vref, RX VrefLevel [Byte0]: 71
2893 23:05:50.287390 [Byte1]: 71
2894 23:05:50.292364
2895 23:05:50.292446 Set Vref, RX VrefLevel [Byte0]: 72
2896 23:05:50.298308 [Byte1]: 72
2897 23:05:50.298391
2898 23:05:50.301610 Set Vref, RX VrefLevel [Byte0]: 73
2899 23:05:50.305464 [Byte1]: 73
2900 23:05:50.305542
2901 23:05:50.309220 Set Vref, RX VrefLevel [Byte0]: 74
2902 23:05:50.311656 [Byte1]: 74
2903 23:05:50.315873
2904 23:05:50.315979 Set Vref, RX VrefLevel [Byte0]: 75
2905 23:05:50.319520 [Byte1]: 75
2906 23:05:50.324120
2907 23:05:50.324226 Set Vref, RX VrefLevel [Byte0]: 76
2908 23:05:50.327481 [Byte1]: 76
2909 23:05:50.332094
2910 23:05:50.332198 Set Vref, RX VrefLevel [Byte0]: 77
2911 23:05:50.334953 [Byte1]: 77
2912 23:05:50.339607
2913 23:05:50.339716 Final RX Vref Byte 0 = 61 to rank0
2914 23:05:50.343074 Final RX Vref Byte 1 = 49 to rank0
2915 23:05:50.346272 Final RX Vref Byte 0 = 61 to rank1
2916 23:05:50.349816 Final RX Vref Byte 1 = 49 to rank1==
2917 23:05:50.353518 Dram Type= 6, Freq= 0, CH_0, rank 0
2918 23:05:50.357022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2919 23:05:50.359439 ==
2920 23:05:50.359522 DQS Delay:
2921 23:05:50.359590 DQS0 = 0, DQS1 = 0
2922 23:05:50.362743 DQM Delay:
2923 23:05:50.362826 DQM0 = 118, DQM1 = 106
2924 23:05:50.366127 DQ Delay:
2925 23:05:50.369819 DQ0 =116, DQ1 =120, DQ2 =116, DQ3 =114
2926 23:05:50.373060 DQ4 =120, DQ5 =110, DQ6 =126, DQ7 =126
2927 23:05:50.376077 DQ8 =96, DQ9 =92, DQ10 =108, DQ11 =98
2928 23:05:50.379291 DQ12 =112, DQ13 =108, DQ14 =118, DQ15 =116
2929 23:05:50.379374
2930 23:05:50.379441
2931 23:05:50.385966 [DQSOSCAuto] RK0, (LSB)MR18= 0x10fc, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 403 ps
2932 23:05:50.389232 CH0 RK0: MR19=403, MR18=10FC
2933 23:05:50.395895 CH0_RK0: MR19=0x403, MR18=0x10FC, DQSOSC=403, MR23=63, INC=40, DEC=26
2934 23:05:50.395980
2935 23:05:50.399370 ----->DramcWriteLeveling(PI) begin...
2936 23:05:50.399455 ==
2937 23:05:50.403041 Dram Type= 6, Freq= 0, CH_0, rank 1
2938 23:05:50.405799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2939 23:05:50.409771 ==
2940 23:05:50.412426 Write leveling (Byte 0): 32 => 32
2941 23:05:50.412510 Write leveling (Byte 1): 30 => 30
2942 23:05:50.416183 DramcWriteLeveling(PI) end<-----
2943 23:05:50.416301
2944 23:05:50.416368 ==
2945 23:05:50.419180 Dram Type= 6, Freq= 0, CH_0, rank 1
2946 23:05:50.426203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2947 23:05:50.426287 ==
2948 23:05:50.429165 [Gating] SW mode calibration
2949 23:05:50.435782 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2950 23:05:50.439360 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2951 23:05:50.445631 0 15 0 | B1->B0 | 2424 3333 | 1 0 | (1 1) (0 0)
2952 23:05:50.449141 0 15 4 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
2953 23:05:50.452197 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2954 23:05:50.458915 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2955 23:05:50.462352 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2956 23:05:50.465534 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2957 23:05:50.471952 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2958 23:05:50.475172 0 15 28 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
2959 23:05:50.478506 1 0 0 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
2960 23:05:50.485371 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2961 23:05:50.488618 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2962 23:05:50.492263 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2963 23:05:50.498385 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2964 23:05:50.501872 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2965 23:05:50.505368 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2966 23:05:50.511857 1 0 28 | B1->B0 | 2423 3434 | 1 1 | (0 0) (0 0)
2967 23:05:50.515568 1 1 0 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
2968 23:05:50.518731 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2969 23:05:50.522153 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2970 23:05:50.528459 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2971 23:05:50.531865 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2972 23:05:50.535396 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2973 23:05:50.541805 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2974 23:05:50.545311 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2975 23:05:50.548253 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
2976 23:05:50.555169 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2977 23:05:50.558554 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2978 23:05:50.561926 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2979 23:05:50.568356 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2980 23:05:50.571553 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2981 23:05:50.575621 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2982 23:05:50.581460 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2983 23:05:50.585237 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2984 23:05:50.588138 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2985 23:05:50.595039 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2986 23:05:50.598377 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2987 23:05:50.601434 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2988 23:05:50.608503 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2989 23:05:50.611833 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2990 23:05:50.614851 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2991 23:05:50.621473 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2992 23:05:50.621677 Total UI for P1: 0, mck2ui 16
2993 23:05:50.628547 best dqsien dly found for B0: ( 1, 3, 26)
2994 23:05:50.631338 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2995 23:05:50.634957 Total UI for P1: 0, mck2ui 16
2996 23:05:50.638218 best dqsien dly found for B1: ( 1, 3, 30)
2997 23:05:50.641281 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2998 23:05:50.644823 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2999 23:05:50.645063
3000 23:05:50.647984 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3001 23:05:50.651107 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3002 23:05:50.654611 [Gating] SW calibration Done
3003 23:05:50.654699 ==
3004 23:05:50.657907 Dram Type= 6, Freq= 0, CH_0, rank 1
3005 23:05:50.661049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3006 23:05:50.664649 ==
3007 23:05:50.664759 RX Vref Scan: 0
3008 23:05:50.664856
3009 23:05:50.667508 RX Vref 0 -> 0, step: 1
3010 23:05:50.667617
3011 23:05:50.671016 RX Delay -40 -> 252, step: 8
3012 23:05:50.674711 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
3013 23:05:50.677851 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
3014 23:05:50.680923 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
3015 23:05:50.684082 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3016 23:05:50.690645 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3017 23:05:50.693914 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
3018 23:05:50.697690 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3019 23:05:50.700778 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
3020 23:05:50.703964 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3021 23:05:50.707726 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3022 23:05:50.713958 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3023 23:05:50.717628 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3024 23:05:50.720788 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3025 23:05:50.724298 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3026 23:05:50.730719 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3027 23:05:50.734331 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3028 23:05:50.734415 ==
3029 23:05:50.737584 Dram Type= 6, Freq= 0, CH_0, rank 1
3030 23:05:50.740968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3031 23:05:50.741051 ==
3032 23:05:50.743942 DQS Delay:
3033 23:05:50.744054 DQS0 = 0, DQS1 = 0
3034 23:05:50.744152 DQM Delay:
3035 23:05:50.747199 DQM0 = 116, DQM1 = 108
3036 23:05:50.747302 DQ Delay:
3037 23:05:50.750594 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =115
3038 23:05:50.754044 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
3039 23:05:50.757308 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
3040 23:05:50.763754 DQ12 =111, DQ13 =119, DQ14 =119, DQ15 =111
3041 23:05:50.763845
3042 23:05:50.763916
3043 23:05:50.763977 ==
3044 23:05:50.767016 Dram Type= 6, Freq= 0, CH_0, rank 1
3045 23:05:50.770608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3046 23:05:50.770708 ==
3047 23:05:50.770812
3048 23:05:50.770901
3049 23:05:50.773635 TX Vref Scan disable
3050 23:05:50.773716 == TX Byte 0 ==
3051 23:05:50.780469 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3052 23:05:50.783445 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3053 23:05:50.783519 == TX Byte 1 ==
3054 23:05:50.790408 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3055 23:05:50.793806 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3056 23:05:50.793906 ==
3057 23:05:50.796883 Dram Type= 6, Freq= 0, CH_0, rank 1
3058 23:05:50.800585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3059 23:05:50.800660 ==
3060 23:05:50.813491 TX Vref=22, minBit 5, minWin=25, winSum=418
3061 23:05:50.816257 TX Vref=24, minBit 5, minWin=25, winSum=422
3062 23:05:50.819728 TX Vref=26, minBit 2, minWin=26, winSum=429
3063 23:05:50.823132 TX Vref=28, minBit 10, minWin=26, winSum=432
3064 23:05:50.826524 TX Vref=30, minBit 4, minWin=26, winSum=432
3065 23:05:50.833359 TX Vref=32, minBit 10, minWin=26, winSum=430
3066 23:05:50.836493 [TxChooseVref] Worse bit 10, Min win 26, Win sum 432, Final Vref 28
3067 23:05:50.836597
3068 23:05:50.839866 Final TX Range 1 Vref 28
3069 23:05:50.839956
3070 23:05:50.840019 ==
3071 23:05:50.842854 Dram Type= 6, Freq= 0, CH_0, rank 1
3072 23:05:50.847052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3073 23:05:50.849607 ==
3074 23:05:50.849688
3075 23:05:50.849754
3076 23:05:50.849814 TX Vref Scan disable
3077 23:05:50.853365 == TX Byte 0 ==
3078 23:05:50.856489 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3079 23:05:50.863178 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3080 23:05:50.863260 == TX Byte 1 ==
3081 23:05:50.866677 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3082 23:05:50.873329 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3083 23:05:50.873440
3084 23:05:50.873507 [DATLAT]
3085 23:05:50.873569 Freq=1200, CH0 RK1
3086 23:05:50.873628
3087 23:05:50.876291 DATLAT Default: 0xd
3088 23:05:50.879489 0, 0xFFFF, sum = 0
3089 23:05:50.879573 1, 0xFFFF, sum = 0
3090 23:05:50.882943 2, 0xFFFF, sum = 0
3091 23:05:50.883026 3, 0xFFFF, sum = 0
3092 23:05:50.885949 4, 0xFFFF, sum = 0
3093 23:05:50.886032 5, 0xFFFF, sum = 0
3094 23:05:50.889816 6, 0xFFFF, sum = 0
3095 23:05:50.889899 7, 0xFFFF, sum = 0
3096 23:05:50.893054 8, 0xFFFF, sum = 0
3097 23:05:50.893137 9, 0xFFFF, sum = 0
3098 23:05:50.896123 10, 0xFFFF, sum = 0
3099 23:05:50.896206 11, 0xFFFF, sum = 0
3100 23:05:50.899262 12, 0x0, sum = 1
3101 23:05:50.899345 13, 0x0, sum = 2
3102 23:05:50.902875 14, 0x0, sum = 3
3103 23:05:50.902958 15, 0x0, sum = 4
3104 23:05:50.906011 best_step = 13
3105 23:05:50.906093
3106 23:05:50.906159 ==
3107 23:05:50.909189 Dram Type= 6, Freq= 0, CH_0, rank 1
3108 23:05:50.912423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3109 23:05:50.912506 ==
3110 23:05:50.912572 RX Vref Scan: 0
3111 23:05:50.916027
3112 23:05:50.916109 RX Vref 0 -> 0, step: 1
3113 23:05:50.916174
3114 23:05:50.919125 RX Delay -21 -> 252, step: 4
3115 23:05:50.925806 iDelay=199, Bit 0, Center 114 (47 ~ 182) 136
3116 23:05:50.929531 iDelay=199, Bit 1, Center 118 (47 ~ 190) 144
3117 23:05:50.932828 iDelay=199, Bit 2, Center 110 (43 ~ 178) 136
3118 23:05:50.936268 iDelay=199, Bit 3, Center 114 (43 ~ 186) 144
3119 23:05:50.939270 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3120 23:05:50.942707 iDelay=199, Bit 5, Center 110 (43 ~ 178) 136
3121 23:05:50.950078 iDelay=199, Bit 6, Center 126 (55 ~ 198) 144
3122 23:05:50.953113 iDelay=199, Bit 7, Center 124 (55 ~ 194) 140
3123 23:05:50.956122 iDelay=199, Bit 8, Center 96 (27 ~ 166) 140
3124 23:05:50.959458 iDelay=199, Bit 9, Center 94 (27 ~ 162) 136
3125 23:05:50.962157 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3126 23:05:50.969105 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3127 23:05:50.972287 iDelay=199, Bit 12, Center 112 (47 ~ 178) 132
3128 23:05:50.976063 iDelay=199, Bit 13, Center 114 (47 ~ 182) 136
3129 23:05:50.979063 iDelay=199, Bit 14, Center 118 (55 ~ 182) 128
3130 23:05:50.985534 iDelay=199, Bit 15, Center 116 (51 ~ 182) 132
3131 23:05:50.985642 ==
3132 23:05:50.988930 Dram Type= 6, Freq= 0, CH_0, rank 1
3133 23:05:50.992130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3134 23:05:50.992243 ==
3135 23:05:50.992337 DQS Delay:
3136 23:05:50.995459 DQS0 = 0, DQS1 = 0
3137 23:05:50.995540 DQM Delay:
3138 23:05:50.999248 DQM0 = 116, DQM1 = 107
3139 23:05:50.999356 DQ Delay:
3140 23:05:51.002044 DQ0 =114, DQ1 =118, DQ2 =110, DQ3 =114
3141 23:05:51.005637 DQ4 =116, DQ5 =110, DQ6 =126, DQ7 =124
3142 23:05:51.009194 DQ8 =96, DQ9 =94, DQ10 =110, DQ11 =100
3143 23:05:51.012213 DQ12 =112, DQ13 =114, DQ14 =118, DQ15 =116
3144 23:05:51.012295
3145 23:05:51.012360
3146 23:05:51.022248 [DQSOSCAuto] RK1, (LSB)MR18= 0xde7, (MSB)MR19= 0x403, tDQSOscB0 = 420 ps tDQSOscB1 = 405 ps
3147 23:05:51.025160 CH0 RK1: MR19=403, MR18=DE7
3148 23:05:51.028528 CH0_RK1: MR19=0x403, MR18=0xDE7, DQSOSC=405, MR23=63, INC=39, DEC=26
3149 23:05:51.032055 [RxdqsGatingPostProcess] freq 1200
3150 23:05:51.038485 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3151 23:05:51.042098 best DQS0 dly(2T, 0.5T) = (0, 11)
3152 23:05:51.045263 best DQS1 dly(2T, 0.5T) = (0, 12)
3153 23:05:51.048752 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3154 23:05:51.051960 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3155 23:05:51.055167 best DQS0 dly(2T, 0.5T) = (0, 11)
3156 23:05:51.058531 best DQS1 dly(2T, 0.5T) = (0, 11)
3157 23:05:51.061540 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3158 23:05:51.065167 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3159 23:05:51.070009 Pre-setting of DQS Precalculation
3160 23:05:51.071833 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3161 23:05:51.071934 ==
3162 23:05:51.074625 Dram Type= 6, Freq= 0, CH_1, rank 0
3163 23:05:51.078223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3164 23:05:51.078307 ==
3165 23:05:51.085360 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3166 23:05:51.091789 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3167 23:05:51.099332 [CA 0] Center 37 (7~67) winsize 61
3168 23:05:51.102842 [CA 1] Center 37 (7~68) winsize 62
3169 23:05:51.105701 [CA 2] Center 34 (4~64) winsize 61
3170 23:05:51.109028 [CA 3] Center 33 (3~64) winsize 62
3171 23:05:51.112241 [CA 4] Center 34 (4~64) winsize 61
3172 23:05:51.115934 [CA 5] Center 33 (3~64) winsize 62
3173 23:05:51.116036
3174 23:05:51.119608 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3175 23:05:51.119704
3176 23:05:51.122493 [CATrainingPosCal] consider 1 rank data
3177 23:05:51.125815 u2DelayCellTimex100 = 270/100 ps
3178 23:05:51.128990 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3179 23:05:51.135464 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3180 23:05:51.138994 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3181 23:05:51.142427 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3182 23:05:51.146043 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3183 23:05:51.148918 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3184 23:05:51.149001
3185 23:05:51.152048 CA PerBit enable=1, Macro0, CA PI delay=33
3186 23:05:51.152131
3187 23:05:51.155797 [CBTSetCACLKResult] CA Dly = 33
3188 23:05:51.158630 CS Dly: 5 (0~36)
3189 23:05:51.158713 ==
3190 23:05:51.162003 Dram Type= 6, Freq= 0, CH_1, rank 1
3191 23:05:51.165865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3192 23:05:51.165948 ==
3193 23:05:51.172516 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3194 23:05:51.175342 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3195 23:05:51.185005 [CA 0] Center 37 (7~67) winsize 61
3196 23:05:51.188569 [CA 1] Center 37 (7~68) winsize 62
3197 23:05:51.191371 [CA 2] Center 34 (4~65) winsize 62
3198 23:05:51.194412 [CA 3] Center 33 (3~64) winsize 62
3199 23:05:51.197986 [CA 4] Center 34 (4~64) winsize 61
3200 23:05:51.201329 [CA 5] Center 33 (3~64) winsize 62
3201 23:05:51.201477
3202 23:05:51.204500 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3203 23:05:51.204604
3204 23:05:51.207607 [CATrainingPosCal] consider 2 rank data
3205 23:05:51.211286 u2DelayCellTimex100 = 270/100 ps
3206 23:05:51.214411 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3207 23:05:51.221445 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3208 23:05:51.224246 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3209 23:05:51.227700 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3210 23:05:51.230878 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3211 23:05:51.234751 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3212 23:05:51.234840
3213 23:05:51.237595 CA PerBit enable=1, Macro0, CA PI delay=33
3214 23:05:51.237684
3215 23:05:51.240999 [CBTSetCACLKResult] CA Dly = 33
3216 23:05:51.244399 CS Dly: 7 (0~40)
3217 23:05:51.244493
3218 23:05:51.247880 ----->DramcWriteLeveling(PI) begin...
3219 23:05:51.247984 ==
3220 23:05:51.251116 Dram Type= 6, Freq= 0, CH_1, rank 0
3221 23:05:51.254339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3222 23:05:51.254453 ==
3223 23:05:51.257940 Write leveling (Byte 0): 25 => 25
3224 23:05:51.261115 Write leveling (Byte 1): 26 => 26
3225 23:05:51.264331 DramcWriteLeveling(PI) end<-----
3226 23:05:51.264414
3227 23:05:51.264480 ==
3228 23:05:51.267765 Dram Type= 6, Freq= 0, CH_1, rank 0
3229 23:05:51.271396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3230 23:05:51.271486 ==
3231 23:05:51.274674 [Gating] SW mode calibration
3232 23:05:51.281087 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3233 23:05:51.287234 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3234 23:05:51.290409 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3235 23:05:51.294128 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3236 23:05:51.300301 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3237 23:05:51.304045 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3238 23:05:51.306996 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3239 23:05:51.313532 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3240 23:05:51.316922 0 15 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
3241 23:05:51.320180 0 15 28 | B1->B0 | 2828 2323 | 1 0 | (1 0) (1 0)
3242 23:05:51.326900 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3243 23:05:51.330081 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3244 23:05:51.333207 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3245 23:05:51.339961 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3246 23:05:51.343558 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3247 23:05:51.346865 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3248 23:05:51.353390 1 0 24 | B1->B0 | 2929 4040 | 0 0 | (0 0) (0 0)
3249 23:05:51.356619 1 0 28 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
3250 23:05:51.359744 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3251 23:05:51.366725 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3252 23:05:51.370039 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3253 23:05:51.373686 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3254 23:05:51.380150 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3255 23:05:51.383339 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3256 23:05:51.386649 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3257 23:05:51.393098 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3258 23:05:51.396660 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3259 23:05:51.400134 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3260 23:05:51.406417 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3261 23:05:51.410010 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3262 23:05:51.413137 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3263 23:05:51.420173 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3264 23:05:51.422955 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3265 23:05:51.426465 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3266 23:05:51.429559 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3267 23:05:51.436469 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3268 23:05:51.439538 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3269 23:05:51.443346 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3270 23:05:51.449454 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3271 23:05:51.453032 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3272 23:05:51.456391 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3273 23:05:51.463325 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3274 23:05:51.466219 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3275 23:05:51.469351 Total UI for P1: 0, mck2ui 16
3276 23:05:51.473286 best dqsien dly found for B0: ( 1, 3, 26)
3277 23:05:51.476507 Total UI for P1: 0, mck2ui 16
3278 23:05:51.479538 best dqsien dly found for B1: ( 1, 3, 28)
3279 23:05:51.482653 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3280 23:05:51.486268 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3281 23:05:51.486366
3282 23:05:51.489065 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3283 23:05:51.495747 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3284 23:05:51.495831 [Gating] SW calibration Done
3285 23:05:51.495898 ==
3286 23:05:51.499568 Dram Type= 6, Freq= 0, CH_1, rank 0
3287 23:05:51.506029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3288 23:05:51.506130 ==
3289 23:05:51.506197 RX Vref Scan: 0
3290 23:05:51.506257
3291 23:05:51.509247 RX Vref 0 -> 0, step: 1
3292 23:05:51.509346
3293 23:05:51.512625 RX Delay -40 -> 252, step: 8
3294 23:05:51.516323 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3295 23:05:51.519196 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3296 23:05:51.522354 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
3297 23:05:51.529175 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3298 23:05:51.532199 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3299 23:05:51.535765 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3300 23:05:51.538927 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3301 23:05:51.542137 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3302 23:05:51.549093 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3303 23:05:51.551861 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3304 23:05:51.555389 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3305 23:05:51.558879 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
3306 23:05:51.562174 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3307 23:05:51.568664 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3308 23:05:51.571935 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3309 23:05:51.575294 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3310 23:05:51.575376 ==
3311 23:05:51.578537 Dram Type= 6, Freq= 0, CH_1, rank 0
3312 23:05:51.582182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3313 23:05:51.582273 ==
3314 23:05:51.586468 DQS Delay:
3315 23:05:51.586905 DQS0 = 0, DQS1 = 0
3316 23:05:51.588928 DQM Delay:
3317 23:05:51.589610 DQM0 = 117, DQM1 = 108
3318 23:05:51.592153 DQ Delay:
3319 23:05:51.595709 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =115
3320 23:05:51.598786 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =115
3321 23:05:51.602598 DQ8 =95, DQ9 =103, DQ10 =111, DQ11 =95
3322 23:05:51.605264 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =119
3323 23:05:51.605969
3324 23:05:51.606431
3325 23:05:51.606752 ==
3326 23:05:51.608971 Dram Type= 6, Freq= 0, CH_1, rank 0
3327 23:05:51.612030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3328 23:05:51.612756 ==
3329 23:05:51.613382
3330 23:05:51.613934
3331 23:05:51.615602 TX Vref Scan disable
3332 23:05:51.618632 == TX Byte 0 ==
3333 23:05:51.621915 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3334 23:05:51.625850 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3335 23:05:51.629385 == TX Byte 1 ==
3336 23:05:51.632824 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3337 23:05:51.635689 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3338 23:05:51.635919 ==
3339 23:05:51.638851 Dram Type= 6, Freq= 0, CH_1, rank 0
3340 23:05:51.642095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3341 23:05:51.645002 ==
3342 23:05:51.655092 TX Vref=22, minBit 10, minWin=24, winSum=416
3343 23:05:51.658515 TX Vref=24, minBit 9, minWin=25, winSum=417
3344 23:05:51.661705 TX Vref=26, minBit 10, minWin=25, winSum=428
3345 23:05:51.664754 TX Vref=28, minBit 10, minWin=25, winSum=434
3346 23:05:51.668051 TX Vref=30, minBit 9, minWin=26, winSum=434
3347 23:05:51.674727 TX Vref=32, minBit 9, minWin=25, winSum=423
3348 23:05:51.678320 [TxChooseVref] Worse bit 9, Min win 26, Win sum 434, Final Vref 30
3349 23:05:51.678407
3350 23:05:51.681227 Final TX Range 1 Vref 30
3351 23:05:51.681315
3352 23:05:51.681384 ==
3353 23:05:51.684476 Dram Type= 6, Freq= 0, CH_1, rank 0
3354 23:05:51.687895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3355 23:05:51.691173 ==
3356 23:05:51.691258
3357 23:05:51.691325
3358 23:05:51.691388 TX Vref Scan disable
3359 23:05:51.694514 == TX Byte 0 ==
3360 23:05:51.697897 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3361 23:05:51.701284 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3362 23:05:51.705057 == TX Byte 1 ==
3363 23:05:51.707873 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3364 23:05:51.714758 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3365 23:05:51.714851
3366 23:05:51.714924 [DATLAT]
3367 23:05:51.714991 Freq=1200, CH1 RK0
3368 23:05:51.715057
3369 23:05:51.718279 DATLAT Default: 0xd
3370 23:05:51.718369 0, 0xFFFF, sum = 0
3371 23:05:51.721274 1, 0xFFFF, sum = 0
3372 23:05:51.721373 2, 0xFFFF, sum = 0
3373 23:05:51.724492 3, 0xFFFF, sum = 0
3374 23:05:51.728062 4, 0xFFFF, sum = 0
3375 23:05:51.728169 5, 0xFFFF, sum = 0
3376 23:05:51.731173 6, 0xFFFF, sum = 0
3377 23:05:51.731289 7, 0xFFFF, sum = 0
3378 23:05:51.734458 8, 0xFFFF, sum = 0
3379 23:05:51.734575 9, 0xFFFF, sum = 0
3380 23:05:51.738301 10, 0xFFFF, sum = 0
3381 23:05:51.738428 11, 0xFFFF, sum = 0
3382 23:05:51.741248 12, 0x0, sum = 1
3383 23:05:51.741390 13, 0x0, sum = 2
3384 23:05:51.744543 14, 0x0, sum = 3
3385 23:05:51.744708 15, 0x0, sum = 4
3386 23:05:51.747662 best_step = 13
3387 23:05:51.747820
3388 23:05:51.747947 ==
3389 23:05:51.751025 Dram Type= 6, Freq= 0, CH_1, rank 0
3390 23:05:51.754663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3391 23:05:51.754877 ==
3392 23:05:51.755048 RX Vref Scan: 1
3393 23:05:51.755208
3394 23:05:51.757949 Set Vref Range= 32 -> 127
3395 23:05:51.758163
3396 23:05:51.761154 RX Vref 32 -> 127, step: 1
3397 23:05:51.761426
3398 23:05:51.764441 RX Delay -21 -> 252, step: 4
3399 23:05:51.764730
3400 23:05:51.767859 Set Vref, RX VrefLevel [Byte0]: 32
3401 23:05:51.771172 [Byte1]: 32
3402 23:05:51.771594
3403 23:05:51.774567 Set Vref, RX VrefLevel [Byte0]: 33
3404 23:05:51.777970 [Byte1]: 33
3405 23:05:51.781564
3406 23:05:51.781987 Set Vref, RX VrefLevel [Byte0]: 34
3407 23:05:51.785203 [Byte1]: 34
3408 23:05:51.789538
3409 23:05:51.789957 Set Vref, RX VrefLevel [Byte0]: 35
3410 23:05:51.792546 [Byte1]: 35
3411 23:05:51.797521
3412 23:05:51.797945 Set Vref, RX VrefLevel [Byte0]: 36
3413 23:05:51.800488 [Byte1]: 36
3414 23:05:51.805259
3415 23:05:51.805734 Set Vref, RX VrefLevel [Byte0]: 37
3416 23:05:51.808846 [Byte1]: 37
3417 23:05:51.813289
3418 23:05:51.813761 Set Vref, RX VrefLevel [Byte0]: 38
3419 23:05:51.816683 [Byte1]: 38
3420 23:05:51.820783
3421 23:05:51.821212 Set Vref, RX VrefLevel [Byte0]: 39
3422 23:05:51.824098 [Byte1]: 39
3423 23:05:51.829072
3424 23:05:51.829544 Set Vref, RX VrefLevel [Byte0]: 40
3425 23:05:51.832348 [Byte1]: 40
3426 23:05:51.837362
3427 23:05:51.837826 Set Vref, RX VrefLevel [Byte0]: 41
3428 23:05:51.840395 [Byte1]: 41
3429 23:05:51.844892
3430 23:05:51.845312 Set Vref, RX VrefLevel [Byte0]: 42
3431 23:05:51.851489 [Byte1]: 42
3432 23:05:51.851929
3433 23:05:51.855061 Set Vref, RX VrefLevel [Byte0]: 43
3434 23:05:51.858179 [Byte1]: 43
3435 23:05:51.858600
3436 23:05:51.861160 Set Vref, RX VrefLevel [Byte0]: 44
3437 23:05:51.864720 [Byte1]: 44
3438 23:05:51.868631
3439 23:05:51.869050 Set Vref, RX VrefLevel [Byte0]: 45
3440 23:05:51.871995 [Byte1]: 45
3441 23:05:51.876865
3442 23:05:51.877286 Set Vref, RX VrefLevel [Byte0]: 46
3443 23:05:51.880297 [Byte1]: 46
3444 23:05:51.884463
3445 23:05:51.884882 Set Vref, RX VrefLevel [Byte0]: 47
3446 23:05:51.887894 [Byte1]: 47
3447 23:05:51.892145
3448 23:05:51.892568 Set Vref, RX VrefLevel [Byte0]: 48
3449 23:05:51.895497 [Byte1]: 48
3450 23:05:51.900271
3451 23:05:51.900851 Set Vref, RX VrefLevel [Byte0]: 49
3452 23:05:51.903773 [Byte1]: 49
3453 23:05:51.908333
3454 23:05:51.908876 Set Vref, RX VrefLevel [Byte0]: 50
3455 23:05:51.911413 [Byte1]: 50
3456 23:05:51.916260
3457 23:05:51.916684 Set Vref, RX VrefLevel [Byte0]: 51
3458 23:05:51.919324 [Byte1]: 51
3459 23:05:51.924064
3460 23:05:51.924534 Set Vref, RX VrefLevel [Byte0]: 52
3461 23:05:51.927470 [Byte1]: 52
3462 23:05:51.932056
3463 23:05:51.932527 Set Vref, RX VrefLevel [Byte0]: 53
3464 23:05:51.935318 [Byte1]: 53
3465 23:05:51.939691
3466 23:05:51.940118 Set Vref, RX VrefLevel [Byte0]: 54
3467 23:05:51.943251 [Byte1]: 54
3468 23:05:51.947829
3469 23:05:51.950843 Set Vref, RX VrefLevel [Byte0]: 55
3470 23:05:51.951375 [Byte1]: 55
3471 23:05:51.955661
3472 23:05:51.956088 Set Vref, RX VrefLevel [Byte0]: 56
3473 23:05:51.959233 [Byte1]: 56
3474 23:05:51.963544
3475 23:05:51.963969 Set Vref, RX VrefLevel [Byte0]: 57
3476 23:05:51.967016 [Byte1]: 57
3477 23:05:51.972218
3478 23:05:51.972751 Set Vref, RX VrefLevel [Byte0]: 58
3479 23:05:51.975030 [Byte1]: 58
3480 23:05:51.979906
3481 23:05:51.980430 Set Vref, RX VrefLevel [Byte0]: 59
3482 23:05:51.982881 [Byte1]: 59
3483 23:05:51.988525
3484 23:05:51.989057 Set Vref, RX VrefLevel [Byte0]: 60
3485 23:05:51.990910 [Byte1]: 60
3486 23:05:51.995326
3487 23:05:51.995751 Set Vref, RX VrefLevel [Byte0]: 61
3488 23:05:51.998609 [Byte1]: 61
3489 23:05:52.003886
3490 23:05:52.004310 Set Vref, RX VrefLevel [Byte0]: 62
3491 23:05:52.006511 [Byte1]: 62
3492 23:05:52.011453
3493 23:05:52.011895 Set Vref, RX VrefLevel [Byte0]: 63
3494 23:05:52.014591 [Byte1]: 63
3495 23:05:52.019322
3496 23:05:52.019798 Set Vref, RX VrefLevel [Byte0]: 64
3497 23:05:52.022674 [Byte1]: 64
3498 23:05:52.027111
3499 23:05:52.027538 Set Vref, RX VrefLevel [Byte0]: 65
3500 23:05:52.030434 [Byte1]: 65
3501 23:05:52.035282
3502 23:05:52.035883 Set Vref, RX VrefLevel [Byte0]: 66
3503 23:05:52.038124 [Byte1]: 66
3504 23:05:52.043382
3505 23:05:52.043933 Set Vref, RX VrefLevel [Byte0]: 67
3506 23:05:52.046262 [Byte1]: 67
3507 23:05:52.051366
3508 23:05:52.051819 Set Vref, RX VrefLevel [Byte0]: 68
3509 23:05:52.054095 [Byte1]: 68
3510 23:05:52.058652
3511 23:05:52.059074 Set Vref, RX VrefLevel [Byte0]: 69
3512 23:05:52.062308 [Byte1]: 69
3513 23:05:52.066698
3514 23:05:52.067125 Final RX Vref Byte 0 = 52 to rank0
3515 23:05:52.070262 Final RX Vref Byte 1 = 60 to rank0
3516 23:05:52.073074 Final RX Vref Byte 0 = 52 to rank1
3517 23:05:52.076369 Final RX Vref Byte 1 = 60 to rank1==
3518 23:05:52.080093 Dram Type= 6, Freq= 0, CH_1, rank 0
3519 23:05:52.086787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3520 23:05:52.087217 ==
3521 23:05:52.087562 DQS Delay:
3522 23:05:52.087881 DQS0 = 0, DQS1 = 0
3523 23:05:52.089842 DQM Delay:
3524 23:05:52.090381 DQM0 = 115, DQM1 = 112
3525 23:05:52.093070 DQ Delay:
3526 23:05:52.096529 DQ0 =120, DQ1 =110, DQ2 =110, DQ3 =110
3527 23:05:52.099522 DQ4 =112, DQ5 =128, DQ6 =124, DQ7 =112
3528 23:05:52.103284 DQ8 =100, DQ9 =100, DQ10 =116, DQ11 =100
3529 23:05:52.106599 DQ12 =120, DQ13 =120, DQ14 =124, DQ15 =122
3530 23:05:52.107022
3531 23:05:52.107359
3532 23:05:52.117040 [DQSOSCAuto] RK0, (LSB)MR18= 0x3f6, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 408 ps
3533 23:05:52.117525 CH1 RK0: MR19=403, MR18=3F6
3534 23:05:52.123346 CH1_RK0: MR19=0x403, MR18=0x3F6, DQSOSC=408, MR23=63, INC=39, DEC=26
3535 23:05:52.123969
3536 23:05:52.126168 ----->DramcWriteLeveling(PI) begin...
3537 23:05:52.126610 ==
3538 23:05:52.129868 Dram Type= 6, Freq= 0, CH_1, rank 1
3539 23:05:52.133109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3540 23:05:52.136370 ==
3541 23:05:52.136795 Write leveling (Byte 0): 24 => 24
3542 23:05:52.139788 Write leveling (Byte 1): 28 => 28
3543 23:05:52.142649 DramcWriteLeveling(PI) end<-----
3544 23:05:52.143175
3545 23:05:52.143792 ==
3546 23:05:52.146187 Dram Type= 6, Freq= 0, CH_1, rank 1
3547 23:05:52.152731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3548 23:05:52.153168 ==
3549 23:05:52.156073 [Gating] SW mode calibration
3550 23:05:52.162891 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3551 23:05:52.166027 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3552 23:05:52.172545 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3553 23:05:52.175851 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3554 23:05:52.179087 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3555 23:05:52.185508 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3556 23:05:52.188977 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3557 23:05:52.192424 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3558 23:05:52.198933 0 15 24 | B1->B0 | 3333 3434 | 0 1 | (0 1) (1 0)
3559 23:05:52.202654 0 15 28 | B1->B0 | 2424 2828 | 0 0 | (1 0) (1 0)
3560 23:05:52.205526 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3561 23:05:52.211964 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3562 23:05:52.215156 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3563 23:05:52.218147 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3564 23:05:52.224782 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3565 23:05:52.228113 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3566 23:05:52.231689 1 0 24 | B1->B0 | 3636 2525 | 0 0 | (0 0) (0 0)
3567 23:05:52.238128 1 0 28 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
3568 23:05:52.241498 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3569 23:05:52.245021 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3570 23:05:52.251231 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3571 23:05:52.254639 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3572 23:05:52.257788 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3573 23:05:52.264721 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3574 23:05:52.267865 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3575 23:05:52.270984 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3576 23:05:52.277461 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3577 23:05:52.280703 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3578 23:05:52.283810 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3579 23:05:52.290859 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3580 23:05:52.294333 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3581 23:05:52.297346 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3582 23:05:52.303846 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3583 23:05:52.307108 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3584 23:05:52.310258 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3585 23:05:52.316914 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3586 23:05:52.320107 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3587 23:05:52.323830 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3588 23:05:52.330595 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3589 23:05:52.333580 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3590 23:05:52.337125 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3591 23:05:52.343324 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3592 23:05:52.346542 Total UI for P1: 0, mck2ui 16
3593 23:05:52.350266 best dqsien dly found for B1: ( 1, 3, 24)
3594 23:05:52.353189 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3595 23:05:52.356440 Total UI for P1: 0, mck2ui 16
3596 23:05:52.360033 best dqsien dly found for B0: ( 1, 3, 26)
3597 23:05:52.363050 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3598 23:05:52.366251 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3599 23:05:52.366678
3600 23:05:52.369508 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3601 23:05:52.376283 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3602 23:05:52.376707 [Gating] SW calibration Done
3603 23:05:52.377050 ==
3604 23:05:52.379577 Dram Type= 6, Freq= 0, CH_1, rank 1
3605 23:05:52.386234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3606 23:05:52.386660 ==
3607 23:05:52.387001 RX Vref Scan: 0
3608 23:05:52.387320
3609 23:05:52.389579 RX Vref 0 -> 0, step: 1
3610 23:05:52.390004
3611 23:05:52.392688 RX Delay -40 -> 252, step: 8
3612 23:05:52.395719 iDelay=208, Bit 0, Center 123 (56 ~ 191) 136
3613 23:05:52.399507 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3614 23:05:52.402304 iDelay=208, Bit 2, Center 103 (32 ~ 175) 144
3615 23:05:52.409195 iDelay=208, Bit 3, Center 111 (40 ~ 183) 144
3616 23:05:52.412500 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3617 23:05:52.415391 iDelay=208, Bit 5, Center 127 (56 ~ 199) 144
3618 23:05:52.418857 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
3619 23:05:52.425321 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3620 23:05:52.428573 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3621 23:05:52.431952 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
3622 23:05:52.435425 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3623 23:05:52.439207 iDelay=208, Bit 11, Center 103 (32 ~ 175) 144
3624 23:05:52.445330 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3625 23:05:52.449040 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3626 23:05:52.451870 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3627 23:05:52.455136 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3628 23:05:52.455568 ==
3629 23:05:52.458811 Dram Type= 6, Freq= 0, CH_1, rank 1
3630 23:05:52.461988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3631 23:05:52.465106 ==
3632 23:05:52.465574 DQS Delay:
3633 23:05:52.465926 DQS0 = 0, DQS1 = 0
3634 23:05:52.468453 DQM Delay:
3635 23:05:52.468877 DQM0 = 117, DQM1 = 110
3636 23:05:52.472086 DQ Delay:
3637 23:05:52.475178 DQ0 =123, DQ1 =111, DQ2 =103, DQ3 =111
3638 23:05:52.478816 DQ4 =115, DQ5 =127, DQ6 =131, DQ7 =115
3639 23:05:52.482251 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3640 23:05:52.485332 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3641 23:05:52.485808
3642 23:05:52.486184
3643 23:05:52.486507 ==
3644 23:05:52.488624 Dram Type= 6, Freq= 0, CH_1, rank 1
3645 23:05:52.492402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3646 23:05:52.492834 ==
3647 23:05:52.494769
3648 23:05:52.495188
3649 23:05:52.495523 TX Vref Scan disable
3650 23:05:52.498570 == TX Byte 0 ==
3651 23:05:52.501551 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3652 23:05:52.505024 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3653 23:05:52.507969 == TX Byte 1 ==
3654 23:05:52.511333 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3655 23:05:52.514502 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3656 23:05:52.514937 ==
3657 23:05:52.518216 Dram Type= 6, Freq= 0, CH_1, rank 1
3658 23:05:52.524767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3659 23:05:52.525256 ==
3660 23:05:52.535658 TX Vref=22, minBit 8, minWin=25, winSum=423
3661 23:05:52.539397 TX Vref=24, minBit 8, minWin=25, winSum=427
3662 23:05:52.541957 TX Vref=26, minBit 8, minWin=26, winSum=433
3663 23:05:52.545552 TX Vref=28, minBit 8, minWin=25, winSum=431
3664 23:05:52.549287 TX Vref=30, minBit 8, minWin=26, winSum=434
3665 23:05:52.555261 TX Vref=32, minBit 9, minWin=25, winSum=430
3666 23:05:52.558439 [TxChooseVref] Worse bit 8, Min win 26, Win sum 434, Final Vref 30
3667 23:05:52.558910
3668 23:05:52.561743 Final TX Range 1 Vref 30
3669 23:05:52.562176
3670 23:05:52.562511 ==
3671 23:05:52.565547 Dram Type= 6, Freq= 0, CH_1, rank 1
3672 23:05:52.568855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3673 23:05:52.572091 ==
3674 23:05:52.572513
3675 23:05:52.572849
3676 23:05:52.573162 TX Vref Scan disable
3677 23:05:52.575395 == TX Byte 0 ==
3678 23:05:52.579025 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3679 23:05:52.585496 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3680 23:05:52.586041 == TX Byte 1 ==
3681 23:05:52.588323 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3682 23:05:52.595127 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3683 23:05:52.595557
3684 23:05:52.595899 [DATLAT]
3685 23:05:52.596216 Freq=1200, CH1 RK1
3686 23:05:52.596529
3687 23:05:52.598397 DATLAT Default: 0xd
3688 23:05:52.598836 0, 0xFFFF, sum = 0
3689 23:05:52.601739 1, 0xFFFF, sum = 0
3690 23:05:52.604908 2, 0xFFFF, sum = 0
3691 23:05:52.605339 3, 0xFFFF, sum = 0
3692 23:05:52.608208 4, 0xFFFF, sum = 0
3693 23:05:52.608671 5, 0xFFFF, sum = 0
3694 23:05:52.611792 6, 0xFFFF, sum = 0
3695 23:05:52.612222 7, 0xFFFF, sum = 0
3696 23:05:52.614992 8, 0xFFFF, sum = 0
3697 23:05:52.615542 9, 0xFFFF, sum = 0
3698 23:05:52.618474 10, 0xFFFF, sum = 0
3699 23:05:52.618906 11, 0xFFFF, sum = 0
3700 23:05:52.621476 12, 0x0, sum = 1
3701 23:05:52.621911 13, 0x0, sum = 2
3702 23:05:52.625145 14, 0x0, sum = 3
3703 23:05:52.625623 15, 0x0, sum = 4
3704 23:05:52.628110 best_step = 13
3705 23:05:52.628532
3706 23:05:52.628870 ==
3707 23:05:52.631490 Dram Type= 6, Freq= 0, CH_1, rank 1
3708 23:05:52.634506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3709 23:05:52.634935 ==
3710 23:05:52.638436 RX Vref Scan: 0
3711 23:05:52.638860
3712 23:05:52.639202 RX Vref 0 -> 0, step: 1
3713 23:05:52.639522
3714 23:05:52.641168 RX Delay -21 -> 252, step: 4
3715 23:05:52.648191 iDelay=199, Bit 0, Center 120 (51 ~ 190) 140
3716 23:05:52.651005 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3717 23:05:52.654741 iDelay=199, Bit 2, Center 108 (43 ~ 174) 132
3718 23:05:52.658034 iDelay=199, Bit 3, Center 110 (43 ~ 178) 136
3719 23:05:52.660741 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3720 23:05:52.667914 iDelay=199, Bit 5, Center 126 (59 ~ 194) 136
3721 23:05:52.671291 iDelay=199, Bit 6, Center 130 (63 ~ 198) 136
3722 23:05:52.674172 iDelay=199, Bit 7, Center 116 (51 ~ 182) 132
3723 23:05:52.677485 iDelay=199, Bit 8, Center 98 (31 ~ 166) 136
3724 23:05:52.680712 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3725 23:05:52.687742 iDelay=199, Bit 10, Center 112 (47 ~ 178) 132
3726 23:05:52.690865 iDelay=199, Bit 11, Center 102 (35 ~ 170) 136
3727 23:05:52.693949 iDelay=199, Bit 12, Center 120 (55 ~ 186) 132
3728 23:05:52.697533 iDelay=199, Bit 13, Center 116 (51 ~ 182) 132
3729 23:05:52.703920 iDelay=199, Bit 14, Center 120 (55 ~ 186) 132
3730 23:05:52.707266 iDelay=199, Bit 15, Center 120 (51 ~ 190) 140
3731 23:05:52.707694 ==
3732 23:05:52.710540 Dram Type= 6, Freq= 0, CH_1, rank 1
3733 23:05:52.713639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3734 23:05:52.714285 ==
3735 23:05:52.717168 DQS Delay:
3736 23:05:52.717636 DQS0 = 0, DQS1 = 0
3737 23:05:52.717981 DQM Delay:
3738 23:05:52.720619 DQM0 = 117, DQM1 = 111
3739 23:05:52.721045 DQ Delay:
3740 23:05:52.723784 DQ0 =120, DQ1 =110, DQ2 =108, DQ3 =110
3741 23:05:52.727194 DQ4 =116, DQ5 =126, DQ6 =130, DQ7 =116
3742 23:05:52.730686 DQ8 =98, DQ9 =100, DQ10 =112, DQ11 =102
3743 23:05:52.737179 DQ12 =120, DQ13 =116, DQ14 =120, DQ15 =120
3744 23:05:52.737654
3745 23:05:52.738004
3746 23:05:52.743700 [DQSOSCAuto] RK1, (LSB)MR18= 0xf6f0, (MSB)MR19= 0x303, tDQSOscB0 = 416 ps tDQSOscB1 = 414 ps
3747 23:05:52.746968 CH1 RK1: MR19=303, MR18=F6F0
3748 23:05:52.753205 CH1_RK1: MR19=0x303, MR18=0xF6F0, DQSOSC=414, MR23=63, INC=38, DEC=25
3749 23:05:52.756774 [RxdqsGatingPostProcess] freq 1200
3750 23:05:52.760090 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3751 23:05:52.763573 best DQS0 dly(2T, 0.5T) = (0, 11)
3752 23:05:52.766809 best DQS1 dly(2T, 0.5T) = (0, 11)
3753 23:05:52.769983 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3754 23:05:52.773377 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3755 23:05:52.776623 best DQS0 dly(2T, 0.5T) = (0, 11)
3756 23:05:52.780500 best DQS1 dly(2T, 0.5T) = (0, 11)
3757 23:05:52.783176 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3758 23:05:52.786570 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3759 23:05:52.789883 Pre-setting of DQS Precalculation
3760 23:05:52.793364 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3761 23:05:52.803003 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3762 23:05:52.809547 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3763 23:05:52.809977
3764 23:05:52.810382
3765 23:05:52.812969 [Calibration Summary] 2400 Mbps
3766 23:05:52.813556 CH 0, Rank 0
3767 23:05:52.815979 SW Impedance : PASS
3768 23:05:52.816412 DUTY Scan : NO K
3769 23:05:52.819289 ZQ Calibration : PASS
3770 23:05:52.822679 Jitter Meter : NO K
3771 23:05:52.823105 CBT Training : PASS
3772 23:05:52.826288 Write leveling : PASS
3773 23:05:52.829751 RX DQS gating : PASS
3774 23:05:52.830189 RX DQ/DQS(RDDQC) : PASS
3775 23:05:52.833034 TX DQ/DQS : PASS
3776 23:05:52.835772 RX DATLAT : PASS
3777 23:05:52.836210 RX DQ/DQS(Engine): PASS
3778 23:05:52.839430 TX OE : NO K
3779 23:05:52.839870 All Pass.
3780 23:05:52.840310
3781 23:05:52.842534 CH 0, Rank 1
3782 23:05:52.842972 SW Impedance : PASS
3783 23:05:52.845851 DUTY Scan : NO K
3784 23:05:52.849184 ZQ Calibration : PASS
3785 23:05:52.849772 Jitter Meter : NO K
3786 23:05:52.852389 CBT Training : PASS
3787 23:05:52.855773 Write leveling : PASS
3788 23:05:52.856195 RX DQS gating : PASS
3789 23:05:52.859115 RX DQ/DQS(RDDQC) : PASS
3790 23:05:52.862576 TX DQ/DQS : PASS
3791 23:05:52.863002 RX DATLAT : PASS
3792 23:05:52.866422 RX DQ/DQS(Engine): PASS
3793 23:05:52.868996 TX OE : NO K
3794 23:05:52.869603 All Pass.
3795 23:05:52.870085
3796 23:05:52.870539 CH 1, Rank 0
3797 23:05:52.872267 SW Impedance : PASS
3798 23:05:52.875348 DUTY Scan : NO K
3799 23:05:52.875772 ZQ Calibration : PASS
3800 23:05:52.879201 Jitter Meter : NO K
3801 23:05:52.879626 CBT Training : PASS
3802 23:05:52.882747 Write leveling : PASS
3803 23:05:52.885832 RX DQS gating : PASS
3804 23:05:52.886257 RX DQ/DQS(RDDQC) : PASS
3805 23:05:52.888808 TX DQ/DQS : PASS
3806 23:05:52.893147 RX DATLAT : PASS
3807 23:05:52.893764 RX DQ/DQS(Engine): PASS
3808 23:05:52.895289 TX OE : NO K
3809 23:05:52.895714 All Pass.
3810 23:05:52.896049
3811 23:05:52.898707 CH 1, Rank 1
3812 23:05:52.899129 SW Impedance : PASS
3813 23:05:52.902447 DUTY Scan : NO K
3814 23:05:52.905699 ZQ Calibration : PASS
3815 23:05:52.906125 Jitter Meter : NO K
3816 23:05:52.908784 CBT Training : PASS
3817 23:05:52.912148 Write leveling : PASS
3818 23:05:52.912574 RX DQS gating : PASS
3819 23:05:52.915450 RX DQ/DQS(RDDQC) : PASS
3820 23:05:52.918467 TX DQ/DQS : PASS
3821 23:05:52.918894 RX DATLAT : PASS
3822 23:05:52.922203 RX DQ/DQS(Engine): PASS
3823 23:05:52.925068 TX OE : NO K
3824 23:05:52.925538 All Pass.
3825 23:05:52.925884
3826 23:05:52.926195 DramC Write-DBI off
3827 23:05:52.928631 PER_BANK_REFRESH: Hybrid Mode
3828 23:05:52.931686 TX_TRACKING: ON
3829 23:05:52.938765 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3830 23:05:52.944750 [FAST_K] Save calibration result to emmc
3831 23:05:52.948117 dramc_set_vcore_voltage set vcore to 650000
3832 23:05:52.948697 Read voltage for 600, 5
3833 23:05:52.951512 Vio18 = 0
3834 23:05:52.951933 Vcore = 650000
3835 23:05:52.952307 Vdram = 0
3836 23:05:52.954810 Vddq = 0
3837 23:05:52.955232 Vmddr = 0
3838 23:05:52.957813 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3839 23:05:52.964969 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3840 23:05:52.968268 MEM_TYPE=3, freq_sel=19
3841 23:05:52.971243 sv_algorithm_assistance_LP4_1600
3842 23:05:52.974690 ============ PULL DRAM RESETB DOWN ============
3843 23:05:52.977840 ========== PULL DRAM RESETB DOWN end =========
3844 23:05:52.984410 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3845 23:05:52.987534 ===================================
3846 23:05:52.987610 LPDDR4 DRAM CONFIGURATION
3847 23:05:52.990529 ===================================
3848 23:05:52.994437 EX_ROW_EN[0] = 0x0
3849 23:05:52.994519 EX_ROW_EN[1] = 0x0
3850 23:05:52.997647 LP4Y_EN = 0x0
3851 23:05:52.997735 WORK_FSP = 0x0
3852 23:05:53.000538 WL = 0x2
3853 23:05:53.003729 RL = 0x2
3854 23:05:53.003828 BL = 0x2
3855 23:05:53.007377 RPST = 0x0
3856 23:05:53.007459 RD_PRE = 0x0
3857 23:05:53.010272 WR_PRE = 0x1
3858 23:05:53.010355 WR_PST = 0x0
3859 23:05:53.014248 DBI_WR = 0x0
3860 23:05:53.014330 DBI_RD = 0x0
3861 23:05:53.018112 OTF = 0x1
3862 23:05:53.020508 ===================================
3863 23:05:53.023741 ===================================
3864 23:05:53.023824 ANA top config
3865 23:05:53.027131 ===================================
3866 23:05:53.030560 DLL_ASYNC_EN = 0
3867 23:05:53.033672 ALL_SLAVE_EN = 1
3868 23:05:53.033754 NEW_RANK_MODE = 1
3869 23:05:53.037107 DLL_IDLE_MODE = 1
3870 23:05:53.040178 LP45_APHY_COMB_EN = 1
3871 23:05:53.043554 TX_ODT_DIS = 1
3872 23:05:53.046687 NEW_8X_MODE = 1
3873 23:05:53.049945 ===================================
3874 23:05:53.053626 ===================================
3875 23:05:53.053708 data_rate = 1200
3876 23:05:53.056942 CKR = 1
3877 23:05:53.060168 DQ_P2S_RATIO = 8
3878 23:05:53.063097 ===================================
3879 23:05:53.066749 CA_P2S_RATIO = 8
3880 23:05:53.069893 DQ_CA_OPEN = 0
3881 23:05:53.073054 DQ_SEMI_OPEN = 0
3882 23:05:53.076550 CA_SEMI_OPEN = 0
3883 23:05:53.076633 CA_FULL_RATE = 0
3884 23:05:53.079626 DQ_CKDIV4_EN = 1
3885 23:05:53.082975 CA_CKDIV4_EN = 1
3886 23:05:53.086661 CA_PREDIV_EN = 0
3887 23:05:53.089949 PH8_DLY = 0
3888 23:05:53.092680 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3889 23:05:53.092762 DQ_AAMCK_DIV = 4
3890 23:05:53.096325 CA_AAMCK_DIV = 4
3891 23:05:53.099712 CA_ADMCK_DIV = 4
3892 23:05:53.102741 DQ_TRACK_CA_EN = 0
3893 23:05:53.105779 CA_PICK = 600
3894 23:05:53.109160 CA_MCKIO = 600
3895 23:05:53.112942 MCKIO_SEMI = 0
3896 23:05:53.113025 PLL_FREQ = 2288
3897 23:05:53.116154 DQ_UI_PI_RATIO = 32
3898 23:05:53.119522 CA_UI_PI_RATIO = 0
3899 23:05:53.122613 ===================================
3900 23:05:53.126127 ===================================
3901 23:05:53.129200 memory_type:LPDDR4
3902 23:05:53.132367 GP_NUM : 10
3903 23:05:53.132449 SRAM_EN : 1
3904 23:05:53.135574 MD32_EN : 0
3905 23:05:53.138982 ===================================
3906 23:05:53.139065 [ANA_INIT] >>>>>>>>>>>>>>
3907 23:05:53.142274 <<<<<< [CONFIGURE PHASE]: ANA_TX
3908 23:05:53.145363 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3909 23:05:53.149150 ===================================
3910 23:05:53.152680 data_rate = 1200,PCW = 0X5800
3911 23:05:53.155903 ===================================
3912 23:05:53.159025 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3913 23:05:53.165366 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3914 23:05:53.171826 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3915 23:05:53.175312 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3916 23:05:53.179107 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3917 23:05:53.181799 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3918 23:05:53.185297 [ANA_INIT] flow start
3919 23:05:53.185380 [ANA_INIT] PLL >>>>>>>>
3920 23:05:53.188398 [ANA_INIT] PLL <<<<<<<<
3921 23:05:53.191715 [ANA_INIT] MIDPI >>>>>>>>
3922 23:05:53.191799 [ANA_INIT] MIDPI <<<<<<<<
3923 23:05:53.194941 [ANA_INIT] DLL >>>>>>>>
3924 23:05:53.198464 [ANA_INIT] flow end
3925 23:05:53.201992 ============ LP4 DIFF to SE enter ============
3926 23:05:53.205319 ============ LP4 DIFF to SE exit ============
3927 23:05:53.208476 [ANA_INIT] <<<<<<<<<<<<<
3928 23:05:53.211603 [Flow] Enable top DCM control >>>>>
3929 23:05:53.215383 [Flow] Enable top DCM control <<<<<
3930 23:05:53.218223 Enable DLL master slave shuffle
3931 23:05:53.225065 ==============================================================
3932 23:05:53.225151 Gating Mode config
3933 23:05:53.231634 ==============================================================
3934 23:05:53.231751 Config description:
3935 23:05:53.241162 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3936 23:05:53.247589 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3937 23:05:53.254696 SELPH_MODE 0: By rank 1: By Phase
3938 23:05:53.257488 ==============================================================
3939 23:05:53.261243 GAT_TRACK_EN = 1
3940 23:05:53.264401 RX_GATING_MODE = 2
3941 23:05:53.267503 RX_GATING_TRACK_MODE = 2
3942 23:05:53.270891 SELPH_MODE = 1
3943 23:05:53.274561 PICG_EARLY_EN = 1
3944 23:05:53.277458 VALID_LAT_VALUE = 1
3945 23:05:53.284008 ==============================================================
3946 23:05:53.287446 Enter into Gating configuration >>>>
3947 23:05:53.290512 Exit from Gating configuration <<<<
3948 23:05:53.294060 Enter into DVFS_PRE_config >>>>>
3949 23:05:53.303626 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3950 23:05:53.307157 Exit from DVFS_PRE_config <<<<<
3951 23:05:53.310612 Enter into PICG configuration >>>>
3952 23:05:53.313912 Exit from PICG configuration <<<<
3953 23:05:53.317150 [RX_INPUT] configuration >>>>>
3954 23:05:53.317247 [RX_INPUT] configuration <<<<<
3955 23:05:53.323544 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3956 23:05:53.330680 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3957 23:05:53.333639 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3958 23:05:53.340697 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3959 23:05:53.346889 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3960 23:05:53.353314 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3961 23:05:53.356435 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3962 23:05:53.360189 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3963 23:05:53.366769 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3964 23:05:53.370560 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3965 23:05:53.373213 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3966 23:05:53.379820 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3967 23:05:53.383274 ===================================
3968 23:05:53.383401 LPDDR4 DRAM CONFIGURATION
3969 23:05:53.386706 ===================================
3970 23:05:53.390079 EX_ROW_EN[0] = 0x0
3971 23:05:53.390221 EX_ROW_EN[1] = 0x0
3972 23:05:53.393160 LP4Y_EN = 0x0
3973 23:05:53.393310 WORK_FSP = 0x0
3974 23:05:53.396710 WL = 0x2
3975 23:05:53.399941 RL = 0x2
3976 23:05:53.400129 BL = 0x2
3977 23:05:53.403181 RPST = 0x0
3978 23:05:53.403394 RD_PRE = 0x0
3979 23:05:53.406899 WR_PRE = 0x1
3980 23:05:53.407187 WR_PST = 0x0
3981 23:05:53.410225 DBI_WR = 0x0
3982 23:05:53.410501 DBI_RD = 0x0
3983 23:05:53.413169 OTF = 0x1
3984 23:05:53.417103 ===================================
3985 23:05:53.419986 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3986 23:05:53.423070 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3987 23:05:53.430022 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3988 23:05:53.433079 ===================================
3989 23:05:53.433559 LPDDR4 DRAM CONFIGURATION
3990 23:05:53.436386 ===================================
3991 23:05:53.439789 EX_ROW_EN[0] = 0x10
3992 23:05:53.440296 EX_ROW_EN[1] = 0x0
3993 23:05:53.443073 LP4Y_EN = 0x0
3994 23:05:53.446758 WORK_FSP = 0x0
3995 23:05:53.447238 WL = 0x2
3996 23:05:53.449771 RL = 0x2
3997 23:05:53.450212 BL = 0x2
3998 23:05:53.452971 RPST = 0x0
3999 23:05:53.453514 RD_PRE = 0x0
4000 23:05:53.456252 WR_PRE = 0x1
4001 23:05:53.456713 WR_PST = 0x0
4002 23:05:53.459174 DBI_WR = 0x0
4003 23:05:53.459565 DBI_RD = 0x0
4004 23:05:53.463174 OTF = 0x1
4005 23:05:53.466050 ===================================
4006 23:05:53.472971 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4007 23:05:53.476015 nWR fixed to 30
4008 23:05:53.476465 [ModeRegInit_LP4] CH0 RK0
4009 23:05:53.479092 [ModeRegInit_LP4] CH0 RK1
4010 23:05:53.482726 [ModeRegInit_LP4] CH1 RK0
4011 23:05:53.485727 [ModeRegInit_LP4] CH1 RK1
4012 23:05:53.486159 match AC timing 17
4013 23:05:53.491984 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
4014 23:05:53.495501 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4015 23:05:53.499016 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
4016 23:05:53.505445 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
4017 23:05:53.508537 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
4018 23:05:53.508996 ==
4019 23:05:53.512486 Dram Type= 6, Freq= 0, CH_0, rank 0
4020 23:05:53.515057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4021 23:05:53.515497 ==
4022 23:05:53.522020 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4023 23:05:53.528617 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4024 23:05:53.531875 [CA 0] Center 36 (6~66) winsize 61
4025 23:05:53.535325 [CA 1] Center 36 (6~66) winsize 61
4026 23:05:53.538263 [CA 2] Center 33 (3~64) winsize 62
4027 23:05:53.541974 [CA 3] Center 33 (3~64) winsize 62
4028 23:05:53.545310 [CA 4] Center 33 (3~64) winsize 62
4029 23:05:53.548139 [CA 5] Center 33 (3~64) winsize 62
4030 23:05:53.548562
4031 23:05:53.551622 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4032 23:05:53.552048
4033 23:05:53.555222 [CATrainingPosCal] consider 1 rank data
4034 23:05:53.558076 u2DelayCellTimex100 = 270/100 ps
4035 23:05:53.561771 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4036 23:05:53.564656 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4037 23:05:53.568047 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4038 23:05:53.571274 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4039 23:05:53.574821 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4040 23:05:53.581003 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4041 23:05:53.581458
4042 23:05:53.584785 CA PerBit enable=1, Macro0, CA PI delay=33
4043 23:05:53.585213
4044 23:05:53.587745 [CBTSetCACLKResult] CA Dly = 33
4045 23:05:53.588171 CS Dly: 5 (0~36)
4046 23:05:53.588515 ==
4047 23:05:53.591191 Dram Type= 6, Freq= 0, CH_0, rank 1
4048 23:05:53.597531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4049 23:05:53.597964 ==
4050 23:05:53.601255 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4051 23:05:53.607505 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4052 23:05:53.610862 [CA 0] Center 36 (6~66) winsize 61
4053 23:05:53.614199 [CA 1] Center 36 (6~66) winsize 61
4054 23:05:53.617283 [CA 2] Center 34 (3~65) winsize 63
4055 23:05:53.621099 [CA 3] Center 33 (3~64) winsize 62
4056 23:05:53.623919 [CA 4] Center 33 (3~64) winsize 62
4057 23:05:53.627557 [CA 5] Center 33 (2~64) winsize 63
4058 23:05:53.628015
4059 23:05:53.630482 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4060 23:05:53.630944
4061 23:05:53.633647 [CATrainingPosCal] consider 2 rank data
4062 23:05:53.637208 u2DelayCellTimex100 = 270/100 ps
4063 23:05:53.640408 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4064 23:05:53.647102 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4065 23:05:53.650269 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4066 23:05:53.654106 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4067 23:05:53.656834 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4068 23:05:53.660220 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4069 23:05:53.660646
4070 23:05:53.663173 CA PerBit enable=1, Macro0, CA PI delay=33
4071 23:05:53.663601
4072 23:05:53.666502 [CBTSetCACLKResult] CA Dly = 33
4073 23:05:53.669991 CS Dly: 5 (0~36)
4074 23:05:53.670438
4075 23:05:53.673535 ----->DramcWriteLeveling(PI) begin...
4076 23:05:53.673968 ==
4077 23:05:53.676315 Dram Type= 6, Freq= 0, CH_0, rank 0
4078 23:05:53.679570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4079 23:05:53.680022 ==
4080 23:05:53.683458 Write leveling (Byte 0): 33 => 33
4081 23:05:53.686774 Write leveling (Byte 1): 29 => 29
4082 23:05:53.690245 DramcWriteLeveling(PI) end<-----
4083 23:05:53.690689
4084 23:05:53.691032 ==
4085 23:05:53.692896 Dram Type= 6, Freq= 0, CH_0, rank 0
4086 23:05:53.696437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4087 23:05:53.696860 ==
4088 23:05:53.699851 [Gating] SW mode calibration
4089 23:05:53.706113 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4090 23:05:53.712699 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4091 23:05:53.715823 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4092 23:05:53.719019 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4093 23:05:53.726008 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4094 23:05:53.729046 0 9 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
4095 23:05:53.732515 0 9 16 | B1->B0 | 2f2f 2626 | 1 0 | (1 0) (0 0)
4096 23:05:53.739012 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4097 23:05:53.742771 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4098 23:05:53.745467 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4099 23:05:53.752447 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4100 23:05:53.755673 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4101 23:05:53.758930 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4102 23:05:53.765359 0 10 12 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
4103 23:05:53.768632 0 10 16 | B1->B0 | 3434 4343 | 0 0 | (0 0) (0 0)
4104 23:05:53.772322 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4105 23:05:53.778733 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4106 23:05:53.781689 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4107 23:05:53.785568 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4108 23:05:53.792093 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4109 23:05:53.795312 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4110 23:05:53.801982 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4111 23:05:53.804968 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4112 23:05:53.808030 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4113 23:05:53.814949 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4114 23:05:53.817786 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4115 23:05:53.821283 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4116 23:05:53.828040 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4117 23:05:53.831377 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4118 23:05:53.834672 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4119 23:05:53.841194 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4120 23:05:53.844526 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4121 23:05:53.847682 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4122 23:05:53.854622 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4123 23:05:53.857541 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4124 23:05:53.860653 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4125 23:05:53.867737 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4126 23:05:53.870678 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4127 23:05:53.874020 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4128 23:05:53.877113 Total UI for P1: 0, mck2ui 16
4129 23:05:53.880724 best dqsien dly found for B0: ( 0, 13, 14)
4130 23:05:53.884109 Total UI for P1: 0, mck2ui 16
4131 23:05:53.887633 best dqsien dly found for B1: ( 0, 13, 14)
4132 23:05:53.890347 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4133 23:05:53.893586 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4134 23:05:53.894022
4135 23:05:53.897309 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4136 23:05:53.903736 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4137 23:05:53.904164 [Gating] SW calibration Done
4138 23:05:53.904510 ==
4139 23:05:53.907324 Dram Type= 6, Freq= 0, CH_0, rank 0
4140 23:05:53.914084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4141 23:05:53.914528 ==
4142 23:05:53.914873 RX Vref Scan: 0
4143 23:05:53.915194
4144 23:05:53.917666 RX Vref 0 -> 0, step: 1
4145 23:05:53.918092
4146 23:05:53.920678 RX Delay -230 -> 252, step: 16
4147 23:05:53.923408 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4148 23:05:53.926789 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4149 23:05:53.933545 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4150 23:05:53.937102 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4151 23:05:53.940205 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4152 23:05:53.943253 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4153 23:05:53.946635 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4154 23:05:53.953685 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4155 23:05:53.956716 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4156 23:05:53.959772 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4157 23:05:53.963283 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4158 23:05:53.970096 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4159 23:05:53.973492 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4160 23:05:53.976383 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4161 23:05:53.979781 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4162 23:05:53.986208 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4163 23:05:53.986641 ==
4164 23:05:53.989524 Dram Type= 6, Freq= 0, CH_0, rank 0
4165 23:05:53.992781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4166 23:05:53.993216 ==
4167 23:05:53.993599 DQS Delay:
4168 23:05:53.996139 DQS0 = 0, DQS1 = 0
4169 23:05:53.996618 DQM Delay:
4170 23:05:53.999759 DQM0 = 42, DQM1 = 29
4171 23:05:54.000205 DQ Delay:
4172 23:05:54.003039 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4173 23:05:54.006379 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4174 23:05:54.009528 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4175 23:05:54.012744 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4176 23:05:54.013174
4177 23:05:54.013563
4178 23:05:54.013893 ==
4179 23:05:54.016558 Dram Type= 6, Freq= 0, CH_0, rank 0
4180 23:05:54.019192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4181 23:05:54.022356 ==
4182 23:05:54.022786
4183 23:05:54.023131
4184 23:05:54.023450 TX Vref Scan disable
4185 23:05:54.026265 == TX Byte 0 ==
4186 23:05:54.029232 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4187 23:05:54.035505 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4188 23:05:54.035940 == TX Byte 1 ==
4189 23:05:54.039404 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4190 23:05:54.045749 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4191 23:05:54.046210 ==
4192 23:05:54.048929 Dram Type= 6, Freq= 0, CH_0, rank 0
4193 23:05:54.052323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4194 23:05:54.052759 ==
4195 23:05:54.053104
4196 23:05:54.053463
4197 23:05:54.055724 TX Vref Scan disable
4198 23:05:54.058708 == TX Byte 0 ==
4199 23:05:54.062230 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4200 23:05:54.065188 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4201 23:05:54.069051 == TX Byte 1 ==
4202 23:05:54.072106 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4203 23:05:54.075378 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4204 23:05:54.075810
4205 23:05:54.078748 [DATLAT]
4206 23:05:54.079180 Freq=600, CH0 RK0
4207 23:05:54.079521
4208 23:05:54.081941 DATLAT Default: 0x9
4209 23:05:54.082025 0, 0xFFFF, sum = 0
4210 23:05:54.085043 1, 0xFFFF, sum = 0
4211 23:05:54.085127 2, 0xFFFF, sum = 0
4212 23:05:54.088127 3, 0xFFFF, sum = 0
4213 23:05:54.088212 4, 0xFFFF, sum = 0
4214 23:05:54.091746 5, 0xFFFF, sum = 0
4215 23:05:54.091831 6, 0xFFFF, sum = 0
4216 23:05:54.094886 7, 0xFFFF, sum = 0
4217 23:05:54.094986 8, 0x0, sum = 1
4218 23:05:54.098130 9, 0x0, sum = 2
4219 23:05:54.098215 10, 0x0, sum = 3
4220 23:05:54.101644 11, 0x0, sum = 4
4221 23:05:54.102081 best_step = 9
4222 23:05:54.102428
4223 23:05:54.102747 ==
4224 23:05:54.105160 Dram Type= 6, Freq= 0, CH_0, rank 0
4225 23:05:54.108275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4226 23:05:54.108718 ==
4227 23:05:54.111769 RX Vref Scan: 1
4228 23:05:54.112318
4229 23:05:54.115558 RX Vref 0 -> 0, step: 1
4230 23:05:54.115989
4231 23:05:54.116333 RX Delay -195 -> 252, step: 8
4232 23:05:54.118648
4233 23:05:54.119075 Set Vref, RX VrefLevel [Byte0]: 61
4234 23:05:54.121828 [Byte1]: 49
4235 23:05:54.126557
4236 23:05:54.127021 Final RX Vref Byte 0 = 61 to rank0
4237 23:05:54.130560 Final RX Vref Byte 1 = 49 to rank0
4238 23:05:54.133030 Final RX Vref Byte 0 = 61 to rank1
4239 23:05:54.136222 Final RX Vref Byte 1 = 49 to rank1==
4240 23:05:54.139738 Dram Type= 6, Freq= 0, CH_0, rank 0
4241 23:05:54.146319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4242 23:05:54.146751 ==
4243 23:05:54.147095 DQS Delay:
4244 23:05:54.149799 DQS0 = 0, DQS1 = 0
4245 23:05:54.150224 DQM Delay:
4246 23:05:54.150563 DQM0 = 43, DQM1 = 32
4247 23:05:54.153259 DQ Delay:
4248 23:05:54.156338 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4249 23:05:54.159626 DQ4 =40, DQ5 =32, DQ6 =52, DQ7 =52
4250 23:05:54.162803 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =24
4251 23:05:54.165944 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =40
4252 23:05:54.166371
4253 23:05:54.166713
4254 23:05:54.172702 [DQSOSCAuto] RK0, (LSB)MR18= 0x6239, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 391 ps
4255 23:05:54.176023 CH0 RK0: MR19=808, MR18=6239
4256 23:05:54.182800 CH0_RK0: MR19=0x808, MR18=0x6239, DQSOSC=391, MR23=63, INC=171, DEC=114
4257 23:05:54.183228
4258 23:05:54.186398 ----->DramcWriteLeveling(PI) begin...
4259 23:05:54.186828 ==
4260 23:05:54.189019 Dram Type= 6, Freq= 0, CH_0, rank 1
4261 23:05:54.192245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4262 23:05:54.192715 ==
4263 23:05:54.195544 Write leveling (Byte 0): 32 => 32
4264 23:05:54.199487 Write leveling (Byte 1): 32 => 32
4265 23:05:54.202269 DramcWriteLeveling(PI) end<-----
4266 23:05:54.202702
4267 23:05:54.203042 ==
4268 23:05:54.205685 Dram Type= 6, Freq= 0, CH_0, rank 1
4269 23:05:54.209042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4270 23:05:54.212198 ==
4271 23:05:54.212626 [Gating] SW mode calibration
4272 23:05:54.222322 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4273 23:05:54.225373 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4274 23:05:54.228585 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4275 23:05:54.235380 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4276 23:05:54.238941 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4277 23:05:54.242462 0 9 12 | B1->B0 | 3333 3434 | 1 0 | (1 1) (0 0)
4278 23:05:54.248392 0 9 16 | B1->B0 | 2d2d 2a2a | 0 0 | (0 0) (0 0)
4279 23:05:54.251740 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4280 23:05:54.255257 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4281 23:05:54.261625 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4282 23:05:54.264990 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4283 23:05:54.268681 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4284 23:05:54.275136 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4285 23:05:54.278724 0 10 12 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
4286 23:05:54.282038 0 10 16 | B1->B0 | 3939 4444 | 0 0 | (0 0) (0 0)
4287 23:05:54.288048 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4288 23:05:54.291365 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4289 23:05:54.295408 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4290 23:05:54.301724 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4291 23:05:54.304926 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4292 23:05:54.308046 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4293 23:05:54.314525 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4294 23:05:54.317797 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4295 23:05:54.321157 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4296 23:05:54.327727 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4297 23:05:54.330806 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4298 23:05:54.334173 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4299 23:05:54.340763 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4300 23:05:54.344313 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4301 23:05:54.347251 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4302 23:05:54.353976 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4303 23:05:54.357525 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4304 23:05:54.361004 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4305 23:05:54.367344 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4306 23:05:54.370289 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4307 23:05:54.375189 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4308 23:05:54.380518 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4309 23:05:54.383622 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4310 23:05:54.387116 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4311 23:05:54.390745 Total UI for P1: 0, mck2ui 16
4312 23:05:54.394074 best dqsien dly found for B0: ( 0, 13, 12)
4313 23:05:54.397542 Total UI for P1: 0, mck2ui 16
4314 23:05:54.400595 best dqsien dly found for B1: ( 0, 13, 12)
4315 23:05:54.403720 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4316 23:05:54.406806 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4317 23:05:54.410138
4318 23:05:54.413218 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4319 23:05:54.416656 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4320 23:05:54.420369 [Gating] SW calibration Done
4321 23:05:54.421101 ==
4322 23:05:54.422921 Dram Type= 6, Freq= 0, CH_0, rank 1
4323 23:05:54.426037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4324 23:05:54.426496 ==
4325 23:05:54.429518 RX Vref Scan: 0
4326 23:05:54.429966
4327 23:05:54.430306 RX Vref 0 -> 0, step: 1
4328 23:05:54.430628
4329 23:05:54.433273 RX Delay -230 -> 252, step: 16
4330 23:05:54.436475 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4331 23:05:54.442681 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4332 23:05:54.446061 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4333 23:05:54.449810 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4334 23:05:54.452702 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4335 23:05:54.459442 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4336 23:05:54.462146 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4337 23:05:54.465758 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4338 23:05:54.469246 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4339 23:05:54.475516 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4340 23:05:54.478490 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4341 23:05:54.481964 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4342 23:05:54.485352 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4343 23:05:54.491846 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4344 23:05:54.495269 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4345 23:05:54.498639 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4346 23:05:54.499070 ==
4347 23:05:54.501882 Dram Type= 6, Freq= 0, CH_0, rank 1
4348 23:05:54.505268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4349 23:05:54.508290 ==
4350 23:05:54.508713 DQS Delay:
4351 23:05:54.509054 DQS0 = 0, DQS1 = 0
4352 23:05:54.511410 DQM Delay:
4353 23:05:54.511931 DQM0 = 41, DQM1 = 35
4354 23:05:54.514549 DQ Delay:
4355 23:05:54.518228 DQ0 =41, DQ1 =49, DQ2 =33, DQ3 =33
4356 23:05:54.521276 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4357 23:05:54.524402 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4358 23:05:54.527723 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =41
4359 23:05:54.528149
4360 23:05:54.528486
4361 23:05:54.528851 ==
4362 23:05:54.531539 Dram Type= 6, Freq= 0, CH_0, rank 1
4363 23:05:54.534689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4364 23:05:54.535168 ==
4365 23:05:54.535506
4366 23:05:54.535814
4367 23:05:54.537522 TX Vref Scan disable
4368 23:05:54.537941 == TX Byte 0 ==
4369 23:05:54.544048 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4370 23:05:54.547588 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4371 23:05:54.550813 == TX Byte 1 ==
4372 23:05:54.554015 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4373 23:05:54.557363 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4374 23:05:54.557877 ==
4375 23:05:54.560834 Dram Type= 6, Freq= 0, CH_0, rank 1
4376 23:05:54.563659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4377 23:05:54.566899 ==
4378 23:05:54.567321
4379 23:05:54.567656
4380 23:05:54.567969 TX Vref Scan disable
4381 23:05:54.571024 == TX Byte 0 ==
4382 23:05:54.574127 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4383 23:05:54.580984 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4384 23:05:54.581436 == TX Byte 1 ==
4385 23:05:54.584318 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4386 23:05:54.590575 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4387 23:05:54.590994
4388 23:05:54.591333 [DATLAT]
4389 23:05:54.591646 Freq=600, CH0 RK1
4390 23:05:54.591950
4391 23:05:54.594086 DATLAT Default: 0x9
4392 23:05:54.597682 0, 0xFFFF, sum = 0
4393 23:05:54.598113 1, 0xFFFF, sum = 0
4394 23:05:54.600639 2, 0xFFFF, sum = 0
4395 23:05:54.601067 3, 0xFFFF, sum = 0
4396 23:05:54.604240 4, 0xFFFF, sum = 0
4397 23:05:54.604768 5, 0xFFFF, sum = 0
4398 23:05:54.607627 6, 0xFFFF, sum = 0
4399 23:05:54.608077 7, 0xFFFF, sum = 0
4400 23:05:54.610667 8, 0x0, sum = 1
4401 23:05:54.611160 9, 0x0, sum = 2
4402 23:05:54.613808 10, 0x0, sum = 3
4403 23:05:54.614403 11, 0x0, sum = 4
4404 23:05:54.614880 best_step = 9
4405 23:05:54.615229
4406 23:05:54.617280 ==
4407 23:05:54.617762 Dram Type= 6, Freq= 0, CH_0, rank 1
4408 23:05:54.623697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4409 23:05:54.624314 ==
4410 23:05:54.624740 RX Vref Scan: 0
4411 23:05:54.625069
4412 23:05:54.627287 RX Vref 0 -> 0, step: 1
4413 23:05:54.627709
4414 23:05:54.630242 RX Delay -195 -> 252, step: 8
4415 23:05:54.637000 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4416 23:05:54.640711 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4417 23:05:54.644175 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4418 23:05:54.647040 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4419 23:05:54.650063 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4420 23:05:54.656993 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4421 23:05:54.660440 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4422 23:05:54.663524 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4423 23:05:54.666625 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4424 23:05:54.673316 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4425 23:05:54.676551 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4426 23:05:54.679973 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4427 23:05:54.683280 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4428 23:05:54.689397 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4429 23:05:54.692682 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4430 23:05:54.696110 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4431 23:05:54.696686 ==
4432 23:05:54.699478 Dram Type= 6, Freq= 0, CH_0, rank 1
4433 23:05:54.702690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4434 23:05:54.706070 ==
4435 23:05:54.706499 DQS Delay:
4436 23:05:54.706868 DQS0 = 0, DQS1 = 0
4437 23:05:54.709658 DQM Delay:
4438 23:05:54.710077 DQM0 = 41, DQM1 = 37
4439 23:05:54.712807 DQ Delay:
4440 23:05:54.716079 DQ0 =36, DQ1 =44, DQ2 =36, DQ3 =40
4441 23:05:54.716499 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4442 23:05:54.719561 DQ8 =28, DQ9 =20, DQ10 =40, DQ11 =28
4443 23:05:54.725673 DQ12 =44, DQ13 =44, DQ14 =48, DQ15 =44
4444 23:05:54.726107
4445 23:05:54.726502
4446 23:05:54.732490 [DQSOSCAuto] RK1, (LSB)MR18= 0x6115, (MSB)MR19= 0x808, tDQSOscB0 = 405 ps tDQSOscB1 = 391 ps
4447 23:05:54.735870 CH0 RK1: MR19=808, MR18=6115
4448 23:05:54.742383 CH0_RK1: MR19=0x808, MR18=0x6115, DQSOSC=391, MR23=63, INC=171, DEC=114
4449 23:05:54.745323 [RxdqsGatingPostProcess] freq 600
4450 23:05:54.748848 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4451 23:05:54.752215 Pre-setting of DQS Precalculation
4452 23:05:54.758764 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4453 23:05:54.759188 ==
4454 23:05:54.762224 Dram Type= 6, Freq= 0, CH_1, rank 0
4455 23:05:54.765327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4456 23:05:54.765791 ==
4457 23:05:54.772108 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4458 23:05:54.778349 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4459 23:05:54.781728 [CA 0] Center 36 (6~66) winsize 61
4460 23:05:54.785077 [CA 1] Center 35 (5~66) winsize 62
4461 23:05:54.788426 [CA 2] Center 34 (4~65) winsize 62
4462 23:05:54.791954 [CA 3] Center 33 (3~64) winsize 62
4463 23:05:54.794949 [CA 4] Center 34 (4~64) winsize 61
4464 23:05:54.798427 [CA 5] Center 33 (3~64) winsize 62
4465 23:05:54.798919
4466 23:05:54.802262 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4467 23:05:54.802686
4468 23:05:54.804754 [CATrainingPosCal] consider 1 rank data
4469 23:05:54.808289 u2DelayCellTimex100 = 270/100 ps
4470 23:05:54.811652 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4471 23:05:54.815047 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4472 23:05:54.818158 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4473 23:05:54.821631 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4474 23:05:54.825027 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4475 23:05:54.828335 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4476 23:05:54.828765
4477 23:05:54.834674 CA PerBit enable=1, Macro0, CA PI delay=33
4478 23:05:54.835101
4479 23:05:54.835470 [CBTSetCACLKResult] CA Dly = 33
4480 23:05:54.837908 CS Dly: 5 (0~36)
4481 23:05:54.838330 ==
4482 23:05:54.841183 Dram Type= 6, Freq= 0, CH_1, rank 1
4483 23:05:54.844814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4484 23:05:54.845383 ==
4485 23:05:54.851195 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4486 23:05:54.858311 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4487 23:05:54.861087 [CA 0] Center 35 (5~66) winsize 62
4488 23:05:54.864163 [CA 1] Center 36 (6~66) winsize 61
4489 23:05:54.867799 [CA 2] Center 34 (4~65) winsize 62
4490 23:05:54.870930 [CA 3] Center 34 (3~65) winsize 63
4491 23:05:54.874500 [CA 4] Center 34 (4~65) winsize 62
4492 23:05:54.877304 [CA 5] Center 34 (3~65) winsize 63
4493 23:05:54.877806
4494 23:05:54.880463 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4495 23:05:54.880886
4496 23:05:54.883877 [CATrainingPosCal] consider 2 rank data
4497 23:05:54.887316 u2DelayCellTimex100 = 270/100 ps
4498 23:05:54.890383 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4499 23:05:54.893865 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4500 23:05:54.897497 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4501 23:05:54.900373 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4502 23:05:54.907532 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4503 23:05:54.910510 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4504 23:05:54.910940
4505 23:05:54.913743 CA PerBit enable=1, Macro0, CA PI delay=33
4506 23:05:54.914194
4507 23:05:54.916825 [CBTSetCACLKResult] CA Dly = 33
4508 23:05:54.917297 CS Dly: 5 (0~36)
4509 23:05:54.917724
4510 23:05:54.920344 ----->DramcWriteLeveling(PI) begin...
4511 23:05:54.920778 ==
4512 23:05:54.923416 Dram Type= 6, Freq= 0, CH_1, rank 0
4513 23:05:54.930606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4514 23:05:54.931041 ==
4515 23:05:54.933946 Write leveling (Byte 0): 32 => 32
4516 23:05:54.936912 Write leveling (Byte 1): 32 => 32
4517 23:05:54.937334 DramcWriteLeveling(PI) end<-----
4518 23:05:54.940006
4519 23:05:54.940426 ==
4520 23:05:54.943305 Dram Type= 6, Freq= 0, CH_1, rank 0
4521 23:05:54.946574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4522 23:05:54.947003 ==
4523 23:05:54.950304 [Gating] SW mode calibration
4524 23:05:54.956506 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4525 23:05:54.959834 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4526 23:05:54.966751 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4527 23:05:54.969769 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4528 23:05:54.973669 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4529 23:05:54.979742 0 9 12 | B1->B0 | 3131 2f2f | 1 0 | (1 1) (0 0)
4530 23:05:54.983139 0 9 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4531 23:05:54.986456 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4532 23:05:54.992875 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4533 23:05:54.996202 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4534 23:05:54.999819 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4535 23:05:55.005945 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4536 23:05:55.010052 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4537 23:05:55.012590 0 10 12 | B1->B0 | 3433 3a3a | 1 0 | (0 0) (0 0)
4538 23:05:55.019584 0 10 16 | B1->B0 | 4343 4646 | 0 0 | (1 1) (0 0)
4539 23:05:55.022426 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4540 23:05:55.025739 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4541 23:05:55.032308 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4542 23:05:55.035846 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4543 23:05:55.038883 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4544 23:05:55.045524 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4545 23:05:55.049382 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4546 23:05:55.052289 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4547 23:05:55.058783 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4548 23:05:55.062080 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4549 23:05:55.066151 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4550 23:05:55.071879 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4551 23:05:55.075472 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4552 23:05:55.078969 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4553 23:05:55.085349 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4554 23:05:55.088737 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4555 23:05:55.092061 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4556 23:05:55.098763 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4557 23:05:55.101635 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4558 23:05:55.104807 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4559 23:05:55.111397 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4560 23:05:55.115008 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4561 23:05:55.117983 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4562 23:05:55.125114 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4563 23:05:55.127966 Total UI for P1: 0, mck2ui 16
4564 23:05:55.131188 best dqsien dly found for B0: ( 0, 13, 12)
4565 23:05:55.134370 Total UI for P1: 0, mck2ui 16
4566 23:05:55.138405 best dqsien dly found for B1: ( 0, 13, 14)
4567 23:05:55.140894 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4568 23:05:55.144351 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4569 23:05:55.144981
4570 23:05:55.147541 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4571 23:05:55.150975 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4572 23:05:55.154663 [Gating] SW calibration Done
4573 23:05:55.155269 ==
4574 23:05:55.157691 Dram Type= 6, Freq= 0, CH_1, rank 0
4575 23:05:55.161266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4576 23:05:55.161820 ==
4577 23:05:55.164323 RX Vref Scan: 0
4578 23:05:55.164869
4579 23:05:55.167686 RX Vref 0 -> 0, step: 1
4580 23:05:55.168190
4581 23:05:55.168678 RX Delay -230 -> 252, step: 16
4582 23:05:55.174379 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4583 23:05:55.177802 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4584 23:05:55.180745 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4585 23:05:55.184491 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4586 23:05:55.190986 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4587 23:05:55.193967 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4588 23:05:55.197567 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4589 23:05:55.200674 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4590 23:05:55.207505 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4591 23:05:55.210688 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4592 23:05:55.214036 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4593 23:05:55.217166 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4594 23:05:55.224401 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4595 23:05:55.227198 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4596 23:05:55.230421 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4597 23:05:55.234011 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4598 23:05:55.234545 ==
4599 23:05:55.237316 Dram Type= 6, Freq= 0, CH_1, rank 0
4600 23:05:55.244374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4601 23:05:55.244956 ==
4602 23:05:55.245348 DQS Delay:
4603 23:05:55.246796 DQS0 = 0, DQS1 = 0
4604 23:05:55.247384 DQM Delay:
4605 23:05:55.247954 DQM0 = 45, DQM1 = 37
4606 23:05:55.250435 DQ Delay:
4607 23:05:55.253708 DQ0 =49, DQ1 =41, DQ2 =41, DQ3 =41
4608 23:05:55.257109 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =41
4609 23:05:55.259876 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4610 23:05:55.263459 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4611 23:05:55.263974
4612 23:05:55.264322
4613 23:05:55.264641 ==
4614 23:05:55.266631 Dram Type= 6, Freq= 0, CH_1, rank 0
4615 23:05:55.269944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4616 23:05:55.270380 ==
4617 23:05:55.270724
4618 23:05:55.271044
4619 23:05:55.273486 TX Vref Scan disable
4620 23:05:55.276606 == TX Byte 0 ==
4621 23:05:55.280205 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4622 23:05:55.282902 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4623 23:05:55.286332 == TX Byte 1 ==
4624 23:05:55.289711 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4625 23:05:55.292973 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4626 23:05:55.293606 ==
4627 23:05:55.296298 Dram Type= 6, Freq= 0, CH_1, rank 0
4628 23:05:55.299466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4629 23:05:55.303095 ==
4630 23:05:55.303555
4631 23:05:55.303930
4632 23:05:55.304254 TX Vref Scan disable
4633 23:05:55.306953 == TX Byte 0 ==
4634 23:05:55.309975 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4635 23:05:55.316791 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4636 23:05:55.317396 == TX Byte 1 ==
4637 23:05:55.320439 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4638 23:05:55.326590 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4639 23:05:55.327103
4640 23:05:55.327465 [DATLAT]
4641 23:05:55.327791 Freq=600, CH1 RK0
4642 23:05:55.328114
4643 23:05:55.330315 DATLAT Default: 0x9
4644 23:05:55.330749 0, 0xFFFF, sum = 0
4645 23:05:55.333354 1, 0xFFFF, sum = 0
4646 23:05:55.336493 2, 0xFFFF, sum = 0
4647 23:05:55.336960 3, 0xFFFF, sum = 0
4648 23:05:55.340093 4, 0xFFFF, sum = 0
4649 23:05:55.340731 5, 0xFFFF, sum = 0
4650 23:05:55.343180 6, 0xFFFF, sum = 0
4651 23:05:55.343648 7, 0xFFFF, sum = 0
4652 23:05:55.346756 8, 0x0, sum = 1
4653 23:05:55.347354 9, 0x0, sum = 2
4654 23:05:55.350246 10, 0x0, sum = 3
4655 23:05:55.350713 11, 0x0, sum = 4
4656 23:05:55.351137 best_step = 9
4657 23:05:55.351465
4658 23:05:55.352900 ==
4659 23:05:55.356150 Dram Type= 6, Freq= 0, CH_1, rank 0
4660 23:05:55.359237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4661 23:05:55.359743 ==
4662 23:05:55.360094 RX Vref Scan: 1
4663 23:05:55.360489
4664 23:05:55.362952 RX Vref 0 -> 0, step: 1
4665 23:05:55.363461
4666 23:05:55.366208 RX Delay -195 -> 252, step: 8
4667 23:05:55.366683
4668 23:05:55.369311 Set Vref, RX VrefLevel [Byte0]: 52
4669 23:05:55.372926 [Byte1]: 60
4670 23:05:55.373355
4671 23:05:55.375960 Final RX Vref Byte 0 = 52 to rank0
4672 23:05:55.379156 Final RX Vref Byte 1 = 60 to rank0
4673 23:05:55.382106 Final RX Vref Byte 0 = 52 to rank1
4674 23:05:55.385262 Final RX Vref Byte 1 = 60 to rank1==
4675 23:05:55.388586 Dram Type= 6, Freq= 0, CH_1, rank 0
4676 23:05:55.395094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4677 23:05:55.395178 ==
4678 23:05:55.395246 DQS Delay:
4679 23:05:55.395308 DQS0 = 0, DQS1 = 0
4680 23:05:55.398818 DQM Delay:
4681 23:05:55.398900 DQM0 = 46, DQM1 = 38
4682 23:05:55.401723 DQ Delay:
4683 23:05:55.405124 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =40
4684 23:05:55.405205 DQ4 =44, DQ5 =56, DQ6 =56, DQ7 =44
4685 23:05:55.409046 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28
4686 23:05:55.415235 DQ12 =48, DQ13 =44, DQ14 =48, DQ15 =48
4687 23:05:55.415339
4688 23:05:55.415422
4689 23:05:55.421804 [DQSOSCAuto] RK0, (LSB)MR18= 0x4e33, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 395 ps
4690 23:05:55.425751 CH1 RK0: MR19=808, MR18=4E33
4691 23:05:55.431921 CH1_RK0: MR19=0x808, MR18=0x4E33, DQSOSC=395, MR23=63, INC=168, DEC=112
4692 23:05:55.432083
4693 23:05:55.434816 ----->DramcWriteLeveling(PI) begin...
4694 23:05:55.434995 ==
4695 23:05:55.438267 Dram Type= 6, Freq= 0, CH_1, rank 1
4696 23:05:55.441351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4697 23:05:55.441694 ==
4698 23:05:55.444997 Write leveling (Byte 0): 29 => 29
4699 23:05:55.448322 Write leveling (Byte 1): 29 => 29
4700 23:05:55.451645 DramcWriteLeveling(PI) end<-----
4701 23:05:55.452000
4702 23:05:55.452272 ==
4703 23:05:55.454882 Dram Type= 6, Freq= 0, CH_1, rank 1
4704 23:05:55.458373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4705 23:05:55.461919 ==
4706 23:05:55.462500 [Gating] SW mode calibration
4707 23:05:55.471420 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4708 23:05:55.474896 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4709 23:05:55.477995 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4710 23:05:55.484402 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4711 23:05:55.487937 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4712 23:05:55.491015 0 9 12 | B1->B0 | 2e2e 3333 | 1 1 | (1 0) (1 1)
4713 23:05:55.497923 0 9 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4714 23:05:55.500972 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4715 23:05:55.504382 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4716 23:05:55.510941 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4717 23:05:55.514805 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4718 23:05:55.517991 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4719 23:05:55.524365 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4720 23:05:55.527589 0 10 12 | B1->B0 | 3535 2c2c | 0 0 | (0 0) (0 0)
4721 23:05:55.530676 0 10 16 | B1->B0 | 4646 4242 | 0 1 | (0 0) (0 0)
4722 23:05:55.537227 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4723 23:05:55.540812 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4724 23:05:55.544505 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4725 23:05:55.551019 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4726 23:05:55.554016 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4727 23:05:55.557590 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4728 23:05:55.564863 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4729 23:05:55.567348 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4730 23:05:55.570402 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4731 23:05:55.577131 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4732 23:05:55.580267 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4733 23:05:55.583377 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4734 23:05:55.590145 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4735 23:05:55.593256 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4736 23:05:55.596738 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4737 23:05:55.603328 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4738 23:05:55.606304 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4739 23:05:55.609926 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4740 23:05:55.616900 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4741 23:05:55.620320 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4742 23:05:55.623049 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4743 23:05:55.629500 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4744 23:05:55.632767 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4745 23:05:55.635936 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4746 23:05:55.639191 Total UI for P1: 0, mck2ui 16
4747 23:05:55.642636 best dqsien dly found for B0: ( 0, 13, 14)
4748 23:05:55.645777 Total UI for P1: 0, mck2ui 16
4749 23:05:55.649250 best dqsien dly found for B1: ( 0, 13, 14)
4750 23:05:55.652442 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4751 23:05:55.658997 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4752 23:05:55.659421
4753 23:05:55.662544 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4754 23:05:55.665245 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4755 23:05:55.668637 [Gating] SW calibration Done
4756 23:05:55.669057 ==
4757 23:05:55.672022 Dram Type= 6, Freq= 0, CH_1, rank 1
4758 23:05:55.675166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4759 23:05:55.675628 ==
4760 23:05:55.678606 RX Vref Scan: 0
4761 23:05:55.679031
4762 23:05:55.679372 RX Vref 0 -> 0, step: 1
4763 23:05:55.679693
4764 23:05:55.681858 RX Delay -230 -> 252, step: 16
4765 23:05:55.688530 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4766 23:05:55.691563 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4767 23:05:55.695285 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4768 23:05:55.698719 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4769 23:05:55.702118 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4770 23:05:55.708430 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4771 23:05:55.711382 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4772 23:05:55.715061 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4773 23:05:55.718649 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4774 23:05:55.724641 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4775 23:05:55.728361 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4776 23:05:55.731342 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4777 23:05:55.734796 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4778 23:05:55.741372 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4779 23:05:55.744364 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4780 23:05:55.747727 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4781 23:05:55.748169 ==
4782 23:05:55.751489 Dram Type= 6, Freq= 0, CH_1, rank 1
4783 23:05:55.754787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4784 23:05:55.757713 ==
4785 23:05:55.758138 DQS Delay:
4786 23:05:55.758473 DQS0 = 0, DQS1 = 0
4787 23:05:55.761188 DQM Delay:
4788 23:05:55.761649 DQM0 = 44, DQM1 = 37
4789 23:05:55.764493 DQ Delay:
4790 23:05:55.764913 DQ0 =49, DQ1 =41, DQ2 =25, DQ3 =41
4791 23:05:55.767838 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4792 23:05:55.771236 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4793 23:05:55.774098 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4794 23:05:55.777343
4795 23:05:55.777813
4796 23:05:55.778153 ==
4797 23:05:55.780911 Dram Type= 6, Freq= 0, CH_1, rank 1
4798 23:05:55.784335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4799 23:05:55.784761 ==
4800 23:05:55.785175
4801 23:05:55.785659
4802 23:05:55.787309 TX Vref Scan disable
4803 23:05:55.787730 == TX Byte 0 ==
4804 23:05:55.793996 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4805 23:05:55.797649 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4806 23:05:55.798161 == TX Byte 1 ==
4807 23:05:55.804488 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4808 23:05:55.807774 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4809 23:05:55.808326 ==
4810 23:05:55.810684 Dram Type= 6, Freq= 0, CH_1, rank 1
4811 23:05:55.813914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4812 23:05:55.814464 ==
4813 23:05:55.814811
4814 23:05:55.815126
4815 23:05:55.817167 TX Vref Scan disable
4816 23:05:55.821296 == TX Byte 0 ==
4817 23:05:55.824022 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4818 23:05:55.827397 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4819 23:05:55.830486 == TX Byte 1 ==
4820 23:05:55.834810 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4821 23:05:55.840065 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4822 23:05:55.840756
4823 23:05:55.841273 [DATLAT]
4824 23:05:55.841912 Freq=600, CH1 RK1
4825 23:05:55.842515
4826 23:05:55.843529 DATLAT Default: 0x9
4827 23:05:55.844049 0, 0xFFFF, sum = 0
4828 23:05:55.846862 1, 0xFFFF, sum = 0
4829 23:05:55.847517 2, 0xFFFF, sum = 0
4830 23:05:55.850235 3, 0xFFFF, sum = 0
4831 23:05:55.853623 4, 0xFFFF, sum = 0
4832 23:05:55.854228 5, 0xFFFF, sum = 0
4833 23:05:55.856610 6, 0xFFFF, sum = 0
4834 23:05:55.857118 7, 0xFFFF, sum = 0
4835 23:05:55.860084 8, 0x0, sum = 1
4836 23:05:55.860669 9, 0x0, sum = 2
4837 23:05:55.861184 10, 0x0, sum = 3
4838 23:05:55.863916 11, 0x0, sum = 4
4839 23:05:55.864564 best_step = 9
4840 23:05:55.865123
4841 23:05:55.865709 ==
4842 23:05:55.866550 Dram Type= 6, Freq= 0, CH_1, rank 1
4843 23:05:55.873356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4844 23:05:55.873866 ==
4845 23:05:55.874252 RX Vref Scan: 0
4846 23:05:55.874648
4847 23:05:55.876548 RX Vref 0 -> 0, step: 1
4848 23:05:55.876982
4849 23:05:55.880152 RX Delay -195 -> 252, step: 8
4850 23:05:55.883560 iDelay=213, Bit 0, Center 48 (-99 ~ 196) 296
4851 23:05:55.889921 iDelay=213, Bit 1, Center 40 (-107 ~ 188) 296
4852 23:05:55.892923 iDelay=213, Bit 2, Center 32 (-115 ~ 180) 296
4853 23:05:55.896176 iDelay=213, Bit 3, Center 40 (-107 ~ 188) 296
4854 23:05:55.899759 iDelay=213, Bit 4, Center 44 (-107 ~ 196) 304
4855 23:05:55.905940 iDelay=213, Bit 5, Center 56 (-91 ~ 204) 296
4856 23:05:55.909741 iDelay=213, Bit 6, Center 60 (-91 ~ 212) 304
4857 23:05:55.913152 iDelay=213, Bit 7, Center 44 (-107 ~ 196) 304
4858 23:05:55.916174 iDelay=213, Bit 8, Center 24 (-131 ~ 180) 312
4859 23:05:55.922940 iDelay=213, Bit 9, Center 24 (-131 ~ 180) 312
4860 23:05:55.926136 iDelay=213, Bit 10, Center 40 (-115 ~ 196) 312
4861 23:05:55.929286 iDelay=213, Bit 11, Center 28 (-123 ~ 180) 304
4862 23:05:55.932707 iDelay=213, Bit 12, Center 48 (-107 ~ 204) 312
4863 23:05:55.939936 iDelay=213, Bit 13, Center 48 (-107 ~ 204) 312
4864 23:05:55.942348 iDelay=213, Bit 14, Center 48 (-107 ~ 204) 312
4865 23:05:55.945476 iDelay=213, Bit 15, Center 48 (-107 ~ 204) 312
4866 23:05:55.945962 ==
4867 23:05:55.949130 Dram Type= 6, Freq= 0, CH_1, rank 1
4868 23:05:55.951978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4869 23:05:55.955467 ==
4870 23:05:55.955971 DQS Delay:
4871 23:05:55.956336 DQS0 = 0, DQS1 = 0
4872 23:05:55.959046 DQM Delay:
4873 23:05:55.959474 DQM0 = 45, DQM1 = 38
4874 23:05:55.961903 DQ Delay:
4875 23:05:55.962334 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4876 23:05:55.965482 DQ4 =44, DQ5 =56, DQ6 =60, DQ7 =44
4877 23:05:55.968597 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28
4878 23:05:55.971936 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =48
4879 23:05:55.975228
4880 23:05:55.975746
4881 23:05:55.982003 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f24, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 400 ps
4882 23:05:55.985201 CH1 RK1: MR19=808, MR18=2F24
4883 23:05:55.991865 CH1_RK1: MR19=0x808, MR18=0x2F24, DQSOSC=400, MR23=63, INC=163, DEC=109
4884 23:05:55.995280 [RxdqsGatingPostProcess] freq 600
4885 23:05:55.999099 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4886 23:05:56.001707 Pre-setting of DQS Precalculation
4887 23:05:56.008377 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4888 23:05:56.015024 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4889 23:05:56.022150 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4890 23:05:56.022722
4891 23:05:56.023099
4892 23:05:56.025199 [Calibration Summary] 1200 Mbps
4893 23:05:56.026026 CH 0, Rank 0
4894 23:05:56.028191 SW Impedance : PASS
4895 23:05:56.031117 DUTY Scan : NO K
4896 23:05:56.031839 ZQ Calibration : PASS
4897 23:05:56.034802 Jitter Meter : NO K
4898 23:05:56.037636 CBT Training : PASS
4899 23:05:56.038156 Write leveling : PASS
4900 23:05:56.041371 RX DQS gating : PASS
4901 23:05:56.045353 RX DQ/DQS(RDDQC) : PASS
4902 23:05:56.045881 TX DQ/DQS : PASS
4903 23:05:56.048012 RX DATLAT : PASS
4904 23:05:56.051010 RX DQ/DQS(Engine): PASS
4905 23:05:56.051568 TX OE : NO K
4906 23:05:56.052005 All Pass.
4907 23:05:56.054060
4908 23:05:56.054666 CH 0, Rank 1
4909 23:05:56.057965 SW Impedance : PASS
4910 23:05:56.058527 DUTY Scan : NO K
4911 23:05:56.061278 ZQ Calibration : PASS
4912 23:05:56.064369 Jitter Meter : NO K
4913 23:05:56.064993 CBT Training : PASS
4914 23:05:56.067653 Write leveling : PASS
4915 23:05:56.068333 RX DQS gating : PASS
4916 23:05:56.071048 RX DQ/DQS(RDDQC) : PASS
4917 23:05:56.074273 TX DQ/DQS : PASS
4918 23:05:56.074925 RX DATLAT : PASS
4919 23:05:56.077337 RX DQ/DQS(Engine): PASS
4920 23:05:56.081398 TX OE : NO K
4921 23:05:56.082024 All Pass.
4922 23:05:56.082600
4923 23:05:56.083177 CH 1, Rank 0
4924 23:05:56.084235 SW Impedance : PASS
4925 23:05:56.087472 DUTY Scan : NO K
4926 23:05:56.088057 ZQ Calibration : PASS
4927 23:05:56.090898 Jitter Meter : NO K
4928 23:05:56.094443 CBT Training : PASS
4929 23:05:56.095069 Write leveling : PASS
4930 23:05:56.097946 RX DQS gating : PASS
4931 23:05:56.100702 RX DQ/DQS(RDDQC) : PASS
4932 23:05:56.101265 TX DQ/DQS : PASS
4933 23:05:56.104259 RX DATLAT : PASS
4934 23:05:56.107329 RX DQ/DQS(Engine): PASS
4935 23:05:56.107980 TX OE : NO K
4936 23:05:56.110879 All Pass.
4937 23:05:56.111436
4938 23:05:56.111970 CH 1, Rank 1
4939 23:05:56.113860 SW Impedance : PASS
4940 23:05:56.114491 DUTY Scan : NO K
4941 23:05:56.117195 ZQ Calibration : PASS
4942 23:05:56.120200 Jitter Meter : NO K
4943 23:05:56.120816 CBT Training : PASS
4944 23:05:56.123687 Write leveling : PASS
4945 23:05:56.126717 RX DQS gating : PASS
4946 23:05:56.127284 RX DQ/DQS(RDDQC) : PASS
4947 23:05:56.130215 TX DQ/DQS : PASS
4948 23:05:56.130862 RX DATLAT : PASS
4949 23:05:56.133375 RX DQ/DQS(Engine): PASS
4950 23:05:56.136676 TX OE : NO K
4951 23:05:56.137278 All Pass.
4952 23:05:56.137870
4953 23:05:56.139865 DramC Write-DBI off
4954 23:05:56.143278 PER_BANK_REFRESH: Hybrid Mode
4955 23:05:56.143913 TX_TRACKING: ON
4956 23:05:56.153147 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4957 23:05:56.156524 [FAST_K] Save calibration result to emmc
4958 23:05:56.160119 dramc_set_vcore_voltage set vcore to 662500
4959 23:05:56.163598 Read voltage for 933, 3
4960 23:05:56.164128 Vio18 = 0
4961 23:05:56.164477 Vcore = 662500
4962 23:05:56.166874 Vdram = 0
4963 23:05:56.167404 Vddq = 0
4964 23:05:56.167750 Vmddr = 0
4965 23:05:56.173604 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4966 23:05:56.176155 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4967 23:05:56.179766 MEM_TYPE=3, freq_sel=17
4968 23:05:56.183556 sv_algorithm_assistance_LP4_1600
4969 23:05:56.186284 ============ PULL DRAM RESETB DOWN ============
4970 23:05:56.189781 ========== PULL DRAM RESETB DOWN end =========
4971 23:05:56.195992 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4972 23:05:56.199168 ===================================
4973 23:05:56.202542 LPDDR4 DRAM CONFIGURATION
4974 23:05:56.202976 ===================================
4975 23:05:56.205823 EX_ROW_EN[0] = 0x0
4976 23:05:56.209558 EX_ROW_EN[1] = 0x0
4977 23:05:56.209986 LP4Y_EN = 0x0
4978 23:05:56.212866 WORK_FSP = 0x0
4979 23:05:56.213297 WL = 0x3
4980 23:05:56.215546 RL = 0x3
4981 23:05:56.216124 BL = 0x2
4982 23:05:56.218967 RPST = 0x0
4983 23:05:56.219388 RD_PRE = 0x0
4984 23:05:56.222235 WR_PRE = 0x1
4985 23:05:56.222760 WR_PST = 0x0
4986 23:05:56.225571 DBI_WR = 0x0
4987 23:05:56.225997 DBI_RD = 0x0
4988 23:05:56.229266 OTF = 0x1
4989 23:05:56.232240 ===================================
4990 23:05:56.235434 ===================================
4991 23:05:56.235857 ANA top config
4992 23:05:56.238781 ===================================
4993 23:05:56.241962 DLL_ASYNC_EN = 0
4994 23:05:56.245512 ALL_SLAVE_EN = 1
4995 23:05:56.248894 NEW_RANK_MODE = 1
4996 23:05:56.249355 DLL_IDLE_MODE = 1
4997 23:05:56.252091 LP45_APHY_COMB_EN = 1
4998 23:05:56.255353 TX_ODT_DIS = 1
4999 23:05:56.259196 NEW_8X_MODE = 1
5000 23:05:56.262089 ===================================
5001 23:05:56.265190 ===================================
5002 23:05:56.268960 data_rate = 1866
5003 23:05:56.272022 CKR = 1
5004 23:05:56.272479 DQ_P2S_RATIO = 8
5005 23:05:56.275173 ===================================
5006 23:05:56.278798 CA_P2S_RATIO = 8
5007 23:05:56.281343 DQ_CA_OPEN = 0
5008 23:05:56.284839 DQ_SEMI_OPEN = 0
5009 23:05:56.288059 CA_SEMI_OPEN = 0
5010 23:05:56.291672 CA_FULL_RATE = 0
5011 23:05:56.292206 DQ_CKDIV4_EN = 1
5012 23:05:56.294896 CA_CKDIV4_EN = 1
5013 23:05:56.298347 CA_PREDIV_EN = 0
5014 23:05:56.301464 PH8_DLY = 0
5015 23:05:56.304482 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
5016 23:05:56.308030 DQ_AAMCK_DIV = 4
5017 23:05:56.308473 CA_AAMCK_DIV = 4
5018 23:05:56.311105 CA_ADMCK_DIV = 4
5019 23:05:56.314612 DQ_TRACK_CA_EN = 0
5020 23:05:56.317991 CA_PICK = 933
5021 23:05:56.321139 CA_MCKIO = 933
5022 23:05:56.324944 MCKIO_SEMI = 0
5023 23:05:56.327559 PLL_FREQ = 3732
5024 23:05:56.331263 DQ_UI_PI_RATIO = 32
5025 23:05:56.331686 CA_UI_PI_RATIO = 0
5026 23:05:56.334540 ===================================
5027 23:05:56.337925 ===================================
5028 23:05:56.341558 memory_type:LPDDR4
5029 23:05:56.344685 GP_NUM : 10
5030 23:05:56.345215 SRAM_EN : 1
5031 23:05:56.347796 MD32_EN : 0
5032 23:05:56.351478 ===================================
5033 23:05:56.353940 [ANA_INIT] >>>>>>>>>>>>>>
5034 23:05:56.357260 <<<<<< [CONFIGURE PHASE]: ANA_TX
5035 23:05:56.361094 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5036 23:05:56.364141 ===================================
5037 23:05:56.364909 data_rate = 1866,PCW = 0X8f00
5038 23:05:56.367480 ===================================
5039 23:05:56.374104 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5040 23:05:56.377149 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5041 23:05:56.383865 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5042 23:05:56.387355 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5043 23:05:56.390573 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5044 23:05:56.393993 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5045 23:05:56.397512 [ANA_INIT] flow start
5046 23:05:56.400758 [ANA_INIT] PLL >>>>>>>>
5047 23:05:56.401320 [ANA_INIT] PLL <<<<<<<<
5048 23:05:56.404040 [ANA_INIT] MIDPI >>>>>>>>
5049 23:05:56.406856 [ANA_INIT] MIDPI <<<<<<<<
5050 23:05:56.407325 [ANA_INIT] DLL >>>>>>>>
5051 23:05:56.410490 [ANA_INIT] flow end
5052 23:05:56.413885 ============ LP4 DIFF to SE enter ============
5053 23:05:56.420519 ============ LP4 DIFF to SE exit ============
5054 23:05:56.421080 [ANA_INIT] <<<<<<<<<<<<<
5055 23:05:56.423931 [Flow] Enable top DCM control >>>>>
5056 23:05:56.426460 [Flow] Enable top DCM control <<<<<
5057 23:05:56.429664 Enable DLL master slave shuffle
5058 23:05:56.436485 ==============================================================
5059 23:05:56.436967 Gating Mode config
5060 23:05:56.443396 ==============================================================
5061 23:05:56.446851 Config description:
5062 23:05:56.456951 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5063 23:05:56.462862 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5064 23:05:56.466057 SELPH_MODE 0: By rank 1: By Phase
5065 23:05:56.472912 ==============================================================
5066 23:05:56.476856 GAT_TRACK_EN = 1
5067 23:05:56.477330 RX_GATING_MODE = 2
5068 23:05:56.479536 RX_GATING_TRACK_MODE = 2
5069 23:05:56.482695 SELPH_MODE = 1
5070 23:05:56.485947 PICG_EARLY_EN = 1
5071 23:05:56.489828 VALID_LAT_VALUE = 1
5072 23:05:56.496100 ==============================================================
5073 23:05:56.499056 Enter into Gating configuration >>>>
5074 23:05:56.502335 Exit from Gating configuration <<<<
5075 23:05:56.505787 Enter into DVFS_PRE_config >>>>>
5076 23:05:56.516048 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5077 23:05:56.519053 Exit from DVFS_PRE_config <<<<<
5078 23:05:56.522462 Enter into PICG configuration >>>>
5079 23:05:56.525852 Exit from PICG configuration <<<<
5080 23:05:56.528688 [RX_INPUT] configuration >>>>>
5081 23:05:56.531923 [RX_INPUT] configuration <<<<<
5082 23:05:56.535667 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5083 23:05:56.541893 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5084 23:05:56.548263 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5085 23:05:56.555169 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5086 23:05:56.558853 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5087 23:05:56.565061 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5088 23:05:56.571856 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5089 23:05:56.575567 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5090 23:05:56.579075 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5091 23:05:56.582380 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5092 23:05:56.585134 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5093 23:05:56.591652 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5094 23:05:56.595374 ===================================
5095 23:05:56.598631 LPDDR4 DRAM CONFIGURATION
5096 23:05:56.601697 ===================================
5097 23:05:56.602265 EX_ROW_EN[0] = 0x0
5098 23:05:56.604972 EX_ROW_EN[1] = 0x0
5099 23:05:56.605505 LP4Y_EN = 0x0
5100 23:05:56.608470 WORK_FSP = 0x0
5101 23:05:56.608943 WL = 0x3
5102 23:05:56.611373 RL = 0x3
5103 23:05:56.611844 BL = 0x2
5104 23:05:56.614536 RPST = 0x0
5105 23:05:56.615004 RD_PRE = 0x0
5106 23:05:56.618324 WR_PRE = 0x1
5107 23:05:56.621796 WR_PST = 0x0
5108 23:05:56.622371 DBI_WR = 0x0
5109 23:05:56.624460 DBI_RD = 0x0
5110 23:05:56.624929 OTF = 0x1
5111 23:05:56.628303 ===================================
5112 23:05:56.631022 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5113 23:05:56.634433 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5114 23:05:56.640824 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5115 23:05:56.644429 ===================================
5116 23:05:56.647668 LPDDR4 DRAM CONFIGURATION
5117 23:05:56.651740 ===================================
5118 23:05:56.652312 EX_ROW_EN[0] = 0x10
5119 23:05:56.654345 EX_ROW_EN[1] = 0x0
5120 23:05:56.654819 LP4Y_EN = 0x0
5121 23:05:56.657506 WORK_FSP = 0x0
5122 23:05:56.657983 WL = 0x3
5123 23:05:56.660743 RL = 0x3
5124 23:05:56.661313 BL = 0x2
5125 23:05:56.664245 RPST = 0x0
5126 23:05:56.667165 RD_PRE = 0x0
5127 23:05:56.667642 WR_PRE = 0x1
5128 23:05:56.670793 WR_PST = 0x0
5129 23:05:56.671360 DBI_WR = 0x0
5130 23:05:56.673660 DBI_RD = 0x0
5131 23:05:56.674129 OTF = 0x1
5132 23:05:56.677504 ===================================
5133 23:05:56.683612 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5134 23:05:56.687945 nWR fixed to 30
5135 23:05:56.691312 [ModeRegInit_LP4] CH0 RK0
5136 23:05:56.691880 [ModeRegInit_LP4] CH0 RK1
5137 23:05:56.694089 [ModeRegInit_LP4] CH1 RK0
5138 23:05:56.697839 [ModeRegInit_LP4] CH1 RK1
5139 23:05:56.698308 match AC timing 9
5140 23:05:56.704872 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5141 23:05:56.707534 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5142 23:05:56.710531 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5143 23:05:56.717572 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5144 23:05:56.721095 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5145 23:05:56.721681 ==
5146 23:05:56.723926 Dram Type= 6, Freq= 0, CH_0, rank 0
5147 23:05:56.727200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5148 23:05:56.727731 ==
5149 23:05:56.733904 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5150 23:05:56.740526 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5151 23:05:56.744022 [CA 0] Center 37 (7~68) winsize 62
5152 23:05:56.746726 [CA 1] Center 37 (7~68) winsize 62
5153 23:05:56.750046 [CA 2] Center 34 (4~65) winsize 62
5154 23:05:56.753784 [CA 3] Center 35 (5~65) winsize 61
5155 23:05:56.756769 [CA 4] Center 33 (3~64) winsize 62
5156 23:05:56.759890 [CA 5] Center 33 (4~63) winsize 60
5157 23:05:56.760315
5158 23:05:56.763961 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5159 23:05:56.764492
5160 23:05:56.766451 [CATrainingPosCal] consider 1 rank data
5161 23:05:56.769725 u2DelayCellTimex100 = 270/100 ps
5162 23:05:56.773291 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5163 23:05:56.776460 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5164 23:05:56.779851 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5165 23:05:56.786455 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5166 23:05:56.790103 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5167 23:05:56.793445 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5168 23:05:56.793937
5169 23:05:56.796662 CA PerBit enable=1, Macro0, CA PI delay=33
5170 23:05:56.797136
5171 23:05:56.800036 [CBTSetCACLKResult] CA Dly = 33
5172 23:05:56.800603 CS Dly: 7 (0~38)
5173 23:05:56.800985 ==
5174 23:05:56.802823 Dram Type= 6, Freq= 0, CH_0, rank 1
5175 23:05:56.809705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5176 23:05:56.810267 ==
5177 23:05:56.812872 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5178 23:05:56.819573 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5179 23:05:56.822691 [CA 0] Center 37 (7~68) winsize 62
5180 23:05:56.826514 [CA 1] Center 37 (7~68) winsize 62
5181 23:05:56.829588 [CA 2] Center 34 (4~65) winsize 62
5182 23:05:56.832610 [CA 3] Center 34 (4~65) winsize 62
5183 23:05:56.835815 [CA 4] Center 33 (3~64) winsize 62
5184 23:05:56.839760 [CA 5] Center 33 (3~63) winsize 61
5185 23:05:56.840326
5186 23:05:56.842473 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5187 23:05:56.842943
5188 23:05:56.845843 [CATrainingPosCal] consider 2 rank data
5189 23:05:56.849632 u2DelayCellTimex100 = 270/100 ps
5190 23:05:56.852439 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5191 23:05:56.859050 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5192 23:05:56.862779 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5193 23:05:56.865664 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5194 23:05:56.869050 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5195 23:05:56.872582 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5196 23:05:56.873005
5197 23:05:56.875457 CA PerBit enable=1, Macro0, CA PI delay=33
5198 23:05:56.875882
5199 23:05:56.878614 [CBTSetCACLKResult] CA Dly = 33
5200 23:05:56.881797 CS Dly: 7 (0~39)
5201 23:05:56.882221
5202 23:05:56.885388 ----->DramcWriteLeveling(PI) begin...
5203 23:05:56.885852 ==
5204 23:05:56.888262 Dram Type= 6, Freq= 0, CH_0, rank 0
5205 23:05:56.892308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5206 23:05:56.892736 ==
5207 23:05:56.895198 Write leveling (Byte 0): 31 => 31
5208 23:05:56.899408 Write leveling (Byte 1): 30 => 30
5209 23:05:56.901938 DramcWriteLeveling(PI) end<-----
5210 23:05:56.902440
5211 23:05:56.902911 ==
5212 23:05:56.905110 Dram Type= 6, Freq= 0, CH_0, rank 0
5213 23:05:56.908346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5214 23:05:56.908745 ==
5215 23:05:56.911455 [Gating] SW mode calibration
5216 23:05:56.918540 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5217 23:05:56.924743 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5218 23:05:56.928216 0 14 0 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
5219 23:05:56.931405 0 14 4 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
5220 23:05:56.938249 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5221 23:05:56.941232 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5222 23:05:56.944709 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5223 23:05:56.951372 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5224 23:05:56.955127 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5225 23:05:56.958089 0 14 28 | B1->B0 | 3434 2727 | 1 0 | (1 1) (0 1)
5226 23:05:56.964438 0 15 0 | B1->B0 | 3232 2323 | 0 0 | (0 0) (0 0)
5227 23:05:56.967623 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5228 23:05:56.970854 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5229 23:05:56.977441 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5230 23:05:56.981024 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5231 23:05:56.987133 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5232 23:05:56.990427 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5233 23:05:56.993717 0 15 28 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
5234 23:05:57.000707 1 0 0 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
5235 23:05:57.003331 1 0 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5236 23:05:57.006694 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5237 23:05:57.013152 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5238 23:05:57.016741 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5239 23:05:57.020141 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5240 23:05:57.026623 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5241 23:05:57.029918 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5242 23:05:57.032795 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5243 23:05:57.039835 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5244 23:05:57.042837 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5245 23:05:57.046270 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5246 23:05:57.052479 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5247 23:05:57.056551 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5248 23:05:57.059699 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5249 23:05:57.065976 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5250 23:05:57.069380 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5251 23:05:57.072807 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5252 23:05:57.079406 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5253 23:05:57.082050 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5254 23:05:57.085704 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5255 23:05:57.092227 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5256 23:05:57.095395 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5257 23:05:57.098666 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5258 23:05:57.102238 Total UI for P1: 0, mck2ui 16
5259 23:05:57.105298 best dqsien dly found for B0: ( 1, 2, 26)
5260 23:05:57.112116 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5261 23:05:57.115113 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5262 23:05:57.118546 Total UI for P1: 0, mck2ui 16
5263 23:05:57.122215 best dqsien dly found for B1: ( 1, 2, 30)
5264 23:05:57.125388 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5265 23:05:57.128408 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5266 23:05:57.128491
5267 23:05:57.131584 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5268 23:05:57.134926 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5269 23:05:57.138148 [Gating] SW calibration Done
5270 23:05:57.138231 ==
5271 23:05:57.141414 Dram Type= 6, Freq= 0, CH_0, rank 0
5272 23:05:57.145139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5273 23:05:57.148298 ==
5274 23:05:57.148412 RX Vref Scan: 0
5275 23:05:57.148492
5276 23:05:57.151356 RX Vref 0 -> 0, step: 1
5277 23:05:57.151470
5278 23:05:57.154474 RX Delay -80 -> 252, step: 8
5279 23:05:57.158114 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5280 23:05:57.161322 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5281 23:05:57.164528 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5282 23:05:57.168251 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5283 23:05:57.174391 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5284 23:05:57.177452 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5285 23:05:57.181713 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5286 23:05:57.184313 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5287 23:05:57.187574 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5288 23:05:57.190977 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5289 23:05:57.197350 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5290 23:05:57.201018 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5291 23:05:57.204239 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5292 23:05:57.207721 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5293 23:05:57.211314 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5294 23:05:57.217970 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5295 23:05:57.218286 ==
5296 23:05:57.220931 Dram Type= 6, Freq= 0, CH_0, rank 0
5297 23:05:57.224239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5298 23:05:57.224632 ==
5299 23:05:57.225128 DQS Delay:
5300 23:05:57.227717 DQS0 = 0, DQS1 = 0
5301 23:05:57.228140 DQM Delay:
5302 23:05:57.231308 DQM0 = 97, DQM1 = 85
5303 23:05:57.231733 DQ Delay:
5304 23:05:57.233968 DQ0 =99, DQ1 =99, DQ2 =91, DQ3 =91
5305 23:05:57.237885 DQ4 =99, DQ5 =83, DQ6 =107, DQ7 =107
5306 23:05:57.240735 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =79
5307 23:05:57.244356 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5308 23:05:57.244826
5309 23:05:57.245354
5310 23:05:57.245830 ==
5311 23:05:57.247501 Dram Type= 6, Freq= 0, CH_0, rank 0
5312 23:05:57.251269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5313 23:05:57.254386 ==
5314 23:05:57.254861
5315 23:05:57.255300
5316 23:05:57.255715 TX Vref Scan disable
5317 23:05:57.257967 == TX Byte 0 ==
5318 23:05:57.260422 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5319 23:05:57.267111 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5320 23:05:57.267710 == TX Byte 1 ==
5321 23:05:57.270427 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5322 23:05:57.276957 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5323 23:05:57.277385 ==
5324 23:05:57.280258 Dram Type= 6, Freq= 0, CH_0, rank 0
5325 23:05:57.283459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5326 23:05:57.283901 ==
5327 23:05:57.284339
5328 23:05:57.284753
5329 23:05:57.286774 TX Vref Scan disable
5330 23:05:57.287210 == TX Byte 0 ==
5331 23:05:57.293339 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5332 23:05:57.297027 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5333 23:05:57.299944 == TX Byte 1 ==
5334 23:05:57.303126 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5335 23:05:57.306636 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5336 23:05:57.307081
5337 23:05:57.307517 [DATLAT]
5338 23:05:57.310267 Freq=933, CH0 RK0
5339 23:05:57.310736
5340 23:05:57.311177 DATLAT Default: 0xd
5341 23:05:57.313005 0, 0xFFFF, sum = 0
5342 23:05:57.316412 1, 0xFFFF, sum = 0
5343 23:05:57.316846 2, 0xFFFF, sum = 0
5344 23:05:57.319869 3, 0xFFFF, sum = 0
5345 23:05:57.320301 4, 0xFFFF, sum = 0
5346 23:05:57.322955 5, 0xFFFF, sum = 0
5347 23:05:57.323388 6, 0xFFFF, sum = 0
5348 23:05:57.326105 7, 0xFFFF, sum = 0
5349 23:05:57.326591 8, 0xFFFF, sum = 0
5350 23:05:57.329279 9, 0xFFFF, sum = 0
5351 23:05:57.329784 10, 0x0, sum = 1
5352 23:05:57.333359 11, 0x0, sum = 2
5353 23:05:57.333859 12, 0x0, sum = 3
5354 23:05:57.335721 13, 0x0, sum = 4
5355 23:05:57.336150 best_step = 11
5356 23:05:57.336493
5357 23:05:57.336827 ==
5358 23:05:57.339683 Dram Type= 6, Freq= 0, CH_0, rank 0
5359 23:05:57.342906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5360 23:05:57.346594 ==
5361 23:05:57.347030 RX Vref Scan: 1
5362 23:05:57.347384
5363 23:05:57.349280 RX Vref 0 -> 0, step: 1
5364 23:05:57.349786
5365 23:05:57.350134 RX Delay -69 -> 252, step: 4
5366 23:05:57.352331
5367 23:05:57.352884 Set Vref, RX VrefLevel [Byte0]: 61
5368 23:05:57.356107 [Byte1]: 49
5369 23:05:57.361336
5370 23:05:57.361669 Final RX Vref Byte 0 = 61 to rank0
5371 23:05:57.364811 Final RX Vref Byte 1 = 49 to rank0
5372 23:05:57.367448 Final RX Vref Byte 0 = 61 to rank1
5373 23:05:57.370655 Final RX Vref Byte 1 = 49 to rank1==
5374 23:05:57.374166 Dram Type= 6, Freq= 0, CH_0, rank 0
5375 23:05:57.380572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5376 23:05:57.380888 ==
5377 23:05:57.381151 DQS Delay:
5378 23:05:57.384119 DQS0 = 0, DQS1 = 0
5379 23:05:57.384418 DQM Delay:
5380 23:05:57.384657 DQM0 = 97, DQM1 = 84
5381 23:05:57.387595 DQ Delay:
5382 23:05:57.391225 DQ0 =96, DQ1 =98, DQ2 =94, DQ3 =92
5383 23:05:57.394215 DQ4 =98, DQ5 =88, DQ6 =106, DQ7 =106
5384 23:05:57.397230 DQ8 =78, DQ9 =74, DQ10 =86, DQ11 =78
5385 23:05:57.400519 DQ12 =88, DQ13 =86, DQ14 =96, DQ15 =92
5386 23:05:57.400906
5387 23:05:57.401256
5388 23:05:57.407463 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f15, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 407 ps
5389 23:05:57.410527 CH0 RK0: MR19=505, MR18=2F15
5390 23:05:57.417216 CH0_RK0: MR19=0x505, MR18=0x2F15, DQSOSC=407, MR23=63, INC=65, DEC=43
5391 23:05:57.417651
5392 23:05:57.420543 ----->DramcWriteLeveling(PI) begin...
5393 23:05:57.420935 ==
5394 23:05:57.424168 Dram Type= 6, Freq= 0, CH_0, rank 1
5395 23:05:57.426991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5396 23:05:57.427398 ==
5397 23:05:57.430495 Write leveling (Byte 0): 33 => 33
5398 23:05:57.433516 Write leveling (Byte 1): 32 => 32
5399 23:05:57.436919 DramcWriteLeveling(PI) end<-----
5400 23:05:57.437307
5401 23:05:57.437665 ==
5402 23:05:57.440198 Dram Type= 6, Freq= 0, CH_0, rank 1
5403 23:05:57.443556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5404 23:05:57.446939 ==
5405 23:05:57.447438 [Gating] SW mode calibration
5406 23:05:57.456658 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5407 23:05:57.460458 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5408 23:05:57.463479 0 14 0 | B1->B0 | 2b2b 3131 | 1 1 | (0 0) (0 0)
5409 23:05:57.470374 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5410 23:05:57.473579 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5411 23:05:57.477331 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5412 23:05:57.483192 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5413 23:05:57.486405 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5414 23:05:57.489978 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5415 23:05:57.496320 0 14 28 | B1->B0 | 3333 3030 | 1 1 | (1 1) (1 1)
5416 23:05:57.500072 0 15 0 | B1->B0 | 2f2f 2525 | 0 0 | (1 1) (0 0)
5417 23:05:57.502585 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5418 23:05:57.509825 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5419 23:05:57.512631 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5420 23:05:57.516166 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5421 23:05:57.522525 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5422 23:05:57.526417 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5423 23:05:57.529146 0 15 28 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
5424 23:05:57.535846 1 0 0 | B1->B0 | 3d3d 4444 | 0 1 | (1 1) (0 0)
5425 23:05:57.538895 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5426 23:05:57.542187 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5427 23:05:57.548928 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5428 23:05:57.552255 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5429 23:05:57.555791 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5430 23:05:57.562090 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5431 23:05:57.565134 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5432 23:05:57.568647 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5433 23:05:57.575293 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5434 23:05:57.578510 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5435 23:05:57.581983 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5436 23:05:57.588484 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5437 23:05:57.592210 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5438 23:05:57.598486 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5439 23:05:57.601438 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5440 23:05:57.604573 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5441 23:05:57.611497 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5442 23:05:57.614438 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5443 23:05:57.618046 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5444 23:05:57.624815 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5445 23:05:57.628149 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5446 23:05:57.631231 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5447 23:05:57.637299 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5448 23:05:57.640844 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5449 23:05:57.643953 Total UI for P1: 0, mck2ui 16
5450 23:05:57.647357 best dqsien dly found for B0: ( 1, 2, 30)
5451 23:05:57.651037 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5452 23:05:57.654241 Total UI for P1: 0, mck2ui 16
5453 23:05:57.657205 best dqsien dly found for B1: ( 1, 3, 0)
5454 23:05:57.660797 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5455 23:05:57.663938 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5456 23:05:57.664380
5457 23:05:57.667392 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5458 23:05:57.673810 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5459 23:05:57.674340 [Gating] SW calibration Done
5460 23:05:57.674688 ==
5461 23:05:57.677432 Dram Type= 6, Freq= 0, CH_0, rank 1
5462 23:05:57.684149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5463 23:05:57.684696 ==
5464 23:05:57.685072 RX Vref Scan: 0
5465 23:05:57.685402
5466 23:05:57.686953 RX Vref 0 -> 0, step: 1
5467 23:05:57.687409
5468 23:05:57.690830 RX Delay -80 -> 252, step: 8
5469 23:05:57.694220 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5470 23:05:57.697066 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5471 23:05:57.700614 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5472 23:05:57.703597 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5473 23:05:57.710414 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5474 23:05:57.714033 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5475 23:05:57.717359 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5476 23:05:57.720479 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5477 23:05:57.723276 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5478 23:05:57.730037 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5479 23:05:57.732880 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5480 23:05:57.736541 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5481 23:05:57.739404 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5482 23:05:57.743434 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5483 23:05:57.749882 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5484 23:05:57.752822 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5485 23:05:57.753377 ==
5486 23:05:57.756313 Dram Type= 6, Freq= 0, CH_0, rank 1
5487 23:05:57.759740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5488 23:05:57.760321 ==
5489 23:05:57.762520 DQS Delay:
5490 23:05:57.762944 DQS0 = 0, DQS1 = 0
5491 23:05:57.763287 DQM Delay:
5492 23:05:57.765916 DQM0 = 97, DQM1 = 87
5493 23:05:57.766376 DQ Delay:
5494 23:05:57.769577 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =91
5495 23:05:57.772821 DQ4 =99, DQ5 =83, DQ6 =107, DQ7 =107
5496 23:05:57.776020 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =79
5497 23:05:57.779218 DQ12 =91, DQ13 =95, DQ14 =95, DQ15 =91
5498 23:05:57.779668
5499 23:05:57.780121
5500 23:05:57.780548 ==
5501 23:05:57.782554 Dram Type= 6, Freq= 0, CH_0, rank 1
5502 23:05:57.789106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5503 23:05:57.789619 ==
5504 23:05:57.790068
5505 23:05:57.790398
5506 23:05:57.790709 TX Vref Scan disable
5507 23:05:57.793124 == TX Byte 0 ==
5508 23:05:57.795906 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5509 23:05:57.802717 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5510 23:05:57.803252 == TX Byte 1 ==
5511 23:05:57.806164 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5512 23:05:57.812730 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5513 23:05:57.813292 ==
5514 23:05:57.815824 Dram Type= 6, Freq= 0, CH_0, rank 1
5515 23:05:57.819552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5516 23:05:57.820128 ==
5517 23:05:57.820510
5518 23:05:57.820859
5519 23:05:57.823065 TX Vref Scan disable
5520 23:05:57.823634 == TX Byte 0 ==
5521 23:05:57.829095 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5522 23:05:57.832810 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5523 23:05:57.836060 == TX Byte 1 ==
5524 23:05:57.838919 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5525 23:05:57.842937 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5526 23:05:57.843585
5527 23:05:57.844002 [DATLAT]
5528 23:05:57.845394 Freq=933, CH0 RK1
5529 23:05:57.845974
5530 23:05:57.846369 DATLAT Default: 0xb
5531 23:05:57.848645 0, 0xFFFF, sum = 0
5532 23:05:57.851932 1, 0xFFFF, sum = 0
5533 23:05:57.852372 2, 0xFFFF, sum = 0
5534 23:05:57.855648 3, 0xFFFF, sum = 0
5535 23:05:57.856186 4, 0xFFFF, sum = 0
5536 23:05:57.858568 5, 0xFFFF, sum = 0
5537 23:05:57.859004 6, 0xFFFF, sum = 0
5538 23:05:57.861950 7, 0xFFFF, sum = 0
5539 23:05:57.862392 8, 0xFFFF, sum = 0
5540 23:05:57.865579 9, 0xFFFF, sum = 0
5541 23:05:57.866018 10, 0x0, sum = 1
5542 23:05:57.868626 11, 0x0, sum = 2
5543 23:05:57.869161 12, 0x0, sum = 3
5544 23:05:57.871845 13, 0x0, sum = 4
5545 23:05:57.872385 best_step = 11
5546 23:05:57.872732
5547 23:05:57.873046 ==
5548 23:05:57.875581 Dram Type= 6, Freq= 0, CH_0, rank 1
5549 23:05:57.878400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5550 23:05:57.881873 ==
5551 23:05:57.882424 RX Vref Scan: 0
5552 23:05:57.882885
5553 23:05:57.885077 RX Vref 0 -> 0, step: 1
5554 23:05:57.885667
5555 23:05:57.888229 RX Delay -61 -> 252, step: 4
5556 23:05:57.891757 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5557 23:05:57.894923 iDelay=203, Bit 1, Center 96 (-1 ~ 194) 196
5558 23:05:57.901980 iDelay=203, Bit 2, Center 90 (-1 ~ 182) 184
5559 23:05:57.905054 iDelay=203, Bit 3, Center 92 (-5 ~ 190) 196
5560 23:05:57.908303 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5561 23:05:57.911447 iDelay=203, Bit 5, Center 86 (-9 ~ 182) 192
5562 23:05:57.914701 iDelay=203, Bit 6, Center 106 (11 ~ 202) 192
5563 23:05:57.917838 iDelay=203, Bit 7, Center 104 (11 ~ 198) 188
5564 23:05:57.925573 iDelay=203, Bit 8, Center 78 (-13 ~ 170) 184
5565 23:05:57.928269 iDelay=203, Bit 9, Center 74 (-17 ~ 166) 184
5566 23:05:57.931624 iDelay=203, Bit 10, Center 86 (-9 ~ 182) 192
5567 23:05:57.935065 iDelay=203, Bit 11, Center 80 (-9 ~ 170) 180
5568 23:05:57.937887 iDelay=203, Bit 12, Center 92 (-1 ~ 186) 188
5569 23:05:57.944661 iDelay=203, Bit 13, Center 92 (-5 ~ 190) 196
5570 23:05:57.947910 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5571 23:05:57.951081 iDelay=203, Bit 15, Center 92 (-1 ~ 186) 188
5572 23:05:57.951660 ==
5573 23:05:57.954177 Dram Type= 6, Freq= 0, CH_0, rank 1
5574 23:05:57.958061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5575 23:05:57.958646 ==
5576 23:05:57.961039 DQS Delay:
5577 23:05:57.961639 DQS0 = 0, DQS1 = 0
5578 23:05:57.964407 DQM Delay:
5579 23:05:57.964982 DQM0 = 95, DQM1 = 86
5580 23:05:57.965374 DQ Delay:
5581 23:05:57.967669 DQ0 =92, DQ1 =96, DQ2 =90, DQ3 =92
5582 23:05:57.970750 DQ4 =96, DQ5 =86, DQ6 =106, DQ7 =104
5583 23:05:57.974139 DQ8 =78, DQ9 =74, DQ10 =86, DQ11 =80
5584 23:05:57.977582 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =92
5585 23:05:57.978055
5586 23:05:57.981105
5587 23:05:57.987712 [DQSOSCAuto] RK1, (LSB)MR18= 0x2afb, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 408 ps
5588 23:05:57.990491 CH0 RK1: MR19=504, MR18=2AFB
5589 23:05:57.997013 CH0_RK1: MR19=0x504, MR18=0x2AFB, DQSOSC=408, MR23=63, INC=65, DEC=43
5590 23:05:58.000684 [RxdqsGatingPostProcess] freq 933
5591 23:05:58.003867 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5592 23:05:58.006867 best DQS0 dly(2T, 0.5T) = (0, 10)
5593 23:05:58.010397 best DQS1 dly(2T, 0.5T) = (0, 10)
5594 23:05:58.013547 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5595 23:05:58.017065 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5596 23:05:58.020518 best DQS0 dly(2T, 0.5T) = (0, 10)
5597 23:05:58.023668 best DQS1 dly(2T, 0.5T) = (0, 11)
5598 23:05:58.027390 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5599 23:05:58.030313 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5600 23:05:58.033445 Pre-setting of DQS Precalculation
5601 23:05:58.036638 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5602 23:05:58.037133 ==
5603 23:05:58.039816 Dram Type= 6, Freq= 0, CH_1, rank 0
5604 23:05:58.046686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5605 23:05:58.047263 ==
5606 23:05:58.050058 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5607 23:05:58.056665 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5608 23:05:58.059890 [CA 0] Center 36 (6~67) winsize 62
5609 23:05:58.063277 [CA 1] Center 36 (6~67) winsize 62
5610 23:05:58.066690 [CA 2] Center 34 (4~65) winsize 62
5611 23:05:58.069815 [CA 3] Center 33 (3~64) winsize 62
5612 23:05:58.073128 [CA 4] Center 34 (4~64) winsize 61
5613 23:05:58.076251 [CA 5] Center 33 (3~64) winsize 62
5614 23:05:58.076724
5615 23:05:58.079568 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5616 23:05:58.080041
5617 23:05:58.083504 [CATrainingPosCal] consider 1 rank data
5618 23:05:58.086370 u2DelayCellTimex100 = 270/100 ps
5619 23:05:58.090096 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5620 23:05:58.093605 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5621 23:05:58.099532 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5622 23:05:58.102717 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5623 23:05:58.106271 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5624 23:05:58.109860 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5625 23:05:58.110331
5626 23:05:58.112703 CA PerBit enable=1, Macro0, CA PI delay=33
5627 23:05:58.113172
5628 23:05:58.116014 [CBTSetCACLKResult] CA Dly = 33
5629 23:05:58.116438 CS Dly: 6 (0~37)
5630 23:05:58.119677 ==
5631 23:05:58.122764 Dram Type= 6, Freq= 0, CH_1, rank 1
5632 23:05:58.126290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5633 23:05:58.126725 ==
5634 23:05:58.129299 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5635 23:05:58.135761 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5636 23:05:58.139916 [CA 0] Center 36 (6~67) winsize 62
5637 23:05:58.142700 [CA 1] Center 36 (6~67) winsize 62
5638 23:05:58.146850 [CA 2] Center 34 (3~65) winsize 63
5639 23:05:58.149290 [CA 3] Center 34 (3~65) winsize 63
5640 23:05:58.152742 [CA 4] Center 34 (3~65) winsize 63
5641 23:05:58.156419 [CA 5] Center 33 (3~64) winsize 62
5642 23:05:58.156997
5643 23:05:58.159154 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5644 23:05:58.159634
5645 23:05:58.162433 [CATrainingPosCal] consider 2 rank data
5646 23:05:58.165719 u2DelayCellTimex100 = 270/100 ps
5647 23:05:58.169541 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5648 23:05:58.175733 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5649 23:05:58.179097 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5650 23:05:58.182856 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5651 23:05:58.185643 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5652 23:05:58.189198 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5653 23:05:58.189861
5654 23:05:58.192345 CA PerBit enable=1, Macro0, CA PI delay=33
5655 23:05:58.192824
5656 23:05:58.195759 [CBTSetCACLKResult] CA Dly = 33
5657 23:05:58.199242 CS Dly: 7 (0~39)
5658 23:05:58.199814
5659 23:05:58.202309 ----->DramcWriteLeveling(PI) begin...
5660 23:05:58.202891 ==
5661 23:05:58.205556 Dram Type= 6, Freq= 0, CH_1, rank 0
5662 23:05:58.209316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5663 23:05:58.209956 ==
5664 23:05:58.212423 Write leveling (Byte 0): 28 => 28
5665 23:05:58.215561 Write leveling (Byte 1): 28 => 28
5666 23:05:58.219082 DramcWriteLeveling(PI) end<-----
5667 23:05:58.219684
5668 23:05:58.220083 ==
5669 23:05:58.222192 Dram Type= 6, Freq= 0, CH_1, rank 0
5670 23:05:58.225850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5671 23:05:58.226427 ==
5672 23:05:58.228832 [Gating] SW mode calibration
5673 23:05:58.235334 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5674 23:05:58.241946 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5675 23:05:58.245287 0 14 0 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
5676 23:05:58.248308 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5677 23:05:58.255574 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5678 23:05:58.258299 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5679 23:05:58.261257 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5680 23:05:58.268447 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5681 23:05:58.271286 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 0)
5682 23:05:58.275215 0 14 28 | B1->B0 | 2e2e 2929 | 1 0 | (1 0) (0 0)
5683 23:05:58.281805 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5684 23:05:58.285057 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5685 23:05:58.288395 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5686 23:05:58.294806 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5687 23:05:58.297793 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5688 23:05:58.301288 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5689 23:05:58.307654 0 15 24 | B1->B0 | 2323 2827 | 0 1 | (0 0) (1 1)
5690 23:05:58.311390 0 15 28 | B1->B0 | 4343 3b3b | 1 0 | (0 0) (0 0)
5691 23:05:58.314526 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5692 23:05:58.321024 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5693 23:05:58.324994 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5694 23:05:58.328108 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5695 23:05:58.334208 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5696 23:05:58.337517 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5697 23:05:58.341072 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5698 23:05:58.347260 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5699 23:05:58.350912 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5700 23:05:58.354144 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5701 23:05:58.360359 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5702 23:05:58.364074 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5703 23:05:58.366972 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5704 23:05:58.373770 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5705 23:05:58.376822 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5706 23:05:58.380526 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5707 23:05:58.386599 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5708 23:05:58.389979 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5709 23:05:58.393479 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5710 23:05:58.400446 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5711 23:05:58.403441 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5712 23:05:58.406893 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5713 23:05:58.413490 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5714 23:05:58.417303 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5715 23:05:58.420090 Total UI for P1: 0, mck2ui 16
5716 23:05:58.423657 best dqsien dly found for B0: ( 1, 2, 24)
5717 23:05:58.426815 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5718 23:05:58.433264 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5719 23:05:58.436301 Total UI for P1: 0, mck2ui 16
5720 23:05:58.440034 best dqsien dly found for B1: ( 1, 2, 30)
5721 23:05:58.442667 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5722 23:05:58.446358 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5723 23:05:58.446866
5724 23:05:58.449360 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5725 23:05:58.453231 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5726 23:05:58.456033 [Gating] SW calibration Done
5727 23:05:58.456505 ==
5728 23:05:58.459593 Dram Type= 6, Freq= 0, CH_1, rank 0
5729 23:05:58.462959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5730 23:05:58.463537 ==
5731 23:05:58.466569 RX Vref Scan: 0
5732 23:05:58.467043
5733 23:05:58.469087 RX Vref 0 -> 0, step: 1
5734 23:05:58.469610
5735 23:05:58.469995 RX Delay -80 -> 252, step: 8
5736 23:05:58.475920 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5737 23:05:58.478952 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5738 23:05:58.482424 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5739 23:05:58.485811 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5740 23:05:58.488982 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5741 23:05:58.495874 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5742 23:05:58.498883 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5743 23:05:58.501720 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5744 23:05:58.505093 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5745 23:05:58.508025 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5746 23:05:58.514523 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5747 23:05:58.517954 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5748 23:05:58.521196 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5749 23:05:58.524318 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5750 23:05:58.528244 iDelay=208, Bit 14, Center 95 (-8 ~ 199) 208
5751 23:05:58.534284 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5752 23:05:58.534381 ==
5753 23:05:58.537532 Dram Type= 6, Freq= 0, CH_1, rank 0
5754 23:05:58.541262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5755 23:05:58.541399 ==
5756 23:05:58.541523 DQS Delay:
5757 23:05:58.544277 DQS0 = 0, DQS1 = 0
5758 23:05:58.544390 DQM Delay:
5759 23:05:58.548202 DQM0 = 101, DQM1 = 90
5760 23:05:58.548409 DQ Delay:
5761 23:05:58.551094 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =99
5762 23:05:58.555294 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =99
5763 23:05:58.557405 DQ8 =75, DQ9 =83, DQ10 =91, DQ11 =79
5764 23:05:58.560842 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =99
5765 23:05:58.561083
5766 23:05:58.561220
5767 23:05:58.561341 ==
5768 23:05:58.563999 Dram Type= 6, Freq= 0, CH_1, rank 0
5769 23:05:58.567228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5770 23:05:58.570675 ==
5771 23:05:58.570971
5772 23:05:58.571186
5773 23:05:58.571378 TX Vref Scan disable
5774 23:05:58.574022 == TX Byte 0 ==
5775 23:05:58.577455 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5776 23:05:58.581215 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5777 23:05:58.584289 == TX Byte 1 ==
5778 23:05:58.587487 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5779 23:05:58.590576 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5780 23:05:58.594440 ==
5781 23:05:58.597549 Dram Type= 6, Freq= 0, CH_1, rank 0
5782 23:05:58.601014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5783 23:05:58.601773 ==
5784 23:05:58.602170
5785 23:05:58.602528
5786 23:05:58.603626 TX Vref Scan disable
5787 23:05:58.604100 == TX Byte 0 ==
5788 23:05:58.610527 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5789 23:05:58.613817 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5790 23:05:58.614390 == TX Byte 1 ==
5791 23:05:58.620571 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5792 23:05:58.623885 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5793 23:05:58.624466
5794 23:05:58.624848 [DATLAT]
5795 23:05:58.627291 Freq=933, CH1 RK0
5796 23:05:58.627863
5797 23:05:58.628241 DATLAT Default: 0xd
5798 23:05:58.630150 0, 0xFFFF, sum = 0
5799 23:05:58.630713 1, 0xFFFF, sum = 0
5800 23:05:58.633977 2, 0xFFFF, sum = 0
5801 23:05:58.636816 3, 0xFFFF, sum = 0
5802 23:05:58.637297 4, 0xFFFF, sum = 0
5803 23:05:58.640072 5, 0xFFFF, sum = 0
5804 23:05:58.640555 6, 0xFFFF, sum = 0
5805 23:05:58.643987 7, 0xFFFF, sum = 0
5806 23:05:58.644534 8, 0xFFFF, sum = 0
5807 23:05:58.646536 9, 0xFFFF, sum = 0
5808 23:05:58.647270 10, 0x0, sum = 1
5809 23:05:58.649860 11, 0x0, sum = 2
5810 23:05:58.650475 12, 0x0, sum = 3
5811 23:05:58.653044 13, 0x0, sum = 4
5812 23:05:58.653664 best_step = 11
5813 23:05:58.654113
5814 23:05:58.654702 ==
5815 23:05:58.656046 Dram Type= 6, Freq= 0, CH_1, rank 0
5816 23:05:58.660179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5817 23:05:58.660634 ==
5818 23:05:58.662860 RX Vref Scan: 1
5819 23:05:58.663329
5820 23:05:58.666532 RX Vref 0 -> 0, step: 1
5821 23:05:58.667126
5822 23:05:58.667641 RX Delay -69 -> 252, step: 4
5823 23:05:58.668184
5824 23:05:58.669930 Set Vref, RX VrefLevel [Byte0]: 52
5825 23:05:58.672835 [Byte1]: 60
5826 23:05:58.677782
5827 23:05:58.678337 Final RX Vref Byte 0 = 52 to rank0
5828 23:05:58.681155 Final RX Vref Byte 1 = 60 to rank0
5829 23:05:58.684497 Final RX Vref Byte 0 = 52 to rank1
5830 23:05:58.687512 Final RX Vref Byte 1 = 60 to rank1==
5831 23:05:58.690958 Dram Type= 6, Freq= 0, CH_1, rank 0
5832 23:05:58.697884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5833 23:05:58.698342 ==
5834 23:05:58.698687 DQS Delay:
5835 23:05:58.700746 DQS0 = 0, DQS1 = 0
5836 23:05:58.701274 DQM Delay:
5837 23:05:58.701663 DQM0 = 100, DQM1 = 95
5838 23:05:58.703913 DQ Delay:
5839 23:05:58.707620 DQ0 =104, DQ1 =96, DQ2 =92, DQ3 =96
5840 23:05:58.710553 DQ4 =98, DQ5 =110, DQ6 =110, DQ7 =96
5841 23:05:58.713809 DQ8 =86, DQ9 =88, DQ10 =94, DQ11 =86
5842 23:05:58.717245 DQ12 =102, DQ13 =102, DQ14 =102, DQ15 =102
5843 23:05:58.717878
5844 23:05:58.718343
5845 23:05:58.723806 [DQSOSCAuto] RK0, (LSB)MR18= 0x1808, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 414 ps
5846 23:05:58.727510 CH1 RK0: MR19=505, MR18=1808
5847 23:05:58.734041 CH1_RK0: MR19=0x505, MR18=0x1808, DQSOSC=414, MR23=63, INC=63, DEC=42
5848 23:05:58.734567
5849 23:05:58.737172 ----->DramcWriteLeveling(PI) begin...
5850 23:05:58.737651 ==
5851 23:05:58.740221 Dram Type= 6, Freq= 0, CH_1, rank 1
5852 23:05:58.743563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5853 23:05:58.747133 ==
5854 23:05:58.747558 Write leveling (Byte 0): 29 => 29
5855 23:05:58.750306 Write leveling (Byte 1): 29 => 29
5856 23:05:58.754318 DramcWriteLeveling(PI) end<-----
5857 23:05:58.754767
5858 23:05:58.755143 ==
5859 23:05:58.756819 Dram Type= 6, Freq= 0, CH_1, rank 1
5860 23:05:58.763654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5861 23:05:58.764227 ==
5862 23:05:58.767150 [Gating] SW mode calibration
5863 23:05:58.773555 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5864 23:05:58.777146 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5865 23:05:58.783317 0 14 0 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
5866 23:05:58.786648 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5867 23:05:58.789748 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5868 23:05:58.796369 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5869 23:05:58.799950 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5870 23:05:58.802835 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5871 23:05:58.809748 0 14 24 | B1->B0 | 3030 3434 | 0 1 | (0 1) (1 1)
5872 23:05:58.812915 0 14 28 | B1->B0 | 2525 2f2f | 0 1 | (0 0) (1 0)
5873 23:05:58.816424 0 15 0 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5874 23:05:58.823122 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5875 23:05:58.826529 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5876 23:05:58.829823 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5877 23:05:58.836313 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5878 23:05:58.839821 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5879 23:05:58.842728 0 15 24 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
5880 23:05:58.849597 0 15 28 | B1->B0 | 3b3b 3535 | 0 1 | (0 0) (0 0)
5881 23:05:58.852676 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5882 23:05:58.856450 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5883 23:05:58.862491 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5884 23:05:58.865628 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5885 23:05:58.869524 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5886 23:05:58.876300 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5887 23:05:58.878906 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5888 23:05:58.882388 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5889 23:05:58.888670 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5890 23:05:58.891907 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5891 23:05:58.895190 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5892 23:05:58.901690 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5893 23:05:58.905326 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5894 23:05:58.908208 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5895 23:05:58.915177 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5896 23:05:58.918151 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5897 23:05:58.921721 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5898 23:05:58.928188 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5899 23:05:58.931492 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5900 23:05:58.934693 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5901 23:05:58.941020 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5902 23:05:58.944397 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5903 23:05:58.947808 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5904 23:05:58.954477 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5905 23:05:58.955082 Total UI for P1: 0, mck2ui 16
5906 23:05:58.961029 best dqsien dly found for B1: ( 1, 2, 26)
5907 23:05:58.964477 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5908 23:05:58.967405 Total UI for P1: 0, mck2ui 16
5909 23:05:58.971073 best dqsien dly found for B0: ( 1, 2, 28)
5910 23:05:58.974093 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5911 23:05:58.977909 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5912 23:05:58.978332
5913 23:05:58.981891 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5914 23:05:58.984063 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5915 23:05:58.987462 [Gating] SW calibration Done
5916 23:05:58.987988 ==
5917 23:05:58.990998 Dram Type= 6, Freq= 0, CH_1, rank 1
5918 23:05:58.997563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5919 23:05:58.998093 ==
5920 23:05:58.998511 RX Vref Scan: 0
5921 23:05:58.998843
5922 23:05:59.000310 RX Vref 0 -> 0, step: 1
5923 23:05:59.000800
5924 23:05:59.003648 RX Delay -80 -> 252, step: 8
5925 23:05:59.007962 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5926 23:05:59.010124 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5927 23:05:59.013512 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5928 23:05:59.017032 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5929 23:05:59.023994 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5930 23:05:59.026722 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5931 23:05:59.030200 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5932 23:05:59.033717 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5933 23:05:59.036812 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5934 23:05:59.043238 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5935 23:05:59.046013 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5936 23:05:59.049794 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5937 23:05:59.052649 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5938 23:05:59.056302 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5939 23:05:59.062771 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5940 23:05:59.066077 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5941 23:05:59.066503 ==
5942 23:05:59.069809 Dram Type= 6, Freq= 0, CH_1, rank 1
5943 23:05:59.073052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5944 23:05:59.073534 ==
5945 23:05:59.073892 DQS Delay:
5946 23:05:59.076321 DQS0 = 0, DQS1 = 0
5947 23:05:59.076744 DQM Delay:
5948 23:05:59.079498 DQM0 = 100, DQM1 = 92
5949 23:05:59.079940 DQ Delay:
5950 23:05:59.082665 DQ0 =103, DQ1 =99, DQ2 =87, DQ3 =99
5951 23:05:59.086125 DQ4 =99, DQ5 =115, DQ6 =107, DQ7 =95
5952 23:05:59.089241 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5953 23:05:59.092522 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =99
5954 23:05:59.092982
5955 23:05:59.093456
5956 23:05:59.093884 ==
5957 23:05:59.096365 Dram Type= 6, Freq= 0, CH_1, rank 1
5958 23:05:59.102488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5959 23:05:59.102932 ==
5960 23:05:59.103378
5961 23:05:59.103798
5962 23:05:59.104212 TX Vref Scan disable
5963 23:05:59.105994 == TX Byte 0 ==
5964 23:05:59.109157 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5965 23:05:59.115927 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5966 23:05:59.116355 == TX Byte 1 ==
5967 23:05:59.119305 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5968 23:05:59.126369 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5969 23:05:59.126813 ==
5970 23:05:59.129102 Dram Type= 6, Freq= 0, CH_1, rank 1
5971 23:05:59.132263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5972 23:05:59.132714 ==
5973 23:05:59.133067
5974 23:05:59.133444
5975 23:05:59.135517 TX Vref Scan disable
5976 23:05:59.138753 == TX Byte 0 ==
5977 23:05:59.142356 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5978 23:05:59.145693 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5979 23:05:59.148690 == TX Byte 1 ==
5980 23:05:59.152356 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5981 23:05:59.155315 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5982 23:05:59.155624
5983 23:05:59.155869 [DATLAT]
5984 23:05:59.158794 Freq=933, CH1 RK1
5985 23:05:59.159027
5986 23:05:59.162005 DATLAT Default: 0xb
5987 23:05:59.162234 0, 0xFFFF, sum = 0
5988 23:05:59.164828 1, 0xFFFF, sum = 0
5989 23:05:59.165015 2, 0xFFFF, sum = 0
5990 23:05:59.168456 3, 0xFFFF, sum = 0
5991 23:05:59.168645 4, 0xFFFF, sum = 0
5992 23:05:59.171595 5, 0xFFFF, sum = 0
5993 23:05:59.171785 6, 0xFFFF, sum = 0
5994 23:05:59.175088 7, 0xFFFF, sum = 0
5995 23:05:59.175276 8, 0xFFFF, sum = 0
5996 23:05:59.178190 9, 0xFFFF, sum = 0
5997 23:05:59.178379 10, 0x0, sum = 1
5998 23:05:59.181853 11, 0x0, sum = 2
5999 23:05:59.182042 12, 0x0, sum = 3
6000 23:05:59.184871 13, 0x0, sum = 4
6001 23:05:59.184956 best_step = 11
6002 23:05:59.185022
6003 23:05:59.185084 ==
6004 23:05:59.188462 Dram Type= 6, Freq= 0, CH_1, rank 1
6005 23:05:59.191165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6006 23:05:59.194570 ==
6007 23:05:59.194653 RX Vref Scan: 0
6008 23:05:59.194721
6009 23:05:59.197759 RX Vref 0 -> 0, step: 1
6010 23:05:59.197842
6011 23:05:59.201185 RX Delay -61 -> 252, step: 4
6012 23:05:59.204453 iDelay=207, Bit 0, Center 106 (19 ~ 194) 176
6013 23:05:59.208253 iDelay=207, Bit 1, Center 94 (7 ~ 182) 176
6014 23:05:59.214307 iDelay=207, Bit 2, Center 90 (3 ~ 178) 176
6015 23:05:59.217423 iDelay=207, Bit 3, Center 98 (15 ~ 182) 168
6016 23:05:59.220887 iDelay=207, Bit 4, Center 98 (7 ~ 190) 184
6017 23:05:59.224160 iDelay=207, Bit 5, Center 112 (23 ~ 202) 180
6018 23:05:59.227526 iDelay=207, Bit 6, Center 114 (23 ~ 206) 184
6019 23:05:59.230757 iDelay=207, Bit 7, Center 98 (7 ~ 190) 184
6020 23:05:59.237687 iDelay=207, Bit 8, Center 84 (-5 ~ 174) 180
6021 23:05:59.240743 iDelay=207, Bit 9, Center 84 (-5 ~ 174) 180
6022 23:05:59.243857 iDelay=207, Bit 10, Center 92 (-1 ~ 186) 188
6023 23:05:59.247090 iDelay=207, Bit 11, Center 86 (-5 ~ 178) 184
6024 23:05:59.250497 iDelay=207, Bit 12, Center 104 (15 ~ 194) 180
6025 23:05:59.257094 iDelay=207, Bit 13, Center 98 (7 ~ 190) 184
6026 23:05:59.260392 iDelay=207, Bit 14, Center 102 (15 ~ 190) 176
6027 23:05:59.263707 iDelay=207, Bit 15, Center 100 (7 ~ 194) 188
6028 23:05:59.263792 ==
6029 23:05:59.267367 Dram Type= 6, Freq= 0, CH_1, rank 1
6030 23:05:59.270323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6031 23:05:59.270408 ==
6032 23:05:59.273688 DQS Delay:
6033 23:05:59.273772 DQS0 = 0, DQS1 = 0
6034 23:05:59.277115 DQM Delay:
6035 23:05:59.277198 DQM0 = 101, DQM1 = 93
6036 23:05:59.277266 DQ Delay:
6037 23:05:59.280181 DQ0 =106, DQ1 =94, DQ2 =90, DQ3 =98
6038 23:05:59.283993 DQ4 =98, DQ5 =112, DQ6 =114, DQ7 =98
6039 23:05:59.286720 DQ8 =84, DQ9 =84, DQ10 =92, DQ11 =86
6040 23:05:59.293369 DQ12 =104, DQ13 =98, DQ14 =102, DQ15 =100
6041 23:05:59.293475
6042 23:05:59.293542
6043 23:05:59.299979 [DQSOSCAuto] RK1, (LSB)MR18= 0x801, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 419 ps
6044 23:05:59.302968 CH1 RK1: MR19=505, MR18=801
6045 23:05:59.309906 CH1_RK1: MR19=0x505, MR18=0x801, DQSOSC=419, MR23=63, INC=61, DEC=41
6046 23:05:59.312881 [RxdqsGatingPostProcess] freq 933
6047 23:05:59.316202 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6048 23:05:59.319872 best DQS0 dly(2T, 0.5T) = (0, 10)
6049 23:05:59.323090 best DQS1 dly(2T, 0.5T) = (0, 10)
6050 23:05:59.326375 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6051 23:05:59.329745 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6052 23:05:59.332979 best DQS0 dly(2T, 0.5T) = (0, 10)
6053 23:05:59.336227 best DQS1 dly(2T, 0.5T) = (0, 10)
6054 23:05:59.339843 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6055 23:05:59.342862 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6056 23:05:59.346544 Pre-setting of DQS Precalculation
6057 23:05:59.350170 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6058 23:05:59.359612 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6059 23:05:59.366190 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6060 23:05:59.366336
6061 23:05:59.366447
6062 23:05:59.369293 [Calibration Summary] 1866 Mbps
6063 23:05:59.369466 CH 0, Rank 0
6064 23:05:59.373184 SW Impedance : PASS
6065 23:05:59.373361 DUTY Scan : NO K
6066 23:05:59.376274 ZQ Calibration : PASS
6067 23:05:59.379704 Jitter Meter : NO K
6068 23:05:59.379983 CBT Training : PASS
6069 23:05:59.382730 Write leveling : PASS
6070 23:05:59.385927 RX DQS gating : PASS
6071 23:05:59.386173 RX DQ/DQS(RDDQC) : PASS
6072 23:05:59.388901 TX DQ/DQS : PASS
6073 23:05:59.392205 RX DATLAT : PASS
6074 23:05:59.392289 RX DQ/DQS(Engine): PASS
6075 23:05:59.395563 TX OE : NO K
6076 23:05:59.395648 All Pass.
6077 23:05:59.395715
6078 23:05:59.398997 CH 0, Rank 1
6079 23:05:59.399080 SW Impedance : PASS
6080 23:05:59.402410 DUTY Scan : NO K
6081 23:05:59.405266 ZQ Calibration : PASS
6082 23:05:59.405349 Jitter Meter : NO K
6083 23:05:59.408556 CBT Training : PASS
6084 23:05:59.412068 Write leveling : PASS
6085 23:05:59.412178 RX DQS gating : PASS
6086 23:05:59.415230 RX DQ/DQS(RDDQC) : PASS
6087 23:05:59.418638 TX DQ/DQS : PASS
6088 23:05:59.418713 RX DATLAT : PASS
6089 23:05:59.422038 RX DQ/DQS(Engine): PASS
6090 23:05:59.422113 TX OE : NO K
6091 23:05:59.425279 All Pass.
6092 23:05:59.425356
6093 23:05:59.425426 CH 1, Rank 0
6094 23:05:59.428577 SW Impedance : PASS
6095 23:05:59.428646 DUTY Scan : NO K
6096 23:05:59.432103 ZQ Calibration : PASS
6097 23:05:59.435200 Jitter Meter : NO K
6098 23:05:59.435290 CBT Training : PASS
6099 23:05:59.438573 Write leveling : PASS
6100 23:05:59.441972 RX DQS gating : PASS
6101 23:05:59.442069 RX DQ/DQS(RDDQC) : PASS
6102 23:05:59.445209 TX DQ/DQS : PASS
6103 23:05:59.448537 RX DATLAT : PASS
6104 23:05:59.448644 RX DQ/DQS(Engine): PASS
6105 23:05:59.451653 TX OE : NO K
6106 23:05:59.451768 All Pass.
6107 23:05:59.451859
6108 23:05:59.455637 CH 1, Rank 1
6109 23:05:59.456164 SW Impedance : PASS
6110 23:05:59.458636 DUTY Scan : NO K
6111 23:05:59.462103 ZQ Calibration : PASS
6112 23:05:59.462585 Jitter Meter : NO K
6113 23:05:59.465495 CBT Training : PASS
6114 23:05:59.468364 Write leveling : PASS
6115 23:05:59.468821 RX DQS gating : PASS
6116 23:05:59.472075 RX DQ/DQS(RDDQC) : PASS
6117 23:05:59.475110 TX DQ/DQS : PASS
6118 23:05:59.475538 RX DATLAT : PASS
6119 23:05:59.478387 RX DQ/DQS(Engine): PASS
6120 23:05:59.481694 TX OE : NO K
6121 23:05:59.482142 All Pass.
6122 23:05:59.482481
6123 23:05:59.482796 DramC Write-DBI off
6124 23:05:59.485201 PER_BANK_REFRESH: Hybrid Mode
6125 23:05:59.488019 TX_TRACKING: ON
6126 23:05:59.494853 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6127 23:05:59.498594 [FAST_K] Save calibration result to emmc
6128 23:05:59.504656 dramc_set_vcore_voltage set vcore to 650000
6129 23:05:59.505115 Read voltage for 400, 6
6130 23:05:59.508389 Vio18 = 0
6131 23:05:59.508767 Vcore = 650000
6132 23:05:59.509141 Vdram = 0
6133 23:05:59.511365 Vddq = 0
6134 23:05:59.511770 Vmddr = 0
6135 23:05:59.515043 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6136 23:05:59.520996 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6137 23:05:59.524255 MEM_TYPE=3, freq_sel=20
6138 23:05:59.528081 sv_algorithm_assistance_LP4_800
6139 23:05:59.531363 ============ PULL DRAM RESETB DOWN ============
6140 23:05:59.534287 ========== PULL DRAM RESETB DOWN end =========
6141 23:05:59.538279 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6142 23:05:59.541099 ===================================
6143 23:05:59.544512 LPDDR4 DRAM CONFIGURATION
6144 23:05:59.547522 ===================================
6145 23:05:59.551076 EX_ROW_EN[0] = 0x0
6146 23:05:59.551654 EX_ROW_EN[1] = 0x0
6147 23:05:59.554171 LP4Y_EN = 0x0
6148 23:05:59.554652 WORK_FSP = 0x0
6149 23:05:59.557938 WL = 0x2
6150 23:05:59.558498 RL = 0x2
6151 23:05:59.560746 BL = 0x2
6152 23:05:59.561224 RPST = 0x0
6153 23:05:59.564404 RD_PRE = 0x0
6154 23:05:59.567535 WR_PRE = 0x1
6155 23:05:59.567999 WR_PST = 0x0
6156 23:05:59.570544 DBI_WR = 0x0
6157 23:05:59.570972 DBI_RD = 0x0
6158 23:05:59.574131 OTF = 0x1
6159 23:05:59.577383 ===================================
6160 23:05:59.580647 ===================================
6161 23:05:59.581067 ANA top config
6162 23:05:59.584461 ===================================
6163 23:05:59.587235 DLL_ASYNC_EN = 0
6164 23:05:59.590594 ALL_SLAVE_EN = 1
6165 23:05:59.591017 NEW_RANK_MODE = 1
6166 23:05:59.593861 DLL_IDLE_MODE = 1
6167 23:05:59.597132 LP45_APHY_COMB_EN = 1
6168 23:05:59.600229 TX_ODT_DIS = 1
6169 23:05:59.603345 NEW_8X_MODE = 1
6170 23:05:59.606593 ===================================
6171 23:05:59.609902 ===================================
6172 23:05:59.613022 data_rate = 800
6173 23:05:59.613489 CKR = 1
6174 23:05:59.616323 DQ_P2S_RATIO = 4
6175 23:05:59.619354 ===================================
6176 23:05:59.622592 CA_P2S_RATIO = 4
6177 23:05:59.626320 DQ_CA_OPEN = 0
6178 23:05:59.629574 DQ_SEMI_OPEN = 1
6179 23:05:59.632773 CA_SEMI_OPEN = 1
6180 23:05:59.632854 CA_FULL_RATE = 0
6181 23:05:59.636081 DQ_CKDIV4_EN = 0
6182 23:05:59.639589 CA_CKDIV4_EN = 1
6183 23:05:59.642484 CA_PREDIV_EN = 0
6184 23:05:59.645666 PH8_DLY = 0
6185 23:05:59.649180 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6186 23:05:59.649264 DQ_AAMCK_DIV = 0
6187 23:05:59.652871 CA_AAMCK_DIV = 0
6188 23:05:59.655864 CA_ADMCK_DIV = 4
6189 23:05:59.659304 DQ_TRACK_CA_EN = 0
6190 23:05:59.662476 CA_PICK = 800
6191 23:05:59.665290 CA_MCKIO = 400
6192 23:05:59.668575 MCKIO_SEMI = 400
6193 23:05:59.672507 PLL_FREQ = 3016
6194 23:05:59.672615 DQ_UI_PI_RATIO = 32
6195 23:05:59.675369 CA_UI_PI_RATIO = 32
6196 23:05:59.678693 ===================================
6197 23:05:59.682151 ===================================
6198 23:05:59.685218 memory_type:LPDDR4
6199 23:05:59.688567 GP_NUM : 10
6200 23:05:59.688649 SRAM_EN : 1
6201 23:05:59.691692 MD32_EN : 0
6202 23:05:59.695363 ===================================
6203 23:05:59.698410 [ANA_INIT] >>>>>>>>>>>>>>
6204 23:05:59.701714 <<<<<< [CONFIGURE PHASE]: ANA_TX
6205 23:05:59.705609 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6206 23:05:59.708992 ===================================
6207 23:05:59.709676 data_rate = 800,PCW = 0X7400
6208 23:05:59.711816 ===================================
6209 23:05:59.714868 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6210 23:05:59.721791 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6211 23:05:59.734876 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6212 23:05:59.737819 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6213 23:05:59.741288 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6214 23:05:59.744758 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6215 23:05:59.748757 [ANA_INIT] flow start
6216 23:05:59.749454 [ANA_INIT] PLL >>>>>>>>
6217 23:05:59.751381 [ANA_INIT] PLL <<<<<<<<
6218 23:05:59.754669 [ANA_INIT] MIDPI >>>>>>>>
6219 23:05:59.755161 [ANA_INIT] MIDPI <<<<<<<<
6220 23:05:59.757941 [ANA_INIT] DLL >>>>>>>>
6221 23:05:59.760882 [ANA_INIT] flow end
6222 23:05:59.764554 ============ LP4 DIFF to SE enter ============
6223 23:05:59.767831 ============ LP4 DIFF to SE exit ============
6224 23:05:59.770907 [ANA_INIT] <<<<<<<<<<<<<
6225 23:05:59.774174 [Flow] Enable top DCM control >>>>>
6226 23:05:59.777856 [Flow] Enable top DCM control <<<<<
6227 23:05:59.781099 Enable DLL master slave shuffle
6228 23:05:59.787647 ==============================================================
6229 23:05:59.788377 Gating Mode config
6230 23:05:59.794439 ==============================================================
6231 23:05:59.794868 Config description:
6232 23:05:59.803829 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6233 23:05:59.810687 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6234 23:05:59.817926 SELPH_MODE 0: By rank 1: By Phase
6235 23:05:59.820425 ==============================================================
6236 23:05:59.824241 GAT_TRACK_EN = 0
6237 23:05:59.827555 RX_GATING_MODE = 2
6238 23:05:59.830964 RX_GATING_TRACK_MODE = 2
6239 23:05:59.833508 SELPH_MODE = 1
6240 23:05:59.836992 PICG_EARLY_EN = 1
6241 23:05:59.840343 VALID_LAT_VALUE = 1
6242 23:05:59.847126 ==============================================================
6243 23:05:59.850456 Enter into Gating configuration >>>>
6244 23:05:59.853612 Exit from Gating configuration <<<<
6245 23:05:59.856579 Enter into DVFS_PRE_config >>>>>
6246 23:05:59.866560 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6247 23:05:59.869820 Exit from DVFS_PRE_config <<<<<
6248 23:05:59.873337 Enter into PICG configuration >>>>
6249 23:05:59.876604 Exit from PICG configuration <<<<
6250 23:05:59.879614 [RX_INPUT] configuration >>>>>
6251 23:05:59.880041 [RX_INPUT] configuration <<<<<
6252 23:05:59.886471 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6253 23:05:59.893205 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6254 23:05:59.896458 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6255 23:05:59.903387 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6256 23:05:59.909363 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6257 23:05:59.916442 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6258 23:05:59.919737 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6259 23:05:59.922969 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6260 23:05:59.929354 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6261 23:05:59.932787 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6262 23:05:59.936449 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6263 23:05:59.943206 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6264 23:05:59.946085 ===================================
6265 23:05:59.946523 LPDDR4 DRAM CONFIGURATION
6266 23:05:59.949001 ===================================
6267 23:05:59.952308 EX_ROW_EN[0] = 0x0
6268 23:05:59.952733 EX_ROW_EN[1] = 0x0
6269 23:05:59.956091 LP4Y_EN = 0x0
6270 23:05:59.960115 WORK_FSP = 0x0
6271 23:05:59.960538 WL = 0x2
6272 23:05:59.962429 RL = 0x2
6273 23:05:59.962852 BL = 0x2
6274 23:05:59.965697 RPST = 0x0
6275 23:05:59.966137 RD_PRE = 0x0
6276 23:05:59.968941 WR_PRE = 0x1
6277 23:05:59.969400 WR_PST = 0x0
6278 23:05:59.972486 DBI_WR = 0x0
6279 23:05:59.972908 DBI_RD = 0x0
6280 23:05:59.975392 OTF = 0x1
6281 23:05:59.978925 ===================================
6282 23:05:59.981883 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6283 23:05:59.985483 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6284 23:05:59.991861 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6285 23:05:59.995568 ===================================
6286 23:05:59.996011 LPDDR4 DRAM CONFIGURATION
6287 23:05:59.998861 ===================================
6288 23:06:00.001768 EX_ROW_EN[0] = 0x10
6289 23:06:00.004835 EX_ROW_EN[1] = 0x0
6290 23:06:00.005258 LP4Y_EN = 0x0
6291 23:06:00.008009 WORK_FSP = 0x0
6292 23:06:00.008580 WL = 0x2
6293 23:06:00.011879 RL = 0x2
6294 23:06:00.012339 BL = 0x2
6295 23:06:00.014729 RPST = 0x0
6296 23:06:00.015153 RD_PRE = 0x0
6297 23:06:00.018372 WR_PRE = 0x1
6298 23:06:00.018811 WR_PST = 0x0
6299 23:06:00.021497 DBI_WR = 0x0
6300 23:06:00.021919 DBI_RD = 0x0
6301 23:06:00.025549 OTF = 0x1
6302 23:06:00.027895 ===================================
6303 23:06:00.034345 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6304 23:06:00.037582 nWR fixed to 30
6305 23:06:00.041059 [ModeRegInit_LP4] CH0 RK0
6306 23:06:00.041561 [ModeRegInit_LP4] CH0 RK1
6307 23:06:00.044291 [ModeRegInit_LP4] CH1 RK0
6308 23:06:00.047323 [ModeRegInit_LP4] CH1 RK1
6309 23:06:00.047764 match AC timing 19
6310 23:06:00.054039 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6311 23:06:00.057528 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6312 23:06:00.060483 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6313 23:06:00.067259 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6314 23:06:00.070246 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6315 23:06:00.070674 ==
6316 23:06:00.074060 Dram Type= 6, Freq= 0, CH_0, rank 0
6317 23:06:00.077032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6318 23:06:00.077510 ==
6319 23:06:00.083715 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6320 23:06:00.090696 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6321 23:06:00.093574 [CA 0] Center 36 (8~64) winsize 57
6322 23:06:00.096883 [CA 1] Center 36 (8~64) winsize 57
6323 23:06:00.100513 [CA 2] Center 36 (8~64) winsize 57
6324 23:06:00.103575 [CA 3] Center 36 (8~64) winsize 57
6325 23:06:00.106544 [CA 4] Center 36 (8~64) winsize 57
6326 23:06:00.110262 [CA 5] Center 36 (8~64) winsize 57
6327 23:06:00.110715
6328 23:06:00.113126 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6329 23:06:00.113634
6330 23:06:00.117159 [CATrainingPosCal] consider 1 rank data
6331 23:06:00.119805 u2DelayCellTimex100 = 270/100 ps
6332 23:06:00.123211 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6333 23:06:00.126471 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6334 23:06:00.129651 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6335 23:06:00.133969 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6336 23:06:00.137542 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6337 23:06:00.139880 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6338 23:06:00.140307
6339 23:06:00.147266 CA PerBit enable=1, Macro0, CA PI delay=36
6340 23:06:00.147691
6341 23:06:00.148030 [CBTSetCACLKResult] CA Dly = 36
6342 23:06:00.149487 CS Dly: 1 (0~32)
6343 23:06:00.149949 ==
6344 23:06:00.153128 Dram Type= 6, Freq= 0, CH_0, rank 1
6345 23:06:00.156109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6346 23:06:00.156537 ==
6347 23:06:00.162767 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6348 23:06:00.169822 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6349 23:06:00.172764 [CA 0] Center 36 (8~64) winsize 57
6350 23:06:00.176798 [CA 1] Center 36 (8~64) winsize 57
6351 23:06:00.179191 [CA 2] Center 36 (8~64) winsize 57
6352 23:06:00.182329 [CA 3] Center 36 (8~64) winsize 57
6353 23:06:00.182757 [CA 4] Center 36 (8~64) winsize 57
6354 23:06:00.185791 [CA 5] Center 36 (8~64) winsize 57
6355 23:06:00.186218
6356 23:06:00.192193 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6357 23:06:00.192623
6358 23:06:00.195936 [CATrainingPosCal] consider 2 rank data
6359 23:06:00.199107 u2DelayCellTimex100 = 270/100 ps
6360 23:06:00.202556 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6361 23:06:00.206157 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6362 23:06:00.208789 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6363 23:06:00.212037 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6364 23:06:00.215530 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6365 23:06:00.219029 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6366 23:06:00.219566
6367 23:06:00.222241 CA PerBit enable=1, Macro0, CA PI delay=36
6368 23:06:00.222851
6369 23:06:00.225510 [CBTSetCACLKResult] CA Dly = 36
6370 23:06:00.229125 CS Dly: 1 (0~32)
6371 23:06:00.229595
6372 23:06:00.232132 ----->DramcWriteLeveling(PI) begin...
6373 23:06:00.232562 ==
6374 23:06:00.235239 Dram Type= 6, Freq= 0, CH_0, rank 0
6375 23:06:00.238675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6376 23:06:00.239140 ==
6377 23:06:00.241950 Write leveling (Byte 0): 40 => 8
6378 23:06:00.245038 Write leveling (Byte 1): 32 => 0
6379 23:06:00.248537 DramcWriteLeveling(PI) end<-----
6380 23:06:00.248998
6381 23:06:00.249330 ==
6382 23:06:00.251626 Dram Type= 6, Freq= 0, CH_0, rank 0
6383 23:06:00.255088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6384 23:06:00.255538 ==
6385 23:06:00.258587 [Gating] SW mode calibration
6386 23:06:00.265535 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6387 23:06:00.272020 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6388 23:06:00.275329 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6389 23:06:00.281499 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6390 23:06:00.285291 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6391 23:06:00.288355 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6392 23:06:00.294565 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6393 23:06:00.297876 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6394 23:06:00.301224 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6395 23:06:00.308077 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6396 23:06:00.311133 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6397 23:06:00.314859 Total UI for P1: 0, mck2ui 16
6398 23:06:00.317895 best dqsien dly found for B0: ( 0, 14, 24)
6399 23:06:00.320887 Total UI for P1: 0, mck2ui 16
6400 23:06:00.324383 best dqsien dly found for B1: ( 0, 14, 24)
6401 23:06:00.327806 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6402 23:06:00.331124 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6403 23:06:00.331544
6404 23:06:00.333990 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6405 23:06:00.338007 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6406 23:06:00.340686 [Gating] SW calibration Done
6407 23:06:00.341102 ==
6408 23:06:00.344242 Dram Type= 6, Freq= 0, CH_0, rank 0
6409 23:06:00.350781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6410 23:06:00.351427 ==
6411 23:06:00.351998 RX Vref Scan: 0
6412 23:06:00.352347
6413 23:06:00.354156 RX Vref 0 -> 0, step: 1
6414 23:06:00.354576
6415 23:06:00.357288 RX Delay -410 -> 252, step: 16
6416 23:06:00.360602 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6417 23:06:00.363871 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6418 23:06:00.367768 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6419 23:06:00.373896 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6420 23:06:00.377129 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6421 23:06:00.380747 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6422 23:06:00.384308 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6423 23:06:00.390824 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6424 23:06:00.393953 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6425 23:06:00.397003 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6426 23:06:00.403897 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6427 23:06:00.407043 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6428 23:06:00.410401 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6429 23:06:00.413651 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6430 23:06:00.420133 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6431 23:06:00.423140 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6432 23:06:00.423667 ==
6433 23:06:00.426493 Dram Type= 6, Freq= 0, CH_0, rank 0
6434 23:06:00.429968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6435 23:06:00.430394 ==
6436 23:06:00.433373 DQS Delay:
6437 23:06:00.433830 DQS0 = 43, DQS1 = 59
6438 23:06:00.437098 DQM Delay:
6439 23:06:00.437554 DQM0 = 10, DQM1 = 11
6440 23:06:00.437897 DQ Delay:
6441 23:06:00.440355 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6442 23:06:00.443083 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6443 23:06:00.446746 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6444 23:06:00.450191 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6445 23:06:00.450613
6446 23:06:00.450953
6447 23:06:00.451265 ==
6448 23:06:00.453061 Dram Type= 6, Freq= 0, CH_0, rank 0
6449 23:06:00.459516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6450 23:06:00.459941 ==
6451 23:06:00.460282
6452 23:06:00.460592
6453 23:06:00.460889 TX Vref Scan disable
6454 23:06:00.463141 == TX Byte 0 ==
6455 23:06:00.466450 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6456 23:06:00.469477 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6457 23:06:00.472965 == TX Byte 1 ==
6458 23:06:00.476482 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6459 23:06:00.479543 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6460 23:06:00.482877 ==
6461 23:06:00.483300 Dram Type= 6, Freq= 0, CH_0, rank 0
6462 23:06:00.489600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6463 23:06:00.490024 ==
6464 23:06:00.490562
6465 23:06:00.490906
6466 23:06:00.492699 TX Vref Scan disable
6467 23:06:00.493117 == TX Byte 0 ==
6468 23:06:00.496296 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6469 23:06:00.502255 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6470 23:06:00.502679 == TX Byte 1 ==
6471 23:06:00.506072 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6472 23:06:00.512480 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6473 23:06:00.512905
6474 23:06:00.513246 [DATLAT]
6475 23:06:00.513598 Freq=400, CH0 RK0
6476 23:06:00.513911
6477 23:06:00.515640 DATLAT Default: 0xf
6478 23:06:00.519048 0, 0xFFFF, sum = 0
6479 23:06:00.519479 1, 0xFFFF, sum = 0
6480 23:06:00.521993 2, 0xFFFF, sum = 0
6481 23:06:00.522420 3, 0xFFFF, sum = 0
6482 23:06:00.525512 4, 0xFFFF, sum = 0
6483 23:06:00.525941 5, 0xFFFF, sum = 0
6484 23:06:00.528502 6, 0xFFFF, sum = 0
6485 23:06:00.528930 7, 0xFFFF, sum = 0
6486 23:06:00.531912 8, 0xFFFF, sum = 0
6487 23:06:00.532340 9, 0xFFFF, sum = 0
6488 23:06:00.535437 10, 0xFFFF, sum = 0
6489 23:06:00.535973 11, 0xFFFF, sum = 0
6490 23:06:00.538834 12, 0xFFFF, sum = 0
6491 23:06:00.539309 13, 0x0, sum = 1
6492 23:06:00.542147 14, 0x0, sum = 2
6493 23:06:00.542623 15, 0x0, sum = 3
6494 23:06:00.545219 16, 0x0, sum = 4
6495 23:06:00.545792 best_step = 14
6496 23:06:00.546276
6497 23:06:00.546767 ==
6498 23:06:00.548447 Dram Type= 6, Freq= 0, CH_0, rank 0
6499 23:06:00.555465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6500 23:06:00.555916 ==
6501 23:06:00.556367 RX Vref Scan: 1
6502 23:06:00.556793
6503 23:06:00.558438 RX Vref 0 -> 0, step: 1
6504 23:06:00.559082
6505 23:06:00.561811 RX Delay -359 -> 252, step: 8
6506 23:06:00.562389
6507 23:06:00.565063 Set Vref, RX VrefLevel [Byte0]: 61
6508 23:06:00.568742 [Byte1]: 49
6509 23:06:00.571764
6510 23:06:00.572286 Final RX Vref Byte 0 = 61 to rank0
6511 23:06:00.574554 Final RX Vref Byte 1 = 49 to rank0
6512 23:06:00.578699 Final RX Vref Byte 0 = 61 to rank1
6513 23:06:00.581281 Final RX Vref Byte 1 = 49 to rank1==
6514 23:06:00.584547 Dram Type= 6, Freq= 0, CH_0, rank 0
6515 23:06:00.591032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6516 23:06:00.591602 ==
6517 23:06:00.592075 DQS Delay:
6518 23:06:00.594745 DQS0 = 44, DQS1 = 60
6519 23:06:00.595176 DQM Delay:
6520 23:06:00.595563 DQM0 = 8, DQM1 = 12
6521 23:06:00.597596 DQ Delay:
6522 23:06:00.600895 DQ0 =8, DQ1 =8, DQ2 =4, DQ3 =4
6523 23:06:00.604788 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6524 23:06:00.605211 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6525 23:06:00.607705 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6526 23:06:00.610926
6527 23:06:00.611342
6528 23:06:00.617277 [DQSOSCAuto] RK0, (LSB)MR18= 0xbe80, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 386 ps
6529 23:06:00.620925 CH0 RK0: MR19=C0C, MR18=BE80
6530 23:06:00.627322 CH0_RK0: MR19=0xC0C, MR18=0xBE80, DQSOSC=386, MR23=63, INC=396, DEC=264
6531 23:06:00.627748 ==
6532 23:06:00.630735 Dram Type= 6, Freq= 0, CH_0, rank 1
6533 23:06:00.634103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6534 23:06:00.634677 ==
6535 23:06:00.637749 [Gating] SW mode calibration
6536 23:06:00.643929 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6537 23:06:00.650370 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6538 23:06:00.654163 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6539 23:06:00.657462 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6540 23:06:00.663775 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6541 23:06:00.667165 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6542 23:06:00.670237 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6543 23:06:00.676879 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6544 23:06:00.680245 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6545 23:06:00.683481 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6546 23:06:00.690096 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6547 23:06:00.690519 Total UI for P1: 0, mck2ui 16
6548 23:06:00.696621 best dqsien dly found for B0: ( 0, 14, 24)
6549 23:06:00.697045 Total UI for P1: 0, mck2ui 16
6550 23:06:00.703730 best dqsien dly found for B1: ( 0, 14, 24)
6551 23:06:00.706779 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6552 23:06:00.709996 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6553 23:06:00.710422
6554 23:06:00.713287 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6555 23:06:00.716447 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6556 23:06:00.719892 [Gating] SW calibration Done
6557 23:06:00.720315 ==
6558 23:06:00.723016 Dram Type= 6, Freq= 0, CH_0, rank 1
6559 23:06:00.726667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6560 23:06:00.727091 ==
6561 23:06:00.729440 RX Vref Scan: 0
6562 23:06:00.729863
6563 23:06:00.730200 RX Vref 0 -> 0, step: 1
6564 23:06:00.732691
6565 23:06:00.733110 RX Delay -410 -> 252, step: 16
6566 23:06:00.739764 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6567 23:06:00.743075 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6568 23:06:00.746290 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6569 23:06:00.749198 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6570 23:06:00.755914 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6571 23:06:00.759608 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6572 23:06:00.763107 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6573 23:06:00.769395 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6574 23:06:00.772393 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6575 23:06:00.776052 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6576 23:06:00.779398 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6577 23:06:00.786345 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6578 23:06:00.788902 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6579 23:06:00.792162 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6580 23:06:00.795538 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6581 23:06:00.802055 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6582 23:06:00.802708 ==
6583 23:06:00.805248 Dram Type= 6, Freq= 0, CH_0, rank 1
6584 23:06:00.808636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6585 23:06:00.809276 ==
6586 23:06:00.809838 DQS Delay:
6587 23:06:00.812515 DQS0 = 43, DQS1 = 59
6588 23:06:00.812921 DQM Delay:
6589 23:06:00.815271 DQM0 = 10, DQM1 = 16
6590 23:06:00.815874 DQ Delay:
6591 23:06:00.818674 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6592 23:06:00.822058 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6593 23:06:00.825691 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6594 23:06:00.828649 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6595 23:06:00.829123
6596 23:06:00.829826
6597 23:06:00.830390 ==
6598 23:06:00.831838 Dram Type= 6, Freq= 0, CH_0, rank 1
6599 23:06:00.835183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6600 23:06:00.835606 ==
6601 23:06:00.835949
6602 23:06:00.836265
6603 23:06:00.839033 TX Vref Scan disable
6604 23:06:00.841962 == TX Byte 0 ==
6605 23:06:00.845529 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6606 23:06:00.848734 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6607 23:06:00.851811 == TX Byte 1 ==
6608 23:06:00.855097 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6609 23:06:00.858709 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6610 23:06:00.859180 ==
6611 23:06:00.861352 Dram Type= 6, Freq= 0, CH_0, rank 1
6612 23:06:00.864864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6613 23:06:00.865291 ==
6614 23:06:00.868512
6615 23:06:00.869131
6616 23:06:00.869522 TX Vref Scan disable
6617 23:06:00.871711 == TX Byte 0 ==
6618 23:06:00.874657 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6619 23:06:00.878131 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6620 23:06:00.881266 == TX Byte 1 ==
6621 23:06:00.884744 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6622 23:06:00.888040 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6623 23:06:00.888632
6624 23:06:00.889125 [DATLAT]
6625 23:06:00.891548 Freq=400, CH0 RK1
6626 23:06:00.891971
6627 23:06:00.894530 DATLAT Default: 0xe
6628 23:06:00.894973 0, 0xFFFF, sum = 0
6629 23:06:00.898207 1, 0xFFFF, sum = 0
6630 23:06:00.898635 2, 0xFFFF, sum = 0
6631 23:06:00.901378 3, 0xFFFF, sum = 0
6632 23:06:00.901858 4, 0xFFFF, sum = 0
6633 23:06:00.904351 5, 0xFFFF, sum = 0
6634 23:06:00.904778 6, 0xFFFF, sum = 0
6635 23:06:00.907986 7, 0xFFFF, sum = 0
6636 23:06:00.908415 8, 0xFFFF, sum = 0
6637 23:06:00.911361 9, 0xFFFF, sum = 0
6638 23:06:00.911791 10, 0xFFFF, sum = 0
6639 23:06:00.914441 11, 0xFFFF, sum = 0
6640 23:06:00.914868 12, 0xFFFF, sum = 0
6641 23:06:00.917903 13, 0x0, sum = 1
6642 23:06:00.918335 14, 0x0, sum = 2
6643 23:06:00.920831 15, 0x0, sum = 3
6644 23:06:00.921260 16, 0x0, sum = 4
6645 23:06:00.924211 best_step = 14
6646 23:06:00.924634
6647 23:06:00.924967 ==
6648 23:06:00.927959 Dram Type= 6, Freq= 0, CH_0, rank 1
6649 23:06:00.931147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6650 23:06:00.931572 ==
6651 23:06:00.934495 RX Vref Scan: 0
6652 23:06:00.934916
6653 23:06:00.935251 RX Vref 0 -> 0, step: 1
6654 23:06:00.935567
6655 23:06:00.937241 RX Delay -359 -> 252, step: 8
6656 23:06:00.945347 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6657 23:06:00.948788 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6658 23:06:00.951973 iDelay=217, Bit 2, Center -44 (-287 ~ 200) 488
6659 23:06:00.958674 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6660 23:06:00.961983 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6661 23:06:00.965435 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6662 23:06:00.968599 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6663 23:06:00.975137 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6664 23:06:00.978367 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6665 23:06:00.981982 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6666 23:06:00.985327 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6667 23:06:00.992339 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6668 23:06:00.994950 iDelay=217, Bit 12, Center -36 (-279 ~ 208) 488
6669 23:06:00.998909 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6670 23:06:01.001545 iDelay=217, Bit 14, Center -32 (-271 ~ 208) 480
6671 23:06:01.008366 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6672 23:06:01.008913 ==
6673 23:06:01.011476 Dram Type= 6, Freq= 0, CH_0, rank 1
6674 23:06:01.014811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6675 23:06:01.015280 ==
6676 23:06:01.015653 DQS Delay:
6677 23:06:01.018204 DQS0 = 44, DQS1 = 60
6678 23:06:01.018678 DQM Delay:
6679 23:06:01.021655 DQM0 = 7, DQM1 = 15
6680 23:06:01.022128 DQ Delay:
6681 23:06:01.024530 DQ0 =4, DQ1 =8, DQ2 =0, DQ3 =4
6682 23:06:01.027779 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6683 23:06:01.031335 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6684 23:06:01.034835 DQ12 =24, DQ13 =20, DQ14 =28, DQ15 =20
6685 23:06:01.035430
6686 23:06:01.035974
6687 23:06:01.041577 [DQSOSCAuto] RK1, (LSB)MR18= 0xb944, (MSB)MR19= 0xc0c, tDQSOscB0 = 401 ps tDQSOscB1 = 386 ps
6688 23:06:01.044642 CH0 RK1: MR19=C0C, MR18=B944
6689 23:06:01.051307 CH0_RK1: MR19=0xC0C, MR18=0xB944, DQSOSC=386, MR23=63, INC=396, DEC=264
6690 23:06:01.054832 [RxdqsGatingPostProcess] freq 400
6691 23:06:01.061337 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6692 23:06:01.064556 best DQS0 dly(2T, 0.5T) = (0, 10)
6693 23:06:01.067546 best DQS1 dly(2T, 0.5T) = (0, 10)
6694 23:06:01.071268 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6695 23:06:01.074378 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6696 23:06:01.074973 best DQS0 dly(2T, 0.5T) = (0, 10)
6697 23:06:01.077693 best DQS1 dly(2T, 0.5T) = (0, 10)
6698 23:06:01.080966 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6699 23:06:01.084038 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6700 23:06:01.087576 Pre-setting of DQS Precalculation
6701 23:06:01.093912 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6702 23:06:01.094338 ==
6703 23:06:01.097038 Dram Type= 6, Freq= 0, CH_1, rank 0
6704 23:06:01.100359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6705 23:06:01.100783 ==
6706 23:06:01.108161 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6707 23:06:01.113820 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6708 23:06:01.117104 [CA 0] Center 36 (8~64) winsize 57
6709 23:06:01.120424 [CA 1] Center 36 (8~64) winsize 57
6710 23:06:01.120849 [CA 2] Center 36 (8~64) winsize 57
6711 23:06:01.123645 [CA 3] Center 36 (8~64) winsize 57
6712 23:06:01.126759 [CA 4] Center 36 (8~64) winsize 57
6713 23:06:01.130209 [CA 5] Center 36 (8~64) winsize 57
6714 23:06:01.130707
6715 23:06:01.133937 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6716 23:06:01.136864
6717 23:06:01.139947 [CATrainingPosCal] consider 1 rank data
6718 23:06:01.140371 u2DelayCellTimex100 = 270/100 ps
6719 23:06:01.146644 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6720 23:06:01.150140 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6721 23:06:01.153485 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6722 23:06:01.156836 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6723 23:06:01.160020 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6724 23:06:01.163962 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6725 23:06:01.164386
6726 23:06:01.166659 CA PerBit enable=1, Macro0, CA PI delay=36
6727 23:06:01.167080
6728 23:06:01.169642 [CBTSetCACLKResult] CA Dly = 36
6729 23:06:01.172903 CS Dly: 1 (0~32)
6730 23:06:01.173325 ==
6731 23:06:01.176263 Dram Type= 6, Freq= 0, CH_1, rank 1
6732 23:06:01.180074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6733 23:06:01.180501 ==
6734 23:06:01.186608 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6735 23:06:01.193467 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6736 23:06:01.193895 [CA 0] Center 36 (8~64) winsize 57
6737 23:06:01.196205 [CA 1] Center 36 (8~64) winsize 57
6738 23:06:01.199561 [CA 2] Center 36 (8~64) winsize 57
6739 23:06:01.203337 [CA 3] Center 36 (8~64) winsize 57
6740 23:06:01.205969 [CA 4] Center 36 (8~64) winsize 57
6741 23:06:01.209517 [CA 5] Center 36 (8~64) winsize 57
6742 23:06:01.209952
6743 23:06:01.212585 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6744 23:06:01.213007
6745 23:06:01.215990 [CATrainingPosCal] consider 2 rank data
6746 23:06:01.219432 u2DelayCellTimex100 = 270/100 ps
6747 23:06:01.222549 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6748 23:06:01.229665 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6749 23:06:01.232681 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6750 23:06:01.235822 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6751 23:06:01.239436 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6752 23:06:01.242528 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6753 23:06:01.242952
6754 23:06:01.245862 CA PerBit enable=1, Macro0, CA PI delay=36
6755 23:06:01.246291
6756 23:06:01.249481 [CBTSetCACLKResult] CA Dly = 36
6757 23:06:01.252395 CS Dly: 1 (0~32)
6758 23:06:01.252832
6759 23:06:01.255347 ----->DramcWriteLeveling(PI) begin...
6760 23:06:01.255993 ==
6761 23:06:01.259061 Dram Type= 6, Freq= 0, CH_1, rank 0
6762 23:06:01.262505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6763 23:06:01.262934 ==
6764 23:06:01.265535 Write leveling (Byte 0): 40 => 8
6765 23:06:01.268711 Write leveling (Byte 1): 32 => 0
6766 23:06:01.272003 DramcWriteLeveling(PI) end<-----
6767 23:06:01.272427
6768 23:06:01.272767 ==
6769 23:06:01.275332 Dram Type= 6, Freq= 0, CH_1, rank 0
6770 23:06:01.278822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6771 23:06:01.279247 ==
6772 23:06:01.281821 [Gating] SW mode calibration
6773 23:06:01.288484 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6774 23:06:01.294860 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6775 23:06:01.298288 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6776 23:06:01.301960 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6777 23:06:01.308297 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6778 23:06:01.311393 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6779 23:06:01.314948 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6780 23:06:01.321365 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6781 23:06:01.324880 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6782 23:06:01.328012 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6783 23:06:01.334491 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6784 23:06:01.338434 Total UI for P1: 0, mck2ui 16
6785 23:06:01.341316 best dqsien dly found for B0: ( 0, 14, 24)
6786 23:06:01.341807 Total UI for P1: 0, mck2ui 16
6787 23:06:01.348156 best dqsien dly found for B1: ( 0, 14, 24)
6788 23:06:01.351099 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6789 23:06:01.354688 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6790 23:06:01.355113
6791 23:06:01.357515 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6792 23:06:01.361214 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6793 23:06:01.364557 [Gating] SW calibration Done
6794 23:06:01.364980 ==
6795 23:06:01.367995 Dram Type= 6, Freq= 0, CH_1, rank 0
6796 23:06:01.370787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6797 23:06:01.371213 ==
6798 23:06:01.374028 RX Vref Scan: 0
6799 23:06:01.374456
6800 23:06:01.377779 RX Vref 0 -> 0, step: 1
6801 23:06:01.378234
6802 23:06:01.378571 RX Delay -410 -> 252, step: 16
6803 23:06:01.384176 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6804 23:06:01.387447 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6805 23:06:01.390540 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6806 23:06:01.397260 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6807 23:06:01.400597 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6808 23:06:01.403893 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6809 23:06:01.407540 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6810 23:06:01.413493 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6811 23:06:01.417014 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6812 23:06:01.420254 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6813 23:06:01.423320 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6814 23:06:01.430101 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6815 23:06:01.433520 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6816 23:06:01.436487 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6817 23:06:01.443575 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6818 23:06:01.446265 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6819 23:06:01.446689 ==
6820 23:06:01.449615 Dram Type= 6, Freq= 0, CH_1, rank 0
6821 23:06:01.453072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6822 23:06:01.453533 ==
6823 23:06:01.456268 DQS Delay:
6824 23:06:01.456894 DQS0 = 43, DQS1 = 51
6825 23:06:01.457262 DQM Delay:
6826 23:06:01.459677 DQM0 = 12, DQM1 = 14
6827 23:06:01.460098 DQ Delay:
6828 23:06:01.462853 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6829 23:06:01.466022 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6830 23:06:01.469243 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6831 23:06:01.472868 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6832 23:06:01.473291
6833 23:06:01.473677
6834 23:06:01.473994 ==
6835 23:06:01.476937 Dram Type= 6, Freq= 0, CH_1, rank 0
6836 23:06:01.479230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6837 23:06:01.482544 ==
6838 23:06:01.482966
6839 23:06:01.483303
6840 23:06:01.483612 TX Vref Scan disable
6841 23:06:01.486127 == TX Byte 0 ==
6842 23:06:01.489519 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6843 23:06:01.492873 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6844 23:06:01.495629 == TX Byte 1 ==
6845 23:06:01.498937 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6846 23:06:01.502541 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6847 23:06:01.502977 ==
6848 23:06:01.505514 Dram Type= 6, Freq= 0, CH_1, rank 0
6849 23:06:01.512062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6850 23:06:01.512487 ==
6851 23:06:01.512825
6852 23:06:01.513136
6853 23:06:01.513462 TX Vref Scan disable
6854 23:06:01.515399 == TX Byte 0 ==
6855 23:06:01.518940 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6856 23:06:01.521891 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6857 23:06:01.525394 == TX Byte 1 ==
6858 23:06:01.528858 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6859 23:06:01.535398 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6860 23:06:01.535820
6861 23:06:01.536158 [DATLAT]
6862 23:06:01.536470 Freq=400, CH1 RK0
6863 23:06:01.536776
6864 23:06:01.538907 DATLAT Default: 0xf
6865 23:06:01.539330 0, 0xFFFF, sum = 0
6866 23:06:01.541790 1, 0xFFFF, sum = 0
6867 23:06:01.542247 2, 0xFFFF, sum = 0
6868 23:06:01.545255 3, 0xFFFF, sum = 0
6869 23:06:01.548598 4, 0xFFFF, sum = 0
6870 23:06:01.549026 5, 0xFFFF, sum = 0
6871 23:06:01.551915 6, 0xFFFF, sum = 0
6872 23:06:01.552405 7, 0xFFFF, sum = 0
6873 23:06:01.555152 8, 0xFFFF, sum = 0
6874 23:06:01.555602 9, 0xFFFF, sum = 0
6875 23:06:01.558208 10, 0xFFFF, sum = 0
6876 23:06:01.558641 11, 0xFFFF, sum = 0
6877 23:06:01.561921 12, 0xFFFF, sum = 0
6878 23:06:01.562353 13, 0x0, sum = 1
6879 23:06:01.564916 14, 0x0, sum = 2
6880 23:06:01.565341 15, 0x0, sum = 3
6881 23:06:01.568064 16, 0x0, sum = 4
6882 23:06:01.568492 best_step = 14
6883 23:06:01.568830
6884 23:06:01.569138 ==
6885 23:06:01.571285 Dram Type= 6, Freq= 0, CH_1, rank 0
6886 23:06:01.574975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6887 23:06:01.578068 ==
6888 23:06:01.578502 RX Vref Scan: 1
6889 23:06:01.578840
6890 23:06:01.581493 RX Vref 0 -> 0, step: 1
6891 23:06:01.581918
6892 23:06:01.584878 RX Delay -343 -> 252, step: 8
6893 23:06:01.585301
6894 23:06:01.588070 Set Vref, RX VrefLevel [Byte0]: 52
6895 23:06:01.591477 [Byte1]: 60
6896 23:06:01.591899
6897 23:06:01.594751 Final RX Vref Byte 0 = 52 to rank0
6898 23:06:01.598129 Final RX Vref Byte 1 = 60 to rank0
6899 23:06:01.601179 Final RX Vref Byte 0 = 52 to rank1
6900 23:06:01.604610 Final RX Vref Byte 1 = 60 to rank1==
6901 23:06:01.607973 Dram Type= 6, Freq= 0, CH_1, rank 0
6902 23:06:01.611686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6903 23:06:01.614746 ==
6904 23:06:01.615168 DQS Delay:
6905 23:06:01.615504 DQS0 = 48, DQS1 = 56
6906 23:06:01.617572 DQM Delay:
6907 23:06:01.617993 DQM0 = 12, DQM1 = 12
6908 23:06:01.620798 DQ Delay:
6909 23:06:01.621219 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =12
6910 23:06:01.624448 DQ4 =8, DQ5 =24, DQ6 =20, DQ7 =8
6911 23:06:01.627464 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6912 23:06:01.631145 DQ12 =24, DQ13 =16, DQ14 =20, DQ15 =24
6913 23:06:01.631568
6914 23:06:01.631902
6915 23:06:01.641084 [DQSOSCAuto] RK0, (LSB)MR18= 0x9b72, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 390 ps
6916 23:06:01.644080 CH1 RK0: MR19=C0C, MR18=9B72
6917 23:06:01.651135 CH1_RK0: MR19=0xC0C, MR18=0x9B72, DQSOSC=390, MR23=63, INC=388, DEC=258
6918 23:06:01.651644 ==
6919 23:06:01.653762 Dram Type= 6, Freq= 0, CH_1, rank 1
6920 23:06:01.657196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6921 23:06:01.657804 ==
6922 23:06:01.660330 [Gating] SW mode calibration
6923 23:06:01.667391 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6924 23:06:01.670779 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6925 23:06:01.677047 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6926 23:06:01.680212 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6927 23:06:01.683706 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6928 23:06:01.690433 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6929 23:06:01.693506 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6930 23:06:01.697014 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6931 23:06:01.703296 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6932 23:06:01.706697 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6933 23:06:01.713745 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6934 23:06:01.714182 Total UI for P1: 0, mck2ui 16
6935 23:06:01.716392 best dqsien dly found for B0: ( 0, 14, 24)
6936 23:06:01.720060 Total UI for P1: 0, mck2ui 16
6937 23:06:01.723800 best dqsien dly found for B1: ( 0, 14, 24)
6938 23:06:01.729692 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6939 23:06:01.733545 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6940 23:06:01.733969
6941 23:06:01.736310 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6942 23:06:01.739908 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6943 23:06:01.743399 [Gating] SW calibration Done
6944 23:06:01.743820 ==
6945 23:06:01.746778 Dram Type= 6, Freq= 0, CH_1, rank 1
6946 23:06:01.749708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6947 23:06:01.750132 ==
6948 23:06:01.752668 RX Vref Scan: 0
6949 23:06:01.753140
6950 23:06:01.753589 RX Vref 0 -> 0, step: 1
6951 23:06:01.753951
6952 23:06:01.756071 RX Delay -410 -> 252, step: 16
6953 23:06:01.762773 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6954 23:06:01.766459 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6955 23:06:01.769929 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6956 23:06:01.772647 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6957 23:06:01.779106 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6958 23:06:01.782470 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6959 23:06:01.785657 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6960 23:06:01.789056 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6961 23:06:01.795817 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6962 23:06:01.798910 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6963 23:06:01.802690 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6964 23:06:01.805559 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6965 23:06:01.812174 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6966 23:06:01.815499 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6967 23:06:01.818946 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6968 23:06:01.825663 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6969 23:06:01.826085 ==
6970 23:06:01.828746 Dram Type= 6, Freq= 0, CH_1, rank 1
6971 23:06:01.832032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6972 23:06:01.832458 ==
6973 23:06:01.832796 DQS Delay:
6974 23:06:01.835761 DQS0 = 43, DQS1 = 59
6975 23:06:01.836181 DQM Delay:
6976 23:06:01.839050 DQM0 = 12, DQM1 = 22
6977 23:06:01.839469 DQ Delay:
6978 23:06:01.842147 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6979 23:06:01.845594 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6980 23:06:01.848495 DQ8 =0, DQ9 =16, DQ10 =16, DQ11 =16
6981 23:06:01.851964 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =32
6982 23:06:01.852389
6983 23:06:01.852727
6984 23:06:01.853040 ==
6985 23:06:01.855547 Dram Type= 6, Freq= 0, CH_1, rank 1
6986 23:06:01.858314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6987 23:06:01.858948 ==
6988 23:06:01.859317
6989 23:06:01.859632
6990 23:06:01.861955 TX Vref Scan disable
6991 23:06:01.862379 == TX Byte 0 ==
6992 23:06:01.868770 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6993 23:06:01.871911 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6994 23:06:01.872470 == TX Byte 1 ==
6995 23:06:01.878345 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6996 23:06:01.882054 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6997 23:06:01.882527 ==
6998 23:06:01.885265 Dram Type= 6, Freq= 0, CH_1, rank 1
6999 23:06:01.888085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7000 23:06:01.888604 ==
7001 23:06:01.888951
7002 23:06:01.889389
7003 23:06:01.891727 TX Vref Scan disable
7004 23:06:01.895184 == TX Byte 0 ==
7005 23:06:01.898370 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
7006 23:06:01.901608 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
7007 23:06:01.902036 == TX Byte 1 ==
7008 23:06:01.908561 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
7009 23:06:01.911369 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
7010 23:06:01.911790
7011 23:06:01.912126 [DATLAT]
7012 23:06:01.915326 Freq=400, CH1 RK1
7013 23:06:01.915752
7014 23:06:01.916088 DATLAT Default: 0xe
7015 23:06:01.918193 0, 0xFFFF, sum = 0
7016 23:06:01.918629 1, 0xFFFF, sum = 0
7017 23:06:01.921530 2, 0xFFFF, sum = 0
7018 23:06:01.921963 3, 0xFFFF, sum = 0
7019 23:06:01.924563 4, 0xFFFF, sum = 0
7020 23:06:01.928162 5, 0xFFFF, sum = 0
7021 23:06:01.928589 6, 0xFFFF, sum = 0
7022 23:06:01.931399 7, 0xFFFF, sum = 0
7023 23:06:01.931832 8, 0xFFFF, sum = 0
7024 23:06:01.934481 9, 0xFFFF, sum = 0
7025 23:06:01.935185 10, 0xFFFF, sum = 0
7026 23:06:01.937718 11, 0xFFFF, sum = 0
7027 23:06:01.938148 12, 0xFFFF, sum = 0
7028 23:06:01.940952 13, 0x0, sum = 1
7029 23:06:01.941555 14, 0x0, sum = 2
7030 23:06:01.944525 15, 0x0, sum = 3
7031 23:06:01.944954 16, 0x0, sum = 4
7032 23:06:01.948109 best_step = 14
7033 23:06:01.948778
7034 23:06:01.949436 ==
7035 23:06:01.951191 Dram Type= 6, Freq= 0, CH_1, rank 1
7036 23:06:01.954279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7037 23:06:01.954703 ==
7038 23:06:01.955045 RX Vref Scan: 0
7039 23:06:01.957967
7040 23:06:01.958575 RX Vref 0 -> 0, step: 1
7041 23:06:01.959057
7042 23:06:01.960780 RX Delay -359 -> 252, step: 8
7043 23:06:01.969055 iDelay=225, Bit 0, Center -28 (-271 ~ 216) 488
7044 23:06:01.972075 iDelay=225, Bit 1, Center -44 (-287 ~ 200) 488
7045 23:06:01.975373 iDelay=225, Bit 2, Center -44 (-287 ~ 200) 488
7046 23:06:01.981327 iDelay=225, Bit 3, Center -40 (-279 ~ 200) 480
7047 23:06:01.984921 iDelay=225, Bit 4, Center -40 (-287 ~ 208) 496
7048 23:06:01.988160 iDelay=225, Bit 5, Center -28 (-271 ~ 216) 488
7049 23:06:01.991399 iDelay=225, Bit 6, Center -24 (-271 ~ 224) 496
7050 23:06:01.998064 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
7051 23:06:02.002113 iDelay=225, Bit 8, Center -60 (-311 ~ 192) 504
7052 23:06:02.004881 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
7053 23:06:02.008202 iDelay=225, Bit 10, Center -44 (-295 ~ 208) 504
7054 23:06:02.014464 iDelay=225, Bit 11, Center -56 (-303 ~ 192) 496
7055 23:06:02.018537 iDelay=225, Bit 12, Center -36 (-287 ~ 216) 504
7056 23:06:02.021010 iDelay=225, Bit 13, Center -36 (-287 ~ 216) 504
7057 23:06:02.024509 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
7058 23:06:02.031042 iDelay=225, Bit 15, Center -36 (-287 ~ 216) 504
7059 23:06:02.031594 ==
7060 23:06:02.034383 Dram Type= 6, Freq= 0, CH_1, rank 1
7061 23:06:02.037911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7062 23:06:02.038497 ==
7063 23:06:02.041314 DQS Delay:
7064 23:06:02.041934 DQS0 = 44, DQS1 = 60
7065 23:06:02.042521 DQM Delay:
7066 23:06:02.044433 DQM0 = 8, DQM1 = 14
7067 23:06:02.044943 DQ Delay:
7068 23:06:02.048033 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =4
7069 23:06:02.051396 DQ4 =4, DQ5 =16, DQ6 =20, DQ7 =4
7070 23:06:02.054422 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
7071 23:06:02.057823 DQ12 =24, DQ13 =24, DQ14 =20, DQ15 =24
7072 23:06:02.058266
7073 23:06:02.058606
7074 23:06:02.064197 [DQSOSCAuto] RK1, (LSB)MR18= 0x6756, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
7075 23:06:02.067324 CH1 RK1: MR19=C0C, MR18=6756
7076 23:06:02.074034 CH1_RK1: MR19=0xC0C, MR18=0x6756, DQSOSC=396, MR23=63, INC=376, DEC=251
7077 23:06:02.077734 [RxdqsGatingPostProcess] freq 400
7078 23:06:02.083922 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7079 23:06:02.087650 best DQS0 dly(2T, 0.5T) = (0, 10)
7080 23:06:02.090867 best DQS1 dly(2T, 0.5T) = (0, 10)
7081 23:06:02.093751 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7082 23:06:02.097080 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7083 23:06:02.097555 best DQS0 dly(2T, 0.5T) = (0, 10)
7084 23:06:02.100523 best DQS1 dly(2T, 0.5T) = (0, 10)
7085 23:06:02.103838 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7086 23:06:02.107188 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7087 23:06:02.110202 Pre-setting of DQS Precalculation
7088 23:06:02.116649 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7089 23:06:02.124288 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7090 23:06:02.129785 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7091 23:06:02.130213
7092 23:06:02.130551
7093 23:06:02.133144 [Calibration Summary] 800 Mbps
7094 23:06:02.136904 CH 0, Rank 0
7095 23:06:02.137325 SW Impedance : PASS
7096 23:06:02.139753 DUTY Scan : NO K
7097 23:06:02.143149 ZQ Calibration : PASS
7098 23:06:02.143581 Jitter Meter : NO K
7099 23:06:02.146624 CBT Training : PASS
7100 23:06:02.149391 Write leveling : PASS
7101 23:06:02.149898 RX DQS gating : PASS
7102 23:06:02.152905 RX DQ/DQS(RDDQC) : PASS
7103 23:06:02.156382 TX DQ/DQS : PASS
7104 23:06:02.157004 RX DATLAT : PASS
7105 23:06:02.159712 RX DQ/DQS(Engine): PASS
7106 23:06:02.160376 TX OE : NO K
7107 23:06:02.162830 All Pass.
7108 23:06:02.163425
7109 23:06:02.163987 CH 0, Rank 1
7110 23:06:02.166092 SW Impedance : PASS
7111 23:06:02.166735 DUTY Scan : NO K
7112 23:06:02.169257 ZQ Calibration : PASS
7113 23:06:02.172473 Jitter Meter : NO K
7114 23:06:02.172954 CBT Training : PASS
7115 23:06:02.176085 Write leveling : NO K
7116 23:06:02.179234 RX DQS gating : PASS
7117 23:06:02.179812 RX DQ/DQS(RDDQC) : PASS
7118 23:06:02.182719 TX DQ/DQS : PASS
7119 23:06:02.186471 RX DATLAT : PASS
7120 23:06:02.187061 RX DQ/DQS(Engine): PASS
7121 23:06:02.189094 TX OE : NO K
7122 23:06:02.189666 All Pass.
7123 23:06:02.190076
7124 23:06:02.192427 CH 1, Rank 0
7125 23:06:02.192892 SW Impedance : PASS
7126 23:06:02.195644 DUTY Scan : NO K
7127 23:06:02.199123 ZQ Calibration : PASS
7128 23:06:02.199651 Jitter Meter : NO K
7129 23:06:02.202737 CBT Training : PASS
7130 23:06:02.205722 Write leveling : PASS
7131 23:06:02.206308 RX DQS gating : PASS
7132 23:06:02.209036 RX DQ/DQS(RDDQC) : PASS
7133 23:06:02.212082 TX DQ/DQS : PASS
7134 23:06:02.212509 RX DATLAT : PASS
7135 23:06:02.215193 RX DQ/DQS(Engine): PASS
7136 23:06:02.219443 TX OE : NO K
7137 23:06:02.219869 All Pass.
7138 23:06:02.220213
7139 23:06:02.220530 CH 1, Rank 1
7140 23:06:02.222013 SW Impedance : PASS
7141 23:06:02.225620 DUTY Scan : NO K
7142 23:06:02.226051 ZQ Calibration : PASS
7143 23:06:02.228921 Jitter Meter : NO K
7144 23:06:02.229348 CBT Training : PASS
7145 23:06:02.231734 Write leveling : NO K
7146 23:06:02.235730 RX DQS gating : PASS
7147 23:06:02.236246 RX DQ/DQS(RDDQC) : PASS
7148 23:06:02.238445 TX DQ/DQS : PASS
7149 23:06:02.242026 RX DATLAT : PASS
7150 23:06:02.242549 RX DQ/DQS(Engine): PASS
7151 23:06:02.245445 TX OE : NO K
7152 23:06:02.245986 All Pass.
7153 23:06:02.246337
7154 23:06:02.248559 DramC Write-DBI off
7155 23:06:02.251854 PER_BANK_REFRESH: Hybrid Mode
7156 23:06:02.252387 TX_TRACKING: ON
7157 23:06:02.261282 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7158 23:06:02.264733 [FAST_K] Save calibration result to emmc
7159 23:06:02.268274 dramc_set_vcore_voltage set vcore to 725000
7160 23:06:02.271336 Read voltage for 1600, 0
7161 23:06:02.271801 Vio18 = 0
7162 23:06:02.274836 Vcore = 725000
7163 23:06:02.275469 Vdram = 0
7164 23:06:02.275981 Vddq = 0
7165 23:06:02.276505 Vmddr = 0
7166 23:06:02.281211 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7167 23:06:02.287941 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7168 23:06:02.288485 MEM_TYPE=3, freq_sel=13
7169 23:06:02.291240 sv_algorithm_assistance_LP4_3733
7170 23:06:02.297740 ============ PULL DRAM RESETB DOWN ============
7171 23:06:02.301033 ========== PULL DRAM RESETB DOWN end =========
7172 23:06:02.304456 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7173 23:06:02.307731 ===================================
7174 23:06:02.310854 LPDDR4 DRAM CONFIGURATION
7175 23:06:02.313801 ===================================
7176 23:06:02.314433 EX_ROW_EN[0] = 0x0
7177 23:06:02.317286 EX_ROW_EN[1] = 0x0
7178 23:06:02.320382 LP4Y_EN = 0x0
7179 23:06:02.321007 WORK_FSP = 0x1
7180 23:06:02.323988 WL = 0x5
7181 23:06:02.324570 RL = 0x5
7182 23:06:02.327242 BL = 0x2
7183 23:06:02.327697 RPST = 0x0
7184 23:06:02.330270 RD_PRE = 0x0
7185 23:06:02.330747 WR_PRE = 0x1
7186 23:06:02.333734 WR_PST = 0x1
7187 23:06:02.334214 DBI_WR = 0x0
7188 23:06:02.337074 DBI_RD = 0x0
7189 23:06:02.337577 OTF = 0x1
7190 23:06:02.340560 ===================================
7191 23:06:02.343916 ===================================
7192 23:06:02.347101 ANA top config
7193 23:06:02.350491 ===================================
7194 23:06:02.353220 DLL_ASYNC_EN = 0
7195 23:06:02.353795 ALL_SLAVE_EN = 0
7196 23:06:02.357167 NEW_RANK_MODE = 1
7197 23:06:02.359992 DLL_IDLE_MODE = 1
7198 23:06:02.363350 LP45_APHY_COMB_EN = 1
7199 23:06:02.366868 TX_ODT_DIS = 0
7200 23:06:02.367461 NEW_8X_MODE = 1
7201 23:06:02.369981 ===================================
7202 23:06:02.373152 ===================================
7203 23:06:02.376547 data_rate = 3200
7204 23:06:02.379958 CKR = 1
7205 23:06:02.383436 DQ_P2S_RATIO = 8
7206 23:06:02.386524 ===================================
7207 23:06:02.390158 CA_P2S_RATIO = 8
7208 23:06:02.393042 DQ_CA_OPEN = 0
7209 23:06:02.393647 DQ_SEMI_OPEN = 0
7210 23:06:02.396401 CA_SEMI_OPEN = 0
7211 23:06:02.399442 CA_FULL_RATE = 0
7212 23:06:02.403082 DQ_CKDIV4_EN = 0
7213 23:06:02.406285 CA_CKDIV4_EN = 0
7214 23:06:02.409628 CA_PREDIV_EN = 0
7215 23:06:02.410236 PH8_DLY = 12
7216 23:06:02.412868 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7217 23:06:02.416414 DQ_AAMCK_DIV = 4
7218 23:06:02.419273 CA_AAMCK_DIV = 4
7219 23:06:02.423130 CA_ADMCK_DIV = 4
7220 23:06:02.425744 DQ_TRACK_CA_EN = 0
7221 23:06:02.429282 CA_PICK = 1600
7222 23:06:02.429862 CA_MCKIO = 1600
7223 23:06:02.432211 MCKIO_SEMI = 0
7224 23:06:02.436044 PLL_FREQ = 3068
7225 23:06:02.438807 DQ_UI_PI_RATIO = 32
7226 23:06:02.442439 CA_UI_PI_RATIO = 0
7227 23:06:02.445815 ===================================
7228 23:06:02.448815 ===================================
7229 23:06:02.452287 memory_type:LPDDR4
7230 23:06:02.452773 GP_NUM : 10
7231 23:06:02.455294 SRAM_EN : 1
7232 23:06:02.455719 MD32_EN : 0
7233 23:06:02.458824 ===================================
7234 23:06:02.462105 [ANA_INIT] >>>>>>>>>>>>>>
7235 23:06:02.465528 <<<<<< [CONFIGURE PHASE]: ANA_TX
7236 23:06:02.468755 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7237 23:06:02.471952 ===================================
7238 23:06:02.475156 data_rate = 3200,PCW = 0X7600
7239 23:06:02.478638 ===================================
7240 23:06:02.482402 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7241 23:06:02.488460 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7242 23:06:02.491828 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7243 23:06:02.498483 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7244 23:06:02.502235 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7245 23:06:02.504835 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7246 23:06:02.505262 [ANA_INIT] flow start
7247 23:06:02.509050 [ANA_INIT] PLL >>>>>>>>
7248 23:06:02.511823 [ANA_INIT] PLL <<<<<<<<
7249 23:06:02.512241 [ANA_INIT] MIDPI >>>>>>>>
7250 23:06:02.515181 [ANA_INIT] MIDPI <<<<<<<<
7251 23:06:02.518347 [ANA_INIT] DLL >>>>>>>>
7252 23:06:02.521808 [ANA_INIT] DLL <<<<<<<<
7253 23:06:02.522230 [ANA_INIT] flow end
7254 23:06:02.525027 ============ LP4 DIFF to SE enter ============
7255 23:06:02.531294 ============ LP4 DIFF to SE exit ============
7256 23:06:02.531376 [ANA_INIT] <<<<<<<<<<<<<
7257 23:06:02.534669 [Flow] Enable top DCM control >>>>>
7258 23:06:02.537468 [Flow] Enable top DCM control <<<<<
7259 23:06:02.540862 Enable DLL master slave shuffle
7260 23:06:02.547354 ==============================================================
7261 23:06:02.547437 Gating Mode config
7262 23:06:02.553906 ==============================================================
7263 23:06:02.558056 Config description:
7264 23:06:02.567650 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7265 23:06:02.574367 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7266 23:06:02.577383 SELPH_MODE 0: By rank 1: By Phase
7267 23:06:02.584009 ==============================================================
7268 23:06:02.587176 GAT_TRACK_EN = 1
7269 23:06:02.590987 RX_GATING_MODE = 2
7270 23:06:02.594522 RX_GATING_TRACK_MODE = 2
7271 23:06:02.594745 SELPH_MODE = 1
7272 23:06:02.597310 PICG_EARLY_EN = 1
7273 23:06:02.600417 VALID_LAT_VALUE = 1
7274 23:06:02.607069 ==============================================================
7275 23:06:02.610212 Enter into Gating configuration >>>>
7276 23:06:02.614009 Exit from Gating configuration <<<<
7277 23:06:02.616830 Enter into DVFS_PRE_config >>>>>
7278 23:06:02.627230 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7279 23:06:02.630678 Exit from DVFS_PRE_config <<<<<
7280 23:06:02.633327 Enter into PICG configuration >>>>
7281 23:06:02.636712 Exit from PICG configuration <<<<
7282 23:06:02.639970 [RX_INPUT] configuration >>>>>
7283 23:06:02.643298 [RX_INPUT] configuration <<<<<
7284 23:06:02.646550 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7285 23:06:02.653203 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7286 23:06:02.660140 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7287 23:06:02.666482 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7288 23:06:02.673206 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7289 23:06:02.679894 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7290 23:06:02.682933 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7291 23:06:02.686067 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7292 23:06:02.690009 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7293 23:06:02.696403 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7294 23:06:02.699974 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7295 23:06:02.702754 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7296 23:06:02.706264 ===================================
7297 23:06:02.709391 LPDDR4 DRAM CONFIGURATION
7298 23:06:02.712738 ===================================
7299 23:06:02.713162 EX_ROW_EN[0] = 0x0
7300 23:06:02.716066 EX_ROW_EN[1] = 0x0
7301 23:06:02.716552 LP4Y_EN = 0x0
7302 23:06:02.719112 WORK_FSP = 0x1
7303 23:06:02.722618 WL = 0x5
7304 23:06:02.723042 RL = 0x5
7305 23:06:02.726174 BL = 0x2
7306 23:06:02.726599 RPST = 0x0
7307 23:06:02.729379 RD_PRE = 0x0
7308 23:06:02.729822 WR_PRE = 0x1
7309 23:06:02.732687 WR_PST = 0x1
7310 23:06:02.733106 DBI_WR = 0x0
7311 23:06:02.735780 DBI_RD = 0x0
7312 23:06:02.736204 OTF = 0x1
7313 23:06:02.739324 ===================================
7314 23:06:02.742572 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7315 23:06:02.748951 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7316 23:06:02.752370 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7317 23:06:02.755760 ===================================
7318 23:06:02.759516 LPDDR4 DRAM CONFIGURATION
7319 23:06:02.761975 ===================================
7320 23:06:02.762399 EX_ROW_EN[0] = 0x10
7321 23:06:02.765353 EX_ROW_EN[1] = 0x0
7322 23:06:02.768958 LP4Y_EN = 0x0
7323 23:06:02.769394 WORK_FSP = 0x1
7324 23:06:02.771971 WL = 0x5
7325 23:06:02.772390 RL = 0x5
7326 23:06:02.775242 BL = 0x2
7327 23:06:02.775664 RPST = 0x0
7328 23:06:02.778824 RD_PRE = 0x0
7329 23:06:02.779280 WR_PRE = 0x1
7330 23:06:02.781937 WR_PST = 0x1
7331 23:06:02.782359 DBI_WR = 0x0
7332 23:06:02.784950 DBI_RD = 0x0
7333 23:06:02.785539 OTF = 0x1
7334 23:06:02.788078 ===================================
7335 23:06:02.795293 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7336 23:06:02.795825 ==
7337 23:06:02.798758 Dram Type= 6, Freq= 0, CH_0, rank 0
7338 23:06:02.805308 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7339 23:06:02.805787 ==
7340 23:06:02.806129 [Duty_Offset_Calibration]
7341 23:06:02.808669 B0:1 B1:-1 CA:0
7342 23:06:02.809090
7343 23:06:02.811400 [DutyScan_Calibration_Flow] k_type=0
7344 23:06:02.820925
7345 23:06:02.821516 ==CLK 0==
7346 23:06:02.823866 Final CLK duty delay cell = 0
7347 23:06:02.827682 [0] MAX Duty = 5124%(X100), DQS PI = 22
7348 23:06:02.830818 [0] MIN Duty = 4907%(X100), DQS PI = 4
7349 23:06:02.831242 [0] AVG Duty = 5015%(X100)
7350 23:06:02.833832
7351 23:06:02.837334 CH0 CLK Duty spec in!! Max-Min= 217%
7352 23:06:02.840412 [DutyScan_Calibration_Flow] ====Done====
7353 23:06:02.841108
7354 23:06:02.844082 [DutyScan_Calibration_Flow] k_type=1
7355 23:06:02.860426
7356 23:06:02.860963 ==DQS 0 ==
7357 23:06:02.863092 Final DQS duty delay cell = -4
7358 23:06:02.866678 [-4] MAX Duty = 4969%(X100), DQS PI = 18
7359 23:06:02.869578 [-4] MIN Duty = 4844%(X100), DQS PI = 56
7360 23:06:02.872694 [-4] AVG Duty = 4906%(X100)
7361 23:06:02.873114
7362 23:06:02.873480 ==DQS 1 ==
7363 23:06:02.876209 Final DQS duty delay cell = 0
7364 23:06:02.879261 [0] MAX Duty = 5156%(X100), DQS PI = 2
7365 23:06:02.882697 [0] MIN Duty = 5031%(X100), DQS PI = 20
7366 23:06:02.886144 [0] AVG Duty = 5093%(X100)
7367 23:06:02.886564
7368 23:06:02.889739 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7369 23:06:02.890162
7370 23:06:02.892933 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7371 23:06:02.896178 [DutyScan_Calibration_Flow] ====Done====
7372 23:06:02.896602
7373 23:06:02.899300 [DutyScan_Calibration_Flow] k_type=3
7374 23:06:02.917303
7375 23:06:02.917769 ==DQM 0 ==
7376 23:06:02.920474 Final DQM duty delay cell = 0
7377 23:06:02.924074 [0] MAX Duty = 5093%(X100), DQS PI = 18
7378 23:06:02.927431 [0] MIN Duty = 4907%(X100), DQS PI = 10
7379 23:06:02.930358 [0] AVG Duty = 5000%(X100)
7380 23:06:02.930780
7381 23:06:02.931114 ==DQM 1 ==
7382 23:06:02.934107 Final DQM duty delay cell = 0
7383 23:06:02.937400 [0] MAX Duty = 5000%(X100), DQS PI = 8
7384 23:06:02.940164 [0] MIN Duty = 4813%(X100), DQS PI = 20
7385 23:06:02.943805 [0] AVG Duty = 4906%(X100)
7386 23:06:02.944227
7387 23:06:02.946939 CH0 DQM 0 Duty spec in!! Max-Min= 186%
7388 23:06:02.947363
7389 23:06:02.950252 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7390 23:06:02.954000 [DutyScan_Calibration_Flow] ====Done====
7391 23:06:02.954424
7392 23:06:02.956598 [DutyScan_Calibration_Flow] k_type=2
7393 23:06:02.973512
7394 23:06:02.973938 ==DQ 0 ==
7395 23:06:02.976838 Final DQ duty delay cell = -4
7396 23:06:02.980077 [-4] MAX Duty = 5031%(X100), DQS PI = 26
7397 23:06:02.983401 [-4] MIN Duty = 4876%(X100), DQS PI = 50
7398 23:06:02.987305 [-4] AVG Duty = 4953%(X100)
7399 23:06:02.987747
7400 23:06:02.988124 ==DQ 1 ==
7401 23:06:02.989852 Final DQ duty delay cell = 0
7402 23:06:02.993305 [0] MAX Duty = 5125%(X100), DQS PI = 4
7403 23:06:02.996462 [0] MIN Duty = 5000%(X100), DQS PI = 38
7404 23:06:03.000132 [0] AVG Duty = 5062%(X100)
7405 23:06:03.000554
7406 23:06:03.003200 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7407 23:06:03.003620
7408 23:06:03.006529 CH0 DQ 1 Duty spec in!! Max-Min= 125%
7409 23:06:03.009901 [DutyScan_Calibration_Flow] ====Done====
7410 23:06:03.010321 ==
7411 23:06:03.013199 Dram Type= 6, Freq= 0, CH_1, rank 0
7412 23:06:03.016710 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7413 23:06:03.017138 ==
7414 23:06:03.019915 [Duty_Offset_Calibration]
7415 23:06:03.020334 B0:-1 B1:1 CA:2
7416 23:06:03.020706
7417 23:06:03.023500 [DutyScan_Calibration_Flow] k_type=0
7418 23:06:03.033877
7419 23:06:03.034295 ==CLK 0==
7420 23:06:03.037336 Final CLK duty delay cell = 0
7421 23:06:03.040953 [0] MAX Duty = 5187%(X100), DQS PI = 22
7422 23:06:03.044116 [0] MIN Duty = 4969%(X100), DQS PI = 62
7423 23:06:03.047333 [0] AVG Duty = 5078%(X100)
7424 23:06:03.047883
7425 23:06:03.050746 CH1 CLK Duty spec in!! Max-Min= 218%
7426 23:06:03.053996 [DutyScan_Calibration_Flow] ====Done====
7427 23:06:03.054648
7428 23:06:03.057889 [DutyScan_Calibration_Flow] k_type=1
7429 23:06:03.074042
7430 23:06:03.074568 ==DQS 0 ==
7431 23:06:03.077110 Final DQS duty delay cell = 0
7432 23:06:03.080844 [0] MAX Duty = 5124%(X100), DQS PI = 18
7433 23:06:03.083719 [0] MIN Duty = 4907%(X100), DQS PI = 10
7434 23:06:03.087342 [0] AVG Duty = 5015%(X100)
7435 23:06:03.087884
7436 23:06:03.088321 ==DQS 1 ==
7437 23:06:03.090624 Final DQS duty delay cell = 0
7438 23:06:03.094364 [0] MAX Duty = 5093%(X100), DQS PI = 10
7439 23:06:03.097585 [0] MIN Duty = 4969%(X100), DQS PI = 56
7440 23:06:03.100556 [0] AVG Duty = 5031%(X100)
7441 23:06:03.100984
7442 23:06:03.104068 CH1 DQS 0 Duty spec in!! Max-Min= 217%
7443 23:06:03.104493
7444 23:06:03.107181 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7445 23:06:03.110706 [DutyScan_Calibration_Flow] ====Done====
7446 23:06:03.111319
7447 23:06:03.113475 [DutyScan_Calibration_Flow] k_type=3
7448 23:06:03.130101
7449 23:06:03.130718 ==DQM 0 ==
7450 23:06:03.133482 Final DQM duty delay cell = -4
7451 23:06:03.136409 [-4] MAX Duty = 5062%(X100), DQS PI = 18
7452 23:06:03.139766 [-4] MIN Duty = 4782%(X100), DQS PI = 8
7453 23:06:03.143168 [-4] AVG Duty = 4922%(X100)
7454 23:06:03.143596
7455 23:06:03.143936 ==DQM 1 ==
7456 23:06:03.146240 Final DQM duty delay cell = 0
7457 23:06:03.149554 [0] MAX Duty = 5156%(X100), DQS PI = 2
7458 23:06:03.153356 [0] MIN Duty = 4969%(X100), DQS PI = 28
7459 23:06:03.156738 [0] AVG Duty = 5062%(X100)
7460 23:06:03.157160
7461 23:06:03.160091 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7462 23:06:03.160574
7463 23:06:03.162748 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7464 23:06:03.166368 [DutyScan_Calibration_Flow] ====Done====
7465 23:06:03.166797
7466 23:06:03.169539 [DutyScan_Calibration_Flow] k_type=2
7467 23:06:03.187709
7468 23:06:03.188306 ==DQ 0 ==
7469 23:06:03.190168 Final DQ duty delay cell = 0
7470 23:06:03.194021 [0] MAX Duty = 5156%(X100), DQS PI = 30
7471 23:06:03.197478 [0] MIN Duty = 4906%(X100), DQS PI = 10
7472 23:06:03.198017 [0] AVG Duty = 5031%(X100)
7473 23:06:03.200448
7474 23:06:03.200999 ==DQ 1 ==
7475 23:06:03.204334 Final DQ duty delay cell = 0
7476 23:06:03.206782 [0] MAX Duty = 5156%(X100), DQS PI = 8
7477 23:06:03.210613 [0] MIN Duty = 4969%(X100), DQS PI = 56
7478 23:06:03.211043 [0] AVG Duty = 5062%(X100)
7479 23:06:03.213392
7480 23:06:03.217072 CH1 DQ 0 Duty spec in!! Max-Min= 250%
7481 23:06:03.217541
7482 23:06:03.220290 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7483 23:06:03.223389 [DutyScan_Calibration_Flow] ====Done====
7484 23:06:03.226710 nWR fixed to 30
7485 23:06:03.227142 [ModeRegInit_LP4] CH0 RK0
7486 23:06:03.230294 [ModeRegInit_LP4] CH0 RK1
7487 23:06:03.233305 [ModeRegInit_LP4] CH1 RK0
7488 23:06:03.237168 [ModeRegInit_LP4] CH1 RK1
7489 23:06:03.237643 match AC timing 5
7490 23:06:03.243278 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7491 23:06:03.246873 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7492 23:06:03.249971 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7493 23:06:03.256884 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7494 23:06:03.259761 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7495 23:06:03.260190 [MiockJmeterHQA]
7496 23:06:03.260527
7497 23:06:03.263280 [DramcMiockJmeter] u1RxGatingPI = 0
7498 23:06:03.266569 0 : 4253, 4026
7499 23:06:03.267003 4 : 4363, 4137
7500 23:06:03.269713 8 : 4252, 4027
7501 23:06:03.270150 12 : 4363, 4138
7502 23:06:03.270502 16 : 4253, 4027
7503 23:06:03.272894 20 : 4252, 4027
7504 23:06:03.273327 24 : 4252, 4027
7505 23:06:03.276675 28 : 4254, 4029
7506 23:06:03.277210 32 : 4361, 4137
7507 23:06:03.279594 36 : 4250, 4027
7508 23:06:03.280028 40 : 4250, 4026
7509 23:06:03.283291 44 : 4252, 4027
7510 23:06:03.283721 48 : 4252, 4029
7511 23:06:03.284067 52 : 4250, 4027
7512 23:06:03.286812 56 : 4360, 4138
7513 23:06:03.287243 60 : 4360, 4137
7514 23:06:03.289984 64 : 4250, 4027
7515 23:06:03.290417 68 : 4253, 4027
7516 23:06:03.292969 72 : 4250, 4027
7517 23:06:03.293399 76 : 4253, 4029
7518 23:06:03.296058 80 : 4252, 4029
7519 23:06:03.296603 84 : 4361, 4137
7520 23:06:03.296954 88 : 4250, 4027
7521 23:06:03.299314 92 : 4250, 674
7522 23:06:03.299749 96 : 4360, 0
7523 23:06:03.302568 100 : 4252, 0
7524 23:06:03.303003 104 : 4252, 0
7525 23:06:03.303349 108 : 4252, 0
7526 23:06:03.306407 112 : 4250, 0
7527 23:06:03.306839 116 : 4250, 0
7528 23:06:03.309276 120 : 4252, 0
7529 23:06:03.309743 124 : 4250, 0
7530 23:06:03.310095 128 : 4250, 0
7531 23:06:03.313132 132 : 4363, 0
7532 23:06:03.313721 136 : 4250, 0
7533 23:06:03.315699 140 : 4252, 0
7534 23:06:03.316135 144 : 4250, 0
7535 23:06:03.316489 148 : 4250, 0
7536 23:06:03.319184 152 : 4250, 0
7537 23:06:03.319617 156 : 4250, 0
7538 23:06:03.322697 160 : 4252, 0
7539 23:06:03.323146 164 : 4250, 0
7540 23:06:03.323491 168 : 4250, 0
7541 23:06:03.326176 172 : 4252, 0
7542 23:06:03.326610 176 : 4253, 0
7543 23:06:03.328888 180 : 4361, 0
7544 23:06:03.329325 184 : 4360, 0
7545 23:06:03.329716 188 : 4250, 0
7546 23:06:03.332847 192 : 4360, 0
7547 23:06:03.333278 196 : 4250, 0
7548 23:06:03.333666 200 : 4250, 0
7549 23:06:03.335831 204 : 4250, 0
7550 23:06:03.336310 208 : 4250, 0
7551 23:06:03.339135 212 : 4250, 0
7552 23:06:03.339571 216 : 4250, 0
7553 23:06:03.339921 220 : 4250, 0
7554 23:06:03.342668 224 : 4252, 185
7555 23:06:03.343100 228 : 4361, 3594
7556 23:06:03.345448 232 : 4250, 4027
7557 23:06:03.345884 236 : 4250, 4027
7558 23:06:03.349195 240 : 4361, 4137
7559 23:06:03.349662 244 : 4250, 4026
7560 23:06:03.352582 248 : 4250, 4027
7561 23:06:03.353013 252 : 4250, 4027
7562 23:06:03.356459 256 : 4252, 4029
7563 23:06:03.356997 260 : 4250, 4026
7564 23:06:03.358869 264 : 4250, 4027
7565 23:06:03.359243 268 : 4360, 4138
7566 23:06:03.359571 272 : 4249, 4027
7567 23:06:03.362350 276 : 4250, 4026
7568 23:06:03.362897 280 : 4361, 4137
7569 23:06:03.365632 284 : 4250, 4027
7570 23:06:03.366077 288 : 4250, 4027
7571 23:06:03.368545 292 : 4362, 4140
7572 23:06:03.368975 296 : 4250, 4026
7573 23:06:03.372141 300 : 4250, 4027
7574 23:06:03.372679 304 : 4250, 4027
7575 23:06:03.375157 308 : 4252, 4029
7576 23:06:03.375590 312 : 4250, 4026
7577 23:06:03.379409 316 : 4250, 4027
7578 23:06:03.379841 320 : 4360, 4138
7579 23:06:03.382065 324 : 4249, 4027
7580 23:06:03.382492 328 : 4250, 4026
7581 23:06:03.385153 332 : 4361, 4137
7582 23:06:03.385617 336 : 4250, 3902
7583 23:06:03.388730 340 : 4250, 2108
7584 23:06:03.389158
7585 23:06:03.389528 MIOCK jitter meter ch=0
7586 23:06:03.389844
7587 23:06:03.391760 1T = (340-92) = 248 dly cells
7588 23:06:03.398156 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 262/100 ps
7589 23:06:03.398580 ==
7590 23:06:03.401481 Dram Type= 6, Freq= 0, CH_0, rank 0
7591 23:06:03.405061 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7592 23:06:03.405519 ==
7593 23:06:03.411361 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7594 23:06:03.414481 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7595 23:06:03.417944 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7596 23:06:03.424786 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7597 23:06:03.434808 [CA 0] Center 43 (12~74) winsize 63
7598 23:06:03.437842 [CA 1] Center 42 (12~73) winsize 62
7599 23:06:03.441274 [CA 2] Center 38 (9~68) winsize 60
7600 23:06:03.444500 [CA 3] Center 38 (8~68) winsize 61
7601 23:06:03.447975 [CA 4] Center 36 (7~66) winsize 60
7602 23:06:03.451093 [CA 5] Center 35 (6~65) winsize 60
7603 23:06:03.451519
7604 23:06:03.454368 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7605 23:06:03.454893
7606 23:06:03.457835 [CATrainingPosCal] consider 1 rank data
7607 23:06:03.460936 u2DelayCellTimex100 = 262/100 ps
7608 23:06:03.467394 CA0 delay=43 (12~74),Diff = 8 PI (29 cell)
7609 23:06:03.470335 CA1 delay=42 (12~73),Diff = 7 PI (26 cell)
7610 23:06:03.473961 CA2 delay=38 (9~68),Diff = 3 PI (11 cell)
7611 23:06:03.476834 CA3 delay=38 (8~68),Diff = 3 PI (11 cell)
7612 23:06:03.480516 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7613 23:06:03.483448 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7614 23:06:03.484088
7615 23:06:03.487115 CA PerBit enable=1, Macro0, CA PI delay=35
7616 23:06:03.487722
7617 23:06:03.490098 [CBTSetCACLKResult] CA Dly = 35
7618 23:06:03.494207 CS Dly: 11 (0~42)
7619 23:06:03.497187 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7620 23:06:03.501058 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7621 23:06:03.501736 ==
7622 23:06:03.503239 Dram Type= 6, Freq= 0, CH_0, rank 1
7623 23:06:03.509869 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7624 23:06:03.510553 ==
7625 23:06:03.513357 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7626 23:06:03.519881 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7627 23:06:03.523585 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7628 23:06:03.529642 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7629 23:06:03.538136 [CA 0] Center 42 (12~73) winsize 62
7630 23:06:03.541643 [CA 1] Center 43 (13~73) winsize 61
7631 23:06:03.544261 [CA 2] Center 37 (8~67) winsize 60
7632 23:06:03.547429 [CA 3] Center 37 (7~67) winsize 61
7633 23:06:03.550835 [CA 4] Center 36 (6~66) winsize 61
7634 23:06:03.554272 [CA 5] Center 35 (5~65) winsize 61
7635 23:06:03.554828
7636 23:06:03.557529 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7637 23:06:03.558059
7638 23:06:03.563704 [CATrainingPosCal] consider 2 rank data
7639 23:06:03.564318 u2DelayCellTimex100 = 262/100 ps
7640 23:06:03.570780 CA0 delay=42 (12~73),Diff = 7 PI (26 cell)
7641 23:06:03.574456 CA1 delay=43 (13~73),Diff = 8 PI (29 cell)
7642 23:06:03.577227 CA2 delay=38 (9~67),Diff = 3 PI (11 cell)
7643 23:06:03.580630 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7644 23:06:03.583758 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7645 23:06:03.587052 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7646 23:06:03.587490
7647 23:06:03.590465 CA PerBit enable=1, Macro0, CA PI delay=35
7648 23:06:03.590907
7649 23:06:03.593789 [CBTSetCACLKResult] CA Dly = 35
7650 23:06:03.596818 CS Dly: 11 (0~43)
7651 23:06:03.600559 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7652 23:06:03.604033 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7653 23:06:03.604469
7654 23:06:03.607228 ----->DramcWriteLeveling(PI) begin...
7655 23:06:03.607670 ==
7656 23:06:03.610582 Dram Type= 6, Freq= 0, CH_0, rank 0
7657 23:06:03.617465 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7658 23:06:03.618019 ==
7659 23:06:03.620013 Write leveling (Byte 0): 38 => 38
7660 23:06:03.623383 Write leveling (Byte 1): 28 => 28
7661 23:06:03.626659 DramcWriteLeveling(PI) end<-----
7662 23:06:03.627095
7663 23:06:03.627542 ==
7664 23:06:03.630127 Dram Type= 6, Freq= 0, CH_0, rank 0
7665 23:06:03.633189 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7666 23:06:03.633656 ==
7667 23:06:03.637094 [Gating] SW mode calibration
7668 23:06:03.642997 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7669 23:06:03.649921 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7670 23:06:03.653627 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7671 23:06:03.656455 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7672 23:06:03.663176 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7673 23:06:03.666292 1 4 12 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
7674 23:06:03.669360 1 4 16 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7675 23:06:03.676230 1 4 20 | B1->B0 | 2726 3434 | 1 1 | (0 0) (1 1)
7676 23:06:03.679184 1 4 24 | B1->B0 | 3232 3434 | 0 1 | (1 1) (1 1)
7677 23:06:03.682665 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7678 23:06:03.689501 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7679 23:06:03.692771 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7680 23:06:03.696409 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7681 23:06:03.699475 1 5 12 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (0 0)
7682 23:06:03.706306 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7683 23:06:03.709322 1 5 20 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
7684 23:06:03.712755 1 5 24 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
7685 23:06:03.719565 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7686 23:06:03.722791 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7687 23:06:03.725779 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7688 23:06:03.732513 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7689 23:06:03.736014 1 6 12 | B1->B0 | 2323 3636 | 0 1 | (0 0) (0 0)
7690 23:06:03.739247 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7691 23:06:03.745380 1 6 20 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
7692 23:06:03.748671 1 6 24 | B1->B0 | 3d3d 4646 | 1 0 | (0 0) (0 0)
7693 23:06:03.755802 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7694 23:06:03.758810 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7695 23:06:03.761697 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7696 23:06:03.765163 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7697 23:06:03.771670 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7698 23:06:03.775046 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7699 23:06:03.781917 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7700 23:06:03.784800 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7701 23:06:03.788412 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7702 23:06:03.794854 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7703 23:06:03.798118 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7704 23:06:03.801726 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7705 23:06:03.808531 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7706 23:06:03.811776 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7707 23:06:03.815285 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7708 23:06:03.821558 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7709 23:06:03.824688 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7710 23:06:03.827747 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7711 23:06:03.834694 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7712 23:06:03.837170 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7713 23:06:03.840495 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7714 23:06:03.847298 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7715 23:06:03.847403 Total UI for P1: 0, mck2ui 16
7716 23:06:03.850263 best dqsien dly found for B0: ( 1, 9, 10)
7717 23:06:03.857014 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7718 23:06:03.860193 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7719 23:06:03.863622 Total UI for P1: 0, mck2ui 16
7720 23:06:03.867573 best dqsien dly found for B1: ( 1, 9, 20)
7721 23:06:03.870182 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7722 23:06:03.873697 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7723 23:06:03.873805
7724 23:06:03.876792 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7725 23:06:03.883866 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7726 23:06:03.883945 [Gating] SW calibration Done
7727 23:06:03.887777 ==
7728 23:06:03.890315 Dram Type= 6, Freq= 0, CH_0, rank 0
7729 23:06:03.893603 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7730 23:06:03.893777 ==
7731 23:06:03.893863 RX Vref Scan: 0
7732 23:06:03.893940
7733 23:06:03.896593 RX Vref 0 -> 0, step: 1
7734 23:06:03.896722
7735 23:06:03.900206 RX Delay 0 -> 252, step: 8
7736 23:06:03.903257 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7737 23:06:03.906832 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7738 23:06:03.909585 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7739 23:06:03.916480 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
7740 23:06:03.919443 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7741 23:06:03.923446 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7742 23:06:03.926619 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7743 23:06:03.929865 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7744 23:06:03.936722 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7745 23:06:03.939484 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7746 23:06:03.943089 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7747 23:06:03.946693 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7748 23:06:03.953056 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7749 23:06:03.956225 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7750 23:06:03.959636 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7751 23:06:03.962907 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7752 23:06:03.963448 ==
7753 23:06:03.966057 Dram Type= 6, Freq= 0, CH_0, rank 0
7754 23:06:03.972903 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7755 23:06:03.973334 ==
7756 23:06:03.973706 DQS Delay:
7757 23:06:03.976187 DQS0 = 0, DQS1 = 0
7758 23:06:03.976713 DQM Delay:
7759 23:06:03.977056 DQM0 = 136, DQM1 = 126
7760 23:06:03.980236 DQ Delay:
7761 23:06:03.982612 DQ0 =135, DQ1 =139, DQ2 =131, DQ3 =135
7762 23:06:03.985777 DQ4 =139, DQ5 =123, DQ6 =143, DQ7 =147
7763 23:06:03.988830 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =119
7764 23:06:03.992272 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =131
7765 23:06:03.992697
7766 23:06:03.993035
7767 23:06:03.993345 ==
7768 23:06:03.995675 Dram Type= 6, Freq= 0, CH_0, rank 0
7769 23:06:04.002386 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7770 23:06:04.002812 ==
7771 23:06:04.003195
7772 23:06:04.003546
7773 23:06:04.003850 TX Vref Scan disable
7774 23:06:04.005608 == TX Byte 0 ==
7775 23:06:04.008938 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
7776 23:06:04.015191 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7777 23:06:04.015614 == TX Byte 1 ==
7778 23:06:04.018919 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7779 23:06:04.025478 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7780 23:06:04.025902 ==
7781 23:06:04.028717 Dram Type= 6, Freq= 0, CH_0, rank 0
7782 23:06:04.031762 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7783 23:06:04.032188 ==
7784 23:06:04.045276
7785 23:06:04.048548 TX Vref early break, caculate TX vref
7786 23:06:04.052443 TX Vref=16, minBit 6, minWin=22, winSum=373
7787 23:06:04.055814 TX Vref=18, minBit 1, minWin=23, winSum=384
7788 23:06:04.059250 TX Vref=20, minBit 1, minWin=24, winSum=396
7789 23:06:04.061599 TX Vref=22, minBit 1, minWin=24, winSum=402
7790 23:06:04.064883 TX Vref=24, minBit 1, minWin=24, winSum=408
7791 23:06:04.071491 TX Vref=26, minBit 0, minWin=26, winSum=423
7792 23:06:04.074920 TX Vref=28, minBit 4, minWin=25, winSum=423
7793 23:06:04.078189 TX Vref=30, minBit 0, minWin=24, winSum=412
7794 23:06:04.081359 TX Vref=32, minBit 0, minWin=24, winSum=403
7795 23:06:04.084561 TX Vref=34, minBit 7, minWin=23, winSum=394
7796 23:06:04.091601 [TxChooseVref] Worse bit 0, Min win 26, Win sum 423, Final Vref 26
7797 23:06:04.092028
7798 23:06:04.094817 Final TX Range 0 Vref 26
7799 23:06:04.095243
7800 23:06:04.095578 ==
7801 23:06:04.098452 Dram Type= 6, Freq= 0, CH_0, rank 0
7802 23:06:04.101200 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7803 23:06:04.101670 ==
7804 23:06:04.102012
7805 23:06:04.102323
7806 23:06:04.104326 TX Vref Scan disable
7807 23:06:04.111527 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
7808 23:06:04.111953 == TX Byte 0 ==
7809 23:06:04.114573 u2DelayCellOfst[0]=14 cells (4 PI)
7810 23:06:04.118130 u2DelayCellOfst[1]=18 cells (5 PI)
7811 23:06:04.120958 u2DelayCellOfst[2]=14 cells (4 PI)
7812 23:06:04.124658 u2DelayCellOfst[3]=14 cells (4 PI)
7813 23:06:04.127823 u2DelayCellOfst[4]=11 cells (3 PI)
7814 23:06:04.131729 u2DelayCellOfst[5]=0 cells (0 PI)
7815 23:06:04.135023 u2DelayCellOfst[6]=22 cells (6 PI)
7816 23:06:04.137970 u2DelayCellOfst[7]=22 cells (6 PI)
7817 23:06:04.141175 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7818 23:06:04.144155 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7819 23:06:04.147448 == TX Byte 1 ==
7820 23:06:04.151158 u2DelayCellOfst[8]=0 cells (0 PI)
7821 23:06:04.154505 u2DelayCellOfst[9]=0 cells (0 PI)
7822 23:06:04.157327 u2DelayCellOfst[10]=7 cells (2 PI)
7823 23:06:04.157783 u2DelayCellOfst[11]=0 cells (0 PI)
7824 23:06:04.161049 u2DelayCellOfst[12]=11 cells (3 PI)
7825 23:06:04.164254 u2DelayCellOfst[13]=11 cells (3 PI)
7826 23:06:04.168000 u2DelayCellOfst[14]=14 cells (4 PI)
7827 23:06:04.170846 u2DelayCellOfst[15]=11 cells (3 PI)
7828 23:06:04.177306 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7829 23:06:04.180825 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7830 23:06:04.181533 DramC Write-DBI on
7831 23:06:04.184254 ==
7832 23:06:04.184847 Dram Type= 6, Freq= 0, CH_0, rank 0
7833 23:06:04.190470 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7834 23:06:04.190899 ==
7835 23:06:04.191268
7836 23:06:04.191653
7837 23:06:04.193567 TX Vref Scan disable
7838 23:06:04.194280 == TX Byte 0 ==
7839 23:06:04.200034 Update DQM dly =738 (2 ,6, 34) DQM OEN =(3 ,3)
7840 23:06:04.200573 == TX Byte 1 ==
7841 23:06:04.203694 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7842 23:06:04.206935 DramC Write-DBI off
7843 23:06:04.207370
7844 23:06:04.207783 [DATLAT]
7845 23:06:04.210509 Freq=1600, CH0 RK0
7846 23:06:04.210934
7847 23:06:04.211268 DATLAT Default: 0xf
7848 23:06:04.213479 0, 0xFFFF, sum = 0
7849 23:06:04.213908 1, 0xFFFF, sum = 0
7850 23:06:04.217258 2, 0xFFFF, sum = 0
7851 23:06:04.217766 3, 0xFFFF, sum = 0
7852 23:06:04.220749 4, 0xFFFF, sum = 0
7853 23:06:04.221180 5, 0xFFFF, sum = 0
7854 23:06:04.223636 6, 0xFFFF, sum = 0
7855 23:06:04.226725 7, 0xFFFF, sum = 0
7856 23:06:04.227153 8, 0xFFFF, sum = 0
7857 23:06:04.230192 9, 0xFFFF, sum = 0
7858 23:06:04.230621 10, 0xFFFF, sum = 0
7859 23:06:04.233509 11, 0xFFFF, sum = 0
7860 23:06:04.233965 12, 0xFFFF, sum = 0
7861 23:06:04.236919 13, 0xFFFF, sum = 0
7862 23:06:04.237348 14, 0x0, sum = 1
7863 23:06:04.240090 15, 0x0, sum = 2
7864 23:06:04.240517 16, 0x0, sum = 3
7865 23:06:04.243534 17, 0x0, sum = 4
7866 23:06:04.243961 best_step = 15
7867 23:06:04.244296
7868 23:06:04.244609 ==
7869 23:06:04.246733 Dram Type= 6, Freq= 0, CH_0, rank 0
7870 23:06:04.249861 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7871 23:06:04.253482 ==
7872 23:06:04.253882 RX Vref Scan: 1
7873 23:06:04.254215
7874 23:06:04.256810 Set Vref Range= 24 -> 127
7875 23:06:04.257230
7876 23:06:04.257618 RX Vref 24 -> 127, step: 1
7877 23:06:04.259886
7878 23:06:04.260304 RX Delay 11 -> 252, step: 4
7879 23:06:04.260642
7880 23:06:04.263271 Set Vref, RX VrefLevel [Byte0]: 24
7881 23:06:04.266514 [Byte1]: 24
7882 23:06:04.270035
7883 23:06:04.270457 Set Vref, RX VrefLevel [Byte0]: 25
7884 23:06:04.273547 [Byte1]: 25
7885 23:06:04.277732
7886 23:06:04.278334 Set Vref, RX VrefLevel [Byte0]: 26
7887 23:06:04.280857 [Byte1]: 26
7888 23:06:04.285674
7889 23:06:04.286289 Set Vref, RX VrefLevel [Byte0]: 27
7890 23:06:04.288722 [Byte1]: 27
7891 23:06:04.292966
7892 23:06:04.293457 Set Vref, RX VrefLevel [Byte0]: 28
7893 23:06:04.296265 [Byte1]: 28
7894 23:06:04.300948
7895 23:06:04.301539 Set Vref, RX VrefLevel [Byte0]: 29
7896 23:06:04.304042 [Byte1]: 29
7897 23:06:04.308125
7898 23:06:04.308598 Set Vref, RX VrefLevel [Byte0]: 30
7899 23:06:04.311767 [Byte1]: 30
7900 23:06:04.316106
7901 23:06:04.316638 Set Vref, RX VrefLevel [Byte0]: 31
7902 23:06:04.319102 [Byte1]: 31
7903 23:06:04.323887
7904 23:06:04.324482 Set Vref, RX VrefLevel [Byte0]: 32
7905 23:06:04.326711 [Byte1]: 32
7906 23:06:04.331166
7907 23:06:04.331700 Set Vref, RX VrefLevel [Byte0]: 33
7908 23:06:04.334435 [Byte1]: 33
7909 23:06:04.338530
7910 23:06:04.339007 Set Vref, RX VrefLevel [Byte0]: 34
7911 23:06:04.342319 [Byte1]: 34
7912 23:06:04.346835
7913 23:06:04.347294 Set Vref, RX VrefLevel [Byte0]: 35
7914 23:06:04.349657 [Byte1]: 35
7915 23:06:04.354128
7916 23:06:04.354549 Set Vref, RX VrefLevel [Byte0]: 36
7917 23:06:04.357271 [Byte1]: 36
7918 23:06:04.361584
7919 23:06:04.362082 Set Vref, RX VrefLevel [Byte0]: 37
7920 23:06:04.364777 [Byte1]: 37
7921 23:06:04.369020
7922 23:06:04.369686 Set Vref, RX VrefLevel [Byte0]: 38
7923 23:06:04.372743 [Byte1]: 38
7924 23:06:04.376379
7925 23:06:04.376988 Set Vref, RX VrefLevel [Byte0]: 39
7926 23:06:04.380362 [Byte1]: 39
7927 23:06:04.384835
7928 23:06:04.385287 Set Vref, RX VrefLevel [Byte0]: 40
7929 23:06:04.387847 [Byte1]: 40
7930 23:06:04.392262
7931 23:06:04.392762 Set Vref, RX VrefLevel [Byte0]: 41
7932 23:06:04.395089 [Byte1]: 41
7933 23:06:04.399726
7934 23:06:04.400235 Set Vref, RX VrefLevel [Byte0]: 42
7935 23:06:04.402703 [Byte1]: 42
7936 23:06:04.406997
7937 23:06:04.407435 Set Vref, RX VrefLevel [Byte0]: 43
7938 23:06:04.410543 [Byte1]: 43
7939 23:06:04.414765
7940 23:06:04.415181 Set Vref, RX VrefLevel [Byte0]: 44
7941 23:06:04.418307 [Byte1]: 44
7942 23:06:04.422450
7943 23:06:04.422967 Set Vref, RX VrefLevel [Byte0]: 45
7944 23:06:04.425894 [Byte1]: 45
7945 23:06:04.430029
7946 23:06:04.430555 Set Vref, RX VrefLevel [Byte0]: 46
7947 23:06:04.433739 [Byte1]: 46
7948 23:06:04.437836
7949 23:06:04.438360 Set Vref, RX VrefLevel [Byte0]: 47
7950 23:06:04.440859 [Byte1]: 47
7951 23:06:04.444748
7952 23:06:04.444856 Set Vref, RX VrefLevel [Byte0]: 48
7953 23:06:04.448175 [Byte1]: 48
7954 23:06:04.452430
7955 23:06:04.452512 Set Vref, RX VrefLevel [Byte0]: 49
7956 23:06:04.456334 [Byte1]: 49
7957 23:06:04.460045
7958 23:06:04.460128 Set Vref, RX VrefLevel [Byte0]: 50
7959 23:06:04.463682 [Byte1]: 50
7960 23:06:04.467861
7961 23:06:04.467947 Set Vref, RX VrefLevel [Byte0]: 51
7962 23:06:04.471071 [Byte1]: 51
7963 23:06:04.475334
7964 23:06:04.475418 Set Vref, RX VrefLevel [Byte0]: 52
7965 23:06:04.478501 [Byte1]: 52
7966 23:06:04.483182
7967 23:06:04.483263 Set Vref, RX VrefLevel [Byte0]: 53
7968 23:06:04.486204 [Byte1]: 53
7969 23:06:04.490634
7970 23:06:04.490715 Set Vref, RX VrefLevel [Byte0]: 54
7971 23:06:04.493742 [Byte1]: 54
7972 23:06:04.498391
7973 23:06:04.498473 Set Vref, RX VrefLevel [Byte0]: 55
7974 23:06:04.501634 [Byte1]: 55
7975 23:06:04.505693
7976 23:06:04.505775 Set Vref, RX VrefLevel [Byte0]: 56
7977 23:06:04.509247 [Byte1]: 56
7978 23:06:04.513351
7979 23:06:04.513469 Set Vref, RX VrefLevel [Byte0]: 57
7980 23:06:04.517153 [Byte1]: 57
7981 23:06:04.520862
7982 23:06:04.520944 Set Vref, RX VrefLevel [Byte0]: 58
7983 23:06:04.524223 [Byte1]: 58
7984 23:06:04.528594
7985 23:06:04.528675 Set Vref, RX VrefLevel [Byte0]: 59
7986 23:06:04.532065 [Byte1]: 59
7987 23:06:04.536388
7988 23:06:04.536475 Set Vref, RX VrefLevel [Byte0]: 60
7989 23:06:04.539407 [Byte1]: 60
7990 23:06:04.543767
7991 23:06:04.543870 Set Vref, RX VrefLevel [Byte0]: 61
7992 23:06:04.547693 [Byte1]: 61
7993 23:06:04.552670
7994 23:06:04.552794 Set Vref, RX VrefLevel [Byte0]: 62
7995 23:06:04.554801 [Byte1]: 62
7996 23:06:04.559510
7997 23:06:04.559592 Set Vref, RX VrefLevel [Byte0]: 63
7998 23:06:04.562560 [Byte1]: 63
7999 23:06:04.566946
8000 23:06:04.567028 Set Vref, RX VrefLevel [Byte0]: 64
8001 23:06:04.570284 [Byte1]: 64
8002 23:06:04.574438
8003 23:06:04.574520 Set Vref, RX VrefLevel [Byte0]: 65
8004 23:06:04.577544 [Byte1]: 65
8005 23:06:04.581917
8006 23:06:04.581999 Set Vref, RX VrefLevel [Byte0]: 66
8007 23:06:04.585249 [Byte1]: 66
8008 23:06:04.589374
8009 23:06:04.589493 Set Vref, RX VrefLevel [Byte0]: 67
8010 23:06:04.592927 [Byte1]: 67
8011 23:06:04.596931
8012 23:06:04.597012 Set Vref, RX VrefLevel [Byte0]: 68
8013 23:06:04.600248 [Byte1]: 68
8014 23:06:04.604732
8015 23:06:04.604814 Set Vref, RX VrefLevel [Byte0]: 69
8016 23:06:04.607771 [Byte1]: 69
8017 23:06:04.612996
8018 23:06:04.613083 Set Vref, RX VrefLevel [Byte0]: 70
8019 23:06:04.615838 [Byte1]: 70
8020 23:06:04.619944
8021 23:06:04.620038 Set Vref, RX VrefLevel [Byte0]: 71
8022 23:06:04.623603 [Byte1]: 71
8023 23:06:04.627951
8024 23:06:04.628072 Set Vref, RX VrefLevel [Byte0]: 72
8025 23:06:04.631018 [Byte1]: 72
8026 23:06:04.636012
8027 23:06:04.636135 Set Vref, RX VrefLevel [Byte0]: 73
8028 23:06:04.639087 [Byte1]: 73
8029 23:06:04.642869
8030 23:06:04.643020 Set Vref, RX VrefLevel [Byte0]: 74
8031 23:06:04.646259 [Byte1]: 74
8032 23:06:04.650571
8033 23:06:04.650743 Set Vref, RX VrefLevel [Byte0]: 75
8034 23:06:04.654079 [Byte1]: 75
8035 23:06:04.658104
8036 23:06:04.658344 Set Vref, RX VrefLevel [Byte0]: 76
8037 23:06:04.661202 [Byte1]: 76
8038 23:06:04.665822
8039 23:06:04.666119 Set Vref, RX VrefLevel [Byte0]: 77
8040 23:06:04.669096 [Byte1]: 77
8041 23:06:04.674021
8042 23:06:04.674447 Set Vref, RX VrefLevel [Byte0]: 78
8043 23:06:04.676993 [Byte1]: 78
8044 23:06:04.681181
8045 23:06:04.681759 Final RX Vref Byte 0 = 66 to rank0
8046 23:06:04.684511 Final RX Vref Byte 1 = 55 to rank0
8047 23:06:04.688398 Final RX Vref Byte 0 = 66 to rank1
8048 23:06:04.691412 Final RX Vref Byte 1 = 55 to rank1==
8049 23:06:04.694248 Dram Type= 6, Freq= 0, CH_0, rank 0
8050 23:06:04.701071 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8051 23:06:04.701607 ==
8052 23:06:04.701968 DQS Delay:
8053 23:06:04.702415 DQS0 = 0, DQS1 = 0
8054 23:06:04.704437 DQM Delay:
8055 23:06:04.704921 DQM0 = 133, DQM1 = 122
8056 23:06:04.708211 DQ Delay:
8057 23:06:04.711014 DQ0 =130, DQ1 =136, DQ2 =132, DQ3 =132
8058 23:06:04.714552 DQ4 =134, DQ5 =122, DQ6 =140, DQ7 =142
8059 23:06:04.717865 DQ8 =114, DQ9 =110, DQ10 =122, DQ11 =116
8060 23:06:04.721025 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =130
8061 23:06:04.721486
8062 23:06:04.721834
8063 23:06:04.722151
8064 23:06:04.724272 [DramC_TX_OE_Calibration] TA2
8065 23:06:04.727656 Original DQ_B0 (3 6) =30, OEN = 27
8066 23:06:04.730832 Original DQ_B1 (3 6) =30, OEN = 27
8067 23:06:04.734325 24, 0x0, End_B0=24 End_B1=24
8068 23:06:04.734773 25, 0x0, End_B0=25 End_B1=25
8069 23:06:04.737942 26, 0x0, End_B0=26 End_B1=26
8070 23:06:04.741098 27, 0x0, End_B0=27 End_B1=27
8071 23:06:04.744185 28, 0x0, End_B0=28 End_B1=28
8072 23:06:04.747632 29, 0x0, End_B0=29 End_B1=29
8073 23:06:04.748080 30, 0x0, End_B0=30 End_B1=30
8074 23:06:04.750586 31, 0x4141, End_B0=30 End_B1=30
8075 23:06:04.754064 Byte0 end_step=30 best_step=27
8076 23:06:04.757118 Byte1 end_step=30 best_step=27
8077 23:06:04.760847 Byte0 TX OE(2T, 0.5T) = (3, 3)
8078 23:06:04.764229 Byte1 TX OE(2T, 0.5T) = (3, 3)
8079 23:06:04.764668
8080 23:06:04.765112
8081 23:06:04.770547 [DQSOSCAuto] RK0, (LSB)MR18= 0x2415, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 391 ps
8082 23:06:04.774419 CH0 RK0: MR19=303, MR18=2415
8083 23:06:04.780446 CH0_RK0: MR19=0x303, MR18=0x2415, DQSOSC=391, MR23=63, INC=24, DEC=16
8084 23:06:04.780873
8085 23:06:04.783699 ----->DramcWriteLeveling(PI) begin...
8086 23:06:04.784127 ==
8087 23:06:04.786891 Dram Type= 6, Freq= 0, CH_0, rank 1
8088 23:06:04.790339 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8089 23:06:04.790763 ==
8090 23:06:04.793363 Write leveling (Byte 0): 35 => 35
8091 23:06:04.797043 Write leveling (Byte 1): 29 => 29
8092 23:06:04.800320 DramcWriteLeveling(PI) end<-----
8093 23:06:04.800844
8094 23:06:04.801185 ==
8095 23:06:04.803761 Dram Type= 6, Freq= 0, CH_0, rank 1
8096 23:06:04.806718 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8097 23:06:04.809954 ==
8098 23:06:04.810379 [Gating] SW mode calibration
8099 23:06:04.820099 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8100 23:06:04.823147 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8101 23:06:04.826496 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8102 23:06:04.833233 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8103 23:06:04.836585 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8104 23:06:04.840347 1 4 12 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
8105 23:06:04.846703 1 4 16 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 0)
8106 23:06:04.849815 1 4 20 | B1->B0 | 2c2c 3434 | 0 1 | (1 1) (1 1)
8107 23:06:04.852852 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8108 23:06:04.859332 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8109 23:06:04.862481 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8110 23:06:04.865599 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8111 23:06:04.872415 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8112 23:06:04.875623 1 5 12 | B1->B0 | 3434 3232 | 1 0 | (1 1) (1 0)
8113 23:06:04.879118 1 5 16 | B1->B0 | 3434 2525 | 1 0 | (1 0) (1 0)
8114 23:06:04.885741 1 5 20 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
8115 23:06:04.889113 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8116 23:06:04.892453 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8117 23:06:04.898990 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8118 23:06:04.902545 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8119 23:06:04.905601 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8120 23:06:04.913254 1 6 12 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
8121 23:06:04.916069 1 6 16 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
8122 23:06:04.919469 1 6 20 | B1->B0 | 4141 4646 | 1 0 | (1 1) (0 0)
8123 23:06:04.926280 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8124 23:06:04.929170 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8125 23:06:04.933643 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8126 23:06:04.939501 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8127 23:06:04.942603 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8128 23:06:04.945874 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8129 23:06:04.953614 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8130 23:06:04.956067 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8131 23:06:04.958674 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8132 23:06:04.965502 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8133 23:06:04.968814 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8134 23:06:04.971960 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8135 23:06:04.978207 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8136 23:06:04.981301 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8137 23:06:04.984865 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8138 23:06:04.991135 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8139 23:06:04.994904 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8140 23:06:04.998305 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8141 23:06:05.004984 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8142 23:06:05.007746 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8143 23:06:05.011408 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8144 23:06:05.017714 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8145 23:06:05.020657 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8146 23:06:05.024573 Total UI for P1: 0, mck2ui 16
8147 23:06:05.027521 best dqsien dly found for B0: ( 1, 9, 10)
8148 23:06:05.030604 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8149 23:06:05.037123 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8150 23:06:05.037209 Total UI for P1: 0, mck2ui 16
8151 23:06:05.043778 best dqsien dly found for B1: ( 1, 9, 20)
8152 23:06:05.047197 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8153 23:06:05.050398 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8154 23:06:05.050484
8155 23:06:05.053773 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8156 23:06:05.057130 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8157 23:06:05.060211 [Gating] SW calibration Done
8158 23:06:05.060312 ==
8159 23:06:05.064013 Dram Type= 6, Freq= 0, CH_0, rank 1
8160 23:06:05.066830 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8161 23:06:05.066948 ==
8162 23:06:05.069952 RX Vref Scan: 0
8163 23:06:05.070069
8164 23:06:05.073528 RX Vref 0 -> 0, step: 1
8165 23:06:05.073656
8166 23:06:05.073810 RX Delay 0 -> 252, step: 8
8167 23:06:05.080197 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8168 23:06:05.083637 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8169 23:06:05.086773 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8170 23:06:05.090446 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8171 23:06:05.093748 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8172 23:06:05.099981 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8173 23:06:05.103877 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8174 23:06:05.106686 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8175 23:06:05.109974 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8176 23:06:05.113806 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8177 23:06:05.120630 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8178 23:06:05.123871 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8179 23:06:05.126850 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8180 23:06:05.130374 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8181 23:06:05.133532 iDelay=200, Bit 14, Center 143 (88 ~ 199) 112
8182 23:06:05.139963 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8183 23:06:05.140534 ==
8184 23:06:05.143490 Dram Type= 6, Freq= 0, CH_0, rank 1
8185 23:06:05.146563 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8186 23:06:05.147036 ==
8187 23:06:05.147412 DQS Delay:
8188 23:06:05.149882 DQS0 = 0, DQS1 = 0
8189 23:06:05.150349 DQM Delay:
8190 23:06:05.153728 DQM0 = 133, DQM1 = 129
8191 23:06:05.154198 DQ Delay:
8192 23:06:05.156303 DQ0 =135, DQ1 =135, DQ2 =127, DQ3 =127
8193 23:06:05.160484 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8194 23:06:05.163635 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8195 23:06:05.166903 DQ12 =135, DQ13 =135, DQ14 =143, DQ15 =135
8196 23:06:05.169864
8197 23:06:05.170425
8198 23:06:05.170802 ==
8199 23:06:05.173348 Dram Type= 6, Freq= 0, CH_0, rank 1
8200 23:06:05.176391 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8201 23:06:05.176995 ==
8202 23:06:05.177597
8203 23:06:05.177973
8204 23:06:05.179543 TX Vref Scan disable
8205 23:06:05.180009 == TX Byte 0 ==
8206 23:06:05.186329 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8207 23:06:05.189398 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8208 23:06:05.189918 == TX Byte 1 ==
8209 23:06:05.196072 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8210 23:06:05.199710 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8211 23:06:05.200135 ==
8212 23:06:05.202530 Dram Type= 6, Freq= 0, CH_0, rank 1
8213 23:06:05.205972 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8214 23:06:05.206398 ==
8215 23:06:05.220135
8216 23:06:05.223355 TX Vref early break, caculate TX vref
8217 23:06:05.226788 TX Vref=16, minBit 0, minWin=22, winSum=377
8218 23:06:05.230187 TX Vref=18, minBit 0, minWin=22, winSum=390
8219 23:06:05.233236 TX Vref=20, minBit 1, minWin=22, winSum=392
8220 23:06:05.236656 TX Vref=22, minBit 1, minWin=24, winSum=406
8221 23:06:05.239841 TX Vref=24, minBit 1, minWin=24, winSum=414
8222 23:06:05.246332 TX Vref=26, minBit 3, minWin=24, winSum=415
8223 23:06:05.249607 TX Vref=28, minBit 1, minWin=24, winSum=416
8224 23:06:05.253240 TX Vref=30, minBit 1, minWin=24, winSum=406
8225 23:06:05.256337 TX Vref=32, minBit 0, minWin=23, winSum=398
8226 23:06:05.260001 TX Vref=34, minBit 0, minWin=23, winSum=391
8227 23:06:05.266222 [TxChooseVref] Worse bit 1, Min win 24, Win sum 416, Final Vref 28
8228 23:06:05.266714
8229 23:06:05.269633 Final TX Range 0 Vref 28
8230 23:06:05.270160
8231 23:06:05.270744 ==
8232 23:06:05.272923 Dram Type= 6, Freq= 0, CH_0, rank 1
8233 23:06:05.276122 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8234 23:06:05.276688 ==
8235 23:06:05.277177
8236 23:06:05.277659
8237 23:06:05.279813 TX Vref Scan disable
8238 23:06:05.286024 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8239 23:06:05.286514 == TX Byte 0 ==
8240 23:06:05.290260 u2DelayCellOfst[0]=14 cells (4 PI)
8241 23:06:05.292718 u2DelayCellOfst[1]=22 cells (6 PI)
8242 23:06:05.296172 u2DelayCellOfst[2]=14 cells (4 PI)
8243 23:06:05.299800 u2DelayCellOfst[3]=18 cells (5 PI)
8244 23:06:05.302613 u2DelayCellOfst[4]=11 cells (3 PI)
8245 23:06:05.305628 u2DelayCellOfst[5]=0 cells (0 PI)
8246 23:06:05.308992 u2DelayCellOfst[6]=22 cells (6 PI)
8247 23:06:05.312398 u2DelayCellOfst[7]=22 cells (6 PI)
8248 23:06:05.315703 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8249 23:06:05.319331 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8250 23:06:05.322756 == TX Byte 1 ==
8251 23:06:05.326466 u2DelayCellOfst[8]=0 cells (0 PI)
8252 23:06:05.328833 u2DelayCellOfst[9]=3 cells (1 PI)
8253 23:06:05.332334 u2DelayCellOfst[10]=7 cells (2 PI)
8254 23:06:05.332775 u2DelayCellOfst[11]=3 cells (1 PI)
8255 23:06:05.335630 u2DelayCellOfst[12]=14 cells (4 PI)
8256 23:06:05.338723 u2DelayCellOfst[13]=14 cells (4 PI)
8257 23:06:05.341687 u2DelayCellOfst[14]=18 cells (5 PI)
8258 23:06:05.344805 u2DelayCellOfst[15]=11 cells (3 PI)
8259 23:06:05.351420 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8260 23:06:05.355075 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8261 23:06:05.358532 DramC Write-DBI on
8262 23:06:05.358723 ==
8263 23:06:05.361296 Dram Type= 6, Freq= 0, CH_0, rank 1
8264 23:06:05.364738 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8265 23:06:05.364928 ==
8266 23:06:05.365132
8267 23:06:05.365314
8268 23:06:05.367956 TX Vref Scan disable
8269 23:06:05.368163 == TX Byte 0 ==
8270 23:06:05.374624 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8271 23:06:05.374814 == TX Byte 1 ==
8272 23:06:05.377562 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8273 23:06:05.381169 DramC Write-DBI off
8274 23:06:05.381359
8275 23:06:05.381564 [DATLAT]
8276 23:06:05.384473 Freq=1600, CH0 RK1
8277 23:06:05.384670
8278 23:06:05.384863 DATLAT Default: 0xf
8279 23:06:05.387330 0, 0xFFFF, sum = 0
8280 23:06:05.391317 1, 0xFFFF, sum = 0
8281 23:06:05.391518 2, 0xFFFF, sum = 0
8282 23:06:05.394251 3, 0xFFFF, sum = 0
8283 23:06:05.394447 4, 0xFFFF, sum = 0
8284 23:06:05.397619 5, 0xFFFF, sum = 0
8285 23:06:05.397812 6, 0xFFFF, sum = 0
8286 23:06:05.400688 7, 0xFFFF, sum = 0
8287 23:06:05.400884 8, 0xFFFF, sum = 0
8288 23:06:05.404124 9, 0xFFFF, sum = 0
8289 23:06:05.404311 10, 0xFFFF, sum = 0
8290 23:06:05.407188 11, 0xFFFF, sum = 0
8291 23:06:05.407386 12, 0xFFFF, sum = 0
8292 23:06:05.411108 13, 0xFFFF, sum = 0
8293 23:06:05.411297 14, 0x0, sum = 1
8294 23:06:05.413619 15, 0x0, sum = 2
8295 23:06:05.413838 16, 0x0, sum = 3
8296 23:06:05.417487 17, 0x0, sum = 4
8297 23:06:05.417784 best_step = 15
8298 23:06:05.418020
8299 23:06:05.418243 ==
8300 23:06:05.420500 Dram Type= 6, Freq= 0, CH_0, rank 1
8301 23:06:05.427145 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8302 23:06:05.427513 ==
8303 23:06:05.427808 RX Vref Scan: 0
8304 23:06:05.428115
8305 23:06:05.430585 RX Vref 0 -> 0, step: 1
8306 23:06:05.430911
8307 23:06:05.434062 RX Delay 11 -> 252, step: 4
8308 23:06:05.437205 iDelay=195, Bit 0, Center 128 (79 ~ 178) 100
8309 23:06:05.440307 iDelay=195, Bit 1, Center 134 (79 ~ 190) 112
8310 23:06:05.446742 iDelay=195, Bit 2, Center 124 (71 ~ 178) 108
8311 23:06:05.449991 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8312 23:06:05.453296 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
8313 23:06:05.456660 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8314 23:06:05.460004 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8315 23:06:05.466779 iDelay=195, Bit 7, Center 140 (87 ~ 194) 108
8316 23:06:05.470282 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8317 23:06:05.473185 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8318 23:06:05.476284 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8319 23:06:05.479565 iDelay=195, Bit 11, Center 118 (67 ~ 170) 104
8320 23:06:05.486379 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8321 23:06:05.489497 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8322 23:06:05.492765 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8323 23:06:05.496490 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8324 23:06:05.496826 ==
8325 23:06:05.499551 Dram Type= 6, Freq= 0, CH_0, rank 1
8326 23:06:05.506081 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8327 23:06:05.506558 ==
8328 23:06:05.507034 DQS Delay:
8329 23:06:05.509286 DQS0 = 0, DQS1 = 0
8330 23:06:05.509725 DQM Delay:
8331 23:06:05.513209 DQM0 = 130, DQM1 = 125
8332 23:06:05.513573 DQ Delay:
8333 23:06:05.516116 DQ0 =128, DQ1 =134, DQ2 =124, DQ3 =128
8334 23:06:05.519161 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =140
8335 23:06:05.522556 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =118
8336 23:06:05.525767 DQ12 =132, DQ13 =132, DQ14 =136, DQ15 =132
8337 23:06:05.526092
8338 23:06:05.526354
8339 23:06:05.526592
8340 23:06:05.529258 [DramC_TX_OE_Calibration] TA2
8341 23:06:05.532188 Original DQ_B0 (3 6) =30, OEN = 27
8342 23:06:05.535540 Original DQ_B1 (3 6) =30, OEN = 27
8343 23:06:05.539083 24, 0x0, End_B0=24 End_B1=24
8344 23:06:05.542081 25, 0x0, End_B0=25 End_B1=25
8345 23:06:05.542276 26, 0x0, End_B0=26 End_B1=26
8346 23:06:05.546215 27, 0x0, End_B0=27 End_B1=27
8347 23:06:05.549246 28, 0x0, End_B0=28 End_B1=28
8348 23:06:05.552379 29, 0x0, End_B0=29 End_B1=29
8349 23:06:05.555379 30, 0x0, End_B0=30 End_B1=30
8350 23:06:05.555573 31, 0x4545, End_B0=30 End_B1=30
8351 23:06:05.559115 Byte0 end_step=30 best_step=27
8352 23:06:05.562080 Byte1 end_step=30 best_step=27
8353 23:06:05.565017 Byte0 TX OE(2T, 0.5T) = (3, 3)
8354 23:06:05.568419 Byte1 TX OE(2T, 0.5T) = (3, 3)
8355 23:06:05.568611
8356 23:06:05.568765
8357 23:06:05.575422 [DQSOSCAuto] RK1, (LSB)MR18= 0x2205, (MSB)MR19= 0x303, tDQSOscB0 = 407 ps tDQSOscB1 = 392 ps
8358 23:06:05.578570 CH0 RK1: MR19=303, MR18=2205
8359 23:06:05.585145 CH0_RK1: MR19=0x303, MR18=0x2205, DQSOSC=392, MR23=63, INC=24, DEC=16
8360 23:06:05.588444 [RxdqsGatingPostProcess] freq 1600
8361 23:06:05.595037 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8362 23:06:05.599082 best DQS0 dly(2T, 0.5T) = (1, 1)
8363 23:06:05.599504 best DQS1 dly(2T, 0.5T) = (1, 1)
8364 23:06:05.602174 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8365 23:06:05.605125 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8366 23:06:05.608526 best DQS0 dly(2T, 0.5T) = (1, 1)
8367 23:06:05.611900 best DQS1 dly(2T, 0.5T) = (1, 1)
8368 23:06:05.614920 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8369 23:06:05.618284 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8370 23:06:05.621667 Pre-setting of DQS Precalculation
8371 23:06:05.625078 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8372 23:06:05.628338 ==
8373 23:06:05.628767 Dram Type= 6, Freq= 0, CH_1, rank 0
8374 23:06:05.634758 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8375 23:06:05.635178 ==
8376 23:06:05.638136 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8377 23:06:05.644848 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8378 23:06:05.647887 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8379 23:06:05.654386 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8380 23:06:05.662616 [CA 0] Center 42 (13~71) winsize 59
8381 23:06:05.666080 [CA 1] Center 41 (12~71) winsize 60
8382 23:06:05.669396 [CA 2] Center 37 (8~66) winsize 59
8383 23:06:05.673062 [CA 3] Center 36 (7~66) winsize 60
8384 23:06:05.676114 [CA 4] Center 37 (7~67) winsize 61
8385 23:06:05.679409 [CA 5] Center 36 (7~65) winsize 59
8386 23:06:05.679830
8387 23:06:05.682733 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8388 23:06:05.683244
8389 23:06:05.688873 [CATrainingPosCal] consider 1 rank data
8390 23:06:05.689294 u2DelayCellTimex100 = 262/100 ps
8391 23:06:05.695784 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8392 23:06:05.698943 CA1 delay=41 (12~71),Diff = 5 PI (18 cell)
8393 23:06:05.702081 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8394 23:06:05.705573 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8395 23:06:05.708836 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
8396 23:06:05.712057 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
8397 23:06:05.712482
8398 23:06:05.715157 CA PerBit enable=1, Macro0, CA PI delay=36
8399 23:06:05.715574
8400 23:06:05.718809 [CBTSetCACLKResult] CA Dly = 36
8401 23:06:05.722337 CS Dly: 8 (0~39)
8402 23:06:05.725260 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8403 23:06:05.728998 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8404 23:06:05.729457 ==
8405 23:06:05.731984 Dram Type= 6, Freq= 0, CH_1, rank 1
8406 23:06:05.738301 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8407 23:06:05.738742 ==
8408 23:06:05.741728 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8409 23:06:05.748093 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8410 23:06:05.751874 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8411 23:06:05.758129 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8412 23:06:05.766482 [CA 0] Center 42 (13~71) winsize 59
8413 23:06:05.769513 [CA 1] Center 42 (13~72) winsize 60
8414 23:06:05.772362 [CA 2] Center 37 (8~67) winsize 60
8415 23:06:05.776112 [CA 3] Center 37 (7~67) winsize 61
8416 23:06:05.779480 [CA 4] Center 37 (8~67) winsize 60
8417 23:06:05.782450 [CA 5] Center 37 (8~66) winsize 59
8418 23:06:05.782893
8419 23:06:05.785564 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8420 23:06:05.786005
8421 23:06:05.791988 [CATrainingPosCal] consider 2 rank data
8422 23:06:05.792431 u2DelayCellTimex100 = 262/100 ps
8423 23:06:05.798617 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8424 23:06:05.802105 CA1 delay=42 (13~71),Diff = 6 PI (22 cell)
8425 23:06:05.805552 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8426 23:06:05.808483 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8427 23:06:05.812283 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8428 23:06:05.815024 CA5 delay=36 (8~65),Diff = 0 PI (0 cell)
8429 23:06:05.815465
8430 23:06:05.818458 CA PerBit enable=1, Macro0, CA PI delay=36
8431 23:06:05.818898
8432 23:06:05.822044 [CBTSetCACLKResult] CA Dly = 36
8433 23:06:05.825451 CS Dly: 10 (0~43)
8434 23:06:05.828345 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8435 23:06:05.831951 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8436 23:06:05.832391
8437 23:06:05.834787 ----->DramcWriteLeveling(PI) begin...
8438 23:06:05.835232 ==
8439 23:06:05.838560 Dram Type= 6, Freq= 0, CH_1, rank 0
8440 23:06:05.845242 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8441 23:06:05.845716 ==
8442 23:06:05.848052 Write leveling (Byte 0): 23 => 23
8443 23:06:05.851731 Write leveling (Byte 1): 27 => 27
8444 23:06:05.854684 DramcWriteLeveling(PI) end<-----
8445 23:06:05.855125
8446 23:06:05.855573 ==
8447 23:06:05.857926 Dram Type= 6, Freq= 0, CH_1, rank 0
8448 23:06:05.861571 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8449 23:06:05.862015 ==
8450 23:06:05.864757 [Gating] SW mode calibration
8451 23:06:05.871538 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8452 23:06:05.877761 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8453 23:06:05.881246 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8454 23:06:05.884653 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8455 23:06:05.890960 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8456 23:06:05.894417 1 4 12 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
8457 23:06:05.897472 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8458 23:06:05.904171 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8459 23:06:05.908069 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8460 23:06:05.911238 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8461 23:06:05.914633 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8462 23:06:05.920788 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8463 23:06:05.924216 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8464 23:06:05.927720 1 5 12 | B1->B0 | 3232 2626 | 0 1 | (0 1) (1 0)
8465 23:06:05.934073 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8466 23:06:05.937146 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8467 23:06:05.943982 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8468 23:06:05.947390 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8469 23:06:05.950606 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8470 23:06:05.956864 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8471 23:06:05.960362 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8472 23:06:05.963584 1 6 12 | B1->B0 | 3939 4444 | 0 1 | (0 0) (0 0)
8473 23:06:05.967064 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8474 23:06:05.973819 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8475 23:06:05.976728 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8476 23:06:05.979978 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8477 23:06:05.986683 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8478 23:06:05.990116 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8479 23:06:05.996702 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8480 23:06:05.999886 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8481 23:06:06.002900 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8482 23:06:06.009667 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8483 23:06:06.013006 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8484 23:06:06.016319 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8485 23:06:06.022917 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8486 23:06:06.026417 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8487 23:06:06.029714 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8488 23:06:06.035879 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8489 23:06:06.039265 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8490 23:06:06.042841 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8491 23:06:06.049198 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8492 23:06:06.052540 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8493 23:06:06.055726 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8494 23:06:06.062680 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8495 23:06:06.065493 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8496 23:06:06.069255 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8497 23:06:06.076021 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8498 23:06:06.076446 Total UI for P1: 0, mck2ui 16
8499 23:06:06.079149 best dqsien dly found for B0: ( 1, 9, 10)
8500 23:06:06.082223 Total UI for P1: 0, mck2ui 16
8501 23:06:06.085702 best dqsien dly found for B1: ( 1, 9, 12)
8502 23:06:06.091822 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8503 23:06:06.095310 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8504 23:06:06.095734
8505 23:06:06.099538 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8506 23:06:06.101887 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8507 23:06:06.105478 [Gating] SW calibration Done
8508 23:06:06.105907 ==
8509 23:06:06.108391 Dram Type= 6, Freq= 0, CH_1, rank 0
8510 23:06:06.111731 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8511 23:06:06.112159 ==
8512 23:06:06.114980 RX Vref Scan: 0
8513 23:06:06.115402
8514 23:06:06.115860 RX Vref 0 -> 0, step: 1
8515 23:06:06.116188
8516 23:06:06.118538 RX Delay 0 -> 252, step: 8
8517 23:06:06.121676 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8518 23:06:06.128321 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8519 23:06:06.131784 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8520 23:06:06.134848 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8521 23:06:06.138138 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8522 23:06:06.141520 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8523 23:06:06.148691 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8524 23:06:06.151593 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8525 23:06:06.154720 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8526 23:06:06.158007 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8527 23:06:06.161294 iDelay=208, Bit 10, Center 127 (72 ~ 183) 112
8528 23:06:06.168031 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8529 23:06:06.171070 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8530 23:06:06.174568 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8531 23:06:06.177801 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8532 23:06:06.184191 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8533 23:06:06.184625 ==
8534 23:06:06.187860 Dram Type= 6, Freq= 0, CH_1, rank 0
8535 23:06:06.190928 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8536 23:06:06.191397 ==
8537 23:06:06.191741 DQS Delay:
8538 23:06:06.194386 DQS0 = 0, DQS1 = 0
8539 23:06:06.194808 DQM Delay:
8540 23:06:06.197923 DQM0 = 137, DQM1 = 128
8541 23:06:06.198345 DQ Delay:
8542 23:06:06.201161 DQ0 =139, DQ1 =131, DQ2 =127, DQ3 =135
8543 23:06:06.204326 DQ4 =135, DQ5 =151, DQ6 =143, DQ7 =135
8544 23:06:06.207364 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =123
8545 23:06:06.210431 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =135
8546 23:06:06.210867
8547 23:06:06.213817
8548 23:06:06.214239 ==
8549 23:06:06.217372 Dram Type= 6, Freq= 0, CH_1, rank 0
8550 23:06:06.220776 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8551 23:06:06.221197 ==
8552 23:06:06.221736
8553 23:06:06.222125
8554 23:06:06.224065 TX Vref Scan disable
8555 23:06:06.224486 == TX Byte 0 ==
8556 23:06:06.230853 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8557 23:06:06.233680 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8558 23:06:06.234107 == TX Byte 1 ==
8559 23:06:06.240239 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8560 23:06:06.243581 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8561 23:06:06.244006 ==
8562 23:06:06.247499 Dram Type= 6, Freq= 0, CH_1, rank 0
8563 23:06:06.250507 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8564 23:06:06.250932 ==
8565 23:06:06.264178
8566 23:06:06.267210 TX Vref early break, caculate TX vref
8567 23:06:06.270548 TX Vref=16, minBit 5, minWin=21, winSum=372
8568 23:06:06.273837 TX Vref=18, minBit 10, minWin=22, winSum=383
8569 23:06:06.277100 TX Vref=20, minBit 0, minWin=23, winSum=390
8570 23:06:06.280329 TX Vref=22, minBit 0, minWin=23, winSum=399
8571 23:06:06.283552 TX Vref=24, minBit 5, minWin=24, winSum=409
8572 23:06:06.290286 TX Vref=26, minBit 0, minWin=25, winSum=417
8573 23:06:06.293560 TX Vref=28, minBit 0, minWin=24, winSum=414
8574 23:06:06.297149 TX Vref=30, minBit 0, minWin=24, winSum=409
8575 23:06:06.299879 TX Vref=32, minBit 1, minWin=24, winSum=403
8576 23:06:06.303196 TX Vref=34, minBit 0, minWin=23, winSum=394
8577 23:06:06.309723 [TxChooseVref] Worse bit 0, Min win 25, Win sum 417, Final Vref 26
8578 23:06:06.310242
8579 23:06:06.313383 Final TX Range 0 Vref 26
8580 23:06:06.313843
8581 23:06:06.314180 ==
8582 23:06:06.316536 Dram Type= 6, Freq= 0, CH_1, rank 0
8583 23:06:06.319781 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8584 23:06:06.320208 ==
8585 23:06:06.320549
8586 23:06:06.322928
8587 23:06:06.323347 TX Vref Scan disable
8588 23:06:06.330093 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8589 23:06:06.330528 == TX Byte 0 ==
8590 23:06:06.333324 u2DelayCellOfst[0]=14 cells (4 PI)
8591 23:06:06.336314 u2DelayCellOfst[1]=11 cells (3 PI)
8592 23:06:06.339915 u2DelayCellOfst[2]=0 cells (0 PI)
8593 23:06:06.343172 u2DelayCellOfst[3]=3 cells (1 PI)
8594 23:06:06.346402 u2DelayCellOfst[4]=7 cells (2 PI)
8595 23:06:06.349448 u2DelayCellOfst[5]=18 cells (5 PI)
8596 23:06:06.353263 u2DelayCellOfst[6]=18 cells (5 PI)
8597 23:06:06.355901 u2DelayCellOfst[7]=3 cells (1 PI)
8598 23:06:06.359422 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8599 23:06:06.362731 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8600 23:06:06.366283 == TX Byte 1 ==
8601 23:06:06.369260 u2DelayCellOfst[8]=0 cells (0 PI)
8602 23:06:06.372807 u2DelayCellOfst[9]=3 cells (1 PI)
8603 23:06:06.373231 u2DelayCellOfst[10]=11 cells (3 PI)
8604 23:06:06.376028 u2DelayCellOfst[11]=3 cells (1 PI)
8605 23:06:06.379171 u2DelayCellOfst[12]=14 cells (4 PI)
8606 23:06:06.382692 u2DelayCellOfst[13]=14 cells (4 PI)
8607 23:06:06.385777 u2DelayCellOfst[14]=18 cells (5 PI)
8608 23:06:06.388967 u2DelayCellOfst[15]=18 cells (5 PI)
8609 23:06:06.395853 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8610 23:06:06.399099 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8611 23:06:06.399532 DramC Write-DBI on
8612 23:06:06.399881 ==
8613 23:06:06.402761 Dram Type= 6, Freq= 0, CH_1, rank 0
8614 23:06:06.408963 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8615 23:06:06.409396 ==
8616 23:06:06.409784
8617 23:06:06.410104
8618 23:06:06.412127 TX Vref Scan disable
8619 23:06:06.412570 == TX Byte 0 ==
8620 23:06:06.418656 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8621 23:06:06.419089 == TX Byte 1 ==
8622 23:06:06.422151 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8623 23:06:06.425883 DramC Write-DBI off
8624 23:06:06.426333
8625 23:06:06.426689 [DATLAT]
8626 23:06:06.429168 Freq=1600, CH1 RK0
8627 23:06:06.429676
8628 23:06:06.430041 DATLAT Default: 0xf
8629 23:06:06.433074 0, 0xFFFF, sum = 0
8630 23:06:06.433568 1, 0xFFFF, sum = 0
8631 23:06:06.434971 2, 0xFFFF, sum = 0
8632 23:06:06.435432 3, 0xFFFF, sum = 0
8633 23:06:06.438374 4, 0xFFFF, sum = 0
8634 23:06:06.438812 5, 0xFFFF, sum = 0
8635 23:06:06.441760 6, 0xFFFF, sum = 0
8636 23:06:06.444868 7, 0xFFFF, sum = 0
8637 23:06:06.445301 8, 0xFFFF, sum = 0
8638 23:06:06.448608 9, 0xFFFF, sum = 0
8639 23:06:06.449064 10, 0xFFFF, sum = 0
8640 23:06:06.452311 11, 0xFFFF, sum = 0
8641 23:06:06.452900 12, 0xFFFF, sum = 0
8642 23:06:06.454858 13, 0xFFFF, sum = 0
8643 23:06:06.455294 14, 0x0, sum = 1
8644 23:06:06.458380 15, 0x0, sum = 2
8645 23:06:06.458817 16, 0x0, sum = 3
8646 23:06:06.461516 17, 0x0, sum = 4
8647 23:06:06.461988 best_step = 15
8648 23:06:06.462339
8649 23:06:06.462694 ==
8650 23:06:06.465110 Dram Type= 6, Freq= 0, CH_1, rank 0
8651 23:06:06.468455 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8652 23:06:06.471285 ==
8653 23:06:06.471732 RX Vref Scan: 1
8654 23:06:06.472086
8655 23:06:06.474389 Set Vref Range= 24 -> 127
8656 23:06:06.474821
8657 23:06:06.477845 RX Vref 24 -> 127, step: 1
8658 23:06:06.478411
8659 23:06:06.478816 RX Delay 11 -> 252, step: 4
8660 23:06:06.479149
8661 23:06:06.481269 Set Vref, RX VrefLevel [Byte0]: 24
8662 23:06:06.484630 [Byte1]: 24
8663 23:06:06.488627
8664 23:06:06.489065 Set Vref, RX VrefLevel [Byte0]: 25
8665 23:06:06.491851 [Byte1]: 25
8666 23:06:06.495940
8667 23:06:06.496378 Set Vref, RX VrefLevel [Byte0]: 26
8668 23:06:06.499662 [Byte1]: 26
8669 23:06:06.503666
8670 23:06:06.504102 Set Vref, RX VrefLevel [Byte0]: 27
8671 23:06:06.507354 [Byte1]: 27
8672 23:06:06.511567
8673 23:06:06.511990 Set Vref, RX VrefLevel [Byte0]: 28
8674 23:06:06.514303 [Byte1]: 28
8675 23:06:06.519162
8676 23:06:06.519589 Set Vref, RX VrefLevel [Byte0]: 29
8677 23:06:06.522102 [Byte1]: 29
8678 23:06:06.526464
8679 23:06:06.526887 Set Vref, RX VrefLevel [Byte0]: 30
8680 23:06:06.532754 [Byte1]: 30
8681 23:06:06.533184
8682 23:06:06.536591 Set Vref, RX VrefLevel [Byte0]: 31
8683 23:06:06.540210 [Byte1]: 31
8684 23:06:06.540637
8685 23:06:06.542965 Set Vref, RX VrefLevel [Byte0]: 32
8686 23:06:06.546463 [Byte1]: 32
8687 23:06:06.549287
8688 23:06:06.549757 Set Vref, RX VrefLevel [Byte0]: 33
8689 23:06:06.552398 [Byte1]: 33
8690 23:06:06.556815
8691 23:06:06.557241 Set Vref, RX VrefLevel [Byte0]: 34
8692 23:06:06.560412 [Byte1]: 34
8693 23:06:06.564475
8694 23:06:06.564899 Set Vref, RX VrefLevel [Byte0]: 35
8695 23:06:06.568162 [Byte1]: 35
8696 23:06:06.572454
8697 23:06:06.572946 Set Vref, RX VrefLevel [Byte0]: 36
8698 23:06:06.575779 [Byte1]: 36
8699 23:06:06.579719
8700 23:06:06.580143 Set Vref, RX VrefLevel [Byte0]: 37
8701 23:06:06.583009 [Byte1]: 37
8702 23:06:06.587272
8703 23:06:06.587710 Set Vref, RX VrefLevel [Byte0]: 38
8704 23:06:06.590469 [Byte1]: 38
8705 23:06:06.595167
8706 23:06:06.595605 Set Vref, RX VrefLevel [Byte0]: 39
8707 23:06:06.598117 [Byte1]: 39
8708 23:06:06.602447
8709 23:06:06.602883 Set Vref, RX VrefLevel [Byte0]: 40
8710 23:06:06.605918 [Byte1]: 40
8711 23:06:06.610152
8712 23:06:06.610594 Set Vref, RX VrefLevel [Byte0]: 41
8713 23:06:06.613278 [Byte1]: 41
8714 23:06:06.617749
8715 23:06:06.618192 Set Vref, RX VrefLevel [Byte0]: 42
8716 23:06:06.620975 [Byte1]: 42
8717 23:06:06.625395
8718 23:06:06.625892 Set Vref, RX VrefLevel [Byte0]: 43
8719 23:06:06.628490 [Byte1]: 43
8720 23:06:06.633345
8721 23:06:06.633817 Set Vref, RX VrefLevel [Byte0]: 44
8722 23:06:06.636484 [Byte1]: 44
8723 23:06:06.640871
8724 23:06:06.641308 Set Vref, RX VrefLevel [Byte0]: 45
8725 23:06:06.643711 [Byte1]: 45
8726 23:06:06.648947
8727 23:06:06.649386 Set Vref, RX VrefLevel [Byte0]: 46
8728 23:06:06.651496 [Byte1]: 46
8729 23:06:06.655860
8730 23:06:06.656316 Set Vref, RX VrefLevel [Byte0]: 47
8731 23:06:06.659245 [Byte1]: 47
8732 23:06:06.663692
8733 23:06:06.664115 Set Vref, RX VrefLevel [Byte0]: 48
8734 23:06:06.666686 [Byte1]: 48
8735 23:06:06.671088
8736 23:06:06.671513 Set Vref, RX VrefLevel [Byte0]: 49
8737 23:06:06.674411 [Byte1]: 49
8738 23:06:06.678560
8739 23:06:06.678984 Set Vref, RX VrefLevel [Byte0]: 50
8740 23:06:06.681761 [Byte1]: 50
8741 23:06:06.686450
8742 23:06:06.686877 Set Vref, RX VrefLevel [Byte0]: 51
8743 23:06:06.689487 [Byte1]: 51
8744 23:06:06.694465
8745 23:06:06.694889 Set Vref, RX VrefLevel [Byte0]: 52
8746 23:06:06.697314 [Byte1]: 52
8747 23:06:06.701576
8748 23:06:06.702002 Set Vref, RX VrefLevel [Byte0]: 53
8749 23:06:06.704778 [Byte1]: 53
8750 23:06:06.709605
8751 23:06:06.710094 Set Vref, RX VrefLevel [Byte0]: 54
8752 23:06:06.712379 [Byte1]: 54
8753 23:06:06.716597
8754 23:06:06.717050 Set Vref, RX VrefLevel [Byte0]: 55
8755 23:06:06.720217 [Byte1]: 55
8756 23:06:06.724277
8757 23:06:06.724687 Set Vref, RX VrefLevel [Byte0]: 56
8758 23:06:06.727079 [Byte1]: 56
8759 23:06:06.731959
8760 23:06:06.732043 Set Vref, RX VrefLevel [Byte0]: 57
8761 23:06:06.735111 [Byte1]: 57
8762 23:06:06.739604
8763 23:06:06.739704 Set Vref, RX VrefLevel [Byte0]: 58
8764 23:06:06.742459 [Byte1]: 58
8765 23:06:06.747082
8766 23:06:06.747173 Set Vref, RX VrefLevel [Byte0]: 59
8767 23:06:06.749929 [Byte1]: 59
8768 23:06:06.754315
8769 23:06:06.754400 Set Vref, RX VrefLevel [Byte0]: 60
8770 23:06:06.757547 [Byte1]: 60
8771 23:06:06.761917
8772 23:06:06.762003 Set Vref, RX VrefLevel [Byte0]: 61
8773 23:06:06.765620 [Byte1]: 61
8774 23:06:06.769561
8775 23:06:06.769661 Set Vref, RX VrefLevel [Byte0]: 62
8776 23:06:06.772787 [Byte1]: 62
8777 23:06:06.777567
8778 23:06:06.777653 Set Vref, RX VrefLevel [Byte0]: 63
8779 23:06:06.780435 [Byte1]: 63
8780 23:06:06.784663
8781 23:06:06.784749 Set Vref, RX VrefLevel [Byte0]: 64
8782 23:06:06.788263 [Byte1]: 64
8783 23:06:06.793060
8784 23:06:06.793145 Set Vref, RX VrefLevel [Byte0]: 65
8785 23:06:06.795925 [Byte1]: 65
8786 23:06:06.800143
8787 23:06:06.800228 Set Vref, RX VrefLevel [Byte0]: 66
8788 23:06:06.804013 [Byte1]: 66
8789 23:06:06.808153
8790 23:06:06.808237 Set Vref, RX VrefLevel [Byte0]: 67
8791 23:06:06.811158 [Byte1]: 67
8792 23:06:06.815217
8793 23:06:06.815302 Set Vref, RX VrefLevel [Byte0]: 68
8794 23:06:06.818737 [Byte1]: 68
8795 23:06:06.822776
8796 23:06:06.822861 Set Vref, RX VrefLevel [Byte0]: 69
8797 23:06:06.829536 [Byte1]: 69
8798 23:06:06.829620
8799 23:06:06.832674 Set Vref, RX VrefLevel [Byte0]: 70
8800 23:06:06.836030 [Byte1]: 70
8801 23:06:06.836114
8802 23:06:06.839290 Set Vref, RX VrefLevel [Byte0]: 71
8803 23:06:06.842375 [Byte1]: 71
8804 23:06:06.846306
8805 23:06:06.846389 Set Vref, RX VrefLevel [Byte0]: 72
8806 23:06:06.849194 [Byte1]: 72
8807 23:06:06.853209
8808 23:06:06.853292 Set Vref, RX VrefLevel [Byte0]: 73
8809 23:06:06.856615 [Byte1]: 73
8810 23:06:06.861326
8811 23:06:06.861421 Set Vref, RX VrefLevel [Byte0]: 74
8812 23:06:06.864445 [Byte1]: 74
8813 23:06:06.869058
8814 23:06:06.869140 Set Vref, RX VrefLevel [Byte0]: 75
8815 23:06:06.872201 [Byte1]: 75
8816 23:06:06.876082
8817 23:06:06.876164 Final RX Vref Byte 0 = 52 to rank0
8818 23:06:06.879499 Final RX Vref Byte 1 = 60 to rank0
8819 23:06:06.882603 Final RX Vref Byte 0 = 52 to rank1
8820 23:06:06.885883 Final RX Vref Byte 1 = 60 to rank1==
8821 23:06:06.889726 Dram Type= 6, Freq= 0, CH_1, rank 0
8822 23:06:06.896104 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8823 23:06:06.896188 ==
8824 23:06:06.896256 DQS Delay:
8825 23:06:06.899608 DQS0 = 0, DQS1 = 0
8826 23:06:06.899786 DQM Delay:
8827 23:06:06.900054 DQM0 = 133, DQM1 = 127
8828 23:06:06.903224 DQ Delay:
8829 23:06:06.905966 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8830 23:06:06.909654 DQ4 =130, DQ5 =146, DQ6 =142, DQ7 =128
8831 23:06:06.912820 DQ8 =114, DQ9 =116, DQ10 =130, DQ11 =116
8832 23:06:06.916248 DQ12 =136, DQ13 =136, DQ14 =136, DQ15 =138
8833 23:06:06.916353
8834 23:06:06.916436
8835 23:06:06.916511
8836 23:06:06.919046 [DramC_TX_OE_Calibration] TA2
8837 23:06:06.922476 Original DQ_B0 (3 6) =30, OEN = 27
8838 23:06:06.925919 Original DQ_B1 (3 6) =30, OEN = 27
8839 23:06:06.929012 24, 0x0, End_B0=24 End_B1=24
8840 23:06:06.929150 25, 0x0, End_B0=25 End_B1=25
8841 23:06:06.932627 26, 0x0, End_B0=26 End_B1=26
8842 23:06:06.936227 27, 0x0, End_B0=27 End_B1=27
8843 23:06:06.939423 28, 0x0, End_B0=28 End_B1=28
8844 23:06:06.942403 29, 0x0, End_B0=29 End_B1=29
8845 23:06:06.942611 30, 0x0, End_B0=30 End_B1=30
8846 23:06:06.945635 31, 0x4141, End_B0=30 End_B1=30
8847 23:06:06.949020 Byte0 end_step=30 best_step=27
8848 23:06:06.952476 Byte1 end_step=30 best_step=27
8849 23:06:06.956239 Byte0 TX OE(2T, 0.5T) = (3, 3)
8850 23:06:06.959842 Byte1 TX OE(2T, 0.5T) = (3, 3)
8851 23:06:06.960268
8852 23:06:06.960652
8853 23:06:06.966317 [DQSOSCAuto] RK0, (LSB)MR18= 0x170d, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 398 ps
8854 23:06:06.969084 CH1 RK0: MR19=303, MR18=170D
8855 23:06:06.976074 CH1_RK0: MR19=0x303, MR18=0x170D, DQSOSC=398, MR23=63, INC=23, DEC=15
8856 23:06:06.976506
8857 23:06:06.979382 ----->DramcWriteLeveling(PI) begin...
8858 23:06:06.979837 ==
8859 23:06:06.982779 Dram Type= 6, Freq= 0, CH_1, rank 1
8860 23:06:06.985724 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8861 23:06:06.986167 ==
8862 23:06:06.988816 Write leveling (Byte 0): 24 => 24
8863 23:06:06.992452 Write leveling (Byte 1): 27 => 27
8864 23:06:06.995362 DramcWriteLeveling(PI) end<-----
8865 23:06:06.995784
8866 23:06:06.996121 ==
8867 23:06:06.999017 Dram Type= 6, Freq= 0, CH_1, rank 1
8868 23:06:07.002531 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8869 23:06:07.005377 ==
8870 23:06:07.005854 [Gating] SW mode calibration
8871 23:06:07.012478 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8872 23:06:07.018575 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8873 23:06:07.021962 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8874 23:06:07.028727 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8875 23:06:07.032287 1 4 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8876 23:06:07.035202 1 4 12 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
8877 23:06:07.041372 1 4 16 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8878 23:06:07.044770 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8879 23:06:07.048020 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8880 23:06:07.054720 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8881 23:06:07.058361 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8882 23:06:07.061520 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8883 23:06:07.068488 1 5 8 | B1->B0 | 3333 3434 | 1 1 | (1 0) (1 1)
8884 23:06:07.071758 1 5 12 | B1->B0 | 2424 3434 | 0 1 | (1 0) (1 0)
8885 23:06:07.075326 1 5 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8886 23:06:07.081250 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8887 23:06:07.085060 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8888 23:06:07.088166 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8889 23:06:07.094909 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8890 23:06:07.098835 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8891 23:06:07.101088 1 6 8 | B1->B0 | 2c2c 2323 | 1 0 | (0 0) (0 0)
8892 23:06:07.108475 1 6 12 | B1->B0 | 4646 3030 | 0 0 | (0 0) (0 0)
8893 23:06:07.111206 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8894 23:06:07.114558 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8895 23:06:07.120991 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8896 23:06:07.124353 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8897 23:06:07.128375 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8898 23:06:07.133987 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8899 23:06:07.137389 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8900 23:06:07.141071 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8901 23:06:07.148103 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8902 23:06:07.151150 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8903 23:06:07.154393 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8904 23:06:07.161394 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8905 23:06:07.164066 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8906 23:06:07.167802 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8907 23:06:07.174329 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8908 23:06:07.176962 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8909 23:06:07.180420 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8910 23:06:07.187155 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8911 23:06:07.190318 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8912 23:06:07.193851 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8913 23:06:07.199982 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8914 23:06:07.203738 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8915 23:06:07.206748 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8916 23:06:07.213227 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8917 23:06:07.216809 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8918 23:06:07.220284 Total UI for P1: 0, mck2ui 16
8919 23:06:07.223212 best dqsien dly found for B0: ( 1, 9, 10)
8920 23:06:07.226858 Total UI for P1: 0, mck2ui 16
8921 23:06:07.229929 best dqsien dly found for B1: ( 1, 9, 10)
8922 23:06:07.232917 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8923 23:06:07.236022 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8924 23:06:07.236124
8925 23:06:07.239282 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8926 23:06:07.242456 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8927 23:06:07.245620 [Gating] SW calibration Done
8928 23:06:07.245706 ==
8929 23:06:07.249602 Dram Type= 6, Freq= 0, CH_1, rank 1
8930 23:06:07.255938 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8931 23:06:07.256024 ==
8932 23:06:07.256110 RX Vref Scan: 0
8933 23:06:07.256192
8934 23:06:07.259686 RX Vref 0 -> 0, step: 1
8935 23:06:07.259794
8936 23:06:07.262537 RX Delay 0 -> 252, step: 8
8937 23:06:07.265731 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8938 23:06:07.268834 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8939 23:06:07.272076 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8940 23:06:07.275526 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8941 23:06:07.281842 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8942 23:06:07.285379 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8943 23:06:07.288510 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8944 23:06:07.292429 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8945 23:06:07.295439 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8946 23:06:07.301932 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8947 23:06:07.305390 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8948 23:06:07.308738 iDelay=208, Bit 11, Center 123 (64 ~ 183) 120
8949 23:06:07.311977 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8950 23:06:07.315346 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8951 23:06:07.322023 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8952 23:06:07.325239 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8953 23:06:07.325324 ==
8954 23:06:07.328699 Dram Type= 6, Freq= 0, CH_1, rank 1
8955 23:06:07.331704 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8956 23:06:07.331785 ==
8957 23:06:07.334792 DQS Delay:
8958 23:06:07.334868 DQS0 = 0, DQS1 = 0
8959 23:06:07.338457 DQM Delay:
8960 23:06:07.338541 DQM0 = 136, DQM1 = 129
8961 23:06:07.338627 DQ Delay:
8962 23:06:07.344740 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8963 23:06:07.348256 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8964 23:06:07.351439 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8965 23:06:07.354768 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8966 23:06:07.354852
8967 23:06:07.354938
8968 23:06:07.355020 ==
8969 23:06:07.358015 Dram Type= 6, Freq= 0, CH_1, rank 1
8970 23:06:07.361187 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8971 23:06:07.361272 ==
8972 23:06:07.361374
8973 23:06:07.361496
8974 23:06:07.364570 TX Vref Scan disable
8975 23:06:07.367598 == TX Byte 0 ==
8976 23:06:07.370839 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8977 23:06:07.374412 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8978 23:06:07.377780 == TX Byte 1 ==
8979 23:06:07.380973 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8980 23:06:07.384215 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8981 23:06:07.384301 ==
8982 23:06:07.387569 Dram Type= 6, Freq= 0, CH_1, rank 1
8983 23:06:07.394255 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8984 23:06:07.394342 ==
8985 23:06:07.405665
8986 23:06:07.408853 TX Vref early break, caculate TX vref
8987 23:06:07.412287 TX Vref=16, minBit 1, minWin=22, winSum=385
8988 23:06:07.416287 TX Vref=18, minBit 1, minWin=23, winSum=393
8989 23:06:07.419048 TX Vref=20, minBit 1, minWin=24, winSum=403
8990 23:06:07.422703 TX Vref=22, minBit 1, minWin=24, winSum=409
8991 23:06:07.426435 TX Vref=24, minBit 0, minWin=24, winSum=415
8992 23:06:07.432564 TX Vref=26, minBit 0, minWin=25, winSum=423
8993 23:06:07.435682 TX Vref=28, minBit 0, minWin=24, winSum=418
8994 23:06:07.439175 TX Vref=30, minBit 0, minWin=24, winSum=416
8995 23:06:07.442684 TX Vref=32, minBit 0, minWin=23, winSum=408
8996 23:06:07.445996 TX Vref=34, minBit 1, minWin=23, winSum=396
8997 23:06:07.452320 [TxChooseVref] Worse bit 0, Min win 25, Win sum 423, Final Vref 26
8998 23:06:07.452485
8999 23:06:07.455363 Final TX Range 0 Vref 26
9000 23:06:07.455533
9001 23:06:07.455729 ==
9002 23:06:07.459350 Dram Type= 6, Freq= 0, CH_1, rank 1
9003 23:06:07.462303 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9004 23:06:07.462750 ==
9005 23:06:07.463282
9006 23:06:07.463708
9007 23:06:07.465550 TX Vref Scan disable
9008 23:06:07.472136 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
9009 23:06:07.472577 == TX Byte 0 ==
9010 23:06:07.475356 u2DelayCellOfst[0]=18 cells (5 PI)
9011 23:06:07.478694 u2DelayCellOfst[1]=11 cells (3 PI)
9012 23:06:07.481886 u2DelayCellOfst[2]=0 cells (0 PI)
9013 23:06:07.485096 u2DelayCellOfst[3]=7 cells (2 PI)
9014 23:06:07.488398 u2DelayCellOfst[4]=7 cells (2 PI)
9015 23:06:07.491981 u2DelayCellOfst[5]=22 cells (6 PI)
9016 23:06:07.495294 u2DelayCellOfst[6]=18 cells (5 PI)
9017 23:06:07.498439 u2DelayCellOfst[7]=7 cells (2 PI)
9018 23:06:07.501702 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
9019 23:06:07.505280 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
9020 23:06:07.508695 == TX Byte 1 ==
9021 23:06:07.511591 u2DelayCellOfst[8]=0 cells (0 PI)
9022 23:06:07.512029 u2DelayCellOfst[9]=3 cells (1 PI)
9023 23:06:07.515529 u2DelayCellOfst[10]=14 cells (4 PI)
9024 23:06:07.518276 u2DelayCellOfst[11]=7 cells (2 PI)
9025 23:06:07.521725 u2DelayCellOfst[12]=14 cells (4 PI)
9026 23:06:07.525249 u2DelayCellOfst[13]=18 cells (5 PI)
9027 23:06:07.528271 u2DelayCellOfst[14]=18 cells (5 PI)
9028 23:06:07.531533 u2DelayCellOfst[15]=18 cells (5 PI)
9029 23:06:07.538186 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
9030 23:06:07.541296 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
9031 23:06:07.541772 DramC Write-DBI on
9032 23:06:07.542120 ==
9033 23:06:07.544475 Dram Type= 6, Freq= 0, CH_1, rank 1
9034 23:06:07.551262 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9035 23:06:07.551697 ==
9036 23:06:07.552045
9037 23:06:07.552363
9038 23:06:07.554682 TX Vref Scan disable
9039 23:06:07.555113 == TX Byte 0 ==
9040 23:06:07.561020 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
9041 23:06:07.561482 == TX Byte 1 ==
9042 23:06:07.564281 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
9043 23:06:07.567713 DramC Write-DBI off
9044 23:06:07.568144
9045 23:06:07.568485 [DATLAT]
9046 23:06:07.571753 Freq=1600, CH1 RK1
9047 23:06:07.572291
9048 23:06:07.572638 DATLAT Default: 0xf
9049 23:06:07.574257 0, 0xFFFF, sum = 0
9050 23:06:07.574696 1, 0xFFFF, sum = 0
9051 23:06:07.577985 2, 0xFFFF, sum = 0
9052 23:06:07.578422 3, 0xFFFF, sum = 0
9053 23:06:07.581081 4, 0xFFFF, sum = 0
9054 23:06:07.581567 5, 0xFFFF, sum = 0
9055 23:06:07.584807 6, 0xFFFF, sum = 0
9056 23:06:07.585264 7, 0xFFFF, sum = 0
9057 23:06:07.587546 8, 0xFFFF, sum = 0
9058 23:06:07.587983 9, 0xFFFF, sum = 0
9059 23:06:07.590856 10, 0xFFFF, sum = 0
9060 23:06:07.594029 11, 0xFFFF, sum = 0
9061 23:06:07.594456 12, 0xFFFF, sum = 0
9062 23:06:07.597555 13, 0xFFFF, sum = 0
9063 23:06:07.597985 14, 0x0, sum = 1
9064 23:06:07.600841 15, 0x0, sum = 2
9065 23:06:07.601302 16, 0x0, sum = 3
9066 23:06:07.604555 17, 0x0, sum = 4
9067 23:06:07.604977 best_step = 15
9068 23:06:07.605311
9069 23:06:07.605675 ==
9070 23:06:07.607472 Dram Type= 6, Freq= 0, CH_1, rank 1
9071 23:06:07.610654 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9072 23:06:07.611107 ==
9073 23:06:07.613875 RX Vref Scan: 0
9074 23:06:07.614295
9075 23:06:07.616926 RX Vref 0 -> 0, step: 1
9076 23:06:07.617390
9077 23:06:07.617784 RX Delay 11 -> 252, step: 4
9078 23:06:07.624294 iDelay=203, Bit 0, Center 138 (87 ~ 190) 104
9079 23:06:07.627861 iDelay=203, Bit 1, Center 128 (75 ~ 182) 108
9080 23:06:07.630861 iDelay=203, Bit 2, Center 122 (67 ~ 178) 112
9081 23:06:07.634287 iDelay=203, Bit 3, Center 130 (79 ~ 182) 104
9082 23:06:07.637893 iDelay=203, Bit 4, Center 134 (79 ~ 190) 112
9083 23:06:07.644149 iDelay=203, Bit 5, Center 146 (95 ~ 198) 104
9084 23:06:07.647871 iDelay=203, Bit 6, Center 146 (91 ~ 202) 112
9085 23:06:07.650664 iDelay=203, Bit 7, Center 130 (79 ~ 182) 104
9086 23:06:07.654307 iDelay=203, Bit 8, Center 112 (55 ~ 170) 116
9087 23:06:07.660911 iDelay=203, Bit 9, Center 116 (63 ~ 170) 108
9088 23:06:07.664129 iDelay=203, Bit 10, Center 128 (75 ~ 182) 108
9089 23:06:07.667200 iDelay=203, Bit 11, Center 118 (67 ~ 170) 104
9090 23:06:07.670935 iDelay=203, Bit 12, Center 136 (83 ~ 190) 108
9091 23:06:07.673921 iDelay=203, Bit 13, Center 136 (83 ~ 190) 108
9092 23:06:07.680387 iDelay=203, Bit 14, Center 134 (79 ~ 190) 112
9093 23:06:07.683513 iDelay=203, Bit 15, Center 138 (83 ~ 194) 112
9094 23:06:07.683947 ==
9095 23:06:07.686979 Dram Type= 6, Freq= 0, CH_1, rank 1
9096 23:06:07.690030 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9097 23:06:07.690464 ==
9098 23:06:07.693843 DQS Delay:
9099 23:06:07.694272 DQS0 = 0, DQS1 = 0
9100 23:06:07.694613 DQM Delay:
9101 23:06:07.696926 DQM0 = 134, DQM1 = 127
9102 23:06:07.697353 DQ Delay:
9103 23:06:07.700475 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =130
9104 23:06:07.703313 DQ4 =134, DQ5 =146, DQ6 =146, DQ7 =130
9105 23:06:07.710603 DQ8 =112, DQ9 =116, DQ10 =128, DQ11 =118
9106 23:06:07.713674 DQ12 =136, DQ13 =136, DQ14 =134, DQ15 =138
9107 23:06:07.714107
9108 23:06:07.714451
9109 23:06:07.714770
9110 23:06:07.717223 [DramC_TX_OE_Calibration] TA2
9111 23:06:07.720230 Original DQ_B0 (3 6) =30, OEN = 27
9112 23:06:07.723499 Original DQ_B1 (3 6) =30, OEN = 27
9113 23:06:07.724051 24, 0x0, End_B0=24 End_B1=24
9114 23:06:07.726748 25, 0x0, End_B0=25 End_B1=25
9115 23:06:07.729792 26, 0x0, End_B0=26 End_B1=26
9116 23:06:07.733166 27, 0x0, End_B0=27 End_B1=27
9117 23:06:07.733714 28, 0x0, End_B0=28 End_B1=28
9118 23:06:07.736739 29, 0x0, End_B0=29 End_B1=29
9119 23:06:07.740418 30, 0x0, End_B0=30 End_B1=30
9120 23:06:07.743168 31, 0x5151, End_B0=30 End_B1=30
9121 23:06:07.746290 Byte0 end_step=30 best_step=27
9122 23:06:07.749530 Byte1 end_step=30 best_step=27
9123 23:06:07.749963 Byte0 TX OE(2T, 0.5T) = (3, 3)
9124 23:06:07.752851 Byte1 TX OE(2T, 0.5T) = (3, 3)
9125 23:06:07.753335
9126 23:06:07.753733
9127 23:06:07.762759 [DQSOSCAuto] RK1, (LSB)MR18= 0xf0c, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 402 ps
9128 23:06:07.766045 CH1 RK1: MR19=303, MR18=F0C
9129 23:06:07.769355 CH1_RK1: MR19=0x303, MR18=0xF0C, DQSOSC=402, MR23=63, INC=22, DEC=15
9130 23:06:07.772705 [RxdqsGatingPostProcess] freq 1600
9131 23:06:07.779338 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9132 23:06:07.782616 best DQS0 dly(2T, 0.5T) = (1, 1)
9133 23:06:07.786023 best DQS1 dly(2T, 0.5T) = (1, 1)
9134 23:06:07.789301 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9135 23:06:07.792406 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9136 23:06:07.796426 best DQS0 dly(2T, 0.5T) = (1, 1)
9137 23:06:07.799010 best DQS1 dly(2T, 0.5T) = (1, 1)
9138 23:06:07.799437 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9139 23:06:07.802354 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9140 23:06:07.805915 Pre-setting of DQS Precalculation
9141 23:06:07.812406 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9142 23:06:07.818998 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9143 23:06:07.825810 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9144 23:06:07.826235
9145 23:06:07.826569
9146 23:06:07.829301 [Calibration Summary] 3200 Mbps
9147 23:06:07.832425 CH 0, Rank 0
9148 23:06:07.832850 SW Impedance : PASS
9149 23:06:07.835763 DUTY Scan : NO K
9150 23:06:07.839028 ZQ Calibration : PASS
9151 23:06:07.839452 Jitter Meter : NO K
9152 23:06:07.842392 CBT Training : PASS
9153 23:06:07.842814 Write leveling : PASS
9154 23:06:07.845904 RX DQS gating : PASS
9155 23:06:07.849102 RX DQ/DQS(RDDQC) : PASS
9156 23:06:07.849576 TX DQ/DQS : PASS
9157 23:06:07.852179 RX DATLAT : PASS
9158 23:06:07.855388 RX DQ/DQS(Engine): PASS
9159 23:06:07.855809 TX OE : PASS
9160 23:06:07.858994 All Pass.
9161 23:06:07.859415
9162 23:06:07.859751 CH 0, Rank 1
9163 23:06:07.862049 SW Impedance : PASS
9164 23:06:07.862472 DUTY Scan : NO K
9165 23:06:07.865842 ZQ Calibration : PASS
9166 23:06:07.868645 Jitter Meter : NO K
9167 23:06:07.869067 CBT Training : PASS
9168 23:06:07.872450 Write leveling : PASS
9169 23:06:07.875497 RX DQS gating : PASS
9170 23:06:07.875917 RX DQ/DQS(RDDQC) : PASS
9171 23:06:07.878464 TX DQ/DQS : PASS
9172 23:06:07.882010 RX DATLAT : PASS
9173 23:06:07.882449 RX DQ/DQS(Engine): PASS
9174 23:06:07.885326 TX OE : PASS
9175 23:06:07.885812 All Pass.
9176 23:06:07.886162
9177 23:06:07.888399 CH 1, Rank 0
9178 23:06:07.888838 SW Impedance : PASS
9179 23:06:07.892078 DUTY Scan : NO K
9180 23:06:07.895040 ZQ Calibration : PASS
9181 23:06:07.895477 Jitter Meter : NO K
9182 23:06:07.898355 CBT Training : PASS
9183 23:06:07.902586 Write leveling : PASS
9184 23:06:07.903024 RX DQS gating : PASS
9185 23:06:07.905184 RX DQ/DQS(RDDQC) : PASS
9186 23:06:07.905669 TX DQ/DQS : PASS
9187 23:06:07.908807 RX DATLAT : PASS
9188 23:06:07.911328 RX DQ/DQS(Engine): PASS
9189 23:06:07.911766 TX OE : PASS
9190 23:06:07.914981 All Pass.
9191 23:06:07.915420
9192 23:06:07.915861 CH 1, Rank 1
9193 23:06:07.918107 SW Impedance : PASS
9194 23:06:07.918544 DUTY Scan : NO K
9195 23:06:07.921502 ZQ Calibration : PASS
9196 23:06:07.925054 Jitter Meter : NO K
9197 23:06:07.925521 CBT Training : PASS
9198 23:06:07.928433 Write leveling : PASS
9199 23:06:07.931606 RX DQS gating : PASS
9200 23:06:07.932044 RX DQ/DQS(RDDQC) : PASS
9201 23:06:07.934813 TX DQ/DQS : PASS
9202 23:06:07.938772 RX DATLAT : PASS
9203 23:06:07.939212 RX DQ/DQS(Engine): PASS
9204 23:06:07.941923 TX OE : PASS
9205 23:06:07.942358 All Pass.
9206 23:06:07.942799
9207 23:06:07.945201 DramC Write-DBI on
9208 23:06:07.948358 PER_BANK_REFRESH: Hybrid Mode
9209 23:06:07.948797 TX_TRACKING: ON
9210 23:06:07.958236 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9211 23:06:07.964905 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9212 23:06:07.971229 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9213 23:06:07.974805 [FAST_K] Save calibration result to emmc
9214 23:06:07.978092 sync common calibartion params.
9215 23:06:07.981043 sync cbt_mode0:1, 1:1
9216 23:06:07.985282 dram_init: ddr_geometry: 2
9217 23:06:07.985764 dram_init: ddr_geometry: 2
9218 23:06:07.987650 dram_init: ddr_geometry: 2
9219 23:06:07.990714 0:dram_rank_size:100000000
9220 23:06:07.994484 1:dram_rank_size:100000000
9221 23:06:07.998116 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9222 23:06:08.000838 DFS_SHUFFLE_HW_MODE: ON
9223 23:06:08.004165 dramc_set_vcore_voltage set vcore to 725000
9224 23:06:08.007594 Read voltage for 1600, 0
9225 23:06:08.008028 Vio18 = 0
9226 23:06:08.010565 Vcore = 725000
9227 23:06:08.010998 Vdram = 0
9228 23:06:08.011439 Vddq = 0
9229 23:06:08.011853 Vmddr = 0
9230 23:06:08.014094 switch to 3200 Mbps bootup
9231 23:06:08.017185 [DramcRunTimeConfig]
9232 23:06:08.017686 PHYPLL
9233 23:06:08.020502 DPM_CONTROL_AFTERK: ON
9234 23:06:08.020937 PER_BANK_REFRESH: ON
9235 23:06:08.023911 REFRESH_OVERHEAD_REDUCTION: ON
9236 23:06:08.027205 CMD_PICG_NEW_MODE: OFF
9237 23:06:08.027640 XRTWTW_NEW_MODE: ON
9238 23:06:08.030396 XRTRTR_NEW_MODE: ON
9239 23:06:08.030833 TX_TRACKING: ON
9240 23:06:08.033642 RDSEL_TRACKING: OFF
9241 23:06:08.034084 DQS Precalculation for DVFS: ON
9242 23:06:08.036865 RX_TRACKING: OFF
9243 23:06:08.037304 HW_GATING DBG: ON
9244 23:06:08.040673 ZQCS_ENABLE_LP4: ON
9245 23:06:08.043675 RX_PICG_NEW_MODE: ON
9246 23:06:08.044113 TX_PICG_NEW_MODE: ON
9247 23:06:08.047375 ENABLE_RX_DCM_DPHY: ON
9248 23:06:08.050246 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9249 23:06:08.053531 DUMMY_READ_FOR_TRACKING: OFF
9250 23:06:08.053978 !!! SPM_CONTROL_AFTERK: OFF
9251 23:06:08.057064 !!! SPM could not control APHY
9252 23:06:08.060191 IMPEDANCE_TRACKING: ON
9253 23:06:08.060621 TEMP_SENSOR: ON
9254 23:06:08.063735 HW_SAVE_FOR_SR: OFF
9255 23:06:08.066841 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9256 23:06:08.070071 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9257 23:06:08.070500 Read ODT Tracking: ON
9258 23:06:08.073331 Refresh Rate DeBounce: ON
9259 23:06:08.076766 DFS_NO_QUEUE_FLUSH: ON
9260 23:06:08.080099 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9261 23:06:08.080528 ENABLE_DFS_RUNTIME_MRW: OFF
9262 23:06:08.083659 DDR_RESERVE_NEW_MODE: ON
9263 23:06:08.086661 MR_CBT_SWITCH_FREQ: ON
9264 23:06:08.087091 =========================
9265 23:06:08.106666 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9266 23:06:08.110092 dram_init: ddr_geometry: 2
9267 23:06:08.128307 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9268 23:06:08.131826 dram_init: dram init end (result: 0)
9269 23:06:08.138499 DRAM-K: Full calibration passed in 24638 msecs
9270 23:06:08.141913 MRC: failed to locate region type 0.
9271 23:06:08.142509 DRAM rank0 size:0x100000000,
9272 23:06:08.144698 DRAM rank1 size=0x100000000
9273 23:06:08.154635 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9274 23:06:08.161344 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9275 23:06:08.168118 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9276 23:06:08.177520 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9277 23:06:08.177956 DRAM rank0 size:0x100000000,
9278 23:06:08.181515 DRAM rank1 size=0x100000000
9279 23:06:08.181945 CBMEM:
9280 23:06:08.184153 IMD: root @ 0xfffff000 254 entries.
9281 23:06:08.187648 IMD: root @ 0xffffec00 62 entries.
9282 23:06:08.191013 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9283 23:06:08.197616 WARNING: RO_VPD is uninitialized or empty.
9284 23:06:08.200743 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9285 23:06:08.208400 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9286 23:06:08.220840 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9287 23:06:08.232334 BS: romstage times (exec / console): total (unknown) / 24127 ms
9288 23:06:08.232777
9289 23:06:08.233217
9290 23:06:08.242330 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9291 23:06:08.245795 ARM64: Exception handlers installed.
9292 23:06:08.248894 ARM64: Testing exception
9293 23:06:08.252124 ARM64: Done test exception
9294 23:06:08.252528 Enumerating buses...
9295 23:06:08.255542 Show all devs... Before device enumeration.
9296 23:06:08.258867 Root Device: enabled 1
9297 23:06:08.261874 CPU_CLUSTER: 0: enabled 1
9298 23:06:08.262308 CPU: 00: enabled 1
9299 23:06:08.265395 Compare with tree...
9300 23:06:08.265862 Root Device: enabled 1
9301 23:06:08.268890 CPU_CLUSTER: 0: enabled 1
9302 23:06:08.272514 CPU: 00: enabled 1
9303 23:06:08.272945 Root Device scanning...
9304 23:06:08.275542 scan_static_bus for Root Device
9305 23:06:08.278939 CPU_CLUSTER: 0 enabled
9306 23:06:08.282126 scan_static_bus for Root Device done
9307 23:06:08.284973 scan_bus: bus Root Device finished in 8 msecs
9308 23:06:08.285442 done
9309 23:06:08.291793 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9310 23:06:08.295036 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9311 23:06:08.301768 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9312 23:06:08.304881 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9313 23:06:08.308581 Allocating resources...
9314 23:06:08.311473 Reading resources...
9315 23:06:08.314732 Root Device read_resources bus 0 link: 0
9316 23:06:08.318288 DRAM rank0 size:0x100000000,
9317 23:06:08.318717 DRAM rank1 size=0x100000000
9318 23:06:08.324832 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9319 23:06:08.325262 CPU: 00 missing read_resources
9320 23:06:08.331542 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9321 23:06:08.334917 Root Device read_resources bus 0 link: 0 done
9322 23:06:08.335350 Done reading resources.
9323 23:06:08.341374 Show resources in subtree (Root Device)...After reading.
9324 23:06:08.345201 Root Device child on link 0 CPU_CLUSTER: 0
9325 23:06:08.348190 CPU_CLUSTER: 0 child on link 0 CPU: 00
9326 23:06:08.358009 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9327 23:06:08.358441 CPU: 00
9328 23:06:08.361245 Root Device assign_resources, bus 0 link: 0
9329 23:06:08.364826 CPU_CLUSTER: 0 missing set_resources
9330 23:06:08.371211 Root Device assign_resources, bus 0 link: 0 done
9331 23:06:08.371743 Done setting resources.
9332 23:06:08.377598 Show resources in subtree (Root Device)...After assigning values.
9333 23:06:08.381246 Root Device child on link 0 CPU_CLUSTER: 0
9334 23:06:08.385182 CPU_CLUSTER: 0 child on link 0 CPU: 00
9335 23:06:08.393868 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9336 23:06:08.394527 CPU: 00
9337 23:06:08.397663 Done allocating resources.
9338 23:06:08.403985 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9339 23:06:08.404419 Enabling resources...
9340 23:06:08.407360 done.
9341 23:06:08.410452 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9342 23:06:08.413843 Initializing devices...
9343 23:06:08.414362 Root Device init
9344 23:06:08.416750 init hardware done!
9345 23:06:08.417401 0x00000018: ctrlr->caps
9346 23:06:08.420178 52.000 MHz: ctrlr->f_max
9347 23:06:08.423306 0.400 MHz: ctrlr->f_min
9348 23:06:08.423968 0x40ff8080: ctrlr->voltages
9349 23:06:08.426977 sclk: 390625
9350 23:06:08.427538 Bus Width = 1
9351 23:06:08.430639 sclk: 390625
9352 23:06:08.431224 Bus Width = 1
9353 23:06:08.433266 Early init status = 3
9354 23:06:08.437185 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9355 23:06:08.440073 in-header: 03 fc 00 00 01 00 00 00
9356 23:06:08.443354 in-data: 00
9357 23:06:08.446778 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9358 23:06:08.452082 in-header: 03 fd 00 00 00 00 00 00
9359 23:06:08.455726 in-data:
9360 23:06:08.459178 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9361 23:06:08.462624 in-header: 03 fc 00 00 01 00 00 00
9362 23:06:08.465556 in-data: 00
9363 23:06:08.469058 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9364 23:06:08.473808 in-header: 03 fd 00 00 00 00 00 00
9365 23:06:08.476810 in-data:
9366 23:06:08.479930 [SSUSB] Setting up USB HOST controller...
9367 23:06:08.483690 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9368 23:06:08.486457 [SSUSB] phy power-on done.
9369 23:06:08.489693 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9370 23:06:08.496504 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9371 23:06:08.499490 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9372 23:06:08.506414 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9373 23:06:08.512562 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9374 23:06:08.519318 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9375 23:06:08.526060 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9376 23:06:08.532831 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9377 23:06:08.535995 SPM: binary array size = 0x9dc
9378 23:06:08.539423 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9379 23:06:08.546130 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9380 23:06:08.552874 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9381 23:06:08.559063 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9382 23:06:08.562232 configure_display: Starting display init
9383 23:06:08.596535 anx7625_power_on_init: Init interface.
9384 23:06:08.600080 anx7625_disable_pd_protocol: Disabled PD feature.
9385 23:06:08.603432 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9386 23:06:08.631202 anx7625_start_dp_work: Secure OCM version=00
9387 23:06:08.634117 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9388 23:06:08.649517 sp_tx_get_edid_block: EDID Block = 1
9389 23:06:08.752086 Extracted contents:
9390 23:06:08.755248 header: 00 ff ff ff ff ff ff 00
9391 23:06:08.758493 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9392 23:06:08.761928 version: 01 04
9393 23:06:08.765495 basic params: 95 1f 11 78 0a
9394 23:06:08.768296 chroma info: 76 90 94 55 54 90 27 21 50 54
9395 23:06:08.771666 established: 00 00 00
9396 23:06:08.778484 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9397 23:06:08.781920 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9398 23:06:08.787974 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9399 23:06:08.794755 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9400 23:06:08.801258 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9401 23:06:08.804295 extensions: 00
9402 23:06:08.804883 checksum: fb
9403 23:06:08.805437
9404 23:06:08.807875 Manufacturer: IVO Model 57d Serial Number 0
9405 23:06:08.811113 Made week 0 of 2020
9406 23:06:08.814111 EDID version: 1.4
9407 23:06:08.814561 Digital display
9408 23:06:08.817390 6 bits per primary color channel
9409 23:06:08.817894 DisplayPort interface
9410 23:06:08.821079 Maximum image size: 31 cm x 17 cm
9411 23:06:08.824847 Gamma: 220%
9412 23:06:08.825469 Check DPMS levels
9413 23:06:08.831085 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9414 23:06:08.834314 First detailed timing is preferred timing
9415 23:06:08.834737 Established timings supported:
9416 23:06:08.837793 Standard timings supported:
9417 23:06:08.841405 Detailed timings
9418 23:06:08.844501 Hex of detail: 383680a07038204018303c0035ae10000019
9419 23:06:08.850793 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9420 23:06:08.854293 0780 0798 07c8 0820 hborder 0
9421 23:06:08.857030 0438 043b 0447 0458 vborder 0
9422 23:06:08.860426 -hsync -vsync
9423 23:06:08.860877 Did detailed timing
9424 23:06:08.867277 Hex of detail: 000000000000000000000000000000000000
9425 23:06:08.870629 Manufacturer-specified data, tag 0
9426 23:06:08.873458 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9427 23:06:08.877100 ASCII string: InfoVision
9428 23:06:08.880394 Hex of detail: 000000fe00523134304e574635205248200a
9429 23:06:08.883270 ASCII string: R140NWF5 RH
9430 23:06:08.883874 Checksum
9431 23:06:08.887185 Checksum: 0xfb (valid)
9432 23:06:08.890439 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9433 23:06:08.893260 DSI data_rate: 832800000 bps
9434 23:06:08.899915 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9435 23:06:08.903093 anx7625_parse_edid: pixelclock(138800).
9436 23:06:08.906368 hactive(1920), hsync(48), hfp(24), hbp(88)
9437 23:06:08.909687 vactive(1080), vsync(12), vfp(3), vbp(17)
9438 23:06:08.912924 anx7625_dsi_config: config dsi.
9439 23:06:08.919885 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9440 23:06:08.933931 anx7625_dsi_config: success to config DSI
9441 23:06:08.936872 anx7625_dp_start: MIPI phy setup OK.
9442 23:06:08.940509 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9443 23:06:08.943677 mtk_ddp_mode_set invalid vrefresh 60
9444 23:06:08.947388 main_disp_path_setup
9445 23:06:08.947956 ovl_layer_smi_id_en
9446 23:06:08.950201 ovl_layer_smi_id_en
9447 23:06:08.950649 ccorr_config
9448 23:06:08.950995 aal_config
9449 23:06:08.953545 gamma_config
9450 23:06:08.954119 postmask_config
9451 23:06:08.956851 dither_config
9452 23:06:08.960210 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9453 23:06:08.966766 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9454 23:06:08.970103 Root Device init finished in 552 msecs
9455 23:06:08.973469 CPU_CLUSTER: 0 init
9456 23:06:08.979945 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9457 23:06:08.987024 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9458 23:06:08.987615 APU_MBOX 0x190000b0 = 0x10001
9459 23:06:08.989902 APU_MBOX 0x190001b0 = 0x10001
9460 23:06:08.993223 APU_MBOX 0x190005b0 = 0x10001
9461 23:06:08.996279 APU_MBOX 0x190006b0 = 0x10001
9462 23:06:09.003442 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9463 23:06:09.012929 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9464 23:06:09.025157 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9465 23:06:09.032075 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9466 23:06:09.043526 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9467 23:06:09.052518 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9468 23:06:09.056150 CPU_CLUSTER: 0 init finished in 81 msecs
9469 23:06:09.059522 Devices initialized
9470 23:06:09.062619 Show all devs... After init.
9471 23:06:09.063044 Root Device: enabled 1
9472 23:06:09.065865 CPU_CLUSTER: 0: enabled 1
9473 23:06:09.069085 CPU: 00: enabled 1
9474 23:06:09.072632 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9475 23:06:09.075658 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9476 23:06:09.079371 ELOG: NV offset 0x57f000 size 0x1000
9477 23:06:09.085619 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9478 23:06:09.092308 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9479 23:06:09.095638 ELOG: Event(17) added with size 13 at 2023-12-01 23:06:09 UTC
9480 23:06:09.099301 out: cmd=0x121: 03 db 21 01 00 00 00 00
9481 23:06:09.102947 in-header: 03 b8 00 00 2c 00 00 00
9482 23:06:09.116268 in-data: a7 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9483 23:06:09.122812 ELOG: Event(A1) added with size 10 at 2023-12-01 23:06:09 UTC
9484 23:06:09.129228 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9485 23:06:09.135899 ELOG: Event(A0) added with size 9 at 2023-12-01 23:06:09 UTC
9486 23:06:09.139120 elog_add_boot_reason: Logged dev mode boot
9487 23:06:09.142662 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9488 23:06:09.146072 Finalize devices...
9489 23:06:09.146535 Devices finalized
9490 23:06:09.152822 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9491 23:06:09.155985 Writing coreboot table at 0xffe64000
9492 23:06:09.159463 0. 000000000010a000-0000000000113fff: RAMSTAGE
9493 23:06:09.162041 1. 0000000040000000-00000000400fffff: RAM
9494 23:06:09.168976 2. 0000000040100000-000000004032afff: RAMSTAGE
9495 23:06:09.172018 3. 000000004032b000-00000000545fffff: RAM
9496 23:06:09.175540 4. 0000000054600000-000000005465ffff: BL31
9497 23:06:09.178794 5. 0000000054660000-00000000ffe63fff: RAM
9498 23:06:09.185308 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9499 23:06:09.188776 7. 0000000100000000-000000023fffffff: RAM
9500 23:06:09.192309 Passing 5 GPIOs to payload:
9501 23:06:09.195529 NAME | PORT | POLARITY | VALUE
9502 23:06:09.198444 EC in RW | 0x000000aa | low | undefined
9503 23:06:09.204964 EC interrupt | 0x00000005 | low | undefined
9504 23:06:09.208430 TPM interrupt | 0x000000ab | high | undefined
9505 23:06:09.214953 SD card detect | 0x00000011 | high | undefined
9506 23:06:09.218386 speaker enable | 0x00000093 | high | undefined
9507 23:06:09.221441 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9508 23:06:09.224621 in-header: 03 f9 00 00 02 00 00 00
9509 23:06:09.227868 in-data: 02 00
9510 23:06:09.228464 ADC[4]: Raw value=900443 ID=7
9511 23:06:09.231067 ADC[3]: Raw value=213282 ID=1
9512 23:06:09.234741 RAM Code: 0x71
9513 23:06:09.237800 ADC[6]: Raw value=75036 ID=0
9514 23:06:09.238259 ADC[5]: Raw value=213652 ID=1
9515 23:06:09.241299 SKU Code: 0x1
9516 23:06:09.244758 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum a1a9
9517 23:06:09.247996 coreboot table: 964 bytes.
9518 23:06:09.251099 IMD ROOT 0. 0xfffff000 0x00001000
9519 23:06:09.254332 IMD SMALL 1. 0xffffe000 0x00001000
9520 23:06:09.258129 RO MCACHE 2. 0xffffc000 0x00001104
9521 23:06:09.260999 CONSOLE 3. 0xfff7c000 0x00080000
9522 23:06:09.264227 FMAP 4. 0xfff7b000 0x00000452
9523 23:06:09.267556 TIME STAMP 5. 0xfff7a000 0x00000910
9524 23:06:09.270587 VBOOT WORK 6. 0xfff66000 0x00014000
9525 23:06:09.274284 RAMOOPS 7. 0xffe66000 0x00100000
9526 23:06:09.277384 COREBOOT 8. 0xffe64000 0x00002000
9527 23:06:09.280566 IMD small region:
9528 23:06:09.283827 IMD ROOT 0. 0xffffec00 0x00000400
9529 23:06:09.287332 VPD 1. 0xffffeb80 0x0000006c
9530 23:06:09.290615 MMC STATUS 2. 0xffffeb60 0x00000004
9531 23:06:09.293755 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9532 23:06:09.297227 Probing TPM: done!
9533 23:06:09.300869 Connected to device vid:did:rid of 1ae0:0028:00
9534 23:06:09.311574 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9535 23:06:09.314978 Initialized TPM device CR50 revision 0
9536 23:06:09.318344 Checking cr50 for pending updates
9537 23:06:09.322170 Reading cr50 TPM mode
9538 23:06:09.331043 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9539 23:06:09.337456 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9540 23:06:09.377725 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9541 23:06:09.381380 Checking segment from ROM address 0x40100000
9542 23:06:09.384523 Checking segment from ROM address 0x4010001c
9543 23:06:09.390734 Loading segment from ROM address 0x40100000
9544 23:06:09.391180 code (compression=0)
9545 23:06:09.401170 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9546 23:06:09.407777 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9547 23:06:09.408310 it's not compressed!
9548 23:06:09.414225 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9549 23:06:09.420968 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9550 23:06:09.438113 Loading segment from ROM address 0x4010001c
9551 23:06:09.438782 Entry Point 0x80000000
9552 23:06:09.441700 Loaded segments
9553 23:06:09.445279 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9554 23:06:09.451465 Jumping to boot code at 0x80000000(0xffe64000)
9555 23:06:09.458015 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9556 23:06:09.464261 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9557 23:06:09.472495 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9558 23:06:09.476006 Checking segment from ROM address 0x40100000
9559 23:06:09.479531 Checking segment from ROM address 0x4010001c
9560 23:06:09.485756 Loading segment from ROM address 0x40100000
9561 23:06:09.486231 code (compression=1)
9562 23:06:09.492368 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9563 23:06:09.502276 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9564 23:06:09.502744 using LZMA
9565 23:06:09.510854 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9566 23:06:09.517212 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9567 23:06:09.520426 Loading segment from ROM address 0x4010001c
9568 23:06:09.520855 Entry Point 0x54601000
9569 23:06:09.523748 Loaded segments
9570 23:06:09.527537 NOTICE: MT8192 bl31_setup
9571 23:06:09.534413 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9572 23:06:09.537517 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9573 23:06:09.540996 WARNING: region 0:
9574 23:06:09.543996 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9575 23:06:09.544450 WARNING: region 1:
9576 23:06:09.550675 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9577 23:06:09.554442 WARNING: region 2:
9578 23:06:09.557559 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9579 23:06:09.560864 WARNING: region 3:
9580 23:06:09.564564 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9581 23:06:09.567331 WARNING: region 4:
9582 23:06:09.574411 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9583 23:06:09.574837 WARNING: region 5:
9584 23:06:09.577338 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9585 23:06:09.581041 WARNING: region 6:
9586 23:06:09.583864 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9587 23:06:09.587620 WARNING: region 7:
9588 23:06:09.590585 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9589 23:06:09.597029 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9590 23:06:09.600272 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9591 23:06:09.603885 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9592 23:06:09.610502 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9593 23:06:09.613928 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9594 23:06:09.620548 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9595 23:06:09.623895 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9596 23:06:09.627624 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9597 23:06:09.633909 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9598 23:06:09.637479 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9599 23:06:09.640684 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9600 23:06:09.647234 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9601 23:06:09.650479 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9602 23:06:09.656807 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9603 23:06:09.660391 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9604 23:06:09.663444 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9605 23:06:09.670499 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9606 23:06:09.673751 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9607 23:06:09.680172 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9608 23:06:09.683320 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9609 23:06:09.686889 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9610 23:06:09.693509 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9611 23:06:09.696671 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9612 23:06:09.699693 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9613 23:06:09.706572 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9614 23:06:09.710002 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9615 23:06:09.716526 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9616 23:06:09.719462 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9617 23:06:09.726243 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9618 23:06:09.729509 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9619 23:06:09.732986 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9620 23:06:09.739858 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9621 23:06:09.742971 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9622 23:06:09.746888 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9623 23:06:09.749405 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9624 23:06:09.756111 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9625 23:06:09.759162 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9626 23:06:09.763326 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9627 23:06:09.770300 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9628 23:06:09.772816 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9629 23:06:09.776491 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9630 23:06:09.779394 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9631 23:06:09.786156 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9632 23:06:09.789178 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9633 23:06:09.792740 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9634 23:06:09.796029 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9635 23:06:09.802542 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9636 23:06:09.806256 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9637 23:06:09.809013 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9638 23:06:09.815563 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9639 23:06:09.819171 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9640 23:06:09.826005 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9641 23:06:09.828722 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9642 23:06:09.835424 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9643 23:06:09.838959 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9644 23:06:09.842251 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9645 23:06:09.848712 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9646 23:06:09.852028 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9647 23:06:09.858713 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9648 23:06:09.861988 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9649 23:06:09.869632 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9650 23:06:09.871880 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9651 23:06:09.875283 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9652 23:06:09.882403 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9653 23:06:09.885399 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9654 23:06:09.892000 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9655 23:06:09.894978 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9656 23:06:09.901720 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9657 23:06:09.904963 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9658 23:06:09.911692 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9659 23:06:09.915073 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9660 23:06:09.918606 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9661 23:06:09.925096 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9662 23:06:09.928279 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9663 23:06:09.934740 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9664 23:06:09.938132 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9665 23:06:09.945106 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9666 23:06:09.948956 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9667 23:06:09.955000 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9668 23:06:09.958182 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9669 23:06:09.961094 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9670 23:06:09.967834 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9671 23:06:09.971062 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9672 23:06:09.977501 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9673 23:06:09.981006 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9674 23:06:09.987730 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9675 23:06:09.990938 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9676 23:06:09.997859 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9677 23:06:10.001226 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9678 23:06:10.004594 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9679 23:06:10.010785 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9680 23:06:10.014471 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9681 23:06:10.021557 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9682 23:06:10.024424 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9683 23:06:10.030836 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9684 23:06:10.034148 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9685 23:06:10.037518 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9686 23:06:10.044075 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9687 23:06:10.047585 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9688 23:06:10.050473 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9689 23:06:10.053838 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9690 23:06:10.061171 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9691 23:06:10.064199 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9692 23:06:10.070675 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9693 23:06:10.073657 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9694 23:06:10.077204 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9695 23:06:10.083494 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9696 23:06:10.086839 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9697 23:06:10.093933 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9698 23:06:10.096654 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9699 23:06:10.100083 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9700 23:06:10.107006 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9701 23:06:10.110344 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9702 23:06:10.116722 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9703 23:06:10.120218 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9704 23:06:10.123290 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9705 23:06:10.130190 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9706 23:06:10.133399 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9707 23:06:10.137004 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9708 23:06:10.143339 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9709 23:06:10.146432 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9710 23:06:10.150084 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9711 23:06:10.153104 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9712 23:06:10.160374 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9713 23:06:10.163073 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9714 23:06:10.166259 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9715 23:06:10.172865 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9716 23:06:10.176523 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9717 23:06:10.183153 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9718 23:06:10.186357 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9719 23:06:10.189712 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9720 23:06:10.196639 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9721 23:06:10.199559 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9722 23:06:10.206172 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9723 23:06:10.209467 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9724 23:06:10.212728 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9725 23:06:10.219763 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9726 23:06:10.222774 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9727 23:06:10.229940 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9728 23:06:10.232636 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9729 23:06:10.236225 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9730 23:06:10.242607 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9731 23:06:10.245758 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9732 23:06:10.252506 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9733 23:06:10.255628 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9734 23:06:10.258929 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9735 23:06:10.266349 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9736 23:06:10.269109 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9737 23:06:10.276033 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9738 23:06:10.279376 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9739 23:06:10.282633 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9740 23:06:10.289010 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9741 23:06:10.292230 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9742 23:06:10.295379 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9743 23:06:10.302499 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9744 23:06:10.305164 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9745 23:06:10.312314 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9746 23:06:10.315591 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9747 23:06:10.318982 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9748 23:06:10.325444 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9749 23:06:10.328867 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9750 23:06:10.335474 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9751 23:06:10.338462 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9752 23:06:10.341708 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9753 23:06:10.348410 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9754 23:06:10.351732 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9755 23:06:10.358301 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9756 23:06:10.361562 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9757 23:06:10.365575 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9758 23:06:10.371981 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9759 23:06:10.374844 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9760 23:06:10.381174 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9761 23:06:10.384599 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9762 23:06:10.388001 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9763 23:06:10.394322 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9764 23:06:10.397736 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9765 23:06:10.404587 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9766 23:06:10.407431 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9767 23:06:10.413842 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9768 23:06:10.417657 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9769 23:06:10.421061 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9770 23:06:10.427584 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9771 23:06:10.430725 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9772 23:06:10.438127 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9773 23:06:10.440329 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9774 23:06:10.444110 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9775 23:06:10.450377 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9776 23:06:10.453800 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9777 23:06:10.460192 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9778 23:06:10.464038 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9779 23:06:10.467022 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9780 23:06:10.473620 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9781 23:06:10.477563 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9782 23:06:10.483502 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9783 23:06:10.486580 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9784 23:06:10.493322 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9785 23:06:10.496857 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9786 23:06:10.499779 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9787 23:06:10.506411 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9788 23:06:10.509448 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9789 23:06:10.516654 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9790 23:06:10.519360 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9791 23:06:10.526972 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9792 23:06:10.529637 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9793 23:06:10.532936 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9794 23:06:10.539105 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9795 23:06:10.542574 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9796 23:06:10.549616 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9797 23:06:10.552733 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9798 23:06:10.559717 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9799 23:06:10.562763 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9800 23:06:10.565777 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9801 23:06:10.572520 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9802 23:06:10.575731 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9803 23:06:10.583018 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9804 23:06:10.586037 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9805 23:06:10.588963 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9806 23:06:10.595637 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9807 23:06:10.598890 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9808 23:06:10.605143 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9809 23:06:10.608902 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9810 23:06:10.615120 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9811 23:06:10.618244 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9812 23:06:10.621561 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9813 23:06:10.628299 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9814 23:06:10.631555 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9815 23:06:10.638591 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9816 23:06:10.641962 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9817 23:06:10.648055 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9818 23:06:10.651619 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9819 23:06:10.654802 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9820 23:06:10.658086 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9821 23:06:10.664650 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9822 23:06:10.668001 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9823 23:06:10.671457 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9824 23:06:10.678047 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9825 23:06:10.681096 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9826 23:06:10.684427 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9827 23:06:10.691104 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9828 23:06:10.693882 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9829 23:06:10.697278 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9830 23:06:10.704028 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9831 23:06:10.706887 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9832 23:06:10.714168 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9833 23:06:10.717483 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9834 23:06:10.720836 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9835 23:06:10.727235 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9836 23:06:10.730440 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9837 23:06:10.733368 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9838 23:06:10.740267 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9839 23:06:10.743549 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9840 23:06:10.750188 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9841 23:06:10.753353 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9842 23:06:10.756983 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9843 23:06:10.763319 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9844 23:06:10.766479 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9845 23:06:10.770085 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9846 23:06:10.776676 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9847 23:06:10.780118 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9848 23:06:10.786209 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9849 23:06:10.789925 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9850 23:06:10.793243 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9851 23:06:10.799176 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9852 23:06:10.802573 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9853 23:06:10.805839 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9854 23:06:10.812392 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9855 23:06:10.815861 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9856 23:06:10.822402 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9857 23:06:10.825996 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9858 23:06:10.829076 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9859 23:06:10.832645 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9860 23:06:10.839449 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9861 23:06:10.842456 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9862 23:06:10.846114 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9863 23:06:10.849014 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9864 23:06:10.856166 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9865 23:06:10.858977 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9866 23:06:10.862543 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9867 23:06:10.865997 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9868 23:06:10.872441 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9869 23:06:10.876035 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9870 23:06:10.879424 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9871 23:06:10.885734 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9872 23:06:10.889072 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9873 23:06:10.895739 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9874 23:06:10.898546 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9875 23:06:10.901784 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9876 23:06:10.908407 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9877 23:06:10.912295 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9878 23:06:10.918316 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9879 23:06:10.922450 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9880 23:06:10.925383 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9881 23:06:10.931854 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9882 23:06:10.934999 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9883 23:06:10.941734 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9884 23:06:10.944483 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9885 23:06:10.951109 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9886 23:06:10.954573 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9887 23:06:10.957645 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9888 23:06:10.965096 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9889 23:06:10.967990 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9890 23:06:10.974211 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9891 23:06:10.978386 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9892 23:06:10.984221 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9893 23:06:10.987546 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9894 23:06:10.990781 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9895 23:06:10.997535 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9896 23:06:11.001124 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9897 23:06:11.007751 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9898 23:06:11.010738 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9899 23:06:11.014571 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9900 23:06:11.021208 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9901 23:06:11.023996 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9902 23:06:11.030787 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9903 23:06:11.034142 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9904 23:06:11.037117 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9905 23:06:11.043860 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9906 23:06:11.046925 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9907 23:06:11.053698 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9908 23:06:11.056727 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9909 23:06:11.063179 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9910 23:06:11.066528 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9911 23:06:11.070633 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9912 23:06:11.076540 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9913 23:06:11.080009 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9914 23:06:11.086754 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9915 23:06:11.089811 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9916 23:06:11.096546 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9917 23:06:11.099450 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9918 23:06:11.102804 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9919 23:06:11.109778 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9920 23:06:11.112856 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9921 23:06:11.119793 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9922 23:06:11.123067 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9923 23:06:11.126382 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9924 23:06:11.132831 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9925 23:06:11.136054 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9926 23:06:11.142727 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9927 23:06:11.146631 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9928 23:06:11.149484 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9929 23:06:11.155736 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9930 23:06:11.159399 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9931 23:06:11.165987 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9932 23:06:11.169824 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9933 23:06:11.176109 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9934 23:06:11.179490 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9935 23:06:11.182473 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9936 23:06:11.189392 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9937 23:06:11.192534 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9938 23:06:11.199538 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9939 23:06:11.202123 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9940 23:06:11.208979 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9941 23:06:11.212209 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9942 23:06:11.215634 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9943 23:06:11.221980 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9944 23:06:11.225079 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9945 23:06:11.232035 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9946 23:06:11.235126 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9947 23:06:11.241731 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9948 23:06:11.245391 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9949 23:06:11.251693 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9950 23:06:11.254814 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9951 23:06:11.258351 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9952 23:06:11.265162 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9953 23:06:11.268036 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9954 23:06:11.275239 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9955 23:06:11.277806 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9956 23:06:11.284668 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9957 23:06:11.287622 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9958 23:06:11.291041 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9959 23:06:11.297875 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9960 23:06:11.300950 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9961 23:06:11.307519 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9962 23:06:11.310770 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9963 23:06:11.318089 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9964 23:06:11.321029 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9965 23:06:11.327243 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9966 23:06:11.330743 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9967 23:06:11.333619 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9968 23:06:11.340815 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9969 23:06:11.343639 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9970 23:06:11.350483 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9971 23:06:11.353853 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9972 23:06:11.360479 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9973 23:06:11.363543 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9974 23:06:11.370279 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9975 23:06:11.373373 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9976 23:06:11.377138 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9977 23:06:11.383374 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9978 23:06:11.386675 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9979 23:06:11.393721 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9980 23:06:11.396816 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9981 23:06:11.403394 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9982 23:06:11.406766 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9983 23:06:11.412900 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9984 23:06:11.416269 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9985 23:06:11.419598 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9986 23:06:11.426269 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9987 23:06:11.429739 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9988 23:06:11.436111 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9989 23:06:11.439983 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9990 23:06:11.445762 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9991 23:06:11.449564 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9992 23:06:11.452716 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9993 23:06:11.459173 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9994 23:06:11.462537 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9995 23:06:11.469229 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9996 23:06:11.472323 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9997 23:06:11.479428 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9998 23:06:11.482936 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9999 23:06:11.488559 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
10000 23:06:11.492089 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
10001 23:06:11.498447 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
10002 23:06:11.501753 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
10003 23:06:11.508978 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
10004 23:06:11.511685 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
10005 23:06:11.518257 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
10006 23:06:11.521529 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
10007 23:06:11.528321 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
10008 23:06:11.531865 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
10009 23:06:11.538145 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
10010 23:06:11.542141 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
10011 23:06:11.548651 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
10012 23:06:11.551453 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
10013 23:06:11.558107 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
10014 23:06:11.561108 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
10015 23:06:11.567926 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
10016 23:06:11.571077 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
10017 23:06:11.578034 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
10018 23:06:11.580768 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
10019 23:06:11.587352 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
10020 23:06:11.591111 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
10021 23:06:11.597668 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
10022 23:06:11.600811 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
10023 23:06:11.607209 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
10024 23:06:11.607521 INFO: [APUAPC] vio 0
10025 23:06:11.613982 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
10026 23:06:11.617442 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
10027 23:06:11.621195 INFO: [APUAPC] D0_APC_0: 0x400510
10028 23:06:11.624283 INFO: [APUAPC] D0_APC_1: 0x0
10029 23:06:11.627472 INFO: [APUAPC] D0_APC_2: 0x1540
10030 23:06:11.630895 INFO: [APUAPC] D0_APC_3: 0x0
10031 23:06:11.634416 INFO: [APUAPC] D1_APC_0: 0xffffffff
10032 23:06:11.637592 INFO: [APUAPC] D1_APC_1: 0xffffffff
10033 23:06:11.640943 INFO: [APUAPC] D1_APC_2: 0x3fffff
10034 23:06:11.644057 INFO: [APUAPC] D1_APC_3: 0x0
10035 23:06:11.647603 INFO: [APUAPC] D2_APC_0: 0xffffffff
10036 23:06:11.650938 INFO: [APUAPC] D2_APC_1: 0xffffffff
10037 23:06:11.653893 INFO: [APUAPC] D2_APC_2: 0x3fffff
10038 23:06:11.657635 INFO: [APUAPC] D2_APC_3: 0x0
10039 23:06:11.660825 INFO: [APUAPC] D3_APC_0: 0xffffffff
10040 23:06:11.663549 INFO: [APUAPC] D3_APC_1: 0xffffffff
10041 23:06:11.667750 INFO: [APUAPC] D3_APC_2: 0x3fffff
10042 23:06:11.670783 INFO: [APUAPC] D3_APC_3: 0x0
10043 23:06:11.674180 INFO: [APUAPC] D4_APC_0: 0xffffffff
10044 23:06:11.677240 INFO: [APUAPC] D4_APC_1: 0xffffffff
10045 23:06:11.680290 INFO: [APUAPC] D4_APC_2: 0x3fffff
10046 23:06:11.683911 INFO: [APUAPC] D4_APC_3: 0x0
10047 23:06:11.687012 INFO: [APUAPC] D5_APC_0: 0xffffffff
10048 23:06:11.690015 INFO: [APUAPC] D5_APC_1: 0xffffffff
10049 23:06:11.693569 INFO: [APUAPC] D5_APC_2: 0x3fffff
10050 23:06:11.696818 INFO: [APUAPC] D5_APC_3: 0x0
10051 23:06:11.700056 INFO: [APUAPC] D6_APC_0: 0xffffffff
10052 23:06:11.703589 INFO: [APUAPC] D6_APC_1: 0xffffffff
10053 23:06:11.706698 INFO: [APUAPC] D6_APC_2: 0x3fffff
10054 23:06:11.707130 INFO: [APUAPC] D6_APC_3: 0x0
10055 23:06:11.710178 INFO: [APUAPC] D7_APC_0: 0xffffffff
10056 23:06:11.716954 INFO: [APUAPC] D7_APC_1: 0xffffffff
10057 23:06:11.720306 INFO: [APUAPC] D7_APC_2: 0x3fffff
10058 23:06:11.720741 INFO: [APUAPC] D7_APC_3: 0x0
10059 23:06:11.723030 INFO: [APUAPC] D8_APC_0: 0xffffffff
10060 23:06:11.726567 INFO: [APUAPC] D8_APC_1: 0xffffffff
10061 23:06:11.729758 INFO: [APUAPC] D8_APC_2: 0x3fffff
10062 23:06:11.733368 INFO: [APUAPC] D8_APC_3: 0x0
10063 23:06:11.736718 INFO: [APUAPC] D9_APC_0: 0xffffffff
10064 23:06:11.740168 INFO: [APUAPC] D9_APC_1: 0xffffffff
10065 23:06:11.743073 INFO: [APUAPC] D9_APC_2: 0x3fffff
10066 23:06:11.746851 INFO: [APUAPC] D9_APC_3: 0x0
10067 23:06:11.750784 INFO: [APUAPC] D10_APC_0: 0xffffffff
10068 23:06:11.753009 INFO: [APUAPC] D10_APC_1: 0xffffffff
10069 23:06:11.756287 INFO: [APUAPC] D10_APC_2: 0x3fffff
10070 23:06:11.759645 INFO: [APUAPC] D10_APC_3: 0x0
10071 23:06:11.762576 INFO: [APUAPC] D11_APC_0: 0xffffffff
10072 23:06:11.765888 INFO: [APUAPC] D11_APC_1: 0xffffffff
10073 23:06:11.772861 INFO: [APUAPC] D11_APC_2: 0x3fffff
10074 23:06:11.773385 INFO: [APUAPC] D11_APC_3: 0x0
10075 23:06:11.776472 INFO: [APUAPC] D12_APC_0: 0xffffffff
10076 23:06:11.782354 INFO: [APUAPC] D12_APC_1: 0xffffffff
10077 23:06:11.786586 INFO: [APUAPC] D12_APC_2: 0x3fffff
10078 23:06:11.787020 INFO: [APUAPC] D12_APC_3: 0x0
10079 23:06:11.789608 INFO: [APUAPC] D13_APC_0: 0xffffffff
10080 23:06:11.795818 INFO: [APUAPC] D13_APC_1: 0xffffffff
10081 23:06:11.799223 INFO: [APUAPC] D13_APC_2: 0x3fffff
10082 23:06:11.799695 INFO: [APUAPC] D13_APC_3: 0x0
10083 23:06:11.805515 INFO: [APUAPC] D14_APC_0: 0xffffffff
10084 23:06:11.808956 INFO: [APUAPC] D14_APC_1: 0xffffffff
10085 23:06:11.812841 INFO: [APUAPC] D14_APC_2: 0x3fffff
10086 23:06:11.815818 INFO: [APUAPC] D14_APC_3: 0x0
10087 23:06:11.819177 INFO: [APUAPC] D15_APC_0: 0xffffffff
10088 23:06:11.822774 INFO: [APUAPC] D15_APC_1: 0xffffffff
10089 23:06:11.825301 INFO: [APUAPC] D15_APC_2: 0x3fffff
10090 23:06:11.828811 INFO: [APUAPC] D15_APC_3: 0x0
10091 23:06:11.829243 INFO: [APUAPC] APC_CON: 0x4
10092 23:06:11.831934 INFO: [NOCDAPC] D0_APC_0: 0x0
10093 23:06:11.835566 INFO: [NOCDAPC] D0_APC_1: 0x0
10094 23:06:11.839078 INFO: [NOCDAPC] D1_APC_0: 0x0
10095 23:06:11.842387 INFO: [NOCDAPC] D1_APC_1: 0xfff
10096 23:06:11.845451 INFO: [NOCDAPC] D2_APC_0: 0x0
10097 23:06:11.848547 INFO: [NOCDAPC] D2_APC_1: 0xfff
10098 23:06:11.852486 INFO: [NOCDAPC] D3_APC_0: 0x0
10099 23:06:11.855712 INFO: [NOCDAPC] D3_APC_1: 0xfff
10100 23:06:11.858357 INFO: [NOCDAPC] D4_APC_0: 0x0
10101 23:06:11.858790 INFO: [NOCDAPC] D4_APC_1: 0xfff
10102 23:06:11.861917 INFO: [NOCDAPC] D5_APC_0: 0x0
10103 23:06:11.865028 INFO: [NOCDAPC] D5_APC_1: 0xfff
10104 23:06:11.868315 INFO: [NOCDAPC] D6_APC_0: 0x0
10105 23:06:11.871426 INFO: [NOCDAPC] D6_APC_1: 0xfff
10106 23:06:11.875124 INFO: [NOCDAPC] D7_APC_0: 0x0
10107 23:06:11.878275 INFO: [NOCDAPC] D7_APC_1: 0xfff
10108 23:06:11.881922 INFO: [NOCDAPC] D8_APC_0: 0x0
10109 23:06:11.884879 INFO: [NOCDAPC] D8_APC_1: 0xfff
10110 23:06:11.888022 INFO: [NOCDAPC] D9_APC_0: 0x0
10111 23:06:11.891443 INFO: [NOCDAPC] D9_APC_1: 0xfff
10112 23:06:11.894647 INFO: [NOCDAPC] D10_APC_0: 0x0
10113 23:06:11.895080 INFO: [NOCDAPC] D10_APC_1: 0xfff
10114 23:06:11.898124 INFO: [NOCDAPC] D11_APC_0: 0x0
10115 23:06:11.901934 INFO: [NOCDAPC] D11_APC_1: 0xfff
10116 23:06:11.904494 INFO: [NOCDAPC] D12_APC_0: 0x0
10117 23:06:11.908193 INFO: [NOCDAPC] D12_APC_1: 0xfff
10118 23:06:11.911745 INFO: [NOCDAPC] D13_APC_0: 0x0
10119 23:06:11.914918 INFO: [NOCDAPC] D13_APC_1: 0xfff
10120 23:06:11.918596 INFO: [NOCDAPC] D14_APC_0: 0x0
10121 23:06:11.921097 INFO: [NOCDAPC] D14_APC_1: 0xfff
10122 23:06:11.924719 INFO: [NOCDAPC] D15_APC_0: 0x0
10123 23:06:11.928208 INFO: [NOCDAPC] D15_APC_1: 0xfff
10124 23:06:11.931630 INFO: [NOCDAPC] APC_CON: 0x4
10125 23:06:11.934976 INFO: [APUAPC] set_apusys_apc done
10126 23:06:11.938046 INFO: [DEVAPC] devapc_init done
10127 23:06:11.941239 INFO: GICv3 without legacy support detected.
10128 23:06:11.944544 INFO: ARM GICv3 driver initialized in EL3
10129 23:06:11.947515 INFO: Maximum SPI INTID supported: 639
10130 23:06:11.951398 INFO: BL31: Initializing runtime services
10131 23:06:11.957508 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10132 23:06:11.960545 INFO: SPM: enable CPC mode
10133 23:06:11.967577 INFO: mcdi ready for mcusys-off-idle and system suspend
10134 23:06:11.971117 INFO: BL31: Preparing for EL3 exit to normal world
10135 23:06:11.974650 INFO: Entry point address = 0x80000000
10136 23:06:11.977868 INFO: SPSR = 0x8
10137 23:06:11.982851
10138 23:06:11.983419
10139 23:06:11.983803
10140 23:06:11.985863 Starting depthcharge on Spherion...
10141 23:06:11.986432
10142 23:06:11.986816 Wipe memory regions:
10143 23:06:11.987171
10144 23:06:11.989993 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10145 23:06:11.990557 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10146 23:06:11.991029 Setting prompt string to ['asurada:']
10147 23:06:11.991491 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10148 23:06:11.992272 [0x00000040000000, 0x00000054600000)
10149 23:06:12.111350
10150 23:06:12.111917 [0x00000054660000, 0x00000080000000)
10151 23:06:12.372269
10152 23:06:12.372836 [0x000000821a7280, 0x000000ffe64000)
10153 23:06:13.117009
10154 23:06:13.117582 [0x00000100000000, 0x00000240000000)
10155 23:06:15.007047
10156 23:06:15.011198 Initializing XHCI USB controller at 0x11200000.
10157 23:06:15.992326
10158 23:06:15.992893 R8152: Initializing
10159 23:06:15.993273
10160 23:06:15.995364 Version 9 (ocp_data = 6010)
10161 23:06:15.995878
10162 23:06:15.998322 R8152: Done initializing
10163 23:06:15.998794
10164 23:06:15.999171 Adding net device
10165 23:06:16.520764
10166 23:06:16.524006 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10167 23:06:16.524573
10168 23:06:16.524949
10169 23:06:16.525296
10170 23:06:16.526187 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10172 23:06:16.627460 asurada: tftpboot 192.168.201.1 12154432/tftp-deploy-jdza9gty/kernel/image.itb 12154432/tftp-deploy-jdza9gty/kernel/cmdline
10173 23:06:16.628103 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10174 23:06:16.628574 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:20)
10175 23:06:16.633280 tftpboot 192.168.201.1 12154432/tftp-deploy-jdza9gty/kernel/image.ittp-deploy-jdza9gty/kernel/cmdline
10176 23:06:16.633769
10177 23:06:16.634115 Waiting for link
10178 23:06:16.835409
10179 23:06:16.835904 done.
10180 23:06:16.836250
10181 23:06:16.836606 MAC: f4:f5:e8:50:de:0a
10182 23:06:16.836927
10183 23:06:16.838522 Sending DHCP discover... done.
10184 23:06:16.838956
10185 23:06:16.842972 Waiting for reply... done.
10186 23:06:16.843402
10187 23:06:16.845494 Sending DHCP request... done.
10188 23:06:16.845932
10189 23:06:16.848677 Waiting for reply... done.
10190 23:06:16.849281
10191 23:06:16.849723 My ip is 192.168.201.14
10192 23:06:16.850055
10193 23:06:16.851736 The DHCP server ip is 192.168.201.1
10194 23:06:16.852174
10195 23:06:16.855534 TFTP server IP predefined by user: 192.168.201.1
10196 23:06:16.858280
10197 23:06:16.862229 Bootfile predefined by user: 12154432/tftp-deploy-jdza9gty/kernel/image.itb
10198 23:06:16.865530
10199 23:06:16.865979 Sending tftp read request... done.
10200 23:06:16.866500
10201 23:06:16.874706 Waiting for the transfer...
10202 23:06:16.875138
10203 23:06:17.173576 00000000 ################################################################
10204 23:06:17.173716
10205 23:06:17.510820 00080000 ################################################################
10206 23:06:17.510989
10207 23:06:17.864348 00100000 ################################################################
10208 23:06:17.864505
10209 23:06:18.197845 00180000 ################################################################
10210 23:06:18.197997
10211 23:06:18.512127 00200000 ################################################################
10212 23:06:18.512282
10213 23:06:18.772448 00280000 ################################################################
10214 23:06:18.772593
10215 23:06:19.010443 00300000 ################################################################
10216 23:06:19.010581
10217 23:06:19.250451 00380000 ################################################################
10218 23:06:19.250606
10219 23:06:19.495768 00400000 ################################################################
10220 23:06:19.495905
10221 23:06:19.734793 00480000 ################################################################
10222 23:06:19.734940
10223 23:06:19.977115 00500000 ################################################################
10224 23:06:19.977253
10225 23:06:20.261318 00580000 ################################################################
10226 23:06:20.261494
10227 23:06:20.610986 00600000 ################################################################
10228 23:06:20.611142
10229 23:06:20.932365 00680000 ################################################################
10230 23:06:20.932518
10231 23:06:21.255694 00700000 ################################################################
10232 23:06:21.255848
10233 23:06:21.495124 00780000 ################################################################
10234 23:06:21.495262
10235 23:06:21.757536 00800000 ################################################################
10236 23:06:21.757680
10237 23:06:22.005058 00880000 ################################################################
10238 23:06:22.005208
10239 23:06:22.234584 00900000 ################################################################
10240 23:06:22.234740
10241 23:06:22.461785 00980000 ################################################################
10242 23:06:22.461973
10243 23:06:22.693413 00a00000 ################################################################
10244 23:06:22.693611
10245 23:06:22.928554 00a80000 ################################################################
10246 23:06:22.928706
10247 23:06:23.158524 00b00000 ################################################################
10248 23:06:23.158665
10249 23:06:23.384608 00b80000 ################################################################
10250 23:06:23.384746
10251 23:06:23.619655 00c00000 ################################################################
10252 23:06:23.619817
10253 23:06:23.860716 00c80000 ################################################################
10254 23:06:23.860856
10255 23:06:24.092850 00d00000 ################################################################
10256 23:06:24.092984
10257 23:06:24.321703 00d80000 ################################################################
10258 23:06:24.321849
10259 23:06:24.553759 00e00000 ################################################################
10260 23:06:24.553903
10261 23:06:24.783556 00e80000 ################################################################
10262 23:06:24.783695
10263 23:06:25.011331 00f00000 ################################################################
10264 23:06:25.011464
10265 23:06:25.234884 00f80000 ################################################################
10266 23:06:25.235023
10267 23:06:25.468152 01000000 ################################################################
10268 23:06:25.468292
10269 23:06:25.693606 01080000 ################################################################
10270 23:06:25.693739
10271 23:06:25.925093 01100000 ################################################################
10272 23:06:25.925283
10273 23:06:26.159987 01180000 ################################################################
10274 23:06:26.160128
10275 23:06:26.426481 01200000 ################################################################
10276 23:06:26.426621
10277 23:06:26.708212 01280000 ################################################################
10278 23:06:26.708347
10279 23:06:26.951096 01300000 ################################################################
10280 23:06:26.951271
10281 23:06:27.203316 01380000 ################################################################
10282 23:06:27.203463
10283 23:06:27.436680 01400000 ################################################################
10284 23:06:27.436821
10285 23:06:27.669261 01480000 ################################################################
10286 23:06:27.669464
10287 23:06:27.921880 01500000 ################################################################
10288 23:06:27.922023
10289 23:06:28.189781 01580000 ################################################################
10290 23:06:28.189917
10291 23:06:28.456943 01600000 ################################################################
10292 23:06:28.457089
10293 23:06:28.701838 01680000 ################################################################
10294 23:06:28.701972
10295 23:06:28.940937 01700000 ################################################################
10296 23:06:28.941074
10297 23:06:29.191968 01780000 ################################################################
10298 23:06:29.192110
10299 23:06:29.432815 01800000 ################################################################
10300 23:06:29.432950
10301 23:06:29.708149 01880000 ################################################################
10302 23:06:29.708292
10303 23:06:29.994488 01900000 ################################################################
10304 23:06:29.994625
10305 23:06:30.276392 01980000 ################################################################
10306 23:06:30.276557
10307 23:06:30.566808 01a00000 ################################################################
10308 23:06:30.566982
10309 23:06:30.854800 01a80000 ################################################################
10310 23:06:30.854931
10311 23:06:31.113754 01b00000 ################################################################
10312 23:06:31.113891
10313 23:06:31.139353 01b80000 ####### done.
10314 23:06:31.139454
10315 23:06:31.142968 The bootfile was 28893034 bytes long.
10316 23:06:31.143051
10317 23:06:31.145799 Sending tftp read request... done.
10318 23:06:31.145907
10319 23:06:31.146028 Waiting for the transfer...
10320 23:06:31.146121
10321 23:06:31.149898 00000000 # done.
10322 23:06:31.149976
10323 23:06:31.155557 Command line loaded dynamically from TFTP file: 12154432/tftp-deploy-jdza9gty/kernel/cmdline
10324 23:06:31.155636
10325 23:06:31.179155 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12154432/extract-nfsrootfs-g7mgmqe7,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10326 23:06:31.179255
10327 23:06:31.179325 Loading FIT.
10328 23:06:31.179388
10329 23:06:31.182101 Image ramdisk-1 has 17799737 bytes.
10330 23:06:31.182184
10331 23:06:31.185547 Image fdt-1 has 47278 bytes.
10332 23:06:31.185636
10333 23:06:31.188616 Image kernel-1 has 11043984 bytes.
10334 23:06:31.188707
10335 23:06:31.198596 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10336 23:06:31.198685
10337 23:06:31.215181 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10338 23:06:31.215274
10339 23:06:31.221391 Choosing best match conf-1 for compat google,spherion-rev2.
10340 23:06:31.221532
10341 23:06:31.229186 Connected to device vid:did:rid of 1ae0:0028:00
10342 23:06:31.236288
10343 23:06:31.239455 tpm_get_response: command 0x17b, return code 0x0
10344 23:06:31.239558
10345 23:06:31.243590 ec_init: CrosEC protocol v3 supported (256, 248)
10346 23:06:31.247690
10347 23:06:31.250405 tpm_cleanup: add release locality here.
10348 23:06:31.250507
10349 23:06:31.250603 Shutting down all USB controllers.
10350 23:06:31.254060
10351 23:06:31.254133 Removing current net device
10352 23:06:31.254195
10353 23:06:31.260108 Exiting depthcharge with code 4 at timestamp: 48709886
10354 23:06:31.260204
10355 23:06:31.263693 LZMA decompressing kernel-1 to 0x821a6718
10356 23:06:31.263794
10357 23:06:31.266773 LZMA decompressing kernel-1 to 0x40000000
10358 23:06:32.660954
10359 23:06:32.661564 jumping to kernel
10360 23:06:32.663338 end: 2.2.4 bootloader-commands (duration 00:00:21) [common]
10361 23:06:32.663883 start: 2.2.5 auto-login-action (timeout 00:04:04) [common]
10362 23:06:32.664287 Setting prompt string to ['Linux version [0-9]']
10363 23:06:32.664657 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10364 23:06:32.665016 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10365 23:06:32.742802
10366 23:06:32.745595 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10367 23:06:32.749035 start: 2.2.5.1 login-action (timeout 00:04:04) [common]
10368 23:06:32.749132 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10369 23:06:32.749206 Setting prompt string to []
10370 23:06:32.749284 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10371 23:06:32.749363 Using line separator: #'\n'#
10372 23:06:32.749449 No login prompt set.
10373 23:06:32.749558 Parsing kernel messages
10374 23:06:32.749614 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10375 23:06:32.749716 [login-action] Waiting for messages, (timeout 00:04:04)
10376 23:06:32.768471 [ 0.000000] Linux version 6.1.64-cip10 (KernelCI@build-j31357-arm64-gcc-10-defconfig-arm64-chromebook-69txj) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Dec 1 22:47:09 UTC 2023
10377 23:06:32.771889 [ 0.000000] random: crng init done
10378 23:06:32.778745 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10379 23:06:32.781768 [ 0.000000] efi: UEFI not found.
10380 23:06:32.788421 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10381 23:06:32.798440 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10382 23:06:32.805111 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10383 23:06:32.814623 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10384 23:06:32.821297 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10385 23:06:32.827894 [ 0.000000] printk: bootconsole [mtk8250] enabled
10386 23:06:32.834412 [ 0.000000] NUMA: No NUMA configuration found
10387 23:06:32.841167 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10388 23:06:32.844465 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10389 23:06:32.847808 [ 0.000000] Zone ranges:
10390 23:06:32.854333 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10391 23:06:32.857843 [ 0.000000] DMA32 empty
10392 23:06:32.864504 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10393 23:06:32.867447 [ 0.000000] Movable zone start for each node
10394 23:06:32.870676 [ 0.000000] Early memory node ranges
10395 23:06:32.877892 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10396 23:06:32.884181 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10397 23:06:32.890954 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10398 23:06:32.897581 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10399 23:06:32.904421 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10400 23:06:32.910396 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10401 23:06:32.966685 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10402 23:06:32.973248 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10403 23:06:32.980159 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10404 23:06:32.983156 [ 0.000000] psci: probing for conduit method from DT.
10405 23:06:32.989988 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10406 23:06:32.992757 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10407 23:06:32.999417 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10408 23:06:33.003125 [ 0.000000] psci: SMC Calling Convention v1.2
10409 23:06:33.009351 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10410 23:06:33.012631 [ 0.000000] Detected VIPT I-cache on CPU0
10411 23:06:33.019121 [ 0.000000] CPU features: detected: GIC system register CPU interface
10412 23:06:33.026251 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10413 23:06:33.032755 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10414 23:06:33.039825 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10415 23:06:33.048909 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10416 23:06:33.055701 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10417 23:06:33.058752 [ 0.000000] alternatives: applying boot alternatives
10418 23:06:33.065333 [ 0.000000] Fallback order for Node 0: 0
10419 23:06:33.072336 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10420 23:06:33.075500 [ 0.000000] Policy zone: Normal
10421 23:06:33.098715 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12154432/extract-nfsrootfs-g7mgmqe7,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10422 23:06:33.108622 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10423 23:06:33.119634 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10424 23:06:33.129360 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10425 23:06:33.136546 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10426 23:06:33.138979 <6>[ 0.000000] software IO TLB: area num 8.
10427 23:06:33.195964 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10428 23:06:33.345290 <6>[ 0.000000] Memory: 7952172K/8385536K available (17984K kernel code, 4116K rwdata, 17316K rodata, 8448K init, 615K bss, 400596K reserved, 32768K cma-reserved)
10429 23:06:33.351706 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10430 23:06:33.358429 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10431 23:06:33.361688 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10432 23:06:33.368067 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10433 23:06:33.374566 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10434 23:06:33.378814 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10435 23:06:33.387586 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10436 23:06:33.394558 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10437 23:06:33.400945 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10438 23:06:33.407754 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10439 23:06:33.410942 <6>[ 0.000000] GICv3: 608 SPIs implemented
10440 23:06:33.414746 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10441 23:06:33.421067 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10442 23:06:33.424522 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10443 23:06:33.430595 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10444 23:06:33.444078 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10445 23:06:33.456920 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10446 23:06:33.464803 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10447 23:06:33.471730 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10448 23:06:33.484896 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10449 23:06:33.491557 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10450 23:06:33.498042 <6>[ 0.009154] Console: colour dummy device 80x25
10451 23:06:33.507866 <6>[ 0.013880] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10452 23:06:33.514903 <6>[ 0.024322] pid_max: default: 32768 minimum: 301
10453 23:06:33.518196 <6>[ 0.029193] LSM: Security Framework initializing
10454 23:06:33.524795 <6>[ 0.034160] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10455 23:06:33.534922 <6>[ 0.042022] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10456 23:06:33.544463 <6>[ 0.051432] cblist_init_generic: Setting adjustable number of callback queues.
10457 23:06:33.547475 <6>[ 0.058920] cblist_init_generic: Setting shift to 3 and lim to 1.
10458 23:06:33.557454 <6>[ 0.065298] cblist_init_generic: Setting adjustable number of callback queues.
10459 23:06:33.565118 <6>[ 0.072725] cblist_init_generic: Setting shift to 3 and lim to 1.
10460 23:06:33.567936 <6>[ 0.079127] rcu: Hierarchical SRCU implementation.
10461 23:06:33.574837 <6>[ 0.084173] rcu: Max phase no-delay instances is 1000.
10462 23:06:33.581319 <6>[ 0.091205] EFI services will not be available.
10463 23:06:33.584013 <6>[ 0.096161] smp: Bringing up secondary CPUs ...
10464 23:06:33.593321 <6>[ 0.101214] Detected VIPT I-cache on CPU1
10465 23:06:33.599831 <6>[ 0.101283] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10466 23:06:33.606447 <6>[ 0.101313] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10467 23:06:33.609268 <6>[ 0.101653] Detected VIPT I-cache on CPU2
10468 23:06:33.619187 <6>[ 0.101705] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10469 23:06:33.625798 <6>[ 0.101722] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10470 23:06:33.629062 <6>[ 0.101983] Detected VIPT I-cache on CPU3
10471 23:06:33.635553 <6>[ 0.102030] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10472 23:06:33.642635 <6>[ 0.102044] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10473 23:06:33.649199 <6>[ 0.102346] CPU features: detected: Spectre-v4
10474 23:06:33.651988 <6>[ 0.102353] CPU features: detected: Spectre-BHB
10475 23:06:33.655333 <6>[ 0.102358] Detected PIPT I-cache on CPU4
10476 23:06:33.661870 <6>[ 0.102415] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10477 23:06:33.668571 <6>[ 0.102433] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10478 23:06:33.675145 <6>[ 0.102727] Detected PIPT I-cache on CPU5
10479 23:06:33.681652 <6>[ 0.102789] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10480 23:06:33.688182 <6>[ 0.102806] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10481 23:06:33.691703 <6>[ 0.103090] Detected PIPT I-cache on CPU6
10482 23:06:33.701862 <6>[ 0.103154] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10483 23:06:33.708336 <6>[ 0.103170] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10484 23:06:33.711470 <6>[ 0.103469] Detected PIPT I-cache on CPU7
10485 23:06:33.718389 <6>[ 0.103533] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10486 23:06:33.724351 <6>[ 0.103550] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10487 23:06:33.727817 <6>[ 0.103599] smp: Brought up 1 node, 8 CPUs
10488 23:06:33.734385 <6>[ 0.244951] SMP: Total of 8 processors activated.
10489 23:06:33.740956 <6>[ 0.249872] CPU features: detected: 32-bit EL0 Support
10490 23:06:33.747582 <6>[ 0.255236] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10491 23:06:33.754569 <6>[ 0.264091] CPU features: detected: Common not Private translations
10492 23:06:33.760785 <6>[ 0.270606] CPU features: detected: CRC32 instructions
10493 23:06:33.767680 <6>[ 0.275958] CPU features: detected: RCpc load-acquire (LDAPR)
10494 23:06:33.770304 <6>[ 0.281918] CPU features: detected: LSE atomic instructions
10495 23:06:33.777228 <6>[ 0.287699] CPU features: detected: Privileged Access Never
10496 23:06:33.784100 <6>[ 0.293479] CPU features: detected: RAS Extension Support
10497 23:06:33.790460 <6>[ 0.299087] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10498 23:06:33.793355 <6>[ 0.306352] CPU: All CPU(s) started at EL2
10499 23:06:33.800297 <6>[ 0.310668] alternatives: applying system-wide alternatives
10500 23:06:33.810717 <6>[ 0.321375] devtmpfs: initialized
10501 23:06:33.826939 <6>[ 0.330322] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10502 23:06:33.832818 <6>[ 0.340283] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10503 23:06:33.839556 <6>[ 0.348509] pinctrl core: initialized pinctrl subsystem
10504 23:06:33.842450 <6>[ 0.355157] DMI not present or invalid.
10505 23:06:33.849263 <6>[ 0.359565] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10506 23:06:33.860041 <6>[ 0.366443] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10507 23:06:33.865657 <6>[ 0.374029] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10508 23:06:33.876023 <6>[ 0.382260] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10509 23:06:33.878835 <6>[ 0.390505] audit: initializing netlink subsys (disabled)
10510 23:06:33.888967 <5>[ 0.396197] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10511 23:06:33.895405 <6>[ 0.396898] thermal_sys: Registered thermal governor 'step_wise'
10512 23:06:33.901775 <6>[ 0.404165] thermal_sys: Registered thermal governor 'power_allocator'
10513 23:06:33.905039 <6>[ 0.410421] cpuidle: using governor menu
10514 23:06:33.911850 <6>[ 0.421382] NET: Registered PF_QIPCRTR protocol family
10515 23:06:33.918747 <6>[ 0.426864] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10516 23:06:33.926104 <6>[ 0.433967] ASID allocator initialised with 32768 entries
10517 23:06:33.928219 <6>[ 0.440523] Serial: AMBA PL011 UART driver
10518 23:06:33.938304 <4>[ 0.449277] Trying to register duplicate clock ID: 134
10519 23:06:33.995148 <6>[ 0.508849] KASLR enabled
10520 23:06:34.008902 <6>[ 0.516607] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10521 23:06:34.015789 <6>[ 0.523622] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10522 23:06:34.022134 <6>[ 0.530109] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10523 23:06:34.029609 <6>[ 0.537113] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10524 23:06:34.036061 <6>[ 0.543601] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10525 23:06:34.041781 <6>[ 0.550605] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10526 23:06:34.048524 <6>[ 0.557093] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10527 23:06:34.055637 <6>[ 0.564099] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10528 23:06:34.058426 <6>[ 0.571612] ACPI: Interpreter disabled.
10529 23:06:34.067308 <6>[ 0.578023] iommu: Default domain type: Translated
10530 23:06:34.073901 <6>[ 0.583137] iommu: DMA domain TLB invalidation policy: strict mode
10531 23:06:34.077375 <5>[ 0.589795] SCSI subsystem initialized
10532 23:06:34.083969 <6>[ 0.593962] usbcore: registered new interface driver usbfs
10533 23:06:34.090127 <6>[ 0.599694] usbcore: registered new interface driver hub
10534 23:06:34.093359 <6>[ 0.605249] usbcore: registered new device driver usb
10535 23:06:34.100498 <6>[ 0.611356] pps_core: LinuxPPS API ver. 1 registered
10536 23:06:34.111189 <6>[ 0.616551] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10537 23:06:34.113683 <6>[ 0.625901] PTP clock support registered
10538 23:06:34.116867 <6>[ 0.630144] EDAC MC: Ver: 3.0.0
10539 23:06:34.124818 <6>[ 0.635298] FPGA manager framework
10540 23:06:34.131355 <6>[ 0.638977] Advanced Linux Sound Architecture Driver Initialized.
10541 23:06:34.134508 <6>[ 0.645758] vgaarb: loaded
10542 23:06:34.140513 <6>[ 0.648920] clocksource: Switched to clocksource arch_sys_counter
10543 23:06:34.144445 <5>[ 0.655356] VFS: Disk quotas dquot_6.6.0
10544 23:06:34.151195 <6>[ 0.659541] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10545 23:06:34.153855 <6>[ 0.666733] pnp: PnP ACPI: disabled
10546 23:06:34.162723 <6>[ 0.673438] NET: Registered PF_INET protocol family
10547 23:06:34.172811 <6>[ 0.679035] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10548 23:06:34.184404 <6>[ 0.691399] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10549 23:06:34.193893 <6>[ 0.700214] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10550 23:06:34.201124 <6>[ 0.708186] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10551 23:06:34.211229 <6>[ 0.716888] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10552 23:06:34.216948 <6>[ 0.726641] TCP: Hash tables configured (established 65536 bind 65536)
10553 23:06:34.223477 <6>[ 0.733508] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10554 23:06:34.233700 <6>[ 0.740709] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10555 23:06:34.240313 <6>[ 0.748411] NET: Registered PF_UNIX/PF_LOCAL protocol family
10556 23:06:34.246663 <6>[ 0.754561] RPC: Registered named UNIX socket transport module.
10557 23:06:34.249837 <6>[ 0.760715] RPC: Registered udp transport module.
10558 23:06:34.256437 <6>[ 0.765648] RPC: Registered tcp transport module.
10559 23:06:34.262842 <6>[ 0.770581] RPC: Registered tcp NFSv4.1 backchannel transport module.
10560 23:06:34.266098 <6>[ 0.777246] PCI: CLS 0 bytes, default 64
10561 23:06:34.269882 <6>[ 0.781580] Unpacking initramfs...
10562 23:06:34.285935 <6>[ 0.793472] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10563 23:06:34.296160 <6>[ 0.802137] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10564 23:06:34.299216 <6>[ 0.810988] kvm [1]: IPA Size Limit: 40 bits
10565 23:06:34.305766 <6>[ 0.815517] kvm [1]: GICv3: no GICV resource entry
10566 23:06:34.308929 <6>[ 0.820538] kvm [1]: disabling GICv2 emulation
10567 23:06:34.315664 <6>[ 0.825227] kvm [1]: GIC system register CPU interface enabled
10568 23:06:34.322087 <6>[ 0.832945] kvm [1]: vgic interrupt IRQ18
10569 23:06:34.325744 <6>[ 0.837325] kvm [1]: VHE mode initialized successfully
10570 23:06:34.333571 <5>[ 0.843716] Initialise system trusted keyrings
10571 23:06:34.339480 <6>[ 0.848510] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10572 23:06:34.347776 <6>[ 0.858586] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10573 23:06:34.354261 <5>[ 0.865003] NFS: Registering the id_resolver key type
10574 23:06:34.357987 <5>[ 0.870298] Key type id_resolver registered
10575 23:06:34.364134 <5>[ 0.874714] Key type id_legacy registered
10576 23:06:34.370645 <6>[ 0.878994] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10577 23:06:34.377052 <6>[ 0.885918] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10578 23:06:34.384054 <6>[ 0.893643] 9p: Installing v9fs 9p2000 file system support
10579 23:06:34.420602 <5>[ 0.931309] Key type asymmetric registered
10580 23:06:34.423809 <5>[ 0.935641] Asymmetric key parser 'x509' registered
10581 23:06:34.433490 <6>[ 0.940793] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10582 23:06:34.437249 <6>[ 0.948408] io scheduler mq-deadline registered
10583 23:06:34.440317 <6>[ 0.953169] io scheduler kyber registered
10584 23:06:34.459677 <6>[ 0.970258] EINJ: ACPI disabled.
10585 23:06:34.492061 <4>[ 0.996164] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10586 23:06:34.501529 <4>[ 1.006806] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10587 23:06:34.516718 <6>[ 1.027746] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10588 23:06:34.524786 <6>[ 1.035847] printk: console [ttyS0] disabled
10589 23:06:34.553084 <6>[ 1.060501] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10590 23:06:34.560166 <6>[ 1.069984] printk: console [ttyS0] enabled
10591 23:06:34.562889 <6>[ 1.069984] printk: console [ttyS0] enabled
10592 23:06:34.569679 <6>[ 1.078881] printk: bootconsole [mtk8250] disabled
10593 23:06:34.574059 <6>[ 1.078881] printk: bootconsole [mtk8250] disabled
10594 23:06:34.579792 <6>[ 1.090127] SuperH (H)SCI(F) driver initialized
10595 23:06:34.582926 <6>[ 1.095418] msm_serial: driver initialized
10596 23:06:34.597000 <6>[ 1.104463] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10597 23:06:34.606871 <6>[ 1.113019] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10598 23:06:34.613223 <6>[ 1.121567] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10599 23:06:34.623915 <6>[ 1.130196] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10600 23:06:34.633253 <6>[ 1.138903] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10601 23:06:34.639662 <6>[ 1.147616] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10602 23:06:34.649549 <6>[ 1.156156] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10603 23:06:34.656040 <6>[ 1.164981] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10604 23:06:34.666260 <6>[ 1.173527] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10605 23:06:34.678633 <6>[ 1.189204] loop: module loaded
10606 23:06:34.684942 <6>[ 1.195191] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10607 23:06:34.708007 <4>[ 1.218609] mtk-pmic-keys: Failed to locate of_node [id: -1]
10608 23:06:34.714870 <6>[ 1.225693] megasas: 07.719.03.00-rc1
10609 23:06:34.725214 <6>[ 1.235337] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10610 23:06:34.733950 <6>[ 1.244301] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10611 23:06:34.751072 <6>[ 1.260994] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10612 23:06:34.811122 <6>[ 1.314937] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10613 23:06:35.011466 <6>[ 1.522066] Freeing initrd memory: 17380K
10614 23:06:35.021511 <6>[ 1.532413] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10615 23:06:35.033219 <6>[ 1.543534] tun: Universal TUN/TAP device driver, 1.6
10616 23:06:35.036227 <6>[ 1.549611] thunder_xcv, ver 1.0
10617 23:06:35.039473 <6>[ 1.553117] thunder_bgx, ver 1.0
10618 23:06:35.043719 <6>[ 1.556607] nicpf, ver 1.0
10619 23:06:35.053746 <6>[ 1.560642] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10620 23:06:35.057056 <6>[ 1.568118] hns3: Copyright (c) 2017 Huawei Corporation.
10621 23:06:35.063252 <6>[ 1.573705] hclge is initializing
10622 23:06:35.066302 <6>[ 1.577286] e1000: Intel(R) PRO/1000 Network Driver
10623 23:06:35.072644 <6>[ 1.582415] e1000: Copyright (c) 1999-2006 Intel Corporation.
10624 23:06:35.076517 <6>[ 1.588427] e1000e: Intel(R) PRO/1000 Network Driver
10625 23:06:35.082888 <6>[ 1.593642] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10626 23:06:35.089404 <6>[ 1.599830] igb: Intel(R) Gigabit Ethernet Network Driver
10627 23:06:35.096143 <6>[ 1.605480] igb: Copyright (c) 2007-2014 Intel Corporation.
10628 23:06:35.103249 <6>[ 1.611317] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10629 23:06:35.109613 <6>[ 1.617835] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10630 23:06:35.112951 <6>[ 1.624303] sky2: driver version 1.30
10631 23:06:35.119426 <6>[ 1.629318] VFIO - User Level meta-driver version: 0.3
10632 23:06:35.126970 <6>[ 1.637579] usbcore: registered new interface driver usb-storage
10633 23:06:35.133734 <6>[ 1.644024] usbcore: registered new device driver onboard-usb-hub
10634 23:06:35.142828 <6>[ 1.653155] mt6397-rtc mt6359-rtc: registered as rtc0
10635 23:06:35.152526 <6>[ 1.658616] mt6397-rtc mt6359-rtc: setting system clock to 2023-12-01T23:06:35 UTC (1701471995)
10636 23:06:35.155257 <6>[ 1.668199] i2c_dev: i2c /dev entries driver
10637 23:06:35.172475 <6>[ 1.680093] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10638 23:06:35.193126 <6>[ 1.704082] cpu cpu0: EM: created perf domain
10639 23:06:35.196444 <6>[ 1.708993] cpu cpu4: EM: created perf domain
10640 23:06:35.203808 <6>[ 1.714609] sdhci: Secure Digital Host Controller Interface driver
10641 23:06:35.210307 <6>[ 1.721042] sdhci: Copyright(c) Pierre Ossman
10642 23:06:35.217051 <6>[ 1.726008] Synopsys Designware Multimedia Card Interface Driver
10643 23:06:35.223873 <6>[ 1.732635] sdhci-pltfm: SDHCI platform and OF driver helper
10644 23:06:35.227340 <6>[ 1.732677] mmc0: CQHCI version 5.10
10645 23:06:35.233943 <6>[ 1.743075] ledtrig-cpu: registered to indicate activity on CPUs
10646 23:06:35.240010 <6>[ 1.750119] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10647 23:06:35.246798 <6>[ 1.757175] usbcore: registered new interface driver usbhid
10648 23:06:35.250734 <6>[ 1.762997] usbhid: USB HID core driver
10649 23:06:35.260259 <6>[ 1.767202] spi_master spi0: will run message pump with realtime priority
10650 23:06:35.306963 <6>[ 1.811286] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10651 23:06:35.326728 <6>[ 1.827155] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10652 23:06:35.329872 <6>[ 1.840774] mmc0: Command Queue Engine enabled
10653 23:06:35.337573 <6>[ 1.842322] cros-ec-spi spi0.0: Chrome EC device registered
10654 23:06:35.343861 <6>[ 1.845529] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10655 23:06:35.347016 <6>[ 1.858624] mmcblk0: mmc0:0001 DA4128 116 GiB
10656 23:06:35.359404 <6>[ 1.866792] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10657 23:06:35.366407 <6>[ 1.868186] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10658 23:06:35.372334 <6>[ 1.877304] NET: Registered PF_PACKET protocol family
10659 23:06:35.376547 <6>[ 1.883553] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10660 23:06:35.382162 <6>[ 1.887439] 9pnet: Installing 9P2000 support
10661 23:06:35.386164 <6>[ 1.893275] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10662 23:06:35.392238 <5>[ 1.897138] Key type dns_resolver registered
10663 23:06:35.399012 <6>[ 1.903042] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10664 23:06:35.402102 <6>[ 1.907287] registered taskstats version 1
10665 23:06:35.405845 <5>[ 1.917759] Loading compiled-in X.509 certificates
10666 23:06:35.435525 <4>[ 1.939491] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10667 23:06:35.445481 <4>[ 1.950191] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10668 23:06:35.452859 <3>[ 1.960719] debugfs: File 'uA_load' in directory '/' already present!
10669 23:06:35.458748 <3>[ 1.967419] debugfs: File 'min_uV' in directory '/' already present!
10670 23:06:35.465570 <3>[ 1.974092] debugfs: File 'max_uV' in directory '/' already present!
10671 23:06:35.471400 <3>[ 1.980709] debugfs: File 'constraint_flags' in directory '/' already present!
10672 23:06:35.482870 <3>[ 1.990479] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10673 23:06:35.492525 <6>[ 2.003431] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10674 23:06:35.499290 <6>[ 2.010213] xhci-mtk 11200000.usb: xHCI Host Controller
10675 23:06:35.506122 <6>[ 2.015753] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10676 23:06:35.516191 <6>[ 2.023630] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10677 23:06:35.523237 <6>[ 2.033064] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10678 23:06:35.530153 <6>[ 2.039138] xhci-mtk 11200000.usb: xHCI Host Controller
10679 23:06:35.536269 <6>[ 2.044615] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10680 23:06:35.542417 <6>[ 2.052265] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10681 23:06:35.549871 <6>[ 2.060151] hub 1-0:1.0: USB hub found
10682 23:06:35.552790 <6>[ 2.064187] hub 1-0:1.0: 1 port detected
10683 23:06:35.562569 <6>[ 2.068468] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10684 23:06:35.566132 <6>[ 2.077238] hub 2-0:1.0: USB hub found
10685 23:06:35.569484 <6>[ 2.081269] hub 2-0:1.0: 1 port detected
10686 23:06:35.577600 <6>[ 2.088717] mtk-msdc 11f70000.mmc: Got CD GPIO
10687 23:06:35.589992 <6>[ 2.097716] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10688 23:06:35.596833 <6>[ 2.105762] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10689 23:06:35.607005 <4>[ 2.113692] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10690 23:06:35.617066 <6>[ 2.123234] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10691 23:06:35.623488 <6>[ 2.131323] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10692 23:06:35.633634 <6>[ 2.139548] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10693 23:06:35.640170 <6>[ 2.147483] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10694 23:06:35.646578 <6>[ 2.155301] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10695 23:06:35.656652 <6>[ 2.163124] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10696 23:06:35.666519 <6>[ 2.173550] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10697 23:06:35.672767 <6>[ 2.181908] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10698 23:06:35.683028 <6>[ 2.190247] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10699 23:06:35.692796 <6>[ 2.198585] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10700 23:06:35.699619 <6>[ 2.206925] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10701 23:06:35.709565 <6>[ 2.215263] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10702 23:06:35.716922 <6>[ 2.223603] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10703 23:06:35.726064 <6>[ 2.231943] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10704 23:06:35.732945 <6>[ 2.240281] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10705 23:06:35.742960 <6>[ 2.248619] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10706 23:06:35.748894 <6>[ 2.256971] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10707 23:06:35.758802 <6>[ 2.265309] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10708 23:06:35.765500 <6>[ 2.273647] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10709 23:06:35.775354 <6>[ 2.281985] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10710 23:06:35.782366 <6>[ 2.290327] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10711 23:06:35.788232 <6>[ 2.299035] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10712 23:06:35.794914 <6>[ 2.306165] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10713 23:06:35.801628 <6>[ 2.312929] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10714 23:06:35.811645 <6>[ 2.319687] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10715 23:06:35.818491 <6>[ 2.326629] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10716 23:06:35.825551 <6>[ 2.333480] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10717 23:06:35.834840 <6>[ 2.342605] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10718 23:06:35.845073 <6>[ 2.351723] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10719 23:06:35.854993 <6>[ 2.361016] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10720 23:06:35.864777 <6>[ 2.370491] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10721 23:06:35.874494 <6>[ 2.379978] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10722 23:06:35.880937 <6>[ 2.389101] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10723 23:06:35.891737 <6>[ 2.398572] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10724 23:06:35.901072 <6>[ 2.407691] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10725 23:06:35.911124 <6>[ 2.416985] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10726 23:06:35.920696 <6>[ 2.427146] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10727 23:06:35.930940 <6>[ 2.438543] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10728 23:06:35.938095 <6>[ 2.448297] Trying to probe devices needed for running init ...
10729 23:06:35.978043 <6>[ 2.485234] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10730 23:06:36.133072 <6>[ 2.643180] hub 1-1:1.0: USB hub found
10731 23:06:36.135972 <6>[ 2.647701] hub 1-1:1.0: 4 ports detected
10732 23:06:36.145644 <6>[ 2.656524] hub 1-1:1.0: USB hub found
10733 23:06:36.148816 <6>[ 2.660874] hub 1-1:1.0: 4 ports detected
10734 23:06:36.257859 <6>[ 2.765546] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10735 23:06:36.284166 <6>[ 2.794819] hub 2-1:1.0: USB hub found
10736 23:06:36.287353 <6>[ 2.799316] hub 2-1:1.0: 3 ports detected
10737 23:06:36.296574 <6>[ 2.807781] hub 2-1:1.0: USB hub found
10738 23:06:36.299772 <6>[ 2.812234] hub 2-1:1.0: 3 ports detected
10739 23:06:36.473623 <6>[ 2.981169] usb 1-1.1: new high-speed USB device number 3 using xhci-mtk
10740 23:06:36.605101 <6>[ 3.115318] hub 1-1.1:1.0: USB hub found
10741 23:06:36.607858 <6>[ 3.119666] hub 1-1.1:1.0: 4 ports detected
10742 23:06:36.721552 <6>[ 3.229320] usb 1-1.4: new high-speed USB device number 4 using xhci-mtk
10743 23:06:36.854926 <6>[ 3.364961] hub 1-1.4:1.0: USB hub found
10744 23:06:36.857350 <6>[ 3.369612] hub 1-1.4:1.0: 2 ports detected
10745 23:06:36.867202 <6>[ 3.378138] hub 1-1.4:1.0: USB hub found
10746 23:06:36.870440 <6>[ 3.382694] hub 1-1.4:1.0: 2 ports detected
10747 23:06:36.934408 <6>[ 3.441227] usb 1-1.1.1: new high-speed USB device number 5 using xhci-mtk
10748 23:06:37.121441 <6>[ 3.629169] usb 1-1.1.4: new full-speed USB device number 6 using xhci-mtk
10749 23:06:37.206617 <3>[ 3.717368] usb 1-1.1.4: device descriptor read/64, error -32
10750 23:06:37.398559 <3>[ 3.909363] usb 1-1.1.4: device descriptor read/64, error -32
10751 23:06:37.593830 <6>[ 4.101203] usb 1-1.1.4: new full-speed USB device number 7 using xhci-mtk
10752 23:06:37.678651 <3>[ 4.189369] usb 1-1.1.4: device descriptor read/64, error -32
10753 23:06:37.870811 <3>[ 4.381368] usb 1-1.1.4: device descriptor read/64, error -32
10754 23:06:37.982589 <6>[ 4.493794] usb 1-1.1-port4: attempt power cycle
10755 23:06:38.065656 <6>[ 4.573230] usb 1-1.4.1: new high-speed USB device number 8 using xhci-mtk
10756 23:06:38.257288 <6>[ 4.765229] usb 1-1.4.2: new high-speed USB device number 9 using xhci-mtk
10757 23:06:38.653549 <6>[ 5.161230] usb 1-1.1.4: new full-speed USB device number 10 using xhci-mtk
10758 23:06:38.660202 <4>[ 5.168715] usb 1-1.1.4: Device not responding to setup address.
10759 23:06:38.870618 <4>[ 5.381452] usb 1-1.1.4: Device not responding to setup address.
10760 23:06:39.082126 <3>[ 5.593167] usb 1-1.1.4: device not accepting address 10, error -71
10761 23:06:39.169982 <6>[ 5.677229] usb 1-1.1.4: new full-speed USB device number 11 using xhci-mtk
10762 23:06:39.176055 <4>[ 5.684710] usb 1-1.1.4: Device not responding to setup address.
10763 23:06:39.386243 <4>[ 5.897458] usb 1-1.1.4: Device not responding to setup address.
10764 23:06:39.598041 <3>[ 6.109255] usb 1-1.1.4: device not accepting address 11, error -71
10765 23:06:39.605035 <3>[ 6.116229] usb 1-1.1-port4: unable to enumerate USB device
10766 23:06:48.218957 <6>[ 14.734192] ALSA device list:
10767 23:06:48.226116 <6>[ 14.737486] No soundcards found.
10768 23:06:48.233084 <6>[ 14.745429] Freeing unused kernel memory: 8448K
10769 23:06:48.236403 <6>[ 14.750458] Run /init as init process
10770 23:06:48.248797 Loading, please wait...
10771 23:06:48.268644 Starting version 247.3-7+deb11u2
10772 23:06:48.459214 <6>[ 14.968057] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10773 23:06:48.481233 <6>[ 14.990245] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10774 23:06:48.488322 <6>[ 14.998092] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10775 23:06:48.494592 <6>[ 15.005752] remoteproc remoteproc0: scp is available
10776 23:06:48.504671 <6>[ 15.007284] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10777 23:06:48.508046 <6>[ 15.012213] remoteproc remoteproc0: powering up scp
10778 23:06:48.518096 <6>[ 15.025923] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10779 23:06:48.521130 <6>[ 15.027274] mc: Linux media interface: v0.10
10780 23:06:48.527581 <6>[ 15.027874] usbcore: registered new interface driver r8152
10781 23:06:48.533999 <6>[ 15.034501] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10782 23:06:48.547023 <3>[ 15.055386] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10783 23:06:48.553568 <3>[ 15.063582] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10784 23:06:48.560447 <6>[ 15.065256] usbcore: registered new interface driver cdc_ether
10785 23:06:48.569743 <3>[ 15.072018] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10786 23:06:48.576348 <3>[ 15.085957] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10787 23:06:48.582975 <6>[ 15.086360] videodev: Linux video capture interface: v2.00
10788 23:06:48.589376 <6>[ 15.089993] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10789 23:06:48.596341 <4>[ 15.092038] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10790 23:06:48.605848 <3>[ 15.094044] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10791 23:06:48.612755 <3>[ 15.094048] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10792 23:06:48.622443 <3>[ 15.094052] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10793 23:06:48.630035 <3>[ 15.094055] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10794 23:06:48.636569 <4>[ 15.113343] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10795 23:06:48.646260 <3>[ 15.113408] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10796 23:06:48.653247 <6>[ 15.120789] usbcore: registered new interface driver r8153_ecm
10797 23:06:48.659837 <3>[ 15.120790] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10798 23:06:48.669546 <3>[ 15.120807] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10799 23:06:48.676217 <3>[ 15.120810] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10800 23:06:48.686137 <3>[ 15.124439] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10801 23:06:48.693055 <4>[ 15.124738] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10802 23:06:48.699011 <4>[ 15.124738] Fallback method does not support PEC.
10803 23:06:48.702182 <6>[ 15.125577] Bluetooth: Core ver 2.22
10804 23:06:48.708668 <6>[ 15.125693] NET: Registered PF_BLUETOOTH protocol family
10805 23:06:48.715262 <6>[ 15.125696] Bluetooth: HCI device and connection manager initialized
10806 23:06:48.718713 <6>[ 15.125721] Bluetooth: HCI socket layer initialized
10807 23:06:48.725181 <6>[ 15.125730] Bluetooth: L2CAP socket layer initialized
10808 23:06:48.728647 <6>[ 15.125748] Bluetooth: SCO socket layer initialized
10809 23:06:48.739453 <3>[ 15.144303] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10810 23:06:48.745560 <6>[ 15.144604] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10811 23:06:48.752083 <6>[ 15.144611] pci_bus 0000:00: root bus resource [bus 00-ff]
10812 23:06:48.758588 <6>[ 15.144616] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10813 23:06:48.769801 <6>[ 15.144619] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10814 23:06:48.775130 <6>[ 15.144649] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10815 23:06:48.781622 <6>[ 15.144663] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10816 23:06:48.785854 <6>[ 15.144741] pci 0000:00:00.0: supports D1 D2
10817 23:06:48.795488 <6>[ 15.144743] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10818 23:06:48.801995 <6>[ 15.145895] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10819 23:06:48.808511 <6>[ 15.146029] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10820 23:06:48.815548 <6>[ 15.146059] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10821 23:06:48.822116 <6>[ 15.146078] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10822 23:06:48.831584 <6>[ 15.146094] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10823 23:06:48.835390 <6>[ 15.146203] pci 0000:01:00.0: supports D1 D2
10824 23:06:48.841821 <6>[ 15.146206] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10825 23:06:48.848391 <3>[ 15.147193] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10826 23:06:48.857885 <3>[ 15.147199] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10827 23:06:48.865587 <3>[ 15.147205] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10828 23:06:48.875174 <3>[ 15.147211] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10829 23:06:48.881373 <3>[ 15.147263] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10830 23:06:48.888558 <6>[ 15.157123] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10831 23:06:48.898042 <6>[ 15.177716] usb 1-1.1.1: reset high-speed USB device number 5 using xhci-mtk
10832 23:06:48.904092 <6>[ 15.185678] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10833 23:06:48.911071 <6>[ 15.185691] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10834 23:06:48.920938 <6>[ 15.186191] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10835 23:06:48.927147 <6>[ 15.186215] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10836 23:06:48.937586 <6>[ 15.186233] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10837 23:06:48.944531 <6>[ 15.186249] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10838 23:06:48.950709 <6>[ 15.186265] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10839 23:06:48.957108 <6>[ 15.186283] pci 0000:00:00.0: PCI bridge to [bus 01]
10840 23:06:48.963715 <6>[ 15.186298] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10841 23:06:48.970294 <6>[ 15.186485] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10842 23:06:48.977015 <6>[ 15.187562] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10843 23:06:48.983734 <6>[ 15.187854] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10844 23:06:48.990353 <6>[ 15.195009] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10845 23:06:48.996900 <6>[ 15.201981] remoteproc remoteproc0: remote processor scp is now up
10846 23:06:49.006961 <6>[ 15.215081] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10847 23:06:49.017337 <6>[ 15.215480] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10848 23:06:49.027517 <6>[ 15.217582] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10849 23:06:49.033286 <6>[ 15.235462] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10850 23:06:49.043289 <4>[ 15.304795] r8152 1-1.1.1:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10851 23:06:49.052935 <3>[ 15.317724] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10852 23:06:49.059631 <4>[ 15.318914] r8152 1-1.1.1:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10853 23:06:49.069403 <5>[ 15.335513] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10854 23:06:49.076378 <6>[ 15.360330] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10855 23:06:49.083048 <6>[ 15.376377] usbcore: registered new interface driver btusb
10856 23:06:49.092501 <4>[ 15.376856] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10857 23:06:49.099132 <3>[ 15.376864] Bluetooth: hci0: Failed to load firmware file (-2)
10858 23:06:49.105792 <3>[ 15.376867] Bluetooth: hci0: Failed to set up firmware (-2)
10859 23:06:49.115594 <4>[ 15.376869] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10860 23:06:49.119138 <6>[ 15.389199] r8152 1-1.1.1:1.0 eth0: v1.12.13
10861 23:06:49.132120 <6>[ 15.392166] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10862 23:06:49.138600 <5>[ 15.393454] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10863 23:06:49.148628 <4>[ 15.393543] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10864 23:06:49.152110 <6>[ 15.393551] cfg80211: failed to load regulatory.db
10865 23:06:49.158222 <6>[ 15.401885] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10866 23:06:49.165272 <6>[ 15.406741] usbcore: registered new interface driver uvcvideo
10867 23:06:49.171705 <6>[ 15.411081] r8152 1-1.1.1:1.0 enxf4f5e850de0a: renamed from eth0
10868 23:06:49.239417 <6>[ 15.747943] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10869 23:06:49.246112 <6>[ 15.755471] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10870 23:06:49.269562 <6>[ 15.782150] mt7921e 0000:01:00.0: ASIC revision: 79610010
10871 23:06:49.375445 <4>[ 15.881056] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10872 23:06:49.383568 Begin: Loading essential drivers ... done.
10873 23:06:49.386404 Begin: Running /scripts/init-premount ... done.
10874 23:06:49.393556 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10875 23:06:49.403012 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10876 23:06:49.406528 Device /sys/class/net/enxf4f5e850de0a found
10877 23:06:49.407022 done.
10878 23:06:49.484212 IP-Config: enxf4f5e850de0a hardware address f4:f5:e8:50:de:0a mtu 1500 DHCP
10879 23:06:49.497817 <4>[ 16.002316] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10880 23:06:49.615407 <4>[ 16.120962] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10881 23:06:49.735188 <4>[ 16.240822] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10882 23:06:49.855363 <4>[ 16.360933] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10883 23:06:49.975336 <4>[ 16.480883] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10884 23:06:50.095542 <4>[ 16.600962] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10885 23:06:50.215099 <4>[ 16.720880] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10886 23:06:50.334994 <4>[ 16.840895] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10887 23:06:50.455140 <4>[ 16.960741] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10888 23:06:50.529551 <6>[ 17.041755] r8152 1-1.1.1:1.0 enxf4f5e850de0a: carrier on
10889 23:06:50.565389 <3>[ 17.077836] mt7921e 0000:01:00.0: hardware init failed
10890 23:06:50.646015 IP-Config: no response after 2 secs - giving up
10891 23:06:50.680182 IP-Config: enxf4f5e850de0a hardware address f4:f5:e8:50:de:0a mtu 1500 DHCP
10892 23:06:50.683254 IP-Config: enxf4f5e850de0a complete (dhcp from 192.168.201.1):
10893 23:06:50.690219 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10894 23:06:50.700231 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10895 23:06:50.706389 host : mt8192-asurada-spherion-r0-cbg-9
10896 23:06:50.713816 domain : lava-rack
10897 23:06:50.716068 rootserver: 192.168.201.1 rootpath:
10898 23:06:50.716633 filename :
10899 23:06:50.793360 done.
10900 23:06:50.799854 Begin: Running /scripts/nfs-bottom ... done.
10901 23:06:50.817789 Begin: Running /scripts/init-bottom ... done.
10902 23:06:52.050683 <6>[ 18.563028] NET: Registered PF_INET6 protocol family
10903 23:06:52.058331 <6>[ 18.570318] Segment Routing with IPv6
10904 23:06:52.060817 <6>[ 18.574345] In-situ OAM (IOAM) with IPv6
10905 23:06:52.187036 <30>[ 18.679939] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10906 23:06:52.190717 <30>[ 18.704308] systemd[1]: Detected architecture arm64.
10907 23:06:52.212704
10908 23:06:52.216284 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10909 23:06:52.216839
10910 23:06:52.235042 <30>[ 18.747990] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10911 23:06:53.122607 <30>[ 19.631749] systemd[1]: Queued start job for default target Graphical Interface.
10912 23:06:53.147229 <30>[ 19.659591] systemd[1]: Created slice system-getty.slice.
10913 23:06:53.153233 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10914 23:06:53.169745 <30>[ 19.682572] systemd[1]: Created slice system-modprobe.slice.
10915 23:06:53.176055 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10916 23:06:53.193839 <30>[ 19.706439] systemd[1]: Created slice system-serial\x2dgetty.slice.
10917 23:06:53.203624 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10918 23:06:53.217336 <30>[ 19.730248] systemd[1]: Created slice User and Session Slice.
10919 23:06:53.224431 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10920 23:06:53.245023 <30>[ 19.754090] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10921 23:06:53.254361 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10922 23:06:53.272699 <30>[ 19.782019] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10923 23:06:53.279363 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10924 23:06:53.303078 <30>[ 19.809372] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10925 23:06:53.310558 <30>[ 19.821536] systemd[1]: Reached target Local Encrypted Volumes.
10926 23:06:53.316291 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10927 23:06:53.333380 <30>[ 19.845798] systemd[1]: Reached target Paths.
10928 23:06:53.336357 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10929 23:06:53.352518 <30>[ 19.865216] systemd[1]: Reached target Remote File Systems.
10930 23:06:53.359240 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10931 23:06:53.376721 <30>[ 19.889475] systemd[1]: Reached target Slices.
10932 23:06:53.383245 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10933 23:06:53.396620 <30>[ 19.909219] systemd[1]: Reached target Swap.
10934 23:06:53.399693 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10935 23:06:53.420190 <30>[ 19.929694] systemd[1]: Listening on initctl Compatibility Named Pipe.
10936 23:06:53.427004 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10937 23:06:53.433156 <30>[ 19.945863] systemd[1]: Listening on Journal Audit Socket.
10938 23:06:53.440151 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10939 23:06:53.457795 <30>[ 19.970544] systemd[1]: Listening on Journal Socket (/dev/log).
10940 23:06:53.464063 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10941 23:06:53.481090 <30>[ 19.993789] systemd[1]: Listening on Journal Socket.
10942 23:06:53.487618 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10943 23:06:53.505216 <30>[ 20.014766] systemd[1]: Listening on Network Service Netlink Socket.
10944 23:06:53.511968 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10945 23:06:53.528085 <30>[ 20.040300] systemd[1]: Listening on udev Control Socket.
10946 23:06:53.534987 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10947 23:06:53.549630 <30>[ 20.061755] systemd[1]: Listening on udev Kernel Socket.
10948 23:06:53.555623 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10949 23:06:53.612661 <30>[ 20.125402] systemd[1]: Mounting Huge Pages File System...
10950 23:06:53.618864 Mounting [0;1;39mHuge Pages File System[0m...
10951 23:06:53.636426 <30>[ 20.149238] systemd[1]: Mounting POSIX Message Queue File System...
10952 23:06:53.643278 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10953 23:06:53.680889 <30>[ 20.193612] systemd[1]: Mounting Kernel Debug File System...
10954 23:06:53.687598 Mounting [0;1;39mKernel Debug File System[0m...
10955 23:06:53.703829 <30>[ 20.213583] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10956 23:06:53.717025 <30>[ 20.227092] systemd[1]: Starting Create list of static device nodes for the current kernel...
10957 23:06:53.726784 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10958 23:06:53.749023 <30>[ 20.261861] systemd[1]: Starting Load Kernel Module configfs...
10959 23:06:53.755731 Starting [0;1;39mLoad Kernel Module configfs[0m...
10960 23:06:53.777224 <30>[ 20.289691] systemd[1]: Starting Load Kernel Module drm...
10961 23:06:53.783142 Starting [0;1;39mLoad Kernel Module drm[0m...
10962 23:06:53.803902 <30>[ 20.316862] systemd[1]: Starting Load Kernel Module fuse...
10963 23:06:53.810330 Starting [0;1;39mLoad Kernel Module fuse[0m...
10964 23:06:53.853130 <30>[ 20.362414] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10965 23:06:53.860398 <6>[ 20.373199] fuse: init (API version 7.37)
10966 23:06:53.892677 <30>[ 20.405677] systemd[1]: Starting Journal Service...
10967 23:06:53.896521 Starting [0;1;39mJournal Service[0m...
10968 23:06:53.919907 <30>[ 20.432820] systemd[1]: Starting Load Kernel Modules...
10969 23:06:53.926389 Starting [0;1;39mLoad Kernel Modules[0m...
10970 23:06:53.973377 <30>[ 20.482049] systemd[1]: Starting Remount Root and Kernel File Systems...
10971 23:06:53.978767 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10972 23:06:53.997358 <30>[ 20.510158] systemd[1]: Starting Coldplug All udev Devices...
10973 23:06:54.004104 Starting [0;1;39mColdplug All udev Devices[0m...
10974 23:06:54.021681 <30>[ 20.533978] systemd[1]: Mounted Huge Pages File System.
10975 23:06:54.028049 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10976 23:06:54.045934 <30>[ 20.558089] systemd[1]: Mounted POSIX Message Queue File System.
10977 23:06:54.051466 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10978 23:06:54.069001 <30>[ 20.581860] systemd[1]: Mounted Kernel Debug File System.
10979 23:06:54.079080 <3>[ 20.585951] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10980 23:06:54.086169 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10981 23:06:54.109182 <30>[ 20.618314] systemd[1]: Finished Create list of static device nodes for the current kernel.
10982 23:06:54.119117 [[0;32m OK [<3>[ 20.627181] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10983 23:06:54.125900 0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10984 23:06:54.141583 <30>[ 20.654175] systemd[1]: modprobe@configfs.service: Succeeded.
10985 23:06:54.148730 <30>[ 20.660958] systemd[1]: Finished Load Kernel Module configfs.
10986 23:06:54.159693 <3>[ 20.666915] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10987 23:06:54.165292 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10988 23:06:54.181961 <30>[ 20.694310] systemd[1]: modprobe@drm.service: Succeeded.
10989 23:06:54.192292 <3>[ 20.700118] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10990 23:06:54.195472 <30>[ 20.700632] systemd[1]: Finished Load Kernel Module drm.
10991 23:06:54.202270 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10992 23:06:54.218197 <30>[ 20.731056] systemd[1]: modprobe@fuse.service: Succeeded.
10993 23:06:54.228896 <3>[ 20.733519] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10994 23:06:54.234779 <30>[ 20.737947] systemd[1]: Finished Load Kernel Module fuse.
10995 23:06:54.238194 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10996 23:06:54.258043 <30>[ 20.771082] systemd[1]: Finished Load Kernel Modules.
10997 23:06:54.268223 <3>[ 20.771296] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10998 23:06:54.271522 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10999 23:06:54.289882 <30>[ 20.801816] systemd[1]: Finished Remount Root and Kernel File Systems.
11000 23:06:54.300181 [[0;32m OK [<3>[ 20.809598] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11001 23:06:54.306669 0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
11002 23:06:54.334881 <3>[ 20.844262] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11003 23:06:54.348113 <30>[ 20.860934] systemd[1]: Mounting FUSE Control File System...
11004 23:06:54.354002 Mounting [0;1;39mFUSE Control File System[0m...
11005 23:06:54.367021 <3>[ 20.877155] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11006 23:06:54.380835 <30>[ 20.891120] systemd[1]: Mounting Kernel Configuration File System...
11007 23:06:54.384570 Mounting [0;1;39mKernel Configuration File System[0m...
11008 23:06:54.397387 <3>[ 20.906571] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11009 23:06:54.410895 <30>[ 20.920758] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
11010 23:06:54.421735 <30>[ 20.930004] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
11011 23:06:54.458941 <30>[ 20.970397] systemd[1]: Starting Load/Save Random Seed...
11012 23:06:54.464762 Starting [0;1;39mLoad/Save Random Seed[0m...
11013 23:06:54.479300 <30>[ 20.992547] systemd[1]: Starting Apply Kernel Variables...
11014 23:06:54.486006 Starting [0;1;39mApply Kernel Variables[0m...
11015 23:06:54.517223 <4>[ 21.020455] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
11016 23:06:54.528181 <3>[ 21.036133] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
11017 23:06:54.553358 <30>[ 21.066301] systemd[1]: Starting Create System Users...
11018 23:06:54.560066 Starting [0;1;39mCreate System Users[0m...
11019 23:06:54.574359 <30>[ 21.087096] systemd[1]: Started Journal Service.
11020 23:06:54.580558 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
11021 23:06:54.600119 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
11022 23:06:54.612655 See 'systemctl status systemd-udev-trigger.service' for details.
11023 23:06:54.629134 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
11024 23:06:54.644721 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
11025 23:06:54.661917 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
11026 23:06:54.678310 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
11027 23:06:54.694466 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
11028 23:06:54.737603 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
11029 23:06:54.754991 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
11030 23:06:54.795983 <46>[ 21.306213] systemd-journald[290]: Received client request to flush runtime journal.
11031 23:06:54.821644 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
11032 23:06:54.836617 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
11033 23:06:54.851777 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
11034 23:06:54.904457 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
11035 23:06:56.215801 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
11036 23:06:56.248508 Starting [0;1;39mCreate Volatile Files and Directories[0m...
11037 23:06:56.301301 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
11038 23:06:56.358068 Starting [0;1;39mNetwork Service[0m...
11039 23:06:56.694286 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
11040 23:06:56.717603 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
11041 23:06:56.776447 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
11042 23:06:56.996613 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
11043 23:06:57.015096 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11044 23:06:57.064805 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11045 23:06:57.081056 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
11046 23:06:57.101393 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
11047 23:06:57.117230 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11048 23:06:57.142222 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
11049 23:06:57.217002 Starting [0;1;39mNetwork Name Resolution[0m...
11050 23:06:57.246025 Starting [0;1;39mNetwork Time Synchronization[0m...
11051 23:06:57.265843 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
11052 23:06:57.323598 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
11053 23:06:57.479856 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
11054 23:06:57.500565 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
11055 23:06:57.523029 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
11056 23:06:57.536253 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
11057 23:06:57.555779 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
11058 23:06:57.689507 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
11059 23:06:57.725208 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
11060 23:06:57.755276 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
11061 23:06:57.781044 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11062 23:06:57.794482 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11063 23:06:57.816069 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11064 23:06:57.827922 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11065 23:06:57.845908 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11066 23:06:57.891661 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11067 23:06:57.971992 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
11068 23:06:58.034095 Starting [0;1;39mUser Login Management[0m...
11069 23:06:58.057141 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
11070 23:06:58.072572 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
11071 23:06:58.095927 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
11072 23:06:58.144708 Starting [0;1;39mPermit User Sessions[0m...
11073 23:06:58.261846 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11074 23:06:58.287753 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
11075 23:06:58.327777 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11076 23:06:58.349389 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11077 23:06:58.364981 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11078 23:06:58.384637 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11079 23:06:58.400423 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11080 23:06:58.415731 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11081 23:06:58.458007 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11082 23:06:58.504268 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11083 23:06:58.578274
11084 23:06:58.578428
11085 23:06:58.581280 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11086 23:06:58.581372
11087 23:06:58.584381 debian-bullseye-arm64 login: root (automatic login)
11088 23:06:58.584457
11089 23:06:58.584519
11090 23:06:58.956328 Linux debian-bullseye-arm64 6.1.64-cip10 #1 SMP PREEMPT Fri Dec 1 22:47:09 UTC 2023 aarch64
11091 23:06:58.956470
11092 23:06:58.963022 The programs included with the Debian GNU/Linux system are free software;
11093 23:06:58.969854 the exact distribution terms for each program are described in the
11094 23:06:58.972817 individual files in /usr/share/doc/*/copyright.
11095 23:06:58.972892
11096 23:06:58.979998 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11097 23:06:58.982799 permitted by applicable law.
11098 23:06:59.754632 Matched prompt #10: / #
11100 23:06:59.754923 Setting prompt string to ['/ #']
11101 23:06:59.755017 end: 2.2.5.1 login-action (duration 00:00:27) [common]
11103 23:06:59.755211 end: 2.2.5 auto-login-action (duration 00:00:27) [common]
11104 23:06:59.755299 start: 2.2.6 expect-shell-connection (timeout 00:03:37) [common]
11105 23:06:59.755375 Setting prompt string to ['/ #']
11106 23:06:59.755437 Forcing a shell prompt, looking for ['/ #']
11108 23:06:59.805632 / #
11109 23:06:59.805781 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11110 23:06:59.805864 Waiting using forced prompt support (timeout 00:02:30)
11111 23:06:59.811069
11112 23:06:59.811345 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11113 23:06:59.811436 start: 2.2.7 export-device-env (timeout 00:03:37) [common]
11115 23:06:59.911780 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12154432/extract-nfsrootfs-g7mgmqe7'
11116 23:06:59.916710 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12154432/extract-nfsrootfs-g7mgmqe7'
11118 23:07:00.017263 / # export NFS_SERVER_IP='192.168.201.1'
11119 23:07:00.022783 export NFS_SERVER_IP='192.168.201.1'
11120 23:07:00.023080 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11121 23:07:00.023181 end: 2.2 depthcharge-retry (duration 00:01:23) [common]
11122 23:07:00.023276 end: 2 depthcharge-action (duration 00:01:23) [common]
11123 23:07:00.023367 start: 3 lava-test-retry (timeout 00:07:57) [common]
11124 23:07:00.023455 start: 3.1 lava-test-shell (timeout 00:07:57) [common]
11125 23:07:00.023532 Using namespace: common
11127 23:07:00.123890 / # #
11128 23:07:00.124095 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11129 23:07:00.129323 #
11130 23:07:00.129617 Using /lava-12154432
11132 23:07:00.229962 / # export SHELL=/bin/bash
11133 23:07:00.235680 export SHELL=/bin/bash
11135 23:07:00.336236 / # . /lava-12154432/environment
11136 23:07:00.341814 . /lava-12154432/environment
11138 23:07:00.447236 / # /lava-12154432/bin/lava-test-runner /lava-12154432/0
11139 23:07:00.447419 Test shell timeout: 10s (minimum of the action and connection timeout)
11140 23:07:00.452375 /lava-12154432/bin/lava-test-runner /lava-12154432/0
11141 23:07:00.705174 + export TESTRUN_ID=0_timesync-off
11142 23:07:00.708436 + TESTRUN_ID=0_timesync-off
11143 23:07:00.711822 + cd /lava-12154432/0/tests/0_timesync-off
11144 23:07:00.714832 ++ cat uuid
11145 23:07:00.718073 + UUID=12154432_1.6.2.3.1
11146 23:07:00.718162 + set +x
11147 23:07:00.721932 <LAVA_SIGNAL_STARTRUN 0_timesync-off 12154432_1.6.2.3.1>
11148 23:07:00.722195 Received signal: <STARTRUN> 0_timesync-off 12154432_1.6.2.3.1
11149 23:07:00.722279 Starting test lava.0_timesync-off (12154432_1.6.2.3.1)
11150 23:07:00.722394 Skipping test definition patterns.
11151 23:07:00.724767 + systemctl stop systemd-timesyncd
11152 23:07:00.791516 + set +x
11153 23:07:00.794372 <LAVA_SIGNAL_ENDRUN 0_timesync-off 12154432_1.6.2.3.1>
11154 23:07:00.794641 Received signal: <ENDRUN> 0_timesync-off 12154432_1.6.2.3.1
11155 23:07:00.794729 Ending use of test pattern.
11156 23:07:00.794793 Ending test lava.0_timesync-off (12154432_1.6.2.3.1), duration 0.07
11158 23:07:00.855012 + export TESTRUN_ID=1_kselftest-rtc
11159 23:07:00.857723 + TESTRUN_ID=1_kselftest-rtc
11160 23:07:00.861021 + cd /lava-12154432/0/tests/1_kselftest-rtc
11161 23:07:00.864064 ++ cat uuid
11162 23:07:00.867788 + UUID=12154432_1.6.2.3.5
11163 23:07:00.867883 + set +x
11164 23:07:00.870976 <LAVA_SIGNAL_STARTRUN 1_kselftest-rtc 12154432_1.6.2.3.5>
11165 23:07:00.871244 Received signal: <STARTRUN> 1_kselftest-rtc 12154432_1.6.2.3.5
11166 23:07:00.871317 Starting test lava.1_kselftest-rtc (12154432_1.6.2.3.5)
11167 23:07:00.871401 Skipping test definition patterns.
11168 23:07:00.874117 + cd ./automated/linux/kselftest/
11169 23:07:00.900525 + ./kselftest.sh -c rtc -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.64-cip10/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11170 23:07:00.932667 INFO: install_deps skipped
11171 23:07:01.042023 --2023-12-01 23:07:01-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.64-cip10/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11172 23:07:01.064614 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11173 23:07:01.193939 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11174 23:07:01.322441 HTTP request sent, awaiting response... 200 OK
11175 23:07:01.325704 Length: 2967588 (2.8M) [application/octet-stream]
11176 23:07:01.328901 Saving to: 'kselftest.tar.xz'
11177 23:07:01.329010
11178 23:07:01.329105
11179 23:07:01.580057 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11180 23:07:01.837703 kselftest.tar.xz 1%[ ] 46.39K 187KB/s
11181 23:07:02.143219 kselftest.tar.xz 7%[> ] 217.50K 437KB/s
11182 23:07:02.351625 kselftest.tar.xz 28%[====> ] 822.71K 1.01MB/s
11183 23:07:02.518482 kselftest.tar.xz 69%[============> ] 1.98M 1.98MB/s
11184 23:07:02.523376 kselftest.tar.xz 100%[===================>] 2.83M 2.44MB/s in 1.2s
11185 23:07:02.523469
11186 23:07:02.788563 2023-12-01 23:07:02 (2.44 MB/s) - 'kselftest.tar.xz' saved [2967588/2967588]
11187 23:07:02.788719
11188 23:07:08.333203 skiplist:
11189 23:07:08.337038 ========================================
11190 23:07:08.339445 ========================================
11191 23:07:08.383809 rtc:rtctest
11192 23:07:08.402303 ============== Tests to run ===============
11193 23:07:08.402410 rtc:rtctest
11194 23:07:08.405745 ===========End Tests to run ===============
11195 23:07:08.410020 shardfile-rtc pass
11196 23:07:08.502287 <12>[ 35.017392] kselftest: Running tests in rtc
11197 23:07:08.511073 TAP version 13
11198 23:07:08.522413 1..1
11199 23:07:08.548583 # selftests: rtc: rtctest
11200 23:07:08.934216 # TAP version 13
11201 23:07:08.934397 # 1..8
11202 23:07:08.937282 # # Starting 8 tests from 2 test cases.
11203 23:07:08.940683 # # RUN rtc.date_read ...
11204 23:07:08.947212 # # rtctest.c:49:date_read:Current RTC date/time is 01/12/2023 23:07:08.
11205 23:07:08.950697 # # OK rtc.date_read
11206 23:07:08.953797 # ok 1 rtc.date_read
11207 23:07:08.957225 # # RUN rtc.date_read_loop ...
11208 23:07:08.967957 # # rtctest.c:88:date_read_loop:Continuously reading RTC time for 30s (with 11ms breaks after every read).
11209 23:07:19.997801 <6>[ 46.517126] vpu: disabling
11210 23:07:20.000774 <6>[ 46.520229] vproc2: disabling
11211 23:07:20.004076 <6>[ 46.523554] vproc1: disabling
11212 23:07:20.007615 <6>[ 46.527131] vaud18: disabling
11213 23:07:20.014284 <6>[ 46.530677] vsram_others: disabling
11214 23:07:20.017940 <6>[ 46.534791] va09: disabling
11215 23:07:20.021031 <6>[ 46.537983] vsram_md: disabling
11216 23:07:20.024316 <6>[ 46.541553] Vgpu: disabling
11217 23:07:38.698976 # # rtctest.c:115:date_read_loop:Performed 2594 RTC time reads.
11218 23:07:38.701841 # # OK rtc.date_read_loop
11219 23:07:38.705223 # ok 2 rtc.date_read_loop
11220 23:07:38.709002 # # RUN rtc.uie_read ...
11221 23:07:41.682417 # # OK rtc.uie_read
11222 23:07:41.686062 # ok 3 rtc.uie_read
11223 23:07:41.689399 # # RUN rtc.uie_select ...
11224 23:07:44.682504 # # OK rtc.uie_select
11225 23:07:44.685898 # ok 4 rtc.uie_select
11226 23:07:44.689500 # # RUN rtc.alarm_alm_set ...
11227 23:07:44.695568 # # rtctest.c:202:alarm_alm_set:Alarm time now set to 23:07:48.
11228 23:07:44.698676 # # rtctest.c:207:alarm_alm_set:Expected -1 (-1) != rc (-1)
11229 23:07:44.705434 # # alarm_alm_set: Test terminated by assertion
11230 23:07:44.708898 # # FAIL rtc.alarm_alm_set
11231 23:07:44.712120 # not ok 5 rtc.alarm_alm_set
11232 23:07:44.715468 # # RUN rtc.alarm_wkalm_set ...
11233 23:07:44.722035 # # rtctest.c:258:alarm_wkalm_set:Alarm time now set to 01/12/2023 23:07:48.
11234 23:07:47.684869 # # OK rtc.alarm_wkalm_set
11235 23:07:47.685394 # ok 6 rtc.alarm_wkalm_set
11236 23:07:47.691148 # # RUN rtc.alarm_alm_set_minute ...
11237 23:07:47.694252 # # rtctest.c:304:alarm_alm_set_minute:Alarm time now set to 23:08:00.
11238 23:07:47.701160 # # rtctest.c:309:alarm_alm_set_minute:Expected -1 (-1) != rc (-1)
11239 23:07:47.707624 # # alarm_alm_set_minute: Test terminated by assertion
11240 23:07:47.711581 # # FAIL rtc.alarm_alm_set_minute
11241 23:07:47.714725 # not ok 7 rtc.alarm_alm_set_minute
11242 23:07:47.717669 # # RUN rtc.alarm_wkalm_set_minute ...
11243 23:07:47.724045 # # rtctest.c:360:alarm_wkalm_set_minute:Alarm time now set to 01/12/2023 23:08:00.
11244 23:07:59.683149 # # OK rtc.alarm_wkalm_set_minute
11245 23:07:59.686360 # ok 8 rtc.alarm_wkalm_set_minute
11246 23:07:59.690111 # # FAILED: 6 / 8 tests passed.
11247 23:07:59.692890 # # Totals: pass:6 fail:2 xfail:0 xpass:0 skip:0 error:0
11248 23:07:59.696343 not ok 1 selftests: rtc: rtctest # exit=1
11249 23:08:00.264234 rtc_rtctest_rtc_date_read pass
11250 23:08:00.267609 rtc_rtctest_rtc_date_read_loop pass
11251 23:08:00.270850 rtc_rtctest_rtc_uie_read pass
11252 23:08:00.275015 rtc_rtctest_rtc_uie_select pass
11253 23:08:00.278407 rtc_rtctest_rtc_alarm_alm_set fail
11254 23:08:00.280855 rtc_rtctest_rtc_alarm_wkalm_set pass
11255 23:08:00.284152 rtc_rtctest_rtc_alarm_alm_set_minute fail
11256 23:08:00.287797 rtc_rtctest_rtc_alarm_wkalm_set_minute pass
11257 23:08:00.291079 rtc_rtctest fail
11258 23:08:00.294033 + ../../utils/send-to-lava.sh ./output/result.txt
11259 23:08:00.347174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-rtc RESULT=pass>
11260 23:08:00.347453 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-rtc RESULT=pass
11262 23:08:00.389255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass>
11263 23:08:00.389528 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass
11265 23:08:00.432467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass>
11266 23:08:00.432724 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass
11268 23:08:00.463597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass>
11269 23:08:00.463879 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass
11271 23:08:00.503794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass>
11272 23:08:00.504081 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass
11274 23:08:00.551238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail>
11275 23:08:00.551501 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail
11277 23:08:00.593864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass>
11278 23:08:00.594137 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass
11280 23:08:00.636316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail>
11281 23:08:00.636573 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail
11283 23:08:00.672970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass>
11284 23:08:00.673247 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass
11286 23:08:00.706923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest RESULT=fail>
11287 23:08:00.707021 + set +x
11288 23:08:00.707261 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest RESULT=fail
11290 23:08:00.713210 <LAVA_SIGNAL_ENDRUN 1_kselftest-rtc 12154432_1.6.2.3.5>
11291 23:08:00.713470 Received signal: <ENDRUN> 1_kselftest-rtc 12154432_1.6.2.3.5
11292 23:08:00.713546 Ending use of test pattern.
11293 23:08:00.713610 Ending test lava.1_kselftest-rtc (12154432_1.6.2.3.5), duration 59.84
11295 23:08:00.713831 ok: lava_test_shell seems to have completed
11296 23:08:00.713966 rtc_rtctest: fail
rtc_rtctest_rtc_alarm_alm_set: fail
rtc_rtctest_rtc_alarm_alm_set_minute: fail
rtc_rtctest_rtc_alarm_wkalm_set: pass
rtc_rtctest_rtc_alarm_wkalm_set_minute: pass
rtc_rtctest_rtc_date_read: pass
rtc_rtctest_rtc_date_read_loop: pass
rtc_rtctest_rtc_uie_read: pass
rtc_rtctest_rtc_uie_select: pass
shardfile-rtc: pass
11297 23:08:00.714059 end: 3.1 lava-test-shell (duration 00:01:01) [common]
11298 23:08:00.714146 end: 3 lava-test-retry (duration 00:01:01) [common]
11299 23:08:00.714231 start: 4 finalize (timeout 00:06:57) [common]
11300 23:08:00.714323 start: 4.1 power-off (timeout 00:00:30) [common]
11301 23:08:00.714476 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=off'
11302 23:08:00.792498 >> Command sent successfully.
11303 23:08:00.794995 Returned 0 in 0 seconds
11304 23:08:00.895356 end: 4.1 power-off (duration 00:00:00) [common]
11306 23:08:00.895687 start: 4.2 read-feedback (timeout 00:06:56) [common]
11308 23:08:00.896254 Listened to connection for namespace 'common' for up to 1s
11309 23:08:01.896863 Finalising connection for namespace 'common'
11310 23:08:01.897038 Disconnecting from shell: Finalise
11311 23:08:01.897122 / #
11312 23:08:01.997467 end: 4.2 read-feedback (duration 00:00:01) [common]
11313 23:08:01.997635 end: 4 finalize (duration 00:00:01) [common]
11314 23:08:01.997745 Cleaning after the job
11315 23:08:01.997854 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12154432/tftp-deploy-jdza9gty/ramdisk
11316 23:08:02.000863 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12154432/tftp-deploy-jdza9gty/kernel
11317 23:08:02.013168 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12154432/tftp-deploy-jdza9gty/dtb
11318 23:08:02.013343 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12154432/tftp-deploy-jdza9gty/nfsrootfs
11319 23:08:02.103113 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12154432/tftp-deploy-jdza9gty/modules
11320 23:08:02.110231 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12154432
11321 23:08:02.776873 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12154432
11322 23:08:02.777062 Job finished correctly