Boot log: mt8192-asurada-spherion-r0
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 27
- Kernel Errors: 38
- Errors: 0
1 23:05:19.390512 lava-dispatcher, installed at version: 2023.10
2 23:05:19.390720 start: 0 validate
3 23:05:19.390845 Start time: 2023-12-01 23:05:19.390837+00:00 (UTC)
4 23:05:19.390958 Using caching service: 'http://localhost/cache/?uri=%s'
5 23:05:19.391086 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 23:05:19.656947 Using caching service: 'http://localhost/cache/?uri=%s'
7 23:05:19.657678 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.64-cip10%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 23:05:19.928791 Using caching service: 'http://localhost/cache/?uri=%s'
9 23:05:19.929670 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.64-cip10%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 23:05:20.201091 Using caching service: 'http://localhost/cache/?uri=%s'
11 23:05:20.201848 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 23:05:20.472021 Using caching service: 'http://localhost/cache/?uri=%s'
13 23:05:20.472834 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.64-cip10%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 23:05:20.749160 validate duration: 1.36
16 23:05:20.750375 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 23:05:20.750934 start: 1.1 download-retry (timeout 00:10:00) [common]
18 23:05:20.751415 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 23:05:20.752018 Not decompressing ramdisk as can be used compressed.
20 23:05:20.752500 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/initrd.cpio.gz
21 23:05:20.752882 saving as /var/lib/lava/dispatcher/tmp/12154433/tftp-deploy-0q52bfe7/ramdisk/initrd.cpio.gz
22 23:05:20.753237 total size: 4665395 (4 MB)
23 23:05:20.758389 progress 0 % (0 MB)
24 23:05:20.766576 progress 5 % (0 MB)
25 23:05:20.773664 progress 10 % (0 MB)
26 23:05:20.778380 progress 15 % (0 MB)
27 23:05:20.781948 progress 20 % (0 MB)
28 23:05:20.784990 progress 25 % (1 MB)
29 23:05:20.787846 progress 30 % (1 MB)
30 23:05:20.790210 progress 35 % (1 MB)
31 23:05:20.792579 progress 40 % (1 MB)
32 23:05:20.794909 progress 45 % (2 MB)
33 23:05:20.796925 progress 50 % (2 MB)
34 23:05:20.798825 progress 55 % (2 MB)
35 23:05:20.800577 progress 60 % (2 MB)
36 23:05:20.802321 progress 65 % (2 MB)
37 23:05:20.803956 progress 70 % (3 MB)
38 23:05:20.805512 progress 75 % (3 MB)
39 23:05:20.807064 progress 80 % (3 MB)
40 23:05:20.808757 progress 85 % (3 MB)
41 23:05:20.810151 progress 90 % (4 MB)
42 23:05:20.811564 progress 95 % (4 MB)
43 23:05:20.812993 progress 100 % (4 MB)
44 23:05:20.813149 4 MB downloaded in 0.06 s (74.23 MB/s)
45 23:05:20.813296 end: 1.1.1 http-download (duration 00:00:00) [common]
47 23:05:20.813532 end: 1.1 download-retry (duration 00:00:00) [common]
48 23:05:20.813618 start: 1.2 download-retry (timeout 00:10:00) [common]
49 23:05:20.813701 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 23:05:20.813832 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.64-cip10/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 23:05:20.813901 saving as /var/lib/lava/dispatcher/tmp/12154433/tftp-deploy-0q52bfe7/kernel/Image
52 23:05:20.813960 total size: 49172992 (46 MB)
53 23:05:20.814021 No compression specified
54 23:05:20.815109 progress 0 % (0 MB)
55 23:05:20.827947 progress 5 % (2 MB)
56 23:05:20.840998 progress 10 % (4 MB)
57 23:05:20.853604 progress 15 % (7 MB)
58 23:05:20.866123 progress 20 % (9 MB)
59 23:05:20.878626 progress 25 % (11 MB)
60 23:05:20.891053 progress 30 % (14 MB)
61 23:05:20.903530 progress 35 % (16 MB)
62 23:05:20.915915 progress 40 % (18 MB)
63 23:05:20.928422 progress 45 % (21 MB)
64 23:05:20.941101 progress 50 % (23 MB)
65 23:05:20.953783 progress 55 % (25 MB)
66 23:05:20.966817 progress 60 % (28 MB)
67 23:05:20.979277 progress 65 % (30 MB)
68 23:05:20.991573 progress 70 % (32 MB)
69 23:05:21.004160 progress 75 % (35 MB)
70 23:05:21.016817 progress 80 % (37 MB)
71 23:05:21.029433 progress 85 % (39 MB)
72 23:05:21.042092 progress 90 % (42 MB)
73 23:05:21.054435 progress 95 % (44 MB)
74 23:05:21.066814 progress 100 % (46 MB)
75 23:05:21.067011 46 MB downloaded in 0.25 s (185.32 MB/s)
76 23:05:21.067155 end: 1.2.1 http-download (duration 00:00:00) [common]
78 23:05:21.067381 end: 1.2 download-retry (duration 00:00:00) [common]
79 23:05:21.067464 start: 1.3 download-retry (timeout 00:10:00) [common]
80 23:05:21.067548 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 23:05:21.067683 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.64-cip10/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 23:05:21.067751 saving as /var/lib/lava/dispatcher/tmp/12154433/tftp-deploy-0q52bfe7/dtb/mt8192-asurada-spherion-r0.dtb
83 23:05:21.067809 total size: 47278 (0 MB)
84 23:05:21.067867 No compression specified
85 23:05:21.069028 progress 69 % (0 MB)
86 23:05:21.069296 progress 100 % (0 MB)
87 23:05:21.069447 0 MB downloaded in 0.00 s (27.57 MB/s)
88 23:05:21.069564 end: 1.3.1 http-download (duration 00:00:00) [common]
90 23:05:21.069774 end: 1.3 download-retry (duration 00:00:00) [common]
91 23:05:21.069857 start: 1.4 download-retry (timeout 00:10:00) [common]
92 23:05:21.069934 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 23:05:21.070042 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/full.rootfs.tar.xz
94 23:05:21.070105 saving as /var/lib/lava/dispatcher/tmp/12154433/tftp-deploy-0q52bfe7/nfsrootfs/full.rootfs.tar
95 23:05:21.070173 total size: 200813988 (191 MB)
96 23:05:21.070238 Using unxz to decompress xz
97 23:05:21.074390 progress 0 % (0 MB)
98 23:05:21.598117 progress 5 % (9 MB)
99 23:05:22.107322 progress 10 % (19 MB)
100 23:05:22.683628 progress 15 % (28 MB)
101 23:05:23.053874 progress 20 % (38 MB)
102 23:05:23.375336 progress 25 % (47 MB)
103 23:05:23.959567 progress 30 % (57 MB)
104 23:05:24.501654 progress 35 % (67 MB)
105 23:05:25.089873 progress 40 % (76 MB)
106 23:05:25.641097 progress 45 % (86 MB)
107 23:05:26.218650 progress 50 % (95 MB)
108 23:05:26.841913 progress 55 % (105 MB)
109 23:05:27.497667 progress 60 % (114 MB)
110 23:05:27.613468 progress 65 % (124 MB)
111 23:05:27.750001 progress 70 % (134 MB)
112 23:05:27.844172 progress 75 % (143 MB)
113 23:05:27.914294 progress 80 % (153 MB)
114 23:05:27.982026 progress 85 % (162 MB)
115 23:05:28.081657 progress 90 % (172 MB)
116 23:05:28.356822 progress 95 % (181 MB)
117 23:05:28.922281 progress 100 % (191 MB)
118 23:05:28.927388 191 MB downloaded in 7.86 s (24.37 MB/s)
119 23:05:28.927634 end: 1.4.1 http-download (duration 00:00:08) [common]
121 23:05:28.927890 end: 1.4 download-retry (duration 00:00:08) [common]
122 23:05:28.927979 start: 1.5 download-retry (timeout 00:09:52) [common]
123 23:05:28.928064 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 23:05:28.928249 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.64-cip10/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 23:05:28.928316 saving as /var/lib/lava/dispatcher/tmp/12154433/tftp-deploy-0q52bfe7/modules/modules.tar
126 23:05:28.928376 total size: 8616152 (8 MB)
127 23:05:28.928436 Using unxz to decompress xz
128 23:05:28.932869 progress 0 % (0 MB)
129 23:05:28.954044 progress 5 % (0 MB)
130 23:05:28.977747 progress 10 % (0 MB)
131 23:05:29.001102 progress 15 % (1 MB)
132 23:05:29.023998 progress 20 % (1 MB)
133 23:05:29.047683 progress 25 % (2 MB)
134 23:05:29.073156 progress 30 % (2 MB)
135 23:05:29.099015 progress 35 % (2 MB)
136 23:05:29.121629 progress 40 % (3 MB)
137 23:05:29.145036 progress 45 % (3 MB)
138 23:05:29.170651 progress 50 % (4 MB)
139 23:05:29.194679 progress 55 % (4 MB)
140 23:05:29.219206 progress 60 % (4 MB)
141 23:05:29.244163 progress 65 % (5 MB)
142 23:05:29.271028 progress 70 % (5 MB)
143 23:05:29.294514 progress 75 % (6 MB)
144 23:05:29.321509 progress 80 % (6 MB)
145 23:05:29.347505 progress 85 % (7 MB)
146 23:05:29.372442 progress 90 % (7 MB)
147 23:05:29.401642 progress 95 % (7 MB)
148 23:05:29.428979 progress 100 % (8 MB)
149 23:05:29.435292 8 MB downloaded in 0.51 s (16.21 MB/s)
150 23:05:29.435545 end: 1.5.1 http-download (duration 00:00:01) [common]
152 23:05:29.435804 end: 1.5 download-retry (duration 00:00:01) [common]
153 23:05:29.435897 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 23:05:29.435992 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 23:05:32.975810 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12154433/extract-nfsrootfs-3jw6zot7
156 23:05:32.976010 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 23:05:32.976109 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 23:05:32.976273 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12154433/lava-overlay-iu94khry
159 23:05:32.976405 makedir: /var/lib/lava/dispatcher/tmp/12154433/lava-overlay-iu94khry/lava-12154433/bin
160 23:05:32.976682 makedir: /var/lib/lava/dispatcher/tmp/12154433/lava-overlay-iu94khry/lava-12154433/tests
161 23:05:32.976785 makedir: /var/lib/lava/dispatcher/tmp/12154433/lava-overlay-iu94khry/lava-12154433/results
162 23:05:32.976886 Creating /var/lib/lava/dispatcher/tmp/12154433/lava-overlay-iu94khry/lava-12154433/bin/lava-add-keys
163 23:05:32.977077 Creating /var/lib/lava/dispatcher/tmp/12154433/lava-overlay-iu94khry/lava-12154433/bin/lava-add-sources
164 23:05:32.977217 Creating /var/lib/lava/dispatcher/tmp/12154433/lava-overlay-iu94khry/lava-12154433/bin/lava-background-process-start
165 23:05:32.977342 Creating /var/lib/lava/dispatcher/tmp/12154433/lava-overlay-iu94khry/lava-12154433/bin/lava-background-process-stop
166 23:05:32.977466 Creating /var/lib/lava/dispatcher/tmp/12154433/lava-overlay-iu94khry/lava-12154433/bin/lava-common-functions
167 23:05:32.977588 Creating /var/lib/lava/dispatcher/tmp/12154433/lava-overlay-iu94khry/lava-12154433/bin/lava-echo-ipv4
168 23:05:32.977711 Creating /var/lib/lava/dispatcher/tmp/12154433/lava-overlay-iu94khry/lava-12154433/bin/lava-install-packages
169 23:05:32.977832 Creating /var/lib/lava/dispatcher/tmp/12154433/lava-overlay-iu94khry/lava-12154433/bin/lava-installed-packages
170 23:05:32.977952 Creating /var/lib/lava/dispatcher/tmp/12154433/lava-overlay-iu94khry/lava-12154433/bin/lava-os-build
171 23:05:32.978073 Creating /var/lib/lava/dispatcher/tmp/12154433/lava-overlay-iu94khry/lava-12154433/bin/lava-probe-channel
172 23:05:32.978194 Creating /var/lib/lava/dispatcher/tmp/12154433/lava-overlay-iu94khry/lava-12154433/bin/lava-probe-ip
173 23:05:32.978315 Creating /var/lib/lava/dispatcher/tmp/12154433/lava-overlay-iu94khry/lava-12154433/bin/lava-target-ip
174 23:05:32.978436 Creating /var/lib/lava/dispatcher/tmp/12154433/lava-overlay-iu94khry/lava-12154433/bin/lava-target-mac
175 23:05:32.978558 Creating /var/lib/lava/dispatcher/tmp/12154433/lava-overlay-iu94khry/lava-12154433/bin/lava-target-storage
176 23:05:32.978682 Creating /var/lib/lava/dispatcher/tmp/12154433/lava-overlay-iu94khry/lava-12154433/bin/lava-test-case
177 23:05:32.978806 Creating /var/lib/lava/dispatcher/tmp/12154433/lava-overlay-iu94khry/lava-12154433/bin/lava-test-event
178 23:05:32.978927 Creating /var/lib/lava/dispatcher/tmp/12154433/lava-overlay-iu94khry/lava-12154433/bin/lava-test-feedback
179 23:05:32.979047 Creating /var/lib/lava/dispatcher/tmp/12154433/lava-overlay-iu94khry/lava-12154433/bin/lava-test-raise
180 23:05:32.979167 Creating /var/lib/lava/dispatcher/tmp/12154433/lava-overlay-iu94khry/lava-12154433/bin/lava-test-reference
181 23:05:32.979289 Creating /var/lib/lava/dispatcher/tmp/12154433/lava-overlay-iu94khry/lava-12154433/bin/lava-test-runner
182 23:05:32.979409 Creating /var/lib/lava/dispatcher/tmp/12154433/lava-overlay-iu94khry/lava-12154433/bin/lava-test-set
183 23:05:32.979531 Creating /var/lib/lava/dispatcher/tmp/12154433/lava-overlay-iu94khry/lava-12154433/bin/lava-test-shell
184 23:05:32.979652 Updating /var/lib/lava/dispatcher/tmp/12154433/lava-overlay-iu94khry/lava-12154433/bin/lava-add-keys (debian)
185 23:05:32.979801 Updating /var/lib/lava/dispatcher/tmp/12154433/lava-overlay-iu94khry/lava-12154433/bin/lava-add-sources (debian)
186 23:05:32.979940 Updating /var/lib/lava/dispatcher/tmp/12154433/lava-overlay-iu94khry/lava-12154433/bin/lava-install-packages (debian)
187 23:05:32.980078 Updating /var/lib/lava/dispatcher/tmp/12154433/lava-overlay-iu94khry/lava-12154433/bin/lava-installed-packages (debian)
188 23:05:32.980212 Updating /var/lib/lava/dispatcher/tmp/12154433/lava-overlay-iu94khry/lava-12154433/bin/lava-os-build (debian)
189 23:05:32.980330 Creating /var/lib/lava/dispatcher/tmp/12154433/lava-overlay-iu94khry/lava-12154433/environment
190 23:05:32.980423 LAVA metadata
191 23:05:32.980490 - LAVA_JOB_ID=12154433
192 23:05:32.980578 - LAVA_DISPATCHER_IP=192.168.201.1
193 23:05:32.980728 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
194 23:05:32.980792 skipped lava-vland-overlay
195 23:05:32.980890 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 23:05:32.980965 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
197 23:05:32.981024 skipped lava-multinode-overlay
198 23:05:32.981093 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 23:05:32.981166 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
200 23:05:32.981235 Loading test definitions
201 23:05:32.981324 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
202 23:05:32.981400 Using /lava-12154433 at stage 0
203 23:05:32.981678 uuid=12154433_1.6.2.3.1 testdef=None
204 23:05:32.981762 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 23:05:32.981843 start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
206 23:05:32.982285 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 23:05:32.982497 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
209 23:05:32.983092 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 23:05:32.983313 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
212 23:05:32.983892 runner path: /var/lib/lava/dispatcher/tmp/12154433/lava-overlay-iu94khry/lava-12154433/0/tests/0_timesync-off test_uuid 12154433_1.6.2.3.1
213 23:05:32.984043 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 23:05:32.984260 start: 1.6.2.3.5 git-repo-action (timeout 00:09:48) [common]
216 23:05:32.984330 Using /lava-12154433 at stage 0
217 23:05:32.984424 Fetching tests from https://github.com/kernelci/test-definitions.git
218 23:05:32.984499 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/12154433/lava-overlay-iu94khry/lava-12154433/0/tests/1_kselftest-tpm2'
219 23:05:38.413430 Running '/usr/bin/git checkout kernelci.org
220 23:05:38.559346 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12154433/lava-overlay-iu94khry/lava-12154433/0/tests/1_kselftest-tpm2/automated/linux/kselftest/kselftest.yaml
221 23:05:38.560104 uuid=12154433_1.6.2.3.5 testdef=None
222 23:05:38.560258 end: 1.6.2.3.5 git-repo-action (duration 00:00:06) [common]
224 23:05:38.560517 start: 1.6.2.3.6 test-overlay (timeout 00:09:42) [common]
225 23:05:38.561296 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 23:05:38.561521 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:42) [common]
228 23:05:38.562498 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 23:05:38.562725 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:42) [common]
231 23:05:38.563627 runner path: /var/lib/lava/dispatcher/tmp/12154433/lava-overlay-iu94khry/lava-12154433/0/tests/1_kselftest-tpm2 test_uuid 12154433_1.6.2.3.5
232 23:05:38.563716 BOARD='mt8192-asurada-spherion-r0'
233 23:05:38.563778 BRANCH='cip'
234 23:05:38.563834 SKIPFILE='/dev/null'
235 23:05:38.563890 SKIP_INSTALL='True'
236 23:05:38.563948 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.64-cip10/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 23:05:38.564040 TST_CASENAME=''
238 23:05:38.564096 TST_CMDFILES='tpm2'
239 23:05:38.564238 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 23:05:38.564437 Creating lava-test-runner.conf files
242 23:05:38.564498 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12154433/lava-overlay-iu94khry/lava-12154433/0 for stage 0
243 23:05:38.564659 - 0_timesync-off
244 23:05:38.564726 - 1_kselftest-tpm2
245 23:05:38.564819 end: 1.6.2.3 test-definition (duration 00:00:06) [common]
246 23:05:38.564905 start: 1.6.2.4 compress-overlay (timeout 00:09:42) [common]
247 23:05:46.059206 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 23:05:46.059367 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:35) [common]
249 23:05:46.059456 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 23:05:46.059557 end: 1.6.2 lava-overlay (duration 00:00:13) [common]
251 23:05:46.059669 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:35) [common]
252 23:05:46.180082 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 23:05:46.180472 start: 1.6.4 extract-modules (timeout 00:09:35) [common]
254 23:05:46.180597 extracting modules file /var/lib/lava/dispatcher/tmp/12154433/tftp-deploy-0q52bfe7/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12154433/extract-nfsrootfs-3jw6zot7
255 23:05:46.407324 extracting modules file /var/lib/lava/dispatcher/tmp/12154433/tftp-deploy-0q52bfe7/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12154433/extract-overlay-ramdisk-sdrj0rof/ramdisk
256 23:05:46.639759 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 23:05:46.639930 start: 1.6.5 apply-overlay-tftp (timeout 00:09:34) [common]
258 23:05:46.640026 [common] Applying overlay to NFS
259 23:05:46.640098 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12154433/compress-overlay-8nxrus7_/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12154433/extract-nfsrootfs-3jw6zot7
260 23:05:47.564687 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 23:05:47.564856 start: 1.6.6 configure-preseed-file (timeout 00:09:33) [common]
262 23:05:47.564951 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 23:05:47.565040 start: 1.6.7 compress-ramdisk (timeout 00:09:33) [common]
264 23:05:47.565119 Building ramdisk /var/lib/lava/dispatcher/tmp/12154433/extract-overlay-ramdisk-sdrj0rof/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12154433/extract-overlay-ramdisk-sdrj0rof/ramdisk
265 23:05:47.898520 >> 119410 blocks
266 23:05:49.795422 rename /var/lib/lava/dispatcher/tmp/12154433/extract-overlay-ramdisk-sdrj0rof/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12154433/tftp-deploy-0q52bfe7/ramdisk/ramdisk.cpio.gz
267 23:05:49.795876 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 23:05:49.796056 start: 1.6.8 prepare-kernel (timeout 00:09:31) [common]
269 23:05:49.796158 start: 1.6.8.1 prepare-fit (timeout 00:09:31) [common]
270 23:05:49.796264 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12154433/tftp-deploy-0q52bfe7/kernel/Image'
271 23:06:02.465468 Returned 0 in 12 seconds
272 23:06:02.566150 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12154433/tftp-deploy-0q52bfe7/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12154433/tftp-deploy-0q52bfe7/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12154433/tftp-deploy-0q52bfe7/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12154433/tftp-deploy-0q52bfe7/kernel/image.itb
273 23:06:02.951042 output: FIT description: Kernel Image image with one or more FDT blobs
274 23:06:02.951440 output: Created: Fri Dec 1 23:06:02 2023
275 23:06:02.951514 output: Image 0 (kernel-1)
276 23:06:02.951575 output: Description:
277 23:06:02.951638 output: Created: Fri Dec 1 23:06:02 2023
278 23:06:02.951697 output: Type: Kernel Image
279 23:06:02.951754 output: Compression: lzma compressed
280 23:06:02.951810 output: Data Size: 11043984 Bytes = 10785.14 KiB = 10.53 MiB
281 23:06:02.951865 output: Architecture: AArch64
282 23:06:02.951918 output: OS: Linux
283 23:06:02.951973 output: Load Address: 0x00000000
284 23:06:02.952027 output: Entry Point: 0x00000000
285 23:06:02.952083 output: Hash algo: crc32
286 23:06:02.952137 output: Hash value: 36c84243
287 23:06:02.952196 output: Image 1 (fdt-1)
288 23:06:02.952248 output: Description: mt8192-asurada-spherion-r0
289 23:06:02.952300 output: Created: Fri Dec 1 23:06:02 2023
290 23:06:02.952352 output: Type: Flat Device Tree
291 23:06:02.952403 output: Compression: uncompressed
292 23:06:02.952454 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 23:06:02.952511 output: Architecture: AArch64
294 23:06:02.952601 output: Hash algo: crc32
295 23:06:02.952652 output: Hash value: cc4352de
296 23:06:02.952704 output: Image 2 (ramdisk-1)
297 23:06:02.952754 output: Description: unavailable
298 23:06:02.952805 output: Created: Fri Dec 1 23:06:02 2023
299 23:06:02.952855 output: Type: RAMDisk Image
300 23:06:02.952906 output: Compression: Unknown Compression
301 23:06:02.952957 output: Data Size: 17799959 Bytes = 17382.77 KiB = 16.98 MiB
302 23:06:02.953008 output: Architecture: AArch64
303 23:06:02.953059 output: OS: Linux
304 23:06:02.953118 output: Load Address: unavailable
305 23:06:02.953170 output: Entry Point: unavailable
306 23:06:02.953221 output: Hash algo: crc32
307 23:06:02.953272 output: Hash value: ada022c0
308 23:06:02.953323 output: Default Configuration: 'conf-1'
309 23:06:02.953374 output: Configuration 0 (conf-1)
310 23:06:02.953425 output: Description: mt8192-asurada-spherion-r0
311 23:06:02.953476 output: Kernel: kernel-1
312 23:06:02.953526 output: Init Ramdisk: ramdisk-1
313 23:06:02.953577 output: FDT: fdt-1
314 23:06:02.953627 output: Loadables: kernel-1
315 23:06:02.953678 output:
316 23:06:02.953884 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
317 23:06:02.953983 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
318 23:06:02.954093 end: 1.6 prepare-tftp-overlay (duration 00:00:34) [common]
319 23:06:02.954186 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:18) [common]
320 23:06:02.954266 No LXC device requested
321 23:06:02.954342 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 23:06:02.954424 start: 1.8 deploy-device-env (timeout 00:09:18) [common]
323 23:06:02.954500 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 23:06:02.954570 Checking files for TFTP limit of 4294967296 bytes.
325 23:06:02.955062 end: 1 tftp-deploy (duration 00:00:42) [common]
326 23:06:02.955176 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 23:06:02.955266 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 23:06:02.955399 substitutions:
329 23:06:02.955469 - {DTB}: 12154433/tftp-deploy-0q52bfe7/dtb/mt8192-asurada-spherion-r0.dtb
330 23:06:02.955533 - {INITRD}: 12154433/tftp-deploy-0q52bfe7/ramdisk/ramdisk.cpio.gz
331 23:06:02.955591 - {KERNEL}: 12154433/tftp-deploy-0q52bfe7/kernel/Image
332 23:06:02.955647 - {LAVA_MAC}: None
333 23:06:02.955702 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12154433/extract-nfsrootfs-3jw6zot7
334 23:06:02.955757 - {NFS_SERVER_IP}: 192.168.201.1
335 23:06:02.955811 - {PRESEED_CONFIG}: None
336 23:06:02.955864 - {PRESEED_LOCAL}: None
337 23:06:02.955916 - {RAMDISK}: 12154433/tftp-deploy-0q52bfe7/ramdisk/ramdisk.cpio.gz
338 23:06:02.955969 - {ROOT_PART}: None
339 23:06:02.956022 - {ROOT}: None
340 23:06:02.956074 - {SERVER_IP}: 192.168.201.1
341 23:06:02.956127 - {TEE}: None
342 23:06:02.956179 Parsed boot commands:
343 23:06:02.956233 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 23:06:02.956435 Parsed boot commands: tftpboot 192.168.201.1 12154433/tftp-deploy-0q52bfe7/kernel/image.itb 12154433/tftp-deploy-0q52bfe7/kernel/cmdline
345 23:06:02.956567 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 23:06:02.956657 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 23:06:02.956751 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 23:06:02.956837 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 23:06:02.956907 Not connected, no need to disconnect.
350 23:06:02.956979 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 23:06:02.957059 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 23:06:02.957170 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
353 23:06:02.961521 Setting prompt string to ['lava-test: # ']
354 23:06:02.961893 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 23:06:02.962008 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 23:06:02.962113 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 23:06:02.962200 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 23:06:02.962442 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=reboot'
359 23:06:08.109992 >> Command sent successfully.
360 23:06:08.121592 Returned 0 in 5 seconds
361 23:06:08.222995 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 23:06:08.224654 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 23:06:08.225362 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 23:06:08.226117 Setting prompt string to 'Starting depthcharge on Spherion...'
366 23:06:08.226513 Changing prompt to 'Starting depthcharge on Spherion...'
367 23:06:08.226940 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 23:06:08.228425 [Enter `^Ec?' for help]
369 23:06:08.393901
370 23:06:08.394519
371 23:06:08.394916 F0: 102B 0000
372 23:06:08.395276
373 23:06:08.397168 F3: 1001 0000 [0200]
374 23:06:08.397635
375 23:06:08.398001 F3: 1001 0000
376 23:06:08.398406
377 23:06:08.398739 F7: 102D 0000
378 23:06:08.399063
379 23:06:08.400585 F1: 0000 0000
380 23:06:08.401052
381 23:06:08.401415 V0: 0000 0000 [0001]
382 23:06:08.401773
383 23:06:08.403509 00: 0007 8000
384 23:06:08.403997
385 23:06:08.404362 01: 0000 0000
386 23:06:08.404758
387 23:06:08.407063 BP: 0C00 0209 [0000]
388 23:06:08.407535
389 23:06:08.407903 G0: 1182 0000
390 23:06:08.408261
391 23:06:08.410828 EC: 0000 0021 [4000]
392 23:06:08.411298
393 23:06:08.411664 S7: 0000 0000 [0000]
394 23:06:08.412003
395 23:06:08.414133 CC: 0000 0000 [0001]
396 23:06:08.414599
397 23:06:08.414961 T0: 0000 0040 [010F]
398 23:06:08.415333
399 23:06:08.415663 Jump to BL
400 23:06:08.417670
401 23:06:08.440477
402 23:06:08.441210
403 23:06:08.441593
404 23:06:08.447669 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 23:06:08.451098 ARM64: Exception handlers installed.
406 23:06:08.454730 ARM64: Testing exception
407 23:06:08.457971 ARM64: Done test exception
408 23:06:08.464606 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 23:06:08.474806 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 23:06:08.481708 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 23:06:08.491866 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 23:06:08.498711 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 23:06:08.508633 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 23:06:08.519066 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 23:06:08.525717 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 23:06:08.543929 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 23:06:08.547248 WDT: Last reset was cold boot
418 23:06:08.550403 SPI1(PAD0) initialized at 2873684 Hz
419 23:06:08.553881 SPI5(PAD0) initialized at 992727 Hz
420 23:06:08.557041 VBOOT: Loading verstage.
421 23:06:08.563619 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 23:06:08.566849 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 23:06:08.570961 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 23:06:08.574105 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 23:06:08.581393 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 23:06:08.587800 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 23:06:08.599022 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
428 23:06:08.599600
429 23:06:08.599969
430 23:06:08.608649 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 23:06:08.612019 ARM64: Exception handlers installed.
432 23:06:08.616033 ARM64: Testing exception
433 23:06:08.616658 ARM64: Done test exception
434 23:06:08.622065 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 23:06:08.625603 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 23:06:08.639779 Probing TPM: . done!
437 23:06:08.640345 TPM ready after 0 ms
438 23:06:08.646943 Connected to device vid:did:rid of 1ae0:0028:00
439 23:06:08.653573 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
440 23:06:08.702578 Initialized TPM device CR50 revision 0
441 23:06:08.717187 tlcl_send_startup: Startup return code is 0
442 23:06:08.717673 TPM: setup succeeded
443 23:06:08.728347 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 23:06:08.737604 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 23:06:08.746857 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 23:06:08.756011 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 23:06:08.759348 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 23:06:08.762677 in-header: 03 07 00 00 08 00 00 00
449 23:06:08.765907 in-data: aa e4 47 04 13 02 00 00
450 23:06:08.769462 Chrome EC: UHEPI supported
451 23:06:08.776033 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 23:06:08.788669 in-header: 03 95 00 00 08 00 00 00
453 23:06:08.792498 in-data: 18 20 20 08 00 00 00 00
454 23:06:08.793140 Phase 1
455 23:06:08.795859 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 23:06:08.803373 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 23:06:08.810350 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 23:06:08.810937 Recovery requested (1009000e)
459 23:06:08.821097 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 23:06:08.826712 tlcl_extend: response is 0
461 23:06:08.835815 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 23:06:08.841352 tlcl_extend: response is 0
463 23:06:08.848593 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 23:06:08.868822 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 23:06:08.875575 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 23:06:08.876151
467 23:06:08.876575
468 23:06:08.883563 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 23:06:08.886807 ARM64: Exception handlers installed.
470 23:06:08.890334 ARM64: Testing exception
471 23:06:08.893652 ARM64: Done test exception
472 23:06:08.913853 pmic_efuse_setting: Set efuses in 11 msecs
473 23:06:08.917053 pmwrap_interface_init: Select PMIF_VLD_RDY
474 23:06:08.923950 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 23:06:08.927216 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 23:06:08.933994 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 23:06:08.937261 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 23:06:08.944057 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 23:06:08.947141 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 23:06:08.950330 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 23:06:08.957166 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 23:06:08.960765 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 23:06:08.968004 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 23:06:08.970758 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 23:06:08.973989 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 23:06:08.981049 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 23:06:08.985197 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 23:06:08.992667 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 23:06:08.995923 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 23:06:09.003580 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 23:06:09.007341 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 23:06:09.014752 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 23:06:09.022238 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 23:06:09.025784 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 23:06:09.032942 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 23:06:09.036953 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 23:06:09.044066 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 23:06:09.047621 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 23:06:09.055039 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 23:06:09.058612 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 23:06:09.062645 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 23:06:09.070039 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 23:06:09.073287 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 23:06:09.076878 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 23:06:09.084313 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 23:06:09.087917 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 23:06:09.091677 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 23:06:09.099078 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 23:06:09.102717 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 23:06:09.106690 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 23:06:09.113775 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 23:06:09.117481 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 23:06:09.121259 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 23:06:09.124976 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 23:06:09.132120 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 23:06:09.135676 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 23:06:09.139545 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 23:06:09.143113 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 23:06:09.146498 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 23:06:09.154168 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 23:06:09.157311 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 23:06:09.160763 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 23:06:09.164704 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 23:06:09.168153 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 23:06:09.175650 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 23:06:09.186732 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 23:06:09.189974 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 23:06:09.197569 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 23:06:09.208189 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 23:06:09.211958 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 23:06:09.215263 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 23:06:09.218499 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 23:06:09.227288 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
534 23:06:09.230808 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 23:06:09.239173 [RTC]rtc_osc_init,62: osc32con val = 0xde70
536 23:06:09.242047 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 23:06:09.251103 [RTC]rtc_get_frequency_meter,154: input=15, output=763
538 23:06:09.260980 [RTC]rtc_get_frequency_meter,154: input=23, output=948
539 23:06:09.270316 [RTC]rtc_get_frequency_meter,154: input=19, output=857
540 23:06:09.279882 [RTC]rtc_get_frequency_meter,154: input=17, output=810
541 23:06:09.289435 [RTC]rtc_get_frequency_meter,154: input=16, output=787
542 23:06:09.299305 [RTC]rtc_get_frequency_meter,154: input=16, output=787
543 23:06:09.309040 [RTC]rtc_get_frequency_meter,154: input=17, output=809
544 23:06:09.312957 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
545 23:06:09.316070 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
546 23:06:09.319871 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 23:06:09.326992 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 23:06:09.330563 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 23:06:09.334217 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 23:06:09.337830 ADC[4]: Raw value=670432 ID=5
551 23:06:09.341452 ADC[3]: Raw value=212549 ID=1
552 23:06:09.341912 RAM Code: 0x51
553 23:06:09.345395 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 23:06:09.352760 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 23:06:09.359486 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
556 23:06:09.363180 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
557 23:06:09.367069 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 23:06:09.371021 in-header: 03 07 00 00 08 00 00 00
559 23:06:09.374435 in-data: aa e4 47 04 13 02 00 00
560 23:06:09.378199 Chrome EC: UHEPI supported
561 23:06:09.385251 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 23:06:09.388691 in-header: 03 95 00 00 08 00 00 00
563 23:06:09.392495 in-data: 18 20 20 08 00 00 00 00
564 23:06:09.396054 MRC: failed to locate region type 0.
565 23:06:09.403949 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 23:06:09.404753 DRAM-K: Running full calibration
567 23:06:09.411401 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
568 23:06:09.412048 header.status = 0x0
569 23:06:09.415144 header.version = 0x6 (expected: 0x6)
570 23:06:09.418695 header.size = 0xd00 (expected: 0xd00)
571 23:06:09.422268 header.flags = 0x0
572 23:06:09.425856 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 23:06:09.445296 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
574 23:06:09.452835 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 23:06:09.456291 dram_init: ddr_geometry: 0
576 23:06:09.456958 [EMI] MDL number = 0
577 23:06:09.459842 [EMI] Get MDL freq = 0
578 23:06:09.460304 dram_init: ddr_type: 0
579 23:06:09.463628 is_discrete_lpddr4: 1
580 23:06:09.467710 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 23:06:09.468357
582 23:06:09.469016
583 23:06:09.469402 [Bian_co] ETT version 0.0.0.1
584 23:06:09.475732 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
585 23:06:09.476193
586 23:06:09.479390 dramc_set_vcore_voltage set vcore to 650000
587 23:06:09.479898 Read voltage for 800, 4
588 23:06:09.480263 Vio18 = 0
589 23:06:09.482843 Vcore = 650000
590 23:06:09.483505 Vdram = 0
591 23:06:09.483900 Vddq = 0
592 23:06:09.486858 Vmddr = 0
593 23:06:09.487273 dram_init: config_dvfs: 1
594 23:06:09.494271 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 23:06:09.497918 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 23:06:09.501767 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
597 23:06:09.505379 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
598 23:06:09.508670 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
599 23:06:09.512619 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
600 23:06:09.516675 MEM_TYPE=3, freq_sel=18
601 23:06:09.517092 sv_algorithm_assistance_LP4_1600
602 23:06:09.523411 ============ PULL DRAM RESETB DOWN ============
603 23:06:09.527061 ========== PULL DRAM RESETB DOWN end =========
604 23:06:09.531086 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 23:06:09.534457 ===================================
606 23:06:09.538068 LPDDR4 DRAM CONFIGURATION
607 23:06:09.541721 ===================================
608 23:06:09.542136 EX_ROW_EN[0] = 0x0
609 23:06:09.545645 EX_ROW_EN[1] = 0x0
610 23:06:09.546065 LP4Y_EN = 0x0
611 23:06:09.548849 WORK_FSP = 0x0
612 23:06:09.549290 WL = 0x2
613 23:06:09.552657 RL = 0x2
614 23:06:09.553073 BL = 0x2
615 23:06:09.553400 RPST = 0x0
616 23:06:09.556272 RD_PRE = 0x0
617 23:06:09.556810 WR_PRE = 0x1
618 23:06:09.560038 WR_PST = 0x0
619 23:06:09.560451 DBI_WR = 0x0
620 23:06:09.563502 DBI_RD = 0x0
621 23:06:09.563917 OTF = 0x1
622 23:06:09.567286 ===================================
623 23:06:09.571005 ===================================
624 23:06:09.574408 ANA top config
625 23:06:09.574948 ===================================
626 23:06:09.578122 DLL_ASYNC_EN = 0
627 23:06:09.581297 ALL_SLAVE_EN = 1
628 23:06:09.584445 NEW_RANK_MODE = 1
629 23:06:09.584921 DLL_IDLE_MODE = 1
630 23:06:09.587850 LP45_APHY_COMB_EN = 1
631 23:06:09.591177 TX_ODT_DIS = 1
632 23:06:09.594829 NEW_8X_MODE = 1
633 23:06:09.597958 ===================================
634 23:06:09.601740 ===================================
635 23:06:09.605309 data_rate = 1600
636 23:06:09.605782 CKR = 1
637 23:06:09.608494 DQ_P2S_RATIO = 8
638 23:06:09.612733 ===================================
639 23:06:09.615848 CA_P2S_RATIO = 8
640 23:06:09.619483 DQ_CA_OPEN = 0
641 23:06:09.620056 DQ_SEMI_OPEN = 0
642 23:06:09.623372 CA_SEMI_OPEN = 0
643 23:06:09.626861 CA_FULL_RATE = 0
644 23:06:09.629797 DQ_CKDIV4_EN = 1
645 23:06:09.630386 CA_CKDIV4_EN = 1
646 23:06:09.633220 CA_PREDIV_EN = 0
647 23:06:09.636172 PH8_DLY = 0
648 23:06:09.640384 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 23:06:09.643624 DQ_AAMCK_DIV = 4
650 23:06:09.644114 CA_AAMCK_DIV = 4
651 23:06:09.646795 CA_ADMCK_DIV = 4
652 23:06:09.650347 DQ_TRACK_CA_EN = 0
653 23:06:09.653860 CA_PICK = 800
654 23:06:09.656859 CA_MCKIO = 800
655 23:06:09.660465 MCKIO_SEMI = 0
656 23:06:09.660970 PLL_FREQ = 3068
657 23:06:09.664375 DQ_UI_PI_RATIO = 32
658 23:06:09.667707 CA_UI_PI_RATIO = 0
659 23:06:09.671583 ===================================
660 23:06:09.675193 ===================================
661 23:06:09.679005 memory_type:LPDDR4
662 23:06:09.679587 GP_NUM : 10
663 23:06:09.682354 SRAM_EN : 1
664 23:06:09.682825 MD32_EN : 0
665 23:06:09.686017 ===================================
666 23:06:09.689683 [ANA_INIT] >>>>>>>>>>>>>>
667 23:06:09.692969 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 23:06:09.696724 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 23:06:09.699661 ===================================
670 23:06:09.700289 data_rate = 1600,PCW = 0X7600
671 23:06:09.702876 ===================================
672 23:06:09.706427 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 23:06:09.712845 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 23:06:09.719921 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 23:06:09.723021 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 23:06:09.726532 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 23:06:09.729550 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 23:06:09.733119 [ANA_INIT] flow start
679 23:06:09.733691 [ANA_INIT] PLL >>>>>>>>
680 23:06:09.736552 [ANA_INIT] PLL <<<<<<<<
681 23:06:09.739567 [ANA_INIT] MIDPI >>>>>>>>
682 23:06:09.743311 [ANA_INIT] MIDPI <<<<<<<<
683 23:06:09.743780 [ANA_INIT] DLL >>>>>>>>
684 23:06:09.746133 [ANA_INIT] flow end
685 23:06:09.749691 ============ LP4 DIFF to SE enter ============
686 23:06:09.752915 ============ LP4 DIFF to SE exit ============
687 23:06:09.756351 [ANA_INIT] <<<<<<<<<<<<<
688 23:06:09.759826 [Flow] Enable top DCM control >>>>>
689 23:06:09.763029 [Flow] Enable top DCM control <<<<<
690 23:06:09.766498 Enable DLL master slave shuffle
691 23:06:09.769777 ==============================================================
692 23:06:09.773020 Gating Mode config
693 23:06:09.779612 ==============================================================
694 23:06:09.780118 Config description:
695 23:06:09.789786 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 23:06:09.796319 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 23:06:09.803157 SELPH_MODE 0: By rank 1: By Phase
698 23:06:09.806423 ==============================================================
699 23:06:09.809613 GAT_TRACK_EN = 1
700 23:06:09.813070 RX_GATING_MODE = 2
701 23:06:09.816754 RX_GATING_TRACK_MODE = 2
702 23:06:09.820142 SELPH_MODE = 1
703 23:06:09.823167 PICG_EARLY_EN = 1
704 23:06:09.826462 VALID_LAT_VALUE = 1
705 23:06:09.829580 ==============================================================
706 23:06:09.832837 Enter into Gating configuration >>>>
707 23:06:09.836037 Exit from Gating configuration <<<<
708 23:06:09.839794 Enter into DVFS_PRE_config >>>>>
709 23:06:09.852982 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 23:06:09.856018 Exit from DVFS_PRE_config <<<<<
711 23:06:09.859302 Enter into PICG configuration >>>>
712 23:06:09.859846 Exit from PICG configuration <<<<
713 23:06:09.862783 [RX_INPUT] configuration >>>>>
714 23:06:09.866017 [RX_INPUT] configuration <<<<<
715 23:06:09.872839 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 23:06:09.875997 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 23:06:09.882506 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 23:06:09.889394 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 23:06:09.895942 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 23:06:09.902297 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 23:06:09.905805 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 23:06:09.908947 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 23:06:09.912346 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 23:06:09.919007 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 23:06:09.922636 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 23:06:09.926115 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 23:06:09.929249 ===================================
728 23:06:09.932354 LPDDR4 DRAM CONFIGURATION
729 23:06:09.935653 ===================================
730 23:06:09.938987 EX_ROW_EN[0] = 0x0
731 23:06:09.939635 EX_ROW_EN[1] = 0x0
732 23:06:09.942239 LP4Y_EN = 0x0
733 23:06:09.942779 WORK_FSP = 0x0
734 23:06:09.945457 WL = 0x2
735 23:06:09.946046 RL = 0x2
736 23:06:09.948819 BL = 0x2
737 23:06:09.949386 RPST = 0x0
738 23:06:09.952466 RD_PRE = 0x0
739 23:06:09.953127 WR_PRE = 0x1
740 23:06:09.955738 WR_PST = 0x0
741 23:06:09.956304 DBI_WR = 0x0
742 23:06:09.958849 DBI_RD = 0x0
743 23:06:09.959403 OTF = 0x1
744 23:06:09.962053 ===================================
745 23:06:09.972109 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 23:06:09.972625 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 23:06:09.975798 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 23:06:09.979107 ===================================
749 23:06:09.982465 LPDDR4 DRAM CONFIGURATION
750 23:06:09.985942 ===================================
751 23:06:09.986486 EX_ROW_EN[0] = 0x10
752 23:06:09.988973 EX_ROW_EN[1] = 0x0
753 23:06:09.992428 LP4Y_EN = 0x0
754 23:06:09.992941 WORK_FSP = 0x0
755 23:06:09.995499 WL = 0x2
756 23:06:09.995966 RL = 0x2
757 23:06:09.999206 BL = 0x2
758 23:06:09.999772 RPST = 0x0
759 23:06:10.002351 RD_PRE = 0x0
760 23:06:10.002907 WR_PRE = 0x1
761 23:06:10.005650 WR_PST = 0x0
762 23:06:10.006134 DBI_WR = 0x0
763 23:06:10.009207 DBI_RD = 0x0
764 23:06:10.009677 OTF = 0x1
765 23:06:10.012739 ===================================
766 23:06:10.018850 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 23:06:10.023112 nWR fixed to 40
768 23:06:10.026506 [ModeRegInit_LP4] CH0 RK0
769 23:06:10.027046 [ModeRegInit_LP4] CH0 RK1
770 23:06:10.030172 [ModeRegInit_LP4] CH1 RK0
771 23:06:10.033106 [ModeRegInit_LP4] CH1 RK1
772 23:06:10.033577 match AC timing 12
773 23:06:10.039669 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
774 23:06:10.043097 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 23:06:10.046644 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 23:06:10.053230 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 23:06:10.056488 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 23:06:10.057080 [EMI DOE] emi_dcm 0
779 23:06:10.063011 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 23:06:10.063565 ==
781 23:06:10.066321 Dram Type= 6, Freq= 0, CH_0, rank 0
782 23:06:10.070349 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
783 23:06:10.070924 ==
784 23:06:10.076413 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 23:06:10.083062 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 23:06:10.090669 [CA 0] Center 37 (7~68) winsize 62
787 23:06:10.093897 [CA 1] Center 37 (7~68) winsize 62
788 23:06:10.097688 [CA 2] Center 35 (5~66) winsize 62
789 23:06:10.100345 [CA 3] Center 35 (5~66) winsize 62
790 23:06:10.104187 [CA 4] Center 34 (4~65) winsize 62
791 23:06:10.107396 [CA 5] Center 33 (3~64) winsize 62
792 23:06:10.107955
793 23:06:10.110548 [CmdBusTrainingLP45] Vref(ca) range 1: 32
794 23:06:10.111038
795 23:06:10.114255 [CATrainingPosCal] consider 1 rank data
796 23:06:10.117369 u2DelayCellTimex100 = 270/100 ps
797 23:06:10.120598 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
798 23:06:10.123926 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
799 23:06:10.130591 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
800 23:06:10.133948 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
801 23:06:10.137156 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
802 23:06:10.140562 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
803 23:06:10.141128
804 23:06:10.143610 CA PerBit enable=1, Macro0, CA PI delay=33
805 23:06:10.144076
806 23:06:10.146790 [CBTSetCACLKResult] CA Dly = 33
807 23:06:10.147257 CS Dly: 6 (0~37)
808 23:06:10.150217 ==
809 23:06:10.153553 Dram Type= 6, Freq= 0, CH_0, rank 1
810 23:06:10.156981 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
811 23:06:10.157452 ==
812 23:06:10.160220 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 23:06:10.166763 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 23:06:10.176667 [CA 0] Center 37 (7~68) winsize 62
815 23:06:10.180126 [CA 1] Center 37 (7~68) winsize 62
816 23:06:10.183430 [CA 2] Center 35 (4~66) winsize 63
817 23:06:10.186648 [CA 3] Center 35 (4~66) winsize 63
818 23:06:10.189563 [CA 4] Center 33 (3~64) winsize 62
819 23:06:10.192993 [CA 5] Center 34 (4~65) winsize 62
820 23:06:10.193462
821 23:06:10.196626 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 23:06:10.197185
823 23:06:10.199497 [CATrainingPosCal] consider 2 rank data
824 23:06:10.203543 u2DelayCellTimex100 = 270/100 ps
825 23:06:10.206484 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
826 23:06:10.212910 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
827 23:06:10.216435 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
828 23:06:10.219925 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
829 23:06:10.223159 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
830 23:06:10.226552 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
831 23:06:10.227113
832 23:06:10.229417 CA PerBit enable=1, Macro0, CA PI delay=34
833 23:06:10.229900
834 23:06:10.233015 [CBTSetCACLKResult] CA Dly = 34
835 23:06:10.233578 CS Dly: 6 (0~37)
836 23:06:10.236112
837 23:06:10.240385 ----->DramcWriteLeveling(PI) begin...
838 23:06:10.241217 ==
839 23:06:10.243147 Dram Type= 6, Freq= 0, CH_0, rank 0
840 23:06:10.246990 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
841 23:06:10.247462 ==
842 23:06:10.250338 Write leveling (Byte 0): 30 => 30
843 23:06:10.250809 Write leveling (Byte 1): 30 => 30
844 23:06:10.254077 DramcWriteLeveling(PI) end<-----
845 23:06:10.254543
846 23:06:10.254910 ==
847 23:06:10.257688 Dram Type= 6, Freq= 0, CH_0, rank 0
848 23:06:10.264389 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
849 23:06:10.264897 ==
850 23:06:10.265271 [Gating] SW mode calibration
851 23:06:10.272213 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 23:06:10.278348 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 23:06:10.281650 0 6 0 | B1->B0 | 3131 2f2f | 1 1 | (1 0) (1 1)
854 23:06:10.285117 0 6 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
855 23:06:10.292124 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 23:06:10.295377 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 23:06:10.298344 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 23:06:10.304910 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 23:06:10.308378 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 23:06:10.311570 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 23:06:10.318369 0 7 0 | B1->B0 | 2828 2c2c | 0 0 | (0 0) (1 1)
862 23:06:10.321905 0 7 4 | B1->B0 | 3b3b 4141 | 1 0 | (0 0) (0 0)
863 23:06:10.325239 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
864 23:06:10.332042 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
865 23:06:10.335634 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
866 23:06:10.338965 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
867 23:06:10.345086 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
868 23:06:10.348708 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
869 23:06:10.352214 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
870 23:06:10.358670 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
871 23:06:10.361522 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
872 23:06:10.365124 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
873 23:06:10.371821 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
874 23:06:10.375165 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
875 23:06:10.378220 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 23:06:10.381748 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 23:06:10.388696 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 23:06:10.391571 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 23:06:10.395280 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 23:06:10.401720 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 23:06:10.404972 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 23:06:10.408288 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 23:06:10.415185 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
884 23:06:10.418062 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
885 23:06:10.421753 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
886 23:06:10.428657 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
887 23:06:10.431681 Total UI for P1: 0, mck2ui 16
888 23:06:10.434718 best dqsien dly found for B0: ( 0, 10, 2)
889 23:06:10.435182 Total UI for P1: 0, mck2ui 16
890 23:06:10.441473 best dqsien dly found for B1: ( 0, 10, 2)
891 23:06:10.445229 best DQS0 dly(MCK, UI, PI) = (0, 10, 2)
892 23:06:10.448101 best DQS1 dly(MCK, UI, PI) = (0, 10, 2)
893 23:06:10.448599
894 23:06:10.451423 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 2)
895 23:06:10.454919 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 2)
896 23:06:10.458094 [Gating] SW calibration Done
897 23:06:10.458784 ==
898 23:06:10.461627 Dram Type= 6, Freq= 0, CH_0, rank 0
899 23:06:10.464759 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
900 23:06:10.465227 ==
901 23:06:10.468140 RX Vref Scan: 0
902 23:06:10.468710
903 23:06:10.469221 RX Vref 0 -> 0, step: 1
904 23:06:10.469684
905 23:06:10.471361 RX Delay -130 -> 252, step: 16
906 23:06:10.474841 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
907 23:06:10.481566 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
908 23:06:10.484964 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
909 23:06:10.488072 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
910 23:06:10.491427 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
911 23:06:10.494738 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
912 23:06:10.501579 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
913 23:06:10.504750 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
914 23:06:10.508333 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
915 23:06:10.511691 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
916 23:06:10.514695 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
917 23:06:10.521556 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
918 23:06:10.524777 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
919 23:06:10.528642 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
920 23:06:10.531811 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
921 23:06:10.535178 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
922 23:06:10.538783 ==
923 23:06:10.539336 Dram Type= 6, Freq= 0, CH_0, rank 0
924 23:06:10.545317 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
925 23:06:10.545882 ==
926 23:06:10.546265 DQS Delay:
927 23:06:10.548399 DQS0 = 0, DQS1 = 0
928 23:06:10.548904 DQM Delay:
929 23:06:10.551586 DQM0 = 85, DQM1 = 75
930 23:06:10.552043 DQ Delay:
931 23:06:10.555069 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77
932 23:06:10.558124 DQ4 =85, DQ5 =77, DQ6 =93, DQ7 =93
933 23:06:10.561602 DQ8 =61, DQ9 =53, DQ10 =77, DQ11 =69
934 23:06:10.564712 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
935 23:06:10.565385
936 23:06:10.565892
937 23:06:10.566239 ==
938 23:06:10.568467 Dram Type= 6, Freq= 0, CH_0, rank 0
939 23:06:10.571722 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
940 23:06:10.572288 ==
941 23:06:10.572708
942 23:06:10.573047
943 23:06:10.574672 TX Vref Scan disable
944 23:06:10.577971 == TX Byte 0 ==
945 23:06:10.581699 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
946 23:06:10.584468 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
947 23:06:10.587985 == TX Byte 1 ==
948 23:06:10.591578 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
949 23:06:10.594699 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
950 23:06:10.595161 ==
951 23:06:10.598256 Dram Type= 6, Freq= 0, CH_0, rank 0
952 23:06:10.601507 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
953 23:06:10.604868 ==
954 23:06:10.615554 TX Vref=22, minBit 0, minWin=27, winSum=444
955 23:06:10.619265 TX Vref=24, minBit 4, minWin=27, winSum=449
956 23:06:10.622372 TX Vref=26, minBit 4, minWin=27, winSum=452
957 23:06:10.625513 TX Vref=28, minBit 4, minWin=27, winSum=451
958 23:06:10.628881 TX Vref=30, minBit 0, minWin=28, winSum=457
959 23:06:10.632404 TX Vref=32, minBit 5, minWin=27, winSum=452
960 23:06:10.639710 [TxChooseVref] Worse bit 0, Min win 28, Win sum 457, Final Vref 30
961 23:06:10.640239
962 23:06:10.643024 Final TX Range 1 Vref 30
963 23:06:10.643491
964 23:06:10.643854 ==
965 23:06:10.646215 Dram Type= 6, Freq= 0, CH_0, rank 0
966 23:06:10.649681 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
967 23:06:10.650176 ==
968 23:06:10.650545
969 23:06:10.650885
970 23:06:10.652760 TX Vref Scan disable
971 23:06:10.656260 == TX Byte 0 ==
972 23:06:10.659824 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
973 23:06:10.662776 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
974 23:06:10.666288 == TX Byte 1 ==
975 23:06:10.669655 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
976 23:06:10.672914 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
977 23:06:10.673476
978 23:06:10.676532 [DATLAT]
979 23:06:10.677232 Freq=800, CH0 RK0
980 23:06:10.677651
981 23:06:10.679739 DATLAT Default: 0xa
982 23:06:10.680282 0, 0xFFFF, sum = 0
983 23:06:10.683132 1, 0xFFFF, sum = 0
984 23:06:10.683793 2, 0xFFFF, sum = 0
985 23:06:10.686421 3, 0xFFFF, sum = 0
986 23:06:10.686892 4, 0xFFFF, sum = 0
987 23:06:10.690007 5, 0xFFFF, sum = 0
988 23:06:10.690508 6, 0xFFFF, sum = 0
989 23:06:10.693148 7, 0xFFFF, sum = 0
990 23:06:10.693640 8, 0x0, sum = 1
991 23:06:10.696349 9, 0x0, sum = 2
992 23:06:10.696900 10, 0x0, sum = 3
993 23:06:10.699908 11, 0x0, sum = 4
994 23:06:10.700447 best_step = 9
995 23:06:10.700875
996 23:06:10.701216 ==
997 23:06:10.703108 Dram Type= 6, Freq= 0, CH_0, rank 0
998 23:06:10.706472 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
999 23:06:10.706938 ==
1000 23:06:10.709859 RX Vref Scan: 1
1001 23:06:10.710370
1002 23:06:10.713150 Set Vref Range= 32 -> 127
1003 23:06:10.713608
1004 23:06:10.713966 RX Vref 32 -> 127, step: 1
1005 23:06:10.714301
1006 23:06:10.716457 RX Delay -111 -> 252, step: 8
1007 23:06:10.716960
1008 23:06:10.719798 Set Vref, RX VrefLevel [Byte0]: 32
1009 23:06:10.723334 [Byte1]: 32
1010 23:06:10.726401
1011 23:06:10.726928 Set Vref, RX VrefLevel [Byte0]: 33
1012 23:06:10.729826 [Byte1]: 33
1013 23:06:10.734096
1014 23:06:10.734578 Set Vref, RX VrefLevel [Byte0]: 34
1015 23:06:10.737381 [Byte1]: 34
1016 23:06:10.742246
1017 23:06:10.742845 Set Vref, RX VrefLevel [Byte0]: 35
1018 23:06:10.745017 [Byte1]: 35
1019 23:06:10.749759
1020 23:06:10.750216 Set Vref, RX VrefLevel [Byte0]: 36
1021 23:06:10.752898 [Byte1]: 36
1022 23:06:10.756998
1023 23:06:10.757486 Set Vref, RX VrefLevel [Byte0]: 37
1024 23:06:10.760246 [Byte1]: 37
1025 23:06:10.764538
1026 23:06:10.764992 Set Vref, RX VrefLevel [Byte0]: 38
1027 23:06:10.767791 [Byte1]: 38
1028 23:06:10.772594
1029 23:06:10.773077 Set Vref, RX VrefLevel [Byte0]: 39
1030 23:06:10.775698 [Byte1]: 39
1031 23:06:10.779791
1032 23:06:10.783177 Set Vref, RX VrefLevel [Byte0]: 40
1033 23:06:10.783739 [Byte1]: 40
1034 23:06:10.787700
1035 23:06:10.788224 Set Vref, RX VrefLevel [Byte0]: 41
1036 23:06:10.790890 [Byte1]: 41
1037 23:06:10.795445
1038 23:06:10.796001 Set Vref, RX VrefLevel [Byte0]: 42
1039 23:06:10.798511 [Byte1]: 42
1040 23:06:10.802946
1041 23:06:10.803682 Set Vref, RX VrefLevel [Byte0]: 43
1042 23:06:10.806129 [Byte1]: 43
1043 23:06:10.810903
1044 23:06:10.811359 Set Vref, RX VrefLevel [Byte0]: 44
1045 23:06:10.814058 [Byte1]: 44
1046 23:06:10.818295
1047 23:06:10.818820 Set Vref, RX VrefLevel [Byte0]: 45
1048 23:06:10.821427 [Byte1]: 45
1049 23:06:10.825860
1050 23:06:10.826464 Set Vref, RX VrefLevel [Byte0]: 46
1051 23:06:10.829390 [Byte1]: 46
1052 23:06:10.833450
1053 23:06:10.833939 Set Vref, RX VrefLevel [Byte0]: 47
1054 23:06:10.836933 [Byte1]: 47
1055 23:06:10.841307
1056 23:06:10.841852 Set Vref, RX VrefLevel [Byte0]: 48
1057 23:06:10.844588 [Byte1]: 48
1058 23:06:10.848924
1059 23:06:10.849381 Set Vref, RX VrefLevel [Byte0]: 49
1060 23:06:10.851912 [Byte1]: 49
1061 23:06:10.856322
1062 23:06:10.856811 Set Vref, RX VrefLevel [Byte0]: 50
1063 23:06:10.859623 [Byte1]: 50
1064 23:06:10.864167
1065 23:06:10.864758 Set Vref, RX VrefLevel [Byte0]: 51
1066 23:06:10.867308 [Byte1]: 51
1067 23:06:10.871665
1068 23:06:10.872138 Set Vref, RX VrefLevel [Byte0]: 52
1069 23:06:10.874842 [Byte1]: 52
1070 23:06:10.879478
1071 23:06:10.880029 Set Vref, RX VrefLevel [Byte0]: 53
1072 23:06:10.882700 [Byte1]: 53
1073 23:06:10.887271
1074 23:06:10.887838 Set Vref, RX VrefLevel [Byte0]: 54
1075 23:06:10.890162 [Byte1]: 54
1076 23:06:10.894700
1077 23:06:10.895273 Set Vref, RX VrefLevel [Byte0]: 55
1078 23:06:10.897884 [Byte1]: 55
1079 23:06:10.902263
1080 23:06:10.902831 Set Vref, RX VrefLevel [Byte0]: 56
1081 23:06:10.905974 [Byte1]: 56
1082 23:06:10.910748
1083 23:06:10.911221 Set Vref, RX VrefLevel [Byte0]: 57
1084 23:06:10.914129 [Byte1]: 57
1085 23:06:10.917977
1086 23:06:10.918448 Set Vref, RX VrefLevel [Byte0]: 58
1087 23:06:10.921115 [Byte1]: 58
1088 23:06:10.925210
1089 23:06:10.925689 Set Vref, RX VrefLevel [Byte0]: 59
1090 23:06:10.928921 [Byte1]: 59
1091 23:06:10.933344
1092 23:06:10.933816 Set Vref, RX VrefLevel [Byte0]: 60
1093 23:06:10.936413 [Byte1]: 60
1094 23:06:10.940687
1095 23:06:10.941194 Set Vref, RX VrefLevel [Byte0]: 61
1096 23:06:10.944099 [Byte1]: 61
1097 23:06:10.948096
1098 23:06:10.948608 Set Vref, RX VrefLevel [Byte0]: 62
1099 23:06:10.951476 [Byte1]: 62
1100 23:06:10.955908
1101 23:06:10.956364 Set Vref, RX VrefLevel [Byte0]: 63
1102 23:06:10.959171 [Byte1]: 63
1103 23:06:10.963462
1104 23:06:10.963988 Set Vref, RX VrefLevel [Byte0]: 64
1105 23:06:10.966689 [Byte1]: 64
1106 23:06:10.971088
1107 23:06:10.971545 Set Vref, RX VrefLevel [Byte0]: 65
1108 23:06:10.974497 [Byte1]: 65
1109 23:06:10.978968
1110 23:06:10.979525 Set Vref, RX VrefLevel [Byte0]: 66
1111 23:06:10.981984 [Byte1]: 66
1112 23:06:10.987577
1113 23:06:10.988127 Set Vref, RX VrefLevel [Byte0]: 67
1114 23:06:10.992703 [Byte1]: 67
1115 23:06:10.993162
1116 23:06:10.996391 Set Vref, RX VrefLevel [Byte0]: 68
1117 23:06:10.999589 [Byte1]: 68
1118 23:06:11.000158
1119 23:06:11.003064 Set Vref, RX VrefLevel [Byte0]: 69
1120 23:06:11.006045 [Byte1]: 69
1121 23:06:11.009173
1122 23:06:11.009628 Set Vref, RX VrefLevel [Byte0]: 70
1123 23:06:11.012640 [Byte1]: 70
1124 23:06:11.017216
1125 23:06:11.017776 Set Vref, RX VrefLevel [Byte0]: 71
1126 23:06:11.020586 [Byte1]: 71
1127 23:06:11.024637
1128 23:06:11.025175 Set Vref, RX VrefLevel [Byte0]: 72
1129 23:06:11.028016 [Byte1]: 72
1130 23:06:11.032766
1131 23:06:11.033350 Set Vref, RX VrefLevel [Byte0]: 73
1132 23:06:11.035701 [Byte1]: 73
1133 23:06:11.040172
1134 23:06:11.040743 Final RX Vref Byte 0 = 48 to rank0
1135 23:06:11.043010 Final RX Vref Byte 1 = 56 to rank0
1136 23:06:11.046696 Final RX Vref Byte 0 = 48 to rank1
1137 23:06:11.049944 Final RX Vref Byte 1 = 56 to rank1==
1138 23:06:11.053051 Dram Type= 6, Freq= 0, CH_0, rank 0
1139 23:06:11.060028 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1140 23:06:11.060608 ==
1141 23:06:11.060981 DQS Delay:
1142 23:06:11.061312 DQS0 = 0, DQS1 = 0
1143 23:06:11.063172 DQM Delay:
1144 23:06:11.063629 DQM0 = 84, DQM1 = 74
1145 23:06:11.066616 DQ Delay:
1146 23:06:11.069819 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =84
1147 23:06:11.070281 DQ4 =88, DQ5 =72, DQ6 =92, DQ7 =92
1148 23:06:11.073409 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1149 23:06:11.076629 DQ12 =84, DQ13 =76, DQ14 =84, DQ15 =84
1150 23:06:11.079661
1151 23:06:11.080220
1152 23:06:11.086439 [DQSOSCAuto] RK0, (LSB)MR18= 0x3c3c, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
1153 23:06:11.089885 CH0 RK0: MR19=606, MR18=3C3C
1154 23:06:11.096668 CH0_RK0: MR19=0x606, MR18=0x3C3C, DQSOSC=394, MR23=63, INC=95, DEC=63
1155 23:06:11.097129
1156 23:06:11.099745 ----->DramcWriteLeveling(PI) begin...
1157 23:06:11.100210 ==
1158 23:06:11.103210 Dram Type= 6, Freq= 0, CH_0, rank 1
1159 23:06:11.106598 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1160 23:06:11.107060 ==
1161 23:06:11.109653 Write leveling (Byte 0): 29 => 29
1162 23:06:11.113180 Write leveling (Byte 1): 29 => 29
1163 23:06:11.116497 DramcWriteLeveling(PI) end<-----
1164 23:06:11.117075
1165 23:06:11.117436 ==
1166 23:06:11.119756 Dram Type= 6, Freq= 0, CH_0, rank 1
1167 23:06:11.123092 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1168 23:06:11.123589 ==
1169 23:06:11.126748 [Gating] SW mode calibration
1170 23:06:11.133099 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1171 23:06:11.139772 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1172 23:06:11.143443 0 6 0 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 1)
1173 23:06:11.146379 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1174 23:06:11.153204 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 23:06:11.156301 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 23:06:11.160017 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 23:06:11.166617 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 23:06:11.169848 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 23:06:11.172951 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 23:06:11.179659 0 7 0 | B1->B0 | 2929 2e2e | 0 0 | (0 0) (0 0)
1181 23:06:11.183264 0 7 4 | B1->B0 | 4444 4545 | 0 0 | (0 0) (1 1)
1182 23:06:11.186480 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1183 23:06:11.192823 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1184 23:06:11.196241 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1185 23:06:11.199926 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1186 23:06:11.203103 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1187 23:06:11.209605 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1188 23:06:11.212902 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1189 23:06:11.216378 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1190 23:06:11.223102 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1191 23:06:11.226400 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1192 23:06:11.229555 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1193 23:06:11.236315 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1194 23:06:11.239741 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1195 23:06:11.243266 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1196 23:06:11.249657 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1197 23:06:11.253327 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1198 23:06:11.256268 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 23:06:11.262927 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 23:06:11.266461 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 23:06:11.269487 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 23:06:11.276484 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 23:06:11.279737 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 23:06:11.283115 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1205 23:06:11.289897 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1206 23:06:11.292975 0 10 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1207 23:06:11.296043 Total UI for P1: 0, mck2ui 16
1208 23:06:11.299770 best dqsien dly found for B0: ( 0, 10, 2)
1209 23:06:11.303563 Total UI for P1: 0, mck2ui 16
1210 23:06:11.306195 best dqsien dly found for B1: ( 0, 10, 2)
1211 23:06:11.309811 best DQS0 dly(MCK, UI, PI) = (0, 10, 2)
1212 23:06:11.312729 best DQS1 dly(MCK, UI, PI) = (0, 10, 2)
1213 23:06:11.313216
1214 23:06:11.316298 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 2)
1215 23:06:11.319651 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 2)
1216 23:06:11.363664 [Gating] SW calibration Done
1217 23:06:11.364244 ==
1218 23:06:11.364659 Dram Type= 6, Freq= 0, CH_0, rank 1
1219 23:06:11.365005 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1220 23:06:11.365326 ==
1221 23:06:11.365992 RX Vref Scan: 0
1222 23:06:11.366336
1223 23:06:11.366646 RX Vref 0 -> 0, step: 1
1224 23:06:11.366949
1225 23:06:11.367244 RX Delay -130 -> 252, step: 16
1226 23:06:11.367546 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1227 23:06:11.367846 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1228 23:06:11.368140 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1229 23:06:11.368432 iDelay=222, Bit 3, Center 77 (-34 ~ 189) 224
1230 23:06:11.368785 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1231 23:06:11.369080 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1232 23:06:11.403431 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1233 23:06:11.404004 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1234 23:06:11.404366 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1235 23:06:11.404746 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1236 23:06:11.405066 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1237 23:06:11.405379 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1238 23:06:11.406049 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1239 23:06:11.406389 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1240 23:06:11.406698 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1241 23:06:11.407002 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1242 23:06:11.407299 ==
1243 23:06:11.407658 Dram Type= 6, Freq= 0, CH_0, rank 1
1244 23:06:11.410868 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1245 23:06:11.411433 ==
1246 23:06:11.411813 DQS Delay:
1247 23:06:11.413854 DQS0 = 0, DQS1 = 0
1248 23:06:11.414327 DQM Delay:
1249 23:06:11.414811 DQM0 = 81, DQM1 = 74
1250 23:06:11.417216 DQ Delay:
1251 23:06:11.420894 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
1252 23:06:11.424154 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =93
1253 23:06:11.427583 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
1254 23:06:11.430572 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1255 23:06:11.431035
1256 23:06:11.431392
1257 23:06:11.431722 ==
1258 23:06:11.433764 Dram Type= 6, Freq= 0, CH_0, rank 1
1259 23:06:11.437152 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1260 23:06:11.437602 ==
1261 23:06:11.437957
1262 23:06:11.438280
1263 23:06:11.441037 TX Vref Scan disable
1264 23:06:11.441587 == TX Byte 0 ==
1265 23:06:11.447840 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1266 23:06:11.450550 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1267 23:06:11.451006 == TX Byte 1 ==
1268 23:06:11.457187 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1269 23:06:11.460943 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1270 23:06:11.461492 ==
1271 23:06:11.463991 Dram Type= 6, Freq= 0, CH_0, rank 1
1272 23:06:11.467455 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1273 23:06:11.468012 ==
1274 23:06:11.481205 TX Vref=22, minBit 0, minWin=27, winSum=444
1275 23:06:11.484973 TX Vref=24, minBit 0, minWin=27, winSum=448
1276 23:06:11.487696 TX Vref=26, minBit 2, minWin=28, winSum=455
1277 23:06:11.491368 TX Vref=28, minBit 2, minWin=28, winSum=459
1278 23:06:11.495003 TX Vref=30, minBit 2, minWin=28, winSum=457
1279 23:06:11.498926 TX Vref=32, minBit 2, minWin=28, winSum=460
1280 23:06:11.506040 [TxChooseVref] Worse bit 2, Min win 28, Win sum 460, Final Vref 32
1281 23:06:11.506595
1282 23:06:11.506952 Final TX Range 1 Vref 32
1283 23:06:11.509087
1284 23:06:11.509533 ==
1285 23:06:11.512778 Dram Type= 6, Freq= 0, CH_0, rank 1
1286 23:06:11.516300 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1287 23:06:11.516796 ==
1288 23:06:11.517154
1289 23:06:11.517481
1290 23:06:11.517794 TX Vref Scan disable
1291 23:06:11.521082 == TX Byte 0 ==
1292 23:06:11.524769 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1293 23:06:11.527688 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1294 23:06:11.531016 == TX Byte 1 ==
1295 23:06:11.534139 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1296 23:06:11.537791 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1297 23:06:11.541041
1298 23:06:11.541596 [DATLAT]
1299 23:06:11.541963 Freq=800, CH0 RK1
1300 23:06:11.542306
1301 23:06:11.544372 DATLAT Default: 0x9
1302 23:06:11.544886 0, 0xFFFF, sum = 0
1303 23:06:11.547512 1, 0xFFFF, sum = 0
1304 23:06:11.547975 2, 0xFFFF, sum = 0
1305 23:06:11.550650 3, 0xFFFF, sum = 0
1306 23:06:11.551106 4, 0xFFFF, sum = 0
1307 23:06:11.554363 5, 0xFFFF, sum = 0
1308 23:06:11.557751 6, 0xFFFF, sum = 0
1309 23:06:11.558312 7, 0xFFFF, sum = 0
1310 23:06:11.558728 8, 0x0, sum = 1
1311 23:06:11.560976 9, 0x0, sum = 2
1312 23:06:11.561528 10, 0x0, sum = 3
1313 23:06:11.564054 11, 0x0, sum = 4
1314 23:06:11.564546 best_step = 9
1315 23:06:11.564908
1316 23:06:11.565235 ==
1317 23:06:11.567622 Dram Type= 6, Freq= 0, CH_0, rank 1
1318 23:06:11.574038 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1319 23:06:11.574495 ==
1320 23:06:11.574855 RX Vref Scan: 0
1321 23:06:11.575182
1322 23:06:11.577574 RX Vref 0 -> 0, step: 1
1323 23:06:11.578027
1324 23:06:11.580956 RX Delay -111 -> 252, step: 8
1325 23:06:11.584410 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
1326 23:06:11.587856 iDelay=209, Bit 1, Center 88 (-31 ~ 208) 240
1327 23:06:11.594231 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1328 23:06:11.597719 iDelay=209, Bit 3, Center 76 (-39 ~ 192) 232
1329 23:06:11.601129 iDelay=209, Bit 4, Center 88 (-31 ~ 208) 240
1330 23:06:11.604394 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1331 23:06:11.607621 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1332 23:06:11.610797 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1333 23:06:11.617438 iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232
1334 23:06:11.620841 iDelay=209, Bit 9, Center 60 (-55 ~ 176) 232
1335 23:06:11.624467 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
1336 23:06:11.628219 iDelay=209, Bit 11, Center 64 (-47 ~ 176) 224
1337 23:06:11.634792 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
1338 23:06:11.637337 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
1339 23:06:11.640829 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
1340 23:06:11.643967 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1341 23:06:11.644562 ==
1342 23:06:11.647723 Dram Type= 6, Freq= 0, CH_0, rank 1
1343 23:06:11.653770 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1344 23:06:11.654266 ==
1345 23:06:11.654626 DQS Delay:
1346 23:06:11.654956 DQS0 = 0, DQS1 = 0
1347 23:06:11.657358 DQM Delay:
1348 23:06:11.657886 DQM0 = 84, DQM1 = 74
1349 23:06:11.660427 DQ Delay:
1350 23:06:11.663889 DQ0 =80, DQ1 =88, DQ2 =84, DQ3 =76
1351 23:06:11.664339 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =92
1352 23:06:11.667919 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =64
1353 23:06:11.670855 DQ12 =84, DQ13 =80, DQ14 =84, DQ15 =84
1354 23:06:11.674246
1355 23:06:11.674692
1356 23:06:11.681178 [DQSOSCAuto] RK1, (LSB)MR18= 0x4a4a, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
1357 23:06:11.684342 CH0 RK1: MR19=606, MR18=4A4A
1358 23:06:11.690883 CH0_RK1: MR19=0x606, MR18=0x4A4A, DQSOSC=391, MR23=63, INC=96, DEC=64
1359 23:06:11.694167 [RxdqsGatingPostProcess] freq 800
1360 23:06:11.697336 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1361 23:06:11.700674 Pre-setting of DQS Precalculation
1362 23:06:11.703986 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1363 23:06:11.707501 ==
1364 23:06:11.710962 Dram Type= 6, Freq= 0, CH_1, rank 0
1365 23:06:11.713934 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1366 23:06:11.714381 ==
1367 23:06:11.717204 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1368 23:06:11.723817 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1369 23:06:11.733771 [CA 0] Center 37 (6~68) winsize 63
1370 23:06:11.737052 [CA 1] Center 37 (6~68) winsize 63
1371 23:06:11.740503 [CA 2] Center 34 (4~65) winsize 62
1372 23:06:11.743560 [CA 3] Center 34 (4~65) winsize 62
1373 23:06:11.746797 [CA 4] Center 33 (2~64) winsize 63
1374 23:06:11.750165 [CA 5] Center 33 (3~64) winsize 62
1375 23:06:11.750588
1376 23:06:11.753445 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1377 23:06:11.753759
1378 23:06:11.756838 [CATrainingPosCal] consider 1 rank data
1379 23:06:11.760293 u2DelayCellTimex100 = 270/100 ps
1380 23:06:11.763725 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1381 23:06:11.766867 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1382 23:06:11.773456 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1383 23:06:11.776697 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1384 23:06:11.780481 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
1385 23:06:11.783549 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1386 23:06:11.784110
1387 23:06:11.786977 CA PerBit enable=1, Macro0, CA PI delay=33
1388 23:06:11.787519
1389 23:06:11.790513 [CBTSetCACLKResult] CA Dly = 33
1390 23:06:11.791060 CS Dly: 5 (0~36)
1391 23:06:11.793359 ==
1392 23:06:11.793900 Dram Type= 6, Freq= 0, CH_1, rank 1
1393 23:06:11.800245 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1394 23:06:11.800831 ==
1395 23:06:11.803627 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1396 23:06:11.809788 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1397 23:06:11.819962 [CA 0] Center 36 (6~67) winsize 62
1398 23:06:11.822845 [CA 1] Center 36 (6~67) winsize 62
1399 23:06:11.825829 [CA 2] Center 34 (4~65) winsize 62
1400 23:06:11.829583 [CA 3] Center 34 (4~65) winsize 62
1401 23:06:11.832944 [CA 4] Center 33 (3~64) winsize 62
1402 23:06:11.836006 [CA 5] Center 33 (3~64) winsize 62
1403 23:06:11.836587
1404 23:06:11.839820 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1405 23:06:11.840364
1406 23:06:11.842930 [CATrainingPosCal] consider 2 rank data
1407 23:06:11.846233 u2DelayCellTimex100 = 270/100 ps
1408 23:06:11.849416 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1409 23:06:11.852976 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1410 23:06:11.859530 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1411 23:06:11.863080 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1412 23:06:11.866198 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1413 23:06:11.869351 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1414 23:06:11.869799
1415 23:06:11.873112 CA PerBit enable=1, Macro0, CA PI delay=33
1416 23:06:11.873557
1417 23:06:11.876065 [CBTSetCACLKResult] CA Dly = 33
1418 23:06:11.876663 CS Dly: 5 (0~36)
1419 23:06:11.877033
1420 23:06:11.879830 ----->DramcWriteLeveling(PI) begin...
1421 23:06:11.882888 ==
1422 23:06:11.886052 Dram Type= 6, Freq= 0, CH_1, rank 0
1423 23:06:11.889517 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1424 23:06:11.890065 ==
1425 23:06:11.892734 Write leveling (Byte 0): 25 => 25
1426 23:06:11.896075 Write leveling (Byte 1): 26 => 26
1427 23:06:11.899361 DramcWriteLeveling(PI) end<-----
1428 23:06:11.899923
1429 23:06:11.900453 ==
1430 23:06:11.902745 Dram Type= 6, Freq= 0, CH_1, rank 0
1431 23:06:11.906137 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1432 23:06:11.906685 ==
1433 23:06:11.909429 [Gating] SW mode calibration
1434 23:06:11.915980 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1435 23:06:11.919740 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1436 23:06:11.926495 0 6 0 | B1->B0 | 3030 2525 | 0 0 | (1 1) (0 0)
1437 23:06:11.929264 0 6 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1438 23:06:11.933018 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1439 23:06:11.939980 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1440 23:06:11.943036 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1441 23:06:11.946177 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1442 23:06:11.952893 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1443 23:06:11.955938 0 6 28 | B1->B0 | 2424 2727 | 0 0 | (1 1) (1 1)
1444 23:06:11.959290 0 7 0 | B1->B0 | 3131 3939 | 0 1 | (0 0) (0 0)
1445 23:06:11.965889 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1446 23:06:11.969433 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1447 23:06:11.972763 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1448 23:06:11.979554 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1449 23:06:11.982988 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1450 23:06:11.986094 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1451 23:06:11.992417 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1452 23:06:11.996064 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1453 23:06:11.999320 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1454 23:06:12.002917 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1455 23:06:12.009526 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1456 23:06:12.012726 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1457 23:06:12.015921 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1458 23:06:12.023166 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1459 23:06:12.026380 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1460 23:06:12.029536 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1461 23:06:12.036641 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1462 23:06:12.039532 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1463 23:06:12.042749 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1464 23:06:12.049638 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1465 23:06:12.052885 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1466 23:06:12.056330 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1467 23:06:12.063073 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1468 23:06:12.066052 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1469 23:06:12.069735 Total UI for P1: 0, mck2ui 16
1470 23:06:12.072712 best dqsien dly found for B0: ( 0, 9, 28)
1471 23:06:12.076285 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1472 23:06:12.079824 Total UI for P1: 0, mck2ui 16
1473 23:06:12.083448 best dqsien dly found for B1: ( 0, 10, 0)
1474 23:06:12.087002 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1475 23:06:12.089632 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1476 23:06:12.090116
1477 23:06:12.092642 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1478 23:06:12.099588 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1479 23:06:12.100041 [Gating] SW calibration Done
1480 23:06:12.100397 ==
1481 23:06:12.102882 Dram Type= 6, Freq= 0, CH_1, rank 0
1482 23:06:12.109531 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1483 23:06:12.110082 ==
1484 23:06:12.110531 RX Vref Scan: 0
1485 23:06:12.110865
1486 23:06:12.113018 RX Vref 0 -> 0, step: 1
1487 23:06:12.113570
1488 23:06:12.116241 RX Delay -130 -> 252, step: 16
1489 23:06:12.119441 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1490 23:06:12.123077 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1491 23:06:12.126380 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1492 23:06:12.133174 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1493 23:06:12.136657 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1494 23:06:12.139486 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1495 23:06:12.142993 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1496 23:06:12.146366 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1497 23:06:12.149799 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1498 23:06:12.153911 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1499 23:06:12.161460 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1500 23:06:12.164736 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1501 23:06:12.168443 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1502 23:06:12.172022 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1503 23:06:12.175499 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1504 23:06:12.178862 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1505 23:06:12.179310 ==
1506 23:06:12.182597 Dram Type= 6, Freq= 0, CH_1, rank 0
1507 23:06:12.186368 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1508 23:06:12.186819 ==
1509 23:06:12.189556 DQS Delay:
1510 23:06:12.190167 DQS0 = 0, DQS1 = 0
1511 23:06:12.190536 DQM Delay:
1512 23:06:12.192873 DQM0 = 81, DQM1 = 75
1513 23:06:12.193354 DQ Delay:
1514 23:06:12.196352 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1515 23:06:12.199723 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1516 23:06:12.202714 DQ8 =61, DQ9 =69, DQ10 =77, DQ11 =69
1517 23:06:12.206200 DQ12 =77, DQ13 =85, DQ14 =77, DQ15 =85
1518 23:06:12.206650
1519 23:06:12.207000
1520 23:06:12.207318 ==
1521 23:06:12.209528 Dram Type= 6, Freq= 0, CH_1, rank 0
1522 23:06:12.216253 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1523 23:06:12.216872 ==
1524 23:06:12.217210
1525 23:06:12.217509
1526 23:06:12.217793 TX Vref Scan disable
1527 23:06:12.219801 == TX Byte 0 ==
1528 23:06:12.223246 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1529 23:06:12.226393 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1530 23:06:12.229758 == TX Byte 1 ==
1531 23:06:12.233157 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1532 23:06:12.236405 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1533 23:06:12.239849 ==
1534 23:06:12.242990 Dram Type= 6, Freq= 0, CH_1, rank 0
1535 23:06:12.246534 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1536 23:06:12.247044 ==
1537 23:06:12.258615 TX Vref=22, minBit 2, minWin=27, winSum=444
1538 23:06:12.262322 TX Vref=24, minBit 0, minWin=28, winSum=450
1539 23:06:12.265497 TX Vref=26, minBit 0, minWin=28, winSum=453
1540 23:06:12.268894 TX Vref=28, minBit 0, minWin=28, winSum=456
1541 23:06:12.272294 TX Vref=30, minBit 0, minWin=28, winSum=459
1542 23:06:12.278837 TX Vref=32, minBit 0, minWin=28, winSum=454
1543 23:06:12.282220 [TxChooseVref] Worse bit 0, Min win 28, Win sum 459, Final Vref 30
1544 23:06:12.282773
1545 23:06:12.285296 Final TX Range 1 Vref 30
1546 23:06:12.285806
1547 23:06:12.286338 ==
1548 23:06:12.288452 Dram Type= 6, Freq= 0, CH_1, rank 0
1549 23:06:12.292188 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1550 23:06:12.292781 ==
1551 23:06:12.295418
1552 23:06:12.295963
1553 23:06:12.296320 TX Vref Scan disable
1554 23:06:12.298634 == TX Byte 0 ==
1555 23:06:12.302138 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1556 23:06:12.308599 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1557 23:06:12.309154 == TX Byte 1 ==
1558 23:06:12.311760 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1559 23:06:12.318592 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1560 23:06:12.319145
1561 23:06:12.319505 [DATLAT]
1562 23:06:12.319835 Freq=800, CH1 RK0
1563 23:06:12.320157
1564 23:06:12.322065 DATLAT Default: 0xa
1565 23:06:12.322613 0, 0xFFFF, sum = 0
1566 23:06:12.325822 1, 0xFFFF, sum = 0
1567 23:06:12.326382 2, 0xFFFF, sum = 0
1568 23:06:12.328584 3, 0xFFFF, sum = 0
1569 23:06:12.332214 4, 0xFFFF, sum = 0
1570 23:06:12.332832 5, 0xFFFF, sum = 0
1571 23:06:12.335342 6, 0xFFFF, sum = 0
1572 23:06:12.335926 7, 0xFFFF, sum = 0
1573 23:06:12.338379 8, 0x0, sum = 1
1574 23:06:12.338845 9, 0x0, sum = 2
1575 23:06:12.339211 10, 0x0, sum = 3
1576 23:06:12.341997 11, 0x0, sum = 4
1577 23:06:12.342555 best_step = 9
1578 23:06:12.342915
1579 23:06:12.343244 ==
1580 23:06:12.344978 Dram Type= 6, Freq= 0, CH_1, rank 0
1581 23:06:12.351784 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1582 23:06:12.352459 ==
1583 23:06:12.352914 RX Vref Scan: 1
1584 23:06:12.353258
1585 23:06:12.355120 Set Vref Range= 32 -> 127
1586 23:06:12.355572
1587 23:06:12.358451 RX Vref 32 -> 127, step: 1
1588 23:06:12.358911
1589 23:06:12.361908 RX Delay -95 -> 252, step: 8
1590 23:06:12.362467
1591 23:06:12.362830 Set Vref, RX VrefLevel [Byte0]: 32
1592 23:06:12.365261 [Byte1]: 32
1593 23:06:12.369545
1594 23:06:12.369995 Set Vref, RX VrefLevel [Byte0]: 33
1595 23:06:12.372996 [Byte1]: 33
1596 23:06:12.377173
1597 23:06:12.377644 Set Vref, RX VrefLevel [Byte0]: 34
1598 23:06:12.380653 [Byte1]: 34
1599 23:06:12.384829
1600 23:06:12.385375 Set Vref, RX VrefLevel [Byte0]: 35
1601 23:06:12.387977 [Byte1]: 35
1602 23:06:12.392681
1603 23:06:12.393234 Set Vref, RX VrefLevel [Byte0]: 36
1604 23:06:12.395950 [Byte1]: 36
1605 23:06:12.399752
1606 23:06:12.400205 Set Vref, RX VrefLevel [Byte0]: 37
1607 23:06:12.403174 [Byte1]: 37
1608 23:06:12.407650
1609 23:06:12.408228 Set Vref, RX VrefLevel [Byte0]: 38
1610 23:06:12.410742 [Byte1]: 38
1611 23:06:12.415336
1612 23:06:12.415882 Set Vref, RX VrefLevel [Byte0]: 39
1613 23:06:12.418518 [Byte1]: 39
1614 23:06:12.422946
1615 23:06:12.423495 Set Vref, RX VrefLevel [Byte0]: 40
1616 23:06:12.426143 [Byte1]: 40
1617 23:06:12.430354
1618 23:06:12.430902 Set Vref, RX VrefLevel [Byte0]: 41
1619 23:06:12.433793 [Byte1]: 41
1620 23:06:12.437987
1621 23:06:12.438532 Set Vref, RX VrefLevel [Byte0]: 42
1622 23:06:12.441285 [Byte1]: 42
1623 23:06:12.445494
1624 23:06:12.446043 Set Vref, RX VrefLevel [Byte0]: 43
1625 23:06:12.449386 [Byte1]: 43
1626 23:06:12.452868
1627 23:06:12.453318 Set Vref, RX VrefLevel [Byte0]: 44
1628 23:06:12.456546 [Byte1]: 44
1629 23:06:12.460751
1630 23:06:12.461200 Set Vref, RX VrefLevel [Byte0]: 45
1631 23:06:12.464130 [Byte1]: 45
1632 23:06:12.468340
1633 23:06:12.468971 Set Vref, RX VrefLevel [Byte0]: 46
1634 23:06:12.471480 [Byte1]: 46
1635 23:06:12.475788
1636 23:06:12.476244 Set Vref, RX VrefLevel [Byte0]: 47
1637 23:06:12.479355 [Byte1]: 47
1638 23:06:12.483666
1639 23:06:12.484219 Set Vref, RX VrefLevel [Byte0]: 48
1640 23:06:12.486879 [Byte1]: 48
1641 23:06:12.491348
1642 23:06:12.491900 Set Vref, RX VrefLevel [Byte0]: 49
1643 23:06:12.494407 [Byte1]: 49
1644 23:06:12.498891
1645 23:06:12.499435 Set Vref, RX VrefLevel [Byte0]: 50
1646 23:06:12.502132 [Byte1]: 50
1647 23:06:12.506360
1648 23:06:12.506989 Set Vref, RX VrefLevel [Byte0]: 51
1649 23:06:12.509564 [Byte1]: 51
1650 23:06:12.514014
1651 23:06:12.514585 Set Vref, RX VrefLevel [Byte0]: 52
1652 23:06:12.517292 [Byte1]: 52
1653 23:06:12.521296
1654 23:06:12.521746 Set Vref, RX VrefLevel [Byte0]: 53
1655 23:06:12.525066 [Byte1]: 53
1656 23:06:12.529303
1657 23:06:12.529850 Set Vref, RX VrefLevel [Byte0]: 54
1658 23:06:12.532752 [Byte1]: 54
1659 23:06:12.537067
1660 23:06:12.537616 Set Vref, RX VrefLevel [Byte0]: 55
1661 23:06:12.539952 [Byte1]: 55
1662 23:06:12.544698
1663 23:06:12.545276 Set Vref, RX VrefLevel [Byte0]: 56
1664 23:06:12.547894 [Byte1]: 56
1665 23:06:12.551818
1666 23:06:12.552329 Set Vref, RX VrefLevel [Byte0]: 57
1667 23:06:12.555577 [Byte1]: 57
1668 23:06:12.559431
1669 23:06:12.560039 Set Vref, RX VrefLevel [Byte0]: 58
1670 23:06:12.562692 [Byte1]: 58
1671 23:06:12.566852
1672 23:06:12.567419 Set Vref, RX VrefLevel [Byte0]: 59
1673 23:06:12.570139 [Byte1]: 59
1674 23:06:12.574436
1675 23:06:12.574980 Set Vref, RX VrefLevel [Byte0]: 60
1676 23:06:12.577727 [Byte1]: 60
1677 23:06:12.582310
1678 23:06:12.582907 Set Vref, RX VrefLevel [Byte0]: 61
1679 23:06:12.585519 [Byte1]: 61
1680 23:06:12.589807
1681 23:06:12.590257 Set Vref, RX VrefLevel [Byte0]: 62
1682 23:06:12.593163 [Byte1]: 62
1683 23:06:12.597840
1684 23:06:12.598389 Set Vref, RX VrefLevel [Byte0]: 63
1685 23:06:12.600914 [Byte1]: 63
1686 23:06:12.605123
1687 23:06:12.605677 Set Vref, RX VrefLevel [Byte0]: 64
1688 23:06:12.608118 [Byte1]: 64
1689 23:06:12.612594
1690 23:06:12.613042 Set Vref, RX VrefLevel [Byte0]: 65
1691 23:06:12.615988 [Byte1]: 65
1692 23:06:12.620232
1693 23:06:12.620717 Set Vref, RX VrefLevel [Byte0]: 66
1694 23:06:12.624253 [Byte1]: 66
1695 23:06:12.628108
1696 23:06:12.628700 Set Vref, RX VrefLevel [Byte0]: 67
1697 23:06:12.631444 [Byte1]: 67
1698 23:06:12.635564
1699 23:06:12.636109 Set Vref, RX VrefLevel [Byte0]: 68
1700 23:06:12.638901 [Byte1]: 68
1701 23:06:12.643206
1702 23:06:12.643750 Set Vref, RX VrefLevel [Byte0]: 69
1703 23:06:12.646205 [Byte1]: 69
1704 23:06:12.650505
1705 23:06:12.651019 Set Vref, RX VrefLevel [Byte0]: 70
1706 23:06:12.653879 [Byte1]: 70
1707 23:06:12.658538
1708 23:06:12.659083 Set Vref, RX VrefLevel [Byte0]: 71
1709 23:06:12.661634 [Byte1]: 71
1710 23:06:12.666035
1711 23:06:12.666580 Set Vref, RX VrefLevel [Byte0]: 72
1712 23:06:12.669495 [Byte1]: 72
1713 23:06:12.673903
1714 23:06:12.674463 Set Vref, RX VrefLevel [Byte0]: 73
1715 23:06:12.676876 [Byte1]: 73
1716 23:06:12.681478
1717 23:06:12.682023 Set Vref, RX VrefLevel [Byte0]: 74
1718 23:06:12.684289 [Byte1]: 74
1719 23:06:12.688701
1720 23:06:12.689249 Set Vref, RX VrefLevel [Byte0]: 75
1721 23:06:12.691963 [Byte1]: 75
1722 23:06:12.696305
1723 23:06:12.696907 Final RX Vref Byte 0 = 60 to rank0
1724 23:06:12.699728 Final RX Vref Byte 1 = 57 to rank0
1725 23:06:12.703162 Final RX Vref Byte 0 = 60 to rank1
1726 23:06:12.706273 Final RX Vref Byte 1 = 57 to rank1==
1727 23:06:12.710054 Dram Type= 6, Freq= 0, CH_1, rank 0
1728 23:06:12.715810 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1729 23:06:12.716321 ==
1730 23:06:12.716718 DQS Delay:
1731 23:06:12.717051 DQS0 = 0, DQS1 = 0
1732 23:06:12.719473 DQM Delay:
1733 23:06:12.720036 DQM0 = 81, DQM1 = 74
1734 23:06:12.723009 DQ Delay:
1735 23:06:12.726211 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =76
1736 23:06:12.729769 DQ4 =80, DQ5 =92, DQ6 =88, DQ7 =76
1737 23:06:12.730315 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =64
1738 23:06:12.733284 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =84
1739 23:06:12.733730
1740 23:06:12.734079
1741 23:06:12.743745 [DQSOSCAuto] RK0, (LSB)MR18= 0x4c4c, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
1742 23:06:12.746878 CH1 RK0: MR19=606, MR18=4C4C
1743 23:06:12.750449 CH1_RK0: MR19=0x606, MR18=0x4C4C, DQSOSC=390, MR23=63, INC=97, DEC=64
1744 23:06:12.753172
1745 23:06:12.756787 ----->DramcWriteLeveling(PI) begin...
1746 23:06:12.757347 ==
1747 23:06:12.760101 Dram Type= 6, Freq= 0, CH_1, rank 1
1748 23:06:12.763767 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1749 23:06:12.764314 ==
1750 23:06:12.766490 Write leveling (Byte 0): 26 => 26
1751 23:06:12.770281 Write leveling (Byte 1): 24 => 24
1752 23:06:12.773588 DramcWriteLeveling(PI) end<-----
1753 23:06:12.774137
1754 23:06:12.774492 ==
1755 23:06:12.776702 Dram Type= 6, Freq= 0, CH_1, rank 1
1756 23:06:12.780113 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1757 23:06:12.780901 ==
1758 23:06:12.783389 [Gating] SW mode calibration
1759 23:06:12.790197 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1760 23:06:12.796891 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1761 23:06:12.800352 0 6 0 | B1->B0 | 2929 2323 | 1 0 | (1 0) (0 0)
1762 23:06:12.803536 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1763 23:06:12.810020 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1764 23:06:12.813361 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1765 23:06:12.816602 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1766 23:06:12.820078 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1767 23:06:12.826776 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1768 23:06:12.830203 0 6 28 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
1769 23:06:12.833088 0 7 0 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
1770 23:06:12.839974 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1771 23:06:12.843233 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1772 23:06:12.846368 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1773 23:06:12.853134 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1774 23:06:12.856661 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1775 23:06:12.859802 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1776 23:06:12.866634 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1777 23:06:12.870130 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1778 23:06:12.873638 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1779 23:06:12.879881 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1780 23:06:12.883481 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1781 23:06:12.886866 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1782 23:06:12.893424 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1783 23:06:12.896666 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1784 23:06:12.900618 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1785 23:06:12.906786 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1786 23:06:12.910044 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1787 23:06:12.913130 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1788 23:06:12.916909 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1789 23:06:12.923279 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1790 23:06:12.926723 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1791 23:06:12.930222 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1792 23:06:12.936664 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1793 23:06:12.939906 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1794 23:06:12.943161 Total UI for P1: 0, mck2ui 16
1795 23:06:12.946744 best dqsien dly found for B0: ( 0, 9, 28)
1796 23:06:12.949975 Total UI for P1: 0, mck2ui 16
1797 23:06:12.952898 best dqsien dly found for B1: ( 0, 9, 30)
1798 23:06:12.956239 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1799 23:06:12.959652 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1800 23:06:12.960101
1801 23:06:12.963136 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1802 23:06:12.966775 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1803 23:06:12.969830 [Gating] SW calibration Done
1804 23:06:12.970380 ==
1805 23:06:12.973202 Dram Type= 6, Freq= 0, CH_1, rank 1
1806 23:06:12.979753 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1807 23:06:12.980209 ==
1808 23:06:12.980599 RX Vref Scan: 0
1809 23:06:12.980935
1810 23:06:12.983194 RX Vref 0 -> 0, step: 1
1811 23:06:12.983743
1812 23:06:12.986715 RX Delay -130 -> 252, step: 16
1813 23:06:12.989942 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1814 23:06:12.993238 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1815 23:06:12.996404 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1816 23:06:12.999906 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1817 23:06:13.006541 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1818 23:06:13.009786 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1819 23:06:13.012918 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1820 23:06:13.016435 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1821 23:06:13.020035 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1822 23:06:13.026822 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1823 23:06:13.029987 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1824 23:06:13.033320 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1825 23:06:13.036781 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1826 23:06:13.039840 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1827 23:06:13.046388 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1828 23:06:13.050052 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1829 23:06:13.050614 ==
1830 23:06:13.052956 Dram Type= 6, Freq= 0, CH_1, rank 1
1831 23:06:13.056583 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1832 23:06:13.057039 ==
1833 23:06:13.059830 DQS Delay:
1834 23:06:13.060382 DQS0 = 0, DQS1 = 0
1835 23:06:13.060806 DQM Delay:
1836 23:06:13.063436 DQM0 = 85, DQM1 = 72
1837 23:06:13.064026 DQ Delay:
1838 23:06:13.066640 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1839 23:06:13.069779 DQ4 =85, DQ5 =101, DQ6 =85, DQ7 =85
1840 23:06:13.073309 DQ8 =53, DQ9 =61, DQ10 =69, DQ11 =61
1841 23:06:13.076362 DQ12 =85, DQ13 =85, DQ14 =77, DQ15 =85
1842 23:06:13.076881
1843 23:06:13.077327
1844 23:06:13.077700 ==
1845 23:06:13.079887 Dram Type= 6, Freq= 0, CH_1, rank 1
1846 23:06:13.086591 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1847 23:06:13.087159 ==
1848 23:06:13.087525
1849 23:06:13.087857
1850 23:06:13.088270 TX Vref Scan disable
1851 23:06:13.090294 == TX Byte 0 ==
1852 23:06:13.093539 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1853 23:06:13.100444 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1854 23:06:13.101049 == TX Byte 1 ==
1855 23:06:13.103551 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1856 23:06:13.109964 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1857 23:06:13.110849 ==
1858 23:06:13.113066 Dram Type= 6, Freq= 0, CH_1, rank 1
1859 23:06:13.116354 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1860 23:06:13.116853 ==
1861 23:06:13.129414 TX Vref=22, minBit 0, minWin=27, winSum=450
1862 23:06:13.132790 TX Vref=24, minBit 0, minWin=27, winSum=452
1863 23:06:13.136042 TX Vref=26, minBit 0, minWin=28, winSum=457
1864 23:06:13.139554 TX Vref=28, minBit 0, minWin=28, winSum=456
1865 23:06:13.142927 TX Vref=30, minBit 0, minWin=28, winSum=455
1866 23:06:13.146070 TX Vref=32, minBit 9, minWin=27, winSum=453
1867 23:06:13.152491 [TxChooseVref] Worse bit 0, Min win 28, Win sum 457, Final Vref 26
1868 23:06:13.153029
1869 23:06:13.155881 Final TX Range 1 Vref 26
1870 23:06:13.156409
1871 23:06:13.156839 ==
1872 23:06:13.159137 Dram Type= 6, Freq= 0, CH_1, rank 1
1873 23:06:13.162889 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1874 23:06:13.163447 ==
1875 23:06:13.163806
1876 23:06:13.164203
1877 23:06:13.166080 TX Vref Scan disable
1878 23:06:13.169407 == TX Byte 0 ==
1879 23:06:13.172974 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1880 23:06:13.175894 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1881 23:06:13.179183 == TX Byte 1 ==
1882 23:06:13.182583 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1883 23:06:13.186200 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1884 23:06:13.186656
1885 23:06:13.189294 [DATLAT]
1886 23:06:13.189747 Freq=800, CH1 RK1
1887 23:06:13.190106
1888 23:06:13.192629 DATLAT Default: 0x9
1889 23:06:13.193083 0, 0xFFFF, sum = 0
1890 23:06:13.196237 1, 0xFFFF, sum = 0
1891 23:06:13.196904 2, 0xFFFF, sum = 0
1892 23:06:13.199388 3, 0xFFFF, sum = 0
1893 23:06:13.199954 4, 0xFFFF, sum = 0
1894 23:06:13.202930 5, 0xFFFF, sum = 0
1895 23:06:13.203494 6, 0xFFFF, sum = 0
1896 23:06:13.206352 7, 0xFFFF, sum = 0
1897 23:06:13.206920 8, 0x0, sum = 1
1898 23:06:13.209316 9, 0x0, sum = 2
1899 23:06:13.209805 10, 0x0, sum = 3
1900 23:06:13.212739 11, 0x0, sum = 4
1901 23:06:13.213215 best_step = 9
1902 23:06:13.213686
1903 23:06:13.214131 ==
1904 23:06:13.216398 Dram Type= 6, Freq= 0, CH_1, rank 1
1905 23:06:13.219267 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1906 23:06:13.222500 ==
1907 23:06:13.222972 RX Vref Scan: 0
1908 23:06:13.223457
1909 23:06:13.225882 RX Vref 0 -> 0, step: 1
1910 23:06:13.226354
1911 23:06:13.229386 RX Delay -111 -> 252, step: 8
1912 23:06:13.232604 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1913 23:06:13.236068 iDelay=209, Bit 1, Center 80 (-39 ~ 200) 240
1914 23:06:13.239366 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1915 23:06:13.245691 iDelay=209, Bit 3, Center 80 (-39 ~ 200) 240
1916 23:06:13.249111 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1917 23:06:13.252446 iDelay=209, Bit 5, Center 92 (-23 ~ 208) 232
1918 23:06:13.255629 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1919 23:06:13.259142 iDelay=209, Bit 7, Center 80 (-39 ~ 200) 240
1920 23:06:13.265707 iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232
1921 23:06:13.269148 iDelay=209, Bit 9, Center 60 (-55 ~ 176) 232
1922 23:06:13.272304 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
1923 23:06:13.275570 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1924 23:06:13.279041 iDelay=209, Bit 12, Center 88 (-31 ~ 208) 240
1925 23:06:13.285763 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
1926 23:06:13.288729 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1927 23:06:13.292436 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1928 23:06:13.292567 ==
1929 23:06:13.295457 Dram Type= 6, Freq= 0, CH_1, rank 1
1930 23:06:13.298713 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1931 23:06:13.298815 ==
1932 23:06:13.302217 DQS Delay:
1933 23:06:13.302316 DQS0 = 0, DQS1 = 0
1934 23:06:13.305535 DQM Delay:
1935 23:06:13.305634 DQM0 = 84, DQM1 = 75
1936 23:06:13.305741 DQ Delay:
1937 23:06:13.308636 DQ0 =88, DQ1 =80, DQ2 =76, DQ3 =80
1938 23:06:13.312258 DQ4 =84, DQ5 =92, DQ6 =92, DQ7 =80
1939 23:06:13.315369 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =68
1940 23:06:13.318733 DQ12 =88, DQ13 =84, DQ14 =80, DQ15 =84
1941 23:06:13.318834
1942 23:06:13.318938
1943 23:06:13.328729 [DQSOSCAuto] RK1, (LSB)MR18= 0x3636, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
1944 23:06:13.331994 CH1 RK1: MR19=606, MR18=3636
1945 23:06:13.335350 CH1_RK1: MR19=0x606, MR18=0x3636, DQSOSC=396, MR23=63, INC=94, DEC=62
1946 23:06:13.338677 [RxdqsGatingPostProcess] freq 800
1947 23:06:13.345531 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1948 23:06:13.348693 Pre-setting of DQS Precalculation
1949 23:06:13.352144 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1950 23:06:13.362265 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1951 23:06:13.368515 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1952 23:06:13.368597
1953 23:06:13.368681
1954 23:06:13.372031 [Calibration Summary] 1600 Mbps
1955 23:06:13.372107 CH 0, Rank 0
1956 23:06:13.375355 SW Impedance : PASS
1957 23:06:13.375429 DUTY Scan : NO K
1958 23:06:13.378724 ZQ Calibration : PASS
1959 23:06:13.381924 Jitter Meter : NO K
1960 23:06:13.382008 CBT Training : PASS
1961 23:06:13.385165 Write leveling : PASS
1962 23:06:13.388652 RX DQS gating : PASS
1963 23:06:13.388732 RX DQ/DQS(RDDQC) : PASS
1964 23:06:13.391984 TX DQ/DQS : PASS
1965 23:06:13.395288 RX DATLAT : PASS
1966 23:06:13.395368 RX DQ/DQS(Engine): PASS
1967 23:06:13.398455 TX OE : NO K
1968 23:06:13.398530 All Pass.
1969 23:06:13.398613
1970 23:06:13.401800 CH 0, Rank 1
1971 23:06:13.401876 SW Impedance : PASS
1972 23:06:13.405176 DUTY Scan : NO K
1973 23:06:13.405256 ZQ Calibration : PASS
1974 23:06:13.408715 Jitter Meter : NO K
1975 23:06:13.411696 CBT Training : PASS
1976 23:06:13.411771 Write leveling : PASS
1977 23:06:13.415188 RX DQS gating : PASS
1978 23:06:13.418587 RX DQ/DQS(RDDQC) : PASS
1979 23:06:13.418674 TX DQ/DQS : PASS
1980 23:06:13.421886 RX DATLAT : PASS
1981 23:06:13.425318 RX DQ/DQS(Engine): PASS
1982 23:06:13.425397 TX OE : NO K
1983 23:06:13.428479 All Pass.
1984 23:06:13.428572
1985 23:06:13.428651 CH 1, Rank 0
1986 23:06:13.432135 SW Impedance : PASS
1987 23:06:13.432212 DUTY Scan : NO K
1988 23:06:13.435150 ZQ Calibration : PASS
1989 23:06:13.438267 Jitter Meter : NO K
1990 23:06:13.438341 CBT Training : PASS
1991 23:06:13.441662 Write leveling : PASS
1992 23:06:13.445384 RX DQS gating : PASS
1993 23:06:13.445458 RX DQ/DQS(RDDQC) : PASS
1994 23:06:13.448324 TX DQ/DQS : PASS
1995 23:06:13.448401 RX DATLAT : PASS
1996 23:06:13.451650 RX DQ/DQS(Engine): PASS
1997 23:06:13.455034 TX OE : NO K
1998 23:06:13.455133 All Pass.
1999 23:06:13.455219
2000 23:06:13.455301 CH 1, Rank 1
2001 23:06:13.458305 SW Impedance : PASS
2002 23:06:13.461680 DUTY Scan : NO K
2003 23:06:13.461760 ZQ Calibration : PASS
2004 23:06:13.465272 Jitter Meter : NO K
2005 23:06:13.468430 CBT Training : PASS
2006 23:06:13.468575 Write leveling : PASS
2007 23:06:13.472104 RX DQS gating : PASS
2008 23:06:13.475068 RX DQ/DQS(RDDQC) : PASS
2009 23:06:13.475147 TX DQ/DQS : PASS
2010 23:06:13.478621 RX DATLAT : PASS
2011 23:06:13.481646 RX DQ/DQS(Engine): PASS
2012 23:06:13.481727 TX OE : NO K
2013 23:06:13.481791 All Pass.
2014 23:06:13.485032
2015 23:06:13.485112 DramC Write-DBI off
2016 23:06:13.488478 PER_BANK_REFRESH: Hybrid Mode
2017 23:06:13.488588 TX_TRACKING: ON
2018 23:06:13.491646 [GetDramInforAfterCalByMRR] Vendor 6.
2019 23:06:13.495089 [GetDramInforAfterCalByMRR] Revision 606.
2020 23:06:13.501595 [GetDramInforAfterCalByMRR] Revision 2 0.
2021 23:06:13.501709 MR0 0x3939
2022 23:06:13.501808 MR8 0x1111
2023 23:06:13.505155 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
2024 23:06:13.505269
2025 23:06:13.508092 MR0 0x3939
2026 23:06:13.508197 MR8 0x1111
2027 23:06:13.511462 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
2028 23:06:13.511571
2029 23:06:13.521491 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2030 23:06:13.525130 [FAST_K] Save calibration result to emmc
2031 23:06:13.528658 [FAST_K] Save calibration result to emmc
2032 23:06:13.531607 dram_init: config_dvfs: 1
2033 23:06:13.534980 dramc_set_vcore_voltage set vcore to 662500
2034 23:06:13.538274 Read voltage for 1200, 2
2035 23:06:13.538355 Vio18 = 0
2036 23:06:13.538418 Vcore = 662500
2037 23:06:13.541946 Vdram = 0
2038 23:06:13.542031 Vddq = 0
2039 23:06:13.542099 Vmddr = 0
2040 23:06:13.548347 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2041 23:06:13.551581 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2042 23:06:13.554940 MEM_TYPE=3, freq_sel=15
2043 23:06:13.558243 sv_algorithm_assistance_LP4_1600
2044 23:06:13.561801 ============ PULL DRAM RESETB DOWN ============
2045 23:06:13.565073 ========== PULL DRAM RESETB DOWN end =========
2046 23:06:13.572013 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2047 23:06:13.575105 ===================================
2048 23:06:13.575253 LPDDR4 DRAM CONFIGURATION
2049 23:06:13.578513 ===================================
2050 23:06:13.581920 EX_ROW_EN[0] = 0x0
2051 23:06:13.582122 EX_ROW_EN[1] = 0x0
2052 23:06:13.585088 LP4Y_EN = 0x0
2053 23:06:13.585299 WORK_FSP = 0x0
2054 23:06:13.588547 WL = 0x4
2055 23:06:13.591969 RL = 0x4
2056 23:06:13.592229 BL = 0x2
2057 23:06:13.595255 RPST = 0x0
2058 23:06:13.595618 RD_PRE = 0x0
2059 23:06:13.598849 WR_PRE = 0x1
2060 23:06:13.599189 WR_PST = 0x0
2061 23:06:13.602112 DBI_WR = 0x0
2062 23:06:13.602484 DBI_RD = 0x0
2063 23:06:13.605544 OTF = 0x1
2064 23:06:13.608956 ===================================
2065 23:06:13.612452 ===================================
2066 23:06:13.612995 ANA top config
2067 23:06:13.615249 ===================================
2068 23:06:13.618692 DLL_ASYNC_EN = 0
2069 23:06:13.622304 ALL_SLAVE_EN = 0
2070 23:06:13.622686 NEW_RANK_MODE = 1
2071 23:06:13.625884 DLL_IDLE_MODE = 1
2072 23:06:13.629020 LP45_APHY_COMB_EN = 1
2073 23:06:13.632059 TX_ODT_DIS = 1
2074 23:06:13.632564 NEW_8X_MODE = 1
2075 23:06:13.635369 ===================================
2076 23:06:13.638927 ===================================
2077 23:06:13.641879 data_rate = 2400
2078 23:06:13.645676 CKR = 1
2079 23:06:13.648871 DQ_P2S_RATIO = 8
2080 23:06:13.652005 ===================================
2081 23:06:13.655324 CA_P2S_RATIO = 8
2082 23:06:13.658589 DQ_CA_OPEN = 0
2083 23:06:13.659016 DQ_SEMI_OPEN = 0
2084 23:06:13.662074 CA_SEMI_OPEN = 0
2085 23:06:13.665508 CA_FULL_RATE = 0
2086 23:06:13.669005 DQ_CKDIV4_EN = 0
2087 23:06:13.672024 CA_CKDIV4_EN = 0
2088 23:06:13.675461 CA_PREDIV_EN = 0
2089 23:06:13.675874 PH8_DLY = 17
2090 23:06:13.678938 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2091 23:06:13.681936 DQ_AAMCK_DIV = 4
2092 23:06:13.685264 CA_AAMCK_DIV = 4
2093 23:06:13.688587 CA_ADMCK_DIV = 4
2094 23:06:13.692119 DQ_TRACK_CA_EN = 0
2095 23:06:13.695126 CA_PICK = 1200
2096 23:06:13.695550 CA_MCKIO = 1200
2097 23:06:13.698451 MCKIO_SEMI = 0
2098 23:06:13.701966 PLL_FREQ = 2366
2099 23:06:13.705125 DQ_UI_PI_RATIO = 32
2100 23:06:13.708325 CA_UI_PI_RATIO = 0
2101 23:06:13.711905 ===================================
2102 23:06:13.715054 ===================================
2103 23:06:13.718786 memory_type:LPDDR4
2104 23:06:13.719198 GP_NUM : 10
2105 23:06:13.721537 SRAM_EN : 1
2106 23:06:13.722021 MD32_EN : 0
2107 23:06:13.725289 ===================================
2108 23:06:13.728607 [ANA_INIT] >>>>>>>>>>>>>>
2109 23:06:13.731768 <<<<<< [CONFIGURE PHASE]: ANA_TX
2110 23:06:13.735036 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2111 23:06:13.738331 ===================================
2112 23:06:13.741718 data_rate = 2400,PCW = 0X5b00
2113 23:06:13.745114 ===================================
2114 23:06:13.748331 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2115 23:06:13.754827 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2116 23:06:13.758148 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2117 23:06:13.764987 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2118 23:06:13.768210 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2119 23:06:13.771586 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2120 23:06:13.772090 [ANA_INIT] flow start
2121 23:06:13.774741 [ANA_INIT] PLL >>>>>>>>
2122 23:06:13.778189 [ANA_INIT] PLL <<<<<<<<
2123 23:06:13.778793 [ANA_INIT] MIDPI >>>>>>>>
2124 23:06:13.781529 [ANA_INIT] MIDPI <<<<<<<<
2125 23:06:13.784829 [ANA_INIT] DLL >>>>>>>>
2126 23:06:13.785391 [ANA_INIT] DLL <<<<<<<<
2127 23:06:13.788300 [ANA_INIT] flow end
2128 23:06:13.791809 ============ LP4 DIFF to SE enter ============
2129 23:06:13.795175 ============ LP4 DIFF to SE exit ============
2130 23:06:13.798363 [ANA_INIT] <<<<<<<<<<<<<
2131 23:06:13.801684 [Flow] Enable top DCM control >>>>>
2132 23:06:13.804920 [Flow] Enable top DCM control <<<<<
2133 23:06:13.808179 Enable DLL master slave shuffle
2134 23:06:13.814942 ==============================================================
2135 23:06:13.815383 Gating Mode config
2136 23:06:13.821676 ==============================================================
2137 23:06:13.822243 Config description:
2138 23:06:13.831454 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2139 23:06:13.838133 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2140 23:06:13.844848 SELPH_MODE 0: By rank 1: By Phase
2141 23:06:13.848053 ==============================================================
2142 23:06:13.851285 GAT_TRACK_EN = 1
2143 23:06:13.854480 RX_GATING_MODE = 2
2144 23:06:13.857798 RX_GATING_TRACK_MODE = 2
2145 23:06:13.861354 SELPH_MODE = 1
2146 23:06:13.864444 PICG_EARLY_EN = 1
2147 23:06:13.868128 VALID_LAT_VALUE = 1
2148 23:06:13.874509 ==============================================================
2149 23:06:13.877731 Enter into Gating configuration >>>>
2150 23:06:13.881083 Exit from Gating configuration <<<<
2151 23:06:13.884427 Enter into DVFS_PRE_config >>>>>
2152 23:06:13.894397 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2153 23:06:13.897765 Exit from DVFS_PRE_config <<<<<
2154 23:06:13.901046 Enter into PICG configuration >>>>
2155 23:06:13.904290 Exit from PICG configuration <<<<
2156 23:06:13.907825 [RX_INPUT] configuration >>>>>
2157 23:06:13.908261 [RX_INPUT] configuration <<<<<
2158 23:06:13.914720 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2159 23:06:13.921110 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2160 23:06:13.924584 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2161 23:06:13.931269 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2162 23:06:13.937854 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2163 23:06:13.944725 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2164 23:06:13.948058 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2165 23:06:13.951523 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2166 23:06:13.957970 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2167 23:06:13.961638 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2168 23:06:13.964699 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2169 23:06:13.967535 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2170 23:06:13.970670 ===================================
2171 23:06:13.973987 LPDDR4 DRAM CONFIGURATION
2172 23:06:13.977605 ===================================
2173 23:06:13.980896 EX_ROW_EN[0] = 0x0
2174 23:06:13.980975 EX_ROW_EN[1] = 0x0
2175 23:06:13.984768 LP4Y_EN = 0x0
2176 23:06:13.984848 WORK_FSP = 0x0
2177 23:06:13.987575 WL = 0x4
2178 23:06:13.987655 RL = 0x4
2179 23:06:13.990914 BL = 0x2
2180 23:06:13.990993 RPST = 0x0
2181 23:06:13.994146 RD_PRE = 0x0
2182 23:06:13.994225 WR_PRE = 0x1
2183 23:06:13.997339 WR_PST = 0x0
2184 23:06:13.997426 DBI_WR = 0x0
2185 23:06:14.001110 DBI_RD = 0x0
2186 23:06:14.001189 OTF = 0x1
2187 23:06:14.004281 ===================================
2188 23:06:14.010960 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2189 23:06:14.014431 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2190 23:06:14.017519 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2191 23:06:14.020763 ===================================
2192 23:06:14.023916 LPDDR4 DRAM CONFIGURATION
2193 23:06:14.027312 ===================================
2194 23:06:14.030627 EX_ROW_EN[0] = 0x10
2195 23:06:14.030723 EX_ROW_EN[1] = 0x0
2196 23:06:14.034241 LP4Y_EN = 0x0
2197 23:06:14.034322 WORK_FSP = 0x0
2198 23:06:14.037621 WL = 0x4
2199 23:06:14.037692 RL = 0x4
2200 23:06:14.040718 BL = 0x2
2201 23:06:14.040790 RPST = 0x0
2202 23:06:14.044032 RD_PRE = 0x0
2203 23:06:14.044131 WR_PRE = 0x1
2204 23:06:14.047450 WR_PST = 0x0
2205 23:06:14.047548 DBI_WR = 0x0
2206 23:06:14.050891 DBI_RD = 0x0
2207 23:06:14.050997 OTF = 0x1
2208 23:06:14.054068 ===================================
2209 23:06:14.061081 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2210 23:06:14.061168 ==
2211 23:06:14.064435 Dram Type= 6, Freq= 0, CH_0, rank 0
2212 23:06:14.067378 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2213 23:06:14.070853 ==
2214 23:06:14.070932 [Duty_Offset_Calibration]
2215 23:06:14.074107 B0:0 B1:2 CA:1
2216 23:06:14.074187
2217 23:06:14.077056 [DutyScan_Calibration_Flow] k_type=0
2218 23:06:14.085683
2219 23:06:14.085772 ==CLK 0==
2220 23:06:14.089388 Final CLK duty delay cell = 0
2221 23:06:14.092659 [0] MAX Duty = 5093%(X100), DQS PI = 12
2222 23:06:14.095969 [0] MIN Duty = 4938%(X100), DQS PI = 52
2223 23:06:14.096049 [0] AVG Duty = 5015%(X100)
2224 23:06:14.099183
2225 23:06:14.102800 CH0 CLK Duty spec in!! Max-Min= 155%
2226 23:06:14.105831 [DutyScan_Calibration_Flow] ====Done====
2227 23:06:14.105910
2228 23:06:14.109168 [DutyScan_Calibration_Flow] k_type=1
2229 23:06:14.125108
2230 23:06:14.125188 ==DQS 0 ==
2231 23:06:14.128597 Final DQS duty delay cell = 0
2232 23:06:14.132183 [0] MAX Duty = 5125%(X100), DQS PI = 28
2233 23:06:14.135315 [0] MIN Duty = 5031%(X100), DQS PI = 4
2234 23:06:14.135395 [0] AVG Duty = 5078%(X100)
2235 23:06:14.138908
2236 23:06:14.138987 ==DQS 1 ==
2237 23:06:14.141951 Final DQS duty delay cell = 0
2238 23:06:14.145296 [0] MAX Duty = 5031%(X100), DQS PI = 52
2239 23:06:14.148778 [0] MIN Duty = 4906%(X100), DQS PI = 16
2240 23:06:14.148858 [0] AVG Duty = 4968%(X100)
2241 23:06:14.151890
2242 23:06:14.155065 CH0 DQS 0 Duty spec in!! Max-Min= 94%
2243 23:06:14.155145
2244 23:06:14.158427 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2245 23:06:14.161863 [DutyScan_Calibration_Flow] ====Done====
2246 23:06:14.161943
2247 23:06:14.165182 [DutyScan_Calibration_Flow] k_type=3
2248 23:06:14.181320
2249 23:06:14.181399 ==DQM 0 ==
2250 23:06:14.184888 Final DQM duty delay cell = 0
2251 23:06:14.187987 [0] MAX Duty = 5124%(X100), DQS PI = 20
2252 23:06:14.191383 [0] MIN Duty = 4969%(X100), DQS PI = 42
2253 23:06:14.194875 [0] AVG Duty = 5046%(X100)
2254 23:06:14.194955
2255 23:06:14.195018 ==DQM 1 ==
2256 23:06:14.198250 Final DQM duty delay cell = 0
2257 23:06:14.201573 [0] MAX Duty = 5000%(X100), DQS PI = 54
2258 23:06:14.204545 [0] MIN Duty = 4844%(X100), DQS PI = 0
2259 23:06:14.208229 [0] AVG Duty = 4922%(X100)
2260 23:06:14.208334
2261 23:06:14.211553 CH0 DQM 0 Duty spec in!! Max-Min= 155%
2262 23:06:14.211633
2263 23:06:14.215130 CH0 DQM 1 Duty spec in!! Max-Min= 156%
2264 23:06:14.218226 [DutyScan_Calibration_Flow] ====Done====
2265 23:06:14.218305
2266 23:06:14.221439 [DutyScan_Calibration_Flow] k_type=2
2267 23:06:14.236487
2268 23:06:14.236610 ==DQ 0 ==
2269 23:06:14.239967 Final DQ duty delay cell = -4
2270 23:06:14.243036 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2271 23:06:14.246349 [-4] MIN Duty = 4813%(X100), DQS PI = 54
2272 23:06:14.249868 [-4] AVG Duty = 4937%(X100)
2273 23:06:14.249966
2274 23:06:14.250055 ==DQ 1 ==
2275 23:06:14.253021 Final DQ duty delay cell = -4
2276 23:06:14.256159 [-4] MAX Duty = 5062%(X100), DQS PI = 6
2277 23:06:14.259880 [-4] MIN Duty = 4876%(X100), DQS PI = 62
2278 23:06:14.262826 [-4] AVG Duty = 4969%(X100)
2279 23:06:14.262928
2280 23:06:14.266261 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2281 23:06:14.266341
2282 23:06:14.269795 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2283 23:06:14.273057 [DutyScan_Calibration_Flow] ====Done====
2284 23:06:14.273137 ==
2285 23:06:14.276494 Dram Type= 6, Freq= 0, CH_1, rank 0
2286 23:06:14.279845 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2287 23:06:14.279926 ==
2288 23:06:14.283132 [Duty_Offset_Calibration]
2289 23:06:14.283213 B0:0 B1:5 CA:-5
2290 23:06:14.283276
2291 23:06:14.286382 [DutyScan_Calibration_Flow] k_type=0
2292 23:06:14.297020
2293 23:06:14.297099 ==CLK 0==
2294 23:06:14.300747 Final CLK duty delay cell = 0
2295 23:06:14.303839 [0] MAX Duty = 5094%(X100), DQS PI = 24
2296 23:06:14.307040 [0] MIN Duty = 4875%(X100), DQS PI = 46
2297 23:06:14.307120 [0] AVG Duty = 4984%(X100)
2298 23:06:14.310278
2299 23:06:14.313896 CH1 CLK Duty spec in!! Max-Min= 219%
2300 23:06:14.317346 [DutyScan_Calibration_Flow] ====Done====
2301 23:06:14.317426
2302 23:06:14.320346 [DutyScan_Calibration_Flow] k_type=1
2303 23:06:14.335614
2304 23:06:14.335693 ==DQS 0 ==
2305 23:06:14.339319 Final DQS duty delay cell = 0
2306 23:06:14.342751 [0] MAX Duty = 5125%(X100), DQS PI = 16
2307 23:06:14.345545 [0] MIN Duty = 4875%(X100), DQS PI = 40
2308 23:06:14.349066 [0] AVG Duty = 5000%(X100)
2309 23:06:14.349146
2310 23:06:14.349209 ==DQS 1 ==
2311 23:06:14.352300 Final DQS duty delay cell = -4
2312 23:06:14.355635 [-4] MAX Duty = 5000%(X100), DQS PI = 6
2313 23:06:14.359064 [-4] MIN Duty = 4907%(X100), DQS PI = 46
2314 23:06:14.362239 [-4] AVG Duty = 4953%(X100)
2315 23:06:14.362319
2316 23:06:14.365802 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2317 23:06:14.365882
2318 23:06:14.368777 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2319 23:06:14.372445 [DutyScan_Calibration_Flow] ====Done====
2320 23:06:14.372581
2321 23:06:14.375574 [DutyScan_Calibration_Flow] k_type=3
2322 23:06:14.390825
2323 23:06:14.390905 ==DQM 0 ==
2324 23:06:14.394044 Final DQM duty delay cell = -4
2325 23:06:14.397528 [-4] MAX Duty = 5094%(X100), DQS PI = 32
2326 23:06:14.400792 [-4] MIN Duty = 4844%(X100), DQS PI = 40
2327 23:06:14.404051 [-4] AVG Duty = 4969%(X100)
2328 23:06:14.404130
2329 23:06:14.404193 ==DQM 1 ==
2330 23:06:14.407365 Final DQM duty delay cell = -4
2331 23:06:14.410665 [-4] MAX Duty = 5094%(X100), DQS PI = 22
2332 23:06:14.414128 [-4] MIN Duty = 4906%(X100), DQS PI = 56
2333 23:06:14.417687 [-4] AVG Duty = 5000%(X100)
2334 23:06:14.417767
2335 23:06:14.420618 CH1 DQM 0 Duty spec in!! Max-Min= 250%
2336 23:06:14.420698
2337 23:06:14.424361 CH1 DQM 1 Duty spec in!! Max-Min= 188%
2338 23:06:14.427567 [DutyScan_Calibration_Flow] ====Done====
2339 23:06:14.427647
2340 23:06:14.430935 [DutyScan_Calibration_Flow] k_type=2
2341 23:06:14.447892
2342 23:06:14.447971 ==DQ 0 ==
2343 23:06:14.451483 Final DQ duty delay cell = 0
2344 23:06:14.454585 [0] MAX Duty = 5062%(X100), DQS PI = 0
2345 23:06:14.458131 [0] MIN Duty = 4969%(X100), DQS PI = 42
2346 23:06:14.458211 [0] AVG Duty = 5015%(X100)
2347 23:06:14.458275
2348 23:06:14.462010 ==DQ 1 ==
2349 23:06:14.464693 Final DQ duty delay cell = 0
2350 23:06:14.467911 [0] MAX Duty = 5000%(X100), DQS PI = 6
2351 23:06:14.471586 [0] MIN Duty = 4907%(X100), DQS PI = 0
2352 23:06:14.471666 [0] AVG Duty = 4953%(X100)
2353 23:06:14.471730
2354 23:06:14.474932 CH1 DQ 0 Duty spec in!! Max-Min= 93%
2355 23:06:14.475012
2356 23:06:14.478230 CH1 DQ 1 Duty spec in!! Max-Min= 93%
2357 23:06:14.481496 [DutyScan_Calibration_Flow] ====Done====
2358 23:06:14.486655 nWR fixed to 30
2359 23:06:14.490041 [ModeRegInit_LP4] CH0 RK0
2360 23:06:14.490121 [ModeRegInit_LP4] CH0 RK1
2361 23:06:14.493577 [ModeRegInit_LP4] CH1 RK0
2362 23:06:14.496834 [ModeRegInit_LP4] CH1 RK1
2363 23:06:14.496913 match AC timing 6
2364 23:06:14.503413 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2365 23:06:14.506658 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2366 23:06:14.510035 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2367 23:06:14.516465 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2368 23:06:14.519911 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2369 23:06:14.520009 ==
2370 23:06:14.523179 Dram Type= 6, Freq= 0, CH_0, rank 0
2371 23:06:14.526911 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2372 23:06:14.527010 ==
2373 23:06:14.533427 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2374 23:06:14.539665 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2375 23:06:14.547701 [CA 0] Center 39 (9~70) winsize 62
2376 23:06:14.550909 [CA 1] Center 39 (9~70) winsize 62
2377 23:06:14.554125 [CA 2] Center 36 (5~67) winsize 63
2378 23:06:14.557368 [CA 3] Center 35 (4~66) winsize 63
2379 23:06:14.560714 [CA 4] Center 34 (3~65) winsize 63
2380 23:06:14.564012 [CA 5] Center 33 (3~64) winsize 62
2381 23:06:14.564087
2382 23:06:14.567441 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2383 23:06:14.567532
2384 23:06:14.570638 [CATrainingPosCal] consider 1 rank data
2385 23:06:14.573994 u2DelayCellTimex100 = 270/100 ps
2386 23:06:14.577591 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2387 23:06:14.580554 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2388 23:06:14.587418 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2389 23:06:14.590532 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2390 23:06:14.593953 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
2391 23:06:14.597312 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2392 23:06:14.597386
2393 23:06:14.600857 CA PerBit enable=1, Macro0, CA PI delay=33
2394 23:06:14.600925
2395 23:06:14.603856 [CBTSetCACLKResult] CA Dly = 33
2396 23:06:14.603949 CS Dly: 7 (0~38)
2397 23:06:14.607590 ==
2398 23:06:14.607685 Dram Type= 6, Freq= 0, CH_0, rank 1
2399 23:06:14.614155 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2400 23:06:14.614228 ==
2401 23:06:14.617407 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2402 23:06:14.623869 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2403 23:06:14.632717 [CA 0] Center 39 (8~70) winsize 63
2404 23:06:14.636424 [CA 1] Center 39 (8~70) winsize 63
2405 23:06:14.639859 [CA 2] Center 36 (5~67) winsize 63
2406 23:06:14.642965 [CA 3] Center 35 (4~66) winsize 63
2407 23:06:14.646419 [CA 4] Center 33 (3~64) winsize 62
2408 23:06:14.649799 [CA 5] Center 34 (3~65) winsize 63
2409 23:06:14.649888
2410 23:06:14.652989 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2411 23:06:14.653056
2412 23:06:14.656184 [CATrainingPosCal] consider 2 rank data
2413 23:06:14.659464 u2DelayCellTimex100 = 270/100 ps
2414 23:06:14.662880 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2415 23:06:14.666132 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2416 23:06:14.672910 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2417 23:06:14.676178 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2418 23:06:14.679794 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2419 23:06:14.682744 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2420 23:06:14.682814
2421 23:06:14.686010 CA PerBit enable=1, Macro0, CA PI delay=33
2422 23:06:14.686112
2423 23:06:14.689738 [CBTSetCACLKResult] CA Dly = 33
2424 23:06:14.689837 CS Dly: 7 (0~39)
2425 23:06:14.689925
2426 23:06:14.692761 ----->DramcWriteLeveling(PI) begin...
2427 23:06:14.696176 ==
2428 23:06:14.699650 Dram Type= 6, Freq= 0, CH_0, rank 0
2429 23:06:14.703004 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2430 23:06:14.703107 ==
2431 23:06:14.706176 Write leveling (Byte 0): 29 => 29
2432 23:06:14.709294 Write leveling (Byte 1): 25 => 25
2433 23:06:14.712764 DramcWriteLeveling(PI) end<-----
2434 23:06:14.712858
2435 23:06:14.712947 ==
2436 23:06:14.715938 Dram Type= 6, Freq= 0, CH_0, rank 0
2437 23:06:14.719817 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2438 23:06:14.719910 ==
2439 23:06:14.722592 [Gating] SW mode calibration
2440 23:06:14.729361 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2441 23:06:14.736104 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2442 23:06:14.739424 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2443 23:06:14.742585 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2444 23:06:14.746223 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2445 23:06:14.752691 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2446 23:06:14.756189 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2447 23:06:14.762425 0 11 20 | B1->B0 | 2d2d 2a2a | 0 0 | (0 0) (1 0)
2448 23:06:14.765785 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2449 23:06:14.769073 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2450 23:06:14.772562 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2451 23:06:14.779173 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2452 23:06:14.782348 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2453 23:06:14.785761 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2454 23:06:14.792414 0 12 16 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
2455 23:06:14.795881 0 12 20 | B1->B0 | 3f3f 4545 | 0 0 | (0 0) (0 0)
2456 23:06:14.799264 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2457 23:06:14.805803 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2458 23:06:14.808982 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2459 23:06:14.812484 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2460 23:06:14.819137 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2461 23:06:14.822768 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2462 23:06:14.825564 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2463 23:06:14.832396 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2464 23:06:14.835735 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2465 23:06:14.838914 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2466 23:06:14.846058 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2467 23:06:14.848877 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2468 23:06:14.852453 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2469 23:06:14.859024 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2470 23:06:14.862262 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2471 23:06:14.865408 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2472 23:06:14.872049 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2473 23:06:14.875755 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2474 23:06:14.878906 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2475 23:06:14.885165 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2476 23:06:14.888492 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2477 23:06:14.891975 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2478 23:06:14.898478 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2479 23:06:14.901866 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2480 23:06:14.905486 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2481 23:06:14.908394 Total UI for P1: 0, mck2ui 16
2482 23:06:14.911917 best dqsien dly found for B0: ( 0, 15, 18)
2483 23:06:14.915049 Total UI for P1: 0, mck2ui 16
2484 23:06:14.918437 best dqsien dly found for B1: ( 0, 15, 18)
2485 23:06:14.921837 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2486 23:06:14.925205 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2487 23:06:14.925306
2488 23:06:14.928490 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2489 23:06:14.935339 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
2490 23:06:14.935438 [Gating] SW calibration Done
2491 23:06:14.935538 ==
2492 23:06:14.938272 Dram Type= 6, Freq= 0, CH_0, rank 0
2493 23:06:14.945012 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2494 23:06:14.945085 ==
2495 23:06:14.945146 RX Vref Scan: 0
2496 23:06:14.945208
2497 23:06:14.948389 RX Vref 0 -> 0, step: 1
2498 23:06:14.948482
2499 23:06:14.951603 RX Delay -40 -> 252, step: 8
2500 23:06:14.955003 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2501 23:06:14.958409 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2502 23:06:14.961649 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2503 23:06:14.968266 iDelay=200, Bit 3, Center 111 (32 ~ 191) 160
2504 23:06:14.971824 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2505 23:06:14.974837 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2506 23:06:14.978370 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2507 23:06:14.981771 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2508 23:06:14.988220 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2509 23:06:14.991922 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2510 23:06:14.995127 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2511 23:06:14.998577 iDelay=200, Bit 11, Center 103 (40 ~ 167) 128
2512 23:06:15.001942 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2513 23:06:15.005066 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2514 23:06:15.011572 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2515 23:06:15.015141 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
2516 23:06:15.015222 ==
2517 23:06:15.018565 Dram Type= 6, Freq= 0, CH_0, rank 0
2518 23:06:15.021801 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2519 23:06:15.021882 ==
2520 23:06:15.025297 DQS Delay:
2521 23:06:15.025377 DQS0 = 0, DQS1 = 0
2522 23:06:15.025439 DQM Delay:
2523 23:06:15.028273 DQM0 = 115, DQM1 = 106
2524 23:06:15.028352 DQ Delay:
2525 23:06:15.031837 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =111
2526 23:06:15.035032 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2527 23:06:15.038404 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =103
2528 23:06:15.044913 DQ12 =111, DQ13 =115, DQ14 =115, DQ15 =115
2529 23:06:15.044993
2530 23:06:15.045056
2531 23:06:15.045113 ==
2532 23:06:15.048293 Dram Type= 6, Freq= 0, CH_0, rank 0
2533 23:06:15.051522 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2534 23:06:15.051602 ==
2535 23:06:15.051665
2536 23:06:15.051723
2537 23:06:15.054876 TX Vref Scan disable
2538 23:06:15.054955 == TX Byte 0 ==
2539 23:06:15.061754 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2540 23:06:15.064806 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2541 23:06:15.064887 == TX Byte 1 ==
2542 23:06:15.071637 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2543 23:06:15.074980 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2544 23:06:15.075064 ==
2545 23:06:15.078330 Dram Type= 6, Freq= 0, CH_0, rank 0
2546 23:06:15.081590 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2547 23:06:15.081677 ==
2548 23:06:15.094603 TX Vref=22, minBit 8, minWin=25, winSum=411
2549 23:06:15.098024 TX Vref=24, minBit 10, minWin=25, winSum=420
2550 23:06:15.101097 TX Vref=26, minBit 10, minWin=25, winSum=429
2551 23:06:15.104798 TX Vref=28, minBit 8, minWin=26, winSum=429
2552 23:06:15.107718 TX Vref=30, minBit 8, minWin=26, winSum=435
2553 23:06:15.114610 TX Vref=32, minBit 9, minWin=26, winSum=436
2554 23:06:15.117980 [TxChooseVref] Worse bit 9, Min win 26, Win sum 436, Final Vref 32
2555 23:06:15.118063
2556 23:06:15.121514 Final TX Range 1 Vref 32
2557 23:06:15.121597
2558 23:06:15.121680 ==
2559 23:06:15.124847 Dram Type= 6, Freq= 0, CH_0, rank 0
2560 23:06:15.128062 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2561 23:06:15.128145 ==
2562 23:06:15.131585
2563 23:06:15.131667
2564 23:06:15.131750 TX Vref Scan disable
2565 23:06:15.134428 == TX Byte 0 ==
2566 23:06:15.137800 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2567 23:06:15.141331 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2568 23:06:15.144606 == TX Byte 1 ==
2569 23:06:15.147762 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2570 23:06:15.151158 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2571 23:06:15.154462
2572 23:06:15.154568 [DATLAT]
2573 23:06:15.154652 Freq=1200, CH0 RK0
2574 23:06:15.154732
2575 23:06:15.158037 DATLAT Default: 0xd
2576 23:06:15.158144 0, 0xFFFF, sum = 0
2577 23:06:15.161179 1, 0xFFFF, sum = 0
2578 23:06:15.161264 2, 0xFFFF, sum = 0
2579 23:06:15.164668 3, 0xFFFF, sum = 0
2580 23:06:15.167801 4, 0xFFFF, sum = 0
2581 23:06:15.167884 5, 0xFFFF, sum = 0
2582 23:06:15.171429 6, 0xFFFF, sum = 0
2583 23:06:15.171512 7, 0xFFFF, sum = 0
2584 23:06:15.174886 8, 0xFFFF, sum = 0
2585 23:06:15.174975 9, 0xFFFF, sum = 0
2586 23:06:15.178086 10, 0xFFFF, sum = 0
2587 23:06:15.178170 11, 0x0, sum = 1
2588 23:06:15.181157 12, 0x0, sum = 2
2589 23:06:15.181245 13, 0x0, sum = 3
2590 23:06:15.181330 14, 0x0, sum = 4
2591 23:06:15.184811 best_step = 12
2592 23:06:15.184894
2593 23:06:15.184977 ==
2594 23:06:15.187866 Dram Type= 6, Freq= 0, CH_0, rank 0
2595 23:06:15.191143 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2596 23:06:15.191277 ==
2597 23:06:15.194639 RX Vref Scan: 1
2598 23:06:15.194722
2599 23:06:15.197793 Set Vref Range= 32 -> 127
2600 23:06:15.197875
2601 23:06:15.197959 RX Vref 32 -> 127, step: 1
2602 23:06:15.198039
2603 23:06:15.201355 RX Delay -21 -> 252, step: 4
2604 23:06:15.201437
2605 23:06:15.204605 Set Vref, RX VrefLevel [Byte0]: 32
2606 23:06:15.207791 [Byte1]: 32
2607 23:06:15.211288
2608 23:06:15.211421 Set Vref, RX VrefLevel [Byte0]: 33
2609 23:06:15.214654 [Byte1]: 33
2610 23:06:15.219243
2611 23:06:15.219324 Set Vref, RX VrefLevel [Byte0]: 34
2612 23:06:15.222538 [Byte1]: 34
2613 23:06:15.227480
2614 23:06:15.227562 Set Vref, RX VrefLevel [Byte0]: 35
2615 23:06:15.230385 [Byte1]: 35
2616 23:06:15.235402
2617 23:06:15.235484 Set Vref, RX VrefLevel [Byte0]: 36
2618 23:06:15.238313 [Byte1]: 36
2619 23:06:15.243171
2620 23:06:15.243253 Set Vref, RX VrefLevel [Byte0]: 37
2621 23:06:15.246214 [Byte1]: 37
2622 23:06:15.250939
2623 23:06:15.251021 Set Vref, RX VrefLevel [Byte0]: 38
2624 23:06:15.254175 [Byte1]: 38
2625 23:06:15.259166
2626 23:06:15.259247 Set Vref, RX VrefLevel [Byte0]: 39
2627 23:06:15.262169 [Byte1]: 39
2628 23:06:15.266927
2629 23:06:15.267009 Set Vref, RX VrefLevel [Byte0]: 40
2630 23:06:15.270108 [Byte1]: 40
2631 23:06:15.274637
2632 23:06:15.274719 Set Vref, RX VrefLevel [Byte0]: 41
2633 23:06:15.278162 [Byte1]: 41
2634 23:06:15.282489
2635 23:06:15.282571 Set Vref, RX VrefLevel [Byte0]: 42
2636 23:06:15.285873 [Byte1]: 42
2637 23:06:15.290661
2638 23:06:15.290743 Set Vref, RX VrefLevel [Byte0]: 43
2639 23:06:15.293882 [Byte1]: 43
2640 23:06:15.298540
2641 23:06:15.298622 Set Vref, RX VrefLevel [Byte0]: 44
2642 23:06:15.301809 [Byte1]: 44
2643 23:06:15.306348
2644 23:06:15.306430 Set Vref, RX VrefLevel [Byte0]: 45
2645 23:06:15.309715 [Byte1]: 45
2646 23:06:15.314658
2647 23:06:15.314743 Set Vref, RX VrefLevel [Byte0]: 46
2648 23:06:15.317618 [Byte1]: 46
2649 23:06:15.322199
2650 23:06:15.322281 Set Vref, RX VrefLevel [Byte0]: 47
2651 23:06:15.325599 [Byte1]: 47
2652 23:06:15.330134
2653 23:06:15.330216 Set Vref, RX VrefLevel [Byte0]: 48
2654 23:06:15.333316 [Byte1]: 48
2655 23:06:15.338129
2656 23:06:15.338211 Set Vref, RX VrefLevel [Byte0]: 49
2657 23:06:15.341349 [Byte1]: 49
2658 23:06:15.346150
2659 23:06:15.346231 Set Vref, RX VrefLevel [Byte0]: 50
2660 23:06:15.349380 [Byte1]: 50
2661 23:06:15.353966
2662 23:06:15.354048 Set Vref, RX VrefLevel [Byte0]: 51
2663 23:06:15.357186 [Byte1]: 51
2664 23:06:15.361994
2665 23:06:15.362076 Set Vref, RX VrefLevel [Byte0]: 52
2666 23:06:15.365217 [Byte1]: 52
2667 23:06:15.369878
2668 23:06:15.369960 Set Vref, RX VrefLevel [Byte0]: 53
2669 23:06:15.372967 [Byte1]: 53
2670 23:06:15.377639
2671 23:06:15.377723 Set Vref, RX VrefLevel [Byte0]: 54
2672 23:06:15.380792 [Byte1]: 54
2673 23:06:15.385649
2674 23:06:15.385731 Set Vref, RX VrefLevel [Byte0]: 55
2675 23:06:15.389293 [Byte1]: 55
2676 23:06:15.393637
2677 23:06:15.393719 Set Vref, RX VrefLevel [Byte0]: 56
2678 23:06:15.397105 [Byte1]: 56
2679 23:06:15.401515
2680 23:06:15.401619 Set Vref, RX VrefLevel [Byte0]: 57
2681 23:06:15.404656 [Byte1]: 57
2682 23:06:15.409457
2683 23:06:15.409536 Set Vref, RX VrefLevel [Byte0]: 58
2684 23:06:15.412713 [Byte1]: 58
2685 23:06:15.417233
2686 23:06:15.417312 Set Vref, RX VrefLevel [Byte0]: 59
2687 23:06:15.420428 [Byte1]: 59
2688 23:06:15.425099
2689 23:06:15.425179 Set Vref, RX VrefLevel [Byte0]: 60
2690 23:06:15.428447 [Byte1]: 60
2691 23:06:15.433281
2692 23:06:15.433360 Set Vref, RX VrefLevel [Byte0]: 61
2693 23:06:15.436421 [Byte1]: 61
2694 23:06:15.440913
2695 23:06:15.440992 Set Vref, RX VrefLevel [Byte0]: 62
2696 23:06:15.444314 [Byte1]: 62
2697 23:06:15.449148
2698 23:06:15.449227 Set Vref, RX VrefLevel [Byte0]: 63
2699 23:06:15.452773 [Byte1]: 63
2700 23:06:15.456907
2701 23:06:15.456987 Set Vref, RX VrefLevel [Byte0]: 64
2702 23:06:15.460269 [Byte1]: 64
2703 23:06:15.464627
2704 23:06:15.464706 Set Vref, RX VrefLevel [Byte0]: 65
2705 23:06:15.468003 [Byte1]: 65
2706 23:06:15.472703
2707 23:06:15.472783 Set Vref, RX VrefLevel [Byte0]: 66
2708 23:06:15.476095 [Byte1]: 66
2709 23:06:15.480895
2710 23:06:15.480974 Set Vref, RX VrefLevel [Byte0]: 67
2711 23:06:15.483822 [Byte1]: 67
2712 23:06:15.488444
2713 23:06:15.488582 Final RX Vref Byte 0 = 46 to rank0
2714 23:06:15.491673 Final RX Vref Byte 1 = 46 to rank0
2715 23:06:15.495204 Final RX Vref Byte 0 = 46 to rank1
2716 23:06:15.498510 Final RX Vref Byte 1 = 46 to rank1==
2717 23:06:15.501843 Dram Type= 6, Freq= 0, CH_0, rank 0
2718 23:06:15.508448 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2719 23:06:15.508567 ==
2720 23:06:15.508631 DQS Delay:
2721 23:06:15.511795 DQS0 = 0, DQS1 = 0
2722 23:06:15.511874 DQM Delay:
2723 23:06:15.511937 DQM0 = 114, DQM1 = 104
2724 23:06:15.514951 DQ Delay:
2725 23:06:15.518411 DQ0 =110, DQ1 =114, DQ2 =112, DQ3 =108
2726 23:06:15.521775 DQ4 =118, DQ5 =106, DQ6 =124, DQ7 =120
2727 23:06:15.525231 DQ8 =94, DQ9 =86, DQ10 =106, DQ11 =96
2728 23:06:15.528376 DQ12 =114, DQ13 =112, DQ14 =116, DQ15 =114
2729 23:06:15.528481
2730 23:06:15.528562
2731 23:06:15.535165 [DQSOSCAuto] RK0, (LSB)MR18= 0x909, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps
2732 23:06:15.538355 CH0 RK0: MR19=404, MR18=909
2733 23:06:15.545109 CH0_RK0: MR19=0x404, MR18=0x909, DQSOSC=406, MR23=63, INC=39, DEC=26
2734 23:06:15.545189
2735 23:06:15.548294 ----->DramcWriteLeveling(PI) begin...
2736 23:06:15.548400 ==
2737 23:06:15.551906 Dram Type= 6, Freq= 0, CH_0, rank 1
2738 23:06:15.555038 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2739 23:06:15.555119 ==
2740 23:06:15.558160 Write leveling (Byte 0): 26 => 26
2741 23:06:15.561600 Write leveling (Byte 1): 24 => 24
2742 23:06:15.564988 DramcWriteLeveling(PI) end<-----
2743 23:06:15.565068
2744 23:06:15.565130 ==
2745 23:06:15.568265 Dram Type= 6, Freq= 0, CH_0, rank 1
2746 23:06:15.575197 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2747 23:06:15.575278 ==
2748 23:06:15.575342 [Gating] SW mode calibration
2749 23:06:15.585243 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2750 23:06:15.588238 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2751 23:06:15.591897 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2752 23:06:15.598652 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2753 23:06:15.601582 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2754 23:06:15.605018 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2755 23:06:15.611750 0 11 16 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2756 23:06:15.615265 0 11 20 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
2757 23:06:15.618324 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2758 23:06:15.624868 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2759 23:06:15.628196 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2760 23:06:15.631970 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2761 23:06:15.638351 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2762 23:06:15.641700 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2763 23:06:15.645117 0 12 16 | B1->B0 | 2525 3333 | 0 1 | (0 0) (0 0)
2764 23:06:15.651718 0 12 20 | B1->B0 | 3c3b 4646 | 1 0 | (0 0) (0 0)
2765 23:06:15.654918 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2766 23:06:15.658493 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2767 23:06:15.665298 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2768 23:06:15.668401 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2769 23:06:15.671773 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2770 23:06:15.674947 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2771 23:06:15.681460 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2772 23:06:15.684958 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2773 23:06:15.688130 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2774 23:06:15.694779 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2775 23:06:15.698332 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2776 23:06:15.701679 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2777 23:06:15.708153 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2778 23:06:15.711436 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2779 23:06:15.714975 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2780 23:06:15.721696 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2781 23:06:15.724807 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2782 23:06:15.728132 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2783 23:06:15.734738 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2784 23:06:15.738061 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2785 23:06:15.741504 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2786 23:06:15.747987 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2787 23:06:15.751356 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2788 23:06:15.754696 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2789 23:06:15.761606 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2790 23:06:15.761686 Total UI for P1: 0, mck2ui 16
2791 23:06:15.764885 best dqsien dly found for B0: ( 0, 15, 18)
2792 23:06:15.768043 Total UI for P1: 0, mck2ui 16
2793 23:06:15.771532 best dqsien dly found for B1: ( 0, 15, 18)
2794 23:06:15.778137 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2795 23:06:15.781358 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2796 23:06:15.781438
2797 23:06:15.784733 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2798 23:06:15.788177 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
2799 23:06:15.791284 [Gating] SW calibration Done
2800 23:06:15.791364 ==
2801 23:06:15.794804 Dram Type= 6, Freq= 0, CH_0, rank 1
2802 23:06:15.797913 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2803 23:06:15.797993 ==
2804 23:06:15.801204 RX Vref Scan: 0
2805 23:06:15.801284
2806 23:06:15.801346 RX Vref 0 -> 0, step: 1
2807 23:06:15.801404
2808 23:06:15.804849 RX Delay -40 -> 252, step: 8
2809 23:06:15.807931 iDelay=200, Bit 0, Center 107 (32 ~ 183) 152
2810 23:06:15.815083 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2811 23:06:15.818193 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2812 23:06:15.821206 iDelay=200, Bit 3, Center 107 (40 ~ 175) 136
2813 23:06:15.824408 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2814 23:06:15.827728 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2815 23:06:15.834684 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2816 23:06:15.837671 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2817 23:06:15.840966 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2818 23:06:15.844480 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2819 23:06:15.847958 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2820 23:06:15.854478 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2821 23:06:15.857772 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2822 23:06:15.860781 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2823 23:06:15.864123 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2824 23:06:15.867610 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2825 23:06:15.870996 ==
2826 23:06:15.873937 Dram Type= 6, Freq= 0, CH_0, rank 1
2827 23:06:15.877678 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2828 23:06:15.877758 ==
2829 23:06:15.877847 DQS Delay:
2830 23:06:15.880780 DQS0 = 0, DQS1 = 0
2831 23:06:15.880861 DQM Delay:
2832 23:06:15.883943 DQM0 = 114, DQM1 = 106
2833 23:06:15.884046 DQ Delay:
2834 23:06:15.887520 DQ0 =107, DQ1 =115, DQ2 =115, DQ3 =107
2835 23:06:15.890636 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2836 23:06:15.894055 DQ8 =91, DQ9 =91, DQ10 =111, DQ11 =99
2837 23:06:15.897370 DQ12 =115, DQ13 =111, DQ14 =119, DQ15 =115
2838 23:06:15.897443
2839 23:06:15.897503
2840 23:06:15.897560 ==
2841 23:06:15.900539 Dram Type= 6, Freq= 0, CH_0, rank 1
2842 23:06:15.907427 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2843 23:06:15.907528 ==
2844 23:06:15.907628
2845 23:06:15.907714
2846 23:06:15.907798 TX Vref Scan disable
2847 23:06:15.910850 == TX Byte 0 ==
2848 23:06:15.914067 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2849 23:06:15.917297 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2850 23:06:15.920733 == TX Byte 1 ==
2851 23:06:15.923846 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2852 23:06:15.930631 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2853 23:06:15.930736 ==
2854 23:06:15.933827 Dram Type= 6, Freq= 0, CH_0, rank 1
2855 23:06:15.936933 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2856 23:06:15.937002 ==
2857 23:06:15.948399 TX Vref=22, minBit 5, minWin=25, winSum=414
2858 23:06:15.951694 TX Vref=24, minBit 8, minWin=25, winSum=420
2859 23:06:15.955234 TX Vref=26, minBit 0, minWin=26, winSum=424
2860 23:06:15.958380 TX Vref=28, minBit 9, minWin=26, winSum=429
2861 23:06:15.961869 TX Vref=30, minBit 1, minWin=26, winSum=425
2862 23:06:15.968393 TX Vref=32, minBit 8, minWin=26, winSum=435
2863 23:06:15.971725 [TxChooseVref] Worse bit 8, Min win 26, Win sum 435, Final Vref 32
2864 23:06:15.971821
2865 23:06:15.975159 Final TX Range 1 Vref 32
2866 23:06:15.975228
2867 23:06:15.975289 ==
2868 23:06:15.978567 Dram Type= 6, Freq= 0, CH_0, rank 1
2869 23:06:15.981826 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2870 23:06:15.981896 ==
2871 23:06:15.981956
2872 23:06:15.985083
2873 23:06:15.985153 TX Vref Scan disable
2874 23:06:15.988744 == TX Byte 0 ==
2875 23:06:15.992010 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2876 23:06:15.995280 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2877 23:06:15.998538 == TX Byte 1 ==
2878 23:06:16.001566 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
2879 23:06:16.004848 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
2880 23:06:16.008213
2881 23:06:16.008308 [DATLAT]
2882 23:06:16.008402 Freq=1200, CH0 RK1
2883 23:06:16.008492
2884 23:06:16.011826 DATLAT Default: 0xc
2885 23:06:16.011925 0, 0xFFFF, sum = 0
2886 23:06:16.015241 1, 0xFFFF, sum = 0
2887 23:06:16.015313 2, 0xFFFF, sum = 0
2888 23:06:16.018449 3, 0xFFFF, sum = 0
2889 23:06:16.018543 4, 0xFFFF, sum = 0
2890 23:06:16.021944 5, 0xFFFF, sum = 0
2891 23:06:16.022038 6, 0xFFFF, sum = 0
2892 23:06:16.024900 7, 0xFFFF, sum = 0
2893 23:06:16.028320 8, 0xFFFF, sum = 0
2894 23:06:16.028415 9, 0xFFFF, sum = 0
2895 23:06:16.032031 10, 0xFFFF, sum = 0
2896 23:06:16.032126 11, 0x0, sum = 1
2897 23:06:16.034972 12, 0x0, sum = 2
2898 23:06:16.035069 13, 0x0, sum = 3
2899 23:06:16.035157 14, 0x0, sum = 4
2900 23:06:16.038415 best_step = 12
2901 23:06:16.038516
2902 23:06:16.038601 ==
2903 23:06:16.042230 Dram Type= 6, Freq= 0, CH_0, rank 1
2904 23:06:16.045280 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2905 23:06:16.045349 ==
2906 23:06:16.048392 RX Vref Scan: 0
2907 23:06:16.048486
2908 23:06:16.048596 RX Vref 0 -> 0, step: 1
2909 23:06:16.048672
2910 23:06:16.051424 RX Delay -21 -> 252, step: 4
2911 23:06:16.058719 iDelay=195, Bit 0, Center 110 (39 ~ 182) 144
2912 23:06:16.062073 iDelay=195, Bit 1, Center 116 (43 ~ 190) 148
2913 23:06:16.065516 iDelay=195, Bit 2, Center 112 (43 ~ 182) 140
2914 23:06:16.069059 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
2915 23:06:16.072419 iDelay=195, Bit 4, Center 118 (47 ~ 190) 144
2916 23:06:16.078573 iDelay=195, Bit 5, Center 106 (35 ~ 178) 144
2917 23:06:16.082171 iDelay=195, Bit 6, Center 124 (55 ~ 194) 140
2918 23:06:16.085309 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
2919 23:06:16.088634 iDelay=195, Bit 8, Center 92 (31 ~ 154) 124
2920 23:06:16.091744 iDelay=195, Bit 9, Center 88 (27 ~ 150) 124
2921 23:06:16.098596 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
2922 23:06:16.101998 iDelay=195, Bit 11, Center 96 (35 ~ 158) 124
2923 23:06:16.105292 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
2924 23:06:16.108430 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
2925 23:06:16.111788 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
2926 23:06:16.118473 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
2927 23:06:16.118570 ==
2928 23:06:16.121979 Dram Type= 6, Freq= 0, CH_0, rank 1
2929 23:06:16.125115 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2930 23:06:16.125197 ==
2931 23:06:16.125261 DQS Delay:
2932 23:06:16.128655 DQS0 = 0, DQS1 = 0
2933 23:06:16.128735 DQM Delay:
2934 23:06:16.132044 DQM0 = 114, DQM1 = 105
2935 23:06:16.132123 DQ Delay:
2936 23:06:16.135212 DQ0 =110, DQ1 =116, DQ2 =112, DQ3 =108
2937 23:06:16.138664 DQ4 =118, DQ5 =106, DQ6 =124, DQ7 =124
2938 23:06:16.141782 DQ8 =92, DQ9 =88, DQ10 =110, DQ11 =96
2939 23:06:16.145069 DQ12 =112, DQ13 =112, DQ14 =116, DQ15 =114
2940 23:06:16.145149
2941 23:06:16.145212
2942 23:06:16.155260 [DQSOSCAuto] RK1, (LSB)MR18= 0xe0e, (MSB)MR19= 0x404, tDQSOscB0 = 404 ps tDQSOscB1 = 404 ps
2943 23:06:16.158582 CH0 RK1: MR19=404, MR18=E0E
2944 23:06:16.161879 CH0_RK1: MR19=0x404, MR18=0xE0E, DQSOSC=404, MR23=63, INC=40, DEC=26
2945 23:06:16.165091 [RxdqsGatingPostProcess] freq 1200
2946 23:06:16.171866 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2947 23:06:16.175150 Pre-setting of DQS Precalculation
2948 23:06:16.178226 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2949 23:06:16.178306 ==
2950 23:06:16.181821 Dram Type= 6, Freq= 0, CH_1, rank 0
2951 23:06:16.188364 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2952 23:06:16.188494 ==
2953 23:06:16.191553 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2954 23:06:16.198114 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2955 23:06:16.207068 [CA 0] Center 37 (7~68) winsize 62
2956 23:06:16.210315 [CA 1] Center 37 (7~68) winsize 62
2957 23:06:16.213574 [CA 2] Center 34 (4~65) winsize 62
2958 23:06:16.217128 [CA 3] Center 33 (3~64) winsize 62
2959 23:06:16.220367 [CA 4] Center 32 (1~63) winsize 63
2960 23:06:16.224086 [CA 5] Center 32 (2~63) winsize 62
2961 23:06:16.224189
2962 23:06:16.227036 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2963 23:06:16.227138
2964 23:06:16.230253 [CATrainingPosCal] consider 1 rank data
2965 23:06:16.233746 u2DelayCellTimex100 = 270/100 ps
2966 23:06:16.237215 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2967 23:06:16.240382 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2968 23:06:16.247085 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2969 23:06:16.250222 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2970 23:06:16.253643 CA4 delay=32 (1~63),Diff = 0 PI (0 cell)
2971 23:06:16.256935 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2972 23:06:16.257003
2973 23:06:16.260158 CA PerBit enable=1, Macro0, CA PI delay=32
2974 23:06:16.260252
2975 23:06:16.263577 [CBTSetCACLKResult] CA Dly = 32
2976 23:06:16.263665 CS Dly: 6 (0~37)
2977 23:06:16.266724 ==
2978 23:06:16.266820 Dram Type= 6, Freq= 0, CH_1, rank 1
2979 23:06:16.273569 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2980 23:06:16.273651 ==
2981 23:06:16.277021 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2982 23:06:16.283395 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2983 23:06:16.292237 [CA 0] Center 37 (6~68) winsize 63
2984 23:06:16.295498 [CA 1] Center 37 (7~68) winsize 62
2985 23:06:16.299266 [CA 2] Center 34 (3~65) winsize 63
2986 23:06:16.302348 [CA 3] Center 33 (3~64) winsize 62
2987 23:06:16.305660 [CA 4] Center 32 (2~63) winsize 62
2988 23:06:16.309149 [CA 5] Center 32 (2~62) winsize 61
2989 23:06:16.309217
2990 23:06:16.312163 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2991 23:06:16.312255
2992 23:06:16.315783 [CATrainingPosCal] consider 2 rank data
2993 23:06:16.318973 u2DelayCellTimex100 = 270/100 ps
2994 23:06:16.322230 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2995 23:06:16.325516 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2996 23:06:16.332360 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2997 23:06:16.335440 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2998 23:06:16.338902 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2999 23:06:16.342108 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
3000 23:06:16.342211
3001 23:06:16.345528 CA PerBit enable=1, Macro0, CA PI delay=32
3002 23:06:16.345601
3003 23:06:16.348741 [CBTSetCACLKResult] CA Dly = 32
3004 23:06:16.348814 CS Dly: 6 (0~38)
3005 23:06:16.348894
3006 23:06:16.352152 ----->DramcWriteLeveling(PI) begin...
3007 23:06:16.355746 ==
3008 23:06:16.359029 Dram Type= 6, Freq= 0, CH_1, rank 0
3009 23:06:16.362027 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3010 23:06:16.362132 ==
3011 23:06:16.365565 Write leveling (Byte 0): 22 => 22
3012 23:06:16.368853 Write leveling (Byte 1): 22 => 22
3013 23:06:16.372122 DramcWriteLeveling(PI) end<-----
3014 23:06:16.372219
3015 23:06:16.372306 ==
3016 23:06:16.375285 Dram Type= 6, Freq= 0, CH_1, rank 0
3017 23:06:16.378921 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3018 23:06:16.379019 ==
3019 23:06:16.382445 [Gating] SW mode calibration
3020 23:06:16.388824 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3021 23:06:16.392273 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3022 23:06:16.398794 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3023 23:06:16.401955 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3024 23:06:16.405222 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3025 23:06:16.411925 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3026 23:06:16.415505 0 11 16 | B1->B0 | 3333 2727 | 1 0 | (1 1) (0 1)
3027 23:06:16.418739 0 11 20 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
3028 23:06:16.425595 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3029 23:06:16.428915 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3030 23:06:16.431986 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3031 23:06:16.438816 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3032 23:06:16.442121 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3033 23:06:16.445377 0 12 12 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
3034 23:06:16.452278 0 12 16 | B1->B0 | 3c3c 4646 | 0 0 | (1 1) (0 0)
3035 23:06:16.455542 0 12 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3036 23:06:16.458585 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3037 23:06:16.465422 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3038 23:06:16.468730 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3039 23:06:16.472269 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3040 23:06:16.479073 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3041 23:06:16.482020 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3042 23:06:16.485326 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3043 23:06:16.488664 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3044 23:06:16.495635 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3045 23:06:16.498543 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3046 23:06:16.502048 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3047 23:06:16.508777 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3048 23:06:16.512071 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3049 23:06:16.515697 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3050 23:06:16.522475 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3051 23:06:16.525420 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3052 23:06:16.528831 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3053 23:06:16.535420 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3054 23:06:16.538867 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3055 23:06:16.541856 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3056 23:06:16.548543 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3057 23:06:16.552143 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3058 23:06:16.555276 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3059 23:06:16.562070 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3060 23:06:16.562150 Total UI for P1: 0, mck2ui 16
3061 23:06:16.568908 best dqsien dly found for B0: ( 0, 15, 16)
3062 23:06:16.571968 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3063 23:06:16.575229 Total UI for P1: 0, mck2ui 16
3064 23:06:16.578556 best dqsien dly found for B1: ( 0, 15, 18)
3065 23:06:16.581870 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
3066 23:06:16.585233 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
3067 23:06:16.585328
3068 23:06:16.588673 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
3069 23:06:16.591989 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
3070 23:06:16.595260 [Gating] SW calibration Done
3071 23:06:16.595357 ==
3072 23:06:16.598405 Dram Type= 6, Freq= 0, CH_1, rank 0
3073 23:06:16.601965 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3074 23:06:16.602035 ==
3075 23:06:16.605437 RX Vref Scan: 0
3076 23:06:16.605506
3077 23:06:16.608574 RX Vref 0 -> 0, step: 1
3078 23:06:16.608676
3079 23:06:16.608764 RX Delay -40 -> 252, step: 8
3080 23:06:16.615337 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160
3081 23:06:16.618869 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3082 23:06:16.621999 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3083 23:06:16.625615 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3084 23:06:16.628747 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3085 23:06:16.635408 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3086 23:06:16.638928 iDelay=208, Bit 6, Center 119 (40 ~ 199) 160
3087 23:06:16.642088 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3088 23:06:16.645743 iDelay=208, Bit 8, Center 87 (16 ~ 159) 144
3089 23:06:16.648919 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
3090 23:06:16.655378 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3091 23:06:16.658986 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3092 23:06:16.662251 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3093 23:06:16.665528 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3094 23:06:16.668514 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3095 23:06:16.675588 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3096 23:06:16.675655 ==
3097 23:06:16.678663 Dram Type= 6, Freq= 0, CH_1, rank 0
3098 23:06:16.682131 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3099 23:06:16.682202 ==
3100 23:06:16.682261 DQS Delay:
3101 23:06:16.685389 DQS0 = 0, DQS1 = 0
3102 23:06:16.685465 DQM Delay:
3103 23:06:16.688906 DQM0 = 116, DQM1 = 109
3104 23:06:16.688992 DQ Delay:
3105 23:06:16.691855 DQ0 =119, DQ1 =111, DQ2 =107, DQ3 =115
3106 23:06:16.695549 DQ4 =115, DQ5 =127, DQ6 =119, DQ7 =115
3107 23:06:16.698860 DQ8 =87, DQ9 =99, DQ10 =111, DQ11 =99
3108 23:06:16.702296 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3109 23:06:16.702401
3110 23:06:16.702490
3111 23:06:16.702575 ==
3112 23:06:16.705276 Dram Type= 6, Freq= 0, CH_1, rank 0
3113 23:06:16.711990 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3114 23:06:16.712091 ==
3115 23:06:16.712186
3116 23:06:16.712271
3117 23:06:16.712362 TX Vref Scan disable
3118 23:06:16.715884 == TX Byte 0 ==
3119 23:06:16.719046 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3120 23:06:16.722696 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3121 23:06:16.725673 == TX Byte 1 ==
3122 23:06:16.728999 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3123 23:06:16.732263 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3124 23:06:16.735828 ==
3125 23:06:16.738911 Dram Type= 6, Freq= 0, CH_1, rank 0
3126 23:06:16.742587 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3127 23:06:16.742691 ==
3128 23:06:16.753206 TX Vref=22, minBit 8, minWin=25, winSum=418
3129 23:06:16.756436 TX Vref=24, minBit 3, minWin=25, winSum=421
3130 23:06:16.759691 TX Vref=26, minBit 11, minWin=25, winSum=425
3131 23:06:16.763328 TX Vref=28, minBit 8, minWin=26, winSum=430
3132 23:06:16.766433 TX Vref=30, minBit 8, minWin=26, winSum=432
3133 23:06:16.773253 TX Vref=32, minBit 9, minWin=25, winSum=430
3134 23:06:16.776481 [TxChooseVref] Worse bit 8, Min win 26, Win sum 432, Final Vref 30
3135 23:06:16.776567
3136 23:06:16.779816 Final TX Range 1 Vref 30
3137 23:06:16.779910
3138 23:06:16.780005 ==
3139 23:06:16.783312 Dram Type= 6, Freq= 0, CH_1, rank 0
3140 23:06:16.786428 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3141 23:06:16.786531 ==
3142 23:06:16.790147
3143 23:06:16.790248
3144 23:06:16.790335 TX Vref Scan disable
3145 23:06:16.793177 == TX Byte 0 ==
3146 23:06:16.796598 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3147 23:06:16.800176 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3148 23:06:16.803085 == TX Byte 1 ==
3149 23:06:16.806537 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3150 23:06:16.810490 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3151 23:06:16.810594
3152 23:06:16.813160 [DATLAT]
3153 23:06:16.813233 Freq=1200, CH1 RK0
3154 23:06:16.813325
3155 23:06:16.816646 DATLAT Default: 0xd
3156 23:06:16.816746 0, 0xFFFF, sum = 0
3157 23:06:16.820166 1, 0xFFFF, sum = 0
3158 23:06:16.820271 2, 0xFFFF, sum = 0
3159 23:06:16.823235 3, 0xFFFF, sum = 0
3160 23:06:16.823336 4, 0xFFFF, sum = 0
3161 23:06:16.826649 5, 0xFFFF, sum = 0
3162 23:06:16.826729 6, 0xFFFF, sum = 0
3163 23:06:16.830408 7, 0xFFFF, sum = 0
3164 23:06:16.833564 8, 0xFFFF, sum = 0
3165 23:06:16.833632 9, 0xFFFF, sum = 0
3166 23:06:16.836515 10, 0xFFFF, sum = 0
3167 23:06:16.836601 11, 0x0, sum = 1
3168 23:06:16.839831 12, 0x0, sum = 2
3169 23:06:16.839926 13, 0x0, sum = 3
3170 23:06:16.840024 14, 0x0, sum = 4
3171 23:06:16.843110 best_step = 12
3172 23:06:16.843203
3173 23:06:16.843298 ==
3174 23:06:16.846705 Dram Type= 6, Freq= 0, CH_1, rank 0
3175 23:06:16.849722 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3176 23:06:16.849796 ==
3177 23:06:16.852928 RX Vref Scan: 1
3178 23:06:16.853020
3179 23:06:16.856661 Set Vref Range= 32 -> 127
3180 23:06:16.856729
3181 23:06:16.856789 RX Vref 32 -> 127, step: 1
3182 23:06:16.856846
3183 23:06:16.859625 RX Delay -29 -> 252, step: 4
3184 23:06:16.859718
3185 23:06:16.863102 Set Vref, RX VrefLevel [Byte0]: 32
3186 23:06:16.866346 [Byte1]: 32
3187 23:06:16.869873
3188 23:06:16.869943 Set Vref, RX VrefLevel [Byte0]: 33
3189 23:06:16.873301 [Byte1]: 33
3190 23:06:16.877677
3191 23:06:16.877747 Set Vref, RX VrefLevel [Byte0]: 34
3192 23:06:16.880940 [Byte1]: 34
3193 23:06:16.885650
3194 23:06:16.885743 Set Vref, RX VrefLevel [Byte0]: 35
3195 23:06:16.888856 [Byte1]: 35
3196 23:06:16.893521
3197 23:06:16.893622 Set Vref, RX VrefLevel [Byte0]: 36
3198 23:06:16.896774 [Byte1]: 36
3199 23:06:16.901551
3200 23:06:16.901656 Set Vref, RX VrefLevel [Byte0]: 37
3201 23:06:16.904809 [Byte1]: 37
3202 23:06:16.909521
3203 23:06:16.909591 Set Vref, RX VrefLevel [Byte0]: 38
3204 23:06:16.912925 [Byte1]: 38
3205 23:06:16.917556
3206 23:06:16.917634 Set Vref, RX VrefLevel [Byte0]: 39
3207 23:06:16.920781 [Byte1]: 39
3208 23:06:16.925634
3209 23:06:16.925731 Set Vref, RX VrefLevel [Byte0]: 40
3210 23:06:16.928647 [Byte1]: 40
3211 23:06:16.933363
3212 23:06:16.933438 Set Vref, RX VrefLevel [Byte0]: 41
3213 23:06:16.936839 [Byte1]: 41
3214 23:06:16.941410
3215 23:06:16.941492 Set Vref, RX VrefLevel [Byte0]: 42
3216 23:06:16.944649 [Byte1]: 42
3217 23:06:16.949343
3218 23:06:16.949440 Set Vref, RX VrefLevel [Byte0]: 43
3219 23:06:16.952862 [Byte1]: 43
3220 23:06:16.957421
3221 23:06:16.957525 Set Vref, RX VrefLevel [Byte0]: 44
3222 23:06:16.960601 [Byte1]: 44
3223 23:06:16.965422
3224 23:06:16.965518 Set Vref, RX VrefLevel [Byte0]: 45
3225 23:06:16.968643 [Byte1]: 45
3226 23:06:16.973297
3227 23:06:16.973368 Set Vref, RX VrefLevel [Byte0]: 46
3228 23:06:16.976483 [Byte1]: 46
3229 23:06:16.981153
3230 23:06:16.981222 Set Vref, RX VrefLevel [Byte0]: 47
3231 23:06:16.984555 [Byte1]: 47
3232 23:06:16.989172
3233 23:06:16.989243 Set Vref, RX VrefLevel [Byte0]: 48
3234 23:06:16.992487 [Byte1]: 48
3235 23:06:16.996985
3236 23:06:16.997057 Set Vref, RX VrefLevel [Byte0]: 49
3237 23:06:17.000500 [Byte1]: 49
3238 23:06:17.004828
3239 23:06:17.004896 Set Vref, RX VrefLevel [Byte0]: 50
3240 23:06:17.008411 [Byte1]: 50
3241 23:06:17.013183
3242 23:06:17.013250 Set Vref, RX VrefLevel [Byte0]: 51
3243 23:06:17.016159 [Byte1]: 51
3244 23:06:17.021016
3245 23:06:17.021128 Set Vref, RX VrefLevel [Byte0]: 52
3246 23:06:17.024135 [Byte1]: 52
3247 23:06:17.028884
3248 23:06:17.028954 Set Vref, RX VrefLevel [Byte0]: 53
3249 23:06:17.032097 [Byte1]: 53
3250 23:06:17.036728
3251 23:06:17.036798 Set Vref, RX VrefLevel [Byte0]: 54
3252 23:06:17.040272 [Byte1]: 54
3253 23:06:17.044671
3254 23:06:17.044747 Set Vref, RX VrefLevel [Byte0]: 55
3255 23:06:17.048166 [Byte1]: 55
3256 23:06:17.052741
3257 23:06:17.052814 Set Vref, RX VrefLevel [Byte0]: 56
3258 23:06:17.056330 [Byte1]: 56
3259 23:06:17.060541
3260 23:06:17.060636 Set Vref, RX VrefLevel [Byte0]: 57
3261 23:06:17.064320 [Byte1]: 57
3262 23:06:17.068631
3263 23:06:17.068711 Set Vref, RX VrefLevel [Byte0]: 58
3264 23:06:17.071902 [Byte1]: 58
3265 23:06:17.076579
3266 23:06:17.076658 Set Vref, RX VrefLevel [Byte0]: 59
3267 23:06:17.079912 [Byte1]: 59
3268 23:06:17.084930
3269 23:06:17.085009 Set Vref, RX VrefLevel [Byte0]: 60
3270 23:06:17.087843 [Byte1]: 60
3271 23:06:17.092435
3272 23:06:17.092577 Set Vref, RX VrefLevel [Byte0]: 61
3273 23:06:17.095639 [Byte1]: 61
3274 23:06:17.100334
3275 23:06:17.100439 Set Vref, RX VrefLevel [Byte0]: 62
3276 23:06:17.103840 [Byte1]: 62
3277 23:06:17.108418
3278 23:06:17.108560 Set Vref, RX VrefLevel [Byte0]: 63
3279 23:06:17.111689 [Byte1]: 63
3280 23:06:17.116321
3281 23:06:17.116426 Set Vref, RX VrefLevel [Byte0]: 64
3282 23:06:17.119541 [Byte1]: 64
3283 23:06:17.124348
3284 23:06:17.124427 Set Vref, RX VrefLevel [Byte0]: 65
3285 23:06:17.127702 [Byte1]: 65
3286 23:06:17.132300
3287 23:06:17.132406 Set Vref, RX VrefLevel [Byte0]: 66
3288 23:06:17.135627 [Byte1]: 66
3289 23:06:17.140272
3290 23:06:17.140351 Final RX Vref Byte 0 = 57 to rank0
3291 23:06:17.143684 Final RX Vref Byte 1 = 48 to rank0
3292 23:06:17.147213 Final RX Vref Byte 0 = 57 to rank1
3293 23:06:17.150145 Final RX Vref Byte 1 = 48 to rank1==
3294 23:06:17.153556 Dram Type= 6, Freq= 0, CH_1, rank 0
3295 23:06:17.160134 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3296 23:06:17.160218 ==
3297 23:06:17.160282 DQS Delay:
3298 23:06:17.160340 DQS0 = 0, DQS1 = 0
3299 23:06:17.163451 DQM Delay:
3300 23:06:17.163531 DQM0 = 115, DQM1 = 105
3301 23:06:17.166700 DQ Delay:
3302 23:06:17.170188 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =114
3303 23:06:17.173850 DQ4 =114, DQ5 =124, DQ6 =120, DQ7 =114
3304 23:06:17.176931 DQ8 =86, DQ9 =94, DQ10 =110, DQ11 =98
3305 23:06:17.180283 DQ12 =114, DQ13 =116, DQ14 =114, DQ15 =114
3306 23:06:17.180388
3307 23:06:17.180478
3308 23:06:17.186993 [DQSOSCAuto] RK0, (LSB)MR18= 0x1919, (MSB)MR19= 0x404, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
3309 23:06:17.190161 CH1 RK0: MR19=404, MR18=1919
3310 23:06:17.196755 CH1_RK0: MR19=0x404, MR18=0x1919, DQSOSC=400, MR23=63, INC=40, DEC=27
3311 23:06:17.196836
3312 23:06:17.200331 ----->DramcWriteLeveling(PI) begin...
3313 23:06:17.200438 ==
3314 23:06:17.203843 Dram Type= 6, Freq= 0, CH_1, rank 1
3315 23:06:17.207073 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3316 23:06:17.210192 ==
3317 23:06:17.210271 Write leveling (Byte 0): 21 => 21
3318 23:06:17.213731 Write leveling (Byte 1): 22 => 22
3319 23:06:17.216693 DramcWriteLeveling(PI) end<-----
3320 23:06:17.216773
3321 23:06:17.216836 ==
3322 23:06:17.220037 Dram Type= 6, Freq= 0, CH_1, rank 1
3323 23:06:17.226631 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3324 23:06:17.226711 ==
3325 23:06:17.226774 [Gating] SW mode calibration
3326 23:06:17.236590 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3327 23:06:17.239882 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3328 23:06:17.243530 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3329 23:06:17.250173 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3330 23:06:17.253278 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3331 23:06:17.256709 0 11 12 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 0)
3332 23:06:17.263485 0 11 16 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
3333 23:06:17.266690 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3334 23:06:17.270155 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3335 23:06:17.276432 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3336 23:06:17.279904 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3337 23:06:17.283139 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3338 23:06:17.290066 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3339 23:06:17.293208 0 12 12 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
3340 23:06:17.296629 0 12 16 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
3341 23:06:17.303171 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3342 23:06:17.306531 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3343 23:06:17.310172 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3344 23:06:17.316547 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3345 23:06:17.319952 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3346 23:06:17.323124 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3347 23:06:17.330171 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3348 23:06:17.333373 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3349 23:06:17.336687 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3350 23:06:17.343287 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3351 23:06:17.346485 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3352 23:06:17.349753 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3353 23:06:17.356427 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3354 23:06:17.359975 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3355 23:06:17.362904 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3356 23:06:17.366407 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3357 23:06:17.373033 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3358 23:06:17.376216 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3359 23:06:17.379626 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3360 23:06:17.386215 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3361 23:06:17.389916 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3362 23:06:17.393120 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3363 23:06:17.399768 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3364 23:06:17.403062 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3365 23:06:17.406359 Total UI for P1: 0, mck2ui 16
3366 23:06:17.409451 best dqsien dly found for B0: ( 0, 15, 10)
3367 23:06:17.413046 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3368 23:06:17.416211 Total UI for P1: 0, mck2ui 16
3369 23:06:17.419862 best dqsien dly found for B1: ( 0, 15, 14)
3370 23:06:17.422920 best DQS0 dly(MCK, UI, PI) = (0, 15, 10)
3371 23:06:17.426219 best DQS1 dly(MCK, UI, PI) = (0, 15, 14)
3372 23:06:17.429496
3373 23:06:17.432988 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 10)
3374 23:06:17.436105 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 14)
3375 23:06:17.439799 [Gating] SW calibration Done
3376 23:06:17.439878 ==
3377 23:06:17.442986 Dram Type= 6, Freq= 0, CH_1, rank 1
3378 23:06:17.446324 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3379 23:06:17.446404 ==
3380 23:06:17.446467 RX Vref Scan: 0
3381 23:06:17.446526
3382 23:06:17.449530 RX Vref 0 -> 0, step: 1
3383 23:06:17.449609
3384 23:06:17.452770 RX Delay -40 -> 252, step: 8
3385 23:06:17.455955 iDelay=208, Bit 0, Center 119 (48 ~ 191) 144
3386 23:06:17.459457 iDelay=208, Bit 1, Center 115 (40 ~ 191) 152
3387 23:06:17.466022 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3388 23:06:17.469337 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3389 23:06:17.472706 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3390 23:06:17.476066 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3391 23:06:17.479352 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3392 23:06:17.486070 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3393 23:06:17.489510 iDelay=208, Bit 8, Center 91 (16 ~ 167) 152
3394 23:06:17.492704 iDelay=208, Bit 9, Center 91 (16 ~ 167) 152
3395 23:06:17.495991 iDelay=208, Bit 10, Center 103 (32 ~ 175) 144
3396 23:06:17.499387 iDelay=208, Bit 11, Center 103 (32 ~ 175) 144
3397 23:06:17.506234 iDelay=208, Bit 12, Center 115 (40 ~ 191) 152
3398 23:06:17.509373 iDelay=208, Bit 13, Center 115 (40 ~ 191) 152
3399 23:06:17.512681 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3400 23:06:17.516086 iDelay=208, Bit 15, Center 111 (40 ~ 183) 144
3401 23:06:17.516182 ==
3402 23:06:17.519211 Dram Type= 6, Freq= 0, CH_1, rank 1
3403 23:06:17.522555 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3404 23:06:17.526081 ==
3405 23:06:17.526187 DQS Delay:
3406 23:06:17.526283 DQS0 = 0, DQS1 = 0
3407 23:06:17.529176 DQM Delay:
3408 23:06:17.529273 DQM0 = 117, DQM1 = 105
3409 23:06:17.532888 DQ Delay:
3410 23:06:17.536019 DQ0 =119, DQ1 =115, DQ2 =107, DQ3 =115
3411 23:06:17.539130 DQ4 =115, DQ5 =131, DQ6 =123, DQ7 =115
3412 23:06:17.542393 DQ8 =91, DQ9 =91, DQ10 =103, DQ11 =103
3413 23:06:17.545716 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =111
3414 23:06:17.545817
3415 23:06:17.545916
3416 23:06:17.546006 ==
3417 23:06:17.549104 Dram Type= 6, Freq= 0, CH_1, rank 1
3418 23:06:17.552482 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3419 23:06:17.552598 ==
3420 23:06:17.552674
3421 23:06:17.552733
3422 23:06:17.555905 TX Vref Scan disable
3423 23:06:17.559548 == TX Byte 0 ==
3424 23:06:17.562566 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3425 23:06:17.566078 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3426 23:06:17.569553 == TX Byte 1 ==
3427 23:06:17.572738 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3428 23:06:17.576167 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3429 23:06:17.576264 ==
3430 23:06:17.579206 Dram Type= 6, Freq= 0, CH_1, rank 1
3431 23:06:17.582739 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3432 23:06:17.585738 ==
3433 23:06:17.596392 TX Vref=22, minBit 9, minWin=25, winSum=421
3434 23:06:17.599352 TX Vref=24, minBit 9, minWin=25, winSum=424
3435 23:06:17.602870 TX Vref=26, minBit 3, minWin=26, winSum=427
3436 23:06:17.606200 TX Vref=28, minBit 8, minWin=26, winSum=431
3437 23:06:17.609285 TX Vref=30, minBit 9, minWin=26, winSum=432
3438 23:06:17.612768 TX Vref=32, minBit 0, minWin=26, winSum=430
3439 23:06:17.619293 [TxChooseVref] Worse bit 9, Min win 26, Win sum 432, Final Vref 30
3440 23:06:17.619398
3441 23:06:17.622872 Final TX Range 1 Vref 30
3442 23:06:17.622972
3443 23:06:17.623060 ==
3444 23:06:17.626132 Dram Type= 6, Freq= 0, CH_1, rank 1
3445 23:06:17.629168 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3446 23:06:17.629264 ==
3447 23:06:17.629356
3448 23:06:17.632866
3449 23:06:17.632933 TX Vref Scan disable
3450 23:06:17.636209 == TX Byte 0 ==
3451 23:06:17.639277 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3452 23:06:17.642515 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3453 23:06:17.646151 == TX Byte 1 ==
3454 23:06:17.649200 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3455 23:06:17.652657 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3456 23:06:17.652737
3457 23:06:17.655983 [DATLAT]
3458 23:06:17.656078 Freq=1200, CH1 RK1
3459 23:06:17.656165
3460 23:06:17.659201 DATLAT Default: 0xc
3461 23:06:17.659294 0, 0xFFFF, sum = 0
3462 23:06:17.662567 1, 0xFFFF, sum = 0
3463 23:06:17.662674 2, 0xFFFF, sum = 0
3464 23:06:17.665965 3, 0xFFFF, sum = 0
3465 23:06:17.666062 4, 0xFFFF, sum = 0
3466 23:06:17.669176 5, 0xFFFF, sum = 0
3467 23:06:17.669271 6, 0xFFFF, sum = 0
3468 23:06:17.672887 7, 0xFFFF, sum = 0
3469 23:06:17.672962 8, 0xFFFF, sum = 0
3470 23:06:17.676012 9, 0xFFFF, sum = 0
3471 23:06:17.679551 10, 0xFFFF, sum = 0
3472 23:06:17.679655 11, 0x0, sum = 1
3473 23:06:17.679746 12, 0x0, sum = 2
3474 23:06:17.682503 13, 0x0, sum = 3
3475 23:06:17.682571 14, 0x0, sum = 4
3476 23:06:17.685997 best_step = 12
3477 23:06:17.686064
3478 23:06:17.686128 ==
3479 23:06:17.689477 Dram Type= 6, Freq= 0, CH_1, rank 1
3480 23:06:17.692596 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3481 23:06:17.692679 ==
3482 23:06:17.695787 RX Vref Scan: 0
3483 23:06:17.695893
3484 23:06:17.695984 RX Vref 0 -> 0, step: 1
3485 23:06:17.696070
3486 23:06:17.699250 RX Delay -29 -> 252, step: 4
3487 23:06:17.706314 iDelay=199, Bit 0, Center 114 (43 ~ 186) 144
3488 23:06:17.710021 iDelay=199, Bit 1, Center 110 (39 ~ 182) 144
3489 23:06:17.713172 iDelay=199, Bit 2, Center 108 (39 ~ 178) 140
3490 23:06:17.716638 iDelay=199, Bit 3, Center 112 (43 ~ 182) 140
3491 23:06:17.719620 iDelay=199, Bit 4, Center 114 (43 ~ 186) 144
3492 23:06:17.726535 iDelay=199, Bit 5, Center 124 (51 ~ 198) 148
3493 23:06:17.729581 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
3494 23:06:17.732933 iDelay=199, Bit 7, Center 114 (43 ~ 186) 144
3495 23:06:17.736243 iDelay=199, Bit 8, Center 86 (19 ~ 154) 136
3496 23:06:17.739541 iDelay=199, Bit 9, Center 90 (23 ~ 158) 136
3497 23:06:17.745960 iDelay=199, Bit 10, Center 106 (39 ~ 174) 136
3498 23:06:17.749571 iDelay=199, Bit 11, Center 96 (31 ~ 162) 132
3499 23:06:17.752699 iDelay=199, Bit 12, Center 112 (43 ~ 182) 140
3500 23:06:17.756366 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
3501 23:06:17.759404 iDelay=199, Bit 14, Center 112 (43 ~ 182) 140
3502 23:06:17.765989 iDelay=199, Bit 15, Center 112 (47 ~ 178) 132
3503 23:06:17.766069 ==
3504 23:06:17.769249 Dram Type= 6, Freq= 0, CH_1, rank 1
3505 23:06:17.772662 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3506 23:06:17.772735 ==
3507 23:06:17.772800 DQS Delay:
3508 23:06:17.775749 DQS0 = 0, DQS1 = 0
3509 23:06:17.775819 DQM Delay:
3510 23:06:17.779195 DQM0 = 114, DQM1 = 103
3511 23:06:17.779266 DQ Delay:
3512 23:06:17.782352 DQ0 =114, DQ1 =110, DQ2 =108, DQ3 =112
3513 23:06:17.785846 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =114
3514 23:06:17.789106 DQ8 =86, DQ9 =90, DQ10 =106, DQ11 =96
3515 23:06:17.792627 DQ12 =112, DQ13 =112, DQ14 =112, DQ15 =112
3516 23:06:17.792697
3517 23:06:17.792756
3518 23:06:17.802447 [DQSOSCAuto] RK1, (LSB)MR18= 0xa0a, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps
3519 23:06:17.805672 CH1 RK1: MR19=404, MR18=A0A
3520 23:06:17.808930 CH1_RK1: MR19=0x404, MR18=0xA0A, DQSOSC=406, MR23=63, INC=39, DEC=26
3521 23:06:17.812355 [RxdqsGatingPostProcess] freq 1200
3522 23:06:17.819086 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3523 23:06:17.822232 Pre-setting of DQS Precalculation
3524 23:06:17.825745 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3525 23:06:17.835766 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3526 23:06:17.842181 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3527 23:06:17.842282
3528 23:06:17.842372
3529 23:06:17.845521 [Calibration Summary] 2400 Mbps
3530 23:06:17.845616 CH 0, Rank 0
3531 23:06:17.849087 SW Impedance : PASS
3532 23:06:17.849180 DUTY Scan : NO K
3533 23:06:17.852152 ZQ Calibration : PASS
3534 23:06:17.855399 Jitter Meter : NO K
3535 23:06:17.855497 CBT Training : PASS
3536 23:06:17.858656 Write leveling : PASS
3537 23:06:17.862385 RX DQS gating : PASS
3538 23:06:17.862483 RX DQ/DQS(RDDQC) : PASS
3539 23:06:17.865603 TX DQ/DQS : PASS
3540 23:06:17.868702 RX DATLAT : PASS
3541 23:06:17.868799 RX DQ/DQS(Engine): PASS
3542 23:06:17.872136 TX OE : NO K
3543 23:06:17.872232 All Pass.
3544 23:06:17.872319
3545 23:06:17.875330 CH 0, Rank 1
3546 23:06:17.875434 SW Impedance : PASS
3547 23:06:17.878870 DUTY Scan : NO K
3548 23:06:17.882334 ZQ Calibration : PASS
3549 23:06:17.882440 Jitter Meter : NO K
3550 23:06:17.885178 CBT Training : PASS
3551 23:06:17.888744 Write leveling : PASS
3552 23:06:17.888843 RX DQS gating : PASS
3553 23:06:17.891811 RX DQ/DQS(RDDQC) : PASS
3554 23:06:17.895458 TX DQ/DQS : PASS
3555 23:06:17.895555 RX DATLAT : PASS
3556 23:06:17.898526 RX DQ/DQS(Engine): PASS
3557 23:06:17.898628 TX OE : NO K
3558 23:06:17.901866 All Pass.
3559 23:06:17.901963
3560 23:06:17.902050 CH 1, Rank 0
3561 23:06:17.905362 SW Impedance : PASS
3562 23:06:17.905463 DUTY Scan : NO K
3563 23:06:17.908616 ZQ Calibration : PASS
3564 23:06:17.911919 Jitter Meter : NO K
3565 23:06:17.912014 CBT Training : PASS
3566 23:06:17.914958 Write leveling : PASS
3567 23:06:17.918340 RX DQS gating : PASS
3568 23:06:17.918437 RX DQ/DQS(RDDQC) : PASS
3569 23:06:17.921745 TX DQ/DQS : PASS
3570 23:06:17.925345 RX DATLAT : PASS
3571 23:06:17.925440 RX DQ/DQS(Engine): PASS
3572 23:06:17.928205 TX OE : NO K
3573 23:06:17.928307 All Pass.
3574 23:06:17.928395
3575 23:06:17.931994 CH 1, Rank 1
3576 23:06:17.932089 SW Impedance : PASS
3577 23:06:17.935124 DUTY Scan : NO K
3578 23:06:17.938196 ZQ Calibration : PASS
3579 23:06:17.938292 Jitter Meter : NO K
3580 23:06:17.941599 CBT Training : PASS
3581 23:06:17.945108 Write leveling : PASS
3582 23:06:17.945206 RX DQS gating : PASS
3583 23:06:17.948425 RX DQ/DQS(RDDQC) : PASS
3584 23:06:17.951480 TX DQ/DQS : PASS
3585 23:06:17.951557 RX DATLAT : PASS
3586 23:06:17.954757 RX DQ/DQS(Engine): PASS
3587 23:06:17.958214 TX OE : NO K
3588 23:06:17.958317 All Pass.
3589 23:06:17.958404
3590 23:06:17.958489 DramC Write-DBI off
3591 23:06:17.961340 PER_BANK_REFRESH: Hybrid Mode
3592 23:06:17.964866 TX_TRACKING: ON
3593 23:06:17.971336 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3594 23:06:17.974589 [FAST_K] Save calibration result to emmc
3595 23:06:17.981401 dramc_set_vcore_voltage set vcore to 650000
3596 23:06:17.981482 Read voltage for 600, 5
3597 23:06:17.984675 Vio18 = 0
3598 23:06:17.984754 Vcore = 650000
3599 23:06:17.984816 Vdram = 0
3600 23:06:17.984874 Vddq = 0
3601 23:06:17.988025 Vmddr = 0
3602 23:06:17.991053 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3603 23:06:17.997868 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3604 23:06:18.001227 MEM_TYPE=3, freq_sel=19
3605 23:06:18.001307 sv_algorithm_assistance_LP4_1600
3606 23:06:18.007878 ============ PULL DRAM RESETB DOWN ============
3607 23:06:18.011040 ========== PULL DRAM RESETB DOWN end =========
3608 23:06:18.014691 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3609 23:06:18.017856 ===================================
3610 23:06:18.021010 LPDDR4 DRAM CONFIGURATION
3611 23:06:18.024783 ===================================
3612 23:06:18.027734 EX_ROW_EN[0] = 0x0
3613 23:06:18.027814 EX_ROW_EN[1] = 0x0
3614 23:06:18.031077 LP4Y_EN = 0x0
3615 23:06:18.031156 WORK_FSP = 0x0
3616 23:06:18.034521 WL = 0x2
3617 23:06:18.034601 RL = 0x2
3618 23:06:18.038069 BL = 0x2
3619 23:06:18.038151 RPST = 0x0
3620 23:06:18.041154 RD_PRE = 0x0
3621 23:06:18.041235 WR_PRE = 0x1
3622 23:06:18.044973 WR_PST = 0x0
3623 23:06:18.045053 DBI_WR = 0x0
3624 23:06:18.047827 DBI_RD = 0x0
3625 23:06:18.047906 OTF = 0x1
3626 23:06:18.051286 ===================================
3627 23:06:18.054779 ===================================
3628 23:06:18.057996 ANA top config
3629 23:06:18.060889 ===================================
3630 23:06:18.064446 DLL_ASYNC_EN = 0
3631 23:06:18.064588 ALL_SLAVE_EN = 1
3632 23:06:18.067584 NEW_RANK_MODE = 1
3633 23:06:18.071285 DLL_IDLE_MODE = 1
3634 23:06:18.074226 LP45_APHY_COMB_EN = 1
3635 23:06:18.074306 TX_ODT_DIS = 1
3636 23:06:18.077600 NEW_8X_MODE = 1
3637 23:06:18.081008 ===================================
3638 23:06:18.084312 ===================================
3639 23:06:18.087516 data_rate = 1200
3640 23:06:18.091245 CKR = 1
3641 23:06:18.094513 DQ_P2S_RATIO = 8
3642 23:06:18.097432 ===================================
3643 23:06:18.100916 CA_P2S_RATIO = 8
3644 23:06:18.100997 DQ_CA_OPEN = 0
3645 23:06:18.104307 DQ_SEMI_OPEN = 0
3646 23:06:18.107555 CA_SEMI_OPEN = 0
3647 23:06:18.110881 CA_FULL_RATE = 0
3648 23:06:18.114380 DQ_CKDIV4_EN = 1
3649 23:06:18.117507 CA_CKDIV4_EN = 1
3650 23:06:18.117603 CA_PREDIV_EN = 0
3651 23:06:18.120961 PH8_DLY = 0
3652 23:06:18.123979 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3653 23:06:18.127583 DQ_AAMCK_DIV = 4
3654 23:06:18.130639 CA_AAMCK_DIV = 4
3655 23:06:18.134155 CA_ADMCK_DIV = 4
3656 23:06:18.134234 DQ_TRACK_CA_EN = 0
3657 23:06:18.137443 CA_PICK = 600
3658 23:06:18.140650 CA_MCKIO = 600
3659 23:06:18.143844 MCKIO_SEMI = 0
3660 23:06:18.147397 PLL_FREQ = 2288
3661 23:06:18.150490 DQ_UI_PI_RATIO = 32
3662 23:06:18.154126 CA_UI_PI_RATIO = 0
3663 23:06:18.157218 ===================================
3664 23:06:18.160677 ===================================
3665 23:06:18.160782 memory_type:LPDDR4
3666 23:06:18.164229 GP_NUM : 10
3667 23:06:18.167067 SRAM_EN : 1
3668 23:06:18.167147 MD32_EN : 0
3669 23:06:18.170379 ===================================
3670 23:06:18.173753 [ANA_INIT] >>>>>>>>>>>>>>
3671 23:06:18.177246 <<<<<< [CONFIGURE PHASE]: ANA_TX
3672 23:06:18.180477 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3673 23:06:18.183770 ===================================
3674 23:06:18.186942 data_rate = 1200,PCW = 0X5800
3675 23:06:18.190208 ===================================
3676 23:06:18.193729 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3677 23:06:18.197060 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3678 23:06:18.203696 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3679 23:06:18.207080 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3680 23:06:18.210269 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3681 23:06:18.213444 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3682 23:06:18.216880 [ANA_INIT] flow start
3683 23:06:18.220031 [ANA_INIT] PLL >>>>>>>>
3684 23:06:18.220128 [ANA_INIT] PLL <<<<<<<<
3685 23:06:18.223405 [ANA_INIT] MIDPI >>>>>>>>
3686 23:06:18.226956 [ANA_INIT] MIDPI <<<<<<<<
3687 23:06:18.229969 [ANA_INIT] DLL >>>>>>>>
3688 23:06:18.230053 [ANA_INIT] flow end
3689 23:06:18.233617 ============ LP4 DIFF to SE enter ============
3690 23:06:18.239904 ============ LP4 DIFF to SE exit ============
3691 23:06:18.239988 [ANA_INIT] <<<<<<<<<<<<<
3692 23:06:18.243180 [Flow] Enable top DCM control >>>>>
3693 23:06:18.246478 [Flow] Enable top DCM control <<<<<
3694 23:06:18.250083 Enable DLL master slave shuffle
3695 23:06:18.257037 ==============================================================
3696 23:06:18.257117 Gating Mode config
3697 23:06:18.263218 ==============================================================
3698 23:06:18.266887 Config description:
3699 23:06:18.276384 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3700 23:06:18.283037 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3701 23:06:18.286414 SELPH_MODE 0: By rank 1: By Phase
3702 23:06:18.293285 ==============================================================
3703 23:06:18.296290 GAT_TRACK_EN = 1
3704 23:06:18.296370 RX_GATING_MODE = 2
3705 23:06:18.299706 RX_GATING_TRACK_MODE = 2
3706 23:06:18.303060 SELPH_MODE = 1
3707 23:06:18.306271 PICG_EARLY_EN = 1
3708 23:06:18.309883 VALID_LAT_VALUE = 1
3709 23:06:18.316336 ==============================================================
3710 23:06:18.319580 Enter into Gating configuration >>>>
3711 23:06:18.322782 Exit from Gating configuration <<<<
3712 23:06:18.326180 Enter into DVFS_PRE_config >>>>>
3713 23:06:18.336259 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3714 23:06:18.339563 Exit from DVFS_PRE_config <<<<<
3715 23:06:18.342917 Enter into PICG configuration >>>>
3716 23:06:18.346353 Exit from PICG configuration <<<<
3717 23:06:18.349370 [RX_INPUT] configuration >>>>>
3718 23:06:18.352639 [RX_INPUT] configuration <<<<<
3719 23:06:18.356155 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3720 23:06:18.362574 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3721 23:06:18.369187 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3722 23:06:18.375666 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3723 23:06:18.378941 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3724 23:06:18.385907 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3725 23:06:18.389046 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3726 23:06:18.395570 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3727 23:06:18.398988 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3728 23:06:18.402194 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3729 23:06:18.405767 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3730 23:06:18.412107 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3731 23:06:18.415499 ===================================
3732 23:06:18.415591 LPDDR4 DRAM CONFIGURATION
3733 23:06:18.418912 ===================================
3734 23:06:18.422193 EX_ROW_EN[0] = 0x0
3735 23:06:18.425476 EX_ROW_EN[1] = 0x0
3736 23:06:18.425556 LP4Y_EN = 0x0
3737 23:06:18.428651 WORK_FSP = 0x0
3738 23:06:18.428731 WL = 0x2
3739 23:06:18.432011 RL = 0x2
3740 23:06:18.432116 BL = 0x2
3741 23:06:18.435179 RPST = 0x0
3742 23:06:18.435258 RD_PRE = 0x0
3743 23:06:18.438480 WR_PRE = 0x1
3744 23:06:18.438560 WR_PST = 0x0
3745 23:06:18.441924 DBI_WR = 0x0
3746 23:06:18.442004 DBI_RD = 0x0
3747 23:06:18.445343 OTF = 0x1
3748 23:06:18.448463 ===================================
3749 23:06:18.451991 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3750 23:06:18.455103 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3751 23:06:18.462366 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3752 23:06:18.465351 ===================================
3753 23:06:18.465431 LPDDR4 DRAM CONFIGURATION
3754 23:06:18.468720 ===================================
3755 23:06:18.471817 EX_ROW_EN[0] = 0x10
3756 23:06:18.475064 EX_ROW_EN[1] = 0x0
3757 23:06:18.475144 LP4Y_EN = 0x0
3758 23:06:18.478366 WORK_FSP = 0x0
3759 23:06:18.478446 WL = 0x2
3760 23:06:18.481724 RL = 0x2
3761 23:06:18.481804 BL = 0x2
3762 23:06:18.484912 RPST = 0x0
3763 23:06:18.484992 RD_PRE = 0x0
3764 23:06:18.488392 WR_PRE = 0x1
3765 23:06:18.488497 WR_PST = 0x0
3766 23:06:18.491498 DBI_WR = 0x0
3767 23:06:18.491578 DBI_RD = 0x0
3768 23:06:18.495198 OTF = 0x1
3769 23:06:18.498312 ===================================
3770 23:06:18.505110 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3771 23:06:18.508214 nWR fixed to 30
3772 23:06:18.511579 [ModeRegInit_LP4] CH0 RK0
3773 23:06:18.511659 [ModeRegInit_LP4] CH0 RK1
3774 23:06:18.514680 [ModeRegInit_LP4] CH1 RK0
3775 23:06:18.518124 [ModeRegInit_LP4] CH1 RK1
3776 23:06:18.518203 match AC timing 16
3777 23:06:18.524718 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3778 23:06:18.527880 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3779 23:06:18.531328 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3780 23:06:18.537836 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3781 23:06:18.541375 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3782 23:06:18.541455 ==
3783 23:06:18.544664 Dram Type= 6, Freq= 0, CH_0, rank 0
3784 23:06:18.547748 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3785 23:06:18.547829 ==
3786 23:06:18.554431 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3787 23:06:18.561728 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3788 23:06:18.564763 [CA 0] Center 35 (5~66) winsize 62
3789 23:06:18.567782 [CA 1] Center 35 (5~66) winsize 62
3790 23:06:18.571061 [CA 2] Center 34 (4~65) winsize 62
3791 23:06:18.574266 [CA 3] Center 34 (3~65) winsize 63
3792 23:06:18.577588 [CA 4] Center 33 (3~64) winsize 62
3793 23:06:18.581100 [CA 5] Center 33 (3~64) winsize 62
3794 23:06:18.581180
3795 23:06:18.584371 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3796 23:06:18.584481
3797 23:06:18.587538 [CATrainingPosCal] consider 1 rank data
3798 23:06:18.590967 u2DelayCellTimex100 = 270/100 ps
3799 23:06:18.594081 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3800 23:06:18.597429 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3801 23:06:18.600822 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3802 23:06:18.604095 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3803 23:06:18.607318 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3804 23:06:18.613838 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3805 23:06:18.613939
3806 23:06:18.616953 CA PerBit enable=1, Macro0, CA PI delay=33
3807 23:06:18.617050
3808 23:06:18.620240 [CBTSetCACLKResult] CA Dly = 33
3809 23:06:18.620342 CS Dly: 6 (0~37)
3810 23:06:18.620430 ==
3811 23:06:18.623782 Dram Type= 6, Freq= 0, CH_0, rank 1
3812 23:06:18.627155 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3813 23:06:18.630463 ==
3814 23:06:18.633802 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3815 23:06:18.640317 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
3816 23:06:18.643772 [CA 0] Center 35 (5~66) winsize 62
3817 23:06:18.646898 [CA 1] Center 35 (5~66) winsize 62
3818 23:06:18.650269 [CA 2] Center 34 (4~65) winsize 62
3819 23:06:18.654025 [CA 3] Center 34 (4~65) winsize 62
3820 23:06:18.657000 [CA 4] Center 33 (3~64) winsize 62
3821 23:06:18.660139 [CA 5] Center 33 (3~64) winsize 62
3822 23:06:18.660237
3823 23:06:18.663530 [CmdBusTrainingLP45] Vref(ca) range 1: 39
3824 23:06:18.663619
3825 23:06:18.667209 [CATrainingPosCal] consider 2 rank data
3826 23:06:18.670085 u2DelayCellTimex100 = 270/100 ps
3827 23:06:18.673629 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3828 23:06:18.676855 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3829 23:06:18.680012 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3830 23:06:18.686707 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3831 23:06:18.689909 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3832 23:06:18.693434 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3833 23:06:18.693539
3834 23:06:18.696590 CA PerBit enable=1, Macro0, CA PI delay=33
3835 23:06:18.696672
3836 23:06:18.699845 [CBTSetCACLKResult] CA Dly = 33
3837 23:06:18.699944 CS Dly: 5 (0~36)
3838 23:06:18.700033
3839 23:06:18.703054 ----->DramcWriteLeveling(PI) begin...
3840 23:06:18.706441 ==
3841 23:06:18.706542 Dram Type= 6, Freq= 0, CH_0, rank 0
3842 23:06:18.713154 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3843 23:06:18.713231 ==
3844 23:06:18.716389 Write leveling (Byte 0): 30 => 30
3845 23:06:18.719852 Write leveling (Byte 1): 29 => 29
3846 23:06:18.723324 DramcWriteLeveling(PI) end<-----
3847 23:06:18.723429
3848 23:06:18.723520 ==
3849 23:06:18.726501 Dram Type= 6, Freq= 0, CH_0, rank 0
3850 23:06:18.729811 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3851 23:06:18.729912 ==
3852 23:06:18.733110 [Gating] SW mode calibration
3853 23:06:18.739781 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3854 23:06:18.743247 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3855 23:06:18.749897 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3856 23:06:18.753076 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3857 23:06:18.756417 0 5 8 | B1->B0 | 3232 3131 | 1 0 | (1 0) (0 0)
3858 23:06:18.762743 0 5 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3859 23:06:18.766234 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3860 23:06:18.769597 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3861 23:06:18.776529 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3862 23:06:18.779539 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3863 23:06:18.782800 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3864 23:06:18.789418 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3865 23:06:18.792540 0 6 8 | B1->B0 | 2f2f 3131 | 0 1 | (0 0) (0 0)
3866 23:06:18.796020 0 6 12 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
3867 23:06:18.802986 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3868 23:06:18.806179 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3869 23:06:18.809178 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3870 23:06:18.815924 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3871 23:06:18.819364 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3872 23:06:18.822454 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3873 23:06:18.829221 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3874 23:06:18.832458 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3875 23:06:18.836043 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3876 23:06:18.842775 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3877 23:06:18.845990 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3878 23:06:18.849124 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3879 23:06:18.855729 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3880 23:06:18.858855 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3881 23:06:18.862166 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3882 23:06:18.868799 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3883 23:06:18.872366 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3884 23:06:18.875379 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3885 23:06:18.882399 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3886 23:06:18.885589 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3887 23:06:18.888885 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3888 23:06:18.895823 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3889 23:06:18.898638 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3890 23:06:18.902064 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3891 23:06:18.905479 Total UI for P1: 0, mck2ui 16
3892 23:06:18.908619 best dqsien dly found for B0: ( 0, 9, 8)
3893 23:06:18.911995 Total UI for P1: 0, mck2ui 16
3894 23:06:18.915274 best dqsien dly found for B1: ( 0, 9, 10)
3895 23:06:18.918655 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
3896 23:06:18.921836 best DQS1 dly(MCK, UI, PI) = (0, 9, 10)
3897 23:06:18.921940
3898 23:06:18.925233 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
3899 23:06:18.932429 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10)
3900 23:06:18.932536 [Gating] SW calibration Done
3901 23:06:18.932604 ==
3902 23:06:18.935310 Dram Type= 6, Freq= 0, CH_0, rank 0
3903 23:06:18.941706 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3904 23:06:18.941779 ==
3905 23:06:18.941839 RX Vref Scan: 0
3906 23:06:18.941896
3907 23:06:18.945078 RX Vref 0 -> 0, step: 1
3908 23:06:18.945145
3909 23:06:18.948496 RX Delay -230 -> 252, step: 16
3910 23:06:18.951857 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
3911 23:06:18.955036 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
3912 23:06:18.961697 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
3913 23:06:18.964959 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
3914 23:06:18.968354 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
3915 23:06:18.971654 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
3916 23:06:18.974804 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3917 23:06:18.981416 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
3918 23:06:18.984610 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3919 23:06:18.988305 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
3920 23:06:18.991378 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
3921 23:06:18.998161 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3922 23:06:19.001358 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3923 23:06:19.004746 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3924 23:06:19.008149 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3925 23:06:19.014475 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3926 23:06:19.014555 ==
3927 23:06:19.017872 Dram Type= 6, Freq= 0, CH_0, rank 0
3928 23:06:19.021098 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3929 23:06:19.021244 ==
3930 23:06:19.021352 DQS Delay:
3931 23:06:19.024484 DQS0 = 0, DQS1 = 0
3932 23:06:19.024629 DQM Delay:
3933 23:06:19.027832 DQM0 = 39, DQM1 = 33
3934 23:06:19.027912 DQ Delay:
3935 23:06:19.030963 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
3936 23:06:19.034267 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
3937 23:06:19.037697 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
3938 23:06:19.040932 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3939 23:06:19.041014
3940 23:06:19.041086
3941 23:06:19.041150 ==
3942 23:06:19.044189 Dram Type= 6, Freq= 0, CH_0, rank 0
3943 23:06:19.047841 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3944 23:06:19.047922 ==
3945 23:06:19.051077
3946 23:06:19.051156
3947 23:06:19.051219 TX Vref Scan disable
3948 23:06:19.054475 == TX Byte 0 ==
3949 23:06:19.057649 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
3950 23:06:19.060631 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
3951 23:06:19.063975 == TX Byte 1 ==
3952 23:06:19.067415 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
3953 23:06:19.070654 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
3954 23:06:19.073789 ==
3955 23:06:19.077232 Dram Type= 6, Freq= 0, CH_0, rank 0
3956 23:06:19.080662 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3957 23:06:19.080742 ==
3958 23:06:19.080805
3959 23:06:19.080863
3960 23:06:19.083855 TX Vref Scan disable
3961 23:06:19.083935 == TX Byte 0 ==
3962 23:06:19.090319 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
3963 23:06:19.093741 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
3964 23:06:19.093822 == TX Byte 1 ==
3965 23:06:19.100342 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
3966 23:06:19.103850 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
3967 23:06:19.103930
3968 23:06:19.103993 [DATLAT]
3969 23:06:19.106913 Freq=600, CH0 RK0
3970 23:06:19.106993
3971 23:06:19.107056 DATLAT Default: 0x9
3972 23:06:19.110140 0, 0xFFFF, sum = 0
3973 23:06:19.113737 1, 0xFFFF, sum = 0
3974 23:06:19.113819 2, 0xFFFF, sum = 0
3975 23:06:19.116826 3, 0xFFFF, sum = 0
3976 23:06:19.116907 4, 0xFFFF, sum = 0
3977 23:06:19.120303 5, 0xFFFF, sum = 0
3978 23:06:19.120411 6, 0xFFFF, sum = 0
3979 23:06:19.123409 7, 0x0, sum = 1
3980 23:06:19.123500 8, 0x0, sum = 2
3981 23:06:19.123571 9, 0x0, sum = 3
3982 23:06:19.126994 10, 0x0, sum = 4
3983 23:06:19.127075 best_step = 8
3984 23:06:19.127137
3985 23:06:19.127195 ==
3986 23:06:19.130178 Dram Type= 6, Freq= 0, CH_0, rank 0
3987 23:06:19.137355 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3988 23:06:19.137436 ==
3989 23:06:19.137499 RX Vref Scan: 1
3990 23:06:19.137557
3991 23:06:19.140293 RX Vref 0 -> 0, step: 1
3992 23:06:19.140398
3993 23:06:19.143638 RX Delay -195 -> 252, step: 8
3994 23:06:19.143718
3995 23:06:19.146876 Set Vref, RX VrefLevel [Byte0]: 46
3996 23:06:19.150119 [Byte1]: 46
3997 23:06:19.150199
3998 23:06:19.153216 Final RX Vref Byte 0 = 46 to rank0
3999 23:06:19.156715 Final RX Vref Byte 1 = 46 to rank0
4000 23:06:19.159739 Final RX Vref Byte 0 = 46 to rank1
4001 23:06:19.163281 Final RX Vref Byte 1 = 46 to rank1==
4002 23:06:19.166459 Dram Type= 6, Freq= 0, CH_0, rank 0
4003 23:06:19.169726 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4004 23:06:19.169832 ==
4005 23:06:19.173096 DQS Delay:
4006 23:06:19.173176 DQS0 = 0, DQS1 = 0
4007 23:06:19.176641 DQM Delay:
4008 23:06:19.176721 DQM0 = 40, DQM1 = 31
4009 23:06:19.176783 DQ Delay:
4010 23:06:19.179894 DQ0 =36, DQ1 =40, DQ2 =36, DQ3 =36
4011 23:06:19.182981 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4012 23:06:19.186368 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4013 23:06:19.189555 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =44
4014 23:06:19.189636
4015 23:06:19.189698
4016 23:06:19.199175 [DQSOSCAuto] RK0, (LSB)MR18= 0x5757, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
4017 23:06:19.202563 CH0 RK0: MR19=808, MR18=5757
4018 23:06:19.209547 CH0_RK0: MR19=0x808, MR18=0x5757, DQSOSC=393, MR23=63, INC=169, DEC=113
4019 23:06:19.209628
4020 23:06:19.212663 ----->DramcWriteLeveling(PI) begin...
4021 23:06:19.212744 ==
4022 23:06:19.215740 Dram Type= 6, Freq= 0, CH_0, rank 1
4023 23:06:19.219330 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4024 23:06:19.219411 ==
4025 23:06:19.222373 Write leveling (Byte 0): 30 => 30
4026 23:06:19.225934 Write leveling (Byte 1): 28 => 28
4027 23:06:19.229453 DramcWriteLeveling(PI) end<-----
4028 23:06:19.229559
4029 23:06:19.229663 ==
4030 23:06:19.232336 Dram Type= 6, Freq= 0, CH_0, rank 1
4031 23:06:19.235654 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4032 23:06:19.235735 ==
4033 23:06:19.238977 [Gating] SW mode calibration
4034 23:06:19.245829 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4035 23:06:19.252219 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4036 23:06:19.255511 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4037 23:06:19.258741 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4038 23:06:19.265637 0 5 8 | B1->B0 | 3434 3131 | 0 0 | (1 1) (0 0)
4039 23:06:19.268625 0 5 12 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
4040 23:06:19.272319 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4041 23:06:19.278656 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4042 23:06:19.282046 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4043 23:06:19.285379 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4044 23:06:19.291983 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4045 23:06:19.295463 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4046 23:06:19.298490 0 6 8 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (0 0)
4047 23:06:19.305420 0 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4048 23:06:19.308563 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4049 23:06:19.312098 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4050 23:06:19.318379 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4051 23:06:19.321765 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4052 23:06:19.325198 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4053 23:06:19.331666 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4054 23:06:19.335589 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4055 23:06:19.338259 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 23:06:19.344895 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 23:06:19.348337 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 23:06:19.351627 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 23:06:19.357985 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 23:06:19.361675 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 23:06:19.364622 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 23:06:19.371388 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 23:06:19.374549 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 23:06:19.377949 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 23:06:19.384763 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 23:06:19.387803 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 23:06:19.391253 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 23:06:19.397730 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 23:06:19.401142 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 23:06:19.404348 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4071 23:06:19.411492 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4072 23:06:19.411572 Total UI for P1: 0, mck2ui 16
4073 23:06:19.417842 best dqsien dly found for B0: ( 0, 9, 8)
4074 23:06:19.417922 Total UI for P1: 0, mck2ui 16
4075 23:06:19.424277 best dqsien dly found for B1: ( 0, 9, 8)
4076 23:06:19.427651 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
4077 23:06:19.431168 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4078 23:06:19.431247
4079 23:06:19.434654 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
4080 23:06:19.437602 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4081 23:06:19.440895 [Gating] SW calibration Done
4082 23:06:19.440976 ==
4083 23:06:19.444189 Dram Type= 6, Freq= 0, CH_0, rank 1
4084 23:06:19.447461 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4085 23:06:19.447541 ==
4086 23:06:19.451205 RX Vref Scan: 0
4087 23:06:19.451285
4088 23:06:19.451347 RX Vref 0 -> 0, step: 1
4089 23:06:19.451405
4090 23:06:19.454081 RX Delay -230 -> 252, step: 16
4091 23:06:19.457712 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4092 23:06:19.464310 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4093 23:06:19.467441 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4094 23:06:19.470645 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4095 23:06:19.474124 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4096 23:06:19.480696 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4097 23:06:19.484174 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4098 23:06:19.487214 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4099 23:06:19.490579 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4100 23:06:19.493784 iDelay=218, Bit 9, Center 9 (-150 ~ 169) 320
4101 23:06:19.500728 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4102 23:06:19.503878 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4103 23:06:19.507628 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4104 23:06:19.510453 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4105 23:06:19.517331 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4106 23:06:19.520546 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4107 23:06:19.520641 ==
4108 23:06:19.524217 Dram Type= 6, Freq= 0, CH_0, rank 1
4109 23:06:19.527138 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4110 23:06:19.527219 ==
4111 23:06:19.530426 DQS Delay:
4112 23:06:19.530506 DQS0 = 0, DQS1 = 0
4113 23:06:19.530569 DQM Delay:
4114 23:06:19.533771 DQM0 = 43, DQM1 = 32
4115 23:06:19.533851 DQ Delay:
4116 23:06:19.537497 DQ0 =33, DQ1 =49, DQ2 =33, DQ3 =41
4117 23:06:19.540402 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =57
4118 23:06:19.543769 DQ8 =25, DQ9 =9, DQ10 =33, DQ11 =25
4119 23:06:19.547017 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4120 23:06:19.547097
4121 23:06:19.547159
4122 23:06:19.547217 ==
4123 23:06:19.550491 Dram Type= 6, Freq= 0, CH_0, rank 1
4124 23:06:19.556803 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4125 23:06:19.556884 ==
4126 23:06:19.556947
4127 23:06:19.557005
4128 23:06:19.557060 TX Vref Scan disable
4129 23:06:19.561027 == TX Byte 0 ==
4130 23:06:19.564029 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4131 23:06:19.570512 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4132 23:06:19.570592 == TX Byte 1 ==
4133 23:06:19.574258 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4134 23:06:19.580423 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4135 23:06:19.580534 ==
4136 23:06:19.584001 Dram Type= 6, Freq= 0, CH_0, rank 1
4137 23:06:19.587201 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4138 23:06:19.587281 ==
4139 23:06:19.587345
4140 23:06:19.587403
4141 23:06:19.590637 TX Vref Scan disable
4142 23:06:19.590717 == TX Byte 0 ==
4143 23:06:19.597297 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4144 23:06:19.600484 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4145 23:06:19.603666 == TX Byte 1 ==
4146 23:06:19.607409 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4147 23:06:19.610544 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4148 23:06:19.610631
4149 23:06:19.610694 [DATLAT]
4150 23:06:19.613703 Freq=600, CH0 RK1
4151 23:06:19.613785
4152 23:06:19.613865 DATLAT Default: 0x8
4153 23:06:19.617274 0, 0xFFFF, sum = 0
4154 23:06:19.620201 1, 0xFFFF, sum = 0
4155 23:06:19.620282 2, 0xFFFF, sum = 0
4156 23:06:19.623690 3, 0xFFFF, sum = 0
4157 23:06:19.623771 4, 0xFFFF, sum = 0
4158 23:06:19.626983 5, 0xFFFF, sum = 0
4159 23:06:19.627064 6, 0xFFFF, sum = 0
4160 23:06:19.630349 7, 0x0, sum = 1
4161 23:06:19.630435 8, 0x0, sum = 2
4162 23:06:19.630501 9, 0x0, sum = 3
4163 23:06:19.634068 10, 0x0, sum = 4
4164 23:06:19.634149 best_step = 8
4165 23:06:19.634211
4166 23:06:19.634269 ==
4167 23:06:19.636989 Dram Type= 6, Freq= 0, CH_0, rank 1
4168 23:06:19.643648 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4169 23:06:19.643755 ==
4170 23:06:19.643820 RX Vref Scan: 0
4171 23:06:19.643879
4172 23:06:19.647101 RX Vref 0 -> 0, step: 1
4173 23:06:19.647181
4174 23:06:19.650079 RX Delay -195 -> 252, step: 8
4175 23:06:19.653687 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4176 23:06:19.660267 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4177 23:06:19.663237 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4178 23:06:19.666475 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4179 23:06:19.669852 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4180 23:06:19.676431 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4181 23:06:19.679676 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4182 23:06:19.683192 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4183 23:06:19.686287 iDelay=205, Bit 8, Center 24 (-123 ~ 172) 296
4184 23:06:19.692987 iDelay=205, Bit 9, Center 16 (-131 ~ 164) 296
4185 23:06:19.696161 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4186 23:06:19.699491 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4187 23:06:19.703243 iDelay=205, Bit 12, Center 40 (-107 ~ 188) 296
4188 23:06:19.709549 iDelay=205, Bit 13, Center 36 (-115 ~ 188) 304
4189 23:06:19.712775 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4190 23:06:19.716028 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4191 23:06:19.716108 ==
4192 23:06:19.719373 Dram Type= 6, Freq= 0, CH_0, rank 1
4193 23:06:19.722719 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4194 23:06:19.722799 ==
4195 23:06:19.726066 DQS Delay:
4196 23:06:19.726145 DQS0 = 0, DQS1 = 0
4197 23:06:19.729506 DQM Delay:
4198 23:06:19.729586 DQM0 = 40, DQM1 = 32
4199 23:06:19.729648 DQ Delay:
4200 23:06:19.732940 DQ0 =36, DQ1 =40, DQ2 =40, DQ3 =36
4201 23:06:19.735882 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4202 23:06:19.739365 DQ8 =24, DQ9 =16, DQ10 =32, DQ11 =24
4203 23:06:19.742502 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4204 23:06:19.742581
4205 23:06:19.742644
4206 23:06:19.752429 [DQSOSCAuto] RK1, (LSB)MR18= 0x6262, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
4207 23:06:19.755725 CH0 RK1: MR19=808, MR18=6262
4208 23:06:19.762835 CH0_RK1: MR19=0x808, MR18=0x6262, DQSOSC=391, MR23=63, INC=171, DEC=114
4209 23:06:19.765677 [RxdqsGatingPostProcess] freq 600
4210 23:06:19.769087 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4211 23:06:19.772662 Pre-setting of DQS Precalculation
4212 23:06:19.775850 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4213 23:06:19.779222 ==
4214 23:06:19.782326 Dram Type= 6, Freq= 0, CH_1, rank 0
4215 23:06:19.785508 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4216 23:06:19.785595 ==
4217 23:06:19.788878 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4218 23:06:19.795491 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4219 23:06:19.799495 [CA 0] Center 35 (5~66) winsize 62
4220 23:06:19.802790 [CA 1] Center 35 (5~66) winsize 62
4221 23:06:19.806007 [CA 2] Center 33 (3~64) winsize 62
4222 23:06:19.809458 [CA 3] Center 33 (3~64) winsize 62
4223 23:06:19.812724 [CA 4] Center 33 (2~64) winsize 63
4224 23:06:19.816099 [CA 5] Center 33 (2~64) winsize 63
4225 23:06:19.816179
4226 23:06:19.819423 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4227 23:06:19.819503
4228 23:06:19.822800 [CATrainingPosCal] consider 1 rank data
4229 23:06:19.825826 u2DelayCellTimex100 = 270/100 ps
4230 23:06:19.829169 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4231 23:06:19.835909 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4232 23:06:19.839321 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4233 23:06:19.842745 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4234 23:06:19.845733 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
4235 23:06:19.849117 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4236 23:06:19.849226
4237 23:06:19.852523 CA PerBit enable=1, Macro0, CA PI delay=33
4238 23:06:19.852607
4239 23:06:19.855796 [CBTSetCACLKResult] CA Dly = 33
4240 23:06:19.858878 CS Dly: 4 (0~35)
4241 23:06:19.858957 ==
4242 23:06:19.862406 Dram Type= 6, Freq= 0, CH_1, rank 1
4243 23:06:19.865516 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4244 23:06:19.865597 ==
4245 23:06:19.872151 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4246 23:06:19.875713 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4247 23:06:19.879491 [CA 0] Center 35 (5~66) winsize 62
4248 23:06:19.882762 [CA 1] Center 34 (4~65) winsize 62
4249 23:06:19.886709 [CA 2] Center 33 (3~64) winsize 62
4250 23:06:19.889788 [CA 3] Center 33 (3~64) winsize 62
4251 23:06:19.893073 [CA 4] Center 32 (2~63) winsize 62
4252 23:06:19.896425 [CA 5] Center 32 (2~63) winsize 62
4253 23:06:19.896528
4254 23:06:19.899798 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4255 23:06:19.899877
4256 23:06:19.903139 [CATrainingPosCal] consider 2 rank data
4257 23:06:19.906342 u2DelayCellTimex100 = 270/100 ps
4258 23:06:19.909389 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4259 23:06:19.912803 CA1 delay=35 (5~65),Diff = 3 PI (28 cell)
4260 23:06:19.919301 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4261 23:06:19.923151 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4262 23:06:19.925974 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4263 23:06:19.929205 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4264 23:06:19.929285
4265 23:06:19.932490 CA PerBit enable=1, Macro0, CA PI delay=32
4266 23:06:19.932579
4267 23:06:19.936018 [CBTSetCACLKResult] CA Dly = 32
4268 23:06:19.936117 CS Dly: 4 (0~36)
4269 23:06:19.939364
4270 23:06:19.942246 ----->DramcWriteLeveling(PI) begin...
4271 23:06:19.942354 ==
4272 23:06:19.945654 Dram Type= 6, Freq= 0, CH_1, rank 0
4273 23:06:19.948838 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4274 23:06:19.948919 ==
4275 23:06:19.952220 Write leveling (Byte 0): 27 => 27
4276 23:06:19.955879 Write leveling (Byte 1): 27 => 27
4277 23:06:19.958802 DramcWriteLeveling(PI) end<-----
4278 23:06:19.958882
4279 23:06:19.958944 ==
4280 23:06:19.962378 Dram Type= 6, Freq= 0, CH_1, rank 0
4281 23:06:19.965570 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4282 23:06:19.965651 ==
4283 23:06:19.969030 [Gating] SW mode calibration
4284 23:06:19.975487 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4285 23:06:19.981988 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4286 23:06:19.985531 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4287 23:06:19.988992 0 5 4 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
4288 23:06:19.995332 0 5 8 | B1->B0 | 2f2f 2525 | 1 1 | (1 1) (1 0)
4289 23:06:19.998538 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4290 23:06:20.002092 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4291 23:06:20.008451 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4292 23:06:20.011749 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4293 23:06:20.015256 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4294 23:06:20.022116 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4295 23:06:20.025004 0 6 4 | B1->B0 | 2323 3333 | 0 1 | (0 0) (0 0)
4296 23:06:20.028253 0 6 8 | B1->B0 | 3434 4242 | 0 0 | (1 1) (0 0)
4297 23:06:20.035208 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4298 23:06:20.038244 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4299 23:06:20.041627 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4300 23:06:20.047995 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4301 23:06:20.051409 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4302 23:06:20.054899 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4303 23:06:20.061357 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4304 23:06:20.064929 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4305 23:06:20.068187 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4306 23:06:20.074924 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4307 23:06:20.078071 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4308 23:06:20.081632 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4309 23:06:20.088135 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4310 23:06:20.091052 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4311 23:06:20.094776 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4312 23:06:20.101461 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4313 23:06:20.104686 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4314 23:06:20.107859 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4315 23:06:20.114643 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4316 23:06:20.117484 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4317 23:06:20.120884 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4318 23:06:20.127686 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4319 23:06:20.130941 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4320 23:06:20.134473 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4321 23:06:20.137360 Total UI for P1: 0, mck2ui 16
4322 23:06:20.140867 best dqsien dly found for B0: ( 0, 9, 4)
4323 23:06:20.144076 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4324 23:06:20.147374 Total UI for P1: 0, mck2ui 16
4325 23:06:20.150636 best dqsien dly found for B1: ( 0, 9, 8)
4326 23:06:20.153944 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
4327 23:06:20.157333 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4328 23:06:20.160665
4329 23:06:20.164364 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
4330 23:06:20.167232 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4331 23:06:20.170482 [Gating] SW calibration Done
4332 23:06:20.170562 ==
4333 23:06:20.173869 Dram Type= 6, Freq= 0, CH_1, rank 0
4334 23:06:20.177410 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4335 23:06:20.177491 ==
4336 23:06:20.177554 RX Vref Scan: 0
4337 23:06:20.180418
4338 23:06:20.180558 RX Vref 0 -> 0, step: 1
4339 23:06:20.180629
4340 23:06:20.184089 RX Delay -230 -> 252, step: 16
4341 23:06:20.187310 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4342 23:06:20.193736 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4343 23:06:20.197218 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4344 23:06:20.200351 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4345 23:06:20.203607 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4346 23:06:20.207194 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4347 23:06:20.213398 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4348 23:06:20.216814 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4349 23:06:20.220187 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4350 23:06:20.223304 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4351 23:06:20.229900 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4352 23:06:20.233473 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4353 23:06:20.236702 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4354 23:06:20.240081 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4355 23:06:20.246596 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4356 23:06:20.250238 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4357 23:06:20.250343 ==
4358 23:06:20.253300 Dram Type= 6, Freq= 0, CH_1, rank 0
4359 23:06:20.256363 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4360 23:06:20.256471 ==
4361 23:06:20.259632 DQS Delay:
4362 23:06:20.259711 DQS0 = 0, DQS1 = 0
4363 23:06:20.259773 DQM Delay:
4364 23:06:20.263148 DQM0 = 39, DQM1 = 34
4365 23:06:20.263227 DQ Delay:
4366 23:06:20.266466 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4367 23:06:20.269558 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4368 23:06:20.272952 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4369 23:06:20.276361 DQ12 =41, DQ13 =49, DQ14 =33, DQ15 =49
4370 23:06:20.276465
4371 23:06:20.276586
4372 23:06:20.276654 ==
4373 23:06:20.279529 Dram Type= 6, Freq= 0, CH_1, rank 0
4374 23:06:20.286010 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4375 23:06:20.286090 ==
4376 23:06:20.286153
4377 23:06:20.286210
4378 23:06:20.286266 TX Vref Scan disable
4379 23:06:20.290130 == TX Byte 0 ==
4380 23:06:20.293273 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4381 23:06:20.300077 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4382 23:06:20.300157 == TX Byte 1 ==
4383 23:06:20.303225 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4384 23:06:20.309817 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4385 23:06:20.309897 ==
4386 23:06:20.313331 Dram Type= 6, Freq= 0, CH_1, rank 0
4387 23:06:20.316297 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4388 23:06:20.316377 ==
4389 23:06:20.316439
4390 23:06:20.316496
4391 23:06:20.319670 TX Vref Scan disable
4392 23:06:20.323302 == TX Byte 0 ==
4393 23:06:20.326750 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4394 23:06:20.329547 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4395 23:06:20.333143 == TX Byte 1 ==
4396 23:06:20.336502 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4397 23:06:20.339405 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4398 23:06:20.339484
4399 23:06:20.339546 [DATLAT]
4400 23:06:20.343012 Freq=600, CH1 RK0
4401 23:06:20.343091
4402 23:06:20.346301 DATLAT Default: 0x9
4403 23:06:20.346382 0, 0xFFFF, sum = 0
4404 23:06:20.349384 1, 0xFFFF, sum = 0
4405 23:06:20.349464 2, 0xFFFF, sum = 0
4406 23:06:20.352873 3, 0xFFFF, sum = 0
4407 23:06:20.352954 4, 0xFFFF, sum = 0
4408 23:06:20.356145 5, 0xFFFF, sum = 0
4409 23:06:20.356225 6, 0xFFFF, sum = 0
4410 23:06:20.359396 7, 0x0, sum = 1
4411 23:06:20.359477 8, 0x0, sum = 2
4412 23:06:20.359539 9, 0x0, sum = 3
4413 23:06:20.362787 10, 0x0, sum = 4
4414 23:06:20.362867 best_step = 8
4415 23:06:20.362930
4416 23:06:20.366231 ==
4417 23:06:20.366309 Dram Type= 6, Freq= 0, CH_1, rank 0
4418 23:06:20.372788 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4419 23:06:20.372867 ==
4420 23:06:20.372930 RX Vref Scan: 1
4421 23:06:20.372988
4422 23:06:20.376125 RX Vref 0 -> 0, step: 1
4423 23:06:20.376203
4424 23:06:20.379245 RX Delay -195 -> 252, step: 8
4425 23:06:20.379325
4426 23:06:20.382724 Set Vref, RX VrefLevel [Byte0]: 57
4427 23:06:20.385921 [Byte1]: 48
4428 23:06:20.386000
4429 23:06:20.389202 Final RX Vref Byte 0 = 57 to rank0
4430 23:06:20.392400 Final RX Vref Byte 1 = 48 to rank0
4431 23:06:20.395938 Final RX Vref Byte 0 = 57 to rank1
4432 23:06:20.399097 Final RX Vref Byte 1 = 48 to rank1==
4433 23:06:20.402496 Dram Type= 6, Freq= 0, CH_1, rank 0
4434 23:06:20.405870 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4435 23:06:20.408934 ==
4436 23:06:20.409013 DQS Delay:
4437 23:06:20.409075 DQS0 = 0, DQS1 = 0
4438 23:06:20.412432 DQM Delay:
4439 23:06:20.412541 DQM0 = 37, DQM1 = 31
4440 23:06:20.415701 DQ Delay:
4441 23:06:20.415780 DQ0 =44, DQ1 =32, DQ2 =28, DQ3 =36
4442 23:06:20.419084 DQ4 =36, DQ5 =44, DQ6 =44, DQ7 =36
4443 23:06:20.422241 DQ8 =12, DQ9 =20, DQ10 =32, DQ11 =24
4444 23:06:20.425688 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4445 23:06:20.425768
4446 23:06:20.429089
4447 23:06:20.435583 [DQSOSCAuto] RK0, (LSB)MR18= 0x7e7e, (MSB)MR19= 0x808, tDQSOscB0 = 386 ps tDQSOscB1 = 386 ps
4448 23:06:20.438981 CH1 RK0: MR19=808, MR18=7E7E
4449 23:06:20.445430 CH1_RK0: MR19=0x808, MR18=0x7E7E, DQSOSC=386, MR23=63, INC=176, DEC=117
4450 23:06:20.445511
4451 23:06:20.448911 ----->DramcWriteLeveling(PI) begin...
4452 23:06:20.448992 ==
4453 23:06:20.452180 Dram Type= 6, Freq= 0, CH_1, rank 1
4454 23:06:20.455577 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4455 23:06:20.455657 ==
4456 23:06:20.458733 Write leveling (Byte 0): 30 => 30
4457 23:06:20.461985 Write leveling (Byte 1): 30 => 30
4458 23:06:20.465194 DramcWriteLeveling(PI) end<-----
4459 23:06:20.465274
4460 23:06:20.465336 ==
4461 23:06:20.468446 Dram Type= 6, Freq= 0, CH_1, rank 1
4462 23:06:20.471935 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4463 23:06:20.472017 ==
4464 23:06:20.475243 [Gating] SW mode calibration
4465 23:06:20.481767 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4466 23:06:20.488349 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4467 23:06:20.491831 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4468 23:06:20.494968 0 5 4 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
4469 23:06:20.501585 0 5 8 | B1->B0 | 2f2f 2323 | 1 0 | (1 1) (1 0)
4470 23:06:20.504964 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4471 23:06:20.508199 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4472 23:06:20.514928 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4473 23:06:20.518086 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4474 23:06:20.521772 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4475 23:06:20.528403 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4476 23:06:20.531617 0 6 4 | B1->B0 | 2626 3232 | 0 0 | (0 0) (0 0)
4477 23:06:20.535263 0 6 8 | B1->B0 | 3939 4545 | 0 0 | (0 0) (0 0)
4478 23:06:20.541421 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4479 23:06:20.544638 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4480 23:06:20.547875 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4481 23:06:20.554865 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4482 23:06:20.557782 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4483 23:06:20.561368 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4484 23:06:20.567853 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4485 23:06:20.571523 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4486 23:06:20.574265 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 23:06:20.581085 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 23:06:20.584242 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 23:06:20.587600 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 23:06:20.594188 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 23:06:20.597510 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 23:06:20.600929 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 23:06:20.607282 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 23:06:20.610764 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 23:06:20.613898 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 23:06:20.620797 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 23:06:20.623920 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 23:06:20.627295 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 23:06:20.634241 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 23:06:20.637334 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4501 23:06:20.640484 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4502 23:06:20.643792 Total UI for P1: 0, mck2ui 16
4503 23:06:20.647132 best dqsien dly found for B0: ( 0, 9, 4)
4504 23:06:20.653762 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4505 23:06:20.653842 Total UI for P1: 0, mck2ui 16
4506 23:06:20.660309 best dqsien dly found for B1: ( 0, 9, 8)
4507 23:06:20.663600 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
4508 23:06:20.666771 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4509 23:06:20.666850
4510 23:06:20.670000 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
4511 23:06:20.673457 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4512 23:06:20.676927 [Gating] SW calibration Done
4513 23:06:20.677007 ==
4514 23:06:20.680390 Dram Type= 6, Freq= 0, CH_1, rank 1
4515 23:06:20.683292 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4516 23:06:20.683372 ==
4517 23:06:20.686610 RX Vref Scan: 0
4518 23:06:20.686690
4519 23:06:20.686752 RX Vref 0 -> 0, step: 1
4520 23:06:20.686810
4521 23:06:20.690300 RX Delay -230 -> 252, step: 16
4522 23:06:20.696705 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4523 23:06:20.699884 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4524 23:06:20.703181 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4525 23:06:20.706713 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4526 23:06:20.709834 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4527 23:06:20.716440 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4528 23:06:20.719948 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4529 23:06:20.723103 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4530 23:06:20.726464 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4531 23:06:20.732951 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4532 23:06:20.736331 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4533 23:06:20.739815 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4534 23:06:20.743082 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4535 23:06:20.749635 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4536 23:06:20.753006 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4537 23:06:20.756375 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4538 23:06:20.756481 ==
4539 23:06:20.759448 Dram Type= 6, Freq= 0, CH_1, rank 1
4540 23:06:20.762800 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4541 23:06:20.762881 ==
4542 23:06:20.766185 DQS Delay:
4543 23:06:20.766264 DQS0 = 0, DQS1 = 0
4544 23:06:20.769630 DQM Delay:
4545 23:06:20.769711 DQM0 = 40, DQM1 = 34
4546 23:06:20.769774 DQ Delay:
4547 23:06:20.772780 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =41
4548 23:06:20.776031 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =33
4549 23:06:20.779422 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4550 23:06:20.782687 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41
4551 23:06:20.782767
4552 23:06:20.782830
4553 23:06:20.785965 ==
4554 23:06:20.789236 Dram Type= 6, Freq= 0, CH_1, rank 1
4555 23:06:20.792871 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4556 23:06:20.792952 ==
4557 23:06:20.793015
4558 23:06:20.793073
4559 23:06:20.795913 TX Vref Scan disable
4560 23:06:20.795993 == TX Byte 0 ==
4561 23:06:20.802435 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4562 23:06:20.805931 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4563 23:06:20.806011 == TX Byte 1 ==
4564 23:06:20.812340 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4565 23:06:20.815628 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4566 23:06:20.815714 ==
4567 23:06:20.819516 Dram Type= 6, Freq= 0, CH_1, rank 1
4568 23:06:20.822445 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4569 23:06:20.822526 ==
4570 23:06:20.822589
4571 23:06:20.822647
4572 23:06:20.825658 TX Vref Scan disable
4573 23:06:20.828945 == TX Byte 0 ==
4574 23:06:20.832728 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4575 23:06:20.835613 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4576 23:06:20.838959 == TX Byte 1 ==
4577 23:06:20.842267 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4578 23:06:20.845548 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4579 23:06:20.845627
4580 23:06:20.848783 [DATLAT]
4581 23:06:20.848863 Freq=600, CH1 RK1
4582 23:06:20.848927
4583 23:06:20.852179 DATLAT Default: 0x8
4584 23:06:20.852258 0, 0xFFFF, sum = 0
4585 23:06:20.855413 1, 0xFFFF, sum = 0
4586 23:06:20.855495 2, 0xFFFF, sum = 0
4587 23:06:20.858807 3, 0xFFFF, sum = 0
4588 23:06:20.858889 4, 0xFFFF, sum = 0
4589 23:06:20.862240 5, 0xFFFF, sum = 0
4590 23:06:20.862321 6, 0xFFFF, sum = 0
4591 23:06:20.865306 7, 0x0, sum = 1
4592 23:06:20.865403 8, 0x0, sum = 2
4593 23:06:20.868688 9, 0x0, sum = 3
4594 23:06:20.868769 10, 0x0, sum = 4
4595 23:06:20.872155 best_step = 8
4596 23:06:20.872259
4597 23:06:20.872324 ==
4598 23:06:20.875078 Dram Type= 6, Freq= 0, CH_1, rank 1
4599 23:06:20.878720 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4600 23:06:20.878801 ==
4601 23:06:20.881930 RX Vref Scan: 0
4602 23:06:20.882010
4603 23:06:20.882073 RX Vref 0 -> 0, step: 1
4604 23:06:20.882130
4605 23:06:20.885210 RX Delay -195 -> 252, step: 8
4606 23:06:20.892096 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4607 23:06:20.895567 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4608 23:06:20.898862 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4609 23:06:20.902439 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4610 23:06:20.908490 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4611 23:06:20.911925 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4612 23:06:20.915670 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4613 23:06:20.918709 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4614 23:06:20.925000 iDelay=205, Bit 8, Center 16 (-139 ~ 172) 312
4615 23:06:20.928381 iDelay=205, Bit 9, Center 16 (-147 ~ 180) 328
4616 23:06:20.931556 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4617 23:06:20.934927 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4618 23:06:20.941519 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4619 23:06:20.945103 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4620 23:06:20.948278 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4621 23:06:20.951664 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4622 23:06:20.951744 ==
4623 23:06:20.954801 Dram Type= 6, Freq= 0, CH_1, rank 1
4624 23:06:20.961605 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4625 23:06:20.961686 ==
4626 23:06:20.961749 DQS Delay:
4627 23:06:20.961807 DQS0 = 0, DQS1 = 0
4628 23:06:20.964737 DQM Delay:
4629 23:06:20.964852 DQM0 = 37, DQM1 = 29
4630 23:06:20.968256 DQ Delay:
4631 23:06:20.971370 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4632 23:06:20.974898 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4633 23:06:20.978381 DQ8 =16, DQ9 =16, DQ10 =28, DQ11 =20
4634 23:06:20.981322 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40
4635 23:06:20.981402
4636 23:06:20.981465
4637 23:06:20.988180 [DQSOSCAuto] RK1, (LSB)MR18= 0x6060, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
4638 23:06:20.991901 CH1 RK1: MR19=808, MR18=6060
4639 23:06:20.997912 CH1_RK1: MR19=0x808, MR18=0x6060, DQSOSC=391, MR23=63, INC=171, DEC=114
4640 23:06:21.001370 [RxdqsGatingPostProcess] freq 600
4641 23:06:21.004438 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4642 23:06:21.008108 Pre-setting of DQS Precalculation
4643 23:06:21.014483 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4644 23:06:21.021258 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4645 23:06:21.028097 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4646 23:06:21.028203
4647 23:06:21.028293
4648 23:06:21.031384 [Calibration Summary] 1200 Mbps
4649 23:06:21.031464 CH 0, Rank 0
4650 23:06:21.034712 SW Impedance : PASS
4651 23:06:21.037982 DUTY Scan : NO K
4652 23:06:21.038063 ZQ Calibration : PASS
4653 23:06:21.041315 Jitter Meter : NO K
4654 23:06:21.044804 CBT Training : PASS
4655 23:06:21.044884 Write leveling : PASS
4656 23:06:21.047746 RX DQS gating : PASS
4657 23:06:21.051128 RX DQ/DQS(RDDQC) : PASS
4658 23:06:21.051208 TX DQ/DQS : PASS
4659 23:06:21.054431 RX DATLAT : PASS
4660 23:06:21.054511 RX DQ/DQS(Engine): PASS
4661 23:06:21.057850 TX OE : NO K
4662 23:06:21.057930 All Pass.
4663 23:06:21.057994
4664 23:06:21.060941 CH 0, Rank 1
4665 23:06:21.064400 SW Impedance : PASS
4666 23:06:21.064511 DUTY Scan : NO K
4667 23:06:21.067634 ZQ Calibration : PASS
4668 23:06:21.067714 Jitter Meter : NO K
4669 23:06:21.071253 CBT Training : PASS
4670 23:06:21.074295 Write leveling : PASS
4671 23:06:21.074375 RX DQS gating : PASS
4672 23:06:21.077520 RX DQ/DQS(RDDQC) : PASS
4673 23:06:21.081310 TX DQ/DQS : PASS
4674 23:06:21.081392 RX DATLAT : PASS
4675 23:06:21.084246 RX DQ/DQS(Engine): PASS
4676 23:06:21.087620 TX OE : NO K
4677 23:06:21.087701 All Pass.
4678 23:06:21.087763
4679 23:06:21.087821 CH 1, Rank 0
4680 23:06:21.090936 SW Impedance : PASS
4681 23:06:21.094408 DUTY Scan : NO K
4682 23:06:21.094489 ZQ Calibration : PASS
4683 23:06:21.097376 Jitter Meter : NO K
4684 23:06:21.100647 CBT Training : PASS
4685 23:06:21.100726 Write leveling : PASS
4686 23:06:21.104131 RX DQS gating : PASS
4687 23:06:21.107347 RX DQ/DQS(RDDQC) : PASS
4688 23:06:21.107435 TX DQ/DQS : PASS
4689 23:06:21.110767 RX DATLAT : PASS
4690 23:06:21.114093 RX DQ/DQS(Engine): PASS
4691 23:06:21.114173 TX OE : NO K
4692 23:06:21.114237 All Pass.
4693 23:06:21.117355
4694 23:06:21.117434 CH 1, Rank 1
4695 23:06:21.120615 SW Impedance : PASS
4696 23:06:21.120695 DUTY Scan : NO K
4697 23:06:21.123844 ZQ Calibration : PASS
4698 23:06:21.123924 Jitter Meter : NO K
4699 23:06:21.127267 CBT Training : PASS
4700 23:06:21.130695 Write leveling : PASS
4701 23:06:21.130775 RX DQS gating : PASS
4702 23:06:21.134147 RX DQ/DQS(RDDQC) : PASS
4703 23:06:21.137040 TX DQ/DQS : PASS
4704 23:06:21.137121 RX DATLAT : PASS
4705 23:06:21.140664 RX DQ/DQS(Engine): PASS
4706 23:06:21.143830 TX OE : NO K
4707 23:06:21.143910 All Pass.
4708 23:06:21.143973
4709 23:06:21.147104 DramC Write-DBI off
4710 23:06:21.147184 PER_BANK_REFRESH: Hybrid Mode
4711 23:06:21.150511 TX_TRACKING: ON
4712 23:06:21.157041 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4713 23:06:21.163576 [FAST_K] Save calibration result to emmc
4714 23:06:21.166932 dramc_set_vcore_voltage set vcore to 662500
4715 23:06:21.167012 Read voltage for 933, 3
4716 23:06:21.170309 Vio18 = 0
4717 23:06:21.170388 Vcore = 662500
4718 23:06:21.170451 Vdram = 0
4719 23:06:21.173719 Vddq = 0
4720 23:06:21.173799 Vmddr = 0
4721 23:06:21.176882 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4722 23:06:21.183647 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4723 23:06:21.186767 MEM_TYPE=3, freq_sel=17
4724 23:06:21.189996 sv_algorithm_assistance_LP4_1600
4725 23:06:21.193338 ============ PULL DRAM RESETB DOWN ============
4726 23:06:21.196752 ========== PULL DRAM RESETB DOWN end =========
4727 23:06:21.203335 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4728 23:06:21.206598 ===================================
4729 23:06:21.206678 LPDDR4 DRAM CONFIGURATION
4730 23:06:21.209976 ===================================
4731 23:06:21.213446 EX_ROW_EN[0] = 0x0
4732 23:06:21.213529 EX_ROW_EN[1] = 0x0
4733 23:06:21.216455 LP4Y_EN = 0x0
4734 23:06:21.219791 WORK_FSP = 0x0
4735 23:06:21.219871 WL = 0x3
4736 23:06:21.223186 RL = 0x3
4737 23:06:21.223265 BL = 0x2
4738 23:06:21.226485 RPST = 0x0
4739 23:06:21.226565 RD_PRE = 0x0
4740 23:06:21.230114 WR_PRE = 0x1
4741 23:06:21.230193 WR_PST = 0x0
4742 23:06:21.233151 DBI_WR = 0x0
4743 23:06:21.233231 DBI_RD = 0x0
4744 23:06:21.236414 OTF = 0x1
4745 23:06:21.239964 ===================================
4746 23:06:21.243184 ===================================
4747 23:06:21.243265 ANA top config
4748 23:06:21.246399 ===================================
4749 23:06:21.249804 DLL_ASYNC_EN = 0
4750 23:06:21.253008 ALL_SLAVE_EN = 1
4751 23:06:21.253089 NEW_RANK_MODE = 1
4752 23:06:21.256563 DLL_IDLE_MODE = 1
4753 23:06:21.259611 LP45_APHY_COMB_EN = 1
4754 23:06:21.263071 TX_ODT_DIS = 1
4755 23:06:21.266745 NEW_8X_MODE = 1
4756 23:06:21.269512 ===================================
4757 23:06:21.272935 ===================================
4758 23:06:21.273015 data_rate = 1866
4759 23:06:21.276139 CKR = 1
4760 23:06:21.279743 DQ_P2S_RATIO = 8
4761 23:06:21.282779 ===================================
4762 23:06:21.285919 CA_P2S_RATIO = 8
4763 23:06:21.289361 DQ_CA_OPEN = 0
4764 23:06:21.292721 DQ_SEMI_OPEN = 0
4765 23:06:21.292801 CA_SEMI_OPEN = 0
4766 23:06:21.295936 CA_FULL_RATE = 0
4767 23:06:21.299245 DQ_CKDIV4_EN = 1
4768 23:06:21.302846 CA_CKDIV4_EN = 1
4769 23:06:21.305873 CA_PREDIV_EN = 0
4770 23:06:21.309213 PH8_DLY = 0
4771 23:06:21.309294 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4772 23:06:21.312428 DQ_AAMCK_DIV = 4
4773 23:06:21.316102 CA_AAMCK_DIV = 4
4774 23:06:21.319095 CA_ADMCK_DIV = 4
4775 23:06:21.322405 DQ_TRACK_CA_EN = 0
4776 23:06:21.325730 CA_PICK = 933
4777 23:06:21.329105 CA_MCKIO = 933
4778 23:06:21.329185 MCKIO_SEMI = 0
4779 23:06:21.332448 PLL_FREQ = 3732
4780 23:06:21.335709 DQ_UI_PI_RATIO = 32
4781 23:06:21.339186 CA_UI_PI_RATIO = 0
4782 23:06:21.342922 ===================================
4783 23:06:21.345900 ===================================
4784 23:06:21.349276 memory_type:LPDDR4
4785 23:06:21.349355 GP_NUM : 10
4786 23:06:21.352649 SRAM_EN : 1
4787 23:06:21.352729 MD32_EN : 0
4788 23:06:21.356302 ===================================
4789 23:06:21.359128 [ANA_INIT] >>>>>>>>>>>>>>
4790 23:06:21.362556 <<<<<< [CONFIGURE PHASE]: ANA_TX
4791 23:06:21.365602 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4792 23:06:21.368935 ===================================
4793 23:06:21.372211 data_rate = 1866,PCW = 0X8f00
4794 23:06:21.375557 ===================================
4795 23:06:21.379166 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4796 23:06:21.385534 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4797 23:06:21.389020 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4798 23:06:21.395524 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4799 23:06:21.399018 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4800 23:06:21.402424 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4801 23:06:21.402504 [ANA_INIT] flow start
4802 23:06:21.405363 [ANA_INIT] PLL >>>>>>>>
4803 23:06:21.408908 [ANA_INIT] PLL <<<<<<<<
4804 23:06:21.408988 [ANA_INIT] MIDPI >>>>>>>>
4805 23:06:21.412219 [ANA_INIT] MIDPI <<<<<<<<
4806 23:06:21.415598 [ANA_INIT] DLL >>>>>>>>
4807 23:06:21.415678 [ANA_INIT] flow end
4808 23:06:21.421976 ============ LP4 DIFF to SE enter ============
4809 23:06:21.425312 ============ LP4 DIFF to SE exit ============
4810 23:06:21.428439 [ANA_INIT] <<<<<<<<<<<<<
4811 23:06:21.431903 [Flow] Enable top DCM control >>>>>
4812 23:06:21.435053 [Flow] Enable top DCM control <<<<<
4813 23:06:21.435133 Enable DLL master slave shuffle
4814 23:06:21.441713 ==============================================================
4815 23:06:21.445440 Gating Mode config
4816 23:06:21.448162 ==============================================================
4817 23:06:21.451710 Config description:
4818 23:06:21.461567 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4819 23:06:21.468243 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4820 23:06:21.471531 SELPH_MODE 0: By rank 1: By Phase
4821 23:06:21.478219 ==============================================================
4822 23:06:21.481719 GAT_TRACK_EN = 1
4823 23:06:21.484613 RX_GATING_MODE = 2
4824 23:06:21.488025 RX_GATING_TRACK_MODE = 2
4825 23:06:21.491690 SELPH_MODE = 1
4826 23:06:21.495023 PICG_EARLY_EN = 1
4827 23:06:21.495103 VALID_LAT_VALUE = 1
4828 23:06:21.501366 ==============================================================
4829 23:06:21.504706 Enter into Gating configuration >>>>
4830 23:06:21.508005 Exit from Gating configuration <<<<
4831 23:06:21.511416 Enter into DVFS_PRE_config >>>>>
4832 23:06:21.521008 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4833 23:06:21.524414 Exit from DVFS_PRE_config <<<<<
4834 23:06:21.527700 Enter into PICG configuration >>>>
4835 23:06:21.531204 Exit from PICG configuration <<<<
4836 23:06:21.534265 [RX_INPUT] configuration >>>>>
4837 23:06:21.537476 [RX_INPUT] configuration <<<<<
4838 23:06:21.544285 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4839 23:06:21.547594 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4840 23:06:21.554204 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4841 23:06:21.560832 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4842 23:06:21.567550 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4843 23:06:21.573955 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4844 23:06:21.577410 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4845 23:06:21.580587 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4846 23:06:21.584314 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4847 23:06:21.590684 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4848 23:06:21.594240 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4849 23:06:21.597084 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4850 23:06:21.600474 ===================================
4851 23:06:21.603636 LPDDR4 DRAM CONFIGURATION
4852 23:06:21.607020 ===================================
4853 23:06:21.610326 EX_ROW_EN[0] = 0x0
4854 23:06:21.610406 EX_ROW_EN[1] = 0x0
4855 23:06:21.613517 LP4Y_EN = 0x0
4856 23:06:21.613597 WORK_FSP = 0x0
4857 23:06:21.616843 WL = 0x3
4858 23:06:21.616923 RL = 0x3
4859 23:06:21.620212 BL = 0x2
4860 23:06:21.620292 RPST = 0x0
4861 23:06:21.623849 RD_PRE = 0x0
4862 23:06:21.623929 WR_PRE = 0x1
4863 23:06:21.626795 WR_PST = 0x0
4864 23:06:21.626875 DBI_WR = 0x0
4865 23:06:21.630288 DBI_RD = 0x0
4866 23:06:21.630368 OTF = 0x1
4867 23:06:21.633520 ===================================
4868 23:06:21.639871 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4869 23:06:21.643262 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4870 23:06:21.646450 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4871 23:06:21.649933 ===================================
4872 23:06:21.653185 LPDDR4 DRAM CONFIGURATION
4873 23:06:21.656477 ===================================
4874 23:06:21.656573 EX_ROW_EN[0] = 0x10
4875 23:06:21.659879 EX_ROW_EN[1] = 0x0
4876 23:06:21.663288 LP4Y_EN = 0x0
4877 23:06:21.663368 WORK_FSP = 0x0
4878 23:06:21.666736 WL = 0x3
4879 23:06:21.666816 RL = 0x3
4880 23:06:21.669970 BL = 0x2
4881 23:06:21.670050 RPST = 0x0
4882 23:06:21.673145 RD_PRE = 0x0
4883 23:06:21.673252 WR_PRE = 0x1
4884 23:06:21.676473 WR_PST = 0x0
4885 23:06:21.676609 DBI_WR = 0x0
4886 23:06:21.680187 DBI_RD = 0x0
4887 23:06:21.680273 OTF = 0x1
4888 23:06:21.683419 ===================================
4889 23:06:21.689691 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4890 23:06:21.694500 nWR fixed to 30
4891 23:06:21.697573 [ModeRegInit_LP4] CH0 RK0
4892 23:06:21.697652 [ModeRegInit_LP4] CH0 RK1
4893 23:06:21.700811 [ModeRegInit_LP4] CH1 RK0
4894 23:06:21.704254 [ModeRegInit_LP4] CH1 RK1
4895 23:06:21.704334 match AC timing 8
4896 23:06:21.710618 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4897 23:06:21.714221 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4898 23:06:21.717435 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4899 23:06:21.724002 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4900 23:06:21.727365 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4901 23:06:21.727445 ==
4902 23:06:21.730595 Dram Type= 6, Freq= 0, CH_0, rank 0
4903 23:06:21.733736 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4904 23:06:21.733817 ==
4905 23:06:21.740427 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4906 23:06:21.747014 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4907 23:06:21.750335 [CA 0] Center 38 (8~69) winsize 62
4908 23:06:21.753857 [CA 1] Center 38 (8~69) winsize 62
4909 23:06:21.757102 [CA 2] Center 36 (5~67) winsize 63
4910 23:06:21.760266 [CA 3] Center 35 (5~66) winsize 62
4911 23:06:21.763831 [CA 4] Center 34 (4~65) winsize 62
4912 23:06:21.766876 [CA 5] Center 34 (4~65) winsize 62
4913 23:06:21.766956
4914 23:06:21.770273 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4915 23:06:21.770354
4916 23:06:21.773321 [CATrainingPosCal] consider 1 rank data
4917 23:06:21.776790 u2DelayCellTimex100 = 270/100 ps
4918 23:06:21.780216 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4919 23:06:21.783669 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4920 23:06:21.787304 CA2 delay=36 (5~67),Diff = 2 PI (12 cell)
4921 23:06:21.790506 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
4922 23:06:21.793662 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4923 23:06:21.800047 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4924 23:06:21.800128
4925 23:06:21.803508 CA PerBit enable=1, Macro0, CA PI delay=34
4926 23:06:21.803588
4927 23:06:21.806767 [CBTSetCACLKResult] CA Dly = 34
4928 23:06:21.806848 CS Dly: 7 (0~38)
4929 23:06:21.806911 ==
4930 23:06:21.810088 Dram Type= 6, Freq= 0, CH_0, rank 1
4931 23:06:21.813189 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4932 23:06:21.816642 ==
4933 23:06:21.819763 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4934 23:06:21.826390 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4935 23:06:21.829913 [CA 0] Center 38 (8~69) winsize 62
4936 23:06:21.833088 [CA 1] Center 38 (8~69) winsize 62
4937 23:06:21.836382 [CA 2] Center 36 (5~67) winsize 63
4938 23:06:21.839494 [CA 3] Center 35 (5~66) winsize 62
4939 23:06:21.842817 [CA 4] Center 34 (3~65) winsize 63
4940 23:06:21.846292 [CA 5] Center 34 (3~65) winsize 63
4941 23:06:21.846373
4942 23:06:21.849395 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4943 23:06:21.849475
4944 23:06:21.852691 [CATrainingPosCal] consider 2 rank data
4945 23:06:21.856133 u2DelayCellTimex100 = 270/100 ps
4946 23:06:21.859155 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4947 23:06:21.862807 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4948 23:06:21.869210 CA2 delay=36 (5~67),Diff = 2 PI (12 cell)
4949 23:06:21.872763 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
4950 23:06:21.875778 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4951 23:06:21.879468 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4952 23:06:21.879548
4953 23:06:21.882867 CA PerBit enable=1, Macro0, CA PI delay=34
4954 23:06:21.882995
4955 23:06:21.885914 [CBTSetCACLKResult] CA Dly = 34
4956 23:06:21.885995 CS Dly: 7 (0~39)
4957 23:06:21.886059
4958 23:06:21.889205 ----->DramcWriteLeveling(PI) begin...
4959 23:06:21.892420 ==
4960 23:06:21.895801 Dram Type= 6, Freq= 0, CH_0, rank 0
4961 23:06:21.898953 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4962 23:06:21.899065 ==
4963 23:06:21.902606 Write leveling (Byte 0): 28 => 28
4964 23:06:21.905717 Write leveling (Byte 1): 28 => 28
4965 23:06:21.908966 DramcWriteLeveling(PI) end<-----
4966 23:06:21.909066
4967 23:06:21.909156 ==
4968 23:06:21.912255 Dram Type= 6, Freq= 0, CH_0, rank 0
4969 23:06:21.915412 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4970 23:06:21.915518 ==
4971 23:06:21.919107 [Gating] SW mode calibration
4972 23:06:21.925423 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4973 23:06:21.931969 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4974 23:06:21.935161 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4975 23:06:21.938687 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4976 23:06:21.945196 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4977 23:06:21.948661 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4978 23:06:21.951843 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4979 23:06:21.958357 0 10 20 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
4980 23:06:21.961616 0 10 24 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
4981 23:06:21.964951 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4982 23:06:21.971584 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4983 23:06:21.975004 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4984 23:06:21.978097 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4985 23:06:21.984860 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4986 23:06:21.987910 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4987 23:06:21.991348 0 11 20 | B1->B0 | 2424 2e2e | 0 0 | (0 0) (1 1)
4988 23:06:21.997913 0 11 24 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
4989 23:06:22.001497 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4990 23:06:22.004667 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4991 23:06:22.011595 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4992 23:06:22.014548 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4993 23:06:22.018230 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4994 23:06:22.024923 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4995 23:06:22.028011 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4996 23:06:22.031302 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4997 23:06:22.034570 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4998 23:06:22.041121 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4999 23:06:22.044427 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5000 23:06:22.047672 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5001 23:06:22.054576 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5002 23:06:22.057967 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5003 23:06:22.061325 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5004 23:06:22.068074 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5005 23:06:22.071149 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5006 23:06:22.074992 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5007 23:06:22.080914 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5008 23:06:22.084260 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5009 23:06:22.087552 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5010 23:06:22.094319 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5011 23:06:22.097659 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5012 23:06:22.101311 Total UI for P1: 0, mck2ui 16
5013 23:06:22.104174 best dqsien dly found for B0: ( 0, 14, 18)
5014 23:06:22.107440 Total UI for P1: 0, mck2ui 16
5015 23:06:22.110984 best dqsien dly found for B1: ( 0, 14, 18)
5016 23:06:22.114084 best DQS0 dly(MCK, UI, PI) = (0, 14, 18)
5017 23:06:22.117378 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5018 23:06:22.117458
5019 23:06:22.120892 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 18)
5020 23:06:22.124053 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5021 23:06:22.127467 [Gating] SW calibration Done
5022 23:06:22.127547 ==
5023 23:06:22.130793 Dram Type= 6, Freq= 0, CH_0, rank 0
5024 23:06:22.137346 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5025 23:06:22.137427 ==
5026 23:06:22.137489 RX Vref Scan: 0
5027 23:06:22.137548
5028 23:06:22.140461 RX Vref 0 -> 0, step: 1
5029 23:06:22.140561
5030 23:06:22.143791 RX Delay -80 -> 252, step: 8
5031 23:06:22.147110 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5032 23:06:22.150386 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5033 23:06:22.153825 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5034 23:06:22.157293 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5035 23:06:22.163948 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5036 23:06:22.167350 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5037 23:06:22.170447 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5038 23:06:22.173581 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5039 23:06:22.176885 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5040 23:06:22.180138 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5041 23:06:22.186982 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5042 23:06:22.190311 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5043 23:06:22.193708 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5044 23:06:22.196879 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5045 23:06:22.200217 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5046 23:06:22.207153 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5047 23:06:22.207233 ==
5048 23:06:22.210355 Dram Type= 6, Freq= 0, CH_0, rank 0
5049 23:06:22.213590 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5050 23:06:22.213670 ==
5051 23:06:22.213734 DQS Delay:
5052 23:06:22.216668 DQS0 = 0, DQS1 = 0
5053 23:06:22.216747 DQM Delay:
5054 23:06:22.220174 DQM0 = 95, DQM1 = 83
5055 23:06:22.220269 DQ Delay:
5056 23:06:22.223420 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5057 23:06:22.226769 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =103
5058 23:06:22.230005 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =75
5059 23:06:22.233259 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5060 23:06:22.233339
5061 23:06:22.233401
5062 23:06:22.233459 ==
5063 23:06:22.237011 Dram Type= 6, Freq= 0, CH_0, rank 0
5064 23:06:22.239951 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5065 23:06:22.243324 ==
5066 23:06:22.243404
5067 23:06:22.243467
5068 23:06:22.243525 TX Vref Scan disable
5069 23:06:22.246673 == TX Byte 0 ==
5070 23:06:22.250172 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5071 23:06:22.253607 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5072 23:06:22.256642 == TX Byte 1 ==
5073 23:06:22.259773 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5074 23:06:22.263558 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5075 23:06:22.266735 ==
5076 23:06:22.266816 Dram Type= 6, Freq= 0, CH_0, rank 0
5077 23:06:22.273274 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5078 23:06:22.273358 ==
5079 23:06:22.273443
5080 23:06:22.273522
5081 23:06:22.276313 TX Vref Scan disable
5082 23:06:22.276396 == TX Byte 0 ==
5083 23:06:22.282855 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5084 23:06:22.286147 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5085 23:06:22.286231 == TX Byte 1 ==
5086 23:06:22.292688 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5087 23:06:22.296275 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5088 23:06:22.296363
5089 23:06:22.296449 [DATLAT]
5090 23:06:22.299447 Freq=933, CH0 RK0
5091 23:06:22.299531
5092 23:06:22.299619 DATLAT Default: 0xd
5093 23:06:22.302633 0, 0xFFFF, sum = 0
5094 23:06:22.302718 1, 0xFFFF, sum = 0
5095 23:06:22.306172 2, 0xFFFF, sum = 0
5096 23:06:22.306254 3, 0xFFFF, sum = 0
5097 23:06:22.309472 4, 0xFFFF, sum = 0
5098 23:06:22.309554 5, 0xFFFF, sum = 0
5099 23:06:22.312631 6, 0xFFFF, sum = 0
5100 23:06:22.315863 7, 0xFFFF, sum = 0
5101 23:06:22.315945 8, 0xFFFF, sum = 0
5102 23:06:22.319425 9, 0xFFFF, sum = 0
5103 23:06:22.319506 10, 0x0, sum = 1
5104 23:06:22.319571 11, 0x0, sum = 2
5105 23:06:22.322522 12, 0x0, sum = 3
5106 23:06:22.322604 13, 0x0, sum = 4
5107 23:06:22.325905 best_step = 11
5108 23:06:22.325986
5109 23:06:22.326049 ==
5110 23:06:22.329152 Dram Type= 6, Freq= 0, CH_0, rank 0
5111 23:06:22.332642 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5112 23:06:22.332724 ==
5113 23:06:22.335976 RX Vref Scan: 1
5114 23:06:22.336057
5115 23:06:22.336120 RX Vref 0 -> 0, step: 1
5116 23:06:22.339106
5117 23:06:22.339187 RX Delay -69 -> 252, step: 4
5118 23:06:22.339251
5119 23:06:22.342344 Set Vref, RX VrefLevel [Byte0]: 46
5120 23:06:22.345730 [Byte1]: 46
5121 23:06:22.350466
5122 23:06:22.350546 Final RX Vref Byte 0 = 46 to rank0
5123 23:06:22.353954 Final RX Vref Byte 1 = 46 to rank0
5124 23:06:22.356968 Final RX Vref Byte 0 = 46 to rank1
5125 23:06:22.360227 Final RX Vref Byte 1 = 46 to rank1==
5126 23:06:22.363855 Dram Type= 6, Freq= 0, CH_0, rank 0
5127 23:06:22.369956 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5128 23:06:22.370037 ==
5129 23:06:22.370101 DQS Delay:
5130 23:06:22.373471 DQS0 = 0, DQS1 = 0
5131 23:06:22.373550 DQM Delay:
5132 23:06:22.373613 DQM0 = 97, DQM1 = 86
5133 23:06:22.376633 DQ Delay:
5134 23:06:22.379778 DQ0 =92, DQ1 =100, DQ2 =94, DQ3 =94
5135 23:06:22.383152 DQ4 =100, DQ5 =88, DQ6 =104, DQ7 =104
5136 23:06:22.386453 DQ8 =76, DQ9 =70, DQ10 =84, DQ11 =78
5137 23:06:22.389989 DQ12 =96, DQ13 =94, DQ14 =98, DQ15 =98
5138 23:06:22.390068
5139 23:06:22.390131
5140 23:06:22.396618 [DQSOSCAuto] RK0, (LSB)MR18= 0x2020, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 411 ps
5141 23:06:22.399850 CH0 RK0: MR19=505, MR18=2020
5142 23:06:22.406370 CH0_RK0: MR19=0x505, MR18=0x2020, DQSOSC=411, MR23=63, INC=64, DEC=42
5143 23:06:22.406452
5144 23:06:22.409763 ----->DramcWriteLeveling(PI) begin...
5145 23:06:22.409845 ==
5146 23:06:22.413130 Dram Type= 6, Freq= 0, CH_0, rank 1
5147 23:06:22.416239 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5148 23:06:22.416320 ==
5149 23:06:22.419605 Write leveling (Byte 0): 29 => 29
5150 23:06:22.423091 Write leveling (Byte 1): 24 => 24
5151 23:06:22.426452 DramcWriteLeveling(PI) end<-----
5152 23:06:22.426533
5153 23:06:22.426596 ==
5154 23:06:22.429916 Dram Type= 6, Freq= 0, CH_0, rank 1
5155 23:06:22.433172 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5156 23:06:22.436234 ==
5157 23:06:22.436314 [Gating] SW mode calibration
5158 23:06:22.442957 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5159 23:06:22.449599 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5160 23:06:22.452796 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5161 23:06:22.459536 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5162 23:06:22.462641 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5163 23:06:22.466188 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5164 23:06:22.472502 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5165 23:06:22.476151 0 10 20 | B1->B0 | 3131 2f2f | 1 1 | (1 1) (1 1)
5166 23:06:22.479334 0 10 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5167 23:06:22.486228 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5168 23:06:22.489190 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5169 23:06:22.492814 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5170 23:06:22.499038 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5171 23:06:22.502688 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5172 23:06:22.505730 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5173 23:06:22.512541 0 11 20 | B1->B0 | 3030 3939 | 0 0 | (0 0) (0 0)
5174 23:06:22.515707 0 11 24 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
5175 23:06:22.518993 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5176 23:06:22.525679 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5177 23:06:22.528916 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5178 23:06:22.532116 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5179 23:06:22.538725 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5180 23:06:22.542563 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5181 23:06:22.545612 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5182 23:06:22.552352 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5183 23:06:22.555343 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 23:06:22.558741 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 23:06:22.565313 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 23:06:22.568734 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 23:06:22.572150 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 23:06:22.578493 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 23:06:22.582238 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 23:06:22.585148 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 23:06:22.592186 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 23:06:22.595274 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 23:06:22.598393 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 23:06:22.601696 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 23:06:22.608448 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 23:06:22.611696 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5197 23:06:22.615007 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5198 23:06:22.618638 Total UI for P1: 0, mck2ui 16
5199 23:06:22.621701 best dqsien dly found for B1: ( 0, 14, 18)
5200 23:06:22.628201 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5201 23:06:22.631534 Total UI for P1: 0, mck2ui 16
5202 23:06:22.634770 best dqsien dly found for B0: ( 0, 14, 18)
5203 23:06:22.638116 best DQS0 dly(MCK, UI, PI) = (0, 14, 18)
5204 23:06:22.641459 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5205 23:06:22.641539
5206 23:06:22.644828 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 18)
5207 23:06:22.648423 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5208 23:06:22.651294 [Gating] SW calibration Done
5209 23:06:22.651374 ==
5210 23:06:22.654881 Dram Type= 6, Freq= 0, CH_0, rank 1
5211 23:06:22.657859 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5212 23:06:22.657940 ==
5213 23:06:22.661327 RX Vref Scan: 0
5214 23:06:22.661407
5215 23:06:22.664431 RX Vref 0 -> 0, step: 1
5216 23:06:22.664571
5217 23:06:22.664637 RX Delay -80 -> 252, step: 8
5218 23:06:22.671439 iDelay=200, Bit 0, Center 91 (-8 ~ 191) 200
5219 23:06:22.674547 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5220 23:06:22.677987 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5221 23:06:22.681579 iDelay=200, Bit 3, Center 91 (0 ~ 183) 184
5222 23:06:22.684484 iDelay=200, Bit 4, Center 99 (0 ~ 199) 200
5223 23:06:22.687940 iDelay=200, Bit 5, Center 87 (-16 ~ 191) 208
5224 23:06:22.694419 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5225 23:06:22.697736 iDelay=200, Bit 7, Center 107 (16 ~ 199) 184
5226 23:06:22.701118 iDelay=200, Bit 8, Center 75 (-16 ~ 167) 184
5227 23:06:22.704404 iDelay=200, Bit 9, Center 71 (-24 ~ 167) 192
5228 23:06:22.707711 iDelay=200, Bit 10, Center 83 (-16 ~ 183) 200
5229 23:06:22.714552 iDelay=200, Bit 11, Center 75 (-16 ~ 167) 184
5230 23:06:22.717728 iDelay=200, Bit 12, Center 91 (0 ~ 183) 184
5231 23:06:22.720878 iDelay=200, Bit 13, Center 91 (-8 ~ 191) 200
5232 23:06:22.724093 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5233 23:06:22.727638 iDelay=200, Bit 15, Center 91 (0 ~ 183) 184
5234 23:06:22.727721 ==
5235 23:06:22.730945 Dram Type= 6, Freq= 0, CH_0, rank 1
5236 23:06:22.737330 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5237 23:06:22.737432 ==
5238 23:06:22.737497 DQS Delay:
5239 23:06:22.740726 DQS0 = 0, DQS1 = 0
5240 23:06:22.740806 DQM Delay:
5241 23:06:22.743999 DQM0 = 96, DQM1 = 84
5242 23:06:22.744080 DQ Delay:
5243 23:06:22.747444 DQ0 =91, DQ1 =99, DQ2 =95, DQ3 =91
5244 23:06:22.750571 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =107
5245 23:06:22.753850 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =75
5246 23:06:22.757261 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =91
5247 23:06:22.757343
5248 23:06:22.757406
5249 23:06:22.757464 ==
5250 23:06:22.760357 Dram Type= 6, Freq= 0, CH_0, rank 1
5251 23:06:22.763682 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5252 23:06:22.763763 ==
5253 23:06:22.763826
5254 23:06:22.763885
5255 23:06:22.767007 TX Vref Scan disable
5256 23:06:22.770443 == TX Byte 0 ==
5257 23:06:22.773844 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5258 23:06:22.777036 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5259 23:06:22.780713 == TX Byte 1 ==
5260 23:06:22.783905 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5261 23:06:22.787466 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5262 23:06:22.787547 ==
5263 23:06:22.790550 Dram Type= 6, Freq= 0, CH_0, rank 1
5264 23:06:22.796919 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5265 23:06:22.797001 ==
5266 23:06:22.797065
5267 23:06:22.797123
5268 23:06:22.797180 TX Vref Scan disable
5269 23:06:22.800921 == TX Byte 0 ==
5270 23:06:22.804400 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5271 23:06:22.810839 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5272 23:06:22.810921 == TX Byte 1 ==
5273 23:06:22.814361 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5274 23:06:22.820917 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5275 23:06:22.820998
5276 23:06:22.821061 [DATLAT]
5277 23:06:22.821120 Freq=933, CH0 RK1
5278 23:06:22.821177
5279 23:06:22.824444 DATLAT Default: 0xb
5280 23:06:22.824582 0, 0xFFFF, sum = 0
5281 23:06:22.827305 1, 0xFFFF, sum = 0
5282 23:06:22.827387 2, 0xFFFF, sum = 0
5283 23:06:22.830605 3, 0xFFFF, sum = 0
5284 23:06:22.834113 4, 0xFFFF, sum = 0
5285 23:06:22.834195 5, 0xFFFF, sum = 0
5286 23:06:22.837370 6, 0xFFFF, sum = 0
5287 23:06:22.837452 7, 0xFFFF, sum = 0
5288 23:06:22.840977 8, 0xFFFF, sum = 0
5289 23:06:22.841059 9, 0xFFFF, sum = 0
5290 23:06:22.844046 10, 0x0, sum = 1
5291 23:06:22.844128 11, 0x0, sum = 2
5292 23:06:22.847349 12, 0x0, sum = 3
5293 23:06:22.847431 13, 0x0, sum = 4
5294 23:06:22.847497 best_step = 11
5295 23:06:22.847556
5296 23:06:22.850646 ==
5297 23:06:22.853812 Dram Type= 6, Freq= 0, CH_0, rank 1
5298 23:06:22.857164 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5299 23:06:22.857245 ==
5300 23:06:22.857309 RX Vref Scan: 0
5301 23:06:22.857369
5302 23:06:22.860453 RX Vref 0 -> 0, step: 1
5303 23:06:22.860571
5304 23:06:22.864099 RX Delay -69 -> 252, step: 4
5305 23:06:22.867272 iDelay=199, Bit 0, Center 94 (7 ~ 182) 176
5306 23:06:22.873546 iDelay=199, Bit 1, Center 100 (7 ~ 194) 188
5307 23:06:22.877311 iDelay=199, Bit 2, Center 96 (7 ~ 186) 180
5308 23:06:22.880396 iDelay=199, Bit 3, Center 92 (7 ~ 178) 172
5309 23:06:22.883571 iDelay=199, Bit 4, Center 102 (15 ~ 190) 176
5310 23:06:22.887082 iDelay=199, Bit 5, Center 90 (-5 ~ 186) 192
5311 23:06:22.893668 iDelay=199, Bit 6, Center 106 (19 ~ 194) 176
5312 23:06:22.896713 iDelay=199, Bit 7, Center 108 (19 ~ 198) 180
5313 23:06:22.900304 iDelay=199, Bit 8, Center 76 (-9 ~ 162) 172
5314 23:06:22.903575 iDelay=199, Bit 9, Center 70 (-17 ~ 158) 176
5315 23:06:22.906927 iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180
5316 23:06:22.910329 iDelay=199, Bit 11, Center 76 (-9 ~ 162) 172
5317 23:06:22.916879 iDelay=199, Bit 12, Center 92 (7 ~ 178) 172
5318 23:06:22.920059 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5319 23:06:22.923735 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5320 23:06:22.926729 iDelay=199, Bit 15, Center 94 (7 ~ 182) 176
5321 23:06:22.926810 ==
5322 23:06:22.930094 Dram Type= 6, Freq= 0, CH_0, rank 1
5323 23:06:22.936412 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5324 23:06:22.936543 ==
5325 23:06:22.936622 DQS Delay:
5326 23:06:22.936682 DQS0 = 0, DQS1 = 0
5327 23:06:22.939775 DQM Delay:
5328 23:06:22.939858 DQM0 = 98, DQM1 = 85
5329 23:06:22.943119 DQ Delay:
5330 23:06:22.946457 DQ0 =94, DQ1 =100, DQ2 =96, DQ3 =92
5331 23:06:22.949891 DQ4 =102, DQ5 =90, DQ6 =106, DQ7 =108
5332 23:06:22.953295 DQ8 =76, DQ9 =70, DQ10 =88, DQ11 =76
5333 23:06:22.956452 DQ12 =92, DQ13 =90, DQ14 =96, DQ15 =94
5334 23:06:22.956585
5335 23:06:22.956649
5336 23:06:22.963094 [DQSOSCAuto] RK1, (LSB)MR18= 0x2a2a, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 408 ps
5337 23:06:22.966459 CH0 RK1: MR19=505, MR18=2A2A
5338 23:06:22.972843 CH0_RK1: MR19=0x505, MR18=0x2A2A, DQSOSC=408, MR23=63, INC=65, DEC=43
5339 23:06:22.976329 [RxdqsGatingPostProcess] freq 933
5340 23:06:22.979407 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5341 23:06:22.982690 Pre-setting of DQS Precalculation
5342 23:06:22.989510 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5343 23:06:22.989593 ==
5344 23:06:22.992733 Dram Type= 6, Freq= 0, CH_1, rank 0
5345 23:06:22.995924 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5346 23:06:22.996006 ==
5347 23:06:23.003032 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5348 23:06:23.009108 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5349 23:06:23.012479 [CA 0] Center 37 (6~68) winsize 63
5350 23:06:23.015730 [CA 1] Center 37 (6~68) winsize 63
5351 23:06:23.019240 [CA 2] Center 34 (4~65) winsize 62
5352 23:06:23.022574 [CA 3] Center 34 (4~65) winsize 62
5353 23:06:23.025970 [CA 4] Center 32 (2~63) winsize 62
5354 23:06:23.029136 [CA 5] Center 33 (3~64) winsize 62
5355 23:06:23.029217
5356 23:06:23.032308 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5357 23:06:23.032388
5358 23:06:23.035629 [CATrainingPosCal] consider 1 rank data
5359 23:06:23.039030 u2DelayCellTimex100 = 270/100 ps
5360 23:06:23.042245 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5361 23:06:23.045681 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5362 23:06:23.049247 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5363 23:06:23.052209 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5364 23:06:23.055582 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
5365 23:06:23.059148 CA5 delay=33 (3~64),Diff = 1 PI (6 cell)
5366 23:06:23.059228
5367 23:06:23.065445 CA PerBit enable=1, Macro0, CA PI delay=32
5368 23:06:23.065526
5369 23:06:23.068694 [CBTSetCACLKResult] CA Dly = 32
5370 23:06:23.068774 CS Dly: 5 (0~36)
5371 23:06:23.068837 ==
5372 23:06:23.072364 Dram Type= 6, Freq= 0, CH_1, rank 1
5373 23:06:23.075386 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5374 23:06:23.075467 ==
5375 23:06:23.081939 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5376 23:06:23.088702 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5377 23:06:23.091848 [CA 0] Center 37 (7~68) winsize 62
5378 23:06:23.095397 [CA 1] Center 37 (6~68) winsize 63
5379 23:06:23.098478 [CA 2] Center 34 (4~65) winsize 62
5380 23:06:23.101783 [CA 3] Center 34 (4~64) winsize 61
5381 23:06:23.105166 [CA 4] Center 33 (3~63) winsize 61
5382 23:06:23.108389 [CA 5] Center 32 (2~63) winsize 62
5383 23:06:23.108469
5384 23:06:23.111966 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5385 23:06:23.112045
5386 23:06:23.114979 [CATrainingPosCal] consider 2 rank data
5387 23:06:23.118350 u2DelayCellTimex100 = 270/100 ps
5388 23:06:23.121671 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5389 23:06:23.124927 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5390 23:06:23.128377 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5391 23:06:23.131720 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5392 23:06:23.135002 CA4 delay=33 (3~63),Diff = 0 PI (0 cell)
5393 23:06:23.141919 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5394 23:06:23.142000
5395 23:06:23.145284 CA PerBit enable=1, Macro0, CA PI delay=33
5396 23:06:23.145364
5397 23:06:23.148784 [CBTSetCACLKResult] CA Dly = 33
5398 23:06:23.148864 CS Dly: 5 (0~37)
5399 23:06:23.148929
5400 23:06:23.151786 ----->DramcWriteLeveling(PI) begin...
5401 23:06:23.151866 ==
5402 23:06:23.155200 Dram Type= 6, Freq= 0, CH_1, rank 0
5403 23:06:23.158782 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5404 23:06:23.161838 ==
5405 23:06:23.164974 Write leveling (Byte 0): 22 => 22
5406 23:06:23.165055 Write leveling (Byte 1): 21 => 21
5407 23:06:23.168270 DramcWriteLeveling(PI) end<-----
5408 23:06:23.168349
5409 23:06:23.168412 ==
5410 23:06:23.171661 Dram Type= 6, Freq= 0, CH_1, rank 0
5411 23:06:23.178141 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5412 23:06:23.178222 ==
5413 23:06:23.181515 [Gating] SW mode calibration
5414 23:06:23.187888 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5415 23:06:23.191482 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5416 23:06:23.198135 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5417 23:06:23.201382 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5418 23:06:23.204746 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5419 23:06:23.211340 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5420 23:06:23.214524 0 10 16 | B1->B0 | 3434 2f2f | 1 1 | (1 0) (1 0)
5421 23:06:23.217904 0 10 20 | B1->B0 | 3030 2323 | 1 0 | (1 0) (1 0)
5422 23:06:23.224634 0 10 24 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
5423 23:06:23.227845 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5424 23:06:23.231142 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5425 23:06:23.238978 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5426 23:06:23.241229 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5427 23:06:23.244408 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5428 23:06:23.247849 0 11 16 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
5429 23:06:23.254336 0 11 20 | B1->B0 | 2727 4343 | 1 0 | (0 0) (0 0)
5430 23:06:23.257729 0 11 24 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
5431 23:06:23.260918 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5432 23:06:23.268049 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5433 23:06:23.271240 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5434 23:06:23.274233 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5435 23:06:23.281144 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5436 23:06:23.284260 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5437 23:06:23.287412 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5438 23:06:23.294255 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5439 23:06:23.297499 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5440 23:06:23.300883 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5441 23:06:23.307603 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5442 23:06:23.310649 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5443 23:06:23.313940 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5444 23:06:23.320979 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5445 23:06:23.324178 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5446 23:06:23.327514 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5447 23:06:23.333952 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5448 23:06:23.337459 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5449 23:06:23.340763 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5450 23:06:23.346993 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5451 23:06:23.350329 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5452 23:06:23.353900 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5453 23:06:23.360489 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5454 23:06:23.360580 Total UI for P1: 0, mck2ui 16
5455 23:06:23.367135 best dqsien dly found for B0: ( 0, 14, 14)
5456 23:06:23.370423 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5457 23:06:23.373748 Total UI for P1: 0, mck2ui 16
5458 23:06:23.377212 best dqsien dly found for B1: ( 0, 14, 20)
5459 23:06:23.380620 best DQS0 dly(MCK, UI, PI) = (0, 14, 14)
5460 23:06:23.383683 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5461 23:06:23.383764
5462 23:06:23.387018 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 14)
5463 23:06:23.390239 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5464 23:06:23.393412 [Gating] SW calibration Done
5465 23:06:23.393492 ==
5466 23:06:23.396814 Dram Type= 6, Freq= 0, CH_1, rank 0
5467 23:06:23.403408 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5468 23:06:23.403489 ==
5469 23:06:23.403553 RX Vref Scan: 0
5470 23:06:23.403612
5471 23:06:23.406813 RX Vref 0 -> 0, step: 1
5472 23:06:23.406893
5473 23:06:23.410190 RX Delay -80 -> 252, step: 8
5474 23:06:23.413332 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5475 23:06:23.416636 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5476 23:06:23.419950 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5477 23:06:23.423363 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5478 23:06:23.429873 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5479 23:06:23.433029 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5480 23:06:23.436419 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5481 23:06:23.439886 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5482 23:06:23.443239 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5483 23:06:23.446284 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5484 23:06:23.452872 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5485 23:06:23.456334 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5486 23:06:23.459594 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5487 23:06:23.462848 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5488 23:06:23.466231 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5489 23:06:23.472758 iDelay=208, Bit 15, Center 95 (-8 ~ 199) 208
5490 23:06:23.472839 ==
5491 23:06:23.476267 Dram Type= 6, Freq= 0, CH_1, rank 0
5492 23:06:23.479614 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5493 23:06:23.479696 ==
5494 23:06:23.479760 DQS Delay:
5495 23:06:23.482880 DQS0 = 0, DQS1 = 0
5496 23:06:23.482961 DQM Delay:
5497 23:06:23.486072 DQM0 = 94, DQM1 = 87
5498 23:06:23.486153 DQ Delay:
5499 23:06:23.489486 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5500 23:06:23.492492 DQ4 =91, DQ5 =107, DQ6 =103, DQ7 =91
5501 23:06:23.496103 DQ8 =71, DQ9 =79, DQ10 =91, DQ11 =79
5502 23:06:23.499371 DQ12 =95, DQ13 =99, DQ14 =91, DQ15 =95
5503 23:06:23.499452
5504 23:06:23.499516
5505 23:06:23.499574 ==
5506 23:06:23.502655 Dram Type= 6, Freq= 0, CH_1, rank 0
5507 23:06:23.506175 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5508 23:06:23.509193 ==
5509 23:06:23.509274
5510 23:06:23.509338
5511 23:06:23.509397 TX Vref Scan disable
5512 23:06:23.512754 == TX Byte 0 ==
5513 23:06:23.516108 Update DQ dly =704 (2 ,5, 32) DQ OEN =(2 ,2)
5514 23:06:23.519091 Update DQM dly =704 (2 ,5, 32) DQM OEN =(2 ,2)
5515 23:06:23.522615 == TX Byte 1 ==
5516 23:06:23.525714 Update DQ dly =704 (2 ,5, 32) DQ OEN =(2 ,2)
5517 23:06:23.529132 Update DQM dly =704 (2 ,5, 32) DQM OEN =(2 ,2)
5518 23:06:23.532437 ==
5519 23:06:23.535719 Dram Type= 6, Freq= 0, CH_1, rank 0
5520 23:06:23.539178 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5521 23:06:23.539251 ==
5522 23:06:23.539312
5523 23:06:23.539369
5524 23:06:23.542266 TX Vref Scan disable
5525 23:06:23.542337 == TX Byte 0 ==
5526 23:06:23.548967 Update DQ dly =704 (2 ,5, 32) DQ OEN =(2 ,2)
5527 23:06:23.551999 Update DQM dly =704 (2 ,5, 32) DQM OEN =(2 ,2)
5528 23:06:23.552079 == TX Byte 1 ==
5529 23:06:23.558748 Update DQ dly =704 (2 ,5, 32) DQ OEN =(2 ,2)
5530 23:06:23.561960 Update DQM dly =704 (2 ,5, 32) DQM OEN =(2 ,2)
5531 23:06:23.562041
5532 23:06:23.562103 [DATLAT]
5533 23:06:23.565252 Freq=933, CH1 RK0
5534 23:06:23.565332
5535 23:06:23.565395 DATLAT Default: 0xd
5536 23:06:23.569033 0, 0xFFFF, sum = 0
5537 23:06:23.569114 1, 0xFFFF, sum = 0
5538 23:06:23.571791 2, 0xFFFF, sum = 0
5539 23:06:23.571872 3, 0xFFFF, sum = 0
5540 23:06:23.575464 4, 0xFFFF, sum = 0
5541 23:06:23.578498 5, 0xFFFF, sum = 0
5542 23:06:23.578579 6, 0xFFFF, sum = 0
5543 23:06:23.581526 7, 0xFFFF, sum = 0
5544 23:06:23.581633 8, 0xFFFF, sum = 0
5545 23:06:23.584948 9, 0xFFFF, sum = 0
5546 23:06:23.585029 10, 0x0, sum = 1
5547 23:06:23.588454 11, 0x0, sum = 2
5548 23:06:23.588574 12, 0x0, sum = 3
5549 23:06:23.591552 13, 0x0, sum = 4
5550 23:06:23.591633 best_step = 11
5551 23:06:23.591696
5552 23:06:23.591754 ==
5553 23:06:23.594794 Dram Type= 6, Freq= 0, CH_1, rank 0
5554 23:06:23.598250 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5555 23:06:23.598369 ==
5556 23:06:23.601543 RX Vref Scan: 1
5557 23:06:23.601622
5558 23:06:23.605008 RX Vref 0 -> 0, step: 1
5559 23:06:23.605088
5560 23:06:23.605150 RX Delay -69 -> 252, step: 4
5561 23:06:23.605210
5562 23:06:23.608009 Set Vref, RX VrefLevel [Byte0]: 57
5563 23:06:23.611510 [Byte1]: 48
5564 23:06:23.615941
5565 23:06:23.616046 Final RX Vref Byte 0 = 57 to rank0
5566 23:06:23.619325 Final RX Vref Byte 1 = 48 to rank0
5567 23:06:23.622710 Final RX Vref Byte 0 = 57 to rank1
5568 23:06:23.625908 Final RX Vref Byte 1 = 48 to rank1==
5569 23:06:23.629229 Dram Type= 6, Freq= 0, CH_1, rank 0
5570 23:06:23.636023 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5571 23:06:23.636104 ==
5572 23:06:23.636167 DQS Delay:
5573 23:06:23.639424 DQS0 = 0, DQS1 = 0
5574 23:06:23.639504 DQM Delay:
5575 23:06:23.639566 DQM0 = 94, DQM1 = 88
5576 23:06:23.642533 DQ Delay:
5577 23:06:23.646064 DQ0 =96, DQ1 =90, DQ2 =86, DQ3 =92
5578 23:06:23.649234 DQ4 =92, DQ5 =104, DQ6 =102, DQ7 =90
5579 23:06:23.652547 DQ8 =70, DQ9 =76, DQ10 =90, DQ11 =80
5580 23:06:23.655870 DQ12 =94, DQ13 =98, DQ14 =98, DQ15 =98
5581 23:06:23.655958
5582 23:06:23.656026
5583 23:06:23.662722 [DQSOSCAuto] RK0, (LSB)MR18= 0x3737, (MSB)MR19= 0x505, tDQSOscB0 = 404 ps tDQSOscB1 = 404 ps
5584 23:06:23.665971 CH1 RK0: MR19=505, MR18=3737
5585 23:06:23.672517 CH1_RK0: MR19=0x505, MR18=0x3737, DQSOSC=404, MR23=63, INC=66, DEC=44
5586 23:06:23.672609
5587 23:06:23.676155 ----->DramcWriteLeveling(PI) begin...
5588 23:06:23.676237 ==
5589 23:06:23.679477 Dram Type= 6, Freq= 0, CH_1, rank 1
5590 23:06:23.682638 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5591 23:06:23.682719 ==
5592 23:06:23.685762 Write leveling (Byte 0): 27 => 27
5593 23:06:23.689113 Write leveling (Byte 1): 22 => 22
5594 23:06:23.692485 DramcWriteLeveling(PI) end<-----
5595 23:06:23.692633
5596 23:06:23.692725 ==
5597 23:06:23.695858 Dram Type= 6, Freq= 0, CH_1, rank 1
5598 23:06:23.698901 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5599 23:06:23.698981 ==
5600 23:06:23.702546 [Gating] SW mode calibration
5601 23:06:23.709324 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5602 23:06:23.715760 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5603 23:06:23.719231 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5604 23:06:23.725746 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5605 23:06:23.728742 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5606 23:06:23.732079 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5607 23:06:23.738652 0 10 16 | B1->B0 | 3434 2929 | 1 0 | (1 1) (0 0)
5608 23:06:23.742432 0 10 20 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
5609 23:06:23.745300 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5610 23:06:23.752214 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5611 23:06:23.755359 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5612 23:06:23.758712 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5613 23:06:23.765194 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5614 23:06:23.768629 0 11 12 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5615 23:06:23.771966 0 11 16 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
5616 23:06:23.778505 0 11 20 | B1->B0 | 3030 4646 | 0 0 | (1 1) (0 0)
5617 23:06:23.782017 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5618 23:06:23.785107 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5619 23:06:23.788453 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5620 23:06:23.794968 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5621 23:06:23.798403 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5622 23:06:23.801674 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5623 23:06:23.808384 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5624 23:06:23.811868 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5625 23:06:23.814931 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 23:06:23.821681 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 23:06:23.825000 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 23:06:23.828341 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 23:06:23.834841 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 23:06:23.838118 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 23:06:23.841533 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 23:06:23.848150 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 23:06:23.851372 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 23:06:23.854759 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 23:06:23.861328 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 23:06:23.864478 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 23:06:23.868173 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5638 23:06:23.874599 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 23:06:23.877794 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5640 23:06:23.881264 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5641 23:06:23.884788 Total UI for P1: 0, mck2ui 16
5642 23:06:23.888106 best dqsien dly found for B1: ( 0, 14, 16)
5643 23:06:23.894609 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5644 23:06:23.894694 Total UI for P1: 0, mck2ui 16
5645 23:06:23.901207 best dqsien dly found for B0: ( 0, 14, 18)
5646 23:06:23.904459 best DQS0 dly(MCK, UI, PI) = (0, 14, 18)
5647 23:06:23.907666 best DQS1 dly(MCK, UI, PI) = (0, 14, 16)
5648 23:06:23.907749
5649 23:06:23.911041 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 18)
5650 23:06:23.914553 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 16)
5651 23:06:23.918003 [Gating] SW calibration Done
5652 23:06:23.918086 ==
5653 23:06:23.920769 Dram Type= 6, Freq= 0, CH_1, rank 1
5654 23:06:23.924218 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5655 23:06:23.924302 ==
5656 23:06:23.927475 RX Vref Scan: 0
5657 23:06:23.927559
5658 23:06:23.927644 RX Vref 0 -> 0, step: 1
5659 23:06:23.930803
5660 23:06:23.930887 RX Delay -80 -> 252, step: 8
5661 23:06:23.937344 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5662 23:06:23.940704 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5663 23:06:23.944236 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5664 23:06:23.947362 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5665 23:06:23.950592 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5666 23:06:23.953807 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5667 23:06:23.960781 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5668 23:06:23.964243 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5669 23:06:23.967170 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5670 23:06:23.970446 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5671 23:06:23.973712 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5672 23:06:23.980103 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5673 23:06:23.983710 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5674 23:06:23.986842 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5675 23:06:23.990411 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5676 23:06:23.993421 iDelay=208, Bit 15, Center 91 (0 ~ 183) 184
5677 23:06:23.993504 ==
5678 23:06:23.996765 Dram Type= 6, Freq= 0, CH_1, rank 1
5679 23:06:24.003534 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5680 23:06:24.003619 ==
5681 23:06:24.003704 DQS Delay:
5682 23:06:24.006969 DQS0 = 0, DQS1 = 0
5683 23:06:24.007053 DQM Delay:
5684 23:06:24.007138 DQM0 = 96, DQM1 = 86
5685 23:06:24.010414 DQ Delay:
5686 23:06:24.013696 DQ0 =99, DQ1 =91, DQ2 =87, DQ3 =91
5687 23:06:24.016916 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =91
5688 23:06:24.020132 DQ8 =75, DQ9 =75, DQ10 =87, DQ11 =79
5689 23:06:24.023462 DQ12 =91, DQ13 =95, DQ14 =95, DQ15 =91
5690 23:06:24.023534
5691 23:06:24.023595
5692 23:06:24.023652 ==
5693 23:06:24.026971 Dram Type= 6, Freq= 0, CH_1, rank 1
5694 23:06:24.029825 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5695 23:06:24.029894 ==
5696 23:06:24.029952
5697 23:06:24.030008
5698 23:06:24.033097 TX Vref Scan disable
5699 23:06:24.036431 == TX Byte 0 ==
5700 23:06:24.039828 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5701 23:06:24.043090 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5702 23:06:24.046811 == TX Byte 1 ==
5703 23:06:24.049671 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5704 23:06:24.052872 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5705 23:06:24.052952 ==
5706 23:06:24.056232 Dram Type= 6, Freq= 0, CH_1, rank 1
5707 23:06:24.059964 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5708 23:06:24.063134 ==
5709 23:06:24.063214
5710 23:06:24.063277
5711 23:06:24.063336 TX Vref Scan disable
5712 23:06:24.066413 == TX Byte 0 ==
5713 23:06:24.069818 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5714 23:06:24.076474 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5715 23:06:24.076570 == TX Byte 1 ==
5716 23:06:24.079979 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5717 23:06:24.086455 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5718 23:06:24.086535
5719 23:06:24.086597 [DATLAT]
5720 23:06:24.086655 Freq=933, CH1 RK1
5721 23:06:24.086711
5722 23:06:24.089726 DATLAT Default: 0xb
5723 23:06:24.089806 0, 0xFFFF, sum = 0
5724 23:06:24.093033 1, 0xFFFF, sum = 0
5725 23:06:24.093114 2, 0xFFFF, sum = 0
5726 23:06:24.096294 3, 0xFFFF, sum = 0
5727 23:06:24.099760 4, 0xFFFF, sum = 0
5728 23:06:24.099841 5, 0xFFFF, sum = 0
5729 23:06:24.102870 6, 0xFFFF, sum = 0
5730 23:06:24.102951 7, 0xFFFF, sum = 0
5731 23:06:24.106310 8, 0xFFFF, sum = 0
5732 23:06:24.106391 9, 0xFFFF, sum = 0
5733 23:06:24.109553 10, 0x0, sum = 1
5734 23:06:24.109625 11, 0x0, sum = 2
5735 23:06:24.113413 12, 0x0, sum = 3
5736 23:06:24.113495 13, 0x0, sum = 4
5737 23:06:24.113559 best_step = 11
5738 23:06:24.113616
5739 23:06:24.116363 ==
5740 23:06:24.119878 Dram Type= 6, Freq= 0, CH_1, rank 1
5741 23:06:24.122889 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5742 23:06:24.122970 ==
5743 23:06:24.123034 RX Vref Scan: 0
5744 23:06:24.123092
5745 23:06:24.126287 RX Vref 0 -> 0, step: 1
5746 23:06:24.126367
5747 23:06:24.129641 RX Delay -69 -> 252, step: 4
5748 23:06:24.132825 iDelay=203, Bit 0, Center 98 (7 ~ 190) 184
5749 23:06:24.139711 iDelay=203, Bit 1, Center 90 (-1 ~ 182) 184
5750 23:06:24.142618 iDelay=203, Bit 2, Center 86 (-9 ~ 182) 192
5751 23:06:24.145953 iDelay=203, Bit 3, Center 92 (-1 ~ 186) 188
5752 23:06:24.149224 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5753 23:06:24.152464 iDelay=203, Bit 5, Center 106 (11 ~ 202) 192
5754 23:06:24.159164 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5755 23:06:24.162584 iDelay=203, Bit 7, Center 94 (3 ~ 186) 184
5756 23:06:24.166111 iDelay=203, Bit 8, Center 74 (-17 ~ 166) 184
5757 23:06:24.169274 iDelay=203, Bit 9, Center 74 (-17 ~ 166) 184
5758 23:06:24.172337 iDelay=203, Bit 10, Center 86 (-5 ~ 178) 184
5759 23:06:24.179113 iDelay=203, Bit 11, Center 78 (-13 ~ 170) 184
5760 23:06:24.182923 iDelay=203, Bit 12, Center 96 (7 ~ 186) 180
5761 23:06:24.185944 iDelay=203, Bit 13, Center 98 (11 ~ 186) 176
5762 23:06:24.189140 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5763 23:06:24.192362 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5764 23:06:24.192446 ==
5765 23:06:24.195731 Dram Type= 6, Freq= 0, CH_1, rank 1
5766 23:06:24.199010 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5767 23:06:24.202521 ==
5768 23:06:24.202606 DQS Delay:
5769 23:06:24.202691 DQS0 = 0, DQS1 = 0
5770 23:06:24.205837 DQM Delay:
5771 23:06:24.205920 DQM0 = 95, DQM1 = 87
5772 23:06:24.209278 DQ Delay:
5773 23:06:24.212494 DQ0 =98, DQ1 =90, DQ2 =86, DQ3 =92
5774 23:06:24.215667 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =94
5775 23:06:24.219061 DQ8 =74, DQ9 =74, DQ10 =86, DQ11 =78
5776 23:06:24.222337 DQ12 =96, DQ13 =98, DQ14 =96, DQ15 =96
5777 23:06:24.222421
5778 23:06:24.222506
5779 23:06:24.229102 [DQSOSCAuto] RK1, (LSB)MR18= 0x2020, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 411 ps
5780 23:06:24.232275 CH1 RK1: MR19=505, MR18=2020
5781 23:06:24.238913 CH1_RK1: MR19=0x505, MR18=0x2020, DQSOSC=411, MR23=63, INC=64, DEC=42
5782 23:06:24.242300 [RxdqsGatingPostProcess] freq 933
5783 23:06:24.245362 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5784 23:06:24.248998 Pre-setting of DQS Precalculation
5785 23:06:24.255589 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5786 23:06:24.261997 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5787 23:06:24.268697 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5788 23:06:24.268782
5789 23:06:24.268865
5790 23:06:24.271848 [Calibration Summary] 1866 Mbps
5791 23:06:24.271945 CH 0, Rank 0
5792 23:06:24.275326 SW Impedance : PASS
5793 23:06:24.278589 DUTY Scan : NO K
5794 23:06:24.278672 ZQ Calibration : PASS
5795 23:06:24.281921 Jitter Meter : NO K
5796 23:06:24.285398 CBT Training : PASS
5797 23:06:24.285482 Write leveling : PASS
5798 23:06:24.288602 RX DQS gating : PASS
5799 23:06:24.291670 RX DQ/DQS(RDDQC) : PASS
5800 23:06:24.291754 TX DQ/DQS : PASS
5801 23:06:24.295069 RX DATLAT : PASS
5802 23:06:24.298458 RX DQ/DQS(Engine): PASS
5803 23:06:24.298542 TX OE : NO K
5804 23:06:24.298628 All Pass.
5805 23:06:24.301996
5806 23:06:24.302079 CH 0, Rank 1
5807 23:06:24.305294 SW Impedance : PASS
5808 23:06:24.305377 DUTY Scan : NO K
5809 23:06:24.308251 ZQ Calibration : PASS
5810 23:06:24.308358 Jitter Meter : NO K
5811 23:06:24.311819 CBT Training : PASS
5812 23:06:24.315322 Write leveling : PASS
5813 23:06:24.315405 RX DQS gating : PASS
5814 23:06:24.318365 RX DQ/DQS(RDDQC) : PASS
5815 23:06:24.321949 TX DQ/DQS : PASS
5816 23:06:24.322034 RX DATLAT : PASS
5817 23:06:24.325288 RX DQ/DQS(Engine): PASS
5818 23:06:24.328585 TX OE : NO K
5819 23:06:24.328667 All Pass.
5820 23:06:24.328730
5821 23:06:24.328788 CH 1, Rank 0
5822 23:06:24.331818 SW Impedance : PASS
5823 23:06:24.335133 DUTY Scan : NO K
5824 23:06:24.335213 ZQ Calibration : PASS
5825 23:06:24.338956 Jitter Meter : NO K
5826 23:06:24.341686 CBT Training : PASS
5827 23:06:24.341767 Write leveling : PASS
5828 23:06:24.344920 RX DQS gating : PASS
5829 23:06:24.348142 RX DQ/DQS(RDDQC) : PASS
5830 23:06:24.348223 TX DQ/DQS : PASS
5831 23:06:24.351452 RX DATLAT : PASS
5832 23:06:24.354790 RX DQ/DQS(Engine): PASS
5833 23:06:24.354871 TX OE : NO K
5834 23:06:24.354935 All Pass.
5835 23:06:24.354993
5836 23:06:24.358665 CH 1, Rank 1
5837 23:06:24.361588 SW Impedance : PASS
5838 23:06:24.361668 DUTY Scan : NO K
5839 23:06:24.365146 ZQ Calibration : PASS
5840 23:06:24.365227 Jitter Meter : NO K
5841 23:06:24.368160 CBT Training : PASS
5842 23:06:24.371405 Write leveling : PASS
5843 23:06:24.371489 RX DQS gating : PASS
5844 23:06:24.374614 RX DQ/DQS(RDDQC) : PASS
5845 23:06:24.377899 TX DQ/DQS : PASS
5846 23:06:24.377984 RX DATLAT : PASS
5847 23:06:24.381133 RX DQ/DQS(Engine): PASS
5848 23:06:24.384477 TX OE : NO K
5849 23:06:24.384644 All Pass.
5850 23:06:24.384729
5851 23:06:24.387995 DramC Write-DBI off
5852 23:06:24.388079 PER_BANK_REFRESH: Hybrid Mode
5853 23:06:24.391402 TX_TRACKING: ON
5854 23:06:24.401218 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5855 23:06:24.404580 [FAST_K] Save calibration result to emmc
5856 23:06:24.408059 dramc_set_vcore_voltage set vcore to 650000
5857 23:06:24.408143 Read voltage for 400, 6
5858 23:06:24.411033 Vio18 = 0
5859 23:06:24.411116 Vcore = 650000
5860 23:06:24.411201 Vdram = 0
5861 23:06:24.414338 Vddq = 0
5862 23:06:24.414421 Vmddr = 0
5863 23:06:24.420793 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5864 23:06:24.424144 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5865 23:06:24.427400 MEM_TYPE=3, freq_sel=20
5866 23:06:24.430890 sv_algorithm_assistance_LP4_800
5867 23:06:24.434422 ============ PULL DRAM RESETB DOWN ============
5868 23:06:24.437356 ========== PULL DRAM RESETB DOWN end =========
5869 23:06:24.444058 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5870 23:06:24.447253 ===================================
5871 23:06:24.447337 LPDDR4 DRAM CONFIGURATION
5872 23:06:24.450719 ===================================
5873 23:06:24.454326 EX_ROW_EN[0] = 0x0
5874 23:06:24.457326 EX_ROW_EN[1] = 0x0
5875 23:06:24.457410 LP4Y_EN = 0x0
5876 23:06:24.460784 WORK_FSP = 0x0
5877 23:06:24.460867 WL = 0x2
5878 23:06:24.464116 RL = 0x2
5879 23:06:24.464199 BL = 0x2
5880 23:06:24.467233 RPST = 0x0
5881 23:06:24.467316 RD_PRE = 0x0
5882 23:06:24.470301 WR_PRE = 0x1
5883 23:06:24.470385 WR_PST = 0x0
5884 23:06:24.473682 DBI_WR = 0x0
5885 23:06:24.473765 DBI_RD = 0x0
5886 23:06:24.476895 OTF = 0x1
5887 23:06:24.480339 ===================================
5888 23:06:24.483432 ===================================
5889 23:06:24.483520 ANA top config
5890 23:06:24.486996 ===================================
5891 23:06:24.490165 DLL_ASYNC_EN = 0
5892 23:06:24.493731 ALL_SLAVE_EN = 1
5893 23:06:24.496793 NEW_RANK_MODE = 1
5894 23:06:24.496874 DLL_IDLE_MODE = 1
5895 23:06:24.500406 LP45_APHY_COMB_EN = 1
5896 23:06:24.503581 TX_ODT_DIS = 1
5897 23:06:24.506979 NEW_8X_MODE = 1
5898 23:06:24.509945 ===================================
5899 23:06:24.513482 ===================================
5900 23:06:24.516852 data_rate = 800
5901 23:06:24.516933 CKR = 1
5902 23:06:24.520027 DQ_P2S_RATIO = 4
5903 23:06:24.523306 ===================================
5904 23:06:24.526488 CA_P2S_RATIO = 4
5905 23:06:24.529725 DQ_CA_OPEN = 0
5906 23:06:24.532939 DQ_SEMI_OPEN = 1
5907 23:06:24.536514 CA_SEMI_OPEN = 1
5908 23:06:24.536595 CA_FULL_RATE = 0
5909 23:06:24.539978 DQ_CKDIV4_EN = 0
5910 23:06:24.543264 CA_CKDIV4_EN = 1
5911 23:06:24.546402 CA_PREDIV_EN = 0
5912 23:06:24.549692 PH8_DLY = 0
5913 23:06:24.553025 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5914 23:06:24.553105 DQ_AAMCK_DIV = 0
5915 23:06:24.556532 CA_AAMCK_DIV = 0
5916 23:06:24.559922 CA_ADMCK_DIV = 4
5917 23:06:24.562731 DQ_TRACK_CA_EN = 0
5918 23:06:24.566215 CA_PICK = 800
5919 23:06:24.569324 CA_MCKIO = 400
5920 23:06:24.572819 MCKIO_SEMI = 400
5921 23:06:24.572899 PLL_FREQ = 3016
5922 23:06:24.576156 DQ_UI_PI_RATIO = 32
5923 23:06:24.579492 CA_UI_PI_RATIO = 32
5924 23:06:24.582577 ===================================
5925 23:06:24.585966 ===================================
5926 23:06:24.589207 memory_type:LPDDR4
5927 23:06:24.592542 GP_NUM : 10
5928 23:06:24.592636 SRAM_EN : 1
5929 23:06:24.596113 MD32_EN : 0
5930 23:06:24.599301 ===================================
5931 23:06:24.599407 [ANA_INIT] >>>>>>>>>>>>>>
5932 23:06:24.602824 <<<<<< [CONFIGURE PHASE]: ANA_TX
5933 23:06:24.605872 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5934 23:06:24.609111 ===================================
5935 23:06:24.612303 data_rate = 800,PCW = 0X7400
5936 23:06:24.615819 ===================================
5937 23:06:24.619393 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5938 23:06:24.625794 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5939 23:06:24.635844 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5940 23:06:24.642422 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5941 23:06:24.645549 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5942 23:06:24.648900 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5943 23:06:24.648980 [ANA_INIT] flow start
5944 23:06:24.652203 [ANA_INIT] PLL >>>>>>>>
5945 23:06:24.655378 [ANA_INIT] PLL <<<<<<<<
5946 23:06:24.658606 [ANA_INIT] MIDPI >>>>>>>>
5947 23:06:24.658686 [ANA_INIT] MIDPI <<<<<<<<
5948 23:06:24.661980 [ANA_INIT] DLL >>>>>>>>
5949 23:06:24.662060 [ANA_INIT] flow end
5950 23:06:24.668759 ============ LP4 DIFF to SE enter ============
5951 23:06:24.672048 ============ LP4 DIFF to SE exit ============
5952 23:06:24.675218 [ANA_INIT] <<<<<<<<<<<<<
5953 23:06:24.678883 [Flow] Enable top DCM control >>>>>
5954 23:06:24.682110 [Flow] Enable top DCM control <<<<<
5955 23:06:24.685232 Enable DLL master slave shuffle
5956 23:06:24.688706 ==============================================================
5957 23:06:24.691935 Gating Mode config
5958 23:06:24.695464 ==============================================================
5959 23:06:24.698515 Config description:
5960 23:06:24.708311 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5961 23:06:24.714983 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5962 23:06:24.718468 SELPH_MODE 0: By rank 1: By Phase
5963 23:06:24.725177 ==============================================================
5964 23:06:24.728747 GAT_TRACK_EN = 0
5965 23:06:24.731760 RX_GATING_MODE = 2
5966 23:06:24.734968 RX_GATING_TRACK_MODE = 2
5967 23:06:24.738010 SELPH_MODE = 1
5968 23:06:24.741578 PICG_EARLY_EN = 1
5969 23:06:24.744850 VALID_LAT_VALUE = 1
5970 23:06:24.748069 ==============================================================
5971 23:06:24.751237 Enter into Gating configuration >>>>
5972 23:06:24.754535 Exit from Gating configuration <<<<
5973 23:06:24.757870 Enter into DVFS_PRE_config >>>>>
5974 23:06:24.771398 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5975 23:06:24.771483 Exit from DVFS_PRE_config <<<<<
5976 23:06:24.774430 Enter into PICG configuration >>>>
5977 23:06:24.777983 Exit from PICG configuration <<<<
5978 23:06:24.781404 [RX_INPUT] configuration >>>>>
5979 23:06:24.784418 [RX_INPUT] configuration <<<<<
5980 23:06:24.791231 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5981 23:06:24.794525 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5982 23:06:24.801105 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5983 23:06:24.807913 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5984 23:06:24.814121 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5985 23:06:24.820880 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5986 23:06:24.824205 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5987 23:06:24.827594 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5988 23:06:24.830917 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5989 23:06:24.837744 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5990 23:06:24.840769 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5991 23:06:24.844242 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5992 23:06:24.847548 ===================================
5993 23:06:24.851054 LPDDR4 DRAM CONFIGURATION
5994 23:06:24.854183 ===================================
5995 23:06:24.854263 EX_ROW_EN[0] = 0x0
5996 23:06:24.857550 EX_ROW_EN[1] = 0x0
5997 23:06:24.860726 LP4Y_EN = 0x0
5998 23:06:24.860806 WORK_FSP = 0x0
5999 23:06:24.863959 WL = 0x2
6000 23:06:24.864038 RL = 0x2
6001 23:06:24.867249 BL = 0x2
6002 23:06:24.867336 RPST = 0x0
6003 23:06:24.870595 RD_PRE = 0x0
6004 23:06:24.870700 WR_PRE = 0x1
6005 23:06:24.873804 WR_PST = 0x0
6006 23:06:24.873887 DBI_WR = 0x0
6007 23:06:24.877135 DBI_RD = 0x0
6008 23:06:24.877240 OTF = 0x1
6009 23:06:24.880360 ===================================
6010 23:06:24.883769 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6011 23:06:24.890402 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6012 23:06:24.894127 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6013 23:06:24.897465 ===================================
6014 23:06:24.900449 LPDDR4 DRAM CONFIGURATION
6015 23:06:24.903907 ===================================
6016 23:06:24.903988 EX_ROW_EN[0] = 0x10
6017 23:06:24.907072 EX_ROW_EN[1] = 0x0
6018 23:06:24.910324 LP4Y_EN = 0x0
6019 23:06:24.910404 WORK_FSP = 0x0
6020 23:06:24.913532 WL = 0x2
6021 23:06:24.913612 RL = 0x2
6022 23:06:24.916964 BL = 0x2
6023 23:06:24.917044 RPST = 0x0
6024 23:06:24.920394 RD_PRE = 0x0
6025 23:06:24.920473 WR_PRE = 0x1
6026 23:06:24.923483 WR_PST = 0x0
6027 23:06:24.923562 DBI_WR = 0x0
6028 23:06:24.926942 DBI_RD = 0x0
6029 23:06:24.927021 OTF = 0x1
6030 23:06:24.930025 ===================================
6031 23:06:24.936864 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6032 23:06:24.941086 nWR fixed to 30
6033 23:06:24.944647 [ModeRegInit_LP4] CH0 RK0
6034 23:06:24.944727 [ModeRegInit_LP4] CH0 RK1
6035 23:06:24.947832 [ModeRegInit_LP4] CH1 RK0
6036 23:06:24.951152 [ModeRegInit_LP4] CH1 RK1
6037 23:06:24.951234 match AC timing 18
6038 23:06:24.957812 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
6039 23:06:24.961005 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6040 23:06:24.964384 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6041 23:06:24.970757 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6042 23:06:24.974102 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6043 23:06:24.974204 ==
6044 23:06:24.977407 Dram Type= 6, Freq= 0, CH_0, rank 0
6045 23:06:24.980895 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6046 23:06:24.980993 ==
6047 23:06:24.987491 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6048 23:06:24.994118 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6049 23:06:24.997525 [CA 0] Center 36 (8~64) winsize 57
6050 23:06:25.000758 [CA 1] Center 36 (8~64) winsize 57
6051 23:06:25.004107 [CA 2] Center 36 (8~64) winsize 57
6052 23:06:25.007365 [CA 3] Center 36 (8~64) winsize 57
6053 23:06:25.007464 [CA 4] Center 36 (8~64) winsize 57
6054 23:06:25.010663 [CA 5] Center 36 (8~64) winsize 57
6055 23:06:25.010760
6056 23:06:25.017399 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6057 23:06:25.017475
6058 23:06:25.020779 [CATrainingPosCal] consider 1 rank data
6059 23:06:25.024238 u2DelayCellTimex100 = 270/100 ps
6060 23:06:25.027364 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6061 23:06:25.030843 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6062 23:06:25.034125 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6063 23:06:25.037491 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6064 23:06:25.040858 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6065 23:06:25.044121 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6066 23:06:25.044219
6067 23:06:25.047445 CA PerBit enable=1, Macro0, CA PI delay=36
6068 23:06:25.047532
6069 23:06:25.050487 [CBTSetCACLKResult] CA Dly = 36
6070 23:06:25.054095 CS Dly: 1 (0~32)
6071 23:06:25.054190 ==
6072 23:06:25.057222 Dram Type= 6, Freq= 0, CH_0, rank 1
6073 23:06:25.060425 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6074 23:06:25.060531 ==
6075 23:06:25.067153 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6076 23:06:25.070790 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6077 23:06:25.073936 [CA 0] Center 36 (8~64) winsize 57
6078 23:06:25.077137 [CA 1] Center 36 (8~64) winsize 57
6079 23:06:25.080408 [CA 2] Center 36 (8~64) winsize 57
6080 23:06:25.083718 [CA 3] Center 36 (8~64) winsize 57
6081 23:06:25.087239 [CA 4] Center 36 (8~64) winsize 57
6082 23:06:25.090569 [CA 5] Center 36 (8~64) winsize 57
6083 23:06:25.090654
6084 23:06:25.093520 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6085 23:06:25.093619
6086 23:06:25.096951 [CATrainingPosCal] consider 2 rank data
6087 23:06:25.100242 u2DelayCellTimex100 = 270/100 ps
6088 23:06:25.103570 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6089 23:06:25.107073 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6090 23:06:25.113625 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6091 23:06:25.116913 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6092 23:06:25.120149 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6093 23:06:25.123436 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6094 23:06:25.123516
6095 23:06:25.126633 CA PerBit enable=1, Macro0, CA PI delay=36
6096 23:06:25.126713
6097 23:06:25.130021 [CBTSetCACLKResult] CA Dly = 36
6098 23:06:25.130100 CS Dly: 1 (0~32)
6099 23:06:25.130163
6100 23:06:25.133424 ----->DramcWriteLeveling(PI) begin...
6101 23:06:25.136590 ==
6102 23:06:25.139962 Dram Type= 6, Freq= 0, CH_0, rank 0
6103 23:06:25.143430 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6104 23:06:25.143511 ==
6105 23:06:25.146880 Write leveling (Byte 0): 32 => 0
6106 23:06:25.149927 Write leveling (Byte 1): 32 => 0
6107 23:06:25.153329 DramcWriteLeveling(PI) end<-----
6108 23:06:25.153409
6109 23:06:25.153471 ==
6110 23:06:25.156789 Dram Type= 6, Freq= 0, CH_0, rank 0
6111 23:06:25.159963 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6112 23:06:25.160044 ==
6113 23:06:25.163556 [Gating] SW mode calibration
6114 23:06:25.169840 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6115 23:06:25.176239 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6116 23:06:25.179973 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6117 23:06:25.183181 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6118 23:06:25.189858 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6119 23:06:25.193021 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6120 23:06:25.196327 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6121 23:06:25.199919 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6122 23:06:25.206217 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6123 23:06:25.209464 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
6124 23:06:25.212772 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6125 23:06:25.216205 Total UI for P1: 0, mck2ui 16
6126 23:06:25.219511 best dqsien dly found for B0: ( 0, 10, 16)
6127 23:06:25.222761 Total UI for P1: 0, mck2ui 16
6128 23:06:25.226267 best dqsien dly found for B1: ( 0, 10, 24)
6129 23:06:25.229402 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6130 23:06:25.236051 best DQS1 dly(MCK, UI, PI) = (0, 10, 24)
6131 23:06:25.236131
6132 23:06:25.239314 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6133 23:06:25.242654 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24)
6134 23:06:25.245919 [Gating] SW calibration Done
6135 23:06:25.246034 ==
6136 23:06:25.249403 Dram Type= 6, Freq= 0, CH_0, rank 0
6137 23:06:25.252676 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6138 23:06:25.252757 ==
6139 23:06:25.256191 RX Vref Scan: 0
6140 23:06:25.256296
6141 23:06:25.256386 RX Vref 0 -> 0, step: 1
6142 23:06:25.256471
6143 23:06:25.259366 RX Delay -410 -> 252, step: 16
6144 23:06:25.265788 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6145 23:06:25.269151 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6146 23:06:25.272449 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6147 23:06:25.275993 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6148 23:06:25.282679 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6149 23:06:25.285586 iDelay=230, Bit 5, Center -51 (-298 ~ 197) 496
6150 23:06:25.288829 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6151 23:06:25.292389 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6152 23:06:25.299124 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6153 23:06:25.301911 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6154 23:06:25.305369 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6155 23:06:25.308546 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6156 23:06:25.315058 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6157 23:06:25.318607 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6158 23:06:25.321940 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6159 23:06:25.324905 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6160 23:06:25.328714 ==
6161 23:06:25.331563 Dram Type= 6, Freq= 0, CH_0, rank 0
6162 23:06:25.335054 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6163 23:06:25.335134 ==
6164 23:06:25.335198 DQS Delay:
6165 23:06:25.338292 DQS0 = 51, DQS1 = 59
6166 23:06:25.338375 DQM Delay:
6167 23:06:25.341595 DQM0 = 12, DQM1 = 16
6168 23:06:25.341675 DQ Delay:
6169 23:06:25.344965 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6170 23:06:25.348190 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6171 23:06:25.351506 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6172 23:06:25.354615 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6173 23:06:25.354695
6174 23:06:25.354757
6175 23:06:25.354815 ==
6176 23:06:25.358185 Dram Type= 6, Freq= 0, CH_0, rank 0
6177 23:06:25.361445 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6178 23:06:25.361526 ==
6179 23:06:25.361589
6180 23:06:25.361646
6181 23:06:25.364915 TX Vref Scan disable
6182 23:06:25.364994 == TX Byte 0 ==
6183 23:06:25.371309 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6184 23:06:25.374542 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6185 23:06:25.374622 == TX Byte 1 ==
6186 23:06:25.381184 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6187 23:06:25.384323 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6188 23:06:25.384428 ==
6189 23:06:25.387704 Dram Type= 6, Freq= 0, CH_0, rank 0
6190 23:06:25.391127 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6191 23:06:25.391208 ==
6192 23:06:25.394589
6193 23:06:25.394668
6194 23:06:25.394731 TX Vref Scan disable
6195 23:06:25.397582 == TX Byte 0 ==
6196 23:06:25.400917 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6197 23:06:25.404189 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6198 23:06:25.407558 == TX Byte 1 ==
6199 23:06:25.410954 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6200 23:06:25.414371 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6201 23:06:25.414466
6202 23:06:25.417685 [DATLAT]
6203 23:06:25.417760 Freq=400, CH0 RK0
6204 23:06:25.417822
6205 23:06:25.420881 DATLAT Default: 0xf
6206 23:06:25.420987 0, 0xFFFF, sum = 0
6207 23:06:25.424172 1, 0xFFFF, sum = 0
6208 23:06:25.424271 2, 0xFFFF, sum = 0
6209 23:06:25.427503 3, 0xFFFF, sum = 0
6210 23:06:25.427604 4, 0xFFFF, sum = 0
6211 23:06:25.430979 5, 0xFFFF, sum = 0
6212 23:06:25.431079 6, 0xFFFF, sum = 0
6213 23:06:25.434010 7, 0xFFFF, sum = 0
6214 23:06:25.434085 8, 0xFFFF, sum = 0
6215 23:06:25.437271 9, 0xFFFF, sum = 0
6216 23:06:25.437345 10, 0xFFFF, sum = 0
6217 23:06:25.440469 11, 0xFFFF, sum = 0
6218 23:06:25.440572 12, 0x0, sum = 1
6219 23:06:25.443827 13, 0x0, sum = 2
6220 23:06:25.443909 14, 0x0, sum = 3
6221 23:06:25.447237 15, 0x0, sum = 4
6222 23:06:25.447331 best_step = 13
6223 23:06:25.447419
6224 23:06:25.447502 ==
6225 23:06:25.450494 Dram Type= 6, Freq= 0, CH_0, rank 0
6226 23:06:25.457274 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6227 23:06:25.457374 ==
6228 23:06:25.457463 RX Vref Scan: 1
6229 23:06:25.457552
6230 23:06:25.460444 RX Vref 0 -> 0, step: 1
6231 23:06:25.460581
6232 23:06:25.463956 RX Delay -359 -> 252, step: 8
6233 23:06:25.464050
6234 23:06:25.466967 Set Vref, RX VrefLevel [Byte0]: 46
6235 23:06:25.470188 [Byte1]: 46
6236 23:06:25.473699
6237 23:06:25.473808 Final RX Vref Byte 0 = 46 to rank0
6238 23:06:25.477302 Final RX Vref Byte 1 = 46 to rank0
6239 23:06:25.480111 Final RX Vref Byte 0 = 46 to rank1
6240 23:06:25.483505 Final RX Vref Byte 1 = 46 to rank1==
6241 23:06:25.486772 Dram Type= 6, Freq= 0, CH_0, rank 0
6242 23:06:25.493387 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6243 23:06:25.493460 ==
6244 23:06:25.493521 DQS Delay:
6245 23:06:25.496704 DQS0 = 52, DQS1 = 68
6246 23:06:25.496801 DQM Delay:
6247 23:06:25.496907 DQM0 = 9, DQM1 = 17
6248 23:06:25.500331 DQ Delay:
6249 23:06:25.503209 DQ0 =4, DQ1 =8, DQ2 =8, DQ3 =4
6250 23:06:25.503308 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6251 23:06:25.506621 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6252 23:06:25.509687 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =28
6253 23:06:25.509755
6254 23:06:25.513087
6255 23:06:25.519904 [DQSOSCAuto] RK0, (LSB)MR18= 0xa1a1, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
6256 23:06:25.522992 CH0 RK0: MR19=C0C, MR18=A1A1
6257 23:06:25.529591 CH0_RK0: MR19=0xC0C, MR18=0xA1A1, DQSOSC=389, MR23=63, INC=390, DEC=260
6258 23:06:25.529666 ==
6259 23:06:25.532924 Dram Type= 6, Freq= 0, CH_0, rank 1
6260 23:06:25.536099 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6261 23:06:25.536170 ==
6262 23:06:25.539894 [Gating] SW mode calibration
6263 23:06:25.546253 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6264 23:06:25.552995 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6265 23:06:25.556255 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6266 23:06:25.559279 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6267 23:06:25.565926 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6268 23:06:25.569284 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6269 23:06:25.572663 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6270 23:06:25.579537 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6271 23:06:25.582544 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6272 23:06:25.585810 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6273 23:06:25.592446 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6274 23:06:25.592551 Total UI for P1: 0, mck2ui 16
6275 23:06:25.595893 best dqsien dly found for B0: ( 0, 10, 16)
6276 23:06:25.598903 Total UI for P1: 0, mck2ui 16
6277 23:06:25.602206 best dqsien dly found for B1: ( 0, 10, 16)
6278 23:06:25.609127 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6279 23:06:25.612299 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6280 23:06:25.612394
6281 23:06:25.615523 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6282 23:06:25.619008 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6283 23:06:25.622032 [Gating] SW calibration Done
6284 23:06:25.622108 ==
6285 23:06:25.625648 Dram Type= 6, Freq= 0, CH_0, rank 1
6286 23:06:25.628846 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6287 23:06:25.628942 ==
6288 23:06:25.632112 RX Vref Scan: 0
6289 23:06:25.632181
6290 23:06:25.632240 RX Vref 0 -> 0, step: 1
6291 23:06:25.632296
6292 23:06:25.635379 RX Delay -410 -> 252, step: 16
6293 23:06:25.642181 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6294 23:06:25.645411 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6295 23:06:25.648872 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6296 23:06:25.652065 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6297 23:06:25.658690 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6298 23:06:25.662126 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6299 23:06:25.665613 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6300 23:06:25.668622 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6301 23:06:25.674953 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6302 23:06:25.678637 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6303 23:06:25.681802 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6304 23:06:25.685224 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6305 23:06:25.691509 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6306 23:06:25.694823 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6307 23:06:25.698102 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6308 23:06:25.704906 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6309 23:06:25.705010 ==
6310 23:06:25.708111 Dram Type= 6, Freq= 0, CH_0, rank 1
6311 23:06:25.711415 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6312 23:06:25.711515 ==
6313 23:06:25.711605 DQS Delay:
6314 23:06:25.714948 DQS0 = 43, DQS1 = 59
6315 23:06:25.715044 DQM Delay:
6316 23:06:25.718151 DQM0 = 7, DQM1 = 15
6317 23:06:25.718247 DQ Delay:
6318 23:06:25.721281 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6319 23:06:25.724682 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6320 23:06:25.728072 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6321 23:06:25.731485 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6322 23:06:25.731558
6323 23:06:25.731619
6324 23:06:25.731684 ==
6325 23:06:25.734612 Dram Type= 6, Freq= 0, CH_0, rank 1
6326 23:06:25.737990 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6327 23:06:25.738061 ==
6328 23:06:25.738131
6329 23:06:25.738188
6330 23:06:25.741448 TX Vref Scan disable
6331 23:06:25.741518 == TX Byte 0 ==
6332 23:06:25.747805 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6333 23:06:25.751166 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6334 23:06:25.751240 == TX Byte 1 ==
6335 23:06:25.758129 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6336 23:06:25.761209 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6337 23:06:25.761282 ==
6338 23:06:25.764429 Dram Type= 6, Freq= 0, CH_0, rank 1
6339 23:06:25.767721 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6340 23:06:25.767820 ==
6341 23:06:25.767910
6342 23:06:25.768007
6343 23:06:25.770978 TX Vref Scan disable
6344 23:06:25.771077 == TX Byte 0 ==
6345 23:06:25.777725 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6346 23:06:25.781055 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6347 23:06:25.781139 == TX Byte 1 ==
6348 23:06:25.787828 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6349 23:06:25.791281 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6350 23:06:25.791381
6351 23:06:25.791471 [DATLAT]
6352 23:06:25.794448 Freq=400, CH0 RK1
6353 23:06:25.794519
6354 23:06:25.794578 DATLAT Default: 0xd
6355 23:06:25.797956 0, 0xFFFF, sum = 0
6356 23:06:25.798055 1, 0xFFFF, sum = 0
6357 23:06:25.800983 2, 0xFFFF, sum = 0
6358 23:06:25.801056 3, 0xFFFF, sum = 0
6359 23:06:25.804227 4, 0xFFFF, sum = 0
6360 23:06:25.804321 5, 0xFFFF, sum = 0
6361 23:06:25.807639 6, 0xFFFF, sum = 0
6362 23:06:25.807733 7, 0xFFFF, sum = 0
6363 23:06:25.810839 8, 0xFFFF, sum = 0
6364 23:06:25.810934 9, 0xFFFF, sum = 0
6365 23:06:25.814517 10, 0xFFFF, sum = 0
6366 23:06:25.817613 11, 0xFFFF, sum = 0
6367 23:06:25.817684 12, 0x0, sum = 1
6368 23:06:25.820984 13, 0x0, sum = 2
6369 23:06:25.821056 14, 0x0, sum = 3
6370 23:06:25.821115 15, 0x0, sum = 4
6371 23:06:25.824146 best_step = 13
6372 23:06:25.824236
6373 23:06:25.824324 ==
6374 23:06:25.827305 Dram Type= 6, Freq= 0, CH_0, rank 1
6375 23:06:25.830774 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6376 23:06:25.830858 ==
6377 23:06:25.833781 RX Vref Scan: 0
6378 23:06:25.833850
6379 23:06:25.837176 RX Vref 0 -> 0, step: 1
6380 23:06:25.837270
6381 23:06:25.837356 RX Delay -359 -> 252, step: 8
6382 23:06:25.845982 iDelay=217, Bit 0, Center -48 (-295 ~ 200) 496
6383 23:06:25.849304 iDelay=217, Bit 1, Center -36 (-287 ~ 216) 504
6384 23:06:25.852658 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504
6385 23:06:25.858982 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6386 23:06:25.862371 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6387 23:06:25.865584 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6388 23:06:25.869198 iDelay=217, Bit 6, Center -32 (-279 ~ 216) 496
6389 23:06:25.875356 iDelay=217, Bit 7, Center -32 (-279 ~ 216) 496
6390 23:06:25.878734 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6391 23:06:25.881883 iDelay=217, Bit 9, Center -64 (-303 ~ 176) 480
6392 23:06:25.885416 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6393 23:06:25.892311 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6394 23:06:25.895310 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6395 23:06:25.898514 iDelay=217, Bit 13, Center -44 (-287 ~ 200) 488
6396 23:06:25.902094 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6397 23:06:25.908500 iDelay=217, Bit 15, Center -44 (-287 ~ 200) 488
6398 23:06:25.908611 ==
6399 23:06:25.911955 Dram Type= 6, Freq= 0, CH_0, rank 1
6400 23:06:25.915205 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6401 23:06:25.915274 ==
6402 23:06:25.915333 DQS Delay:
6403 23:06:25.918741 DQS0 = 52, DQS1 = 64
6404 23:06:25.918837 DQM Delay:
6405 23:06:25.921995 DQM0 = 10, DQM1 = 13
6406 23:06:25.922062 DQ Delay:
6407 23:06:25.925426 DQ0 =4, DQ1 =16, DQ2 =8, DQ3 =4
6408 23:06:25.928411 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6409 23:06:25.931826 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6410 23:06:25.935345 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6411 23:06:25.935413
6412 23:06:25.935472
6413 23:06:25.941855 [DQSOSCAuto] RK1, (LSB)MR18= 0xbdbd, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 386 ps
6414 23:06:25.945016 CH0 RK1: MR19=C0C, MR18=BDBD
6415 23:06:25.952047 CH0_RK1: MR19=0xC0C, MR18=0xBDBD, DQSOSC=386, MR23=63, INC=396, DEC=264
6416 23:06:25.955202 [RxdqsGatingPostProcess] freq 400
6417 23:06:25.962486 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6418 23:06:25.965118 Pre-setting of DQS Precalculation
6419 23:06:25.968492 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6420 23:06:25.968589 ==
6421 23:06:25.971856 Dram Type= 6, Freq= 0, CH_1, rank 0
6422 23:06:25.975078 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6423 23:06:25.975161 ==
6424 23:06:25.981868 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6425 23:06:25.988406 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6426 23:06:25.991707 [CA 0] Center 36 (8~64) winsize 57
6427 23:06:25.995096 [CA 1] Center 36 (8~64) winsize 57
6428 23:06:25.998349 [CA 2] Center 36 (8~64) winsize 57
6429 23:06:26.001887 [CA 3] Center 36 (8~64) winsize 57
6430 23:06:26.005402 [CA 4] Center 36 (8~64) winsize 57
6431 23:06:26.005482 [CA 5] Center 36 (8~64) winsize 57
6432 23:06:26.008325
6433 23:06:26.011637 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6434 23:06:26.011717
6435 23:06:26.014973 [CATrainingPosCal] consider 1 rank data
6436 23:06:26.018299 u2DelayCellTimex100 = 270/100 ps
6437 23:06:26.021365 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6438 23:06:26.024767 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6439 23:06:26.028036 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6440 23:06:26.031536 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6441 23:06:26.034880 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6442 23:06:26.037951 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6443 23:06:26.038032
6444 23:06:26.041295 CA PerBit enable=1, Macro0, CA PI delay=36
6445 23:06:26.041375
6446 23:06:26.044537 [CBTSetCACLKResult] CA Dly = 36
6447 23:06:26.048150 CS Dly: 1 (0~32)
6448 23:06:26.048255 ==
6449 23:06:26.051276 Dram Type= 6, Freq= 0, CH_1, rank 1
6450 23:06:26.054566 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6451 23:06:26.054647 ==
6452 23:06:26.061338 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6453 23:06:26.068110 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6454 23:06:26.070905 [CA 0] Center 36 (8~64) winsize 57
6455 23:06:26.074411 [CA 1] Center 36 (8~64) winsize 57
6456 23:06:26.074492 [CA 2] Center 36 (8~64) winsize 57
6457 23:06:26.077628 [CA 3] Center 36 (8~64) winsize 57
6458 23:06:26.080997 [CA 4] Center 36 (8~64) winsize 57
6459 23:06:26.084299 [CA 5] Center 36 (8~64) winsize 57
6460 23:06:26.084373
6461 23:06:26.087386 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6462 23:06:26.087472
6463 23:06:26.094313 [CATrainingPosCal] consider 2 rank data
6464 23:06:26.094403 u2DelayCellTimex100 = 270/100 ps
6465 23:06:26.100758 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6466 23:06:26.104181 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6467 23:06:26.107370 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6468 23:06:26.110924 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6469 23:06:26.113962 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6470 23:06:26.117358 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6471 23:06:26.117448
6472 23:06:26.120599 CA PerBit enable=1, Macro0, CA PI delay=36
6473 23:06:26.120707
6474 23:06:26.123924 [CBTSetCACLKResult] CA Dly = 36
6475 23:06:26.127197 CS Dly: 1 (0~32)
6476 23:06:26.127305
6477 23:06:26.130433 ----->DramcWriteLeveling(PI) begin...
6478 23:06:26.130516 ==
6479 23:06:26.133907 Dram Type= 6, Freq= 0, CH_1, rank 0
6480 23:06:26.137235 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6481 23:06:26.137315 ==
6482 23:06:26.140456 Write leveling (Byte 0): 32 => 0
6483 23:06:26.143794 Write leveling (Byte 1): 32 => 0
6484 23:06:26.147142 DramcWriteLeveling(PI) end<-----
6485 23:06:26.147222
6486 23:06:26.147283 ==
6487 23:06:26.150535 Dram Type= 6, Freq= 0, CH_1, rank 0
6488 23:06:26.153613 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6489 23:06:26.153694 ==
6490 23:06:26.156800 [Gating] SW mode calibration
6491 23:06:26.163386 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6492 23:06:26.170107 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6493 23:06:26.173588 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6494 23:06:26.176769 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6495 23:06:26.183568 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6496 23:06:26.186560 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6497 23:06:26.189935 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6498 23:06:26.196601 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6499 23:06:26.199886 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6500 23:06:26.203169 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6501 23:06:26.209913 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6502 23:06:26.209993 Total UI for P1: 0, mck2ui 16
6503 23:06:26.216348 best dqsien dly found for B0: ( 0, 10, 16)
6504 23:06:26.216454 Total UI for P1: 0, mck2ui 16
6505 23:06:26.222927 best dqsien dly found for B1: ( 0, 10, 16)
6506 23:06:26.226623 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6507 23:06:26.229878 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6508 23:06:26.229959
6509 23:06:26.232802 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6510 23:06:26.236147 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6511 23:06:26.239645 [Gating] SW calibration Done
6512 23:06:26.239725 ==
6513 23:06:26.243247 Dram Type= 6, Freq= 0, CH_1, rank 0
6514 23:06:26.246376 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6515 23:06:26.246457 ==
6516 23:06:26.249863 RX Vref Scan: 0
6517 23:06:26.249950
6518 23:06:26.253055 RX Vref 0 -> 0, step: 1
6519 23:06:26.253135
6520 23:06:26.253198 RX Delay -410 -> 252, step: 16
6521 23:06:26.259197 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6522 23:06:26.262885 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6523 23:06:26.265881 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6524 23:06:26.272425 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6525 23:06:26.275549 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6526 23:06:26.278865 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6527 23:06:26.282366 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6528 23:06:26.289214 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6529 23:06:26.292122 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6530 23:06:26.295530 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6531 23:06:26.298873 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6532 23:06:26.305470 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6533 23:06:26.308706 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6534 23:06:26.312094 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6535 23:06:26.315654 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6536 23:06:26.321877 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6537 23:06:26.321958 ==
6538 23:06:26.325229 Dram Type= 6, Freq= 0, CH_1, rank 0
6539 23:06:26.328839 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6540 23:06:26.328965 ==
6541 23:06:26.329052 DQS Delay:
6542 23:06:26.332000 DQS0 = 43, DQS1 = 59
6543 23:06:26.332080 DQM Delay:
6544 23:06:26.335321 DQM0 = 6, DQM1 = 14
6545 23:06:26.335401 DQ Delay:
6546 23:06:26.338592 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6547 23:06:26.342041 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6548 23:06:26.345236 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6549 23:06:26.348643 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =32
6550 23:06:26.348723
6551 23:06:26.348785
6552 23:06:26.348842 ==
6553 23:06:26.351711 Dram Type= 6, Freq= 0, CH_1, rank 0
6554 23:06:26.355113 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6555 23:06:26.355194 ==
6556 23:06:26.355257
6557 23:06:26.358423
6558 23:06:26.358503 TX Vref Scan disable
6559 23:06:26.361781 == TX Byte 0 ==
6560 23:06:26.364969 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6561 23:06:26.368627 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6562 23:06:26.371520 == TX Byte 1 ==
6563 23:06:26.375127 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6564 23:06:26.378259 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6565 23:06:26.378339 ==
6566 23:06:26.381546 Dram Type= 6, Freq= 0, CH_1, rank 0
6567 23:06:26.388489 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6568 23:06:26.388580 ==
6569 23:06:26.388643
6570 23:06:26.388700
6571 23:06:26.388756 TX Vref Scan disable
6572 23:06:26.391447 == TX Byte 0 ==
6573 23:06:26.394603 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6574 23:06:26.397864 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6575 23:06:26.401245 == TX Byte 1 ==
6576 23:06:26.404731 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6577 23:06:26.408114 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6578 23:06:26.408194
6579 23:06:26.411506 [DATLAT]
6580 23:06:26.411586 Freq=400, CH1 RK0
6581 23:06:26.411649
6582 23:06:26.414752 DATLAT Default: 0xf
6583 23:06:26.414832 0, 0xFFFF, sum = 0
6584 23:06:26.418159 1, 0xFFFF, sum = 0
6585 23:06:26.418242 2, 0xFFFF, sum = 0
6586 23:06:26.421034 3, 0xFFFF, sum = 0
6587 23:06:26.421117 4, 0xFFFF, sum = 0
6588 23:06:26.424445 5, 0xFFFF, sum = 0
6589 23:06:26.427683 6, 0xFFFF, sum = 0
6590 23:06:26.427766 7, 0xFFFF, sum = 0
6591 23:06:26.430936 8, 0xFFFF, sum = 0
6592 23:06:26.431019 9, 0xFFFF, sum = 0
6593 23:06:26.434126 10, 0xFFFF, sum = 0
6594 23:06:26.434209 11, 0xFFFF, sum = 0
6595 23:06:26.438004 12, 0x0, sum = 1
6596 23:06:26.438088 13, 0x0, sum = 2
6597 23:06:26.440955 14, 0x0, sum = 3
6598 23:06:26.441055 15, 0x0, sum = 4
6599 23:06:26.441154 best_step = 13
6600 23:06:26.441233
6601 23:06:26.444330 ==
6602 23:06:26.447711 Dram Type= 6, Freq= 0, CH_1, rank 0
6603 23:06:26.451080 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6604 23:06:26.451162 ==
6605 23:06:26.451245 RX Vref Scan: 1
6606 23:06:26.451324
6607 23:06:26.454149 RX Vref 0 -> 0, step: 1
6608 23:06:26.454231
6609 23:06:26.457824 RX Delay -359 -> 252, step: 8
6610 23:06:26.457906
6611 23:06:26.460752 Set Vref, RX VrefLevel [Byte0]: 57
6612 23:06:26.463811 [Byte1]: 48
6613 23:06:26.468198
6614 23:06:26.468279 Final RX Vref Byte 0 = 57 to rank0
6615 23:06:26.471429 Final RX Vref Byte 1 = 48 to rank0
6616 23:06:26.474382 Final RX Vref Byte 0 = 57 to rank1
6617 23:06:26.477713 Final RX Vref Byte 1 = 48 to rank1==
6618 23:06:26.481080 Dram Type= 6, Freq= 0, CH_1, rank 0
6619 23:06:26.488117 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6620 23:06:26.488200 ==
6621 23:06:26.488283 DQS Delay:
6622 23:06:26.491370 DQS0 = 52, DQS1 = 64
6623 23:06:26.491452 DQM Delay:
6624 23:06:26.491535 DQM0 = 10, DQM1 = 15
6625 23:06:26.494395 DQ Delay:
6626 23:06:26.497644 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6627 23:06:26.497726 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
6628 23:06:26.500825 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6629 23:06:26.504478 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6630 23:06:26.504583
6631 23:06:26.507772
6632 23:06:26.514221 [DQSOSCAuto] RK0, (LSB)MR18= 0xdfdf, (MSB)MR19= 0xc0c, tDQSOscB0 = 382 ps tDQSOscB1 = 382 ps
6633 23:06:26.517415 CH1 RK0: MR19=C0C, MR18=DFDF
6634 23:06:26.523930 CH1_RK0: MR19=0xC0C, MR18=0xDFDF, DQSOSC=382, MR23=63, INC=404, DEC=269
6635 23:06:26.524012 ==
6636 23:06:26.527580 Dram Type= 6, Freq= 0, CH_1, rank 1
6637 23:06:26.530651 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6638 23:06:26.530733 ==
6639 23:06:26.534074 [Gating] SW mode calibration
6640 23:06:26.540498 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6641 23:06:26.547245 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6642 23:06:26.550488 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6643 23:06:26.553799 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6644 23:06:26.560702 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6645 23:06:26.563965 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6646 23:06:26.567095 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6647 23:06:26.573621 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6648 23:06:26.577034 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6649 23:06:26.580257 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
6650 23:06:26.583536 Total UI for P1: 0, mck2ui 16
6651 23:06:26.587141 best dqsien dly found for B0: ( 0, 10, 8)
6652 23:06:26.590563 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6653 23:06:26.593809 Total UI for P1: 0, mck2ui 16
6654 23:06:26.597259 best dqsien dly found for B1: ( 0, 10, 16)
6655 23:06:26.603432 best DQS0 dly(MCK, UI, PI) = (0, 10, 8)
6656 23:06:26.606810 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6657 23:06:26.606893
6658 23:06:26.610150 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 8)
6659 23:06:26.613361 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6660 23:06:26.616752 [Gating] SW calibration Done
6661 23:06:26.616834 ==
6662 23:06:26.619969 Dram Type= 6, Freq= 0, CH_1, rank 1
6663 23:06:26.623198 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6664 23:06:26.623281 ==
6665 23:06:26.626549 RX Vref Scan: 0
6666 23:06:26.626631
6667 23:06:26.626714 RX Vref 0 -> 0, step: 1
6668 23:06:26.626792
6669 23:06:26.630158 RX Delay -410 -> 252, step: 16
6670 23:06:26.636718 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6671 23:06:26.639918 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6672 23:06:26.643011 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6673 23:06:26.646414 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6674 23:06:26.652992 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6675 23:06:26.656391 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6676 23:06:26.659612 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6677 23:06:26.663014 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6678 23:06:26.669381 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6679 23:06:26.672699 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6680 23:06:26.675962 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6681 23:06:26.679218 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6682 23:06:26.685849 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6683 23:06:26.689067 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6684 23:06:26.692404 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6685 23:06:26.699175 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6686 23:06:26.699255 ==
6687 23:06:26.702786 Dram Type= 6, Freq= 0, CH_1, rank 1
6688 23:06:26.706022 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6689 23:06:26.706106 ==
6690 23:06:26.706170 DQS Delay:
6691 23:06:26.709147 DQS0 = 43, DQS1 = 59
6692 23:06:26.709227 DQM Delay:
6693 23:06:26.712348 DQM0 = 10, DQM1 = 17
6694 23:06:26.712454 DQ Delay:
6695 23:06:26.715891 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6696 23:06:26.719462 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6697 23:06:26.722384 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6698 23:06:26.725794 DQ12 =32, DQ13 =32, DQ14 =24, DQ15 =24
6699 23:06:26.725874
6700 23:06:26.725937
6701 23:06:26.725995 ==
6702 23:06:26.729101 Dram Type= 6, Freq= 0, CH_1, rank 1
6703 23:06:26.732481 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6704 23:06:26.732604 ==
6705 23:06:26.732669
6706 23:06:26.732727
6707 23:06:26.735769 TX Vref Scan disable
6708 23:06:26.735849 == TX Byte 0 ==
6709 23:06:26.742343 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6710 23:06:26.745623 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6711 23:06:26.745703 == TX Byte 1 ==
6712 23:06:26.752305 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6713 23:06:26.756035 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6714 23:06:26.756116 ==
6715 23:06:26.759154 Dram Type= 6, Freq= 0, CH_1, rank 1
6716 23:06:26.762083 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6717 23:06:26.762164 ==
6718 23:06:26.762227
6719 23:06:26.762285
6720 23:06:26.765786 TX Vref Scan disable
6721 23:06:26.765866 == TX Byte 0 ==
6722 23:06:26.772426 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6723 23:06:26.775509 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6724 23:06:26.775590 == TX Byte 1 ==
6725 23:06:26.782072 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6726 23:06:26.785305 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6727 23:06:26.785392
6728 23:06:26.785469 [DATLAT]
6729 23:06:26.788768 Freq=400, CH1 RK1
6730 23:06:26.788849
6731 23:06:26.788912 DATLAT Default: 0xd
6732 23:06:26.792099 0, 0xFFFF, sum = 0
6733 23:06:26.792180 1, 0xFFFF, sum = 0
6734 23:06:26.795304 2, 0xFFFF, sum = 0
6735 23:06:26.795390 3, 0xFFFF, sum = 0
6736 23:06:26.798525 4, 0xFFFF, sum = 0
6737 23:06:26.798606 5, 0xFFFF, sum = 0
6738 23:06:26.801796 6, 0xFFFF, sum = 0
6739 23:06:26.801907 7, 0xFFFF, sum = 0
6740 23:06:26.805462 8, 0xFFFF, sum = 0
6741 23:06:26.805545 9, 0xFFFF, sum = 0
6742 23:06:26.808730 10, 0xFFFF, sum = 0
6743 23:06:26.811871 11, 0xFFFF, sum = 0
6744 23:06:26.811952 12, 0x0, sum = 1
6745 23:06:26.812016 13, 0x0, sum = 2
6746 23:06:26.815259 14, 0x0, sum = 3
6747 23:06:26.815340 15, 0x0, sum = 4
6748 23:06:26.818748 best_step = 13
6749 23:06:26.818828
6750 23:06:26.818891 ==
6751 23:06:26.821760 Dram Type= 6, Freq= 0, CH_1, rank 1
6752 23:06:26.825051 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6753 23:06:26.825132 ==
6754 23:06:26.828434 RX Vref Scan: 0
6755 23:06:26.828572
6756 23:06:26.828638 RX Vref 0 -> 0, step: 1
6757 23:06:26.831478
6758 23:06:26.831557 RX Delay -359 -> 252, step: 8
6759 23:06:26.840249 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6760 23:06:26.843481 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6761 23:06:26.846532 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6762 23:06:26.853458 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6763 23:06:26.856934 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6764 23:06:26.859985 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6765 23:06:26.863327 iDelay=217, Bit 6, Center -32 (-279 ~ 216) 496
6766 23:06:26.866614 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6767 23:06:26.873165 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6768 23:06:26.876412 iDelay=217, Bit 9, Center -60 (-311 ~ 192) 504
6769 23:06:26.879870 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6770 23:06:26.886613 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
6771 23:06:26.889930 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6772 23:06:26.893084 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6773 23:06:26.896458 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6774 23:06:26.902865 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6775 23:06:26.902946 ==
6776 23:06:26.906222 Dram Type= 6, Freq= 0, CH_1, rank 1
6777 23:06:26.909482 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6778 23:06:26.909563 ==
6779 23:06:26.909629 DQS Delay:
6780 23:06:26.912959 DQS0 = 48, DQS1 = 64
6781 23:06:26.913039 DQM Delay:
6782 23:06:26.916134 DQM0 = 9, DQM1 = 15
6783 23:06:26.916214 DQ Delay:
6784 23:06:26.919624 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6785 23:06:26.923161 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6786 23:06:26.926285 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6787 23:06:26.929256 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6788 23:06:26.929327
6789 23:06:26.929387
6790 23:06:26.936174 [DQSOSCAuto] RK1, (LSB)MR18= 0xa8a8, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
6791 23:06:26.939625 CH1 RK1: MR19=C0C, MR18=A8A8
6792 23:06:26.946176 CH1_RK1: MR19=0xC0C, MR18=0xA8A8, DQSOSC=388, MR23=63, INC=392, DEC=261
6793 23:06:26.949372 [RxdqsGatingPostProcess] freq 400
6794 23:06:26.955918 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6795 23:06:26.959330 Pre-setting of DQS Precalculation
6796 23:06:26.962607 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6797 23:06:26.969194 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6798 23:06:26.975949 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6799 23:06:26.976050
6800 23:06:26.976143
6801 23:06:26.979239 [Calibration Summary] 800 Mbps
6802 23:06:26.982422 CH 0, Rank 0
6803 23:06:26.982491 SW Impedance : PASS
6804 23:06:26.985808 DUTY Scan : NO K
6805 23:06:26.989222 ZQ Calibration : PASS
6806 23:06:26.989302 Jitter Meter : NO K
6807 23:06:26.992726 CBT Training : PASS
6808 23:06:26.995582 Write leveling : PASS
6809 23:06:26.995660 RX DQS gating : PASS
6810 23:06:26.998794 RX DQ/DQS(RDDQC) : PASS
6811 23:06:27.002107 TX DQ/DQS : PASS
6812 23:06:27.002190 RX DATLAT : PASS
6813 23:06:27.005719 RX DQ/DQS(Engine): PASS
6814 23:06:27.008820 TX OE : NO K
6815 23:06:27.008901 All Pass.
6816 23:06:27.008964
6817 23:06:27.009023 CH 0, Rank 1
6818 23:06:27.012445 SW Impedance : PASS
6819 23:06:27.012583 DUTY Scan : NO K
6820 23:06:27.015320 ZQ Calibration : PASS
6821 23:06:27.018492 Jitter Meter : NO K
6822 23:06:27.018571 CBT Training : PASS
6823 23:06:27.022067 Write leveling : NO K
6824 23:06:27.025154 RX DQS gating : PASS
6825 23:06:27.025234 RX DQ/DQS(RDDQC) : PASS
6826 23:06:27.028325 TX DQ/DQS : PASS
6827 23:06:27.032016 RX DATLAT : PASS
6828 23:06:27.032096 RX DQ/DQS(Engine): PASS
6829 23:06:27.035086 TX OE : NO K
6830 23:06:27.035191 All Pass.
6831 23:06:27.035283
6832 23:06:27.038492 CH 1, Rank 0
6833 23:06:27.038572 SW Impedance : PASS
6834 23:06:27.042037 DUTY Scan : NO K
6835 23:06:27.045130 ZQ Calibration : PASS
6836 23:06:27.045210 Jitter Meter : NO K
6837 23:06:27.048468 CBT Training : PASS
6838 23:06:27.051794 Write leveling : PASS
6839 23:06:27.051874 RX DQS gating : PASS
6840 23:06:27.054886 RX DQ/DQS(RDDQC) : PASS
6841 23:06:27.058662 TX DQ/DQS : PASS
6842 23:06:27.058742 RX DATLAT : PASS
6843 23:06:27.062004 RX DQ/DQS(Engine): PASS
6844 23:06:27.064767 TX OE : NO K
6845 23:06:27.064847 All Pass.
6846 23:06:27.064910
6847 23:06:27.064969 CH 1, Rank 1
6848 23:06:27.068116 SW Impedance : PASS
6849 23:06:27.071598 DUTY Scan : NO K
6850 23:06:27.071678 ZQ Calibration : PASS
6851 23:06:27.074962 Jitter Meter : NO K
6852 23:06:27.078151 CBT Training : PASS
6853 23:06:27.078231 Write leveling : NO K
6854 23:06:27.081406 RX DQS gating : PASS
6855 23:06:27.081511 RX DQ/DQS(RDDQC) : PASS
6856 23:06:27.084656 TX DQ/DQS : PASS
6857 23:06:27.088015 RX DATLAT : PASS
6858 23:06:27.088120 RX DQ/DQS(Engine): PASS
6859 23:06:27.091241 TX OE : NO K
6860 23:06:27.091321 All Pass.
6861 23:06:27.091383
6862 23:06:27.094966 DramC Write-DBI off
6863 23:06:27.097992 PER_BANK_REFRESH: Hybrid Mode
6864 23:06:27.098071 TX_TRACKING: ON
6865 23:06:27.107940 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6866 23:06:27.111507 [FAST_K] Save calibration result to emmc
6867 23:06:27.114449 dramc_set_vcore_voltage set vcore to 725000
6868 23:06:27.117760 Read voltage for 1600, 0
6869 23:06:27.117839 Vio18 = 0
6870 23:06:27.121114 Vcore = 725000
6871 23:06:27.121193 Vdram = 0
6872 23:06:27.121256 Vddq = 0
6873 23:06:27.121314 Vmddr = 0
6874 23:06:27.127881 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6875 23:06:27.134469 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6876 23:06:27.134549 MEM_TYPE=3, freq_sel=13
6877 23:06:27.137827 sv_algorithm_assistance_LP4_3733
6878 23:06:27.141151 ============ PULL DRAM RESETB DOWN ============
6879 23:06:27.147797 ========== PULL DRAM RESETB DOWN end =========
6880 23:06:27.150962 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6881 23:06:27.154196 ===================================
6882 23:06:27.157703 LPDDR4 DRAM CONFIGURATION
6883 23:06:27.160760 ===================================
6884 23:06:27.160841 EX_ROW_EN[0] = 0x0
6885 23:06:27.164235 EX_ROW_EN[1] = 0x0
6886 23:06:27.164315 LP4Y_EN = 0x0
6887 23:06:27.167455 WORK_FSP = 0x1
6888 23:06:27.167535 WL = 0x5
6889 23:06:27.170778 RL = 0x5
6890 23:06:27.174239 BL = 0x2
6891 23:06:27.174319 RPST = 0x0
6892 23:06:27.177329 RD_PRE = 0x0
6893 23:06:27.177409 WR_PRE = 0x1
6894 23:06:27.180808 WR_PST = 0x1
6895 23:06:27.180888 DBI_WR = 0x0
6896 23:06:27.184039 DBI_RD = 0x0
6897 23:06:27.184118 OTF = 0x1
6898 23:06:27.187556 ===================================
6899 23:06:27.190739 ===================================
6900 23:06:27.194225 ANA top config
6901 23:06:27.197302 ===================================
6902 23:06:27.197383 DLL_ASYNC_EN = 0
6903 23:06:27.200545 ALL_SLAVE_EN = 0
6904 23:06:27.203973 NEW_RANK_MODE = 1
6905 23:06:27.207200 DLL_IDLE_MODE = 1
6906 23:06:27.207280 LP45_APHY_COMB_EN = 1
6907 23:06:27.210477 TX_ODT_DIS = 0
6908 23:06:27.213893 NEW_8X_MODE = 1
6909 23:06:27.217156 ===================================
6910 23:06:27.220326 ===================================
6911 23:06:27.223651 data_rate = 3200
6912 23:06:27.227284 CKR = 1
6913 23:06:27.230599 DQ_P2S_RATIO = 8
6914 23:06:27.233503 ===================================
6915 23:06:27.233583 CA_P2S_RATIO = 8
6916 23:06:27.236924 DQ_CA_OPEN = 0
6917 23:06:27.240310 DQ_SEMI_OPEN = 0
6918 23:06:27.243421 CA_SEMI_OPEN = 0
6919 23:06:27.246900 CA_FULL_RATE = 0
6920 23:06:27.250108 DQ_CKDIV4_EN = 0
6921 23:06:27.250188 CA_CKDIV4_EN = 0
6922 23:06:27.253408 CA_PREDIV_EN = 0
6923 23:06:27.256724 PH8_DLY = 12
6924 23:06:27.259975 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6925 23:06:27.263387 DQ_AAMCK_DIV = 4
6926 23:06:27.266783 CA_AAMCK_DIV = 4
6927 23:06:27.266862 CA_ADMCK_DIV = 4
6928 23:06:27.269666 DQ_TRACK_CA_EN = 0
6929 23:06:27.273190 CA_PICK = 1600
6930 23:06:27.276371 CA_MCKIO = 1600
6931 23:06:27.279613 MCKIO_SEMI = 0
6932 23:06:27.283039 PLL_FREQ = 3068
6933 23:06:27.286253 DQ_UI_PI_RATIO = 32
6934 23:06:27.289514 CA_UI_PI_RATIO = 0
6935 23:06:27.292928 ===================================
6936 23:06:27.296715 ===================================
6937 23:06:27.296796 memory_type:LPDDR4
6938 23:06:27.299607 GP_NUM : 10
6939 23:06:27.303005 SRAM_EN : 1
6940 23:06:27.303085 MD32_EN : 0
6941 23:06:27.306362 ===================================
6942 23:06:27.309550 [ANA_INIT] >>>>>>>>>>>>>>
6943 23:06:27.312952 <<<<<< [CONFIGURE PHASE]: ANA_TX
6944 23:06:27.315815 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6945 23:06:27.319364 ===================================
6946 23:06:27.323067 data_rate = 3200,PCW = 0X7600
6947 23:06:27.325782 ===================================
6948 23:06:27.329597 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6949 23:06:27.332654 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6950 23:06:27.339336 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6951 23:06:27.342473 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6952 23:06:27.346095 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6953 23:06:27.349444 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6954 23:06:27.352431 [ANA_INIT] flow start
6955 23:06:27.355701 [ANA_INIT] PLL >>>>>>>>
6956 23:06:27.355780 [ANA_INIT] PLL <<<<<<<<
6957 23:06:27.359255 [ANA_INIT] MIDPI >>>>>>>>
6958 23:06:27.362442 [ANA_INIT] MIDPI <<<<<<<<
6959 23:06:27.365706 [ANA_INIT] DLL >>>>>>>>
6960 23:06:27.365786 [ANA_INIT] DLL <<<<<<<<
6961 23:06:27.368885 [ANA_INIT] flow end
6962 23:06:27.372433 ============ LP4 DIFF to SE enter ============
6963 23:06:27.375594 ============ LP4 DIFF to SE exit ============
6964 23:06:27.379021 [ANA_INIT] <<<<<<<<<<<<<
6965 23:06:27.382121 [Flow] Enable top DCM control >>>>>
6966 23:06:27.385405 [Flow] Enable top DCM control <<<<<
6967 23:06:27.388889 Enable DLL master slave shuffle
6968 23:06:27.395297 ==============================================================
6969 23:06:27.395393 Gating Mode config
6970 23:06:27.401926 ==============================================================
6971 23:06:27.402006 Config description:
6972 23:06:27.411874 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6973 23:06:27.418597 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6974 23:06:27.425250 SELPH_MODE 0: By rank 1: By Phase
6975 23:06:27.428364 ==============================================================
6976 23:06:27.431612 GAT_TRACK_EN = 1
6977 23:06:27.434819 RX_GATING_MODE = 2
6978 23:06:27.438116 RX_GATING_TRACK_MODE = 2
6979 23:06:27.441919 SELPH_MODE = 1
6980 23:06:27.444994 PICG_EARLY_EN = 1
6981 23:06:27.448315 VALID_LAT_VALUE = 1
6982 23:06:27.454838 ==============================================================
6983 23:06:27.458175 Enter into Gating configuration >>>>
6984 23:06:27.461431 Exit from Gating configuration <<<<
6985 23:06:27.464686 Enter into DVFS_PRE_config >>>>>
6986 23:06:27.474564 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6987 23:06:27.477901 Exit from DVFS_PRE_config <<<<<
6988 23:06:27.481271 Enter into PICG configuration >>>>
6989 23:06:27.484701 Exit from PICG configuration <<<<
6990 23:06:27.487977 [RX_INPUT] configuration >>>>>
6991 23:06:27.488057 [RX_INPUT] configuration <<<<<
6992 23:06:27.494762 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6993 23:06:27.501189 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6994 23:06:27.504393 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6995 23:06:27.511138 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6996 23:06:27.517736 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6997 23:06:27.524224 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6998 23:06:27.527585 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6999 23:06:27.531174 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7000 23:06:27.537487 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7001 23:06:27.540671 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7002 23:06:27.544434 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7003 23:06:27.550899 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7004 23:06:27.554150 ===================================
7005 23:06:27.554233 LPDDR4 DRAM CONFIGURATION
7006 23:06:27.557306 ===================================
7007 23:06:27.560840 EX_ROW_EN[0] = 0x0
7008 23:06:27.563823 EX_ROW_EN[1] = 0x0
7009 23:06:27.563903 LP4Y_EN = 0x0
7010 23:06:27.567691 WORK_FSP = 0x1
7011 23:06:27.567771 WL = 0x5
7012 23:06:27.570632 RL = 0x5
7013 23:06:27.570711 BL = 0x2
7014 23:06:27.574146 RPST = 0x0
7015 23:06:27.574254 RD_PRE = 0x0
7016 23:06:27.577015 WR_PRE = 0x1
7017 23:06:27.577095 WR_PST = 0x1
7018 23:06:27.580363 DBI_WR = 0x0
7019 23:06:27.580468 DBI_RD = 0x0
7020 23:06:27.583580 OTF = 0x1
7021 23:06:27.587040 ===================================
7022 23:06:27.590291 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7023 23:06:27.593750 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7024 23:06:27.600436 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7025 23:06:27.603414 ===================================
7026 23:06:27.603494 LPDDR4 DRAM CONFIGURATION
7027 23:06:27.606831 ===================================
7028 23:06:27.610062 EX_ROW_EN[0] = 0x10
7029 23:06:27.613410 EX_ROW_EN[1] = 0x0
7030 23:06:27.613490 LP4Y_EN = 0x0
7031 23:06:27.617028 WORK_FSP = 0x1
7032 23:06:27.617108 WL = 0x5
7033 23:06:27.620062 RL = 0x5
7034 23:06:27.620142 BL = 0x2
7035 23:06:27.623583 RPST = 0x0
7036 23:06:27.623662 RD_PRE = 0x0
7037 23:06:27.626594 WR_PRE = 0x1
7038 23:06:27.626673 WR_PST = 0x1
7039 23:06:27.629957 DBI_WR = 0x0
7040 23:06:27.630037 DBI_RD = 0x0
7041 23:06:27.633481 OTF = 0x1
7042 23:06:27.636512 ===================================
7043 23:06:27.643502 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7044 23:06:27.643582 ==
7045 23:06:27.646272 Dram Type= 6, Freq= 0, CH_0, rank 0
7046 23:06:27.649781 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7047 23:06:27.649862 ==
7048 23:06:27.653569 [Duty_Offset_Calibration]
7049 23:06:27.653655 B0:0 B1:2 CA:1
7050 23:06:27.653738
7051 23:06:27.656487 [DutyScan_Calibration_Flow] k_type=0
7052 23:06:27.667003
7053 23:06:27.667082 ==CLK 0==
7054 23:06:27.670511 Final CLK duty delay cell = 0
7055 23:06:27.673408 [0] MAX Duty = 5187%(X100), DQS PI = 24
7056 23:06:27.676745 [0] MIN Duty = 4938%(X100), DQS PI = 52
7057 23:06:27.676825 [0] AVG Duty = 5062%(X100)
7058 23:06:27.680121
7059 23:06:27.683647 CH0 CLK Duty spec in!! Max-Min= 249%
7060 23:06:27.686678 [DutyScan_Calibration_Flow] ====Done====
7061 23:06:27.686758
7062 23:06:27.690058 [DutyScan_Calibration_Flow] k_type=1
7063 23:06:27.707605
7064 23:06:27.707686 ==DQS 0 ==
7065 23:06:27.710366 Final DQS duty delay cell = 0
7066 23:06:27.713424 [0] MAX Duty = 5156%(X100), DQS PI = 34
7067 23:06:27.717009 [0] MIN Duty = 5031%(X100), DQS PI = 8
7068 23:06:27.720299 [0] AVG Duty = 5093%(X100)
7069 23:06:27.720379
7070 23:06:27.720441 ==DQS 1 ==
7071 23:06:27.723562 Final DQS duty delay cell = 0
7072 23:06:27.727104 [0] MAX Duty = 5031%(X100), DQS PI = 2
7073 23:06:27.730299 [0] MIN Duty = 4876%(X100), DQS PI = 16
7074 23:06:27.730379 [0] AVG Duty = 4953%(X100)
7075 23:06:27.733364
7076 23:06:27.736924 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7077 23:06:27.737004
7078 23:06:27.739887 CH0 DQS 1 Duty spec in!! Max-Min= 155%
7079 23:06:27.743373 [DutyScan_Calibration_Flow] ====Done====
7080 23:06:27.743453
7081 23:06:27.746538 [DutyScan_Calibration_Flow] k_type=3
7082 23:06:27.764220
7083 23:06:27.764300 ==DQM 0 ==
7084 23:06:27.767244 Final DQM duty delay cell = 0
7085 23:06:27.770536 [0] MAX Duty = 5187%(X100), DQS PI = 22
7086 23:06:27.774206 [0] MIN Duty = 4907%(X100), DQS PI = 42
7087 23:06:27.777182 [0] AVG Duty = 5047%(X100)
7088 23:06:27.777263
7089 23:06:27.777326 ==DQM 1 ==
7090 23:06:27.780469 Final DQM duty delay cell = 0
7091 23:06:27.783823 [0] MAX Duty = 5031%(X100), DQS PI = 50
7092 23:06:27.787177 [0] MIN Duty = 4782%(X100), DQS PI = 12
7093 23:06:27.790540 [0] AVG Duty = 4906%(X100)
7094 23:06:27.790620
7095 23:06:27.793670 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7096 23:06:27.793750
7097 23:06:27.797009 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7098 23:06:27.800572 [DutyScan_Calibration_Flow] ====Done====
7099 23:06:27.800652
7100 23:06:27.803673 [DutyScan_Calibration_Flow] k_type=2
7101 23:06:27.820667
7102 23:06:27.820760 ==DQ 0 ==
7103 23:06:27.823669 Final DQ duty delay cell = 0
7104 23:06:27.827318 [0] MAX Duty = 5218%(X100), DQS PI = 18
7105 23:06:27.830190 [0] MIN Duty = 4938%(X100), DQS PI = 56
7106 23:06:27.830271 [0] AVG Duty = 5078%(X100)
7107 23:06:27.833573
7108 23:06:27.833652 ==DQ 1 ==
7109 23:06:27.836712 Final DQ duty delay cell = -4
7110 23:06:27.840251 [-4] MAX Duty = 5062%(X100), DQS PI = 4
7111 23:06:27.843389 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7112 23:06:27.847125 [-4] AVG Duty = 4953%(X100)
7113 23:06:27.847204
7114 23:06:27.850233 CH0 DQ 0 Duty spec in!! Max-Min= 280%
7115 23:06:27.850313
7116 23:06:27.853527 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7117 23:06:27.856906 [DutyScan_Calibration_Flow] ====Done====
7118 23:06:27.856986 ==
7119 23:06:27.859909 Dram Type= 6, Freq= 0, CH_1, rank 0
7120 23:06:27.863237 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7121 23:06:27.863318 ==
7122 23:06:27.866820 [Duty_Offset_Calibration]
7123 23:06:27.866900 B0:0 B1:5 CA:-5
7124 23:06:27.866971
7125 23:06:27.870287 [DutyScan_Calibration_Flow] k_type=0
7126 23:06:27.880843
7127 23:06:27.880955 ==CLK 0==
7128 23:06:27.884204 Final CLK duty delay cell = 0
7129 23:06:27.887620 [0] MAX Duty = 5156%(X100), DQS PI = 20
7130 23:06:27.890984 [0] MIN Duty = 4906%(X100), DQS PI = 50
7131 23:06:27.894079 [0] AVG Duty = 5031%(X100)
7132 23:06:27.894159
7133 23:06:27.897353 CH1 CLK Duty spec in!! Max-Min= 250%
7134 23:06:27.900897 [DutyScan_Calibration_Flow] ====Done====
7135 23:06:27.900978
7136 23:06:27.904040 [DutyScan_Calibration_Flow] k_type=1
7137 23:06:27.920015
7138 23:06:27.920095 ==DQS 0 ==
7139 23:06:27.923191 Final DQS duty delay cell = 0
7140 23:06:27.926694 [0] MAX Duty = 5187%(X100), DQS PI = 20
7141 23:06:27.929996 [0] MIN Duty = 4876%(X100), DQS PI = 42
7142 23:06:27.933138 [0] AVG Duty = 5031%(X100)
7143 23:06:27.933217
7144 23:06:27.933280 ==DQS 1 ==
7145 23:06:27.936310 Final DQS duty delay cell = -4
7146 23:06:27.939868 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7147 23:06:27.942985 [-4] MIN Duty = 4844%(X100), DQS PI = 38
7148 23:06:27.946253 [-4] AVG Duty = 4922%(X100)
7149 23:06:27.946333
7150 23:06:27.949665 CH1 DQS 0 Duty spec in!! Max-Min= 311%
7151 23:06:27.949745
7152 23:06:27.953332 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7153 23:06:27.956662 [DutyScan_Calibration_Flow] ====Done====
7154 23:06:27.956742
7155 23:06:27.959734 [DutyScan_Calibration_Flow] k_type=3
7156 23:06:27.975771
7157 23:06:27.975851 ==DQM 0 ==
7158 23:06:27.979004 Final DQM duty delay cell = -4
7159 23:06:27.982222 [-4] MAX Duty = 5062%(X100), DQS PI = 34
7160 23:06:27.985754 [-4] MIN Duty = 4813%(X100), DQS PI = 42
7161 23:06:27.988941 [-4] AVG Duty = 4937%(X100)
7162 23:06:27.989021
7163 23:06:27.989083 ==DQM 1 ==
7164 23:06:27.992357 Final DQM duty delay cell = -4
7165 23:06:27.995657 [-4] MAX Duty = 5062%(X100), DQS PI = 18
7166 23:06:27.998759 [-4] MIN Duty = 4907%(X100), DQS PI = 36
7167 23:06:28.001914 [-4] AVG Duty = 4984%(X100)
7168 23:06:28.001994
7169 23:06:28.005961 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7170 23:06:28.006041
7171 23:06:28.009155 CH1 DQM 1 Duty spec in!! Max-Min= 155%
7172 23:06:28.012031 [DutyScan_Calibration_Flow] ====Done====
7173 23:06:28.012111
7174 23:06:28.015186 [DutyScan_Calibration_Flow] k_type=2
7175 23:06:28.033442
7176 23:06:28.033521 ==DQ 0 ==
7177 23:06:28.036715 Final DQ duty delay cell = 0
7178 23:06:28.039866 [0] MAX Duty = 5093%(X100), DQS PI = 20
7179 23:06:28.043042 [0] MIN Duty = 4969%(X100), DQS PI = 44
7180 23:06:28.046416 [0] AVG Duty = 5031%(X100)
7181 23:06:28.046495
7182 23:06:28.046557 ==DQ 1 ==
7183 23:06:28.049559 Final DQ duty delay cell = 0
7184 23:06:28.052809 [0] MAX Duty = 5031%(X100), DQS PI = 4
7185 23:06:28.056142 [0] MIN Duty = 4875%(X100), DQS PI = 28
7186 23:06:28.056222 [0] AVG Duty = 4953%(X100)
7187 23:06:28.059449
7188 23:06:28.063004 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7189 23:06:28.063084
7190 23:06:28.066485 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7191 23:06:28.069865 [DutyScan_Calibration_Flow] ====Done====
7192 23:06:28.073167 nWR fixed to 30
7193 23:06:28.073247 [ModeRegInit_LP4] CH0 RK0
7194 23:06:28.076178 [ModeRegInit_LP4] CH0 RK1
7195 23:06:28.079563 [ModeRegInit_LP4] CH1 RK0
7196 23:06:28.083024 [ModeRegInit_LP4] CH1 RK1
7197 23:06:28.083103 match AC timing 4
7198 23:06:28.089670 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7199 23:06:28.092682 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7200 23:06:28.096169 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7201 23:06:28.103025 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7202 23:06:28.105954 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7203 23:06:28.106033 [MiockJmeterHQA]
7204 23:06:28.106096
7205 23:06:28.109284 [DramcMiockJmeter] u1RxGatingPI = 0
7206 23:06:28.112620 0 : 4252, 4027
7207 23:06:28.112702 4 : 4253, 4027
7208 23:06:28.115943 8 : 4363, 4137
7209 23:06:28.116023 12 : 4254, 4029
7210 23:06:28.116087 16 : 4363, 4137
7211 23:06:28.119458 20 : 4253, 4027
7212 23:06:28.119538 24 : 4361, 4138
7213 23:06:28.122621 28 : 4253, 4027
7214 23:06:28.122701 32 : 4250, 4026
7215 23:06:28.125979 36 : 4250, 4027
7216 23:06:28.126060 40 : 4361, 4137
7217 23:06:28.129186 44 : 4361, 4137
7218 23:06:28.129267 48 : 4250, 4027
7219 23:06:28.129331 52 : 4250, 4027
7220 23:06:28.132646 56 : 4250, 4027
7221 23:06:28.132726 60 : 4250, 4027
7222 23:06:28.135935 64 : 4253, 4029
7223 23:06:28.136015 68 : 4361, 4138
7224 23:06:28.139455 72 : 4250, 4027
7225 23:06:28.139536 76 : 4250, 4027
7226 23:06:28.142361 80 : 4250, 4027
7227 23:06:28.142441 84 : 4253, 4029
7228 23:06:28.142504 88 : 4250, 4027
7229 23:06:28.145778 92 : 4361, 4137
7230 23:06:28.145859 96 : 4361, 4137
7231 23:06:28.148935 100 : 4250, 2200
7232 23:06:28.149016 104 : 4360, 0
7233 23:06:28.152122 108 : 4360, 0
7234 23:06:28.152202 112 : 4361, 0
7235 23:06:28.152266 116 : 4250, 0
7236 23:06:28.155561 120 : 4251, 0
7237 23:06:28.155642 124 : 4250, 0
7238 23:06:28.158887 128 : 4250, 0
7239 23:06:28.158967 132 : 4250, 0
7240 23:06:28.159031 136 : 4250, 0
7241 23:06:28.162262 140 : 4253, 0
7242 23:06:28.162343 144 : 4250, 0
7243 23:06:28.162407 148 : 4250, 0
7244 23:06:28.165682 152 : 4252, 0
7245 23:06:28.165763 156 : 4361, 0
7246 23:06:28.168728 160 : 4250, 0
7247 23:06:28.168809 164 : 4250, 0
7248 23:06:28.168873 168 : 4361, 0
7249 23:06:28.172049 172 : 4250, 0
7250 23:06:28.172129 176 : 4250, 0
7251 23:06:28.175294 180 : 4250, 0
7252 23:06:28.175374 184 : 4250, 0
7253 23:06:28.175439 188 : 4250, 0
7254 23:06:28.178813 192 : 4253, 0
7255 23:06:28.178893 196 : 4250, 0
7256 23:06:28.181843 200 : 4250, 0
7257 23:06:28.181924 204 : 4252, 0
7258 23:06:28.181988 208 : 4250, 0
7259 23:06:28.185295 212 : 4360, 0
7260 23:06:28.185376 216 : 4250, 0
7261 23:06:28.188396 220 : 4361, 421
7262 23:06:28.188476 224 : 4250, 3941
7263 23:06:28.192286 228 : 4360, 4137
7264 23:06:28.192367 232 : 4250, 4027
7265 23:06:28.192430 236 : 4250, 4027
7266 23:06:28.195142 240 : 4363, 4139
7267 23:06:28.195222 244 : 4250, 4027
7268 23:06:28.198307 248 : 4252, 4030
7269 23:06:28.198388 252 : 4250, 4026
7270 23:06:28.201858 256 : 4253, 4030
7271 23:06:28.201939 260 : 4250, 4027
7272 23:06:28.205179 264 : 4250, 4027
7273 23:06:28.205260 268 : 4361, 4137
7274 23:06:28.208615 272 : 4250, 4026
7275 23:06:28.208696 276 : 4250, 4027
7276 23:06:28.211722 280 : 4361, 4137
7277 23:06:28.211803 284 : 4250, 4027
7278 23:06:28.215048 288 : 4250, 4027
7279 23:06:28.215128 292 : 4363, 4139
7280 23:06:28.215191 296 : 4250, 4027
7281 23:06:28.218173 300 : 4250, 4027
7282 23:06:28.218254 304 : 4250, 4026
7283 23:06:28.221789 308 : 4253, 4029
7284 23:06:28.221870 312 : 4250, 4027
7285 23:06:28.224906 316 : 4250, 4027
7286 23:06:28.224986 320 : 4361, 4137
7287 23:06:28.228448 324 : 4250, 4027
7288 23:06:28.228568 328 : 4250, 4027
7289 23:06:28.231426 332 : 4360, 4138
7290 23:06:28.231506 336 : 4250, 3869
7291 23:06:28.234855 340 : 4250, 2028
7292 23:06:28.234936
7293 23:06:28.234999 MIOCK jitter meter ch=0
7294 23:06:28.235060
7295 23:06:28.238809 1T = (340-104) = 236 dly cells
7296 23:06:28.244802 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7297 23:06:28.244883 ==
7298 23:06:28.248340 Dram Type= 6, Freq= 0, CH_0, rank 0
7299 23:06:28.251566 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7300 23:06:28.251647 ==
7301 23:06:28.257851 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7302 23:06:28.261678 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7303 23:06:28.267899 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7304 23:06:28.271367 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7305 23:06:28.280441 [CA 0] Center 43 (13~73) winsize 61
7306 23:06:28.283703 [CA 1] Center 42 (12~73) winsize 62
7307 23:06:28.286958 [CA 2] Center 39 (9~69) winsize 61
7308 23:06:28.290575 [CA 3] Center 38 (9~68) winsize 60
7309 23:06:28.293572 [CA 4] Center 36 (6~67) winsize 62
7310 23:06:28.297255 [CA 5] Center 36 (6~66) winsize 61
7311 23:06:28.297336
7312 23:06:28.300483 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7313 23:06:28.300575
7314 23:06:28.303561 [CATrainingPosCal] consider 1 rank data
7315 23:06:28.306971 u2DelayCellTimex100 = 275/100 ps
7316 23:06:28.313472 CA0 delay=43 (13~73),Diff = 7 PI (24 cell)
7317 23:06:28.317167 CA1 delay=42 (12~73),Diff = 6 PI (21 cell)
7318 23:06:28.320126 CA2 delay=39 (9~69),Diff = 3 PI (10 cell)
7319 23:06:28.323438 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7320 23:06:28.326687 CA4 delay=36 (6~67),Diff = 0 PI (0 cell)
7321 23:06:28.329909 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7322 23:06:28.329988
7323 23:06:28.333337 CA PerBit enable=1, Macro0, CA PI delay=36
7324 23:06:28.333416
7325 23:06:28.336894 [CBTSetCACLKResult] CA Dly = 36
7326 23:06:28.339934 CS Dly: 10 (0~41)
7327 23:06:28.343625 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7328 23:06:28.346742 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7329 23:06:28.346821 ==
7330 23:06:28.349976 Dram Type= 6, Freq= 0, CH_0, rank 1
7331 23:06:28.356813 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7332 23:06:28.356894 ==
7333 23:06:28.359895 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7334 23:06:28.363352 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7335 23:06:28.370112 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7336 23:06:28.376460 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7337 23:06:28.383336 [CA 0] Center 42 (12~73) winsize 62
7338 23:06:28.386469 [CA 1] Center 41 (11~72) winsize 62
7339 23:06:28.390071 [CA 2] Center 38 (9~68) winsize 60
7340 23:06:28.393279 [CA 3] Center 37 (7~67) winsize 61
7341 23:06:28.396325 [CA 4] Center 35 (5~65) winsize 61
7342 23:06:28.399731 [CA 5] Center 35 (5~66) winsize 62
7343 23:06:28.399810
7344 23:06:28.403117 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7345 23:06:28.403198
7346 23:06:28.406315 [CATrainingPosCal] consider 2 rank data
7347 23:06:28.409657 u2DelayCellTimex100 = 275/100 ps
7348 23:06:28.413252 CA0 delay=43 (13~73),Diff = 8 PI (28 cell)
7349 23:06:28.419875 CA1 delay=42 (12~72),Diff = 7 PI (24 cell)
7350 23:06:28.422775 CA2 delay=38 (9~68),Diff = 3 PI (10 cell)
7351 23:06:28.426796 CA3 delay=38 (9~67),Diff = 3 PI (10 cell)
7352 23:06:28.429541 CA4 delay=35 (6~65),Diff = 0 PI (0 cell)
7353 23:06:28.432924 CA5 delay=36 (6~66),Diff = 1 PI (3 cell)
7354 23:06:28.433004
7355 23:06:28.436216 CA PerBit enable=1, Macro0, CA PI delay=35
7356 23:06:28.436296
7357 23:06:28.439342 [CBTSetCACLKResult] CA Dly = 35
7358 23:06:28.442671 CS Dly: 11 (0~43)
7359 23:06:28.445847 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7360 23:06:28.449410 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7361 23:06:28.449489
7362 23:06:28.452405 ----->DramcWriteLeveling(PI) begin...
7363 23:06:28.452486 ==
7364 23:06:28.456007 Dram Type= 6, Freq= 0, CH_0, rank 0
7365 23:06:28.462793 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7366 23:06:28.462874 ==
7367 23:06:28.465924 Write leveling (Byte 0): 29 => 29
7368 23:06:28.469344 Write leveling (Byte 1): 26 => 26
7369 23:06:28.469424 DramcWriteLeveling(PI) end<-----
7370 23:06:28.469486
7371 23:06:28.472641 ==
7372 23:06:28.475673 Dram Type= 6, Freq= 0, CH_0, rank 0
7373 23:06:28.479126 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7374 23:06:28.479251 ==
7375 23:06:28.482800 [Gating] SW mode calibration
7376 23:06:28.489026 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7377 23:06:28.492225 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7378 23:06:28.499012 0 12 0 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7379 23:06:28.502324 0 12 4 | B1->B0 | 2929 3434 | 1 1 | (1 1) (1 1)
7380 23:06:28.505600 0 12 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7381 23:06:28.512316 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7382 23:06:28.515489 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7383 23:06:28.518733 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7384 23:06:28.525355 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7385 23:06:28.528694 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7386 23:06:28.531977 0 13 0 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 0)
7387 23:06:28.539016 0 13 4 | B1->B0 | 3131 2525 | 0 0 | (0 1) (0 0)
7388 23:06:28.542470 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7389 23:06:28.545199 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7390 23:06:28.552017 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7391 23:06:28.555518 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7392 23:06:28.558447 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7393 23:06:28.565294 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7394 23:06:28.568771 0 14 0 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
7395 23:06:28.571782 0 14 4 | B1->B0 | 3232 4646 | 0 0 | (0 0) (0 0)
7396 23:06:28.578604 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7397 23:06:28.581790 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7398 23:06:28.585107 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7399 23:06:28.591756 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7400 23:06:28.594892 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7401 23:06:28.598385 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7402 23:06:28.604649 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7403 23:06:28.608260 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7404 23:06:28.611287 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7405 23:06:28.617971 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7406 23:06:28.621520 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7407 23:06:28.624637 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7408 23:06:28.631383 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7409 23:06:28.634708 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7410 23:06:28.638091 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7411 23:06:28.644736 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7412 23:06:28.647997 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7413 23:06:28.651161 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7414 23:06:28.658112 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7415 23:06:28.661187 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7416 23:06:28.664427 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7417 23:06:28.670952 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7418 23:06:28.674382 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7419 23:06:28.677685 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7420 23:06:28.680796 Total UI for P1: 0, mck2ui 16
7421 23:06:28.684100 best dqsien dly found for B0: ( 1, 0, 30)
7422 23:06:28.687594 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7423 23:06:28.694218 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7424 23:06:28.697449 Total UI for P1: 0, mck2ui 16
7425 23:06:28.701006 best dqsien dly found for B1: ( 1, 1, 6)
7426 23:06:28.704036 best DQS0 dly(MCK, UI, PI) = (1, 0, 30)
7427 23:06:28.707323 best DQS1 dly(MCK, UI, PI) = (1, 1, 6)
7428 23:06:28.707406
7429 23:06:28.710818 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 30)
7430 23:06:28.713888 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 6)
7431 23:06:28.717286 [Gating] SW calibration Done
7432 23:06:28.717367 ==
7433 23:06:28.720630 Dram Type= 6, Freq= 0, CH_0, rank 0
7434 23:06:28.723992 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7435 23:06:28.724074 ==
7436 23:06:28.727169 RX Vref Scan: 0
7437 23:06:28.727251
7438 23:06:28.730610 RX Vref 0 -> 0, step: 1
7439 23:06:28.730693
7440 23:06:28.730775 RX Delay 0 -> 252, step: 8
7441 23:06:28.733948 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7442 23:06:28.740461 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7443 23:06:28.744188 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
7444 23:06:28.747231 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7445 23:06:28.750429 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7446 23:06:28.753853 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7447 23:06:28.760742 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7448 23:06:28.764123 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7449 23:06:28.767021 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
7450 23:06:28.770362 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7451 23:06:28.776803 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7452 23:06:28.780186 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7453 23:06:28.783437 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7454 23:06:28.786861 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7455 23:06:28.790236 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
7456 23:06:28.796741 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7457 23:06:28.796823 ==
7458 23:06:28.800212 Dram Type= 6, Freq= 0, CH_0, rank 0
7459 23:06:28.803377 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7460 23:06:28.803460 ==
7461 23:06:28.803544 DQS Delay:
7462 23:06:28.806781 DQS0 = 0, DQS1 = 0
7463 23:06:28.806863 DQM Delay:
7464 23:06:28.809980 DQM0 = 130, DQM1 = 124
7465 23:06:28.810062 DQ Delay:
7466 23:06:28.813308 DQ0 =127, DQ1 =131, DQ2 =123, DQ3 =127
7467 23:06:28.816740 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7468 23:06:28.819932 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
7469 23:06:28.823474 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7470 23:06:28.823556
7471 23:06:28.826455
7472 23:06:28.826536 ==
7473 23:06:28.830077 Dram Type= 6, Freq= 0, CH_0, rank 0
7474 23:06:28.833281 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7475 23:06:28.833363 ==
7476 23:06:28.833447
7477 23:06:28.833526
7478 23:06:28.836734 TX Vref Scan disable
7479 23:06:28.836816 == TX Byte 0 ==
7480 23:06:28.843113 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7481 23:06:28.846597 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7482 23:06:28.846679 == TX Byte 1 ==
7483 23:06:28.853175 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7484 23:06:28.856373 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7485 23:06:28.856455 ==
7486 23:06:28.859451 Dram Type= 6, Freq= 0, CH_0, rank 0
7487 23:06:28.863136 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7488 23:06:28.863219 ==
7489 23:06:28.876267
7490 23:06:28.880117 TX Vref early break, caculate TX vref
7491 23:06:28.883033 TX Vref=16, minBit 8, minWin=21, winSum=372
7492 23:06:28.886214 TX Vref=18, minBit 9, minWin=22, winSum=381
7493 23:06:28.889782 TX Vref=20, minBit 9, minWin=22, winSum=390
7494 23:06:28.892899 TX Vref=22, minBit 11, minWin=23, winSum=401
7495 23:06:28.896304 TX Vref=24, minBit 9, minWin=24, winSum=405
7496 23:06:28.902952 TX Vref=26, minBit 7, minWin=25, winSum=411
7497 23:06:28.906186 TX Vref=28, minBit 8, minWin=25, winSum=416
7498 23:06:28.909538 TX Vref=30, minBit 0, minWin=25, winSum=412
7499 23:06:28.912945 TX Vref=32, minBit 6, minWin=24, winSum=400
7500 23:06:28.916388 TX Vref=34, minBit 8, minWin=23, winSum=391
7501 23:06:28.922905 [TxChooseVref] Worse bit 8, Min win 25, Win sum 416, Final Vref 28
7502 23:06:28.922986
7503 23:06:28.926320 Final TX Range 0 Vref 28
7504 23:06:28.926400
7505 23:06:28.926463 ==
7506 23:06:28.929486 Dram Type= 6, Freq= 0, CH_0, rank 0
7507 23:06:28.932880 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7508 23:06:28.932961 ==
7509 23:06:28.933024
7510 23:06:28.933082
7511 23:06:28.936002 TX Vref Scan disable
7512 23:06:28.942888 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7513 23:06:28.942968 == TX Byte 0 ==
7514 23:06:28.945866 u2DelayCellOfst[0]=10 cells (3 PI)
7515 23:06:28.949210 u2DelayCellOfst[1]=17 cells (5 PI)
7516 23:06:28.952466 u2DelayCellOfst[2]=14 cells (4 PI)
7517 23:06:28.955966 u2DelayCellOfst[3]=10 cells (3 PI)
7518 23:06:28.959222 u2DelayCellOfst[4]=10 cells (3 PI)
7519 23:06:28.962627 u2DelayCellOfst[5]=0 cells (0 PI)
7520 23:06:28.965826 u2DelayCellOfst[6]=17 cells (5 PI)
7521 23:06:28.969455 u2DelayCellOfst[7]=17 cells (5 PI)
7522 23:06:28.972609 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7523 23:06:28.975930 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7524 23:06:28.979202 == TX Byte 1 ==
7525 23:06:28.982525 u2DelayCellOfst[8]=3 cells (1 PI)
7526 23:06:28.982611 u2DelayCellOfst[9]=0 cells (0 PI)
7527 23:06:28.985686 u2DelayCellOfst[10]=10 cells (3 PI)
7528 23:06:28.989033 u2DelayCellOfst[11]=7 cells (2 PI)
7529 23:06:28.992412 u2DelayCellOfst[12]=14 cells (4 PI)
7530 23:06:28.995586 u2DelayCellOfst[13]=14 cells (4 PI)
7531 23:06:28.998852 u2DelayCellOfst[14]=17 cells (5 PI)
7532 23:06:29.002459 u2DelayCellOfst[15]=17 cells (5 PI)
7533 23:06:29.005736 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
7534 23:06:29.012117 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7535 23:06:29.012223 DramC Write-DBI on
7536 23:06:29.012313 ==
7537 23:06:29.015472 Dram Type= 6, Freq= 0, CH_0, rank 0
7538 23:06:29.022203 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7539 23:06:29.022283 ==
7540 23:06:29.022347
7541 23:06:29.022404
7542 23:06:29.022460 TX Vref Scan disable
7543 23:06:29.025972 == TX Byte 0 ==
7544 23:06:29.029440 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7545 23:06:29.033027 == TX Byte 1 ==
7546 23:06:29.035999 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
7547 23:06:29.039566 DramC Write-DBI off
7548 23:06:29.039646
7549 23:06:29.039708 [DATLAT]
7550 23:06:29.039766 Freq=1600, CH0 RK0
7551 23:06:29.039823
7552 23:06:29.042597 DATLAT Default: 0xf
7553 23:06:29.042678 0, 0xFFFF, sum = 0
7554 23:06:29.045830 1, 0xFFFF, sum = 0
7555 23:06:29.049219 2, 0xFFFF, sum = 0
7556 23:06:29.049299 3, 0xFFFF, sum = 0
7557 23:06:29.052472 4, 0xFFFF, sum = 0
7558 23:06:29.052570 5, 0xFFFF, sum = 0
7559 23:06:29.055963 6, 0xFFFF, sum = 0
7560 23:06:29.056054 7, 0xFFFF, sum = 0
7561 23:06:29.059271 8, 0xFFFF, sum = 0
7562 23:06:29.059352 9, 0xFFFF, sum = 0
7563 23:06:29.062560 10, 0xFFFF, sum = 0
7564 23:06:29.062641 11, 0xFFFF, sum = 0
7565 23:06:29.065776 12, 0xFFF, sum = 0
7566 23:06:29.065857 13, 0x0, sum = 1
7567 23:06:29.068995 14, 0x0, sum = 2
7568 23:06:29.069076 15, 0x0, sum = 3
7569 23:06:29.072338 16, 0x0, sum = 4
7570 23:06:29.072419 best_step = 14
7571 23:06:29.072482
7572 23:06:29.072589 ==
7573 23:06:29.075998 Dram Type= 6, Freq= 0, CH_0, rank 0
7574 23:06:29.079153 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7575 23:06:29.082220 ==
7576 23:06:29.082300 RX Vref Scan: 1
7577 23:06:29.082362
7578 23:06:29.085527 Set Vref Range= 24 -> 127
7579 23:06:29.085607
7580 23:06:29.088725 RX Vref 24 -> 127, step: 1
7581 23:06:29.088805
7582 23:06:29.088868 RX Delay 11 -> 252, step: 4
7583 23:06:29.088927
7584 23:06:29.092277 Set Vref, RX VrefLevel [Byte0]: 24
7585 23:06:29.095532 [Byte1]: 24
7586 23:06:29.099263
7587 23:06:29.099343 Set Vref, RX VrefLevel [Byte0]: 25
7588 23:06:29.102776 [Byte1]: 25
7589 23:06:29.107031
7590 23:06:29.107114 Set Vref, RX VrefLevel [Byte0]: 26
7591 23:06:29.110294 [Byte1]: 26
7592 23:06:29.114601
7593 23:06:29.114680 Set Vref, RX VrefLevel [Byte0]: 27
7594 23:06:29.117956 [Byte1]: 27
7595 23:06:29.122382
7596 23:06:29.122462 Set Vref, RX VrefLevel [Byte0]: 28
7597 23:06:29.125892 [Byte1]: 28
7598 23:06:29.130018
7599 23:06:29.130097 Set Vref, RX VrefLevel [Byte0]: 29
7600 23:06:29.133448 [Byte1]: 29
7601 23:06:29.137444
7602 23:06:29.137523 Set Vref, RX VrefLevel [Byte0]: 30
7603 23:06:29.140800 [Byte1]: 30
7604 23:06:29.145043
7605 23:06:29.145122 Set Vref, RX VrefLevel [Byte0]: 31
7606 23:06:29.148306 [Byte1]: 31
7607 23:06:29.152476
7608 23:06:29.152570 Set Vref, RX VrefLevel [Byte0]: 32
7609 23:06:29.155959 [Byte1]: 32
7610 23:06:29.160339
7611 23:06:29.160444 Set Vref, RX VrefLevel [Byte0]: 33
7612 23:06:29.163440 [Byte1]: 33
7613 23:06:29.167703
7614 23:06:29.167782 Set Vref, RX VrefLevel [Byte0]: 34
7615 23:06:29.171140 [Byte1]: 34
7616 23:06:29.175604
7617 23:06:29.175684 Set Vref, RX VrefLevel [Byte0]: 35
7618 23:06:29.179132 [Byte1]: 35
7619 23:06:29.183243
7620 23:06:29.183348 Set Vref, RX VrefLevel [Byte0]: 36
7621 23:06:29.186329 [Byte1]: 36
7622 23:06:29.190864
7623 23:06:29.190943 Set Vref, RX VrefLevel [Byte0]: 37
7624 23:06:29.194115 [Byte1]: 37
7625 23:06:29.198265
7626 23:06:29.198345 Set Vref, RX VrefLevel [Byte0]: 38
7627 23:06:29.201721 [Byte1]: 38
7628 23:06:29.206045
7629 23:06:29.206127 Set Vref, RX VrefLevel [Byte0]: 39
7630 23:06:29.209381 [Byte1]: 39
7631 23:06:29.213778
7632 23:06:29.213857 Set Vref, RX VrefLevel [Byte0]: 40
7633 23:06:29.217019 [Byte1]: 40
7634 23:06:29.221103
7635 23:06:29.221182 Set Vref, RX VrefLevel [Byte0]: 41
7636 23:06:29.224459 [Byte1]: 41
7637 23:06:29.228886
7638 23:06:29.228966 Set Vref, RX VrefLevel [Byte0]: 42
7639 23:06:29.231975 [Byte1]: 42
7640 23:06:29.236312
7641 23:06:29.236392 Set Vref, RX VrefLevel [Byte0]: 43
7642 23:06:29.239538 [Byte1]: 43
7643 23:06:29.243883
7644 23:06:29.243963 Set Vref, RX VrefLevel [Byte0]: 44
7645 23:06:29.247437 [Byte1]: 44
7646 23:06:29.251581
7647 23:06:29.251661 Set Vref, RX VrefLevel [Byte0]: 45
7648 23:06:29.254795 [Byte1]: 45
7649 23:06:29.259150
7650 23:06:29.259229 Set Vref, RX VrefLevel [Byte0]: 46
7651 23:06:29.262406 [Byte1]: 46
7652 23:06:29.266678
7653 23:06:29.266761 Set Vref, RX VrefLevel [Byte0]: 47
7654 23:06:29.270020 [Byte1]: 47
7655 23:06:29.274334
7656 23:06:29.274414 Set Vref, RX VrefLevel [Byte0]: 48
7657 23:06:29.277741 [Byte1]: 48
7658 23:06:29.282013
7659 23:06:29.282092 Set Vref, RX VrefLevel [Byte0]: 49
7660 23:06:29.285386 [Byte1]: 49
7661 23:06:29.289498
7662 23:06:29.289578 Set Vref, RX VrefLevel [Byte0]: 50
7663 23:06:29.292990 [Byte1]: 50
7664 23:06:29.297296
7665 23:06:29.297375 Set Vref, RX VrefLevel [Byte0]: 51
7666 23:06:29.300435 [Byte1]: 51
7667 23:06:29.304782
7668 23:06:29.304861 Set Vref, RX VrefLevel [Byte0]: 52
7669 23:06:29.308038 [Byte1]: 52
7670 23:06:29.312629
7671 23:06:29.312709 Set Vref, RX VrefLevel [Byte0]: 53
7672 23:06:29.315777 [Byte1]: 53
7673 23:06:29.320041
7674 23:06:29.320120 Set Vref, RX VrefLevel [Byte0]: 54
7675 23:06:29.323236 [Byte1]: 54
7676 23:06:29.327866
7677 23:06:29.327945 Set Vref, RX VrefLevel [Byte0]: 55
7678 23:06:29.331016 [Byte1]: 55
7679 23:06:29.335229
7680 23:06:29.335308 Set Vref, RX VrefLevel [Byte0]: 56
7681 23:06:29.338665 [Byte1]: 56
7682 23:06:29.342844
7683 23:06:29.342924 Set Vref, RX VrefLevel [Byte0]: 57
7684 23:06:29.346187 [Byte1]: 57
7685 23:06:29.350484
7686 23:06:29.350563 Set Vref, RX VrefLevel [Byte0]: 58
7687 23:06:29.353965 [Byte1]: 58
7688 23:06:29.358066
7689 23:06:29.358145 Set Vref, RX VrefLevel [Byte0]: 59
7690 23:06:29.361291 [Byte1]: 59
7691 23:06:29.365572
7692 23:06:29.365651 Set Vref, RX VrefLevel [Byte0]: 60
7693 23:06:29.369257 [Byte1]: 60
7694 23:06:29.373446
7695 23:06:29.373526 Set Vref, RX VrefLevel [Byte0]: 61
7696 23:06:29.376736 [Byte1]: 61
7697 23:06:29.381093
7698 23:06:29.381173 Set Vref, RX VrefLevel [Byte0]: 62
7699 23:06:29.384357 [Byte1]: 62
7700 23:06:29.388633
7701 23:06:29.388713 Set Vref, RX VrefLevel [Byte0]: 63
7702 23:06:29.391875 [Byte1]: 63
7703 23:06:29.396193
7704 23:06:29.396272 Set Vref, RX VrefLevel [Byte0]: 64
7705 23:06:29.399885 [Byte1]: 64
7706 23:06:29.403873
7707 23:06:29.403952 Set Vref, RX VrefLevel [Byte0]: 65
7708 23:06:29.407308 [Byte1]: 65
7709 23:06:29.411568
7710 23:06:29.411648 Set Vref, RX VrefLevel [Byte0]: 66
7711 23:06:29.414638 [Byte1]: 66
7712 23:06:29.419134
7713 23:06:29.419213 Set Vref, RX VrefLevel [Byte0]: 67
7714 23:06:29.422264 [Byte1]: 67
7715 23:06:29.426840
7716 23:06:29.426922 Set Vref, RX VrefLevel [Byte0]: 68
7717 23:06:29.429807 [Byte1]: 68
7718 23:06:29.434540
7719 23:06:29.434622 Set Vref, RX VrefLevel [Byte0]: 69
7720 23:06:29.437604 [Byte1]: 69
7721 23:06:29.442102
7722 23:06:29.442182 Set Vref, RX VrefLevel [Byte0]: 70
7723 23:06:29.445142 [Byte1]: 70
7724 23:06:29.449721
7725 23:06:29.449801 Set Vref, RX VrefLevel [Byte0]: 71
7726 23:06:29.453021 [Byte1]: 71
7727 23:06:29.457236
7728 23:06:29.457315 Set Vref, RX VrefLevel [Byte0]: 72
7729 23:06:29.460595 [Byte1]: 72
7730 23:06:29.464674
7731 23:06:29.464779 Final RX Vref Byte 0 = 54 to rank0
7732 23:06:29.468316 Final RX Vref Byte 1 = 55 to rank0
7733 23:06:29.471461 Final RX Vref Byte 0 = 54 to rank1
7734 23:06:29.474539 Final RX Vref Byte 1 = 55 to rank1==
7735 23:06:29.478096 Dram Type= 6, Freq= 0, CH_0, rank 0
7736 23:06:29.484547 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7737 23:06:29.484628 ==
7738 23:06:29.484691 DQS Delay:
7739 23:06:29.484749 DQS0 = 0, DQS1 = 0
7740 23:06:29.488074 DQM Delay:
7741 23:06:29.488153 DQM0 = 126, DQM1 = 121
7742 23:06:29.491210 DQ Delay:
7743 23:06:29.494700 DQ0 =122, DQ1 =128, DQ2 =124, DQ3 =122
7744 23:06:29.497914 DQ4 =130, DQ5 =116, DQ6 =138, DQ7 =134
7745 23:06:29.501347 DQ8 =112, DQ9 =104, DQ10 =120, DQ11 =112
7746 23:06:29.504494 DQ12 =126, DQ13 =126, DQ14 =136, DQ15 =134
7747 23:06:29.504599
7748 23:06:29.504662
7749 23:06:29.504719
7750 23:06:29.508007 [DramC_TX_OE_Calibration] TA2
7751 23:06:29.511204 Original DQ_B0 (3 6) =30, OEN = 27
7752 23:06:29.514202 Original DQ_B1 (3 6) =30, OEN = 27
7753 23:06:29.517848 24, 0x0, End_B0=24 End_B1=24
7754 23:06:29.517932 25, 0x0, End_B0=25 End_B1=25
7755 23:06:29.520822 26, 0x0, End_B0=26 End_B1=26
7756 23:06:29.524236 27, 0x0, End_B0=27 End_B1=27
7757 23:06:29.527598 28, 0x0, End_B0=28 End_B1=28
7758 23:06:29.530998 29, 0x0, End_B0=29 End_B1=29
7759 23:06:29.531079 30, 0x0, End_B0=30 End_B1=30
7760 23:06:29.534076 31, 0x4141, End_B0=30 End_B1=30
7761 23:06:29.537828 Byte0 end_step=30 best_step=27
7762 23:06:29.540875 Byte1 end_step=30 best_step=27
7763 23:06:29.544051 Byte0 TX OE(2T, 0.5T) = (3, 3)
7764 23:06:29.547475 Byte1 TX OE(2T, 0.5T) = (3, 3)
7765 23:06:29.547554
7766 23:06:29.547618
7767 23:06:29.554590 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d1d, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
7768 23:06:29.557515 CH0 RK0: MR19=303, MR18=1D1D
7769 23:06:29.564142 CH0_RK0: MR19=0x303, MR18=0x1D1D, DQSOSC=395, MR23=63, INC=23, DEC=15
7770 23:06:29.564222
7771 23:06:29.567371 ----->DramcWriteLeveling(PI) begin...
7772 23:06:29.567452 ==
7773 23:06:29.570566 Dram Type= 6, Freq= 0, CH_0, rank 1
7774 23:06:29.574187 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7775 23:06:29.574268 ==
7776 23:06:29.577302 Write leveling (Byte 0): 30 => 30
7777 23:06:29.580630 Write leveling (Byte 1): 27 => 27
7778 23:06:29.583929 DramcWriteLeveling(PI) end<-----
7779 23:06:29.584037
7780 23:06:29.584127 ==
7781 23:06:29.587141 Dram Type= 6, Freq= 0, CH_0, rank 1
7782 23:06:29.590537 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7783 23:06:29.590617 ==
7784 23:06:29.594096 [Gating] SW mode calibration
7785 23:06:29.600503 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7786 23:06:29.606974 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7787 23:06:29.610178 0 12 0 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
7788 23:06:29.616944 0 12 4 | B1->B0 | 2525 3434 | 1 1 | (0 0) (1 1)
7789 23:06:29.620195 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7790 23:06:29.623378 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7791 23:06:29.630246 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7792 23:06:29.633770 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7793 23:06:29.636887 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7794 23:06:29.643566 0 12 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
7795 23:06:29.646471 0 13 0 | B1->B0 | 3434 2e2e | 1 0 | (1 0) (0 1)
7796 23:06:29.649987 0 13 4 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
7797 23:06:29.656729 0 13 8 | B1->B0 | 2525 2323 | 1 0 | (1 0) (0 0)
7798 23:06:29.659964 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7799 23:06:29.663205 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7800 23:06:29.669766 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7801 23:06:29.673102 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7802 23:06:29.676359 0 13 28 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
7803 23:06:29.683134 0 14 0 | B1->B0 | 2323 4141 | 0 1 | (0 0) (0 0)
7804 23:06:29.686466 0 14 4 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
7805 23:06:29.689599 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7806 23:06:29.696398 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7807 23:06:29.699741 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7808 23:06:29.702862 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7809 23:06:29.709738 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7810 23:06:29.712733 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7811 23:06:29.716299 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7812 23:06:29.719536 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7813 23:06:29.726162 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7814 23:06:29.729633 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7815 23:06:29.732748 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7816 23:06:29.739617 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7817 23:06:29.742651 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7818 23:06:29.746222 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7819 23:06:29.752766 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7820 23:06:29.755896 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7821 23:06:29.759363 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7822 23:06:29.766032 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7823 23:06:29.769145 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7824 23:06:29.772491 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7825 23:06:29.779343 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7826 23:06:29.782477 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7827 23:06:29.785660 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7828 23:06:29.792271 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7829 23:06:29.795493 Total UI for P1: 0, mck2ui 16
7830 23:06:29.798834 best dqsien dly found for B0: ( 1, 0, 28)
7831 23:06:29.798914 Total UI for P1: 0, mck2ui 16
7832 23:06:29.805432 best dqsien dly found for B1: ( 1, 1, 2)
7833 23:06:29.808969 best DQS0 dly(MCK, UI, PI) = (1, 0, 28)
7834 23:06:29.812307 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
7835 23:06:29.812386
7836 23:06:29.815610 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 28)
7837 23:06:29.818706 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
7838 23:06:29.822376 [Gating] SW calibration Done
7839 23:06:29.822458 ==
7840 23:06:29.825254 Dram Type= 6, Freq= 0, CH_0, rank 1
7841 23:06:29.828939 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7842 23:06:29.829022 ==
7843 23:06:29.831820 RX Vref Scan: 0
7844 23:06:29.831902
7845 23:06:29.831985 RX Vref 0 -> 0, step: 1
7846 23:06:29.832064
7847 23:06:29.835391 RX Delay 0 -> 252, step: 8
7848 23:06:29.838647 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7849 23:06:29.845230 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7850 23:06:29.848756 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7851 23:06:29.851688 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7852 23:06:29.855137 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
7853 23:06:29.858285 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7854 23:06:29.865169 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7855 23:06:29.868424 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
7856 23:06:29.871547 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7857 23:06:29.874811 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7858 23:06:29.878686 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7859 23:06:29.884895 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7860 23:06:29.888083 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7861 23:06:29.891550 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7862 23:06:29.894753 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7863 23:06:29.901343 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7864 23:06:29.901425 ==
7865 23:06:29.904670 Dram Type= 6, Freq= 0, CH_0, rank 1
7866 23:06:29.907865 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7867 23:06:29.907948 ==
7868 23:06:29.908032 DQS Delay:
7869 23:06:29.911175 DQS0 = 0, DQS1 = 0
7870 23:06:29.911257 DQM Delay:
7871 23:06:29.914668 DQM0 = 131, DQM1 = 123
7872 23:06:29.914750 DQ Delay:
7873 23:06:29.917877 DQ0 =127, DQ1 =135, DQ2 =131, DQ3 =127
7874 23:06:29.921149 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =143
7875 23:06:29.924337 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =115
7876 23:06:29.927894 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =131
7877 23:06:29.927976
7878 23:06:29.930942
7879 23:06:29.931023 ==
7880 23:06:29.934311 Dram Type= 6, Freq= 0, CH_0, rank 1
7881 23:06:29.937977 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7882 23:06:29.938060 ==
7883 23:06:29.938143
7884 23:06:29.938221
7885 23:06:29.941367 TX Vref Scan disable
7886 23:06:29.941450 == TX Byte 0 ==
7887 23:06:29.947692 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7888 23:06:29.950817 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7889 23:06:29.950900 == TX Byte 1 ==
7890 23:06:29.957620 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7891 23:06:29.960767 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7892 23:06:29.960848 ==
7893 23:06:29.964000 Dram Type= 6, Freq= 0, CH_0, rank 1
7894 23:06:29.967345 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7895 23:06:29.967428 ==
7896 23:06:29.981009
7897 23:06:29.984192 TX Vref early break, caculate TX vref
7898 23:06:29.987418 TX Vref=16, minBit 1, minWin=22, winSum=377
7899 23:06:29.990994 TX Vref=18, minBit 9, minWin=22, winSum=385
7900 23:06:29.994110 TX Vref=20, minBit 8, minWin=23, winSum=391
7901 23:06:29.997391 TX Vref=22, minBit 1, minWin=24, winSum=398
7902 23:06:30.001060 TX Vref=24, minBit 8, minWin=24, winSum=406
7903 23:06:30.007365 TX Vref=26, minBit 1, minWin=25, winSum=414
7904 23:06:30.010899 TX Vref=28, minBit 8, minWin=25, winSum=418
7905 23:06:30.013947 TX Vref=30, minBit 0, minWin=25, winSum=411
7906 23:06:30.017199 TX Vref=32, minBit 3, minWin=24, winSum=404
7907 23:06:30.020671 TX Vref=34, minBit 1, minWin=24, winSum=396
7908 23:06:30.027500 [TxChooseVref] Worse bit 8, Min win 25, Win sum 418, Final Vref 28
7909 23:06:30.027579
7910 23:06:30.030645 Final TX Range 0 Vref 28
7911 23:06:30.030725
7912 23:06:30.030787 ==
7913 23:06:30.033858 Dram Type= 6, Freq= 0, CH_0, rank 1
7914 23:06:30.037213 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7915 23:06:30.037295 ==
7916 23:06:30.037362
7917 23:06:30.037441
7918 23:06:30.040408 TX Vref Scan disable
7919 23:06:30.047258 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7920 23:06:30.047340 == TX Byte 0 ==
7921 23:06:30.050428 u2DelayCellOfst[0]=10 cells (3 PI)
7922 23:06:30.053765 u2DelayCellOfst[1]=14 cells (4 PI)
7923 23:06:30.056907 u2DelayCellOfst[2]=7 cells (2 PI)
7924 23:06:30.060435 u2DelayCellOfst[3]=7 cells (2 PI)
7925 23:06:30.063586 u2DelayCellOfst[4]=7 cells (2 PI)
7926 23:06:30.066934 u2DelayCellOfst[5]=0 cells (0 PI)
7927 23:06:30.070349 u2DelayCellOfst[6]=17 cells (5 PI)
7928 23:06:30.070431 u2DelayCellOfst[7]=14 cells (4 PI)
7929 23:06:30.077028 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7930 23:06:30.080313 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7931 23:06:30.083763 == TX Byte 1 ==
7932 23:06:30.083845 u2DelayCellOfst[8]=0 cells (0 PI)
7933 23:06:30.087253 u2DelayCellOfst[9]=0 cells (0 PI)
7934 23:06:30.090238 u2DelayCellOfst[10]=10 cells (3 PI)
7935 23:06:30.093544 u2DelayCellOfst[11]=3 cells (1 PI)
7936 23:06:30.097006 u2DelayCellOfst[12]=14 cells (4 PI)
7937 23:06:30.100224 u2DelayCellOfst[13]=14 cells (4 PI)
7938 23:06:30.103766 u2DelayCellOfst[14]=17 cells (5 PI)
7939 23:06:30.106668 u2DelayCellOfst[15]=14 cells (4 PI)
7940 23:06:30.110460 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7941 23:06:30.116777 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7942 23:06:30.116860 DramC Write-DBI on
7943 23:06:30.116943 ==
7944 23:06:30.120152 Dram Type= 6, Freq= 0, CH_0, rank 1
7945 23:06:30.123199 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7946 23:06:30.126571 ==
7947 23:06:30.126653
7948 23:06:30.126736
7949 23:06:30.126813 TX Vref Scan disable
7950 23:06:30.130226 == TX Byte 0 ==
7951 23:06:30.133632 Update DQM dly =729 (2 ,6, 25) DQM OEN =(3 ,3)
7952 23:06:30.136821 == TX Byte 1 ==
7953 23:06:30.140177 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7954 23:06:30.143226 DramC Write-DBI off
7955 23:06:30.143307
7956 23:06:30.143391 [DATLAT]
7957 23:06:30.143469 Freq=1600, CH0 RK1
7958 23:06:30.143547
7959 23:06:30.146626 DATLAT Default: 0xe
7960 23:06:30.149816 0, 0xFFFF, sum = 0
7961 23:06:30.149899 1, 0xFFFF, sum = 0
7962 23:06:30.153115 2, 0xFFFF, sum = 0
7963 23:06:30.153198 3, 0xFFFF, sum = 0
7964 23:06:30.156556 4, 0xFFFF, sum = 0
7965 23:06:30.156639 5, 0xFFFF, sum = 0
7966 23:06:30.159650 6, 0xFFFF, sum = 0
7967 23:06:30.159734 7, 0xFFFF, sum = 0
7968 23:06:30.163104 8, 0xFFFF, sum = 0
7969 23:06:30.163187 9, 0xFFFF, sum = 0
7970 23:06:30.166441 10, 0xFFFF, sum = 0
7971 23:06:30.166525 11, 0xFFFF, sum = 0
7972 23:06:30.169745 12, 0x8FFF, sum = 0
7973 23:06:30.169828 13, 0x0, sum = 1
7974 23:06:30.173220 14, 0x0, sum = 2
7975 23:06:30.173302 15, 0x0, sum = 3
7976 23:06:30.176291 16, 0x0, sum = 4
7977 23:06:30.176374 best_step = 14
7978 23:06:30.176472
7979 23:06:30.176596 ==
7980 23:06:30.179616 Dram Type= 6, Freq= 0, CH_0, rank 1
7981 23:06:30.183152 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7982 23:06:30.186204 ==
7983 23:06:30.186285 RX Vref Scan: 0
7984 23:06:30.186370
7985 23:06:30.189627 RX Vref 0 -> 0, step: 1
7986 23:06:30.189708
7987 23:06:30.192990 RX Delay 11 -> 252, step: 4
7988 23:06:30.196637 iDelay=195, Bit 0, Center 124 (71 ~ 178) 108
7989 23:06:30.199632 iDelay=195, Bit 1, Center 132 (79 ~ 186) 108
7990 23:06:30.202875 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
7991 23:06:30.209785 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
7992 23:06:30.213244 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
7993 23:06:30.216135 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
7994 23:06:30.219361 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
7995 23:06:30.222698 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
7996 23:06:30.229296 iDelay=195, Bit 8, Center 108 (55 ~ 162) 108
7997 23:06:30.232550 iDelay=195, Bit 9, Center 108 (55 ~ 162) 108
7998 23:06:30.235919 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
7999 23:06:30.239150 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
8000 23:06:30.242749 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
8001 23:06:30.249238 iDelay=195, Bit 13, Center 128 (75 ~ 182) 108
8002 23:06:30.252677 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
8003 23:06:30.255722 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
8004 23:06:30.255804 ==
8005 23:06:30.259134 Dram Type= 6, Freq= 0, CH_0, rank 1
8006 23:06:30.262486 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8007 23:06:30.266054 ==
8008 23:06:30.266136 DQS Delay:
8009 23:06:30.266220 DQS0 = 0, DQS1 = 0
8010 23:06:30.269129 DQM Delay:
8011 23:06:30.269210 DQM0 = 129, DQM1 = 121
8012 23:06:30.272420 DQ Delay:
8013 23:06:30.275904 DQ0 =124, DQ1 =132, DQ2 =126, DQ3 =124
8014 23:06:30.279128 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =138
8015 23:06:30.282527 DQ8 =108, DQ9 =108, DQ10 =122, DQ11 =112
8016 23:06:30.285993 DQ12 =126, DQ13 =128, DQ14 =134, DQ15 =130
8017 23:06:30.286075
8018 23:06:30.286158
8019 23:06:30.286237
8020 23:06:30.289243 [DramC_TX_OE_Calibration] TA2
8021 23:06:30.292677 Original DQ_B0 (3 6) =30, OEN = 27
8022 23:06:30.295769 Original DQ_B1 (3 6) =30, OEN = 27
8023 23:06:30.295851 24, 0x0, End_B0=24 End_B1=24
8024 23:06:30.299056 25, 0x0, End_B0=25 End_B1=25
8025 23:06:30.302582 26, 0x0, End_B0=26 End_B1=26
8026 23:06:30.305828 27, 0x0, End_B0=27 End_B1=27
8027 23:06:30.308940 28, 0x0, End_B0=28 End_B1=28
8028 23:06:30.309024 29, 0x0, End_B0=29 End_B1=29
8029 23:06:30.312299 30, 0x0, End_B0=30 End_B1=30
8030 23:06:30.315467 31, 0x4141, End_B0=30 End_B1=30
8031 23:06:30.319053 Byte0 end_step=30 best_step=27
8032 23:06:30.322607 Byte1 end_step=30 best_step=27
8033 23:06:30.325606 Byte0 TX OE(2T, 0.5T) = (3, 3)
8034 23:06:30.325688 Byte1 TX OE(2T, 0.5T) = (3, 3)
8035 23:06:30.325771
8036 23:06:30.325849
8037 23:06:30.335620 [DQSOSCAuto] RK1, (LSB)MR18= 0x2323, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
8038 23:06:30.338984 CH0 RK1: MR19=303, MR18=2323
8039 23:06:30.345687 CH0_RK1: MR19=0x303, MR18=0x2323, DQSOSC=392, MR23=63, INC=24, DEC=16
8040 23:06:30.345771 [RxdqsGatingPostProcess] freq 1600
8041 23:06:30.352254 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8042 23:06:30.355575 Pre-setting of DQS Precalculation
8043 23:06:30.362127 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8044 23:06:30.362208 ==
8045 23:06:30.365466 Dram Type= 6, Freq= 0, CH_1, rank 0
8046 23:06:30.368863 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8047 23:06:30.368970 ==
8048 23:06:30.375324 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8049 23:06:30.378551 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8050 23:06:30.381802 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8051 23:06:30.388687 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8052 23:06:30.396311 [CA 0] Center 41 (11~71) winsize 61
8053 23:06:30.399444 [CA 1] Center 40 (10~70) winsize 61
8054 23:06:30.402820 [CA 2] Center 36 (6~66) winsize 61
8055 23:06:30.406027 [CA 3] Center 35 (6~65) winsize 60
8056 23:06:30.409225 [CA 4] Center 33 (4~63) winsize 60
8057 23:06:30.412828 [CA 5] Center 33 (4~63) winsize 60
8058 23:06:30.412907
8059 23:06:30.416024 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8060 23:06:30.416104
8061 23:06:30.419605 [CATrainingPosCal] consider 1 rank data
8062 23:06:30.422484 u2DelayCellTimex100 = 275/100 ps
8063 23:06:30.429239 CA0 delay=41 (11~71),Diff = 8 PI (28 cell)
8064 23:06:30.432306 CA1 delay=40 (10~70),Diff = 7 PI (24 cell)
8065 23:06:30.435860 CA2 delay=36 (6~66),Diff = 3 PI (10 cell)
8066 23:06:30.439027 CA3 delay=35 (6~65),Diff = 2 PI (7 cell)
8067 23:06:30.442409 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
8068 23:06:30.445915 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
8069 23:06:30.445994
8070 23:06:30.449024 CA PerBit enable=1, Macro0, CA PI delay=33
8071 23:06:30.449103
8072 23:06:30.452321 [CBTSetCACLKResult] CA Dly = 33
8073 23:06:30.455866 CS Dly: 9 (0~40)
8074 23:06:30.459227 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8075 23:06:30.462314 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8076 23:06:30.462393 ==
8077 23:06:30.465598 Dram Type= 6, Freq= 0, CH_1, rank 1
8078 23:06:30.472092 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8079 23:06:30.472171 ==
8080 23:06:30.475868 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8081 23:06:30.478821 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8082 23:06:30.485798 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8083 23:06:30.491942 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8084 23:06:30.498597 [CA 0] Center 41 (11~71) winsize 61
8085 23:06:30.502190 [CA 1] Center 41 (11~71) winsize 61
8086 23:06:30.505555 [CA 2] Center 36 (7~66) winsize 60
8087 23:06:30.508823 [CA 3] Center 35 (6~65) winsize 60
8088 23:06:30.512163 [CA 4] Center 34 (5~64) winsize 60
8089 23:06:30.515235 [CA 5] Center 34 (4~64) winsize 61
8090 23:06:30.515317
8091 23:06:30.518580 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8092 23:06:30.518662
8093 23:06:30.522357 [CATrainingPosCal] consider 2 rank data
8094 23:06:30.525564 u2DelayCellTimex100 = 275/100 ps
8095 23:06:30.528682 CA0 delay=41 (11~71),Diff = 8 PI (28 cell)
8096 23:06:30.535232 CA1 delay=40 (11~70),Diff = 7 PI (24 cell)
8097 23:06:30.538607 CA2 delay=36 (7~66),Diff = 3 PI (10 cell)
8098 23:06:30.541792 CA3 delay=35 (6~65),Diff = 2 PI (7 cell)
8099 23:06:30.545281 CA4 delay=34 (5~63),Diff = 1 PI (3 cell)
8100 23:06:30.548689 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
8101 23:06:30.548771
8102 23:06:30.551667 CA PerBit enable=1, Macro0, CA PI delay=33
8103 23:06:30.551749
8104 23:06:30.555139 [CBTSetCACLKResult] CA Dly = 33
8105 23:06:30.558383 CS Dly: 9 (0~41)
8106 23:06:30.561695 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8107 23:06:30.565154 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8108 23:06:30.565236
8109 23:06:30.568177 ----->DramcWriteLeveling(PI) begin...
8110 23:06:30.568260 ==
8111 23:06:30.571669 Dram Type= 6, Freq= 0, CH_1, rank 0
8112 23:06:30.574911 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8113 23:06:30.578681 ==
8114 23:06:30.578764 Write leveling (Byte 0): 22 => 22
8115 23:06:30.581564 Write leveling (Byte 1): 22 => 22
8116 23:06:30.584814 DramcWriteLeveling(PI) end<-----
8117 23:06:30.584895
8118 23:06:30.584979 ==
8119 23:06:30.588253 Dram Type= 6, Freq= 0, CH_1, rank 0
8120 23:06:30.594949 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8121 23:06:30.595031 ==
8122 23:06:30.598409 [Gating] SW mode calibration
8123 23:06:30.604682 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8124 23:06:30.608259 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8125 23:06:30.614841 0 12 0 | B1->B0 | 2424 3434 | 0 0 | (0 0) (0 0)
8126 23:06:30.617892 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8127 23:06:30.621197 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8128 23:06:30.627805 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8129 23:06:30.631192 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8130 23:06:30.634550 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8131 23:06:30.641615 0 12 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
8132 23:06:30.644846 0 12 28 | B1->B0 | 3434 2525 | 1 0 | (1 0) (1 0)
8133 23:06:30.647801 0 13 0 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (1 0)
8134 23:06:30.654472 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8135 23:06:30.657908 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8136 23:06:30.661304 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8137 23:06:30.664894 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8138 23:06:30.671330 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8139 23:06:30.674498 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8140 23:06:30.677704 0 13 28 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)
8141 23:06:30.684662 0 14 0 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
8142 23:06:30.687992 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8143 23:06:30.691108 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8144 23:06:30.698046 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8145 23:06:30.700909 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8146 23:06:30.704381 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8147 23:06:30.711059 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8148 23:06:30.714204 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8149 23:06:30.717751 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8150 23:06:30.724390 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8151 23:06:30.727445 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8152 23:06:30.730746 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8153 23:06:30.737692 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8154 23:06:30.740857 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8155 23:06:30.744169 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8156 23:06:30.750893 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8157 23:06:30.753926 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8158 23:06:30.757744 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8159 23:06:30.764058 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8160 23:06:30.767396 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8161 23:06:30.770961 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8162 23:06:30.777440 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8163 23:06:30.780722 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8164 23:06:30.783960 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8165 23:06:30.790623 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8166 23:06:30.790702 Total UI for P1: 0, mck2ui 16
8167 23:06:30.794205 best dqsien dly found for B0: ( 1, 0, 26)
8168 23:06:30.800746 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8169 23:06:30.804075 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8170 23:06:30.807258 Total UI for P1: 0, mck2ui 16
8171 23:06:30.810393 best dqsien dly found for B1: ( 1, 1, 0)
8172 23:06:30.813731 best DQS0 dly(MCK, UI, PI) = (1, 0, 26)
8173 23:06:30.817161 best DQS1 dly(MCK, UI, PI) = (1, 1, 0)
8174 23:06:30.817243
8175 23:06:30.820667 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 26)
8176 23:06:30.826791 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 0)
8177 23:06:30.826874 [Gating] SW calibration Done
8178 23:06:30.826958 ==
8179 23:06:30.830169 Dram Type= 6, Freq= 0, CH_1, rank 0
8180 23:06:30.836848 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8181 23:06:30.836930 ==
8182 23:06:30.837013 RX Vref Scan: 0
8183 23:06:30.837092
8184 23:06:30.839916 RX Vref 0 -> 0, step: 1
8185 23:06:30.839997
8186 23:06:30.843611 RX Delay 0 -> 252, step: 8
8187 23:06:30.846652 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8188 23:06:30.850244 iDelay=200, Bit 1, Center 123 (72 ~ 175) 104
8189 23:06:30.853638 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8190 23:06:30.859861 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8191 23:06:30.863216 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8192 23:06:30.866791 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8193 23:06:30.869932 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8194 23:06:30.873182 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8195 23:06:30.879772 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8196 23:06:30.883234 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8197 23:06:30.886542 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8198 23:06:30.889807 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8199 23:06:30.892977 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8200 23:06:30.899866 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8201 23:06:30.903078 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8202 23:06:30.906486 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8203 23:06:30.906569 ==
8204 23:06:30.909700 Dram Type= 6, Freq= 0, CH_1, rank 0
8205 23:06:30.912934 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8206 23:06:30.913017 ==
8207 23:06:30.916423 DQS Delay:
8208 23:06:30.916511 DQS0 = 0, DQS1 = 0
8209 23:06:30.919875 DQM Delay:
8210 23:06:30.919956 DQM0 = 129, DQM1 = 125
8211 23:06:30.922927 DQ Delay:
8212 23:06:30.926287 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =127
8213 23:06:30.929335 DQ4 =131, DQ5 =139, DQ6 =135, DQ7 =127
8214 23:06:30.932834 DQ8 =107, DQ9 =115, DQ10 =127, DQ11 =119
8215 23:06:30.936103 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =135
8216 23:06:30.936185
8217 23:06:30.936284
8218 23:06:30.936380 ==
8219 23:06:30.939691 Dram Type= 6, Freq= 0, CH_1, rank 0
8220 23:06:30.942809 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8221 23:06:30.942895 ==
8222 23:06:30.942978
8223 23:06:30.943055
8224 23:06:30.946527 TX Vref Scan disable
8225 23:06:30.949491 == TX Byte 0 ==
8226 23:06:30.953101 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8227 23:06:30.956182 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8228 23:06:30.959691 == TX Byte 1 ==
8229 23:06:30.962909 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8230 23:06:30.965962 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8231 23:06:30.966045 ==
8232 23:06:30.969517 Dram Type= 6, Freq= 0, CH_1, rank 0
8233 23:06:30.975899 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8234 23:06:30.975981 ==
8235 23:06:30.987623
8236 23:06:30.991007 TX Vref early break, caculate TX vref
8237 23:06:30.994541 TX Vref=16, minBit 3, minWin=21, winSum=366
8238 23:06:30.997584 TX Vref=18, minBit 3, minWin=21, winSum=375
8239 23:06:31.001369 TX Vref=20, minBit 0, minWin=22, winSum=382
8240 23:06:31.004118 TX Vref=22, minBit 3, minWin=23, winSum=392
8241 23:06:31.007568 TX Vref=24, minBit 0, minWin=24, winSum=402
8242 23:06:31.014419 TX Vref=26, minBit 0, minWin=24, winSum=410
8243 23:06:31.017672 TX Vref=28, minBit 3, minWin=24, winSum=411
8244 23:06:31.020867 TX Vref=30, minBit 0, minWin=24, winSum=403
8245 23:06:31.024192 TX Vref=32, minBit 3, minWin=23, winSum=397
8246 23:06:31.027459 TX Vref=34, minBit 3, minWin=23, winSum=392
8247 23:06:31.031064 TX Vref=36, minBit 3, minWin=21, winSum=375
8248 23:06:31.037775 [TxChooseVref] Worse bit 3, Min win 24, Win sum 411, Final Vref 28
8249 23:06:31.037858
8250 23:06:31.040775 Final TX Range 0 Vref 28
8251 23:06:31.040862
8252 23:06:31.040944 ==
8253 23:06:31.044365 Dram Type= 6, Freq= 0, CH_1, rank 0
8254 23:06:31.047355 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8255 23:06:31.047438 ==
8256 23:06:31.047522
8257 23:06:31.047600
8258 23:06:31.050921 TX Vref Scan disable
8259 23:06:31.057470 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8260 23:06:31.057552 == TX Byte 0 ==
8261 23:06:31.060822 u2DelayCellOfst[0]=17 cells (5 PI)
8262 23:06:31.064161 u2DelayCellOfst[1]=14 cells (4 PI)
8263 23:06:31.067211 u2DelayCellOfst[2]=0 cells (0 PI)
8264 23:06:31.070745 u2DelayCellOfst[3]=10 cells (3 PI)
8265 23:06:31.073997 u2DelayCellOfst[4]=10 cells (3 PI)
8266 23:06:31.077454 u2DelayCellOfst[5]=17 cells (5 PI)
8267 23:06:31.080663 u2DelayCellOfst[6]=17 cells (5 PI)
8268 23:06:31.084081 u2DelayCellOfst[7]=10 cells (3 PI)
8269 23:06:31.087154 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8270 23:06:31.090603 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8271 23:06:31.093758 == TX Byte 1 ==
8272 23:06:31.097869 u2DelayCellOfst[8]=0 cells (0 PI)
8273 23:06:31.100526 u2DelayCellOfst[9]=7 cells (2 PI)
8274 23:06:31.100624 u2DelayCellOfst[10]=10 cells (3 PI)
8275 23:06:31.103898 u2DelayCellOfst[11]=3 cells (1 PI)
8276 23:06:31.107112 u2DelayCellOfst[12]=17 cells (5 PI)
8277 23:06:31.110552 u2DelayCellOfst[13]=21 cells (6 PI)
8278 23:06:31.113750 u2DelayCellOfst[14]=17 cells (5 PI)
8279 23:06:31.117036 u2DelayCellOfst[15]=17 cells (5 PI)
8280 23:06:31.123666 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8281 23:06:31.127325 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8282 23:06:31.127405 DramC Write-DBI on
8283 23:06:31.127469 ==
8284 23:06:31.130289 Dram Type= 6, Freq= 0, CH_1, rank 0
8285 23:06:31.137073 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8286 23:06:31.137154 ==
8287 23:06:31.137217
8288 23:06:31.137274
8289 23:06:31.137330 TX Vref Scan disable
8290 23:06:31.141245 == TX Byte 0 ==
8291 23:06:31.144480 Update DQM dly =718 (2 ,6, 14) DQM OEN =(3 ,3)
8292 23:06:31.147993 == TX Byte 1 ==
8293 23:06:31.151150 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8294 23:06:31.151232 DramC Write-DBI off
8295 23:06:31.154333
8296 23:06:31.154415 [DATLAT]
8297 23:06:31.154497 Freq=1600, CH1 RK0
8298 23:06:31.154576
8299 23:06:31.157992 DATLAT Default: 0xf
8300 23:06:31.158073 0, 0xFFFF, sum = 0
8301 23:06:31.161099 1, 0xFFFF, sum = 0
8302 23:06:31.161182 2, 0xFFFF, sum = 0
8303 23:06:31.164229 3, 0xFFFF, sum = 0
8304 23:06:31.167739 4, 0xFFFF, sum = 0
8305 23:06:31.167821 5, 0xFFFF, sum = 0
8306 23:06:31.171505 6, 0xFFFF, sum = 0
8307 23:06:31.171596 7, 0xFFFF, sum = 0
8308 23:06:31.174251 8, 0xFFFF, sum = 0
8309 23:06:31.174332 9, 0xFFFF, sum = 0
8310 23:06:31.177483 10, 0xFFFF, sum = 0
8311 23:06:31.177563 11, 0xFFFF, sum = 0
8312 23:06:31.180777 12, 0xF7F, sum = 0
8313 23:06:31.180859 13, 0x0, sum = 1
8314 23:06:31.184088 14, 0x0, sum = 2
8315 23:06:31.184169 15, 0x0, sum = 3
8316 23:06:31.187544 16, 0x0, sum = 4
8317 23:06:31.187626 best_step = 14
8318 23:06:31.187689
8319 23:06:31.187747 ==
8320 23:06:31.190796 Dram Type= 6, Freq= 0, CH_1, rank 0
8321 23:06:31.194478 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8322 23:06:31.194561 ==
8323 23:06:31.197788 RX Vref Scan: 1
8324 23:06:31.197869
8325 23:06:31.200705 Set Vref Range= 24 -> 127
8326 23:06:31.200785
8327 23:06:31.200848 RX Vref 24 -> 127, step: 1
8328 23:06:31.204242
8329 23:06:31.204321 RX Delay 3 -> 252, step: 4
8330 23:06:31.204398
8331 23:06:31.207244 Set Vref, RX VrefLevel [Byte0]: 24
8332 23:06:31.210658 [Byte1]: 24
8333 23:06:31.214247
8334 23:06:31.214333 Set Vref, RX VrefLevel [Byte0]: 25
8335 23:06:31.217560 [Byte1]: 25
8336 23:06:31.221942
8337 23:06:31.222021 Set Vref, RX VrefLevel [Byte0]: 26
8338 23:06:31.225100 [Byte1]: 26
8339 23:06:31.229685
8340 23:06:31.229765 Set Vref, RX VrefLevel [Byte0]: 27
8341 23:06:31.233153 [Byte1]: 27
8342 23:06:31.237111
8343 23:06:31.237190 Set Vref, RX VrefLevel [Byte0]: 28
8344 23:06:31.240398 [Byte1]: 28
8345 23:06:31.244967
8346 23:06:31.245046 Set Vref, RX VrefLevel [Byte0]: 29
8347 23:06:31.248121 [Byte1]: 29
8348 23:06:31.252341
8349 23:06:31.252423 Set Vref, RX VrefLevel [Byte0]: 30
8350 23:06:31.255748 [Byte1]: 30
8351 23:06:31.260029
8352 23:06:31.260109 Set Vref, RX VrefLevel [Byte0]: 31
8353 23:06:31.263397 [Byte1]: 31
8354 23:06:31.267661
8355 23:06:31.267741 Set Vref, RX VrefLevel [Byte0]: 32
8356 23:06:31.271062 [Byte1]: 32
8357 23:06:31.275548
8358 23:06:31.275628 Set Vref, RX VrefLevel [Byte0]: 33
8359 23:06:31.278894 [Byte1]: 33
8360 23:06:31.282974
8361 23:06:31.283058 Set Vref, RX VrefLevel [Byte0]: 34
8362 23:06:31.286487 [Byte1]: 34
8363 23:06:31.290626
8364 23:06:31.290705 Set Vref, RX VrefLevel [Byte0]: 35
8365 23:06:31.294176 [Byte1]: 35
8366 23:06:31.298302
8367 23:06:31.298380 Set Vref, RX VrefLevel [Byte0]: 36
8368 23:06:31.301738 [Byte1]: 36
8369 23:06:31.305923
8370 23:06:31.306002 Set Vref, RX VrefLevel [Byte0]: 37
8371 23:06:31.309535 [Byte1]: 37
8372 23:06:31.313573
8373 23:06:31.313652 Set Vref, RX VrefLevel [Byte0]: 38
8374 23:06:31.316907 [Byte1]: 38
8375 23:06:31.321251
8376 23:06:31.321330 Set Vref, RX VrefLevel [Byte0]: 39
8377 23:06:31.324494 [Byte1]: 39
8378 23:06:31.329024
8379 23:06:31.329103 Set Vref, RX VrefLevel [Byte0]: 40
8380 23:06:31.332796 [Byte1]: 40
8381 23:06:31.336902
8382 23:06:31.336981 Set Vref, RX VrefLevel [Byte0]: 41
8383 23:06:31.340077 [Byte1]: 41
8384 23:06:31.344279
8385 23:06:31.344357 Set Vref, RX VrefLevel [Byte0]: 42
8386 23:06:31.347437 [Byte1]: 42
8387 23:06:31.351929
8388 23:06:31.352008 Set Vref, RX VrefLevel [Byte0]: 43
8389 23:06:31.355152 [Byte1]: 43
8390 23:06:31.359578
8391 23:06:31.359656 Set Vref, RX VrefLevel [Byte0]: 44
8392 23:06:31.362740 [Byte1]: 44
8393 23:06:31.367210
8394 23:06:31.367299 Set Vref, RX VrefLevel [Byte0]: 45
8395 23:06:31.370473 [Byte1]: 45
8396 23:06:31.374799
8397 23:06:31.374870 Set Vref, RX VrefLevel [Byte0]: 46
8398 23:06:31.378161 [Byte1]: 46
8399 23:06:31.382713
8400 23:06:31.382786 Set Vref, RX VrefLevel [Byte0]: 47
8401 23:06:31.385910 [Byte1]: 47
8402 23:06:31.390070
8403 23:06:31.390151 Set Vref, RX VrefLevel [Byte0]: 48
8404 23:06:31.393462 [Byte1]: 48
8405 23:06:31.397810
8406 23:06:31.397887 Set Vref, RX VrefLevel [Byte0]: 49
8407 23:06:31.400951 [Byte1]: 49
8408 23:06:31.405588
8409 23:06:31.405663 Set Vref, RX VrefLevel [Byte0]: 50
8410 23:06:31.411889 [Byte1]: 50
8411 23:06:31.411966
8412 23:06:31.415140 Set Vref, RX VrefLevel [Byte0]: 51
8413 23:06:31.418446 [Byte1]: 51
8414 23:06:31.418524
8415 23:06:31.421629 Set Vref, RX VrefLevel [Byte0]: 52
8416 23:06:31.424899 [Byte1]: 52
8417 23:06:31.428317
8418 23:06:31.428413 Set Vref, RX VrefLevel [Byte0]: 53
8419 23:06:31.431831 [Byte1]: 53
8420 23:06:31.435954
8421 23:06:31.436033 Set Vref, RX VrefLevel [Byte0]: 54
8422 23:06:31.439531 [Byte1]: 54
8423 23:06:31.443844
8424 23:06:31.443917 Set Vref, RX VrefLevel [Byte0]: 55
8425 23:06:31.446947 [Byte1]: 55
8426 23:06:31.451272
8427 23:06:31.451341 Set Vref, RX VrefLevel [Byte0]: 56
8428 23:06:31.454576 [Byte1]: 56
8429 23:06:31.459204
8430 23:06:31.459274 Set Vref, RX VrefLevel [Byte0]: 57
8431 23:06:31.462321 [Byte1]: 57
8432 23:06:31.466868
8433 23:06:31.466938 Set Vref, RX VrefLevel [Byte0]: 58
8434 23:06:31.469938 [Byte1]: 58
8435 23:06:31.474471
8436 23:06:31.474540 Set Vref, RX VrefLevel [Byte0]: 59
8437 23:06:31.477735 [Byte1]: 59
8438 23:06:31.481991
8439 23:06:31.482063 Set Vref, RX VrefLevel [Byte0]: 60
8440 23:06:31.485408 [Byte1]: 60
8441 23:06:31.489720
8442 23:06:31.489796 Set Vref, RX VrefLevel [Byte0]: 61
8443 23:06:31.492818 [Byte1]: 61
8444 23:06:31.497431
8445 23:06:31.497507 Set Vref, RX VrefLevel [Byte0]: 62
8446 23:06:31.500439 [Byte1]: 62
8447 23:06:31.504983
8448 23:06:31.505062 Set Vref, RX VrefLevel [Byte0]: 63
8449 23:06:31.508179 [Byte1]: 63
8450 23:06:31.512709
8451 23:06:31.512787 Set Vref, RX VrefLevel [Byte0]: 64
8452 23:06:31.515839 [Byte1]: 64
8453 23:06:31.520368
8454 23:06:31.520446 Set Vref, RX VrefLevel [Byte0]: 65
8455 23:06:31.523697 [Byte1]: 65
8456 23:06:31.528004
8457 23:06:31.528082 Set Vref, RX VrefLevel [Byte0]: 66
8458 23:06:31.531103 [Byte1]: 66
8459 23:06:31.535813
8460 23:06:31.535892 Set Vref, RX VrefLevel [Byte0]: 67
8461 23:06:31.538851 [Byte1]: 67
8462 23:06:31.543177
8463 23:06:31.543256 Set Vref, RX VrefLevel [Byte0]: 68
8464 23:06:31.546628 [Byte1]: 68
8465 23:06:31.550970
8466 23:06:31.551049 Set Vref, RX VrefLevel [Byte0]: 69
8467 23:06:31.554466 [Byte1]: 69
8468 23:06:31.558494
8469 23:06:31.558572 Set Vref, RX VrefLevel [Byte0]: 70
8470 23:06:31.561797 [Byte1]: 70
8471 23:06:31.566193
8472 23:06:31.566275 Set Vref, RX VrefLevel [Byte0]: 71
8473 23:06:31.569362 [Byte1]: 71
8474 23:06:31.573805
8475 23:06:31.573883 Set Vref, RX VrefLevel [Byte0]: 72
8476 23:06:31.577353 [Byte1]: 72
8477 23:06:31.581381
8478 23:06:31.581460 Set Vref, RX VrefLevel [Byte0]: 73
8479 23:06:31.584724 [Byte1]: 73
8480 23:06:31.589061
8481 23:06:31.589140 Set Vref, RX VrefLevel [Byte0]: 74
8482 23:06:31.592278 [Byte1]: 74
8483 23:06:31.596650
8484 23:06:31.596728 Set Vref, RX VrefLevel [Byte0]: 75
8485 23:06:31.600028 [Byte1]: 75
8486 23:06:31.604516
8487 23:06:31.604627 Set Vref, RX VrefLevel [Byte0]: 76
8488 23:06:31.607630 [Byte1]: 76
8489 23:06:31.612152
8490 23:06:31.612231 Final RX Vref Byte 0 = 61 to rank0
8491 23:06:31.615321 Final RX Vref Byte 1 = 53 to rank0
8492 23:06:31.618898 Final RX Vref Byte 0 = 61 to rank1
8493 23:06:31.622020 Final RX Vref Byte 1 = 53 to rank1==
8494 23:06:31.625471 Dram Type= 6, Freq= 0, CH_1, rank 0
8495 23:06:31.632027 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8496 23:06:31.632111 ==
8497 23:06:31.632175 DQS Delay:
8498 23:06:31.632233 DQS0 = 0, DQS1 = 0
8499 23:06:31.635495 DQM Delay:
8500 23:06:31.635575 DQM0 = 128, DQM1 = 124
8501 23:06:31.638659 DQ Delay:
8502 23:06:31.641740 DQ0 =132, DQ1 =122, DQ2 =118, DQ3 =126
8503 23:06:31.645100 DQ4 =130, DQ5 =138, DQ6 =138, DQ7 =126
8504 23:06:31.648613 DQ8 =106, DQ9 =114, DQ10 =126, DQ11 =114
8505 23:06:31.651898 DQ12 =130, DQ13 =134, DQ14 =134, DQ15 =134
8506 23:06:31.651977
8507 23:06:31.652040
8508 23:06:31.652097
8509 23:06:31.655141 [DramC_TX_OE_Calibration] TA2
8510 23:06:31.658586 Original DQ_B0 (3 6) =30, OEN = 27
8511 23:06:31.661658 Original DQ_B1 (3 6) =30, OEN = 27
8512 23:06:31.665175 24, 0x0, End_B0=24 End_B1=24
8513 23:06:31.665255 25, 0x0, End_B0=25 End_B1=25
8514 23:06:31.668550 26, 0x0, End_B0=26 End_B1=26
8515 23:06:31.671925 27, 0x0, End_B0=27 End_B1=27
8516 23:06:31.675389 28, 0x0, End_B0=28 End_B1=28
8517 23:06:31.678463 29, 0x0, End_B0=29 End_B1=29
8518 23:06:31.678543 30, 0x0, End_B0=30 End_B1=30
8519 23:06:31.681828 31, 0x4545, End_B0=30 End_B1=30
8520 23:06:31.685561 Byte0 end_step=30 best_step=27
8521 23:06:31.688938 Byte1 end_step=30 best_step=27
8522 23:06:31.691786 Byte0 TX OE(2T, 0.5T) = (3, 3)
8523 23:06:31.695363 Byte1 TX OE(2T, 0.5T) = (3, 3)
8524 23:06:31.695443
8525 23:06:31.695505
8526 23:06:31.701425 [DQSOSCAuto] RK0, (LSB)MR18= 0x2626, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
8527 23:06:31.704813 CH1 RK0: MR19=303, MR18=2626
8528 23:06:31.711376 CH1_RK0: MR19=0x303, MR18=0x2626, DQSOSC=390, MR23=63, INC=24, DEC=16
8529 23:06:31.711457
8530 23:06:31.714945 ----->DramcWriteLeveling(PI) begin...
8531 23:06:31.715026 ==
8532 23:06:31.718131 Dram Type= 6, Freq= 0, CH_1, rank 1
8533 23:06:31.721472 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8534 23:06:31.721552 ==
8535 23:06:31.724566 Write leveling (Byte 0): 23 => 23
8536 23:06:31.727954 Write leveling (Byte 1): 23 => 23
8537 23:06:31.731344 DramcWriteLeveling(PI) end<-----
8538 23:06:31.731422
8539 23:06:31.731484 ==
8540 23:06:31.734669 Dram Type= 6, Freq= 0, CH_1, rank 1
8541 23:06:31.738147 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8542 23:06:31.738227 ==
8543 23:06:31.741354 [Gating] SW mode calibration
8544 23:06:31.748156 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8545 23:06:31.754549 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8546 23:06:31.757751 0 12 0 | B1->B0 | 3232 3434 | 1 1 | (0 0) (1 1)
8547 23:06:31.764398 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8548 23:06:31.767652 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8549 23:06:31.770973 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8550 23:06:31.777722 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8551 23:06:31.780871 0 12 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8552 23:06:31.784434 0 12 24 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8553 23:06:31.791221 0 12 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
8554 23:06:31.794105 0 13 0 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (0 0)
8555 23:06:31.797783 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8556 23:06:31.804085 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8557 23:06:31.807475 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8558 23:06:31.810775 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8559 23:06:31.814435 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8560 23:06:31.821004 0 13 24 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
8561 23:06:31.823931 0 13 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8562 23:06:31.827333 0 14 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8563 23:06:31.834311 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8564 23:06:31.837170 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8565 23:06:31.840434 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8566 23:06:31.847101 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8567 23:06:31.850348 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8568 23:06:31.857163 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8569 23:06:31.860235 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8570 23:06:31.863681 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8571 23:06:31.866819 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8572 23:06:31.873583 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8573 23:06:31.876866 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8574 23:06:31.879967 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8575 23:06:31.887048 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8576 23:06:31.889911 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8577 23:06:31.893295 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8578 23:06:31.900243 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8579 23:06:31.903362 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8580 23:06:31.906488 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8581 23:06:31.913098 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8582 23:06:31.916301 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8583 23:06:31.919837 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8584 23:06:31.926470 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8585 23:06:31.929855 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8586 23:06:31.932879 Total UI for P1: 0, mck2ui 16
8587 23:06:31.936221 best dqsien dly found for B0: ( 1, 0, 22)
8588 23:06:31.939549 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8589 23:06:31.945939 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8590 23:06:31.949677 Total UI for P1: 0, mck2ui 16
8591 23:06:31.952673 best dqsien dly found for B1: ( 1, 1, 0)
8592 23:06:31.956228 best DQS0 dly(MCK, UI, PI) = (1, 0, 22)
8593 23:06:31.959136 best DQS1 dly(MCK, UI, PI) = (1, 1, 0)
8594 23:06:31.959215
8595 23:06:31.962690 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 22)
8596 23:06:31.966029 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 0)
8597 23:06:31.969493 [Gating] SW calibration Done
8598 23:06:31.969572 ==
8599 23:06:31.972622 Dram Type= 6, Freq= 0, CH_1, rank 1
8600 23:06:31.975950 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8601 23:06:31.976030 ==
8602 23:06:31.979172 RX Vref Scan: 0
8603 23:06:31.979251
8604 23:06:31.979313 RX Vref 0 -> 0, step: 1
8605 23:06:31.982452
8606 23:06:31.982531 RX Delay 0 -> 252, step: 8
8607 23:06:31.985798 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8608 23:06:31.992517 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120
8609 23:06:31.995817 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8610 23:06:31.999139 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8611 23:06:32.002208 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8612 23:06:32.009137 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8613 23:06:32.012361 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8614 23:06:32.015712 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8615 23:06:32.018818 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8616 23:06:32.022010 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8617 23:06:32.028800 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8618 23:06:32.031798 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8619 23:06:32.035181 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8620 23:06:32.038722 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8621 23:06:32.041969 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8622 23:06:32.048525 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8623 23:06:32.048601 ==
8624 23:06:32.051728 Dram Type= 6, Freq= 0, CH_1, rank 1
8625 23:06:32.055190 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8626 23:06:32.055288 ==
8627 23:06:32.055381 DQS Delay:
8628 23:06:32.058485 DQS0 = 0, DQS1 = 0
8629 23:06:32.058555 DQM Delay:
8630 23:06:32.062054 DQM0 = 131, DQM1 = 125
8631 23:06:32.062132 DQ Delay:
8632 23:06:32.065099 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =131
8633 23:06:32.068591 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =131
8634 23:06:32.071596 DQ8 =107, DQ9 =115, DQ10 =123, DQ11 =115
8635 23:06:32.074877 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =135
8636 23:06:32.078367
8637 23:06:32.078439
8638 23:06:32.078502 ==
8639 23:06:32.081461 Dram Type= 6, Freq= 0, CH_1, rank 1
8640 23:06:32.084821 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8641 23:06:32.084895 ==
8642 23:06:32.084957
8643 23:06:32.085014
8644 23:06:32.088446 TX Vref Scan disable
8645 23:06:32.088561 == TX Byte 0 ==
8646 23:06:32.094766 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8647 23:06:32.097866 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8648 23:06:32.097964 == TX Byte 1 ==
8649 23:06:32.104429 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8650 23:06:32.108286 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8651 23:06:32.108388 ==
8652 23:06:32.111309 Dram Type= 6, Freq= 0, CH_1, rank 1
8653 23:06:32.114256 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8654 23:06:32.114355 ==
8655 23:06:32.127723
8656 23:06:32.131420 TX Vref early break, caculate TX vref
8657 23:06:32.134390 TX Vref=16, minBit 0, minWin=21, winSum=370
8658 23:06:32.137738 TX Vref=18, minBit 0, minWin=22, winSum=380
8659 23:06:32.140809 TX Vref=20, minBit 4, minWin=23, winSum=393
8660 23:06:32.144229 TX Vref=22, minBit 6, minWin=23, winSum=396
8661 23:06:32.147574 TX Vref=24, minBit 0, minWin=23, winSum=409
8662 23:06:32.154344 TX Vref=26, minBit 5, minWin=24, winSum=413
8663 23:06:32.157549 TX Vref=28, minBit 0, minWin=24, winSum=414
8664 23:06:32.161021 TX Vref=30, minBit 0, minWin=24, winSum=411
8665 23:06:32.164190 TX Vref=32, minBit 0, minWin=22, winSum=400
8666 23:06:32.167241 TX Vref=34, minBit 0, minWin=23, winSum=392
8667 23:06:32.173945 [TxChooseVref] Worse bit 0, Min win 24, Win sum 414, Final Vref 28
8668 23:06:32.174021
8669 23:06:32.177416 Final TX Range 0 Vref 28
8670 23:06:32.177484
8671 23:06:32.177543 ==
8672 23:06:32.180761 Dram Type= 6, Freq= 0, CH_1, rank 1
8673 23:06:32.183916 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8674 23:06:32.183986 ==
8675 23:06:32.184046
8676 23:06:32.184103
8677 23:06:32.187158 TX Vref Scan disable
8678 23:06:32.193821 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8679 23:06:32.193890 == TX Byte 0 ==
8680 23:06:32.197098 u2DelayCellOfst[0]=17 cells (5 PI)
8681 23:06:32.200497 u2DelayCellOfst[1]=10 cells (3 PI)
8682 23:06:32.203840 u2DelayCellOfst[2]=0 cells (0 PI)
8683 23:06:32.206974 u2DelayCellOfst[3]=10 cells (3 PI)
8684 23:06:32.210226 u2DelayCellOfst[4]=10 cells (3 PI)
8685 23:06:32.213973 u2DelayCellOfst[5]=21 cells (6 PI)
8686 23:06:32.216864 u2DelayCellOfst[6]=17 cells (5 PI)
8687 23:06:32.220161 u2DelayCellOfst[7]=7 cells (2 PI)
8688 23:06:32.223617 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8689 23:06:32.226858 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8690 23:06:32.230452 == TX Byte 1 ==
8691 23:06:32.233581 u2DelayCellOfst[8]=0 cells (0 PI)
8692 23:06:32.233681 u2DelayCellOfst[9]=7 cells (2 PI)
8693 23:06:32.236943 u2DelayCellOfst[10]=14 cells (4 PI)
8694 23:06:32.240141 u2DelayCellOfst[11]=7 cells (2 PI)
8695 23:06:32.243377 u2DelayCellOfst[12]=17 cells (5 PI)
8696 23:06:32.246641 u2DelayCellOfst[13]=21 cells (6 PI)
8697 23:06:32.250096 u2DelayCellOfst[14]=21 cells (6 PI)
8698 23:06:32.253349 u2DelayCellOfst[15]=21 cells (6 PI)
8699 23:06:32.256933 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8700 23:06:32.263399 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8701 23:06:32.263474 DramC Write-DBI on
8702 23:06:32.263572 ==
8703 23:06:32.266850 Dram Type= 6, Freq= 0, CH_1, rank 1
8704 23:06:32.273203 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8705 23:06:32.273273 ==
8706 23:06:32.273333
8707 23:06:32.273390
8708 23:06:32.273451 TX Vref Scan disable
8709 23:06:32.276978 == TX Byte 0 ==
8710 23:06:32.280663 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8711 23:06:32.283867 == TX Byte 1 ==
8712 23:06:32.287347 Update DQM dly =717 (2 ,6, 13) DQM OEN =(3 ,3)
8713 23:06:32.290372 DramC Write-DBI off
8714 23:06:32.290465
8715 23:06:32.290556 [DATLAT]
8716 23:06:32.290641 Freq=1600, CH1 RK1
8717 23:06:32.290726
8718 23:06:32.293974 DATLAT Default: 0xe
8719 23:06:32.294068 0, 0xFFFF, sum = 0
8720 23:06:32.296942 1, 0xFFFF, sum = 0
8721 23:06:32.300362 2, 0xFFFF, sum = 0
8722 23:06:32.300454 3, 0xFFFF, sum = 0
8723 23:06:32.303681 4, 0xFFFF, sum = 0
8724 23:06:32.303776 5, 0xFFFF, sum = 0
8725 23:06:32.306696 6, 0xFFFF, sum = 0
8726 23:06:32.306804 7, 0xFFFF, sum = 0
8727 23:06:32.310542 8, 0xFFFF, sum = 0
8728 23:06:32.310646 9, 0xFFFF, sum = 0
8729 23:06:32.313179 10, 0xFFFF, sum = 0
8730 23:06:32.313269 11, 0xFFFF, sum = 0
8731 23:06:32.316761 12, 0xF7F, sum = 0
8732 23:06:32.316835 13, 0x0, sum = 1
8733 23:06:32.319904 14, 0x0, sum = 2
8734 23:06:32.320004 15, 0x0, sum = 3
8735 23:06:32.323231 16, 0x0, sum = 4
8736 23:06:32.323331 best_step = 14
8737 23:06:32.323430
8738 23:06:32.323516 ==
8739 23:06:32.326535 Dram Type= 6, Freq= 0, CH_1, rank 1
8740 23:06:32.329763 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8741 23:06:32.333105 ==
8742 23:06:32.333189 RX Vref Scan: 0
8743 23:06:32.333251
8744 23:06:32.336536 RX Vref 0 -> 0, step: 1
8745 23:06:32.336630
8746 23:06:32.336693 RX Delay 3 -> 252, step: 4
8747 23:06:32.344038 iDelay=195, Bit 0, Center 128 (75 ~ 182) 108
8748 23:06:32.347491 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
8749 23:06:32.350583 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
8750 23:06:32.354094 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8751 23:06:32.357206 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8752 23:06:32.363878 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8753 23:06:32.367591 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
8754 23:06:32.370303 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8755 23:06:32.373490 iDelay=195, Bit 8, Center 108 (51 ~ 166) 116
8756 23:06:32.380187 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8757 23:06:32.383672 iDelay=195, Bit 10, Center 124 (67 ~ 182) 116
8758 23:06:32.386838 iDelay=195, Bit 11, Center 112 (55 ~ 170) 116
8759 23:06:32.389869 iDelay=195, Bit 12, Center 132 (75 ~ 190) 116
8760 23:06:32.393459 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8761 23:06:32.400085 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
8762 23:06:32.403587 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8763 23:06:32.403666 ==
8764 23:06:32.406573 Dram Type= 6, Freq= 0, CH_1, rank 1
8765 23:06:32.410353 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8766 23:06:32.410432 ==
8767 23:06:32.413117 DQS Delay:
8768 23:06:32.413196 DQS0 = 0, DQS1 = 0
8769 23:06:32.413258 DQM Delay:
8770 23:06:32.416391 DQM0 = 127, DQM1 = 123
8771 23:06:32.416470 DQ Delay:
8772 23:06:32.420000 DQ0 =128, DQ1 =124, DQ2 =118, DQ3 =124
8773 23:06:32.423422 DQ4 =126, DQ5 =138, DQ6 =136, DQ7 =126
8774 23:06:32.429848 DQ8 =108, DQ9 =110, DQ10 =124, DQ11 =112
8775 23:06:32.433024 DQ12 =132, DQ13 =132, DQ14 =134, DQ15 =132
8776 23:06:32.433104
8777 23:06:32.433167
8778 23:06:32.433224
8779 23:06:32.436497 [DramC_TX_OE_Calibration] TA2
8780 23:06:32.439705 Original DQ_B0 (3 6) =30, OEN = 27
8781 23:06:32.442903 Original DQ_B1 (3 6) =30, OEN = 27
8782 23:06:32.442982 24, 0x0, End_B0=24 End_B1=24
8783 23:06:32.446391 25, 0x0, End_B0=25 End_B1=25
8784 23:06:32.449922 26, 0x0, End_B0=26 End_B1=26
8785 23:06:32.453058 27, 0x0, End_B0=27 End_B1=27
8786 23:06:32.453139 28, 0x0, End_B0=28 End_B1=28
8787 23:06:32.456101 29, 0x0, End_B0=29 End_B1=29
8788 23:06:32.459815 30, 0x0, End_B0=30 End_B1=30
8789 23:06:32.462891 31, 0x4141, End_B0=30 End_B1=30
8790 23:06:32.466365 Byte0 end_step=30 best_step=27
8791 23:06:32.469445 Byte1 end_step=30 best_step=27
8792 23:06:32.469523 Byte0 TX OE(2T, 0.5T) = (3, 3)
8793 23:06:32.473135 Byte1 TX OE(2T, 0.5T) = (3, 3)
8794 23:06:32.473215
8795 23:06:32.473276
8796 23:06:32.482863 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f1f, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
8797 23:06:32.486102 CH1 RK1: MR19=303, MR18=1F1F
8798 23:06:32.489412 CH1_RK1: MR19=0x303, MR18=0x1F1F, DQSOSC=394, MR23=63, INC=23, DEC=15
8799 23:06:32.492971 [RxdqsGatingPostProcess] freq 1600
8800 23:06:32.499142 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8801 23:06:32.502776 Pre-setting of DQS Precalculation
8802 23:06:32.506178 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8803 23:06:32.515559 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8804 23:06:32.522428 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8805 23:06:32.522508
8806 23:06:32.522571
8807 23:06:32.525830 [Calibration Summary] 3200 Mbps
8808 23:06:32.525909 CH 0, Rank 0
8809 23:06:32.529078 SW Impedance : PASS
8810 23:06:32.529158 DUTY Scan : NO K
8811 23:06:32.532710 ZQ Calibration : PASS
8812 23:06:32.535680 Jitter Meter : NO K
8813 23:06:32.535759 CBT Training : PASS
8814 23:06:32.538710 Write leveling : PASS
8815 23:06:32.542079 RX DQS gating : PASS
8816 23:06:32.542158 RX DQ/DQS(RDDQC) : PASS
8817 23:06:32.545672 TX DQ/DQS : PASS
8818 23:06:32.548685 RX DATLAT : PASS
8819 23:06:32.548764 RX DQ/DQS(Engine): PASS
8820 23:06:32.552258 TX OE : PASS
8821 23:06:32.552337 All Pass.
8822 23:06:32.552399
8823 23:06:32.555393 CH 0, Rank 1
8824 23:06:32.555472 SW Impedance : PASS
8825 23:06:32.558911 DUTY Scan : NO K
8826 23:06:32.562032 ZQ Calibration : PASS
8827 23:06:32.562112 Jitter Meter : NO K
8828 23:06:32.565466 CBT Training : PASS
8829 23:06:32.568842 Write leveling : PASS
8830 23:06:32.568921 RX DQS gating : PASS
8831 23:06:32.572169 RX DQ/DQS(RDDQC) : PASS
8832 23:06:32.572248 TX DQ/DQS : PASS
8833 23:06:32.575328 RX DATLAT : PASS
8834 23:06:32.578729 RX DQ/DQS(Engine): PASS
8835 23:06:32.578807 TX OE : PASS
8836 23:06:32.582129 All Pass.
8837 23:06:32.582209
8838 23:06:32.582271 CH 1, Rank 0
8839 23:06:32.585268 SW Impedance : PASS
8840 23:06:32.585347 DUTY Scan : NO K
8841 23:06:32.588448 ZQ Calibration : PASS
8842 23:06:32.591880 Jitter Meter : NO K
8843 23:06:32.591959 CBT Training : PASS
8844 23:06:32.595236 Write leveling : PASS
8845 23:06:32.598408 RX DQS gating : PASS
8846 23:06:32.598487 RX DQ/DQS(RDDQC) : PASS
8847 23:06:32.601994 TX DQ/DQS : PASS
8848 23:06:32.605202 RX DATLAT : PASS
8849 23:06:32.605281 RX DQ/DQS(Engine): PASS
8850 23:06:32.608656 TX OE : PASS
8851 23:06:32.608736 All Pass.
8852 23:06:32.608798
8853 23:06:32.611831 CH 1, Rank 1
8854 23:06:32.611909 SW Impedance : PASS
8855 23:06:32.615213 DUTY Scan : NO K
8856 23:06:32.618877 ZQ Calibration : PASS
8857 23:06:32.618956 Jitter Meter : NO K
8858 23:06:32.621770 CBT Training : PASS
8859 23:06:32.625323 Write leveling : PASS
8860 23:06:32.625402 RX DQS gating : PASS
8861 23:06:32.628349 RX DQ/DQS(RDDQC) : PASS
8862 23:06:32.631798 TX DQ/DQS : PASS
8863 23:06:32.631878 RX DATLAT : PASS
8864 23:06:32.635036 RX DQ/DQS(Engine): PASS
8865 23:06:32.635115 TX OE : PASS
8866 23:06:32.638383 All Pass.
8867 23:06:32.638462
8868 23:06:32.638525 DramC Write-DBI on
8869 23:06:32.641439 PER_BANK_REFRESH: Hybrid Mode
8870 23:06:32.644968 TX_TRACKING: ON
8871 23:06:32.651416 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8872 23:06:32.661793 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8873 23:06:32.667860 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8874 23:06:32.671527 [FAST_K] Save calibration result to emmc
8875 23:06:32.674929 sync common calibartion params.
8876 23:06:32.675029 sync cbt_mode0:0, 1:0
8877 23:06:32.677917 dram_init: ddr_geometry: 0
8878 23:06:32.681487 dram_init: ddr_geometry: 0
8879 23:06:32.684732 dram_init: ddr_geometry: 0
8880 23:06:32.684811 0:dram_rank_size:80000000
8881 23:06:32.688081 1:dram_rank_size:80000000
8882 23:06:32.694384 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8883 23:06:32.694461 DFS_SHUFFLE_HW_MODE: ON
8884 23:06:32.701255 dramc_set_vcore_voltage set vcore to 725000
8885 23:06:32.701332 Read voltage for 1600, 0
8886 23:06:32.701410 Vio18 = 0
8887 23:06:32.704259 Vcore = 725000
8888 23:06:32.704356 Vdram = 0
8889 23:06:32.704457 Vddq = 0
8890 23:06:32.707813 Vmddr = 0
8891 23:06:32.707891 switch to 3200 Mbps bootup
8892 23:06:32.711038 [DramcRunTimeConfig]
8893 23:06:32.711139 PHYPLL
8894 23:06:32.714335 DPM_CONTROL_AFTERK: ON
8895 23:06:32.714433 PER_BANK_REFRESH: ON
8896 23:06:32.717740 REFRESH_OVERHEAD_REDUCTION: ON
8897 23:06:32.720985 CMD_PICG_NEW_MODE: OFF
8898 23:06:32.721059 XRTWTW_NEW_MODE: ON
8899 23:06:32.724049 XRTRTR_NEW_MODE: ON
8900 23:06:32.724146 TX_TRACKING: ON
8901 23:06:32.727489 RDSEL_TRACKING: OFF
8902 23:06:32.730650 DQS Precalculation for DVFS: ON
8903 23:06:32.730753 RX_TRACKING: OFF
8904 23:06:32.734194 HW_GATING DBG: ON
8905 23:06:32.734293 ZQCS_ENABLE_LP4: ON
8906 23:06:32.737464 RX_PICG_NEW_MODE: ON
8907 23:06:32.740741 TX_PICG_NEW_MODE: ON
8908 23:06:32.740814 ENABLE_RX_DCM_DPHY: ON
8909 23:06:32.744075 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8910 23:06:32.747590 DUMMY_READ_FOR_TRACKING: OFF
8911 23:06:32.750771 !!! SPM_CONTROL_AFTERK: OFF
8912 23:06:32.750877 !!! SPM could not control APHY
8913 23:06:32.753975 IMPEDANCE_TRACKING: ON
8914 23:06:32.754072 TEMP_SENSOR: ON
8915 23:06:32.757467 HW_SAVE_FOR_SR: OFF
8916 23:06:32.760684 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8917 23:06:32.763958 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8918 23:06:32.767317 Read ODT Tracking: ON
8919 23:06:32.767417 Refresh Rate DeBounce: ON
8920 23:06:32.770602 DFS_NO_QUEUE_FLUSH: ON
8921 23:06:32.773859 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8922 23:06:32.777489 ENABLE_DFS_RUNTIME_MRW: OFF
8923 23:06:32.777588 DDR_RESERVE_NEW_MODE: ON
8924 23:06:32.780749 MR_CBT_SWITCH_FREQ: ON
8925 23:06:32.783769 =========================
8926 23:06:32.801614 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8927 23:06:32.804779 dram_init: ddr_geometry: 0
8928 23:06:32.822931 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8929 23:06:32.826084 dram_init: dram init end (result: 0)
8930 23:06:32.832774 DRAM-K: Full calibration passed in 23417 msecs
8931 23:06:32.836179 MRC: failed to locate region type 0.
8932 23:06:32.836255 DRAM rank0 size:0x80000000,
8933 23:06:32.839364 DRAM rank1 size=0x80000000
8934 23:06:32.849493 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8935 23:06:32.856183 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8936 23:06:32.862583 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8937 23:06:32.869239 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8938 23:06:32.872623 DRAM rank0 size:0x80000000,
8939 23:06:32.875805 DRAM rank1 size=0x80000000
8940 23:06:32.875909 CBMEM:
8941 23:06:32.879321 IMD: root @ 0xfffff000 254 entries.
8942 23:06:32.882371 IMD: root @ 0xffffec00 62 entries.
8943 23:06:32.885730 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8944 23:06:32.889136 WARNING: RO_VPD is uninitialized or empty.
8945 23:06:32.895681 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8946 23:06:32.903055 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8947 23:06:32.915236 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
8948 23:06:32.926781 BS: romstage times (exec / console): total (unknown) / 22957 ms
8949 23:06:32.926861
8950 23:06:32.926923
8951 23:06:32.936768 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8952 23:06:32.939853 ARM64: Exception handlers installed.
8953 23:06:32.943274 ARM64: Testing exception
8954 23:06:32.946471 ARM64: Done test exception
8955 23:06:32.946551 Enumerating buses...
8956 23:06:32.949947 Show all devs... Before device enumeration.
8957 23:06:32.953608 Root Device: enabled 1
8958 23:06:32.956624 CPU_CLUSTER: 0: enabled 1
8959 23:06:32.956704 CPU: 00: enabled 1
8960 23:06:32.959824 Compare with tree...
8961 23:06:32.959902 Root Device: enabled 1
8962 23:06:32.963236 CPU_CLUSTER: 0: enabled 1
8963 23:06:32.966673 CPU: 00: enabled 1
8964 23:06:32.966752 Root Device scanning...
8965 23:06:32.969757 scan_static_bus for Root Device
8966 23:06:32.973245 CPU_CLUSTER: 0 enabled
8967 23:06:32.976415 scan_static_bus for Root Device done
8968 23:06:32.979617 scan_bus: bus Root Device finished in 8 msecs
8969 23:06:32.979697 done
8970 23:06:32.986492 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8971 23:06:32.989569 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8972 23:06:32.996412 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8973 23:06:32.999341 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8974 23:06:33.002830 Allocating resources...
8975 23:06:33.006189 Reading resources...
8976 23:06:33.009239 Root Device read_resources bus 0 link: 0
8977 23:06:33.009319 DRAM rank0 size:0x80000000,
8978 23:06:33.012715 DRAM rank1 size=0x80000000
8979 23:06:33.015956 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8980 23:06:33.019074 CPU: 00 missing read_resources
8981 23:06:33.025911 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8982 23:06:33.029082 Root Device read_resources bus 0 link: 0 done
8983 23:06:33.029162 Done reading resources.
8984 23:06:33.035671 Show resources in subtree (Root Device)...After reading.
8985 23:06:33.038951 Root Device child on link 0 CPU_CLUSTER: 0
8986 23:06:33.042620 CPU_CLUSTER: 0 child on link 0 CPU: 00
8987 23:06:33.052438 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8988 23:06:33.052576 CPU: 00
8989 23:06:33.055665 Root Device assign_resources, bus 0 link: 0
8990 23:06:33.058865 CPU_CLUSTER: 0 missing set_resources
8991 23:06:33.065531 Root Device assign_resources, bus 0 link: 0 done
8992 23:06:33.065611 Done setting resources.
8993 23:06:33.072228 Show resources in subtree (Root Device)...After assigning values.
8994 23:06:33.076287 Root Device child on link 0 CPU_CLUSTER: 0
8995 23:06:33.078671 CPU_CLUSTER: 0 child on link 0 CPU: 00
8996 23:06:33.088859 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8997 23:06:33.088939 CPU: 00
8998 23:06:33.091909 Done allocating resources.
8999 23:06:33.098649 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9000 23:06:33.098752 Enabling resources...
9001 23:06:33.098818 done.
9002 23:06:33.105149 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9003 23:06:33.105229 Initializing devices...
9004 23:06:33.108771 Root Device init
9005 23:06:33.108849 init hardware done!
9006 23:06:33.112179 0x00000018: ctrlr->caps
9007 23:06:33.115176 52.000 MHz: ctrlr->f_max
9008 23:06:33.115257 0.400 MHz: ctrlr->f_min
9009 23:06:33.118676 0x40ff8080: ctrlr->voltages
9010 23:06:33.122117 sclk: 390625
9011 23:06:33.122196 Bus Width = 1
9012 23:06:33.122257 sclk: 390625
9013 23:06:33.125370 Bus Width = 1
9014 23:06:33.125448 Early init status = 3
9015 23:06:33.131723 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9016 23:06:33.134883 in-header: 03 fc 00 00 01 00 00 00
9017 23:06:33.138501 in-data: 00
9018 23:06:33.141569 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9019 23:06:33.145352 in-header: 03 fd 00 00 00 00 00 00
9020 23:06:33.148543 in-data:
9021 23:06:33.151766 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9022 23:06:33.155233 in-header: 03 fc 00 00 01 00 00 00
9023 23:06:33.158538 in-data: 00
9024 23:06:33.161660 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9025 23:06:33.166721 in-header: 03 fd 00 00 00 00 00 00
9026 23:06:33.170033 in-data:
9027 23:06:33.173139 [SSUSB] Setting up USB HOST controller...
9028 23:06:33.176473 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9029 23:06:33.179942 [SSUSB] phy power-on done.
9030 23:06:33.183145 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9031 23:06:33.189684 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9032 23:06:33.193124 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9033 23:06:33.199700 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9034 23:06:33.206195 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9035 23:06:33.212960 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9036 23:06:33.219810 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9037 23:06:33.226267 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9038 23:06:33.229558 SPM: binary array size = 0x9dc
9039 23:06:33.232975 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9040 23:06:33.239531 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9041 23:06:33.246303 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9042 23:06:33.252777 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9043 23:06:33.255798 configure_display: Starting display init
9044 23:06:33.289955 anx7625_power_on_init: Init interface.
9045 23:06:33.293238 anx7625_disable_pd_protocol: Disabled PD feature.
9046 23:06:33.296322 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9047 23:06:33.324394 anx7625_start_dp_work: Secure OCM version=00
9048 23:06:33.327670 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9049 23:06:33.342235 sp_tx_get_edid_block: EDID Block = 1
9050 23:06:33.444947 Extracted contents:
9051 23:06:33.448240 header: 00 ff ff ff ff ff ff 00
9052 23:06:33.451513 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9053 23:06:33.454882 version: 01 04
9054 23:06:33.458152 basic params: 95 1f 11 78 0a
9055 23:06:33.461708 chroma info: 76 90 94 55 54 90 27 21 50 54
9056 23:06:33.464696 established: 00 00 00
9057 23:06:33.471196 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9058 23:06:33.474519 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9059 23:06:33.481114 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9060 23:06:33.487854 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9061 23:06:33.494401 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9062 23:06:33.497844 extensions: 00
9063 23:06:33.497922 checksum: fb
9064 23:06:33.497984
9065 23:06:33.501096 Manufacturer: IVO Model 57d Serial Number 0
9066 23:06:33.504353 Made week 0 of 2020
9067 23:06:33.508048 EDID version: 1.4
9068 23:06:33.508128 Digital display
9069 23:06:33.511249 6 bits per primary color channel
9070 23:06:33.511330 DisplayPort interface
9071 23:06:33.514525 Maximum image size: 31 cm x 17 cm
9072 23:06:33.517613 Gamma: 220%
9073 23:06:33.517692 Check DPMS levels
9074 23:06:33.520971 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9075 23:06:33.527526 First detailed timing is preferred timing
9076 23:06:33.527607 Established timings supported:
9077 23:06:33.530565 Standard timings supported:
9078 23:06:33.533902 Detailed timings
9079 23:06:33.537655 Hex of detail: 383680a07038204018303c0035ae10000019
9080 23:06:33.543893 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9081 23:06:33.547356 0780 0798 07c8 0820 hborder 0
9082 23:06:33.550869 0438 043b 0447 0458 vborder 0
9083 23:06:33.553733 -hsync -vsync
9084 23:06:33.553811 Did detailed timing
9085 23:06:33.560534 Hex of detail: 000000000000000000000000000000000000
9086 23:06:33.563887 Manufacturer-specified data, tag 0
9087 23:06:33.566976 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9088 23:06:33.570337 ASCII string: InfoVision
9089 23:06:33.573768 Hex of detail: 000000fe00523134304e574635205248200a
9090 23:06:33.577023 ASCII string: R140NWF5 RH
9091 23:06:33.577102 Checksum
9092 23:06:33.580433 Checksum: 0xfb (valid)
9093 23:06:33.583659 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9094 23:06:33.587088 DSI data_rate: 832800000 bps
9095 23:06:33.593557 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9096 23:06:33.596637 anx7625_parse_edid: pixelclock(138800).
9097 23:06:33.600318 hactive(1920), hsync(48), hfp(24), hbp(88)
9098 23:06:33.603258 vactive(1080), vsync(12), vfp(3), vbp(17)
9099 23:06:33.606603 anx7625_dsi_config: config dsi.
9100 23:06:33.613502 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9101 23:06:33.626843 anx7625_dsi_config: success to config DSI
9102 23:06:33.630331 anx7625_dp_start: MIPI phy setup OK.
9103 23:06:33.633766 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9104 23:06:33.637114 mtk_ddp_mode_set invalid vrefresh 60
9105 23:06:33.640178 main_disp_path_setup
9106 23:06:33.640260 ovl_layer_smi_id_en
9107 23:06:33.643495 ovl_layer_smi_id_en
9108 23:06:33.643574 ccorr_config
9109 23:06:33.643636 aal_config
9110 23:06:33.646943 gamma_config
9111 23:06:33.647022 postmask_config
9112 23:06:33.650160 dither_config
9113 23:06:33.653516 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9114 23:06:33.660081 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9115 23:06:33.663266 Root Device init finished in 551 msecs
9116 23:06:33.666652 CPU_CLUSTER: 0 init
9117 23:06:33.673279 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9118 23:06:33.679989 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9119 23:06:33.680068 APU_MBOX 0x190000b0 = 0x10001
9120 23:06:33.683166 APU_MBOX 0x190001b0 = 0x10001
9121 23:06:33.686683 APU_MBOX 0x190005b0 = 0x10001
9122 23:06:33.689882 APU_MBOX 0x190006b0 = 0x10001
9123 23:06:33.693268 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9124 23:06:33.705825 read SPI 0x539f4 0xe237: 6246 us, 9271 KB/s, 74.168 Mbps
9125 23:06:33.718287 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9126 23:06:33.724901 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9127 23:06:33.736439 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9128 23:06:33.745641 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9129 23:06:33.749144 CPU_CLUSTER: 0 init finished in 81 msecs
9130 23:06:33.752522 Devices initialized
9131 23:06:33.755624 Show all devs... After init.
9132 23:06:33.755703 Root Device: enabled 1
9133 23:06:33.759062 CPU_CLUSTER: 0: enabled 1
9134 23:06:33.762209 CPU: 00: enabled 1
9135 23:06:33.765677 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9136 23:06:33.768757 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9137 23:06:33.772013 ELOG: NV offset 0x57f000 size 0x1000
9138 23:06:33.778847 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9139 23:06:33.786026 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9140 23:06:33.788657 ELOG: Event(17) added with size 13 at 2023-12-01 23:06:34 UTC
9141 23:06:33.795146 out: cmd=0x121: 03 db 21 01 00 00 00 00
9142 23:06:33.798392 in-header: 03 eb 00 00 2c 00 00 00
9143 23:06:33.811839 in-data: 78 64 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9144 23:06:33.815151 ELOG: Event(A1) added with size 10 at 2023-12-01 23:06:34 UTC
9145 23:06:33.821771 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9146 23:06:33.828193 ELOG: Event(A0) added with size 9 at 2023-12-01 23:06:34 UTC
9147 23:06:33.831331 elog_add_boot_reason: Logged dev mode boot
9148 23:06:33.838086 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9149 23:06:33.838181 Finalize devices...
9150 23:06:33.841402 Devices finalized
9151 23:06:33.845028 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9152 23:06:33.848156 Writing coreboot table at 0xffe64000
9153 23:06:33.854690 0. 000000000010a000-0000000000113fff: RAMSTAGE
9154 23:06:33.858000 1. 0000000040000000-00000000400fffff: RAM
9155 23:06:33.861138 2. 0000000040100000-000000004032afff: RAMSTAGE
9156 23:06:33.864679 3. 000000004032b000-00000000545fffff: RAM
9157 23:06:33.867776 4. 0000000054600000-000000005465ffff: BL31
9158 23:06:33.870873 5. 0000000054660000-00000000ffe63fff: RAM
9159 23:06:33.877514 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9160 23:06:33.881023 7. 0000000100000000-000000013fffffff: RAM
9161 23:06:33.884317 Passing 5 GPIOs to payload:
9162 23:06:33.887709 NAME | PORT | POLARITY | VALUE
9163 23:06:33.894225 EC in RW | 0x000000aa | low | undefined
9164 23:06:33.897422 EC interrupt | 0x00000005 | low | undefined
9165 23:06:33.904075 TPM interrupt | 0x000000ab | high | undefined
9166 23:06:33.907403 SD card detect | 0x00000011 | high | undefined
9167 23:06:33.910722 speaker enable | 0x00000093 | high | undefined
9168 23:06:33.914105 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9169 23:06:33.917249 in-header: 03 f8 00 00 02 00 00 00
9170 23:06:33.920785 in-data: 03 00
9171 23:06:33.924161 ADC[4]: Raw value=668958 ID=5
9172 23:06:33.927674 ADC[3]: Raw value=212549 ID=1
9173 23:06:33.927753 RAM Code: 0x51
9174 23:06:33.930725 ADC[6]: Raw value=74410 ID=0
9175 23:06:33.934019 ADC[5]: Raw value=211444 ID=1
9176 23:06:33.934099 SKU Code: 0x1
9177 23:06:33.940480 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 8b6a
9178 23:06:33.940605 coreboot table: 964 bytes.
9179 23:06:33.944161 IMD ROOT 0. 0xfffff000 0x00001000
9180 23:06:33.947117 IMD SMALL 1. 0xffffe000 0x00001000
9181 23:06:33.950401 RO MCACHE 2. 0xffffc000 0x00001104
9182 23:06:33.953873 CONSOLE 3. 0xfff7c000 0x00080000
9183 23:06:33.957106 FMAP 4. 0xfff7b000 0x00000452
9184 23:06:33.960302 TIME STAMP 5. 0xfff7a000 0x00000910
9185 23:06:33.963680 VBOOT WORK 6. 0xfff66000 0x00014000
9186 23:06:33.966939 RAMOOPS 7. 0xffe66000 0x00100000
9187 23:06:33.970126 COREBOOT 8. 0xffe64000 0x00002000
9188 23:06:33.973616 IMD small region:
9189 23:06:33.977226 IMD ROOT 0. 0xffffec00 0x00000400
9190 23:06:33.980416 VPD 1. 0xffffeb80 0x0000006c
9191 23:06:33.983601 MMC STATUS 2. 0xffffeb60 0x00000004
9192 23:06:33.990312 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9193 23:06:33.990391 Probing TPM: done!
9194 23:06:33.993791 Connected to device vid:did:rid of 1ae0:0028:00
9195 23:06:34.004987 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
9196 23:06:34.008387 Initialized TPM device CR50 revision 0
9197 23:06:34.011861 Checking cr50 for pending updates
9198 23:06:34.015659 Reading cr50 TPM mode
9199 23:06:34.024075 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9200 23:06:34.030627 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9201 23:06:34.071214 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9202 23:06:34.074147 Checking segment from ROM address 0x40100000
9203 23:06:34.077976 Checking segment from ROM address 0x4010001c
9204 23:06:34.084433 Loading segment from ROM address 0x40100000
9205 23:06:34.084572 code (compression=0)
9206 23:06:34.094302 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9207 23:06:34.101030 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9208 23:06:34.101111 it's not compressed!
9209 23:06:34.107430 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9210 23:06:34.110864 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9211 23:06:34.131302 Loading segment from ROM address 0x4010001c
9212 23:06:34.131383 Entry Point 0x80000000
9213 23:06:34.134847 Loaded segments
9214 23:06:34.138092 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9215 23:06:34.144450 Jumping to boot code at 0x80000000(0xffe64000)
9216 23:06:34.151452 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9217 23:06:34.157931 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9218 23:06:34.165995 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9219 23:06:34.168941 Checking segment from ROM address 0x40100000
9220 23:06:34.172301 Checking segment from ROM address 0x4010001c
9221 23:06:34.179128 Loading segment from ROM address 0x40100000
9222 23:06:34.179208 code (compression=1)
9223 23:06:34.185873 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9224 23:06:34.195438 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9225 23:06:34.195518 using LZMA
9226 23:06:34.204270 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9227 23:06:34.210878 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9228 23:06:34.213955 Loading segment from ROM address 0x4010001c
9229 23:06:34.214036 Entry Point 0x54601000
9230 23:06:34.217288 Loaded segments
9231 23:06:34.220678 NOTICE: MT8192 bl31_setup
9232 23:06:34.227744 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9233 23:06:34.230865 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9234 23:06:34.234421 WARNING: region 0:
9235 23:06:34.237610 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9236 23:06:34.237690 WARNING: region 1:
9237 23:06:34.244339 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9238 23:06:34.247618 WARNING: region 2:
9239 23:06:34.251270 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9240 23:06:34.254072 WARNING: region 3:
9241 23:06:34.257427 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9242 23:06:34.260968 WARNING: region 4:
9243 23:06:34.267555 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9244 23:06:34.267635 WARNING: region 5:
9245 23:06:34.270740 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9246 23:06:34.274052 WARNING: region 6:
9247 23:06:34.277376 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9248 23:06:34.280818 WARNING: region 7:
9249 23:06:34.284041 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9250 23:06:34.290560 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9251 23:06:34.294169 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9252 23:06:34.297119 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9253 23:06:34.303888 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9254 23:06:34.307356 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9255 23:06:34.313828 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9256 23:06:34.317271 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9257 23:06:34.320651 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9258 23:06:34.327072 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9259 23:06:34.330662 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9260 23:06:34.333957 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9261 23:06:34.340656 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9262 23:06:34.343856 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9263 23:06:34.347466 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9264 23:06:34.353957 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9265 23:06:34.357340 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9266 23:06:34.363919 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9267 23:06:34.367413 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9268 23:06:34.370569 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9269 23:06:34.377489 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9270 23:06:34.380496 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9271 23:06:34.383745 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9272 23:06:34.390414 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9273 23:06:34.394180 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9274 23:06:34.400514 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9275 23:06:34.403970 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9276 23:06:34.410511 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9277 23:06:34.413620 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9278 23:06:34.417242 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9279 23:06:34.423742 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9280 23:06:34.427408 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9281 23:06:34.430505 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9282 23:06:34.437348 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9283 23:06:34.440542 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9284 23:06:34.443880 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9285 23:06:34.446926 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9286 23:06:34.453723 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9287 23:06:34.457107 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9288 23:06:34.460347 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9289 23:06:34.463597 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9290 23:06:34.470434 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9291 23:06:34.473624 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9292 23:06:34.477114 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9293 23:06:34.480317 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9294 23:06:34.486944 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9295 23:06:34.490136 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9296 23:06:34.493534 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9297 23:06:34.497055 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9298 23:06:34.503929 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9299 23:06:34.507244 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9300 23:06:34.513837 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9301 23:06:34.516936 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9302 23:06:34.523937 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9303 23:06:34.526879 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9304 23:06:34.530462 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9305 23:06:34.537034 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9306 23:06:34.540517 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9307 23:06:34.547122 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9308 23:06:34.550285 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9309 23:06:34.556904 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9310 23:06:34.560170 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9311 23:06:34.566945 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9312 23:06:34.570395 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9313 23:06:34.573439 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9314 23:06:34.580679 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9315 23:06:34.583527 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9316 23:06:34.590292 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9317 23:06:34.593363 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9318 23:06:34.599956 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9319 23:06:34.603754 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9320 23:06:34.606601 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9321 23:06:34.613583 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9322 23:06:34.616842 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9323 23:06:34.623108 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9324 23:06:34.626356 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9325 23:06:34.633094 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9326 23:06:34.636510 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9327 23:06:34.643360 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9328 23:06:34.646231 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9329 23:06:34.653243 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9330 23:06:34.656317 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9331 23:06:34.659858 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9332 23:06:34.666327 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9333 23:06:34.669571 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9334 23:06:34.676239 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9335 23:06:34.679485 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9336 23:06:34.686274 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9337 23:06:34.689486 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9338 23:06:34.693189 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9339 23:06:34.699475 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9340 23:06:34.702652 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9341 23:06:34.709336 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9342 23:06:34.712907 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9343 23:06:34.719303 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9344 23:06:34.722625 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9345 23:06:34.729299 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9346 23:06:34.732808 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9347 23:06:34.735968 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9348 23:06:34.739238 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9349 23:06:34.745795 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9350 23:06:34.749277 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9351 23:06:34.752490 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9352 23:06:34.759316 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9353 23:06:34.762680 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9354 23:06:34.766248 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9355 23:06:34.772817 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9356 23:06:34.775861 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9357 23:06:34.782507 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9358 23:06:34.785861 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9359 23:06:34.789316 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9360 23:06:34.795734 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9361 23:06:34.799231 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9362 23:06:34.805738 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9363 23:06:34.809245 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9364 23:06:34.812566 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9365 23:06:34.819112 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9366 23:06:34.822548 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9367 23:06:34.825718 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9368 23:06:34.832441 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9369 23:06:34.835677 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9370 23:06:34.839152 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9371 23:06:34.842380 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9372 23:06:34.848931 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9373 23:06:34.852365 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9374 23:06:34.855780 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9375 23:06:34.862436 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9376 23:06:34.865836 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9377 23:06:34.868840 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9378 23:06:34.875751 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9379 23:06:34.878795 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9380 23:06:34.885644 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9381 23:06:34.888833 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9382 23:06:34.892244 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9383 23:06:34.898804 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9384 23:06:34.902375 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9385 23:06:34.908963 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9386 23:06:34.912329 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9387 23:06:34.915677 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9388 23:06:34.922135 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9389 23:06:34.925695 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9390 23:06:34.928880 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9391 23:06:34.935537 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9392 23:06:34.938757 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9393 23:06:34.945343 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9394 23:06:34.948883 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9395 23:06:34.952301 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9396 23:06:34.959332 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9397 23:06:34.962243 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9398 23:06:34.968982 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9399 23:06:34.972082 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9400 23:06:34.975648 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9401 23:06:34.982054 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9402 23:06:34.985311 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9403 23:06:34.988756 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9404 23:06:34.995498 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9405 23:06:34.998789 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9406 23:06:35.005495 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9407 23:06:35.008501 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9408 23:06:35.012346 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9409 23:06:35.018738 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9410 23:06:35.022076 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9411 23:06:35.028642 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9412 23:06:35.031815 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9413 23:06:35.035091 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9414 23:06:35.041808 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9415 23:06:35.045104 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9416 23:06:35.051520 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9417 23:06:35.055156 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9418 23:06:35.058463 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9419 23:06:35.065241 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9420 23:06:35.068148 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9421 23:06:35.074583 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9422 23:06:35.078121 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9423 23:06:35.081256 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9424 23:06:35.088163 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9425 23:06:35.091205 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9426 23:06:35.097776 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9427 23:06:35.101346 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9428 23:06:35.104336 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9429 23:06:35.110790 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9430 23:06:35.114445 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9431 23:06:35.120871 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9432 23:06:35.124241 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9433 23:06:35.127875 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9434 23:06:35.134077 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9435 23:06:35.137410 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9436 23:06:35.143843 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9437 23:06:35.147058 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9438 23:06:35.150629 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9439 23:06:35.157038 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9440 23:06:35.160664 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9441 23:06:35.166965 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9442 23:06:35.170291 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9443 23:06:35.176949 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9444 23:06:35.180249 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9445 23:06:35.183454 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9446 23:06:35.190344 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9447 23:06:35.193648 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9448 23:06:35.199904 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9449 23:06:35.203266 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9450 23:06:35.210090 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9451 23:06:35.213080 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9452 23:06:35.216706 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9453 23:06:35.223186 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9454 23:06:35.226512 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9455 23:06:35.233199 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9456 23:06:35.236398 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9457 23:06:35.242691 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9458 23:06:35.245959 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9459 23:06:35.249301 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9460 23:06:35.256090 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9461 23:06:35.259530 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9462 23:06:35.265955 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9463 23:06:35.269098 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9464 23:06:35.275970 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9465 23:06:35.279081 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9466 23:06:35.282378 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9467 23:06:35.289134 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9468 23:06:35.292438 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9469 23:06:35.299046 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9470 23:06:35.302233 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9471 23:06:35.308749 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9472 23:06:35.311972 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9473 23:06:35.315243 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9474 23:06:35.322121 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9475 23:06:35.325481 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9476 23:06:35.331848 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9477 23:06:35.335035 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9478 23:06:35.341935 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9479 23:06:35.345390 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9480 23:06:35.348437 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9481 23:06:35.351639 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9482 23:06:35.354891 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9483 23:06:35.361433 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9484 23:06:35.364830 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9485 23:06:35.367903 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9486 23:06:35.374661 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9487 23:06:35.377971 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9488 23:06:35.384756 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9489 23:06:35.387954 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9490 23:06:35.391138 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9491 23:06:35.397881 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9492 23:06:35.400973 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9493 23:06:35.404454 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9494 23:06:35.410882 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9495 23:06:35.414341 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9496 23:06:35.420739 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9497 23:06:35.424121 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9498 23:06:35.427355 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9499 23:06:35.433914 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9500 23:06:35.437389 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9501 23:06:35.440660 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9502 23:06:35.447149 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9503 23:06:35.450443 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9504 23:06:35.457171 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9505 23:06:35.460604 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9506 23:06:35.463721 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9507 23:06:35.470488 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9508 23:06:35.473621 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9509 23:06:35.476945 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9510 23:06:35.483559 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9511 23:06:35.486769 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9512 23:06:35.493196 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9513 23:06:35.496487 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9514 23:06:35.499838 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9515 23:06:35.506368 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9516 23:06:35.509536 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9517 23:06:35.516355 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9518 23:06:35.519727 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9519 23:06:35.523055 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9520 23:06:35.526332 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9521 23:06:35.529641 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9522 23:06:35.536177 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9523 23:06:35.539499 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9524 23:06:35.542819 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9525 23:06:35.546158 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9526 23:06:35.552783 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9527 23:06:35.556281 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9528 23:06:35.559388 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9529 23:06:35.562658 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9530 23:06:35.569389 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9531 23:06:35.572777 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9532 23:06:35.579129 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9533 23:06:35.582462 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9534 23:06:35.585573 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9535 23:06:35.592518 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9536 23:06:35.595798 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9537 23:06:35.602145 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9538 23:06:35.605530 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9539 23:06:35.608777 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9540 23:06:35.615606 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9541 23:06:35.618968 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9542 23:06:35.625303 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9543 23:06:35.628663 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9544 23:06:35.635356 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9545 23:06:35.638685 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9546 23:06:35.642057 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9547 23:06:35.648728 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9548 23:06:35.651791 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9549 23:06:35.658242 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9550 23:06:35.661995 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9551 23:06:35.668173 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9552 23:06:35.671344 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9553 23:06:35.674778 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9554 23:06:35.681381 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9555 23:06:35.684543 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9556 23:06:35.691133 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9557 23:06:35.694670 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9558 23:06:35.698336 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9559 23:06:35.704368 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9560 23:06:35.707825 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9561 23:06:35.714699 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9562 23:06:35.717631 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9563 23:06:35.720851 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9564 23:06:35.727485 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9565 23:06:35.730912 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9566 23:06:35.737477 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9567 23:06:35.740745 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9568 23:06:35.747426 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9569 23:06:35.750910 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9570 23:06:35.757641 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9571 23:06:35.760880 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9572 23:06:35.763839 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9573 23:06:35.770401 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9574 23:06:35.773631 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9575 23:06:35.780327 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9576 23:06:35.783776 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9577 23:06:35.786865 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9578 23:06:35.793348 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9579 23:06:35.796617 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9580 23:06:35.803178 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9581 23:06:35.806725 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9582 23:06:35.809865 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9583 23:06:35.816649 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9584 23:06:35.820098 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9585 23:06:35.826436 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9586 23:06:35.829787 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9587 23:06:35.833197 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9588 23:06:35.839463 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9589 23:06:35.842893 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9590 23:06:35.849370 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9591 23:06:35.852819 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9592 23:06:35.859463 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9593 23:06:35.862875 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9594 23:06:35.869432 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9595 23:06:35.873040 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9596 23:06:35.875892 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9597 23:06:35.882473 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9598 23:06:35.885805 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9599 23:06:35.892559 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9600 23:06:35.895735 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9601 23:06:35.898998 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9602 23:06:35.906079 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9603 23:06:35.909068 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9604 23:06:35.915532 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9605 23:06:35.918782 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9606 23:06:35.922056 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9607 23:06:35.928707 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9608 23:06:35.932238 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9609 23:06:35.938497 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9610 23:06:35.941843 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9611 23:06:35.948420 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9612 23:06:35.951871 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9613 23:06:35.958559 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9614 23:06:35.961854 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9615 23:06:35.968255 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9616 23:06:35.971510 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9617 23:06:35.975186 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9618 23:06:35.981510 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9619 23:06:35.984772 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9620 23:06:35.991415 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9621 23:06:35.994428 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9622 23:06:36.001341 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9623 23:06:36.004487 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9624 23:06:36.011053 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9625 23:06:36.014678 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9626 23:06:36.017618 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9627 23:06:36.024197 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9628 23:06:36.027450 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9629 23:06:36.034014 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9630 23:06:36.037887 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9631 23:06:36.044290 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9632 23:06:36.047268 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9633 23:06:36.053991 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9634 23:06:36.057235 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9635 23:06:36.060670 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9636 23:06:36.067083 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9637 23:06:36.070381 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9638 23:06:36.076927 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9639 23:06:36.080747 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9640 23:06:36.086904 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9641 23:06:36.090254 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9642 23:06:36.096878 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9643 23:06:36.100314 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9644 23:06:36.103515 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9645 23:06:36.110296 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9646 23:06:36.113552 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9647 23:06:36.119981 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9648 23:06:36.123055 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9649 23:06:36.129879 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9650 23:06:36.133431 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9651 23:06:36.136674 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9652 23:06:36.143326 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9653 23:06:36.146504 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9654 23:06:36.153287 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9655 23:06:36.156158 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9656 23:06:36.162989 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9657 23:06:36.166319 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9658 23:06:36.173068 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9659 23:06:36.176193 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9660 23:06:36.182899 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9661 23:06:36.186279 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9662 23:06:36.192903 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9663 23:06:36.196030 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9664 23:06:36.202615 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9665 23:06:36.205973 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9666 23:06:36.212467 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9667 23:06:36.215812 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9668 23:06:36.219241 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9669 23:06:36.226109 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9670 23:06:36.228881 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9671 23:06:36.235677 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9672 23:06:36.238869 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9673 23:06:36.245730 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9674 23:06:36.252195 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9675 23:06:36.255465 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9676 23:06:36.262082 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9677 23:06:36.265275 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9678 23:06:36.271926 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9679 23:06:36.275343 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9680 23:06:36.281821 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9681 23:06:36.285068 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9682 23:06:36.291414 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9683 23:06:36.294763 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9684 23:06:36.298264 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9685 23:06:36.301630 INFO: [APUAPC] vio 0
9686 23:06:36.307902 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9687 23:06:36.311394 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9688 23:06:36.314702 INFO: [APUAPC] D0_APC_0: 0x400510
9689 23:06:36.317812 INFO: [APUAPC] D0_APC_1: 0x0
9690 23:06:36.321281 INFO: [APUAPC] D0_APC_2: 0x1540
9691 23:06:36.324449 INFO: [APUAPC] D0_APC_3: 0x0
9692 23:06:36.327929 INFO: [APUAPC] D1_APC_0: 0xffffffff
9693 23:06:36.331108 INFO: [APUAPC] D1_APC_1: 0xffffffff
9694 23:06:36.334429 INFO: [APUAPC] D1_APC_2: 0x3fffff
9695 23:06:36.337732 INFO: [APUAPC] D1_APC_3: 0x0
9696 23:06:36.340962 INFO: [APUAPC] D2_APC_0: 0xffffffff
9697 23:06:36.344470 INFO: [APUAPC] D2_APC_1: 0xffffffff
9698 23:06:36.347544 INFO: [APUAPC] D2_APC_2: 0x3fffff
9699 23:06:36.350759 INFO: [APUAPC] D2_APC_3: 0x0
9700 23:06:36.354294 INFO: [APUAPC] D3_APC_0: 0xffffffff
9701 23:06:36.357437 INFO: [APUAPC] D3_APC_1: 0xffffffff
9702 23:06:36.360981 INFO: [APUAPC] D3_APC_2: 0x3fffff
9703 23:06:36.361061 INFO: [APUAPC] D3_APC_3: 0x0
9704 23:06:36.367384 INFO: [APUAPC] D4_APC_0: 0xffffffff
9705 23:06:36.370685 INFO: [APUAPC] D4_APC_1: 0xffffffff
9706 23:06:36.374034 INFO: [APUAPC] D4_APC_2: 0x3fffff
9707 23:06:36.374113 INFO: [APUAPC] D4_APC_3: 0x0
9708 23:06:36.377262 INFO: [APUAPC] D5_APC_0: 0xffffffff
9709 23:06:36.383923 INFO: [APUAPC] D5_APC_1: 0xffffffff
9710 23:06:36.384028 INFO: [APUAPC] D5_APC_2: 0x3fffff
9711 23:06:36.387176 INFO: [APUAPC] D5_APC_3: 0x0
9712 23:06:36.390338 INFO: [APUAPC] D6_APC_0: 0xffffffff
9713 23:06:36.393764 INFO: [APUAPC] D6_APC_1: 0xffffffff
9714 23:06:36.397278 INFO: [APUAPC] D6_APC_2: 0x3fffff
9715 23:06:36.400437 INFO: [APUAPC] D6_APC_3: 0x0
9716 23:06:36.404052 INFO: [APUAPC] D7_APC_0: 0xffffffff
9717 23:06:36.407306 INFO: [APUAPC] D7_APC_1: 0xffffffff
9718 23:06:36.410542 INFO: [APUAPC] D7_APC_2: 0x3fffff
9719 23:06:36.413573 INFO: [APUAPC] D7_APC_3: 0x0
9720 23:06:36.416947 INFO: [APUAPC] D8_APC_0: 0xffffffff
9721 23:06:36.420137 INFO: [APUAPC] D8_APC_1: 0xffffffff
9722 23:06:36.423674 INFO: [APUAPC] D8_APC_2: 0x3fffff
9723 23:06:36.426906 INFO: [APUAPC] D8_APC_3: 0x0
9724 23:06:36.430119 INFO: [APUAPC] D9_APC_0: 0xffffffff
9725 23:06:36.433473 INFO: [APUAPC] D9_APC_1: 0xffffffff
9726 23:06:36.436820 INFO: [APUAPC] D9_APC_2: 0x3fffff
9727 23:06:36.440314 INFO: [APUAPC] D9_APC_3: 0x0
9728 23:06:36.443276 INFO: [APUAPC] D10_APC_0: 0xffffffff
9729 23:06:36.447059 INFO: [APUAPC] D10_APC_1: 0xffffffff
9730 23:06:36.450067 INFO: [APUAPC] D10_APC_2: 0x3fffff
9731 23:06:36.453455 INFO: [APUAPC] D10_APC_3: 0x0
9732 23:06:36.456778 INFO: [APUAPC] D11_APC_0: 0xffffffff
9733 23:06:36.459830 INFO: [APUAPC] D11_APC_1: 0xffffffff
9734 23:06:36.463413 INFO: [APUAPC] D11_APC_2: 0x3fffff
9735 23:06:36.466569 INFO: [APUAPC] D11_APC_3: 0x0
9736 23:06:36.469800 INFO: [APUAPC] D12_APC_0: 0xffffffff
9737 23:06:36.473015 INFO: [APUAPC] D12_APC_1: 0xffffffff
9738 23:06:36.476357 INFO: [APUAPC] D12_APC_2: 0x3fffff
9739 23:06:36.479744 INFO: [APUAPC] D12_APC_3: 0x0
9740 23:06:36.482962 INFO: [APUAPC] D13_APC_0: 0xffffffff
9741 23:06:36.486165 INFO: [APUAPC] D13_APC_1: 0xffffffff
9742 23:06:36.489659 INFO: [APUAPC] D13_APC_2: 0x3fffff
9743 23:06:36.493013 INFO: [APUAPC] D13_APC_3: 0x0
9744 23:06:36.496203 INFO: [APUAPC] D14_APC_0: 0xffffffff
9745 23:06:36.499570 INFO: [APUAPC] D14_APC_1: 0xffffffff
9746 23:06:36.502634 INFO: [APUAPC] D14_APC_2: 0x3fffff
9747 23:06:36.506394 INFO: [APUAPC] D14_APC_3: 0x0
9748 23:06:36.509270 INFO: [APUAPC] D15_APC_0: 0xffffffff
9749 23:06:36.515847 INFO: [APUAPC] D15_APC_1: 0xffffffff
9750 23:06:36.519160 INFO: [APUAPC] D15_APC_2: 0x3fffff
9751 23:06:36.519240 INFO: [APUAPC] D15_APC_3: 0x0
9752 23:06:36.522367 INFO: [APUAPC] APC_CON: 0x4
9753 23:06:36.525612 INFO: [NOCDAPC] D0_APC_0: 0x0
9754 23:06:36.528784 INFO: [NOCDAPC] D0_APC_1: 0x0
9755 23:06:36.532233 INFO: [NOCDAPC] D1_APC_0: 0x0
9756 23:06:36.535826 INFO: [NOCDAPC] D1_APC_1: 0xfff
9757 23:06:36.539165 INFO: [NOCDAPC] D2_APC_0: 0x0
9758 23:06:36.542202 INFO: [NOCDAPC] D2_APC_1: 0xfff
9759 23:06:36.545371 INFO: [NOCDAPC] D3_APC_0: 0x0
9760 23:06:36.548875 INFO: [NOCDAPC] D3_APC_1: 0xfff
9761 23:06:36.548954 INFO: [NOCDAPC] D4_APC_0: 0x0
9762 23:06:36.552103 INFO: [NOCDAPC] D4_APC_1: 0xfff
9763 23:06:36.555601 INFO: [NOCDAPC] D5_APC_0: 0x0
9764 23:06:36.558897 INFO: [NOCDAPC] D5_APC_1: 0xfff
9765 23:06:36.561900 INFO: [NOCDAPC] D6_APC_0: 0x0
9766 23:06:36.565257 INFO: [NOCDAPC] D6_APC_1: 0xfff
9767 23:06:36.568491 INFO: [NOCDAPC] D7_APC_0: 0x0
9768 23:06:36.571841 INFO: [NOCDAPC] D7_APC_1: 0xfff
9769 23:06:36.575163 INFO: [NOCDAPC] D8_APC_0: 0x0
9770 23:06:36.578532 INFO: [NOCDAPC] D8_APC_1: 0xfff
9771 23:06:36.581922 INFO: [NOCDAPC] D9_APC_0: 0x0
9772 23:06:36.584882 INFO: [NOCDAPC] D9_APC_1: 0xfff
9773 23:06:36.584961 INFO: [NOCDAPC] D10_APC_0: 0x0
9774 23:06:36.588436 INFO: [NOCDAPC] D10_APC_1: 0xfff
9775 23:06:36.591525 INFO: [NOCDAPC] D11_APC_0: 0x0
9776 23:06:36.594912 INFO: [NOCDAPC] D11_APC_1: 0xfff
9777 23:06:36.598548 INFO: [NOCDAPC] D12_APC_0: 0x0
9778 23:06:36.601524 INFO: [NOCDAPC] D12_APC_1: 0xfff
9779 23:06:36.604981 INFO: [NOCDAPC] D13_APC_0: 0x0
9780 23:06:36.608234 INFO: [NOCDAPC] D13_APC_1: 0xfff
9781 23:06:36.611579 INFO: [NOCDAPC] D14_APC_0: 0x0
9782 23:06:36.614703 INFO: [NOCDAPC] D14_APC_1: 0xfff
9783 23:06:36.617977 INFO: [NOCDAPC] D15_APC_0: 0x0
9784 23:06:36.621239 INFO: [NOCDAPC] D15_APC_1: 0xfff
9785 23:06:36.624702 INFO: [NOCDAPC] APC_CON: 0x4
9786 23:06:36.627880 INFO: [APUAPC] set_apusys_apc done
9787 23:06:36.631312 INFO: [DEVAPC] devapc_init done
9788 23:06:36.635195 INFO: GICv3 without legacy support detected.
9789 23:06:36.637868 INFO: ARM GICv3 driver initialized in EL3
9790 23:06:36.641069 INFO: Maximum SPI INTID supported: 639
9791 23:06:36.644643 INFO: BL31: Initializing runtime services
9792 23:06:36.650973 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9793 23:06:36.654512 INFO: SPM: enable CPC mode
9794 23:06:36.661011 INFO: mcdi ready for mcusys-off-idle and system suspend
9795 23:06:36.664159 INFO: BL31: Preparing for EL3 exit to normal world
9796 23:06:36.667444 INFO: Entry point address = 0x80000000
9797 23:06:36.670978 INFO: SPSR = 0x8
9798 23:06:36.675459
9799 23:06:36.675537
9800 23:06:36.675599
9801 23:06:36.678803 Starting depthcharge on Spherion...
9802 23:06:36.678882
9803 23:06:36.678944 Wipe memory regions:
9804 23:06:36.679002
9805 23:06:36.679654 end: 2.2.3 depthcharge-start (duration 00:00:28) [common]
9806 23:06:36.679750 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
9807 23:06:36.679834 Setting prompt string to ['asurada:']
9808 23:06:36.679913 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
9809 23:06:36.682217 [0x00000040000000, 0x00000054600000)
9810 23:06:36.804387
9811 23:06:36.804522 [0x00000054660000, 0x00000080000000)
9812 23:06:37.065027
9813 23:06:37.065159 [0x000000821a7280, 0x000000ffe64000)
9814 23:06:37.809641
9815 23:06:37.809784 [0x00000100000000, 0x00000140000000)
9816 23:06:38.190583
9817 23:06:38.193886 Initializing XHCI USB controller at 0x11200000.
9818 23:06:39.231608
9819 23:06:39.234661 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9820 23:06:39.234743
9821 23:06:39.234805
9822 23:06:39.234862
9823 23:06:39.235139 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9825 23:06:39.335476 asurada: tftpboot 192.168.201.1 12154433/tftp-deploy-0q52bfe7/kernel/image.itb 12154433/tftp-deploy-0q52bfe7/kernel/cmdline
9826 23:06:39.335594 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9827 23:06:39.335689 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:24)
9828 23:06:39.339657 tftpboot 192.168.201.1 12154433/tftp-deploy-0q52bfe7/kernel/image.ittp-deploy-0q52bfe7/kernel/cmdline
9829 23:06:39.339742
9830 23:06:39.339804 Waiting for link
9831 23:06:39.500329
9832 23:06:39.500440 R8152: Initializing
9833 23:06:39.500502
9834 23:06:39.503381 Version 9 (ocp_data = 6010)
9835 23:06:39.503464
9836 23:06:39.507117 R8152: Done initializing
9837 23:06:39.507197
9838 23:06:39.507259 Adding net device
9839 23:06:41.393422
9840 23:06:41.393590 done.
9841 23:06:41.393658
9842 23:06:41.393717 MAC: 00:e0:4c:68:03:bd
9843 23:06:41.393773
9844 23:06:41.396723 Sending DHCP discover... done.
9845 23:06:41.396804
9846 23:06:41.400102 Waiting for reply... done.
9847 23:06:41.400183
9848 23:06:41.403388 Sending DHCP request... done.
9849 23:06:41.403468
9850 23:06:41.407921 Waiting for reply... done.
9851 23:06:41.408001
9852 23:06:41.408062 My ip is 192.168.201.16
9853 23:06:41.408120
9854 23:06:41.411388 The DHCP server ip is 192.168.201.1
9855 23:06:41.411467
9856 23:06:41.418216 TFTP server IP predefined by user: 192.168.201.1
9857 23:06:41.418296
9858 23:06:41.424433 Bootfile predefined by user: 12154433/tftp-deploy-0q52bfe7/kernel/image.itb
9859 23:06:41.424570
9860 23:06:41.427615 Sending tftp read request... done.
9861 23:06:41.427695
9862 23:06:41.431493 Waiting for the transfer...
9863 23:06:41.431571
9864 23:06:41.724296 00000000 ################################################################
9865 23:06:41.724460
9866 23:06:41.983822 00080000 ################################################################
9867 23:06:41.983966
9868 23:06:42.234646 00100000 ################################################################
9869 23:06:42.234784
9870 23:06:42.491120 00180000 ################################################################
9871 23:06:42.491280
9872 23:06:42.743510 00200000 ################################################################
9873 23:06:42.743642
9874 23:06:42.995356 00280000 ################################################################
9875 23:06:42.995494
9876 23:06:43.245342 00300000 ################################################################
9877 23:06:43.245476
9878 23:06:43.497108 00380000 ################################################################
9879 23:06:43.497240
9880 23:06:43.751597 00400000 ################################################################
9881 23:06:43.751734
9882 23:06:44.002558 00480000 ################################################################
9883 23:06:44.002696
9884 23:06:44.254639 00500000 ################################################################
9885 23:06:44.254780
9886 23:06:44.504090 00580000 ################################################################
9887 23:06:44.504275
9888 23:06:44.755470 00600000 ################################################################
9889 23:06:44.755608
9890 23:06:45.007126 00680000 ################################################################
9891 23:06:45.007287
9892 23:06:45.259232 00700000 ################################################################
9893 23:06:45.259368
9894 23:06:45.510828 00780000 ################################################################
9895 23:06:45.510964
9896 23:06:45.762121 00800000 ################################################################
9897 23:06:45.762255
9898 23:06:46.013800 00880000 ################################################################
9899 23:06:46.013937
9900 23:06:46.271491 00900000 ################################################################
9901 23:06:46.271655
9902 23:06:46.522664 00980000 ################################################################
9903 23:06:46.522806
9904 23:06:46.777407 00a00000 ################################################################
9905 23:06:46.777573
9906 23:06:47.029598 00a80000 ################################################################
9907 23:06:47.029733
9908 23:06:47.284286 00b00000 ################################################################
9909 23:06:47.284482
9910 23:06:47.536813 00b80000 ################################################################
9911 23:06:47.536956
9912 23:06:47.788129 00c00000 ################################################################
9913 23:06:47.788253
9914 23:06:48.039838 00c80000 ################################################################
9915 23:06:48.039977
9916 23:06:48.290395 00d00000 ################################################################
9917 23:06:48.290516
9918 23:06:48.541487 00d80000 ################################################################
9919 23:06:48.541616
9920 23:06:48.800364 00e00000 ################################################################
9921 23:06:48.800538
9922 23:06:49.057676 00e80000 ################################################################
9923 23:06:49.057796
9924 23:06:49.328857 00f00000 ################################################################
9925 23:06:49.328988
9926 23:06:49.594292 00f80000 ################################################################
9927 23:06:49.594419
9928 23:06:49.845477 01000000 ################################################################
9929 23:06:49.845626
9930 23:06:50.098522 01080000 ################################################################
9931 23:06:50.098673
9932 23:06:50.351028 01100000 ################################################################
9933 23:06:50.351158
9934 23:06:50.617464 01180000 ################################################################
9935 23:06:50.617593
9936 23:06:50.868765 01200000 ################################################################
9937 23:06:50.868898
9938 23:06:51.119817 01280000 ################################################################
9939 23:06:51.119956
9940 23:06:51.370819 01300000 ################################################################
9941 23:06:51.370973
9942 23:06:51.648077 01380000 ################################################################
9943 23:06:51.648236
9944 23:06:51.932514 01400000 ################################################################
9945 23:06:51.932681
9946 23:06:52.213689 01480000 ################################################################
9947 23:06:52.213820
9948 23:06:52.492498 01500000 ################################################################
9949 23:06:52.492627
9950 23:06:52.769809 01580000 ################################################################
9951 23:06:52.769946
9952 23:06:53.037428 01600000 ################################################################
9953 23:06:53.037562
9954 23:06:53.298143 01680000 ################################################################
9955 23:06:53.298270
9956 23:06:53.549483 01700000 ################################################################
9957 23:06:53.549616
9958 23:06:53.801953 01780000 ################################################################
9959 23:06:53.802074
9960 23:06:54.074980 01800000 ################################################################
9961 23:06:54.075139
9962 23:06:54.346679 01880000 ################################################################
9963 23:06:54.346826
9964 23:06:54.648016 01900000 ################################################################
9965 23:06:54.648146
9966 23:06:54.950052 01980000 ################################################################
9967 23:06:54.950223
9968 23:06:55.230132 01a00000 ################################################################
9969 23:06:55.230262
9970 23:06:55.507298 01a80000 ################################################################
9971 23:06:55.507455
9972 23:06:55.758637 01b00000 ################################################################
9973 23:06:55.758785
9974 23:06:55.787195 01b80000 ######## done.
9975 23:06:55.787273
9976 23:06:55.790536 The bootfile was 28893254 bytes long.
9977 23:06:55.790705
9978 23:06:55.793971 Sending tftp read request... done.
9979 23:06:55.794082
9980 23:06:55.794148 Waiting for the transfer...
9981 23:06:55.794210
9982 23:06:55.797267 00000000 # done.
9983 23:06:55.797360
9984 23:06:55.803708 Command line loaded dynamically from TFTP file: 12154433/tftp-deploy-0q52bfe7/kernel/cmdline
9985 23:06:55.803838
9986 23:06:55.827633 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12154433/extract-nfsrootfs-3jw6zot7,tcp,hard ip=dhcp tftpserverip=192.168.201.1
9987 23:06:55.827897
9988 23:06:55.828040 Loading FIT.
9989 23:06:55.828168
9990 23:06:55.830194 Image ramdisk-1 has 17799959 bytes.
9991 23:06:55.830392
9992 23:06:55.833585 Image fdt-1 has 47278 bytes.
9993 23:06:55.833870
9994 23:06:55.837046 Image kernel-1 has 11043984 bytes.
9995 23:06:55.837371
9996 23:06:55.847057 Compat preference: google,spherion-rev3-sku1 google,spherion-rev3 google,spherion-sku1 google,spherion
9997 23:06:55.847528
9998 23:06:55.863956 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 (match) google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
9999 23:06:55.864590
10000 23:06:55.870154 Choosing best match conf-1 for compat google,spherion-rev3.
10001 23:06:55.870712
10002 23:06:55.878397 Connected to device vid:did:rid of 1ae0:0028:00
10003 23:06:55.886113
10004 23:06:55.889264 tpm_get_response: command 0x17b, return code 0x0
10005 23:06:55.889718
10006 23:06:55.893069 ec_init: CrosEC protocol v3 supported (256, 248)
10007 23:06:55.897135
10008 23:06:55.900350 tpm_cleanup: add release locality here.
10009 23:06:55.900944
10010 23:06:55.901301 Shutting down all USB controllers.
10011 23:06:55.903496
10012 23:06:55.903965 Removing current net device
10013 23:06:55.904325
10014 23:06:55.910007 Exiting depthcharge with code 4 at timestamp: 47465708
10015 23:06:55.910695
10016 23:06:55.913243 LZMA decompressing kernel-1 to 0x821a6718
10017 23:06:55.913710
10018 23:06:55.916469 LZMA decompressing kernel-1 to 0x40000000
10019 23:06:57.309928
10020 23:06:57.310492 jumping to kernel
10021 23:06:57.313273 end: 2.2.4 bootloader-commands (duration 00:00:21) [common]
10022 23:06:57.314017 start: 2.2.5 auto-login-action (timeout 00:04:06) [common]
10023 23:06:57.314598 Setting prompt string to ['Linux version [0-9]']
10024 23:06:57.315147 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10025 23:06:57.315284 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10026 23:06:57.360110
10027 23:06:57.363479 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10028 23:06:57.367310 start: 2.2.5.1 login-action (timeout 00:04:06) [common]
10029 23:06:57.367883 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10030 23:06:57.368268 Setting prompt string to []
10031 23:06:57.368726 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10032 23:06:57.369107 Using line separator: #'\n'#
10033 23:06:57.369604 No login prompt set.
10034 23:06:57.369981 Parsing kernel messages
10035 23:06:57.370287 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10036 23:06:57.370830 [login-action] Waiting for messages, (timeout 00:04:06)
10037 23:06:57.386539 [ 0.000000] Linux version 6.1.64-cip10 (KernelCI@build-j31357-arm64-gcc-10-defconfig-arm64-chromebook-69txj) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Dec 1 22:47:09 UTC 2023
10038 23:06:57.390055 [ 0.000000] random: crng init done
10039 23:06:57.396777 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10040 23:06:57.399818 [ 0.000000] efi: UEFI not found.
10041 23:06:57.406790 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10042 23:06:57.413298 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10043 23:06:57.422708 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10044 23:06:57.433094 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10045 23:06:57.439321 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10046 23:06:57.446024 [ 0.000000] printk: bootconsole [mtk8250] enabled
10047 23:06:57.452499 [ 0.000000] NUMA: No NUMA configuration found
10048 23:06:57.458978 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10049 23:06:57.462621 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d4a00-0x13f7d6fff]
10050 23:06:57.466142 [ 0.000000] Zone ranges:
10051 23:06:57.472198 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10052 23:06:57.475792 [ 0.000000] DMA32 empty
10053 23:06:57.482381 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10054 23:06:57.485520 [ 0.000000] Movable zone start for each node
10055 23:06:57.489082 [ 0.000000] Early memory node ranges
10056 23:06:57.495571 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10057 23:06:57.502208 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10058 23:06:57.508442 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10059 23:06:57.515057 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10060 23:06:57.521923 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10061 23:06:57.528126 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10062 23:06:57.558227 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10063 23:06:57.564908 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10064 23:06:57.571760 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10065 23:06:57.574923 [ 0.000000] psci: probing for conduit method from DT.
10066 23:06:57.581700 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10067 23:06:57.584753 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10068 23:06:57.591414 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10069 23:06:57.594677 [ 0.000000] psci: SMC Calling Convention v1.2
10070 23:06:57.601248 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10071 23:06:57.604724 [ 0.000000] Detected VIPT I-cache on CPU0
10072 23:06:57.611477 [ 0.000000] CPU features: detected: GIC system register CPU interface
10073 23:06:57.617604 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10074 23:06:57.624598 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10075 23:06:57.631067 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10076 23:06:57.640934 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10077 23:06:57.647491 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10078 23:06:57.650799 [ 0.000000] alternatives: applying boot alternatives
10079 23:06:57.657695 [ 0.000000] Fallback order for Node 0: 0
10080 23:06:57.664459 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10081 23:06:57.667010 [ 0.000000] Policy zone: Normal
10082 23:06:57.690500 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12154433/extract-nfsrootfs-3jw6zot7,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10083 23:06:57.700732 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10084 23:06:57.710112 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10085 23:06:57.716970 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10086 23:06:57.723147 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10087 23:06:57.729759 <6>[ 0.000000] software IO TLB: area num 8.
10088 23:06:57.784986 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10089 23:06:57.865134 <6>[ 0.000000] Memory: 3837760K/4191232K available (17984K kernel code, 4116K rwdata, 17316K rodata, 8448K init, 615K bss, 320704K reserved, 32768K cma-reserved)
10090 23:06:57.871709 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10091 23:06:57.878669 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10092 23:06:57.881847 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10093 23:06:57.888277 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10094 23:06:57.894886 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10095 23:06:57.898185 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10096 23:06:57.908307 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10097 23:06:57.914603 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10098 23:06:57.921599 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10099 23:06:57.928263 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10100 23:06:57.931529 <6>[ 0.000000] GICv3: 608 SPIs implemented
10101 23:06:57.934256 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10102 23:06:57.941215 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10103 23:06:57.944264 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10104 23:06:57.951431 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10105 23:06:57.964126 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10106 23:06:57.977295 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10107 23:06:57.984247 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10108 23:06:57.991721 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10109 23:06:58.004933 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10110 23:06:58.011570 <6>[ 0.000001] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10111 23:06:58.017866 <6>[ 0.009182] Console: colour dummy device 80x25
10112 23:06:58.027803 <6>[ 0.013906] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10113 23:06:58.034622 <6>[ 0.024412] pid_max: default: 32768 minimum: 301
10114 23:06:58.038285 <6>[ 0.029284] LSM: Security Framework initializing
10115 23:06:58.044504 <6>[ 0.034199] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10116 23:06:58.054018 <6>[ 0.041852] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10117 23:06:58.061219 <6>[ 0.051084] cblist_init_generic: Setting adjustable number of callback queues.
10118 23:06:58.067554 <6>[ 0.058572] cblist_init_generic: Setting shift to 3 and lim to 1.
10119 23:06:58.077712 <6>[ 0.064910] cblist_init_generic: Setting adjustable number of callback queues.
10120 23:06:58.084296 <6>[ 0.072383] cblist_init_generic: Setting shift to 3 and lim to 1.
10121 23:06:58.087362 <6>[ 0.078781] rcu: Hierarchical SRCU implementation.
10122 23:06:58.094352 <6>[ 0.083796] rcu: Max phase no-delay instances is 1000.
10123 23:06:58.100845 <6>[ 0.090819] EFI services will not be available.
10124 23:06:58.103970 <6>[ 0.095773] smp: Bringing up secondary CPUs ...
10125 23:06:58.112139 <6>[ 0.100824] Detected VIPT I-cache on CPU1
10126 23:06:58.118517 <6>[ 0.100894] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10127 23:06:58.125562 <6>[ 0.100922] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10128 23:06:58.128685 <6>[ 0.101253] Detected VIPT I-cache on CPU2
10129 23:06:58.138642 <6>[ 0.101299] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10130 23:06:58.145342 <6>[ 0.101314] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10131 23:06:58.148609 <6>[ 0.101569] Detected VIPT I-cache on CPU3
10132 23:06:58.155500 <6>[ 0.101614] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10133 23:06:58.161656 <6>[ 0.101629] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10134 23:06:58.168182 <6>[ 0.101933] CPU features: detected: Spectre-v4
10135 23:06:58.171198 <6>[ 0.101939] CPU features: detected: Spectre-BHB
10136 23:06:58.174770 <6>[ 0.101944] Detected PIPT I-cache on CPU4
10137 23:06:58.181482 <6>[ 0.102000] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10138 23:06:58.191139 <6>[ 0.102016] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10139 23:06:58.194574 <6>[ 0.102309] Detected PIPT I-cache on CPU5
10140 23:06:58.201250 <6>[ 0.102371] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10141 23:06:58.208078 <6>[ 0.102388] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10142 23:06:58.211053 <6>[ 0.102668] Detected PIPT I-cache on CPU6
10143 23:06:58.220638 <6>[ 0.102729] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10144 23:06:58.227290 <6>[ 0.102745] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10145 23:06:58.230755 <6>[ 0.103045] Detected PIPT I-cache on CPU7
10146 23:06:58.237462 <6>[ 0.103108] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10147 23:06:58.243815 <6>[ 0.103125] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10148 23:06:58.247134 <6>[ 0.103172] smp: Brought up 1 node, 8 CPUs
10149 23:06:58.254017 <6>[ 0.244846] SMP: Total of 8 processors activated.
10150 23:06:58.260112 <6>[ 0.249767] CPU features: detected: 32-bit EL0 Support
10151 23:06:58.267192 <6>[ 0.255131] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10152 23:06:58.273519 <6>[ 0.263931] CPU features: detected: Common not Private translations
10153 23:06:58.280215 <6>[ 0.270406] CPU features: detected: CRC32 instructions
10154 23:06:58.286779 <6>[ 0.275758] CPU features: detected: RCpc load-acquire (LDAPR)
10155 23:06:58.289869 <6>[ 0.281755] CPU features: detected: LSE atomic instructions
10156 23:06:58.296475 <6>[ 0.287572] CPU features: detected: Privileged Access Never
10157 23:06:58.303227 <6>[ 0.293351] CPU features: detected: RAS Extension Support
10158 23:06:58.309640 <6>[ 0.298960] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10159 23:06:58.312951 <6>[ 0.306179] CPU: All CPU(s) started at EL2
10160 23:06:58.319351 <6>[ 0.310495] alternatives: applying system-wide alternatives
10161 23:06:58.329014 <6>[ 0.320350] devtmpfs: initialized
10162 23:06:58.344175 <6>[ 0.328705] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10163 23:06:58.350978 <6>[ 0.338670] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10164 23:06:58.357079 <6>[ 0.346920] pinctrl core: initialized pinctrl subsystem
10165 23:06:58.360740 <6>[ 0.353576] DMI not present or invalid.
10166 23:06:58.367580 <6>[ 0.357983] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10167 23:06:58.377031 <6>[ 0.364849] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
10168 23:06:58.383731 <6>[ 0.372298] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10169 23:06:58.393807 <6>[ 0.380393] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10170 23:06:58.396896 <6>[ 0.388552] audit: initializing netlink subsys (disabled)
10171 23:06:58.406760 <5>[ 0.394251] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10172 23:06:58.413474 <6>[ 0.394944] thermal_sys: Registered thermal governor 'step_wise'
10173 23:06:58.419906 <6>[ 0.402221] thermal_sys: Registered thermal governor 'power_allocator'
10174 23:06:58.423485 <6>[ 0.408478] cpuidle: using governor menu
10175 23:06:58.430109 <6>[ 0.419440] NET: Registered PF_QIPCRTR protocol family
10176 23:06:58.436587 <6>[ 0.424925] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10177 23:06:58.443340 <6>[ 0.432028] ASID allocator initialised with 32768 entries
10178 23:06:58.446539 <6>[ 0.438575] Serial: AMBA PL011 UART driver
10179 23:06:58.456098 <4>[ 0.447309] Trying to register duplicate clock ID: 134
10180 23:06:58.512228 <6>[ 0.506844] KASLR enabled
10181 23:06:58.526661 <6>[ 0.514612] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10182 23:06:58.533210 <6>[ 0.521629] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10183 23:06:58.540147 <6>[ 0.528122] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10184 23:06:58.546774 <6>[ 0.535128] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10185 23:06:58.553145 <6>[ 0.541617] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10186 23:06:58.559922 <6>[ 0.548624] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10187 23:06:58.566288 <6>[ 0.555113] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10188 23:06:58.572881 <6>[ 0.562120] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10189 23:06:58.576105 <6>[ 0.569568] ACPI: Interpreter disabled.
10190 23:06:58.585068 <6>[ 0.575973] iommu: Default domain type: Translated
10191 23:06:58.591428 <6>[ 0.581089] iommu: DMA domain TLB invalidation policy: strict mode
10192 23:06:58.595072 <5>[ 0.587749] SCSI subsystem initialized
10193 23:06:58.601181 <6>[ 0.591913] usbcore: registered new interface driver usbfs
10194 23:06:58.608084 <6>[ 0.597648] usbcore: registered new interface driver hub
10195 23:06:58.611101 <6>[ 0.603203] usbcore: registered new device driver usb
10196 23:06:58.618314 <6>[ 0.609298] pps_core: LinuxPPS API ver. 1 registered
10197 23:06:58.628200 <6>[ 0.614493] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10198 23:06:58.631359 <6>[ 0.623846] PTP clock support registered
10199 23:06:58.634573 <6>[ 0.628090] EDAC MC: Ver: 3.0.0
10200 23:06:58.642469 <6>[ 0.633239] FPGA manager framework
10201 23:06:58.648896 <6>[ 0.636918] Advanced Linux Sound Architecture Driver Initialized.
10202 23:06:58.651974 <6>[ 0.643701] vgaarb: loaded
10203 23:06:58.658437 <6>[ 0.646864] clocksource: Switched to clocksource arch_sys_counter
10204 23:06:58.661656 <5>[ 0.653310] VFS: Disk quotas dquot_6.6.0
10205 23:06:58.668442 <6>[ 0.657496] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10206 23:06:58.671574 <6>[ 0.664689] pnp: PnP ACPI: disabled
10207 23:06:58.680234 <6>[ 0.671358] NET: Registered PF_INET protocol family
10208 23:06:58.686766 <6>[ 0.676741] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
10209 23:06:58.699105 <6>[ 0.686768] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
10210 23:06:58.709325 <6>[ 0.695561] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10211 23:06:58.715387 <6>[ 0.703529] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
10212 23:06:58.721912 <6>[ 0.711934] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
10213 23:06:58.732755 <6>[ 0.720573] TCP: Hash tables configured (established 32768 bind 32768)
10214 23:06:58.739393 <6>[ 0.727438] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
10215 23:06:58.745932 <6>[ 0.734460] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
10216 23:06:58.752556 <6>[ 0.741981] NET: Registered PF_UNIX/PF_LOCAL protocol family
10217 23:06:58.759435 <6>[ 0.748131] RPC: Registered named UNIX socket transport module.
10218 23:06:58.762514 <6>[ 0.754286] RPC: Registered udp transport module.
10219 23:06:58.768762 <6>[ 0.759222] RPC: Registered tcp transport module.
10220 23:06:58.775518 <6>[ 0.764155] RPC: Registered tcp NFSv4.1 backchannel transport module.
10221 23:06:58.778968 <6>[ 0.770822] PCI: CLS 0 bytes, default 64
10222 23:06:58.781951 <6>[ 0.775145] Unpacking initramfs...
10223 23:06:58.799536 <6>[ 0.787415] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10224 23:06:58.809480 <6>[ 0.796073] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10225 23:06:58.812861 <6>[ 0.804920] kvm [1]: IPA Size Limit: 40 bits
10226 23:06:58.819692 <6>[ 0.809450] kvm [1]: GICv3: no GICV resource entry
10227 23:06:58.822732 <6>[ 0.814475] kvm [1]: disabling GICv2 emulation
10228 23:06:58.829181 <6>[ 0.819166] kvm [1]: GIC system register CPU interface enabled
10229 23:06:58.832861 <6>[ 0.825333] kvm [1]: vgic interrupt IRQ18
10230 23:06:58.839481 <6>[ 0.829693] kvm [1]: VHE mode initialized successfully
10231 23:06:58.846175 <5>[ 0.836177] Initialise system trusted keyrings
10232 23:06:58.852259 <6>[ 0.840970] workingset: timestamp_bits=42 max_order=20 bucket_order=0
10233 23:06:58.859904 <6>[ 0.851037] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10234 23:06:58.866303 <5>[ 0.857441] NFS: Registering the id_resolver key type
10235 23:06:58.869616 <5>[ 0.862745] Key type id_resolver registered
10236 23:06:58.876247 <5>[ 0.867163] Key type id_legacy registered
10237 23:06:58.882993 <6>[ 0.871442] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10238 23:06:58.889515 <6>[ 0.878365] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10239 23:06:58.896130 <6>[ 0.886072] 9p: Installing v9fs 9p2000 file system support
10240 23:06:58.932876 <5>[ 0.924166] Key type asymmetric registered
10241 23:06:58.936555 <5>[ 0.928499] Asymmetric key parser 'x509' registered
10242 23:06:58.946286 <6>[ 0.933643] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10243 23:06:58.949702 <6>[ 0.941261] io scheduler mq-deadline registered
10244 23:06:58.952739 <6>[ 0.946048] io scheduler kyber registered
10245 23:06:58.971809 <6>[ 0.963067] EINJ: ACPI disabled.
10246 23:06:59.003924 <4>[ 0.988423] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10247 23:06:59.013771 <4>[ 0.999076] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10248 23:06:59.028924 <6>[ 1.020098] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10249 23:06:59.036806 <6>[ 1.028173] printk: console [ttyS0] disabled
10250 23:06:59.065053 <6>[ 1.052820] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10251 23:06:59.071398 <6>[ 1.062315] printk: console [ttyS0] enabled
10252 23:06:59.074793 <6>[ 1.062315] printk: console [ttyS0] enabled
10253 23:06:59.081479 <6>[ 1.071210] printk: bootconsole [mtk8250] disabled
10254 23:06:59.084636 <6>[ 1.071210] printk: bootconsole [mtk8250] disabled
10255 23:06:59.091131 <6>[ 1.082486] SuperH (H)SCI(F) driver initialized
10256 23:06:59.094896 <6>[ 1.087773] msm_serial: driver initialized
10257 23:06:59.109518 <6>[ 1.096786] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10258 23:06:59.118926 <6>[ 1.105337] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10259 23:06:59.125387 <6>[ 1.113879] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10260 23:06:59.135182 <6>[ 1.122507] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10261 23:06:59.145466 <6>[ 1.131217] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10262 23:06:59.152010 <6>[ 1.139930] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10263 23:06:59.162128 <6>[ 1.148470] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10264 23:06:59.168821 <6>[ 1.157271] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10265 23:06:59.178202 <6>[ 1.165815] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10266 23:06:59.190351 <6>[ 1.181511] loop: module loaded
10267 23:06:59.196939 <6>[ 1.187535] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10268 23:06:59.219439 <4>[ 1.210703] mtk-pmic-keys: Failed to locate of_node [id: -1]
10269 23:06:59.226453 <6>[ 1.217662] megasas: 07.719.03.00-rc1
10270 23:06:59.236229 <6>[ 1.227287] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10271 23:06:59.242984 <6>[ 1.234275] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10272 23:06:59.259834 <6>[ 1.250865] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10273 23:06:59.316675 <6>[ 1.300955] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10274 23:06:59.526822 <6>[ 1.518097] Freeing initrd memory: 17380K
10275 23:06:59.537254 <6>[ 1.528047] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10276 23:06:59.547932 <6>[ 1.539077] tun: Universal TUN/TAP device driver, 1.6
10277 23:06:59.551549 <6>[ 1.545134] thunder_xcv, ver 1.0
10278 23:06:59.554548 <6>[ 1.548637] thunder_bgx, ver 1.0
10279 23:06:59.557375 <6>[ 1.552130] nicpf, ver 1.0
10280 23:06:59.568088 <6>[ 1.556138] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10281 23:06:59.571375 <6>[ 1.563613] hns3: Copyright (c) 2017 Huawei Corporation.
10282 23:06:59.578131 <6>[ 1.569199] hclge is initializing
10283 23:06:59.581097 <6>[ 1.572785] e1000: Intel(R) PRO/1000 Network Driver
10284 23:06:59.588216 <6>[ 1.577915] e1000: Copyright (c) 1999-2006 Intel Corporation.
10285 23:06:59.591767 <6>[ 1.583930] e1000e: Intel(R) PRO/1000 Network Driver
10286 23:06:59.598265 <6>[ 1.589145] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10287 23:06:59.604960 <6>[ 1.595331] igb: Intel(R) Gigabit Ethernet Network Driver
10288 23:06:59.611328 <6>[ 1.600981] igb: Copyright (c) 2007-2014 Intel Corporation.
10289 23:06:59.617696 <6>[ 1.606816] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10290 23:06:59.624783 <6>[ 1.613333] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10291 23:06:59.628092 <6>[ 1.619800] sky2: driver version 1.30
10292 23:06:59.634259 <6>[ 1.624777] VFIO - User Level meta-driver version: 0.3
10293 23:06:59.642120 <6>[ 1.633016] usbcore: registered new interface driver usb-storage
10294 23:06:59.648960 <6>[ 1.639461] usbcore: registered new device driver onboard-usb-hub
10295 23:06:59.657552 <6>[ 1.648607] mt6397-rtc mt6359-rtc: registered as rtc0
10296 23:06:59.667484 <6>[ 1.654075] mt6397-rtc mt6359-rtc: setting system clock to 2023-12-01T23:07:00 UTC (1701472020)
10297 23:06:59.670556 <6>[ 1.663636] i2c_dev: i2c /dev entries driver
10298 23:06:59.687644 <6>[ 1.675339] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10299 23:06:59.708282 <6>[ 1.699310] cpu cpu0: EM: created perf domain
10300 23:06:59.711390 <6>[ 1.704216] cpu cpu4: EM: created perf domain
10301 23:06:59.718546 <6>[ 1.709737] sdhci: Secure Digital Host Controller Interface driver
10302 23:06:59.725067 <6>[ 1.716169] sdhci: Copyright(c) Pierre Ossman
10303 23:06:59.731813 <6>[ 1.721076] Synopsys Designware Multimedia Card Interface Driver
10304 23:06:59.738652 <6>[ 1.727661] sdhci-pltfm: SDHCI platform and OF driver helper
10305 23:06:59.742202 <6>[ 1.727788] mmc0: CQHCI version 5.10
10306 23:06:59.748560 <6>[ 1.737542] ledtrig-cpu: registered to indicate activity on CPUs
10307 23:06:59.754869 <6>[ 1.744480] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10308 23:06:59.761895 <6>[ 1.751516] usbcore: registered new interface driver usbhid
10309 23:06:59.765176 <6>[ 1.757337] usbhid: USB HID core driver
10310 23:06:59.771656 <6>[ 1.761518] spi_master spi0: will run message pump with realtime priority
10311 23:06:59.813545 <6>[ 1.798527] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10312 23:06:59.832896 <6>[ 1.814427] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10313 23:06:59.836781 <6>[ 1.828027] mmc0: Command Queue Engine enabled
10314 23:06:59.843699 <6>[ 1.832796] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10315 23:06:59.850511 <6>[ 1.839721] cros-ec-spi spi0.0: Chrome EC device registered
10316 23:06:59.853587 <6>[ 1.840012] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10317 23:06:59.863226 <6>[ 1.854509] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10318 23:06:59.871327 <6>[ 1.862716] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10319 23:06:59.877827 <6>[ 1.868596] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10320 23:06:59.884330 <6>[ 1.874678] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10321 23:06:59.899474 <6>[ 1.887637] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10322 23:06:59.907313 <6>[ 1.898441] NET: Registered PF_PACKET protocol family
10323 23:06:59.910647 <6>[ 1.903871] 9pnet: Installing 9P2000 support
10324 23:06:59.917415 <5>[ 1.908445] Key type dns_resolver registered
10325 23:06:59.920452 <6>[ 1.913489] registered taskstats version 1
10326 23:06:59.927053 <5>[ 1.917875] Loading compiled-in X.509 certificates
10327 23:06:59.957222 <4>[ 1.941755] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10328 23:06:59.967512 <4>[ 1.952574] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10329 23:06:59.973496 <3>[ 1.963116] debugfs: File 'uA_load' in directory '/' already present!
10330 23:06:59.980352 <3>[ 1.969818] debugfs: File 'min_uV' in directory '/' already present!
10331 23:06:59.987116 <3>[ 1.976425] debugfs: File 'max_uV' in directory '/' already present!
10332 23:06:59.993510 <3>[ 1.983031] debugfs: File 'constraint_flags' in directory '/' already present!
10333 23:07:00.004699 <3>[ 1.992626] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10334 23:07:00.013456 <6>[ 2.004989] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10335 23:07:00.020314 <6>[ 2.011762] xhci-mtk 11200000.usb: xHCI Host Controller
10336 23:07:00.027327 <6>[ 2.017276] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10337 23:07:00.037291 <6>[ 2.025120] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10338 23:07:00.043953 <6>[ 2.034537] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10339 23:07:00.050433 <6>[ 2.040605] xhci-mtk 11200000.usb: xHCI Host Controller
10340 23:07:00.057162 <6>[ 2.046079] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10341 23:07:00.063565 <6>[ 2.053723] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10342 23:07:00.070425 <6>[ 2.061347] hub 1-0:1.0: USB hub found
10343 23:07:00.073571 <6>[ 2.065361] hub 1-0:1.0: 1 port detected
10344 23:07:00.079967 <6>[ 2.069624] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10345 23:07:00.087059 <6>[ 2.078285] hub 2-0:1.0: USB hub found
10346 23:07:00.090493 <6>[ 2.082297] hub 2-0:1.0: 1 port detected
10347 23:07:00.099229 <6>[ 2.090283] mtk-msdc 11f70000.mmc: Got CD GPIO
10348 23:07:00.108786 <6>[ 2.096746] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10349 23:07:00.115801 <6>[ 2.104781] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10350 23:07:00.125387 <4>[ 2.112671] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10351 23:07:00.135200 <6>[ 2.122188] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10352 23:07:00.141890 <6>[ 2.130264] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10353 23:07:00.148617 <6>[ 2.138267] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10354 23:07:00.158512 <6>[ 2.146184] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10355 23:07:00.165539 <6>[ 2.154005] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10356 23:07:00.174844 <6>[ 2.161821] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10357 23:07:00.185085 <6>[ 2.172183] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10358 23:07:00.191711 <6>[ 2.180541] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10359 23:07:00.201680 <6>[ 2.188890] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10360 23:07:00.208416 <6>[ 2.197229] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10361 23:07:00.218124 <6>[ 2.205568] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10362 23:07:00.224758 <6>[ 2.213906] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10363 23:07:00.235111 <6>[ 2.222245] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10364 23:07:00.241352 <6>[ 2.230583] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10365 23:07:00.251303 <6>[ 2.238933] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10366 23:07:00.257862 <6>[ 2.247270] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10367 23:07:00.267967 <6>[ 2.255617] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10368 23:07:00.274144 <6>[ 2.263958] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10369 23:07:00.284336 <6>[ 2.272297] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10370 23:07:00.294387 <6>[ 2.280636] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10371 23:07:00.301119 <6>[ 2.288974] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10372 23:07:00.307805 <6>[ 2.297701] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10373 23:07:00.314004 <6>[ 2.304819] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10374 23:07:00.320688 <6>[ 2.311542] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10375 23:07:00.327321 <6>[ 2.318274] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10376 23:07:00.337261 <6>[ 2.325176] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10377 23:07:00.343925 <6>[ 2.332007] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10378 23:07:00.354001 <6>[ 2.341132] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10379 23:07:00.363438 <6>[ 2.350250] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10380 23:07:00.373277 <6>[ 2.359543] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10381 23:07:00.383581 <6>[ 2.369014] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10382 23:07:00.390098 <6>[ 2.378481] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10383 23:07:00.399923 <6>[ 2.387600] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10384 23:07:00.409541 <6>[ 2.397068] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10385 23:07:00.419820 <6>[ 2.406186] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10386 23:07:00.429857 <6>[ 2.415478] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10387 23:07:00.439482 <6>[ 2.425638] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10388 23:07:00.449140 <6>[ 2.437259] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10389 23:07:00.455574 <6>[ 2.446702] Trying to probe devices needed for running init ...
10390 23:07:00.479344 <6>[ 2.467411] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10391 23:07:00.507249 <6>[ 2.498536] hub 2-1:1.0: USB hub found
10392 23:07:00.510465 <6>[ 2.503039] hub 2-1:1.0: 3 ports detected
10393 23:07:00.518580 <6>[ 2.510102] hub 2-1:1.0: USB hub found
10394 23:07:00.521741 <6>[ 2.514472] hub 2-1:1.0: 3 ports detected
10395 23:07:00.631296 <6>[ 2.619165] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10396 23:07:00.785770 <6>[ 2.777152] hub 1-1:1.0: USB hub found
10397 23:07:00.789113 <6>[ 2.781651] hub 1-1:1.0: 4 ports detected
10398 23:07:00.799842 <6>[ 2.790938] hub 1-1:1.0: USB hub found
10399 23:07:00.802878 <6>[ 2.795418] hub 1-1:1.0: 4 ports detected
10400 23:07:00.871209 <6>[ 2.859328] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10401 23:07:01.123260 <6>[ 3.111151] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10402 23:07:01.255551 <6>[ 3.246628] hub 1-1.4:1.0: USB hub found
10403 23:07:01.258297 <6>[ 3.251281] hub 1-1.4:1.0: 2 ports detected
10404 23:07:01.267399 <6>[ 3.258627] hub 1-1.4:1.0: USB hub found
10405 23:07:01.270533 <6>[ 3.263223] hub 1-1.4:1.0: 2 ports detected
10406 23:07:01.566865 <6>[ 3.555146] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10407 23:07:01.758924 <6>[ 3.747146] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10408 23:07:12.740667 <6>[ 14.736176] ALSA device list:
10409 23:07:12.746533 <6>[ 14.739466] No soundcards found.
10410 23:07:12.754534 <6>[ 14.747245] Freeing unused kernel memory: 8448K
10411 23:07:12.757594 <6>[ 14.752227] Run /init as init process
10412 23:07:12.768819 Loading, please wait...
10413 23:07:12.788553 Starting version 247.3-7+deb11u2
10414 23:07:12.960438 <6>[ 14.950051] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10415 23:07:12.983603 <6>[ 14.976159] remoteproc remoteproc0: scp is available
10416 23:07:12.990266 <6>[ 14.981733] remoteproc remoteproc0: powering up scp
10417 23:07:12.996558 <6>[ 14.986929] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10418 23:07:13.003655 <6>[ 14.996634] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10419 23:07:13.010379 <6>[ 14.996966] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10420 23:07:13.020307 <3>[ 15.000718] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10421 23:07:13.027188 <3>[ 15.000742] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10422 23:07:13.037037 <3>[ 15.000752] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10423 23:07:13.043583 <3>[ 15.000881] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10424 23:07:13.053426 <3>[ 15.000890] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10425 23:07:13.060401 <3>[ 15.000897] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10426 23:07:13.069972 <3>[ 15.000907] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10427 23:07:13.076946 <3>[ 15.000915] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10428 23:07:13.086458 <3>[ 15.000965] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10429 23:07:13.093203 <3>[ 15.001021] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10430 23:07:13.099727 <3>[ 15.001029] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10431 23:07:13.109379 <3>[ 15.001037] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10432 23:07:13.116487 <3>[ 15.001099] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10433 23:07:13.126230 <3>[ 15.001108] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10434 23:07:13.132795 <3>[ 15.001120] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10435 23:07:13.142642 <3>[ 15.001132] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10436 23:07:13.148887 <3>[ 15.001139] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10437 23:07:13.156166 <3>[ 15.001188] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10438 23:07:13.162956 <6>[ 15.050795] mc: Linux media interface: v0.10
10439 23:07:13.170062 <6>[ 15.058399] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10440 23:07:13.180125 <4>[ 15.070071] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10441 23:07:13.186103 <6>[ 15.070379] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10442 23:07:13.196424 <6>[ 15.074542] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10443 23:07:13.199588 <6>[ 15.107848] videodev: Linux video capture interface: v2.00
10444 23:07:13.206104 <6>[ 15.108868] usbcore: registered new interface driver r8152
10445 23:07:13.212687 <4>[ 15.115343] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10446 23:07:13.222954 <4>[ 15.123645] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10447 23:07:13.226424 <4>[ 15.123645] Fallback method does not support PEC.
10448 23:07:13.233124 <6>[ 15.128131] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10449 23:07:13.242969 <6>[ 15.131161] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10450 23:07:13.252807 <3>[ 15.157776] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10451 23:07:13.259267 <6>[ 15.160008] remoteproc remoteproc0: remote processor scp is now up
10452 23:07:13.269800 <6>[ 15.168849] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10453 23:07:13.275813 <6>[ 15.177304] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10454 23:07:13.285980 <6>[ 15.184359] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10455 23:07:13.292416 <6>[ 15.193253] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10456 23:07:13.299098 <6>[ 15.205979] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10457 23:07:13.309078 <6>[ 15.212242] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10458 23:07:13.315686 <3>[ 15.219728] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10459 23:07:13.322435 <6>[ 15.225028] pci_bus 0000:00: root bus resource [bus 00-ff]
10460 23:07:13.332115 <4>[ 15.233822] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10461 23:07:13.338724 <6>[ 15.240576] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10462 23:07:13.348482 <6>[ 15.240583] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10463 23:07:13.355040 <4>[ 15.249403] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10464 23:07:13.361907 <6>[ 15.255941] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10465 23:07:13.371928 <6>[ 15.269591] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10466 23:07:13.378327 <6>[ 15.274161] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10467 23:07:13.384899 <6>[ 15.315021] r8152 2-1.3:1.0 eth0: v1.12.13
10468 23:07:13.388220 <6>[ 15.315649] usbcore: registered new interface driver cdc_ether
10469 23:07:13.394844 <6>[ 15.320513] pci 0000:00:00.0: supports D1 D2
10470 23:07:13.401402 <6>[ 15.330014] usbcore: registered new interface driver r8153_ecm
10471 23:07:13.408115 <6>[ 15.336210] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10472 23:07:13.414728 <6>[ 15.337081] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10473 23:07:13.418097 <6>[ 15.337144] Bluetooth: Core ver 2.22
10474 23:07:13.424685 <6>[ 15.337268] NET: Registered PF_BLUETOOTH protocol family
10475 23:07:13.431150 <6>[ 15.337270] Bluetooth: HCI device and connection manager initialized
10476 23:07:13.437930 <6>[ 15.337308] Bluetooth: HCI socket layer initialized
10477 23:07:13.441247 <6>[ 15.337317] Bluetooth: L2CAP socket layer initialized
10478 23:07:13.447422 <6>[ 15.337333] Bluetooth: SCO socket layer initialized
10479 23:07:13.454324 <6>[ 15.337769] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10480 23:07:13.467401 <6>[ 15.338831] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10481 23:07:13.473911 <6>[ 15.338953] usbcore: registered new interface driver uvcvideo
10482 23:07:13.477464 <6>[ 15.352455] r8152 2-1.3:1.0 enx00e04c6803bd: renamed from eth0
10483 23:07:13.484097 <6>[ 15.354339] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10484 23:07:13.490454 <6>[ 15.378092] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10485 23:07:13.500766 <6>[ 15.381607] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10486 23:07:13.504148 <6>[ 15.392613] usbcore: registered new interface driver btusb
10487 23:07:13.513869 <4>[ 15.393344] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10488 23:07:13.520766 <3>[ 15.393354] Bluetooth: hci0: Failed to load firmware file (-2)
10489 23:07:13.527202 <3>[ 15.393358] Bluetooth: hci0: Failed to set up firmware (-2)
10490 23:07:13.536912 <4>[ 15.393362] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10491 23:07:13.543503 <6>[ 15.398274] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10492 23:07:13.553066 <6>[ 15.542674] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10493 23:07:13.556779 <6>[ 15.550256] pci 0000:01:00.0: supports D1 D2
10494 23:07:13.563543 <6>[ 15.554776] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10495 23:07:13.581378 <6>[ 15.571161] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10496 23:07:13.588105 <6>[ 15.578057] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10497 23:07:13.594727 <6>[ 15.586135] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10498 23:07:13.604473 <6>[ 15.594132] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10499 23:07:13.611492 <6>[ 15.602133] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10500 23:07:13.620923 <6>[ 15.610132] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10501 23:07:13.624575 <6>[ 15.618132] pci 0000:00:00.0: PCI bridge to [bus 01]
10502 23:07:13.634606 <6>[ 15.623348] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10503 23:07:13.641167 <6>[ 15.631474] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10504 23:07:13.647423 <6>[ 15.638286] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10505 23:07:13.653969 <6>[ 15.644863] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10506 23:07:13.677760 <5>[ 15.667414] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10507 23:07:13.699065 <5>[ 15.688622] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10508 23:07:13.705542 <4>[ 15.695537] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10509 23:07:13.712210 <6>[ 15.704430] cfg80211: failed to load regulatory.db
10510 23:07:13.767303 <6>[ 15.756879] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10511 23:07:13.773702 <6>[ 15.764508] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10512 23:07:13.798238 <6>[ 15.791347] mt7921e 0000:01:00.0: ASIC revision: 79610010
10513 23:07:13.904966 <4>[ 15.891430] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10514 23:07:13.931915 Begin: Loading essential drivers ... done.
10515 23:07:13.934992 Begin: Running /scripts/init-premount ... done.
10516 23:07:13.941749 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10517 23:07:13.951247 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10518 23:07:13.954467 Device /sys/class/net/enx00e04c6803bd found
10519 23:07:13.954938 done.
10520 23:07:14.023962 <4>[ 16.010230] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10521 23:07:14.049308 IP-Config: enx00e04c6803bd hardware address 00:e0:4c:68:03:bd mtu 1500 DHCP
10522 23:07:14.138677 <4>[ 16.124693] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10523 23:07:14.255965 <4>[ 16.242499] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10524 23:07:14.375800 <4>[ 16.362327] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10525 23:07:14.496218 <4>[ 16.482262] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10526 23:07:14.615869 <4>[ 16.602310] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10527 23:07:14.735549 <4>[ 16.722250] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10528 23:07:14.855732 <4>[ 16.842315] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10529 23:07:14.905936 <6>[ 16.898806] r8152 2-1.3:1.0 enx00e04c6803bd: carrier on
10530 23:07:14.975482 <4>[ 16.962254] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10531 23:07:15.087118 <3>[ 17.080151] mt7921e 0000:01:00.0: hardware init failed
10532 23:07:15.160932 IP-Config: no response after 2 secs - giving up
10533 23:07:15.196999 IP-Config: enx00e04c6803bd hardware address 00:e0:4c:68:03:bd mtu 1500 DHCP
10534 23:07:15.200577 IP-Config: enx00e04c6803bd complete (dhcp from 192.168.201.1):
10535 23:07:15.207303 address: 192.168.201.16 broadcast: 192.168.201.255 netmask: 255.255.255.0
10536 23:07:15.216973 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10537 23:07:15.223554 host : mt8192-asurada-spherion-r0-cbg-4
10538 23:07:15.230176 domain : lava-rack
10539 23:07:15.233331 rootserver: 192.168.201.1 rootpath:
10540 23:07:15.233782 filename :
10541 23:07:15.304455 done.
10542 23:07:15.311235 Begin: Running /scripts/nfs-bottom ... done.
10543 23:07:15.331845 Begin: Running /scripts/init-bottom ... done.
10544 23:07:16.513103 <6>[ 18.506430] NET: Registered PF_INET6 protocol family
10545 23:07:16.520495 <6>[ 18.513521] Segment Routing with IPv6
10546 23:07:16.523473 <6>[ 18.517500] In-situ OAM (IOAM) with IPv6
10547 23:07:16.649307 <30>[ 18.622536] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10548 23:07:16.652562 <30>[ 18.646987] systemd[1]: Detected architecture arm64.
10549 23:07:16.675166
10550 23:07:16.678300 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10551 23:07:16.678849
10552 23:07:16.697313 <30>[ 18.690063] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10553 23:07:17.592287 <30>[ 19.582438] systemd[1]: Queued start job for default target Graphical Interface.
10554 23:07:17.628198 <30>[ 19.621470] systemd[1]: Created slice system-getty.slice.
10555 23:07:17.634815 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10556 23:07:17.651519 <30>[ 19.644471] systemd[1]: Created slice system-modprobe.slice.
10557 23:07:17.657468 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10558 23:07:17.676128 <30>[ 19.669189] systemd[1]: Created slice system-serial\x2dgetty.slice.
10559 23:07:17.686257 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10560 23:07:17.698997 <30>[ 19.692207] systemd[1]: Created slice User and Session Slice.
10561 23:07:17.705765 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10562 23:07:17.726070 <30>[ 19.715889] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10563 23:07:17.735482 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10564 23:07:17.753983 <30>[ 19.743916] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10565 23:07:17.759861 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10566 23:07:17.784076 <30>[ 19.771317] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10567 23:07:17.791013 <30>[ 19.783480] systemd[1]: Reached target Local Encrypted Volumes.
10568 23:07:17.797488 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10569 23:07:17.813911 <30>[ 19.807714] systemd[1]: Reached target Paths.
10570 23:07:17.817614 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10571 23:07:17.833998 <30>[ 19.827142] systemd[1]: Reached target Remote File Systems.
10572 23:07:17.840309 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10573 23:07:17.858463 <30>[ 19.851500] systemd[1]: Reached target Slices.
10574 23:07:17.864543 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10575 23:07:17.877645 <30>[ 19.871160] systemd[1]: Reached target Swap.
10576 23:07:17.880778 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10577 23:07:17.901781 <30>[ 19.891669] systemd[1]: Listening on initctl Compatibility Named Pipe.
10578 23:07:17.907969 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10579 23:07:17.914537 <30>[ 19.907841] systemd[1]: Listening on Journal Audit Socket.
10580 23:07:17.921178 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10581 23:07:17.939366 <30>[ 19.932679] systemd[1]: Listening on Journal Socket (/dev/log).
10582 23:07:17.945810 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10583 23:07:17.962663 <30>[ 19.955785] systemd[1]: Listening on Journal Socket.
10584 23:07:17.969183 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10585 23:07:17.986399 <30>[ 19.976706] systemd[1]: Listening on Network Service Netlink Socket.
10586 23:07:17.992965 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10587 23:07:18.009044 <30>[ 20.002402] systemd[1]: Listening on udev Control Socket.
10588 23:07:18.015435 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10589 23:07:18.030238 <30>[ 20.023587] systemd[1]: Listening on udev Kernel Socket.
10590 23:07:18.036763 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10591 23:07:18.085753 <30>[ 20.079298] systemd[1]: Mounting Huge Pages File System...
10592 23:07:18.092113 Mounting [0;1;39mHuge Pages File System[0m...
10593 23:07:18.114002 <30>[ 20.107538] systemd[1]: Mounting POSIX Message Queue File System...
10594 23:07:18.120862 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10595 23:07:18.142077 <30>[ 20.135554] systemd[1]: Mounting Kernel Debug File System...
10596 23:07:18.148444 Mounting [0;1;39mKernel Debug File System[0m...
10597 23:07:18.169329 <30>[ 20.159714] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10598 23:07:18.190768 <30>[ 20.180603] systemd[1]: Starting Create list of static device nodes for the current kernel...
10599 23:07:18.197118 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10600 23:07:18.216409 <30>[ 20.210101] systemd[1]: Starting Load Kernel Module configfs...
10601 23:07:18.223385 Starting [0;1;39mLoad Kernel Module configfs[0m...
10602 23:07:18.246004 <30>[ 20.239434] systemd[1]: Starting Load Kernel Module drm...
10603 23:07:18.252470 Starting [0;1;39mLoad Kernel Module drm[0m...
10604 23:07:18.298225 <30>[ 20.291873] systemd[1]: Starting Load Kernel Module fuse...
10605 23:07:18.304824 Starting [0;1;39mLoad Kernel Module fuse[0m...
10606 23:07:18.326448 <30>[ 20.316610] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10607 23:07:18.342030 <30>[ 20.335731] systemd[1]: Starting Journal Service...
10608 23:07:18.345550 Starting [0;1;39mJournal Service[0m...
10609 23:07:18.354393 <6>[ 20.347495] fuse: init (API version 7.37)
10610 23:07:18.394683 <30>[ 20.388127] systemd[1]: Starting Load Kernel Modules...
10611 23:07:18.401054 Starting [0;1;39mLoad Kernel Modules[0m...
10612 23:07:18.424988 <30>[ 20.415280] systemd[1]: Starting Remount Root and Kernel File Systems...
10613 23:07:18.431595 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10614 23:07:18.449040 <30>[ 20.442875] systemd[1]: Starting Coldplug All udev Devices...
10615 23:07:18.455710 Starting [0;1;39mColdplug All udev Devices[0m...
10616 23:07:18.473494 <30>[ 20.467323] systemd[1]: Mounted Huge Pages File System.
10617 23:07:18.480371 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10618 23:07:18.490806 <3>[ 20.479232] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10619 23:07:18.496897 <30>[ 20.488826] systemd[1]: Mounted POSIX Message Queue File System.
10620 23:07:18.503800 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10621 23:07:18.517697 <30>[ 20.511644] systemd[1]: Mounted Kernel Debug File System.
10622 23:07:18.527520 <3>[ 20.512175] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10623 23:07:18.534251 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10624 23:07:18.553769 <30>[ 20.544219] systemd[1]: Finished Create list of static device nodes for the current kernel.
10625 23:07:18.564070 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10626 23:07:18.570713 <3>[ 20.561109] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10627 23:07:18.578941 <30>[ 20.572785] systemd[1]: modprobe@configfs.service: Succeeded.
10628 23:07:18.586075 <30>[ 20.579578] systemd[1]: Finished Load Kernel Module configfs.
10629 23:07:18.600128 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configf<3>[ 20.590671] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10630 23:07:18.603766 s[0m.
10631 23:07:18.624227 <30>[ 20.616876] systemd[1]: modprobe@drm.service: Succeeded.
10632 23:07:18.634091 <3>[ 20.623127] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10633 23:07:18.640666 <30>[ 20.623259] systemd[1]: Finished Load Kernel Module drm.
10634 23:07:18.644014 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10635 23:07:18.663860 <3>[ 20.653861] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10636 23:07:18.671353 <30>[ 20.664651] systemd[1]: modprobe@fuse.service: Succeeded.
10637 23:07:18.678494 <30>[ 20.671912] systemd[1]: Finished Load Kernel Module fuse.
10638 23:07:18.685053 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10639 23:07:18.696806 <3>[ 20.686964] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10640 23:07:18.704856 <30>[ 20.698074] systemd[1]: Finished Load Kernel Modules.
10641 23:07:18.711436 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10642 23:07:18.729630 <3>[ 20.719702] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10643 23:07:18.736355 <30>[ 20.719855] systemd[1]: Finished Remount Root and Kernel File Systems.
10644 23:07:18.742995 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10645 23:07:18.761956 <3>[ 20.752056] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10646 23:07:18.793818 <3>[ 20.784236] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10647 23:07:18.805574 <30>[ 20.799312] systemd[1]: Mounting FUSE Control File System...
10648 23:07:18.812399 Mounting [0;1;39mFUSE Control File System[0m...
10649 23:07:18.832243 <30>[ 20.825870] systemd[1]: Mounting Kernel Configuration File System...
10650 23:07:18.839126 Mounting [0;1;39mKernel Configuration File System[0m...
10651 23:07:18.866162 <30>[ 20.856186] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10652 23:07:18.875682 <30>[ 20.865373] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10653 23:07:18.907212 <30>[ 20.900327] systemd[1]: Starting Load/Save Random Seed...
10654 23:07:18.914079 Starting [0;1;39mLoad/Save Random Seed[0m...
10655 23:07:18.930270 <30>[ 20.923657] systemd[1]: Starting Apply Kernel Variables...
10656 23:07:18.936570 Starting [0;1;39mApply Kernel Variables[0m...
10657 23:07:18.954663 <30>[ 20.948299] systemd[1]: Starting Create System Users...
10658 23:07:18.971343 <4>[ 20.948590] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10659 23:07:18.978131 <3>[ 20.969626] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10660 23:07:18.984441 Starting [0;1;39mCreate System Users[0m...
10661 23:07:18.999735 <30>[ 20.992949] systemd[1]: Started Journal Service.
10662 23:07:19.003263 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10663 23:07:19.033086 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10664 23:07:19.045583 See 'systemctl status systemd-udev-trigger.service' for details.
10665 23:07:19.065951 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10666 23:07:19.081785 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10667 23:07:19.099394 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10668 23:07:19.119572 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10669 23:07:19.135518 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10670 23:07:19.182243 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10671 23:07:19.205145 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10672 23:07:19.241110 <46>[ 21.231578] systemd-journald[301]: Received client request to flush runtime journal.
10673 23:07:20.366093 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10674 23:07:20.377724 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10675 23:07:20.393630 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10676 23:07:20.445382 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10677 23:07:20.657521 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10678 23:07:20.695309 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10679 23:07:20.812879 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10680 23:07:20.875415 Starting [0;1;39mNetwork Service[0m...
10681 23:07:20.908595 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10682 23:07:20.934105 Starting [0;1;39mNetwork Time Synchronization[0m...
10683 23:07:20.958828 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10684 23:07:21.084299 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10685 23:07:21.160435 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10686 23:07:21.210072 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10687 23:07:21.226701 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10688 23:07:21.514953 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10689 23:07:21.532520 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10690 23:07:21.582151 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10691 23:07:21.613918 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10692 23:07:21.657122 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10693 23:07:21.673766 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10694 23:07:21.689738 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10695 23:07:21.706149 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10696 23:07:21.724234 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10697 23:07:21.736749 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10698 23:07:21.752817 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10699 23:07:21.777188 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10700 23:07:22.326812 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10701 23:07:22.507377 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10702 23:07:22.840559 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10703 23:07:22.857128 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10704 23:07:22.878531 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10705 23:07:22.893029 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10706 23:07:22.909383 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10707 23:07:22.950484 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10708 23:07:23.003678 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10709 23:07:23.062395 Starting [0;1;39mUser Login Management[0m...
10710 23:07:23.173813 Starting [0;1;39mNetwork Name Resolution[0m...
10711 23:07:23.303942 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10712 23:07:23.367108 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10713 23:07:24.027340 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10714 23:07:24.046807 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10715 23:07:24.069127 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10716 23:07:24.115417 Starting [0;1;39mPermit User Sessions[0m...
10717 23:07:24.152978 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10718 23:07:24.214789 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10719 23:07:24.262781 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10720 23:07:24.278505 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10721 23:07:24.293939 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10722 23:07:24.310122 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10723 23:07:24.361914 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10724 23:07:24.416570 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10725 23:07:24.485398
10726 23:07:24.485560
10727 23:07:24.488772 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10728 23:07:24.488865
10729 23:07:24.491662 debian-bullseye-arm64 login: root (automatic login)
10730 23:07:24.491776
10731 23:07:24.491855
10732 23:07:24.843735 Linux debian-bullseye-arm64 6.1.64-cip10 #1 SMP PREEMPT Fri Dec 1 22:47:09 UTC 2023 aarch64
10733 23:07:24.843874
10734 23:07:24.850049 The programs included with the Debian GNU/Linux system are free software;
10735 23:07:24.856639 the exact distribution terms for each program are described in the
10736 23:07:24.859849 individual files in /usr/share/doc/*/copyright.
10737 23:07:24.859929
10738 23:07:24.866491 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10739 23:07:24.869735 permitted by applicable law.
10740 23:07:25.767097 Matched prompt #10: / #
10742 23:07:25.767393 Setting prompt string to ['/ #']
10743 23:07:25.767493 end: 2.2.5.1 login-action (duration 00:00:28) [common]
10745 23:07:25.767708 end: 2.2.5 auto-login-action (duration 00:00:28) [common]
10746 23:07:25.767803 start: 2.2.6 expect-shell-connection (timeout 00:03:37) [common]
10747 23:07:25.767876 Setting prompt string to ['/ #']
10748 23:07:25.767940 Forcing a shell prompt, looking for ['/ #']
10750 23:07:25.818258 / #
10751 23:07:25.818714 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10752 23:07:25.819027 Waiting using forced prompt support (timeout 00:02:30)
10753 23:07:25.824221
10754 23:07:25.825341 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10755 23:07:25.825887 start: 2.2.7 export-device-env (timeout 00:03:37) [common]
10757 23:07:25.927217 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12154433/extract-nfsrootfs-3jw6zot7'
10758 23:07:25.933828 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12154433/extract-nfsrootfs-3jw6zot7'
10760 23:07:26.035284 / # export NFS_SERVER_IP='192.168.201.1'
10761 23:07:26.040642 export NFS_SERVER_IP='192.168.201.1'
10762 23:07:26.041200 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10763 23:07:26.041463 end: 2.2 depthcharge-retry (duration 00:01:23) [common]
10764 23:07:26.041677 end: 2 depthcharge-action (duration 00:01:23) [common]
10765 23:07:26.041882 start: 3 lava-test-retry (timeout 00:07:55) [common]
10766 23:07:26.042081 start: 3.1 lava-test-shell (timeout 00:07:55) [common]
10767 23:07:26.042250 Using namespace: common
10769 23:07:26.143135 / # #
10770 23:07:26.143832 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10771 23:07:26.149480 #
10772 23:07:26.150516 Using /lava-12154433
10774 23:07:26.251931 / # export SHELL=/bin/bash
10775 23:07:26.258731 export SHELL=/bin/bash
10777 23:07:26.360503 / # . /lava-12154433/environment
10778 23:07:26.366852 . /lava-12154433/environment
10780 23:07:26.475043 / # /lava-12154433/bin/lava-test-runner /lava-12154433/0
10781 23:07:26.475740 Test shell timeout: 10s (minimum of the action and connection timeout)
10782 23:07:26.481396 /lava-12154433/bin/lava-test-runner /lava-12154433/0
10783 23:07:26.773699 + export TESTRUN_ID=0_timesync-off
10784 23:07:26.776696 + TESTRUN_ID=0_timesync-off
10785 23:07:26.779747 + cd /lava-12154433/0/tests/0_timesync-off
10786 23:07:26.783406 ++ cat uuid
10787 23:07:26.787132 + UUID=12154433_1.6.2.3.1
10788 23:07:26.787238 + set +x
10789 23:07:26.793890 <LAVA_SIGNAL_STARTRUN 0_timesync-off 12154433_1.6.2.3.1>
10790 23:07:26.794198 Received signal: <STARTRUN> 0_timesync-off 12154433_1.6.2.3.1
10791 23:07:26.794307 Starting test lava.0_timesync-off (12154433_1.6.2.3.1)
10792 23:07:26.794431 Skipping test definition patterns.
10793 23:07:26.796893 + systemctl stop systemd-timesyncd
10794 23:07:26.847881 + set +x
10795 23:07:26.851286 <LAVA_SIGNAL_ENDRUN 0_timesync-off 12154433_1.6.2.3.1>
10796 23:07:26.851574 Received signal: <ENDRUN> 0_timesync-off 12154433_1.6.2.3.1
10797 23:07:26.851689 Ending use of test pattern.
10798 23:07:26.851771 Ending test lava.0_timesync-off (12154433_1.6.2.3.1), duration 0.06
10800 23:07:26.918872 + export TESTRUN_ID=1_kselftest-tpm2
10801 23:07:26.922468 + TESTRUN_ID=1_kselftest-tpm2
10802 23:07:26.928709 + cd /lava-12154433/0/tests/1_kselftest-tpm2
10803 23:07:26.928890 ++ cat uuid
10804 23:07:26.931996 + UUID=12154433_1.6.2.3.5
10805 23:07:26.932198 + set +x
10806 23:07:26.935393 <LAVA_SIGNAL_STARTRUN 1_kselftest-tpm2 12154433_1.6.2.3.5>
10807 23:07:26.935845 Received signal: <STARTRUN> 1_kselftest-tpm2 12154433_1.6.2.3.5
10808 23:07:26.936045 Starting test lava.1_kselftest-tpm2 (12154433_1.6.2.3.5)
10809 23:07:26.936265 Skipping test definition patterns.
10810 23:07:26.938861 + cd ./automated/linux/kselftest/
10811 23:07:26.965354 + ./kselftest.sh -c tpm2 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.64-cip10/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
10812 23:07:26.998365 INFO: install_deps skipped
10813 23:07:27.108481 --2023-12-01 23:07:27-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.64-cip10/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
10814 23:07:27.128700 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
10815 23:07:27.263125 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
10816 23:07:27.396678 HTTP request sent, awaiting response... 200 OK
10817 23:07:27.399993 Length: 2967588 (2.8M) [application/octet-stream]
10818 23:07:27.403288 Saving to: 'kselftest.tar.xz'
10819 23:07:27.403852
10820 23:07:27.404211
10821 23:07:27.663512 kselftest.tar.xz 0%[ ] 0 --.-KB/s
10822 23:07:27.930056 kselftest.tar.xz 1%[ ] 49.22K 185KB/s
10823 23:07:28.245767 kselftest.tar.xz 7%[> ] 218.91K 411KB/s
10824 23:07:28.519914 kselftest.tar.xz 28%[====> ] 822.71K 971KB/s
10825 23:07:28.652381 kselftest.tar.xz 67%[============> ] 1.91M 1.70MB/s
10826 23:07:28.658366 kselftest.tar.xz 100%[===================>] 2.83M 2.26MB/s in 1.3s
10827 23:07:28.658449
10828 23:07:28.916932 2023-12-01 23:07:28 (2.26 MB/s) - 'kselftest.tar.xz' saved [2967588/2967588]
10829 23:07:28.917451
10830 23:07:35.567602 skiplist:
10831 23:07:35.570944 ========================================
10832 23:07:35.574205 ========================================
10833 23:07:35.625458 tpm2:test_smoke.sh
10834 23:07:35.628853 tpm2:test_space.sh
10835 23:07:35.646319 ============== Tests to run ===============
10836 23:07:35.649798 tpm2:test_smoke.sh
10837 23:07:35.650233 tpm2:test_space.sh
10838 23:07:35.652900 ===========End Tests to run ===============
10839 23:07:35.656754 shardfile-tpm2 pass
10840 23:07:35.773323 <12>[ 37.768943] kselftest: Running tests in tpm2
10841 23:07:35.784142 TAP version 13
10842 23:07:35.798604 1..2
10843 23:07:35.832560 # selftests: tpm2: test_smoke.sh
10844 23:07:37.348878 # test_read_partial_overwrite (tpm2_tests.SmokeTest) ... ERROR
10845 23:07:37.352274 # test_read_partial_resp (tpm2_tests.SmokeTest) ... ERROR
10846 23:07:37.359168 # Exception ignored in: <function Client.__del__ at 0xffffbafa7d30>
10847 23:07:37.362360 # Traceback (most recent call last):
10848 23:07:37.372541 # File "/lava-12154433/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
10849 23:07:37.375424 # if self.tpm:
10850 23:07:37.379131 # AttributeError: 'Client' object has no attribute 'tpm'
10851 23:07:37.385538 # test_seal_with_auth (tpm2_tests.SmokeTest) ... ERROR
10852 23:07:37.388687 # Exception ignored in: <function Client.__del__ at 0xffffbafa7d30>
10853 23:07:37.391991 # Traceback (most recent call last):
10854 23:07:37.402129 # File "/lava-12154433/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
10855 23:07:37.405077 # if self.tpm:
10856 23:07:37.408681 # AttributeError: 'Client' object has no attribute 'tpm'
10857 23:07:37.414986 # test_seal_with_policy (tpm2_tests.SmokeTest) ... ERROR
10858 23:07:37.421832 # Exception ignored in: <function Client.__del__ at 0xffffbafa7d30>
10859 23:07:37.424894 # Traceback (most recent call last):
10860 23:07:37.434954 # File "/lava-12154433/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
10861 23:07:37.435451 # if self.tpm:
10862 23:07:37.441322 # AttributeError: 'Client' object has no attribute 'tpm'
10863 23:07:37.444706 # test_seal_with_too_long_auth (tpm2_tests.SmokeTest) ... ERROR
10864 23:07:37.451303 # Exception ignored in: <function Client.__del__ at 0xffffbafa7d30>
10865 23:07:37.454586 # Traceback (most recent call last):
10866 23:07:37.464315 # File "/lava-12154433/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
10867 23:07:37.467723 # if self.tpm:
10868 23:07:37.471125 # AttributeError: 'Client' object has no attribute 'tpm'
10869 23:07:37.477791 # test_send_two_cmds (tpm2_tests.SmokeTest) ... ERROR
10870 23:07:37.484279 # Exception ignored in: <function Client.__del__ at 0xffffbafa7d30>
10871 23:07:37.487414 # Traceback (most recent call last):
10872 23:07:37.497428 # File "/lava-12154433/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
10873 23:07:37.497933 # if self.tpm:
10874 23:07:37.503970 # AttributeError: 'Client' object has no attribute 'tpm'
10875 23:07:37.507647 # test_too_short_cmd (tpm2_tests.SmokeTest) ... ERROR
10876 23:07:37.514249 # Exception ignored in: <function Client.__del__ at 0xffffbafa7d30>
10877 23:07:37.517062 # Traceback (most recent call last):
10878 23:07:37.527321 # File "/lava-12154433/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
10879 23:07:37.527913 # if self.tpm:
10880 23:07:37.533777 # AttributeError: 'Client' object has no attribute 'tpm'
10881 23:07:37.540575 # test_unseal_with_wrong_auth (tpm2_tests.SmokeTest) ... ERROR
10882 23:07:37.543644 # Exception ignored in: <function Client.__del__ at 0xffffbafa7d30>
10883 23:07:37.546865 # Traceback (most recent call last):
10884 23:07:37.557167 # File "/lava-12154433/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
10885 23:07:37.560367 # if self.tpm:
10886 23:07:37.563860 # AttributeError: 'Client' object has no attribute 'tpm'
10887 23:07:37.570277 # test_unseal_with_wrong_policy (tpm2_tests.SmokeTest) ... ERROR
10888 23:07:37.576894 # Exception ignored in: <function Client.__del__ at 0xffffbafa7d30>
10889 23:07:37.580234 # Traceback (most recent call last):
10890 23:07:37.590294 # File "/lava-12154433/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
10891 23:07:37.590840 # if self.tpm:
10892 23:07:37.596709 # AttributeError: 'Client' object has no attribute 'tpm'
10893 23:07:37.597175 #
10894 23:07:37.603606 # ======================================================================
10895 23:07:37.609934 # ERROR: test_read_partial_overwrite (tpm2_tests.SmokeTest)
10896 23:07:37.613485 # ----------------------------------------------------------------------
10897 23:07:37.616384 # Traceback (most recent call last):
10898 23:07:37.630438 # File "/lava-12154433/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 16, in setUp
10899 23:07:37.633770 # self.root_key = self.client.create_root_key()
10900 23:07:37.643976 # File "/lava-12154433/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
10901 23:07:37.650421 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
10902 23:07:37.657344 # File "/lava-12154433/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
10903 23:07:37.660933 # raise ProtocolError(cc, rc)
10904 23:07:37.667661 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
10905 23:07:37.668210 #
10906 23:07:37.674010 # ======================================================================
10907 23:07:37.680488 # ERROR: test_read_partial_resp (tpm2_tests.SmokeTest)
10908 23:07:37.687024 # ----------------------------------------------------------------------
10909 23:07:37.690537 # Traceback (most recent call last):
10910 23:07:37.700206 # File "/lava-12154433/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
10911 23:07:37.703775 # self.client = tpm2.Client()
10912 23:07:37.713318 # File "/lava-12154433/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
10913 23:07:37.716696 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
10914 23:07:37.723627 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
10915 23:07:37.724089 #
10916 23:07:37.730000 # ======================================================================
10917 23:07:37.733128 # ERROR: test_seal_with_auth (tpm2_tests.SmokeTest)
10918 23:07:37.740236 # ----------------------------------------------------------------------
10919 23:07:37.743252 # Traceback (most recent call last):
10920 23:07:37.753151 # File "/lava-12154433/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
10921 23:07:37.757000 # self.client = tpm2.Client()
10922 23:07:37.766275 # File "/lava-12154433/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
10923 23:07:37.769817 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
10924 23:07:37.776465 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
10925 23:07:37.776922 #
10926 23:07:37.783040 # ======================================================================
10927 23:07:37.786433 # ERROR: test_seal_with_policy (tpm2_tests.SmokeTest)
10928 23:07:37.792892 # ----------------------------------------------------------------------
10929 23:07:37.796099 # Traceback (most recent call last):
10930 23:07:37.806363 # File "/lava-12154433/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
10931 23:07:37.809621 # self.client = tpm2.Client()
10932 23:07:37.819423 # File "/lava-12154433/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
10933 23:07:37.825983 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
10934 23:07:37.829794 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
10935 23:07:37.830356 #
10936 23:07:37.835988 # ======================================================================
10937 23:07:37.842386 # ERROR: test_seal_with_too_long_auth (tpm2_tests.SmokeTest)
10938 23:07:37.849468 # ----------------------------------------------------------------------
10939 23:07:37.852410 # Traceback (most recent call last):
10940 23:07:37.862528 # File "/lava-12154433/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
10941 23:07:37.866206 # self.client = tpm2.Client()
10942 23:07:37.876101 # File "/lava-12154433/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
10943 23:07:37.878977 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
10944 23:07:37.885529 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
10945 23:07:37.885993 #
10946 23:07:37.892077 # ======================================================================
10947 23:07:37.895676 # ERROR: test_send_two_cmds (tpm2_tests.SmokeTest)
10948 23:07:37.902234 # ----------------------------------------------------------------------
10949 23:07:37.905331 # Traceback (most recent call last):
10950 23:07:37.915277 # File "/lava-12154433/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
10951 23:07:37.918555 # self.client = tpm2.Client()
10952 23:07:37.928860 # File "/lava-12154433/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
10953 23:07:37.937410 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
10954 23:07:37.940964 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
10955 23:07:37.941422 #
10956 23:07:37.947545 # ======================================================================
10957 23:07:37.951005 # ERROR: test_too_short_cmd (tpm2_tests.SmokeTest)
10958 23:07:37.960635 # ----------------------------------------------------------------------
10959 23:07:37.961190 # Traceback (most recent call last):
10960 23:07:37.970277 # File "/lava-12154433/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
10961 23:07:37.973947 # self.client = tpm2.Client()
10962 23:07:37.983254 # File "/lava-12154433/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
10963 23:07:37.990263 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
10964 23:07:37.993726 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
10965 23:07:37.994263 #
10966 23:07:38.001663 # ======================================================================
10967 23:07:38.005338 # ERROR: test_unseal_with_wrong_auth (tpm2_tests.SmokeTest)
10968 23:07:38.011676 # ----------------------------------------------------------------------
10969 23:07:38.015333 # Traceback (most recent call last):
10970 23:07:38.025072 # File "/lava-12154433/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
10971 23:07:38.028459 # self.client = tpm2.Client()
10972 23:07:38.038208 # File "/lava-12154433/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
10973 23:07:38.044596 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
10974 23:07:38.047819 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
10975 23:07:38.048311 #
10976 23:07:38.054727 # ======================================================================
10977 23:07:38.061289 # ERROR: test_unseal_with_wrong_policy (tpm2_tests.SmokeTest)
10978 23:07:38.068047 # ----------------------------------------------------------------------
10979 23:07:38.071362 # Traceback (most recent call last):
10980 23:07:38.081416 # File "/lava-12154433/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
10981 23:07:38.084424 # self.client = tpm2.Client()
10982 23:07:38.094414 # File "/lava-12154433/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
10983 23:07:38.097757 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
10984 23:07:38.104318 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
10985 23:07:38.104935 #
10986 23:07:38.110801 # ----------------------------------------------------------------------
10987 23:07:38.114354 # Ran 9 tests in 0.038s
10988 23:07:38.114912 #
10989 23:07:38.115277 # FAILED (errors=9)
10990 23:07:38.117239 # test_async (tpm2_tests.AsyncTest) ... ok
10991 23:07:38.124193 # test_flush_invalid_context (tpm2_tests.AsyncTest) ... ok
10992 23:07:38.124895 #
10993 23:07:38.130928 # ----------------------------------------------------------------------
10994 23:07:38.134160 # Ran 2 tests in 0.029s
10995 23:07:38.134710 #
10996 23:07:38.135074 # OK
10997 23:07:38.137512 ok 1 selftests: tpm2: test_smoke.sh
10998 23:07:38.140861 # selftests: tpm2: test_space.sh
10999 23:07:38.144570 # test_flush_context (tpm2_tests.SpaceTest) ... ERROR
11000 23:07:38.150518 # test_get_handles (tpm2_tests.SpaceTest) ... ERROR
11001 23:07:38.153971 # test_invalid_cc (tpm2_tests.SpaceTest) ... ERROR
11002 23:07:38.157239 # test_make_two_spaces (tpm2_tests.SpaceTest) ... ERROR
11003 23:07:38.160570 #
11004 23:07:38.163903 # ======================================================================
11005 23:07:38.170480 # ERROR: test_flush_context (tpm2_tests.SpaceTest)
11006 23:07:38.176890 # ----------------------------------------------------------------------
11007 23:07:38.180678 # Traceback (most recent call last):
11008 23:07:38.190583 # File "/lava-12154433/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 261, in test_flush_context
11009 23:07:38.193528 # root1 = space1.create_root_key()
11010 23:07:38.203625 # File "/lava-12154433/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11011 23:07:38.210430 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11012 23:07:38.220013 # File "/lava-12154433/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11013 23:07:38.223315 # raise ProtocolError(cc, rc)
11014 23:07:38.229895 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11015 23:07:38.230456 #
11016 23:07:38.236597 # ======================================================================
11017 23:07:38.239740 # ERROR: test_get_handles (tpm2_tests.SpaceTest)
11018 23:07:38.246414 # ----------------------------------------------------------------------
11019 23:07:38.249740 # Traceback (most recent call last):
11020 23:07:38.260039 # File "/lava-12154433/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 271, in test_get_handles
11021 23:07:38.263338 # space1.create_root_key()
11022 23:07:38.273110 # File "/lava-12154433/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11023 23:07:38.279818 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11024 23:07:38.289625 # File "/lava-12154433/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11025 23:07:38.293274 # raise ProtocolError(cc, rc)
11026 23:07:38.299884 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11027 23:07:38.300443 #
11028 23:07:38.306414 # ======================================================================
11029 23:07:38.309479 # ERROR: test_invalid_cc (tpm2_tests.SpaceTest)
11030 23:07:38.316006 # ----------------------------------------------------------------------
11031 23:07:38.319518 # Traceback (most recent call last):
11032 23:07:38.329398 # File "/lava-12154433/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 290, in test_invalid_cc
11033 23:07:38.336134 # root1 = space1.create_root_key()
11034 23:07:38.345932 # File "/lava-12154433/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11035 23:07:38.348948 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11036 23:07:38.359172 # File "/lava-12154433/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11037 23:07:38.362389 # raise ProtocolError(cc, rc)
11038 23:07:38.368668 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11039 23:07:38.369156 #
11040 23:07:38.375701 # ======================================================================
11041 23:07:38.381811 # ERROR: test_make_two_spaces (tpm2_tests.SpaceTest)
11042 23:07:38.388902 # ----------------------------------------------------------------------
11043 23:07:38.392139 # Traceback (most recent call last):
11044 23:07:38.402021 # File "/lava-12154433/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 247, in test_make_two_spaces
11045 23:07:38.405310 # root1 = space1.create_root_key()
11046 23:07:38.415418 # File "/lava-12154433/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11047 23:07:38.421943 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11048 23:07:38.431801 # File "/lava-12154433/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11049 23:07:38.435270 # raise ProtocolError(cc, rc)
11050 23:07:38.441672 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11051 23:07:38.442243 #
11052 23:07:38.448158 # ----------------------------------------------------------------------
11053 23:07:38.448763 # Ran 4 tests in 0.087s
11054 23:07:38.449132 #
11055 23:07:38.451588 # FAILED (errors=4)
11056 23:07:38.454903 not ok 2 selftests: tpm2: test_space.sh # exit=1
11057 23:07:38.480448 tpm2_test_smoke_sh pass
11058 23:07:38.483307 tpm2_test_space_sh fail
11059 23:07:38.497393 + ../../utils/send-to-lava.sh ./output/result.txt
11060 23:07:38.573869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-tpm2 RESULT=pass>
11061 23:07:38.575013 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-tpm2 RESULT=pass
11063 23:07:38.630471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass>
11064 23:07:38.631470 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass
11066 23:07:38.683545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_space_sh RESULT=fail>
11067 23:07:38.684158 + set +x
11068 23:07:38.684944 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_space_sh RESULT=fail
11070 23:07:38.690830 <LAVA_SIGNAL_ENDRUN 1_kselftest-tpm2 12154433_1.6.2.3.5>
11071 23:07:38.691683 Received signal: <ENDRUN> 1_kselftest-tpm2 12154433_1.6.2.3.5
11072 23:07:38.692091 Ending use of test pattern.
11073 23:07:38.692434 Ending test lava.1_kselftest-tpm2 (12154433_1.6.2.3.5), duration 11.76
11075 23:07:38.693786 <LAVA_TEST_RUNNER EXIT>
11076 23:07:38.694442 ok: lava_test_shell seems to have completed
11077 23:07:38.694997 shardfile-tpm2: pass
tpm2_test_smoke_sh: pass
tpm2_test_space_sh: fail
11078 23:07:38.695444 end: 3.1 lava-test-shell (duration 00:00:13) [common]
11079 23:07:38.695888 end: 3 lava-test-retry (duration 00:00:13) [common]
11080 23:07:38.696356 start: 4 finalize (timeout 00:07:42) [common]
11081 23:07:38.696907 start: 4.1 power-off (timeout 00:00:30) [common]
11082 23:07:38.697721 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=off'
11083 23:07:38.784385 >> Command sent successfully.
11084 23:07:38.788624 Returned 0 in 0 seconds
11085 23:07:38.889605 end: 4.1 power-off (duration 00:00:00) [common]
11087 23:07:38.891313 start: 4.2 read-feedback (timeout 00:07:42) [common]
11088 23:07:38.892865 Listened to connection for namespace 'common' for up to 1s
11089 23:07:39.892841 Finalising connection for namespace 'common'
11090 23:07:39.893723 Disconnecting from shell: Finalise
11091 23:07:39.894191 / #
11092 23:07:39.995198 end: 4.2 read-feedback (duration 00:00:01) [common]
11093 23:07:39.995880 end: 4 finalize (duration 00:00:01) [common]
11094 23:07:39.996476 Cleaning after the job
11095 23:07:39.997077 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12154433/tftp-deploy-0q52bfe7/ramdisk
11096 23:07:40.011188 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12154433/tftp-deploy-0q52bfe7/kernel
11097 23:07:40.047081 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12154433/tftp-deploy-0q52bfe7/dtb
11098 23:07:40.047376 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12154433/tftp-deploy-0q52bfe7/nfsrootfs
11099 23:07:40.141957 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12154433/tftp-deploy-0q52bfe7/modules
11100 23:07:40.149428 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12154433
11101 23:07:40.782543 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12154433
11102 23:07:40.782730 Job finished correctly