Boot log: mt8192-asurada-spherion-r0
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 27
- Kernel Errors: 36
- Errors: 0
1 23:02:05.430048 lava-dispatcher, installed at version: 2023.10
2 23:02:05.430298 start: 0 validate
3 23:02:05.430448 Start time: 2023-12-01 23:02:05.430437+00:00 (UTC)
4 23:02:05.430579 Using caching service: 'http://localhost/cache/?uri=%s'
5 23:02:05.430711 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-libcamera%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 23:02:05.690566 Using caching service: 'http://localhost/cache/?uri=%s'
7 23:02:05.690883 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.64-cip10%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 23:02:30.463579 Using caching service: 'http://localhost/cache/?uri=%s'
9 23:02:30.464417 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.64-cip10%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 23:02:30.734365 Using caching service: 'http://localhost/cache/?uri=%s'
11 23:02:30.735077 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-libcamera%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 23:02:31.267036 Using caching service: 'http://localhost/cache/?uri=%s'
13 23:02:31.268024 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.64-cip10%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 23:02:34.278116 validate duration: 28.85
16 23:02:34.278409 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 23:02:34.278507 start: 1.1 download-retry (timeout 00:10:00) [common]
18 23:02:34.278591 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 23:02:34.278716 Not decompressing ramdisk as can be used compressed.
20 23:02:34.278797 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-libcamera/20230623.0/arm64/initrd.cpio.gz
21 23:02:34.278860 saving as /var/lib/lava/dispatcher/tmp/12154430/tftp-deploy-s7vuzfyl/ramdisk/initrd.cpio.gz
22 23:02:34.278983 total size: 4665398 (4 MB)
23 23:02:34.544634 progress 0 % (0 MB)
24 23:02:34.546198 progress 5 % (0 MB)
25 23:02:34.547511 progress 10 % (0 MB)
26 23:02:34.548771 progress 15 % (0 MB)
27 23:02:34.550015 progress 20 % (0 MB)
28 23:02:34.551248 progress 25 % (1 MB)
29 23:02:34.552484 progress 30 % (1 MB)
30 23:02:34.553708 progress 35 % (1 MB)
31 23:02:34.554952 progress 40 % (1 MB)
32 23:02:34.556354 progress 45 % (2 MB)
33 23:02:34.557593 progress 50 % (2 MB)
34 23:02:34.558870 progress 55 % (2 MB)
35 23:02:34.560112 progress 60 % (2 MB)
36 23:02:34.561342 progress 65 % (2 MB)
37 23:02:34.562660 progress 70 % (3 MB)
38 23:02:34.563892 progress 75 % (3 MB)
39 23:02:34.565116 progress 80 % (3 MB)
40 23:02:34.566552 progress 85 % (3 MB)
41 23:02:34.567776 progress 90 % (4 MB)
42 23:02:34.569011 progress 95 % (4 MB)
43 23:02:34.570255 progress 100 % (4 MB)
44 23:02:34.570411 4 MB downloaded in 0.29 s (15.27 MB/s)
45 23:02:34.570615 end: 1.1.1 http-download (duration 00:00:00) [common]
47 23:02:34.570849 end: 1.1 download-retry (duration 00:00:00) [common]
48 23:02:34.570934 start: 1.2 download-retry (timeout 00:10:00) [common]
49 23:02:34.571014 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 23:02:34.571150 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.64-cip10/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 23:02:34.571217 saving as /var/lib/lava/dispatcher/tmp/12154430/tftp-deploy-s7vuzfyl/kernel/Image
52 23:02:34.571277 total size: 49172992 (46 MB)
53 23:02:34.571337 No compression specified
54 23:02:34.572430 progress 0 % (0 MB)
55 23:02:34.585189 progress 5 % (2 MB)
56 23:02:34.597849 progress 10 % (4 MB)
57 23:02:34.610529 progress 15 % (7 MB)
58 23:02:34.623428 progress 20 % (9 MB)
59 23:02:34.636536 progress 25 % (11 MB)
60 23:02:34.649471 progress 30 % (14 MB)
61 23:02:34.662271 progress 35 % (16 MB)
62 23:02:34.675050 progress 40 % (18 MB)
63 23:02:34.688003 progress 45 % (21 MB)
64 23:02:34.700848 progress 50 % (23 MB)
65 23:02:34.713712 progress 55 % (25 MB)
66 23:02:34.726763 progress 60 % (28 MB)
67 23:02:34.739773 progress 65 % (30 MB)
68 23:02:34.752933 progress 70 % (32 MB)
69 23:02:34.765977 progress 75 % (35 MB)
70 23:02:34.778828 progress 80 % (37 MB)
71 23:02:34.791635 progress 85 % (39 MB)
72 23:02:34.804673 progress 90 % (42 MB)
73 23:02:34.817379 progress 95 % (44 MB)
74 23:02:34.829991 progress 100 % (46 MB)
75 23:02:34.830286 46 MB downloaded in 0.26 s (181.06 MB/s)
76 23:02:34.830455 end: 1.2.1 http-download (duration 00:00:00) [common]
78 23:02:34.830681 end: 1.2 download-retry (duration 00:00:00) [common]
79 23:02:34.830769 start: 1.3 download-retry (timeout 00:09:59) [common]
80 23:02:34.830853 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 23:02:34.830994 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.64-cip10/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 23:02:34.831065 saving as /var/lib/lava/dispatcher/tmp/12154430/tftp-deploy-s7vuzfyl/dtb/mt8192-asurada-spherion-r0.dtb
83 23:02:34.831126 total size: 47278 (0 MB)
84 23:02:34.831185 No compression specified
85 23:02:34.832299 progress 69 % (0 MB)
86 23:02:34.832580 progress 100 % (0 MB)
87 23:02:34.832734 0 MB downloaded in 0.00 s (28.08 MB/s)
88 23:02:34.832855 end: 1.3.1 http-download (duration 00:00:00) [common]
90 23:02:34.833073 end: 1.3 download-retry (duration 00:00:00) [common]
91 23:02:34.833161 start: 1.4 download-retry (timeout 00:09:59) [common]
92 23:02:34.833243 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 23:02:34.833355 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-libcamera/20230623.0/arm64/full.rootfs.tar.xz
94 23:02:34.833422 saving as /var/lib/lava/dispatcher/tmp/12154430/tftp-deploy-s7vuzfyl/nfsrootfs/full.rootfs.tar
95 23:02:34.833481 total size: 89451516 (85 MB)
96 23:02:34.833541 Using unxz to decompress xz
97 23:02:34.837768 progress 0 % (0 MB)
98 23:02:35.062845 progress 5 % (4 MB)
99 23:02:35.288927 progress 10 % (8 MB)
100 23:02:35.549744 progress 15 % (12 MB)
101 23:02:35.751565 progress 20 % (17 MB)
102 23:02:35.852758 progress 25 % (21 MB)
103 23:02:36.107997 progress 30 % (25 MB)
104 23:02:36.404081 progress 35 % (29 MB)
105 23:02:36.680382 progress 40 % (34 MB)
106 23:02:36.954367 progress 45 % (38 MB)
107 23:02:37.209166 progress 50 % (42 MB)
108 23:02:37.482738 progress 55 % (46 MB)
109 23:02:37.742325 progress 60 % (51 MB)
110 23:02:38.018929 progress 65 % (55 MB)
111 23:02:38.323985 progress 70 % (59 MB)
112 23:02:38.639983 progress 75 % (64 MB)
113 23:02:38.955653 progress 80 % (68 MB)
114 23:02:39.223443 progress 85 % (72 MB)
115 23:02:39.464342 progress 90 % (76 MB)
116 23:02:39.735120 progress 95 % (81 MB)
117 23:02:40.015770 progress 100 % (85 MB)
118 23:02:40.022339 85 MB downloaded in 5.19 s (16.44 MB/s)
119 23:02:40.022737 end: 1.4.1 http-download (duration 00:00:05) [common]
121 23:02:40.023141 end: 1.4 download-retry (duration 00:00:05) [common]
122 23:02:40.023276 start: 1.5 download-retry (timeout 00:09:54) [common]
123 23:02:40.023408 start: 1.5.1 http-download (timeout 00:09:54) [common]
124 23:02:40.023608 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.64-cip10/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 23:02:40.023713 saving as /var/lib/lava/dispatcher/tmp/12154430/tftp-deploy-s7vuzfyl/modules/modules.tar
126 23:02:40.023808 total size: 8616152 (8 MB)
127 23:02:40.023909 Using unxz to decompress xz
128 23:02:40.029324 progress 0 % (0 MB)
129 23:02:40.051905 progress 5 % (0 MB)
130 23:02:40.076537 progress 10 % (0 MB)
131 23:02:40.101437 progress 15 % (1 MB)
132 23:02:40.127254 progress 20 % (1 MB)
133 23:02:40.152581 progress 25 % (2 MB)
134 23:02:40.179113 progress 30 % (2 MB)
135 23:02:40.206339 progress 35 % (2 MB)
136 23:02:40.231016 progress 40 % (3 MB)
137 23:02:40.257697 progress 45 % (3 MB)
138 23:02:40.285055 progress 50 % (4 MB)
139 23:02:40.311702 progress 55 % (4 MB)
140 23:02:40.338567 progress 60 % (4 MB)
141 23:02:40.366758 progress 65 % (5 MB)
142 23:02:40.395440 progress 70 % (5 MB)
143 23:02:40.419941 progress 75 % (6 MB)
144 23:02:40.448633 progress 80 % (6 MB)
145 23:02:40.476297 progress 85 % (7 MB)
146 23:02:40.503341 progress 90 % (7 MB)
147 23:02:40.535056 progress 95 % (7 MB)
148 23:02:40.565291 progress 100 % (8 MB)
149 23:02:40.572217 8 MB downloaded in 0.55 s (14.98 MB/s)
150 23:02:40.572515 end: 1.5.1 http-download (duration 00:00:01) [common]
152 23:02:40.572788 end: 1.5 download-retry (duration 00:00:01) [common]
153 23:02:40.572882 start: 1.6 prepare-tftp-overlay (timeout 00:09:54) [common]
154 23:02:40.572978 start: 1.6.1 extract-nfsrootfs (timeout 00:09:54) [common]
155 23:02:42.446261 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12154430/extract-nfsrootfs-ao66pv48
156 23:02:42.446474 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 23:02:42.446582 start: 1.6.2 lava-overlay (timeout 00:09:52) [common]
158 23:02:42.446764 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12154430/lava-overlay-yzjngwcx
159 23:02:42.446900 makedir: /var/lib/lava/dispatcher/tmp/12154430/lava-overlay-yzjngwcx/lava-12154430/bin
160 23:02:42.447005 makedir: /var/lib/lava/dispatcher/tmp/12154430/lava-overlay-yzjngwcx/lava-12154430/tests
161 23:02:42.447106 makedir: /var/lib/lava/dispatcher/tmp/12154430/lava-overlay-yzjngwcx/lava-12154430/results
162 23:02:42.447212 Creating /var/lib/lava/dispatcher/tmp/12154430/lava-overlay-yzjngwcx/lava-12154430/bin/lava-add-keys
163 23:02:42.447362 Creating /var/lib/lava/dispatcher/tmp/12154430/lava-overlay-yzjngwcx/lava-12154430/bin/lava-add-sources
164 23:02:42.447494 Creating /var/lib/lava/dispatcher/tmp/12154430/lava-overlay-yzjngwcx/lava-12154430/bin/lava-background-process-start
165 23:02:42.447625 Creating /var/lib/lava/dispatcher/tmp/12154430/lava-overlay-yzjngwcx/lava-12154430/bin/lava-background-process-stop
166 23:02:42.447755 Creating /var/lib/lava/dispatcher/tmp/12154430/lava-overlay-yzjngwcx/lava-12154430/bin/lava-common-functions
167 23:02:42.447908 Creating /var/lib/lava/dispatcher/tmp/12154430/lava-overlay-yzjngwcx/lava-12154430/bin/lava-echo-ipv4
168 23:02:42.448072 Creating /var/lib/lava/dispatcher/tmp/12154430/lava-overlay-yzjngwcx/lava-12154430/bin/lava-install-packages
169 23:02:42.448205 Creating /var/lib/lava/dispatcher/tmp/12154430/lava-overlay-yzjngwcx/lava-12154430/bin/lava-installed-packages
170 23:02:42.448335 Creating /var/lib/lava/dispatcher/tmp/12154430/lava-overlay-yzjngwcx/lava-12154430/bin/lava-os-build
171 23:02:42.448463 Creating /var/lib/lava/dispatcher/tmp/12154430/lava-overlay-yzjngwcx/lava-12154430/bin/lava-probe-channel
172 23:02:42.448590 Creating /var/lib/lava/dispatcher/tmp/12154430/lava-overlay-yzjngwcx/lava-12154430/bin/lava-probe-ip
173 23:02:42.448717 Creating /var/lib/lava/dispatcher/tmp/12154430/lava-overlay-yzjngwcx/lava-12154430/bin/lava-target-ip
174 23:02:42.448847 Creating /var/lib/lava/dispatcher/tmp/12154430/lava-overlay-yzjngwcx/lava-12154430/bin/lava-target-mac
175 23:02:42.448973 Creating /var/lib/lava/dispatcher/tmp/12154430/lava-overlay-yzjngwcx/lava-12154430/bin/lava-target-storage
176 23:02:42.449101 Creating /var/lib/lava/dispatcher/tmp/12154430/lava-overlay-yzjngwcx/lava-12154430/bin/lava-test-case
177 23:02:42.449229 Creating /var/lib/lava/dispatcher/tmp/12154430/lava-overlay-yzjngwcx/lava-12154430/bin/lava-test-event
178 23:02:42.449355 Creating /var/lib/lava/dispatcher/tmp/12154430/lava-overlay-yzjngwcx/lava-12154430/bin/lava-test-feedback
179 23:02:42.449481 Creating /var/lib/lava/dispatcher/tmp/12154430/lava-overlay-yzjngwcx/lava-12154430/bin/lava-test-raise
180 23:02:42.449606 Creating /var/lib/lava/dispatcher/tmp/12154430/lava-overlay-yzjngwcx/lava-12154430/bin/lava-test-reference
181 23:02:42.449731 Creating /var/lib/lava/dispatcher/tmp/12154430/lava-overlay-yzjngwcx/lava-12154430/bin/lava-test-runner
182 23:02:42.449855 Creating /var/lib/lava/dispatcher/tmp/12154430/lava-overlay-yzjngwcx/lava-12154430/bin/lava-test-set
183 23:02:42.450001 Creating /var/lib/lava/dispatcher/tmp/12154430/lava-overlay-yzjngwcx/lava-12154430/bin/lava-test-shell
184 23:02:42.450164 Updating /var/lib/lava/dispatcher/tmp/12154430/lava-overlay-yzjngwcx/lava-12154430/bin/lava-install-packages (oe)
185 23:02:42.450496 Updating /var/lib/lava/dispatcher/tmp/12154430/lava-overlay-yzjngwcx/lava-12154430/bin/lava-installed-packages (oe)
186 23:02:42.450627 Creating /var/lib/lava/dispatcher/tmp/12154430/lava-overlay-yzjngwcx/lava-12154430/environment
187 23:02:42.450727 LAVA metadata
188 23:02:42.450802 - LAVA_JOB_ID=12154430
189 23:02:42.450867 - LAVA_DISPATCHER_IP=192.168.201.1
190 23:02:42.450977 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:52) [common]
191 23:02:42.451045 skipped lava-vland-overlay
192 23:02:42.451120 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 23:02:42.451200 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:52) [common]
194 23:02:42.451261 skipped lava-multinode-overlay
195 23:02:42.451333 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 23:02:42.451410 start: 1.6.2.3 test-definition (timeout 00:09:52) [common]
197 23:02:42.451485 Loading test definitions
198 23:02:42.451576 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:52) [common]
199 23:02:42.451647 Using /lava-12154430 at stage 0
200 23:02:42.451960 uuid=12154430_1.6.2.3.1 testdef=None
201 23:02:42.452075 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 23:02:42.452161 start: 1.6.2.3.2 test-overlay (timeout 00:09:52) [common]
203 23:02:42.452668 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 23:02:42.452893 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:52) [common]
206 23:02:42.453512 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 23:02:42.453738 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:52) [common]
209 23:02:42.454435 runner path: /var/lib/lava/dispatcher/tmp/12154430/lava-overlay-yzjngwcx/lava-12154430/0/tests/0_lc-compliance test_uuid 12154430_1.6.2.3.1
210 23:02:42.454597 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 23:02:42.454802 Creating lava-test-runner.conf files
213 23:02:42.454865 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12154430/lava-overlay-yzjngwcx/lava-12154430/0 for stage 0
214 23:02:42.454954 - 0_lc-compliance
215 23:02:42.455053 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
216 23:02:42.455137 start: 1.6.2.4 compress-overlay (timeout 00:09:52) [common]
217 23:02:42.461636 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
218 23:02:42.461779 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:52) [common]
219 23:02:42.461872 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
220 23:02:42.461967 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
221 23:02:42.462055 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:52) [common]
222 23:02:42.586334 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
223 23:02:42.586814 start: 1.6.4 extract-modules (timeout 00:09:52) [common]
224 23:02:42.586984 extracting modules file /var/lib/lava/dispatcher/tmp/12154430/tftp-deploy-s7vuzfyl/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12154430/extract-nfsrootfs-ao66pv48
225 23:02:42.828062 extracting modules file /var/lib/lava/dispatcher/tmp/12154430/tftp-deploy-s7vuzfyl/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12154430/extract-overlay-ramdisk-kxmq9zgs/ramdisk
226 23:02:43.065024 end: 1.6.4 extract-modules (duration 00:00:00) [common]
227 23:02:43.065197 start: 1.6.5 apply-overlay-tftp (timeout 00:09:51) [common]
228 23:02:43.065289 [common] Applying overlay to NFS
229 23:02:43.065363 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12154430/compress-overlay-si_9fbrt/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12154430/extract-nfsrootfs-ao66pv48
230 23:02:43.072225 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
231 23:02:43.072377 start: 1.6.6 configure-preseed-file (timeout 00:09:51) [common]
232 23:02:43.072471 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
233 23:02:43.072559 start: 1.6.7 compress-ramdisk (timeout 00:09:51) [common]
234 23:02:43.072643 Building ramdisk /var/lib/lava/dispatcher/tmp/12154430/extract-overlay-ramdisk-kxmq9zgs/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12154430/extract-overlay-ramdisk-kxmq9zgs/ramdisk
235 23:02:43.412095 >> 119410 blocks
236 23:02:45.390398 rename /var/lib/lava/dispatcher/tmp/12154430/extract-overlay-ramdisk-kxmq9zgs/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12154430/tftp-deploy-s7vuzfyl/ramdisk/ramdisk.cpio.gz
237 23:02:45.390856 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
238 23:02:45.390985 start: 1.6.8 prepare-kernel (timeout 00:09:49) [common]
239 23:02:45.391088 start: 1.6.8.1 prepare-fit (timeout 00:09:49) [common]
240 23:02:45.391196 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12154430/tftp-deploy-s7vuzfyl/kernel/Image'
241 23:02:58.875533 Returned 0 in 13 seconds
242 23:02:58.976157 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12154430/tftp-deploy-s7vuzfyl/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12154430/tftp-deploy-s7vuzfyl/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12154430/tftp-deploy-s7vuzfyl/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12154430/tftp-deploy-s7vuzfyl/kernel/image.itb
243 23:02:59.339287 output: FIT description: Kernel Image image with one or more FDT blobs
244 23:02:59.339648 output: Created: Fri Dec 1 23:02:59 2023
245 23:02:59.339724 output: Image 0 (kernel-1)
246 23:02:59.339787 output: Description:
247 23:02:59.339848 output: Created: Fri Dec 1 23:02:59 2023
248 23:02:59.339910 output: Type: Kernel Image
249 23:02:59.339970 output: Compression: lzma compressed
250 23:02:59.340029 output: Data Size: 11043984 Bytes = 10785.14 KiB = 10.53 MiB
251 23:02:59.340090 output: Architecture: AArch64
252 23:02:59.340151 output: OS: Linux
253 23:02:59.340210 output: Load Address: 0x00000000
254 23:02:59.340269 output: Entry Point: 0x00000000
255 23:02:59.340327 output: Hash algo: crc32
256 23:02:59.340386 output: Hash value: 36c84243
257 23:02:59.340443 output: Image 1 (fdt-1)
258 23:02:59.340498 output: Description: mt8192-asurada-spherion-r0
259 23:02:59.340551 output: Created: Fri Dec 1 23:02:59 2023
260 23:02:59.340604 output: Type: Flat Device Tree
261 23:02:59.340656 output: Compression: uncompressed
262 23:02:59.340709 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
263 23:02:59.340762 output: Architecture: AArch64
264 23:02:59.340815 output: Hash algo: crc32
265 23:02:59.340868 output: Hash value: cc4352de
266 23:02:59.340920 output: Image 2 (ramdisk-1)
267 23:02:59.340972 output: Description: unavailable
268 23:02:59.341025 output: Created: Fri Dec 1 23:02:59 2023
269 23:02:59.341077 output: Type: RAMDisk Image
270 23:02:59.341129 output: Compression: Unknown Compression
271 23:02:59.341181 output: Data Size: 17795173 Bytes = 17378.10 KiB = 16.97 MiB
272 23:02:59.341234 output: Architecture: AArch64
273 23:02:59.341285 output: OS: Linux
274 23:02:59.341338 output: Load Address: unavailable
275 23:02:59.341390 output: Entry Point: unavailable
276 23:02:59.341443 output: Hash algo: crc32
277 23:02:59.341495 output: Hash value: 54b3969e
278 23:02:59.341547 output: Default Configuration: 'conf-1'
279 23:02:59.341599 output: Configuration 0 (conf-1)
280 23:02:59.341651 output: Description: mt8192-asurada-spherion-r0
281 23:02:59.341703 output: Kernel: kernel-1
282 23:02:59.341755 output: Init Ramdisk: ramdisk-1
283 23:02:59.341807 output: FDT: fdt-1
284 23:02:59.341860 output: Loadables: kernel-1
285 23:02:59.341912 output:
286 23:02:59.342125 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
287 23:02:59.342281 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
288 23:02:59.342464 end: 1.6 prepare-tftp-overlay (duration 00:00:19) [common]
289 23:02:59.342600 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:35) [common]
290 23:02:59.342710 No LXC device requested
291 23:02:59.342796 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
292 23:02:59.342886 start: 1.8 deploy-device-env (timeout 00:09:35) [common]
293 23:02:59.342966 end: 1.8 deploy-device-env (duration 00:00:00) [common]
294 23:02:59.343038 Checking files for TFTP limit of 4294967296 bytes.
295 23:02:59.343549 end: 1 tftp-deploy (duration 00:00:25) [common]
296 23:02:59.343649 start: 2 depthcharge-action (timeout 00:05:00) [common]
297 23:02:59.343745 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
298 23:02:59.343891 substitutions:
299 23:02:59.343959 - {DTB}: 12154430/tftp-deploy-s7vuzfyl/dtb/mt8192-asurada-spherion-r0.dtb
300 23:02:59.344025 - {INITRD}: 12154430/tftp-deploy-s7vuzfyl/ramdisk/ramdisk.cpio.gz
301 23:02:59.344086 - {KERNEL}: 12154430/tftp-deploy-s7vuzfyl/kernel/Image
302 23:02:59.344144 - {LAVA_MAC}: None
303 23:02:59.344201 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12154430/extract-nfsrootfs-ao66pv48
304 23:02:59.344258 - {NFS_SERVER_IP}: 192.168.201.1
305 23:02:59.344314 - {PRESEED_CONFIG}: None
306 23:02:59.344369 - {PRESEED_LOCAL}: None
307 23:02:59.344423 - {RAMDISK}: 12154430/tftp-deploy-s7vuzfyl/ramdisk/ramdisk.cpio.gz
308 23:02:59.344477 - {ROOT_PART}: None
309 23:02:59.344530 - {ROOT}: None
310 23:02:59.344583 - {SERVER_IP}: 192.168.201.1
311 23:02:59.344637 - {TEE}: None
312 23:02:59.344690 Parsed boot commands:
313 23:02:59.344744 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
314 23:02:59.344932 Parsed boot commands: tftpboot 192.168.201.1 12154430/tftp-deploy-s7vuzfyl/kernel/image.itb 12154430/tftp-deploy-s7vuzfyl/kernel/cmdline
315 23:02:59.345021 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
316 23:02:59.345105 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
317 23:02:59.345197 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
318 23:02:59.345283 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
319 23:02:59.345354 Not connected, no need to disconnect.
320 23:02:59.345428 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
321 23:02:59.345509 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
322 23:02:59.345576 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-2'
323 23:02:59.349889 Setting prompt string to ['lava-test: # ']
324 23:02:59.350366 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
325 23:02:59.350480 end: 2.2.1 reset-connection (duration 00:00:00) [common]
326 23:02:59.350583 start: 2.2.2 reset-device (timeout 00:05:00) [common]
327 23:02:59.350694 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
328 23:02:59.350905 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=reboot'
329 23:03:04.488336 >> Command sent successfully.
330 23:03:04.490971 Returned 0 in 5 seconds
331 23:03:04.591416 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
333 23:03:04.591794 end: 2.2.2 reset-device (duration 00:00:05) [common]
334 23:03:04.591917 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
335 23:03:04.592017 Setting prompt string to 'Starting depthcharge on Spherion...'
336 23:03:04.592102 Changing prompt to 'Starting depthcharge on Spherion...'
337 23:03:04.592193 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
338 23:03:04.592558 [Enter `^Ec?' for help]
339 23:03:04.763800
340 23:03:04.763962
341 23:03:04.764062 F0: 102B 0000
342 23:03:04.764151
343 23:03:04.764232 F3: 1001 0000 [0200]
344 23:03:04.767156
345 23:03:04.767245 F3: 1001 0000
346 23:03:04.767334
347 23:03:04.767418 F7: 102D 0000
348 23:03:04.767500
349 23:03:04.770049 F1: 0000 0000
350 23:03:04.770150
351 23:03:04.770259 V0: 0000 0000 [0001]
352 23:03:04.770392
353 23:03:04.773421 00: 0007 8000
354 23:03:04.773514
355 23:03:04.773618 01: 0000 0000
356 23:03:04.773722
357 23:03:04.776496 BP: 0C00 0209 [0000]
358 23:03:04.776584
359 23:03:04.776672 G0: 1182 0000
360 23:03:04.776755
361 23:03:04.780291 EC: 0000 0021 [4000]
362 23:03:04.780380
363 23:03:04.780484 S7: 0000 0000 [0000]
364 23:03:04.780586
365 23:03:04.784367 CC: 0000 0000 [0001]
366 23:03:04.784519
367 23:03:04.784609 T0: 0000 0040 [010F]
368 23:03:04.784693
369 23:03:04.784773 Jump to BL
370 23:03:04.784872
371 23:03:04.811161
372 23:03:04.811310
373 23:03:04.811442
374 23:03:04.817659 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
375 23:03:04.820893 ARM64: Exception handlers installed.
376 23:03:04.825011 ARM64: Testing exception
377 23:03:04.828346 ARM64: Done test exception
378 23:03:04.834898 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
379 23:03:04.844732 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
380 23:03:04.851634 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
381 23:03:04.861865 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
382 23:03:04.868704 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
383 23:03:04.874914 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
384 23:03:04.887547 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
385 23:03:04.894123 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
386 23:03:04.913212 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
387 23:03:04.916676 WDT: Last reset was cold boot
388 23:03:04.920726 SPI1(PAD0) initialized at 2873684 Hz
389 23:03:04.923850 SPI5(PAD0) initialized at 992727 Hz
390 23:03:04.926607 VBOOT: Loading verstage.
391 23:03:04.933136 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
392 23:03:04.936795 FMAP: Found "FLASH" version 1.1 at 0x20000.
393 23:03:04.940110 FMAP: base = 0x0 size = 0x800000 #areas = 25
394 23:03:04.943137 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
395 23:03:04.950795 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
396 23:03:04.957456 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
397 23:03:04.968311 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
398 23:03:04.968467
399 23:03:04.968569
400 23:03:04.978265 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
401 23:03:04.981260 ARM64: Exception handlers installed.
402 23:03:04.984602 ARM64: Testing exception
403 23:03:04.988255 ARM64: Done test exception
404 23:03:04.992002 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
405 23:03:04.995163 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
406 23:03:05.009303 Probing TPM: . done!
407 23:03:05.009436 TPM ready after 0 ms
408 23:03:05.016635 Connected to device vid:did:rid of 1ae0:0028:00
409 23:03:05.023130 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
410 23:03:05.081791 Initialized TPM device CR50 revision 0
411 23:03:05.093558 tlcl_send_startup: Startup return code is 0
412 23:03:05.093777 TPM: setup succeeded
413 23:03:05.105140 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
414 23:03:05.113483 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
415 23:03:05.125645 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
416 23:03:05.135500 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
417 23:03:05.139215 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
418 23:03:05.144212 in-header: 03 07 00 00 08 00 00 00
419 23:03:05.148135 in-data: aa e4 47 04 13 02 00 00
420 23:03:05.151515 Chrome EC: UHEPI supported
421 23:03:05.159211 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
422 23:03:05.162161 in-header: 03 95 00 00 08 00 00 00
423 23:03:05.166008 in-data: 18 20 20 08 00 00 00 00
424 23:03:05.166151 Phase 1
425 23:03:05.169147 FMAP: area GBB found @ 3f5000 (12032 bytes)
426 23:03:05.176275 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
427 23:03:05.180255 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
428 23:03:05.183873 Recovery requested (1009000e)
429 23:03:05.192838 TPM: Extending digest for VBOOT: boot mode into PCR 0
430 23:03:05.198298 tlcl_extend: response is 0
431 23:03:05.207667 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
432 23:03:05.212845 tlcl_extend: response is 0
433 23:03:05.219982 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
434 23:03:05.239984 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
435 23:03:05.246467 BS: bootblock times (exec / console): total (unknown) / 148 ms
436 23:03:05.246597
437 23:03:05.246699
438 23:03:05.256897 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
439 23:03:05.260237 ARM64: Exception handlers installed.
440 23:03:05.262889 ARM64: Testing exception
441 23:03:05.262987 ARM64: Done test exception
442 23:03:05.284962 pmic_efuse_setting: Set efuses in 11 msecs
443 23:03:05.288926 pmwrap_interface_init: Select PMIF_VLD_RDY
444 23:03:05.295444 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
445 23:03:05.298614 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
446 23:03:05.305484 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
447 23:03:05.309057 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
448 23:03:05.312660 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
449 23:03:05.320356 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
450 23:03:05.323714 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
451 23:03:05.327397 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
452 23:03:05.331306 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
453 23:03:05.339127 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
454 23:03:05.342140 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
455 23:03:05.345973 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
456 23:03:05.350026 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
457 23:03:05.357580 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
458 23:03:05.364516 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
459 23:03:05.368399 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
460 23:03:05.376099 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
461 23:03:05.379995 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
462 23:03:05.386693 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
463 23:03:05.390519 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
464 23:03:05.397980 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
465 23:03:05.401921 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
466 23:03:05.409422 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
467 23:03:05.413412 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
468 23:03:05.417268 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
469 23:03:05.424642 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
470 23:03:05.428176 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
471 23:03:05.435347 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
472 23:03:05.438733 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
473 23:03:05.442843 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
474 23:03:05.449612 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
475 23:03:05.453547 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
476 23:03:05.460251 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
477 23:03:05.464365 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
478 23:03:05.468016 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
479 23:03:05.475173 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
480 23:03:05.479460 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
481 23:03:05.482838 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
482 23:03:05.490103 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
483 23:03:05.493677 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
484 23:03:05.497861 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
485 23:03:05.501181 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
486 23:03:05.504427 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
487 23:03:05.512264 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
488 23:03:05.516129 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
489 23:03:05.519938 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
490 23:03:05.523043 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
491 23:03:05.526856 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
492 23:03:05.533983 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
493 23:03:05.537766 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
494 23:03:05.541397 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
495 23:03:05.548931 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
496 23:03:05.556583 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
497 23:03:05.559490 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
498 23:03:05.570449 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
499 23:03:05.578003 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
500 23:03:05.581816 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
501 23:03:05.588773 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
502 23:03:05.592399 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
503 23:03:05.600023 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x3b
504 23:03:05.603063 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
505 23:03:05.610511 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
506 23:03:05.613745 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
507 23:03:05.623033 [RTC]rtc_get_frequency_meter,154: input=15, output=853
508 23:03:05.632107 [RTC]rtc_get_frequency_meter,154: input=7, output=724
509 23:03:05.642406 [RTC]rtc_get_frequency_meter,154: input=11, output=789
510 23:03:05.651392 [RTC]rtc_get_frequency_meter,154: input=13, output=821
511 23:03:05.660764 [RTC]rtc_get_frequency_meter,154: input=12, output=804
512 23:03:05.669952 [RTC]rtc_get_frequency_meter,154: input=11, output=789
513 23:03:05.680436 [RTC]rtc_get_frequency_meter,154: input=12, output=804
514 23:03:05.684269 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
515 23:03:05.687829 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
516 23:03:05.692125 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
517 23:03:05.699043 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
518 23:03:05.702432 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
519 23:03:05.706198 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
520 23:03:05.710442 ADC[4]: Raw value=904064 ID=7
521 23:03:05.710543 ADC[3]: Raw value=213546 ID=1
522 23:03:05.713672 RAM Code: 0x71
523 23:03:05.717330 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
524 23:03:05.721222 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
525 23:03:05.732255 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
526 23:03:05.735821 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
527 23:03:05.739577 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
528 23:03:05.743583 in-header: 03 07 00 00 08 00 00 00
529 23:03:05.746999 in-data: aa e4 47 04 13 02 00 00
530 23:03:05.750477 Chrome EC: UHEPI supported
531 23:03:05.757663 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
532 23:03:05.761429 in-header: 03 95 00 00 08 00 00 00
533 23:03:05.765608 in-data: 18 20 20 08 00 00 00 00
534 23:03:05.768388 MRC: failed to locate region type 0.
535 23:03:05.771983 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
536 23:03:05.775812 DRAM-K: Running full calibration
537 23:03:05.782995 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
538 23:03:05.783126 header.status = 0x0
539 23:03:05.786447 header.version = 0x6 (expected: 0x6)
540 23:03:05.790370 header.size = 0xd00 (expected: 0xd00)
541 23:03:05.794677 header.flags = 0x0
542 23:03:05.798068 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
543 23:03:05.817638 read SPI 0x72590 0x1c583: 12500 us, 9287 KB/s, 74.296 Mbps
544 23:03:05.824670 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
545 23:03:05.828490 dram_init: ddr_geometry: 2
546 23:03:05.828585 [EMI] MDL number = 2
547 23:03:05.832246 [EMI] Get MDL freq = 0
548 23:03:05.832326 dram_init: ddr_type: 0
549 23:03:05.835823 is_discrete_lpddr4: 1
550 23:03:05.839712 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
551 23:03:05.839797
552 23:03:05.839870
553 23:03:05.839967 [Bian_co] ETT version 0.0.0.1
554 23:03:05.846693 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
555 23:03:05.846804
556 23:03:05.850813 dramc_set_vcore_voltage set vcore to 650000
557 23:03:05.850905 Read voltage for 800, 4
558 23:03:05.853907 Vio18 = 0
559 23:03:05.854013 Vcore = 650000
560 23:03:05.854111 Vdram = 0
561 23:03:05.857259 Vddq = 0
562 23:03:05.857365 Vmddr = 0
563 23:03:05.860490 dram_init: config_dvfs: 1
564 23:03:05.863889 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
565 23:03:05.871174 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
566 23:03:05.874552 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
567 23:03:05.877999 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
568 23:03:05.881591 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
569 23:03:05.885068 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
570 23:03:05.885161 MEM_TYPE=3, freq_sel=18
571 23:03:05.888727 sv_algorithm_assistance_LP4_1600
572 23:03:05.892437 ============ PULL DRAM RESETB DOWN ============
573 23:03:05.899271 ========== PULL DRAM RESETB DOWN end =========
574 23:03:05.902400 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
575 23:03:05.905650 ===================================
576 23:03:05.908898 LPDDR4 DRAM CONFIGURATION
577 23:03:05.912423 ===================================
578 23:03:05.912514 EX_ROW_EN[0] = 0x0
579 23:03:05.915607 EX_ROW_EN[1] = 0x0
580 23:03:05.919001 LP4Y_EN = 0x0
581 23:03:05.919084 WORK_FSP = 0x0
582 23:03:05.922180 WL = 0x2
583 23:03:05.922286 RL = 0x2
584 23:03:05.925487 BL = 0x2
585 23:03:05.925562 RPST = 0x0
586 23:03:05.929201 RD_PRE = 0x0
587 23:03:05.929274 WR_PRE = 0x1
588 23:03:05.932277 WR_PST = 0x0
589 23:03:05.932355 DBI_WR = 0x0
590 23:03:05.935521 DBI_RD = 0x0
591 23:03:05.935591 OTF = 0x1
592 23:03:05.939151 ===================================
593 23:03:05.942065 ===================================
594 23:03:05.945768 ANA top config
595 23:03:05.948708 ===================================
596 23:03:05.948796 DLL_ASYNC_EN = 0
597 23:03:05.952434 ALL_SLAVE_EN = 1
598 23:03:05.955545 NEW_RANK_MODE = 1
599 23:03:05.959342 DLL_IDLE_MODE = 1
600 23:03:05.959423 LP45_APHY_COMB_EN = 1
601 23:03:05.962484 TX_ODT_DIS = 1
602 23:03:05.965892 NEW_8X_MODE = 1
603 23:03:05.968927 ===================================
604 23:03:05.972168 ===================================
605 23:03:05.975901 data_rate = 1600
606 23:03:05.978826 CKR = 1
607 23:03:05.981800 DQ_P2S_RATIO = 8
608 23:03:05.985588 ===================================
609 23:03:05.985686 CA_P2S_RATIO = 8
610 23:03:05.989001 DQ_CA_OPEN = 0
611 23:03:05.992436 DQ_SEMI_OPEN = 0
612 23:03:05.995729 CA_SEMI_OPEN = 0
613 23:03:05.999649 CA_FULL_RATE = 0
614 23:03:05.999751 DQ_CKDIV4_EN = 1
615 23:03:06.002558 CA_CKDIV4_EN = 1
616 23:03:06.005626 CA_PREDIV_EN = 0
617 23:03:06.009105 PH8_DLY = 0
618 23:03:06.012578 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
619 23:03:06.015685 DQ_AAMCK_DIV = 4
620 23:03:06.015773 CA_AAMCK_DIV = 4
621 23:03:06.019053 CA_ADMCK_DIV = 4
622 23:03:06.022797 DQ_TRACK_CA_EN = 0
623 23:03:06.025939 CA_PICK = 800
624 23:03:06.028913 CA_MCKIO = 800
625 23:03:06.032773 MCKIO_SEMI = 0
626 23:03:06.032854 PLL_FREQ = 3068
627 23:03:06.036216 DQ_UI_PI_RATIO = 32
628 23:03:06.040025 CA_UI_PI_RATIO = 0
629 23:03:06.044114 ===================================
630 23:03:06.047002 ===================================
631 23:03:06.050686 memory_type:LPDDR4
632 23:03:06.050773 GP_NUM : 10
633 23:03:06.054248 SRAM_EN : 1
634 23:03:06.054373 MD32_EN : 0
635 23:03:06.058137 ===================================
636 23:03:06.062042 [ANA_INIT] >>>>>>>>>>>>>>
637 23:03:06.062152 <<<<<< [CONFIGURE PHASE]: ANA_TX
638 23:03:06.065385 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
639 23:03:06.069348 ===================================
640 23:03:06.072443 data_rate = 1600,PCW = 0X7600
641 23:03:06.075834 ===================================
642 23:03:06.078987 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
643 23:03:06.085848 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
644 23:03:06.088918 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
645 23:03:06.095678 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
646 23:03:06.099120 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
647 23:03:06.102493 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
648 23:03:06.105712 [ANA_INIT] flow start
649 23:03:06.105831 [ANA_INIT] PLL >>>>>>>>
650 23:03:06.109128 [ANA_INIT] PLL <<<<<<<<
651 23:03:06.112351 [ANA_INIT] MIDPI >>>>>>>>
652 23:03:06.112440 [ANA_INIT] MIDPI <<<<<<<<
653 23:03:06.115515 [ANA_INIT] DLL >>>>>>>>
654 23:03:06.118779 [ANA_INIT] flow end
655 23:03:06.122515 ============ LP4 DIFF to SE enter ============
656 23:03:06.125944 ============ LP4 DIFF to SE exit ============
657 23:03:06.128954 [ANA_INIT] <<<<<<<<<<<<<
658 23:03:06.132099 [Flow] Enable top DCM control >>>>>
659 23:03:06.135668 [Flow] Enable top DCM control <<<<<
660 23:03:06.138912 Enable DLL master slave shuffle
661 23:03:06.142354 ==============================================================
662 23:03:06.145831 Gating Mode config
663 23:03:06.151930 ==============================================================
664 23:03:06.152037 Config description:
665 23:03:06.162089 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
666 23:03:06.168597 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
667 23:03:06.171938 SELPH_MODE 0: By rank 1: By Phase
668 23:03:06.178189 ==============================================================
669 23:03:06.181717 GAT_TRACK_EN = 1
670 23:03:06.185152 RX_GATING_MODE = 2
671 23:03:06.188241 RX_GATING_TRACK_MODE = 2
672 23:03:06.191674 SELPH_MODE = 1
673 23:03:06.195254 PICG_EARLY_EN = 1
674 23:03:06.198482 VALID_LAT_VALUE = 1
675 23:03:06.201707 ==============================================================
676 23:03:06.205052 Enter into Gating configuration >>>>
677 23:03:06.209051 Exit from Gating configuration <<<<
678 23:03:06.211743 Enter into DVFS_PRE_config >>>>>
679 23:03:06.225041 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
680 23:03:06.225176 Exit from DVFS_PRE_config <<<<<
681 23:03:06.228936 Enter into PICG configuration >>>>
682 23:03:06.231313 Exit from PICG configuration <<<<
683 23:03:06.234842 [RX_INPUT] configuration >>>>>
684 23:03:06.237970 [RX_INPUT] configuration <<<<<
685 23:03:06.244747 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
686 23:03:06.248228 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
687 23:03:06.254777 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
688 23:03:06.261273 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
689 23:03:06.267785 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
690 23:03:06.274681 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
691 23:03:06.278189 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
692 23:03:06.281244 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
693 23:03:06.284589 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
694 23:03:06.291276 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
695 23:03:06.294381 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
696 23:03:06.298089 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
697 23:03:06.301353 ===================================
698 23:03:06.304361 LPDDR4 DRAM CONFIGURATION
699 23:03:06.307881 ===================================
700 23:03:06.311488 EX_ROW_EN[0] = 0x0
701 23:03:06.311582 EX_ROW_EN[1] = 0x0
702 23:03:06.314029 LP4Y_EN = 0x0
703 23:03:06.314185 WORK_FSP = 0x0
704 23:03:06.317631 WL = 0x2
705 23:03:06.317716 RL = 0x2
706 23:03:06.320889 BL = 0x2
707 23:03:06.320974 RPST = 0x0
708 23:03:06.324057 RD_PRE = 0x0
709 23:03:06.324141 WR_PRE = 0x1
710 23:03:06.327992 WR_PST = 0x0
711 23:03:06.328077 DBI_WR = 0x0
712 23:03:06.331181 DBI_RD = 0x0
713 23:03:06.331273 OTF = 0x1
714 23:03:06.334056 ===================================
715 23:03:06.340817 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
716 23:03:06.343953 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
717 23:03:06.347828 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
718 23:03:06.350454 ===================================
719 23:03:06.354135 LPDDR4 DRAM CONFIGURATION
720 23:03:06.357464 ===================================
721 23:03:06.360293 EX_ROW_EN[0] = 0x10
722 23:03:06.360371 EX_ROW_EN[1] = 0x0
723 23:03:06.363935 LP4Y_EN = 0x0
724 23:03:06.364011 WORK_FSP = 0x0
725 23:03:06.367129 WL = 0x2
726 23:03:06.367204 RL = 0x2
727 23:03:06.370828 BL = 0x2
728 23:03:06.370911 RPST = 0x0
729 23:03:06.373911 RD_PRE = 0x0
730 23:03:06.373993 WR_PRE = 0x1
731 23:03:06.377614 WR_PST = 0x0
732 23:03:06.377693 DBI_WR = 0x0
733 23:03:06.380405 DBI_RD = 0x0
734 23:03:06.380480 OTF = 0x1
735 23:03:06.384469 ===================================
736 23:03:06.390614 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
737 23:03:06.394867 nWR fixed to 40
738 23:03:06.398734 [ModeRegInit_LP4] CH0 RK0
739 23:03:06.398817 [ModeRegInit_LP4] CH0 RK1
740 23:03:06.402021 [ModeRegInit_LP4] CH1 RK0
741 23:03:06.405081 [ModeRegInit_LP4] CH1 RK1
742 23:03:06.405161 match AC timing 13
743 23:03:06.411838 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
744 23:03:06.414735 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
745 23:03:06.418575 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
746 23:03:06.424852 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
747 23:03:06.428402 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
748 23:03:06.432044 [EMI DOE] emi_dcm 0
749 23:03:06.435026 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
750 23:03:06.435107 ==
751 23:03:06.438150 Dram Type= 6, Freq= 0, CH_0, rank 0
752 23:03:06.441693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
753 23:03:06.441776 ==
754 23:03:06.447955 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
755 23:03:06.454727 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
756 23:03:06.462863 [CA 0] Center 37 (7~68) winsize 62
757 23:03:06.466316 [CA 1] Center 37 (6~68) winsize 63
758 23:03:06.469327 [CA 2] Center 34 (4~65) winsize 62
759 23:03:06.472324 [CA 3] Center 35 (4~66) winsize 63
760 23:03:06.475654 [CA 4] Center 33 (3~64) winsize 62
761 23:03:06.479093 [CA 5] Center 33 (3~64) winsize 62
762 23:03:06.479175
763 23:03:06.482364 [CmdBusTrainingLP45] Vref(ca) range 1: 34
764 23:03:06.482441
765 23:03:06.485976 [CATrainingPosCal] consider 1 rank data
766 23:03:06.488946 u2DelayCellTimex100 = 270/100 ps
767 23:03:06.492438 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
768 23:03:06.499335 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
769 23:03:06.501964 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
770 23:03:06.505313 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
771 23:03:06.508560 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
772 23:03:06.512382 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
773 23:03:06.512467
774 23:03:06.515408 CA PerBit enable=1, Macro0, CA PI delay=33
775 23:03:06.515483
776 23:03:06.518834 [CBTSetCACLKResult] CA Dly = 33
777 23:03:06.522081 CS Dly: 5 (0~36)
778 23:03:06.522165 ==
779 23:03:06.525231 Dram Type= 6, Freq= 0, CH_0, rank 1
780 23:03:06.528402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
781 23:03:06.528494 ==
782 23:03:06.535309 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
783 23:03:06.538331 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
784 23:03:06.548679 [CA 0] Center 38 (7~69) winsize 63
785 23:03:06.552610 [CA 1] Center 37 (7~68) winsize 62
786 23:03:06.555731 [CA 2] Center 35 (4~66) winsize 63
787 23:03:06.558640 [CA 3] Center 35 (4~66) winsize 63
788 23:03:06.562243 [CA 4] Center 34 (3~65) winsize 63
789 23:03:06.565531 [CA 5] Center 33 (3~64) winsize 62
790 23:03:06.565612
791 23:03:06.569263 [CmdBusTrainingLP45] Vref(ca) range 1: 34
792 23:03:06.569337
793 23:03:06.571956 [CATrainingPosCal] consider 2 rank data
794 23:03:06.575258 u2DelayCellTimex100 = 270/100 ps
795 23:03:06.578806 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
796 23:03:06.585870 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
797 23:03:06.588852 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
798 23:03:06.591966 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
799 23:03:06.595333 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
800 23:03:06.598797 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
801 23:03:06.598881
802 23:03:06.601807 CA PerBit enable=1, Macro0, CA PI delay=33
803 23:03:06.601951
804 23:03:06.605466 [CBTSetCACLKResult] CA Dly = 33
805 23:03:06.605551 CS Dly: 6 (0~38)
806 23:03:06.608514
807 23:03:06.612420 ----->DramcWriteLeveling(PI) begin...
808 23:03:06.612507 ==
809 23:03:06.612572 Dram Type= 6, Freq= 0, CH_0, rank 0
810 23:03:06.619499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 23:03:06.619621 ==
812 23:03:06.623357 Write leveling (Byte 0): 31 => 31
813 23:03:06.623440 Write leveling (Byte 1): 27 => 27
814 23:03:06.627085 DramcWriteLeveling(PI) end<-----
815 23:03:06.627170
816 23:03:06.627233 ==
817 23:03:06.630037 Dram Type= 6, Freq= 0, CH_0, rank 0
818 23:03:06.636896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
819 23:03:06.637007 ==
820 23:03:06.637074 [Gating] SW mode calibration
821 23:03:06.643775 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
822 23:03:06.650924 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
823 23:03:06.654151 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
824 23:03:06.660248 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
825 23:03:06.663824 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
826 23:03:06.667351 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
827 23:03:06.673911 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 23:03:06.676865 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 23:03:06.680227 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 23:03:06.686847 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 23:03:06.690571 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 23:03:06.693490 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 23:03:06.697602 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
834 23:03:06.703480 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
835 23:03:06.707141 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
836 23:03:06.710435 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
837 23:03:06.716984 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
838 23:03:06.720479 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 23:03:06.723883 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
840 23:03:06.730095 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
841 23:03:06.733609 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
842 23:03:06.737544 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 23:03:06.743221 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 23:03:06.746681 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 23:03:06.750248 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
846 23:03:06.756991 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
847 23:03:06.760077 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
848 23:03:06.763109 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
849 23:03:06.769736 0 9 8 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (1 1)
850 23:03:06.773131 0 9 12 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
851 23:03:06.777063 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
852 23:03:06.783538 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
853 23:03:06.786382 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
854 23:03:06.790347 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
855 23:03:06.796234 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
856 23:03:06.799564 0 10 4 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
857 23:03:06.802959 0 10 8 | B1->B0 | 3333 2727 | 0 0 | (0 1) (1 1)
858 23:03:06.809904 0 10 12 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
859 23:03:06.812926 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 23:03:06.816151 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 23:03:06.823506 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 23:03:06.826421 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 23:03:06.829637 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 23:03:06.836226 0 11 4 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0)
865 23:03:06.839734 0 11 8 | B1->B0 | 2828 4141 | 1 1 | (0 0) (0 0)
866 23:03:06.843100 0 11 12 | B1->B0 | 3f3f 4646 | 0 0 | (1 1) (0 0)
867 23:03:06.849801 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
868 23:03:06.852830 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
869 23:03:06.856493 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
870 23:03:06.862773 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
871 23:03:06.866380 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
872 23:03:06.869852 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
873 23:03:06.875949 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
874 23:03:06.879445 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
875 23:03:06.882768 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 23:03:06.886449 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 23:03:06.892813 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 23:03:06.896164 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 23:03:06.899605 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 23:03:06.906134 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 23:03:06.908983 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 23:03:06.912666 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 23:03:06.919167 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
884 23:03:06.922197 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
885 23:03:06.925946 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
886 23:03:06.932204 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
887 23:03:06.936272 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
888 23:03:06.939507 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
889 23:03:06.945651 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
890 23:03:06.948906 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
891 23:03:06.952395 Total UI for P1: 0, mck2ui 16
892 23:03:06.955822 best dqsien dly found for B0: ( 0, 14, 6)
893 23:03:06.958946 Total UI for P1: 0, mck2ui 16
894 23:03:06.962517 best dqsien dly found for B1: ( 0, 14, 6)
895 23:03:06.965378 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
896 23:03:06.968874 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
897 23:03:06.968971
898 23:03:06.971916 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
899 23:03:06.976214 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
900 23:03:06.978815 [Gating] SW calibration Done
901 23:03:06.978906 ==
902 23:03:06.982036 Dram Type= 6, Freq= 0, CH_0, rank 0
903 23:03:06.985123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
904 23:03:06.989023 ==
905 23:03:06.989110 RX Vref Scan: 0
906 23:03:06.989183
907 23:03:06.992335 RX Vref 0 -> 0, step: 1
908 23:03:06.992409
909 23:03:06.992476 RX Delay -130 -> 252, step: 16
910 23:03:06.999294 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
911 23:03:07.002466 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
912 23:03:07.006067 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
913 23:03:07.009096 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
914 23:03:07.012613 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
915 23:03:07.018717 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
916 23:03:07.022496 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
917 23:03:07.025532 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
918 23:03:07.028702 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
919 23:03:07.035483 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
920 23:03:07.038561 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
921 23:03:07.041861 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
922 23:03:07.045865 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
923 23:03:07.048705 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
924 23:03:07.055314 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
925 23:03:07.058526 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
926 23:03:07.058619 ==
927 23:03:07.062203 Dram Type= 6, Freq= 0, CH_0, rank 0
928 23:03:07.065374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
929 23:03:07.065464 ==
930 23:03:07.068697 DQS Delay:
931 23:03:07.068779 DQS0 = 0, DQS1 = 0
932 23:03:07.068844 DQM Delay:
933 23:03:07.072009 DQM0 = 87, DQM1 = 75
934 23:03:07.072084 DQ Delay:
935 23:03:07.075293 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
936 23:03:07.078148 DQ4 =93, DQ5 =69, DQ6 =101, DQ7 =93
937 23:03:07.081929 DQ8 =69, DQ9 =53, DQ10 =69, DQ11 =69
938 23:03:07.085030 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
939 23:03:07.085131
940 23:03:07.085196
941 23:03:07.085256 ==
942 23:03:07.088501 Dram Type= 6, Freq= 0, CH_0, rank 0
943 23:03:07.095226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
944 23:03:07.095344 ==
945 23:03:07.095422
946 23:03:07.095486
947 23:03:07.095544 TX Vref Scan disable
948 23:03:07.099230 == TX Byte 0 ==
949 23:03:07.101827 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
950 23:03:07.108717 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
951 23:03:07.108832 == TX Byte 1 ==
952 23:03:07.112207 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
953 23:03:07.118792 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
954 23:03:07.118893 ==
955 23:03:07.122359 Dram Type= 6, Freq= 0, CH_0, rank 0
956 23:03:07.125591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
957 23:03:07.125668 ==
958 23:03:07.138389 TX Vref=22, minBit 0, minWin=26, winSum=436
959 23:03:07.141196 TX Vref=24, minBit 0, minWin=27, winSum=441
960 23:03:07.144727 TX Vref=26, minBit 1, minWin=27, winSum=444
961 23:03:07.147824 TX Vref=28, minBit 2, minWin=27, winSum=449
962 23:03:07.151071 TX Vref=30, minBit 0, minWin=28, winSum=454
963 23:03:07.158171 TX Vref=32, minBit 2, minWin=27, winSum=447
964 23:03:07.161172 [TxChooseVref] Worse bit 0, Min win 28, Win sum 454, Final Vref 30
965 23:03:07.161270
966 23:03:07.164369 Final TX Range 1 Vref 30
967 23:03:07.164457
968 23:03:07.164524 ==
969 23:03:07.167838 Dram Type= 6, Freq= 0, CH_0, rank 0
970 23:03:07.171636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
971 23:03:07.171733 ==
972 23:03:07.174234
973 23:03:07.174386
974 23:03:07.174478 TX Vref Scan disable
975 23:03:07.178145 == TX Byte 0 ==
976 23:03:07.181554 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
977 23:03:07.184910 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
978 23:03:07.188322 == TX Byte 1 ==
979 23:03:07.191737 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
980 23:03:07.198032 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
981 23:03:07.198138
982 23:03:07.198209 [DATLAT]
983 23:03:07.198303 Freq=800, CH0 RK0
984 23:03:07.198379
985 23:03:07.201098 DATLAT Default: 0xa
986 23:03:07.201181 0, 0xFFFF, sum = 0
987 23:03:07.204556 1, 0xFFFF, sum = 0
988 23:03:07.204650 2, 0xFFFF, sum = 0
989 23:03:07.207837 3, 0xFFFF, sum = 0
990 23:03:07.211078 4, 0xFFFF, sum = 0
991 23:03:07.211172 5, 0xFFFF, sum = 0
992 23:03:07.214740 6, 0xFFFF, sum = 0
993 23:03:07.214838 7, 0xFFFF, sum = 0
994 23:03:07.218001 8, 0xFFFF, sum = 0
995 23:03:07.218095 9, 0x0, sum = 1
996 23:03:07.221430 10, 0x0, sum = 2
997 23:03:07.221549 11, 0x0, sum = 3
998 23:03:07.221647 12, 0x0, sum = 4
999 23:03:07.224692 best_step = 10
1000 23:03:07.224778
1001 23:03:07.224866 ==
1002 23:03:07.227940 Dram Type= 6, Freq= 0, CH_0, rank 0
1003 23:03:07.231241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1004 23:03:07.231363 ==
1005 23:03:07.234725 RX Vref Scan: 1
1006 23:03:07.234810
1007 23:03:07.237705 Set Vref Range= 32 -> 127
1008 23:03:07.237806
1009 23:03:07.237890 RX Vref 32 -> 127, step: 1
1010 23:03:07.237953
1011 23:03:07.241230 RX Delay -111 -> 252, step: 8
1012 23:03:07.241343
1013 23:03:07.244316 Set Vref, RX VrefLevel [Byte0]: 32
1014 23:03:07.247623 [Byte1]: 32
1015 23:03:07.250860
1016 23:03:07.250959 Set Vref, RX VrefLevel [Byte0]: 33
1017 23:03:07.254493 [Byte1]: 33
1018 23:03:07.258461
1019 23:03:07.258555 Set Vref, RX VrefLevel [Byte0]: 34
1020 23:03:07.262066 [Byte1]: 34
1021 23:03:07.266055
1022 23:03:07.266182 Set Vref, RX VrefLevel [Byte0]: 35
1023 23:03:07.269343 [Byte1]: 35
1024 23:03:07.273750
1025 23:03:07.273849 Set Vref, RX VrefLevel [Byte0]: 36
1026 23:03:07.277380 [Byte1]: 36
1027 23:03:07.282134
1028 23:03:07.282234 Set Vref, RX VrefLevel [Byte0]: 37
1029 23:03:07.285534 [Byte1]: 37
1030 23:03:07.289571
1031 23:03:07.289665 Set Vref, RX VrefLevel [Byte0]: 38
1032 23:03:07.293300 [Byte1]: 38
1033 23:03:07.296741
1034 23:03:07.296834 Set Vref, RX VrefLevel [Byte0]: 39
1035 23:03:07.300430 [Byte1]: 39
1036 23:03:07.305078
1037 23:03:07.305180 Set Vref, RX VrefLevel [Byte0]: 40
1038 23:03:07.308333 [Byte1]: 40
1039 23:03:07.312683
1040 23:03:07.312785 Set Vref, RX VrefLevel [Byte0]: 41
1041 23:03:07.315971 [Byte1]: 41
1042 23:03:07.319773
1043 23:03:07.319968 Set Vref, RX VrefLevel [Byte0]: 42
1044 23:03:07.322872 [Byte1]: 42
1045 23:03:07.327004
1046 23:03:07.327102 Set Vref, RX VrefLevel [Byte0]: 43
1047 23:03:07.330619 [Byte1]: 43
1048 23:03:07.334644
1049 23:03:07.334736 Set Vref, RX VrefLevel [Byte0]: 44
1050 23:03:07.338782 [Byte1]: 44
1051 23:03:07.342762
1052 23:03:07.342849 Set Vref, RX VrefLevel [Byte0]: 45
1053 23:03:07.345671 [Byte1]: 45
1054 23:03:07.350018
1055 23:03:07.350115 Set Vref, RX VrefLevel [Byte0]: 46
1056 23:03:07.354085 [Byte1]: 46
1057 23:03:07.358440
1058 23:03:07.358533 Set Vref, RX VrefLevel [Byte0]: 47
1059 23:03:07.361257 [Byte1]: 47
1060 23:03:07.365288
1061 23:03:07.365403 Set Vref, RX VrefLevel [Byte0]: 48
1062 23:03:07.368910 [Byte1]: 48
1063 23:03:07.373009
1064 23:03:07.373095 Set Vref, RX VrefLevel [Byte0]: 49
1065 23:03:07.376101 [Byte1]: 49
1066 23:03:07.381145
1067 23:03:07.381242 Set Vref, RX VrefLevel [Byte0]: 50
1068 23:03:07.384286 [Byte1]: 50
1069 23:03:07.388724
1070 23:03:07.388821 Set Vref, RX VrefLevel [Byte0]: 51
1071 23:03:07.391878 [Byte1]: 51
1072 23:03:07.395852
1073 23:03:07.395950 Set Vref, RX VrefLevel [Byte0]: 52
1074 23:03:07.400062 [Byte1]: 52
1075 23:03:07.403773
1076 23:03:07.403878 Set Vref, RX VrefLevel [Byte0]: 53
1077 23:03:07.407096 [Byte1]: 53
1078 23:03:07.411494
1079 23:03:07.411610 Set Vref, RX VrefLevel [Byte0]: 54
1080 23:03:07.414439 [Byte1]: 54
1081 23:03:07.419081
1082 23:03:07.419173 Set Vref, RX VrefLevel [Byte0]: 55
1083 23:03:07.422389 [Byte1]: 55
1084 23:03:07.426759
1085 23:03:07.426854 Set Vref, RX VrefLevel [Byte0]: 56
1086 23:03:07.429654 [Byte1]: 56
1087 23:03:07.434196
1088 23:03:07.434301 Set Vref, RX VrefLevel [Byte0]: 57
1089 23:03:07.437710 [Byte1]: 57
1090 23:03:07.442404
1091 23:03:07.442500 Set Vref, RX VrefLevel [Byte0]: 58
1092 23:03:07.445232 [Byte1]: 58
1093 23:03:07.449445
1094 23:03:07.449571 Set Vref, RX VrefLevel [Byte0]: 59
1095 23:03:07.453009 [Byte1]: 59
1096 23:03:07.457488
1097 23:03:07.457599 Set Vref, RX VrefLevel [Byte0]: 60
1098 23:03:07.460652 [Byte1]: 60
1099 23:03:07.465461
1100 23:03:07.465567 Set Vref, RX VrefLevel [Byte0]: 61
1101 23:03:07.468210 [Byte1]: 61
1102 23:03:07.472873
1103 23:03:07.472985 Set Vref, RX VrefLevel [Byte0]: 62
1104 23:03:07.476028 [Byte1]: 62
1105 23:03:07.480032
1106 23:03:07.480124 Set Vref, RX VrefLevel [Byte0]: 63
1107 23:03:07.483186 [Byte1]: 63
1108 23:03:07.488005
1109 23:03:07.488104 Set Vref, RX VrefLevel [Byte0]: 64
1110 23:03:07.490908 [Byte1]: 64
1111 23:03:07.495627
1112 23:03:07.495717 Set Vref, RX VrefLevel [Byte0]: 65
1113 23:03:07.499676 [Byte1]: 65
1114 23:03:07.503375
1115 23:03:07.503495 Set Vref, RX VrefLevel [Byte0]: 66
1116 23:03:07.506826 [Byte1]: 66
1117 23:03:07.510789
1118 23:03:07.510880 Set Vref, RX VrefLevel [Byte0]: 67
1119 23:03:07.514131 [Byte1]: 67
1120 23:03:07.518531
1121 23:03:07.518622 Set Vref, RX VrefLevel [Byte0]: 68
1122 23:03:07.521584 [Byte1]: 68
1123 23:03:07.526275
1124 23:03:07.526371 Set Vref, RX VrefLevel [Byte0]: 69
1125 23:03:07.529464 [Byte1]: 69
1126 23:03:07.533851
1127 23:03:07.533978 Set Vref, RX VrefLevel [Byte0]: 70
1128 23:03:07.536820 [Byte1]: 70
1129 23:03:07.541703
1130 23:03:07.541797 Set Vref, RX VrefLevel [Byte0]: 71
1131 23:03:07.544454 [Byte1]: 71
1132 23:03:07.549001
1133 23:03:07.549123 Set Vref, RX VrefLevel [Byte0]: 72
1134 23:03:07.552139 [Byte1]: 72
1135 23:03:07.556363
1136 23:03:07.556459 Set Vref, RX VrefLevel [Byte0]: 73
1137 23:03:07.560411 [Byte1]: 73
1138 23:03:07.564951
1139 23:03:07.565043 Final RX Vref Byte 0 = 57 to rank0
1140 23:03:07.567456 Final RX Vref Byte 1 = 60 to rank0
1141 23:03:07.570953 Final RX Vref Byte 0 = 57 to rank1
1142 23:03:07.574156 Final RX Vref Byte 1 = 60 to rank1==
1143 23:03:07.577210 Dram Type= 6, Freq= 0, CH_0, rank 0
1144 23:03:07.584333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1145 23:03:07.584469 ==
1146 23:03:07.584537 DQS Delay:
1147 23:03:07.584604 DQS0 = 0, DQS1 = 0
1148 23:03:07.587569 DQM Delay:
1149 23:03:07.587659 DQM0 = 88, DQM1 = 76
1150 23:03:07.591141 DQ Delay:
1151 23:03:07.594039 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1152 23:03:07.597475 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1153 23:03:07.597584 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =72
1154 23:03:07.603956 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1155 23:03:07.604119
1156 23:03:07.604216
1157 23:03:07.610494 [DQSOSCAuto] RK0, (LSB)MR18= 0x2a24, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 399 ps
1158 23:03:07.614902 CH0 RK0: MR19=606, MR18=2A24
1159 23:03:07.620715 CH0_RK0: MR19=0x606, MR18=0x2A24, DQSOSC=399, MR23=63, INC=92, DEC=61
1160 23:03:07.620823
1161 23:03:07.624092 ----->DramcWriteLeveling(PI) begin...
1162 23:03:07.624182 ==
1163 23:03:07.627134 Dram Type= 6, Freq= 0, CH_0, rank 1
1164 23:03:07.630849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1165 23:03:07.630973 ==
1166 23:03:07.634279 Write leveling (Byte 0): 32 => 32
1167 23:03:07.637177 Write leveling (Byte 1): 27 => 27
1168 23:03:07.640808 DramcWriteLeveling(PI) end<-----
1169 23:03:07.640900
1170 23:03:07.640975 ==
1171 23:03:07.643974 Dram Type= 6, Freq= 0, CH_0, rank 1
1172 23:03:07.647256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1173 23:03:07.647343 ==
1174 23:03:07.650812 [Gating] SW mode calibration
1175 23:03:07.657297 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1176 23:03:07.663649 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1177 23:03:07.667498 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1178 23:03:07.670436 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1179 23:03:07.676981 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1180 23:03:07.721431 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 23:03:07.721975 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 23:03:07.722059 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 23:03:07.722318 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 23:03:07.722662 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 23:03:07.723115 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 23:03:07.723544 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 23:03:07.723636 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 23:03:07.724006 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 23:03:07.724820 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 23:03:07.749340 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 23:03:07.749730 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 23:03:07.749823 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 23:03:07.750168 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1194 23:03:07.750542 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1195 23:03:07.751637 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1196 23:03:07.754145 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 23:03:07.757445 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 23:03:07.760730 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 23:03:07.763776 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 23:03:07.767257 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 23:03:07.773878 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 23:03:07.777222 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 23:03:07.780381 0 9 8 | B1->B0 | 2423 3232 | 1 0 | (0 0) (0 0)
1204 23:03:07.786936 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1205 23:03:07.790497 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1206 23:03:07.793702 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1207 23:03:07.800503 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1208 23:03:07.803817 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1209 23:03:07.806910 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1210 23:03:07.813507 0 10 4 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
1211 23:03:07.817020 0 10 8 | B1->B0 | 2f2f 2323 | 0 0 | (1 0) (1 0)
1212 23:03:07.820259 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 23:03:07.826956 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 23:03:07.830638 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 23:03:07.833874 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 23:03:07.839865 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 23:03:07.843257 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 23:03:07.846743 0 11 4 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
1219 23:03:07.853738 0 11 8 | B1->B0 | 3232 4646 | 0 0 | (0 0) (0 0)
1220 23:03:07.856339 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1221 23:03:07.860377 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1222 23:03:07.863787 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1223 23:03:07.871310 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1224 23:03:07.875668 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1225 23:03:07.878884 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1226 23:03:07.881993 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1227 23:03:07.889048 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1228 23:03:07.892438 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1229 23:03:07.895779 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1230 23:03:07.899222 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1231 23:03:07.906232 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1232 23:03:07.909249 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1233 23:03:07.912599 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1234 23:03:07.919103 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1235 23:03:07.922350 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1236 23:03:07.925880 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1237 23:03:07.932334 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1238 23:03:07.936088 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1239 23:03:07.939045 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1240 23:03:07.945774 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1241 23:03:07.948629 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1242 23:03:07.952320 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1243 23:03:07.958769 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1244 23:03:07.958880 Total UI for P1: 0, mck2ui 16
1245 23:03:07.965670 best dqsien dly found for B0: ( 0, 14, 4)
1246 23:03:07.965770 Total UI for P1: 0, mck2ui 16
1247 23:03:07.971741 best dqsien dly found for B1: ( 0, 14, 6)
1248 23:03:07.975104 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1249 23:03:07.978759 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1250 23:03:07.978854
1251 23:03:07.981857 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1252 23:03:07.985113 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1253 23:03:07.988533 [Gating] SW calibration Done
1254 23:03:07.988647 ==
1255 23:03:07.991702 Dram Type= 6, Freq= 0, CH_0, rank 1
1256 23:03:07.994846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1257 23:03:07.994928 ==
1258 23:03:07.998352 RX Vref Scan: 0
1259 23:03:07.998431
1260 23:03:07.998494 RX Vref 0 -> 0, step: 1
1261 23:03:07.998554
1262 23:03:08.001839 RX Delay -130 -> 252, step: 16
1263 23:03:08.005207 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1264 23:03:08.011984 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1265 23:03:08.014858 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1266 23:03:08.018193 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1267 23:03:08.021636 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1268 23:03:08.025194 iDelay=206, Bit 5, Center 69 (-50 ~ 189) 240
1269 23:03:08.031758 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1270 23:03:08.034701 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1271 23:03:08.037950 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1272 23:03:08.041350 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1273 23:03:08.044775 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1274 23:03:08.051591 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1275 23:03:08.054815 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1276 23:03:08.058311 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1277 23:03:08.061668 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1278 23:03:08.068338 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1279 23:03:08.068451 ==
1280 23:03:08.071053 Dram Type= 6, Freq= 0, CH_0, rank 1
1281 23:03:08.074609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1282 23:03:08.074707 ==
1283 23:03:08.074775 DQS Delay:
1284 23:03:08.077750 DQS0 = 0, DQS1 = 0
1285 23:03:08.077837 DQM Delay:
1286 23:03:08.081240 DQM0 = 85, DQM1 = 77
1287 23:03:08.081326 DQ Delay:
1288 23:03:08.084927 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1289 23:03:08.088325 DQ4 =93, DQ5 =69, DQ6 =93, DQ7 =93
1290 23:03:08.090949 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1291 23:03:08.094589 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1292 23:03:08.094681
1293 23:03:08.094747
1294 23:03:08.094807 ==
1295 23:03:08.097923 Dram Type= 6, Freq= 0, CH_0, rank 1
1296 23:03:08.101399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1297 23:03:08.101488 ==
1298 23:03:08.101555
1299 23:03:08.101616
1300 23:03:08.104411 TX Vref Scan disable
1301 23:03:08.107768 == TX Byte 0 ==
1302 23:03:08.110990 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1303 23:03:08.114676 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1304 23:03:08.117764 == TX Byte 1 ==
1305 23:03:08.121512 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1306 23:03:08.124544 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1307 23:03:08.124642 ==
1308 23:03:08.127891 Dram Type= 6, Freq= 0, CH_0, rank 1
1309 23:03:08.134235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1310 23:03:08.134381 ==
1311 23:03:08.147035 TX Vref=22, minBit 1, minWin=27, winSum=441
1312 23:03:08.149969 TX Vref=24, minBit 2, minWin=27, winSum=447
1313 23:03:08.153447 TX Vref=26, minBit 1, minWin=27, winSum=449
1314 23:03:08.156805 TX Vref=28, minBit 2, minWin=27, winSum=451
1315 23:03:08.159565 TX Vref=30, minBit 1, minWin=27, winSum=449
1316 23:03:08.166611 TX Vref=32, minBit 1, minWin=27, winSum=448
1317 23:03:08.169925 [TxChooseVref] Worse bit 2, Min win 27, Win sum 451, Final Vref 28
1318 23:03:08.170031
1319 23:03:08.173038 Final TX Range 1 Vref 28
1320 23:03:08.173124
1321 23:03:08.173191 ==
1322 23:03:08.176155 Dram Type= 6, Freq= 0, CH_0, rank 1
1323 23:03:08.179702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1324 23:03:08.182728 ==
1325 23:03:08.182822
1326 23:03:08.182888
1327 23:03:08.182949 TX Vref Scan disable
1328 23:03:08.186560 == TX Byte 0 ==
1329 23:03:08.190075 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1330 23:03:08.196347 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1331 23:03:08.196457 == TX Byte 1 ==
1332 23:03:08.199712 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1333 23:03:08.206431 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1334 23:03:08.206542
1335 23:03:08.206610 [DATLAT]
1336 23:03:08.206671 Freq=800, CH0 RK1
1337 23:03:08.206730
1338 23:03:08.209961 DATLAT Default: 0xa
1339 23:03:08.210061 0, 0xFFFF, sum = 0
1340 23:03:08.213258 1, 0xFFFF, sum = 0
1341 23:03:08.213348 2, 0xFFFF, sum = 0
1342 23:03:08.216283 3, 0xFFFF, sum = 0
1343 23:03:08.219641 4, 0xFFFF, sum = 0
1344 23:03:08.219730 5, 0xFFFF, sum = 0
1345 23:03:08.222993 6, 0xFFFF, sum = 0
1346 23:03:08.223083 7, 0xFFFF, sum = 0
1347 23:03:08.226203 8, 0xFFFF, sum = 0
1348 23:03:08.226319 9, 0x0, sum = 1
1349 23:03:08.229270 10, 0x0, sum = 2
1350 23:03:08.229353 11, 0x0, sum = 3
1351 23:03:08.229417 12, 0x0, sum = 4
1352 23:03:08.232719 best_step = 10
1353 23:03:08.232801
1354 23:03:08.232864 ==
1355 23:03:08.236018 Dram Type= 6, Freq= 0, CH_0, rank 1
1356 23:03:08.239874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1357 23:03:08.239964 ==
1358 23:03:08.243054 RX Vref Scan: 0
1359 23:03:08.243139
1360 23:03:08.246460 RX Vref 0 -> 0, step: 1
1361 23:03:08.246546
1362 23:03:08.246612 RX Delay -95 -> 252, step: 8
1363 23:03:08.253030 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1364 23:03:08.256469 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1365 23:03:08.259931 iDelay=209, Bit 2, Center 84 (-23 ~ 192) 216
1366 23:03:08.263027 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1367 23:03:08.266656 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1368 23:03:08.273490 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1369 23:03:08.276989 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1370 23:03:08.280022 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1371 23:03:08.283251 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1372 23:03:08.286569 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1373 23:03:08.293191 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1374 23:03:08.296394 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
1375 23:03:08.299885 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1376 23:03:08.302872 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1377 23:03:08.306977 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1378 23:03:08.313073 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1379 23:03:08.313178 ==
1380 23:03:08.316886 Dram Type= 6, Freq= 0, CH_0, rank 1
1381 23:03:08.319941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1382 23:03:08.320025 ==
1383 23:03:08.320087 DQS Delay:
1384 23:03:08.323700 DQS0 = 0, DQS1 = 0
1385 23:03:08.323783 DQM Delay:
1386 23:03:08.327164 DQM0 = 87, DQM1 = 76
1387 23:03:08.327240 DQ Delay:
1388 23:03:08.329761 DQ0 =84, DQ1 =92, DQ2 =84, DQ3 =80
1389 23:03:08.333083 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1390 23:03:08.336213 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =72
1391 23:03:08.339392 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1392 23:03:08.339471
1393 23:03:08.339532
1394 23:03:08.349575 [DQSOSCAuto] RK1, (LSB)MR18= 0x2a27, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 399 ps
1395 23:03:08.349690 CH0 RK1: MR19=606, MR18=2A27
1396 23:03:08.356047 CH0_RK1: MR19=0x606, MR18=0x2A27, DQSOSC=399, MR23=63, INC=92, DEC=61
1397 23:03:08.359297 [RxdqsGatingPostProcess] freq 800
1398 23:03:08.365867 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1399 23:03:08.369053 Pre-setting of DQS Precalculation
1400 23:03:08.372496 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1401 23:03:08.372591 ==
1402 23:03:08.375433 Dram Type= 6, Freq= 0, CH_1, rank 0
1403 23:03:08.382360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1404 23:03:08.382470 ==
1405 23:03:08.386420 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1406 23:03:08.392103 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1407 23:03:08.401644 [CA 0] Center 36 (6~67) winsize 62
1408 23:03:08.405098 [CA 1] Center 37 (6~68) winsize 63
1409 23:03:08.408236 [CA 2] Center 34 (4~65) winsize 62
1410 23:03:08.411429 [CA 3] Center 34 (4~65) winsize 62
1411 23:03:08.415026 [CA 4] Center 34 (4~65) winsize 62
1412 23:03:08.418231 [CA 5] Center 34 (3~65) winsize 63
1413 23:03:08.418325
1414 23:03:08.421398 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1415 23:03:08.421482
1416 23:03:08.425037 [CATrainingPosCal] consider 1 rank data
1417 23:03:08.428413 u2DelayCellTimex100 = 270/100 ps
1418 23:03:08.431592 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1419 23:03:08.434845 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1420 23:03:08.441361 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1421 23:03:08.444858 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1422 23:03:08.448467 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1423 23:03:08.451393 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1424 23:03:08.451487
1425 23:03:08.454765 CA PerBit enable=1, Macro0, CA PI delay=34
1426 23:03:08.454857
1427 23:03:08.457857 [CBTSetCACLKResult] CA Dly = 34
1428 23:03:08.457935 CS Dly: 4 (0~35)
1429 23:03:08.461144 ==
1430 23:03:08.461218 Dram Type= 6, Freq= 0, CH_1, rank 1
1431 23:03:08.468085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1432 23:03:08.468167 ==
1433 23:03:08.470866 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1434 23:03:08.477917 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1435 23:03:08.487992 [CA 0] Center 36 (6~67) winsize 62
1436 23:03:08.491109 [CA 1] Center 36 (6~67) winsize 62
1437 23:03:08.494100 [CA 2] Center 34 (4~65) winsize 62
1438 23:03:08.497857 [CA 3] Center 34 (3~65) winsize 63
1439 23:03:08.501141 [CA 4] Center 34 (3~65) winsize 63
1440 23:03:08.504090 [CA 5] Center 33 (3~64) winsize 62
1441 23:03:08.504165
1442 23:03:08.507804 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1443 23:03:08.507889
1444 23:03:08.511202 [CATrainingPosCal] consider 2 rank data
1445 23:03:08.514068 u2DelayCellTimex100 = 270/100 ps
1446 23:03:08.517313 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1447 23:03:08.520904 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1448 23:03:08.527795 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1449 23:03:08.531519 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1450 23:03:08.534962 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1451 23:03:08.539085 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1452 23:03:08.539168
1453 23:03:08.543338 CA PerBit enable=1, Macro0, CA PI delay=33
1454 23:03:08.543421
1455 23:03:08.543487 [CBTSetCACLKResult] CA Dly = 33
1456 23:03:08.546620 CS Dly: 5 (0~37)
1457 23:03:08.546702
1458 23:03:08.549848 ----->DramcWriteLeveling(PI) begin...
1459 23:03:08.549931 ==
1460 23:03:08.553881 Dram Type= 6, Freq= 0, CH_1, rank 0
1461 23:03:08.557185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1462 23:03:08.557268 ==
1463 23:03:08.560925 Write leveling (Byte 0): 26 => 26
1464 23:03:08.564276 Write leveling (Byte 1): 27 => 27
1465 23:03:08.568329 DramcWriteLeveling(PI) end<-----
1466 23:03:08.568413
1467 23:03:08.568478 ==
1468 23:03:08.570935 Dram Type= 6, Freq= 0, CH_1, rank 0
1469 23:03:08.573891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1470 23:03:08.573976 ==
1471 23:03:08.577314 [Gating] SW mode calibration
1472 23:03:08.584427 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1473 23:03:08.590936 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1474 23:03:08.593843 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1475 23:03:08.597389 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1476 23:03:08.600841 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1477 23:03:08.607832 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 23:03:08.610480 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 23:03:08.613747 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 23:03:08.620730 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 23:03:08.623846 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 23:03:08.627207 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 23:03:08.633762 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 23:03:08.637322 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 23:03:08.640432 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 23:03:08.647134 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 23:03:08.650937 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 23:03:08.653703 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 23:03:08.660310 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 23:03:08.664360 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1491 23:03:08.667334 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1492 23:03:08.673581 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 23:03:08.677076 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 23:03:08.680071 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 23:03:08.686976 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 23:03:08.690013 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 23:03:08.693451 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 23:03:08.700187 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 23:03:08.703496 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1500 23:03:08.706466 0 9 8 | B1->B0 | 2f2e 3333 | 1 1 | (0 0) (1 1)
1501 23:03:08.713321 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1502 23:03:08.716844 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1503 23:03:08.720147 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1504 23:03:08.726686 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1505 23:03:08.730304 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1506 23:03:08.733412 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1507 23:03:08.739902 0 10 4 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
1508 23:03:08.743714 0 10 8 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1509 23:03:08.746499 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 23:03:08.753232 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 23:03:08.756901 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 23:03:08.760367 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 23:03:08.763460 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 23:03:08.769890 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 23:03:08.773775 0 11 4 | B1->B0 | 2525 2e2e | 0 1 | (0 0) (0 0)
1516 23:03:08.776533 0 11 8 | B1->B0 | 4040 4444 | 1 1 | (0 0) (0 0)
1517 23:03:08.783109 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1518 23:03:08.786423 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1519 23:03:08.789861 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1520 23:03:08.796260 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1521 23:03:08.799984 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1522 23:03:08.803320 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1523 23:03:08.809627 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1524 23:03:08.812837 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1525 23:03:08.816398 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1526 23:03:08.822992 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1527 23:03:08.826282 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1528 23:03:08.829885 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1529 23:03:08.837308 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1530 23:03:08.839641 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1531 23:03:08.842907 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1532 23:03:08.849756 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1533 23:03:08.852987 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1534 23:03:08.856270 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1535 23:03:08.863999 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1536 23:03:08.866611 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1537 23:03:08.869783 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1538 23:03:08.873068 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1539 23:03:08.879868 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1540 23:03:08.882891 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1541 23:03:08.887323 Total UI for P1: 0, mck2ui 16
1542 23:03:08.889938 best dqsien dly found for B0: ( 0, 14, 4)
1543 23:03:08.893184 Total UI for P1: 0, mck2ui 16
1544 23:03:08.896178 best dqsien dly found for B1: ( 0, 14, 4)
1545 23:03:08.899404 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1546 23:03:08.902855 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1547 23:03:08.902940
1548 23:03:08.906153 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1549 23:03:08.909243 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1550 23:03:08.912984 [Gating] SW calibration Done
1551 23:03:08.913070 ==
1552 23:03:08.916068 Dram Type= 6, Freq= 0, CH_1, rank 0
1553 23:03:08.922683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1554 23:03:08.922799 ==
1555 23:03:08.922888 RX Vref Scan: 0
1556 23:03:08.922971
1557 23:03:08.926358 RX Vref 0 -> 0, step: 1
1558 23:03:08.926466
1559 23:03:08.929705 RX Delay -130 -> 252, step: 16
1560 23:03:08.932526 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1561 23:03:08.935916 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1562 23:03:08.939461 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1563 23:03:08.946212 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1564 23:03:08.949019 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1565 23:03:08.952602 iDelay=222, Bit 5, Center 93 (-18 ~ 205) 224
1566 23:03:08.956072 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1567 23:03:08.959478 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1568 23:03:08.962847 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1569 23:03:08.969170 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1570 23:03:08.972619 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1571 23:03:08.975690 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1572 23:03:08.979146 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1573 23:03:08.985459 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1574 23:03:08.989338 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1575 23:03:08.992431 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1576 23:03:08.992518 ==
1577 23:03:08.995870 Dram Type= 6, Freq= 0, CH_1, rank 0
1578 23:03:08.998780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1579 23:03:08.998866 ==
1580 23:03:09.002486 DQS Delay:
1581 23:03:09.002572 DQS0 = 0, DQS1 = 0
1582 23:03:09.005331 DQM Delay:
1583 23:03:09.005435 DQM0 = 86, DQM1 = 83
1584 23:03:09.005518 DQ Delay:
1585 23:03:09.009189 DQ0 =93, DQ1 =77, DQ2 =69, DQ3 =85
1586 23:03:09.011860 DQ4 =85, DQ5 =93, DQ6 =101, DQ7 =85
1587 23:03:09.015625 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1588 23:03:09.018686 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1589 23:03:09.018773
1590 23:03:09.021902
1591 23:03:09.021987 ==
1592 23:03:09.025382 Dram Type= 6, Freq= 0, CH_1, rank 0
1593 23:03:09.028648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1594 23:03:09.028735 ==
1595 23:03:09.028821
1596 23:03:09.028901
1597 23:03:09.032077 TX Vref Scan disable
1598 23:03:09.032223 == TX Byte 0 ==
1599 23:03:09.038762 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1600 23:03:09.041710 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1601 23:03:09.041795 == TX Byte 1 ==
1602 23:03:09.048596 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1603 23:03:09.052080 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1604 23:03:09.052168 ==
1605 23:03:09.055505 Dram Type= 6, Freq= 0, CH_1, rank 0
1606 23:03:09.058272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1607 23:03:09.058377 ==
1608 23:03:09.072167 TX Vref=22, minBit 2, minWin=27, winSum=443
1609 23:03:09.075180 TX Vref=24, minBit 3, minWin=27, winSum=446
1610 23:03:09.078813 TX Vref=26, minBit 5, minWin=27, winSum=452
1611 23:03:09.081774 TX Vref=28, minBit 4, minWin=27, winSum=453
1612 23:03:09.085203 TX Vref=30, minBit 5, minWin=27, winSum=454
1613 23:03:09.091620 TX Vref=32, minBit 1, minWin=27, winSum=453
1614 23:03:09.095003 [TxChooseVref] Worse bit 5, Min win 27, Win sum 454, Final Vref 30
1615 23:03:09.095105
1616 23:03:09.098496 Final TX Range 1 Vref 30
1617 23:03:09.098580
1618 23:03:09.098645 ==
1619 23:03:09.101814 Dram Type= 6, Freq= 0, CH_1, rank 0
1620 23:03:09.104849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1621 23:03:09.104933 ==
1622 23:03:09.108577
1623 23:03:09.108665
1624 23:03:09.108751 TX Vref Scan disable
1625 23:03:09.112939 == TX Byte 0 ==
1626 23:03:09.115588 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1627 23:03:09.118817 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1628 23:03:09.122695 == TX Byte 1 ==
1629 23:03:09.125485 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1630 23:03:09.128884 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1631 23:03:09.128973
1632 23:03:09.132264 [DATLAT]
1633 23:03:09.132350 Freq=800, CH1 RK0
1634 23:03:09.132437
1635 23:03:09.135457 DATLAT Default: 0xa
1636 23:03:09.135542 0, 0xFFFF, sum = 0
1637 23:03:09.138856 1, 0xFFFF, sum = 0
1638 23:03:09.138969 2, 0xFFFF, sum = 0
1639 23:03:09.142428 3, 0xFFFF, sum = 0
1640 23:03:09.142512 4, 0xFFFF, sum = 0
1641 23:03:09.145474 5, 0xFFFF, sum = 0
1642 23:03:09.145557 6, 0xFFFF, sum = 0
1643 23:03:09.149044 7, 0xFFFF, sum = 0
1644 23:03:09.149127 8, 0xFFFF, sum = 0
1645 23:03:09.152515 9, 0x0, sum = 1
1646 23:03:09.152600 10, 0x0, sum = 2
1647 23:03:09.155809 11, 0x0, sum = 3
1648 23:03:09.155894 12, 0x0, sum = 4
1649 23:03:09.159325 best_step = 10
1650 23:03:09.159407
1651 23:03:09.159472 ==
1652 23:03:09.162181 Dram Type= 6, Freq= 0, CH_1, rank 0
1653 23:03:09.165679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1654 23:03:09.165767 ==
1655 23:03:09.168388 RX Vref Scan: 1
1656 23:03:09.168474
1657 23:03:09.168589 Set Vref Range= 32 -> 127
1658 23:03:09.168670
1659 23:03:09.172224 RX Vref 32 -> 127, step: 1
1660 23:03:09.172310
1661 23:03:09.175122 RX Delay -95 -> 252, step: 8
1662 23:03:09.175207
1663 23:03:09.178845 Set Vref, RX VrefLevel [Byte0]: 32
1664 23:03:09.182127 [Byte1]: 32
1665 23:03:09.182243
1666 23:03:09.185424 Set Vref, RX VrefLevel [Byte0]: 33
1667 23:03:09.188830 [Byte1]: 33
1668 23:03:09.192073
1669 23:03:09.192162 Set Vref, RX VrefLevel [Byte0]: 34
1670 23:03:09.198687 [Byte1]: 34
1671 23:03:09.198779
1672 23:03:09.201700 Set Vref, RX VrefLevel [Byte0]: 35
1673 23:03:09.205379 [Byte1]: 35
1674 23:03:09.205466
1675 23:03:09.208769 Set Vref, RX VrefLevel [Byte0]: 36
1676 23:03:09.211861 [Byte1]: 36
1677 23:03:09.215113
1678 23:03:09.215214 Set Vref, RX VrefLevel [Byte0]: 37
1679 23:03:09.218537 [Byte1]: 37
1680 23:03:09.222500
1681 23:03:09.222587 Set Vref, RX VrefLevel [Byte0]: 38
1682 23:03:09.225953 [Byte1]: 38
1683 23:03:09.230107
1684 23:03:09.230194 Set Vref, RX VrefLevel [Byte0]: 39
1685 23:03:09.233319 [Byte1]: 39
1686 23:03:09.238069
1687 23:03:09.238158 Set Vref, RX VrefLevel [Byte0]: 40
1688 23:03:09.240904 [Byte1]: 40
1689 23:03:09.245363
1690 23:03:09.245451 Set Vref, RX VrefLevel [Byte0]: 41
1691 23:03:09.248457 [Byte1]: 41
1692 23:03:09.253027
1693 23:03:09.253119 Set Vref, RX VrefLevel [Byte0]: 42
1694 23:03:09.256437 [Byte1]: 42
1695 23:03:09.260953
1696 23:03:09.261031 Set Vref, RX VrefLevel [Byte0]: 43
1697 23:03:09.264150 [Byte1]: 43
1698 23:03:09.267908
1699 23:03:09.267979 Set Vref, RX VrefLevel [Byte0]: 44
1700 23:03:09.271645 [Byte1]: 44
1701 23:03:09.275532
1702 23:03:09.275610 Set Vref, RX VrefLevel [Byte0]: 45
1703 23:03:09.279585 [Byte1]: 45
1704 23:03:09.283272
1705 23:03:09.283349 Set Vref, RX VrefLevel [Byte0]: 46
1706 23:03:09.286733 [Byte1]: 46
1707 23:03:09.291239
1708 23:03:09.291322 Set Vref, RX VrefLevel [Byte0]: 47
1709 23:03:09.294628 [Byte1]: 47
1710 23:03:09.298857
1711 23:03:09.298936 Set Vref, RX VrefLevel [Byte0]: 48
1712 23:03:09.301616 [Byte1]: 48
1713 23:03:09.306296
1714 23:03:09.306393 Set Vref, RX VrefLevel [Byte0]: 49
1715 23:03:09.309230 [Byte1]: 49
1716 23:03:09.313729
1717 23:03:09.313817 Set Vref, RX VrefLevel [Byte0]: 50
1718 23:03:09.316983 [Byte1]: 50
1719 23:03:09.321073
1720 23:03:09.321146 Set Vref, RX VrefLevel [Byte0]: 51
1721 23:03:09.324491 [Byte1]: 51
1722 23:03:09.328799
1723 23:03:09.328876 Set Vref, RX VrefLevel [Byte0]: 52
1724 23:03:09.332315 [Byte1]: 52
1725 23:03:09.336648
1726 23:03:09.336729 Set Vref, RX VrefLevel [Byte0]: 53
1727 23:03:09.340225 [Byte1]: 53
1728 23:03:09.344293
1729 23:03:09.344373 Set Vref, RX VrefLevel [Byte0]: 54
1730 23:03:09.347094 [Byte1]: 54
1731 23:03:09.351984
1732 23:03:09.352078 Set Vref, RX VrefLevel [Byte0]: 55
1733 23:03:09.354825 [Byte1]: 55
1734 23:03:09.359292
1735 23:03:09.359393 Set Vref, RX VrefLevel [Byte0]: 56
1736 23:03:09.362766 [Byte1]: 56
1737 23:03:09.367009
1738 23:03:09.367117 Set Vref, RX VrefLevel [Byte0]: 57
1739 23:03:09.370335 [Byte1]: 57
1740 23:03:09.374627
1741 23:03:09.374728 Set Vref, RX VrefLevel [Byte0]: 58
1742 23:03:09.377616 [Byte1]: 58
1743 23:03:09.381845
1744 23:03:09.381943 Set Vref, RX VrefLevel [Byte0]: 59
1745 23:03:09.385704 [Byte1]: 59
1746 23:03:09.389931
1747 23:03:09.390058 Set Vref, RX VrefLevel [Byte0]: 60
1748 23:03:09.393050 [Byte1]: 60
1749 23:03:09.397198
1750 23:03:09.397287 Set Vref, RX VrefLevel [Byte0]: 61
1751 23:03:09.400605 [Byte1]: 61
1752 23:03:09.404623
1753 23:03:09.404714 Set Vref, RX VrefLevel [Byte0]: 62
1754 23:03:09.407860 [Byte1]: 62
1755 23:03:09.412875
1756 23:03:09.413031 Set Vref, RX VrefLevel [Byte0]: 63
1757 23:03:09.415809 [Byte1]: 63
1758 23:03:09.420038
1759 23:03:09.420142 Set Vref, RX VrefLevel [Byte0]: 64
1760 23:03:09.423353 [Byte1]: 64
1761 23:03:09.427682
1762 23:03:09.427802 Set Vref, RX VrefLevel [Byte0]: 65
1763 23:03:09.431176 [Byte1]: 65
1764 23:03:09.435824
1765 23:03:09.435940 Set Vref, RX VrefLevel [Byte0]: 66
1766 23:03:09.438426 [Byte1]: 66
1767 23:03:09.443731
1768 23:03:09.443817 Set Vref, RX VrefLevel [Byte0]: 67
1769 23:03:09.446602 [Byte1]: 67
1770 23:03:09.450402
1771 23:03:09.450486 Set Vref, RX VrefLevel [Byte0]: 68
1772 23:03:09.453789 [Byte1]: 68
1773 23:03:09.458180
1774 23:03:09.458337 Set Vref, RX VrefLevel [Byte0]: 69
1775 23:03:09.461656 [Byte1]: 69
1776 23:03:09.465878
1777 23:03:09.465961 Set Vref, RX VrefLevel [Byte0]: 70
1778 23:03:09.468764 [Byte1]: 70
1779 23:03:09.473959
1780 23:03:09.474048 Set Vref, RX VrefLevel [Byte0]: 71
1781 23:03:09.476472 [Byte1]: 71
1782 23:03:09.480582
1783 23:03:09.480668 Set Vref, RX VrefLevel [Byte0]: 72
1784 23:03:09.483979 [Byte1]: 72
1785 23:03:09.488300
1786 23:03:09.488390 Set Vref, RX VrefLevel [Byte0]: 73
1787 23:03:09.491699 [Byte1]: 73
1788 23:03:09.495882
1789 23:03:09.495965 Set Vref, RX VrefLevel [Byte0]: 74
1790 23:03:09.499575 [Byte1]: 74
1791 23:03:09.503751
1792 23:03:09.503863 Set Vref, RX VrefLevel [Byte0]: 75
1793 23:03:09.506996 [Byte1]: 75
1794 23:03:09.511347
1795 23:03:09.511430 Final RX Vref Byte 0 = 54 to rank0
1796 23:03:09.514688 Final RX Vref Byte 1 = 55 to rank0
1797 23:03:09.517682 Final RX Vref Byte 0 = 54 to rank1
1798 23:03:09.521379 Final RX Vref Byte 1 = 55 to rank1==
1799 23:03:09.524661 Dram Type= 6, Freq= 0, CH_1, rank 0
1800 23:03:09.531049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1801 23:03:09.531142 ==
1802 23:03:09.531211 DQS Delay:
1803 23:03:09.534771 DQS0 = 0, DQS1 = 0
1804 23:03:09.534850 DQM Delay:
1805 23:03:09.534913 DQM0 = 84, DQM1 = 80
1806 23:03:09.537695 DQ Delay:
1807 23:03:09.540784 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1808 23:03:09.543983 DQ4 =80, DQ5 =92, DQ6 =96, DQ7 =76
1809 23:03:09.547535 DQ8 =64, DQ9 =72, DQ10 =80, DQ11 =76
1810 23:03:09.551305 DQ12 =88, DQ13 =88, DQ14 =84, DQ15 =88
1811 23:03:09.551391
1812 23:03:09.551459
1813 23:03:09.557177 [DQSOSCAuto] RK0, (LSB)MR18= 0x172a, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 404 ps
1814 23:03:09.560565 CH1 RK0: MR19=606, MR18=172A
1815 23:03:09.567341 CH1_RK0: MR19=0x606, MR18=0x172A, DQSOSC=399, MR23=63, INC=92, DEC=61
1816 23:03:09.567437
1817 23:03:09.570869 ----->DramcWriteLeveling(PI) begin...
1818 23:03:09.570946 ==
1819 23:03:09.573944 Dram Type= 6, Freq= 0, CH_1, rank 1
1820 23:03:09.577135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1821 23:03:09.577214 ==
1822 23:03:09.580242 Write leveling (Byte 0): 27 => 27
1823 23:03:09.583890 Write leveling (Byte 1): 28 => 28
1824 23:03:09.587374 DramcWriteLeveling(PI) end<-----
1825 23:03:09.587452
1826 23:03:09.587513 ==
1827 23:03:09.590476 Dram Type= 6, Freq= 0, CH_1, rank 1
1828 23:03:09.594016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1829 23:03:09.594095 ==
1830 23:03:09.596960 [Gating] SW mode calibration
1831 23:03:09.603628 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1832 23:03:09.610951 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1833 23:03:09.613469 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1834 23:03:09.620137 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1835 23:03:09.623327 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1836 23:03:09.626782 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 23:03:09.633557 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 23:03:09.636515 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 23:03:09.639823 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 23:03:09.646579 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 23:03:09.650442 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 23:03:09.653395 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 23:03:09.659720 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 23:03:09.663196 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 23:03:09.666406 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 23:03:09.673383 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 23:03:09.677114 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 23:03:09.680439 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 23:03:09.683350 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 23:03:09.689928 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1851 23:03:09.693639 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1852 23:03:09.697098 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 23:03:09.702892 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 23:03:09.706344 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 23:03:09.709938 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 23:03:09.716107 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 23:03:09.719539 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 23:03:09.723267 0 9 4 | B1->B0 | 2323 3030 | 1 0 | (1 1) (0 0)
1859 23:03:09.729496 0 9 8 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
1860 23:03:09.733026 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1861 23:03:09.736600 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1862 23:03:09.742835 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1863 23:03:09.746013 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1864 23:03:09.749721 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1865 23:03:09.756201 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1866 23:03:09.759485 0 10 4 | B1->B0 | 3333 2f2f | 1 0 | (1 0) (0 0)
1867 23:03:09.762433 0 10 8 | B1->B0 | 2929 2323 | 1 0 | (1 0) (0 0)
1868 23:03:09.768993 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 23:03:09.772650 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 23:03:09.775748 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 23:03:09.782793 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 23:03:09.786320 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 23:03:09.789560 0 11 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1874 23:03:09.795957 0 11 4 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
1875 23:03:09.798883 0 11 8 | B1->B0 | 3838 4646 | 1 0 | (0 0) (0 0)
1876 23:03:09.802118 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1877 23:03:09.808812 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1878 23:03:09.812198 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1879 23:03:09.815777 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1880 23:03:09.822597 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1881 23:03:09.825750 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1882 23:03:09.828639 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1883 23:03:09.835682 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1884 23:03:09.839320 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1885 23:03:09.842053 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1886 23:03:09.848926 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1887 23:03:09.851888 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1888 23:03:09.855172 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1889 23:03:09.861836 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1890 23:03:09.865069 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1891 23:03:09.868435 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1892 23:03:09.875338 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1893 23:03:09.878457 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1894 23:03:09.881606 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1895 23:03:09.888306 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1896 23:03:09.891722 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1897 23:03:09.895511 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1898 23:03:09.898552 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1899 23:03:09.905016 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1900 23:03:09.908692 Total UI for P1: 0, mck2ui 16
1901 23:03:09.911830 best dqsien dly found for B0: ( 0, 14, 4)
1902 23:03:09.914796 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1903 23:03:09.918329 Total UI for P1: 0, mck2ui 16
1904 23:03:09.921813 best dqsien dly found for B1: ( 0, 14, 8)
1905 23:03:09.925124 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1906 23:03:09.928137 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1907 23:03:09.928221
1908 23:03:09.931903 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1909 23:03:09.934908 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1910 23:03:09.938126 [Gating] SW calibration Done
1911 23:03:09.938208 ==
1912 23:03:09.941742 Dram Type= 6, Freq= 0, CH_1, rank 1
1913 23:03:09.948721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1914 23:03:09.948808 ==
1915 23:03:09.948874 RX Vref Scan: 0
1916 23:03:09.948934
1917 23:03:09.952274 RX Vref 0 -> 0, step: 1
1918 23:03:09.952357
1919 23:03:09.954697 RX Delay -130 -> 252, step: 16
1920 23:03:09.958321 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1921 23:03:09.961587 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1922 23:03:09.964911 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1923 23:03:09.970982 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1924 23:03:09.974411 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1925 23:03:09.977853 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1926 23:03:09.981349 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1927 23:03:09.984351 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1928 23:03:09.991223 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
1929 23:03:09.994379 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1930 23:03:09.997702 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1931 23:03:10.000953 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1932 23:03:10.004378 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1933 23:03:10.010822 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1934 23:03:10.014554 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1935 23:03:10.017841 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1936 23:03:10.017915 ==
1937 23:03:10.021508 Dram Type= 6, Freq= 0, CH_1, rank 1
1938 23:03:10.024297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1939 23:03:10.024377 ==
1940 23:03:10.027805 DQS Delay:
1941 23:03:10.027875 DQS0 = 0, DQS1 = 0
1942 23:03:10.030963 DQM Delay:
1943 23:03:10.031033 DQM0 = 84, DQM1 = 83
1944 23:03:10.031093 DQ Delay:
1945 23:03:10.034658 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1946 23:03:10.037527 DQ4 =85, DQ5 =93, DQ6 =85, DQ7 =85
1947 23:03:10.040647 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
1948 23:03:10.044130 DQ12 =93, DQ13 =85, DQ14 =85, DQ15 =85
1949 23:03:10.044231
1950 23:03:10.044329
1951 23:03:10.047191 ==
1952 23:03:10.051027 Dram Type= 6, Freq= 0, CH_1, rank 1
1953 23:03:10.054160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1954 23:03:10.054287 ==
1955 23:03:10.054373
1956 23:03:10.054434
1957 23:03:10.057145 TX Vref Scan disable
1958 23:03:10.057249 == TX Byte 0 ==
1959 23:03:10.064008 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1960 23:03:10.067817 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1961 23:03:10.067900 == TX Byte 1 ==
1962 23:03:10.073775 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1963 23:03:10.077570 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1964 23:03:10.077678 ==
1965 23:03:10.080417 Dram Type= 6, Freq= 0, CH_1, rank 1
1966 23:03:10.083636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1967 23:03:10.083721 ==
1968 23:03:10.097542 TX Vref=22, minBit 1, minWin=27, winSum=448
1969 23:03:10.100428 TX Vref=24, minBit 1, minWin=27, winSum=451
1970 23:03:10.103907 TX Vref=26, minBit 5, minWin=27, winSum=452
1971 23:03:10.107177 TX Vref=28, minBit 1, minWin=27, winSum=451
1972 23:03:10.110748 TX Vref=30, minBit 5, minWin=27, winSum=456
1973 23:03:10.117224 TX Vref=32, minBit 2, minWin=27, winSum=453
1974 23:03:10.120322 [TxChooseVref] Worse bit 5, Min win 27, Win sum 456, Final Vref 30
1975 23:03:10.120409
1976 23:03:10.123785 Final TX Range 1 Vref 30
1977 23:03:10.123870
1978 23:03:10.123936 ==
1979 23:03:10.127405 Dram Type= 6, Freq= 0, CH_1, rank 1
1980 23:03:10.130605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1981 23:03:10.130690 ==
1982 23:03:10.133752
1983 23:03:10.133834
1984 23:03:10.133899 TX Vref Scan disable
1985 23:03:10.137453 == TX Byte 0 ==
1986 23:03:10.140410 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1987 23:03:10.147352 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1988 23:03:10.147440 == TX Byte 1 ==
1989 23:03:10.150522 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1990 23:03:10.157149 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1991 23:03:10.157257
1992 23:03:10.157323 [DATLAT]
1993 23:03:10.157384 Freq=800, CH1 RK1
1994 23:03:10.157443
1995 23:03:10.160594 DATLAT Default: 0xa
1996 23:03:10.160678 0, 0xFFFF, sum = 0
1997 23:03:10.164006 1, 0xFFFF, sum = 0
1998 23:03:10.166739 2, 0xFFFF, sum = 0
1999 23:03:10.166823 3, 0xFFFF, sum = 0
2000 23:03:10.170821 4, 0xFFFF, sum = 0
2001 23:03:10.170926 5, 0xFFFF, sum = 0
2002 23:03:10.173589 6, 0xFFFF, sum = 0
2003 23:03:10.173673 7, 0xFFFF, sum = 0
2004 23:03:10.177046 8, 0xFFFF, sum = 0
2005 23:03:10.177131 9, 0x0, sum = 1
2006 23:03:10.180467 10, 0x0, sum = 2
2007 23:03:10.180553 11, 0x0, sum = 3
2008 23:03:10.183597 12, 0x0, sum = 4
2009 23:03:10.183680 best_step = 10
2010 23:03:10.183745
2011 23:03:10.183805 ==
2012 23:03:10.187120 Dram Type= 6, Freq= 0, CH_1, rank 1
2013 23:03:10.189941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2014 23:03:10.190098 ==
2015 23:03:10.193623 RX Vref Scan: 0
2016 23:03:10.193704
2017 23:03:10.196848 RX Vref 0 -> 0, step: 1
2018 23:03:10.196930
2019 23:03:10.196995 RX Delay -95 -> 252, step: 8
2020 23:03:10.203757 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
2021 23:03:10.207161 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
2022 23:03:10.210622 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
2023 23:03:10.213919 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
2024 23:03:10.217336 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
2025 23:03:10.223780 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
2026 23:03:10.227102 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2027 23:03:10.230536 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
2028 23:03:10.233838 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
2029 23:03:10.237008 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2030 23:03:10.243749 iDelay=209, Bit 10, Center 84 (-31 ~ 200) 232
2031 23:03:10.247148 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
2032 23:03:10.250242 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
2033 23:03:10.253990 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2034 23:03:10.256935 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2035 23:03:10.263640 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2036 23:03:10.263737 ==
2037 23:03:10.267080 Dram Type= 6, Freq= 0, CH_1, rank 1
2038 23:03:10.270512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2039 23:03:10.270601 ==
2040 23:03:10.270667 DQS Delay:
2041 23:03:10.273829 DQS0 = 0, DQS1 = 0
2042 23:03:10.273912 DQM Delay:
2043 23:03:10.277229 DQM0 = 86, DQM1 = 81
2044 23:03:10.277313 DQ Delay:
2045 23:03:10.280168 DQ0 =88, DQ1 =84, DQ2 =76, DQ3 =84
2046 23:03:10.283719 DQ4 =84, DQ5 =96, DQ6 =92, DQ7 =84
2047 23:03:10.286712 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =72
2048 23:03:10.289954 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
2049 23:03:10.290037
2050 23:03:10.290103
2051 23:03:10.300209 [DQSOSCAuto] RK1, (LSB)MR18= 0x1c38, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 402 ps
2052 23:03:10.300320 CH1 RK1: MR19=606, MR18=1C38
2053 23:03:10.306685 CH1_RK1: MR19=0x606, MR18=0x1C38, DQSOSC=395, MR23=63, INC=94, DEC=63
2054 23:03:10.310195 [RxdqsGatingPostProcess] freq 800
2055 23:03:10.316495 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2056 23:03:10.320288 Pre-setting of DQS Precalculation
2057 23:03:10.323475 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2058 23:03:10.330411 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2059 23:03:10.336886 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2060 23:03:10.340323
2061 23:03:10.340426
2062 23:03:10.340492 [Calibration Summary] 1600 Mbps
2063 23:03:10.343533 CH 0, Rank 0
2064 23:03:10.343628 SW Impedance : PASS
2065 23:03:10.347199 DUTY Scan : NO K
2066 23:03:10.349927 ZQ Calibration : PASS
2067 23:03:10.350008 Jitter Meter : NO K
2068 23:03:10.353296 CBT Training : PASS
2069 23:03:10.357224 Write leveling : PASS
2070 23:03:10.357308 RX DQS gating : PASS
2071 23:03:10.360208 RX DQ/DQS(RDDQC) : PASS
2072 23:03:10.363346 TX DQ/DQS : PASS
2073 23:03:10.363430 RX DATLAT : PASS
2074 23:03:10.366460 RX DQ/DQS(Engine): PASS
2075 23:03:10.370011 TX OE : NO K
2076 23:03:10.370124 All Pass.
2077 23:03:10.370220
2078 23:03:10.370332 CH 0, Rank 1
2079 23:03:10.373416 SW Impedance : PASS
2080 23:03:10.377214 DUTY Scan : NO K
2081 23:03:10.377313 ZQ Calibration : PASS
2082 23:03:10.379815 Jitter Meter : NO K
2083 23:03:10.383654 CBT Training : PASS
2084 23:03:10.383736 Write leveling : PASS
2085 23:03:10.386850 RX DQS gating : PASS
2086 23:03:10.386934 RX DQ/DQS(RDDQC) : PASS
2087 23:03:10.389964 TX DQ/DQS : PASS
2088 23:03:10.393238 RX DATLAT : PASS
2089 23:03:10.393324 RX DQ/DQS(Engine): PASS
2090 23:03:10.396451 TX OE : NO K
2091 23:03:10.396544 All Pass.
2092 23:03:10.396656
2093 23:03:10.400154 CH 1, Rank 0
2094 23:03:10.400236 SW Impedance : PASS
2095 23:03:10.403280 DUTY Scan : NO K
2096 23:03:10.406720 ZQ Calibration : PASS
2097 23:03:10.406803 Jitter Meter : NO K
2098 23:03:10.410178 CBT Training : PASS
2099 23:03:10.413458 Write leveling : PASS
2100 23:03:10.413540 RX DQS gating : PASS
2101 23:03:10.416485 RX DQ/DQS(RDDQC) : PASS
2102 23:03:10.419776 TX DQ/DQS : PASS
2103 23:03:10.419874 RX DATLAT : PASS
2104 23:03:10.423410 RX DQ/DQS(Engine): PASS
2105 23:03:10.426937 TX OE : NO K
2106 23:03:10.427019 All Pass.
2107 23:03:10.427085
2108 23:03:10.427145 CH 1, Rank 1
2109 23:03:10.430019 SW Impedance : PASS
2110 23:03:10.433080 DUTY Scan : NO K
2111 23:03:10.433163 ZQ Calibration : PASS
2112 23:03:10.436439 Jitter Meter : NO K
2113 23:03:10.439956 CBT Training : PASS
2114 23:03:10.440048 Write leveling : PASS
2115 23:03:10.443474 RX DQS gating : PASS
2116 23:03:10.443556 RX DQ/DQS(RDDQC) : PASS
2117 23:03:10.446538 TX DQ/DQS : PASS
2118 23:03:10.450032 RX DATLAT : PASS
2119 23:03:10.450114 RX DQ/DQS(Engine): PASS
2120 23:03:10.453124 TX OE : NO K
2121 23:03:10.453207 All Pass.
2122 23:03:10.453273
2123 23:03:10.456979 DramC Write-DBI off
2124 23:03:10.459522 PER_BANK_REFRESH: Hybrid Mode
2125 23:03:10.459627 TX_TRACKING: ON
2126 23:03:10.463487 [GetDramInforAfterCalByMRR] Vendor 6.
2127 23:03:10.466827 [GetDramInforAfterCalByMRR] Revision 606.
2128 23:03:10.469743 [GetDramInforAfterCalByMRR] Revision 2 0.
2129 23:03:10.473077 MR0 0x3b3b
2130 23:03:10.473160 MR8 0x5151
2131 23:03:10.476214 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2132 23:03:10.476296
2133 23:03:10.479494 MR0 0x3b3b
2134 23:03:10.479655 MR8 0x5151
2135 23:03:10.482822 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2136 23:03:10.482906
2137 23:03:10.492953 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2138 23:03:10.496119 [FAST_K] Save calibration result to emmc
2139 23:03:10.499693 [FAST_K] Save calibration result to emmc
2140 23:03:10.503193 dram_init: config_dvfs: 1
2141 23:03:10.506387 dramc_set_vcore_voltage set vcore to 662500
2142 23:03:10.506470 Read voltage for 1200, 2
2143 23:03:10.509504 Vio18 = 0
2144 23:03:10.509587 Vcore = 662500
2145 23:03:10.509652 Vdram = 0
2146 23:03:10.513143 Vddq = 0
2147 23:03:10.513225 Vmddr = 0
2148 23:03:10.516222 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2149 23:03:10.522740 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2150 23:03:10.526108 MEM_TYPE=3, freq_sel=15
2151 23:03:10.529697 sv_algorithm_assistance_LP4_1600
2152 23:03:10.533450 ============ PULL DRAM RESETB DOWN ============
2153 23:03:10.536287 ========== PULL DRAM RESETB DOWN end =========
2154 23:03:10.543181 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2155 23:03:10.543270 ===================================
2156 23:03:10.546241 LPDDR4 DRAM CONFIGURATION
2157 23:03:10.549249 ===================================
2158 23:03:10.552857 EX_ROW_EN[0] = 0x0
2159 23:03:10.552943 EX_ROW_EN[1] = 0x0
2160 23:03:10.556228 LP4Y_EN = 0x0
2161 23:03:10.556313 WORK_FSP = 0x0
2162 23:03:10.559410 WL = 0x4
2163 23:03:10.559493 RL = 0x4
2164 23:03:10.562515 BL = 0x2
2165 23:03:10.566050 RPST = 0x0
2166 23:03:10.566134 RD_PRE = 0x0
2167 23:03:10.569217 WR_PRE = 0x1
2168 23:03:10.569313 WR_PST = 0x0
2169 23:03:10.572343 DBI_WR = 0x0
2170 23:03:10.572442 DBI_RD = 0x0
2171 23:03:10.576118 OTF = 0x1
2172 23:03:10.579415 ===================================
2173 23:03:10.582743 ===================================
2174 23:03:10.582827 ANA top config
2175 23:03:10.586197 ===================================
2176 23:03:10.589108 DLL_ASYNC_EN = 0
2177 23:03:10.592856 ALL_SLAVE_EN = 0
2178 23:03:10.592939 NEW_RANK_MODE = 1
2179 23:03:10.595969 DLL_IDLE_MODE = 1
2180 23:03:10.599381 LP45_APHY_COMB_EN = 1
2181 23:03:10.602465 TX_ODT_DIS = 1
2182 23:03:10.602548 NEW_8X_MODE = 1
2183 23:03:10.605824 ===================================
2184 23:03:10.609133 ===================================
2185 23:03:10.612716 data_rate = 2400
2186 23:03:10.616174 CKR = 1
2187 23:03:10.619043 DQ_P2S_RATIO = 8
2188 23:03:10.622246 ===================================
2189 23:03:10.626056 CA_P2S_RATIO = 8
2190 23:03:10.628893 DQ_CA_OPEN = 0
2191 23:03:10.628977 DQ_SEMI_OPEN = 0
2192 23:03:10.632236 CA_SEMI_OPEN = 0
2193 23:03:10.635746 CA_FULL_RATE = 0
2194 23:03:10.639124 DQ_CKDIV4_EN = 0
2195 23:03:10.642344 CA_CKDIV4_EN = 0
2196 23:03:10.645654 CA_PREDIV_EN = 0
2197 23:03:10.649210 PH8_DLY = 17
2198 23:03:10.649295 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2199 23:03:10.652067 DQ_AAMCK_DIV = 4
2200 23:03:10.655605 CA_AAMCK_DIV = 4
2201 23:03:10.658973 CA_ADMCK_DIV = 4
2202 23:03:10.662066 DQ_TRACK_CA_EN = 0
2203 23:03:10.665617 CA_PICK = 1200
2204 23:03:10.665716 CA_MCKIO = 1200
2205 23:03:10.668672 MCKIO_SEMI = 0
2206 23:03:10.672556 PLL_FREQ = 2366
2207 23:03:10.675935 DQ_UI_PI_RATIO = 32
2208 23:03:10.678740 CA_UI_PI_RATIO = 0
2209 23:03:10.681834 ===================================
2210 23:03:10.685581 ===================================
2211 23:03:10.688444 memory_type:LPDDR4
2212 23:03:10.688528 GP_NUM : 10
2213 23:03:10.692492 SRAM_EN : 1
2214 23:03:10.692576 MD32_EN : 0
2215 23:03:10.695489 ===================================
2216 23:03:10.698904 [ANA_INIT] >>>>>>>>>>>>>>
2217 23:03:10.701995 <<<<<< [CONFIGURE PHASE]: ANA_TX
2218 23:03:10.705286 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2219 23:03:10.708367 ===================================
2220 23:03:10.711938 data_rate = 2400,PCW = 0X5b00
2221 23:03:10.715631 ===================================
2222 23:03:10.718165 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2223 23:03:10.725100 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2224 23:03:10.728519 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2225 23:03:10.735071 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2226 23:03:10.738399 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2227 23:03:10.741833 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2228 23:03:10.741918 [ANA_INIT] flow start
2229 23:03:10.745455 [ANA_INIT] PLL >>>>>>>>
2230 23:03:10.748679 [ANA_INIT] PLL <<<<<<<<
2231 23:03:10.748766 [ANA_INIT] MIDPI >>>>>>>>
2232 23:03:10.751865 [ANA_INIT] MIDPI <<<<<<<<
2233 23:03:10.755139 [ANA_INIT] DLL >>>>>>>>
2234 23:03:10.755227 [ANA_INIT] DLL <<<<<<<<
2235 23:03:10.758091 [ANA_INIT] flow end
2236 23:03:10.762091 ============ LP4 DIFF to SE enter ============
2237 23:03:10.768620 ============ LP4 DIFF to SE exit ============
2238 23:03:10.768716 [ANA_INIT] <<<<<<<<<<<<<
2239 23:03:10.771286 [Flow] Enable top DCM control >>>>>
2240 23:03:10.774781 [Flow] Enable top DCM control <<<<<
2241 23:03:10.778067 Enable DLL master slave shuffle
2242 23:03:10.784867 ==============================================================
2243 23:03:10.784973 Gating Mode config
2244 23:03:10.791374 ==============================================================
2245 23:03:10.794621 Config description:
2246 23:03:10.801292 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2247 23:03:10.807950 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2248 23:03:10.815148 SELPH_MODE 0: By rank 1: By Phase
2249 23:03:10.821716 ==============================================================
2250 23:03:10.824802 GAT_TRACK_EN = 1
2251 23:03:10.824913 RX_GATING_MODE = 2
2252 23:03:10.828091 RX_GATING_TRACK_MODE = 2
2253 23:03:10.831643 SELPH_MODE = 1
2254 23:03:10.834589 PICG_EARLY_EN = 1
2255 23:03:10.837735 VALID_LAT_VALUE = 1
2256 23:03:10.844161 ==============================================================
2257 23:03:10.848072 Enter into Gating configuration >>>>
2258 23:03:10.850621 Exit from Gating configuration <<<<
2259 23:03:10.854006 Enter into DVFS_PRE_config >>>>>
2260 23:03:10.864781 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2261 23:03:10.867730 Exit from DVFS_PRE_config <<<<<
2262 23:03:10.870722 Enter into PICG configuration >>>>
2263 23:03:10.874175 Exit from PICG configuration <<<<
2264 23:03:10.877697 [RX_INPUT] configuration >>>>>
2265 23:03:10.880382 [RX_INPUT] configuration <<<<<
2266 23:03:10.884204 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2267 23:03:10.890350 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2268 23:03:10.897331 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2269 23:03:10.903885 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2270 23:03:10.906871 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2271 23:03:10.913469 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2272 23:03:10.917086 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2273 23:03:10.923286 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2274 23:03:10.926989 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2275 23:03:10.930186 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2276 23:03:10.933357 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2277 23:03:10.940026 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2278 23:03:10.943177 ===================================
2279 23:03:10.946764 LPDDR4 DRAM CONFIGURATION
2280 23:03:10.949933 ===================================
2281 23:03:10.950021 EX_ROW_EN[0] = 0x0
2282 23:03:10.953047 EX_ROW_EN[1] = 0x0
2283 23:03:10.953132 LP4Y_EN = 0x0
2284 23:03:10.956438 WORK_FSP = 0x0
2285 23:03:10.956525 WL = 0x4
2286 23:03:10.959706 RL = 0x4
2287 23:03:10.959791 BL = 0x2
2288 23:03:10.963510 RPST = 0x0
2289 23:03:10.963594 RD_PRE = 0x0
2290 23:03:10.966164 WR_PRE = 0x1
2291 23:03:10.966246 WR_PST = 0x0
2292 23:03:10.969891 DBI_WR = 0x0
2293 23:03:10.970015 DBI_RD = 0x0
2294 23:03:10.973164 OTF = 0x1
2295 23:03:10.976670 ===================================
2296 23:03:10.980004 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2297 23:03:10.983454 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2298 23:03:10.989797 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2299 23:03:10.992962 ===================================
2300 23:03:10.993058 LPDDR4 DRAM CONFIGURATION
2301 23:03:10.996732 ===================================
2302 23:03:10.999414 EX_ROW_EN[0] = 0x10
2303 23:03:11.003277 EX_ROW_EN[1] = 0x0
2304 23:03:11.003361 LP4Y_EN = 0x0
2305 23:03:11.006536 WORK_FSP = 0x0
2306 23:03:11.006634 WL = 0x4
2307 23:03:11.009622 RL = 0x4
2308 23:03:11.009705 BL = 0x2
2309 23:03:11.012887 RPST = 0x0
2310 23:03:11.012971 RD_PRE = 0x0
2311 23:03:11.015928 WR_PRE = 0x1
2312 23:03:11.016014 WR_PST = 0x0
2313 23:03:11.019282 DBI_WR = 0x0
2314 23:03:11.019401 DBI_RD = 0x0
2315 23:03:11.023106 OTF = 0x1
2316 23:03:11.026280 ===================================
2317 23:03:11.032570 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2318 23:03:11.032664 ==
2319 23:03:11.036318 Dram Type= 6, Freq= 0, CH_0, rank 0
2320 23:03:11.039709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2321 23:03:11.039793 ==
2322 23:03:11.042943 [Duty_Offset_Calibration]
2323 23:03:11.043070 B0:2 B1:0 CA:4
2324 23:03:11.043140
2325 23:03:11.045625 [DutyScan_Calibration_Flow] k_type=0
2326 23:03:11.055985
2327 23:03:11.056090 ==CLK 0==
2328 23:03:11.058892 Final CLK duty delay cell = -4
2329 23:03:11.062489 [-4] MAX Duty = 5031%(X100), DQS PI = 14
2330 23:03:11.065809 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2331 23:03:11.069458 [-4] AVG Duty = 4937%(X100)
2332 23:03:11.069544
2333 23:03:11.073422 CH0 CLK Duty spec in!! Max-Min= 187%
2334 23:03:11.075865 [DutyScan_Calibration_Flow] ====Done====
2335 23:03:11.075948
2336 23:03:11.079679 [DutyScan_Calibration_Flow] k_type=1
2337 23:03:11.095378
2338 23:03:11.095505 ==DQS 0 ==
2339 23:03:11.099100 Final DQS duty delay cell = 0
2340 23:03:11.101926 [0] MAX Duty = 5156%(X100), DQS PI = 20
2341 23:03:11.105980 [0] MIN Duty = 5093%(X100), DQS PI = 0
2342 23:03:11.106065 [0] AVG Duty = 5124%(X100)
2343 23:03:11.108827
2344 23:03:11.108912 ==DQS 1 ==
2345 23:03:11.112530 Final DQS duty delay cell = 0
2346 23:03:11.115722 [0] MAX Duty = 5125%(X100), DQS PI = 50
2347 23:03:11.118778 [0] MIN Duty = 5000%(X100), DQS PI = 0
2348 23:03:11.118903 [0] AVG Duty = 5062%(X100)
2349 23:03:11.122072
2350 23:03:11.125477 CH0 DQS 0 Duty spec in!! Max-Min= 63%
2351 23:03:11.125570
2352 23:03:11.128481 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2353 23:03:11.132390 [DutyScan_Calibration_Flow] ====Done====
2354 23:03:11.132478
2355 23:03:11.134871 [DutyScan_Calibration_Flow] k_type=3
2356 23:03:11.151893
2357 23:03:11.152005 ==DQM 0 ==
2358 23:03:11.155404 Final DQM duty delay cell = 0
2359 23:03:11.158205 [0] MAX Duty = 5093%(X100), DQS PI = 20
2360 23:03:11.162026 [0] MIN Duty = 4875%(X100), DQS PI = 44
2361 23:03:11.165202 [0] AVG Duty = 4984%(X100)
2362 23:03:11.165283
2363 23:03:11.165347 ==DQM 1 ==
2364 23:03:11.168687 Final DQM duty delay cell = 0
2365 23:03:11.171646 [0] MAX Duty = 4969%(X100), DQS PI = 2
2366 23:03:11.175149 [0] MIN Duty = 4907%(X100), DQS PI = 12
2367 23:03:11.177923 [0] AVG Duty = 4938%(X100)
2368 23:03:11.178005
2369 23:03:11.181735 CH0 DQM 0 Duty spec in!! Max-Min= 218%
2370 23:03:11.181816
2371 23:03:11.184568 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2372 23:03:11.187869 [DutyScan_Calibration_Flow] ====Done====
2373 23:03:11.187950
2374 23:03:11.191121 [DutyScan_Calibration_Flow] k_type=2
2375 23:03:11.208491
2376 23:03:11.208605 ==DQ 0 ==
2377 23:03:11.211525 Final DQ duty delay cell = 0
2378 23:03:11.215410 [0] MAX Duty = 5125%(X100), DQS PI = 18
2379 23:03:11.217788 [0] MIN Duty = 4969%(X100), DQS PI = 52
2380 23:03:11.217873 [0] AVG Duty = 5047%(X100)
2381 23:03:11.221327
2382 23:03:11.221419 ==DQ 1 ==
2383 23:03:11.225287 Final DQ duty delay cell = 0
2384 23:03:11.228439 [0] MAX Duty = 5156%(X100), DQS PI = 4
2385 23:03:11.231635 [0] MIN Duty = 4938%(X100), DQS PI = 14
2386 23:03:11.231719 [0] AVG Duty = 5047%(X100)
2387 23:03:11.231785
2388 23:03:11.234767 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2389 23:03:11.238236
2390 23:03:11.241307 CH0 DQ 1 Duty spec in!! Max-Min= 218%
2391 23:03:11.244547 [DutyScan_Calibration_Flow] ====Done====
2392 23:03:11.244666 ==
2393 23:03:11.247800 Dram Type= 6, Freq= 0, CH_1, rank 0
2394 23:03:11.251236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2395 23:03:11.251330 ==
2396 23:03:11.254825 [Duty_Offset_Calibration]
2397 23:03:11.254920 B0:0 B1:-1 CA:3
2398 23:03:11.254987
2399 23:03:11.258126 [DutyScan_Calibration_Flow] k_type=0
2400 23:03:11.267441
2401 23:03:11.267543 ==CLK 0==
2402 23:03:11.271528 Final CLK duty delay cell = -4
2403 23:03:11.273938 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2404 23:03:11.277315 [-4] MIN Duty = 4876%(X100), DQS PI = 36
2405 23:03:11.280587 [-4] AVG Duty = 4938%(X100)
2406 23:03:11.280691
2407 23:03:11.283865 CH1 CLK Duty spec in!! Max-Min= 124%
2408 23:03:11.287141 [DutyScan_Calibration_Flow] ====Done====
2409 23:03:11.287252
2410 23:03:11.290230 [DutyScan_Calibration_Flow] k_type=1
2411 23:03:11.306899
2412 23:03:11.307034 ==DQS 0 ==
2413 23:03:11.310483 Final DQS duty delay cell = 0
2414 23:03:11.313953 [0] MAX Duty = 5187%(X100), DQS PI = 28
2415 23:03:11.316602 [0] MIN Duty = 4907%(X100), DQS PI = 38
2416 23:03:11.320466 [0] AVG Duty = 5047%(X100)
2417 23:03:11.320577
2418 23:03:11.320671 ==DQS 1 ==
2419 23:03:11.323265 Final DQS duty delay cell = 0
2420 23:03:11.326733 [0] MAX Duty = 5156%(X100), DQS PI = 8
2421 23:03:11.330107 [0] MIN Duty = 5031%(X100), DQS PI = 20
2422 23:03:11.333409 [0] AVG Duty = 5093%(X100)
2423 23:03:11.333493
2424 23:03:11.337034 CH1 DQS 0 Duty spec in!! Max-Min= 280%
2425 23:03:11.337116
2426 23:03:11.340174 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2427 23:03:11.343065 [DutyScan_Calibration_Flow] ====Done====
2428 23:03:11.343155
2429 23:03:11.346701 [DutyScan_Calibration_Flow] k_type=3
2430 23:03:11.363297
2431 23:03:11.363416 ==DQM 0 ==
2432 23:03:11.366851 Final DQM duty delay cell = 0
2433 23:03:11.369929 [0] MAX Duty = 5031%(X100), DQS PI = 28
2434 23:03:11.373043 [0] MIN Duty = 4813%(X100), DQS PI = 38
2435 23:03:11.377092 [0] AVG Duty = 4922%(X100)
2436 23:03:11.377214
2437 23:03:11.377307 ==DQM 1 ==
2438 23:03:11.379724 Final DQM duty delay cell = 0
2439 23:03:11.383306 [0] MAX Duty = 4969%(X100), DQS PI = 30
2440 23:03:11.386927 [0] MIN Duty = 4844%(X100), DQS PI = 0
2441 23:03:11.389829 [0] AVG Duty = 4906%(X100)
2442 23:03:11.389930
2443 23:03:11.393624 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2444 23:03:11.393732
2445 23:03:11.396271 CH1 DQM 1 Duty spec in!! Max-Min= 125%
2446 23:03:11.399559 [DutyScan_Calibration_Flow] ====Done====
2447 23:03:11.399661
2448 23:03:11.402893 [DutyScan_Calibration_Flow] k_type=2
2449 23:03:11.419562
2450 23:03:11.419674 ==DQ 0 ==
2451 23:03:11.422127 Final DQ duty delay cell = -4
2452 23:03:11.425440 [-4] MAX Duty = 5031%(X100), DQS PI = 30
2453 23:03:11.428834 [-4] MIN Duty = 4844%(X100), DQS PI = 34
2454 23:03:11.432328 [-4] AVG Duty = 4937%(X100)
2455 23:03:11.432431
2456 23:03:11.432523 ==DQ 1 ==
2457 23:03:11.435692 Final DQ duty delay cell = 0
2458 23:03:11.439045 [0] MAX Duty = 5031%(X100), DQS PI = 32
2459 23:03:11.442100 [0] MIN Duty = 4844%(X100), DQS PI = 0
2460 23:03:11.445274 [0] AVG Duty = 4937%(X100)
2461 23:03:11.445375
2462 23:03:11.449151 CH1 DQ 0 Duty spec in!! Max-Min= 187%
2463 23:03:11.449251
2464 23:03:11.452042 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2465 23:03:11.455516 [DutyScan_Calibration_Flow] ====Done====
2466 23:03:11.458832 nWR fixed to 30
2467 23:03:11.461910 [ModeRegInit_LP4] CH0 RK0
2468 23:03:11.462017 [ModeRegInit_LP4] CH0 RK1
2469 23:03:11.465103 [ModeRegInit_LP4] CH1 RK0
2470 23:03:11.468306 [ModeRegInit_LP4] CH1 RK1
2471 23:03:11.468409 match AC timing 7
2472 23:03:11.475664 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2473 23:03:11.478756 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2474 23:03:11.481849 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2475 23:03:11.488815 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2476 23:03:11.491599 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2477 23:03:11.491684 ==
2478 23:03:11.495125 Dram Type= 6, Freq= 0, CH_0, rank 0
2479 23:03:11.498330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2480 23:03:11.498410 ==
2481 23:03:11.505143 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2482 23:03:11.511326 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2483 23:03:11.519525 [CA 0] Center 39 (9~70) winsize 62
2484 23:03:11.522479 [CA 1] Center 39 (9~70) winsize 62
2485 23:03:11.526143 [CA 2] Center 35 (5~66) winsize 62
2486 23:03:11.529588 [CA 3] Center 35 (5~66) winsize 62
2487 23:03:11.532675 [CA 4] Center 33 (3~64) winsize 62
2488 23:03:11.536622 [CA 5] Center 33 (3~63) winsize 61
2489 23:03:11.536727
2490 23:03:11.539091 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2491 23:03:11.539188
2492 23:03:11.542919 [CATrainingPosCal] consider 1 rank data
2493 23:03:11.545822 u2DelayCellTimex100 = 270/100 ps
2494 23:03:11.549057 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2495 23:03:11.552695 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2496 23:03:11.559110 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2497 23:03:11.562222 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2498 23:03:11.565609 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2499 23:03:11.569128 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2500 23:03:11.569228
2501 23:03:11.572348 CA PerBit enable=1, Macro0, CA PI delay=33
2502 23:03:11.572438
2503 23:03:11.575479 [CBTSetCACLKResult] CA Dly = 33
2504 23:03:11.575559 CS Dly: 7 (0~38)
2505 23:03:11.578746 ==
2506 23:03:11.582593 Dram Type= 6, Freq= 0, CH_0, rank 1
2507 23:03:11.585686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2508 23:03:11.585796 ==
2509 23:03:11.589093 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2510 23:03:11.595444 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2511 23:03:11.605104 [CA 0] Center 39 (9~70) winsize 62
2512 23:03:11.608220 [CA 1] Center 39 (9~70) winsize 62
2513 23:03:11.611914 [CA 2] Center 35 (5~66) winsize 62
2514 23:03:11.615267 [CA 3] Center 35 (5~66) winsize 62
2515 23:03:11.618149 [CA 4] Center 34 (4~65) winsize 62
2516 23:03:11.622168 [CA 5] Center 33 (3~64) winsize 62
2517 23:03:11.622278
2518 23:03:11.624829 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2519 23:03:11.624939
2520 23:03:11.628188 [CATrainingPosCal] consider 2 rank data
2521 23:03:11.631798 u2DelayCellTimex100 = 270/100 ps
2522 23:03:11.634633 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2523 23:03:11.641659 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2524 23:03:11.644867 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2525 23:03:11.648156 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2526 23:03:11.651183 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2527 23:03:11.654983 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2528 23:03:11.655090
2529 23:03:11.658466 CA PerBit enable=1, Macro0, CA PI delay=33
2530 23:03:11.658546
2531 23:03:11.661392 [CBTSetCACLKResult] CA Dly = 33
2532 23:03:11.661496 CS Dly: 8 (0~41)
2533 23:03:11.664577
2534 23:03:11.667702 ----->DramcWriteLeveling(PI) begin...
2535 23:03:11.667806 ==
2536 23:03:11.671166 Dram Type= 6, Freq= 0, CH_0, rank 0
2537 23:03:11.675128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2538 23:03:11.675206 ==
2539 23:03:11.677984 Write leveling (Byte 0): 32 => 32
2540 23:03:11.681106 Write leveling (Byte 1): 27 => 27
2541 23:03:11.684184 DramcWriteLeveling(PI) end<-----
2542 23:03:11.684280
2543 23:03:11.684347 ==
2544 23:03:11.687739 Dram Type= 6, Freq= 0, CH_0, rank 0
2545 23:03:11.691247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2546 23:03:11.691354 ==
2547 23:03:11.694425 [Gating] SW mode calibration
2548 23:03:11.700748 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2549 23:03:11.707431 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2550 23:03:11.711133 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2551 23:03:11.714326 0 15 4 | B1->B0 | 2929 3434 | 1 1 | (0 0) (1 1)
2552 23:03:11.721100 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2553 23:03:11.723860 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2554 23:03:11.727736 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2555 23:03:11.734542 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2556 23:03:11.737211 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2557 23:03:11.740523 0 15 28 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 1)
2558 23:03:11.747350 1 0 0 | B1->B0 | 3131 2323 | 0 0 | (0 0) (0 0)
2559 23:03:11.751139 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2560 23:03:11.753824 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2561 23:03:11.761017 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2562 23:03:11.764249 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2563 23:03:11.767281 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2564 23:03:11.773926 1 0 24 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
2565 23:03:11.777351 1 0 28 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
2566 23:03:11.780501 1 1 0 | B1->B0 | 2e2e 4646 | 0 0 | (0 0) (0 0)
2567 23:03:11.787441 1 1 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
2568 23:03:11.790558 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2569 23:03:11.793858 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2570 23:03:11.797135 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2571 23:03:11.803955 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2572 23:03:11.808026 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2573 23:03:11.810478 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2574 23:03:11.816864 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2575 23:03:11.820594 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2576 23:03:11.823563 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2577 23:03:11.830531 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2578 23:03:11.833674 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2579 23:03:11.836671 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2580 23:03:11.844271 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2581 23:03:11.846860 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2582 23:03:11.850476 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2583 23:03:11.857168 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2584 23:03:11.860172 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2585 23:03:11.863412 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2586 23:03:11.869849 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2587 23:03:11.873600 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2588 23:03:11.876790 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2589 23:03:11.883367 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2590 23:03:11.886794 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2591 23:03:11.889739 Total UI for P1: 0, mck2ui 16
2592 23:03:11.893405 best dqsien dly found for B0: ( 1, 3, 26)
2593 23:03:11.896445 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2594 23:03:11.900392 Total UI for P1: 0, mck2ui 16
2595 23:03:11.903401 best dqsien dly found for B1: ( 1, 4, 0)
2596 23:03:11.906291 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2597 23:03:11.909776 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2598 23:03:11.909884
2599 23:03:11.916449 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2600 23:03:11.920025 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2601 23:03:11.920109 [Gating] SW calibration Done
2602 23:03:11.923328 ==
2603 23:03:11.923410 Dram Type= 6, Freq= 0, CH_0, rank 0
2604 23:03:11.929831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2605 23:03:11.929975 ==
2606 23:03:11.930071 RX Vref Scan: 0
2607 23:03:11.930162
2608 23:03:11.932979 RX Vref 0 -> 0, step: 1
2609 23:03:11.933062
2610 23:03:11.936367 RX Delay -40 -> 252, step: 8
2611 23:03:11.939699 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2612 23:03:11.942886 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2613 23:03:11.946464 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2614 23:03:11.953194 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2615 23:03:11.956271 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2616 23:03:11.959736 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2617 23:03:11.963450 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2618 23:03:11.966810 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2619 23:03:11.972962 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2620 23:03:11.976580 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2621 23:03:11.979754 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2622 23:03:11.983193 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2623 23:03:11.986239 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2624 23:03:11.992970 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2625 23:03:11.996001 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2626 23:03:11.999465 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2627 23:03:11.999554 ==
2628 23:03:12.002676 Dram Type= 6, Freq= 0, CH_0, rank 0
2629 23:03:12.006113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2630 23:03:12.009919 ==
2631 23:03:12.010006 DQS Delay:
2632 23:03:12.010074 DQS0 = 0, DQS1 = 0
2633 23:03:12.013408 DQM Delay:
2634 23:03:12.013496 DQM0 = 117, DQM1 = 107
2635 23:03:12.015948 DQ Delay:
2636 23:03:12.019611 DQ0 =115, DQ1 =119, DQ2 =119, DQ3 =111
2637 23:03:12.022838 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =123
2638 23:03:12.026029 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2639 23:03:12.029242 DQ12 =119, DQ13 =111, DQ14 =119, DQ15 =111
2640 23:03:12.029327
2641 23:03:12.029395
2642 23:03:12.029457 ==
2643 23:03:12.032907 Dram Type= 6, Freq= 0, CH_0, rank 0
2644 23:03:12.036027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2645 23:03:12.036113 ==
2646 23:03:12.036180
2647 23:03:12.036242
2648 23:03:12.039066 TX Vref Scan disable
2649 23:03:12.042650 == TX Byte 0 ==
2650 23:03:12.045701 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2651 23:03:12.049072 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2652 23:03:12.052435 == TX Byte 1 ==
2653 23:03:12.056179 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2654 23:03:12.059657 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2655 23:03:12.059748 ==
2656 23:03:12.062398 Dram Type= 6, Freq= 0, CH_0, rank 0
2657 23:03:12.066274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2658 23:03:12.069176 ==
2659 23:03:12.079767 TX Vref=22, minBit 4, minWin=25, winSum=410
2660 23:03:12.083080 TX Vref=24, minBit 3, minWin=25, winSum=421
2661 23:03:12.086430 TX Vref=26, minBit 1, minWin=25, winSum=419
2662 23:03:12.089603 TX Vref=28, minBit 4, minWin=26, winSum=433
2663 23:03:12.092811 TX Vref=30, minBit 5, minWin=26, winSum=434
2664 23:03:12.099302 TX Vref=32, minBit 4, minWin=26, winSum=430
2665 23:03:12.103309 [TxChooseVref] Worse bit 5, Min win 26, Win sum 434, Final Vref 30
2666 23:03:12.103396
2667 23:03:12.106306 Final TX Range 1 Vref 30
2668 23:03:12.106380
2669 23:03:12.106443 ==
2670 23:03:12.110064 Dram Type= 6, Freq= 0, CH_0, rank 0
2671 23:03:12.112779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2672 23:03:12.112864 ==
2673 23:03:12.115908
2674 23:03:12.115992
2675 23:03:12.116059 TX Vref Scan disable
2676 23:03:12.119286 == TX Byte 0 ==
2677 23:03:12.122518 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2678 23:03:12.129419 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2679 23:03:12.129504 == TX Byte 1 ==
2680 23:03:12.132534 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2681 23:03:12.139291 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2682 23:03:12.139377
2683 23:03:12.139444 [DATLAT]
2684 23:03:12.139506 Freq=1200, CH0 RK0
2685 23:03:12.139566
2686 23:03:12.142624 DATLAT Default: 0xd
2687 23:03:12.142708 0, 0xFFFF, sum = 0
2688 23:03:12.145720 1, 0xFFFF, sum = 0
2689 23:03:12.149338 2, 0xFFFF, sum = 0
2690 23:03:12.149444 3, 0xFFFF, sum = 0
2691 23:03:12.152369 4, 0xFFFF, sum = 0
2692 23:03:12.152457 5, 0xFFFF, sum = 0
2693 23:03:12.155818 6, 0xFFFF, sum = 0
2694 23:03:12.155905 7, 0xFFFF, sum = 0
2695 23:03:12.159230 8, 0xFFFF, sum = 0
2696 23:03:12.159316 9, 0xFFFF, sum = 0
2697 23:03:12.162545 10, 0xFFFF, sum = 0
2698 23:03:12.162631 11, 0xFFFF, sum = 0
2699 23:03:12.165584 12, 0x0, sum = 1
2700 23:03:12.165669 13, 0x0, sum = 2
2701 23:03:12.169275 14, 0x0, sum = 3
2702 23:03:12.169361 15, 0x0, sum = 4
2703 23:03:12.172580 best_step = 13
2704 23:03:12.172673
2705 23:03:12.172747 ==
2706 23:03:12.175953 Dram Type= 6, Freq= 0, CH_0, rank 0
2707 23:03:12.179281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2708 23:03:12.179393 ==
2709 23:03:12.179494 RX Vref Scan: 1
2710 23:03:12.179590
2711 23:03:12.182382 Set Vref Range= 32 -> 127
2712 23:03:12.182466
2713 23:03:12.185470 RX Vref 32 -> 127, step: 1
2714 23:03:12.185554
2715 23:03:12.188871 RX Delay -21 -> 252, step: 4
2716 23:03:12.188955
2717 23:03:12.192285 Set Vref, RX VrefLevel [Byte0]: 32
2718 23:03:12.195356 [Byte1]: 32
2719 23:03:12.195443
2720 23:03:12.198617 Set Vref, RX VrefLevel [Byte0]: 33
2721 23:03:12.202284 [Byte1]: 33
2722 23:03:12.205880
2723 23:03:12.205964 Set Vref, RX VrefLevel [Byte0]: 34
2724 23:03:12.208947 [Byte1]: 34
2725 23:03:12.214148
2726 23:03:12.214234 Set Vref, RX VrefLevel [Byte0]: 35
2727 23:03:12.217527 [Byte1]: 35
2728 23:03:12.221522
2729 23:03:12.221607 Set Vref, RX VrefLevel [Byte0]: 36
2730 23:03:12.225239 [Byte1]: 36
2731 23:03:12.229700
2732 23:03:12.229809 Set Vref, RX VrefLevel [Byte0]: 37
2733 23:03:12.233113 [Byte1]: 37
2734 23:03:12.237671
2735 23:03:12.237755 Set Vref, RX VrefLevel [Byte0]: 38
2736 23:03:12.240739 [Byte1]: 38
2737 23:03:12.245739
2738 23:03:12.245824 Set Vref, RX VrefLevel [Byte0]: 39
2739 23:03:12.248847 [Byte1]: 39
2740 23:03:12.253315
2741 23:03:12.253399 Set Vref, RX VrefLevel [Byte0]: 40
2742 23:03:12.256731 [Byte1]: 40
2743 23:03:12.261775
2744 23:03:12.261864 Set Vref, RX VrefLevel [Byte0]: 41
2745 23:03:12.265178 [Byte1]: 41
2746 23:03:12.269210
2747 23:03:12.269324 Set Vref, RX VrefLevel [Byte0]: 42
2748 23:03:12.272582 [Byte1]: 42
2749 23:03:12.277589
2750 23:03:12.277675 Set Vref, RX VrefLevel [Byte0]: 43
2751 23:03:12.280576 [Byte1]: 43
2752 23:03:12.285214
2753 23:03:12.285299 Set Vref, RX VrefLevel [Byte0]: 44
2754 23:03:12.289437 [Byte1]: 44
2755 23:03:12.293450
2756 23:03:12.293534 Set Vref, RX VrefLevel [Byte0]: 45
2757 23:03:12.296497 [Byte1]: 45
2758 23:03:12.300787
2759 23:03:12.300894 Set Vref, RX VrefLevel [Byte0]: 46
2760 23:03:12.304325 [Byte1]: 46
2761 23:03:12.308979
2762 23:03:12.309064 Set Vref, RX VrefLevel [Byte0]: 47
2763 23:03:12.312467 [Byte1]: 47
2764 23:03:12.316761
2765 23:03:12.316888 Set Vref, RX VrefLevel [Byte0]: 48
2766 23:03:12.320435 [Byte1]: 48
2767 23:03:12.324544
2768 23:03:12.324628 Set Vref, RX VrefLevel [Byte0]: 49
2769 23:03:12.328108 [Byte1]: 49
2770 23:03:12.333367
2771 23:03:12.333447 Set Vref, RX VrefLevel [Byte0]: 50
2772 23:03:12.335862 [Byte1]: 50
2773 23:03:12.340719
2774 23:03:12.340811 Set Vref, RX VrefLevel [Byte0]: 51
2775 23:03:12.343804 [Byte1]: 51
2776 23:03:12.348781
2777 23:03:12.348865 Set Vref, RX VrefLevel [Byte0]: 52
2778 23:03:12.351651 [Byte1]: 52
2779 23:03:12.356548
2780 23:03:12.356633 Set Vref, RX VrefLevel [Byte0]: 53
2781 23:03:12.359941 [Byte1]: 53
2782 23:03:12.364611
2783 23:03:12.364697 Set Vref, RX VrefLevel [Byte0]: 54
2784 23:03:12.367799 [Byte1]: 54
2785 23:03:12.372873
2786 23:03:12.372962 Set Vref, RX VrefLevel [Byte0]: 55
2787 23:03:12.375616 [Byte1]: 55
2788 23:03:12.380498
2789 23:03:12.380584 Set Vref, RX VrefLevel [Byte0]: 56
2790 23:03:12.384127 [Byte1]: 56
2791 23:03:12.388008
2792 23:03:12.388094 Set Vref, RX VrefLevel [Byte0]: 57
2793 23:03:12.391361 [Byte1]: 57
2794 23:03:12.396357
2795 23:03:12.396443 Set Vref, RX VrefLevel [Byte0]: 58
2796 23:03:12.399541 [Byte1]: 58
2797 23:03:12.404130
2798 23:03:12.404216 Set Vref, RX VrefLevel [Byte0]: 59
2799 23:03:12.407510 [Byte1]: 59
2800 23:03:12.412306
2801 23:03:12.412393 Set Vref, RX VrefLevel [Byte0]: 60
2802 23:03:12.415619 [Byte1]: 60
2803 23:03:12.420335
2804 23:03:12.420421 Set Vref, RX VrefLevel [Byte0]: 61
2805 23:03:12.422883 [Byte1]: 61
2806 23:03:12.427593
2807 23:03:12.427679 Set Vref, RX VrefLevel [Byte0]: 62
2808 23:03:12.431007 [Byte1]: 62
2809 23:03:12.435897
2810 23:03:12.435982 Set Vref, RX VrefLevel [Byte0]: 63
2811 23:03:12.439071 [Byte1]: 63
2812 23:03:12.443606
2813 23:03:12.443690 Set Vref, RX VrefLevel [Byte0]: 64
2814 23:03:12.447057 [Byte1]: 64
2815 23:03:12.451859
2816 23:03:12.451944 Set Vref, RX VrefLevel [Byte0]: 65
2817 23:03:12.454729 [Byte1]: 65
2818 23:03:12.459468
2819 23:03:12.459554 Set Vref, RX VrefLevel [Byte0]: 66
2820 23:03:12.462951 [Byte1]: 66
2821 23:03:12.467428
2822 23:03:12.467514 Set Vref, RX VrefLevel [Byte0]: 67
2823 23:03:12.471093 [Byte1]: 67
2824 23:03:12.475120
2825 23:03:12.475206 Set Vref, RX VrefLevel [Byte0]: 68
2826 23:03:12.478813 [Byte1]: 68
2827 23:03:12.483592
2828 23:03:12.483685 Set Vref, RX VrefLevel [Byte0]: 69
2829 23:03:12.486409 [Byte1]: 69
2830 23:03:12.491140
2831 23:03:12.491253 Final RX Vref Byte 0 = 52 to rank0
2832 23:03:12.494749 Final RX Vref Byte 1 = 59 to rank0
2833 23:03:12.497972 Final RX Vref Byte 0 = 52 to rank1
2834 23:03:12.501059 Final RX Vref Byte 1 = 59 to rank1==
2835 23:03:12.504827 Dram Type= 6, Freq= 0, CH_0, rank 0
2836 23:03:12.511382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2837 23:03:12.511473 ==
2838 23:03:12.511542 DQS Delay:
2839 23:03:12.511605 DQS0 = 0, DQS1 = 0
2840 23:03:12.514455 DQM Delay:
2841 23:03:12.514565 DQM0 = 117, DQM1 = 105
2842 23:03:12.518069 DQ Delay:
2843 23:03:12.521106 DQ0 =118, DQ1 =118, DQ2 =114, DQ3 =114
2844 23:03:12.524495 DQ4 =118, DQ5 =110, DQ6 =124, DQ7 =122
2845 23:03:12.527759 DQ8 =94, DQ9 =90, DQ10 =106, DQ11 =100
2846 23:03:12.531051 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =112
2847 23:03:12.531139
2848 23:03:12.531207
2849 23:03:12.537828 [DQSOSCAuto] RK0, (LSB)MR18= 0x1fc, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 409 ps
2850 23:03:12.540721 CH0 RK0: MR19=403, MR18=1FC
2851 23:03:12.547905 CH0_RK0: MR19=0x403, MR18=0x1FC, DQSOSC=409, MR23=63, INC=39, DEC=26
2852 23:03:12.548005
2853 23:03:12.551006 ----->DramcWriteLeveling(PI) begin...
2854 23:03:12.551120 ==
2855 23:03:12.554562 Dram Type= 6, Freq= 0, CH_0, rank 1
2856 23:03:12.557419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2857 23:03:12.560623 ==
2858 23:03:12.563810 Write leveling (Byte 0): 32 => 32
2859 23:03:12.563896 Write leveling (Byte 1): 25 => 25
2860 23:03:12.567038 DramcWriteLeveling(PI) end<-----
2861 23:03:12.567123
2862 23:03:12.567190 ==
2863 23:03:12.570716 Dram Type= 6, Freq= 0, CH_0, rank 1
2864 23:03:12.577252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2865 23:03:12.577345 ==
2866 23:03:12.580427 [Gating] SW mode calibration
2867 23:03:12.587156 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2868 23:03:12.590843 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2869 23:03:12.597039 0 15 0 | B1->B0 | 2323 3434 | 1 1 | (1 1) (1 1)
2870 23:03:12.600188 0 15 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
2871 23:03:12.603694 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2872 23:03:12.610577 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2873 23:03:12.613933 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2874 23:03:12.617111 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2875 23:03:12.623384 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2876 23:03:12.627178 0 15 28 | B1->B0 | 3434 2929 | 1 0 | (1 1) (0 0)
2877 23:03:12.630316 1 0 0 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
2878 23:03:12.636812 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2879 23:03:12.640621 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2880 23:03:12.643311 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2881 23:03:12.646919 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2882 23:03:12.653261 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2883 23:03:12.656770 1 0 24 | B1->B0 | 2323 3939 | 0 0 | (0 0) (1 1)
2884 23:03:12.660131 1 0 28 | B1->B0 | 2424 4444 | 0 1 | (0 0) (0 0)
2885 23:03:12.666945 1 1 0 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
2886 23:03:12.670184 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2887 23:03:12.673420 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2888 23:03:12.680148 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2889 23:03:12.683130 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2890 23:03:12.686634 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2891 23:03:12.693856 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2892 23:03:12.696933 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2893 23:03:12.699974 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 23:03:12.706578 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 23:03:12.709836 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2896 23:03:12.713286 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2897 23:03:12.719828 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2898 23:03:12.723670 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2899 23:03:12.726418 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2900 23:03:12.733653 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2901 23:03:12.736312 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2902 23:03:12.739806 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2903 23:03:12.746531 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2904 23:03:12.749852 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2905 23:03:12.753247 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2906 23:03:12.759647 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2907 23:03:12.763409 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2908 23:03:12.766687 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2909 23:03:12.772947 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2910 23:03:12.773048 Total UI for P1: 0, mck2ui 16
2911 23:03:12.776819 best dqsien dly found for B0: ( 1, 3, 24)
2912 23:03:12.782702 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2913 23:03:12.786127 Total UI for P1: 0, mck2ui 16
2914 23:03:12.789401 best dqsien dly found for B1: ( 1, 4, 0)
2915 23:03:12.793252 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2916 23:03:12.796205 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2917 23:03:12.796287
2918 23:03:12.799477 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2919 23:03:12.803131 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2920 23:03:12.806117 [Gating] SW calibration Done
2921 23:03:12.806209 ==
2922 23:03:12.809583 Dram Type= 6, Freq= 0, CH_0, rank 1
2923 23:03:12.812339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2924 23:03:12.812432 ==
2925 23:03:12.815944 RX Vref Scan: 0
2926 23:03:12.816044
2927 23:03:12.818971 RX Vref 0 -> 0, step: 1
2928 23:03:12.819063
2929 23:03:12.819131 RX Delay -40 -> 252, step: 8
2930 23:03:12.825935 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2931 23:03:12.828989 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2932 23:03:12.832421 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2933 23:03:12.835957 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2934 23:03:12.838961 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2935 23:03:12.845853 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2936 23:03:12.849283 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2937 23:03:12.852142 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2938 23:03:12.855618 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2939 23:03:12.858931 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2940 23:03:12.865923 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2941 23:03:12.868708 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2942 23:03:12.872205 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2943 23:03:12.875368 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2944 23:03:12.882632 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2945 23:03:12.885119 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2946 23:03:12.885201 ==
2947 23:03:12.888557 Dram Type= 6, Freq= 0, CH_0, rank 1
2948 23:03:12.891717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2949 23:03:12.891823 ==
2950 23:03:12.891895 DQS Delay:
2951 23:03:12.895571 DQS0 = 0, DQS1 = 0
2952 23:03:12.895681 DQM Delay:
2953 23:03:12.898683 DQM0 = 116, DQM1 = 109
2954 23:03:12.898804 DQ Delay:
2955 23:03:12.901644 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =111
2956 23:03:12.905452 DQ4 =119, DQ5 =107, DQ6 =127, DQ7 =123
2957 23:03:12.908699 DQ8 =99, DQ9 =91, DQ10 =111, DQ11 =103
2958 23:03:12.912216 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =115
2959 23:03:12.915134
2960 23:03:12.915218
2961 23:03:12.915284 ==
2962 23:03:12.918362 Dram Type= 6, Freq= 0, CH_0, rank 1
2963 23:03:12.921583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2964 23:03:12.921725 ==
2965 23:03:12.921852
2966 23:03:12.921969
2967 23:03:12.925332 TX Vref Scan disable
2968 23:03:12.925443 == TX Byte 0 ==
2969 23:03:12.931996 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2970 23:03:12.934934 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2971 23:03:12.935016 == TX Byte 1 ==
2972 23:03:12.941292 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2973 23:03:12.944856 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2974 23:03:12.944964 ==
2975 23:03:12.947909 Dram Type= 6, Freq= 0, CH_0, rank 1
2976 23:03:12.951699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2977 23:03:12.951836 ==
2978 23:03:12.964836 TX Vref=22, minBit 3, minWin=25, winSum=416
2979 23:03:12.968314 TX Vref=24, minBit 13, minWin=25, winSum=422
2980 23:03:12.971298 TX Vref=26, minBit 3, minWin=26, winSum=428
2981 23:03:12.974669 TX Vref=28, minBit 2, minWin=26, winSum=430
2982 23:03:12.978186 TX Vref=30, minBit 10, minWin=26, winSum=432
2983 23:03:12.984608 TX Vref=32, minBit 4, minWin=26, winSum=427
2984 23:03:12.988445 [TxChooseVref] Worse bit 10, Min win 26, Win sum 432, Final Vref 30
2985 23:03:12.988551
2986 23:03:12.991845 Final TX Range 1 Vref 30
2987 23:03:12.991944
2988 23:03:12.992011 ==
2989 23:03:12.995079 Dram Type= 6, Freq= 0, CH_0, rank 1
2990 23:03:12.998217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2991 23:03:13.001334 ==
2992 23:03:13.001447
2993 23:03:13.001540
2994 23:03:13.001640 TX Vref Scan disable
2995 23:03:13.005009 == TX Byte 0 ==
2996 23:03:13.007893 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2997 23:03:13.015088 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2998 23:03:13.015217 == TX Byte 1 ==
2999 23:03:13.017774 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3000 23:03:13.024558 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3001 23:03:13.024682
3002 23:03:13.024777 [DATLAT]
3003 23:03:13.024877 Freq=1200, CH0 RK1
3004 23:03:13.024969
3005 23:03:13.027783 DATLAT Default: 0xd
3006 23:03:13.027882 0, 0xFFFF, sum = 0
3007 23:03:13.031526 1, 0xFFFF, sum = 0
3008 23:03:13.034371 2, 0xFFFF, sum = 0
3009 23:03:13.034477 3, 0xFFFF, sum = 0
3010 23:03:13.038013 4, 0xFFFF, sum = 0
3011 23:03:13.038122 5, 0xFFFF, sum = 0
3012 23:03:13.041092 6, 0xFFFF, sum = 0
3013 23:03:13.041206 7, 0xFFFF, sum = 0
3014 23:03:13.044773 8, 0xFFFF, sum = 0
3015 23:03:13.044871 9, 0xFFFF, sum = 0
3016 23:03:13.048131 10, 0xFFFF, sum = 0
3017 23:03:13.048212 11, 0xFFFF, sum = 0
3018 23:03:13.051481 12, 0x0, sum = 1
3019 23:03:13.051568 13, 0x0, sum = 2
3020 23:03:13.054787 14, 0x0, sum = 3
3021 23:03:13.054876 15, 0x0, sum = 4
3022 23:03:13.057772 best_step = 13
3023 23:03:13.057891
3024 23:03:13.057986 ==
3025 23:03:13.061690 Dram Type= 6, Freq= 0, CH_0, rank 1
3026 23:03:13.064696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3027 23:03:13.064813 ==
3028 23:03:13.064908 RX Vref Scan: 0
3029 23:03:13.067796
3030 23:03:13.067900 RX Vref 0 -> 0, step: 1
3031 23:03:13.068005
3032 23:03:13.070971 RX Delay -21 -> 252, step: 4
3033 23:03:13.077475 iDelay=195, Bit 0, Center 114 (51 ~ 178) 128
3034 23:03:13.080860 iDelay=195, Bit 1, Center 116 (47 ~ 186) 140
3035 23:03:13.084620 iDelay=195, Bit 2, Center 112 (47 ~ 178) 132
3036 23:03:13.087713 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3037 23:03:13.090543 iDelay=195, Bit 4, Center 118 (51 ~ 186) 136
3038 23:03:13.097548 iDelay=195, Bit 5, Center 108 (43 ~ 174) 132
3039 23:03:13.100675 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3040 23:03:13.103847 iDelay=195, Bit 7, Center 122 (55 ~ 190) 136
3041 23:03:13.107434 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3042 23:03:13.110758 iDelay=195, Bit 9, Center 92 (27 ~ 158) 132
3043 23:03:13.114422 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3044 23:03:13.120400 iDelay=195, Bit 11, Center 102 (35 ~ 170) 136
3045 23:03:13.123894 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3046 23:03:13.127613 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
3047 23:03:13.130738 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3048 23:03:13.137126 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3049 23:03:13.137279 ==
3050 23:03:13.140229 Dram Type= 6, Freq= 0, CH_0, rank 1
3051 23:03:13.144124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3052 23:03:13.144254 ==
3053 23:03:13.144344 DQS Delay:
3054 23:03:13.147226 DQS0 = 0, DQS1 = 0
3055 23:03:13.147345 DQM Delay:
3056 23:03:13.150562 DQM0 = 116, DQM1 = 107
3057 23:03:13.150665 DQ Delay:
3058 23:03:13.153439 DQ0 =114, DQ1 =116, DQ2 =112, DQ3 =112
3059 23:03:13.157168 DQ4 =118, DQ5 =108, DQ6 =126, DQ7 =122
3060 23:03:13.160400 DQ8 =96, DQ9 =92, DQ10 =110, DQ11 =102
3061 23:03:13.163863 DQ12 =112, DQ13 =112, DQ14 =118, DQ15 =114
3062 23:03:13.164005
3063 23:03:13.164138
3064 23:03:13.173654 [DQSOSCAuto] RK1, (LSB)MR18= 0xfdfa, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 411 ps
3065 23:03:13.177329 CH0 RK1: MR19=303, MR18=FDFA
3066 23:03:13.183367 CH0_RK1: MR19=0x303, MR18=0xFDFA, DQSOSC=411, MR23=63, INC=38, DEC=25
3067 23:03:13.183504 [RxdqsGatingPostProcess] freq 1200
3068 23:03:13.189980 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3069 23:03:13.193765 best DQS0 dly(2T, 0.5T) = (0, 11)
3070 23:03:13.196804 best DQS1 dly(2T, 0.5T) = (0, 12)
3071 23:03:13.200029 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3072 23:03:13.203342 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3073 23:03:13.206645 best DQS0 dly(2T, 0.5T) = (0, 11)
3074 23:03:13.209896 best DQS1 dly(2T, 0.5T) = (0, 12)
3075 23:03:13.213005 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3076 23:03:13.216403 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3077 23:03:13.219986 Pre-setting of DQS Precalculation
3078 23:03:13.223243 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3079 23:03:13.223336 ==
3080 23:03:13.226452 Dram Type= 6, Freq= 0, CH_1, rank 0
3081 23:03:13.230098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3082 23:03:13.233256 ==
3083 23:03:13.236388 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3084 23:03:13.242923 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3085 23:03:13.251125 [CA 0] Center 38 (8~68) winsize 61
3086 23:03:13.254354 [CA 1] Center 37 (7~68) winsize 62
3087 23:03:13.257972 [CA 2] Center 35 (6~65) winsize 60
3088 23:03:13.261030 [CA 3] Center 34 (4~64) winsize 61
3089 23:03:13.264633 [CA 4] Center 34 (4~65) winsize 62
3090 23:03:13.267721 [CA 5] Center 34 (4~64) winsize 61
3091 23:03:13.267829
3092 23:03:13.270956 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3093 23:03:13.271065
3094 23:03:13.274486 [CATrainingPosCal] consider 1 rank data
3095 23:03:13.277699 u2DelayCellTimex100 = 270/100 ps
3096 23:03:13.280989 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3097 23:03:13.284584 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3098 23:03:13.290988 CA2 delay=35 (6~65),Diff = 1 PI (4 cell)
3099 23:03:13.294083 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
3100 23:03:13.297566 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3101 23:03:13.300959 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3102 23:03:13.301076
3103 23:03:13.304906 CA PerBit enable=1, Macro0, CA PI delay=34
3104 23:03:13.305037
3105 23:03:13.307699 [CBTSetCACLKResult] CA Dly = 34
3106 23:03:13.307804 CS Dly: 4 (0~35)
3107 23:03:13.310781 ==
3108 23:03:13.310862 Dram Type= 6, Freq= 0, CH_1, rank 1
3109 23:03:13.317602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3110 23:03:13.317723 ==
3111 23:03:13.320603 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3112 23:03:13.327284 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3113 23:03:13.336559 [CA 0] Center 37 (7~68) winsize 62
3114 23:03:13.340164 [CA 1] Center 38 (8~68) winsize 61
3115 23:03:13.343306 [CA 2] Center 34 (4~65) winsize 62
3116 23:03:13.346928 [CA 3] Center 33 (3~64) winsize 62
3117 23:03:13.350192 [CA 4] Center 34 (4~64) winsize 61
3118 23:03:13.353322 [CA 5] Center 33 (3~63) winsize 61
3119 23:03:13.353400
3120 23:03:13.356562 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3121 23:03:13.356685
3122 23:03:13.360328 [CATrainingPosCal] consider 2 rank data
3123 23:03:13.363682 u2DelayCellTimex100 = 270/100 ps
3124 23:03:13.366756 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3125 23:03:13.370263 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3126 23:03:13.377008 CA2 delay=35 (6~65),Diff = 2 PI (9 cell)
3127 23:03:13.380044 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3128 23:03:13.383013 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3129 23:03:13.387172 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3130 23:03:13.387304
3131 23:03:13.389613 CA PerBit enable=1, Macro0, CA PI delay=33
3132 23:03:13.389731
3133 23:03:13.393063 [CBTSetCACLKResult] CA Dly = 33
3134 23:03:13.393173 CS Dly: 6 (0~39)
3135 23:03:13.393274
3136 23:03:13.396645 ----->DramcWriteLeveling(PI) begin...
3137 23:03:13.399491 ==
3138 23:03:13.403666 Dram Type= 6, Freq= 0, CH_1, rank 0
3139 23:03:13.406541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3140 23:03:13.406651 ==
3141 23:03:13.409837 Write leveling (Byte 0): 24 => 24
3142 23:03:13.413030 Write leveling (Byte 1): 26 => 26
3143 23:03:13.416791 DramcWriteLeveling(PI) end<-----
3144 23:03:13.416901
3145 23:03:13.417000 ==
3146 23:03:13.419699 Dram Type= 6, Freq= 0, CH_1, rank 0
3147 23:03:13.422835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3148 23:03:13.422943 ==
3149 23:03:13.426031 [Gating] SW mode calibration
3150 23:03:13.432915 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3151 23:03:13.439691 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3152 23:03:13.442599 0 15 0 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
3153 23:03:13.446448 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3154 23:03:13.452720 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3155 23:03:13.455876 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3156 23:03:13.459505 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3157 23:03:13.465956 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3158 23:03:13.469336 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3159 23:03:13.472780 0 15 28 | B1->B0 | 2828 2525 | 0 0 | (1 0) (0 0)
3160 23:03:13.479595 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3161 23:03:13.482501 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3162 23:03:13.485713 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3163 23:03:13.492273 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3164 23:03:13.495753 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3165 23:03:13.499170 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3166 23:03:13.505396 1 0 24 | B1->B0 | 2626 3232 | 0 0 | (0 0) (0 0)
3167 23:03:13.509340 1 0 28 | B1->B0 | 3b3b 4444 | 0 1 | (1 1) (0 0)
3168 23:03:13.512167 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3169 23:03:13.519135 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3170 23:03:13.521891 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3171 23:03:13.525216 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3172 23:03:13.531981 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3173 23:03:13.535574 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3174 23:03:13.539049 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3175 23:03:13.541867 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3176 23:03:13.548602 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 23:03:13.551961 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3178 23:03:13.555226 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3179 23:03:13.561693 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3180 23:03:13.565069 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3181 23:03:13.568402 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3182 23:03:13.575083 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3183 23:03:13.578547 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3184 23:03:13.581681 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3185 23:03:13.588240 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3186 23:03:13.592140 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3187 23:03:13.595305 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3188 23:03:13.601661 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3189 23:03:13.605270 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3190 23:03:13.608623 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3191 23:03:13.615062 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3192 23:03:13.615185 Total UI for P1: 0, mck2ui 16
3193 23:03:13.621504 best dqsien dly found for B0: ( 1, 3, 24)
3194 23:03:13.624987 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3195 23:03:13.628139 Total UI for P1: 0, mck2ui 16
3196 23:03:13.631825 best dqsien dly found for B1: ( 1, 3, 28)
3197 23:03:13.634919 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3198 23:03:13.638316 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3199 23:03:13.638436
3200 23:03:13.642009 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3201 23:03:13.644773 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3202 23:03:13.648316 [Gating] SW calibration Done
3203 23:03:13.648423 ==
3204 23:03:13.651233 Dram Type= 6, Freq= 0, CH_1, rank 0
3205 23:03:13.654670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3206 23:03:13.658177 ==
3207 23:03:13.658291 RX Vref Scan: 0
3208 23:03:13.658390
3209 23:03:13.661178 RX Vref 0 -> 0, step: 1
3210 23:03:13.661288
3211 23:03:13.665189 RX Delay -40 -> 252, step: 8
3212 23:03:13.668259 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3213 23:03:13.671559 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3214 23:03:13.674826 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3215 23:03:13.678695 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3216 23:03:13.684402 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3217 23:03:13.687943 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3218 23:03:13.691212 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3219 23:03:13.694299 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3220 23:03:13.697795 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3221 23:03:13.704501 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3222 23:03:13.707591 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3223 23:03:13.711224 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3224 23:03:13.714549 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3225 23:03:13.717795 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3226 23:03:13.724315 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3227 23:03:13.728285 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3228 23:03:13.728370 ==
3229 23:03:13.730809 Dram Type= 6, Freq= 0, CH_1, rank 0
3230 23:03:13.734578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3231 23:03:13.734660 ==
3232 23:03:13.737539 DQS Delay:
3233 23:03:13.737636 DQS0 = 0, DQS1 = 0
3234 23:03:13.737730 DQM Delay:
3235 23:03:13.740873 DQM0 = 115, DQM1 = 112
3236 23:03:13.740973 DQ Delay:
3237 23:03:13.744388 DQ0 =123, DQ1 =111, DQ2 =103, DQ3 =115
3238 23:03:13.747615 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3239 23:03:13.754202 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3240 23:03:13.757530 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3241 23:03:13.757635
3242 23:03:13.757730
3243 23:03:13.757820 ==
3244 23:03:13.760528 Dram Type= 6, Freq= 0, CH_1, rank 0
3245 23:03:13.764035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3246 23:03:13.764140 ==
3247 23:03:13.764237
3248 23:03:13.764327
3249 23:03:13.767335 TX Vref Scan disable
3250 23:03:13.767441 == TX Byte 0 ==
3251 23:03:13.774297 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3252 23:03:13.777063 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3253 23:03:13.780734 == TX Byte 1 ==
3254 23:03:13.784040 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3255 23:03:13.787309 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3256 23:03:13.787413 ==
3257 23:03:13.790244 Dram Type= 6, Freq= 0, CH_1, rank 0
3258 23:03:13.794339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3259 23:03:13.794445 ==
3260 23:03:13.806939 TX Vref=22, minBit 3, minWin=24, winSum=407
3261 23:03:13.809923 TX Vref=24, minBit 9, minWin=24, winSum=409
3262 23:03:13.813352 TX Vref=26, minBit 9, minWin=25, winSum=420
3263 23:03:13.816662 TX Vref=28, minBit 9, minWin=24, winSum=421
3264 23:03:13.819901 TX Vref=30, minBit 9, minWin=24, winSum=427
3265 23:03:13.826521 TX Vref=32, minBit 9, minWin=24, winSum=426
3266 23:03:13.829969 [TxChooseVref] Worse bit 9, Min win 25, Win sum 420, Final Vref 26
3267 23:03:13.830077
3268 23:03:13.833444 Final TX Range 1 Vref 26
3269 23:03:13.833551
3270 23:03:13.833649 ==
3271 23:03:13.836908 Dram Type= 6, Freq= 0, CH_1, rank 0
3272 23:03:13.839798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3273 23:03:13.839875 ==
3274 23:03:13.843366
3275 23:03:13.843468
3276 23:03:13.843559 TX Vref Scan disable
3277 23:03:13.846720 == TX Byte 0 ==
3278 23:03:13.850074 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3279 23:03:13.853386 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3280 23:03:13.856559 == TX Byte 1 ==
3281 23:03:13.859846 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3282 23:03:13.866612 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3283 23:03:13.866701
3284 23:03:13.866781 [DATLAT]
3285 23:03:13.866844 Freq=1200, CH1 RK0
3286 23:03:13.866905
3287 23:03:13.869544 DATLAT Default: 0xd
3288 23:03:13.869627 0, 0xFFFF, sum = 0
3289 23:03:13.873061 1, 0xFFFF, sum = 0
3290 23:03:13.876680 2, 0xFFFF, sum = 0
3291 23:03:13.876766 3, 0xFFFF, sum = 0
3292 23:03:13.879704 4, 0xFFFF, sum = 0
3293 23:03:13.879790 5, 0xFFFF, sum = 0
3294 23:03:13.883191 6, 0xFFFF, sum = 0
3295 23:03:13.883277 7, 0xFFFF, sum = 0
3296 23:03:13.886141 8, 0xFFFF, sum = 0
3297 23:03:13.886261 9, 0xFFFF, sum = 0
3298 23:03:13.889798 10, 0xFFFF, sum = 0
3299 23:03:13.889884 11, 0xFFFF, sum = 0
3300 23:03:13.893302 12, 0x0, sum = 1
3301 23:03:13.893387 13, 0x0, sum = 2
3302 23:03:13.896222 14, 0x0, sum = 3
3303 23:03:13.896306 15, 0x0, sum = 4
3304 23:03:13.899573 best_step = 13
3305 23:03:13.899656
3306 23:03:13.899722 ==
3307 23:03:13.902867 Dram Type= 6, Freq= 0, CH_1, rank 0
3308 23:03:13.906588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3309 23:03:13.906678 ==
3310 23:03:13.906748 RX Vref Scan: 1
3311 23:03:13.906812
3312 23:03:13.909413 Set Vref Range= 32 -> 127
3313 23:03:13.909512
3314 23:03:13.912761 RX Vref 32 -> 127, step: 1
3315 23:03:13.912871
3316 23:03:13.916319 RX Delay -13 -> 252, step: 4
3317 23:03:13.916403
3318 23:03:13.919995 Set Vref, RX VrefLevel [Byte0]: 32
3319 23:03:13.922667 [Byte1]: 32
3320 23:03:13.922751
3321 23:03:13.925951 Set Vref, RX VrefLevel [Byte0]: 33
3322 23:03:13.929476 [Byte1]: 33
3323 23:03:13.933185
3324 23:03:13.933269 Set Vref, RX VrefLevel [Byte0]: 34
3325 23:03:13.936523 [Byte1]: 34
3326 23:03:13.940739
3327 23:03:13.940852 Set Vref, RX VrefLevel [Byte0]: 35
3328 23:03:13.944059 [Byte1]: 35
3329 23:03:13.949035
3330 23:03:13.949121 Set Vref, RX VrefLevel [Byte0]: 36
3331 23:03:13.952326 [Byte1]: 36
3332 23:03:13.956532
3333 23:03:13.956616 Set Vref, RX VrefLevel [Byte0]: 37
3334 23:03:13.960165 [Byte1]: 37
3335 23:03:13.964346
3336 23:03:13.964459 Set Vref, RX VrefLevel [Byte0]: 38
3337 23:03:13.967612 [Byte1]: 38
3338 23:03:13.972693
3339 23:03:13.972777 Set Vref, RX VrefLevel [Byte0]: 39
3340 23:03:13.975829 [Byte1]: 39
3341 23:03:13.980479
3342 23:03:13.980563 Set Vref, RX VrefLevel [Byte0]: 40
3343 23:03:13.983521 [Byte1]: 40
3344 23:03:13.988450
3345 23:03:13.988536 Set Vref, RX VrefLevel [Byte0]: 41
3346 23:03:13.991528 [Byte1]: 41
3347 23:03:13.996294
3348 23:03:13.996379 Set Vref, RX VrefLevel [Byte0]: 42
3349 23:03:13.999712 [Byte1]: 42
3350 23:03:14.004047
3351 23:03:14.004163 Set Vref, RX VrefLevel [Byte0]: 43
3352 23:03:14.007394 [Byte1]: 43
3353 23:03:14.012386
3354 23:03:14.012469 Set Vref, RX VrefLevel [Byte0]: 44
3355 23:03:14.015351 [Byte1]: 44
3356 23:03:14.019591
3357 23:03:14.019675 Set Vref, RX VrefLevel [Byte0]: 45
3358 23:03:14.022933 [Byte1]: 45
3359 23:03:14.027297
3360 23:03:14.027379 Set Vref, RX VrefLevel [Byte0]: 46
3361 23:03:14.031178 [Byte1]: 46
3362 23:03:14.035508
3363 23:03:14.035590 Set Vref, RX VrefLevel [Byte0]: 47
3364 23:03:14.038527 [Byte1]: 47
3365 23:03:14.043222
3366 23:03:14.046519 Set Vref, RX VrefLevel [Byte0]: 48
3367 23:03:14.049926 [Byte1]: 48
3368 23:03:14.050009
3369 23:03:14.052931 Set Vref, RX VrefLevel [Byte0]: 49
3370 23:03:14.056395 [Byte1]: 49
3371 23:03:14.056502
3372 23:03:14.059669 Set Vref, RX VrefLevel [Byte0]: 50
3373 23:03:14.062718 [Byte1]: 50
3374 23:03:14.066960
3375 23:03:14.067043 Set Vref, RX VrefLevel [Byte0]: 51
3376 23:03:14.070381 [Byte1]: 51
3377 23:03:14.074670
3378 23:03:14.074753 Set Vref, RX VrefLevel [Byte0]: 52
3379 23:03:14.078371 [Byte1]: 52
3380 23:03:14.082462
3381 23:03:14.082553 Set Vref, RX VrefLevel [Byte0]: 53
3382 23:03:14.085956 [Byte1]: 53
3383 23:03:14.090621
3384 23:03:14.090711 Set Vref, RX VrefLevel [Byte0]: 54
3385 23:03:14.093815 [Byte1]: 54
3386 23:03:14.098280
3387 23:03:14.098369 Set Vref, RX VrefLevel [Byte0]: 55
3388 23:03:14.101670 [Byte1]: 55
3389 23:03:14.106372
3390 23:03:14.106458 Set Vref, RX VrefLevel [Byte0]: 56
3391 23:03:14.109307 [Byte1]: 56
3392 23:03:14.113960
3393 23:03:14.114061 Set Vref, RX VrefLevel [Byte0]: 57
3394 23:03:14.117618 [Byte1]: 57
3395 23:03:14.121817
3396 23:03:14.121898 Set Vref, RX VrefLevel [Byte0]: 58
3397 23:03:14.125445 [Byte1]: 58
3398 23:03:14.129800
3399 23:03:14.129875 Set Vref, RX VrefLevel [Byte0]: 59
3400 23:03:14.133198 [Byte1]: 59
3401 23:03:14.138122
3402 23:03:14.138225 Set Vref, RX VrefLevel [Byte0]: 60
3403 23:03:14.140810 [Byte1]: 60
3404 23:03:14.145683
3405 23:03:14.145759 Set Vref, RX VrefLevel [Byte0]: 61
3406 23:03:14.148970 [Byte1]: 61
3407 23:03:14.153419
3408 23:03:14.153496 Set Vref, RX VrefLevel [Byte0]: 62
3409 23:03:14.156695 [Byte1]: 62
3410 23:03:14.161522
3411 23:03:14.161597 Set Vref, RX VrefLevel [Byte0]: 63
3412 23:03:14.164960 [Byte1]: 63
3413 23:03:14.169499
3414 23:03:14.169583 Set Vref, RX VrefLevel [Byte0]: 64
3415 23:03:14.172547 [Byte1]: 64
3416 23:03:14.177375
3417 23:03:14.177454 Final RX Vref Byte 0 = 51 to rank0
3418 23:03:14.180330 Final RX Vref Byte 1 = 52 to rank0
3419 23:03:14.183771 Final RX Vref Byte 0 = 51 to rank1
3420 23:03:14.187343 Final RX Vref Byte 1 = 52 to rank1==
3421 23:03:14.190464 Dram Type= 6, Freq= 0, CH_1, rank 0
3422 23:03:14.197323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3423 23:03:14.197403 ==
3424 23:03:14.197497 DQS Delay:
3425 23:03:14.197578 DQS0 = 0, DQS1 = 0
3426 23:03:14.200491 DQM Delay:
3427 23:03:14.200589 DQM0 = 114, DQM1 = 113
3428 23:03:14.204057 DQ Delay:
3429 23:03:14.207109 DQ0 =120, DQ1 =110, DQ2 =104, DQ3 =114
3430 23:03:14.210572 DQ4 =110, DQ5 =122, DQ6 =126, DQ7 =110
3431 23:03:14.213451 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =108
3432 23:03:14.216973 DQ12 =122, DQ13 =120, DQ14 =120, DQ15 =120
3433 23:03:14.217104
3434 23:03:14.217187
3435 23:03:14.227192 [DQSOSCAuto] RK0, (LSB)MR18= 0xf603, (MSB)MR19= 0x304, tDQSOscB0 = 408 ps tDQSOscB1 = 414 ps
3436 23:03:14.227444 CH1 RK0: MR19=304, MR18=F603
3437 23:03:14.233568 CH1_RK0: MR19=0x304, MR18=0xF603, DQSOSC=408, MR23=63, INC=39, DEC=26
3438 23:03:14.233742
3439 23:03:14.236795 ----->DramcWriteLeveling(PI) begin...
3440 23:03:14.236887 ==
3441 23:03:14.240116 Dram Type= 6, Freq= 0, CH_1, rank 1
3442 23:03:14.246952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3443 23:03:14.247042 ==
3444 23:03:14.250093 Write leveling (Byte 0): 26 => 26
3445 23:03:14.250209 Write leveling (Byte 1): 29 => 29
3446 23:03:14.253752 DramcWriteLeveling(PI) end<-----
3447 23:03:14.253848
3448 23:03:14.256851 ==
3449 23:03:14.256942 Dram Type= 6, Freq= 0, CH_1, rank 1
3450 23:03:14.263232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3451 23:03:14.263352 ==
3452 23:03:14.266857 [Gating] SW mode calibration
3453 23:03:14.273398 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3454 23:03:14.276549 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3455 23:03:14.283161 0 15 0 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
3456 23:03:14.286512 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3457 23:03:14.289858 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3458 23:03:14.296758 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3459 23:03:14.300268 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3460 23:03:14.303278 0 15 20 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
3461 23:03:14.309794 0 15 24 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
3462 23:03:14.313332 0 15 28 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)
3463 23:03:14.316402 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3464 23:03:14.322795 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3465 23:03:14.326657 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3466 23:03:14.329836 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3467 23:03:14.336131 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3468 23:03:14.339594 1 0 20 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
3469 23:03:14.343058 1 0 24 | B1->B0 | 2727 4646 | 0 0 | (1 1) (0 0)
3470 23:03:14.349807 1 0 28 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
3471 23:03:14.353039 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3472 23:03:14.356292 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3473 23:03:14.362686 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3474 23:03:14.365968 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3475 23:03:14.369243 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3476 23:03:14.376246 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3477 23:03:14.379468 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3478 23:03:14.382212 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3479 23:03:14.389196 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3480 23:03:14.392658 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 23:03:14.395528 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 23:03:14.402488 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 23:03:14.405404 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 23:03:14.408778 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 23:03:14.415210 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 23:03:14.418905 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 23:03:14.421904 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 23:03:14.428935 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 23:03:14.432060 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3490 23:03:14.435587 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3491 23:03:14.441954 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 23:03:14.445157 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3493 23:03:14.448571 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3494 23:03:14.452024 Total UI for P1: 0, mck2ui 16
3495 23:03:14.454774 best dqsien dly found for B0: ( 1, 3, 22)
3496 23:03:14.461806 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3497 23:03:14.461925 Total UI for P1: 0, mck2ui 16
3498 23:03:14.465748 best dqsien dly found for B1: ( 1, 3, 24)
3499 23:03:14.471865 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3500 23:03:14.474741 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3501 23:03:14.474825
3502 23:03:14.478032 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3503 23:03:14.481430 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3504 23:03:14.484494 [Gating] SW calibration Done
3505 23:03:14.484609 ==
3506 23:03:14.487950 Dram Type= 6, Freq= 0, CH_1, rank 1
3507 23:03:14.491420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3508 23:03:14.491507 ==
3509 23:03:14.494586 RX Vref Scan: 0
3510 23:03:14.494672
3511 23:03:14.494740 RX Vref 0 -> 0, step: 1
3512 23:03:14.494803
3513 23:03:14.497967 RX Delay -40 -> 252, step: 8
3514 23:03:14.500929 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3515 23:03:14.507666 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3516 23:03:14.511137 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3517 23:03:14.514064 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3518 23:03:14.517596 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3519 23:03:14.521045 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3520 23:03:14.527745 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3521 23:03:14.530636 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3522 23:03:14.534242 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3523 23:03:14.537828 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3524 23:03:14.540522 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3525 23:03:14.547319 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3526 23:03:14.551422 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3527 23:03:14.554312 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3528 23:03:14.557693 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3529 23:03:14.563780 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3530 23:03:14.563895 ==
3531 23:03:14.567124 Dram Type= 6, Freq= 0, CH_1, rank 1
3532 23:03:14.570411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3533 23:03:14.570498 ==
3534 23:03:14.570579 DQS Delay:
3535 23:03:14.573862 DQS0 = 0, DQS1 = 0
3536 23:03:14.574021 DQM Delay:
3537 23:03:14.576956 DQM0 = 114, DQM1 = 111
3538 23:03:14.577097 DQ Delay:
3539 23:03:14.580116 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3540 23:03:14.583477 DQ4 =115, DQ5 =123, DQ6 =119, DQ7 =115
3541 23:03:14.586844 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =107
3542 23:03:14.590416 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3543 23:03:14.590543
3544 23:03:14.590654
3545 23:03:14.593878 ==
3546 23:03:14.596494 Dram Type= 6, Freq= 0, CH_1, rank 1
3547 23:03:14.600288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3548 23:03:14.600376 ==
3549 23:03:14.600443
3550 23:03:14.600505
3551 23:03:14.603693 TX Vref Scan disable
3552 23:03:14.603777 == TX Byte 0 ==
3553 23:03:14.609998 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3554 23:03:14.612886 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3555 23:03:14.612973 == TX Byte 1 ==
3556 23:03:14.619439 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3557 23:03:14.623146 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3558 23:03:14.623232 ==
3559 23:03:14.626597 Dram Type= 6, Freq= 0, CH_1, rank 1
3560 23:03:14.629810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3561 23:03:14.629894 ==
3562 23:03:14.641693 TX Vref=22, minBit 9, minWin=25, winSum=422
3563 23:03:14.645170 TX Vref=24, minBit 3, minWin=25, winSum=422
3564 23:03:14.649476 TX Vref=26, minBit 1, minWin=26, winSum=429
3565 23:03:14.651892 TX Vref=28, minBit 2, minWin=26, winSum=431
3566 23:03:14.654798 TX Vref=30, minBit 1, minWin=26, winSum=431
3567 23:03:14.661448 TX Vref=32, minBit 1, minWin=26, winSum=431
3568 23:03:14.665324 [TxChooseVref] Worse bit 2, Min win 26, Win sum 431, Final Vref 28
3569 23:03:14.665410
3570 23:03:14.668396 Final TX Range 1 Vref 28
3571 23:03:14.668506
3572 23:03:14.668603 ==
3573 23:03:14.671450 Dram Type= 6, Freq= 0, CH_1, rank 1
3574 23:03:14.677746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3575 23:03:14.677831 ==
3576 23:03:14.677946
3577 23:03:14.678007
3578 23:03:14.678065 TX Vref Scan disable
3579 23:03:14.681861 == TX Byte 0 ==
3580 23:03:14.685075 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3581 23:03:14.691712 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3582 23:03:14.691795 == TX Byte 1 ==
3583 23:03:14.694848 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3584 23:03:14.701727 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3585 23:03:14.701809
3586 23:03:14.701904 [DATLAT]
3587 23:03:14.701964 Freq=1200, CH1 RK1
3588 23:03:14.702023
3589 23:03:14.704946 DATLAT Default: 0xd
3590 23:03:14.708067 0, 0xFFFF, sum = 0
3591 23:03:14.708192 1, 0xFFFF, sum = 0
3592 23:03:14.711660 2, 0xFFFF, sum = 0
3593 23:03:14.711775 3, 0xFFFF, sum = 0
3594 23:03:14.714369 4, 0xFFFF, sum = 0
3595 23:03:14.714452 5, 0xFFFF, sum = 0
3596 23:03:14.718370 6, 0xFFFF, sum = 0
3597 23:03:14.718476 7, 0xFFFF, sum = 0
3598 23:03:14.721822 8, 0xFFFF, sum = 0
3599 23:03:14.721921 9, 0xFFFF, sum = 0
3600 23:03:14.724266 10, 0xFFFF, sum = 0
3601 23:03:14.724349 11, 0xFFFF, sum = 0
3602 23:03:14.728043 12, 0x0, sum = 1
3603 23:03:14.728126 13, 0x0, sum = 2
3604 23:03:14.730884 14, 0x0, sum = 3
3605 23:03:14.730966 15, 0x0, sum = 4
3606 23:03:14.734394 best_step = 13
3607 23:03:14.734475
3608 23:03:14.734540 ==
3609 23:03:14.737637 Dram Type= 6, Freq= 0, CH_1, rank 1
3610 23:03:14.741221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3611 23:03:14.741304 ==
3612 23:03:14.744119 RX Vref Scan: 0
3613 23:03:14.744200
3614 23:03:14.744280 RX Vref 0 -> 0, step: 1
3615 23:03:14.744353
3616 23:03:14.747421 RX Delay -13 -> 252, step: 4
3617 23:03:14.754378 iDelay=195, Bit 0, Center 116 (47 ~ 186) 140
3618 23:03:14.757676 iDelay=195, Bit 1, Center 110 (39 ~ 182) 144
3619 23:03:14.760653 iDelay=195, Bit 2, Center 106 (39 ~ 174) 136
3620 23:03:14.764591 iDelay=195, Bit 3, Center 114 (47 ~ 182) 136
3621 23:03:14.767638 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3622 23:03:14.773759 iDelay=195, Bit 5, Center 122 (51 ~ 194) 144
3623 23:03:14.777125 iDelay=195, Bit 6, Center 122 (55 ~ 190) 136
3624 23:03:14.780530 iDelay=195, Bit 7, Center 110 (39 ~ 182) 144
3625 23:03:14.783982 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3626 23:03:14.786845 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3627 23:03:14.794042 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3628 23:03:14.797129 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3629 23:03:14.800117 iDelay=195, Bit 12, Center 120 (59 ~ 182) 124
3630 23:03:14.803644 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3631 23:03:14.810199 iDelay=195, Bit 14, Center 116 (55 ~ 178) 124
3632 23:03:14.813611 iDelay=195, Bit 15, Center 122 (59 ~ 186) 128
3633 23:03:14.813693 ==
3634 23:03:14.816764 Dram Type= 6, Freq= 0, CH_1, rank 1
3635 23:03:14.820130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3636 23:03:14.820212 ==
3637 23:03:14.823391 DQS Delay:
3638 23:03:14.823472 DQS0 = 0, DQS1 = 0
3639 23:03:14.823535 DQM Delay:
3640 23:03:14.826840 DQM0 = 114, DQM1 = 112
3641 23:03:14.826921 DQ Delay:
3642 23:03:14.829697 DQ0 =116, DQ1 =110, DQ2 =106, DQ3 =114
3643 23:03:14.832984 DQ4 =112, DQ5 =122, DQ6 =122, DQ7 =110
3644 23:03:14.839531 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =106
3645 23:03:14.842947 DQ12 =120, DQ13 =118, DQ14 =116, DQ15 =122
3646 23:03:14.843027
3647 23:03:14.843092
3648 23:03:14.849768 [DQSOSCAuto] RK1, (LSB)MR18= 0xf90b, (MSB)MR19= 0x304, tDQSOscB0 = 405 ps tDQSOscB1 = 412 ps
3649 23:03:14.853385 CH1 RK1: MR19=304, MR18=F90B
3650 23:03:14.859278 CH1_RK1: MR19=0x304, MR18=0xF90B, DQSOSC=405, MR23=63, INC=39, DEC=26
3651 23:03:14.862683 [RxdqsGatingPostProcess] freq 1200
3652 23:03:14.869644 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3653 23:03:14.869726 best DQS0 dly(2T, 0.5T) = (0, 11)
3654 23:03:14.872401 best DQS1 dly(2T, 0.5T) = (0, 11)
3655 23:03:14.875836 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3656 23:03:14.879266 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3657 23:03:14.882361 best DQS0 dly(2T, 0.5T) = (0, 11)
3658 23:03:14.885469 best DQS1 dly(2T, 0.5T) = (0, 11)
3659 23:03:14.888789 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3660 23:03:14.892286 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3661 23:03:14.895837 Pre-setting of DQS Precalculation
3662 23:03:14.902073 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3663 23:03:14.909038 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3664 23:03:14.915376 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3665 23:03:14.915460
3666 23:03:14.915542
3667 23:03:14.918802 [Calibration Summary] 2400 Mbps
3668 23:03:14.918877 CH 0, Rank 0
3669 23:03:14.922050 SW Impedance : PASS
3670 23:03:14.925723 DUTY Scan : NO K
3671 23:03:14.925795 ZQ Calibration : PASS
3672 23:03:14.928543 Jitter Meter : NO K
3673 23:03:14.932152 CBT Training : PASS
3674 23:03:14.932225 Write leveling : PASS
3675 23:03:14.935021 RX DQS gating : PASS
3676 23:03:14.938549 RX DQ/DQS(RDDQC) : PASS
3677 23:03:14.938617 TX DQ/DQS : PASS
3678 23:03:14.941994 RX DATLAT : PASS
3679 23:03:14.945316 RX DQ/DQS(Engine): PASS
3680 23:03:14.945390 TX OE : NO K
3681 23:03:14.945466 All Pass.
3682 23:03:14.948268
3683 23:03:14.948361 CH 0, Rank 1
3684 23:03:14.952035 SW Impedance : PASS
3685 23:03:14.952106 DUTY Scan : NO K
3686 23:03:14.955022 ZQ Calibration : PASS
3687 23:03:14.958143 Jitter Meter : NO K
3688 23:03:14.958259 CBT Training : PASS
3689 23:03:14.961364 Write leveling : PASS
3690 23:03:14.961460 RX DQS gating : PASS
3691 23:03:14.964800 RX DQ/DQS(RDDQC) : PASS
3692 23:03:14.967822 TX DQ/DQS : PASS
3693 23:03:14.967894 RX DATLAT : PASS
3694 23:03:14.971361 RX DQ/DQS(Engine): PASS
3695 23:03:14.974568 TX OE : NO K
3696 23:03:14.974651 All Pass.
3697 23:03:14.974717
3698 23:03:14.974777 CH 1, Rank 0
3699 23:03:14.977696 SW Impedance : PASS
3700 23:03:14.981042 DUTY Scan : NO K
3701 23:03:14.981124 ZQ Calibration : PASS
3702 23:03:14.984576 Jitter Meter : NO K
3703 23:03:14.987907 CBT Training : PASS
3704 23:03:14.987989 Write leveling : PASS
3705 23:03:14.991194 RX DQS gating : PASS
3706 23:03:14.994520 RX DQ/DQS(RDDQC) : PASS
3707 23:03:14.994602 TX DQ/DQS : PASS
3708 23:03:14.997694 RX DATLAT : PASS
3709 23:03:15.001347 RX DQ/DQS(Engine): PASS
3710 23:03:15.001429 TX OE : NO K
3711 23:03:15.004584 All Pass.
3712 23:03:15.004669
3713 23:03:15.004767 CH 1, Rank 1
3714 23:03:15.008013 SW Impedance : PASS
3715 23:03:15.008095 DUTY Scan : NO K
3716 23:03:15.011296 ZQ Calibration : PASS
3717 23:03:15.014383 Jitter Meter : NO K
3718 23:03:15.014465 CBT Training : PASS
3719 23:03:15.017291 Write leveling : PASS
3720 23:03:15.020607 RX DQS gating : PASS
3721 23:03:15.020688 RX DQ/DQS(RDDQC) : PASS
3722 23:03:15.024086 TX DQ/DQS : PASS
3723 23:03:15.027463 RX DATLAT : PASS
3724 23:03:15.027545 RX DQ/DQS(Engine): PASS
3725 23:03:15.030514 TX OE : NO K
3726 23:03:15.030595 All Pass.
3727 23:03:15.030661
3728 23:03:15.034195 DramC Write-DBI off
3729 23:03:15.037525 PER_BANK_REFRESH: Hybrid Mode
3730 23:03:15.037607 TX_TRACKING: ON
3731 23:03:15.047494 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3732 23:03:15.050889 [FAST_K] Save calibration result to emmc
3733 23:03:15.053688 dramc_set_vcore_voltage set vcore to 650000
3734 23:03:15.057385 Read voltage for 600, 5
3735 23:03:15.057467 Vio18 = 0
3736 23:03:15.057532 Vcore = 650000
3737 23:03:15.060639 Vdram = 0
3738 23:03:15.060721 Vddq = 0
3739 23:03:15.060786 Vmddr = 0
3740 23:03:15.067326 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3741 23:03:15.070772 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3742 23:03:15.073613 MEM_TYPE=3, freq_sel=19
3743 23:03:15.077093 sv_algorithm_assistance_LP4_1600
3744 23:03:15.080534 ============ PULL DRAM RESETB DOWN ============
3745 23:03:15.083606 ========== PULL DRAM RESETB DOWN end =========
3746 23:03:15.090112 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3747 23:03:15.093738 ===================================
3748 23:03:15.093877 LPDDR4 DRAM CONFIGURATION
3749 23:03:15.097334 ===================================
3750 23:03:15.100205 EX_ROW_EN[0] = 0x0
3751 23:03:15.103553 EX_ROW_EN[1] = 0x0
3752 23:03:15.103641 LP4Y_EN = 0x0
3753 23:03:15.106815 WORK_FSP = 0x0
3754 23:03:15.106885 WL = 0x2
3755 23:03:15.110054 RL = 0x2
3756 23:03:15.110154 BL = 0x2
3757 23:03:15.113624 RPST = 0x0
3758 23:03:15.113718 RD_PRE = 0x0
3759 23:03:15.116666 WR_PRE = 0x1
3760 23:03:15.116767 WR_PST = 0x0
3761 23:03:15.119851 DBI_WR = 0x0
3762 23:03:15.119952 DBI_RD = 0x0
3763 23:03:15.123223 OTF = 0x1
3764 23:03:15.126428 ===================================
3765 23:03:15.129819 ===================================
3766 23:03:15.129921 ANA top config
3767 23:03:15.133134 ===================================
3768 23:03:15.136562 DLL_ASYNC_EN = 0
3769 23:03:15.139368 ALL_SLAVE_EN = 1
3770 23:03:15.142799 NEW_RANK_MODE = 1
3771 23:03:15.146009 DLL_IDLE_MODE = 1
3772 23:03:15.146150 LP45_APHY_COMB_EN = 1
3773 23:03:15.149383 TX_ODT_DIS = 1
3774 23:03:15.152735 NEW_8X_MODE = 1
3775 23:03:15.155805 ===================================
3776 23:03:15.158945 ===================================
3777 23:03:15.162683 data_rate = 1200
3778 23:03:15.166067 CKR = 1
3779 23:03:15.166166 DQ_P2S_RATIO = 8
3780 23:03:15.169367 ===================================
3781 23:03:15.172673 CA_P2S_RATIO = 8
3782 23:03:15.176135 DQ_CA_OPEN = 0
3783 23:03:15.178985 DQ_SEMI_OPEN = 0
3784 23:03:15.182554 CA_SEMI_OPEN = 0
3785 23:03:15.185922 CA_FULL_RATE = 0
3786 23:03:15.189052 DQ_CKDIV4_EN = 1
3787 23:03:15.189153 CA_CKDIV4_EN = 1
3788 23:03:15.191860 CA_PREDIV_EN = 0
3789 23:03:15.195767 PH8_DLY = 0
3790 23:03:15.198533 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3791 23:03:15.201966 DQ_AAMCK_DIV = 4
3792 23:03:15.205089 CA_AAMCK_DIV = 4
3793 23:03:15.205196 CA_ADMCK_DIV = 4
3794 23:03:15.208375 DQ_TRACK_CA_EN = 0
3795 23:03:15.212044 CA_PICK = 600
3796 23:03:15.215213 CA_MCKIO = 600
3797 23:03:15.218775 MCKIO_SEMI = 0
3798 23:03:15.221719 PLL_FREQ = 2288
3799 23:03:15.225045 DQ_UI_PI_RATIO = 32
3800 23:03:15.225144 CA_UI_PI_RATIO = 0
3801 23:03:15.228019 ===================================
3802 23:03:15.231526 ===================================
3803 23:03:15.234833 memory_type:LPDDR4
3804 23:03:15.238465 GP_NUM : 10
3805 23:03:15.238541 SRAM_EN : 1
3806 23:03:15.241334 MD32_EN : 0
3807 23:03:15.244993 ===================================
3808 23:03:15.248320 [ANA_INIT] >>>>>>>>>>>>>>
3809 23:03:15.251447 <<<<<< [CONFIGURE PHASE]: ANA_TX
3810 23:03:15.254786 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3811 23:03:15.257840 ===================================
3812 23:03:15.261322 data_rate = 1200,PCW = 0X5800
3813 23:03:15.261400 ===================================
3814 23:03:15.267829 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3815 23:03:15.270957 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3816 23:03:15.277854 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3817 23:03:15.281161 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3818 23:03:15.284172 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3819 23:03:15.287515 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3820 23:03:15.290853 [ANA_INIT] flow start
3821 23:03:15.293854 [ANA_INIT] PLL >>>>>>>>
3822 23:03:15.293958 [ANA_INIT] PLL <<<<<<<<
3823 23:03:15.297412 [ANA_INIT] MIDPI >>>>>>>>
3824 23:03:15.300435 [ANA_INIT] MIDPI <<<<<<<<
3825 23:03:15.303950 [ANA_INIT] DLL >>>>>>>>
3826 23:03:15.304058 [ANA_INIT] flow end
3827 23:03:15.307622 ============ LP4 DIFF to SE enter ============
3828 23:03:15.313650 ============ LP4 DIFF to SE exit ============
3829 23:03:15.313756 [ANA_INIT] <<<<<<<<<<<<<
3830 23:03:15.317814 [Flow] Enable top DCM control >>>>>
3831 23:03:15.320196 [Flow] Enable top DCM control <<<<<
3832 23:03:15.323417 Enable DLL master slave shuffle
3833 23:03:15.330342 ==============================================================
3834 23:03:15.330414 Gating Mode config
3835 23:03:15.336831 ==============================================================
3836 23:03:15.340508 Config description:
3837 23:03:15.350614 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3838 23:03:15.356891 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3839 23:03:15.360309 SELPH_MODE 0: By rank 1: By Phase
3840 23:03:15.366793 ==============================================================
3841 23:03:15.369666 GAT_TRACK_EN = 1
3842 23:03:15.372995 RX_GATING_MODE = 2
3843 23:03:15.376139 RX_GATING_TRACK_MODE = 2
3844 23:03:15.376238 SELPH_MODE = 1
3845 23:03:15.379577 PICG_EARLY_EN = 1
3846 23:03:15.383157 VALID_LAT_VALUE = 1
3847 23:03:15.389543 ==============================================================
3848 23:03:15.393379 Enter into Gating configuration >>>>
3849 23:03:15.396289 Exit from Gating configuration <<<<
3850 23:03:15.399558 Enter into DVFS_PRE_config >>>>>
3851 23:03:15.409570 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3852 23:03:15.412409 Exit from DVFS_PRE_config <<<<<
3853 23:03:15.415941 Enter into PICG configuration >>>>
3854 23:03:15.419224 Exit from PICG configuration <<<<
3855 23:03:15.422687 [RX_INPUT] configuration >>>>>
3856 23:03:15.425655 [RX_INPUT] configuration <<<<<
3857 23:03:15.428996 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3858 23:03:15.435912 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3859 23:03:15.442445 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3860 23:03:15.448930 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3861 23:03:15.455915 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3862 23:03:15.462072 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3863 23:03:15.465551 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3864 23:03:15.468368 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3865 23:03:15.471953 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3866 23:03:15.478813 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3867 23:03:15.481893 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3868 23:03:15.485259 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3869 23:03:15.488378 ===================================
3870 23:03:15.492035 LPDDR4 DRAM CONFIGURATION
3871 23:03:15.494759 ===================================
3872 23:03:15.494858 EX_ROW_EN[0] = 0x0
3873 23:03:15.498287 EX_ROW_EN[1] = 0x0
3874 23:03:15.501836 LP4Y_EN = 0x0
3875 23:03:15.501939 WORK_FSP = 0x0
3876 23:03:15.504825 WL = 0x2
3877 23:03:15.504923 RL = 0x2
3878 23:03:15.507926 BL = 0x2
3879 23:03:15.508023 RPST = 0x0
3880 23:03:15.511233 RD_PRE = 0x0
3881 23:03:15.511321 WR_PRE = 0x1
3882 23:03:15.514667 WR_PST = 0x0
3883 23:03:15.514756 DBI_WR = 0x0
3884 23:03:15.517900 DBI_RD = 0x0
3885 23:03:15.518000 OTF = 0x1
3886 23:03:15.521095 ===================================
3887 23:03:15.524486 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3888 23:03:15.531378 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3889 23:03:15.534455 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3890 23:03:15.537764 ===================================
3891 23:03:15.540607 LPDDR4 DRAM CONFIGURATION
3892 23:03:15.544485 ===================================
3893 23:03:15.544588 EX_ROW_EN[0] = 0x10
3894 23:03:15.547437 EX_ROW_EN[1] = 0x0
3895 23:03:15.550877 LP4Y_EN = 0x0
3896 23:03:15.551011 WORK_FSP = 0x0
3897 23:03:15.554419 WL = 0x2
3898 23:03:15.554492 RL = 0x2
3899 23:03:15.557145 BL = 0x2
3900 23:03:15.557220 RPST = 0x0
3901 23:03:15.560672 RD_PRE = 0x0
3902 23:03:15.560772 WR_PRE = 0x1
3903 23:03:15.563753 WR_PST = 0x0
3904 23:03:15.563873 DBI_WR = 0x0
3905 23:03:15.567448 DBI_RD = 0x0
3906 23:03:15.567549 OTF = 0x1
3907 23:03:15.570615 ===================================
3908 23:03:15.577043 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3909 23:03:15.581693 nWR fixed to 30
3910 23:03:15.584888 [ModeRegInit_LP4] CH0 RK0
3911 23:03:15.584989 [ModeRegInit_LP4] CH0 RK1
3912 23:03:15.588292 [ModeRegInit_LP4] CH1 RK0
3913 23:03:15.591562 [ModeRegInit_LP4] CH1 RK1
3914 23:03:15.591707 match AC timing 17
3915 23:03:15.598288 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3916 23:03:15.601721 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3917 23:03:15.605139 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3918 23:03:15.611382 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3919 23:03:15.614609 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3920 23:03:15.614686 ==
3921 23:03:15.617906 Dram Type= 6, Freq= 0, CH_0, rank 0
3922 23:03:15.621357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3923 23:03:15.624333 ==
3924 23:03:15.627521 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3925 23:03:15.634044 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3926 23:03:15.637773 [CA 0] Center 36 (6~67) winsize 62
3927 23:03:15.641324 [CA 1] Center 36 (6~66) winsize 61
3928 23:03:15.644358 [CA 2] Center 34 (3~65) winsize 63
3929 23:03:15.647741 [CA 3] Center 34 (3~65) winsize 63
3930 23:03:15.650793 [CA 4] Center 33 (3~64) winsize 62
3931 23:03:15.654272 [CA 5] Center 33 (3~64) winsize 62
3932 23:03:15.654362
3933 23:03:15.657140 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3934 23:03:15.657242
3935 23:03:15.661096 [CATrainingPosCal] consider 1 rank data
3936 23:03:15.663864 u2DelayCellTimex100 = 270/100 ps
3937 23:03:15.667230 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3938 23:03:15.670851 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3939 23:03:15.673899 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
3940 23:03:15.680609 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3941 23:03:15.684091 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3942 23:03:15.687054 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3943 23:03:15.687153
3944 23:03:15.690356 CA PerBit enable=1, Macro0, CA PI delay=33
3945 23:03:15.690430
3946 23:03:15.693493 [CBTSetCACLKResult] CA Dly = 33
3947 23:03:15.693591 CS Dly: 5 (0~36)
3948 23:03:15.693679 ==
3949 23:03:15.697202 Dram Type= 6, Freq= 0, CH_0, rank 1
3950 23:03:15.703690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3951 23:03:15.703794 ==
3952 23:03:15.707228 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3953 23:03:15.713615 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3954 23:03:15.717083 [CA 0] Center 36 (6~67) winsize 62
3955 23:03:15.720204 [CA 1] Center 36 (6~67) winsize 62
3956 23:03:15.723779 [CA 2] Center 34 (4~65) winsize 62
3957 23:03:15.727195 [CA 3] Center 34 (4~65) winsize 62
3958 23:03:15.730449 [CA 4] Center 34 (3~65) winsize 63
3959 23:03:15.733389 [CA 5] Center 33 (3~64) winsize 62
3960 23:03:15.733487
3961 23:03:15.736553 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3962 23:03:15.736635
3963 23:03:15.739947 [CATrainingPosCal] consider 2 rank data
3964 23:03:15.743302 u2DelayCellTimex100 = 270/100 ps
3965 23:03:15.750109 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3966 23:03:15.753284 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3967 23:03:15.756394 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3968 23:03:15.760048 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3969 23:03:15.763202 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3970 23:03:15.766670 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3971 23:03:15.766746
3972 23:03:15.769936 CA PerBit enable=1, Macro0, CA PI delay=33
3973 23:03:15.770041
3974 23:03:15.773267 [CBTSetCACLKResult] CA Dly = 33
3975 23:03:15.776105 CS Dly: 6 (0~38)
3976 23:03:15.776218
3977 23:03:15.779676 ----->DramcWriteLeveling(PI) begin...
3978 23:03:15.779794 ==
3979 23:03:15.783078 Dram Type= 6, Freq= 0, CH_0, rank 0
3980 23:03:15.786521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3981 23:03:15.786623 ==
3982 23:03:15.789941 Write leveling (Byte 0): 33 => 33
3983 23:03:15.793005 Write leveling (Byte 1): 29 => 29
3984 23:03:15.796059 DramcWriteLeveling(PI) end<-----
3985 23:03:15.796154
3986 23:03:15.796243 ==
3987 23:03:15.799372 Dram Type= 6, Freq= 0, CH_0, rank 0
3988 23:03:15.803176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3989 23:03:15.803259 ==
3990 23:03:15.806070 [Gating] SW mode calibration
3991 23:03:15.812575 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3992 23:03:15.819248 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3993 23:03:15.822820 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3994 23:03:15.825632 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3995 23:03:15.832162 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3996 23:03:15.835458 0 9 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
3997 23:03:15.838722 0 9 16 | B1->B0 | 2e2e 2525 | 0 0 | (1 0) (0 0)
3998 23:03:15.845812 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3999 23:03:15.848430 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4000 23:03:15.855574 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4001 23:03:15.858948 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4002 23:03:15.861844 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4003 23:03:15.868720 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4004 23:03:15.872064 0 10 12 | B1->B0 | 2424 3131 | 0 0 | (0 0) (1 1)
4005 23:03:15.874946 0 10 16 | B1->B0 | 3c3c 4545 | 0 1 | (0 0) (0 0)
4006 23:03:15.878413 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4007 23:03:15.885160 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4008 23:03:15.888860 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4009 23:03:15.894664 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4010 23:03:15.898364 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4011 23:03:15.901322 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4012 23:03:15.907730 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4013 23:03:15.911378 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4014 23:03:15.914216 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 23:03:15.920920 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 23:03:15.924094 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 23:03:15.927532 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 23:03:15.934247 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 23:03:15.937662 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 23:03:15.941226 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 23:03:15.947190 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 23:03:15.950644 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 23:03:15.954190 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 23:03:15.960690 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 23:03:15.964022 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 23:03:15.967015 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 23:03:15.973743 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 23:03:15.977378 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4029 23:03:15.980209 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4030 23:03:15.983876 Total UI for P1: 0, mck2ui 16
4031 23:03:15.987368 best dqsien dly found for B0: ( 0, 13, 14)
4032 23:03:15.993416 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4033 23:03:15.993537 Total UI for P1: 0, mck2ui 16
4034 23:03:15.996895 best dqsien dly found for B1: ( 0, 13, 14)
4035 23:03:16.003743 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4036 23:03:16.006647 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4037 23:03:16.006720
4038 23:03:16.010282 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4039 23:03:16.013570 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4040 23:03:16.016374 [Gating] SW calibration Done
4041 23:03:16.016496 ==
4042 23:03:16.019617 Dram Type= 6, Freq= 0, CH_0, rank 0
4043 23:03:16.023041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4044 23:03:16.023150 ==
4045 23:03:16.026496 RX Vref Scan: 0
4046 23:03:16.026602
4047 23:03:16.026695 RX Vref 0 -> 0, step: 1
4048 23:03:16.026794
4049 23:03:16.029702 RX Delay -230 -> 252, step: 16
4050 23:03:16.036156 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4051 23:03:16.039750 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4052 23:03:16.043054 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4053 23:03:16.046040 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4054 23:03:16.052599 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4055 23:03:16.056135 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4056 23:03:16.059518 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4057 23:03:16.062470 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4058 23:03:16.065860 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4059 23:03:16.072413 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4060 23:03:16.075925 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4061 23:03:16.079277 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4062 23:03:16.082455 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4063 23:03:16.089352 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4064 23:03:16.092665 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4065 23:03:16.095538 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4066 23:03:16.095636 ==
4067 23:03:16.098586 Dram Type= 6, Freq= 0, CH_0, rank 0
4068 23:03:16.105632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4069 23:03:16.105736 ==
4070 23:03:16.105827 DQS Delay:
4071 23:03:16.109078 DQS0 = 0, DQS1 = 0
4072 23:03:16.109149 DQM Delay:
4073 23:03:16.109212 DQM0 = 41, DQM1 = 33
4074 23:03:16.111906 DQ Delay:
4075 23:03:16.115169 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4076 23:03:16.118477 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4077 23:03:16.121847 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4078 23:03:16.124750 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4079 23:03:16.124818
4080 23:03:16.124882
4081 23:03:16.124944 ==
4082 23:03:16.128222 Dram Type= 6, Freq= 0, CH_0, rank 0
4083 23:03:16.131872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4084 23:03:16.131973 ==
4085 23:03:16.132068
4086 23:03:16.132156
4087 23:03:16.135013 TX Vref Scan disable
4088 23:03:16.138075 == TX Byte 0 ==
4089 23:03:16.141230 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4090 23:03:16.144967 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4091 23:03:16.148128 == TX Byte 1 ==
4092 23:03:16.151113 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4093 23:03:16.154386 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4094 23:03:16.154459 ==
4095 23:03:16.158033 Dram Type= 6, Freq= 0, CH_0, rank 0
4096 23:03:16.164228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4097 23:03:16.164319 ==
4098 23:03:16.164410
4099 23:03:16.164474
4100 23:03:16.164560 TX Vref Scan disable
4101 23:03:16.168599 == TX Byte 0 ==
4102 23:03:16.171774 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4103 23:03:16.178591 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4104 23:03:16.178686 == TX Byte 1 ==
4105 23:03:16.181809 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4106 23:03:16.188682 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4107 23:03:16.188773
4108 23:03:16.188837 [DATLAT]
4109 23:03:16.188898 Freq=600, CH0 RK0
4110 23:03:16.188957
4111 23:03:16.191677 DATLAT Default: 0x9
4112 23:03:16.191750 0, 0xFFFF, sum = 0
4113 23:03:16.195250 1, 0xFFFF, sum = 0
4114 23:03:16.198392 2, 0xFFFF, sum = 0
4115 23:03:16.198514 3, 0xFFFF, sum = 0
4116 23:03:16.201464 4, 0xFFFF, sum = 0
4117 23:03:16.201567 5, 0xFFFF, sum = 0
4118 23:03:16.205146 6, 0xFFFF, sum = 0
4119 23:03:16.205247 7, 0xFFFF, sum = 0
4120 23:03:16.207964 8, 0x0, sum = 1
4121 23:03:16.208051 9, 0x0, sum = 2
4122 23:03:16.211324 10, 0x0, sum = 3
4123 23:03:16.211426 11, 0x0, sum = 4
4124 23:03:16.211519 best_step = 9
4125 23:03:16.211586
4126 23:03:16.214939 ==
4127 23:03:16.218236 Dram Type= 6, Freq= 0, CH_0, rank 0
4128 23:03:16.221735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4129 23:03:16.221836 ==
4130 23:03:16.221927 RX Vref Scan: 1
4131 23:03:16.222026
4132 23:03:16.224354 RX Vref 0 -> 0, step: 1
4133 23:03:16.224428
4134 23:03:16.227766 RX Delay -195 -> 252, step: 8
4135 23:03:16.227863
4136 23:03:16.231147 Set Vref, RX VrefLevel [Byte0]: 52
4137 23:03:16.234855 [Byte1]: 59
4138 23:03:16.234936
4139 23:03:16.237767 Final RX Vref Byte 0 = 52 to rank0
4140 23:03:16.241333 Final RX Vref Byte 1 = 59 to rank0
4141 23:03:16.244427 Final RX Vref Byte 0 = 52 to rank1
4142 23:03:16.247782 Final RX Vref Byte 1 = 59 to rank1==
4143 23:03:16.250697 Dram Type= 6, Freq= 0, CH_0, rank 0
4144 23:03:16.254342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4145 23:03:16.257362 ==
4146 23:03:16.257474 DQS Delay:
4147 23:03:16.257539 DQS0 = 0, DQS1 = 0
4148 23:03:16.260597 DQM Delay:
4149 23:03:16.260678 DQM0 = 42, DQM1 = 33
4150 23:03:16.264132 DQ Delay:
4151 23:03:16.267935 DQ0 =44, DQ1 =44, DQ2 =36, DQ3 =40
4152 23:03:16.268016 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =48
4153 23:03:16.270528 DQ8 =24, DQ9 =16, DQ10 =36, DQ11 =28
4154 23:03:16.277074 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4155 23:03:16.277171
4156 23:03:16.277236
4157 23:03:16.283908 [DQSOSCAuto] RK0, (LSB)MR18= 0x4e46, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps
4158 23:03:16.287223 CH0 RK0: MR19=808, MR18=4E46
4159 23:03:16.294040 CH0_RK0: MR19=0x808, MR18=0x4E46, DQSOSC=395, MR23=63, INC=168, DEC=112
4160 23:03:16.294137
4161 23:03:16.297328 ----->DramcWriteLeveling(PI) begin...
4162 23:03:16.297411 ==
4163 23:03:16.300031 Dram Type= 6, Freq= 0, CH_0, rank 1
4164 23:03:16.303640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4165 23:03:16.303722 ==
4166 23:03:16.307175 Write leveling (Byte 0): 35 => 35
4167 23:03:16.309980 Write leveling (Byte 1): 30 => 30
4168 23:03:16.313444 DramcWriteLeveling(PI) end<-----
4169 23:03:16.313527
4170 23:03:16.313611 ==
4171 23:03:16.316702 Dram Type= 6, Freq= 0, CH_0, rank 1
4172 23:03:16.320028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4173 23:03:16.323650 ==
4174 23:03:16.323731 [Gating] SW mode calibration
4175 23:03:16.329861 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4176 23:03:16.336412 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4177 23:03:16.340121 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4178 23:03:16.346457 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4179 23:03:16.349944 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4180 23:03:16.353074 0 9 12 | B1->B0 | 3333 2f2f | 1 1 | (1 1) (1 0)
4181 23:03:16.359390 0 9 16 | B1->B0 | 2f2f 2b2b | 0 0 | (1 1) (1 1)
4182 23:03:16.362706 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4183 23:03:16.365873 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4184 23:03:16.372531 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4185 23:03:16.376006 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4186 23:03:16.379595 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4187 23:03:16.386010 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4188 23:03:16.389459 0 10 12 | B1->B0 | 2626 3333 | 0 0 | (0 0) (0 0)
4189 23:03:16.392414 0 10 16 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
4190 23:03:16.398795 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4191 23:03:16.402992 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4192 23:03:16.405407 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4193 23:03:16.412383 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4194 23:03:16.415239 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4195 23:03:16.419163 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4196 23:03:16.425495 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4197 23:03:16.428493 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4198 23:03:16.432175 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 23:03:16.438306 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 23:03:16.442055 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 23:03:16.445176 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 23:03:16.451763 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 23:03:16.455275 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 23:03:16.458463 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 23:03:16.464749 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 23:03:16.468550 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 23:03:16.471426 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 23:03:16.478131 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 23:03:16.481466 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 23:03:16.484540 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 23:03:16.491202 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 23:03:16.494586 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4213 23:03:16.498077 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4214 23:03:16.500886 Total UI for P1: 0, mck2ui 16
4215 23:03:16.504325 best dqsien dly found for B0: ( 0, 13, 12)
4216 23:03:16.510855 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4217 23:03:16.514083 Total UI for P1: 0, mck2ui 16
4218 23:03:16.517784 best dqsien dly found for B1: ( 0, 13, 14)
4219 23:03:16.520825 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4220 23:03:16.524560 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4221 23:03:16.524642
4222 23:03:16.527201 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4223 23:03:16.530615 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4224 23:03:16.534076 [Gating] SW calibration Done
4225 23:03:16.534158 ==
4226 23:03:16.537255 Dram Type= 6, Freq= 0, CH_0, rank 1
4227 23:03:16.540184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4228 23:03:16.540266 ==
4229 23:03:16.543692 RX Vref Scan: 0
4230 23:03:16.543774
4231 23:03:16.547554 RX Vref 0 -> 0, step: 1
4232 23:03:16.547635
4233 23:03:16.550113 RX Delay -230 -> 252, step: 16
4234 23:03:16.553865 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4235 23:03:16.557137 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4236 23:03:16.559996 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4237 23:03:16.566765 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4238 23:03:16.570085 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4239 23:03:16.573452 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4240 23:03:16.576637 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4241 23:03:16.579750 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4242 23:03:16.586701 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4243 23:03:16.589556 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4244 23:03:16.592808 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4245 23:03:16.596766 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4246 23:03:16.603112 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4247 23:03:16.606168 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4248 23:03:16.610025 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4249 23:03:16.613034 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4250 23:03:16.616312 ==
4251 23:03:16.619788 Dram Type= 6, Freq= 0, CH_0, rank 1
4252 23:03:16.622767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4253 23:03:16.622850 ==
4254 23:03:16.622916 DQS Delay:
4255 23:03:16.625777 DQS0 = 0, DQS1 = 0
4256 23:03:16.625859 DQM Delay:
4257 23:03:16.629258 DQM0 = 40, DQM1 = 36
4258 23:03:16.629339 DQ Delay:
4259 23:03:16.632882 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4260 23:03:16.636195 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4261 23:03:16.639150 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4262 23:03:16.642568 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4263 23:03:16.642651
4264 23:03:16.642716
4265 23:03:16.642776 ==
4266 23:03:16.645864 Dram Type= 6, Freq= 0, CH_0, rank 1
4267 23:03:16.649412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4268 23:03:16.649511 ==
4269 23:03:16.649578
4270 23:03:16.649653
4271 23:03:16.652171 TX Vref Scan disable
4272 23:03:16.655532 == TX Byte 0 ==
4273 23:03:16.659221 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4274 23:03:16.662082 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4275 23:03:16.665404 == TX Byte 1 ==
4276 23:03:16.668630 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4277 23:03:16.672041 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4278 23:03:16.672123 ==
4279 23:03:16.675496 Dram Type= 6, Freq= 0, CH_0, rank 1
4280 23:03:16.681636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4281 23:03:16.681718 ==
4282 23:03:16.681783
4283 23:03:16.681843
4284 23:03:16.685083 TX Vref Scan disable
4285 23:03:16.685175 == TX Byte 0 ==
4286 23:03:16.691703 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4287 23:03:16.694799 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4288 23:03:16.694881 == TX Byte 1 ==
4289 23:03:16.701306 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4290 23:03:16.705013 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4291 23:03:16.705152
4292 23:03:16.705247 [DATLAT]
4293 23:03:16.708059 Freq=600, CH0 RK1
4294 23:03:16.708154
4295 23:03:16.708257 DATLAT Default: 0x9
4296 23:03:16.711677 0, 0xFFFF, sum = 0
4297 23:03:16.714788 1, 0xFFFF, sum = 0
4298 23:03:16.714872 2, 0xFFFF, sum = 0
4299 23:03:16.717923 3, 0xFFFF, sum = 0
4300 23:03:16.718021 4, 0xFFFF, sum = 0
4301 23:03:16.721633 5, 0xFFFF, sum = 0
4302 23:03:16.721737 6, 0xFFFF, sum = 0
4303 23:03:16.724661 7, 0xFFFF, sum = 0
4304 23:03:16.724761 8, 0x0, sum = 1
4305 23:03:16.727895 9, 0x0, sum = 2
4306 23:03:16.727978 10, 0x0, sum = 3
4307 23:03:16.731295 11, 0x0, sum = 4
4308 23:03:16.731378 best_step = 9
4309 23:03:16.731479
4310 23:03:16.731539 ==
4311 23:03:16.734198 Dram Type= 6, Freq= 0, CH_0, rank 1
4312 23:03:16.737675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4313 23:03:16.737757 ==
4314 23:03:16.740823 RX Vref Scan: 0
4315 23:03:16.740904
4316 23:03:16.744147 RX Vref 0 -> 0, step: 1
4317 23:03:16.744298
4318 23:03:16.744364 RX Delay -179 -> 252, step: 8
4319 23:03:16.752487 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4320 23:03:16.755441 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4321 23:03:16.758412 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4322 23:03:16.761914 iDelay=205, Bit 3, Center 40 (-107 ~ 188) 296
4323 23:03:16.768320 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4324 23:03:16.771541 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4325 23:03:16.775341 iDelay=205, Bit 6, Center 44 (-107 ~ 196) 304
4326 23:03:16.778726 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4327 23:03:16.784627 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4328 23:03:16.787963 iDelay=205, Bit 9, Center 16 (-139 ~ 172) 312
4329 23:03:16.791412 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4330 23:03:16.794857 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4331 23:03:16.801373 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4332 23:03:16.804585 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4333 23:03:16.808081 iDelay=205, Bit 14, Center 48 (-107 ~ 204) 312
4334 23:03:16.811107 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4335 23:03:16.811188 ==
4336 23:03:16.814679 Dram Type= 6, Freq= 0, CH_0, rank 1
4337 23:03:16.820869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4338 23:03:16.820950 ==
4339 23:03:16.821016 DQS Delay:
4340 23:03:16.824568 DQS0 = 0, DQS1 = 0
4341 23:03:16.824649 DQM Delay:
4342 23:03:16.824713 DQM0 = 40, DQM1 = 33
4343 23:03:16.827708 DQ Delay:
4344 23:03:16.830953 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =40
4345 23:03:16.834091 DQ4 =44, DQ5 =28, DQ6 =44, DQ7 =48
4346 23:03:16.837567 DQ8 =24, DQ9 =16, DQ10 =36, DQ11 =24
4347 23:03:16.840471 DQ12 =40, DQ13 =40, DQ14 =48, DQ15 =40
4348 23:03:16.840552
4349 23:03:16.840616
4350 23:03:16.847320 [DQSOSCAuto] RK1, (LSB)MR18= 0x413c, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
4351 23:03:16.850688 CH0 RK1: MR19=808, MR18=413C
4352 23:03:16.857074 CH0_RK1: MR19=0x808, MR18=0x413C, DQSOSC=397, MR23=63, INC=166, DEC=110
4353 23:03:16.860546 [RxdqsGatingPostProcess] freq 600
4354 23:03:16.866754 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4355 23:03:16.870242 Pre-setting of DQS Precalculation
4356 23:03:16.873906 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4357 23:03:16.874020 ==
4358 23:03:16.876813 Dram Type= 6, Freq= 0, CH_1, rank 0
4359 23:03:16.880658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4360 23:03:16.880741 ==
4361 23:03:16.886555 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4362 23:03:16.893186 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4363 23:03:16.896499 [CA 0] Center 36 (6~66) winsize 61
4364 23:03:16.900108 [CA 1] Center 35 (5~66) winsize 62
4365 23:03:16.903636 [CA 2] Center 34 (4~65) winsize 62
4366 23:03:16.906726 [CA 3] Center 34 (4~65) winsize 62
4367 23:03:16.910112 [CA 4] Center 34 (4~65) winsize 62
4368 23:03:16.913140 [CA 5] Center 34 (3~65) winsize 63
4369 23:03:16.913221
4370 23:03:16.916411 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4371 23:03:16.916492
4372 23:03:16.919760 [CATrainingPosCal] consider 1 rank data
4373 23:03:16.923185 u2DelayCellTimex100 = 270/100 ps
4374 23:03:16.926669 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4375 23:03:16.929401 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4376 23:03:16.933275 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4377 23:03:16.936276 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4378 23:03:16.942728 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4379 23:03:16.945999 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4380 23:03:16.946080
4381 23:03:16.949331 CA PerBit enable=1, Macro0, CA PI delay=34
4382 23:03:16.949413
4383 23:03:16.953044 [CBTSetCACLKResult] CA Dly = 34
4384 23:03:16.953140 CS Dly: 5 (0~36)
4385 23:03:16.953206 ==
4386 23:03:16.955877 Dram Type= 6, Freq= 0, CH_1, rank 1
4387 23:03:16.962499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4388 23:03:16.962582 ==
4389 23:03:16.965674 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4390 23:03:16.972622 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4391 23:03:16.975842 [CA 0] Center 35 (5~66) winsize 62
4392 23:03:16.979167 [CA 1] Center 35 (5~66) winsize 62
4393 23:03:16.982533 [CA 2] Center 34 (4~65) winsize 62
4394 23:03:16.985369 [CA 3] Center 34 (3~65) winsize 63
4395 23:03:16.989144 [CA 4] Center 34 (4~65) winsize 62
4396 23:03:16.992023 [CA 5] Center 34 (3~65) winsize 63
4397 23:03:16.992105
4398 23:03:16.995374 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4399 23:03:16.995456
4400 23:03:16.998887 [CATrainingPosCal] consider 2 rank data
4401 23:03:17.002290 u2DelayCellTimex100 = 270/100 ps
4402 23:03:17.005293 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4403 23:03:17.008575 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4404 23:03:17.015834 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4405 23:03:17.019049 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4406 23:03:17.021782 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4407 23:03:17.025335 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4408 23:03:17.025446
4409 23:03:17.028428 CA PerBit enable=1, Macro0, CA PI delay=34
4410 23:03:17.028534
4411 23:03:17.031860 [CBTSetCACLKResult] CA Dly = 34
4412 23:03:17.031973 CS Dly: 5 (0~36)
4413 23:03:17.034786
4414 23:03:17.038367 ----->DramcWriteLeveling(PI) begin...
4415 23:03:17.038451 ==
4416 23:03:17.042143 Dram Type= 6, Freq= 0, CH_1, rank 0
4417 23:03:17.044803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4418 23:03:17.044888 ==
4419 23:03:17.047947 Write leveling (Byte 0): 30 => 30
4420 23:03:17.051892 Write leveling (Byte 1): 30 => 30
4421 23:03:17.054783 DramcWriteLeveling(PI) end<-----
4422 23:03:17.054865
4423 23:03:17.054930 ==
4424 23:03:17.057912 Dram Type= 6, Freq= 0, CH_1, rank 0
4425 23:03:17.061404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4426 23:03:17.061489 ==
4427 23:03:17.064763 [Gating] SW mode calibration
4428 23:03:17.071346 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4429 23:03:17.077692 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4430 23:03:17.081051 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4431 23:03:17.084622 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4432 23:03:17.091277 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4433 23:03:17.094653 0 9 12 | B1->B0 | 2f2f 2f2f | 1 0 | (1 0) (1 1)
4434 23:03:17.097324 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4435 23:03:17.104028 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4436 23:03:17.107702 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4437 23:03:17.110642 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4438 23:03:17.117088 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4439 23:03:17.120560 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4440 23:03:17.123960 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4441 23:03:17.130216 0 10 12 | B1->B0 | 3232 3838 | 0 0 | (0 0) (0 0)
4442 23:03:17.133801 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4443 23:03:17.137260 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4444 23:03:17.143513 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4445 23:03:17.146977 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4446 23:03:17.150389 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4447 23:03:17.156733 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4448 23:03:17.159900 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4449 23:03:17.163410 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4450 23:03:17.170198 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4451 23:03:17.173097 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 23:03:17.176701 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 23:03:17.183199 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 23:03:17.186306 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 23:03:17.189733 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 23:03:17.196419 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 23:03:17.199514 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 23:03:17.203059 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 23:03:17.209428 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 23:03:17.212691 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 23:03:17.216149 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 23:03:17.222875 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 23:03:17.225916 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 23:03:17.229184 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 23:03:17.235947 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4466 23:03:17.238686 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4467 23:03:17.242591 Total UI for P1: 0, mck2ui 16
4468 23:03:17.245591 best dqsien dly found for B0: ( 0, 13, 12)
4469 23:03:17.248946 Total UI for P1: 0, mck2ui 16
4470 23:03:17.252505 best dqsien dly found for B1: ( 0, 13, 12)
4471 23:03:17.255468 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4472 23:03:17.258675 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4473 23:03:17.258757
4474 23:03:17.262064 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4475 23:03:17.269066 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4476 23:03:17.269150 [Gating] SW calibration Done
4477 23:03:17.269218 ==
4478 23:03:17.271822 Dram Type= 6, Freq= 0, CH_1, rank 0
4479 23:03:17.278761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4480 23:03:17.278838 ==
4481 23:03:17.278910 RX Vref Scan: 0
4482 23:03:17.278971
4483 23:03:17.281998 RX Vref 0 -> 0, step: 1
4484 23:03:17.282084
4485 23:03:17.285352 RX Delay -230 -> 252, step: 16
4486 23:03:17.288853 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4487 23:03:17.291571 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4488 23:03:17.298580 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4489 23:03:17.301787 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4490 23:03:17.305383 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4491 23:03:17.308154 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4492 23:03:17.311878 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4493 23:03:17.318206 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4494 23:03:17.321390 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4495 23:03:17.324481 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4496 23:03:17.328108 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4497 23:03:17.334681 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4498 23:03:17.338187 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4499 23:03:17.340849 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4500 23:03:17.344405 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4501 23:03:17.351183 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4502 23:03:17.351263 ==
4503 23:03:17.354222 Dram Type= 6, Freq= 0, CH_1, rank 0
4504 23:03:17.357950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4505 23:03:17.358027 ==
4506 23:03:17.358089 DQS Delay:
4507 23:03:17.360966 DQS0 = 0, DQS1 = 0
4508 23:03:17.361034 DQM Delay:
4509 23:03:17.364219 DQM0 = 41, DQM1 = 38
4510 23:03:17.364292 DQ Delay:
4511 23:03:17.367544 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4512 23:03:17.370830 DQ4 =33, DQ5 =57, DQ6 =49, DQ7 =33
4513 23:03:17.374177 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4514 23:03:17.377264 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4515 23:03:17.377345
4516 23:03:17.377412
4517 23:03:17.377472 ==
4518 23:03:17.380699 Dram Type= 6, Freq= 0, CH_1, rank 0
4519 23:03:17.387068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4520 23:03:17.387157 ==
4521 23:03:17.387224
4522 23:03:17.387284
4523 23:03:17.387346 TX Vref Scan disable
4524 23:03:17.390602 == TX Byte 0 ==
4525 23:03:17.393997 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4526 23:03:17.400889 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4527 23:03:17.400970 == TX Byte 1 ==
4528 23:03:17.403804 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4529 23:03:17.410519 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4530 23:03:17.410605 ==
4531 23:03:17.413983 Dram Type= 6, Freq= 0, CH_1, rank 0
4532 23:03:17.416914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4533 23:03:17.416995 ==
4534 23:03:17.417063
4535 23:03:17.417122
4536 23:03:17.420299 TX Vref Scan disable
4537 23:03:17.423692 == TX Byte 0 ==
4538 23:03:17.426727 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4539 23:03:17.430555 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4540 23:03:17.433592 == TX Byte 1 ==
4541 23:03:17.436825 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4542 23:03:17.440023 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4543 23:03:17.440133
4544 23:03:17.440229 [DATLAT]
4545 23:03:17.443133 Freq=600, CH1 RK0
4546 23:03:17.443211
4547 23:03:17.446544 DATLAT Default: 0x9
4548 23:03:17.446626 0, 0xFFFF, sum = 0
4549 23:03:17.449813 1, 0xFFFF, sum = 0
4550 23:03:17.449896 2, 0xFFFF, sum = 0
4551 23:03:17.453181 3, 0xFFFF, sum = 0
4552 23:03:17.453259 4, 0xFFFF, sum = 0
4553 23:03:17.456668 5, 0xFFFF, sum = 0
4554 23:03:17.456754 6, 0xFFFF, sum = 0
4555 23:03:17.459838 7, 0xFFFF, sum = 0
4556 23:03:17.459915 8, 0x0, sum = 1
4557 23:03:17.463223 9, 0x0, sum = 2
4558 23:03:17.463299 10, 0x0, sum = 3
4559 23:03:17.466602 11, 0x0, sum = 4
4560 23:03:17.466685 best_step = 9
4561 23:03:17.466750
4562 23:03:17.466810 ==
4563 23:03:17.469357 Dram Type= 6, Freq= 0, CH_1, rank 0
4564 23:03:17.473062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4565 23:03:17.476366 ==
4566 23:03:17.476448 RX Vref Scan: 1
4567 23:03:17.476513
4568 23:03:17.479301 RX Vref 0 -> 0, step: 1
4569 23:03:17.479383
4570 23:03:17.482739 RX Delay -179 -> 252, step: 8
4571 23:03:17.482821
4572 23:03:17.486177 Set Vref, RX VrefLevel [Byte0]: 51
4573 23:03:17.489624 [Byte1]: 52
4574 23:03:17.489789
4575 23:03:17.492825 Final RX Vref Byte 0 = 51 to rank0
4576 23:03:17.496377 Final RX Vref Byte 1 = 52 to rank0
4577 23:03:17.499020 Final RX Vref Byte 0 = 51 to rank1
4578 23:03:17.502427 Final RX Vref Byte 1 = 52 to rank1==
4579 23:03:17.505865 Dram Type= 6, Freq= 0, CH_1, rank 0
4580 23:03:17.509381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4581 23:03:17.509464 ==
4582 23:03:17.512371 DQS Delay:
4583 23:03:17.512453 DQS0 = 0, DQS1 = 0
4584 23:03:17.512518 DQM Delay:
4585 23:03:17.515569 DQM0 = 42, DQM1 = 34
4586 23:03:17.515651 DQ Delay:
4587 23:03:17.519056 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =44
4588 23:03:17.522437 DQ4 =36, DQ5 =48, DQ6 =52, DQ7 =36
4589 23:03:17.526068 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =28
4590 23:03:17.528901 DQ12 =44, DQ13 =44, DQ14 =40, DQ15 =40
4591 23:03:17.528982
4592 23:03:17.529047
4593 23:03:17.538905 [DQSOSCAuto] RK0, (LSB)MR18= 0x304a, (MSB)MR19= 0x808, tDQSOscB0 = 395 ps tDQSOscB1 = 400 ps
4594 23:03:17.538990 CH1 RK0: MR19=808, MR18=304A
4595 23:03:17.545438 CH1_RK0: MR19=0x808, MR18=0x304A, DQSOSC=395, MR23=63, INC=168, DEC=112
4596 23:03:17.545520
4597 23:03:17.548753 ----->DramcWriteLeveling(PI) begin...
4598 23:03:17.552099 ==
4599 23:03:17.555128 Dram Type= 6, Freq= 0, CH_1, rank 1
4600 23:03:17.558680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4601 23:03:17.558762 ==
4602 23:03:17.562047 Write leveling (Byte 0): 30 => 30
4603 23:03:17.565181 Write leveling (Byte 1): 30 => 30
4604 23:03:17.568182 DramcWriteLeveling(PI) end<-----
4605 23:03:17.568264
4606 23:03:17.568329 ==
4607 23:03:17.571695 Dram Type= 6, Freq= 0, CH_1, rank 1
4608 23:03:17.575162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4609 23:03:17.575245 ==
4610 23:03:17.578189 [Gating] SW mode calibration
4611 23:03:17.585202 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4612 23:03:17.591473 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4613 23:03:17.594786 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4614 23:03:17.598130 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4615 23:03:17.604697 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4616 23:03:17.607869 0 9 12 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 1)
4617 23:03:17.611278 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4618 23:03:17.617457 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4619 23:03:17.621228 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4620 23:03:17.624478 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4621 23:03:17.630577 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4622 23:03:17.634007 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4623 23:03:17.637310 0 10 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
4624 23:03:17.643932 0 10 12 | B1->B0 | 3232 3d3d | 0 0 | (0 0) (0 0)
4625 23:03:17.647502 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4626 23:03:17.650984 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4627 23:03:17.656965 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4628 23:03:17.660481 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4629 23:03:17.663926 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4630 23:03:17.670278 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4631 23:03:17.673788 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4632 23:03:17.677138 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4633 23:03:17.683867 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 23:03:17.686724 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 23:03:17.690058 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 23:03:17.696729 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 23:03:17.699713 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 23:03:17.703052 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 23:03:17.709762 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 23:03:17.713188 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 23:03:17.716339 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 23:03:17.723183 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 23:03:17.726280 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 23:03:17.729829 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 23:03:17.736360 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 23:03:17.739955 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 23:03:17.742957 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4648 23:03:17.749496 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4649 23:03:17.752885 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4650 23:03:17.755617 Total UI for P1: 0, mck2ui 16
4651 23:03:17.759068 best dqsien dly found for B0: ( 0, 13, 10)
4652 23:03:17.762539 Total UI for P1: 0, mck2ui 16
4653 23:03:17.765913 best dqsien dly found for B1: ( 0, 13, 14)
4654 23:03:17.769247 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4655 23:03:17.772565 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4656 23:03:17.772640
4657 23:03:17.775807 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4658 23:03:17.782145 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4659 23:03:17.782269 [Gating] SW calibration Done
4660 23:03:17.782361 ==
4661 23:03:17.785950 Dram Type= 6, Freq= 0, CH_1, rank 1
4662 23:03:17.792080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4663 23:03:17.792161 ==
4664 23:03:17.792225 RX Vref Scan: 0
4665 23:03:17.792294
4666 23:03:17.795709 RX Vref 0 -> 0, step: 1
4667 23:03:17.795786
4668 23:03:17.798796 RX Delay -230 -> 252, step: 16
4669 23:03:17.801709 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4670 23:03:17.805198 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4671 23:03:17.812153 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4672 23:03:17.815108 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4673 23:03:17.818657 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4674 23:03:17.821508 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4675 23:03:17.824724 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4676 23:03:17.831268 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4677 23:03:17.834582 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4678 23:03:17.837881 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4679 23:03:17.841286 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4680 23:03:17.848522 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4681 23:03:17.851483 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4682 23:03:17.854660 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4683 23:03:17.857763 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4684 23:03:17.864404 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4685 23:03:17.864486 ==
4686 23:03:17.868023 Dram Type= 6, Freq= 0, CH_1, rank 1
4687 23:03:17.871131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4688 23:03:17.871213 ==
4689 23:03:17.871279 DQS Delay:
4690 23:03:17.874397 DQS0 = 0, DQS1 = 0
4691 23:03:17.874477 DQM Delay:
4692 23:03:17.877514 DQM0 = 41, DQM1 = 39
4693 23:03:17.877590 DQ Delay:
4694 23:03:17.881248 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4695 23:03:17.884134 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =33
4696 23:03:17.887681 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4697 23:03:17.891151 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4698 23:03:17.891233
4699 23:03:17.891300
4700 23:03:17.891359 ==
4701 23:03:17.893839 Dram Type= 6, Freq= 0, CH_1, rank 1
4702 23:03:17.900753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4703 23:03:17.900836 ==
4704 23:03:17.900900
4705 23:03:17.900966
4706 23:03:17.901027 TX Vref Scan disable
4707 23:03:17.903956 == TX Byte 0 ==
4708 23:03:17.907040 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4709 23:03:17.914020 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4710 23:03:17.914100 == TX Byte 1 ==
4711 23:03:17.917389 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4712 23:03:17.923848 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4713 23:03:17.923925 ==
4714 23:03:17.926963 Dram Type= 6, Freq= 0, CH_1, rank 1
4715 23:03:17.930268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4716 23:03:17.930359 ==
4717 23:03:17.930423
4718 23:03:17.930489
4719 23:03:17.933715 TX Vref Scan disable
4720 23:03:17.937103 == TX Byte 0 ==
4721 23:03:17.940133 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4722 23:03:17.943232 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4723 23:03:17.946575 == TX Byte 1 ==
4724 23:03:17.949751 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4725 23:03:17.953209 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4726 23:03:17.953282
4727 23:03:17.956529 [DATLAT]
4728 23:03:17.956611 Freq=600, CH1 RK1
4729 23:03:17.956679
4730 23:03:17.959791 DATLAT Default: 0x9
4731 23:03:17.959870 0, 0xFFFF, sum = 0
4732 23:03:17.962974 1, 0xFFFF, sum = 0
4733 23:03:17.963047 2, 0xFFFF, sum = 0
4734 23:03:17.966540 3, 0xFFFF, sum = 0
4735 23:03:17.966654 4, 0xFFFF, sum = 0
4736 23:03:17.969582 5, 0xFFFF, sum = 0
4737 23:03:17.969665 6, 0xFFFF, sum = 0
4738 23:03:17.972961 7, 0xFFFF, sum = 0
4739 23:03:17.973038 8, 0x0, sum = 1
4740 23:03:17.976067 9, 0x0, sum = 2
4741 23:03:17.976165 10, 0x0, sum = 3
4742 23:03:17.979669 11, 0x0, sum = 4
4743 23:03:17.979750 best_step = 9
4744 23:03:17.979815
4745 23:03:17.979878 ==
4746 23:03:17.982802 Dram Type= 6, Freq= 0, CH_1, rank 1
4747 23:03:17.986162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4748 23:03:17.989577 ==
4749 23:03:17.989677 RX Vref Scan: 0
4750 23:03:17.989767
4751 23:03:17.993009 RX Vref 0 -> 0, step: 1
4752 23:03:17.993112
4753 23:03:17.996260 RX Delay -179 -> 252, step: 8
4754 23:03:17.999301 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4755 23:03:18.002589 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4756 23:03:18.008993 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4757 23:03:18.012354 iDelay=205, Bit 3, Center 36 (-123 ~ 196) 320
4758 23:03:18.016006 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4759 23:03:18.019156 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4760 23:03:18.025566 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4761 23:03:18.029023 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4762 23:03:18.032403 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4763 23:03:18.035528 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4764 23:03:18.042118 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4765 23:03:18.045456 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4766 23:03:18.049018 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4767 23:03:18.051783 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4768 23:03:18.058526 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4769 23:03:18.061543 iDelay=205, Bit 15, Center 44 (-115 ~ 204) 320
4770 23:03:18.061621 ==
4771 23:03:18.065233 Dram Type= 6, Freq= 0, CH_1, rank 1
4772 23:03:18.068351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4773 23:03:18.068430 ==
4774 23:03:18.071816 DQS Delay:
4775 23:03:18.071925 DQS0 = 0, DQS1 = 0
4776 23:03:18.071995 DQM Delay:
4777 23:03:18.075037 DQM0 = 38, DQM1 = 35
4778 23:03:18.075117 DQ Delay:
4779 23:03:18.078544 DQ0 =40, DQ1 =36, DQ2 =28, DQ3 =36
4780 23:03:18.081584 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =32
4781 23:03:18.085025 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =24
4782 23:03:18.088562 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =44
4783 23:03:18.088648
4784 23:03:18.088714
4785 23:03:18.098318 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f55, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 400 ps
4786 23:03:18.101621 CH1 RK1: MR19=808, MR18=2F55
4787 23:03:18.104707 CH1_RK1: MR19=0x808, MR18=0x2F55, DQSOSC=393, MR23=63, INC=169, DEC=113
4788 23:03:18.107805 [RxdqsGatingPostProcess] freq 600
4789 23:03:18.114653 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4790 23:03:18.117899 Pre-setting of DQS Precalculation
4791 23:03:18.121028 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4792 23:03:18.130801 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4793 23:03:18.137332 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4794 23:03:18.137413
4795 23:03:18.137479
4796 23:03:18.141074 [Calibration Summary] 1200 Mbps
4797 23:03:18.141154 CH 0, Rank 0
4798 23:03:18.143815 SW Impedance : PASS
4799 23:03:18.143911 DUTY Scan : NO K
4800 23:03:18.147358 ZQ Calibration : PASS
4801 23:03:18.150609 Jitter Meter : NO K
4802 23:03:18.150680 CBT Training : PASS
4803 23:03:18.154163 Write leveling : PASS
4804 23:03:18.157182 RX DQS gating : PASS
4805 23:03:18.157258 RX DQ/DQS(RDDQC) : PASS
4806 23:03:18.160495 TX DQ/DQS : PASS
4807 23:03:18.164044 RX DATLAT : PASS
4808 23:03:18.164146 RX DQ/DQS(Engine): PASS
4809 23:03:18.166915 TX OE : NO K
4810 23:03:18.167027 All Pass.
4811 23:03:18.167116
4812 23:03:18.170243 CH 0, Rank 1
4813 23:03:18.170383 SW Impedance : PASS
4814 23:03:18.173573 DUTY Scan : NO K
4815 23:03:18.176644 ZQ Calibration : PASS
4816 23:03:18.176715 Jitter Meter : NO K
4817 23:03:18.180523 CBT Training : PASS
4818 23:03:18.183288 Write leveling : PASS
4819 23:03:18.183362 RX DQS gating : PASS
4820 23:03:18.186695 RX DQ/DQS(RDDQC) : PASS
4821 23:03:18.190063 TX DQ/DQS : PASS
4822 23:03:18.190173 RX DATLAT : PASS
4823 23:03:18.193306 RX DQ/DQS(Engine): PASS
4824 23:03:18.196345 TX OE : NO K
4825 23:03:18.196425 All Pass.
4826 23:03:18.196488
4827 23:03:18.196578 CH 1, Rank 0
4828 23:03:18.199774 SW Impedance : PASS
4829 23:03:18.203423 DUTY Scan : NO K
4830 23:03:18.203503 ZQ Calibration : PASS
4831 23:03:18.206570 Jitter Meter : NO K
4832 23:03:18.210088 CBT Training : PASS
4833 23:03:18.210166 Write leveling : PASS
4834 23:03:18.213559 RX DQS gating : PASS
4835 23:03:18.216725 RX DQ/DQS(RDDQC) : PASS
4836 23:03:18.216863 TX DQ/DQS : PASS
4837 23:03:18.219844 RX DATLAT : PASS
4838 23:03:18.219929 RX DQ/DQS(Engine): PASS
4839 23:03:18.222862 TX OE : NO K
4840 23:03:18.222939 All Pass.
4841 23:03:18.223009
4842 23:03:18.226128 CH 1, Rank 1
4843 23:03:18.229549 SW Impedance : PASS
4844 23:03:18.229624 DUTY Scan : NO K
4845 23:03:18.232804 ZQ Calibration : PASS
4846 23:03:18.232885 Jitter Meter : NO K
4847 23:03:18.236577 CBT Training : PASS
4848 23:03:18.239171 Write leveling : PASS
4849 23:03:18.239244 RX DQS gating : PASS
4850 23:03:18.242514 RX DQ/DQS(RDDQC) : PASS
4851 23:03:18.245948 TX DQ/DQS : PASS
4852 23:03:18.246022 RX DATLAT : PASS
4853 23:03:18.249378 RX DQ/DQS(Engine): PASS
4854 23:03:18.252313 TX OE : NO K
4855 23:03:18.252393 All Pass.
4856 23:03:18.252460
4857 23:03:18.255622 DramC Write-DBI off
4858 23:03:18.255694 PER_BANK_REFRESH: Hybrid Mode
4859 23:03:18.259252 TX_TRACKING: ON
4860 23:03:18.269075 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4861 23:03:18.272237 [FAST_K] Save calibration result to emmc
4862 23:03:18.276069 dramc_set_vcore_voltage set vcore to 662500
4863 23:03:18.276146 Read voltage for 933, 3
4864 23:03:18.279297 Vio18 = 0
4865 23:03:18.279384 Vcore = 662500
4866 23:03:18.279447 Vdram = 0
4867 23:03:18.282071 Vddq = 0
4868 23:03:18.282152 Vmddr = 0
4869 23:03:18.285911 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4870 23:03:18.292218 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4871 23:03:18.295772 MEM_TYPE=3, freq_sel=17
4872 23:03:18.299182 sv_algorithm_assistance_LP4_1600
4873 23:03:18.301979 ============ PULL DRAM RESETB DOWN ============
4874 23:03:18.305716 ========== PULL DRAM RESETB DOWN end =========
4875 23:03:18.312141 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4876 23:03:18.315356 ===================================
4877 23:03:18.315436 LPDDR4 DRAM CONFIGURATION
4878 23:03:18.318467 ===================================
4879 23:03:18.321962 EX_ROW_EN[0] = 0x0
4880 23:03:18.325022 EX_ROW_EN[1] = 0x0
4881 23:03:18.325115 LP4Y_EN = 0x0
4882 23:03:18.328415 WORK_FSP = 0x0
4883 23:03:18.328493 WL = 0x3
4884 23:03:18.331891 RL = 0x3
4885 23:03:18.331968 BL = 0x2
4886 23:03:18.335147 RPST = 0x0
4887 23:03:18.335227 RD_PRE = 0x0
4888 23:03:18.338161 WR_PRE = 0x1
4889 23:03:18.338236 WR_PST = 0x0
4890 23:03:18.341852 DBI_WR = 0x0
4891 23:03:18.341935 DBI_RD = 0x0
4892 23:03:18.344955 OTF = 0x1
4893 23:03:18.347821 ===================================
4894 23:03:18.351429 ===================================
4895 23:03:18.351509 ANA top config
4896 23:03:18.354653 ===================================
4897 23:03:18.358149 DLL_ASYNC_EN = 0
4898 23:03:18.360956 ALL_SLAVE_EN = 1
4899 23:03:18.364400 NEW_RANK_MODE = 1
4900 23:03:18.364475 DLL_IDLE_MODE = 1
4901 23:03:18.367964 LP45_APHY_COMB_EN = 1
4902 23:03:18.371572 TX_ODT_DIS = 1
4903 23:03:18.374244 NEW_8X_MODE = 1
4904 23:03:18.377787 ===================================
4905 23:03:18.380895 ===================================
4906 23:03:18.384139 data_rate = 1866
4907 23:03:18.387630 CKR = 1
4908 23:03:18.387710 DQ_P2S_RATIO = 8
4909 23:03:18.391086 ===================================
4910 23:03:18.394013 CA_P2S_RATIO = 8
4911 23:03:18.397566 DQ_CA_OPEN = 0
4912 23:03:18.400425 DQ_SEMI_OPEN = 0
4913 23:03:18.403693 CA_SEMI_OPEN = 0
4914 23:03:18.407323 CA_FULL_RATE = 0
4915 23:03:18.407394 DQ_CKDIV4_EN = 1
4916 23:03:18.410458 CA_CKDIV4_EN = 1
4917 23:03:18.413483 CA_PREDIV_EN = 0
4918 23:03:18.416941 PH8_DLY = 0
4919 23:03:18.420750 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4920 23:03:18.423751 DQ_AAMCK_DIV = 4
4921 23:03:18.423828 CA_AAMCK_DIV = 4
4922 23:03:18.427041 CA_ADMCK_DIV = 4
4923 23:03:18.430374 DQ_TRACK_CA_EN = 0
4924 23:03:18.433646 CA_PICK = 933
4925 23:03:18.436870 CA_MCKIO = 933
4926 23:03:18.440247 MCKIO_SEMI = 0
4927 23:03:18.443463 PLL_FREQ = 3732
4928 23:03:18.446723 DQ_UI_PI_RATIO = 32
4929 23:03:18.446815 CA_UI_PI_RATIO = 0
4930 23:03:18.450338 ===================================
4931 23:03:18.453411 ===================================
4932 23:03:18.456318 memory_type:LPDDR4
4933 23:03:18.459856 GP_NUM : 10
4934 23:03:18.459932 SRAM_EN : 1
4935 23:03:18.463064 MD32_EN : 0
4936 23:03:18.466859 ===================================
4937 23:03:18.469552 [ANA_INIT] >>>>>>>>>>>>>>
4938 23:03:18.472840 <<<<<< [CONFIGURE PHASE]: ANA_TX
4939 23:03:18.476287 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4940 23:03:18.479664 ===================================
4941 23:03:18.479739 data_rate = 1866,PCW = 0X8f00
4942 23:03:18.482730 ===================================
4943 23:03:18.486191 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4944 23:03:18.492478 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4945 23:03:18.499400 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4946 23:03:18.502477 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4947 23:03:18.505560 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4948 23:03:18.508977 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4949 23:03:18.512452 [ANA_INIT] flow start
4950 23:03:18.515808 [ANA_INIT] PLL >>>>>>>>
4951 23:03:18.515887 [ANA_INIT] PLL <<<<<<<<
4952 23:03:18.519212 [ANA_INIT] MIDPI >>>>>>>>
4953 23:03:18.522045 [ANA_INIT] MIDPI <<<<<<<<
4954 23:03:18.522157 [ANA_INIT] DLL >>>>>>>>
4955 23:03:18.525676 [ANA_INIT] flow end
4956 23:03:18.528922 ============ LP4 DIFF to SE enter ============
4957 23:03:18.535529 ============ LP4 DIFF to SE exit ============
4958 23:03:18.535640 [ANA_INIT] <<<<<<<<<<<<<
4959 23:03:18.538773 [Flow] Enable top DCM control >>>>>
4960 23:03:18.542094 [Flow] Enable top DCM control <<<<<
4961 23:03:18.545564 Enable DLL master slave shuffle
4962 23:03:18.551728 ==============================================================
4963 23:03:18.551817 Gating Mode config
4964 23:03:18.558374 ==============================================================
4965 23:03:18.561892 Config description:
4966 23:03:18.571679 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4967 23:03:18.578213 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4968 23:03:18.581263 SELPH_MODE 0: By rank 1: By Phase
4969 23:03:18.588132 ==============================================================
4970 23:03:18.591332 GAT_TRACK_EN = 1
4971 23:03:18.594869 RX_GATING_MODE = 2
4972 23:03:18.594963 RX_GATING_TRACK_MODE = 2
4973 23:03:18.597736 SELPH_MODE = 1
4974 23:03:18.601108 PICG_EARLY_EN = 1
4975 23:03:18.604559 VALID_LAT_VALUE = 1
4976 23:03:18.611118 ==============================================================
4977 23:03:18.614373 Enter into Gating configuration >>>>
4978 23:03:18.617798 Exit from Gating configuration <<<<
4979 23:03:18.621048 Enter into DVFS_PRE_config >>>>>
4980 23:03:18.630745 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4981 23:03:18.634574 Exit from DVFS_PRE_config <<<<<
4982 23:03:18.637275 Enter into PICG configuration >>>>
4983 23:03:18.641059 Exit from PICG configuration <<<<
4984 23:03:18.644133 [RX_INPUT] configuration >>>>>
4985 23:03:18.647048 [RX_INPUT] configuration <<<<<
4986 23:03:18.650424 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4987 23:03:18.657631 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4988 23:03:18.663633 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4989 23:03:18.670196 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4990 23:03:18.676721 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4991 23:03:18.683685 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4992 23:03:18.687098 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4993 23:03:18.689939 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4994 23:03:18.693053 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4995 23:03:18.696492 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4996 23:03:18.703154 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4997 23:03:18.706830 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4998 23:03:18.709652 ===================================
4999 23:03:18.713265 LPDDR4 DRAM CONFIGURATION
5000 23:03:18.716278 ===================================
5001 23:03:18.716382 EX_ROW_EN[0] = 0x0
5002 23:03:18.719573 EX_ROW_EN[1] = 0x0
5003 23:03:18.722676 LP4Y_EN = 0x0
5004 23:03:18.722786 WORK_FSP = 0x0
5005 23:03:18.726600 WL = 0x3
5006 23:03:18.726712 RL = 0x3
5007 23:03:18.729551 BL = 0x2
5008 23:03:18.729642 RPST = 0x0
5009 23:03:18.732873 RD_PRE = 0x0
5010 23:03:18.732949 WR_PRE = 0x1
5011 23:03:18.735956 WR_PST = 0x0
5012 23:03:18.736039 DBI_WR = 0x0
5013 23:03:18.739095 DBI_RD = 0x0
5014 23:03:18.739219 OTF = 0x1
5015 23:03:18.742856 ===================================
5016 23:03:18.745842 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5017 23:03:18.752721 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5018 23:03:18.755699 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5019 23:03:18.758940 ===================================
5020 23:03:18.762143 LPDDR4 DRAM CONFIGURATION
5021 23:03:18.765519 ===================================
5022 23:03:18.765608 EX_ROW_EN[0] = 0x10
5023 23:03:18.768895 EX_ROW_EN[1] = 0x0
5024 23:03:18.772017 LP4Y_EN = 0x0
5025 23:03:18.772141 WORK_FSP = 0x0
5026 23:03:18.775397 WL = 0x3
5027 23:03:18.775521 RL = 0x3
5028 23:03:18.778927 BL = 0x2
5029 23:03:18.779023 RPST = 0x0
5030 23:03:18.781904 RD_PRE = 0x0
5031 23:03:18.781988 WR_PRE = 0x1
5032 23:03:18.785454 WR_PST = 0x0
5033 23:03:18.785538 DBI_WR = 0x0
5034 23:03:18.788785 DBI_RD = 0x0
5035 23:03:18.788870 OTF = 0x1
5036 23:03:18.791837 ===================================
5037 23:03:18.798649 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5038 23:03:18.803078 nWR fixed to 30
5039 23:03:18.806087 [ModeRegInit_LP4] CH0 RK0
5040 23:03:18.806211 [ModeRegInit_LP4] CH0 RK1
5041 23:03:18.809453 [ModeRegInit_LP4] CH1 RK0
5042 23:03:18.812688 [ModeRegInit_LP4] CH1 RK1
5043 23:03:18.812772 match AC timing 9
5044 23:03:18.819358 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5045 23:03:18.822850 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5046 23:03:18.825761 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5047 23:03:18.832669 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5048 23:03:18.836013 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5049 23:03:18.836099 ==
5050 23:03:18.839263 Dram Type= 6, Freq= 0, CH_0, rank 0
5051 23:03:18.842677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5052 23:03:18.842763 ==
5053 23:03:18.849358 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5054 23:03:18.855643 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5055 23:03:18.859225 [CA 0] Center 37 (7~68) winsize 62
5056 23:03:18.862548 [CA 1] Center 37 (7~68) winsize 62
5057 23:03:18.865729 [CA 2] Center 34 (4~64) winsize 61
5058 23:03:18.868932 [CA 3] Center 34 (4~64) winsize 61
5059 23:03:18.871933 [CA 4] Center 32 (2~63) winsize 62
5060 23:03:18.875220 [CA 5] Center 32 (2~63) winsize 62
5061 23:03:18.875316
5062 23:03:18.878749 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5063 23:03:18.878836
5064 23:03:18.882308 [CATrainingPosCal] consider 1 rank data
5065 23:03:18.885017 u2DelayCellTimex100 = 270/100 ps
5066 23:03:18.888339 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5067 23:03:18.891937 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5068 23:03:18.895131 CA2 delay=34 (4~64),Diff = 2 PI (12 cell)
5069 23:03:18.902113 CA3 delay=34 (4~64),Diff = 2 PI (12 cell)
5070 23:03:18.904881 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
5071 23:03:18.908383 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5072 23:03:18.908469
5073 23:03:18.911766 CA PerBit enable=1, Macro0, CA PI delay=32
5074 23:03:18.911851
5075 23:03:18.915146 [CBTSetCACLKResult] CA Dly = 32
5076 23:03:18.915231 CS Dly: 5 (0~36)
5077 23:03:18.915298 ==
5078 23:03:18.918125 Dram Type= 6, Freq= 0, CH_0, rank 1
5079 23:03:18.924609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5080 23:03:18.924697 ==
5081 23:03:18.927808 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5082 23:03:18.934720 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5083 23:03:18.938082 [CA 0] Center 38 (8~68) winsize 61
5084 23:03:18.941424 [CA 1] Center 37 (7~68) winsize 62
5085 23:03:18.945140 [CA 2] Center 34 (4~65) winsize 62
5086 23:03:18.948104 [CA 3] Center 34 (4~65) winsize 62
5087 23:03:18.951179 [CA 4] Center 33 (3~64) winsize 62
5088 23:03:18.954528 [CA 5] Center 32 (2~63) winsize 62
5089 23:03:18.954613
5090 23:03:18.957721 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5091 23:03:18.957834
5092 23:03:18.961132 [CATrainingPosCal] consider 2 rank data
5093 23:03:18.964356 u2DelayCellTimex100 = 270/100 ps
5094 23:03:18.968011 CA0 delay=38 (8~68),Diff = 6 PI (37 cell)
5095 23:03:18.974236 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5096 23:03:18.977339 CA2 delay=34 (4~64),Diff = 2 PI (12 cell)
5097 23:03:18.981298 CA3 delay=34 (4~64),Diff = 2 PI (12 cell)
5098 23:03:18.984057 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5099 23:03:18.987793 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5100 23:03:18.987887
5101 23:03:18.991075 CA PerBit enable=1, Macro0, CA PI delay=32
5102 23:03:18.991173
5103 23:03:18.994466 [CBTSetCACLKResult] CA Dly = 32
5104 23:03:18.997442 CS Dly: 6 (0~39)
5105 23:03:18.997598
5106 23:03:19.000378 ----->DramcWriteLeveling(PI) begin...
5107 23:03:19.000530 ==
5108 23:03:19.004077 Dram Type= 6, Freq= 0, CH_0, rank 0
5109 23:03:19.007056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5110 23:03:19.007212 ==
5111 23:03:19.010683 Write leveling (Byte 0): 33 => 33
5112 23:03:19.014039 Write leveling (Byte 1): 25 => 25
5113 23:03:19.016978 DramcWriteLeveling(PI) end<-----
5114 23:03:19.017132
5115 23:03:19.017260 ==
5116 23:03:19.020431 Dram Type= 6, Freq= 0, CH_0, rank 0
5117 23:03:19.023380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5118 23:03:19.023529 ==
5119 23:03:19.026971 [Gating] SW mode calibration
5120 23:03:19.033439 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5121 23:03:19.040028 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5122 23:03:19.043535 0 14 0 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
5123 23:03:19.049736 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5124 23:03:19.052890 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5125 23:03:19.056283 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5126 23:03:19.062988 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5127 23:03:19.066427 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5128 23:03:19.069469 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5129 23:03:19.076684 0 14 28 | B1->B0 | 3434 2e2e | 1 0 | (1 0) (1 0)
5130 23:03:19.079139 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
5131 23:03:19.082816 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5132 23:03:19.089405 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5133 23:03:19.092733 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5134 23:03:19.095973 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5135 23:03:19.102623 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5136 23:03:19.106044 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5137 23:03:19.109037 0 15 28 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (1 1)
5138 23:03:19.115860 1 0 0 | B1->B0 | 3a3a 4646 | 0 0 | (1 1) (0 0)
5139 23:03:19.118683 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5140 23:03:19.122217 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5141 23:03:19.128496 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5142 23:03:19.131764 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5143 23:03:19.135278 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5144 23:03:19.141534 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5145 23:03:19.144998 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5146 23:03:19.148651 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5147 23:03:19.155074 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5148 23:03:19.158214 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5149 23:03:19.161665 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5150 23:03:19.168401 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 23:03:19.171604 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 23:03:19.175156 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5153 23:03:19.181432 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 23:03:19.184698 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 23:03:19.188104 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 23:03:19.194379 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 23:03:19.197864 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5158 23:03:19.200732 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5159 23:03:19.207416 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5160 23:03:19.210873 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 23:03:19.213963 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5162 23:03:19.221007 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5163 23:03:19.223921 Total UI for P1: 0, mck2ui 16
5164 23:03:19.227286 best dqsien dly found for B0: ( 1, 2, 28)
5165 23:03:19.230581 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5166 23:03:19.233913 Total UI for P1: 0, mck2ui 16
5167 23:03:19.237597 best dqsien dly found for B1: ( 1, 3, 0)
5168 23:03:19.240630 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5169 23:03:19.244084 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5170 23:03:19.244189
5171 23:03:19.246988 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5172 23:03:19.250561 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5173 23:03:19.253492 [Gating] SW calibration Done
5174 23:03:19.253575 ==
5175 23:03:19.256878 Dram Type= 6, Freq= 0, CH_0, rank 0
5176 23:03:19.263500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5177 23:03:19.263610 ==
5178 23:03:19.263705 RX Vref Scan: 0
5179 23:03:19.263800
5180 23:03:19.266934 RX Vref 0 -> 0, step: 1
5181 23:03:19.267032
5182 23:03:19.269961 RX Delay -80 -> 252, step: 8
5183 23:03:19.273647 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5184 23:03:19.277078 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5185 23:03:19.279621 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5186 23:03:19.283202 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5187 23:03:19.289763 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5188 23:03:19.293749 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5189 23:03:19.296597 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5190 23:03:19.299560 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5191 23:03:19.303180 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5192 23:03:19.306703 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5193 23:03:19.313074 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5194 23:03:19.315913 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5195 23:03:19.319290 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5196 23:03:19.323039 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5197 23:03:19.326146 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5198 23:03:19.332799 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5199 23:03:19.332903 ==
5200 23:03:19.335818 Dram Type= 6, Freq= 0, CH_0, rank 0
5201 23:03:19.339578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5202 23:03:19.339663 ==
5203 23:03:19.339729 DQS Delay:
5204 23:03:19.342839 DQS0 = 0, DQS1 = 0
5205 23:03:19.342922 DQM Delay:
5206 23:03:19.345971 DQM0 = 99, DQM1 = 88
5207 23:03:19.346054 DQ Delay:
5208 23:03:19.348842 DQ0 =103, DQ1 =99, DQ2 =95, DQ3 =95
5209 23:03:19.352177 DQ4 =103, DQ5 =87, DQ6 =107, DQ7 =107
5210 23:03:19.355654 DQ8 =83, DQ9 =75, DQ10 =87, DQ11 =83
5211 23:03:19.358560 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5212 23:03:19.358671
5213 23:03:19.358766
5214 23:03:19.358873 ==
5215 23:03:19.362060 Dram Type= 6, Freq= 0, CH_0, rank 0
5216 23:03:19.368662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5217 23:03:19.368781 ==
5218 23:03:19.368880
5219 23:03:19.368968
5220 23:03:19.369071 TX Vref Scan disable
5221 23:03:19.371980 == TX Byte 0 ==
5222 23:03:19.375376 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5223 23:03:19.381927 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5224 23:03:19.382010 == TX Byte 1 ==
5225 23:03:19.385569 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5226 23:03:19.392160 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5227 23:03:19.392244 ==
5228 23:03:19.395315 Dram Type= 6, Freq= 0, CH_0, rank 0
5229 23:03:19.398335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5230 23:03:19.398447 ==
5231 23:03:19.398567
5232 23:03:19.398667
5233 23:03:19.402126 TX Vref Scan disable
5234 23:03:19.405091 == TX Byte 0 ==
5235 23:03:19.408369 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5236 23:03:19.411460 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5237 23:03:19.415023 == TX Byte 1 ==
5238 23:03:19.418571 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5239 23:03:19.421663 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5240 23:03:19.421747
5241 23:03:19.421812 [DATLAT]
5242 23:03:19.425146 Freq=933, CH0 RK0
5243 23:03:19.425229
5244 23:03:19.428423 DATLAT Default: 0xd
5245 23:03:19.428505 0, 0xFFFF, sum = 0
5246 23:03:19.431526 1, 0xFFFF, sum = 0
5247 23:03:19.431610 2, 0xFFFF, sum = 0
5248 23:03:19.434689 3, 0xFFFF, sum = 0
5249 23:03:19.434776 4, 0xFFFF, sum = 0
5250 23:03:19.437995 5, 0xFFFF, sum = 0
5251 23:03:19.438080 6, 0xFFFF, sum = 0
5252 23:03:19.441425 7, 0xFFFF, sum = 0
5253 23:03:19.441509 8, 0xFFFF, sum = 0
5254 23:03:19.444949 9, 0xFFFF, sum = 0
5255 23:03:19.445035 10, 0x0, sum = 1
5256 23:03:19.447660 11, 0x0, sum = 2
5257 23:03:19.447747 12, 0x0, sum = 3
5258 23:03:19.451145 13, 0x0, sum = 4
5259 23:03:19.451229 best_step = 11
5260 23:03:19.451295
5261 23:03:19.451356 ==
5262 23:03:19.454569 Dram Type= 6, Freq= 0, CH_0, rank 0
5263 23:03:19.457987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5264 23:03:19.461222 ==
5265 23:03:19.461305 RX Vref Scan: 1
5266 23:03:19.461371
5267 23:03:19.464607 RX Vref 0 -> 0, step: 1
5268 23:03:19.464690
5269 23:03:19.467854 RX Delay -61 -> 252, step: 4
5270 23:03:19.467937
5271 23:03:19.470895 Set Vref, RX VrefLevel [Byte0]: 52
5272 23:03:19.474587 [Byte1]: 59
5273 23:03:19.474671
5274 23:03:19.477594 Final RX Vref Byte 0 = 52 to rank0
5275 23:03:19.481057 Final RX Vref Byte 1 = 59 to rank0
5276 23:03:19.484401 Final RX Vref Byte 0 = 52 to rank1
5277 23:03:19.487058 Final RX Vref Byte 1 = 59 to rank1==
5278 23:03:19.490743 Dram Type= 6, Freq= 0, CH_0, rank 0
5279 23:03:19.493980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5280 23:03:19.494063 ==
5281 23:03:19.497118 DQS Delay:
5282 23:03:19.497200 DQS0 = 0, DQS1 = 0
5283 23:03:19.497267 DQM Delay:
5284 23:03:19.500403 DQM0 = 99, DQM1 = 87
5285 23:03:19.500485 DQ Delay:
5286 23:03:19.504326 DQ0 =100, DQ1 =100, DQ2 =94, DQ3 =96
5287 23:03:19.507216 DQ4 =100, DQ5 =90, DQ6 =108, DQ7 =104
5288 23:03:19.510665 DQ8 =78, DQ9 =74, DQ10 =88, DQ11 =82
5289 23:03:19.513601 DQ12 =96, DQ13 =92, DQ14 =98, DQ15 =94
5290 23:03:19.513678
5291 23:03:19.513745
5292 23:03:19.523452 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b16, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 413 ps
5293 23:03:19.526727 CH0 RK0: MR19=505, MR18=1B16
5294 23:03:19.534032 CH0_RK0: MR19=0x505, MR18=0x1B16, DQSOSC=413, MR23=63, INC=63, DEC=42
5295 23:03:19.534120
5296 23:03:19.536620 ----->DramcWriteLeveling(PI) begin...
5297 23:03:19.536705 ==
5298 23:03:19.540880 Dram Type= 6, Freq= 0, CH_0, rank 1
5299 23:03:19.543297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5300 23:03:19.543381 ==
5301 23:03:19.546687 Write leveling (Byte 0): 33 => 33
5302 23:03:19.550123 Write leveling (Byte 1): 31 => 31
5303 23:03:19.553410 DramcWriteLeveling(PI) end<-----
5304 23:03:19.553499
5305 23:03:19.553566 ==
5306 23:03:19.556796 Dram Type= 6, Freq= 0, CH_0, rank 1
5307 23:03:19.559645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5308 23:03:19.559756 ==
5309 23:03:19.563177 [Gating] SW mode calibration
5310 23:03:19.569683 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5311 23:03:19.576358 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5312 23:03:19.579331 0 14 0 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
5313 23:03:19.586167 0 14 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
5314 23:03:19.589801 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5315 23:03:19.592604 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5316 23:03:19.599685 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5317 23:03:19.602433 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5318 23:03:19.605888 0 14 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
5319 23:03:19.612617 0 14 28 | B1->B0 | 3333 2b2b | 1 0 | (0 1) (0 0)
5320 23:03:19.615634 0 15 0 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
5321 23:03:19.619042 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5322 23:03:19.625830 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5323 23:03:19.628815 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5324 23:03:19.632418 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5325 23:03:19.638691 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5326 23:03:19.641759 0 15 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5327 23:03:19.645173 0 15 28 | B1->B0 | 2727 3c3c | 0 0 | (0 0) (0 0)
5328 23:03:19.651571 1 0 0 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
5329 23:03:19.654816 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5330 23:03:19.658179 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5331 23:03:19.665170 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5332 23:03:19.668033 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5333 23:03:19.671410 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5334 23:03:19.678208 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5335 23:03:19.681386 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5336 23:03:19.684532 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5337 23:03:19.691120 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5338 23:03:19.694768 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5339 23:03:19.697951 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5340 23:03:19.704510 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5341 23:03:19.707929 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5342 23:03:19.711191 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 23:03:19.717930 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5344 23:03:19.720977 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5345 23:03:19.724261 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5346 23:03:19.730563 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5347 23:03:19.734019 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5348 23:03:19.737444 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5349 23:03:19.744088 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5350 23:03:19.747494 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5351 23:03:19.750848 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5352 23:03:19.757095 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5353 23:03:19.757175 Total UI for P1: 0, mck2ui 16
5354 23:03:19.763999 best dqsien dly found for B0: ( 1, 2, 28)
5355 23:03:19.766734 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5356 23:03:19.770619 Total UI for P1: 0, mck2ui 16
5357 23:03:19.773772 best dqsien dly found for B1: ( 1, 3, 0)
5358 23:03:19.776928 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5359 23:03:19.780144 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5360 23:03:19.780221
5361 23:03:19.783309 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5362 23:03:19.786793 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5363 23:03:19.790026 [Gating] SW calibration Done
5364 23:03:19.790132 ==
5365 23:03:19.793498 Dram Type= 6, Freq= 0, CH_0, rank 1
5366 23:03:19.800038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5367 23:03:19.800123 ==
5368 23:03:19.800189 RX Vref Scan: 0
5369 23:03:19.800251
5370 23:03:19.803305 RX Vref 0 -> 0, step: 1
5371 23:03:19.803402
5372 23:03:19.806559 RX Delay -80 -> 252, step: 8
5373 23:03:19.809619 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5374 23:03:19.812984 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5375 23:03:19.816551 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5376 23:03:19.819792 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5377 23:03:19.822630 iDelay=200, Bit 4, Center 99 (0 ~ 199) 200
5378 23:03:19.829297 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5379 23:03:19.832611 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5380 23:03:19.835951 iDelay=200, Bit 7, Center 107 (16 ~ 199) 184
5381 23:03:19.839324 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5382 23:03:19.843101 iDelay=200, Bit 9, Center 79 (-8 ~ 167) 176
5383 23:03:19.849035 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5384 23:03:19.852422 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5385 23:03:19.855815 iDelay=200, Bit 12, Center 95 (8 ~ 183) 176
5386 23:03:19.859076 iDelay=200, Bit 13, Center 99 (8 ~ 191) 184
5387 23:03:19.862165 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5388 23:03:19.865712 iDelay=200, Bit 15, Center 99 (8 ~ 191) 184
5389 23:03:19.868864 ==
5390 23:03:19.871904 Dram Type= 6, Freq= 0, CH_0, rank 1
5391 23:03:19.875297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5392 23:03:19.875380 ==
5393 23:03:19.875447 DQS Delay:
5394 23:03:19.878715 DQS0 = 0, DQS1 = 0
5395 23:03:19.878797 DQM Delay:
5396 23:03:19.882143 DQM0 = 97, DQM1 = 91
5397 23:03:19.882271 DQ Delay:
5398 23:03:19.885524 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =95
5399 23:03:19.888454 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =107
5400 23:03:19.892129 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =83
5401 23:03:19.895034 DQ12 =95, DQ13 =99, DQ14 =99, DQ15 =99
5402 23:03:19.895117
5403 23:03:19.895182
5404 23:03:19.895242 ==
5405 23:03:19.898695 Dram Type= 6, Freq= 0, CH_0, rank 1
5406 23:03:19.901774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5407 23:03:19.901868 ==
5408 23:03:19.905029
5409 23:03:19.905136
5410 23:03:19.905206 TX Vref Scan disable
5411 23:03:19.908094 == TX Byte 0 ==
5412 23:03:19.911535 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5413 23:03:19.914916 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5414 23:03:19.918059 == TX Byte 1 ==
5415 23:03:19.921546 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5416 23:03:19.925051 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5417 23:03:19.925133 ==
5418 23:03:19.927832 Dram Type= 6, Freq= 0, CH_0, rank 1
5419 23:03:19.934475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5420 23:03:19.934558 ==
5421 23:03:19.934624
5422 23:03:19.934683
5423 23:03:19.937783 TX Vref Scan disable
5424 23:03:19.937864 == TX Byte 0 ==
5425 23:03:19.944791 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5426 23:03:19.947615 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5427 23:03:19.947697 == TX Byte 1 ==
5428 23:03:19.954459 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5429 23:03:19.957814 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5430 23:03:19.957895
5431 23:03:19.957960 [DATLAT]
5432 23:03:19.961087 Freq=933, CH0 RK1
5433 23:03:19.961169
5434 23:03:19.961234 DATLAT Default: 0xb
5435 23:03:19.964183 0, 0xFFFF, sum = 0
5436 23:03:19.964267 1, 0xFFFF, sum = 0
5437 23:03:19.967718 2, 0xFFFF, sum = 0
5438 23:03:19.967801 3, 0xFFFF, sum = 0
5439 23:03:19.970925 4, 0xFFFF, sum = 0
5440 23:03:19.971023 5, 0xFFFF, sum = 0
5441 23:03:19.974088 6, 0xFFFF, sum = 0
5442 23:03:19.977263 7, 0xFFFF, sum = 0
5443 23:03:19.977346 8, 0xFFFF, sum = 0
5444 23:03:19.981064 9, 0xFFFF, sum = 0
5445 23:03:19.981173 10, 0x0, sum = 1
5446 23:03:19.983625 11, 0x0, sum = 2
5447 23:03:19.983709 12, 0x0, sum = 3
5448 23:03:19.983776 13, 0x0, sum = 4
5449 23:03:19.987069 best_step = 11
5450 23:03:19.987151
5451 23:03:19.987216 ==
5452 23:03:19.990430 Dram Type= 6, Freq= 0, CH_0, rank 1
5453 23:03:19.993663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5454 23:03:19.993790 ==
5455 23:03:19.996877 RX Vref Scan: 0
5456 23:03:19.996958
5457 23:03:20.000359 RX Vref 0 -> 0, step: 1
5458 23:03:20.000441
5459 23:03:20.000506 RX Delay -53 -> 252, step: 4
5460 23:03:20.007972 iDelay=195, Bit 0, Center 96 (11 ~ 182) 172
5461 23:03:20.011488 iDelay=195, Bit 1, Center 98 (7 ~ 190) 184
5462 23:03:20.014459 iDelay=195, Bit 2, Center 94 (3 ~ 186) 184
5463 23:03:20.017637 iDelay=195, Bit 3, Center 94 (3 ~ 186) 184
5464 23:03:20.020956 iDelay=195, Bit 4, Center 102 (11 ~ 194) 184
5465 23:03:20.027888 iDelay=195, Bit 5, Center 86 (-5 ~ 178) 184
5466 23:03:20.031138 iDelay=195, Bit 6, Center 106 (19 ~ 194) 176
5467 23:03:20.034385 iDelay=195, Bit 7, Center 104 (15 ~ 194) 180
5468 23:03:20.037452 iDelay=195, Bit 8, Center 80 (-5 ~ 166) 172
5469 23:03:20.040990 iDelay=195, Bit 9, Center 76 (-9 ~ 162) 172
5470 23:03:20.047585 iDelay=195, Bit 10, Center 90 (-1 ~ 182) 184
5471 23:03:20.050562 iDelay=195, Bit 11, Center 84 (-5 ~ 174) 180
5472 23:03:20.053877 iDelay=195, Bit 12, Center 94 (7 ~ 182) 176
5473 23:03:20.057341 iDelay=195, Bit 13, Center 96 (7 ~ 186) 180
5474 23:03:20.060735 iDelay=195, Bit 14, Center 98 (11 ~ 186) 176
5475 23:03:20.063786 iDelay=195, Bit 15, Center 96 (7 ~ 186) 180
5476 23:03:20.067321 ==
5477 23:03:20.070546 Dram Type= 6, Freq= 0, CH_0, rank 1
5478 23:03:20.073381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5479 23:03:20.073485 ==
5480 23:03:20.073553 DQS Delay:
5481 23:03:20.076685 DQS0 = 0, DQS1 = 0
5482 23:03:20.076766 DQM Delay:
5483 23:03:20.080426 DQM0 = 97, DQM1 = 89
5484 23:03:20.080509 DQ Delay:
5485 23:03:20.083411 DQ0 =96, DQ1 =98, DQ2 =94, DQ3 =94
5486 23:03:20.086703 DQ4 =102, DQ5 =86, DQ6 =106, DQ7 =104
5487 23:03:20.090101 DQ8 =80, DQ9 =76, DQ10 =90, DQ11 =84
5488 23:03:20.093165 DQ12 =94, DQ13 =96, DQ14 =98, DQ15 =96
5489 23:03:20.093271
5490 23:03:20.093360
5491 23:03:20.100313 [DQSOSCAuto] RK1, (LSB)MR18= 0x1512, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 415 ps
5492 23:03:20.103454 CH0 RK1: MR19=505, MR18=1512
5493 23:03:20.110064 CH0_RK1: MR19=0x505, MR18=0x1512, DQSOSC=415, MR23=63, INC=62, DEC=41
5494 23:03:20.113047 [RxdqsGatingPostProcess] freq 933
5495 23:03:20.119618 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5496 23:03:20.122911 best DQS0 dly(2T, 0.5T) = (0, 10)
5497 23:03:20.126316 best DQS1 dly(2T, 0.5T) = (0, 11)
5498 23:03:20.129630 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5499 23:03:20.133222 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5500 23:03:20.133298 best DQS0 dly(2T, 0.5T) = (0, 10)
5501 23:03:20.136227 best DQS1 dly(2T, 0.5T) = (0, 11)
5502 23:03:20.139891 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5503 23:03:20.142760 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5504 23:03:20.146027 Pre-setting of DQS Precalculation
5505 23:03:20.152883 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5506 23:03:20.152976 ==
5507 23:03:20.156365 Dram Type= 6, Freq= 0, CH_1, rank 0
5508 23:03:20.159851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5509 23:03:20.159926 ==
5510 23:03:20.166029 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5511 23:03:20.172832 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5512 23:03:20.176004 [CA 0] Center 36 (6~67) winsize 62
5513 23:03:20.179411 [CA 1] Center 36 (6~67) winsize 62
5514 23:03:20.182441 [CA 2] Center 34 (4~64) winsize 61
5515 23:03:20.185703 [CA 3] Center 33 (3~64) winsize 62
5516 23:03:20.189141 [CA 4] Center 33 (3~64) winsize 62
5517 23:03:20.192605 [CA 5] Center 33 (3~64) winsize 62
5518 23:03:20.192679
5519 23:03:20.196147 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5520 23:03:20.196223
5521 23:03:20.199203 [CATrainingPosCal] consider 1 rank data
5522 23:03:20.202339 u2DelayCellTimex100 = 270/100 ps
5523 23:03:20.205756 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5524 23:03:20.208823 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5525 23:03:20.211978 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5526 23:03:20.215229 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5527 23:03:20.218829 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5528 23:03:20.222309 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5529 23:03:20.222385
5530 23:03:20.228327 CA PerBit enable=1, Macro0, CA PI delay=33
5531 23:03:20.228412
5532 23:03:20.231718 [CBTSetCACLKResult] CA Dly = 33
5533 23:03:20.231820 CS Dly: 4 (0~35)
5534 23:03:20.231916 ==
5535 23:03:20.235351 Dram Type= 6, Freq= 0, CH_1, rank 1
5536 23:03:20.238574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5537 23:03:20.238656 ==
5538 23:03:20.245353 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5539 23:03:20.251413 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5540 23:03:20.254709 [CA 0] Center 36 (6~66) winsize 61
5541 23:03:20.258135 [CA 1] Center 36 (6~67) winsize 62
5542 23:03:20.261786 [CA 2] Center 34 (4~65) winsize 62
5543 23:03:20.265079 [CA 3] Center 33 (3~64) winsize 62
5544 23:03:20.267760 [CA 4] Center 34 (4~64) winsize 61
5545 23:03:20.271345 [CA 5] Center 33 (3~64) winsize 62
5546 23:03:20.271453
5547 23:03:20.274955 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5548 23:03:20.275068
5549 23:03:20.277732 [CATrainingPosCal] consider 2 rank data
5550 23:03:20.281379 u2DelayCellTimex100 = 270/100 ps
5551 23:03:20.284672 CA0 delay=36 (6~66),Diff = 3 PI (18 cell)
5552 23:03:20.287969 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5553 23:03:20.291255 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5554 23:03:20.294269 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5555 23:03:20.301300 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5556 23:03:20.304753 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5557 23:03:20.304834
5558 23:03:20.307354 CA PerBit enable=1, Macro0, CA PI delay=33
5559 23:03:20.307431
5560 23:03:20.310655 [CBTSetCACLKResult] CA Dly = 33
5561 23:03:20.310733 CS Dly: 5 (0~38)
5562 23:03:20.310799
5563 23:03:20.314529 ----->DramcWriteLeveling(PI) begin...
5564 23:03:20.314601 ==
5565 23:03:20.317445 Dram Type= 6, Freq= 0, CH_1, rank 0
5566 23:03:20.324231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5567 23:03:20.324311 ==
5568 23:03:20.327517 Write leveling (Byte 0): 26 => 26
5569 23:03:20.330399 Write leveling (Byte 1): 26 => 26
5570 23:03:20.333660 DramcWriteLeveling(PI) end<-----
5571 23:03:20.333735
5572 23:03:20.333797 ==
5573 23:03:20.337136 Dram Type= 6, Freq= 0, CH_1, rank 0
5574 23:03:20.340637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5575 23:03:20.340715 ==
5576 23:03:20.344332 [Gating] SW mode calibration
5577 23:03:20.350205 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5578 23:03:20.357046 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5579 23:03:20.360487 0 14 0 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
5580 23:03:20.363688 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5581 23:03:20.370683 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5582 23:03:20.373712 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5583 23:03:20.376428 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5584 23:03:20.379927 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5585 23:03:20.386780 0 14 24 | B1->B0 | 3434 3232 | 0 0 | (0 0) (0 1)
5586 23:03:20.389669 0 14 28 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
5587 23:03:20.393160 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5588 23:03:20.399947 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5589 23:03:20.403132 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5590 23:03:20.406516 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5591 23:03:20.412984 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5592 23:03:20.416290 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5593 23:03:20.419784 0 15 24 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
5594 23:03:20.426455 0 15 28 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
5595 23:03:20.429543 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5596 23:03:20.433415 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5597 23:03:20.439319 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5598 23:03:20.442709 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5599 23:03:20.446137 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5600 23:03:20.453037 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5601 23:03:20.455665 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5602 23:03:20.459218 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5603 23:03:20.465973 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5604 23:03:20.469022 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5605 23:03:20.472772 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5606 23:03:20.479103 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5607 23:03:20.482537 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 23:03:20.485840 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 23:03:20.492008 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5610 23:03:20.495784 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 23:03:20.499102 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 23:03:20.505354 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 23:03:20.508712 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5614 23:03:20.512093 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5615 23:03:20.519020 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 23:03:20.522133 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 23:03:20.525242 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 23:03:20.531575 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5619 23:03:20.535205 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5620 23:03:20.538718 Total UI for P1: 0, mck2ui 16
5621 23:03:20.541440 best dqsien dly found for B0: ( 1, 2, 28)
5622 23:03:20.544913 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5623 23:03:20.548241 Total UI for P1: 0, mck2ui 16
5624 23:03:20.551408 best dqsien dly found for B1: ( 1, 2, 30)
5625 23:03:20.554861 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5626 23:03:20.561336 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5627 23:03:20.561413
5628 23:03:20.564813 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5629 23:03:20.567928 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5630 23:03:20.571404 [Gating] SW calibration Done
5631 23:03:20.571483 ==
5632 23:03:20.574557 Dram Type= 6, Freq= 0, CH_1, rank 0
5633 23:03:20.577680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5634 23:03:20.577803 ==
5635 23:03:20.581162 RX Vref Scan: 0
5636 23:03:20.581247
5637 23:03:20.581313 RX Vref 0 -> 0, step: 1
5638 23:03:20.581374
5639 23:03:20.584676 RX Delay -80 -> 252, step: 8
5640 23:03:20.587544 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5641 23:03:20.594405 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5642 23:03:20.597444 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5643 23:03:20.600726 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5644 23:03:20.604561 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5645 23:03:20.607288 iDelay=208, Bit 5, Center 107 (16 ~ 199) 184
5646 23:03:20.610785 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5647 23:03:20.617569 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5648 23:03:20.620497 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5649 23:03:20.624234 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5650 23:03:20.627313 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5651 23:03:20.630470 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5652 23:03:20.634053 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5653 23:03:20.640622 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5654 23:03:20.643711 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5655 23:03:20.647042 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5656 23:03:20.647119 ==
5657 23:03:20.650377 Dram Type= 6, Freq= 0, CH_1, rank 0
5658 23:03:20.653641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5659 23:03:20.653712 ==
5660 23:03:20.656884 DQS Delay:
5661 23:03:20.656986 DQS0 = 0, DQS1 = 0
5662 23:03:20.660294 DQM Delay:
5663 23:03:20.660367 DQM0 = 98, DQM1 = 95
5664 23:03:20.663366 DQ Delay:
5665 23:03:20.663437 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =99
5666 23:03:20.667061 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =95
5667 23:03:20.670401 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =87
5668 23:03:20.676808 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5669 23:03:20.676891
5670 23:03:20.676956
5671 23:03:20.677020 ==
5672 23:03:20.680317 Dram Type= 6, Freq= 0, CH_1, rank 0
5673 23:03:20.683453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5674 23:03:20.683540 ==
5675 23:03:20.683607
5676 23:03:20.683668
5677 23:03:20.686789 TX Vref Scan disable
5678 23:03:20.686862 == TX Byte 0 ==
5679 23:03:20.693552 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5680 23:03:20.696719 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5681 23:03:20.696821 == TX Byte 1 ==
5682 23:03:20.702946 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5683 23:03:20.706386 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5684 23:03:20.706462 ==
5685 23:03:20.709599 Dram Type= 6, Freq= 0, CH_1, rank 0
5686 23:03:20.712801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5687 23:03:20.712875 ==
5688 23:03:20.716190
5689 23:03:20.716265
5690 23:03:20.716328 TX Vref Scan disable
5691 23:03:20.719482 == TX Byte 0 ==
5692 23:03:20.722859 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5693 23:03:20.729398 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5694 23:03:20.729473 == TX Byte 1 ==
5695 23:03:20.732857 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5696 23:03:20.739808 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5697 23:03:20.739880
5698 23:03:20.739942 [DATLAT]
5699 23:03:20.740000 Freq=933, CH1 RK0
5700 23:03:20.740062
5701 23:03:20.742916 DATLAT Default: 0xd
5702 23:03:20.745953 0, 0xFFFF, sum = 0
5703 23:03:20.746027 1, 0xFFFF, sum = 0
5704 23:03:20.749072 2, 0xFFFF, sum = 0
5705 23:03:20.749145 3, 0xFFFF, sum = 0
5706 23:03:20.752179 4, 0xFFFF, sum = 0
5707 23:03:20.752255 5, 0xFFFF, sum = 0
5708 23:03:20.755599 6, 0xFFFF, sum = 0
5709 23:03:20.755676 7, 0xFFFF, sum = 0
5710 23:03:20.758875 8, 0xFFFF, sum = 0
5711 23:03:20.758946 9, 0xFFFF, sum = 0
5712 23:03:20.762084 10, 0x0, sum = 1
5713 23:03:20.762185 11, 0x0, sum = 2
5714 23:03:20.765310 12, 0x0, sum = 3
5715 23:03:20.765399 13, 0x0, sum = 4
5716 23:03:20.768682 best_step = 11
5717 23:03:20.768765
5718 23:03:20.768831 ==
5719 23:03:20.772211 Dram Type= 6, Freq= 0, CH_1, rank 0
5720 23:03:20.775705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5721 23:03:20.775798 ==
5722 23:03:20.775865 RX Vref Scan: 1
5723 23:03:20.778820
5724 23:03:20.778919 RX Vref 0 -> 0, step: 1
5725 23:03:20.779018
5726 23:03:20.782051 RX Delay -53 -> 252, step: 4
5727 23:03:20.782149
5728 23:03:20.785218 Set Vref, RX VrefLevel [Byte0]: 51
5729 23:03:20.788395 [Byte1]: 52
5730 23:03:20.792283
5731 23:03:20.792419 Final RX Vref Byte 0 = 51 to rank0
5732 23:03:20.795692 Final RX Vref Byte 1 = 52 to rank0
5733 23:03:20.798574 Final RX Vref Byte 0 = 51 to rank1
5734 23:03:20.802039 Final RX Vref Byte 1 = 52 to rank1==
5735 23:03:20.805424 Dram Type= 6, Freq= 0, CH_1, rank 0
5736 23:03:20.812038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5737 23:03:20.812121 ==
5738 23:03:20.812219 DQS Delay:
5739 23:03:20.815102 DQS0 = 0, DQS1 = 0
5740 23:03:20.815184 DQM Delay:
5741 23:03:20.815249 DQM0 = 98, DQM1 = 95
5742 23:03:20.818565 DQ Delay:
5743 23:03:20.822020 DQ0 =102, DQ1 =94, DQ2 =88, DQ3 =98
5744 23:03:20.824810 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =94
5745 23:03:20.828320 DQ8 =80, DQ9 =84, DQ10 =94, DQ11 =90
5746 23:03:20.832104 DQ12 =104, DQ13 =102, DQ14 =102, DQ15 =104
5747 23:03:20.832186
5748 23:03:20.832252
5749 23:03:20.838430 [DQSOSCAuto] RK0, (LSB)MR18= 0x818, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 419 ps
5750 23:03:20.841844 CH1 RK0: MR19=505, MR18=818
5751 23:03:20.848245 CH1_RK0: MR19=0x505, MR18=0x818, DQSOSC=414, MR23=63, INC=63, DEC=42
5752 23:03:20.848328
5753 23:03:20.851648 ----->DramcWriteLeveling(PI) begin...
5754 23:03:20.851731 ==
5755 23:03:20.854985 Dram Type= 6, Freq= 0, CH_1, rank 1
5756 23:03:20.858153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5757 23:03:20.858237 ==
5758 23:03:20.861542 Write leveling (Byte 0): 26 => 26
5759 23:03:20.864218 Write leveling (Byte 1): 29 => 29
5760 23:03:20.867549 DramcWriteLeveling(PI) end<-----
5761 23:03:20.867655
5762 23:03:20.867756 ==
5763 23:03:20.871193 Dram Type= 6, Freq= 0, CH_1, rank 1
5764 23:03:20.878405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5765 23:03:20.878488 ==
5766 23:03:20.878570 [Gating] SW mode calibration
5767 23:03:20.887403 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5768 23:03:20.890621 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5769 23:03:20.897922 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5770 23:03:20.900622 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5771 23:03:20.904015 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5772 23:03:20.910740 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5773 23:03:20.914214 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5774 23:03:20.917115 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5775 23:03:20.923722 0 14 24 | B1->B0 | 3434 2f2f | 0 0 | (0 0) (0 0)
5776 23:03:20.927224 0 14 28 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
5777 23:03:20.930145 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5778 23:03:20.936781 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5779 23:03:20.940210 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5780 23:03:20.943338 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5781 23:03:20.950529 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5782 23:03:20.953484 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5783 23:03:20.957025 0 15 24 | B1->B0 | 2929 3535 | 0 0 | (1 1) (1 1)
5784 23:03:20.963288 0 15 28 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
5785 23:03:20.966811 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5786 23:03:20.969990 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5787 23:03:20.976213 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5788 23:03:20.979687 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5789 23:03:20.983207 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5790 23:03:20.989473 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5791 23:03:20.992615 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5792 23:03:20.996358 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5793 23:03:21.002363 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5794 23:03:21.006027 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5795 23:03:21.009708 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5796 23:03:21.015922 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5797 23:03:21.019433 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5798 23:03:21.022541 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5799 23:03:21.029037 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5800 23:03:21.031914 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5801 23:03:21.035327 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5802 23:03:21.041704 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5803 23:03:21.045345 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5804 23:03:21.048361 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5805 23:03:21.054917 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5806 23:03:21.058184 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5807 23:03:21.061430 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 23:03:21.068193 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5809 23:03:21.068277 Total UI for P1: 0, mck2ui 16
5810 23:03:21.074752 best dqsien dly found for B0: ( 1, 2, 26)
5811 23:03:21.078241 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5812 23:03:21.081648 Total UI for P1: 0, mck2ui 16
5813 23:03:21.084542 best dqsien dly found for B1: ( 1, 2, 28)
5814 23:03:21.087744 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5815 23:03:21.091352 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5816 23:03:21.091434
5817 23:03:21.094585 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5818 23:03:21.098228 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5819 23:03:21.101060 [Gating] SW calibration Done
5820 23:03:21.101142 ==
5821 23:03:21.104393 Dram Type= 6, Freq= 0, CH_1, rank 1
5822 23:03:21.111288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5823 23:03:21.111372 ==
5824 23:03:21.111439 RX Vref Scan: 0
5825 23:03:21.111500
5826 23:03:21.114684 RX Vref 0 -> 0, step: 1
5827 23:03:21.114765
5828 23:03:21.117494 RX Delay -80 -> 252, step: 8
5829 23:03:21.121031 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5830 23:03:21.123909 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5831 23:03:21.127234 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5832 23:03:21.130604 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5833 23:03:21.137383 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5834 23:03:21.140429 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5835 23:03:21.143952 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5836 23:03:21.147361 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5837 23:03:21.150596 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5838 23:03:21.154019 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5839 23:03:21.160151 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5840 23:03:21.163685 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5841 23:03:21.166738 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5842 23:03:21.170211 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5843 23:03:21.173532 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5844 23:03:21.180544 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5845 23:03:21.180671 ==
5846 23:03:21.183472 Dram Type= 6, Freq= 0, CH_1, rank 1
5847 23:03:21.186928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5848 23:03:21.187011 ==
5849 23:03:21.187077 DQS Delay:
5850 23:03:21.189979 DQS0 = 0, DQS1 = 0
5851 23:03:21.190086 DQM Delay:
5852 23:03:21.193518 DQM0 = 97, DQM1 = 94
5853 23:03:21.193599 DQ Delay:
5854 23:03:21.196410 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =95
5855 23:03:21.200044 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5856 23:03:21.203172 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5857 23:03:21.206685 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5858 23:03:21.206767
5859 23:03:21.206832
5860 23:03:21.206892 ==
5861 23:03:21.209600 Dram Type= 6, Freq= 0, CH_1, rank 1
5862 23:03:21.216598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5863 23:03:21.216680 ==
5864 23:03:21.216745
5865 23:03:21.216805
5866 23:03:21.216864 TX Vref Scan disable
5867 23:03:21.219660 == TX Byte 0 ==
5868 23:03:21.223274 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5869 23:03:21.229949 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5870 23:03:21.230032 == TX Byte 1 ==
5871 23:03:21.233177 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5872 23:03:21.239543 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5873 23:03:21.239628 ==
5874 23:03:21.243109 Dram Type= 6, Freq= 0, CH_1, rank 1
5875 23:03:21.246229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5876 23:03:21.246359 ==
5877 23:03:21.246453
5878 23:03:21.246540
5879 23:03:21.249530 TX Vref Scan disable
5880 23:03:21.249612 == TX Byte 0 ==
5881 23:03:21.256231 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5882 23:03:21.259223 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5883 23:03:21.262612 == TX Byte 1 ==
5884 23:03:21.265717 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5885 23:03:21.269364 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5886 23:03:21.269447
5887 23:03:21.269520 [DATLAT]
5888 23:03:21.272524 Freq=933, CH1 RK1
5889 23:03:21.272631
5890 23:03:21.275879 DATLAT Default: 0xb
5891 23:03:21.275961 0, 0xFFFF, sum = 0
5892 23:03:21.279368 1, 0xFFFF, sum = 0
5893 23:03:21.279467 2, 0xFFFF, sum = 0
5894 23:03:21.282235 3, 0xFFFF, sum = 0
5895 23:03:21.282356 4, 0xFFFF, sum = 0
5896 23:03:21.285458 5, 0xFFFF, sum = 0
5897 23:03:21.285541 6, 0xFFFF, sum = 0
5898 23:03:21.288847 7, 0xFFFF, sum = 0
5899 23:03:21.288930 8, 0xFFFF, sum = 0
5900 23:03:21.292575 9, 0xFFFF, sum = 0
5901 23:03:21.292659 10, 0x0, sum = 1
5902 23:03:21.295848 11, 0x0, sum = 2
5903 23:03:21.295932 12, 0x0, sum = 3
5904 23:03:21.298859 13, 0x0, sum = 4
5905 23:03:21.298942 best_step = 11
5906 23:03:21.299007
5907 23:03:21.299067 ==
5908 23:03:21.302174 Dram Type= 6, Freq= 0, CH_1, rank 1
5909 23:03:21.305767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5910 23:03:21.308596 ==
5911 23:03:21.308713 RX Vref Scan: 0
5912 23:03:21.308779
5913 23:03:21.312087 RX Vref 0 -> 0, step: 1
5914 23:03:21.312170
5915 23:03:21.315395 RX Delay -53 -> 252, step: 4
5916 23:03:21.318312 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5917 23:03:21.321816 iDelay=199, Bit 1, Center 94 (-1 ~ 190) 192
5918 23:03:21.328737 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5919 23:03:21.331641 iDelay=199, Bit 3, Center 96 (3 ~ 190) 188
5920 23:03:21.335201 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5921 23:03:21.338706 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5922 23:03:21.341281 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5923 23:03:21.344659 iDelay=199, Bit 7, Center 94 (-1 ~ 190) 192
5924 23:03:21.351322 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5925 23:03:21.354826 iDelay=199, Bit 9, Center 84 (-5 ~ 174) 180
5926 23:03:21.357990 iDelay=199, Bit 10, Center 92 (-1 ~ 186) 188
5927 23:03:21.361352 iDelay=199, Bit 11, Center 86 (-5 ~ 178) 184
5928 23:03:21.364876 iDelay=199, Bit 12, Center 102 (11 ~ 194) 184
5929 23:03:21.371429 iDelay=199, Bit 13, Center 100 (7 ~ 194) 188
5930 23:03:21.374760 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5931 23:03:21.377629 iDelay=199, Bit 15, Center 102 (11 ~ 194) 184
5932 23:03:21.377707 ==
5933 23:03:21.381353 Dram Type= 6, Freq= 0, CH_1, rank 1
5934 23:03:21.384232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5935 23:03:21.384334 ==
5936 23:03:21.387706 DQS Delay:
5937 23:03:21.387813 DQS0 = 0, DQS1 = 0
5938 23:03:21.390981 DQM Delay:
5939 23:03:21.391095 DQM0 = 97, DQM1 = 93
5940 23:03:21.394443 DQ Delay:
5941 23:03:21.394512 DQ0 =102, DQ1 =94, DQ2 =86, DQ3 =96
5942 23:03:21.397793 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =94
5943 23:03:21.400624 DQ8 =80, DQ9 =84, DQ10 =92, DQ11 =86
5944 23:03:21.407201 DQ12 =102, DQ13 =100, DQ14 =98, DQ15 =102
5945 23:03:21.407288
5946 23:03:21.407353
5947 23:03:21.414192 [DQSOSCAuto] RK1, (LSB)MR18= 0xa21, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 418 ps
5948 23:03:21.417136 CH1 RK1: MR19=505, MR18=A21
5949 23:03:21.424098 CH1_RK1: MR19=0x505, MR18=0xA21, DQSOSC=411, MR23=63, INC=64, DEC=42
5950 23:03:21.426888 [RxdqsGatingPostProcess] freq 933
5951 23:03:21.430471 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5952 23:03:21.433704 best DQS0 dly(2T, 0.5T) = (0, 10)
5953 23:03:21.437245 best DQS1 dly(2T, 0.5T) = (0, 10)
5954 23:03:21.440065 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5955 23:03:21.443631 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5956 23:03:21.447137 best DQS0 dly(2T, 0.5T) = (0, 10)
5957 23:03:21.450150 best DQS1 dly(2T, 0.5T) = (0, 10)
5958 23:03:21.453366 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5959 23:03:21.456394 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5960 23:03:21.460241 Pre-setting of DQS Precalculation
5961 23:03:21.463572 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5962 23:03:21.473423 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5963 23:03:21.479881 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5964 23:03:21.479960
5965 23:03:21.480028
5966 23:03:21.483123 [Calibration Summary] 1866 Mbps
5967 23:03:21.483194 CH 0, Rank 0
5968 23:03:21.486571 SW Impedance : PASS
5969 23:03:21.486641 DUTY Scan : NO K
5970 23:03:21.489691 ZQ Calibration : PASS
5971 23:03:21.492654 Jitter Meter : NO K
5972 23:03:21.492722 CBT Training : PASS
5973 23:03:21.496492 Write leveling : PASS
5974 23:03:21.499679 RX DQS gating : PASS
5975 23:03:21.499756 RX DQ/DQS(RDDQC) : PASS
5976 23:03:21.503198 TX DQ/DQS : PASS
5977 23:03:21.506073 RX DATLAT : PASS
5978 23:03:21.506146 RX DQ/DQS(Engine): PASS
5979 23:03:21.509782 TX OE : NO K
5980 23:03:21.509860 All Pass.
5981 23:03:21.509934
5982 23:03:21.512950 CH 0, Rank 1
5983 23:03:21.513026 SW Impedance : PASS
5984 23:03:21.516194 DUTY Scan : NO K
5985 23:03:21.519182 ZQ Calibration : PASS
5986 23:03:21.519251 Jitter Meter : NO K
5987 23:03:21.522399 CBT Training : PASS
5988 23:03:21.525702 Write leveling : PASS
5989 23:03:21.525780 RX DQS gating : PASS
5990 23:03:21.529190 RX DQ/DQS(RDDQC) : PASS
5991 23:03:21.532277 TX DQ/DQS : PASS
5992 23:03:21.532354 RX DATLAT : PASS
5993 23:03:21.535699 RX DQ/DQS(Engine): PASS
5994 23:03:21.538679 TX OE : NO K
5995 23:03:21.538751 All Pass.
5996 23:03:21.538814
5997 23:03:21.538871 CH 1, Rank 0
5998 23:03:21.542220 SW Impedance : PASS
5999 23:03:21.545506 DUTY Scan : NO K
6000 23:03:21.545580 ZQ Calibration : PASS
6001 23:03:21.548839 Jitter Meter : NO K
6002 23:03:21.552094 CBT Training : PASS
6003 23:03:21.552166 Write leveling : PASS
6004 23:03:21.555852 RX DQS gating : PASS
6005 23:03:21.558682 RX DQ/DQS(RDDQC) : PASS
6006 23:03:21.558753 TX DQ/DQS : PASS
6007 23:03:21.561588 RX DATLAT : PASS
6008 23:03:21.565115 RX DQ/DQS(Engine): PASS
6009 23:03:21.565186 TX OE : NO K
6010 23:03:21.565251 All Pass.
6011 23:03:21.568286
6012 23:03:21.568355 CH 1, Rank 1
6013 23:03:21.571414 SW Impedance : PASS
6014 23:03:21.571486 DUTY Scan : NO K
6015 23:03:21.574884 ZQ Calibration : PASS
6016 23:03:21.578450 Jitter Meter : NO K
6017 23:03:21.578565 CBT Training : PASS
6018 23:03:21.581917 Write leveling : PASS
6019 23:03:21.582014 RX DQS gating : PASS
6020 23:03:21.584494 RX DQ/DQS(RDDQC) : PASS
6021 23:03:21.587775 TX DQ/DQS : PASS
6022 23:03:21.587852 RX DATLAT : PASS
6023 23:03:21.591380 RX DQ/DQS(Engine): PASS
6024 23:03:21.594793 TX OE : NO K
6025 23:03:21.594867 All Pass.
6026 23:03:21.594932
6027 23:03:21.597789 DramC Write-DBI off
6028 23:03:21.597887 PER_BANK_REFRESH: Hybrid Mode
6029 23:03:21.601264 TX_TRACKING: ON
6030 23:03:21.611066 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6031 23:03:21.614739 [FAST_K] Save calibration result to emmc
6032 23:03:21.617857 dramc_set_vcore_voltage set vcore to 650000
6033 23:03:21.621139 Read voltage for 400, 6
6034 23:03:21.621249 Vio18 = 0
6035 23:03:21.621373 Vcore = 650000
6036 23:03:21.624544 Vdram = 0
6037 23:03:21.624622 Vddq = 0
6038 23:03:21.624683 Vmddr = 0
6039 23:03:21.630851 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6040 23:03:21.634416 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6041 23:03:21.637443 MEM_TYPE=3, freq_sel=20
6042 23:03:21.641037 sv_algorithm_assistance_LP4_800
6043 23:03:21.643999 ============ PULL DRAM RESETB DOWN ============
6044 23:03:21.647291 ========== PULL DRAM RESETB DOWN end =========
6045 23:03:21.654121 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6046 23:03:21.657064 ===================================
6047 23:03:21.657147 LPDDR4 DRAM CONFIGURATION
6048 23:03:21.660730 ===================================
6049 23:03:21.663980 EX_ROW_EN[0] = 0x0
6050 23:03:21.666793 EX_ROW_EN[1] = 0x0
6051 23:03:21.666866 LP4Y_EN = 0x0
6052 23:03:21.670018 WORK_FSP = 0x0
6053 23:03:21.670095 WL = 0x2
6054 23:03:21.673579 RL = 0x2
6055 23:03:21.673657 BL = 0x2
6056 23:03:21.677291 RPST = 0x0
6057 23:03:21.677369 RD_PRE = 0x0
6058 23:03:21.680576 WR_PRE = 0x1
6059 23:03:21.680695 WR_PST = 0x0
6060 23:03:21.683631 DBI_WR = 0x0
6061 23:03:21.683731 DBI_RD = 0x0
6062 23:03:21.686901 OTF = 0x1
6063 23:03:21.690157 ===================================
6064 23:03:21.693296 ===================================
6065 23:03:21.693442 ANA top config
6066 23:03:21.696827 ===================================
6067 23:03:21.699840 DLL_ASYNC_EN = 0
6068 23:03:21.703252 ALL_SLAVE_EN = 1
6069 23:03:21.706590 NEW_RANK_MODE = 1
6070 23:03:21.706692 DLL_IDLE_MODE = 1
6071 23:03:21.710016 LP45_APHY_COMB_EN = 1
6072 23:03:21.713534 TX_ODT_DIS = 1
6073 23:03:21.716565 NEW_8X_MODE = 1
6074 23:03:21.719704 ===================================
6075 23:03:21.723490 ===================================
6076 23:03:21.726668 data_rate = 800
6077 23:03:21.729677 CKR = 1
6078 23:03:21.729776 DQ_P2S_RATIO = 4
6079 23:03:21.732875 ===================================
6080 23:03:21.736376 CA_P2S_RATIO = 4
6081 23:03:21.739917 DQ_CA_OPEN = 0
6082 23:03:21.743172 DQ_SEMI_OPEN = 1
6083 23:03:21.746510 CA_SEMI_OPEN = 1
6084 23:03:21.750052 CA_FULL_RATE = 0
6085 23:03:21.750133 DQ_CKDIV4_EN = 0
6086 23:03:21.752590 CA_CKDIV4_EN = 1
6087 23:03:21.756253 CA_PREDIV_EN = 0
6088 23:03:21.759570 PH8_DLY = 0
6089 23:03:21.762615 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6090 23:03:21.766278 DQ_AAMCK_DIV = 0
6091 23:03:21.766374 CA_AAMCK_DIV = 0
6092 23:03:21.768912 CA_ADMCK_DIV = 4
6093 23:03:21.772345 DQ_TRACK_CA_EN = 0
6094 23:03:21.775856 CA_PICK = 800
6095 23:03:21.778837 CA_MCKIO = 400
6096 23:03:21.782355 MCKIO_SEMI = 400
6097 23:03:21.785553 PLL_FREQ = 3016
6098 23:03:21.788895 DQ_UI_PI_RATIO = 32
6099 23:03:21.788976 CA_UI_PI_RATIO = 32
6100 23:03:21.792391 ===================================
6101 23:03:21.795604 ===================================
6102 23:03:21.798659 memory_type:LPDDR4
6103 23:03:21.802147 GP_NUM : 10
6104 23:03:21.802276 SRAM_EN : 1
6105 23:03:21.805435 MD32_EN : 0
6106 23:03:21.808833 ===================================
6107 23:03:21.811776 [ANA_INIT] >>>>>>>>>>>>>>
6108 23:03:21.815463 <<<<<< [CONFIGURE PHASE]: ANA_TX
6109 23:03:21.818239 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6110 23:03:21.821522 ===================================
6111 23:03:21.825013 data_rate = 800,PCW = 0X7400
6112 23:03:21.828448 ===================================
6113 23:03:21.831651 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6114 23:03:21.834762 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6115 23:03:21.847772 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6116 23:03:21.851367 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6117 23:03:21.855092 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6118 23:03:21.857919 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6119 23:03:21.861438 [ANA_INIT] flow start
6120 23:03:21.861529 [ANA_INIT] PLL >>>>>>>>
6121 23:03:21.864476 [ANA_INIT] PLL <<<<<<<<
6122 23:03:21.867788 [ANA_INIT] MIDPI >>>>>>>>
6123 23:03:21.871349 [ANA_INIT] MIDPI <<<<<<<<
6124 23:03:21.871448 [ANA_INIT] DLL >>>>>>>>
6125 23:03:21.874416 [ANA_INIT] flow end
6126 23:03:21.878326 ============ LP4 DIFF to SE enter ============
6127 23:03:21.881038 ============ LP4 DIFF to SE exit ============
6128 23:03:21.884244 [ANA_INIT] <<<<<<<<<<<<<
6129 23:03:21.887926 [Flow] Enable top DCM control >>>>>
6130 23:03:21.891066 [Flow] Enable top DCM control <<<<<
6131 23:03:21.894818 Enable DLL master slave shuffle
6132 23:03:21.900732 ==============================================================
6133 23:03:21.900836 Gating Mode config
6134 23:03:21.907361 ==============================================================
6135 23:03:21.907445 Config description:
6136 23:03:21.917071 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6137 23:03:21.923811 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6138 23:03:21.930473 SELPH_MODE 0: By rank 1: By Phase
6139 23:03:21.936653 ==============================================================
6140 23:03:21.936735 GAT_TRACK_EN = 0
6141 23:03:21.940150 RX_GATING_MODE = 2
6142 23:03:21.943482 RX_GATING_TRACK_MODE = 2
6143 23:03:21.946732 SELPH_MODE = 1
6144 23:03:21.950066 PICG_EARLY_EN = 1
6145 23:03:21.953632 VALID_LAT_VALUE = 1
6146 23:03:21.959662 ==============================================================
6147 23:03:21.963036 Enter into Gating configuration >>>>
6148 23:03:21.966633 Exit from Gating configuration <<<<
6149 23:03:21.970096 Enter into DVFS_PRE_config >>>>>
6150 23:03:21.979834 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6151 23:03:21.982853 Exit from DVFS_PRE_config <<<<<
6152 23:03:21.986118 Enter into PICG configuration >>>>
6153 23:03:21.989721 Exit from PICG configuration <<<<
6154 23:03:21.992686 [RX_INPUT] configuration >>>>>
6155 23:03:21.996187 [RX_INPUT] configuration <<<<<
6156 23:03:21.999346 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6157 23:03:22.006081 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6158 23:03:22.012811 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6159 23:03:22.019228 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6160 23:03:22.022581 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6161 23:03:22.028948 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6162 23:03:22.035506 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6163 23:03:22.038664 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6164 23:03:22.042072 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6165 23:03:22.045769 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6166 23:03:22.052344 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6167 23:03:22.055422 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6168 23:03:22.058461 ===================================
6169 23:03:22.061682 LPDDR4 DRAM CONFIGURATION
6170 23:03:22.064762 ===================================
6171 23:03:22.064837 EX_ROW_EN[0] = 0x0
6172 23:03:22.068596 EX_ROW_EN[1] = 0x0
6173 23:03:22.068670 LP4Y_EN = 0x0
6174 23:03:22.071945 WORK_FSP = 0x0
6175 23:03:22.072032 WL = 0x2
6176 23:03:22.074939 RL = 0x2
6177 23:03:22.075008 BL = 0x2
6178 23:03:22.078262 RPST = 0x0
6179 23:03:22.082014 RD_PRE = 0x0
6180 23:03:22.082119 WR_PRE = 0x1
6181 23:03:22.085242 WR_PST = 0x0
6182 23:03:22.085340 DBI_WR = 0x0
6183 23:03:22.088081 DBI_RD = 0x0
6184 23:03:22.088189 OTF = 0x1
6185 23:03:22.091737 ===================================
6186 23:03:22.094523 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6187 23:03:22.101466 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6188 23:03:22.104621 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6189 23:03:22.108070 ===================================
6190 23:03:22.111319 LPDDR4 DRAM CONFIGURATION
6191 23:03:22.114577 ===================================
6192 23:03:22.114665 EX_ROW_EN[0] = 0x10
6193 23:03:22.117729 EX_ROW_EN[1] = 0x0
6194 23:03:22.117813 LP4Y_EN = 0x0
6195 23:03:22.120776 WORK_FSP = 0x0
6196 23:03:22.124520 WL = 0x2
6197 23:03:22.124625 RL = 0x2
6198 23:03:22.127578 BL = 0x2
6199 23:03:22.127657 RPST = 0x0
6200 23:03:22.130819 RD_PRE = 0x0
6201 23:03:22.130893 WR_PRE = 0x1
6202 23:03:22.134196 WR_PST = 0x0
6203 23:03:22.134317 DBI_WR = 0x0
6204 23:03:22.137582 DBI_RD = 0x0
6205 23:03:22.137676 OTF = 0x1
6206 23:03:22.141044 ===================================
6207 23:03:22.147330 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6208 23:03:22.151433 nWR fixed to 30
6209 23:03:22.154545 [ModeRegInit_LP4] CH0 RK0
6210 23:03:22.154622 [ModeRegInit_LP4] CH0 RK1
6211 23:03:22.158129 [ModeRegInit_LP4] CH1 RK0
6212 23:03:22.161296 [ModeRegInit_LP4] CH1 RK1
6213 23:03:22.161367 match AC timing 19
6214 23:03:22.168117 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6215 23:03:22.170892 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6216 23:03:22.174047 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6217 23:03:22.180760 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6218 23:03:22.184050 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6219 23:03:22.184125 ==
6220 23:03:22.188027 Dram Type= 6, Freq= 0, CH_0, rank 0
6221 23:03:22.190583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6222 23:03:22.193910 ==
6223 23:03:22.197375 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6224 23:03:22.203735 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6225 23:03:22.207378 [CA 0] Center 36 (8~64) winsize 57
6226 23:03:22.210712 [CA 1] Center 36 (8~64) winsize 57
6227 23:03:22.213567 [CA 2] Center 36 (8~64) winsize 57
6228 23:03:22.217134 [CA 3] Center 36 (8~64) winsize 57
6229 23:03:22.220487 [CA 4] Center 36 (8~64) winsize 57
6230 23:03:22.223860 [CA 5] Center 36 (8~64) winsize 57
6231 23:03:22.223941
6232 23:03:22.226769 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6233 23:03:22.226851
6234 23:03:22.230169 [CATrainingPosCal] consider 1 rank data
6235 23:03:22.233670 u2DelayCellTimex100 = 270/100 ps
6236 23:03:22.236821 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6237 23:03:22.240080 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6238 23:03:22.243614 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6239 23:03:22.246756 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6240 23:03:22.249967 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6241 23:03:22.253151 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6242 23:03:22.253230
6243 23:03:22.259844 CA PerBit enable=1, Macro0, CA PI delay=36
6244 23:03:22.259923
6245 23:03:22.263062 [CBTSetCACLKResult] CA Dly = 36
6246 23:03:22.263135 CS Dly: 1 (0~32)
6247 23:03:22.263197 ==
6248 23:03:22.266230 Dram Type= 6, Freq= 0, CH_0, rank 1
6249 23:03:22.269572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6250 23:03:22.269649 ==
6251 23:03:22.276298 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6252 23:03:22.282511 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6253 23:03:22.286179 [CA 0] Center 36 (8~64) winsize 57
6254 23:03:22.289802 [CA 1] Center 36 (8~64) winsize 57
6255 23:03:22.292650 [CA 2] Center 36 (8~64) winsize 57
6256 23:03:22.296082 [CA 3] Center 36 (8~64) winsize 57
6257 23:03:22.299833 [CA 4] Center 36 (8~64) winsize 57
6258 23:03:22.299914 [CA 5] Center 36 (8~64) winsize 57
6259 23:03:22.302513
6260 23:03:22.306104 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6261 23:03:22.306182
6262 23:03:22.309199 [CATrainingPosCal] consider 2 rank data
6263 23:03:22.312994 u2DelayCellTimex100 = 270/100 ps
6264 23:03:22.316210 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6265 23:03:22.319164 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6266 23:03:22.322953 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6267 23:03:22.325768 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6268 23:03:22.329131 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6269 23:03:22.332514 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6270 23:03:22.332590
6271 23:03:22.336179 CA PerBit enable=1, Macro0, CA PI delay=36
6272 23:03:22.339038
6273 23:03:22.339106 [CBTSetCACLKResult] CA Dly = 36
6274 23:03:22.342360 CS Dly: 1 (0~32)
6275 23:03:22.342441
6276 23:03:22.345444 ----->DramcWriteLeveling(PI) begin...
6277 23:03:22.345526 ==
6278 23:03:22.348879 Dram Type= 6, Freq= 0, CH_0, rank 0
6279 23:03:22.352234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6280 23:03:22.352316 ==
6281 23:03:22.355345 Write leveling (Byte 0): 40 => 8
6282 23:03:22.358824 Write leveling (Byte 1): 40 => 8
6283 23:03:22.362233 DramcWriteLeveling(PI) end<-----
6284 23:03:22.362336
6285 23:03:22.362400 ==
6286 23:03:22.364918 Dram Type= 6, Freq= 0, CH_0, rank 0
6287 23:03:22.368285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6288 23:03:22.371855 ==
6289 23:03:22.371930 [Gating] SW mode calibration
6290 23:03:22.381954 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6291 23:03:22.384760 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6292 23:03:22.387906 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6293 23:03:22.394592 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6294 23:03:22.398034 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6295 23:03:22.401486 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6296 23:03:22.407891 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6297 23:03:22.411224 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6298 23:03:22.414150 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6299 23:03:22.420736 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6300 23:03:22.424109 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6301 23:03:22.427549 Total UI for P1: 0, mck2ui 16
6302 23:03:22.430684 best dqsien dly found for B0: ( 0, 14, 24)
6303 23:03:22.433933 Total UI for P1: 0, mck2ui 16
6304 23:03:22.437621 best dqsien dly found for B1: ( 0, 14, 24)
6305 23:03:22.441094 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6306 23:03:22.444427 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6307 23:03:22.444500
6308 23:03:22.447551 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6309 23:03:22.454218 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6310 23:03:22.454376 [Gating] SW calibration Done
6311 23:03:22.457295 ==
6312 23:03:22.457376 Dram Type= 6, Freq= 0, CH_0, rank 0
6313 23:03:22.464405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6314 23:03:22.464559 ==
6315 23:03:22.464663 RX Vref Scan: 0
6316 23:03:22.464724
6317 23:03:22.467070 RX Vref 0 -> 0, step: 1
6318 23:03:22.467143
6319 23:03:22.470248 RX Delay -410 -> 252, step: 16
6320 23:03:22.473532 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6321 23:03:22.477192 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6322 23:03:22.483815 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6323 23:03:22.486644 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6324 23:03:22.490212 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6325 23:03:22.496942 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6326 23:03:22.500504 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6327 23:03:22.503415 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6328 23:03:22.506737 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6329 23:03:22.513271 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6330 23:03:22.516165 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6331 23:03:22.519545 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6332 23:03:22.523167 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6333 23:03:22.529332 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6334 23:03:22.532853 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6335 23:03:22.535909 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6336 23:03:22.535992 ==
6337 23:03:22.539554 Dram Type= 6, Freq= 0, CH_0, rank 0
6338 23:03:22.545719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6339 23:03:22.545802 ==
6340 23:03:22.545867 DQS Delay:
6341 23:03:22.549303 DQS0 = 35, DQS1 = 51
6342 23:03:22.549385 DQM Delay:
6343 23:03:22.549451 DQM0 = 5, DQM1 = 11
6344 23:03:22.552837 DQ Delay:
6345 23:03:22.556090 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6346 23:03:22.556172 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6347 23:03:22.559572 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6348 23:03:22.562805 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6349 23:03:22.562886
6350 23:03:22.566194
6351 23:03:22.566283 ==
6352 23:03:22.569088 Dram Type= 6, Freq= 0, CH_0, rank 0
6353 23:03:22.572662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6354 23:03:22.572745 ==
6355 23:03:22.572810
6356 23:03:22.572869
6357 23:03:22.575610 TX Vref Scan disable
6358 23:03:22.575692 == TX Byte 0 ==
6359 23:03:22.578921 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6360 23:03:22.585671 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6361 23:03:22.585752 == TX Byte 1 ==
6362 23:03:22.589084 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6363 23:03:22.595241 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6364 23:03:22.595321 ==
6365 23:03:22.598737 Dram Type= 6, Freq= 0, CH_0, rank 0
6366 23:03:22.601784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6367 23:03:22.601865 ==
6368 23:03:22.601929
6369 23:03:22.601987
6370 23:03:22.605393 TX Vref Scan disable
6371 23:03:22.605473 == TX Byte 0 ==
6372 23:03:22.611655 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6373 23:03:22.614865 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6374 23:03:22.614947 == TX Byte 1 ==
6375 23:03:22.621529 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6376 23:03:22.624997 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6377 23:03:22.625077
6378 23:03:22.625141 [DATLAT]
6379 23:03:22.628338 Freq=400, CH0 RK0
6380 23:03:22.628418
6381 23:03:22.628481 DATLAT Default: 0xf
6382 23:03:22.631349 0, 0xFFFF, sum = 0
6383 23:03:22.631431 1, 0xFFFF, sum = 0
6384 23:03:22.634633 2, 0xFFFF, sum = 0
6385 23:03:22.634737 3, 0xFFFF, sum = 0
6386 23:03:22.638122 4, 0xFFFF, sum = 0
6387 23:03:22.638204 5, 0xFFFF, sum = 0
6388 23:03:22.641209 6, 0xFFFF, sum = 0
6389 23:03:22.641290 7, 0xFFFF, sum = 0
6390 23:03:22.644774 8, 0xFFFF, sum = 0
6391 23:03:22.647810 9, 0xFFFF, sum = 0
6392 23:03:22.647891 10, 0xFFFF, sum = 0
6393 23:03:22.651239 11, 0xFFFF, sum = 0
6394 23:03:22.651320 12, 0xFFFF, sum = 0
6395 23:03:22.654180 13, 0x0, sum = 1
6396 23:03:22.654284 14, 0x0, sum = 2
6397 23:03:22.657992 15, 0x0, sum = 3
6398 23:03:22.658073 16, 0x0, sum = 4
6399 23:03:22.658138 best_step = 14
6400 23:03:22.660774
6401 23:03:22.660854 ==
6402 23:03:22.664385 Dram Type= 6, Freq= 0, CH_0, rank 0
6403 23:03:22.667771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6404 23:03:22.667854 ==
6405 23:03:22.667919 RX Vref Scan: 1
6406 23:03:22.667979
6407 23:03:22.671326 RX Vref 0 -> 0, step: 1
6408 23:03:22.671407
6409 23:03:22.674537 RX Delay -343 -> 252, step: 8
6410 23:03:22.674617
6411 23:03:22.677299 Set Vref, RX VrefLevel [Byte0]: 52
6412 23:03:22.681043 [Byte1]: 59
6413 23:03:22.684693
6414 23:03:22.684814 Final RX Vref Byte 0 = 52 to rank0
6415 23:03:22.687865 Final RX Vref Byte 1 = 59 to rank0
6416 23:03:22.691607 Final RX Vref Byte 0 = 52 to rank1
6417 23:03:22.694470 Final RX Vref Byte 1 = 59 to rank1==
6418 23:03:22.697589 Dram Type= 6, Freq= 0, CH_0, rank 0
6419 23:03:22.704416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6420 23:03:22.704498 ==
6421 23:03:22.704562 DQS Delay:
6422 23:03:22.707945 DQS0 = 40, DQS1 = 60
6423 23:03:22.708027 DQM Delay:
6424 23:03:22.708109 DQM0 = 6, DQM1 = 16
6425 23:03:22.711409 DQ Delay:
6426 23:03:22.714500 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6427 23:03:22.714579 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =12
6428 23:03:22.717755 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =12
6429 23:03:22.721090 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6430 23:03:22.721172
6431 23:03:22.724361
6432 23:03:22.731286 [DQSOSCAuto] RK0, (LSB)MR18= 0x8e83, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
6433 23:03:22.734489 CH0 RK0: MR19=C0C, MR18=8E83
6434 23:03:22.740877 CH0_RK0: MR19=0xC0C, MR18=0x8E83, DQSOSC=392, MR23=63, INC=384, DEC=256
6435 23:03:22.741001 ==
6436 23:03:22.743980 Dram Type= 6, Freq= 0, CH_0, rank 1
6437 23:03:22.747268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6438 23:03:22.747355 ==
6439 23:03:22.750660 [Gating] SW mode calibration
6440 23:03:22.757103 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6441 23:03:22.763949 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6442 23:03:22.766938 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6443 23:03:22.770437 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6444 23:03:22.776783 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6445 23:03:22.780223 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6446 23:03:22.783409 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6447 23:03:22.789971 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6448 23:03:22.793275 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6449 23:03:22.796675 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6450 23:03:22.803038 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6451 23:03:22.806474 Total UI for P1: 0, mck2ui 16
6452 23:03:22.809702 best dqsien dly found for B0: ( 0, 14, 24)
6453 23:03:22.809784 Total UI for P1: 0, mck2ui 16
6454 23:03:22.816277 best dqsien dly found for B1: ( 0, 14, 24)
6455 23:03:22.819687 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6456 23:03:22.823145 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6457 23:03:22.823228
6458 23:03:22.826036 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6459 23:03:22.829336 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6460 23:03:22.833078 [Gating] SW calibration Done
6461 23:03:22.833164 ==
6462 23:03:22.836124 Dram Type= 6, Freq= 0, CH_0, rank 1
6463 23:03:22.839506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6464 23:03:22.839591 ==
6465 23:03:22.842922 RX Vref Scan: 0
6466 23:03:22.843007
6467 23:03:22.845565 RX Vref 0 -> 0, step: 1
6468 23:03:22.845649
6469 23:03:22.845734 RX Delay -410 -> 252, step: 16
6470 23:03:22.853039 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6471 23:03:22.856035 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6472 23:03:22.859131 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6473 23:03:22.865738 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6474 23:03:22.868871 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6475 23:03:22.872548 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6476 23:03:22.875678 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6477 23:03:22.882350 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6478 23:03:22.885892 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6479 23:03:22.888601 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6480 23:03:22.892081 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6481 23:03:22.898615 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6482 23:03:22.901985 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6483 23:03:22.905526 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6484 23:03:22.908407 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6485 23:03:22.915577 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6486 23:03:22.915659 ==
6487 23:03:22.918413 Dram Type= 6, Freq= 0, CH_0, rank 1
6488 23:03:22.921891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6489 23:03:22.921973 ==
6490 23:03:22.922039 DQS Delay:
6491 23:03:22.924873 DQS0 = 35, DQS1 = 59
6492 23:03:22.924955 DQM Delay:
6493 23:03:22.928422 DQM0 = 5, DQM1 = 16
6494 23:03:22.928530 DQ Delay:
6495 23:03:22.931722 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6496 23:03:22.935274 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6497 23:03:22.938406 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6498 23:03:22.941548 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6499 23:03:22.941629
6500 23:03:22.941694
6501 23:03:22.941753 ==
6502 23:03:22.944847 Dram Type= 6, Freq= 0, CH_0, rank 1
6503 23:03:22.948211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6504 23:03:22.948320 ==
6505 23:03:22.951387
6506 23:03:22.951469
6507 23:03:22.951534 TX Vref Scan disable
6508 23:03:22.954622 == TX Byte 0 ==
6509 23:03:22.958290 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6510 23:03:22.961118 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6511 23:03:22.964659 == TX Byte 1 ==
6512 23:03:22.967948 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6513 23:03:22.971223 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6514 23:03:22.971305 ==
6515 23:03:22.974734 Dram Type= 6, Freq= 0, CH_0, rank 1
6516 23:03:22.977620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6517 23:03:22.981290 ==
6518 23:03:22.981371
6519 23:03:22.981436
6520 23:03:22.981496 TX Vref Scan disable
6521 23:03:22.984368 == TX Byte 0 ==
6522 23:03:22.987756 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6523 23:03:22.991112 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6524 23:03:22.994056 == TX Byte 1 ==
6525 23:03:22.997543 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6526 23:03:23.000883 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6527 23:03:23.000965
6528 23:03:23.004330 [DATLAT]
6529 23:03:23.004411 Freq=400, CH0 RK1
6530 23:03:23.004477
6531 23:03:23.007324 DATLAT Default: 0xe
6532 23:03:23.007408 0, 0xFFFF, sum = 0
6533 23:03:23.010641 1, 0xFFFF, sum = 0
6534 23:03:23.010725 2, 0xFFFF, sum = 0
6535 23:03:23.013982 3, 0xFFFF, sum = 0
6536 23:03:23.014064 4, 0xFFFF, sum = 0
6537 23:03:23.017071 5, 0xFFFF, sum = 0
6538 23:03:23.017158 6, 0xFFFF, sum = 0
6539 23:03:23.020675 7, 0xFFFF, sum = 0
6540 23:03:23.020760 8, 0xFFFF, sum = 0
6541 23:03:23.024143 9, 0xFFFF, sum = 0
6542 23:03:23.024229 10, 0xFFFF, sum = 0
6543 23:03:23.026927 11, 0xFFFF, sum = 0
6544 23:03:23.030323 12, 0xFFFF, sum = 0
6545 23:03:23.030410 13, 0x0, sum = 1
6546 23:03:23.030497 14, 0x0, sum = 2
6547 23:03:23.033597 15, 0x0, sum = 3
6548 23:03:23.033682 16, 0x0, sum = 4
6549 23:03:23.037319 best_step = 14
6550 23:03:23.037403
6551 23:03:23.037489 ==
6552 23:03:23.040410 Dram Type= 6, Freq= 0, CH_0, rank 1
6553 23:03:23.043920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6554 23:03:23.044005 ==
6555 23:03:23.046875 RX Vref Scan: 0
6556 23:03:23.046960
6557 23:03:23.047046 RX Vref 0 -> 0, step: 1
6558 23:03:23.050466
6559 23:03:23.050550 RX Delay -359 -> 252, step: 8
6560 23:03:23.058504 iDelay=209, Bit 0, Center -36 (-271 ~ 200) 472
6561 23:03:23.062113 iDelay=209, Bit 1, Center -32 (-271 ~ 208) 480
6562 23:03:23.065105 iDelay=209, Bit 2, Center -36 (-271 ~ 200) 472
6563 23:03:23.071454 iDelay=209, Bit 3, Center -36 (-271 ~ 200) 472
6564 23:03:23.075161 iDelay=209, Bit 4, Center -32 (-271 ~ 208) 480
6565 23:03:23.078623 iDelay=209, Bit 5, Center -44 (-279 ~ 192) 472
6566 23:03:23.081431 iDelay=209, Bit 6, Center -28 (-263 ~ 208) 472
6567 23:03:23.088240 iDelay=209, Bit 7, Center -28 (-263 ~ 208) 472
6568 23:03:23.091317 iDelay=209, Bit 8, Center -52 (-295 ~ 192) 488
6569 23:03:23.095353 iDelay=209, Bit 9, Center -60 (-303 ~ 184) 488
6570 23:03:23.098098 iDelay=209, Bit 10, Center -44 (-287 ~ 200) 488
6571 23:03:23.104893 iDelay=209, Bit 11, Center -52 (-295 ~ 192) 488
6572 23:03:23.107745 iDelay=209, Bit 12, Center -36 (-279 ~ 208) 488
6573 23:03:23.111235 iDelay=209, Bit 13, Center -36 (-279 ~ 208) 488
6574 23:03:23.114480 iDelay=209, Bit 14, Center -36 (-279 ~ 208) 488
6575 23:03:23.121244 iDelay=209, Bit 15, Center -36 (-279 ~ 208) 488
6576 23:03:23.121330 ==
6577 23:03:23.124643 Dram Type= 6, Freq= 0, CH_0, rank 1
6578 23:03:23.128177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6579 23:03:23.128263 ==
6580 23:03:23.128350 DQS Delay:
6581 23:03:23.130981 DQS0 = 44, DQS1 = 60
6582 23:03:23.131095 DQM Delay:
6583 23:03:23.134437 DQM0 = 10, DQM1 = 16
6584 23:03:23.134518 DQ Delay:
6585 23:03:23.137893 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6586 23:03:23.140742 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6587 23:03:23.144375 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6588 23:03:23.147393 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6589 23:03:23.147475
6590 23:03:23.147540
6591 23:03:23.157205 [DQSOSCAuto] RK1, (LSB)MR18= 0x827c, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
6592 23:03:23.157288 CH0 RK1: MR19=C0C, MR18=827C
6593 23:03:23.163769 CH0_RK1: MR19=0xC0C, MR18=0x827C, DQSOSC=393, MR23=63, INC=382, DEC=254
6594 23:03:23.167259 [RxdqsGatingPostProcess] freq 400
6595 23:03:23.173719 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6596 23:03:23.177604 best DQS0 dly(2T, 0.5T) = (0, 10)
6597 23:03:23.180808 best DQS1 dly(2T, 0.5T) = (0, 10)
6598 23:03:23.184055 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6599 23:03:23.186987 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6600 23:03:23.190406 best DQS0 dly(2T, 0.5T) = (0, 10)
6601 23:03:23.193958 best DQS1 dly(2T, 0.5T) = (0, 10)
6602 23:03:23.194043 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6603 23:03:23.197139 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6604 23:03:23.200099 Pre-setting of DQS Precalculation
6605 23:03:23.206688 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6606 23:03:23.206773 ==
6607 23:03:23.210328 Dram Type= 6, Freq= 0, CH_1, rank 0
6608 23:03:23.213640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6609 23:03:23.213726 ==
6610 23:03:23.220066 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6611 23:03:23.226694 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6612 23:03:23.230361 [CA 0] Center 36 (8~64) winsize 57
6613 23:03:23.233265 [CA 1] Center 36 (8~64) winsize 57
6614 23:03:23.236670 [CA 2] Center 36 (8~64) winsize 57
6615 23:03:23.240077 [CA 3] Center 36 (8~64) winsize 57
6616 23:03:23.240163 [CA 4] Center 36 (8~64) winsize 57
6617 23:03:23.242926 [CA 5] Center 36 (8~64) winsize 57
6618 23:03:23.243010
6619 23:03:23.249539 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6620 23:03:23.249638
6621 23:03:23.252810 [CATrainingPosCal] consider 1 rank data
6622 23:03:23.256278 u2DelayCellTimex100 = 270/100 ps
6623 23:03:23.259740 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6624 23:03:23.263113 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6625 23:03:23.266067 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6626 23:03:23.269424 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6627 23:03:23.272881 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6628 23:03:23.275967 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6629 23:03:23.276049
6630 23:03:23.279389 CA PerBit enable=1, Macro0, CA PI delay=36
6631 23:03:23.279505
6632 23:03:23.282301 [CBTSetCACLKResult] CA Dly = 36
6633 23:03:23.285701 CS Dly: 1 (0~32)
6634 23:03:23.285785 ==
6635 23:03:23.289246 Dram Type= 6, Freq= 0, CH_1, rank 1
6636 23:03:23.292379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6637 23:03:23.292461 ==
6638 23:03:23.299266 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6639 23:03:23.305934 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6640 23:03:23.308673 [CA 0] Center 36 (8~64) winsize 57
6641 23:03:23.312571 [CA 1] Center 36 (8~64) winsize 57
6642 23:03:23.315439 [CA 2] Center 36 (8~64) winsize 57
6643 23:03:23.315548 [CA 3] Center 36 (8~64) winsize 57
6644 23:03:23.318869 [CA 4] Center 36 (8~64) winsize 57
6645 23:03:23.322377 [CA 5] Center 36 (8~64) winsize 57
6646 23:03:23.322460
6647 23:03:23.328883 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6648 23:03:23.328965
6649 23:03:23.331721 [CATrainingPosCal] consider 2 rank data
6650 23:03:23.335129 u2DelayCellTimex100 = 270/100 ps
6651 23:03:23.338304 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6652 23:03:23.341735 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6653 23:03:23.345066 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6654 23:03:23.348349 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6655 23:03:23.351884 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6656 23:03:23.355008 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6657 23:03:23.355116
6658 23:03:23.358112 CA PerBit enable=1, Macro0, CA PI delay=36
6659 23:03:23.358193
6660 23:03:23.361679 [CBTSetCACLKResult] CA Dly = 36
6661 23:03:23.365137 CS Dly: 1 (0~32)
6662 23:03:23.365218
6663 23:03:23.368146 ----->DramcWriteLeveling(PI) begin...
6664 23:03:23.368229 ==
6665 23:03:23.371652 Dram Type= 6, Freq= 0, CH_1, rank 0
6666 23:03:23.375042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6667 23:03:23.375124 ==
6668 23:03:23.378277 Write leveling (Byte 0): 40 => 8
6669 23:03:23.381429 Write leveling (Byte 1): 40 => 8
6670 23:03:23.384664 DramcWriteLeveling(PI) end<-----
6671 23:03:23.384746
6672 23:03:23.384811 ==
6673 23:03:23.388037 Dram Type= 6, Freq= 0, CH_1, rank 0
6674 23:03:23.391368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6675 23:03:23.391451 ==
6676 23:03:23.394233 [Gating] SW mode calibration
6677 23:03:23.400837 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6678 23:03:23.407524 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6679 23:03:23.410771 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6680 23:03:23.417526 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6681 23:03:23.420853 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6682 23:03:23.424238 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6683 23:03:23.430666 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6684 23:03:23.434092 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6685 23:03:23.437692 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6686 23:03:23.444084 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6687 23:03:23.447277 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6688 23:03:23.450198 Total UI for P1: 0, mck2ui 16
6689 23:03:23.453754 best dqsien dly found for B0: ( 0, 14, 24)
6690 23:03:23.457240 Total UI for P1: 0, mck2ui 16
6691 23:03:23.460250 best dqsien dly found for B1: ( 0, 14, 24)
6692 23:03:23.463359 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6693 23:03:23.467355 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6694 23:03:23.467437
6695 23:03:23.470039 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6696 23:03:23.473407 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6697 23:03:23.476869 [Gating] SW calibration Done
6698 23:03:23.476949 ==
6699 23:03:23.479784 Dram Type= 6, Freq= 0, CH_1, rank 0
6700 23:03:23.486739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6701 23:03:23.486821 ==
6702 23:03:23.486886 RX Vref Scan: 0
6703 23:03:23.486946
6704 23:03:23.490064 RX Vref 0 -> 0, step: 1
6705 23:03:23.490172
6706 23:03:23.493644 RX Delay -410 -> 252, step: 16
6707 23:03:23.496649 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6708 23:03:23.499703 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6709 23:03:23.506406 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6710 23:03:23.509928 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6711 23:03:23.512794 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6712 23:03:23.516224 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6713 23:03:23.522886 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6714 23:03:23.526106 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6715 23:03:23.529855 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6716 23:03:23.532530 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6717 23:03:23.538973 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6718 23:03:23.542653 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6719 23:03:23.545703 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6720 23:03:23.552532 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6721 23:03:23.555689 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6722 23:03:23.558520 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6723 23:03:23.558602 ==
6724 23:03:23.562148 Dram Type= 6, Freq= 0, CH_1, rank 0
6725 23:03:23.565693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6726 23:03:23.568501 ==
6727 23:03:23.568583 DQS Delay:
6728 23:03:23.568648 DQS0 = 35, DQS1 = 51
6729 23:03:23.571789 DQM Delay:
6730 23:03:23.571870 DQM0 = 6, DQM1 = 13
6731 23:03:23.575154 DQ Delay:
6732 23:03:23.575236 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6733 23:03:23.578521 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6734 23:03:23.581475 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6735 23:03:23.585327 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16
6736 23:03:23.585413
6737 23:03:23.585501
6738 23:03:23.588469 ==
6739 23:03:23.591841 Dram Type= 6, Freq= 0, CH_1, rank 0
6740 23:03:23.595133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6741 23:03:23.595215 ==
6742 23:03:23.595280
6743 23:03:23.595356
6744 23:03:23.598057 TX Vref Scan disable
6745 23:03:23.598141 == TX Byte 0 ==
6746 23:03:23.601486 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6747 23:03:23.608165 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6748 23:03:23.608251 == TX Byte 1 ==
6749 23:03:23.611386 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6750 23:03:23.618180 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6751 23:03:23.618288 ==
6752 23:03:23.621387 Dram Type= 6, Freq= 0, CH_1, rank 0
6753 23:03:23.624798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6754 23:03:23.624884 ==
6755 23:03:23.624971
6756 23:03:23.625051
6757 23:03:23.628147 TX Vref Scan disable
6758 23:03:23.628231 == TX Byte 0 ==
6759 23:03:23.631108 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6760 23:03:23.637834 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6761 23:03:23.637920 == TX Byte 1 ==
6762 23:03:23.641151 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6763 23:03:23.647971 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6764 23:03:23.648054
6765 23:03:23.648157 [DATLAT]
6766 23:03:23.650572 Freq=400, CH1 RK0
6767 23:03:23.650654
6768 23:03:23.650719 DATLAT Default: 0xf
6769 23:03:23.654030 0, 0xFFFF, sum = 0
6770 23:03:23.654113 1, 0xFFFF, sum = 0
6771 23:03:23.657509 2, 0xFFFF, sum = 0
6772 23:03:23.657592 3, 0xFFFF, sum = 0
6773 23:03:23.660306 4, 0xFFFF, sum = 0
6774 23:03:23.660393 5, 0xFFFF, sum = 0
6775 23:03:23.664205 6, 0xFFFF, sum = 0
6776 23:03:23.664320 7, 0xFFFF, sum = 0
6777 23:03:23.667213 8, 0xFFFF, sum = 0
6778 23:03:23.667295 9, 0xFFFF, sum = 0
6779 23:03:23.670669 10, 0xFFFF, sum = 0
6780 23:03:23.670752 11, 0xFFFF, sum = 0
6781 23:03:23.673511 12, 0xFFFF, sum = 0
6782 23:03:23.673594 13, 0x0, sum = 1
6783 23:03:23.676920 14, 0x0, sum = 2
6784 23:03:23.677003 15, 0x0, sum = 3
6785 23:03:23.680342 16, 0x0, sum = 4
6786 23:03:23.680425 best_step = 14
6787 23:03:23.680490
6788 23:03:23.680550 ==
6789 23:03:23.683304 Dram Type= 6, Freq= 0, CH_1, rank 0
6790 23:03:23.690245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6791 23:03:23.690349 ==
6792 23:03:23.690415 RX Vref Scan: 1
6793 23:03:23.690475
6794 23:03:23.693766 RX Vref 0 -> 0, step: 1
6795 23:03:23.693846
6796 23:03:23.697169 RX Delay -343 -> 252, step: 8
6797 23:03:23.697251
6798 23:03:23.700647 Set Vref, RX VrefLevel [Byte0]: 51
6799 23:03:23.703835 [Byte1]: 52
6800 23:03:23.707223
6801 23:03:23.707305 Final RX Vref Byte 0 = 51 to rank0
6802 23:03:23.710059 Final RX Vref Byte 1 = 52 to rank0
6803 23:03:23.713775 Final RX Vref Byte 0 = 51 to rank1
6804 23:03:23.717157 Final RX Vref Byte 1 = 52 to rank1==
6805 23:03:23.719871 Dram Type= 6, Freq= 0, CH_1, rank 0
6806 23:03:23.726928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6807 23:03:23.727011 ==
6808 23:03:23.727076 DQS Delay:
6809 23:03:23.729760 DQS0 = 44, DQS1 = 52
6810 23:03:23.729842 DQM Delay:
6811 23:03:23.729907 DQM0 = 11, DQM1 = 10
6812 23:03:23.733157 DQ Delay:
6813 23:03:23.736851 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =12
6814 23:03:23.739918 DQ4 =8, DQ5 =20, DQ6 =24, DQ7 =4
6815 23:03:23.740003 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6816 23:03:23.746612 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =16
6817 23:03:23.746696
6818 23:03:23.746783
6819 23:03:23.753008 [DQSOSCAuto] RK0, (LSB)MR18= 0x6c93, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 396 ps
6820 23:03:23.756073 CH1 RK0: MR19=C0C, MR18=6C93
6821 23:03:23.762801 CH1_RK0: MR19=0xC0C, MR18=0x6C93, DQSOSC=391, MR23=63, INC=386, DEC=257
6822 23:03:23.762883 ==
6823 23:03:23.766362 Dram Type= 6, Freq= 0, CH_1, rank 1
6824 23:03:23.769388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6825 23:03:23.769463 ==
6826 23:03:23.772504 [Gating] SW mode calibration
6827 23:03:23.779136 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6828 23:03:23.785831 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6829 23:03:23.789330 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6830 23:03:23.792553 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6831 23:03:23.798832 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6832 23:03:23.802135 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6833 23:03:23.805517 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6834 23:03:23.812574 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6835 23:03:23.815905 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6836 23:03:23.818998 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6837 23:03:23.825511 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6838 23:03:23.825590 Total UI for P1: 0, mck2ui 16
6839 23:03:23.832130 best dqsien dly found for B0: ( 0, 14, 24)
6840 23:03:23.832205 Total UI for P1: 0, mck2ui 16
6841 23:03:23.838721 best dqsien dly found for B1: ( 0, 14, 24)
6842 23:03:23.841914 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6843 23:03:23.845607 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6844 23:03:23.845687
6845 23:03:23.848908 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6846 23:03:23.851644 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6847 23:03:23.854926 [Gating] SW calibration Done
6848 23:03:23.855006 ==
6849 23:03:23.858538 Dram Type= 6, Freq= 0, CH_1, rank 1
6850 23:03:23.861739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6851 23:03:23.861840 ==
6852 23:03:23.865222 RX Vref Scan: 0
6853 23:03:23.865301
6854 23:03:23.868043 RX Vref 0 -> 0, step: 1
6855 23:03:23.868113
6856 23:03:23.868173 RX Delay -410 -> 252, step: 16
6857 23:03:23.874792 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6858 23:03:23.878754 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6859 23:03:23.881358 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6860 23:03:23.888302 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6861 23:03:23.891389 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6862 23:03:23.894463 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6863 23:03:23.898127 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6864 23:03:23.904185 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6865 23:03:23.907865 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6866 23:03:23.911151 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6867 23:03:23.914448 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6868 23:03:23.921088 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6869 23:03:23.924546 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6870 23:03:23.927827 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6871 23:03:23.933897 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6872 23:03:23.937404 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6873 23:03:23.937488 ==
6874 23:03:23.941021 Dram Type= 6, Freq= 0, CH_1, rank 1
6875 23:03:23.943692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6876 23:03:23.943777 ==
6877 23:03:23.947113 DQS Delay:
6878 23:03:23.947197 DQS0 = 43, DQS1 = 51
6879 23:03:23.947284 DQM Delay:
6880 23:03:23.950682 DQM0 = 10, DQM1 = 14
6881 23:03:23.950766 DQ Delay:
6882 23:03:23.954126 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6883 23:03:23.956941 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6884 23:03:23.960660 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6885 23:03:23.963610 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6886 23:03:23.963694
6887 23:03:23.963798
6888 23:03:23.963923 ==
6889 23:03:23.966798 Dram Type= 6, Freq= 0, CH_1, rank 1
6890 23:03:23.970173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6891 23:03:23.973593 ==
6892 23:03:23.973677
6893 23:03:23.973763
6894 23:03:23.973845 TX Vref Scan disable
6895 23:03:23.977096 == TX Byte 0 ==
6896 23:03:23.980172 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6897 23:03:23.983264 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6898 23:03:23.986566 == TX Byte 1 ==
6899 23:03:23.989914 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6900 23:03:23.993482 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6901 23:03:23.993567 ==
6902 23:03:23.996597 Dram Type= 6, Freq= 0, CH_1, rank 1
6903 23:03:24.003424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6904 23:03:24.003509 ==
6905 23:03:24.003596
6906 23:03:24.003677
6907 23:03:24.003756 TX Vref Scan disable
6908 23:03:24.006543 == TX Byte 0 ==
6909 23:03:24.009462 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6910 23:03:24.012959 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6911 23:03:24.016070 == TX Byte 1 ==
6912 23:03:24.019359 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6913 23:03:24.022810 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6914 23:03:24.022895
6915 23:03:24.026412 [DATLAT]
6916 23:03:24.026496 Freq=400, CH1 RK1
6917 23:03:24.026598
6918 23:03:24.029565 DATLAT Default: 0xe
6919 23:03:24.029650 0, 0xFFFF, sum = 0
6920 23:03:24.032987 1, 0xFFFF, sum = 0
6921 23:03:24.033072 2, 0xFFFF, sum = 0
6922 23:03:24.035815 3, 0xFFFF, sum = 0
6923 23:03:24.035901 4, 0xFFFF, sum = 0
6924 23:03:24.039375 5, 0xFFFF, sum = 0
6925 23:03:24.039462 6, 0xFFFF, sum = 0
6926 23:03:24.042798 7, 0xFFFF, sum = 0
6927 23:03:24.042884 8, 0xFFFF, sum = 0
6928 23:03:24.045946 9, 0xFFFF, sum = 0
6929 23:03:24.049397 10, 0xFFFF, sum = 0
6930 23:03:24.049525 11, 0xFFFF, sum = 0
6931 23:03:24.052846 12, 0xFFFF, sum = 0
6932 23:03:24.052955 13, 0x0, sum = 1
6933 23:03:24.055923 14, 0x0, sum = 2
6934 23:03:24.056038 15, 0x0, sum = 3
6935 23:03:24.059050 16, 0x0, sum = 4
6936 23:03:24.059137 best_step = 14
6937 23:03:24.059224
6938 23:03:24.059305 ==
6939 23:03:24.062421 Dram Type= 6, Freq= 0, CH_1, rank 1
6940 23:03:24.066074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6941 23:03:24.066159 ==
6942 23:03:24.069201 RX Vref Scan: 0
6943 23:03:24.069285
6944 23:03:24.072042 RX Vref 0 -> 0, step: 1
6945 23:03:24.072127
6946 23:03:24.072214 RX Delay -343 -> 252, step: 8
6947 23:03:24.081503 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6948 23:03:24.084109 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6949 23:03:24.087775 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6950 23:03:24.094441 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6951 23:03:24.097341 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6952 23:03:24.100907 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6953 23:03:24.104355 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6954 23:03:24.110753 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6955 23:03:24.113661 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6956 23:03:24.117185 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6957 23:03:24.120897 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6958 23:03:24.127298 iDelay=217, Bit 11, Center -48 (-287 ~ 192) 480
6959 23:03:24.130997 iDelay=217, Bit 12, Center -32 (-271 ~ 208) 480
6960 23:03:24.134019 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6961 23:03:24.137156 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6962 23:03:24.143578 iDelay=217, Bit 15, Center -32 (-279 ~ 216) 496
6963 23:03:24.143663 ==
6964 23:03:24.146549 Dram Type= 6, Freq= 0, CH_1, rank 1
6965 23:03:24.149838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6966 23:03:24.149923 ==
6967 23:03:24.153719 DQS Delay:
6968 23:03:24.153803 DQS0 = 48, DQS1 = 52
6969 23:03:24.153890 DQM Delay:
6970 23:03:24.156826 DQM0 = 11, DQM1 = 11
6971 23:03:24.156943 DQ Delay:
6972 23:03:24.160248 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6973 23:03:24.163110 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =8
6974 23:03:24.166537 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6975 23:03:24.169552 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
6976 23:03:24.169637
6977 23:03:24.169722
6978 23:03:24.179401 [DQSOSCAuto] RK1, (LSB)MR18= 0x70a7, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 395 ps
6979 23:03:24.179488 CH1 RK1: MR19=C0C, MR18=70A7
6980 23:03:24.185916 CH1_RK1: MR19=0xC0C, MR18=0x70A7, DQSOSC=389, MR23=63, INC=390, DEC=260
6981 23:03:24.189002 [RxdqsGatingPostProcess] freq 400
6982 23:03:24.195816 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6983 23:03:24.199728 best DQS0 dly(2T, 0.5T) = (0, 10)
6984 23:03:24.202686 best DQS1 dly(2T, 0.5T) = (0, 10)
6985 23:03:24.205936 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6986 23:03:24.209058 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6987 23:03:24.212465 best DQS0 dly(2T, 0.5T) = (0, 10)
6988 23:03:24.215640 best DQS1 dly(2T, 0.5T) = (0, 10)
6989 23:03:24.218824 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6990 23:03:24.222217 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6991 23:03:24.225694 Pre-setting of DQS Precalculation
6992 23:03:24.228594 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6993 23:03:24.235375 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6994 23:03:24.242148 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6995 23:03:24.242267
6996 23:03:24.245858
6997 23:03:24.245941 [Calibration Summary] 800 Mbps
6998 23:03:24.249260 CH 0, Rank 0
6999 23:03:24.249363 SW Impedance : PASS
7000 23:03:24.251989 DUTY Scan : NO K
7001 23:03:24.255081 ZQ Calibration : PASS
7002 23:03:24.255166 Jitter Meter : NO K
7003 23:03:24.258426 CBT Training : PASS
7004 23:03:24.261856 Write leveling : PASS
7005 23:03:24.261940 RX DQS gating : PASS
7006 23:03:24.264994 RX DQ/DQS(RDDQC) : PASS
7007 23:03:24.268693 TX DQ/DQS : PASS
7008 23:03:24.268778 RX DATLAT : PASS
7009 23:03:24.271357 RX DQ/DQS(Engine): PASS
7010 23:03:24.274526 TX OE : NO K
7011 23:03:24.274610 All Pass.
7012 23:03:24.274675
7013 23:03:24.274744 CH 0, Rank 1
7014 23:03:24.277973 SW Impedance : PASS
7015 23:03:24.281584 DUTY Scan : NO K
7016 23:03:24.281659 ZQ Calibration : PASS
7017 23:03:24.284552 Jitter Meter : NO K
7018 23:03:24.287983 CBT Training : PASS
7019 23:03:24.288060 Write leveling : NO K
7020 23:03:24.291118 RX DQS gating : PASS
7021 23:03:24.294592 RX DQ/DQS(RDDQC) : PASS
7022 23:03:24.294664 TX DQ/DQS : PASS
7023 23:03:24.298020 RX DATLAT : PASS
7024 23:03:24.301351 RX DQ/DQS(Engine): PASS
7025 23:03:24.301425 TX OE : NO K
7026 23:03:24.301489 All Pass.
7027 23:03:24.304874
7028 23:03:24.304942 CH 1, Rank 0
7029 23:03:24.307655 SW Impedance : PASS
7030 23:03:24.307753 DUTY Scan : NO K
7031 23:03:24.311119 ZQ Calibration : PASS
7032 23:03:24.311200 Jitter Meter : NO K
7033 23:03:24.314106 CBT Training : PASS
7034 23:03:24.317591 Write leveling : PASS
7035 23:03:24.317676 RX DQS gating : PASS
7036 23:03:24.320976 RX DQ/DQS(RDDQC) : PASS
7037 23:03:24.324388 TX DQ/DQS : PASS
7038 23:03:24.324474 RX DATLAT : PASS
7039 23:03:24.327321 RX DQ/DQS(Engine): PASS
7040 23:03:24.330595 TX OE : NO K
7041 23:03:24.330680 All Pass.
7042 23:03:24.330766
7043 23:03:24.330847 CH 1, Rank 1
7044 23:03:24.333820 SW Impedance : PASS
7045 23:03:24.337256 DUTY Scan : NO K
7046 23:03:24.337340 ZQ Calibration : PASS
7047 23:03:24.340450 Jitter Meter : NO K
7048 23:03:24.344065 CBT Training : PASS
7049 23:03:24.344150 Write leveling : NO K
7050 23:03:24.347269 RX DQS gating : PASS
7051 23:03:24.350732 RX DQ/DQS(RDDQC) : PASS
7052 23:03:24.350817 TX DQ/DQS : PASS
7053 23:03:24.353931 RX DATLAT : PASS
7054 23:03:24.356811 RX DQ/DQS(Engine): PASS
7055 23:03:24.356896 TX OE : NO K
7056 23:03:24.360466 All Pass.
7057 23:03:24.360550
7058 23:03:24.360635 DramC Write-DBI off
7059 23:03:24.364074 PER_BANK_REFRESH: Hybrid Mode
7060 23:03:24.366996 TX_TRACKING: ON
7061 23:03:24.373547 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7062 23:03:24.376708 [FAST_K] Save calibration result to emmc
7063 23:03:24.380234 dramc_set_vcore_voltage set vcore to 725000
7064 23:03:24.383778 Read voltage for 1600, 0
7065 23:03:24.383859 Vio18 = 0
7066 23:03:24.386363 Vcore = 725000
7067 23:03:24.386436 Vdram = 0
7068 23:03:24.386497 Vddq = 0
7069 23:03:24.389853 Vmddr = 0
7070 23:03:24.393309 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7071 23:03:24.400006 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7072 23:03:24.403026 MEM_TYPE=3, freq_sel=13
7073 23:03:24.403121 sv_algorithm_assistance_LP4_3733
7074 23:03:24.409838 ============ PULL DRAM RESETB DOWN ============
7075 23:03:24.412922 ========== PULL DRAM RESETB DOWN end =========
7076 23:03:24.416473 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7077 23:03:24.419764 ===================================
7078 23:03:24.422889 LPDDR4 DRAM CONFIGURATION
7079 23:03:24.426309 ===================================
7080 23:03:24.429514 EX_ROW_EN[0] = 0x0
7081 23:03:24.429599 EX_ROW_EN[1] = 0x0
7082 23:03:24.432507 LP4Y_EN = 0x0
7083 23:03:24.432590 WORK_FSP = 0x1
7084 23:03:24.436029 WL = 0x5
7085 23:03:24.436114 RL = 0x5
7086 23:03:24.438938 BL = 0x2
7087 23:03:24.439022 RPST = 0x0
7088 23:03:24.442654 RD_PRE = 0x0
7089 23:03:24.442739 WR_PRE = 0x1
7090 23:03:24.445801 WR_PST = 0x1
7091 23:03:24.449158 DBI_WR = 0x0
7092 23:03:24.449243 DBI_RD = 0x0
7093 23:03:24.452562 OTF = 0x1
7094 23:03:24.456268 ===================================
7095 23:03:24.458959 ===================================
7096 23:03:24.459044 ANA top config
7097 23:03:24.462513 ===================================
7098 23:03:24.465405 DLL_ASYNC_EN = 0
7099 23:03:24.469040 ALL_SLAVE_EN = 0
7100 23:03:24.469126 NEW_RANK_MODE = 1
7101 23:03:24.472071 DLL_IDLE_MODE = 1
7102 23:03:24.475405 LP45_APHY_COMB_EN = 1
7103 23:03:24.478383 TX_ODT_DIS = 0
7104 23:03:24.481835 NEW_8X_MODE = 1
7105 23:03:24.484866 ===================================
7106 23:03:24.484999 ===================================
7107 23:03:24.488694 data_rate = 3200
7108 23:03:24.491758 CKR = 1
7109 23:03:24.494826 DQ_P2S_RATIO = 8
7110 23:03:24.498009 ===================================
7111 23:03:24.501548 CA_P2S_RATIO = 8
7112 23:03:24.504753 DQ_CA_OPEN = 0
7113 23:03:24.507920 DQ_SEMI_OPEN = 0
7114 23:03:24.508053 CA_SEMI_OPEN = 0
7115 23:03:24.511642 CA_FULL_RATE = 0
7116 23:03:24.514587 DQ_CKDIV4_EN = 0
7117 23:03:24.518233 CA_CKDIV4_EN = 0
7118 23:03:24.521530 CA_PREDIV_EN = 0
7119 23:03:24.524469 PH8_DLY = 12
7120 23:03:24.527778 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7121 23:03:24.527859 DQ_AAMCK_DIV = 4
7122 23:03:24.530958 CA_AAMCK_DIV = 4
7123 23:03:24.534327 CA_ADMCK_DIV = 4
7124 23:03:24.537966 DQ_TRACK_CA_EN = 0
7125 23:03:24.541397 CA_PICK = 1600
7126 23:03:24.544349 CA_MCKIO = 1600
7127 23:03:24.547548 MCKIO_SEMI = 0
7128 23:03:24.547654 PLL_FREQ = 3068
7129 23:03:24.551228 DQ_UI_PI_RATIO = 32
7130 23:03:24.554273 CA_UI_PI_RATIO = 0
7131 23:03:24.557309 ===================================
7132 23:03:24.560635 ===================================
7133 23:03:24.564443 memory_type:LPDDR4
7134 23:03:24.567377 GP_NUM : 10
7135 23:03:24.567459 SRAM_EN : 1
7136 23:03:24.570607 MD32_EN : 0
7137 23:03:24.574098 ===================================
7138 23:03:24.574217 [ANA_INIT] >>>>>>>>>>>>>>
7139 23:03:24.577441 <<<<<< [CONFIGURE PHASE]: ANA_TX
7140 23:03:24.580429 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7141 23:03:24.583904 ===================================
7142 23:03:24.587337 data_rate = 3200,PCW = 0X7600
7143 23:03:24.590478 ===================================
7144 23:03:24.593575 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7145 23:03:24.599886 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7146 23:03:24.606880 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7147 23:03:24.610170 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7148 23:03:24.613272 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7149 23:03:24.617347 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7150 23:03:24.619943 [ANA_INIT] flow start
7151 23:03:24.620016 [ANA_INIT] PLL >>>>>>>>
7152 23:03:24.623014 [ANA_INIT] PLL <<<<<<<<
7153 23:03:24.626358 [ANA_INIT] MIDPI >>>>>>>>
7154 23:03:24.630310 [ANA_INIT] MIDPI <<<<<<<<
7155 23:03:24.630418 [ANA_INIT] DLL >>>>>>>>
7156 23:03:24.633101 [ANA_INIT] DLL <<<<<<<<
7157 23:03:24.633200 [ANA_INIT] flow end
7158 23:03:24.640076 ============ LP4 DIFF to SE enter ============
7159 23:03:24.642841 ============ LP4 DIFF to SE exit ============
7160 23:03:24.646245 [ANA_INIT] <<<<<<<<<<<<<
7161 23:03:24.649717 [Flow] Enable top DCM control >>>>>
7162 23:03:24.652706 [Flow] Enable top DCM control <<<<<
7163 23:03:24.656295 Enable DLL master slave shuffle
7164 23:03:24.659267 ==============================================================
7165 23:03:24.662657 Gating Mode config
7166 23:03:24.669041 ==============================================================
7167 23:03:24.669130 Config description:
7168 23:03:24.679189 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7169 23:03:24.686035 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7170 23:03:24.688836 SELPH_MODE 0: By rank 1: By Phase
7171 23:03:24.696118 ==============================================================
7172 23:03:24.699595 GAT_TRACK_EN = 1
7173 23:03:24.702100 RX_GATING_MODE = 2
7174 23:03:24.705719 RX_GATING_TRACK_MODE = 2
7175 23:03:24.709185 SELPH_MODE = 1
7176 23:03:24.712247 PICG_EARLY_EN = 1
7177 23:03:24.715919 VALID_LAT_VALUE = 1
7178 23:03:24.718428 ==============================================================
7179 23:03:24.722070 Enter into Gating configuration >>>>
7180 23:03:24.725410 Exit from Gating configuration <<<<
7181 23:03:24.729172 Enter into DVFS_PRE_config >>>>>
7182 23:03:24.741782 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7183 23:03:24.745301 Exit from DVFS_PRE_config <<<<<
7184 23:03:24.748212 Enter into PICG configuration >>>>
7185 23:03:24.748310 Exit from PICG configuration <<<<
7186 23:03:24.751508 [RX_INPUT] configuration >>>>>
7187 23:03:24.754815 [RX_INPUT] configuration <<<<<
7188 23:03:24.761668 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7189 23:03:24.764747 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7190 23:03:24.771377 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7191 23:03:24.778171 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7192 23:03:24.784698 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7193 23:03:24.791284 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7194 23:03:24.794427 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7195 23:03:24.797455 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7196 23:03:24.804409 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7197 23:03:24.807372 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7198 23:03:24.810584 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7199 23:03:24.814080 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7200 23:03:24.817360 ===================================
7201 23:03:24.820579 LPDDR4 DRAM CONFIGURATION
7202 23:03:24.824152 ===================================
7203 23:03:24.827233 EX_ROW_EN[0] = 0x0
7204 23:03:24.827313 EX_ROW_EN[1] = 0x0
7205 23:03:24.830806 LP4Y_EN = 0x0
7206 23:03:24.830887 WORK_FSP = 0x1
7207 23:03:24.834136 WL = 0x5
7208 23:03:24.834244 RL = 0x5
7209 23:03:24.837893 BL = 0x2
7210 23:03:24.840397 RPST = 0x0
7211 23:03:24.840473 RD_PRE = 0x0
7212 23:03:24.844021 WR_PRE = 0x1
7213 23:03:24.844092 WR_PST = 0x1
7214 23:03:24.847552 DBI_WR = 0x0
7215 23:03:24.847649 DBI_RD = 0x0
7216 23:03:24.850594 OTF = 0x1
7217 23:03:24.853363 ===================================
7218 23:03:24.857133 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7219 23:03:24.860268 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7220 23:03:24.866816 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7221 23:03:24.870235 ===================================
7222 23:03:24.870347 LPDDR4 DRAM CONFIGURATION
7223 23:03:24.873225 ===================================
7224 23:03:24.877050 EX_ROW_EN[0] = 0x10
7225 23:03:24.877133 EX_ROW_EN[1] = 0x0
7226 23:03:24.879789 LP4Y_EN = 0x0
7227 23:03:24.883229 WORK_FSP = 0x1
7228 23:03:24.883314 WL = 0x5
7229 23:03:24.886415 RL = 0x5
7230 23:03:24.886491 BL = 0x2
7231 23:03:24.889916 RPST = 0x0
7232 23:03:24.890019 RD_PRE = 0x0
7233 23:03:24.892942 WR_PRE = 0x1
7234 23:03:24.893085 WR_PST = 0x1
7235 23:03:24.896552 DBI_WR = 0x0
7236 23:03:24.896637 DBI_RD = 0x0
7237 23:03:24.899434 OTF = 0x1
7238 23:03:24.903045 ===================================
7239 23:03:24.909621 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7240 23:03:24.909750 ==
7241 23:03:24.912618 Dram Type= 6, Freq= 0, CH_0, rank 0
7242 23:03:24.916189 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7243 23:03:24.916315 ==
7244 23:03:24.919395 [Duty_Offset_Calibration]
7245 23:03:24.919498 B0:2 B1:0 CA:4
7246 23:03:24.919587
7247 23:03:24.922782 [DutyScan_Calibration_Flow] k_type=0
7248 23:03:24.932434
7249 23:03:24.932529 ==CLK 0==
7250 23:03:24.935420 Final CLK duty delay cell = -4
7251 23:03:24.939119 [-4] MAX Duty = 5031%(X100), DQS PI = 32
7252 23:03:24.942506 [-4] MIN Duty = 4844%(X100), DQS PI = 2
7253 23:03:24.945362 [-4] AVG Duty = 4937%(X100)
7254 23:03:24.945433
7255 23:03:24.948795 CH0 CLK Duty spec in!! Max-Min= 187%
7256 23:03:24.952233 [DutyScan_Calibration_Flow] ====Done====
7257 23:03:24.952316
7258 23:03:24.955863 [DutyScan_Calibration_Flow] k_type=1
7259 23:03:24.972714
7260 23:03:24.972814 ==DQS 0 ==
7261 23:03:24.975818 Final DQS duty delay cell = 0
7262 23:03:24.979224 [0] MAX Duty = 5218%(X100), DQS PI = 38
7263 23:03:24.982730 [0] MIN Duty = 5093%(X100), DQS PI = 8
7264 23:03:24.986178 [0] AVG Duty = 5155%(X100)
7265 23:03:24.986304
7266 23:03:24.986408 ==DQS 1 ==
7267 23:03:24.989210 Final DQS duty delay cell = 0
7268 23:03:24.992613 [0] MAX Duty = 5187%(X100), DQS PI = 2
7269 23:03:24.995537 [0] MIN Duty = 4969%(X100), DQS PI = 12
7270 23:03:24.998901 [0] AVG Duty = 5078%(X100)
7271 23:03:24.999009
7272 23:03:25.002131 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7273 23:03:25.002255
7274 23:03:25.005295 CH0 DQS 1 Duty spec in!! Max-Min= 218%
7275 23:03:25.009126 [DutyScan_Calibration_Flow] ====Done====
7276 23:03:25.009279
7277 23:03:25.012308 [DutyScan_Calibration_Flow] k_type=3
7278 23:03:25.029579
7279 23:03:25.029657 ==DQM 0 ==
7280 23:03:25.033249 Final DQM duty delay cell = 0
7281 23:03:25.036535 [0] MAX Duty = 5124%(X100), DQS PI = 20
7282 23:03:25.039400 [0] MIN Duty = 4875%(X100), DQS PI = 54
7283 23:03:25.043382 [0] AVG Duty = 4999%(X100)
7284 23:03:25.043466
7285 23:03:25.043532 ==DQM 1 ==
7286 23:03:25.046239 Final DQM duty delay cell = 0
7287 23:03:25.049548 [0] MAX Duty = 5000%(X100), DQS PI = 2
7288 23:03:25.052865 [0] MIN Duty = 4844%(X100), DQS PI = 40
7289 23:03:25.056203 [0] AVG Duty = 4922%(X100)
7290 23:03:25.056284
7291 23:03:25.059962 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7292 23:03:25.060044
7293 23:03:25.062641 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7294 23:03:25.066086 [DutyScan_Calibration_Flow] ====Done====
7295 23:03:25.066208
7296 23:03:25.069152 [DutyScan_Calibration_Flow] k_type=2
7297 23:03:25.087506
7298 23:03:25.087593 ==DQ 0 ==
7299 23:03:25.089989 Final DQ duty delay cell = 0
7300 23:03:25.093841 [0] MAX Duty = 5125%(X100), DQS PI = 20
7301 23:03:25.096579 [0] MIN Duty = 4938%(X100), DQS PI = 12
7302 23:03:25.096665 [0] AVG Duty = 5031%(X100)
7303 23:03:25.099965
7304 23:03:25.100048 ==DQ 1 ==
7305 23:03:25.103421 Final DQ duty delay cell = 0
7306 23:03:25.106374 [0] MAX Duty = 5187%(X100), DQS PI = 2
7307 23:03:25.110010 [0] MIN Duty = 4938%(X100), DQS PI = 12
7308 23:03:25.113459 [0] AVG Duty = 5062%(X100)
7309 23:03:25.113544
7310 23:03:25.116806 CH0 DQ 0 Duty spec in!! Max-Min= 187%
7311 23:03:25.116891
7312 23:03:25.119595 CH0 DQ 1 Duty spec in!! Max-Min= 249%
7313 23:03:25.123038 [DutyScan_Calibration_Flow] ====Done====
7314 23:03:25.123123 ==
7315 23:03:25.126281 Dram Type= 6, Freq= 0, CH_1, rank 0
7316 23:03:25.129576 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7317 23:03:25.129661 ==
7318 23:03:25.132691 [Duty_Offset_Calibration]
7319 23:03:25.132775 B0:0 B1:-1 CA:3
7320 23:03:25.132841
7321 23:03:25.136501 [DutyScan_Calibration_Flow] k_type=0
7322 23:03:25.146707
7323 23:03:25.146790 ==CLK 0==
7324 23:03:25.149244 Final CLK duty delay cell = -4
7325 23:03:25.152826 [-4] MAX Duty = 5000%(X100), DQS PI = 4
7326 23:03:25.156414 [-4] MIN Duty = 4875%(X100), DQS PI = 12
7327 23:03:25.159902 [-4] AVG Duty = 4937%(X100)
7328 23:03:25.160008
7329 23:03:25.162468 CH1 CLK Duty spec in!! Max-Min= 125%
7330 23:03:25.165994 [DutyScan_Calibration_Flow] ====Done====
7331 23:03:25.166099
7332 23:03:25.169502 [DutyScan_Calibration_Flow] k_type=1
7333 23:03:25.185809
7334 23:03:25.185912 ==DQS 0 ==
7335 23:03:25.188508 Final DQS duty delay cell = 0
7336 23:03:25.192144 [0] MAX Duty = 5250%(X100), DQS PI = 30
7337 23:03:25.195382 [0] MIN Duty = 4907%(X100), DQS PI = 56
7338 23:03:25.198734 [0] AVG Duty = 5078%(X100)
7339 23:03:25.198815
7340 23:03:25.198957 ==DQS 1 ==
7341 23:03:25.201754 Final DQS duty delay cell = -4
7342 23:03:25.205206 [-4] MAX Duty = 5000%(X100), DQS PI = 30
7343 23:03:25.208607 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7344 23:03:25.211539 [-4] AVG Duty = 4906%(X100)
7345 23:03:25.211615
7346 23:03:25.215027 CH1 DQS 0 Duty spec in!! Max-Min= 343%
7347 23:03:25.215129
7348 23:03:25.218403 CH1 DQS 1 Duty spec in!! Max-Min= 187%
7349 23:03:25.221231 [DutyScan_Calibration_Flow] ====Done====
7350 23:03:25.221324
7351 23:03:25.224518 [DutyScan_Calibration_Flow] k_type=3
7352 23:03:25.242554
7353 23:03:25.242633 ==DQM 0 ==
7354 23:03:25.245866 Final DQM duty delay cell = 0
7355 23:03:25.248984 [0] MAX Duty = 5031%(X100), DQS PI = 30
7356 23:03:25.252569 [0] MIN Duty = 4750%(X100), DQS PI = 40
7357 23:03:25.255858 [0] AVG Duty = 4890%(X100)
7358 23:03:25.255932
7359 23:03:25.256001 ==DQM 1 ==
7360 23:03:25.259348 Final DQM duty delay cell = 0
7361 23:03:25.262239 [0] MAX Duty = 5000%(X100), DQS PI = 30
7362 23:03:25.265539 [0] MIN Duty = 4813%(X100), DQS PI = 0
7363 23:03:25.269560 [0] AVG Duty = 4906%(X100)
7364 23:03:25.269630
7365 23:03:25.272372 CH1 DQM 0 Duty spec in!! Max-Min= 281%
7366 23:03:25.272470
7367 23:03:25.275612 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7368 23:03:25.278860 [DutyScan_Calibration_Flow] ====Done====
7369 23:03:25.278926
7370 23:03:25.282039 [DutyScan_Calibration_Flow] k_type=2
7371 23:03:25.298834
7372 23:03:25.298935 ==DQ 0 ==
7373 23:03:25.301952 Final DQ duty delay cell = -4
7374 23:03:25.305062 [-4] MAX Duty = 4969%(X100), DQS PI = 32
7375 23:03:25.308976 [-4] MIN Duty = 4813%(X100), DQS PI = 22
7376 23:03:25.311599 [-4] AVG Duty = 4891%(X100)
7377 23:03:25.311696
7378 23:03:25.311784 ==DQ 1 ==
7379 23:03:25.314830 Final DQ duty delay cell = 0
7380 23:03:25.318517 [0] MAX Duty = 5031%(X100), DQS PI = 30
7381 23:03:25.321708 [0] MIN Duty = 4875%(X100), DQS PI = 56
7382 23:03:25.324954 [0] AVG Duty = 4953%(X100)
7383 23:03:25.325062
7384 23:03:25.328327 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7385 23:03:25.328399
7386 23:03:25.331584 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7387 23:03:25.334667 [DutyScan_Calibration_Flow] ====Done====
7388 23:03:25.338769 nWR fixed to 30
7389 23:03:25.341624 [ModeRegInit_LP4] CH0 RK0
7390 23:03:25.341739 [ModeRegInit_LP4] CH0 RK1
7391 23:03:25.344888 [ModeRegInit_LP4] CH1 RK0
7392 23:03:25.348222 [ModeRegInit_LP4] CH1 RK1
7393 23:03:25.348335 match AC timing 5
7394 23:03:25.355125 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7395 23:03:25.357844 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7396 23:03:25.361444 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7397 23:03:25.368237 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7398 23:03:25.371165 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7399 23:03:25.374421 [MiockJmeterHQA]
7400 23:03:25.374501
7401 23:03:25.377844 [DramcMiockJmeter] u1RxGatingPI = 0
7402 23:03:25.377927 0 : 4255, 4029
7403 23:03:25.377998 4 : 4252, 4026
7404 23:03:25.380776 8 : 4252, 4026
7405 23:03:25.380891 12 : 4254, 4029
7406 23:03:25.384338 16 : 4252, 4027
7407 23:03:25.384431 20 : 4363, 4137
7408 23:03:25.387720 24 : 4363, 4137
7409 23:03:25.387796 28 : 4252, 4027
7410 23:03:25.390738 32 : 4253, 4026
7411 23:03:25.390808 36 : 4252, 4027
7412 23:03:25.390868 40 : 4252, 4027
7413 23:03:25.394539 44 : 4252, 4027
7414 23:03:25.394646 48 : 4363, 4138
7415 23:03:25.397729 52 : 4252, 4027
7416 23:03:25.397836 56 : 4253, 4027
7417 23:03:25.400635 60 : 4249, 4027
7418 23:03:25.400732 64 : 4255, 4029
7419 23:03:25.404315 68 : 4250, 4027
7420 23:03:25.404425 72 : 4360, 4137
7421 23:03:25.404506 76 : 4361, 4137
7422 23:03:25.407888 80 : 4252, 4027
7423 23:03:25.407956 84 : 4250, 4026
7424 23:03:25.410231 88 : 4250, 4027
7425 23:03:25.410340 92 : 4249, 4027
7426 23:03:25.413753 96 : 4253, 2493
7427 23:03:25.413854 100 : 4360, 0
7428 23:03:25.413950 104 : 4361, 0
7429 23:03:25.416941 108 : 4253, 0
7430 23:03:25.417041 112 : 4253, 0
7431 23:03:25.420285 116 : 4250, 0
7432 23:03:25.420382 120 : 4252, 0
7433 23:03:25.420476 124 : 4249, 0
7434 23:03:25.423872 128 : 4361, 0
7435 23:03:25.423973 132 : 4250, 0
7436 23:03:25.426913 136 : 4249, 0
7437 23:03:25.426993 140 : 4250, 0
7438 23:03:25.427061 144 : 4250, 0
7439 23:03:25.430405 148 : 4253, 0
7440 23:03:25.430476 152 : 4360, 0
7441 23:03:25.433957 156 : 4361, 0
7442 23:03:25.434054 160 : 4249, 0
7443 23:03:25.434142 164 : 4360, 0
7444 23:03:25.437041 168 : 4250, 0
7445 23:03:25.437142 172 : 4250, 0
7446 23:03:25.437229 176 : 4249, 0
7447 23:03:25.440101 180 : 4361, 0
7448 23:03:25.440186 184 : 4250, 0
7449 23:03:25.443937 188 : 4249, 0
7450 23:03:25.444013 192 : 4250, 0
7451 23:03:25.444074 196 : 4253, 0
7452 23:03:25.446545 200 : 4249, 0
7453 23:03:25.446631 204 : 4361, 0
7454 23:03:25.450654 208 : 4360, 0
7455 23:03:25.450770 212 : 4250, 0
7456 23:03:25.450866 216 : 4249, 0
7457 23:03:25.453369 220 : 4250, 788
7458 23:03:25.453454 224 : 4249, 4017
7459 23:03:25.457018 228 : 4253, 4029
7460 23:03:25.457121 232 : 4250, 4026
7461 23:03:25.459891 236 : 4250, 4027
7462 23:03:25.459987 240 : 4250, 4027
7463 23:03:25.463457 244 : 4360, 4137
7464 23:03:25.463530 248 : 4250, 4027
7465 23:03:25.466727 252 : 4250, 4027
7466 23:03:25.466800 256 : 4360, 4138
7467 23:03:25.469872 260 : 4253, 4027
7468 23:03:25.469939 264 : 4250, 4026
7469 23:03:25.473405 268 : 4363, 4139
7470 23:03:25.473479 272 : 4249, 4027
7471 23:03:25.473541 276 : 4249, 4027
7472 23:03:25.476379 280 : 4250, 4026
7473 23:03:25.476448 284 : 4253, 4029
7474 23:03:25.479614 288 : 4250, 4027
7475 23:03:25.479688 292 : 4250, 4027
7476 23:03:25.482803 296 : 4360, 4137
7477 23:03:25.482874 300 : 4250, 4026
7478 23:03:25.486523 304 : 4250, 4027
7479 23:03:25.486621 308 : 4361, 4137
7480 23:03:25.489462 312 : 4249, 4027
7481 23:03:25.489562 316 : 4250, 4026
7482 23:03:25.493045 320 : 4363, 4140
7483 23:03:25.493121 324 : 4250, 4027
7484 23:03:25.495923 328 : 4250, 4027
7485 23:03:25.496022 332 : 4250, 3649
7486 23:03:25.499090 336 : 4253, 1578
7487 23:03:25.499164
7488 23:03:25.499225 MIOCK jitter meter ch=0
7489 23:03:25.499283
7490 23:03:25.502636 1T = (336-100) = 236 dly cells
7491 23:03:25.509290 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7492 23:03:25.509368 ==
7493 23:03:25.512651 Dram Type= 6, Freq= 0, CH_0, rank 0
7494 23:03:25.515537 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7495 23:03:25.515608 ==
7496 23:03:25.522333 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7497 23:03:25.525397 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7498 23:03:25.529341 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7499 23:03:25.535526 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7500 23:03:25.545630 [CA 0] Center 43 (13~74) winsize 62
7501 23:03:25.548862 [CA 1] Center 42 (12~73) winsize 62
7502 23:03:25.551810 [CA 2] Center 37 (8~67) winsize 60
7503 23:03:25.555099 [CA 3] Center 37 (8~67) winsize 60
7504 23:03:25.558271 [CA 4] Center 36 (6~66) winsize 61
7505 23:03:25.562011 [CA 5] Center 35 (5~66) winsize 62
7506 23:03:25.562092
7507 23:03:25.565137 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7508 23:03:25.565218
7509 23:03:25.571373 [CATrainingPosCal] consider 1 rank data
7510 23:03:25.571454 u2DelayCellTimex100 = 275/100 ps
7511 23:03:25.578268 CA0 delay=43 (13~74),Diff = 8 PI (28 cell)
7512 23:03:25.581691 CA1 delay=42 (12~73),Diff = 7 PI (24 cell)
7513 23:03:25.584932 CA2 delay=37 (8~67),Diff = 2 PI (7 cell)
7514 23:03:25.587792 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7515 23:03:25.591571 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7516 23:03:25.594939 CA5 delay=35 (5~66),Diff = 0 PI (0 cell)
7517 23:03:25.595048
7518 23:03:25.597939 CA PerBit enable=1, Macro0, CA PI delay=35
7519 23:03:25.598037
7520 23:03:25.600955 [CBTSetCACLKResult] CA Dly = 35
7521 23:03:25.604404 CS Dly: 11 (0~42)
7522 23:03:25.607927 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7523 23:03:25.611228 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7524 23:03:25.611299 ==
7525 23:03:25.614161 Dram Type= 6, Freq= 0, CH_0, rank 1
7526 23:03:25.621290 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7527 23:03:25.621389 ==
7528 23:03:25.623882 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7529 23:03:25.631138 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7530 23:03:25.633927 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7531 23:03:25.640746 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7532 23:03:25.648809 [CA 0] Center 44 (14~75) winsize 62
7533 23:03:25.651924 [CA 1] Center 44 (14~74) winsize 61
7534 23:03:25.655567 [CA 2] Center 39 (10~69) winsize 60
7535 23:03:25.658793 [CA 3] Center 39 (10~68) winsize 59
7536 23:03:25.662138 [CA 4] Center 37 (7~67) winsize 61
7537 23:03:25.665286 [CA 5] Center 36 (7~66) winsize 60
7538 23:03:25.665368
7539 23:03:25.668636 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7540 23:03:25.668732
7541 23:03:25.675286 [CATrainingPosCal] consider 2 rank data
7542 23:03:25.675390 u2DelayCellTimex100 = 275/100 ps
7543 23:03:25.681914 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7544 23:03:25.684786 CA1 delay=43 (14~73),Diff = 7 PI (24 cell)
7545 23:03:25.688233 CA2 delay=38 (10~67),Diff = 2 PI (7 cell)
7546 23:03:25.691639 CA3 delay=38 (10~67),Diff = 2 PI (7 cell)
7547 23:03:25.694962 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7548 23:03:25.697870 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7549 23:03:25.697976
7550 23:03:25.701281 CA PerBit enable=1, Macro0, CA PI delay=36
7551 23:03:25.701377
7552 23:03:25.704923 [CBTSetCACLKResult] CA Dly = 36
7553 23:03:25.707816 CS Dly: 12 (0~44)
7554 23:03:25.711461 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7555 23:03:25.714671 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7556 23:03:25.714744
7557 23:03:25.718240 ----->DramcWriteLeveling(PI) begin...
7558 23:03:25.721187 ==
7559 23:03:25.724670 Dram Type= 6, Freq= 0, CH_0, rank 0
7560 23:03:25.727914 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7561 23:03:25.727996 ==
7562 23:03:25.731072 Write leveling (Byte 0): 34 => 34
7563 23:03:25.734475 Write leveling (Byte 1): 28 => 28
7564 23:03:25.737621 DramcWriteLeveling(PI) end<-----
7565 23:03:25.737701
7566 23:03:25.737765 ==
7567 23:03:25.740811 Dram Type= 6, Freq= 0, CH_0, rank 0
7568 23:03:25.744208 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7569 23:03:25.744289 ==
7570 23:03:25.748012 [Gating] SW mode calibration
7571 23:03:25.753735 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7572 23:03:25.760452 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7573 23:03:25.763959 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7574 23:03:25.767413 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7575 23:03:25.774191 1 4 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7576 23:03:25.776936 1 4 12 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
7577 23:03:25.780339 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7578 23:03:25.787047 1 4 20 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
7579 23:03:25.790349 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7580 23:03:25.793536 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7581 23:03:25.800066 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7582 23:03:25.803517 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7583 23:03:25.806684 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
7584 23:03:25.813597 1 5 12 | B1->B0 | 3434 2828 | 1 0 | (1 1) (1 0)
7585 23:03:25.816808 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7586 23:03:25.819706 1 5 20 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (0 0)
7587 23:03:25.826239 1 5 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
7588 23:03:25.829650 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7589 23:03:25.832985 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7590 23:03:25.840186 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7591 23:03:25.842993 1 6 8 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
7592 23:03:25.846247 1 6 12 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
7593 23:03:25.853104 1 6 16 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
7594 23:03:25.856432 1 6 20 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
7595 23:03:25.859652 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7596 23:03:25.866516 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7597 23:03:25.869666 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7598 23:03:25.873009 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7599 23:03:25.879420 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7600 23:03:25.882786 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7601 23:03:25.886148 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7602 23:03:25.892576 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7603 23:03:25.896191 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7604 23:03:25.899118 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7605 23:03:25.905988 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7606 23:03:25.909104 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7607 23:03:25.912013 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7608 23:03:25.919218 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7609 23:03:25.922198 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7610 23:03:25.926033 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7611 23:03:25.932292 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7612 23:03:25.936128 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7613 23:03:25.938518 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7614 23:03:25.945247 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7615 23:03:25.948503 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7616 23:03:25.951438 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7617 23:03:25.957947 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7618 23:03:25.961289 Total UI for P1: 0, mck2ui 16
7619 23:03:25.964531 best dqsien dly found for B0: ( 1, 9, 10)
7620 23:03:25.967940 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7621 23:03:25.971289 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7622 23:03:25.977464 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7623 23:03:25.980930 Total UI for P1: 0, mck2ui 16
7624 23:03:25.984524 best dqsien dly found for B1: ( 1, 9, 22)
7625 23:03:25.987488 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7626 23:03:25.990962 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7627 23:03:25.991062
7628 23:03:25.993917 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7629 23:03:25.997533 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7630 23:03:26.000924 [Gating] SW calibration Done
7631 23:03:26.001003 ==
7632 23:03:26.004116 Dram Type= 6, Freq= 0, CH_0, rank 0
7633 23:03:26.007113 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7634 23:03:26.010796 ==
7635 23:03:26.010867 RX Vref Scan: 0
7636 23:03:26.010928
7637 23:03:26.013740 RX Vref 0 -> 0, step: 1
7638 23:03:26.013836
7639 23:03:26.013923 RX Delay 0 -> 252, step: 8
7640 23:03:26.020201 iDelay=192, Bit 0, Center 135 (80 ~ 191) 112
7641 23:03:26.024024 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7642 23:03:26.026985 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7643 23:03:26.030522 iDelay=192, Bit 3, Center 123 (72 ~ 175) 104
7644 23:03:26.033819 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7645 23:03:26.040442 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7646 23:03:26.043283 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7647 23:03:26.046557 iDelay=192, Bit 7, Center 135 (80 ~ 191) 112
7648 23:03:26.050089 iDelay=192, Bit 8, Center 115 (64 ~ 167) 104
7649 23:03:26.056814 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7650 23:03:26.059971 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7651 23:03:26.063069 iDelay=192, Bit 11, Center 123 (72 ~ 175) 104
7652 23:03:26.066715 iDelay=192, Bit 12, Center 131 (72 ~ 191) 120
7653 23:03:26.069730 iDelay=192, Bit 13, Center 135 (80 ~ 191) 112
7654 23:03:26.076415 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7655 23:03:26.079638 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7656 23:03:26.079710 ==
7657 23:03:26.083094 Dram Type= 6, Freq= 0, CH_0, rank 0
7658 23:03:26.086442 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7659 23:03:26.086531 ==
7660 23:03:26.089473 DQS Delay:
7661 23:03:26.089553 DQS0 = 0, DQS1 = 0
7662 23:03:26.089624 DQM Delay:
7663 23:03:26.092851 DQM0 = 131, DQM1 = 126
7664 23:03:26.092932 DQ Delay:
7665 23:03:26.095992 DQ0 =135, DQ1 =135, DQ2 =127, DQ3 =123
7666 23:03:26.102722 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =135
7667 23:03:26.106234 DQ8 =115, DQ9 =111, DQ10 =127, DQ11 =123
7668 23:03:26.109396 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =135
7669 23:03:26.109819
7670 23:03:26.110151
7671 23:03:26.110604 ==
7672 23:03:26.112969 Dram Type= 6, Freq= 0, CH_0, rank 0
7673 23:03:26.116657 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7674 23:03:26.117178 ==
7675 23:03:26.117515
7676 23:03:26.117819
7677 23:03:26.119574 TX Vref Scan disable
7678 23:03:26.122981 == TX Byte 0 ==
7679 23:03:26.126370 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7680 23:03:26.129419 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7681 23:03:26.132451 == TX Byte 1 ==
7682 23:03:26.136073 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7683 23:03:26.139734 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7684 23:03:26.140151 ==
7685 23:03:26.142790 Dram Type= 6, Freq= 0, CH_0, rank 0
7686 23:03:26.149304 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7687 23:03:26.149726 ==
7688 23:03:26.161019
7689 23:03:26.164430 TX Vref early break, caculate TX vref
7690 23:03:26.167514 TX Vref=16, minBit 1, minWin=22, winSum=367
7691 23:03:26.170850 TX Vref=18, minBit 6, minWin=22, winSum=380
7692 23:03:26.173914 TX Vref=20, minBit 1, minWin=23, winSum=392
7693 23:03:26.177302 TX Vref=22, minBit 6, minWin=24, winSum=401
7694 23:03:26.181062 TX Vref=24, minBit 7, minWin=24, winSum=412
7695 23:03:26.187286 TX Vref=26, minBit 1, minWin=25, winSum=418
7696 23:03:26.190579 TX Vref=28, minBit 4, minWin=25, winSum=427
7697 23:03:26.194054 TX Vref=30, minBit 2, minWin=25, winSum=421
7698 23:03:26.197348 TX Vref=32, minBit 4, minWin=24, winSum=410
7699 23:03:26.200873 TX Vref=34, minBit 1, minWin=23, winSum=400
7700 23:03:26.207278 [TxChooseVref] Worse bit 4, Min win 25, Win sum 427, Final Vref 28
7701 23:03:26.207737
7702 23:03:26.210699 Final TX Range 0 Vref 28
7703 23:03:26.211119
7704 23:03:26.211449 ==
7705 23:03:26.213623 Dram Type= 6, Freq= 0, CH_0, rank 0
7706 23:03:26.217217 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7707 23:03:26.217638 ==
7708 23:03:26.217968
7709 23:03:26.218314
7710 23:03:26.220156 TX Vref Scan disable
7711 23:03:26.226783 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7712 23:03:26.227198 == TX Byte 0 ==
7713 23:03:26.229918 u2DelayCellOfst[0]=10 cells (3 PI)
7714 23:03:26.233610 u2DelayCellOfst[1]=14 cells (4 PI)
7715 23:03:26.236349 u2DelayCellOfst[2]=10 cells (3 PI)
7716 23:03:26.239703 u2DelayCellOfst[3]=10 cells (3 PI)
7717 23:03:26.243496 u2DelayCellOfst[4]=7 cells (2 PI)
7718 23:03:26.246153 u2DelayCellOfst[5]=0 cells (0 PI)
7719 23:03:26.249803 u2DelayCellOfst[6]=17 cells (5 PI)
7720 23:03:26.255217 u2DelayCellOfst[7]=14 cells (4 PI)
7721 23:03:26.256304 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7722 23:03:26.259582 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7723 23:03:26.263156 == TX Byte 1 ==
7724 23:03:26.266074 u2DelayCellOfst[8]=0 cells (0 PI)
7725 23:03:26.269401 u2DelayCellOfst[9]=0 cells (0 PI)
7726 23:03:26.272805 u2DelayCellOfst[10]=7 cells (2 PI)
7727 23:03:26.276095 u2DelayCellOfst[11]=3 cells (1 PI)
7728 23:03:26.279050 u2DelayCellOfst[12]=10 cells (3 PI)
7729 23:03:26.282524 u2DelayCellOfst[13]=10 cells (3 PI)
7730 23:03:26.283000 u2DelayCellOfst[14]=14 cells (4 PI)
7731 23:03:26.285480 u2DelayCellOfst[15]=10 cells (3 PI)
7732 23:03:26.292224 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7733 23:03:26.295841 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7734 23:03:26.299356 DramC Write-DBI on
7735 23:03:26.299958 ==
7736 23:03:26.302374 Dram Type= 6, Freq= 0, CH_0, rank 0
7737 23:03:26.305645 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7738 23:03:26.306333 ==
7739 23:03:26.306795
7740 23:03:26.307147
7741 23:03:26.308913 TX Vref Scan disable
7742 23:03:26.309325 == TX Byte 0 ==
7743 23:03:26.315761 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
7744 23:03:26.316210 == TX Byte 1 ==
7745 23:03:26.318739 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
7746 23:03:26.322210 DramC Write-DBI off
7747 23:03:26.322666
7748 23:03:26.323035 [DATLAT]
7749 23:03:26.325506 Freq=1600, CH0 RK0
7750 23:03:26.325919
7751 23:03:26.326320 DATLAT Default: 0xf
7752 23:03:26.328894 0, 0xFFFF, sum = 0
7753 23:03:26.329345 1, 0xFFFF, sum = 0
7754 23:03:26.331748 2, 0xFFFF, sum = 0
7755 23:03:26.335268 3, 0xFFFF, sum = 0
7756 23:03:26.335706 4, 0xFFFF, sum = 0
7757 23:03:26.338589 5, 0xFFFF, sum = 0
7758 23:03:26.339006 6, 0xFFFF, sum = 0
7759 23:03:26.341711 7, 0xFFFF, sum = 0
7760 23:03:26.342127 8, 0xFFFF, sum = 0
7761 23:03:26.345765 9, 0xFFFF, sum = 0
7762 23:03:26.346363 10, 0xFFFF, sum = 0
7763 23:03:26.348093 11, 0xFFFF, sum = 0
7764 23:03:26.348690 12, 0xFFFF, sum = 0
7765 23:03:26.351822 13, 0xFFFF, sum = 0
7766 23:03:26.352243 14, 0x0, sum = 1
7767 23:03:26.355153 15, 0x0, sum = 2
7768 23:03:26.355577 16, 0x0, sum = 3
7769 23:03:26.358513 17, 0x0, sum = 4
7770 23:03:26.358936 best_step = 15
7771 23:03:26.359265
7772 23:03:26.359569 ==
7773 23:03:26.361893 Dram Type= 6, Freq= 0, CH_0, rank 0
7774 23:03:26.368102 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7775 23:03:26.368568 ==
7776 23:03:26.368907 RX Vref Scan: 1
7777 23:03:26.369219
7778 23:03:26.371832 Set Vref Range= 24 -> 127
7779 23:03:26.372245
7780 23:03:26.374705 RX Vref 24 -> 127, step: 1
7781 23:03:26.375123
7782 23:03:26.375453 RX Delay 11 -> 252, step: 4
7783 23:03:26.378462
7784 23:03:26.378981 Set Vref, RX VrefLevel [Byte0]: 24
7785 23:03:26.381575 [Byte1]: 24
7786 23:03:26.385422
7787 23:03:26.385994 Set Vref, RX VrefLevel [Byte0]: 25
7788 23:03:26.389132 [Byte1]: 25
7789 23:03:26.393009
7790 23:03:26.393598 Set Vref, RX VrefLevel [Byte0]: 26
7791 23:03:26.396197 [Byte1]: 26
7792 23:03:26.400567
7793 23:03:26.400959 Set Vref, RX VrefLevel [Byte0]: 27
7794 23:03:26.403747 [Byte1]: 27
7795 23:03:26.408730
7796 23:03:26.408954 Set Vref, RX VrefLevel [Byte0]: 28
7797 23:03:26.411553 [Byte1]: 28
7798 23:03:26.415901
7799 23:03:26.416167 Set Vref, RX VrefLevel [Byte0]: 29
7800 23:03:26.418913 [Byte1]: 29
7801 23:03:26.423652
7802 23:03:26.423873 Set Vref, RX VrefLevel [Byte0]: 30
7803 23:03:26.426542 [Byte1]: 30
7804 23:03:26.431217
7805 23:03:26.431438 Set Vref, RX VrefLevel [Byte0]: 31
7806 23:03:26.434276 [Byte1]: 31
7807 23:03:26.438818
7808 23:03:26.439040 Set Vref, RX VrefLevel [Byte0]: 32
7809 23:03:26.441641 [Byte1]: 32
7810 23:03:26.446358
7811 23:03:26.446623 Set Vref, RX VrefLevel [Byte0]: 33
7812 23:03:26.449395 [Byte1]: 33
7813 23:03:26.454343
7814 23:03:26.454597 Set Vref, RX VrefLevel [Byte0]: 34
7815 23:03:26.456919 [Byte1]: 34
7816 23:03:26.461463
7817 23:03:26.461684 Set Vref, RX VrefLevel [Byte0]: 35
7818 23:03:26.464948 [Byte1]: 35
7819 23:03:26.469283
7820 23:03:26.469516 Set Vref, RX VrefLevel [Byte0]: 36
7821 23:03:26.472435 [Byte1]: 36
7822 23:03:26.476600
7823 23:03:26.476822 Set Vref, RX VrefLevel [Byte0]: 37
7824 23:03:26.480092 [Byte1]: 37
7825 23:03:26.484145
7826 23:03:26.484226 Set Vref, RX VrefLevel [Byte0]: 38
7827 23:03:26.487400 [Byte1]: 38
7828 23:03:26.491799
7829 23:03:26.491894 Set Vref, RX VrefLevel [Byte0]: 39
7830 23:03:26.495200 [Byte1]: 39
7831 23:03:26.499688
7832 23:03:26.499769 Set Vref, RX VrefLevel [Byte0]: 40
7833 23:03:26.502549 [Byte1]: 40
7834 23:03:26.506619
7835 23:03:26.506697 Set Vref, RX VrefLevel [Byte0]: 41
7836 23:03:26.510698 [Byte1]: 41
7837 23:03:26.514659
7838 23:03:26.514740 Set Vref, RX VrefLevel [Byte0]: 42
7839 23:03:26.518186 [Byte1]: 42
7840 23:03:26.522134
7841 23:03:26.522214 Set Vref, RX VrefLevel [Byte0]: 43
7842 23:03:26.525306 [Byte1]: 43
7843 23:03:26.529873
7844 23:03:26.529952 Set Vref, RX VrefLevel [Byte0]: 44
7845 23:03:26.533273 [Byte1]: 44
7846 23:03:26.537824
7847 23:03:26.537903 Set Vref, RX VrefLevel [Byte0]: 45
7848 23:03:26.540811 [Byte1]: 45
7849 23:03:26.544967
7850 23:03:26.545059 Set Vref, RX VrefLevel [Byte0]: 46
7851 23:03:26.548339 [Byte1]: 46
7852 23:03:26.552940
7853 23:03:26.553043 Set Vref, RX VrefLevel [Byte0]: 47
7854 23:03:26.556412 [Byte1]: 47
7855 23:03:26.560349
7856 23:03:26.560545 Set Vref, RX VrefLevel [Byte0]: 48
7857 23:03:26.563478 [Byte1]: 48
7858 23:03:26.568107
7859 23:03:26.568345 Set Vref, RX VrefLevel [Byte0]: 49
7860 23:03:26.571092 [Byte1]: 49
7861 23:03:26.575956
7862 23:03:26.576160 Set Vref, RX VrefLevel [Byte0]: 50
7863 23:03:26.578947 [Byte1]: 50
7864 23:03:26.583150
7865 23:03:26.583374 Set Vref, RX VrefLevel [Byte0]: 51
7866 23:03:26.586351 [Byte1]: 51
7867 23:03:26.591211
7868 23:03:26.591734 Set Vref, RX VrefLevel [Byte0]: 52
7869 23:03:26.594213 [Byte1]: 52
7870 23:03:26.598830
7871 23:03:26.599210 Set Vref, RX VrefLevel [Byte0]: 53
7872 23:03:26.602052 [Byte1]: 53
7873 23:03:26.606149
7874 23:03:26.606611 Set Vref, RX VrefLevel [Byte0]: 54
7875 23:03:26.609333 [Byte1]: 54
7876 23:03:26.613713
7877 23:03:26.614123 Set Vref, RX VrefLevel [Byte0]: 55
7878 23:03:26.617319 [Byte1]: 55
7879 23:03:26.621399
7880 23:03:26.621814 Set Vref, RX VrefLevel [Byte0]: 56
7881 23:03:26.625087 [Byte1]: 56
7882 23:03:26.629277
7883 23:03:26.629695 Set Vref, RX VrefLevel [Byte0]: 57
7884 23:03:26.632514 [Byte1]: 57
7885 23:03:26.636493
7886 23:03:26.636951 Set Vref, RX VrefLevel [Byte0]: 58
7887 23:03:26.639914 [Byte1]: 58
7888 23:03:26.644657
7889 23:03:26.645091 Set Vref, RX VrefLevel [Byte0]: 59
7890 23:03:26.647486 [Byte1]: 59
7891 23:03:26.651850
7892 23:03:26.651931 Set Vref, RX VrefLevel [Byte0]: 60
7893 23:03:26.658109 [Byte1]: 60
7894 23:03:26.658190
7895 23:03:26.661191 Set Vref, RX VrefLevel [Byte0]: 61
7896 23:03:26.664882 [Byte1]: 61
7897 23:03:26.664966
7898 23:03:26.668032 Set Vref, RX VrefLevel [Byte0]: 62
7899 23:03:26.671058 [Byte1]: 62
7900 23:03:26.674542
7901 23:03:26.674643 Set Vref, RX VrefLevel [Byte0]: 63
7902 23:03:26.677654 [Byte1]: 63
7903 23:03:26.682396
7904 23:03:26.682551 Set Vref, RX VrefLevel [Byte0]: 64
7905 23:03:26.685184 [Byte1]: 64
7906 23:03:26.689921
7907 23:03:26.690032 Set Vref, RX VrefLevel [Byte0]: 65
7908 23:03:26.693423 [Byte1]: 65
7909 23:03:26.697251
7910 23:03:26.697365 Set Vref, RX VrefLevel [Byte0]: 66
7911 23:03:26.700940 [Byte1]: 66
7912 23:03:26.704867
7913 23:03:26.704948 Set Vref, RX VrefLevel [Byte0]: 67
7914 23:03:26.708605 [Byte1]: 67
7915 23:03:26.713044
7916 23:03:26.713128 Set Vref, RX VrefLevel [Byte0]: 68
7917 23:03:26.716149 [Byte1]: 68
7918 23:03:26.719972
7919 23:03:26.720052 Set Vref, RX VrefLevel [Byte0]: 69
7920 23:03:26.723246 [Byte1]: 69
7921 23:03:26.728024
7922 23:03:26.728169 Set Vref, RX VrefLevel [Byte0]: 70
7923 23:03:26.731500 [Byte1]: 70
7924 23:03:26.735213
7925 23:03:26.735289 Set Vref, RX VrefLevel [Byte0]: 71
7926 23:03:26.738463 [Byte1]: 71
7927 23:03:26.743050
7928 23:03:26.743128 Set Vref, RX VrefLevel [Byte0]: 72
7929 23:03:26.746412 [Byte1]: 72
7930 23:03:26.750687
7931 23:03:26.750776 Set Vref, RX VrefLevel [Byte0]: 73
7932 23:03:26.757300 [Byte1]: 73
7933 23:03:26.757400
7934 23:03:26.760037 Set Vref, RX VrefLevel [Byte0]: 74
7935 23:03:26.763351 [Byte1]: 74
7936 23:03:26.763431
7937 23:03:26.767313 Set Vref, RX VrefLevel [Byte0]: 75
7938 23:03:26.770248 [Byte1]: 75
7939 23:03:26.770375
7940 23:03:26.773732 Final RX Vref Byte 0 = 54 to rank0
7941 23:03:26.777237 Final RX Vref Byte 1 = 65 to rank0
7942 23:03:26.780171 Final RX Vref Byte 0 = 54 to rank1
7943 23:03:26.783698 Final RX Vref Byte 1 = 65 to rank1==
7944 23:03:26.786623 Dram Type= 6, Freq= 0, CH_0, rank 0
7945 23:03:26.793703 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7946 23:03:26.793875 ==
7947 23:03:26.793958 DQS Delay:
7948 23:03:26.794045 DQS0 = 0, DQS1 = 0
7949 23:03:26.796566 DQM Delay:
7950 23:03:26.796755 DQM0 = 128, DQM1 = 124
7951 23:03:26.800176 DQ Delay:
7952 23:03:26.803196 DQ0 =130, DQ1 =130, DQ2 =124, DQ3 =124
7953 23:03:26.806887 DQ4 =130, DQ5 =118, DQ6 =138, DQ7 =134
7954 23:03:26.810111 DQ8 =114, DQ9 =110, DQ10 =124, DQ11 =120
7955 23:03:26.813247 DQ12 =130, DQ13 =132, DQ14 =134, DQ15 =128
7956 23:03:26.813382
7957 23:03:26.813490
7958 23:03:26.813590
7959 23:03:26.816358 [DramC_TX_OE_Calibration] TA2
7960 23:03:26.819460 Original DQ_B0 (3 6) =30, OEN = 27
7961 23:03:26.822694 Original DQ_B1 (3 6) =30, OEN = 27
7962 23:03:26.826291 24, 0x0, End_B0=24 End_B1=24
7963 23:03:26.829454 25, 0x0, End_B0=25 End_B1=25
7964 23:03:26.829714 26, 0x0, End_B0=26 End_B1=26
7965 23:03:26.833064 27, 0x0, End_B0=27 End_B1=27
7966 23:03:26.836229 28, 0x0, End_B0=28 End_B1=28
7967 23:03:26.839599 29, 0x0, End_B0=29 End_B1=29
7968 23:03:26.839883 30, 0x0, End_B0=30 End_B1=30
7969 23:03:26.842655 31, 0x4141, End_B0=30 End_B1=30
7970 23:03:26.845794 Byte0 end_step=30 best_step=27
7971 23:03:26.848894 Byte1 end_step=30 best_step=27
7972 23:03:26.852510 Byte0 TX OE(2T, 0.5T) = (3, 3)
7973 23:03:26.855531 Byte1 TX OE(2T, 0.5T) = (3, 3)
7974 23:03:26.855613
7975 23:03:26.855678
7976 23:03:26.862403 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a17, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
7977 23:03:26.866007 CH0 RK0: MR19=303, MR18=1A17
7978 23:03:26.872658 CH0_RK0: MR19=0x303, MR18=0x1A17, DQSOSC=396, MR23=63, INC=23, DEC=15
7979 23:03:26.872736
7980 23:03:26.875787 ----->DramcWriteLeveling(PI) begin...
7981 23:03:26.875870 ==
7982 23:03:26.878608 Dram Type= 6, Freq= 0, CH_0, rank 1
7983 23:03:26.882202 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7984 23:03:26.882326 ==
7985 23:03:26.884936 Write leveling (Byte 0): 34 => 34
7986 23:03:26.888442 Write leveling (Byte 1): 27 => 27
7987 23:03:26.892095 DramcWriteLeveling(PI) end<-----
7988 23:03:26.892258
7989 23:03:26.892337 ==
7990 23:03:26.895081 Dram Type= 6, Freq= 0, CH_0, rank 1
7991 23:03:26.901943 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7992 23:03:26.902115 ==
7993 23:03:26.902213 [Gating] SW mode calibration
7994 23:03:26.911338 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7995 23:03:26.914915 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7996 23:03:26.921510 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7997 23:03:26.924662 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7998 23:03:26.928127 1 4 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
7999 23:03:26.934804 1 4 12 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
8000 23:03:26.937902 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8001 23:03:26.941440 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8002 23:03:26.948142 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8003 23:03:26.951021 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8004 23:03:26.954770 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8005 23:03:26.961233 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8006 23:03:26.964441 1 5 8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
8007 23:03:26.967650 1 5 12 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 1)
8008 23:03:26.974577 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8009 23:03:26.977892 1 5 20 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
8010 23:03:26.980717 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8011 23:03:26.987452 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8012 23:03:26.991001 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8013 23:03:26.993722 1 6 4 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
8014 23:03:27.000802 1 6 8 | B1->B0 | 2323 3636 | 0 1 | (0 0) (0 0)
8015 23:03:27.004336 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8016 23:03:27.007066 1 6 16 | B1->B0 | 3131 4646 | 0 0 | (0 0) (0 0)
8017 23:03:27.013507 1 6 20 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8018 23:03:27.017004 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8019 23:03:27.020632 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8020 23:03:27.026700 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8021 23:03:27.030450 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8022 23:03:27.033710 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8023 23:03:27.040075 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8024 23:03:27.043197 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8025 23:03:27.046626 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8026 23:03:27.053474 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8027 23:03:27.056349 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8028 23:03:27.059536 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8029 23:03:27.066405 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8030 23:03:27.069506 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8031 23:03:27.072885 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8032 23:03:27.079463 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8033 23:03:27.082844 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8034 23:03:27.086043 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8035 23:03:27.092412 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8036 23:03:27.095814 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8037 23:03:27.099058 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8038 23:03:27.106160 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8039 23:03:27.109000 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8040 23:03:27.112260 Total UI for P1: 0, mck2ui 16
8041 23:03:27.115802 best dqsien dly found for B0: ( 1, 9, 6)
8042 23:03:27.118753 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8043 23:03:27.125900 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8044 23:03:27.128720 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8045 23:03:27.132138 Total UI for P1: 0, mck2ui 16
8046 23:03:27.135559 best dqsien dly found for B1: ( 1, 9, 18)
8047 23:03:27.138529 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8048 23:03:27.141963 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8049 23:03:27.142283
8050 23:03:27.145515 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8051 23:03:27.148411 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8052 23:03:27.151908 [Gating] SW calibration Done
8053 23:03:27.152215 ==
8054 23:03:27.155313 Dram Type= 6, Freq= 0, CH_0, rank 1
8055 23:03:27.161767 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8056 23:03:27.162088 ==
8057 23:03:27.162372 RX Vref Scan: 0
8058 23:03:27.162597
8059 23:03:27.165657 RX Vref 0 -> 0, step: 1
8060 23:03:27.165946
8061 23:03:27.168666 RX Delay 0 -> 252, step: 8
8062 23:03:27.171821 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
8063 23:03:27.174583 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8064 23:03:27.178328 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8065 23:03:27.181394 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8066 23:03:27.187864 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8067 23:03:27.191412 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8068 23:03:27.194402 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8069 23:03:27.198242 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8070 23:03:27.204655 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8071 23:03:27.208154 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8072 23:03:27.210839 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8073 23:03:27.214304 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8074 23:03:27.217808 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8075 23:03:27.224349 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8076 23:03:27.227626 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8077 23:03:27.230651 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8078 23:03:27.230947 ==
8079 23:03:27.234135 Dram Type= 6, Freq= 0, CH_0, rank 1
8080 23:03:27.237103 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8081 23:03:27.240609 ==
8082 23:03:27.240931 DQS Delay:
8083 23:03:27.241164 DQS0 = 0, DQS1 = 0
8084 23:03:27.244044 DQM Delay:
8085 23:03:27.244335 DQM0 = 132, DQM1 = 125
8086 23:03:27.247147 DQ Delay:
8087 23:03:27.250491 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
8088 23:03:27.253591 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
8089 23:03:27.256804 DQ8 =115, DQ9 =111, DQ10 =131, DQ11 =119
8090 23:03:27.260522 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
8091 23:03:27.260829
8092 23:03:27.261140
8093 23:03:27.261435 ==
8094 23:03:27.263454 Dram Type= 6, Freq= 0, CH_0, rank 1
8095 23:03:27.266829 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8096 23:03:27.267138 ==
8097 23:03:27.270064
8098 23:03:27.270389
8099 23:03:27.270704 TX Vref Scan disable
8100 23:03:27.274095 == TX Byte 0 ==
8101 23:03:27.276695 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8102 23:03:27.279916 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8103 23:03:27.283671 == TX Byte 1 ==
8104 23:03:27.286568 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8105 23:03:27.289875 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8106 23:03:27.293197 ==
8107 23:03:27.293594 Dram Type= 6, Freq= 0, CH_0, rank 1
8108 23:03:27.300050 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8109 23:03:27.300555 ==
8110 23:03:27.312567
8111 23:03:27.316008 TX Vref early break, caculate TX vref
8112 23:03:27.319534 TX Vref=16, minBit 1, minWin=23, winSum=382
8113 23:03:27.322357 TX Vref=18, minBit 8, minWin=23, winSum=393
8114 23:03:27.325828 TX Vref=20, minBit 2, minWin=24, winSum=399
8115 23:03:27.329106 TX Vref=22, minBit 9, minWin=24, winSum=406
8116 23:03:27.332825 TX Vref=24, minBit 3, minWin=25, winSum=416
8117 23:03:27.339073 TX Vref=26, minBit 4, minWin=25, winSum=421
8118 23:03:27.342435 TX Vref=28, minBit 4, minWin=25, winSum=424
8119 23:03:27.345313 TX Vref=30, minBit 2, minWin=25, winSum=416
8120 23:03:27.348666 TX Vref=32, minBit 1, minWin=24, winSum=406
8121 23:03:27.352452 TX Vref=34, minBit 1, minWin=24, winSum=401
8122 23:03:27.358810 [TxChooseVref] Worse bit 4, Min win 25, Win sum 424, Final Vref 28
8123 23:03:27.359336
8124 23:03:27.362618 Final TX Range 0 Vref 28
8125 23:03:27.363039
8126 23:03:27.363388 ==
8127 23:03:27.365173 Dram Type= 6, Freq= 0, CH_0, rank 1
8128 23:03:27.368304 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8129 23:03:27.368684 ==
8130 23:03:27.368972
8131 23:03:27.369232
8132 23:03:27.371921 TX Vref Scan disable
8133 23:03:27.378241 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8134 23:03:27.378442 == TX Byte 0 ==
8135 23:03:27.381892 u2DelayCellOfst[0]=10 cells (3 PI)
8136 23:03:27.384805 u2DelayCellOfst[1]=14 cells (4 PI)
8137 23:03:27.387827 u2DelayCellOfst[2]=7 cells (2 PI)
8138 23:03:27.391327 u2DelayCellOfst[3]=10 cells (3 PI)
8139 23:03:27.394592 u2DelayCellOfst[4]=7 cells (2 PI)
8140 23:03:27.397979 u2DelayCellOfst[5]=0 cells (0 PI)
8141 23:03:27.401723 u2DelayCellOfst[6]=14 cells (4 PI)
8142 23:03:27.404515 u2DelayCellOfst[7]=14 cells (4 PI)
8143 23:03:27.408080 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8144 23:03:27.411278 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8145 23:03:27.414888 == TX Byte 1 ==
8146 23:03:27.417562 u2DelayCellOfst[8]=0 cells (0 PI)
8147 23:03:27.421414 u2DelayCellOfst[9]=0 cells (0 PI)
8148 23:03:27.421495 u2DelayCellOfst[10]=7 cells (2 PI)
8149 23:03:27.424410 u2DelayCellOfst[11]=3 cells (1 PI)
8150 23:03:27.427449 u2DelayCellOfst[12]=10 cells (3 PI)
8151 23:03:27.430943 u2DelayCellOfst[13]=10 cells (3 PI)
8152 23:03:27.434125 u2DelayCellOfst[14]=14 cells (4 PI)
8153 23:03:27.437687 u2DelayCellOfst[15]=10 cells (3 PI)
8154 23:03:27.444129 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8155 23:03:27.447540 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8156 23:03:27.447622 DramC Write-DBI on
8157 23:03:27.447728 ==
8158 23:03:27.450434 Dram Type= 6, Freq= 0, CH_0, rank 1
8159 23:03:27.457387 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8160 23:03:27.457470 ==
8161 23:03:27.457536
8162 23:03:27.457597
8163 23:03:27.460593 TX Vref Scan disable
8164 23:03:27.460675 == TX Byte 0 ==
8165 23:03:27.466996 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8166 23:03:27.467084 == TX Byte 1 ==
8167 23:03:27.470443 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8168 23:03:27.473444 DramC Write-DBI off
8169 23:03:27.473529
8170 23:03:27.473632 [DATLAT]
8171 23:03:27.476947 Freq=1600, CH0 RK1
8172 23:03:27.477054
8173 23:03:27.477146 DATLAT Default: 0xf
8174 23:03:27.480513 0, 0xFFFF, sum = 0
8175 23:03:27.480615 1, 0xFFFF, sum = 0
8176 23:03:27.483211 2, 0xFFFF, sum = 0
8177 23:03:27.483314 3, 0xFFFF, sum = 0
8178 23:03:27.487304 4, 0xFFFF, sum = 0
8179 23:03:27.490232 5, 0xFFFF, sum = 0
8180 23:03:27.490370 6, 0xFFFF, sum = 0
8181 23:03:27.493201 7, 0xFFFF, sum = 0
8182 23:03:27.493326 8, 0xFFFF, sum = 0
8183 23:03:27.496534 9, 0xFFFF, sum = 0
8184 23:03:27.496634 10, 0xFFFF, sum = 0
8185 23:03:27.500188 11, 0xFFFF, sum = 0
8186 23:03:27.500284 12, 0xFFFF, sum = 0
8187 23:03:27.503328 13, 0xFFFF, sum = 0
8188 23:03:27.503411 14, 0x0, sum = 1
8189 23:03:27.507172 15, 0x0, sum = 2
8190 23:03:27.507272 16, 0x0, sum = 3
8191 23:03:27.510133 17, 0x0, sum = 4
8192 23:03:27.510232 best_step = 15
8193 23:03:27.510343
8194 23:03:27.510422 ==
8195 23:03:27.513360 Dram Type= 6, Freq= 0, CH_0, rank 1
8196 23:03:27.516787 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8197 23:03:27.519636 ==
8198 23:03:27.519717 RX Vref Scan: 0
8199 23:03:27.519782
8200 23:03:27.523507 RX Vref 0 -> 0, step: 1
8201 23:03:27.523589
8202 23:03:27.526282 RX Delay 11 -> 252, step: 4
8203 23:03:27.529694 iDelay=187, Bit 0, Center 128 (79 ~ 178) 100
8204 23:03:27.532931 iDelay=187, Bit 1, Center 132 (79 ~ 186) 108
8205 23:03:27.536265 iDelay=187, Bit 2, Center 124 (71 ~ 178) 108
8206 23:03:27.543142 iDelay=187, Bit 3, Center 126 (75 ~ 178) 104
8207 23:03:27.546584 iDelay=187, Bit 4, Center 132 (83 ~ 182) 100
8208 23:03:27.549716 iDelay=187, Bit 5, Center 120 (67 ~ 174) 108
8209 23:03:27.552664 iDelay=187, Bit 6, Center 138 (91 ~ 186) 96
8210 23:03:27.556145 iDelay=187, Bit 7, Center 134 (83 ~ 186) 104
8211 23:03:27.562434 iDelay=187, Bit 8, Center 114 (63 ~ 166) 104
8212 23:03:27.565853 iDelay=187, Bit 9, Center 110 (59 ~ 162) 104
8213 23:03:27.569235 iDelay=187, Bit 10, Center 126 (71 ~ 182) 112
8214 23:03:27.572985 iDelay=187, Bit 11, Center 118 (67 ~ 170) 104
8215 23:03:27.575685 iDelay=187, Bit 12, Center 126 (75 ~ 178) 104
8216 23:03:27.582388 iDelay=187, Bit 13, Center 130 (79 ~ 182) 104
8217 23:03:27.585646 iDelay=187, Bit 14, Center 134 (83 ~ 186) 104
8218 23:03:27.589232 iDelay=187, Bit 15, Center 128 (75 ~ 182) 108
8219 23:03:27.589313 ==
8220 23:03:27.592682 Dram Type= 6, Freq= 0, CH_0, rank 1
8221 23:03:27.595619 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8222 23:03:27.598926 ==
8223 23:03:27.599007 DQS Delay:
8224 23:03:27.599072 DQS0 = 0, DQS1 = 0
8225 23:03:27.602150 DQM Delay:
8226 23:03:27.602245 DQM0 = 129, DQM1 = 123
8227 23:03:27.605247 DQ Delay:
8228 23:03:27.608873 DQ0 =128, DQ1 =132, DQ2 =124, DQ3 =126
8229 23:03:27.612483 DQ4 =132, DQ5 =120, DQ6 =138, DQ7 =134
8230 23:03:27.615475 DQ8 =114, DQ9 =110, DQ10 =126, DQ11 =118
8231 23:03:27.618898 DQ12 =126, DQ13 =130, DQ14 =134, DQ15 =128
8232 23:03:27.618979
8233 23:03:27.619044
8234 23:03:27.619103
8235 23:03:27.621885 [DramC_TX_OE_Calibration] TA2
8236 23:03:27.625166 Original DQ_B0 (3 6) =30, OEN = 27
8237 23:03:27.628671 Original DQ_B1 (3 6) =30, OEN = 27
8238 23:03:27.631409 24, 0x0, End_B0=24 End_B1=24
8239 23:03:27.631491 25, 0x0, End_B0=25 End_B1=25
8240 23:03:27.635121 26, 0x0, End_B0=26 End_B1=26
8241 23:03:27.638463 27, 0x0, End_B0=27 End_B1=27
8242 23:03:27.641603 28, 0x0, End_B0=28 End_B1=28
8243 23:03:27.644861 29, 0x0, End_B0=29 End_B1=29
8244 23:03:27.644944 30, 0x0, End_B0=30 End_B1=30
8245 23:03:27.648278 31, 0x4141, End_B0=30 End_B1=30
8246 23:03:27.651666 Byte0 end_step=30 best_step=27
8247 23:03:27.655042 Byte1 end_step=30 best_step=27
8248 23:03:27.658071 Byte0 TX OE(2T, 0.5T) = (3, 3)
8249 23:03:27.661212 Byte1 TX OE(2T, 0.5T) = (3, 3)
8250 23:03:27.661294
8251 23:03:27.661359
8252 23:03:27.668090 [DQSOSCAuto] RK1, (LSB)MR18= 0x1311, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 400 ps
8253 23:03:27.671263 CH0 RK1: MR19=303, MR18=1311
8254 23:03:27.677509 CH0_RK1: MR19=0x303, MR18=0x1311, DQSOSC=400, MR23=63, INC=23, DEC=15
8255 23:03:27.680997 [RxdqsGatingPostProcess] freq 1600
8256 23:03:27.684538 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8257 23:03:27.687483 best DQS0 dly(2T, 0.5T) = (1, 1)
8258 23:03:27.691225 best DQS1 dly(2T, 0.5T) = (1, 1)
8259 23:03:27.694380 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8260 23:03:27.697774 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8261 23:03:27.700482 best DQS0 dly(2T, 0.5T) = (1, 1)
8262 23:03:27.704307 best DQS1 dly(2T, 0.5T) = (1, 1)
8263 23:03:27.707738 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8264 23:03:27.710720 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8265 23:03:27.713755 Pre-setting of DQS Precalculation
8266 23:03:27.717318 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8267 23:03:27.717400 ==
8268 23:03:27.720593 Dram Type= 6, Freq= 0, CH_1, rank 0
8269 23:03:27.727242 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8270 23:03:27.727326 ==
8271 23:03:27.730652 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8272 23:03:27.736980 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8273 23:03:27.740401 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8274 23:03:27.746570 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8275 23:03:27.754630 [CA 0] Center 41 (12~71) winsize 60
8276 23:03:27.757903 [CA 1] Center 41 (11~72) winsize 62
8277 23:03:27.761494 [CA 2] Center 38 (9~67) winsize 59
8278 23:03:27.764923 [CA 3] Center 37 (8~66) winsize 59
8279 23:03:27.767840 [CA 4] Center 37 (8~67) winsize 60
8280 23:03:27.771062 [CA 5] Center 36 (6~66) winsize 61
8281 23:03:27.771153
8282 23:03:27.774352 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8283 23:03:27.774434
8284 23:03:27.780898 [CATrainingPosCal] consider 1 rank data
8285 23:03:27.780980 u2DelayCellTimex100 = 275/100 ps
8286 23:03:27.787782 CA0 delay=41 (12~71),Diff = 5 PI (17 cell)
8287 23:03:27.790919 CA1 delay=41 (11~72),Diff = 5 PI (17 cell)
8288 23:03:27.794512 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8289 23:03:27.797381 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8290 23:03:27.801338 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8291 23:03:27.803918 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
8292 23:03:27.804000
8293 23:03:27.807393 CA PerBit enable=1, Macro0, CA PI delay=36
8294 23:03:27.807475
8295 23:03:27.810842 [CBTSetCACLKResult] CA Dly = 36
8296 23:03:27.813866 CS Dly: 8 (0~39)
8297 23:03:27.817543 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8298 23:03:27.820650 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8299 23:03:27.820745 ==
8300 23:03:27.824123 Dram Type= 6, Freq= 0, CH_1, rank 1
8301 23:03:27.830120 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8302 23:03:27.830219 ==
8303 23:03:27.833985 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8304 23:03:27.840355 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8305 23:03:27.843359 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8306 23:03:27.849695 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8307 23:03:27.857873 [CA 0] Center 42 (12~72) winsize 61
8308 23:03:27.861249 [CA 1] Center 42 (13~72) winsize 60
8309 23:03:27.864204 [CA 2] Center 38 (9~68) winsize 60
8310 23:03:27.867770 [CA 3] Center 37 (7~67) winsize 61
8311 23:03:27.871174 [CA 4] Center 37 (8~67) winsize 60
8312 23:03:27.874098 [CA 5] Center 37 (7~67) winsize 61
8313 23:03:27.874205
8314 23:03:27.877614 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8315 23:03:27.877697
8316 23:03:27.884111 [CATrainingPosCal] consider 2 rank data
8317 23:03:27.884193 u2DelayCellTimex100 = 275/100 ps
8318 23:03:27.890672 CA0 delay=41 (12~71),Diff = 5 PI (17 cell)
8319 23:03:27.894343 CA1 delay=42 (13~72),Diff = 6 PI (21 cell)
8320 23:03:27.897710 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8321 23:03:27.900516 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8322 23:03:27.903862 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8323 23:03:27.907109 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8324 23:03:27.907191
8325 23:03:27.910544 CA PerBit enable=1, Macro0, CA PI delay=36
8326 23:03:27.910625
8327 23:03:27.913466 [CBTSetCACLKResult] CA Dly = 36
8328 23:03:27.916935 CS Dly: 9 (0~42)
8329 23:03:27.920405 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8330 23:03:27.923691 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8331 23:03:27.923773
8332 23:03:27.927042 ----->DramcWriteLeveling(PI) begin...
8333 23:03:27.927124 ==
8334 23:03:27.929940 Dram Type= 6, Freq= 0, CH_1, rank 0
8335 23:03:27.936977 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8336 23:03:27.937057 ==
8337 23:03:27.939995 Write leveling (Byte 0): 24 => 24
8338 23:03:27.943415 Write leveling (Byte 1): 27 => 27
8339 23:03:27.946736 DramcWriteLeveling(PI) end<-----
8340 23:03:27.946816
8341 23:03:27.946879 ==
8342 23:03:27.950240 Dram Type= 6, Freq= 0, CH_1, rank 0
8343 23:03:27.953513 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8344 23:03:27.953593 ==
8345 23:03:27.956691 [Gating] SW mode calibration
8346 23:03:27.963093 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8347 23:03:27.969632 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8348 23:03:27.973120 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8349 23:03:27.976332 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8350 23:03:27.983124 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8351 23:03:27.986077 1 4 12 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
8352 23:03:27.989406 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8353 23:03:27.996273 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8354 23:03:27.999239 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8355 23:03:28.002844 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8356 23:03:28.006166 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8357 23:03:28.012847 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8358 23:03:28.016214 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8359 23:03:28.022339 1 5 12 | B1->B0 | 3434 2c2c | 1 0 | (1 0) (0 1)
8360 23:03:28.025886 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8361 23:03:28.029308 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8362 23:03:28.035872 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8363 23:03:28.039519 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8364 23:03:28.042891 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8365 23:03:28.049338 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8366 23:03:28.052251 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8367 23:03:28.055797 1 6 12 | B1->B0 | 2424 3c3c | 0 0 | (0 0) (0 0)
8368 23:03:28.062467 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8369 23:03:28.066028 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8370 23:03:28.068951 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8371 23:03:28.075532 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8372 23:03:28.079093 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8373 23:03:28.082400 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8374 23:03:28.088554 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8375 23:03:28.092292 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8376 23:03:28.094997 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8377 23:03:28.101930 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8378 23:03:28.105002 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8379 23:03:28.108209 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8380 23:03:28.114930 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8381 23:03:28.117929 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8382 23:03:28.121442 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8383 23:03:28.127795 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8384 23:03:28.131242 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8385 23:03:28.134712 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8386 23:03:28.141638 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8387 23:03:28.144309 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8388 23:03:28.147789 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8389 23:03:28.154213 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8390 23:03:28.157719 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8391 23:03:28.161093 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8392 23:03:28.167222 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8393 23:03:28.167645 Total UI for P1: 0, mck2ui 16
8394 23:03:28.174318 best dqsien dly found for B0: ( 1, 9, 10)
8395 23:03:28.177365 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8396 23:03:28.180921 Total UI for P1: 0, mck2ui 16
8397 23:03:28.183986 best dqsien dly found for B1: ( 1, 9, 14)
8398 23:03:28.186794 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8399 23:03:28.190202 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8400 23:03:28.190321
8401 23:03:28.193786 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8402 23:03:28.196652 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8403 23:03:28.200038 [Gating] SW calibration Done
8404 23:03:28.200119 ==
8405 23:03:28.203368 Dram Type= 6, Freq= 0, CH_1, rank 0
8406 23:03:28.209743 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8407 23:03:28.209824 ==
8408 23:03:28.209889 RX Vref Scan: 0
8409 23:03:28.209949
8410 23:03:28.213143 RX Vref 0 -> 0, step: 1
8411 23:03:28.213224
8412 23:03:28.216618 RX Delay 0 -> 252, step: 8
8413 23:03:28.219835 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8414 23:03:28.222920 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8415 23:03:28.226204 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8416 23:03:28.229363 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8417 23:03:28.236913 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8418 23:03:28.239899 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8419 23:03:28.243647 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8420 23:03:28.246498 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8421 23:03:28.249830 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8422 23:03:28.256299 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8423 23:03:28.259793 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8424 23:03:28.263459 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8425 23:03:28.266131 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8426 23:03:28.272952 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8427 23:03:28.276254 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8428 23:03:28.279239 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8429 23:03:28.279771 ==
8430 23:03:28.282810 Dram Type= 6, Freq= 0, CH_1, rank 0
8431 23:03:28.285818 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8432 23:03:28.286395 ==
8433 23:03:28.289640 DQS Delay:
8434 23:03:28.290060 DQS0 = 0, DQS1 = 0
8435 23:03:28.292420 DQM Delay:
8436 23:03:28.292849 DQM0 = 134, DQM1 = 129
8437 23:03:28.295893 DQ Delay:
8438 23:03:28.299217 DQ0 =139, DQ1 =127, DQ2 =123, DQ3 =135
8439 23:03:28.302878 DQ4 =127, DQ5 =147, DQ6 =147, DQ7 =127
8440 23:03:28.305958 DQ8 =115, DQ9 =119, DQ10 =127, DQ11 =127
8441 23:03:28.309297 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =135
8442 23:03:28.309787
8443 23:03:28.310130
8444 23:03:28.310537 ==
8445 23:03:28.312636 Dram Type= 6, Freq= 0, CH_1, rank 0
8446 23:03:28.315598 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8447 23:03:28.316016 ==
8448 23:03:28.316419
8449 23:03:28.318989
8450 23:03:28.319405 TX Vref Scan disable
8451 23:03:28.322496 == TX Byte 0 ==
8452 23:03:28.326298 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8453 23:03:28.328759 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8454 23:03:28.332184 == TX Byte 1 ==
8455 23:03:28.335387 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8456 23:03:28.339118 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8457 23:03:28.339512 ==
8458 23:03:28.342169 Dram Type= 6, Freq= 0, CH_1, rank 0
8459 23:03:28.348468 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8460 23:03:28.348893 ==
8461 23:03:28.361466
8462 23:03:28.365238 TX Vref early break, caculate TX vref
8463 23:03:28.368212 TX Vref=16, minBit 8, minWin=21, winSum=368
8464 23:03:28.371610 TX Vref=18, minBit 9, minWin=22, winSum=377
8465 23:03:28.374666 TX Vref=20, minBit 8, minWin=23, winSum=387
8466 23:03:28.378105 TX Vref=22, minBit 8, minWin=23, winSum=396
8467 23:03:28.380918 TX Vref=24, minBit 9, minWin=24, winSum=409
8468 23:03:28.387822 TX Vref=26, minBit 1, minWin=25, winSum=412
8469 23:03:28.391280 TX Vref=28, minBit 0, minWin=25, winSum=415
8470 23:03:28.394029 TX Vref=30, minBit 0, minWin=25, winSum=414
8471 23:03:28.398046 TX Vref=32, minBit 9, minWin=24, winSum=404
8472 23:03:28.400876 TX Vref=34, minBit 11, minWin=23, winSum=394
8473 23:03:28.407857 TX Vref=36, minBit 9, minWin=22, winSum=390
8474 23:03:28.410798 [TxChooseVref] Worse bit 0, Min win 25, Win sum 415, Final Vref 28
8475 23:03:28.411217
8476 23:03:28.414238 Final TX Range 0 Vref 28
8477 23:03:28.414721
8478 23:03:28.415056 ==
8479 23:03:28.417716 Dram Type= 6, Freq= 0, CH_1, rank 0
8480 23:03:28.420647 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8481 23:03:28.424323 ==
8482 23:03:28.424820
8483 23:03:28.425206
8484 23:03:28.425543 TX Vref Scan disable
8485 23:03:28.431172 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8486 23:03:28.431649 == TX Byte 0 ==
8487 23:03:28.433905 u2DelayCellOfst[0]=14 cells (4 PI)
8488 23:03:28.437636 u2DelayCellOfst[1]=7 cells (2 PI)
8489 23:03:28.440369 u2DelayCellOfst[2]=0 cells (0 PI)
8490 23:03:28.443762 u2DelayCellOfst[3]=3 cells (1 PI)
8491 23:03:28.446987 u2DelayCellOfst[4]=7 cells (2 PI)
8492 23:03:28.450114 u2DelayCellOfst[5]=14 cells (4 PI)
8493 23:03:28.453530 u2DelayCellOfst[6]=14 cells (4 PI)
8494 23:03:28.456990 u2DelayCellOfst[7]=3 cells (1 PI)
8495 23:03:28.460035 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8496 23:03:28.463720 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8497 23:03:28.466743 == TX Byte 1 ==
8498 23:03:28.470530 u2DelayCellOfst[8]=0 cells (0 PI)
8499 23:03:28.473597 u2DelayCellOfst[9]=3 cells (1 PI)
8500 23:03:28.476639 u2DelayCellOfst[10]=14 cells (4 PI)
8501 23:03:28.480341 u2DelayCellOfst[11]=7 cells (2 PI)
8502 23:03:28.483537 u2DelayCellOfst[12]=14 cells (4 PI)
8503 23:03:28.486761 u2DelayCellOfst[13]=14 cells (4 PI)
8504 23:03:28.490139 u2DelayCellOfst[14]=17 cells (5 PI)
8505 23:03:28.493459 u2DelayCellOfst[15]=17 cells (5 PI)
8506 23:03:28.496335 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8507 23:03:28.499620 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8508 23:03:28.502803 DramC Write-DBI on
8509 23:03:28.503218 ==
8510 23:03:28.506209 Dram Type= 6, Freq= 0, CH_1, rank 0
8511 23:03:28.509898 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8512 23:03:28.510363 ==
8513 23:03:28.510704
8514 23:03:28.511081
8515 23:03:28.512632 TX Vref Scan disable
8516 23:03:28.513048 == TX Byte 0 ==
8517 23:03:28.519323 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8518 23:03:28.519733 == TX Byte 1 ==
8519 23:03:28.526082 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8520 23:03:28.526484 DramC Write-DBI off
8521 23:03:28.526847
8522 23:03:28.527147 [DATLAT]
8523 23:03:28.529523 Freq=1600, CH1 RK0
8524 23:03:28.529893
8525 23:03:28.532895 DATLAT Default: 0xf
8526 23:03:28.533320 0, 0xFFFF, sum = 0
8527 23:03:28.535654 1, 0xFFFF, sum = 0
8528 23:03:28.536080 2, 0xFFFF, sum = 0
8529 23:03:28.539254 3, 0xFFFF, sum = 0
8530 23:03:28.539672 4, 0xFFFF, sum = 0
8531 23:03:28.542784 5, 0xFFFF, sum = 0
8532 23:03:28.543207 6, 0xFFFF, sum = 0
8533 23:03:28.546540 7, 0xFFFF, sum = 0
8534 23:03:28.546965 8, 0xFFFF, sum = 0
8535 23:03:28.549410 9, 0xFFFF, sum = 0
8536 23:03:28.549831 10, 0xFFFF, sum = 0
8537 23:03:28.552997 11, 0xFFFF, sum = 0
8538 23:03:28.553421 12, 0xFFFF, sum = 0
8539 23:03:28.555781 13, 0xFFFF, sum = 0
8540 23:03:28.556206 14, 0x0, sum = 1
8541 23:03:28.559134 15, 0x0, sum = 2
8542 23:03:28.559557 16, 0x0, sum = 3
8543 23:03:28.562002 17, 0x0, sum = 4
8544 23:03:28.562466 best_step = 15
8545 23:03:28.562804
8546 23:03:28.563117 ==
8547 23:03:28.565396 Dram Type= 6, Freq= 0, CH_1, rank 0
8548 23:03:28.572330 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8549 23:03:28.572749 ==
8550 23:03:28.573082 RX Vref Scan: 1
8551 23:03:28.573388
8552 23:03:28.575629 Set Vref Range= 24 -> 127
8553 23:03:28.576046
8554 23:03:28.578867 RX Vref 24 -> 127, step: 1
8555 23:03:28.579286
8556 23:03:28.581681 RX Delay 19 -> 252, step: 4
8557 23:03:28.582179
8558 23:03:28.585610 Set Vref, RX VrefLevel [Byte0]: 24
8559 23:03:28.588288 [Byte1]: 24
8560 23:03:28.588891
8561 23:03:28.591629 Set Vref, RX VrefLevel [Byte0]: 25
8562 23:03:28.595034 [Byte1]: 25
8563 23:03:28.595530
8564 23:03:28.598132 Set Vref, RX VrefLevel [Byte0]: 26
8565 23:03:28.601732 [Byte1]: 26
8566 23:03:28.605198
8567 23:03:28.605618 Set Vref, RX VrefLevel [Byte0]: 27
8568 23:03:28.608431 [Byte1]: 27
8569 23:03:28.612690
8570 23:03:28.613136 Set Vref, RX VrefLevel [Byte0]: 28
8571 23:03:28.616337 [Byte1]: 28
8572 23:03:28.620057
8573 23:03:28.620469 Set Vref, RX VrefLevel [Byte0]: 29
8574 23:03:28.623276 [Byte1]: 29
8575 23:03:28.627574
8576 23:03:28.628044 Set Vref, RX VrefLevel [Byte0]: 30
8577 23:03:28.631116 [Byte1]: 30
8578 23:03:28.635572
8579 23:03:28.635986 Set Vref, RX VrefLevel [Byte0]: 31
8580 23:03:28.638517 [Byte1]: 31
8581 23:03:28.642544
8582 23:03:28.642954 Set Vref, RX VrefLevel [Byte0]: 32
8583 23:03:28.646065 [Byte1]: 32
8584 23:03:28.650360
8585 23:03:28.650777 Set Vref, RX VrefLevel [Byte0]: 33
8586 23:03:28.654031 [Byte1]: 33
8587 23:03:28.658175
8588 23:03:28.658620 Set Vref, RX VrefLevel [Byte0]: 34
8589 23:03:28.660949 [Byte1]: 34
8590 23:03:28.665671
8591 23:03:28.666085 Set Vref, RX VrefLevel [Byte0]: 35
8592 23:03:28.669116 [Byte1]: 35
8593 23:03:28.673151
8594 23:03:28.673642 Set Vref, RX VrefLevel [Byte0]: 36
8595 23:03:28.676520 [Byte1]: 36
8596 23:03:28.680905
8597 23:03:28.681449 Set Vref, RX VrefLevel [Byte0]: 37
8598 23:03:28.684057 [Byte1]: 37
8599 23:03:28.688511
8600 23:03:28.688926 Set Vref, RX VrefLevel [Byte0]: 38
8601 23:03:28.691445 [Byte1]: 38
8602 23:03:28.696171
8603 23:03:28.696657 Set Vref, RX VrefLevel [Byte0]: 39
8604 23:03:28.699153 [Byte1]: 39
8605 23:03:28.703461
8606 23:03:28.703875 Set Vref, RX VrefLevel [Byte0]: 40
8607 23:03:28.706466 [Byte1]: 40
8608 23:03:28.710885
8609 23:03:28.711423 Set Vref, RX VrefLevel [Byte0]: 41
8610 23:03:28.714214 [Byte1]: 41
8611 23:03:28.718347
8612 23:03:28.718760 Set Vref, RX VrefLevel [Byte0]: 42
8613 23:03:28.721733 [Byte1]: 42
8614 23:03:28.726343
8615 23:03:28.726803 Set Vref, RX VrefLevel [Byte0]: 43
8616 23:03:28.729651 [Byte1]: 43
8617 23:03:28.733417
8618 23:03:28.733832 Set Vref, RX VrefLevel [Byte0]: 44
8619 23:03:28.736665 [Byte1]: 44
8620 23:03:28.741363
8621 23:03:28.741778 Set Vref, RX VrefLevel [Byte0]: 45
8622 23:03:28.744672 [Byte1]: 45
8623 23:03:28.748974
8624 23:03:28.749391 Set Vref, RX VrefLevel [Byte0]: 46
8625 23:03:28.752019 [Byte1]: 46
8626 23:03:28.756829
8627 23:03:28.757241 Set Vref, RX VrefLevel [Byte0]: 47
8628 23:03:28.759390 [Byte1]: 47
8629 23:03:28.764109
8630 23:03:28.764472 Set Vref, RX VrefLevel [Byte0]: 48
8631 23:03:28.767074 [Byte1]: 48
8632 23:03:28.771705
8633 23:03:28.772072 Set Vref, RX VrefLevel [Byte0]: 49
8634 23:03:28.774800 [Byte1]: 49
8635 23:03:28.778810
8636 23:03:28.779358 Set Vref, RX VrefLevel [Byte0]: 50
8637 23:03:28.782177 [Byte1]: 50
8638 23:03:28.786724
8639 23:03:28.787135 Set Vref, RX VrefLevel [Byte0]: 51
8640 23:03:28.789815 [Byte1]: 51
8641 23:03:28.794278
8642 23:03:28.794698 Set Vref, RX VrefLevel [Byte0]: 52
8643 23:03:28.797596 [Byte1]: 52
8644 23:03:28.801641
8645 23:03:28.802235 Set Vref, RX VrefLevel [Byte0]: 53
8646 23:03:28.805311 [Byte1]: 53
8647 23:03:28.809826
8648 23:03:28.810244 Set Vref, RX VrefLevel [Byte0]: 54
8649 23:03:28.813051 [Byte1]: 54
8650 23:03:28.816836
8651 23:03:28.817294 Set Vref, RX VrefLevel [Byte0]: 55
8652 23:03:28.820381 [Byte1]: 55
8653 23:03:28.824702
8654 23:03:28.825126 Set Vref, RX VrefLevel [Byte0]: 56
8655 23:03:28.827640 [Byte1]: 56
8656 23:03:28.832213
8657 23:03:28.832636 Set Vref, RX VrefLevel [Byte0]: 57
8658 23:03:28.835843 [Byte1]: 57
8659 23:03:28.839657
8660 23:03:28.840096 Set Vref, RX VrefLevel [Byte0]: 58
8661 23:03:28.842887 [Byte1]: 58
8662 23:03:28.846970
8663 23:03:28.847407 Set Vref, RX VrefLevel [Byte0]: 59
8664 23:03:28.850283 [Byte1]: 59
8665 23:03:28.854968
8666 23:03:28.855518 Set Vref, RX VrefLevel [Byte0]: 60
8667 23:03:28.861482 [Byte1]: 60
8668 23:03:28.861924
8669 23:03:28.864536 Set Vref, RX VrefLevel [Byte0]: 61
8670 23:03:28.867998 [Byte1]: 61
8671 23:03:28.868431
8672 23:03:28.871136 Set Vref, RX VrefLevel [Byte0]: 62
8673 23:03:28.874775 [Byte1]: 62
8674 23:03:28.875206
8675 23:03:28.878158 Set Vref, RX VrefLevel [Byte0]: 63
8676 23:03:28.880766 [Byte1]: 63
8677 23:03:28.885077
8678 23:03:28.885579 Set Vref, RX VrefLevel [Byte0]: 64
8679 23:03:28.888779 [Byte1]: 64
8680 23:03:28.892962
8681 23:03:28.893398 Set Vref, RX VrefLevel [Byte0]: 65
8682 23:03:28.895834 [Byte1]: 65
8683 23:03:28.900593
8684 23:03:28.901003 Set Vref, RX VrefLevel [Byte0]: 66
8685 23:03:28.903175 [Byte1]: 66
8686 23:03:28.907767
8687 23:03:28.908177 Set Vref, RX VrefLevel [Byte0]: 67
8688 23:03:28.911191 [Byte1]: 67
8689 23:03:28.915171
8690 23:03:28.915612 Set Vref, RX VrefLevel [Byte0]: 68
8691 23:03:28.918728 [Byte1]: 68
8692 23:03:28.922824
8693 23:03:28.923241 Set Vref, RX VrefLevel [Byte0]: 69
8694 23:03:28.926007 [Byte1]: 69
8695 23:03:28.930531
8696 23:03:28.930946 Set Vref, RX VrefLevel [Byte0]: 70
8697 23:03:28.933611 [Byte1]: 70
8698 23:03:28.938357
8699 23:03:28.939035 Set Vref, RX VrefLevel [Byte0]: 71
8700 23:03:28.941356 [Byte1]: 71
8701 23:03:28.945904
8702 23:03:28.946472 Final RX Vref Byte 0 = 55 to rank0
8703 23:03:28.949375 Final RX Vref Byte 1 = 56 to rank0
8704 23:03:28.952031 Final RX Vref Byte 0 = 55 to rank1
8705 23:03:28.955565 Final RX Vref Byte 1 = 56 to rank1==
8706 23:03:28.959132 Dram Type= 6, Freq= 0, CH_1, rank 0
8707 23:03:28.965438 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8708 23:03:28.965852 ==
8709 23:03:28.966215 DQS Delay:
8710 23:03:28.968697 DQS0 = 0, DQS1 = 0
8711 23:03:28.969125 DQM Delay:
8712 23:03:28.969468 DQM0 = 132, DQM1 = 127
8713 23:03:28.971915 DQ Delay:
8714 23:03:28.975365 DQ0 =140, DQ1 =128, DQ2 =118, DQ3 =132
8715 23:03:28.978317 DQ4 =126, DQ5 =144, DQ6 =144, DQ7 =126
8716 23:03:28.981780 DQ8 =112, DQ9 =116, DQ10 =128, DQ11 =122
8717 23:03:28.985307 DQ12 =136, DQ13 =136, DQ14 =134, DQ15 =138
8718 23:03:28.985725
8719 23:03:28.986054
8720 23:03:28.986406
8721 23:03:28.988118 [DramC_TX_OE_Calibration] TA2
8722 23:03:28.991759 Original DQ_B0 (3 6) =30, OEN = 27
8723 23:03:28.994856 Original DQ_B1 (3 6) =30, OEN = 27
8724 23:03:28.998081 24, 0x0, End_B0=24 End_B1=24
8725 23:03:29.001408 25, 0x0, End_B0=25 End_B1=25
8726 23:03:29.001867 26, 0x0, End_B0=26 End_B1=26
8727 23:03:29.004798 27, 0x0, End_B0=27 End_B1=27
8728 23:03:29.008384 28, 0x0, End_B0=28 End_B1=28
8729 23:03:29.011412 29, 0x0, End_B0=29 End_B1=29
8730 23:03:29.011923 30, 0x0, End_B0=30 End_B1=30
8731 23:03:29.014435 31, 0x4141, End_B0=30 End_B1=30
8732 23:03:29.017794 Byte0 end_step=30 best_step=27
8733 23:03:29.021402 Byte1 end_step=30 best_step=27
8734 23:03:29.024360 Byte0 TX OE(2T, 0.5T) = (3, 3)
8735 23:03:29.028094 Byte1 TX OE(2T, 0.5T) = (3, 3)
8736 23:03:29.028484
8737 23:03:29.028912
8738 23:03:29.034432 [DQSOSCAuto] RK0, (LSB)MR18= 0xd17, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 403 ps
8739 23:03:29.037961 CH1 RK0: MR19=303, MR18=D17
8740 23:03:29.044185 CH1_RK0: MR19=0x303, MR18=0xD17, DQSOSC=398, MR23=63, INC=23, DEC=15
8741 23:03:29.044572
8742 23:03:29.047774 ----->DramcWriteLeveling(PI) begin...
8743 23:03:29.048226 ==
8744 23:03:29.050509 Dram Type= 6, Freq= 0, CH_1, rank 1
8745 23:03:29.053994 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8746 23:03:29.054442 ==
8747 23:03:29.057203 Write leveling (Byte 0): 24 => 24
8748 23:03:29.060887 Write leveling (Byte 1): 26 => 26
8749 23:03:29.064052 DramcWriteLeveling(PI) end<-----
8750 23:03:29.064481
8751 23:03:29.064935 ==
8752 23:03:29.066896 Dram Type= 6, Freq= 0, CH_1, rank 1
8753 23:03:29.073674 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8754 23:03:29.074128 ==
8755 23:03:29.074593 [Gating] SW mode calibration
8756 23:03:29.083630 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8757 23:03:29.086726 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8758 23:03:29.090406 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8759 23:03:29.096827 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8760 23:03:29.099882 1 4 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8761 23:03:29.106789 1 4 12 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
8762 23:03:29.109926 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8763 23:03:29.113645 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8764 23:03:29.119835 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8765 23:03:29.123537 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8766 23:03:29.126806 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8767 23:03:29.133289 1 5 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8768 23:03:29.136562 1 5 8 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
8769 23:03:29.140172 1 5 12 | B1->B0 | 3333 2323 | 0 0 | (0 1) (1 0)
8770 23:03:29.146473 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8771 23:03:29.149377 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8772 23:03:29.152955 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8773 23:03:29.159173 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8774 23:03:29.163623 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8775 23:03:29.166018 1 6 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8776 23:03:29.172379 1 6 8 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8777 23:03:29.175918 1 6 12 | B1->B0 | 3030 4646 | 0 0 | (0 0) (0 0)
8778 23:03:29.179178 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8779 23:03:29.186337 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8780 23:03:29.188889 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8781 23:03:29.192331 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8782 23:03:29.199138 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8783 23:03:29.202484 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8784 23:03:29.205750 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8785 23:03:29.212127 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8786 23:03:29.215226 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8787 23:03:29.219075 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8788 23:03:29.225758 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8789 23:03:29.229063 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8790 23:03:29.232227 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8791 23:03:29.235372 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8792 23:03:29.241688 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8793 23:03:29.245669 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8794 23:03:29.251828 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8795 23:03:29.255013 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8796 23:03:29.258289 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8797 23:03:29.261629 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8798 23:03:29.268597 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8799 23:03:29.271458 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8800 23:03:29.274725 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8801 23:03:29.281598 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8802 23:03:29.284555 Total UI for P1: 0, mck2ui 16
8803 23:03:29.288240 best dqsien dly found for B0: ( 1, 9, 6)
8804 23:03:29.291018 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8805 23:03:29.294621 Total UI for P1: 0, mck2ui 16
8806 23:03:29.298007 best dqsien dly found for B1: ( 1, 9, 10)
8807 23:03:29.301166 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8808 23:03:29.304594 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8809 23:03:29.305023
8810 23:03:29.307815 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8811 23:03:29.314525 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8812 23:03:29.314969 [Gating] SW calibration Done
8813 23:03:29.315409 ==
8814 23:03:29.317507 Dram Type= 6, Freq= 0, CH_1, rank 1
8815 23:03:29.324677 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8816 23:03:29.325112 ==
8817 23:03:29.325555 RX Vref Scan: 0
8818 23:03:29.325974
8819 23:03:29.327851 RX Vref 0 -> 0, step: 1
8820 23:03:29.328267
8821 23:03:29.330967 RX Delay 0 -> 252, step: 8
8822 23:03:29.333740 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8823 23:03:29.337236 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8824 23:03:29.340907 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8825 23:03:29.347421 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8826 23:03:29.350504 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8827 23:03:29.354082 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8828 23:03:29.357023 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8829 23:03:29.360109 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8830 23:03:29.367095 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8831 23:03:29.370507 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8832 23:03:29.373602 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8833 23:03:29.377075 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8834 23:03:29.383383 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8835 23:03:29.386604 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8836 23:03:29.389882 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8837 23:03:29.393211 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8838 23:03:29.393780 ==
8839 23:03:29.396753 Dram Type= 6, Freq= 0, CH_1, rank 1
8840 23:03:29.402996 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8841 23:03:29.403587 ==
8842 23:03:29.404109 DQS Delay:
8843 23:03:29.406367 DQS0 = 0, DQS1 = 0
8844 23:03:29.406853 DQM Delay:
8845 23:03:29.407294 DQM0 = 133, DQM1 = 130
8846 23:03:29.409785 DQ Delay:
8847 23:03:29.412912 DQ0 =135, DQ1 =131, DQ2 =123, DQ3 =131
8848 23:03:29.416701 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =131
8849 23:03:29.419963 DQ8 =115, DQ9 =119, DQ10 =135, DQ11 =123
8850 23:03:29.423061 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8851 23:03:29.423372
8852 23:03:29.423687
8853 23:03:29.423985 ==
8854 23:03:29.426183 Dram Type= 6, Freq= 0, CH_1, rank 1
8855 23:03:29.429620 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8856 23:03:29.433521 ==
8857 23:03:29.433846
8858 23:03:29.434162
8859 23:03:29.434497 TX Vref Scan disable
8860 23:03:29.436245 == TX Byte 0 ==
8861 23:03:29.439198 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8862 23:03:29.442611 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8863 23:03:29.445948 == TX Byte 1 ==
8864 23:03:29.449616 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8865 23:03:29.452700 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8866 23:03:29.456143 ==
8867 23:03:29.459321 Dram Type= 6, Freq= 0, CH_1, rank 1
8868 23:03:29.462543 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8869 23:03:29.462854 ==
8870 23:03:29.475711
8871 23:03:29.479024 TX Vref early break, caculate TX vref
8872 23:03:29.482483 TX Vref=16, minBit 9, minWin=22, winSum=381
8873 23:03:29.485566 TX Vref=18, minBit 9, minWin=22, winSum=388
8874 23:03:29.488652 TX Vref=20, minBit 9, minWin=22, winSum=390
8875 23:03:29.492181 TX Vref=22, minBit 9, minWin=22, winSum=402
8876 23:03:29.495598 TX Vref=24, minBit 9, minWin=23, winSum=409
8877 23:03:29.501786 TX Vref=26, minBit 9, minWin=24, winSum=416
8878 23:03:29.505513 TX Vref=28, minBit 9, minWin=25, winSum=419
8879 23:03:29.508533 TX Vref=30, minBit 9, minWin=24, winSum=414
8880 23:03:29.512212 TX Vref=32, minBit 9, minWin=24, winSum=406
8881 23:03:29.515369 TX Vref=34, minBit 0, minWin=24, winSum=400
8882 23:03:29.521740 TX Vref=36, minBit 9, minWin=23, winSum=395
8883 23:03:29.525016 [TxChooseVref] Worse bit 9, Min win 25, Win sum 419, Final Vref 28
8884 23:03:29.525450
8885 23:03:29.528300 Final TX Range 0 Vref 28
8886 23:03:29.528742
8887 23:03:29.529194 ==
8888 23:03:29.531640 Dram Type= 6, Freq= 0, CH_1, rank 1
8889 23:03:29.534874 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8890 23:03:29.537700 ==
8891 23:03:29.538133
8892 23:03:29.538601
8893 23:03:29.539021 TX Vref Scan disable
8894 23:03:29.545187 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8895 23:03:29.545623 == TX Byte 0 ==
8896 23:03:29.548214 u2DelayCellOfst[0]=14 cells (4 PI)
8897 23:03:29.551054 u2DelayCellOfst[1]=10 cells (3 PI)
8898 23:03:29.554609 u2DelayCellOfst[2]=0 cells (0 PI)
8899 23:03:29.557933 u2DelayCellOfst[3]=7 cells (2 PI)
8900 23:03:29.561427 u2DelayCellOfst[4]=7 cells (2 PI)
8901 23:03:29.564822 u2DelayCellOfst[5]=14 cells (4 PI)
8902 23:03:29.568382 u2DelayCellOfst[6]=14 cells (4 PI)
8903 23:03:29.571156 u2DelayCellOfst[7]=7 cells (2 PI)
8904 23:03:29.574718 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8905 23:03:29.577517 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8906 23:03:29.580911 == TX Byte 1 ==
8907 23:03:29.583938 u2DelayCellOfst[8]=0 cells (0 PI)
8908 23:03:29.587290 u2DelayCellOfst[9]=7 cells (2 PI)
8909 23:03:29.591123 u2DelayCellOfst[10]=14 cells (4 PI)
8910 23:03:29.594102 u2DelayCellOfst[11]=10 cells (3 PI)
8911 23:03:29.597430 u2DelayCellOfst[12]=14 cells (4 PI)
8912 23:03:29.600589 u2DelayCellOfst[13]=17 cells (5 PI)
8913 23:03:29.604261 u2DelayCellOfst[14]=21 cells (6 PI)
8914 23:03:29.607279 u2DelayCellOfst[15]=21 cells (6 PI)
8915 23:03:29.610560 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8916 23:03:29.613984 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8917 23:03:29.617218 DramC Write-DBI on
8918 23:03:29.617789 ==
8919 23:03:29.620471 Dram Type= 6, Freq= 0, CH_1, rank 1
8920 23:03:29.624058 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8921 23:03:29.624567 ==
8922 23:03:29.624907
8923 23:03:29.625215
8924 23:03:29.627059 TX Vref Scan disable
8925 23:03:29.630339 == TX Byte 0 ==
8926 23:03:29.633871 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8927 23:03:29.634458 == TX Byte 1 ==
8928 23:03:29.640276 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8929 23:03:29.640863 DramC Write-DBI off
8930 23:03:29.641353
8931 23:03:29.641706 [DATLAT]
8932 23:03:29.643427 Freq=1600, CH1 RK1
8933 23:03:29.643842
8934 23:03:29.646843 DATLAT Default: 0xf
8935 23:03:29.647421 0, 0xFFFF, sum = 0
8936 23:03:29.650005 1, 0xFFFF, sum = 0
8937 23:03:29.650467 2, 0xFFFF, sum = 0
8938 23:03:29.653173 3, 0xFFFF, sum = 0
8939 23:03:29.653678 4, 0xFFFF, sum = 0
8940 23:03:29.656361 5, 0xFFFF, sum = 0
8941 23:03:29.656800 6, 0xFFFF, sum = 0
8942 23:03:29.659873 7, 0xFFFF, sum = 0
8943 23:03:29.660317 8, 0xFFFF, sum = 0
8944 23:03:29.663361 9, 0xFFFF, sum = 0
8945 23:03:29.663799 10, 0xFFFF, sum = 0
8946 23:03:29.666345 11, 0xFFFF, sum = 0
8947 23:03:29.666787 12, 0xFFFF, sum = 0
8948 23:03:29.669742 13, 0xFFFF, sum = 0
8949 23:03:29.673201 14, 0x0, sum = 1
8950 23:03:29.673642 15, 0x0, sum = 2
8951 23:03:29.674092 16, 0x0, sum = 3
8952 23:03:29.675914 17, 0x0, sum = 4
8953 23:03:29.676353 best_step = 15
8954 23:03:29.676790
8955 23:03:29.679458 ==
8956 23:03:29.679891 Dram Type= 6, Freq= 0, CH_1, rank 1
8957 23:03:29.686145 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8958 23:03:29.686648 ==
8959 23:03:29.687093 RX Vref Scan: 0
8960 23:03:29.687512
8961 23:03:29.689936 RX Vref 0 -> 0, step: 1
8962 23:03:29.690409
8963 23:03:29.693141 RX Delay 11 -> 252, step: 4
8964 23:03:29.695988 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
8965 23:03:29.699132 iDelay=195, Bit 1, Center 128 (75 ~ 182) 108
8966 23:03:29.705930 iDelay=195, Bit 2, Center 120 (67 ~ 174) 108
8967 23:03:29.709111 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8968 23:03:29.712570 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
8969 23:03:29.715917 iDelay=195, Bit 5, Center 142 (91 ~ 194) 104
8970 23:03:29.719034 iDelay=195, Bit 6, Center 140 (87 ~ 194) 108
8971 23:03:29.725397 iDelay=195, Bit 7, Center 128 (75 ~ 182) 108
8972 23:03:29.729248 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8973 23:03:29.732307 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8974 23:03:29.735774 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8975 23:03:29.741828 iDelay=195, Bit 11, Center 122 (67 ~ 178) 112
8976 23:03:29.745157 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
8977 23:03:29.748611 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8978 23:03:29.751667 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
8979 23:03:29.754841 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
8980 23:03:29.758724 ==
8981 23:03:29.761871 Dram Type= 6, Freq= 0, CH_1, rank 1
8982 23:03:29.765150 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8983 23:03:29.765568 ==
8984 23:03:29.765969 DQS Delay:
8985 23:03:29.768698 DQS0 = 0, DQS1 = 0
8986 23:03:29.769110 DQM Delay:
8987 23:03:29.771544 DQM0 = 131, DQM1 = 128
8988 23:03:29.771960 DQ Delay:
8989 23:03:29.775154 DQ0 =134, DQ1 =128, DQ2 =120, DQ3 =128
8990 23:03:29.778230 DQ4 =130, DQ5 =142, DQ6 =140, DQ7 =128
8991 23:03:29.782013 DQ8 =114, DQ9 =118, DQ10 =128, DQ11 =122
8992 23:03:29.784803 DQ12 =136, DQ13 =136, DQ14 =132, DQ15 =138
8993 23:03:29.785214
8994 23:03:29.785545
8995 23:03:29.785970
8996 23:03:29.788302 [DramC_TX_OE_Calibration] TA2
8997 23:03:29.791323 Original DQ_B0 (3 6) =30, OEN = 27
8998 23:03:29.794793 Original DQ_B1 (3 6) =30, OEN = 27
8999 23:03:29.797936 24, 0x0, End_B0=24 End_B1=24
9000 23:03:29.801180 25, 0x0, End_B0=25 End_B1=25
9001 23:03:29.804380 26, 0x0, End_B0=26 End_B1=26
9002 23:03:29.804804 27, 0x0, End_B0=27 End_B1=27
9003 23:03:29.807815 28, 0x0, End_B0=28 End_B1=28
9004 23:03:29.811087 29, 0x0, End_B0=29 End_B1=29
9005 23:03:29.814554 30, 0x0, End_B0=30 End_B1=30
9006 23:03:29.817373 31, 0x5151, End_B0=30 End_B1=30
9007 23:03:29.817799 Byte0 end_step=30 best_step=27
9008 23:03:29.821165 Byte1 end_step=30 best_step=27
9009 23:03:29.824250 Byte0 TX OE(2T, 0.5T) = (3, 3)
9010 23:03:29.827194 Byte1 TX OE(2T, 0.5T) = (3, 3)
9011 23:03:29.827607
9012 23:03:29.827935
9013 23:03:29.837546 [DQSOSCAuto] RK1, (LSB)MR18= 0x101e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 401 ps
9014 23:03:29.837969 CH1 RK1: MR19=303, MR18=101E
9015 23:03:29.843846 CH1_RK1: MR19=0x303, MR18=0x101E, DQSOSC=394, MR23=63, INC=23, DEC=15
9016 23:03:29.847014 [RxdqsGatingPostProcess] freq 1600
9017 23:03:29.853441 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9018 23:03:29.857042 best DQS0 dly(2T, 0.5T) = (1, 1)
9019 23:03:29.860403 best DQS1 dly(2T, 0.5T) = (1, 1)
9020 23:03:29.863736 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9021 23:03:29.866914 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9022 23:03:29.867337 best DQS0 dly(2T, 0.5T) = (1, 1)
9023 23:03:29.870209 best DQS1 dly(2T, 0.5T) = (1, 1)
9024 23:03:29.873639 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9025 23:03:29.876596 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9026 23:03:29.879895 Pre-setting of DQS Precalculation
9027 23:03:29.886503 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9028 23:03:29.892886 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9029 23:03:29.899640 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9030 23:03:29.899794
9031 23:03:29.899915
9032 23:03:29.903272 [Calibration Summary] 3200 Mbps
9033 23:03:29.903429 CH 0, Rank 0
9034 23:03:29.906134 SW Impedance : PASS
9035 23:03:29.909496 DUTY Scan : NO K
9036 23:03:29.909702 ZQ Calibration : PASS
9037 23:03:29.912671 Jitter Meter : NO K
9038 23:03:29.916991 CBT Training : PASS
9039 23:03:29.917524 Write leveling : PASS
9040 23:03:29.919969 RX DQS gating : PASS
9041 23:03:29.922935 RX DQ/DQS(RDDQC) : PASS
9042 23:03:29.923355 TX DQ/DQS : PASS
9043 23:03:29.926473 RX DATLAT : PASS
9044 23:03:29.929520 RX DQ/DQS(Engine): PASS
9045 23:03:29.929748 TX OE : PASS
9046 23:03:29.932894 All Pass.
9047 23:03:29.933123
9048 23:03:29.933305 CH 0, Rank 1
9049 23:03:29.935508 SW Impedance : PASS
9050 23:03:29.935690 DUTY Scan : NO K
9051 23:03:29.938995 ZQ Calibration : PASS
9052 23:03:29.942757 Jitter Meter : NO K
9053 23:03:29.942909 CBT Training : PASS
9054 23:03:29.945890 Write leveling : PASS
9055 23:03:29.948987 RX DQS gating : PASS
9056 23:03:29.949119 RX DQ/DQS(RDDQC) : PASS
9057 23:03:29.952628 TX DQ/DQS : PASS
9058 23:03:29.955865 RX DATLAT : PASS
9059 23:03:29.955979 RX DQ/DQS(Engine): PASS
9060 23:03:29.958714 TX OE : PASS
9061 23:03:29.958829 All Pass.
9062 23:03:29.958920
9063 23:03:29.962159 CH 1, Rank 0
9064 23:03:29.962317 SW Impedance : PASS
9065 23:03:29.965392 DUTY Scan : NO K
9066 23:03:29.969386 ZQ Calibration : PASS
9067 23:03:29.969506 Jitter Meter : NO K
9068 23:03:29.971955 CBT Training : PASS
9069 23:03:29.972072 Write leveling : PASS
9070 23:03:29.975125 RX DQS gating : PASS
9071 23:03:29.978528 RX DQ/DQS(RDDQC) : PASS
9072 23:03:29.978647 TX DQ/DQS : PASS
9073 23:03:29.981823 RX DATLAT : PASS
9074 23:03:29.984817 RX DQ/DQS(Engine): PASS
9075 23:03:29.984935 TX OE : PASS
9076 23:03:29.988214 All Pass.
9077 23:03:29.988334
9078 23:03:29.988454 CH 1, Rank 1
9079 23:03:29.991609 SW Impedance : PASS
9080 23:03:29.991727 DUTY Scan : NO K
9081 23:03:29.994817 ZQ Calibration : PASS
9082 23:03:29.997918 Jitter Meter : NO K
9083 23:03:29.998003 CBT Training : PASS
9084 23:03:30.001476 Write leveling : PASS
9085 23:03:30.004539 RX DQS gating : PASS
9086 23:03:30.004623 RX DQ/DQS(RDDQC) : PASS
9087 23:03:30.007700 TX DQ/DQS : PASS
9088 23:03:30.011619 RX DATLAT : PASS
9089 23:03:30.011701 RX DQ/DQS(Engine): PASS
9090 23:03:30.014841 TX OE : PASS
9091 23:03:30.014924 All Pass.
9092 23:03:30.014990
9093 23:03:30.017680 DramC Write-DBI on
9094 23:03:30.021023 PER_BANK_REFRESH: Hybrid Mode
9095 23:03:30.021106 TX_TRACKING: ON
9096 23:03:30.030656 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9097 23:03:30.037507 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9098 23:03:30.044452 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9099 23:03:30.050622 [FAST_K] Save calibration result to emmc
9100 23:03:30.050708 sync common calibartion params.
9101 23:03:30.053985 sync cbt_mode0:1, 1:1
9102 23:03:30.057723 dram_init: ddr_geometry: 2
9103 23:03:30.060386 dram_init: ddr_geometry: 2
9104 23:03:30.060469 dram_init: ddr_geometry: 2
9105 23:03:30.063682 0:dram_rank_size:100000000
9106 23:03:30.067454 1:dram_rank_size:100000000
9107 23:03:30.070458 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9108 23:03:30.073935 DFS_SHUFFLE_HW_MODE: ON
9109 23:03:30.077186 dramc_set_vcore_voltage set vcore to 725000
9110 23:03:30.080224 Read voltage for 1600, 0
9111 23:03:30.080306 Vio18 = 0
9112 23:03:30.083736 Vcore = 725000
9113 23:03:30.083833 Vdram = 0
9114 23:03:30.083899 Vddq = 0
9115 23:03:30.083960 Vmddr = 0
9116 23:03:30.087103 switch to 3200 Mbps bootup
9117 23:03:30.090662 [DramcRunTimeConfig]
9118 23:03:30.090742 PHYPLL
9119 23:03:30.093303 DPM_CONTROL_AFTERK: ON
9120 23:03:30.093384 PER_BANK_REFRESH: ON
9121 23:03:30.097109 REFRESH_OVERHEAD_REDUCTION: ON
9122 23:03:30.100249 CMD_PICG_NEW_MODE: OFF
9123 23:03:30.100338 XRTWTW_NEW_MODE: ON
9124 23:03:30.103659 XRTRTR_NEW_MODE: ON
9125 23:03:30.103741 TX_TRACKING: ON
9126 23:03:30.106911 RDSEL_TRACKING: OFF
9127 23:03:30.109716 DQS Precalculation for DVFS: ON
9128 23:03:30.109814 RX_TRACKING: OFF
9129 23:03:30.113345 HW_GATING DBG: ON
9130 23:03:30.113427 ZQCS_ENABLE_LP4: ON
9131 23:03:30.116631 RX_PICG_NEW_MODE: ON
9132 23:03:30.116714 TX_PICG_NEW_MODE: ON
9133 23:03:30.119871 ENABLE_RX_DCM_DPHY: ON
9134 23:03:30.123317 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9135 23:03:30.126708 DUMMY_READ_FOR_TRACKING: OFF
9136 23:03:30.126789 !!! SPM_CONTROL_AFTERK: OFF
9137 23:03:30.129969 !!! SPM could not control APHY
9138 23:03:30.133015 IMPEDANCE_TRACKING: ON
9139 23:03:30.133096 TEMP_SENSOR: ON
9140 23:03:30.136415 HW_SAVE_FOR_SR: OFF
9141 23:03:30.139922 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9142 23:03:30.142779 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9143 23:03:30.142860 Read ODT Tracking: ON
9144 23:03:30.146342 Refresh Rate DeBounce: ON
9145 23:03:30.149553 DFS_NO_QUEUE_FLUSH: ON
9146 23:03:30.153058 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9147 23:03:30.156380 ENABLE_DFS_RUNTIME_MRW: OFF
9148 23:03:30.156462 DDR_RESERVE_NEW_MODE: ON
9149 23:03:30.159273 MR_CBT_SWITCH_FREQ: ON
9150 23:03:30.162306 =========================
9151 23:03:30.180103 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9152 23:03:30.183462 dram_init: ddr_geometry: 2
9153 23:03:30.201796 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9154 23:03:30.205003 dram_init: dram init end (result: 0)
9155 23:03:30.211707 DRAM-K: Full calibration passed in 24423 msecs
9156 23:03:30.215108 MRC: failed to locate region type 0.
9157 23:03:30.215189 DRAM rank0 size:0x100000000,
9158 23:03:30.218449 DRAM rank1 size=0x100000000
9159 23:03:30.228401 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9160 23:03:30.235143 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9161 23:03:30.241363 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9162 23:03:30.251338 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9163 23:03:30.251449 DRAM rank0 size:0x100000000,
9164 23:03:30.254376 DRAM rank1 size=0x100000000
9165 23:03:30.254502 CBMEM:
9166 23:03:30.257615 IMD: root @ 0xfffff000 254 entries.
9167 23:03:30.261099 IMD: root @ 0xffffec00 62 entries.
9168 23:03:30.264418 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9169 23:03:30.271113 WARNING: RO_VPD is uninitialized or empty.
9170 23:03:30.273911 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9171 23:03:30.282338 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9172 23:03:30.295033 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9173 23:03:30.306406 BS: romstage times (exec / console): total (unknown) / 23953 ms
9174 23:03:30.306835
9175 23:03:30.307173
9176 23:03:30.316114 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9177 23:03:30.319492 ARM64: Exception handlers installed.
9178 23:03:30.322558 ARM64: Testing exception
9179 23:03:30.325843 ARM64: Done test exception
9180 23:03:30.326388 Enumerating buses...
9181 23:03:30.329556 Show all devs... Before device enumeration.
9182 23:03:30.332448 Root Device: enabled 1
9183 23:03:30.335897 CPU_CLUSTER: 0: enabled 1
9184 23:03:30.336496 CPU: 00: enabled 1
9185 23:03:30.339145 Compare with tree...
9186 23:03:30.339567 Root Device: enabled 1
9187 23:03:30.342555 CPU_CLUSTER: 0: enabled 1
9188 23:03:30.346017 CPU: 00: enabled 1
9189 23:03:30.346589 Root Device scanning...
9190 23:03:30.348881 scan_static_bus for Root Device
9191 23:03:30.352353 CPU_CLUSTER: 0 enabled
9192 23:03:30.355369 scan_static_bus for Root Device done
9193 23:03:30.358566 scan_bus: bus Root Device finished in 8 msecs
9194 23:03:30.358992 done
9195 23:03:30.365526 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9196 23:03:30.368923 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9197 23:03:30.375558 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9198 23:03:30.381810 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9199 23:03:30.382285 Allocating resources...
9200 23:03:30.385424 Reading resources...
9201 23:03:30.388830 Root Device read_resources bus 0 link: 0
9202 23:03:30.391789 DRAM rank0 size:0x100000000,
9203 23:03:30.392214 DRAM rank1 size=0x100000000
9204 23:03:30.398380 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9205 23:03:30.398808 CPU: 00 missing read_resources
9206 23:03:30.405101 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9207 23:03:30.408155 Root Device read_resources bus 0 link: 0 done
9208 23:03:30.411993 Done reading resources.
9209 23:03:30.415142 Show resources in subtree (Root Device)...After reading.
9210 23:03:30.418199 Root Device child on link 0 CPU_CLUSTER: 0
9211 23:03:30.421798 CPU_CLUSTER: 0 child on link 0 CPU: 00
9212 23:03:30.431592 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9213 23:03:30.432018 CPU: 00
9214 23:03:30.437843 Root Device assign_resources, bus 0 link: 0
9215 23:03:30.441287 CPU_CLUSTER: 0 missing set_resources
9216 23:03:30.444983 Root Device assign_resources, bus 0 link: 0 done
9217 23:03:30.447789 Done setting resources.
9218 23:03:30.451078 Show resources in subtree (Root Device)...After assigning values.
9219 23:03:30.454089 Root Device child on link 0 CPU_CLUSTER: 0
9220 23:03:30.460887 CPU_CLUSTER: 0 child on link 0 CPU: 00
9221 23:03:30.467911 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9222 23:03:30.471103 CPU: 00
9223 23:03:30.471612 Done allocating resources.
9224 23:03:30.477620 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9225 23:03:30.478045 Enabling resources...
9226 23:03:30.481055 done.
9227 23:03:30.483949 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9228 23:03:30.487652 Initializing devices...
9229 23:03:30.488176 Root Device init
9230 23:03:30.490884 init hardware done!
9231 23:03:30.491413 0x00000018: ctrlr->caps
9232 23:03:30.493817 52.000 MHz: ctrlr->f_max
9233 23:03:30.497125 0.400 MHz: ctrlr->f_min
9234 23:03:30.500543 0x40ff8080: ctrlr->voltages
9235 23:03:30.500979 sclk: 390625
9236 23:03:30.501506 Bus Width = 1
9237 23:03:30.504017 sclk: 390625
9238 23:03:30.504486 Bus Width = 1
9239 23:03:30.507451 Early init status = 3
9240 23:03:30.510563 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9241 23:03:30.514696 in-header: 03 fc 00 00 01 00 00 00
9242 23:03:30.518018 in-data: 00
9243 23:03:30.521163 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9244 23:03:30.526857 in-header: 03 fd 00 00 00 00 00 00
9245 23:03:30.530242 in-data:
9246 23:03:30.533540 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9247 23:03:30.538036 in-header: 03 fc 00 00 01 00 00 00
9248 23:03:30.541386 in-data: 00
9249 23:03:30.544306 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9250 23:03:30.550338 in-header: 03 fd 00 00 00 00 00 00
9251 23:03:30.553493 in-data:
9252 23:03:30.556899 [SSUSB] Setting up USB HOST controller...
9253 23:03:30.560429 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9254 23:03:30.563092 [SSUSB] phy power-on done.
9255 23:03:30.566831 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9256 23:03:30.573313 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9257 23:03:30.576150 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9258 23:03:30.583154 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9259 23:03:30.589639 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9260 23:03:30.595979 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9261 23:03:30.602722 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9262 23:03:30.609634 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9263 23:03:30.613013 SPM: binary array size = 0x9dc
9264 23:03:30.616076 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9265 23:03:30.622466 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9266 23:03:30.628830 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9267 23:03:30.635541 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9268 23:03:30.638792 configure_display: Starting display init
9269 23:03:30.673387 anx7625_power_on_init: Init interface.
9270 23:03:30.676456 anx7625_disable_pd_protocol: Disabled PD feature.
9271 23:03:30.679760 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9272 23:03:30.708041 anx7625_start_dp_work: Secure OCM version=00
9273 23:03:30.710927 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9274 23:03:30.725649 sp_tx_get_edid_block: EDID Block = 1
9275 23:03:30.828827 Extracted contents:
9276 23:03:30.831914 header: 00 ff ff ff ff ff ff 00
9277 23:03:30.835083 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9278 23:03:30.838163 version: 01 04
9279 23:03:30.841574 basic params: 95 1f 11 78 0a
9280 23:03:30.844724 chroma info: 76 90 94 55 54 90 27 21 50 54
9281 23:03:30.848090 established: 00 00 00
9282 23:03:30.854888 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9283 23:03:30.861431 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9284 23:03:30.864453 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9285 23:03:30.871482 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9286 23:03:30.878097 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9287 23:03:30.881276 extensions: 00
9288 23:03:30.881799 checksum: fb
9289 23:03:30.882171
9290 23:03:30.887712 Manufacturer: IVO Model 57d Serial Number 0
9291 23:03:30.888305 Made week 0 of 2020
9292 23:03:30.890785 EDID version: 1.4
9293 23:03:30.891214 Digital display
9294 23:03:30.894026 6 bits per primary color channel
9295 23:03:30.897707 DisplayPort interface
9296 23:03:30.898206 Maximum image size: 31 cm x 17 cm
9297 23:03:30.901126 Gamma: 220%
9298 23:03:30.901543 Check DPMS levels
9299 23:03:30.907162 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9300 23:03:30.910423 First detailed timing is preferred timing
9301 23:03:30.913711 Established timings supported:
9302 23:03:30.914389 Standard timings supported:
9303 23:03:30.917251 Detailed timings
9304 23:03:30.920509 Hex of detail: 383680a07038204018303c0035ae10000019
9305 23:03:30.927302 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9306 23:03:30.930586 0780 0798 07c8 0820 hborder 0
9307 23:03:30.933819 0438 043b 0447 0458 vborder 0
9308 23:03:30.937218 -hsync -vsync
9309 23:03:30.937637 Did detailed timing
9310 23:03:30.944280 Hex of detail: 000000000000000000000000000000000000
9311 23:03:30.947389 Manufacturer-specified data, tag 0
9312 23:03:30.950539 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9313 23:03:30.953763 ASCII string: InfoVision
9314 23:03:30.957052 Hex of detail: 000000fe00523134304e574635205248200a
9315 23:03:30.959954 ASCII string: R140NWF5 RH
9316 23:03:30.960510 Checksum
9317 23:03:30.963903 Checksum: 0xfb (valid)
9318 23:03:30.967050 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9319 23:03:30.970115 DSI data_rate: 832800000 bps
9320 23:03:30.977040 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9321 23:03:30.980429 anx7625_parse_edid: pixelclock(138800).
9322 23:03:30.983127 hactive(1920), hsync(48), hfp(24), hbp(88)
9323 23:03:30.986633 vactive(1080), vsync(12), vfp(3), vbp(17)
9324 23:03:30.989851 anx7625_dsi_config: config dsi.
9325 23:03:30.996865 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9326 23:03:31.010555 anx7625_dsi_config: success to config DSI
9327 23:03:31.013935 anx7625_dp_start: MIPI phy setup OK.
9328 23:03:31.017345 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9329 23:03:31.020438 mtk_ddp_mode_set invalid vrefresh 60
9330 23:03:31.023401 main_disp_path_setup
9331 23:03:31.023812 ovl_layer_smi_id_en
9332 23:03:31.027168 ovl_layer_smi_id_en
9333 23:03:31.027581 ccorr_config
9334 23:03:31.027909 aal_config
9335 23:03:31.030202 gamma_config
9336 23:03:31.030677 postmask_config
9337 23:03:31.033386 dither_config
9338 23:03:31.037162 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9339 23:03:31.043677 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9340 23:03:31.046771 Root Device init finished in 555 msecs
9341 23:03:31.049944 CPU_CLUSTER: 0 init
9342 23:03:31.057075 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9343 23:03:31.063073 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9344 23:03:31.063484 APU_MBOX 0x190000b0 = 0x10001
9345 23:03:31.066438 APU_MBOX 0x190001b0 = 0x10001
9346 23:03:31.069923 APU_MBOX 0x190005b0 = 0x10001
9347 23:03:31.073125 APU_MBOX 0x190006b0 = 0x10001
9348 23:03:31.080013 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9349 23:03:31.089331 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9350 23:03:31.101958 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9351 23:03:31.108356 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9352 23:03:31.119875 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9353 23:03:31.129390 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9354 23:03:31.132532 CPU_CLUSTER: 0 init finished in 81 msecs
9355 23:03:31.135922 Devices initialized
9356 23:03:31.138853 Show all devs... After init.
9357 23:03:31.139270 Root Device: enabled 1
9358 23:03:31.142221 CPU_CLUSTER: 0: enabled 1
9359 23:03:31.145402 CPU: 00: enabled 1
9360 23:03:31.148723 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9361 23:03:31.152165 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9362 23:03:31.155653 ELOG: NV offset 0x57f000 size 0x1000
9363 23:03:31.162105 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9364 23:03:31.168653 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9365 23:03:31.171947 ELOG: Event(17) added with size 13 at 2023-12-01 23:03:31 UTC
9366 23:03:31.178855 out: cmd=0x121: 03 db 21 01 00 00 00 00
9367 23:03:31.181926 in-header: 03 2e 00 00 2c 00 00 00
9368 23:03:31.195319 in-data: 31 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9369 23:03:31.198726 ELOG: Event(A1) added with size 10 at 2023-12-01 23:03:31 UTC
9370 23:03:31.205011 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9371 23:03:31.211745 ELOG: Event(A0) added with size 9 at 2023-12-01 23:03:31 UTC
9372 23:03:31.214883 elog_add_boot_reason: Logged dev mode boot
9373 23:03:31.221245 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9374 23:03:31.221661 Finalize devices...
9375 23:03:31.225221 Devices finalized
9376 23:03:31.227709 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9377 23:03:31.231274 Writing coreboot table at 0xffe64000
9378 23:03:31.237854 0. 000000000010a000-0000000000113fff: RAMSTAGE
9379 23:03:31.241592 1. 0000000040000000-00000000400fffff: RAM
9380 23:03:31.244954 2. 0000000040100000-000000004032afff: RAMSTAGE
9381 23:03:31.247692 3. 000000004032b000-00000000545fffff: RAM
9382 23:03:31.251161 4. 0000000054600000-000000005465ffff: BL31
9383 23:03:31.254631 5. 0000000054660000-00000000ffe63fff: RAM
9384 23:03:31.260957 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9385 23:03:31.264751 7. 0000000100000000-000000023fffffff: RAM
9386 23:03:31.267739 Passing 5 GPIOs to payload:
9387 23:03:31.270679 NAME | PORT | POLARITY | VALUE
9388 23:03:31.277393 EC in RW | 0x000000aa | low | undefined
9389 23:03:31.280506 EC interrupt | 0x00000005 | low | undefined
9390 23:03:31.287251 TPM interrupt | 0x000000ab | high | undefined
9391 23:03:31.290536 SD card detect | 0x00000011 | high | undefined
9392 23:03:31.296889 speaker enable | 0x00000093 | high | undefined
9393 23:03:31.300382 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9394 23:03:31.303262 in-header: 03 f9 00 00 02 00 00 00
9395 23:03:31.303677 in-data: 02 00
9396 23:03:31.306856 ADC[4]: Raw value=902955 ID=7
9397 23:03:31.310108 ADC[3]: Raw value=213546 ID=1
9398 23:03:31.310565 RAM Code: 0x71
9399 23:03:31.313560 ADC[6]: Raw value=75000 ID=0
9400 23:03:31.317114 ADC[5]: Raw value=213916 ID=1
9401 23:03:31.317529 SKU Code: 0x1
9402 23:03:31.323144 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 25e5
9403 23:03:31.326832 coreboot table: 964 bytes.
9404 23:03:31.330142 IMD ROOT 0. 0xfffff000 0x00001000
9405 23:03:31.333223 IMD SMALL 1. 0xffffe000 0x00001000
9406 23:03:31.336348 RO MCACHE 2. 0xffffc000 0x00001104
9407 23:03:31.339975 CONSOLE 3. 0xfff7c000 0x00080000
9408 23:03:31.342826 FMAP 4. 0xfff7b000 0x00000452
9409 23:03:31.346281 TIME STAMP 5. 0xfff7a000 0x00000910
9410 23:03:31.349785 VBOOT WORK 6. 0xfff66000 0x00014000
9411 23:03:31.352814 RAMOOPS 7. 0xffe66000 0x00100000
9412 23:03:31.356301 COREBOOT 8. 0xffe64000 0x00002000
9413 23:03:31.356737 IMD small region:
9414 23:03:31.359539 IMD ROOT 0. 0xffffec00 0x00000400
9415 23:03:31.363035 VPD 1. 0xffffeb80 0x0000006c
9416 23:03:31.365637 MMC STATUS 2. 0xffffeb60 0x00000004
9417 23:03:31.372328 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9418 23:03:31.372408 Probing TPM: done!
9419 23:03:31.378870 Connected to device vid:did:rid of 1ae0:0028:00
9420 23:03:31.388652 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
9421 23:03:31.392615 Initialized TPM device CR50 revision 0
9422 23:03:31.392708 Checking cr50 for pending updates
9423 23:03:31.398640 Reading cr50 TPM mode
9424 23:03:31.407470 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9425 23:03:31.413915 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9426 23:03:31.454242 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9427 23:03:31.457884 Checking segment from ROM address 0x40100000
9428 23:03:31.461385 Checking segment from ROM address 0x4010001c
9429 23:03:31.467703 Loading segment from ROM address 0x40100000
9430 23:03:31.468122 code (compression=0)
9431 23:03:31.477426 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9432 23:03:31.484034 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9433 23:03:31.484453 it's not compressed!
9434 23:03:31.490957 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9435 23:03:31.497698 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9436 23:03:31.515027 Loading segment from ROM address 0x4010001c
9437 23:03:31.515445 Entry Point 0x80000000
9438 23:03:31.518185 Loaded segments
9439 23:03:31.521548 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9440 23:03:31.528514 Jumping to boot code at 0x80000000(0xffe64000)
9441 23:03:31.534602 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9442 23:03:31.541572 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9443 23:03:31.549200 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9444 23:03:31.552615 Checking segment from ROM address 0x40100000
9445 23:03:31.555722 Checking segment from ROM address 0x4010001c
9446 23:03:31.562209 Loading segment from ROM address 0x40100000
9447 23:03:31.562670 code (compression=1)
9448 23:03:31.569163 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9449 23:03:31.579325 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9450 23:03:31.579836 using LZMA
9451 23:03:31.587974 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9452 23:03:31.594449 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9453 23:03:31.598237 Loading segment from ROM address 0x4010001c
9454 23:03:31.598818 Entry Point 0x54601000
9455 23:03:31.600898 Loaded segments
9456 23:03:31.604473 NOTICE: MT8192 bl31_setup
9457 23:03:31.611109 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9458 23:03:31.614591 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9459 23:03:31.617974 WARNING: region 0:
9460 23:03:31.621157 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9461 23:03:31.621578 WARNING: region 1:
9462 23:03:31.628038 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9463 23:03:31.631262 WARNING: region 2:
9464 23:03:31.634165 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9465 23:03:31.637766 WARNING: region 3:
9466 23:03:31.641130 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9467 23:03:31.644414 WARNING: region 4:
9468 23:03:31.651254 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9469 23:03:31.651820 WARNING: region 5:
9470 23:03:31.654530 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9471 23:03:31.657402 WARNING: region 6:
9472 23:03:31.661310 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9473 23:03:31.664279 WARNING: region 7:
9474 23:03:31.667751 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9475 23:03:31.674098 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9476 23:03:31.677526 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9477 23:03:31.681228 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9478 23:03:31.687930 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9479 23:03:31.690900 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9480 23:03:31.694321 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9481 23:03:31.700805 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9482 23:03:31.704452 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9483 23:03:31.711075 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9484 23:03:31.714014 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9485 23:03:31.717696 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9486 23:03:31.724028 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9487 23:03:31.727572 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9488 23:03:31.730935 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9489 23:03:31.737220 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9490 23:03:31.740764 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9491 23:03:31.747677 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9492 23:03:31.750808 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9493 23:03:31.753859 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9494 23:03:31.760593 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9495 23:03:31.763573 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9496 23:03:31.770717 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9497 23:03:31.773944 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9498 23:03:31.777174 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9499 23:03:31.783637 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9500 23:03:31.787082 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9501 23:03:31.793445 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9502 23:03:31.796555 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9503 23:03:31.803321 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9504 23:03:31.806826 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9505 23:03:31.810330 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9506 23:03:31.816478 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9507 23:03:31.819732 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9508 23:03:31.823191 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9509 23:03:31.826173 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9510 23:03:31.832660 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9511 23:03:31.836378 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9512 23:03:31.839394 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9513 23:03:31.842892 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9514 23:03:31.849570 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9515 23:03:31.852894 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9516 23:03:31.856124 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9517 23:03:31.859475 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9518 23:03:31.866515 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9519 23:03:31.869354 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9520 23:03:31.873016 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9521 23:03:31.879344 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9522 23:03:31.882369 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9523 23:03:31.885778 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9524 23:03:31.892901 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9525 23:03:31.895768 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9526 23:03:31.902196 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9527 23:03:31.905420 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9528 23:03:31.908962 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9529 23:03:31.915844 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9530 23:03:31.918771 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9531 23:03:31.925649 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9532 23:03:31.928771 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9533 23:03:31.935489 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9534 23:03:31.938631 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9535 23:03:31.945544 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9536 23:03:31.948747 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9537 23:03:31.955448 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9538 23:03:31.958782 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9539 23:03:31.962281 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9540 23:03:31.968600 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9541 23:03:31.972290 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9542 23:03:31.978592 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9543 23:03:31.981675 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9544 23:03:31.988562 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9545 23:03:31.992216 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9546 23:03:31.995065 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9547 23:03:32.001696 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9548 23:03:32.005052 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9549 23:03:32.012207 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9550 23:03:32.014882 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9551 23:03:32.021757 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9552 23:03:32.025530 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9553 23:03:32.031965 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9554 23:03:32.035156 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9555 23:03:32.037792 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9556 23:03:32.044885 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9557 23:03:32.048035 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9558 23:03:32.054413 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9559 23:03:32.057915 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9560 23:03:32.064810 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9561 23:03:32.067699 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9562 23:03:32.074695 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9563 23:03:32.077958 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9564 23:03:32.081436 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9565 23:03:32.087604 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9566 23:03:32.091040 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9567 23:03:32.097561 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9568 23:03:32.101065 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9569 23:03:32.107923 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9570 23:03:32.110835 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9571 23:03:32.114285 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9572 23:03:32.120970 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9573 23:03:32.124422 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9574 23:03:32.127379 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9575 23:03:32.130753 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9576 23:03:32.137668 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9577 23:03:32.141007 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9578 23:03:32.147325 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9579 23:03:32.150932 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9580 23:03:32.153763 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9581 23:03:32.160640 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9582 23:03:32.164248 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9583 23:03:32.170532 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9584 23:03:32.174044 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9585 23:03:32.177679 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9586 23:03:32.183563 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9587 23:03:32.187041 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9588 23:03:32.193790 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9589 23:03:32.196853 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9590 23:03:32.200574 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9591 23:03:32.207173 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9592 23:03:32.210577 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9593 23:03:32.213549 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9594 23:03:32.220100 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9595 23:03:32.223498 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9596 23:03:32.226667 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9597 23:03:32.229892 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9598 23:03:32.236734 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9599 23:03:32.239947 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9600 23:03:32.243449 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9601 23:03:32.250367 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9602 23:03:32.253362 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9603 23:03:32.260084 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9604 23:03:32.263142 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9605 23:03:32.266830 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9606 23:03:32.272921 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9607 23:03:32.276724 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9608 23:03:32.283295 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9609 23:03:32.287050 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9610 23:03:32.289915 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9611 23:03:32.296801 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9612 23:03:32.299671 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9613 23:03:32.302961 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9614 23:03:32.309706 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9615 23:03:32.312884 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9616 23:03:32.319411 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9617 23:03:32.323130 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9618 23:03:32.329589 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9619 23:03:32.332944 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9620 23:03:32.335985 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9621 23:03:32.342883 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9622 23:03:32.346091 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9623 23:03:32.349514 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9624 23:03:32.356475 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9625 23:03:32.359395 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9626 23:03:32.366649 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9627 23:03:32.369867 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9628 23:03:32.372833 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9629 23:03:32.379649 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9630 23:03:32.382912 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9631 23:03:32.389331 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9632 23:03:32.392777 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9633 23:03:32.395989 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9634 23:03:32.402518 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9635 23:03:32.405398 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9636 23:03:32.412784 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9637 23:03:32.415244 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9638 23:03:32.418898 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9639 23:03:32.425544 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9640 23:03:32.428635 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9641 23:03:32.435270 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9642 23:03:32.438471 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9643 23:03:32.441725 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9644 23:03:32.448421 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9645 23:03:32.451547 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9646 23:03:32.458383 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9647 23:03:32.461577 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9648 23:03:32.465574 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9649 23:03:32.471651 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9650 23:03:32.474509 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9651 23:03:32.481507 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9652 23:03:32.484527 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9653 23:03:32.491303 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9654 23:03:32.494383 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9655 23:03:32.497743 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9656 23:03:32.504416 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9657 23:03:32.507518 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9658 23:03:32.511102 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9659 23:03:32.517719 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9660 23:03:32.520596 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9661 23:03:32.527383 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9662 23:03:32.530696 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9663 23:03:32.536981 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9664 23:03:32.540466 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9665 23:03:32.543539 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9666 23:03:32.550313 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9667 23:03:32.553656 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9668 23:03:32.560536 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9669 23:03:32.563674 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9670 23:03:32.570311 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9671 23:03:32.572976 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9672 23:03:32.576439 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9673 23:03:32.582887 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9674 23:03:32.586360 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9675 23:03:32.592615 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9676 23:03:32.596094 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9677 23:03:32.603134 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9678 23:03:32.605837 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9679 23:03:32.609472 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9680 23:03:32.616032 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9681 23:03:32.619134 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9682 23:03:32.625697 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9683 23:03:32.629000 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9684 23:03:32.635811 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9685 23:03:32.638739 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9686 23:03:32.642530 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9687 23:03:32.648993 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9688 23:03:32.651982 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9689 23:03:32.658807 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9690 23:03:32.661981 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9691 23:03:32.668947 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9692 23:03:32.672251 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9693 23:03:32.675611 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9694 23:03:32.681468 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9695 23:03:32.684786 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9696 23:03:32.691677 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9697 23:03:32.695218 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9698 23:03:32.701638 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9699 23:03:32.704586 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9700 23:03:32.711387 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9701 23:03:32.714640 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9702 23:03:32.718086 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9703 23:03:32.725357 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9704 23:03:32.727857 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9705 23:03:32.730924 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9706 23:03:32.734547 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9707 23:03:32.741026 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9708 23:03:32.744331 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9709 23:03:32.747787 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9710 23:03:32.754596 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9711 23:03:32.757550 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9712 23:03:32.763797 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9713 23:03:32.767275 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9714 23:03:32.770816 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9715 23:03:32.777100 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9716 23:03:32.780855 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9717 23:03:32.783737 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9718 23:03:32.790779 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9719 23:03:32.793401 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9720 23:03:32.800080 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9721 23:03:32.803585 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9722 23:03:32.806490 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9723 23:03:32.813307 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9724 23:03:32.816764 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9725 23:03:32.819601 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9726 23:03:32.826329 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9727 23:03:32.829840 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9728 23:03:32.833721 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9729 23:03:32.839475 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9730 23:03:32.842761 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9731 23:03:32.849838 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9732 23:03:32.852646 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9733 23:03:32.855980 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9734 23:03:32.862744 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9735 23:03:32.865904 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9736 23:03:32.872563 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9737 23:03:32.875903 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9738 23:03:32.878852 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9739 23:03:32.885563 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9740 23:03:32.889025 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9741 23:03:32.895422 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9742 23:03:32.898926 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9743 23:03:32.902151 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9744 23:03:32.905394 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9745 23:03:32.912239 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9746 23:03:32.914929 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9747 23:03:32.918429 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9748 23:03:32.922048 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9749 23:03:32.928082 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9750 23:03:32.931757 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9751 23:03:32.935235 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9752 23:03:32.937998 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9753 23:03:32.944945 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9754 23:03:32.948256 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9755 23:03:32.951827 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9756 23:03:32.954536 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9757 23:03:32.961425 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9758 23:03:32.964543 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9759 23:03:32.971639 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9760 23:03:32.974708 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9761 23:03:32.981327 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9762 23:03:32.984122 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9763 23:03:32.990834 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9764 23:03:32.994065 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9765 23:03:32.997442 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9766 23:03:33.003679 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9767 23:03:33.007444 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9768 23:03:33.013684 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9769 23:03:33.017175 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9770 23:03:33.023564 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9771 23:03:33.027136 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9772 23:03:33.030429 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9773 23:03:33.036747 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9774 23:03:33.040140 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9775 23:03:33.046903 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9776 23:03:33.050066 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9777 23:03:33.053104 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9778 23:03:33.059858 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9779 23:03:33.063558 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9780 23:03:33.069937 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9781 23:03:33.073289 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9782 23:03:33.076335 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9783 23:03:33.083327 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9784 23:03:33.086568 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9785 23:03:33.093378 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9786 23:03:33.096438 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9787 23:03:33.102938 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9788 23:03:33.106007 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9789 23:03:33.109397 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9790 23:03:33.116124 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9791 23:03:33.119407 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9792 23:03:33.125814 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9793 23:03:33.129837 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9794 23:03:33.135756 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9795 23:03:33.139192 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9796 23:03:33.142394 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9797 23:03:33.149561 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9798 23:03:33.152644 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9799 23:03:33.159227 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9800 23:03:33.162099 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9801 23:03:33.165995 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9802 23:03:33.171953 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9803 23:03:33.175557 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9804 23:03:33.181817 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9805 23:03:33.185092 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9806 23:03:33.191982 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9807 23:03:33.195248 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9808 23:03:33.198220 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9809 23:03:33.205367 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9810 23:03:33.208258 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9811 23:03:33.214611 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9812 23:03:33.218308 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9813 23:03:33.221372 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9814 23:03:33.227737 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9815 23:03:33.231317 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9816 23:03:33.237849 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9817 23:03:33.241245 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9818 23:03:33.247740 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9819 23:03:33.251234 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9820 23:03:33.254619 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9821 23:03:33.261119 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9822 23:03:33.264093 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9823 23:03:33.270977 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9824 23:03:33.274134 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9825 23:03:33.280981 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9826 23:03:33.283838 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9827 23:03:33.287411 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9828 23:03:33.293891 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9829 23:03:33.297214 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9830 23:03:33.303812 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9831 23:03:33.306685 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9832 23:03:33.312980 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9833 23:03:33.316482 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9834 23:03:33.322964 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9835 23:03:33.326121 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9836 23:03:33.329590 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9837 23:03:33.335778 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9838 23:03:33.339280 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9839 23:03:33.346279 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9840 23:03:33.349409 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9841 23:03:33.355596 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9842 23:03:33.359016 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9843 23:03:33.366009 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9844 23:03:33.369470 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9845 23:03:33.372325 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9846 23:03:33.379160 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9847 23:03:33.382498 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9848 23:03:33.388902 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9849 23:03:33.392399 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9850 23:03:33.398714 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9851 23:03:33.402486 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9852 23:03:33.405009 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9853 23:03:33.411700 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9854 23:03:33.414886 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9855 23:03:33.421619 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9856 23:03:33.425102 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9857 23:03:33.431522 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9858 23:03:33.434780 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9859 23:03:33.441325 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9860 23:03:33.444743 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9861 23:03:33.448145 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9862 23:03:33.454554 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9863 23:03:33.458061 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9864 23:03:33.464253 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9865 23:03:33.467530 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9866 23:03:33.474519 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9867 23:03:33.477415 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9868 23:03:33.484298 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9869 23:03:33.487373 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9870 23:03:33.494089 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9871 23:03:33.497261 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9872 23:03:33.500913 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9873 23:03:33.507398 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9874 23:03:33.510618 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9875 23:03:33.517004 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9876 23:03:33.520607 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9877 23:03:33.523565 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9878 23:03:33.530436 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9879 23:03:33.533895 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9880 23:03:33.540241 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9881 23:03:33.543555 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9882 23:03:33.550060 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9883 23:03:33.553340 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9884 23:03:33.560152 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9885 23:03:33.563638 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9886 23:03:33.569895 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9887 23:03:33.573239 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9888 23:03:33.580238 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9889 23:03:33.583256 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9890 23:03:33.589979 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9891 23:03:33.592788 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9892 23:03:33.599397 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9893 23:03:33.602771 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9894 23:03:33.609584 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9895 23:03:33.612654 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9896 23:03:33.619143 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9897 23:03:33.622532 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9898 23:03:33.628869 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9899 23:03:33.632670 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9900 23:03:33.638677 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9901 23:03:33.641863 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9902 23:03:33.648877 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9903 23:03:33.652118 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9904 23:03:33.658485 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9905 23:03:33.665315 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9906 23:03:33.668439 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9907 23:03:33.674844 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9908 23:03:33.678140 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9909 23:03:33.681580 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9910 23:03:33.685164 INFO: [APUAPC] vio 0
9911 23:03:33.691443 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9912 23:03:33.694508 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9913 23:03:33.698363 INFO: [APUAPC] D0_APC_0: 0x400510
9914 23:03:33.701371 INFO: [APUAPC] D0_APC_1: 0x0
9915 23:03:33.704746 INFO: [APUAPC] D0_APC_2: 0x1540
9916 23:03:33.707954 INFO: [APUAPC] D0_APC_3: 0x0
9917 23:03:33.711328 INFO: [APUAPC] D1_APC_0: 0xffffffff
9918 23:03:33.714880 INFO: [APUAPC] D1_APC_1: 0xffffffff
9919 23:03:33.718368 INFO: [APUAPC] D1_APC_2: 0x3fffff
9920 23:03:33.718450 INFO: [APUAPC] D1_APC_3: 0x0
9921 23:03:33.724406 INFO: [APUAPC] D2_APC_0: 0xffffffff
9922 23:03:33.728012 INFO: [APUAPC] D2_APC_1: 0xffffffff
9923 23:03:33.730847 INFO: [APUAPC] D2_APC_2: 0x3fffff
9924 23:03:33.730928 INFO: [APUAPC] D2_APC_3: 0x0
9925 23:03:33.734587 INFO: [APUAPC] D3_APC_0: 0xffffffff
9926 23:03:33.740996 INFO: [APUAPC] D3_APC_1: 0xffffffff
9927 23:03:33.744414 INFO: [APUAPC] D3_APC_2: 0x3fffff
9928 23:03:33.744521 INFO: [APUAPC] D3_APC_3: 0x0
9929 23:03:33.747494 INFO: [APUAPC] D4_APC_0: 0xffffffff
9930 23:03:33.750935 INFO: [APUAPC] D4_APC_1: 0xffffffff
9931 23:03:33.754009 INFO: [APUAPC] D4_APC_2: 0x3fffff
9932 23:03:33.757413 INFO: [APUAPC] D4_APC_3: 0x0
9933 23:03:33.760310 INFO: [APUAPC] D5_APC_0: 0xffffffff
9934 23:03:33.763792 INFO: [APUAPC] D5_APC_1: 0xffffffff
9935 23:03:33.766929 INFO: [APUAPC] D5_APC_2: 0x3fffff
9936 23:03:33.770451 INFO: [APUAPC] D5_APC_3: 0x0
9937 23:03:33.773830 INFO: [APUAPC] D6_APC_0: 0xffffffff
9938 23:03:33.776818 INFO: [APUAPC] D6_APC_1: 0xffffffff
9939 23:03:33.780689 INFO: [APUAPC] D6_APC_2: 0x3fffff
9940 23:03:33.783581 INFO: [APUAPC] D6_APC_3: 0x0
9941 23:03:33.787075 INFO: [APUAPC] D7_APC_0: 0xffffffff
9942 23:03:33.790082 INFO: [APUAPC] D7_APC_1: 0xffffffff
9943 23:03:33.793756 INFO: [APUAPC] D7_APC_2: 0x3fffff
9944 23:03:33.796493 INFO: [APUAPC] D7_APC_3: 0x0
9945 23:03:33.800033 INFO: [APUAPC] D8_APC_0: 0xffffffff
9946 23:03:33.803018 INFO: [APUAPC] D8_APC_1: 0xffffffff
9947 23:03:33.806464 INFO: [APUAPC] D8_APC_2: 0x3fffff
9948 23:03:33.809794 INFO: [APUAPC] D8_APC_3: 0x0
9949 23:03:33.813101 INFO: [APUAPC] D9_APC_0: 0xffffffff
9950 23:03:33.816736 INFO: [APUAPC] D9_APC_1: 0xffffffff
9951 23:03:33.819560 INFO: [APUAPC] D9_APC_2: 0x3fffff
9952 23:03:33.823052 INFO: [APUAPC] D9_APC_3: 0x0
9953 23:03:33.826421 INFO: [APUAPC] D10_APC_0: 0xffffffff
9954 23:03:33.829558 INFO: [APUAPC] D10_APC_1: 0xffffffff
9955 23:03:33.832873 INFO: [APUAPC] D10_APC_2: 0x3fffff
9956 23:03:33.835994 INFO: [APUAPC] D10_APC_3: 0x0
9957 23:03:33.839540 INFO: [APUAPC] D11_APC_0: 0xffffffff
9958 23:03:33.842708 INFO: [APUAPC] D11_APC_1: 0xffffffff
9959 23:03:33.845899 INFO: [APUAPC] D11_APC_2: 0x3fffff
9960 23:03:33.849485 INFO: [APUAPC] D11_APC_3: 0x0
9961 23:03:33.852789 INFO: [APUAPC] D12_APC_0: 0xffffffff
9962 23:03:33.856499 INFO: [APUAPC] D12_APC_1: 0xffffffff
9963 23:03:33.859665 INFO: [APUAPC] D12_APC_2: 0x3fffff
9964 23:03:33.862851 INFO: [APUAPC] D12_APC_3: 0x0
9965 23:03:33.865960 INFO: [APUAPC] D13_APC_0: 0xffffffff
9966 23:03:33.869167 INFO: [APUAPC] D13_APC_1: 0xffffffff
9967 23:03:33.872360 INFO: [APUAPC] D13_APC_2: 0x3fffff
9968 23:03:33.875757 INFO: [APUAPC] D13_APC_3: 0x0
9969 23:03:33.878911 INFO: [APUAPC] D14_APC_0: 0xffffffff
9970 23:03:33.882480 INFO: [APUAPC] D14_APC_1: 0xffffffff
9971 23:03:33.889048 INFO: [APUAPC] D14_APC_2: 0x3fffff
9972 23:03:33.889133 INFO: [APUAPC] D14_APC_3: 0x0
9973 23:03:33.891961 INFO: [APUAPC] D15_APC_0: 0xffffffff
9974 23:03:33.898768 INFO: [APUAPC] D15_APC_1: 0xffffffff
9975 23:03:33.902447 INFO: [APUAPC] D15_APC_2: 0x3fffff
9976 23:03:33.902528 INFO: [APUAPC] D15_APC_3: 0x0
9977 23:03:33.905238 INFO: [APUAPC] APC_CON: 0x4
9978 23:03:33.908638 INFO: [NOCDAPC] D0_APC_0: 0x0
9979 23:03:33.912507 INFO: [NOCDAPC] D0_APC_1: 0x0
9980 23:03:33.915098 INFO: [NOCDAPC] D1_APC_0: 0x0
9981 23:03:33.918538 INFO: [NOCDAPC] D1_APC_1: 0xfff
9982 23:03:33.921806 INFO: [NOCDAPC] D2_APC_0: 0x0
9983 23:03:33.925131 INFO: [NOCDAPC] D2_APC_1: 0xfff
9984 23:03:33.928293 INFO: [NOCDAPC] D3_APC_0: 0x0
9985 23:03:33.931903 INFO: [NOCDAPC] D3_APC_1: 0xfff
9986 23:03:33.932010 INFO: [NOCDAPC] D4_APC_0: 0x0
9987 23:03:33.935096 INFO: [NOCDAPC] D4_APC_1: 0xfff
9988 23:03:33.938159 INFO: [NOCDAPC] D5_APC_0: 0x0
9989 23:03:33.941942 INFO: [NOCDAPC] D5_APC_1: 0xfff
9990 23:03:33.944902 INFO: [NOCDAPC] D6_APC_0: 0x0
9991 23:03:33.948006 INFO: [NOCDAPC] D6_APC_1: 0xfff
9992 23:03:33.951228 INFO: [NOCDAPC] D7_APC_0: 0x0
9993 23:03:33.954836 INFO: [NOCDAPC] D7_APC_1: 0xfff
9994 23:03:33.958499 INFO: [NOCDAPC] D8_APC_0: 0x0
9995 23:03:33.961109 INFO: [NOCDAPC] D8_APC_1: 0xfff
9996 23:03:33.965063 INFO: [NOCDAPC] D9_APC_0: 0x0
9997 23:03:33.967798 INFO: [NOCDAPC] D9_APC_1: 0xfff
9998 23:03:33.967905 INFO: [NOCDAPC] D10_APC_0: 0x0
9999 23:03:33.971011 INFO: [NOCDAPC] D10_APC_1: 0xfff
10000 23:03:33.974198 INFO: [NOCDAPC] D11_APC_0: 0x0
10001 23:03:33.977873 INFO: [NOCDAPC] D11_APC_1: 0xfff
10002 23:03:33.981353 INFO: [NOCDAPC] D12_APC_0: 0x0
10003 23:03:33.984332 INFO: [NOCDAPC] D12_APC_1: 0xfff
10004 23:03:33.987370 INFO: [NOCDAPC] D13_APC_0: 0x0
10005 23:03:33.990967 INFO: [NOCDAPC] D13_APC_1: 0xfff
10006 23:03:33.994781 INFO: [NOCDAPC] D14_APC_0: 0x0
10007 23:03:33.997761 INFO: [NOCDAPC] D14_APC_1: 0xfff
10008 23:03:34.000718 INFO: [NOCDAPC] D15_APC_0: 0x0
10009 23:03:34.004097 INFO: [NOCDAPC] D15_APC_1: 0xfff
10010 23:03:34.007676 INFO: [NOCDAPC] APC_CON: 0x4
10011 23:03:34.010570 INFO: [APUAPC] set_apusys_apc done
10012 23:03:34.014198 INFO: [DEVAPC] devapc_init done
10013 23:03:34.017411 INFO: GICv3 without legacy support detected.
10014 23:03:34.020660 INFO: ARM GICv3 driver initialized in EL3
10015 23:03:34.023816 INFO: Maximum SPI INTID supported: 639
10016 23:03:34.030092 INFO: BL31: Initializing runtime services
10017 23:03:34.033879 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10018 23:03:34.036830 INFO: SPM: enable CPC mode
10019 23:03:34.043371 INFO: mcdi ready for mcusys-off-idle and system suspend
10020 23:03:34.046910 INFO: BL31: Preparing for EL3 exit to normal world
10021 23:03:34.050119 INFO: Entry point address = 0x80000000
10022 23:03:34.053378 INFO: SPSR = 0x8
10023 23:03:34.058527
10024 23:03:34.058608
10025 23:03:34.058672
10026 23:03:34.062075 Starting depthcharge on Spherion...
10027 23:03:34.062156
10028 23:03:34.062221 Wipe memory regions:
10029 23:03:34.062321
10030 23:03:34.063002 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10031 23:03:34.063103 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10032 23:03:34.063185 Setting prompt string to ['asurada:']
10033 23:03:34.063268 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10034 23:03:34.065245 [0x00000040000000, 0x00000054600000)
10035 23:03:34.187374
10036 23:03:34.187503 [0x00000054660000, 0x00000080000000)
10037 23:03:34.448346
10038 23:03:34.448499 [0x000000821a7280, 0x000000ffe64000)
10039 23:03:35.193403
10040 23:03:35.193541 [0x00000100000000, 0x00000240000000)
10041 23:03:37.083591
10042 23:03:37.086822 Initializing XHCI USB controller at 0x11200000.
10043 23:03:38.125034
10044 23:03:38.127897 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10045 23:03:38.128010
10046 23:03:38.128102
10047 23:03:38.128184
10048 23:03:38.128464 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10050 23:03:38.228762 asurada: tftpboot 192.168.201.1 12154430/tftp-deploy-s7vuzfyl/kernel/image.itb 12154430/tftp-deploy-s7vuzfyl/kernel/cmdline
10051 23:03:38.228900 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10052 23:03:38.228991 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10053 23:03:38.233286 tftpboot 192.168.201.1 12154430/tftp-deploy-s7vuzfyl/kernel/image.ittp-deploy-s7vuzfyl/kernel/cmdline
10054 23:03:38.233369
10055 23:03:38.233434 Waiting for link
10056 23:03:38.393642
10057 23:03:38.393767 R8152: Initializing
10058 23:03:38.393832
10059 23:03:38.396851 Version 6 (ocp_data = 5c30)
10060 23:03:38.396933
10061 23:03:38.400035 R8152: Done initializing
10062 23:03:38.400116
10063 23:03:38.400181 Adding net device
10064 23:03:40.303099
10065 23:03:40.303240 done.
10066 23:03:40.303308
10067 23:03:40.303369 MAC: 00:24:32:30:7c:7b
10068 23:03:40.303430
10069 23:03:40.306528 Sending DHCP discover... done.
10070 23:03:40.306598
10071 23:03:44.023092 Waiting for reply... done.
10072 23:03:44.023240
10073 23:03:44.023309 Sending DHCP request... done.
10074 23:03:44.026613
10075 23:03:44.026695 Waiting for reply... done.
10076 23:03:44.026760
10077 23:03:44.029291 My ip is 192.168.201.14
10078 23:03:44.029371
10079 23:03:44.032958 The DHCP server ip is 192.168.201.1
10080 23:03:44.033040
10081 23:03:44.035812 TFTP server IP predefined by user: 192.168.201.1
10082 23:03:44.035923
10083 23:03:44.043047 Bootfile predefined by user: 12154430/tftp-deploy-s7vuzfyl/kernel/image.itb
10084 23:03:44.043145
10085 23:03:44.045760 Sending tftp read request... done.
10086 23:03:44.045857
10087 23:03:44.049260 Waiting for the transfer...
10088 23:03:44.049370
10089 23:03:44.590549 00000000 ################################################################
10090 23:03:44.590681
10091 23:03:45.112057 00080000 ################################################################
10092 23:03:45.112187
10093 23:03:45.637468 00100000 ################################################################
10094 23:03:45.637598
10095 23:03:46.177646 00180000 ################################################################
10096 23:03:46.177784
10097 23:03:46.714135 00200000 ################################################################
10098 23:03:46.714310
10099 23:03:47.262426 00280000 ################################################################
10100 23:03:47.262593
10101 23:03:47.899865 00300000 ################################################################
10102 23:03:47.900396
10103 23:03:48.594663 00380000 ################################################################
10104 23:03:48.595271
10105 23:03:49.306199 00400000 ################################################################
10106 23:03:49.306718
10107 23:03:49.959964 00480000 ################################################################
10108 23:03:49.960100
10109 23:03:50.479953 00500000 ################################################################
10110 23:03:50.480092
10111 23:03:51.027608 00580000 ################################################################
10112 23:03:51.027761
10113 23:03:51.644119 00600000 ################################################################
10114 23:03:51.644251
10115 23:03:52.243682 00680000 ################################################################
10116 23:03:52.243818
10117 23:03:52.830423 00700000 ################################################################
10118 23:03:52.830911
10119 23:03:53.491927 00780000 ################################################################
10120 23:03:53.492153
10121 23:03:54.170889 00800000 ################################################################
10122 23:03:54.171377
10123 23:03:54.806008 00880000 ################################################################
10124 23:03:54.806588
10125 23:03:55.493622 00900000 ################################################################
10126 23:03:55.494127
10127 23:03:56.116829 00980000 ################################################################
10128 23:03:56.117388
10129 23:03:56.786242 00a00000 ################################################################
10130 23:03:56.786782
10131 23:03:57.438364 00a80000 ################################################################
10132 23:03:57.438852
10133 23:03:58.101306 00b00000 ################################################################
10134 23:03:58.101794
10135 23:03:58.723287 00b80000 ################################################################
10136 23:03:58.723418
10137 23:03:59.293115 00c00000 ################################################################
10138 23:03:59.293605
10139 23:03:59.860373 00c80000 ################################################################
10140 23:03:59.860507
10141 23:04:00.431465 00d00000 ################################################################
10142 23:04:00.431597
10143 23:04:01.071963 00d80000 ################################################################
10144 23:04:01.072452
10145 23:04:01.719870 00e00000 ################################################################
10146 23:04:01.720573
10147 23:04:02.345448 00e80000 ################################################################
10148 23:04:02.345605
10149 23:04:02.985152 00f00000 ################################################################
10150 23:04:02.985644
10151 23:04:03.606194 00f80000 ################################################################
10152 23:04:03.606778
10153 23:04:04.255892 01000000 ################################################################
10154 23:04:04.256157
10155 23:04:04.937803 01080000 ################################################################
10156 23:04:04.938400
10157 23:04:05.613362 01100000 ################################################################
10158 23:04:05.613903
10159 23:04:06.304982 01180000 ################################################################
10160 23:04:06.305504
10161 23:04:06.976170 01200000 ################################################################
10162 23:04:06.976705
10163 23:04:07.677403 01280000 ################################################################
10164 23:04:07.677921
10165 23:04:08.384547 01300000 ################################################################
10166 23:04:08.385202
10167 23:04:09.082131 01380000 ################################################################
10168 23:04:09.082305
10169 23:04:09.686452 01400000 ################################################################
10170 23:04:09.686955
10171 23:04:10.237372 01480000 ################################################################
10172 23:04:10.237509
10173 23:04:10.794427 01500000 ################################################################
10174 23:04:10.794586
10175 23:04:11.399545 01580000 ################################################################
10176 23:04:11.399701
10177 23:04:11.962519 01600000 ################################################################
10178 23:04:11.962669
10179 23:04:12.642717 01680000 ################################################################
10180 23:04:12.643441
10181 23:04:13.297169 01700000 ################################################################
10182 23:04:13.297674
10183 23:04:13.986877 01780000 ################################################################
10184 23:04:13.987024
10185 23:04:14.742019 01800000 ################################################################
10186 23:04:14.742165
10187 23:04:15.413807 01880000 ################################################################
10188 23:04:15.413953
10189 23:04:15.992885 01900000 ################################################################
10190 23:04:15.993023
10191 23:04:16.624819 01980000 ################################################################
10192 23:04:16.624969
10193 23:04:17.320043 01a00000 ################################################################
10194 23:04:17.320193
10195 23:04:17.961510 01a80000 ################################################################
10196 23:04:17.961648
10197 23:04:18.557864 01b00000 ################################################################
10198 23:04:18.558014
10199 23:04:18.618164 01b80000 ####### done.
10200 23:04:18.618266
10201 23:04:18.621001 The bootfile was 28888470 bytes long.
10202 23:04:18.621091
10203 23:04:18.624437 Sending tftp read request... done.
10204 23:04:18.624531
10205 23:04:18.624606 Waiting for the transfer...
10206 23:04:18.624676
10207 23:04:18.627688 00000000 # done.
10208 23:04:18.627785
10209 23:04:18.634633 Command line loaded dynamically from TFTP file: 12154430/tftp-deploy-s7vuzfyl/kernel/cmdline
10210 23:04:18.634822
10211 23:04:18.657682 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12154430/extract-nfsrootfs-ao66pv48,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10212 23:04:18.658021
10213 23:04:18.658204 Loading FIT.
10214 23:04:18.658402
10215 23:04:18.661522 Image ramdisk-1 has 17795173 bytes.
10216 23:04:18.661879
10217 23:04:18.664014 Image fdt-1 has 47278 bytes.
10218 23:04:18.664266
10219 23:04:18.667321 Image kernel-1 has 11043984 bytes.
10220 23:04:18.667562
10221 23:04:18.677631 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10222 23:04:18.678131
10223 23:04:18.694170 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10224 23:04:18.694732
10225 23:04:18.700528 Choosing best match conf-1 for compat google,spherion-rev2.
10226 23:04:18.703572
10227 23:04:18.708789 Connected to device vid:did:rid of 1ae0:0028:00
10228 23:04:18.715276
10229 23:04:18.718447 tpm_get_response: command 0x17b, return code 0x0
10230 23:04:18.718915
10231 23:04:18.722399 ec_init: CrosEC protocol v3 supported (256, 248)
10232 23:04:18.726177
10233 23:04:18.729695 tpm_cleanup: add release locality here.
10234 23:04:18.730290
10235 23:04:18.730685 Shutting down all USB controllers.
10236 23:04:18.733231
10237 23:04:18.733692 Removing current net device
10238 23:04:18.734064
10239 23:04:18.739297 Exiting depthcharge with code 4 at timestamp: 73924650
10240 23:04:18.739857
10241 23:04:18.742823 LZMA decompressing kernel-1 to 0x821a6718
10242 23:04:18.743246
10243 23:04:18.746169 LZMA decompressing kernel-1 to 0x40000000
10244 23:04:20.139983
10245 23:04:20.140539 jumping to kernel
10246 23:04:20.142229 end: 2.2.4 bootloader-commands (duration 00:00:46) [common]
10247 23:04:20.142809 start: 2.2.5 auto-login-action (timeout 00:03:39) [common]
10248 23:04:20.143215 Setting prompt string to ['Linux version [0-9]']
10249 23:04:20.143553 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10250 23:04:20.143896 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10251 23:04:20.222433
10252 23:04:20.225453 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10253 23:04:20.229043 start: 2.2.5.1 login-action (timeout 00:03:39) [common]
10254 23:04:20.229621 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10255 23:04:20.230000 Setting prompt string to []
10256 23:04:20.230421 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10257 23:04:20.230874 Using line separator: #'\n'#
10258 23:04:20.231197 No login prompt set.
10259 23:04:20.231547 Parsing kernel messages
10260 23:04:20.231957 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10261 23:04:20.232505 [login-action] Waiting for messages, (timeout 00:03:39)
10262 23:04:20.248421 [ 0.000000] Linux version 6.1.64-cip10 (KernelCI@build-j31357-arm64-gcc-10-defconfig-arm64-chromebook-69txj) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Dec 1 22:47:09 UTC 2023
10263 23:04:20.251204 [ 0.000000] random: crng init done
10264 23:04:20.258227 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10265 23:04:20.261198 [ 0.000000] efi: UEFI not found.
10266 23:04:20.267935 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10267 23:04:20.277952 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10268 23:04:20.284335 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10269 23:04:20.294328 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10270 23:04:20.300775 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10271 23:04:20.307747 [ 0.000000] printk: bootconsole [mtk8250] enabled
10272 23:04:20.314905 [ 0.000000] NUMA: No NUMA configuration found
10273 23:04:20.320888 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10274 23:04:20.327267 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10275 23:04:20.327583 [ 0.000000] Zone ranges:
10276 23:04:20.334328 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10277 23:04:20.337318 [ 0.000000] DMA32 empty
10278 23:04:20.344276 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10279 23:04:20.347446 [ 0.000000] Movable zone start for each node
10280 23:04:20.350842 [ 0.000000] Early memory node ranges
10281 23:04:20.357014 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10282 23:04:20.363548 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10283 23:04:20.369866 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10284 23:04:20.376818 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10285 23:04:20.383428 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10286 23:04:20.389886 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10287 23:04:20.446643 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10288 23:04:20.453407 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10289 23:04:20.460011 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10290 23:04:20.463269 [ 0.000000] psci: probing for conduit method from DT.
10291 23:04:20.469884 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10292 23:04:20.473432 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10293 23:04:20.479775 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10294 23:04:20.483134 [ 0.000000] psci: SMC Calling Convention v1.2
10295 23:04:20.489993 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10296 23:04:20.492421 [ 0.000000] Detected VIPT I-cache on CPU0
10297 23:04:20.499689 [ 0.000000] CPU features: detected: GIC system register CPU interface
10298 23:04:20.506352 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10299 23:04:20.513041 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10300 23:04:20.519282 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10301 23:04:20.528997 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10302 23:04:20.535425 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10303 23:04:20.538821 [ 0.000000] alternatives: applying boot alternatives
10304 23:04:20.545391 [ 0.000000] Fallback order for Node 0: 0
10305 23:04:20.551894 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10306 23:04:20.555374 [ 0.000000] Policy zone: Normal
10307 23:04:20.578536 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12154430/extract-nfsrootfs-ao66pv48,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10308 23:04:20.588039 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10309 23:04:20.598232 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10310 23:04:20.607859 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10311 23:04:20.614980 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10312 23:04:20.618183 <6>[ 0.000000] software IO TLB: area num 8.
10313 23:04:20.674996 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10314 23:04:20.823863 <6>[ 0.000000] Memory: 7952176K/8385536K available (17984K kernel code, 4116K rwdata, 17316K rodata, 8448K init, 615K bss, 400592K reserved, 32768K cma-reserved)
10315 23:04:20.831066 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10316 23:04:20.837219 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10317 23:04:20.840389 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10318 23:04:20.847958 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10319 23:04:20.853707 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10320 23:04:20.857013 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10321 23:04:20.866604 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10322 23:04:20.873178 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10323 23:04:20.879778 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10324 23:04:20.886668 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10325 23:04:20.889770 <6>[ 0.000000] GICv3: 608 SPIs implemented
10326 23:04:20.893219 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10327 23:04:20.899837 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10328 23:04:20.903096 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10329 23:04:20.909796 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10330 23:04:20.923168 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10331 23:04:20.935972 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10332 23:04:20.942375 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10333 23:04:20.951606 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10334 23:04:20.963690 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10335 23:04:20.970953 <6>[ 0.000001] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10336 23:04:20.977873 <6>[ 0.009181] Console: colour dummy device 80x25
10337 23:04:20.987967 <6>[ 0.013909] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10338 23:04:20.994008 <6>[ 0.024350] pid_max: default: 32768 minimum: 301
10339 23:04:20.997311 <6>[ 0.029251] LSM: Security Framework initializing
10340 23:04:21.003552 <6>[ 0.034218] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10341 23:04:21.013710 <6>[ 0.042031] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10342 23:04:21.024091 <6>[ 0.051442] cblist_init_generic: Setting adjustable number of callback queues.
10343 23:04:21.029857 <6>[ 0.058886] cblist_init_generic: Setting shift to 3 and lim to 1.
10344 23:04:21.036714 <6>[ 0.065224] cblist_init_generic: Setting adjustable number of callback queues.
10345 23:04:21.043325 <6>[ 0.072650] cblist_init_generic: Setting shift to 3 and lim to 1.
10346 23:04:21.046770 <6>[ 0.079050] rcu: Hierarchical SRCU implementation.
10347 23:04:21.053231 <6>[ 0.084065] rcu: Max phase no-delay instances is 1000.
10348 23:04:21.060263 <6>[ 0.091128] EFI services will not be available.
10349 23:04:21.063235 <6>[ 0.096115] smp: Bringing up secondary CPUs ...
10350 23:04:21.072006 <6>[ 0.101196] Detected VIPT I-cache on CPU1
10351 23:04:21.078218 <6>[ 0.101264] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10352 23:04:21.085029 <6>[ 0.101295] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10353 23:04:21.088637 <6>[ 0.101627] Detected VIPT I-cache on CPU2
10354 23:04:21.098079 <6>[ 0.101674] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10355 23:04:21.104653 <6>[ 0.101689] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10356 23:04:21.108083 <6>[ 0.101946] Detected VIPT I-cache on CPU3
10357 23:04:21.114908 <6>[ 0.101992] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10358 23:04:21.121453 <6>[ 0.102005] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10359 23:04:21.127468 <6>[ 0.102305] CPU features: detected: Spectre-v4
10360 23:04:21.131217 <6>[ 0.102312] CPU features: detected: Spectre-BHB
10361 23:04:21.134208 <6>[ 0.102317] Detected PIPT I-cache on CPU4
10362 23:04:21.141142 <6>[ 0.102373] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10363 23:04:21.150896 <6>[ 0.102390] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10364 23:04:21.154007 <6>[ 0.102681] Detected PIPT I-cache on CPU5
10365 23:04:21.160847 <6>[ 0.102743] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10366 23:04:21.167125 <6>[ 0.102759] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10367 23:04:21.170563 <6>[ 0.103042] Detected PIPT I-cache on CPU6
10368 23:04:21.180077 <6>[ 0.103106] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10369 23:04:21.186773 <6>[ 0.103122] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10370 23:04:21.190418 <6>[ 0.103420] Detected PIPT I-cache on CPU7
10371 23:04:21.196746 <6>[ 0.103483] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10372 23:04:21.203459 <6>[ 0.103499] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10373 23:04:21.206735 <6>[ 0.103546] smp: Brought up 1 node, 8 CPUs
10374 23:04:21.213228 <6>[ 0.244829] SMP: Total of 8 processors activated.
10375 23:04:21.220002 <6>[ 0.249781] CPU features: detected: 32-bit EL0 Support
10376 23:04:21.226418 <6>[ 0.255178] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10377 23:04:21.233355 <6>[ 0.264033] CPU features: detected: Common not Private translations
10378 23:04:21.239968 <6>[ 0.270509] CPU features: detected: CRC32 instructions
10379 23:04:21.245948 <6>[ 0.275860] CPU features: detected: RCpc load-acquire (LDAPR)
10380 23:04:21.249685 <6>[ 0.281821] CPU features: detected: LSE atomic instructions
10381 23:04:21.256251 <6>[ 0.287602] CPU features: detected: Privileged Access Never
10382 23:04:21.262666 <6>[ 0.293417] CPU features: detected: RAS Extension Support
10383 23:04:21.269057 <6>[ 0.299026] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10384 23:04:21.272874 <6>[ 0.306246] CPU: All CPU(s) started at EL2
10385 23:04:21.278876 <6>[ 0.310562] alternatives: applying system-wide alternatives
10386 23:04:21.289335 <6>[ 0.321303] devtmpfs: initialized
10387 23:04:21.305446 <6>[ 0.330283] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10388 23:04:21.311729 <6>[ 0.340243] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10389 23:04:21.318226 <6>[ 0.348502] pinctrl core: initialized pinctrl subsystem
10390 23:04:21.321458 <6>[ 0.355145] DMI not present or invalid.
10391 23:04:21.328379 <6>[ 0.359554] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10392 23:04:21.338299 <6>[ 0.366439] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10393 23:04:21.344970 <6>[ 0.374021] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10394 23:04:21.354433 <6>[ 0.382249] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10395 23:04:21.357979 <6>[ 0.390492] audit: initializing netlink subsys (disabled)
10396 23:04:21.367490 <5>[ 0.396184] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10397 23:04:21.374333 <6>[ 0.396881] thermal_sys: Registered thermal governor 'step_wise'
10398 23:04:21.380938 <6>[ 0.404153] thermal_sys: Registered thermal governor 'power_allocator'
10399 23:04:21.384927 <6>[ 0.410407] cpuidle: using governor menu
10400 23:04:21.391169 <6>[ 0.421368] NET: Registered PF_QIPCRTR protocol family
10401 23:04:21.397583 <6>[ 0.426850] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10402 23:04:21.403718 <6>[ 0.433953] ASID allocator initialised with 32768 entries
10403 23:04:21.407019 <6>[ 0.440512] Serial: AMBA PL011 UART driver
10404 23:04:21.417536 <4>[ 0.449297] Trying to register duplicate clock ID: 134
10405 23:04:21.474403 <6>[ 0.508930] KASLR enabled
10406 23:04:21.488524 <6>[ 0.516673] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10407 23:04:21.494904 <6>[ 0.523686] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10408 23:04:21.502139 <6>[ 0.530175] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10409 23:04:21.507971 <6>[ 0.537176] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10410 23:04:21.514701 <6>[ 0.543662] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10411 23:04:21.521325 <6>[ 0.550666] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10412 23:04:21.527473 <6>[ 0.557153] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10413 23:04:21.534484 <6>[ 0.564159] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10414 23:04:21.537748 <6>[ 0.571680] ACPI: Interpreter disabled.
10415 23:04:21.546168 <6>[ 0.578089] iommu: Default domain type: Translated
10416 23:04:21.552838 <6>[ 0.583201] iommu: DMA domain TLB invalidation policy: strict mode
10417 23:04:21.556172 <5>[ 0.589861] SCSI subsystem initialized
10418 23:04:21.562748 <6>[ 0.594025] usbcore: registered new interface driver usbfs
10419 23:04:21.569581 <6>[ 0.599758] usbcore: registered new interface driver hub
10420 23:04:21.572774 <6>[ 0.605308] usbcore: registered new device driver usb
10421 23:04:21.579885 <6>[ 0.611410] pps_core: LinuxPPS API ver. 1 registered
10422 23:04:21.589692 <6>[ 0.616605] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10423 23:04:21.592624 <6>[ 0.625953] PTP clock support registered
10424 23:04:21.596552 <6>[ 0.630189] EDAC MC: Ver: 3.0.0
10425 23:04:21.603534 <6>[ 0.635346] FPGA manager framework
10426 23:04:21.609952 <6>[ 0.639024] Advanced Linux Sound Architecture Driver Initialized.
10427 23:04:21.613388 <6>[ 0.645808] vgaarb: loaded
10428 23:04:21.619745 <6>[ 0.648969] clocksource: Switched to clocksource arch_sys_counter
10429 23:04:21.623223 <5>[ 0.655407] VFS: Disk quotas dquot_6.6.0
10430 23:04:21.629996 <6>[ 0.659595] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10431 23:04:21.633271 <6>[ 0.666786] pnp: PnP ACPI: disabled
10432 23:04:21.641430 <6>[ 0.673500] NET: Registered PF_INET protocol family
10433 23:04:21.651415 <6>[ 0.679095] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10434 23:04:21.662819 <6>[ 0.691409] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10435 23:04:21.673067 <6>[ 0.700219] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10436 23:04:21.679300 <6>[ 0.708188] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10437 23:04:21.686058 <6>[ 0.716887] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10438 23:04:21.694829 <6>[ 0.726648] TCP: Hash tables configured (established 65536 bind 65536)
10439 23:04:21.705207 <6>[ 0.733511] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10440 23:04:21.711409 <6>[ 0.740711] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10441 23:04:21.718017 <6>[ 0.748414] NET: Registered PF_UNIX/PF_LOCAL protocol family
10442 23:04:21.724622 <6>[ 0.754567] RPC: Registered named UNIX socket transport module.
10443 23:04:21.727594 <6>[ 0.760722] RPC: Registered udp transport module.
10444 23:04:21.734733 <6>[ 0.765655] RPC: Registered tcp transport module.
10445 23:04:21.740662 <6>[ 0.770585] RPC: Registered tcp NFSv4.1 backchannel transport module.
10446 23:04:21.744488 <6>[ 0.777250] PCI: CLS 0 bytes, default 64
10447 23:04:21.747484 <6>[ 0.781584] Unpacking initramfs...
10448 23:04:21.772534 <6>[ 0.801092] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10449 23:04:21.782175 <6>[ 0.809742] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10450 23:04:21.785539 <6>[ 0.818586] kvm [1]: IPA Size Limit: 40 bits
10451 23:04:21.792355 <6>[ 0.823114] kvm [1]: GICv3: no GICV resource entry
10452 23:04:21.795673 <6>[ 0.828136] kvm [1]: disabling GICv2 emulation
10453 23:04:21.802002 <6>[ 0.832827] kvm [1]: GIC system register CPU interface enabled
10454 23:04:21.805991 <6>[ 0.838988] kvm [1]: vgic interrupt IRQ18
10455 23:04:21.812208 <6>[ 0.843359] kvm [1]: VHE mode initialized successfully
10456 23:04:21.818841 <5>[ 0.849875] Initialise system trusted keyrings
10457 23:04:21.825679 <6>[ 0.854712] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10458 23:04:21.832877 <6>[ 0.864729] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10459 23:04:21.839681 <5>[ 0.871099] NFS: Registering the id_resolver key type
10460 23:04:21.842855 <5>[ 0.876398] Key type id_resolver registered
10461 23:04:21.849110 <5>[ 0.880811] Key type id_legacy registered
10462 23:04:21.855735 <6>[ 0.885090] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10463 23:04:21.862626 <6>[ 0.892011] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10464 23:04:21.868814 <6>[ 0.899724] 9p: Installing v9fs 9p2000 file system support
10465 23:04:21.905325 <5>[ 0.937424] Key type asymmetric registered
10466 23:04:21.909219 <5>[ 0.941759] Asymmetric key parser 'x509' registered
10467 23:04:21.918803 <6>[ 0.946903] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10468 23:04:21.921832 <6>[ 0.954514] io scheduler mq-deadline registered
10469 23:04:21.925228 <6>[ 0.959299] io scheduler kyber registered
10470 23:04:21.944121 <6>[ 0.976288] EINJ: ACPI disabled.
10471 23:04:21.976586 <4>[ 1.002133] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10472 23:04:21.986485 <4>[ 1.012780] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10473 23:04:22.001355 <6>[ 1.033657] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10474 23:04:22.009710 <6>[ 1.041719] printk: console [ttyS0] disabled
10475 23:04:22.037821 <6>[ 1.066365] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10476 23:04:22.044186 <6>[ 1.075839] printk: console [ttyS0] enabled
10477 23:04:22.047729 <6>[ 1.075839] printk: console [ttyS0] enabled
10478 23:04:22.054153 <6>[ 1.084735] printk: bootconsole [mtk8250] disabled
10479 23:04:22.057405 <6>[ 1.084735] printk: bootconsole [mtk8250] disabled
10480 23:04:22.064099 <6>[ 1.095962] SuperH (H)SCI(F) driver initialized
10481 23:04:22.067641 <6>[ 1.101279] msm_serial: driver initialized
10482 23:04:22.081861 <6>[ 1.110341] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10483 23:04:22.091518 <6>[ 1.118888] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10484 23:04:22.098225 <6>[ 1.127431] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10485 23:04:22.108601 <6>[ 1.136059] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10486 23:04:22.118316 <6>[ 1.144766] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10487 23:04:22.124747 <6>[ 1.153486] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10488 23:04:22.135317 <6>[ 1.162028] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10489 23:04:22.141704 <6>[ 1.170848] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10490 23:04:22.151090 <6>[ 1.179395] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10491 23:04:22.163442 <6>[ 1.195204] loop: module loaded
10492 23:04:22.170404 <6>[ 1.201202] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10493 23:04:22.192869 <4>[ 1.224658] mtk-pmic-keys: Failed to locate of_node [id: -1]
10494 23:04:22.200028 <6>[ 1.231720] megasas: 07.719.03.00-rc1
10495 23:04:22.209464 <6>[ 1.241418] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10496 23:04:22.216467 <6>[ 1.248360] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10497 23:04:22.233176 <6>[ 1.265068] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10498 23:04:22.290053 <6>[ 1.315358] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10499 23:04:22.494339 <6>[ 1.526159] Freeing initrd memory: 17376K
10500 23:04:22.505321 <6>[ 1.536395] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10501 23:04:22.515313 <6>[ 1.547494] tun: Universal TUN/TAP device driver, 1.6
10502 23:04:22.518619 <6>[ 1.553558] thunder_xcv, ver 1.0
10503 23:04:22.522117 <6>[ 1.557060] thunder_bgx, ver 1.0
10504 23:04:22.525577 <6>[ 1.560553] nicpf, ver 1.0
10505 23:04:22.536475 <6>[ 1.564576] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10506 23:04:22.540060 <6>[ 1.572052] hns3: Copyright (c) 2017 Huawei Corporation.
10507 23:04:22.546227 <6>[ 1.577642] hclge is initializing
10508 23:04:22.549594 <6>[ 1.581223] e1000: Intel(R) PRO/1000 Network Driver
10509 23:04:22.555991 <6>[ 1.586352] e1000: Copyright (c) 1999-2006 Intel Corporation.
10510 23:04:22.558948 <6>[ 1.592365] e1000e: Intel(R) PRO/1000 Network Driver
10511 23:04:22.565752 <6>[ 1.597580] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10512 23:04:22.572235 <6>[ 1.603765] igb: Intel(R) Gigabit Ethernet Network Driver
10513 23:04:22.580078 <6>[ 1.609416] igb: Copyright (c) 2007-2014 Intel Corporation.
10514 23:04:22.585896 <6>[ 1.615251] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10515 23:04:22.592119 <6>[ 1.621769] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10516 23:04:22.595592 <6>[ 1.628233] sky2: driver version 1.30
10517 23:04:22.602046 <6>[ 1.633241] VFIO - User Level meta-driver version: 0.3
10518 23:04:22.609435 <6>[ 1.641484] usbcore: registered new interface driver usb-storage
10519 23:04:22.616456 <6>[ 1.647929] usbcore: registered new device driver onboard-usb-hub
10520 23:04:22.625036 <6>[ 1.657091] mt6397-rtc mt6359-rtc: registered as rtc0
10521 23:04:22.635236 <6>[ 1.662554] mt6397-rtc mt6359-rtc: setting system clock to 2023-12-01T23:04:22 UTC (1701471862)
10522 23:04:22.638111 <6>[ 1.672117] i2c_dev: i2c /dev entries driver
10523 23:04:22.655067 <6>[ 1.683908] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10524 23:04:22.675826 <6>[ 1.707894] cpu cpu0: EM: created perf domain
10525 23:04:22.678968 <6>[ 1.712832] cpu cpu4: EM: created perf domain
10526 23:04:22.686532 <6>[ 1.718435] sdhci: Secure Digital Host Controller Interface driver
10527 23:04:22.693403 <6>[ 1.724869] sdhci: Copyright(c) Pierre Ossman
10528 23:04:22.700498 <6>[ 1.729827] Synopsys Designware Multimedia Card Interface Driver
10529 23:04:22.706723 <6>[ 1.736443] sdhci-pltfm: SDHCI platform and OF driver helper
10530 23:04:22.710036 <6>[ 1.736451] mmc0: CQHCI version 5.10
10531 23:04:22.716522 <6>[ 1.746813] ledtrig-cpu: registered to indicate activity on CPUs
10532 23:04:22.723026 <6>[ 1.753853] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10533 23:04:22.729860 <6>[ 1.760909] usbcore: registered new interface driver usbhid
10534 23:04:22.732910 <6>[ 1.766731] usbhid: USB HID core driver
10535 23:04:22.739283 <6>[ 1.770925] spi_master spi0: will run message pump with realtime priority
10536 23:04:22.782870 <6>[ 1.808477] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10537 23:04:22.802806 <6>[ 1.824573] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10538 23:04:22.810334 <6>[ 1.839256] cros-ec-spi spi0.0: Chrome EC device registered
10539 23:04:22.813737 <6>[ 1.845281] mmc0: Command Queue Engine enabled
10540 23:04:22.820474 <6>[ 1.850046] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10541 23:04:22.826650 <6>[ 1.857687] mmcblk0: mmc0:0001 DA4128 116 GiB
10542 23:04:22.835173 <6>[ 1.866932] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10543 23:04:22.842923 <6>[ 1.874174] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10544 23:04:22.852539 <6>[ 1.878647] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10545 23:04:22.856460 <6>[ 1.880139] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10546 23:04:22.862107 <6>[ 1.889955] NET: Registered PF_PACKET protocol family
10547 23:04:22.869361 <6>[ 1.894624] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10548 23:04:22.872437 <6>[ 1.899328] 9pnet: Installing 9P2000 support
10549 23:04:22.878994 <5>[ 1.910325] Key type dns_resolver registered
10550 23:04:22.882681 <6>[ 1.915275] registered taskstats version 1
10551 23:04:22.889223 <5>[ 1.919656] Loading compiled-in X.509 certificates
10552 23:04:22.918497 <4>[ 1.943073] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10553 23:04:22.927608 <4>[ 1.954006] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10554 23:04:22.934615 <3>[ 1.964552] debugfs: File 'uA_load' in directory '/' already present!
10555 23:04:22.940927 <3>[ 1.971311] debugfs: File 'min_uV' in directory '/' already present!
10556 23:04:22.948007 <3>[ 1.977943] debugfs: File 'max_uV' in directory '/' already present!
10557 23:04:22.954219 <3>[ 1.984570] debugfs: File 'constraint_flags' in directory '/' already present!
10558 23:04:22.966022 <3>[ 1.994369] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10559 23:04:22.975320 <6>[ 2.007020] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10560 23:04:22.982453 <6>[ 2.013818] xhci-mtk 11200000.usb: xHCI Host Controller
10561 23:04:22.988454 <6>[ 2.019337] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10562 23:04:22.998952 <6>[ 2.027221] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10563 23:04:23.005497 <6>[ 2.036653] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10564 23:04:23.011989 <6>[ 2.042718] xhci-mtk 11200000.usb: xHCI Host Controller
10565 23:04:23.019212 <6>[ 2.048192] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10566 23:04:23.025618 <6>[ 2.055836] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10567 23:04:23.031695 <6>[ 2.063456] hub 1-0:1.0: USB hub found
10568 23:04:23.035082 <6>[ 2.067467] hub 1-0:1.0: 1 port detected
10569 23:04:23.041842 <6>[ 2.071702] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10570 23:04:23.048683 <6>[ 2.080353] hub 2-0:1.0: USB hub found
10571 23:04:23.051576 <6>[ 2.084368] hub 2-0:1.0: 1 port detected
10572 23:04:23.060469 <6>[ 2.092420] mtk-msdc 11f70000.mmc: Got CD GPIO
10573 23:04:23.072310 <6>[ 2.100472] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10574 23:04:23.078927 <6>[ 2.108500] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10575 23:04:23.089126 <4>[ 2.116419] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10576 23:04:23.098084 <6>[ 2.125953] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10577 23:04:23.105254 <6>[ 2.134029] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10578 23:04:23.111866 <6>[ 2.142144] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10579 23:04:23.121687 <6>[ 2.150067] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10580 23:04:23.128229 <6>[ 2.157885] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10581 23:04:23.138195 <6>[ 2.165702] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10582 23:04:23.148316 <6>[ 2.176102] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10583 23:04:23.155230 <6>[ 2.184466] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10584 23:04:23.165414 <6>[ 2.192806] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10585 23:04:23.172135 <6>[ 2.201146] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10586 23:04:23.181599 <6>[ 2.209485] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10587 23:04:23.187813 <6>[ 2.217825] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10588 23:04:23.198078 <6>[ 2.226163] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10589 23:04:23.204487 <6>[ 2.234501] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10590 23:04:23.214564 <6>[ 2.242839] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10591 23:04:23.221562 <6>[ 2.251183] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10592 23:04:23.231008 <6>[ 2.259522] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10593 23:04:23.238244 <6>[ 2.267861] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10594 23:04:23.248226 <6>[ 2.276202] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10595 23:04:23.254596 <6>[ 2.284542] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10596 23:04:23.264486 <6>[ 2.292890] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10597 23:04:23.271452 <6>[ 2.301642] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10598 23:04:23.278153 <6>[ 2.308787] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10599 23:04:23.283978 <6>[ 2.315548] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10600 23:04:23.290932 <6>[ 2.322302] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10601 23:04:23.300892 <6>[ 2.329230] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10602 23:04:23.307350 <6>[ 2.336077] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10603 23:04:23.317032 <6>[ 2.345203] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10604 23:04:23.327243 <6>[ 2.354322] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10605 23:04:23.337091 <6>[ 2.363616] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10606 23:04:23.347177 <6>[ 2.373087] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10607 23:04:23.353755 <6>[ 2.382554] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10608 23:04:23.363363 <6>[ 2.391675] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10609 23:04:23.373816 <6>[ 2.401143] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10610 23:04:23.383486 <6>[ 2.410260] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10611 23:04:23.393278 <6>[ 2.419554] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10612 23:04:23.403776 <6>[ 2.429714] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10613 23:04:23.412734 <6>[ 2.441455] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10614 23:04:23.419705 <6>[ 2.451181] Trying to probe devices needed for running init ...
10615 23:04:23.440850 <6>[ 2.469279] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10616 23:04:23.468099 <6>[ 2.500822] hub 2-1:1.0: USB hub found
10617 23:04:23.471637 <6>[ 2.505309] hub 2-1:1.0: 3 ports detected
10618 23:04:23.480603 <6>[ 2.512721] hub 2-1:1.0: USB hub found
10619 23:04:23.484039 <6>[ 2.517147] hub 2-1:1.0: 3 ports detected
10620 23:04:23.592699 <6>[ 2.621241] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10621 23:04:23.746749 <6>[ 2.779033] hub 1-1:1.0: USB hub found
10622 23:04:23.749789 <6>[ 2.783492] hub 1-1:1.0: 4 ports detected
10623 23:04:23.760151 <6>[ 2.792578] hub 1-1:1.0: USB hub found
10624 23:04:23.763511 <6>[ 2.797209] hub 1-1:1.0: 4 ports detected
10625 23:04:23.832554 <6>[ 2.861492] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10626 23:04:24.084264 <6>[ 3.113280] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10627 23:04:24.217441 <6>[ 3.249112] hub 1-1.4:1.0: USB hub found
10628 23:04:24.220250 <6>[ 3.253778] hub 1-1.4:1.0: 2 ports detected
10629 23:04:24.230590 <6>[ 3.262468] hub 1-1.4:1.0: USB hub found
10630 23:04:24.233564 <6>[ 3.267055] hub 1-1.4:1.0: 2 ports detected
10631 23:04:24.532559 <6>[ 3.561262] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10632 23:04:24.724069 <6>[ 3.753266] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10633 23:04:35.697689 <6>[ 14.734248] ALSA device list:
10634 23:04:35.703874 <6>[ 14.737540] No soundcards found.
10635 23:04:35.712045 <6>[ 14.745543] Freeing unused kernel memory: 8448K
10636 23:04:35.715533 <6>[ 14.750523] Run /init as init process
10637 23:04:35.726794 Loading, please wait...
10638 23:04:35.747064 Starting version 247.3-7+deb11u2
10639 23:04:35.953066 <6>[ 14.981350] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10640 23:04:35.962429 <3>[ 14.992471] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10641 23:04:35.968946 <3>[ 15.000693] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10642 23:04:35.979814 <3>[ 15.008814] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10643 23:04:35.990114 <3>[ 15.019717] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10644 23:04:35.996437 <6>[ 15.021842] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10645 23:04:36.006150 <6>[ 15.021930] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10646 23:04:36.012681 <4>[ 15.022676] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10647 23:04:36.015897 <6>[ 15.027194] remoteproc remoteproc0: scp is available
10648 23:04:36.025678 <4>[ 15.027230] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10649 23:04:36.029080 <6>[ 15.027307] remoteproc remoteproc0: powering up scp
10650 23:04:36.040304 <6>[ 15.027314] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10651 23:04:36.042495 <6>[ 15.027333] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10652 23:04:36.052407 <3>[ 15.027869] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10653 23:04:36.059692 <3>[ 15.027875] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10654 23:04:36.068921 <3>[ 15.027883] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10655 23:04:36.076079 <3>[ 15.027886] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10656 23:04:36.086165 <3>[ 15.029004] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10657 23:04:36.092029 <6>[ 15.035526] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10658 23:04:36.102119 <3>[ 15.054288] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10659 23:04:36.108970 <6>[ 15.055740] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10660 23:04:36.118808 <3>[ 15.063346] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10661 23:04:36.122163 <6>[ 15.064713] mc: Linux media interface: v0.10
10662 23:04:36.129338 <6>[ 15.083099] videodev: Linux video capture interface: v2.00
10663 23:04:36.134898 <6>[ 15.086521] usbcore: registered new interface driver r8152
10664 23:04:36.142107 <3>[ 15.090488] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10665 23:04:36.148837 <6>[ 15.152919] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10666 23:04:36.158550 <6>[ 15.152942] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10667 23:04:36.164887 <6>[ 15.152949] remoteproc remoteproc0: remote processor scp is now up
10668 23:04:36.171673 <3>[ 15.156610] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10669 23:04:36.181840 <6>[ 15.156662] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10670 23:04:36.188341 <6>[ 15.169286] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10671 23:04:36.198363 <3>[ 15.172486] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10672 23:04:36.207399 <6>[ 15.189393] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10673 23:04:36.214169 <3>[ 15.196003] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10674 23:04:36.223784 <3>[ 15.196011] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10675 23:04:36.230967 <3>[ 15.196017] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10676 23:04:36.241495 <3>[ 15.196052] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10677 23:04:36.247486 <6>[ 15.202955] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10678 23:04:36.257718 <4>[ 15.204400] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10679 23:04:36.264746 <4>[ 15.204409] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10680 23:04:36.273750 <6>[ 15.209424] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10681 23:04:36.276759 <6>[ 15.209434] pci_bus 0000:00: root bus resource [bus 00-ff]
10682 23:04:36.284002 <6>[ 15.209444] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10683 23:04:36.293960 <6>[ 15.209451] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10684 23:04:36.300182 <6>[ 15.209495] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10685 23:04:36.310782 <6>[ 15.209520] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10686 23:04:36.313989 <6>[ 15.209624] pci 0000:00:00.0: supports D1 D2
10687 23:04:36.320864 <6>[ 15.209629] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10688 23:04:36.327816 <6>[ 15.212406] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10689 23:04:36.337076 <6>[ 15.236798] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10690 23:04:36.341160 <6>[ 15.245203] r8152 2-1.3:1.0 eth0: v1.12.13
10691 23:04:36.350895 <4>[ 15.249763] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10692 23:04:36.354416 <4>[ 15.249763] Fallback method does not support PEC.
10693 23:04:36.361174 <6>[ 15.253578] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10694 23:04:36.368091 <6>[ 15.253990] usbcore: registered new interface driver cdc_ether
10695 23:04:36.374516 <6>[ 15.256490] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10696 23:04:36.380476 <6>[ 15.270316] usbcore: registered new interface driver r8153_ecm
10697 23:04:36.387318 <6>[ 15.277794] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10698 23:04:36.394177 <6>[ 15.287488] Bluetooth: Core ver 2.22
10699 23:04:36.400946 <6>[ 15.288744] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10700 23:04:36.414019 <6>[ 15.289855] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10701 23:04:36.417204 <6>[ 15.290026] usbcore: registered new interface driver uvcvideo
10702 23:04:36.427076 <6>[ 15.295829] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10703 23:04:36.430759 <6>[ 15.296459] r8152 2-1.3:1.0 enx002432307c7b: renamed from eth0
10704 23:04:36.436414 <6>[ 15.303915] NET: Registered PF_BLUETOOTH protocol family
10705 23:04:36.443178 <6>[ 15.304482] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10706 23:04:36.450193 <6>[ 15.310752] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10707 23:04:36.457230 <6>[ 15.316443] Bluetooth: HCI device and connection manager initialized
10708 23:04:36.463210 <6>[ 15.316454] Bluetooth: HCI socket layer initialized
10709 23:04:36.466618 <6>[ 15.323799] pci 0000:01:00.0: supports D1 D2
10710 23:04:36.473262 <6>[ 15.333476] Bluetooth: L2CAP socket layer initialized
10711 23:04:36.476789 <6>[ 15.333489] Bluetooth: SCO socket layer initialized
10712 23:04:36.486200 <6>[ 15.339735] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10713 23:04:36.492983 <3>[ 15.351305] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10714 23:04:36.499884 <6>[ 15.361093] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10715 23:04:36.509840 <3>[ 15.391842] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10716 23:04:36.516331 <6>[ 15.393121] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10717 23:04:36.522687 <6>[ 15.399791] usbcore: registered new interface driver btusb
10718 23:04:36.532371 <4>[ 15.400502] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10719 23:04:36.539416 <3>[ 15.400517] Bluetooth: hci0: Failed to load firmware file (-2)
10720 23:04:36.545735 <3>[ 15.400524] Bluetooth: hci0: Failed to set up firmware (-2)
10721 23:04:36.555384 <4>[ 15.400531] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10722 23:04:36.562996 <6>[ 15.405428] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10723 23:04:36.572264 <6>[ 15.405438] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10724 23:04:36.578966 <6>[ 15.610109] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10725 23:04:36.589250 <6>[ 15.618112] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10726 23:04:36.592328 <6>[ 15.626183] pci 0000:00:00.0: PCI bridge to [bus 01]
10727 23:04:36.602540 <6>[ 15.631400] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10728 23:04:36.608436 <6>[ 15.639533] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10729 23:04:36.615140 <6>[ 15.646339] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10730 23:04:36.621510 <6>[ 15.652718] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10731 23:04:36.635372 <5>[ 15.665826] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10732 23:04:36.657236 <5>[ 15.687012] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10733 23:04:36.663960 <4>[ 15.693944] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10734 23:04:36.669943 <6>[ 15.702838] cfg80211: failed to load regulatory.db
10735 23:04:36.718811 <6>[ 15.749155] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10736 23:04:36.725934 <6>[ 15.756686] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10737 23:04:36.749932 <6>[ 15.783401] mt7921e 0000:01:00.0: ASIC revision: 79610010
10738 23:04:36.857886 <4>[ 15.884623] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10739 23:04:36.860920 Begin: Loading essential drivers ... done.
10740 23:04:36.865216 Begin: Running /scripts/init-premount ... done.
10741 23:04:36.874525 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10742 23:04:36.880766 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10743 23:04:36.884028 Device /sys/class/net/enx002432307c7b found
10744 23:04:36.887837 done.
10745 23:04:36.927178 IP-Config: enx002432307c7b hardware address 00:24:32:30:7c:7b mtu 1500 DHCP
10746 23:04:36.978034 <4>[ 16.004752] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10747 23:04:37.098208 <4>[ 16.124798] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10748 23:04:37.218067 <4>[ 16.244792] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10749 23:04:37.338040 <4>[ 16.364799] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10750 23:04:37.457989 <4>[ 16.484752] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10751 23:04:37.577997 <4>[ 16.604875] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10752 23:04:37.698322 <4>[ 16.724815] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10753 23:04:37.817784 <4>[ 16.844818] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10754 23:04:37.938363 <4>[ 16.964759] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10755 23:04:37.945862 <6>[ 16.979183] r8152 2-1.3:1.0 enx002432307c7b: carrier on
10756 23:04:38.049179 <3>[ 17.082747] mt7921e 0000:01:00.0: hardware init failed
10757 23:04:38.129145 IP-Config: no response after 2 secs - giving up
10758 23:04:38.162832 IP-Config: enx002432307c7b hardware address 00:24:32:30:7c:7b mtu 1500 DHCP
10759 23:04:38.169644 IP-Config: enx002432307c7b complete (dhcp from 192.168.201.1):
10760 23:04:38.176699 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10761 23:04:38.183030 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10762 23:04:38.189503 host : mt8192-asurada-spherion-r0-cbg-2
10763 23:04:38.196149 domain : lava-rack
10764 23:04:38.199226 rootserver: 192.168.201.1 rootpath:
10765 23:04:38.199839 filename :
10766 23:04:38.297384 done.
10767 23:04:38.305811 Begin: Running /scripts/nfs-bottom ... done.
10768 23:04:38.325662 Begin: Running /scripts/init-bottom ... done.
10769 23:04:39.589219 <6>[ 18.622207] NET: Registered PF_INET6 protocol family
10770 23:04:39.595841 <6>[ 18.629485] Segment Routing with IPv6
10771 23:04:39.599088 <6>[ 18.633497] In-situ OAM (IOAM) with IPv6
10772 23:04:39.738379 <30>[ 18.752334] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10773 23:04:39.741546 <30>[ 18.776632] systemd[1]: Detected architecture arm64.
10774 23:04:39.765101
10775 23:04:39.768696 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10776 23:04:39.769084
10777 23:04:39.786186 <30>[ 18.820325] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10778 23:04:40.766604 <30>[ 19.796707] systemd[1]: Queued start job for default target Graphical Interface.
10779 23:04:40.810329 <30>[ 19.843627] systemd[1]: Created slice system-getty.slice.
10780 23:04:40.816273 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10781 23:04:40.833012 <30>[ 19.866662] systemd[1]: Created slice system-modprobe.slice.
10782 23:04:40.839410 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10783 23:04:40.857821 <30>[ 19.891377] systemd[1]: Created slice system-serial\x2dgetty.slice.
10784 23:04:40.868255 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10785 23:04:40.880662 <30>[ 19.914286] systemd[1]: Created slice User and Session Slice.
10786 23:04:40.886796 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10787 23:04:40.908238 <30>[ 19.938094] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10788 23:04:40.917254 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10789 23:04:40.935362 <30>[ 19.966033] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10790 23:04:40.941807 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10791 23:04:40.966370 <30>[ 19.993415] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10792 23:04:40.973488 <30>[ 20.005576] systemd[1]: Reached target Local Encrypted Volumes.
10793 23:04:40.979961 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10794 23:04:40.996501 <30>[ 20.029804] systemd[1]: Reached target Paths.
10795 23:04:41.002720 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10796 23:04:41.015191 <30>[ 20.049265] systemd[1]: Reached target Remote File Systems.
10797 23:04:41.022180 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10798 23:04:41.035815 <30>[ 20.069448] systemd[1]: Reached target Slices.
10799 23:04:41.039449 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10800 23:04:41.056328 <30>[ 20.089340] systemd[1]: Reached target Swap.
10801 23:04:41.058498 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10802 23:04:41.079531 <30>[ 20.109762] systemd[1]: Listening on initctl Compatibility Named Pipe.
10803 23:04:41.086138 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10804 23:04:41.092385 <30>[ 20.126180] systemd[1]: Listening on Journal Audit Socket.
10805 23:04:41.098796 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10806 23:04:41.117551 <30>[ 20.151065] systemd[1]: Listening on Journal Socket (/dev/log).
10807 23:04:41.123724 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10808 23:04:41.140260 <30>[ 20.173820] systemd[1]: Listening on Journal Socket.
10809 23:04:41.146404 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10810 23:04:41.164610 <30>[ 20.195013] systemd[1]: Listening on Network Service Netlink Socket.
10811 23:04:41.170863 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10812 23:04:41.186864 <30>[ 20.220778] systemd[1]: Listening on udev Control Socket.
10813 23:04:41.193862 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10814 23:04:41.208382 <30>[ 20.241683] systemd[1]: Listening on udev Kernel Socket.
10815 23:04:41.214334 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10816 23:04:41.267657 <30>[ 20.301455] systemd[1]: Mounting Huge Pages File System...
10817 23:04:41.274354 Mounting [0;1;39mHuge Pages File System[0m...
10818 23:04:41.294855 <30>[ 20.325685] systemd[1]: Mounting POSIX Message Queue File System...
10819 23:04:41.297806 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10820 23:04:41.319909 <30>[ 20.353725] systemd[1]: Mounting Kernel Debug File System...
10821 23:04:41.326364 Mounting [0;1;39mKernel Debug File System[0m...
10822 23:04:41.343359 <30>[ 20.373677] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10823 23:04:41.379330 <30>[ 20.409962] systemd[1]: Starting Create list of static device nodes for the current kernel...
10824 23:04:41.389001 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10825 23:04:41.399175 <30>[ 20.433384] systemd[1]: Starting Load Kernel Module configfs...
10826 23:04:41.406516 Starting [0;1;39mLoad Kernel Module configfs[0m...
10827 23:04:41.426646 <30>[ 20.460460] systemd[1]: Starting Load Kernel Module drm...
10828 23:04:41.433297 Starting [0;1;39mLoad Kernel Module drm[0m...
10829 23:04:41.451462 <30>[ 20.485328] systemd[1]: Starting Load Kernel Module fuse...
10830 23:04:41.458026 Starting [0;1;39mLoad Kernel Module fuse[0m...
10831 23:04:41.483279 <30>[ 20.513701] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10832 23:04:41.498358 <6>[ 20.532288] fuse: init (API version 7.37)
10833 23:04:41.523862 <30>[ 20.557830] systemd[1]: Starting Journal Service...
10834 23:04:41.530181 Starting [0;1;39mJournal Service[0m...
10835 23:04:41.553369 <30>[ 20.587158] systemd[1]: Starting Load Kernel Modules...
10836 23:04:41.559594 Starting [0;1;39mLoad Kernel Modules[0m...
10837 23:04:41.581226 <30>[ 20.612226] systemd[1]: Starting Remount Root and Kernel File Systems...
10838 23:04:41.587725 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10839 23:04:41.607095 <30>[ 20.641727] systemd[1]: Starting Coldplug All udev Devices...
10840 23:04:41.614331 Starting [0;1;39mColdplug All udev Devices[0m...
10841 23:04:41.631376 <30>[ 20.665783] systemd[1]: Mounted Huge Pages File System.
10842 23:04:41.637811 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10843 23:04:41.656219 <30>[ 20.690298] systemd[1]: Mounted POSIX Message Queue File System.
10844 23:04:41.662665 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10845 23:04:41.680491 <30>[ 20.714177] systemd[1]: Mounted Kernel Debug File System.
10846 23:04:41.686768 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10847 23:04:41.708312 <30>[ 20.739066] systemd[1]: Finished Create list of static device nodes for the current kernel.
10848 23:04:41.718149 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10849 23:04:41.733437 <30>[ 20.767329] systemd[1]: modprobe@configfs.service: Succeeded.
10850 23:04:41.741215 <30>[ 20.775497] systemd[1]: Finished Load Kernel Module configfs.
10851 23:04:41.747956 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10852 23:04:41.764817 <30>[ 20.798263] systemd[1]: modprobe@drm.service: Succeeded.
10853 23:04:41.771197 <30>[ 20.804826] systemd[1]: Finished Load Kernel Module drm.
10854 23:04:41.777392 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10855 23:04:41.792649 <30>[ 20.826117] systemd[1]: modprobe@fuse.service: Succeeded.
10856 23:04:41.799012 <30>[ 20.832506] systemd[1]: Finished Load Kernel Module fuse.
10857 23:04:41.805650 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10858 23:04:41.820783 <30>[ 20.854643] systemd[1]: Finished Load Kernel Modules.
10859 23:04:41.831052 <3>[ 20.857272] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10860 23:04:41.837105 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10861 23:04:41.857197 <30>[ 20.887386] systemd[1]: Finished Remount Root and Kernel File Systems.
10862 23:04:41.863517 <3>[ 20.891366] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10863 23:04:41.869952 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10864 23:04:41.902711 <3>[ 20.933598] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10865 23:04:41.919869 <30>[ 20.953533] systemd[1]: Mounting FUSE Control File System...
10866 23:04:41.933151 Mounting [0;1;39mFUSE Control File Sys<3>[ 20.962522] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10867 23:04:41.933578 tem[0m...
10868 23:04:41.949932 <30>[ 20.983902] systemd[1]: Mounting Kernel Configuration File System...
10869 23:04:41.963775 Mounting [0;1;39mKerne<3>[ 20.992891] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10870 23:04:41.966868 l Configuration File System[0m...
10871 23:04:41.993859 <3>[ 21.024547] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10872 23:04:42.004610 <30>[ 21.024720] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10873 23:04:42.013906 <30>[ 21.042450] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10874 23:04:42.035439 <3>[ 21.066152] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10875 23:04:42.045704 <3>[ 21.066917] power_supply sbs-5-000b: driver failed to report `current_avg' property: -6
10876 23:04:42.060410 <30>[ 21.094132] systemd[1]: Starting Load/Save Random Seed...
10877 23:04:42.073672 Starting [0;1;39mLoad/Save Random Seed<3>[ 21.103935] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10878 23:04:42.074227 [0m...
10879 23:04:42.095593 <30>[ 21.129935] systemd[1]: Starting Apply Kernel Variables...
10880 23:04:42.102131 Starting [0;1;39mApply Kernel Variables[0m...
10881 23:04:42.117992 <3>[ 21.148766] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10882 23:04:42.135534 <4>[ 21.157582] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10883 23:04:42.141409 <3>[ 21.173267] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10884 23:04:42.148661 <30>[ 21.176337] systemd[1]: Starting Create System Users...
10885 23:04:42.152352 Starting [0;1;39mCreate System Users[0m...
10886 23:04:42.173986 <29>[ 21.204694] systemd[1]: systemd-udev-trigger.service: Main process exited, code=exited, status=1/FAILURE
10887 23:04:42.184860 <28>[ 21.215364] systemd[1]: systemd-udev-trigger.service: Failed with result 'exit-code'.
10888 23:04:42.191356 <27>[ 21.224480] systemd[1]: Failed to start Coldplug All udev Devices.
10889 23:04:42.198303 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10890 23:04:42.211460 See 'systemctl status systemd-udev-trigger.service' for details.
10891 23:04:42.227695 <30>[ 21.261894] systemd[1]: Started Journal Service.
10892 23:04:42.234442 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10893 23:04:42.249991 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10894 23:04:42.267638 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10895 23:04:42.283489 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10896 23:04:42.301120 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10897 23:04:42.316806 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10898 23:04:42.376508 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10899 23:04:42.393673 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10900 23:04:42.445872 <46>[ 21.476769] systemd-journald[301]: Received client request to flush runtime journal.
10901 23:04:42.951176 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10902 23:04:42.963398 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10903 23:04:42.978538 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10904 23:04:43.026590 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10905 23:04:43.853237 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10906 23:04:43.895925 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10907 23:04:43.970845 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10908 23:04:44.032192 Starting [0;1;39mNetwork Service[0m...
10909 23:04:44.356794 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10910 23:04:44.391398 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10911 23:04:44.447154 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10912 23:04:44.716655 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10913 23:04:44.734258 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10914 23:04:44.783543 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10915 23:04:44.799407 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10916 23:04:44.820145 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10917 23:04:44.852379 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10918 23:04:44.871810 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10919 23:04:44.923375 Starting [0;1;39mNetwork Name Resolution[0m...
10920 23:04:44.952582 Starting [0;1;39mNetwork Time Synchronization[0m...
10921 23:04:44.972574 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10922 23:04:45.042421 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10923 23:04:45.227396 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10924 23:04:45.243464 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10925 23:04:45.262376 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10926 23:04:45.274726 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10927 23:04:45.294879 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10928 23:04:45.418658 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10929 23:04:45.455655 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10930 23:04:45.491027 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10931 23:04:45.531653 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10932 23:04:45.543154 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10933 23:04:45.568975 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10934 23:04:45.582395 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10935 23:04:45.598441 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10936 23:04:45.659529 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10937 23:04:45.714200 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10938 23:04:45.777318 Starting [0;1;39mUser Login Management[0m...
10939 23:04:45.796219 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10940 23:04:45.815617 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10941 23:04:45.834609 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10942 23:04:45.883675 Starting [0;1;39mPermit User Sessions[0m...
10943 23:04:46.005458 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10944 23:04:46.047630 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10945 23:04:46.075410 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10946 23:04:46.091336 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10947 23:04:46.118131 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10948 23:04:46.148431 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10949 23:04:46.164118 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10950 23:04:46.178638 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10951 23:04:46.222144 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10952 23:04:46.275117 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10953 23:04:46.389185
10954 23:04:46.389322
10955 23:04:46.392055 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10956 23:04:46.392137
10957 23:04:46.395234 debian-bullseye-arm64 login: root (automatic login)
10958 23:04:46.395317
10959 23:04:46.395381
10960 23:04:46.737396 Linux debian-bullseye-arm64 6.1.64-cip10 #1 SMP PREEMPT Fri Dec 1 22:47:09 UTC 2023 aarch64
10961 23:04:46.737545
10962 23:04:46.744146 The programs included with the Debian GNU/Linux system are free software;
10963 23:04:46.750174 the exact distribution terms for each program are described in the
10964 23:04:46.753584 individual files in /usr/share/doc/*/copyright.
10965 23:04:46.753665
10966 23:04:46.760256 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10967 23:04:46.763640 permitted by applicable law.
10968 23:04:46.867263 Matched prompt #10: / #
10970 23:04:46.867533 Setting prompt string to ['/ #']
10971 23:04:46.867629 end: 2.2.5.1 login-action (duration 00:00:27) [common]
10973 23:04:46.867822 end: 2.2.5 auto-login-action (duration 00:00:27) [common]
10974 23:04:46.867909 start: 2.2.6 expect-shell-connection (timeout 00:03:12) [common]
10975 23:04:46.867978 Setting prompt string to ['/ #']
10976 23:04:46.868037 Forcing a shell prompt, looking for ['/ #']
10978 23:04:46.918310 / #
10979 23:04:46.918487 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10980 23:04:46.918643 Waiting using forced prompt support (timeout 00:02:30)
10981 23:04:46.923482
10982 23:04:46.923763 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10983 23:04:46.923856 start: 2.2.7 export-device-env (timeout 00:03:12) [common]
10985 23:04:47.024229 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12154430/extract-nfsrootfs-ao66pv48'
10986 23:04:47.030052 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12154430/extract-nfsrootfs-ao66pv48'
10988 23:04:47.130564 / # export NFS_SERVER_IP='192.168.201.1'
10989 23:04:47.135760 export NFS_SERVER_IP='192.168.201.1'
10990 23:04:47.136051 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10991 23:04:47.136149 end: 2.2 depthcharge-retry (duration 00:01:48) [common]
10992 23:04:47.136237 end: 2 depthcharge-action (duration 00:01:48) [common]
10993 23:04:47.136338 start: 3 lava-test-retry (timeout 00:30:00) [common]
10994 23:04:47.136423 start: 3.1 lava-test-shell (timeout 00:30:00) [common]
10995 23:04:47.136526 Using namespace: common
10997 23:04:47.236888 / # #
10998 23:04:47.237101 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:30:00)
10999 23:04:47.241733 #
11000 23:04:47.242002 Using /lava-12154430
11002 23:04:47.342348 / # export SHELL=/bin/sh
11003 23:04:47.347635 export SHELL=/bin/sh
11005 23:04:47.448190 / # . /lava-12154430/environment
11006 23:04:47.453608 . /lava-12154430/environment
11008 23:04:47.559978 / # /lava-12154430/bin/lava-test-runner /lava-12154430/0
11009 23:04:47.560144 Test shell timeout: 10s (minimum of the action and connection timeout)
11010 23:04:47.565211 /lava-12154430/bin/lava-test-runner /lava-12154430/0
11011 23:04:47.840976 + export TESTRUN_ID=0_lc-compliance
11012 23:04:47.847012 + cd /lava-12154430/0/tests/0_lc-compliance
11013 23:04:47.847105 + cat uuid
11014 23:04:47.858490 + UUID=12154430_1.6.2.3.1
11015 23:04:47.858584 + set +x
11016 23:04:47.865357 <LAVA_SIGNAL_STARTRUN 0_lc-compliance 12154430_1.6.2.3.1>
11017 23:04:47.865625 Received signal: <STARTRUN> 0_lc-compliance 12154430_1.6.2.3.1
11018 23:04:47.865700 Starting test lava.0_lc-compliance (12154430_1.6.2.3.1)
11019 23:04:47.865786 Skipping test definition patterns.
11020 23:04:47.868734 + /usr/bin/lc-compliance-parser.sh
11021 23:04:49.107705 [0:00:28.062124991] [406] [1;32m INFO [1;37mCamera [1;34mcamera_manager.cpp:297 [0mlibcamera v0.0.0+1-1f607da9
11022 23:04:49.111480 Using camera /base/soc/usb@11200000-1.4.1:1.0-04f2:b741
11023 23:04:49.129951 [0:00:28.084592790] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11024 23:04:49.190116 [0:00:28.145729967] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11025 23:04:49.209329 [==========] Running 120 tests from 1 test suite.
11026 23:04:49.248803 [0:00:28.204553399] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11027 23:04:49.293690 [----------] Global test environment set-up.
11028 23:04:49.303981 [0:00:28.259470118] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11029 23:04:49.380139 [----------] 120 tests from CaptureTests/SingleStream
11030 23:04:49.470246 [ RUN ] CaptureTests/SingleStream.Capture/Raw_1
11031 23:04:49.535556 <LAVA_SIGNAL_TESTSET START CaptureTests/SingleStream>
11032 23:04:49.535890 Received signal: <TESTSET> START CaptureTests/SingleStream
11033 23:04:49.535971 Starting test_set CaptureTests/SingleStream
11034 23:04:49.538829 Camera needs 4 requests, can't test only 1
11035 23:04:49.625642 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11036 23:04:49.714273
11037 23:04:49.732677 [0:00:28.693637227] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11038 23:04:49.813628 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_1 (63 ms)
11039 23:04:49.922060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_1 RESULT=skip>
11040 23:04:49.922418 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_1 RESULT=skip
11042 23:04:49.940126 [ RUN ] CaptureTests/SingleStream.Capture/Raw_2
11043 23:04:49.998211 Camera needs 4 requests, can't test only 2
11044 23:04:50.093358 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11045 23:04:50.197432 [0:00:29.162628152] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11046 23:04:50.197597
11047 23:04:50.284563 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_2 (58 ms)
11048 23:04:50.398556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_2 RESULT=skip>
11049 23:04:50.398878 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_2 RESULT=skip
11051 23:04:50.418547 [ RUN ] CaptureTests/SingleStream.Capture/Raw_3
11052 23:04:50.480304 Camera needs 4 requests, can't test only 3
11053 23:04:50.568658 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11054 23:04:50.653980
11055 23:04:50.748636 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_3 (54 ms)
11056 23:04:50.851154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_3 RESULT=skip>
11057 23:04:50.851477 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_3 RESULT=skip
11059 23:04:50.870175 [ RUN ] CaptureTests/SingleStream.Capture/Raw_5
11060 23:04:50.894902 [0:00:29.866305796] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11061 23:04:50.933474 [ OK ] CaptureTests/SingleStream.Capture/Raw_5 (435 ms)
11062 23:04:51.036394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_5 RESULT=pass>
11063 23:04:51.036716 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_5 RESULT=pass
11065 23:04:51.054145 [ RUN ] CaptureTests/SingleStream.Capture/Raw_8
11066 23:04:51.111017 [ OK ] CaptureTests/SingleStream.Capture/Raw_8 (468 ms)
11067 23:04:51.213531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_8 RESULT=pass>
11068 23:04:51.213853 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_8 RESULT=pass
11070 23:04:51.233969 [ RUN ] CaptureTests/SingleStream.Capture/Raw_13
11071 23:04:51.296483 [ OK ] CaptureTests/SingleStream.Capture/Raw_13 (703 ms)
11072 23:04:51.398263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_13 RESULT=pass>
11073 23:04:51.398584 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_13 RESULT=pass
11075 23:04:51.415552 [ RUN ] CaptureTests/SingleStream.Capture/Raw_21
11076 23:04:51.784842 [ OK ] CaptureTests/SingleStream.Capture/Raw_21 (907 ms)
11077 23:04:51.794662 [0:00:30.773046002] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11078 23:04:51.901432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_21 RESULT=pass>
11079 23:04:51.901748 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_21 RESULT=pass
11081 23:04:51.923027 [ RUN ] CaptureTests/SingleStream.Capture/Raw_34
11082 23:04:53.120151 [ OK ] CaptureTests/SingleStream.Capture/Raw_34 (1343 ms)
11083 23:04:53.129027 [0:00:32.116685502] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11084 23:04:53.234072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_34 RESULT=pass>
11085 23:04:53.234398 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_34 RESULT=pass
11087 23:04:53.251094 [ RUN ] CaptureTests/SingleStream.Capture/Raw_55
11088 23:04:55.248491 [ OK ] CaptureTests/SingleStream.Capture/Raw_55 (2141 ms)
11089 23:04:55.259082 [0:00:34.258066610] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11090 23:04:55.360667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_55 RESULT=pass>
11091 23:04:55.360963 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_55 RESULT=pass
11093 23:04:55.379743 [ RUN ] CaptureTests/SingleStream.Capture/Raw_89
11094 23:04:58.415123 [ OK ] CaptureTests/SingleStream.Capture/Raw_89 (3179 ms)
11095 23:04:58.425039 [0:00:37.438808776] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11096 23:04:58.482291 [0:00:37.494284264] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11097 23:04:58.536591 [0:00:37.548661406] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11098 23:04:58.540027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_89 RESULT=pass>
11099 23:04:58.540298 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_89 RESULT=pass
11101 23:04:58.551474 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_1
11102 23:04:58.590083 [0:00:37.602241407] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11103 23:04:58.611919 Camera needs 4 requests, can't test only 1
11104 23:04:58.699630 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11105 23:04:58.782921
11106 23:04:58.879351 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_1 (56 ms)
11107 23:04:58.987501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip>
11108 23:04:58.987831 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip
11110 23:04:59.009245 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_2
11111 23:04:59.018655 [0:00:38.031577021] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11112 23:04:59.070822 Camera needs 4 requests, can't test only 2
11113 23:04:59.164025 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11114 23:04:59.252008
11115 23:04:59.342626 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_2 (56 ms)
11116 23:04:59.442748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip>
11117 23:04:59.443073 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip
11119 23:04:59.459264 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_3
11120 23:04:59.484583 [0:00:38.499386758] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11121 23:04:59.521742 Camera needs 4 requests, can't test only 3
11122 23:04:59.614437 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11123 23:04:59.694644
11124 23:04:59.780428 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_3 (53 ms)
11125 23:04:59.876078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip>
11126 23:04:59.876406 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip
11128 23:04:59.892982 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_5
11129 23:04:59.949523 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_5 (428 ms)
11130 23:05:00.056125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass>
11131 23:05:00.056452 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass
11133 23:05:00.073103 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_8
11134 23:05:00.131952 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_8 (468 ms)
11135 23:05:00.181323 [0:00:39.197272773] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11136 23:05:00.237862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass>
11137 23:05:00.238188 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass
11139 23:05:00.256619 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_13
11140 23:05:00.315854 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_13 (698 ms)
11141 23:05:00.414592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass>
11142 23:05:00.414921 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass
11144 23:05:00.431713 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_21
11145 23:05:01.106948 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_21 (937 ms)
11146 23:05:01.119719 [0:00:40.134925477] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11147 23:05:01.216926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass>
11148 23:05:01.217249 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass
11150 23:05:01.234393 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_34
11151 23:05:02.504000 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_34 (1400 ms)
11152 23:05:02.517656 [0:00:41.534844985] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11153 23:05:02.617028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass>
11154 23:05:02.617359 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass
11156 23:05:02.634727 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_55
11157 23:05:04.601490 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_55 (2101 ms)
11158 23:05:04.614547 [0:00:43.635757896] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11159 23:05:04.712792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass>
11160 23:05:04.713131 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass
11162 23:05:04.733031 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_89
11163 23:05:07.007114 <6>[ 46.046672] vpu: disabling
11164 23:05:07.009653 <6>[ 46.049853] vproc2: disabling
11165 23:05:07.012782 <6>[ 46.053297] vproc1: disabling
11166 23:05:07.016369 <6>[ 46.056937] vaud18: disabling
11167 23:05:07.023514 <6>[ 46.060589] vsram_others: disabling
11168 23:05:07.026548 <6>[ 46.064692] va09: disabling
11169 23:05:07.029762 <6>[ 46.067985] vsram_md: disabling
11170 23:05:07.032900 <6>[ 46.071702] Vgpu: disabling
11171 23:05:07.831009 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_89 (3234 ms)
11172 23:05:07.844346 [0:00:46.869395517] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11173 23:05:07.896551 [0:00:46.925691919] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11174 23:05:07.951897 [0:00:46.981079891] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11175 23:05:07.958396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass>
11176 23:05:07.958680 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass
11178 23:05:07.970739 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_1
11179 23:05:08.005563 [0:00:47.034751479] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11180 23:05:08.031673 Camera needs 4 requests, can't test only 1
11181 23:05:08.120011 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11182 23:05:08.199462
11183 23:05:08.292096 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_1 (56 ms)
11184 23:05:08.367151 [0:00:47.396480006] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11185 23:05:08.398499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip>
11186 23:05:08.399109 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip
11188 23:05:08.418465 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_2
11189 23:05:08.482921 Camera needs 4 requests, can't test only 2
11190 23:05:08.579085 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11191 23:05:08.672664
11192 23:05:08.769236 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_2 (55 ms)
11193 23:05:08.828894 [0:00:47.858762439] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11194 23:05:08.876602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip>
11195 23:05:08.876985 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip
11197 23:05:08.895315 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_3
11198 23:05:08.963909 Camera needs 4 requests, can't test only 3
11199 23:05:09.078808 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11200 23:05:09.180261
11201 23:05:09.292591 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_3 (55 ms)
11202 23:05:09.412187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip>
11203 23:05:09.412897 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip
11205 23:05:09.436590 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_5
11206 23:05:09.508944 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_5 (362 ms)
11207 23:05:09.522439 [0:00:48.552895647] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11208 23:05:09.636201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass>
11209 23:05:09.636915 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass
11211 23:05:09.658317 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_8
11212 23:05:09.727226 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_8 (462 ms)
11213 23:05:09.851416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass>
11214 23:05:09.852259 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass
11216 23:05:09.875165 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_13
11217 23:05:09.949044 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_13 (694 ms)
11218 23:05:10.082627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass>
11219 23:05:10.083457 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass
11221 23:05:10.106332 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_21
11222 23:05:10.410311 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_21 (896 ms)
11223 23:05:10.423839 [0:00:49.450438388] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11224 23:05:10.552467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass>
11225 23:05:10.553224 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass
11227 23:05:10.577055 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_34
11228 23:05:11.747861 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_34 (1335 ms)
11229 23:05:11.757430 [0:00:50.785505732] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11230 23:05:11.878668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass>
11231 23:05:11.879558 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass
11233 23:05:11.898710 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_55
11234 23:05:13.878491 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_55 (2132 ms)
11235 23:05:13.888004 [0:00:52.917437033] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11236 23:05:14.004894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass>
11237 23:05:14.005798 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass
11239 23:05:14.027476 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_89
11240 23:05:17.042394 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_89 (3168 ms)
11241 23:05:17.055241 [0:00:56.085822085] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11242 23:05:17.107974 [0:00:56.142183389] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11243 23:05:17.163662 [0:00:56.198107744] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11244 23:05:17.188626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass>
11245 23:05:17.189361 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass
11247 23:05:17.212247 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_1
11248 23:05:17.221913 [0:00:56.256182221] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11249 23:05:17.284728 Camera needs 4 requests, can't test only 1
11250 23:05:17.390334 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11251 23:05:17.494927
11252 23:05:17.612015 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_1 (57 ms)
11253 23:05:17.653017 [0:00:56.687244865] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11254 23:05:17.747138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip>
11255 23:05:17.747897 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip
11257 23:05:17.771129 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_2
11258 23:05:17.844114 Camera needs 4 requests, can't test only 2
11259 23:05:17.954325 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11260 23:05:18.070911
11261 23:05:18.183194 [0:00:57.217651034] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11262 23:05:18.189698 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_2 (56 ms)
11263 23:05:18.319312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip>
11264 23:05:18.320074 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip
11266 23:05:18.341532 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_3
11267 23:05:18.411808 Camera needs 4 requests, can't test only 3
11268 23:05:18.515387 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11269 23:05:18.605924
11270 23:05:18.701346 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_3 (56 ms)
11271 23:05:18.800238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip>
11272 23:05:18.800545 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip
11274 23:05:18.817179 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_5
11275 23:05:18.876427 [0:00:57.911582757] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11276 23:05:18.882851 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_5 (433 ms)
11277 23:05:18.986558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass>
11278 23:05:18.986882 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass
11280 23:05:19.005738 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_8
11281 23:05:19.069594 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_8 (530 ms)
11282 23:05:19.179311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass>
11283 23:05:19.179620 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass
11285 23:05:19.198458 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_13
11286 23:05:19.259556 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_13 (695 ms)
11287 23:05:19.361754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass>
11288 23:05:19.362083 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass
11290 23:05:19.380361 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_21
11291 23:05:19.764985 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_21 (896 ms)
11292 23:05:19.778127 [0:00:58.808297691] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11293 23:05:19.877453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass>
11294 23:05:19.877743 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass
11296 23:05:19.896666 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_34
11297 23:05:21.161703 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_34 (1397 ms)
11298 23:05:21.174859 [0:01:00.205174157] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11299 23:05:21.274430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass>
11300 23:05:21.274732 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass
11302 23:05:21.292507 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_55
11303 23:05:23.258806 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_55 (2096 ms)
11304 23:05:23.271721 [0:01:02.302481236] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11305 23:05:23.368714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass>
11306 23:05:23.369029 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass
11308 23:05:23.388652 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_89
11309 23:05:26.487358 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_89 (3229 ms)
11310 23:05:26.500232 [0:01:05.531971454] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11311 23:05:26.550690 [0:01:05.587043359] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11312 23:05:26.590401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass>
11313 23:05:26.590674 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass
11315 23:05:26.604988 [0:01:05.641588853] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11316 23:05:26.607992 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_1
11317 23:05:26.657642 [0:01:05.693638068] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11318 23:05:26.674039 Camera needs 4 requests, can't test only 1
11319 23:05:26.764567 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11320 23:05:26.852056
11321 23:05:26.946851 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_1 (55 ms)
11322 23:05:27.058551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip>
11323 23:05:27.058855 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip
11325 23:05:27.077905 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_2
11326 23:05:27.136988 Camera needs 4 requests, can't test only 2
11327 23:05:27.222448 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11328 23:05:27.305034
11329 23:05:27.394299 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_2 (55 ms)
11330 23:05:27.492828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip>
11331 23:05:27.493120 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip
11333 23:05:27.510478 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_3
11334 23:05:27.567318 Camera needs 4 requests, can't test only 3
11335 23:05:27.650105 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11336 23:05:27.732530
11337 23:05:27.747836 [0:01:06.784669138] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11338 23:05:27.825609 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_3 (52 ms)
11339 23:05:27.924126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip>
11340 23:05:27.924454 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip
11342 23:05:27.943179 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_5
11343 23:05:27.998125 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_5 (1091 ms)
11344 23:05:28.098986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass>
11345 23:05:28.099292 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass
11347 23:05:28.117377 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_8
11348 23:05:29.126548 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_8 (1387 ms)
11349 23:05:29.140127 [0:01:08.174919688] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11350 23:05:29.227749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass>
11351 23:05:29.228047 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass
11353 23:05:29.245591 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_13
11354 23:05:31.212220 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_13 (2085 ms)
11355 23:05:31.225536 [0:01:10.260039547] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11356 23:05:31.314439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass>
11357 23:05:31.314739 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass
11359 23:05:31.333072 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_21
11360 23:05:33.899705 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_21 (2688 ms)
11361 23:05:33.913104 [0:01:12.948084472] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11362 23:05:34.034073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass>
11363 23:05:34.034953 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass
11365 23:05:34.056674 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_34
11366 23:05:38.115520 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_34 (4216 ms)
11367 23:05:38.128876 [0:01:17.164082919] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11368 23:05:38.250731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass>
11369 23:05:38.251481 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass
11371 23:05:38.275533 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_55
11372 23:05:44.397545 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_55 (6283 ms)
11373 23:05:44.410580 [0:01:23.447201593] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11374 23:05:44.534918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass>
11375 23:05:44.535668 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass
11377 23:05:44.556528 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_89
11378 23:05:54.108678 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_89 (9713 ms)
11379 23:05:54.122191 [0:01:33.160094137] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11380 23:05:54.176760 [0:01:33.217472946] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11381 23:05:54.218970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass>
11382 23:05:54.219242 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass
11384 23:05:54.231785 [0:01:33.271824631] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11385 23:05:54.239347 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1
11386 23:05:54.286768 [0:01:33.326736324] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11387 23:05:54.302932 Camera needs 4 requests, can't test only 1
11388 23:05:54.412803 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11389 23:05:54.511606
11390 23:05:54.617555 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1 (58 ms)
11391 23:05:54.722000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip>
11392 23:05:54.722312 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip
11394 23:05:54.739323 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2
11395 23:05:54.802576 Camera needs 4 requests, can't test only 2
11396 23:05:54.899079 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11397 23:05:55.004406
11398 23:05:55.123127 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2 (57 ms)
11399 23:05:55.247321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip>
11400 23:05:55.248082 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip
11402 23:05:55.266920 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3
11403 23:05:55.339291 Camera needs 4 requests, can't test only 3
11404 23:05:55.374472 [0:01:34.414461647] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11405 23:05:55.436214 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11406 23:05:55.536901
11407 23:05:55.651603 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3 (53 ms)
11408 23:05:55.779890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip>
11409 23:05:55.780634 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip
11411 23:05:55.798191 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5
11412 23:05:55.874417 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5 (1089 ms)
11413 23:05:56.003726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass>
11414 23:05:56.004533 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass
11416 23:05:56.023361 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8
11417 23:05:56.756893 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8 (1388 ms)
11418 23:05:56.766531 [0:01:35.802406794] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11419 23:05:56.888897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass>
11420 23:05:56.889645 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass
11422 23:05:56.908060 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13
11423 23:05:58.837744 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13 (2081 ms)
11424 23:05:58.847530 [0:01:37.886528038] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11425 23:05:58.938380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass>
11426 23:05:58.938684 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass
11428 23:05:58.953360 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21
11429 23:06:01.525461 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21 (2688 ms)
11430 23:06:01.534917 [0:01:40.574188462] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11431 23:06:01.647749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass>
11432 23:06:01.648488 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass
11434 23:06:01.666060 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34
11435 23:06:05.741270 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34 (4216 ms)
11436 23:06:05.751286 [0:01:44.790438549] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11437 23:06:05.860059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass>
11438 23:06:05.860409 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass
11440 23:06:05.876546 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55
11441 23:06:12.055649 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55 (6315 ms)
11442 23:06:12.065265 [0:01:51.104928221] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11443 23:06:12.195435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass>
11444 23:06:12.196346 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass
11446 23:06:12.215151 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89
11447 23:06:21.670699 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89 (9617 ms)
11448 23:06:21.680270 [0:02:00.721765111] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11449 23:06:21.732356 [0:02:00.776216978] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11450 23:06:21.788847 [0:02:00.832601884] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11451 23:06:21.815337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass>
11452 23:06:21.816088 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass
11454 23:06:21.835259 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1
11455 23:06:21.848238 [0:02:00.887821890] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11456 23:06:21.912595 Camera needs 4 requests, can't test only 1
11457 23:06:22.028652 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11458 23:06:22.137510
11459 23:06:22.256038 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1 (57 ms)
11460 23:06:22.386707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip>
11461 23:06:22.387464 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip
11463 23:06:22.407290 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2
11464 23:06:22.482757 Camera needs 4 requests, can't test only 2
11465 23:06:22.591407 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11466 23:06:22.695333
11467 23:06:22.810060 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2 (57 ms)
11468 23:06:22.930943 [0:02:01.974479686] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11469 23:06:22.937524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip>
11470 23:06:22.938213 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip
11472 23:06:22.957469 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3
11473 23:06:23.029201 Camera needs 4 requests, can't test only 3
11474 23:06:23.138380 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11475 23:06:23.248456
11476 23:06:23.371701 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3 (52 ms)
11477 23:06:23.501564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip>
11478 23:06:23.502379 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip
11480 23:06:23.522393 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5
11481 23:06:23.602475 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5 (1089 ms)
11482 23:06:23.727403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass>
11483 23:06:23.728150 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass
11485 23:06:23.746336 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8
11486 23:06:24.319825 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8 (1393 ms)
11487 23:06:24.329486 [0:02:03.367628644] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11488 23:06:24.449477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass>
11489 23:06:24.450317 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass
11491 23:06:24.469810 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13
11492 23:06:26.433265 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13 (2113 ms)
11493 23:06:26.442439 [0:02:05.483523471] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11494 23:06:26.571858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass>
11495 23:06:26.572675 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass
11497 23:06:26.594005 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21
11498 23:06:29.120794 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21 (2687 ms)
11499 23:06:29.130684 [0:02:08.171081462] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11500 23:06:29.256528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass>
11501 23:06:29.257314 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass
11503 23:06:29.274598 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34
11504 23:06:33.239717 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34 (4119 ms)
11505 23:06:33.249622 [0:02:12.289786928] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11506 23:06:33.374680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass>
11507 23:06:33.375473 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass
11509 23:06:33.396567 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55
11510 23:06:39.553826 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55 (6313 ms)
11511 23:06:39.563167 [0:02:18.603242683] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11512 23:06:39.685488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass>
11513 23:06:39.686283 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass
11515 23:06:39.707188 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89
11516 23:06:49.169575 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89 (9615 ms)
11517 23:06:49.178892 [0:02:28.218637124] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11518 23:06:49.231807 [0:02:28.273784515] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11519 23:06:49.285058 [0:02:28.327198653] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11520 23:06:49.291669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass>
11521 23:06:49.292368 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass
11523 23:06:49.310861 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1
11524 23:06:49.340243 [0:02:28.382248517] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11525 23:06:49.382997 Camera needs 4 requests, can't test only 1
11526 23:06:49.499331 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11527 23:06:49.610787
11528 23:06:49.731673 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1 (58 ms)
11529 23:06:49.867764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip>
11530 23:06:49.868540 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip
11532 23:06:49.889109 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2
11533 23:06:49.963743 Camera needs 4 requests, can't test only 2
11534 23:06:50.075590 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11535 23:06:50.186420
11536 23:06:50.308377 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2 (54 ms)
11537 23:06:50.440032 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip
11539 23:06:50.443039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip>
11540 23:06:50.462788 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3
11541 23:06:50.493340 [0:02:29.534910573] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11542 23:06:50.539804 Camera needs 4 requests, can't test only 3
11543 23:06:50.652059 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11544 23:06:50.760299
11545 23:06:50.874113 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3 (54 ms)
11546 23:06:51.004345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip>
11547 23:06:51.005160 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip
11549 23:06:51.025280 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5
11550 23:06:51.100841 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5 (1154 ms)
11551 23:06:51.232865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass>
11552 23:06:51.233706 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass
11554 23:06:51.253819 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8
11555 23:06:51.874564 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8 (1385 ms)
11556 23:06:51.884279 [0:02:30.920686566] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11557 23:06:52.010572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass>
11558 23:06:52.011332 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass
11560 23:06:52.029768 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13
11561 23:06:53.956628 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13 (2082 ms)
11562 23:06:53.966087 [0:02:33.006211674] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11563 23:06:54.087529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass>
11564 23:06:54.088442 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass
11566 23:06:54.108551 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21
11567 23:06:56.642699 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21 (2686 ms)
11568 23:06:56.654236 [0:02:35.693027083] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11569 23:06:56.772171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass>
11570 23:06:56.773100 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass
11572 23:06:56.789220 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34
11573 23:07:00.824981 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34 (4182 ms)
11574 23:07:00.834894 [0:02:39.875016690] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11575 23:07:00.951670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass>
11576 23:07:00.952400 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass
11578 23:07:00.972042 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55
11579 23:07:07.106670 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55 (6281 ms)
11580 23:07:07.116425 [0:02:46.156804038] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11581 23:07:07.231864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass>
11582 23:07:07.232664 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass
11584 23:07:07.249175 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89
11585 23:07:16.818720 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89 (9712 ms)
11586 23:07:16.829241 [0:02:55.869709922] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11587 23:07:16.952102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass>
11588 23:07:16.952848 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass
11590 23:07:16.973039 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_1
11591 23:07:17.115546 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_1 (300 ms)
11592 23:07:17.128396 [0:02:56.167238342] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11593 23:07:17.261170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass>
11594 23:07:17.261928 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass
11596 23:07:17.285411 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_2
11597 23:07:17.381921 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_2 (266 ms)
11598 23:07:17.394703 [0:02:56.433544304] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11599 23:07:17.522542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass>
11600 23:07:17.523300 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass
11602 23:07:17.546651 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_3
11603 23:07:17.682242 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_3 (300 ms)
11604 23:07:17.694941 [0:02:56.733568349] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11605 23:07:17.826363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass>
11606 23:07:17.827193 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass
11608 23:07:17.848274 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_5
11609 23:07:18.114431 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_5 (432 ms)
11610 23:07:18.124168 [0:02:57.165794424] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11611 23:07:18.258763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass>
11612 23:07:18.259548 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass
11614 23:07:18.283966 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_8
11615 23:07:18.646467 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_8 (532 ms)
11616 23:07:18.659680 [0:02:57.697815984] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11617 23:07:18.788455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass>
11618 23:07:18.789300 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass
11620 23:07:18.812600 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_13
11621 23:07:19.343499 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_13 (698 ms)
11622 23:07:19.356905 [0:02:58.395125725] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11623 23:07:19.478427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass>
11624 23:07:19.479141 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass
11626 23:07:19.502519 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_21
11627 23:07:20.243175 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_21 (900 ms)
11628 23:07:20.256493 [0:02:59.295272176] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11629 23:07:20.377153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass>
11630 23:07:20.378084 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass
11632 23:07:20.401320 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_34
11633 23:07:21.640762 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_34 (1397 ms)
11634 23:07:21.653605 [0:03:00.692873465] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11635 23:07:21.786009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass>
11636 23:07:21.786775 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass
11638 23:07:21.805252 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_55
11639 23:07:23.737810 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_55 (2096 ms)
11640 23:07:23.750759 [0:03:02.789777323] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11641 23:07:23.876459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass>
11642 23:07:23.877219 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass
11644 23:07:23.897962 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_89
11645 23:07:26.969260 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_89 (3231 ms)
11646 23:07:26.981418 [0:03:06.020712269] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11647 23:07:27.108544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass>
11648 23:07:27.109327 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass
11650 23:07:27.131470 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1
11651 23:07:27.207581 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1 (235 ms)
11652 23:07:27.216999 [0:03:06.255009688] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11653 23:07:27.336770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass>
11654 23:07:27.337540 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass
11656 23:07:27.356080 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2
11657 23:07:27.473381 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2 (266 ms)
11658 23:07:27.482538 [0:03:06.521405524] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11659 23:07:27.610095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass>
11660 23:07:27.610889 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass
11662 23:07:27.631137 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3
11663 23:07:27.772333 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3 (300 ms)
11664 23:07:27.782088 [0:03:06.821417745] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11665 23:07:27.913295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass>
11666 23:07:27.914093 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass
11668 23:07:27.932364 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5
11669 23:07:28.204187 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5 (432 ms)
11670 23:07:28.213970 [0:03:07.253135301] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11671 23:07:28.331741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass>
11672 23:07:28.332470 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass
11674 23:07:28.351144 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8
11675 23:07:28.735447 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8 (531 ms)
11676 23:07:28.745995 [0:03:07.784461384] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11677 23:07:28.870410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass>
11678 23:07:28.871170 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass
11680 23:07:28.888461 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13
11681 23:07:29.433490 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13 (697 ms)
11682 23:07:29.442908 [0:03:08.481786969] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11683 23:07:29.569998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass>
11684 23:07:29.570817 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass
11686 23:07:29.588027 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21
11687 23:07:30.332525 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21 (900 ms)
11688 23:07:30.341623 [0:03:09.381185751] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11689 23:07:30.470103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass>
11690 23:07:30.470913 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass
11692 23:07:30.490486 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34
11693 23:07:31.729364 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34 (1397 ms)
11694 23:07:31.739139 [0:03:10.780510547] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11695 23:07:31.865332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass>
11696 23:07:31.866141 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass
11698 23:07:31.882346 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55
11699 23:07:33.827595 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55 (2098 ms)
11700 23:07:33.837564 [0:03:12.878934689] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11701 23:07:33.966989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass>
11702 23:07:33.967799 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass
11704 23:07:33.987840 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89
11705 23:07:37.058383 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89 (3231 ms)
11706 23:07:37.068782 [0:03:16.110490742] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11707 23:07:37.197796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass>
11708 23:07:37.198762 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass
11710 23:07:37.218893 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1
11711 23:07:37.358247 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1 (299 ms)
11712 23:07:37.367154 [0:03:16.407549975] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11713 23:07:37.497096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass>
11714 23:07:37.497867 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass
11716 23:07:37.514425 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2
11717 23:07:37.625751 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2 (267 ms)
11718 23:07:37.635299 [0:03:16.673711357] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11719 23:07:37.760961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass>
11720 23:07:37.761732 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass
11722 23:07:37.780265 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3
11723 23:07:37.924241 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3 (299 ms)
11724 23:07:37.933877 [0:03:16.973388863] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11725 23:07:38.039550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass>
11726 23:07:38.039839 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass
11728 23:07:38.054941 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5
11729 23:07:38.355427 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5 (431 ms)
11730 23:07:38.365320 [0:03:17.404885891] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11731 23:07:38.493408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass>
11732 23:07:38.494147 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass
11734 23:07:38.513175 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8
11735 23:07:38.821754 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8 (467 ms)
11736 23:07:38.831449 [0:03:17.871447053] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11737 23:07:38.953812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass>
11738 23:07:38.954694 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass
11740 23:07:38.973504 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13
11741 23:07:39.519826 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13 (698 ms)
11742 23:07:39.529319 [0:03:18.569182493] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11743 23:07:39.659683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass>
11744 23:07:39.660522 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass
11746 23:07:39.681892 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21
11747 23:07:40.418657 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21 (899 ms)
11748 23:07:40.428419 [0:03:19.468413693] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11749 23:07:40.559112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass>
11750 23:07:40.559880 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass
11752 23:07:40.580449 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34
11753 23:07:41.815829 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34 (1397 ms)
11754 23:07:41.825514 [0:03:20.867617891] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11755 23:07:41.947478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass>
11756 23:07:41.948291 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass
11758 23:07:41.967733 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55
11759 23:07:43.913681 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55 (2098 ms)
11760 23:07:43.923526 [0:03:22.966139479] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11761 23:07:44.044813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass>
11762 23:07:44.045587 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass
11764 23:07:44.062666 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89
11765 23:07:47.145451 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89 (3231 ms)
11766 23:07:47.155141 [0:03:26.197902026] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11767 23:07:47.276202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass>
11768 23:07:47.276972 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass
11770 23:07:47.294234 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1
11771 23:07:47.444027 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1 (299 ms)
11772 23:07:47.454011 [0:03:26.495000081] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11773 23:07:47.547745 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass
11775 23:07:47.550446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass>
11776 23:07:47.568622 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2
11777 23:07:47.775570 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2 (331 ms)
11778 23:07:47.784841 [0:03:26.826007750] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11779 23:07:47.894998 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass
11781 23:07:47.897622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass>
11782 23:07:47.914139 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3
11783 23:07:48.075043 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3 (299 ms)
11784 23:07:48.085323 [0:03:27.125691978] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11785 23:07:48.203632 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass
11787 23:07:48.207026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass>
11788 23:07:48.223899 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5
11789 23:07:48.539872 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5 (464 ms)
11790 23:07:48.549268 [0:03:27.589860962] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11791 23:07:48.674462 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass
11793 23:07:48.677945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass>
11794 23:07:48.699327 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8
11795 23:07:49.103702 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8 (563 ms)
11796 23:07:49.112837 [0:03:28.153753345] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11797 23:07:49.241679 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass
11799 23:07:49.245177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass>
11800 23:07:49.264035 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13
11801 23:07:49.801656 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13 (698 ms)
11802 23:07:49.811210 [0:03:28.851597827] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11803 23:07:49.936794 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass
11805 23:07:49.939632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass>
11806 23:07:49.959802 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21
11807 23:07:50.700488 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21 (899 ms)
11808 23:07:50.710070 [0:03:29.750867895] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11809 23:07:50.829103 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass
11811 23:07:50.832105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass>
11812 23:07:50.852369 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34
11813 23:07:52.097312 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34 (1397 ms)
11814 23:07:52.107075 [0:03:31.149994147] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11815 23:07:52.230409 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass
11817 23:07:52.233394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass>
11818 23:07:52.250831 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55
11819 23:07:54.228381 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55 (2131 ms)
11820 23:07:54.238448 [0:03:33.281202883] [406] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11821 23:07:54.364856 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass
11823 23:07:54.367760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass>
11824 23:07:54.388285 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89
11825 23:07:57.459782 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89 (3231 ms)
11826 23:07:57.574882 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass
11828 23:07:57.578027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass>
11829 23:07:57.594076 [----------] 120 tests from CaptureTests/SingleStream (188427 ms total)
11830 23:07:57.691870
11831 23:07:57.802707 [----------] Global test environment tear-down
11832 23:07:57.916662 [==========] 120 tests from 1 test suite ran. (188428 ms total)
11833 23:07:58.035908 <LAVA_SIGNAL_TESTSET STOP>
11834 23:07:58.036713 Received signal: <TESTSET> STOP
11835 23:07:58.037102 Closing test_set CaptureTests/SingleStream
11836 23:07:58.050403 + set +x
11837 23:07:58.053264 <LAVA_SIGNAL_ENDRUN 0_lc-compliance 12154430_1.6.2.3.1>
11838 23:07:58.053934 Received signal: <ENDRUN> 0_lc-compliance 12154430_1.6.2.3.1
11839 23:07:58.054373 Ending use of test pattern.
11840 23:07:58.054704 Ending test lava.0_lc-compliance (12154430_1.6.2.3.1), duration 190.19
11842 23:07:58.057434 <LAVA_TEST_RUNNER EXIT>
11843 23:07:58.058098 ok: lava_test_shell seems to have completed
11844 23:07:58.067391 Capture/Raw_1:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_13:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_2:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_21:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_3:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_34:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_5:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_55:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_8:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_89:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
11845 23:07:58.068425 end: 3.1 lava-test-shell (duration 00:03:11) [common]
11846 23:07:58.068917 end: 3 lava-test-retry (duration 00:03:11) [common]
11847 23:07:58.069362 start: 4 finalize (timeout 00:10:00) [common]
11848 23:07:58.069815 start: 4.1 power-off (timeout 00:00:30) [common]
11849 23:07:58.070599 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=off'
11850 23:07:58.158582 >> Command sent successfully.
11851 23:07:58.163759 Returned 0 in 0 seconds
11852 23:07:58.264833 end: 4.1 power-off (duration 00:00:00) [common]
11854 23:07:58.266424 start: 4.2 read-feedback (timeout 00:10:00) [common]
11855 23:07:58.267741 Listened to connection for namespace 'common' for up to 1s
11856 23:07:58.268613 Listened to connection for namespace 'common' for up to 1s
11857 23:07:59.268421 Finalising connection for namespace 'common'
11858 23:07:59.269039 Disconnecting from shell: Finalise
11859 23:07:59.269438 / #
11860 23:07:59.370465 end: 4.2 read-feedback (duration 00:00:01) [common]
11861 23:07:59.371161 end: 4 finalize (duration 00:00:01) [common]
11862 23:07:59.371771 Cleaning after the job
11863 23:07:59.372278 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12154430/tftp-deploy-s7vuzfyl/ramdisk
11864 23:07:59.377419 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12154430/tftp-deploy-s7vuzfyl/kernel
11865 23:07:59.389872 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12154430/tftp-deploy-s7vuzfyl/dtb
11866 23:07:59.390031 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12154430/tftp-deploy-s7vuzfyl/nfsrootfs
11867 23:07:59.448088 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12154430/tftp-deploy-s7vuzfyl/modules
11868 23:07:59.455158 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12154430
11869 23:07:59.772907 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12154430
11870 23:07:59.773086 Job finished correctly