Boot log: mt8192-asurada-spherion-r0
- Boot result: FAIL
- Warnings: 1
- Kernel Warnings: 7
- Kernel Errors: 5
- Errors: 3
1 23:02:00.914642 lava-dispatcher, installed at version: 2023.10
2 23:02:00.914920 start: 0 validate
3 23:02:00.915084 Start time: 2023-12-01 23:02:00.915076+00:00 (UTC)
4 23:02:00.915209 Using caching service: 'http://localhost/cache/?uri=%s'
5 23:02:00.915346 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 23:02:01.184610 Using caching service: 'http://localhost/cache/?uri=%s'
7 23:02:01.184791 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.64-cip10%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 23:02:01.450292 Using caching service: 'http://localhost/cache/?uri=%s'
9 23:02:01.450474 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.64-cip10%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 23:02:35.981649 Using caching service: 'http://localhost/cache/?uri=%s'
11 23:02:35.982375 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.64-cip10%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 23:02:36.514146 validate duration: 35.60
14 23:02:36.514414 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 23:02:36.514510 start: 1.1 download-retry (timeout 00:10:00) [common]
16 23:02:36.514634 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 23:02:36.514787 Not decompressing ramdisk as can be used compressed.
18 23:02:36.514933 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/rootfs.cpio.gz
19 23:02:36.515028 saving as /var/lib/lava/dispatcher/tmp/12154390/tftp-deploy-2ku5fbdd/ramdisk/rootfs.cpio.gz
20 23:02:36.515093 total size: 84918747 (80 MB)
21 23:02:39.425402 progress 0 % (0 MB)
22 23:02:39.450808 progress 5 % (4 MB)
23 23:02:39.473138 progress 10 % (8 MB)
24 23:02:39.494925 progress 15 % (12 MB)
25 23:02:39.516924 progress 20 % (16 MB)
26 23:02:39.538724 progress 25 % (20 MB)
27 23:02:39.560918 progress 30 % (24 MB)
28 23:02:39.582946 progress 35 % (28 MB)
29 23:02:39.604771 progress 40 % (32 MB)
30 23:02:39.626480 progress 45 % (36 MB)
31 23:02:39.689927 progress 50 % (40 MB)
32 23:02:39.712433 progress 55 % (44 MB)
33 23:02:39.735726 progress 60 % (48 MB)
34 23:02:39.758615 progress 65 % (52 MB)
35 23:02:39.780980 progress 70 % (56 MB)
36 23:02:39.803000 progress 75 % (60 MB)
37 23:02:39.825696 progress 80 % (64 MB)
38 23:02:39.848677 progress 85 % (68 MB)
39 23:02:39.871861 progress 90 % (72 MB)
40 23:02:39.894125 progress 95 % (76 MB)
41 23:02:39.916147 progress 100 % (80 MB)
42 23:02:39.916417 80 MB downloaded in 3.40 s (23.81 MB/s)
43 23:02:39.916624 end: 1.1.1 http-download (duration 00:00:03) [common]
45 23:02:39.916917 end: 1.1 download-retry (duration 00:00:03) [common]
46 23:02:39.917034 start: 1.2 download-retry (timeout 00:09:57) [common]
47 23:02:39.917151 start: 1.2.1 http-download (timeout 00:09:57) [common]
48 23:02:39.917328 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.64-cip10/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 23:02:39.917398 saving as /var/lib/lava/dispatcher/tmp/12154390/tftp-deploy-2ku5fbdd/kernel/Image
50 23:02:39.917463 total size: 49172992 (46 MB)
51 23:02:39.917526 No compression specified
52 23:02:39.918670 progress 0 % (0 MB)
53 23:02:39.931760 progress 5 % (2 MB)
54 23:02:39.945183 progress 10 % (4 MB)
55 23:02:39.958487 progress 15 % (7 MB)
56 23:02:39.971663 progress 20 % (9 MB)
57 23:02:39.984737 progress 25 % (11 MB)
58 23:02:39.997710 progress 30 % (14 MB)
59 23:02:40.010709 progress 35 % (16 MB)
60 23:02:40.024223 progress 40 % (18 MB)
61 23:02:40.037253 progress 45 % (21 MB)
62 23:02:40.050379 progress 50 % (23 MB)
63 23:02:40.063689 progress 55 % (25 MB)
64 23:02:40.076869 progress 60 % (28 MB)
65 23:02:40.090102 progress 65 % (30 MB)
66 23:02:40.103133 progress 70 % (32 MB)
67 23:02:40.116171 progress 75 % (35 MB)
68 23:02:40.129173 progress 80 % (37 MB)
69 23:02:40.142285 progress 85 % (39 MB)
70 23:02:40.155500 progress 90 % (42 MB)
71 23:02:40.168457 progress 95 % (44 MB)
72 23:02:40.181513 progress 100 % (46 MB)
73 23:02:40.181788 46 MB downloaded in 0.26 s (177.42 MB/s)
74 23:02:40.181957 end: 1.2.1 http-download (duration 00:00:00) [common]
76 23:02:40.182192 end: 1.2 download-retry (duration 00:00:00) [common]
77 23:02:40.182281 start: 1.3 download-retry (timeout 00:09:56) [common]
78 23:02:40.182372 start: 1.3.1 http-download (timeout 00:09:56) [common]
79 23:02:40.182517 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.64-cip10/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 23:02:40.182595 saving as /var/lib/lava/dispatcher/tmp/12154390/tftp-deploy-2ku5fbdd/dtb/mt8192-asurada-spherion-r0.dtb
81 23:02:40.182659 total size: 47278 (0 MB)
82 23:02:40.182721 No compression specified
83 23:02:40.183889 progress 69 % (0 MB)
84 23:02:40.184174 progress 100 % (0 MB)
85 23:02:40.184337 0 MB downloaded in 0.00 s (26.90 MB/s)
86 23:02:40.184465 end: 1.3.1 http-download (duration 00:00:00) [common]
88 23:02:40.184691 end: 1.3 download-retry (duration 00:00:00) [common]
89 23:02:40.184777 start: 1.4 download-retry (timeout 00:09:56) [common]
90 23:02:40.184864 start: 1.4.1 http-download (timeout 00:09:56) [common]
91 23:02:40.184989 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.64-cip10/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 23:02:40.185059 saving as /var/lib/lava/dispatcher/tmp/12154390/tftp-deploy-2ku5fbdd/modules/modules.tar
93 23:02:40.185121 total size: 8616152 (8 MB)
94 23:02:40.185182 Using unxz to decompress xz
95 23:02:40.189688 progress 0 % (0 MB)
96 23:02:40.212556 progress 5 % (0 MB)
97 23:02:40.238281 progress 10 % (0 MB)
98 23:02:40.263550 progress 15 % (1 MB)
99 23:02:40.287751 progress 20 % (1 MB)
100 23:02:40.312491 progress 25 % (2 MB)
101 23:02:40.340288 progress 30 % (2 MB)
102 23:02:40.367541 progress 35 % (2 MB)
103 23:02:40.391628 progress 40 % (3 MB)
104 23:02:40.417213 progress 45 % (3 MB)
105 23:02:40.444483 progress 50 % (4 MB)
106 23:02:40.470294 progress 55 % (4 MB)
107 23:02:40.495819 progress 60 % (4 MB)
108 23:02:40.523385 progress 65 % (5 MB)
109 23:02:40.552661 progress 70 % (5 MB)
110 23:02:40.578519 progress 75 % (6 MB)
111 23:02:40.607970 progress 80 % (6 MB)
112 23:02:40.636170 progress 85 % (7 MB)
113 23:02:40.662247 progress 90 % (7 MB)
114 23:02:40.694686 progress 95 % (7 MB)
115 23:02:40.724612 progress 100 % (8 MB)
116 23:02:40.731433 8 MB downloaded in 0.55 s (15.04 MB/s)
117 23:02:40.731798 end: 1.4.1 http-download (duration 00:00:01) [common]
119 23:02:40.732222 end: 1.4 download-retry (duration 00:00:01) [common]
120 23:02:40.732364 start: 1.5 prepare-tftp-overlay (timeout 00:09:56) [common]
121 23:02:40.732509 start: 1.5.1 extract-nfsrootfs (timeout 00:09:56) [common]
122 23:02:40.732642 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 23:02:40.732778 start: 1.5.2 lava-overlay (timeout 00:09:56) [common]
124 23:02:40.733097 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12154390/lava-overlay-qullkyyj
125 23:02:40.733303 makedir: /var/lib/lava/dispatcher/tmp/12154390/lava-overlay-qullkyyj/lava-12154390/bin
126 23:02:40.733462 makedir: /var/lib/lava/dispatcher/tmp/12154390/lava-overlay-qullkyyj/lava-12154390/tests
127 23:02:40.733616 makedir: /var/lib/lava/dispatcher/tmp/12154390/lava-overlay-qullkyyj/lava-12154390/results
128 23:02:40.733790 Creating /var/lib/lava/dispatcher/tmp/12154390/lava-overlay-qullkyyj/lava-12154390/bin/lava-add-keys
129 23:02:40.734004 Creating /var/lib/lava/dispatcher/tmp/12154390/lava-overlay-qullkyyj/lava-12154390/bin/lava-add-sources
130 23:02:40.734210 Creating /var/lib/lava/dispatcher/tmp/12154390/lava-overlay-qullkyyj/lava-12154390/bin/lava-background-process-start
131 23:02:40.734408 Creating /var/lib/lava/dispatcher/tmp/12154390/lava-overlay-qullkyyj/lava-12154390/bin/lava-background-process-stop
132 23:02:40.734601 Creating /var/lib/lava/dispatcher/tmp/12154390/lava-overlay-qullkyyj/lava-12154390/bin/lava-common-functions
133 23:02:40.734795 Creating /var/lib/lava/dispatcher/tmp/12154390/lava-overlay-qullkyyj/lava-12154390/bin/lava-echo-ipv4
134 23:02:40.735002 Creating /var/lib/lava/dispatcher/tmp/12154390/lava-overlay-qullkyyj/lava-12154390/bin/lava-install-packages
135 23:02:40.735193 Creating /var/lib/lava/dispatcher/tmp/12154390/lava-overlay-qullkyyj/lava-12154390/bin/lava-installed-packages
136 23:02:40.735386 Creating /var/lib/lava/dispatcher/tmp/12154390/lava-overlay-qullkyyj/lava-12154390/bin/lava-os-build
137 23:02:40.735577 Creating /var/lib/lava/dispatcher/tmp/12154390/lava-overlay-qullkyyj/lava-12154390/bin/lava-probe-channel
138 23:02:40.735772 Creating /var/lib/lava/dispatcher/tmp/12154390/lava-overlay-qullkyyj/lava-12154390/bin/lava-probe-ip
139 23:02:40.735964 Creating /var/lib/lava/dispatcher/tmp/12154390/lava-overlay-qullkyyj/lava-12154390/bin/lava-target-ip
140 23:02:40.736155 Creating /var/lib/lava/dispatcher/tmp/12154390/lava-overlay-qullkyyj/lava-12154390/bin/lava-target-mac
141 23:02:40.736352 Creating /var/lib/lava/dispatcher/tmp/12154390/lava-overlay-qullkyyj/lava-12154390/bin/lava-target-storage
142 23:02:40.736553 Creating /var/lib/lava/dispatcher/tmp/12154390/lava-overlay-qullkyyj/lava-12154390/bin/lava-test-case
143 23:02:40.736746 Creating /var/lib/lava/dispatcher/tmp/12154390/lava-overlay-qullkyyj/lava-12154390/bin/lava-test-event
144 23:02:40.736939 Creating /var/lib/lava/dispatcher/tmp/12154390/lava-overlay-qullkyyj/lava-12154390/bin/lava-test-feedback
145 23:02:40.737139 Creating /var/lib/lava/dispatcher/tmp/12154390/lava-overlay-qullkyyj/lava-12154390/bin/lava-test-raise
146 23:02:40.737331 Creating /var/lib/lava/dispatcher/tmp/12154390/lava-overlay-qullkyyj/lava-12154390/bin/lava-test-reference
147 23:02:40.737526 Creating /var/lib/lava/dispatcher/tmp/12154390/lava-overlay-qullkyyj/lava-12154390/bin/lava-test-runner
148 23:02:40.737729 Creating /var/lib/lava/dispatcher/tmp/12154390/lava-overlay-qullkyyj/lava-12154390/bin/lava-test-set
149 23:02:40.737922 Creating /var/lib/lava/dispatcher/tmp/12154390/lava-overlay-qullkyyj/lava-12154390/bin/lava-test-shell
150 23:02:40.738121 Updating /var/lib/lava/dispatcher/tmp/12154390/lava-overlay-qullkyyj/lava-12154390/bin/lava-install-packages (oe)
151 23:02:40.738348 Updating /var/lib/lava/dispatcher/tmp/12154390/lava-overlay-qullkyyj/lava-12154390/bin/lava-installed-packages (oe)
152 23:02:40.738537 Creating /var/lib/lava/dispatcher/tmp/12154390/lava-overlay-qullkyyj/lava-12154390/environment
153 23:02:40.738691 LAVA metadata
154 23:02:40.738813 - LAVA_JOB_ID=12154390
155 23:02:40.738932 - LAVA_DISPATCHER_IP=192.168.201.1
156 23:02:40.739093 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:56) [common]
157 23:02:40.739201 skipped lava-vland-overlay
158 23:02:40.739322 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 23:02:40.739455 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:56) [common]
160 23:02:40.739575 skipped lava-multinode-overlay
161 23:02:40.739703 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 23:02:40.739840 start: 1.5.2.3 test-definition (timeout 00:09:56) [common]
163 23:02:40.739967 Loading test definitions
164 23:02:40.740113 start: 1.5.2.3.1 git-repo-action (timeout 00:09:56) [common]
165 23:02:40.740239 Using /lava-12154390 at stage 0
166 23:02:40.740400 Fetching tests from https://github.com/kernelci/kernelci-core
167 23:02:40.740533 Running '/usr/bin/git clone -b kernelci.org --depth=1 https://github.com/kernelci/kernelci-core /var/lib/lava/dispatcher/tmp/12154390/lava-overlay-qullkyyj/lava-12154390/0/tests/0_sleep'
168 23:02:41.414768 Removing '.git' directory in /var/lib/lava/dispatcher/tmp/12154390/lava-overlay-qullkyyj/lava-12154390/0/tests/0_sleep
169 23:02:41.416513 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12154390/lava-overlay-qullkyyj/lava-12154390/0/tests/0_sleep/config/lava/sleep/sleep.yaml
170 23:02:41.417065 uuid=12154390_1.5.2.3.1 testdef=None
171 23:02:41.417262 end: 1.5.2.3.1 git-repo-action (duration 00:00:01) [common]
173 23:02:41.417639 start: 1.5.2.3.2 test-overlay (timeout 00:09:55) [common]
174 23:02:41.418492 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
176 23:02:41.418893 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:55) [common]
177 23:02:41.419621 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
179 23:02:41.419859 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:55) [common]
180 23:02:41.420584 runner path: /var/lib/lava/dispatcher/tmp/12154390/lava-overlay-qullkyyj/lava-12154390/0/tests/0_sleep test_uuid 12154390_1.5.2.3.1
181 23:02:41.420670 sleep_params='mem freeze'
182 23:02:41.420883 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
184 23:02:41.421125 Creating lava-test-runner.conf files
185 23:02:41.421204 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12154390/lava-overlay-qullkyyj/lava-12154390/0 for stage 0
186 23:02:41.421299 - 0_sleep
187 23:02:41.421403 end: 1.5.2.3 test-definition (duration 00:00:01) [common]
188 23:02:41.421520 start: 1.5.2.4 compress-overlay (timeout 00:09:55) [common]
189 23:02:41.557658 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
190 23:02:41.557827 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:55) [common]
191 23:02:41.557940 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
192 23:02:41.558152 end: 1.5.2 lava-overlay (duration 00:00:01) [common]
193 23:02:41.558301 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:55) [common]
194 23:02:44.152581 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:03) [common]
195 23:02:44.153031 start: 1.5.4 extract-modules (timeout 00:09:52) [common]
196 23:02:44.153166 extracting modules file /var/lib/lava/dispatcher/tmp/12154390/tftp-deploy-2ku5fbdd/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12154390/extract-overlay-ramdisk-v51m7dmj/ramdisk
197 23:02:44.396997 end: 1.5.4 extract-modules (duration 00:00:00) [common]
198 23:02:44.397187 start: 1.5.5 apply-overlay-tftp (timeout 00:09:52) [common]
199 23:02:44.397308 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12154390/compress-overlay-c7plqqk8/overlay-1.5.2.4.tar.gz to ramdisk
200 23:02:44.397394 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12154390/compress-overlay-c7plqqk8/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12154390/extract-overlay-ramdisk-v51m7dmj/ramdisk
201 23:02:44.496033 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
202 23:02:44.496207 start: 1.5.6 configure-preseed-file (timeout 00:09:52) [common]
203 23:02:44.496329 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
204 23:02:44.496438 start: 1.5.7 compress-ramdisk (timeout 00:09:52) [common]
205 23:02:44.496537 Building ramdisk /var/lib/lava/dispatcher/tmp/12154390/extract-overlay-ramdisk-v51m7dmj/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12154390/extract-overlay-ramdisk-v51m7dmj/ramdisk
206 23:02:46.085447 >> 563574 blocks
207 23:02:56.252635 rename /var/lib/lava/dispatcher/tmp/12154390/extract-overlay-ramdisk-v51m7dmj/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12154390/tftp-deploy-2ku5fbdd/ramdisk/ramdisk.cpio.gz
208 23:02:56.253113 end: 1.5.7 compress-ramdisk (duration 00:00:12) [common]
209 23:02:56.253248 start: 1.5.8 prepare-kernel (timeout 00:09:40) [common]
210 23:02:56.253359 start: 1.5.8.1 prepare-fit (timeout 00:09:40) [common]
211 23:02:56.253478 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12154390/tftp-deploy-2ku5fbdd/kernel/Image'
212 23:03:09.017261 Returned 0 in 12 seconds
213 23:03:09.117960 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12154390/tftp-deploy-2ku5fbdd/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12154390/tftp-deploy-2ku5fbdd/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12154390/tftp-deploy-2ku5fbdd/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12154390/tftp-deploy-2ku5fbdd/kernel/image.itb
214 23:03:10.499466 output: FIT description: Kernel Image image with one or more FDT blobs
215 23:03:10.499840 output: Created: Fri Dec 1 23:03:10 2023
216 23:03:10.499947 output: Image 0 (kernel-1)
217 23:03:10.500035 output: Description:
218 23:03:10.500115 output: Created: Fri Dec 1 23:03:10 2023
219 23:03:10.500212 output: Type: Kernel Image
220 23:03:10.500310 output: Compression: lzma compressed
221 23:03:10.500410 output: Data Size: 11043984 Bytes = 10785.14 KiB = 10.53 MiB
222 23:03:10.500510 output: Architecture: AArch64
223 23:03:10.500609 output: OS: Linux
224 23:03:10.500707 output: Load Address: 0x00000000
225 23:03:10.500810 output: Entry Point: 0x00000000
226 23:03:10.500912 output: Hash algo: crc32
227 23:03:10.501014 output: Hash value: 36c84243
228 23:03:10.501114 output: Image 1 (fdt-1)
229 23:03:10.501212 output: Description: mt8192-asurada-spherion-r0
230 23:03:10.501305 output: Created: Fri Dec 1 23:03:10 2023
231 23:03:10.501398 output: Type: Flat Device Tree
232 23:03:10.501491 output: Compression: uncompressed
233 23:03:10.501584 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
234 23:03:10.501676 output: Architecture: AArch64
235 23:03:10.501769 output: Hash algo: crc32
236 23:03:10.501861 output: Hash value: cc4352de
237 23:03:10.501953 output: Image 2 (ramdisk-1)
238 23:03:10.502045 output: Description: unavailable
239 23:03:10.502137 output: Created: Fri Dec 1 23:03:10 2023
240 23:03:10.502230 output: Type: RAMDisk Image
241 23:03:10.502322 output: Compression: Unknown Compression
242 23:03:10.502417 output: Data Size: 98354976 Bytes = 96049.78 KiB = 93.80 MiB
243 23:03:10.502510 output: Architecture: AArch64
244 23:03:10.502605 output: OS: Linux
245 23:03:10.502698 output: Load Address: unavailable
246 23:03:10.502790 output: Entry Point: unavailable
247 23:03:10.502915 output: Hash algo: crc32
248 23:03:10.503022 output: Hash value: da160ead
249 23:03:10.503115 output: Default Configuration: 'conf-1'
250 23:03:10.503207 output: Configuration 0 (conf-1)
251 23:03:10.503300 output: Description: mt8192-asurada-spherion-r0
252 23:03:10.503391 output: Kernel: kernel-1
253 23:03:10.503482 output: Init Ramdisk: ramdisk-1
254 23:03:10.503573 output: FDT: fdt-1
255 23:03:10.503664 output: Loadables: kernel-1
256 23:03:10.503755 output:
257 23:03:10.504015 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
258 23:03:10.504159 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
259 23:03:10.504309 end: 1.5 prepare-tftp-overlay (duration 00:00:30) [common]
260 23:03:10.504445 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:26) [common]
261 23:03:10.504560 No LXC device requested
262 23:03:10.504681 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
263 23:03:10.504809 start: 1.7 deploy-device-env (timeout 00:09:26) [common]
264 23:03:10.504928 end: 1.7 deploy-device-env (duration 00:00:00) [common]
265 23:03:10.505039 Checking files for TFTP limit of 4294967296 bytes.
266 23:03:10.505720 end: 1 tftp-deploy (duration 00:00:34) [common]
267 23:03:10.505866 start: 2 depthcharge-action (timeout 00:05:00) [common]
268 23:03:10.506003 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
269 23:03:10.506213 substitutions:
270 23:03:10.506289 - {DTB}: 12154390/tftp-deploy-2ku5fbdd/dtb/mt8192-asurada-spherion-r0.dtb
271 23:03:10.506374 - {INITRD}: 12154390/tftp-deploy-2ku5fbdd/ramdisk/ramdisk.cpio.gz
272 23:03:10.506454 - {KERNEL}: 12154390/tftp-deploy-2ku5fbdd/kernel/Image
273 23:03:10.506533 - {LAVA_MAC}: None
274 23:03:10.506611 - {PRESEED_CONFIG}: None
275 23:03:10.506707 - {PRESEED_LOCAL}: None
276 23:03:10.506803 - {RAMDISK}: 12154390/tftp-deploy-2ku5fbdd/ramdisk/ramdisk.cpio.gz
277 23:03:10.506943 - {ROOT_PART}: None
278 23:03:10.507039 - {ROOT}: None
279 23:03:10.507135 - {SERVER_IP}: 192.168.201.1
280 23:03:10.507229 - {TEE}: None
281 23:03:10.507324 Parsed boot commands:
282 23:03:10.507419 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
283 23:03:10.507669 Parsed boot commands: tftpboot 192.168.201.1 12154390/tftp-deploy-2ku5fbdd/kernel/image.itb 12154390/tftp-deploy-2ku5fbdd/kernel/cmdline
284 23:03:10.507799 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
285 23:03:10.507926 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
286 23:03:10.508066 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
287 23:03:10.508193 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
288 23:03:10.508302 Not connected, no need to disconnect.
289 23:03:10.508420 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
290 23:03:10.508547 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
291 23:03:10.508650 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-3'
292 23:03:10.513279 Setting prompt string to ['lava-test: # ']
293 23:03:10.513752 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
294 23:03:10.513909 end: 2.2.1 reset-connection (duration 00:00:00) [common]
295 23:03:10.514027 start: 2.2.2 reset-device (timeout 00:05:00) [common]
296 23:03:10.514170 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
297 23:03:10.514405 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=reboot'
298 23:03:15.649997 >> Command sent successfully.
299 23:03:15.652704 Returned 0 in 5 seconds
300 23:03:15.753148 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
302 23:03:15.753525 end: 2.2.2 reset-device (duration 00:00:05) [common]
303 23:03:15.753647 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
304 23:03:15.753754 Setting prompt string to 'Starting depthcharge on Spherion...'
305 23:03:15.753835 Changing prompt to 'Starting depthcharge on Spherion...'
306 23:03:15.753932 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
307 23:03:15.754322 [Enter `^Ec?' for help]
308 23:03:15.927268
309 23:03:15.927440
310 23:03:15.927539 F0: 102B 0000
311 23:03:15.927625
312 23:03:15.927708 F3: 1001 0000 [0200]
313 23:03:15.927787
314 23:03:15.931110 F3: 1001 0000
315 23:03:15.931197
316 23:03:15.931284 F7: 102D 0000
317 23:03:15.931367
318 23:03:15.931448 F1: 0000 0000
319 23:03:15.931527
320 23:03:15.934802 V0: 0000 0000 [0001]
321 23:03:15.934941
322 23:03:15.935010 00: 0007 8000
323 23:03:15.935087
324 23:03:15.938649 01: 0000 0000
325 23:03:15.938722
326 23:03:15.938809 BP: 0C00 0209 [0000]
327 23:03:15.938894
328 23:03:15.942598 G0: 1182 0000
329 23:03:15.942666
330 23:03:15.942740 EC: 0000 0021 [4000]
331 23:03:15.942827
332 23:03:15.945915 S7: 0000 0000 [0000]
333 23:03:15.946000
334 23:03:15.946067 CC: 0000 0000 [0001]
335 23:03:15.946128
336 23:03:15.949239 T0: 0000 0040 [010F]
337 23:03:15.949323
338 23:03:15.949389 Jump to BL
339 23:03:15.949449
340 23:03:15.974728
341 23:03:15.974873
342 23:03:15.974974
343 23:03:15.981410 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
344 23:03:15.985621 ARM64: Exception handlers installed.
345 23:03:15.988641 ARM64: Testing exception
346 23:03:15.992613 ARM64: Done test exception
347 23:03:15.999151 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
348 23:03:16.009582 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
349 23:03:16.016431 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
350 23:03:16.026740 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
351 23:03:16.033753 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
352 23:03:16.039608 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
353 23:03:16.050530 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
354 23:03:16.057564 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
355 23:03:16.077130 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
356 23:03:16.080594 WDT: Last reset was cold boot
357 23:03:16.084059 SPI1(PAD0) initialized at 2873684 Hz
358 23:03:16.086700 SPI5(PAD0) initialized at 992727 Hz
359 23:03:16.090422 VBOOT: Loading verstage.
360 23:03:16.097033 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
361 23:03:16.100463 FMAP: Found "FLASH" version 1.1 at 0x20000.
362 23:03:16.103392 FMAP: base = 0x0 size = 0x800000 #areas = 25
363 23:03:16.106747 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
364 23:03:16.114554 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
365 23:03:16.121076 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
366 23:03:16.131725 read SPI 0x96554 0xa1eb: 4594 us, 9022 KB/s, 72.176 Mbps
367 23:03:16.131818
368 23:03:16.131884
369 23:03:16.142413 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
370 23:03:16.145044 ARM64: Exception handlers installed.
371 23:03:16.148400 ARM64: Testing exception
372 23:03:16.148485 ARM64: Done test exception
373 23:03:16.155329 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
374 23:03:16.158592 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
375 23:03:16.173007 Probing TPM: . done!
376 23:03:16.173151 TPM ready after 0 ms
377 23:03:16.180161 Connected to device vid:did:rid of 1ae0:0028:00
378 23:03:16.186791 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
379 23:03:16.244122 Initialized TPM device CR50 revision 0
380 23:03:16.256251 tlcl_send_startup: Startup return code is 0
381 23:03:16.256388 TPM: setup succeeded
382 23:03:16.267367 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
383 23:03:16.275954 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
384 23:03:16.286848 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
385 23:03:16.297433 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
386 23:03:16.300350 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
387 23:03:16.308907 in-header: 03 07 00 00 08 00 00 00
388 23:03:16.312861 in-data: aa e4 47 04 13 02 00 00
389 23:03:16.316473 Chrome EC: UHEPI supported
390 23:03:16.324026 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
391 23:03:16.327202 in-header: 03 ad 00 00 08 00 00 00
392 23:03:16.327305 in-data: 00 20 20 08 00 00 00 00
393 23:03:16.330856 Phase 1
394 23:03:16.334744 FMAP: area GBB found @ 3f5000 (12032 bytes)
395 23:03:16.338982 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
396 23:03:16.346233 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
397 23:03:16.350541 Recovery requested (1009000e)
398 23:03:16.357579 TPM: Extending digest for VBOOT: boot mode into PCR 0
399 23:03:16.363121 tlcl_extend: response is 0
400 23:03:16.372577 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
401 23:03:16.377587 tlcl_extend: response is 0
402 23:03:16.384955 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
403 23:03:16.405344 read SPI 0x210d4 0x2173b: 15146 us, 9046 KB/s, 72.368 Mbps
404 23:03:16.411386 BS: bootblock times (exec / console): total (unknown) / 148 ms
405 23:03:16.411508
406 23:03:16.411600
407 23:03:16.422555 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
408 23:03:16.426011 ARM64: Exception handlers installed.
409 23:03:16.426113 ARM64: Testing exception
410 23:03:16.429593 ARM64: Done test exception
411 23:03:16.450253 pmic_efuse_setting: Set efuses in 11 msecs
412 23:03:16.453855 pmwrap_interface_init: Select PMIF_VLD_RDY
413 23:03:16.461095 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
414 23:03:16.463958 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
415 23:03:16.467703 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
416 23:03:16.474668 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
417 23:03:16.478558 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
418 23:03:16.482418 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
419 23:03:16.489476 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
420 23:03:16.493325 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
421 23:03:16.496850 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
422 23:03:16.500610 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
423 23:03:16.508316 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
424 23:03:16.512399 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
425 23:03:16.515777 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
426 23:03:16.523090 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
427 23:03:16.526694 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
428 23:03:16.533993 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
429 23:03:16.538122 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
430 23:03:16.545440 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
431 23:03:16.552601 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
432 23:03:16.556778 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
433 23:03:16.560369 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
434 23:03:16.567479 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
435 23:03:16.575086 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
436 23:03:16.578743 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
437 23:03:16.582438 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
438 23:03:16.590403 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
439 23:03:16.593705 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
440 23:03:16.600885 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
441 23:03:16.604985 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
442 23:03:16.608083 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
443 23:03:16.616082 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
444 23:03:16.619650 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
445 23:03:16.623285 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
446 23:03:16.630385 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
447 23:03:16.634397 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
448 23:03:16.638039 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
449 23:03:16.645663 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
450 23:03:16.649662 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
451 23:03:16.652946 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
452 23:03:16.656828 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
453 23:03:16.664088 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
454 23:03:16.668044 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
455 23:03:16.671254 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
456 23:03:16.675237 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
457 23:03:16.678692 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
458 23:03:16.685971 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
459 23:03:16.689482 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
460 23:03:16.693292 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
461 23:03:16.696966 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
462 23:03:16.700880 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
463 23:03:16.704295 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
464 23:03:16.711747 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
465 23:03:16.722739 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
466 23:03:16.726574 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
467 23:03:16.734478 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
468 23:03:16.741171 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
469 23:03:16.748698 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
470 23:03:16.752695 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
471 23:03:16.755811 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
472 23:03:16.763957 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x3
473 23:03:16.766985 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
474 23:03:16.775235 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
475 23:03:16.778343 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
476 23:03:16.787884 [RTC]rtc_get_frequency_meter,154: input=15, output=790
477 23:03:16.797355 [RTC]rtc_get_frequency_meter,154: input=23, output=979
478 23:03:16.806365 [RTC]rtc_get_frequency_meter,154: input=19, output=884
479 23:03:16.816018 [RTC]rtc_get_frequency_meter,154: input=17, output=838
480 23:03:16.825793 [RTC]rtc_get_frequency_meter,154: input=16, output=813
481 23:03:16.835031 [RTC]rtc_get_frequency_meter,154: input=15, output=790
482 23:03:16.844964 [RTC]rtc_get_frequency_meter,154: input=16, output=814
483 23:03:16.849041 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
484 23:03:16.852607 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
485 23:03:16.856072 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
486 23:03:16.863238 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
487 23:03:16.866913 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
488 23:03:16.870876 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
489 23:03:16.874595 ADC[4]: Raw value=901328 ID=7
490 23:03:16.874689 ADC[3]: Raw value=213336 ID=1
491 23:03:16.878387 RAM Code: 0x71
492 23:03:16.882018 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
493 23:03:16.885794 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
494 23:03:16.897215 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
495 23:03:16.904368 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
496 23:03:16.904484 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
497 23:03:16.909027 in-header: 03 07 00 00 08 00 00 00
498 23:03:16.912137 in-data: aa e4 47 04 13 02 00 00
499 23:03:16.915879 Chrome EC: UHEPI supported
500 23:03:16.922820 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
501 23:03:16.926787 in-header: 03 ed 00 00 08 00 00 00
502 23:03:16.930555 in-data: 80 20 60 08 00 00 00 00
503 23:03:16.930649 MRC: failed to locate region type 0.
504 23:03:16.937515 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
505 23:03:16.941624 DRAM-K: Running full calibration
506 23:03:16.949804 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
507 23:03:16.949931 header.status = 0x0
508 23:03:16.953249 header.version = 0x6 (expected: 0x6)
509 23:03:16.956893 header.size = 0xd00 (expected: 0xd00)
510 23:03:16.956981 header.flags = 0x0
511 23:03:16.964100 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
512 23:03:16.981872 read SPI 0x72590 0x1c583: 12503 us, 9285 KB/s, 74.280 Mbps
513 23:03:16.989506 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
514 23:03:16.993500 dram_init: ddr_geometry: 2
515 23:03:16.993595 [EMI] MDL number = 2
516 23:03:16.997557 [EMI] Get MDL freq = 0
517 23:03:16.997647 dram_init: ddr_type: 0
518 23:03:17.000795 is_discrete_lpddr4: 1
519 23:03:17.003861 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
520 23:03:17.003949
521 23:03:17.004036
522 23:03:17.007748 [Bian_co] ETT version 0.0.0.1
523 23:03:17.010931 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
524 23:03:17.011047
525 23:03:17.015251 dramc_set_vcore_voltage set vcore to 650000
526 23:03:17.018884 Read voltage for 800, 4
527 23:03:17.019003 Vio18 = 0
528 23:03:17.019084 Vcore = 650000
529 23:03:17.019146 Vdram = 0
530 23:03:17.021859 Vddq = 0
531 23:03:17.021942 Vmddr = 0
532 23:03:17.025703 dram_init: config_dvfs: 1
533 23:03:17.028527 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
534 23:03:17.035539 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
535 23:03:17.038570 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
536 23:03:17.042458 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
537 23:03:17.045154 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
538 23:03:17.048797 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
539 23:03:17.052100 MEM_TYPE=3, freq_sel=18
540 23:03:17.055577 sv_algorithm_assistance_LP4_1600
541 23:03:17.058761 ============ PULL DRAM RESETB DOWN ============
542 23:03:17.062526 ========== PULL DRAM RESETB DOWN end =========
543 23:03:17.068788 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
544 23:03:17.072475 ===================================
545 23:03:17.072563 LPDDR4 DRAM CONFIGURATION
546 23:03:17.076401 ===================================
547 23:03:17.079432 EX_ROW_EN[0] = 0x0
548 23:03:17.082184 EX_ROW_EN[1] = 0x0
549 23:03:17.082270 LP4Y_EN = 0x0
550 23:03:17.085625 WORK_FSP = 0x0
551 23:03:17.085711 WL = 0x2
552 23:03:17.088919 RL = 0x2
553 23:03:17.089005 BL = 0x2
554 23:03:17.092511 RPST = 0x0
555 23:03:17.092607 RD_PRE = 0x0
556 23:03:17.096023 WR_PRE = 0x1
557 23:03:17.096134 WR_PST = 0x0
558 23:03:17.099067 DBI_WR = 0x0
559 23:03:17.099154 DBI_RD = 0x0
560 23:03:17.102674 OTF = 0x1
561 23:03:17.105994 ===================================
562 23:03:17.108997 ===================================
563 23:03:17.109087 ANA top config
564 23:03:17.112632 ===================================
565 23:03:17.115884 DLL_ASYNC_EN = 0
566 23:03:17.119346 ALL_SLAVE_EN = 1
567 23:03:17.119433 NEW_RANK_MODE = 1
568 23:03:17.122396 DLL_IDLE_MODE = 1
569 23:03:17.125867 LP45_APHY_COMB_EN = 1
570 23:03:17.129522 TX_ODT_DIS = 1
571 23:03:17.129611 NEW_8X_MODE = 1
572 23:03:17.133145 ===================================
573 23:03:17.136358 ===================================
574 23:03:17.139558 data_rate = 1600
575 23:03:17.142998 CKR = 1
576 23:03:17.146621 DQ_P2S_RATIO = 8
577 23:03:17.150057 ===================================
578 23:03:17.152717 CA_P2S_RATIO = 8
579 23:03:17.156012 DQ_CA_OPEN = 0
580 23:03:17.156105 DQ_SEMI_OPEN = 0
581 23:03:17.159572 CA_SEMI_OPEN = 0
582 23:03:17.162791 CA_FULL_RATE = 0
583 23:03:17.166444 DQ_CKDIV4_EN = 1
584 23:03:17.169710 CA_CKDIV4_EN = 1
585 23:03:17.169819 CA_PREDIV_EN = 0
586 23:03:17.172954 PH8_DLY = 0
587 23:03:17.176560 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
588 23:03:17.180207 DQ_AAMCK_DIV = 4
589 23:03:17.183341 CA_AAMCK_DIV = 4
590 23:03:17.186140 CA_ADMCK_DIV = 4
591 23:03:17.186256 DQ_TRACK_CA_EN = 0
592 23:03:17.190036 CA_PICK = 800
593 23:03:17.192887 CA_MCKIO = 800
594 23:03:17.196213 MCKIO_SEMI = 0
595 23:03:17.200317 PLL_FREQ = 3068
596 23:03:17.203798 DQ_UI_PI_RATIO = 32
597 23:03:17.203991 CA_UI_PI_RATIO = 0
598 23:03:17.207745 ===================================
599 23:03:17.210819 ===================================
600 23:03:17.214879 memory_type:LPDDR4
601 23:03:17.215025 GP_NUM : 10
602 23:03:17.218562 SRAM_EN : 1
603 23:03:17.218666 MD32_EN : 0
604 23:03:17.222615 ===================================
605 23:03:17.226138 [ANA_INIT] >>>>>>>>>>>>>>
606 23:03:17.229876 <<<<<< [CONFIGURE PHASE]: ANA_TX
607 23:03:17.233369 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
608 23:03:17.237022 ===================================
609 23:03:17.237182 data_rate = 1600,PCW = 0X7600
610 23:03:17.240545 ===================================
611 23:03:17.244082 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
612 23:03:17.250836 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
613 23:03:17.257690 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
614 23:03:17.260973 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
615 23:03:17.264061 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
616 23:03:17.267332 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
617 23:03:17.270760 [ANA_INIT] flow start
618 23:03:17.270844 [ANA_INIT] PLL >>>>>>>>
619 23:03:17.274321 [ANA_INIT] PLL <<<<<<<<
620 23:03:17.277631 [ANA_INIT] MIDPI >>>>>>>>
621 23:03:17.277709 [ANA_INIT] MIDPI <<<<<<<<
622 23:03:17.280759 [ANA_INIT] DLL >>>>>>>>
623 23:03:17.284104 [ANA_INIT] flow end
624 23:03:17.287426 ============ LP4 DIFF to SE enter ============
625 23:03:17.290865 ============ LP4 DIFF to SE exit ============
626 23:03:17.294302 [ANA_INIT] <<<<<<<<<<<<<
627 23:03:17.297979 [Flow] Enable top DCM control >>>>>
628 23:03:17.301039 [Flow] Enable top DCM control <<<<<
629 23:03:17.304613 Enable DLL master slave shuffle
630 23:03:17.307708 ==============================================================
631 23:03:17.311303 Gating Mode config
632 23:03:17.314373 ==============================================================
633 23:03:17.317912 Config description:
634 23:03:17.327820 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
635 23:03:17.334442 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
636 23:03:17.338117 SELPH_MODE 0: By rank 1: By Phase
637 23:03:17.344541 ==============================================================
638 23:03:17.348193 GAT_TRACK_EN = 1
639 23:03:17.351458 RX_GATING_MODE = 2
640 23:03:17.354950 RX_GATING_TRACK_MODE = 2
641 23:03:17.355045 SELPH_MODE = 1
642 23:03:17.358060 PICG_EARLY_EN = 1
643 23:03:17.361740 VALID_LAT_VALUE = 1
644 23:03:17.368158 ==============================================================
645 23:03:17.371857 Enter into Gating configuration >>>>
646 23:03:17.374717 Exit from Gating configuration <<<<
647 23:03:17.378501 Enter into DVFS_PRE_config >>>>>
648 23:03:17.388138 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
649 23:03:17.391503 Exit from DVFS_PRE_config <<<<<
650 23:03:17.394892 Enter into PICG configuration >>>>
651 23:03:17.398594 Exit from PICG configuration <<<<
652 23:03:17.402057 [RX_INPUT] configuration >>>>>
653 23:03:17.405222 [RX_INPUT] configuration <<<<<
654 23:03:17.408936 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
655 23:03:17.415047 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
656 23:03:17.419017 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
657 23:03:17.425989 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
658 23:03:17.432784 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
659 23:03:17.439225 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
660 23:03:17.442683 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
661 23:03:17.446061 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
662 23:03:17.449642 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
663 23:03:17.456299 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
664 23:03:17.459733 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
665 23:03:17.462938 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
666 23:03:17.466334 ===================================
667 23:03:17.469811 LPDDR4 DRAM CONFIGURATION
668 23:03:17.473407 ===================================
669 23:03:17.473505 EX_ROW_EN[0] = 0x0
670 23:03:17.476483 EX_ROW_EN[1] = 0x0
671 23:03:17.479754 LP4Y_EN = 0x0
672 23:03:17.479838 WORK_FSP = 0x0
673 23:03:17.483199 WL = 0x2
674 23:03:17.483295 RL = 0x2
675 23:03:17.486785 BL = 0x2
676 23:03:17.486879 RPST = 0x0
677 23:03:17.490148 RD_PRE = 0x0
678 23:03:17.490228 WR_PRE = 0x1
679 23:03:17.493818 WR_PST = 0x0
680 23:03:17.493924 DBI_WR = 0x0
681 23:03:17.496727 DBI_RD = 0x0
682 23:03:17.496806 OTF = 0x1
683 23:03:17.500018 ===================================
684 23:03:17.503982 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
685 23:03:17.510002 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
686 23:03:17.513513 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
687 23:03:17.517383 ===================================
688 23:03:17.520540 LPDDR4 DRAM CONFIGURATION
689 23:03:17.523582 ===================================
690 23:03:17.523678 EX_ROW_EN[0] = 0x10
691 23:03:17.526858 EX_ROW_EN[1] = 0x0
692 23:03:17.526950 LP4Y_EN = 0x0
693 23:03:17.530339 WORK_FSP = 0x0
694 23:03:17.530422 WL = 0x2
695 23:03:17.533378 RL = 0x2
696 23:03:17.533457 BL = 0x2
697 23:03:17.537025 RPST = 0x0
698 23:03:17.537102 RD_PRE = 0x0
699 23:03:17.540342 WR_PRE = 0x1
700 23:03:17.540442 WR_PST = 0x0
701 23:03:17.543990 DBI_WR = 0x0
702 23:03:17.544083 DBI_RD = 0x0
703 23:03:17.547225 OTF = 0x1
704 23:03:17.550680 ===================================
705 23:03:17.557165 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
706 23:03:17.560636 nWR fixed to 40
707 23:03:17.563767 [ModeRegInit_LP4] CH0 RK0
708 23:03:17.563856 [ModeRegInit_LP4] CH0 RK1
709 23:03:17.567795 [ModeRegInit_LP4] CH1 RK0
710 23:03:17.571306 [ModeRegInit_LP4] CH1 RK1
711 23:03:17.571394 match AC timing 13
712 23:03:17.577712 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
713 23:03:17.580570 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
714 23:03:17.584205 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
715 23:03:17.587322 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
716 23:03:17.594885 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
717 23:03:17.595001 [EMI DOE] emi_dcm 0
718 23:03:17.600816 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
719 23:03:17.600930 ==
720 23:03:17.604421 Dram Type= 6, Freq= 0, CH_0, rank 0
721 23:03:17.607753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
722 23:03:17.607842 ==
723 23:03:17.610879 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
724 23:03:17.617707 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
725 23:03:17.627488 [CA 0] Center 37 (7~68) winsize 62
726 23:03:17.631279 [CA 1] Center 37 (6~68) winsize 63
727 23:03:17.634389 [CA 2] Center 35 (5~66) winsize 62
728 23:03:17.637988 [CA 3] Center 34 (4~65) winsize 62
729 23:03:17.640954 [CA 4] Center 34 (3~65) winsize 63
730 23:03:17.644422 [CA 5] Center 33 (3~64) winsize 62
731 23:03:17.644517
732 23:03:17.647821 [CmdBusTrainingLP45] Vref(ca) range 1: 34
733 23:03:17.647914
734 23:03:17.651153 [CATrainingPosCal] consider 1 rank data
735 23:03:17.654586 u2DelayCellTimex100 = 270/100 ps
736 23:03:17.658024 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
737 23:03:17.660960 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
738 23:03:17.668125 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
739 23:03:17.671176 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
740 23:03:17.674978 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
741 23:03:17.678079 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
742 23:03:17.678169
743 23:03:17.681778 CA PerBit enable=1, Macro0, CA PI delay=33
744 23:03:17.681860
745 23:03:17.684721 [CBTSetCACLKResult] CA Dly = 33
746 23:03:17.684802 CS Dly: 5 (0~36)
747 23:03:17.684867 ==
748 23:03:17.687967 Dram Type= 6, Freq= 0, CH_0, rank 1
749 23:03:17.694598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
750 23:03:17.694700 ==
751 23:03:17.697938 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
752 23:03:17.704606 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
753 23:03:17.713910 [CA 0] Center 37 (7~68) winsize 62
754 23:03:17.717099 [CA 1] Center 37 (7~68) winsize 62
755 23:03:17.720440 [CA 2] Center 35 (4~66) winsize 63
756 23:03:17.724131 [CA 3] Center 34 (4~65) winsize 62
757 23:03:17.726973 [CA 4] Center 34 (3~65) winsize 63
758 23:03:17.730492 [CA 5] Center 33 (3~64) winsize 62
759 23:03:17.730580
760 23:03:17.734253 [CmdBusTrainingLP45] Vref(ca) range 1: 34
761 23:03:17.734341
762 23:03:17.737420 [CATrainingPosCal] consider 2 rank data
763 23:03:17.740558 u2DelayCellTimex100 = 270/100 ps
764 23:03:17.744215 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
765 23:03:17.747432 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
766 23:03:17.750982 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
767 23:03:17.757727 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
768 23:03:17.760830 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
769 23:03:17.764624 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
770 23:03:17.764715
771 23:03:17.767689 CA PerBit enable=1, Macro0, CA PI delay=33
772 23:03:17.767781
773 23:03:17.771126 [CBTSetCACLKResult] CA Dly = 33
774 23:03:17.771208 CS Dly: 5 (0~37)
775 23:03:17.771275
776 23:03:17.774451 ----->DramcWriteLeveling(PI) begin...
777 23:03:17.774533 ==
778 23:03:17.777501 Dram Type= 6, Freq= 0, CH_0, rank 0
779 23:03:17.784923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
780 23:03:17.785097 ==
781 23:03:17.785198 Write leveling (Byte 0): 31 => 31
782 23:03:17.788759 Write leveling (Byte 1): 28 => 28
783 23:03:17.792089 DramcWriteLeveling(PI) end<-----
784 23:03:17.792185
785 23:03:17.792256 ==
786 23:03:17.796372 Dram Type= 6, Freq= 0, CH_0, rank 0
787 23:03:17.799568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
788 23:03:17.799663 ==
789 23:03:17.803056 [Gating] SW mode calibration
790 23:03:17.809906 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
791 23:03:17.816909 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
792 23:03:17.820759 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
793 23:03:17.823808 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
794 23:03:17.826987 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
795 23:03:17.833887 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
796 23:03:17.837007 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 23:03:17.840487 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 23:03:17.847291 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 23:03:17.851135 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 23:03:17.853905 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 23:03:17.860760 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 23:03:17.863690 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 23:03:17.867457 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 23:03:17.874147 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 23:03:17.877832 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 23:03:17.880599 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 23:03:17.884284 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 23:03:17.890866 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 23:03:17.894212 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 23:03:17.897875 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
811 23:03:17.904190 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
812 23:03:17.907826 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 23:03:17.911173 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
814 23:03:17.917838 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
815 23:03:17.921255 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 23:03:17.924459 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 23:03:17.931587 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 23:03:17.934998 0 9 8 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
819 23:03:17.937976 0 9 12 | B1->B0 | 2525 3333 | 0 0 | (1 0) (1 1)
820 23:03:17.941200 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
821 23:03:17.947857 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
822 23:03:17.951533 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
823 23:03:17.954887 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
824 23:03:17.961572 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
825 23:03:17.965050 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
826 23:03:17.968023 0 10 8 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
827 23:03:17.974615 0 10 12 | B1->B0 | 2e2e 2525 | 1 0 | (1 0) (0 0)
828 23:03:17.978057 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 23:03:17.981271 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 23:03:17.988333 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 23:03:17.991386 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 23:03:17.995189 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 23:03:17.998262 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
834 23:03:18.005093 0 11 8 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
835 23:03:18.008399 0 11 12 | B1->B0 | 3434 4444 | 0 0 | (0 0) (0 0)
836 23:03:18.011586 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
837 23:03:18.018232 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
838 23:03:18.022074 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
839 23:03:18.024898 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
840 23:03:18.031858 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
841 23:03:18.035498 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
842 23:03:18.038825 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
843 23:03:18.045743 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
844 23:03:18.048772 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 23:03:18.052125 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 23:03:18.055625 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 23:03:18.062656 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 23:03:18.065427 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 23:03:18.069191 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 23:03:18.075742 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 23:03:18.079402 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 23:03:18.082525 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
853 23:03:18.089015 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
854 23:03:18.092708 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
855 23:03:18.096226 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
856 23:03:18.099337 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
857 23:03:18.106101 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
858 23:03:18.109309 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
859 23:03:18.113109 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
860 23:03:18.119833 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
861 23:03:18.123100 Total UI for P1: 0, mck2ui 16
862 23:03:18.126427 best dqsien dly found for B0: ( 0, 14, 10)
863 23:03:18.126540 Total UI for P1: 0, mck2ui 16
864 23:03:18.133094 best dqsien dly found for B1: ( 0, 14, 10)
865 23:03:18.136450 best DQS0 dly(MCK, UI, PI) = (0, 14, 10)
866 23:03:18.139509 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
867 23:03:18.139665
868 23:03:18.142739 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 10)
869 23:03:18.146148 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
870 23:03:18.149630 [Gating] SW calibration Done
871 23:03:18.149792 ==
872 23:03:18.153138 Dram Type= 6, Freq= 0, CH_0, rank 0
873 23:03:18.156679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
874 23:03:18.156796 ==
875 23:03:18.159759 RX Vref Scan: 0
876 23:03:18.159867
877 23:03:18.159937 RX Vref 0 -> 0, step: 1
878 23:03:18.160000
879 23:03:18.163256 RX Delay -130 -> 252, step: 16
880 23:03:18.166626 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
881 23:03:18.173025 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
882 23:03:18.176783 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
883 23:03:18.180058 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
884 23:03:18.183769 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
885 23:03:18.186692 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
886 23:03:18.190140 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
887 23:03:18.196663 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
888 23:03:18.199983 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
889 23:03:18.203365 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
890 23:03:18.206686 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
891 23:03:18.210086 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
892 23:03:18.216758 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
893 23:03:18.220179 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
894 23:03:18.223471 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
895 23:03:18.226847 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
896 23:03:18.226962 ==
897 23:03:18.230436 Dram Type= 6, Freq= 0, CH_0, rank 0
898 23:03:18.237014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
899 23:03:18.237184 ==
900 23:03:18.237295 DQS Delay:
901 23:03:18.237397 DQS0 = 0, DQS1 = 0
902 23:03:18.240497 DQM Delay:
903 23:03:18.240613 DQM0 = 84, DQM1 = 79
904 23:03:18.244607 DQ Delay:
905 23:03:18.244719 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
906 23:03:18.247052 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =85
907 23:03:18.250774 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =77
908 23:03:18.253958 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
909 23:03:18.254065
910 23:03:18.257188
911 23:03:18.257287 ==
912 23:03:18.260985 Dram Type= 6, Freq= 0, CH_0, rank 0
913 23:03:18.264213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
914 23:03:18.264320 ==
915 23:03:18.264413
916 23:03:18.264495
917 23:03:18.267355 TX Vref Scan disable
918 23:03:18.267440 == TX Byte 0 ==
919 23:03:18.271354 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
920 23:03:18.277705 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
921 23:03:18.277856 == TX Byte 1 ==
922 23:03:18.280966 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
923 23:03:18.287590 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
924 23:03:18.287718 ==
925 23:03:18.290798 Dram Type= 6, Freq= 0, CH_0, rank 0
926 23:03:18.294195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
927 23:03:18.294297 ==
928 23:03:18.307567 TX Vref=22, minBit 5, minWin=27, winSum=440
929 23:03:18.311084 TX Vref=24, minBit 5, minWin=27, winSum=444
930 23:03:18.314461 TX Vref=26, minBit 12, minWin=27, winSum=448
931 23:03:18.317622 TX Vref=28, minBit 8, minWin=27, winSum=452
932 23:03:18.321155 TX Vref=30, minBit 2, minWin=28, winSum=456
933 23:03:18.328002 TX Vref=32, minBit 2, minWin=28, winSum=458
934 23:03:18.331474 [TxChooseVref] Worse bit 2, Min win 28, Win sum 458, Final Vref 32
935 23:03:18.331579
936 23:03:18.334828 Final TX Range 1 Vref 32
937 23:03:18.334933
938 23:03:18.335020 ==
939 23:03:18.337600 Dram Type= 6, Freq= 0, CH_0, rank 0
940 23:03:18.341277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
941 23:03:18.341397 ==
942 23:03:18.344337
943 23:03:18.344432
944 23:03:18.344535 TX Vref Scan disable
945 23:03:18.347984 == TX Byte 0 ==
946 23:03:18.351015 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
947 23:03:18.354833 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
948 23:03:18.358271 == TX Byte 1 ==
949 23:03:18.361448 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
950 23:03:18.364588 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
951 23:03:18.368052
952 23:03:18.368162 [DATLAT]
953 23:03:18.368236 Freq=800, CH0 RK0
954 23:03:18.368301
955 23:03:18.371359 DATLAT Default: 0xa
956 23:03:18.371440 0, 0xFFFF, sum = 0
957 23:03:18.374431 1, 0xFFFF, sum = 0
958 23:03:18.374517 2, 0xFFFF, sum = 0
959 23:03:18.378140 3, 0xFFFF, sum = 0
960 23:03:18.378237 4, 0xFFFF, sum = 0
961 23:03:18.381214 5, 0xFFFF, sum = 0
962 23:03:18.381301 6, 0xFFFF, sum = 0
963 23:03:18.384970 7, 0xFFFF, sum = 0
964 23:03:18.385069 8, 0xFFFF, sum = 0
965 23:03:18.388423 9, 0x0, sum = 1
966 23:03:18.388512 10, 0x0, sum = 2
967 23:03:18.391406 11, 0x0, sum = 3
968 23:03:18.391490 12, 0x0, sum = 4
969 23:03:18.394739 best_step = 10
970 23:03:18.394821
971 23:03:18.394909 ==
972 23:03:18.398344 Dram Type= 6, Freq= 0, CH_0, rank 0
973 23:03:18.401599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 23:03:18.401704 ==
975 23:03:18.404776 RX Vref Scan: 1
976 23:03:18.404871
977 23:03:18.404940 Set Vref Range= 32 -> 127
978 23:03:18.405003
979 23:03:18.408077 RX Vref 32 -> 127, step: 1
980 23:03:18.408166
981 23:03:18.411404 RX Delay -95 -> 252, step: 8
982 23:03:18.411496
983 23:03:18.414832 Set Vref, RX VrefLevel [Byte0]: 32
984 23:03:18.418167 [Byte1]: 32
985 23:03:18.418272
986 23:03:18.422101 Set Vref, RX VrefLevel [Byte0]: 33
987 23:03:18.425463 [Byte1]: 33
988 23:03:18.425569
989 23:03:18.428930 Set Vref, RX VrefLevel [Byte0]: 34
990 23:03:18.432291 [Byte1]: 34
991 23:03:18.435507
992 23:03:18.435623 Set Vref, RX VrefLevel [Byte0]: 35
993 23:03:18.438943 [Byte1]: 35
994 23:03:18.443665
995 23:03:18.443783 Set Vref, RX VrefLevel [Byte0]: 36
996 23:03:18.446550 [Byte1]: 36
997 23:03:18.451394
998 23:03:18.451504 Set Vref, RX VrefLevel [Byte0]: 37
999 23:03:18.454707 [Byte1]: 37
1000 23:03:18.459180
1001 23:03:18.459298 Set Vref, RX VrefLevel [Byte0]: 38
1002 23:03:18.462278 [Byte1]: 38
1003 23:03:18.466459
1004 23:03:18.466561 Set Vref, RX VrefLevel [Byte0]: 39
1005 23:03:18.469769 [Byte1]: 39
1006 23:03:18.474548
1007 23:03:18.474655 Set Vref, RX VrefLevel [Byte0]: 40
1008 23:03:18.477401 [Byte1]: 40
1009 23:03:18.481825
1010 23:03:18.481925 Set Vref, RX VrefLevel [Byte0]: 41
1011 23:03:18.484653 [Byte1]: 41
1012 23:03:18.488818
1013 23:03:18.488924 Set Vref, RX VrefLevel [Byte0]: 42
1014 23:03:18.492453 [Byte1]: 42
1015 23:03:18.496324
1016 23:03:18.496464 Set Vref, RX VrefLevel [Byte0]: 43
1017 23:03:18.500004 [Byte1]: 43
1018 23:03:18.504491
1019 23:03:18.504582 Set Vref, RX VrefLevel [Byte0]: 44
1020 23:03:18.507561 [Byte1]: 44
1021 23:03:18.511424
1022 23:03:18.511514 Set Vref, RX VrefLevel [Byte0]: 45
1023 23:03:18.514981 [Byte1]: 45
1024 23:03:18.519459
1025 23:03:18.519570 Set Vref, RX VrefLevel [Byte0]: 46
1026 23:03:18.522652 [Byte1]: 46
1027 23:03:18.527000
1028 23:03:18.527093 Set Vref, RX VrefLevel [Byte0]: 47
1029 23:03:18.530158 [Byte1]: 47
1030 23:03:18.534739
1031 23:03:18.534842 Set Vref, RX VrefLevel [Byte0]: 48
1032 23:03:18.537528 [Byte1]: 48
1033 23:03:18.542183
1034 23:03:18.542307 Set Vref, RX VrefLevel [Byte0]: 49
1035 23:03:18.545578 [Byte1]: 49
1036 23:03:18.549477
1037 23:03:18.549577 Set Vref, RX VrefLevel [Byte0]: 50
1038 23:03:18.553388 [Byte1]: 50
1039 23:03:18.557174
1040 23:03:18.557278 Set Vref, RX VrefLevel [Byte0]: 51
1041 23:03:18.560809 [Byte1]: 51
1042 23:03:18.564976
1043 23:03:18.565088 Set Vref, RX VrefLevel [Byte0]: 52
1044 23:03:18.568468 [Byte1]: 52
1045 23:03:18.572242
1046 23:03:18.572338 Set Vref, RX VrefLevel [Byte0]: 53
1047 23:03:18.575685 [Byte1]: 53
1048 23:03:18.580054
1049 23:03:18.580155 Set Vref, RX VrefLevel [Byte0]: 54
1050 23:03:18.583284 [Byte1]: 54
1051 23:03:18.587474
1052 23:03:18.587570 Set Vref, RX VrefLevel [Byte0]: 55
1053 23:03:18.590798 [Byte1]: 55
1054 23:03:18.595388
1055 23:03:18.595481 Set Vref, RX VrefLevel [Byte0]: 56
1056 23:03:18.598887 [Byte1]: 56
1057 23:03:18.603089
1058 23:03:18.603182 Set Vref, RX VrefLevel [Byte0]: 57
1059 23:03:18.606163 [Byte1]: 57
1060 23:03:18.610384
1061 23:03:18.610474 Set Vref, RX VrefLevel [Byte0]: 58
1062 23:03:18.613824 [Byte1]: 58
1063 23:03:18.618449
1064 23:03:18.618547 Set Vref, RX VrefLevel [Byte0]: 59
1065 23:03:18.621207 [Byte1]: 59
1066 23:03:18.625955
1067 23:03:18.626050 Set Vref, RX VrefLevel [Byte0]: 60
1068 23:03:18.628987 [Byte1]: 60
1069 23:03:18.632996
1070 23:03:18.633088 Set Vref, RX VrefLevel [Byte0]: 61
1071 23:03:18.636738 [Byte1]: 61
1072 23:03:18.640897
1073 23:03:18.641006 Set Vref, RX VrefLevel [Byte0]: 62
1074 23:03:18.643978 [Byte1]: 62
1075 23:03:18.648574
1076 23:03:18.648670 Set Vref, RX VrefLevel [Byte0]: 63
1077 23:03:18.651684 [Byte1]: 63
1078 23:03:18.655875
1079 23:03:18.655975 Set Vref, RX VrefLevel [Byte0]: 64
1080 23:03:18.659014 [Byte1]: 64
1081 23:03:18.663549
1082 23:03:18.663660 Set Vref, RX VrefLevel [Byte0]: 65
1083 23:03:18.667165 [Byte1]: 65
1084 23:03:18.671286
1085 23:03:18.671398 Set Vref, RX VrefLevel [Byte0]: 66
1086 23:03:18.674644 [Byte1]: 66
1087 23:03:18.678731
1088 23:03:18.678855 Set Vref, RX VrefLevel [Byte0]: 67
1089 23:03:18.682182 [Byte1]: 67
1090 23:03:18.686449
1091 23:03:18.686549 Set Vref, RX VrefLevel [Byte0]: 68
1092 23:03:18.689461 [Byte1]: 68
1093 23:03:18.693835
1094 23:03:18.693927 Set Vref, RX VrefLevel [Byte0]: 69
1095 23:03:18.697499 [Byte1]: 69
1096 23:03:18.701474
1097 23:03:18.701562 Set Vref, RX VrefLevel [Byte0]: 70
1098 23:03:18.704805 [Byte1]: 70
1099 23:03:18.709458
1100 23:03:18.709552 Set Vref, RX VrefLevel [Byte0]: 71
1101 23:03:18.712272 [Byte1]: 71
1102 23:03:18.716728
1103 23:03:18.716823 Set Vref, RX VrefLevel [Byte0]: 72
1104 23:03:18.719911 [Byte1]: 72
1105 23:03:18.724228
1106 23:03:18.724307 Set Vref, RX VrefLevel [Byte0]: 73
1107 23:03:18.728099 [Byte1]: 73
1108 23:03:18.731887
1109 23:03:18.731967 Set Vref, RX VrefLevel [Byte0]: 74
1110 23:03:18.735085 [Byte1]: 74
1111 23:03:18.739325
1112 23:03:18.739409 Set Vref, RX VrefLevel [Byte0]: 75
1113 23:03:18.742697 [Byte1]: 75
1114 23:03:18.747123
1115 23:03:18.747219 Set Vref, RX VrefLevel [Byte0]: 76
1116 23:03:18.750954 [Byte1]: 76
1117 23:03:18.755111
1118 23:03:18.755189 Final RX Vref Byte 0 = 61 to rank0
1119 23:03:18.758121 Final RX Vref Byte 1 = 58 to rank0
1120 23:03:18.761369 Final RX Vref Byte 0 = 61 to rank1
1121 23:03:18.764679 Final RX Vref Byte 1 = 58 to rank1==
1122 23:03:18.767910 Dram Type= 6, Freq= 0, CH_0, rank 0
1123 23:03:18.774519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1124 23:03:18.774613 ==
1125 23:03:18.774681 DQS Delay:
1126 23:03:18.774749 DQS0 = 0, DQS1 = 0
1127 23:03:18.777951 DQM Delay:
1128 23:03:18.778025 DQM0 = 87, DQM1 = 79
1129 23:03:18.781527 DQ Delay:
1130 23:03:18.784741 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84
1131 23:03:18.784816 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =92
1132 23:03:18.788182 DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =76
1133 23:03:18.791606 DQ12 =88, DQ13 =84, DQ14 =88, DQ15 =88
1134 23:03:18.794516
1135 23:03:18.794589
1136 23:03:18.801534 [DQSOSCAuto] RK0, (LSB)MR18= 0x260d, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 400 ps
1137 23:03:18.805079 CH0 RK0: MR19=606, MR18=260D
1138 23:03:18.811630 CH0_RK0: MR19=0x606, MR18=0x260D, DQSOSC=400, MR23=63, INC=92, DEC=61
1139 23:03:18.811714
1140 23:03:18.814941 ----->DramcWriteLeveling(PI) begin...
1141 23:03:18.815045 ==
1142 23:03:18.818616 Dram Type= 6, Freq= 0, CH_0, rank 1
1143 23:03:18.821921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1144 23:03:18.821996 ==
1145 23:03:18.824900 Write leveling (Byte 0): 31 => 31
1146 23:03:18.828483 Write leveling (Byte 1): 26 => 26
1147 23:03:18.831601 DramcWriteLeveling(PI) end<-----
1148 23:03:18.831689
1149 23:03:18.831775 ==
1150 23:03:18.834907 Dram Type= 6, Freq= 0, CH_0, rank 1
1151 23:03:18.838395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1152 23:03:18.838475 ==
1153 23:03:18.842030 [Gating] SW mode calibration
1154 23:03:18.848427 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1155 23:03:18.855128 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1156 23:03:18.858549 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1157 23:03:18.861998 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1158 23:03:18.906033 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1159 23:03:18.906379 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 23:03:18.906474 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 23:03:18.906560 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 23:03:18.906656 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 23:03:18.906950 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 23:03:18.907489 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 23:03:18.907750 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 23:03:18.907822 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 23:03:18.907905 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 23:03:18.932931 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 23:03:18.933256 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 23:03:18.933530 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 23:03:18.933606 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 23:03:18.933880 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 23:03:18.936667 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1174 23:03:18.940226 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1175 23:03:18.943189 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 23:03:18.946481 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 23:03:18.950097 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 23:03:18.953810 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 23:03:18.959971 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 23:03:18.963392 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 23:03:18.967077 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
1182 23:03:18.974339 0 9 8 | B1->B0 | 2323 2f2f | 0 0 | (1 1) (0 0)
1183 23:03:18.977090 0 9 12 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
1184 23:03:18.980436 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 23:03:18.986819 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 23:03:18.990176 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1187 23:03:18.993787 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1188 23:03:18.997180 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1189 23:03:19.003736 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
1190 23:03:19.006994 0 10 8 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)
1191 23:03:19.010281 0 10 12 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
1192 23:03:19.017257 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 23:03:19.020784 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 23:03:19.024427 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 23:03:19.030921 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 23:03:19.034580 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 23:03:19.038916 0 11 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
1198 23:03:19.042654 0 11 8 | B1->B0 | 2e2e 4241 | 0 1 | (0 0) (0 0)
1199 23:03:19.046359 0 11 12 | B1->B0 | 3f3f 4646 | 1 0 | (0 0) (0 0)
1200 23:03:19.049787 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 23:03:19.056323 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 23:03:19.060192 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 23:03:19.064444 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1204 23:03:19.067681 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1205 23:03:19.074591 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1206 23:03:19.078041 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1207 23:03:19.081301 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1208 23:03:19.087980 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 23:03:19.091247 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 23:03:19.094851 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 23:03:19.101464 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 23:03:19.104619 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 23:03:19.108110 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 23:03:19.111495 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 23:03:19.118612 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 23:03:19.121577 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 23:03:19.125094 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 23:03:19.131922 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 23:03:19.135120 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 23:03:19.138399 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 23:03:19.145408 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 23:03:19.148264 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1223 23:03:19.151817 Total UI for P1: 0, mck2ui 16
1224 23:03:19.155241 best dqsien dly found for B0: ( 0, 14, 6)
1225 23:03:19.158689 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1226 23:03:19.161789 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1227 23:03:19.165325 Total UI for P1: 0, mck2ui 16
1228 23:03:19.168940 best dqsien dly found for B1: ( 0, 14, 10)
1229 23:03:19.171922 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1230 23:03:19.175307 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1231 23:03:19.175412
1232 23:03:19.182174 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1233 23:03:19.185323 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1234 23:03:19.185407 [Gating] SW calibration Done
1235 23:03:19.188846 ==
1236 23:03:19.192114 Dram Type= 6, Freq= 0, CH_0, rank 1
1237 23:03:19.195533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1238 23:03:19.195617 ==
1239 23:03:19.195703 RX Vref Scan: 0
1240 23:03:19.195785
1241 23:03:19.198903 RX Vref 0 -> 0, step: 1
1242 23:03:19.199005
1243 23:03:19.202065 RX Delay -130 -> 252, step: 16
1244 23:03:19.205639 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1245 23:03:19.208745 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1246 23:03:19.212107 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1247 23:03:19.219081 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1248 23:03:19.222667 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1249 23:03:19.226102 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1250 23:03:19.229165 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1251 23:03:19.232803 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1252 23:03:19.239129 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1253 23:03:19.242609 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1254 23:03:19.245679 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1255 23:03:19.249283 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1256 23:03:19.252563 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1257 23:03:19.259969 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1258 23:03:19.262974 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1259 23:03:19.266047 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1260 23:03:19.266139 ==
1261 23:03:19.269359 Dram Type= 6, Freq= 0, CH_0, rank 1
1262 23:03:19.273178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1263 23:03:19.273263 ==
1264 23:03:19.276439 DQS Delay:
1265 23:03:19.276515 DQS0 = 0, DQS1 = 0
1266 23:03:19.276579 DQM Delay:
1267 23:03:19.279772 DQM0 = 90, DQM1 = 80
1268 23:03:19.279847 DQ Delay:
1269 23:03:19.283042 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
1270 23:03:19.286208 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
1271 23:03:19.289642 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =77
1272 23:03:19.293274 DQ12 =77, DQ13 =93, DQ14 =93, DQ15 =93
1273 23:03:19.293349
1274 23:03:19.293410
1275 23:03:19.293469 ==
1276 23:03:19.297002 Dram Type= 6, Freq= 0, CH_0, rank 1
1277 23:03:19.303111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1278 23:03:19.303204 ==
1279 23:03:19.303270
1280 23:03:19.303330
1281 23:03:19.303388 TX Vref Scan disable
1282 23:03:19.306798 == TX Byte 0 ==
1283 23:03:19.309885 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1284 23:03:19.313295 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1285 23:03:19.316736 == TX Byte 1 ==
1286 23:03:19.320109 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1287 23:03:19.323428 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1288 23:03:19.327072 ==
1289 23:03:19.327150 Dram Type= 6, Freq= 0, CH_0, rank 1
1290 23:03:19.333331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1291 23:03:19.333418 ==
1292 23:03:19.346116 TX Vref=22, minBit 9, minWin=26, winSum=439
1293 23:03:19.349618 TX Vref=24, minBit 9, minWin=26, winSum=443
1294 23:03:19.352806 TX Vref=26, minBit 12, minWin=26, winSum=443
1295 23:03:19.356187 TX Vref=28, minBit 8, minWin=27, winSum=450
1296 23:03:19.360032 TX Vref=30, minBit 8, minWin=27, winSum=452
1297 23:03:19.363223 TX Vref=32, minBit 9, minWin=27, winSum=452
1298 23:03:19.370093 [TxChooseVref] Worse bit 8, Min win 27, Win sum 452, Final Vref 30
1299 23:03:19.370191
1300 23:03:19.373086 Final TX Range 1 Vref 30
1301 23:03:19.373165
1302 23:03:19.373267 ==
1303 23:03:19.376421 Dram Type= 6, Freq= 0, CH_0, rank 1
1304 23:03:19.379870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1305 23:03:19.379949 ==
1306 23:03:19.380011
1307 23:03:19.380070
1308 23:03:19.383454 TX Vref Scan disable
1309 23:03:19.386479 == TX Byte 0 ==
1310 23:03:19.390228 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1311 23:03:19.393371 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1312 23:03:19.396540 == TX Byte 1 ==
1313 23:03:19.400223 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1314 23:03:19.403506 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1315 23:03:19.403586
1316 23:03:19.407067 [DATLAT]
1317 23:03:19.407141 Freq=800, CH0 RK1
1318 23:03:19.407203
1319 23:03:19.410518 DATLAT Default: 0xa
1320 23:03:19.410594 0, 0xFFFF, sum = 0
1321 23:03:19.413590 1, 0xFFFF, sum = 0
1322 23:03:19.413665 2, 0xFFFF, sum = 0
1323 23:03:19.416815 3, 0xFFFF, sum = 0
1324 23:03:19.416922 4, 0xFFFF, sum = 0
1325 23:03:19.420222 5, 0xFFFF, sum = 0
1326 23:03:19.420299 6, 0xFFFF, sum = 0
1327 23:03:19.423761 7, 0xFFFF, sum = 0
1328 23:03:19.423834 8, 0xFFFF, sum = 0
1329 23:03:19.427326 9, 0x0, sum = 1
1330 23:03:19.427410 10, 0x0, sum = 2
1331 23:03:19.430496 11, 0x0, sum = 3
1332 23:03:19.430571 12, 0x0, sum = 4
1333 23:03:19.433843 best_step = 10
1334 23:03:19.433937
1335 23:03:19.434029 ==
1336 23:03:19.437340 Dram Type= 6, Freq= 0, CH_0, rank 1
1337 23:03:19.440217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1338 23:03:19.440293 ==
1339 23:03:19.444046 RX Vref Scan: 0
1340 23:03:19.444156
1341 23:03:19.444222 RX Vref 0 -> 0, step: 1
1342 23:03:19.444282
1343 23:03:19.446967 RX Delay -111 -> 252, step: 8
1344 23:03:19.453812 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1345 23:03:19.457408 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1346 23:03:19.460288 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1347 23:03:19.463653 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1348 23:03:19.467520 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1349 23:03:19.470570 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1350 23:03:19.477499 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1351 23:03:19.480936 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1352 23:03:19.484727 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1353 23:03:19.487654 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1354 23:03:19.490966 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1355 23:03:19.494248 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1356 23:03:19.501219 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1357 23:03:19.504531 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1358 23:03:19.507629 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1359 23:03:19.510786 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1360 23:03:19.510894 ==
1361 23:03:19.514638 Dram Type= 6, Freq= 0, CH_0, rank 1
1362 23:03:19.521206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1363 23:03:19.521305 ==
1364 23:03:19.521369 DQS Delay:
1365 23:03:19.524810 DQS0 = 0, DQS1 = 0
1366 23:03:19.524892 DQM Delay:
1367 23:03:19.524956 DQM0 = 87, DQM1 = 77
1368 23:03:19.528037 DQ Delay:
1369 23:03:19.531470 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1370 23:03:19.531546 DQ4 =84, DQ5 =76, DQ6 =96, DQ7 =96
1371 23:03:19.534628 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1372 23:03:19.538042 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =88
1373 23:03:19.541471
1374 23:03:19.541567
1375 23:03:19.548311 [DQSOSCAuto] RK1, (LSB)MR18= 0x341e, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
1376 23:03:19.551594 CH0 RK1: MR19=606, MR18=341E
1377 23:03:19.558106 CH0_RK1: MR19=0x606, MR18=0x341E, DQSOSC=396, MR23=63, INC=94, DEC=62
1378 23:03:19.558206 [RxdqsGatingPostProcess] freq 800
1379 23:03:19.564990 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1380 23:03:19.568301 Pre-setting of DQS Precalculation
1381 23:03:19.571920 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1382 23:03:19.575270 ==
1383 23:03:19.578069 Dram Type= 6, Freq= 0, CH_1, rank 0
1384 23:03:19.581720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1385 23:03:19.581824 ==
1386 23:03:19.585141 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1387 23:03:19.591434 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1388 23:03:19.601445 [CA 0] Center 36 (7~66) winsize 60
1389 23:03:19.604683 [CA 1] Center 36 (6~66) winsize 61
1390 23:03:19.608329 [CA 2] Center 35 (5~65) winsize 61
1391 23:03:19.611757 [CA 3] Center 34 (3~65) winsize 63
1392 23:03:19.615181 [CA 4] Center 34 (4~65) winsize 62
1393 23:03:19.618538 [CA 5] Center 33 (3~64) winsize 62
1394 23:03:19.618630
1395 23:03:19.621382 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1396 23:03:19.621457
1397 23:03:19.624802 [CATrainingPosCal] consider 1 rank data
1398 23:03:19.628638 u2DelayCellTimex100 = 270/100 ps
1399 23:03:19.632157 CA0 delay=36 (7~66),Diff = 3 PI (21 cell)
1400 23:03:19.635120 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1401 23:03:19.638625 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1402 23:03:19.645057 CA3 delay=34 (3~65),Diff = 1 PI (7 cell)
1403 23:03:19.648432 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1404 23:03:19.652158 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1405 23:03:19.652247
1406 23:03:19.655159 CA PerBit enable=1, Macro0, CA PI delay=33
1407 23:03:19.655233
1408 23:03:19.658741 [CBTSetCACLKResult] CA Dly = 33
1409 23:03:19.658847 CS Dly: 4 (0~35)
1410 23:03:19.658931 ==
1411 23:03:19.661541 Dram Type= 6, Freq= 0, CH_1, rank 1
1412 23:03:19.668690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1413 23:03:19.668782 ==
1414 23:03:19.671866 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1415 23:03:19.678537 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1416 23:03:19.687523 [CA 0] Center 36 (6~66) winsize 61
1417 23:03:19.690964 [CA 1] Center 36 (6~66) winsize 61
1418 23:03:19.694060 [CA 2] Center 33 (3~64) winsize 62
1419 23:03:19.697505 [CA 3] Center 33 (3~64) winsize 62
1420 23:03:19.701045 [CA 4] Center 34 (4~65) winsize 62
1421 23:03:19.704713 [CA 5] Center 33 (3~64) winsize 62
1422 23:03:19.704805
1423 23:03:19.708514 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1424 23:03:19.708602
1425 23:03:19.711926 [CATrainingPosCal] consider 2 rank data
1426 23:03:19.716466 u2DelayCellTimex100 = 270/100 ps
1427 23:03:19.720028 CA0 delay=36 (7~66),Diff = 3 PI (21 cell)
1428 23:03:19.723104 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1429 23:03:19.727007 CA2 delay=34 (5~64),Diff = 1 PI (7 cell)
1430 23:03:19.731059 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1431 23:03:19.734281 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1432 23:03:19.738075 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1433 23:03:19.738187
1434 23:03:19.741566 CA PerBit enable=1, Macro0, CA PI delay=33
1435 23:03:19.741689
1436 23:03:19.744705 [CBTSetCACLKResult] CA Dly = 33
1437 23:03:19.744810 CS Dly: 5 (0~37)
1438 23:03:19.744911
1439 23:03:19.747824 ----->DramcWriteLeveling(PI) begin...
1440 23:03:19.747902 ==
1441 23:03:19.751269 Dram Type= 6, Freq= 0, CH_1, rank 0
1442 23:03:19.758222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1443 23:03:19.758309 ==
1444 23:03:19.761429 Write leveling (Byte 0): 29 => 29
1445 23:03:19.761507 Write leveling (Byte 1): 30 => 30
1446 23:03:19.764795 DramcWriteLeveling(PI) end<-----
1447 23:03:19.764873
1448 23:03:19.764936 ==
1449 23:03:19.768104 Dram Type= 6, Freq= 0, CH_1, rank 0
1450 23:03:19.774616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1451 23:03:19.774708 ==
1452 23:03:19.778414 [Gating] SW mode calibration
1453 23:03:19.784765 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1454 23:03:19.788240 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1455 23:03:19.791856 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1456 23:03:19.798369 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1457 23:03:19.801884 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 23:03:19.805026 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 23:03:19.812278 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 23:03:19.815144 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 23:03:19.818739 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 23:03:19.825392 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 23:03:19.828355 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 23:03:19.832119 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 23:03:19.838664 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 23:03:19.842444 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 23:03:19.845533 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 23:03:19.852021 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 23:03:19.855340 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 23:03:19.858975 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 23:03:19.862292 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 23:03:19.868997 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 23:03:19.872031 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1474 23:03:19.875492 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 23:03:19.882556 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 23:03:19.885607 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 23:03:19.889017 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 23:03:19.895811 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 23:03:19.898979 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 23:03:19.902187 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 23:03:19.909296 0 9 8 | B1->B0 | 2a2a 2525 | 1 1 | (1 1) (1 1)
1482 23:03:19.912564 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 23:03:19.916105 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 23:03:19.918845 0 9 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1485 23:03:19.925621 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1486 23:03:19.929231 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1487 23:03:19.932449 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1488 23:03:19.939142 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 0)
1489 23:03:19.942701 0 10 8 | B1->B0 | 2f2f 2f2f | 1 1 | (1 0) (1 0)
1490 23:03:19.946100 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 23:03:19.952520 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 23:03:19.956134 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 23:03:19.959498 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 23:03:19.966115 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 23:03:19.969407 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 23:03:19.972724 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 23:03:19.976103 0 11 8 | B1->B0 | 3131 3232 | 1 1 | (0 0) (0 0)
1498 23:03:19.983098 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 23:03:19.986107 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 23:03:19.989709 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 23:03:19.996386 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1502 23:03:19.999886 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1503 23:03:20.003121 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1504 23:03:20.009942 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1505 23:03:20.012924 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1506 23:03:20.016403 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 23:03:20.023143 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 23:03:20.026360 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 23:03:20.029947 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 23:03:20.036489 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 23:03:20.039653 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 23:03:20.043519 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 23:03:20.046926 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 23:03:20.053284 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 23:03:20.056569 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 23:03:20.059951 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 23:03:20.067034 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 23:03:20.070463 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 23:03:20.073945 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 23:03:20.080511 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1521 23:03:20.083449 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1522 23:03:20.086817 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1523 23:03:20.090352 Total UI for P1: 0, mck2ui 16
1524 23:03:20.093653 best dqsien dly found for B0: ( 0, 14, 8)
1525 23:03:20.096828 Total UI for P1: 0, mck2ui 16
1526 23:03:20.100130 best dqsien dly found for B1: ( 0, 14, 8)
1527 23:03:20.104088 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1528 23:03:20.106833 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1529 23:03:20.106934
1530 23:03:20.110382 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1531 23:03:20.113723 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1532 23:03:20.116962 [Gating] SW calibration Done
1533 23:03:20.117042 ==
1534 23:03:20.120421 Dram Type= 6, Freq= 0, CH_1, rank 0
1535 23:03:20.127587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1536 23:03:20.127671 ==
1537 23:03:20.127734 RX Vref Scan: 0
1538 23:03:20.127798
1539 23:03:20.130686 RX Vref 0 -> 0, step: 1
1540 23:03:20.130754
1541 23:03:20.133659 RX Delay -130 -> 252, step: 16
1542 23:03:20.136987 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1543 23:03:20.140455 iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224
1544 23:03:20.143643 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1545 23:03:20.147350 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1546 23:03:20.154035 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1547 23:03:20.157404 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1548 23:03:20.160476 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1549 23:03:20.163822 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1550 23:03:20.167015 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1551 23:03:20.173829 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1552 23:03:20.177042 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1553 23:03:20.180686 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1554 23:03:20.184048 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1555 23:03:20.187349 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1556 23:03:20.194132 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1557 23:03:20.197300 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1558 23:03:20.197388 ==
1559 23:03:20.200617 Dram Type= 6, Freq= 0, CH_1, rank 0
1560 23:03:20.203939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1561 23:03:20.204026 ==
1562 23:03:20.204092 DQS Delay:
1563 23:03:20.207451 DQS0 = 0, DQS1 = 0
1564 23:03:20.207525 DQM Delay:
1565 23:03:20.211127 DQM0 = 85, DQM1 = 77
1566 23:03:20.211202 DQ Delay:
1567 23:03:20.214556 DQ0 =85, DQ1 =77, DQ2 =77, DQ3 =85
1568 23:03:20.217770 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =85
1569 23:03:20.221253 DQ8 =61, DQ9 =69, DQ10 =77, DQ11 =69
1570 23:03:20.224679 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1571 23:03:20.224770
1572 23:03:20.224838
1573 23:03:20.224899 ==
1574 23:03:20.227450 Dram Type= 6, Freq= 0, CH_1, rank 0
1575 23:03:20.230731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1576 23:03:20.230840 ==
1577 23:03:20.234150
1578 23:03:20.234232
1579 23:03:20.234301 TX Vref Scan disable
1580 23:03:20.237654 == TX Byte 0 ==
1581 23:03:20.240805 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1582 23:03:20.244424 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1583 23:03:20.247634 == TX Byte 1 ==
1584 23:03:20.250951 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1585 23:03:20.254419 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1586 23:03:20.254508 ==
1587 23:03:20.257734 Dram Type= 6, Freq= 0, CH_1, rank 0
1588 23:03:20.264307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1589 23:03:20.264400 ==
1590 23:03:20.276085 TX Vref=22, minBit 1, minWin=27, winSum=442
1591 23:03:20.279240 TX Vref=24, minBit 1, minWin=27, winSum=444
1592 23:03:20.282774 TX Vref=26, minBit 0, minWin=28, winSum=450
1593 23:03:20.286809 TX Vref=28, minBit 15, minWin=27, winSum=450
1594 23:03:20.290095 TX Vref=30, minBit 0, minWin=27, winSum=448
1595 23:03:20.293659 TX Vref=32, minBit 11, minWin=27, winSum=450
1596 23:03:20.300122 [TxChooseVref] Worse bit 0, Min win 28, Win sum 450, Final Vref 26
1597 23:03:20.300234
1598 23:03:20.303596 Final TX Range 1 Vref 26
1599 23:03:20.303675
1600 23:03:20.303749 ==
1601 23:03:20.306782 Dram Type= 6, Freq= 0, CH_1, rank 0
1602 23:03:20.310457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1603 23:03:20.310538 ==
1604 23:03:20.310606
1605 23:03:20.310668
1606 23:03:20.313620 TX Vref Scan disable
1607 23:03:20.316873 == TX Byte 0 ==
1608 23:03:20.320170 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1609 23:03:20.323334 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1610 23:03:20.327116 == TX Byte 1 ==
1611 23:03:20.330642 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1612 23:03:20.333821 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1613 23:03:20.333897
1614 23:03:20.336923 [DATLAT]
1615 23:03:20.336996 Freq=800, CH1 RK0
1616 23:03:20.337058
1617 23:03:20.340525 DATLAT Default: 0xa
1618 23:03:20.340605 0, 0xFFFF, sum = 0
1619 23:03:20.343636 1, 0xFFFF, sum = 0
1620 23:03:20.343753 2, 0xFFFF, sum = 0
1621 23:03:20.347334 3, 0xFFFF, sum = 0
1622 23:03:20.347414 4, 0xFFFF, sum = 0
1623 23:03:20.350466 5, 0xFFFF, sum = 0
1624 23:03:20.350544 6, 0xFFFF, sum = 0
1625 23:03:20.354013 7, 0xFFFF, sum = 0
1626 23:03:20.354089 8, 0xFFFF, sum = 0
1627 23:03:20.357207 9, 0x0, sum = 1
1628 23:03:20.357286 10, 0x0, sum = 2
1629 23:03:20.360356 11, 0x0, sum = 3
1630 23:03:20.360431 12, 0x0, sum = 4
1631 23:03:20.360493 best_step = 10
1632 23:03:20.364029
1633 23:03:20.364128 ==
1634 23:03:20.366896 Dram Type= 6, Freq= 0, CH_1, rank 0
1635 23:03:20.370668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1636 23:03:20.370747 ==
1637 23:03:20.370811 RX Vref Scan: 1
1638 23:03:20.370882
1639 23:03:20.373800 Set Vref Range= 32 -> 127
1640 23:03:20.373876
1641 23:03:20.377324 RX Vref 32 -> 127, step: 1
1642 23:03:20.377405
1643 23:03:20.380326 RX Delay -111 -> 252, step: 8
1644 23:03:20.380413
1645 23:03:20.383669 Set Vref, RX VrefLevel [Byte0]: 32
1646 23:03:20.387207 [Byte1]: 32
1647 23:03:20.387312
1648 23:03:20.390408 Set Vref, RX VrefLevel [Byte0]: 33
1649 23:03:20.394220 [Byte1]: 33
1650 23:03:20.394301
1651 23:03:20.397304 Set Vref, RX VrefLevel [Byte0]: 34
1652 23:03:20.400395 [Byte1]: 34
1653 23:03:20.404061
1654 23:03:20.404146 Set Vref, RX VrefLevel [Byte0]: 35
1655 23:03:20.407717 [Byte1]: 35
1656 23:03:20.412094
1657 23:03:20.412177 Set Vref, RX VrefLevel [Byte0]: 36
1658 23:03:20.414976 [Byte1]: 36
1659 23:03:20.419316
1660 23:03:20.419410 Set Vref, RX VrefLevel [Byte0]: 37
1661 23:03:20.423065 [Byte1]: 37
1662 23:03:20.427306
1663 23:03:20.427392 Set Vref, RX VrefLevel [Byte0]: 38
1664 23:03:20.430364 [Byte1]: 38
1665 23:03:20.434791
1666 23:03:20.434908 Set Vref, RX VrefLevel [Byte0]: 39
1667 23:03:20.438182 [Byte1]: 39
1668 23:03:20.442314
1669 23:03:20.442408 Set Vref, RX VrefLevel [Byte0]: 40
1670 23:03:20.445785 [Byte1]: 40
1671 23:03:20.449860
1672 23:03:20.449979 Set Vref, RX VrefLevel [Byte0]: 41
1673 23:03:20.453104 [Byte1]: 41
1674 23:03:20.457463
1675 23:03:20.457551 Set Vref, RX VrefLevel [Byte0]: 42
1676 23:03:20.460904 [Byte1]: 42
1677 23:03:20.465408
1678 23:03:20.465495 Set Vref, RX VrefLevel [Byte0]: 43
1679 23:03:20.468737 [Byte1]: 43
1680 23:03:20.473154
1681 23:03:20.473243 Set Vref, RX VrefLevel [Byte0]: 44
1682 23:03:20.476382 [Byte1]: 44
1683 23:03:20.480714
1684 23:03:20.480803 Set Vref, RX VrefLevel [Byte0]: 45
1685 23:03:20.484014 [Byte1]: 45
1686 23:03:20.488455
1687 23:03:20.488543 Set Vref, RX VrefLevel [Byte0]: 46
1688 23:03:20.491809 [Byte1]: 46
1689 23:03:20.496138
1690 23:03:20.496227 Set Vref, RX VrefLevel [Byte0]: 47
1691 23:03:20.499476 [Byte1]: 47
1692 23:03:20.503379
1693 23:03:20.503467 Set Vref, RX VrefLevel [Byte0]: 48
1694 23:03:20.506832 [Byte1]: 48
1695 23:03:20.510963
1696 23:03:20.511052 Set Vref, RX VrefLevel [Byte0]: 49
1697 23:03:20.514613 [Byte1]: 49
1698 23:03:20.519210
1699 23:03:20.519334 Set Vref, RX VrefLevel [Byte0]: 50
1700 23:03:20.521952 [Byte1]: 50
1701 23:03:20.526301
1702 23:03:20.526391 Set Vref, RX VrefLevel [Byte0]: 51
1703 23:03:20.529789 [Byte1]: 51
1704 23:03:20.534756
1705 23:03:20.534890 Set Vref, RX VrefLevel [Byte0]: 52
1706 23:03:20.537606 [Byte1]: 52
1707 23:03:20.541728
1708 23:03:20.541841 Set Vref, RX VrefLevel [Byte0]: 53
1709 23:03:20.544973 [Byte1]: 53
1710 23:03:20.549425
1711 23:03:20.549548 Set Vref, RX VrefLevel [Byte0]: 54
1712 23:03:20.552564 [Byte1]: 54
1713 23:03:20.556996
1714 23:03:20.557086 Set Vref, RX VrefLevel [Byte0]: 55
1715 23:03:20.560754 [Byte1]: 55
1716 23:03:20.564872
1717 23:03:20.564959 Set Vref, RX VrefLevel [Byte0]: 56
1718 23:03:20.567943 [Byte1]: 56
1719 23:03:20.572335
1720 23:03:20.572454 Set Vref, RX VrefLevel [Byte0]: 57
1721 23:03:20.576032 [Byte1]: 57
1722 23:03:20.580296
1723 23:03:20.580382 Set Vref, RX VrefLevel [Byte0]: 58
1724 23:03:20.583409 [Byte1]: 58
1725 23:03:20.587544
1726 23:03:20.587635 Set Vref, RX VrefLevel [Byte0]: 59
1727 23:03:20.591135 [Byte1]: 59
1728 23:03:20.595208
1729 23:03:20.595307 Set Vref, RX VrefLevel [Byte0]: 60
1730 23:03:20.598418 [Byte1]: 60
1731 23:03:20.603574
1732 23:03:20.603671 Set Vref, RX VrefLevel [Byte0]: 61
1733 23:03:20.606844 [Byte1]: 61
1734 23:03:20.611342
1735 23:03:20.611442 Set Vref, RX VrefLevel [Byte0]: 62
1736 23:03:20.614062 [Byte1]: 62
1737 23:03:20.618253
1738 23:03:20.618348 Set Vref, RX VrefLevel [Byte0]: 63
1739 23:03:20.621721 [Byte1]: 63
1740 23:03:20.625797
1741 23:03:20.625887 Set Vref, RX VrefLevel [Byte0]: 64
1742 23:03:20.629090 [Byte1]: 64
1743 23:03:20.634077
1744 23:03:20.634170 Set Vref, RX VrefLevel [Byte0]: 65
1745 23:03:20.637458 [Byte1]: 65
1746 23:03:20.641141
1747 23:03:20.641236 Set Vref, RX VrefLevel [Byte0]: 66
1748 23:03:20.644421 [Byte1]: 66
1749 23:03:20.648880
1750 23:03:20.648973 Set Vref, RX VrefLevel [Byte0]: 67
1751 23:03:20.652302 [Byte1]: 67
1752 23:03:20.656549
1753 23:03:20.656644 Set Vref, RX VrefLevel [Byte0]: 68
1754 23:03:20.660036 [Byte1]: 68
1755 23:03:20.664333
1756 23:03:20.664442 Set Vref, RX VrefLevel [Byte0]: 69
1757 23:03:20.667497 [Byte1]: 69
1758 23:03:20.671873
1759 23:03:20.671958 Set Vref, RX VrefLevel [Byte0]: 70
1760 23:03:20.675401 [Byte1]: 70
1761 23:03:20.679645
1762 23:03:20.679721 Set Vref, RX VrefLevel [Byte0]: 71
1763 23:03:20.682947 [Byte1]: 71
1764 23:03:20.687126
1765 23:03:20.687200 Set Vref, RX VrefLevel [Byte0]: 72
1766 23:03:20.690647 [Byte1]: 72
1767 23:03:20.694761
1768 23:03:20.694835 Set Vref, RX VrefLevel [Byte0]: 73
1769 23:03:20.697822 [Byte1]: 73
1770 23:03:20.702647
1771 23:03:20.702728 Set Vref, RX VrefLevel [Byte0]: 74
1772 23:03:20.705973 [Byte1]: 74
1773 23:03:20.710221
1774 23:03:20.710299 Set Vref, RX VrefLevel [Byte0]: 75
1775 23:03:20.713451 [Byte1]: 75
1776 23:03:20.717568
1777 23:03:20.717661 Set Vref, RX VrefLevel [Byte0]: 76
1778 23:03:20.724141 [Byte1]: 76
1779 23:03:20.724225
1780 23:03:20.727594 Set Vref, RX VrefLevel [Byte0]: 77
1781 23:03:20.731428 [Byte1]: 77
1782 23:03:20.731519
1783 23:03:20.734463 Set Vref, RX VrefLevel [Byte0]: 78
1784 23:03:20.737561 [Byte1]: 78
1785 23:03:20.737647
1786 23:03:20.741071 Final RX Vref Byte 0 = 56 to rank0
1787 23:03:20.744512 Final RX Vref Byte 1 = 57 to rank0
1788 23:03:20.748081 Final RX Vref Byte 0 = 56 to rank1
1789 23:03:20.751226 Final RX Vref Byte 1 = 57 to rank1==
1790 23:03:20.754351 Dram Type= 6, Freq= 0, CH_1, rank 0
1791 23:03:20.758089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1792 23:03:20.758187 ==
1793 23:03:20.761123 DQS Delay:
1794 23:03:20.761199 DQS0 = 0, DQS1 = 0
1795 23:03:20.764938 DQM Delay:
1796 23:03:20.765021 DQM0 = 83, DQM1 = 74
1797 23:03:20.765086 DQ Delay:
1798 23:03:20.767837 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =84
1799 23:03:20.771715 DQ4 =84, DQ5 =92, DQ6 =96, DQ7 =76
1800 23:03:20.774872 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =68
1801 23:03:20.778026 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =76
1802 23:03:20.778109
1803 23:03:20.778188
1804 23:03:20.788470 [DQSOSCAuto] RK0, (LSB)MR18= 0x26fb, (MSB)MR19= 0x605, tDQSOscB0 = 411 ps tDQSOscB1 = 400 ps
1805 23:03:20.791789 CH1 RK0: MR19=605, MR18=26FB
1806 23:03:20.794755 CH1_RK0: MR19=0x605, MR18=0x26FB, DQSOSC=400, MR23=63, INC=92, DEC=61
1807 23:03:20.794878
1808 23:03:20.798507 ----->DramcWriteLeveling(PI) begin...
1809 23:03:20.801623 ==
1810 23:03:20.801706 Dram Type= 6, Freq= 0, CH_1, rank 1
1811 23:03:20.808076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1812 23:03:20.808177 ==
1813 23:03:20.811893 Write leveling (Byte 0): 30 => 30
1814 23:03:20.815105 Write leveling (Byte 1): 30 => 30
1815 23:03:20.815210 DramcWriteLeveling(PI) end<-----
1816 23:03:20.818474
1817 23:03:20.818570 ==
1818 23:03:20.821951 Dram Type= 6, Freq= 0, CH_1, rank 1
1819 23:03:20.824889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1820 23:03:20.824966 ==
1821 23:03:20.828631 [Gating] SW mode calibration
1822 23:03:20.835350 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1823 23:03:20.838825 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1824 23:03:20.845618 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1825 23:03:20.848804 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1826 23:03:20.852345 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1827 23:03:20.859240 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 23:03:20.861956 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 23:03:20.865507 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 23:03:20.871880 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 23:03:20.875581 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 23:03:20.878649 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 23:03:20.882382 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 23:03:20.889295 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 23:03:20.892529 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 23:03:20.895726 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 23:03:20.902419 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 23:03:20.905661 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 23:03:20.909309 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 23:03:20.915670 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 23:03:20.919113 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1842 23:03:20.923084 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1843 23:03:20.929224 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 23:03:20.932469 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 23:03:20.935975 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 23:03:20.939159 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 23:03:20.946085 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 23:03:20.949547 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 23:03:20.952510 0 9 4 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
1850 23:03:20.959370 0 9 8 | B1->B0 | 2929 3434 | 1 1 | (1 1) (1 1)
1851 23:03:20.962807 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1852 23:03:20.966461 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1853 23:03:20.972734 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1854 23:03:20.976498 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1855 23:03:20.979703 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1856 23:03:20.986321 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1857 23:03:20.989412 0 10 4 | B1->B0 | 3030 2f2f | 1 1 | (1 1) (1 0)
1858 23:03:20.992603 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 23:03:20.996158 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 23:03:21.002916 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 23:03:21.006201 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 23:03:21.009624 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 23:03:21.016302 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 23:03:21.019649 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 23:03:21.022876 0 11 4 | B1->B0 | 2b2b 3434 | 0 0 | (0 0) (0 0)
1866 23:03:21.029940 0 11 8 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
1867 23:03:21.032837 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1868 23:03:21.036131 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1869 23:03:21.043127 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1870 23:03:21.046718 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1871 23:03:21.050133 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1872 23:03:21.056517 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1873 23:03:21.059823 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1874 23:03:21.063434 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1875 23:03:21.066640 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 23:03:21.073336 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 23:03:21.076584 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 23:03:21.080227 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 23:03:21.086989 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 23:03:21.089831 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 23:03:21.093398 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 23:03:21.100094 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 23:03:21.103609 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1884 23:03:21.106771 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1885 23:03:21.113847 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1886 23:03:21.116871 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1887 23:03:21.119943 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1888 23:03:21.126713 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1889 23:03:21.130095 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1890 23:03:21.133326 Total UI for P1: 0, mck2ui 16
1891 23:03:21.136893 best dqsien dly found for B0: ( 0, 14, 2)
1892 23:03:21.140450 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1893 23:03:21.143451 Total UI for P1: 0, mck2ui 16
1894 23:03:21.146933 best dqsien dly found for B1: ( 0, 14, 4)
1895 23:03:21.150457 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1896 23:03:21.154381 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1897 23:03:21.154457
1898 23:03:21.157219 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1899 23:03:21.160682 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1900 23:03:21.163978 [Gating] SW calibration Done
1901 23:03:21.164066 ==
1902 23:03:21.166881 Dram Type= 6, Freq= 0, CH_1, rank 1
1903 23:03:21.170784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1904 23:03:21.173729 ==
1905 23:03:21.173812 RX Vref Scan: 0
1906 23:03:21.173878
1907 23:03:21.177034 RX Vref 0 -> 0, step: 1
1908 23:03:21.177116
1909 23:03:21.180537 RX Delay -130 -> 252, step: 16
1910 23:03:21.183852 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1911 23:03:21.187015 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1912 23:03:21.190403 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1913 23:03:21.194344 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1914 23:03:21.197250 iDelay=206, Bit 4, Center 77 (-50 ~ 205) 256
1915 23:03:21.204079 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1916 23:03:21.207078 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1917 23:03:21.210688 iDelay=206, Bit 7, Center 69 (-50 ~ 189) 240
1918 23:03:21.213850 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1919 23:03:21.217918 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1920 23:03:21.224144 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1921 23:03:21.227580 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1922 23:03:21.230711 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1923 23:03:21.234340 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1924 23:03:21.238299 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1925 23:03:21.244327 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1926 23:03:21.244429 ==
1927 23:03:21.248138 Dram Type= 6, Freq= 0, CH_1, rank 1
1928 23:03:21.251121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1929 23:03:21.251205 ==
1930 23:03:21.251271 DQS Delay:
1931 23:03:21.254567 DQS0 = 0, DQS1 = 0
1932 23:03:21.254658 DQM Delay:
1933 23:03:21.257733 DQM0 = 80, DQM1 = 76
1934 23:03:21.257842 DQ Delay:
1935 23:03:21.261414 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1936 23:03:21.264454 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =69
1937 23:03:21.267762 DQ8 =61, DQ9 =69, DQ10 =69, DQ11 =69
1938 23:03:21.271110 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1939 23:03:21.271221
1940 23:03:21.271289
1941 23:03:21.271350 ==
1942 23:03:21.274308 Dram Type= 6, Freq= 0, CH_1, rank 1
1943 23:03:21.277693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1944 23:03:21.277777 ==
1945 23:03:21.277843
1946 23:03:21.277904
1947 23:03:21.281310 TX Vref Scan disable
1948 23:03:21.284470 == TX Byte 0 ==
1949 23:03:21.287778 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1950 23:03:21.291032 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1951 23:03:21.294491 == TX Byte 1 ==
1952 23:03:21.297939 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1953 23:03:21.301381 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1954 23:03:21.301465 ==
1955 23:03:21.304469 Dram Type= 6, Freq= 0, CH_1, rank 1
1956 23:03:21.307896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1957 23:03:21.311852 ==
1958 23:03:21.322595 TX Vref=22, minBit 3, minWin=27, winSum=441
1959 23:03:21.325531 TX Vref=24, minBit 2, minWin=27, winSum=446
1960 23:03:21.328997 TX Vref=26, minBit 0, minWin=27, winSum=445
1961 23:03:21.332409 TX Vref=28, minBit 3, minWin=27, winSum=449
1962 23:03:21.335827 TX Vref=30, minBit 7, minWin=27, winSum=452
1963 23:03:21.339389 TX Vref=32, minBit 0, minWin=27, winSum=452
1964 23:03:21.345834 [TxChooseVref] Worse bit 7, Min win 27, Win sum 452, Final Vref 30
1965 23:03:21.345954
1966 23:03:21.349354 Final TX Range 1 Vref 30
1967 23:03:21.349439
1968 23:03:21.349504 ==
1969 23:03:21.352646 Dram Type= 6, Freq= 0, CH_1, rank 1
1970 23:03:21.355889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1971 23:03:21.355967 ==
1972 23:03:21.356060
1973 23:03:21.356148
1974 23:03:21.359599 TX Vref Scan disable
1975 23:03:21.362681 == TX Byte 0 ==
1976 23:03:21.365946 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1977 23:03:21.369537 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1978 23:03:21.372945 == TX Byte 1 ==
1979 23:03:21.376245 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1980 23:03:21.379323 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1981 23:03:21.379434
1982 23:03:21.382813 [DATLAT]
1983 23:03:21.382908 Freq=800, CH1 RK1
1984 23:03:21.382972
1985 23:03:21.385867 DATLAT Default: 0xa
1986 23:03:21.385936 0, 0xFFFF, sum = 0
1987 23:03:21.389339 1, 0xFFFF, sum = 0
1988 23:03:21.389411 2, 0xFFFF, sum = 0
1989 23:03:21.392890 3, 0xFFFF, sum = 0
1990 23:03:21.392966 4, 0xFFFF, sum = 0
1991 23:03:21.396243 5, 0xFFFF, sum = 0
1992 23:03:21.396324 6, 0xFFFF, sum = 0
1993 23:03:21.399524 7, 0xFFFF, sum = 0
1994 23:03:21.399601 8, 0xFFFF, sum = 0
1995 23:03:21.402708 9, 0x0, sum = 1
1996 23:03:21.402815 10, 0x0, sum = 2
1997 23:03:21.406341 11, 0x0, sum = 3
1998 23:03:21.406456 12, 0x0, sum = 4
1999 23:03:21.409640 best_step = 10
2000 23:03:21.409736
2001 23:03:21.409824 ==
2002 23:03:21.412989 Dram Type= 6, Freq= 0, CH_1, rank 1
2003 23:03:21.416273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2004 23:03:21.416347 ==
2005 23:03:21.416413 RX Vref Scan: 0
2006 23:03:21.416473
2007 23:03:21.420159 RX Vref 0 -> 0, step: 1
2008 23:03:21.420277
2009 23:03:21.423370 RX Delay -111 -> 252, step: 8
2010 23:03:21.426833 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
2011 23:03:21.433727 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2012 23:03:21.436875 iDelay=209, Bit 2, Center 68 (-47 ~ 184) 232
2013 23:03:21.439998 iDelay=209, Bit 3, Center 76 (-39 ~ 192) 232
2014 23:03:21.443382 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
2015 23:03:21.446974 iDelay=209, Bit 5, Center 92 (-23 ~ 208) 232
2016 23:03:21.450272 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2017 23:03:21.457202 iDelay=209, Bit 7, Center 76 (-39 ~ 192) 232
2018 23:03:21.460198 iDelay=209, Bit 8, Center 68 (-47 ~ 184) 232
2019 23:03:21.463341 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
2020 23:03:21.467062 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
2021 23:03:21.470429 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
2022 23:03:21.476989 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
2023 23:03:21.480424 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
2024 23:03:21.483371 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
2025 23:03:21.486950 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
2026 23:03:21.487048 ==
2027 23:03:21.490482 Dram Type= 6, Freq= 0, CH_1, rank 1
2028 23:03:21.496976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2029 23:03:21.497057 ==
2030 23:03:21.497120 DQS Delay:
2031 23:03:21.497179 DQS0 = 0, DQS1 = 0
2032 23:03:21.500223 DQM Delay:
2033 23:03:21.500298 DQM0 = 80, DQM1 = 76
2034 23:03:21.503585 DQ Delay:
2035 23:03:21.507182 DQ0 =84, DQ1 =72, DQ2 =68, DQ3 =76
2036 23:03:21.507259 DQ4 =84, DQ5 =92, DQ6 =92, DQ7 =76
2037 23:03:21.510174 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
2038 23:03:21.513803 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84
2039 23:03:21.517302
2040 23:03:21.517401
2041 23:03:21.523533 [DQSOSCAuto] RK1, (LSB)MR18= 0x1c28, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 402 ps
2042 23:03:21.527372 CH1 RK1: MR19=606, MR18=1C28
2043 23:03:21.534060 CH1_RK1: MR19=0x606, MR18=0x1C28, DQSOSC=399, MR23=63, INC=92, DEC=61
2044 23:03:21.534211 [RxdqsGatingPostProcess] freq 800
2045 23:03:21.540893 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2046 23:03:21.543900 Pre-setting of DQS Precalculation
2047 23:03:21.547358 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2048 23:03:21.557339 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2049 23:03:21.564364 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2050 23:03:21.564514
2051 23:03:21.564608
2052 23:03:21.567921 [Calibration Summary] 1600 Mbps
2053 23:03:21.568034 CH 0, Rank 0
2054 23:03:21.571183 SW Impedance : PASS
2055 23:03:21.571277 DUTY Scan : NO K
2056 23:03:21.574666 ZQ Calibration : PASS
2057 23:03:21.577684 Jitter Meter : NO K
2058 23:03:21.577817 CBT Training : PASS
2059 23:03:21.581047 Write leveling : PASS
2060 23:03:21.584474 RX DQS gating : PASS
2061 23:03:21.584576 RX DQ/DQS(RDDQC) : PASS
2062 23:03:21.588108 TX DQ/DQS : PASS
2063 23:03:21.590814 RX DATLAT : PASS
2064 23:03:21.590934 RX DQ/DQS(Engine): PASS
2065 23:03:21.594610 TX OE : NO K
2066 23:03:21.594709 All Pass.
2067 23:03:21.594797
2068 23:03:21.594918 CH 0, Rank 1
2069 23:03:21.597530 SW Impedance : PASS
2070 23:03:21.601074 DUTY Scan : NO K
2071 23:03:21.601162 ZQ Calibration : PASS
2072 23:03:21.604338 Jitter Meter : NO K
2073 23:03:21.608019 CBT Training : PASS
2074 23:03:21.608096 Write leveling : PASS
2075 23:03:21.611628 RX DQS gating : PASS
2076 23:03:21.614449 RX DQ/DQS(RDDQC) : PASS
2077 23:03:21.614525 TX DQ/DQS : PASS
2078 23:03:21.617915 RX DATLAT : PASS
2079 23:03:21.621246 RX DQ/DQS(Engine): PASS
2080 23:03:21.621319 TX OE : NO K
2081 23:03:21.621381 All Pass.
2082 23:03:21.621439
2083 23:03:21.624787 CH 1, Rank 0
2084 23:03:21.624861 SW Impedance : PASS
2085 23:03:21.628179 DUTY Scan : NO K
2086 23:03:21.631551 ZQ Calibration : PASS
2087 23:03:21.631625 Jitter Meter : NO K
2088 23:03:21.634791 CBT Training : PASS
2089 23:03:21.638320 Write leveling : PASS
2090 23:03:21.638394 RX DQS gating : PASS
2091 23:03:21.641732 RX DQ/DQS(RDDQC) : PASS
2092 23:03:21.645331 TX DQ/DQS : PASS
2093 23:03:21.645447 RX DATLAT : PASS
2094 23:03:21.648611 RX DQ/DQS(Engine): PASS
2095 23:03:21.648722 TX OE : NO K
2096 23:03:21.652570 All Pass.
2097 23:03:21.652649
2098 23:03:21.652711 CH 1, Rank 1
2099 23:03:21.655484 SW Impedance : PASS
2100 23:03:21.655555 DUTY Scan : NO K
2101 23:03:21.658819 ZQ Calibration : PASS
2102 23:03:21.662169 Jitter Meter : NO K
2103 23:03:21.662246 CBT Training : PASS
2104 23:03:21.665356 Write leveling : PASS
2105 23:03:21.669200 RX DQS gating : PASS
2106 23:03:21.669301 RX DQ/DQS(RDDQC) : PASS
2107 23:03:21.672459 TX DQ/DQS : PASS
2108 23:03:21.675452 RX DATLAT : PASS
2109 23:03:21.675552 RX DQ/DQS(Engine): PASS
2110 23:03:21.678871 TX OE : NO K
2111 23:03:21.678963 All Pass.
2112 23:03:21.679053
2113 23:03:21.681858 DramC Write-DBI off
2114 23:03:21.685649 PER_BANK_REFRESH: Hybrid Mode
2115 23:03:21.685904 TX_TRACKING: ON
2116 23:03:21.688752 [GetDramInforAfterCalByMRR] Vendor 6.
2117 23:03:21.692320 [GetDramInforAfterCalByMRR] Revision 606.
2118 23:03:21.695373 [GetDramInforAfterCalByMRR] Revision 2 0.
2119 23:03:21.698931 MR0 0x3b3b
2120 23:03:21.699030 MR8 0x5151
2121 23:03:21.702512 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2122 23:03:21.702629
2123 23:03:21.702738 MR0 0x3b3b
2124 23:03:21.705746 MR8 0x5151
2125 23:03:21.709323 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2126 23:03:21.709433
2127 23:03:21.715540 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2128 23:03:21.719184 [FAST_K] Save calibration result to emmc
2129 23:03:21.722567 [FAST_K] Save calibration result to emmc
2130 23:03:21.726085 dram_init: config_dvfs: 1
2131 23:03:21.729361 dramc_set_vcore_voltage set vcore to 662500
2132 23:03:21.732392 Read voltage for 1200, 2
2133 23:03:21.732497 Vio18 = 0
2134 23:03:21.736018 Vcore = 662500
2135 23:03:21.736102 Vdram = 0
2136 23:03:21.736165 Vddq = 0
2137 23:03:21.739180 Vmddr = 0
2138 23:03:21.742516 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2139 23:03:21.749015 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2140 23:03:21.749138 MEM_TYPE=3, freq_sel=15
2141 23:03:21.752376 sv_algorithm_assistance_LP4_1600
2142 23:03:21.755859 ============ PULL DRAM RESETB DOWN ============
2143 23:03:21.762332 ========== PULL DRAM RESETB DOWN end =========
2144 23:03:21.766209 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2145 23:03:21.769051 ===================================
2146 23:03:21.772360 LPDDR4 DRAM CONFIGURATION
2147 23:03:21.776106 ===================================
2148 23:03:21.776211 EX_ROW_EN[0] = 0x0
2149 23:03:21.779370 EX_ROW_EN[1] = 0x0
2150 23:03:21.779452 LP4Y_EN = 0x0
2151 23:03:21.782503 WORK_FSP = 0x0
2152 23:03:21.782579 WL = 0x4
2153 23:03:21.786225 RL = 0x4
2154 23:03:21.786300 BL = 0x2
2155 23:03:21.789380 RPST = 0x0
2156 23:03:21.792468 RD_PRE = 0x0
2157 23:03:21.792547 WR_PRE = 0x1
2158 23:03:21.796132 WR_PST = 0x0
2159 23:03:21.796208 DBI_WR = 0x0
2160 23:03:21.799367 DBI_RD = 0x0
2161 23:03:21.799440 OTF = 0x1
2162 23:03:21.802994 ===================================
2163 23:03:21.806195 ===================================
2164 23:03:21.806299 ANA top config
2165 23:03:21.809621 ===================================
2166 23:03:21.812768 DLL_ASYNC_EN = 0
2167 23:03:21.816580 ALL_SLAVE_EN = 0
2168 23:03:21.819705 NEW_RANK_MODE = 1
2169 23:03:21.819819 DLL_IDLE_MODE = 1
2170 23:03:21.822977 LP45_APHY_COMB_EN = 1
2171 23:03:21.826337 TX_ODT_DIS = 1
2172 23:03:21.829697 NEW_8X_MODE = 1
2173 23:03:21.832794 ===================================
2174 23:03:21.836510 ===================================
2175 23:03:21.839601 data_rate = 2400
2176 23:03:21.839683 CKR = 1
2177 23:03:21.843419 DQ_P2S_RATIO = 8
2178 23:03:21.846630 ===================================
2179 23:03:21.850060 CA_P2S_RATIO = 8
2180 23:03:21.853160 DQ_CA_OPEN = 0
2181 23:03:21.856337 DQ_SEMI_OPEN = 0
2182 23:03:21.859790 CA_SEMI_OPEN = 0
2183 23:03:21.859891 CA_FULL_RATE = 0
2184 23:03:21.863265 DQ_CKDIV4_EN = 0
2185 23:03:21.866480 CA_CKDIV4_EN = 0
2186 23:03:21.869993 CA_PREDIV_EN = 0
2187 23:03:21.873334 PH8_DLY = 17
2188 23:03:21.873442 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2189 23:03:21.876850 DQ_AAMCK_DIV = 4
2190 23:03:21.880479 CA_AAMCK_DIV = 4
2191 23:03:21.883584 CA_ADMCK_DIV = 4
2192 23:03:21.886777 DQ_TRACK_CA_EN = 0
2193 23:03:21.889993 CA_PICK = 1200
2194 23:03:21.893698 CA_MCKIO = 1200
2195 23:03:21.893808 MCKIO_SEMI = 0
2196 23:03:21.897201 PLL_FREQ = 2366
2197 23:03:21.900136 DQ_UI_PI_RATIO = 32
2198 23:03:21.903673 CA_UI_PI_RATIO = 0
2199 23:03:21.907148 ===================================
2200 23:03:21.910550 ===================================
2201 23:03:21.913557 memory_type:LPDDR4
2202 23:03:21.913664 GP_NUM : 10
2203 23:03:21.917000 SRAM_EN : 1
2204 23:03:21.917088 MD32_EN : 0
2205 23:03:21.920341 ===================================
2206 23:03:21.924157 [ANA_INIT] >>>>>>>>>>>>>>
2207 23:03:21.927481 <<<<<< [CONFIGURE PHASE]: ANA_TX
2208 23:03:21.930509 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2209 23:03:21.934369 ===================================
2210 23:03:21.937489 data_rate = 2400,PCW = 0X5b00
2211 23:03:21.940556 ===================================
2212 23:03:21.943698 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2213 23:03:21.947643 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2214 23:03:21.954259 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2215 23:03:21.957692 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2216 23:03:21.960900 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2217 23:03:21.964462 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2218 23:03:21.967604 [ANA_INIT] flow start
2219 23:03:21.970634 [ANA_INIT] PLL >>>>>>>>
2220 23:03:21.970743 [ANA_INIT] PLL <<<<<<<<
2221 23:03:21.974020 [ANA_INIT] MIDPI >>>>>>>>
2222 23:03:21.977825 [ANA_INIT] MIDPI <<<<<<<<
2223 23:03:21.980966 [ANA_INIT] DLL >>>>>>>>
2224 23:03:21.981065 [ANA_INIT] DLL <<<<<<<<
2225 23:03:21.984709 [ANA_INIT] flow end
2226 23:03:21.987472 ============ LP4 DIFF to SE enter ============
2227 23:03:21.990655 ============ LP4 DIFF to SE exit ============
2228 23:03:21.994173 [ANA_INIT] <<<<<<<<<<<<<
2229 23:03:21.998069 [Flow] Enable top DCM control >>>>>
2230 23:03:22.000678 [Flow] Enable top DCM control <<<<<
2231 23:03:22.004459 Enable DLL master slave shuffle
2232 23:03:22.008112 ==============================================================
2233 23:03:22.011146 Gating Mode config
2234 23:03:22.017534 ==============================================================
2235 23:03:22.017636 Config description:
2236 23:03:22.027759 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2237 23:03:22.034605 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2238 23:03:22.037786 SELPH_MODE 0: By rank 1: By Phase
2239 23:03:22.044436 ==============================================================
2240 23:03:22.047950 GAT_TRACK_EN = 1
2241 23:03:22.051304 RX_GATING_MODE = 2
2242 23:03:22.054578 RX_GATING_TRACK_MODE = 2
2243 23:03:22.058150 SELPH_MODE = 1
2244 23:03:22.061468 PICG_EARLY_EN = 1
2245 23:03:22.064934 VALID_LAT_VALUE = 1
2246 23:03:22.067830 ==============================================================
2247 23:03:22.071225 Enter into Gating configuration >>>>
2248 23:03:22.074660 Exit from Gating configuration <<<<
2249 23:03:22.078178 Enter into DVFS_PRE_config >>>>>
2250 23:03:22.088281 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2251 23:03:22.091309 Exit from DVFS_PRE_config <<<<<
2252 23:03:22.094737 Enter into PICG configuration >>>>
2253 23:03:22.098342 Exit from PICG configuration <<<<
2254 23:03:22.101620 [RX_INPUT] configuration >>>>>
2255 23:03:22.104553 [RX_INPUT] configuration <<<<<
2256 23:03:22.108253 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2257 23:03:22.114949 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2258 23:03:22.121786 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2259 23:03:22.128291 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2260 23:03:22.134766 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2261 23:03:22.138365 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2262 23:03:22.145008 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2263 23:03:22.148221 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2264 23:03:22.151827 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2265 23:03:22.155052 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2266 23:03:22.158388 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2267 23:03:22.165186 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2268 23:03:22.168324 ===================================
2269 23:03:22.168401 LPDDR4 DRAM CONFIGURATION
2270 23:03:22.171790 ===================================
2271 23:03:22.175165 EX_ROW_EN[0] = 0x0
2272 23:03:22.178723 EX_ROW_EN[1] = 0x0
2273 23:03:22.178821 LP4Y_EN = 0x0
2274 23:03:22.182239 WORK_FSP = 0x0
2275 23:03:22.182310 WL = 0x4
2276 23:03:22.185776 RL = 0x4
2277 23:03:22.185854 BL = 0x2
2278 23:03:22.188828 RPST = 0x0
2279 23:03:22.188910 RD_PRE = 0x0
2280 23:03:22.192544 WR_PRE = 0x1
2281 23:03:22.192613 WR_PST = 0x0
2282 23:03:22.195291 DBI_WR = 0x0
2283 23:03:22.195387 DBI_RD = 0x0
2284 23:03:22.198878 OTF = 0x1
2285 23:03:22.202242 ===================================
2286 23:03:22.205510 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2287 23:03:22.208934 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2288 23:03:22.212825 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2289 23:03:22.216226 ===================================
2290 23:03:22.219161 LPDDR4 DRAM CONFIGURATION
2291 23:03:22.222789 ===================================
2292 23:03:22.226193 EX_ROW_EN[0] = 0x10
2293 23:03:22.226293 EX_ROW_EN[1] = 0x0
2294 23:03:22.229079 LP4Y_EN = 0x0
2295 23:03:22.229174 WORK_FSP = 0x0
2296 23:03:22.232601 WL = 0x4
2297 23:03:22.232696 RL = 0x4
2298 23:03:22.235928 BL = 0x2
2299 23:03:22.236024 RPST = 0x0
2300 23:03:22.239395 RD_PRE = 0x0
2301 23:03:22.239490 WR_PRE = 0x1
2302 23:03:22.242853 WR_PST = 0x0
2303 23:03:22.242970 DBI_WR = 0x0
2304 23:03:22.245976 DBI_RD = 0x0
2305 23:03:22.246132 OTF = 0x1
2306 23:03:22.249433 ===================================
2307 23:03:22.256249 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2308 23:03:22.256352 ==
2309 23:03:22.259259 Dram Type= 6, Freq= 0, CH_0, rank 0
2310 23:03:22.266213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2311 23:03:22.266314 ==
2312 23:03:22.266408 [Duty_Offset_Calibration]
2313 23:03:22.269377 B0:2 B1:-1 CA:1
2314 23:03:22.269471
2315 23:03:22.272688 [DutyScan_Calibration_Flow] k_type=0
2316 23:03:22.281090
2317 23:03:22.281165 ==CLK 0==
2318 23:03:22.284035 Final CLK duty delay cell = -4
2319 23:03:22.288040 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2320 23:03:22.291365 [-4] MIN Duty = 4875%(X100), DQS PI = 30
2321 23:03:22.294794 [-4] AVG Duty = 4953%(X100)
2322 23:03:22.294909
2323 23:03:22.297733 CH0 CLK Duty spec in!! Max-Min= 156%
2324 23:03:22.301496 [DutyScan_Calibration_Flow] ====Done====
2325 23:03:22.301565
2326 23:03:22.304213 [DutyScan_Calibration_Flow] k_type=1
2327 23:03:22.318746
2328 23:03:22.318869 ==DQS 0 ==
2329 23:03:22.322535 Final DQS duty delay cell = -4
2330 23:03:22.325565 [-4] MAX Duty = 5031%(X100), DQS PI = 54
2331 23:03:22.329304 [-4] MIN Duty = 4876%(X100), DQS PI = 12
2332 23:03:22.332816 [-4] AVG Duty = 4953%(X100)
2333 23:03:22.332889
2334 23:03:22.332950 ==DQS 1 ==
2335 23:03:22.336013 Final DQS duty delay cell = -4
2336 23:03:22.339246 [-4] MAX Duty = 5124%(X100), DQS PI = 6
2337 23:03:22.342451 [-4] MIN Duty = 5000%(X100), DQS PI = 50
2338 23:03:22.345991 [-4] AVG Duty = 5062%(X100)
2339 23:03:22.346118
2340 23:03:22.349394 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2341 23:03:22.349466
2342 23:03:22.352532 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2343 23:03:22.356077 [DutyScan_Calibration_Flow] ====Done====
2344 23:03:22.356174
2345 23:03:22.358947 [DutyScan_Calibration_Flow] k_type=3
2346 23:03:22.376115
2347 23:03:22.376190 ==DQM 0 ==
2348 23:03:22.379332 Final DQM duty delay cell = 0
2349 23:03:22.382870 [0] MAX Duty = 5000%(X100), DQS PI = 46
2350 23:03:22.386049 [0] MIN Duty = 4907%(X100), DQS PI = 2
2351 23:03:22.386121 [0] AVG Duty = 4953%(X100)
2352 23:03:22.386182
2353 23:03:22.389436 ==DQM 1 ==
2354 23:03:22.392816 Final DQM duty delay cell = 0
2355 23:03:22.396359 [0] MAX Duty = 5156%(X100), DQS PI = 62
2356 23:03:22.399905 [0] MIN Duty = 4969%(X100), DQS PI = 10
2357 23:03:22.399974 [0] AVG Duty = 5062%(X100)
2358 23:03:22.400033
2359 23:03:22.403415 CH0 DQM 0 Duty spec in!! Max-Min= 93%
2360 23:03:22.406255
2361 23:03:22.409687 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2362 23:03:22.413155 [DutyScan_Calibration_Flow] ====Done====
2363 23:03:22.413250
2364 23:03:22.416692 [DutyScan_Calibration_Flow] k_type=2
2365 23:03:22.431911
2366 23:03:22.431992 ==DQ 0 ==
2367 23:03:22.434956 Final DQ duty delay cell = -4
2368 23:03:22.438667 [-4] MAX Duty = 5062%(X100), DQS PI = 54
2369 23:03:22.442195 [-4] MIN Duty = 4876%(X100), DQS PI = 16
2370 23:03:22.445472 [-4] AVG Duty = 4969%(X100)
2371 23:03:22.445547
2372 23:03:22.445609 ==DQ 1 ==
2373 23:03:22.448473 Final DQ duty delay cell = 0
2374 23:03:22.451893 [0] MAX Duty = 5031%(X100), DQS PI = 18
2375 23:03:22.455332 [0] MIN Duty = 4907%(X100), DQS PI = 46
2376 23:03:22.455408 [0] AVG Duty = 4969%(X100)
2377 23:03:22.458733
2378 23:03:22.461845 CH0 DQ 0 Duty spec in!! Max-Min= 186%
2379 23:03:22.461942
2380 23:03:22.465691 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2381 23:03:22.469335 [DutyScan_Calibration_Flow] ====Done====
2382 23:03:22.469407 ==
2383 23:03:22.472560 Dram Type= 6, Freq= 0, CH_1, rank 0
2384 23:03:22.475666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2385 23:03:22.475775 ==
2386 23:03:22.478658 [Duty_Offset_Calibration]
2387 23:03:22.478752 B0:1 B1:1 CA:2
2388 23:03:22.478841
2389 23:03:22.482351 [DutyScan_Calibration_Flow] k_type=0
2390 23:03:22.492469
2391 23:03:22.492545 ==CLK 0==
2392 23:03:22.495592 Final CLK duty delay cell = 0
2393 23:03:22.499139 [0] MAX Duty = 5156%(X100), DQS PI = 24
2394 23:03:22.502564 [0] MIN Duty = 4938%(X100), DQS PI = 40
2395 23:03:22.502668 [0] AVG Duty = 5047%(X100)
2396 23:03:22.502758
2397 23:03:22.505979 CH1 CLK Duty spec in!! Max-Min= 218%
2398 23:03:22.512364 [DutyScan_Calibration_Flow] ====Done====
2399 23:03:22.512464
2400 23:03:22.515750 [DutyScan_Calibration_Flow] k_type=1
2401 23:03:22.531514
2402 23:03:22.531615 ==DQS 0 ==
2403 23:03:22.534978 Final DQS duty delay cell = 0
2404 23:03:22.538100 [0] MAX Duty = 5031%(X100), DQS PI = 18
2405 23:03:22.541717 [0] MIN Duty = 4844%(X100), DQS PI = 48
2406 23:03:22.544714 [0] AVG Duty = 4937%(X100)
2407 23:03:22.544809
2408 23:03:22.544897 ==DQS 1 ==
2409 23:03:22.548161 Final DQS duty delay cell = 0
2410 23:03:22.551431 [0] MAX Duty = 5062%(X100), DQS PI = 54
2411 23:03:22.555084 [0] MIN Duty = 4907%(X100), DQS PI = 8
2412 23:03:22.555158 [0] AVG Duty = 4984%(X100)
2413 23:03:22.558391
2414 23:03:22.561596 CH1 DQS 0 Duty spec in!! Max-Min= 187%
2415 23:03:22.561692
2416 23:03:22.565305 CH1 DQS 1 Duty spec in!! Max-Min= 155%
2417 23:03:22.568400 [DutyScan_Calibration_Flow] ====Done====
2418 23:03:22.568472
2419 23:03:22.571760 [DutyScan_Calibration_Flow] k_type=3
2420 23:03:22.587691
2421 23:03:22.587776 ==DQM 0 ==
2422 23:03:22.591384 Final DQM duty delay cell = 0
2423 23:03:22.594737 [0] MAX Duty = 5093%(X100), DQS PI = 18
2424 23:03:22.598087 [0] MIN Duty = 4907%(X100), DQS PI = 48
2425 23:03:22.598190 [0] AVG Duty = 5000%(X100)
2426 23:03:22.601350
2427 23:03:22.601445 ==DQM 1 ==
2428 23:03:22.604378 Final DQM duty delay cell = 0
2429 23:03:22.607741 [0] MAX Duty = 5156%(X100), DQS PI = 62
2430 23:03:22.611568 [0] MIN Duty = 4938%(X100), DQS PI = 22
2431 23:03:22.611640 [0] AVG Duty = 5047%(X100)
2432 23:03:22.614594
2433 23:03:22.618056 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2434 23:03:22.618153
2435 23:03:22.621556 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2436 23:03:22.624957 [DutyScan_Calibration_Flow] ====Done====
2437 23:03:22.625054
2438 23:03:22.627766 [DutyScan_Calibration_Flow] k_type=2
2439 23:03:22.644640
2440 23:03:22.644713 ==DQ 0 ==
2441 23:03:22.648161 Final DQ duty delay cell = 0
2442 23:03:22.651344 [0] MAX Duty = 5093%(X100), DQS PI = 18
2443 23:03:22.654680 [0] MIN Duty = 4907%(X100), DQS PI = 50
2444 23:03:22.654754 [0] AVG Duty = 5000%(X100)
2445 23:03:22.654815
2446 23:03:22.658325 ==DQ 1 ==
2447 23:03:22.661416 Final DQ duty delay cell = 0
2448 23:03:22.664393 [0] MAX Duty = 5124%(X100), DQS PI = 58
2449 23:03:22.667684 [0] MIN Duty = 5000%(X100), DQS PI = 50
2450 23:03:22.667767 [0] AVG Duty = 5062%(X100)
2451 23:03:22.667829
2452 23:03:22.671080 CH1 DQ 0 Duty spec in!! Max-Min= 186%
2453 23:03:22.671149
2454 23:03:22.674747 CH1 DQ 1 Duty spec in!! Max-Min= 124%
2455 23:03:22.681475 [DutyScan_Calibration_Flow] ====Done====
2456 23:03:22.684793 nWR fixed to 30
2457 23:03:22.684866 [ModeRegInit_LP4] CH0 RK0
2458 23:03:22.687981 [ModeRegInit_LP4] CH0 RK1
2459 23:03:22.691417 [ModeRegInit_LP4] CH1 RK0
2460 23:03:22.691487 [ModeRegInit_LP4] CH1 RK1
2461 23:03:22.694582 match AC timing 7
2462 23:03:22.698478 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2463 23:03:22.701305 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2464 23:03:22.708498 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2465 23:03:22.711390 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2466 23:03:22.718508 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2467 23:03:22.718614 ==
2468 23:03:22.721898 Dram Type= 6, Freq= 0, CH_0, rank 0
2469 23:03:22.724975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2470 23:03:22.725087 ==
2471 23:03:22.728244 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2472 23:03:22.735311 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2473 23:03:22.744635 [CA 0] Center 40 (10~71) winsize 62
2474 23:03:22.748282 [CA 1] Center 39 (9~70) winsize 62
2475 23:03:22.751013 [CA 2] Center 36 (6~67) winsize 62
2476 23:03:22.754383 [CA 3] Center 35 (5~66) winsize 62
2477 23:03:22.758064 [CA 4] Center 34 (4~65) winsize 62
2478 23:03:22.761244 [CA 5] Center 34 (4~64) winsize 61
2479 23:03:22.761339
2480 23:03:22.765089 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2481 23:03:22.765186
2482 23:03:22.767913 [CATrainingPosCal] consider 1 rank data
2483 23:03:22.771402 u2DelayCellTimex100 = 270/100 ps
2484 23:03:22.775003 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2485 23:03:22.778643 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2486 23:03:22.781772 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2487 23:03:22.788372 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2488 23:03:22.791679 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2489 23:03:22.795155 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2490 23:03:22.795255
2491 23:03:22.797999 CA PerBit enable=1, Macro0, CA PI delay=34
2492 23:03:22.798074
2493 23:03:22.801425 [CBTSetCACLKResult] CA Dly = 34
2494 23:03:22.801524 CS Dly: 7 (0~38)
2495 23:03:22.801612 ==
2496 23:03:22.804968 Dram Type= 6, Freq= 0, CH_0, rank 1
2497 23:03:22.812054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2498 23:03:22.812158 ==
2499 23:03:22.815015 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2500 23:03:22.821608 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2501 23:03:22.830631 [CA 0] Center 39 (9~70) winsize 62
2502 23:03:22.834283 [CA 1] Center 39 (9~70) winsize 62
2503 23:03:22.837298 [CA 2] Center 36 (6~67) winsize 62
2504 23:03:22.840382 [CA 3] Center 36 (5~67) winsize 63
2505 23:03:22.843911 [CA 4] Center 34 (4~65) winsize 62
2506 23:03:22.847355 [CA 5] Center 34 (4~64) winsize 61
2507 23:03:22.847429
2508 23:03:22.850521 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2509 23:03:22.850620
2510 23:03:22.853996 [CATrainingPosCal] consider 2 rank data
2511 23:03:22.857339 u2DelayCellTimex100 = 270/100 ps
2512 23:03:22.860815 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2513 23:03:22.864299 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2514 23:03:22.867079 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2515 23:03:22.873976 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2516 23:03:22.877370 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2517 23:03:22.880828 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2518 23:03:22.880904
2519 23:03:22.884446 CA PerBit enable=1, Macro0, CA PI delay=34
2520 23:03:22.884525
2521 23:03:22.887384 [CBTSetCACLKResult] CA Dly = 34
2522 23:03:22.887471 CS Dly: 8 (0~41)
2523 23:03:22.887534
2524 23:03:22.890783 ----->DramcWriteLeveling(PI) begin...
2525 23:03:22.890921 ==
2526 23:03:22.894469 Dram Type= 6, Freq= 0, CH_0, rank 0
2527 23:03:22.900622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2528 23:03:22.900721 ==
2529 23:03:22.904571 Write leveling (Byte 0): 32 => 32
2530 23:03:22.907682 Write leveling (Byte 1): 30 => 30
2531 23:03:22.907758 DramcWriteLeveling(PI) end<-----
2532 23:03:22.907821
2533 23:03:22.911186 ==
2534 23:03:22.914290 Dram Type= 6, Freq= 0, CH_0, rank 0
2535 23:03:22.917585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2536 23:03:22.917712 ==
2537 23:03:22.921107 [Gating] SW mode calibration
2538 23:03:22.927789 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2539 23:03:22.931329 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2540 23:03:22.937955 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2541 23:03:22.941215 0 15 4 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (1 1)
2542 23:03:22.944263 0 15 8 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
2543 23:03:22.950892 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2544 23:03:22.954302 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2545 23:03:22.957379 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2546 23:03:22.964436 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2547 23:03:22.967862 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2548 23:03:22.970929 1 0 0 | B1->B0 | 3434 2e2e | 1 0 | (1 0) (1 0)
2549 23:03:22.974641 1 0 4 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
2550 23:03:22.980916 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2551 23:03:22.984431 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2552 23:03:22.988319 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2553 23:03:22.994676 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2554 23:03:22.997874 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2555 23:03:23.001583 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2556 23:03:23.008104 1 1 0 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
2557 23:03:23.011489 1 1 4 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
2558 23:03:23.014727 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2559 23:03:23.021082 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2560 23:03:23.024570 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2561 23:03:23.028116 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2562 23:03:23.031552 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2563 23:03:23.037859 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2564 23:03:23.041792 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2565 23:03:23.044934 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2566 23:03:23.051639 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 23:03:23.055030 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 23:03:23.058402 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 23:03:23.064933 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 23:03:23.068457 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 23:03:23.071515 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 23:03:23.078147 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 23:03:23.081793 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 23:03:23.085309 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2575 23:03:23.091729 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2576 23:03:23.095557 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2577 23:03:23.099072 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2578 23:03:23.101791 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2579 23:03:23.108408 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2580 23:03:23.112278 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2581 23:03:23.115409 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2582 23:03:23.118844 Total UI for P1: 0, mck2ui 16
2583 23:03:23.122320 best dqsien dly found for B0: ( 1, 4, 0)
2584 23:03:23.125474 Total UI for P1: 0, mck2ui 16
2585 23:03:23.128672 best dqsien dly found for B1: ( 1, 4, 0)
2586 23:03:23.132452 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2587 23:03:23.135638 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2588 23:03:23.135735
2589 23:03:23.138832 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2590 23:03:23.142073 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2591 23:03:23.145609 [Gating] SW calibration Done
2592 23:03:23.145688 ==
2593 23:03:23.149047 Dram Type= 6, Freq= 0, CH_0, rank 0
2594 23:03:23.155586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2595 23:03:23.155709 ==
2596 23:03:23.155825 RX Vref Scan: 0
2597 23:03:23.155930
2598 23:03:23.159126 RX Vref 0 -> 0, step: 1
2599 23:03:23.159263
2600 23:03:23.162566 RX Delay -40 -> 252, step: 8
2601 23:03:23.165749 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2602 23:03:23.169212 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2603 23:03:23.172554 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2604 23:03:23.176017 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2605 23:03:23.182408 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2606 23:03:23.185826 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2607 23:03:23.189580 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2608 23:03:23.192865 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2609 23:03:23.196106 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2610 23:03:23.199428 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2611 23:03:23.206247 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2612 23:03:23.210023 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2613 23:03:23.212536 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2614 23:03:23.215979 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2615 23:03:23.219428 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2616 23:03:23.226581 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2617 23:03:23.226688 ==
2618 23:03:23.229398 Dram Type= 6, Freq= 0, CH_0, rank 0
2619 23:03:23.233058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2620 23:03:23.233156 ==
2621 23:03:23.233249 DQS Delay:
2622 23:03:23.236341 DQS0 = 0, DQS1 = 0
2623 23:03:23.236444 DQM Delay:
2624 23:03:23.239978 DQM0 = 115, DQM1 = 106
2625 23:03:23.240075 DQ Delay:
2626 23:03:23.243127 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =111
2627 23:03:23.246414 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
2628 23:03:23.249984 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99
2629 23:03:23.253076 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2630 23:03:23.253229
2631 23:03:23.253366
2632 23:03:23.253488 ==
2633 23:03:23.256914 Dram Type= 6, Freq= 0, CH_0, rank 0
2634 23:03:23.263239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2635 23:03:23.263399 ==
2636 23:03:23.263531
2637 23:03:23.263653
2638 23:03:23.263781 TX Vref Scan disable
2639 23:03:23.266529 == TX Byte 0 ==
2640 23:03:23.270524 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2641 23:03:23.273662 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2642 23:03:23.276610 == TX Byte 1 ==
2643 23:03:23.279955 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2644 23:03:23.283513 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2645 23:03:23.287030 ==
2646 23:03:23.287144 Dram Type= 6, Freq= 0, CH_0, rank 0
2647 23:03:23.293827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2648 23:03:23.293969 ==
2649 23:03:23.304625 TX Vref=22, minBit 0, minWin=25, winSum=413
2650 23:03:23.308069 TX Vref=24, minBit 0, minWin=26, winSum=423
2651 23:03:23.311755 TX Vref=26, minBit 12, minWin=25, winSum=424
2652 23:03:23.314810 TX Vref=28, minBit 0, minWin=26, winSum=429
2653 23:03:23.317912 TX Vref=30, minBit 0, minWin=26, winSum=430
2654 23:03:23.321154 TX Vref=32, minBit 0, minWin=26, winSum=426
2655 23:03:23.328184 [TxChooseVref] Worse bit 0, Min win 26, Win sum 430, Final Vref 30
2656 23:03:23.328325
2657 23:03:23.331824 Final TX Range 1 Vref 30
2658 23:03:23.331975
2659 23:03:23.332127 ==
2660 23:03:23.334540 Dram Type= 6, Freq= 0, CH_0, rank 0
2661 23:03:23.338022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2662 23:03:23.338164 ==
2663 23:03:23.338290
2664 23:03:23.338418
2665 23:03:23.341608 TX Vref Scan disable
2666 23:03:23.344877 == TX Byte 0 ==
2667 23:03:23.348383 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2668 23:03:23.351618 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2669 23:03:23.354980 == TX Byte 1 ==
2670 23:03:23.358432 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2671 23:03:23.361933 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2672 23:03:23.362085
2673 23:03:23.365248 [DATLAT]
2674 23:03:23.365386 Freq=1200, CH0 RK0
2675 23:03:23.365515
2676 23:03:23.368289 DATLAT Default: 0xd
2677 23:03:23.368432 0, 0xFFFF, sum = 0
2678 23:03:23.371485 1, 0xFFFF, sum = 0
2679 23:03:23.371628 2, 0xFFFF, sum = 0
2680 23:03:23.375029 3, 0xFFFF, sum = 0
2681 23:03:23.375177 4, 0xFFFF, sum = 0
2682 23:03:23.378413 5, 0xFFFF, sum = 0
2683 23:03:23.378563 6, 0xFFFF, sum = 0
2684 23:03:23.381592 7, 0xFFFF, sum = 0
2685 23:03:23.381730 8, 0xFFFF, sum = 0
2686 23:03:23.384920 9, 0xFFFF, sum = 0
2687 23:03:23.385034 10, 0xFFFF, sum = 0
2688 23:03:23.388782 11, 0xFFFF, sum = 0
2689 23:03:23.388890 12, 0x0, sum = 1
2690 23:03:23.391895 13, 0x0, sum = 2
2691 23:03:23.392005 14, 0x0, sum = 3
2692 23:03:23.395162 15, 0x0, sum = 4
2693 23:03:23.395251 best_step = 13
2694 23:03:23.395316
2695 23:03:23.395375 ==
2696 23:03:23.398309 Dram Type= 6, Freq= 0, CH_0, rank 0
2697 23:03:23.405321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2698 23:03:23.405464 ==
2699 23:03:23.405588 RX Vref Scan: 1
2700 23:03:23.405706
2701 23:03:23.408370 Set Vref Range= 32 -> 127
2702 23:03:23.408513
2703 23:03:23.411894 RX Vref 32 -> 127, step: 1
2704 23:03:23.412028
2705 23:03:23.412211 RX Delay -21 -> 252, step: 4
2706 23:03:23.412369
2707 23:03:23.415490 Set Vref, RX VrefLevel [Byte0]: 32
2708 23:03:23.418571 [Byte1]: 32
2709 23:03:23.423024
2710 23:03:23.423129 Set Vref, RX VrefLevel [Byte0]: 33
2711 23:03:23.426492 [Byte1]: 33
2712 23:03:23.430591
2713 23:03:23.430719 Set Vref, RX VrefLevel [Byte0]: 34
2714 23:03:23.434101 [Byte1]: 34
2715 23:03:23.438748
2716 23:03:23.438882 Set Vref, RX VrefLevel [Byte0]: 35
2717 23:03:23.442385 [Byte1]: 35
2718 23:03:23.446748
2719 23:03:23.446867 Set Vref, RX VrefLevel [Byte0]: 36
2720 23:03:23.450254 [Byte1]: 36
2721 23:03:23.454593
2722 23:03:23.454717 Set Vref, RX VrefLevel [Byte0]: 37
2723 23:03:23.458142 [Byte1]: 37
2724 23:03:23.462555
2725 23:03:23.462676 Set Vref, RX VrefLevel [Byte0]: 38
2726 23:03:23.465982 [Byte1]: 38
2727 23:03:23.470588
2728 23:03:23.470715 Set Vref, RX VrefLevel [Byte0]: 39
2729 23:03:23.474022 [Byte1]: 39
2730 23:03:23.478998
2731 23:03:23.479126 Set Vref, RX VrefLevel [Byte0]: 40
2732 23:03:23.481954 [Byte1]: 40
2733 23:03:23.486069
2734 23:03:23.486186 Set Vref, RX VrefLevel [Byte0]: 41
2735 23:03:23.489532 [Byte1]: 41
2736 23:03:23.494234
2737 23:03:23.494359 Set Vref, RX VrefLevel [Byte0]: 42
2738 23:03:23.497268 [Byte1]: 42
2739 23:03:23.502192
2740 23:03:23.502311 Set Vref, RX VrefLevel [Byte0]: 43
2741 23:03:23.505434 [Byte1]: 43
2742 23:03:23.510320
2743 23:03:23.510450 Set Vref, RX VrefLevel [Byte0]: 44
2744 23:03:23.513405 [Byte1]: 44
2745 23:03:23.517982
2746 23:03:23.518077 Set Vref, RX VrefLevel [Byte0]: 45
2747 23:03:23.521343 [Byte1]: 45
2748 23:03:23.525877
2749 23:03:23.525963 Set Vref, RX VrefLevel [Byte0]: 46
2750 23:03:23.529397 [Byte1]: 46
2751 23:03:23.534042
2752 23:03:23.534125 Set Vref, RX VrefLevel [Byte0]: 47
2753 23:03:23.540807 [Byte1]: 47
2754 23:03:23.540894
2755 23:03:23.543719 Set Vref, RX VrefLevel [Byte0]: 48
2756 23:03:23.547080 [Byte1]: 48
2757 23:03:23.547163
2758 23:03:23.550582 Set Vref, RX VrefLevel [Byte0]: 49
2759 23:03:23.554004 [Byte1]: 49
2760 23:03:23.557944
2761 23:03:23.558047 Set Vref, RX VrefLevel [Byte0]: 50
2762 23:03:23.561260 [Byte1]: 50
2763 23:03:23.565710
2764 23:03:23.565853 Set Vref, RX VrefLevel [Byte0]: 51
2765 23:03:23.568924 [Byte1]: 51
2766 23:03:23.573596
2767 23:03:23.573719 Set Vref, RX VrefLevel [Byte0]: 52
2768 23:03:23.577015 [Byte1]: 52
2769 23:03:23.581659
2770 23:03:23.581801 Set Vref, RX VrefLevel [Byte0]: 53
2771 23:03:23.584845 [Byte1]: 53
2772 23:03:23.589408
2773 23:03:23.589550 Set Vref, RX VrefLevel [Byte0]: 54
2774 23:03:23.592899 [Byte1]: 54
2775 23:03:23.597557
2776 23:03:23.597673 Set Vref, RX VrefLevel [Byte0]: 55
2777 23:03:23.600907 [Byte1]: 55
2778 23:03:23.605548
2779 23:03:23.605649 Set Vref, RX VrefLevel [Byte0]: 56
2780 23:03:23.608783 [Byte1]: 56
2781 23:03:23.613233
2782 23:03:23.613344 Set Vref, RX VrefLevel [Byte0]: 57
2783 23:03:23.616823 [Byte1]: 57
2784 23:03:23.620810
2785 23:03:23.620913 Set Vref, RX VrefLevel [Byte0]: 58
2786 23:03:23.624597 [Byte1]: 58
2787 23:03:23.629005
2788 23:03:23.629114 Set Vref, RX VrefLevel [Byte0]: 59
2789 23:03:23.632323 [Byte1]: 59
2790 23:03:23.636774
2791 23:03:23.636890 Set Vref, RX VrefLevel [Byte0]: 60
2792 23:03:23.640390 [Byte1]: 60
2793 23:03:23.644521
2794 23:03:23.644633 Set Vref, RX VrefLevel [Byte0]: 61
2795 23:03:23.648257 [Byte1]: 61
2796 23:03:23.652548
2797 23:03:23.652648 Set Vref, RX VrefLevel [Byte0]: 62
2798 23:03:23.656337 [Byte1]: 62
2799 23:03:23.660690
2800 23:03:23.660774 Set Vref, RX VrefLevel [Byte0]: 63
2801 23:03:23.664133 [Byte1]: 63
2802 23:03:23.668890
2803 23:03:23.669012 Set Vref, RX VrefLevel [Byte0]: 64
2804 23:03:23.671996 [Byte1]: 64
2805 23:03:23.676659
2806 23:03:23.676746 Set Vref, RX VrefLevel [Byte0]: 65
2807 23:03:23.680118 [Byte1]: 65
2808 23:03:23.684540
2809 23:03:23.684626 Set Vref, RX VrefLevel [Byte0]: 66
2810 23:03:23.688035 [Byte1]: 66
2811 23:03:23.692562
2812 23:03:23.692643 Set Vref, RX VrefLevel [Byte0]: 67
2813 23:03:23.695617 [Byte1]: 67
2814 23:03:23.700199
2815 23:03:23.700281 Set Vref, RX VrefLevel [Byte0]: 68
2816 23:03:23.703682 [Byte1]: 68
2817 23:03:23.708437
2818 23:03:23.708518 Set Vref, RX VrefLevel [Byte0]: 69
2819 23:03:23.711833 [Byte1]: 69
2820 23:03:23.716523
2821 23:03:23.716633 Final RX Vref Byte 0 = 53 to rank0
2822 23:03:23.720076 Final RX Vref Byte 1 = 50 to rank0
2823 23:03:23.723239 Final RX Vref Byte 0 = 53 to rank1
2824 23:03:23.726139 Final RX Vref Byte 1 = 50 to rank1==
2825 23:03:23.729488 Dram Type= 6, Freq= 0, CH_0, rank 0
2826 23:03:23.736246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2827 23:03:23.736331 ==
2828 23:03:23.736397 DQS Delay:
2829 23:03:23.736494 DQS0 = 0, DQS1 = 0
2830 23:03:23.739783 DQM Delay:
2831 23:03:23.739865 DQM0 = 115, DQM1 = 104
2832 23:03:23.742903 DQ Delay:
2833 23:03:23.746719 DQ0 =114, DQ1 =114, DQ2 =112, DQ3 =114
2834 23:03:23.750006 DQ4 =116, DQ5 =108, DQ6 =120, DQ7 =122
2835 23:03:23.753284 DQ8 =92, DQ9 =90, DQ10 =104, DQ11 =96
2836 23:03:23.756899 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =114
2837 23:03:23.756984
2838 23:03:23.757050
2839 23:03:23.763183 [DQSOSCAuto] RK0, (LSB)MR18= 0xfbea, (MSB)MR19= 0x303, tDQSOscB0 = 419 ps tDQSOscB1 = 412 ps
2840 23:03:23.766515 CH0 RK0: MR19=303, MR18=FBEA
2841 23:03:23.773220 CH0_RK0: MR19=0x303, MR18=0xFBEA, DQSOSC=412, MR23=63, INC=38, DEC=25
2842 23:03:23.773345
2843 23:03:23.776672 ----->DramcWriteLeveling(PI) begin...
2844 23:03:23.776759 ==
2845 23:03:23.780156 Dram Type= 6, Freq= 0, CH_0, rank 1
2846 23:03:23.783069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2847 23:03:23.783167 ==
2848 23:03:23.786545 Write leveling (Byte 0): 33 => 33
2849 23:03:23.789882 Write leveling (Byte 1): 29 => 29
2850 23:03:23.793321 DramcWriteLeveling(PI) end<-----
2851 23:03:23.793417
2852 23:03:23.793482 ==
2853 23:03:23.796970 Dram Type= 6, Freq= 0, CH_0, rank 1
2854 23:03:23.799928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2855 23:03:23.800010 ==
2856 23:03:23.803309 [Gating] SW mode calibration
2857 23:03:23.809793 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2858 23:03:23.816884 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2859 23:03:23.819809 0 15 0 | B1->B0 | 2323 2626 | 0 1 | (0 0) (1 1)
2860 23:03:23.826972 0 15 4 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
2861 23:03:23.830101 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2862 23:03:23.833668 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2863 23:03:23.836867 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2864 23:03:23.843801 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2865 23:03:23.847095 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
2866 23:03:23.850515 0 15 28 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 1)
2867 23:03:23.856958 1 0 0 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
2868 23:03:23.860352 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2869 23:03:23.863951 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2870 23:03:23.870630 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2871 23:03:23.873754 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2872 23:03:23.877157 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2873 23:03:23.883718 1 0 24 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
2874 23:03:23.887369 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2875 23:03:23.902787 1 1 0 | B1->B0 | 2c2c 3c3c | 0 0 | (0 0) (0 0)
2876 23:03:23.902943 1 1 4 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
2877 23:03:23.903014 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2878 23:03:23.904151 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2879 23:03:23.907666 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2880 23:03:23.913945 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2881 23:03:23.917463 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2882 23:03:23.920797 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2883 23:03:23.927268 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2884 23:03:23.931119 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2885 23:03:23.934318 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 23:03:23.940941 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 23:03:23.944066 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 23:03:23.947528 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 23:03:23.954301 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 23:03:23.957550 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 23:03:23.961146 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 23:03:23.964508 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 23:03:23.970911 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 23:03:23.974661 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 23:03:23.977604 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2896 23:03:23.984418 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2897 23:03:23.987538 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2898 23:03:23.991119 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2899 23:03:23.997697 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2900 23:03:23.997813 Total UI for P1: 0, mck2ui 16
2901 23:03:24.004412 best dqsien dly found for B0: ( 1, 3, 26)
2902 23:03:24.007942 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2903 23:03:24.011226 Total UI for P1: 0, mck2ui 16
2904 23:03:24.014402 best dqsien dly found for B1: ( 1, 4, 0)
2905 23:03:24.017961 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2906 23:03:24.021572 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2907 23:03:24.021655
2908 23:03:24.024483 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2909 23:03:24.027822 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2910 23:03:24.031298 [Gating] SW calibration Done
2911 23:03:24.031381 ==
2912 23:03:24.034720 Dram Type= 6, Freq= 0, CH_0, rank 1
2913 23:03:24.038264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2914 23:03:24.038348 ==
2915 23:03:24.041592 RX Vref Scan: 0
2916 23:03:24.041674
2917 23:03:24.041740 RX Vref 0 -> 0, step: 1
2918 23:03:24.044795
2919 23:03:24.044880 RX Delay -40 -> 252, step: 8
2920 23:03:24.051728 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2921 23:03:24.054727 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2922 23:03:24.058700 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2923 23:03:24.061584 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2924 23:03:24.064792 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2925 23:03:24.068553 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2926 23:03:24.075327 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2927 23:03:24.078769 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2928 23:03:24.081608 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2929 23:03:24.085039 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2930 23:03:24.089021 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2931 23:03:24.092490 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2932 23:03:24.098770 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2933 23:03:24.102223 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2934 23:03:24.105642 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2935 23:03:24.108994 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2936 23:03:24.109075 ==
2937 23:03:24.112400 Dram Type= 6, Freq= 0, CH_0, rank 1
2938 23:03:24.119035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2939 23:03:24.119132 ==
2940 23:03:24.119197 DQS Delay:
2941 23:03:24.119257 DQS0 = 0, DQS1 = 0
2942 23:03:24.122289 DQM Delay:
2943 23:03:24.122370 DQM0 = 115, DQM1 = 105
2944 23:03:24.125866 DQ Delay:
2945 23:03:24.129087 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
2946 23:03:24.132393 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2947 23:03:24.135801 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
2948 23:03:24.139246 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2949 23:03:24.139328
2950 23:03:24.139391
2951 23:03:24.139450 ==
2952 23:03:24.142259 Dram Type= 6, Freq= 0, CH_0, rank 1
2953 23:03:24.145762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2954 23:03:24.145840 ==
2955 23:03:24.145900
2956 23:03:24.145958
2957 23:03:24.149260 TX Vref Scan disable
2958 23:03:24.152642 == TX Byte 0 ==
2959 23:03:24.155532 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2960 23:03:24.159210 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2961 23:03:24.162695 == TX Byte 1 ==
2962 23:03:24.166091 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2963 23:03:24.169611 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2964 23:03:24.169692 ==
2965 23:03:24.172574 Dram Type= 6, Freq= 0, CH_0, rank 1
2966 23:03:24.176063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2967 23:03:24.179197 ==
2968 23:03:24.189549 TX Vref=22, minBit 3, minWin=25, winSum=425
2969 23:03:24.192959 TX Vref=24, minBit 3, minWin=25, winSum=430
2970 23:03:24.196439 TX Vref=26, minBit 3, minWin=25, winSum=433
2971 23:03:24.199762 TX Vref=28, minBit 2, minWin=26, winSum=436
2972 23:03:24.203147 TX Vref=30, minBit 0, minWin=27, winSum=439
2973 23:03:24.206511 TX Vref=32, minBit 3, minWin=26, winSum=435
2974 23:03:24.212874 [TxChooseVref] Worse bit 0, Min win 27, Win sum 439, Final Vref 30
2975 23:03:24.212956
2976 23:03:24.216276 Final TX Range 1 Vref 30
2977 23:03:24.216357
2978 23:03:24.216421 ==
2979 23:03:24.219560 Dram Type= 6, Freq= 0, CH_0, rank 1
2980 23:03:24.222877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2981 23:03:24.222972 ==
2982 23:03:24.223053
2983 23:03:24.223116
2984 23:03:24.226344 TX Vref Scan disable
2985 23:03:24.230211 == TX Byte 0 ==
2986 23:03:24.233078 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2987 23:03:24.236675 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2988 23:03:24.239522 == TX Byte 1 ==
2989 23:03:24.242863 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2990 23:03:24.246650 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2991 23:03:24.246731
2992 23:03:24.250070 [DATLAT]
2993 23:03:24.250152 Freq=1200, CH0 RK1
2994 23:03:24.250217
2995 23:03:24.253266 DATLAT Default: 0xd
2996 23:03:24.253346 0, 0xFFFF, sum = 0
2997 23:03:24.256631 1, 0xFFFF, sum = 0
2998 23:03:24.256713 2, 0xFFFF, sum = 0
2999 23:03:24.259798 3, 0xFFFF, sum = 0
3000 23:03:24.259880 4, 0xFFFF, sum = 0
3001 23:03:24.262960 5, 0xFFFF, sum = 0
3002 23:03:24.263042 6, 0xFFFF, sum = 0
3003 23:03:24.266495 7, 0xFFFF, sum = 0
3004 23:03:24.266570 8, 0xFFFF, sum = 0
3005 23:03:24.269920 9, 0xFFFF, sum = 0
3006 23:03:24.269989 10, 0xFFFF, sum = 0
3007 23:03:24.273206 11, 0xFFFF, sum = 0
3008 23:03:24.273273 12, 0x0, sum = 1
3009 23:03:24.276566 13, 0x0, sum = 2
3010 23:03:24.276647 14, 0x0, sum = 3
3011 23:03:24.279857 15, 0x0, sum = 4
3012 23:03:24.279937 best_step = 13
3013 23:03:24.280001
3014 23:03:24.280060 ==
3015 23:03:24.283424 Dram Type= 6, Freq= 0, CH_0, rank 1
3016 23:03:24.290019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3017 23:03:24.290100 ==
3018 23:03:24.290163 RX Vref Scan: 0
3019 23:03:24.290223
3020 23:03:24.293445 RX Vref 0 -> 0, step: 1
3021 23:03:24.293524
3022 23:03:24.296895 RX Delay -21 -> 252, step: 4
3023 23:03:24.300373 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3024 23:03:24.303374 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3025 23:03:24.306729 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3026 23:03:24.313633 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3027 23:03:24.317126 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3028 23:03:24.320370 iDelay=195, Bit 5, Center 104 (35 ~ 174) 140
3029 23:03:24.323836 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3030 23:03:24.327383 iDelay=195, Bit 7, Center 120 (51 ~ 190) 140
3031 23:03:24.333969 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3032 23:03:24.336920 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3033 23:03:24.340302 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3034 23:03:24.344105 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3035 23:03:24.347124 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3036 23:03:24.350586 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3037 23:03:24.357782 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3038 23:03:24.360545 iDelay=195, Bit 15, Center 114 (47 ~ 182) 136
3039 23:03:24.360626 ==
3040 23:03:24.364138 Dram Type= 6, Freq= 0, CH_0, rank 1
3041 23:03:24.367754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3042 23:03:24.367844 ==
3043 23:03:24.370587 DQS Delay:
3044 23:03:24.370655 DQS0 = 0, DQS1 = 0
3045 23:03:24.370715 DQM Delay:
3046 23:03:24.373853 DQM0 = 113, DQM1 = 104
3047 23:03:24.373925 DQ Delay:
3048 23:03:24.377497 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3049 23:03:24.380594 DQ4 =112, DQ5 =104, DQ6 =122, DQ7 =120
3050 23:03:24.384309 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =94
3051 23:03:24.387328 DQ12 =110, DQ13 =110, DQ14 =116, DQ15 =114
3052 23:03:24.391072
3053 23:03:24.391147
3054 23:03:24.397724 [DQSOSCAuto] RK1, (LSB)MR18= 0x5f7, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 408 ps
3055 23:03:24.400669 CH0 RK1: MR19=403, MR18=5F7
3056 23:03:24.407708 CH0_RK1: MR19=0x403, MR18=0x5F7, DQSOSC=408, MR23=63, INC=39, DEC=26
3057 23:03:24.407783 [RxdqsGatingPostProcess] freq 1200
3058 23:03:24.414812 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3059 23:03:24.418035 best DQS0 dly(2T, 0.5T) = (0, 12)
3060 23:03:24.421433 best DQS1 dly(2T, 0.5T) = (0, 12)
3061 23:03:24.424360 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3062 23:03:24.428117 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3063 23:03:24.431070 best DQS0 dly(2T, 0.5T) = (0, 11)
3064 23:03:24.434555 best DQS1 dly(2T, 0.5T) = (0, 12)
3065 23:03:24.437992 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3066 23:03:24.438064 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3067 23:03:24.441470 Pre-setting of DQS Precalculation
3068 23:03:24.447818 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3069 23:03:24.447894 ==
3070 23:03:24.451158 Dram Type= 6, Freq= 0, CH_1, rank 0
3071 23:03:24.454516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3072 23:03:24.454588 ==
3073 23:03:24.461475 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3074 23:03:24.468146 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3075 23:03:24.474847 [CA 0] Center 38 (9~68) winsize 60
3076 23:03:24.478135 [CA 1] Center 38 (8~68) winsize 61
3077 23:03:24.481403 [CA 2] Center 35 (5~65) winsize 61
3078 23:03:24.484811 [CA 3] Center 34 (4~65) winsize 62
3079 23:03:24.488650 [CA 4] Center 34 (4~65) winsize 62
3080 23:03:24.491842 [CA 5] Center 34 (4~64) winsize 61
3081 23:03:24.491915
3082 23:03:24.495151 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3083 23:03:24.495222
3084 23:03:24.498363 [CATrainingPosCal] consider 1 rank data
3085 23:03:24.501790 u2DelayCellTimex100 = 270/100 ps
3086 23:03:24.505409 CA0 delay=38 (9~68),Diff = 4 PI (19 cell)
3087 23:03:24.508595 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3088 23:03:24.512225 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3089 23:03:24.518687 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3090 23:03:24.522335 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3091 23:03:24.525680 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3092 23:03:24.525760
3093 23:03:24.528738 CA PerBit enable=1, Macro0, CA PI delay=34
3094 23:03:24.528818
3095 23:03:24.532572 [CBTSetCACLKResult] CA Dly = 34
3096 23:03:24.532652 CS Dly: 6 (0~37)
3097 23:03:24.532717 ==
3098 23:03:24.535471 Dram Type= 6, Freq= 0, CH_1, rank 1
3099 23:03:24.542224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3100 23:03:24.542304 ==
3101 23:03:24.545506 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3102 23:03:24.552602 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3103 23:03:24.560914 [CA 0] Center 38 (8~68) winsize 61
3104 23:03:24.564267 [CA 1] Center 38 (9~67) winsize 59
3105 23:03:24.567269 [CA 2] Center 34 (4~65) winsize 62
3106 23:03:24.570502 [CA 3] Center 34 (4~65) winsize 62
3107 23:03:24.574229 [CA 4] Center 34 (4~65) winsize 62
3108 23:03:24.577813 [CA 5] Center 33 (3~64) winsize 62
3109 23:03:24.577894
3110 23:03:24.581025 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3111 23:03:24.581105
3112 23:03:24.584289 [CATrainingPosCal] consider 2 rank data
3113 23:03:24.587620 u2DelayCellTimex100 = 270/100 ps
3114 23:03:24.590964 CA0 delay=38 (9~68),Diff = 4 PI (19 cell)
3115 23:03:24.594661 CA1 delay=38 (9~67),Diff = 4 PI (19 cell)
3116 23:03:24.600802 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3117 23:03:24.604213 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3118 23:03:24.607481 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3119 23:03:24.611078 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3120 23:03:24.611152
3121 23:03:24.614403 CA PerBit enable=1, Macro0, CA PI delay=34
3122 23:03:24.614484
3123 23:03:24.617371 [CBTSetCACLKResult] CA Dly = 34
3124 23:03:24.617452 CS Dly: 7 (0~40)
3125 23:03:24.617520
3126 23:03:24.620671 ----->DramcWriteLeveling(PI) begin...
3127 23:03:24.620753 ==
3128 23:03:24.624336 Dram Type= 6, Freq= 0, CH_1, rank 0
3129 23:03:24.630707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3130 23:03:24.630787 ==
3131 23:03:24.634295 Write leveling (Byte 0): 25 => 25
3132 23:03:24.637570 Write leveling (Byte 1): 30 => 30
3133 23:03:24.637650 DramcWriteLeveling(PI) end<-----
3134 23:03:24.637731
3135 23:03:24.641068 ==
3136 23:03:24.644219 Dram Type= 6, Freq= 0, CH_1, rank 0
3137 23:03:24.647685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3138 23:03:24.647766 ==
3139 23:03:24.650785 [Gating] SW mode calibration
3140 23:03:24.657489 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3141 23:03:24.661156 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3142 23:03:24.668105 0 15 0 | B1->B0 | 2828 2323 | 1 1 | (0 0) (0 0)
3143 23:03:24.671203 0 15 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3144 23:03:24.674337 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3145 23:03:24.681252 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3146 23:03:24.684712 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3147 23:03:24.688189 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3148 23:03:24.691657 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3149 23:03:24.698353 0 15 28 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 0)
3150 23:03:24.701430 1 0 0 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
3151 23:03:24.704802 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3152 23:03:24.711427 1 0 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3153 23:03:24.714972 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3154 23:03:24.717917 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3155 23:03:24.724684 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3156 23:03:24.728096 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3157 23:03:24.731732 1 0 28 | B1->B0 | 2a2a 2323 | 1 0 | (0 0) (0 0)
3158 23:03:24.738209 1 1 0 | B1->B0 | 4242 3535 | 0 0 | (0 0) (1 1)
3159 23:03:24.741616 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3160 23:03:24.745359 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3161 23:03:24.748497 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3162 23:03:24.755024 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3163 23:03:24.758757 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3164 23:03:24.761977 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3165 23:03:24.768722 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3166 23:03:24.772106 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3167 23:03:24.775537 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 23:03:24.782116 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 23:03:24.785337 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 23:03:24.788659 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 23:03:24.795700 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 23:03:24.798857 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 23:03:24.802195 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 23:03:24.805701 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 23:03:24.812561 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 23:03:24.815384 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 23:03:24.818833 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3178 23:03:24.825973 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3179 23:03:24.828701 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3180 23:03:24.832147 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3181 23:03:24.839225 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3182 23:03:24.842168 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3183 23:03:24.846315 Total UI for P1: 0, mck2ui 16
3184 23:03:24.849087 best dqsien dly found for B0: ( 1, 3, 28)
3185 23:03:24.852675 Total UI for P1: 0, mck2ui 16
3186 23:03:24.856372 best dqsien dly found for B1: ( 1, 3, 28)
3187 23:03:24.859167 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3188 23:03:24.862477 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3189 23:03:24.862559
3190 23:03:24.866235 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3191 23:03:24.869314 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3192 23:03:24.872719 [Gating] SW calibration Done
3193 23:03:24.872799 ==
3194 23:03:24.876103 Dram Type= 6, Freq= 0, CH_1, rank 0
3195 23:03:24.879385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3196 23:03:24.879465 ==
3197 23:03:24.883121 RX Vref Scan: 0
3198 23:03:24.883203
3199 23:03:24.883267 RX Vref 0 -> 0, step: 1
3200 23:03:24.886283
3201 23:03:24.886362 RX Delay -40 -> 252, step: 8
3202 23:03:24.893363 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3203 23:03:24.895989 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3204 23:03:24.899628 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3205 23:03:24.902657 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3206 23:03:24.906602 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3207 23:03:24.909839 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3208 23:03:24.916059 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3209 23:03:24.919832 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3210 23:03:24.923006 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3211 23:03:24.926704 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3212 23:03:24.929496 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3213 23:03:24.936347 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3214 23:03:24.939990 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3215 23:03:24.943197 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3216 23:03:24.946738 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3217 23:03:24.949587 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3218 23:03:24.949667 ==
3219 23:03:24.953383 Dram Type= 6, Freq= 0, CH_1, rank 0
3220 23:03:24.959849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3221 23:03:24.959930 ==
3222 23:03:24.959994 DQS Delay:
3223 23:03:24.963259 DQS0 = 0, DQS1 = 0
3224 23:03:24.963343 DQM Delay:
3225 23:03:24.966825 DQM0 = 116, DQM1 = 108
3226 23:03:24.966949 DQ Delay:
3227 23:03:24.970158 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3228 23:03:24.973401 DQ4 =111, DQ5 =127, DQ6 =127, DQ7 =115
3229 23:03:24.976961 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
3230 23:03:24.980138 DQ12 =123, DQ13 =115, DQ14 =111, DQ15 =111
3231 23:03:24.980218
3232 23:03:24.980282
3233 23:03:24.980341 ==
3234 23:03:24.983088 Dram Type= 6, Freq= 0, CH_1, rank 0
3235 23:03:24.986824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3236 23:03:24.990096 ==
3237 23:03:24.990175
3238 23:03:24.990237
3239 23:03:24.990295 TX Vref Scan disable
3240 23:03:24.993525 == TX Byte 0 ==
3241 23:03:24.996589 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3242 23:03:24.999987 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3243 23:03:25.003450 == TX Byte 1 ==
3244 23:03:25.007345 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3245 23:03:25.010412 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3246 23:03:25.010492 ==
3247 23:03:25.013432 Dram Type= 6, Freq= 0, CH_1, rank 0
3248 23:03:25.020357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3249 23:03:25.020439 ==
3250 23:03:25.030728 TX Vref=22, minBit 1, minWin=24, winSum=412
3251 23:03:25.034147 TX Vref=24, minBit 1, minWin=25, winSum=415
3252 23:03:25.037323 TX Vref=26, minBit 0, minWin=26, winSum=422
3253 23:03:25.040968 TX Vref=28, minBit 1, minWin=26, winSum=427
3254 23:03:25.044433 TX Vref=30, minBit 1, minWin=26, winSum=426
3255 23:03:25.048327 TX Vref=32, minBit 1, minWin=26, winSum=426
3256 23:03:25.054600 [TxChooseVref] Worse bit 1, Min win 26, Win sum 427, Final Vref 28
3257 23:03:25.054683
3258 23:03:25.057426 Final TX Range 1 Vref 28
3259 23:03:25.057506
3260 23:03:25.057569 ==
3261 23:03:25.061127 Dram Type= 6, Freq= 0, CH_1, rank 0
3262 23:03:25.064612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3263 23:03:25.064693 ==
3264 23:03:25.064757
3265 23:03:25.064815
3266 23:03:25.067708 TX Vref Scan disable
3267 23:03:25.071212 == TX Byte 0 ==
3268 23:03:25.074641 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3269 23:03:25.077984 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3270 23:03:25.081487 == TX Byte 1 ==
3271 23:03:25.084833 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3272 23:03:25.088320 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3273 23:03:25.088424
3274 23:03:25.091468 [DATLAT]
3275 23:03:25.091548 Freq=1200, CH1 RK0
3276 23:03:25.091612
3277 23:03:25.094273 DATLAT Default: 0xd
3278 23:03:25.094352 0, 0xFFFF, sum = 0
3279 23:03:25.098053 1, 0xFFFF, sum = 0
3280 23:03:25.098138 2, 0xFFFF, sum = 0
3281 23:03:25.101032 3, 0xFFFF, sum = 0
3282 23:03:25.101114 4, 0xFFFF, sum = 0
3283 23:03:25.104550 5, 0xFFFF, sum = 0
3284 23:03:25.104632 6, 0xFFFF, sum = 0
3285 23:03:25.108125 7, 0xFFFF, sum = 0
3286 23:03:25.108283 8, 0xFFFF, sum = 0
3287 23:03:25.111829 9, 0xFFFF, sum = 0
3288 23:03:25.111912 10, 0xFFFF, sum = 0
3289 23:03:25.114638 11, 0xFFFF, sum = 0
3290 23:03:25.114720 12, 0x0, sum = 1
3291 23:03:25.117930 13, 0x0, sum = 2
3292 23:03:25.118015 14, 0x0, sum = 3
3293 23:03:25.121054 15, 0x0, sum = 4
3294 23:03:25.121136 best_step = 13
3295 23:03:25.121201
3296 23:03:25.121260 ==
3297 23:03:25.125171 Dram Type= 6, Freq= 0, CH_1, rank 0
3298 23:03:25.131183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3299 23:03:25.131266 ==
3300 23:03:25.131330 RX Vref Scan: 1
3301 23:03:25.131390
3302 23:03:25.134723 Set Vref Range= 32 -> 127
3303 23:03:25.134820
3304 23:03:25.138420 RX Vref 32 -> 127, step: 1
3305 23:03:25.138514
3306 23:03:25.138577 RX Delay -21 -> 252, step: 4
3307 23:03:25.138638
3308 23:03:25.141647 Set Vref, RX VrefLevel [Byte0]: 32
3309 23:03:25.145219 [Byte1]: 32
3310 23:03:25.149129
3311 23:03:25.149209 Set Vref, RX VrefLevel [Byte0]: 33
3312 23:03:25.152365 [Byte1]: 33
3313 23:03:25.157179
3314 23:03:25.157259 Set Vref, RX VrefLevel [Byte0]: 34
3315 23:03:25.160752 [Byte1]: 34
3316 23:03:25.165358
3317 23:03:25.165438 Set Vref, RX VrefLevel [Byte0]: 35
3318 23:03:25.168285 [Byte1]: 35
3319 23:03:25.173174
3320 23:03:25.173254 Set Vref, RX VrefLevel [Byte0]: 36
3321 23:03:25.176704 [Byte1]: 36
3322 23:03:25.180627
3323 23:03:25.180699 Set Vref, RX VrefLevel [Byte0]: 37
3324 23:03:25.184028 [Byte1]: 37
3325 23:03:25.189003
3326 23:03:25.189082 Set Vref, RX VrefLevel [Byte0]: 38
3327 23:03:25.191895 [Byte1]: 38
3328 23:03:25.197003
3329 23:03:25.197082 Set Vref, RX VrefLevel [Byte0]: 39
3330 23:03:25.200152 [Byte1]: 39
3331 23:03:25.204433
3332 23:03:25.204512 Set Vref, RX VrefLevel [Byte0]: 40
3333 23:03:25.208062 [Byte1]: 40
3334 23:03:25.212742
3335 23:03:25.212822 Set Vref, RX VrefLevel [Byte0]: 41
3336 23:03:25.216273 [Byte1]: 41
3337 23:03:25.220465
3338 23:03:25.220545 Set Vref, RX VrefLevel [Byte0]: 42
3339 23:03:25.223816 [Byte1]: 42
3340 23:03:25.228334
3341 23:03:25.228413 Set Vref, RX VrefLevel [Byte0]: 43
3342 23:03:25.231514 [Byte1]: 43
3343 23:03:25.236192
3344 23:03:25.236305 Set Vref, RX VrefLevel [Byte0]: 44
3345 23:03:25.239552 [Byte1]: 44
3346 23:03:25.243937
3347 23:03:25.244017 Set Vref, RX VrefLevel [Byte0]: 45
3348 23:03:25.247310 [Byte1]: 45
3349 23:03:25.252491
3350 23:03:25.252571 Set Vref, RX VrefLevel [Byte0]: 46
3351 23:03:25.255925 [Byte1]: 46
3352 23:03:25.260236
3353 23:03:25.260321 Set Vref, RX VrefLevel [Byte0]: 47
3354 23:03:25.263487 [Byte1]: 47
3355 23:03:25.268174
3356 23:03:25.268254 Set Vref, RX VrefLevel [Byte0]: 48
3357 23:03:25.271031 [Byte1]: 48
3358 23:03:25.275985
3359 23:03:25.276066 Set Vref, RX VrefLevel [Byte0]: 49
3360 23:03:25.279367 [Byte1]: 49
3361 23:03:25.283573
3362 23:03:25.283653 Set Vref, RX VrefLevel [Byte0]: 50
3363 23:03:25.287016 [Byte1]: 50
3364 23:03:25.291969
3365 23:03:25.292049 Set Vref, RX VrefLevel [Byte0]: 51
3366 23:03:25.294815 [Byte1]: 51
3367 23:03:25.299802
3368 23:03:25.299883 Set Vref, RX VrefLevel [Byte0]: 52
3369 23:03:25.302724 [Byte1]: 52
3370 23:03:25.307985
3371 23:03:25.308065 Set Vref, RX VrefLevel [Byte0]: 53
3372 23:03:25.310715 [Byte1]: 53
3373 23:03:25.315678
3374 23:03:25.315758 Set Vref, RX VrefLevel [Byte0]: 54
3375 23:03:25.318820 [Byte1]: 54
3376 23:03:25.323559
3377 23:03:25.323640 Set Vref, RX VrefLevel [Byte0]: 55
3378 23:03:25.326978 [Byte1]: 55
3379 23:03:25.331189
3380 23:03:25.331269 Set Vref, RX VrefLevel [Byte0]: 56
3381 23:03:25.334660 [Byte1]: 56
3382 23:03:25.339179
3383 23:03:25.339259 Set Vref, RX VrefLevel [Byte0]: 57
3384 23:03:25.342399 [Byte1]: 57
3385 23:03:25.347213
3386 23:03:25.347293 Set Vref, RX VrefLevel [Byte0]: 58
3387 23:03:25.350332 [Byte1]: 58
3388 23:03:25.355311
3389 23:03:25.355393 Set Vref, RX VrefLevel [Byte0]: 59
3390 23:03:25.358730 [Byte1]: 59
3391 23:03:25.362731
3392 23:03:25.362811 Set Vref, RX VrefLevel [Byte0]: 60
3393 23:03:25.366561 [Byte1]: 60
3394 23:03:25.371210
3395 23:03:25.371291 Set Vref, RX VrefLevel [Byte0]: 61
3396 23:03:25.374359 [Byte1]: 61
3397 23:03:25.378819
3398 23:03:25.378941 Set Vref, RX VrefLevel [Byte0]: 62
3399 23:03:25.382071 [Byte1]: 62
3400 23:03:25.386723
3401 23:03:25.386803 Set Vref, RX VrefLevel [Byte0]: 63
3402 23:03:25.389889 [Byte1]: 63
3403 23:03:25.395315
3404 23:03:25.395395 Set Vref, RX VrefLevel [Byte0]: 64
3405 23:03:25.398053 [Byte1]: 64
3406 23:03:25.402683
3407 23:03:25.402764 Set Vref, RX VrefLevel [Byte0]: 65
3408 23:03:25.406460 [Byte1]: 65
3409 23:03:25.410416
3410 23:03:25.410496 Set Vref, RX VrefLevel [Byte0]: 66
3411 23:03:25.414049 [Byte1]: 66
3412 23:03:25.418622
3413 23:03:25.418707 Set Vref, RX VrefLevel [Byte0]: 67
3414 23:03:25.421749 [Byte1]: 67
3415 23:03:25.426688
3416 23:03:25.426777 Set Vref, RX VrefLevel [Byte0]: 68
3417 23:03:25.430016 [Byte1]: 68
3418 23:03:25.434387
3419 23:03:25.434532 Set Vref, RX VrefLevel [Byte0]: 69
3420 23:03:25.437439 [Byte1]: 69
3421 23:03:25.442121
3422 23:03:25.442202 Final RX Vref Byte 0 = 60 to rank0
3423 23:03:25.445603 Final RX Vref Byte 1 = 51 to rank0
3424 23:03:25.448863 Final RX Vref Byte 0 = 60 to rank1
3425 23:03:25.452240 Final RX Vref Byte 1 = 51 to rank1==
3426 23:03:25.455608 Dram Type= 6, Freq= 0, CH_1, rank 0
3427 23:03:25.459188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3428 23:03:25.462477 ==
3429 23:03:25.462573 DQS Delay:
3430 23:03:25.462637 DQS0 = 0, DQS1 = 0
3431 23:03:25.465768 DQM Delay:
3432 23:03:25.465848 DQM0 = 117, DQM1 = 109
3433 23:03:25.469248 DQ Delay:
3434 23:03:25.472154 DQ0 =120, DQ1 =112, DQ2 =106, DQ3 =116
3435 23:03:25.475886 DQ4 =116, DQ5 =124, DQ6 =128, DQ7 =114
3436 23:03:25.479022 DQ8 =98, DQ9 =98, DQ10 =110, DQ11 =104
3437 23:03:25.482574 DQ12 =116, DQ13 =116, DQ14 =116, DQ15 =114
3438 23:03:25.482692
3439 23:03:25.482783
3440 23:03:25.489260 [DQSOSCAuto] RK0, (LSB)MR18= 0xfce1, (MSB)MR19= 0x303, tDQSOscB0 = 422 ps tDQSOscB1 = 411 ps
3441 23:03:25.492338 CH1 RK0: MR19=303, MR18=FCE1
3442 23:03:25.499598 CH1_RK0: MR19=0x303, MR18=0xFCE1, DQSOSC=411, MR23=63, INC=38, DEC=25
3443 23:03:25.499680
3444 23:03:25.502756 ----->DramcWriteLeveling(PI) begin...
3445 23:03:25.502839 ==
3446 23:03:25.506063 Dram Type= 6, Freq= 0, CH_1, rank 1
3447 23:03:25.509527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3448 23:03:25.509609 ==
3449 23:03:25.512902 Write leveling (Byte 0): 27 => 27
3450 23:03:25.516623 Write leveling (Byte 1): 29 => 29
3451 23:03:25.519459 DramcWriteLeveling(PI) end<-----
3452 23:03:25.519540
3453 23:03:25.519604 ==
3454 23:03:25.522603 Dram Type= 6, Freq= 0, CH_1, rank 1
3455 23:03:25.526110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3456 23:03:25.526191 ==
3457 23:03:25.529223 [Gating] SW mode calibration
3458 23:03:25.536249 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3459 23:03:25.543294 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3460 23:03:25.546159 0 15 0 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
3461 23:03:25.553124 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3462 23:03:25.556638 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3463 23:03:25.559928 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3464 23:03:25.563006 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3465 23:03:25.569685 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
3466 23:03:25.572842 0 15 24 | B1->B0 | 3434 2e2e | 0 0 | (0 0) (0 1)
3467 23:03:25.576835 0 15 28 | B1->B0 | 2727 2323 | 0 0 | (0 0) (1 0)
3468 23:03:25.583393 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3469 23:03:25.586707 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3470 23:03:25.589843 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3471 23:03:25.596813 1 0 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3472 23:03:25.600095 1 0 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3473 23:03:25.603567 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3474 23:03:25.610183 1 0 24 | B1->B0 | 2424 3737 | 0 1 | (0 0) (0 0)
3475 23:03:25.613642 1 0 28 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
3476 23:03:25.616847 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3477 23:03:25.622854 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3478 23:03:25.626693 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3479 23:03:25.629802 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3480 23:03:25.636543 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3481 23:03:25.640073 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3482 23:03:25.643506 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
3483 23:03:25.646255 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3484 23:03:25.653229 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 23:03:25.656927 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 23:03:25.660176 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 23:03:25.666532 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 23:03:25.669820 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 23:03:25.673117 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3490 23:03:25.679700 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3491 23:03:25.683065 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 23:03:25.686585 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3493 23:03:25.692993 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3494 23:03:25.696285 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3495 23:03:25.699569 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3496 23:03:25.706427 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3497 23:03:25.709918 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3498 23:03:25.713349 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3499 23:03:25.720020 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3500 23:03:25.720101 Total UI for P1: 0, mck2ui 16
3501 23:03:25.726526 best dqsien dly found for B0: ( 1, 3, 22)
3502 23:03:25.729664 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3503 23:03:25.733277 Total UI for P1: 0, mck2ui 16
3504 23:03:25.737007 best dqsien dly found for B1: ( 1, 3, 28)
3505 23:03:25.739605 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3506 23:03:25.743051 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3507 23:03:25.743132
3508 23:03:25.746613 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3509 23:03:25.750002 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3510 23:03:25.753380 [Gating] SW calibration Done
3511 23:03:25.753461 ==
3512 23:03:25.756353 Dram Type= 6, Freq= 0, CH_1, rank 1
3513 23:03:25.760087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3514 23:03:25.760169 ==
3515 23:03:25.763184 RX Vref Scan: 0
3516 23:03:25.763281
3517 23:03:25.763360 RX Vref 0 -> 0, step: 1
3518 23:03:25.766793
3519 23:03:25.766898 RX Delay -40 -> 252, step: 8
3520 23:03:25.773480 iDelay=192, Bit 0, Center 111 (40 ~ 183) 144
3521 23:03:25.776355 iDelay=192, Bit 1, Center 111 (40 ~ 183) 144
3522 23:03:25.779668 iDelay=192, Bit 2, Center 103 (32 ~ 175) 144
3523 23:03:25.783386 iDelay=192, Bit 3, Center 115 (48 ~ 183) 136
3524 23:03:25.786653 iDelay=192, Bit 4, Center 111 (40 ~ 183) 144
3525 23:03:25.793497 iDelay=192, Bit 5, Center 123 (56 ~ 191) 136
3526 23:03:25.796343 iDelay=192, Bit 6, Center 119 (48 ~ 191) 144
3527 23:03:25.799964 iDelay=192, Bit 7, Center 107 (40 ~ 175) 136
3528 23:03:25.803309 iDelay=192, Bit 8, Center 99 (24 ~ 175) 152
3529 23:03:25.806894 iDelay=192, Bit 9, Center 95 (24 ~ 167) 144
3530 23:03:25.810127 iDelay=192, Bit 10, Center 111 (40 ~ 183) 144
3531 23:03:25.816852 iDelay=192, Bit 11, Center 103 (32 ~ 175) 144
3532 23:03:25.820262 iDelay=192, Bit 12, Center 115 (48 ~ 183) 136
3533 23:03:25.823179 iDelay=192, Bit 13, Center 119 (48 ~ 191) 144
3534 23:03:25.826409 iDelay=192, Bit 14, Center 119 (48 ~ 191) 144
3535 23:03:25.830176 iDelay=192, Bit 15, Center 119 (48 ~ 191) 144
3536 23:03:25.833145 ==
3537 23:03:25.836354 Dram Type= 6, Freq= 0, CH_1, rank 1
3538 23:03:25.840137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3539 23:03:25.840219 ==
3540 23:03:25.840283 DQS Delay:
3541 23:03:25.843192 DQS0 = 0, DQS1 = 0
3542 23:03:25.843273 DQM Delay:
3543 23:03:25.846648 DQM0 = 112, DQM1 = 110
3544 23:03:25.846732 DQ Delay:
3545 23:03:25.850222 DQ0 =111, DQ1 =111, DQ2 =103, DQ3 =115
3546 23:03:25.853591 DQ4 =111, DQ5 =123, DQ6 =119, DQ7 =107
3547 23:03:25.856393 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =103
3548 23:03:25.860363 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =119
3549 23:03:25.860467
3550 23:03:25.860532
3551 23:03:25.860594 ==
3552 23:03:25.863566 Dram Type= 6, Freq= 0, CH_1, rank 1
3553 23:03:25.869986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3554 23:03:25.870068 ==
3555 23:03:25.870154
3556 23:03:25.870226
3557 23:03:25.870284 TX Vref Scan disable
3558 23:03:25.873534 == TX Byte 0 ==
3559 23:03:25.876892 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3560 23:03:25.880603 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3561 23:03:25.883485 == TX Byte 1 ==
3562 23:03:25.887078 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3563 23:03:25.889925 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3564 23:03:25.893335 ==
3565 23:03:25.896882 Dram Type= 6, Freq= 0, CH_1, rank 1
3566 23:03:25.900068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3567 23:03:25.900150 ==
3568 23:03:25.911918 TX Vref=22, minBit 1, minWin=25, winSum=420
3569 23:03:25.914433 TX Vref=24, minBit 0, minWin=26, winSum=427
3570 23:03:25.917715 TX Vref=26, minBit 1, minWin=26, winSum=428
3571 23:03:25.921069 TX Vref=28, minBit 2, minWin=26, winSum=431
3572 23:03:25.924325 TX Vref=30, minBit 2, minWin=26, winSum=433
3573 23:03:25.928485 TX Vref=32, minBit 3, minWin=26, winSum=432
3574 23:03:25.934921 [TxChooseVref] Worse bit 2, Min win 26, Win sum 433, Final Vref 30
3575 23:03:25.935004
3576 23:03:25.937800 Final TX Range 1 Vref 30
3577 23:03:25.937882
3578 23:03:25.937946 ==
3579 23:03:25.941103 Dram Type= 6, Freq= 0, CH_1, rank 1
3580 23:03:25.944626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3581 23:03:25.944724 ==
3582 23:03:25.944803
3583 23:03:25.944863
3584 23:03:25.947758 TX Vref Scan disable
3585 23:03:25.951671 == TX Byte 0 ==
3586 23:03:25.954700 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3587 23:03:25.957814 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3588 23:03:25.961307 == TX Byte 1 ==
3589 23:03:25.964465 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3590 23:03:25.968084 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3591 23:03:25.968165
3592 23:03:25.971409 [DATLAT]
3593 23:03:25.971489 Freq=1200, CH1 RK1
3594 23:03:25.971555
3595 23:03:25.974489 DATLAT Default: 0xd
3596 23:03:25.974600 0, 0xFFFF, sum = 0
3597 23:03:25.977615 1, 0xFFFF, sum = 0
3598 23:03:25.977697 2, 0xFFFF, sum = 0
3599 23:03:25.981202 3, 0xFFFF, sum = 0
3600 23:03:25.981285 4, 0xFFFF, sum = 0
3601 23:03:25.984582 5, 0xFFFF, sum = 0
3602 23:03:25.984664 6, 0xFFFF, sum = 0
3603 23:03:25.988177 7, 0xFFFF, sum = 0
3604 23:03:25.988260 8, 0xFFFF, sum = 0
3605 23:03:25.991345 9, 0xFFFF, sum = 0
3606 23:03:25.991429 10, 0xFFFF, sum = 0
3607 23:03:25.994816 11, 0xFFFF, sum = 0
3608 23:03:25.997892 12, 0x0, sum = 1
3609 23:03:25.997979 13, 0x0, sum = 2
3610 23:03:25.998079 14, 0x0, sum = 3
3611 23:03:26.001426 15, 0x0, sum = 4
3612 23:03:26.001508 best_step = 13
3613 23:03:26.001572
3614 23:03:26.001632 ==
3615 23:03:26.004726 Dram Type= 6, Freq= 0, CH_1, rank 1
3616 23:03:26.011233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3617 23:03:26.011352 ==
3618 23:03:26.011417 RX Vref Scan: 0
3619 23:03:26.011478
3620 23:03:26.014729 RX Vref 0 -> 0, step: 1
3621 23:03:26.014810
3622 23:03:26.018039 RX Delay -21 -> 252, step: 4
3623 23:03:26.021329 iDelay=191, Bit 0, Center 114 (47 ~ 182) 136
3624 23:03:26.024651 iDelay=191, Bit 1, Center 108 (43 ~ 174) 132
3625 23:03:26.031073 iDelay=191, Bit 2, Center 106 (43 ~ 170) 128
3626 23:03:26.034641 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3627 23:03:26.037873 iDelay=191, Bit 4, Center 114 (51 ~ 178) 128
3628 23:03:26.041032 iDelay=191, Bit 5, Center 124 (59 ~ 190) 132
3629 23:03:26.044756 iDelay=191, Bit 6, Center 120 (55 ~ 186) 132
3630 23:03:26.051112 iDelay=191, Bit 7, Center 110 (47 ~ 174) 128
3631 23:03:26.054364 iDelay=191, Bit 8, Center 96 (31 ~ 162) 132
3632 23:03:26.057852 iDelay=191, Bit 9, Center 98 (35 ~ 162) 128
3633 23:03:26.061616 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3634 23:03:26.064608 iDelay=191, Bit 11, Center 102 (35 ~ 170) 136
3635 23:03:26.071410 iDelay=191, Bit 12, Center 114 (51 ~ 178) 128
3636 23:03:26.075021 iDelay=191, Bit 13, Center 120 (55 ~ 186) 132
3637 23:03:26.078034 iDelay=191, Bit 14, Center 118 (55 ~ 182) 128
3638 23:03:26.081488 iDelay=191, Bit 15, Center 116 (51 ~ 182) 132
3639 23:03:26.081570 ==
3640 23:03:26.084524 Dram Type= 6, Freq= 0, CH_1, rank 1
3641 23:03:26.087731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3642 23:03:26.091206 ==
3643 23:03:26.091287 DQS Delay:
3644 23:03:26.091351 DQS0 = 0, DQS1 = 0
3645 23:03:26.094701 DQM Delay:
3646 23:03:26.094782 DQM0 = 113, DQM1 = 109
3647 23:03:26.098081 DQ Delay:
3648 23:03:26.101469 DQ0 =114, DQ1 =108, DQ2 =106, DQ3 =112
3649 23:03:26.104802 DQ4 =114, DQ5 =124, DQ6 =120, DQ7 =110
3650 23:03:26.107746 DQ8 =96, DQ9 =98, DQ10 =110, DQ11 =102
3651 23:03:26.111343 DQ12 =114, DQ13 =120, DQ14 =118, DQ15 =116
3652 23:03:26.111424
3653 23:03:26.111489
3654 23:03:26.117758 [DQSOSCAuto] RK1, (LSB)MR18= 0xf5fd, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 414 ps
3655 23:03:26.122160 CH1 RK1: MR19=303, MR18=F5FD
3656 23:03:26.127937 CH1_RK1: MR19=0x303, MR18=0xF5FD, DQSOSC=411, MR23=63, INC=38, DEC=25
3657 23:03:26.131547 [RxdqsGatingPostProcess] freq 1200
3658 23:03:26.137965 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3659 23:03:26.138077 best DQS0 dly(2T, 0.5T) = (0, 11)
3660 23:03:26.141546 best DQS1 dly(2T, 0.5T) = (0, 11)
3661 23:03:26.144869 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3662 23:03:26.148070 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3663 23:03:26.151689 best DQS0 dly(2T, 0.5T) = (0, 11)
3664 23:03:26.155119 best DQS1 dly(2T, 0.5T) = (0, 11)
3665 23:03:26.157869 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3666 23:03:26.161383 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3667 23:03:26.165028 Pre-setting of DQS Precalculation
3668 23:03:26.168022 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3669 23:03:26.177815 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3670 23:03:26.184705 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3671 23:03:26.184787
3672 23:03:26.184850
3673 23:03:26.187949 [Calibration Summary] 2400 Mbps
3674 23:03:26.188031 CH 0, Rank 0
3675 23:03:26.191266 SW Impedance : PASS
3676 23:03:26.191348 DUTY Scan : NO K
3677 23:03:26.194761 ZQ Calibration : PASS
3678 23:03:26.198065 Jitter Meter : NO K
3679 23:03:26.198146 CBT Training : PASS
3680 23:03:26.201613 Write leveling : PASS
3681 23:03:26.204651 RX DQS gating : PASS
3682 23:03:26.204732 RX DQ/DQS(RDDQC) : PASS
3683 23:03:26.208477 TX DQ/DQS : PASS
3684 23:03:26.211758 RX DATLAT : PASS
3685 23:03:26.211839 RX DQ/DQS(Engine): PASS
3686 23:03:26.214743 TX OE : NO K
3687 23:03:26.214825 All Pass.
3688 23:03:26.214900
3689 23:03:26.218251 CH 0, Rank 1
3690 23:03:26.218332 SW Impedance : PASS
3691 23:03:26.221709 DUTY Scan : NO K
3692 23:03:26.224931 ZQ Calibration : PASS
3693 23:03:26.225011 Jitter Meter : NO K
3694 23:03:26.227937 CBT Training : PASS
3695 23:03:26.228018 Write leveling : PASS
3696 23:03:26.231811 RX DQS gating : PASS
3697 23:03:26.234841 RX DQ/DQS(RDDQC) : PASS
3698 23:03:26.234959 TX DQ/DQS : PASS
3699 23:03:26.237865 RX DATLAT : PASS
3700 23:03:26.241462 RX DQ/DQS(Engine): PASS
3701 23:03:26.241543 TX OE : NO K
3702 23:03:26.244725 All Pass.
3703 23:03:26.244806
3704 23:03:26.244869 CH 1, Rank 0
3705 23:03:26.248480 SW Impedance : PASS
3706 23:03:26.248561 DUTY Scan : NO K
3707 23:03:26.251615 ZQ Calibration : PASS
3708 23:03:26.254712 Jitter Meter : NO K
3709 23:03:26.254794 CBT Training : PASS
3710 23:03:26.258291 Write leveling : PASS
3711 23:03:26.261681 RX DQS gating : PASS
3712 23:03:26.261762 RX DQ/DQS(RDDQC) : PASS
3713 23:03:26.265311 TX DQ/DQS : PASS
3714 23:03:26.265392 RX DATLAT : PASS
3715 23:03:26.268532 RX DQ/DQS(Engine): PASS
3716 23:03:26.271898 TX OE : NO K
3717 23:03:26.271979 All Pass.
3718 23:03:26.272043
3719 23:03:26.272103 CH 1, Rank 1
3720 23:03:26.274957 SW Impedance : PASS
3721 23:03:26.278428 DUTY Scan : NO K
3722 23:03:26.278509 ZQ Calibration : PASS
3723 23:03:26.282015 Jitter Meter : NO K
3724 23:03:26.285360 CBT Training : PASS
3725 23:03:26.285442 Write leveling : PASS
3726 23:03:26.288783 RX DQS gating : PASS
3727 23:03:26.292073 RX DQ/DQS(RDDQC) : PASS
3728 23:03:26.292154 TX DQ/DQS : PASS
3729 23:03:26.295095 RX DATLAT : PASS
3730 23:03:26.295176 RX DQ/DQS(Engine): PASS
3731 23:03:26.298557 TX OE : NO K
3732 23:03:26.298638 All Pass.
3733 23:03:26.298703
3734 23:03:26.302133 DramC Write-DBI off
3735 23:03:26.305512 PER_BANK_REFRESH: Hybrid Mode
3736 23:03:26.305593 TX_TRACKING: ON
3737 23:03:26.315454 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3738 23:03:26.318189 [FAST_K] Save calibration result to emmc
3739 23:03:26.321822 dramc_set_vcore_voltage set vcore to 650000
3740 23:03:26.325007 Read voltage for 600, 5
3741 23:03:26.325088 Vio18 = 0
3742 23:03:26.328442 Vcore = 650000
3743 23:03:26.328523 Vdram = 0
3744 23:03:26.328588 Vddq = 0
3745 23:03:26.328647 Vmddr = 0
3746 23:03:26.335328 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3747 23:03:26.338838 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3748 23:03:26.341605 MEM_TYPE=3, freq_sel=19
3749 23:03:26.344953 sv_algorithm_assistance_LP4_1600
3750 23:03:26.348318 ============ PULL DRAM RESETB DOWN ============
3751 23:03:26.355150 ========== PULL DRAM RESETB DOWN end =========
3752 23:03:26.358657 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3753 23:03:26.362088 ===================================
3754 23:03:26.364932 LPDDR4 DRAM CONFIGURATION
3755 23:03:26.368536 ===================================
3756 23:03:26.368617 EX_ROW_EN[0] = 0x0
3757 23:03:26.371763 EX_ROW_EN[1] = 0x0
3758 23:03:26.371844 LP4Y_EN = 0x0
3759 23:03:26.375187 WORK_FSP = 0x0
3760 23:03:26.375269 WL = 0x2
3761 23:03:26.378545 RL = 0x2
3762 23:03:26.378626 BL = 0x2
3763 23:03:26.381808 RPST = 0x0
3764 23:03:26.381889 RD_PRE = 0x0
3765 23:03:26.384973 WR_PRE = 0x1
3766 23:03:26.388678 WR_PST = 0x0
3767 23:03:26.388759 DBI_WR = 0x0
3768 23:03:26.391448 DBI_RD = 0x0
3769 23:03:26.391529 OTF = 0x1
3770 23:03:26.395133 ===================================
3771 23:03:26.398224 ===================================
3772 23:03:26.398305 ANA top config
3773 23:03:26.401789 ===================================
3774 23:03:26.404840 DLL_ASYNC_EN = 0
3775 23:03:26.408209 ALL_SLAVE_EN = 1
3776 23:03:26.411622 NEW_RANK_MODE = 1
3777 23:03:26.414919 DLL_IDLE_MODE = 1
3778 23:03:26.415000 LP45_APHY_COMB_EN = 1
3779 23:03:26.418268 TX_ODT_DIS = 1
3780 23:03:26.421472 NEW_8X_MODE = 1
3781 23:03:26.425099 ===================================
3782 23:03:26.428220 ===================================
3783 23:03:26.431208 data_rate = 1200
3784 23:03:26.434669 CKR = 1
3785 23:03:26.434749 DQ_P2S_RATIO = 8
3786 23:03:26.438642 ===================================
3787 23:03:26.441706 CA_P2S_RATIO = 8
3788 23:03:26.444580 DQ_CA_OPEN = 0
3789 23:03:26.448432 DQ_SEMI_OPEN = 0
3790 23:03:26.451944 CA_SEMI_OPEN = 0
3791 23:03:26.455150 CA_FULL_RATE = 0
3792 23:03:26.455232 DQ_CKDIV4_EN = 1
3793 23:03:26.458403 CA_CKDIV4_EN = 1
3794 23:03:26.461942 CA_PREDIV_EN = 0
3795 23:03:26.464858 PH8_DLY = 0
3796 23:03:26.468340 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3797 23:03:26.468422 DQ_AAMCK_DIV = 4
3798 23:03:26.471726 CA_AAMCK_DIV = 4
3799 23:03:26.475165 CA_ADMCK_DIV = 4
3800 23:03:26.478558 DQ_TRACK_CA_EN = 0
3801 23:03:26.482149 CA_PICK = 600
3802 23:03:26.484962 CA_MCKIO = 600
3803 23:03:26.485043 MCKIO_SEMI = 0
3804 23:03:26.488554 PLL_FREQ = 2288
3805 23:03:26.491916 DQ_UI_PI_RATIO = 32
3806 23:03:26.495335 CA_UI_PI_RATIO = 0
3807 23:03:26.498672 ===================================
3808 23:03:26.501891 ===================================
3809 23:03:26.505021 memory_type:LPDDR4
3810 23:03:26.505102 GP_NUM : 10
3811 23:03:26.508604 SRAM_EN : 1
3812 23:03:26.511584 MD32_EN : 0
3813 23:03:26.515025 ===================================
3814 23:03:26.515108 [ANA_INIT] >>>>>>>>>>>>>>
3815 23:03:26.518262 <<<<<< [CONFIGURE PHASE]: ANA_TX
3816 23:03:26.521405 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3817 23:03:26.525089 ===================================
3818 23:03:26.528271 data_rate = 1200,PCW = 0X5800
3819 23:03:26.532054 ===================================
3820 23:03:26.535324 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3821 23:03:26.541563 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3822 23:03:26.544847 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3823 23:03:26.551789 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3824 23:03:26.555115 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3825 23:03:26.558608 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3826 23:03:26.558707 [ANA_INIT] flow start
3827 23:03:26.562148 [ANA_INIT] PLL >>>>>>>>
3828 23:03:26.565752 [ANA_INIT] PLL <<<<<<<<
3829 23:03:26.565833 [ANA_INIT] MIDPI >>>>>>>>
3830 23:03:26.568986 [ANA_INIT] MIDPI <<<<<<<<
3831 23:03:26.571840 [ANA_INIT] DLL >>>>>>>>
3832 23:03:26.571921 [ANA_INIT] flow end
3833 23:03:26.578522 ============ LP4 DIFF to SE enter ============
3834 23:03:26.582235 ============ LP4 DIFF to SE exit ============
3835 23:03:26.585403 [ANA_INIT] <<<<<<<<<<<<<
3836 23:03:26.588269 [Flow] Enable top DCM control >>>>>
3837 23:03:26.592084 [Flow] Enable top DCM control <<<<<
3838 23:03:26.592165 Enable DLL master slave shuffle
3839 23:03:26.598568 ==============================================================
3840 23:03:26.602147 Gating Mode config
3841 23:03:26.605867 ==============================================================
3842 23:03:26.608392 Config description:
3843 23:03:26.618662 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3844 23:03:26.625282 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3845 23:03:26.628868 SELPH_MODE 0: By rank 1: By Phase
3846 23:03:26.635325 ==============================================================
3847 23:03:26.638807 GAT_TRACK_EN = 1
3848 23:03:26.641817 RX_GATING_MODE = 2
3849 23:03:26.641898 RX_GATING_TRACK_MODE = 2
3850 23:03:26.645608 SELPH_MODE = 1
3851 23:03:26.648902 PICG_EARLY_EN = 1
3852 23:03:26.652302 VALID_LAT_VALUE = 1
3853 23:03:26.659000 ==============================================================
3854 23:03:26.661954 Enter into Gating configuration >>>>
3855 23:03:26.665828 Exit from Gating configuration <<<<
3856 23:03:26.669224 Enter into DVFS_PRE_config >>>>>
3857 23:03:26.679174 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3858 23:03:26.682634 Exit from DVFS_PRE_config <<<<<
3859 23:03:26.685340 Enter into PICG configuration >>>>
3860 23:03:26.688752 Exit from PICG configuration <<<<
3861 23:03:26.692142 [RX_INPUT] configuration >>>>>
3862 23:03:26.695878 [RX_INPUT] configuration <<<<<
3863 23:03:26.699265 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3864 23:03:26.705723 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3865 23:03:26.709081 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3866 23:03:26.715930 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3867 23:03:26.723012 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3868 23:03:26.728928 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3869 23:03:26.732714 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3870 23:03:26.736030 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3871 23:03:26.742727 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3872 23:03:26.745686 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3873 23:03:26.749209 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3874 23:03:26.755689 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3875 23:03:26.759169 ===================================
3876 23:03:26.759251 LPDDR4 DRAM CONFIGURATION
3877 23:03:26.762422 ===================================
3878 23:03:26.766060 EX_ROW_EN[0] = 0x0
3879 23:03:26.766148 EX_ROW_EN[1] = 0x0
3880 23:03:26.769158 LP4Y_EN = 0x0
3881 23:03:26.769239 WORK_FSP = 0x0
3882 23:03:26.772697 WL = 0x2
3883 23:03:26.772778 RL = 0x2
3884 23:03:26.775717 BL = 0x2
3885 23:03:26.775798 RPST = 0x0
3886 23:03:26.779310 RD_PRE = 0x0
3887 23:03:26.782309 WR_PRE = 0x1
3888 23:03:26.782389 WR_PST = 0x0
3889 23:03:26.785694 DBI_WR = 0x0
3890 23:03:26.785775 DBI_RD = 0x0
3891 23:03:26.789559 OTF = 0x1
3892 23:03:26.792544 ===================================
3893 23:03:26.795583 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3894 23:03:26.799122 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3895 23:03:26.802547 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3896 23:03:26.805589 ===================================
3897 23:03:26.808937 LPDDR4 DRAM CONFIGURATION
3898 23:03:26.812458 ===================================
3899 23:03:26.815802 EX_ROW_EN[0] = 0x10
3900 23:03:26.815883 EX_ROW_EN[1] = 0x0
3901 23:03:26.818851 LP4Y_EN = 0x0
3902 23:03:26.818937 WORK_FSP = 0x0
3903 23:03:26.822354 WL = 0x2
3904 23:03:26.822460 RL = 0x2
3905 23:03:26.825788 BL = 0x2
3906 23:03:26.825868 RPST = 0x0
3907 23:03:26.829181 RD_PRE = 0x0
3908 23:03:26.829262 WR_PRE = 0x1
3909 23:03:26.832280 WR_PST = 0x0
3910 23:03:26.832360 DBI_WR = 0x0
3911 23:03:26.835702 DBI_RD = 0x0
3912 23:03:26.835783 OTF = 0x1
3913 23:03:26.839844 ===================================
3914 23:03:26.845789 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3915 23:03:26.850394 nWR fixed to 30
3916 23:03:26.853755 [ModeRegInit_LP4] CH0 RK0
3917 23:03:26.853836 [ModeRegInit_LP4] CH0 RK1
3918 23:03:26.857451 [ModeRegInit_LP4] CH1 RK0
3919 23:03:26.860733 [ModeRegInit_LP4] CH1 RK1
3920 23:03:26.860813 match AC timing 17
3921 23:03:26.867151 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3922 23:03:26.870346 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3923 23:03:26.873937 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3924 23:03:26.880373 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3925 23:03:26.884031 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3926 23:03:26.884112 ==
3927 23:03:26.887025 Dram Type= 6, Freq= 0, CH_0, rank 0
3928 23:03:26.890672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3929 23:03:26.890754 ==
3930 23:03:26.897182 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3931 23:03:26.903566 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3932 23:03:26.907294 [CA 0] Center 36 (6~67) winsize 62
3933 23:03:26.910685 [CA 1] Center 36 (6~66) winsize 61
3934 23:03:26.914170 [CA 2] Center 34 (4~65) winsize 62
3935 23:03:26.917229 [CA 3] Center 34 (4~65) winsize 62
3936 23:03:26.920352 [CA 4] Center 33 (3~64) winsize 62
3937 23:03:26.923840 [CA 5] Center 33 (3~64) winsize 62
3938 23:03:26.923921
3939 23:03:26.927130 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3940 23:03:26.927212
3941 23:03:26.930726 [CATrainingPosCal] consider 1 rank data
3942 23:03:26.933965 u2DelayCellTimex100 = 270/100 ps
3943 23:03:26.937279 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3944 23:03:26.940815 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3945 23:03:26.943675 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3946 23:03:26.947503 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3947 23:03:26.950351 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3948 23:03:26.954548 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3949 23:03:26.954631
3950 23:03:26.960695 CA PerBit enable=1, Macro0, CA PI delay=33
3951 23:03:26.960777
3952 23:03:26.960841 [CBTSetCACLKResult] CA Dly = 33
3953 23:03:26.963953 CS Dly: 3 (0~34)
3954 23:03:26.964035 ==
3955 23:03:26.967395 Dram Type= 6, Freq= 0, CH_0, rank 1
3956 23:03:26.970719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3957 23:03:26.970819 ==
3958 23:03:26.977132 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3959 23:03:26.984178 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3960 23:03:26.987342 [CA 0] Center 36 (6~67) winsize 62
3961 23:03:26.990812 [CA 1] Center 36 (6~66) winsize 61
3962 23:03:26.994189 [CA 2] Center 34 (4~64) winsize 61
3963 23:03:26.997345 [CA 3] Center 34 (4~64) winsize 61
3964 23:03:27.001418 [CA 4] Center 33 (3~64) winsize 62
3965 23:03:27.004057 [CA 5] Center 33 (3~64) winsize 62
3966 23:03:27.004143
3967 23:03:27.007153 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3968 23:03:27.007290
3969 23:03:27.010703 [CATrainingPosCal] consider 2 rank data
3970 23:03:27.014143 u2DelayCellTimex100 = 270/100 ps
3971 23:03:27.017884 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3972 23:03:27.020542 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3973 23:03:27.023933 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
3974 23:03:27.027459 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
3975 23:03:27.030793 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3976 23:03:27.034296 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3977 23:03:27.034384
3978 23:03:27.037323 CA PerBit enable=1, Macro0, CA PI delay=33
3979 23:03:27.041137
3980 23:03:27.041219 [CBTSetCACLKResult] CA Dly = 33
3981 23:03:27.044496 CS Dly: 4 (0~37)
3982 23:03:27.044603
3983 23:03:27.048201 ----->DramcWriteLeveling(PI) begin...
3984 23:03:27.048312 ==
3985 23:03:27.051109 Dram Type= 6, Freq= 0, CH_0, rank 0
3986 23:03:27.054272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3987 23:03:27.054358 ==
3988 23:03:27.057951 Write leveling (Byte 0): 32 => 32
3989 23:03:27.060787 Write leveling (Byte 1): 30 => 30
3990 23:03:27.064125 DramcWriteLeveling(PI) end<-----
3991 23:03:27.064233
3992 23:03:27.064327 ==
3993 23:03:27.068263 Dram Type= 6, Freq= 0, CH_0, rank 0
3994 23:03:27.071098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3995 23:03:27.071181 ==
3996 23:03:27.074487 [Gating] SW mode calibration
3997 23:03:27.080776 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3998 23:03:27.087841 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3999 23:03:27.091173 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4000 23:03:27.097408 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4001 23:03:27.101287 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4002 23:03:27.104260 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4003 23:03:27.111256 0 9 16 | B1->B0 | 3131 2626 | 1 1 | (1 0) (0 0)
4004 23:03:27.114371 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4005 23:03:27.117753 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4006 23:03:27.121025 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4007 23:03:27.127687 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4008 23:03:27.131125 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4009 23:03:27.134386 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4010 23:03:27.141120 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4011 23:03:27.144427 0 10 16 | B1->B0 | 2f2f 3d3d | 1 1 | (1 1) (0 0)
4012 23:03:27.147544 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4013 23:03:27.154337 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4014 23:03:27.158047 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4015 23:03:27.161327 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4016 23:03:27.167759 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4017 23:03:27.171023 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4018 23:03:27.174391 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4019 23:03:27.181214 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4020 23:03:27.184547 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 23:03:27.187440 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 23:03:27.194171 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 23:03:27.197691 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 23:03:27.201164 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 23:03:27.207601 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 23:03:27.211097 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 23:03:27.214352 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 23:03:27.217510 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 23:03:27.224041 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 23:03:27.227423 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 23:03:27.231016 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 23:03:27.237440 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4033 23:03:27.241200 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4034 23:03:27.244371 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 23:03:27.250980 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4036 23:03:27.251064 Total UI for P1: 0, mck2ui 16
4037 23:03:27.258215 best dqsien dly found for B0: ( 0, 13, 14)
4038 23:03:27.261213 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4039 23:03:27.264243 Total UI for P1: 0, mck2ui 16
4040 23:03:27.268089 best dqsien dly found for B1: ( 0, 13, 16)
4041 23:03:27.271500 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4042 23:03:27.274741 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4043 23:03:27.274825
4044 23:03:27.278218 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4045 23:03:27.281176 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4046 23:03:27.284484 [Gating] SW calibration Done
4047 23:03:27.284565 ==
4048 23:03:27.288014 Dram Type= 6, Freq= 0, CH_0, rank 0
4049 23:03:27.291341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4050 23:03:27.291424 ==
4051 23:03:27.294649 RX Vref Scan: 0
4052 23:03:27.294730
4053 23:03:27.297649 RX Vref 0 -> 0, step: 1
4054 23:03:27.297731
4055 23:03:27.297795 RX Delay -230 -> 252, step: 16
4056 23:03:27.304594 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4057 23:03:27.308189 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4058 23:03:27.311438 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4059 23:03:27.314981 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4060 23:03:27.321499 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4061 23:03:27.324828 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4062 23:03:27.328141 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4063 23:03:27.331502 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4064 23:03:27.334728 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4065 23:03:27.341586 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4066 23:03:27.344670 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4067 23:03:27.348040 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4068 23:03:27.351477 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4069 23:03:27.358525 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4070 23:03:27.361271 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4071 23:03:27.365058 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4072 23:03:27.365140 ==
4073 23:03:27.368365 Dram Type= 6, Freq= 0, CH_0, rank 0
4074 23:03:27.371517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4075 23:03:27.371598 ==
4076 23:03:27.374723 DQS Delay:
4077 23:03:27.374804 DQS0 = 0, DQS1 = 0
4078 23:03:27.378484 DQM Delay:
4079 23:03:27.378565 DQM0 = 40, DQM1 = 32
4080 23:03:27.378628 DQ Delay:
4081 23:03:27.382037 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4082 23:03:27.385101 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4083 23:03:27.388003 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4084 23:03:27.392084 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =41
4085 23:03:27.392165
4086 23:03:27.392229
4087 23:03:27.392289 ==
4088 23:03:27.394977 Dram Type= 6, Freq= 0, CH_0, rank 0
4089 23:03:27.401313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4090 23:03:27.401395 ==
4091 23:03:27.401460
4092 23:03:27.401519
4093 23:03:27.401575 TX Vref Scan disable
4094 23:03:27.405406 == TX Byte 0 ==
4095 23:03:27.409078 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4096 23:03:27.412070 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4097 23:03:27.415356 == TX Byte 1 ==
4098 23:03:27.418609 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4099 23:03:27.425472 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4100 23:03:27.425555 ==
4101 23:03:27.429056 Dram Type= 6, Freq= 0, CH_0, rank 0
4102 23:03:27.432304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4103 23:03:27.432387 ==
4104 23:03:27.432452
4105 23:03:27.432511
4106 23:03:27.435852 TX Vref Scan disable
4107 23:03:27.435933 == TX Byte 0 ==
4108 23:03:27.442523 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4109 23:03:27.445349 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4110 23:03:27.445431 == TX Byte 1 ==
4111 23:03:27.452285 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4112 23:03:27.456190 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4113 23:03:27.456274
4114 23:03:27.456338 [DATLAT]
4115 23:03:27.458799 Freq=600, CH0 RK0
4116 23:03:27.458921
4117 23:03:27.458987 DATLAT Default: 0x9
4118 23:03:27.462340 0, 0xFFFF, sum = 0
4119 23:03:27.462423 1, 0xFFFF, sum = 0
4120 23:03:27.465305 2, 0xFFFF, sum = 0
4121 23:03:27.465402 3, 0xFFFF, sum = 0
4122 23:03:27.469047 4, 0xFFFF, sum = 0
4123 23:03:27.469175 5, 0xFFFF, sum = 0
4124 23:03:27.472277 6, 0xFFFF, sum = 0
4125 23:03:27.476019 7, 0xFFFF, sum = 0
4126 23:03:27.476102 8, 0x0, sum = 1
4127 23:03:27.476168 9, 0x0, sum = 2
4128 23:03:27.479177 10, 0x0, sum = 3
4129 23:03:27.479259 11, 0x0, sum = 4
4130 23:03:27.482249 best_step = 9
4131 23:03:27.482371
4132 23:03:27.482439 ==
4133 23:03:27.485312 Dram Type= 6, Freq= 0, CH_0, rank 0
4134 23:03:27.488659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4135 23:03:27.488756 ==
4136 23:03:27.492635 RX Vref Scan: 1
4137 23:03:27.492736
4138 23:03:27.492801 RX Vref 0 -> 0, step: 1
4139 23:03:27.492861
4140 23:03:27.495742 RX Delay -195 -> 252, step: 8
4141 23:03:27.495811
4142 23:03:27.499114 Set Vref, RX VrefLevel [Byte0]: 53
4143 23:03:27.502096 [Byte1]: 50
4144 23:03:27.505950
4145 23:03:27.506029 Final RX Vref Byte 0 = 53 to rank0
4146 23:03:27.509764 Final RX Vref Byte 1 = 50 to rank0
4147 23:03:27.512971 Final RX Vref Byte 0 = 53 to rank1
4148 23:03:27.516043 Final RX Vref Byte 1 = 50 to rank1==
4149 23:03:27.519761 Dram Type= 6, Freq= 0, CH_0, rank 0
4150 23:03:27.526207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4151 23:03:27.526330 ==
4152 23:03:27.526428 DQS Delay:
4153 23:03:27.526495 DQS0 = 0, DQS1 = 0
4154 23:03:27.529675 DQM Delay:
4155 23:03:27.529756 DQM0 = 41, DQM1 = 34
4156 23:03:27.532773 DQ Delay:
4157 23:03:27.536381 DQ0 =44, DQ1 =40, DQ2 =36, DQ3 =40
4158 23:03:27.536492 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4159 23:03:27.539535 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =32
4160 23:03:27.543206 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4161 23:03:27.546325
4162 23:03:27.546405
4163 23:03:27.552861 [DQSOSCAuto] RK0, (LSB)MR18= 0x401f, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 397 ps
4164 23:03:27.556105 CH0 RK0: MR19=808, MR18=401F
4165 23:03:27.562995 CH0_RK0: MR19=0x808, MR18=0x401F, DQSOSC=397, MR23=63, INC=166, DEC=110
4166 23:03:27.563093
4167 23:03:27.566029 ----->DramcWriteLeveling(PI) begin...
4168 23:03:27.566100 ==
4169 23:03:27.569749 Dram Type= 6, Freq= 0, CH_0, rank 1
4170 23:03:27.573308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4171 23:03:27.573407 ==
4172 23:03:27.576759 Write leveling (Byte 0): 34 => 34
4173 23:03:27.579865 Write leveling (Byte 1): 31 => 31
4174 23:03:27.582763 DramcWriteLeveling(PI) end<-----
4175 23:03:27.582843
4176 23:03:27.582952 ==
4177 23:03:27.586334 Dram Type= 6, Freq= 0, CH_0, rank 1
4178 23:03:27.589876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4179 23:03:27.589956 ==
4180 23:03:27.592724 [Gating] SW mode calibration
4181 23:03:27.599314 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4182 23:03:27.606464 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4183 23:03:27.610035 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4184 23:03:27.613010 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4185 23:03:27.619530 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4186 23:03:27.622813 0 9 12 | B1->B0 | 3434 3030 | 1 1 | (1 0) (1 0)
4187 23:03:27.626276 0 9 16 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
4188 23:03:27.633308 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4189 23:03:27.636349 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4190 23:03:27.640251 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4191 23:03:27.643463 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4192 23:03:27.650012 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4193 23:03:27.653492 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4194 23:03:27.656717 0 10 12 | B1->B0 | 2323 3838 | 0 0 | (0 0) (0 0)
4195 23:03:27.663037 0 10 16 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
4196 23:03:27.666464 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4197 23:03:27.670059 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4198 23:03:27.676742 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4199 23:03:27.679669 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4200 23:03:27.683072 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4201 23:03:27.690357 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4202 23:03:27.692902 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4203 23:03:27.696189 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4204 23:03:27.703396 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 23:03:27.706453 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 23:03:27.709884 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 23:03:27.716358 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 23:03:27.719704 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 23:03:27.722968 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 23:03:27.729865 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 23:03:27.733286 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 23:03:27.736667 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 23:03:27.740102 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4214 23:03:27.746800 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4215 23:03:27.749970 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4216 23:03:27.753415 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4217 23:03:27.759495 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4218 23:03:27.763229 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4219 23:03:27.766208 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4220 23:03:27.769867 Total UI for P1: 0, mck2ui 16
4221 23:03:27.773053 best dqsien dly found for B0: ( 0, 13, 14)
4222 23:03:27.780021 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4223 23:03:27.780132 Total UI for P1: 0, mck2ui 16
4224 23:03:27.786724 best dqsien dly found for B1: ( 0, 13, 18)
4225 23:03:27.789695 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4226 23:03:27.793000 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4227 23:03:27.793080
4228 23:03:27.796517 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4229 23:03:27.799767 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4230 23:03:27.803673 [Gating] SW calibration Done
4231 23:03:27.803754 ==
4232 23:03:27.806441 Dram Type= 6, Freq= 0, CH_0, rank 1
4233 23:03:27.809957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4234 23:03:27.810039 ==
4235 23:03:27.813124 RX Vref Scan: 0
4236 23:03:27.813237
4237 23:03:27.813300 RX Vref 0 -> 0, step: 1
4238 23:03:27.813359
4239 23:03:27.816432 RX Delay -230 -> 252, step: 16
4240 23:03:27.819966 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4241 23:03:27.826710 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4242 23:03:27.830209 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4243 23:03:27.833128 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4244 23:03:27.836467 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4245 23:03:27.843569 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4246 23:03:27.846799 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4247 23:03:27.850004 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4248 23:03:27.853816 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4249 23:03:27.856925 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4250 23:03:27.863786 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4251 23:03:27.866631 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4252 23:03:27.870110 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4253 23:03:27.873759 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4254 23:03:27.879955 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4255 23:03:27.883815 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4256 23:03:27.883892 ==
4257 23:03:27.886824 Dram Type= 6, Freq= 0, CH_0, rank 1
4258 23:03:27.890256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4259 23:03:27.890359 ==
4260 23:03:27.893793 DQS Delay:
4261 23:03:27.893869 DQS0 = 0, DQS1 = 0
4262 23:03:27.893931 DQM Delay:
4263 23:03:27.897026 DQM0 = 41, DQM1 = 33
4264 23:03:27.897098 DQ Delay:
4265 23:03:27.900820 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4266 23:03:27.903397 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4267 23:03:27.907024 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4268 23:03:27.910418 DQ12 =33, DQ13 =41, DQ14 =49, DQ15 =41
4269 23:03:27.910490
4270 23:03:27.910551
4271 23:03:27.910609 ==
4272 23:03:27.913699 Dram Type= 6, Freq= 0, CH_0, rank 1
4273 23:03:27.917135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4274 23:03:27.920380 ==
4275 23:03:27.920454
4276 23:03:27.920517
4277 23:03:27.920575 TX Vref Scan disable
4278 23:03:27.923459 == TX Byte 0 ==
4279 23:03:27.927209 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4280 23:03:27.930761 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4281 23:03:27.933404 == TX Byte 1 ==
4282 23:03:27.936760 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4283 23:03:27.940071 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4284 23:03:27.943755 ==
4285 23:03:27.946821 Dram Type= 6, Freq= 0, CH_0, rank 1
4286 23:03:27.950118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4287 23:03:27.950214 ==
4288 23:03:27.950279
4289 23:03:27.950338
4290 23:03:27.953363 TX Vref Scan disable
4291 23:03:27.953442 == TX Byte 0 ==
4292 23:03:27.960223 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4293 23:03:27.963621 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4294 23:03:27.963704 == TX Byte 1 ==
4295 23:03:27.970185 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4296 23:03:27.973998 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4297 23:03:27.974074
4298 23:03:27.974138 [DATLAT]
4299 23:03:27.976813 Freq=600, CH0 RK1
4300 23:03:27.976887
4301 23:03:27.976948 DATLAT Default: 0x9
4302 23:03:27.980481 0, 0xFFFF, sum = 0
4303 23:03:27.980556 1, 0xFFFF, sum = 0
4304 23:03:27.983862 2, 0xFFFF, sum = 0
4305 23:03:27.983937 3, 0xFFFF, sum = 0
4306 23:03:27.986962 4, 0xFFFF, sum = 0
4307 23:03:27.987037 5, 0xFFFF, sum = 0
4308 23:03:27.990527 6, 0xFFFF, sum = 0
4309 23:03:27.990601 7, 0xFFFF, sum = 0
4310 23:03:27.993513 8, 0x0, sum = 1
4311 23:03:27.993587 9, 0x0, sum = 2
4312 23:03:27.997073 10, 0x0, sum = 3
4313 23:03:27.997146 11, 0x0, sum = 4
4314 23:03:28.000346 best_step = 9
4315 23:03:28.000417
4316 23:03:28.000479 ==
4317 23:03:28.003800 Dram Type= 6, Freq= 0, CH_0, rank 1
4318 23:03:28.007217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4319 23:03:28.007297 ==
4320 23:03:28.010721 RX Vref Scan: 0
4321 23:03:28.010799
4322 23:03:28.010867 RX Vref 0 -> 0, step: 1
4323 23:03:28.010928
4324 23:03:28.013445 RX Delay -195 -> 252, step: 8
4325 23:03:28.021023 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4326 23:03:28.024194 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4327 23:03:28.027191 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4328 23:03:28.030932 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4329 23:03:28.037392 iDelay=205, Bit 4, Center 36 (-115 ~ 188) 304
4330 23:03:28.040645 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4331 23:03:28.044128 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4332 23:03:28.047281 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4333 23:03:28.050417 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4334 23:03:28.057667 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4335 23:03:28.060689 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4336 23:03:28.064119 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4337 23:03:28.067186 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4338 23:03:28.073970 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4339 23:03:28.077585 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4340 23:03:28.080656 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4341 23:03:28.080739 ==
4342 23:03:28.084054 Dram Type= 6, Freq= 0, CH_0, rank 1
4343 23:03:28.087359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4344 23:03:28.087442 ==
4345 23:03:28.090685 DQS Delay:
4346 23:03:28.090766 DQS0 = 0, DQS1 = 0
4347 23:03:28.093859 DQM Delay:
4348 23:03:28.093940 DQM0 = 40, DQM1 = 33
4349 23:03:28.094005 DQ Delay:
4350 23:03:28.097342 DQ0 =44, DQ1 =40, DQ2 =36, DQ3 =40
4351 23:03:28.100853 DQ4 =36, DQ5 =28, DQ6 =48, DQ7 =48
4352 23:03:28.104199 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =24
4353 23:03:28.107160 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =40
4354 23:03:28.107236
4355 23:03:28.107300
4356 23:03:28.117549 [DQSOSCAuto] RK1, (LSB)MR18= 0x482a, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps
4357 23:03:28.120713 CH0 RK1: MR19=808, MR18=482A
4358 23:03:28.127697 CH0_RK1: MR19=0x808, MR18=0x482A, DQSOSC=396, MR23=63, INC=167, DEC=111
4359 23:03:28.127785 [RxdqsGatingPostProcess] freq 600
4360 23:03:28.134532 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4361 23:03:28.137279 Pre-setting of DQS Precalculation
4362 23:03:28.140465 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4363 23:03:28.143847 ==
4364 23:03:28.143930 Dram Type= 6, Freq= 0, CH_1, rank 0
4365 23:03:28.150434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4366 23:03:28.150516 ==
4367 23:03:28.153782 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4368 23:03:28.160573 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4369 23:03:28.164250 [CA 0] Center 35 (5~65) winsize 61
4370 23:03:28.167498 [CA 1] Center 35 (5~66) winsize 62
4371 23:03:28.170815 [CA 2] Center 34 (4~65) winsize 62
4372 23:03:28.174256 [CA 3] Center 33 (3~64) winsize 62
4373 23:03:28.177698 [CA 4] Center 34 (3~65) winsize 63
4374 23:03:28.180980 [CA 5] Center 33 (2~64) winsize 63
4375 23:03:28.181053
4376 23:03:28.184152 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4377 23:03:28.184226
4378 23:03:28.187875 [CATrainingPosCal] consider 1 rank data
4379 23:03:28.190638 u2DelayCellTimex100 = 270/100 ps
4380 23:03:28.194146 CA0 delay=35 (5~65),Diff = 2 PI (19 cell)
4381 23:03:28.197358 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4382 23:03:28.204362 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4383 23:03:28.207766 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4384 23:03:28.211212 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4385 23:03:28.214350 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4386 23:03:28.214455
4387 23:03:28.217762 CA PerBit enable=1, Macro0, CA PI delay=33
4388 23:03:28.217861
4389 23:03:28.221258 [CBTSetCACLKResult] CA Dly = 33
4390 23:03:28.221356 CS Dly: 5 (0~36)
4391 23:03:28.221455 ==
4392 23:03:28.224208 Dram Type= 6, Freq= 0, CH_1, rank 1
4393 23:03:28.230961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4394 23:03:28.231063 ==
4395 23:03:28.234609 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4396 23:03:28.241266 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4397 23:03:28.244494 [CA 0] Center 35 (5~66) winsize 62
4398 23:03:28.248415 [CA 1] Center 36 (6~66) winsize 61
4399 23:03:28.251819 [CA 2] Center 34 (4~65) winsize 62
4400 23:03:28.254370 [CA 3] Center 34 (3~65) winsize 63
4401 23:03:28.257864 [CA 4] Center 34 (4~65) winsize 62
4402 23:03:28.261200 [CA 5] Center 33 (3~64) winsize 62
4403 23:03:28.261282
4404 23:03:28.265110 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4405 23:03:28.265192
4406 23:03:28.267949 [CATrainingPosCal] consider 2 rank data
4407 23:03:28.271094 u2DelayCellTimex100 = 270/100 ps
4408 23:03:28.274710 CA0 delay=35 (5~65),Diff = 2 PI (19 cell)
4409 23:03:28.277764 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4410 23:03:28.281119 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4411 23:03:28.287967 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4412 23:03:28.290958 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4413 23:03:28.294601 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4414 23:03:28.294681
4415 23:03:28.297778 CA PerBit enable=1, Macro0, CA PI delay=33
4416 23:03:28.297858
4417 23:03:28.301361 [CBTSetCACLKResult] CA Dly = 33
4418 23:03:28.301441 CS Dly: 5 (0~37)
4419 23:03:28.301505
4420 23:03:28.304793 ----->DramcWriteLeveling(PI) begin...
4421 23:03:28.304876 ==
4422 23:03:28.308204 Dram Type= 6, Freq= 0, CH_1, rank 0
4423 23:03:28.314458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4424 23:03:28.314539 ==
4425 23:03:28.317886 Write leveling (Byte 0): 29 => 29
4426 23:03:28.321706 Write leveling (Byte 1): 32 => 32
4427 23:03:28.321787 DramcWriteLeveling(PI) end<-----
4428 23:03:28.321851
4429 23:03:28.324477 ==
4430 23:03:28.327730 Dram Type= 6, Freq= 0, CH_1, rank 0
4431 23:03:28.331286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4432 23:03:28.331363 ==
4433 23:03:28.334722 [Gating] SW mode calibration
4434 23:03:28.341331 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4435 23:03:28.344745 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4436 23:03:28.351594 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4437 23:03:28.354728 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4438 23:03:28.357907 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4439 23:03:28.364794 0 9 12 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 1)
4440 23:03:28.368416 0 9 16 | B1->B0 | 2b2b 2a2a | 0 0 | (1 1) (1 1)
4441 23:03:28.371554 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4442 23:03:28.375301 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4443 23:03:28.381677 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4444 23:03:28.385307 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4445 23:03:28.388202 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4446 23:03:28.395209 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4447 23:03:28.398411 0 10 12 | B1->B0 | 2626 2b2b | 0 1 | (0 0) (0 0)
4448 23:03:28.401397 0 10 16 | B1->B0 | 4141 4242 | 0 1 | (0 0) (0 0)
4449 23:03:28.408093 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4450 23:03:28.411460 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4451 23:03:28.415224 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4452 23:03:28.421761 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4453 23:03:28.425028 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4454 23:03:28.428030 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4455 23:03:28.434872 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4456 23:03:28.438143 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4457 23:03:28.441652 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 23:03:28.448663 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 23:03:28.452186 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 23:03:28.455065 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 23:03:28.458774 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 23:03:28.465055 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 23:03:28.468440 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 23:03:28.472165 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 23:03:28.478518 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 23:03:28.482061 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 23:03:28.485688 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 23:03:28.491700 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 23:03:28.495393 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 23:03:28.498650 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 23:03:28.505436 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4472 23:03:28.508640 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4473 23:03:28.511851 Total UI for P1: 0, mck2ui 16
4474 23:03:28.515121 best dqsien dly found for B1: ( 0, 13, 12)
4475 23:03:28.518532 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4476 23:03:28.521981 Total UI for P1: 0, mck2ui 16
4477 23:03:28.525266 best dqsien dly found for B0: ( 0, 13, 14)
4478 23:03:28.528934 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4479 23:03:28.531695 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4480 23:03:28.531776
4481 23:03:28.535521 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4482 23:03:28.542063 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4483 23:03:28.542145 [Gating] SW calibration Done
4484 23:03:28.542208 ==
4485 23:03:28.545392 Dram Type= 6, Freq= 0, CH_1, rank 0
4486 23:03:28.551894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4487 23:03:28.551976 ==
4488 23:03:28.552039 RX Vref Scan: 0
4489 23:03:28.552098
4490 23:03:28.555344 RX Vref 0 -> 0, step: 1
4491 23:03:28.555424
4492 23:03:28.558801 RX Delay -230 -> 252, step: 16
4493 23:03:28.562272 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4494 23:03:28.565244 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4495 23:03:28.568726 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4496 23:03:28.575749 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4497 23:03:28.579283 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4498 23:03:28.582190 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4499 23:03:28.585640 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4500 23:03:28.592575 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4501 23:03:28.595673 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4502 23:03:28.599276 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4503 23:03:28.602567 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4504 23:03:28.605486 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4505 23:03:28.612474 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4506 23:03:28.615677 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4507 23:03:28.619320 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4508 23:03:28.622130 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4509 23:03:28.622214 ==
4510 23:03:28.625507 Dram Type= 6, Freq= 0, CH_1, rank 0
4511 23:03:28.632366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4512 23:03:28.632444 ==
4513 23:03:28.632516 DQS Delay:
4514 23:03:28.635825 DQS0 = 0, DQS1 = 0
4515 23:03:28.635911 DQM Delay:
4516 23:03:28.635976 DQM0 = 44, DQM1 = 33
4517 23:03:28.639432 DQ Delay:
4518 23:03:28.642020 DQ0 =49, DQ1 =41, DQ2 =25, DQ3 =41
4519 23:03:28.645382 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4520 23:03:28.649178 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =33
4521 23:03:28.652369 DQ12 =49, DQ13 =41, DQ14 =33, DQ15 =33
4522 23:03:28.652449
4523 23:03:28.652513
4524 23:03:28.652572 ==
4525 23:03:28.655539 Dram Type= 6, Freq= 0, CH_1, rank 0
4526 23:03:28.658947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4527 23:03:28.659030 ==
4528 23:03:28.659094
4529 23:03:28.659153
4530 23:03:28.662351 TX Vref Scan disable
4531 23:03:28.662432 == TX Byte 0 ==
4532 23:03:28.669143 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4533 23:03:28.672945 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4534 23:03:28.673025 == TX Byte 1 ==
4535 23:03:28.678979 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4536 23:03:28.682424 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4537 23:03:28.682530 ==
4538 23:03:28.685655 Dram Type= 6, Freq= 0, CH_1, rank 0
4539 23:03:28.689414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4540 23:03:28.689495 ==
4541 23:03:28.689559
4542 23:03:28.689617
4543 23:03:28.693111 TX Vref Scan disable
4544 23:03:28.696264 == TX Byte 0 ==
4545 23:03:28.699340 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4546 23:03:28.702871 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4547 23:03:28.705923 == TX Byte 1 ==
4548 23:03:28.708926 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4549 23:03:28.712363 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4550 23:03:28.712459
4551 23:03:28.715758 [DATLAT]
4552 23:03:28.715838 Freq=600, CH1 RK0
4553 23:03:28.715903
4554 23:03:28.719168 DATLAT Default: 0x9
4555 23:03:28.719239 0, 0xFFFF, sum = 0
4556 23:03:28.722378 1, 0xFFFF, sum = 0
4557 23:03:28.722447 2, 0xFFFF, sum = 0
4558 23:03:28.725740 3, 0xFFFF, sum = 0
4559 23:03:28.725810 4, 0xFFFF, sum = 0
4560 23:03:28.729646 5, 0xFFFF, sum = 0
4561 23:03:28.729729 6, 0xFFFF, sum = 0
4562 23:03:28.732604 7, 0xFFFF, sum = 0
4563 23:03:28.732693 8, 0x0, sum = 1
4564 23:03:28.736145 9, 0x0, sum = 2
4565 23:03:28.736227 10, 0x0, sum = 3
4566 23:03:28.739154 11, 0x0, sum = 4
4567 23:03:28.739236 best_step = 9
4568 23:03:28.739299
4569 23:03:28.739359 ==
4570 23:03:28.742376 Dram Type= 6, Freq= 0, CH_1, rank 0
4571 23:03:28.749406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4572 23:03:28.749486 ==
4573 23:03:28.749551 RX Vref Scan: 1
4574 23:03:28.749610
4575 23:03:28.752470 RX Vref 0 -> 0, step: 1
4576 23:03:28.752550
4577 23:03:28.756250 RX Delay -195 -> 252, step: 8
4578 23:03:28.756331
4579 23:03:28.759220 Set Vref, RX VrefLevel [Byte0]: 60
4580 23:03:28.762774 [Byte1]: 51
4581 23:03:28.762883
4582 23:03:28.765707 Final RX Vref Byte 0 = 60 to rank0
4583 23:03:28.769166 Final RX Vref Byte 1 = 51 to rank0
4584 23:03:28.772800 Final RX Vref Byte 0 = 60 to rank1
4585 23:03:28.776023 Final RX Vref Byte 1 = 51 to rank1==
4586 23:03:28.779730 Dram Type= 6, Freq= 0, CH_1, rank 0
4587 23:03:28.782342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4588 23:03:28.782423 ==
4589 23:03:28.785729 DQS Delay:
4590 23:03:28.785812 DQS0 = 0, DQS1 = 0
4591 23:03:28.785875 DQM Delay:
4592 23:03:28.789282 DQM0 = 40, DQM1 = 33
4593 23:03:28.789362 DQ Delay:
4594 23:03:28.792650 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4595 23:03:28.795728 DQ4 =36, DQ5 =48, DQ6 =52, DQ7 =36
4596 23:03:28.798909 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =28
4597 23:03:28.802638 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4598 23:03:28.802718
4599 23:03:28.802781
4600 23:03:28.812908 [DQSOSCAuto] RK0, (LSB)MR18= 0x480e, (MSB)MR19= 0x808, tDQSOscB0 = 407 ps tDQSOscB1 = 396 ps
4601 23:03:28.812989 CH1 RK0: MR19=808, MR18=480E
4602 23:03:28.819525 CH1_RK0: MR19=0x808, MR18=0x480E, DQSOSC=396, MR23=63, INC=167, DEC=111
4603 23:03:28.819606
4604 23:03:28.822487 ----->DramcWriteLeveling(PI) begin...
4605 23:03:28.822568 ==
4606 23:03:28.826319 Dram Type= 6, Freq= 0, CH_1, rank 1
4607 23:03:28.832586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4608 23:03:28.832669 ==
4609 23:03:28.836218 Write leveling (Byte 0): 29 => 29
4610 23:03:28.839095 Write leveling (Byte 1): 30 => 30
4611 23:03:28.839176 DramcWriteLeveling(PI) end<-----
4612 23:03:28.839241
4613 23:03:28.842477 ==
4614 23:03:28.845972 Dram Type= 6, Freq= 0, CH_1, rank 1
4615 23:03:28.849386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4616 23:03:28.849468 ==
4617 23:03:28.852577 [Gating] SW mode calibration
4618 23:03:28.859203 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4619 23:03:28.862427 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4620 23:03:28.869710 0 9 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4621 23:03:28.872429 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4622 23:03:28.875802 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4623 23:03:28.882771 0 9 12 | B1->B0 | 3131 2929 | 1 1 | (1 1) (1 0)
4624 23:03:28.886255 0 9 16 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
4625 23:03:28.889303 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4626 23:03:28.895834 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4627 23:03:28.899654 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4628 23:03:28.902794 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4629 23:03:28.905813 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4630 23:03:28.912669 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4631 23:03:28.916284 0 10 12 | B1->B0 | 3434 4646 | 0 0 | (1 1) (0 0)
4632 23:03:28.919260 0 10 16 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
4633 23:03:28.926022 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4634 23:03:28.929291 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4635 23:03:28.933124 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4636 23:03:28.939161 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4637 23:03:28.942533 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4638 23:03:28.946144 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4639 23:03:28.952919 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4640 23:03:28.956174 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 23:03:28.959648 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 23:03:28.966216 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 23:03:28.969304 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 23:03:28.972729 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 23:03:28.979366 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 23:03:28.982680 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 23:03:28.986189 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 23:03:28.992555 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 23:03:28.995862 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 23:03:28.999664 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 23:03:29.003083 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4652 23:03:29.009294 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4653 23:03:29.012873 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4654 23:03:29.016207 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4655 23:03:29.022457 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4656 23:03:29.026106 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4657 23:03:29.029516 Total UI for P1: 0, mck2ui 16
4658 23:03:29.032468 best dqsien dly found for B0: ( 0, 13, 10)
4659 23:03:29.035883 Total UI for P1: 0, mck2ui 16
4660 23:03:29.039388 best dqsien dly found for B1: ( 0, 13, 14)
4661 23:03:29.042550 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4662 23:03:29.045952 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4663 23:03:29.046034
4664 23:03:29.049327 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4665 23:03:29.052780 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4666 23:03:29.056123 [Gating] SW calibration Done
4667 23:03:29.056213 ==
4668 23:03:29.059602 Dram Type= 6, Freq= 0, CH_1, rank 1
4669 23:03:29.066332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4670 23:03:29.066419 ==
4671 23:03:29.066486 RX Vref Scan: 0
4672 23:03:29.066546
4673 23:03:29.069445 RX Vref 0 -> 0, step: 1
4674 23:03:29.069526
4675 23:03:29.072624 RX Delay -230 -> 252, step: 16
4676 23:03:29.076072 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4677 23:03:29.079362 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4678 23:03:29.082749 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4679 23:03:29.089572 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4680 23:03:29.092477 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4681 23:03:29.095903 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4682 23:03:29.099194 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4683 23:03:29.102771 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4684 23:03:29.109278 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4685 23:03:29.112542 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4686 23:03:29.115806 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4687 23:03:29.119489 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4688 23:03:29.122817 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4689 23:03:29.129360 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4690 23:03:29.132677 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4691 23:03:29.136225 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4692 23:03:29.136309 ==
4693 23:03:29.139556 Dram Type= 6, Freq= 0, CH_1, rank 1
4694 23:03:29.143367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4695 23:03:29.146250 ==
4696 23:03:29.146347 DQS Delay:
4697 23:03:29.146441 DQS0 = 0, DQS1 = 0
4698 23:03:29.149728 DQM Delay:
4699 23:03:29.149831 DQM0 = 40, DQM1 = 36
4700 23:03:29.153066 DQ Delay:
4701 23:03:29.153168 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =41
4702 23:03:29.156521 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =33
4703 23:03:29.159448 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4704 23:03:29.162938 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =41
4705 23:03:29.163019
4706 23:03:29.166618
4707 23:03:29.166715 ==
4708 23:03:29.169909 Dram Type= 6, Freq= 0, CH_1, rank 1
4709 23:03:29.173235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4710 23:03:29.173340 ==
4711 23:03:29.173478
4712 23:03:29.173578
4713 23:03:29.176486 TX Vref Scan disable
4714 23:03:29.176582 == TX Byte 0 ==
4715 23:03:29.182771 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4716 23:03:29.186828 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4717 23:03:29.186969 == TX Byte 1 ==
4718 23:03:29.192982 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4719 23:03:29.196430 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4720 23:03:29.196517 ==
4721 23:03:29.199759 Dram Type= 6, Freq= 0, CH_1, rank 1
4722 23:03:29.203469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4723 23:03:29.203573 ==
4724 23:03:29.203689
4725 23:03:29.203791
4726 23:03:29.206337 TX Vref Scan disable
4727 23:03:29.209784 == TX Byte 0 ==
4728 23:03:29.213250 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4729 23:03:29.216242 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4730 23:03:29.219615 == TX Byte 1 ==
4731 23:03:29.223459 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4732 23:03:29.226352 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4733 23:03:29.226426
4734 23:03:29.229727 [DATLAT]
4735 23:03:29.229838 Freq=600, CH1 RK1
4736 23:03:29.229930
4737 23:03:29.233457 DATLAT Default: 0x9
4738 23:03:29.233552 0, 0xFFFF, sum = 0
4739 23:03:29.236723 1, 0xFFFF, sum = 0
4740 23:03:29.236819 2, 0xFFFF, sum = 0
4741 23:03:29.239940 3, 0xFFFF, sum = 0
4742 23:03:29.240037 4, 0xFFFF, sum = 0
4743 23:03:29.243000 5, 0xFFFF, sum = 0
4744 23:03:29.243070 6, 0xFFFF, sum = 0
4745 23:03:29.246285 7, 0xFFFF, sum = 0
4746 23:03:29.246360 8, 0x0, sum = 1
4747 23:03:29.250141 9, 0x0, sum = 2
4748 23:03:29.250216 10, 0x0, sum = 3
4749 23:03:29.253120 11, 0x0, sum = 4
4750 23:03:29.253221 best_step = 9
4751 23:03:29.253309
4752 23:03:29.253394 ==
4753 23:03:29.256787 Dram Type= 6, Freq= 0, CH_1, rank 1
4754 23:03:29.259643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4755 23:03:29.259747 ==
4756 23:03:29.263100 RX Vref Scan: 0
4757 23:03:29.263179
4758 23:03:29.266425 RX Vref 0 -> 0, step: 1
4759 23:03:29.266523
4760 23:03:29.269808 RX Delay -179 -> 252, step: 8
4761 23:03:29.272649 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4762 23:03:29.276197 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4763 23:03:29.283056 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4764 23:03:29.286452 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4765 23:03:29.289548 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4766 23:03:29.293392 iDelay=205, Bit 5, Center 52 (-99 ~ 204) 304
4767 23:03:29.296564 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4768 23:03:29.302823 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4769 23:03:29.306677 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4770 23:03:29.309835 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4771 23:03:29.313137 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4772 23:03:29.319529 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4773 23:03:29.323246 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4774 23:03:29.326374 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4775 23:03:29.329532 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4776 23:03:29.336393 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4777 23:03:29.336484 ==
4778 23:03:29.339314 Dram Type= 6, Freq= 0, CH_1, rank 1
4779 23:03:29.343167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4780 23:03:29.343239 ==
4781 23:03:29.343299 DQS Delay:
4782 23:03:29.346417 DQS0 = 0, DQS1 = 0
4783 23:03:29.346485 DQM Delay:
4784 23:03:29.349682 DQM0 = 38, DQM1 = 33
4785 23:03:29.349752 DQ Delay:
4786 23:03:29.353221 DQ0 =44, DQ1 =32, DQ2 =24, DQ3 =36
4787 23:03:29.356359 DQ4 =40, DQ5 =52, DQ6 =48, DQ7 =32
4788 23:03:29.359689 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =24
4789 23:03:29.362768 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4790 23:03:29.362906
4791 23:03:29.362972
4792 23:03:29.369495 [DQSOSCAuto] RK1, (LSB)MR18= 0x3c4b, (MSB)MR19= 0x808, tDQSOscB0 = 395 ps tDQSOscB1 = 398 ps
4793 23:03:29.372924 CH1 RK1: MR19=808, MR18=3C4B
4794 23:03:29.379951 CH1_RK1: MR19=0x808, MR18=0x3C4B, DQSOSC=395, MR23=63, INC=168, DEC=112
4795 23:03:29.382810 [RxdqsGatingPostProcess] freq 600
4796 23:03:29.389800 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4797 23:03:29.389882 Pre-setting of DQS Precalculation
4798 23:03:29.396379 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4799 23:03:29.402991 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4800 23:03:29.409877 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4801 23:03:29.409990
4802 23:03:29.410055
4803 23:03:29.412869 [Calibration Summary] 1200 Mbps
4804 23:03:29.412967 CH 0, Rank 0
4805 23:03:29.416410 SW Impedance : PASS
4806 23:03:29.419875 DUTY Scan : NO K
4807 23:03:29.419948 ZQ Calibration : PASS
4808 23:03:29.423298 Jitter Meter : NO K
4809 23:03:29.426633 CBT Training : PASS
4810 23:03:29.426706 Write leveling : PASS
4811 23:03:29.429634 RX DQS gating : PASS
4812 23:03:29.433008 RX DQ/DQS(RDDQC) : PASS
4813 23:03:29.433108 TX DQ/DQS : PASS
4814 23:03:29.436366 RX DATLAT : PASS
4815 23:03:29.440068 RX DQ/DQS(Engine): PASS
4816 23:03:29.440141 TX OE : NO K
4817 23:03:29.442786 All Pass.
4818 23:03:29.442871
4819 23:03:29.442981 CH 0, Rank 1
4820 23:03:29.446755 SW Impedance : PASS
4821 23:03:29.446886 DUTY Scan : NO K
4822 23:03:29.449708 ZQ Calibration : PASS
4823 23:03:29.453232 Jitter Meter : NO K
4824 23:03:29.453320 CBT Training : PASS
4825 23:03:29.456594 Write leveling : PASS
4826 23:03:29.456665 RX DQS gating : PASS
4827 23:03:29.459836 RX DQ/DQS(RDDQC) : PASS
4828 23:03:29.463163 TX DQ/DQS : PASS
4829 23:03:29.463240 RX DATLAT : PASS
4830 23:03:29.466795 RX DQ/DQS(Engine): PASS
4831 23:03:29.470140 TX OE : NO K
4832 23:03:29.470213 All Pass.
4833 23:03:29.470299
4834 23:03:29.470372 CH 1, Rank 0
4835 23:03:29.473472 SW Impedance : PASS
4836 23:03:29.476584 DUTY Scan : NO K
4837 23:03:29.476659 ZQ Calibration : PASS
4838 23:03:29.480145 Jitter Meter : NO K
4839 23:03:29.483349 CBT Training : PASS
4840 23:03:29.483422 Write leveling : PASS
4841 23:03:29.486546 RX DQS gating : PASS
4842 23:03:29.486622 RX DQ/DQS(RDDQC) : PASS
4843 23:03:29.490141 TX DQ/DQS : PASS
4844 23:03:29.493406 RX DATLAT : PASS
4845 23:03:29.493477 RX DQ/DQS(Engine): PASS
4846 23:03:29.496322 TX OE : NO K
4847 23:03:29.496393 All Pass.
4848 23:03:29.496479
4849 23:03:29.499943 CH 1, Rank 1
4850 23:03:29.500011 SW Impedance : PASS
4851 23:03:29.503211 DUTY Scan : NO K
4852 23:03:29.506383 ZQ Calibration : PASS
4853 23:03:29.506457 Jitter Meter : NO K
4854 23:03:29.509838 CBT Training : PASS
4855 23:03:29.513066 Write leveling : PASS
4856 23:03:29.513164 RX DQS gating : PASS
4857 23:03:29.516669 RX DQ/DQS(RDDQC) : PASS
4858 23:03:29.520129 TX DQ/DQS : PASS
4859 23:03:29.520229 RX DATLAT : PASS
4860 23:03:29.523700 RX DQ/DQS(Engine): PASS
4861 23:03:29.526749 TX OE : NO K
4862 23:03:29.526848 All Pass.
4863 23:03:29.526981
4864 23:03:29.527068 DramC Write-DBI off
4865 23:03:29.530142 PER_BANK_REFRESH: Hybrid Mode
4866 23:03:29.533663 TX_TRACKING: ON
4867 23:03:29.540236 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4868 23:03:29.543392 [FAST_K] Save calibration result to emmc
4869 23:03:29.546802 dramc_set_vcore_voltage set vcore to 662500
4870 23:03:29.549932 Read voltage for 933, 3
4871 23:03:29.550008 Vio18 = 0
4872 23:03:29.553930 Vcore = 662500
4873 23:03:29.554029 Vdram = 0
4874 23:03:29.554119 Vddq = 0
4875 23:03:29.556587 Vmddr = 0
4876 23:03:29.560335 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4877 23:03:29.566969 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4878 23:03:29.567047 MEM_TYPE=3, freq_sel=17
4879 23:03:29.570312 sv_algorithm_assistance_LP4_1600
4880 23:03:29.576732 ============ PULL DRAM RESETB DOWN ============
4881 23:03:29.580494 ========== PULL DRAM RESETB DOWN end =========
4882 23:03:29.583529 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4883 23:03:29.587088 ===================================
4884 23:03:29.590250 LPDDR4 DRAM CONFIGURATION
4885 23:03:29.593910 ===================================
4886 23:03:29.594022 EX_ROW_EN[0] = 0x0
4887 23:03:29.596784 EX_ROW_EN[1] = 0x0
4888 23:03:29.600241 LP4Y_EN = 0x0
4889 23:03:29.600318 WORK_FSP = 0x0
4890 23:03:29.603854 WL = 0x3
4891 23:03:29.603928 RL = 0x3
4892 23:03:29.606678 BL = 0x2
4893 23:03:29.606749 RPST = 0x0
4894 23:03:29.610589 RD_PRE = 0x0
4895 23:03:29.610663 WR_PRE = 0x1
4896 23:03:29.613610 WR_PST = 0x0
4897 23:03:29.613682 DBI_WR = 0x0
4898 23:03:29.616832 DBI_RD = 0x0
4899 23:03:29.616967 OTF = 0x1
4900 23:03:29.620524 ===================================
4901 23:03:29.623462 ===================================
4902 23:03:29.626836 ANA top config
4903 23:03:29.630489 ===================================
4904 23:03:29.630563 DLL_ASYNC_EN = 0
4905 23:03:29.633860 ALL_SLAVE_EN = 1
4906 23:03:29.636774 NEW_RANK_MODE = 1
4907 23:03:29.640514 DLL_IDLE_MODE = 1
4908 23:03:29.640599 LP45_APHY_COMB_EN = 1
4909 23:03:29.643556 TX_ODT_DIS = 1
4910 23:03:29.647107 NEW_8X_MODE = 1
4911 23:03:29.650751 ===================================
4912 23:03:29.653882 ===================================
4913 23:03:29.656830 data_rate = 1866
4914 23:03:29.660942 CKR = 1
4915 23:03:29.663569 DQ_P2S_RATIO = 8
4916 23:03:29.663652 ===================================
4917 23:03:29.667474 CA_P2S_RATIO = 8
4918 23:03:29.670655 DQ_CA_OPEN = 0
4919 23:03:29.673951 DQ_SEMI_OPEN = 0
4920 23:03:29.676917 CA_SEMI_OPEN = 0
4921 23:03:29.680767 CA_FULL_RATE = 0
4922 23:03:29.680849 DQ_CKDIV4_EN = 1
4923 23:03:29.683884 CA_CKDIV4_EN = 1
4924 23:03:29.687608 CA_PREDIV_EN = 0
4925 23:03:29.690304 PH8_DLY = 0
4926 23:03:29.694190 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4927 23:03:29.697269 DQ_AAMCK_DIV = 4
4928 23:03:29.697353 CA_AAMCK_DIV = 4
4929 23:03:29.700949 CA_ADMCK_DIV = 4
4930 23:03:29.703857 DQ_TRACK_CA_EN = 0
4931 23:03:29.707636 CA_PICK = 933
4932 23:03:29.710364 CA_MCKIO = 933
4933 23:03:29.713778 MCKIO_SEMI = 0
4934 23:03:29.717251 PLL_FREQ = 3732
4935 23:03:29.717333 DQ_UI_PI_RATIO = 32
4936 23:03:29.720658 CA_UI_PI_RATIO = 0
4937 23:03:29.723746 ===================================
4938 23:03:29.727151 ===================================
4939 23:03:29.730563 memory_type:LPDDR4
4940 23:03:29.733763 GP_NUM : 10
4941 23:03:29.733845 SRAM_EN : 1
4942 23:03:29.737694 MD32_EN : 0
4943 23:03:29.740564 ===================================
4944 23:03:29.740646 [ANA_INIT] >>>>>>>>>>>>>>
4945 23:03:29.744086 <<<<<< [CONFIGURE PHASE]: ANA_TX
4946 23:03:29.746968 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4947 23:03:29.750638 ===================================
4948 23:03:29.754169 data_rate = 1866,PCW = 0X8f00
4949 23:03:29.757263 ===================================
4950 23:03:29.760583 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4951 23:03:29.767424 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4952 23:03:29.771072 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4953 23:03:29.777405 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4954 23:03:29.780685 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4955 23:03:29.783814 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4956 23:03:29.787008 [ANA_INIT] flow start
4957 23:03:29.787082 [ANA_INIT] PLL >>>>>>>>
4958 23:03:29.790268 [ANA_INIT] PLL <<<<<<<<
4959 23:03:29.794122 [ANA_INIT] MIDPI >>>>>>>>
4960 23:03:29.794203 [ANA_INIT] MIDPI <<<<<<<<
4961 23:03:29.797510 [ANA_INIT] DLL >>>>>>>>
4962 23:03:29.800240 [ANA_INIT] flow end
4963 23:03:29.804101 ============ LP4 DIFF to SE enter ============
4964 23:03:29.806998 ============ LP4 DIFF to SE exit ============
4965 23:03:29.810447 [ANA_INIT] <<<<<<<<<<<<<
4966 23:03:29.813814 [Flow] Enable top DCM control >>>>>
4967 23:03:29.817398 [Flow] Enable top DCM control <<<<<
4968 23:03:29.820937 Enable DLL master slave shuffle
4969 23:03:29.823993 ==============================================================
4970 23:03:29.827175 Gating Mode config
4971 23:03:29.830546 ==============================================================
4972 23:03:29.833916 Config description:
4973 23:03:29.843694 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4974 23:03:29.850534 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4975 23:03:29.853606 SELPH_MODE 0: By rank 1: By Phase
4976 23:03:29.860473 ==============================================================
4977 23:03:29.863866 GAT_TRACK_EN = 1
4978 23:03:29.867680 RX_GATING_MODE = 2
4979 23:03:29.870224 RX_GATING_TRACK_MODE = 2
4980 23:03:29.874172 SELPH_MODE = 1
4981 23:03:29.874281 PICG_EARLY_EN = 1
4982 23:03:29.877111 VALID_LAT_VALUE = 1
4983 23:03:29.884209 ==============================================================
4984 23:03:29.887362 Enter into Gating configuration >>>>
4985 23:03:29.890198 Exit from Gating configuration <<<<
4986 23:03:29.894053 Enter into DVFS_PRE_config >>>>>
4987 23:03:29.904304 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4988 23:03:29.907337 Exit from DVFS_PRE_config <<<<<
4989 23:03:29.910837 Enter into PICG configuration >>>>
4990 23:03:29.913582 Exit from PICG configuration <<<<
4991 23:03:29.917424 [RX_INPUT] configuration >>>>>
4992 23:03:29.920683 [RX_INPUT] configuration <<<<<
4993 23:03:29.923739 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4994 23:03:29.930341 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4995 23:03:29.937281 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4996 23:03:29.943977 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4997 23:03:29.947139 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4998 23:03:29.954096 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4999 23:03:29.957385 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5000 23:03:29.964145 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5001 23:03:29.967395 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5002 23:03:29.970664 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5003 23:03:29.974023 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5004 23:03:29.980806 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5005 23:03:29.984250 ===================================
5006 23:03:29.984325 LPDDR4 DRAM CONFIGURATION
5007 23:03:29.987729 ===================================
5008 23:03:29.991134 EX_ROW_EN[0] = 0x0
5009 23:03:29.994169 EX_ROW_EN[1] = 0x0
5010 23:03:29.994241 LP4Y_EN = 0x0
5011 23:03:29.997741 WORK_FSP = 0x0
5012 23:03:29.997811 WL = 0x3
5013 23:03:30.001101 RL = 0x3
5014 23:03:30.001171 BL = 0x2
5015 23:03:30.004205 RPST = 0x0
5016 23:03:30.004275 RD_PRE = 0x0
5017 23:03:30.007760 WR_PRE = 0x1
5018 23:03:30.007830 WR_PST = 0x0
5019 23:03:30.010896 DBI_WR = 0x0
5020 23:03:30.010967 DBI_RD = 0x0
5021 23:03:30.014262 OTF = 0x1
5022 23:03:30.017700 ===================================
5023 23:03:30.020908 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5024 23:03:30.024616 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5025 23:03:30.031552 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5026 23:03:30.034119 ===================================
5027 23:03:30.034217 LPDDR4 DRAM CONFIGURATION
5028 23:03:30.037749 ===================================
5029 23:03:30.041361 EX_ROW_EN[0] = 0x10
5030 23:03:30.041459 EX_ROW_EN[1] = 0x0
5031 23:03:30.044476 LP4Y_EN = 0x0
5032 23:03:30.044573 WORK_FSP = 0x0
5033 23:03:30.047951 WL = 0x3
5034 23:03:30.048047 RL = 0x3
5035 23:03:30.051328 BL = 0x2
5036 23:03:30.054320 RPST = 0x0
5037 23:03:30.054425 RD_PRE = 0x0
5038 23:03:30.057886 WR_PRE = 0x1
5039 23:03:30.057989 WR_PST = 0x0
5040 23:03:30.061202 DBI_WR = 0x0
5041 23:03:30.061280 DBI_RD = 0x0
5042 23:03:30.064706 OTF = 0x1
5043 23:03:30.068094 ===================================
5044 23:03:30.070955 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5045 23:03:30.076483 nWR fixed to 30
5046 23:03:30.079842 [ModeRegInit_LP4] CH0 RK0
5047 23:03:30.079916 [ModeRegInit_LP4] CH0 RK1
5048 23:03:30.083301 [ModeRegInit_LP4] CH1 RK0
5049 23:03:30.086772 [ModeRegInit_LP4] CH1 RK1
5050 23:03:30.086876 match AC timing 9
5051 23:03:30.093130 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5052 23:03:30.096519 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5053 23:03:30.099595 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5054 23:03:30.106658 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5055 23:03:30.109488 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5056 23:03:30.109563 ==
5057 23:03:30.112910 Dram Type= 6, Freq= 0, CH_0, rank 0
5058 23:03:30.116554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5059 23:03:30.116633 ==
5060 23:03:30.123162 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5061 23:03:30.129979 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5062 23:03:30.133472 [CA 0] Center 38 (8~69) winsize 62
5063 23:03:30.136442 [CA 1] Center 38 (7~69) winsize 63
5064 23:03:30.139861 [CA 2] Center 35 (5~66) winsize 62
5065 23:03:30.143162 [CA 3] Center 35 (5~66) winsize 62
5066 23:03:30.146586 [CA 4] Center 34 (4~64) winsize 61
5067 23:03:30.149509 [CA 5] Center 34 (4~64) winsize 61
5068 23:03:30.149589
5069 23:03:30.153173 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5070 23:03:30.153253
5071 23:03:30.156488 [CATrainingPosCal] consider 1 rank data
5072 23:03:30.159934 u2DelayCellTimex100 = 270/100 ps
5073 23:03:30.163483 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5074 23:03:30.166129 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5075 23:03:30.169760 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5076 23:03:30.173136 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5077 23:03:30.176459 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5078 23:03:30.179462 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5079 23:03:30.179549
5080 23:03:30.186395 CA PerBit enable=1, Macro0, CA PI delay=34
5081 23:03:30.186469
5082 23:03:30.186558 [CBTSetCACLKResult] CA Dly = 34
5083 23:03:30.189628 CS Dly: 6 (0~37)
5084 23:03:30.189709 ==
5085 23:03:30.193070 Dram Type= 6, Freq= 0, CH_0, rank 1
5086 23:03:30.196589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5087 23:03:30.196670 ==
5088 23:03:30.203193 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5089 23:03:30.209955 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5090 23:03:30.213398 [CA 0] Center 38 (7~69) winsize 63
5091 23:03:30.216298 [CA 1] Center 38 (7~69) winsize 63
5092 23:03:30.220006 [CA 2] Center 35 (5~66) winsize 62
5093 23:03:30.223159 [CA 3] Center 35 (5~66) winsize 62
5094 23:03:30.226578 [CA 4] Center 33 (3~64) winsize 62
5095 23:03:30.230154 [CA 5] Center 33 (3~64) winsize 62
5096 23:03:30.230234
5097 23:03:30.233439 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5098 23:03:30.233519
5099 23:03:30.236447 [CATrainingPosCal] consider 2 rank data
5100 23:03:30.240047 u2DelayCellTimex100 = 270/100 ps
5101 23:03:30.243811 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5102 23:03:30.246726 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5103 23:03:30.249932 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5104 23:03:30.253432 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5105 23:03:30.256807 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5106 23:03:30.259717 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5107 23:03:30.259801
5108 23:03:30.263063 CA PerBit enable=1, Macro0, CA PI delay=34
5109 23:03:30.266461
5110 23:03:30.266541 [CBTSetCACLKResult] CA Dly = 34
5111 23:03:30.269755 CS Dly: 7 (0~39)
5112 23:03:30.269835
5113 23:03:30.273286 ----->DramcWriteLeveling(PI) begin...
5114 23:03:30.273369 ==
5115 23:03:30.276295 Dram Type= 6, Freq= 0, CH_0, rank 0
5116 23:03:30.279896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5117 23:03:30.279980 ==
5118 23:03:30.283410 Write leveling (Byte 0): 31 => 31
5119 23:03:30.286435 Write leveling (Byte 1): 27 => 27
5120 23:03:30.289578 DramcWriteLeveling(PI) end<-----
5121 23:03:30.289659
5122 23:03:30.289722 ==
5123 23:03:30.293048 Dram Type= 6, Freq= 0, CH_0, rank 0
5124 23:03:30.296349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5125 23:03:30.299401 ==
5126 23:03:30.299482 [Gating] SW mode calibration
5127 23:03:30.306453 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5128 23:03:30.312978 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5129 23:03:30.316312 0 14 0 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
5130 23:03:30.322881 0 14 4 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
5131 23:03:30.326647 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5132 23:03:30.329812 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5133 23:03:30.336386 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5134 23:03:30.339702 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5135 23:03:30.342873 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5136 23:03:30.349417 0 14 28 | B1->B0 | 3434 3232 | 1 1 | (1 0) (1 0)
5137 23:03:30.353074 0 15 0 | B1->B0 | 3434 3030 | 0 0 | (1 0) (0 1)
5138 23:03:30.356484 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5139 23:03:30.359440 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5140 23:03:30.366287 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5141 23:03:30.369498 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5142 23:03:30.373043 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5143 23:03:30.379683 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5144 23:03:30.383087 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5145 23:03:30.386587 1 0 0 | B1->B0 | 2a2a 3b3b | 1 0 | (1 1) (0 0)
5146 23:03:30.393169 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5147 23:03:30.396518 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5148 23:03:30.399784 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5149 23:03:30.406423 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5150 23:03:30.409853 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5151 23:03:30.413249 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5152 23:03:30.420177 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5153 23:03:30.423170 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5154 23:03:30.426589 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5155 23:03:30.433465 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 23:03:30.436652 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 23:03:30.440051 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5158 23:03:30.443337 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5159 23:03:30.450248 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5160 23:03:30.453462 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 23:03:30.456427 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 23:03:30.463342 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 23:03:30.466819 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 23:03:30.470164 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5165 23:03:30.476918 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5166 23:03:30.480240 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5167 23:03:30.483731 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5168 23:03:30.489957 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5169 23:03:30.493525 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5170 23:03:30.497071 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5171 23:03:30.500286 Total UI for P1: 0, mck2ui 16
5172 23:03:30.503288 best dqsien dly found for B0: ( 1, 3, 0)
5173 23:03:30.506625 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5174 23:03:30.510047 Total UI for P1: 0, mck2ui 16
5175 23:03:30.513609 best dqsien dly found for B1: ( 1, 3, 2)
5176 23:03:30.516507 best DQS0 dly(MCK, UI, PI) = (1, 3, 0)
5177 23:03:30.523499 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5178 23:03:30.523585
5179 23:03:30.526797 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 0)
5180 23:03:30.530004 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5181 23:03:30.533483 [Gating] SW calibration Done
5182 23:03:30.533563 ==
5183 23:03:30.536821 Dram Type= 6, Freq= 0, CH_0, rank 0
5184 23:03:30.540291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5185 23:03:30.540363 ==
5186 23:03:30.540424 RX Vref Scan: 0
5187 23:03:30.540483
5188 23:03:30.543288 RX Vref 0 -> 0, step: 1
5189 23:03:30.543356
5190 23:03:30.546540 RX Delay -80 -> 252, step: 8
5191 23:03:30.549861 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5192 23:03:30.553419 iDelay=200, Bit 1, Center 103 (8 ~ 199) 192
5193 23:03:30.556873 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5194 23:03:30.563727 iDelay=200, Bit 3, Center 91 (-8 ~ 191) 200
5195 23:03:30.567058 iDelay=200, Bit 4, Center 103 (8 ~ 199) 192
5196 23:03:30.570499 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5197 23:03:30.573386 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5198 23:03:30.577429 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5199 23:03:30.580001 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5200 23:03:30.586763 iDelay=200, Bit 9, Center 75 (-16 ~ 167) 184
5201 23:03:30.590323 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5202 23:03:30.594004 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5203 23:03:30.596630 iDelay=200, Bit 12, Center 91 (-8 ~ 191) 200
5204 23:03:30.599888 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5205 23:03:30.606982 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5206 23:03:30.610137 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5207 23:03:30.610208 ==
5208 23:03:30.613413 Dram Type= 6, Freq= 0, CH_0, rank 0
5209 23:03:30.616506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5210 23:03:30.616584 ==
5211 23:03:30.616664 DQS Delay:
5212 23:03:30.620254 DQS0 = 0, DQS1 = 0
5213 23:03:30.620327 DQM Delay:
5214 23:03:30.623366 DQM0 = 98, DQM1 = 87
5215 23:03:30.623445 DQ Delay:
5216 23:03:30.626843 DQ0 =95, DQ1 =103, DQ2 =95, DQ3 =91
5217 23:03:30.630474 DQ4 =103, DQ5 =87, DQ6 =107, DQ7 =103
5218 23:03:30.633721 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =79
5219 23:03:30.636598 DQ12 =91, DQ13 =95, DQ14 =95, DQ15 =95
5220 23:03:30.636682
5221 23:03:30.636768
5222 23:03:30.636849 ==
5223 23:03:30.640176 Dram Type= 6, Freq= 0, CH_0, rank 0
5224 23:03:30.643279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5225 23:03:30.647008 ==
5226 23:03:30.647091
5227 23:03:30.647177
5228 23:03:30.647257 TX Vref Scan disable
5229 23:03:30.649934 == TX Byte 0 ==
5230 23:03:30.653454 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5231 23:03:30.656607 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5232 23:03:30.659915 == TX Byte 1 ==
5233 23:03:30.663740 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5234 23:03:30.666681 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5235 23:03:30.670360 ==
5236 23:03:30.670444 Dram Type= 6, Freq= 0, CH_0, rank 0
5237 23:03:30.677378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5238 23:03:30.677463 ==
5239 23:03:30.677550
5240 23:03:30.677632
5241 23:03:30.680078 TX Vref Scan disable
5242 23:03:30.680162 == TX Byte 0 ==
5243 23:03:30.687085 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5244 23:03:30.690643 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5245 23:03:30.690731 == TX Byte 1 ==
5246 23:03:30.696789 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5247 23:03:30.700618 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5248 23:03:30.700695
5249 23:03:30.700759 [DATLAT]
5250 23:03:30.703573 Freq=933, CH0 RK0
5251 23:03:30.703658
5252 23:03:30.703743 DATLAT Default: 0xd
5253 23:03:30.706628 0, 0xFFFF, sum = 0
5254 23:03:30.706759 1, 0xFFFF, sum = 0
5255 23:03:30.710073 2, 0xFFFF, sum = 0
5256 23:03:30.710158 3, 0xFFFF, sum = 0
5257 23:03:30.713605 4, 0xFFFF, sum = 0
5258 23:03:30.713690 5, 0xFFFF, sum = 0
5259 23:03:30.716975 6, 0xFFFF, sum = 0
5260 23:03:30.717061 7, 0xFFFF, sum = 0
5261 23:03:30.720294 8, 0xFFFF, sum = 0
5262 23:03:30.720380 9, 0xFFFF, sum = 0
5263 23:03:30.723422 10, 0x0, sum = 1
5264 23:03:30.723507 11, 0x0, sum = 2
5265 23:03:30.727231 12, 0x0, sum = 3
5266 23:03:30.727337 13, 0x0, sum = 4
5267 23:03:30.730096 best_step = 11
5268 23:03:30.730192
5269 23:03:30.730330 ==
5270 23:03:30.733394 Dram Type= 6, Freq= 0, CH_0, rank 0
5271 23:03:30.737003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5272 23:03:30.737088 ==
5273 23:03:30.740563 RX Vref Scan: 1
5274 23:03:30.740647
5275 23:03:30.740733 RX Vref 0 -> 0, step: 1
5276 23:03:30.740845
5277 23:03:30.743977 RX Delay -61 -> 252, step: 4
5278 23:03:30.744060
5279 23:03:30.746810 Set Vref, RX VrefLevel [Byte0]: 53
5280 23:03:30.750084 [Byte1]: 50
5281 23:03:30.754010
5282 23:03:30.754093 Final RX Vref Byte 0 = 53 to rank0
5283 23:03:30.757147 Final RX Vref Byte 1 = 50 to rank0
5284 23:03:30.760770 Final RX Vref Byte 0 = 53 to rank1
5285 23:03:30.763888 Final RX Vref Byte 1 = 50 to rank1==
5286 23:03:30.767166 Dram Type= 6, Freq= 0, CH_0, rank 0
5287 23:03:30.773881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5288 23:03:30.773965 ==
5289 23:03:30.774052 DQS Delay:
5290 23:03:30.774133 DQS0 = 0, DQS1 = 0
5291 23:03:30.777487 DQM Delay:
5292 23:03:30.777571 DQM0 = 97, DQM1 = 88
5293 23:03:30.780608 DQ Delay:
5294 23:03:30.784192 DQ0 =96, DQ1 =98, DQ2 =94, DQ3 =94
5295 23:03:30.787712 DQ4 =98, DQ5 =88, DQ6 =104, DQ7 =104
5296 23:03:30.787796 DQ8 =78, DQ9 =74, DQ10 =92, DQ11 =82
5297 23:03:30.794124 DQ12 =96, DQ13 =94, DQ14 =98, DQ15 =96
5298 23:03:30.794208
5299 23:03:30.794307
5300 23:03:30.800509 [DQSOSCAuto] RK0, (LSB)MR18= 0x1703, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 414 ps
5301 23:03:30.803935 CH0 RK0: MR19=505, MR18=1703
5302 23:03:30.810496 CH0_RK0: MR19=0x505, MR18=0x1703, DQSOSC=414, MR23=63, INC=63, DEC=42
5303 23:03:30.810577
5304 23:03:30.814277 ----->DramcWriteLeveling(PI) begin...
5305 23:03:30.814358 ==
5306 23:03:30.817309 Dram Type= 6, Freq= 0, CH_0, rank 1
5307 23:03:30.820767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5308 23:03:30.820848 ==
5309 23:03:30.824264 Write leveling (Byte 0): 32 => 32
5310 23:03:30.827548 Write leveling (Byte 1): 30 => 30
5311 23:03:30.831122 DramcWriteLeveling(PI) end<-----
5312 23:03:30.831202
5313 23:03:30.831265 ==
5314 23:03:30.834127 Dram Type= 6, Freq= 0, CH_0, rank 1
5315 23:03:30.837951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5316 23:03:30.838051 ==
5317 23:03:30.840755 [Gating] SW mode calibration
5318 23:03:30.847470 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5319 23:03:30.854284 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5320 23:03:30.857711 0 14 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
5321 23:03:30.861263 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5322 23:03:30.868010 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5323 23:03:30.871142 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5324 23:03:30.874497 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5325 23:03:30.881307 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5326 23:03:30.884076 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5327 23:03:30.887902 0 14 28 | B1->B0 | 3333 2f2f | 0 1 | (0 0) (1 0)
5328 23:03:30.894601 0 15 0 | B1->B0 | 2e2e 2323 | 1 0 | (1 1) (0 0)
5329 23:03:30.897584 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5330 23:03:30.901439 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5331 23:03:30.904817 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5332 23:03:30.911300 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5333 23:03:30.914280 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5334 23:03:30.917636 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5335 23:03:30.924631 0 15 28 | B1->B0 | 2727 3939 | 0 1 | (0 0) (0 0)
5336 23:03:30.928282 1 0 0 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
5337 23:03:30.931118 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5338 23:03:30.937942 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5339 23:03:30.940945 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5340 23:03:30.944465 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5341 23:03:30.951141 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5342 23:03:30.954422 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5343 23:03:30.957781 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5344 23:03:30.964830 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5345 23:03:30.968116 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5346 23:03:30.971799 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5347 23:03:30.975154 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5348 23:03:30.981119 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5349 23:03:30.984591 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5350 23:03:30.988289 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5351 23:03:30.994718 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5352 23:03:30.998166 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5353 23:03:31.001630 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5354 23:03:31.008010 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5355 23:03:31.011527 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5356 23:03:31.014808 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5357 23:03:31.021448 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5358 23:03:31.024713 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5359 23:03:31.027789 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5360 23:03:31.034514 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5361 23:03:31.038077 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5362 23:03:31.041515 Total UI for P1: 0, mck2ui 16
5363 23:03:31.044612 best dqsien dly found for B0: ( 1, 2, 28)
5364 23:03:31.047892 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5365 23:03:31.051455 Total UI for P1: 0, mck2ui 16
5366 23:03:31.055028 best dqsien dly found for B1: ( 1, 3, 2)
5367 23:03:31.057876 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5368 23:03:31.061256 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5369 23:03:31.061364
5370 23:03:31.064755 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5371 23:03:31.071402 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5372 23:03:31.071486 [Gating] SW calibration Done
5373 23:03:31.071573 ==
5374 23:03:31.074487 Dram Type= 6, Freq= 0, CH_0, rank 1
5375 23:03:31.081397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5376 23:03:31.081506 ==
5377 23:03:31.081615 RX Vref Scan: 0
5378 23:03:31.081697
5379 23:03:31.084489 RX Vref 0 -> 0, step: 1
5380 23:03:31.084572
5381 23:03:31.088077 RX Delay -80 -> 252, step: 8
5382 23:03:31.091072 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5383 23:03:31.094772 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5384 23:03:31.097620 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5385 23:03:31.100945 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5386 23:03:31.108082 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5387 23:03:31.111350 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5388 23:03:31.114479 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5389 23:03:31.118171 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5390 23:03:31.121296 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5391 23:03:31.124491 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5392 23:03:31.131405 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5393 23:03:31.134344 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5394 23:03:31.137618 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5395 23:03:31.141376 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5396 23:03:31.144616 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5397 23:03:31.147699 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5398 23:03:31.151573 ==
5399 23:03:31.154618 Dram Type= 6, Freq= 0, CH_0, rank 1
5400 23:03:31.157786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5401 23:03:31.157879 ==
5402 23:03:31.157965 DQS Delay:
5403 23:03:31.161196 DQS0 = 0, DQS1 = 0
5404 23:03:31.161298 DQM Delay:
5405 23:03:31.164303 DQM0 = 96, DQM1 = 87
5406 23:03:31.164377 DQ Delay:
5407 23:03:31.168135 DQ0 =99, DQ1 =99, DQ2 =91, DQ3 =91
5408 23:03:31.171445 DQ4 =95, DQ5 =87, DQ6 =107, DQ7 =103
5409 23:03:31.174376 DQ8 =83, DQ9 =79, DQ10 =87, DQ11 =79
5410 23:03:31.177899 DQ12 =87, DQ13 =91, DQ14 =95, DQ15 =95
5411 23:03:31.177983
5412 23:03:31.178068
5413 23:03:31.178150 ==
5414 23:03:31.181200 Dram Type= 6, Freq= 0, CH_0, rank 1
5415 23:03:31.184719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5416 23:03:31.184803 ==
5417 23:03:31.184890
5418 23:03:31.184970
5419 23:03:31.187985 TX Vref Scan disable
5420 23:03:31.191525 == TX Byte 0 ==
5421 23:03:31.194500 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5422 23:03:31.198006 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5423 23:03:31.201316 == TX Byte 1 ==
5424 23:03:31.204895 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5425 23:03:31.208287 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5426 23:03:31.208370 ==
5427 23:03:31.211574 Dram Type= 6, Freq= 0, CH_0, rank 1
5428 23:03:31.215088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5429 23:03:31.217835 ==
5430 23:03:31.217918
5431 23:03:31.218004
5432 23:03:31.218085 TX Vref Scan disable
5433 23:03:31.221547 == TX Byte 0 ==
5434 23:03:31.224989 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5435 23:03:31.228064 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5436 23:03:31.231497 == TX Byte 1 ==
5437 23:03:31.235120 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5438 23:03:31.238534 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5439 23:03:31.241358
5440 23:03:31.241441 [DATLAT]
5441 23:03:31.241527 Freq=933, CH0 RK1
5442 23:03:31.241610
5443 23:03:31.244867 DATLAT Default: 0xb
5444 23:03:31.244951 0, 0xFFFF, sum = 0
5445 23:03:31.248053 1, 0xFFFF, sum = 0
5446 23:03:31.248161 2, 0xFFFF, sum = 0
5447 23:03:31.251581 3, 0xFFFF, sum = 0
5448 23:03:31.251654 4, 0xFFFF, sum = 0
5449 23:03:31.254671 5, 0xFFFF, sum = 0
5450 23:03:31.254770 6, 0xFFFF, sum = 0
5451 23:03:31.258282 7, 0xFFFF, sum = 0
5452 23:03:31.261515 8, 0xFFFF, sum = 0
5453 23:03:31.261623 9, 0xFFFF, sum = 0
5454 23:03:31.264968 10, 0x0, sum = 1
5455 23:03:31.265075 11, 0x0, sum = 2
5456 23:03:31.265168 12, 0x0, sum = 3
5457 23:03:31.267955 13, 0x0, sum = 4
5458 23:03:31.268026 best_step = 11
5459 23:03:31.268091
5460 23:03:31.268177 ==
5461 23:03:31.271876 Dram Type= 6, Freq= 0, CH_0, rank 1
5462 23:03:31.278338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5463 23:03:31.278440 ==
5464 23:03:31.278530 RX Vref Scan: 0
5465 23:03:31.278616
5466 23:03:31.281199 RX Vref 0 -> 0, step: 1
5467 23:03:31.281295
5468 23:03:31.284537 RX Delay -61 -> 252, step: 4
5469 23:03:31.288347 iDelay=199, Bit 0, Center 96 (3 ~ 190) 188
5470 23:03:31.291432 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5471 23:03:31.298287 iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188
5472 23:03:31.301385 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5473 23:03:31.304845 iDelay=199, Bit 4, Center 94 (3 ~ 186) 184
5474 23:03:31.308212 iDelay=199, Bit 5, Center 84 (-9 ~ 178) 188
5475 23:03:31.311490 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5476 23:03:31.314875 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5477 23:03:31.321451 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5478 23:03:31.324903 iDelay=199, Bit 9, Center 80 (-9 ~ 170) 180
5479 23:03:31.328232 iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180
5480 23:03:31.331381 iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176
5481 23:03:31.335057 iDelay=199, Bit 12, Center 90 (-1 ~ 182) 184
5482 23:03:31.338407 iDelay=199, Bit 13, Center 92 (3 ~ 182) 180
5483 23:03:31.345332 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5484 23:03:31.348331 iDelay=199, Bit 15, Center 92 (3 ~ 182) 180
5485 23:03:31.348413 ==
5486 23:03:31.351929 Dram Type= 6, Freq= 0, CH_0, rank 1
5487 23:03:31.354897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5488 23:03:31.354994 ==
5489 23:03:31.358124 DQS Delay:
5490 23:03:31.358236 DQS0 = 0, DQS1 = 0
5491 23:03:31.358348 DQM Delay:
5492 23:03:31.361628 DQM0 = 95, DQM1 = 87
5493 23:03:31.361744 DQ Delay:
5494 23:03:31.365261 DQ0 =96, DQ1 =96, DQ2 =92, DQ3 =94
5495 23:03:31.368269 DQ4 =94, DQ5 =84, DQ6 =104, DQ7 =102
5496 23:03:31.371566 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =78
5497 23:03:31.375096 DQ12 =90, DQ13 =92, DQ14 =98, DQ15 =92
5498 23:03:31.375177
5499 23:03:31.375242
5500 23:03:31.385017 [DQSOSCAuto] RK1, (LSB)MR18= 0x1a07, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 413 ps
5501 23:03:31.385123 CH0 RK1: MR19=505, MR18=1A07
5502 23:03:31.391378 CH0_RK1: MR19=0x505, MR18=0x1A07, DQSOSC=413, MR23=63, INC=63, DEC=42
5503 23:03:31.395319 [RxdqsGatingPostProcess] freq 933
5504 23:03:31.401665 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5505 23:03:31.404952 best DQS0 dly(2T, 0.5T) = (0, 11)
5506 23:03:31.408421 best DQS1 dly(2T, 0.5T) = (0, 11)
5507 23:03:31.411462 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
5508 23:03:31.414976 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5509 23:03:31.415074 best DQS0 dly(2T, 0.5T) = (0, 10)
5510 23:03:31.418318 best DQS1 dly(2T, 0.5T) = (0, 11)
5511 23:03:31.422100 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5512 23:03:31.424864 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5513 23:03:31.428434 Pre-setting of DQS Precalculation
5514 23:03:31.435034 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5515 23:03:31.435116 ==
5516 23:03:31.438327 Dram Type= 6, Freq= 0, CH_1, rank 0
5517 23:03:31.441621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5518 23:03:31.441724 ==
5519 23:03:31.448475 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5520 23:03:31.455333 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5521 23:03:31.458676 [CA 0] Center 36 (6~67) winsize 62
5522 23:03:31.461558 [CA 1] Center 36 (6~67) winsize 62
5523 23:03:31.464981 [CA 2] Center 34 (4~64) winsize 61
5524 23:03:31.468535 [CA 3] Center 33 (3~64) winsize 62
5525 23:03:31.472032 [CA 4] Center 34 (3~65) winsize 63
5526 23:03:31.472115 [CA 5] Center 33 (3~64) winsize 62
5527 23:03:31.474790
5528 23:03:31.478068 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5529 23:03:31.478149
5530 23:03:31.481748 [CATrainingPosCal] consider 1 rank data
5531 23:03:31.485218 u2DelayCellTimex100 = 270/100 ps
5532 23:03:31.488539 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5533 23:03:31.491788 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5534 23:03:31.495395 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5535 23:03:31.498117 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5536 23:03:31.502086 CA4 delay=34 (3~65),Diff = 1 PI (6 cell)
5537 23:03:31.505099 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5538 23:03:31.505173
5539 23:03:31.508526 CA PerBit enable=1, Macro0, CA PI delay=33
5540 23:03:31.508612
5541 23:03:31.512323 [CBTSetCACLKResult] CA Dly = 33
5542 23:03:31.515368 CS Dly: 4 (0~35)
5543 23:03:31.515458 ==
5544 23:03:31.518187 Dram Type= 6, Freq= 0, CH_1, rank 1
5545 23:03:31.521525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5546 23:03:31.521631 ==
5547 23:03:31.528678 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5548 23:03:31.535223 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5549 23:03:31.539123 [CA 0] Center 37 (7~67) winsize 61
5550 23:03:31.542038 [CA 1] Center 37 (7~67) winsize 61
5551 23:03:31.545084 [CA 2] Center 34 (3~65) winsize 63
5552 23:03:31.548600 [CA 3] Center 33 (3~64) winsize 62
5553 23:03:31.548701 [CA 4] Center 34 (4~65) winsize 62
5554 23:03:31.552217 [CA 5] Center 32 (2~63) winsize 62
5555 23:03:31.552288
5556 23:03:31.558325 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5557 23:03:31.558429
5558 23:03:31.562049 [CATrainingPosCal] consider 2 rank data
5559 23:03:31.565185 u2DelayCellTimex100 = 270/100 ps
5560 23:03:31.568751 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5561 23:03:31.572021 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5562 23:03:31.574986 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5563 23:03:31.578542 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5564 23:03:31.581919 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5565 23:03:31.584978 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5566 23:03:31.585074
5567 23:03:31.588143 CA PerBit enable=1, Macro0, CA PI delay=33
5568 23:03:31.588224
5569 23:03:31.591617 [CBTSetCACLKResult] CA Dly = 33
5570 23:03:31.595108 CS Dly: 5 (0~38)
5571 23:03:31.595180
5572 23:03:31.598515 ----->DramcWriteLeveling(PI) begin...
5573 23:03:31.598588 ==
5574 23:03:31.601919 Dram Type= 6, Freq= 0, CH_1, rank 0
5575 23:03:31.605129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5576 23:03:31.605228 ==
5577 23:03:31.608730 Write leveling (Byte 0): 24 => 24
5578 23:03:31.611666 Write leveling (Byte 1): 26 => 26
5579 23:03:31.615070 DramcWriteLeveling(PI) end<-----
5580 23:03:31.615165
5581 23:03:31.615228 ==
5582 23:03:31.618463 Dram Type= 6, Freq= 0, CH_1, rank 0
5583 23:03:31.622104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5584 23:03:31.622188 ==
5585 23:03:31.625473 [Gating] SW mode calibration
5586 23:03:31.631815 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5587 23:03:31.638557 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5588 23:03:31.642156 0 14 0 | B1->B0 | 3232 3232 | 0 1 | (0 0) (1 1)
5589 23:03:31.645388 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5590 23:03:31.652176 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5591 23:03:31.655433 0 14 12 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
5592 23:03:31.658707 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5593 23:03:31.665351 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5594 23:03:31.668973 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5595 23:03:31.671926 0 14 28 | B1->B0 | 3131 3232 | 0 0 | (1 0) (0 1)
5596 23:03:31.679069 0 15 0 | B1->B0 | 2323 2c2c | 0 1 | (1 0) (1 0)
5597 23:03:31.682371 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5598 23:03:31.685608 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5599 23:03:31.688912 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5600 23:03:31.695387 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5601 23:03:31.699292 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5602 23:03:31.702123 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5603 23:03:31.709078 0 15 28 | B1->B0 | 2d2c 2b2b | 1 0 | (1 1) (0 0)
5604 23:03:31.712483 1 0 0 | B1->B0 | 4343 3d3d | 0 0 | (0 0) (0 0)
5605 23:03:31.715693 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5606 23:03:31.722495 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5607 23:03:31.725532 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5608 23:03:31.728638 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5609 23:03:31.735814 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5610 23:03:31.739196 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5611 23:03:31.742552 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5612 23:03:31.749160 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 23:03:31.752328 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5614 23:03:31.755487 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5615 23:03:31.762801 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 23:03:31.765879 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 23:03:31.768930 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 23:03:31.772499 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 23:03:31.778798 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 23:03:31.782290 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 23:03:31.785586 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 23:03:31.792338 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 23:03:31.796088 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 23:03:31.799003 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 23:03:31.806042 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 23:03:31.809362 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 23:03:31.812896 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5628 23:03:31.819274 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5629 23:03:31.819380 Total UI for P1: 0, mck2ui 16
5630 23:03:31.825956 best dqsien dly found for B0: ( 1, 2, 28)
5631 23:03:31.829458 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5632 23:03:31.832433 Total UI for P1: 0, mck2ui 16
5633 23:03:31.835914 best dqsien dly found for B1: ( 1, 2, 30)
5634 23:03:31.839623 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5635 23:03:31.842405 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5636 23:03:31.842482
5637 23:03:31.846048 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5638 23:03:31.849383 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5639 23:03:31.852402 [Gating] SW calibration Done
5640 23:03:31.852483 ==
5641 23:03:31.855664 Dram Type= 6, Freq= 0, CH_1, rank 0
5642 23:03:31.859180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5643 23:03:31.859261 ==
5644 23:03:31.862469 RX Vref Scan: 0
5645 23:03:31.862589
5646 23:03:31.865990 RX Vref 0 -> 0, step: 1
5647 23:03:31.866097
5648 23:03:31.866194 RX Delay -80 -> 252, step: 8
5649 23:03:31.872880 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5650 23:03:31.875798 iDelay=200, Bit 1, Center 91 (-8 ~ 191) 200
5651 23:03:31.878934 iDelay=200, Bit 2, Center 79 (-16 ~ 175) 192
5652 23:03:31.882527 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5653 23:03:31.886062 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5654 23:03:31.889020 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5655 23:03:31.896195 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5656 23:03:31.899423 iDelay=200, Bit 7, Center 91 (-8 ~ 191) 200
5657 23:03:31.902348 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5658 23:03:31.905823 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5659 23:03:31.909278 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5660 23:03:31.915637 iDelay=200, Bit 11, Center 87 (-8 ~ 183) 192
5661 23:03:31.918812 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5662 23:03:31.922585 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5663 23:03:31.925666 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5664 23:03:31.929177 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5665 23:03:31.929255 ==
5666 23:03:31.932683 Dram Type= 6, Freq= 0, CH_1, rank 0
5667 23:03:31.936019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5668 23:03:31.939341 ==
5669 23:03:31.939424 DQS Delay:
5670 23:03:31.939492 DQS0 = 0, DQS1 = 0
5671 23:03:31.942594 DQM Delay:
5672 23:03:31.942675 DQM0 = 95, DQM1 = 89
5673 23:03:31.945871 DQ Delay:
5674 23:03:31.945951 DQ0 =99, DQ1 =91, DQ2 =79, DQ3 =95
5675 23:03:31.949428 DQ4 =95, DQ5 =103, DQ6 =107, DQ7 =91
5676 23:03:31.952822 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =87
5677 23:03:31.956006 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5678 23:03:31.956091
5679 23:03:31.959318
5680 23:03:31.959393 ==
5681 23:03:31.962393 Dram Type= 6, Freq= 0, CH_1, rank 0
5682 23:03:31.965881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5683 23:03:31.965962 ==
5684 23:03:31.966030
5685 23:03:31.966102
5686 23:03:31.969036 TX Vref Scan disable
5687 23:03:31.969122 == TX Byte 0 ==
5688 23:03:31.975981 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5689 23:03:31.979261 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5690 23:03:31.979340 == TX Byte 1 ==
5691 23:03:31.986263 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5692 23:03:31.989060 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5693 23:03:31.989140 ==
5694 23:03:31.992552 Dram Type= 6, Freq= 0, CH_1, rank 0
5695 23:03:31.995962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5696 23:03:31.996038 ==
5697 23:03:31.996106
5698 23:03:31.996172
5699 23:03:31.999462 TX Vref Scan disable
5700 23:03:32.002827 == TX Byte 0 ==
5701 23:03:32.006304 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5702 23:03:32.009551 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5703 23:03:32.012600 == TX Byte 1 ==
5704 23:03:32.016291 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5705 23:03:32.019258 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5706 23:03:32.019336
5707 23:03:32.019400 [DATLAT]
5708 23:03:32.022744 Freq=933, CH1 RK0
5709 23:03:32.022818
5710 23:03:32.026160 DATLAT Default: 0xd
5711 23:03:32.026237 0, 0xFFFF, sum = 0
5712 23:03:32.029625 1, 0xFFFF, sum = 0
5713 23:03:32.029713 2, 0xFFFF, sum = 0
5714 23:03:32.032862 3, 0xFFFF, sum = 0
5715 23:03:32.032943 4, 0xFFFF, sum = 0
5716 23:03:32.036147 5, 0xFFFF, sum = 0
5717 23:03:32.036221 6, 0xFFFF, sum = 0
5718 23:03:32.039243 7, 0xFFFF, sum = 0
5719 23:03:32.039315 8, 0xFFFF, sum = 0
5720 23:03:32.042894 9, 0xFFFF, sum = 0
5721 23:03:32.042969 10, 0x0, sum = 1
5722 23:03:32.045894 11, 0x0, sum = 2
5723 23:03:32.045966 12, 0x0, sum = 3
5724 23:03:32.049347 13, 0x0, sum = 4
5725 23:03:32.049418 best_step = 11
5726 23:03:32.049478
5727 23:03:32.049547 ==
5728 23:03:32.052577 Dram Type= 6, Freq= 0, CH_1, rank 0
5729 23:03:32.056120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5730 23:03:32.056192 ==
5731 23:03:32.059432 RX Vref Scan: 1
5732 23:03:32.059506
5733 23:03:32.062921 RX Vref 0 -> 0, step: 1
5734 23:03:32.063003
5735 23:03:32.063074 RX Delay -61 -> 252, step: 4
5736 23:03:32.063139
5737 23:03:32.066196 Set Vref, RX VrefLevel [Byte0]: 60
5738 23:03:32.069212 [Byte1]: 51
5739 23:03:32.074116
5740 23:03:32.074192 Final RX Vref Byte 0 = 60 to rank0
5741 23:03:32.077752 Final RX Vref Byte 1 = 51 to rank0
5742 23:03:32.080450 Final RX Vref Byte 0 = 60 to rank1
5743 23:03:32.083869 Final RX Vref Byte 1 = 51 to rank1==
5744 23:03:32.087235 Dram Type= 6, Freq= 0, CH_1, rank 0
5745 23:03:32.094222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5746 23:03:32.094298 ==
5747 23:03:32.094360 DQS Delay:
5748 23:03:32.094446 DQS0 = 0, DQS1 = 0
5749 23:03:32.097459 DQM Delay:
5750 23:03:32.097538 DQM0 = 98, DQM1 = 90
5751 23:03:32.100642 DQ Delay:
5752 23:03:32.104228 DQ0 =102, DQ1 =92, DQ2 =88, DQ3 =98
5753 23:03:32.107619 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =96
5754 23:03:32.111054 DQ8 =80, DQ9 =76, DQ10 =94, DQ11 =86
5755 23:03:32.114152 DQ12 =96, DQ13 =98, DQ14 =96, DQ15 =96
5756 23:03:32.114229
5757 23:03:32.114291
5758 23:03:32.120970 [DQSOSCAuto] RK0, (LSB)MR18= 0x11ee, (MSB)MR19= 0x504, tDQSOscB0 = 428 ps tDQSOscB1 = 416 ps
5759 23:03:32.124041 CH1 RK0: MR19=504, MR18=11EE
5760 23:03:32.130539 CH1_RK0: MR19=0x504, MR18=0x11EE, DQSOSC=416, MR23=63, INC=62, DEC=41
5761 23:03:32.130623
5762 23:03:32.134154 ----->DramcWriteLeveling(PI) begin...
5763 23:03:32.134242 ==
5764 23:03:32.137628 Dram Type= 6, Freq= 0, CH_1, rank 1
5765 23:03:32.140611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5766 23:03:32.140691 ==
5767 23:03:32.144064 Write leveling (Byte 0): 28 => 28
5768 23:03:32.147730 Write leveling (Byte 1): 28 => 28
5769 23:03:32.151119 DramcWriteLeveling(PI) end<-----
5770 23:03:32.151191
5771 23:03:32.151261 ==
5772 23:03:32.154652 Dram Type= 6, Freq= 0, CH_1, rank 1
5773 23:03:32.157142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5774 23:03:32.157219 ==
5775 23:03:32.161356 [Gating] SW mode calibration
5776 23:03:32.167564 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5777 23:03:32.174066 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5778 23:03:32.177396 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5779 23:03:32.180549 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5780 23:03:32.187853 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5781 23:03:32.190975 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5782 23:03:32.194476 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5783 23:03:32.200855 0 14 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5784 23:03:32.204302 0 14 24 | B1->B0 | 3131 2d2d | 1 0 | (1 1) (0 0)
5785 23:03:32.207821 0 14 28 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
5786 23:03:32.214097 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5787 23:03:32.217311 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5788 23:03:32.220931 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5789 23:03:32.227273 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5790 23:03:32.230843 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5791 23:03:32.234210 0 15 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5792 23:03:32.240832 0 15 24 | B1->B0 | 2a2a 3434 | 1 0 | (0 0) (1 1)
5793 23:03:32.244333 0 15 28 | B1->B0 | 3c3c 4646 | 1 0 | (0 0) (0 0)
5794 23:03:32.247772 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5795 23:03:32.254150 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5796 23:03:32.257597 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5797 23:03:32.261090 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5798 23:03:32.264807 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5799 23:03:32.270829 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5800 23:03:32.274277 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5801 23:03:32.277652 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5802 23:03:32.283998 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5803 23:03:32.287531 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5804 23:03:32.291023 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5805 23:03:32.297368 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5806 23:03:32.300769 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5807 23:03:32.303836 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 23:03:32.310670 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5809 23:03:32.314049 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5810 23:03:32.317071 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5811 23:03:32.323988 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5812 23:03:32.327544 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5813 23:03:32.330897 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5814 23:03:32.337824 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5815 23:03:32.340646 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5816 23:03:32.344252 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5817 23:03:32.347706 Total UI for P1: 0, mck2ui 16
5818 23:03:32.350739 best dqsien dly found for B0: ( 1, 2, 22)
5819 23:03:32.353956 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5820 23:03:32.360813 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5821 23:03:32.364327 Total UI for P1: 0, mck2ui 16
5822 23:03:32.367266 best dqsien dly found for B1: ( 1, 2, 26)
5823 23:03:32.370639 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5824 23:03:32.373953 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5825 23:03:32.374040
5826 23:03:32.377434 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5827 23:03:32.380794 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5828 23:03:32.384335 [Gating] SW calibration Done
5829 23:03:32.384414 ==
5830 23:03:32.387302 Dram Type= 6, Freq= 0, CH_1, rank 1
5831 23:03:32.390878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5832 23:03:32.390954 ==
5833 23:03:32.394253 RX Vref Scan: 0
5834 23:03:32.394334
5835 23:03:32.394399 RX Vref 0 -> 0, step: 1
5836 23:03:32.397450
5837 23:03:32.397524 RX Delay -80 -> 252, step: 8
5838 23:03:32.404335 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5839 23:03:32.407956 iDelay=200, Bit 1, Center 87 (-8 ~ 183) 192
5840 23:03:32.411024 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5841 23:03:32.413911 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5842 23:03:32.417492 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5843 23:03:32.420790 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5844 23:03:32.424321 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5845 23:03:32.430779 iDelay=200, Bit 7, Center 91 (0 ~ 183) 184
5846 23:03:32.434326 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5847 23:03:32.437486 iDelay=200, Bit 9, Center 83 (-8 ~ 175) 184
5848 23:03:32.441118 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5849 23:03:32.444416 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5850 23:03:32.447414 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5851 23:03:32.454147 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5852 23:03:32.457252 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5853 23:03:32.460948 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5854 23:03:32.461023 ==
5855 23:03:32.464015 Dram Type= 6, Freq= 0, CH_1, rank 1
5856 23:03:32.467605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5857 23:03:32.467691 ==
5858 23:03:32.470829 DQS Delay:
5859 23:03:32.470944 DQS0 = 0, DQS1 = 0
5860 23:03:32.471013 DQM Delay:
5861 23:03:32.474165 DQM0 = 94, DQM1 = 90
5862 23:03:32.474249 DQ Delay:
5863 23:03:32.477740 DQ0 =95, DQ1 =87, DQ2 =87, DQ3 =95
5864 23:03:32.481110 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =91
5865 23:03:32.484077 DQ8 =83, DQ9 =83, DQ10 =91, DQ11 =83
5866 23:03:32.487661 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5867 23:03:32.487734
5868 23:03:32.487806
5869 23:03:32.487867 ==
5870 23:03:32.491053 Dram Type= 6, Freq= 0, CH_1, rank 1
5871 23:03:32.497280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5872 23:03:32.497355 ==
5873 23:03:32.497427
5874 23:03:32.497488
5875 23:03:32.497543 TX Vref Scan disable
5876 23:03:32.500902 == TX Byte 0 ==
5877 23:03:32.504500 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5878 23:03:32.511521 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5879 23:03:32.511602 == TX Byte 1 ==
5880 23:03:32.514847 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5881 23:03:32.517711 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5882 23:03:32.521159 ==
5883 23:03:32.524715 Dram Type= 6, Freq= 0, CH_1, rank 1
5884 23:03:32.527786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5885 23:03:32.527867 ==
5886 23:03:32.527930
5887 23:03:32.527988
5888 23:03:32.531411 TX Vref Scan disable
5889 23:03:32.531490 == TX Byte 0 ==
5890 23:03:32.538163 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5891 23:03:32.541600 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5892 23:03:32.541677 == TX Byte 1 ==
5893 23:03:32.547775 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5894 23:03:32.551502 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5895 23:03:32.551582
5896 23:03:32.551645 [DATLAT]
5897 23:03:32.554520 Freq=933, CH1 RK1
5898 23:03:32.554621
5899 23:03:32.554709 DATLAT Default: 0xb
5900 23:03:32.557793 0, 0xFFFF, sum = 0
5901 23:03:32.557879 1, 0xFFFF, sum = 0
5902 23:03:32.560876 2, 0xFFFF, sum = 0
5903 23:03:32.560947 3, 0xFFFF, sum = 0
5904 23:03:32.564088 4, 0xFFFF, sum = 0
5905 23:03:32.564169 5, 0xFFFF, sum = 0
5906 23:03:32.567903 6, 0xFFFF, sum = 0
5907 23:03:32.568008 7, 0xFFFF, sum = 0
5908 23:03:32.571077 8, 0xFFFF, sum = 0
5909 23:03:32.571177 9, 0xFFFF, sum = 0
5910 23:03:32.574825 10, 0x0, sum = 1
5911 23:03:32.574950 11, 0x0, sum = 2
5912 23:03:32.577930 12, 0x0, sum = 3
5913 23:03:32.578006 13, 0x0, sum = 4
5914 23:03:32.581518 best_step = 11
5915 23:03:32.581590
5916 23:03:32.581654 ==
5917 23:03:32.584285 Dram Type= 6, Freq= 0, CH_1, rank 1
5918 23:03:32.587733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5919 23:03:32.587801 ==
5920 23:03:32.590817 RX Vref Scan: 0
5921 23:03:32.590946
5922 23:03:32.591007 RX Vref 0 -> 0, step: 1
5923 23:03:32.591065
5924 23:03:32.594701 RX Delay -53 -> 252, step: 4
5925 23:03:32.601541 iDelay=195, Bit 0, Center 98 (7 ~ 190) 184
5926 23:03:32.604477 iDelay=195, Bit 1, Center 90 (-1 ~ 182) 184
5927 23:03:32.607921 iDelay=195, Bit 2, Center 86 (-5 ~ 178) 184
5928 23:03:32.611433 iDelay=195, Bit 3, Center 94 (3 ~ 186) 184
5929 23:03:32.614589 iDelay=195, Bit 4, Center 96 (7 ~ 186) 180
5930 23:03:32.618042 iDelay=195, Bit 5, Center 104 (15 ~ 194) 180
5931 23:03:32.624746 iDelay=195, Bit 6, Center 102 (11 ~ 194) 184
5932 23:03:32.628220 iDelay=195, Bit 7, Center 92 (3 ~ 182) 180
5933 23:03:32.631265 iDelay=195, Bit 8, Center 82 (-9 ~ 174) 184
5934 23:03:32.634773 iDelay=195, Bit 9, Center 80 (-9 ~ 170) 180
5935 23:03:32.637981 iDelay=195, Bit 10, Center 94 (3 ~ 186) 184
5936 23:03:32.641526 iDelay=195, Bit 11, Center 84 (-5 ~ 174) 180
5937 23:03:32.647994 iDelay=195, Bit 12, Center 96 (7 ~ 186) 180
5938 23:03:32.651427 iDelay=195, Bit 13, Center 98 (7 ~ 190) 184
5939 23:03:32.654634 iDelay=195, Bit 14, Center 98 (7 ~ 190) 184
5940 23:03:32.658372 iDelay=195, Bit 15, Center 100 (11 ~ 190) 180
5941 23:03:32.658447 ==
5942 23:03:32.661553 Dram Type= 6, Freq= 0, CH_1, rank 1
5943 23:03:32.664851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5944 23:03:32.668471 ==
5945 23:03:32.668561 DQS Delay:
5946 23:03:32.668626 DQS0 = 0, DQS1 = 0
5947 23:03:32.671558 DQM Delay:
5948 23:03:32.671629 DQM0 = 95, DQM1 = 91
5949 23:03:32.671688 DQ Delay:
5950 23:03:32.675389 DQ0 =98, DQ1 =90, DQ2 =86, DQ3 =94
5951 23:03:32.678003 DQ4 =96, DQ5 =104, DQ6 =102, DQ7 =92
5952 23:03:32.681370 DQ8 =82, DQ9 =80, DQ10 =94, DQ11 =84
5953 23:03:32.684823 DQ12 =96, DQ13 =98, DQ14 =98, DQ15 =100
5954 23:03:32.684895
5955 23:03:32.688159
5956 23:03:32.695077 [DQSOSCAuto] RK1, (LSB)MR18= 0xf18, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 417 ps
5957 23:03:32.698659 CH1 RK1: MR19=505, MR18=F18
5958 23:03:32.701499 CH1_RK1: MR19=0x505, MR18=0xF18, DQSOSC=414, MR23=63, INC=63, DEC=42
5959 23:03:32.704958 [RxdqsGatingPostProcess] freq 933
5960 23:03:32.711882 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5961 23:03:32.715347 best DQS0 dly(2T, 0.5T) = (0, 10)
5962 23:03:32.718103 best DQS1 dly(2T, 0.5T) = (0, 10)
5963 23:03:32.721884 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5964 23:03:32.725073 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5965 23:03:32.728387 best DQS0 dly(2T, 0.5T) = (0, 10)
5966 23:03:32.731829 best DQS1 dly(2T, 0.5T) = (0, 10)
5967 23:03:32.735646 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5968 23:03:32.738393 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5969 23:03:32.738469 Pre-setting of DQS Precalculation
5970 23:03:32.744742 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5971 23:03:32.751836 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5972 23:03:32.758232 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5973 23:03:32.758307
5974 23:03:32.758389
5975 23:03:32.761495 [Calibration Summary] 1866 Mbps
5976 23:03:32.765568 CH 0, Rank 0
5977 23:03:32.765656 SW Impedance : PASS
5978 23:03:32.768660 DUTY Scan : NO K
5979 23:03:32.771749 ZQ Calibration : PASS
5980 23:03:32.771820 Jitter Meter : NO K
5981 23:03:32.775027 CBT Training : PASS
5982 23:03:32.775095 Write leveling : PASS
5983 23:03:32.778531 RX DQS gating : PASS
5984 23:03:32.781964 RX DQ/DQS(RDDQC) : PASS
5985 23:03:32.782068 TX DQ/DQS : PASS
5986 23:03:32.785103 RX DATLAT : PASS
5987 23:03:32.788750 RX DQ/DQS(Engine): PASS
5988 23:03:32.788821 TX OE : NO K
5989 23:03:32.791848 All Pass.
5990 23:03:32.791927
5991 23:03:32.791987 CH 0, Rank 1
5992 23:03:32.795180 SW Impedance : PASS
5993 23:03:32.795246 DUTY Scan : NO K
5994 23:03:32.798778 ZQ Calibration : PASS
5995 23:03:32.801906 Jitter Meter : NO K
5996 23:03:32.801971 CBT Training : PASS
5997 23:03:32.804933 Write leveling : PASS
5998 23:03:32.808501 RX DQS gating : PASS
5999 23:03:32.808571 RX DQ/DQS(RDDQC) : PASS
6000 23:03:32.812154 TX DQ/DQS : PASS
6001 23:03:32.812229 RX DATLAT : PASS
6002 23:03:32.815532 RX DQ/DQS(Engine): PASS
6003 23:03:32.818735 TX OE : NO K
6004 23:03:32.818813 All Pass.
6005 23:03:32.818892
6006 23:03:32.818963 CH 1, Rank 0
6007 23:03:32.821649 SW Impedance : PASS
6008 23:03:32.825254 DUTY Scan : NO K
6009 23:03:32.825335 ZQ Calibration : PASS
6010 23:03:32.828591 Jitter Meter : NO K
6011 23:03:32.831936 CBT Training : PASS
6012 23:03:32.832010 Write leveling : PASS
6013 23:03:32.835088 RX DQS gating : PASS
6014 23:03:32.838798 RX DQ/DQS(RDDQC) : PASS
6015 23:03:32.838926 TX DQ/DQS : PASS
6016 23:03:32.841763 RX DATLAT : PASS
6017 23:03:32.844887 RX DQ/DQS(Engine): PASS
6018 23:03:32.844963 TX OE : NO K
6019 23:03:32.848515 All Pass.
6020 23:03:32.848595
6021 23:03:32.848689 CH 1, Rank 1
6022 23:03:32.851757 SW Impedance : PASS
6023 23:03:32.851829 DUTY Scan : NO K
6024 23:03:32.855066 ZQ Calibration : PASS
6025 23:03:32.858430 Jitter Meter : NO K
6026 23:03:32.858515 CBT Training : PASS
6027 23:03:32.861914 Write leveling : PASS
6028 23:03:32.862015 RX DQS gating : PASS
6029 23:03:32.865365 RX DQ/DQS(RDDQC) : PASS
6030 23:03:32.868904 TX DQ/DQS : PASS
6031 23:03:32.868982 RX DATLAT : PASS
6032 23:03:32.871790 RX DQ/DQS(Engine): PASS
6033 23:03:32.875145 TX OE : NO K
6034 23:03:32.875218 All Pass.
6035 23:03:32.875279
6036 23:03:32.878478 DramC Write-DBI off
6037 23:03:32.878583 PER_BANK_REFRESH: Hybrid Mode
6038 23:03:32.881994 TX_TRACKING: ON
6039 23:03:32.888345 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6040 23:03:32.895011 [FAST_K] Save calibration result to emmc
6041 23:03:32.898711 dramc_set_vcore_voltage set vcore to 650000
6042 23:03:32.898839 Read voltage for 400, 6
6043 23:03:32.901810 Vio18 = 0
6044 23:03:32.901907 Vcore = 650000
6045 23:03:32.902001 Vdram = 0
6046 23:03:32.905350 Vddq = 0
6047 23:03:32.905444 Vmddr = 0
6048 23:03:32.908695 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6049 23:03:32.915716 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6050 23:03:32.918495 MEM_TYPE=3, freq_sel=20
6051 23:03:32.918566 sv_algorithm_assistance_LP4_800
6052 23:03:32.925143 ============ PULL DRAM RESETB DOWN ============
6053 23:03:32.928670 ========== PULL DRAM RESETB DOWN end =========
6054 23:03:32.931957 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6055 23:03:32.935376 ===================================
6056 23:03:32.938916 LPDDR4 DRAM CONFIGURATION
6057 23:03:32.942522 ===================================
6058 23:03:32.944934 EX_ROW_EN[0] = 0x0
6059 23:03:32.945003 EX_ROW_EN[1] = 0x0
6060 23:03:32.948669 LP4Y_EN = 0x0
6061 23:03:32.948745 WORK_FSP = 0x0
6062 23:03:32.951702 WL = 0x2
6063 23:03:32.951852 RL = 0x2
6064 23:03:32.955596 BL = 0x2
6065 23:03:32.955690 RPST = 0x0
6066 23:03:32.958838 RD_PRE = 0x0
6067 23:03:32.958934 WR_PRE = 0x1
6068 23:03:32.962084 WR_PST = 0x0
6069 23:03:32.962151 DBI_WR = 0x0
6070 23:03:32.965242 DBI_RD = 0x0
6071 23:03:32.965363 OTF = 0x1
6072 23:03:32.968799 ===================================
6073 23:03:32.971876 ===================================
6074 23:03:32.975442 ANA top config
6075 23:03:32.978448 ===================================
6076 23:03:32.981688 DLL_ASYNC_EN = 0
6077 23:03:32.981762 ALL_SLAVE_EN = 1
6078 23:03:32.985490 NEW_RANK_MODE = 1
6079 23:03:32.989132 DLL_IDLE_MODE = 1
6080 23:03:32.992345 LP45_APHY_COMB_EN = 1
6081 23:03:32.992417 TX_ODT_DIS = 1
6082 23:03:32.995421 NEW_8X_MODE = 1
6083 23:03:32.998953 ===================================
6084 23:03:33.002286 ===================================
6085 23:03:33.005199 data_rate = 800
6086 23:03:33.008560 CKR = 1
6087 23:03:33.012002 DQ_P2S_RATIO = 4
6088 23:03:33.015584 ===================================
6089 23:03:33.019043 CA_P2S_RATIO = 4
6090 23:03:33.019115 DQ_CA_OPEN = 0
6091 23:03:33.021786 DQ_SEMI_OPEN = 1
6092 23:03:33.025451 CA_SEMI_OPEN = 1
6093 23:03:33.028941 CA_FULL_RATE = 0
6094 23:03:33.032292 DQ_CKDIV4_EN = 0
6095 23:03:33.035233 CA_CKDIV4_EN = 1
6096 23:03:33.035305 CA_PREDIV_EN = 0
6097 23:03:33.038937 PH8_DLY = 0
6098 23:03:33.042307 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6099 23:03:33.045266 DQ_AAMCK_DIV = 0
6100 23:03:33.049129 CA_AAMCK_DIV = 0
6101 23:03:33.049241 CA_ADMCK_DIV = 4
6102 23:03:33.052030 DQ_TRACK_CA_EN = 0
6103 23:03:33.055345 CA_PICK = 800
6104 23:03:33.059107 CA_MCKIO = 400
6105 23:03:33.062333 MCKIO_SEMI = 400
6106 23:03:33.065513 PLL_FREQ = 3016
6107 23:03:33.068832 DQ_UI_PI_RATIO = 32
6108 23:03:33.072235 CA_UI_PI_RATIO = 32
6109 23:03:33.075311 ===================================
6110 23:03:33.075397 ===================================
6111 23:03:33.078741 memory_type:LPDDR4
6112 23:03:33.081994 GP_NUM : 10
6113 23:03:33.082088 SRAM_EN : 1
6114 23:03:33.085496 MD32_EN : 0
6115 23:03:33.088861 ===================================
6116 23:03:33.092553 [ANA_INIT] >>>>>>>>>>>>>>
6117 23:03:33.095468 <<<<<< [CONFIGURE PHASE]: ANA_TX
6118 23:03:33.098853 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6119 23:03:33.101980 ===================================
6120 23:03:33.102054 data_rate = 800,PCW = 0X7400
6121 23:03:33.105714 ===================================
6122 23:03:33.108729 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6123 23:03:33.115508 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6124 23:03:33.125863 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6125 23:03:33.132335 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6126 23:03:33.135900 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6127 23:03:33.139229 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6128 23:03:33.142419 [ANA_INIT] flow start
6129 23:03:33.142498 [ANA_INIT] PLL >>>>>>>>
6130 23:03:33.145980 [ANA_INIT] PLL <<<<<<<<
6131 23:03:33.148840 [ANA_INIT] MIDPI >>>>>>>>
6132 23:03:33.148915 [ANA_INIT] MIDPI <<<<<<<<
6133 23:03:33.152626 [ANA_INIT] DLL >>>>>>>>
6134 23:03:33.156073 [ANA_INIT] flow end
6135 23:03:33.158890 ============ LP4 DIFF to SE enter ============
6136 23:03:33.162321 ============ LP4 DIFF to SE exit ============
6137 23:03:33.165630 [ANA_INIT] <<<<<<<<<<<<<
6138 23:03:33.168826 [Flow] Enable top DCM control >>>>>
6139 23:03:33.172267 [Flow] Enable top DCM control <<<<<
6140 23:03:33.176049 Enable DLL master slave shuffle
6141 23:03:33.178846 ==============================================================
6142 23:03:33.182455 Gating Mode config
6143 23:03:33.185741 ==============================================================
6144 23:03:33.189166 Config description:
6145 23:03:33.198833 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6146 23:03:33.205451 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6147 23:03:33.209051 SELPH_MODE 0: By rank 1: By Phase
6148 23:03:33.215421 ==============================================================
6149 23:03:33.218986 GAT_TRACK_EN = 0
6150 23:03:33.222474 RX_GATING_MODE = 2
6151 23:03:33.226043 RX_GATING_TRACK_MODE = 2
6152 23:03:33.229158 SELPH_MODE = 1
6153 23:03:33.229239 PICG_EARLY_EN = 1
6154 23:03:33.232557 VALID_LAT_VALUE = 1
6155 23:03:33.239518 ==============================================================
6156 23:03:33.242220 Enter into Gating configuration >>>>
6157 23:03:33.245538 Exit from Gating configuration <<<<
6158 23:03:33.249359 Enter into DVFS_PRE_config >>>>>
6159 23:03:33.259246 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6160 23:03:33.262741 Exit from DVFS_PRE_config <<<<<
6161 23:03:33.266052 Enter into PICG configuration >>>>
6162 23:03:33.269342 Exit from PICG configuration <<<<
6163 23:03:33.272335 [RX_INPUT] configuration >>>>>
6164 23:03:33.275593 [RX_INPUT] configuration <<<<<
6165 23:03:33.279312 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6166 23:03:33.286093 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6167 23:03:33.292380 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6168 23:03:33.299166 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6169 23:03:33.302811 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6170 23:03:33.308950 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6171 23:03:33.312658 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6172 23:03:33.319239 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6173 23:03:33.322517 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6174 23:03:33.325935 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6175 23:03:33.330003 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6176 23:03:33.336124 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6177 23:03:33.339276 ===================================
6178 23:03:33.339353 LPDDR4 DRAM CONFIGURATION
6179 23:03:33.342761 ===================================
6180 23:03:33.345977 EX_ROW_EN[0] = 0x0
6181 23:03:33.349637 EX_ROW_EN[1] = 0x0
6182 23:03:33.349712 LP4Y_EN = 0x0
6183 23:03:33.352916 WORK_FSP = 0x0
6184 23:03:33.352993 WL = 0x2
6185 23:03:33.355734 RL = 0x2
6186 23:03:33.355806 BL = 0x2
6187 23:03:33.359225 RPST = 0x0
6188 23:03:33.359300 RD_PRE = 0x0
6189 23:03:33.362691 WR_PRE = 0x1
6190 23:03:33.362796 WR_PST = 0x0
6191 23:03:33.366198 DBI_WR = 0x0
6192 23:03:33.366278 DBI_RD = 0x0
6193 23:03:33.369301 OTF = 0x1
6194 23:03:33.372270 ===================================
6195 23:03:33.375611 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6196 23:03:33.379080 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6197 23:03:33.385862 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6198 23:03:33.389145 ===================================
6199 23:03:33.389219 LPDDR4 DRAM CONFIGURATION
6200 23:03:33.392362 ===================================
6201 23:03:33.395653 EX_ROW_EN[0] = 0x10
6202 23:03:33.399157 EX_ROW_EN[1] = 0x0
6203 23:03:33.399228 LP4Y_EN = 0x0
6204 23:03:33.402454 WORK_FSP = 0x0
6205 23:03:33.402527 WL = 0x2
6206 23:03:33.405558 RL = 0x2
6207 23:03:33.405628 BL = 0x2
6208 23:03:33.408985 RPST = 0x0
6209 23:03:33.409060 RD_PRE = 0x0
6210 23:03:33.412394 WR_PRE = 0x1
6211 23:03:33.412467 WR_PST = 0x0
6212 23:03:33.415840 DBI_WR = 0x0
6213 23:03:33.415916 DBI_RD = 0x0
6214 23:03:33.419323 OTF = 0x1
6215 23:03:33.422496 ===================================
6216 23:03:33.429153 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6217 23:03:33.432655 nWR fixed to 30
6218 23:03:33.432734 [ModeRegInit_LP4] CH0 RK0
6219 23:03:33.436019 [ModeRegInit_LP4] CH0 RK1
6220 23:03:33.439187 [ModeRegInit_LP4] CH1 RK0
6221 23:03:33.439266 [ModeRegInit_LP4] CH1 RK1
6222 23:03:33.442387 match AC timing 19
6223 23:03:33.445774 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6224 23:03:33.448916 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6225 23:03:33.455871 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6226 23:03:33.459464 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6227 23:03:33.466125 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6228 23:03:33.466248 ==
6229 23:03:33.469254 Dram Type= 6, Freq= 0, CH_0, rank 0
6230 23:03:33.472374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6231 23:03:33.472453 ==
6232 23:03:33.479065 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6233 23:03:33.482392 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6234 23:03:33.485808 [CA 0] Center 36 (8~64) winsize 57
6235 23:03:33.489224 [CA 1] Center 36 (8~64) winsize 57
6236 23:03:33.492498 [CA 2] Center 36 (8~64) winsize 57
6237 23:03:33.495834 [CA 3] Center 36 (8~64) winsize 57
6238 23:03:33.499363 [CA 4] Center 36 (8~64) winsize 57
6239 23:03:33.502812 [CA 5] Center 36 (8~64) winsize 57
6240 23:03:33.502931
6241 23:03:33.506375 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6242 23:03:33.506487
6243 23:03:33.509064 [CATrainingPosCal] consider 1 rank data
6244 23:03:33.512546 u2DelayCellTimex100 = 270/100 ps
6245 23:03:33.515619 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6246 23:03:33.518948 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6247 23:03:33.522386 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6248 23:03:33.529182 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6249 23:03:33.532826 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 23:03:33.536488 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6251 23:03:33.536601
6252 23:03:33.539096 CA PerBit enable=1, Macro0, CA PI delay=36
6253 23:03:33.539181
6254 23:03:33.542761 [CBTSetCACLKResult] CA Dly = 36
6255 23:03:33.542837 CS Dly: 1 (0~32)
6256 23:03:33.542953 ==
6257 23:03:33.546107 Dram Type= 6, Freq= 0, CH_0, rank 1
6258 23:03:33.552373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6259 23:03:33.552455 ==
6260 23:03:33.556089 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6261 23:03:33.562446 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6262 23:03:33.566189 [CA 0] Center 36 (8~64) winsize 57
6263 23:03:33.569350 [CA 1] Center 36 (8~64) winsize 57
6264 23:03:33.572891 [CA 2] Center 36 (8~64) winsize 57
6265 23:03:33.576189 [CA 3] Center 36 (8~64) winsize 57
6266 23:03:33.579055 [CA 4] Center 36 (8~64) winsize 57
6267 23:03:33.582503 [CA 5] Center 36 (8~64) winsize 57
6268 23:03:33.582585
6269 23:03:33.586203 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6270 23:03:33.586286
6271 23:03:33.589588 [CATrainingPosCal] consider 2 rank data
6272 23:03:33.592901 u2DelayCellTimex100 = 270/100 ps
6273 23:03:33.595777 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6274 23:03:33.599373 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6275 23:03:33.602570 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6276 23:03:33.606125 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6277 23:03:33.609446 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6278 23:03:33.612928 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6279 23:03:33.613011
6280 23:03:33.615660 CA PerBit enable=1, Macro0, CA PI delay=36
6281 23:03:33.619012
6282 23:03:33.619094 [CBTSetCACLKResult] CA Dly = 36
6283 23:03:33.622750 CS Dly: 1 (0~32)
6284 23:03:33.622841
6285 23:03:33.626025 ----->DramcWriteLeveling(PI) begin...
6286 23:03:33.626109 ==
6287 23:03:33.628992 Dram Type= 6, Freq= 0, CH_0, rank 0
6288 23:03:33.632899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6289 23:03:33.632983 ==
6290 23:03:33.635785 Write leveling (Byte 0): 40 => 8
6291 23:03:33.639333 Write leveling (Byte 1): 32 => 0
6292 23:03:33.642225 DramcWriteLeveling(PI) end<-----
6293 23:03:33.642308
6294 23:03:33.642374 ==
6295 23:03:33.645868 Dram Type= 6, Freq= 0, CH_0, rank 0
6296 23:03:33.649188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6297 23:03:33.649272 ==
6298 23:03:33.652234 [Gating] SW mode calibration
6299 23:03:33.659345 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6300 23:03:33.665678 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6301 23:03:33.669219 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6302 23:03:33.676231 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6303 23:03:33.679222 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6304 23:03:33.682455 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6305 23:03:33.685650 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6306 23:03:33.692592 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6307 23:03:33.696239 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6308 23:03:33.699517 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6309 23:03:33.705957 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6310 23:03:33.709385 Total UI for P1: 0, mck2ui 16
6311 23:03:33.712514 best dqsien dly found for B0: ( 0, 14, 24)
6312 23:03:33.712587 Total UI for P1: 0, mck2ui 16
6313 23:03:33.719082 best dqsien dly found for B1: ( 0, 14, 24)
6314 23:03:33.722844 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6315 23:03:33.726289 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6316 23:03:33.726357
6317 23:03:33.729668 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6318 23:03:33.732659 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6319 23:03:33.735836 [Gating] SW calibration Done
6320 23:03:33.735906 ==
6321 23:03:33.739646 Dram Type= 6, Freq= 0, CH_0, rank 0
6322 23:03:33.742998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6323 23:03:33.743066 ==
6324 23:03:33.745758 RX Vref Scan: 0
6325 23:03:33.745834
6326 23:03:33.745893 RX Vref 0 -> 0, step: 1
6327 23:03:33.745950
6328 23:03:33.749335 RX Delay -410 -> 252, step: 16
6329 23:03:33.756083 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6330 23:03:33.759607 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6331 23:03:33.762798 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6332 23:03:33.765883 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6333 23:03:33.772711 iDelay=230, Bit 4, Center -19 (-266 ~ 229) 496
6334 23:03:33.776244 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6335 23:03:33.779241 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6336 23:03:33.782781 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6337 23:03:33.789339 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6338 23:03:33.792622 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6339 23:03:33.796198 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6340 23:03:33.799668 iDelay=230, Bit 11, Center -43 (-282 ~ 197) 480
6341 23:03:33.803159 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6342 23:03:33.809617 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6343 23:03:33.813150 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6344 23:03:33.816472 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6345 23:03:33.816554 ==
6346 23:03:33.819884 Dram Type= 6, Freq= 0, CH_0, rank 0
6347 23:03:33.826372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6348 23:03:33.826482 ==
6349 23:03:33.826580 DQS Delay:
6350 23:03:33.830219 DQS0 = 35, DQS1 = 51
6351 23:03:33.830301 DQM Delay:
6352 23:03:33.830393 DQM0 = 8, DQM1 = 11
6353 23:03:33.832990 DQ Delay:
6354 23:03:33.836353 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6355 23:03:33.836435 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6356 23:03:33.839747 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6357 23:03:33.843184 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6358 23:03:33.843266
6359 23:03:33.846434
6360 23:03:33.846514 ==
6361 23:03:33.849396 Dram Type= 6, Freq= 0, CH_0, rank 0
6362 23:03:33.852881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6363 23:03:33.852962 ==
6364 23:03:33.853026
6365 23:03:33.853084
6366 23:03:33.856642 TX Vref Scan disable
6367 23:03:33.856750 == TX Byte 0 ==
6368 23:03:33.859642 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6369 23:03:33.866482 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6370 23:03:33.866591 == TX Byte 1 ==
6371 23:03:33.869187 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6372 23:03:33.876436 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6373 23:03:33.876516 ==
6374 23:03:33.879070 Dram Type= 6, Freq= 0, CH_0, rank 0
6375 23:03:33.882693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6376 23:03:33.882804 ==
6377 23:03:33.882929
6378 23:03:33.882990
6379 23:03:33.885975 TX Vref Scan disable
6380 23:03:33.886046 == TX Byte 0 ==
6381 23:03:33.889424 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6382 23:03:33.895904 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6383 23:03:33.895980 == TX Byte 1 ==
6384 23:03:33.899280 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6385 23:03:33.906282 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6386 23:03:33.906357
6387 23:03:33.906418 [DATLAT]
6388 23:03:33.906483 Freq=400, CH0 RK0
6389 23:03:33.909316
6390 23:03:33.909403 DATLAT Default: 0xf
6391 23:03:33.912620 0, 0xFFFF, sum = 0
6392 23:03:33.912689 1, 0xFFFF, sum = 0
6393 23:03:33.916173 2, 0xFFFF, sum = 0
6394 23:03:33.916248 3, 0xFFFF, sum = 0
6395 23:03:33.919672 4, 0xFFFF, sum = 0
6396 23:03:33.919748 5, 0xFFFF, sum = 0
6397 23:03:33.922718 6, 0xFFFF, sum = 0
6398 23:03:33.922822 7, 0xFFFF, sum = 0
6399 23:03:33.926169 8, 0xFFFF, sum = 0
6400 23:03:33.926245 9, 0xFFFF, sum = 0
6401 23:03:33.929634 10, 0xFFFF, sum = 0
6402 23:03:33.929742 11, 0xFFFF, sum = 0
6403 23:03:33.932582 12, 0xFFFF, sum = 0
6404 23:03:33.932650 13, 0x0, sum = 1
6405 23:03:33.936269 14, 0x0, sum = 2
6406 23:03:33.936343 15, 0x0, sum = 3
6407 23:03:33.939385 16, 0x0, sum = 4
6408 23:03:33.939451 best_step = 14
6409 23:03:33.939510
6410 23:03:33.939565 ==
6411 23:03:33.942778 Dram Type= 6, Freq= 0, CH_0, rank 0
6412 23:03:33.949651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6413 23:03:33.949730 ==
6414 23:03:33.949790 RX Vref Scan: 1
6415 23:03:33.949847
6416 23:03:33.952569 RX Vref 0 -> 0, step: 1
6417 23:03:33.952639
6418 23:03:33.955883 RX Delay -343 -> 252, step: 8
6419 23:03:33.955951
6420 23:03:33.959422 Set Vref, RX VrefLevel [Byte0]: 53
6421 23:03:33.962707 [Byte1]: 50
6422 23:03:33.962778
6423 23:03:33.966231 Final RX Vref Byte 0 = 53 to rank0
6424 23:03:33.969612 Final RX Vref Byte 1 = 50 to rank0
6425 23:03:33.972715 Final RX Vref Byte 0 = 53 to rank1
6426 23:03:33.976105 Final RX Vref Byte 1 = 50 to rank1==
6427 23:03:33.979990 Dram Type= 6, Freq= 0, CH_0, rank 0
6428 23:03:33.982540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6429 23:03:33.982614 ==
6430 23:03:33.986051 DQS Delay:
6431 23:03:33.986124 DQS0 = 44, DQS1 = 60
6432 23:03:33.989418 DQM Delay:
6433 23:03:33.989490 DQM0 = 11, DQM1 = 15
6434 23:03:33.989551 DQ Delay:
6435 23:03:33.993158 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =8
6436 23:03:33.996092 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6437 23:03:33.999474 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =8
6438 23:03:34.002828 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =28
6439 23:03:34.002927
6440 23:03:34.002990
6441 23:03:34.012660 [DQSOSCAuto] RK0, (LSB)MR18= 0x8654, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 393 ps
6442 23:03:34.016597 CH0 RK0: MR19=C0C, MR18=8654
6443 23:03:34.019248 CH0_RK0: MR19=0xC0C, MR18=0x8654, DQSOSC=393, MR23=63, INC=382, DEC=254
6444 23:03:34.022713 ==
6445 23:03:34.022788 Dram Type= 6, Freq= 0, CH_0, rank 1
6446 23:03:34.029601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6447 23:03:34.029703 ==
6448 23:03:34.032609 [Gating] SW mode calibration
6449 23:03:34.039685 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6450 23:03:34.042973 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6451 23:03:34.049865 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6452 23:03:34.052493 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6453 23:03:34.055957 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6454 23:03:34.063015 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6455 23:03:34.066279 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6456 23:03:34.069509 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6457 23:03:34.072825 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6458 23:03:34.079761 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6459 23:03:34.082615 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6460 23:03:34.086610 Total UI for P1: 0, mck2ui 16
6461 23:03:34.089750 best dqsien dly found for B0: ( 0, 14, 24)
6462 23:03:34.093149 Total UI for P1: 0, mck2ui 16
6463 23:03:34.096416 best dqsien dly found for B1: ( 0, 14, 24)
6464 23:03:34.100105 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6465 23:03:34.102769 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6466 23:03:34.102873
6467 23:03:34.106152 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6468 23:03:34.109944 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6469 23:03:34.113071 [Gating] SW calibration Done
6470 23:03:34.113151 ==
6471 23:03:34.116236 Dram Type= 6, Freq= 0, CH_0, rank 1
6472 23:03:34.122771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6473 23:03:34.122903 ==
6474 23:03:34.122985 RX Vref Scan: 0
6475 23:03:34.123046
6476 23:03:34.126085 RX Vref 0 -> 0, step: 1
6477 23:03:34.126166
6478 23:03:34.129559 RX Delay -410 -> 252, step: 16
6479 23:03:34.132987 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6480 23:03:34.136120 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6481 23:03:34.139721 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6482 23:03:34.146040 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6483 23:03:34.149607 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6484 23:03:34.153293 iDelay=230, Bit 5, Center -43 (-282 ~ 197) 480
6485 23:03:34.156147 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6486 23:03:34.163248 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6487 23:03:34.166174 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6488 23:03:34.169478 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6489 23:03:34.172844 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6490 23:03:34.179704 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6491 23:03:34.183292 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6492 23:03:34.186666 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6493 23:03:34.189420 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6494 23:03:34.196311 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6495 23:03:34.196393 ==
6496 23:03:34.200044 Dram Type= 6, Freq= 0, CH_0, rank 1
6497 23:03:34.202899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6498 23:03:34.202981 ==
6499 23:03:34.203046 DQS Delay:
6500 23:03:34.206473 DQS0 = 43, DQS1 = 51
6501 23:03:34.206553 DQM Delay:
6502 23:03:34.210171 DQM0 = 11, DQM1 = 10
6503 23:03:34.210252 DQ Delay:
6504 23:03:34.212805 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6505 23:03:34.216397 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6506 23:03:34.219930 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6507 23:03:34.223094 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6508 23:03:34.223175
6509 23:03:34.223247
6510 23:03:34.223307 ==
6511 23:03:34.226299 Dram Type= 6, Freq= 0, CH_0, rank 1
6512 23:03:34.229653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6513 23:03:34.229742 ==
6514 23:03:34.229807
6515 23:03:34.229867
6516 23:03:34.233049 TX Vref Scan disable
6517 23:03:34.233165 == TX Byte 0 ==
6518 23:03:34.239971 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6519 23:03:34.243445 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6520 23:03:34.243522 == TX Byte 1 ==
6521 23:03:34.249599 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6522 23:03:34.253283 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6523 23:03:34.253356 ==
6524 23:03:34.256671 Dram Type= 6, Freq= 0, CH_0, rank 1
6525 23:03:34.259745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6526 23:03:34.259849 ==
6527 23:03:34.259938
6528 23:03:34.260023
6529 23:03:34.262917 TX Vref Scan disable
6530 23:03:34.263033 == TX Byte 0 ==
6531 23:03:34.270167 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6532 23:03:34.273359 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6533 23:03:34.273435 == TX Byte 1 ==
6534 23:03:34.279968 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6535 23:03:34.282931 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6536 23:03:34.283002
6537 23:03:34.283063 [DATLAT]
6538 23:03:34.286281 Freq=400, CH0 RK1
6539 23:03:34.286351
6540 23:03:34.286409 DATLAT Default: 0xe
6541 23:03:34.289941 0, 0xFFFF, sum = 0
6542 23:03:34.290012 1, 0xFFFF, sum = 0
6543 23:03:34.293241 2, 0xFFFF, sum = 0
6544 23:03:34.293312 3, 0xFFFF, sum = 0
6545 23:03:34.296566 4, 0xFFFF, sum = 0
6546 23:03:34.296643 5, 0xFFFF, sum = 0
6547 23:03:34.299686 6, 0xFFFF, sum = 0
6548 23:03:34.299754 7, 0xFFFF, sum = 0
6549 23:03:34.303190 8, 0xFFFF, sum = 0
6550 23:03:34.303271 9, 0xFFFF, sum = 0
6551 23:03:34.306477 10, 0xFFFF, sum = 0
6552 23:03:34.309853 11, 0xFFFF, sum = 0
6553 23:03:34.309935 12, 0xFFFF, sum = 0
6554 23:03:34.312812 13, 0x0, sum = 1
6555 23:03:34.312893 14, 0x0, sum = 2
6556 23:03:34.312959 15, 0x0, sum = 3
6557 23:03:34.316421 16, 0x0, sum = 4
6558 23:03:34.316503 best_step = 14
6559 23:03:34.316577
6560 23:03:34.319673 ==
6561 23:03:34.319754 Dram Type= 6, Freq= 0, CH_0, rank 1
6562 23:03:34.326334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6563 23:03:34.326416 ==
6564 23:03:34.326481 RX Vref Scan: 0
6565 23:03:34.326541
6566 23:03:34.329637 RX Vref 0 -> 0, step: 1
6567 23:03:34.329717
6568 23:03:34.332618 RX Delay -343 -> 252, step: 8
6569 23:03:34.339695 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6570 23:03:34.343132 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6571 23:03:34.346427 iDelay=217, Bit 2, Center -36 (-271 ~ 200) 472
6572 23:03:34.349759 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6573 23:03:34.356748 iDelay=217, Bit 4, Center -36 (-271 ~ 200) 472
6574 23:03:34.359764 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6575 23:03:34.363080 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6576 23:03:34.366215 iDelay=217, Bit 7, Center -28 (-263 ~ 208) 472
6577 23:03:34.373001 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6578 23:03:34.376424 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6579 23:03:34.379892 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6580 23:03:34.382924 iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480
6581 23:03:34.389793 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6582 23:03:34.392832 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6583 23:03:34.396350 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6584 23:03:34.399697 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6585 23:03:34.403255 ==
6586 23:03:34.406798 Dram Type= 6, Freq= 0, CH_0, rank 1
6587 23:03:34.409538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6588 23:03:34.409610 ==
6589 23:03:34.409671 DQS Delay:
6590 23:03:34.412868 DQS0 = 48, DQS1 = 60
6591 23:03:34.412938 DQM Delay:
6592 23:03:34.416793 DQM0 = 13, DQM1 = 13
6593 23:03:34.416881 DQ Delay:
6594 23:03:34.419638 DQ0 =16, DQ1 =16, DQ2 =12, DQ3 =12
6595 23:03:34.423156 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6596 23:03:34.426453 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6597 23:03:34.430048 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =24
6598 23:03:34.430154
6599 23:03:34.430246
6600 23:03:34.436676 [DQSOSCAuto] RK1, (LSB)MR18= 0x9062, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 391 ps
6601 23:03:34.439563 CH0 RK1: MR19=C0C, MR18=9062
6602 23:03:34.446267 CH0_RK1: MR19=0xC0C, MR18=0x9062, DQSOSC=391, MR23=63, INC=386, DEC=257
6603 23:03:34.449552 [RxdqsGatingPostProcess] freq 400
6604 23:03:34.453418 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6605 23:03:34.456509 best DQS0 dly(2T, 0.5T) = (0, 10)
6606 23:03:34.459694 best DQS1 dly(2T, 0.5T) = (0, 10)
6607 23:03:34.463288 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6608 23:03:34.466691 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6609 23:03:34.469838 best DQS0 dly(2T, 0.5T) = (0, 10)
6610 23:03:34.473362 best DQS1 dly(2T, 0.5T) = (0, 10)
6611 23:03:34.476722 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6612 23:03:34.480050 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6613 23:03:34.483268 Pre-setting of DQS Precalculation
6614 23:03:34.486869 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6615 23:03:34.486952 ==
6616 23:03:34.490527 Dram Type= 6, Freq= 0, CH_1, rank 0
6617 23:03:34.496889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6618 23:03:34.497009 ==
6619 23:03:34.499840 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6620 23:03:34.506730 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6621 23:03:34.510070 [CA 0] Center 36 (8~64) winsize 57
6622 23:03:34.513643 [CA 1] Center 36 (8~64) winsize 57
6623 23:03:34.517254 [CA 2] Center 36 (8~64) winsize 57
6624 23:03:34.520028 [CA 3] Center 36 (8~64) winsize 57
6625 23:03:34.523437 [CA 4] Center 36 (8~64) winsize 57
6626 23:03:34.527020 [CA 5] Center 36 (8~64) winsize 57
6627 23:03:34.527099
6628 23:03:34.529903 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6629 23:03:34.529979
6630 23:03:34.533727 [CATrainingPosCal] consider 1 rank data
6631 23:03:34.537136 u2DelayCellTimex100 = 270/100 ps
6632 23:03:34.540085 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6633 23:03:34.543367 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6634 23:03:34.547034 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6635 23:03:34.550225 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6636 23:03:34.553636 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 23:03:34.556632 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6638 23:03:34.556733
6639 23:03:34.563562 CA PerBit enable=1, Macro0, CA PI delay=36
6640 23:03:34.563639
6641 23:03:34.563703 [CBTSetCACLKResult] CA Dly = 36
6642 23:03:34.567004 CS Dly: 1 (0~32)
6643 23:03:34.567108 ==
6644 23:03:34.570573 Dram Type= 6, Freq= 0, CH_1, rank 1
6645 23:03:34.573482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6646 23:03:34.573561 ==
6647 23:03:34.580606 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6648 23:03:34.586938 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6649 23:03:34.590325 [CA 0] Center 36 (8~64) winsize 57
6650 23:03:34.593516 [CA 1] Center 36 (8~64) winsize 57
6651 23:03:34.593591 [CA 2] Center 36 (8~64) winsize 57
6652 23:03:34.597284 [CA 3] Center 36 (8~64) winsize 57
6653 23:03:34.600708 [CA 4] Center 36 (8~64) winsize 57
6654 23:03:34.603687 [CA 5] Center 36 (8~64) winsize 57
6655 23:03:34.603759
6656 23:03:34.607390 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6657 23:03:34.607471
6658 23:03:34.613652 [CATrainingPosCal] consider 2 rank data
6659 23:03:34.613733 u2DelayCellTimex100 = 270/100 ps
6660 23:03:34.617004 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6661 23:03:34.624240 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6662 23:03:34.626960 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6663 23:03:34.630854 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6664 23:03:34.634108 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6665 23:03:34.637393 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6666 23:03:34.637486
6667 23:03:34.640546 CA PerBit enable=1, Macro0, CA PI delay=36
6668 23:03:34.640651
6669 23:03:34.643889 [CBTSetCACLKResult] CA Dly = 36
6670 23:03:34.643990 CS Dly: 1 (0~32)
6671 23:03:34.644080
6672 23:03:34.647408 ----->DramcWriteLeveling(PI) begin...
6673 23:03:34.651038 ==
6674 23:03:34.653872 Dram Type= 6, Freq= 0, CH_1, rank 0
6675 23:03:34.657231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6676 23:03:34.657341 ==
6677 23:03:34.660626 Write leveling (Byte 0): 40 => 8
6678 23:03:34.664100 Write leveling (Byte 1): 40 => 8
6679 23:03:34.667042 DramcWriteLeveling(PI) end<-----
6680 23:03:34.667128
6681 23:03:34.667193 ==
6682 23:03:34.670325 Dram Type= 6, Freq= 0, CH_1, rank 0
6683 23:03:34.674474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6684 23:03:34.674548 ==
6685 23:03:34.677272 [Gating] SW mode calibration
6686 23:03:34.684061 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6687 23:03:34.687755 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6688 23:03:34.693613 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6689 23:03:34.697000 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6690 23:03:34.700734 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6691 23:03:34.707083 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6692 23:03:34.710497 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6693 23:03:34.713598 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6694 23:03:34.720500 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6695 23:03:34.723981 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6696 23:03:34.727752 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6697 23:03:34.730370 Total UI for P1: 0, mck2ui 16
6698 23:03:34.733633 best dqsien dly found for B0: ( 0, 14, 24)
6699 23:03:34.737031 Total UI for P1: 0, mck2ui 16
6700 23:03:34.740102 best dqsien dly found for B1: ( 0, 14, 24)
6701 23:03:34.743609 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6702 23:03:34.747250 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6703 23:03:34.747326
6704 23:03:34.753813 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6705 23:03:34.757249 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6706 23:03:34.757322 [Gating] SW calibration Done
6707 23:03:34.760721 ==
6708 23:03:34.763797 Dram Type= 6, Freq= 0, CH_1, rank 0
6709 23:03:34.767387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6710 23:03:34.767488 ==
6711 23:03:34.767577 RX Vref Scan: 0
6712 23:03:34.767650
6713 23:03:34.769991 RX Vref 0 -> 0, step: 1
6714 23:03:34.770062
6715 23:03:34.773412 RX Delay -410 -> 252, step: 16
6716 23:03:34.776834 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6717 23:03:34.783735 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6718 23:03:34.787501 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6719 23:03:34.789927 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6720 23:03:34.793291 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6721 23:03:34.800311 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6722 23:03:34.803301 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6723 23:03:34.806976 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6724 23:03:34.810143 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6725 23:03:34.814042 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6726 23:03:34.820365 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6727 23:03:34.823417 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6728 23:03:34.827048 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6729 23:03:34.833404 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6730 23:03:34.836746 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6731 23:03:34.840056 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6732 23:03:34.840137 ==
6733 23:03:34.843617 Dram Type= 6, Freq= 0, CH_1, rank 0
6734 23:03:34.847025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6735 23:03:34.847106 ==
6736 23:03:34.850500 DQS Delay:
6737 23:03:34.850580 DQS0 = 51, DQS1 = 59
6738 23:03:34.853930 DQM Delay:
6739 23:03:34.854011 DQM0 = 19, DQM1 = 17
6740 23:03:34.857258 DQ Delay:
6741 23:03:34.857338 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6742 23:03:34.860499 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6743 23:03:34.863650 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6744 23:03:34.866961 DQ12 =32, DQ13 =24, DQ14 =24, DQ15 =24
6745 23:03:34.867076
6746 23:03:34.867158
6747 23:03:34.867249 ==
6748 23:03:34.870449 Dram Type= 6, Freq= 0, CH_1, rank 0
6749 23:03:34.876698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6750 23:03:34.876779 ==
6751 23:03:34.876854
6752 23:03:34.876915
6753 23:03:34.876971 TX Vref Scan disable
6754 23:03:34.880565 == TX Byte 0 ==
6755 23:03:34.883800 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6756 23:03:34.886878 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6757 23:03:34.890275 == TX Byte 1 ==
6758 23:03:34.893493 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6759 23:03:34.897019 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6760 23:03:34.897114 ==
6761 23:03:34.900392 Dram Type= 6, Freq= 0, CH_1, rank 0
6762 23:03:34.906874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6763 23:03:34.906982 ==
6764 23:03:34.907090
6765 23:03:34.907150
6766 23:03:34.907208 TX Vref Scan disable
6767 23:03:34.910367 == TX Byte 0 ==
6768 23:03:34.913791 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6769 23:03:34.916994 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6770 23:03:34.920498 == TX Byte 1 ==
6771 23:03:34.923941 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6772 23:03:34.927766 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6773 23:03:34.927840
6774 23:03:34.930611 [DATLAT]
6775 23:03:34.930709 Freq=400, CH1 RK0
6776 23:03:34.930805
6777 23:03:34.933902 DATLAT Default: 0xf
6778 23:03:34.934010 0, 0xFFFF, sum = 0
6779 23:03:34.937596 1, 0xFFFF, sum = 0
6780 23:03:34.937670 2, 0xFFFF, sum = 0
6781 23:03:34.940787 3, 0xFFFF, sum = 0
6782 23:03:34.940923 4, 0xFFFF, sum = 0
6783 23:03:34.944005 5, 0xFFFF, sum = 0
6784 23:03:34.944081 6, 0xFFFF, sum = 0
6785 23:03:34.947100 7, 0xFFFF, sum = 0
6786 23:03:34.947183 8, 0xFFFF, sum = 0
6787 23:03:34.950520 9, 0xFFFF, sum = 0
6788 23:03:34.950616 10, 0xFFFF, sum = 0
6789 23:03:34.954075 11, 0xFFFF, sum = 0
6790 23:03:34.954159 12, 0xFFFF, sum = 0
6791 23:03:34.957512 13, 0x0, sum = 1
6792 23:03:34.957596 14, 0x0, sum = 2
6793 23:03:34.960845 15, 0x0, sum = 3
6794 23:03:34.960929 16, 0x0, sum = 4
6795 23:03:34.963925 best_step = 14
6796 23:03:34.964008
6797 23:03:34.964074 ==
6798 23:03:34.967246 Dram Type= 6, Freq= 0, CH_1, rank 0
6799 23:03:34.970519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6800 23:03:34.970602 ==
6801 23:03:34.973857 RX Vref Scan: 1
6802 23:03:34.973946
6803 23:03:34.974011 RX Vref 0 -> 0, step: 1
6804 23:03:34.974072
6805 23:03:34.977201 RX Delay -359 -> 252, step: 8
6806 23:03:34.977284
6807 23:03:34.980869 Set Vref, RX VrefLevel [Byte0]: 60
6808 23:03:34.983730 [Byte1]: 51
6809 23:03:34.988896
6810 23:03:34.988979 Final RX Vref Byte 0 = 60 to rank0
6811 23:03:34.991920 Final RX Vref Byte 1 = 51 to rank0
6812 23:03:34.995185 Final RX Vref Byte 0 = 60 to rank1
6813 23:03:34.999105 Final RX Vref Byte 1 = 51 to rank1==
6814 23:03:35.002196 Dram Type= 6, Freq= 0, CH_1, rank 0
6815 23:03:35.008764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6816 23:03:35.008845 ==
6817 23:03:35.008911 DQS Delay:
6818 23:03:35.012271 DQS0 = 48, DQS1 = 60
6819 23:03:35.012345 DQM Delay:
6820 23:03:35.012407 DQM0 = 12, DQM1 = 12
6821 23:03:35.015573 DQ Delay:
6822 23:03:35.018588 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6823 23:03:35.018660 DQ4 =8, DQ5 =20, DQ6 =24, DQ7 =8
6824 23:03:35.022193 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6825 23:03:35.025789 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6826 23:03:35.025867
6827 23:03:35.025931
6828 23:03:35.035526 [DQSOSCAuto] RK0, (LSB)MR18= 0x882f, (MSB)MR19= 0xc0c, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
6829 23:03:35.039202 CH1 RK0: MR19=C0C, MR18=882F
6830 23:03:35.045612 CH1_RK0: MR19=0xC0C, MR18=0x882F, DQSOSC=392, MR23=63, INC=384, DEC=256
6831 23:03:35.045689 ==
6832 23:03:35.049281 Dram Type= 6, Freq= 0, CH_1, rank 1
6833 23:03:35.052564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6834 23:03:35.052636 ==
6835 23:03:35.055338 [Gating] SW mode calibration
6836 23:03:35.062382 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6837 23:03:35.065961 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6838 23:03:35.072430 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6839 23:03:35.075691 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6840 23:03:35.079535 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6841 23:03:35.085541 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6842 23:03:35.088782 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6843 23:03:35.092332 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6844 23:03:35.099013 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6845 23:03:35.102111 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6846 23:03:35.105483 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6847 23:03:35.108996 Total UI for P1: 0, mck2ui 16
6848 23:03:35.112445 best dqsien dly found for B0: ( 0, 14, 24)
6849 23:03:35.115355 Total UI for P1: 0, mck2ui 16
6850 23:03:35.118794 best dqsien dly found for B1: ( 0, 14, 24)
6851 23:03:35.122373 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6852 23:03:35.125745 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6853 23:03:35.125837
6854 23:03:35.129180 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6855 23:03:35.135863 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6856 23:03:35.135943 [Gating] SW calibration Done
6857 23:03:35.136014 ==
6858 23:03:35.139290 Dram Type= 6, Freq= 0, CH_1, rank 1
6859 23:03:35.145883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6860 23:03:35.145965 ==
6861 23:03:35.146031 RX Vref Scan: 0
6862 23:03:35.146092
6863 23:03:35.148931 RX Vref 0 -> 0, step: 1
6864 23:03:35.149020
6865 23:03:35.152537 RX Delay -410 -> 252, step: 16
6866 23:03:35.155970 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6867 23:03:35.159374 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6868 23:03:35.166024 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6869 23:03:35.169366 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6870 23:03:35.172713 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6871 23:03:35.176305 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6872 23:03:35.182265 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6873 23:03:35.185576 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6874 23:03:35.189239 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6875 23:03:35.192603 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6876 23:03:35.199416 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6877 23:03:35.202288 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6878 23:03:35.205779 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6879 23:03:35.209171 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6880 23:03:35.215714 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6881 23:03:35.219088 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6882 23:03:35.219166 ==
6883 23:03:35.222754 Dram Type= 6, Freq= 0, CH_1, rank 1
6884 23:03:35.226026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6885 23:03:35.226106 ==
6886 23:03:35.229353 DQS Delay:
6887 23:03:35.229423 DQS0 = 43, DQS1 = 59
6888 23:03:35.229491 DQM Delay:
6889 23:03:35.232698 DQM0 = 10, DQM1 = 19
6890 23:03:35.232768 DQ Delay:
6891 23:03:35.236124 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6892 23:03:35.239543 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6893 23:03:35.242851 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6894 23:03:35.246054 DQ12 =24, DQ13 =32, DQ14 =32, DQ15 =32
6895 23:03:35.246132
6896 23:03:35.246203
6897 23:03:35.246264 ==
6898 23:03:35.249177 Dram Type= 6, Freq= 0, CH_1, rank 1
6899 23:03:35.252615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6900 23:03:35.252701 ==
6901 23:03:35.252769
6902 23:03:35.252831
6903 23:03:35.255977 TX Vref Scan disable
6904 23:03:35.259343 == TX Byte 0 ==
6905 23:03:35.262720 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6906 23:03:35.266406 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6907 23:03:35.269300 == TX Byte 1 ==
6908 23:03:35.272550 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6909 23:03:35.275987 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6910 23:03:35.276069 ==
6911 23:03:35.279794 Dram Type= 6, Freq= 0, CH_1, rank 1
6912 23:03:35.283050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6913 23:03:35.283133 ==
6914 23:03:35.283198
6915 23:03:35.283258
6916 23:03:35.286154 TX Vref Scan disable
6917 23:03:35.289524 == TX Byte 0 ==
6918 23:03:35.292687 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6919 23:03:35.296237 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6920 23:03:35.296319 == TX Byte 1 ==
6921 23:03:35.302720 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6922 23:03:35.305982 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6923 23:03:35.306064
6924 23:03:35.306129 [DATLAT]
6925 23:03:35.309426 Freq=400, CH1 RK1
6926 23:03:35.309508
6927 23:03:35.309573 DATLAT Default: 0xe
6928 23:03:35.312754 0, 0xFFFF, sum = 0
6929 23:03:35.312838 1, 0xFFFF, sum = 0
6930 23:03:35.316364 2, 0xFFFF, sum = 0
6931 23:03:35.316447 3, 0xFFFF, sum = 0
6932 23:03:35.319323 4, 0xFFFF, sum = 0
6933 23:03:35.319428 5, 0xFFFF, sum = 0
6934 23:03:35.322967 6, 0xFFFF, sum = 0
6935 23:03:35.323050 7, 0xFFFF, sum = 0
6936 23:03:35.326483 8, 0xFFFF, sum = 0
6937 23:03:35.329583 9, 0xFFFF, sum = 0
6938 23:03:35.329667 10, 0xFFFF, sum = 0
6939 23:03:35.332952 11, 0xFFFF, sum = 0
6940 23:03:35.333034 12, 0xFFFF, sum = 0
6941 23:03:35.335918 13, 0x0, sum = 1
6942 23:03:35.336001 14, 0x0, sum = 2
6943 23:03:35.339656 15, 0x0, sum = 3
6944 23:03:35.339749 16, 0x0, sum = 4
6945 23:03:35.339816 best_step = 14
6946 23:03:35.339877
6947 23:03:35.342847 ==
6948 23:03:35.342929 Dram Type= 6, Freq= 0, CH_1, rank 1
6949 23:03:35.349502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6950 23:03:35.349585 ==
6951 23:03:35.349651 RX Vref Scan: 0
6952 23:03:35.349712
6953 23:03:35.353052 RX Vref 0 -> 0, step: 1
6954 23:03:35.353147
6955 23:03:35.356040 RX Delay -359 -> 252, step: 8
6956 23:03:35.363116 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6957 23:03:35.366371 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6958 23:03:35.370146 iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488
6959 23:03:35.373230 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6960 23:03:35.379416 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6961 23:03:35.383331 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6962 23:03:35.386386 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6963 23:03:35.389697 iDelay=217, Bit 7, Center -40 (-279 ~ 200) 480
6964 23:03:35.396313 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6965 23:03:35.399380 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6966 23:03:35.403143 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6967 23:03:35.409168 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6968 23:03:35.412984 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6969 23:03:35.415852 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6970 23:03:35.419528 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6971 23:03:35.425665 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6972 23:03:35.425749 ==
6973 23:03:35.428969 Dram Type= 6, Freq= 0, CH_1, rank 1
6974 23:03:35.432580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6975 23:03:35.432654 ==
6976 23:03:35.432717 DQS Delay:
6977 23:03:35.436143 DQS0 = 52, DQS1 = 56
6978 23:03:35.436223 DQM Delay:
6979 23:03:35.438887 DQM0 = 14, DQM1 = 9
6980 23:03:35.438982 DQ Delay:
6981 23:03:35.442495 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =16
6982 23:03:35.445743 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =12
6983 23:03:35.449218 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6984 23:03:35.452537 DQ12 =12, DQ13 =16, DQ14 =16, DQ15 =16
6985 23:03:35.452616
6986 23:03:35.452680
6987 23:03:35.458852 [DQSOSCAuto] RK1, (LSB)MR18= 0x788e, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 394 ps
6988 23:03:35.462310 CH1 RK1: MR19=C0C, MR18=788E
6989 23:03:35.468992 CH1_RK1: MR19=0xC0C, MR18=0x788E, DQSOSC=392, MR23=63, INC=384, DEC=256
6990 23:03:35.472407 [RxdqsGatingPostProcess] freq 400
6991 23:03:35.479072 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6992 23:03:35.479209 best DQS0 dly(2T, 0.5T) = (0, 10)
6993 23:03:35.482970 best DQS1 dly(2T, 0.5T) = (0, 10)
6994 23:03:35.485810 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6995 23:03:35.489794 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6996 23:03:35.492271 best DQS0 dly(2T, 0.5T) = (0, 10)
6997 23:03:35.495791 best DQS1 dly(2T, 0.5T) = (0, 10)
6998 23:03:35.499240 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6999 23:03:35.502294 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7000 23:03:35.506039 Pre-setting of DQS Precalculation
7001 23:03:35.512539 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7002 23:03:35.519302 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7003 23:03:35.525779 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7004 23:03:35.525860
7005 23:03:35.525924
7006 23:03:35.529170 [Calibration Summary] 800 Mbps
7007 23:03:35.529251 CH 0, Rank 0
7008 23:03:35.532606 SW Impedance : PASS
7009 23:03:35.532687 DUTY Scan : NO K
7010 23:03:35.536202 ZQ Calibration : PASS
7011 23:03:35.538864 Jitter Meter : NO K
7012 23:03:35.538961 CBT Training : PASS
7013 23:03:35.542532 Write leveling : PASS
7014 23:03:35.545727 RX DQS gating : PASS
7015 23:03:35.545807 RX DQ/DQS(RDDQC) : PASS
7016 23:03:35.549488 TX DQ/DQS : PASS
7017 23:03:35.552690 RX DATLAT : PASS
7018 23:03:35.552769 RX DQ/DQS(Engine): PASS
7019 23:03:35.556301 TX OE : NO K
7020 23:03:35.556381 All Pass.
7021 23:03:35.556444
7022 23:03:35.559578 CH 0, Rank 1
7023 23:03:35.559684 SW Impedance : PASS
7024 23:03:35.562849 DUTY Scan : NO K
7025 23:03:35.562968 ZQ Calibration : PASS
7026 23:03:35.565929 Jitter Meter : NO K
7027 23:03:35.569353 CBT Training : PASS
7028 23:03:35.569435 Write leveling : NO K
7029 23:03:35.572703 RX DQS gating : PASS
7030 23:03:35.575735 RX DQ/DQS(RDDQC) : PASS
7031 23:03:35.575820 TX DQ/DQS : PASS
7032 23:03:35.579633 RX DATLAT : PASS
7033 23:03:35.582725 RX DQ/DQS(Engine): PASS
7034 23:03:35.582840 TX OE : NO K
7035 23:03:35.586181 All Pass.
7036 23:03:35.586268
7037 23:03:35.586350 CH 1, Rank 0
7038 23:03:35.589250 SW Impedance : PASS
7039 23:03:35.589328 DUTY Scan : NO K
7040 23:03:35.592492 ZQ Calibration : PASS
7041 23:03:35.596162 Jitter Meter : NO K
7042 23:03:35.596245 CBT Training : PASS
7043 23:03:35.599535 Write leveling : PASS
7044 23:03:35.602648 RX DQS gating : PASS
7045 23:03:35.602729 RX DQ/DQS(RDDQC) : PASS
7046 23:03:35.606162 TX DQ/DQS : PASS
7047 23:03:35.606241 RX DATLAT : PASS
7048 23:03:35.609635 RX DQ/DQS(Engine): PASS
7049 23:03:35.612667 TX OE : NO K
7050 23:03:35.612760 All Pass.
7051 23:03:35.612825
7052 23:03:35.612884 CH 1, Rank 1
7053 23:03:35.615832 SW Impedance : PASS
7054 23:03:35.619408 DUTY Scan : NO K
7055 23:03:35.619486 ZQ Calibration : PASS
7056 23:03:35.622643 Jitter Meter : NO K
7057 23:03:35.625846 CBT Training : PASS
7058 23:03:35.625933 Write leveling : NO K
7059 23:03:35.629519 RX DQS gating : PASS
7060 23:03:35.633085 RX DQ/DQS(RDDQC) : PASS
7061 23:03:35.633171 TX DQ/DQS : PASS
7062 23:03:35.635816 RX DATLAT : PASS
7063 23:03:35.639187 RX DQ/DQS(Engine): PASS
7064 23:03:35.639267 TX OE : NO K
7065 23:03:35.639332 All Pass.
7066 23:03:35.642705
7067 23:03:35.642775 DramC Write-DBI off
7068 23:03:35.646604 PER_BANK_REFRESH: Hybrid Mode
7069 23:03:35.646741 TX_TRACKING: ON
7070 23:03:35.656285 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7071 23:03:35.659694 [FAST_K] Save calibration result to emmc
7072 23:03:35.663019 dramc_set_vcore_voltage set vcore to 725000
7073 23:03:35.666109 Read voltage for 1600, 0
7074 23:03:35.666194 Vio18 = 0
7075 23:03:35.669480 Vcore = 725000
7076 23:03:35.669564 Vdram = 0
7077 23:03:35.669655 Vddq = 0
7078 23:03:35.669721 Vmddr = 0
7079 23:03:35.676244 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7080 23:03:35.682869 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7081 23:03:35.682953 MEM_TYPE=3, freq_sel=13
7082 23:03:35.686280 sv_algorithm_assistance_LP4_3733
7083 23:03:35.689185 ============ PULL DRAM RESETB DOWN ============
7084 23:03:35.696285 ========== PULL DRAM RESETB DOWN end =========
7085 23:03:35.699460 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7086 23:03:35.702478 ===================================
7087 23:03:35.706171 LPDDR4 DRAM CONFIGURATION
7088 23:03:35.709574 ===================================
7089 23:03:35.709657 EX_ROW_EN[0] = 0x0
7090 23:03:35.712701 EX_ROW_EN[1] = 0x0
7091 23:03:35.712788 LP4Y_EN = 0x0
7092 23:03:35.716678 WORK_FSP = 0x1
7093 23:03:35.716760 WL = 0x5
7094 23:03:35.720038 RL = 0x5
7095 23:03:35.720120 BL = 0x2
7096 23:03:35.723081 RPST = 0x0
7097 23:03:35.723164 RD_PRE = 0x0
7098 23:03:35.726410 WR_PRE = 0x1
7099 23:03:35.726492 WR_PST = 0x1
7100 23:03:35.729621 DBI_WR = 0x0
7101 23:03:35.729704 DBI_RD = 0x0
7102 23:03:35.733021 OTF = 0x1
7103 23:03:35.736154 ===================================
7104 23:03:35.739591 ===================================
7105 23:03:35.739674 ANA top config
7106 23:03:35.743087 ===================================
7107 23:03:35.746473 DLL_ASYNC_EN = 0
7108 23:03:35.749597 ALL_SLAVE_EN = 0
7109 23:03:35.753077 NEW_RANK_MODE = 1
7110 23:03:35.753158 DLL_IDLE_MODE = 1
7111 23:03:35.756107 LP45_APHY_COMB_EN = 1
7112 23:03:35.759708 TX_ODT_DIS = 0
7113 23:03:35.763275 NEW_8X_MODE = 1
7114 23:03:35.766053 ===================================
7115 23:03:35.769471 ===================================
7116 23:03:35.772708 data_rate = 3200
7117 23:03:35.772786 CKR = 1
7118 23:03:35.776695 DQ_P2S_RATIO = 8
7119 23:03:35.779285 ===================================
7120 23:03:35.782708 CA_P2S_RATIO = 8
7121 23:03:35.786244 DQ_CA_OPEN = 0
7122 23:03:35.789322 DQ_SEMI_OPEN = 0
7123 23:03:35.793237 CA_SEMI_OPEN = 0
7124 23:03:35.793326 CA_FULL_RATE = 0
7125 23:03:35.796568 DQ_CKDIV4_EN = 0
7126 23:03:35.799814 CA_CKDIV4_EN = 0
7127 23:03:35.802958 CA_PREDIV_EN = 0
7128 23:03:35.806379 PH8_DLY = 12
7129 23:03:35.809913 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7130 23:03:35.809984 DQ_AAMCK_DIV = 4
7131 23:03:35.812703 CA_AAMCK_DIV = 4
7132 23:03:35.816273 CA_ADMCK_DIV = 4
7133 23:03:35.819432 DQ_TRACK_CA_EN = 0
7134 23:03:35.823086 CA_PICK = 1600
7135 23:03:35.826168 CA_MCKIO = 1600
7136 23:03:35.829512 MCKIO_SEMI = 0
7137 23:03:35.829584 PLL_FREQ = 3068
7138 23:03:35.833138 DQ_UI_PI_RATIO = 32
7139 23:03:35.836572 CA_UI_PI_RATIO = 0
7140 23:03:35.839394 ===================================
7141 23:03:35.842804 ===================================
7142 23:03:35.846440 memory_type:LPDDR4
7143 23:03:35.846516 GP_NUM : 10
7144 23:03:35.849806 SRAM_EN : 1
7145 23:03:35.853484 MD32_EN : 0
7146 23:03:35.856619 ===================================
7147 23:03:35.856698 [ANA_INIT] >>>>>>>>>>>>>>
7148 23:03:35.860348 <<<<<< [CONFIGURE PHASE]: ANA_TX
7149 23:03:35.862888 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7150 23:03:35.866359 ===================================
7151 23:03:35.869600 data_rate = 3200,PCW = 0X7600
7152 23:03:35.873254 ===================================
7153 23:03:35.876566 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7154 23:03:35.882978 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7155 23:03:35.886710 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7156 23:03:35.893508 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7157 23:03:35.896436 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7158 23:03:35.899789 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7159 23:03:35.899864 [ANA_INIT] flow start
7160 23:03:35.903095 [ANA_INIT] PLL >>>>>>>>
7161 23:03:35.906743 [ANA_INIT] PLL <<<<<<<<
7162 23:03:35.906814 [ANA_INIT] MIDPI >>>>>>>>
7163 23:03:35.910042 [ANA_INIT] MIDPI <<<<<<<<
7164 23:03:35.913427 [ANA_INIT] DLL >>>>>>>>
7165 23:03:35.913536 [ANA_INIT] DLL <<<<<<<<
7166 23:03:35.916872 [ANA_INIT] flow end
7167 23:03:35.920098 ============ LP4 DIFF to SE enter ============
7168 23:03:35.926781 ============ LP4 DIFF to SE exit ============
7169 23:03:35.926873 [ANA_INIT] <<<<<<<<<<<<<
7170 23:03:35.929826 [Flow] Enable top DCM control >>>>>
7171 23:03:35.933548 [Flow] Enable top DCM control <<<<<
7172 23:03:35.936463 Enable DLL master slave shuffle
7173 23:03:35.943439 ==============================================================
7174 23:03:35.943518 Gating Mode config
7175 23:03:35.949719 ==============================================================
7176 23:03:35.949795 Config description:
7177 23:03:35.959762 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7178 23:03:35.966732 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7179 23:03:35.973306 SELPH_MODE 0: By rank 1: By Phase
7180 23:03:35.976639 ==============================================================
7181 23:03:35.979789 GAT_TRACK_EN = 1
7182 23:03:35.983145 RX_GATING_MODE = 2
7183 23:03:35.986331 RX_GATING_TRACK_MODE = 2
7184 23:03:35.989878 SELPH_MODE = 1
7185 23:03:35.993471 PICG_EARLY_EN = 1
7186 23:03:35.996306 VALID_LAT_VALUE = 1
7187 23:03:36.003468 ==============================================================
7188 23:03:36.006603 Enter into Gating configuration >>>>
7189 23:03:36.010382 Exit from Gating configuration <<<<
7190 23:03:36.013418 Enter into DVFS_PRE_config >>>>>
7191 23:03:36.023032 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7192 23:03:36.026347 Exit from DVFS_PRE_config <<<<<
7193 23:03:36.030046 Enter into PICG configuration >>>>
7194 23:03:36.033343 Exit from PICG configuration <<<<
7195 23:03:36.033443 [RX_INPUT] configuration >>>>>
7196 23:03:36.036524 [RX_INPUT] configuration <<<<<
7197 23:03:36.043202 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7198 23:03:36.046564 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7199 23:03:36.053002 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7200 23:03:36.059998 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7201 23:03:36.066440 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7202 23:03:36.073563 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7203 23:03:36.076455 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7204 23:03:36.079786 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7205 23:03:36.083089 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7206 23:03:36.090011 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7207 23:03:36.093261 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7208 23:03:36.096883 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7209 23:03:36.100100 ===================================
7210 23:03:36.103469 LPDDR4 DRAM CONFIGURATION
7211 23:03:36.106840 ===================================
7212 23:03:36.109758 EX_ROW_EN[0] = 0x0
7213 23:03:36.109864 EX_ROW_EN[1] = 0x0
7214 23:03:36.113083 LP4Y_EN = 0x0
7215 23:03:36.113170 WORK_FSP = 0x1
7216 23:03:36.116521 WL = 0x5
7217 23:03:36.116610 RL = 0x5
7218 23:03:36.120035 BL = 0x2
7219 23:03:36.120145 RPST = 0x0
7220 23:03:36.123245 RD_PRE = 0x0
7221 23:03:36.123329 WR_PRE = 0x1
7222 23:03:36.126634 WR_PST = 0x1
7223 23:03:36.126704 DBI_WR = 0x0
7224 23:03:36.129990 DBI_RD = 0x0
7225 23:03:36.130090 OTF = 0x1
7226 23:03:36.133391 ===================================
7227 23:03:36.136737 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7228 23:03:36.143153 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7229 23:03:36.147019 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7230 23:03:36.150030 ===================================
7231 23:03:36.153542 LPDDR4 DRAM CONFIGURATION
7232 23:03:36.157041 ===================================
7233 23:03:36.157119 EX_ROW_EN[0] = 0x10
7234 23:03:36.160400 EX_ROW_EN[1] = 0x0
7235 23:03:36.163176 LP4Y_EN = 0x0
7236 23:03:36.163280 WORK_FSP = 0x1
7237 23:03:36.166604 WL = 0x5
7238 23:03:36.166710 RL = 0x5
7239 23:03:36.170199 BL = 0x2
7240 23:03:36.170278 RPST = 0x0
7241 23:03:36.173786 RD_PRE = 0x0
7242 23:03:36.173882 WR_PRE = 0x1
7243 23:03:36.176661 WR_PST = 0x1
7244 23:03:36.176756 DBI_WR = 0x0
7245 23:03:36.180352 DBI_RD = 0x0
7246 23:03:36.180454 OTF = 0x1
7247 23:03:36.183541 ===================================
7248 23:03:36.190002 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7249 23:03:36.190075 ==
7250 23:03:36.193496 Dram Type= 6, Freq= 0, CH_0, rank 0
7251 23:03:36.197054 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7252 23:03:36.197155 ==
7253 23:03:36.199860 [Duty_Offset_Calibration]
7254 23:03:36.203724 B0:2 B1:-1 CA:1
7255 23:03:36.203825
7256 23:03:36.206504 [DutyScan_Calibration_Flow] k_type=0
7257 23:03:36.214661
7258 23:03:36.214737 ==CLK 0==
7259 23:03:36.217932 Final CLK duty delay cell = -4
7260 23:03:36.221198 [-4] MAX Duty = 5031%(X100), DQS PI = 22
7261 23:03:36.224410 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7262 23:03:36.227613 [-4] AVG Duty = 4937%(X100)
7263 23:03:36.227687
7264 23:03:36.230994 CH0 CLK Duty spec in!! Max-Min= 187%
7265 23:03:36.234576 [DutyScan_Calibration_Flow] ====Done====
7266 23:03:36.234677
7267 23:03:36.237870 [DutyScan_Calibration_Flow] k_type=1
7268 23:03:36.253849
7269 23:03:36.253924 ==DQS 0 ==
7270 23:03:36.257412 Final DQS duty delay cell = 0
7271 23:03:36.260556 [0] MAX Duty = 5125%(X100), DQS PI = 56
7272 23:03:36.264280 [0] MIN Duty = 5000%(X100), DQS PI = 16
7273 23:03:36.267463 [0] AVG Duty = 5062%(X100)
7274 23:03:36.267572
7275 23:03:36.267669 ==DQS 1 ==
7276 23:03:36.270775 Final DQS duty delay cell = -4
7277 23:03:36.273781 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7278 23:03:36.277042 [-4] MIN Duty = 5000%(X100), DQS PI = 40
7279 23:03:36.280504 [-4] AVG Duty = 5046%(X100)
7280 23:03:36.280606
7281 23:03:36.284259 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7282 23:03:36.284356
7283 23:03:36.286926 CH0 DQS 1 Duty spec in!! Max-Min= 93%
7284 23:03:36.290391 [DutyScan_Calibration_Flow] ====Done====
7285 23:03:36.290508
7286 23:03:36.293772 [DutyScan_Calibration_Flow] k_type=3
7287 23:03:36.311076
7288 23:03:36.311153 ==DQM 0 ==
7289 23:03:36.314497 Final DQM duty delay cell = 0
7290 23:03:36.317767 [0] MAX Duty = 5000%(X100), DQS PI = 20
7291 23:03:36.321454 [0] MIN Duty = 4875%(X100), DQS PI = 6
7292 23:03:36.321554 [0] AVG Duty = 4937%(X100)
7293 23:03:36.324457
7294 23:03:36.324553 ==DQM 1 ==
7295 23:03:36.327950 Final DQM duty delay cell = 0
7296 23:03:36.331406 [0] MAX Duty = 5218%(X100), DQS PI = 58
7297 23:03:36.334748 [0] MIN Duty = 4969%(X100), DQS PI = 20
7298 23:03:36.334875 [0] AVG Duty = 5093%(X100)
7299 23:03:36.337833
7300 23:03:36.341065 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7301 23:03:36.341178
7302 23:03:36.344383 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7303 23:03:36.348105 [DutyScan_Calibration_Flow] ====Done====
7304 23:03:36.348175
7305 23:03:36.351011 [DutyScan_Calibration_Flow] k_type=2
7306 23:03:36.367676
7307 23:03:36.367758 ==DQ 0 ==
7308 23:03:36.370708 Final DQ duty delay cell = -4
7309 23:03:36.374151 [-4] MAX Duty = 5000%(X100), DQS PI = 0
7310 23:03:36.377734 [-4] MIN Duty = 4844%(X100), DQS PI = 14
7311 23:03:36.380587 [-4] AVG Duty = 4922%(X100)
7312 23:03:36.380659
7313 23:03:36.380725 ==DQ 1 ==
7314 23:03:36.384064 Final DQ duty delay cell = 0
7315 23:03:36.387604 [0] MAX Duty = 5031%(X100), DQS PI = 30
7316 23:03:36.391047 [0] MIN Duty = 4907%(X100), DQS PI = 18
7317 23:03:36.394446 [0] AVG Duty = 4969%(X100)
7318 23:03:36.394518
7319 23:03:36.397519 CH0 DQ 0 Duty spec in!! Max-Min= 156%
7320 23:03:36.397589
7321 23:03:36.400966 CH0 DQ 1 Duty spec in!! Max-Min= 124%
7322 23:03:36.404449 [DutyScan_Calibration_Flow] ====Done====
7323 23:03:36.404518 ==
7324 23:03:36.407295 Dram Type= 6, Freq= 0, CH_1, rank 0
7325 23:03:36.410615 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7326 23:03:36.410684 ==
7327 23:03:36.414295 [Duty_Offset_Calibration]
7328 23:03:36.414378 B0:1 B1:1 CA:2
7329 23:03:36.414441
7330 23:03:36.417491 [DutyScan_Calibration_Flow] k_type=0
7331 23:03:36.428096
7332 23:03:36.428174 ==CLK 0==
7333 23:03:36.431131 Final CLK duty delay cell = 0
7334 23:03:36.434484 [0] MAX Duty = 5187%(X100), DQS PI = 24
7335 23:03:36.437797 [0] MIN Duty = 4969%(X100), DQS PI = 42
7336 23:03:36.437873 [0] AVG Duty = 5078%(X100)
7337 23:03:36.441035
7338 23:03:36.445179 CH1 CLK Duty spec in!! Max-Min= 218%
7339 23:03:36.447976 [DutyScan_Calibration_Flow] ====Done====
7340 23:03:36.448081
7341 23:03:36.451050 [DutyScan_Calibration_Flow] k_type=1
7342 23:03:36.467402
7343 23:03:36.467507 ==DQS 0 ==
7344 23:03:36.470996 Final DQS duty delay cell = 0
7345 23:03:36.474107 [0] MAX Duty = 5062%(X100), DQS PI = 20
7346 23:03:36.478108 [0] MIN Duty = 4813%(X100), DQS PI = 52
7347 23:03:36.478203 [0] AVG Duty = 4937%(X100)
7348 23:03:36.481128
7349 23:03:36.481207 ==DQS 1 ==
7350 23:03:36.484312 Final DQS duty delay cell = 0
7351 23:03:36.487757 [0] MAX Duty = 5062%(X100), DQS PI = 56
7352 23:03:36.491012 [0] MIN Duty = 4938%(X100), DQS PI = 14
7353 23:03:36.491084 [0] AVG Duty = 5000%(X100)
7354 23:03:36.494209
7355 23:03:36.497664 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7356 23:03:36.497732
7357 23:03:36.500858 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7358 23:03:36.504135 [DutyScan_Calibration_Flow] ====Done====
7359 23:03:36.504203
7360 23:03:36.507851 [DutyScan_Calibration_Flow] k_type=3
7361 23:03:36.524569
7362 23:03:36.524645 ==DQM 0 ==
7363 23:03:36.527922 Final DQM duty delay cell = 0
7364 23:03:36.531227 [0] MAX Duty = 5124%(X100), DQS PI = 20
7365 23:03:36.534405 [0] MIN Duty = 4844%(X100), DQS PI = 50
7366 23:03:36.534473 [0] AVG Duty = 4984%(X100)
7367 23:03:36.538164
7368 23:03:36.538234 ==DQM 1 ==
7369 23:03:36.541341 Final DQM duty delay cell = 0
7370 23:03:36.544660 [0] MAX Duty = 5156%(X100), DQS PI = 60
7371 23:03:36.547827 [0] MIN Duty = 4907%(X100), DQS PI = 18
7372 23:03:36.551237 [0] AVG Duty = 5031%(X100)
7373 23:03:36.551310
7374 23:03:36.554175 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7375 23:03:36.554240
7376 23:03:36.558250 CH1 DQM 1 Duty spec in!! Max-Min= 249%
7377 23:03:36.561205 [DutyScan_Calibration_Flow] ====Done====
7378 23:03:36.561278
7379 23:03:36.564518 [DutyScan_Calibration_Flow] k_type=2
7380 23:03:36.581709
7381 23:03:36.581816 ==DQ 0 ==
7382 23:03:36.584714 Final DQ duty delay cell = 0
7383 23:03:36.587927 [0] MAX Duty = 5156%(X100), DQS PI = 20
7384 23:03:36.591381 [0] MIN Duty = 4907%(X100), DQS PI = 52
7385 23:03:36.591493 [0] AVG Duty = 5031%(X100)
7386 23:03:36.594602
7387 23:03:36.594674 ==DQ 1 ==
7388 23:03:36.597892 Final DQ duty delay cell = 0
7389 23:03:36.601264 [0] MAX Duty = 5093%(X100), DQS PI = 8
7390 23:03:36.605072 [0] MIN Duty = 5031%(X100), DQS PI = 0
7391 23:03:36.605152 [0] AVG Duty = 5062%(X100)
7392 23:03:36.605254
7393 23:03:36.608500 CH1 DQ 0 Duty spec in!! Max-Min= 249%
7394 23:03:36.608579
7395 23:03:36.611136 CH1 DQ 1 Duty spec in!! Max-Min= 62%
7396 23:03:36.618259 [DutyScan_Calibration_Flow] ====Done====
7397 23:03:36.621702 nWR fixed to 30
7398 23:03:36.621795 [ModeRegInit_LP4] CH0 RK0
7399 23:03:36.624520 [ModeRegInit_LP4] CH0 RK1
7400 23:03:36.627917 [ModeRegInit_LP4] CH1 RK0
7401 23:03:36.627988 [ModeRegInit_LP4] CH1 RK1
7402 23:03:36.631526 match AC timing 5
7403 23:03:36.635025 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7404 23:03:36.637828 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7405 23:03:36.644707 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7406 23:03:36.648189 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7407 23:03:36.654734 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7408 23:03:36.654840 [MiockJmeterHQA]
7409 23:03:36.654925
7410 23:03:36.658209 [DramcMiockJmeter] u1RxGatingPI = 0
7411 23:03:36.658279 0 : 4252, 4027
7412 23:03:36.661431 4 : 4252, 4027
7413 23:03:36.661503 8 : 4252, 4027
7414 23:03:36.665183 12 : 4252, 4027
7415 23:03:36.665257 16 : 4252, 4026
7416 23:03:36.668648 20 : 4258, 4030
7417 23:03:36.668760 24 : 4257, 4029
7418 23:03:36.668854 28 : 4365, 4140
7419 23:03:36.671655 32 : 4255, 4030
7420 23:03:36.671758 36 : 4365, 4140
7421 23:03:36.675084 40 : 4253, 4027
7422 23:03:36.675160 44 : 4255, 4029
7423 23:03:36.678605 48 : 4255, 4029
7424 23:03:36.678707 52 : 4253, 4026
7425 23:03:36.681238 56 : 4258, 4032
7426 23:03:36.681317 60 : 4360, 4138
7427 23:03:36.681387 64 : 4250, 4027
7428 23:03:36.684750 68 : 4250, 4027
7429 23:03:36.684824 72 : 4253, 4029
7430 23:03:36.688473 76 : 4257, 4032
7431 23:03:36.688544 80 : 4363, 4140
7432 23:03:36.691466 84 : 4255, 4029
7433 23:03:36.691535 88 : 4250, 4027
7434 23:03:36.691596 92 : 4253, 4029
7435 23:03:36.695132 96 : 4255, 3210
7436 23:03:36.695205 100 : 4255, 0
7437 23:03:36.698234 104 : 4252, 0
7438 23:03:36.698321 108 : 4250, 0
7439 23:03:36.698388 112 : 4250, 0
7440 23:03:36.701442 116 : 4258, 0
7441 23:03:36.701516 120 : 4249, 0
7442 23:03:36.704616 124 : 4363, 0
7443 23:03:36.704690 128 : 4363, 0
7444 23:03:36.704756 132 : 4250, 0
7445 23:03:36.708283 136 : 4250, 0
7446 23:03:36.708352 140 : 4365, 0
7447 23:03:36.711893 144 : 4250, 0
7448 23:03:36.711963 148 : 4365, 0
7449 23:03:36.712023 152 : 4252, 0
7450 23:03:36.715069 156 : 4252, 0
7451 23:03:36.715140 160 : 4363, 0
7452 23:03:36.715200 164 : 4253, 0
7453 23:03:36.718265 168 : 4252, 0
7454 23:03:36.718354 172 : 4361, 0
7455 23:03:36.721807 176 : 4250, 0
7456 23:03:36.721888 180 : 4361, 0
7457 23:03:36.721974 184 : 4250, 0
7458 23:03:36.725304 188 : 4250, 0
7459 23:03:36.725382 192 : 4250, 0
7460 23:03:36.728729 196 : 4257, 0
7461 23:03:36.728810 200 : 4363, 0
7462 23:03:36.728875 204 : 4249, 0
7463 23:03:36.731569 208 : 4360, 0
7464 23:03:36.731644 212 : 4258, 164
7465 23:03:36.735087 216 : 4363, 3985
7466 23:03:36.735166 220 : 4250, 4026
7467 23:03:36.738735 224 : 4253, 4029
7468 23:03:36.738816 228 : 4361, 4137
7469 23:03:36.738889 232 : 4252, 4029
7470 23:03:36.741672 236 : 4363, 4137
7471 23:03:36.741746 240 : 4253, 4029
7472 23:03:36.744945 244 : 4361, 4137
7473 23:03:36.745020 248 : 4252, 4029
7474 23:03:36.748358 252 : 4360, 4138
7475 23:03:36.748443 256 : 4360, 4138
7476 23:03:36.752031 260 : 4250, 4027
7477 23:03:36.752123 264 : 4253, 4030
7478 23:03:36.755074 268 : 4252, 4029
7479 23:03:36.755151 272 : 4361, 4138
7480 23:03:36.758345 276 : 4250, 4027
7481 23:03:36.758422 280 : 4252, 4029
7482 23:03:36.761768 284 : 4254, 4029
7483 23:03:36.761850 288 : 4250, 4026
7484 23:03:36.761935 292 : 4363, 4137
7485 23:03:36.765062 296 : 4363, 4140
7486 23:03:36.765139 300 : 4250, 4026
7487 23:03:36.768576 304 : 4361, 4137
7488 23:03:36.768658 308 : 4250, 4026
7489 23:03:36.772219 312 : 4250, 4026
7490 23:03:36.772305 316 : 4255, 4030
7491 23:03:36.775275 320 : 4365, 4139
7492 23:03:36.775361 324 : 4252, 4029
7493 23:03:36.778561 328 : 4250, 4026
7494 23:03:36.778648 332 : 4252, 3007
7495 23:03:36.782016 336 : 4250, 51
7496 23:03:36.782109
7497 23:03:36.782194 MIOCK jitter meter ch=0
7498 23:03:36.782277
7499 23:03:36.785289 1T = (336-100) = 236 dly cells
7500 23:03:36.791897 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7501 23:03:36.791984 ==
7502 23:03:36.794845 Dram Type= 6, Freq= 0, CH_0, rank 0
7503 23:03:36.798603 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7504 23:03:36.798690 ==
7505 23:03:36.805613 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7506 23:03:36.808520 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7507 23:03:36.811877 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7508 23:03:36.818558 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7509 23:03:36.827700 [CA 0] Center 44 (14~75) winsize 62
7510 23:03:36.830946 [CA 1] Center 44 (14~75) winsize 62
7511 23:03:36.834394 [CA 2] Center 40 (11~69) winsize 59
7512 23:03:36.837813 [CA 3] Center 39 (10~69) winsize 60
7513 23:03:36.840992 [CA 4] Center 38 (8~68) winsize 61
7514 23:03:36.844550 [CA 5] Center 37 (7~67) winsize 61
7515 23:03:36.844635
7516 23:03:36.847874 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7517 23:03:36.847960
7518 23:03:36.851354 [CATrainingPosCal] consider 1 rank data
7519 23:03:36.854560 u2DelayCellTimex100 = 275/100 ps
7520 23:03:36.857711 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7521 23:03:36.864228 CA1 delay=44 (14~75),Diff = 7 PI (24 cell)
7522 23:03:36.867709 CA2 delay=40 (11~69),Diff = 3 PI (10 cell)
7523 23:03:36.871147 CA3 delay=39 (10~69),Diff = 2 PI (7 cell)
7524 23:03:36.874544 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
7525 23:03:36.877981 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7526 23:03:36.878076
7527 23:03:36.881236 CA PerBit enable=1, Macro0, CA PI delay=37
7528 23:03:36.881330
7529 23:03:36.884506 [CBTSetCACLKResult] CA Dly = 37
7530 23:03:36.888008 CS Dly: 10 (0~41)
7531 23:03:36.891692 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7532 23:03:36.894832 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7533 23:03:36.894934 ==
7534 23:03:36.897752 Dram Type= 6, Freq= 0, CH_0, rank 1
7535 23:03:36.900986 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7536 23:03:36.904491 ==
7537 23:03:36.908151 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7538 23:03:36.911569 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7539 23:03:36.918387 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7540 23:03:36.921574 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7541 23:03:36.931867 [CA 0] Center 44 (14~75) winsize 62
7542 23:03:36.934678 [CA 1] Center 44 (14~75) winsize 62
7543 23:03:36.938185 [CA 2] Center 40 (10~70) winsize 61
7544 23:03:36.941705 [CA 3] Center 39 (10~69) winsize 60
7545 23:03:36.944922 [CA 4] Center 38 (9~67) winsize 59
7546 23:03:36.948388 [CA 5] Center 37 (7~67) winsize 61
7547 23:03:36.948474
7548 23:03:36.951583 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7549 23:03:36.951669
7550 23:03:36.955511 [CATrainingPosCal] consider 2 rank data
7551 23:03:36.958144 u2DelayCellTimex100 = 275/100 ps
7552 23:03:36.961551 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7553 23:03:36.968359 CA1 delay=44 (14~75),Diff = 7 PI (24 cell)
7554 23:03:36.971999 CA2 delay=40 (11~69),Diff = 3 PI (10 cell)
7555 23:03:36.974996 CA3 delay=39 (10~69),Diff = 2 PI (7 cell)
7556 23:03:36.978715 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
7557 23:03:36.981910 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7558 23:03:36.981999
7559 23:03:36.985312 CA PerBit enable=1, Macro0, CA PI delay=37
7560 23:03:36.985393
7561 23:03:36.988337 [CBTSetCACLKResult] CA Dly = 37
7562 23:03:36.992219 CS Dly: 11 (0~44)
7563 23:03:36.995311 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7564 23:03:36.998187 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7565 23:03:36.998266
7566 23:03:37.001687 ----->DramcWriteLeveling(PI) begin...
7567 23:03:37.001801 ==
7568 23:03:37.004864 Dram Type= 6, Freq= 0, CH_0, rank 0
7569 23:03:37.008444 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7570 23:03:37.011895 ==
7571 23:03:37.011975 Write leveling (Byte 0): 32 => 32
7572 23:03:37.015490 Write leveling (Byte 1): 28 => 28
7573 23:03:37.018315 DramcWriteLeveling(PI) end<-----
7574 23:03:37.018391
7575 23:03:37.018473 ==
7576 23:03:37.021763 Dram Type= 6, Freq= 0, CH_0, rank 0
7577 23:03:37.028643 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7578 23:03:37.028725 ==
7579 23:03:37.028810 [Gating] SW mode calibration
7580 23:03:37.038966 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7581 23:03:37.042115 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7582 23:03:37.048297 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7583 23:03:37.051776 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7584 23:03:37.055146 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7585 23:03:37.058553 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7586 23:03:37.065501 1 4 16 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7587 23:03:37.068261 1 4 20 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
7588 23:03:37.072256 1 4 24 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
7589 23:03:37.078450 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7590 23:03:37.081750 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7591 23:03:37.084871 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7592 23:03:37.091470 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7593 23:03:37.094824 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7594 23:03:37.098635 1 5 16 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
7595 23:03:37.104830 1 5 20 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7596 23:03:37.108328 1 5 24 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
7597 23:03:37.111661 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7598 23:03:37.118574 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7599 23:03:37.121855 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7600 23:03:37.125450 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7601 23:03:37.132047 1 6 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7602 23:03:37.135211 1 6 16 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
7603 23:03:37.138611 1 6 20 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
7604 23:03:37.141981 1 6 24 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
7605 23:03:37.148434 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7606 23:03:37.151693 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7607 23:03:37.158339 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7608 23:03:37.161811 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7609 23:03:37.164652 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7610 23:03:37.168462 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7611 23:03:37.175462 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7612 23:03:37.178539 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7613 23:03:37.181595 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7614 23:03:37.188505 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7615 23:03:37.191786 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7616 23:03:37.194753 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7617 23:03:37.201830 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7618 23:03:37.205000 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7619 23:03:37.208608 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7620 23:03:37.214966 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7621 23:03:37.218308 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7622 23:03:37.221844 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 23:03:37.228376 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 23:03:37.231807 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7625 23:03:37.234762 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7626 23:03:37.241726 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7627 23:03:37.244694 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7628 23:03:37.248550 Total UI for P1: 0, mck2ui 16
7629 23:03:37.251374 best dqsien dly found for B0: ( 1, 9, 16)
7630 23:03:37.254878 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7631 23:03:37.258627 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7632 23:03:37.261548 Total UI for P1: 0, mck2ui 16
7633 23:03:37.265066 best dqsien dly found for B1: ( 1, 9, 22)
7634 23:03:37.268152 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
7635 23:03:37.271660 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7636 23:03:37.275099
7637 23:03:37.278966 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
7638 23:03:37.281531 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7639 23:03:37.284855 [Gating] SW calibration Done
7640 23:03:37.284933 ==
7641 23:03:37.288645 Dram Type= 6, Freq= 0, CH_0, rank 0
7642 23:03:37.292086 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7643 23:03:37.292167 ==
7644 23:03:37.292258 RX Vref Scan: 0
7645 23:03:37.295108
7646 23:03:37.295184 RX Vref 0 -> 0, step: 1
7647 23:03:37.295267
7648 23:03:37.298516 RX Delay 0 -> 252, step: 8
7649 23:03:37.301633 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7650 23:03:37.305268 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
7651 23:03:37.308326 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7652 23:03:37.315082 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7653 23:03:37.318661 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7654 23:03:37.321758 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7655 23:03:37.325302 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7656 23:03:37.329012 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7657 23:03:37.335065 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7658 23:03:37.338585 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7659 23:03:37.341975 iDelay=200, Bit 10, Center 119 (64 ~ 175) 112
7660 23:03:37.345319 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7661 23:03:37.348301 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7662 23:03:37.355457 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7663 23:03:37.358300 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7664 23:03:37.361880 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7665 23:03:37.361971 ==
7666 23:03:37.365551 Dram Type= 6, Freq= 0, CH_0, rank 0
7667 23:03:37.368514 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7668 23:03:37.371845 ==
7669 23:03:37.371929 DQS Delay:
7670 23:03:37.372012 DQS0 = 0, DQS1 = 0
7671 23:03:37.375264 DQM Delay:
7672 23:03:37.375349 DQM0 = 131, DQM1 = 123
7673 23:03:37.378582 DQ Delay:
7674 23:03:37.382154 DQ0 =131, DQ1 =131, DQ2 =127, DQ3 =127
7675 23:03:37.385069 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7676 23:03:37.388434 DQ8 =111, DQ9 =111, DQ10 =119, DQ11 =115
7677 23:03:37.391968 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7678 23:03:37.392047
7679 23:03:37.392128
7680 23:03:37.392206 ==
7681 23:03:37.395317 Dram Type= 6, Freq= 0, CH_0, rank 0
7682 23:03:37.398771 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7683 23:03:37.398847 ==
7684 23:03:37.398967
7685 23:03:37.399046
7686 23:03:37.401718 TX Vref Scan disable
7687 23:03:37.405141 == TX Byte 0 ==
7688 23:03:37.408602 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7689 23:03:37.411943 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7690 23:03:37.415429 == TX Byte 1 ==
7691 23:03:37.418950 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7692 23:03:37.421868 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7693 23:03:37.421945 ==
7694 23:03:37.425640 Dram Type= 6, Freq= 0, CH_0, rank 0
7695 23:03:37.429252 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7696 23:03:37.431802 ==
7697 23:03:37.443416
7698 23:03:37.446832 TX Vref early break, caculate TX vref
7699 23:03:37.450057 TX Vref=16, minBit 1, minWin=21, winSum=359
7700 23:03:37.453520 TX Vref=18, minBit 1, minWin=22, winSum=369
7701 23:03:37.457215 TX Vref=20, minBit 0, minWin=22, winSum=377
7702 23:03:37.459888 TX Vref=22, minBit 4, minWin=22, winSum=389
7703 23:03:37.463470 TX Vref=24, minBit 7, minWin=23, winSum=397
7704 23:03:37.470443 TX Vref=26, minBit 1, minWin=24, winSum=412
7705 23:03:37.473681 TX Vref=28, minBit 4, minWin=24, winSum=417
7706 23:03:37.476640 TX Vref=30, minBit 4, minWin=24, winSum=421
7707 23:03:37.480136 TX Vref=32, minBit 4, minWin=23, winSum=405
7708 23:03:37.483676 TX Vref=34, minBit 0, minWin=23, winSum=395
7709 23:03:37.490097 [TxChooseVref] Worse bit 4, Min win 24, Win sum 421, Final Vref 30
7710 23:03:37.490189
7711 23:03:37.493483 Final TX Range 0 Vref 30
7712 23:03:37.493564
7713 23:03:37.493646 ==
7714 23:03:37.497118 Dram Type= 6, Freq= 0, CH_0, rank 0
7715 23:03:37.500347 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7716 23:03:37.500429 ==
7717 23:03:37.500511
7718 23:03:37.500589
7719 23:03:37.503597 TX Vref Scan disable
7720 23:03:37.507010 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7721 23:03:37.510426 == TX Byte 0 ==
7722 23:03:37.514070 u2DelayCellOfst[0]=14 cells (4 PI)
7723 23:03:37.516845 u2DelayCellOfst[1]=17 cells (5 PI)
7724 23:03:37.520667 u2DelayCellOfst[2]=10 cells (3 PI)
7725 23:03:37.523579 u2DelayCellOfst[3]=14 cells (4 PI)
7726 23:03:37.527224 u2DelayCellOfst[4]=10 cells (3 PI)
7727 23:03:37.530051 u2DelayCellOfst[5]=0 cells (0 PI)
7728 23:03:37.530133 u2DelayCellOfst[6]=21 cells (6 PI)
7729 23:03:37.533860 u2DelayCellOfst[7]=17 cells (5 PI)
7730 23:03:37.540287 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7731 23:03:37.543718 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7732 23:03:37.543793 == TX Byte 1 ==
7733 23:03:37.547462 u2DelayCellOfst[8]=0 cells (0 PI)
7734 23:03:37.550808 u2DelayCellOfst[9]=0 cells (0 PI)
7735 23:03:37.553631 u2DelayCellOfst[10]=7 cells (2 PI)
7736 23:03:37.557223 u2DelayCellOfst[11]=0 cells (0 PI)
7737 23:03:37.560603 u2DelayCellOfst[12]=14 cells (4 PI)
7738 23:03:37.563800 u2DelayCellOfst[13]=14 cells (4 PI)
7739 23:03:37.567202 u2DelayCellOfst[14]=17 cells (5 PI)
7740 23:03:37.570595 u2DelayCellOfst[15]=14 cells (4 PI)
7741 23:03:37.573619 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7742 23:03:37.577184 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7743 23:03:37.580537 DramC Write-DBI on
7744 23:03:37.580619 ==
7745 23:03:37.583505 Dram Type= 6, Freq= 0, CH_0, rank 0
7746 23:03:37.587021 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7747 23:03:37.587103 ==
7748 23:03:37.587168
7749 23:03:37.587228
7750 23:03:37.590800 TX Vref Scan disable
7751 23:03:37.593808 == TX Byte 0 ==
7752 23:03:37.596876 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7753 23:03:37.600399 == TX Byte 1 ==
7754 23:03:37.603572 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
7755 23:03:37.603653 DramC Write-DBI off
7756 23:03:37.603729
7757 23:03:37.607177 [DATLAT]
7758 23:03:37.607259 Freq=1600, CH0 RK0
7759 23:03:37.607324
7760 23:03:37.610261 DATLAT Default: 0xf
7761 23:03:37.610333 0, 0xFFFF, sum = 0
7762 23:03:37.613432 1, 0xFFFF, sum = 0
7763 23:03:37.613505 2, 0xFFFF, sum = 0
7764 23:03:37.616928 3, 0xFFFF, sum = 0
7765 23:03:37.617026 4, 0xFFFF, sum = 0
7766 23:03:37.620490 5, 0xFFFF, sum = 0
7767 23:03:37.620573 6, 0xFFFF, sum = 0
7768 23:03:37.623824 7, 0xFFFF, sum = 0
7769 23:03:37.623934 8, 0xFFFF, sum = 0
7770 23:03:37.627347 9, 0xFFFF, sum = 0
7771 23:03:37.627430 10, 0xFFFF, sum = 0
7772 23:03:37.630425 11, 0xFFFF, sum = 0
7773 23:03:37.633907 12, 0xFFFF, sum = 0
7774 23:03:37.633989 13, 0xFFFF, sum = 0
7775 23:03:37.636842 14, 0x0, sum = 1
7776 23:03:37.636924 15, 0x0, sum = 2
7777 23:03:37.636989 16, 0x0, sum = 3
7778 23:03:37.640583 17, 0x0, sum = 4
7779 23:03:37.640692 best_step = 15
7780 23:03:37.640785
7781 23:03:37.640872 ==
7782 23:03:37.643640 Dram Type= 6, Freq= 0, CH_0, rank 0
7783 23:03:37.650542 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7784 23:03:37.650624 ==
7785 23:03:37.650695 RX Vref Scan: 1
7786 23:03:37.650760
7787 23:03:37.653914 Set Vref Range= 24 -> 127
7788 23:03:37.653996
7789 23:03:37.657366 RX Vref 24 -> 127, step: 1
7790 23:03:37.657443
7791 23:03:37.660308 RX Delay 11 -> 252, step: 4
7792 23:03:37.660387
7793 23:03:37.663503 Set Vref, RX VrefLevel [Byte0]: 24
7794 23:03:37.667121 [Byte1]: 24
7795 23:03:37.667196
7796 23:03:37.670353 Set Vref, RX VrefLevel [Byte0]: 25
7797 23:03:37.673768 [Byte1]: 25
7798 23:03:37.673854
7799 23:03:37.677015 Set Vref, RX VrefLevel [Byte0]: 26
7800 23:03:37.680205 [Byte1]: 26
7801 23:03:37.680285
7802 23:03:37.683712 Set Vref, RX VrefLevel [Byte0]: 27
7803 23:03:37.687223 [Byte1]: 27
7804 23:03:37.691201
7805 23:03:37.691282 Set Vref, RX VrefLevel [Byte0]: 28
7806 23:03:37.694060 [Byte1]: 28
7807 23:03:37.698718
7808 23:03:37.698799 Set Vref, RX VrefLevel [Byte0]: 29
7809 23:03:37.702074 [Byte1]: 29
7810 23:03:37.706033
7811 23:03:37.706118 Set Vref, RX VrefLevel [Byte0]: 30
7812 23:03:37.709469 [Byte1]: 30
7813 23:03:37.713686
7814 23:03:37.713768 Set Vref, RX VrefLevel [Byte0]: 31
7815 23:03:37.717127 [Byte1]: 31
7816 23:03:37.721197
7817 23:03:37.721275 Set Vref, RX VrefLevel [Byte0]: 32
7818 23:03:37.724921 [Byte1]: 32
7819 23:03:37.729393
7820 23:03:37.729475 Set Vref, RX VrefLevel [Byte0]: 33
7821 23:03:37.732774 [Byte1]: 33
7822 23:03:37.736600
7823 23:03:37.736687 Set Vref, RX VrefLevel [Byte0]: 34
7824 23:03:37.740089 [Byte1]: 34
7825 23:03:37.744206
7826 23:03:37.744284 Set Vref, RX VrefLevel [Byte0]: 35
7827 23:03:37.747578 [Byte1]: 35
7828 23:03:37.752090
7829 23:03:37.752169 Set Vref, RX VrefLevel [Byte0]: 36
7830 23:03:37.755134 [Byte1]: 36
7831 23:03:37.759775
7832 23:03:37.759852 Set Vref, RX VrefLevel [Byte0]: 37
7833 23:03:37.762781 [Byte1]: 37
7834 23:03:37.767375
7835 23:03:37.767454 Set Vref, RX VrefLevel [Byte0]: 38
7836 23:03:37.770198 [Byte1]: 38
7837 23:03:37.774795
7838 23:03:37.774929 Set Vref, RX VrefLevel [Byte0]: 39
7839 23:03:37.778001 [Byte1]: 39
7840 23:03:37.782635
7841 23:03:37.782758 Set Vref, RX VrefLevel [Byte0]: 40
7842 23:03:37.785460 [Byte1]: 40
7843 23:03:37.789955
7844 23:03:37.790034 Set Vref, RX VrefLevel [Byte0]: 41
7845 23:03:37.793295 [Byte1]: 41
7846 23:03:37.797358
7847 23:03:37.797488 Set Vref, RX VrefLevel [Byte0]: 42
7848 23:03:37.801115 [Byte1]: 42
7849 23:03:37.805189
7850 23:03:37.805287 Set Vref, RX VrefLevel [Byte0]: 43
7851 23:03:37.808820 [Byte1]: 43
7852 23:03:37.813070
7853 23:03:37.813154 Set Vref, RX VrefLevel [Byte0]: 44
7854 23:03:37.816132 [Byte1]: 44
7855 23:03:37.820372
7856 23:03:37.820459 Set Vref, RX VrefLevel [Byte0]: 45
7857 23:03:37.823647 [Byte1]: 45
7858 23:03:37.828012
7859 23:03:37.828084 Set Vref, RX VrefLevel [Byte0]: 46
7860 23:03:37.831262 [Byte1]: 46
7861 23:03:37.835728
7862 23:03:37.835823 Set Vref, RX VrefLevel [Byte0]: 47
7863 23:03:37.838984 [Byte1]: 47
7864 23:03:37.843108
7865 23:03:37.843188 Set Vref, RX VrefLevel [Byte0]: 48
7866 23:03:37.846636 [Byte1]: 48
7867 23:03:37.851135
7868 23:03:37.851255 Set Vref, RX VrefLevel [Byte0]: 49
7869 23:03:37.854044 [Byte1]: 49
7870 23:03:37.858701
7871 23:03:37.858800 Set Vref, RX VrefLevel [Byte0]: 50
7872 23:03:37.862056 [Byte1]: 50
7873 23:03:37.866084
7874 23:03:37.866166 Set Vref, RX VrefLevel [Byte0]: 51
7875 23:03:37.869706 [Byte1]: 51
7876 23:03:37.873562
7877 23:03:37.873674 Set Vref, RX VrefLevel [Byte0]: 52
7878 23:03:37.880346 [Byte1]: 52
7879 23:03:37.880454
7880 23:03:37.883484 Set Vref, RX VrefLevel [Byte0]: 53
7881 23:03:37.887187 [Byte1]: 53
7882 23:03:37.887270
7883 23:03:37.890248 Set Vref, RX VrefLevel [Byte0]: 54
7884 23:03:37.893445 [Byte1]: 54
7885 23:03:37.893528
7886 23:03:37.896777 Set Vref, RX VrefLevel [Byte0]: 55
7887 23:03:37.899845 [Byte1]: 55
7888 23:03:37.904125
7889 23:03:37.904207 Set Vref, RX VrefLevel [Byte0]: 56
7890 23:03:37.907831 [Byte1]: 56
7891 23:03:37.912008
7892 23:03:37.912090 Set Vref, RX VrefLevel [Byte0]: 57
7893 23:03:37.915148 [Byte1]: 57
7894 23:03:37.919228
7895 23:03:37.919310 Set Vref, RX VrefLevel [Byte0]: 58
7896 23:03:37.922991 [Byte1]: 58
7897 23:03:37.927403
7898 23:03:37.927486 Set Vref, RX VrefLevel [Byte0]: 59
7899 23:03:37.930227 [Byte1]: 59
7900 23:03:37.934531
7901 23:03:37.934613 Set Vref, RX VrefLevel [Byte0]: 60
7902 23:03:37.938087 [Byte1]: 60
7903 23:03:37.942129
7904 23:03:37.942211 Set Vref, RX VrefLevel [Byte0]: 61
7905 23:03:37.945527 [Byte1]: 61
7906 23:03:37.950002
7907 23:03:37.950079 Set Vref, RX VrefLevel [Byte0]: 62
7908 23:03:37.953334 [Byte1]: 62
7909 23:03:37.957411
7910 23:03:37.957490 Set Vref, RX VrefLevel [Byte0]: 63
7911 23:03:37.960652 [Byte1]: 63
7912 23:03:37.965114
7913 23:03:37.965197 Set Vref, RX VrefLevel [Byte0]: 64
7914 23:03:37.968710 [Byte1]: 64
7915 23:03:37.972609
7916 23:03:37.972692 Set Vref, RX VrefLevel [Byte0]: 65
7917 23:03:37.975926 [Byte1]: 65
7918 23:03:37.980528
7919 23:03:37.980611 Set Vref, RX VrefLevel [Byte0]: 66
7920 23:03:37.983485 [Byte1]: 66
7921 23:03:37.988146
7922 23:03:37.988228 Set Vref, RX VrefLevel [Byte0]: 67
7923 23:03:37.991362 [Byte1]: 67
7924 23:03:37.995814
7925 23:03:37.995896 Set Vref, RX VrefLevel [Byte0]: 68
7926 23:03:37.999051 [Byte1]: 68
7927 23:03:38.003376
7928 23:03:38.003458 Set Vref, RX VrefLevel [Byte0]: 69
7929 23:03:38.006420 [Byte1]: 69
7930 23:03:38.011033
7931 23:03:38.011115 Set Vref, RX VrefLevel [Byte0]: 70
7932 23:03:38.014022 [Byte1]: 70
7933 23:03:38.018673
7934 23:03:38.018755 Set Vref, RX VrefLevel [Byte0]: 71
7935 23:03:38.021501 [Byte1]: 71
7936 23:03:38.026252
7937 23:03:38.026327 Set Vref, RX VrefLevel [Byte0]: 72
7938 23:03:38.029445 [Byte1]: 72
7939 23:03:38.033569
7940 23:03:38.033650 Set Vref, RX VrefLevel [Byte0]: 73
7941 23:03:38.037035 [Byte1]: 73
7942 23:03:38.041393
7943 23:03:38.041472 Set Vref, RX VrefLevel [Byte0]: 74
7944 23:03:38.044738 [Byte1]: 74
7945 23:03:38.048814
7946 23:03:38.048890 Set Vref, RX VrefLevel [Byte0]: 75
7947 23:03:38.052258 [Byte1]: 75
7948 23:03:38.057007
7949 23:03:38.057084 Set Vref, RX VrefLevel [Byte0]: 76
7950 23:03:38.059852 [Byte1]: 76
7951 23:03:38.064409
7952 23:03:38.064493 Set Vref, RX VrefLevel [Byte0]: 77
7953 23:03:38.067717 [Byte1]: 77
7954 23:03:38.071749
7955 23:03:38.071851 Final RX Vref Byte 0 = 62 to rank0
7956 23:03:38.074873 Final RX Vref Byte 1 = 61 to rank0
7957 23:03:38.078169 Final RX Vref Byte 0 = 62 to rank1
7958 23:03:38.081349 Final RX Vref Byte 1 = 61 to rank1==
7959 23:03:38.084720 Dram Type= 6, Freq= 0, CH_0, rank 0
7960 23:03:38.091568 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7961 23:03:38.091682 ==
7962 23:03:38.091747 DQS Delay:
7963 23:03:38.091807 DQS0 = 0, DQS1 = 0
7964 23:03:38.094725 DQM Delay:
7965 23:03:38.094832 DQM0 = 130, DQM1 = 121
7966 23:03:38.098701 DQ Delay:
7967 23:03:38.101709 DQ0 =130, DQ1 =134, DQ2 =126, DQ3 =126
7968 23:03:38.105353 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =138
7969 23:03:38.108355 DQ8 =110, DQ9 =110, DQ10 =122, DQ11 =116
7970 23:03:38.111813 DQ12 =126, DQ13 =126, DQ14 =132, DQ15 =132
7971 23:03:38.111902
7972 23:03:38.111963
7973 23:03:38.112021
7974 23:03:38.115212 [DramC_TX_OE_Calibration] TA2
7975 23:03:38.118426 Original DQ_B0 (3 6) =30, OEN = 27
7976 23:03:38.121463 Original DQ_B1 (3 6) =30, OEN = 27
7977 23:03:38.124959 24, 0x0, End_B0=24 End_B1=24
7978 23:03:38.125035 25, 0x0, End_B0=25 End_B1=25
7979 23:03:38.128420 26, 0x0, End_B0=26 End_B1=26
7980 23:03:38.131834 27, 0x0, End_B0=27 End_B1=27
7981 23:03:38.135330 28, 0x0, End_B0=28 End_B1=28
7982 23:03:38.135407 29, 0x0, End_B0=29 End_B1=29
7983 23:03:38.138296 30, 0x0, End_B0=30 End_B1=30
7984 23:03:38.141811 31, 0x4141, End_B0=30 End_B1=30
7985 23:03:38.145123 Byte0 end_step=30 best_step=27
7986 23:03:38.148405 Byte1 end_step=30 best_step=27
7987 23:03:38.151630 Byte0 TX OE(2T, 0.5T) = (3, 3)
7988 23:03:38.151744 Byte1 TX OE(2T, 0.5T) = (3, 3)
7989 23:03:38.151852
7990 23:03:38.151945
7991 23:03:38.161847 [DQSOSCAuto] RK0, (LSB)MR18= 0x1509, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 399 ps
7992 23:03:38.165182 CH0 RK0: MR19=303, MR18=1509
7993 23:03:38.171884 CH0_RK0: MR19=0x303, MR18=0x1509, DQSOSC=399, MR23=63, INC=23, DEC=15
7994 23:03:38.171992
7995 23:03:38.174823 ----->DramcWriteLeveling(PI) begin...
7996 23:03:38.174915 ==
7997 23:03:38.178424 Dram Type= 6, Freq= 0, CH_0, rank 1
7998 23:03:38.181990 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7999 23:03:38.182074 ==
8000 23:03:38.184844 Write leveling (Byte 0): 34 => 34
8001 23:03:38.188294 Write leveling (Byte 1): 26 => 26
8002 23:03:38.191488 DramcWriteLeveling(PI) end<-----
8003 23:03:38.191570
8004 23:03:38.191635 ==
8005 23:03:38.194916 Dram Type= 6, Freq= 0, CH_0, rank 1
8006 23:03:38.198337 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8007 23:03:38.198419 ==
8008 23:03:38.201560 [Gating] SW mode calibration
8009 23:03:38.207971 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8010 23:03:38.214904 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8011 23:03:38.217940 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8012 23:03:38.222317 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8013 23:03:38.228175 1 4 8 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
8014 23:03:38.232001 1 4 12 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
8015 23:03:38.234879 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8016 23:03:38.241733 1 4 20 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
8017 23:03:38.245436 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8018 23:03:38.248737 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8019 23:03:38.254824 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8020 23:03:38.258596 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8021 23:03:38.261540 1 5 8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
8022 23:03:38.264708 1 5 12 | B1->B0 | 3434 2525 | 1 0 | (1 1) (1 0)
8023 23:03:38.271524 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8024 23:03:38.275081 1 5 20 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
8025 23:03:38.278489 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8026 23:03:38.284666 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8027 23:03:38.288017 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8028 23:03:38.291316 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8029 23:03:38.298479 1 6 8 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
8030 23:03:38.301745 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8031 23:03:38.304780 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8032 23:03:38.311374 1 6 20 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
8033 23:03:38.314526 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8034 23:03:38.317904 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8035 23:03:38.325118 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8036 23:03:38.328138 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8037 23:03:38.331884 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8038 23:03:38.337838 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8039 23:03:38.341378 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8040 23:03:38.345021 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8041 23:03:38.351944 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8042 23:03:38.355067 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8043 23:03:38.358606 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8044 23:03:38.361669 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8045 23:03:38.368398 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8046 23:03:38.371733 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8047 23:03:38.374725 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8048 23:03:38.381715 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8049 23:03:38.384812 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8050 23:03:38.387933 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8051 23:03:38.395097 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8052 23:03:38.397999 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8053 23:03:38.401607 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8054 23:03:38.408168 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8055 23:03:38.408298 Total UI for P1: 0, mck2ui 16
8056 23:03:38.415117 best dqsien dly found for B0: ( 1, 9, 8)
8057 23:03:38.418460 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8058 23:03:38.421400 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8059 23:03:38.428364 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8060 23:03:38.428447 Total UI for P1: 0, mck2ui 16
8061 23:03:38.434581 best dqsien dly found for B1: ( 1, 9, 18)
8062 23:03:38.438049 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8063 23:03:38.441425 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8064 23:03:38.441507
8065 23:03:38.444994 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8066 23:03:38.448641 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8067 23:03:38.451577 [Gating] SW calibration Done
8068 23:03:38.451658 ==
8069 23:03:38.454870 Dram Type= 6, Freq= 0, CH_0, rank 1
8070 23:03:38.458422 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8071 23:03:38.458504 ==
8072 23:03:38.461837 RX Vref Scan: 0
8073 23:03:38.461927
8074 23:03:38.461991 RX Vref 0 -> 0, step: 1
8075 23:03:38.462051
8076 23:03:38.464744 RX Delay 0 -> 252, step: 8
8077 23:03:38.468128 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8078 23:03:38.471534 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8079 23:03:38.478577 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8080 23:03:38.482135 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8081 23:03:38.485291 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8082 23:03:38.488810 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8083 23:03:38.492116 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8084 23:03:38.498314 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8085 23:03:38.501756 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8086 23:03:38.504902 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8087 23:03:38.508490 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8088 23:03:38.511780 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8089 23:03:38.518576 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8090 23:03:38.522395 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8091 23:03:38.525343 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8092 23:03:38.528720 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8093 23:03:38.528810 ==
8094 23:03:38.532350 Dram Type= 6, Freq= 0, CH_0, rank 1
8095 23:03:38.535644 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8096 23:03:38.538756 ==
8097 23:03:38.538839 DQS Delay:
8098 23:03:38.538928 DQS0 = 0, DQS1 = 0
8099 23:03:38.542422 DQM Delay:
8100 23:03:38.542518 DQM0 = 131, DQM1 = 124
8101 23:03:38.545370 DQ Delay:
8102 23:03:38.548805 DQ0 =131, DQ1 =131, DQ2 =127, DQ3 =127
8103 23:03:38.552104 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
8104 23:03:38.555670 DQ8 =115, DQ9 =115, DQ10 =123, DQ11 =119
8105 23:03:38.559284 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =131
8106 23:03:38.559366
8107 23:03:38.559429
8108 23:03:38.559488 ==
8109 23:03:38.562428 Dram Type= 6, Freq= 0, CH_0, rank 1
8110 23:03:38.565831 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8111 23:03:38.565912 ==
8112 23:03:38.565976
8113 23:03:38.566034
8114 23:03:38.569069 TX Vref Scan disable
8115 23:03:38.572484 == TX Byte 0 ==
8116 23:03:38.575818 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8117 23:03:38.578718 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8118 23:03:38.582159 == TX Byte 1 ==
8119 23:03:38.585783 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8120 23:03:38.589186 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8121 23:03:38.589268 ==
8122 23:03:38.592000 Dram Type= 6, Freq= 0, CH_0, rank 1
8123 23:03:38.595353 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8124 23:03:38.598801 ==
8125 23:03:38.612219
8126 23:03:38.615558 TX Vref early break, caculate TX vref
8127 23:03:38.619161 TX Vref=16, minBit 4, minWin=22, winSum=371
8128 23:03:38.622238 TX Vref=18, minBit 9, minWin=22, winSum=381
8129 23:03:38.625504 TX Vref=20, minBit 2, minWin=23, winSum=387
8130 23:03:38.629167 TX Vref=22, minBit 1, minWin=24, winSum=396
8131 23:03:38.632324 TX Vref=24, minBit 5, minWin=23, winSum=400
8132 23:03:38.635629 TX Vref=26, minBit 1, minWin=25, winSum=412
8133 23:03:38.642228 TX Vref=28, minBit 2, minWin=25, winSum=414
8134 23:03:38.645407 TX Vref=30, minBit 4, minWin=25, winSum=418
8135 23:03:38.649215 TX Vref=32, minBit 8, minWin=24, winSum=411
8136 23:03:38.651967 TX Vref=34, minBit 0, minWin=24, winSum=402
8137 23:03:38.655836 TX Vref=36, minBit 4, minWin=23, winSum=392
8138 23:03:38.662409 [TxChooseVref] Worse bit 4, Min win 25, Win sum 418, Final Vref 30
8139 23:03:38.662493
8140 23:03:38.665589 Final TX Range 0 Vref 30
8141 23:03:38.665671
8142 23:03:38.665736 ==
8143 23:03:38.668673 Dram Type= 6, Freq= 0, CH_0, rank 1
8144 23:03:38.672166 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8145 23:03:38.672276 ==
8146 23:03:38.672382
8147 23:03:38.672484
8148 23:03:38.675464 TX Vref Scan disable
8149 23:03:38.682184 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8150 23:03:38.682297 == TX Byte 0 ==
8151 23:03:38.685647 u2DelayCellOfst[0]=14 cells (4 PI)
8152 23:03:38.689200 u2DelayCellOfst[1]=17 cells (5 PI)
8153 23:03:38.692128 u2DelayCellOfst[2]=10 cells (3 PI)
8154 23:03:38.695815 u2DelayCellOfst[3]=10 cells (3 PI)
8155 23:03:38.698822 u2DelayCellOfst[4]=10 cells (3 PI)
8156 23:03:38.702351 u2DelayCellOfst[5]=0 cells (0 PI)
8157 23:03:38.705950 u2DelayCellOfst[6]=17 cells (5 PI)
8158 23:03:38.708838 u2DelayCellOfst[7]=17 cells (5 PI)
8159 23:03:38.712398 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8160 23:03:38.715607 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8161 23:03:38.719216 == TX Byte 1 ==
8162 23:03:38.719318 u2DelayCellOfst[8]=0 cells (0 PI)
8163 23:03:38.722842 u2DelayCellOfst[9]=0 cells (0 PI)
8164 23:03:38.726139 u2DelayCellOfst[10]=7 cells (2 PI)
8165 23:03:38.728917 u2DelayCellOfst[11]=0 cells (0 PI)
8166 23:03:38.732324 u2DelayCellOfst[12]=10 cells (3 PI)
8167 23:03:38.736067 u2DelayCellOfst[13]=7 cells (2 PI)
8168 23:03:38.738835 u2DelayCellOfst[14]=14 cells (4 PI)
8169 23:03:38.742247 u2DelayCellOfst[15]=10 cells (3 PI)
8170 23:03:38.745781 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8171 23:03:38.752541 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8172 23:03:38.752650 DramC Write-DBI on
8173 23:03:38.752743 ==
8174 23:03:38.755506 Dram Type= 6, Freq= 0, CH_0, rank 1
8175 23:03:38.759080 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8176 23:03:38.759183 ==
8177 23:03:38.759277
8178 23:03:38.762259
8179 23:03:38.762363 TX Vref Scan disable
8180 23:03:38.765904 == TX Byte 0 ==
8181 23:03:38.769271 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8182 23:03:38.772575 == TX Byte 1 ==
8183 23:03:38.775949 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8184 23:03:38.776062 DramC Write-DBI off
8185 23:03:38.779054
8186 23:03:38.779162 [DATLAT]
8187 23:03:38.779267 Freq=1600, CH0 RK1
8188 23:03:38.779370
8189 23:03:38.782632 DATLAT Default: 0xf
8190 23:03:38.782738 0, 0xFFFF, sum = 0
8191 23:03:38.785898 1, 0xFFFF, sum = 0
8192 23:03:38.786006 2, 0xFFFF, sum = 0
8193 23:03:38.788838 3, 0xFFFF, sum = 0
8194 23:03:38.788952 4, 0xFFFF, sum = 0
8195 23:03:38.792067 5, 0xFFFF, sum = 0
8196 23:03:38.795841 6, 0xFFFF, sum = 0
8197 23:03:38.795951 7, 0xFFFF, sum = 0
8198 23:03:38.799317 8, 0xFFFF, sum = 0
8199 23:03:38.799435 9, 0xFFFF, sum = 0
8200 23:03:38.802267 10, 0xFFFF, sum = 0
8201 23:03:38.802378 11, 0xFFFF, sum = 0
8202 23:03:38.805297 12, 0xFFFF, sum = 0
8203 23:03:38.805406 13, 0xFFFF, sum = 0
8204 23:03:38.808792 14, 0x0, sum = 1
8205 23:03:38.808904 15, 0x0, sum = 2
8206 23:03:38.812365 16, 0x0, sum = 3
8207 23:03:38.812473 17, 0x0, sum = 4
8208 23:03:38.815349 best_step = 15
8209 23:03:38.815456
8210 23:03:38.815560 ==
8211 23:03:38.818977 Dram Type= 6, Freq= 0, CH_0, rank 1
8212 23:03:38.822310 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8213 23:03:38.822420 ==
8214 23:03:38.822522 RX Vref Scan: 0
8215 23:03:38.822623
8216 23:03:38.825789 RX Vref 0 -> 0, step: 1
8217 23:03:38.825911
8218 23:03:38.829012 RX Delay 11 -> 252, step: 4
8219 23:03:38.832505 iDelay=191, Bit 0, Center 126 (71 ~ 182) 112
8220 23:03:38.835947 iDelay=191, Bit 1, Center 130 (75 ~ 186) 112
8221 23:03:38.842663 iDelay=191, Bit 2, Center 124 (71 ~ 178) 108
8222 23:03:38.845737 iDelay=191, Bit 3, Center 126 (71 ~ 182) 112
8223 23:03:38.849115 iDelay=191, Bit 4, Center 128 (75 ~ 182) 108
8224 23:03:38.852556 iDelay=191, Bit 5, Center 116 (63 ~ 170) 108
8225 23:03:38.856080 iDelay=191, Bit 6, Center 136 (83 ~ 190) 108
8226 23:03:38.862247 iDelay=191, Bit 7, Center 136 (83 ~ 190) 108
8227 23:03:38.865499 iDelay=191, Bit 8, Center 112 (59 ~ 166) 108
8228 23:03:38.869111 iDelay=191, Bit 9, Center 110 (55 ~ 166) 112
8229 23:03:38.872295 iDelay=191, Bit 10, Center 122 (67 ~ 178) 112
8230 23:03:38.875627 iDelay=191, Bit 11, Center 116 (63 ~ 170) 108
8231 23:03:38.882304 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8232 23:03:38.885860 iDelay=191, Bit 13, Center 126 (71 ~ 182) 112
8233 23:03:38.888957 iDelay=191, Bit 14, Center 134 (79 ~ 190) 112
8234 23:03:38.892356 iDelay=191, Bit 15, Center 130 (75 ~ 186) 112
8235 23:03:38.892461 ==
8236 23:03:38.895859 Dram Type= 6, Freq= 0, CH_0, rank 1
8237 23:03:38.902210 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8238 23:03:38.902317 ==
8239 23:03:38.902422 DQS Delay:
8240 23:03:38.902522 DQS0 = 0, DQS1 = 0
8241 23:03:38.905549 DQM Delay:
8242 23:03:38.905650 DQM0 = 127, DQM1 = 122
8243 23:03:38.909287 DQ Delay:
8244 23:03:38.912235 DQ0 =126, DQ1 =130, DQ2 =124, DQ3 =126
8245 23:03:38.915613 DQ4 =128, DQ5 =116, DQ6 =136, DQ7 =136
8246 23:03:38.919247 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
8247 23:03:38.922577 DQ12 =126, DQ13 =126, DQ14 =134, DQ15 =130
8248 23:03:38.922684
8249 23:03:38.922785
8250 23:03:38.922919
8251 23:03:38.925658 [DramC_TX_OE_Calibration] TA2
8252 23:03:38.929222 Original DQ_B0 (3 6) =30, OEN = 27
8253 23:03:38.932498 Original DQ_B1 (3 6) =30, OEN = 27
8254 23:03:38.935770 24, 0x0, End_B0=24 End_B1=24
8255 23:03:38.935872 25, 0x0, End_B0=25 End_B1=25
8256 23:03:38.939157 26, 0x0, End_B0=26 End_B1=26
8257 23:03:38.942721 27, 0x0, End_B0=27 End_B1=27
8258 23:03:38.946023 28, 0x0, End_B0=28 End_B1=28
8259 23:03:38.946132 29, 0x0, End_B0=29 End_B1=29
8260 23:03:38.949261 30, 0x0, End_B0=30 End_B1=30
8261 23:03:38.952789 31, 0x4141, End_B0=30 End_B1=30
8262 23:03:38.955784 Byte0 end_step=30 best_step=27
8263 23:03:38.959454 Byte1 end_step=30 best_step=27
8264 23:03:38.962688 Byte0 TX OE(2T, 0.5T) = (3, 3)
8265 23:03:38.962794 Byte1 TX OE(2T, 0.5T) = (3, 3)
8266 23:03:38.962900
8267 23:03:38.962983
8268 23:03:38.972729 [DQSOSCAuto] RK1, (LSB)MR18= 0x170b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 398 ps
8269 23:03:38.975971 CH0 RK1: MR19=303, MR18=170B
8270 23:03:38.982578 CH0_RK1: MR19=0x303, MR18=0x170B, DQSOSC=398, MR23=63, INC=23, DEC=15
8271 23:03:38.982684 [RxdqsGatingPostProcess] freq 1600
8272 23:03:38.989389 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8273 23:03:38.992748 best DQS0 dly(2T, 0.5T) = (1, 1)
8274 23:03:38.996297 best DQS1 dly(2T, 0.5T) = (1, 1)
8275 23:03:38.999631 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8276 23:03:39.002713 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8277 23:03:39.006170 best DQS0 dly(2T, 0.5T) = (1, 1)
8278 23:03:39.009567 best DQS1 dly(2T, 0.5T) = (1, 1)
8279 23:03:39.009671 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8280 23:03:39.012925 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8281 23:03:39.016401 Pre-setting of DQS Precalculation
8282 23:03:39.022731 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8283 23:03:39.022836 ==
8284 23:03:39.026238 Dram Type= 6, Freq= 0, CH_1, rank 0
8285 23:03:39.029326 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8286 23:03:39.029432 ==
8287 23:03:39.036071 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8288 23:03:39.039642 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8289 23:03:39.042839 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8290 23:03:39.049731 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8291 23:03:39.058580 [CA 0] Center 44 (15~73) winsize 59
8292 23:03:39.061767 [CA 1] Center 44 (15~73) winsize 59
8293 23:03:39.065359 [CA 2] Center 38 (10~67) winsize 58
8294 23:03:39.068574 [CA 3] Center 37 (8~67) winsize 60
8295 23:03:39.072225 [CA 4] Center 38 (9~68) winsize 60
8296 23:03:39.075212 [CA 5] Center 38 (9~67) winsize 59
8297 23:03:39.075323
8298 23:03:39.078857 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8299 23:03:39.078972
8300 23:03:39.082186 [CATrainingPosCal] consider 1 rank data
8301 23:03:39.085053 u2DelayCellTimex100 = 275/100 ps
8302 23:03:39.088371 CA0 delay=44 (15~73),Diff = 7 PI (24 cell)
8303 23:03:39.095248 CA1 delay=44 (15~73),Diff = 7 PI (24 cell)
8304 23:03:39.098564 CA2 delay=38 (10~67),Diff = 1 PI (3 cell)
8305 23:03:39.101907 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8306 23:03:39.105747 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8307 23:03:39.108856 CA5 delay=38 (9~67),Diff = 1 PI (3 cell)
8308 23:03:39.108970
8309 23:03:39.112069 CA PerBit enable=1, Macro0, CA PI delay=37
8310 23:03:39.112183
8311 23:03:39.115498 [CBTSetCACLKResult] CA Dly = 37
8312 23:03:39.115610 CS Dly: 9 (0~40)
8313 23:03:39.122173 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8314 23:03:39.125596 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8315 23:03:39.125714 ==
8316 23:03:39.128361 Dram Type= 6, Freq= 0, CH_1, rank 1
8317 23:03:39.131985 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8318 23:03:39.132096 ==
8319 23:03:39.138809 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8320 23:03:39.141776 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8321 23:03:39.148697 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8322 23:03:39.152112 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8323 23:03:39.161603 [CA 0] Center 43 (15~72) winsize 58
8324 23:03:39.165008 [CA 1] Center 43 (14~72) winsize 59
8325 23:03:39.168523 [CA 2] Center 38 (10~67) winsize 58
8326 23:03:39.171990 [CA 3] Center 37 (8~66) winsize 59
8327 23:03:39.175322 [CA 4] Center 38 (9~68) winsize 60
8328 23:03:39.178356 [CA 5] Center 37 (8~66) winsize 59
8329 23:03:39.178462
8330 23:03:39.181965 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8331 23:03:39.182072
8332 23:03:39.185069 [CATrainingPosCal] consider 2 rank data
8333 23:03:39.188619 u2DelayCellTimex100 = 275/100 ps
8334 23:03:39.192058 CA0 delay=43 (15~72),Diff = 6 PI (21 cell)
8335 23:03:39.199162 CA1 delay=43 (15~72),Diff = 6 PI (21 cell)
8336 23:03:39.201803 CA2 delay=38 (10~67),Diff = 1 PI (3 cell)
8337 23:03:39.205360 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8338 23:03:39.208567 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8339 23:03:39.212068 CA5 delay=37 (9~66),Diff = 0 PI (0 cell)
8340 23:03:39.212171
8341 23:03:39.215636 CA PerBit enable=1, Macro0, CA PI delay=37
8342 23:03:39.215736
8343 23:03:39.218521 [CBTSetCACLKResult] CA Dly = 37
8344 23:03:39.222027 CS Dly: 11 (0~44)
8345 23:03:39.225154 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8346 23:03:39.229263 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8347 23:03:39.229371
8348 23:03:39.232040 ----->DramcWriteLeveling(PI) begin...
8349 23:03:39.232150 ==
8350 23:03:39.235529 Dram Type= 6, Freq= 0, CH_1, rank 0
8351 23:03:39.238785 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8352 23:03:39.238924 ==
8353 23:03:39.241730 Write leveling (Byte 0): 23 => 23
8354 23:03:39.245728 Write leveling (Byte 1): 30 => 30
8355 23:03:39.248837 DramcWriteLeveling(PI) end<-----
8356 23:03:39.248948
8357 23:03:39.249049 ==
8358 23:03:39.252354 Dram Type= 6, Freq= 0, CH_1, rank 0
8359 23:03:39.259007 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8360 23:03:39.259117 ==
8361 23:03:39.259221 [Gating] SW mode calibration
8362 23:03:39.268779 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8363 23:03:39.272180 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8364 23:03:39.275606 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8365 23:03:39.282290 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8366 23:03:39.285577 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8367 23:03:39.288802 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8368 23:03:39.295504 1 4 16 | B1->B0 | 3131 2c2c | 0 1 | (0 0) (0 0)
8369 23:03:39.298634 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8370 23:03:39.301861 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8371 23:03:39.308805 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8372 23:03:39.312342 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8373 23:03:39.315316 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8374 23:03:39.322089 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8375 23:03:39.325638 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8376 23:03:39.329128 1 5 16 | B1->B0 | 2f2f 3434 | 0 1 | (1 0) (1 0)
8377 23:03:39.335490 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8378 23:03:39.338624 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8379 23:03:39.343033 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8380 23:03:39.345439 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8381 23:03:39.352024 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8382 23:03:39.355180 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8383 23:03:39.358619 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8384 23:03:39.365240 1 6 16 | B1->B0 | 3c3c 2a2a | 1 0 | (0 0) (0 0)
8385 23:03:39.368736 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8386 23:03:39.372277 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8387 23:03:39.378683 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8388 23:03:39.382024 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8389 23:03:39.385324 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8390 23:03:39.392519 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8391 23:03:39.395710 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8392 23:03:39.399242 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8393 23:03:39.405614 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8394 23:03:39.408730 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8395 23:03:39.412172 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 23:03:39.418852 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8397 23:03:39.422510 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 23:03:39.425274 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 23:03:39.432193 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 23:03:39.435670 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 23:03:39.438620 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 23:03:39.445564 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 23:03:39.448949 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 23:03:39.452194 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 23:03:39.455716 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8406 23:03:39.462312 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 23:03:39.465567 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8408 23:03:39.469015 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8409 23:03:39.475835 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8410 23:03:39.478789 Total UI for P1: 0, mck2ui 16
8411 23:03:39.482173 best dqsien dly found for B0: ( 1, 9, 14)
8412 23:03:39.482283 Total UI for P1: 0, mck2ui 16
8413 23:03:39.488538 best dqsien dly found for B1: ( 1, 9, 14)
8414 23:03:39.491936 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8415 23:03:39.495486 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8416 23:03:39.495589
8417 23:03:39.498733 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8418 23:03:39.501907 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8419 23:03:39.505305 [Gating] SW calibration Done
8420 23:03:39.505414 ==
8421 23:03:39.509044 Dram Type= 6, Freq= 0, CH_1, rank 0
8422 23:03:39.512362 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8423 23:03:39.512472 ==
8424 23:03:39.515326 RX Vref Scan: 0
8425 23:03:39.515429
8426 23:03:39.515528 RX Vref 0 -> 0, step: 1
8427 23:03:39.515629
8428 23:03:39.518740 RX Delay 0 -> 252, step: 8
8429 23:03:39.522113 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8430 23:03:39.528981 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8431 23:03:39.532430 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8432 23:03:39.535277 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8433 23:03:39.538680 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8434 23:03:39.542153 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8435 23:03:39.549283 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8436 23:03:39.552548 iDelay=200, Bit 7, Center 131 (80 ~ 183) 104
8437 23:03:39.555359 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8438 23:03:39.558801 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8439 23:03:39.562310 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8440 23:03:39.565923 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8441 23:03:39.572651 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8442 23:03:39.576091 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8443 23:03:39.579208 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8444 23:03:39.582462 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8445 23:03:39.582570 ==
8446 23:03:39.585531 Dram Type= 6, Freq= 0, CH_1, rank 0
8447 23:03:39.592584 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8448 23:03:39.592760 ==
8449 23:03:39.592913 DQS Delay:
8450 23:03:39.595896 DQS0 = 0, DQS1 = 0
8451 23:03:39.596007 DQM Delay:
8452 23:03:39.596093 DQM0 = 134, DQM1 = 127
8453 23:03:39.599001 DQ Delay:
8454 23:03:39.602259 DQ0 =139, DQ1 =127, DQ2 =123, DQ3 =135
8455 23:03:39.605789 DQ4 =135, DQ5 =143, DQ6 =143, DQ7 =131
8456 23:03:39.608647 DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =123
8457 23:03:39.612149 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8458 23:03:39.612233
8459 23:03:39.612324
8460 23:03:39.612399 ==
8461 23:03:39.615685 Dram Type= 6, Freq= 0, CH_1, rank 0
8462 23:03:39.618823 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8463 23:03:39.622266 ==
8464 23:03:39.622387
8465 23:03:39.622551
8466 23:03:39.622640 TX Vref Scan disable
8467 23:03:39.625795 == TX Byte 0 ==
8468 23:03:39.628766 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8469 23:03:39.632007 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8470 23:03:39.635581 == TX Byte 1 ==
8471 23:03:39.638494 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
8472 23:03:39.641934 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
8473 23:03:39.645407 ==
8474 23:03:39.648782 Dram Type= 6, Freq= 0, CH_1, rank 0
8475 23:03:39.652348 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8476 23:03:39.652449 ==
8477 23:03:39.665911
8478 23:03:39.669160 TX Vref early break, caculate TX vref
8479 23:03:39.672872 TX Vref=16, minBit 8, minWin=20, winSum=362
8480 23:03:39.675683 TX Vref=18, minBit 8, minWin=21, winSum=375
8481 23:03:39.679576 TX Vref=20, minBit 8, minWin=22, winSum=380
8482 23:03:39.682642 TX Vref=22, minBit 8, minWin=23, winSum=392
8483 23:03:39.686275 TX Vref=24, minBit 5, minWin=24, winSum=405
8484 23:03:39.690000 TX Vref=26, minBit 8, minWin=23, winSum=413
8485 23:03:39.696277 TX Vref=28, minBit 8, minWin=25, winSum=420
8486 23:03:39.699392 TX Vref=30, minBit 9, minWin=25, winSum=419
8487 23:03:39.702879 TX Vref=32, minBit 11, minWin=24, winSum=410
8488 23:03:39.706466 TX Vref=34, minBit 0, minWin=24, winSum=401
8489 23:03:39.709678 TX Vref=36, minBit 6, minWin=23, winSum=388
8490 23:03:39.716172 [TxChooseVref] Worse bit 8, Min win 25, Win sum 420, Final Vref 28
8491 23:03:39.716279
8492 23:03:39.720266 Final TX Range 0 Vref 28
8493 23:03:39.720342
8494 23:03:39.720423 ==
8495 23:03:39.723194 Dram Type= 6, Freq= 0, CH_1, rank 0
8496 23:03:39.726068 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8497 23:03:39.726175 ==
8498 23:03:39.726277
8499 23:03:39.726365
8500 23:03:39.729585 TX Vref Scan disable
8501 23:03:39.736250 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8502 23:03:39.736342 == TX Byte 0 ==
8503 23:03:39.739414 u2DelayCellOfst[0]=17 cells (5 PI)
8504 23:03:39.743145 u2DelayCellOfst[1]=14 cells (4 PI)
8505 23:03:39.746377 u2DelayCellOfst[2]=0 cells (0 PI)
8506 23:03:39.749963 u2DelayCellOfst[3]=7 cells (2 PI)
8507 23:03:39.752905 u2DelayCellOfst[4]=7 cells (2 PI)
8508 23:03:39.756509 u2DelayCellOfst[5]=17 cells (5 PI)
8509 23:03:39.759819 u2DelayCellOfst[6]=17 cells (5 PI)
8510 23:03:39.759901 u2DelayCellOfst[7]=7 cells (2 PI)
8511 23:03:39.766485 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8512 23:03:39.770154 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8513 23:03:39.770254 == TX Byte 1 ==
8514 23:03:39.773749 u2DelayCellOfst[8]=0 cells (0 PI)
8515 23:03:39.776316 u2DelayCellOfst[9]=3 cells (1 PI)
8516 23:03:39.779738 u2DelayCellOfst[10]=7 cells (2 PI)
8517 23:03:39.783251 u2DelayCellOfst[11]=3 cells (1 PI)
8518 23:03:39.786486 u2DelayCellOfst[12]=10 cells (3 PI)
8519 23:03:39.790176 u2DelayCellOfst[13]=14 cells (4 PI)
8520 23:03:39.793281 u2DelayCellOfst[14]=14 cells (4 PI)
8521 23:03:39.796873 u2DelayCellOfst[15]=14 cells (4 PI)
8522 23:03:39.800134 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8523 23:03:39.803438 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
8524 23:03:39.806260 DramC Write-DBI on
8525 23:03:39.806341 ==
8526 23:03:39.810084 Dram Type= 6, Freq= 0, CH_1, rank 0
8527 23:03:39.813145 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8528 23:03:39.813223 ==
8529 23:03:39.813301
8530 23:03:39.813393
8531 23:03:39.816788 TX Vref Scan disable
8532 23:03:39.819919 == TX Byte 0 ==
8533 23:03:39.823397 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8534 23:03:39.823479 == TX Byte 1 ==
8535 23:03:39.829770 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8536 23:03:39.829885 DramC Write-DBI off
8537 23:03:39.829989
8538 23:03:39.833746 [DATLAT]
8539 23:03:39.833832 Freq=1600, CH1 RK0
8540 23:03:39.833906
8541 23:03:39.836932 DATLAT Default: 0xf
8542 23:03:39.837016 0, 0xFFFF, sum = 0
8543 23:03:39.839687 1, 0xFFFF, sum = 0
8544 23:03:39.839763 2, 0xFFFF, sum = 0
8545 23:03:39.843414 3, 0xFFFF, sum = 0
8546 23:03:39.843493 4, 0xFFFF, sum = 0
8547 23:03:39.846629 5, 0xFFFF, sum = 0
8548 23:03:39.846730 6, 0xFFFF, sum = 0
8549 23:03:39.850005 7, 0xFFFF, sum = 0
8550 23:03:39.850105 8, 0xFFFF, sum = 0
8551 23:03:39.853502 9, 0xFFFF, sum = 0
8552 23:03:39.853588 10, 0xFFFF, sum = 0
8553 23:03:39.857347 11, 0xFFFF, sum = 0
8554 23:03:39.857433 12, 0xFFFF, sum = 0
8555 23:03:39.859767 13, 0xFFFF, sum = 0
8556 23:03:39.859852 14, 0x0, sum = 1
8557 23:03:39.863205 15, 0x0, sum = 2
8558 23:03:39.863289 16, 0x0, sum = 3
8559 23:03:39.867096 17, 0x0, sum = 4
8560 23:03:39.867180 best_step = 15
8561 23:03:39.867246
8562 23:03:39.867307 ==
8563 23:03:39.870150 Dram Type= 6, Freq= 0, CH_1, rank 0
8564 23:03:39.877158 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8565 23:03:39.877248 ==
8566 23:03:39.877315 RX Vref Scan: 1
8567 23:03:39.877377
8568 23:03:39.879853 Set Vref Range= 24 -> 127
8569 23:03:39.879936
8570 23:03:39.883327 RX Vref 24 -> 127, step: 1
8571 23:03:39.883410
8572 23:03:39.883475 RX Delay 11 -> 252, step: 4
8573 23:03:39.886672
8574 23:03:39.886754 Set Vref, RX VrefLevel [Byte0]: 24
8575 23:03:39.890148 [Byte1]: 24
8576 23:03:39.894285
8577 23:03:39.894367 Set Vref, RX VrefLevel [Byte0]: 25
8578 23:03:39.897636 [Byte1]: 25
8579 23:03:39.902079
8580 23:03:39.902161 Set Vref, RX VrefLevel [Byte0]: 26
8581 23:03:39.905527 [Byte1]: 26
8582 23:03:39.909568
8583 23:03:39.909650 Set Vref, RX VrefLevel [Byte0]: 27
8584 23:03:39.913090 [Byte1]: 27
8585 23:03:39.917349
8586 23:03:39.917431 Set Vref, RX VrefLevel [Byte0]: 28
8587 23:03:39.920677 [Byte1]: 28
8588 23:03:39.924729
8589 23:03:39.924812 Set Vref, RX VrefLevel [Byte0]: 29
8590 23:03:39.928410 [Byte1]: 29
8591 23:03:39.933118
8592 23:03:39.933200 Set Vref, RX VrefLevel [Byte0]: 30
8593 23:03:39.935876 [Byte1]: 30
8594 23:03:39.939806
8595 23:03:39.939890 Set Vref, RX VrefLevel [Byte0]: 31
8596 23:03:39.943414 [Byte1]: 31
8597 23:03:39.947740
8598 23:03:39.947822 Set Vref, RX VrefLevel [Byte0]: 32
8599 23:03:39.951082 [Byte1]: 32
8600 23:03:39.955579
8601 23:03:39.955661 Set Vref, RX VrefLevel [Byte0]: 33
8602 23:03:39.958721 [Byte1]: 33
8603 23:03:39.962773
8604 23:03:39.962856 Set Vref, RX VrefLevel [Byte0]: 34
8605 23:03:39.966249 [Byte1]: 34
8606 23:03:39.970296
8607 23:03:39.970379 Set Vref, RX VrefLevel [Byte0]: 35
8608 23:03:39.973614 [Byte1]: 35
8609 23:03:39.978337
8610 23:03:39.978420 Set Vref, RX VrefLevel [Byte0]: 36
8611 23:03:39.981127 [Byte1]: 36
8612 23:03:39.985860
8613 23:03:39.985943 Set Vref, RX VrefLevel [Byte0]: 37
8614 23:03:39.988744 [Byte1]: 37
8615 23:03:39.993159
8616 23:03:39.993241 Set Vref, RX VrefLevel [Byte0]: 38
8617 23:03:39.996697 [Byte1]: 38
8618 23:03:40.000875
8619 23:03:40.000958 Set Vref, RX VrefLevel [Byte0]: 39
8620 23:03:40.003946 [Byte1]: 39
8621 23:03:40.008725
8622 23:03:40.008808 Set Vref, RX VrefLevel [Byte0]: 40
8623 23:03:40.011833 [Byte1]: 40
8624 23:03:40.016236
8625 23:03:40.016318 Set Vref, RX VrefLevel [Byte0]: 41
8626 23:03:40.019577 [Byte1]: 41
8627 23:03:40.023521
8628 23:03:40.023603 Set Vref, RX VrefLevel [Byte0]: 42
8629 23:03:40.026796 [Byte1]: 42
8630 23:03:40.031319
8631 23:03:40.031401 Set Vref, RX VrefLevel [Byte0]: 43
8632 23:03:40.034762 [Byte1]: 43
8633 23:03:40.038758
8634 23:03:40.038866 Set Vref, RX VrefLevel [Byte0]: 44
8635 23:03:40.042481 [Byte1]: 44
8636 23:03:40.046636
8637 23:03:40.046736 Set Vref, RX VrefLevel [Byte0]: 45
8638 23:03:40.049825 [Byte1]: 45
8639 23:03:40.054229
8640 23:03:40.054302 Set Vref, RX VrefLevel [Byte0]: 46
8641 23:03:40.058053 [Byte1]: 46
8642 23:03:40.061576
8643 23:03:40.061672 Set Vref, RX VrefLevel [Byte0]: 47
8644 23:03:40.065293 [Byte1]: 47
8645 23:03:40.069848
8646 23:03:40.069946 Set Vref, RX VrefLevel [Byte0]: 48
8647 23:03:40.072924 [Byte1]: 48
8648 23:03:40.076941
8649 23:03:40.077041 Set Vref, RX VrefLevel [Byte0]: 49
8650 23:03:40.080504 [Byte1]: 49
8651 23:03:40.084700
8652 23:03:40.084798 Set Vref, RX VrefLevel [Byte0]: 50
8653 23:03:40.088185 [Byte1]: 50
8654 23:03:40.092198
8655 23:03:40.092305 Set Vref, RX VrefLevel [Byte0]: 51
8656 23:03:40.095697 [Byte1]: 51
8657 23:03:40.100089
8658 23:03:40.100171 Set Vref, RX VrefLevel [Byte0]: 52
8659 23:03:40.102970 [Byte1]: 52
8660 23:03:40.107352
8661 23:03:40.107434 Set Vref, RX VrefLevel [Byte0]: 53
8662 23:03:40.110698 [Byte1]: 53
8663 23:03:40.115520
8664 23:03:40.115662 Set Vref, RX VrefLevel [Byte0]: 54
8665 23:03:40.118567 [Byte1]: 54
8666 23:03:40.122802
8667 23:03:40.122929 Set Vref, RX VrefLevel [Byte0]: 55
8668 23:03:40.125926 [Byte1]: 55
8669 23:03:40.130517
8670 23:03:40.130598 Set Vref, RX VrefLevel [Byte0]: 56
8671 23:03:40.133766 [Byte1]: 56
8672 23:03:40.138499
8673 23:03:40.138597 Set Vref, RX VrefLevel [Byte0]: 57
8674 23:03:40.141143 [Byte1]: 57
8675 23:03:40.145301
8676 23:03:40.145381 Set Vref, RX VrefLevel [Byte0]: 58
8677 23:03:40.148850 [Byte1]: 58
8678 23:03:40.153588
8679 23:03:40.153669 Set Vref, RX VrefLevel [Byte0]: 59
8680 23:03:40.156312 [Byte1]: 59
8681 23:03:40.160855
8682 23:03:40.160950 Set Vref, RX VrefLevel [Byte0]: 60
8683 23:03:40.164420 [Byte1]: 60
8684 23:03:40.168802
8685 23:03:40.168883 Set Vref, RX VrefLevel [Byte0]: 61
8686 23:03:40.171671 [Byte1]: 61
8687 23:03:40.176463
8688 23:03:40.176546 Set Vref, RX VrefLevel [Byte0]: 62
8689 23:03:40.179525 [Byte1]: 62
8690 23:03:40.183398
8691 23:03:40.183481 Set Vref, RX VrefLevel [Byte0]: 63
8692 23:03:40.186789 [Byte1]: 63
8693 23:03:40.190995
8694 23:03:40.191076 Set Vref, RX VrefLevel [Byte0]: 64
8695 23:03:40.194478 [Byte1]: 64
8696 23:03:40.198661
8697 23:03:40.198776 Set Vref, RX VrefLevel [Byte0]: 65
8698 23:03:40.202122 [Byte1]: 65
8699 23:03:40.206311
8700 23:03:40.206391 Set Vref, RX VrefLevel [Byte0]: 66
8701 23:03:40.209971 [Byte1]: 66
8702 23:03:40.213897
8703 23:03:40.214003 Set Vref, RX VrefLevel [Byte0]: 67
8704 23:03:40.217230 [Byte1]: 67
8705 23:03:40.221746
8706 23:03:40.221847 Set Vref, RX VrefLevel [Byte0]: 68
8707 23:03:40.224947 [Byte1]: 68
8708 23:03:40.229587
8709 23:03:40.229668 Set Vref, RX VrefLevel [Byte0]: 69
8710 23:03:40.232296 [Byte1]: 69
8711 23:03:40.236926
8712 23:03:40.237007 Set Vref, RX VrefLevel [Byte0]: 70
8713 23:03:40.240405 [Byte1]: 70
8714 23:03:40.244662
8715 23:03:40.244742 Set Vref, RX VrefLevel [Byte0]: 71
8716 23:03:40.247671 [Byte1]: 71
8717 23:03:40.252570
8718 23:03:40.252651 Set Vref, RX VrefLevel [Byte0]: 72
8719 23:03:40.255389 [Byte1]: 72
8720 23:03:40.259503
8721 23:03:40.259637 Set Vref, RX VrefLevel [Byte0]: 73
8722 23:03:40.263077 [Byte1]: 73
8723 23:03:40.267222
8724 23:03:40.267320 Set Vref, RX VrefLevel [Byte0]: 74
8725 23:03:40.270435 [Byte1]: 74
8726 23:03:40.274845
8727 23:03:40.274976 Final RX Vref Byte 0 = 55 to rank0
8728 23:03:40.278259 Final RX Vref Byte 1 = 54 to rank0
8729 23:03:40.281859 Final RX Vref Byte 0 = 55 to rank1
8730 23:03:40.284890 Final RX Vref Byte 1 = 54 to rank1==
8731 23:03:40.288140 Dram Type= 6, Freq= 0, CH_1, rank 0
8732 23:03:40.295125 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8733 23:03:40.295206 ==
8734 23:03:40.295302 DQS Delay:
8735 23:03:40.295390 DQS0 = 0, DQS1 = 0
8736 23:03:40.298277 DQM Delay:
8737 23:03:40.298375 DQM0 = 130, DQM1 = 125
8738 23:03:40.301779 DQ Delay:
8739 23:03:40.305133 DQ0 =134, DQ1 =124, DQ2 =118, DQ3 =130
8740 23:03:40.308286 DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =126
8741 23:03:40.311577 DQ8 =112, DQ9 =112, DQ10 =128, DQ11 =120
8742 23:03:40.315043 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8743 23:03:40.315124
8744 23:03:40.315187
8745 23:03:40.315245
8746 23:03:40.318670 [DramC_TX_OE_Calibration] TA2
8747 23:03:40.322091 Original DQ_B0 (3 6) =30, OEN = 27
8748 23:03:40.325255 Original DQ_B1 (3 6) =30, OEN = 27
8749 23:03:40.328522 24, 0x0, End_B0=24 End_B1=24
8750 23:03:40.328625 25, 0x0, End_B0=25 End_B1=25
8751 23:03:40.331956 26, 0x0, End_B0=26 End_B1=26
8752 23:03:40.335395 27, 0x0, End_B0=27 End_B1=27
8753 23:03:40.338650 28, 0x0, End_B0=28 End_B1=28
8754 23:03:40.338765 29, 0x0, End_B0=29 End_B1=29
8755 23:03:40.341808 30, 0x0, End_B0=30 End_B1=30
8756 23:03:40.344970 31, 0x4141, End_B0=30 End_B1=30
8757 23:03:40.348477 Byte0 end_step=30 best_step=27
8758 23:03:40.351672 Byte1 end_step=30 best_step=27
8759 23:03:40.355291 Byte0 TX OE(2T, 0.5T) = (3, 3)
8760 23:03:40.355400 Byte1 TX OE(2T, 0.5T) = (3, 3)
8761 23:03:40.355465
8762 23:03:40.355524
8763 23:03:40.365590 [DQSOSCAuto] RK0, (LSB)MR18= 0x13ff, (MSB)MR19= 0x302, tDQSOscB0 = 410 ps tDQSOscB1 = 400 ps
8764 23:03:40.368449 CH1 RK0: MR19=302, MR18=13FF
8765 23:03:40.371715 CH1_RK0: MR19=0x302, MR18=0x13FF, DQSOSC=400, MR23=63, INC=23, DEC=15
8766 23:03:40.375285
8767 23:03:40.378815 ----->DramcWriteLeveling(PI) begin...
8768 23:03:40.378936 ==
8769 23:03:40.382155 Dram Type= 6, Freq= 0, CH_1, rank 1
8770 23:03:40.385001 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8771 23:03:40.385091 ==
8772 23:03:40.388734 Write leveling (Byte 0): 25 => 25
8773 23:03:40.391735 Write leveling (Byte 1): 26 => 26
8774 23:03:40.395409 DramcWriteLeveling(PI) end<-----
8775 23:03:40.395485
8776 23:03:40.395547 ==
8777 23:03:40.398804 Dram Type= 6, Freq= 0, CH_1, rank 1
8778 23:03:40.402090 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8779 23:03:40.402167 ==
8780 23:03:40.405425 [Gating] SW mode calibration
8781 23:03:40.411937 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8782 23:03:40.418825 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8783 23:03:40.422139 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8784 23:03:40.425066 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8785 23:03:40.431927 1 4 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
8786 23:03:40.435102 1 4 12 | B1->B0 | 2b2b 3434 | 1 1 | (0 0) (1 1)
8787 23:03:40.438418 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8788 23:03:40.441786 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8789 23:03:40.448596 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8790 23:03:40.451788 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8791 23:03:40.455241 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8792 23:03:40.462123 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8793 23:03:40.465129 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
8794 23:03:40.468746 1 5 12 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
8795 23:03:40.475452 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8796 23:03:40.478794 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8797 23:03:40.482217 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8798 23:03:40.489192 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8799 23:03:40.492242 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8800 23:03:40.496414 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8801 23:03:40.502293 1 6 8 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
8802 23:03:40.505573 1 6 12 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
8803 23:03:40.508944 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8804 23:03:40.512391 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8805 23:03:40.518798 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8806 23:03:40.522450 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8807 23:03:40.525543 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8808 23:03:40.532114 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8809 23:03:40.535588 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8810 23:03:40.539157 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8811 23:03:40.545296 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8812 23:03:40.548990 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8813 23:03:40.552304 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8814 23:03:40.558790 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8815 23:03:40.561929 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8816 23:03:40.565200 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8817 23:03:40.572498 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8818 23:03:40.575161 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8819 23:03:40.578589 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8820 23:03:40.585411 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8821 23:03:40.588877 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8822 23:03:40.591840 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8823 23:03:40.598622 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8824 23:03:40.602092 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8825 23:03:40.605449 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8826 23:03:40.611911 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8827 23:03:40.611989 Total UI for P1: 0, mck2ui 16
8828 23:03:40.615245 best dqsien dly found for B0: ( 1, 9, 6)
8829 23:03:40.622346 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8830 23:03:40.625585 Total UI for P1: 0, mck2ui 16
8831 23:03:40.628678 best dqsien dly found for B1: ( 1, 9, 10)
8832 23:03:40.632372 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8833 23:03:40.635602 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8834 23:03:40.635676
8835 23:03:40.639077 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8836 23:03:40.641962 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8837 23:03:40.645462 [Gating] SW calibration Done
8838 23:03:40.645533 ==
8839 23:03:40.649149 Dram Type= 6, Freq= 0, CH_1, rank 1
8840 23:03:40.652185 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8841 23:03:40.652257 ==
8842 23:03:40.655379 RX Vref Scan: 0
8843 23:03:40.655454
8844 23:03:40.655512 RX Vref 0 -> 0, step: 1
8845 23:03:40.655569
8846 23:03:40.659253 RX Delay 0 -> 252, step: 8
8847 23:03:40.661991 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8848 23:03:40.669008 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8849 23:03:40.672020 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8850 23:03:40.675775 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8851 23:03:40.678844 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8852 23:03:40.682285 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8853 23:03:40.686138 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8854 23:03:40.692153 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8855 23:03:40.695561 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8856 23:03:40.698951 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8857 23:03:40.702391 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8858 23:03:40.706222 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8859 23:03:40.712215 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8860 23:03:40.715546 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8861 23:03:40.719261 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8862 23:03:40.722587 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8863 23:03:40.722665 ==
8864 23:03:40.725861 Dram Type= 6, Freq= 0, CH_1, rank 1
8865 23:03:40.732578 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8866 23:03:40.732680 ==
8867 23:03:40.732770 DQS Delay:
8868 23:03:40.736006 DQS0 = 0, DQS1 = 0
8869 23:03:40.736079 DQM Delay:
8870 23:03:40.736139 DQM0 = 132, DQM1 = 127
8871 23:03:40.739513 DQ Delay:
8872 23:03:40.742360 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8873 23:03:40.745888 DQ4 =131, DQ5 =147, DQ6 =139, DQ7 =127
8874 23:03:40.749221 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8875 23:03:40.752445 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8876 23:03:40.752519
8877 23:03:40.752608
8878 23:03:40.752666 ==
8879 23:03:40.755744 Dram Type= 6, Freq= 0, CH_1, rank 1
8880 23:03:40.759084 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8881 23:03:40.762848 ==
8882 23:03:40.762973
8883 23:03:40.763050
8884 23:03:40.763108 TX Vref Scan disable
8885 23:03:40.765737 == TX Byte 0 ==
8886 23:03:40.769246 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8887 23:03:40.772669 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8888 23:03:40.776177 == TX Byte 1 ==
8889 23:03:40.779366 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8890 23:03:40.782665 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8891 23:03:40.782764 ==
8892 23:03:40.786378 Dram Type= 6, Freq= 0, CH_1, rank 1
8893 23:03:40.792538 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8894 23:03:40.792624 ==
8895 23:03:40.805375
8896 23:03:40.808534 TX Vref early break, caculate TX vref
8897 23:03:40.812102 TX Vref=16, minBit 11, minWin=22, winSum=379
8898 23:03:40.815471 TX Vref=18, minBit 5, minWin=23, winSum=391
8899 23:03:40.818927 TX Vref=20, minBit 8, minWin=24, winSum=399
8900 23:03:40.822118 TX Vref=22, minBit 8, minWin=24, winSum=409
8901 23:03:40.825259 TX Vref=24, minBit 0, minWin=25, winSum=413
8902 23:03:40.832592 TX Vref=26, minBit 0, minWin=25, winSum=422
8903 23:03:40.835059 TX Vref=28, minBit 5, minWin=25, winSum=428
8904 23:03:40.838666 TX Vref=30, minBit 5, minWin=25, winSum=428
8905 23:03:40.841943 TX Vref=32, minBit 0, minWin=25, winSum=419
8906 23:03:40.845467 TX Vref=34, minBit 5, minWin=24, winSum=410
8907 23:03:40.848393 TX Vref=36, minBit 0, minWin=24, winSum=401
8908 23:03:40.855535 [TxChooseVref] Worse bit 5, Min win 25, Win sum 428, Final Vref 28
8909 23:03:40.855627
8910 23:03:40.858820 Final TX Range 0 Vref 28
8911 23:03:40.858929
8912 23:03:40.859021 ==
8913 23:03:40.861840 Dram Type= 6, Freq= 0, CH_1, rank 1
8914 23:03:40.865445 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8915 23:03:40.865522 ==
8916 23:03:40.865603
8917 23:03:40.865665
8918 23:03:40.868368 TX Vref Scan disable
8919 23:03:40.875276 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8920 23:03:40.875356 == TX Byte 0 ==
8921 23:03:40.878817 u2DelayCellOfst[0]=14 cells (4 PI)
8922 23:03:40.882059 u2DelayCellOfst[1]=10 cells (3 PI)
8923 23:03:40.885476 u2DelayCellOfst[2]=0 cells (0 PI)
8924 23:03:40.888664 u2DelayCellOfst[3]=7 cells (2 PI)
8925 23:03:40.892390 u2DelayCellOfst[4]=10 cells (3 PI)
8926 23:03:40.895449 u2DelayCellOfst[5]=21 cells (6 PI)
8927 23:03:40.899067 u2DelayCellOfst[6]=17 cells (5 PI)
8928 23:03:40.902257 u2DelayCellOfst[7]=3 cells (1 PI)
8929 23:03:40.905380 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8930 23:03:40.909067 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8931 23:03:40.912059 == TX Byte 1 ==
8932 23:03:40.912142 u2DelayCellOfst[8]=0 cells (0 PI)
8933 23:03:40.915512 u2DelayCellOfst[9]=7 cells (2 PI)
8934 23:03:40.918970 u2DelayCellOfst[10]=14 cells (4 PI)
8935 23:03:40.921887 u2DelayCellOfst[11]=7 cells (2 PI)
8936 23:03:40.925223 u2DelayCellOfst[12]=17 cells (5 PI)
8937 23:03:40.928725 u2DelayCellOfst[13]=17 cells (5 PI)
8938 23:03:40.932057 u2DelayCellOfst[14]=21 cells (6 PI)
8939 23:03:40.935221 u2DelayCellOfst[15]=17 cells (5 PI)
8940 23:03:40.938738 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8941 23:03:40.945439 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8942 23:03:40.945522 DramC Write-DBI on
8943 23:03:40.945588 ==
8944 23:03:40.948820 Dram Type= 6, Freq= 0, CH_1, rank 1
8945 23:03:40.952489 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8946 23:03:40.952587 ==
8947 23:03:40.955652
8948 23:03:40.955748
8949 23:03:40.955814 TX Vref Scan disable
8950 23:03:40.958815 == TX Byte 0 ==
8951 23:03:40.962063 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8952 23:03:40.965418 == TX Byte 1 ==
8953 23:03:40.968424 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8954 23:03:40.968516 DramC Write-DBI off
8955 23:03:40.971786
8956 23:03:40.971861 [DATLAT]
8957 23:03:40.971924 Freq=1600, CH1 RK1
8958 23:03:40.971984
8959 23:03:40.975197 DATLAT Default: 0xf
8960 23:03:40.975284 0, 0xFFFF, sum = 0
8961 23:03:40.978611 1, 0xFFFF, sum = 0
8962 23:03:40.978694 2, 0xFFFF, sum = 0
8963 23:03:40.981801 3, 0xFFFF, sum = 0
8964 23:03:40.981878 4, 0xFFFF, sum = 0
8965 23:03:40.985598 5, 0xFFFF, sum = 0
8966 23:03:40.985676 6, 0xFFFF, sum = 0
8967 23:03:40.988689 7, 0xFFFF, sum = 0
8968 23:03:40.991838 8, 0xFFFF, sum = 0
8969 23:03:40.991919 9, 0xFFFF, sum = 0
8970 23:03:40.995513 10, 0xFFFF, sum = 0
8971 23:03:40.995604 11, 0xFFFF, sum = 0
8972 23:03:40.999076 12, 0xFFFF, sum = 0
8973 23:03:40.999150 13, 0xFFFF, sum = 0
8974 23:03:41.002189 14, 0x0, sum = 1
8975 23:03:41.002263 15, 0x0, sum = 2
8976 23:03:41.005313 16, 0x0, sum = 3
8977 23:03:41.005402 17, 0x0, sum = 4
8978 23:03:41.005465 best_step = 15
8979 23:03:41.008847
8980 23:03:41.008942 ==
8981 23:03:41.012135 Dram Type= 6, Freq= 0, CH_1, rank 1
8982 23:03:41.015398 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8983 23:03:41.015496 ==
8984 23:03:41.015579 RX Vref Scan: 0
8985 23:03:41.015690
8986 23:03:41.018535 RX Vref 0 -> 0, step: 1
8987 23:03:41.018633
8988 23:03:41.022201 RX Delay 11 -> 252, step: 4
8989 23:03:41.025459 iDelay=195, Bit 0, Center 132 (83 ~ 182) 100
8990 23:03:41.032498 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
8991 23:03:41.035185 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
8992 23:03:41.038605 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
8993 23:03:41.042006 iDelay=195, Bit 4, Center 128 (75 ~ 182) 108
8994 23:03:41.045614 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
8995 23:03:41.048731 iDelay=195, Bit 6, Center 138 (87 ~ 190) 104
8996 23:03:41.055140 iDelay=195, Bit 7, Center 124 (71 ~ 178) 108
8997 23:03:41.058548 iDelay=195, Bit 8, Center 112 (55 ~ 170) 116
8998 23:03:41.061602 iDelay=195, Bit 9, Center 114 (59 ~ 170) 112
8999 23:03:41.064932 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9000 23:03:41.068624 iDelay=195, Bit 11, Center 118 (67 ~ 170) 104
9001 23:03:41.075098 iDelay=195, Bit 12, Center 134 (83 ~ 186) 104
9002 23:03:41.078311 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
9003 23:03:41.082072 iDelay=195, Bit 14, Center 134 (83 ~ 186) 104
9004 23:03:41.085507 iDelay=195, Bit 15, Center 134 (83 ~ 186) 104
9005 23:03:41.085609 ==
9006 23:03:41.088498 Dram Type= 6, Freq= 0, CH_1, rank 1
9007 23:03:41.095281 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9008 23:03:41.095366 ==
9009 23:03:41.095432 DQS Delay:
9010 23:03:41.098794 DQS0 = 0, DQS1 = 0
9011 23:03:41.098873 DQM Delay:
9012 23:03:41.098937 DQM0 = 129, DQM1 = 126
9013 23:03:41.101940 DQ Delay:
9014 23:03:41.105585 DQ0 =132, DQ1 =124, DQ2 =118, DQ3 =126
9015 23:03:41.108538 DQ4 =128, DQ5 =144, DQ6 =138, DQ7 =124
9016 23:03:41.111710 DQ8 =112, DQ9 =114, DQ10 =128, DQ11 =118
9017 23:03:41.115268 DQ12 =134, DQ13 =136, DQ14 =134, DQ15 =134
9018 23:03:41.115351
9019 23:03:41.115422
9020 23:03:41.115484
9021 23:03:41.118908 [DramC_TX_OE_Calibration] TA2
9022 23:03:41.122216 Original DQ_B0 (3 6) =30, OEN = 27
9023 23:03:41.125051 Original DQ_B1 (3 6) =30, OEN = 27
9024 23:03:41.128522 24, 0x0, End_B0=24 End_B1=24
9025 23:03:41.128597 25, 0x0, End_B0=25 End_B1=25
9026 23:03:41.132207 26, 0x0, End_B0=26 End_B1=26
9027 23:03:41.135346 27, 0x0, End_B0=27 End_B1=27
9028 23:03:41.139165 28, 0x0, End_B0=28 End_B1=28
9029 23:03:41.142210 29, 0x0, End_B0=29 End_B1=29
9030 23:03:41.142287 30, 0x0, End_B0=30 End_B1=30
9031 23:03:41.145135 31, 0x4141, End_B0=30 End_B1=30
9032 23:03:41.148805 Byte0 end_step=30 best_step=27
9033 23:03:41.152290 Byte1 end_step=30 best_step=27
9034 23:03:41.155750 Byte0 TX OE(2T, 0.5T) = (3, 3)
9035 23:03:41.155823 Byte1 TX OE(2T, 0.5T) = (3, 3)
9036 23:03:41.159067
9037 23:03:41.159139
9038 23:03:41.165486 [DQSOSCAuto] RK1, (LSB)MR18= 0xe14, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 402 ps
9039 23:03:41.168922 CH1 RK1: MR19=303, MR18=E14
9040 23:03:41.175452 CH1_RK1: MR19=0x303, MR18=0xE14, DQSOSC=399, MR23=63, INC=23, DEC=15
9041 23:03:41.175532 [RxdqsGatingPostProcess] freq 1600
9042 23:03:41.182259 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9043 23:03:41.185809 best DQS0 dly(2T, 0.5T) = (1, 1)
9044 23:03:41.188856 best DQS1 dly(2T, 0.5T) = (1, 1)
9045 23:03:41.192062 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9046 23:03:41.195525 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9047 23:03:41.198826 best DQS0 dly(2T, 0.5T) = (1, 1)
9048 23:03:41.201906 best DQS1 dly(2T, 0.5T) = (1, 1)
9049 23:03:41.205507 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9050 23:03:41.205585 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9051 23:03:41.208923 Pre-setting of DQS Precalculation
9052 23:03:41.215550 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9053 23:03:41.222062 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9054 23:03:41.229019 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9055 23:03:41.229133
9056 23:03:41.229228
9057 23:03:41.232275 [Calibration Summary] 3200 Mbps
9058 23:03:41.235528 CH 0, Rank 0
9059 23:03:41.235629 SW Impedance : PASS
9060 23:03:41.239063 DUTY Scan : NO K
9061 23:03:41.239165 ZQ Calibration : PASS
9062 23:03:41.242028 Jitter Meter : NO K
9063 23:03:41.246087 CBT Training : PASS
9064 23:03:41.246163 Write leveling : PASS
9065 23:03:41.248606 RX DQS gating : PASS
9066 23:03:41.252095 RX DQ/DQS(RDDQC) : PASS
9067 23:03:41.252168 TX DQ/DQS : PASS
9068 23:03:41.255482 RX DATLAT : PASS
9069 23:03:41.259047 RX DQ/DQS(Engine): PASS
9070 23:03:41.259120 TX OE : PASS
9071 23:03:41.262191 All Pass.
9072 23:03:41.262265
9073 23:03:41.262326 CH 0, Rank 1
9074 23:03:41.265575 SW Impedance : PASS
9075 23:03:41.265650 DUTY Scan : NO K
9076 23:03:41.268667 ZQ Calibration : PASS
9077 23:03:41.272084 Jitter Meter : NO K
9078 23:03:41.272161 CBT Training : PASS
9079 23:03:41.276221 Write leveling : PASS
9080 23:03:41.276312 RX DQS gating : PASS
9081 23:03:41.279192 RX DQ/DQS(RDDQC) : PASS
9082 23:03:41.282614 TX DQ/DQS : PASS
9083 23:03:41.282694 RX DATLAT : PASS
9084 23:03:41.285590 RX DQ/DQS(Engine): PASS
9085 23:03:41.289840 TX OE : PASS
9086 23:03:41.289949 All Pass.
9087 23:03:41.290044
9088 23:03:41.290139 CH 1, Rank 0
9089 23:03:41.292358 SW Impedance : PASS
9090 23:03:41.295869 DUTY Scan : NO K
9091 23:03:41.295943 ZQ Calibration : PASS
9092 23:03:41.299284 Jitter Meter : NO K
9093 23:03:41.302276 CBT Training : PASS
9094 23:03:41.302348 Write leveling : PASS
9095 23:03:41.305649 RX DQS gating : PASS
9096 23:03:41.309283 RX DQ/DQS(RDDQC) : PASS
9097 23:03:41.309366 TX DQ/DQS : PASS
9098 23:03:41.312886 RX DATLAT : PASS
9099 23:03:41.312960 RX DQ/DQS(Engine): PASS
9100 23:03:41.315762 TX OE : PASS
9101 23:03:41.315840 All Pass.
9102 23:03:41.315904
9103 23:03:41.319239 CH 1, Rank 1
9104 23:03:41.319338 SW Impedance : PASS
9105 23:03:41.322547 DUTY Scan : NO K
9106 23:03:41.326124 ZQ Calibration : PASS
9107 23:03:41.326227 Jitter Meter : NO K
9108 23:03:41.329812 CBT Training : PASS
9109 23:03:41.332775 Write leveling : PASS
9110 23:03:41.332876 RX DQS gating : PASS
9111 23:03:41.336252 RX DQ/DQS(RDDQC) : PASS
9112 23:03:41.339592 TX DQ/DQS : PASS
9113 23:03:41.339692 RX DATLAT : PASS
9114 23:03:41.342459 RX DQ/DQS(Engine): PASS
9115 23:03:41.346167 TX OE : PASS
9116 23:03:41.346243 All Pass.
9117 23:03:41.346318
9118 23:03:41.346384 DramC Write-DBI on
9119 23:03:41.349441 PER_BANK_REFRESH: Hybrid Mode
9120 23:03:41.353265 TX_TRACKING: ON
9121 23:03:41.359177 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9122 23:03:41.369466 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9123 23:03:41.376286 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9124 23:03:41.379843 [FAST_K] Save calibration result to emmc
9125 23:03:41.382794 sync common calibartion params.
9126 23:03:41.382903 sync cbt_mode0:1, 1:1
9127 23:03:41.386793 dram_init: ddr_geometry: 2
9128 23:03:41.389869 dram_init: ddr_geometry: 2
9129 23:03:41.389971 dram_init: ddr_geometry: 2
9130 23:03:41.393286 0:dram_rank_size:100000000
9131 23:03:41.396410 1:dram_rank_size:100000000
9132 23:03:41.402892 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9133 23:03:41.402973 DFS_SHUFFLE_HW_MODE: ON
9134 23:03:41.406217 dramc_set_vcore_voltage set vcore to 725000
9135 23:03:41.409626 Read voltage for 1600, 0
9136 23:03:41.409726 Vio18 = 0
9137 23:03:41.412998 Vcore = 725000
9138 23:03:41.413072 Vdram = 0
9139 23:03:41.413135 Vddq = 0
9140 23:03:41.416438 Vmddr = 0
9141 23:03:41.416512 switch to 3200 Mbps bootup
9142 23:03:41.419811 [DramcRunTimeConfig]
9143 23:03:41.419908 PHYPLL
9144 23:03:41.423156 DPM_CONTROL_AFTERK: ON
9145 23:03:41.423236 PER_BANK_REFRESH: ON
9146 23:03:41.426193 REFRESH_OVERHEAD_REDUCTION: ON
9147 23:03:41.429749 CMD_PICG_NEW_MODE: OFF
9148 23:03:41.429831 XRTWTW_NEW_MODE: ON
9149 23:03:41.433224 XRTRTR_NEW_MODE: ON
9150 23:03:41.433306 TX_TRACKING: ON
9151 23:03:41.436386 RDSEL_TRACKING: OFF
9152 23:03:41.439561 DQS Precalculation for DVFS: ON
9153 23:03:41.439661 RX_TRACKING: OFF
9154 23:03:41.442967 HW_GATING DBG: ON
9155 23:03:41.443045 ZQCS_ENABLE_LP4: ON
9156 23:03:41.446220 RX_PICG_NEW_MODE: ON
9157 23:03:41.446297 TX_PICG_NEW_MODE: ON
9158 23:03:41.449930 ENABLE_RX_DCM_DPHY: ON
9159 23:03:41.452863 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9160 23:03:41.456590 DUMMY_READ_FOR_TRACKING: OFF
9161 23:03:41.456666 !!! SPM_CONTROL_AFTERK: OFF
9162 23:03:41.459987 !!! SPM could not control APHY
9163 23:03:41.462988 IMPEDANCE_TRACKING: ON
9164 23:03:41.463064 TEMP_SENSOR: ON
9165 23:03:41.466582 HW_SAVE_FOR_SR: OFF
9166 23:03:41.470135 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9167 23:03:41.472952 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9168 23:03:41.473035 Read ODT Tracking: ON
9169 23:03:41.476338 Refresh Rate DeBounce: ON
9170 23:03:41.480165 DFS_NO_QUEUE_FLUSH: ON
9171 23:03:41.483288 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9172 23:03:41.483370 ENABLE_DFS_RUNTIME_MRW: OFF
9173 23:03:41.486371 DDR_RESERVE_NEW_MODE: ON
9174 23:03:41.489877 MR_CBT_SWITCH_FREQ: ON
9175 23:03:41.489965 =========================
9176 23:03:41.509847 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9177 23:03:41.513047 dram_init: ddr_geometry: 2
9178 23:03:41.531573 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9179 23:03:41.534871 dram_init: dram init end (result: 0)
9180 23:03:41.541368 DRAM-K: Full calibration passed in 24588 msecs
9181 23:03:41.544711 MRC: failed to locate region type 0.
9182 23:03:41.544796 DRAM rank0 size:0x100000000,
9183 23:03:41.548195 DRAM rank1 size=0x100000000
9184 23:03:41.558174 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9185 23:03:41.564977 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9186 23:03:41.571313 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9187 23:03:41.578102 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9188 23:03:41.581345 DRAM rank0 size:0x100000000,
9189 23:03:41.584772 DRAM rank1 size=0x100000000
9190 23:03:41.584852 CBMEM:
9191 23:03:41.588114 IMD: root @ 0xfffff000 254 entries.
9192 23:03:41.592204 IMD: root @ 0xffffec00 62 entries.
9193 23:03:41.595146 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9194 23:03:41.598367 WARNING: RO_VPD is uninitialized or empty.
9195 23:03:41.602416 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9196 23:03:41.611929 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9197 23:03:41.624218 read SPI 0x42894 0xe01e: 6227 us, 9213 KB/s, 73.704 Mbps
9198 23:03:41.635533 BS: romstage times (exec / console): total (unknown) / 24091 ms
9199 23:03:41.635648
9200 23:03:41.635749
9201 23:03:41.645751 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9202 23:03:41.649006 ARM64: Exception handlers installed.
9203 23:03:41.652022 ARM64: Testing exception
9204 23:03:41.655317 ARM64: Done test exception
9205 23:03:41.655410 Enumerating buses...
9206 23:03:41.658790 Show all devs... Before device enumeration.
9207 23:03:41.662275 Root Device: enabled 1
9208 23:03:41.665673 CPU_CLUSTER: 0: enabled 1
9209 23:03:41.665792 CPU: 00: enabled 1
9210 23:03:41.669033 Compare with tree...
9211 23:03:41.669116 Root Device: enabled 1
9212 23:03:41.672107 CPU_CLUSTER: 0: enabled 1
9213 23:03:41.675688 CPU: 00: enabled 1
9214 23:03:41.675769 Root Device scanning...
9215 23:03:41.678769 scan_static_bus for Root Device
9216 23:03:41.682182 CPU_CLUSTER: 0 enabled
9217 23:03:41.685654 scan_static_bus for Root Device done
9218 23:03:41.689262 scan_bus: bus Root Device finished in 8 msecs
9219 23:03:41.689339 done
9220 23:03:41.695842 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9221 23:03:41.699256 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9222 23:03:41.705772 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9223 23:03:41.709372 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9224 23:03:41.712203 Allocating resources...
9225 23:03:41.712292 Reading resources...
9226 23:03:41.719142 Root Device read_resources bus 0 link: 0
9227 23:03:41.719226 DRAM rank0 size:0x100000000,
9228 23:03:41.722344 DRAM rank1 size=0x100000000
9229 23:03:41.725542 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9230 23:03:41.729194 CPU: 00 missing read_resources
9231 23:03:41.732300 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9232 23:03:41.739308 Root Device read_resources bus 0 link: 0 done
9233 23:03:41.739389 Done reading resources.
9234 23:03:41.745701 Show resources in subtree (Root Device)...After reading.
9235 23:03:41.749298 Root Device child on link 0 CPU_CLUSTER: 0
9236 23:03:41.752593 CPU_CLUSTER: 0 child on link 0 CPU: 00
9237 23:03:41.762331 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9238 23:03:41.762418 CPU: 00
9239 23:03:41.765909 Root Device assign_resources, bus 0 link: 0
9240 23:03:41.769171 CPU_CLUSTER: 0 missing set_resources
9241 23:03:41.772186 Root Device assign_resources, bus 0 link: 0 done
9242 23:03:41.775808 Done setting resources.
9243 23:03:41.782584 Show resources in subtree (Root Device)...After assigning values.
9244 23:03:41.785663 Root Device child on link 0 CPU_CLUSTER: 0
9245 23:03:41.789062 CPU_CLUSTER: 0 child on link 0 CPU: 00
9246 23:03:41.798805 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9247 23:03:41.798906 CPU: 00
9248 23:03:41.802526 Done allocating resources.
9249 23:03:41.805521 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9250 23:03:41.808748 Enabling resources...
9251 23:03:41.808834 done.
9252 23:03:41.812271 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9253 23:03:41.815650 Initializing devices...
9254 23:03:41.815757 Root Device init
9255 23:03:41.819025 init hardware done!
9256 23:03:41.822428 0x00000018: ctrlr->caps
9257 23:03:41.822523 52.000 MHz: ctrlr->f_max
9258 23:03:41.825886 0.400 MHz: ctrlr->f_min
9259 23:03:41.829316 0x40ff8080: ctrlr->voltages
9260 23:03:41.829399 sclk: 390625
9261 23:03:41.832340 Bus Width = 1
9262 23:03:41.832425 sclk: 390625
9263 23:03:41.832491 Bus Width = 1
9264 23:03:41.835736 Early init status = 3
9265 23:03:41.838765 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9266 23:03:41.843104 in-header: 03 fc 00 00 01 00 00 00
9267 23:03:41.846455 in-data: 00
9268 23:03:41.849634 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9269 23:03:41.854445 in-header: 03 fd 00 00 00 00 00 00
9270 23:03:41.857800 in-data:
9271 23:03:41.861593 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9272 23:03:41.864600 in-header: 03 fc 00 00 01 00 00 00
9273 23:03:41.867602 in-data: 00
9274 23:03:41.871055 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9275 23:03:41.875493 in-header: 03 fd 00 00 00 00 00 00
9276 23:03:41.878902 in-data:
9277 23:03:41.882584 [SSUSB] Setting up USB HOST controller...
9278 23:03:41.885973 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9279 23:03:41.888770 [SSUSB] phy power-on done.
9280 23:03:41.892118 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9281 23:03:41.898564 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9282 23:03:41.902181 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9283 23:03:41.908868 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9284 23:03:41.915539 read SPI 0x50eb0 0x2ad3: 1173 us, 9346 KB/s, 74.768 Mbps
9285 23:03:41.922679 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9286 23:03:41.929361 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9287 23:03:41.935595 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9288 23:03:41.935671 SPM: binary array size = 0x9dc
9289 23:03:41.942653 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9290 23:03:41.949354 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9291 23:03:41.955629 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9292 23:03:41.959144 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9293 23:03:41.962655 configure_display: Starting display init
9294 23:03:41.998730 anx7625_power_on_init: Init interface.
9295 23:03:42.002294 anx7625_disable_pd_protocol: Disabled PD feature.
9296 23:03:42.005406 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9297 23:03:42.033429 anx7625_start_dp_work: Secure OCM version=00
9298 23:03:42.036443 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9299 23:03:42.051330 sp_tx_get_edid_block: EDID Block = 1
9300 23:03:42.154219 Extracted contents:
9301 23:03:42.157567 header: 00 ff ff ff ff ff ff 00
9302 23:03:42.160337 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9303 23:03:42.163761 version: 01 04
9304 23:03:42.167262 basic params: 95 1f 11 78 0a
9305 23:03:42.170511 chroma info: 76 90 94 55 54 90 27 21 50 54
9306 23:03:42.173719 established: 00 00 00
9307 23:03:42.180773 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9308 23:03:42.184030 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9309 23:03:42.190890 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9310 23:03:42.197027 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9311 23:03:42.203920 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9312 23:03:42.207479 extensions: 00
9313 23:03:42.207565 checksum: fb
9314 23:03:42.207632
9315 23:03:42.210918 Manufacturer: IVO Model 57d Serial Number 0
9316 23:03:42.213599 Made week 0 of 2020
9317 23:03:42.213699 EDID version: 1.4
9318 23:03:42.217402 Digital display
9319 23:03:42.220419 6 bits per primary color channel
9320 23:03:42.220495 DisplayPort interface
9321 23:03:42.223686 Maximum image size: 31 cm x 17 cm
9322 23:03:42.223787 Gamma: 220%
9323 23:03:42.227123 Check DPMS levels
9324 23:03:42.230637 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9325 23:03:42.234498 First detailed timing is preferred timing
9326 23:03:42.237118 Established timings supported:
9327 23:03:42.240646 Standard timings supported:
9328 23:03:42.240731 Detailed timings
9329 23:03:42.247391 Hex of detail: 383680a07038204018303c0035ae10000019
9330 23:03:42.250734 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9331 23:03:42.254241 0780 0798 07c8 0820 hborder 0
9332 23:03:42.260470 0438 043b 0447 0458 vborder 0
9333 23:03:42.260556 -hsync -vsync
9334 23:03:42.264062 Did detailed timing
9335 23:03:42.267677 Hex of detail: 000000000000000000000000000000000000
9336 23:03:42.270705 Manufacturer-specified data, tag 0
9337 23:03:42.277257 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9338 23:03:42.277332 ASCII string: InfoVision
9339 23:03:42.283856 Hex of detail: 000000fe00523134304e574635205248200a
9340 23:03:42.283937 ASCII string: R140NWF5 RH
9341 23:03:42.287242 Checksum
9342 23:03:42.287332 Checksum: 0xfb (valid)
9343 23:03:42.294484 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9344 23:03:42.294559 DSI data_rate: 832800000 bps
9345 23:03:42.301482 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9346 23:03:42.304619 anx7625_parse_edid: pixelclock(138800).
9347 23:03:42.308273 hactive(1920), hsync(48), hfp(24), hbp(88)
9348 23:03:42.311343 vactive(1080), vsync(12), vfp(3), vbp(17)
9349 23:03:42.315097 anx7625_dsi_config: config dsi.
9350 23:03:42.322055 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9351 23:03:42.335811 anx7625_dsi_config: success to config DSI
9352 23:03:42.339242 anx7625_dp_start: MIPI phy setup OK.
9353 23:03:42.342581 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9354 23:03:42.346178 mtk_ddp_mode_set invalid vrefresh 60
9355 23:03:42.349954 main_disp_path_setup
9356 23:03:42.350076 ovl_layer_smi_id_en
9357 23:03:42.352489 ovl_layer_smi_id_en
9358 23:03:42.352605 ccorr_config
9359 23:03:42.352732 aal_config
9360 23:03:42.355955 gamma_config
9361 23:03:42.356057 postmask_config
9362 23:03:42.359442 dither_config
9363 23:03:42.362320 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9364 23:03:42.369515 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9365 23:03:42.372853 Root Device init finished in 551 msecs
9366 23:03:42.372968 CPU_CLUSTER: 0 init
9367 23:03:42.382427 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9368 23:03:42.386295 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9369 23:03:42.389186 APU_MBOX 0x190000b0 = 0x10001
9370 23:03:42.392556 APU_MBOX 0x190001b0 = 0x10001
9371 23:03:42.396172 APU_MBOX 0x190005b0 = 0x10001
9372 23:03:42.399816 APU_MBOX 0x190006b0 = 0x10001
9373 23:03:42.402495 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9374 23:03:42.415127 read SPI 0x539f4 0xe237: 6250 us, 9265 KB/s, 74.120 Mbps
9375 23:03:42.427310 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9376 23:03:42.433698 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9377 23:03:42.445528 read SPI 0x61c74 0xe8ef: 6412 us, 9299 KB/s, 74.392 Mbps
9378 23:03:42.455030 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9379 23:03:42.458384 CPU_CLUSTER: 0 init finished in 81 msecs
9380 23:03:42.461582 Devices initialized
9381 23:03:42.464581 Show all devs... After init.
9382 23:03:42.464662 Root Device: enabled 1
9383 23:03:42.468049 CPU_CLUSTER: 0: enabled 1
9384 23:03:42.471442 CPU: 00: enabled 1
9385 23:03:42.474656 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9386 23:03:42.478060 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9387 23:03:42.481642 ELOG: NV offset 0x57f000 size 0x1000
9388 23:03:42.488385 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9389 23:03:42.494985 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9390 23:03:42.498469 ELOG: Event(17) added with size 13 at 2023-12-01 23:03:45 UTC
9391 23:03:42.501336 out: cmd=0x121: 03 db 21 01 00 00 00 00
9392 23:03:42.504840 in-header: 03 d1 00 00 2c 00 00 00
9393 23:03:42.518507 in-data: 8e 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9394 23:03:42.525272 ELOG: Event(A1) added with size 10 at 2023-12-01 23:03:45 UTC
9395 23:03:42.532079 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9396 23:03:42.538314 ELOG: Event(A0) added with size 9 at 2023-12-01 23:03:45 UTC
9397 23:03:42.542038 elog_add_boot_reason: Logged dev mode boot
9398 23:03:42.544968 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9399 23:03:42.548351 Finalize devices...
9400 23:03:42.548494 Devices finalized
9401 23:03:42.555195 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9402 23:03:42.558355 Writing coreboot table at 0xffe64000
9403 23:03:42.561547 0. 000000000010a000-0000000000113fff: RAMSTAGE
9404 23:03:42.565144 1. 0000000040000000-00000000400fffff: RAM
9405 23:03:42.568438 2. 0000000040100000-000000004032afff: RAMSTAGE
9406 23:03:42.574838 3. 000000004032b000-00000000545fffff: RAM
9407 23:03:42.578461 4. 0000000054600000-000000005465ffff: BL31
9408 23:03:42.581660 5. 0000000054660000-00000000ffe63fff: RAM
9409 23:03:42.588062 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9410 23:03:42.591523 7. 0000000100000000-000000023fffffff: RAM
9411 23:03:42.591675 Passing 5 GPIOs to payload:
9412 23:03:42.598497 NAME | PORT | POLARITY | VALUE
9413 23:03:42.601672 EC in RW | 0x000000aa | low | undefined
9414 23:03:42.608196 EC interrupt | 0x00000005 | low | undefined
9415 23:03:42.611452 TPM interrupt | 0x000000ab | high | undefined
9416 23:03:42.614802 SD card detect | 0x00000011 | high | undefined
9417 23:03:42.621510 speaker enable | 0x00000093 | high | undefined
9418 23:03:42.624991 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9419 23:03:42.628685 in-header: 03 f9 00 00 02 00 00 00
9420 23:03:42.628786 in-data: 02 00
9421 23:03:42.632038 ADC[4]: Raw value=899114 ID=7
9422 23:03:42.634787 ADC[3]: Raw value=213336 ID=1
9423 23:03:42.634918 RAM Code: 0x71
9424 23:03:42.638334 ADC[6]: Raw value=74557 ID=0
9425 23:03:42.641596 ADC[5]: Raw value=212229 ID=1
9426 23:03:42.641695 SKU Code: 0x1
9427 23:03:42.648004 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum e36e
9428 23:03:42.651517 coreboot table: 964 bytes.
9429 23:03:42.654822 IMD ROOT 0. 0xfffff000 0x00001000
9430 23:03:42.658034 IMD SMALL 1. 0xffffe000 0x00001000
9431 23:03:42.661738 RO MCACHE 2. 0xffffc000 0x00001104
9432 23:03:42.664707 CONSOLE 3. 0xfff7c000 0x00080000
9433 23:03:42.668385 FMAP 4. 0xfff7b000 0x00000452
9434 23:03:42.671876 TIME STAMP 5. 0xfff7a000 0x00000910
9435 23:03:42.674787 VBOOT WORK 6. 0xfff66000 0x00014000
9436 23:03:42.678326 RAMOOPS 7. 0xffe66000 0x00100000
9437 23:03:42.681830 COREBOOT 8. 0xffe64000 0x00002000
9438 23:03:42.681934 IMD small region:
9439 23:03:42.685212 IMD ROOT 0. 0xffffec00 0x00000400
9440 23:03:42.688725 VPD 1. 0xffffeb80 0x0000006c
9441 23:03:42.691825 MMC STATUS 2. 0xffffeb60 0x00000004
9442 23:03:42.698461 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9443 23:03:42.698565 Probing TPM: done!
9444 23:03:42.705395 Connected to device vid:did:rid of 1ae0:0028:00
9445 23:03:42.712245 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9446 23:03:42.714971 Initialized TPM device CR50 revision 0
9447 23:03:42.718888 Checking cr50 for pending updates
9448 23:03:42.724624 Reading cr50 TPM mode
9449 23:03:42.733237 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9450 23:03:42.739786 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9451 23:03:42.780172 read SPI 0x3990ec 0x4f1b0: 34859 us, 9295 KB/s, 74.360 Mbps
9452 23:03:42.783345 Checking segment from ROM address 0x40100000
9453 23:03:42.787114 Checking segment from ROM address 0x4010001c
9454 23:03:42.793258 Loading segment from ROM address 0x40100000
9455 23:03:42.793371 code (compression=0)
9456 23:03:42.800310 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9457 23:03:42.810357 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9458 23:03:42.810469 it's not compressed!
9459 23:03:42.817046 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9460 23:03:42.820146 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9461 23:03:42.840290 Loading segment from ROM address 0x4010001c
9462 23:03:42.840403 Entry Point 0x80000000
9463 23:03:42.843849 Loaded segments
9464 23:03:42.847197 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9465 23:03:42.853804 Jumping to boot code at 0x80000000(0xffe64000)
9466 23:03:42.860209 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9467 23:03:42.867214 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9468 23:03:42.875089 read SPI 0x8eb68 0x74a8: 3225 us, 9260 KB/s, 74.080 Mbps
9469 23:03:42.878432 Checking segment from ROM address 0x40100000
9470 23:03:42.881260 Checking segment from ROM address 0x4010001c
9471 23:03:42.888333 Loading segment from ROM address 0x40100000
9472 23:03:42.888442 code (compression=1)
9473 23:03:42.895068 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9474 23:03:42.904735 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9475 23:03:42.904845 using LZMA
9476 23:03:42.913369 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9477 23:03:42.919808 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9478 23:03:42.923488 Loading segment from ROM address 0x4010001c
9479 23:03:42.923593 Entry Point 0x54601000
9480 23:03:42.927125 Loaded segments
9481 23:03:42.929703 NOTICE: MT8192 bl31_setup
9482 23:03:42.936714 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9483 23:03:42.940160 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9484 23:03:42.943642 WARNING: region 0:
9485 23:03:42.946619 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9486 23:03:42.946719 WARNING: region 1:
9487 23:03:42.953557 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9488 23:03:42.957251 WARNING: region 2:
9489 23:03:42.959923 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9490 23:03:42.963330 WARNING: region 3:
9491 23:03:42.967054 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9492 23:03:42.970470 WARNING: region 4:
9493 23:03:42.973409 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9494 23:03:42.976902 WARNING: region 5:
9495 23:03:42.980496 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9496 23:03:42.983868 WARNING: region 6:
9497 23:03:42.987272 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9498 23:03:42.987376 WARNING: region 7:
9499 23:03:42.993977 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9500 23:03:43.000203 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9501 23:03:43.004032 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9502 23:03:43.006883 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9503 23:03:43.010797 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9504 23:03:43.017682 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9505 23:03:43.020970 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9506 23:03:43.027450 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9507 23:03:43.031029 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9508 23:03:43.034282 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9509 23:03:43.040619 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9510 23:03:43.044097 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9511 23:03:43.047864 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9512 23:03:43.053949 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9513 23:03:43.057495 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9514 23:03:43.061231 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9515 23:03:43.067649 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9516 23:03:43.070886 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9517 23:03:43.077667 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9518 23:03:43.081292 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9519 23:03:43.084409 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9520 23:03:43.091259 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9521 23:03:43.094474 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9522 23:03:43.097677 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9523 23:03:43.104766 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9524 23:03:43.107860 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9525 23:03:43.114785 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9526 23:03:43.117814 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9527 23:03:43.121364 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9528 23:03:43.128097 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9529 23:03:43.131675 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9530 23:03:43.137987 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9531 23:03:43.141639 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9532 23:03:43.144505 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9533 23:03:43.147970 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9534 23:03:43.154816 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9535 23:03:43.157764 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9536 23:03:43.161766 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9537 23:03:43.164951 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9538 23:03:43.171585 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9539 23:03:43.174906 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9540 23:03:43.178220 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9541 23:03:43.181572 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9542 23:03:43.188490 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9543 23:03:43.191437 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9544 23:03:43.194773 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9545 23:03:43.198328 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9546 23:03:43.205487 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9547 23:03:43.208677 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9548 23:03:43.211588 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9549 23:03:43.219000 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9550 23:03:43.222054 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9551 23:03:43.225103 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9552 23:03:43.231991 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9553 23:03:43.235115 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9554 23:03:43.242240 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9555 23:03:43.245730 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9556 23:03:43.249094 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9557 23:03:43.255405 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9558 23:03:43.258842 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9559 23:03:43.265727 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9560 23:03:43.269190 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9561 23:03:43.275444 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9562 23:03:43.278749 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9563 23:03:43.285731 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9564 23:03:43.289114 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9565 23:03:43.292256 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9566 23:03:43.299073 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9567 23:03:43.302656 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9568 23:03:43.308963 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9569 23:03:43.312570 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9570 23:03:43.315921 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9571 23:03:43.322360 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9572 23:03:43.325773 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9573 23:03:43.332817 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9574 23:03:43.335741 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9575 23:03:43.342794 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9576 23:03:43.346125 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9577 23:03:43.349552 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9578 23:03:43.356390 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9579 23:03:43.359495 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9580 23:03:43.366260 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9581 23:03:43.369996 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9582 23:03:43.372851 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9583 23:03:43.379761 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9584 23:03:43.383719 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9585 23:03:43.390081 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9586 23:03:43.392960 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9587 23:03:43.399902 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9588 23:03:43.403260 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9589 23:03:43.406835 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9590 23:03:43.412948 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9591 23:03:43.416467 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9592 23:03:43.423304 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9593 23:03:43.426830 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9594 23:03:43.433718 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9595 23:03:43.436930 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9596 23:03:43.439828 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9597 23:03:43.446461 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9598 23:03:43.449807 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9599 23:03:43.453488 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9600 23:03:43.456748 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9601 23:03:43.463555 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9602 23:03:43.466784 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9603 23:03:43.470280 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9604 23:03:43.477040 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9605 23:03:43.480379 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9606 23:03:43.486732 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9607 23:03:43.490673 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9608 23:03:43.493458 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9609 23:03:43.500408 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9610 23:03:43.503788 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9611 23:03:43.509948 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9612 23:03:43.513333 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9613 23:03:43.517135 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9614 23:03:43.523799 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9615 23:03:43.527567 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9616 23:03:43.530465 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9617 23:03:43.537001 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9618 23:03:43.540422 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9619 23:03:43.544095 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9620 23:03:43.547164 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9621 23:03:43.553828 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9622 23:03:43.557741 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9623 23:03:43.561057 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9624 23:03:43.564451 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9625 23:03:43.571083 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9626 23:03:43.574272 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9627 23:03:43.580992 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9628 23:03:43.584290 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9629 23:03:43.587744 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9630 23:03:43.594169 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9631 23:03:43.597889 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9632 23:03:43.601398 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9633 23:03:43.607755 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9634 23:03:43.611090 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9635 23:03:43.617503 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9636 23:03:43.621284 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9637 23:03:43.624293 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9638 23:03:43.631084 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9639 23:03:43.634532 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9640 23:03:43.638141 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9641 23:03:43.644866 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9642 23:03:43.648580 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9643 23:03:43.654968 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9644 23:03:43.658372 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9645 23:03:43.661468 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9646 23:03:43.668194 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9647 23:03:43.671549 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9648 23:03:43.674908 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9649 23:03:43.682107 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9650 23:03:43.685175 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9651 23:03:43.688755 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9652 23:03:43.695203 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9653 23:03:43.698888 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9654 23:03:43.705595 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9655 23:03:43.708737 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9656 23:03:43.711869 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9657 23:03:43.718703 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9658 23:03:43.721960 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9659 23:03:43.728577 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9660 23:03:43.731925 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9661 23:03:43.735414 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9662 23:03:43.742082 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9663 23:03:43.745507 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9664 23:03:43.748970 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9665 23:03:43.755211 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9666 23:03:43.758699 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9667 23:03:43.765136 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9668 23:03:43.768644 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9669 23:03:43.771992 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9670 23:03:43.778728 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9671 23:03:43.782271 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9672 23:03:43.789011 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9673 23:03:43.792129 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9674 23:03:43.795282 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9675 23:03:43.802147 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9676 23:03:43.805792 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9677 23:03:43.808820 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9678 23:03:43.815372 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9679 23:03:43.818643 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9680 23:03:43.825537 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9681 23:03:43.828620 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9682 23:03:43.831977 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9683 23:03:43.838598 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9684 23:03:43.841922 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9685 23:03:43.848932 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9686 23:03:43.852452 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9687 23:03:43.855392 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9688 23:03:43.862086 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9689 23:03:43.865491 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9690 23:03:43.871918 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9691 23:03:43.875671 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9692 23:03:43.878663 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9693 23:03:43.885470 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9694 23:03:43.888915 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9695 23:03:43.895852 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9696 23:03:43.898651 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9697 23:03:43.902133 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9698 23:03:43.908691 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9699 23:03:43.912029 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9700 23:03:43.919385 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9701 23:03:43.922442 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9702 23:03:43.925983 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9703 23:03:43.931966 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9704 23:03:43.935362 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9705 23:03:43.942370 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9706 23:03:43.945599 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9707 23:03:43.948647 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9708 23:03:43.955852 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9709 23:03:43.959292 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9710 23:03:43.966356 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9711 23:03:43.969518 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9712 23:03:43.975516 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9713 23:03:43.979001 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9714 23:03:43.982624 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9715 23:03:43.989269 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9716 23:03:43.992776 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9717 23:03:43.998970 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9718 23:03:44.002132 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9719 23:03:44.005846 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9720 23:03:44.012374 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9721 23:03:44.016125 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9722 23:03:44.022898 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9723 23:03:44.026366 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9724 23:03:44.029266 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9725 23:03:44.035868 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9726 23:03:44.038985 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9727 23:03:44.045906 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9728 23:03:44.048849 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9729 23:03:44.052663 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9730 23:03:44.055926 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9731 23:03:44.062441 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9732 23:03:44.066222 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9733 23:03:44.068860 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9734 23:03:44.075893 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9735 23:03:44.078735 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9736 23:03:44.082315 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9737 23:03:44.088818 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9738 23:03:44.092267 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9739 23:03:44.095686 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9740 23:03:44.102108 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9741 23:03:44.105727 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9742 23:03:44.111997 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9743 23:03:44.115456 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9744 23:03:44.118870 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9745 23:03:44.126051 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9746 23:03:44.128700 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9747 23:03:44.132142 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9748 23:03:44.139037 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9749 23:03:44.142053 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9750 23:03:44.145348 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9751 23:03:44.152385 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9752 23:03:44.156006 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9753 23:03:44.158719 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9754 23:03:44.165711 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9755 23:03:44.168851 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9756 23:03:44.175502 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9757 23:03:44.179159 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9758 23:03:44.182461 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9759 23:03:44.188872 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9760 23:03:44.192079 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9761 23:03:44.195457 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9762 23:03:44.201953 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9763 23:03:44.205624 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9764 23:03:44.208543 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9765 23:03:44.215356 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9766 23:03:44.219021 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9767 23:03:44.225348 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9768 23:03:44.228641 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9769 23:03:44.232499 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9770 23:03:44.235541 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9771 23:03:44.239388 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9772 23:03:44.245869 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9773 23:03:44.249234 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9774 23:03:44.252632 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9775 23:03:44.255425 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9776 23:03:44.262458 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9777 23:03:44.265708 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9778 23:03:44.268873 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9779 23:03:44.272175 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9780 23:03:44.279137 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9781 23:03:44.282302 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9782 23:03:44.285633 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9783 23:03:44.292130 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9784 23:03:44.295464 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9785 23:03:44.302519 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9786 23:03:44.305359 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9787 23:03:44.308840 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9788 23:03:44.315695 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9789 23:03:44.319257 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9790 23:03:44.322205 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9791 23:03:44.329456 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9792 23:03:44.332734 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9793 23:03:44.338842 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9794 23:03:44.342362 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9795 23:03:44.349358 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9796 23:03:44.352594 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9797 23:03:44.355618 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9798 23:03:44.362571 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9799 23:03:44.365673 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9800 23:03:44.372574 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9801 23:03:44.376084 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9802 23:03:44.379256 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9803 23:03:44.385661 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9804 23:03:44.388992 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9805 23:03:44.392429 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9806 23:03:44.399331 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9807 23:03:44.402727 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9808 23:03:44.409330 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9809 23:03:44.412767 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9810 23:03:44.419429 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9811 23:03:44.422427 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9812 23:03:44.425835 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9813 23:03:44.432951 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9814 23:03:44.435962 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9815 23:03:44.439679 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9816 23:03:44.445922 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9817 23:03:44.449337 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9818 23:03:44.456116 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9819 23:03:44.459382 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9820 23:03:44.466101 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9821 23:03:44.469135 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9822 23:03:44.472769 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9823 23:03:44.479538 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9824 23:03:44.482512 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9825 23:03:44.489461 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9826 23:03:44.492420 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9827 23:03:44.496178 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9828 23:03:44.502461 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9829 23:03:44.505723 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9830 23:03:44.512454 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9831 23:03:44.516037 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9832 23:03:44.519410 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9833 23:03:44.525761 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9834 23:03:44.529217 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9835 23:03:44.535977 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9836 23:03:44.539267 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9837 23:03:44.542783 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9838 23:03:44.549252 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9839 23:03:44.552765 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9840 23:03:44.559842 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9841 23:03:44.562549 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9842 23:03:44.565879 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9843 23:03:44.572838 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9844 23:03:44.575691 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9845 23:03:44.582683 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9846 23:03:44.586216 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9847 23:03:44.589113 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9848 23:03:44.595975 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9849 23:03:44.599551 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9850 23:03:44.606114 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9851 23:03:44.609772 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9852 23:03:44.616112 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9853 23:03:44.619329 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9854 23:03:44.622516 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9855 23:03:44.629616 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9856 23:03:44.632534 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9857 23:03:44.639107 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9858 23:03:44.642837 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9859 23:03:44.646143 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9860 23:03:44.652709 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9861 23:03:44.656232 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9862 23:03:44.662429 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9863 23:03:44.666049 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9864 23:03:44.672459 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9865 23:03:44.675763 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9866 23:03:44.679344 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9867 23:03:44.686453 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9868 23:03:44.689492 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9869 23:03:44.696208 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9870 23:03:44.699218 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9871 23:03:44.703142 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9872 23:03:44.709195 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9873 23:03:44.712782 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9874 23:03:44.719371 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9875 23:03:44.723023 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9876 23:03:44.729758 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9877 23:03:44.732631 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9878 23:03:44.736173 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9879 23:03:44.742653 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9880 23:03:44.746148 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9881 23:03:44.752912 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9882 23:03:44.756455 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9883 23:03:44.763010 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9884 23:03:44.766148 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9885 23:03:44.769558 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9886 23:03:44.776433 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9887 23:03:44.779631 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9888 23:03:44.786481 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9889 23:03:44.789724 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9890 23:03:44.796442 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9891 23:03:44.799634 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9892 23:03:44.803214 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9893 23:03:44.809643 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9894 23:03:44.812924 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9895 23:03:44.820018 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9896 23:03:44.823081 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9897 23:03:44.829806 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9898 23:03:44.832812 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9899 23:03:44.836400 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9900 23:03:44.842790 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9901 23:03:44.846536 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9902 23:03:44.849764 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9903 23:03:44.856674 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9904 23:03:44.859527 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9905 23:03:44.866388 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9906 23:03:44.869508 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9907 23:03:44.876393 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9908 23:03:44.880331 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9909 23:03:44.886340 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9910 23:03:44.890049 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9911 23:03:44.896272 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9912 23:03:44.899596 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9913 23:03:44.906184 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9914 23:03:44.910003 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9915 23:03:44.916319 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9916 23:03:44.919974 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9917 23:03:44.926516 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9918 23:03:44.929617 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9919 23:03:44.933043 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9920 23:03:44.939659 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9921 23:03:44.942769 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9922 23:03:44.949958 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9923 23:03:44.953323 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9924 23:03:44.959728 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9925 23:03:44.963078 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9926 23:03:44.969545 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9927 23:03:44.972963 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9928 23:03:44.979384 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9929 23:03:44.982871 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9930 23:03:44.989381 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9931 23:03:44.992791 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9932 23:03:44.999369 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9933 23:03:45.006042 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9934 23:03:45.009294 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9935 23:03:45.009398 INFO: [APUAPC] vio 0
9936 23:03:45.016781 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9937 23:03:45.019724 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9938 23:03:45.023278 INFO: [APUAPC] D0_APC_0: 0x400510
9939 23:03:45.026647 INFO: [APUAPC] D0_APC_1: 0x0
9940 23:03:45.030223 INFO: [APUAPC] D0_APC_2: 0x1540
9941 23:03:45.033307 INFO: [APUAPC] D0_APC_3: 0x0
9942 23:03:45.036518 INFO: [APUAPC] D1_APC_0: 0xffffffff
9943 23:03:45.040034 INFO: [APUAPC] D1_APC_1: 0xffffffff
9944 23:03:45.043626 INFO: [APUAPC] D1_APC_2: 0x3fffff
9945 23:03:45.046720 INFO: [APUAPC] D1_APC_3: 0x0
9946 23:03:45.050452 INFO: [APUAPC] D2_APC_0: 0xffffffff
9947 23:03:45.053204 INFO: [APUAPC] D2_APC_1: 0xffffffff
9948 23:03:45.056781 INFO: [APUAPC] D2_APC_2: 0x3fffff
9949 23:03:45.060107 INFO: [APUAPC] D2_APC_3: 0x0
9950 23:03:45.063404 INFO: [APUAPC] D3_APC_0: 0xffffffff
9951 23:03:45.066801 INFO: [APUAPC] D3_APC_1: 0xffffffff
9952 23:03:45.069657 INFO: [APUAPC] D3_APC_2: 0x3fffff
9953 23:03:45.069766 INFO: [APUAPC] D3_APC_3: 0x0
9954 23:03:45.073226 INFO: [APUAPC] D4_APC_0: 0xffffffff
9955 23:03:45.079741 INFO: [APUAPC] D4_APC_1: 0xffffffff
9956 23:03:45.083535 INFO: [APUAPC] D4_APC_2: 0x3fffff
9957 23:03:45.083648 INFO: [APUAPC] D4_APC_3: 0x0
9958 23:03:45.086328 INFO: [APUAPC] D5_APC_0: 0xffffffff
9959 23:03:45.089808 INFO: [APUAPC] D5_APC_1: 0xffffffff
9960 23:03:45.093183 INFO: [APUAPC] D5_APC_2: 0x3fffff
9961 23:03:45.096666 INFO: [APUAPC] D5_APC_3: 0x0
9962 23:03:45.100240 INFO: [APUAPC] D6_APC_0: 0xffffffff
9963 23:03:45.103777 INFO: [APUAPC] D6_APC_1: 0xffffffff
9964 23:03:45.106460 INFO: [APUAPC] D6_APC_2: 0x3fffff
9965 23:03:45.110247 INFO: [APUAPC] D6_APC_3: 0x0
9966 23:03:45.113019 INFO: [APUAPC] D7_APC_0: 0xffffffff
9967 23:03:45.116837 INFO: [APUAPC] D7_APC_1: 0xffffffff
9968 23:03:45.120057 INFO: [APUAPC] D7_APC_2: 0x3fffff
9969 23:03:45.123479 INFO: [APUAPC] D7_APC_3: 0x0
9970 23:03:45.126662 INFO: [APUAPC] D8_APC_0: 0xffffffff
9971 23:03:45.130050 INFO: [APUAPC] D8_APC_1: 0xffffffff
9972 23:03:45.133531 INFO: [APUAPC] D8_APC_2: 0x3fffff
9973 23:03:45.136648 INFO: [APUAPC] D8_APC_3: 0x0
9974 23:03:45.140228 INFO: [APUAPC] D9_APC_0: 0xffffffff
9975 23:03:45.143191 INFO: [APUAPC] D9_APC_1: 0xffffffff
9976 23:03:45.146528 INFO: [APUAPC] D9_APC_2: 0x3fffff
9977 23:03:45.150568 INFO: [APUAPC] D9_APC_3: 0x0
9978 23:03:45.153313 INFO: [APUAPC] D10_APC_0: 0xffffffff
9979 23:03:45.156833 INFO: [APUAPC] D10_APC_1: 0xffffffff
9980 23:03:45.160162 INFO: [APUAPC] D10_APC_2: 0x3fffff
9981 23:03:45.163534 INFO: [APUAPC] D10_APC_3: 0x0
9982 23:03:45.167122 INFO: [APUAPC] D11_APC_0: 0xffffffff
9983 23:03:45.170360 INFO: [APUAPC] D11_APC_1: 0xffffffff
9984 23:03:45.173500 INFO: [APUAPC] D11_APC_2: 0x3fffff
9985 23:03:45.176800 INFO: [APUAPC] D11_APC_3: 0x0
9986 23:03:45.180397 INFO: [APUAPC] D12_APC_0: 0xffffffff
9987 23:03:45.183425 INFO: [APUAPC] D12_APC_1: 0xffffffff
9988 23:03:45.186625 INFO: [APUAPC] D12_APC_2: 0x3fffff
9989 23:03:45.190415 INFO: [APUAPC] D12_APC_3: 0x0
9990 23:03:45.193508 INFO: [APUAPC] D13_APC_0: 0xffffffff
9991 23:03:45.196957 INFO: [APUAPC] D13_APC_1: 0xffffffff
9992 23:03:45.200360 INFO: [APUAPC] D13_APC_2: 0x3fffff
9993 23:03:45.204059 INFO: [APUAPC] D13_APC_3: 0x0
9994 23:03:45.206635 INFO: [APUAPC] D14_APC_0: 0xffffffff
9995 23:03:45.210156 INFO: [APUAPC] D14_APC_1: 0xffffffff
9996 23:03:45.213895 INFO: [APUAPC] D14_APC_2: 0x3fffff
9997 23:03:45.217339 INFO: [APUAPC] D14_APC_3: 0x0
9998 23:03:45.219881 INFO: [APUAPC] D15_APC_0: 0xffffffff
9999 23:03:45.223344 INFO: [APUAPC] D15_APC_1: 0xffffffff
10000 23:03:45.226888 INFO: [APUAPC] D15_APC_2: 0x3fffff
10001 23:03:45.230107 INFO: [APUAPC] D15_APC_3: 0x0
10002 23:03:45.233803 INFO: [APUAPC] APC_CON: 0x4
10003 23:03:45.237042 INFO: [NOCDAPC] D0_APC_0: 0x0
10004 23:03:45.237116 INFO: [NOCDAPC] D0_APC_1: 0x0
10005 23:03:45.240278 INFO: [NOCDAPC] D1_APC_0: 0x0
10006 23:03:45.243418 INFO: [NOCDAPC] D1_APC_1: 0xfff
10007 23:03:45.246851 INFO: [NOCDAPC] D2_APC_0: 0x0
10008 23:03:45.250136 INFO: [NOCDAPC] D2_APC_1: 0xfff
10009 23:03:45.253480 INFO: [NOCDAPC] D3_APC_0: 0x0
10010 23:03:45.256831 INFO: [NOCDAPC] D3_APC_1: 0xfff
10011 23:03:45.260407 INFO: [NOCDAPC] D4_APC_0: 0x0
10012 23:03:45.263823 INFO: [NOCDAPC] D4_APC_1: 0xfff
10013 23:03:45.263932 INFO: [NOCDAPC] D5_APC_0: 0x0
10014 23:03:45.266909 INFO: [NOCDAPC] D5_APC_1: 0xfff
10015 23:03:45.270265 INFO: [NOCDAPC] D6_APC_0: 0x0
10016 23:03:45.273589 INFO: [NOCDAPC] D6_APC_1: 0xfff
10017 23:03:45.276786 INFO: [NOCDAPC] D7_APC_0: 0x0
10018 23:03:45.280380 INFO: [NOCDAPC] D7_APC_1: 0xfff
10019 23:03:45.283857 INFO: [NOCDAPC] D8_APC_0: 0x0
10020 23:03:45.287010 INFO: [NOCDAPC] D8_APC_1: 0xfff
10021 23:03:45.290485 INFO: [NOCDAPC] D9_APC_0: 0x0
10022 23:03:45.293848 INFO: [NOCDAPC] D9_APC_1: 0xfff
10023 23:03:45.297058 INFO: [NOCDAPC] D10_APC_0: 0x0
10024 23:03:45.297177 INFO: [NOCDAPC] D10_APC_1: 0xfff
10025 23:03:45.300634 INFO: [NOCDAPC] D11_APC_0: 0x0
10026 23:03:45.303595 INFO: [NOCDAPC] D11_APC_1: 0xfff
10027 23:03:45.307131 INFO: [NOCDAPC] D12_APC_0: 0x0
10028 23:03:45.310549 INFO: [NOCDAPC] D12_APC_1: 0xfff
10029 23:03:45.314070 INFO: [NOCDAPC] D13_APC_0: 0x0
10030 23:03:45.317149 INFO: [NOCDAPC] D13_APC_1: 0xfff
10031 23:03:45.320664 INFO: [NOCDAPC] D14_APC_0: 0x0
10032 23:03:45.323755 INFO: [NOCDAPC] D14_APC_1: 0xfff
10033 23:03:45.327015 INFO: [NOCDAPC] D15_APC_0: 0x0
10034 23:03:45.330491 INFO: [NOCDAPC] D15_APC_1: 0xfff
10035 23:03:45.334048 INFO: [NOCDAPC] APC_CON: 0x4
10036 23:03:45.336907 INFO: [APUAPC] set_apusys_apc done
10037 23:03:45.340234 INFO: [DEVAPC] devapc_init done
10038 23:03:45.343835 INFO: GICv3 without legacy support detected.
10039 23:03:45.347122 INFO: ARM GICv3 driver initialized in EL3
10040 23:03:45.350228 INFO: Maximum SPI INTID supported: 639
10041 23:03:45.353658 INFO: BL31: Initializing runtime services
10042 23:03:45.360422 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10043 23:03:45.363881 INFO: SPM: enable CPC mode
10044 23:03:45.367122 INFO: mcdi ready for mcusys-off-idle and system suspend
10045 23:03:45.373775 INFO: BL31: Preparing for EL3 exit to normal world
10046 23:03:45.377079 INFO: Entry point address = 0x80000000
10047 23:03:45.380538 INFO: SPSR = 0x8
10048 23:03:45.384629
10049 23:03:45.384710
10050 23:03:45.384774
10051 23:03:45.388258 Starting depthcharge on Spherion...
10052 23:03:45.388364
10053 23:03:45.388453 Wipe memory regions:
10054 23:03:45.388544
10055 23:03:45.389384 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10056 23:03:45.389514 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10057 23:03:45.389637 Setting prompt string to ['asurada:']
10058 23:03:45.389745 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10059 23:03:45.391586 [0x00000040000000, 0x00000054600000)
10060 23:03:45.513943
10061 23:03:45.514163 [0x00000054660000, 0x00000080000000)
10062 23:03:45.773952
10063 23:03:45.774086 [0x000000821a7280, 0x000000ffe64000)
10064 23:03:46.518892
10065 23:03:46.519026 [0x00000100000000, 0x00000240000000)
10066 23:03:48.409550
10067 23:03:48.412492 Initializing XHCI USB controller at 0x11200000.
10068 23:03:49.451150
10069 23:03:49.454542 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10070 23:03:49.454623
10071 23:03:49.454685
10072 23:03:49.454744
10073 23:03:49.455029 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10075 23:03:49.555366 asurada: tftpboot 192.168.201.1 12154390/tftp-deploy-2ku5fbdd/kernel/image.itb 12154390/tftp-deploy-2ku5fbdd/kernel/cmdline
10076 23:03:49.555528 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10077 23:03:49.555631 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10078 23:03:49.560287 tftpboot 192.168.201.1 12154390/tftp-deploy-2ku5fbdd/kernel/image.itp-deploy-2ku5fbdd/kernel/cmdline
10079 23:03:49.560371
10080 23:03:49.560435 Waiting for link
10081 23:03:49.720377
10082 23:03:49.720509 R8152: Initializing
10083 23:03:49.720577
10084 23:03:49.723808 Version 6 (ocp_data = 5c30)
10085 23:03:49.723891
10086 23:03:49.727191 R8152: Done initializing
10087 23:03:49.727299
10088 23:03:49.727393 Adding net device
10089 23:03:51.692611
10090 23:03:51.692769 done.
10091 23:03:51.692939
10092 23:03:51.693086 MAC: 00:24:32:30:78:52
10093 23:03:51.693189
10094 23:03:51.696142 Sending DHCP discover... done.
10095 23:03:51.696249
10096 23:03:51.699894 Waiting for reply... done.
10097 23:03:51.700003
10098 23:03:51.702686 Sending DHCP request... done.
10099 23:03:51.702785
10100 23:03:51.707770 Waiting for reply... done.
10101 23:03:51.707851
10102 23:03:51.707916 My ip is 192.168.201.14
10103 23:03:51.707976
10104 23:03:51.711051 The DHCP server ip is 192.168.201.1
10105 23:03:51.711132
10106 23:03:51.717499 TFTP server IP predefined by user: 192.168.201.1
10107 23:03:51.717580
10108 23:03:51.724463 Bootfile predefined by user: 12154390/tftp-deploy-2ku5fbdd/kernel/image.itb
10109 23:03:51.724544
10110 23:03:51.724608 Sending tftp read request... done.
10111 23:03:51.727949
10112 23:03:51.731211 Waiting for the transfer...
10113 23:03:51.731324
10114 23:03:52.255476 00000000 ################################################################
10115 23:03:52.255656
10116 23:03:52.777546 00080000 ################################################################
10117 23:03:52.777690
10118 23:03:53.305750 00100000 ################################################################
10119 23:03:53.305912
10120 23:03:53.821854 00180000 ################################################################
10121 23:03:53.822002
10122 23:03:54.341100 00200000 ################################################################
10123 23:03:54.341289
10124 23:03:54.886283 00280000 ################################################################
10125 23:03:54.886772
10126 23:03:55.565588 00300000 ################################################################
10127 23:03:55.566101
10128 23:03:56.253228 00380000 ################################################################
10129 23:03:56.253736
10130 23:03:56.940288 00400000 ################################################################
10131 23:03:56.940784
10132 23:03:57.611142 00480000 ################################################################
10133 23:03:57.611945
10134 23:03:58.259017 00500000 ################################################################
10135 23:03:58.259146
10136 23:03:58.863502 00580000 ################################################################
10137 23:03:58.863632
10138 23:03:59.539298 00600000 ################################################################
10139 23:03:59.539835
10140 23:04:00.216495 00680000 ################################################################
10141 23:04:00.216987
10142 23:04:00.898759 00700000 ################################################################
10143 23:04:00.899300
10144 23:04:01.584047 00780000 ################################################################
10145 23:04:01.584556
10146 23:04:02.270095 00800000 ################################################################
10147 23:04:02.270708
10148 23:04:02.958099 00880000 ################################################################
10149 23:04:02.958729
10150 23:04:03.660502 00900000 ################################################################
10151 23:04:03.661014
10152 23:04:04.344527 00980000 ################################################################
10153 23:04:04.345104
10154 23:04:05.036181 00a00000 ################################################################
10155 23:04:05.036708
10156 23:04:05.740810 00a80000 ################################################################
10157 23:04:05.741373
10158 23:04:06.381959 00b00000 ################################################################
10159 23:04:06.382496
10160 23:04:07.077816 00b80000 ################################################################
10161 23:04:07.078355
10162 23:04:07.783273 00c00000 ################################################################
10163 23:04:07.783756
10164 23:04:08.360886 00c80000 ################################################################
10165 23:04:08.361031
10166 23:04:08.916373 00d00000 ################################################################
10167 23:04:08.916506
10168 23:04:09.491870 00d80000 ################################################################
10169 23:04:09.492003
10170 23:04:10.053657 00e00000 ################################################################
10171 23:04:10.053785
10172 23:04:10.630279 00e80000 ################################################################
10173 23:04:10.630411
10174 23:04:11.212428 00f00000 ################################################################
10175 23:04:11.212563
10176 23:04:11.836399 00f80000 ################################################################
10177 23:04:11.836573
10178 23:04:12.481981 01000000 ################################################################
10179 23:04:12.482132
10180 23:04:13.099823 01080000 ################################################################
10181 23:04:13.100331
10182 23:04:13.768790 01100000 ################################################################
10183 23:04:13.769279
10184 23:04:14.410932 01180000 ################################################################
10185 23:04:14.411076
10186 23:04:14.993043 01200000 ################################################################
10187 23:04:14.993194
10188 23:04:15.609671 01280000 ################################################################
10189 23:04:15.610276
10190 23:04:16.236950 01300000 ################################################################
10191 23:04:16.237495
10192 23:04:16.865682 01380000 ################################################################
10193 23:04:16.865832
10194 23:04:17.461439 01400000 ################################################################
10195 23:04:17.461576
10196 23:04:18.038872 01480000 ################################################################
10197 23:04:18.039021
10198 23:04:18.667128 01500000 ################################################################
10199 23:04:18.667656
10200 23:04:19.352964 01580000 ################################################################
10201 23:04:19.353115
10202 23:04:20.021845 01600000 ################################################################
10203 23:04:20.022040
10204 23:04:20.704073 01680000 ################################################################
10205 23:04:20.704443
10206 23:04:21.341532 01700000 ################################################################
10207 23:04:21.341667
10208 23:04:21.964337 01780000 ################################################################
10209 23:04:21.964473
10210 23:04:22.585190 01800000 ################################################################
10211 23:04:22.585327
10212 23:04:23.250641 01880000 ################################################################
10213 23:04:23.250776
10214 23:04:23.898341 01900000 ################################################################
10215 23:04:23.898492
10216 23:04:24.507989 01980000 ################################################################
10217 23:04:24.508125
10218 23:04:25.155755 01a00000 ################################################################
10219 23:04:25.155899
10220 23:04:25.739274 01a80000 ################################################################
10221 23:04:25.739415
10222 23:04:26.377957 01b00000 ################################################################
10223 23:04:26.378485
10224 23:04:27.072386 01b80000 ################################################################
10225 23:04:27.072911
10226 23:04:27.769207 01c00000 ################################################################
10227 23:04:27.769713
10228 23:04:28.489660 01c80000 ################################################################
10229 23:04:28.490206
10230 23:04:29.164558 01d00000 ################################################################
10231 23:04:29.165070
10232 23:04:29.879213 01d80000 ################################################################
10233 23:04:29.879837
10234 23:04:30.598918 01e00000 ################################################################
10235 23:04:30.599522
10236 23:04:31.250472 01e80000 ################################################################
10237 23:04:31.250622
10238 23:04:31.898544 01f00000 ################################################################
10239 23:04:31.898693
10240 23:04:32.491011 01f80000 ################################################################
10241 23:04:32.491156
10242 23:04:33.037323 02000000 ################################################################
10243 23:04:33.037473
10244 23:04:33.585782 02080000 ################################################################
10245 23:04:33.585954
10246 23:04:34.230669 02100000 ################################################################
10247 23:04:34.230821
10248 23:04:34.866069 02180000 ################################################################
10249 23:04:34.866230
10250 23:04:35.450058 02200000 ################################################################
10251 23:04:35.450210
10252 23:04:36.029288 02280000 ################################################################
10253 23:04:36.029435
10254 23:04:36.629377 02300000 ################################################################
10255 23:04:36.629527
10256 23:04:37.221838 02380000 ################################################################
10257 23:04:37.222011
10258 23:04:37.810690 02400000 ################################################################
10259 23:04:37.810874
10260 23:04:38.409689 02480000 ################################################################
10261 23:04:38.409827
10262 23:04:39.017364 02500000 ################################################################
10263 23:04:39.017913
10264 23:04:39.703491 02580000 ################################################################
10265 23:04:39.704025
10266 23:04:40.415331 02600000 ################################################################
10267 23:04:40.415898
10268 23:04:41.021380 02680000 ################################################################
10269 23:04:41.021522
10270 23:04:41.672326 02700000 ################################################################
10271 23:04:41.672842
10272 23:04:42.390680 02780000 ################################################################
10273 23:04:42.391226
10274 23:04:42.980047 02800000 ################################################################
10275 23:04:42.980195
10276 23:04:43.577748 02880000 ################################################################
10277 23:04:43.577899
10278 23:04:44.151996 02900000 ################################################################
10279 23:04:44.152148
10280 23:04:44.742399 02980000 ################################################################
10281 23:04:44.742548
10282 23:04:45.337307 02a00000 ################################################################
10283 23:04:45.337456
10284 23:04:45.928059 02a80000 ################################################################
10285 23:04:45.928204
10286 23:04:46.522822 02b00000 ################################################################
10287 23:04:46.523003
10288 23:04:47.097944 02b80000 ################################################################
10289 23:04:47.098077
10290 23:04:47.654535 02c00000 ################################################################
10291 23:04:47.654682
10292 23:04:48.232009 02c80000 ################################################################
10293 23:04:48.232146
10294 23:04:48.826113 02d00000 ################################################################
10295 23:04:48.826263
10296 23:04:49.421641 02d80000 ################################################################
10297 23:04:49.421792
10298 23:04:50.020127 02e00000 ################################################################
10299 23:04:50.020267
10300 23:04:50.611229 02e80000 ################################################################
10301 23:04:50.611373
10302 23:04:51.212046 02f00000 ################################################################
10303 23:04:51.212192
10304 23:04:51.810166 02f80000 ################################################################
10305 23:04:51.810317
10306 23:04:52.405792 03000000 ################################################################
10307 23:04:52.405972
10308 23:04:52.984036 03080000 ################################################################
10309 23:04:52.984183
10310 23:04:53.675145 03100000 ################################################################
10311 23:04:53.675312
10312 23:04:54.324036 03180000 ################################################################
10313 23:04:54.324422
10314 23:04:54.972476 03200000 ################################################################
10315 23:04:54.972620
10316 23:04:55.606023 03280000 ################################################################
10317 23:04:55.606204
10318 23:04:56.230749 03300000 ################################################################
10319 23:04:56.230899
10320 23:04:56.831791 03380000 ################################################################
10321 23:04:56.831947
10322 23:04:57.422838 03400000 ################################################################
10323 23:04:57.422987
10324 23:04:57.998811 03480000 ################################################################
10325 23:04:57.999017
10326 23:04:58.568522 03500000 ################################################################
10327 23:04:58.568691
10328 23:04:59.131546 03580000 ################################################################
10329 23:04:59.131695
10330 23:04:59.731865 03600000 ################################################################
10331 23:04:59.732010
10332 23:05:00.328381 03680000 ################################################################
10333 23:05:00.328521
10334 23:05:00.910234 03700000 ################################################################
10335 23:05:00.910376
10336 23:05:01.480925 03780000 ################################################################
10337 23:05:01.481073
10338 23:05:02.074857 03800000 ################################################################
10339 23:05:02.075003
10340 23:05:02.672892 03880000 ################################################################
10341 23:05:02.673038
10342 23:05:03.252681 03900000 ################################################################
10343 23:05:03.252827
10344 23:05:03.851063 03980000 ################################################################
10345 23:05:03.851207
10346 23:05:04.454850 03a00000 ################################################################
10347 23:05:04.455002
10348 23:05:05.037818 03a80000 ################################################################
10349 23:05:05.037969
10350 23:05:05.633599 03b00000 ################################################################
10351 23:05:05.633754
10352 23:05:06.218772 03b80000 ################################################################
10353 23:05:06.218959
10354 23:05:06.816010 03c00000 ################################################################
10355 23:05:06.816157
10356 23:05:07.400168 03c80000 ################################################################
10357 23:05:07.400315
10358 23:05:07.991076 03d00000 ################################################################
10359 23:05:07.991264
10360 23:05:08.591316 03d80000 ################################################################
10361 23:05:08.591464
10362 23:05:09.163555 03e00000 ################################################################
10363 23:05:09.163707
10364 23:05:09.759605 03e80000 ################################################################
10365 23:05:09.759755
10366 23:05:10.342909 03f00000 ################################################################
10367 23:05:10.343063
10368 23:05:10.930212 03f80000 ################################################################
10369 23:05:10.930368
10370 23:05:11.518690 04000000 ################################################################
10371 23:05:11.518847
10372 23:05:12.102520 04080000 ################################################################
10373 23:05:12.102675
10374 23:05:12.693677 04100000 ################################################################
10375 23:05:12.693837
10376 23:05:13.276916 04180000 ################################################################
10377 23:05:13.277067
10378 23:05:13.856010 04200000 ################################################################
10379 23:05:13.856165
10380 23:05:14.438914 04280000 ################################################################
10381 23:05:14.439061
10382 23:05:15.023071 04300000 ################################################################
10383 23:05:15.023222
10384 23:05:15.605158 04380000 ################################################################
10385 23:05:15.605310
10386 23:05:16.202319 04400000 ################################################################
10387 23:05:16.202474
10388 23:05:16.794524 04480000 ################################################################
10389 23:05:16.794680
10390 23:05:17.382829 04500000 ################################################################
10391 23:05:17.383006
10392 23:05:17.969557 04580000 ################################################################
10393 23:05:17.969703
10394 23:05:18.567310 04600000 ################################################################
10395 23:05:18.567458
10396 23:05:19.167743 04680000 ################################################################
10397 23:05:19.167894
10398 23:05:19.767170 04700000 ################################################################
10399 23:05:19.767319
10400 23:05:20.368361 04780000 ################################################################
10401 23:05:20.368510
10402 23:05:20.954805 04800000 ################################################################
10403 23:05:20.955021
10404 23:05:21.629616 04880000 ################################################################
10405 23:05:21.630155
10406 23:05:22.337588 04900000 ################################################################
10407 23:05:22.338172
10408 23:05:23.056174 04980000 ################################################################
10409 23:05:23.056692
10410 23:05:23.734347 04a00000 ################################################################
10411 23:05:23.734519
10412 23:05:24.374157 04a80000 ################################################################
10413 23:05:24.374672
10414 23:05:25.096349 04b00000 ################################################################
10415 23:05:25.096853
10416 23:05:25.813774 04b80000 ################################################################
10417 23:05:25.814316
10418 23:05:26.525909 04c00000 ################################################################
10419 23:05:26.526432
10420 23:05:27.244536 04c80000 ################################################################
10421 23:05:27.245051
10422 23:05:27.912320 04d00000 ################################################################
10423 23:05:27.912452
10424 23:05:28.562820 04d80000 ################################################################
10425 23:05:28.563400
10426 23:05:29.239025 04e00000 ################################################################
10427 23:05:29.239156
10428 23:05:29.928047 04e80000 ################################################################
10429 23:05:29.928575
10430 23:05:30.647583 04f00000 ################################################################
10431 23:05:30.648098
10432 23:05:31.372443 04f80000 ################################################################
10433 23:05:31.372960
10434 23:05:31.991851 05000000 ################################################################
10435 23:05:31.991991
10436 23:05:32.562502 05080000 ################################################################
10437 23:05:32.562644
10438 23:05:33.134783 05100000 ################################################################
10439 23:05:33.134949
10440 23:05:33.706400 05180000 ################################################################
10441 23:05:33.706537
10442 23:05:34.285175 05200000 ################################################################
10443 23:05:34.285310
10444 23:05:34.840490 05280000 ################################################################
10445 23:05:34.840620
10446 23:05:35.414182 05300000 ################################################################
10447 23:05:35.414316
10448 23:05:35.992422 05380000 ################################################################
10449 23:05:35.992550
10450 23:05:36.560049 05400000 ################################################################
10451 23:05:36.560182
10452 23:05:37.127451 05480000 ################################################################
10453 23:05:37.127582
10454 23:05:37.679547 05500000 ################################################################
10455 23:05:37.679674
10456 23:05:38.236914 05580000 ################################################################
10457 23:05:38.237051
10458 23:05:38.809810 05600000 ################################################################
10459 23:05:38.809949
10460 23:05:39.372554 05680000 ################################################################
10461 23:05:39.372725
10462 23:05:39.941000 05700000 ################################################################
10463 23:05:39.941142
10464 23:05:40.505998 05780000 ################################################################
10465 23:05:40.506130
10466 23:05:41.060774 05800000 ################################################################
10467 23:05:41.060909
10468 23:05:41.618482 05880000 ################################################################
10469 23:05:41.618643
10470 23:05:42.176867 05900000 ################################################################
10471 23:05:42.177000
10472 23:05:42.754271 05980000 ################################################################
10473 23:05:42.754407
10474 23:05:43.320158 05a00000 ################################################################
10475 23:05:43.320295
10476 23:05:43.872730 05a80000 ################################################################
10477 23:05:43.872862
10478 23:05:44.438173 05b00000 ################################################################
10479 23:05:44.438331
10480 23:05:44.995689 05b80000 ################################################################
10481 23:05:44.995817
10482 23:05:45.553857 05c00000 ################################################################
10483 23:05:45.554014
10484 23:05:46.112591 05c80000 ################################################################
10485 23:05:46.112724
10486 23:05:46.674400 05d00000 ################################################################
10487 23:05:46.674540
10488 23:05:47.242981 05d80000 ################################################################
10489 23:05:47.243116
10490 23:05:47.921879 05e00000 ################################################################
10491 23:05:47.922446
10492 23:05:48.646720 05e80000 ################################################################
10493 23:05:48.647336
10494 23:05:49.384050 05f00000 ################################################################
10495 23:05:49.384702
10496 23:05:50.033627 05f80000 ################################################################
10497 23:05:50.033760
10498 23:05:50.608322 06000000 ################################################################
10499 23:05:50.608456
10500 23:05:51.252759 06080000 ################################################################
10501 23:05:51.253313
10502 23:05:51.887662 06100000 ################################################################
10503 23:05:51.888158
10504 23:05:52.547104 06180000 ################################################################
10505 23:05:52.547652
10506 23:05:53.224884 06200000 ################################################################
10507 23:05:53.225412
10508 23:05:53.938105 06280000 ################################################################
10509 23:05:53.938597
10510 23:05:54.661408 06300000 ################################################################
10511 23:05:54.661957
10512 23:05:55.375486 06380000 ################################################################
10513 23:05:55.376098
10514 23:05:56.107471 06400000 ################################################################
10515 23:05:56.108026
10516 23:05:56.826269 06480000 ################################################################
10517 23:05:56.826845
10518 23:05:57.554221 06500000 ################################################################
10519 23:05:57.554901
10520 23:05:58.267461 06580000 ################################################################
10521 23:05:58.267978
10522 23:05:58.988044 06600000 ################################################################
10523 23:05:58.988577
10524 23:05:59.727695 06680000 ################################################################
10525 23:05:59.728291
10526 23:06:00.417154 06700000 ################################################################
10527 23:06:00.417421
10528 23:06:01.072359 06780000 ################################################################
10529 23:06:01.072530
10530 23:06:01.577597 06800000 ################################################# done.
10531 23:06:01.578118
10532 23:06:01.580440 The bootfile was 109448270 bytes long.
10533 23:06:01.580857
10534 23:06:01.584236 Sending tftp read request... done.
10535 23:06:01.584691
10536 23:06:01.588060 Waiting for the transfer...
10537 23:06:01.588475
10538 23:06:01.588803 00000000 # done.
10539 23:06:01.589117
10540 23:06:01.594489 Command line loaded dynamically from TFTP file: 12154390/tftp-deploy-2ku5fbdd/kernel/cmdline
10541 23:06:01.594952
10542 23:06:01.608132 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10543 23:06:01.611549
10544 23:06:01.612059 Loading FIT.
10545 23:06:01.612390
10546 23:06:01.614541 Image ramdisk-1 has 98354976 bytes.
10547 23:06:01.614985
10548 23:06:01.617766 Image fdt-1 has 47278 bytes.
10549 23:06:01.618178
10550 23:06:01.618509 Image kernel-1 has 11043984 bytes.
10551 23:06:01.621253
10552 23:06:01.628413 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10553 23:06:01.628926
10554 23:06:01.644330 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10555 23:06:01.647538
10556 23:06:01.651058 Choosing best match conf-1 for compat google,spherion-rev2.
10557 23:06:01.655786
10558 23:06:01.679815 Connected to device vid:did:rid of 1ae0:0028:00
10559 23:06:01.713107
10560 23:06:01.716357 tpm_get_response: command 0x17b, return code 0x0
10561 23:06:01.716931
10562 23:06:01.719940 ec_init: CrosEC protocol v3 supported (256, 248)
10563 23:06:01.724479
10564 23:06:01.727386 tpm_cleanup: add release locality here.
10565 23:06:01.727852
10566 23:06:01.728220 Shutting down all USB controllers.
10567 23:06:01.731034
10568 23:06:01.731590 Removing current net device
10569 23:06:01.731966
10570 23:06:01.737861 Exiting depthcharge with code 4 at timestamp: 165759748
10571 23:06:01.738427
10572 23:06:01.740889 LZMA decompressing kernel-1 to 0x821a6718
10573 23:06:01.741355
10574 23:06:01.744035 LZMA decompressing kernel-1 to 0x40000000
10575 23:06:03.138058
10576 23:06:03.138209 jumping to kernel
10577 23:06:03.138771 end: 2.2.4 bootloader-commands (duration 00:02:18) [common]
10578 23:06:03.138904 start: 2.2.5 auto-login-action (timeout 00:02:07) [common]
10579 23:06:03.138997 Setting prompt string to ['Linux version [0-9]']
10580 23:06:03.139067 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10581 23:06:03.139138 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10582 23:06:03.220970
10583 23:06:03.224199 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10584 23:06:03.227803 start: 2.2.5.1 login-action (timeout 00:02:07) [common]
10585 23:06:03.227899 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10586 23:06:03.227971 Setting prompt string to []
10587 23:06:03.228052 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10588 23:06:03.228125 Using line separator: #'\n'#
10589 23:06:03.228184 No login prompt set.
10590 23:06:03.228247 Parsing kernel messages
10591 23:06:03.228302 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10592 23:06:03.228404 [login-action] Waiting for messages, (timeout 00:02:07)
10593 23:06:03.247504 [ 0.000000] Linux version 6.1.64-cip10 (KernelCI@build-j31357-arm64-gcc-10-defconfig-arm64-chromebook-69txj) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Dec 1 22:47:09 UTC 2023
10594 23:06:03.251286 [ 0.000000] random: crng init done
10595 23:06:03.254851 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10596 23:06:03.258298 [ 0.000000] efi: UEFI not found.
10597 23:06:03.267725 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10598 23:06:03.274260 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10599 23:06:03.284547 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10600 23:06:03.294452 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10601 23:06:03.300927 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10602 23:06:03.304493 [ 0.000000] printk: bootconsole [mtk8250] enabled
10603 23:06:03.313157 [ 0.000000] NUMA: No NUMA configuration found
10604 23:06:03.319804 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10605 23:06:03.326567 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10606 23:06:03.327150 [ 0.000000] Zone ranges:
10607 23:06:03.333357 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10608 23:06:03.336531 [ 0.000000] DMA32 empty
10609 23:06:03.342969 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10610 23:06:03.346419 [ 0.000000] Movable zone start for each node
10611 23:06:03.349556 [ 0.000000] Early memory node ranges
10612 23:06:03.356444 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10613 23:06:03.363003 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10614 23:06:03.370536 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10615 23:06:03.376331 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10616 23:06:03.383078 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10617 23:06:03.389367 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10618 23:06:03.445077 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10619 23:06:03.451651 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10620 23:06:03.458454 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10621 23:06:03.461886 [ 0.000000] psci: probing for conduit method from DT.
10622 23:06:03.468467 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10623 23:06:03.471593 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10624 23:06:03.478508 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10625 23:06:03.481496 [ 0.000000] psci: SMC Calling Convention v1.2
10626 23:06:03.488523 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10627 23:06:03.491849 [ 0.000000] Detected VIPT I-cache on CPU0
10628 23:06:03.498743 [ 0.000000] CPU features: detected: GIC system register CPU interface
10629 23:06:03.505215 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10630 23:06:03.512108 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10631 23:06:03.518460 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10632 23:06:03.525110 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10633 23:06:03.532009 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10634 23:06:03.538626 [ 0.000000] alternatives: applying boot alternatives
10635 23:06:03.542466 [ 0.000000] Fallback order for Node 0: 0
10636 23:06:03.548884 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10637 23:06:03.551906 [ 0.000000] Policy zone: Normal
10638 23:06:03.568472 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10639 23:06:03.578811 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10640 23:06:03.590132 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10641 23:06:03.600007 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10642 23:06:03.606464 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10643 23:06:03.610369 <6>[ 0.000000] software IO TLB: area num 8.
10644 23:06:03.665324 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10645 23:06:03.814812 <6>[ 0.000000] Memory: 7873504K/8385536K available (17984K kernel code, 4116K rwdata, 17316K rodata, 8448K init, 615K bss, 479264K reserved, 32768K cma-reserved)
10646 23:06:03.821147 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10647 23:06:03.827901 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10648 23:06:03.831312 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10649 23:06:03.838168 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10650 23:06:03.845075 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10651 23:06:03.847925 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10652 23:06:03.858264 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10653 23:06:03.864885 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10654 23:06:03.867845 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10655 23:06:03.875752 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10656 23:06:03.879477 <6>[ 0.000000] GICv3: 608 SPIs implemented
10657 23:06:03.885732 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10658 23:06:03.888908 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10659 23:06:03.892260 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10660 23:06:03.902305 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10661 23:06:03.912549 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10662 23:06:03.925442 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10663 23:06:03.932285 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10664 23:06:03.941477 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10665 23:06:03.954564 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10666 23:06:03.961264 <6>[ 0.000001] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10667 23:06:03.968597 <6>[ 0.009239] Console: colour dummy device 80x25
10668 23:06:03.977906 <6>[ 0.013964] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10669 23:06:03.981815 <6>[ 0.024405] pid_max: default: 32768 minimum: 301
10670 23:06:03.987662 <6>[ 0.029307] LSM: Security Framework initializing
10671 23:06:03.994572 <6>[ 0.034275] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10672 23:06:04.004609 <6>[ 0.042137] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10673 23:06:04.011566 <6>[ 0.051561] cblist_init_generic: Setting adjustable number of callback queues.
10674 23:06:04.017827 <6>[ 0.059050] cblist_init_generic: Setting shift to 3 and lim to 1.
10675 23:06:04.024613 <6>[ 0.065389] cblist_init_generic: Setting adjustable number of callback queues.
10676 23:06:04.031406 <6>[ 0.072861] cblist_init_generic: Setting shift to 3 and lim to 1.
10677 23:06:04.038179 <6>[ 0.079261] rcu: Hierarchical SRCU implementation.
10678 23:06:04.041616 <6>[ 0.084307] rcu: Max phase no-delay instances is 1000.
10679 23:06:04.049426 <6>[ 0.091375] EFI services will not be available.
10680 23:06:04.052745 <6>[ 0.096328] smp: Bringing up secondary CPUs ...
10681 23:06:04.062146 <6>[ 0.101377] Detected VIPT I-cache on CPU1
10682 23:06:04.068824 <6>[ 0.101447] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10683 23:06:04.075523 <6>[ 0.101475] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10684 23:06:04.078820 <6>[ 0.101811] Detected VIPT I-cache on CPU2
10685 23:06:04.085120 <6>[ 0.101859] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10686 23:06:04.092072 <6>[ 0.101875] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10687 23:06:04.098585 <6>[ 0.102132] Detected VIPT I-cache on CPU3
10688 23:06:04.105227 <6>[ 0.102179] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10689 23:06:04.112323 <6>[ 0.102193] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10690 23:06:04.115542 <6>[ 0.102497] CPU features: detected: Spectre-v4
10691 23:06:04.121978 <6>[ 0.102504] CPU features: detected: Spectre-BHB
10692 23:06:04.125605 <6>[ 0.102509] Detected PIPT I-cache on CPU4
10693 23:06:04.132536 <6>[ 0.102566] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10694 23:06:04.138830 <6>[ 0.102583] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10695 23:06:04.142492 <6>[ 0.102873] Detected PIPT I-cache on CPU5
10696 23:06:04.151933 <6>[ 0.102935] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10697 23:06:04.158803 <6>[ 0.102951] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10698 23:06:04.162133 <6>[ 0.103233] Detected PIPT I-cache on CPU6
10699 23:06:04.168673 <6>[ 0.103297] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10700 23:06:04.175308 <6>[ 0.103313] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10701 23:06:04.178379 <6>[ 0.103612] Detected PIPT I-cache on CPU7
10702 23:06:04.188556 <6>[ 0.103676] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10703 23:06:04.195201 <6>[ 0.103692] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10704 23:06:04.198711 <6>[ 0.103739] smp: Brought up 1 node, 8 CPUs
10705 23:06:04.201701 <6>[ 0.245159] SMP: Total of 8 processors activated.
10706 23:06:04.208572 <6>[ 0.250110] CPU features: detected: 32-bit EL0 Support
10707 23:06:04.218628 <6>[ 0.255474] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10708 23:06:04.225676 <6>[ 0.264329] CPU features: detected: Common not Private translations
10709 23:06:04.228935 <6>[ 0.270845] CPU features: detected: CRC32 instructions
10710 23:06:04.235018 <6>[ 0.276196] CPU features: detected: RCpc load-acquire (LDAPR)
10711 23:06:04.242341 <6>[ 0.282157] CPU features: detected: LSE atomic instructions
10712 23:06:04.245381 <6>[ 0.287974] CPU features: detected: Privileged Access Never
10713 23:06:04.252129 <6>[ 0.293753] CPU features: detected: RAS Extension Support
10714 23:06:04.258807 <6>[ 0.299396] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10715 23:06:04.265404 <6>[ 0.306611] CPU: All CPU(s) started at EL2
10716 23:06:04.268515 <6>[ 0.310954] alternatives: applying system-wide alternatives
10717 23:06:04.279852 <6>[ 0.321661] devtmpfs: initialized
10718 23:06:04.292498 <6>[ 0.330594] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10719 23:06:04.302497 <6>[ 0.340551] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10720 23:06:04.309391 <6>[ 0.348792] pinctrl core: initialized pinctrl subsystem
10721 23:06:04.312231 <6>[ 0.355430] DMI not present or invalid.
10722 23:06:04.319105 <6>[ 0.359837] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10723 23:06:04.328980 <6>[ 0.366708] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10724 23:06:04.335637 <6>[ 0.374290] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10725 23:06:04.345515 <6>[ 0.382520] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10726 23:06:04.348691 <6>[ 0.390759] audit: initializing netlink subsys (disabled)
10727 23:06:04.358640 <5>[ 0.396449] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10728 23:06:04.365421 <6>[ 0.397157] thermal_sys: Registered thermal governor 'step_wise'
10729 23:06:04.371987 <6>[ 0.404416] thermal_sys: Registered thermal governor 'power_allocator'
10730 23:06:04.375540 <6>[ 0.410674] cpuidle: using governor menu
10731 23:06:04.379079 <6>[ 0.421633] NET: Registered PF_QIPCRTR protocol family
10732 23:06:04.388660 <6>[ 0.427112] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10733 23:06:04.392277 <6>[ 0.434212] ASID allocator initialised with 32768 entries
10734 23:06:04.399027 <6>[ 0.440762] Serial: AMBA PL011 UART driver
10735 23:06:04.407772 <4>[ 0.449507] Trying to register duplicate clock ID: 134
10736 23:06:04.461952 <6>[ 0.507046] KASLR enabled
10737 23:06:04.476228 <6>[ 0.514752] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10738 23:06:04.482953 <6>[ 0.521769] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10739 23:06:04.489459 <6>[ 0.528260] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10740 23:06:04.496074 <6>[ 0.535265] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10741 23:06:04.503052 <6>[ 0.541751] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10742 23:06:04.509854 <6>[ 0.548753] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10743 23:06:04.516411 <6>[ 0.555242] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10744 23:06:04.522828 <6>[ 0.562245] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10745 23:06:04.526252 <6>[ 0.569761] ACPI: Interpreter disabled.
10746 23:06:04.534393 <6>[ 0.576161] iommu: Default domain type: Translated
10747 23:06:04.541224 <6>[ 0.581273] iommu: DMA domain TLB invalidation policy: strict mode
10748 23:06:04.544692 <5>[ 0.587932] SCSI subsystem initialized
10749 23:06:04.551189 <6>[ 0.592091] usbcore: registered new interface driver usbfs
10750 23:06:04.557918 <6>[ 0.597824] usbcore: registered new interface driver hub
10751 23:06:04.560876 <6>[ 0.603372] usbcore: registered new device driver usb
10752 23:06:04.568091 <6>[ 0.609467] pps_core: LinuxPPS API ver. 1 registered
10753 23:06:04.578079 <6>[ 0.614662] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10754 23:06:04.581180 <6>[ 0.624009] PTP clock support registered
10755 23:06:04.584184 <6>[ 0.628250] EDAC MC: Ver: 3.0.0
10756 23:06:04.591570 <6>[ 0.633417] FPGA manager framework
10757 23:06:04.598581 <6>[ 0.637096] Advanced Linux Sound Architecture Driver Initialized.
10758 23:06:04.601724 <6>[ 0.643878] vgaarb: loaded
10759 23:06:04.604879 <6>[ 0.647018] clocksource: Switched to clocksource arch_sys_counter
10760 23:06:04.611646 <5>[ 0.653458] VFS: Disk quotas dquot_6.6.0
10761 23:06:04.618394 <6>[ 0.657643] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10762 23:06:04.621407 <6>[ 0.664832] pnp: PnP ACPI: disabled
10763 23:06:04.629933 <6>[ 0.671495] NET: Registered PF_INET protocol family
10764 23:06:04.639766 <6>[ 0.677088] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10765 23:06:04.650732 <6>[ 0.689414] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10766 23:06:04.661171 <6>[ 0.698229] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10767 23:06:04.667834 <6>[ 0.706202] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10768 23:06:04.674024 <6>[ 0.714903] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10769 23:06:04.686516 <6>[ 0.724660] TCP: Hash tables configured (established 65536 bind 65536)
10770 23:06:04.693230 <6>[ 0.731526] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10771 23:06:04.699757 <6>[ 0.738727] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10772 23:06:04.706153 <6>[ 0.746428] NET: Registered PF_UNIX/PF_LOCAL protocol family
10773 23:06:04.712755 <6>[ 0.752586] RPC: Registered named UNIX socket transport module.
10774 23:06:04.716063 <6>[ 0.758738] RPC: Registered udp transport module.
10775 23:06:04.723613 <6>[ 0.763673] RPC: Registered tcp transport module.
10776 23:06:04.729769 <6>[ 0.768604] RPC: Registered tcp NFSv4.1 backchannel transport module.
10777 23:06:04.732861 <6>[ 0.775267] PCI: CLS 0 bytes, default 64
10778 23:06:04.736323 <6>[ 0.779602] Unpacking initramfs...
10779 23:06:04.760958 <6>[ 0.799161] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10780 23:06:04.771051 <6>[ 0.807826] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10781 23:06:04.774145 <6>[ 0.816679] kvm [1]: IPA Size Limit: 40 bits
10782 23:06:04.781225 <6>[ 0.821207] kvm [1]: GICv3: no GICV resource entry
10783 23:06:04.783976 <6>[ 0.826228] kvm [1]: disabling GICv2 emulation
10784 23:06:04.790521 <6>[ 0.830918] kvm [1]: GIC system register CPU interface enabled
10785 23:06:04.794482 <6>[ 0.837079] kvm [1]: vgic interrupt IRQ18
10786 23:06:04.800996 <6>[ 0.841434] kvm [1]: VHE mode initialized successfully
10787 23:06:04.807708 <5>[ 0.847907] Initialise system trusted keyrings
10788 23:06:04.813933 <6>[ 0.852720] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10789 23:06:04.821146 <6>[ 0.862660] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10790 23:06:04.827583 <5>[ 0.869047] NFS: Registering the id_resolver key type
10791 23:06:04.830783 <5>[ 0.874350] Key type id_resolver registered
10792 23:06:04.837620 <5>[ 0.878765] Key type id_legacy registered
10793 23:06:04.844376 <6>[ 0.883056] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10794 23:06:04.850626 <6>[ 0.889980] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10795 23:06:04.857190 <6>[ 0.897693] 9p: Installing v9fs 9p2000 file system support
10796 23:06:04.894494 <5>[ 0.936170] Key type asymmetric registered
10797 23:06:04.897893 <5>[ 0.940504] Asymmetric key parser 'x509' registered
10798 23:06:04.907645 <6>[ 0.945699] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10799 23:06:04.911598 <6>[ 0.953318] io scheduler mq-deadline registered
10800 23:06:04.914751 <6>[ 0.958091] io scheduler kyber registered
10801 23:06:04.933668 <6>[ 0.975269] EINJ: ACPI disabled.
10802 23:06:04.965778 <4>[ 1.001037] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10803 23:06:04.975831 <4>[ 1.011678] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10804 23:06:04.990422 <6>[ 1.032388] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10805 23:06:04.998749 <6>[ 1.040345] printk: console [ttyS0] disabled
10806 23:06:05.026393 <6>[ 1.064996] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10807 23:06:05.033633 <6>[ 1.074480] printk: console [ttyS0] enabled
10808 23:06:05.036617 <6>[ 1.074480] printk: console [ttyS0] enabled
10809 23:06:05.043443 <6>[ 1.083375] printk: bootconsole [mtk8250] disabled
10810 23:06:05.046690 <6>[ 1.083375] printk: bootconsole [mtk8250] disabled
10811 23:06:05.053495 <6>[ 1.094608] SuperH (H)SCI(F) driver initialized
10812 23:06:05.056406 <6>[ 1.099888] msm_serial: driver initialized
10813 23:06:05.070442 <6>[ 1.108917] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10814 23:06:05.080507 <6>[ 1.117470] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10815 23:06:05.086927 <6>[ 1.126011] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10816 23:06:05.097239 <6>[ 1.134639] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10817 23:06:05.104153 <6>[ 1.143346] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10818 23:06:05.113775 <6>[ 1.152067] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10819 23:06:05.123825 <6>[ 1.160609] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10820 23:06:05.130211 <6>[ 1.169410] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10821 23:06:05.140206 <6>[ 1.177958] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10822 23:06:05.152243 <6>[ 1.193652] loop: module loaded
10823 23:06:05.158396 <6>[ 1.199675] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10824 23:06:05.181434 <4>[ 1.222798] mtk-pmic-keys: Failed to locate of_node [id: -1]
10825 23:06:05.188435 <6>[ 1.229640] megasas: 07.719.03.00-rc1
10826 23:06:05.197161 <6>[ 1.239110] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10827 23:06:05.204686 <6>[ 1.246398] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10828 23:06:05.221690 <6>[ 1.263198] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10829 23:06:05.278583 <6>[ 1.313469] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10830 23:06:08.768595 <6>[ 4.810666] Freeing initrd memory: 96048K
10831 23:06:08.778673 <6>[ 4.820955] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10832 23:06:08.789530 <6>[ 4.831876] tun: Universal TUN/TAP device driver, 1.6
10833 23:06:08.792869 <6>[ 4.837932] thunder_xcv, ver 1.0
10834 23:06:08.795911 <6>[ 4.841438] thunder_bgx, ver 1.0
10835 23:06:08.799274 <6>[ 4.844935] nicpf, ver 1.0
10836 23:06:08.809675 <6>[ 4.848932] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10837 23:06:08.813052 <6>[ 4.856408] hns3: Copyright (c) 2017 Huawei Corporation.
10838 23:06:08.819851 <6>[ 4.862005] hclge is initializing
10839 23:06:08.822949 <6>[ 4.865585] e1000: Intel(R) PRO/1000 Network Driver
10840 23:06:08.830480 <6>[ 4.870714] e1000: Copyright (c) 1999-2006 Intel Corporation.
10841 23:06:08.833591 <6>[ 4.876727] e1000e: Intel(R) PRO/1000 Network Driver
10842 23:06:08.839834 <6>[ 4.881942] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10843 23:06:08.846706 <6>[ 4.888128] igb: Intel(R) Gigabit Ethernet Network Driver
10844 23:06:08.853433 <6>[ 4.893777] igb: Copyright (c) 2007-2014 Intel Corporation.
10845 23:06:08.859672 <6>[ 4.899613] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10846 23:06:08.866732 <6>[ 4.906130] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10847 23:06:08.869755 <6>[ 4.912618] sky2: driver version 1.30
10848 23:06:08.876400 <6>[ 4.917616] VFIO - User Level meta-driver version: 0.3
10849 23:06:08.883503 <6>[ 4.925835] usbcore: registered new interface driver usb-storage
10850 23:06:08.889959 <6>[ 4.932281] usbcore: registered new device driver onboard-usb-hub
10851 23:06:08.899179 <6>[ 4.941422] mt6397-rtc mt6359-rtc: registered as rtc0
10852 23:06:08.909182 <6>[ 4.946888] mt6397-rtc mt6359-rtc: setting system clock to 2023-12-01T23:06:11 UTC (1701471971)
10853 23:06:08.912478 <6>[ 4.956455] i2c_dev: i2c /dev entries driver
10854 23:06:08.928777 <6>[ 4.968170] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10855 23:06:08.949031 <6>[ 4.991157] cpu cpu0: EM: created perf domain
10856 23:06:08.951923 <6>[ 4.996097] cpu cpu4: EM: created perf domain
10857 23:06:08.959083 <6>[ 5.001679] sdhci: Secure Digital Host Controller Interface driver
10858 23:06:08.966001 <6>[ 5.008113] sdhci: Copyright(c) Pierre Ossman
10859 23:06:08.972236 <6>[ 5.013062] Synopsys Designware Multimedia Card Interface Driver
10860 23:06:08.978976 <6>[ 5.019698] sdhci-pltfm: SDHCI platform and OF driver helper
10861 23:06:08.982173 <6>[ 5.019724] mmc0: CQHCI version 5.10
10862 23:06:08.989141 <6>[ 5.029985] ledtrig-cpu: registered to indicate activity on CPUs
10863 23:06:08.995452 <6>[ 5.037078] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10864 23:06:09.002317 <6>[ 5.044154] usbcore: registered new interface driver usbhid
10865 23:06:09.005482 <6>[ 5.049975] usbhid: USB HID core driver
10866 23:06:09.012359 <6>[ 5.054163] spi_master spi0: will run message pump with realtime priority
10867 23:06:09.059018 <6>[ 5.094680] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10868 23:06:09.079418 <6>[ 5.111398] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10869 23:06:09.082244 <6>[ 5.124951] mmc0: Command Queue Engine enabled
10870 23:06:09.089932 <6>[ 5.126861] cros-ec-spi spi0.0: Chrome EC device registered
10871 23:06:09.096536 <6>[ 5.129682] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10872 23:06:09.099851 <6>[ 5.142795] mmcblk0: mmc0:0001 DA4128 116 GiB
10873 23:06:09.110801 <6>[ 5.149584] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10874 23:06:09.117458 <6>[ 5.154334] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10875 23:06:09.123868 <6>[ 5.160028] NET: Registered PF_PACKET protocol family
10876 23:06:09.127044 <6>[ 5.166201] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10877 23:06:09.134164 <6>[ 5.170212] 9pnet: Installing 9P2000 support
10878 23:06:09.137258 <6>[ 5.176019] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10879 23:06:09.144061 <5>[ 5.179902] Key type dns_resolver registered
10880 23:06:09.147048 <6>[ 5.185715] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10881 23:06:09.153903 <6>[ 5.190135] registered taskstats version 1
10882 23:06:09.156972 <5>[ 5.200511] Loading compiled-in X.509 certificates
10883 23:06:09.190085 <4>[ 5.225689] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10884 23:06:09.199639 <4>[ 5.236370] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10885 23:06:09.206313 <3>[ 5.246895] debugfs: File 'uA_load' in directory '/' already present!
10886 23:06:09.213121 <3>[ 5.253595] debugfs: File 'min_uV' in directory '/' already present!
10887 23:06:09.219868 <3>[ 5.260253] debugfs: File 'max_uV' in directory '/' already present!
10888 23:06:09.226584 <3>[ 5.266864] debugfs: File 'constraint_flags' in directory '/' already present!
10889 23:06:09.238977 <3>[ 5.278259] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10890 23:06:09.251734 <6>[ 5.294220] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10891 23:06:09.258596 <6>[ 5.301073] xhci-mtk 11200000.usb: xHCI Host Controller
10892 23:06:09.265228 <6>[ 5.306578] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10893 23:06:09.275433 <6>[ 5.314457] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10894 23:06:09.282037 <6>[ 5.323917] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10895 23:06:09.288572 <6>[ 5.330115] xhci-mtk 11200000.usb: xHCI Host Controller
10896 23:06:09.295267 <6>[ 5.335606] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10897 23:06:09.302198 <6>[ 5.343257] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10898 23:06:09.308898 <6>[ 5.351078] hub 1-0:1.0: USB hub found
10899 23:06:09.312112 <6>[ 5.355094] hub 1-0:1.0: 1 port detected
10900 23:06:09.318828 <6>[ 5.359378] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10901 23:06:09.325872 <6>[ 5.368086] hub 2-0:1.0: USB hub found
10902 23:06:09.328862 <6>[ 5.372103] hub 2-0:1.0: 1 port detected
10903 23:06:09.338277 <6>[ 5.380386] mtk-msdc 11f70000.mmc: Got CD GPIO
10904 23:06:09.348405 <6>[ 5.387512] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10905 23:06:09.354751 <6>[ 5.395533] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10906 23:06:09.364825 <4>[ 5.403435] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10907 23:06:09.374761 <6>[ 5.412967] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10908 23:06:09.381298 <6>[ 5.421046] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10909 23:06:09.387921 <6>[ 5.429149] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10910 23:06:09.397862 <6>[ 5.437079] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10911 23:06:09.404470 <6>[ 5.444899] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10912 23:06:09.414333 <6>[ 5.452719] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10913 23:06:09.424910 <6>[ 5.463244] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10914 23:06:09.430964 <6>[ 5.471622] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10915 23:06:09.441110 <6>[ 5.479961] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10916 23:06:09.447532 <6>[ 5.488302] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10917 23:06:09.457602 <6>[ 5.496640] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10918 23:06:09.464299 <6>[ 5.504982] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10919 23:06:09.474221 <6>[ 5.513322] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10920 23:06:09.481114 <6>[ 5.521660] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10921 23:06:09.490810 <6>[ 5.529999] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10922 23:06:09.501304 <6>[ 5.538337] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10923 23:06:09.507706 <6>[ 5.546676] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10924 23:06:09.517371 <6>[ 5.555015] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10925 23:06:09.524081 <6>[ 5.563354] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10926 23:06:09.533712 <6>[ 5.571693] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10927 23:06:09.540226 <6>[ 5.580032] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10928 23:06:09.546972 <6>[ 5.588901] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10929 23:06:09.553747 <6>[ 5.596231] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10930 23:06:09.561057 <6>[ 5.603171] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10931 23:06:09.570765 <6>[ 5.610036] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10932 23:06:09.577792 <6>[ 5.617004] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10933 23:06:09.584020 <6>[ 5.623842] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10934 23:06:09.594283 <6>[ 5.632968] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10935 23:06:09.603918 <6>[ 5.642087] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10936 23:06:09.613938 <6>[ 5.651380] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10937 23:06:09.624633 <6>[ 5.660854] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10938 23:06:09.630963 <6>[ 5.670326] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10939 23:06:09.640513 <6>[ 5.679448] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10940 23:06:09.650683 <6>[ 5.688922] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10941 23:06:09.660475 <6>[ 5.698040] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10942 23:06:09.670147 <6>[ 5.707337] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10943 23:06:09.680273 <6>[ 5.717502] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10944 23:06:09.690402 <6>[ 5.729530] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10945 23:06:09.720267 <6>[ 5.759531] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10946 23:06:09.748281 <6>[ 5.790828] hub 2-1:1.0: USB hub found
10947 23:06:09.751731 <6>[ 5.795316] hub 2-1:1.0: 3 ports detected
10948 23:06:09.760427 <6>[ 5.802771] hub 2-1:1.0: USB hub found
10949 23:06:09.763877 <6>[ 5.807200] hub 2-1:1.0: 3 ports detected
10950 23:06:09.872535 <6>[ 5.911300] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10951 23:06:10.027026 <6>[ 6.069399] hub 1-1:1.0: USB hub found
10952 23:06:10.030075 <6>[ 6.073860] hub 1-1:1.0: 4 ports detected
10953 23:06:10.039392 <6>[ 6.081985] hub 1-1:1.0: USB hub found
10954 23:06:10.042634 <6>[ 6.086485] hub 1-1:1.0: 4 ports detected
10955 23:06:10.112303 <6>[ 6.151542] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10956 23:06:10.363871 <6>[ 6.403329] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10957 23:06:10.497253 <6>[ 6.539143] hub 1-1.4:1.0: USB hub found
10958 23:06:10.499943 <6>[ 6.543805] hub 1-1.4:1.0: 2 ports detected
10959 23:06:10.510544 <6>[ 6.552612] hub 1-1.4:1.0: USB hub found
10960 23:06:10.513253 <6>[ 6.557193] hub 1-1.4:1.0: 2 ports detected
10961 23:06:10.811630 <6>[ 6.851300] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10962 23:06:11.003909 <6>[ 7.043329] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10964 23:08:10.228869 end: 2.2.5.1 login-action (duration 00:02:07) [common]
10966 23:08:10.229895 auto-login-action failed: 1 of 1 attempts. 'login-action timed out after 127 seconds'
10968 23:08:10.230656 end: 2.2.5 auto-login-action (duration 00:02:07) [common]
10970 23:08:10.231668 depthcharge-retry failed: 1 of 1 attempts. 'login-action timed out after 127 seconds'
10972 23:08:10.232592 end: 2.2 depthcharge-retry (duration 00:05:00) [common]
10975 23:08:10.233755 end: 2 depthcharge-action (duration 00:05:00) [common]
10977 23:08:10.234010 Cleaning after the job
10978 23:08:10.234097 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12154390/tftp-deploy-2ku5fbdd/ramdisk
10979 23:08:10.247459 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12154390/tftp-deploy-2ku5fbdd/kernel
10980 23:08:10.270466 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12154390/tftp-deploy-2ku5fbdd/dtb
10981 23:08:10.270687 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12154390/tftp-deploy-2ku5fbdd/modules
10982 23:08:10.278055 start: 4.1 power-off (timeout 00:00:30) [common]
10983 23:08:10.278238 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=off'
10984 23:08:10.356134 >> Command sent successfully.
10985 23:08:10.358538 Returned 0 in 0 seconds
10986 23:08:10.458932 end: 4.1 power-off (duration 00:00:00) [common]
10988 23:08:10.459351 start: 4.2 read-feedback (timeout 00:10:00) [common]
10989 23:08:10.459666 Listened to connection for namespace 'common' for up to 1s
10990 23:08:11.460602 Finalising connection for namespace 'common'
10991 23:08:11.460823 Disconnecting from shell: Finalise
10992 23:08:11.561481 end: 4.2 read-feedback (duration 00:00:01) [common]
10993 23:08:11.562051 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12154390
10994 23:08:11.761284 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12154390
10995 23:08:11.761466 JobError: Your job cannot terminate cleanly.