Boot log: mt8192-asurada-spherion-r0
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 24
- Kernel Errors: 32
- Errors: 1
1 23:01:59.151647 lava-dispatcher, installed at version: 2023.10
2 23:01:59.151851 start: 0 validate
3 23:01:59.151976 Start time: 2023-12-01 23:01:59.151968+00:00 (UTC)
4 23:01:59.152093 Using caching service: 'http://localhost/cache/?uri=%s'
5 23:01:59.152223 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-v4l2%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 23:01:59.420343 Using caching service: 'http://localhost/cache/?uri=%s'
7 23:01:59.420538 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.64-cip10%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 23:01:59.688696 Using caching service: 'http://localhost/cache/?uri=%s'
9 23:01:59.689504 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.64-cip10%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 23:02:43.545440 Using caching service: 'http://localhost/cache/?uri=%s'
11 23:02:43.546164 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.64-cip10%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 23:02:44.078898 validate duration: 44.93
14 23:02:44.079558 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 23:02:44.079832 start: 1.1 download-retry (timeout 00:10:00) [common]
16 23:02:44.080075 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 23:02:44.080391 Not decompressing ramdisk as can be used compressed.
18 23:02:44.080660 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-v4l2/20230623.0/arm64/rootfs.cpio.gz
19 23:02:44.080776 saving as /var/lib/lava/dispatcher/tmp/12154375/tftp-deploy-4cahwfen/ramdisk/rootfs.cpio.gz
20 23:02:44.080841 total size: 26246609 (25 MB)
21 23:02:46.772458 progress 0 % (0 MB)
22 23:02:46.782270 progress 5 % (1 MB)
23 23:02:46.789106 progress 10 % (2 MB)
24 23:02:46.795831 progress 15 % (3 MB)
25 23:02:46.802820 progress 20 % (5 MB)
26 23:02:46.809545 progress 25 % (6 MB)
27 23:02:46.816219 progress 30 % (7 MB)
28 23:02:46.822951 progress 35 % (8 MB)
29 23:02:46.829603 progress 40 % (10 MB)
30 23:02:46.836245 progress 45 % (11 MB)
31 23:02:46.842998 progress 50 % (12 MB)
32 23:02:46.849698 progress 55 % (13 MB)
33 23:02:46.856357 progress 60 % (15 MB)
34 23:02:46.863122 progress 65 % (16 MB)
35 23:02:46.869984 progress 70 % (17 MB)
36 23:02:46.876988 progress 75 % (18 MB)
37 23:02:46.883743 progress 80 % (20 MB)
38 23:02:46.890622 progress 85 % (21 MB)
39 23:02:46.897419 progress 90 % (22 MB)
40 23:02:46.904287 progress 95 % (23 MB)
41 23:02:46.910960 progress 100 % (25 MB)
42 23:02:46.911204 25 MB downloaded in 2.83 s (8.84 MB/s)
43 23:02:46.911361 end: 1.1.1 http-download (duration 00:00:03) [common]
45 23:02:46.911596 end: 1.1 download-retry (duration 00:00:03) [common]
46 23:02:46.911680 start: 1.2 download-retry (timeout 00:09:57) [common]
47 23:02:46.911761 start: 1.2.1 http-download (timeout 00:09:57) [common]
48 23:02:46.911901 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.64-cip10/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 23:02:46.911969 saving as /var/lib/lava/dispatcher/tmp/12154375/tftp-deploy-4cahwfen/kernel/Image
50 23:02:46.912029 total size: 49172992 (46 MB)
51 23:02:46.912090 No compression specified
52 23:02:46.913217 progress 0 % (0 MB)
53 23:02:46.925885 progress 5 % (2 MB)
54 23:02:46.938362 progress 10 % (4 MB)
55 23:02:46.950800 progress 15 % (7 MB)
56 23:02:46.963188 progress 20 % (9 MB)
57 23:02:46.975902 progress 25 % (11 MB)
58 23:02:46.988729 progress 30 % (14 MB)
59 23:02:47.001659 progress 35 % (16 MB)
60 23:02:47.014279 progress 40 % (18 MB)
61 23:02:47.026746 progress 45 % (21 MB)
62 23:02:47.039161 progress 50 % (23 MB)
63 23:02:47.051529 progress 55 % (25 MB)
64 23:02:47.063912 progress 60 % (28 MB)
65 23:02:47.076474 progress 65 % (30 MB)
66 23:02:47.089186 progress 70 % (32 MB)
67 23:02:47.102094 progress 75 % (35 MB)
68 23:02:47.114851 progress 80 % (37 MB)
69 23:02:47.127824 progress 85 % (39 MB)
70 23:02:47.140756 progress 90 % (42 MB)
71 23:02:47.153124 progress 95 % (44 MB)
72 23:02:47.165431 progress 100 % (46 MB)
73 23:02:47.165649 46 MB downloaded in 0.25 s (184.91 MB/s)
74 23:02:47.165800 end: 1.2.1 http-download (duration 00:00:00) [common]
76 23:02:47.166032 end: 1.2 download-retry (duration 00:00:00) [common]
77 23:02:47.166122 start: 1.3 download-retry (timeout 00:09:57) [common]
78 23:02:47.166208 start: 1.3.1 http-download (timeout 00:09:57) [common]
79 23:02:47.166350 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.64-cip10/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 23:02:47.166425 saving as /var/lib/lava/dispatcher/tmp/12154375/tftp-deploy-4cahwfen/dtb/mt8192-asurada-spherion-r0.dtb
81 23:02:47.166487 total size: 47278 (0 MB)
82 23:02:47.166548 No compression specified
83 23:02:47.167657 progress 69 % (0 MB)
84 23:02:47.167933 progress 100 % (0 MB)
85 23:02:47.168090 0 MB downloaded in 0.00 s (28.17 MB/s)
86 23:02:47.168213 end: 1.3.1 http-download (duration 00:00:00) [common]
88 23:02:47.168430 end: 1.3 download-retry (duration 00:00:00) [common]
89 23:02:47.168521 start: 1.4 download-retry (timeout 00:09:57) [common]
90 23:02:47.168603 start: 1.4.1 http-download (timeout 00:09:57) [common]
91 23:02:47.168719 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.64-cip10/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 23:02:47.168787 saving as /var/lib/lava/dispatcher/tmp/12154375/tftp-deploy-4cahwfen/modules/modules.tar
93 23:02:47.168848 total size: 8616152 (8 MB)
94 23:02:47.168909 Using unxz to decompress xz
95 23:02:47.173197 progress 0 % (0 MB)
96 23:02:47.194162 progress 5 % (0 MB)
97 23:02:47.218018 progress 10 % (0 MB)
98 23:02:47.242128 progress 15 % (1 MB)
99 23:02:47.266684 progress 20 % (1 MB)
100 23:02:47.291707 progress 25 % (2 MB)
101 23:02:47.318963 progress 30 % (2 MB)
102 23:02:47.346527 progress 35 % (2 MB)
103 23:02:47.371201 progress 40 % (3 MB)
104 23:02:47.395748 progress 45 % (3 MB)
105 23:02:47.421680 progress 50 % (4 MB)
106 23:02:47.445618 progress 55 % (4 MB)
107 23:02:47.470549 progress 60 % (4 MB)
108 23:02:47.497429 progress 65 % (5 MB)
109 23:02:47.525642 progress 70 % (5 MB)
110 23:02:47.549826 progress 75 % (6 MB)
111 23:02:47.577991 progress 80 % (6 MB)
112 23:02:47.605123 progress 85 % (7 MB)
113 23:02:47.631394 progress 90 % (7 MB)
114 23:02:47.661888 progress 95 % (7 MB)
115 23:02:47.690768 progress 100 % (8 MB)
116 23:02:47.697264 8 MB downloaded in 0.53 s (15.55 MB/s)
117 23:02:47.697516 end: 1.4.1 http-download (duration 00:00:01) [common]
119 23:02:47.697778 end: 1.4 download-retry (duration 00:00:01) [common]
120 23:02:47.697870 start: 1.5 prepare-tftp-overlay (timeout 00:09:56) [common]
121 23:02:47.697965 start: 1.5.1 extract-nfsrootfs (timeout 00:09:56) [common]
122 23:02:47.698048 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 23:02:47.698131 start: 1.5.2 lava-overlay (timeout 00:09:56) [common]
124 23:02:47.698362 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12154375/lava-overlay-jtkfq56j
125 23:02:47.698495 makedir: /var/lib/lava/dispatcher/tmp/12154375/lava-overlay-jtkfq56j/lava-12154375/bin
126 23:02:47.698603 makedir: /var/lib/lava/dispatcher/tmp/12154375/lava-overlay-jtkfq56j/lava-12154375/tests
127 23:02:47.698702 makedir: /var/lib/lava/dispatcher/tmp/12154375/lava-overlay-jtkfq56j/lava-12154375/results
128 23:02:47.698824 Creating /var/lib/lava/dispatcher/tmp/12154375/lava-overlay-jtkfq56j/lava-12154375/bin/lava-add-keys
129 23:02:47.698972 Creating /var/lib/lava/dispatcher/tmp/12154375/lava-overlay-jtkfq56j/lava-12154375/bin/lava-add-sources
130 23:02:47.699107 Creating /var/lib/lava/dispatcher/tmp/12154375/lava-overlay-jtkfq56j/lava-12154375/bin/lava-background-process-start
131 23:02:47.699238 Creating /var/lib/lava/dispatcher/tmp/12154375/lava-overlay-jtkfq56j/lava-12154375/bin/lava-background-process-stop
132 23:02:47.699365 Creating /var/lib/lava/dispatcher/tmp/12154375/lava-overlay-jtkfq56j/lava-12154375/bin/lava-common-functions
133 23:02:47.699490 Creating /var/lib/lava/dispatcher/tmp/12154375/lava-overlay-jtkfq56j/lava-12154375/bin/lava-echo-ipv4
134 23:02:47.699617 Creating /var/lib/lava/dispatcher/tmp/12154375/lava-overlay-jtkfq56j/lava-12154375/bin/lava-install-packages
135 23:02:47.699741 Creating /var/lib/lava/dispatcher/tmp/12154375/lava-overlay-jtkfq56j/lava-12154375/bin/lava-installed-packages
136 23:02:47.699896 Creating /var/lib/lava/dispatcher/tmp/12154375/lava-overlay-jtkfq56j/lava-12154375/bin/lava-os-build
137 23:02:47.700095 Creating /var/lib/lava/dispatcher/tmp/12154375/lava-overlay-jtkfq56j/lava-12154375/bin/lava-probe-channel
138 23:02:47.700290 Creating /var/lib/lava/dispatcher/tmp/12154375/lava-overlay-jtkfq56j/lava-12154375/bin/lava-probe-ip
139 23:02:47.700421 Creating /var/lib/lava/dispatcher/tmp/12154375/lava-overlay-jtkfq56j/lava-12154375/bin/lava-target-ip
140 23:02:47.700586 Creating /var/lib/lava/dispatcher/tmp/12154375/lava-overlay-jtkfq56j/lava-12154375/bin/lava-target-mac
141 23:02:47.700714 Creating /var/lib/lava/dispatcher/tmp/12154375/lava-overlay-jtkfq56j/lava-12154375/bin/lava-target-storage
142 23:02:47.700844 Creating /var/lib/lava/dispatcher/tmp/12154375/lava-overlay-jtkfq56j/lava-12154375/bin/lava-test-case
143 23:02:47.700973 Creating /var/lib/lava/dispatcher/tmp/12154375/lava-overlay-jtkfq56j/lava-12154375/bin/lava-test-event
144 23:02:47.701098 Creating /var/lib/lava/dispatcher/tmp/12154375/lava-overlay-jtkfq56j/lava-12154375/bin/lava-test-feedback
145 23:02:47.701222 Creating /var/lib/lava/dispatcher/tmp/12154375/lava-overlay-jtkfq56j/lava-12154375/bin/lava-test-raise
146 23:02:47.701348 Creating /var/lib/lava/dispatcher/tmp/12154375/lava-overlay-jtkfq56j/lava-12154375/bin/lava-test-reference
147 23:02:47.701473 Creating /var/lib/lava/dispatcher/tmp/12154375/lava-overlay-jtkfq56j/lava-12154375/bin/lava-test-runner
148 23:02:47.701598 Creating /var/lib/lava/dispatcher/tmp/12154375/lava-overlay-jtkfq56j/lava-12154375/bin/lava-test-set
149 23:02:47.701724 Creating /var/lib/lava/dispatcher/tmp/12154375/lava-overlay-jtkfq56j/lava-12154375/bin/lava-test-shell
150 23:02:47.701852 Updating /var/lib/lava/dispatcher/tmp/12154375/lava-overlay-jtkfq56j/lava-12154375/bin/lava-install-packages (oe)
151 23:02:47.702006 Updating /var/lib/lava/dispatcher/tmp/12154375/lava-overlay-jtkfq56j/lava-12154375/bin/lava-installed-packages (oe)
152 23:02:47.702129 Creating /var/lib/lava/dispatcher/tmp/12154375/lava-overlay-jtkfq56j/lava-12154375/environment
153 23:02:47.702230 LAVA metadata
154 23:02:47.702304 - LAVA_JOB_ID=12154375
155 23:02:47.702368 - LAVA_DISPATCHER_IP=192.168.201.1
156 23:02:47.702471 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:56) [common]
157 23:02:47.702538 skipped lava-vland-overlay
158 23:02:47.702612 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 23:02:47.702689 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:56) [common]
160 23:02:47.702755 skipped lava-multinode-overlay
161 23:02:47.702826 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 23:02:47.702907 start: 1.5.2.3 test-definition (timeout 00:09:56) [common]
163 23:02:47.702981 Loading test definitions
164 23:02:47.703069 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:56) [common]
165 23:02:47.703142 Using /lava-12154375 at stage 0
166 23:02:47.703454 uuid=12154375_1.5.2.3.1 testdef=None
167 23:02:47.703539 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 23:02:47.703623 start: 1.5.2.3.2 test-overlay (timeout 00:09:56) [common]
169 23:02:47.704133 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 23:02:47.704346 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:56) [common]
172 23:02:47.704993 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 23:02:47.705216 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:56) [common]
175 23:02:47.706381 runner path: /var/lib/lava/dispatcher/tmp/12154375/lava-overlay-jtkfq56j/lava-12154375/0/tests/0_v4l2-compliance-mtk-vcodec-enc test_uuid 12154375_1.5.2.3.1
176 23:02:47.706537 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 23:02:47.706747 Creating lava-test-runner.conf files
179 23:02:47.706810 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12154375/lava-overlay-jtkfq56j/lava-12154375/0 for stage 0
180 23:02:47.706898 - 0_v4l2-compliance-mtk-vcodec-enc
181 23:02:47.706997 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 23:02:47.707080 start: 1.5.2.4 compress-overlay (timeout 00:09:56) [common]
183 23:02:47.713753 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 23:02:47.713857 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:56) [common]
185 23:02:47.713941 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 23:02:47.714026 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 23:02:47.714113 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:56) [common]
188 23:02:48.440448 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 23:02:48.440836 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
190 23:02:48.440953 extracting modules file /var/lib/lava/dispatcher/tmp/12154375/tftp-deploy-4cahwfen/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12154375/extract-overlay-ramdisk-hgxxa14l/ramdisk
191 23:02:48.672759 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 23:02:48.672927 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
193 23:02:48.673032 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12154375/compress-overlay-6wcfmxpa/overlay-1.5.2.4.tar.gz to ramdisk
194 23:02:48.673103 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12154375/compress-overlay-6wcfmxpa/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12154375/extract-overlay-ramdisk-hgxxa14l/ramdisk
195 23:02:48.679920 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 23:02:48.680044 start: 1.5.6 configure-preseed-file (timeout 00:09:55) [common]
197 23:02:48.680137 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 23:02:48.680225 start: 1.5.7 compress-ramdisk (timeout 00:09:55) [common]
199 23:02:48.680308 Building ramdisk /var/lib/lava/dispatcher/tmp/12154375/extract-overlay-ramdisk-hgxxa14l/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12154375/extract-overlay-ramdisk-hgxxa14l/ramdisk
200 23:02:49.316908 >> 228439 blocks
201 23:02:53.320865 rename /var/lib/lava/dispatcher/tmp/12154375/extract-overlay-ramdisk-hgxxa14l/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12154375/tftp-deploy-4cahwfen/ramdisk/ramdisk.cpio.gz
202 23:02:53.321318 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 23:02:53.321445 start: 1.5.8 prepare-kernel (timeout 00:09:51) [common]
204 23:02:53.321563 start: 1.5.8.1 prepare-fit (timeout 00:09:51) [common]
205 23:02:53.321674 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12154375/tftp-deploy-4cahwfen/kernel/Image'
206 23:03:05.539814 Returned 0 in 12 seconds
207 23:03:05.640455 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12154375/tftp-deploy-4cahwfen/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12154375/tftp-deploy-4cahwfen/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12154375/tftp-deploy-4cahwfen/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12154375/tftp-deploy-4cahwfen/kernel/image.itb
208 23:03:06.261375 output: FIT description: Kernel Image image with one or more FDT blobs
209 23:03:06.261756 output: Created: Fri Dec 1 23:03:06 2023
210 23:03:06.261836 output: Image 0 (kernel-1)
211 23:03:06.261904 output: Description:
212 23:03:06.261968 output: Created: Fri Dec 1 23:03:06 2023
213 23:03:06.262029 output: Type: Kernel Image
214 23:03:06.262093 output: Compression: lzma compressed
215 23:03:06.262150 output: Data Size: 11043984 Bytes = 10785.14 KiB = 10.53 MiB
216 23:03:06.262206 output: Architecture: AArch64
217 23:03:06.262261 output: OS: Linux
218 23:03:06.262317 output: Load Address: 0x00000000
219 23:03:06.262372 output: Entry Point: 0x00000000
220 23:03:06.262426 output: Hash algo: crc32
221 23:03:06.262477 output: Hash value: 36c84243
222 23:03:06.262532 output: Image 1 (fdt-1)
223 23:03:06.262585 output: Description: mt8192-asurada-spherion-r0
224 23:03:06.262636 output: Created: Fri Dec 1 23:03:06 2023
225 23:03:06.262689 output: Type: Flat Device Tree
226 23:03:06.262740 output: Compression: uncompressed
227 23:03:06.262792 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 23:03:06.262843 output: Architecture: AArch64
229 23:03:06.262894 output: Hash algo: crc32
230 23:03:06.262946 output: Hash value: cc4352de
231 23:03:06.262997 output: Image 2 (ramdisk-1)
232 23:03:06.263047 output: Description: unavailable
233 23:03:06.263099 output: Created: Fri Dec 1 23:03:06 2023
234 23:03:06.263150 output: Type: RAMDisk Image
235 23:03:06.263201 output: Compression: Unknown Compression
236 23:03:06.263252 output: Data Size: 39374781 Bytes = 38451.93 KiB = 37.55 MiB
237 23:03:06.263304 output: Architecture: AArch64
238 23:03:06.263355 output: OS: Linux
239 23:03:06.263406 output: Load Address: unavailable
240 23:03:06.263457 output: Entry Point: unavailable
241 23:03:06.263507 output: Hash algo: crc32
242 23:03:06.263573 output: Hash value: 5e87aa38
243 23:03:06.263628 output: Default Configuration: 'conf-1'
244 23:03:06.263679 output: Configuration 0 (conf-1)
245 23:03:06.263729 output: Description: mt8192-asurada-spherion-r0
246 23:03:06.263780 output: Kernel: kernel-1
247 23:03:06.263831 output: Init Ramdisk: ramdisk-1
248 23:03:06.263883 output: FDT: fdt-1
249 23:03:06.263934 output: Loadables: kernel-1
250 23:03:06.263985 output:
251 23:03:06.264185 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
252 23:03:06.264280 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
253 23:03:06.264378 end: 1.5 prepare-tftp-overlay (duration 00:00:19) [common]
254 23:03:06.264469 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:38) [common]
255 23:03:06.264586 No LXC device requested
256 23:03:06.264666 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 23:03:06.264747 start: 1.7 deploy-device-env (timeout 00:09:38) [common]
258 23:03:06.264820 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 23:03:06.264890 Checking files for TFTP limit of 4294967296 bytes.
260 23:03:06.265377 end: 1 tftp-deploy (duration 00:00:22) [common]
261 23:03:06.265477 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 23:03:06.265574 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 23:03:06.265743 substitutions:
264 23:03:06.265811 - {DTB}: 12154375/tftp-deploy-4cahwfen/dtb/mt8192-asurada-spherion-r0.dtb
265 23:03:06.265874 - {INITRD}: 12154375/tftp-deploy-4cahwfen/ramdisk/ramdisk.cpio.gz
266 23:03:06.265932 - {KERNEL}: 12154375/tftp-deploy-4cahwfen/kernel/Image
267 23:03:06.265988 - {LAVA_MAC}: None
268 23:03:06.266042 - {PRESEED_CONFIG}: None
269 23:03:06.266095 - {PRESEED_LOCAL}: None
270 23:03:06.266148 - {RAMDISK}: 12154375/tftp-deploy-4cahwfen/ramdisk/ramdisk.cpio.gz
271 23:03:06.266200 - {ROOT_PART}: None
272 23:03:06.266253 - {ROOT}: None
273 23:03:06.266305 - {SERVER_IP}: 192.168.201.1
274 23:03:06.266357 - {TEE}: None
275 23:03:06.266409 Parsed boot commands:
276 23:03:06.266462 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 23:03:06.266693 Parsed boot commands: tftpboot 192.168.201.1 12154375/tftp-deploy-4cahwfen/kernel/image.itb 12154375/tftp-deploy-4cahwfen/kernel/cmdline
278 23:03:06.266784 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 23:03:06.266868 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 23:03:06.266964 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 23:03:06.267045 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 23:03:06.267113 Not connected, no need to disconnect.
283 23:03:06.267185 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 23:03:06.267263 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 23:03:06.267328 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
286 23:03:06.271428 Setting prompt string to ['lava-test: # ']
287 23:03:06.271794 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 23:03:06.271905 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 23:03:06.272039 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 23:03:06.272159 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 23:03:06.272391 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=reboot'
292 23:03:11.407269 >> Command sent successfully.
293 23:03:11.409792 Returned 0 in 5 seconds
294 23:03:11.510177 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 23:03:11.510502 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 23:03:11.510596 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 23:03:11.510684 Setting prompt string to 'Starting depthcharge on Spherion...'
299 23:03:11.510751 Changing prompt to 'Starting depthcharge on Spherion...'
300 23:03:11.510818 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 23:03:11.511081 [Enter `^Ec?' for help]
302 23:03:11.688939
303 23:03:11.689086
304 23:03:11.689160 F0: 102B 0000
305 23:03:11.689226
306 23:03:11.689287 F3: 1001 0000 [0200]
307 23:03:11.689346
308 23:03:11.692645 F3: 1001 0000
309 23:03:11.692728
310 23:03:11.692793 F7: 102D 0000
311 23:03:11.692854
312 23:03:11.696152 F1: 0000 0000
313 23:03:11.696235
314 23:03:11.696302 V0: 0000 0000 [0001]
315 23:03:11.696363
316 23:03:11.696423 00: 0007 8000
317 23:03:11.696482
318 23:03:11.699905 01: 0000 0000
319 23:03:11.699988
320 23:03:11.700054 BP: 0C00 0209 [0000]
321 23:03:11.700114
322 23:03:11.703640 G0: 1182 0000
323 23:03:11.703722
324 23:03:11.703788 EC: 0000 0021 [4000]
325 23:03:11.703886
326 23:03:11.707359 S7: 0000 0000 [0000]
327 23:03:11.707441
328 23:03:11.707506 CC: 0000 0000 [0001]
329 23:03:11.707566
330 23:03:11.710506 T0: 0000 0040 [010F]
331 23:03:11.710589
332 23:03:11.710654 Jump to BL
333 23:03:11.710714
334 23:03:11.736256
335 23:03:11.736350
336 23:03:11.736416
337 23:03:11.743641 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 23:03:11.746986 ARM64: Exception handlers installed.
339 23:03:11.750873 ARM64: Testing exception
340 23:03:11.754559 ARM64: Done test exception
341 23:03:11.762100 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 23:03:11.768930 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 23:03:11.775995 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 23:03:11.786937 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 23:03:11.793435 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 23:03:11.803679 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 23:03:11.813503 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 23:03:11.820113 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 23:03:11.838718 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 23:03:11.841916 WDT: Last reset was cold boot
351 23:03:11.845207 SPI1(PAD0) initialized at 2873684 Hz
352 23:03:11.848576 SPI5(PAD0) initialized at 992727 Hz
353 23:03:11.851909 VBOOT: Loading verstage.
354 23:03:11.858678 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 23:03:11.861937 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 23:03:11.865452 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 23:03:11.868760 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 23:03:11.876094 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 23:03:11.882632 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 23:03:11.893649 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
361 23:03:11.893746
362 23:03:11.893812
363 23:03:11.903660 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 23:03:11.907886 ARM64: Exception handlers installed.
365 23:03:11.907970 ARM64: Testing exception
366 23:03:11.911287 ARM64: Done test exception
367 23:03:11.914490 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 23:03:11.921301 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 23:03:11.934595 Probing TPM: . done!
370 23:03:11.934699 TPM ready after 0 ms
371 23:03:11.941819 Connected to device vid:did:rid of 1ae0:0028:00
372 23:03:11.948697 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
373 23:03:11.996397 Initialized TPM device CR50 revision 0
374 23:03:12.011936 tlcl_send_startup: Startup return code is 0
375 23:03:12.012048 TPM: setup succeeded
376 23:03:12.022520 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 23:03:12.031452 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 23:03:12.041504 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 23:03:12.050470 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 23:03:12.053425 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 23:03:12.056783 in-header: 03 07 00 00 08 00 00 00
382 23:03:12.060105 in-data: aa e4 47 04 13 02 00 00
383 23:03:12.063353 Chrome EC: UHEPI supported
384 23:03:12.070142 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 23:03:12.073580 in-header: 03 95 00 00 08 00 00 00
386 23:03:12.077458 in-data: 18 20 20 08 00 00 00 00
387 23:03:12.077542 Phase 1
388 23:03:12.080773 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 23:03:12.088172 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 23:03:12.091756 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 23:03:12.095645 Recovery requested (1009000e)
392 23:03:12.104704 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 23:03:12.110431 tlcl_extend: response is 0
394 23:03:12.119860 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 23:03:12.125434 tlcl_extend: response is 0
396 23:03:12.132099 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 23:03:12.152985 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 23:03:12.160207 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 23:03:12.160301
400 23:03:12.160368
401 23:03:12.167606 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 23:03:12.171249 ARM64: Exception handlers installed.
403 23:03:12.174726 ARM64: Testing exception
404 23:03:12.178697 ARM64: Done test exception
405 23:03:12.197851 pmic_efuse_setting: Set efuses in 11 msecs
406 23:03:12.201136 pmwrap_interface_init: Select PMIF_VLD_RDY
407 23:03:12.207993 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 23:03:12.211335 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 23:03:12.217976 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 23:03:12.221080 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 23:03:12.227738 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 23:03:12.231202 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 23:03:12.234622 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 23:03:12.241159 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 23:03:12.244428 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 23:03:12.251316 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 23:03:12.254534 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 23:03:12.257777 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 23:03:12.264488 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 23:03:12.271609 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 23:03:12.274757 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 23:03:12.281919 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 23:03:12.285950 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 23:03:12.293227 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 23:03:12.300626 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 23:03:12.304194 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 23:03:12.307883 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 23:03:12.315317 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 23:03:12.322737 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 23:03:12.326095 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 23:03:12.329897 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 23:03:12.337321 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 23:03:12.341035 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 23:03:12.348405 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 23:03:12.352186 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 23:03:12.355909 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 23:03:12.362999 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 23:03:12.366724 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 23:03:12.370547 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 23:03:12.377891 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 23:03:12.381497 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 23:03:12.389028 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 23:03:12.392338 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 23:03:12.395805 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 23:03:12.399569 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 23:03:12.407185 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 23:03:12.410625 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 23:03:12.414469 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 23:03:12.418465 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 23:03:12.421953 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 23:03:12.429080 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 23:03:12.432656 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 23:03:12.436391 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 23:03:12.439911 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 23:03:12.443712 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 23:03:12.447141 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 23:03:12.450957 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 23:03:12.462254 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 23:03:12.469384 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 23:03:12.472934 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 23:03:12.480595 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 23:03:12.491520 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 23:03:12.495530 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 23:03:12.499192 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 23:03:12.502242 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 23:03:12.511392 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
467 23:03:12.514790 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 23:03:12.523253 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 23:03:12.526371 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 23:03:12.535649 [RTC]rtc_get_frequency_meter,154: input=15, output=764
471 23:03:12.544908 [RTC]rtc_get_frequency_meter,154: input=23, output=948
472 23:03:12.554350 [RTC]rtc_get_frequency_meter,154: input=19, output=857
473 23:03:12.563893 [RTC]rtc_get_frequency_meter,154: input=17, output=811
474 23:03:12.573285 [RTC]rtc_get_frequency_meter,154: input=16, output=787
475 23:03:12.582903 [RTC]rtc_get_frequency_meter,154: input=16, output=787
476 23:03:12.592541 [RTC]rtc_get_frequency_meter,154: input=17, output=810
477 23:03:12.595924 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
478 23:03:12.603533 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
479 23:03:12.606888 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 23:03:12.610374 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 23:03:12.613906 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 23:03:12.617525 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 23:03:12.621228 ADC[4]: Raw value=670432 ID=5
484 23:03:12.624926 ADC[3]: Raw value=212549 ID=1
485 23:03:12.625009 RAM Code: 0x51
486 23:03:12.628213 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 23:03:12.635443 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 23:03:12.642664 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
489 23:03:12.650248 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
490 23:03:12.653673 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 23:03:12.657219 in-header: 03 07 00 00 08 00 00 00
492 23:03:12.661138 in-data: aa e4 47 04 13 02 00 00
493 23:03:12.661222 Chrome EC: UHEPI supported
494 23:03:12.668455 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 23:03:12.672339 in-header: 03 95 00 00 08 00 00 00
496 23:03:12.675725 in-data: 18 20 20 08 00 00 00 00
497 23:03:12.679349 MRC: failed to locate region type 0.
498 23:03:12.686912 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 23:03:12.690668 DRAM-K: Running full calibration
500 23:03:12.694471 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
501 23:03:12.697873 header.status = 0x0
502 23:03:12.697957 header.version = 0x6 (expected: 0x6)
503 23:03:12.702009 header.size = 0xd00 (expected: 0xd00)
504 23:03:12.705510 header.flags = 0x0
505 23:03:12.709199 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 23:03:12.728947 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
507 23:03:12.736100 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 23:03:12.739824 dram_init: ddr_geometry: 0
509 23:03:12.739906 [EMI] MDL number = 0
510 23:03:12.743199 [EMI] Get MDL freq = 0
511 23:03:12.743283 dram_init: ddr_type: 0
512 23:03:12.747036 is_discrete_lpddr4: 1
513 23:03:12.750639 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 23:03:12.750723
515 23:03:12.750790
516 23:03:12.754472 [Bian_co] ETT version 0.0.0.1
517 23:03:12.758162 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
518 23:03:12.758245
519 23:03:12.761957 dramc_set_vcore_voltage set vcore to 650000
520 23:03:12.762040 Read voltage for 800, 4
521 23:03:12.765467 Vio18 = 0
522 23:03:12.765550 Vcore = 650000
523 23:03:12.765616 Vdram = 0
524 23:03:12.769376 Vddq = 0
525 23:03:12.769459 Vmddr = 0
526 23:03:12.769526 dram_init: config_dvfs: 1
527 23:03:12.776739 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 23:03:12.780252 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 23:03:12.784032 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
530 23:03:12.787697 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
531 23:03:12.791121 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
532 23:03:12.794788 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
533 23:03:12.798395 MEM_TYPE=3, freq_sel=18
534 23:03:12.801823 sv_algorithm_assistance_LP4_1600
535 23:03:12.805574 ============ PULL DRAM RESETB DOWN ============
536 23:03:12.809199 ========== PULL DRAM RESETB DOWN end =========
537 23:03:12.812935 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 23:03:12.816868 ===================================
539 23:03:12.820745 LPDDR4 DRAM CONFIGURATION
540 23:03:12.824274 ===================================
541 23:03:12.824358 EX_ROW_EN[0] = 0x0
542 23:03:12.827893 EX_ROW_EN[1] = 0x0
543 23:03:12.827977 LP4Y_EN = 0x0
544 23:03:12.831784 WORK_FSP = 0x0
545 23:03:12.831868 WL = 0x2
546 23:03:12.835150 RL = 0x2
547 23:03:12.835234 BL = 0x2
548 23:03:12.838888 RPST = 0x0
549 23:03:12.838972 RD_PRE = 0x0
550 23:03:12.842733 WR_PRE = 0x1
551 23:03:12.842818 WR_PST = 0x0
552 23:03:12.846031 DBI_WR = 0x0
553 23:03:12.846115 DBI_RD = 0x0
554 23:03:12.849953 OTF = 0x1
555 23:03:12.850038 ===================================
556 23:03:12.853731 ===================================
557 23:03:12.857060 ANA top config
558 23:03:12.860929 ===================================
559 23:03:12.861016 DLL_ASYNC_EN = 0
560 23:03:12.864397 ALL_SLAVE_EN = 1
561 23:03:12.867795 NEW_RANK_MODE = 1
562 23:03:12.871125 DLL_IDLE_MODE = 1
563 23:03:12.871209 LP45_APHY_COMB_EN = 1
564 23:03:12.874616 TX_ODT_DIS = 1
565 23:03:12.877832 NEW_8X_MODE = 1
566 23:03:12.881268 ===================================
567 23:03:12.884808 ===================================
568 23:03:12.887924 data_rate = 1600
569 23:03:12.888007 CKR = 1
570 23:03:12.891738 DQ_P2S_RATIO = 8
571 23:03:12.895071 ===================================
572 23:03:12.898844 CA_P2S_RATIO = 8
573 23:03:12.902566 DQ_CA_OPEN = 0
574 23:03:12.902649 DQ_SEMI_OPEN = 0
575 23:03:12.906101 CA_SEMI_OPEN = 0
576 23:03:12.909571 CA_FULL_RATE = 0
577 23:03:12.912832 DQ_CKDIV4_EN = 1
578 23:03:12.916088 CA_CKDIV4_EN = 1
579 23:03:12.916171 CA_PREDIV_EN = 0
580 23:03:12.919393 PH8_DLY = 0
581 23:03:12.922724 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 23:03:12.926810 DQ_AAMCK_DIV = 4
583 23:03:12.930639 CA_AAMCK_DIV = 4
584 23:03:12.930723 CA_ADMCK_DIV = 4
585 23:03:12.933992 DQ_TRACK_CA_EN = 0
586 23:03:12.937782 CA_PICK = 800
587 23:03:12.941550 CA_MCKIO = 800
588 23:03:12.941635 MCKIO_SEMI = 0
589 23:03:12.944939 PLL_FREQ = 3068
590 23:03:12.948154 DQ_UI_PI_RATIO = 32
591 23:03:12.951499 CA_UI_PI_RATIO = 0
592 23:03:12.954955 ===================================
593 23:03:12.958446 ===================================
594 23:03:12.962111 memory_type:LPDDR4
595 23:03:12.962195 GP_NUM : 10
596 23:03:12.965968 SRAM_EN : 1
597 23:03:12.966052 MD32_EN : 0
598 23:03:12.969555 ===================================
599 23:03:12.973112 [ANA_INIT] >>>>>>>>>>>>>>
600 23:03:12.976898 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 23:03:12.976990 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 23:03:12.980658 ===================================
603 23:03:12.984268 data_rate = 1600,PCW = 0X7600
604 23:03:12.987987 ===================================
605 23:03:12.991421 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 23:03:12.995578 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 23:03:13.001992 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 23:03:13.005232 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 23:03:13.008662 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 23:03:13.015247 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 23:03:13.015332 [ANA_INIT] flow start
612 23:03:13.018735 [ANA_INIT] PLL >>>>>>>>
613 23:03:13.018819 [ANA_INIT] PLL <<<<<<<<
614 23:03:13.021913 [ANA_INIT] MIDPI >>>>>>>>
615 23:03:13.025345 [ANA_INIT] MIDPI <<<<<<<<
616 23:03:13.028832 [ANA_INIT] DLL >>>>>>>>
617 23:03:13.028915 [ANA_INIT] flow end
618 23:03:13.032188 ============ LP4 DIFF to SE enter ============
619 23:03:13.038733 ============ LP4 DIFF to SE exit ============
620 23:03:13.038816 [ANA_INIT] <<<<<<<<<<<<<
621 23:03:13.041896 [Flow] Enable top DCM control >>>>>
622 23:03:13.045409 [Flow] Enable top DCM control <<<<<
623 23:03:13.048625 Enable DLL master slave shuffle
624 23:03:13.055355 ==============================================================
625 23:03:13.055438 Gating Mode config
626 23:03:13.062010 ==============================================================
627 23:03:13.065316 Config description:
628 23:03:13.072263 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 23:03:13.078678 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 23:03:13.085433 SELPH_MODE 0: By rank 1: By Phase
631 23:03:13.092361 ==============================================================
632 23:03:13.092444 GAT_TRACK_EN = 1
633 23:03:13.095766 RX_GATING_MODE = 2
634 23:03:13.098942 RX_GATING_TRACK_MODE = 2
635 23:03:13.102229 SELPH_MODE = 1
636 23:03:13.105639 PICG_EARLY_EN = 1
637 23:03:13.108823 VALID_LAT_VALUE = 1
638 23:03:13.115441 ==============================================================
639 23:03:13.118901 Enter into Gating configuration >>>>
640 23:03:13.122389 Exit from Gating configuration <<<<
641 23:03:13.125539 Enter into DVFS_PRE_config >>>>>
642 23:03:13.135369 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 23:03:13.138647 Exit from DVFS_PRE_config <<<<<
644 23:03:13.141980 Enter into PICG configuration >>>>
645 23:03:13.145301 Exit from PICG configuration <<<<
646 23:03:13.148656 [RX_INPUT] configuration >>>>>
647 23:03:13.148739 [RX_INPUT] configuration <<<<<
648 23:03:13.155597 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 23:03:13.161858 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 23:03:13.165411 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 23:03:13.171834 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 23:03:13.178673 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 23:03:13.185237 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 23:03:13.188476 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 23:03:13.191864 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 23:03:13.198322 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 23:03:13.201675 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 23:03:13.205222 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 23:03:13.211780 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 23:03:13.215060 ===================================
661 23:03:13.215143 LPDDR4 DRAM CONFIGURATION
662 23:03:13.218489 ===================================
663 23:03:13.221625 EX_ROW_EN[0] = 0x0
664 23:03:13.221707 EX_ROW_EN[1] = 0x0
665 23:03:13.225429 LP4Y_EN = 0x0
666 23:03:13.225511 WORK_FSP = 0x0
667 23:03:13.228432 WL = 0x2
668 23:03:13.228537 RL = 0x2
669 23:03:13.231850 BL = 0x2
670 23:03:13.235084 RPST = 0x0
671 23:03:13.235170 RD_PRE = 0x0
672 23:03:13.238527 WR_PRE = 0x1
673 23:03:13.238610 WR_PST = 0x0
674 23:03:13.241887 DBI_WR = 0x0
675 23:03:13.241969 DBI_RD = 0x0
676 23:03:13.245101 OTF = 0x1
677 23:03:13.248548 ===================================
678 23:03:13.251788 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 23:03:13.255013 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 23:03:13.258468 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 23:03:13.261754 ===================================
682 23:03:13.265337 LPDDR4 DRAM CONFIGURATION
683 23:03:13.268527 ===================================
684 23:03:13.271734 EX_ROW_EN[0] = 0x10
685 23:03:13.271816 EX_ROW_EN[1] = 0x0
686 23:03:13.275250 LP4Y_EN = 0x0
687 23:03:13.275332 WORK_FSP = 0x0
688 23:03:13.278400 WL = 0x2
689 23:03:13.278482 RL = 0x2
690 23:03:13.282083 BL = 0x2
691 23:03:13.282165 RPST = 0x0
692 23:03:13.285123 RD_PRE = 0x0
693 23:03:13.285206 WR_PRE = 0x1
694 23:03:13.288498 WR_PST = 0x0
695 23:03:13.288619 DBI_WR = 0x0
696 23:03:13.291982 DBI_RD = 0x0
697 23:03:13.292064 OTF = 0x1
698 23:03:13.294990 ===================================
699 23:03:13.301616 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 23:03:13.306646 nWR fixed to 40
701 23:03:13.310259 [ModeRegInit_LP4] CH0 RK0
702 23:03:13.310341 [ModeRegInit_LP4] CH0 RK1
703 23:03:13.313717 [ModeRegInit_LP4] CH1 RK0
704 23:03:13.316707 [ModeRegInit_LP4] CH1 RK1
705 23:03:13.316826 match AC timing 12
706 23:03:13.323663 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
707 23:03:13.327089 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 23:03:13.330203 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 23:03:13.336864 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 23:03:13.340203 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 23:03:13.340285 [EMI DOE] emi_dcm 0
712 23:03:13.346809 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 23:03:13.346892 ==
714 23:03:13.350318 Dram Type= 6, Freq= 0, CH_0, rank 0
715 23:03:13.353581 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
716 23:03:13.353664 ==
717 23:03:13.359945 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 23:03:13.366663 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 23:03:13.374099 [CA 0] Center 37 (7~68) winsize 62
720 23:03:13.377202 [CA 1] Center 37 (7~68) winsize 62
721 23:03:13.380741 [CA 2] Center 35 (4~66) winsize 63
722 23:03:13.384031 [CA 3] Center 35 (4~66) winsize 63
723 23:03:13.387409 [CA 4] Center 34 (4~65) winsize 62
724 23:03:13.390968 [CA 5] Center 34 (4~64) winsize 61
725 23:03:13.391049
726 23:03:13.393816 [CmdBusTrainingLP45] Vref(ca) range 1: 32
727 23:03:13.393897
728 23:03:13.397175 [CATrainingPosCal] consider 1 rank data
729 23:03:13.400442 u2DelayCellTimex100 = 270/100 ps
730 23:03:13.403755 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
731 23:03:13.407319 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
732 23:03:13.413845 CA2 delay=35 (4~66),Diff = 1 PI (7 cell)
733 23:03:13.417309 CA3 delay=35 (4~66),Diff = 1 PI (7 cell)
734 23:03:13.420439 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
735 23:03:13.423767 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
736 23:03:13.423847
737 23:03:13.427195 CA PerBit enable=1, Macro0, CA PI delay=34
738 23:03:13.427276
739 23:03:13.430439 [CBTSetCACLKResult] CA Dly = 34
740 23:03:13.430520 CS Dly: 6 (0~37)
741 23:03:13.433852 ==
742 23:03:13.433933 Dram Type= 6, Freq= 0, CH_0, rank 1
743 23:03:13.440528 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
744 23:03:13.440623 ==
745 23:03:13.443930 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 23:03:13.450399 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 23:03:13.459747 [CA 0] Center 37 (7~68) winsize 62
748 23:03:13.463287 [CA 1] Center 37 (6~68) winsize 63
749 23:03:13.466489 [CA 2] Center 35 (5~66) winsize 62
750 23:03:13.470129 [CA 3] Center 35 (4~66) winsize 63
751 23:03:13.473296 [CA 4] Center 33 (3~64) winsize 62
752 23:03:13.476885 [CA 5] Center 34 (3~65) winsize 63
753 23:03:13.476967
754 23:03:13.479949 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 23:03:13.480031
756 23:03:13.483266 [CATrainingPosCal] consider 2 rank data
757 23:03:13.486709 u2DelayCellTimex100 = 270/100 ps
758 23:03:13.490210 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
759 23:03:13.493335 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
760 23:03:13.500090 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
761 23:03:13.503408 CA3 delay=35 (4~66),Diff = 1 PI (7 cell)
762 23:03:13.506557 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
763 23:03:13.510000 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
764 23:03:13.510083
765 23:03:13.513386 CA PerBit enable=1, Macro0, CA PI delay=34
766 23:03:13.513469
767 23:03:13.516631 [CBTSetCACLKResult] CA Dly = 34
768 23:03:13.516714 CS Dly: 6 (0~37)
769 23:03:13.516780
770 23:03:13.519991 ----->DramcWriteLeveling(PI) begin...
771 23:03:13.523228 ==
772 23:03:13.523310 Dram Type= 6, Freq= 0, CH_0, rank 0
773 23:03:13.529819 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
774 23:03:13.529901 ==
775 23:03:13.533075 Write leveling (Byte 0): 28 => 28
776 23:03:13.537056 Write leveling (Byte 1): 28 => 28
777 23:03:13.537139 DramcWriteLeveling(PI) end<-----
778 23:03:13.537204
779 23:03:13.540468 ==
780 23:03:13.540587 Dram Type= 6, Freq= 0, CH_0, rank 0
781 23:03:13.547673 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
782 23:03:13.547756 ==
783 23:03:13.547822 [Gating] SW mode calibration
784 23:03:13.554952 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 23:03:13.561490 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 23:03:13.565006 0 6 0 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 0)
787 23:03:13.568659 0 6 4 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
788 23:03:13.575467 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 23:03:13.578462 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 23:03:13.582148 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 23:03:13.588474 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 23:03:13.591955 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 23:03:13.595163 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 23:03:13.601867 0 7 0 | B1->B0 | 2424 2c2c | 0 0 | (0 0) (1 1)
795 23:03:13.605153 0 7 4 | B1->B0 | 4141 4444 | 0 0 | (0 0) (0 0)
796 23:03:13.608797 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
797 23:03:13.615000 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
798 23:03:13.618396 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
799 23:03:13.621802 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
800 23:03:13.628630 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
801 23:03:13.631689 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
802 23:03:13.635178 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
803 23:03:13.641766 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
804 23:03:13.645363 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
805 23:03:13.648657 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
806 23:03:13.655183 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
807 23:03:13.658564 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
808 23:03:13.661849 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
809 23:03:13.665144 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
810 23:03:13.671936 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
811 23:03:13.675010 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
812 23:03:13.678369 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
813 23:03:13.685229 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
814 23:03:13.688531 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
815 23:03:13.691939 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
816 23:03:13.698358 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
817 23:03:13.701878 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
818 23:03:13.705141 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
819 23:03:13.711922 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
820 23:03:13.712005 Total UI for P1: 0, mck2ui 16
821 23:03:13.718411 best dqsien dly found for B1: ( 0, 10, 0)
822 23:03:13.721708 0 10 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
823 23:03:13.725155 Total UI for P1: 0, mck2ui 16
824 23:03:13.728463 best dqsien dly found for B0: ( 0, 10, 2)
825 23:03:13.732108 best DQS0 dly(MCK, UI, PI) = (0, 10, 2)
826 23:03:13.735280 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
827 23:03:13.735363
828 23:03:13.738607 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 2)
829 23:03:13.741800 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
830 23:03:13.745398 [Gating] SW calibration Done
831 23:03:13.745480 ==
832 23:03:13.748456 Dram Type= 6, Freq= 0, CH_0, rank 0
833 23:03:13.751840 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
834 23:03:13.751923 ==
835 23:03:13.755133 RX Vref Scan: 0
836 23:03:13.755215
837 23:03:13.758612 RX Vref 0 -> 0, step: 1
838 23:03:13.758694
839 23:03:13.758760 RX Delay -130 -> 252, step: 16
840 23:03:13.765181 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
841 23:03:13.768585 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
842 23:03:13.772094 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
843 23:03:13.775125 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
844 23:03:13.778544 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
845 23:03:13.785115 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
846 23:03:13.788411 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
847 23:03:13.791798 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
848 23:03:13.795249 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
849 23:03:13.798513 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
850 23:03:13.805173 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
851 23:03:13.808418 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
852 23:03:13.811731 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
853 23:03:13.815171 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
854 23:03:13.821760 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
855 23:03:13.824907 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
856 23:03:13.824990 ==
857 23:03:13.828284 Dram Type= 6, Freq= 0, CH_0, rank 0
858 23:03:13.831626 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
859 23:03:13.831709 ==
860 23:03:13.831774 DQS Delay:
861 23:03:13.834939 DQS0 = 0, DQS1 = 0
862 23:03:13.835021 DQM Delay:
863 23:03:13.838193 DQM0 = 84, DQM1 = 74
864 23:03:13.838276 DQ Delay:
865 23:03:13.841807 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
866 23:03:13.844955 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =101
867 23:03:13.848336 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
868 23:03:13.851675 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
869 23:03:13.851757
870 23:03:13.851823
871 23:03:13.851883 ==
872 23:03:13.855087 Dram Type= 6, Freq= 0, CH_0, rank 0
873 23:03:13.861750 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
874 23:03:13.861833 ==
875 23:03:13.861899
876 23:03:13.861959
877 23:03:13.862017 TX Vref Scan disable
878 23:03:13.864846 == TX Byte 0 ==
879 23:03:13.868175 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
880 23:03:13.871810 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
881 23:03:13.874909 == TX Byte 1 ==
882 23:03:13.878250 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
883 23:03:13.881947 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
884 23:03:13.884956 ==
885 23:03:13.888182 Dram Type= 6, Freq= 0, CH_0, rank 0
886 23:03:13.891432 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
887 23:03:13.891515 ==
888 23:03:13.903689 TX Vref=22, minBit 0, minWin=27, winSum=442
889 23:03:13.906936 TX Vref=24, minBit 2, minWin=27, winSum=444
890 23:03:13.910309 TX Vref=26, minBit 2, minWin=27, winSum=449
891 23:03:13.913886 TX Vref=28, minBit 4, minWin=27, winSum=451
892 23:03:13.916952 TX Vref=30, minBit 0, minWin=28, winSum=453
893 23:03:13.920294 TX Vref=32, minBit 0, minWin=28, winSum=454
894 23:03:13.927051 [TxChooseVref] Worse bit 0, Min win 28, Win sum 454, Final Vref 32
895 23:03:13.927134
896 23:03:13.930327 Final TX Range 1 Vref 32
897 23:03:13.930435
898 23:03:13.930530 ==
899 23:03:13.934169 Dram Type= 6, Freq= 0, CH_0, rank 0
900 23:03:13.937622 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
901 23:03:13.937705 ==
902 23:03:13.937772
903 23:03:13.937832
904 23:03:13.940953 TX Vref Scan disable
905 23:03:13.944378 == TX Byte 0 ==
906 23:03:13.947699 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
907 23:03:13.951133 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
908 23:03:13.954509 == TX Byte 1 ==
909 23:03:13.957935 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
910 23:03:13.961130 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
911 23:03:13.961212
912 23:03:13.964446 [DATLAT]
913 23:03:13.964534 Freq=800, CH0 RK0
914 23:03:13.964613
915 23:03:13.967908 DATLAT Default: 0xa
916 23:03:13.967988 0, 0xFFFF, sum = 0
917 23:03:13.971218 1, 0xFFFF, sum = 0
918 23:03:13.971303 2, 0xFFFF, sum = 0
919 23:03:13.974427 3, 0xFFFF, sum = 0
920 23:03:13.974509 4, 0xFFFF, sum = 0
921 23:03:13.977849 5, 0xFFFF, sum = 0
922 23:03:13.977932 6, 0xFFFF, sum = 0
923 23:03:13.981052 7, 0xFFFF, sum = 0
924 23:03:13.981134 8, 0x0, sum = 1
925 23:03:13.984300 9, 0x0, sum = 2
926 23:03:13.984403 10, 0x0, sum = 3
927 23:03:13.987699 11, 0x0, sum = 4
928 23:03:13.987781 best_step = 9
929 23:03:13.987845
930 23:03:13.987905 ==
931 23:03:13.991064 Dram Type= 6, Freq= 0, CH_0, rank 0
932 23:03:13.994294 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
933 23:03:13.994375 ==
934 23:03:13.997832 RX Vref Scan: 1
935 23:03:13.997912
936 23:03:14.001382 Set Vref Range= 32 -> 127
937 23:03:14.001462
938 23:03:14.001527 RX Vref 32 -> 127, step: 1
939 23:03:14.001587
940 23:03:14.004357 RX Delay -111 -> 252, step: 8
941 23:03:14.004437
942 23:03:14.007623 Set Vref, RX VrefLevel [Byte0]: 32
943 23:03:14.011051 [Byte1]: 32
944 23:03:14.014612
945 23:03:14.014739 Set Vref, RX VrefLevel [Byte0]: 33
946 23:03:14.020929 [Byte1]: 33
947 23:03:14.021057
948 23:03:14.024154 Set Vref, RX VrefLevel [Byte0]: 34
949 23:03:14.027449 [Byte1]: 34
950 23:03:14.027529
951 23:03:14.030835 Set Vref, RX VrefLevel [Byte0]: 35
952 23:03:14.034200 [Byte1]: 35
953 23:03:14.034281
954 23:03:14.037500 Set Vref, RX VrefLevel [Byte0]: 36
955 23:03:14.041044 [Byte1]: 36
956 23:03:14.045070
957 23:03:14.045150 Set Vref, RX VrefLevel [Byte0]: 37
958 23:03:14.048411 [Byte1]: 37
959 23:03:14.052658
960 23:03:14.052739 Set Vref, RX VrefLevel [Byte0]: 38
961 23:03:14.055922 [Byte1]: 38
962 23:03:14.060256
963 23:03:14.060336 Set Vref, RX VrefLevel [Byte0]: 39
964 23:03:14.063625 [Byte1]: 39
965 23:03:14.067911
966 23:03:14.067993 Set Vref, RX VrefLevel [Byte0]: 40
967 23:03:14.071222 [Byte1]: 40
968 23:03:14.075593
969 23:03:14.075675 Set Vref, RX VrefLevel [Byte0]: 41
970 23:03:14.078935 [Byte1]: 41
971 23:03:14.083356
972 23:03:14.083437 Set Vref, RX VrefLevel [Byte0]: 42
973 23:03:14.086533 [Byte1]: 42
974 23:03:14.091000
975 23:03:14.091081 Set Vref, RX VrefLevel [Byte0]: 43
976 23:03:14.094257 [Byte1]: 43
977 23:03:14.098541
978 23:03:14.098623 Set Vref, RX VrefLevel [Byte0]: 44
979 23:03:14.101684 [Byte1]: 44
980 23:03:14.106194
981 23:03:14.106276 Set Vref, RX VrefLevel [Byte0]: 45
982 23:03:14.109431 [Byte1]: 45
983 23:03:14.113782
984 23:03:14.113864 Set Vref, RX VrefLevel [Byte0]: 46
985 23:03:14.117239 [Byte1]: 46
986 23:03:14.121491
987 23:03:14.121575 Set Vref, RX VrefLevel [Byte0]: 47
988 23:03:14.125092 [Byte1]: 47
989 23:03:14.129241
990 23:03:14.129322 Set Vref, RX VrefLevel [Byte0]: 48
991 23:03:14.132545 [Byte1]: 48
992 23:03:14.136732
993 23:03:14.136816 Set Vref, RX VrefLevel [Byte0]: 49
994 23:03:14.140135 [Byte1]: 49
995 23:03:14.144326
996 23:03:14.144409 Set Vref, RX VrefLevel [Byte0]: 50
997 23:03:14.147601 [Byte1]: 50
998 23:03:14.152195
999 23:03:14.152278 Set Vref, RX VrefLevel [Byte0]: 51
1000 23:03:14.155382 [Byte1]: 51
1001 23:03:14.159696
1002 23:03:14.159779 Set Vref, RX VrefLevel [Byte0]: 52
1003 23:03:14.163023 [Byte1]: 52
1004 23:03:14.167451
1005 23:03:14.167533 Set Vref, RX VrefLevel [Byte0]: 53
1006 23:03:14.170591 [Byte1]: 53
1007 23:03:14.174907
1008 23:03:14.174990 Set Vref, RX VrefLevel [Byte0]: 54
1009 23:03:14.178327 [Byte1]: 54
1010 23:03:14.182745
1011 23:03:14.182827 Set Vref, RX VrefLevel [Byte0]: 55
1012 23:03:14.185849 [Byte1]: 55
1013 23:03:14.190528
1014 23:03:14.190612 Set Vref, RX VrefLevel [Byte0]: 56
1015 23:03:14.193546 [Byte1]: 56
1016 23:03:14.198025
1017 23:03:14.198109 Set Vref, RX VrefLevel [Byte0]: 57
1018 23:03:14.201365 [Byte1]: 57
1019 23:03:14.205861
1020 23:03:14.205943 Set Vref, RX VrefLevel [Byte0]: 58
1021 23:03:14.209053 [Byte1]: 58
1022 23:03:14.213502
1023 23:03:14.213585 Set Vref, RX VrefLevel [Byte0]: 59
1024 23:03:14.216924 [Byte1]: 59
1025 23:03:14.221099
1026 23:03:14.221181 Set Vref, RX VrefLevel [Byte0]: 60
1027 23:03:14.224707 [Byte1]: 60
1028 23:03:14.228561
1029 23:03:14.228644 Set Vref, RX VrefLevel [Byte0]: 61
1030 23:03:14.232118 [Byte1]: 61
1031 23:03:14.236617
1032 23:03:14.236700 Set Vref, RX VrefLevel [Byte0]: 62
1033 23:03:14.239992 [Byte1]: 62
1034 23:03:14.243882
1035 23:03:14.243964 Set Vref, RX VrefLevel [Byte0]: 63
1036 23:03:14.246926 [Byte1]: 63
1037 23:03:14.251520
1038 23:03:14.251603 Set Vref, RX VrefLevel [Byte0]: 64
1039 23:03:14.254770 [Byte1]: 64
1040 23:03:14.259040
1041 23:03:14.259122 Set Vref, RX VrefLevel [Byte0]: 65
1042 23:03:14.262529 [Byte1]: 65
1043 23:03:14.266818
1044 23:03:14.266900 Set Vref, RX VrefLevel [Byte0]: 66
1045 23:03:14.269980 [Byte1]: 66
1046 23:03:14.274219
1047 23:03:14.274301 Set Vref, RX VrefLevel [Byte0]: 67
1048 23:03:14.277644 [Byte1]: 67
1049 23:03:14.281936
1050 23:03:14.282018 Set Vref, RX VrefLevel [Byte0]: 68
1051 23:03:14.285493 [Byte1]: 68
1052 23:03:14.289524
1053 23:03:14.289610 Set Vref, RX VrefLevel [Byte0]: 69
1054 23:03:14.293451 [Byte1]: 69
1055 23:03:14.297290
1056 23:03:14.297372 Set Vref, RX VrefLevel [Byte0]: 70
1057 23:03:14.300519 [Byte1]: 70
1058 23:03:14.304972
1059 23:03:14.305054 Set Vref, RX VrefLevel [Byte0]: 71
1060 23:03:14.308410 [Byte1]: 71
1061 23:03:14.312526
1062 23:03:14.312610 Set Vref, RX VrefLevel [Byte0]: 72
1063 23:03:14.315938 [Byte1]: 72
1064 23:03:14.320319
1065 23:03:14.320427 Set Vref, RX VrefLevel [Byte0]: 73
1066 23:03:14.323480 [Byte1]: 73
1067 23:03:14.327911
1068 23:03:14.327993 Set Vref, RX VrefLevel [Byte0]: 74
1069 23:03:14.331103 [Byte1]: 74
1070 23:03:14.335584
1071 23:03:14.335668 Set Vref, RX VrefLevel [Byte0]: 75
1072 23:03:14.338985 [Byte1]: 75
1073 23:03:14.343071
1074 23:03:14.343153 Final RX Vref Byte 0 = 50 to rank0
1075 23:03:14.346639 Final RX Vref Byte 1 = 56 to rank0
1076 23:03:14.349730 Final RX Vref Byte 0 = 50 to rank1
1077 23:03:14.353203 Final RX Vref Byte 1 = 56 to rank1==
1078 23:03:14.356603 Dram Type= 6, Freq= 0, CH_0, rank 0
1079 23:03:14.359791 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1080 23:03:14.363161 ==
1081 23:03:14.363244 DQS Delay:
1082 23:03:14.363310 DQS0 = 0, DQS1 = 0
1083 23:03:14.366727 DQM Delay:
1084 23:03:14.366809 DQM0 = 84, DQM1 = 74
1085 23:03:14.370043 DQ Delay:
1086 23:03:14.373383 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1087 23:03:14.373465 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =92
1088 23:03:14.376859 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1089 23:03:14.380039 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =84
1090 23:03:14.383157
1091 23:03:14.383239
1092 23:03:14.389807 [DQSOSCAuto] RK0, (LSB)MR18= 0x3939, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
1093 23:03:14.393329 CH0 RK0: MR19=606, MR18=3939
1094 23:03:14.399819 CH0_RK0: MR19=0x606, MR18=0x3939, DQSOSC=395, MR23=63, INC=94, DEC=63
1095 23:03:14.399901
1096 23:03:14.403242 ----->DramcWriteLeveling(PI) begin...
1097 23:03:14.403325 ==
1098 23:03:14.406492 Dram Type= 6, Freq= 0, CH_0, rank 1
1099 23:03:14.409740 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1100 23:03:14.409823 ==
1101 23:03:14.413148 Write leveling (Byte 0): 27 => 27
1102 23:03:14.416587 Write leveling (Byte 1): 27 => 27
1103 23:03:14.419594 DramcWriteLeveling(PI) end<-----
1104 23:03:14.419704
1105 23:03:14.419797 ==
1106 23:03:14.423054 Dram Type= 6, Freq= 0, CH_0, rank 1
1107 23:03:14.426296 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1108 23:03:14.426379 ==
1109 23:03:14.429916 [Gating] SW mode calibration
1110 23:03:14.436273 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1111 23:03:14.443211 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1112 23:03:14.446557 0 6 0 | B1->B0 | 3030 3030 | 1 1 | (1 0) (0 1)
1113 23:03:14.449903 0 6 4 | B1->B0 | 2525 2424 | 0 1 | (1 0) (1 0)
1114 23:03:14.456513 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1115 23:03:14.459746 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1116 23:03:14.462885 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1117 23:03:14.469718 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1118 23:03:14.473048 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1119 23:03:14.476398 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1120 23:03:14.482989 0 7 0 | B1->B0 | 2d2d 3030 | 0 1 | (0 0) (0 0)
1121 23:03:14.486293 0 7 4 | B1->B0 | 4141 4444 | 0 0 | (0 0) (0 0)
1122 23:03:14.489655 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1123 23:03:14.496529 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1124 23:03:14.499738 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1125 23:03:14.503004 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1126 23:03:14.509761 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1127 23:03:14.513146 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1128 23:03:14.516493 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1129 23:03:14.519668 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1130 23:03:14.526408 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1131 23:03:14.529769 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1132 23:03:14.532890 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1133 23:03:14.539782 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1134 23:03:14.542976 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1135 23:03:14.546277 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1136 23:03:14.552952 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1137 23:03:14.556127 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1138 23:03:14.559583 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1139 23:03:14.566135 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1140 23:03:14.569481 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1141 23:03:14.572966 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1142 23:03:14.579567 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1143 23:03:14.583170 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1144 23:03:14.586710 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1145 23:03:14.592934 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1146 23:03:14.596209 0 10 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1147 23:03:14.599485 Total UI for P1: 0, mck2ui 16
1148 23:03:14.602838 best dqsien dly found for B0: ( 0, 10, 2)
1149 23:03:14.606312 Total UI for P1: 0, mck2ui 16
1150 23:03:14.609629 best dqsien dly found for B1: ( 0, 10, 2)
1151 23:03:14.612968 best DQS0 dly(MCK, UI, PI) = (0, 10, 2)
1152 23:03:14.657031 best DQS1 dly(MCK, UI, PI) = (0, 10, 2)
1153 23:03:14.657119
1154 23:03:14.657184 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 2)
1155 23:03:14.657440 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 2)
1156 23:03:14.657505 [Gating] SW calibration Done
1157 23:03:14.657566 ==
1158 23:03:14.657623 Dram Type= 6, Freq= 0, CH_0, rank 1
1159 23:03:14.657689 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1160 23:03:14.657747 ==
1161 23:03:14.657832 RX Vref Scan: 0
1162 23:03:14.657886
1163 23:03:14.657950 RX Vref 0 -> 0, step: 1
1164 23:03:14.658005
1165 23:03:14.658058 RX Delay -130 -> 252, step: 16
1166 23:03:14.658295 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1167 23:03:14.658538 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1168 23:03:14.658600 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1169 23:03:14.658837 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1170 23:03:14.698213 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1171 23:03:14.698479 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1172 23:03:14.698551 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1173 23:03:14.698797 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1174 23:03:14.699042 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1175 23:03:14.699170 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1176 23:03:14.699238 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1177 23:03:14.699604 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1178 23:03:14.699868 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1179 23:03:14.699937 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1180 23:03:14.702635 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1181 23:03:14.705928 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1182 23:03:14.706009 ==
1183 23:03:14.709542 Dram Type= 6, Freq= 0, CH_0, rank 1
1184 23:03:14.712575 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1185 23:03:14.712656 ==
1186 23:03:14.712721 DQS Delay:
1187 23:03:14.715963 DQS0 = 0, DQS1 = 0
1188 23:03:14.716043 DQM Delay:
1189 23:03:14.719375 DQM0 = 81, DQM1 = 73
1190 23:03:14.719455 DQ Delay:
1191 23:03:14.722760 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =69
1192 23:03:14.726111 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1193 23:03:14.729243 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
1194 23:03:14.732664 DQ12 =85, DQ13 =77, DQ14 =85, DQ15 =85
1195 23:03:14.732745
1196 23:03:14.732809
1197 23:03:14.732868 ==
1198 23:03:14.736097 Dram Type= 6, Freq= 0, CH_0, rank 1
1199 23:03:14.739324 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1200 23:03:14.739408 ==
1201 23:03:14.742685
1202 23:03:14.742778
1203 23:03:14.742843 TX Vref Scan disable
1204 23:03:14.745912 == TX Byte 0 ==
1205 23:03:14.749508 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1206 23:03:14.752740 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1207 23:03:14.755918 == TX Byte 1 ==
1208 23:03:14.759312 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1209 23:03:14.762749 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1210 23:03:14.762833 ==
1211 23:03:14.765908 Dram Type= 6, Freq= 0, CH_0, rank 1
1212 23:03:14.772501 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1213 23:03:14.772623 ==
1214 23:03:14.784648 TX Vref=22, minBit 1, minWin=27, winSum=440
1215 23:03:14.788556 TX Vref=24, minBit 0, minWin=27, winSum=446
1216 23:03:14.791929 TX Vref=26, minBit 14, minWin=27, winSum=448
1217 23:03:14.795516 TX Vref=28, minBit 4, minWin=28, winSum=455
1218 23:03:14.799413 TX Vref=30, minBit 2, minWin=28, winSum=456
1219 23:03:14.802812 TX Vref=32, minBit 2, minWin=28, winSum=456
1220 23:03:14.809755 [TxChooseVref] Worse bit 2, Min win 28, Win sum 456, Final Vref 30
1221 23:03:14.809849
1222 23:03:14.809917 Final TX Range 1 Vref 30
1223 23:03:14.809980
1224 23:03:14.813217 ==
1225 23:03:14.813300 Dram Type= 6, Freq= 0, CH_0, rank 1
1226 23:03:14.819786 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1227 23:03:14.819875 ==
1228 23:03:14.819942
1229 23:03:14.820002
1230 23:03:14.820061 TX Vref Scan disable
1231 23:03:14.824228 == TX Byte 0 ==
1232 23:03:14.827657 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1233 23:03:14.831098 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1234 23:03:14.834460 == TX Byte 1 ==
1235 23:03:14.837770 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1236 23:03:14.841104 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1237 23:03:14.844423
1238 23:03:14.844513 [DATLAT]
1239 23:03:14.844615 Freq=800, CH0 RK1
1240 23:03:14.844677
1241 23:03:14.847512 DATLAT Default: 0x9
1242 23:03:14.847594 0, 0xFFFF, sum = 0
1243 23:03:14.851181 1, 0xFFFF, sum = 0
1244 23:03:14.851266 2, 0xFFFF, sum = 0
1245 23:03:14.854265 3, 0xFFFF, sum = 0
1246 23:03:14.854350 4, 0xFFFF, sum = 0
1247 23:03:14.857618 5, 0xFFFF, sum = 0
1248 23:03:14.861040 6, 0xFFFF, sum = 0
1249 23:03:14.861130 7, 0xFFFF, sum = 0
1250 23:03:14.861198 8, 0x0, sum = 1
1251 23:03:14.864465 9, 0x0, sum = 2
1252 23:03:14.864568 10, 0x0, sum = 3
1253 23:03:14.867564 11, 0x0, sum = 4
1254 23:03:14.867648 best_step = 9
1255 23:03:14.867714
1256 23:03:14.867775 ==
1257 23:03:14.870902 Dram Type= 6, Freq= 0, CH_0, rank 1
1258 23:03:14.877495 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1259 23:03:14.877582 ==
1260 23:03:14.877649 RX Vref Scan: 0
1261 23:03:14.877711
1262 23:03:14.881087 RX Vref 0 -> 0, step: 1
1263 23:03:14.881169
1264 23:03:14.884098 RX Delay -111 -> 252, step: 8
1265 23:03:14.887392 iDelay=217, Bit 0, Center 80 (-39 ~ 200) 240
1266 23:03:14.891169 iDelay=217, Bit 1, Center 88 (-31 ~ 208) 240
1267 23:03:14.897299 iDelay=217, Bit 2, Center 84 (-31 ~ 200) 232
1268 23:03:14.900824 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1269 23:03:14.904124 iDelay=217, Bit 4, Center 88 (-31 ~ 208) 240
1270 23:03:14.907327 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1271 23:03:14.910799 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1272 23:03:14.917264 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1273 23:03:14.920670 iDelay=217, Bit 8, Center 60 (-55 ~ 176) 232
1274 23:03:14.924068 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1275 23:03:14.927468 iDelay=217, Bit 10, Center 72 (-47 ~ 192) 240
1276 23:03:14.930772 iDelay=217, Bit 11, Center 64 (-47 ~ 176) 224
1277 23:03:14.937365 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1278 23:03:14.940760 iDelay=217, Bit 13, Center 80 (-39 ~ 200) 240
1279 23:03:14.944208 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1280 23:03:14.947285 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1281 23:03:14.947372 ==
1282 23:03:14.951053 Dram Type= 6, Freq= 0, CH_0, rank 1
1283 23:03:14.954261 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1284 23:03:14.957629 ==
1285 23:03:14.957713 DQS Delay:
1286 23:03:14.957780 DQS0 = 0, DQS1 = 0
1287 23:03:14.960888 DQM Delay:
1288 23:03:14.960971 DQM0 = 85, DQM1 = 73
1289 23:03:14.964250 DQ Delay:
1290 23:03:14.964334 DQ0 =80, DQ1 =88, DQ2 =84, DQ3 =80
1291 23:03:14.967449 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1292 23:03:14.970928 DQ8 =60, DQ9 =60, DQ10 =72, DQ11 =64
1293 23:03:14.974105 DQ12 =84, DQ13 =80, DQ14 =84, DQ15 =84
1294 23:03:14.974193
1295 23:03:14.977427
1296 23:03:14.984086 [DQSOSCAuto] RK1, (LSB)MR18= 0x4a4a, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
1297 23:03:14.987350 CH0 RK1: MR19=606, MR18=4A4A
1298 23:03:14.994045 CH0_RK1: MR19=0x606, MR18=0x4A4A, DQSOSC=391, MR23=63, INC=96, DEC=64
1299 23:03:14.997280 [RxdqsGatingPostProcess] freq 800
1300 23:03:15.000822 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1301 23:03:15.004012 Pre-setting of DQS Precalculation
1302 23:03:15.007463 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1303 23:03:15.010597 ==
1304 23:03:15.014161 Dram Type= 6, Freq= 0, CH_1, rank 0
1305 23:03:15.017321 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1306 23:03:15.017406 ==
1307 23:03:15.020686 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1308 23:03:15.027460 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1309 23:03:15.036948 [CA 0] Center 36 (6~67) winsize 62
1310 23:03:15.040276 [CA 1] Center 36 (5~67) winsize 63
1311 23:03:15.043761 [CA 2] Center 34 (4~65) winsize 62
1312 23:03:15.047092 [CA 3] Center 34 (4~65) winsize 62
1313 23:03:15.050211 [CA 4] Center 33 (2~64) winsize 63
1314 23:03:15.053694 [CA 5] Center 33 (2~64) winsize 63
1315 23:03:15.053782
1316 23:03:15.057214 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1317 23:03:15.057299
1318 23:03:15.060382 [CATrainingPosCal] consider 1 rank data
1319 23:03:15.063995 u2DelayCellTimex100 = 270/100 ps
1320 23:03:15.066955 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1321 23:03:15.070493 CA1 delay=36 (5~67),Diff = 3 PI (21 cell)
1322 23:03:15.076950 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1323 23:03:15.080452 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1324 23:03:15.083563 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
1325 23:03:15.087249 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
1326 23:03:15.087332
1327 23:03:15.090234 CA PerBit enable=1, Macro0, CA PI delay=33
1328 23:03:15.090317
1329 23:03:15.093682 [CBTSetCACLKResult] CA Dly = 33
1330 23:03:15.093764 CS Dly: 4 (0~35)
1331 23:03:15.093833 ==
1332 23:03:15.097064 Dram Type= 6, Freq= 0, CH_1, rank 1
1333 23:03:15.103553 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1334 23:03:15.103641 ==
1335 23:03:15.106978 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1336 23:03:15.113625 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1337 23:03:15.122765 [CA 0] Center 36 (6~67) winsize 62
1338 23:03:15.126039 [CA 1] Center 36 (5~67) winsize 63
1339 23:03:15.129212 [CA 2] Center 34 (4~65) winsize 62
1340 23:03:15.132664 [CA 3] Center 34 (3~65) winsize 63
1341 23:03:15.136111 [CA 4] Center 32 (2~63) winsize 62
1342 23:03:15.139542 [CA 5] Center 33 (3~63) winsize 61
1343 23:03:15.139635
1344 23:03:15.142625 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1345 23:03:15.142709
1346 23:03:15.145967 [CATrainingPosCal] consider 2 rank data
1347 23:03:15.149439 u2DelayCellTimex100 = 270/100 ps
1348 23:03:15.152767 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
1349 23:03:15.156281 CA1 delay=36 (5~67),Diff = 4 PI (28 cell)
1350 23:03:15.163052 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
1351 23:03:15.166191 CA3 delay=34 (4~65),Diff = 2 PI (14 cell)
1352 23:03:15.169380 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
1353 23:03:15.172615 CA5 delay=33 (3~63),Diff = 1 PI (7 cell)
1354 23:03:15.172697
1355 23:03:15.176046 CA PerBit enable=1, Macro0, CA PI delay=32
1356 23:03:15.176128
1357 23:03:15.179418 [CBTSetCACLKResult] CA Dly = 32
1358 23:03:15.179500 CS Dly: 4 (0~36)
1359 23:03:15.179565
1360 23:03:15.182788 ----->DramcWriteLeveling(PI) begin...
1361 23:03:15.186019 ==
1362 23:03:15.189417 Dram Type= 6, Freq= 0, CH_1, rank 0
1363 23:03:15.192928 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1364 23:03:15.193014 ==
1365 23:03:15.195917 Write leveling (Byte 0): 25 => 25
1366 23:03:15.199154 Write leveling (Byte 1): 25 => 25
1367 23:03:15.202469 DramcWriteLeveling(PI) end<-----
1368 23:03:15.202551
1369 23:03:15.202616 ==
1370 23:03:15.205716 Dram Type= 6, Freq= 0, CH_1, rank 0
1371 23:03:15.209125 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1372 23:03:15.209211 ==
1373 23:03:15.212547 [Gating] SW mode calibration
1374 23:03:15.219159 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1375 23:03:15.225620 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1376 23:03:15.229087 0 6 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
1377 23:03:15.232978 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1378 23:03:15.239008 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1379 23:03:15.242446 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1380 23:03:15.245721 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1381 23:03:15.249086 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1382 23:03:15.255709 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1383 23:03:15.259054 0 6 28 | B1->B0 | 2525 2f2f | 0 0 | (0 0) (0 0)
1384 23:03:15.262385 0 7 0 | B1->B0 | 3030 3d3d | 0 1 | (0 0) (0 0)
1385 23:03:15.269067 0 7 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1386 23:03:15.272244 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1387 23:03:15.275554 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1388 23:03:15.282188 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1389 23:03:15.285520 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1390 23:03:15.288912 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1391 23:03:15.295760 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1392 23:03:15.299028 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1393 23:03:15.302251 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1394 23:03:15.309125 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1395 23:03:15.312406 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1396 23:03:15.315624 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1397 23:03:15.322373 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1398 23:03:15.325607 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1399 23:03:15.329020 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1400 23:03:15.335436 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1401 23:03:15.338838 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1402 23:03:15.342267 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1403 23:03:15.348784 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1404 23:03:15.352032 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1405 23:03:15.355514 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1406 23:03:15.358996 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1407 23:03:15.365650 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1408 23:03:15.368981 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1409 23:03:15.372303 Total UI for P1: 0, mck2ui 16
1410 23:03:15.375660 best dqsien dly found for B0: ( 0, 9, 30)
1411 23:03:15.378991 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1412 23:03:15.382320 Total UI for P1: 0, mck2ui 16
1413 23:03:15.385598 best dqsien dly found for B1: ( 0, 10, 0)
1414 23:03:15.388760 best DQS0 dly(MCK, UI, PI) = (0, 9, 30)
1415 23:03:15.392043 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1416 23:03:15.395523
1417 23:03:15.398929 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 30)
1418 23:03:15.402194 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1419 23:03:15.405640 [Gating] SW calibration Done
1420 23:03:15.405727 ==
1421 23:03:15.408841 Dram Type= 6, Freq= 0, CH_1, rank 0
1422 23:03:15.412166 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1423 23:03:15.412253 ==
1424 23:03:15.412320 RX Vref Scan: 0
1425 23:03:15.412381
1426 23:03:15.415396 RX Vref 0 -> 0, step: 1
1427 23:03:15.415480
1428 23:03:15.418820 RX Delay -130 -> 252, step: 16
1429 23:03:15.422195 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1430 23:03:15.425530 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1431 23:03:15.432194 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1432 23:03:15.435304 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1433 23:03:15.438753 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1434 23:03:15.442200 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1435 23:03:15.445690 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1436 23:03:15.449228 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1437 23:03:15.453171 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1438 23:03:15.460374 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1439 23:03:15.464078 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1440 23:03:15.467764 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1441 23:03:15.471368 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1442 23:03:15.474978 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1443 23:03:15.478690 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1444 23:03:15.482624 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1445 23:03:15.482716 ==
1446 23:03:15.486252 Dram Type= 6, Freq= 0, CH_1, rank 0
1447 23:03:15.489231 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1448 23:03:15.492394 ==
1449 23:03:15.492485 DQS Delay:
1450 23:03:15.492593 DQS0 = 0, DQS1 = 0
1451 23:03:15.495719 DQM Delay:
1452 23:03:15.495804 DQM0 = 82, DQM1 = 72
1453 23:03:15.499207 DQ Delay:
1454 23:03:15.499291 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1455 23:03:15.502480 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =77
1456 23:03:15.505693 DQ8 =53, DQ9 =61, DQ10 =77, DQ11 =61
1457 23:03:15.508986 DQ12 =77, DQ13 =85, DQ14 =77, DQ15 =85
1458 23:03:15.509078
1459 23:03:15.512487
1460 23:03:15.512579 ==
1461 23:03:15.515681 Dram Type= 6, Freq= 0, CH_1, rank 0
1462 23:03:15.518966 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1463 23:03:15.519053 ==
1464 23:03:15.519118
1465 23:03:15.519179
1466 23:03:15.522530 TX Vref Scan disable
1467 23:03:15.522618 == TX Byte 0 ==
1468 23:03:15.529153 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1469 23:03:15.532399 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1470 23:03:15.532489 == TX Byte 1 ==
1471 23:03:15.538917 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1472 23:03:15.542392 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1473 23:03:15.542486 ==
1474 23:03:15.545561 Dram Type= 6, Freq= 0, CH_1, rank 0
1475 23:03:15.548847 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1476 23:03:15.548934 ==
1477 23:03:15.562095 TX Vref=22, minBit 3, minWin=27, winSum=446
1478 23:03:15.565433 TX Vref=24, minBit 0, minWin=28, winSum=450
1479 23:03:15.568714 TX Vref=26, minBit 0, minWin=28, winSum=454
1480 23:03:15.571971 TX Vref=28, minBit 0, minWin=28, winSum=454
1481 23:03:15.575376 TX Vref=30, minBit 3, minWin=28, winSum=455
1482 23:03:15.578736 TX Vref=32, minBit 2, minWin=28, winSum=456
1483 23:03:15.585414 [TxChooseVref] Worse bit 2, Min win 28, Win sum 456, Final Vref 32
1484 23:03:15.585513
1485 23:03:15.588779 Final TX Range 1 Vref 32
1486 23:03:15.588866
1487 23:03:15.588931 ==
1488 23:03:15.592023 Dram Type= 6, Freq= 0, CH_1, rank 0
1489 23:03:15.595447 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1490 23:03:15.595546 ==
1491 23:03:15.595614
1492 23:03:15.598982
1493 23:03:15.599067 TX Vref Scan disable
1494 23:03:15.602069 == TX Byte 0 ==
1495 23:03:15.605478 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1496 23:03:15.608869 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1497 23:03:15.612082 == TX Byte 1 ==
1498 23:03:15.615416 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1499 23:03:15.618859 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1500 23:03:15.618951
1501 23:03:15.622105 [DATLAT]
1502 23:03:15.622214 Freq=800, CH1 RK0
1503 23:03:15.622284
1504 23:03:15.625493 DATLAT Default: 0xa
1505 23:03:15.625578 0, 0xFFFF, sum = 0
1506 23:03:15.628797 1, 0xFFFF, sum = 0
1507 23:03:15.628883 2, 0xFFFF, sum = 0
1508 23:03:15.632255 3, 0xFFFF, sum = 0
1509 23:03:15.632340 4, 0xFFFF, sum = 0
1510 23:03:15.635696 5, 0xFFFF, sum = 0
1511 23:03:15.635783 6, 0xFFFF, sum = 0
1512 23:03:15.638875 7, 0xFFFF, sum = 0
1513 23:03:15.638961 8, 0x0, sum = 1
1514 23:03:15.642065 9, 0x0, sum = 2
1515 23:03:15.642150 10, 0x0, sum = 3
1516 23:03:15.645453 11, 0x0, sum = 4
1517 23:03:15.645540 best_step = 9
1518 23:03:15.645608
1519 23:03:15.645668 ==
1520 23:03:15.648900 Dram Type= 6, Freq= 0, CH_1, rank 0
1521 23:03:15.655363 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1522 23:03:15.655456 ==
1523 23:03:15.655524 RX Vref Scan: 1
1524 23:03:15.655586
1525 23:03:15.658596 Set Vref Range= 32 -> 127
1526 23:03:15.658682
1527 23:03:15.661966 RX Vref 32 -> 127, step: 1
1528 23:03:15.662053
1529 23:03:15.662121 RX Delay -111 -> 252, step: 8
1530 23:03:15.662185
1531 23:03:15.665661 Set Vref, RX VrefLevel [Byte0]: 32
1532 23:03:15.668811 [Byte1]: 32
1533 23:03:15.672726
1534 23:03:15.672815 Set Vref, RX VrefLevel [Byte0]: 33
1535 23:03:15.676147 [Byte1]: 33
1536 23:03:15.680442
1537 23:03:15.680549 Set Vref, RX VrefLevel [Byte0]: 34
1538 23:03:15.683937 [Byte1]: 34
1539 23:03:15.688184
1540 23:03:15.688272 Set Vref, RX VrefLevel [Byte0]: 35
1541 23:03:15.691492 [Byte1]: 35
1542 23:03:15.695779
1543 23:03:15.695867 Set Vref, RX VrefLevel [Byte0]: 36
1544 23:03:15.699152 [Byte1]: 36
1545 23:03:15.703317
1546 23:03:15.703405 Set Vref, RX VrefLevel [Byte0]: 37
1547 23:03:15.706813 [Byte1]: 37
1548 23:03:15.711066
1549 23:03:15.711155 Set Vref, RX VrefLevel [Byte0]: 38
1550 23:03:15.714613 [Byte1]: 38
1551 23:03:15.718739
1552 23:03:15.718828 Set Vref, RX VrefLevel [Byte0]: 39
1553 23:03:15.722196 [Byte1]: 39
1554 23:03:15.726467
1555 23:03:15.726560 Set Vref, RX VrefLevel [Byte0]: 40
1556 23:03:15.729815 [Byte1]: 40
1557 23:03:15.734111
1558 23:03:15.734208 Set Vref, RX VrefLevel [Byte0]: 41
1559 23:03:15.737285 [Byte1]: 41
1560 23:03:15.741563
1561 23:03:15.741655 Set Vref, RX VrefLevel [Byte0]: 42
1562 23:03:15.744896 [Byte1]: 42
1563 23:03:15.749444
1564 23:03:15.749533 Set Vref, RX VrefLevel [Byte0]: 43
1565 23:03:15.752566 [Byte1]: 43
1566 23:03:15.756904
1567 23:03:15.756992 Set Vref, RX VrefLevel [Byte0]: 44
1568 23:03:15.760149 [Byte1]: 44
1569 23:03:15.764561
1570 23:03:15.764662 Set Vref, RX VrefLevel [Byte0]: 45
1571 23:03:15.767885 [Byte1]: 45
1572 23:03:15.772174
1573 23:03:15.772262 Set Vref, RX VrefLevel [Byte0]: 46
1574 23:03:15.775749 [Byte1]: 46
1575 23:03:15.779928
1576 23:03:15.780017 Set Vref, RX VrefLevel [Byte0]: 47
1577 23:03:15.783242 [Byte1]: 47
1578 23:03:15.787479
1579 23:03:15.787564 Set Vref, RX VrefLevel [Byte0]: 48
1580 23:03:15.790842 [Byte1]: 48
1581 23:03:15.795316
1582 23:03:15.795404 Set Vref, RX VrefLevel [Byte0]: 49
1583 23:03:15.798557 [Byte1]: 49
1584 23:03:15.802890
1585 23:03:15.802975 Set Vref, RX VrefLevel [Byte0]: 50
1586 23:03:15.806079 [Byte1]: 50
1587 23:03:15.810672
1588 23:03:15.810759 Set Vref, RX VrefLevel [Byte0]: 51
1589 23:03:15.814027 [Byte1]: 51
1590 23:03:15.818325
1591 23:03:15.818413 Set Vref, RX VrefLevel [Byte0]: 52
1592 23:03:15.821434 [Byte1]: 52
1593 23:03:15.825973
1594 23:03:15.826086 Set Vref, RX VrefLevel [Byte0]: 53
1595 23:03:15.829285 [Byte1]: 53
1596 23:03:15.833384
1597 23:03:15.833472 Set Vref, RX VrefLevel [Byte0]: 54
1598 23:03:15.836794 [Byte1]: 54
1599 23:03:15.841130
1600 23:03:15.841223 Set Vref, RX VrefLevel [Byte0]: 55
1601 23:03:15.844383 [Byte1]: 55
1602 23:03:15.848546
1603 23:03:15.848680 Set Vref, RX VrefLevel [Byte0]: 56
1604 23:03:15.852112 [Byte1]: 56
1605 23:03:15.856214
1606 23:03:15.856307 Set Vref, RX VrefLevel [Byte0]: 57
1607 23:03:15.859572 [Byte1]: 57
1608 23:03:15.863943
1609 23:03:15.864034 Set Vref, RX VrefLevel [Byte0]: 58
1610 23:03:15.867263 [Byte1]: 58
1611 23:03:15.871502
1612 23:03:15.871589 Set Vref, RX VrefLevel [Byte0]: 59
1613 23:03:15.875017 [Byte1]: 59
1614 23:03:15.879348
1615 23:03:15.879436 Set Vref, RX VrefLevel [Byte0]: 60
1616 23:03:15.882543 [Byte1]: 60
1617 23:03:15.886904
1618 23:03:15.886994 Set Vref, RX VrefLevel [Byte0]: 61
1619 23:03:15.890440 [Byte1]: 61
1620 23:03:15.894513
1621 23:03:15.894600 Set Vref, RX VrefLevel [Byte0]: 62
1622 23:03:15.897790 [Byte1]: 62
1623 23:03:15.902080
1624 23:03:15.902167 Set Vref, RX VrefLevel [Byte0]: 63
1625 23:03:15.905590 [Byte1]: 63
1626 23:03:15.909882
1627 23:03:15.909969 Set Vref, RX VrefLevel [Byte0]: 64
1628 23:03:15.913134 [Byte1]: 64
1629 23:03:15.917596
1630 23:03:15.917683 Set Vref, RX VrefLevel [Byte0]: 65
1631 23:03:15.920920 [Byte1]: 65
1632 23:03:15.925163
1633 23:03:15.925259 Set Vref, RX VrefLevel [Byte0]: 66
1634 23:03:15.928474 [Byte1]: 66
1635 23:03:15.932767
1636 23:03:15.932857 Set Vref, RX VrefLevel [Byte0]: 67
1637 23:03:15.936106 [Byte1]: 67
1638 23:03:15.940294
1639 23:03:15.940385 Set Vref, RX VrefLevel [Byte0]: 68
1640 23:03:15.943655 [Byte1]: 68
1641 23:03:15.948035
1642 23:03:15.948127 Set Vref, RX VrefLevel [Byte0]: 69
1643 23:03:15.951762 [Byte1]: 69
1644 23:03:15.956037
1645 23:03:15.956124 Set Vref, RX VrefLevel [Byte0]: 70
1646 23:03:15.958899 [Byte1]: 70
1647 23:03:15.963386
1648 23:03:15.963478 Set Vref, RX VrefLevel [Byte0]: 71
1649 23:03:15.966543 [Byte1]: 71
1650 23:03:15.971020
1651 23:03:15.971110 Set Vref, RX VrefLevel [Byte0]: 72
1652 23:03:15.974512 [Byte1]: 72
1653 23:03:15.978755
1654 23:03:15.978845 Set Vref, RX VrefLevel [Byte0]: 73
1655 23:03:15.981864 [Byte1]: 73
1656 23:03:15.986430
1657 23:03:15.986527 Set Vref, RX VrefLevel [Byte0]: 74
1658 23:03:15.989735 [Byte1]: 74
1659 23:03:15.993970
1660 23:03:15.994062 Final RX Vref Byte 0 = 59 to rank0
1661 23:03:15.997198 Final RX Vref Byte 1 = 54 to rank0
1662 23:03:16.000609 Final RX Vref Byte 0 = 59 to rank1
1663 23:03:16.003968 Final RX Vref Byte 1 = 54 to rank1==
1664 23:03:16.007503 Dram Type= 6, Freq= 0, CH_1, rank 0
1665 23:03:16.010756 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1666 23:03:16.014353 ==
1667 23:03:16.014440 DQS Delay:
1668 23:03:16.014507 DQS0 = 0, DQS1 = 0
1669 23:03:16.017511 DQM Delay:
1670 23:03:16.017594 DQM0 = 80, DQM1 = 72
1671 23:03:16.020551 DQ Delay:
1672 23:03:16.023883 DQ0 =84, DQ1 =76, DQ2 =72, DQ3 =76
1673 23:03:16.023974 DQ4 =76, DQ5 =92, DQ6 =88, DQ7 =76
1674 23:03:16.027709 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =64
1675 23:03:16.031285 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =80
1676 23:03:16.031383
1677 23:03:16.031452
1678 23:03:16.041465 [DQSOSCAuto] RK0, (LSB)MR18= 0x4e4e, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
1679 23:03:16.044542 CH1 RK0: MR19=606, MR18=4E4E
1680 23:03:16.048531 CH1_RK0: MR19=0x606, MR18=0x4E4E, DQSOSC=390, MR23=63, INC=97, DEC=64
1681 23:03:16.048625
1682 23:03:16.051521 ----->DramcWriteLeveling(PI) begin...
1683 23:03:16.054929 ==
1684 23:03:16.058488 Dram Type= 6, Freq= 0, CH_1, rank 1
1685 23:03:16.061475 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1686 23:03:16.061563 ==
1687 23:03:16.064730 Write leveling (Byte 0): 25 => 25
1688 23:03:16.068410 Write leveling (Byte 1): 25 => 25
1689 23:03:16.071550 DramcWriteLeveling(PI) end<-----
1690 23:03:16.071656
1691 23:03:16.071751 ==
1692 23:03:16.074794 Dram Type= 6, Freq= 0, CH_1, rank 1
1693 23:03:16.077991 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1694 23:03:16.078077 ==
1695 23:03:16.081286 [Gating] SW mode calibration
1696 23:03:16.088119 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1697 23:03:16.094497 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1698 23:03:16.097857 0 6 0 | B1->B0 | 2b2b 2323 | 0 0 | (1 1) (0 0)
1699 23:03:16.101162 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1700 23:03:16.104652 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1701 23:03:16.111218 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1702 23:03:16.114405 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1703 23:03:16.117652 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1704 23:03:16.124402 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1705 23:03:16.127562 0 6 28 | B1->B0 | 2424 3434 | 0 0 | (0 0) (0 0)
1706 23:03:16.131060 0 7 0 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
1707 23:03:16.137580 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1708 23:03:16.140924 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1709 23:03:16.144410 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1710 23:03:16.151026 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1711 23:03:16.153976 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1712 23:03:16.157357 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1713 23:03:16.163984 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1714 23:03:16.167559 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1715 23:03:16.170727 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1716 23:03:16.177443 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1717 23:03:16.180957 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1718 23:03:16.183963 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1719 23:03:16.190676 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1720 23:03:16.194025 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1721 23:03:16.197523 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1722 23:03:16.204115 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1723 23:03:16.207486 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1724 23:03:16.210728 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1725 23:03:16.217509 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1726 23:03:16.220849 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1727 23:03:16.224040 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1728 23:03:16.230766 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1729 23:03:16.234056 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1730 23:03:16.237406 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1731 23:03:16.240783 Total UI for P1: 0, mck2ui 16
1732 23:03:16.244242 best dqsien dly found for B0: ( 0, 9, 28)
1733 23:03:16.247375 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1734 23:03:16.250613 Total UI for P1: 0, mck2ui 16
1735 23:03:16.254034 best dqsien dly found for B1: ( 0, 10, 0)
1736 23:03:16.257441 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1737 23:03:16.264017 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1738 23:03:16.264129
1739 23:03:16.267551 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1740 23:03:16.270683 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1741 23:03:16.274117 [Gating] SW calibration Done
1742 23:03:16.274208 ==
1743 23:03:16.277312 Dram Type= 6, Freq= 0, CH_1, rank 1
1744 23:03:16.280800 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1745 23:03:16.280886 ==
1746 23:03:16.280952 RX Vref Scan: 0
1747 23:03:16.284066
1748 23:03:16.284150 RX Vref 0 -> 0, step: 1
1749 23:03:16.284216
1750 23:03:16.287318 RX Delay -130 -> 252, step: 16
1751 23:03:16.290647 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1752 23:03:16.293864 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1753 23:03:16.300491 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1754 23:03:16.304027 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1755 23:03:16.307294 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1756 23:03:16.310875 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1757 23:03:16.313952 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1758 23:03:16.320790 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1759 23:03:16.324004 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1760 23:03:16.327208 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1761 23:03:16.330892 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1762 23:03:16.333879 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1763 23:03:16.340701 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1764 23:03:16.343738 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1765 23:03:16.347352 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1766 23:03:16.350721 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1767 23:03:16.350810 ==
1768 23:03:16.353978 Dram Type= 6, Freq= 0, CH_1, rank 1
1769 23:03:16.360691 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1770 23:03:16.360795 ==
1771 23:03:16.360865 DQS Delay:
1772 23:03:16.364023 DQS0 = 0, DQS1 = 0
1773 23:03:16.364108 DQM Delay:
1774 23:03:16.364175 DQM0 = 82, DQM1 = 71
1775 23:03:16.367421 DQ Delay:
1776 23:03:16.370493 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1777 23:03:16.374018 DQ4 =85, DQ5 =93, DQ6 =85, DQ7 =77
1778 23:03:16.377074 DQ8 =53, DQ9 =61, DQ10 =69, DQ11 =61
1779 23:03:16.380481 DQ12 =77, DQ13 =85, DQ14 =77, DQ15 =85
1780 23:03:16.380583
1781 23:03:16.380651
1782 23:03:16.380713 ==
1783 23:03:16.383735 Dram Type= 6, Freq= 0, CH_1, rank 1
1784 23:03:16.387278 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1785 23:03:16.387366 ==
1786 23:03:16.387434
1787 23:03:16.387495
1788 23:03:16.390449 TX Vref Scan disable
1789 23:03:16.390533 == TX Byte 0 ==
1790 23:03:16.397348 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1791 23:03:16.400756 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1792 23:03:16.400848 == TX Byte 1 ==
1793 23:03:16.407150 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1794 23:03:16.410677 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1795 23:03:16.410770 ==
1796 23:03:16.413702 Dram Type= 6, Freq= 0, CH_1, rank 1
1797 23:03:16.416932 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1798 23:03:16.417020 ==
1799 23:03:16.430763 TX Vref=22, minBit 12, minWin=27, winSum=448
1800 23:03:16.433990 TX Vref=24, minBit 0, minWin=28, winSum=452
1801 23:03:16.437858 TX Vref=26, minBit 0, minWin=28, winSum=456
1802 23:03:16.440652 TX Vref=28, minBit 0, minWin=28, winSum=459
1803 23:03:16.444130 TX Vref=30, minBit 0, minWin=28, winSum=458
1804 23:03:16.450871 TX Vref=32, minBit 9, minWin=27, winSum=453
1805 23:03:16.454059 [TxChooseVref] Worse bit 0, Min win 28, Win sum 459, Final Vref 28
1806 23:03:16.454154
1807 23:03:16.457428 Final TX Range 1 Vref 28
1808 23:03:16.457515
1809 23:03:16.457581 ==
1810 23:03:16.460693 Dram Type= 6, Freq= 0, CH_1, rank 1
1811 23:03:16.463877 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1812 23:03:16.463962 ==
1813 23:03:16.467380
1814 23:03:16.467463
1815 23:03:16.467528 TX Vref Scan disable
1816 23:03:16.470709 == TX Byte 0 ==
1817 23:03:16.474016 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1818 23:03:16.477951 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1819 23:03:16.480869 == TX Byte 1 ==
1820 23:03:16.484297 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1821 23:03:16.487522 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1822 23:03:16.487611
1823 23:03:16.491006 [DATLAT]
1824 23:03:16.491092 Freq=800, CH1 RK1
1825 23:03:16.491161
1826 23:03:16.494335 DATLAT Default: 0x9
1827 23:03:16.494419 0, 0xFFFF, sum = 0
1828 23:03:16.497620 1, 0xFFFF, sum = 0
1829 23:03:16.497705 2, 0xFFFF, sum = 0
1830 23:03:16.500980 3, 0xFFFF, sum = 0
1831 23:03:16.501068 4, 0xFFFF, sum = 0
1832 23:03:16.504262 5, 0xFFFF, sum = 0
1833 23:03:16.504347 6, 0xFFFF, sum = 0
1834 23:03:16.507763 7, 0xFFFF, sum = 0
1835 23:03:16.507850 8, 0x0, sum = 1
1836 23:03:16.511096 9, 0x0, sum = 2
1837 23:03:16.511184 10, 0x0, sum = 3
1838 23:03:16.514239 11, 0x0, sum = 4
1839 23:03:16.514325 best_step = 9
1840 23:03:16.514391
1841 23:03:16.514453 ==
1842 23:03:16.517523 Dram Type= 6, Freq= 0, CH_1, rank 1
1843 23:03:16.520867 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1844 23:03:16.524281 ==
1845 23:03:16.524398 RX Vref Scan: 0
1846 23:03:16.524494
1847 23:03:16.527632 RX Vref 0 -> 0, step: 1
1848 23:03:16.527717
1849 23:03:16.530892 RX Delay -111 -> 252, step: 8
1850 23:03:16.534143 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1851 23:03:16.537451 iDelay=217, Bit 1, Center 76 (-39 ~ 192) 232
1852 23:03:16.540854 iDelay=217, Bit 2, Center 72 (-47 ~ 192) 240
1853 23:03:16.547521 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1854 23:03:16.550789 iDelay=217, Bit 4, Center 80 (-39 ~ 200) 240
1855 23:03:16.554066 iDelay=217, Bit 5, Center 96 (-23 ~ 216) 240
1856 23:03:16.557453 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1857 23:03:16.560717 iDelay=217, Bit 7, Center 80 (-39 ~ 200) 240
1858 23:03:16.567489 iDelay=217, Bit 8, Center 56 (-63 ~ 176) 240
1859 23:03:16.570775 iDelay=217, Bit 9, Center 60 (-63 ~ 184) 248
1860 23:03:16.574324 iDelay=217, Bit 10, Center 72 (-47 ~ 192) 240
1861 23:03:16.577495 iDelay=217, Bit 11, Center 64 (-55 ~ 184) 240
1862 23:03:16.580866 iDelay=217, Bit 12, Center 80 (-39 ~ 200) 240
1863 23:03:16.587507 iDelay=217, Bit 13, Center 80 (-39 ~ 200) 240
1864 23:03:16.590991 iDelay=217, Bit 14, Center 80 (-39 ~ 200) 240
1865 23:03:16.594068 iDelay=217, Bit 15, Center 80 (-39 ~ 200) 240
1866 23:03:16.594155 ==
1867 23:03:16.597488 Dram Type= 6, Freq= 0, CH_1, rank 1
1868 23:03:16.601029 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1869 23:03:16.604204 ==
1870 23:03:16.604290 DQS Delay:
1871 23:03:16.604355 DQS0 = 0, DQS1 = 0
1872 23:03:16.607424 DQM Delay:
1873 23:03:16.607508 DQM0 = 82, DQM1 = 71
1874 23:03:16.610781 DQ Delay:
1875 23:03:16.610864 DQ0 =84, DQ1 =76, DQ2 =72, DQ3 =80
1876 23:03:16.614251 DQ4 =80, DQ5 =96, DQ6 =92, DQ7 =80
1877 23:03:16.617526 DQ8 =56, DQ9 =60, DQ10 =72, DQ11 =64
1878 23:03:16.620762 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =80
1879 23:03:16.620851
1880 23:03:16.620916
1881 23:03:16.630890 [DQSOSCAuto] RK1, (LSB)MR18= 0x4242, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
1882 23:03:16.634313 CH1 RK1: MR19=606, MR18=4242
1883 23:03:16.640795 CH1_RK1: MR19=0x606, MR18=0x4242, DQSOSC=393, MR23=63, INC=95, DEC=63
1884 23:03:16.640911 [RxdqsGatingPostProcess] freq 800
1885 23:03:16.647426 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1886 23:03:16.650780 Pre-setting of DQS Precalculation
1887 23:03:16.654198 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1888 23:03:16.664098 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1889 23:03:16.670653 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1890 23:03:16.670766
1891 23:03:16.670833
1892 23:03:16.674173 [Calibration Summary] 1600 Mbps
1893 23:03:16.674258 CH 0, Rank 0
1894 23:03:16.677303 SW Impedance : PASS
1895 23:03:16.677386 DUTY Scan : NO K
1896 23:03:16.680774 ZQ Calibration : PASS
1897 23:03:16.683987 Jitter Meter : NO K
1898 23:03:16.684072 CBT Training : PASS
1899 23:03:16.687332 Write leveling : PASS
1900 23:03:16.690763 RX DQS gating : PASS
1901 23:03:16.690851 RX DQ/DQS(RDDQC) : PASS
1902 23:03:16.694062 TX DQ/DQS : PASS
1903 23:03:16.697383 RX DATLAT : PASS
1904 23:03:16.697471 RX DQ/DQS(Engine): PASS
1905 23:03:16.700637 TX OE : NO K
1906 23:03:16.700721 All Pass.
1907 23:03:16.700787
1908 23:03:16.704025 CH 0, Rank 1
1909 23:03:16.704108 SW Impedance : PASS
1910 23:03:16.707374 DUTY Scan : NO K
1911 23:03:16.707458 ZQ Calibration : PASS
1912 23:03:16.710750 Jitter Meter : NO K
1913 23:03:16.713934 CBT Training : PASS
1914 23:03:16.714018 Write leveling : PASS
1915 23:03:16.717403 RX DQS gating : PASS
1916 23:03:16.720896 RX DQ/DQS(RDDQC) : PASS
1917 23:03:16.720982 TX DQ/DQS : PASS
1918 23:03:16.723971 RX DATLAT : PASS
1919 23:03:16.727704 RX DQ/DQS(Engine): PASS
1920 23:03:16.727857 TX OE : NO K
1921 23:03:16.730962 All Pass.
1922 23:03:16.731046
1923 23:03:16.731111 CH 1, Rank 0
1924 23:03:16.733936 SW Impedance : PASS
1925 23:03:16.734019 DUTY Scan : NO K
1926 23:03:16.737289 ZQ Calibration : PASS
1927 23:03:16.740552 Jitter Meter : NO K
1928 23:03:16.740652 CBT Training : PASS
1929 23:03:16.743989 Write leveling : PASS
1930 23:03:16.747345 RX DQS gating : PASS
1931 23:03:16.747429 RX DQ/DQS(RDDQC) : PASS
1932 23:03:16.750893 TX DQ/DQS : PASS
1933 23:03:16.750979 RX DATLAT : PASS
1934 23:03:16.754164 RX DQ/DQS(Engine): PASS
1935 23:03:16.757377 TX OE : NO K
1936 23:03:16.757464 All Pass.
1937 23:03:16.757529
1938 23:03:16.757590 CH 1, Rank 1
1939 23:03:16.760655 SW Impedance : PASS
1940 23:03:16.764033 DUTY Scan : NO K
1941 23:03:16.764119 ZQ Calibration : PASS
1942 23:03:16.767419 Jitter Meter : NO K
1943 23:03:16.770925 CBT Training : PASS
1944 23:03:16.771012 Write leveling : PASS
1945 23:03:16.774045 RX DQS gating : PASS
1946 23:03:16.777387 RX DQ/DQS(RDDQC) : PASS
1947 23:03:16.777472 TX DQ/DQS : PASS
1948 23:03:16.780605 RX DATLAT : PASS
1949 23:03:16.784074 RX DQ/DQS(Engine): PASS
1950 23:03:16.784167 TX OE : NO K
1951 23:03:16.784235 All Pass.
1952 23:03:16.787351
1953 23:03:16.787437 DramC Write-DBI off
1954 23:03:16.790769 PER_BANK_REFRESH: Hybrid Mode
1955 23:03:16.790853 TX_TRACKING: ON
1956 23:03:16.794062 [GetDramInforAfterCalByMRR] Vendor 6.
1957 23:03:16.797382 [GetDramInforAfterCalByMRR] Revision 606.
1958 23:03:16.803958 [GetDramInforAfterCalByMRR] Revision 2 0.
1959 23:03:16.804060 MR0 0x3939
1960 23:03:16.804130 MR8 0x1111
1961 23:03:16.807632 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
1962 23:03:16.807717
1963 23:03:16.810758 MR0 0x3939
1964 23:03:16.810842 MR8 0x1111
1965 23:03:16.814051 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
1966 23:03:16.814136
1967 23:03:16.823912 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
1968 23:03:16.827233 [FAST_K] Save calibration result to emmc
1969 23:03:16.830658 [FAST_K] Save calibration result to emmc
1970 23:03:16.833923 dram_init: config_dvfs: 1
1971 23:03:16.837350 dramc_set_vcore_voltage set vcore to 662500
1972 23:03:16.837445 Read voltage for 1200, 2
1973 23:03:16.840750 Vio18 = 0
1974 23:03:16.840841 Vcore = 662500
1975 23:03:16.840909 Vdram = 0
1976 23:03:16.843981 Vddq = 0
1977 23:03:16.844064 Vmddr = 0
1978 23:03:16.850623 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
1979 23:03:16.853925 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
1980 23:03:16.857430 MEM_TYPE=3, freq_sel=15
1981 23:03:16.860989 sv_algorithm_assistance_LP4_1600
1982 23:03:16.864002 ============ PULL DRAM RESETB DOWN ============
1983 23:03:16.867366 ========== PULL DRAM RESETB DOWN end =========
1984 23:03:16.873950 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
1985 23:03:16.877334 ===================================
1986 23:03:16.877428 LPDDR4 DRAM CONFIGURATION
1987 23:03:16.881033 ===================================
1988 23:03:16.884241 EX_ROW_EN[0] = 0x0
1989 23:03:16.884326 EX_ROW_EN[1] = 0x0
1990 23:03:16.887474 LP4Y_EN = 0x0
1991 23:03:16.887563 WORK_FSP = 0x0
1992 23:03:16.890782 WL = 0x4
1993 23:03:16.890869 RL = 0x4
1994 23:03:16.894086 BL = 0x2
1995 23:03:16.897376 RPST = 0x0
1996 23:03:16.897462 RD_PRE = 0x0
1997 23:03:16.900843 WR_PRE = 0x1
1998 23:03:16.900930 WR_PST = 0x0
1999 23:03:16.904186 DBI_WR = 0x0
2000 23:03:16.904270 DBI_RD = 0x0
2001 23:03:16.907596 OTF = 0x1
2002 23:03:16.910841 ===================================
2003 23:03:16.914003 ===================================
2004 23:03:16.914090 ANA top config
2005 23:03:16.917360 ===================================
2006 23:03:16.920794 DLL_ASYNC_EN = 0
2007 23:03:16.923832 ALL_SLAVE_EN = 0
2008 23:03:16.923926 NEW_RANK_MODE = 1
2009 23:03:16.927337 DLL_IDLE_MODE = 1
2010 23:03:16.930446 LP45_APHY_COMB_EN = 1
2011 23:03:16.933791 TX_ODT_DIS = 1
2012 23:03:16.933911 NEW_8X_MODE = 1
2013 23:03:16.937159 ===================================
2014 23:03:16.940570 ===================================
2015 23:03:16.943896 data_rate = 2400
2016 23:03:16.947155 CKR = 1
2017 23:03:16.950456 DQ_P2S_RATIO = 8
2018 23:03:16.953730 ===================================
2019 23:03:16.957206 CA_P2S_RATIO = 8
2020 23:03:16.960389 DQ_CA_OPEN = 0
2021 23:03:16.960478 DQ_SEMI_OPEN = 0
2022 23:03:16.963696 CA_SEMI_OPEN = 0
2023 23:03:16.966978 CA_FULL_RATE = 0
2024 23:03:16.970791 DQ_CKDIV4_EN = 0
2025 23:03:16.973838 CA_CKDIV4_EN = 0
2026 23:03:16.977250 CA_PREDIV_EN = 0
2027 23:03:16.977339 PH8_DLY = 17
2028 23:03:16.980364 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2029 23:03:16.983596 DQ_AAMCK_DIV = 4
2030 23:03:16.986981 CA_AAMCK_DIV = 4
2031 23:03:16.990467 CA_ADMCK_DIV = 4
2032 23:03:16.993531 DQ_TRACK_CA_EN = 0
2033 23:03:16.997012 CA_PICK = 1200
2034 23:03:16.997097 CA_MCKIO = 1200
2035 23:03:17.000586 MCKIO_SEMI = 0
2036 23:03:17.003751 PLL_FREQ = 2366
2037 23:03:17.006914 DQ_UI_PI_RATIO = 32
2038 23:03:17.010343 CA_UI_PI_RATIO = 0
2039 23:03:17.013714 ===================================
2040 23:03:17.017019 ===================================
2041 23:03:17.020236 memory_type:LPDDR4
2042 23:03:17.020321 GP_NUM : 10
2043 23:03:17.024004 SRAM_EN : 1
2044 23:03:17.024090 MD32_EN : 0
2045 23:03:17.027210 ===================================
2046 23:03:17.030338 [ANA_INIT] >>>>>>>>>>>>>>
2047 23:03:17.033761 <<<<<< [CONFIGURE PHASE]: ANA_TX
2048 23:03:17.037092 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2049 23:03:17.040258 ===================================
2050 23:03:17.043685 data_rate = 2400,PCW = 0X5b00
2051 23:03:17.047154 ===================================
2052 23:03:17.050551 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2053 23:03:17.053648 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2054 23:03:17.060373 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2055 23:03:17.063680 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2056 23:03:17.067155 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2057 23:03:17.073794 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2058 23:03:17.073894 [ANA_INIT] flow start
2059 23:03:17.077143 [ANA_INIT] PLL >>>>>>>>
2060 23:03:17.077236 [ANA_INIT] PLL <<<<<<<<
2061 23:03:17.080413 [ANA_INIT] MIDPI >>>>>>>>
2062 23:03:17.083918 [ANA_INIT] MIDPI <<<<<<<<
2063 23:03:17.087039 [ANA_INIT] DLL >>>>>>>>
2064 23:03:17.087127 [ANA_INIT] DLL <<<<<<<<
2065 23:03:17.090329 [ANA_INIT] flow end
2066 23:03:17.094015 ============ LP4 DIFF to SE enter ============
2067 23:03:17.097111 ============ LP4 DIFF to SE exit ============
2068 23:03:17.100457 [ANA_INIT] <<<<<<<<<<<<<
2069 23:03:17.103894 [Flow] Enable top DCM control >>>>>
2070 23:03:17.107091 [Flow] Enable top DCM control <<<<<
2071 23:03:17.110647 Enable DLL master slave shuffle
2072 23:03:17.117115 ==============================================================
2073 23:03:17.117222 Gating Mode config
2074 23:03:17.123887 ==============================================================
2075 23:03:17.123990 Config description:
2076 23:03:17.133768 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2077 23:03:17.140432 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2078 23:03:17.147031 SELPH_MODE 0: By rank 1: By Phase
2079 23:03:17.150349 ==============================================================
2080 23:03:17.153677 GAT_TRACK_EN = 1
2081 23:03:17.157020 RX_GATING_MODE = 2
2082 23:03:17.160350 RX_GATING_TRACK_MODE = 2
2083 23:03:17.163777 SELPH_MODE = 1
2084 23:03:17.166951 PICG_EARLY_EN = 1
2085 23:03:17.170422 VALID_LAT_VALUE = 1
2086 23:03:17.173807 ==============================================================
2087 23:03:17.177204 Enter into Gating configuration >>>>
2088 23:03:17.180466 Exit from Gating configuration <<<<
2089 23:03:17.183600 Enter into DVFS_PRE_config >>>>>
2090 23:03:17.197184 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2091 23:03:17.200587 Exit from DVFS_PRE_config <<<<<
2092 23:03:17.200690 Enter into PICG configuration >>>>
2093 23:03:17.203756 Exit from PICG configuration <<<<
2094 23:03:17.207081 [RX_INPUT] configuration >>>>>
2095 23:03:17.210525 [RX_INPUT] configuration <<<<<
2096 23:03:17.217099 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2097 23:03:17.220404 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2098 23:03:17.227167 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2099 23:03:17.233646 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2100 23:03:17.240482 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2101 23:03:17.246882 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2102 23:03:17.250236 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2103 23:03:17.253884 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2104 23:03:17.257016 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2105 23:03:17.263691 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2106 23:03:17.267021 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2107 23:03:17.270489 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2108 23:03:17.273798 ===================================
2109 23:03:17.276923 LPDDR4 DRAM CONFIGURATION
2110 23:03:17.280319 ===================================
2111 23:03:17.280419 EX_ROW_EN[0] = 0x0
2112 23:03:17.283692 EX_ROW_EN[1] = 0x0
2113 23:03:17.286999 LP4Y_EN = 0x0
2114 23:03:17.287088 WORK_FSP = 0x0
2115 23:03:17.290347 WL = 0x4
2116 23:03:17.290432 RL = 0x4
2117 23:03:17.293807 BL = 0x2
2118 23:03:17.293892 RPST = 0x0
2119 23:03:17.297026 RD_PRE = 0x0
2120 23:03:17.297111 WR_PRE = 0x1
2121 23:03:17.300573 WR_PST = 0x0
2122 23:03:17.300657 DBI_WR = 0x0
2123 23:03:17.303506 DBI_RD = 0x0
2124 23:03:17.303591 OTF = 0x1
2125 23:03:17.306840 ===================================
2126 23:03:17.310292 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2127 23:03:17.317075 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2128 23:03:17.320268 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2129 23:03:17.323726 ===================================
2130 23:03:17.326972 LPDDR4 DRAM CONFIGURATION
2131 23:03:17.330399 ===================================
2132 23:03:17.330496 EX_ROW_EN[0] = 0x10
2133 23:03:17.333753 EX_ROW_EN[1] = 0x0
2134 23:03:17.333841 LP4Y_EN = 0x0
2135 23:03:17.336671 WORK_FSP = 0x0
2136 23:03:17.339813 WL = 0x4
2137 23:03:17.339903 RL = 0x4
2138 23:03:17.343479 BL = 0x2
2139 23:03:17.343565 RPST = 0x0
2140 23:03:17.346581 RD_PRE = 0x0
2141 23:03:17.346666 WR_PRE = 0x1
2142 23:03:17.350114 WR_PST = 0x0
2143 23:03:17.350202 DBI_WR = 0x0
2144 23:03:17.353469 DBI_RD = 0x0
2145 23:03:17.353554 OTF = 0x1
2146 23:03:17.356688 ===================================
2147 23:03:17.363185 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2148 23:03:17.363285 ==
2149 23:03:17.366492 Dram Type= 6, Freq= 0, CH_0, rank 0
2150 23:03:17.369868 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2151 23:03:17.369955 ==
2152 23:03:17.373252 [Duty_Offset_Calibration]
2153 23:03:17.376683 B0:0 B1:2 CA:1
2154 23:03:17.376771
2155 23:03:17.379728 [DutyScan_Calibration_Flow] k_type=0
2156 23:03:17.388272
2157 23:03:17.388424 ==CLK 0==
2158 23:03:17.391289 Final CLK duty delay cell = 0
2159 23:03:17.394595 [0] MAX Duty = 5093%(X100), DQS PI = 12
2160 23:03:17.398199 [0] MIN Duty = 4938%(X100), DQS PI = 52
2161 23:03:17.398291 [0] AVG Duty = 5015%(X100)
2162 23:03:17.401296
2163 23:03:17.404656 CH0 CLK Duty spec in!! Max-Min= 155%
2164 23:03:17.407875 [DutyScan_Calibration_Flow] ====Done====
2165 23:03:17.407964
2166 23:03:17.411227 [DutyScan_Calibration_Flow] k_type=1
2167 23:03:17.427392
2168 23:03:17.427548 ==DQS 0 ==
2169 23:03:17.430732 Final DQS duty delay cell = 0
2170 23:03:17.434136 [0] MAX Duty = 5125%(X100), DQS PI = 20
2171 23:03:17.437397 [0] MIN Duty = 5031%(X100), DQS PI = 6
2172 23:03:17.437491 [0] AVG Duty = 5078%(X100)
2173 23:03:17.440869
2174 23:03:17.440957 ==DQS 1 ==
2175 23:03:17.444211 Final DQS duty delay cell = 0
2176 23:03:17.447275 [0] MAX Duty = 5062%(X100), DQS PI = 58
2177 23:03:17.450685 [0] MIN Duty = 4906%(X100), DQS PI = 16
2178 23:03:17.454012 [0] AVG Duty = 4984%(X100)
2179 23:03:17.454102
2180 23:03:17.457347 CH0 DQS 0 Duty spec in!! Max-Min= 94%
2181 23:03:17.457434
2182 23:03:17.460568 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2183 23:03:17.463861 [DutyScan_Calibration_Flow] ====Done====
2184 23:03:17.463948
2185 23:03:17.467030 [DutyScan_Calibration_Flow] k_type=3
2186 23:03:17.483763
2187 23:03:17.483908 ==DQM 0 ==
2188 23:03:17.486946 Final DQM duty delay cell = 0
2189 23:03:17.490479 [0] MAX Duty = 5156%(X100), DQS PI = 20
2190 23:03:17.493683 [0] MIN Duty = 4969%(X100), DQS PI = 40
2191 23:03:17.493775 [0] AVG Duty = 5062%(X100)
2192 23:03:17.497240
2193 23:03:17.497326 ==DQM 1 ==
2194 23:03:17.500765 Final DQM duty delay cell = 0
2195 23:03:17.503867 [0] MAX Duty = 5000%(X100), DQS PI = 56
2196 23:03:17.507189 [0] MIN Duty = 4844%(X100), DQS PI = 2
2197 23:03:17.507277 [0] AVG Duty = 4922%(X100)
2198 23:03:17.507344
2199 23:03:17.513682 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2200 23:03:17.513774
2201 23:03:17.517066 CH0 DQM 1 Duty spec in!! Max-Min= 156%
2202 23:03:17.520439 [DutyScan_Calibration_Flow] ====Done====
2203 23:03:17.520533
2204 23:03:17.523567 [DutyScan_Calibration_Flow] k_type=2
2205 23:03:17.538672
2206 23:03:17.538825 ==DQ 0 ==
2207 23:03:17.541962 Final DQ duty delay cell = -4
2208 23:03:17.545121 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2209 23:03:17.548498 [-4] MIN Duty = 4813%(X100), DQS PI = 54
2210 23:03:17.551740 [-4] AVG Duty = 4937%(X100)
2211 23:03:17.551828
2212 23:03:17.551895 ==DQ 1 ==
2213 23:03:17.555231 Final DQ duty delay cell = -4
2214 23:03:17.558828 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2215 23:03:17.562137 [-4] MIN Duty = 4876%(X100), DQS PI = 62
2216 23:03:17.565052 [-4] AVG Duty = 4969%(X100)
2217 23:03:17.565141
2218 23:03:17.568815 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2219 23:03:17.568901
2220 23:03:17.572213 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2221 23:03:17.575190 [DutyScan_Calibration_Flow] ====Done====
2222 23:03:17.575275 ==
2223 23:03:17.578484 Dram Type= 6, Freq= 0, CH_1, rank 0
2224 23:03:17.581872 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2225 23:03:17.581958 ==
2226 23:03:17.585266 [Duty_Offset_Calibration]
2227 23:03:17.585350 B0:0 B1:5 CA:-5
2228 23:03:17.585416
2229 23:03:17.588727 [DutyScan_Calibration_Flow] k_type=0
2230 23:03:17.599142
2231 23:03:17.599270 ==CLK 0==
2232 23:03:17.602572 Final CLK duty delay cell = 0
2233 23:03:17.605690 [0] MAX Duty = 5094%(X100), DQS PI = 24
2234 23:03:17.609173 [0] MIN Duty = 4875%(X100), DQS PI = 46
2235 23:03:17.609278 [0] AVG Duty = 4984%(X100)
2236 23:03:17.612471
2237 23:03:17.615828 CH1 CLK Duty spec in!! Max-Min= 219%
2238 23:03:17.619256 [DutyScan_Calibration_Flow] ====Done====
2239 23:03:17.619344
2240 23:03:17.622486 [DutyScan_Calibration_Flow] k_type=1
2241 23:03:17.637611
2242 23:03:17.637759 ==DQS 0 ==
2243 23:03:17.641237 Final DQS duty delay cell = 0
2244 23:03:17.644422 [0] MAX Duty = 5125%(X100), DQS PI = 16
2245 23:03:17.647881 [0] MIN Duty = 4875%(X100), DQS PI = 40
2246 23:03:17.650985 [0] AVG Duty = 5000%(X100)
2247 23:03:17.651092
2248 23:03:17.651159 ==DQS 1 ==
2249 23:03:17.654260 Final DQS duty delay cell = -4
2250 23:03:17.657696 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2251 23:03:17.661056 [-4] MIN Duty = 4907%(X100), DQS PI = 58
2252 23:03:17.664245 [-4] AVG Duty = 4969%(X100)
2253 23:03:17.664369
2254 23:03:17.667699 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2255 23:03:17.667785
2256 23:03:17.670892 CH1 DQS 1 Duty spec in!! Max-Min= 124%
2257 23:03:17.674279 [DutyScan_Calibration_Flow] ====Done====
2258 23:03:17.674367
2259 23:03:17.677784 [DutyScan_Calibration_Flow] k_type=3
2260 23:03:17.693040
2261 23:03:17.693201 ==DQM 0 ==
2262 23:03:17.696247 Final DQM duty delay cell = -4
2263 23:03:17.699842 [-4] MAX Duty = 5094%(X100), DQS PI = 32
2264 23:03:17.702921 [-4] MIN Duty = 4844%(X100), DQS PI = 40
2265 23:03:17.706294 [-4] AVG Duty = 4969%(X100)
2266 23:03:17.706383
2267 23:03:17.706448 ==DQM 1 ==
2268 23:03:17.709711 Final DQM duty delay cell = -4
2269 23:03:17.713072 [-4] MAX Duty = 5094%(X100), DQS PI = 20
2270 23:03:17.716377 [-4] MIN Duty = 4906%(X100), DQS PI = 46
2271 23:03:17.719658 [-4] AVG Duty = 5000%(X100)
2272 23:03:17.719747
2273 23:03:17.723128 CH1 DQM 0 Duty spec in!! Max-Min= 250%
2274 23:03:17.723214
2275 23:03:17.726313 CH1 DQM 1 Duty spec in!! Max-Min= 188%
2276 23:03:17.729578 [DutyScan_Calibration_Flow] ====Done====
2277 23:03:17.729682
2278 23:03:17.732845 [DutyScan_Calibration_Flow] k_type=2
2279 23:03:17.750204
2280 23:03:17.750359 ==DQ 0 ==
2281 23:03:17.753429 Final DQ duty delay cell = 0
2282 23:03:17.756795 [0] MAX Duty = 5093%(X100), DQS PI = 32
2283 23:03:17.760206 [0] MIN Duty = 4969%(X100), DQS PI = 44
2284 23:03:17.760296 [0] AVG Duty = 5031%(X100)
2285 23:03:17.763422
2286 23:03:17.763507 ==DQ 1 ==
2287 23:03:17.766778 Final DQ duty delay cell = 0
2288 23:03:17.770254 [0] MAX Duty = 5031%(X100), DQS PI = 8
2289 23:03:17.773683 [0] MIN Duty = 4875%(X100), DQS PI = 44
2290 23:03:17.773770 [0] AVG Duty = 4953%(X100)
2291 23:03:17.773837
2292 23:03:17.777107 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2293 23:03:17.777192
2294 23:03:17.780209 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2295 23:03:17.786869 [DutyScan_Calibration_Flow] ====Done====
2296 23:03:17.790291 nWR fixed to 30
2297 23:03:17.790387 [ModeRegInit_LP4] CH0 RK0
2298 23:03:17.793501 [ModeRegInit_LP4] CH0 RK1
2299 23:03:17.796931 [ModeRegInit_LP4] CH1 RK0
2300 23:03:17.797019 [ModeRegInit_LP4] CH1 RK1
2301 23:03:17.800102 match AC timing 6
2302 23:03:17.803638 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2303 23:03:17.806791 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2304 23:03:17.813439 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2305 23:03:17.816745 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2306 23:03:17.823473 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2307 23:03:17.823572 ==
2308 23:03:17.826971 Dram Type= 6, Freq= 0, CH_0, rank 0
2309 23:03:17.830156 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2310 23:03:17.830251 ==
2311 23:03:17.836782 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2312 23:03:17.840020 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2313 23:03:17.850024 [CA 0] Center 39 (9~70) winsize 62
2314 23:03:17.853377 [CA 1] Center 39 (9~70) winsize 62
2315 23:03:17.856549 [CA 2] Center 36 (5~67) winsize 63
2316 23:03:17.860030 [CA 3] Center 35 (5~66) winsize 62
2317 23:03:17.863177 [CA 4] Center 34 (3~65) winsize 63
2318 23:03:17.866559 [CA 5] Center 33 (3~64) winsize 62
2319 23:03:17.866646
2320 23:03:17.869952 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2321 23:03:17.870035
2322 23:03:17.873305 [CATrainingPosCal] consider 1 rank data
2323 23:03:17.876711 u2DelayCellTimex100 = 270/100 ps
2324 23:03:17.879960 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2325 23:03:17.883273 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2326 23:03:17.890123 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2327 23:03:17.893391 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2328 23:03:17.896926 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
2329 23:03:17.900101 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2330 23:03:17.900188
2331 23:03:17.903619 CA PerBit enable=1, Macro0, CA PI delay=33
2332 23:03:17.903705
2333 23:03:17.906741 [CBTSetCACLKResult] CA Dly = 33
2334 23:03:17.906825 CS Dly: 7 (0~38)
2335 23:03:17.906890 ==
2336 23:03:17.910018 Dram Type= 6, Freq= 0, CH_0, rank 1
2337 23:03:17.916782 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2338 23:03:17.916888 ==
2339 23:03:17.919852 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2340 23:03:17.926633 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2341 23:03:17.935409 [CA 0] Center 39 (8~70) winsize 63
2342 23:03:17.938647 [CA 1] Center 39 (8~70) winsize 63
2343 23:03:17.942305 [CA 2] Center 36 (5~67) winsize 63
2344 23:03:17.945264 [CA 3] Center 35 (4~66) winsize 63
2345 23:03:17.948627 [CA 4] Center 33 (3~64) winsize 62
2346 23:03:17.952042 [CA 5] Center 34 (3~65) winsize 63
2347 23:03:17.952127
2348 23:03:17.955357 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2349 23:03:17.955441
2350 23:03:17.958837 [CATrainingPosCal] consider 2 rank data
2351 23:03:17.962327 u2DelayCellTimex100 = 270/100 ps
2352 23:03:17.965584 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2353 23:03:17.968574 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2354 23:03:17.975365 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2355 23:03:17.978487 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2356 23:03:17.981985 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2357 23:03:17.985141 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2358 23:03:17.985228
2359 23:03:17.988660 CA PerBit enable=1, Macro0, CA PI delay=33
2360 23:03:17.988744
2361 23:03:17.991987 [CBTSetCACLKResult] CA Dly = 33
2362 23:03:17.992069 CS Dly: 7 (0~39)
2363 23:03:17.992133
2364 23:03:17.995431 ----->DramcWriteLeveling(PI) begin...
2365 23:03:17.998591 ==
2366 23:03:18.002000 Dram Type= 6, Freq= 0, CH_0, rank 0
2367 23:03:18.005396 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2368 23:03:18.005485 ==
2369 23:03:18.008637 Write leveling (Byte 0): 25 => 25
2370 23:03:18.011908 Write leveling (Byte 1): 25 => 25
2371 23:03:18.015441 DramcWriteLeveling(PI) end<-----
2372 23:03:18.015527
2373 23:03:18.015592 ==
2374 23:03:18.018631 Dram Type= 6, Freq= 0, CH_0, rank 0
2375 23:03:18.021927 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2376 23:03:18.022010 ==
2377 23:03:18.025451 [Gating] SW mode calibration
2378 23:03:18.031943 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2379 23:03:18.038494 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2380 23:03:18.042178 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2381 23:03:18.045291 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2382 23:03:18.048670 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2383 23:03:18.055382 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2384 23:03:18.058566 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
2385 23:03:18.061951 0 11 20 | B1->B0 | 2c2c 2929 | 0 0 | (0 0) (0 0)
2386 23:03:18.068651 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2387 23:03:18.072066 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2388 23:03:18.075267 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2389 23:03:18.081892 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2390 23:03:18.085143 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2391 23:03:18.088626 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2392 23:03:18.095274 0 12 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
2393 23:03:18.098583 0 12 20 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
2394 23:03:18.101992 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2395 23:03:18.108496 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2396 23:03:18.112131 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2397 23:03:18.115310 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2398 23:03:18.121754 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2399 23:03:18.125258 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2400 23:03:18.128464 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2401 23:03:18.135095 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2402 23:03:18.138796 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2403 23:03:18.141884 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2404 23:03:18.145095 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2405 23:03:18.151751 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2406 23:03:18.155169 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2407 23:03:18.158677 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2408 23:03:18.165023 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2409 23:03:18.168418 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2410 23:03:18.171921 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2411 23:03:18.178620 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2412 23:03:18.181833 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2413 23:03:18.185263 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2414 23:03:18.191817 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2415 23:03:18.195237 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2416 23:03:18.198604 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2417 23:03:18.205256 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2418 23:03:18.205361 Total UI for P1: 0, mck2ui 16
2419 23:03:18.211995 best dqsien dly found for B0: ( 0, 15, 18)
2420 23:03:18.215240 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2421 23:03:18.218471 Total UI for P1: 0, mck2ui 16
2422 23:03:18.221804 best dqsien dly found for B1: ( 0, 15, 20)
2423 23:03:18.225127 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2424 23:03:18.228404 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2425 23:03:18.228498
2426 23:03:18.231687 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2427 23:03:18.234907 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2428 23:03:18.238331 [Gating] SW calibration Done
2429 23:03:18.238440 ==
2430 23:03:18.241558 Dram Type= 6, Freq= 0, CH_0, rank 0
2431 23:03:18.245015 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2432 23:03:18.248314 ==
2433 23:03:18.248425 RX Vref Scan: 0
2434 23:03:18.248548
2435 23:03:18.251489 RX Vref 0 -> 0, step: 1
2436 23:03:18.251572
2437 23:03:18.254991 RX Delay -40 -> 252, step: 8
2438 23:03:18.258219 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2439 23:03:18.261456 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2440 23:03:18.264950 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2441 23:03:18.268467 iDelay=200, Bit 3, Center 111 (32 ~ 191) 160
2442 23:03:18.274910 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2443 23:03:18.278169 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2444 23:03:18.281465 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2445 23:03:18.284714 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2446 23:03:18.288140 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2447 23:03:18.291552 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2448 23:03:18.298201 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2449 23:03:18.301524 iDelay=200, Bit 11, Center 103 (40 ~ 167) 128
2450 23:03:18.304659 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2451 23:03:18.308250 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2452 23:03:18.314715 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2453 23:03:18.318166 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
2454 23:03:18.318263 ==
2455 23:03:18.321457 Dram Type= 6, Freq= 0, CH_0, rank 0
2456 23:03:18.324986 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2457 23:03:18.325073 ==
2458 23:03:18.325140 DQS Delay:
2459 23:03:18.328308 DQS0 = 0, DQS1 = 0
2460 23:03:18.328396 DQM Delay:
2461 23:03:18.331375 DQM0 = 115, DQM1 = 106
2462 23:03:18.331461 DQ Delay:
2463 23:03:18.334738 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =111
2464 23:03:18.337941 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2465 23:03:18.341300 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =103
2466 23:03:18.344856 DQ12 =111, DQ13 =115, DQ14 =115, DQ15 =115
2467 23:03:18.347844
2468 23:03:18.347931
2469 23:03:18.347996 ==
2470 23:03:18.351277 Dram Type= 6, Freq= 0, CH_0, rank 0
2471 23:03:18.354599 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2472 23:03:18.354685 ==
2473 23:03:18.354752
2474 23:03:18.354812
2475 23:03:18.357901 TX Vref Scan disable
2476 23:03:18.357985 == TX Byte 0 ==
2477 23:03:18.364963 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2478 23:03:18.367893 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2479 23:03:18.367985 == TX Byte 1 ==
2480 23:03:18.374937 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2481 23:03:18.378149 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2482 23:03:18.378242 ==
2483 23:03:18.381515 Dram Type= 6, Freq= 0, CH_0, rank 0
2484 23:03:18.384693 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2485 23:03:18.384782 ==
2486 23:03:18.396863 TX Vref=22, minBit 4, minWin=25, winSum=410
2487 23:03:18.400139 TX Vref=24, minBit 10, minWin=24, winSum=409
2488 23:03:18.403566 TX Vref=26, minBit 12, minWin=25, winSum=418
2489 23:03:18.406879 TX Vref=28, minBit 1, minWin=26, winSum=423
2490 23:03:18.410212 TX Vref=30, minBit 1, minWin=26, winSum=427
2491 23:03:18.416982 TX Vref=32, minBit 1, minWin=26, winSum=427
2492 23:03:18.420107 [TxChooseVref] Worse bit 1, Min win 26, Win sum 427, Final Vref 30
2493 23:03:18.420203
2494 23:03:18.423400 Final TX Range 1 Vref 30
2495 23:03:18.423485
2496 23:03:18.423550 ==
2497 23:03:18.426782 Dram Type= 6, Freq= 0, CH_0, rank 0
2498 23:03:18.430082 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2499 23:03:18.430173 ==
2500 23:03:18.433368
2501 23:03:18.433454
2502 23:03:18.433519 TX Vref Scan disable
2503 23:03:18.436700 == TX Byte 0 ==
2504 23:03:18.440087 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2505 23:03:18.443331 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2506 23:03:18.446612 == TX Byte 1 ==
2507 23:03:18.450022 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2508 23:03:18.453223 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2509 23:03:18.456534
2510 23:03:18.456621 [DATLAT]
2511 23:03:18.456688 Freq=1200, CH0 RK0
2512 23:03:18.456750
2513 23:03:18.459710 DATLAT Default: 0xd
2514 23:03:18.459794 0, 0xFFFF, sum = 0
2515 23:03:18.463252 1, 0xFFFF, sum = 0
2516 23:03:18.463338 2, 0xFFFF, sum = 0
2517 23:03:18.466693 3, 0xFFFF, sum = 0
2518 23:03:18.469884 4, 0xFFFF, sum = 0
2519 23:03:18.469972 5, 0xFFFF, sum = 0
2520 23:03:18.473122 6, 0xFFFF, sum = 0
2521 23:03:18.473207 7, 0xFFFF, sum = 0
2522 23:03:18.476402 8, 0xFFFF, sum = 0
2523 23:03:18.476522 9, 0xFFFF, sum = 0
2524 23:03:18.479931 10, 0xFFFF, sum = 0
2525 23:03:18.480017 11, 0x0, sum = 1
2526 23:03:18.483289 12, 0x0, sum = 2
2527 23:03:18.483376 13, 0x0, sum = 3
2528 23:03:18.486748 14, 0x0, sum = 4
2529 23:03:18.486835 best_step = 12
2530 23:03:18.486901
2531 23:03:18.486963 ==
2532 23:03:18.489807 Dram Type= 6, Freq= 0, CH_0, rank 0
2533 23:03:18.493069 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2534 23:03:18.493158 ==
2535 23:03:18.496255 RX Vref Scan: 1
2536 23:03:18.496344
2537 23:03:18.499749 Set Vref Range= 32 -> 127
2538 23:03:18.499836
2539 23:03:18.499902 RX Vref 32 -> 127, step: 1
2540 23:03:18.499964
2541 23:03:18.502994 RX Delay -21 -> 252, step: 4
2542 23:03:18.503080
2543 23:03:18.506539 Set Vref, RX VrefLevel [Byte0]: 32
2544 23:03:18.509581 [Byte1]: 32
2545 23:03:18.513260
2546 23:03:18.513351 Set Vref, RX VrefLevel [Byte0]: 33
2547 23:03:18.516694 [Byte1]: 33
2548 23:03:18.521219
2549 23:03:18.521310 Set Vref, RX VrefLevel [Byte0]: 34
2550 23:03:18.524393 [Byte1]: 34
2551 23:03:18.529159
2552 23:03:18.529261 Set Vref, RX VrefLevel [Byte0]: 35
2553 23:03:18.532401 [Byte1]: 35
2554 23:03:18.537083
2555 23:03:18.537178 Set Vref, RX VrefLevel [Byte0]: 36
2556 23:03:18.540407 [Byte1]: 36
2557 23:03:18.544835
2558 23:03:18.544929 Set Vref, RX VrefLevel [Byte0]: 37
2559 23:03:18.548457 [Byte1]: 37
2560 23:03:18.553038
2561 23:03:18.553130 Set Vref, RX VrefLevel [Byte0]: 38
2562 23:03:18.556058 [Byte1]: 38
2563 23:03:18.560735
2564 23:03:18.560830 Set Vref, RX VrefLevel [Byte0]: 39
2565 23:03:18.564075 [Byte1]: 39
2566 23:03:18.568551
2567 23:03:18.568642 Set Vref, RX VrefLevel [Byte0]: 40
2568 23:03:18.572151 [Byte1]: 40
2569 23:03:18.576900
2570 23:03:18.576990 Set Vref, RX VrefLevel [Byte0]: 41
2571 23:03:18.579961 [Byte1]: 41
2572 23:03:18.584537
2573 23:03:18.584627 Set Vref, RX VrefLevel [Byte0]: 42
2574 23:03:18.587860 [Byte1]: 42
2575 23:03:18.592342
2576 23:03:18.592430 Set Vref, RX VrefLevel [Byte0]: 43
2577 23:03:18.595624 [Byte1]: 43
2578 23:03:18.600541
2579 23:03:18.600634 Set Vref, RX VrefLevel [Byte0]: 44
2580 23:03:18.603688 [Byte1]: 44
2581 23:03:18.608293
2582 23:03:18.608383 Set Vref, RX VrefLevel [Byte0]: 45
2583 23:03:18.611915 [Byte1]: 45
2584 23:03:18.616146
2585 23:03:18.616237 Set Vref, RX VrefLevel [Byte0]: 46
2586 23:03:18.619630 [Byte1]: 46
2587 23:03:18.624132
2588 23:03:18.624222 Set Vref, RX VrefLevel [Byte0]: 47
2589 23:03:18.627379 [Byte1]: 47
2590 23:03:18.632185
2591 23:03:18.632286 Set Vref, RX VrefLevel [Byte0]: 48
2592 23:03:18.635305 [Byte1]: 48
2593 23:03:18.639880
2594 23:03:18.639977 Set Vref, RX VrefLevel [Byte0]: 49
2595 23:03:18.643351 [Byte1]: 49
2596 23:03:18.648015
2597 23:03:18.648101 Set Vref, RX VrefLevel [Byte0]: 50
2598 23:03:18.651424 [Byte1]: 50
2599 23:03:18.655772
2600 23:03:18.655862 Set Vref, RX VrefLevel [Byte0]: 51
2601 23:03:18.659215 [Byte1]: 51
2602 23:03:18.663715
2603 23:03:18.663805 Set Vref, RX VrefLevel [Byte0]: 52
2604 23:03:18.667207 [Byte1]: 52
2605 23:03:18.671829
2606 23:03:18.671919 Set Vref, RX VrefLevel [Byte0]: 53
2607 23:03:18.674939 [Byte1]: 53
2608 23:03:18.679536
2609 23:03:18.679624 Set Vref, RX VrefLevel [Byte0]: 54
2610 23:03:18.683087 [Byte1]: 54
2611 23:03:18.687768
2612 23:03:18.687857 Set Vref, RX VrefLevel [Byte0]: 55
2613 23:03:18.690734 [Byte1]: 55
2614 23:03:18.695420
2615 23:03:18.695509 Set Vref, RX VrefLevel [Byte0]: 56
2616 23:03:18.698681 [Byte1]: 56
2617 23:03:18.703264
2618 23:03:18.703353 Set Vref, RX VrefLevel [Byte0]: 57
2619 23:03:18.706549 [Byte1]: 57
2620 23:03:18.711268
2621 23:03:18.711357 Set Vref, RX VrefLevel [Byte0]: 58
2622 23:03:18.714567 [Byte1]: 58
2623 23:03:18.719134
2624 23:03:18.719226 Set Vref, RX VrefLevel [Byte0]: 59
2625 23:03:18.722539 [Byte1]: 59
2626 23:03:18.727244
2627 23:03:18.727341 Set Vref, RX VrefLevel [Byte0]: 60
2628 23:03:18.730419 [Byte1]: 60
2629 23:03:18.734962
2630 23:03:18.735058 Set Vref, RX VrefLevel [Byte0]: 61
2631 23:03:18.738583 [Byte1]: 61
2632 23:03:18.742904
2633 23:03:18.743001 Set Vref, RX VrefLevel [Byte0]: 62
2634 23:03:18.746215 [Byte1]: 62
2635 23:03:18.750866
2636 23:03:18.750959 Set Vref, RX VrefLevel [Byte0]: 63
2637 23:03:18.754217 [Byte1]: 63
2638 23:03:18.758894
2639 23:03:18.758985 Set Vref, RX VrefLevel [Byte0]: 64
2640 23:03:18.762121 [Byte1]: 64
2641 23:03:18.766632
2642 23:03:18.766723 Set Vref, RX VrefLevel [Byte0]: 65
2643 23:03:18.769929 [Byte1]: 65
2644 23:03:18.775206
2645 23:03:18.775299 Set Vref, RX VrefLevel [Byte0]: 66
2646 23:03:18.777940 [Byte1]: 66
2647 23:03:18.782579
2648 23:03:18.782667 Final RX Vref Byte 0 = 47 to rank0
2649 23:03:18.785886 Final RX Vref Byte 1 = 48 to rank0
2650 23:03:18.789213 Final RX Vref Byte 0 = 47 to rank1
2651 23:03:18.792497 Final RX Vref Byte 1 = 48 to rank1==
2652 23:03:18.796049 Dram Type= 6, Freq= 0, CH_0, rank 0
2653 23:03:18.802701 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2654 23:03:18.802805 ==
2655 23:03:18.802874 DQS Delay:
2656 23:03:18.802935 DQS0 = 0, DQS1 = 0
2657 23:03:18.805679 DQM Delay:
2658 23:03:18.805766 DQM0 = 114, DQM1 = 105
2659 23:03:18.809056 DQ Delay:
2660 23:03:18.812399 DQ0 =110, DQ1 =116, DQ2 =112, DQ3 =108
2661 23:03:18.815929 DQ4 =118, DQ5 =108, DQ6 =124, DQ7 =120
2662 23:03:18.819197 DQ8 =94, DQ9 =86, DQ10 =106, DQ11 =96
2663 23:03:18.822352 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =116
2664 23:03:18.822441
2665 23:03:18.822506
2666 23:03:18.828988 [DQSOSCAuto] RK0, (LSB)MR18= 0x707, (MSB)MR19= 0x404, tDQSOscB0 = 407 ps tDQSOscB1 = 407 ps
2667 23:03:18.832264 CH0 RK0: MR19=404, MR18=707
2668 23:03:18.839136 CH0_RK0: MR19=0x404, MR18=0x707, DQSOSC=407, MR23=63, INC=39, DEC=26
2669 23:03:18.839250
2670 23:03:18.842246 ----->DramcWriteLeveling(PI) begin...
2671 23:03:18.842340 ==
2672 23:03:18.845515 Dram Type= 6, Freq= 0, CH_0, rank 1
2673 23:03:18.848973 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2674 23:03:18.849064 ==
2675 23:03:18.852495 Write leveling (Byte 0): 29 => 29
2676 23:03:18.855799 Write leveling (Byte 1): 25 => 25
2677 23:03:18.858939 DramcWriteLeveling(PI) end<-----
2678 23:03:18.859027
2679 23:03:18.859093 ==
2680 23:03:18.862421 Dram Type= 6, Freq= 0, CH_0, rank 1
2681 23:03:18.868911 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2682 23:03:18.869011 ==
2683 23:03:18.869080 [Gating] SW mode calibration
2684 23:03:18.878942 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2685 23:03:18.882192 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2686 23:03:18.885577 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2687 23:03:18.892129 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2688 23:03:18.895562 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2689 23:03:18.899146 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2690 23:03:18.905609 0 11 16 | B1->B0 | 3434 3333 | 1 1 | (1 0) (1 0)
2691 23:03:18.908897 0 11 20 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (1 0)
2692 23:03:18.912160 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2693 23:03:18.918700 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2694 23:03:18.922021 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2695 23:03:18.925282 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2696 23:03:18.932048 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2697 23:03:18.935445 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2698 23:03:18.938559 0 12 16 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
2699 23:03:18.945570 0 12 20 | B1->B0 | 4242 4646 | 0 0 | (1 1) (0 0)
2700 23:03:18.948908 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2701 23:03:18.951952 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2702 23:03:18.958753 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2703 23:03:18.962016 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2704 23:03:18.965308 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2705 23:03:18.971971 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2706 23:03:18.975242 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2707 23:03:18.978497 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2708 23:03:18.985258 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2709 23:03:18.988501 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2710 23:03:18.991959 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2711 23:03:18.995575 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2712 23:03:19.002179 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2713 23:03:19.005299 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2714 23:03:19.008955 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2715 23:03:19.015283 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2716 23:03:19.018794 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2717 23:03:19.022058 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2718 23:03:19.028702 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2719 23:03:19.032029 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2720 23:03:19.035456 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2721 23:03:19.041909 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2722 23:03:19.045338 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2723 23:03:19.048780 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2724 23:03:19.052018 Total UI for P1: 0, mck2ui 16
2725 23:03:19.055208 best dqsien dly found for B0: ( 0, 15, 16)
2726 23:03:19.062078 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2727 23:03:19.062184 Total UI for P1: 0, mck2ui 16
2728 23:03:19.065489 best dqsien dly found for B1: ( 0, 15, 18)
2729 23:03:19.072263 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
2730 23:03:19.075648 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2731 23:03:19.075741
2732 23:03:19.078863 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
2733 23:03:19.082125 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
2734 23:03:19.085453 [Gating] SW calibration Done
2735 23:03:19.085555 ==
2736 23:03:19.088755 Dram Type= 6, Freq= 0, CH_0, rank 1
2737 23:03:19.092216 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2738 23:03:19.092301 ==
2739 23:03:19.095317 RX Vref Scan: 0
2740 23:03:19.095399
2741 23:03:19.095463 RX Vref 0 -> 0, step: 1
2742 23:03:19.095523
2743 23:03:19.098746 RX Delay -40 -> 252, step: 8
2744 23:03:19.102415 iDelay=200, Bit 0, Center 107 (32 ~ 183) 152
2745 23:03:19.108685 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2746 23:03:19.112058 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2747 23:03:19.115416 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2748 23:03:19.118632 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2749 23:03:19.122356 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2750 23:03:19.125278 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2751 23:03:19.131933 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2752 23:03:19.135634 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2753 23:03:19.138866 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2754 23:03:19.142207 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2755 23:03:19.145559 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2756 23:03:19.151907 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2757 23:03:19.155473 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2758 23:03:19.158854 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2759 23:03:19.161859 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2760 23:03:19.161947 ==
2761 23:03:19.165383 Dram Type= 6, Freq= 0, CH_0, rank 1
2762 23:03:19.171995 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2763 23:03:19.172095 ==
2764 23:03:19.172163 DQS Delay:
2765 23:03:19.175394 DQS0 = 0, DQS1 = 0
2766 23:03:19.175557 DQM Delay:
2767 23:03:19.175653 DQM0 = 114, DQM1 = 106
2768 23:03:19.178492 DQ Delay:
2769 23:03:19.182152 DQ0 =107, DQ1 =115, DQ2 =115, DQ3 =111
2770 23:03:19.185090 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2771 23:03:19.188727 DQ8 =91, DQ9 =91, DQ10 =107, DQ11 =99
2772 23:03:19.191792 DQ12 =115, DQ13 =111, DQ14 =119, DQ15 =115
2773 23:03:19.191880
2774 23:03:19.191946
2775 23:03:19.192006 ==
2776 23:03:19.195031 Dram Type= 6, Freq= 0, CH_0, rank 1
2777 23:03:19.198497 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2778 23:03:19.201969 ==
2779 23:03:19.202054
2780 23:03:19.202119
2781 23:03:19.202178 TX Vref Scan disable
2782 23:03:19.205067 == TX Byte 0 ==
2783 23:03:19.208313 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2784 23:03:19.211758 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2785 23:03:19.215064 == TX Byte 1 ==
2786 23:03:19.218543 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2787 23:03:19.221731 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2788 23:03:19.221820 ==
2789 23:03:19.224930 Dram Type= 6, Freq= 0, CH_0, rank 1
2790 23:03:19.231530 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2791 23:03:19.231641 ==
2792 23:03:19.242636 TX Vref=22, minBit 1, minWin=26, winSum=423
2793 23:03:19.245997 TX Vref=24, minBit 9, minWin=25, winSum=423
2794 23:03:19.249291 TX Vref=26, minBit 9, minWin=26, winSum=430
2795 23:03:19.252796 TX Vref=28, minBit 9, minWin=26, winSum=435
2796 23:03:19.255821 TX Vref=30, minBit 9, minWin=26, winSum=434
2797 23:03:19.262678 TX Vref=32, minBit 8, minWin=26, winSum=435
2798 23:03:19.265974 [TxChooseVref] Worse bit 9, Min win 26, Win sum 435, Final Vref 28
2799 23:03:19.266071
2800 23:03:19.269407 Final TX Range 1 Vref 28
2801 23:03:19.269493
2802 23:03:19.269559 ==
2803 23:03:19.272631 Dram Type= 6, Freq= 0, CH_0, rank 1
2804 23:03:19.275768 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2805 23:03:19.275854 ==
2806 23:03:19.279085
2807 23:03:19.279169
2808 23:03:19.279235 TX Vref Scan disable
2809 23:03:19.282376 == TX Byte 0 ==
2810 23:03:19.285717 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2811 23:03:19.292420 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2812 23:03:19.292551 == TX Byte 1 ==
2813 23:03:19.295557 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2814 23:03:19.302314 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2815 23:03:19.302437
2816 23:03:19.302508 [DATLAT]
2817 23:03:19.302570 Freq=1200, CH0 RK1
2818 23:03:19.302630
2819 23:03:19.306066 DATLAT Default: 0xc
2820 23:03:19.306153 0, 0xFFFF, sum = 0
2821 23:03:19.309021 1, 0xFFFF, sum = 0
2822 23:03:19.309107 2, 0xFFFF, sum = 0
2823 23:03:19.312460 3, 0xFFFF, sum = 0
2824 23:03:19.315674 4, 0xFFFF, sum = 0
2825 23:03:19.315762 5, 0xFFFF, sum = 0
2826 23:03:19.319113 6, 0xFFFF, sum = 0
2827 23:03:19.319199 7, 0xFFFF, sum = 0
2828 23:03:19.322281 8, 0xFFFF, sum = 0
2829 23:03:19.322366 9, 0xFFFF, sum = 0
2830 23:03:19.325666 10, 0xFFFF, sum = 0
2831 23:03:19.325753 11, 0x0, sum = 1
2832 23:03:19.329141 12, 0x0, sum = 2
2833 23:03:19.329230 13, 0x0, sum = 3
2834 23:03:19.332292 14, 0x0, sum = 4
2835 23:03:19.332408 best_step = 12
2836 23:03:19.332502
2837 23:03:19.332612 ==
2838 23:03:19.335759 Dram Type= 6, Freq= 0, CH_0, rank 1
2839 23:03:19.339158 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2840 23:03:19.339245 ==
2841 23:03:19.342254 RX Vref Scan: 0
2842 23:03:19.342363
2843 23:03:19.345502 RX Vref 0 -> 0, step: 1
2844 23:03:19.345586
2845 23:03:19.345652 RX Delay -21 -> 252, step: 4
2846 23:03:19.352954 iDelay=195, Bit 0, Center 110 (39 ~ 182) 144
2847 23:03:19.356362 iDelay=195, Bit 1, Center 116 (43 ~ 190) 148
2848 23:03:19.359533 iDelay=195, Bit 2, Center 114 (43 ~ 186) 144
2849 23:03:19.362992 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
2850 23:03:19.366289 iDelay=195, Bit 4, Center 118 (47 ~ 190) 144
2851 23:03:19.372947 iDelay=195, Bit 5, Center 108 (39 ~ 178) 140
2852 23:03:19.376322 iDelay=195, Bit 6, Center 124 (55 ~ 194) 140
2853 23:03:19.379456 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
2854 23:03:19.382888 iDelay=195, Bit 8, Center 94 (31 ~ 158) 128
2855 23:03:19.386181 iDelay=195, Bit 9, Center 90 (27 ~ 154) 128
2856 23:03:19.392865 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
2857 23:03:19.396254 iDelay=195, Bit 11, Center 96 (35 ~ 158) 124
2858 23:03:19.399778 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
2859 23:03:19.402778 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
2860 23:03:19.406314 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
2861 23:03:19.413130 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
2862 23:03:19.413240 ==
2863 23:03:19.416629 Dram Type= 6, Freq= 0, CH_0, rank 1
2864 23:03:19.419745 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2865 23:03:19.419832 ==
2866 23:03:19.419897 DQS Delay:
2867 23:03:19.423202 DQS0 = 0, DQS1 = 0
2868 23:03:19.423287 DQM Delay:
2869 23:03:19.426399 DQM0 = 115, DQM1 = 106
2870 23:03:19.426484 DQ Delay:
2871 23:03:19.429499 DQ0 =110, DQ1 =116, DQ2 =114, DQ3 =108
2872 23:03:19.432912 DQ4 =118, DQ5 =108, DQ6 =124, DQ7 =122
2873 23:03:19.436403 DQ8 =94, DQ9 =90, DQ10 =110, DQ11 =96
2874 23:03:19.439415 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =114
2875 23:03:19.439506
2876 23:03:19.439573
2877 23:03:19.449543 [DQSOSCAuto] RK1, (LSB)MR18= 0xe0e, (MSB)MR19= 0x404, tDQSOscB0 = 404 ps tDQSOscB1 = 404 ps
2878 23:03:19.452893 CH0 RK1: MR19=404, MR18=E0E
2879 23:03:19.456149 CH0_RK1: MR19=0x404, MR18=0xE0E, DQSOSC=404, MR23=63, INC=40, DEC=26
2880 23:03:19.459537 [RxdqsGatingPostProcess] freq 1200
2881 23:03:19.466121 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2882 23:03:19.469482 Pre-setting of DQS Precalculation
2883 23:03:19.472861 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2884 23:03:19.472951 ==
2885 23:03:19.476152 Dram Type= 6, Freq= 0, CH_1, rank 0
2886 23:03:19.482943 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2887 23:03:19.483050 ==
2888 23:03:19.485985 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2889 23:03:19.492710 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2890 23:03:19.501485 [CA 0] Center 37 (7~67) winsize 61
2891 23:03:19.504708 [CA 1] Center 37 (7~68) winsize 62
2892 23:03:19.507867 [CA 2] Center 34 (4~65) winsize 62
2893 23:03:19.511244 [CA 3] Center 33 (3~64) winsize 62
2894 23:03:19.514685 [CA 4] Center 32 (1~63) winsize 63
2895 23:03:19.517948 [CA 5] Center 32 (2~63) winsize 62
2896 23:03:19.518036
2897 23:03:19.521244 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2898 23:03:19.521333
2899 23:03:19.524668 [CATrainingPosCal] consider 1 rank data
2900 23:03:19.528034 u2DelayCellTimex100 = 270/100 ps
2901 23:03:19.531369 CA0 delay=37 (7~67),Diff = 5 PI (24 cell)
2902 23:03:19.534423 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2903 23:03:19.541359 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2904 23:03:19.544409 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2905 23:03:19.547968 CA4 delay=32 (1~63),Diff = 0 PI (0 cell)
2906 23:03:19.551036 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2907 23:03:19.551128
2908 23:03:19.554410 CA PerBit enable=1, Macro0, CA PI delay=32
2909 23:03:19.554496
2910 23:03:19.557778 [CBTSetCACLKResult] CA Dly = 32
2911 23:03:19.557864 CS Dly: 6 (0~37)
2912 23:03:19.561029 ==
2913 23:03:19.561114 Dram Type= 6, Freq= 0, CH_1, rank 1
2914 23:03:19.567807 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2915 23:03:19.567904 ==
2916 23:03:19.571230 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2917 23:03:19.577784 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2918 23:03:19.586731 [CA 0] Center 37 (7~68) winsize 62
2919 23:03:19.589903 [CA 1] Center 37 (6~68) winsize 63
2920 23:03:19.593130 [CA 2] Center 34 (3~65) winsize 63
2921 23:03:19.596380 [CA 3] Center 33 (3~64) winsize 62
2922 23:03:19.599785 [CA 4] Center 32 (2~63) winsize 62
2923 23:03:19.603357 [CA 5] Center 32 (1~63) winsize 63
2924 23:03:19.603447
2925 23:03:19.606483 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2926 23:03:19.606568
2927 23:03:19.609780 [CATrainingPosCal] consider 2 rank data
2928 23:03:19.613084 u2DelayCellTimex100 = 270/100 ps
2929 23:03:19.616272 CA0 delay=37 (7~67),Diff = 5 PI (24 cell)
2930 23:03:19.619833 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2931 23:03:19.626475 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2932 23:03:19.629566 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2933 23:03:19.633331 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2934 23:03:19.636324 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2935 23:03:19.636415
2936 23:03:19.639628 CA PerBit enable=1, Macro0, CA PI delay=32
2937 23:03:19.639717
2938 23:03:19.643112 [CBTSetCACLKResult] CA Dly = 32
2939 23:03:19.643211 CS Dly: 6 (0~38)
2940 23:03:19.643286
2941 23:03:19.646382 ----->DramcWriteLeveling(PI) begin...
2942 23:03:19.649781 ==
2943 23:03:19.653023 Dram Type= 6, Freq= 0, CH_1, rank 0
2944 23:03:19.656455 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2945 23:03:19.656589 ==
2946 23:03:19.659866 Write leveling (Byte 0): 21 => 21
2947 23:03:19.663107 Write leveling (Byte 1): 22 => 22
2948 23:03:19.666296 DramcWriteLeveling(PI) end<-----
2949 23:03:19.666384
2950 23:03:19.666451 ==
2951 23:03:19.669667 Dram Type= 6, Freq= 0, CH_1, rank 0
2952 23:03:19.673115 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2953 23:03:19.673201 ==
2954 23:03:19.676385 [Gating] SW mode calibration
2955 23:03:19.683371 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2956 23:03:19.686389 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2957 23:03:19.693282 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2958 23:03:19.696531 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2959 23:03:19.699817 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2960 23:03:19.706430 0 11 12 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
2961 23:03:19.710119 0 11 16 | B1->B0 | 3030 2525 | 1 0 | (1 0) (1 0)
2962 23:03:19.713086 0 11 20 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
2963 23:03:19.719926 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2964 23:03:19.723430 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2965 23:03:19.726634 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2966 23:03:19.733402 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2967 23:03:19.736767 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2968 23:03:19.739765 0 12 12 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
2969 23:03:19.746436 0 12 16 | B1->B0 | 3535 4545 | 1 0 | (0 0) (0 0)
2970 23:03:19.749801 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2971 23:03:19.753042 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2972 23:03:19.759977 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2973 23:03:19.763076 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2974 23:03:19.766704 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2975 23:03:19.773015 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2976 23:03:19.776369 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2977 23:03:19.779776 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2978 23:03:19.783262 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2979 23:03:19.789947 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2980 23:03:19.793168 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2981 23:03:19.796450 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2982 23:03:19.803207 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2983 23:03:19.806716 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2984 23:03:19.809784 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2985 23:03:19.816451 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2986 23:03:19.819854 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2987 23:03:19.823380 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2988 23:03:19.829887 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2989 23:03:19.833417 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2990 23:03:19.836534 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2991 23:03:19.843261 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2992 23:03:19.846832 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2993 23:03:19.850084 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2994 23:03:19.853406 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2995 23:03:19.856666 Total UI for P1: 0, mck2ui 16
2996 23:03:19.860098 best dqsien dly found for B0: ( 0, 15, 16)
2997 23:03:19.866630 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2998 23:03:19.869943 Total UI for P1: 0, mck2ui 16
2999 23:03:19.873464 best dqsien dly found for B1: ( 0, 15, 20)
3000 23:03:19.876786 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
3001 23:03:19.879803 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
3002 23:03:19.879890
3003 23:03:19.883247 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
3004 23:03:19.886645 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
3005 23:03:19.889951 [Gating] SW calibration Done
3006 23:03:19.890036 ==
3007 23:03:19.893107 Dram Type= 6, Freq= 0, CH_1, rank 0
3008 23:03:19.896436 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3009 23:03:19.896529 ==
3010 23:03:19.899931 RX Vref Scan: 0
3011 23:03:19.900014
3012 23:03:19.903346 RX Vref 0 -> 0, step: 1
3013 23:03:19.903431
3014 23:03:19.903496 RX Delay -40 -> 252, step: 8
3015 23:03:19.909893 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160
3016 23:03:19.913420 iDelay=208, Bit 1, Center 107 (32 ~ 183) 152
3017 23:03:19.916726 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3018 23:03:19.920021 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3019 23:03:19.923352 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3020 23:03:19.930063 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3021 23:03:19.933567 iDelay=208, Bit 6, Center 119 (40 ~ 199) 160
3022 23:03:19.936637 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3023 23:03:19.940038 iDelay=208, Bit 8, Center 87 (16 ~ 159) 144
3024 23:03:19.943316 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144
3025 23:03:19.946562 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3026 23:03:19.953105 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3027 23:03:19.956399 iDelay=208, Bit 12, Center 115 (40 ~ 191) 152
3028 23:03:19.959779 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3029 23:03:19.963406 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3030 23:03:19.969757 iDelay=208, Bit 15, Center 115 (40 ~ 191) 152
3031 23:03:19.969864 ==
3032 23:03:19.973271 Dram Type= 6, Freq= 0, CH_1, rank 0
3033 23:03:19.976385 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3034 23:03:19.976473 ==
3035 23:03:19.976546 DQS Delay:
3036 23:03:19.979509 DQS0 = 0, DQS1 = 0
3037 23:03:19.979592 DQM Delay:
3038 23:03:19.983151 DQM0 = 115, DQM1 = 107
3039 23:03:19.983235 DQ Delay:
3040 23:03:19.986318 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115
3041 23:03:19.989635 DQ4 =115, DQ5 =127, DQ6 =119, DQ7 =115
3042 23:03:19.992908 DQ8 =87, DQ9 =95, DQ10 =111, DQ11 =99
3043 23:03:19.996261 DQ12 =115, DQ13 =119, DQ14 =115, DQ15 =115
3044 23:03:19.996346
3045 23:03:19.996410
3046 23:03:19.996469 ==
3047 23:03:19.999612 Dram Type= 6, Freq= 0, CH_1, rank 0
3048 23:03:20.006258 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3049 23:03:20.006355 ==
3050 23:03:20.006420
3051 23:03:20.006479
3052 23:03:20.006535 TX Vref Scan disable
3053 23:03:20.010068 == TX Byte 0 ==
3054 23:03:20.013677 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3055 23:03:20.016494 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3056 23:03:20.019937 == TX Byte 1 ==
3057 23:03:20.023158 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3058 23:03:20.030323 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3059 23:03:20.030436 ==
3060 23:03:20.033554 Dram Type= 6, Freq= 0, CH_1, rank 0
3061 23:03:20.036458 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3062 23:03:20.036597 ==
3063 23:03:20.047558 TX Vref=22, minBit 8, minWin=25, winSum=414
3064 23:03:20.050918 TX Vref=24, minBit 11, minWin=25, winSum=419
3065 23:03:20.054351 TX Vref=26, minBit 0, minWin=26, winSum=422
3066 23:03:20.057518 TX Vref=28, minBit 1, minWin=26, winSum=427
3067 23:03:20.061122 TX Vref=30, minBit 0, minWin=26, winSum=431
3068 23:03:20.067589 TX Vref=32, minBit 9, minWin=25, winSum=427
3069 23:03:20.071062 [TxChooseVref] Worse bit 0, Min win 26, Win sum 431, Final Vref 30
3070 23:03:20.071156
3071 23:03:20.074217 Final TX Range 1 Vref 30
3072 23:03:20.074302
3073 23:03:20.074368 ==
3074 23:03:20.077609 Dram Type= 6, Freq= 0, CH_1, rank 0
3075 23:03:20.080964 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3076 23:03:20.081049 ==
3077 23:03:20.081113
3078 23:03:20.084333
3079 23:03:20.084415 TX Vref Scan disable
3080 23:03:20.087645 == TX Byte 0 ==
3081 23:03:20.090939 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3082 23:03:20.094305 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3083 23:03:20.097510 == TX Byte 1 ==
3084 23:03:20.100770 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3085 23:03:20.104286 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3086 23:03:20.104373
3087 23:03:20.107472 [DATLAT]
3088 23:03:20.107577 Freq=1200, CH1 RK0
3089 23:03:20.107644
3090 23:03:20.111055 DATLAT Default: 0xd
3091 23:03:20.111138 0, 0xFFFF, sum = 0
3092 23:03:20.114330 1, 0xFFFF, sum = 0
3093 23:03:20.114414 2, 0xFFFF, sum = 0
3094 23:03:20.117801 3, 0xFFFF, sum = 0
3095 23:03:20.117886 4, 0xFFFF, sum = 0
3096 23:03:20.121038 5, 0xFFFF, sum = 0
3097 23:03:20.121122 6, 0xFFFF, sum = 0
3098 23:03:20.124383 7, 0xFFFF, sum = 0
3099 23:03:20.124467 8, 0xFFFF, sum = 0
3100 23:03:20.127811 9, 0xFFFF, sum = 0
3101 23:03:20.130801 10, 0xFFFF, sum = 0
3102 23:03:20.130891 11, 0x0, sum = 1
3103 23:03:20.130957 12, 0x0, sum = 2
3104 23:03:20.134188 13, 0x0, sum = 3
3105 23:03:20.134274 14, 0x0, sum = 4
3106 23:03:20.137460 best_step = 12
3107 23:03:20.137543
3108 23:03:20.137608 ==
3109 23:03:20.140855 Dram Type= 6, Freq= 0, CH_1, rank 0
3110 23:03:20.144165 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3111 23:03:20.144253 ==
3112 23:03:20.147955 RX Vref Scan: 1
3113 23:03:20.148040
3114 23:03:20.148106 Set Vref Range= 32 -> 127
3115 23:03:20.150974
3116 23:03:20.151056 RX Vref 32 -> 127, step: 1
3117 23:03:20.151120
3118 23:03:20.154204 RX Delay -29 -> 252, step: 4
3119 23:03:20.154287
3120 23:03:20.157832 Set Vref, RX VrefLevel [Byte0]: 32
3121 23:03:20.160768 [Byte1]: 32
3122 23:03:20.164075
3123 23:03:20.164157 Set Vref, RX VrefLevel [Byte0]: 33
3124 23:03:20.167599 [Byte1]: 33
3125 23:03:20.172098
3126 23:03:20.172187 Set Vref, RX VrefLevel [Byte0]: 34
3127 23:03:20.175405 [Byte1]: 34
3128 23:03:20.180148
3129 23:03:20.180240 Set Vref, RX VrefLevel [Byte0]: 35
3130 23:03:20.183204 [Byte1]: 35
3131 23:03:20.187966
3132 23:03:20.188059 Set Vref, RX VrefLevel [Byte0]: 36
3133 23:03:20.191201 [Byte1]: 36
3134 23:03:20.196073
3135 23:03:20.196166 Set Vref, RX VrefLevel [Byte0]: 37
3136 23:03:20.199339 [Byte1]: 37
3137 23:03:20.204252
3138 23:03:20.204343 Set Vref, RX VrefLevel [Byte0]: 38
3139 23:03:20.207255 [Byte1]: 38
3140 23:03:20.211975
3141 23:03:20.212065 Set Vref, RX VrefLevel [Byte0]: 39
3142 23:03:20.215182 [Byte1]: 39
3143 23:03:20.219776
3144 23:03:20.219864 Set Vref, RX VrefLevel [Byte0]: 40
3145 23:03:20.222955 [Byte1]: 40
3146 23:03:20.227637
3147 23:03:20.227724 Set Vref, RX VrefLevel [Byte0]: 41
3148 23:03:20.231041 [Byte1]: 41
3149 23:03:20.235574
3150 23:03:20.235669 Set Vref, RX VrefLevel [Byte0]: 42
3151 23:03:20.239225 [Byte1]: 42
3152 23:03:20.244029
3153 23:03:20.244128 Set Vref, RX VrefLevel [Byte0]: 43
3154 23:03:20.247185 [Byte1]: 43
3155 23:03:20.251725
3156 23:03:20.251817 Set Vref, RX VrefLevel [Byte0]: 44
3157 23:03:20.254891 [Byte1]: 44
3158 23:03:20.259444
3159 23:03:20.259533 Set Vref, RX VrefLevel [Byte0]: 45
3160 23:03:20.262877 [Byte1]: 45
3161 23:03:20.267428
3162 23:03:20.267518 Set Vref, RX VrefLevel [Byte0]: 46
3163 23:03:20.271036 [Byte1]: 46
3164 23:03:20.275685
3165 23:03:20.275792 Set Vref, RX VrefLevel [Byte0]: 47
3166 23:03:20.278692 [Byte1]: 47
3167 23:03:20.283465
3168 23:03:20.283554 Set Vref, RX VrefLevel [Byte0]: 48
3169 23:03:20.286929 [Byte1]: 48
3170 23:03:20.291292
3171 23:03:20.291380 Set Vref, RX VrefLevel [Byte0]: 49
3172 23:03:20.294935 [Byte1]: 49
3173 23:03:20.299588
3174 23:03:20.299699 Set Vref, RX VrefLevel [Byte0]: 50
3175 23:03:20.302741 [Byte1]: 50
3176 23:03:20.307351
3177 23:03:20.307442 Set Vref, RX VrefLevel [Byte0]: 51
3178 23:03:20.310571 [Byte1]: 51
3179 23:03:20.315141
3180 23:03:20.315232 Set Vref, RX VrefLevel [Byte0]: 52
3181 23:03:20.318613 [Byte1]: 52
3182 23:03:20.323308
3183 23:03:20.323398 Set Vref, RX VrefLevel [Byte0]: 53
3184 23:03:20.326594 [Byte1]: 53
3185 23:03:20.331022
3186 23:03:20.331143 Set Vref, RX VrefLevel [Byte0]: 54
3187 23:03:20.334518 [Byte1]: 54
3188 23:03:20.339111
3189 23:03:20.339200 Set Vref, RX VrefLevel [Byte0]: 55
3190 23:03:20.342547 [Byte1]: 55
3191 23:03:20.347122
3192 23:03:20.347218 Set Vref, RX VrefLevel [Byte0]: 56
3193 23:03:20.350316 [Byte1]: 56
3194 23:03:20.355430
3195 23:03:20.355539 Set Vref, RX VrefLevel [Byte0]: 57
3196 23:03:20.358310 [Byte1]: 57
3197 23:03:20.362961
3198 23:03:20.363052 Set Vref, RX VrefLevel [Byte0]: 58
3199 23:03:20.366299 [Byte1]: 58
3200 23:03:20.370964
3201 23:03:20.371060 Set Vref, RX VrefLevel [Byte0]: 59
3202 23:03:20.374223 [Byte1]: 59
3203 23:03:20.378832
3204 23:03:20.378925 Set Vref, RX VrefLevel [Byte0]: 60
3205 23:03:20.382460 [Byte1]: 60
3206 23:03:20.386788
3207 23:03:20.386881 Set Vref, RX VrefLevel [Byte0]: 61
3208 23:03:20.390197 [Byte1]: 61
3209 23:03:20.394801
3210 23:03:20.394896 Set Vref, RX VrefLevel [Byte0]: 62
3211 23:03:20.398058 [Byte1]: 62
3212 23:03:20.402682
3213 23:03:20.402780 Set Vref, RX VrefLevel [Byte0]: 63
3214 23:03:20.405950 [Byte1]: 63
3215 23:03:20.410743
3216 23:03:20.410838 Set Vref, RX VrefLevel [Byte0]: 64
3217 23:03:20.414026 [Byte1]: 64
3218 23:03:20.418671
3219 23:03:20.418765 Set Vref, RX VrefLevel [Byte0]: 65
3220 23:03:20.421927 [Byte1]: 65
3221 23:03:20.426767
3222 23:03:20.426859 Set Vref, RX VrefLevel [Byte0]: 66
3223 23:03:20.429871 [Byte1]: 66
3224 23:03:20.434591
3225 23:03:20.434691 Final RX Vref Byte 0 = 52 to rank0
3226 23:03:20.438028 Final RX Vref Byte 1 = 48 to rank0
3227 23:03:20.441373 Final RX Vref Byte 0 = 52 to rank1
3228 23:03:20.444691 Final RX Vref Byte 1 = 48 to rank1==
3229 23:03:20.448121 Dram Type= 6, Freq= 0, CH_1, rank 0
3230 23:03:20.451514 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3231 23:03:20.455053 ==
3232 23:03:20.455145 DQS Delay:
3233 23:03:20.455230 DQS0 = 0, DQS1 = 0
3234 23:03:20.458200 DQM Delay:
3235 23:03:20.458283 DQM0 = 115, DQM1 = 104
3236 23:03:20.461471 DQ Delay:
3237 23:03:20.464882 DQ0 =120, DQ1 =110, DQ2 =106, DQ3 =114
3238 23:03:20.468063 DQ4 =114, DQ5 =126, DQ6 =122, DQ7 =114
3239 23:03:20.471648 DQ8 =86, DQ9 =94, DQ10 =108, DQ11 =96
3240 23:03:20.474960 DQ12 =112, DQ13 =116, DQ14 =114, DQ15 =112
3241 23:03:20.475047
3242 23:03:20.475131
3243 23:03:20.481596 [DQSOSCAuto] RK0, (LSB)MR18= 0x1515, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 401 ps
3244 23:03:20.484947 CH1 RK0: MR19=404, MR18=1515
3245 23:03:20.491194 CH1_RK0: MR19=0x404, MR18=0x1515, DQSOSC=401, MR23=63, INC=40, DEC=27
3246 23:03:20.491298
3247 23:03:20.494510 ----->DramcWriteLeveling(PI) begin...
3248 23:03:20.494597 ==
3249 23:03:20.498155 Dram Type= 6, Freq= 0, CH_1, rank 1
3250 23:03:20.501367 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3251 23:03:20.501459 ==
3252 23:03:20.504879 Write leveling (Byte 0): 20 => 20
3253 23:03:20.507862 Write leveling (Byte 1): 23 => 23
3254 23:03:20.511297 DramcWriteLeveling(PI) end<-----
3255 23:03:20.511384
3256 23:03:20.511470 ==
3257 23:03:20.514623 Dram Type= 6, Freq= 0, CH_1, rank 1
3258 23:03:20.521299 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3259 23:03:20.521398 ==
3260 23:03:20.521486 [Gating] SW mode calibration
3261 23:03:20.531176 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3262 23:03:20.534762 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3263 23:03:20.537884 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3264 23:03:20.544342 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3265 23:03:20.547700 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3266 23:03:20.551283 0 11 12 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (1 0)
3267 23:03:20.557801 0 11 16 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
3268 23:03:20.560985 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3269 23:03:20.564325 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3270 23:03:20.570928 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3271 23:03:20.574195 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3272 23:03:20.577656 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3273 23:03:20.584334 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3274 23:03:20.587612 0 12 12 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
3275 23:03:20.590984 0 12 16 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
3276 23:03:20.597692 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3277 23:03:20.601006 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3278 23:03:20.604326 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3279 23:03:20.610917 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3280 23:03:20.614153 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3281 23:03:20.617731 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3282 23:03:20.624353 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3283 23:03:20.627973 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3284 23:03:20.630951 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3285 23:03:20.637523 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3286 23:03:20.640908 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3287 23:03:20.644127 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3288 23:03:20.647948 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3289 23:03:20.654193 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3290 23:03:20.657448 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3291 23:03:20.660672 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3292 23:03:20.667491 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3293 23:03:20.670636 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3294 23:03:20.674135 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3295 23:03:20.680657 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3296 23:03:20.684197 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3297 23:03:20.687228 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3298 23:03:20.694093 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3299 23:03:20.697507 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3300 23:03:20.700929 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3301 23:03:20.704141 Total UI for P1: 0, mck2ui 16
3302 23:03:20.707417 best dqsien dly found for B0: ( 0, 15, 12)
3303 23:03:20.710539 Total UI for P1: 0, mck2ui 16
3304 23:03:20.714095 best dqsien dly found for B1: ( 0, 15, 16)
3305 23:03:20.717451 best DQS0 dly(MCK, UI, PI) = (0, 15, 12)
3306 23:03:20.720812 best DQS1 dly(MCK, UI, PI) = (0, 15, 16)
3307 23:03:20.720901
3308 23:03:20.727350 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 12)
3309 23:03:20.730562 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 16)
3310 23:03:20.733934 [Gating] SW calibration Done
3311 23:03:20.734031 ==
3312 23:03:20.737290 Dram Type= 6, Freq= 0, CH_1, rank 1
3313 23:03:20.740645 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3314 23:03:20.740773 ==
3315 23:03:20.740840 RX Vref Scan: 0
3316 23:03:20.740899
3317 23:03:20.743963 RX Vref 0 -> 0, step: 1
3318 23:03:20.744114
3319 23:03:20.747668 RX Delay -40 -> 252, step: 8
3320 23:03:20.750730 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3321 23:03:20.754003 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3322 23:03:20.757365 iDelay=200, Bit 2, Center 107 (32 ~ 183) 152
3323 23:03:20.763942 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3324 23:03:20.767430 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3325 23:03:20.770700 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3326 23:03:20.773936 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3327 23:03:20.777310 iDelay=200, Bit 7, Center 111 (32 ~ 191) 160
3328 23:03:20.784020 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
3329 23:03:20.787244 iDelay=200, Bit 9, Center 91 (16 ~ 167) 152
3330 23:03:20.790730 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3331 23:03:20.794381 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
3332 23:03:20.797459 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3333 23:03:20.804203 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3334 23:03:20.807448 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3335 23:03:20.810877 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3336 23:03:20.810963 ==
3337 23:03:20.814079 Dram Type= 6, Freq= 0, CH_1, rank 1
3338 23:03:20.817343 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3339 23:03:20.817430 ==
3340 23:03:20.821043 DQS Delay:
3341 23:03:20.821127 DQS0 = 0, DQS1 = 0
3342 23:03:20.824423 DQM Delay:
3343 23:03:20.824527 DQM0 = 115, DQM1 = 105
3344 23:03:20.824607 DQ Delay:
3345 23:03:20.827608 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115
3346 23:03:20.834305 DQ4 =115, DQ5 =123, DQ6 =123, DQ7 =111
3347 23:03:20.837420 DQ8 =91, DQ9 =91, DQ10 =103, DQ11 =99
3348 23:03:20.840836 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =111
3349 23:03:20.840949
3350 23:03:20.841016
3351 23:03:20.841075 ==
3352 23:03:20.844161 Dram Type= 6, Freq= 0, CH_1, rank 1
3353 23:03:20.847527 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3354 23:03:20.847615 ==
3355 23:03:20.847679
3356 23:03:20.847738
3357 23:03:20.850931 TX Vref Scan disable
3358 23:03:20.851014 == TX Byte 0 ==
3359 23:03:20.857506 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3360 23:03:20.860880 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3361 23:03:20.860968 == TX Byte 1 ==
3362 23:03:20.867471 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3363 23:03:20.871284 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3364 23:03:20.871378 ==
3365 23:03:20.874405 Dram Type= 6, Freq= 0, CH_1, rank 1
3366 23:03:20.877586 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3367 23:03:20.877671 ==
3368 23:03:20.890437 TX Vref=22, minBit 8, minWin=25, winSum=418
3369 23:03:20.893717 TX Vref=24, minBit 8, minWin=25, winSum=426
3370 23:03:20.896982 TX Vref=26, minBit 8, minWin=26, winSum=429
3371 23:03:20.900376 TX Vref=28, minBit 8, minWin=26, winSum=430
3372 23:03:20.903687 TX Vref=30, minBit 9, minWin=26, winSum=433
3373 23:03:20.907073 TX Vref=32, minBit 9, minWin=26, winSum=430
3374 23:03:20.913652 [TxChooseVref] Worse bit 9, Min win 26, Win sum 433, Final Vref 30
3375 23:03:20.913761
3376 23:03:20.916867 Final TX Range 1 Vref 30
3377 23:03:20.916953
3378 23:03:20.917019 ==
3379 23:03:20.920324 Dram Type= 6, Freq= 0, CH_1, rank 1
3380 23:03:20.923639 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3381 23:03:20.923726 ==
3382 23:03:20.923792
3383 23:03:20.927149
3384 23:03:20.927232 TX Vref Scan disable
3385 23:03:20.930610 == TX Byte 0 ==
3386 23:03:20.933579 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3387 23:03:20.937163 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3388 23:03:20.940480 == TX Byte 1 ==
3389 23:03:20.943599 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3390 23:03:20.946915 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3391 23:03:20.947010
3392 23:03:20.950338 [DATLAT]
3393 23:03:20.950427 Freq=1200, CH1 RK1
3394 23:03:20.950514
3395 23:03:20.953621 DATLAT Default: 0xc
3396 23:03:20.953707 0, 0xFFFF, sum = 0
3397 23:03:20.957014 1, 0xFFFF, sum = 0
3398 23:03:20.957104 2, 0xFFFF, sum = 0
3399 23:03:20.960408 3, 0xFFFF, sum = 0
3400 23:03:20.960529 4, 0xFFFF, sum = 0
3401 23:03:20.963634 5, 0xFFFF, sum = 0
3402 23:03:20.963722 6, 0xFFFF, sum = 0
3403 23:03:20.966874 7, 0xFFFF, sum = 0
3404 23:03:20.970311 8, 0xFFFF, sum = 0
3405 23:03:20.970401 9, 0xFFFF, sum = 0
3406 23:03:20.973405 10, 0xFFFF, sum = 0
3407 23:03:20.973490 11, 0x0, sum = 1
3408 23:03:20.976985 12, 0x0, sum = 2
3409 23:03:20.977071 13, 0x0, sum = 3
3410 23:03:20.977138 14, 0x0, sum = 4
3411 23:03:20.980538 best_step = 12
3412 23:03:20.980637
3413 23:03:20.980703 ==
3414 23:03:20.983489 Dram Type= 6, Freq= 0, CH_1, rank 1
3415 23:03:20.986809 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3416 23:03:20.986893 ==
3417 23:03:20.990077 RX Vref Scan: 0
3418 23:03:20.990160
3419 23:03:20.993323 RX Vref 0 -> 0, step: 1
3420 23:03:20.993406
3421 23:03:20.993470 RX Delay -29 -> 252, step: 4
3422 23:03:21.000660 iDelay=199, Bit 0, Center 116 (47 ~ 186) 140
3423 23:03:21.004041 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3424 23:03:21.007191 iDelay=199, Bit 2, Center 108 (39 ~ 178) 140
3425 23:03:21.010821 iDelay=199, Bit 3, Center 112 (43 ~ 182) 140
3426 23:03:21.014067 iDelay=199, Bit 4, Center 114 (43 ~ 186) 144
3427 23:03:21.020727 iDelay=199, Bit 5, Center 124 (51 ~ 198) 148
3428 23:03:21.024147 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
3429 23:03:21.027364 iDelay=199, Bit 7, Center 114 (43 ~ 186) 144
3430 23:03:21.030758 iDelay=199, Bit 8, Center 86 (19 ~ 154) 136
3431 23:03:21.034270 iDelay=199, Bit 9, Center 92 (27 ~ 158) 132
3432 23:03:21.040604 iDelay=199, Bit 10, Center 106 (39 ~ 174) 136
3433 23:03:21.044029 iDelay=199, Bit 11, Center 98 (31 ~ 166) 136
3434 23:03:21.047481 iDelay=199, Bit 12, Center 112 (43 ~ 182) 140
3435 23:03:21.050699 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
3436 23:03:21.053945 iDelay=199, Bit 14, Center 114 (47 ~ 182) 136
3437 23:03:21.060867 iDelay=199, Bit 15, Center 110 (43 ~ 178) 136
3438 23:03:21.060982 ==
3439 23:03:21.063842 Dram Type= 6, Freq= 0, CH_1, rank 1
3440 23:03:21.067287 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3441 23:03:21.067386 ==
3442 23:03:21.067451 DQS Delay:
3443 23:03:21.070610 DQS0 = 0, DQS1 = 0
3444 23:03:21.070695 DQM Delay:
3445 23:03:21.073935 DQM0 = 115, DQM1 = 103
3446 23:03:21.074021 DQ Delay:
3447 23:03:21.077360 DQ0 =116, DQ1 =110, DQ2 =108, DQ3 =112
3448 23:03:21.080673 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =114
3449 23:03:21.084265 DQ8 =86, DQ9 =92, DQ10 =106, DQ11 =98
3450 23:03:21.087513 DQ12 =112, DQ13 =112, DQ14 =114, DQ15 =110
3451 23:03:21.087603
3452 23:03:21.087668
3453 23:03:21.097492 [DQSOSCAuto] RK1, (LSB)MR18= 0xd0d, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
3454 23:03:21.097609 CH1 RK1: MR19=404, MR18=D0D
3455 23:03:21.103992 CH1_RK1: MR19=0x404, MR18=0xD0D, DQSOSC=405, MR23=63, INC=39, DEC=26
3456 23:03:21.107550 [RxdqsGatingPostProcess] freq 1200
3457 23:03:21.114048 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3458 23:03:21.117511 Pre-setting of DQS Precalculation
3459 23:03:21.120797 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3460 23:03:21.127345 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3461 23:03:21.137589 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3462 23:03:21.137728
3463 23:03:21.137798
3464 23:03:21.140944 [Calibration Summary] 2400 Mbps
3465 23:03:21.141028 CH 0, Rank 0
3466 23:03:21.143959 SW Impedance : PASS
3467 23:03:21.144043 DUTY Scan : NO K
3468 23:03:21.147239 ZQ Calibration : PASS
3469 23:03:21.150654 Jitter Meter : NO K
3470 23:03:21.150742 CBT Training : PASS
3471 23:03:21.154010 Write leveling : PASS
3472 23:03:21.154094 RX DQS gating : PASS
3473 23:03:21.157200 RX DQ/DQS(RDDQC) : PASS
3474 23:03:21.160549 TX DQ/DQS : PASS
3475 23:03:21.160637 RX DATLAT : PASS
3476 23:03:21.163954 RX DQ/DQS(Engine): PASS
3477 23:03:21.167357 TX OE : NO K
3478 23:03:21.167477 All Pass.
3479 23:03:21.167548
3480 23:03:21.167610 CH 0, Rank 1
3481 23:03:21.170595 SW Impedance : PASS
3482 23:03:21.173901 DUTY Scan : NO K
3483 23:03:21.173988 ZQ Calibration : PASS
3484 23:03:21.177252 Jitter Meter : NO K
3485 23:03:21.180536 CBT Training : PASS
3486 23:03:21.180635 Write leveling : PASS
3487 23:03:21.184123 RX DQS gating : PASS
3488 23:03:21.187154 RX DQ/DQS(RDDQC) : PASS
3489 23:03:21.187251 TX DQ/DQS : PASS
3490 23:03:21.190584 RX DATLAT : PASS
3491 23:03:21.193815 RX DQ/DQS(Engine): PASS
3492 23:03:21.193910 TX OE : NO K
3493 23:03:21.193998 All Pass.
3494 23:03:21.197116
3495 23:03:21.197205 CH 1, Rank 0
3496 23:03:21.200438 SW Impedance : PASS
3497 23:03:21.200559 DUTY Scan : NO K
3498 23:03:21.203835 ZQ Calibration : PASS
3499 23:03:21.203919 Jitter Meter : NO K
3500 23:03:21.207167 CBT Training : PASS
3501 23:03:21.210538 Write leveling : PASS
3502 23:03:21.210626 RX DQS gating : PASS
3503 23:03:21.213949 RX DQ/DQS(RDDQC) : PASS
3504 23:03:21.217072 TX DQ/DQS : PASS
3505 23:03:21.217162 RX DATLAT : PASS
3506 23:03:21.220490 RX DQ/DQS(Engine): PASS
3507 23:03:21.223936 TX OE : NO K
3508 23:03:21.224044 All Pass.
3509 23:03:21.224117
3510 23:03:21.224196 CH 1, Rank 1
3511 23:03:21.227036 SW Impedance : PASS
3512 23:03:21.230563 DUTY Scan : NO K
3513 23:03:21.230651 ZQ Calibration : PASS
3514 23:03:21.233567 Jitter Meter : NO K
3515 23:03:21.236984 CBT Training : PASS
3516 23:03:21.237078 Write leveling : PASS
3517 23:03:21.240437 RX DQS gating : PASS
3518 23:03:21.243881 RX DQ/DQS(RDDQC) : PASS
3519 23:03:21.244007 TX DQ/DQS : PASS
3520 23:03:21.246980 RX DATLAT : PASS
3521 23:03:21.247093 RX DQ/DQS(Engine): PASS
3522 23:03:21.250451 TX OE : NO K
3523 23:03:21.250569 All Pass.
3524 23:03:21.250685
3525 23:03:21.253857 DramC Write-DBI off
3526 23:03:21.257349 PER_BANK_REFRESH: Hybrid Mode
3527 23:03:21.257438 TX_TRACKING: ON
3528 23:03:21.267084 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3529 23:03:21.270543 [FAST_K] Save calibration result to emmc
3530 23:03:21.273832 dramc_set_vcore_voltage set vcore to 650000
3531 23:03:21.277134 Read voltage for 600, 5
3532 23:03:21.277308 Vio18 = 0
3533 23:03:21.277410 Vcore = 650000
3534 23:03:21.280472 Vdram = 0
3535 23:03:21.280609 Vddq = 0
3536 23:03:21.280675 Vmddr = 0
3537 23:03:21.286956 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3538 23:03:21.290297 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3539 23:03:21.293638 MEM_TYPE=3, freq_sel=19
3540 23:03:21.297190 sv_algorithm_assistance_LP4_1600
3541 23:03:21.300321 ============ PULL DRAM RESETB DOWN ============
3542 23:03:21.306820 ========== PULL DRAM RESETB DOWN end =========
3543 23:03:21.310416 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3544 23:03:21.313633 ===================================
3545 23:03:21.316871 LPDDR4 DRAM CONFIGURATION
3546 23:03:21.320405 ===================================
3547 23:03:21.320561 EX_ROW_EN[0] = 0x0
3548 23:03:21.323452 EX_ROW_EN[1] = 0x0
3549 23:03:21.323537 LP4Y_EN = 0x0
3550 23:03:21.326872 WORK_FSP = 0x0
3551 23:03:21.326957 WL = 0x2
3552 23:03:21.330104 RL = 0x2
3553 23:03:21.330188 BL = 0x2
3554 23:03:21.333331 RPST = 0x0
3555 23:03:21.333421 RD_PRE = 0x0
3556 23:03:21.336788 WR_PRE = 0x1
3557 23:03:21.340040 WR_PST = 0x0
3558 23:03:21.340128 DBI_WR = 0x0
3559 23:03:21.343260 DBI_RD = 0x0
3560 23:03:21.343348 OTF = 0x1
3561 23:03:21.346594 ===================================
3562 23:03:21.350105 ===================================
3563 23:03:21.350195 ANA top config
3564 23:03:21.353245 ===================================
3565 23:03:21.356570 DLL_ASYNC_EN = 0
3566 23:03:21.359931 ALL_SLAVE_EN = 1
3567 23:03:21.363170 NEW_RANK_MODE = 1
3568 23:03:21.366614 DLL_IDLE_MODE = 1
3569 23:03:21.366705 LP45_APHY_COMB_EN = 1
3570 23:03:21.369768 TX_ODT_DIS = 1
3571 23:03:21.373155 NEW_8X_MODE = 1
3572 23:03:21.376389 ===================================
3573 23:03:21.379639 ===================================
3574 23:03:21.382969 data_rate = 1200
3575 23:03:21.386296 CKR = 1
3576 23:03:21.389409 DQ_P2S_RATIO = 8
3577 23:03:21.393073 ===================================
3578 23:03:21.393166 CA_P2S_RATIO = 8
3579 23:03:21.396285 DQ_CA_OPEN = 0
3580 23:03:21.399476 DQ_SEMI_OPEN = 0
3581 23:03:21.402676 CA_SEMI_OPEN = 0
3582 23:03:21.406122 CA_FULL_RATE = 0
3583 23:03:21.409694 DQ_CKDIV4_EN = 1
3584 23:03:21.409779 CA_CKDIV4_EN = 1
3585 23:03:21.412674 CA_PREDIV_EN = 0
3586 23:03:21.415930 PH8_DLY = 0
3587 23:03:21.419131 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3588 23:03:21.422406 DQ_AAMCK_DIV = 4
3589 23:03:21.425882 CA_AAMCK_DIV = 4
3590 23:03:21.425965 CA_ADMCK_DIV = 4
3591 23:03:21.429101 DQ_TRACK_CA_EN = 0
3592 23:03:21.432432 CA_PICK = 600
3593 23:03:21.435749 CA_MCKIO = 600
3594 23:03:21.439382 MCKIO_SEMI = 0
3595 23:03:21.442311 PLL_FREQ = 2288
3596 23:03:21.445828 DQ_UI_PI_RATIO = 32
3597 23:03:21.445914 CA_UI_PI_RATIO = 0
3598 23:03:21.449071 ===================================
3599 23:03:21.452371 ===================================
3600 23:03:21.455828 memory_type:LPDDR4
3601 23:03:21.459017 GP_NUM : 10
3602 23:03:21.459101 SRAM_EN : 1
3603 23:03:21.462382 MD32_EN : 0
3604 23:03:21.465500 ===================================
3605 23:03:21.468941 [ANA_INIT] >>>>>>>>>>>>>>
3606 23:03:21.472071 <<<<<< [CONFIGURE PHASE]: ANA_TX
3607 23:03:21.475639 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3608 23:03:21.478728 ===================================
3609 23:03:21.478813 data_rate = 1200,PCW = 0X5800
3610 23:03:21.482159 ===================================
3611 23:03:21.485437 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3612 23:03:21.492210 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3613 23:03:21.498668 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3614 23:03:21.501915 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3615 23:03:21.505436 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3616 23:03:21.508628 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3617 23:03:21.511871 [ANA_INIT] flow start
3618 23:03:21.515096 [ANA_INIT] PLL >>>>>>>>
3619 23:03:21.515179 [ANA_INIT] PLL <<<<<<<<
3620 23:03:21.518493 [ANA_INIT] MIDPI >>>>>>>>
3621 23:03:21.521703 [ANA_INIT] MIDPI <<<<<<<<
3622 23:03:21.521787 [ANA_INIT] DLL >>>>>>>>
3623 23:03:21.525189 [ANA_INIT] flow end
3624 23:03:21.528402 ============ LP4 DIFF to SE enter ============
3625 23:03:21.531712 ============ LP4 DIFF to SE exit ============
3626 23:03:21.535031 [ANA_INIT] <<<<<<<<<<<<<
3627 23:03:21.538184 [Flow] Enable top DCM control >>>>>
3628 23:03:21.541687 [Flow] Enable top DCM control <<<<<
3629 23:03:21.544807 Enable DLL master slave shuffle
3630 23:03:21.551309 ==============================================================
3631 23:03:21.551393 Gating Mode config
3632 23:03:21.558140 ==============================================================
3633 23:03:21.561499 Config description:
3634 23:03:21.568502 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3635 23:03:21.574670 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3636 23:03:21.581217 SELPH_MODE 0: By rank 1: By Phase
3637 23:03:21.588297 ==============================================================
3638 23:03:21.588384 GAT_TRACK_EN = 1
3639 23:03:21.591260 RX_GATING_MODE = 2
3640 23:03:21.594417 RX_GATING_TRACK_MODE = 2
3641 23:03:21.597947 SELPH_MODE = 1
3642 23:03:21.601097 PICG_EARLY_EN = 1
3643 23:03:21.604301 VALID_LAT_VALUE = 1
3644 23:03:21.611183 ==============================================================
3645 23:03:21.614446 Enter into Gating configuration >>>>
3646 23:03:21.617851 Exit from Gating configuration <<<<
3647 23:03:21.620997 Enter into DVFS_PRE_config >>>>>
3648 23:03:21.630972 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3649 23:03:21.634123 Exit from DVFS_PRE_config <<<<<
3650 23:03:21.637590 Enter into PICG configuration >>>>
3651 23:03:21.640886 Exit from PICG configuration <<<<
3652 23:03:21.644243 [RX_INPUT] configuration >>>>>
3653 23:03:21.644356 [RX_INPUT] configuration <<<<<
3654 23:03:21.651006 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3655 23:03:21.657651 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3656 23:03:21.663842 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3657 23:03:21.667353 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3658 23:03:21.673877 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3659 23:03:21.680605 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3660 23:03:21.683845 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3661 23:03:21.687089 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3662 23:03:21.693859 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3663 23:03:21.697025 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3664 23:03:21.700311 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3665 23:03:21.707034 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3666 23:03:21.710249 ===================================
3667 23:03:21.710335 LPDDR4 DRAM CONFIGURATION
3668 23:03:21.713816 ===================================
3669 23:03:21.716941 EX_ROW_EN[0] = 0x0
3670 23:03:21.720240 EX_ROW_EN[1] = 0x0
3671 23:03:21.720326 LP4Y_EN = 0x0
3672 23:03:21.723924 WORK_FSP = 0x0
3673 23:03:21.724026 WL = 0x2
3674 23:03:21.727065 RL = 0x2
3675 23:03:21.727148 BL = 0x2
3676 23:03:21.730229 RPST = 0x0
3677 23:03:21.730312 RD_PRE = 0x0
3678 23:03:21.733420 WR_PRE = 0x1
3679 23:03:21.733505 WR_PST = 0x0
3680 23:03:21.736766 DBI_WR = 0x0
3681 23:03:21.736850 DBI_RD = 0x0
3682 23:03:21.739988 OTF = 0x1
3683 23:03:21.743276 ===================================
3684 23:03:21.746728 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3685 23:03:21.749914 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3686 23:03:21.756403 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3687 23:03:21.759760 ===================================
3688 23:03:21.759843 LPDDR4 DRAM CONFIGURATION
3689 23:03:21.763160 ===================================
3690 23:03:21.766379 EX_ROW_EN[0] = 0x10
3691 23:03:21.769609 EX_ROW_EN[1] = 0x0
3692 23:03:21.769692 LP4Y_EN = 0x0
3693 23:03:21.772967 WORK_FSP = 0x0
3694 23:03:21.773050 WL = 0x2
3695 23:03:21.776209 RL = 0x2
3696 23:03:21.776292 BL = 0x2
3697 23:03:21.779685 RPST = 0x0
3698 23:03:21.779769 RD_PRE = 0x0
3699 23:03:21.783043 WR_PRE = 0x1
3700 23:03:21.783125 WR_PST = 0x0
3701 23:03:21.786211 DBI_WR = 0x0
3702 23:03:21.786293 DBI_RD = 0x0
3703 23:03:21.789493 OTF = 0x1
3704 23:03:21.792868 ===================================
3705 23:03:21.799263 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3706 23:03:21.802705 nWR fixed to 30
3707 23:03:21.806272 [ModeRegInit_LP4] CH0 RK0
3708 23:03:21.806354 [ModeRegInit_LP4] CH0 RK1
3709 23:03:21.809269 [ModeRegInit_LP4] CH1 RK0
3710 23:03:21.812912 [ModeRegInit_LP4] CH1 RK1
3711 23:03:21.812994 match AC timing 16
3712 23:03:21.819468 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3713 23:03:21.822574 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3714 23:03:21.826047 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3715 23:03:21.832320 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3716 23:03:21.835838 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3717 23:03:21.835955 ==
3718 23:03:21.839023 Dram Type= 6, Freq= 0, CH_0, rank 0
3719 23:03:21.842412 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3720 23:03:21.842496 ==
3721 23:03:21.848892 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3722 23:03:21.856156 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3723 23:03:21.858930 [CA 0] Center 35 (5~66) winsize 62
3724 23:03:21.862363 [CA 1] Center 35 (5~66) winsize 62
3725 23:03:21.865560 [CA 2] Center 34 (4~65) winsize 62
3726 23:03:21.869023 [CA 3] Center 34 (4~65) winsize 62
3727 23:03:21.872223 [CA 4] Center 33 (3~64) winsize 62
3728 23:03:21.875363 [CA 5] Center 33 (3~64) winsize 62
3729 23:03:21.875446
3730 23:03:21.878798 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3731 23:03:21.878881
3732 23:03:21.882112 [CATrainingPosCal] consider 1 rank data
3733 23:03:21.885622 u2DelayCellTimex100 = 270/100 ps
3734 23:03:21.888745 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3735 23:03:21.892023 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3736 23:03:21.895355 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3737 23:03:21.898719 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3738 23:03:21.902118 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3739 23:03:21.908581 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3740 23:03:21.908665
3741 23:03:21.911844 CA PerBit enable=1, Macro0, CA PI delay=33
3742 23:03:21.911926
3743 23:03:21.915260 [CBTSetCACLKResult] CA Dly = 33
3744 23:03:21.915343 CS Dly: 6 (0~37)
3745 23:03:21.915408 ==
3746 23:03:21.918459 Dram Type= 6, Freq= 0, CH_0, rank 1
3747 23:03:21.921820 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3748 23:03:21.925021 ==
3749 23:03:21.928307 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3750 23:03:21.934845 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3751 23:03:21.938108 [CA 0] Center 36 (6~66) winsize 61
3752 23:03:21.941641 [CA 1] Center 35 (5~66) winsize 62
3753 23:03:21.944678 [CA 2] Center 34 (4~65) winsize 62
3754 23:03:21.948159 [CA 3] Center 34 (3~65) winsize 63
3755 23:03:21.951346 [CA 4] Center 33 (3~64) winsize 62
3756 23:03:21.954938 [CA 5] Center 33 (3~64) winsize 62
3757 23:03:21.955022
3758 23:03:21.958127 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3759 23:03:21.958210
3760 23:03:21.961466 [CATrainingPosCal] consider 2 rank data
3761 23:03:21.964525 u2DelayCellTimex100 = 270/100 ps
3762 23:03:21.967910 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3763 23:03:21.971310 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3764 23:03:21.974507 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3765 23:03:21.981353 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3766 23:03:21.984672 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3767 23:03:21.987748 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3768 23:03:21.987831
3769 23:03:21.991071 CA PerBit enable=1, Macro0, CA PI delay=33
3770 23:03:21.991154
3771 23:03:21.994440 [CBTSetCACLKResult] CA Dly = 33
3772 23:03:21.994527 CS Dly: 6 (0~37)
3773 23:03:21.994595
3774 23:03:21.997679 ----->DramcWriteLeveling(PI) begin...
3775 23:03:22.000896 ==
3776 23:03:22.000980 Dram Type= 6, Freq= 0, CH_0, rank 0
3777 23:03:22.007434 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3778 23:03:22.007518 ==
3779 23:03:22.010867 Write leveling (Byte 0): 30 => 30
3780 23:03:22.014161 Write leveling (Byte 1): 31 => 31
3781 23:03:22.017541 DramcWriteLeveling(PI) end<-----
3782 23:03:22.017623
3783 23:03:22.017688 ==
3784 23:03:22.020784 Dram Type= 6, Freq= 0, CH_0, rank 0
3785 23:03:22.024086 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3786 23:03:22.024168 ==
3787 23:03:22.027193 [Gating] SW mode calibration
3788 23:03:22.034043 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3789 23:03:22.040681 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3790 23:03:22.043856 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3791 23:03:22.047425 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3792 23:03:22.050472 0 5 8 | B1->B0 | 3232 3030 | 0 1 | (1 0) (1 0)
3793 23:03:22.057474 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3794 23:03:22.060443 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3795 23:03:22.067041 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3796 23:03:22.070389 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3797 23:03:22.073618 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3798 23:03:22.080408 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3799 23:03:22.083436 0 6 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
3800 23:03:22.086649 0 6 8 | B1->B0 | 2e2e 3131 | 0 0 | (0 0) (0 0)
3801 23:03:22.093430 0 6 12 | B1->B0 | 4040 4646 | 1 0 | (0 0) (0 0)
3802 23:03:22.096632 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3803 23:03:22.100064 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3804 23:03:22.103318 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3805 23:03:22.109986 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3806 23:03:22.113425 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3807 23:03:22.116511 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3808 23:03:22.123140 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3809 23:03:22.126588 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3810 23:03:22.129655 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3811 23:03:22.136369 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3812 23:03:22.139784 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3813 23:03:22.143135 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3814 23:03:22.149915 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3815 23:03:22.152927 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3816 23:03:22.156324 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3817 23:03:22.162848 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3818 23:03:22.166187 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3819 23:03:22.169501 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3820 23:03:22.176026 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3821 23:03:22.179444 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3822 23:03:22.182643 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3823 23:03:22.189141 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3824 23:03:22.192321 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3825 23:03:22.195694 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3826 23:03:22.199013 Total UI for P1: 0, mck2ui 16
3827 23:03:22.202434 best dqsien dly found for B0: ( 0, 9, 8)
3828 23:03:22.205691 Total UI for P1: 0, mck2ui 16
3829 23:03:22.209215 best dqsien dly found for B1: ( 0, 9, 8)
3830 23:03:22.212321 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
3831 23:03:22.215823 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
3832 23:03:22.215908
3833 23:03:22.222439 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
3834 23:03:22.225801 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
3835 23:03:22.228894 [Gating] SW calibration Done
3836 23:03:22.228980 ==
3837 23:03:22.232012 Dram Type= 6, Freq= 0, CH_0, rank 0
3838 23:03:22.235397 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3839 23:03:22.235486 ==
3840 23:03:22.235554 RX Vref Scan: 0
3841 23:03:22.235617
3842 23:03:22.238625 RX Vref 0 -> 0, step: 1
3843 23:03:22.238709
3844 23:03:22.242007 RX Delay -230 -> 252, step: 16
3845 23:03:22.245379 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
3846 23:03:22.248547 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
3847 23:03:22.255298 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
3848 23:03:22.258702 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
3849 23:03:22.261783 iDelay=218, Bit 4, Center 41 (-134 ~ 217) 352
3850 23:03:22.265185 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
3851 23:03:22.271955 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3852 23:03:22.275360 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
3853 23:03:22.278517 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3854 23:03:22.281911 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
3855 23:03:22.288636 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
3856 23:03:22.291766 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3857 23:03:22.295033 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3858 23:03:22.298251 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3859 23:03:22.304904 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3860 23:03:22.308314 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3861 23:03:22.308421 ==
3862 23:03:22.311648 Dram Type= 6, Freq= 0, CH_0, rank 0
3863 23:03:22.314928 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3864 23:03:22.315021 ==
3865 23:03:22.315089 DQS Delay:
3866 23:03:22.318468 DQS0 = 0, DQS1 = 0
3867 23:03:22.318555 DQM Delay:
3868 23:03:22.322086 DQM0 = 37, DQM1 = 33
3869 23:03:22.322177 DQ Delay:
3870 23:03:22.324953 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
3871 23:03:22.328282 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
3872 23:03:22.331539 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
3873 23:03:22.334701 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3874 23:03:22.334809
3875 23:03:22.334882
3876 23:03:22.334944 ==
3877 23:03:22.338161 Dram Type= 6, Freq= 0, CH_0, rank 0
3878 23:03:22.341569 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3879 23:03:22.344910 ==
3880 23:03:22.345012
3881 23:03:22.345078
3882 23:03:22.345139 TX Vref Scan disable
3883 23:03:22.348230 == TX Byte 0 ==
3884 23:03:22.351466 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
3885 23:03:22.358027 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
3886 23:03:22.358117 == TX Byte 1 ==
3887 23:03:22.361337 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
3888 23:03:22.367854 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
3889 23:03:22.367938 ==
3890 23:03:22.371350 Dram Type= 6, Freq= 0, CH_0, rank 0
3891 23:03:22.374565 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3892 23:03:22.374649 ==
3893 23:03:22.374715
3894 23:03:22.374776
3895 23:03:22.377717 TX Vref Scan disable
3896 23:03:22.381099 == TX Byte 0 ==
3897 23:03:22.384433 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
3898 23:03:22.387745 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
3899 23:03:22.391063 == TX Byte 1 ==
3900 23:03:22.394327 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
3901 23:03:22.397689 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
3902 23:03:22.397772
3903 23:03:22.397838 [DATLAT]
3904 23:03:22.400971 Freq=600, CH0 RK0
3905 23:03:22.401055
3906 23:03:22.404342 DATLAT Default: 0x9
3907 23:03:22.404424 0, 0xFFFF, sum = 0
3908 23:03:22.407478 1, 0xFFFF, sum = 0
3909 23:03:22.407562 2, 0xFFFF, sum = 0
3910 23:03:22.410979 3, 0xFFFF, sum = 0
3911 23:03:22.411064 4, 0xFFFF, sum = 0
3912 23:03:22.414096 5, 0xFFFF, sum = 0
3913 23:03:22.414180 6, 0xFFFF, sum = 0
3914 23:03:22.417451 7, 0x0, sum = 1
3915 23:03:22.417535 8, 0x0, sum = 2
3916 23:03:22.420919 9, 0x0, sum = 3
3917 23:03:22.421003 10, 0x0, sum = 4
3918 23:03:22.421070 best_step = 8
3919 23:03:22.421130
3920 23:03:22.424036 ==
3921 23:03:22.424118 Dram Type= 6, Freq= 0, CH_0, rank 0
3922 23:03:22.430770 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3923 23:03:22.430889 ==
3924 23:03:22.430959 RX Vref Scan: 1
3925 23:03:22.431021
3926 23:03:22.433981 RX Vref 0 -> 0, step: 1
3927 23:03:22.434063
3928 23:03:22.437247 RX Delay -195 -> 252, step: 8
3929 23:03:22.437331
3930 23:03:22.440525 Set Vref, RX VrefLevel [Byte0]: 47
3931 23:03:22.443822 [Byte1]: 48
3932 23:03:22.443906
3933 23:03:22.447233 Final RX Vref Byte 0 = 47 to rank0
3934 23:03:22.450548 Final RX Vref Byte 1 = 48 to rank0
3935 23:03:22.453761 Final RX Vref Byte 0 = 47 to rank1
3936 23:03:22.457496 Final RX Vref Byte 1 = 48 to rank1==
3937 23:03:22.460355 Dram Type= 6, Freq= 0, CH_0, rank 0
3938 23:03:22.463625 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3939 23:03:22.466900 ==
3940 23:03:22.466983 DQS Delay:
3941 23:03:22.467050 DQS0 = 0, DQS1 = 0
3942 23:03:22.470328 DQM Delay:
3943 23:03:22.470411 DQM0 = 41, DQM1 = 31
3944 23:03:22.473503 DQ Delay:
3945 23:03:22.477022 DQ0 =40, DQ1 =40, DQ2 =40, DQ3 =36
3946 23:03:22.477106 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
3947 23:03:22.480349 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
3948 23:03:22.483405 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =44
3949 23:03:22.486772
3950 23:03:22.486855
3951 23:03:22.493520 [DQSOSCAuto] RK0, (LSB)MR18= 0x4e4e, (MSB)MR19= 0x808, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
3952 23:03:22.497047 CH0 RK0: MR19=808, MR18=4E4E
3953 23:03:22.503478 CH0_RK0: MR19=0x808, MR18=0x4E4E, DQSOSC=395, MR23=63, INC=168, DEC=112
3954 23:03:22.503563
3955 23:03:22.506694 ----->DramcWriteLeveling(PI) begin...
3956 23:03:22.506778 ==
3957 23:03:22.509993 Dram Type= 6, Freq= 0, CH_0, rank 1
3958 23:03:22.513700 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3959 23:03:22.513782 ==
3960 23:03:22.516922 Write leveling (Byte 0): 30 => 30
3961 23:03:22.519918 Write leveling (Byte 1): 30 => 30
3962 23:03:22.523167 DramcWriteLeveling(PI) end<-----
3963 23:03:22.523249
3964 23:03:22.523315 ==
3965 23:03:22.526805 Dram Type= 6, Freq= 0, CH_0, rank 1
3966 23:03:22.529835 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3967 23:03:22.529917 ==
3968 23:03:22.533236 [Gating] SW mode calibration
3969 23:03:22.540100 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3970 23:03:22.546329 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3971 23:03:22.549781 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3972 23:03:22.556259 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3973 23:03:22.559583 0 5 8 | B1->B0 | 3434 3232 | 0 1 | (0 1) (0 0)
3974 23:03:22.562964 0 5 12 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
3975 23:03:22.566398 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3976 23:03:22.572882 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3977 23:03:22.576342 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3978 23:03:22.579510 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3979 23:03:22.586120 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3980 23:03:22.589249 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3981 23:03:22.592511 0 6 8 | B1->B0 | 2727 3636 | 0 0 | (0 0) (1 1)
3982 23:03:22.599347 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3983 23:03:22.602491 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3984 23:03:22.605922 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3985 23:03:22.612438 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3986 23:03:22.615687 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3987 23:03:22.619150 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3988 23:03:22.625559 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3989 23:03:22.628901 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3990 23:03:22.632453 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3991 23:03:22.638872 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3992 23:03:22.642024 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3993 23:03:22.645467 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3994 23:03:22.652164 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 23:03:22.655435 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 23:03:22.658592 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 23:03:22.665325 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 23:03:22.668817 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 23:03:22.671888 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 23:03:22.678560 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 23:03:22.681900 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 23:03:22.685227 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 23:03:22.691516 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 23:03:22.694984 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4005 23:03:22.698360 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4006 23:03:22.704883 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4007 23:03:22.708317 Total UI for P1: 0, mck2ui 16
4008 23:03:22.711664 best dqsien dly found for B0: ( 0, 9, 6)
4009 23:03:22.711748 Total UI for P1: 0, mck2ui 16
4010 23:03:22.718214 best dqsien dly found for B1: ( 0, 9, 10)
4011 23:03:22.721363 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
4012 23:03:22.724700 best DQS1 dly(MCK, UI, PI) = (0, 9, 10)
4013 23:03:22.724782
4014 23:03:22.727852 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
4015 23:03:22.731357 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10)
4016 23:03:22.734636 [Gating] SW calibration Done
4017 23:03:22.734720 ==
4018 23:03:22.737853 Dram Type= 6, Freq= 0, CH_0, rank 1
4019 23:03:22.741199 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4020 23:03:22.741302 ==
4021 23:03:22.744694 RX Vref Scan: 0
4022 23:03:22.744784
4023 23:03:22.744851 RX Vref 0 -> 0, step: 1
4024 23:03:22.747909
4025 23:03:22.747992 RX Delay -230 -> 252, step: 16
4026 23:03:22.754410 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4027 23:03:22.757691 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4028 23:03:22.760988 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4029 23:03:22.764530 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4030 23:03:22.770880 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4031 23:03:22.774406 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4032 23:03:22.777613 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4033 23:03:22.780949 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4034 23:03:22.784096 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4035 23:03:22.790837 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4036 23:03:22.794382 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4037 23:03:22.797331 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4038 23:03:22.800736 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4039 23:03:22.807249 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4040 23:03:22.810648 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4041 23:03:22.814268 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4042 23:03:22.814351 ==
4043 23:03:22.817722 Dram Type= 6, Freq= 0, CH_0, rank 1
4044 23:03:22.823938 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4045 23:03:22.824024 ==
4046 23:03:22.824091 DQS Delay:
4047 23:03:22.824152 DQS0 = 0, DQS1 = 0
4048 23:03:22.827250 DQM Delay:
4049 23:03:22.827333 DQM0 = 44, DQM1 = 34
4050 23:03:22.830549 DQ Delay:
4051 23:03:22.833883 DQ0 =33, DQ1 =49, DQ2 =33, DQ3 =33
4052 23:03:22.833967 DQ4 =57, DQ5 =33, DQ6 =57, DQ7 =57
4053 23:03:22.837244 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4054 23:03:22.843707 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4055 23:03:22.843796
4056 23:03:22.843862
4057 23:03:22.843923 ==
4058 23:03:22.847347 Dram Type= 6, Freq= 0, CH_0, rank 1
4059 23:03:22.850356 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4060 23:03:22.850440 ==
4061 23:03:22.850506
4062 23:03:22.850567
4063 23:03:22.854058 TX Vref Scan disable
4064 23:03:22.854141 == TX Byte 0 ==
4065 23:03:22.860371 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4066 23:03:22.863975 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4067 23:03:22.864059 == TX Byte 1 ==
4068 23:03:22.870576 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4069 23:03:22.873747 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4070 23:03:22.873831 ==
4071 23:03:22.877113 Dram Type= 6, Freq= 0, CH_0, rank 1
4072 23:03:22.880425 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4073 23:03:22.880516 ==
4074 23:03:22.880584
4075 23:03:22.880645
4076 23:03:22.883752 TX Vref Scan disable
4077 23:03:22.887307 == TX Byte 0 ==
4078 23:03:22.890772 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4079 23:03:22.893681 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4080 23:03:22.897164 == TX Byte 1 ==
4081 23:03:22.900514 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4082 23:03:22.903955 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4083 23:03:22.904043
4084 23:03:22.907050 [DATLAT]
4085 23:03:22.907133 Freq=600, CH0 RK1
4086 23:03:22.907199
4087 23:03:22.910314 DATLAT Default: 0x8
4088 23:03:22.910396 0, 0xFFFF, sum = 0
4089 23:03:22.913894 1, 0xFFFF, sum = 0
4090 23:03:22.913978 2, 0xFFFF, sum = 0
4091 23:03:22.916998 3, 0xFFFF, sum = 0
4092 23:03:22.917081 4, 0xFFFF, sum = 0
4093 23:03:22.920240 5, 0xFFFF, sum = 0
4094 23:03:22.920325 6, 0xFFFF, sum = 0
4095 23:03:22.923605 7, 0x0, sum = 1
4096 23:03:22.923689 8, 0x0, sum = 2
4097 23:03:22.926951 9, 0x0, sum = 3
4098 23:03:22.927035 10, 0x0, sum = 4
4099 23:03:22.930105 best_step = 8
4100 23:03:22.930187
4101 23:03:22.930252 ==
4102 23:03:22.933721 Dram Type= 6, Freq= 0, CH_0, rank 1
4103 23:03:22.936924 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4104 23:03:22.937010 ==
4105 23:03:22.940330 RX Vref Scan: 0
4106 23:03:22.940412
4107 23:03:22.940478 RX Vref 0 -> 0, step: 1
4108 23:03:22.940571
4109 23:03:22.943343 RX Delay -195 -> 252, step: 8
4110 23:03:22.950492 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4111 23:03:22.953763 iDelay=205, Bit 1, Center 44 (-115 ~ 204) 320
4112 23:03:22.956905 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4113 23:03:22.960267 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4114 23:03:22.966968 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4115 23:03:22.970358 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4116 23:03:22.973624 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4117 23:03:22.976944 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4118 23:03:22.980288 iDelay=205, Bit 8, Center 20 (-131 ~ 172) 304
4119 23:03:22.987029 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4120 23:03:22.990097 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4121 23:03:22.993478 iDelay=205, Bit 11, Center 20 (-131 ~ 172) 304
4122 23:03:22.996715 iDelay=205, Bit 12, Center 36 (-115 ~ 188) 304
4123 23:03:23.003561 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4124 23:03:23.006659 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4125 23:03:23.010144 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4126 23:03:23.010228 ==
4127 23:03:23.013173 Dram Type= 6, Freq= 0, CH_0, rank 1
4128 23:03:23.019911 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4129 23:03:23.019998 ==
4130 23:03:23.020064 DQS Delay:
4131 23:03:23.020124 DQS0 = 0, DQS1 = 0
4132 23:03:23.023432 DQM Delay:
4133 23:03:23.023514 DQM0 = 41, DQM1 = 32
4134 23:03:23.026544 DQ Delay:
4135 23:03:23.029793 DQ0 =36, DQ1 =44, DQ2 =40, DQ3 =36
4136 23:03:23.029876 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4137 23:03:23.033190 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =20
4138 23:03:23.036694 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =44
4139 23:03:23.039990
4140 23:03:23.040084
4141 23:03:23.046690 [DQSOSCAuto] RK1, (LSB)MR18= 0x6e6e, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
4142 23:03:23.049888 CH0 RK1: MR19=808, MR18=6E6E
4143 23:03:23.056906 CH0_RK1: MR19=0x808, MR18=0x6E6E, DQSOSC=389, MR23=63, INC=173, DEC=115
4144 23:03:23.059720 [RxdqsGatingPostProcess] freq 600
4145 23:03:23.062881 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4146 23:03:23.066394 Pre-setting of DQS Precalculation
4147 23:03:23.072908 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4148 23:03:23.072993 ==
4149 23:03:23.076112 Dram Type= 6, Freq= 0, CH_1, rank 0
4150 23:03:23.079492 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4151 23:03:23.079585 ==
4152 23:03:23.086387 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4153 23:03:23.089416 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4154 23:03:23.093796 [CA 0] Center 35 (5~66) winsize 62
4155 23:03:23.097059 [CA 1] Center 35 (4~66) winsize 63
4156 23:03:23.100390 [CA 2] Center 33 (3~64) winsize 62
4157 23:03:23.103689 [CA 3] Center 33 (3~64) winsize 62
4158 23:03:23.106907 [CA 4] Center 33 (2~64) winsize 63
4159 23:03:23.110269 [CA 5] Center 33 (2~64) winsize 63
4160 23:03:23.110349
4161 23:03:23.113558 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4162 23:03:23.113639
4163 23:03:23.116845 [CATrainingPosCal] consider 1 rank data
4164 23:03:23.120125 u2DelayCellTimex100 = 270/100 ps
4165 23:03:23.123419 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4166 23:03:23.130089 CA1 delay=35 (4~66),Diff = 2 PI (19 cell)
4167 23:03:23.133446 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4168 23:03:23.136840 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4169 23:03:23.140003 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
4170 23:03:23.143435 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4171 23:03:23.143519
4172 23:03:23.146769 CA PerBit enable=1, Macro0, CA PI delay=33
4173 23:03:23.146852
4174 23:03:23.150067 [CBTSetCACLKResult] CA Dly = 33
4175 23:03:23.153468 CS Dly: 4 (0~35)
4176 23:03:23.153555 ==
4177 23:03:23.156515 Dram Type= 6, Freq= 0, CH_1, rank 1
4178 23:03:23.159986 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4179 23:03:23.160084 ==
4180 23:03:23.166613 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4181 23:03:23.169704 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4182 23:03:23.173948 [CA 0] Center 35 (5~66) winsize 62
4183 23:03:23.177232 [CA 1] Center 34 (4~65) winsize 62
4184 23:03:23.180649 [CA 2] Center 33 (3~64) winsize 62
4185 23:03:23.183896 [CA 3] Center 33 (3~64) winsize 62
4186 23:03:23.187078 [CA 4] Center 32 (2~63) winsize 62
4187 23:03:23.190452 [CA 5] Center 32 (2~63) winsize 62
4188 23:03:23.190534
4189 23:03:23.193882 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4190 23:03:23.193964
4191 23:03:23.197103 [CATrainingPosCal] consider 2 rank data
4192 23:03:23.200363 u2DelayCellTimex100 = 270/100 ps
4193 23:03:23.203712 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4194 23:03:23.207134 CA1 delay=34 (4~65),Diff = 2 PI (19 cell)
4195 23:03:23.213743 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4196 23:03:23.216930 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4197 23:03:23.220238 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4198 23:03:23.223603 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4199 23:03:23.223685
4200 23:03:23.226929 CA PerBit enable=1, Macro0, CA PI delay=32
4201 23:03:23.227011
4202 23:03:23.230068 [CBTSetCACLKResult] CA Dly = 32
4203 23:03:23.230149 CS Dly: 4 (0~36)
4204 23:03:23.233339
4205 23:03:23.236836 ----->DramcWriteLeveling(PI) begin...
4206 23:03:23.236939 ==
4207 23:03:23.240226 Dram Type= 6, Freq= 0, CH_1, rank 0
4208 23:03:23.243533 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4209 23:03:23.243616 ==
4210 23:03:23.246932 Write leveling (Byte 0): 28 => 28
4211 23:03:23.250020 Write leveling (Byte 1): 28 => 28
4212 23:03:23.253315 DramcWriteLeveling(PI) end<-----
4213 23:03:23.253398
4214 23:03:23.253464 ==
4215 23:03:23.256613 Dram Type= 6, Freq= 0, CH_1, rank 0
4216 23:03:23.260083 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4217 23:03:23.260166 ==
4218 23:03:23.263632 [Gating] SW mode calibration
4219 23:03:23.270255 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4220 23:03:23.276594 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4221 23:03:23.279945 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4222 23:03:23.283137 0 5 4 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 0)
4223 23:03:23.289900 0 5 8 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
4224 23:03:23.293092 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4225 23:03:23.296380 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4226 23:03:23.302929 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4227 23:03:23.306101 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4228 23:03:23.309557 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4229 23:03:23.316156 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4230 23:03:23.319434 0 6 4 | B1->B0 | 2424 2c2c | 0 0 | (0 0) (0 0)
4231 23:03:23.323195 0 6 8 | B1->B0 | 3737 4242 | 0 0 | (0 0) (0 0)
4232 23:03:23.329571 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4233 23:03:23.332833 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4234 23:03:23.336159 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4235 23:03:23.342656 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4236 23:03:23.345988 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4237 23:03:23.349189 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4238 23:03:23.355647 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4239 23:03:23.359092 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4240 23:03:23.362740 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 23:03:23.369210 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 23:03:23.372211 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 23:03:23.375749 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 23:03:23.382161 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 23:03:23.385780 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 23:03:23.388983 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 23:03:23.395444 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 23:03:23.398678 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 23:03:23.402172 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 23:03:23.408665 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 23:03:23.411880 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 23:03:23.415368 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 23:03:23.418948 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 23:03:23.425466 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 23:03:23.428489 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4256 23:03:23.431956 Total UI for P1: 0, mck2ui 16
4257 23:03:23.435259 best dqsien dly found for B0: ( 0, 9, 6)
4258 23:03:23.438524 Total UI for P1: 0, mck2ui 16
4259 23:03:23.441745 best dqsien dly found for B1: ( 0, 9, 6)
4260 23:03:23.444932 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
4261 23:03:23.448453 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4262 23:03:23.448581
4263 23:03:23.451659 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
4264 23:03:23.454972 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4265 23:03:23.458410 [Gating] SW calibration Done
4266 23:03:23.458490 ==
4267 23:03:23.462005 Dram Type= 6, Freq= 0, CH_1, rank 0
4268 23:03:23.468121 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4269 23:03:23.468203 ==
4270 23:03:23.468273 RX Vref Scan: 0
4271 23:03:23.468334
4272 23:03:23.471443 RX Vref 0 -> 0, step: 1
4273 23:03:23.471525
4274 23:03:23.474764 RX Delay -230 -> 252, step: 16
4275 23:03:23.478305 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4276 23:03:23.481531 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4277 23:03:23.484585 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4278 23:03:23.491347 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4279 23:03:23.494774 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4280 23:03:23.498072 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4281 23:03:23.501502 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4282 23:03:23.507930 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4283 23:03:23.511336 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4284 23:03:23.514720 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4285 23:03:23.517857 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4286 23:03:23.524699 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4287 23:03:23.527584 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4288 23:03:23.531015 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4289 23:03:23.534159 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4290 23:03:23.540779 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4291 23:03:23.540867 ==
4292 23:03:23.544015 Dram Type= 6, Freq= 0, CH_1, rank 0
4293 23:03:23.547523 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4294 23:03:23.547610 ==
4295 23:03:23.547675 DQS Delay:
4296 23:03:23.550801 DQS0 = 0, DQS1 = 0
4297 23:03:23.550884 DQM Delay:
4298 23:03:23.554113 DQM0 = 39, DQM1 = 33
4299 23:03:23.554194 DQ Delay:
4300 23:03:23.557396 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4301 23:03:23.560807 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4302 23:03:23.564007 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4303 23:03:23.567375 DQ12 =33, DQ13 =49, DQ14 =33, DQ15 =49
4304 23:03:23.567456
4305 23:03:23.567520
4306 23:03:23.567579 ==
4307 23:03:23.570879 Dram Type= 6, Freq= 0, CH_1, rank 0
4308 23:03:23.573870 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4309 23:03:23.573951 ==
4310 23:03:23.574017
4311 23:03:23.574076
4312 23:03:23.577244 TX Vref Scan disable
4313 23:03:23.580427 == TX Byte 0 ==
4314 23:03:23.584050 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4315 23:03:23.586980 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4316 23:03:23.590376 == TX Byte 1 ==
4317 23:03:23.593686 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4318 23:03:23.596852 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4319 23:03:23.596934 ==
4320 23:03:23.600349 Dram Type= 6, Freq= 0, CH_1, rank 0
4321 23:03:23.606862 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4322 23:03:23.606951 ==
4323 23:03:23.607017
4324 23:03:23.607077
4325 23:03:23.610060 TX Vref Scan disable
4326 23:03:23.610140 == TX Byte 0 ==
4327 23:03:23.616752 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4328 23:03:23.619966 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4329 23:03:23.620047 == TX Byte 1 ==
4330 23:03:23.626483 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4331 23:03:23.629831 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4332 23:03:23.629915
4333 23:03:23.629980 [DATLAT]
4334 23:03:23.633086 Freq=600, CH1 RK0
4335 23:03:23.633167
4336 23:03:23.633232 DATLAT Default: 0x9
4337 23:03:23.636373 0, 0xFFFF, sum = 0
4338 23:03:23.636459 1, 0xFFFF, sum = 0
4339 23:03:23.639886 2, 0xFFFF, sum = 0
4340 23:03:23.643053 3, 0xFFFF, sum = 0
4341 23:03:23.643138 4, 0xFFFF, sum = 0
4342 23:03:23.646523 5, 0xFFFF, sum = 0
4343 23:03:23.646615 6, 0xFFFF, sum = 0
4344 23:03:23.646683 7, 0x0, sum = 1
4345 23:03:23.649615 8, 0x0, sum = 2
4346 23:03:23.649700 9, 0x0, sum = 3
4347 23:03:23.653006 10, 0x0, sum = 4
4348 23:03:23.653091 best_step = 8
4349 23:03:23.653156
4350 23:03:23.653217 ==
4351 23:03:23.656335 Dram Type= 6, Freq= 0, CH_1, rank 0
4352 23:03:23.663109 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4353 23:03:23.663201 ==
4354 23:03:23.663269 RX Vref Scan: 1
4355 23:03:23.663329
4356 23:03:23.666377 RX Vref 0 -> 0, step: 1
4357 23:03:23.666460
4358 23:03:23.669612 RX Delay -195 -> 252, step: 8
4359 23:03:23.669695
4360 23:03:23.673042 Set Vref, RX VrefLevel [Byte0]: 52
4361 23:03:23.676285 [Byte1]: 48
4362 23:03:23.676368
4363 23:03:23.679547 Final RX Vref Byte 0 = 52 to rank0
4364 23:03:23.682718 Final RX Vref Byte 1 = 48 to rank0
4365 23:03:23.686073 Final RX Vref Byte 0 = 52 to rank1
4366 23:03:23.689477 Final RX Vref Byte 1 = 48 to rank1==
4367 23:03:23.692654 Dram Type= 6, Freq= 0, CH_1, rank 0
4368 23:03:23.696039 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4369 23:03:23.696124 ==
4370 23:03:23.699315 DQS Delay:
4371 23:03:23.699399 DQS0 = 0, DQS1 = 0
4372 23:03:23.702571 DQM Delay:
4373 23:03:23.702655 DQM0 = 37, DQM1 = 30
4374 23:03:23.702721 DQ Delay:
4375 23:03:23.705975 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =36
4376 23:03:23.709191 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4377 23:03:23.712531 DQ8 =12, DQ9 =20, DQ10 =32, DQ11 =24
4378 23:03:23.715770 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40
4379 23:03:23.715855
4380 23:03:23.715920
4381 23:03:23.725660 [DQSOSCAuto] RK0, (LSB)MR18= 0x7272, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
4382 23:03:23.728891 CH1 RK0: MR19=808, MR18=7272
4383 23:03:23.735598 CH1_RK0: MR19=0x808, MR18=0x7272, DQSOSC=388, MR23=63, INC=174, DEC=116
4384 23:03:23.735694
4385 23:03:23.738961 ----->DramcWriteLeveling(PI) begin...
4386 23:03:23.739063 ==
4387 23:03:23.742277 Dram Type= 6, Freq= 0, CH_1, rank 1
4388 23:03:23.745647 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4389 23:03:23.745734 ==
4390 23:03:23.748919 Write leveling (Byte 0): 28 => 28
4391 23:03:23.752201 Write leveling (Byte 1): 28 => 28
4392 23:03:23.755621 DramcWriteLeveling(PI) end<-----
4393 23:03:23.755705
4394 23:03:23.755771 ==
4395 23:03:23.758870 Dram Type= 6, Freq= 0, CH_1, rank 1
4396 23:03:23.762310 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4397 23:03:23.762407 ==
4398 23:03:23.765354 [Gating] SW mode calibration
4399 23:03:23.772003 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4400 23:03:23.778538 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4401 23:03:23.781714 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4402 23:03:23.785131 0 5 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
4403 23:03:23.791751 0 5 8 | B1->B0 | 3030 2323 | 0 0 | (0 1) (1 0)
4404 23:03:23.795142 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4405 23:03:23.798365 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4406 23:03:23.805160 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4407 23:03:23.808286 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4408 23:03:23.811556 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4409 23:03:23.818243 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4410 23:03:23.821708 0 6 4 | B1->B0 | 2424 3131 | 0 0 | (0 0) (1 1)
4411 23:03:23.824794 0 6 8 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
4412 23:03:23.831500 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4413 23:03:23.834959 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4414 23:03:23.837982 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4415 23:03:23.844462 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4416 23:03:23.848017 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4417 23:03:23.851246 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4418 23:03:23.857859 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4419 23:03:23.861337 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4420 23:03:23.864367 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4421 23:03:23.871145 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4422 23:03:23.874652 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4423 23:03:23.877722 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4424 23:03:23.884375 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4425 23:03:23.887647 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4426 23:03:23.890993 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4427 23:03:23.897503 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4428 23:03:23.900941 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4429 23:03:23.904393 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 23:03:23.910841 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 23:03:23.913993 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 23:03:23.917337 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 23:03:23.924053 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 23:03:23.927349 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4435 23:03:23.930648 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4436 23:03:23.933941 Total UI for P1: 0, mck2ui 16
4437 23:03:23.937296 best dqsien dly found for B0: ( 0, 9, 4)
4438 23:03:23.940495 Total UI for P1: 0, mck2ui 16
4439 23:03:23.943931 best dqsien dly found for B1: ( 0, 9, 6)
4440 23:03:23.947067 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
4441 23:03:23.950329 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4442 23:03:23.950414
4443 23:03:23.953708 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
4444 23:03:23.960278 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4445 23:03:23.960362 [Gating] SW calibration Done
4446 23:03:23.963456 ==
4447 23:03:23.963539 Dram Type= 6, Freq= 0, CH_1, rank 1
4448 23:03:23.970175 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4449 23:03:23.970261 ==
4450 23:03:23.970326 RX Vref Scan: 0
4451 23:03:23.970386
4452 23:03:23.973634 RX Vref 0 -> 0, step: 1
4453 23:03:23.973715
4454 23:03:23.976756 RX Delay -230 -> 252, step: 16
4455 23:03:23.980461 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4456 23:03:23.983682 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4457 23:03:23.990277 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4458 23:03:23.993443 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4459 23:03:23.997143 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4460 23:03:24.000410 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4461 23:03:24.003409 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4462 23:03:24.010248 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4463 23:03:24.013455 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4464 23:03:24.016841 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4465 23:03:24.020093 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4466 23:03:24.026642 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4467 23:03:24.030001 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4468 23:03:24.033698 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4469 23:03:24.036903 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4470 23:03:24.043159 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4471 23:03:24.043251 ==
4472 23:03:24.046471 Dram Type= 6, Freq= 0, CH_1, rank 1
4473 23:03:24.049807 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4474 23:03:24.049892 ==
4475 23:03:24.049957 DQS Delay:
4476 23:03:24.052981 DQS0 = 0, DQS1 = 0
4477 23:03:24.053062 DQM Delay:
4478 23:03:24.056473 DQM0 = 39, DQM1 = 33
4479 23:03:24.056592 DQ Delay:
4480 23:03:24.059607 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4481 23:03:24.063168 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =33
4482 23:03:24.066330 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4483 23:03:24.069722 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41
4484 23:03:24.069805
4485 23:03:24.069869
4486 23:03:24.069928 ==
4487 23:03:24.073060 Dram Type= 6, Freq= 0, CH_1, rank 1
4488 23:03:24.076030 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4489 23:03:24.076111 ==
4490 23:03:24.079808
4491 23:03:24.079890
4492 23:03:24.079954 TX Vref Scan disable
4493 23:03:24.082857 == TX Byte 0 ==
4494 23:03:24.086031 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4495 23:03:24.089525 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4496 23:03:24.092698 == TX Byte 1 ==
4497 23:03:24.095923 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4498 23:03:24.099475 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4499 23:03:24.102610 ==
4500 23:03:24.102694 Dram Type= 6, Freq= 0, CH_1, rank 1
4501 23:03:24.109203 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4502 23:03:24.109291 ==
4503 23:03:24.109357
4504 23:03:24.109416
4505 23:03:24.112554 TX Vref Scan disable
4506 23:03:24.112635 == TX Byte 0 ==
4507 23:03:24.119275 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4508 23:03:24.122469 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4509 23:03:24.122551 == TX Byte 1 ==
4510 23:03:24.129246 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4511 23:03:24.132393 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4512 23:03:24.132476
4513 23:03:24.132552 [DATLAT]
4514 23:03:24.135687 Freq=600, CH1 RK1
4515 23:03:24.135768
4516 23:03:24.135832 DATLAT Default: 0x8
4517 23:03:24.139039 0, 0xFFFF, sum = 0
4518 23:03:24.139124 1, 0xFFFF, sum = 0
4519 23:03:24.142309 2, 0xFFFF, sum = 0
4520 23:03:24.142391 3, 0xFFFF, sum = 0
4521 23:03:24.145628 4, 0xFFFF, sum = 0
4522 23:03:24.149017 5, 0xFFFF, sum = 0
4523 23:03:24.149102 6, 0xFFFF, sum = 0
4524 23:03:24.149169 7, 0x0, sum = 1
4525 23:03:24.152334 8, 0x0, sum = 2
4526 23:03:24.152417 9, 0x0, sum = 3
4527 23:03:24.155351 10, 0x0, sum = 4
4528 23:03:24.155434 best_step = 8
4529 23:03:24.155499
4530 23:03:24.155574 ==
4531 23:03:24.158853 Dram Type= 6, Freq= 0, CH_1, rank 1
4532 23:03:24.165613 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4533 23:03:24.165694 ==
4534 23:03:24.165758 RX Vref Scan: 0
4535 23:03:24.165818
4536 23:03:24.168713 RX Vref 0 -> 0, step: 1
4537 23:03:24.168792
4538 23:03:24.172029 RX Delay -195 -> 252, step: 8
4539 23:03:24.175534 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4540 23:03:24.182118 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4541 23:03:24.185317 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4542 23:03:24.188800 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4543 23:03:24.191977 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4544 23:03:24.195297 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4545 23:03:24.201871 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4546 23:03:24.205138 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4547 23:03:24.208447 iDelay=205, Bit 8, Center 12 (-147 ~ 172) 320
4548 23:03:24.211780 iDelay=205, Bit 9, Center 16 (-139 ~ 172) 312
4549 23:03:24.218704 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4550 23:03:24.221909 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4551 23:03:24.225218 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4552 23:03:24.228442 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4553 23:03:24.235087 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4554 23:03:24.238482 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4555 23:03:24.238566 ==
4556 23:03:24.241895 Dram Type= 6, Freq= 0, CH_1, rank 1
4557 23:03:24.245068 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4558 23:03:24.245153 ==
4559 23:03:24.248668 DQS Delay:
4560 23:03:24.248787 DQS0 = 0, DQS1 = 0
4561 23:03:24.248921 DQM Delay:
4562 23:03:24.251947 DQM0 = 37, DQM1 = 29
4563 23:03:24.252065 DQ Delay:
4564 23:03:24.255188 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4565 23:03:24.258389 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4566 23:03:24.261816 DQ8 =12, DQ9 =16, DQ10 =32, DQ11 =20
4567 23:03:24.265297 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40
4568 23:03:24.265379
4569 23:03:24.265443
4570 23:03:24.274758 [DQSOSCAuto] RK1, (LSB)MR18= 0x6363, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
4571 23:03:24.278174 CH1 RK1: MR19=808, MR18=6363
4572 23:03:24.281507 CH1_RK1: MR19=0x808, MR18=0x6363, DQSOSC=391, MR23=63, INC=171, DEC=114
4573 23:03:24.285140 [RxdqsGatingPostProcess] freq 600
4574 23:03:24.291450 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4575 23:03:24.295007 Pre-setting of DQS Precalculation
4576 23:03:24.298161 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4577 23:03:24.307969 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4578 23:03:24.314732 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4579 23:03:24.314813
4580 23:03:24.314878
4581 23:03:24.317915 [Calibration Summary] 1200 Mbps
4582 23:03:24.317996 CH 0, Rank 0
4583 23:03:24.321340 SW Impedance : PASS
4584 23:03:24.321421 DUTY Scan : NO K
4585 23:03:24.324639 ZQ Calibration : PASS
4586 23:03:24.327913 Jitter Meter : NO K
4587 23:03:24.327993 CBT Training : PASS
4588 23:03:24.331058 Write leveling : PASS
4589 23:03:24.334590 RX DQS gating : PASS
4590 23:03:24.334670 RX DQ/DQS(RDDQC) : PASS
4591 23:03:24.337811 TX DQ/DQS : PASS
4592 23:03:24.337892 RX DATLAT : PASS
4593 23:03:24.341291 RX DQ/DQS(Engine): PASS
4594 23:03:24.344428 TX OE : NO K
4595 23:03:24.344516 All Pass.
4596 23:03:24.344584
4597 23:03:24.344643 CH 0, Rank 1
4598 23:03:24.347963 SW Impedance : PASS
4599 23:03:24.351155 DUTY Scan : NO K
4600 23:03:24.351237 ZQ Calibration : PASS
4601 23:03:24.354639 Jitter Meter : NO K
4602 23:03:24.357982 CBT Training : PASS
4603 23:03:24.358063 Write leveling : PASS
4604 23:03:24.361095 RX DQS gating : PASS
4605 23:03:24.364659 RX DQ/DQS(RDDQC) : PASS
4606 23:03:24.364740 TX DQ/DQS : PASS
4607 23:03:24.367997 RX DATLAT : PASS
4608 23:03:24.371136 RX DQ/DQS(Engine): PASS
4609 23:03:24.371216 TX OE : NO K
4610 23:03:24.374426 All Pass.
4611 23:03:24.374506
4612 23:03:24.374570 CH 1, Rank 0
4613 23:03:24.377772 SW Impedance : PASS
4614 23:03:24.377853 DUTY Scan : NO K
4615 23:03:24.381269 ZQ Calibration : PASS
4616 23:03:24.384474 Jitter Meter : NO K
4617 23:03:24.384593 CBT Training : PASS
4618 23:03:24.387518 Write leveling : PASS
4619 23:03:24.390777 RX DQS gating : PASS
4620 23:03:24.390858 RX DQ/DQS(RDDQC) : PASS
4621 23:03:24.394423 TX DQ/DQS : PASS
4622 23:03:24.394504 RX DATLAT : PASS
4623 23:03:24.397556 RX DQ/DQS(Engine): PASS
4624 23:03:24.400807 TX OE : NO K
4625 23:03:24.400887 All Pass.
4626 23:03:24.400951
4627 23:03:24.401010 CH 1, Rank 1
4628 23:03:24.404140 SW Impedance : PASS
4629 23:03:24.407427 DUTY Scan : NO K
4630 23:03:24.407508 ZQ Calibration : PASS
4631 23:03:24.410808 Jitter Meter : NO K
4632 23:03:24.414305 CBT Training : PASS
4633 23:03:24.414385 Write leveling : PASS
4634 23:03:24.417655 RX DQS gating : PASS
4635 23:03:24.420805 RX DQ/DQS(RDDQC) : PASS
4636 23:03:24.420885 TX DQ/DQS : PASS
4637 23:03:24.424078 RX DATLAT : PASS
4638 23:03:24.427433 RX DQ/DQS(Engine): PASS
4639 23:03:24.427513 TX OE : NO K
4640 23:03:24.430733 All Pass.
4641 23:03:24.430814
4642 23:03:24.430879 DramC Write-DBI off
4643 23:03:24.434114 PER_BANK_REFRESH: Hybrid Mode
4644 23:03:24.434195 TX_TRACKING: ON
4645 23:03:24.444000 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4646 23:03:24.447258 [FAST_K] Save calibration result to emmc
4647 23:03:24.450971 dramc_set_vcore_voltage set vcore to 662500
4648 23:03:24.453920 Read voltage for 933, 3
4649 23:03:24.454001 Vio18 = 0
4650 23:03:24.457210 Vcore = 662500
4651 23:03:24.457290 Vdram = 0
4652 23:03:24.457355 Vddq = 0
4653 23:03:24.457415 Vmddr = 0
4654 23:03:24.464026 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4655 23:03:24.470651 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4656 23:03:24.470732 MEM_TYPE=3, freq_sel=17
4657 23:03:24.473726 sv_algorithm_assistance_LP4_1600
4658 23:03:24.477186 ============ PULL DRAM RESETB DOWN ============
4659 23:03:24.483670 ========== PULL DRAM RESETB DOWN end =========
4660 23:03:24.487082 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4661 23:03:24.490367 ===================================
4662 23:03:24.493970 LPDDR4 DRAM CONFIGURATION
4663 23:03:24.497330 ===================================
4664 23:03:24.497413 EX_ROW_EN[0] = 0x0
4665 23:03:24.500356 EX_ROW_EN[1] = 0x0
4666 23:03:24.500436 LP4Y_EN = 0x0
4667 23:03:24.503899 WORK_FSP = 0x0
4668 23:03:24.503979 WL = 0x3
4669 23:03:24.507291 RL = 0x3
4670 23:03:24.510442 BL = 0x2
4671 23:03:24.510522 RPST = 0x0
4672 23:03:24.514036 RD_PRE = 0x0
4673 23:03:24.514116 WR_PRE = 0x1
4674 23:03:24.517097 WR_PST = 0x0
4675 23:03:24.517181 DBI_WR = 0x0
4676 23:03:24.520378 DBI_RD = 0x0
4677 23:03:24.520457 OTF = 0x1
4678 23:03:24.523895 ===================================
4679 23:03:24.527235 ===================================
4680 23:03:24.530613 ANA top config
4681 23:03:24.533550 ===================================
4682 23:03:24.533631 DLL_ASYNC_EN = 0
4683 23:03:24.537039 ALL_SLAVE_EN = 1
4684 23:03:24.540213 NEW_RANK_MODE = 1
4685 23:03:24.543739 DLL_IDLE_MODE = 1
4686 23:03:24.543820 LP45_APHY_COMB_EN = 1
4687 23:03:24.546989 TX_ODT_DIS = 1
4688 23:03:24.550190 NEW_8X_MODE = 1
4689 23:03:24.553356 ===================================
4690 23:03:24.556901 ===================================
4691 23:03:24.560092 data_rate = 1866
4692 23:03:24.563349 CKR = 1
4693 23:03:24.566510 DQ_P2S_RATIO = 8
4694 23:03:24.569885 ===================================
4695 23:03:24.569966 CA_P2S_RATIO = 8
4696 23:03:24.573241 DQ_CA_OPEN = 0
4697 23:03:24.576862 DQ_SEMI_OPEN = 0
4698 23:03:24.579933 CA_SEMI_OPEN = 0
4699 23:03:24.583054 CA_FULL_RATE = 0
4700 23:03:24.586437 DQ_CKDIV4_EN = 1
4701 23:03:24.586518 CA_CKDIV4_EN = 1
4702 23:03:24.589734 CA_PREDIV_EN = 0
4703 23:03:24.593145 PH8_DLY = 0
4704 23:03:24.596533 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4705 23:03:24.599742 DQ_AAMCK_DIV = 4
4706 23:03:24.603079 CA_AAMCK_DIV = 4
4707 23:03:24.603160 CA_ADMCK_DIV = 4
4708 23:03:24.606449 DQ_TRACK_CA_EN = 0
4709 23:03:24.609839 CA_PICK = 933
4710 23:03:24.613084 CA_MCKIO = 933
4711 23:03:24.616203 MCKIO_SEMI = 0
4712 23:03:24.619593 PLL_FREQ = 3732
4713 23:03:24.623194 DQ_UI_PI_RATIO = 32
4714 23:03:24.623275 CA_UI_PI_RATIO = 0
4715 23:03:24.626251 ===================================
4716 23:03:24.629727 ===================================
4717 23:03:24.633050 memory_type:LPDDR4
4718 23:03:24.636400 GP_NUM : 10
4719 23:03:24.636480 SRAM_EN : 1
4720 23:03:24.639583 MD32_EN : 0
4721 23:03:24.642857 ===================================
4722 23:03:24.646119 [ANA_INIT] >>>>>>>>>>>>>>
4723 23:03:24.649433 <<<<<< [CONFIGURE PHASE]: ANA_TX
4724 23:03:24.652883 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4725 23:03:24.656240 ===================================
4726 23:03:24.656321 data_rate = 1866,PCW = 0X8f00
4727 23:03:24.659525 ===================================
4728 23:03:24.662775 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4729 23:03:24.669496 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4730 23:03:24.676064 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4731 23:03:24.679318 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4732 23:03:24.682716 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4733 23:03:24.686145 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4734 23:03:24.689390 [ANA_INIT] flow start
4735 23:03:24.689471 [ANA_INIT] PLL >>>>>>>>
4736 23:03:24.692794 [ANA_INIT] PLL <<<<<<<<
4737 23:03:24.695929 [ANA_INIT] MIDPI >>>>>>>>
4738 23:03:24.699216 [ANA_INIT] MIDPI <<<<<<<<
4739 23:03:24.699297 [ANA_INIT] DLL >>>>>>>>
4740 23:03:24.702586 [ANA_INIT] flow end
4741 23:03:24.705897 ============ LP4 DIFF to SE enter ============
4742 23:03:24.709147 ============ LP4 DIFF to SE exit ============
4743 23:03:24.712711 [ANA_INIT] <<<<<<<<<<<<<
4744 23:03:24.716026 [Flow] Enable top DCM control >>>>>
4745 23:03:24.719215 [Flow] Enable top DCM control <<<<<
4746 23:03:24.722741 Enable DLL master slave shuffle
4747 23:03:24.729076 ==============================================================
4748 23:03:24.729160 Gating Mode config
4749 23:03:24.735730 ==============================================================
4750 23:03:24.735812 Config description:
4751 23:03:24.745721 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4752 23:03:24.752229 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4753 23:03:24.758897 SELPH_MODE 0: By rank 1: By Phase
4754 23:03:24.762383 ==============================================================
4755 23:03:24.765429 GAT_TRACK_EN = 1
4756 23:03:24.768797 RX_GATING_MODE = 2
4757 23:03:24.772057 RX_GATING_TRACK_MODE = 2
4758 23:03:24.775381 SELPH_MODE = 1
4759 23:03:24.778734 PICG_EARLY_EN = 1
4760 23:03:24.781966 VALID_LAT_VALUE = 1
4761 23:03:24.788865 ==============================================================
4762 23:03:24.792411 Enter into Gating configuration >>>>
4763 23:03:24.795408 Exit from Gating configuration <<<<
4764 23:03:24.798830 Enter into DVFS_PRE_config >>>>>
4765 23:03:24.808741 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4766 23:03:24.812215 Exit from DVFS_PRE_config <<<<<
4767 23:03:24.815340 Enter into PICG configuration >>>>
4768 23:03:24.818582 Exit from PICG configuration <<<<
4769 23:03:24.818664 [RX_INPUT] configuration >>>>>
4770 23:03:24.822088 [RX_INPUT] configuration <<<<<
4771 23:03:24.828626 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4772 23:03:24.835205 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4773 23:03:24.838486 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4774 23:03:24.845230 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4775 23:03:24.851757 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4776 23:03:24.858334 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4777 23:03:24.861793 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4778 23:03:24.864934 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4779 23:03:24.871582 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4780 23:03:24.875026 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4781 23:03:24.878179 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4782 23:03:24.884734 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4783 23:03:24.888018 ===================================
4784 23:03:24.888100 LPDDR4 DRAM CONFIGURATION
4785 23:03:24.891487 ===================================
4786 23:03:24.894703 EX_ROW_EN[0] = 0x0
4787 23:03:24.894786 EX_ROW_EN[1] = 0x0
4788 23:03:24.898068 LP4Y_EN = 0x0
4789 23:03:24.898150 WORK_FSP = 0x0
4790 23:03:24.901371 WL = 0x3
4791 23:03:24.904665 RL = 0x3
4792 23:03:24.904746 BL = 0x2
4793 23:03:24.907893 RPST = 0x0
4794 23:03:24.907973 RD_PRE = 0x0
4795 23:03:24.911383 WR_PRE = 0x1
4796 23:03:24.911464 WR_PST = 0x0
4797 23:03:24.914668 DBI_WR = 0x0
4798 23:03:24.914749 DBI_RD = 0x0
4799 23:03:24.917687 OTF = 0x1
4800 23:03:24.921191 ===================================
4801 23:03:24.924503 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4802 23:03:24.927765 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4803 23:03:24.934300 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4804 23:03:24.934382 ===================================
4805 23:03:24.937780 LPDDR4 DRAM CONFIGURATION
4806 23:03:24.941092 ===================================
4807 23:03:24.944315 EX_ROW_EN[0] = 0x10
4808 23:03:24.944399 EX_ROW_EN[1] = 0x0
4809 23:03:24.947696 LP4Y_EN = 0x0
4810 23:03:24.947779 WORK_FSP = 0x0
4811 23:03:24.950942 WL = 0x3
4812 23:03:24.954492 RL = 0x3
4813 23:03:24.954574 BL = 0x2
4814 23:03:24.957610 RPST = 0x0
4815 23:03:24.957692 RD_PRE = 0x0
4816 23:03:24.960792 WR_PRE = 0x1
4817 23:03:24.960874 WR_PST = 0x0
4818 23:03:24.964061 DBI_WR = 0x0
4819 23:03:24.964143 DBI_RD = 0x0
4820 23:03:24.967319 OTF = 0x1
4821 23:03:24.970637 ===================================
4822 23:03:24.977154 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4823 23:03:24.980468 nWR fixed to 30
4824 23:03:24.980559 [ModeRegInit_LP4] CH0 RK0
4825 23:03:24.983884 [ModeRegInit_LP4] CH0 RK1
4826 23:03:24.987231 [ModeRegInit_LP4] CH1 RK0
4827 23:03:24.987314 [ModeRegInit_LP4] CH1 RK1
4828 23:03:24.990638 match AC timing 8
4829 23:03:24.993880 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4830 23:03:24.997162 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4831 23:03:25.003754 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4832 23:03:25.006958 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4833 23:03:25.013764 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4834 23:03:25.013848 ==
4835 23:03:25.017121 Dram Type= 6, Freq= 0, CH_0, rank 0
4836 23:03:25.020313 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4837 23:03:25.020396 ==
4838 23:03:25.027010 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4839 23:03:25.033583 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4840 23:03:25.036820 [CA 0] Center 38 (8~69) winsize 62
4841 23:03:25.040023 [CA 1] Center 38 (7~69) winsize 63
4842 23:03:25.043417 [CA 2] Center 36 (6~67) winsize 62
4843 23:03:25.046586 [CA 3] Center 36 (6~66) winsize 61
4844 23:03:25.049900 [CA 4] Center 34 (4~65) winsize 62
4845 23:03:25.053342 [CA 5] Center 34 (4~65) winsize 62
4846 23:03:25.053426
4847 23:03:25.056548 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4848 23:03:25.056645
4849 23:03:25.060014 [CATrainingPosCal] consider 1 rank data
4850 23:03:25.063422 u2DelayCellTimex100 = 270/100 ps
4851 23:03:25.066623 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4852 23:03:25.069895 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
4853 23:03:25.073284 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4854 23:03:25.076343 CA3 delay=36 (6~66),Diff = 2 PI (12 cell)
4855 23:03:25.079957 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4856 23:03:25.083191 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4857 23:03:25.083273
4858 23:03:25.089838 CA PerBit enable=1, Macro0, CA PI delay=34
4859 23:03:25.089920
4860 23:03:25.089986 [CBTSetCACLKResult] CA Dly = 34
4861 23:03:25.093050 CS Dly: 7 (0~38)
4862 23:03:25.093133 ==
4863 23:03:25.096173 Dram Type= 6, Freq= 0, CH_0, rank 1
4864 23:03:25.099509 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4865 23:03:25.099592 ==
4866 23:03:25.106110 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4867 23:03:25.113021 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4868 23:03:25.116075 [CA 0] Center 38 (8~69) winsize 62
4869 23:03:25.119456 [CA 1] Center 38 (8~69) winsize 62
4870 23:03:25.122956 [CA 2] Center 36 (5~67) winsize 63
4871 23:03:25.126249 [CA 3] Center 35 (5~66) winsize 62
4872 23:03:25.129742 [CA 4] Center 34 (4~65) winsize 62
4873 23:03:25.132637 [CA 5] Center 34 (4~65) winsize 62
4874 23:03:25.132720
4875 23:03:25.135988 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4876 23:03:25.136071
4877 23:03:25.139310 [CATrainingPosCal] consider 2 rank data
4878 23:03:25.142509 u2DelayCellTimex100 = 270/100 ps
4879 23:03:25.145985 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4880 23:03:25.149115 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4881 23:03:25.152630 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4882 23:03:25.156093 CA3 delay=36 (6~66),Diff = 2 PI (12 cell)
4883 23:03:25.158993 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4884 23:03:25.165664 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4885 23:03:25.165750
4886 23:03:25.169213 CA PerBit enable=1, Macro0, CA PI delay=34
4887 23:03:25.169297
4888 23:03:25.172379 [CBTSetCACLKResult] CA Dly = 34
4889 23:03:25.172461 CS Dly: 7 (0~39)
4890 23:03:25.172558
4891 23:03:25.175618 ----->DramcWriteLeveling(PI) begin...
4892 23:03:25.175703 ==
4893 23:03:25.179006 Dram Type= 6, Freq= 0, CH_0, rank 0
4894 23:03:25.185621 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4895 23:03:25.185707 ==
4896 23:03:25.188883 Write leveling (Byte 0): 31 => 31
4897 23:03:25.188967 Write leveling (Byte 1): 26 => 26
4898 23:03:25.192229 DramcWriteLeveling(PI) end<-----
4899 23:03:25.192312
4900 23:03:25.192412 ==
4901 23:03:25.195674 Dram Type= 6, Freq= 0, CH_0, rank 0
4902 23:03:25.202008 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4903 23:03:25.202092 ==
4904 23:03:25.205316 [Gating] SW mode calibration
4905 23:03:25.211962 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4906 23:03:25.215279 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4907 23:03:25.221969 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4908 23:03:25.225088 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4909 23:03:25.228627 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4910 23:03:25.235096 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4911 23:03:25.238434 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4912 23:03:25.241977 0 10 20 | B1->B0 | 3434 2f2f | 0 0 | (0 1) (0 0)
4913 23:03:25.248367 0 10 24 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
4914 23:03:25.251733 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4915 23:03:25.255033 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4916 23:03:25.261606 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4917 23:03:25.265124 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4918 23:03:25.268393 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4919 23:03:25.274807 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4920 23:03:25.278463 0 11 20 | B1->B0 | 2424 2f2f | 0 0 | (0 0) (0 0)
4921 23:03:25.281745 0 11 24 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
4922 23:03:25.288266 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4923 23:03:25.291431 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4924 23:03:25.294844 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4925 23:03:25.301343 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4926 23:03:25.304669 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4927 23:03:25.308001 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4928 23:03:25.314458 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4929 23:03:25.317938 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4930 23:03:25.321322 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4931 23:03:25.327770 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4932 23:03:25.331206 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4933 23:03:25.334794 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4934 23:03:25.340936 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4935 23:03:25.344379 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4936 23:03:25.347682 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4937 23:03:25.354203 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4938 23:03:25.357553 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4939 23:03:25.360814 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4940 23:03:25.367382 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4941 23:03:25.371015 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4942 23:03:25.374183 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4943 23:03:25.377343 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4944 23:03:25.384002 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4945 23:03:25.387512 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4946 23:03:25.391058 Total UI for P1: 0, mck2ui 16
4947 23:03:25.393977 best dqsien dly found for B0: ( 0, 14, 22)
4948 23:03:25.397329 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4949 23:03:25.400869 Total UI for P1: 0, mck2ui 16
4950 23:03:25.404021 best dqsien dly found for B1: ( 0, 14, 22)
4951 23:03:25.407316 best DQS0 dly(MCK, UI, PI) = (0, 14, 22)
4952 23:03:25.413862 best DQS1 dly(MCK, UI, PI) = (0, 14, 22)
4953 23:03:25.413949
4954 23:03:25.417141 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 22)
4955 23:03:25.420856 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 22)
4956 23:03:25.423891 [Gating] SW calibration Done
4957 23:03:25.423976 ==
4958 23:03:25.427221 Dram Type= 6, Freq= 0, CH_0, rank 0
4959 23:03:25.430525 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4960 23:03:25.430610 ==
4961 23:03:25.430698 RX Vref Scan: 0
4962 23:03:25.433894
4963 23:03:25.433979 RX Vref 0 -> 0, step: 1
4964 23:03:25.434066
4965 23:03:25.437134 RX Delay -80 -> 252, step: 8
4966 23:03:25.440274 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
4967 23:03:25.443647 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
4968 23:03:25.450381 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
4969 23:03:25.453671 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
4970 23:03:25.456971 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
4971 23:03:25.460494 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
4972 23:03:25.463680 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
4973 23:03:25.466990 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
4974 23:03:25.473905 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
4975 23:03:25.476977 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
4976 23:03:25.480213 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
4977 23:03:25.483878 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
4978 23:03:25.486917 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
4979 23:03:25.493690 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
4980 23:03:25.496976 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
4981 23:03:25.500114 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
4982 23:03:25.500198 ==
4983 23:03:25.503425 Dram Type= 6, Freq= 0, CH_0, rank 0
4984 23:03:25.506643 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4985 23:03:25.506728 ==
4986 23:03:25.510149 DQS Delay:
4987 23:03:25.510247 DQS0 = 0, DQS1 = 0
4988 23:03:25.513336 DQM Delay:
4989 23:03:25.513420 DQM0 = 95, DQM1 = 84
4990 23:03:25.513506 DQ Delay:
4991 23:03:25.516610 DQ0 =91, DQ1 =95, DQ2 =95, DQ3 =91
4992 23:03:25.520136 DQ4 =99, DQ5 =83, DQ6 =103, DQ7 =107
4993 23:03:25.523439 DQ8 =75, DQ9 =71, DQ10 =87, DQ11 =79
4994 23:03:25.526949 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
4995 23:03:25.527032
4996 23:03:25.527118
4997 23:03:25.530021 ==
4998 23:03:25.533184 Dram Type= 6, Freq= 0, CH_0, rank 0
4999 23:03:25.536461 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5000 23:03:25.536585 ==
5001 23:03:25.536670
5002 23:03:25.536750
5003 23:03:25.539651 TX Vref Scan disable
5004 23:03:25.539735 == TX Byte 0 ==
5005 23:03:25.546427 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5006 23:03:25.549872 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5007 23:03:25.549955 == TX Byte 1 ==
5008 23:03:25.556299 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5009 23:03:25.559646 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5010 23:03:25.559747 ==
5011 23:03:25.562955 Dram Type= 6, Freq= 0, CH_0, rank 0
5012 23:03:25.566386 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5013 23:03:25.566482 ==
5014 23:03:25.566546
5015 23:03:25.566605
5016 23:03:25.569580 TX Vref Scan disable
5017 23:03:25.573157 == TX Byte 0 ==
5018 23:03:25.576130 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5019 23:03:25.579415 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5020 23:03:25.582815 == TX Byte 1 ==
5021 23:03:25.586114 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5022 23:03:25.589428 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5023 23:03:25.589509
5024 23:03:25.592768 [DATLAT]
5025 23:03:25.592848 Freq=933, CH0 RK0
5026 23:03:25.592912
5027 23:03:25.596271 DATLAT Default: 0xd
5028 23:03:25.596351 0, 0xFFFF, sum = 0
5029 23:03:25.599547 1, 0xFFFF, sum = 0
5030 23:03:25.599629 2, 0xFFFF, sum = 0
5031 23:03:25.602809 3, 0xFFFF, sum = 0
5032 23:03:25.602890 4, 0xFFFF, sum = 0
5033 23:03:25.606127 5, 0xFFFF, sum = 0
5034 23:03:25.606209 6, 0xFFFF, sum = 0
5035 23:03:25.609466 7, 0xFFFF, sum = 0
5036 23:03:25.609547 8, 0xFFFF, sum = 0
5037 23:03:25.612722 9, 0xFFFF, sum = 0
5038 23:03:25.612804 10, 0x0, sum = 1
5039 23:03:25.616052 11, 0x0, sum = 2
5040 23:03:25.616134 12, 0x0, sum = 3
5041 23:03:25.619434 13, 0x0, sum = 4
5042 23:03:25.619515 best_step = 11
5043 23:03:25.619580
5044 23:03:25.619639 ==
5045 23:03:25.622698 Dram Type= 6, Freq= 0, CH_0, rank 0
5046 23:03:25.629335 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5047 23:03:25.629416 ==
5048 23:03:25.629481 RX Vref Scan: 1
5049 23:03:25.629540
5050 23:03:25.632727 RX Vref 0 -> 0, step: 1
5051 23:03:25.632807
5052 23:03:25.635922 RX Delay -69 -> 252, step: 4
5053 23:03:25.636002
5054 23:03:25.639177 Set Vref, RX VrefLevel [Byte0]: 47
5055 23:03:25.642494 [Byte1]: 48
5056 23:03:25.642576
5057 23:03:25.645801 Final RX Vref Byte 0 = 47 to rank0
5058 23:03:25.649254 Final RX Vref Byte 1 = 48 to rank0
5059 23:03:25.652461 Final RX Vref Byte 0 = 47 to rank1
5060 23:03:25.655988 Final RX Vref Byte 1 = 48 to rank1==
5061 23:03:25.659169 Dram Type= 6, Freq= 0, CH_0, rank 0
5062 23:03:25.662417 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5063 23:03:25.662499 ==
5064 23:03:25.665710 DQS Delay:
5065 23:03:25.665837 DQS0 = 0, DQS1 = 0
5066 23:03:25.665951 DQM Delay:
5067 23:03:25.669137 DQM0 = 97, DQM1 = 86
5068 23:03:25.669221 DQ Delay:
5069 23:03:25.672394 DQ0 =94, DQ1 =100, DQ2 =94, DQ3 =94
5070 23:03:25.675789 DQ4 =98, DQ5 =90, DQ6 =104, DQ7 =102
5071 23:03:25.679140 DQ8 =78, DQ9 =70, DQ10 =86, DQ11 =78
5072 23:03:25.682556 DQ12 =92, DQ13 =94, DQ14 =98, DQ15 =96
5073 23:03:25.682641
5074 23:03:25.682726
5075 23:03:25.692402 [DQSOSCAuto] RK0, (LSB)MR18= 0x2121, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 411 ps
5076 23:03:25.695414 CH0 RK0: MR19=505, MR18=2121
5077 23:03:25.699151 CH0_RK0: MR19=0x505, MR18=0x2121, DQSOSC=411, MR23=63, INC=64, DEC=42
5078 23:03:25.702282
5079 23:03:25.705425 ----->DramcWriteLeveling(PI) begin...
5080 23:03:25.705510 ==
5081 23:03:25.708986 Dram Type= 6, Freq= 0, CH_0, rank 1
5082 23:03:25.712130 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5083 23:03:25.712214 ==
5084 23:03:25.715410 Write leveling (Byte 0): 26 => 26
5085 23:03:25.718973 Write leveling (Byte 1): 25 => 25
5086 23:03:25.722142 DramcWriteLeveling(PI) end<-----
5087 23:03:25.722225
5088 23:03:25.722310 ==
5089 23:03:25.725586 Dram Type= 6, Freq= 0, CH_0, rank 1
5090 23:03:25.728836 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5091 23:03:25.728931 ==
5092 23:03:25.732352 [Gating] SW mode calibration
5093 23:03:25.738911 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5094 23:03:25.745357 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5095 23:03:25.748550 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5096 23:03:25.752037 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5097 23:03:25.758789 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5098 23:03:25.762168 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5099 23:03:25.765243 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5100 23:03:25.771935 0 10 20 | B1->B0 | 3030 2e2e | 0 1 | (0 1) (1 1)
5101 23:03:25.775282 0 10 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5102 23:03:25.778652 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5103 23:03:25.781962 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5104 23:03:25.788517 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5105 23:03:25.791844 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5106 23:03:25.795136 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5107 23:03:25.801839 0 11 16 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5108 23:03:25.804893 0 11 20 | B1->B0 | 2929 3737 | 0 1 | (0 0) (0 0)
5109 23:03:25.808279 0 11 24 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
5110 23:03:25.814970 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5111 23:03:25.818177 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5112 23:03:25.821646 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5113 23:03:25.828238 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5114 23:03:25.831732 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5115 23:03:25.834913 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5116 23:03:25.841651 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5117 23:03:25.844792 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5118 23:03:25.848256 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5119 23:03:25.854680 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5120 23:03:25.858117 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5121 23:03:25.861305 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5122 23:03:25.868067 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5123 23:03:25.871138 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5124 23:03:25.874557 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5125 23:03:25.881277 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5126 23:03:25.884492 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 23:03:25.888010 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 23:03:25.894526 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 23:03:25.897653 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 23:03:25.900880 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 23:03:25.907822 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 23:03:25.911006 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5133 23:03:25.914342 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5134 23:03:25.917652 Total UI for P1: 0, mck2ui 16
5135 23:03:25.920909 best dqsien dly found for B0: ( 0, 14, 20)
5136 23:03:25.924207 Total UI for P1: 0, mck2ui 16
5137 23:03:25.927593 best dqsien dly found for B1: ( 0, 14, 20)
5138 23:03:25.930963 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
5139 23:03:25.934368 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5140 23:03:25.934456
5141 23:03:25.941145 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
5142 23:03:25.944287 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5143 23:03:25.947592 [Gating] SW calibration Done
5144 23:03:25.947680 ==
5145 23:03:25.950888 Dram Type= 6, Freq= 0, CH_0, rank 1
5146 23:03:25.954303 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5147 23:03:25.954387 ==
5148 23:03:25.954453 RX Vref Scan: 0
5149 23:03:25.954515
5150 23:03:25.957870 RX Vref 0 -> 0, step: 1
5151 23:03:25.957953
5152 23:03:25.960908 RX Delay -80 -> 252, step: 8
5153 23:03:25.964262 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5154 23:03:25.967567 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5155 23:03:25.970968 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5156 23:03:25.977437 iDelay=208, Bit 3, Center 87 (-8 ~ 183) 192
5157 23:03:25.980651 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5158 23:03:25.984202 iDelay=208, Bit 5, Center 87 (-16 ~ 191) 208
5159 23:03:25.987533 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5160 23:03:25.990569 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5161 23:03:25.993912 iDelay=208, Bit 8, Center 75 (-16 ~ 167) 184
5162 23:03:26.000635 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5163 23:03:26.003918 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5164 23:03:26.007093 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5165 23:03:26.010435 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5166 23:03:26.013847 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5167 23:03:26.020604 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5168 23:03:26.023687 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5169 23:03:26.023770 ==
5170 23:03:26.027375 Dram Type= 6, Freq= 0, CH_0, rank 1
5171 23:03:26.030384 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5172 23:03:26.030468 ==
5173 23:03:26.033612 DQS Delay:
5174 23:03:26.033694 DQS0 = 0, DQS1 = 0
5175 23:03:26.033761 DQM Delay:
5176 23:03:26.037217 DQM0 = 95, DQM1 = 85
5177 23:03:26.037300 DQ Delay:
5178 23:03:26.040345 DQ0 =91, DQ1 =99, DQ2 =91, DQ3 =87
5179 23:03:26.043681 DQ4 =99, DQ5 =87, DQ6 =99, DQ7 =107
5180 23:03:26.047106 DQ8 =75, DQ9 =67, DQ10 =87, DQ11 =75
5181 23:03:26.050371 DQ12 =95, DQ13 =91, DQ14 =95, DQ15 =95
5182 23:03:26.050455
5183 23:03:26.050521
5184 23:03:26.050581 ==
5185 23:03:26.053612 Dram Type= 6, Freq= 0, CH_0, rank 1
5186 23:03:26.060298 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5187 23:03:26.060382 ==
5188 23:03:26.060449
5189 23:03:26.060520
5190 23:03:26.060637 TX Vref Scan disable
5191 23:03:26.063521 == TX Byte 0 ==
5192 23:03:26.066964 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5193 23:03:26.070290 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5194 23:03:26.073507 == TX Byte 1 ==
5195 23:03:26.076935 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5196 23:03:26.083456 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5197 23:03:26.083544 ==
5198 23:03:26.086921 Dram Type= 6, Freq= 0, CH_0, rank 1
5199 23:03:26.090174 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5200 23:03:26.090260 ==
5201 23:03:26.090348
5202 23:03:26.090430
5203 23:03:26.093404 TX Vref Scan disable
5204 23:03:26.093489 == TX Byte 0 ==
5205 23:03:26.100057 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5206 23:03:26.103340 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5207 23:03:26.103425 == TX Byte 1 ==
5208 23:03:26.110174 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5209 23:03:26.113458 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5210 23:03:26.113544
5211 23:03:26.113631 [DATLAT]
5212 23:03:26.116433 Freq=933, CH0 RK1
5213 23:03:26.116554
5214 23:03:26.116658 DATLAT Default: 0xb
5215 23:03:26.119896 0, 0xFFFF, sum = 0
5216 23:03:26.119998 1, 0xFFFF, sum = 0
5217 23:03:26.123090 2, 0xFFFF, sum = 0
5218 23:03:26.126362 3, 0xFFFF, sum = 0
5219 23:03:26.126449 4, 0xFFFF, sum = 0
5220 23:03:26.130148 5, 0xFFFF, sum = 0
5221 23:03:26.130235 6, 0xFFFF, sum = 0
5222 23:03:26.132849 7, 0xFFFF, sum = 0
5223 23:03:26.132936 8, 0xFFFF, sum = 0
5224 23:03:26.136455 9, 0xFFFF, sum = 0
5225 23:03:26.136571 10, 0x0, sum = 1
5226 23:03:26.139612 11, 0x0, sum = 2
5227 23:03:26.139698 12, 0x0, sum = 3
5228 23:03:26.142884 13, 0x0, sum = 4
5229 23:03:26.142971 best_step = 11
5230 23:03:26.143057
5231 23:03:26.143139 ==
5232 23:03:26.146083 Dram Type= 6, Freq= 0, CH_0, rank 1
5233 23:03:26.149579 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5234 23:03:26.149665 ==
5235 23:03:26.152906 RX Vref Scan: 0
5236 23:03:26.152991
5237 23:03:26.156296 RX Vref 0 -> 0, step: 1
5238 23:03:26.156406
5239 23:03:26.156517 RX Delay -77 -> 252, step: 4
5240 23:03:26.163896 iDelay=199, Bit 0, Center 92 (-1 ~ 186) 188
5241 23:03:26.167402 iDelay=199, Bit 1, Center 98 (3 ~ 194) 192
5242 23:03:26.170701 iDelay=199, Bit 2, Center 96 (7 ~ 186) 180
5243 23:03:26.174150 iDelay=199, Bit 3, Center 94 (7 ~ 182) 176
5244 23:03:26.177188 iDelay=199, Bit 4, Center 102 (11 ~ 194) 184
5245 23:03:26.180531 iDelay=199, Bit 5, Center 90 (-1 ~ 182) 184
5246 23:03:26.187385 iDelay=199, Bit 6, Center 104 (15 ~ 194) 180
5247 23:03:26.190586 iDelay=199, Bit 7, Center 108 (19 ~ 198) 180
5248 23:03:26.193875 iDelay=199, Bit 8, Center 74 (-13 ~ 162) 176
5249 23:03:26.197223 iDelay=199, Bit 9, Center 72 (-17 ~ 162) 180
5250 23:03:26.200653 iDelay=199, Bit 10, Center 86 (-9 ~ 182) 192
5251 23:03:26.207216 iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176
5252 23:03:26.210512 iDelay=199, Bit 12, Center 92 (3 ~ 182) 180
5253 23:03:26.213772 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5254 23:03:26.217302 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5255 23:03:26.220391 iDelay=199, Bit 15, Center 96 (7 ~ 186) 180
5256 23:03:26.220475 ==
5257 23:03:26.223922 Dram Type= 6, Freq= 0, CH_0, rank 1
5258 23:03:26.230303 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5259 23:03:26.230390 ==
5260 23:03:26.230477 DQS Delay:
5261 23:03:26.233801 DQS0 = 0, DQS1 = 0
5262 23:03:26.233885 DQM Delay:
5263 23:03:26.233971 DQM0 = 98, DQM1 = 85
5264 23:03:26.237404 DQ Delay:
5265 23:03:26.240210 DQ0 =92, DQ1 =98, DQ2 =96, DQ3 =94
5266 23:03:26.243534 DQ4 =102, DQ5 =90, DQ6 =104, DQ7 =108
5267 23:03:26.246704 DQ8 =74, DQ9 =72, DQ10 =86, DQ11 =78
5268 23:03:26.250131 DQ12 =92, DQ13 =90, DQ14 =96, DQ15 =96
5269 23:03:26.250216
5270 23:03:26.250302
5271 23:03:26.256712 [DQSOSCAuto] RK1, (LSB)MR18= 0x2e2e, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 407 ps
5272 23:03:26.260049 CH0 RK1: MR19=505, MR18=2E2E
5273 23:03:26.267047 CH0_RK1: MR19=0x505, MR18=0x2E2E, DQSOSC=407, MR23=63, INC=65, DEC=43
5274 23:03:26.269909 [RxdqsGatingPostProcess] freq 933
5275 23:03:26.276634 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5276 23:03:26.276743 Pre-setting of DQS Precalculation
5277 23:03:26.283426 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5278 23:03:26.283536 ==
5279 23:03:26.286561 Dram Type= 6, Freq= 0, CH_1, rank 0
5280 23:03:26.289824 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5281 23:03:26.289931 ==
5282 23:03:26.296285 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5283 23:03:26.303005 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5284 23:03:26.306380 [CA 0] Center 37 (6~68) winsize 63
5285 23:03:26.309584 [CA 1] Center 37 (6~68) winsize 63
5286 23:03:26.313133 [CA 2] Center 34 (4~65) winsize 62
5287 23:03:26.316370 [CA 3] Center 34 (4~65) winsize 62
5288 23:03:26.319663 [CA 4] Center 33 (3~64) winsize 62
5289 23:03:26.323114 [CA 5] Center 33 (2~64) winsize 63
5290 23:03:26.323199
5291 23:03:26.326261 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5292 23:03:26.326344
5293 23:03:26.329456 [CATrainingPosCal] consider 1 rank data
5294 23:03:26.332942 u2DelayCellTimex100 = 270/100 ps
5295 23:03:26.336029 CA0 delay=37 (6~68),Diff = 4 PI (24 cell)
5296 23:03:26.339312 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5297 23:03:26.342666 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5298 23:03:26.346339 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5299 23:03:26.349387 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5300 23:03:26.352700 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
5301 23:03:26.356042
5302 23:03:26.359646 CA PerBit enable=1, Macro0, CA PI delay=33
5303 23:03:26.359728
5304 23:03:26.362795 [CBTSetCACLKResult] CA Dly = 33
5305 23:03:26.362877 CS Dly: 5 (0~36)
5306 23:03:26.362942 ==
5307 23:03:26.366013 Dram Type= 6, Freq= 0, CH_1, rank 1
5308 23:03:26.369274 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5309 23:03:26.369358 ==
5310 23:03:26.375857 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5311 23:03:26.382754 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5312 23:03:26.385952 [CA 0] Center 37 (6~68) winsize 63
5313 23:03:26.389232 [CA 1] Center 37 (6~68) winsize 63
5314 23:03:26.392485 [CA 2] Center 34 (4~65) winsize 62
5315 23:03:26.395655 [CA 3] Center 34 (4~65) winsize 62
5316 23:03:26.399083 [CA 4] Center 33 (2~64) winsize 63
5317 23:03:26.402450 [CA 5] Center 32 (2~63) winsize 62
5318 23:03:26.402533
5319 23:03:26.405941 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5320 23:03:26.406022
5321 23:03:26.409041 [CATrainingPosCal] consider 2 rank data
5322 23:03:26.412348 u2DelayCellTimex100 = 270/100 ps
5323 23:03:26.415617 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5324 23:03:26.418866 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5325 23:03:26.422162 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5326 23:03:26.425446 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5327 23:03:26.432154 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5328 23:03:26.435511 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5329 23:03:26.435591
5330 23:03:26.438960 CA PerBit enable=1, Macro0, CA PI delay=32
5331 23:03:26.439040
5332 23:03:26.442201 [CBTSetCACLKResult] CA Dly = 32
5333 23:03:26.442284 CS Dly: 5 (0~37)
5334 23:03:26.442349
5335 23:03:26.445305 ----->DramcWriteLeveling(PI) begin...
5336 23:03:26.445386 ==
5337 23:03:26.448798 Dram Type= 6, Freq= 0, CH_1, rank 0
5338 23:03:26.455411 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5339 23:03:26.455493 ==
5340 23:03:26.458629 Write leveling (Byte 0): 23 => 23
5341 23:03:26.462071 Write leveling (Byte 1): 23 => 23
5342 23:03:26.462152 DramcWriteLeveling(PI) end<-----
5343 23:03:26.462216
5344 23:03:26.465266 ==
5345 23:03:26.468621 Dram Type= 6, Freq= 0, CH_1, rank 0
5346 23:03:26.471892 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5347 23:03:26.471973 ==
5348 23:03:26.475207 [Gating] SW mode calibration
5349 23:03:26.481927 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5350 23:03:26.485123 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5351 23:03:26.491997 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5352 23:03:26.495108 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5353 23:03:26.498412 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5354 23:03:26.505165 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5355 23:03:26.508496 0 10 16 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
5356 23:03:26.511585 0 10 20 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
5357 23:03:26.518501 0 10 24 | B1->B0 | 2b2b 2323 | 0 0 | (1 1) (0 0)
5358 23:03:26.521706 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5359 23:03:26.524917 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5360 23:03:26.531688 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5361 23:03:26.534962 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5362 23:03:26.538286 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5363 23:03:26.545003 0 11 16 | B1->B0 | 2323 3131 | 0 1 | (0 0) (0 0)
5364 23:03:26.548108 0 11 20 | B1->B0 | 2828 4646 | 0 0 | (1 1) (0 0)
5365 23:03:26.551779 0 11 24 | B1->B0 | 3e3e 4646 | 0 0 | (1 1) (0 0)
5366 23:03:26.558209 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5367 23:03:26.561374 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5368 23:03:26.564872 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5369 23:03:26.571188 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5370 23:03:26.574566 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5371 23:03:26.577874 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5372 23:03:26.584457 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5373 23:03:26.587784 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 23:03:26.591228 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 23:03:26.597600 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 23:03:26.601113 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 23:03:26.604281 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 23:03:26.611006 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 23:03:26.614134 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 23:03:26.617793 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 23:03:26.624074 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 23:03:26.627316 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 23:03:26.630757 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 23:03:26.637505 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 23:03:26.640917 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 23:03:26.644112 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 23:03:26.650572 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5388 23:03:26.653832 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5389 23:03:26.657305 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5390 23:03:26.660450 Total UI for P1: 0, mck2ui 16
5391 23:03:26.663859 best dqsien dly found for B0: ( 0, 14, 18)
5392 23:03:26.667177 Total UI for P1: 0, mck2ui 16
5393 23:03:26.670716 best dqsien dly found for B1: ( 0, 14, 18)
5394 23:03:26.673863 best DQS0 dly(MCK, UI, PI) = (0, 14, 18)
5395 23:03:26.677196 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5396 23:03:26.677277
5397 23:03:26.680478 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 18)
5398 23:03:26.687123 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5399 23:03:26.687204 [Gating] SW calibration Done
5400 23:03:26.687269 ==
5401 23:03:26.690270 Dram Type= 6, Freq= 0, CH_1, rank 0
5402 23:03:26.696931 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5403 23:03:26.697013 ==
5404 23:03:26.697078 RX Vref Scan: 0
5405 23:03:26.697137
5406 23:03:26.700400 RX Vref 0 -> 0, step: 1
5407 23:03:26.700494
5408 23:03:26.703578 RX Delay -80 -> 252, step: 8
5409 23:03:26.706937 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5410 23:03:26.710323 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5411 23:03:26.713974 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5412 23:03:26.720372 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5413 23:03:26.723679 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5414 23:03:26.727141 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5415 23:03:26.730177 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5416 23:03:26.733477 iDelay=208, Bit 7, Center 95 (-8 ~ 199) 208
5417 23:03:26.736835 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5418 23:03:26.743281 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5419 23:03:26.746696 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5420 23:03:26.750004 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5421 23:03:26.753386 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5422 23:03:26.756835 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5423 23:03:26.763345 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5424 23:03:26.766379 iDelay=208, Bit 15, Center 95 (-8 ~ 199) 208
5425 23:03:26.766461 ==
5426 23:03:26.769843 Dram Type= 6, Freq= 0, CH_1, rank 0
5427 23:03:26.773206 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5428 23:03:26.773288 ==
5429 23:03:26.776406 DQS Delay:
5430 23:03:26.776487 DQS0 = 0, DQS1 = 0
5431 23:03:26.776598 DQM Delay:
5432 23:03:26.779660 DQM0 = 95, DQM1 = 85
5433 23:03:26.779742 DQ Delay:
5434 23:03:26.782991 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5435 23:03:26.786463 DQ4 =91, DQ5 =107, DQ6 =107, DQ7 =95
5436 23:03:26.789732 DQ8 =71, DQ9 =75, DQ10 =91, DQ11 =75
5437 23:03:26.793080 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =95
5438 23:03:26.793161
5439 23:03:26.793225
5440 23:03:26.793285 ==
5441 23:03:26.796462 Dram Type= 6, Freq= 0, CH_1, rank 0
5442 23:03:26.803043 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5443 23:03:26.803130 ==
5444 23:03:26.803196
5445 23:03:26.803255
5446 23:03:26.803312 TX Vref Scan disable
5447 23:03:26.806464 == TX Byte 0 ==
5448 23:03:26.809863 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5449 23:03:26.813143 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5450 23:03:26.816440 == TX Byte 1 ==
5451 23:03:26.820210 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5452 23:03:26.826752 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5453 23:03:26.826913 ==
5454 23:03:26.829931 Dram Type= 6, Freq= 0, CH_1, rank 0
5455 23:03:26.833572 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5456 23:03:26.833734 ==
5457 23:03:26.833811
5458 23:03:26.833879
5459 23:03:26.836706 TX Vref Scan disable
5460 23:03:26.836868 == TX Byte 0 ==
5461 23:03:26.843170 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5462 23:03:26.846412 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5463 23:03:26.846563 == TX Byte 1 ==
5464 23:03:26.853099 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5465 23:03:26.856409 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5466 23:03:26.856601
5467 23:03:26.856691 [DATLAT]
5468 23:03:26.859712 Freq=933, CH1 RK0
5469 23:03:26.859882
5470 23:03:26.859976 DATLAT Default: 0xd
5471 23:03:26.863309 0, 0xFFFF, sum = 0
5472 23:03:26.863483 1, 0xFFFF, sum = 0
5473 23:03:26.866814 2, 0xFFFF, sum = 0
5474 23:03:26.866991 3, 0xFFFF, sum = 0
5475 23:03:26.869792 4, 0xFFFF, sum = 0
5476 23:03:26.873116 5, 0xFFFF, sum = 0
5477 23:03:26.873311 6, 0xFFFF, sum = 0
5478 23:03:26.876400 7, 0xFFFF, sum = 0
5479 23:03:26.876624 8, 0xFFFF, sum = 0
5480 23:03:26.879618 9, 0xFFFF, sum = 0
5481 23:03:26.879820 10, 0x0, sum = 1
5482 23:03:26.882787 11, 0x0, sum = 2
5483 23:03:26.883001 12, 0x0, sum = 3
5484 23:03:26.886163 13, 0x0, sum = 4
5485 23:03:26.886376 best_step = 11
5486 23:03:26.886511
5487 23:03:26.886622 ==
5488 23:03:26.889532 Dram Type= 6, Freq= 0, CH_1, rank 0
5489 23:03:26.892906 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5490 23:03:26.893167 ==
5491 23:03:26.895954 RX Vref Scan: 1
5492 23:03:26.896158
5493 23:03:26.899216 RX Vref 0 -> 0, step: 1
5494 23:03:26.899418
5495 23:03:26.899579 RX Delay -69 -> 252, step: 4
5496 23:03:26.899728
5497 23:03:26.902581 Set Vref, RX VrefLevel [Byte0]: 52
5498 23:03:26.906062 [Byte1]: 48
5499 23:03:26.910833
5500 23:03:26.911228 Final RX Vref Byte 0 = 52 to rank0
5501 23:03:26.914699 Final RX Vref Byte 1 = 48 to rank0
5502 23:03:26.917558 Final RX Vref Byte 0 = 52 to rank1
5503 23:03:26.921022 Final RX Vref Byte 1 = 48 to rank1==
5504 23:03:26.924296 Dram Type= 6, Freq= 0, CH_1, rank 0
5505 23:03:26.930539 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5506 23:03:26.930724 ==
5507 23:03:26.930805 DQS Delay:
5508 23:03:26.933671 DQS0 = 0, DQS1 = 0
5509 23:03:26.933835 DQM Delay:
5510 23:03:26.933917 DQM0 = 94, DQM1 = 88
5511 23:03:26.936841 DQ Delay:
5512 23:03:26.940060 DQ0 =98, DQ1 =90, DQ2 =86, DQ3 =90
5513 23:03:26.943525 DQ4 =94, DQ5 =104, DQ6 =102, DQ7 =92
5514 23:03:26.946954 DQ8 =72, DQ9 =78, DQ10 =88, DQ11 =80
5515 23:03:26.950105 DQ12 =94, DQ13 =98, DQ14 =98, DQ15 =98
5516 23:03:26.950228
5517 23:03:26.950304
5518 23:03:26.956849 [DQSOSCAuto] RK0, (LSB)MR18= 0x3838, (MSB)MR19= 0x505, tDQSOscB0 = 404 ps tDQSOscB1 = 404 ps
5519 23:03:26.960192 CH1 RK0: MR19=505, MR18=3838
5520 23:03:26.966724 CH1_RK0: MR19=0x505, MR18=0x3838, DQSOSC=404, MR23=63, INC=66, DEC=44
5521 23:03:26.966810
5522 23:03:26.969869 ----->DramcWriteLeveling(PI) begin...
5523 23:03:26.969961 ==
5524 23:03:26.973310 Dram Type= 6, Freq= 0, CH_1, rank 1
5525 23:03:26.976516 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5526 23:03:26.976612 ==
5527 23:03:26.979878 Write leveling (Byte 0): 24 => 24
5528 23:03:26.983236 Write leveling (Byte 1): 22 => 22
5529 23:03:26.986523 DramcWriteLeveling(PI) end<-----
5530 23:03:26.986610
5531 23:03:26.986675 ==
5532 23:03:26.989719 Dram Type= 6, Freq= 0, CH_1, rank 1
5533 23:03:26.993442 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5534 23:03:26.993771 ==
5535 23:03:26.996792 [Gating] SW mode calibration
5536 23:03:27.003381 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5537 23:03:27.009778 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5538 23:03:27.013245 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5539 23:03:27.019970 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5540 23:03:27.023326 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5541 23:03:27.026663 0 10 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
5542 23:03:27.033086 0 10 16 | B1->B0 | 3434 2b2b | 1 0 | (1 0) (0 0)
5543 23:03:27.036436 0 10 20 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
5544 23:03:27.039650 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5545 23:03:27.046313 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5546 23:03:27.049553 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5547 23:03:27.052902 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5548 23:03:27.059639 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5549 23:03:27.062931 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5550 23:03:27.066307 0 11 16 | B1->B0 | 2525 4343 | 0 0 | (0 0) (0 0)
5551 23:03:27.072813 0 11 20 | B1->B0 | 302f 4646 | 1 0 | (0 0) (0 0)
5552 23:03:27.075852 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5553 23:03:27.079236 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5554 23:03:27.085835 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5555 23:03:27.089212 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5556 23:03:27.092642 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5557 23:03:27.099089 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5558 23:03:27.102637 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5559 23:03:27.105657 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5560 23:03:27.109065 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5561 23:03:27.115721 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5562 23:03:27.119089 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5563 23:03:27.122413 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5564 23:03:27.129177 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5565 23:03:27.132323 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5566 23:03:27.135806 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5567 23:03:27.142550 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5568 23:03:27.145746 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5569 23:03:27.148772 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5570 23:03:27.155639 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5571 23:03:27.158856 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5572 23:03:27.162213 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5573 23:03:27.168789 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5574 23:03:27.172033 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5575 23:03:27.175503 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5576 23:03:27.178583 Total UI for P1: 0, mck2ui 16
5577 23:03:27.181934 best dqsien dly found for B0: ( 0, 14, 14)
5578 23:03:27.185562 Total UI for P1: 0, mck2ui 16
5579 23:03:27.188492 best dqsien dly found for B1: ( 0, 14, 18)
5580 23:03:27.192221 best DQS0 dly(MCK, UI, PI) = (0, 14, 14)
5581 23:03:27.195270 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5582 23:03:27.198426
5583 23:03:27.201790 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 14)
5584 23:03:27.205074 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5585 23:03:27.208369 [Gating] SW calibration Done
5586 23:03:27.208451 ==
5587 23:03:27.211804 Dram Type= 6, Freq= 0, CH_1, rank 1
5588 23:03:27.215063 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5589 23:03:27.215146 ==
5590 23:03:27.215212 RX Vref Scan: 0
5591 23:03:27.218455
5592 23:03:27.218536 RX Vref 0 -> 0, step: 1
5593 23:03:27.218603
5594 23:03:27.221714 RX Delay -80 -> 252, step: 8
5595 23:03:27.225122 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5596 23:03:27.228305 iDelay=208, Bit 1, Center 91 (0 ~ 183) 184
5597 23:03:27.235044 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5598 23:03:27.238258 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5599 23:03:27.241619 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5600 23:03:27.244941 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5601 23:03:27.248241 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5602 23:03:27.251716 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5603 23:03:27.255148 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5604 23:03:27.261542 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5605 23:03:27.264852 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5606 23:03:27.268134 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5607 23:03:27.271419 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5608 23:03:27.274643 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5609 23:03:27.281501 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5610 23:03:27.284632 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5611 23:03:27.284714 ==
5612 23:03:27.288017 Dram Type= 6, Freq= 0, CH_1, rank 1
5613 23:03:27.291290 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5614 23:03:27.291374 ==
5615 23:03:27.291440 DQS Delay:
5616 23:03:27.294668 DQS0 = 0, DQS1 = 0
5617 23:03:27.294750 DQM Delay:
5618 23:03:27.298044 DQM0 = 97, DQM1 = 87
5619 23:03:27.298126 DQ Delay:
5620 23:03:27.301345 DQ0 =99, DQ1 =91, DQ2 =91, DQ3 =95
5621 23:03:27.304434 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =95
5622 23:03:27.307933 DQ8 =75, DQ9 =75, DQ10 =91, DQ11 =75
5623 23:03:27.311194 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5624 23:03:27.311278
5625 23:03:27.311344
5626 23:03:27.311404 ==
5627 23:03:27.314390 Dram Type= 6, Freq= 0, CH_1, rank 1
5628 23:03:27.320920 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5629 23:03:27.321050 ==
5630 23:03:27.321123
5631 23:03:27.321184
5632 23:03:27.321244 TX Vref Scan disable
5633 23:03:27.324341 == TX Byte 0 ==
5634 23:03:27.327661 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5635 23:03:27.334432 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5636 23:03:27.334522 == TX Byte 1 ==
5637 23:03:27.337755 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5638 23:03:27.344580 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5639 23:03:27.344732 ==
5640 23:03:27.347846 Dram Type= 6, Freq= 0, CH_1, rank 1
5641 23:03:27.351399 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5642 23:03:27.351538 ==
5643 23:03:27.351616
5644 23:03:27.351684
5645 23:03:27.354552 TX Vref Scan disable
5646 23:03:27.354709 == TX Byte 0 ==
5647 23:03:27.361106 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5648 23:03:27.364252 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5649 23:03:27.364388 == TX Byte 1 ==
5650 23:03:27.371060 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5651 23:03:27.374571 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5652 23:03:27.374760
5653 23:03:27.374858 [DATLAT]
5654 23:03:27.377564 Freq=933, CH1 RK1
5655 23:03:27.377768
5656 23:03:27.377899 DATLAT Default: 0xb
5657 23:03:27.381117 0, 0xFFFF, sum = 0
5658 23:03:27.381324 1, 0xFFFF, sum = 0
5659 23:03:27.384192 2, 0xFFFF, sum = 0
5660 23:03:27.384340 3, 0xFFFF, sum = 0
5661 23:03:27.387536 4, 0xFFFF, sum = 0
5662 23:03:27.390878 5, 0xFFFF, sum = 0
5663 23:03:27.391132 6, 0xFFFF, sum = 0
5664 23:03:27.394247 7, 0xFFFF, sum = 0
5665 23:03:27.394521 8, 0xFFFF, sum = 0
5666 23:03:27.397793 9, 0xFFFF, sum = 0
5667 23:03:27.398095 10, 0x0, sum = 1
5668 23:03:27.401340 11, 0x0, sum = 2
5669 23:03:27.401644 12, 0x0, sum = 3
5670 23:03:27.401882 13, 0x0, sum = 4
5671 23:03:27.404197 best_step = 11
5672 23:03:27.404446
5673 23:03:27.404732 ==
5674 23:03:27.407837 Dram Type= 6, Freq= 0, CH_1, rank 1
5675 23:03:27.411180 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5676 23:03:27.411609 ==
5677 23:03:27.414526 RX Vref Scan: 0
5678 23:03:27.415035
5679 23:03:27.417727 RX Vref 0 -> 0, step: 1
5680 23:03:27.418273
5681 23:03:27.418732 RX Delay -69 -> 252, step: 4
5682 23:03:27.425414 iDelay=203, Bit 0, Center 98 (7 ~ 190) 184
5683 23:03:27.428949 iDelay=203, Bit 1, Center 90 (-1 ~ 182) 184
5684 23:03:27.432052 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5685 23:03:27.435571 iDelay=203, Bit 3, Center 92 (-1 ~ 186) 188
5686 23:03:27.438785 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5687 23:03:27.444997 iDelay=203, Bit 5, Center 106 (11 ~ 202) 192
5688 23:03:27.448599 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5689 23:03:27.451847 iDelay=203, Bit 7, Center 94 (3 ~ 186) 184
5690 23:03:27.455000 iDelay=203, Bit 8, Center 74 (-17 ~ 166) 184
5691 23:03:27.458851 iDelay=203, Bit 9, Center 74 (-17 ~ 166) 184
5692 23:03:27.461809 iDelay=203, Bit 10, Center 86 (-5 ~ 178) 184
5693 23:03:27.468550 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5694 23:03:27.472150 iDelay=203, Bit 12, Center 96 (3 ~ 190) 188
5695 23:03:27.474930 iDelay=203, Bit 13, Center 98 (11 ~ 186) 176
5696 23:03:27.478336 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5697 23:03:27.481548 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5698 23:03:27.484885 ==
5699 23:03:27.485302 Dram Type= 6, Freq= 0, CH_1, rank 1
5700 23:03:27.491543 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5701 23:03:27.491985 ==
5702 23:03:27.492433 DQS Delay:
5703 23:03:27.494849 DQS0 = 0, DQS1 = 0
5704 23:03:27.495397 DQM Delay:
5705 23:03:27.498104 DQM0 = 96, DQM1 = 87
5706 23:03:27.498538 DQ Delay:
5707 23:03:27.501310 DQ0 =98, DQ1 =90, DQ2 =88, DQ3 =92
5708 23:03:27.504584 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =94
5709 23:03:27.508136 DQ8 =74, DQ9 =74, DQ10 =86, DQ11 =80
5710 23:03:27.511609 DQ12 =96, DQ13 =98, DQ14 =96, DQ15 =96
5711 23:03:27.512152
5712 23:03:27.512701
5713 23:03:27.518091 [DQSOSCAuto] RK1, (LSB)MR18= 0x2222, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 411 ps
5714 23:03:27.521541 CH1 RK1: MR19=505, MR18=2222
5715 23:03:27.528149 CH1_RK1: MR19=0x505, MR18=0x2222, DQSOSC=411, MR23=63, INC=64, DEC=42
5716 23:03:27.531333 [RxdqsGatingPostProcess] freq 933
5717 23:03:27.538062 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5718 23:03:27.538585 Pre-setting of DQS Precalculation
5719 23:03:27.544676 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5720 23:03:27.551007 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5721 23:03:27.557925 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5722 23:03:27.558444
5723 23:03:27.558825
5724 23:03:27.561051 [Calibration Summary] 1866 Mbps
5725 23:03:27.564103 CH 0, Rank 0
5726 23:03:27.564561 SW Impedance : PASS
5727 23:03:27.567837 DUTY Scan : NO K
5728 23:03:27.571150 ZQ Calibration : PASS
5729 23:03:27.571668 Jitter Meter : NO K
5730 23:03:27.574044 CBT Training : PASS
5731 23:03:27.577270 Write leveling : PASS
5732 23:03:27.577687 RX DQS gating : PASS
5733 23:03:27.580867 RX DQ/DQS(RDDQC) : PASS
5734 23:03:27.584355 TX DQ/DQS : PASS
5735 23:03:27.584934 RX DATLAT : PASS
5736 23:03:27.587405 RX DQ/DQS(Engine): PASS
5737 23:03:27.587933 TX OE : NO K
5738 23:03:27.590452 All Pass.
5739 23:03:27.590866
5740 23:03:27.591198 CH 0, Rank 1
5741 23:03:27.594099 SW Impedance : PASS
5742 23:03:27.597452 DUTY Scan : NO K
5743 23:03:27.597969 ZQ Calibration : PASS
5744 23:03:27.600815 Jitter Meter : NO K
5745 23:03:27.601360 CBT Training : PASS
5746 23:03:27.604247 Write leveling : PASS
5747 23:03:27.607051 RX DQS gating : PASS
5748 23:03:27.607485 RX DQ/DQS(RDDQC) : PASS
5749 23:03:27.610661 TX DQ/DQS : PASS
5750 23:03:27.613859 RX DATLAT : PASS
5751 23:03:27.614382 RX DQ/DQS(Engine): PASS
5752 23:03:27.617462 TX OE : NO K
5753 23:03:27.617989 All Pass.
5754 23:03:27.618333
5755 23:03:27.620256 CH 1, Rank 0
5756 23:03:27.620726 SW Impedance : PASS
5757 23:03:27.623857 DUTY Scan : NO K
5758 23:03:27.626995 ZQ Calibration : PASS
5759 23:03:27.627514 Jitter Meter : NO K
5760 23:03:27.630382 CBT Training : PASS
5761 23:03:27.633491 Write leveling : PASS
5762 23:03:27.634019 RX DQS gating : PASS
5763 23:03:27.637091 RX DQ/DQS(RDDQC) : PASS
5764 23:03:27.640368 TX DQ/DQS : PASS
5765 23:03:27.640869 RX DATLAT : PASS
5766 23:03:27.643464 RX DQ/DQS(Engine): PASS
5767 23:03:27.646762 TX OE : NO K
5768 23:03:27.647210 All Pass.
5769 23:03:27.647655
5770 23:03:27.648076 CH 1, Rank 1
5771 23:03:27.649983 SW Impedance : PASS
5772 23:03:27.653237 DUTY Scan : NO K
5773 23:03:27.653681 ZQ Calibration : PASS
5774 23:03:27.656416 Jitter Meter : NO K
5775 23:03:27.660193 CBT Training : PASS
5776 23:03:27.660767 Write leveling : PASS
5777 23:03:27.663221 RX DQS gating : PASS
5778 23:03:27.663643 RX DQ/DQS(RDDQC) : PASS
5779 23:03:27.666530 TX DQ/DQS : PASS
5780 23:03:27.669669 RX DATLAT : PASS
5781 23:03:27.670091 RX DQ/DQS(Engine): PASS
5782 23:03:27.673385 TX OE : NO K
5783 23:03:27.673909 All Pass.
5784 23:03:27.674251
5785 23:03:27.676598 DramC Write-DBI off
5786 23:03:27.679927 PER_BANK_REFRESH: Hybrid Mode
5787 23:03:27.680444 TX_TRACKING: ON
5788 23:03:27.689967 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5789 23:03:27.693272 [FAST_K] Save calibration result to emmc
5790 23:03:27.696339 dramc_set_vcore_voltage set vcore to 650000
5791 23:03:27.699508 Read voltage for 400, 6
5792 23:03:27.699930 Vio18 = 0
5793 23:03:27.703215 Vcore = 650000
5794 23:03:27.703740 Vdram = 0
5795 23:03:27.704081 Vddq = 0
5796 23:03:27.704391 Vmddr = 0
5797 23:03:27.709379 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5798 23:03:27.716161 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5799 23:03:27.716721 MEM_TYPE=3, freq_sel=20
5800 23:03:27.719520 sv_algorithm_assistance_LP4_800
5801 23:03:27.722685 ============ PULL DRAM RESETB DOWN ============
5802 23:03:27.729229 ========== PULL DRAM RESETB DOWN end =========
5803 23:03:27.732716 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5804 23:03:27.735532 ===================================
5805 23:03:27.739419 LPDDR4 DRAM CONFIGURATION
5806 23:03:27.742744 ===================================
5807 23:03:27.743266 EX_ROW_EN[0] = 0x0
5808 23:03:27.745825 EX_ROW_EN[1] = 0x0
5809 23:03:27.746504 LP4Y_EN = 0x0
5810 23:03:27.748788 WORK_FSP = 0x0
5811 23:03:27.749226 WL = 0x2
5812 23:03:27.752282 RL = 0x2
5813 23:03:27.752821 BL = 0x2
5814 23:03:27.755620 RPST = 0x0
5815 23:03:27.759477 RD_PRE = 0x0
5816 23:03:27.760016 WR_PRE = 0x1
5817 23:03:27.762579 WR_PST = 0x0
5818 23:03:27.763125 DBI_WR = 0x0
5819 23:03:27.765841 DBI_RD = 0x0
5820 23:03:27.766377 OTF = 0x1
5821 23:03:27.769590 ===================================
5822 23:03:27.772648 ===================================
5823 23:03:27.776262 ANA top config
5824 23:03:27.776864 ===================================
5825 23:03:27.779022 DLL_ASYNC_EN = 0
5826 23:03:27.782529 ALL_SLAVE_EN = 1
5827 23:03:27.785818 NEW_RANK_MODE = 1
5828 23:03:27.788938 DLL_IDLE_MODE = 1
5829 23:03:27.789375 LP45_APHY_COMB_EN = 1
5830 23:03:27.792343 TX_ODT_DIS = 1
5831 23:03:27.795589 NEW_8X_MODE = 1
5832 23:03:27.798956 ===================================
5833 23:03:27.801911 ===================================
5834 23:03:27.805683 data_rate = 800
5835 23:03:27.808639 CKR = 1
5836 23:03:27.812154 DQ_P2S_RATIO = 4
5837 23:03:27.815586 ===================================
5838 23:03:27.816190 CA_P2S_RATIO = 4
5839 23:03:27.818593 DQ_CA_OPEN = 0
5840 23:03:27.822120 DQ_SEMI_OPEN = 1
5841 23:03:27.825121 CA_SEMI_OPEN = 1
5842 23:03:27.828444 CA_FULL_RATE = 0
5843 23:03:27.832170 DQ_CKDIV4_EN = 0
5844 23:03:27.832729 CA_CKDIV4_EN = 1
5845 23:03:27.835349 CA_PREDIV_EN = 0
5846 23:03:27.838993 PH8_DLY = 0
5847 23:03:27.841693 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5848 23:03:27.845506 DQ_AAMCK_DIV = 0
5849 23:03:27.848603 CA_AAMCK_DIV = 0
5850 23:03:27.849059 CA_ADMCK_DIV = 4
5851 23:03:27.851691 DQ_TRACK_CA_EN = 0
5852 23:03:27.854787 CA_PICK = 800
5853 23:03:27.858535 CA_MCKIO = 400
5854 23:03:27.862037 MCKIO_SEMI = 400
5855 23:03:27.865124 PLL_FREQ = 3016
5856 23:03:27.868951 DQ_UI_PI_RATIO = 32
5857 23:03:27.869463 CA_UI_PI_RATIO = 32
5858 23:03:27.871418 ===================================
5859 23:03:27.875243 ===================================
5860 23:03:27.878364 memory_type:LPDDR4
5861 23:03:27.882020 GP_NUM : 10
5862 23:03:27.882538 SRAM_EN : 1
5863 23:03:27.884914 MD32_EN : 0
5864 23:03:27.888293 ===================================
5865 23:03:27.891381 [ANA_INIT] >>>>>>>>>>>>>>
5866 23:03:27.894946 <<<<<< [CONFIGURE PHASE]: ANA_TX
5867 23:03:27.898467 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5868 23:03:27.901565 ===================================
5869 23:03:27.902084 data_rate = 800,PCW = 0X7400
5870 23:03:27.905061 ===================================
5871 23:03:27.907972 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5872 23:03:27.915083 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5873 23:03:27.928438 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5874 23:03:27.931613 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5875 23:03:27.934836 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5876 23:03:27.938121 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5877 23:03:27.941241 [ANA_INIT] flow start
5878 23:03:27.941688 [ANA_INIT] PLL >>>>>>>>
5879 23:03:27.944439 [ANA_INIT] PLL <<<<<<<<
5880 23:03:27.947844 [ANA_INIT] MIDPI >>>>>>>>
5881 23:03:27.948284 [ANA_INIT] MIDPI <<<<<<<<
5882 23:03:27.951035 [ANA_INIT] DLL >>>>>>>>
5883 23:03:27.954371 [ANA_INIT] flow end
5884 23:03:27.957629 ============ LP4 DIFF to SE enter ============
5885 23:03:27.961019 ============ LP4 DIFF to SE exit ============
5886 23:03:27.964602 [ANA_INIT] <<<<<<<<<<<<<
5887 23:03:27.967803 [Flow] Enable top DCM control >>>>>
5888 23:03:27.971477 [Flow] Enable top DCM control <<<<<
5889 23:03:27.974717 Enable DLL master slave shuffle
5890 23:03:27.977998 ==============================================================
5891 23:03:27.981346 Gating Mode config
5892 23:03:27.987890 ==============================================================
5893 23:03:27.988434 Config description:
5894 23:03:27.998012 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5895 23:03:28.004656 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5896 23:03:28.011174 SELPH_MODE 0: By rank 1: By Phase
5897 23:03:28.014435 ==============================================================
5898 23:03:28.017474 GAT_TRACK_EN = 0
5899 23:03:28.020837 RX_GATING_MODE = 2
5900 23:03:28.024640 RX_GATING_TRACK_MODE = 2
5901 23:03:28.028087 SELPH_MODE = 1
5902 23:03:28.030776 PICG_EARLY_EN = 1
5903 23:03:28.034347 VALID_LAT_VALUE = 1
5904 23:03:28.037858 ==============================================================
5905 23:03:28.041081 Enter into Gating configuration >>>>
5906 23:03:28.044279 Exit from Gating configuration <<<<
5907 23:03:28.047633 Enter into DVFS_PRE_config >>>>>
5908 23:03:28.060804 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5909 23:03:28.064060 Exit from DVFS_PRE_config <<<<<
5910 23:03:28.064621 Enter into PICG configuration >>>>
5911 23:03:28.067650 Exit from PICG configuration <<<<
5912 23:03:28.070620 [RX_INPUT] configuration >>>>>
5913 23:03:28.074088 [RX_INPUT] configuration <<<<<
5914 23:03:28.080395 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5915 23:03:28.083909 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5916 23:03:28.090593 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5917 23:03:28.097348 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5918 23:03:28.103423 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5919 23:03:28.110185 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5920 23:03:28.113369 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5921 23:03:28.116697 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5922 23:03:28.120108 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5923 23:03:28.126869 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5924 23:03:28.130222 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5925 23:03:28.133328 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5926 23:03:28.136612 ===================================
5927 23:03:28.140421 LPDDR4 DRAM CONFIGURATION
5928 23:03:28.143404 ===================================
5929 23:03:28.146347 EX_ROW_EN[0] = 0x0
5930 23:03:28.146732 EX_ROW_EN[1] = 0x0
5931 23:03:28.149901 LP4Y_EN = 0x0
5932 23:03:28.150317 WORK_FSP = 0x0
5933 23:03:28.153167 WL = 0x2
5934 23:03:28.153596 RL = 0x2
5935 23:03:28.156279 BL = 0x2
5936 23:03:28.157009 RPST = 0x0
5937 23:03:28.159522 RD_PRE = 0x0
5938 23:03:28.160134 WR_PRE = 0x1
5939 23:03:28.163241 WR_PST = 0x0
5940 23:03:28.163808 DBI_WR = 0x0
5941 23:03:28.166191 DBI_RD = 0x0
5942 23:03:28.169608 OTF = 0x1
5943 23:03:28.173090 ===================================
5944 23:03:28.176624 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5945 23:03:28.179575 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5946 23:03:28.182934 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5947 23:03:28.186880 ===================================
5948 23:03:28.189625 LPDDR4 DRAM CONFIGURATION
5949 23:03:28.193074 ===================================
5950 23:03:28.196413 EX_ROW_EN[0] = 0x10
5951 23:03:28.197149 EX_ROW_EN[1] = 0x0
5952 23:03:28.200030 LP4Y_EN = 0x0
5953 23:03:28.200590 WORK_FSP = 0x0
5954 23:03:28.203044 WL = 0x2
5955 23:03:28.203562 RL = 0x2
5956 23:03:28.206650 BL = 0x2
5957 23:03:28.207167 RPST = 0x0
5958 23:03:28.209722 RD_PRE = 0x0
5959 23:03:28.210242 WR_PRE = 0x1
5960 23:03:28.212640 WR_PST = 0x0
5961 23:03:28.213055 DBI_WR = 0x0
5962 23:03:28.216364 DBI_RD = 0x0
5963 23:03:28.216930 OTF = 0x1
5964 23:03:28.219795 ===================================
5965 23:03:28.226248 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5966 23:03:28.231089 nWR fixed to 30
5967 23:03:28.234762 [ModeRegInit_LP4] CH0 RK0
5968 23:03:28.235298 [ModeRegInit_LP4] CH0 RK1
5969 23:03:28.237350 [ModeRegInit_LP4] CH1 RK0
5970 23:03:28.241214 [ModeRegInit_LP4] CH1 RK1
5971 23:03:28.241733 match AC timing 18
5972 23:03:28.247668 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
5973 23:03:28.250796 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5974 23:03:28.253912 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
5975 23:03:28.260618 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
5976 23:03:28.264180 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
5977 23:03:28.264751 ==
5978 23:03:28.267738 Dram Type= 6, Freq= 0, CH_0, rank 0
5979 23:03:28.270732 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
5980 23:03:28.271358 ==
5981 23:03:28.277172 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
5982 23:03:28.283849 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5983 23:03:28.287173 [CA 0] Center 36 (8~64) winsize 57
5984 23:03:28.291040 [CA 1] Center 36 (8~64) winsize 57
5985 23:03:28.294202 [CA 2] Center 36 (8~64) winsize 57
5986 23:03:28.297370 [CA 3] Center 36 (8~64) winsize 57
5987 23:03:28.300279 [CA 4] Center 36 (8~64) winsize 57
5988 23:03:28.300833 [CA 5] Center 36 (8~64) winsize 57
5989 23:03:28.303979
5990 23:03:28.307082 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5991 23:03:28.307607
5992 23:03:28.310364 [CATrainingPosCal] consider 1 rank data
5993 23:03:28.313637 u2DelayCellTimex100 = 270/100 ps
5994 23:03:28.316708 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
5995 23:03:28.320581 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
5996 23:03:28.323837 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
5997 23:03:28.327068 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
5998 23:03:28.330388 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
5999 23:03:28.333991 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6000 23:03:28.334525
6001 23:03:28.336975 CA PerBit enable=1, Macro0, CA PI delay=36
6002 23:03:28.337495
6003 23:03:28.340268 [CBTSetCACLKResult] CA Dly = 36
6004 23:03:28.343892 CS Dly: 1 (0~32)
6005 23:03:28.344411 ==
6006 23:03:28.346901 Dram Type= 6, Freq= 0, CH_0, rank 1
6007 23:03:28.350341 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6008 23:03:28.350765 ==
6009 23:03:28.356881 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6010 23:03:28.363579 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6011 23:03:28.366836 [CA 0] Center 36 (8~64) winsize 57
6012 23:03:28.367355 [CA 1] Center 36 (8~64) winsize 57
6013 23:03:28.369851 [CA 2] Center 36 (8~64) winsize 57
6014 23:03:28.373357 [CA 3] Center 36 (8~64) winsize 57
6015 23:03:28.376609 [CA 4] Center 36 (8~64) winsize 57
6016 23:03:28.379954 [CA 5] Center 36 (8~64) winsize 57
6017 23:03:28.380369
6018 23:03:28.383873 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6019 23:03:28.384393
6020 23:03:28.386397 [CATrainingPosCal] consider 2 rank data
6021 23:03:28.389916 u2DelayCellTimex100 = 270/100 ps
6022 23:03:28.393586 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6023 23:03:28.400336 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6024 23:03:28.403102 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6025 23:03:28.406686 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6026 23:03:28.409986 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6027 23:03:28.412859 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6028 23:03:28.413278
6029 23:03:28.416648 CA PerBit enable=1, Macro0, CA PI delay=36
6030 23:03:28.417179
6031 23:03:28.419715 [CBTSetCACLKResult] CA Dly = 36
6032 23:03:28.423279 CS Dly: 1 (0~32)
6033 23:03:28.423796
6034 23:03:28.426711 ----->DramcWriteLeveling(PI) begin...
6035 23:03:28.427240 ==
6036 23:03:28.429668 Dram Type= 6, Freq= 0, CH_0, rank 0
6037 23:03:28.432762 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6038 23:03:28.433285 ==
6039 23:03:28.436112 Write leveling (Byte 0): 32 => 0
6040 23:03:28.439307 Write leveling (Byte 1): 32 => 0
6041 23:03:28.442578 DramcWriteLeveling(PI) end<-----
6042 23:03:28.443009
6043 23:03:28.443344 ==
6044 23:03:28.446335 Dram Type= 6, Freq= 0, CH_0, rank 0
6045 23:03:28.449110 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6046 23:03:28.449530 ==
6047 23:03:28.452904 [Gating] SW mode calibration
6048 23:03:28.458725 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6049 23:03:28.465515 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6050 23:03:28.469032 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6051 23:03:28.472551 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6052 23:03:28.479321 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6053 23:03:28.482793 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6054 23:03:28.485495 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6055 23:03:28.492578 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6056 23:03:28.496042 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6057 23:03:28.499173 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6058 23:03:28.505554 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6059 23:03:28.506069 Total UI for P1: 0, mck2ui 16
6060 23:03:28.512445 best dqsien dly found for B0: ( 0, 10, 16)
6061 23:03:28.512998 Total UI for P1: 0, mck2ui 16
6062 23:03:28.518799 best dqsien dly found for B1: ( 0, 10, 16)
6063 23:03:28.521731 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6064 23:03:28.525438 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6065 23:03:28.525953
6066 23:03:28.528979 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6067 23:03:28.532676 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6068 23:03:28.535646 [Gating] SW calibration Done
6069 23:03:28.536162 ==
6070 23:03:28.539081 Dram Type= 6, Freq= 0, CH_0, rank 0
6071 23:03:28.542132 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6072 23:03:28.542553 ==
6073 23:03:28.545687 RX Vref Scan: 0
6074 23:03:28.546210
6075 23:03:28.546542 RX Vref 0 -> 0, step: 1
6076 23:03:28.546852
6077 23:03:28.548503 RX Delay -410 -> 252, step: 16
6078 23:03:28.555111 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6079 23:03:28.558368 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6080 23:03:28.562450 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6081 23:03:28.565189 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6082 23:03:28.572182 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6083 23:03:28.575255 iDelay=230, Bit 5, Center -51 (-298 ~ 197) 496
6084 23:03:28.578633 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6085 23:03:28.581826 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6086 23:03:28.588690 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6087 23:03:28.591912 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6088 23:03:28.595037 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6089 23:03:28.598742 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6090 23:03:28.605386 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6091 23:03:28.608658 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6092 23:03:28.611556 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6093 23:03:28.615178 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6094 23:03:28.618370 ==
6095 23:03:28.621458 Dram Type= 6, Freq= 0, CH_0, rank 0
6096 23:03:28.624975 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6097 23:03:28.625500 ==
6098 23:03:28.625839 DQS Delay:
6099 23:03:28.627969 DQS0 = 51, DQS1 = 59
6100 23:03:28.628385 DQM Delay:
6101 23:03:28.631331 DQM0 = 12, DQM1 = 16
6102 23:03:28.631845 DQ Delay:
6103 23:03:28.634970 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6104 23:03:28.638406 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6105 23:03:28.641523 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6106 23:03:28.644648 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6107 23:03:28.645162
6108 23:03:28.645494
6109 23:03:28.645801 ==
6110 23:03:28.648142 Dram Type= 6, Freq= 0, CH_0, rank 0
6111 23:03:28.651091 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6112 23:03:28.651774 ==
6113 23:03:28.652166
6114 23:03:28.652487
6115 23:03:28.654306 TX Vref Scan disable
6116 23:03:28.654719 == TX Byte 0 ==
6117 23:03:28.661237 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6118 23:03:28.664472 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6119 23:03:28.664921 == TX Byte 1 ==
6120 23:03:28.671082 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6121 23:03:28.674848 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6122 23:03:28.675365 ==
6123 23:03:28.678019 Dram Type= 6, Freq= 0, CH_0, rank 0
6124 23:03:28.681248 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6125 23:03:28.681774 ==
6126 23:03:28.682115
6127 23:03:28.682423
6128 23:03:28.684709 TX Vref Scan disable
6129 23:03:28.687882 == TX Byte 0 ==
6130 23:03:28.691307 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6131 23:03:28.694632 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6132 23:03:28.697593 == TX Byte 1 ==
6133 23:03:28.701296 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6134 23:03:28.704605 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6135 23:03:28.705123
6136 23:03:28.705457 [DATLAT]
6137 23:03:28.707806 Freq=400, CH0 RK0
6138 23:03:28.708324
6139 23:03:28.711446 DATLAT Default: 0xf
6140 23:03:28.711980 0, 0xFFFF, sum = 0
6141 23:03:28.714102 1, 0xFFFF, sum = 0
6142 23:03:28.714524 2, 0xFFFF, sum = 0
6143 23:03:28.717769 3, 0xFFFF, sum = 0
6144 23:03:28.718296 4, 0xFFFF, sum = 0
6145 23:03:28.721170 5, 0xFFFF, sum = 0
6146 23:03:28.721720 6, 0xFFFF, sum = 0
6147 23:03:28.723950 7, 0xFFFF, sum = 0
6148 23:03:28.724368 8, 0xFFFF, sum = 0
6149 23:03:28.727588 9, 0xFFFF, sum = 0
6150 23:03:28.728010 10, 0xFFFF, sum = 0
6151 23:03:28.731031 11, 0xFFFF, sum = 0
6152 23:03:28.731561 12, 0x0, sum = 1
6153 23:03:28.734120 13, 0x0, sum = 2
6154 23:03:28.734544 14, 0x0, sum = 3
6155 23:03:28.737283 15, 0x0, sum = 4
6156 23:03:28.737704 best_step = 13
6157 23:03:28.738037
6158 23:03:28.738350 ==
6159 23:03:28.740690 Dram Type= 6, Freq= 0, CH_0, rank 0
6160 23:03:28.744082 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6161 23:03:28.747561 ==
6162 23:03:28.748092 RX Vref Scan: 1
6163 23:03:28.748427
6164 23:03:28.750734 RX Vref 0 -> 0, step: 1
6165 23:03:28.751145
6166 23:03:28.753857 RX Delay -359 -> 252, step: 8
6167 23:03:28.754339
6168 23:03:28.757360 Set Vref, RX VrefLevel [Byte0]: 47
6169 23:03:28.760493 [Byte1]: 48
6170 23:03:28.760950
6171 23:03:28.763833 Final RX Vref Byte 0 = 47 to rank0
6172 23:03:28.767804 Final RX Vref Byte 1 = 48 to rank0
6173 23:03:28.770724 Final RX Vref Byte 0 = 47 to rank1
6174 23:03:28.774145 Final RX Vref Byte 1 = 48 to rank1==
6175 23:03:28.777300 Dram Type= 6, Freq= 0, CH_0, rank 0
6176 23:03:28.780934 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6177 23:03:28.784091 ==
6178 23:03:28.784653 DQS Delay:
6179 23:03:28.784988 DQS0 = 52, DQS1 = 68
6180 23:03:28.787638 DQM Delay:
6181 23:03:28.788154 DQM0 = 9, DQM1 = 16
6182 23:03:28.790341 DQ Delay:
6183 23:03:28.790756 DQ0 =4, DQ1 =8, DQ2 =8, DQ3 =4
6184 23:03:28.793630 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6185 23:03:28.796957 DQ8 =8, DQ9 =0, DQ10 =12, DQ11 =8
6186 23:03:28.800564 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =28
6187 23:03:28.801101
6188 23:03:28.801437
6189 23:03:28.810463 [DQSOSCAuto] RK0, (LSB)MR18= 0x9d9d, (MSB)MR19= 0xc0c, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
6190 23:03:28.813592 CH0 RK0: MR19=C0C, MR18=9D9D
6191 23:03:28.817201 CH0_RK0: MR19=0xC0C, MR18=0x9D9D, DQSOSC=390, MR23=63, INC=388, DEC=258
6192 23:03:28.820583 ==
6193 23:03:28.823632 Dram Type= 6, Freq= 0, CH_0, rank 1
6194 23:03:28.827159 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6195 23:03:28.827582 ==
6196 23:03:28.830148 [Gating] SW mode calibration
6197 23:03:28.836863 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6198 23:03:28.839949 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6199 23:03:28.846781 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6200 23:03:28.850025 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6201 23:03:28.853207 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6202 23:03:28.859935 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6203 23:03:28.863143 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6204 23:03:28.866663 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6205 23:03:28.873526 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6206 23:03:28.876975 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6207 23:03:28.879796 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6208 23:03:28.883243 Total UI for P1: 0, mck2ui 16
6209 23:03:28.886447 best dqsien dly found for B0: ( 0, 10, 16)
6210 23:03:28.889567 Total UI for P1: 0, mck2ui 16
6211 23:03:28.892993 best dqsien dly found for B1: ( 0, 10, 16)
6212 23:03:28.896609 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6213 23:03:28.899852 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6214 23:03:28.900417
6215 23:03:28.906478 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6216 23:03:28.909468 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6217 23:03:28.912907 [Gating] SW calibration Done
6218 23:03:28.913481 ==
6219 23:03:28.916424 Dram Type= 6, Freq= 0, CH_0, rank 1
6220 23:03:28.919627 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6221 23:03:28.920224 ==
6222 23:03:28.920654 RX Vref Scan: 0
6223 23:03:28.922981
6224 23:03:28.923437 RX Vref 0 -> 0, step: 1
6225 23:03:28.923796
6226 23:03:28.925854 RX Delay -410 -> 252, step: 16
6227 23:03:28.929564 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6228 23:03:28.936084 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6229 23:03:28.939597 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6230 23:03:28.942608 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6231 23:03:28.946027 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6232 23:03:28.952628 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6233 23:03:28.955870 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6234 23:03:28.959131 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6235 23:03:28.962803 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6236 23:03:28.969124 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6237 23:03:28.972777 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6238 23:03:28.975871 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6239 23:03:28.979252 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6240 23:03:28.985959 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6241 23:03:28.989012 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6242 23:03:28.992748 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6243 23:03:28.993272 ==
6244 23:03:28.995949 Dram Type= 6, Freq= 0, CH_0, rank 1
6245 23:03:29.002670 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6246 23:03:29.003192 ==
6247 23:03:29.003531 DQS Delay:
6248 23:03:29.005764 DQS0 = 43, DQS1 = 59
6249 23:03:29.006298 DQM Delay:
6250 23:03:29.006638 DQM0 = 7, DQM1 = 15
6251 23:03:29.009454 DQ Delay:
6252 23:03:29.009969 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6253 23:03:29.012739 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6254 23:03:29.015547 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6255 23:03:29.019140 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6256 23:03:29.019658
6257 23:03:29.019993
6258 23:03:29.022617 ==
6259 23:03:29.025662 Dram Type= 6, Freq= 0, CH_0, rank 1
6260 23:03:29.029042 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6261 23:03:29.029560 ==
6262 23:03:29.029895
6263 23:03:29.030201
6264 23:03:29.032426 TX Vref Scan disable
6265 23:03:29.033019 == TX Byte 0 ==
6266 23:03:29.035597 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6267 23:03:29.042233 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6268 23:03:29.042754 == TX Byte 1 ==
6269 23:03:29.045643 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6270 23:03:29.051991 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6271 23:03:29.052655 ==
6272 23:03:29.055280 Dram Type= 6, Freq= 0, CH_0, rank 1
6273 23:03:29.058734 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6274 23:03:29.059153 ==
6275 23:03:29.059535
6276 23:03:29.059863
6277 23:03:29.062350 TX Vref Scan disable
6278 23:03:29.062868 == TX Byte 0 ==
6279 23:03:29.065713 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6280 23:03:29.071783 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6281 23:03:29.072209 == TX Byte 1 ==
6282 23:03:29.075464 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6283 23:03:29.081957 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6284 23:03:29.082463
6285 23:03:29.082795 [DATLAT]
6286 23:03:29.083171 Freq=400, CH0 RK1
6287 23:03:29.083484
6288 23:03:29.085170 DATLAT Default: 0xd
6289 23:03:29.088532 0, 0xFFFF, sum = 0
6290 23:03:29.089071 1, 0xFFFF, sum = 0
6291 23:03:29.091725 2, 0xFFFF, sum = 0
6292 23:03:29.092264 3, 0xFFFF, sum = 0
6293 23:03:29.094907 4, 0xFFFF, sum = 0
6294 23:03:29.095486 5, 0xFFFF, sum = 0
6295 23:03:29.097900 6, 0xFFFF, sum = 0
6296 23:03:29.097982 7, 0xFFFF, sum = 0
6297 23:03:29.101194 8, 0xFFFF, sum = 0
6298 23:03:29.101277 9, 0xFFFF, sum = 0
6299 23:03:29.104769 10, 0xFFFF, sum = 0
6300 23:03:29.104933 11, 0xFFFF, sum = 0
6301 23:03:29.108004 12, 0x0, sum = 1
6302 23:03:29.108165 13, 0x0, sum = 2
6303 23:03:29.111184 14, 0x0, sum = 3
6304 23:03:29.111347 15, 0x0, sum = 4
6305 23:03:29.114348 best_step = 13
6306 23:03:29.114511
6307 23:03:29.114587 ==
6308 23:03:29.117580 Dram Type= 6, Freq= 0, CH_0, rank 1
6309 23:03:29.121166 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6310 23:03:29.121339 ==
6311 23:03:29.124318 RX Vref Scan: 0
6312 23:03:29.124497
6313 23:03:29.124607 RX Vref 0 -> 0, step: 1
6314 23:03:29.124688
6315 23:03:29.127636 RX Delay -359 -> 252, step: 8
6316 23:03:29.135516 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6317 23:03:29.138869 iDelay=217, Bit 1, Center -36 (-287 ~ 216) 504
6318 23:03:29.142154 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504
6319 23:03:29.149088 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6320 23:03:29.152244 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6321 23:03:29.155154 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6322 23:03:29.158845 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6323 23:03:29.162759 iDelay=217, Bit 7, Center -32 (-279 ~ 216) 496
6324 23:03:29.168924 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6325 23:03:29.172048 iDelay=217, Bit 9, Center -64 (-311 ~ 184) 496
6326 23:03:29.175614 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6327 23:03:29.182014 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6328 23:03:29.185593 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6329 23:03:29.188493 iDelay=217, Bit 13, Center -48 (-295 ~ 200) 496
6330 23:03:29.192126 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6331 23:03:29.198629 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6332 23:03:29.199076 ==
6333 23:03:29.202210 Dram Type= 6, Freq= 0, CH_0, rank 1
6334 23:03:29.205122 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6335 23:03:29.205584 ==
6336 23:03:29.205940 DQS Delay:
6337 23:03:29.208597 DQS0 = 52, DQS1 = 64
6338 23:03:29.209154 DQM Delay:
6339 23:03:29.211845 DQM0 = 10, DQM1 = 13
6340 23:03:29.212346 DQ Delay:
6341 23:03:29.215130 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =4
6342 23:03:29.218684 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6343 23:03:29.221779 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6344 23:03:29.225171 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =24
6345 23:03:29.225586
6346 23:03:29.225910
6347 23:03:29.232150 [DQSOSCAuto] RK1, (LSB)MR18= 0xbdbd, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 386 ps
6348 23:03:29.235448 CH0 RK1: MR19=C0C, MR18=BDBD
6349 23:03:29.241921 CH0_RK1: MR19=0xC0C, MR18=0xBDBD, DQSOSC=386, MR23=63, INC=396, DEC=264
6350 23:03:29.245218 [RxdqsGatingPostProcess] freq 400
6351 23:03:29.251848 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6352 23:03:29.254937 Pre-setting of DQS Precalculation
6353 23:03:29.258019 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6354 23:03:29.258488 ==
6355 23:03:29.261376 Dram Type= 6, Freq= 0, CH_1, rank 0
6356 23:03:29.265258 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6357 23:03:29.265787 ==
6358 23:03:29.271598 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6359 23:03:29.278569 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6360 23:03:29.281530 [CA 0] Center 36 (8~64) winsize 57
6361 23:03:29.284884 [CA 1] Center 36 (8~64) winsize 57
6362 23:03:29.288338 [CA 2] Center 36 (8~64) winsize 57
6363 23:03:29.291244 [CA 3] Center 36 (8~64) winsize 57
6364 23:03:29.294740 [CA 4] Center 36 (8~64) winsize 57
6365 23:03:29.295312 [CA 5] Center 36 (8~64) winsize 57
6366 23:03:29.297875
6367 23:03:29.301621 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6368 23:03:29.302183
6369 23:03:29.304780 [CATrainingPosCal] consider 1 rank data
6370 23:03:29.308593 u2DelayCellTimex100 = 270/100 ps
6371 23:03:29.311666 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6372 23:03:29.314886 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6373 23:03:29.317847 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6374 23:03:29.340827 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6375 23:03:29.341267 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6376 23:03:29.341611 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6377 23:03:29.341933
6378 23:03:29.342283 CA PerBit enable=1, Macro0, CA PI delay=36
6379 23:03:29.342698
6380 23:03:29.343125 [CBTSetCACLKResult] CA Dly = 36
6381 23:03:29.343435 CS Dly: 1 (0~32)
6382 23:03:29.343736 ==
6383 23:03:29.344541 Dram Type= 6, Freq= 0, CH_1, rank 1
6384 23:03:29.345025 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6385 23:03:29.345447 ==
6386 23:03:29.350641 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6387 23:03:29.357520 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6388 23:03:29.360695 [CA 0] Center 36 (8~64) winsize 57
6389 23:03:29.364266 [CA 1] Center 36 (8~64) winsize 57
6390 23:03:29.364838 [CA 2] Center 36 (8~64) winsize 57
6391 23:03:29.367667 [CA 3] Center 36 (8~64) winsize 57
6392 23:03:29.370727 [CA 4] Center 36 (8~64) winsize 57
6393 23:03:29.374315 [CA 5] Center 36 (8~64) winsize 57
6394 23:03:29.374838
6395 23:03:29.377317 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6396 23:03:29.381084
6397 23:03:29.384046 [CATrainingPosCal] consider 2 rank data
6398 23:03:29.384601 u2DelayCellTimex100 = 270/100 ps
6399 23:03:29.390787 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6400 23:03:29.393937 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6401 23:03:29.397270 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6402 23:03:29.400786 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6403 23:03:29.403777 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6404 23:03:29.407161 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6405 23:03:29.407681
6406 23:03:29.410800 CA PerBit enable=1, Macro0, CA PI delay=36
6407 23:03:29.411318
6408 23:03:29.413384 [CBTSetCACLKResult] CA Dly = 36
6409 23:03:29.417171 CS Dly: 1 (0~32)
6410 23:03:29.417752
6411 23:03:29.420737 ----->DramcWriteLeveling(PI) begin...
6412 23:03:29.421263 ==
6413 23:03:29.424021 Dram Type= 6, Freq= 0, CH_1, rank 0
6414 23:03:29.426679 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6415 23:03:29.427104 ==
6416 23:03:29.430505 Write leveling (Byte 0): 32 => 0
6417 23:03:29.433733 Write leveling (Byte 1): 32 => 0
6418 23:03:29.436976 DramcWriteLeveling(PI) end<-----
6419 23:03:29.437497
6420 23:03:29.437838 ==
6421 23:03:29.440172 Dram Type= 6, Freq= 0, CH_1, rank 0
6422 23:03:29.443304 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6423 23:03:29.443733 ==
6424 23:03:29.446805 [Gating] SW mode calibration
6425 23:03:29.453493 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6426 23:03:29.459748 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6427 23:03:29.463296 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6428 23:03:29.466371 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6429 23:03:29.473084 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6430 23:03:29.476403 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6431 23:03:29.479663 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6432 23:03:29.486418 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6433 23:03:29.489389 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6434 23:03:29.492626 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6435 23:03:29.499513 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6436 23:03:29.502818 Total UI for P1: 0, mck2ui 16
6437 23:03:29.505990 best dqsien dly found for B0: ( 0, 10, 16)
6438 23:03:29.509429 Total UI for P1: 0, mck2ui 16
6439 23:03:29.512606 best dqsien dly found for B1: ( 0, 10, 16)
6440 23:03:29.515623 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6441 23:03:29.519339 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6442 23:03:29.519905
6443 23:03:29.522480 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6444 23:03:29.525488 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6445 23:03:29.529116 [Gating] SW calibration Done
6446 23:03:29.529581 ==
6447 23:03:29.532577 Dram Type= 6, Freq= 0, CH_1, rank 0
6448 23:03:29.535935 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6449 23:03:29.536798 ==
6450 23:03:29.539093 RX Vref Scan: 0
6451 23:03:29.539681
6452 23:03:29.542388 RX Vref 0 -> 0, step: 1
6453 23:03:29.542957
6454 23:03:29.545326 RX Delay -410 -> 252, step: 16
6455 23:03:29.549075 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6456 23:03:29.552150 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6457 23:03:29.555313 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6458 23:03:29.562191 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6459 23:03:29.565418 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6460 23:03:29.568537 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6461 23:03:29.572376 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6462 23:03:29.578925 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6463 23:03:29.581915 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6464 23:03:29.585381 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6465 23:03:29.588621 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6466 23:03:29.595337 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6467 23:03:29.598644 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6468 23:03:29.601936 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6469 23:03:29.608593 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6470 23:03:29.612074 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6471 23:03:29.612681 ==
6472 23:03:29.615373 Dram Type= 6, Freq= 0, CH_1, rank 0
6473 23:03:29.618729 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6474 23:03:29.619307 ==
6475 23:03:29.619688 DQS Delay:
6476 23:03:29.622071 DQS0 = 43, DQS1 = 59
6477 23:03:29.622641 DQM Delay:
6478 23:03:29.624938 DQM0 = 6, DQM1 = 16
6479 23:03:29.625405 DQ Delay:
6480 23:03:29.628544 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6481 23:03:29.631566 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6482 23:03:29.635067 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6483 23:03:29.638032 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =32
6484 23:03:29.638504
6485 23:03:29.638894
6486 23:03:29.639239 ==
6487 23:03:29.641467 Dram Type= 6, Freq= 0, CH_1, rank 0
6488 23:03:29.645001 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6489 23:03:29.645569 ==
6490 23:03:29.648200
6491 23:03:29.648824
6492 23:03:29.649268 TX Vref Scan disable
6493 23:03:29.651546 == TX Byte 0 ==
6494 23:03:29.654672 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6495 23:03:29.658211 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6496 23:03:29.661211 == TX Byte 1 ==
6497 23:03:29.664980 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6498 23:03:29.668384 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6499 23:03:29.668979 ==
6500 23:03:29.671589 Dram Type= 6, Freq= 0, CH_1, rank 0
6501 23:03:29.678190 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6502 23:03:29.678759 ==
6503 23:03:29.679136
6504 23:03:29.679480
6505 23:03:29.679803 TX Vref Scan disable
6506 23:03:29.681059 == TX Byte 0 ==
6507 23:03:29.684435 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6508 23:03:29.688420 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6509 23:03:29.691033 == TX Byte 1 ==
6510 23:03:29.694509 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6511 23:03:29.697733 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6512 23:03:29.698335
6513 23:03:29.700837 [DATLAT]
6514 23:03:29.701299 Freq=400, CH1 RK0
6515 23:03:29.701670
6516 23:03:29.704358 DATLAT Default: 0xf
6517 23:03:29.704992 0, 0xFFFF, sum = 0
6518 23:03:29.707342 1, 0xFFFF, sum = 0
6519 23:03:29.707907 2, 0xFFFF, sum = 0
6520 23:03:29.710923 3, 0xFFFF, sum = 0
6521 23:03:29.711495 4, 0xFFFF, sum = 0
6522 23:03:29.714232 5, 0xFFFF, sum = 0
6523 23:03:29.717473 6, 0xFFFF, sum = 0
6524 23:03:29.717953 7, 0xFFFF, sum = 0
6525 23:03:29.721066 8, 0xFFFF, sum = 0
6526 23:03:29.721640 9, 0xFFFF, sum = 0
6527 23:03:29.724162 10, 0xFFFF, sum = 0
6528 23:03:29.724829 11, 0xFFFF, sum = 0
6529 23:03:29.727210 12, 0x0, sum = 1
6530 23:03:29.727683 13, 0x0, sum = 2
6531 23:03:29.731407 14, 0x0, sum = 3
6532 23:03:29.731988 15, 0x0, sum = 4
6533 23:03:29.732367 best_step = 13
6534 23:03:29.733806
6535 23:03:29.734335 ==
6536 23:03:29.737573 Dram Type= 6, Freq= 0, CH_1, rank 0
6537 23:03:29.740883 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6538 23:03:29.741452 ==
6539 23:03:29.741823 RX Vref Scan: 1
6540 23:03:29.742169
6541 23:03:29.744025 RX Vref 0 -> 0, step: 1
6542 23:03:29.744648
6543 23:03:29.747161 RX Delay -359 -> 252, step: 8
6544 23:03:29.747725
6545 23:03:29.750448 Set Vref, RX VrefLevel [Byte0]: 52
6546 23:03:29.753679 [Byte1]: 48
6547 23:03:29.757977
6548 23:03:29.758695 Final RX Vref Byte 0 = 52 to rank0
6549 23:03:29.761047 Final RX Vref Byte 1 = 48 to rank0
6550 23:03:29.764618 Final RX Vref Byte 0 = 52 to rank1
6551 23:03:29.767777 Final RX Vref Byte 1 = 48 to rank1==
6552 23:03:29.771014 Dram Type= 6, Freq= 0, CH_1, rank 0
6553 23:03:29.777344 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6554 23:03:29.777869 ==
6555 23:03:29.778210 DQS Delay:
6556 23:03:29.780720 DQS0 = 48, DQS1 = 64
6557 23:03:29.781139 DQM Delay:
6558 23:03:29.781478 DQM0 = 8, DQM1 = 16
6559 23:03:29.784239 DQ Delay:
6560 23:03:29.787605 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =4
6561 23:03:29.788121 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6562 23:03:29.790787 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6563 23:03:29.794050 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6564 23:03:29.794572
6565 23:03:29.794911
6566 23:03:29.804268 [DQSOSCAuto] RK0, (LSB)MR18= 0xdede, (MSB)MR19= 0xc0c, tDQSOscB0 = 382 ps tDQSOscB1 = 382 ps
6567 23:03:29.807759 CH1 RK0: MR19=C0C, MR18=DEDE
6568 23:03:29.813999 CH1_RK0: MR19=0xC0C, MR18=0xDEDE, DQSOSC=382, MR23=63, INC=404, DEC=269
6569 23:03:29.814517 ==
6570 23:03:29.817050 Dram Type= 6, Freq= 0, CH_1, rank 1
6571 23:03:29.820704 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6572 23:03:29.821264 ==
6573 23:03:29.823735 [Gating] SW mode calibration
6574 23:03:29.831061 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6575 23:03:29.833845 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6576 23:03:29.840796 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6577 23:03:29.843691 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6578 23:03:29.847133 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6579 23:03:29.853557 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6580 23:03:29.857549 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6581 23:03:29.860332 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6582 23:03:29.867094 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6583 23:03:29.870216 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
6584 23:03:29.873412 Total UI for P1: 0, mck2ui 16
6585 23:03:29.876798 best dqsien dly found for B0: ( 0, 10, 8)
6586 23:03:29.880421 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6587 23:03:29.883347 Total UI for P1: 0, mck2ui 16
6588 23:03:29.886813 best dqsien dly found for B1: ( 0, 10, 16)
6589 23:03:29.890317 best DQS0 dly(MCK, UI, PI) = (0, 10, 8)
6590 23:03:29.896824 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6591 23:03:29.897401
6592 23:03:29.900072 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 8)
6593 23:03:29.903222 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6594 23:03:29.906686 [Gating] SW calibration Done
6595 23:03:29.907257 ==
6596 23:03:29.909834 Dram Type= 6, Freq= 0, CH_1, rank 1
6597 23:03:29.913011 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6598 23:03:29.913484 ==
6599 23:03:29.916447 RX Vref Scan: 0
6600 23:03:29.916952
6601 23:03:29.917324 RX Vref 0 -> 0, step: 1
6602 23:03:29.917674
6603 23:03:29.919884 RX Delay -410 -> 252, step: 16
6604 23:03:29.926559 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6605 23:03:29.929616 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6606 23:03:29.932939 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6607 23:03:29.936766 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6608 23:03:29.939717 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6609 23:03:29.946546 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6610 23:03:29.949664 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6611 23:03:29.953143 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6612 23:03:29.956166 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6613 23:03:29.962811 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6614 23:03:29.966237 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6615 23:03:29.969265 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6616 23:03:29.976294 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6617 23:03:29.979652 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6618 23:03:29.982799 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6619 23:03:29.986326 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6620 23:03:29.986887 ==
6621 23:03:29.989474 Dram Type= 6, Freq= 0, CH_1, rank 1
6622 23:03:29.996213 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6623 23:03:29.996811 ==
6624 23:03:29.997196 DQS Delay:
6625 23:03:29.999530 DQS0 = 43, DQS1 = 59
6626 23:03:30.000089 DQM Delay:
6627 23:03:30.002894 DQM0 = 11, DQM1 = 16
6628 23:03:30.003457 DQ Delay:
6629 23:03:30.005823 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6630 23:03:30.009937 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6631 23:03:30.010507 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6632 23:03:30.013098 DQ12 =32, DQ13 =24, DQ14 =24, DQ15 =24
6633 23:03:30.016014
6634 23:03:30.016607
6635 23:03:30.016982 ==
6636 23:03:30.019498 Dram Type= 6, Freq= 0, CH_1, rank 1
6637 23:03:30.022710 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6638 23:03:30.023276 ==
6639 23:03:30.023655
6640 23:03:30.024004
6641 23:03:30.025943 TX Vref Scan disable
6642 23:03:30.026407 == TX Byte 0 ==
6643 23:03:30.029313 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6644 23:03:30.035755 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6645 23:03:30.036318 == TX Byte 1 ==
6646 23:03:30.039253 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6647 23:03:30.045643 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6648 23:03:30.046201 ==
6649 23:03:30.049010 Dram Type= 6, Freq= 0, CH_1, rank 1
6650 23:03:30.052675 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6651 23:03:30.053246 ==
6652 23:03:30.053627
6653 23:03:30.053980
6654 23:03:30.055333 TX Vref Scan disable
6655 23:03:30.055798 == TX Byte 0 ==
6656 23:03:30.062072 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6657 23:03:30.065448 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6658 23:03:30.065917 == TX Byte 1 ==
6659 23:03:30.068765 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6660 23:03:30.075700 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6661 23:03:30.076274
6662 23:03:30.076710 [DATLAT]
6663 23:03:30.078763 Freq=400, CH1 RK1
6664 23:03:30.079338
6665 23:03:30.079748 DATLAT Default: 0xd
6666 23:03:30.082133 0, 0xFFFF, sum = 0
6667 23:03:30.082862 1, 0xFFFF, sum = 0
6668 23:03:30.085157 2, 0xFFFF, sum = 0
6669 23:03:30.085631 3, 0xFFFF, sum = 0
6670 23:03:30.088597 4, 0xFFFF, sum = 0
6671 23:03:30.089076 5, 0xFFFF, sum = 0
6672 23:03:30.092092 6, 0xFFFF, sum = 0
6673 23:03:30.092727 7, 0xFFFF, sum = 0
6674 23:03:30.095527 8, 0xFFFF, sum = 0
6675 23:03:30.096123 9, 0xFFFF, sum = 0
6676 23:03:30.098851 10, 0xFFFF, sum = 0
6677 23:03:30.099424 11, 0xFFFF, sum = 0
6678 23:03:30.102137 12, 0x0, sum = 1
6679 23:03:30.102711 13, 0x0, sum = 2
6680 23:03:30.105403 14, 0x0, sum = 3
6681 23:03:30.106201 15, 0x0, sum = 4
6682 23:03:30.108942 best_step = 13
6683 23:03:30.109515
6684 23:03:30.109958 ==
6685 23:03:30.112190 Dram Type= 6, Freq= 0, CH_1, rank 1
6686 23:03:30.115254 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6687 23:03:30.115829 ==
6688 23:03:30.118726 RX Vref Scan: 0
6689 23:03:30.119293
6690 23:03:30.119669 RX Vref 0 -> 0, step: 1
6691 23:03:30.120020
6692 23:03:30.121954 RX Delay -359 -> 252, step: 8
6693 23:03:30.130141 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6694 23:03:30.133458 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6695 23:03:30.136684 iDelay=217, Bit 2, Center -44 (-287 ~ 200) 488
6696 23:03:30.143154 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
6697 23:03:30.146575 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6698 23:03:30.149536 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6699 23:03:30.153173 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6700 23:03:30.156400 iDelay=217, Bit 7, Center -40 (-279 ~ 200) 480
6701 23:03:30.162757 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6702 23:03:30.166178 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6703 23:03:30.169486 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6704 23:03:30.176419 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
6705 23:03:30.179470 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6706 23:03:30.182801 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6707 23:03:30.186361 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6708 23:03:30.192986 iDelay=217, Bit 15, Center -40 (-279 ~ 200) 480
6709 23:03:30.193550 ==
6710 23:03:30.196256 Dram Type= 6, Freq= 0, CH_1, rank 1
6711 23:03:30.199806 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6712 23:03:30.200371 ==
6713 23:03:30.200834 DQS Delay:
6714 23:03:30.202685 DQS0 = 44, DQS1 = 64
6715 23:03:30.203250 DQM Delay:
6716 23:03:30.206059 DQM0 = 6, DQM1 = 16
6717 23:03:30.206626 DQ Delay:
6718 23:03:30.209395 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6719 23:03:30.212701 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =4
6720 23:03:30.216127 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6721 23:03:30.219471 DQ12 =24, DQ13 =28, DQ14 =24, DQ15 =24
6722 23:03:30.220029
6723 23:03:30.220401
6724 23:03:30.225747 [DQSOSCAuto] RK1, (LSB)MR18= 0xb7b7, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps
6725 23:03:30.228901 CH1 RK1: MR19=C0C, MR18=B7B7
6726 23:03:30.235725 CH1_RK1: MR19=0xC0C, MR18=0xB7B7, DQSOSC=387, MR23=63, INC=394, DEC=262
6727 23:03:30.238733 [RxdqsGatingPostProcess] freq 400
6728 23:03:30.245930 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6729 23:03:30.246504 Pre-setting of DQS Precalculation
6730 23:03:30.252502 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6731 23:03:30.258710 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6732 23:03:30.265300 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6733 23:03:30.265772
6734 23:03:30.266171
6735 23:03:30.268467 [Calibration Summary] 800 Mbps
6736 23:03:30.272448 CH 0, Rank 0
6737 23:03:30.273074 SW Impedance : PASS
6738 23:03:30.275057 DUTY Scan : NO K
6739 23:03:30.278471 ZQ Calibration : PASS
6740 23:03:30.278939 Jitter Meter : NO K
6741 23:03:30.282042 CBT Training : PASS
6742 23:03:30.284979 Write leveling : PASS
6743 23:03:30.285632 RX DQS gating : PASS
6744 23:03:30.288339 RX DQ/DQS(RDDQC) : PASS
6745 23:03:30.291479 TX DQ/DQS : PASS
6746 23:03:30.291910 RX DATLAT : PASS
6747 23:03:30.294713 RX DQ/DQS(Engine): PASS
6748 23:03:30.298710 TX OE : NO K
6749 23:03:30.299256 All Pass.
6750 23:03:30.299606
6751 23:03:30.299919 CH 0, Rank 1
6752 23:03:30.301328 SW Impedance : PASS
6753 23:03:30.304754 DUTY Scan : NO K
6754 23:03:30.305181 ZQ Calibration : PASS
6755 23:03:30.308349 Jitter Meter : NO K
6756 23:03:30.311728 CBT Training : PASS
6757 23:03:30.312283 Write leveling : NO K
6758 23:03:30.314807 RX DQS gating : PASS
6759 23:03:30.317848 RX DQ/DQS(RDDQC) : PASS
6760 23:03:30.318318 TX DQ/DQS : PASS
6761 23:03:30.321456 RX DATLAT : PASS
6762 23:03:30.322017 RX DQ/DQS(Engine): PASS
6763 23:03:30.324981 TX OE : NO K
6764 23:03:30.325542 All Pass.
6765 23:03:30.325919
6766 23:03:30.327911 CH 1, Rank 0
6767 23:03:30.328389 SW Impedance : PASS
6768 23:03:30.331602 DUTY Scan : NO K
6769 23:03:30.334879 ZQ Calibration : PASS
6770 23:03:30.335441 Jitter Meter : NO K
6771 23:03:30.337579 CBT Training : PASS
6772 23:03:30.341208 Write leveling : PASS
6773 23:03:30.341772 RX DQS gating : PASS
6774 23:03:30.344846 RX DQ/DQS(RDDQC) : PASS
6775 23:03:30.347884 TX DQ/DQS : PASS
6776 23:03:30.348441 RX DATLAT : PASS
6777 23:03:30.351347 RX DQ/DQS(Engine): PASS
6778 23:03:30.354372 TX OE : NO K
6779 23:03:30.354873 All Pass.
6780 23:03:30.355338
6781 23:03:30.355694 CH 1, Rank 1
6782 23:03:30.357244 SW Impedance : PASS
6783 23:03:30.361022 DUTY Scan : NO K
6784 23:03:30.361720 ZQ Calibration : PASS
6785 23:03:30.363932 Jitter Meter : NO K
6786 23:03:30.368012 CBT Training : PASS
6787 23:03:30.368631 Write leveling : NO K
6788 23:03:30.370910 RX DQS gating : PASS
6789 23:03:30.374426 RX DQ/DQS(RDDQC) : PASS
6790 23:03:30.374992 TX DQ/DQS : PASS
6791 23:03:30.377251 RX DATLAT : PASS
6792 23:03:30.380948 RX DQ/DQS(Engine): PASS
6793 23:03:30.381515 TX OE : NO K
6794 23:03:30.381896 All Pass.
6795 23:03:30.384663
6796 23:03:30.385237 DramC Write-DBI off
6797 23:03:30.387689 PER_BANK_REFRESH: Hybrid Mode
6798 23:03:30.388249 TX_TRACKING: ON
6799 23:03:30.397516 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6800 23:03:30.400780 [FAST_K] Save calibration result to emmc
6801 23:03:30.404163 dramc_set_vcore_voltage set vcore to 725000
6802 23:03:30.407754 Read voltage for 1600, 0
6803 23:03:30.408334 Vio18 = 0
6804 23:03:30.410936 Vcore = 725000
6805 23:03:30.411565 Vdram = 0
6806 23:03:30.412127 Vddq = 0
6807 23:03:30.412499 Vmddr = 0
6808 23:03:30.417523 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6809 23:03:30.424265 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6810 23:03:30.424878 MEM_TYPE=3, freq_sel=13
6811 23:03:30.427086 sv_algorithm_assistance_LP4_3733
6812 23:03:30.430386 ============ PULL DRAM RESETB DOWN ============
6813 23:03:30.437244 ========== PULL DRAM RESETB DOWN end =========
6814 23:03:30.440690 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6815 23:03:30.443965 ===================================
6816 23:03:30.447448 LPDDR4 DRAM CONFIGURATION
6817 23:03:30.450418 ===================================
6818 23:03:30.450980 EX_ROW_EN[0] = 0x0
6819 23:03:30.453887 EX_ROW_EN[1] = 0x0
6820 23:03:30.457048 LP4Y_EN = 0x0
6821 23:03:30.457516 WORK_FSP = 0x1
6822 23:03:30.460261 WL = 0x5
6823 23:03:30.460802 RL = 0x5
6824 23:03:30.463348 BL = 0x2
6825 23:03:30.463817 RPST = 0x0
6826 23:03:30.467088 RD_PRE = 0x0
6827 23:03:30.467645 WR_PRE = 0x1
6828 23:03:30.470264 WR_PST = 0x1
6829 23:03:30.470825 DBI_WR = 0x0
6830 23:03:30.473089 DBI_RD = 0x0
6831 23:03:30.473555 OTF = 0x1
6832 23:03:30.477004 ===================================
6833 23:03:30.480400 ===================================
6834 23:03:30.483256 ANA top config
6835 23:03:30.486853 ===================================
6836 23:03:30.487422 DLL_ASYNC_EN = 0
6837 23:03:30.490124 ALL_SLAVE_EN = 0
6838 23:03:30.493007 NEW_RANK_MODE = 1
6839 23:03:30.496305 DLL_IDLE_MODE = 1
6840 23:03:30.500014 LP45_APHY_COMB_EN = 1
6841 23:03:30.500606 TX_ODT_DIS = 0
6842 23:03:30.503504 NEW_8X_MODE = 1
6843 23:03:30.506419 ===================================
6844 23:03:30.509426 ===================================
6845 23:03:30.513133 data_rate = 3200
6846 23:03:30.516222 CKR = 1
6847 23:03:30.519552 DQ_P2S_RATIO = 8
6848 23:03:30.523061 ===================================
6849 23:03:30.526086 CA_P2S_RATIO = 8
6850 23:03:30.526558 DQ_CA_OPEN = 0
6851 23:03:30.529474 DQ_SEMI_OPEN = 0
6852 23:03:30.532602 CA_SEMI_OPEN = 0
6853 23:03:30.536018 CA_FULL_RATE = 0
6854 23:03:30.539426 DQ_CKDIV4_EN = 0
6855 23:03:30.542636 CA_CKDIV4_EN = 0
6856 23:03:30.543206 CA_PREDIV_EN = 0
6857 23:03:30.546029 PH8_DLY = 12
6858 23:03:30.549170 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6859 23:03:30.552978 DQ_AAMCK_DIV = 4
6860 23:03:30.555546 CA_AAMCK_DIV = 4
6861 23:03:30.559155 CA_ADMCK_DIV = 4
6862 23:03:30.559632 DQ_TRACK_CA_EN = 0
6863 23:03:30.562196 CA_PICK = 1600
6864 23:03:30.565628 CA_MCKIO = 1600
6865 23:03:30.569145 MCKIO_SEMI = 0
6866 23:03:30.572427 PLL_FREQ = 3068
6867 23:03:30.575739 DQ_UI_PI_RATIO = 32
6868 23:03:30.579352 CA_UI_PI_RATIO = 0
6869 23:03:30.582679 ===================================
6870 23:03:30.585473 ===================================
6871 23:03:30.585935 memory_type:LPDDR4
6872 23:03:30.588780 GP_NUM : 10
6873 23:03:30.592252 SRAM_EN : 1
6874 23:03:30.592844 MD32_EN : 0
6875 23:03:30.595459 ===================================
6876 23:03:30.598746 [ANA_INIT] >>>>>>>>>>>>>>
6877 23:03:30.602006 <<<<<< [CONFIGURE PHASE]: ANA_TX
6878 23:03:30.605616 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6879 23:03:30.608765 ===================================
6880 23:03:30.612202 data_rate = 3200,PCW = 0X7600
6881 23:03:30.615070 ===================================
6882 23:03:30.618695 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6883 23:03:30.621681 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6884 23:03:30.628490 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6885 23:03:30.634899 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6886 23:03:30.637927 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6887 23:03:30.641829 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6888 23:03:30.642396 [ANA_INIT] flow start
6889 23:03:30.644789 [ANA_INIT] PLL >>>>>>>>
6890 23:03:30.648343 [ANA_INIT] PLL <<<<<<<<
6891 23:03:30.648910 [ANA_INIT] MIDPI >>>>>>>>
6892 23:03:30.651892 [ANA_INIT] MIDPI <<<<<<<<
6893 23:03:30.654809 [ANA_INIT] DLL >>>>>>>>
6894 23:03:30.655369 [ANA_INIT] DLL <<<<<<<<
6895 23:03:30.657957 [ANA_INIT] flow end
6896 23:03:30.661096 ============ LP4 DIFF to SE enter ============
6897 23:03:30.664645 ============ LP4 DIFF to SE exit ============
6898 23:03:30.667993 [ANA_INIT] <<<<<<<<<<<<<
6899 23:03:30.671654 [Flow] Enable top DCM control >>>>>
6900 23:03:30.674690 [Flow] Enable top DCM control <<<<<
6901 23:03:30.678436 Enable DLL master slave shuffle
6902 23:03:30.684879 ==============================================================
6903 23:03:30.685441 Gating Mode config
6904 23:03:30.691300 ==============================================================
6905 23:03:30.694539 Config description:
6906 23:03:30.701461 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6907 23:03:30.708078 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6908 23:03:30.714813 SELPH_MODE 0: By rank 1: By Phase
6909 23:03:30.717700 ==============================================================
6910 23:03:30.721145 GAT_TRACK_EN = 1
6911 23:03:30.724979 RX_GATING_MODE = 2
6912 23:03:30.727617 RX_GATING_TRACK_MODE = 2
6913 23:03:30.731060 SELPH_MODE = 1
6914 23:03:30.734368 PICG_EARLY_EN = 1
6915 23:03:30.737900 VALID_LAT_VALUE = 1
6916 23:03:30.744390 ==============================================================
6917 23:03:30.747519 Enter into Gating configuration >>>>
6918 23:03:30.750915 Exit from Gating configuration <<<<
6919 23:03:30.754663 Enter into DVFS_PRE_config >>>>>
6920 23:03:30.763986 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6921 23:03:30.767721 Exit from DVFS_PRE_config <<<<<
6922 23:03:30.770923 Enter into PICG configuration >>>>
6923 23:03:30.774247 Exit from PICG configuration <<<<
6924 23:03:30.777396 [RX_INPUT] configuration >>>>>
6925 23:03:30.777856 [RX_INPUT] configuration <<<<<
6926 23:03:30.784076 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6927 23:03:30.790805 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6928 23:03:30.794213 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6929 23:03:30.800824 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6930 23:03:30.807551 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6931 23:03:30.813774 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6932 23:03:30.817059 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6933 23:03:30.820411 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6934 23:03:30.827364 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6935 23:03:30.829963 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6936 23:03:30.833685 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6937 23:03:30.840410 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6938 23:03:30.843488 ===================================
6939 23:03:30.844051 LPDDR4 DRAM CONFIGURATION
6940 23:03:30.846589 ===================================
6941 23:03:30.849926 EX_ROW_EN[0] = 0x0
6942 23:03:30.853449 EX_ROW_EN[1] = 0x0
6943 23:03:30.853968 LP4Y_EN = 0x0
6944 23:03:30.856500 WORK_FSP = 0x1
6945 23:03:30.856955 WL = 0x5
6946 23:03:30.860194 RL = 0x5
6947 23:03:30.860662 BL = 0x2
6948 23:03:30.863522 RPST = 0x0
6949 23:03:30.864164 RD_PRE = 0x0
6950 23:03:30.866885 WR_PRE = 0x1
6951 23:03:30.867419 WR_PST = 0x1
6952 23:03:30.870142 DBI_WR = 0x0
6953 23:03:30.870667 DBI_RD = 0x0
6954 23:03:30.873188 OTF = 0x1
6955 23:03:30.877007 ===================================
6956 23:03:30.880037 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6957 23:03:30.883153 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6958 23:03:30.889819 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6959 23:03:30.893422 ===================================
6960 23:03:30.893945 LPDDR4 DRAM CONFIGURATION
6961 23:03:30.896211 ===================================
6962 23:03:30.900025 EX_ROW_EN[0] = 0x10
6963 23:03:30.900582 EX_ROW_EN[1] = 0x0
6964 23:03:30.903077 LP4Y_EN = 0x0
6965 23:03:30.906342 WORK_FSP = 0x1
6966 23:03:30.906859 WL = 0x5
6967 23:03:30.909729 RL = 0x5
6968 23:03:30.910246 BL = 0x2
6969 23:03:30.912740 RPST = 0x0
6970 23:03:30.913157 RD_PRE = 0x0
6971 23:03:30.916591 WR_PRE = 0x1
6972 23:03:30.917106 WR_PST = 0x1
6973 23:03:30.919414 DBI_WR = 0x0
6974 23:03:30.919830 DBI_RD = 0x0
6975 23:03:30.922885 OTF = 0x1
6976 23:03:30.926190 ===================================
6977 23:03:30.932969 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6978 23:03:30.933490 ==
6979 23:03:30.936211 Dram Type= 6, Freq= 0, CH_0, rank 0
6980 23:03:30.939582 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
6981 23:03:30.940017 ==
6982 23:03:30.942962 [Duty_Offset_Calibration]
6983 23:03:30.943377 B0:0 B1:2 CA:1
6984 23:03:30.943734
6985 23:03:30.946420 [DutyScan_Calibration_Flow] k_type=0
6986 23:03:30.956642
6987 23:03:30.957151 ==CLK 0==
6988 23:03:30.959661 Final CLK duty delay cell = 0
6989 23:03:30.963324 [0] MAX Duty = 5156%(X100), DQS PI = 22
6990 23:03:30.966395 [0] MIN Duty = 4938%(X100), DQS PI = 54
6991 23:03:30.966912 [0] AVG Duty = 5047%(X100)
6992 23:03:30.969898
6993 23:03:30.972872 CH0 CLK Duty spec in!! Max-Min= 218%
6994 23:03:30.976453 [DutyScan_Calibration_Flow] ====Done====
6995 23:03:30.977023
6996 23:03:30.979542 [DutyScan_Calibration_Flow] k_type=1
6997 23:03:30.996671
6998 23:03:30.997189 ==DQS 0 ==
6999 23:03:31.000267 Final DQS duty delay cell = 0
7000 23:03:31.003086 [0] MAX Duty = 5156%(X100), DQS PI = 34
7001 23:03:31.006734 [0] MIN Duty = 5062%(X100), DQS PI = 6
7002 23:03:31.009695 [0] AVG Duty = 5109%(X100)
7003 23:03:31.010248
7004 23:03:31.010622 ==DQS 1 ==
7005 23:03:31.013132 Final DQS duty delay cell = 0
7006 23:03:31.016352 [0] MAX Duty = 5062%(X100), DQS PI = 6
7007 23:03:31.020119 [0] MIN Duty = 4876%(X100), DQS PI = 16
7008 23:03:31.023290 [0] AVG Duty = 4969%(X100)
7009 23:03:31.023801
7010 23:03:31.026097 CH0 DQS 0 Duty spec in!! Max-Min= 94%
7011 23:03:31.026608
7012 23:03:31.029324 CH0 DQS 1 Duty spec in!! Max-Min= 186%
7013 23:03:31.032898 [DutyScan_Calibration_Flow] ====Done====
7014 23:03:31.033410
7015 23:03:31.035963 [DutyScan_Calibration_Flow] k_type=3
7016 23:03:31.053731
7017 23:03:31.054284 ==DQM 0 ==
7018 23:03:31.056764 Final DQM duty delay cell = 0
7019 23:03:31.060035 [0] MAX Duty = 5187%(X100), DQS PI = 22
7020 23:03:31.063326 [0] MIN Duty = 4907%(X100), DQS PI = 42
7021 23:03:31.066594 [0] AVG Duty = 5047%(X100)
7022 23:03:31.067055
7023 23:03:31.067507 ==DQM 1 ==
7024 23:03:31.070293 Final DQM duty delay cell = 0
7025 23:03:31.073162 [0] MAX Duty = 5031%(X100), DQS PI = 4
7026 23:03:31.076636 [0] MIN Duty = 4782%(X100), DQS PI = 14
7027 23:03:31.080556 [0] AVG Duty = 4906%(X100)
7028 23:03:31.081121
7029 23:03:31.083243 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7030 23:03:31.083703
7031 23:03:31.086795 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7032 23:03:31.089945 [DutyScan_Calibration_Flow] ====Done====
7033 23:03:31.090463
7034 23:03:31.093223 [DutyScan_Calibration_Flow] k_type=2
7035 23:03:31.109981
7036 23:03:31.110535 ==DQ 0 ==
7037 23:03:31.113447 Final DQ duty delay cell = 0
7038 23:03:31.116774 [0] MAX Duty = 5218%(X100), DQS PI = 18
7039 23:03:31.120111 [0] MIN Duty = 4969%(X100), DQS PI = 54
7040 23:03:31.120714 [0] AVG Duty = 5093%(X100)
7041 23:03:31.123159
7042 23:03:31.123716 ==DQ 1 ==
7043 23:03:31.126584 Final DQ duty delay cell = -4
7044 23:03:31.129591 [-4] MAX Duty = 5062%(X100), DQS PI = 4
7045 23:03:31.133327 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7046 23:03:31.136669 [-4] AVG Duty = 4953%(X100)
7047 23:03:31.137232
7048 23:03:31.139696 CH0 DQ 0 Duty spec in!! Max-Min= 249%
7049 23:03:31.140256
7050 23:03:31.143005 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7051 23:03:31.146860 [DutyScan_Calibration_Flow] ====Done====
7052 23:03:31.147422 ==
7053 23:03:31.149989 Dram Type= 6, Freq= 0, CH_1, rank 0
7054 23:03:31.153474 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7055 23:03:31.154034 ==
7056 23:03:31.156234 [Duty_Offset_Calibration]
7057 23:03:31.156801 B0:0 B1:5 CA:-5
7058 23:03:31.157234
7059 23:03:31.159656 [DutyScan_Calibration_Flow] k_type=0
7060 23:03:31.170740
7061 23:03:31.171297 ==CLK 0==
7062 23:03:31.173921 Final CLK duty delay cell = 0
7063 23:03:31.177302 [0] MAX Duty = 5156%(X100), DQS PI = 20
7064 23:03:31.180215 [0] MIN Duty = 4906%(X100), DQS PI = 52
7065 23:03:31.183606 [0] AVG Duty = 5031%(X100)
7066 23:03:31.184065
7067 23:03:31.187061 CH1 CLK Duty spec in!! Max-Min= 250%
7068 23:03:31.190585 [DutyScan_Calibration_Flow] ====Done====
7069 23:03:31.191138
7070 23:03:31.193733 [DutyScan_Calibration_Flow] k_type=1
7071 23:03:31.209473
7072 23:03:31.210028 ==DQS 0 ==
7073 23:03:31.212830 Final DQS duty delay cell = 0
7074 23:03:31.215964 [0] MAX Duty = 5156%(X100), DQS PI = 18
7075 23:03:31.219147 [0] MIN Duty = 4876%(X100), DQS PI = 42
7076 23:03:31.222427 [0] AVG Duty = 5016%(X100)
7077 23:03:31.222886
7078 23:03:31.223251 ==DQS 1 ==
7079 23:03:31.226035 Final DQS duty delay cell = -4
7080 23:03:31.229061 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7081 23:03:31.232228 [-4] MIN Duty = 4844%(X100), DQS PI = 38
7082 23:03:31.235633 [-4] AVG Duty = 4922%(X100)
7083 23:03:31.236091
7084 23:03:31.239305 CH1 DQS 0 Duty spec in!! Max-Min= 280%
7085 23:03:31.239821
7086 23:03:31.242685 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7087 23:03:31.245801 [DutyScan_Calibration_Flow] ====Done====
7088 23:03:31.246360
7089 23:03:31.249120 [DutyScan_Calibration_Flow] k_type=3
7090 23:03:31.265152
7091 23:03:31.265938 ==DQM 0 ==
7092 23:03:31.268292 Final DQM duty delay cell = -4
7093 23:03:31.271751 [-4] MAX Duty = 5093%(X100), DQS PI = 34
7094 23:03:31.275370 [-4] MIN Duty = 4813%(X100), DQS PI = 42
7095 23:03:31.278563 [-4] AVG Duty = 4953%(X100)
7096 23:03:31.279024
7097 23:03:31.279386 ==DQM 1 ==
7098 23:03:31.281717 Final DQM duty delay cell = -4
7099 23:03:31.285209 [-4] MAX Duty = 5062%(X100), DQS PI = 18
7100 23:03:31.288591 [-4] MIN Duty = 4876%(X100), DQS PI = 40
7101 23:03:31.291879 [-4] AVG Duty = 4969%(X100)
7102 23:03:31.292439
7103 23:03:31.294891 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7104 23:03:31.295353
7105 23:03:31.298704 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7106 23:03:31.301631 [DutyScan_Calibration_Flow] ====Done====
7107 23:03:31.302200
7108 23:03:31.305025 [DutyScan_Calibration_Flow] k_type=2
7109 23:03:31.323058
7110 23:03:31.323652 ==DQ 0 ==
7111 23:03:31.325997 Final DQ duty delay cell = 0
7112 23:03:31.329304 [0] MAX Duty = 5093%(X100), DQS PI = 4
7113 23:03:31.332736 [0] MIN Duty = 4969%(X100), DQS PI = 46
7114 23:03:31.333153 [0] AVG Duty = 5031%(X100)
7115 23:03:31.333489
7116 23:03:31.335910 ==DQ 1 ==
7117 23:03:31.339207 Final DQ duty delay cell = 0
7118 23:03:31.342802 [0] MAX Duty = 5031%(X100), DQS PI = 6
7119 23:03:31.345962 [0] MIN Duty = 4907%(X100), DQS PI = 22
7120 23:03:31.346482 [0] AVG Duty = 4969%(X100)
7121 23:03:31.346815
7122 23:03:31.349474 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7123 23:03:31.352955
7124 23:03:31.355897 CH1 DQ 1 Duty spec in!! Max-Min= 124%
7125 23:03:31.359452 [DutyScan_Calibration_Flow] ====Done====
7126 23:03:31.362137 nWR fixed to 30
7127 23:03:31.362573 [ModeRegInit_LP4] CH0 RK0
7128 23:03:31.365617 [ModeRegInit_LP4] CH0 RK1
7129 23:03:31.368978 [ModeRegInit_LP4] CH1 RK0
7130 23:03:31.372108 [ModeRegInit_LP4] CH1 RK1
7131 23:03:31.372557 match AC timing 4
7132 23:03:31.375420 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7133 23:03:31.382565 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7134 23:03:31.385588 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7135 23:03:31.392404 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7136 23:03:31.395413 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7137 23:03:31.395832 [MiockJmeterHQA]
7138 23:03:31.396159
7139 23:03:31.398880 [DramcMiockJmeter] u1RxGatingPI = 0
7140 23:03:31.402275 0 : 4253, 4026
7141 23:03:31.402809 4 : 4363, 4137
7142 23:03:31.405296 8 : 4252, 4027
7143 23:03:31.405720 12 : 4253, 4026
7144 23:03:31.406063 16 : 4252, 4027
7145 23:03:31.408568 20 : 4253, 4027
7146 23:03:31.408986 24 : 4363, 4137
7147 23:03:31.411886 28 : 4363, 4138
7148 23:03:31.412307 32 : 4253, 4026
7149 23:03:31.415194 36 : 4252, 4027
7150 23:03:31.415615 40 : 4253, 4027
7151 23:03:31.418971 44 : 4253, 4027
7152 23:03:31.419503 48 : 4255, 4030
7153 23:03:31.419843 52 : 4363, 4138
7154 23:03:31.422116 56 : 4253, 4026
7155 23:03:31.422639 60 : 4250, 4027
7156 23:03:31.425421 64 : 4252, 4027
7157 23:03:31.425940 68 : 4252, 4029
7158 23:03:31.428651 72 : 4250, 4027
7159 23:03:31.429188 76 : 4363, 4138
7160 23:03:31.429533 80 : 4360, 4138
7161 23:03:31.431807 84 : 4250, 4026
7162 23:03:31.432226 88 : 4250, 4027
7163 23:03:31.435332 92 : 4250, 4026
7164 23:03:31.435856 96 : 4250, 4026
7165 23:03:31.438595 100 : 4252, 2059
7166 23:03:31.439120 104 : 4250, 0
7167 23:03:31.439455 108 : 4253, 0
7168 23:03:31.442483 112 : 4250, 0
7169 23:03:31.443012 116 : 4250, 0
7170 23:03:31.444960 120 : 4253, 0
7171 23:03:31.445380 124 : 4361, 0
7172 23:03:31.445719 128 : 4361, 0
7173 23:03:31.448587 132 : 4363, 0
7174 23:03:31.449120 136 : 4250, 0
7175 23:03:31.451823 140 : 4250, 0
7176 23:03:31.452346 144 : 4250, 0
7177 23:03:31.452725 148 : 4250, 0
7178 23:03:31.455030 152 : 4250, 0
7179 23:03:31.455452 156 : 4250, 0
7180 23:03:31.458276 160 : 4252, 0
7181 23:03:31.458743 164 : 4250, 0
7182 23:03:31.459078 168 : 4250, 0
7183 23:03:31.461606 172 : 4253, 0
7184 23:03:31.462027 176 : 4361, 0
7185 23:03:31.464775 180 : 4361, 0
7186 23:03:31.465196 184 : 4363, 0
7187 23:03:31.465533 188 : 4360, 0
7188 23:03:31.468038 192 : 4250, 0
7189 23:03:31.468626 196 : 4250, 0
7190 23:03:31.468978 200 : 4250, 0
7191 23:03:31.471779 204 : 4250, 0
7192 23:03:31.472298 208 : 4249, 0
7193 23:03:31.475014 212 : 4250, 0
7194 23:03:31.475538 216 : 4250, 0
7195 23:03:31.478100 220 : 4250, 399
7196 23:03:31.478521 224 : 4361, 4033
7197 23:03:31.478859 228 : 4250, 4027
7198 23:03:31.481322 232 : 4360, 4138
7199 23:03:31.481741 236 : 4363, 4140
7200 23:03:31.484872 240 : 4251, 4027
7201 23:03:31.485393 244 : 4250, 4027
7202 23:03:31.488217 248 : 4363, 4140
7203 23:03:31.488810 252 : 4250, 4027
7204 23:03:31.491369 256 : 4250, 4026
7205 23:03:31.491824 260 : 4250, 4027
7206 23:03:31.494618 264 : 4252, 4029
7207 23:03:31.495036 268 : 4250, 4027
7208 23:03:31.498408 272 : 4250, 4026
7209 23:03:31.498933 276 : 4361, 4138
7210 23:03:31.501307 280 : 4250, 4027
7211 23:03:31.501727 284 : 4250, 4027
7212 23:03:31.502060 288 : 4361, 4138
7213 23:03:31.504895 292 : 4250, 4026
7214 23:03:31.505424 296 : 4250, 4027
7215 23:03:31.508084 300 : 4363, 4140
7216 23:03:31.508642 304 : 4250, 4027
7217 23:03:31.511653 308 : 4250, 4027
7218 23:03:31.512180 312 : 4250, 4027
7219 23:03:31.514905 316 : 4250, 4027
7220 23:03:31.515440 320 : 4250, 4027
7221 23:03:31.518332 324 : 4250, 4026
7222 23:03:31.518857 328 : 4361, 4138
7223 23:03:31.521000 332 : 4250, 4027
7224 23:03:31.521421 336 : 4250, 3784
7225 23:03:31.524334 340 : 4361, 1776
7226 23:03:31.524889
7227 23:03:31.525219 MIOCK jitter meter ch=0
7228 23:03:31.525582
7229 23:03:31.527983 1T = (340-100) = 240 dly cells
7230 23:03:31.534470 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 271/100 ps
7231 23:03:31.534985 ==
7232 23:03:31.537899 Dram Type= 6, Freq= 0, CH_0, rank 0
7233 23:03:31.541351 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7234 23:03:31.541870 ==
7235 23:03:31.547838 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7236 23:03:31.550856 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7237 23:03:31.554182 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7238 23:03:31.560772 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7239 23:03:31.569877 [CA 0] Center 41 (11~72) winsize 62
7240 23:03:31.573253 [CA 1] Center 41 (11~72) winsize 62
7241 23:03:31.576328 [CA 2] Center 37 (7~68) winsize 62
7242 23:03:31.580010 [CA 3] Center 37 (7~67) winsize 61
7243 23:03:31.583353 [CA 4] Center 35 (5~66) winsize 62
7244 23:03:31.586615 [CA 5] Center 35 (5~65) winsize 61
7245 23:03:31.587177
7246 23:03:31.589720 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7247 23:03:31.590282
7248 23:03:31.593128 [CATrainingPosCal] consider 1 rank data
7249 23:03:31.596468 u2DelayCellTimex100 = 271/100 ps
7250 23:03:31.599955 CA0 delay=41 (11~72),Diff = 6 PI (21 cell)
7251 23:03:31.606384 CA1 delay=41 (11~72),Diff = 6 PI (21 cell)
7252 23:03:31.609738 CA2 delay=37 (7~68),Diff = 2 PI (7 cell)
7253 23:03:31.613181 CA3 delay=37 (7~67),Diff = 2 PI (7 cell)
7254 23:03:31.616398 CA4 delay=35 (5~66),Diff = 0 PI (0 cell)
7255 23:03:31.619626 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7256 23:03:31.620185
7257 23:03:31.623171 CA PerBit enable=1, Macro0, CA PI delay=35
7258 23:03:31.623732
7259 23:03:31.626106 [CBTSetCACLKResult] CA Dly = 35
7260 23:03:31.629330 CS Dly: 11 (0~42)
7261 23:03:31.632619 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7262 23:03:31.636185 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7263 23:03:31.636792 ==
7264 23:03:31.639391 Dram Type= 6, Freq= 0, CH_0, rank 1
7265 23:03:31.642821 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7266 23:03:31.646219 ==
7267 23:03:31.649132 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7268 23:03:31.652762 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7269 23:03:31.659286 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7270 23:03:31.662482 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7271 23:03:31.672372 [CA 0] Center 42 (12~73) winsize 62
7272 23:03:31.675780 [CA 1] Center 41 (11~72) winsize 62
7273 23:03:31.678981 [CA 2] Center 38 (9~68) winsize 60
7274 23:03:31.682366 [CA 3] Center 37 (7~67) winsize 61
7275 23:03:31.685358 [CA 4] Center 35 (5~65) winsize 61
7276 23:03:31.688685 [CA 5] Center 35 (5~66) winsize 62
7277 23:03:31.689301
7278 23:03:31.691993 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7279 23:03:31.692453
7280 23:03:31.695240 [CATrainingPosCal] consider 2 rank data
7281 23:03:31.698574 u2DelayCellTimex100 = 271/100 ps
7282 23:03:31.705213 CA0 delay=42 (12~72),Diff = 7 PI (25 cell)
7283 23:03:31.708730 CA1 delay=41 (11~72),Diff = 6 PI (21 cell)
7284 23:03:31.712150 CA2 delay=38 (9~68),Diff = 3 PI (10 cell)
7285 23:03:31.715362 CA3 delay=37 (7~67),Diff = 2 PI (7 cell)
7286 23:03:31.718591 CA4 delay=35 (5~65),Diff = 0 PI (0 cell)
7287 23:03:31.721938 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7288 23:03:31.722398
7289 23:03:31.725430 CA PerBit enable=1, Macro0, CA PI delay=35
7290 23:03:31.725988
7291 23:03:31.728828 [CBTSetCACLKResult] CA Dly = 35
7292 23:03:31.731931 CS Dly: 11 (0~43)
7293 23:03:31.734851 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7294 23:03:31.738350 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7295 23:03:31.738764
7296 23:03:31.741751 ----->DramcWriteLeveling(PI) begin...
7297 23:03:31.742164 ==
7298 23:03:31.744860 Dram Type= 6, Freq= 0, CH_0, rank 0
7299 23:03:31.751282 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7300 23:03:31.751698 ==
7301 23:03:31.755168 Write leveling (Byte 0): 29 => 29
7302 23:03:31.758011 Write leveling (Byte 1): 26 => 26
7303 23:03:31.758435 DramcWriteLeveling(PI) end<-----
7304 23:03:31.758805
7305 23:03:31.761641 ==
7306 23:03:31.764679 Dram Type= 6, Freq= 0, CH_0, rank 0
7307 23:03:31.768340 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7308 23:03:31.769222 ==
7309 23:03:31.771313 [Gating] SW mode calibration
7310 23:03:31.778140 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7311 23:03:31.781352 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7312 23:03:31.787895 0 12 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7313 23:03:31.791308 0 12 4 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
7314 23:03:31.794571 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7315 23:03:31.801002 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7316 23:03:31.804598 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7317 23:03:31.808152 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7318 23:03:31.814894 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7319 23:03:31.818014 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7320 23:03:31.821074 0 13 0 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (1 0)
7321 23:03:31.828212 0 13 4 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (1 0)
7322 23:03:31.831289 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7323 23:03:31.834843 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7324 23:03:31.841419 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7325 23:03:31.844482 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7326 23:03:31.847906 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7327 23:03:31.854488 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7328 23:03:31.857442 0 14 0 | B1->B0 | 2323 3838 | 0 1 | (0 0) (0 0)
7329 23:03:31.861208 0 14 4 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
7330 23:03:31.867644 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7331 23:03:31.870585 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7332 23:03:31.874221 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7333 23:03:31.880784 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7334 23:03:31.883966 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7335 23:03:31.887151 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7336 23:03:31.894361 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7337 23:03:31.897284 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7338 23:03:31.900305 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7339 23:03:31.907078 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7340 23:03:31.910396 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7341 23:03:31.913898 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7342 23:03:31.920472 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7343 23:03:31.923809 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7344 23:03:31.927146 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7345 23:03:31.934083 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7346 23:03:31.937059 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7347 23:03:31.940328 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7348 23:03:31.946984 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7349 23:03:31.950579 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7350 23:03:31.953466 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7351 23:03:31.956894 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7352 23:03:31.963426 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7353 23:03:31.966717 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7354 23:03:31.970292 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7355 23:03:31.973474 Total UI for P1: 0, mck2ui 16
7356 23:03:31.976637 best dqsien dly found for B0: ( 1, 1, 0)
7357 23:03:31.983489 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7358 23:03:31.986522 Total UI for P1: 0, mck2ui 16
7359 23:03:31.990354 best dqsien dly found for B1: ( 1, 1, 4)
7360 23:03:31.993313 best DQS0 dly(MCK, UI, PI) = (1, 1, 0)
7361 23:03:31.996970 best DQS1 dly(MCK, UI, PI) = (1, 1, 4)
7362 23:03:31.997524
7363 23:03:31.999571 best DQS0 P1 dly(MCK, UI, PI) = (1, 5, 0)
7364 23:03:32.003446 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 4)
7365 23:03:32.006341 [Gating] SW calibration Done
7366 23:03:32.006801 ==
7367 23:03:32.009931 Dram Type= 6, Freq= 0, CH_0, rank 0
7368 23:03:32.013289 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7369 23:03:32.013855 ==
7370 23:03:32.016261 RX Vref Scan: 0
7371 23:03:32.016844
7372 23:03:32.017208 RX Vref 0 -> 0, step: 1
7373 23:03:32.019933
7374 23:03:32.020500 RX Delay 0 -> 252, step: 8
7375 23:03:32.022921 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7376 23:03:32.029906 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7377 23:03:32.032972 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7378 23:03:32.036367 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7379 23:03:32.039540 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7380 23:03:32.043098 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7381 23:03:32.049563 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
7382 23:03:32.052754 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7383 23:03:32.056290 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
7384 23:03:32.059291 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7385 23:03:32.062501 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7386 23:03:32.069450 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7387 23:03:32.072633 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7388 23:03:32.076179 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7389 23:03:32.079591 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
7390 23:03:32.086150 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7391 23:03:32.086707 ==
7392 23:03:32.089279 Dram Type= 6, Freq= 0, CH_0, rank 0
7393 23:03:32.092570 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7394 23:03:32.093135 ==
7395 23:03:32.093500 DQS Delay:
7396 23:03:32.095775 DQS0 = 0, DQS1 = 0
7397 23:03:32.096337 DQM Delay:
7398 23:03:32.099237 DQM0 = 130, DQM1 = 124
7399 23:03:32.099694 DQ Delay:
7400 23:03:32.102637 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =127
7401 23:03:32.105696 DQ4 =135, DQ5 =119, DQ6 =135, DQ7 =139
7402 23:03:32.109477 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
7403 23:03:32.112556 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7404 23:03:32.113129
7405 23:03:32.113496
7406 23:03:32.115620 ==
7407 23:03:32.119444 Dram Type= 6, Freq= 0, CH_0, rank 0
7408 23:03:32.122334 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7409 23:03:32.122797 ==
7410 23:03:32.123159
7411 23:03:32.123491
7412 23:03:32.126007 TX Vref Scan disable
7413 23:03:32.126466 == TX Byte 0 ==
7414 23:03:32.128986 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7415 23:03:32.135826 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7416 23:03:32.136381 == TX Byte 1 ==
7417 23:03:32.139035 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7418 23:03:32.145589 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7419 23:03:32.146148 ==
7420 23:03:32.149184 Dram Type= 6, Freq= 0, CH_0, rank 0
7421 23:03:32.152202 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7422 23:03:32.152815 ==
7423 23:03:32.165288
7424 23:03:32.168374 TX Vref early break, caculate TX vref
7425 23:03:32.171909 TX Vref=16, minBit 9, minWin=22, winSum=373
7426 23:03:32.175424 TX Vref=18, minBit 8, minWin=22, winSum=376
7427 23:03:32.178589 TX Vref=20, minBit 8, minWin=23, winSum=390
7428 23:03:32.181878 TX Vref=22, minBit 8, minWin=23, winSum=393
7429 23:03:32.184972 TX Vref=24, minBit 8, minWin=24, winSum=405
7430 23:03:32.192062 TX Vref=26, minBit 8, minWin=25, winSum=415
7431 23:03:32.194813 TX Vref=28, minBit 8, minWin=25, winSum=412
7432 23:03:32.198167 TX Vref=30, minBit 1, minWin=25, winSum=409
7433 23:03:32.201188 TX Vref=32, minBit 0, minWin=24, winSum=399
7434 23:03:32.204366 TX Vref=34, minBit 8, minWin=23, winSum=392
7435 23:03:32.210783 [TxChooseVref] Worse bit 8, Min win 25, Win sum 415, Final Vref 26
7436 23:03:32.210879
7437 23:03:32.214462 Final TX Range 0 Vref 26
7438 23:03:32.214555
7439 23:03:32.214624 ==
7440 23:03:32.217466 Dram Type= 6, Freq= 0, CH_0, rank 0
7441 23:03:32.221378 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7442 23:03:32.221853 ==
7443 23:03:32.222192
7444 23:03:32.222507
7445 23:03:32.224667 TX Vref Scan disable
7446 23:03:32.231366 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7447 23:03:32.231786 == TX Byte 0 ==
7448 23:03:32.234348 u2DelayCellOfst[0]=10 cells (3 PI)
7449 23:03:32.237978 u2DelayCellOfst[1]=18 cells (5 PI)
7450 23:03:32.240730 u2DelayCellOfst[2]=14 cells (4 PI)
7451 23:03:32.244058 u2DelayCellOfst[3]=10 cells (3 PI)
7452 23:03:32.247314 u2DelayCellOfst[4]=7 cells (2 PI)
7453 23:03:32.251052 u2DelayCellOfst[5]=0 cells (0 PI)
7454 23:03:32.253941 u2DelayCellOfst[6]=18 cells (5 PI)
7455 23:03:32.257447 u2DelayCellOfst[7]=18 cells (5 PI)
7456 23:03:32.260700 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7457 23:03:32.263751 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7458 23:03:32.267144 == TX Byte 1 ==
7459 23:03:32.270311 u2DelayCellOfst[8]=3 cells (1 PI)
7460 23:03:32.273883 u2DelayCellOfst[9]=0 cells (0 PI)
7461 23:03:32.273992 u2DelayCellOfst[10]=10 cells (3 PI)
7462 23:03:32.277139 u2DelayCellOfst[11]=7 cells (2 PI)
7463 23:03:32.280129 u2DelayCellOfst[12]=14 cells (4 PI)
7464 23:03:32.283559 u2DelayCellOfst[13]=18 cells (5 PI)
7465 23:03:32.287462 u2DelayCellOfst[14]=18 cells (5 PI)
7466 23:03:32.290312 u2DelayCellOfst[15]=14 cells (4 PI)
7467 23:03:32.296982 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
7468 23:03:32.300022 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7469 23:03:32.300110 DramC Write-DBI on
7470 23:03:32.300174 ==
7471 23:03:32.303351 Dram Type= 6, Freq= 0, CH_0, rank 0
7472 23:03:32.310136 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7473 23:03:32.310232 ==
7474 23:03:32.310299
7475 23:03:32.310359
7476 23:03:32.310415 TX Vref Scan disable
7477 23:03:32.314186 == TX Byte 0 ==
7478 23:03:32.317411 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7479 23:03:32.320622 == TX Byte 1 ==
7480 23:03:32.324118 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
7481 23:03:32.327755 DramC Write-DBI off
7482 23:03:32.327836
7483 23:03:32.327901 [DATLAT]
7484 23:03:32.327962 Freq=1600, CH0 RK0
7485 23:03:32.328020
7486 23:03:32.330925 DATLAT Default: 0xf
7487 23:03:32.331006 0, 0xFFFF, sum = 0
7488 23:03:32.334123 1, 0xFFFF, sum = 0
7489 23:03:32.337139 2, 0xFFFF, sum = 0
7490 23:03:32.337221 3, 0xFFFF, sum = 0
7491 23:03:32.341009 4, 0xFFFF, sum = 0
7492 23:03:32.341091 5, 0xFFFF, sum = 0
7493 23:03:32.343968 6, 0xFFFF, sum = 0
7494 23:03:32.344064 7, 0xFFFF, sum = 0
7495 23:03:32.347477 8, 0xFFFF, sum = 0
7496 23:03:32.347560 9, 0xFFFF, sum = 0
7497 23:03:32.350497 10, 0xFFFF, sum = 0
7498 23:03:32.350579 11, 0xFFFF, sum = 0
7499 23:03:32.353840 12, 0xFFF, sum = 0
7500 23:03:32.353922 13, 0x0, sum = 1
7501 23:03:32.357112 14, 0x0, sum = 2
7502 23:03:32.357194 15, 0x0, sum = 3
7503 23:03:32.360459 16, 0x0, sum = 4
7504 23:03:32.360597 best_step = 14
7505 23:03:32.360662
7506 23:03:32.360722 ==
7507 23:03:32.363970 Dram Type= 6, Freq= 0, CH_0, rank 0
7508 23:03:32.367026 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7509 23:03:32.370639 ==
7510 23:03:32.370724 RX Vref Scan: 1
7511 23:03:32.370788
7512 23:03:32.373717 Set Vref Range= 24 -> 127
7513 23:03:32.373800
7514 23:03:32.377013 RX Vref 24 -> 127, step: 1
7515 23:03:32.377096
7516 23:03:32.377160 RX Delay 11 -> 252, step: 4
7517 23:03:32.377220
7518 23:03:32.380371 Set Vref, RX VrefLevel [Byte0]: 24
7519 23:03:32.383600 [Byte1]: 24
7520 23:03:32.387574
7521 23:03:32.387654 Set Vref, RX VrefLevel [Byte0]: 25
7522 23:03:32.391039 [Byte1]: 25
7523 23:03:32.395088
7524 23:03:32.395207 Set Vref, RX VrefLevel [Byte0]: 26
7525 23:03:32.401574 [Byte1]: 26
7526 23:03:32.401661
7527 23:03:32.404883 Set Vref, RX VrefLevel [Byte0]: 27
7528 23:03:32.407994 [Byte1]: 27
7529 23:03:32.408075
7530 23:03:32.411410 Set Vref, RX VrefLevel [Byte0]: 28
7531 23:03:32.414854 [Byte1]: 28
7532 23:03:32.414975
7533 23:03:32.417962 Set Vref, RX VrefLevel [Byte0]: 29
7534 23:03:32.421275 [Byte1]: 29
7535 23:03:32.425599
7536 23:03:32.425681 Set Vref, RX VrefLevel [Byte0]: 30
7537 23:03:32.428814 [Byte1]: 30
7538 23:03:32.432962
7539 23:03:32.433044 Set Vref, RX VrefLevel [Byte0]: 31
7540 23:03:32.436383 [Byte1]: 31
7541 23:03:32.440789
7542 23:03:32.440872 Set Vref, RX VrefLevel [Byte0]: 32
7543 23:03:32.444235 [Byte1]: 32
7544 23:03:32.448466
7545 23:03:32.448606 Set Vref, RX VrefLevel [Byte0]: 33
7546 23:03:32.451851 [Byte1]: 33
7547 23:03:32.456297
7548 23:03:32.456769 Set Vref, RX VrefLevel [Byte0]: 34
7549 23:03:32.459845 [Byte1]: 34
7550 23:03:32.463990
7551 23:03:32.464403 Set Vref, RX VrefLevel [Byte0]: 35
7552 23:03:32.467174 [Byte1]: 35
7553 23:03:32.471671
7554 23:03:32.472323 Set Vref, RX VrefLevel [Byte0]: 36
7555 23:03:32.474829 [Byte1]: 36
7556 23:03:32.479139
7557 23:03:32.479547 Set Vref, RX VrefLevel [Byte0]: 37
7558 23:03:32.482503 [Byte1]: 37
7559 23:03:32.486901
7560 23:03:32.487191 Set Vref, RX VrefLevel [Byte0]: 38
7561 23:03:32.489746 [Byte1]: 38
7562 23:03:32.494141
7563 23:03:32.494321 Set Vref, RX VrefLevel [Byte0]: 39
7564 23:03:32.497330 [Byte1]: 39
7565 23:03:32.501981
7566 23:03:32.502135 Set Vref, RX VrefLevel [Byte0]: 40
7567 23:03:32.504837 [Byte1]: 40
7568 23:03:32.509585
7569 23:03:32.509704 Set Vref, RX VrefLevel [Byte0]: 41
7570 23:03:32.512469 [Byte1]: 41
7571 23:03:32.516835
7572 23:03:32.516938 Set Vref, RX VrefLevel [Byte0]: 42
7573 23:03:32.520067 [Byte1]: 42
7574 23:03:32.524469
7575 23:03:32.524567 Set Vref, RX VrefLevel [Byte0]: 43
7576 23:03:32.527886 [Byte1]: 43
7577 23:03:32.531914
7578 23:03:32.531997 Set Vref, RX VrefLevel [Byte0]: 44
7579 23:03:32.535613 [Byte1]: 44
7580 23:03:32.539622
7581 23:03:32.539787 Set Vref, RX VrefLevel [Byte0]: 45
7582 23:03:32.543033 [Byte1]: 45
7583 23:03:32.547404
7584 23:03:32.547503 Set Vref, RX VrefLevel [Byte0]: 46
7585 23:03:32.550602 [Byte1]: 46
7586 23:03:32.554843
7587 23:03:32.554927 Set Vref, RX VrefLevel [Byte0]: 47
7588 23:03:32.558168 [Byte1]: 47
7589 23:03:32.562819
7590 23:03:32.562903 Set Vref, RX VrefLevel [Byte0]: 48
7591 23:03:32.565744 [Byte1]: 48
7592 23:03:32.570072
7593 23:03:32.570163 Set Vref, RX VrefLevel [Byte0]: 49
7594 23:03:32.573855 [Byte1]: 49
7595 23:03:32.577673
7596 23:03:32.577763 Set Vref, RX VrefLevel [Byte0]: 50
7597 23:03:32.581211 [Byte1]: 50
7598 23:03:32.585623
7599 23:03:32.585711 Set Vref, RX VrefLevel [Byte0]: 51
7600 23:03:32.588656 [Byte1]: 51
7601 23:03:32.592879
7602 23:03:32.593049 Set Vref, RX VrefLevel [Byte0]: 52
7603 23:03:32.596106 [Byte1]: 52
7604 23:03:32.600855
7605 23:03:32.600935 Set Vref, RX VrefLevel [Byte0]: 53
7606 23:03:32.604137 [Byte1]: 53
7607 23:03:32.608017
7608 23:03:32.608098 Set Vref, RX VrefLevel [Byte0]: 54
7609 23:03:32.611421 [Byte1]: 54
7610 23:03:32.615882
7611 23:03:32.615963 Set Vref, RX VrefLevel [Byte0]: 55
7612 23:03:32.619165 [Byte1]: 55
7613 23:03:32.623460
7614 23:03:32.623546 Set Vref, RX VrefLevel [Byte0]: 56
7615 23:03:32.626747 [Byte1]: 56
7616 23:03:32.631101
7617 23:03:32.631203 Set Vref, RX VrefLevel [Byte0]: 57
7618 23:03:32.634502 [Byte1]: 57
7619 23:03:32.638736
7620 23:03:32.638817 Set Vref, RX VrefLevel [Byte0]: 58
7621 23:03:32.642067 [Byte1]: 58
7622 23:03:32.646782
7623 23:03:32.647196 Set Vref, RX VrefLevel [Byte0]: 59
7624 23:03:32.649913 [Byte1]: 59
7625 23:03:32.654184
7626 23:03:32.654665 Set Vref, RX VrefLevel [Byte0]: 60
7627 23:03:32.657762 [Byte1]: 60
7628 23:03:32.661948
7629 23:03:32.662373 Set Vref, RX VrefLevel [Byte0]: 61
7630 23:03:32.665025 [Byte1]: 61
7631 23:03:32.669462
7632 23:03:32.669904 Set Vref, RX VrefLevel [Byte0]: 62
7633 23:03:32.672658 [Byte1]: 62
7634 23:03:32.677057
7635 23:03:32.677542 Set Vref, RX VrefLevel [Byte0]: 63
7636 23:03:32.680022 [Byte1]: 63
7637 23:03:32.684761
7638 23:03:32.685174 Set Vref, RX VrefLevel [Byte0]: 64
7639 23:03:32.688024 [Byte1]: 64
7640 23:03:32.692220
7641 23:03:32.692614 Set Vref, RX VrefLevel [Byte0]: 65
7642 23:03:32.698493 [Byte1]: 65
7643 23:03:32.698721
7644 23:03:32.702069 Set Vref, RX VrefLevel [Byte0]: 66
7645 23:03:32.704936 [Byte1]: 66
7646 23:03:32.705119
7647 23:03:32.708344 Set Vref, RX VrefLevel [Byte0]: 67
7648 23:03:32.711721 [Byte1]: 67
7649 23:03:32.714995
7650 23:03:32.715124 Set Vref, RX VrefLevel [Byte0]: 68
7651 23:03:32.718211 [Byte1]: 68
7652 23:03:32.722269
7653 23:03:32.722382 Set Vref, RX VrefLevel [Byte0]: 69
7654 23:03:32.725893 [Byte1]: 69
7655 23:03:32.729904
7656 23:03:32.730072 Set Vref, RX VrefLevel [Byte0]: 70
7657 23:03:32.733630 [Byte1]: 70
7658 23:03:32.737774
7659 23:03:32.737910 Set Vref, RX VrefLevel [Byte0]: 71
7660 23:03:32.740870 [Byte1]: 71
7661 23:03:32.745614
7662 23:03:32.745755 Set Vref, RX VrefLevel [Byte0]: 72
7663 23:03:32.748527 [Byte1]: 72
7664 23:03:32.752767
7665 23:03:32.752855 Final RX Vref Byte 0 = 53 to rank0
7666 23:03:32.756218 Final RX Vref Byte 1 = 56 to rank0
7667 23:03:32.759350 Final RX Vref Byte 0 = 53 to rank1
7668 23:03:32.762719 Final RX Vref Byte 1 = 56 to rank1==
7669 23:03:32.765946 Dram Type= 6, Freq= 0, CH_0, rank 0
7670 23:03:32.772867 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7671 23:03:32.773058 ==
7672 23:03:32.773221 DQS Delay:
7673 23:03:32.773366 DQS0 = 0, DQS1 = 0
7674 23:03:32.776087 DQM Delay:
7675 23:03:32.776187 DQM0 = 126, DQM1 = 121
7676 23:03:32.779664 DQ Delay:
7677 23:03:32.783136 DQ0 =122, DQ1 =128, DQ2 =124, DQ3 =122
7678 23:03:32.786285 DQ4 =130, DQ5 =116, DQ6 =138, DQ7 =134
7679 23:03:32.789426 DQ8 =112, DQ9 =104, DQ10 =120, DQ11 =112
7680 23:03:32.792977 DQ12 =126, DQ13 =126, DQ14 =136, DQ15 =134
7681 23:03:32.793182
7682 23:03:32.793293
7683 23:03:32.793391
7684 23:03:32.796523 [DramC_TX_OE_Calibration] TA2
7685 23:03:32.799640 Original DQ_B0 (3 6) =30, OEN = 27
7686 23:03:32.802728 Original DQ_B1 (3 6) =30, OEN = 27
7687 23:03:32.805949 24, 0x0, End_B0=24 End_B1=24
7688 23:03:32.806192 25, 0x0, End_B0=25 End_B1=25
7689 23:03:32.809642 26, 0x0, End_B0=26 End_B1=26
7690 23:03:32.812851 27, 0x0, End_B0=27 End_B1=27
7691 23:03:32.816436 28, 0x0, End_B0=28 End_B1=28
7692 23:03:32.819810 29, 0x0, End_B0=29 End_B1=29
7693 23:03:32.820238 30, 0x0, End_B0=30 End_B1=30
7694 23:03:32.822651 31, 0x4141, End_B0=30 End_B1=30
7695 23:03:32.826189 Byte0 end_step=30 best_step=27
7696 23:03:32.829633 Byte1 end_step=30 best_step=27
7697 23:03:32.832642 Byte0 TX OE(2T, 0.5T) = (3, 3)
7698 23:03:32.836031 Byte1 TX OE(2T, 0.5T) = (3, 3)
7699 23:03:32.836603
7700 23:03:32.836971
7701 23:03:32.842763 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a1a, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
7702 23:03:32.846144 CH0 RK0: MR19=303, MR18=1A1A
7703 23:03:32.852897 CH0_RK0: MR19=0x303, MR18=0x1A1A, DQSOSC=396, MR23=63, INC=23, DEC=15
7704 23:03:32.853458
7705 23:03:32.856010 ----->DramcWriteLeveling(PI) begin...
7706 23:03:32.856473 ==
7707 23:03:32.859070 Dram Type= 6, Freq= 0, CH_0, rank 1
7708 23:03:32.862692 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7709 23:03:32.863250 ==
7710 23:03:32.865808 Write leveling (Byte 0): 30 => 30
7711 23:03:32.869746 Write leveling (Byte 1): 26 => 26
7712 23:03:32.872695 DramcWriteLeveling(PI) end<-----
7713 23:03:32.873440
7714 23:03:32.874054 ==
7715 23:03:32.875816 Dram Type= 6, Freq= 0, CH_0, rank 1
7716 23:03:32.879143 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7717 23:03:32.879604 ==
7718 23:03:32.882549 [Gating] SW mode calibration
7719 23:03:32.888991 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7720 23:03:32.895866 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7721 23:03:32.899306 0 12 0 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
7722 23:03:32.905777 0 12 4 | B1->B0 | 2424 3434 | 1 1 | (0 0) (1 1)
7723 23:03:32.908941 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7724 23:03:32.912081 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7725 23:03:32.918953 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7726 23:03:32.922691 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7727 23:03:32.925360 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7728 23:03:32.928888 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7729 23:03:32.935569 0 13 0 | B1->B0 | 3434 2b2b | 1 0 | (1 0) (1 0)
7730 23:03:32.938952 0 13 4 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
7731 23:03:32.942117 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7732 23:03:32.948722 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7733 23:03:32.952290 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7734 23:03:32.955407 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7735 23:03:32.961981 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7736 23:03:32.965492 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7737 23:03:32.968798 0 14 0 | B1->B0 | 2525 4343 | 0 0 | (0 0) (0 0)
7738 23:03:32.975813 0 14 4 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
7739 23:03:32.978974 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7740 23:03:32.981842 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7741 23:03:32.989002 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7742 23:03:32.991682 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7743 23:03:32.995485 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7744 23:03:33.001652 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7745 23:03:33.005502 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7746 23:03:33.008467 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7747 23:03:33.015321 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7748 23:03:33.019060 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7749 23:03:33.021923 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7750 23:03:33.028809 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7751 23:03:33.031964 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7752 23:03:33.035089 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7753 23:03:33.041982 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7754 23:03:33.045287 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7755 23:03:33.048697 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7756 23:03:33.055369 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7757 23:03:33.058505 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7758 23:03:33.061913 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7759 23:03:33.065167 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7760 23:03:33.071565 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7761 23:03:33.074943 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7762 23:03:33.078596 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7763 23:03:33.082052 Total UI for P1: 0, mck2ui 16
7764 23:03:33.084906 best dqsien dly found for B0: ( 1, 0, 28)
7765 23:03:33.091840 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7766 23:03:33.095385 Total UI for P1: 0, mck2ui 16
7767 23:03:33.098583 best dqsien dly found for B1: ( 1, 1, 2)
7768 23:03:33.101795 best DQS0 dly(MCK, UI, PI) = (1, 0, 28)
7769 23:03:33.105059 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
7770 23:03:33.105594
7771 23:03:33.108477 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 28)
7772 23:03:33.111687 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
7773 23:03:33.115113 [Gating] SW calibration Done
7774 23:03:33.115649 ==
7775 23:03:33.118599 Dram Type= 6, Freq= 0, CH_0, rank 1
7776 23:03:33.121859 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7777 23:03:33.122421 ==
7778 23:03:33.125151 RX Vref Scan: 0
7779 23:03:33.125704
7780 23:03:33.126074 RX Vref 0 -> 0, step: 1
7781 23:03:33.126412
7782 23:03:33.128183 RX Delay 0 -> 252, step: 8
7783 23:03:33.131666 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7784 23:03:33.138436 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7785 23:03:33.141488 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7786 23:03:33.145140 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7787 23:03:33.148053 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
7788 23:03:33.151505 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7789 23:03:33.158666 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7790 23:03:33.161728 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
7791 23:03:33.164899 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7792 23:03:33.168032 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7793 23:03:33.171684 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7794 23:03:33.178525 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7795 23:03:33.182138 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7796 23:03:33.184894 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7797 23:03:33.188635 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7798 23:03:33.191713 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7799 23:03:33.194890 ==
7800 23:03:33.198400 Dram Type= 6, Freq= 0, CH_0, rank 1
7801 23:03:33.201468 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7802 23:03:33.202020 ==
7803 23:03:33.202387 DQS Delay:
7804 23:03:33.205045 DQS0 = 0, DQS1 = 0
7805 23:03:33.205597 DQM Delay:
7806 23:03:33.208409 DQM0 = 131, DQM1 = 124
7807 23:03:33.209013 DQ Delay:
7808 23:03:33.211646 DQ0 =127, DQ1 =135, DQ2 =131, DQ3 =127
7809 23:03:33.215106 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =143
7810 23:03:33.218247 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =119
7811 23:03:33.221412 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =131
7812 23:03:33.222010
7813 23:03:33.222378
7814 23:03:33.222739 ==
7815 23:03:33.224651 Dram Type= 6, Freq= 0, CH_0, rank 1
7816 23:03:33.231462 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7817 23:03:33.232069 ==
7818 23:03:33.232448
7819 23:03:33.232924
7820 23:03:33.233262 TX Vref Scan disable
7821 23:03:33.235379 == TX Byte 0 ==
7822 23:03:33.238871 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7823 23:03:33.244621 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7824 23:03:33.245081 == TX Byte 1 ==
7825 23:03:33.248083 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7826 23:03:33.255122 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7827 23:03:33.255675 ==
7828 23:03:33.258201 Dram Type= 6, Freq= 0, CH_0, rank 1
7829 23:03:33.261317 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7830 23:03:33.261782 ==
7831 23:03:33.274267
7832 23:03:33.277766 TX Vref early break, caculate TX vref
7833 23:03:33.280701 TX Vref=16, minBit 1, minWin=22, winSum=374
7834 23:03:33.283823 TX Vref=18, minBit 1, minWin=23, winSum=380
7835 23:03:33.287156 TX Vref=20, minBit 11, minWin=23, winSum=393
7836 23:03:33.290629 TX Vref=22, minBit 1, minWin=24, winSum=398
7837 23:03:33.296973 TX Vref=24, minBit 8, minWin=24, winSum=403
7838 23:03:33.300042 TX Vref=26, minBit 8, minWin=24, winSum=410
7839 23:03:33.303547 TX Vref=28, minBit 1, minWin=24, winSum=415
7840 23:03:33.307109 TX Vref=30, minBit 8, minWin=24, winSum=409
7841 23:03:33.310216 TX Vref=32, minBit 3, minWin=24, winSum=400
7842 23:03:33.313614 TX Vref=34, minBit 8, minWin=23, winSum=393
7843 23:03:33.319880 [TxChooseVref] Worse bit 1, Min win 24, Win sum 415, Final Vref 28
7844 23:03:33.320344
7845 23:03:33.323431 Final TX Range 0 Vref 28
7846 23:03:33.323981
7847 23:03:33.324343 ==
7848 23:03:33.326720 Dram Type= 6, Freq= 0, CH_0, rank 1
7849 23:03:33.330113 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7850 23:03:33.330676 ==
7851 23:03:33.331208
7852 23:03:33.331586
7853 23:03:33.333227 TX Vref Scan disable
7854 23:03:33.340009 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7855 23:03:33.340637 == TX Byte 0 ==
7856 23:03:33.343632 u2DelayCellOfst[0]=10 cells (3 PI)
7857 23:03:33.346803 u2DelayCellOfst[1]=14 cells (4 PI)
7858 23:03:33.349749 u2DelayCellOfst[2]=10 cells (3 PI)
7859 23:03:33.353416 u2DelayCellOfst[3]=10 cells (3 PI)
7860 23:03:33.356409 u2DelayCellOfst[4]=7 cells (2 PI)
7861 23:03:33.359697 u2DelayCellOfst[5]=0 cells (0 PI)
7862 23:03:33.362925 u2DelayCellOfst[6]=18 cells (5 PI)
7863 23:03:33.366742 u2DelayCellOfst[7]=14 cells (4 PI)
7864 23:03:33.369644 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7865 23:03:33.372997 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7866 23:03:33.376675 == TX Byte 1 ==
7867 23:03:33.379548 u2DelayCellOfst[8]=0 cells (0 PI)
7868 23:03:33.383062 u2DelayCellOfst[9]=0 cells (0 PI)
7869 23:03:33.386061 u2DelayCellOfst[10]=10 cells (3 PI)
7870 23:03:33.386535 u2DelayCellOfst[11]=3 cells (1 PI)
7871 23:03:33.389956 u2DelayCellOfst[12]=10 cells (3 PI)
7872 23:03:33.392761 u2DelayCellOfst[13]=14 cells (4 PI)
7873 23:03:33.396007 u2DelayCellOfst[14]=18 cells (5 PI)
7874 23:03:33.399318 u2DelayCellOfst[15]=14 cells (4 PI)
7875 23:03:33.405824 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
7876 23:03:33.409370 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7877 23:03:33.409979 DramC Write-DBI on
7878 23:03:33.413020 ==
7879 23:03:33.413477 Dram Type= 6, Freq= 0, CH_0, rank 1
7880 23:03:33.419799 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7881 23:03:33.420374 ==
7882 23:03:33.420817
7883 23:03:33.421166
7884 23:03:33.422256 TX Vref Scan disable
7885 23:03:33.422715 == TX Byte 0 ==
7886 23:03:33.429315 Update DQM dly =729 (2 ,6, 25) DQM OEN =(3 ,3)
7887 23:03:33.430071 == TX Byte 1 ==
7888 23:03:33.432431 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
7889 23:03:33.436141 DramC Write-DBI off
7890 23:03:33.436763
7891 23:03:33.437141 [DATLAT]
7892 23:03:33.439151 Freq=1600, CH0 RK1
7893 23:03:33.439724
7894 23:03:33.440096 DATLAT Default: 0xe
7895 23:03:33.442480 0, 0xFFFF, sum = 0
7896 23:03:33.442947 1, 0xFFFF, sum = 0
7897 23:03:33.445508 2, 0xFFFF, sum = 0
7898 23:03:33.446025 3, 0xFFFF, sum = 0
7899 23:03:33.448860 4, 0xFFFF, sum = 0
7900 23:03:33.449378 5, 0xFFFF, sum = 0
7901 23:03:33.452325 6, 0xFFFF, sum = 0
7902 23:03:33.452844 7, 0xFFFF, sum = 0
7903 23:03:33.455704 8, 0xFFFF, sum = 0
7904 23:03:33.458757 9, 0xFFFF, sum = 0
7905 23:03:33.459314 10, 0xFFFF, sum = 0
7906 23:03:33.462267 11, 0xFFFF, sum = 0
7907 23:03:33.462783 12, 0x8FFF, sum = 0
7908 23:03:33.465288 13, 0x0, sum = 1
7909 23:03:33.465853 14, 0x0, sum = 2
7910 23:03:33.468806 15, 0x0, sum = 3
7911 23:03:33.469299 16, 0x0, sum = 4
7912 23:03:33.469766 best_step = 14
7913 23:03:33.472003
7914 23:03:33.472459 ==
7915 23:03:33.475431 Dram Type= 6, Freq= 0, CH_0, rank 1
7916 23:03:33.478597 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7917 23:03:33.479058 ==
7918 23:03:33.479427 RX Vref Scan: 0
7919 23:03:33.479769
7920 23:03:33.481882 RX Vref 0 -> 0, step: 1
7921 23:03:33.482337
7922 23:03:33.485259 RX Delay 11 -> 252, step: 4
7923 23:03:33.488217 iDelay=195, Bit 0, Center 124 (71 ~ 178) 108
7924 23:03:33.495130 iDelay=195, Bit 1, Center 132 (79 ~ 186) 108
7925 23:03:33.498396 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
7926 23:03:33.501521 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
7927 23:03:33.505017 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
7928 23:03:33.508396 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
7929 23:03:33.514897 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
7930 23:03:33.518864 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
7931 23:03:33.521409 iDelay=195, Bit 8, Center 108 (55 ~ 162) 108
7932 23:03:33.524914 iDelay=195, Bit 9, Center 108 (55 ~ 162) 108
7933 23:03:33.528336 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
7934 23:03:33.535108 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
7935 23:03:33.538097 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
7936 23:03:33.541506 iDelay=195, Bit 13, Center 126 (71 ~ 182) 112
7937 23:03:33.544765 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
7938 23:03:33.551155 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
7939 23:03:33.551675 ==
7940 23:03:33.554289 Dram Type= 6, Freq= 0, CH_0, rank 1
7941 23:03:33.557885 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7942 23:03:33.558406 ==
7943 23:03:33.558743 DQS Delay:
7944 23:03:33.561002 DQS0 = 0, DQS1 = 0
7945 23:03:33.561533 DQM Delay:
7946 23:03:33.564562 DQM0 = 129, DQM1 = 120
7947 23:03:33.565078 DQ Delay:
7948 23:03:33.567494 DQ0 =124, DQ1 =132, DQ2 =126, DQ3 =124
7949 23:03:33.571433 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =138
7950 23:03:33.574371 DQ8 =108, DQ9 =108, DQ10 =122, DQ11 =112
7951 23:03:33.577349 DQ12 =126, DQ13 =126, DQ14 =132, DQ15 =132
7952 23:03:33.577989
7953 23:03:33.578339
7954 23:03:33.580815
7955 23:03:33.581229 [DramC_TX_OE_Calibration] TA2
7956 23:03:33.584118 Original DQ_B0 (3 6) =30, OEN = 27
7957 23:03:33.587456 Original DQ_B1 (3 6) =30, OEN = 27
7958 23:03:33.590778 24, 0x0, End_B0=24 End_B1=24
7959 23:03:33.594445 25, 0x0, End_B0=25 End_B1=25
7960 23:03:33.597608 26, 0x0, End_B0=26 End_B1=26
7961 23:03:33.598042 27, 0x0, End_B0=27 End_B1=27
7962 23:03:33.600860 28, 0x0, End_B0=28 End_B1=28
7963 23:03:33.604313 29, 0x0, End_B0=29 End_B1=29
7964 23:03:33.607594 30, 0x0, End_B0=30 End_B1=30
7965 23:03:33.608134 31, 0x4545, End_B0=30 End_B1=30
7966 23:03:33.610836 Byte0 end_step=30 best_step=27
7967 23:03:33.613906 Byte1 end_step=30 best_step=27
7968 23:03:33.617119 Byte0 TX OE(2T, 0.5T) = (3, 3)
7969 23:03:33.620652 Byte1 TX OE(2T, 0.5T) = (3, 3)
7970 23:03:33.621161
7971 23:03:33.621490
7972 23:03:33.627455 [DQSOSCAuto] RK1, (LSB)MR18= 0x2323, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
7973 23:03:33.630530 CH0 RK1: MR19=303, MR18=2323
7974 23:03:33.637244 CH0_RK1: MR19=0x303, MR18=0x2323, DQSOSC=392, MR23=63, INC=24, DEC=16
7975 23:03:33.640562 [RxdqsGatingPostProcess] freq 1600
7976 23:03:33.647386 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
7977 23:03:33.650358 Pre-setting of DQS Precalculation
7978 23:03:33.653427 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7979 23:03:33.653948 ==
7980 23:03:33.656963 Dram Type= 6, Freq= 0, CH_1, rank 0
7981 23:03:33.660085 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7982 23:03:33.663453 ==
7983 23:03:33.666735 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7984 23:03:33.670024 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
7985 23:03:33.676842 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
7986 23:03:33.683402 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7987 23:03:33.689755 [CA 0] Center 40 (10~71) winsize 62
7988 23:03:33.693228 [CA 1] Center 40 (10~71) winsize 62
7989 23:03:33.696239 [CA 2] Center 36 (6~66) winsize 61
7990 23:03:33.699724 [CA 3] Center 35 (6~65) winsize 60
7991 23:03:33.703155 [CA 4] Center 33 (3~63) winsize 61
7992 23:03:33.706321 [CA 5] Center 33 (4~63) winsize 60
7993 23:03:33.706882
7994 23:03:33.709430 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7995 23:03:33.710136
7996 23:03:33.712546 [CATrainingPosCal] consider 1 rank data
7997 23:03:33.716286 u2DelayCellTimex100 = 271/100 ps
7998 23:03:33.722977 CA0 delay=40 (10~71),Diff = 7 PI (25 cell)
7999 23:03:33.726125 CA1 delay=40 (10~71),Diff = 7 PI (25 cell)
8000 23:03:33.729393 CA2 delay=36 (6~66),Diff = 3 PI (10 cell)
8001 23:03:33.732553 CA3 delay=35 (6~65),Diff = 2 PI (7 cell)
8002 23:03:33.736409 CA4 delay=33 (3~63),Diff = 0 PI (0 cell)
8003 23:03:33.739449 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
8004 23:03:33.740005
8005 23:03:33.742446 CA PerBit enable=1, Macro0, CA PI delay=33
8006 23:03:33.742906
8007 23:03:33.745944 [CBTSetCACLKResult] CA Dly = 33
8008 23:03:33.749151 CS Dly: 8 (0~39)
8009 23:03:33.752651 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8010 23:03:33.755403 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8011 23:03:33.755865 ==
8012 23:03:33.758906 Dram Type= 6, Freq= 0, CH_1, rank 1
8013 23:03:33.765728 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8014 23:03:33.766191 ==
8015 23:03:33.768825 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8016 23:03:33.772320 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8017 23:03:33.778806 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8018 23:03:33.785456 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8019 23:03:33.792308 [CA 0] Center 41 (11~71) winsize 61
8020 23:03:33.795342 [CA 1] Center 41 (11~71) winsize 61
8021 23:03:33.798784 [CA 2] Center 36 (7~66) winsize 60
8022 23:03:33.801816 [CA 3] Center 36 (7~65) winsize 59
8023 23:03:33.805369 [CA 4] Center 34 (5~64) winsize 60
8024 23:03:33.808495 [CA 5] Center 34 (4~64) winsize 61
8025 23:03:33.809071
8026 23:03:33.811963 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8027 23:03:33.812556
8028 23:03:33.815390 [CATrainingPosCal] consider 2 rank data
8029 23:03:33.818253 u2DelayCellTimex100 = 271/100 ps
8030 23:03:33.824963 CA0 delay=41 (11~71),Diff = 8 PI (28 cell)
8031 23:03:33.828339 CA1 delay=41 (11~71),Diff = 8 PI (28 cell)
8032 23:03:33.831994 CA2 delay=36 (7~66),Diff = 3 PI (10 cell)
8033 23:03:33.834847 CA3 delay=36 (7~65),Diff = 3 PI (10 cell)
8034 23:03:33.838367 CA4 delay=34 (5~63),Diff = 1 PI (3 cell)
8035 23:03:33.841526 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
8036 23:03:33.841988
8037 23:03:33.844816 CA PerBit enable=1, Macro0, CA PI delay=33
8038 23:03:33.845281
8039 23:03:33.848386 [CBTSetCACLKResult] CA Dly = 33
8040 23:03:33.851525 CS Dly: 8 (0~40)
8041 23:03:33.854784 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8042 23:03:33.858257 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8043 23:03:33.858722
8044 23:03:33.861326 ----->DramcWriteLeveling(PI) begin...
8045 23:03:33.861849 ==
8046 23:03:33.864502 Dram Type= 6, Freq= 0, CH_1, rank 0
8047 23:03:33.871089 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8048 23:03:33.871559 ==
8049 23:03:33.874824 Write leveling (Byte 0): 23 => 23
8050 23:03:33.877772 Write leveling (Byte 1): 23 => 23
8051 23:03:33.878312 DramcWriteLeveling(PI) end<-----
8052 23:03:33.878690
8053 23:03:33.881062 ==
8054 23:03:33.884423 Dram Type= 6, Freq= 0, CH_1, rank 0
8055 23:03:33.887716 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8056 23:03:33.888251 ==
8057 23:03:33.891324 [Gating] SW mode calibration
8058 23:03:33.897469 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8059 23:03:33.900885 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8060 23:03:33.907493 0 12 0 | B1->B0 | 2726 3434 | 1 1 | (1 1) (1 1)
8061 23:03:33.911196 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8062 23:03:33.914180 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8063 23:03:33.921172 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8064 23:03:33.924266 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8065 23:03:33.927506 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8066 23:03:33.934099 0 12 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8067 23:03:33.937337 0 12 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
8068 23:03:33.941014 0 13 0 | B1->B0 | 2f2f 2323 | 0 0 | (1 0) (0 0)
8069 23:03:33.947581 0 13 4 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
8070 23:03:33.950364 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8071 23:03:33.954113 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8072 23:03:33.960675 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8073 23:03:33.963737 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8074 23:03:33.967053 0 13 24 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
8075 23:03:33.973874 0 13 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8076 23:03:33.976832 0 14 0 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
8077 23:03:33.980146 0 14 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8078 23:03:33.986993 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8079 23:03:33.990533 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8080 23:03:33.993560 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8081 23:03:33.999994 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8082 23:03:34.003456 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8083 23:03:34.006821 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8084 23:03:34.013329 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8085 23:03:34.016472 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8086 23:03:34.019759 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8087 23:03:34.026512 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8088 23:03:34.029948 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8089 23:03:34.033312 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8090 23:03:34.039967 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8091 23:03:34.043220 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8092 23:03:34.046620 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8093 23:03:34.052799 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8094 23:03:34.056242 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8095 23:03:34.059715 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8096 23:03:34.066406 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8097 23:03:34.069317 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8098 23:03:34.073039 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8099 23:03:34.079225 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8100 23:03:34.082438 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8101 23:03:34.086206 Total UI for P1: 0, mck2ui 16
8102 23:03:34.089173 best dqsien dly found for B0: ( 1, 0, 28)
8103 23:03:34.092589 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8104 23:03:34.099261 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8105 23:03:34.099818 Total UI for P1: 0, mck2ui 16
8106 23:03:34.105688 best dqsien dly found for B1: ( 1, 1, 2)
8107 23:03:34.109314 best DQS0 dly(MCK, UI, PI) = (1, 0, 28)
8108 23:03:34.112606 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
8109 23:03:34.113171
8110 23:03:34.115965 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 28)
8111 23:03:34.119370 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
8112 23:03:34.122554 [Gating] SW calibration Done
8113 23:03:34.123108 ==
8114 23:03:34.125788 Dram Type= 6, Freq= 0, CH_1, rank 0
8115 23:03:34.129257 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8116 23:03:34.129719 ==
8117 23:03:34.132472 RX Vref Scan: 0
8118 23:03:34.133070
8119 23:03:34.133442 RX Vref 0 -> 0, step: 1
8120 23:03:34.133782
8121 23:03:34.135845 RX Delay 0 -> 252, step: 8
8122 23:03:34.138764 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8123 23:03:34.145608 iDelay=200, Bit 1, Center 123 (72 ~ 175) 104
8124 23:03:34.148970 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8125 23:03:34.152351 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8126 23:03:34.155332 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8127 23:03:34.158825 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8128 23:03:34.165193 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8129 23:03:34.168876 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8130 23:03:34.172137 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8131 23:03:34.175545 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8132 23:03:34.178461 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8133 23:03:34.185592 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8134 23:03:34.188588 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8135 23:03:34.192114 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8136 23:03:34.195293 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8137 23:03:34.198673 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8138 23:03:34.201705 ==
8139 23:03:34.205087 Dram Type= 6, Freq= 0, CH_1, rank 0
8140 23:03:34.208288 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8141 23:03:34.208902 ==
8142 23:03:34.209400 DQS Delay:
8143 23:03:34.211570 DQS0 = 0, DQS1 = 0
8144 23:03:34.212031 DQM Delay:
8145 23:03:34.215234 DQM0 = 129, DQM1 = 125
8146 23:03:34.215789 DQ Delay:
8147 23:03:34.218239 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =127
8148 23:03:34.221446 DQ4 =127, DQ5 =143, DQ6 =135, DQ7 =127
8149 23:03:34.224880 DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =115
8150 23:03:34.228283 DQ12 =131, DQ13 =139, DQ14 =131, DQ15 =135
8151 23:03:34.228905
8152 23:03:34.229276
8153 23:03:34.231621 ==
8154 23:03:34.234499 Dram Type= 6, Freq= 0, CH_1, rank 0
8155 23:03:34.238256 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8156 23:03:34.238828 ==
8157 23:03:34.239253
8158 23:03:34.239629
8159 23:03:34.241089 TX Vref Scan disable
8160 23:03:34.241552 == TX Byte 0 ==
8161 23:03:34.244336 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8162 23:03:34.251100 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8163 23:03:34.251647 == TX Byte 1 ==
8164 23:03:34.254392 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8165 23:03:34.261055 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8166 23:03:34.261598 ==
8167 23:03:34.264342 Dram Type= 6, Freq= 0, CH_1, rank 0
8168 23:03:34.267604 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8169 23:03:34.268188 ==
8170 23:03:34.280273
8171 23:03:34.283354 TX Vref early break, caculate TX vref
8172 23:03:34.287241 TX Vref=16, minBit 0, minWin=22, winSum=367
8173 23:03:34.290508 TX Vref=18, minBit 0, minWin=23, winSum=375
8174 23:03:34.293572 TX Vref=20, minBit 0, minWin=23, winSum=381
8175 23:03:34.296636 TX Vref=22, minBit 0, minWin=24, winSum=391
8176 23:03:34.300551 TX Vref=24, minBit 3, minWin=23, winSum=400
8177 23:03:34.306477 TX Vref=26, minBit 3, minWin=24, winSum=409
8178 23:03:34.309904 TX Vref=28, minBit 0, minWin=25, winSum=412
8179 23:03:34.313246 TX Vref=30, minBit 9, minWin=24, winSum=405
8180 23:03:34.316403 TX Vref=32, minBit 3, minWin=23, winSum=398
8181 23:03:34.319641 TX Vref=34, minBit 1, minWin=23, winSum=383
8182 23:03:34.326653 [TxChooseVref] Worse bit 0, Min win 25, Win sum 412, Final Vref 28
8183 23:03:34.327220
8184 23:03:34.330222 Final TX Range 0 Vref 28
8185 23:03:34.330924
8186 23:03:34.331349 ==
8187 23:03:34.333106 Dram Type= 6, Freq= 0, CH_1, rank 0
8188 23:03:34.336695 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8189 23:03:34.337202 ==
8190 23:03:34.337567
8191 23:03:34.337910
8192 23:03:34.339735 TX Vref Scan disable
8193 23:03:34.346814 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8194 23:03:34.347379 == TX Byte 0 ==
8195 23:03:34.349745 u2DelayCellOfst[0]=14 cells (4 PI)
8196 23:03:34.353300 u2DelayCellOfst[1]=10 cells (3 PI)
8197 23:03:34.356367 u2DelayCellOfst[2]=0 cells (0 PI)
8198 23:03:34.359788 u2DelayCellOfst[3]=7 cells (2 PI)
8199 23:03:34.363563 u2DelayCellOfst[4]=7 cells (2 PI)
8200 23:03:34.366737 u2DelayCellOfst[5]=14 cells (4 PI)
8201 23:03:34.369829 u2DelayCellOfst[6]=18 cells (5 PI)
8202 23:03:34.370297 u2DelayCellOfst[7]=7 cells (2 PI)
8203 23:03:34.376448 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8204 23:03:34.379821 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8205 23:03:34.380281 == TX Byte 1 ==
8206 23:03:34.382941 u2DelayCellOfst[8]=0 cells (0 PI)
8207 23:03:34.386402 u2DelayCellOfst[9]=7 cells (2 PI)
8208 23:03:34.389803 u2DelayCellOfst[10]=10 cells (3 PI)
8209 23:03:34.393229 u2DelayCellOfst[11]=3 cells (1 PI)
8210 23:03:34.396460 u2DelayCellOfst[12]=18 cells (5 PI)
8211 23:03:34.399881 u2DelayCellOfst[13]=21 cells (6 PI)
8212 23:03:34.403245 u2DelayCellOfst[14]=21 cells (6 PI)
8213 23:03:34.406191 u2DelayCellOfst[15]=21 cells (6 PI)
8214 23:03:34.409632 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8215 23:03:34.416406 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8216 23:03:34.416978 DramC Write-DBI on
8217 23:03:34.417317 ==
8218 23:03:34.420032 Dram Type= 6, Freq= 0, CH_1, rank 0
8219 23:03:34.423182 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8220 23:03:34.423707 ==
8221 23:03:34.426261
8222 23:03:34.426700
8223 23:03:34.427034 TX Vref Scan disable
8224 23:03:34.429472 == TX Byte 0 ==
8225 23:03:34.432873 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
8226 23:03:34.435901 == TX Byte 1 ==
8227 23:03:34.439571 Update DQM dly =717 (2 ,6, 13) DQM OEN =(3 ,3)
8228 23:03:34.440109 DramC Write-DBI off
8229 23:03:34.442846
8230 23:03:34.443392 [DATLAT]
8231 23:03:34.443737 Freq=1600, CH1 RK0
8232 23:03:34.444053
8233 23:03:34.445956 DATLAT Default: 0xf
8234 23:03:34.446403 0, 0xFFFF, sum = 0
8235 23:03:34.449352 1, 0xFFFF, sum = 0
8236 23:03:34.449778 2, 0xFFFF, sum = 0
8237 23:03:34.452677 3, 0xFFFF, sum = 0
8238 23:03:34.456073 4, 0xFFFF, sum = 0
8239 23:03:34.456705 5, 0xFFFF, sum = 0
8240 23:03:34.459202 6, 0xFFFF, sum = 0
8241 23:03:34.459728 7, 0xFFFF, sum = 0
8242 23:03:34.462285 8, 0xFFFF, sum = 0
8243 23:03:34.462707 9, 0xFFFF, sum = 0
8244 23:03:34.465960 10, 0xFFFF, sum = 0
8245 23:03:34.466439 11, 0xFFFF, sum = 0
8246 23:03:34.469110 12, 0xF7F, sum = 0
8247 23:03:34.469575 13, 0x0, sum = 1
8248 23:03:34.472224 14, 0x0, sum = 2
8249 23:03:34.472766 15, 0x0, sum = 3
8250 23:03:34.476077 16, 0x0, sum = 4
8251 23:03:34.476645 best_step = 14
8252 23:03:34.476992
8253 23:03:34.477306 ==
8254 23:03:34.478943 Dram Type= 6, Freq= 0, CH_1, rank 0
8255 23:03:34.482293 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8256 23:03:34.485638 ==
8257 23:03:34.486117 RX Vref Scan: 1
8258 23:03:34.486454
8259 23:03:34.488791 Set Vref Range= 24 -> 127
8260 23:03:34.489210
8261 23:03:34.492339 RX Vref 24 -> 127, step: 1
8262 23:03:34.492852
8263 23:03:34.493197 RX Delay 11 -> 252, step: 4
8264 23:03:34.493515
8265 23:03:34.495447 Set Vref, RX VrefLevel [Byte0]: 24
8266 23:03:34.499156 [Byte1]: 24
8267 23:03:34.502731
8268 23:03:34.503248 Set Vref, RX VrefLevel [Byte0]: 25
8269 23:03:34.505845 [Byte1]: 25
8270 23:03:34.510564
8271 23:03:34.511094 Set Vref, RX VrefLevel [Byte0]: 26
8272 23:03:34.513956 [Byte1]: 26
8273 23:03:34.517879
8274 23:03:34.518401 Set Vref, RX VrefLevel [Byte0]: 27
8275 23:03:34.520992 [Byte1]: 27
8276 23:03:34.525582
8277 23:03:34.525997 Set Vref, RX VrefLevel [Byte0]: 28
8278 23:03:34.528613 [Byte1]: 28
8279 23:03:34.532994
8280 23:03:34.533634 Set Vref, RX VrefLevel [Byte0]: 29
8281 23:03:34.536646 [Byte1]: 29
8282 23:03:34.540488
8283 23:03:34.541076 Set Vref, RX VrefLevel [Byte0]: 30
8284 23:03:34.543895 [Byte1]: 30
8285 23:03:34.548223
8286 23:03:34.548680 Set Vref, RX VrefLevel [Byte0]: 31
8287 23:03:34.551559 [Byte1]: 31
8288 23:03:34.555768
8289 23:03:34.556214 Set Vref, RX VrefLevel [Byte0]: 32
8290 23:03:34.558974 [Byte1]: 32
8291 23:03:34.563253
8292 23:03:34.563760 Set Vref, RX VrefLevel [Byte0]: 33
8293 23:03:34.566743 [Byte1]: 33
8294 23:03:34.570841
8295 23:03:34.571257 Set Vref, RX VrefLevel [Byte0]: 34
8296 23:03:34.574273 [Byte1]: 34
8297 23:03:34.578756
8298 23:03:34.579167 Set Vref, RX VrefLevel [Byte0]: 35
8299 23:03:34.581937 [Byte1]: 35
8300 23:03:34.586322
8301 23:03:34.586731 Set Vref, RX VrefLevel [Byte0]: 36
8302 23:03:34.589653 [Byte1]: 36
8303 23:03:34.594118
8304 23:03:34.594623 Set Vref, RX VrefLevel [Byte0]: 37
8305 23:03:34.597101 [Byte1]: 37
8306 23:03:34.601455
8307 23:03:34.601954 Set Vref, RX VrefLevel [Byte0]: 38
8308 23:03:34.604680 [Byte1]: 38
8309 23:03:34.609015
8310 23:03:34.609424 Set Vref, RX VrefLevel [Byte0]: 39
8311 23:03:34.612663 [Byte1]: 39
8312 23:03:34.616633
8313 23:03:34.617047 Set Vref, RX VrefLevel [Byte0]: 40
8314 23:03:34.620052 [Byte1]: 40
8315 23:03:34.624765
8316 23:03:34.625327 Set Vref, RX VrefLevel [Byte0]: 41
8317 23:03:34.628061 [Byte1]: 41
8318 23:03:34.632279
8319 23:03:34.632855 Set Vref, RX VrefLevel [Byte0]: 42
8320 23:03:34.635405 [Byte1]: 42
8321 23:03:34.639758
8322 23:03:34.640318 Set Vref, RX VrefLevel [Byte0]: 43
8323 23:03:34.643063 [Byte1]: 43
8324 23:03:34.647458
8325 23:03:34.648034 Set Vref, RX VrefLevel [Byte0]: 44
8326 23:03:34.650374 [Byte1]: 44
8327 23:03:34.654929
8328 23:03:34.655469 Set Vref, RX VrefLevel [Byte0]: 45
8329 23:03:34.658554 [Byte1]: 45
8330 23:03:34.662534
8331 23:03:34.662993 Set Vref, RX VrefLevel [Byte0]: 46
8332 23:03:34.665569 [Byte1]: 46
8333 23:03:34.670153
8334 23:03:34.670616 Set Vref, RX VrefLevel [Byte0]: 47
8335 23:03:34.673223 [Byte1]: 47
8336 23:03:34.677878
8337 23:03:34.678340 Set Vref, RX VrefLevel [Byte0]: 48
8338 23:03:34.681062 [Byte1]: 48
8339 23:03:34.685525
8340 23:03:34.685991 Set Vref, RX VrefLevel [Byte0]: 49
8341 23:03:34.688616 [Byte1]: 49
8342 23:03:34.692900
8343 23:03:34.693433 Set Vref, RX VrefLevel [Byte0]: 50
8344 23:03:34.696018 [Byte1]: 50
8345 23:03:34.700694
8346 23:03:34.701223 Set Vref, RX VrefLevel [Byte0]: 51
8347 23:03:34.703809 [Byte1]: 51
8348 23:03:34.708242
8349 23:03:34.708840 Set Vref, RX VrefLevel [Byte0]: 52
8350 23:03:34.711467 [Byte1]: 52
8351 23:03:34.715634
8352 23:03:34.716187 Set Vref, RX VrefLevel [Byte0]: 53
8353 23:03:34.718892 [Byte1]: 53
8354 23:03:34.723426
8355 23:03:34.724192 Set Vref, RX VrefLevel [Byte0]: 54
8356 23:03:34.726494 [Byte1]: 54
8357 23:03:34.731246
8358 23:03:34.731849 Set Vref, RX VrefLevel [Byte0]: 55
8359 23:03:34.734244 [Byte1]: 55
8360 23:03:34.738839
8361 23:03:34.739410 Set Vref, RX VrefLevel [Byte0]: 56
8362 23:03:34.741717 [Byte1]: 56
8363 23:03:34.746629
8364 23:03:34.747185 Set Vref, RX VrefLevel [Byte0]: 57
8365 23:03:34.749207 [Byte1]: 57
8366 23:03:34.753641
8367 23:03:34.754195 Set Vref, RX VrefLevel [Byte0]: 58
8368 23:03:34.756960 [Byte1]: 58
8369 23:03:34.761370
8370 23:03:34.761921 Set Vref, RX VrefLevel [Byte0]: 59
8371 23:03:34.764893 [Byte1]: 59
8372 23:03:34.769000
8373 23:03:34.769467 Set Vref, RX VrefLevel [Byte0]: 60
8374 23:03:34.772404 [Byte1]: 60
8375 23:03:34.776824
8376 23:03:34.777352 Set Vref, RX VrefLevel [Byte0]: 61
8377 23:03:34.779791 [Byte1]: 61
8378 23:03:34.784098
8379 23:03:34.784605 Set Vref, RX VrefLevel [Byte0]: 62
8380 23:03:34.787388 [Byte1]: 62
8381 23:03:34.791885
8382 23:03:34.792654 Set Vref, RX VrefLevel [Byte0]: 63
8383 23:03:34.795261 [Byte1]: 63
8384 23:03:34.799272
8385 23:03:34.799830 Set Vref, RX VrefLevel [Byte0]: 64
8386 23:03:34.802503 [Byte1]: 64
8387 23:03:34.807098
8388 23:03:34.807564 Set Vref, RX VrefLevel [Byte0]: 65
8389 23:03:34.810752 [Byte1]: 65
8390 23:03:34.814728
8391 23:03:34.815190 Set Vref, RX VrefLevel [Byte0]: 66
8392 23:03:34.817907 [Byte1]: 66
8393 23:03:34.822559
8394 23:03:34.823108 Set Vref, RX VrefLevel [Byte0]: 67
8395 23:03:34.825647 [Byte1]: 67
8396 23:03:34.829790
8397 23:03:34.830249 Set Vref, RX VrefLevel [Byte0]: 68
8398 23:03:34.833148 [Byte1]: 68
8399 23:03:34.837410
8400 23:03:34.837936 Set Vref, RX VrefLevel [Byte0]: 69
8401 23:03:34.840987 [Byte1]: 69
8402 23:03:34.845169
8403 23:03:34.845730 Set Vref, RX VrefLevel [Byte0]: 70
8404 23:03:34.848363 [Byte1]: 70
8405 23:03:34.852744
8406 23:03:34.853266 Set Vref, RX VrefLevel [Byte0]: 71
8407 23:03:34.856220 [Byte1]: 71
8408 23:03:34.860578
8409 23:03:34.861133 Set Vref, RX VrefLevel [Byte0]: 72
8410 23:03:34.863976 [Byte1]: 72
8411 23:03:34.868008
8412 23:03:34.868603 Set Vref, RX VrefLevel [Byte0]: 73
8413 23:03:34.871187 [Byte1]: 73
8414 23:03:34.875791
8415 23:03:34.876346 Set Vref, RX VrefLevel [Byte0]: 74
8416 23:03:34.879053 [Byte1]: 74
8417 23:03:34.883487
8418 23:03:34.884070 Set Vref, RX VrefLevel [Byte0]: 75
8419 23:03:34.886635 [Byte1]: 75
8420 23:03:34.890840
8421 23:03:34.891493 Final RX Vref Byte 0 = 59 to rank0
8422 23:03:34.893876 Final RX Vref Byte 1 = 52 to rank0
8423 23:03:34.897249 Final RX Vref Byte 0 = 59 to rank1
8424 23:03:34.900860 Final RX Vref Byte 1 = 52 to rank1==
8425 23:03:34.903885 Dram Type= 6, Freq= 0, CH_1, rank 0
8426 23:03:34.910774 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8427 23:03:34.911316 ==
8428 23:03:34.911689 DQS Delay:
8429 23:03:34.914206 DQS0 = 0, DQS1 = 0
8430 23:03:34.914756 DQM Delay:
8431 23:03:34.915133 DQM0 = 128, DQM1 = 122
8432 23:03:34.917344 DQ Delay:
8433 23:03:34.920870 DQ0 =132, DQ1 =124, DQ2 =116, DQ3 =126
8434 23:03:34.923702 DQ4 =130, DQ5 =140, DQ6 =138, DQ7 =124
8435 23:03:34.927211 DQ8 =104, DQ9 =114, DQ10 =124, DQ11 =112
8436 23:03:34.930613 DQ12 =130, DQ13 =134, DQ14 =132, DQ15 =132
8437 23:03:34.931191
8438 23:03:34.931571
8439 23:03:34.931916
8440 23:03:34.933963 [DramC_TX_OE_Calibration] TA2
8441 23:03:34.937398 Original DQ_B0 (3 6) =30, OEN = 27
8442 23:03:34.940669 Original DQ_B1 (3 6) =30, OEN = 27
8443 23:03:34.943680 24, 0x0, End_B0=24 End_B1=24
8444 23:03:34.944151 25, 0x0, End_B0=25 End_B1=25
8445 23:03:34.947237 26, 0x0, End_B0=26 End_B1=26
8446 23:03:34.950662 27, 0x0, End_B0=27 End_B1=27
8447 23:03:34.953667 28, 0x0, End_B0=28 End_B1=28
8448 23:03:34.957224 29, 0x0, End_B0=29 End_B1=29
8449 23:03:34.957693 30, 0x0, End_B0=30 End_B1=30
8450 23:03:34.960368 31, 0x4141, End_B0=30 End_B1=30
8451 23:03:34.963566 Byte0 end_step=30 best_step=27
8452 23:03:34.966800 Byte1 end_step=30 best_step=27
8453 23:03:34.970234 Byte0 TX OE(2T, 0.5T) = (3, 3)
8454 23:03:34.973863 Byte1 TX OE(2T, 0.5T) = (3, 3)
8455 23:03:34.974325
8456 23:03:34.974685
8457 23:03:34.980210 [DQSOSCAuto] RK0, (LSB)MR18= 0x2626, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
8458 23:03:34.983894 CH1 RK0: MR19=303, MR18=2626
8459 23:03:34.990350 CH1_RK0: MR19=0x303, MR18=0x2626, DQSOSC=390, MR23=63, INC=24, DEC=16
8460 23:03:34.990816
8461 23:03:34.993361 ----->DramcWriteLeveling(PI) begin...
8462 23:03:34.993832 ==
8463 23:03:34.996797 Dram Type= 6, Freq= 0, CH_1, rank 1
8464 23:03:35.000223 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8465 23:03:35.000847 ==
8466 23:03:35.003841 Write leveling (Byte 0): 23 => 23
8467 23:03:35.006458 Write leveling (Byte 1): 23 => 23
8468 23:03:35.009840 DramcWriteLeveling(PI) end<-----
8469 23:03:35.010299
8470 23:03:35.010661 ==
8471 23:03:35.013104 Dram Type= 6, Freq= 0, CH_1, rank 1
8472 23:03:35.016664 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8473 23:03:35.017217 ==
8474 23:03:35.019876 [Gating] SW mode calibration
8475 23:03:35.026644 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8476 23:03:35.033353 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8477 23:03:35.036645 0 12 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
8478 23:03:35.043145 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8479 23:03:35.046135 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8480 23:03:35.050010 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8481 23:03:35.056919 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8482 23:03:35.059527 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8483 23:03:35.062773 0 12 24 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
8484 23:03:35.069436 0 12 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8485 23:03:35.072906 0 13 0 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
8486 23:03:35.076143 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8487 23:03:35.082715 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8488 23:03:35.086129 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8489 23:03:35.089454 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8490 23:03:35.096412 0 13 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8491 23:03:35.099487 0 13 24 | B1->B0 | 2323 4141 | 0 1 | (0 0) (0 0)
8492 23:03:35.102857 0 13 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8493 23:03:35.106021 0 14 0 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
8494 23:03:35.112702 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8495 23:03:35.116173 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8496 23:03:35.119464 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8497 23:03:35.126227 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8498 23:03:35.129140 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8499 23:03:35.132644 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8500 23:03:35.139064 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8501 23:03:35.142333 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8502 23:03:35.145480 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8503 23:03:35.152627 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8504 23:03:35.155620 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8505 23:03:35.159012 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8506 23:03:35.165314 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8507 23:03:35.168953 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8508 23:03:35.171960 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8509 23:03:35.178558 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8510 23:03:35.181783 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8511 23:03:35.185366 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8512 23:03:35.191996 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8513 23:03:35.195468 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8514 23:03:35.198672 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8515 23:03:35.205349 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8516 23:03:35.208873 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8517 23:03:35.212130 Total UI for P1: 0, mck2ui 16
8518 23:03:35.215078 best dqsien dly found for B0: ( 1, 0, 24)
8519 23:03:35.218542 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8520 23:03:35.225328 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8521 23:03:35.228296 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8522 23:03:35.231435 Total UI for P1: 0, mck2ui 16
8523 23:03:35.234876 best dqsien dly found for B1: ( 1, 1, 0)
8524 23:03:35.238024 best DQS0 dly(MCK, UI, PI) = (1, 0, 24)
8525 23:03:35.241702 best DQS1 dly(MCK, UI, PI) = (1, 1, 0)
8526 23:03:35.242264
8527 23:03:35.244869 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 24)
8528 23:03:35.248027 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 0)
8529 23:03:35.251884 [Gating] SW calibration Done
8530 23:03:35.252443 ==
8531 23:03:35.254787 Dram Type= 6, Freq= 0, CH_1, rank 1
8532 23:03:35.261263 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8533 23:03:35.261793 ==
8534 23:03:35.262195 RX Vref Scan: 0
8535 23:03:35.262537
8536 23:03:35.264864 RX Vref 0 -> 0, step: 1
8537 23:03:35.265341
8538 23:03:35.268089 RX Delay 0 -> 252, step: 8
8539 23:03:35.271256 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8540 23:03:35.274310 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8541 23:03:35.278876 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8542 23:03:35.281184 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8543 23:03:35.287723 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8544 23:03:35.291132 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8545 23:03:35.294236 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8546 23:03:35.298050 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8547 23:03:35.301006 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8548 23:03:35.307893 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8549 23:03:35.310676 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8550 23:03:35.314602 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8551 23:03:35.317445 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8552 23:03:35.320667 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8553 23:03:35.327279 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8554 23:03:35.330881 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8555 23:03:35.331341 ==
8556 23:03:35.333848 Dram Type= 6, Freq= 0, CH_1, rank 1
8557 23:03:35.337302 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8558 23:03:35.337767 ==
8559 23:03:35.340861 DQS Delay:
8560 23:03:35.341387 DQS0 = 0, DQS1 = 0
8561 23:03:35.341759 DQM Delay:
8562 23:03:35.343805 DQM0 = 132, DQM1 = 125
8563 23:03:35.344266 DQ Delay:
8564 23:03:35.347217 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8565 23:03:35.350812 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =131
8566 23:03:35.357279 DQ8 =107, DQ9 =115, DQ10 =123, DQ11 =115
8567 23:03:35.360568 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =135
8568 23:03:35.361104
8569 23:03:35.361468
8570 23:03:35.361804 ==
8571 23:03:35.363610 Dram Type= 6, Freq= 0, CH_1, rank 1
8572 23:03:35.367057 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8573 23:03:35.367520 ==
8574 23:03:35.367961
8575 23:03:35.368305
8576 23:03:35.370570 TX Vref Scan disable
8577 23:03:35.373665 == TX Byte 0 ==
8578 23:03:35.377227 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8579 23:03:35.380620 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8580 23:03:35.383542 == TX Byte 1 ==
8581 23:03:35.386819 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8582 23:03:35.390408 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8583 23:03:35.390871 ==
8584 23:03:35.393986 Dram Type= 6, Freq= 0, CH_1, rank 1
8585 23:03:35.397072 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8586 23:03:35.397532 ==
8587 23:03:35.412425
8588 23:03:35.415300 TX Vref early break, caculate TX vref
8589 23:03:35.418728 TX Vref=16, minBit 0, minWin=21, winSum=373
8590 23:03:35.422105 TX Vref=18, minBit 0, minWin=22, winSum=380
8591 23:03:35.424966 TX Vref=20, minBit 0, minWin=22, winSum=389
8592 23:03:35.428140 TX Vref=22, minBit 0, minWin=24, winSum=399
8593 23:03:35.431912 TX Vref=24, minBit 0, minWin=24, winSum=405
8594 23:03:35.438196 TX Vref=26, minBit 1, minWin=25, winSum=415
8595 23:03:35.441855 TX Vref=28, minBit 0, minWin=24, winSum=417
8596 23:03:35.444886 TX Vref=30, minBit 0, minWin=24, winSum=411
8597 23:03:35.448380 TX Vref=32, minBit 0, minWin=22, winSum=402
8598 23:03:35.451444 TX Vref=34, minBit 5, minWin=23, winSum=397
8599 23:03:35.455615 TX Vref=36, minBit 0, minWin=22, winSum=387
8600 23:03:35.461374 [TxChooseVref] Worse bit 1, Min win 25, Win sum 415, Final Vref 26
8601 23:03:35.461934
8602 23:03:35.464625 Final TX Range 0 Vref 26
8603 23:03:35.465153
8604 23:03:35.465533 ==
8605 23:03:35.468003 Dram Type= 6, Freq= 0, CH_1, rank 1
8606 23:03:35.471089 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8607 23:03:35.471641 ==
8608 23:03:35.474633
8609 23:03:35.475088
8610 23:03:35.475453 TX Vref Scan disable
8611 23:03:35.481350 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8612 23:03:35.481913 == TX Byte 0 ==
8613 23:03:35.484875 u2DelayCellOfst[0]=18 cells (5 PI)
8614 23:03:35.488019 u2DelayCellOfst[1]=7 cells (2 PI)
8615 23:03:35.491081 u2DelayCellOfst[2]=0 cells (0 PI)
8616 23:03:35.494510 u2DelayCellOfst[3]=3 cells (1 PI)
8617 23:03:35.497862 u2DelayCellOfst[4]=7 cells (2 PI)
8618 23:03:35.500931 u2DelayCellOfst[5]=14 cells (4 PI)
8619 23:03:35.504841 u2DelayCellOfst[6]=14 cells (4 PI)
8620 23:03:35.507689 u2DelayCellOfst[7]=3 cells (1 PI)
8621 23:03:35.511347 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8622 23:03:35.514687 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8623 23:03:35.517696 == TX Byte 1 ==
8624 23:03:35.521156 u2DelayCellOfst[8]=0 cells (0 PI)
8625 23:03:35.524605 u2DelayCellOfst[9]=7 cells (2 PI)
8626 23:03:35.527932 u2DelayCellOfst[10]=14 cells (4 PI)
8627 23:03:35.528490 u2DelayCellOfst[11]=7 cells (2 PI)
8628 23:03:35.531003 u2DelayCellOfst[12]=18 cells (5 PI)
8629 23:03:35.534147 u2DelayCellOfst[13]=21 cells (6 PI)
8630 23:03:35.537475 u2DelayCellOfst[14]=21 cells (6 PI)
8631 23:03:35.540637 u2DelayCellOfst[15]=18 cells (5 PI)
8632 23:03:35.547244 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8633 23:03:35.550936 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8634 23:03:35.551399 DramC Write-DBI on
8635 23:03:35.553624 ==
8636 23:03:35.554080 Dram Type= 6, Freq= 0, CH_1, rank 1
8637 23:03:35.560620 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8638 23:03:35.561182 ==
8639 23:03:35.561553
8640 23:03:35.561892
8641 23:03:35.563650 TX Vref Scan disable
8642 23:03:35.564210 == TX Byte 0 ==
8643 23:03:35.570246 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8644 23:03:35.570708 == TX Byte 1 ==
8645 23:03:35.573489 Update DQM dly =718 (2 ,6, 14) DQM OEN =(3 ,3)
8646 23:03:35.576938 DramC Write-DBI off
8647 23:03:35.577493
8648 23:03:35.577864 [DATLAT]
8649 23:03:35.580662 Freq=1600, CH1 RK1
8650 23:03:35.581293
8651 23:03:35.581667 DATLAT Default: 0xe
8652 23:03:35.583798 0, 0xFFFF, sum = 0
8653 23:03:35.584366 1, 0xFFFF, sum = 0
8654 23:03:35.587043 2, 0xFFFF, sum = 0
8655 23:03:35.587680 3, 0xFFFF, sum = 0
8656 23:03:35.590108 4, 0xFFFF, sum = 0
8657 23:03:35.590683 5, 0xFFFF, sum = 0
8658 23:03:35.593309 6, 0xFFFF, sum = 0
8659 23:03:35.593773 7, 0xFFFF, sum = 0
8660 23:03:35.596584 8, 0xFFFF, sum = 0
8661 23:03:35.600171 9, 0xFFFF, sum = 0
8662 23:03:35.600693 10, 0xFFFF, sum = 0
8663 23:03:35.603423 11, 0xFFFF, sum = 0
8664 23:03:35.603889 12, 0xF7F, sum = 0
8665 23:03:35.606875 13, 0x0, sum = 1
8666 23:03:35.607702 14, 0x0, sum = 2
8667 23:03:35.610031 15, 0x0, sum = 3
8668 23:03:35.610498 16, 0x0, sum = 4
8669 23:03:35.610869 best_step = 14
8670 23:03:35.611206
8671 23:03:35.613464 ==
8672 23:03:35.616691 Dram Type= 6, Freq= 0, CH_1, rank 1
8673 23:03:35.619852 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8674 23:03:35.620314 ==
8675 23:03:35.620728 RX Vref Scan: 0
8676 23:03:35.621069
8677 23:03:35.623163 RX Vref 0 -> 0, step: 1
8678 23:03:35.623619
8679 23:03:35.626693 RX Delay 3 -> 252, step: 4
8680 23:03:35.629989 iDelay=195, Bit 0, Center 128 (75 ~ 182) 108
8681 23:03:35.633169 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
8682 23:03:35.640129 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
8683 23:03:35.643762 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8684 23:03:35.646483 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8685 23:03:35.649982 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8686 23:03:35.653286 iDelay=195, Bit 6, Center 134 (79 ~ 190) 112
8687 23:03:35.659858 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8688 23:03:35.663109 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
8689 23:03:35.666232 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8690 23:03:35.669661 iDelay=195, Bit 10, Center 124 (67 ~ 182) 116
8691 23:03:35.673071 iDelay=195, Bit 11, Center 112 (55 ~ 170) 116
8692 23:03:35.680564 iDelay=195, Bit 12, Center 132 (75 ~ 190) 116
8693 23:03:35.683102 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8694 23:03:35.686575 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
8695 23:03:35.690026 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8696 23:03:35.690488 ==
8697 23:03:35.693261 Dram Type= 6, Freq= 0, CH_1, rank 1
8698 23:03:35.699758 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8699 23:03:35.700317 ==
8700 23:03:35.700754 DQS Delay:
8701 23:03:35.703001 DQS0 = 0, DQS1 = 0
8702 23:03:35.703560 DQM Delay:
8703 23:03:35.706338 DQM0 = 127, DQM1 = 122
8704 23:03:35.706899 DQ Delay:
8705 23:03:35.709611 DQ0 =128, DQ1 =124, DQ2 =116, DQ3 =124
8706 23:03:35.712868 DQ4 =126, DQ5 =138, DQ6 =134, DQ7 =126
8707 23:03:35.716220 DQ8 =106, DQ9 =110, DQ10 =124, DQ11 =112
8708 23:03:35.719446 DQ12 =132, DQ13 =132, DQ14 =134, DQ15 =132
8709 23:03:35.720016
8710 23:03:35.720380
8711 23:03:35.720785
8712 23:03:35.722642 [DramC_TX_OE_Calibration] TA2
8713 23:03:35.726286 Original DQ_B0 (3 6) =30, OEN = 27
8714 23:03:35.729522 Original DQ_B1 (3 6) =30, OEN = 27
8715 23:03:35.732664 24, 0x0, End_B0=24 End_B1=24
8716 23:03:35.736040 25, 0x0, End_B0=25 End_B1=25
8717 23:03:35.736547 26, 0x0, End_B0=26 End_B1=26
8718 23:03:35.739085 27, 0x0, End_B0=27 End_B1=27
8719 23:03:35.742787 28, 0x0, End_B0=28 End_B1=28
8720 23:03:35.745679 29, 0x0, End_B0=29 End_B1=29
8721 23:03:35.746144 30, 0x0, End_B0=30 End_B1=30
8722 23:03:35.748922 31, 0x5151, End_B0=30 End_B1=30
8723 23:03:35.752555 Byte0 end_step=30 best_step=27
8724 23:03:35.755956 Byte1 end_step=30 best_step=27
8725 23:03:35.759292 Byte0 TX OE(2T, 0.5T) = (3, 3)
8726 23:03:35.762225 Byte1 TX OE(2T, 0.5T) = (3, 3)
8727 23:03:35.762683
8728 23:03:35.763044
8729 23:03:35.769024 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e1e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
8730 23:03:35.772252 CH1 RK1: MR19=303, MR18=1E1E
8731 23:03:35.779045 CH1_RK1: MR19=0x303, MR18=0x1E1E, DQSOSC=394, MR23=63, INC=23, DEC=15
8732 23:03:35.782351 [RxdqsGatingPostProcess] freq 1600
8733 23:03:35.785479 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8734 23:03:35.788983 Pre-setting of DQS Precalculation
8735 23:03:35.795587 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8736 23:03:35.802316 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8737 23:03:35.808864 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8738 23:03:35.809430
8739 23:03:35.809792
8740 23:03:35.812413 [Calibration Summary] 3200 Mbps
8741 23:03:35.815662 CH 0, Rank 0
8742 23:03:35.816217 SW Impedance : PASS
8743 23:03:35.818651 DUTY Scan : NO K
8744 23:03:35.821895 ZQ Calibration : PASS
8745 23:03:35.822455 Jitter Meter : NO K
8746 23:03:35.825209 CBT Training : PASS
8747 23:03:35.828626 Write leveling : PASS
8748 23:03:35.829189 RX DQS gating : PASS
8749 23:03:35.831991 RX DQ/DQS(RDDQC) : PASS
8750 23:03:35.832589 TX DQ/DQS : PASS
8751 23:03:35.835024 RX DATLAT : PASS
8752 23:03:35.838251 RX DQ/DQS(Engine): PASS
8753 23:03:35.838815 TX OE : PASS
8754 23:03:35.841792 All Pass.
8755 23:03:35.842350
8756 23:03:35.842715 CH 0, Rank 1
8757 23:03:35.844763 SW Impedance : PASS
8758 23:03:35.845224 DUTY Scan : NO K
8759 23:03:35.848368 ZQ Calibration : PASS
8760 23:03:35.851339 Jitter Meter : NO K
8761 23:03:35.851806 CBT Training : PASS
8762 23:03:35.855262 Write leveling : PASS
8763 23:03:35.858467 RX DQS gating : PASS
8764 23:03:35.859058 RX DQ/DQS(RDDQC) : PASS
8765 23:03:35.861419 TX DQ/DQS : PASS
8766 23:03:35.864815 RX DATLAT : PASS
8767 23:03:35.865380 RX DQ/DQS(Engine): PASS
8768 23:03:35.868318 TX OE : PASS
8769 23:03:35.868980 All Pass.
8770 23:03:35.869362
8771 23:03:35.871487 CH 1, Rank 0
8772 23:03:35.872047 SW Impedance : PASS
8773 23:03:35.874655 DUTY Scan : NO K
8774 23:03:35.878188 ZQ Calibration : PASS
8775 23:03:35.878841 Jitter Meter : NO K
8776 23:03:35.881302 CBT Training : PASS
8777 23:03:35.884689 Write leveling : PASS
8778 23:03:35.885260 RX DQS gating : PASS
8779 23:03:35.888050 RX DQ/DQS(RDDQC) : PASS
8780 23:03:35.888666 TX DQ/DQS : PASS
8781 23:03:35.891492 RX DATLAT : PASS
8782 23:03:35.895089 RX DQ/DQS(Engine): PASS
8783 23:03:35.895660 TX OE : PASS
8784 23:03:35.897793 All Pass.
8785 23:03:35.898423
8786 23:03:35.898809 CH 1, Rank 1
8787 23:03:35.901246 SW Impedance : PASS
8788 23:03:35.901715 DUTY Scan : NO K
8789 23:03:35.904979 ZQ Calibration : PASS
8790 23:03:35.908358 Jitter Meter : NO K
8791 23:03:35.908997 CBT Training : PASS
8792 23:03:35.911590 Write leveling : PASS
8793 23:03:35.914815 RX DQS gating : PASS
8794 23:03:35.915389 RX DQ/DQS(RDDQC) : PASS
8795 23:03:35.918090 TX DQ/DQS : PASS
8796 23:03:35.921446 RX DATLAT : PASS
8797 23:03:35.922028 RX DQ/DQS(Engine): PASS
8798 23:03:35.924703 TX OE : PASS
8799 23:03:35.925267 All Pass.
8800 23:03:35.925639
8801 23:03:35.927963 DramC Write-DBI on
8802 23:03:35.931302 PER_BANK_REFRESH: Hybrid Mode
8803 23:03:35.931847 TX_TRACKING: ON
8804 23:03:35.941404 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8805 23:03:35.947832 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8806 23:03:35.954589 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8807 23:03:35.957665 [FAST_K] Save calibration result to emmc
8808 23:03:35.960919 sync common calibartion params.
8809 23:03:35.964025 sync cbt_mode0:0, 1:0
8810 23:03:35.967553 dram_init: ddr_geometry: 0
8811 23:03:35.968018 dram_init: ddr_geometry: 0
8812 23:03:35.971062 dram_init: ddr_geometry: 0
8813 23:03:35.974064 0:dram_rank_size:80000000
8814 23:03:35.974542 1:dram_rank_size:80000000
8815 23:03:35.981192 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8816 23:03:35.984232 DFS_SHUFFLE_HW_MODE: ON
8817 23:03:35.987380 dramc_set_vcore_voltage set vcore to 725000
8818 23:03:35.990733 Read voltage for 1600, 0
8819 23:03:35.991235 Vio18 = 0
8820 23:03:35.991614 Vcore = 725000
8821 23:03:35.994001 Vdram = 0
8822 23:03:35.994568 Vddq = 0
8823 23:03:35.994940 Vmddr = 0
8824 23:03:35.997407 switch to 3200 Mbps bootup
8825 23:03:35.997873 [DramcRunTimeConfig]
8826 23:03:36.000750 PHYPLL
8827 23:03:36.001304 DPM_CONTROL_AFTERK: ON
8828 23:03:36.004263 PER_BANK_REFRESH: ON
8829 23:03:36.007511 REFRESH_OVERHEAD_REDUCTION: ON
8830 23:03:36.008231 CMD_PICG_NEW_MODE: OFF
8831 23:03:36.010993 XRTWTW_NEW_MODE: ON
8832 23:03:36.011563 XRTRTR_NEW_MODE: ON
8833 23:03:36.013961 TX_TRACKING: ON
8834 23:03:36.014535 RDSEL_TRACKING: OFF
8835 23:03:36.017877 DQS Precalculation for DVFS: ON
8836 23:03:36.020799 RX_TRACKING: OFF
8837 23:03:36.021263 HW_GATING DBG: ON
8838 23:03:36.024344 ZQCS_ENABLE_LP4: ON
8839 23:03:36.024952 RX_PICG_NEW_MODE: ON
8840 23:03:36.027644 TX_PICG_NEW_MODE: ON
8841 23:03:36.028211 ENABLE_RX_DCM_DPHY: ON
8842 23:03:36.030813 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8843 23:03:36.034279 DUMMY_READ_FOR_TRACKING: OFF
8844 23:03:36.037324 !!! SPM_CONTROL_AFTERK: OFF
8845 23:03:36.040578 !!! SPM could not control APHY
8846 23:03:36.041155 IMPEDANCE_TRACKING: ON
8847 23:03:36.044112 TEMP_SENSOR: ON
8848 23:03:36.044729 HW_SAVE_FOR_SR: OFF
8849 23:03:36.046858 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8850 23:03:36.050266 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8851 23:03:36.053923 Read ODT Tracking: ON
8852 23:03:36.057387 Refresh Rate DeBounce: ON
8853 23:03:36.057947 DFS_NO_QUEUE_FLUSH: ON
8854 23:03:36.060113 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8855 23:03:36.063754 ENABLE_DFS_RUNTIME_MRW: OFF
8856 23:03:36.066876 DDR_RESERVE_NEW_MODE: ON
8857 23:03:36.067372 MR_CBT_SWITCH_FREQ: ON
8858 23:03:36.070137 =========================
8859 23:03:36.089472 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8860 23:03:36.092586 dram_init: ddr_geometry: 0
8861 23:03:36.111158 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8862 23:03:36.114220 dram_init: dram init end (result: 0)
8863 23:03:36.120967 DRAM-K: Full calibration passed in 23420 msecs
8864 23:03:36.124198 MRC: failed to locate region type 0.
8865 23:03:36.124808 DRAM rank0 size:0x80000000,
8866 23:03:36.127561 DRAM rank1 size=0x80000000
8867 23:03:36.137208 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8868 23:03:36.143919 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8869 23:03:36.150656 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8870 23:03:36.157422 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8871 23:03:36.160285 DRAM rank0 size:0x80000000,
8872 23:03:36.163733 DRAM rank1 size=0x80000000
8873 23:03:36.164295 CBMEM:
8874 23:03:36.166768 IMD: root @ 0xfffff000 254 entries.
8875 23:03:36.170035 IMD: root @ 0xffffec00 62 entries.
8876 23:03:36.173514 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8877 23:03:36.176649 WARNING: RO_VPD is uninitialized or empty.
8878 23:03:36.183489 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8879 23:03:36.190363 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8880 23:03:36.203073 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
8881 23:03:36.214532 BS: romstage times (exec / console): total (unknown) / 22963 ms
8882 23:03:36.215091
8883 23:03:36.215469
8884 23:03:36.224313 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8885 23:03:36.227942 ARM64: Exception handlers installed.
8886 23:03:36.231250 ARM64: Testing exception
8887 23:03:36.234128 ARM64: Done test exception
8888 23:03:36.234594 Enumerating buses...
8889 23:03:36.237780 Show all devs... Before device enumeration.
8890 23:03:36.240824 Root Device: enabled 1
8891 23:03:36.244589 CPU_CLUSTER: 0: enabled 1
8892 23:03:36.245163 CPU: 00: enabled 1
8893 23:03:36.247647 Compare with tree...
8894 23:03:36.248212 Root Device: enabled 1
8895 23:03:36.250978 CPU_CLUSTER: 0: enabled 1
8896 23:03:36.254184 CPU: 00: enabled 1
8897 23:03:36.254740 Root Device scanning...
8898 23:03:36.257707 scan_static_bus for Root Device
8899 23:03:36.260825 CPU_CLUSTER: 0 enabled
8900 23:03:36.264284 scan_static_bus for Root Device done
8901 23:03:36.267568 scan_bus: bus Root Device finished in 8 msecs
8902 23:03:36.268038 done
8903 23:03:36.274161 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8904 23:03:36.277139 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8905 23:03:36.284091 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8906 23:03:36.287444 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8907 23:03:36.290874 Allocating resources...
8908 23:03:36.293918 Reading resources...
8909 23:03:36.297370 Root Device read_resources bus 0 link: 0
8910 23:03:36.297843 DRAM rank0 size:0x80000000,
8911 23:03:36.300699 DRAM rank1 size=0x80000000
8912 23:03:36.304293 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8913 23:03:36.307313 CPU: 00 missing read_resources
8914 23:03:36.310663 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8915 23:03:36.317732 Root Device read_resources bus 0 link: 0 done
8916 23:03:36.318292 Done reading resources.
8917 23:03:36.323789 Show resources in subtree (Root Device)...After reading.
8918 23:03:36.327173 Root Device child on link 0 CPU_CLUSTER: 0
8919 23:03:36.330184 CPU_CLUSTER: 0 child on link 0 CPU: 00
8920 23:03:36.340051 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8921 23:03:36.340799 CPU: 00
8922 23:03:36.343934 Root Device assign_resources, bus 0 link: 0
8923 23:03:36.347134 CPU_CLUSTER: 0 missing set_resources
8924 23:03:36.353496 Root Device assign_resources, bus 0 link: 0 done
8925 23:03:36.354048 Done setting resources.
8926 23:03:36.360571 Show resources in subtree (Root Device)...After assigning values.
8927 23:03:36.363512 Root Device child on link 0 CPU_CLUSTER: 0
8928 23:03:36.366547 CPU_CLUSTER: 0 child on link 0 CPU: 00
8929 23:03:36.376680 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8930 23:03:36.377256 CPU: 00
8931 23:03:36.380053 Done allocating resources.
8932 23:03:36.386637 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
8933 23:03:36.387209 Enabling resources...
8934 23:03:36.387586 done.
8935 23:03:36.393212 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
8936 23:03:36.393781 Initializing devices...
8937 23:03:36.396590 Root Device init
8938 23:03:36.397156 init hardware done!
8939 23:03:36.399977 0x00000018: ctrlr->caps
8940 23:03:36.403575 52.000 MHz: ctrlr->f_max
8941 23:03:36.404153 0.400 MHz: ctrlr->f_min
8942 23:03:36.406732 0x40ff8080: ctrlr->voltages
8943 23:03:36.409870 sclk: 390625
8944 23:03:36.410443 Bus Width = 1
8945 23:03:36.410820 sclk: 390625
8946 23:03:36.412801 Bus Width = 1
8947 23:03:36.413265 Early init status = 3
8948 23:03:36.419610 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
8949 23:03:36.423058 in-header: 03 fc 00 00 01 00 00 00
8950 23:03:36.426086 in-data: 00
8951 23:03:36.429618 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
8952 23:03:36.435256 in-header: 03 fd 00 00 00 00 00 00
8953 23:03:36.438473 in-data:
8954 23:03:36.441591 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
8955 23:03:36.446094 in-header: 03 fc 00 00 01 00 00 00
8956 23:03:36.449790 in-data: 00
8957 23:03:36.452871 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
8958 23:03:36.458432 in-header: 03 fd 00 00 00 00 00 00
8959 23:03:36.461708 in-data:
8960 23:03:36.465169 [SSUSB] Setting up USB HOST controller...
8961 23:03:36.468217 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
8962 23:03:36.471564 [SSUSB] phy power-on done.
8963 23:03:36.474698 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
8964 23:03:36.481683 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
8965 23:03:36.485395 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
8966 23:03:36.491583 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
8967 23:03:36.498174 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
8968 23:03:36.504894 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
8969 23:03:36.512019 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
8970 23:03:36.517988 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
8971 23:03:36.521465 SPM: binary array size = 0x9dc
8972 23:03:36.524772 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
8973 23:03:36.531577 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
8974 23:03:36.537882 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
8975 23:03:36.544625 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
8976 23:03:36.547820 configure_display: Starting display init
8977 23:03:36.581973 anx7625_power_on_init: Init interface.
8978 23:03:36.584993 anx7625_disable_pd_protocol: Disabled PD feature.
8979 23:03:36.588320 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
8980 23:03:36.616114 anx7625_start_dp_work: Secure OCM version=00
8981 23:03:36.619332 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
8982 23:03:36.634346 sp_tx_get_edid_block: EDID Block = 1
8983 23:03:36.737254 Extracted contents:
8984 23:03:36.740239 header: 00 ff ff ff ff ff ff 00
8985 23:03:36.743604 serial number: 26 cf 7d 05 00 00 00 00 00 1e
8986 23:03:36.746717 version: 01 04
8987 23:03:36.750066 basic params: 95 1f 11 78 0a
8988 23:03:36.753503 chroma info: 76 90 94 55 54 90 27 21 50 54
8989 23:03:36.756829 established: 00 00 00
8990 23:03:36.763299 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
8991 23:03:36.766260 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
8992 23:03:36.773210 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
8993 23:03:36.779758 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
8994 23:03:36.786222 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
8995 23:03:36.789358 extensions: 00
8996 23:03:36.789823 checksum: fb
8997 23:03:36.790189
8998 23:03:36.792743 Manufacturer: IVO Model 57d Serial Number 0
8999 23:03:36.796032 Made week 0 of 2020
9000 23:03:36.796725 EDID version: 1.4
9001 23:03:36.800216 Digital display
9002 23:03:36.802987 6 bits per primary color channel
9003 23:03:36.803535 DisplayPort interface
9004 23:03:36.806348 Maximum image size: 31 cm x 17 cm
9005 23:03:36.809792 Gamma: 220%
9006 23:03:36.810330 Check DPMS levels
9007 23:03:36.812584 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9008 23:03:36.819483 First detailed timing is preferred timing
9009 23:03:36.820046 Established timings supported:
9010 23:03:36.822865 Standard timings supported:
9011 23:03:36.825766 Detailed timings
9012 23:03:36.829397 Hex of detail: 383680a07038204018303c0035ae10000019
9013 23:03:36.836263 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9014 23:03:36.839409 0780 0798 07c8 0820 hborder 0
9015 23:03:36.842316 0438 043b 0447 0458 vborder 0
9016 23:03:36.845888 -hsync -vsync
9017 23:03:36.846444 Did detailed timing
9018 23:03:36.852693 Hex of detail: 000000000000000000000000000000000000
9019 23:03:36.855846 Manufacturer-specified data, tag 0
9020 23:03:36.859382 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9021 23:03:36.862265 ASCII string: InfoVision
9022 23:03:36.865515 Hex of detail: 000000fe00523134304e574635205248200a
9023 23:03:36.868888 ASCII string: R140NWF5 RH
9024 23:03:36.869350 Checksum
9025 23:03:36.872244 Checksum: 0xfb (valid)
9026 23:03:36.875363 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9027 23:03:36.878696 DSI data_rate: 832800000 bps
9028 23:03:36.885570 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9029 23:03:36.888978 anx7625_parse_edid: pixelclock(138800).
9030 23:03:36.892458 hactive(1920), hsync(48), hfp(24), hbp(88)
9031 23:03:36.895544 vactive(1080), vsync(12), vfp(3), vbp(17)
9032 23:03:36.898701 anx7625_dsi_config: config dsi.
9033 23:03:36.905663 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9034 23:03:36.918876 anx7625_dsi_config: success to config DSI
9035 23:03:36.922127 anx7625_dp_start: MIPI phy setup OK.
9036 23:03:36.925118 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9037 23:03:36.928596 mtk_ddp_mode_set invalid vrefresh 60
9038 23:03:36.931905 main_disp_path_setup
9039 23:03:36.932457 ovl_layer_smi_id_en
9040 23:03:36.935336 ovl_layer_smi_id_en
9041 23:03:36.935894 ccorr_config
9042 23:03:36.936258 aal_config
9043 23:03:36.938625 gamma_config
9044 23:03:36.939186 postmask_config
9045 23:03:36.941933 dither_config
9046 23:03:36.945126 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9047 23:03:36.951878 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9048 23:03:36.955196 Root Device init finished in 555 msecs
9049 23:03:36.958290 CPU_CLUSTER: 0 init
9050 23:03:36.965107 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9051 23:03:36.968595 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9052 23:03:36.971829 APU_MBOX 0x190000b0 = 0x10001
9053 23:03:36.975215 APU_MBOX 0x190001b0 = 0x10001
9054 23:03:36.978308 APU_MBOX 0x190005b0 = 0x10001
9055 23:03:36.981593 APU_MBOX 0x190006b0 = 0x10001
9056 23:03:36.984760 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9057 23:03:36.997592 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9058 23:03:37.009980 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9059 23:03:37.016921 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9060 23:03:37.028849 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9061 23:03:37.037529 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9062 23:03:37.040678 CPU_CLUSTER: 0 init finished in 81 msecs
9063 23:03:37.043916 Devices initialized
9064 23:03:37.047290 Show all devs... After init.
9065 23:03:37.047754 Root Device: enabled 1
9066 23:03:37.050716 CPU_CLUSTER: 0: enabled 1
9067 23:03:37.054093 CPU: 00: enabled 1
9068 23:03:37.057348 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9069 23:03:37.060389 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9070 23:03:37.063655 ELOG: NV offset 0x57f000 size 0x1000
9071 23:03:37.070490 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9072 23:03:37.076920 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9073 23:03:37.080336 ELOG: Event(17) added with size 13 at 2023-12-01 23:03:37 UTC
9074 23:03:37.084324 out: cmd=0x121: 03 db 21 01 00 00 00 00
9075 23:03:37.087722 in-header: 03 f3 00 00 2c 00 00 00
9076 23:03:37.101486 in-data: 70 64 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9077 23:03:37.107891 ELOG: Event(A1) added with size 10 at 2023-12-01 23:03:37 UTC
9078 23:03:37.114307 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9079 23:03:37.120910 ELOG: Event(A0) added with size 9 at 2023-12-01 23:03:37 UTC
9080 23:03:37.124548 elog_add_boot_reason: Logged dev mode boot
9081 23:03:37.127654 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9082 23:03:37.131148 Finalize devices...
9083 23:03:37.131720 Devices finalized
9084 23:03:37.137604 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9085 23:03:37.140756 Writing coreboot table at 0xffe64000
9086 23:03:37.144055 0. 000000000010a000-0000000000113fff: RAMSTAGE
9087 23:03:37.147609 1. 0000000040000000-00000000400fffff: RAM
9088 23:03:37.154019 2. 0000000040100000-000000004032afff: RAMSTAGE
9089 23:03:37.157708 3. 000000004032b000-00000000545fffff: RAM
9090 23:03:37.160659 4. 0000000054600000-000000005465ffff: BL31
9091 23:03:37.163766 5. 0000000054660000-00000000ffe63fff: RAM
9092 23:03:37.170653 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9093 23:03:37.173571 7. 0000000100000000-000000013fffffff: RAM
9094 23:03:37.177118 Passing 5 GPIOs to payload:
9095 23:03:37.180489 NAME | PORT | POLARITY | VALUE
9096 23:03:37.183572 EC in RW | 0x000000aa | low | undefined
9097 23:03:37.190609 EC interrupt | 0x00000005 | low | undefined
9098 23:03:37.193804 TPM interrupt | 0x000000ab | high | undefined
9099 23:03:37.200227 SD card detect | 0x00000011 | high | undefined
9100 23:03:37.203385 speaker enable | 0x00000093 | high | undefined
9101 23:03:37.208228 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9102 23:03:37.210085 in-header: 03 f4 00 00 02 00 00 00
9103 23:03:37.210552 in-data: 07 00
9104 23:03:37.213443 ADC[4]: Raw value=669327 ID=5
9105 23:03:37.216813 ADC[3]: Raw value=212549 ID=1
9106 23:03:37.220595 RAM Code: 0x51
9107 23:03:37.221168 ADC[6]: Raw value=74778 ID=0
9108 23:03:37.223627 ADC[5]: Raw value=211444 ID=1
9109 23:03:37.226497 SKU Code: 0x1
9110 23:03:37.230269 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 8b66
9111 23:03:37.233566 coreboot table: 964 bytes.
9112 23:03:37.236491 IMD ROOT 0. 0xfffff000 0x00001000
9113 23:03:37.240106 IMD SMALL 1. 0xffffe000 0x00001000
9114 23:03:37.243379 RO MCACHE 2. 0xffffc000 0x00001104
9115 23:03:37.246452 CONSOLE 3. 0xfff7c000 0x00080000
9116 23:03:37.249959 FMAP 4. 0xfff7b000 0x00000452
9117 23:03:37.253307 TIME STAMP 5. 0xfff7a000 0x00000910
9118 23:03:37.256497 VBOOT WORK 6. 0xfff66000 0x00014000
9119 23:03:37.259818 RAMOOPS 7. 0xffe66000 0x00100000
9120 23:03:37.263062 COREBOOT 8. 0xffe64000 0x00002000
9121 23:03:37.263697 IMD small region:
9122 23:03:37.266481 IMD ROOT 0. 0xffffec00 0x00000400
9123 23:03:37.269755 VPD 1. 0xffffeb80 0x0000006c
9124 23:03:37.276025 MMC STATUS 2. 0xffffeb60 0x00000004
9125 23:03:37.279360 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9126 23:03:37.282641 Probing TPM: done!
9127 23:03:37.285890 Connected to device vid:did:rid of 1ae0:0028:00
9128 23:03:37.295969 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
9129 23:03:37.299271 Initialized TPM device CR50 revision 0
9130 23:03:37.302777 Checking cr50 for pending updates
9131 23:03:37.306271 Reading cr50 TPM mode
9132 23:03:37.315154 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9133 23:03:37.321769 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9134 23:03:37.361694 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9135 23:03:37.365007 Checking segment from ROM address 0x40100000
9136 23:03:37.368494 Checking segment from ROM address 0x4010001c
9137 23:03:37.375066 Loading segment from ROM address 0x40100000
9138 23:03:37.375142 code (compression=0)
9139 23:03:37.384883 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9140 23:03:37.391496 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9141 23:03:37.391603 it's not compressed!
9142 23:03:37.398102 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9143 23:03:37.405071 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9144 23:03:37.422327 Loading segment from ROM address 0x4010001c
9145 23:03:37.422441 Entry Point 0x80000000
9146 23:03:37.425430 Loaded segments
9147 23:03:37.429217 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9148 23:03:37.435622 Jumping to boot code at 0x80000000(0xffe64000)
9149 23:03:37.442019 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9150 23:03:37.448928 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9151 23:03:37.456578 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9152 23:03:37.460028 Checking segment from ROM address 0x40100000
9153 23:03:37.463469 Checking segment from ROM address 0x4010001c
9154 23:03:37.469820 Loading segment from ROM address 0x40100000
9155 23:03:37.469901 code (compression=1)
9156 23:03:37.476542 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9157 23:03:37.486503 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9158 23:03:37.486584 using LZMA
9159 23:03:37.495052 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9160 23:03:37.501459 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9161 23:03:37.504928 Loading segment from ROM address 0x4010001c
9162 23:03:37.505016 Entry Point 0x54601000
9163 23:03:37.508424 Loaded segments
9164 23:03:37.511588 NOTICE: MT8192 bl31_setup
9165 23:03:37.518601 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9166 23:03:37.521953 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9167 23:03:37.525378 WARNING: region 0:
9168 23:03:37.528494 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9169 23:03:37.528586 WARNING: region 1:
9170 23:03:37.535228 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9171 23:03:37.538966 WARNING: region 2:
9172 23:03:37.541932 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9173 23:03:37.545332 WARNING: region 3:
9174 23:03:37.548525 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9175 23:03:37.551808 WARNING: region 4:
9176 23:03:37.558496 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9177 23:03:37.558578 WARNING: region 5:
9178 23:03:37.561739 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9179 23:03:37.565281 WARNING: region 6:
9180 23:03:37.568690 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9181 23:03:37.571882 WARNING: region 7:
9182 23:03:37.575416 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9183 23:03:37.582139 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9184 23:03:37.585214 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9185 23:03:37.588536 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9186 23:03:37.595163 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9187 23:03:37.598430 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9188 23:03:37.601894 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9189 23:03:37.608657 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9190 23:03:37.611852 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9191 23:03:37.618428 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9192 23:03:37.621604 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9193 23:03:37.624862 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9194 23:03:37.631766 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9195 23:03:37.634924 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9196 23:03:37.638228 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9197 23:03:37.645074 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9198 23:03:37.648348 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9199 23:03:37.655171 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9200 23:03:37.658411 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9201 23:03:37.661670 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9202 23:03:37.668179 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9203 23:03:37.671756 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9204 23:03:37.674848 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9205 23:03:37.682094 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9206 23:03:37.684911 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9207 23:03:37.691592 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9208 23:03:37.694892 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9209 23:03:37.698313 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9210 23:03:37.704689 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9211 23:03:37.708135 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9212 23:03:37.715101 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9213 23:03:37.718515 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9214 23:03:37.721788 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9215 23:03:37.728310 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9216 23:03:37.731808 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9217 23:03:37.735196 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9218 23:03:37.738429 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9219 23:03:37.745019 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9220 23:03:37.748453 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9221 23:03:37.751951 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9222 23:03:37.754978 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9223 23:03:37.761589 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9224 23:03:37.764927 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9225 23:03:37.768319 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9226 23:03:37.771612 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9227 23:03:37.778425 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9228 23:03:37.781628 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9229 23:03:37.785066 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9230 23:03:37.788229 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9231 23:03:37.794930 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9232 23:03:37.798190 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9233 23:03:37.805010 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9234 23:03:37.808221 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9235 23:03:37.814788 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9236 23:03:37.818197 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9237 23:03:37.821734 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9238 23:03:37.828213 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9239 23:03:37.831798 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9240 23:03:37.838357 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9241 23:03:37.841594 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9242 23:03:37.844890 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9243 23:03:37.851672 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9244 23:03:37.855199 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9245 23:03:37.861608 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9246 23:03:37.864734 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9247 23:03:37.871449 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9248 23:03:37.874844 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9249 23:03:37.881450 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9250 23:03:37.884689 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9251 23:03:37.888240 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9252 23:03:37.894713 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9253 23:03:37.897813 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9254 23:03:37.904669 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9255 23:03:37.908127 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9256 23:03:37.914601 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9257 23:03:37.917987 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9258 23:03:37.921262 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9259 23:03:37.928092 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9260 23:03:37.931445 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9261 23:03:37.937881 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9262 23:03:37.941230 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9263 23:03:37.948100 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9264 23:03:37.951730 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9265 23:03:37.958364 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9266 23:03:37.961226 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9267 23:03:37.964961 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9268 23:03:37.971256 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9269 23:03:37.974724 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9270 23:03:37.981172 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9271 23:03:37.984678 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9272 23:03:37.991419 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9273 23:03:37.994788 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9274 23:03:37.997883 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9275 23:03:38.004588 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9276 23:03:38.007986 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9277 23:03:38.014538 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9278 23:03:38.017917 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9279 23:03:38.021329 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9280 23:03:38.027877 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9281 23:03:38.031072 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9282 23:03:38.034525 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9283 23:03:38.037837 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9284 23:03:38.044574 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9285 23:03:38.047799 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9286 23:03:38.054401 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9287 23:03:38.057714 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9288 23:03:38.061119 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9289 23:03:38.067876 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9290 23:03:38.071784 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9291 23:03:38.078236 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9292 23:03:38.081149 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9293 23:03:38.084456 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9294 23:03:38.091063 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9295 23:03:38.094374 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9296 23:03:38.101081 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9297 23:03:38.104647 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9298 23:03:38.107637 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9299 23:03:38.114344 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9300 23:03:38.117836 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9301 23:03:38.121277 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9302 23:03:38.127824 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9303 23:03:38.131039 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9304 23:03:38.134197 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9305 23:03:38.137585 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9306 23:03:38.141029 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9307 23:03:38.147861 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9308 23:03:38.151129 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9309 23:03:38.157801 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9310 23:03:38.160991 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9311 23:03:38.164319 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9312 23:03:38.171400 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9313 23:03:38.174639 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9314 23:03:38.180861 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9315 23:03:38.184132 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9316 23:03:38.187689 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9317 23:03:38.194754 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9318 23:03:38.197689 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9319 23:03:38.204236 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9320 23:03:38.207731 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9321 23:03:38.210992 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9322 23:03:38.217448 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9323 23:03:38.220909 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9324 23:03:38.227545 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9325 23:03:38.230801 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9326 23:03:38.234174 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9327 23:03:38.241161 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9328 23:03:38.244302 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9329 23:03:38.247524 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9330 23:03:38.254137 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9331 23:03:38.257637 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9332 23:03:38.264555 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9333 23:03:38.267614 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9334 23:03:38.270896 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9335 23:03:38.277781 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9336 23:03:38.280958 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9337 23:03:38.284310 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9338 23:03:38.290805 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9339 23:03:38.294554 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9340 23:03:38.300893 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9341 23:03:38.304068 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9342 23:03:38.307702 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9343 23:03:38.314234 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9344 23:03:38.317521 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9345 23:03:38.323963 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9346 23:03:38.327253 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9347 23:03:38.333646 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9348 23:03:38.337141 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9349 23:03:38.340460 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9350 23:03:38.347059 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9351 23:03:38.350121 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9352 23:03:38.353720 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9353 23:03:38.360254 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9354 23:03:38.363838 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9355 23:03:38.370171 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9356 23:03:38.373411 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9357 23:03:38.376863 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9358 23:03:38.383629 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9359 23:03:38.387059 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9360 23:03:38.393584 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9361 23:03:38.396851 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9362 23:03:38.400188 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9363 23:03:38.406783 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9364 23:03:38.409912 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9365 23:03:38.416590 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9366 23:03:38.420147 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9367 23:03:38.423215 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9368 23:03:38.429559 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9369 23:03:38.433587 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9370 23:03:38.439942 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9371 23:03:38.442974 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9372 23:03:38.446176 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9373 23:03:38.452864 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9374 23:03:38.456214 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9375 23:03:38.463065 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9376 23:03:38.466301 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9377 23:03:38.472683 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9378 23:03:38.476006 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9379 23:03:38.479437 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9380 23:03:38.485834 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9381 23:03:38.489115 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9382 23:03:38.495911 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9383 23:03:38.499307 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9384 23:03:38.502609 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9385 23:03:38.509317 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9386 23:03:38.512854 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9387 23:03:38.519069 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9388 23:03:38.522561 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9389 23:03:38.529004 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9390 23:03:38.532252 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9391 23:03:38.535597 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9392 23:03:38.542332 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9393 23:03:38.545451 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9394 23:03:38.552248 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9395 23:03:38.555686 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9396 23:03:38.562045 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9397 23:03:38.565433 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9398 23:03:38.568814 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9399 23:03:38.575400 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9400 23:03:38.578876 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9401 23:03:38.585502 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9402 23:03:38.588685 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9403 23:03:38.591997 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9404 23:03:38.598601 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9405 23:03:38.602030 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9406 23:03:38.608562 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9407 23:03:38.612273 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9408 23:03:38.618624 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9409 23:03:38.622018 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9410 23:03:38.625121 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9411 23:03:38.632067 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9412 23:03:38.635315 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9413 23:03:38.638640 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9414 23:03:38.641850 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9415 23:03:38.648201 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9416 23:03:38.651616 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9417 23:03:38.655007 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9418 23:03:38.661456 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9419 23:03:38.664792 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9420 23:03:38.671730 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9421 23:03:38.674959 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9422 23:03:38.677986 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9423 23:03:38.684915 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9424 23:03:38.688120 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9425 23:03:38.691270 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9426 23:03:38.697927 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9427 23:03:38.701307 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9428 23:03:38.704712 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9429 23:03:38.711043 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9430 23:03:38.714524 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9431 23:03:38.717644 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9432 23:03:38.724311 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9433 23:03:38.728033 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9434 23:03:38.734355 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9435 23:03:38.737719 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9436 23:03:38.741066 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9437 23:03:38.747738 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9438 23:03:38.750899 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9439 23:03:38.754339 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9440 23:03:38.760882 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9441 23:03:38.764187 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9442 23:03:38.770735 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9443 23:03:38.774152 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9444 23:03:38.777568 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9445 23:03:38.783959 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9446 23:03:38.787247 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9447 23:03:38.790614 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9448 23:03:38.797242 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9449 23:03:38.800778 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9450 23:03:38.807260 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9451 23:03:38.810319 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9452 23:03:38.813963 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9453 23:03:38.817089 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9454 23:03:38.823800 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9455 23:03:38.826994 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9456 23:03:38.830139 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9457 23:03:38.833715 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9458 23:03:38.837117 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9459 23:03:38.843457 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9460 23:03:38.847035 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9461 23:03:38.850198 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9462 23:03:38.853457 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9463 23:03:38.860233 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9464 23:03:38.863415 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9465 23:03:38.870101 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9466 23:03:38.873559 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9467 23:03:38.876702 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9468 23:03:38.883149 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9469 23:03:38.886738 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9470 23:03:38.893213 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9471 23:03:38.896424 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9472 23:03:38.900277 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9473 23:03:38.906659 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9474 23:03:38.909908 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9475 23:03:38.916632 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9476 23:03:38.919804 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9477 23:03:38.926474 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9478 23:03:38.929589 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9479 23:03:38.932969 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9480 23:03:38.939766 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9481 23:03:38.942831 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9482 23:03:38.949588 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9483 23:03:38.952705 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9484 23:03:38.956271 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9485 23:03:38.962665 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9486 23:03:38.966172 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9487 23:03:38.972923 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9488 23:03:38.976197 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9489 23:03:38.979607 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9490 23:03:38.985963 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9491 23:03:38.989230 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9492 23:03:38.995925 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9493 23:03:38.999264 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9494 23:03:39.005701 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9495 23:03:39.008895 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9496 23:03:39.012435 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9497 23:03:39.018995 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9498 23:03:39.022474 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9499 23:03:39.028959 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9500 23:03:39.032404 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9501 23:03:39.035597 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9502 23:03:39.042267 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9503 23:03:39.045618 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9504 23:03:39.052330 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9505 23:03:39.055805 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9506 23:03:39.059070 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9507 23:03:39.065321 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9508 23:03:39.068783 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9509 23:03:39.075083 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9510 23:03:39.078653 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9511 23:03:39.085093 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9512 23:03:39.088446 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9513 23:03:39.091811 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9514 23:03:39.098412 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9515 23:03:39.101980 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9516 23:03:39.108423 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9517 23:03:39.111640 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9518 23:03:39.114818 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9519 23:03:39.121818 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9520 23:03:39.124818 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9521 23:03:39.131395 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9522 23:03:39.135023 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9523 23:03:39.137996 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9524 23:03:39.144656 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9525 23:03:39.148216 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9526 23:03:39.155003 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9527 23:03:39.157969 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9528 23:03:39.164398 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9529 23:03:39.167656 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9530 23:03:39.171048 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9531 23:03:39.177607 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9532 23:03:39.180958 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9533 23:03:39.187825 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9534 23:03:39.191031 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9535 23:03:39.197853 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9536 23:03:39.200775 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9537 23:03:39.204152 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9538 23:03:39.210858 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9539 23:03:39.213834 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9540 23:03:39.220474 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9541 23:03:39.223948 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9542 23:03:39.230329 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9543 23:03:39.233795 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9544 23:03:39.237313 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9545 23:03:39.243886 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9546 23:03:39.246967 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9547 23:03:39.253731 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9548 23:03:39.257349 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9549 23:03:39.263520 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9550 23:03:39.266640 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9551 23:03:39.273313 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9552 23:03:39.276495 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9553 23:03:39.279957 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9554 23:03:39.286734 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9555 23:03:39.290005 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9556 23:03:39.296633 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9557 23:03:39.299767 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9558 23:03:39.306662 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9559 23:03:39.310033 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9560 23:03:39.313216 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9561 23:03:39.320052 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9562 23:03:39.323042 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9563 23:03:39.329738 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9564 23:03:39.333369 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9565 23:03:39.339519 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9566 23:03:39.342744 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9567 23:03:39.349743 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9568 23:03:39.352700 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9569 23:03:39.356269 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9570 23:03:39.362726 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9571 23:03:39.365966 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9572 23:03:39.372909 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9573 23:03:39.375907 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9574 23:03:39.382982 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9575 23:03:39.385858 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9576 23:03:39.389234 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9577 23:03:39.395733 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9578 23:03:39.399080 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9579 23:03:39.406060 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9580 23:03:39.409149 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9581 23:03:39.416052 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9582 23:03:39.419067 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9583 23:03:39.425716 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9584 23:03:39.428841 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9585 23:03:39.432273 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9586 23:03:39.439157 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9587 23:03:39.442273 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9588 23:03:39.448833 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9589 23:03:39.452219 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9590 23:03:39.458840 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9591 23:03:39.462087 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9592 23:03:39.468758 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9593 23:03:39.472082 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9594 23:03:39.478732 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9595 23:03:39.481901 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9596 23:03:39.485372 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9597 23:03:39.492300 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9598 23:03:39.495251 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9599 23:03:39.501947 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9600 23:03:39.505307 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9601 23:03:39.512095 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9602 23:03:39.515227 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9603 23:03:39.522010 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9604 23:03:39.525285 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9605 23:03:39.531949 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9606 23:03:39.535092 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9607 23:03:39.541825 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9608 23:03:39.544948 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9609 23:03:39.551521 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9610 23:03:39.554950 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9611 23:03:39.561573 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9612 23:03:39.564750 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9613 23:03:39.571781 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9614 23:03:39.574914 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9615 23:03:39.581554 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9616 23:03:39.584857 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9617 23:03:39.591441 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9618 23:03:39.591542 INFO: [APUAPC] vio 0
9619 23:03:39.598355 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9620 23:03:39.601993 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9621 23:03:39.605506 INFO: [APUAPC] D0_APC_0: 0x400510
9622 23:03:39.608566 INFO: [APUAPC] D0_APC_1: 0x0
9623 23:03:39.611789 INFO: [APUAPC] D0_APC_2: 0x1540
9624 23:03:39.615042 INFO: [APUAPC] D0_APC_3: 0x0
9625 23:03:39.618189 INFO: [APUAPC] D1_APC_0: 0xffffffff
9626 23:03:39.621533 INFO: [APUAPC] D1_APC_1: 0xffffffff
9627 23:03:39.624936 INFO: [APUAPC] D1_APC_2: 0x3fffff
9628 23:03:39.628199 INFO: [APUAPC] D1_APC_3: 0x0
9629 23:03:39.631553 INFO: [APUAPC] D2_APC_0: 0xffffffff
9630 23:03:39.634867 INFO: [APUAPC] D2_APC_1: 0xffffffff
9631 23:03:39.638334 INFO: [APUAPC] D2_APC_2: 0x3fffff
9632 23:03:39.641891 INFO: [APUAPC] D2_APC_3: 0x0
9633 23:03:39.644882 INFO: [APUAPC] D3_APC_0: 0xffffffff
9634 23:03:39.648137 INFO: [APUAPC] D3_APC_1: 0xffffffff
9635 23:03:39.651585 INFO: [APUAPC] D3_APC_2: 0x3fffff
9636 23:03:39.654813 INFO: [APUAPC] D3_APC_3: 0x0
9637 23:03:39.658093 INFO: [APUAPC] D4_APC_0: 0xffffffff
9638 23:03:39.661543 INFO: [APUAPC] D4_APC_1: 0xffffffff
9639 23:03:39.664862 INFO: [APUAPC] D4_APC_2: 0x3fffff
9640 23:03:39.664931 INFO: [APUAPC] D4_APC_3: 0x0
9641 23:03:39.668308 INFO: [APUAPC] D5_APC_0: 0xffffffff
9642 23:03:39.671368 INFO: [APUAPC] D5_APC_1: 0xffffffff
9643 23:03:39.674710 INFO: [APUAPC] D5_APC_2: 0x3fffff
9644 23:03:39.678513 INFO: [APUAPC] D5_APC_3: 0x0
9645 23:03:39.681603 INFO: [APUAPC] D6_APC_0: 0xffffffff
9646 23:03:39.684812 INFO: [APUAPC] D6_APC_1: 0xffffffff
9647 23:03:39.688028 INFO: [APUAPC] D6_APC_2: 0x3fffff
9648 23:03:39.691220 INFO: [APUAPC] D6_APC_3: 0x0
9649 23:03:39.694579 INFO: [APUAPC] D7_APC_0: 0xffffffff
9650 23:03:39.698049 INFO: [APUAPC] D7_APC_1: 0xffffffff
9651 23:03:39.701397 INFO: [APUAPC] D7_APC_2: 0x3fffff
9652 23:03:39.704705 INFO: [APUAPC] D7_APC_3: 0x0
9653 23:03:39.707837 INFO: [APUAPC] D8_APC_0: 0xffffffff
9654 23:03:39.711643 INFO: [APUAPC] D8_APC_1: 0xffffffff
9655 23:03:39.714833 INFO: [APUAPC] D8_APC_2: 0x3fffff
9656 23:03:39.718154 INFO: [APUAPC] D8_APC_3: 0x0
9657 23:03:39.721444 INFO: [APUAPC] D9_APC_0: 0xffffffff
9658 23:03:39.724514 INFO: [APUAPC] D9_APC_1: 0xffffffff
9659 23:03:39.727896 INFO: [APUAPC] D9_APC_2: 0x3fffff
9660 23:03:39.731043 INFO: [APUAPC] D9_APC_3: 0x0
9661 23:03:39.734615 INFO: [APUAPC] D10_APC_0: 0xffffffff
9662 23:03:39.737931 INFO: [APUAPC] D10_APC_1: 0xffffffff
9663 23:03:39.740933 INFO: [APUAPC] D10_APC_2: 0x3fffff
9664 23:03:39.744414 INFO: [APUAPC] D10_APC_3: 0x0
9665 23:03:39.747554 INFO: [APUAPC] D11_APC_0: 0xffffffff
9666 23:03:39.751184 INFO: [APUAPC] D11_APC_1: 0xffffffff
9667 23:03:39.754452 INFO: [APUAPC] D11_APC_2: 0x3fffff
9668 23:03:39.757563 INFO: [APUAPC] D11_APC_3: 0x0
9669 23:03:39.760926 INFO: [APUAPC] D12_APC_0: 0xffffffff
9670 23:03:39.764238 INFO: [APUAPC] D12_APC_1: 0xffffffff
9671 23:03:39.767549 INFO: [APUAPC] D12_APC_2: 0x3fffff
9672 23:03:39.770806 INFO: [APUAPC] D12_APC_3: 0x0
9673 23:03:39.774263 INFO: [APUAPC] D13_APC_0: 0xffffffff
9674 23:03:39.777262 INFO: [APUAPC] D13_APC_1: 0xffffffff
9675 23:03:39.780799 INFO: [APUAPC] D13_APC_2: 0x3fffff
9676 23:03:39.784007 INFO: [APUAPC] D13_APC_3: 0x0
9677 23:03:39.787157 INFO: [APUAPC] D14_APC_0: 0xffffffff
9678 23:03:39.790442 INFO: [APUAPC] D14_APC_1: 0xffffffff
9679 23:03:39.793781 INFO: [APUAPC] D14_APC_2: 0x3fffff
9680 23:03:39.797141 INFO: [APUAPC] D14_APC_3: 0x0
9681 23:03:39.800461 INFO: [APUAPC] D15_APC_0: 0xffffffff
9682 23:03:39.803701 INFO: [APUAPC] D15_APC_1: 0xffffffff
9683 23:03:39.807234 INFO: [APUAPC] D15_APC_2: 0x3fffff
9684 23:03:39.810262 INFO: [APUAPC] D15_APC_3: 0x0
9685 23:03:39.813646 INFO: [APUAPC] APC_CON: 0x4
9686 23:03:39.817112 INFO: [NOCDAPC] D0_APC_0: 0x0
9687 23:03:39.820268 INFO: [NOCDAPC] D0_APC_1: 0x0
9688 23:03:39.823750 INFO: [NOCDAPC] D1_APC_0: 0x0
9689 23:03:39.827105 INFO: [NOCDAPC] D1_APC_1: 0xfff
9690 23:03:39.830138 INFO: [NOCDAPC] D2_APC_0: 0x0
9691 23:03:39.833331 INFO: [NOCDAPC] D2_APC_1: 0xfff
9692 23:03:39.833399 INFO: [NOCDAPC] D3_APC_0: 0x0
9693 23:03:39.836840 INFO: [NOCDAPC] D3_APC_1: 0xfff
9694 23:03:39.840025 INFO: [NOCDAPC] D4_APC_0: 0x0
9695 23:03:39.843389 INFO: [NOCDAPC] D4_APC_1: 0xfff
9696 23:03:39.846736 INFO: [NOCDAPC] D5_APC_0: 0x0
9697 23:03:39.850005 INFO: [NOCDAPC] D5_APC_1: 0xfff
9698 23:03:39.853304 INFO: [NOCDAPC] D6_APC_0: 0x0
9699 23:03:39.856539 INFO: [NOCDAPC] D6_APC_1: 0xfff
9700 23:03:39.859782 INFO: [NOCDAPC] D7_APC_0: 0x0
9701 23:03:39.863062 INFO: [NOCDAPC] D7_APC_1: 0xfff
9702 23:03:39.866555 INFO: [NOCDAPC] D8_APC_0: 0x0
9703 23:03:39.866626 INFO: [NOCDAPC] D8_APC_1: 0xfff
9704 23:03:39.869778 INFO: [NOCDAPC] D9_APC_0: 0x0
9705 23:03:39.873446 INFO: [NOCDAPC] D9_APC_1: 0xfff
9706 23:03:39.876802 INFO: [NOCDAPC] D10_APC_0: 0x0
9707 23:03:39.879835 INFO: [NOCDAPC] D10_APC_1: 0xfff
9708 23:03:39.883321 INFO: [NOCDAPC] D11_APC_0: 0x0
9709 23:03:39.886439 INFO: [NOCDAPC] D11_APC_1: 0xfff
9710 23:03:39.889765 INFO: [NOCDAPC] D12_APC_0: 0x0
9711 23:03:39.892987 INFO: [NOCDAPC] D12_APC_1: 0xfff
9712 23:03:39.896498 INFO: [NOCDAPC] D13_APC_0: 0x0
9713 23:03:39.899616 INFO: [NOCDAPC] D13_APC_1: 0xfff
9714 23:03:39.902775 INFO: [NOCDAPC] D14_APC_0: 0x0
9715 23:03:39.906284 INFO: [NOCDAPC] D14_APC_1: 0xfff
9716 23:03:39.909735 INFO: [NOCDAPC] D15_APC_0: 0x0
9717 23:03:39.912928 INFO: [NOCDAPC] D15_APC_1: 0xfff
9718 23:03:39.913004 INFO: [NOCDAPC] APC_CON: 0x4
9719 23:03:39.916121 INFO: [APUAPC] set_apusys_apc done
9720 23:03:39.919748 INFO: [DEVAPC] devapc_init done
9721 23:03:39.926219 INFO: GICv3 without legacy support detected.
9722 23:03:39.929466 INFO: ARM GICv3 driver initialized in EL3
9723 23:03:39.932691 INFO: Maximum SPI INTID supported: 639
9724 23:03:39.935917 INFO: BL31: Initializing runtime services
9725 23:03:39.942555 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9726 23:03:39.945900 INFO: SPM: enable CPC mode
9727 23:03:39.949355 INFO: mcdi ready for mcusys-off-idle and system suspend
9728 23:03:39.955957 INFO: BL31: Preparing for EL3 exit to normal world
9729 23:03:39.959065 INFO: Entry point address = 0x80000000
9730 23:03:39.959165 INFO: SPSR = 0x8
9731 23:03:39.966694
9732 23:03:39.966777
9733 23:03:39.966841
9734 23:03:39.970106 Starting depthcharge on Spherion...
9735 23:03:39.970195
9736 23:03:39.970265 Wipe memory regions:
9737 23:03:39.970326
9738 23:03:39.971137 end: 2.2.3 depthcharge-start (duration 00:00:28) [common]
9739 23:03:39.971270 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
9740 23:03:39.971379 Setting prompt string to ['asurada:']
9741 23:03:39.971491 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
9742 23:03:39.973128 [0x00000040000000, 0x00000054600000)
9743 23:03:40.095079
9744 23:03:40.095193 [0x00000054660000, 0x00000080000000)
9745 23:03:40.355910
9746 23:03:40.356034 [0x000000821a7280, 0x000000ffe64000)
9747 23:03:41.100521
9748 23:03:41.100680 [0x00000100000000, 0x00000140000000)
9749 23:03:41.481754
9750 23:03:41.484684 Initializing XHCI USB controller at 0x11200000.
9751 23:03:42.522676
9752 23:03:42.525915 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9753 23:03:42.526023
9754 23:03:42.526114
9755 23:03:42.526210
9756 23:03:42.526528 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9758 23:03:42.626874 asurada: tftpboot 192.168.201.1 12154375/tftp-deploy-4cahwfen/kernel/image.itb 12154375/tftp-deploy-4cahwfen/kernel/cmdline
9759 23:03:42.627006 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9760 23:03:42.627094 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:24)
9761 23:03:42.631241 tftpboot 192.168.201.1 12154375/tftp-deploy-4cahwfen/kernel/image.itp-deploy-4cahwfen/kernel/cmdline
9762 23:03:42.631321
9763 23:03:42.631386 Waiting for link
9764 23:03:42.791625
9765 23:03:42.791745 R8152: Initializing
9766 23:03:42.791813
9767 23:03:42.794791 Version 9 (ocp_data = 6010)
9768 23:03:42.794891
9769 23:03:42.798056 R8152: Done initializing
9770 23:03:42.798128
9771 23:03:42.798189 Adding net device
9772 23:03:44.799727
9773 23:03:44.799872 done.
9774 23:03:44.799941
9775 23:03:44.800002 MAC: 00:e0:4c:68:03:bd
9776 23:03:44.800061
9777 23:03:44.802956 Sending DHCP discover... done.
9778 23:03:44.803038
9779 23:03:55.022930 Waiting for reply... R8152: Bulk read error 0xffffffbf
9780 23:03:55.023619
9781 23:03:55.026119 Receive failed.
9782 23:03:55.026822
9783 23:03:55.027441 done.
9784 23:03:55.027906
9785 23:03:55.029358 Sending DHCP request... done.
9786 23:03:55.029926
9787 23:03:55.036597 Waiting for reply... done.
9788 23:03:55.037014
9789 23:03:55.037346 My ip is 192.168.201.16
9790 23:03:55.037655
9791 23:03:55.040124 The DHCP server ip is 192.168.201.1
9792 23:03:55.040581
9793 23:03:55.046783 TFTP server IP predefined by user: 192.168.201.1
9794 23:03:55.047202
9795 23:03:55.053391 Bootfile predefined by user: 12154375/tftp-deploy-4cahwfen/kernel/image.itb
9796 23:03:55.053882
9797 23:03:55.056185 Sending tftp read request... done.
9798 23:03:55.056777
9799 23:03:55.062583 Waiting for the transfer...
9800 23:03:55.063158
9801 23:03:55.407416 00000000 ################################################################
9802 23:03:55.408120
9803 23:03:55.747957 00080000 ################################################################
9804 23:03:55.748097
9805 23:03:56.015878 00100000 ################################################################
9806 23:03:56.016004
9807 23:03:56.270846 00180000 ################################################################
9808 23:03:56.270977
9809 23:03:56.567277 00200000 ################################################################
9810 23:03:56.567418
9811 23:03:56.864766 00280000 ################################################################
9812 23:03:56.864896
9813 23:03:57.162411 00300000 ################################################################
9814 23:03:57.162549
9815 23:03:57.465351 00380000 ################################################################
9816 23:03:57.465496
9817 23:03:57.732706 00400000 ################################################################
9818 23:03:57.732835
9819 23:03:57.995458 00480000 ################################################################
9820 23:03:57.995608
9821 23:03:58.292212 00500000 ################################################################
9822 23:03:58.292365
9823 23:03:58.575405 00580000 ################################################################
9824 23:03:58.575895
9825 23:03:58.851403 00600000 ################################################################
9826 23:03:58.851534
9827 23:03:59.127728 00680000 ################################################################
9828 23:03:59.127857
9829 23:03:59.396222 00700000 ################################################################
9830 23:03:59.396379
9831 23:03:59.682388 00780000 ################################################################
9832 23:03:59.682542
9833 23:03:59.976319 00800000 ################################################################
9834 23:03:59.976449
9835 23:04:00.244682 00880000 ################################################################
9836 23:04:00.244836
9837 23:04:00.531399 00900000 ################################################################
9838 23:04:00.531555
9839 23:04:00.817387 00980000 ################################################################
9840 23:04:00.817522
9841 23:04:01.105504 00a00000 ################################################################
9842 23:04:01.105634
9843 23:04:01.376837 00a80000 ################################################################
9844 23:04:01.376965
9845 23:04:01.652282 00b00000 ################################################################
9846 23:04:01.652408
9847 23:04:01.940124 00b80000 ################################################################
9848 23:04:01.940267
9849 23:04:02.236258 00c00000 ################################################################
9850 23:04:02.236448
9851 23:04:02.532632 00c80000 ################################################################
9852 23:04:02.532764
9853 23:04:02.829837 00d00000 ################################################################
9854 23:04:02.829969
9855 23:04:03.122785 00d80000 ################################################################
9856 23:04:03.122924
9857 23:04:03.387496 00e00000 ################################################################
9858 23:04:03.387639
9859 23:04:03.669090 00e80000 ################################################################
9860 23:04:03.669221
9861 23:04:03.922175 00f00000 ################################################################
9862 23:04:03.922306
9863 23:04:04.208874 00f80000 ################################################################
9864 23:04:04.209010
9865 23:04:04.488928 01000000 ################################################################
9866 23:04:04.489061
9867 23:04:04.786264 01080000 ################################################################
9868 23:04:04.786397
9869 23:04:05.074123 01100000 ################################################################
9870 23:04:05.074263
9871 23:04:05.340961 01180000 ################################################################
9872 23:04:05.341098
9873 23:04:05.638440 01200000 ################################################################
9874 23:04:05.638583
9875 23:04:05.933166 01280000 ################################################################
9876 23:04:05.933297
9877 23:04:06.229206 01300000 ################################################################
9878 23:04:06.229347
9879 23:04:06.531915 01380000 ################################################################
9880 23:04:06.532051
9881 23:04:06.828236 01400000 ################################################################
9882 23:04:06.828363
9883 23:04:07.105248 01480000 ################################################################
9884 23:04:07.105384
9885 23:04:07.392424 01500000 ################################################################
9886 23:04:07.392620
9887 23:04:07.655757 01580000 ################################################################
9888 23:04:07.655890
9889 23:04:07.925797 01600000 ################################################################
9890 23:04:07.925931
9891 23:04:08.222339 01680000 ################################################################
9892 23:04:08.222470
9893 23:04:08.497413 01700000 ################################################################
9894 23:04:08.497546
9895 23:04:08.795086 01780000 ################################################################
9896 23:04:08.795223
9897 23:04:09.065760 01800000 ################################################################
9898 23:04:09.065891
9899 23:04:09.347716 01880000 ################################################################
9900 23:04:09.347846
9901 23:04:09.635785 01900000 ################################################################
9902 23:04:09.635919
9903 23:04:09.932700 01980000 ################################################################
9904 23:04:09.932835
9905 23:04:10.227761 01a00000 ################################################################
9906 23:04:10.227893
9907 23:04:10.509060 01a80000 ################################################################
9908 23:04:10.509190
9909 23:04:10.773984 01b00000 ################################################################
9910 23:04:10.774133
9911 23:04:11.056835 01b80000 ################################################################
9912 23:04:11.056969
9913 23:04:11.330259 01c00000 ################################################################
9914 23:04:11.330391
9915 23:04:11.616953 01c80000 ################################################################
9916 23:04:11.617086
9917 23:04:11.907326 01d00000 ################################################################
9918 23:04:11.907461
9919 23:04:12.199734 01d80000 ################################################################
9920 23:04:12.199867
9921 23:04:12.494065 01e00000 ################################################################
9922 23:04:12.494201
9923 23:04:12.785602 01e80000 ################################################################
9924 23:04:12.785738
9925 23:04:13.066828 01f00000 ################################################################
9926 23:04:13.066984
9927 23:04:13.352169 01f80000 ################################################################
9928 23:04:13.352302
9929 23:04:13.633862 02000000 ################################################################
9930 23:04:13.633993
9931 23:04:13.922783 02080000 ################################################################
9932 23:04:13.923006
9933 23:04:14.220135 02100000 ################################################################
9934 23:04:14.220291
9935 23:04:14.504256 02180000 ################################################################
9936 23:04:14.504407
9937 23:04:14.778796 02200000 ################################################################
9938 23:04:14.778949
9939 23:04:15.065311 02280000 ################################################################
9940 23:04:15.065442
9941 23:04:15.353033 02300000 ################################################################
9942 23:04:15.353163
9943 23:04:15.615267 02380000 ################################################################
9944 23:04:15.615422
9945 23:04:15.891284 02400000 ################################################################
9946 23:04:15.891414
9947 23:04:16.162259 02480000 ################################################################
9948 23:04:16.162482
9949 23:04:16.437013 02500000 ################################################################
9950 23:04:16.437167
9951 23:04:16.713330 02580000 ################################################################
9952 23:04:16.713484
9953 23:04:17.008425 02600000 ################################################################
9954 23:04:17.008620
9955 23:04:17.289774 02680000 ################################################################
9956 23:04:17.289920
9957 23:04:17.588264 02700000 ################################################################
9958 23:04:17.588438
9959 23:04:17.896729 02780000 ################################################################
9960 23:04:17.896867
9961 23:04:18.195282 02800000 ################################################################
9962 23:04:18.195421
9963 23:04:18.492981 02880000 ################################################################
9964 23:04:18.493148
9965 23:04:18.787405 02900000 ################################################################
9966 23:04:18.787558
9967 23:04:19.090749 02980000 ################################################################
9968 23:04:19.090932
9969 23:04:19.369734 02a00000 ################################################################
9970 23:04:19.369900
9971 23:04:19.639359 02a80000 ################################################################
9972 23:04:19.639525
9973 23:04:19.915009 02b00000 ################################################################
9974 23:04:19.915141
9975 23:04:20.191327 02b80000 ################################################################
9976 23:04:20.191454
9977 23:04:20.480751 02c00000 ################################################################
9978 23:04:20.480881
9979 23:04:20.741781 02c80000 ################################################################
9980 23:04:20.741942
9981 23:04:21.009586 02d00000 ################################################################
9982 23:04:21.009712
9983 23:04:21.276318 02d80000 ################################################################
9984 23:04:21.276472
9985 23:04:21.534324 02e00000 ################################################################
9986 23:04:21.534477
9987 23:04:21.810884 02e80000 ################################################################
9988 23:04:21.811040
9989 23:04:22.077822 02f00000 ################################################################
9990 23:04:22.077993
9991 23:04:22.352008 02f80000 ################################################################
9992 23:04:22.352182
9993 23:04:22.421314 03000000 ################# done.
9994 23:04:22.421455
9995 23:04:22.424783 The bootfile was 50468078 bytes long.
9996 23:04:22.424861
9997 23:04:22.428285 Sending tftp read request... done.
9998 23:04:22.428388
9999 23:04:22.428481 Waiting for the transfer...
10000 23:04:22.428610
10001 23:04:22.431142 00000000 # done.
10002 23:04:22.431269
10003 23:04:22.437928 Command line loaded dynamically from TFTP file: 12154375/tftp-deploy-4cahwfen/kernel/cmdline
10004 23:04:22.438030
10005 23:04:22.450862 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10006 23:04:22.450942
10007 23:04:22.454434 Loading FIT.
10008 23:04:22.454510
10009 23:04:22.457916 Image ramdisk-1 has 39374781 bytes.
10010 23:04:22.457994
10011 23:04:22.458055 Image fdt-1 has 47278 bytes.
10012 23:04:22.458113
10013 23:04:22.460855 Image kernel-1 has 11043984 bytes.
10014 23:04:22.460928
10015 23:04:22.470584 Compat preference: google,spherion-rev7-sku1 google,spherion-rev7 google,spherion-sku1 google,spherion
10016 23:04:22.470662
10017 23:04:22.487391 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion (match) mediatek,mt8192
10018 23:04:22.487498
10019 23:04:22.493972 Choosing best match conf-1 for compat google,spherion.
10020 23:04:22.497600
10021 23:04:22.502076 Connected to device vid:did:rid of 1ae0:0028:00
10022 23:04:22.509534
10023 23:04:22.512207 tpm_get_response: command 0x17b, return code 0x0
10024 23:04:22.512304
10025 23:04:22.515575 ec_init: CrosEC protocol v3 supported (256, 248)
10026 23:04:22.520812
10027 23:04:22.524225 tpm_cleanup: add release locality here.
10028 23:04:22.524323
10029 23:04:22.524418 Shutting down all USB controllers.
10030 23:04:22.527666
10031 23:04:22.527737 Removing current net device
10032 23:04:22.527798
10033 23:04:22.534097 Exiting depthcharge with code 4 at timestamp: 70794803
10034 23:04:22.534195
10035 23:04:22.537374 LZMA decompressing kernel-1 to 0x821a6718
10036 23:04:22.537450
10037 23:04:22.540441 LZMA decompressing kernel-1 to 0x40000000
10038 23:04:23.933906
10039 23:04:23.934524 jumping to kernel
10040 23:04:23.937410 end: 2.2.4 bootloader-commands (duration 00:00:44) [common]
10041 23:04:23.937897 start: 2.2.5 auto-login-action (timeout 00:03:42) [common]
10042 23:04:23.938268 Setting prompt string to ['Linux version [0-9]']
10043 23:04:23.938605 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10044 23:04:23.938953 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10045 23:04:23.984966
10046 23:04:23.988165 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10047 23:04:23.992032 start: 2.2.5.1 login-action (timeout 00:03:42) [common]
10048 23:04:23.992559 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10049 23:04:23.992931 Setting prompt string to []
10050 23:04:23.993330 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10051 23:04:23.993687 Using line separator: #'\n'#
10052 23:04:23.993999 No login prompt set.
10053 23:04:23.994306 Parsing kernel messages
10054 23:04:23.994672 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10055 23:04:23.995189 [login-action] Waiting for messages, (timeout 00:03:42)
10056 23:04:24.011139 [ 0.000000] Linux version 6.1.64-cip10 (KernelCI@build-j31357-arm64-gcc-10-defconfig-arm64-chromebook-69txj) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Dec 1 22:47:09 UTC 2023
10057 23:04:24.014629 [ 0.000000] random: crng init done
10058 23:04:24.021264 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10059 23:04:24.024291 [ 0.000000] efi: UEFI not found.
10060 23:04:24.031189 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10061 23:04:24.037609 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10062 23:04:24.047322 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10063 23:04:24.057975 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10064 23:04:24.063527 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10065 23:04:24.070110 [ 0.000000] printk: bootconsole [mtk8250] enabled
10066 23:04:24.077086 [ 0.000000] NUMA: No NUMA configuration found
10067 23:04:24.083450 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10068 23:04:24.086501 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d4a00-0x13f7d6fff]
10069 23:04:24.090544 [ 0.000000] Zone ranges:
10070 23:04:24.096453 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10071 23:04:24.099972 [ 0.000000] DMA32 empty
10072 23:04:24.106536 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10073 23:04:24.109799 [ 0.000000] Movable zone start for each node
10074 23:04:24.113100 [ 0.000000] Early memory node ranges
10075 23:04:24.119776 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10076 23:04:24.126380 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10077 23:04:24.133102 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10078 23:04:24.139432 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10079 23:04:24.145871 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10080 23:04:24.152399 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10081 23:04:24.183305 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10082 23:04:24.189880 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10083 23:04:24.196628 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10084 23:04:24.199776 [ 0.000000] psci: probing for conduit method from DT.
10085 23:04:24.206456 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10086 23:04:24.209836 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10087 23:04:24.216462 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10088 23:04:24.219863 [ 0.000000] psci: SMC Calling Convention v1.2
10089 23:04:24.226324 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10090 23:04:24.229662 [ 0.000000] Detected VIPT I-cache on CPU0
10091 23:04:24.236309 [ 0.000000] CPU features: detected: GIC system register CPU interface
10092 23:04:24.242964 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10093 23:04:24.249324 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10094 23:04:24.256008 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10095 23:04:24.262415 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10096 23:04:24.272368 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10097 23:04:24.275688 [ 0.000000] alternatives: applying boot alternatives
10098 23:04:24.282189 [ 0.000000] Fallback order for Node 0: 0
10099 23:04:24.289052 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10100 23:04:24.292197 [ 0.000000] Policy zone: Normal
10101 23:04:24.305670 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10102 23:04:24.315325 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10103 23:04:24.325397 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10104 23:04:24.335211 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10105 23:04:24.342016 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10106 23:04:24.345547 <6>[ 0.000000] software IO TLB: area num 8.
10107 23:04:24.401511 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10108 23:04:24.481555 <6>[ 0.000000] Memory: 3816692K/4191232K available (17984K kernel code, 4116K rwdata, 17316K rodata, 8448K init, 615K bss, 341772K reserved, 32768K cma-reserved)
10109 23:04:24.488464 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10110 23:04:24.494974 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10111 23:04:24.498597 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10112 23:04:24.504755 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10113 23:04:24.511664 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10114 23:04:24.514701 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10115 23:04:24.524687 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10116 23:04:24.531240 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10117 23:04:24.537859 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10118 23:04:24.544369 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10119 23:04:24.547825 <6>[ 0.000000] GICv3: 608 SPIs implemented
10120 23:04:24.551131 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10121 23:04:24.557619 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10122 23:04:24.561071 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10123 23:04:24.567678 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10124 23:04:24.580765 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10125 23:04:24.594109 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10126 23:04:24.600574 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10127 23:04:24.608337 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10128 23:04:24.621337 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10129 23:04:24.628000 <6>[ 0.000001] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10130 23:04:24.634889 <6>[ 0.009232] Console: colour dummy device 80x25
10131 23:04:24.645036 <6>[ 0.013959] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10132 23:04:24.651543 <6>[ 0.024400] pid_max: default: 32768 minimum: 301
10133 23:04:24.654759 <6>[ 0.029271] LSM: Security Framework initializing
10134 23:04:24.661374 <6>[ 0.034183] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10135 23:04:24.670892 <6>[ 0.041790] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10136 23:04:24.677869 <6>[ 0.051075] cblist_init_generic: Setting adjustable number of callback queues.
10137 23:04:24.684632 <6>[ 0.058518] cblist_init_generic: Setting shift to 3 and lim to 1.
10138 23:04:24.694175 <6>[ 0.064857] cblist_init_generic: Setting adjustable number of callback queues.
10139 23:04:24.697742 <6>[ 0.072283] cblist_init_generic: Setting shift to 3 and lim to 1.
10140 23:04:24.704398 <6>[ 0.078683] rcu: Hierarchical SRCU implementation.
10141 23:04:24.710595 <6>[ 0.083730] rcu: Max phase no-delay instances is 1000.
10142 23:04:24.717330 <6>[ 0.090761] EFI services will not be available.
10143 23:04:24.720790 <6>[ 0.095723] smp: Bringing up secondary CPUs ...
10144 23:04:24.728726 <6>[ 0.100772] Detected VIPT I-cache on CPU1
10145 23:04:24.735263 <6>[ 0.100842] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10146 23:04:24.741573 <6>[ 0.100874] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10147 23:04:24.745399 <6>[ 0.101202] Detected VIPT I-cache on CPU2
10148 23:04:24.754741 <6>[ 0.101249] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10149 23:04:24.761521 <6>[ 0.101264] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10150 23:04:24.764955 <6>[ 0.101520] Detected VIPT I-cache on CPU3
10151 23:04:24.771545 <6>[ 0.101565] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10152 23:04:24.778245 <6>[ 0.101579] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10153 23:04:24.784567 <6>[ 0.101882] CPU features: detected: Spectre-v4
10154 23:04:24.788051 <6>[ 0.101888] CPU features: detected: Spectre-BHB
10155 23:04:24.791186 <6>[ 0.101892] Detected PIPT I-cache on CPU4
10156 23:04:24.797706 <6>[ 0.101947] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10157 23:04:24.807936 <6>[ 0.101964] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10158 23:04:24.810856 <6>[ 0.102255] Detected PIPT I-cache on CPU5
10159 23:04:24.817531 <6>[ 0.102316] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10160 23:04:24.824088 <6>[ 0.102333] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10161 23:04:24.827472 <6>[ 0.102612] Detected PIPT I-cache on CPU6
10162 23:04:24.837181 <6>[ 0.102674] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10163 23:04:24.843870 <6>[ 0.102691] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10164 23:04:24.847891 <6>[ 0.102991] Detected PIPT I-cache on CPU7
10165 23:04:24.854336 <6>[ 0.103055] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10166 23:04:24.861087 <6>[ 0.103072] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10167 23:04:24.864394 <6>[ 0.103119] smp: Brought up 1 node, 8 CPUs
10168 23:04:24.870416 <6>[ 0.244588] SMP: Total of 8 processors activated.
10169 23:04:24.876896 <6>[ 0.249509] CPU features: detected: 32-bit EL0 Support
10170 23:04:24.883876 <6>[ 0.254906] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10171 23:04:24.890608 <6>[ 0.263706] CPU features: detected: Common not Private translations
10172 23:04:24.897365 <6>[ 0.270181] CPU features: detected: CRC32 instructions
10173 23:04:24.903524 <6>[ 0.275533] CPU features: detected: RCpc load-acquire (LDAPR)
10174 23:04:24.906694 <6>[ 0.281493] CPU features: detected: LSE atomic instructions
10175 23:04:24.913404 <6>[ 0.287274] CPU features: detected: Privileged Access Never
10176 23:04:24.919972 <6>[ 0.293054] CPU features: detected: RAS Extension Support
10177 23:04:24.926565 <6>[ 0.298663] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10178 23:04:24.930098 <6>[ 0.305929] CPU: All CPU(s) started at EL2
10179 23:04:24.936576 <6>[ 0.310272] alternatives: applying system-wide alternatives
10180 23:04:24.945495 <6>[ 0.320157] devtmpfs: initialized
10181 23:04:24.960784 <6>[ 0.328483] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10182 23:04:24.967369 <6>[ 0.338448] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10183 23:04:24.973986 <6>[ 0.346683] pinctrl core: initialized pinctrl subsystem
10184 23:04:24.976918 <6>[ 0.353329] DMI not present or invalid.
10185 23:04:24.983700 <6>[ 0.357732] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10186 23:04:24.994021 <6>[ 0.364596] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
10187 23:04:25.000267 <6>[ 0.372048] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10188 23:04:25.010120 <6>[ 0.380138] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10189 23:04:25.013478 <6>[ 0.388298] audit: initializing netlink subsys (disabled)
10190 23:04:25.023320 <5>[ 0.393994] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10191 23:04:25.029882 <6>[ 0.394688] thermal_sys: Registered thermal governor 'step_wise'
10192 23:04:25.036566 <6>[ 0.401963] thermal_sys: Registered thermal governor 'power_allocator'
10193 23:04:25.039783 <6>[ 0.408220] cpuidle: using governor menu
10194 23:04:25.046568 <6>[ 0.419188] NET: Registered PF_QIPCRTR protocol family
10195 23:04:25.053201 <6>[ 0.424661] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10196 23:04:25.056420 <6>[ 0.431765] ASID allocator initialised with 32768 entries
10197 23:04:25.063695 <6>[ 0.438309] Serial: AMBA PL011 UART driver
10198 23:04:25.072503 <4>[ 0.447051] Trying to register duplicate clock ID: 134
10199 23:04:25.128855 <6>[ 0.506454] KASLR enabled
10200 23:04:25.143100 <6>[ 0.514231] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10201 23:04:25.150018 <6>[ 0.521247] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10202 23:04:25.156443 <6>[ 0.527736] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10203 23:04:25.162676 <6>[ 0.534744] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10204 23:04:25.169372 <6>[ 0.541233] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10205 23:04:25.176054 <6>[ 0.548242] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10206 23:04:25.183039 <6>[ 0.554732] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10207 23:04:25.189216 <6>[ 0.561740] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10208 23:04:25.192811 <6>[ 0.569166] ACPI: Interpreter disabled.
10209 23:04:25.201341 <6>[ 0.575565] iommu: Default domain type: Translated
10210 23:04:25.207953 <6>[ 0.580680] iommu: DMA domain TLB invalidation policy: strict mode
10211 23:04:25.211581 <5>[ 0.587341] SCSI subsystem initialized
10212 23:04:25.217760 <6>[ 0.591505] usbcore: registered new interface driver usbfs
10213 23:04:25.224470 <6>[ 0.597242] usbcore: registered new interface driver hub
10214 23:04:25.227665 <6>[ 0.602796] usbcore: registered new device driver usb
10215 23:04:25.234814 <6>[ 0.608896] pps_core: LinuxPPS API ver. 1 registered
10216 23:04:25.244267 <6>[ 0.614090] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10217 23:04:25.247903 <6>[ 0.623441] PTP clock support registered
10218 23:04:25.250789 <6>[ 0.627685] EDAC MC: Ver: 3.0.0
10219 23:04:25.258419 <6>[ 0.632828] FPGA manager framework
10220 23:04:25.265226 <6>[ 0.636510] Advanced Linux Sound Architecture Driver Initialized.
10221 23:04:25.268293 <6>[ 0.643290] vgaarb: loaded
10222 23:04:25.274858 <6>[ 0.646454] clocksource: Switched to clocksource arch_sys_counter
10223 23:04:25.278205 <5>[ 0.652897] VFS: Disk quotas dquot_6.6.0
10224 23:04:25.284747 <6>[ 0.657084] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10225 23:04:25.288405 <6>[ 0.664277] pnp: PnP ACPI: disabled
10226 23:04:25.296838 <6>[ 0.671029] NET: Registered PF_INET protocol family
10227 23:04:25.303106 <6>[ 0.676428] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
10228 23:04:25.315382 <6>[ 0.686468] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
10229 23:04:25.325177 <6>[ 0.695253] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10230 23:04:25.331923 <6>[ 0.703222] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
10231 23:04:25.338437 <6>[ 0.711626] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
10232 23:04:25.349136 <6>[ 0.720264] TCP: Hash tables configured (established 32768 bind 32768)
10233 23:04:25.355545 <6>[ 0.727125] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
10234 23:04:25.362133 <6>[ 0.734148] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
10235 23:04:25.368598 <6>[ 0.741670] NET: Registered PF_UNIX/PF_LOCAL protocol family
10236 23:04:25.375689 <6>[ 0.747747] RPC: Registered named UNIX socket transport module.
10237 23:04:25.378413 <6>[ 0.753898] RPC: Registered udp transport module.
10238 23:04:25.385164 <6>[ 0.758833] RPC: Registered tcp transport module.
10239 23:04:25.392016 <6>[ 0.763767] RPC: Registered tcp NFSv4.1 backchannel transport module.
10240 23:04:25.395299 <6>[ 0.770433] PCI: CLS 0 bytes, default 64
10241 23:04:25.398657 <6>[ 0.774777] Unpacking initramfs...
10242 23:04:25.423396 <6>[ 0.794630] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10243 23:04:25.433081 <6>[ 0.803287] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10244 23:04:25.436731 <6>[ 0.812128] kvm [1]: IPA Size Limit: 40 bits
10245 23:04:25.443173 <6>[ 0.816653] kvm [1]: GICv3: no GICV resource entry
10246 23:04:25.446478 <6>[ 0.821676] kvm [1]: disabling GICv2 emulation
10247 23:04:25.453112 <6>[ 0.826365] kvm [1]: GIC system register CPU interface enabled
10248 23:04:25.456414 <6>[ 0.832526] kvm [1]: vgic interrupt IRQ18
10249 23:04:25.462980 <6>[ 0.836879] kvm [1]: VHE mode initialized successfully
10250 23:04:25.469702 <5>[ 0.843178] Initialise system trusted keyrings
10251 23:04:25.476372 <6>[ 0.847950] workingset: timestamp_bits=42 max_order=20 bucket_order=0
10252 23:04:25.483255 <6>[ 0.857914] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10253 23:04:25.490025 <5>[ 0.864299] NFS: Registering the id_resolver key type
10254 23:04:25.493200 <5>[ 0.869604] Key type id_resolver registered
10255 23:04:25.499682 <5>[ 0.874021] Key type id_legacy registered
10256 23:04:25.506693 <6>[ 0.878302] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10257 23:04:25.512882 <6>[ 0.885226] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10258 23:04:25.519578 <6>[ 0.892927] 9p: Installing v9fs 9p2000 file system support
10259 23:04:25.556621 <5>[ 0.930965] Key type asymmetric registered
10260 23:04:25.559625 <5>[ 0.935298] Asymmetric key parser 'x509' registered
10261 23:04:25.569828 <6>[ 0.940438] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10262 23:04:25.573182 <6>[ 0.948056] io scheduler mq-deadline registered
10263 23:04:25.576596 <6>[ 0.952819] io scheduler kyber registered
10264 23:04:25.595090 <6>[ 0.969679] EINJ: ACPI disabled.
10265 23:04:25.627131 <4>[ 0.995038] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10266 23:04:25.636837 <4>[ 1.005656] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10267 23:04:25.651487 <6>[ 1.026135] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10268 23:04:25.659574 <6>[ 1.034050] printk: console [ttyS0] disabled
10269 23:04:25.687430 <6>[ 1.058712] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10270 23:04:25.694412 <6>[ 1.068188] printk: console [ttyS0] enabled
10271 23:04:25.697451 <6>[ 1.068188] printk: console [ttyS0] enabled
10272 23:04:25.703907 <6>[ 1.077084] printk: bootconsole [mtk8250] disabled
10273 23:04:25.707127 <6>[ 1.077084] printk: bootconsole [mtk8250] disabled
10274 23:04:25.713690 <6>[ 1.088108] SuperH (H)SCI(F) driver initialized
10275 23:04:25.717018 <6>[ 1.093377] msm_serial: driver initialized
10276 23:04:25.730909 <6>[ 1.102254] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10277 23:04:25.740963 <6>[ 1.110804] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10278 23:04:25.747492 <6>[ 1.119352] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10279 23:04:25.757679 <6>[ 1.127981] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10280 23:04:25.767464 <6>[ 1.136690] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10281 23:04:25.774280 <6>[ 1.145405] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10282 23:04:25.783916 <6>[ 1.153946] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10283 23:04:25.790821 <6>[ 1.162748] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10284 23:04:25.801024 <6>[ 1.171292] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10285 23:04:25.812409 <6>[ 1.187051] loop: module loaded
10286 23:04:25.819039 <6>[ 1.193001] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10287 23:04:25.841828 <4>[ 1.216253] mtk-pmic-keys: Failed to locate of_node [id: -1]
10288 23:04:25.848642 <6>[ 1.223083] megasas: 07.719.03.00-rc1
10289 23:04:25.858235 <6>[ 1.232629] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10290 23:04:25.867483 <6>[ 1.241825] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10291 23:04:25.884157 <6>[ 1.258262] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10292 23:04:25.938831 <6>[ 1.307218] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10293 23:04:27.032472 <6>[ 2.407455] Freeing initrd memory: 38448K
10294 23:04:27.042997 <6>[ 2.417490] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10295 23:04:27.053574 <6>[ 2.428368] tun: Universal TUN/TAP device driver, 1.6
10296 23:04:27.057012 <6>[ 2.434422] thunder_xcv, ver 1.0
10297 23:04:27.060162 <6>[ 2.437926] thunder_bgx, ver 1.0
10298 23:04:27.063328 <6>[ 2.441421] nicpf, ver 1.0
10299 23:04:27.074582 <6>[ 2.445423] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10300 23:04:27.077731 <6>[ 2.452899] hns3: Copyright (c) 2017 Huawei Corporation.
10301 23:04:27.084198 <6>[ 2.458484] hclge is initializing
10302 23:04:27.087512 <6>[ 2.462056] e1000: Intel(R) PRO/1000 Network Driver
10303 23:04:27.094471 <6>[ 2.467186] e1000: Copyright (c) 1999-2006 Intel Corporation.
10304 23:04:27.097251 <6>[ 2.473198] e1000e: Intel(R) PRO/1000 Network Driver
10305 23:04:27.104080 <6>[ 2.478414] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10306 23:04:27.110642 <6>[ 2.484600] igb: Intel(R) Gigabit Ethernet Network Driver
10307 23:04:27.117356 <6>[ 2.490250] igb: Copyright (c) 2007-2014 Intel Corporation.
10308 23:04:27.123924 <6>[ 2.496086] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10309 23:04:27.130443 <6>[ 2.502602] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10310 23:04:27.133554 <6>[ 2.509062] sky2: driver version 1.30
10311 23:04:27.140037 <6>[ 2.514041] VFIO - User Level meta-driver version: 0.3
10312 23:04:27.147555 <6>[ 2.522234] usbcore: registered new interface driver usb-storage
10313 23:04:27.154264 <6>[ 2.528681] usbcore: registered new device driver onboard-usb-hub
10314 23:04:27.163386 <6>[ 2.537837] mt6397-rtc mt6359-rtc: registered as rtc0
10315 23:04:27.172895 <6>[ 2.543301] mt6397-rtc mt6359-rtc: setting system clock to 2023-12-01T23:04:27 UTC (1701471867)
10316 23:04:27.176626 <6>[ 2.552861] i2c_dev: i2c /dev entries driver
10317 23:04:27.193193 <6>[ 2.564548] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10318 23:04:27.214117 <6>[ 2.588525] cpu cpu0: EM: created perf domain
10319 23:04:27.217308 <6>[ 2.593430] cpu cpu4: EM: created perf domain
10320 23:04:27.224318 <6>[ 2.598960] sdhci: Secure Digital Host Controller Interface driver
10321 23:04:27.230853 <6>[ 2.605389] sdhci: Copyright(c) Pierre Ossman
10322 23:04:27.237549 <6>[ 2.610304] Synopsys Designware Multimedia Card Interface Driver
10323 23:04:27.243990 <6>[ 2.616895] sdhci-pltfm: SDHCI platform and OF driver helper
10324 23:04:27.247260 <6>[ 2.616983] mmc0: CQHCI version 5.10
10325 23:04:27.254339 <6>[ 2.627242] ledtrig-cpu: registered to indicate activity on CPUs
10326 23:04:27.260442 <6>[ 2.634303] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10327 23:04:27.266998 <6>[ 2.641328] usbcore: registered new interface driver usbhid
10328 23:04:27.270525 <6>[ 2.647149] usbhid: USB HID core driver
10329 23:04:27.277505 <6>[ 2.651348] spi_master spi0: will run message pump with realtime priority
10330 23:04:27.328587 <6>[ 2.696246] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10331 23:04:27.347380 <6>[ 2.711716] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10332 23:04:27.350777 <6>[ 2.725295] mmc0: Command Queue Engine enabled
10333 23:04:27.357675 <6>[ 2.726530] cros-ec-spi spi0.0: Chrome EC device registered
10334 23:04:27.363911 <6>[ 2.730030] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10335 23:04:27.367372 <6>[ 2.743223] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10336 23:04:27.377725 <6>[ 2.749013] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10337 23:04:27.384407 <6>[ 2.752346] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10338 23:04:27.390683 <6>[ 2.759339] NET: Registered PF_PACKET protocol family
10339 23:04:27.394240 <6>[ 2.765580] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10340 23:04:27.400808 <6>[ 2.769631] 9pnet: Installing 9P2000 support
10341 23:04:27.404459 <6>[ 2.775401] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10342 23:04:27.410705 <5>[ 2.779324] Key type dns_resolver registered
10343 23:04:27.417156 <6>[ 2.785144] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10344 23:04:27.420572 <6>[ 2.789530] registered taskstats version 1
10345 23:04:27.424170 <5>[ 2.799931] Loading compiled-in X.509 certificates
10346 23:04:27.453384 <4>[ 2.821043] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10347 23:04:27.463134 <4>[ 2.831734] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10348 23:04:27.469462 <3>[ 2.842259] debugfs: File 'uA_load' in directory '/' already present!
10349 23:04:27.476030 <3>[ 2.848958] debugfs: File 'min_uV' in directory '/' already present!
10350 23:04:27.482600 <3>[ 2.855625] debugfs: File 'max_uV' in directory '/' already present!
10351 23:04:27.489230 <3>[ 2.862239] debugfs: File 'constraint_flags' in directory '/' already present!
10352 23:04:27.500382 <3>[ 2.871739] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10353 23:04:27.508823 <6>[ 2.883510] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10354 23:04:27.515481 <6>[ 2.890195] xhci-mtk 11200000.usb: xHCI Host Controller
10355 23:04:27.522196 <6>[ 2.895703] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10356 23:04:27.532113 <6>[ 2.903552] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10357 23:04:27.538775 <6>[ 2.912974] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10358 23:04:27.545185 <6>[ 2.919043] xhci-mtk 11200000.usb: xHCI Host Controller
10359 23:04:27.552122 <6>[ 2.924520] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10360 23:04:27.558396 <6>[ 2.932165] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10361 23:04:27.565157 <6>[ 2.939864] hub 1-0:1.0: USB hub found
10362 23:04:27.568250 <6>[ 2.943873] hub 1-0:1.0: 1 port detected
10363 23:04:27.575282 <6>[ 2.948114] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10364 23:04:27.581777 <6>[ 2.956630] hub 2-0:1.0: USB hub found
10365 23:04:27.584870 <6>[ 2.960634] hub 2-0:1.0: 1 port detected
10366 23:04:27.593387 <6>[ 2.968130] mtk-msdc 11f70000.mmc: Got CD GPIO
10367 23:04:27.604479 <6>[ 2.975963] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10368 23:04:27.611051 <6>[ 2.983985] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10369 23:04:27.621159 <4>[ 2.991895] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10370 23:04:27.631030 <6>[ 3.001415] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10371 23:04:27.637595 <6>[ 3.009491] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10372 23:04:27.644229 <6>[ 3.017584] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10373 23:04:27.654033 <6>[ 3.025513] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10374 23:04:27.660348 <6>[ 3.033329] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10375 23:04:27.670606 <6>[ 3.041146] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10376 23:04:27.680588 <6>[ 3.051606] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10377 23:04:27.686976 <6>[ 3.059989] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10378 23:04:27.696949 <6>[ 3.068330] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10379 23:04:27.703629 <6>[ 3.076669] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10380 23:04:27.713312 <6>[ 3.085006] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10381 23:04:27.723279 <6>[ 3.093344] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10382 23:04:27.729994 <6>[ 3.101682] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10383 23:04:27.739984 <6>[ 3.110020] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10384 23:04:27.746544 <6>[ 3.118358] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10385 23:04:27.756454 <6>[ 3.126700] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10386 23:04:27.763112 <6>[ 3.135039] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10387 23:04:27.772952 <6>[ 3.143377] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10388 23:04:27.779735 <6>[ 3.151715] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10389 23:04:27.789676 <6>[ 3.160054] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10390 23:04:27.796071 <6>[ 3.168392] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10391 23:04:27.802438 <6>[ 3.177137] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10392 23:04:27.809351 <6>[ 3.184253] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10393 23:04:27.816369 <6>[ 3.190975] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10394 23:04:27.826631 <6>[ 3.197700] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10395 23:04:27.832852 <6>[ 3.204605] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10396 23:04:27.839177 <6>[ 3.211462] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10397 23:04:27.849641 <6>[ 3.220590] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10398 23:04:27.859019 <6>[ 3.229711] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10399 23:04:27.869109 <6>[ 3.239005] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10400 23:04:27.879138 <6>[ 3.248492] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10401 23:04:27.889142 <6>[ 3.257961] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10402 23:04:27.895761 <6>[ 3.267081] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10403 23:04:27.905597 <6>[ 3.276548] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10404 23:04:27.915258 <6>[ 3.285666] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10405 23:04:27.925215 <6>[ 3.294958] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10406 23:04:27.935478 <6>[ 3.305117] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10407 23:04:27.945028 <6>[ 3.316673] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10408 23:04:27.975978 <6>[ 3.346985] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10409 23:04:28.003639 <6>[ 3.378135] hub 2-1:1.0: USB hub found
10410 23:04:28.006714 <6>[ 3.382599] hub 2-1:1.0: 3 ports detected
10411 23:04:28.015208 <6>[ 3.389843] hub 2-1:1.0: USB hub found
10412 23:04:28.018475 <6>[ 3.394177] hub 2-1:1.0: 3 ports detected
10413 23:04:28.127455 <6>[ 3.498724] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10414 23:04:28.282369 <6>[ 3.656927] hub 1-1:1.0: USB hub found
10415 23:04:28.285360 <6>[ 3.661390] hub 1-1:1.0: 4 ports detected
10416 23:04:28.294893 <6>[ 3.669430] hub 1-1:1.0: USB hub found
10417 23:04:28.297931 <6>[ 3.673793] hub 1-1:1.0: 4 ports detected
10418 23:04:28.367548 <6>[ 3.738971] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10419 23:04:28.619001 <6>[ 3.990793] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10420 23:04:28.751801 <6>[ 4.126645] hub 1-1.4:1.0: USB hub found
10421 23:04:28.754775 <6>[ 4.131316] hub 1-1.4:1.0: 2 ports detected
10422 23:04:28.764288 <6>[ 4.139352] hub 1-1.4:1.0: USB hub found
10423 23:04:28.767592 <6>[ 4.144013] hub 1-1.4:1.0: 2 ports detected
10424 23:04:29.063002 <6>[ 4.434752] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10425 23:04:29.254814 <6>[ 4.626579] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10426 23:04:40.220133 <6>[ 15.599723] ALSA device list:
10427 23:04:40.226392 <6>[ 15.603009] No soundcards found.
10428 23:04:40.234455 <6>[ 15.610833] Freeing unused kernel memory: 8448K
10429 23:04:40.237912 <6>[ 15.615812] Run /init as init process
10430 23:04:40.284105 <6>[ 15.660442] NET: Registered PF_INET6 protocol family
10431 23:04:40.287422 <6>[ 15.666434] Segment Routing with IPv6
10432 23:04:40.293822 <6>[ 15.670375] In-situ OAM (IOAM) with IPv6
10433 23:04:40.327519 <30>[ 15.684099] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10434 23:04:40.330941 <30>[ 15.707945] systemd[1]: Detected architecture arm64.
10435 23:04:40.331392
10436 23:04:40.337384 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10437 23:04:40.337917
10438 23:04:40.350514 <30>[ 15.726778] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10439 23:04:40.475901 <30>[ 15.848946] systemd[1]: Queued start job for default target Graphical Interface.
10440 23:04:40.523319 <30>[ 15.899504] systemd[1]: Created slice system-getty.slice.
10441 23:04:40.529988 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10442 23:04:40.547075 <30>[ 15.923378] systemd[1]: Created slice system-modprobe.slice.
10443 23:04:40.553827 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10444 23:04:40.571342 <30>[ 15.947588] systemd[1]: Created slice system-serial\x2dgetty.slice.
10445 23:04:40.581495 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10446 23:04:40.595881 <30>[ 15.972128] systemd[1]: Created slice User and Session Slice.
10447 23:04:40.602321 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10448 23:04:40.622694 <30>[ 15.995500] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10449 23:04:40.632741 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10450 23:04:40.650453 <30>[ 16.023497] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10451 23:04:40.657199 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10452 23:04:40.681842 <30>[ 16.051220] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10453 23:04:40.688369 <30>[ 16.063475] systemd[1]: Reached target Local Encrypted Volumes.
10454 23:04:40.695025 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10455 23:04:40.711042 <30>[ 16.087277] systemd[1]: Reached target Paths.
10456 23:04:40.714323 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10457 23:04:40.730541 <30>[ 16.106746] systemd[1]: Reached target Remote File Systems.
10458 23:04:40.737260 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10459 23:04:40.750229 <30>[ 16.126718] systemd[1]: Reached target Slices.
10460 23:04:40.754046 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10461 23:04:40.770327 <30>[ 16.146747] systemd[1]: Reached target Swap.
10462 23:04:40.773738 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10463 23:04:40.794364 <30>[ 16.167202] systemd[1]: Listening on initctl Compatibility Named Pipe.
10464 23:04:40.800601 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10465 23:04:40.815922 <30>[ 16.192186] systemd[1]: Listening on Journal Audit Socket.
10466 23:04:40.822501 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10467 23:04:40.839751 <30>[ 16.215874] systemd[1]: Listening on Journal Socket (/dev/log).
10468 23:04:40.846305 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10469 23:04:40.863536 <30>[ 16.239918] systemd[1]: Listening on Journal Socket.
10470 23:04:40.870294 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10471 23:04:40.886532 <30>[ 16.259412] systemd[1]: Listening on Network Service Netlink Socket.
10472 23:04:40.893017 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10473 23:04:40.907828 <30>[ 16.283946] systemd[1]: Listening on udev Control Socket.
10474 23:04:40.914008 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10475 23:04:40.931693 <30>[ 16.307751] systemd[1]: Listening on udev Kernel Socket.
10476 23:04:40.938110 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10477 23:04:40.990554 <30>[ 16.366983] systemd[1]: Mounting Huge Pages File System...
10478 23:04:40.997104 Mounting [0;1;39mHuge Pages File System[0m...
10479 23:04:41.013856 <30>[ 16.390258] systemd[1]: Mounting POSIX Message Queue File System...
10480 23:04:41.021083 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10481 23:04:41.042416 <30>[ 16.418548] systemd[1]: Mounting Kernel Debug File System...
10482 23:04:41.048899 Mounting [0;1;39mKernel Debug File System[0m...
10483 23:04:41.066089 <30>[ 16.439138] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10484 23:04:41.114330 <30>[ 16.487243] systemd[1]: Starting Create list of static device nodes for the current kernel...
10485 23:04:41.120832 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10486 23:04:41.142881 <30>[ 16.518935] systemd[1]: Starting Load Kernel Module configfs...
10487 23:04:41.149586 Starting [0;1;39mLoad Kernel Module configfs[0m...
10488 23:04:41.166076 <30>[ 16.542526] systemd[1]: Starting Load Kernel Module drm...
10489 23:04:41.172646 Starting [0;1;39mLoad Kernel Module drm[0m...
10490 23:04:41.189971 <30>[ 16.562855] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10491 23:04:41.227008 <30>[ 16.603160] systemd[1]: Starting Journal Service...
10492 23:04:41.230092 Starting [0;1;39mJournal Service[0m...
10493 23:04:41.249148 <30>[ 16.625487] systemd[1]: Starting Load Kernel Modules...
10494 23:04:41.255771 Starting [0;1;39mLoad Kernel Modules[0m...
10495 23:04:41.282886 <30>[ 16.655788] systemd[1]: Starting Remount Root and Kernel File Systems...
10496 23:04:41.289477 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10497 23:04:41.305066 <30>[ 16.681468] systemd[1]: Starting Coldplug All udev Devices...
10498 23:04:41.311566 Starting [0;1;39mColdplug All udev Devices[0m...
10499 23:04:41.330644 <30>[ 16.706817] systemd[1]: Started Journal Service.
10500 23:04:41.337009 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10501 23:04:41.352014 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10502 23:04:41.367819 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10503 23:04:41.383457 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10504 23:04:41.407604 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10505 23:04:41.428901 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10506 23:04:41.449640 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10507 23:04:41.472574 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10508 23:04:41.496574 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10509 23:04:41.514716 See 'systemctl status systemd-remount-fs.service' for details.
10510 23:04:41.555591 Mounting [0;1;39mKernel Configuration File System[0m...
10511 23:04:41.576958 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10512 23:04:41.590023 <46>[ 16.963070] systemd-journald[174]: Received client request to flush runtime journal.
10513 23:04:41.598111 Starting [0;1;39mLoad/Save Random Seed[0m...
10514 23:04:41.618425 Starting [0;1;39mApply Kernel Variables[0m...
10515 23:04:41.639534 Starting [0;1;39mCreate System Users[0m...
10516 23:04:41.659667 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10517 23:04:41.675501 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10518 23:04:41.696053 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10519 23:04:41.712314 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10520 23:04:41.728555 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10521 23:04:41.744106 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10522 23:04:41.779234 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10523 23:04:41.799523 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10524 23:04:41.810801 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10525 23:04:41.826355 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10526 23:04:41.875311 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10527 23:04:41.906506 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10528 23:04:41.929563 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10529 23:04:41.949940 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10530 23:04:42.019358 Starting [0;1;39mNetwork Service[0m...
10531 23:04:42.044742 Starting [0;1;39mNetwork Time Synchronization[0m...
10532 23:04:42.051261 <6>[ 17.426119] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10533 23:04:42.063369 <6>[ 17.436558] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10534 23:04:42.070024 Startin<6>[ 17.444991] remoteproc remoteproc0: scp is available
10535 23:04:42.079999 g [0;1;39mUpdat<6>[ 17.445164] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10536 23:04:42.086527 <6>[ 17.452236] remoteproc remoteproc0: powering up scp
10537 23:04:42.096715 e UTMP about Sys<6>[ 17.462329] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10538 23:04:42.106368 tem Boot/Shutdow<6>[ 17.469048] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10539 23:04:42.106923 n[0m...
10540 23:04:42.112846 <6>[ 17.487237] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10541 23:04:42.123569 <6>[ 17.499731] mc: Linux media interface: v0.10
10542 23:04:42.146745 <6>[ 17.523338] usbcore: registered new interface driver r8152
10543 23:04:42.153831 <6>[ 17.526619] videodev: Linux video capture interface: v2.00
10544 23:04:42.166797 [[0;32m OK [0m] Finished [0;1;39mUpdate UTM<3>[ 17.539055] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10545 23:04:42.176719 P about System B<3>[ 17.547819] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10546 23:04:42.183695 oot/Shutdown[0m<4>[ 17.550896] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10547 23:04:42.184205 .
10548 23:04:42.193145 <3>[ 17.556995] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10549 23:04:42.203176 [[0;32m OK [<4>[ 17.575674] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10550 23:04:42.206428 0m] Started [0;1;39mNetwork Service[0m.
10551 23:04:42.218424 <3>[ 17.591384] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10552 23:04:42.224877 <3>[ 17.599602] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10553 23:04:42.235259 <3>[ 17.608363] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10554 23:04:42.245070 [[0;32m OK [<3>[ 17.617135] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10555 23:04:42.255234 0m] Found device<6>[ 17.618779] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10556 23:04:42.264913 [0;1;39m/dev/t<6>[ 17.626496] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10557 23:04:42.265439 tyS0[0m.
10558 23:04:42.271636 <6>[ 17.626512] remoteproc remoteproc0: remote processor scp is now up
10559 23:04:42.278267 <3>[ 17.626572] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10560 23:04:42.288094 <6>[ 17.661025] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10561 23:04:42.294841 <3>[ 17.662470] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10562 23:04:42.301227 <6>[ 17.666746] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10563 23:04:42.307929 <6>[ 17.667984] pci_bus 0000:00: root bus resource [bus 00-ff]
10564 23:04:42.318028 <6>[ 17.669128] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10565 23:04:42.324403 <6>[ 17.677794] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10566 23:04:42.334798 <6>[ 17.678576] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10567 23:04:42.341546 <6>[ 17.683139] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10568 23:04:42.351567 <6>[ 17.683149] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10569 23:04:42.358094 <6>[ 17.683234] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10570 23:04:42.364803 <3>[ 17.684930] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10571 23:04:42.375813 <3>[ 17.684942] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10572 23:04:42.382252 <3>[ 17.684946] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10573 23:04:42.388589 <3>[ 17.693037] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10574 23:04:42.398705 <6>[ 17.699015] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10575 23:04:42.405243 <4>[ 17.701766] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10576 23:04:42.415220 <4>[ 17.701774] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10577 23:04:42.421738 <4>[ 17.704406] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10578 23:04:42.428623 <4>[ 17.704406] Fallback method does not support PEC.
10579 23:04:42.435091 <3>[ 17.706660] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10580 23:04:42.445131 <6>[ 17.712861] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10581 23:04:42.452112 <6>[ 17.715806] pci 0000:00:00.0: supports D1 D2
10582 23:04:42.458424 <3>[ 17.719077] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10583 23:04:42.465433 <3>[ 17.722942] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10584 23:04:42.472886 <6>[ 17.732748] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10585 23:04:42.482663 <3>[ 17.739002] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10586 23:04:42.489174 <3>[ 17.739008] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10587 23:04:42.499055 <3>[ 17.740974] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10588 23:04:42.505540 <3>[ 17.756129] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10589 23:04:42.515672 <6>[ 17.772225] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10590 23:04:42.519048 <6>[ 17.781830] usbcore: registered new interface driver cdc_ether
10591 23:04:42.529561 <6>[ 17.790186] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10592 23:04:42.542487 <6>[ 17.792923] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10593 23:04:42.546286 <6>[ 17.797960] usbcore: registered new interface driver uvcvideo
10594 23:04:42.552355 <6>[ 17.814352] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10595 23:04:42.559086 <6>[ 17.826985] r8152 2-1.3:1.0 eth0: v1.12.13
10596 23:04:42.565650 <6>[ 17.827292] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10597 23:04:42.572128 <6>[ 17.841665] usbcore: registered new interface driver r8153_ecm
10598 23:04:42.578809 <6>[ 17.848655] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10599 23:04:42.585466 <6>[ 17.848679] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10600 23:04:42.592008 <6>[ 17.848887] pci 0000:01:00.0: supports D1 D2
10601 23:04:42.598451 <3>[ 17.849975] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10602 23:04:42.602345 <6>[ 17.855990] Bluetooth: Core ver 2.22
10603 23:04:42.608767 <6>[ 17.863650] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10604 23:04:42.618360 <6>[ 17.894556] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10605 23:04:42.622064 <6>[ 17.896217] NET: Registered PF_BLUETOOTH protocol family
10606 23:04:42.631786 <6>[ 17.901891] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10607 23:04:42.638635 <6>[ 17.902365] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10608 23:04:42.644886 <3>[ 17.908765] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10609 23:04:42.651357 <6>[ 17.909971] Bluetooth: HCI device and connection manager initialized
10610 23:04:42.658257 <6>[ 17.909997] Bluetooth: HCI socket layer initialized
10611 23:04:42.664615 <6>[ 17.922861] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10612 23:04:42.671628 <6>[ 17.928764] Bluetooth: L2CAP socket layer initialized
10613 23:04:42.677994 <6>[ 17.936037] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10614 23:04:42.684622 <6>[ 17.939114] Bluetooth: SCO socket layer initialized
10615 23:04:42.691007 <6>[ 17.946655] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10616 23:04:42.700915 <6>[ 17.963880] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10617 23:04:42.707757 <6>[ 17.964731] r8152 2-1.3:1.0 enx00e04c6803bd: renamed from eth0
10618 23:04:42.714142 <6>[ 17.968054] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10619 23:04:42.724169 <6>[ 17.975374] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10620 23:04:42.727436 <6>[ 17.980942] pci 0000:00:00.0: PCI bridge to [bus 01]
10621 23:04:42.734082 <6>[ 18.004944] usbcore: registered new interface driver btusb
10622 23:04:42.743752 <4>[ 18.005596] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10623 23:04:42.750725 <3>[ 18.005603] Bluetooth: hci0: Failed to load firmware file (-2)
10624 23:04:42.757304 <3>[ 18.005605] Bluetooth: hci0: Failed to set up firmware (-2)
10625 23:04:42.767207 <4>[ 18.005608] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10626 23:04:42.773836 <6>[ 18.012157] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10627 23:04:42.780051 <6>[ 18.156190] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10628 23:04:42.787305 [[0;32m OK [<6>[ 18.163278] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10629 23:04:42.797604 0m] Started [0;<6>[ 18.170719] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10630 23:04:42.800932 1;39mNetwork Time Synchronization[0m.
10631 23:04:42.811397 <3>[ 18.183842] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10632 23:04:42.821355 <3>[ 18.184504] power_supply sbs-5-000b: driver failed to report `capacity_level' property: -6
10633 23:04:42.828014 <3>[ 18.200644] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10634 23:04:42.835409 <5>[ 18.202998] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10635 23:04:42.847060 <3>[ 18.219814] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10636 23:04:42.853270 <5>[ 18.229407] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10637 23:04:42.863268 <4>[ 18.236262] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10638 23:04:42.869917 <6>[ 18.245128] cfg80211: failed to load regulatory.db
10639 23:04:42.881043 <3>[ 18.253976] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10640 23:04:42.911640 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbac<3>[ 18.282529] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10641 23:04:42.912146 klight.slice[0m.
10642 23:04:42.921705 <6>[ 18.294996] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10643 23:04:42.928777 <6>[ 18.302496] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10644 23:04:42.931884 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10645 23:04:42.946273 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10646 23:04:42.952859 <6>[ 18.329235] mt7921e 0000:01:00.0: ASIC revision: 79610010
10647 23:04:42.962364 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10648 23:04:42.982022 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10649 23:04:43.033929 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10650 23:04:43.062516 <4>[ 18.432339] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10651 23:04:43.068939 Starting [0;1;39mNetwork Name Resolution[0m...
10652 23:04:43.088558 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10653 23:04:43.103250 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10654 23:04:43.122395 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10655 23:04:43.141560 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10656 23:04:43.154671 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10657 23:04:43.179163 <4>[ 18.548986] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10658 23:04:43.185733 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10659 23:04:43.198230 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10660 23:04:43.218442 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10661 23:04:43.274793 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10662 23:04:43.299590 <4>[ 18.670305] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10663 23:04:43.313561 Starting [0;1;39mUser Login Management[0m...
10664 23:04:43.334337 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10665 23:04:43.351007 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10666 23:04:43.367300 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10667 23:04:43.384809 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10668 23:04:43.401558 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10669 23:04:43.419247 <4>[ 18.789095] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10670 23:04:43.451393 Starting [0;1;39mPermit User Sessions[0m...
10671 23:04:43.473099 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10672 23:04:43.481632 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10673 23:04:43.492920 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10674 23:04:43.512084 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10675 23:04:43.529247 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10676 23:04:43.543048 <4>[ 18.912889] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10677 23:04:43.552414 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10678 23:04:43.571593 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10679 23:04:43.616240 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10680 23:04:43.664000 <4>[ 19.034135] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10681 23:04:43.670876 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10682 23:04:43.720194
10683 23:04:43.720677
10684 23:04:43.723554 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10685 23:04:43.723987
10686 23:04:43.726814 debian-bullseye-arm64 login: root (automatic login)
10687 23:04:43.727262
10688 23:04:43.727603
10689 23:04:43.754280 Linux debian-bullseye-arm64 6.1.64-cip10 #1 SMP PREEMPT Fri Dec 1 22:47:09 UTC 2023 aarch64
10690 23:04:43.754740
10691 23:04:43.760746 The programs included with the Debian GNU/Linux system are free software;
10692 23:04:43.767553 the exact distribution terms for each program are described in the
10693 23:04:43.770762 individual files in /usr/share/doc/*/copyright.
10694 23:04:43.771218
10695 23:04:43.783443 Debian GNU/Lin<4>[ 19.152833] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10696 23:04:43.786853 ux comes with ABSOLUTELY NO WARRANTY, to the extent
10697 23:04:43.790190 permitted by applicable law.
10698 23:04:43.790575 Matched prompt #10: / #
10700 23:04:43.790783 Setting prompt string to ['/ #']
10701 23:04:43.790875 end: 2.2.5.1 login-action (duration 00:00:20) [common]
10703 23:04:43.791076 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
10704 23:04:43.791163 start: 2.2.6 expect-shell-connection (timeout 00:03:22) [common]
10705 23:04:43.791241 Setting prompt string to ['/ #']
10706 23:04:43.791303 Forcing a shell prompt, looking for ['/ #']
10708 23:04:43.841503 / #
10709 23:04:43.841677 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10710 23:04:43.841759 Waiting using forced prompt support (timeout 00:02:30)
10711 23:04:43.846462
10712 23:04:43.846749 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10713 23:04:43.846844 start: 2.2.7 export-device-env (timeout 00:03:22) [common]
10714 23:04:43.846935 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10715 23:04:43.847021 end: 2.2 depthcharge-retry (duration 00:01:38) [common]
10716 23:04:43.847112 end: 2 depthcharge-action (duration 00:01:38) [common]
10717 23:04:43.847198 start: 3 lava-test-retry (timeout 00:08:00) [common]
10718 23:04:43.847284 start: 3.1 lava-test-shell (timeout 00:08:00) [common]
10719 23:04:43.847430 Using namespace: common
10721 23:04:43.947968 / # #
10722 23:04:43.948629 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10723 23:04:43.949202 <4>[ 19.272984] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10724 23:04:43.992928 #<6>[ 19.329658] IPv6: ADDRCONF(NETDEV_CHANGE): enx00e04c6803bd: link becomes ready
10725 23:04:43.993491
10726 23:04:43.993882 <6>[ 19.337739] r8152 2-1.3:1.0 enx00e04c6803bd: carrier on
10727 23:04:43.994562 Using /lava-12154375
10729 23:04:44.095787 / # export SHELL=/bin/sh
10730 23:04:44.096713 <4>[ 19.393070] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10731 23:04:44.102287 export SHELL=/bin/sh
10733 23:04:44.203896 / # . /lava-12154375/environment
10734 23:04:44.204741 <4>[ 19.512813] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10735 23:04:44.210162 . /lava-12154375/environment
10737 23:04:44.311715 / # /lava-12154375/bin/lava-test-runner /lava-12154375/0
10738 23:04:44.312244 Test shell timeout: 10s (minimum of the action and connection timeout)
10739 23:04:44.314193 <3>[ 19.626804] mt7921e 0000:01:00.0: hardware init failed
10740 23:04:44.317814 /lava-12154375/bin/lava-test-runner /lava-12154375/0
10741 23:04:44.364904 + export TESTRUN_ID=0_v4l2-compliance-mtk-vcodec-enc
10742 23:04:44.365779 + cd /lava-12154375/0/tests/0_v4l2-compliance-mtk-vcodec-enc
10743 23:04:44.366211 + cat uuid
10744 23:04:44.366587 + UUID=12154375_1.5.2.3.1
10745 23:04:44.366952 + set +x
10746 23:04:44.367470 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-mtk-vcodec-enc 12154375_1.5.2.3.1>
10747 23:04:44.367929 + /usr/bin/v4l2-parser.sh -d mtk-vcodec-enc
10748 23:04:44.368458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
10749 23:04:44.369252 Received signal: <STARTRUN> 0_v4l2-compliance-mtk-vcodec-enc 12154375_1.5.2.3.1
10750 23:04:44.369646 Starting test lava.0_v4l2-compliance-mtk-vcodec-enc (12154375_1.5.2.3.1)
10751 23:04:44.370069 Skipping test definition patterns.
10752 23:04:44.370592 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
10754 23:04:44.377219 device: /dev/vide<4>[ 19.749621] use of bytesused == 0 is deprecated and will be removed in the future,
10755 23:04:44.377653 o2
10756 23:04:44.380438 <4>[ 19.757597] use the actual size instead.
10757 23:04:44.395252 v4l2-compliance 1.25.0-1, 64 bits, 64-bit time_t
10758 23:04:44.404363 v4l2-compliance SHA: 16e70e28584c 2023-06-22 09:47:27
10759 23:04:44.411407
10760 23:04:44.425714 Compliance test for mtk-vcodec-enc device /dev/video2:
10761 23:04:44.433745
10762 23:04:44.448481 Driver Info:
10763 23:04:44.459383 Driver name : mtk-vcodec-enc
10764 23:04:44.476861 Card type : MT8192 video encoder
10765 23:04:44.490420 Bus info : platform:17020000.vcodec
10766 23:04:44.500722 Driver version : 6.1.64
10767 23:04:44.510143 Capabilities : 0x84204000
10768 23:04:44.525770 Video Memory-to-Memory Multiplanar
10769 23:04:44.537754 Streaming
10770 23:04:44.551619 Extended Pix Format
10771 23:04:44.565376 Device Capabilities
10772 23:04:44.578100 Device Caps : 0x04204000
10773 23:04:44.589931 Video Memory-to-Memory Multiplanar
10774 23:04:44.605586 Streaming
10775 23:04:44.616398 Extended Pix Format
10776 23:04:44.628290 Detected Stateful Encoder
10777 23:04:44.641251
10778 23:04:44.656133 Required ioctls:
10779 23:04:44.670838 <LAVA_SIGNAL_TESTSET START Required-ioctls>
10780 23:04:44.671260 test VIDIOC_QUERYCAP: OK
10781 23:04:44.671875 Received signal: <TESTSET> START Required-ioctls
10782 23:04:44.672240 Starting test_set Required-ioctls
10783 23:04:44.693456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
10784 23:04:44.694218 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
10786 23:04:44.697034 test invalid ioctls: OK
10787 23:04:44.720159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
10788 23:04:44.720884
10789 23:04:44.721638 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
10791 23:04:44.729401 Allow for multiple opens:
10792 23:04:44.740261 <LAVA_SIGNAL_TESTSET STOP>
10793 23:04:44.741036 Received signal: <TESTSET> STOP
10794 23:04:44.741431 Closing test_set Required-ioctls
10795 23:04:44.750940 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
10796 23:04:44.751746 Received signal: <TESTSET> START Allow-for-multiple-opens
10797 23:04:44.752192 Starting test_set Allow-for-multiple-opens
10798 23:04:44.753922 test second /dev/video2 open: OK
10799 23:04:44.776277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video2-open RESULT=pass>
10800 23:04:44.777073 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video2-open RESULT=pass
10802 23:04:44.779643 test VIDIOC_QUERYCAP: OK
10803 23:04:44.800778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
10804 23:04:44.801580 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
10806 23:04:44.803713 test VIDIOC_G/S_PRIORITY: OK
10807 23:04:44.824488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
10808 23:04:44.825433 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
10810 23:04:44.827622 test for unlimited opens: OK
10811 23:04:44.848278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
10812 23:04:44.848838
10813 23:04:44.849443 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
10815 23:04:44.859919 Debug ioctls:
10816 23:04:44.866244 <LAVA_SIGNAL_TESTSET STOP>
10817 23:04:44.867020 Received signal: <TESTSET> STOP
10818 23:04:44.867380 Closing test_set Allow-for-multiple-opens
10819 23:04:44.876203 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
10820 23:04:44.876933 Received signal: <TESTSET> START Debug-ioctls
10821 23:04:44.877310 Starting test_set Debug-ioctls
10822 23:04:44.879197 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
10823 23:04:44.903437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
10824 23:04:44.904187 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
10826 23:04:44.909999 test VIDIOC_LOG_STATUS: OK (Not Supported)
10827 23:04:44.926919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
10828 23:04:44.927389
10829 23:04:44.928025 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
10831 23:04:44.936347 Input ioctls:
10832 23:04:44.945151 <LAVA_SIGNAL_TESTSET STOP>
10833 23:04:44.945405 Received signal: <TESTSET> STOP
10834 23:04:44.945477 Closing test_set Debug-ioctls
10835 23:04:44.956315 <LAVA_SIGNAL_TESTSET START Input-ioctls>
10836 23:04:44.956562 Received signal: <TESTSET> START Input-ioctls
10837 23:04:44.956643 Starting test_set Input-ioctls
10838 23:04:44.959653 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
10839 23:04:44.986100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
10840 23:04:44.986357 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
10842 23:04:44.989265 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
10843 23:04:45.009553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
10844 23:04:45.009812 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
10846 23:04:45.016127 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
10847 23:04:45.033365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
10848 23:04:45.033712 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
10850 23:04:45.039489 test VIDIOC_ENUMAUDIO: OK (Not Supported)
10851 23:04:45.056931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
10852 23:04:45.057194 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
10854 23:04:45.060531 test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
10855 23:04:45.082807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
10856 23:04:45.083151 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
10858 23:04:45.086112 test VIDIOC_G/S_AUDIO: OK (Not Supported)
10859 23:04:45.108826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
10860 23:04:45.109597 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
10862 23:04:45.112066 Inputs: 0 Audio Inputs: 0 Tuners: 0
10863 23:04:45.120692
10864 23:04:45.138120 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
10865 23:04:45.159406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
10866 23:04:45.160277 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
10868 23:04:45.165829 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
10869 23:04:45.184104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
10870 23:04:45.184932 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
10872 23:04:45.187358 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
10873 23:04:45.208819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
10874 23:04:45.209554 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
10876 23:04:45.215229 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
10877 23:04:45.235308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
10878 23:04:45.235570 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
10880 23:04:45.241663 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
10881 23:04:45.258549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
10882 23:04:45.258685
10883 23:04:45.258980 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
10885 23:04:45.275336 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
10886 23:04:45.302683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
10887 23:04:45.303401 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
10889 23:04:45.309657 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
10890 23:04:45.330748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
10891 23:04:45.331484 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
10893 23:04:45.333947 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
10894 23:04:45.356698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
10895 23:04:45.357512 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
10897 23:04:45.359983 test VIDIOC_G/S_EDID: OK (Not Supported)
10898 23:04:45.380293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
10899 23:04:45.380916
10900 23:04:45.381668 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
10902 23:04:45.387829 Control ioctls:
10903 23:04:45.394007 <LAVA_SIGNAL_TESTSET STOP>
10904 23:04:45.394801 Received signal: <TESTSET> STOP
10905 23:04:45.394997 Closing test_set Input-ioctls
10906 23:04:45.403285 <LAVA_SIGNAL_TESTSET START Control-ioctls>
10907 23:04:45.403540 Received signal: <TESTSET> START Control-ioctls
10908 23:04:45.403614 Starting test_set Control-ioctls
10909 23:04:45.406279 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
10910 23:04:45.437415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
10911 23:04:45.437909 test VIDIOC_QUERYCTRL: OK
10912 23:04:45.438556 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
10914 23:04:45.459142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
10915 23:04:45.459404 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
10917 23:04:45.462320 test VIDIOC_G/S_CTRL: OK
10918 23:04:45.487071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
10919 23:04:45.487336 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
10921 23:04:45.490418 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
10922 23:04:45.514468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
10923 23:04:45.514879 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
10925 23:04:45.524551 fail: ../utils/v4l2-compliance/v4l2-test-controls.cpp(1167): node->codec_mask & STATEFUL_ENCODER
10926 23:04:45.527276 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: FAIL
10927 23:04:45.555614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail>
10928 23:04:45.556330 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail
10930 23:04:45.558929 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
10931 23:04:45.580045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
10932 23:04:45.580300 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
10934 23:04:45.583538 Standard Controls: 16 Private Controls: 0
10935 23:04:45.591652
10936 23:04:45.601954 Format ioctls:
10937 23:04:45.607523 <LAVA_SIGNAL_TESTSET STOP>
10938 23:04:45.607825 Received signal: <TESTSET> STOP
10939 23:04:45.607932 Closing test_set Control-ioctls
10940 23:04:45.617126 <LAVA_SIGNAL_TESTSET START Format-ioctls>
10941 23:04:45.617378 Received signal: <TESTSET> START Format-ioctls
10942 23:04:45.617449 Starting test_set Format-ioctls
10943 23:04:45.620610 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
10944 23:04:45.648784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
10945 23:04:45.649076 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
10947 23:04:45.651977 test VIDIOC_G/S_PARM: OK
10948 23:04:45.669195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
10949 23:04:45.669576 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
10951 23:04:45.672407 test VIDIOC_G_FBUF: OK (Not Supported)
10952 23:04:45.699077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
10953 23:04:45.699363 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
10955 23:04:45.702298 test VIDIOC_G_FMT: OK
10956 23:04:45.723047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
10957 23:04:45.723412 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
10959 23:04:45.726162 test VIDIOC_TRY_FMT: OK
10960 23:04:45.748106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
10961 23:04:45.748850 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
10963 23:04:45.758003 fail: ../utils/v4l2-compliance/v4l2-test-formats.cpp(924): sel.r.width != fmt.g_width()
10964 23:04:45.761260 test VIDIOC_S_FMT: FAIL
10965 23:04:45.787129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail>
10966 23:04:45.787824 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail
10968 23:04:45.790424 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
10969 23:04:45.812463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
10970 23:04:45.813227 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
10972 23:04:45.815919 test Cropping: OK
10973 23:04:45.836374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
10974 23:04:45.837088 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
10976 23:04:45.839136 test Composing: OK (Not Supported)
10977 23:04:45.863477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
10978 23:04:45.864306 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
10980 23:04:45.866726 test Scaling: OK (Not Supported)
10981 23:04:45.889492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
10982 23:04:45.889937
10983 23:04:45.890584 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
10985 23:04:45.900752 Codec ioctls:
10986 23:04:45.908020 <LAVA_SIGNAL_TESTSET STOP>
10987 23:04:45.908274 Received signal: <TESTSET> STOP
10988 23:04:45.908362 Closing test_set Format-ioctls
10989 23:04:45.917044 <LAVA_SIGNAL_TESTSET START Codec-ioctls>
10990 23:04:45.917296 Received signal: <TESTSET> START Codec-ioctls
10991 23:04:45.917365 Starting test_set Codec-ioctls
10992 23:04:45.919958 test VIDIOC_(TRY_)ENCODER_CMD: OK
10993 23:04:45.940579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
10994 23:04:45.941306 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
10996 23:04:45.946778 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
10997 23:04:45.963941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
10998 23:04:45.964263 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11000 23:04:45.970106 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11001 23:04:45.988686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11002 23:04:45.988782
11003 23:04:45.989031 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11005 23:04:46.000395 Buffer ioctls:
11006 23:04:46.006511 <LAVA_SIGNAL_TESTSET STOP>
11007 23:04:46.006812 Received signal: <TESTSET> STOP
11008 23:04:46.006937 Closing test_set Codec-ioctls
11009 23:04:46.016602 <LAVA_SIGNAL_TESTSET START Buffer-ioctls>
11010 23:04:46.017074 Received signal: <TESTSET> START Buffer-ioctls
11011 23:04:46.017246 Starting test_set Buffer-ioctls
11012 23:04:46.020214 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11013 23:04:46.043685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11014 23:04:46.044199 test VIDIOC_EXPBUF: OK
11015 23:04:46.044895 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11017 23:04:46.065379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11018 23:04:46.066156 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11020 23:04:46.068458 test Requests: OK (Not Supported)
11021 23:04:46.088912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11022 23:04:46.089487
11023 23:04:46.090120 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11025 23:04:46.102918 Test input 0:
11026 23:04:46.112642
11027 23:04:46.126256 Streaming ioctls:
11028 23:04:46.132113 <LAVA_SIGNAL_TESTSET STOP>
11029 23:04:46.132879 Received signal: <TESTSET> STOP
11030 23:04:46.133269 Closing test_set Buffer-ioctls
11031 23:04:46.141472 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11032 23:04:46.142148 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11033 23:04:46.142503 Starting test_set Streaming-ioctls_Test-input-0
11034 23:04:46.144924 test read/write: OK (Not Supported)
11035 23:04:46.165587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11036 23:04:46.165837 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11038 23:04:46.172182 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2798): node->streamon(q.g_type())
11039 23:04:46.182198 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2845): testBlockingDQBuf(node, q)
11040 23:04:46.186520 test blocking wait: FAIL
11041 23:04:46.212305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=fail>
11042 23:04:46.212532 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=fail
11044 23:04:46.222412 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())
11045 23:04:46.225613 test MMAP (select): FAIL
11046 23:04:46.251099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11047 23:04:46.251378 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11049 23:04:46.257769 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())
11050 23:04:46.262764 test MMAP (epoll): FAIL
11051 23:04:46.286085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11052 23:04:46.286411 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11054 23:04:46.295891 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1602): ret && ret != ENOTTY (got 22)
11055 23:04:46.302613 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1733): setupUserPtr(node, q)
11056 23:04:46.310735 test USERPTR (select): FAIL
11057 23:04:46.337047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=fail>
11058 23:04:46.337374 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=fail
11060 23:04:46.340465 test DMABUF: Cannot test, specify --expbuf-device
11061 23:04:46.347670
11062 23:04:46.366649 Total for mtk-vcodec-enc device /dev/video2: 50, Succeeded: 44, Failed: 6, Warnings: 0
11063 23:04:46.374587 <LAVA_TEST_RUNNER EXIT>
11064 23:04:46.374849 ok: lava_test_shell seems to have completed
11065 23:04:46.374926 Marking unfinished test run as failed
11067 23:04:46.375798 Composing:
result: pass
set: Format-ioctls
Cropping:
result: pass
set: Format-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls
Scaling:
result: pass
set: Format-ioctls
USERPTR-select:
result: fail
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls
VIDIOC_G_FMT:
result: pass
set: Format-ioctls
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls
VIDIOC_S_FMT:
result: fail
set: Format-ioctls
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: fail
set: Control-ioctls
blocking-wait:
result: fail
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video2-open:
result: pass
set: Allow-for-multiple-opens
11068 23:04:46.375916 end: 3.1 lava-test-shell (duration 00:00:03) [common]
11069 23:04:46.376001 end: 3 lava-test-retry (duration 00:00:03) [common]
11070 23:04:46.376101 start: 4 finalize (timeout 00:07:58) [common]
11071 23:04:46.376229 start: 4.1 power-off (timeout 00:00:30) [common]
11072 23:04:46.376379 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=off'
11073 23:04:50.474047 >> Command sent successfully.
11074 23:04:50.476583 Returned 0 in 4 seconds
11075 23:04:50.576966 end: 4.1 power-off (duration 00:00:04) [common]
11077 23:04:50.577279 start: 4.2 read-feedback (timeout 00:07:54) [common]
11078 23:04:50.577547 Listened to connection for namespace 'common' for up to 1s
11079 23:04:51.578655 Finalising connection for namespace 'common'
11080 23:04:51.579270 Disconnecting from shell: Finalise
11081 23:04:51.579657 / #
11082 23:04:51.680316 end: 4.2 read-feedback (duration 00:00:01) [common]
11083 23:04:51.680494 end: 4 finalize (duration 00:00:05) [common]
11084 23:04:51.680688 Cleaning after the job
11085 23:04:51.680789 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12154375/tftp-deploy-4cahwfen/ramdisk
11086 23:04:51.686582 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12154375/tftp-deploy-4cahwfen/kernel
11087 23:04:51.695068 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12154375/tftp-deploy-4cahwfen/dtb
11088 23:04:51.695236 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12154375/tftp-deploy-4cahwfen/modules
11089 23:04:51.702753 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12154375
11090 23:04:51.771293 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12154375
11091 23:04:51.771453 Job finished correctly